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add child device node for qcs404. misc fixes. - mediatek : enable support for mt8183. misc rejig of cmdq driver. new client-reg dt property. - armada: use device-managed registration api -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEE6EwehDt/SOnwFyTyf9lkf8eYP5UFAl2CUw8ACgkQf9lkf8eY P5XWdQ/+JMGoG8nbTkFdvgnRXvxdtZLylOTotnEpYtIOQ6qAckkOc0rGih3qXXRq 5FUCynImnx0Pqjso8ny8xSqfGy2B1f87tg+GD2r38XjLPo+5gJMkd5aCZ4JtEKZQ ms+23pPXCLhh6bej6WW3fmuwk8T3USWfGGhRFQOHN9e152dThXt3vvLo40vy/GD5 xT2qChONXmyPrG1F3qJhGcHuiubBzZ2mxfEC294PyVwWKdaJ5StlBmSQpomJsJP3 v04SNI8P/gMtNhFfIVks9Hj1eu2PlO7p+4DpyhBDQii5Dzv+bSnJHIJch6DOYdou h1aezWGHdJ5IcJTZcKVq0a8wyCoOGFU6znQQKRDtIdpgoDfGVmIe2bheFB4ePXOQ XI9gsNGBrgS4uA5lJKJyJrAokXpTCiwA69c7UULRPKa0jbmVwbrJxxbLYL4k5euC Qi6r3qPxvJ+3kYzegqtzHRYx9s+3Bt0CkHG8hv/XtETzM2Jg7TXy9yEF6d53jFAx f0eU7PWdfM8TbQYGQ67BRYtSITaL8TgVafby5S1T9jLA5QnCAf4/TMCtJjxvCOVp hMBm9JCnQ2U9c8geGkcU51Oz78sdTByE+q0Rzw6C9jFQxECRiSC/a7tvI7Pkui4y w9UpCJNfypGHi+WT/UuCePi2JlnPRVCquKR2TEb8BZQKTEV4owk= =V6QY -----END PGP SIGNATURE----- Merge tag 'mailbox-v5.4' of git://git.linaro.org/landing-teams/working/fujitsu/integration Pull mailbox updates from Jassi Brar: - qcom: - enable support for ipq8074, sm1850 and sm7180 - add child device node for qcs404 - misc fixes - mediatek: - enable support for mt8183 - misc rejig of cmdq driver - new client-reg dt property - armada: - use device-managed registration api * tag 'mailbox-v5.4' of git://git.linaro.org/landing-teams/working/fujitsu/integration: mailbox: qcom-apcs: fix max_register value mailbox: qcom: Add support for IPQ8074 APCS dt-bindings: mailbox: qom: Add ipq8074 APPS compatible mailbox: qcom: Add support for Qualcomm SM8150 and SC7180 SoCs dt-bindings: mailbox: Add APSS shared for SM8150 and SC7180 SoCs mbox: qcom: replace integer with valid macro mbox: qcom: add APCS child device for QCS404 mailbox: mediatek: cmdq: clear the event in cmdq initial flow mailbox: mediatek: cmdq: support mt8183 gce function mailbox: mediatek: cmdq: move the CMDQ_IRQ_MASK into cmdq driver data dt-binding: gce: add binding for gce client reg property dt-binding: gce: add gce header file for mt8183 dt-binding: gce: remove thread-num property mailbox: armada-37xx-rwtm: Use device-managed registration API
130 lines
3.7 KiB
C
130 lines
3.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2018 MediaTek Inc.
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*
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*/
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#ifndef __MTK_CMDQ_H__
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#define __MTK_CMDQ_H__
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#include <linux/mailbox_client.h>
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#include <linux/mailbox/mtk-cmdq-mailbox.h>
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#include <linux/timer.h>
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#define CMDQ_NO_TIMEOUT 0xffffffffu
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struct cmdq_pkt;
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struct cmdq_client {
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spinlock_t lock;
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u32 pkt_cnt;
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struct mbox_client client;
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struct mbox_chan *chan;
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struct timer_list timer;
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u32 timeout_ms; /* in unit of microsecond */
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};
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/**
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* cmdq_mbox_create() - create CMDQ mailbox client and channel
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* @dev: device of CMDQ mailbox client
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* @index: index of CMDQ mailbox channel
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* @timeout: timeout of a pkt execution by GCE, in unit of microsecond, set
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* CMDQ_NO_TIMEOUT if a timer is not used.
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*
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* Return: CMDQ mailbox client pointer
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*/
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struct cmdq_client *cmdq_mbox_create(struct device *dev, int index,
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u32 timeout);
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/**
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* cmdq_mbox_destroy() - destroy CMDQ mailbox client and channel
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* @client: the CMDQ mailbox client
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*/
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void cmdq_mbox_destroy(struct cmdq_client *client);
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/**
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* cmdq_pkt_create() - create a CMDQ packet
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* @client: the CMDQ mailbox client
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* @size: required CMDQ buffer size
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*
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* Return: CMDQ packet pointer
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*/
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struct cmdq_pkt *cmdq_pkt_create(struct cmdq_client *client, size_t size);
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/**
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* cmdq_pkt_destroy() - destroy the CMDQ packet
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* @pkt: the CMDQ packet
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*/
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void cmdq_pkt_destroy(struct cmdq_pkt *pkt);
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/**
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* cmdq_pkt_write() - append write command to the CMDQ packet
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* @pkt: the CMDQ packet
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* @subsys: the CMDQ sub system code
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* @offset: register offset from CMDQ sub system
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* @value: the specified target register value
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*
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* Return: 0 for success; else the error code is returned
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*/
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int cmdq_pkt_write(struct cmdq_pkt *pkt, u8 subsys, u16 offset, u32 value);
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/**
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* cmdq_pkt_write_mask() - append write command with mask to the CMDQ packet
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* @pkt: the CMDQ packet
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* @subsys: the CMDQ sub system code
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* @offset: register offset from CMDQ sub system
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* @value: the specified target register value
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* @mask: the specified target register mask
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*
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* Return: 0 for success; else the error code is returned
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*/
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int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u8 subsys,
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u16 offset, u32 value, u32 mask);
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/**
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* cmdq_pkt_wfe() - append wait for event command to the CMDQ packet
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* @pkt: the CMDQ packet
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* @event: the desired event type to "wait and CLEAR"
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*
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* Return: 0 for success; else the error code is returned
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*/
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int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u16 event);
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/**
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* cmdq_pkt_clear_event() - append clear event command to the CMDQ packet
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* @pkt: the CMDQ packet
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* @event: the desired event to be cleared
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*
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* Return: 0 for success; else the error code is returned
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*/
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int cmdq_pkt_clear_event(struct cmdq_pkt *pkt, u16 event);
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/**
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* cmdq_pkt_flush_async() - trigger CMDQ to asynchronously execute the CMDQ
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* packet and call back at the end of done packet
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* @pkt: the CMDQ packet
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* @cb: called at the end of done packet
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* @data: this data will pass back to cb
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*
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* Return: 0 for success; else the error code is returned
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*
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* Trigger CMDQ to asynchronously execute the CMDQ packet and call back
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* at the end of done packet. Note that this is an ASYNC function. When the
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* function returned, it may or may not be finished.
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*/
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int cmdq_pkt_flush_async(struct cmdq_pkt *pkt, cmdq_async_flush_cb cb,
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void *data);
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/**
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* cmdq_pkt_flush() - trigger CMDQ to execute the CMDQ packet
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* @pkt: the CMDQ packet
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*
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* Return: 0 for success; else the error code is returned
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*
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* Trigger CMDQ to execute the CMDQ packet. Note that this is a
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* synchronous flush function. When the function returned, the recorded
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* commands have been done.
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*/
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int cmdq_pkt_flush(struct cmdq_pkt *pkt);
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#endif /* __MTK_CMDQ_H__ */
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