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a6ba44e879
So far we had only one watchpoint, so we have hardcoded HBP_NUM to 1. But Power10 is introducing 2nd DAWR and thus kernel should be able to dynamically find actual number of watchpoints supported by hw it's running on. Introduce function for the same. Also convert HBP_NUM macro to HBP_NUM_MAX, which will now represent maximum number of watchpoints supported by Powerpc. Signed-off-by: Ravi Bangoria <ravi.bangoria@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Reviewed-by: Michael Neuling <mikey@neuling.org> Link: https://lore.kernel.org/r/20200514111741.97993-4-ravi.bangoria@linux.ibm.com
114 lines
3.2 KiB
C
114 lines
3.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* PowerPC BookIII S hardware breakpoint definitions
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*
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* Copyright 2010, IBM Corporation.
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* Author: K.Prasad <prasad@linux.vnet.ibm.com>
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*/
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#ifndef _PPC_BOOK3S_64_HW_BREAKPOINT_H
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#define _PPC_BOOK3S_64_HW_BREAKPOINT_H
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#ifdef __KERNEL__
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struct arch_hw_breakpoint {
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unsigned long address;
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u16 type;
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u16 len; /* length of the target data symbol */
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u16 hw_len; /* length programmed in hw */
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};
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/* Note: Don't change the the first 6 bits below as they are in the same order
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* as the dabr and dabrx.
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*/
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#define HW_BRK_TYPE_READ 0x01
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#define HW_BRK_TYPE_WRITE 0x02
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#define HW_BRK_TYPE_TRANSLATE 0x04
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#define HW_BRK_TYPE_USER 0x08
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#define HW_BRK_TYPE_KERNEL 0x10
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#define HW_BRK_TYPE_HYP 0x20
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#define HW_BRK_TYPE_EXTRANEOUS_IRQ 0x80
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/* bits that overlap with the bottom 3 bits of the dabr */
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#define HW_BRK_TYPE_RDWR (HW_BRK_TYPE_READ | HW_BRK_TYPE_WRITE)
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#define HW_BRK_TYPE_DABR (HW_BRK_TYPE_RDWR | HW_BRK_TYPE_TRANSLATE)
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#define HW_BRK_TYPE_PRIV_ALL (HW_BRK_TYPE_USER | HW_BRK_TYPE_KERNEL | \
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HW_BRK_TYPE_HYP)
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#ifdef CONFIG_PPC_8xx
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#define HW_BREAKPOINT_ALIGN 0x3
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#else
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#define HW_BREAKPOINT_ALIGN 0x7
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#endif
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#define DABR_MAX_LEN 8
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#define DAWR_MAX_LEN 512
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static inline int nr_wp_slots(void)
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{
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return HBP_NUM_MAX;
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}
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#ifdef CONFIG_HAVE_HW_BREAKPOINT
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#include <linux/kdebug.h>
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#include <asm/reg.h>
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#include <asm/debug.h>
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struct perf_event_attr;
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struct perf_event;
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struct pmu;
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struct perf_sample_data;
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struct task_struct;
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extern int hw_breakpoint_slots(int type);
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extern int arch_bp_generic_fields(int type, int *gen_bp_type);
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extern int arch_check_bp_in_kernelspace(struct arch_hw_breakpoint *hw);
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extern int hw_breakpoint_arch_parse(struct perf_event *bp,
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const struct perf_event_attr *attr,
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struct arch_hw_breakpoint *hw);
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extern int hw_breakpoint_exceptions_notify(struct notifier_block *unused,
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unsigned long val, void *data);
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int arch_install_hw_breakpoint(struct perf_event *bp);
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void arch_uninstall_hw_breakpoint(struct perf_event *bp);
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void arch_unregister_hw_breakpoint(struct perf_event *bp);
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void hw_breakpoint_pmu_read(struct perf_event *bp);
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extern void flush_ptrace_hw_breakpoint(struct task_struct *tsk);
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extern struct pmu perf_ops_bp;
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extern void ptrace_triggered(struct perf_event *bp,
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struct perf_sample_data *data, struct pt_regs *regs);
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static inline void hw_breakpoint_disable(void)
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{
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struct arch_hw_breakpoint brk;
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brk.address = 0;
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brk.type = 0;
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brk.len = 0;
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brk.hw_len = 0;
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if (ppc_breakpoint_available())
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__set_breakpoint(&brk);
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}
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extern void thread_change_pc(struct task_struct *tsk, struct pt_regs *regs);
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int hw_breakpoint_handler(struct die_args *args);
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#else /* CONFIG_HAVE_HW_BREAKPOINT */
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static inline void hw_breakpoint_disable(void) { }
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static inline void thread_change_pc(struct task_struct *tsk,
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struct pt_regs *regs) { }
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#endif /* CONFIG_HAVE_HW_BREAKPOINT */
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#ifdef CONFIG_PPC_DAWR
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extern bool dawr_force_enable;
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static inline bool dawr_enabled(void)
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{
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return dawr_force_enable;
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}
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int set_dawr(struct arch_hw_breakpoint *brk);
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#else
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static inline bool dawr_enabled(void) { return false; }
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static inline int set_dawr(struct arch_hw_breakpoint *brk) { return -1; }
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#endif
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#endif /* __KERNEL__ */
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#endif /* _PPC_BOOK3S_64_HW_BREAKPOINT_H */
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