mirror of
https://github.com/Fishwaldo/Star64_linux.git
synced 2025-07-23 15:27:29 +00:00
aeaa0bfe89
The Designware controller has common registers to set number of fast training sequence ordered sets. The Artpec6, Intel, and Tegra driver initialize these register fields. Let's move the initialization to the common setup code and drivers just have to provide the value. There's a slight change in that the common clock mode N_FTS field is now initialized. Previously only the Intel driver set this. It's not clear from the code if common clock mode is used in the Artpec6 or Tegra driver. It depends on the DWC configuration. Given the field is not initialized while the others are, it seems unlikely common clock mode is used. Link: https://lore.kernel.org/r/20200821035420.380495-40-robh@kernel.org Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Jesper Nilsson <jesper.nilsson@axis.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Jingoo Han <jingoohan1@gmail.com> Cc: Gustavo Pimentel <gustavo.pimentel@synopsys.com> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Jonathan Hunter <jonathanh@nvidia.com> Cc: linux-tegra@vger.kernel.org |
||
|---|---|---|
| .. | ||
| Kconfig | ||
| Makefile | ||
| pci-dra7xx.c | ||
| pci-exynos.c | ||
| pci-imx6.c | ||
| pci-keystone.c | ||
| pci-layerscape-ep.c | ||
| pci-layerscape.c | ||
| pci-meson.c | ||
| pcie-al.c | ||
| pcie-armada8k.c | ||
| pcie-artpec6.c | ||
| pcie-designware-ep.c | ||
| pcie-designware-host.c | ||
| pcie-designware-plat.c | ||
| pcie-designware.c | ||
| pcie-designware.h | ||
| pcie-hisi.c | ||
| pcie-histb.c | ||
| pcie-intel-gw.c | ||
| pcie-kirin.c | ||
| pcie-qcom.c | ||
| pcie-spear13xx.c | ||
| pcie-tegra194.c | ||
| pcie-uniphier-ep.c | ||
| pcie-uniphier.c | ||