Star64_linux/drivers/gpu/drm/i915/display
Imre Deak b30edfd8d0 drm/i915: Switch to LTTPR non-transparent mode link training
The DP Standard's recommendation is to use the LTTPR non-transparent
mode link training if LTTPRs are detected, so let's do this.

Besides power-saving, the advantages of this are that the maximum number
of LTTPRs can only be used in non-transparent mode (the limit is 5-8 in
transparent mode), and it provides a way to narrow down the reason for a
link training failure to a given link segment. Non-transparent mode is
probably also the mode that was tested the most by the industry.

The changes in this patchset:
- Pass the DP PHY that is currently link trained to all LT helpers, so
  that these can access the correct LTTPR/DPRX DPCD registers.
- During LT take into account the LTTPR common lane rate/count and the
  per LTTPR-PHY vswing/pre-emph limits.
- Switch to LTTPR non-transparent LT mode and train each link segment
  according to the sequence in DP Standard v2.0 (complete CR/EQ for
  each segment before continuing with the next segment).

v2:
- Switch to non-transparent mode during connector detection, which is
  required before reading the per-PHY LTTPR capabilities.
- Move the DP_PHY_LTTPR() macro to drm_dp_helper.h (Ville)
- Use the new drm_dp_dpcd_read_phy_link_status() instead of adding the
  same logic to intel_dp_get_link_status(). (Ville)
- Make intel_dp_lttpr_phy_caps() return a pointer to the whole array
  instead of a pointer to its first element. (Ville)
- Add the intel_dp_phy_is_downstream_of_source() helper. (Ville)
- Add a code comment about the disable->enable quirk of
  non-transparent mode.
- Add the intel_dp_training_pattern_set_reg() helper.
- Fix checkpatch/sparse warns.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20201007170917.1764556-7-imre.deak@intel.com
2020-10-12 15:33:03 +03:00
..
dvo_ch7xxx.c
dvo_ch7017.c
dvo_ivch.c
dvo_ns2501.c
dvo_sil164.c
dvo_tfp410.c
icl_dsi.c drm/i915: Move the initial fastset commit check to encoder hooks 2020-10-06 14:00:24 +03:00
intel_acpi.c
intel_acpi.h
intel_atomic.c drm/i915: Remove the old global state stuff 2020-09-17 20:08:08 +03:00
intel_atomic.h drm/i915: Remove the old global state stuff 2020-09-17 20:08:08 +03:00
intel_atomic_plane.c drm/i915: Add dedicated plane hook for async flip case 2020-09-28 14:12:49 +03:00
intel_atomic_plane.h
intel_audio.c drm/i915: Nuke force_min_cdclk_changed 2020-09-17 20:10:21 +03:00
intel_audio.h
intel_bios.c drm/i915/vbt: Update the version and expected size of BDB_GENERAL_DEFINITIONS map 2020-10-09 14:09:53 -07:00
intel_bios.h
intel_bw.c
intel_bw.h
intel_cdclk.c drm/i915/dg1: Initialize RAWCLK properly 2020-10-07 13:51:19 -07:00
intel_cdclk.h drm/i915: Nuke force_min_cdclk_changed 2020-09-17 20:10:21 +03:00
intel_color.c drm/i915: Replace some gamma_mode ifs with switches 2020-09-28 18:09:52 +03:00
intel_color.h
intel_combo_phy.c drm/i915/dg1: Update comp master/slave relationships for PHYs 2020-10-07 13:51:24 -07:00
intel_combo_phy.h
intel_connector.c
intel_connector.h
intel_crt.c drm/i915: Reduce INTEL_DISPLAY_ENABLED to just treat outputs as disconnected 2020-09-15 15:28:21 +03:00
intel_crt.h
intel_csr.c
intel_csr.h
intel_ddi.c drm/i915: Fix DP link training pattern mask 2020-10-12 15:31:35 +03:00
intel_ddi.h drm/i915: Eliminate intel_dp.regs.dp_tp_{ctl,status} 2020-10-01 16:45:57 +03:00
intel_de.h
intel_display.c drm/i915/display: Program PSR2 selective fetch registers 2020-10-09 15:07:39 -07:00
intel_display.h drm/i915: Add more AUX CHs to the enum 2020-09-15 17:46:56 +03:00
intel_display_debugfs.c drm/dp: Pimp drm_dp_downstream_max_bpc() 2020-09-17 17:12:15 +03:00
intel_display_debugfs.h
intel_display_power.c
intel_display_power.h
intel_display_types.h drm/i915: Switch to LTTPR non-transparent mode link training 2020-10-12 15:33:03 +03:00
intel_dp.c drm/i915: Switch to LTTPR non-transparent mode link training 2020-10-12 15:33:03 +03:00
intel_dp.h drm/i915: Switch to LTTPR non-transparent mode link training 2020-10-12 15:33:03 +03:00
intel_dp_aux_backlight.c
intel_dp_aux_backlight.h
intel_dp_hdcp.c
intel_dp_link_training.c drm/i915: Switch to LTTPR non-transparent mode link training 2020-10-12 15:33:03 +03:00
intel_dp_link_training.h drm/i915: Switch to LTTPR non-transparent mode link training 2020-10-12 15:33:03 +03:00
intel_dp_mst.c drm/i915: Move the initial fastset commit check to encoder hooks 2020-10-06 14:00:24 +03:00
intel_dp_mst.h
intel_dpio_phy.c drm/i915: Plumb crtc_state to link training 2020-10-01 16:45:57 +03:00
intel_dpio_phy.h drm/i915: Plumb crtc_state to link training 2020-10-01 16:45:57 +03:00
intel_dpll_mgr.c drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock 2020-10-06 14:00:38 +03:00
intel_dpll_mgr.h
intel_dsb.c
intel_dsb.h
intel_dsi.c
intel_dsi.h drm/i915/dsi: Initiate frame request in cmd mode 2020-09-28 20:02:14 +03:00
intel_dsi_dcs_backlight.c
intel_dsi_dcs_backlight.h
intel_dsi_vbt.c
intel_dvo.c drm/i915: Reduce INTEL_DISPLAY_ENABLED to just treat outputs as disconnected 2020-09-15 15:28:21 +03:00
intel_dvo.h
intel_dvo_dev.h
intel_fbc.c
intel_fbc.h
intel_fbdev.c drm/i915: Reduce INTEL_DISPLAY_ENABLED to just removing the outputs 2020-09-15 14:57:13 +03:00
intel_fbdev.h
intel_fifo_underrun.c
intel_fifo_underrun.h
intel_frontbuffer.c
intel_frontbuffer.h
intel_global_state.c
intel_global_state.h
intel_gmbus.c drm/i915/dg1: gmbus pin mapping 2020-10-07 13:51:21 -07:00
intel_gmbus.h
intel_hdcp.c drm/i915: dont retry stream management at seq_num_m roll over 2020-09-24 15:44:57 +05:30
intel_hdcp.h
intel_hdmi.c drm/i915/dg1: gmbus pin mapping 2020-10-07 13:51:21 -07:00
intel_hdmi.h drm/i915: Do YCbCr 444->420 conversion via DP protocol converters 2020-09-17 18:43:09 +03:00
intel_hotplug.c drm/i915: Nuke pointless variable 2020-09-15 18:01:57 +03:00
intel_hotplug.h
intel_lpe_audio.c
intel_lpe_audio.h
intel_lspcon.c drm/i915: Make lspcon_init() static 2020-10-02 14:10:27 +03:00
intel_lspcon.h drm/i915: Init lspcon after HPD in intel_dp_detect() 2020-10-01 19:22:10 +03:00
intel_lvds.c drm/i915: Wait for LVDS panel power cycle delay on reboot 2020-10-09 21:12:13 +03:00
intel_lvds.h
intel_opregion.c
intel_opregion.h
intel_overlay.c
intel_overlay.h
intel_panel.c drm/i915: Reduce INTEL_DISPLAY_ENABLED to just treat outputs as disconnected 2020-09-15 15:28:21 +03:00
intel_panel.h drm/i915: Reduce INTEL_DISPLAY_ENABLED to just treat outputs as disconnected 2020-09-15 15:28:21 +03:00
intel_pipe_crc.c
intel_pipe_crc.h
intel_psr.c drm/i915/display: Program PSR2 selective fetch registers 2020-10-09 15:07:39 -07:00
intel_psr.h drm/i915/display: Program PSR2 selective fetch registers 2020-10-09 15:07:39 -07:00
intel_quirks.c
intel_quirks.h
intel_sdvo.c drm/i915: Reduce INTEL_DISPLAY_ENABLED to just treat outputs as disconnected 2020-09-15 15:28:21 +03:00
intel_sdvo.h
intel_sdvo_regs.h
intel_sprite.c drm/i915/display: Program PSR2 selective fetch registers 2020-10-09 15:07:39 -07:00
intel_sprite.h
intel_tc.c
intel_tc.h
intel_tv.c drm/i915: Reduce INTEL_DISPLAY_ENABLED to just treat outputs as disconnected 2020-09-15 15:28:21 +03:00
intel_tv.h
intel_vbt_defs.h drm/i915/vbt: Add VRR VBT toggle 2020-10-09 14:09:54 -07:00
intel_vdsc.c
intel_vdsc.h
intel_vga.c
intel_vga.h
vlv_dsi.c drm/i915: Wait for VLV/CHV/BXT/GLK DSI panel power cycle delay on reboot 2020-10-09 21:12:13 +03:00
vlv_dsi_pll.c