Brendan Jackman 981f94c3e9 bpf: Add bitwise atomic instructions ... This adds instructions for atomic[64]_[fetch_]and atomic[64]_[fetch_]or atomic[64]_[fetch_]xor All these operations are isomorphic enough to implement with the same verifier, interpreter, and x86 JIT code, hence being a single commit. The main interesting thing here is that x86 doesn't directly support the fetch_ version these operations, so we need to generate a CMPXCHG loop in the JIT. This requires the use of two temporary registers, IIUC it's safe to use BPF_REG_AX and x86's AUX_REG for this purpose. Signed-off-by: Brendan Jackman <jackmanb@google.com> Signed-off-by: Alexei Starovoitov <ast@kernel.org> Acked-by: Yonghong Song <yhs@fb.com> Link: https://lore.kernel.org/bpf/20210114181751.768687-10-jackmanb@google.com		2021-01-14 18:34:29 -08:00
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alpha
arc	ARC updates for 5.11-rc3	2021-01-05 12:46:27 -08:00
arm	bpf: Rename BPF_XADD and prepare to encode other atomics in .imm	2021-01-14 18:34:29 -08:00
arm64	bpf: Rename BPF_XADD and prepare to encode other atomics in .imm	2021-01-14 18:34:29 -08:00
c6x
csky
h8300
hexagon
ia64
m68k
microblaze
mips	bpf: Rename BPF_XADD and prepare to encode other atomics in .imm	2021-01-14 18:34:29 -08:00
nds32
nios2
openrisc
parisc
powerpc	bpf: Rename BPF_XADD and prepare to encode other atomics in .imm	2021-01-14 18:34:29 -08:00
riscv	bpf: Rename BPF_XADD and prepare to encode other atomics in .imm	2021-01-14 18:34:29 -08:00
s390	bpf: Rename BPF_XADD and prepare to encode other atomics in .imm	2021-01-14 18:34:29 -08:00
sh
sparc	bpf: Rename BPF_XADD and prepare to encode other atomics in .imm	2021-01-14 18:34:29 -08:00
um
x86	bpf: Add bitwise atomic instructions	2021-01-14 18:34:29 -08:00
xtensa
.gitignore
Kconfig