mirror of
https://github.com/Fishwaldo/Star64_linux.git
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On systems with VHE the kernel and KVM's world-switch code run at the
same exception level. Code that is only used on a VHE system does not
need to be annotated as __hyp_text as it can reside anywhere in the
kernel text.
__hyp_text was also used to prevent kprobes from patching breakpoint
instructions into this region, as this code runs at a different
exception level. While this is no longer true with VHE, KVM still
switches VBAR_EL1, meaning a kprobe's breakpoint executed in the
world-switch code will cause a hyp-panic.
echo "p:weasel sysreg_save_guest_state_vhe" > /sys/kernel/debug/tracing/kprobe_events
echo 1 > /sys/kernel/debug/tracing/events/kprobes/weasel/enable
lkvm run -k /boot/Image --console serial -p "console=ttyS0 earlycon=uart,mmio,0x3f8"
# lkvm run -k /boot/Image -m 384 -c 3 --name guest-1474
Info: Placing fdt at 0x8fe00000 - 0x8fffffff
Info: virtio-mmio.devices=0x200@0x10000:36
Info: virtio-mmio.devices=0x200@0x10200:37
Info: virtio-mmio.devices=0x200@0x10400:38
[ 614.178186] Kernel panic - not syncing: HYP panic:
[ 614.178186] PS:404003c9 PC:ffff0000100d70e0 ESR:f2000004
[ 614.178186] FAR:0000000080080000 HPFAR:0000000000800800 PAR:1d00007edbadc0de
[ 614.178186] VCPU:00000000f8de32f1
[ 614.178383] CPU: 2 PID: 1482 Comm: kvm-vcpu-0 Not tainted 5.0.0-rc2 #10799
[ 614.178446] Call trace:
[ 614.178480] dump_backtrace+0x0/0x148
[ 614.178567] show_stack+0x24/0x30
[ 614.178658] dump_stack+0x90/0xb4
[ 614.178710] panic+0x13c/0x2d8
[ 614.178793] hyp_panic+0xac/0xd8
[ 614.178880] kvm_vcpu_run_vhe+0x9c/0xe0
[ 614.178958] kvm_arch_vcpu_ioctl_run+0x454/0x798
[ 614.179038] kvm_vcpu_ioctl+0x360/0x898
[ 614.179087] do_vfs_ioctl+0xc4/0x858
[ 614.179174] ksys_ioctl+0x84/0xb8
[ 614.179261] __arm64_sys_ioctl+0x28/0x38
[ 614.179348] el0_svc_common+0x94/0x108
[ 614.179401] el0_svc_handler+0x38/0x78
[ 614.179487] el0_svc+0x8/0xc
[ 614.179558] SMP: stopping secondary CPUs
[ 614.179661] Kernel Offset: disabled
[ 614.179695] CPU features: 0x003,2a80aa38
[ 614.179758] Memory Limit: none
[ 614.179858] ---[ end Kernel panic - not syncing: HYP panic:
[ 614.179858] PS:404003c9 PC:ffff0000100d70e0 ESR:f2000004
[ 614.179858] FAR:0000000080080000 HPFAR:0000000000800800 PAR:1d00007edbadc0de
[ 614.179858] VCPU:00000000f8de32f1 ]---
Annotate the VHE world-switch functions that aren't marked
__hyp_text using NOKPROBE_SYMBOL().
Signed-off-by: James Morse <james.morse@arm.com>
Fixes: 3f5c90b890
("KVM: arm64: Introduce VHE-specific kvm_vcpu_run")
Acked-by: Masami Hiramatsu <mhiramat@kernel.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
641 lines
16 KiB
C
641 lines
16 KiB
C
/*
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* Copyright (C) 2015 - ARM Ltd
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/arm-smccc.h>
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#include <linux/types.h>
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#include <linux/jump_label.h>
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#include <uapi/linux/psci.h>
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#include <kvm/arm_psci.h>
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#include <asm/cpufeature.h>
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#include <asm/kprobes.h>
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#include <asm/kvm_asm.h>
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#include <asm/kvm_emulate.h>
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#include <asm/kvm_host.h>
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#include <asm/kvm_hyp.h>
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#include <asm/kvm_mmu.h>
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#include <asm/fpsimd.h>
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#include <asm/debug-monitors.h>
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#include <asm/processor.h>
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#include <asm/thread_info.h>
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/* Check whether the FP regs were dirtied while in the host-side run loop: */
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static bool __hyp_text update_fp_enabled(struct kvm_vcpu *vcpu)
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{
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if (vcpu->arch.host_thread_info->flags & _TIF_FOREIGN_FPSTATE)
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vcpu->arch.flags &= ~(KVM_ARM64_FP_ENABLED |
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KVM_ARM64_FP_HOST);
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return !!(vcpu->arch.flags & KVM_ARM64_FP_ENABLED);
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}
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/* Save the 32-bit only FPSIMD system register state */
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static void __hyp_text __fpsimd_save_fpexc32(struct kvm_vcpu *vcpu)
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{
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if (!vcpu_el1_is_32bit(vcpu))
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return;
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vcpu->arch.ctxt.sys_regs[FPEXC32_EL2] = read_sysreg(fpexc32_el2);
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}
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static void __hyp_text __activate_traps_fpsimd32(struct kvm_vcpu *vcpu)
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{
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/*
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* We are about to set CPTR_EL2.TFP to trap all floating point
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* register accesses to EL2, however, the ARM ARM clearly states that
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* traps are only taken to EL2 if the operation would not otherwise
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* trap to EL1. Therefore, always make sure that for 32-bit guests,
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* we set FPEXC.EN to prevent traps to EL1, when setting the TFP bit.
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* If FP/ASIMD is not implemented, FPEXC is UNDEFINED and any access to
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* it will cause an exception.
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*/
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if (vcpu_el1_is_32bit(vcpu) && system_supports_fpsimd()) {
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write_sysreg(1 << 30, fpexc32_el2);
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isb();
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}
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}
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static void __hyp_text __activate_traps_common(struct kvm_vcpu *vcpu)
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{
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/* Trap on AArch32 cp15 c15 (impdef sysregs) accesses (EL1 or EL0) */
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write_sysreg(1 << 15, hstr_el2);
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/*
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* Make sure we trap PMU access from EL0 to EL2. Also sanitize
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* PMSELR_EL0 to make sure it never contains the cycle
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* counter, which could make a PMXEVCNTR_EL0 access UNDEF at
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* EL1 instead of being trapped to EL2.
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*/
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write_sysreg(0, pmselr_el0);
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write_sysreg(ARMV8_PMU_USERENR_MASK, pmuserenr_el0);
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write_sysreg(vcpu->arch.mdcr_el2, mdcr_el2);
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}
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static void __hyp_text __deactivate_traps_common(void)
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{
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write_sysreg(0, hstr_el2);
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write_sysreg(0, pmuserenr_el0);
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}
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static void activate_traps_vhe(struct kvm_vcpu *vcpu)
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{
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u64 val;
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val = read_sysreg(cpacr_el1);
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val |= CPACR_EL1_TTA;
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val &= ~CPACR_EL1_ZEN;
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if (!update_fp_enabled(vcpu)) {
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val &= ~CPACR_EL1_FPEN;
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__activate_traps_fpsimd32(vcpu);
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}
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write_sysreg(val, cpacr_el1);
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write_sysreg(kvm_get_hyp_vector(), vbar_el1);
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}
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NOKPROBE_SYMBOL(activate_traps_vhe);
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static void __hyp_text __activate_traps_nvhe(struct kvm_vcpu *vcpu)
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{
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u64 val;
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__activate_traps_common(vcpu);
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val = CPTR_EL2_DEFAULT;
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val |= CPTR_EL2_TTA | CPTR_EL2_TZ;
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if (!update_fp_enabled(vcpu)) {
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val |= CPTR_EL2_TFP;
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__activate_traps_fpsimd32(vcpu);
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}
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write_sysreg(val, cptr_el2);
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}
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static void __hyp_text __activate_traps(struct kvm_vcpu *vcpu)
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{
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u64 hcr = vcpu->arch.hcr_el2;
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write_sysreg(hcr, hcr_el2);
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if (cpus_have_const_cap(ARM64_HAS_RAS_EXTN) && (hcr & HCR_VSE))
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write_sysreg_s(vcpu->arch.vsesr_el2, SYS_VSESR_EL2);
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if (has_vhe())
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activate_traps_vhe(vcpu);
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else
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__activate_traps_nvhe(vcpu);
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}
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static void deactivate_traps_vhe(void)
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{
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extern char vectors[]; /* kernel exception vectors */
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write_sysreg(HCR_HOST_VHE_FLAGS, hcr_el2);
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/*
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* ARM erratum 1165522 requires the actual execution of the above
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* before we can switch to the EL2/EL0 translation regime used by
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* the host.
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*/
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asm(ALTERNATIVE("nop", "isb", ARM64_WORKAROUND_1165522));
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write_sysreg(CPACR_EL1_DEFAULT, cpacr_el1);
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write_sysreg(vectors, vbar_el1);
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}
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NOKPROBE_SYMBOL(deactivate_traps_vhe);
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static void __hyp_text __deactivate_traps_nvhe(void)
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{
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u64 mdcr_el2 = read_sysreg(mdcr_el2);
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__deactivate_traps_common();
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mdcr_el2 &= MDCR_EL2_HPMN_MASK;
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mdcr_el2 |= MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT;
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write_sysreg(mdcr_el2, mdcr_el2);
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write_sysreg(HCR_HOST_NVHE_FLAGS, hcr_el2);
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write_sysreg(CPTR_EL2_DEFAULT, cptr_el2);
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}
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static void __hyp_text __deactivate_traps(struct kvm_vcpu *vcpu)
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{
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/*
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* If we pended a virtual abort, preserve it until it gets
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* cleared. See D1.14.3 (Virtual Interrupts) for details, but
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* the crucial bit is "On taking a vSError interrupt,
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* HCR_EL2.VSE is cleared to 0."
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*/
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if (vcpu->arch.hcr_el2 & HCR_VSE)
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vcpu->arch.hcr_el2 = read_sysreg(hcr_el2);
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if (has_vhe())
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deactivate_traps_vhe();
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else
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__deactivate_traps_nvhe();
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}
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void activate_traps_vhe_load(struct kvm_vcpu *vcpu)
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{
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__activate_traps_common(vcpu);
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}
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void deactivate_traps_vhe_put(void)
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{
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u64 mdcr_el2 = read_sysreg(mdcr_el2);
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mdcr_el2 &= MDCR_EL2_HPMN_MASK |
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MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT |
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MDCR_EL2_TPMS;
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write_sysreg(mdcr_el2, mdcr_el2);
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__deactivate_traps_common();
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}
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static void __hyp_text __activate_vm(struct kvm *kvm)
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{
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__load_guest_stage2(kvm);
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}
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static void __hyp_text __deactivate_vm(struct kvm_vcpu *vcpu)
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{
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write_sysreg(0, vttbr_el2);
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}
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/* Save VGICv3 state on non-VHE systems */
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static void __hyp_text __hyp_vgic_save_state(struct kvm_vcpu *vcpu)
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{
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if (static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif)) {
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__vgic_v3_save_state(vcpu);
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__vgic_v3_deactivate_traps(vcpu);
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}
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}
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/* Restore VGICv3 state on non_VEH systems */
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static void __hyp_text __hyp_vgic_restore_state(struct kvm_vcpu *vcpu)
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{
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if (static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif)) {
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__vgic_v3_activate_traps(vcpu);
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__vgic_v3_restore_state(vcpu);
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}
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}
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static bool __hyp_text __true_value(void)
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{
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return true;
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}
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static bool __hyp_text __false_value(void)
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{
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return false;
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}
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static hyp_alternate_select(__check_arm_834220,
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__false_value, __true_value,
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ARM64_WORKAROUND_834220);
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static bool __hyp_text __translate_far_to_hpfar(u64 far, u64 *hpfar)
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{
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u64 par, tmp;
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/*
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* Resolve the IPA the hard way using the guest VA.
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*
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* Stage-1 translation already validated the memory access
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* rights. As such, we can use the EL1 translation regime, and
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* don't have to distinguish between EL0 and EL1 access.
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*
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* We do need to save/restore PAR_EL1 though, as we haven't
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* saved the guest context yet, and we may return early...
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*/
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par = read_sysreg(par_el1);
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asm volatile("at s1e1r, %0" : : "r" (far));
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isb();
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tmp = read_sysreg(par_el1);
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write_sysreg(par, par_el1);
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if (unlikely(tmp & 1))
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return false; /* Translation failed, back to guest */
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/* Convert PAR to HPFAR format */
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*hpfar = PAR_TO_HPFAR(tmp);
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return true;
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}
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static bool __hyp_text __populate_fault_info(struct kvm_vcpu *vcpu)
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{
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u8 ec;
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u64 esr;
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u64 hpfar, far;
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esr = vcpu->arch.fault.esr_el2;
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ec = ESR_ELx_EC(esr);
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if (ec != ESR_ELx_EC_DABT_LOW && ec != ESR_ELx_EC_IABT_LOW)
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return true;
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far = read_sysreg_el2(far);
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/*
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* The HPFAR can be invalid if the stage 2 fault did not
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* happen during a stage 1 page table walk (the ESR_EL2.S1PTW
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* bit is clear) and one of the two following cases are true:
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* 1. The fault was due to a permission fault
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* 2. The processor carries errata 834220
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*
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* Therefore, for all non S1PTW faults where we either have a
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* permission fault or the errata workaround is enabled, we
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* resolve the IPA using the AT instruction.
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*/
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if (!(esr & ESR_ELx_S1PTW) &&
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(__check_arm_834220()() || (esr & ESR_ELx_FSC_TYPE) == FSC_PERM)) {
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if (!__translate_far_to_hpfar(far, &hpfar))
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return false;
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} else {
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hpfar = read_sysreg(hpfar_el2);
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}
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vcpu->arch.fault.far_el2 = far;
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vcpu->arch.fault.hpfar_el2 = hpfar;
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return true;
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}
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static bool __hyp_text __hyp_switch_fpsimd(struct kvm_vcpu *vcpu)
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{
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struct user_fpsimd_state *host_fpsimd = vcpu->arch.host_fpsimd_state;
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if (has_vhe())
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write_sysreg(read_sysreg(cpacr_el1) | CPACR_EL1_FPEN,
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cpacr_el1);
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else
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write_sysreg(read_sysreg(cptr_el2) & ~(u64)CPTR_EL2_TFP,
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cptr_el2);
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isb();
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if (vcpu->arch.flags & KVM_ARM64_FP_HOST) {
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/*
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* In the SVE case, VHE is assumed: it is enforced by
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* Kconfig and kvm_arch_init().
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*/
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if (system_supports_sve() &&
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(vcpu->arch.flags & KVM_ARM64_HOST_SVE_IN_USE)) {
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struct thread_struct *thread = container_of(
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host_fpsimd,
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struct thread_struct, uw.fpsimd_state);
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sve_save_state(sve_pffr(thread), &host_fpsimd->fpsr);
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} else {
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__fpsimd_save_state(host_fpsimd);
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}
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vcpu->arch.flags &= ~KVM_ARM64_FP_HOST;
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}
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__fpsimd_restore_state(&vcpu->arch.ctxt.gp_regs.fp_regs);
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/* Skip restoring fpexc32 for AArch64 guests */
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if (!(read_sysreg(hcr_el2) & HCR_RW))
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write_sysreg(vcpu->arch.ctxt.sys_regs[FPEXC32_EL2],
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fpexc32_el2);
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vcpu->arch.flags |= KVM_ARM64_FP_ENABLED;
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return true;
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}
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/*
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* Return true when we were able to fixup the guest exit and should return to
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* the guest, false when we should restore the host state and return to the
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* main run loop.
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*/
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static bool __hyp_text fixup_guest_exit(struct kvm_vcpu *vcpu, u64 *exit_code)
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{
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if (ARM_EXCEPTION_CODE(*exit_code) != ARM_EXCEPTION_IRQ)
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vcpu->arch.fault.esr_el2 = read_sysreg_el2(esr);
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/*
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* We're using the raw exception code in order to only process
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* the trap if no SError is pending. We will come back to the
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* same PC once the SError has been injected, and replay the
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* trapping instruction.
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*/
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if (*exit_code != ARM_EXCEPTION_TRAP)
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goto exit;
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/*
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* We trap the first access to the FP/SIMD to save the host context
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* and restore the guest context lazily.
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* If FP/SIMD is not implemented, handle the trap and inject an
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* undefined instruction exception to the guest.
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*/
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if (system_supports_fpsimd() &&
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kvm_vcpu_trap_get_class(vcpu) == ESR_ELx_EC_FP_ASIMD)
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return __hyp_switch_fpsimd(vcpu);
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if (!__populate_fault_info(vcpu))
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return true;
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if (static_branch_unlikely(&vgic_v2_cpuif_trap)) {
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bool valid;
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valid = kvm_vcpu_trap_get_class(vcpu) == ESR_ELx_EC_DABT_LOW &&
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kvm_vcpu_trap_get_fault_type(vcpu) == FSC_FAULT &&
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kvm_vcpu_dabt_isvalid(vcpu) &&
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!kvm_vcpu_dabt_isextabt(vcpu) &&
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!kvm_vcpu_dabt_iss1tw(vcpu);
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if (valid) {
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int ret = __vgic_v2_perform_cpuif_access(vcpu);
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if (ret == 1)
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return true;
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|
|
|
/* Promote an illegal access to an SError.*/
|
|
if (ret == -1)
|
|
*exit_code = ARM_EXCEPTION_EL1_SERROR;
|
|
|
|
goto exit;
|
|
}
|
|
}
|
|
|
|
if (static_branch_unlikely(&vgic_v3_cpuif_trap) &&
|
|
(kvm_vcpu_trap_get_class(vcpu) == ESR_ELx_EC_SYS64 ||
|
|
kvm_vcpu_trap_get_class(vcpu) == ESR_ELx_EC_CP15_32)) {
|
|
int ret = __vgic_v3_perform_cpuif_access(vcpu);
|
|
|
|
if (ret == 1)
|
|
return true;
|
|
}
|
|
|
|
exit:
|
|
/* Return to the host kernel and handle the exit */
|
|
return false;
|
|
}
|
|
|
|
static inline bool __hyp_text __needs_ssbd_off(struct kvm_vcpu *vcpu)
|
|
{
|
|
if (!cpus_have_const_cap(ARM64_SSBD))
|
|
return false;
|
|
|
|
return !(vcpu->arch.workaround_flags & VCPU_WORKAROUND_2_FLAG);
|
|
}
|
|
|
|
static void __hyp_text __set_guest_arch_workaround_state(struct kvm_vcpu *vcpu)
|
|
{
|
|
#ifdef CONFIG_ARM64_SSBD
|
|
/*
|
|
* The host runs with the workaround always present. If the
|
|
* guest wants it disabled, so be it...
|
|
*/
|
|
if (__needs_ssbd_off(vcpu) &&
|
|
__hyp_this_cpu_read(arm64_ssbd_callback_required))
|
|
arm_smccc_1_1_smc(ARM_SMCCC_ARCH_WORKAROUND_2, 0, NULL);
|
|
#endif
|
|
}
|
|
|
|
static void __hyp_text __set_host_arch_workaround_state(struct kvm_vcpu *vcpu)
|
|
{
|
|
#ifdef CONFIG_ARM64_SSBD
|
|
/*
|
|
* If the guest has disabled the workaround, bring it back on.
|
|
*/
|
|
if (__needs_ssbd_off(vcpu) &&
|
|
__hyp_this_cpu_read(arm64_ssbd_callback_required))
|
|
arm_smccc_1_1_smc(ARM_SMCCC_ARCH_WORKAROUND_2, 1, NULL);
|
|
#endif
|
|
}
|
|
|
|
/* Switch to the guest for VHE systems running in EL2 */
|
|
int kvm_vcpu_run_vhe(struct kvm_vcpu *vcpu)
|
|
{
|
|
struct kvm_cpu_context *host_ctxt;
|
|
struct kvm_cpu_context *guest_ctxt;
|
|
u64 exit_code;
|
|
|
|
host_ctxt = vcpu->arch.host_cpu_context;
|
|
host_ctxt->__hyp_running_vcpu = vcpu;
|
|
guest_ctxt = &vcpu->arch.ctxt;
|
|
|
|
sysreg_save_host_state_vhe(host_ctxt);
|
|
|
|
/*
|
|
* ARM erratum 1165522 requires us to configure both stage 1 and
|
|
* stage 2 translation for the guest context before we clear
|
|
* HCR_EL2.TGE.
|
|
*
|
|
* We have already configured the guest's stage 1 translation in
|
|
* kvm_vcpu_load_sysregs above. We must now call __activate_vm
|
|
* before __activate_traps, because __activate_vm configures
|
|
* stage 2 translation, and __activate_traps clear HCR_EL2.TGE
|
|
* (among other things).
|
|
*/
|
|
__activate_vm(vcpu->kvm);
|
|
__activate_traps(vcpu);
|
|
|
|
sysreg_restore_guest_state_vhe(guest_ctxt);
|
|
__debug_switch_to_guest(vcpu);
|
|
|
|
__set_guest_arch_workaround_state(vcpu);
|
|
|
|
do {
|
|
/* Jump in the fire! */
|
|
exit_code = __guest_enter(vcpu, host_ctxt);
|
|
|
|
/* And we're baaack! */
|
|
} while (fixup_guest_exit(vcpu, &exit_code));
|
|
|
|
__set_host_arch_workaround_state(vcpu);
|
|
|
|
sysreg_save_guest_state_vhe(guest_ctxt);
|
|
|
|
__deactivate_traps(vcpu);
|
|
|
|
sysreg_restore_host_state_vhe(host_ctxt);
|
|
|
|
if (vcpu->arch.flags & KVM_ARM64_FP_ENABLED)
|
|
__fpsimd_save_fpexc32(vcpu);
|
|
|
|
__debug_switch_to_host(vcpu);
|
|
|
|
return exit_code;
|
|
}
|
|
NOKPROBE_SYMBOL(kvm_vcpu_run_vhe);
|
|
|
|
/* Switch to the guest for legacy non-VHE systems */
|
|
int __hyp_text __kvm_vcpu_run_nvhe(struct kvm_vcpu *vcpu)
|
|
{
|
|
struct kvm_cpu_context *host_ctxt;
|
|
struct kvm_cpu_context *guest_ctxt;
|
|
u64 exit_code;
|
|
|
|
vcpu = kern_hyp_va(vcpu);
|
|
|
|
host_ctxt = kern_hyp_va(vcpu->arch.host_cpu_context);
|
|
host_ctxt->__hyp_running_vcpu = vcpu;
|
|
guest_ctxt = &vcpu->arch.ctxt;
|
|
|
|
__sysreg_save_state_nvhe(host_ctxt);
|
|
|
|
__activate_vm(kern_hyp_va(vcpu->kvm));
|
|
__activate_traps(vcpu);
|
|
|
|
__hyp_vgic_restore_state(vcpu);
|
|
__timer_enable_traps(vcpu);
|
|
|
|
/*
|
|
* We must restore the 32-bit state before the sysregs, thanks
|
|
* to erratum #852523 (Cortex-A57) or #853709 (Cortex-A72).
|
|
*/
|
|
__sysreg32_restore_state(vcpu);
|
|
__sysreg_restore_state_nvhe(guest_ctxt);
|
|
__debug_switch_to_guest(vcpu);
|
|
|
|
__set_guest_arch_workaround_state(vcpu);
|
|
|
|
do {
|
|
/* Jump in the fire! */
|
|
exit_code = __guest_enter(vcpu, host_ctxt);
|
|
|
|
/* And we're baaack! */
|
|
} while (fixup_guest_exit(vcpu, &exit_code));
|
|
|
|
__set_host_arch_workaround_state(vcpu);
|
|
|
|
__sysreg_save_state_nvhe(guest_ctxt);
|
|
__sysreg32_save_state(vcpu);
|
|
__timer_disable_traps(vcpu);
|
|
__hyp_vgic_save_state(vcpu);
|
|
|
|
__deactivate_traps(vcpu);
|
|
__deactivate_vm(vcpu);
|
|
|
|
__sysreg_restore_state_nvhe(host_ctxt);
|
|
|
|
if (vcpu->arch.flags & KVM_ARM64_FP_ENABLED)
|
|
__fpsimd_save_fpexc32(vcpu);
|
|
|
|
/*
|
|
* This must come after restoring the host sysregs, since a non-VHE
|
|
* system may enable SPE here and make use of the TTBRs.
|
|
*/
|
|
__debug_switch_to_host(vcpu);
|
|
|
|
return exit_code;
|
|
}
|
|
|
|
static const char __hyp_panic_string[] = "HYP panic:\nPS:%08llx PC:%016llx ESR:%08llx\nFAR:%016llx HPFAR:%016llx PAR:%016llx\nVCPU:%p\n";
|
|
|
|
static void __hyp_text __hyp_call_panic_nvhe(u64 spsr, u64 elr, u64 par,
|
|
struct kvm_cpu_context *__host_ctxt)
|
|
{
|
|
struct kvm_vcpu *vcpu;
|
|
unsigned long str_va;
|
|
|
|
vcpu = __host_ctxt->__hyp_running_vcpu;
|
|
|
|
if (read_sysreg(vttbr_el2)) {
|
|
__timer_disable_traps(vcpu);
|
|
__deactivate_traps(vcpu);
|
|
__deactivate_vm(vcpu);
|
|
__sysreg_restore_state_nvhe(__host_ctxt);
|
|
}
|
|
|
|
/*
|
|
* Force the panic string to be loaded from the literal pool,
|
|
* making sure it is a kernel address and not a PC-relative
|
|
* reference.
|
|
*/
|
|
asm volatile("ldr %0, =__hyp_panic_string" : "=r" (str_va));
|
|
|
|
__hyp_do_panic(str_va,
|
|
spsr, elr,
|
|
read_sysreg(esr_el2), read_sysreg_el2(far),
|
|
read_sysreg(hpfar_el2), par, vcpu);
|
|
}
|
|
|
|
static void __hyp_call_panic_vhe(u64 spsr, u64 elr, u64 par,
|
|
struct kvm_cpu_context *host_ctxt)
|
|
{
|
|
struct kvm_vcpu *vcpu;
|
|
vcpu = host_ctxt->__hyp_running_vcpu;
|
|
|
|
__deactivate_traps(vcpu);
|
|
sysreg_restore_host_state_vhe(host_ctxt);
|
|
|
|
panic(__hyp_panic_string,
|
|
spsr, elr,
|
|
read_sysreg_el2(esr), read_sysreg_el2(far),
|
|
read_sysreg(hpfar_el2), par, vcpu);
|
|
}
|
|
NOKPROBE_SYMBOL(__hyp_call_panic_vhe);
|
|
|
|
void __hyp_text __noreturn hyp_panic(struct kvm_cpu_context *host_ctxt)
|
|
{
|
|
u64 spsr = read_sysreg_el2(spsr);
|
|
u64 elr = read_sysreg_el2(elr);
|
|
u64 par = read_sysreg(par_el1);
|
|
|
|
if (!has_vhe())
|
|
__hyp_call_panic_nvhe(spsr, elr, par, host_ctxt);
|
|
else
|
|
__hyp_call_panic_vhe(spsr, elr, par, host_ctxt);
|
|
|
|
unreachable();
|
|
}
|