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Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 3029 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
136 lines
3.5 KiB
C
136 lines
3.5 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* the ACC Virtual Support Module of AMD CS5536
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*
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* Copyright (C) 2007 Lemote, Inc.
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* Author : jlliu, liujl@lemote.com
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*
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* Copyright (C) 2009 Lemote, Inc.
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* Author: Wu Zhangjin, wuzhangjin@gmail.com
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*/
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#include <cs5536/cs5536.h>
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#include <cs5536/cs5536_pci.h>
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void pci_acc_write_reg(int reg, u32 value)
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{
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u32 hi = 0, lo = value;
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switch (reg) {
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case PCI_COMMAND:
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_rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo);
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if (value & PCI_COMMAND_MASTER)
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lo |= (0x03 << 8);
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else
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lo &= ~(0x03 << 8);
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_wrmsr(GLIU_MSR_REG(GLIU_PAE), hi, lo);
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break;
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case PCI_STATUS:
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if (value & PCI_STATUS_PARITY) {
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_rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
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if (lo & SB_PARE_ERR_FLAG) {
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lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG;
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_wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);
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}
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}
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break;
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case PCI_BAR0_REG:
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if (value == PCI_BAR_RANGE_MASK) {
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_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
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lo |= SOFT_BAR_ACC_FLAG;
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_wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
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} else if (value & 0x01) {
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value &= 0xfffffffc;
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hi = 0xA0000000 | ((value & 0x000ff000) >> 12);
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lo = 0x000fff80 | ((value & 0x00000fff) << 20);
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_wrmsr(GLIU_MSR_REG(GLIU_IOD_BM1), hi, lo);
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}
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break;
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case PCI_ACC_INT_REG:
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_rdmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), &hi, &lo);
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/* disable all the usb interrupt in PIC */
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lo &= ~(0xf << PIC_YSEL_LOW_ACC_SHIFT);
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if (value) /* enable all the acc interrupt in PIC */
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lo |= (CS5536_ACC_INTR << PIC_YSEL_LOW_ACC_SHIFT);
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_wrmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), hi, lo);
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break;
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default:
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break;
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}
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}
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u32 pci_acc_read_reg(int reg)
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{
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u32 hi, lo;
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u32 conf_data = 0;
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switch (reg) {
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case PCI_VENDOR_ID:
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conf_data =
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CFG_PCI_VENDOR_ID(CS5536_ACC_DEVICE_ID, CS5536_VENDOR_ID);
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break;
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case PCI_COMMAND:
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_rdmsr(GLIU_MSR_REG(GLIU_IOD_BM1), &hi, &lo);
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if (((lo & 0xfff00000) || (hi & 0x000000ff))
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&& ((hi & 0xf0000000) == 0xa0000000))
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conf_data |= PCI_COMMAND_IO;
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_rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo);
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if ((lo & 0x300) == 0x300)
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conf_data |= PCI_COMMAND_MASTER;
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break;
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case PCI_STATUS:
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conf_data |= PCI_STATUS_66MHZ;
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conf_data |= PCI_STATUS_FAST_BACK;
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_rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
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if (lo & SB_PARE_ERR_FLAG)
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conf_data |= PCI_STATUS_PARITY;
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conf_data |= PCI_STATUS_DEVSEL_MEDIUM;
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break;
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case PCI_CLASS_REVISION:
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_rdmsr(ACC_MSR_REG(ACC_CAP), &hi, &lo);
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conf_data = lo & 0x000000ff;
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conf_data |= (CS5536_ACC_CLASS_CODE << 8);
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break;
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case PCI_CACHE_LINE_SIZE:
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conf_data =
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CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE,
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PCI_NORMAL_LATENCY_TIMER);
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break;
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case PCI_BAR0_REG:
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_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
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if (lo & SOFT_BAR_ACC_FLAG) {
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conf_data = CS5536_ACC_RANGE |
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PCI_BASE_ADDRESS_SPACE_IO;
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lo &= ~SOFT_BAR_ACC_FLAG;
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_wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
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} else {
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_rdmsr(GLIU_MSR_REG(GLIU_IOD_BM1), &hi, &lo);
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conf_data = (hi & 0x000000ff) << 12;
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conf_data |= (lo & 0xfff00000) >> 20;
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conf_data |= 0x01;
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conf_data &= ~0x02;
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}
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break;
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case PCI_CARDBUS_CIS:
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conf_data = PCI_CARDBUS_CIS_POINTER;
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break;
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case PCI_SUBSYSTEM_VENDOR_ID:
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conf_data =
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CFG_PCI_VENDOR_ID(CS5536_ACC_SUB_ID, CS5536_SUB_VENDOR_ID);
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break;
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case PCI_ROM_ADDRESS:
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conf_data = PCI_EXPANSION_ROM_BAR;
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break;
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case PCI_CAPABILITY_LIST:
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conf_data = PCI_CAPLIST_USB_POINTER;
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break;
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case PCI_INTERRUPT_LINE:
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conf_data =
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CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_ACC_INTR);
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break;
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default:
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break;
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}
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return conf_data;
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}
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