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562f818dea
This simple patch activates SMP for mt6589 by adding the missing "enable-method" property. After applying this patch kernel log indicates all cores are brought up: [ 0.070122] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000 [ 0.071652] Setting up static identity map for 0x80100000 - 0x80100054 [ 0.072711] rcu: Hierarchical SRCU implementation. [ 0.073853] smp: Bringing up secondary CPUs ... [ 0.133675] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001 [ 0.193675] CPU2: thread -1, cpu 2, socket 0, mpidr 80000002 [ 0.253675] CPU3: thread -1, cpu 3, socket 0, mpidr 80000003 [ 0.253818] smp: Brought up 1 node, 4 CPUs [ 0.256930] SMP: Total of 4 processors activated (7982.28 BogoMIPS). [ 0.257855] CPU: All CPU(s) started in SVC mode. Before this change CPU cores 1-3 didn't start and the following lines were in kernel log: [ 0.070126] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000 [ 0.071640] Setting up static identity map for 0x80100000 - 0x80100054 [ 0.072706] rcu: Hierarchical SRCU implementation. [ 0.073850] smp: Bringing up secondary CPUs ... [ 0.076052] smp: Brought up 1 node, 1 CPU [ 0.076678] SMP: Total of 1 processors activated (2000.48 BogoMIPS). [ 0.077603] CPU: All CPU(s) started in SVC mode. Signed-off-by: Boris Lysov <arzamas-16@mail.ee> Link: https://lore.kernel.org/r/20210314023735.052d2d35@pc Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
141 lines
2.9 KiB
Text
141 lines
2.9 KiB
Text
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2014 MundoReader S.L.
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* Author: Matthias Brugger <matthias.bgg@gmail.com>
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*
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*/
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "mediatek,mt6589";
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interrupt-parent = <&sysirq>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "mediatek,mt6589-smp";
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x0>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x1>;
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};
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cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x2>;
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};
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cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x3>;
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};
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};
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clocks {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges;
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system_clk: dummy13m {
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compatible = "fixed-clock";
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clock-frequency = <13000000>;
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#clock-cells = <0>;
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};
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rtc_clk: dummy32k {
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compatible = "fixed-clock";
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clock-frequency = <32000>;
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#clock-cells = <0>;
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};
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uart_clk: dummy26m {
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compatible = "fixed-clock";
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clock-frequency = <26000000>;
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#clock-cells = <0>;
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};
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges;
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timer: timer@10008000 {
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compatible = "mediatek,mt6577-timer";
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reg = <0x10008000 0x80>;
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interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&system_clk>, <&rtc_clk>;
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clock-names = "system-clk", "rtc-clk";
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};
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sysirq: interrupt-controller@10200100 {
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compatible = "mediatek,mt6589-sysirq",
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"mediatek,mt6577-sysirq";
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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reg = <0x10200100 0x1c>;
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};
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gic: interrupt-controller@10211000 {
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compatible = "arm,cortex-a7-gic";
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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reg = <0x10211000 0x1000>,
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<0x10212000 0x2000>,
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<0x10214000 0x2000>,
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<0x10216000 0x2000>;
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};
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uart0: serial@11006000 {
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compatible = "mediatek,mt6577-uart";
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reg = <0x11006000 0x400>;
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interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&uart_clk>;
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status = "disabled";
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};
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uart1: serial@11007000 {
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compatible = "mediatek,mt6577-uart";
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reg = <0x11007000 0x400>;
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interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&uart_clk>;
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status = "disabled";
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};
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uart2: serial@11008000 {
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compatible = "mediatek,mt6577-uart";
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reg = <0x11008000 0x400>;
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interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&uart_clk>;
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status = "disabled";
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};
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uart3: serial@11009000 {
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compatible = "mediatek,mt6577-uart";
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reg = <0x11009000 0x400>;
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interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&uart_clk>;
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status = "disabled";
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};
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wdt: watchdog@10000000 {
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compatible = "mediatek,mt6589-wdt";
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reg = <0x10000000 0x44>;
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};
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};
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};
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