[fix][uart][spi] fix uart and spi device oflag in device control dma

This commit is contained in:
jzlv 2021-07-12 16:59:29 +08:00
parent 98043ff151
commit 006e4bface
2 changed files with 40 additions and 32 deletions

View file

@ -201,6 +201,7 @@ int spi_control(struct device *dev, int cmd, void *args)
uint32_t tmpVal = BL_RD_REG(SPI_BASE + spi_device->id * 0x100, SPI_FIFO_CONFIG_0);
tmpVal = BL_CLR_REG_BIT(tmpVal, SPI_DMA_TX_EN);
BL_WR_REG(SPI_BASE + spi_device->id * 0x100, SPI_FIFO_CONFIG_0, tmpVal);
dev->oflag &= ~DEVICE_OFLAG_DMA_TX;
break;
}
@ -208,6 +209,7 @@ int spi_control(struct device *dev, int cmd, void *args)
uint32_t tmpVal = BL_RD_REG(SPI_BASE + spi_device->id * 0x100, SPI_FIFO_CONFIG_0);
tmpVal = BL_CLR_REG_BIT(tmpVal, SPI_DMA_RX_EN);
BL_WR_REG(SPI_BASE + spi_device->id * 0x100, SPI_FIFO_CONFIG_0, tmpVal);
dev->oflag &= ~DEVICE_OFLAG_DMA_RX;
break;
}
@ -215,6 +217,7 @@ int spi_control(struct device *dev, int cmd, void *args)
uint32_t tmpVal = BL_RD_REG(SPI_BASE + spi_device->id * 0x100, SPI_FIFO_CONFIG_0);
tmpVal = BL_SET_REG_BIT(tmpVal, SPI_DMA_TX_EN);
BL_WR_REG(SPI_BASE + spi_device->id * 0x100, SPI_FIFO_CONFIG_0, tmpVal);
dev->oflag |= DEVICE_OFLAG_DMA_TX;
break;
}
@ -222,6 +225,7 @@ int spi_control(struct device *dev, int cmd, void *args)
uint32_t tmpVal = BL_RD_REG(SPI_BASE + spi_device->id * 0x100, SPI_FIFO_CONFIG_0);
tmpVal = BL_SET_REG_BIT(tmpVal, SPI_DMA_RX_EN);
BL_WR_REG(SPI_BASE + spi_device->id * 0x100, SPI_FIFO_CONFIG_0, tmpVal);
dev->oflag |= DEVICE_OFLAG_DMA_RX;
break;
}
@ -258,34 +262,34 @@ int spi_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t siz
return 0;
} else {
if (spi_device->datasize == SPI_DATASIZE_32BIT) {
SPI_Send_32bits(spi_device->id, (uint32_t *)buffer, size, SPI_TIMEOUT_DISABLE);
return 0;
} else if (spi_device->datasize == SPI_DATASIZE_24BIT) {
} else if (spi_device->datasize == SPI_DATASIZE_16BIT) {
uint32_t residue32 = size % 2;
uint32_t trade32 = size / 2;
SPI_Send_32bits(spi_device->id, (uint32_t *)buffer, trade32, SPI_TIMEOUT_DISABLE);
buffer += sizeof(uint32_t) * trade32;
SPI_Send_16bits(spi_device->id, (uint16_t *)buffer, residue32, SPI_TIMEOUT_DISABLE);
return 0;
} else if (spi_device->datasize == SPI_DATASIZE_8BIT) {
uint32_t residue32 = size % 4;
uint32_t trade32 = size / 4;
SPI_Send_32bits(spi_device->id, (uint32_t *)buffer, trade32, SPI_TIMEOUT_DISABLE);
buffer += sizeof(uint32_t) * trade32;
// if (spi_device->datasize == SPI_DATASIZE_32BIT) {
// SPI_Send_32bits(spi_device->id, (uint32_t *)buffer, size, SPI_TIMEOUT_DISABLE);
// return 0;
// } else if (spi_device->datasize == SPI_DATASIZE_24BIT) {
// } else if (spi_device->datasize == SPI_DATASIZE_16BIT) {
// uint32_t residue32 = size % 2;
// uint32_t trade32 = size / 2;
// SPI_Send_32bits(spi_device->id, (uint32_t *)buffer, trade32, SPI_TIMEOUT_DISABLE);
// buffer += sizeof(uint32_t) * trade32;
// SPI_Send_16bits(spi_device->id, (uint16_t *)buffer, residue32, SPI_TIMEOUT_DISABLE);
// return 0;
// } else if (spi_device->datasize == SPI_DATASIZE_8BIT) {
// uint32_t residue32 = size % 4;
// uint32_t trade32 = size / 4;
// SPI_Send_32bits(spi_device->id, (uint32_t *)buffer, trade32, SPI_TIMEOUT_DISABLE);
// buffer += sizeof(uint32_t) * trade32;
uint32_t residue16 = residue32 % 2;
uint32_t trade16 = residue32 / 2;
SPI_Send_16bits(spi_device->id, (uint16_t *)buffer, trade16, SPI_TIMEOUT_DISABLE);
buffer += sizeof(uint16_t) * trade16;
// uint32_t residue16 = residue32 % 2;
// uint32_t trade16 = residue32 / 2;
// SPI_Send_16bits(spi_device->id, (uint16_t *)buffer, trade16, SPI_TIMEOUT_DISABLE);
// buffer += sizeof(uint16_t) * trade16;
SPI_Send_8bits(spi_device->id, (uint8_t *)buffer, residue16, SPI_TIMEOUT_DISABLE);
return 0;
}
// SPI_Send_8bits(spi_device->id, (uint8_t *)buffer, residue16, SPI_TIMEOUT_DISABLE);
// return 0;
// }
return -2;
}
return -2;
}
/**
* @brief
@ -314,9 +318,8 @@ int spi_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size)
return 0;
} else {
return -2;
}
return -2;
}
/**
* @brief

View file

@ -223,24 +223,28 @@ int uart_control(struct device *dev, int cmd, void *args)
uint32_t tmpVal = BL_RD_REG(UART0_BASE + uart_device->id * 0x100, UART_FIFO_CONFIG_0);
tmpVal = BL_CLR_REG_BIT(tmpVal, UART_DMA_TX_EN);
BL_WR_REG(UART0_BASE + uart_device->id * 0x100, UART_FIFO_CONFIG_0, tmpVal);
dev->oflag &= ~DEVICE_OFLAG_DMA_TX;
break;
}
case DEVICE_CTRL_RX_DMA_SUSPEND: {
uint32_t tmpVal = BL_RD_REG(UART0_BASE + uart_device->id * 0x100, UART_FIFO_CONFIG_0);
tmpVal = BL_CLR_REG_BIT(tmpVal, UART_DMA_RX_EN);
BL_WR_REG(UART0_BASE + uart_device->id * 0x100, UART_FIFO_CONFIG_0, tmpVal);
dev->oflag &= ~DEVICE_OFLAG_DMA_RX;
break;
}
case DEVICE_CTRL_TX_DMA_RESUME: {
uint32_t tmpVal = BL_RD_REG(UART0_BASE + uart_device->id * 0x100, UART_FIFO_CONFIG_0);
tmpVal = BL_SET_REG_BIT(tmpVal, UART_DMA_TX_EN);
BL_WR_REG(UART0_BASE + uart_device->id * 0x100, UART_FIFO_CONFIG_0, tmpVal);
dev->oflag |= DEVICE_OFLAG_DMA_TX;
break;
}
case DEVICE_CTRL_RX_DMA_RESUME: {
uint32_t tmpVal = BL_RD_REG(UART0_BASE + uart_device->id * 0x100, UART_FIFO_CONFIG_0);
tmpVal = BL_SET_REG_BIT(tmpVal, UART_DMA_RX_EN);
BL_WR_REG(UART0_BASE + uart_device->id * 0x100, UART_FIFO_CONFIG_0, tmpVal);
dev->oflag |= DEVICE_OFLAG_DMA_RX;
break;
}
case DEVICE_CTRL_UART_GET_TX_FIFO /* constant-expression */:
@ -278,10 +282,10 @@ int uart_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t si
dma_channel_start(dma_ch);
}
return 0;
} else if (dev->oflag & DEVICE_OFLAG_STREAM_TX) {
return UART_SendData(uart_device->id, (uint8_t *)buffer, size);
} else if (dev->oflag & DEVICE_OFLAG_INT_TX) {
return -2;
} else
return -1;
return UART_SendData(uart_device->id, (uint8_t *)buffer, size);
}
/**
* @brief
@ -308,14 +312,15 @@ int uart_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size)
dma_channel_start(dma_ch);
}
return 0;
} else if (dev->oflag & DEVICE_OFLAG_STREAM_RX) {
} else if (dev->oflag & DEVICE_OFLAG_INT_RX) {
return -2;
} else {
uint32_t rx_len = 0;
while (rx_len < size) {
rx_len += UART_ReceiveData(uart_device->id, (uint8_t *)buffer + rx_len, size - rx_len);
}
return 0;
}
return -1;
}
/**
* @brief