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[refactor][boot2_iap] refactor bl702 hal boot2 iap

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This commit is contained in:
qqwang 2021-08-05 17:37:53 +08:00
parent d32c3358a5
commit 07924c6222
2 changed files with 85 additions and 65 deletions
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23
drivers/bl702_driver/hal_drv/inc/hal_boot2.h
View file

@ -50,6 +50,7 @@
#define BL_FLASH_XIP_BASE BL702_FLASH_XIP_BASE
#define FLASH_NOT_DETECT 0x10
#define HAL_BOOT2_SUPPORT_DECOMPRESS 0 /* 1 support decompress, 0 not support */
typedef struct
{
@ -60,7 +61,7 @@ typedef struct
uint8_t chip_id[8];
uint8_t pk_hash_cpu0[HAL_EFUSE_PK_HASH_SIZE];
uint8_t pk_hash_cpu1[HAL_EFUSE_PK_HASH_SIZE];
} boot_efuse_hw_config;
} boot2_efuse_hw_config;
typedef struct
{
@ -89,13 +90,15 @@ typedef struct
} hal_flash_config;
uint32_t hal_boot2_custom(void);
void hal_reset_sec_eng(void);
void hal_sw_system_reset(void);
int32_t hal_pll_init(hal_pll_config *pll_cfg);
void hal_hbn_set_status_flag(uint32_t flag);
uint32_t hal_hbn_get_status_flag(void);
uint8_t *hal_hbn_get_user_specified_fw(void);
void hal_hbn_clr_user_specified_fw(void);
void efuse_get_boot2_cfg(boot_efuse_hw_config *g_efuse_cfg);
int32_t flash_get_clk_cfg(hal_pll_config *cfg);
void hal_boot2_reset_sec_eng(void);
void hal_boot2_sw_system_reset(void);
void hal_boot2_set_psmode_status(uint32_t flag);
uint32_t hal_boot2_get_psmode_status(void);
uint8_t *hal_boot2_get_user_fw(void);
void hal_boot2_clr_user_fw(void);
void hal_boot2_get_efuse_cfg(boot2_efuse_hw_config *g_efuse_cfg);
int32_t hal_boot2_get_clk_cfg(hal_pll_config *cfg);
void hal_boot2_sboot_finish(void);
void hal_boot2_uart_gpio_init(void);
void hal_boot2_debug_uart_gpio_init(void);
#endif

127
drivers/bl702_driver/hal_drv/src/hal_boot2.c
View file

@ -1,8 +1,12 @@
#include "hal_boot2.h"
#include "hal_flash.h"
#include "bl702_ef_ctrl.h"
#include "bl702_hbn.h"
#include "bl702_glb.h"
#include "bl702_xip_sflash.h"
#include "tzc_sec_reg.h"
#include "hal_gpio.h"
/**
* @brief boot2 custom
*
@ -14,46 +18,7 @@ uint32_t hal_boot2_custom(void)
return 0;
}
/**
* @brief reset sec eng clock
*
* @return
*/
void hal_reset_sec_eng(void)
{
GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_SEC);
}
/**
* @brief system soft reset
*
* @return
*/
void hal_sw_system_reset(void)
{
GLB_SW_System_Reset();
}
/**
* @brief system soft reset
*
* @param pll_cfg
* @return
*/
int32_t ATTR_TCM_SECTION hal_pll_init(hal_pll_config *pll_cfg)
{
/* PLL config */
if (pll_cfg->cfg.xtal_type > 0) {
/* use xtal in aon to config PLL */
GLB_Set_System_CLK(pll_cfg->cfg.xtal_type, pll_cfg->cfg.pll_clk);
GLB_Set_System_CLK_Div(pll_cfg->cfg.hclk_div, pll_cfg->cfg.bclk_div);
GLB_Set_SF_CLK(1, (GLB_SFLASH_CLK_Type)pll_cfg->cfg.flash_clk_type, pll_cfg->cfg.flash_clk_div);
} else {
return -1;
}
return 0;
}
/**
* @brief get efuse Boot2 config
@ -63,7 +28,7 @@ int32_t ATTR_TCM_SECTION hal_pll_init(hal_pll_config *pll_cfg)
* @param
* @return None
*/
void efuse_get_boot2_cfg(boot_efuse_hw_config *g_efuse_cfg)
void hal_boot2_get_efuse_cfg(boot2_efuse_hw_config *g_efuse_cfg)
{
uint32_t tmp;
@ -81,6 +46,26 @@ void efuse_get_boot2_cfg(boot_efuse_hw_config *g_efuse_cfg)
GLB_Set_System_CLK_Div(0, 1);
HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_DLL);
}
/**
* @brief reset sec eng clock
*
* @return
*/
void hal_boot2_reset_sec_eng(void)
{
GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_SEC);
}
/**
* @brief system soft reset
*
* @return
*/
void hal_boot2_sw_system_reset(void)
{
GLB_SW_System_Reset();
}
/**
* @brief
@ -90,7 +75,7 @@ void efuse_get_boot2_cfg(boot_efuse_hw_config *g_efuse_cfg)
* @param
* @return
*/
void hal_hbn_set_status_flag(uint32_t flag)
void hal_boot2_set_psmode_status(uint32_t flag)
{
HBN_Set_Status_Flag(flag);
}
@ -103,7 +88,7 @@ void hal_hbn_set_status_flag(uint32_t flag)
* @param
* @return flag
*/
uint32_t hal_hbn_get_status_flag(void)
uint32_t hal_boot2_get_psmode_status(void)
{
return HBN_Get_Status_Flag();
}
@ -116,7 +101,7 @@ uint32_t hal_hbn_get_status_flag(void)
* @param
* @return user define flag
*/
uint8_t *hal_hbn_get_user_specified_fw(void)
uint8_t *hal_boot2_get_user_fw(void)
{
return (uint8_t *)(HBN_BASE + HBN_RSV0_OFFSET);
}
@ -129,21 +114,53 @@ uint8_t *hal_hbn_get_user_specified_fw(void)
* @param
* @return
*/
void hal_hbn_clr_user_specified_fw(void)
void hal_boot2_clr_user_fw(void)
{
uint32_t *p = (uint32_t *)(HBN_BASE + HBN_RSV0_OFFSET);
*p = 0;
}
/**
* @brief flash_get_clk_cfg
*
* @return 0
*/
int32_t ATTR_TCM_SECTION flash_get_clk_cfg(hal_pll_config *cfg)
{
L1C_Cache_Flush(0xf);
XIP_SFlash_Read_Via_Cache_Need_Lock(8 + sizeof(hal_flash_config) + BL_FLASH_XIP_BASE, (uint8_t *)cfg, sizeof(hal_pll_config));
L1C_Cache_Flush(0x0);
return 0;
/**
* @brief hal_boot2_sboot_finish
*
* @return
*/
void ATTR_TCM_SECTION hal_boot2_sboot_finish(void)
{
uint32_t tmp_val;
tmp_val = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_CTRL);
tmp_val = BL_SET_REG_BITS_VAL(tmp_val, TZC_SEC_TZC_SBOOT_DONE, 0xf);
BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_CTRL, tmp_val);
}
/**
* @brief hal_boot2_pll_init
*
* @return
*/
void hal_boot2_uart_gpio_init(void)
{
GLB_GPIO_Type gpios[]={GPIO_PIN_14,GPIO_PIN_15};
GLB_GPIO_Func_Init(GPIO_FUN_UART,gpios,2);
GLB_UART_Fun_Sel((GPIO_PIN_14 % 8), GLB_UART_SIG_FUN_UART0_TXD);// GPIO_FUN_UART1_TX
GLB_UART_Fun_Sel((GPIO_PIN_15 % 8), GLB_UART_SIG_FUN_UART0_RXD);
}
/**
* @brief hal_boot2_pll_init
*
* @return
*/
void hal_boot2_debug_uart_gpio_init(void)
{
GLB_GPIO_Type gpios[]={GPIO_PIN_17};
GLB_GPIO_Func_Init(GPIO_FUN_UART,gpios,1);
GLB_UART_Fun_Sel((GPIO_PIN_17 % 8), GLB_UART_SIG_FUN_UART1_TXD);
}