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[update][soc] update efuse api, add some drivers for boot2

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This commit is contained in:
jzlv 2022-12-21 20:25:11 +08:00
parent a77b0dc866
commit 0ea925c313
55 changed files with 6729 additions and 961 deletions
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1
drivers/soc/bl602/CMakeLists.txt
View file

@ -29,7 +29,6 @@ sdk_library_add_sources(bl602_std/src/bl602_xip_sflash_ext.c)
sdk_library_add_sources(port/bl602_clock.c)
sdk_library_add_sources(port/bl602_flash.c)
sdk_library_add_sources(port/bl602_efuse.c)
sdk_add_include_directories(
bl602_std/include

16
drivers/soc/bl602/bl602_std/include/bl602_ef_cfg.h
View file

@ -1,6 +1,6 @@
/**
******************************************************************************
* @file bl602_ef_ctrl.h
* @file bl602_ef_cfg.h
* @version V1.0
* @date
* @brief This file is the standard driver header file
@ -36,8 +36,8 @@
#ifndef __BL602_EF_CFG_H__
#define __BL602_EF_CFG_H__
#include "ef_ctrl_reg.h"
#include "bl602_common.h"
#include "bflb_ef_ctrl.h"
/** @addtogroup BL602_Peripheral_Driver
* @{
@ -55,12 +55,12 @@
* @brief Efuse Ctrl key slot type definition
*/
typedef struct {
uint32_t rsvd : 19; /*!< Reserved */
uint32_t rsvd_18_0 : 19; /*!< Reserved */
uint32_t chip_ver : 3; /*!< chip revision */
uint32_t customerID : 2; /*!< Efuse customer ID information */
uint32_t rsvd_info : 3; /*!< Efuse device info extension: 1:BL602C, 2:BL602L, 3:BL602E */
uint32_t memoryInfo : 2; /*!< Efuse memory info 0:no memory, 1:1MB flash, 2:2MB flash */
uint32_t coreInfo : 1; /*!< Efuse reserved */
uint32_t rsvd_23_22 : 2; /*!< Reserved */
uint32_t extInfo : 3; /*!< Efuse device info extension: 1:BL602C, 2:BL602L, 3:BL602E, 4:POS/AT */
uint32_t memoryInfo : 2; /*!< Efuse memory info 0:no memory, 1:1MB flash, 2:2MB flash, 3:4MB flash */
uint32_t rsvd_29 : 1; /*!< Efuse reserved */
uint32_t mcuInfo : 1; /*!< Efuse mcu info 0:wifi, 1:mcu */
uint32_t pinInfo : 1; /*!< Efuse pin info 0:QFN32, 1:QFN40 */
} bflb_efuse_device_info_type;
@ -86,7 +86,7 @@ typedef struct {
void bflb_efuse_switch_cpu_clock_save(void);
void bflb_efuse_switch_cpu_clock_restore(void);
void bflb_ef_ctrl_get_device_info(bflb_efuse_device_info_type *deviceInfo);
uint32_t bflb_ef_ctrl_get_common_trim_list(const bflb_ef_ctrl_com_trim_cfg **trim_list);
uint32_t bflb_ef_ctrl_get_common_trim_list(const bflb_ef_ctrl_com_trim_cfg_t **trim_list);
/*@} end of group EF_CTRL_Public_Functions */

84
drivers/soc/bl602/bl602_std/include/bl602_tzc_sec.h Normal file
View file

@ -0,0 +1,84 @@
/**
******************************************************************************
* @file bl602_tzc_sec.h
* @version V1.0
* @date
* @brief This file is the standard driver header file
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __BL602_TZC_SEC_H__
#define __BL602_TZC_SEC_H__
#include "tzc_sec_reg.h"
#include "bl602_common.h"
/** @addtogroup BL602_Peripheral_Driver
* @{
*/
/** @addtogroup TZC_SEC
* @{
*/
/** @defgroup TZC_SEC_Public_Types
* @{
*/
/*@} end of group TZC_SEC_Public_Types */
/** @defgroup TZC_SEC_Public_Constants
* @{
*/
/*@} end of group TZC_SEC_Public_Constants */
/** @defgroup TZC_SEC_Public_Macros
* @{
*/
/*@} end of group TZC_SEC_Public_Macros */
/** @defgroup TZC_SEC_Public_Functions
* @{
*/
void TZC_Sboot_Set(uint8_t Val);
void TZC_Set_Rom0_R0_Protect(uint32_t start, uint32_t length);
void TZC_Set_Rom0_R1_Protect(uint32_t start, uint32_t length);
void TZC_Set_Rom1_R0_Protect(uint32_t start, uint32_t length);
void TZC_Set_Rom1_R1_Protect(uint32_t start, uint32_t length);
/*@} end of group TZC_SEC_Public_Functions */
/*@} end of group TZC_SEC */
/*@} end of group BL602_Peripheral_Driver */
#endif /* __BL602_TZC_SEC_H__ */

762
drivers/soc/bl602/bl602_std/include/hardware/ef_data_reg.h Normal file
View file

@ -0,0 +1,762 @@
/**
******************************************************************************
* @file EF_DATA_reg.h
* @version V1.2
* @date 2019-11-22
* @brief This file is the description of.IP register
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2019 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __EF_DATA_REG_H__
#define __EF_DATA_REG_H__
#include "bl602.h"
/* 0x0 : ef_cfg_0 */
#define EF_DATA_EF_CFG_0_OFFSET (0x0)
#define EF_DATA_EF_SF_AES_MODE EF_DATA_EF_SF_AES_MODE
#define EF_DATA_EF_SF_AES_MODE_POS (0U)
#define EF_DATA_EF_SF_AES_MODE_LEN (2U)
#define EF_DATA_EF_SF_AES_MODE_MSK (((1U << EF_DATA_EF_SF_AES_MODE_LEN) - 1) << EF_DATA_EF_SF_AES_MODE_POS)
#define EF_DATA_EF_SF_AES_MODE_UMSK (~(((1U << EF_DATA_EF_SF_AES_MODE_LEN) - 1) << EF_DATA_EF_SF_AES_MODE_POS))
#define EF_DATA_EF_SBOOT_SIGN_MODE EF_DATA_EF_SBOOT_SIGN_MODE
#define EF_DATA_EF_SBOOT_SIGN_MODE_POS (2U)
#define EF_DATA_EF_SBOOT_SIGN_MODE_LEN (2U)
#define EF_DATA_EF_SBOOT_SIGN_MODE_MSK (((1U << EF_DATA_EF_SBOOT_SIGN_MODE_LEN) - 1) << EF_DATA_EF_SBOOT_SIGN_MODE_POS)
#define EF_DATA_EF_SBOOT_SIGN_MODE_UMSK (~(((1U << EF_DATA_EF_SBOOT_SIGN_MODE_LEN) - 1) << EF_DATA_EF_SBOOT_SIGN_MODE_POS))
#define EF_DATA_EF_SBOOT_EN EF_DATA_EF_SBOOT_EN
#define EF_DATA_EF_SBOOT_EN_POS (4U)
#define EF_DATA_EF_SBOOT_EN_LEN (2U)
#define EF_DATA_EF_SBOOT_EN_MSK (((1U << EF_DATA_EF_SBOOT_EN_LEN) - 1) << EF_DATA_EF_SBOOT_EN_POS)
#define EF_DATA_EF_SBOOT_EN_UMSK (~(((1U << EF_DATA_EF_SBOOT_EN_LEN) - 1) << EF_DATA_EF_SBOOT_EN_POS))
#define EF_DATA_EF_CPU0_ENC_EN EF_DATA_EF_CPU0_ENC_EN
#define EF_DATA_EF_CPU0_ENC_EN_POS (7U)
#define EF_DATA_EF_CPU0_ENC_EN_LEN (1U)
#define EF_DATA_EF_CPU0_ENC_EN_MSK (((1U << EF_DATA_EF_CPU0_ENC_EN_LEN) - 1) << EF_DATA_EF_CPU0_ENC_EN_POS)
#define EF_DATA_EF_CPU0_ENC_EN_UMSK (~(((1U << EF_DATA_EF_CPU0_ENC_EN_LEN) - 1) << EF_DATA_EF_CPU0_ENC_EN_POS))
#define EF_DATA_EF_TRIM_EN EF_DATA_EF_TRIM_EN
#define EF_DATA_EF_TRIM_EN_POS (12U)
#define EF_DATA_EF_TRIM_EN_LEN (1U)
#define EF_DATA_EF_TRIM_EN_MSK (((1U << EF_DATA_EF_TRIM_EN_LEN) - 1) << EF_DATA_EF_TRIM_EN_POS)
#define EF_DATA_EF_TRIM_EN_UMSK (~(((1U << EF_DATA_EF_TRIM_EN_LEN) - 1) << EF_DATA_EF_TRIM_EN_POS))
#define EF_DATA_EF_NO_HD_BOOT_EN EF_DATA_EF_NO_HD_BOOT_EN
#define EF_DATA_EF_NO_HD_BOOT_EN_POS (13U)
#define EF_DATA_EF_NO_HD_BOOT_EN_LEN (1U)
#define EF_DATA_EF_NO_HD_BOOT_EN_MSK (((1U << EF_DATA_EF_NO_HD_BOOT_EN_LEN) - 1) << EF_DATA_EF_NO_HD_BOOT_EN_POS)
#define EF_DATA_EF_NO_HD_BOOT_EN_UMSK (~(((1U << EF_DATA_EF_NO_HD_BOOT_EN_LEN) - 1) << EF_DATA_EF_NO_HD_BOOT_EN_POS))
#define EF_DATA_EF_0_KEY_ENC_EN EF_DATA_EF_0_KEY_ENC_EN
#define EF_DATA_EF_0_KEY_ENC_EN_POS (17U)
#define EF_DATA_EF_0_KEY_ENC_EN_LEN (1U)
#define EF_DATA_EF_0_KEY_ENC_EN_MSK (((1U << EF_DATA_EF_0_KEY_ENC_EN_LEN) - 1) << EF_DATA_EF_0_KEY_ENC_EN_POS)
#define EF_DATA_EF_0_KEY_ENC_EN_UMSK (~(((1U << EF_DATA_EF_0_KEY_ENC_EN_LEN) - 1) << EF_DATA_EF_0_KEY_ENC_EN_POS))
#define EF_DATA_EF_DBG_JTAG_0_DIS EF_DATA_EF_DBG_JTAG_0_DIS
#define EF_DATA_EF_DBG_JTAG_0_DIS_POS (26U)
#define EF_DATA_EF_DBG_JTAG_0_DIS_LEN (2U)
#define EF_DATA_EF_DBG_JTAG_0_DIS_MSK (((1U << EF_DATA_EF_DBG_JTAG_0_DIS_LEN) - 1) << EF_DATA_EF_DBG_JTAG_0_DIS_POS)
#define EF_DATA_EF_DBG_JTAG_0_DIS_UMSK (~(((1U << EF_DATA_EF_DBG_JTAG_0_DIS_LEN) - 1) << EF_DATA_EF_DBG_JTAG_0_DIS_POS))
#define EF_DATA_EF_DBG_MODE EF_DATA_EF_DBG_MODE
#define EF_DATA_EF_DBG_MODE_POS (28U)
#define EF_DATA_EF_DBG_MODE_LEN (4U)
#define EF_DATA_EF_DBG_MODE_MSK (((1U << EF_DATA_EF_DBG_MODE_LEN) - 1) << EF_DATA_EF_DBG_MODE_POS)
#define EF_DATA_EF_DBG_MODE_UMSK (~(((1U << EF_DATA_EF_DBG_MODE_LEN) - 1) << EF_DATA_EF_DBG_MODE_POS))
/* 0x4 : ef_dbg_pwd_low */
#define EF_DATA_EF_DBG_PWD_LOW_OFFSET (0x4)
#define EF_DATA_EF_DBG_PWD_LOW EF_DATA_EF_DBG_PWD_LOW
#define EF_DATA_EF_DBG_PWD_LOW_POS (0U)
#define EF_DATA_EF_DBG_PWD_LOW_LEN (32U)
#define EF_DATA_EF_DBG_PWD_LOW_MSK (((1U << EF_DATA_EF_DBG_PWD_LOW_LEN) - 1) << EF_DATA_EF_DBG_PWD_LOW_POS)
#define EF_DATA_EF_DBG_PWD_LOW_UMSK (~(((1U << EF_DATA_EF_DBG_PWD_LOW_LEN) - 1) << EF_DATA_EF_DBG_PWD_LOW_POS))
/* 0x8 : ef_dbg_pwd_high */
#define EF_DATA_EF_DBG_PWD_HIGH_OFFSET (0x8)
#define EF_DATA_EF_DBG_PWD_HIGH EF_DATA_EF_DBG_PWD_HIGH
#define EF_DATA_EF_DBG_PWD_HIGH_POS (0U)
#define EF_DATA_EF_DBG_PWD_HIGH_LEN (32U)
#define EF_DATA_EF_DBG_PWD_HIGH_MSK (((1U << EF_DATA_EF_DBG_PWD_HIGH_LEN) - 1) << EF_DATA_EF_DBG_PWD_HIGH_POS)
#define EF_DATA_EF_DBG_PWD_HIGH_UMSK (~(((1U << EF_DATA_EF_DBG_PWD_HIGH_LEN) - 1) << EF_DATA_EF_DBG_PWD_HIGH_POS))
/* 0xC : ef_ana_trim_0 */
#define EF_DATA_EF_ANA_TRIM_0_OFFSET (0xC)
#define EF_DATA_EF_ANA_TRIM_0 EF_DATA_EF_ANA_TRIM_0
#define EF_DATA_EF_ANA_TRIM_0_POS (0U)
#define EF_DATA_EF_ANA_TRIM_0_LEN (32U)
#define EF_DATA_EF_ANA_TRIM_0_MSK (((1U << EF_DATA_EF_ANA_TRIM_0_LEN) - 1) << EF_DATA_EF_ANA_TRIM_0_POS)
#define EF_DATA_EF_ANA_TRIM_0_UMSK (~(((1U << EF_DATA_EF_ANA_TRIM_0_LEN) - 1) << EF_DATA_EF_ANA_TRIM_0_POS))
/* 0x10 : ef_sw_usage_0 */
#define EF_DATA_EF_SW_USAGE_0_OFFSET (0x10)
#define EF_DATA_EF_SW_USAGE_0 EF_DATA_EF_SW_USAGE_0
#define EF_DATA_EF_SW_USAGE_0_POS (0U)
#define EF_DATA_EF_SW_USAGE_0_LEN (32U)
#define EF_DATA_EF_SW_USAGE_0_MSK (((1U << EF_DATA_EF_SW_USAGE_0_LEN) - 1) << EF_DATA_EF_SW_USAGE_0_POS)
#define EF_DATA_EF_SW_USAGE_0_UMSK (~(((1U << EF_DATA_EF_SW_USAGE_0_LEN) - 1) << EF_DATA_EF_SW_USAGE_0_POS))
/* 0x14 : ef_wifi_mac_low */
#define EF_DATA_EF_WIFI_MAC_LOW_OFFSET (0x14)
#define EF_DATA_EF_WIFI_MAC_LOW EF_DATA_EF_WIFI_MAC_LOW
#define EF_DATA_EF_WIFI_MAC_LOW_POS (0U)
#define EF_DATA_EF_WIFI_MAC_LOW_LEN (32U)
#define EF_DATA_EF_WIFI_MAC_LOW_MSK (((1U << EF_DATA_EF_WIFI_MAC_LOW_LEN) - 1) << EF_DATA_EF_WIFI_MAC_LOW_POS)
#define EF_DATA_EF_WIFI_MAC_LOW_UMSK (~(((1U << EF_DATA_EF_WIFI_MAC_LOW_LEN) - 1) << EF_DATA_EF_WIFI_MAC_LOW_POS))
/* 0x18 : ef_wifi_mac_high */
#define EF_DATA_EF_WIFI_MAC_HIGH_OFFSET (0x18)
#define EF_DATA_EF_WIFI_MAC_HIGH EF_DATA_EF_WIFI_MAC_HIGH
#define EF_DATA_EF_WIFI_MAC_HIGH_POS (0U)
#define EF_DATA_EF_WIFI_MAC_HIGH_LEN (32U)
#define EF_DATA_EF_WIFI_MAC_HIGH_MSK (((1U << EF_DATA_EF_WIFI_MAC_HIGH_LEN) - 1) << EF_DATA_EF_WIFI_MAC_HIGH_POS)
#define EF_DATA_EF_WIFI_MAC_HIGH_UMSK (~(((1U << EF_DATA_EF_WIFI_MAC_HIGH_LEN) - 1) << EF_DATA_EF_WIFI_MAC_HIGH_POS))
/* 0x1C : ef_key_slot_0_w0 */
#define EF_DATA_EF_KEY_SLOT_0_W0_OFFSET (0x1C)
#define EF_DATA_EF_KEY_SLOT_0_W0 EF_DATA_EF_KEY_SLOT_0_W0
#define EF_DATA_EF_KEY_SLOT_0_W0_POS (0U)
#define EF_DATA_EF_KEY_SLOT_0_W0_LEN (32U)
#define EF_DATA_EF_KEY_SLOT_0_W0_MSK (((1U << EF_DATA_EF_KEY_SLOT_0_W0_LEN) - 1) << EF_DATA_EF_KEY_SLOT_0_W0_POS)
#define EF_DATA_EF_KEY_SLOT_0_W0_UMSK (~(((1U << EF_DATA_EF_KEY_SLOT_0_W0_LEN) - 1) << EF_DATA_EF_KEY_SLOT_0_W0_POS))
/* 0x20 : ef_key_slot_0_w1 */
#define EF_DATA_EF_KEY_SLOT_0_W1_OFFSET (0x20)
#define EF_DATA_EF_KEY_SLOT_0_W1 EF_DATA_EF_KEY_SLOT_0_W1
#define EF_DATA_EF_KEY_SLOT_0_W1_POS (0U)
#define EF_DATA_EF_KEY_SLOT_0_W1_LEN (32U)
#define EF_DATA_EF_KEY_SLOT_0_W1_MSK (((1U << EF_DATA_EF_KEY_SLOT_0_W1_LEN) - 1) << EF_DATA_EF_KEY_SLOT_0_W1_POS)
#define EF_DATA_EF_KEY_SLOT_0_W1_UMSK (~(((1U << EF_DATA_EF_KEY_SLOT_0_W1_LEN) - 1) << EF_DATA_EF_KEY_SLOT_0_W1_POS))
/* 0x24 : ef_key_slot_0_w2 */
#define EF_DATA_EF_KEY_SLOT_0_W2_OFFSET (0x24)
#define EF_DATA_EF_KEY_SLOT_0_W2 EF_DATA_EF_KEY_SLOT_0_W2
#define EF_DATA_EF_KEY_SLOT_0_W2_POS (0U)
#define EF_DATA_EF_KEY_SLOT_0_W2_LEN (32U)
#define EF_DATA_EF_KEY_SLOT_0_W2_MSK (((1U << EF_DATA_EF_KEY_SLOT_0_W2_LEN) - 1) << EF_DATA_EF_KEY_SLOT_0_W2_POS)
#define EF_DATA_EF_KEY_SLOT_0_W2_UMSK (~(((1U << EF_DATA_EF_KEY_SLOT_0_W2_LEN) - 1) << EF_DATA_EF_KEY_SLOT_0_W2_POS))
/* 0x28 : ef_key_slot_0_w3 */
#define EF_DATA_EF_KEY_SLOT_0_W3_OFFSET (0x28)
#define EF_DATA_EF_KEY_SLOT_0_W3 EF_DATA_EF_KEY_SLOT_0_W3
#define EF_DATA_EF_KEY_SLOT_0_W3_POS (0U)
#define EF_DATA_EF_KEY_SLOT_0_W3_LEN (32U)
#define EF_DATA_EF_KEY_SLOT_0_W3_MSK (((1U << EF_DATA_EF_KEY_SLOT_0_W3_LEN) - 1) << EF_DATA_EF_KEY_SLOT_0_W3_POS)
#define EF_DATA_EF_KEY_SLOT_0_W3_UMSK (~(((1U << EF_DATA_EF_KEY_SLOT_0_W3_LEN) - 1) << EF_DATA_EF_KEY_SLOT_0_W3_POS))
/* 0x2C : ef_key_slot_1_w0 */
#define EF_DATA_EF_KEY_SLOT_1_W0_OFFSET (0x2C)
#define EF_DATA_EF_KEY_SLOT_1_W0 EF_DATA_EF_KEY_SLOT_1_W0
#define EF_DATA_EF_KEY_SLOT_1_W0_POS (0U)
#define EF_DATA_EF_KEY_SLOT_1_W0_LEN (32U)
#define EF_DATA_EF_KEY_SLOT_1_W0_MSK (((1U << EF_DATA_EF_KEY_SLOT_1_W0_LEN) - 1) << EF_DATA_EF_KEY_SLOT_1_W0_POS)
#define EF_DATA_EF_KEY_SLOT_1_W0_UMSK (~(((1U << EF_DATA_EF_KEY_SLOT_1_W0_LEN) - 1) << EF_DATA_EF_KEY_SLOT_1_W0_POS))
/* 0x30 : ef_key_slot_1_w1 */
#define EF_DATA_EF_KEY_SLOT_1_W1_OFFSET (0x30)
#define EF_DATA_EF_KEY_SLOT_1_W1 EF_DATA_EF_KEY_SLOT_1_W1
#define EF_DATA_EF_KEY_SLOT_1_W1_POS (0U)
#define EF_DATA_EF_KEY_SLOT_1_W1_LEN (32U)
#define EF_DATA_EF_KEY_SLOT_1_W1_MSK (((1U << EF_DATA_EF_KEY_SLOT_1_W1_LEN) - 1) << EF_DATA_EF_KEY_SLOT_1_W1_POS)
#define EF_DATA_EF_KEY_SLOT_1_W1_UMSK (~(((1U << EF_DATA_EF_KEY_SLOT_1_W1_LEN) - 1) << EF_DATA_EF_KEY_SLOT_1_W1_POS))
/* 0x34 : ef_key_slot_1_w2 */
#define EF_DATA_EF_KEY_SLOT_1_W2_OFFSET (0x34)
#define EF_DATA_EF_KEY_SLOT_1_W2 EF_DATA_EF_KEY_SLOT_1_W2
#define EF_DATA_EF_KEY_SLOT_1_W2_POS (0U)
#define EF_DATA_EF_KEY_SLOT_1_W2_LEN (32U)
#define EF_DATA_EF_KEY_SLOT_1_W2_MSK (((1U << EF_DATA_EF_KEY_SLOT_1_W2_LEN) - 1) << EF_DATA_EF_KEY_SLOT_1_W2_POS)
#define EF_DATA_EF_KEY_SLOT_1_W2_UMSK (~(((1U << EF_DATA_EF_KEY_SLOT_1_W2_LEN) - 1) << EF_DATA_EF_KEY_SLOT_1_W2_POS))
/* 0x38 : ef_key_slot_1_w3 */
#define EF_DATA_EF_KEY_SLOT_1_W3_OFFSET (0x38)
#define EF_DATA_EF_KEY_SLOT_1_W3 EF_DATA_EF_KEY_SLOT_1_W3
#define EF_DATA_EF_KEY_SLOT_1_W3_POS (0U)
#define EF_DATA_EF_KEY_SLOT_1_W3_LEN (32U)
#define EF_DATA_EF_KEY_SLOT_1_W3_MSK (((1U << EF_DATA_EF_KEY_SLOT_1_W3_LEN) - 1) << EF_DATA_EF_KEY_SLOT_1_W3_POS)
#define EF_DATA_EF_KEY_SLOT_1_W3_UMSK (~(((1U << EF_DATA_EF_KEY_SLOT_1_W3_LEN) - 1) << EF_DATA_EF_KEY_SLOT_1_W3_POS))
/* 0x3C : ef_key_slot_2_w0 */
#define EF_DATA_EF_KEY_SLOT_2_W0_OFFSET (0x3C)
#define EF_DATA_EF_KEY_SLOT_2_W0 EF_DATA_EF_KEY_SLOT_2_W0
#define EF_DATA_EF_KEY_SLOT_2_W0_POS (0U)
#define EF_DATA_EF_KEY_SLOT_2_W0_LEN (32U)
#define EF_DATA_EF_KEY_SLOT_2_W0_MSK (((1U << EF_DATA_EF_KEY_SLOT_2_W0_LEN) - 1) << EF_DATA_EF_KEY_SLOT_2_W0_POS)
#define EF_DATA_EF_KEY_SLOT_2_W0_UMSK (~(((1U << EF_DATA_EF_KEY_SLOT_2_W0_LEN) - 1) << EF_DATA_EF_KEY_SLOT_2_W0_POS))
/* 0x40 : ef_key_slot_2_w1 */
#define EF_DATA_EF_KEY_SLOT_2_W1_OFFSET (0x40)
#define EF_DATA_EF_KEY_SLOT_2_W1 EF_DATA_EF_KEY_SLOT_2_W1
#define EF_DATA_EF_KEY_SLOT_2_W1_POS (0U)
#define EF_DATA_EF_KEY_SLOT_2_W1_LEN (32U)
#define EF_DATA_EF_KEY_SLOT_2_W1_MSK (((1U << EF_DATA_EF_KEY_SLOT_2_W1_LEN) - 1) << EF_DATA_EF_KEY_SLOT_2_W1_POS)
#define EF_DATA_EF_KEY_SLOT_2_W1_UMSK (~(((1U << EF_DATA_EF_KEY_SLOT_2_W1_LEN) - 1) << EF_DATA_EF_KEY_SLOT_2_W1_POS))
/* 0x44 : ef_key_slot_2_w2 */
#define EF_DATA_EF_KEY_SLOT_2_W2_OFFSET (0x44)
#define EF_DATA_EF_KEY_SLOT_2_W2 EF_DATA_EF_KEY_SLOT_2_W2
#define EF_DATA_EF_KEY_SLOT_2_W2_POS (0U)
#define EF_DATA_EF_KEY_SLOT_2_W2_LEN (32U)
#define EF_DATA_EF_KEY_SLOT_2_W2_MSK (((1U << EF_DATA_EF_KEY_SLOT_2_W2_LEN) - 1) << EF_DATA_EF_KEY_SLOT_2_W2_POS)
#define EF_DATA_EF_KEY_SLOT_2_W2_UMSK (~(((1U << EF_DATA_EF_KEY_SLOT_2_W2_LEN) - 1) << EF_DATA_EF_KEY_SLOT_2_W2_POS))
/* 0x48 : ef_key_slot_2_w3 */
#define EF_DATA_EF_KEY_SLOT_2_W3_OFFSET (0x48)
#define EF_DATA_EF_KEY_SLOT_2_W3 EF_DATA_EF_KEY_SLOT_2_W3
#define EF_DATA_EF_KEY_SLOT_2_W3_POS (0U)
#define EF_DATA_EF_KEY_SLOT_2_W3_LEN (32U)
#define EF_DATA_EF_KEY_SLOT_2_W3_MSK (((1U << EF_DATA_EF_KEY_SLOT_2_W3_LEN) - 1) << EF_DATA_EF_KEY_SLOT_2_W3_POS)
#define EF_DATA_EF_KEY_SLOT_2_W3_UMSK (~(((1U << EF_DATA_EF_KEY_SLOT_2_W3_LEN) - 1) << EF_DATA_EF_KEY_SLOT_2_W3_POS))
/* 0x4C : ef_key_slot_3_w0 */
#define EF_DATA_EF_KEY_SLOT_3_W0_OFFSET (0x4C)
#define EF_DATA_EF_KEY_SLOT_3_W0 EF_DATA_EF_KEY_SLOT_3_W0
#define EF_DATA_EF_KEY_SLOT_3_W0_POS (0U)
#define EF_DATA_EF_KEY_SLOT_3_W0_LEN (32U)
#define EF_DATA_EF_KEY_SLOT_3_W0_MSK (((1U << EF_DATA_EF_KEY_SLOT_3_W0_LEN) - 1) << EF_DATA_EF_KEY_SLOT_3_W0_POS)
#define EF_DATA_EF_KEY_SLOT_3_W0_UMSK (~(((1U << EF_DATA_EF_KEY_SLOT_3_W0_LEN) - 1) << EF_DATA_EF_KEY_SLOT_3_W0_POS))
/* 0x50 : ef_key_slot_3_w1 */
#define EF_DATA_EF_KEY_SLOT_3_W1_OFFSET (0x50)
#define EF_DATA_EF_KEY_SLOT_3_W1 EF_DATA_EF_KEY_SLOT_3_W1
#define EF_DATA_EF_KEY_SLOT_3_W1_POS (0U)
#define EF_DATA_EF_KEY_SLOT_3_W1_LEN (32U)
#define EF_DATA_EF_KEY_SLOT_3_W1_MSK (((1U << EF_DATA_EF_KEY_SLOT_3_W1_LEN) - 1) << EF_DATA_EF_KEY_SLOT_3_W1_POS)
#define EF_DATA_EF_KEY_SLOT_3_W1_UMSK (~(((1U << EF_DATA_EF_KEY_SLOT_3_W1_LEN) - 1) << EF_DATA_EF_KEY_SLOT_3_W1_POS))
/* 0x54 : ef_key_slot_3_w2 */
#define EF_DATA_EF_KEY_SLOT_3_W2_OFFSET (0x54)
#define EF_DATA_EF_KEY_SLOT_3_W2 EF_DATA_EF_KEY_SLOT_3_W2
#define EF_DATA_EF_KEY_SLOT_3_W2_POS (0U)
#define EF_DATA_EF_KEY_SLOT_3_W2_LEN (32U)
#define EF_DATA_EF_KEY_SLOT_3_W2_MSK (((1U << EF_DATA_EF_KEY_SLOT_3_W2_LEN) - 1) << EF_DATA_EF_KEY_SLOT_3_W2_POS)
#define EF_DATA_EF_KEY_SLOT_3_W2_UMSK (~(((1U << EF_DATA_EF_KEY_SLOT_3_W2_LEN) - 1) << EF_DATA_EF_KEY_SLOT_3_W2_POS))
/* 0x58 : ef_key_slot_3_w3 */
#define EF_DATA_EF_KEY_SLOT_3_W3_OFFSET (0x58)
#define EF_DATA_EF_KEY_SLOT_3_W3 EF_DATA_EF_KEY_SLOT_3_W3
#define EF_DATA_EF_KEY_SLOT_3_W3_POS (0U)
#define EF_DATA_EF_KEY_SLOT_3_W3_LEN (32U)
#define EF_DATA_EF_KEY_SLOT_3_W3_MSK (((1U << EF_DATA_EF_KEY_SLOT_3_W3_LEN) - 1) << EF_DATA_EF_KEY_SLOT_3_W3_POS)
#define EF_DATA_EF_KEY_SLOT_3_W3_UMSK (~(((1U << EF_DATA_EF_KEY_SLOT_3_W3_LEN) - 1) << EF_DATA_EF_KEY_SLOT_3_W3_POS))
/* 0x5C : ef_key_slot_4_w0 */
#define EF_DATA_EF_KEY_SLOT_4_W0_OFFSET (0x5C)
#define EF_DATA_EF_KEY_SLOT_4_W0 EF_DATA_EF_KEY_SLOT_4_W0
#define EF_DATA_EF_KEY_SLOT_4_W0_POS (0U)
#define EF_DATA_EF_KEY_SLOT_4_W0_LEN (32U)
#define EF_DATA_EF_KEY_SLOT_4_W0_MSK (((1U << EF_DATA_EF_KEY_SLOT_4_W0_LEN) - 1) << EF_DATA_EF_KEY_SLOT_4_W0_POS)
#define EF_DATA_EF_KEY_SLOT_4_W0_UMSK (~(((1U << EF_DATA_EF_KEY_SLOT_4_W0_LEN) - 1) << EF_DATA_EF_KEY_SLOT_4_W0_POS))
/* 0x60 : ef_key_slot_4_w1 */
#define EF_DATA_EF_KEY_SLOT_4_W1_OFFSET (0x60)
#define EF_DATA_EF_KEY_SLOT_4_W1 EF_DATA_EF_KEY_SLOT_4_W1
#define EF_DATA_EF_KEY_SLOT_4_W1_POS (0U)
#define EF_DATA_EF_KEY_SLOT_4_W1_LEN (32U)
#define EF_DATA_EF_KEY_SLOT_4_W1_MSK (((1U << EF_DATA_EF_KEY_SLOT_4_W1_LEN) - 1) << EF_DATA_EF_KEY_SLOT_4_W1_POS)
#define EF_DATA_EF_KEY_SLOT_4_W1_UMSK (~(((1U << EF_DATA_EF_KEY_SLOT_4_W1_LEN) - 1) << EF_DATA_EF_KEY_SLOT_4_W1_POS))
/* 0x64 : ef_key_slot_4_w2 */
#define EF_DATA_EF_KEY_SLOT_4_W2_OFFSET (0x64)
#define EF_DATA_EF_KEY_SLOT_4_W2 EF_DATA_EF_KEY_SLOT_4_W2
#define EF_DATA_EF_KEY_SLOT_4_W2_POS (0U)
#define EF_DATA_EF_KEY_SLOT_4_W2_LEN (32U)
#define EF_DATA_EF_KEY_SLOT_4_W2_MSK (((1U << EF_DATA_EF_KEY_SLOT_4_W2_LEN) - 1) << EF_DATA_EF_KEY_SLOT_4_W2_POS)
#define EF_DATA_EF_KEY_SLOT_4_W2_UMSK (~(((1U << EF_DATA_EF_KEY_SLOT_4_W2_LEN) - 1) << EF_DATA_EF_KEY_SLOT_4_W2_POS))
/* 0x68 : ef_key_slot_4_w3 */
#define EF_DATA_EF_KEY_SLOT_4_W3_OFFSET (0x68)
#define EF_DATA_EF_KEY_SLOT_4_W3 EF_DATA_EF_KEY_SLOT_4_W3
#define EF_DATA_EF_KEY_SLOT_4_W3_POS (0U)
#define EF_DATA_EF_KEY_SLOT_4_W3_LEN (32U)
#define EF_DATA_EF_KEY_SLOT_4_W3_MSK (((1U << EF_DATA_EF_KEY_SLOT_4_W3_LEN) - 1) << EF_DATA_EF_KEY_SLOT_4_W3_POS)
#define EF_DATA_EF_KEY_SLOT_4_W3_UMSK (~(((1U << EF_DATA_EF_KEY_SLOT_4_W3_LEN) - 1) << EF_DATA_EF_KEY_SLOT_4_W3_POS))
/* 0x6C : ef_key_slot_5_w0 */
#define EF_DATA_EF_KEY_SLOT_5_W0_OFFSET (0x6C)
#define EF_DATA_EF_KEY_SLOT_5_W0 EF_DATA_EF_KEY_SLOT_5_W0
#define EF_DATA_EF_KEY_SLOT_5_W0_POS (0U)
#define EF_DATA_EF_KEY_SLOT_5_W0_LEN (32U)
#define EF_DATA_EF_KEY_SLOT_5_W0_MSK (((1U << EF_DATA_EF_KEY_SLOT_5_W0_LEN) - 1) << EF_DATA_EF_KEY_SLOT_5_W0_POS)
#define EF_DATA_EF_KEY_SLOT_5_W0_UMSK (~(((1U << EF_DATA_EF_KEY_SLOT_5_W0_LEN) - 1) << EF_DATA_EF_KEY_SLOT_5_W0_POS))
/* 0x70 : ef_key_slot_5_w1 */
#define EF_DATA_EF_KEY_SLOT_5_W1_OFFSET (0x70)
#define EF_DATA_EF_KEY_SLOT_5_W1 EF_DATA_EF_KEY_SLOT_5_W1
#define EF_DATA_EF_KEY_SLOT_5_W1_POS (0U)
#define EF_DATA_EF_KEY_SLOT_5_W1_LEN (32U)
#define EF_DATA_EF_KEY_SLOT_5_W1_MSK (((1U << EF_DATA_EF_KEY_SLOT_5_W1_LEN) - 1) << EF_DATA_EF_KEY_SLOT_5_W1_POS)
#define EF_DATA_EF_KEY_SLOT_5_W1_UMSK (~(((1U << EF_DATA_EF_KEY_SLOT_5_W1_LEN) - 1) << EF_DATA_EF_KEY_SLOT_5_W1_POS))
/* 0x74 : ef_key_slot_5_w2 */
#define EF_DATA_EF_KEY_SLOT_5_W2_OFFSET (0x74)
#define EF_DATA_EF_KEY_SLOT_5_W2 EF_DATA_EF_KEY_SLOT_5_W2
#define EF_DATA_EF_KEY_SLOT_5_W2_POS (0U)
#define EF_DATA_EF_KEY_SLOT_5_W2_LEN (32U)
#define EF_DATA_EF_KEY_SLOT_5_W2_MSK (((1U << EF_DATA_EF_KEY_SLOT_5_W2_LEN) - 1) << EF_DATA_EF_KEY_SLOT_5_W2_POS)
#define EF_DATA_EF_KEY_SLOT_5_W2_UMSK (~(((1U << EF_DATA_EF_KEY_SLOT_5_W2_LEN) - 1) << EF_DATA_EF_KEY_SLOT_5_W2_POS))
/* 0x78 : ef_key_slot_5_w3 */
#define EF_DATA_EF_KEY_SLOT_5_W3_OFFSET (0x78)
#define EF_DATA_EF_KEY_SLOT_5_W3 EF_DATA_EF_KEY_SLOT_5_W3
#define EF_DATA_EF_KEY_SLOT_5_W3_POS (0U)
#define EF_DATA_EF_KEY_SLOT_5_W3_LEN (32U)
#define EF_DATA_EF_KEY_SLOT_5_W3_MSK (((1U << EF_DATA_EF_KEY_SLOT_5_W3_LEN) - 1) << EF_DATA_EF_KEY_SLOT_5_W3_POS)
#define EF_DATA_EF_KEY_SLOT_5_W3_UMSK (~(((1U << EF_DATA_EF_KEY_SLOT_5_W3_LEN) - 1) << EF_DATA_EF_KEY_SLOT_5_W3_POS))
/* 0x7C : EF_DATA_lock */
#define EF_DATA_LOCK_OFFSET (0x7C)
#define EF_DATA_EF_ANA_TRIM_1 EF_DATA_EF_ANA_TRIM_1
#define EF_DATA_EF_ANA_TRIM_1_POS (0U)
#define EF_DATA_EF_ANA_TRIM_1_LEN (13U)
#define EF_DATA_EF_ANA_TRIM_1_MSK (((1U << EF_DATA_EF_ANA_TRIM_1_LEN) - 1) << EF_DATA_EF_ANA_TRIM_1_POS)
#define EF_DATA_EF_ANA_TRIM_1_UMSK (~(((1U << EF_DATA_EF_ANA_TRIM_1_LEN) - 1) << EF_DATA_EF_ANA_TRIM_1_POS))
#define EF_DATA_WR_LOCK_KEY_SLOT_4_L EF_DATA_WR_LOCK_KEY_SLOT_4_L
#define EF_DATA_WR_LOCK_KEY_SLOT_4_L_POS (13U)
#define EF_DATA_WR_LOCK_KEY_SLOT_4_L_LEN (1U)
#define EF_DATA_WR_LOCK_KEY_SLOT_4_L_MSK (((1U << EF_DATA_WR_LOCK_KEY_SLOT_4_L_LEN) - 1) << EF_DATA_WR_LOCK_KEY_SLOT_4_L_POS)
#define EF_DATA_WR_LOCK_KEY_SLOT_4_L_UMSK (~(((1U << EF_DATA_WR_LOCK_KEY_SLOT_4_L_LEN) - 1) << EF_DATA_WR_LOCK_KEY_SLOT_4_L_POS))
#define EF_DATA_WR_LOCK_KEY_SLOT_5_L EF_DATA_WR_LOCK_KEY_SLOT_5_L
#define EF_DATA_WR_LOCK_KEY_SLOT_5_L_POS (14U)
#define EF_DATA_WR_LOCK_KEY_SLOT_5_L_LEN (1U)
#define EF_DATA_WR_LOCK_KEY_SLOT_5_L_MSK (((1U << EF_DATA_WR_LOCK_KEY_SLOT_5_L_LEN) - 1) << EF_DATA_WR_LOCK_KEY_SLOT_5_L_POS)
#define EF_DATA_WR_LOCK_KEY_SLOT_5_L_UMSK (~(((1U << EF_DATA_WR_LOCK_KEY_SLOT_5_L_LEN) - 1) << EF_DATA_WR_LOCK_KEY_SLOT_5_L_POS))
#define EF_DATA_WR_LOCK_BOOT_MODE EF_DATA_WR_LOCK_BOOT_MODE
#define EF_DATA_WR_LOCK_BOOT_MODE_POS (15U)
#define EF_DATA_WR_LOCK_BOOT_MODE_LEN (1U)
#define EF_DATA_WR_LOCK_BOOT_MODE_MSK (((1U << EF_DATA_WR_LOCK_BOOT_MODE_LEN) - 1) << EF_DATA_WR_LOCK_BOOT_MODE_POS)
#define EF_DATA_WR_LOCK_BOOT_MODE_UMSK (~(((1U << EF_DATA_WR_LOCK_BOOT_MODE_LEN) - 1) << EF_DATA_WR_LOCK_BOOT_MODE_POS))
#define EF_DATA_WR_LOCK_DBG_PWD EF_DATA_WR_LOCK_DBG_PWD
#define EF_DATA_WR_LOCK_DBG_PWD_POS (16U)
#define EF_DATA_WR_LOCK_DBG_PWD_LEN (1U)
#define EF_DATA_WR_LOCK_DBG_PWD_MSK (((1U << EF_DATA_WR_LOCK_DBG_PWD_LEN) - 1) << EF_DATA_WR_LOCK_DBG_PWD_POS)
#define EF_DATA_WR_LOCK_DBG_PWD_UMSK (~(((1U << EF_DATA_WR_LOCK_DBG_PWD_LEN) - 1) << EF_DATA_WR_LOCK_DBG_PWD_POS))
#define EF_DATA_WR_LOCK_SW_USAGE_0 EF_DATA_WR_LOCK_SW_USAGE_0
#define EF_DATA_WR_LOCK_SW_USAGE_0_POS (17U)
#define EF_DATA_WR_LOCK_SW_USAGE_0_LEN (1U)
#define EF_DATA_WR_LOCK_SW_USAGE_0_MSK (((1U << EF_DATA_WR_LOCK_SW_USAGE_0_LEN) - 1) << EF_DATA_WR_LOCK_SW_USAGE_0_POS)
#define EF_DATA_WR_LOCK_SW_USAGE_0_UMSK (~(((1U << EF_DATA_WR_LOCK_SW_USAGE_0_LEN) - 1) << EF_DATA_WR_LOCK_SW_USAGE_0_POS))
#define EF_DATA_WR_LOCK_WIFI_MAC EF_DATA_WR_LOCK_WIFI_MAC
#define EF_DATA_WR_LOCK_WIFI_MAC_POS (18U)
#define EF_DATA_WR_LOCK_WIFI_MAC_LEN (1U)
#define EF_DATA_WR_LOCK_WIFI_MAC_MSK (((1U << EF_DATA_WR_LOCK_WIFI_MAC_LEN) - 1) << EF_DATA_WR_LOCK_WIFI_MAC_POS)
#define EF_DATA_WR_LOCK_WIFI_MAC_UMSK (~(((1U << EF_DATA_WR_LOCK_WIFI_MAC_LEN) - 1) << EF_DATA_WR_LOCK_WIFI_MAC_POS))
#define EF_DATA_WR_LOCK_KEY_SLOT_0 EF_DATA_WR_LOCK_KEY_SLOT_0
#define EF_DATA_WR_LOCK_KEY_SLOT_0_POS (19U)
#define EF_DATA_WR_LOCK_KEY_SLOT_0_LEN (1U)
#define EF_DATA_WR_LOCK_KEY_SLOT_0_MSK (((1U << EF_DATA_WR_LOCK_KEY_SLOT_0_LEN) - 1) << EF_DATA_WR_LOCK_KEY_SLOT_0_POS)
#define EF_DATA_WR_LOCK_KEY_SLOT_0_UMSK (~(((1U << EF_DATA_WR_LOCK_KEY_SLOT_0_LEN) - 1) << EF_DATA_WR_LOCK_KEY_SLOT_0_POS))
#define EF_DATA_WR_LOCK_KEY_SLOT_1 EF_DATA_WR_LOCK_KEY_SLOT_1
#define EF_DATA_WR_LOCK_KEY_SLOT_1_POS (20U)
#define EF_DATA_WR_LOCK_KEY_SLOT_1_LEN (1U)
#define EF_DATA_WR_LOCK_KEY_SLOT_1_MSK (((1U << EF_DATA_WR_LOCK_KEY_SLOT_1_LEN) - 1) << EF_DATA_WR_LOCK_KEY_SLOT_1_POS)
#define EF_DATA_WR_LOCK_KEY_SLOT_1_UMSK (~(((1U << EF_DATA_WR_LOCK_KEY_SLOT_1_LEN) - 1) << EF_DATA_WR_LOCK_KEY_SLOT_1_POS))
#define EF_DATA_WR_LOCK_KEY_SLOT_2 EF_DATA_WR_LOCK_KEY_SLOT_2
#define EF_DATA_WR_LOCK_KEY_SLOT_2_POS (21U)
#define EF_DATA_WR_LOCK_KEY_SLOT_2_LEN (1U)
#define EF_DATA_WR_LOCK_KEY_SLOT_2_MSK (((1U << EF_DATA_WR_LOCK_KEY_SLOT_2_LEN) - 1) << EF_DATA_WR_LOCK_KEY_SLOT_2_POS)
#define EF_DATA_WR_LOCK_KEY_SLOT_2_UMSK (~(((1U << EF_DATA_WR_LOCK_KEY_SLOT_2_LEN) - 1) << EF_DATA_WR_LOCK_KEY_SLOT_2_POS))
#define EF_DATA_WR_LOCK_KEY_SLOT_3 EF_DATA_WR_LOCK_KEY_SLOT_3
#define EF_DATA_WR_LOCK_KEY_SLOT_3_POS (22U)
#define EF_DATA_WR_LOCK_KEY_SLOT_3_LEN (1U)
#define EF_DATA_WR_LOCK_KEY_SLOT_3_MSK (((1U << EF_DATA_WR_LOCK_KEY_SLOT_3_LEN) - 1) << EF_DATA_WR_LOCK_KEY_SLOT_3_POS)
#define EF_DATA_WR_LOCK_KEY_SLOT_3_UMSK (~(((1U << EF_DATA_WR_LOCK_KEY_SLOT_3_LEN) - 1) << EF_DATA_WR_LOCK_KEY_SLOT_3_POS))
#define EF_DATA_WR_LOCK_KEY_SLOT_4_H EF_DATA_WR_LOCK_KEY_SLOT_4_H
#define EF_DATA_WR_LOCK_KEY_SLOT_4_H_POS (23U)
#define EF_DATA_WR_LOCK_KEY_SLOT_4_H_LEN (1U)
#define EF_DATA_WR_LOCK_KEY_SLOT_4_H_MSK (((1U << EF_DATA_WR_LOCK_KEY_SLOT_4_H_LEN) - 1) << EF_DATA_WR_LOCK_KEY_SLOT_4_H_POS)
#define EF_DATA_WR_LOCK_KEY_SLOT_4_H_UMSK (~(((1U << EF_DATA_WR_LOCK_KEY_SLOT_4_H_LEN) - 1) << EF_DATA_WR_LOCK_KEY_SLOT_4_H_POS))
#define EF_DATA_WR_LOCK_KEY_SLOT_5_H EF_DATA_WR_LOCK_KEY_SLOT_5_H
#define EF_DATA_WR_LOCK_KEY_SLOT_5_H_POS (24U)
#define EF_DATA_WR_LOCK_KEY_SLOT_5_H_LEN (1U)
#define EF_DATA_WR_LOCK_KEY_SLOT_5_H_MSK (((1U << EF_DATA_WR_LOCK_KEY_SLOT_5_H_LEN) - 1) << EF_DATA_WR_LOCK_KEY_SLOT_5_H_POS)
#define EF_DATA_WR_LOCK_KEY_SLOT_5_H_UMSK (~(((1U << EF_DATA_WR_LOCK_KEY_SLOT_5_H_LEN) - 1) << EF_DATA_WR_LOCK_KEY_SLOT_5_H_POS))
#define EF_DATA_RD_LOCK_DBG_PWD EF_DATA_RD_LOCK_DBG_PWD
#define EF_DATA_RD_LOCK_DBG_PWD_POS (25U)
#define EF_DATA_RD_LOCK_DBG_PWD_LEN (1U)
#define EF_DATA_RD_LOCK_DBG_PWD_MSK (((1U << EF_DATA_RD_LOCK_DBG_PWD_LEN) - 1) << EF_DATA_RD_LOCK_DBG_PWD_POS)
#define EF_DATA_RD_LOCK_DBG_PWD_UMSK (~(((1U << EF_DATA_RD_LOCK_DBG_PWD_LEN) - 1) << EF_DATA_RD_LOCK_DBG_PWD_POS))
#define EF_DATA_RD_LOCK_KEY_SLOT_0 EF_DATA_RD_LOCK_KEY_SLOT_0
#define EF_DATA_RD_LOCK_KEY_SLOT_0_POS (26U)
#define EF_DATA_RD_LOCK_KEY_SLOT_0_LEN (1U)
#define EF_DATA_RD_LOCK_KEY_SLOT_0_MSK (((1U << EF_DATA_RD_LOCK_KEY_SLOT_0_LEN) - 1) << EF_DATA_RD_LOCK_KEY_SLOT_0_POS)
#define EF_DATA_RD_LOCK_KEY_SLOT_0_UMSK (~(((1U << EF_DATA_RD_LOCK_KEY_SLOT_0_LEN) - 1) << EF_DATA_RD_LOCK_KEY_SLOT_0_POS))
#define EF_DATA_RD_LOCK_KEY_SLOT_1 EF_DATA_RD_LOCK_KEY_SLOT_1
#define EF_DATA_RD_LOCK_KEY_SLOT_1_POS (27U)
#define EF_DATA_RD_LOCK_KEY_SLOT_1_LEN (1U)
#define EF_DATA_RD_LOCK_KEY_SLOT_1_MSK (((1U << EF_DATA_RD_LOCK_KEY_SLOT_1_LEN) - 1) << EF_DATA_RD_LOCK_KEY_SLOT_1_POS)
#define EF_DATA_RD_LOCK_KEY_SLOT_1_UMSK (~(((1U << EF_DATA_RD_LOCK_KEY_SLOT_1_LEN) - 1) << EF_DATA_RD_LOCK_KEY_SLOT_1_POS))
#define EF_DATA_RD_LOCK_KEY_SLOT_2 EF_DATA_RD_LOCK_KEY_SLOT_2
#define EF_DATA_RD_LOCK_KEY_SLOT_2_POS (28U)
#define EF_DATA_RD_LOCK_KEY_SLOT_2_LEN (1U)
#define EF_DATA_RD_LOCK_KEY_SLOT_2_MSK (((1U << EF_DATA_RD_LOCK_KEY_SLOT_2_LEN) - 1) << EF_DATA_RD_LOCK_KEY_SLOT_2_POS)
#define EF_DATA_RD_LOCK_KEY_SLOT_2_UMSK (~(((1U << EF_DATA_RD_LOCK_KEY_SLOT_2_LEN) - 1) << EF_DATA_RD_LOCK_KEY_SLOT_2_POS))
#define EF_DATA_RD_LOCK_KEY_SLOT_3 EF_DATA_RD_LOCK_KEY_SLOT_3
#define EF_DATA_RD_LOCK_KEY_SLOT_3_POS (29U)
#define EF_DATA_RD_LOCK_KEY_SLOT_3_LEN (1U)
#define EF_DATA_RD_LOCK_KEY_SLOT_3_MSK (((1U << EF_DATA_RD_LOCK_KEY_SLOT_3_LEN) - 1) << EF_DATA_RD_LOCK_KEY_SLOT_3_POS)
#define EF_DATA_RD_LOCK_KEY_SLOT_3_UMSK (~(((1U << EF_DATA_RD_LOCK_KEY_SLOT_3_LEN) - 1) << EF_DATA_RD_LOCK_KEY_SLOT_3_POS))
#define EF_DATA_RD_LOCK_KEY_SLOT_4 EF_DATA_RD_LOCK_KEY_SLOT_4
#define EF_DATA_RD_LOCK_KEY_SLOT_4_POS (30U)
#define EF_DATA_RD_LOCK_KEY_SLOT_4_LEN (1U)
#define EF_DATA_RD_LOCK_KEY_SLOT_4_MSK (((1U << EF_DATA_RD_LOCK_KEY_SLOT_4_LEN) - 1) << EF_DATA_RD_LOCK_KEY_SLOT_4_POS)
#define EF_DATA_RD_LOCK_KEY_SLOT_4_UMSK (~(((1U << EF_DATA_RD_LOCK_KEY_SLOT_4_LEN) - 1) << EF_DATA_RD_LOCK_KEY_SLOT_4_POS))
#define EF_DATA_RD_LOCK_KEY_SLOT_5 EF_DATA_RD_LOCK_KEY_SLOT_5
#define EF_DATA_RD_LOCK_KEY_SLOT_5_POS (31U)
#define EF_DATA_RD_LOCK_KEY_SLOT_5_LEN (1U)
#define EF_DATA_RD_LOCK_KEY_SLOT_5_MSK (((1U << EF_DATA_RD_LOCK_KEY_SLOT_5_LEN) - 1) << EF_DATA_RD_LOCK_KEY_SLOT_5_POS)
#define EF_DATA_RD_LOCK_KEY_SLOT_5_UMSK (~(((1U << EF_DATA_RD_LOCK_KEY_SLOT_5_LEN) - 1) << EF_DATA_RD_LOCK_KEY_SLOT_5_POS))
struct EF_DATA_reg {
/* 0x0 : ef_cfg_0 */
union {
struct
{
uint32_t ef_sf_aes_mode : 2; /* [ 1: 0], r/w, 0x0 */
uint32_t ef_sboot_sign_mode : 2; /* [ 3: 2], r/w, 0x0 */
uint32_t ef_sboot_en : 2; /* [ 5: 4], r/w, 0x0 */
uint32_t reserved_6 : 1; /* [ 6], rsvd, 0x0 */
uint32_t ef_cpu0_enc_en : 1; /* [ 7], r/w, 0x0 */
uint32_t reserved_8_11 : 4; /* [11: 8], rsvd, 0x0 */
uint32_t ef_sw_usage_1 : 2; /* [13:12], r/w, 0x0 */
uint32_t rsvd0 : 1; /* [ 14], r/w, 0x0 */
uint32_t rsvd1 : 1; /* [ 15], r/w, 0x0 */
uint32_t rsvd2 : 1; /* [ 16], r/w, 0x0 */
uint32_t ef_0_key_enc_en : 1; /* [ 17], r/w, 0x0 */
uint32_t reserved_18 : 1; /* [ 18], rsvd, 0x0 */
uint32_t rsvd3 : 1; /* [ 19], r/w, 0x0 */
uint32_t reserved_20 : 1; /* [ 20], rsvd, 0x0 */
uint32_t rsvd4 : 1; /* [ 21], r/w, 0x0 */
uint32_t rsvd5 : 1; /* [ 22], r/w, 0x0 */
uint32_t rsvd6 : 1; /* [ 23], r/w, 0x0 */
uint32_t reserved_24_25 : 2; /* [25:24], rsvd, 0x0 */
uint32_t ef_dbg_jtag_0_dis : 2; /* [27:26], r/w, 0x0 */
uint32_t ef_dbg_mode : 4; /* [31:28], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_cfg_0;
/* 0x4 : ef_dbg_pwd_low */
union {
struct
{
uint32_t ef_dbg_pwd_low : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_dbg_pwd_low;
/* 0x8 : ef_dbg_pwd_high */
union {
struct
{
uint32_t ef_dbg_pwd_high : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_dbg_pwd_high;
/* 0xC : ef_ana_trim_0 */
union {
struct
{
uint32_t ef_ana_trim_0 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_ana_trim_0;
/* 0x10 : ef_sw_usage_0 */
union {
struct
{
uint32_t ef_sw_usage_0 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_sw_usage_0;
/* 0x14 : ef_wifi_mac_low */
union {
struct
{
uint32_t ef_wifi_mac_low : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_wifi_mac_low;
/* 0x18 : ef_wifi_mac_high */
union {
struct
{
uint32_t ef_wifi_mac_high : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_wifi_mac_high;
/* 0x1C : ef_key_slot_0_w0 */
union {
struct
{
uint32_t ef_key_slot_0_w0 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_0_w0;
/* 0x20 : ef_key_slot_0_w1 */
union {
struct
{
uint32_t ef_key_slot_0_w1 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_0_w1;
/* 0x24 : ef_key_slot_0_w2 */
union {
struct
{
uint32_t ef_key_slot_0_w2 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_0_w2;
/* 0x28 : ef_key_slot_0_w3 */
union {
struct
{
uint32_t ef_key_slot_0_w3 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_0_w3;
/* 0x2C : ef_key_slot_1_w0 */
union {
struct
{
uint32_t ef_key_slot_1_w0 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_1_w0;
/* 0x30 : ef_key_slot_1_w1 */
union {
struct
{
uint32_t ef_key_slot_1_w1 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_1_w1;
/* 0x34 : ef_key_slot_1_w2 */
union {
struct
{
uint32_t ef_key_slot_1_w2 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_1_w2;
/* 0x38 : ef_key_slot_1_w3 */
union {
struct
{
uint32_t ef_key_slot_1_w3 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_1_w3;
/* 0x3C : ef_key_slot_2_w0 */
union {
struct
{
uint32_t ef_key_slot_2_w0 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_2_w0;
/* 0x40 : ef_key_slot_2_w1 */
union {
struct
{
uint32_t ef_key_slot_2_w1 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_2_w1;
/* 0x44 : ef_key_slot_2_w2 */
union {
struct
{
uint32_t ef_key_slot_2_w2 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_2_w2;
/* 0x48 : ef_key_slot_2_w3 */
union {
struct
{
uint32_t ef_key_slot_2_w3 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_2_w3;
/* 0x4C : ef_key_slot_3_w0 */
union {
struct
{
uint32_t ef_key_slot_3_w0 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_3_w0;
/* 0x50 : ef_key_slot_3_w1 */
union {
struct
{
uint32_t ef_key_slot_3_w1 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_3_w1;
/* 0x54 : ef_key_slot_3_w2 */
union {
struct
{
uint32_t ef_key_slot_3_w2 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_3_w2;
/* 0x58 : ef_key_slot_3_w3 */
union {
struct
{
uint32_t ef_key_slot_3_w3 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_3_w3;
/* 0x5C : ef_key_slot_4_w0 */
union {
struct
{
uint32_t ef_key_slot_4_w0 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_4_w0;
/* 0x60 : ef_key_slot_4_w1 */
union {
struct
{
uint32_t ef_key_slot_4_w1 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_4_w1;
/* 0x64 : ef_key_slot_4_w2 */
union {
struct
{
uint32_t ef_key_slot_4_w2 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_4_w2;
/* 0x68 : ef_key_slot_4_w3 */
union {
struct
{
uint32_t ef_key_slot_4_w3 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_4_w3;
/* 0x6C : ef_key_slot_5_w0 */
union {
struct
{
uint32_t ef_key_slot_5_w0 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_5_w0;
/* 0x70 : ef_key_slot_5_w1 */
union {
struct
{
uint32_t ef_key_slot_5_w1 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_5_w1;
/* 0x74 : ef_key_slot_5_w2 */
union {
struct
{
uint32_t ef_key_slot_5_w2 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_5_w2;
/* 0x78 : ef_key_slot_5_w3 */
union {
struct
{
uint32_t ef_key_slot_5_w3 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_5_w3;
/* 0x7C : EF_DATA_lock */
union {
struct
{
uint32_t ef_ana_trim_1 : 13; /* [12: 0], r/w, 0x0 */
uint32_t wr_lock_key_slot_4_l : 1; /* [ 13], r/w, 0x0 */
uint32_t wr_lock_key_slot_5_l : 1; /* [ 14], r/w, 0x0 */
uint32_t wr_lock_boot_mode : 1; /* [ 15], r/w, 0x0 */
uint32_t wr_lock_dbg_pwd : 1; /* [ 16], r/w, 0x0 */
uint32_t wr_lock_sw_usage_0 : 1; /* [ 17], r/w, 0x0 */
uint32_t wr_lock_wifi_mac : 1; /* [ 18], r/w, 0x0 */
uint32_t wr_lock_key_slot_0 : 1; /* [ 19], r/w, 0x0 */
uint32_t wr_lock_key_slot_1 : 1; /* [ 20], r/w, 0x0 */
uint32_t wr_lock_key_slot_2 : 1; /* [ 21], r/w, 0x0 */
uint32_t wr_lock_key_slot_3 : 1; /* [ 22], r/w, 0x0 */
uint32_t wr_lock_key_slot_4_h : 1; /* [ 23], r/w, 0x0 */
uint32_t wr_lock_key_slot_5_h : 1; /* [ 24], r/w, 0x0 */
uint32_t rd_lock_dbg_pwd : 1; /* [ 25], r/w, 0x0 */
uint32_t rd_lock_key_slot_0 : 1; /* [ 26], r/w, 0x0 */
uint32_t rd_lock_key_slot_1 : 1; /* [ 27], r/w, 0x0 */
uint32_t rd_lock_key_slot_2 : 1; /* [ 28], r/w, 0x0 */
uint32_t rd_lock_key_slot_3 : 1; /* [ 29], r/w, 0x0 */
uint32_t rd_lock_key_slot_4 : 1; /* [ 30], r/w, 0x0 */
uint32_t rd_lock_key_slot_5 : 1; /* [ 31], r/w, 0x0 */
} BF;
uint32_t WORD;
} EF_DATA_lock;
};
typedef volatile struct EF_DATA_reg EF_DATA_reg_t;
#endif /* __EF_DATA_REG_H__ */

256
drivers/soc/bl602/bl602_std/include/hardware/tzc_sec_reg.h Normal file
View file

@ -0,0 +1,256 @@
/**
******************************************************************************
* @file tzc_sec_reg.h
* @version V1.2
* @date 2020-04-30
* @brief This file is the description of.IP register
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __TZC_SEC_REG_H__
#define __TZC_SEC_REG_H__
#include "bl602.h"
/* 0x40 : tzc_rom_ctrl */
#define TZC_SEC_TZC_ROM_CTRL_OFFSET (0x40)
#define TZC_SEC_TZC_ROM0_R0_ID0_EN TZC_SEC_TZC_ROM0_R0_ID0_EN
#define TZC_SEC_TZC_ROM0_R0_ID0_EN_POS (0U)
#define TZC_SEC_TZC_ROM0_R0_ID0_EN_LEN (1U)
#define TZC_SEC_TZC_ROM0_R0_ID0_EN_MSK (((1U << TZC_SEC_TZC_ROM0_R0_ID0_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_ID0_EN_POS)
#define TZC_SEC_TZC_ROM0_R0_ID0_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R0_ID0_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_ID0_EN_POS))
#define TZC_SEC_TZC_ROM0_R1_ID0_EN TZC_SEC_TZC_ROM0_R1_ID0_EN
#define TZC_SEC_TZC_ROM0_R1_ID0_EN_POS (1U)
#define TZC_SEC_TZC_ROM0_R1_ID0_EN_LEN (1U)
#define TZC_SEC_TZC_ROM0_R1_ID0_EN_MSK (((1U << TZC_SEC_TZC_ROM0_R1_ID0_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_ID0_EN_POS)
#define TZC_SEC_TZC_ROM0_R1_ID0_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R1_ID0_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_ID0_EN_POS))
#define TZC_SEC_TZC_ROM1_R0_ID0_EN TZC_SEC_TZC_ROM1_R0_ID0_EN
#define TZC_SEC_TZC_ROM1_R0_ID0_EN_POS (2U)
#define TZC_SEC_TZC_ROM1_R0_ID0_EN_LEN (1U)
#define TZC_SEC_TZC_ROM1_R0_ID0_EN_MSK (((1U << TZC_SEC_TZC_ROM1_R0_ID0_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_ID0_EN_POS)
#define TZC_SEC_TZC_ROM1_R0_ID0_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R0_ID0_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_ID0_EN_POS))
#define TZC_SEC_TZC_ROM1_R1_ID0_EN TZC_SEC_TZC_ROM1_R1_ID0_EN
#define TZC_SEC_TZC_ROM1_R1_ID0_EN_POS (3U)
#define TZC_SEC_TZC_ROM1_R1_ID0_EN_LEN (1U)
#define TZC_SEC_TZC_ROM1_R1_ID0_EN_MSK (((1U << TZC_SEC_TZC_ROM1_R1_ID0_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_ID0_EN_POS)
#define TZC_SEC_TZC_ROM1_R1_ID0_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R1_ID0_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_ID0_EN_POS))
#define TZC_SEC_TZC_ROM0_R0_ID1_EN TZC_SEC_TZC_ROM0_R0_ID1_EN
#define TZC_SEC_TZC_ROM0_R0_ID1_EN_POS (8U)
#define TZC_SEC_TZC_ROM0_R0_ID1_EN_LEN (1U)
#define TZC_SEC_TZC_ROM0_R0_ID1_EN_MSK (((1U << TZC_SEC_TZC_ROM0_R0_ID1_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_ID1_EN_POS)
#define TZC_SEC_TZC_ROM0_R0_ID1_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R0_ID1_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_ID1_EN_POS))
#define TZC_SEC_TZC_ROM0_R1_ID1_EN TZC_SEC_TZC_ROM0_R1_ID1_EN
#define TZC_SEC_TZC_ROM0_R1_ID1_EN_POS (9U)
#define TZC_SEC_TZC_ROM0_R1_ID1_EN_LEN (1U)
#define TZC_SEC_TZC_ROM0_R1_ID1_EN_MSK (((1U << TZC_SEC_TZC_ROM0_R1_ID1_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_ID1_EN_POS)
#define TZC_SEC_TZC_ROM0_R1_ID1_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R1_ID1_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_ID1_EN_POS))
#define TZC_SEC_TZC_ROM1_R0_ID1_EN TZC_SEC_TZC_ROM1_R0_ID1_EN
#define TZC_SEC_TZC_ROM1_R0_ID1_EN_POS (10U)
#define TZC_SEC_TZC_ROM1_R0_ID1_EN_LEN (1U)
#define TZC_SEC_TZC_ROM1_R0_ID1_EN_MSK (((1U << TZC_SEC_TZC_ROM1_R0_ID1_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_ID1_EN_POS)
#define TZC_SEC_TZC_ROM1_R0_ID1_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R0_ID1_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_ID1_EN_POS))
#define TZC_SEC_TZC_ROM1_R1_ID1_EN TZC_SEC_TZC_ROM1_R1_ID1_EN
#define TZC_SEC_TZC_ROM1_R1_ID1_EN_POS (11U)
#define TZC_SEC_TZC_ROM1_R1_ID1_EN_LEN (1U)
#define TZC_SEC_TZC_ROM1_R1_ID1_EN_MSK (((1U << TZC_SEC_TZC_ROM1_R1_ID1_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_ID1_EN_POS)
#define TZC_SEC_TZC_ROM1_R1_ID1_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R1_ID1_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_ID1_EN_POS))
#define TZC_SEC_TZC_ROM0_R0_EN TZC_SEC_TZC_ROM0_R0_EN
#define TZC_SEC_TZC_ROM0_R0_EN_POS (16U)
#define TZC_SEC_TZC_ROM0_R0_EN_LEN (1U)
#define TZC_SEC_TZC_ROM0_R0_EN_MSK (((1U << TZC_SEC_TZC_ROM0_R0_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_EN_POS)
#define TZC_SEC_TZC_ROM0_R0_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R0_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_EN_POS))
#define TZC_SEC_TZC_ROM0_R1_EN TZC_SEC_TZC_ROM0_R1_EN
#define TZC_SEC_TZC_ROM0_R1_EN_POS (17U)
#define TZC_SEC_TZC_ROM0_R1_EN_LEN (1U)
#define TZC_SEC_TZC_ROM0_R1_EN_MSK (((1U << TZC_SEC_TZC_ROM0_R1_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_EN_POS)
#define TZC_SEC_TZC_ROM0_R1_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R1_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_EN_POS))
#define TZC_SEC_TZC_ROM1_R0_EN TZC_SEC_TZC_ROM1_R0_EN
#define TZC_SEC_TZC_ROM1_R0_EN_POS (18U)
#define TZC_SEC_TZC_ROM1_R0_EN_LEN (1U)
#define TZC_SEC_TZC_ROM1_R0_EN_MSK (((1U << TZC_SEC_TZC_ROM1_R0_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_EN_POS)
#define TZC_SEC_TZC_ROM1_R0_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R0_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_EN_POS))
#define TZC_SEC_TZC_ROM1_R1_EN TZC_SEC_TZC_ROM1_R1_EN
#define TZC_SEC_TZC_ROM1_R1_EN_POS (19U)
#define TZC_SEC_TZC_ROM1_R1_EN_LEN (1U)
#define TZC_SEC_TZC_ROM1_R1_EN_MSK (((1U << TZC_SEC_TZC_ROM1_R1_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_EN_POS)
#define TZC_SEC_TZC_ROM1_R1_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R1_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_EN_POS))
#define TZC_SEC_TZC_ROM0_R0_LOCK TZC_SEC_TZC_ROM0_R0_LOCK
#define TZC_SEC_TZC_ROM0_R0_LOCK_POS (24U)
#define TZC_SEC_TZC_ROM0_R0_LOCK_LEN (1U)
#define TZC_SEC_TZC_ROM0_R0_LOCK_MSK (((1U << TZC_SEC_TZC_ROM0_R0_LOCK_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_LOCK_POS)
#define TZC_SEC_TZC_ROM0_R0_LOCK_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R0_LOCK_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_LOCK_POS))
#define TZC_SEC_TZC_ROM0_R1_LOCK TZC_SEC_TZC_ROM0_R1_LOCK
#define TZC_SEC_TZC_ROM0_R1_LOCK_POS (25U)
#define TZC_SEC_TZC_ROM0_R1_LOCK_LEN (1U)
#define TZC_SEC_TZC_ROM0_R1_LOCK_MSK (((1U << TZC_SEC_TZC_ROM0_R1_LOCK_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_LOCK_POS)
#define TZC_SEC_TZC_ROM0_R1_LOCK_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R1_LOCK_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_LOCK_POS))
#define TZC_SEC_TZC_ROM1_R0_LOCK TZC_SEC_TZC_ROM1_R0_LOCK
#define TZC_SEC_TZC_ROM1_R0_LOCK_POS (26U)
#define TZC_SEC_TZC_ROM1_R0_LOCK_LEN (1U)
#define TZC_SEC_TZC_ROM1_R0_LOCK_MSK (((1U << TZC_SEC_TZC_ROM1_R0_LOCK_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_LOCK_POS)
#define TZC_SEC_TZC_ROM1_R0_LOCK_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R0_LOCK_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_LOCK_POS))
#define TZC_SEC_TZC_ROM1_R1_LOCK TZC_SEC_TZC_ROM1_R1_LOCK
#define TZC_SEC_TZC_ROM1_R1_LOCK_POS (27U)
#define TZC_SEC_TZC_ROM1_R1_LOCK_LEN (1U)
#define TZC_SEC_TZC_ROM1_R1_LOCK_MSK (((1U << TZC_SEC_TZC_ROM1_R1_LOCK_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_LOCK_POS)
#define TZC_SEC_TZC_ROM1_R1_LOCK_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R1_LOCK_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_LOCK_POS))
#define TZC_SEC_TZC_SBOOT_DONE TZC_SEC_TZC_SBOOT_DONE
#define TZC_SEC_TZC_SBOOT_DONE_POS (28U)
#define TZC_SEC_TZC_SBOOT_DONE_LEN (4U)
#define TZC_SEC_TZC_SBOOT_DONE_MSK (((1U << TZC_SEC_TZC_SBOOT_DONE_LEN) - 1) << TZC_SEC_TZC_SBOOT_DONE_POS)
#define TZC_SEC_TZC_SBOOT_DONE_UMSK (~(((1U << TZC_SEC_TZC_SBOOT_DONE_LEN) - 1) << TZC_SEC_TZC_SBOOT_DONE_POS))
/* 0x44 : tzc_rom0_r0 */
#define TZC_SEC_TZC_ROM0_R0_OFFSET (0x44)
#define TZC_SEC_TZC_ROM0_R0_END TZC_SEC_TZC_ROM0_R0_END
#define TZC_SEC_TZC_ROM0_R0_END_POS (0U)
#define TZC_SEC_TZC_ROM0_R0_END_LEN (16U)
#define TZC_SEC_TZC_ROM0_R0_END_MSK (((1U << TZC_SEC_TZC_ROM0_R0_END_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_END_POS)
#define TZC_SEC_TZC_ROM0_R0_END_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R0_END_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_END_POS))
#define TZC_SEC_TZC_ROM0_R0_START TZC_SEC_TZC_ROM0_R0_START
#define TZC_SEC_TZC_ROM0_R0_START_POS (16U)
#define TZC_SEC_TZC_ROM0_R0_START_LEN (16U)
#define TZC_SEC_TZC_ROM0_R0_START_MSK (((1U << TZC_SEC_TZC_ROM0_R0_START_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_START_POS)
#define TZC_SEC_TZC_ROM0_R0_START_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R0_START_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_START_POS))
/* 0x48 : tzc_rom0_r1 */
#define TZC_SEC_TZC_ROM0_R1_OFFSET (0x48)
#define TZC_SEC_TZC_ROM0_R1_END TZC_SEC_TZC_ROM0_R1_END
#define TZC_SEC_TZC_ROM0_R1_END_POS (0U)
#define TZC_SEC_TZC_ROM0_R1_END_LEN (16U)
#define TZC_SEC_TZC_ROM0_R1_END_MSK (((1U << TZC_SEC_TZC_ROM0_R1_END_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_END_POS)
#define TZC_SEC_TZC_ROM0_R1_END_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R1_END_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_END_POS))
#define TZC_SEC_TZC_ROM0_R1_START TZC_SEC_TZC_ROM0_R1_START
#define TZC_SEC_TZC_ROM0_R1_START_POS (16U)
#define TZC_SEC_TZC_ROM0_R1_START_LEN (16U)
#define TZC_SEC_TZC_ROM0_R1_START_MSK (((1U << TZC_SEC_TZC_ROM0_R1_START_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_START_POS)
#define TZC_SEC_TZC_ROM0_R1_START_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R1_START_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_START_POS))
/* 0x4C : tzc_rom1_r0 */
#define TZC_SEC_TZC_ROM1_R0_OFFSET (0x4C)
#define TZC_SEC_TZC_ROM1_R0_END TZC_SEC_TZC_ROM1_R0_END
#define TZC_SEC_TZC_ROM1_R0_END_POS (0U)
#define TZC_SEC_TZC_ROM1_R0_END_LEN (16U)
#define TZC_SEC_TZC_ROM1_R0_END_MSK (((1U << TZC_SEC_TZC_ROM1_R0_END_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_END_POS)
#define TZC_SEC_TZC_ROM1_R0_END_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R0_END_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_END_POS))
#define TZC_SEC_TZC_ROM1_R0_START TZC_SEC_TZC_ROM1_R0_START
#define TZC_SEC_TZC_ROM1_R0_START_POS (16U)
#define TZC_SEC_TZC_ROM1_R0_START_LEN (16U)
#define TZC_SEC_TZC_ROM1_R0_START_MSK (((1U << TZC_SEC_TZC_ROM1_R0_START_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_START_POS)
#define TZC_SEC_TZC_ROM1_R0_START_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R0_START_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_START_POS))
/* 0x50 : tzc_rom1_r1 */
#define TZC_SEC_TZC_ROM1_R1_OFFSET (0x50)
#define TZC_SEC_TZC_ROM1_R1_END TZC_SEC_TZC_ROM1_R1_END
#define TZC_SEC_TZC_ROM1_R1_END_POS (0U)
#define TZC_SEC_TZC_ROM1_R1_END_LEN (16U)
#define TZC_SEC_TZC_ROM1_R1_END_MSK (((1U << TZC_SEC_TZC_ROM1_R1_END_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_END_POS)
#define TZC_SEC_TZC_ROM1_R1_END_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R1_END_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_END_POS))
#define TZC_SEC_TZC_ROM1_R1_START TZC_SEC_TZC_ROM1_R1_START
#define TZC_SEC_TZC_ROM1_R1_START_POS (16U)
#define TZC_SEC_TZC_ROM1_R1_START_LEN (16U)
#define TZC_SEC_TZC_ROM1_R1_START_MSK (((1U << TZC_SEC_TZC_ROM1_R1_START_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_START_POS)
#define TZC_SEC_TZC_ROM1_R1_START_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R1_START_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_START_POS))
struct tzc_sec_reg {
/* 0x0 reserved */
uint8_t RESERVED0x0[64];
/* 0x40 : tzc_rom_ctrl */
union {
struct
{
uint32_t tzc_rom0_r0_id0_en : 1; /* [ 0], r/w, 0x1 */
uint32_t tzc_rom0_r1_id0_en : 1; /* [ 1], r/w, 0x1 */
uint32_t tzc_rom1_r0_id0_en : 1; /* [ 2], r/w, 0x1 */
uint32_t tzc_rom1_r1_id0_en : 1; /* [ 3], r/w, 0x1 */
uint32_t reserved_4_7 : 4; /* [ 7: 4], rsvd, 0x0 */
uint32_t tzc_rom0_r0_id1_en : 1; /* [ 8], r/w, 0x1 */
uint32_t tzc_rom0_r1_id1_en : 1; /* [ 9], r/w, 0x1 */
uint32_t tzc_rom1_r0_id1_en : 1; /* [ 10], r/w, 0x1 */
uint32_t tzc_rom1_r1_id1_en : 1; /* [ 11], r/w, 0x1 */
uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */
uint32_t tzc_rom0_r0_en : 1; /* [ 16], r/w, 0x0 */
uint32_t tzc_rom0_r1_en : 1; /* [ 17], r/w, 0x0 */
uint32_t tzc_rom1_r0_en : 1; /* [ 18], r/w, 0x0 */
uint32_t tzc_rom1_r1_en : 1; /* [ 19], r/w, 0x0 */
uint32_t reserved_20_23 : 4; /* [23:20], rsvd, 0x0 */
uint32_t tzc_rom0_r0_lock : 1; /* [ 24], r/w, 0x0 */
uint32_t tzc_rom0_r1_lock : 1; /* [ 25], r/w, 0x0 */
uint32_t tzc_rom1_r0_lock : 1; /* [ 26], r/w, 0x0 */
uint32_t tzc_rom1_r1_lock : 1; /* [ 27], r/w, 0x0 */
uint32_t tzc_sboot_done : 4; /* [31:28], r/w, 0x0 */
} BF;
uint32_t WORD;
} tzc_rom_ctrl;
/* 0x44 : tzc_rom0_r0 */
union {
struct
{
uint32_t tzc_rom0_r0_end : 16; /* [15: 0], r/w, 0xffff */
uint32_t tzc_rom0_r0_start : 16; /* [31:16], r/w, 0x0 */
} BF;
uint32_t WORD;
} tzc_rom0_r0;
/* 0x48 : tzc_rom0_r1 */
union {
struct
{
uint32_t tzc_rom0_r1_end : 16; /* [15: 0], r/w, 0xffff */
uint32_t tzc_rom0_r1_start : 16; /* [31:16], r/w, 0x0 */
} BF;
uint32_t WORD;
} tzc_rom0_r1;
/* 0x4C : tzc_rom1_r0 */
union {
struct
{
uint32_t tzc_rom1_r0_end : 16; /* [15: 0], r/w, 0xffff */
uint32_t tzc_rom1_r0_start : 16; /* [31:16], r/w, 0x0 */
} BF;
uint32_t WORD;
} tzc_rom1_r0;
/* 0x50 : tzc_rom1_r1 */
union {
struct
{
uint32_t tzc_rom1_r1_end : 16; /* [15: 0], r/w, 0xffff */
uint32_t tzc_rom1_r1_start : 16; /* [31:16], r/w, 0x0 */
} BF;
uint32_t WORD;
} tzc_rom1_r1;
};
typedef volatile struct tzc_sec_reg tzc_sec_reg_t;
#endif /* __TZC_SEC_REG_H__ */

394
drivers/soc/bl602/bl602_std/src/bl602_ef_cfg.c
View file

@ -33,36 +33,13 @@
*
******************************************************************************
*/
#include "string.h"
#include "bflb_ef_ctrl.h"
#include "bl602_ef_cfg.h"
#include "bl602_glb.h"
#include "hardware/ef_data_reg.h"
/** @addtogroup BL702_Peripheral_Driver
* @{
*/
extern int bflb_efuse_read_mac_address_opt(uint8_t slot, uint8_t mac[6], uint8_t reload);
/** @addtogroup SEC_EF_CTRL
* @{
*/
/** @defgroup SEC_EF_CTRL_Private_Macros
* @{
*/
/*@} end of group SEC_EF_CTRL_Private_Macros */
/** @defgroup SEC_EF_CTRL_Private_Types
* @{
*/
/*@} end of group SEC_EF_CTRL_Private_Types */
/** @defgroup SEC_EF_CTRL_Private_Variables
* @{
*/
static bflb_ef_ctrl_com_trim_cfg trim_list[] = {
static bflb_ef_ctrl_com_trim_cfg_t trim_list[] = {
{
.name = "rc32m",
.en_addr = 0x78 * 8 + 1,
@ -93,81 +70,9 @@ static bflb_ef_ctrl_com_trim_cfg trim_list[] = {
}
};
#define EF_CTRL_DEVICE_INFO_OFFSET 0x18
/* 0x14 : ef_wifi_mac_low */
#define EF_DATA_EF_WIFI_MAC_LOW_OFFSET (0x14)
/* 0x18 : ef_wifi_mac_high */
#define EF_DATA_EF_WIFI_MAC_HIGH_OFFSET (0x18)
/* 0x1C : ef_key_slot_0_w0 */
#define EF_DATA_EF_KEY_SLOT_0_W0_OFFSET (0x1C)
/* 0x20 : ef_key_slot_0_w1 */
#define EF_DATA_EF_KEY_SLOT_0_W1_OFFSET (0x20)
/* 0x24 : ef_key_slot_0_w2 */
#define EF_DATA_EF_KEY_SLOT_0_W2_OFFSET (0x24)
/* 0x28 : ef_key_slot_0_w3 */
#define EF_DATA_EF_KEY_SLOT_0_W3_OFFSET (0x28)
/* 0x2C : ef_key_slot_1_w0 */
#define EF_DATA_EF_KEY_SLOT_1_W0_OFFSET (0x2C)
/* 0x30 : ef_key_slot_1_w1 */
#define EF_DATA_EF_KEY_SLOT_1_W1_OFFSET (0x30)
/* 0x34 : ef_key_slot_1_w2 */
#define EF_DATA_EF_KEY_SLOT_1_W2_OFFSET (0x34)
/* 0x38 : ef_key_slot_1_w3 */
#define EF_DATA_EF_KEY_SLOT_1_W3_OFFSET (0x38)
/* 0x3C : ef_key_slot_2_w0 */
#define EF_DATA_EF_KEY_SLOT_2_W0_OFFSET (0x3C)
/* 0x40 : ef_key_slot_2_w1 */
#define EF_DATA_EF_KEY_SLOT_2_W1_OFFSET (0x40)
/* 0x44 : ef_key_slot_2_w2 */
#define EF_DATA_EF_KEY_SLOT_2_W2_OFFSET (0x44)
/* 0x48 : ef_key_slot_2_w3 */
#define EF_DATA_EF_KEY_SLOT_2_W3_OFFSET (0x48)
/* 0x4C : ef_key_slot_3_w0 */
#define EF_DATA_EF_KEY_SLOT_3_W0_OFFSET (0x4C)
/* 0x50 : ef_key_slot_3_w1 */
#define EF_DATA_EF_KEY_SLOT_3_W1_OFFSET (0x50)
/* 0x54 : ef_key_slot_3_w2 */
#define EF_DATA_EF_KEY_SLOT_3_W2_OFFSET (0x54)
/* 0x58 : ef_key_slot_3_w3 */
#define EF_DATA_EF_KEY_SLOT_3_W3_OFFSET (0x58)
/* 0x5C : ef_key_slot_4_w0 */
#define EF_DATA_EF_KEY_SLOT_4_W0_OFFSET (0x5C)
/* 0x60 : ef_key_slot_4_w1 */
#define EF_DATA_EF_KEY_SLOT_4_W1_OFFSET (0x60)
/* 0x64 : ef_key_slot_4_w2 */
#define EF_DATA_EF_KEY_SLOT_4_W2_OFFSET (0x64)
/* 0x68 : ef_key_slot_4_w3 */
#define EF_DATA_EF_KEY_SLOT_4_W3_OFFSET (0x68)
/* 0x6C : ef_key_slot_5_w0 */
#define EF_DATA_EF_KEY_SLOT_5_W0_OFFSET (0x6C)
/* 0x70 : ef_key_slot_5_w1 */
#define EF_DATA_EF_KEY_SLOT_5_W1_OFFSET (0x70)
/* 0x74 : ef_key_slot_5_w2 */
#define EF_DATA_EF_KEY_SLOT_5_W2_OFFSET (0x74)
/* 0x78 : ef_key_slot_5_w3 */
#define EF_DATA_EF_KEY_SLOT_5_W3_OFFSET (0x78)
static GLB_ROOT_CLK_Type rtClk;
static uint8_t bdiv, hdiv;
/*@} end of group SEC_EF_CTRL_Private_Variables */
/** @defgroup SEC_EF_CTRL_Global_Variables
* @{
*/
/*@} end of group SEC_EF_CTRL_Global_Variables */
/** @defgroup SEC_EF_CTRL_Private_Fun_Declaration
* @{
*/
/*@} end of group SEC_EF_CTRL_Private_Fun_Declaration */
/** @defgroup SEC_EF_CTRL_Private_Functions
* @{
*/
/****************************************************************************/ /**
* @brief Efuse read write switch clock save
*
@ -176,7 +81,7 @@ static uint8_t bdiv, hdiv;
* @return None
*
*******************************************************************************/
void ATTR_TCM_SECTION bflb_efuse_switch_cpu_clock_save(void)
void ATTR_TCM_SECTION bflb_efuse_switch_cpu_clock_save(void)
{
/* all API should be place at tcm section */
bdiv = GLB_Get_BCLK_Div();
@ -201,6 +106,20 @@ void ATTR_TCM_SECTION bflb_efuse_switch_cpu_clock_restore(void)
HBN_Set_ROOT_CLK_Sel(rtClk);
}
/****************************************************************************/ /**
* @brief Efuse get trim list
*
* @param trim_list: Trim list pointer
*
* @return Trim list count
*
*******************************************************************************/
uint32_t bflb_ef_ctrl_get_common_trim_list(const bflb_ef_ctrl_com_trim_cfg_t **ptrim_list)
{
*ptrim_list = &trim_list[0];
return sizeof(trim_list) / sizeof(trim_list[0]);
}
/****************************************************************************/ /**
* @brief Efuse read device info
*
@ -212,26 +131,283 @@ void ATTR_TCM_SECTION bflb_efuse_switch_cpu_clock_restore(void)
void bflb_ef_ctrl_get_device_info(bflb_efuse_device_info_type *deviceInfo)
{
uint32_t *p = (uint32_t *)deviceInfo;
uint32_t tmpval;
bflb_ef_ctrl_read_direct(NULL, EF_CTRL_DEVICE_INFO_OFFSET, p, 1, 1);
bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_WIFI_MAC_HIGH_OFFSET, p, 1, 1);
bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_CFG_0_OFFSET, &tmpval, 1, 1);
deviceInfo->chip_ver = (tmpval >> 8) & 0x7;
}
void bflb_efuse_get_chipid(uint8_t chipid[8])
{
bflb_efuse_read_mac_address_opt(0, chipid, 1);
chipid[6] = 0;
chipid[7] = 0;
}
/****************************************************************************/ /**
* @brief Efuse get trim list
* @brief Whether MAC address slot is empty
*
* @param trim_list: Trim list pointer
* @param slot: MAC address slot
* @param reload: whether reload to check
*
* @return Trim list count
* @return 0 for all slots full,1 for others
*
*******************************************************************************/
uint32_t bflb_ef_ctrl_get_common_trim_list(const bflb_ef_ctrl_com_trim_cfg **ptrim_list)
uint8_t bflb_efuse_is_mac_address_slot_empty(uint8_t slot, uint8_t reload)
{
*ptrim_list = &trim_list[0];
return sizeof(trim_list) / sizeof(trim_list[0]);
uint32_t tmp1 = 0xffffffff, tmp2 = 0xffffffff;
uint32_t part1Empty = 0, part2Empty = 0;
if (slot == 0) {
bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_WIFI_MAC_LOW_OFFSET, &tmp1, 1, reload);
bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_WIFI_MAC_HIGH_OFFSET, &tmp2, 1, reload);
} else if (slot == 1) {
bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_KEY_SLOT_5_W0_OFFSET, &tmp1, 1, reload);
bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_KEY_SLOT_5_W1_OFFSET, &tmp2, 1, reload);
} else if (slot == 2) {
bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_DBG_PWD_LOW_OFFSET, &tmp1, 1, reload);
bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_DBG_PWD_HIGH_OFFSET, &tmp2, 1, reload);
}
part1Empty = (bflb_ef_ctrl_is_all_bits_zero(tmp1, 0, 32));
part2Empty = (bflb_ef_ctrl_is_all_bits_zero(tmp2, 0, 22));
return (part1Empty && part2Empty);
}
/*@} end of group SEC_EF_CTRL_Public_Functions */
/****************************************************************************/ /**
* @brief Efuse write optional MAC address
*
* @param slot: MAC address slot
* @param mac[6]: MAC address buffer
* @param program: Whether program
*
* @return 0 or -1
*
*******************************************************************************/
int bflb_efuse_write_mac_address_opt(uint8_t slot, uint8_t mac[6], uint8_t program)
{
uint8_t *maclow = (uint8_t *)mac;
uint8_t *machigh = (uint8_t *)(mac + 4);
uint32_t tmpval;
uint32_t i = 0, cnt;
/*@} end of group SEC_EF_CTRL */
if (slot >= 3) {
return -1;
}
/*@} end of group BL702_Peripheral_Driver */
/* Change to local order */
for (i = 0; i < 3; i++) {
tmpval = mac[i];
mac[i] = mac[5 - i];
mac[5 - i] = tmpval;
}
/* The low 32 bits */
tmpval = BL_RDWD_FRM_BYTEP(maclow);
if (slot == 0) {
bflb_ef_ctrl_write_direct(NULL, EF_DATA_EF_WIFI_MAC_LOW_OFFSET, &tmpval, 1, program);
} else if (slot == 1) {
bflb_ef_ctrl_write_direct(NULL, EF_DATA_EF_KEY_SLOT_5_W0_OFFSET, &tmpval, 1, program);
} else if (slot == 2) {
bflb_ef_ctrl_write_direct(NULL, EF_DATA_EF_DBG_PWD_LOW_OFFSET, &tmpval, 1, program);
}
/* The high 16 bits */
tmpval = machigh[0] + (machigh[1] << 8);
cnt = 0;
for (i = 0; i < 6; i++) {
cnt += bflb_ef_ctrl_get_byte_zero_cnt(mac[i]);
}
tmpval |= ((cnt & 0x3f) << 16);
if (slot == 0) {
bflb_ef_ctrl_write_direct(NULL, EF_DATA_EF_WIFI_MAC_HIGH_OFFSET, &tmpval, 1, program);
} else if (slot == 1) {
bflb_ef_ctrl_write_direct(NULL, EF_DATA_EF_KEY_SLOT_5_W1_OFFSET, &tmpval, 1, program);
} else if (slot == 2) {
bflb_ef_ctrl_write_direct(NULL, EF_DATA_EF_DBG_PWD_HIGH_OFFSET, &tmpval, 1, program);
}
return 0;
}
/****************************************************************************/ /**
* @brief Efuse read optional MAC address
*
* @param slot: MAC address slot
* @param mac[6]: MAC address buffer
* @param reload: Whether reload
*
* @return 0 or -1
*
*******************************************************************************/
int bflb_efuse_read_mac_address_opt(uint8_t slot, uint8_t mac[6], uint8_t reload)
{
uint8_t *maclow = (uint8_t *)mac;
uint8_t *machigh = (uint8_t *)(mac + 4);
uint32_t tmpval = 0;
uint32_t i = 0;
uint32_t cnt = 0;
if (slot >= 3) {
return -1;
}
if (slot == 0) {
bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_WIFI_MAC_LOW_OFFSET, &tmpval, 1, reload);
} else if (slot == 1) {
bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_KEY_SLOT_5_W0_OFFSET, &tmpval, 1, reload);
} else if (slot == 2) {
bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_DBG_PWD_LOW_OFFSET, &tmpval, 1, reload);
}
BL_WRWD_TO_BYTEP(maclow, tmpval);
if (slot == 0) {
bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_WIFI_MAC_HIGH_OFFSET, &tmpval, 1, reload);
} else if (slot == 1) {
bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_KEY_SLOT_5_W1_OFFSET, &tmpval, 1, reload);
} else if (slot == 2) {
bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_DBG_PWD_HIGH_OFFSET, &tmpval, 1, reload);
}
machigh[0] = tmpval & 0xff;
machigh[1] = (tmpval >> 8) & 0xff;
/* Check parity */
for (i = 0; i < 6; i++) {
cnt += bflb_ef_ctrl_get_byte_zero_cnt(mac[i]);
}
if ((cnt & 0x3f) == ((tmpval >> 16) & 0x3f)) {
/* Change to network order */
for (i = 0; i < 3; i++) {
tmpval = mac[i];
mac[i] = mac[5 - i];
mac[5 - i] = tmpval;
}
return 0;
} else {
return -1;
}
}
float bflb_efuse_get_adc_trim(void)
{
bflb_ef_ctrl_com_trim_t trim;
uint32_t tmp;
float coe = 1.0;
bflb_ef_ctrl_read_common_trim(NULL, "gpadc_gain", &trim, 1);
if (trim.en) {
if (trim.parity == bflb_ef_ctrl_get_trim_parity(trim.value, trim.len)) {
tmp = trim.value;
if (tmp & 0x800) {
tmp = ~tmp;
tmp += 1;
tmp = tmp & 0xfff;
coe = (1.0 + ((float)tmp / 2048.0));
} else {
coe = (1.0 - ((float)tmp / 2048.0));
}
}
}
return coe;
}
uint32_t bflb_efuse_get_adc_tsen_trim(void)
{
bflb_ef_ctrl_com_trim_t trim;
bflb_ef_ctrl_read_common_trim(NULL, "tsen", &trim, 1);
if (trim.en) {
if (trim.parity == bflb_ef_ctrl_get_trim_parity(trim.value, trim.len)) {
return trim.value;
}
}
return 2042;
}
void bflb_efuse_read_secure_boot(uint8_t *sign, uint8_t *aes)
{
uint32_t tmpval = 0;
bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_CFG_0_OFFSET, &tmpval, 1, 1);
*sign = ((tmpval & EF_DATA_EF_SBOOT_SIGN_MODE_MSK) >> EF_DATA_EF_SBOOT_SIGN_MODE_POS) & 0x01;
*aes = ((tmpval & EF_DATA_EF_SF_AES_MODE_MSK) >> EF_DATA_EF_SF_AES_MODE_POS);
}
void bflb_efuse_write_aes_key(uint8_t index, uint8_t *data, uint32_t len)
{
if (index > 5) {
return;
}
bflb_ef_ctrl_write_direct(NULL, 0x1C + index * 4, (uint32_t *)data, len, 1);
}
void bflb_efuse_read_aes_key(uint8_t index, uint8_t *data, uint32_t len)
{
if (index > 5) {
return;
}
bflb_ef_ctrl_read_direct(NULL, 0x1C + index * 4, (uint32_t *)data, len, 1);
}
void bflb_efuse_lock_aes_key_write(uint8_t index)
{
uint32_t lock = 0;
if (index > 5) {
return;
}
/* write lock */
if (index <= 3) {
lock |= (1 << (index + 19));
} else {
lock |= (1 << (index + 19));
lock |= (1 << (index - 4 + 13));
}
bflb_ef_ctrl_write_direct(NULL, 0x7c, &lock, 1, 1);
}
void bflb_efuse_lock_aes_key_read(uint8_t index)
{
uint32_t lock = 0;
if (index > 5) {
return;
}
/* read lock */
lock |= (1 << (index + 26));
bflb_ef_ctrl_write_direct(NULL, 0x7c, &lock, 1, 1);
}
void bflb_efuse_write_sw_usage(uint32_t index, uint32_t usage, uint8_t program)
{
if (index != 0) {
return;
}
bflb_ef_ctrl_write_direct(NULL, EF_DATA_EF_SW_USAGE_0_OFFSET + index * 4, &usage, 1, program);
}
void bflb_efuse_read_sw_usage(uint32_t index, uint32_t *usage)
{
if (index != 0) {
return;
}
bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_SW_USAGE_0_OFFSET + index * 4, (uint32_t *)usage, 1, 1);
}

237
drivers/soc/bl602/bl602_std/src/bl602_tzc_sec.c Normal file
View file

@ -0,0 +1,237 @@
/**
******************************************************************************
* @file bl602_tzc_sec.c
* @version V1.0
* @date
* @brief This file is the standard driver c file
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#include "string.h"
#include "bl602_tzc_sec.h"
/** @addtogroup BL602_Peripheral_Driver
* @{
*/
/** @addtogroup TZC_SEC
* @{
*/
/** @defgroup TZC_SEC_Private_Macros
* @{
*/
/*@} end of group TZC_SEC_Private_Macros */
/** @defgroup TZC_SEC_Private_Types
* @{
*/
/*@} end of group TZC_SEC_Private_Types */
/** @defgroup TZC_SEC_Private_Variables
* @{
*/
/*@} end of group TZC_SEC_Private_Variables */
/** @defgroup TZC_SEC_Global_Variables
* @{
*/
/*@} end of group TZC_SEC_Global_Variables */
/** @defgroup TZC_SEC_Private_Fun_Declaration
* @{
*/
/*@} end of group TZC_SEC_Private_Fun_Declaration */
/** @defgroup TZC_SEC_Public_Functions
* @{
*/
/****************************************************************************/ /**
* @brief TZC Security boot set
*
* @param Val: 0 for security boot start, and 0xf for security boot finished
*
* @return None
*
*******************************************************************************/
void TZC_Sboot_Set(uint8_t Val)
{
uint32_t tmpVal;
tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_CTRL);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_SBOOT_DONE, Val);
BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_CTRL, tmpVal);
}
/****************************************************************************/ /**
* @brief TZC Set ROM0 R0 protect range
*
* @param start: Start address to protect
* @param length: length to protect
*
* @return None
*
*******************************************************************************/
void TZC_Set_Rom0_R0_Protect(uint32_t start, uint32_t length)
{
uint32_t tmpVal;
uint32_t alignEnd = (start+length+1023)&~0x3FF;
/* Set Range */
tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM0_R0);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM0_R0_START, ((start >> 10)&0xffff));
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM0_R0_END, ((alignEnd >> 10)&0xffff)-1);
BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM0_R0, tmpVal);
/* Enable */
tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_CTRL);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM0_R0_ID0_EN, 0);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM0_R0_ID1_EN, 0);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM0_R0_EN, 1);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM0_R0_LOCK, 1);
BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_CTRL, tmpVal);
}
/****************************************************************************/ /**
* @brief TZC Set ROM0 R1 protect range
*
* @param start: Start address to protect
* @param length: length to protect
*
* @return None
*
*******************************************************************************/
void TZC_Set_Rom0_R1_Protect(uint32_t start, uint32_t length)
{
uint32_t tmpVal;
uint32_t alignEnd = (start+length+1023)&~0x3FF;
/* Set Range */
tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM0_R1);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM0_R1_START, ((start >> 10)&0xffff));
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM0_R1_END, ((alignEnd >> 10)&0xffff)-1);
BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM0_R1, tmpVal);
/* Enable */
tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_CTRL);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM0_R1_ID0_EN, 0);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM0_R1_ID1_EN, 0);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM0_R1_EN, 1);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM0_R1_LOCK, 1);
BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_CTRL, tmpVal);
}
/****************************************************************************/ /**
* @brief TZC Set ROM1 R0 protect range
*
* @param start: Start address to protect
* @param length: length to protect
*
* @return None
*
*******************************************************************************/
void TZC_Set_Rom1_R0_Protect(uint32_t start, uint32_t length)
{
uint32_t tmpVal;
uint32_t alignEnd = (start+length+1023)&~0x3FF;
/* Set Range */
tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM1_R0);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM1_R0_START, ((start >> 10)&0xffff));
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM1_R0_END, ((alignEnd >> 10)&0xffff)-1);
BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM1_R0, tmpVal);
/* Enable */
tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_CTRL);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM1_R0_ID0_EN, 0);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM1_R0_ID1_EN, 0);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM1_R0_EN, 1);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM1_R0_LOCK, 1);
BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_CTRL, tmpVal);
}
/****************************************************************************/ /**
* @brief TZC Set ROM1 R1 protect range
*
* @param start: Start address to protect
* @param length: length to protect
*
* @return None
*
*******************************************************************************/
void TZC_Set_Rom1_R1_Protect(uint32_t start, uint32_t length)
{
uint32_t tmpVal;
uint32_t alignEnd = (start+length+1023)&~0x3FF;
/* Set Range */
tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM1_R1);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM1_R1_START, ((start >> 10)&0xffff));
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM1_R1_END, ((alignEnd >> 10)&0xffff)-1);
BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM1_R1, tmpVal);
/* Enable */
tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_CTRL);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM1_R1_ID0_EN, 0);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM1_R1_ID1_EN, 0);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM1_R1_EN, 1);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM1_R1_LOCK, 1);
BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_CTRL, tmpVal);
}
/*@} end of group TZC_SEC_Public_Functions */
/*@} end of group TZC_SEC */
/*@} end of group BL602_Peripheral_Driver */

82
drivers/soc/bl602/port/bl602_efuse.c
View file

@ -1,82 +0,0 @@
#include "bflb_efuse.h"
#include "bflb_ef_ctrl.h"
#include "bl602_ef_cfg.h"
float bflb_efuse_get_adc_trim(void)
{
bflb_ef_ctrl_com_trim_type trim;
uint32_t tmp;
float coe = 1.0;
bflb_ef_ctrl_read_common_trim(NULL, "gpadc_gain", &trim, 1);
if (trim.en) {
if (trim.parity == bflb_ef_ctrl_get_trim_parity(trim.value, trim.len)) {
tmp = trim.value;
if (tmp & 0x800) {
tmp = ~tmp;
tmp += 1;
tmp = tmp & 0xfff;
coe = (1.0 + ((float)tmp / 2048.0));
} else {
coe = (1.0 - ((float)tmp / 2048.0));
}
}
}
return coe;
}
uint32_t bflb_efuse_get_adc_tsen_trim(void)
{
bflb_ef_ctrl_com_trim_type trim;
bflb_ef_ctrl_read_common_trim(NULL,"tsen", &trim,1);
if (trim.en) {
if (trim.parity == bflb_ef_ctrl_get_trim_parity(trim.value, trim.len)) {
return trim.value;
}
}
return 2042;
}
void bflb_efuse_write_aes_key(uint8_t index, uint8_t *data, uint32_t len)
{
bflb_ef_ctrl_write_direct(NULL, 0x1C + index * 4, (uint32_t *)data, len, 1);
}
void bflb_efuse_lock_aes_key_write(uint8_t index)
{
uint32_t lock = 0;
if (index > 5) {
return;
}
/* write lock */
if (index <= 3) {
lock |= (1 << (index + 19));
} else {
lock |= (1 << (index + 19));
lock |= (1 << (index - 4 + 13));
}
bflb_ef_ctrl_write_direct(NULL, 0x7c, (uint32_t *)lock, 1, 1);
}
void bflb_efuse_lock_aes_key_read(uint8_t index)
{
uint32_t lock = 0;
if (index > 5) {
return;
}
/* read lock */
lock |= (1 << (index + 26));
bflb_ef_ctrl_write_direct(NULL, 0x7c, (uint32_t *)lock, 1, 1);
}
void bflb_efuse_read_aes_key(uint8_t index, uint8_t *data, uint32_t len)
{
bflb_ef_ctrl_read_direct(NULL, 0x1C + index * 4, (uint32_t *)data, len, 1);
}

1
drivers/soc/bl616/CMakeLists.txt
View file

@ -33,7 +33,6 @@ sdk_library_add_sources(bl616_std/src/bl616_psram.c)
sdk_library_add_sources(port/bl616_clock.c)
sdk_library_add_sources(port/bl616_flash.c)
sdk_library_add_sources(port/bl616_efuse.c)
sdk_add_include_directories(
bl616_std/include

165
drivers/soc/bl616/bl616_std/include/bl616_audac.h Normal file
View file

@ -0,0 +1,165 @@
#ifndef _BFLB_AUDAC_H
#define _BFLB_AUDAC_H
#include "bflb_core.h"
/**
* @defgroup AUDAC_SAMPLING_RATE audac sampling rate
*/
#define AUDAC_SAMPLING_RATE_8K 0
#define AUDAC_SAMPLING_RATE_16K 1
#define AUDAC_SAMPLING_RATE_22P05K 5
#define AUDAC_SAMPLING_RATE_24K 3
#define AUDAC_SAMPLING_RATE_32K 2
#define AUDAC_SAMPLING_RATE_44P1K 6
#define AUDAC_SAMPLING_RATE_48K 4
/**
* @}
*/
/**
* @defgroup AUDAC_OUTPUT_MODE audac output mode
*/
#define AUDAC_OUTPUT_MODE_PWM 0
#define AUDAC_OUTPUT_MODE_GPDAC_CH_A 1
#define AUDAC_OUTPUT_MODE_GPDAC_CH_B 2
#define AUDAC_OUTPUT_MODE_GPDAC_CH_A_B 3
/**
* @}
*/
/**
* @defgroup AUDAC_SOURCE_CHANNEL source channels num
*/
#define AUDAC_SOURCE_CHANNEL_SINGLE 0x01
#define AUDAC_SOURCE_CHANNEL_DUAL 0x03
/**
* @}
*/
/**
* @defgroup AUDAC_MIXER_MODE audac mixer mode, this parameter is valid only in AUDAC_SOURCE_CHANNEL_DUAL mode
*/
#define AUDAC_MIXER_MODE_ONLY_L 0
#define AUDAC_MIXER_MODE_ONLY_R 1
#define AUDAC_MIXER_MODE_SUM 2
#define AUDAC_MIXER_MODE_AVERAGE 3
/**
* @}
*/
/**
* @defgroup AUDAC_DATA_FORMAT audac data format
*/
#define AUDAC_DATA_FORMAT_16BIT 3
#define AUDAC_DATA_FORMAT_20BIT 2
#define AUDAC_DATA_FORMAT_24BIT 1
#define AUDAC_DATA_FORMAT_32BIT 0
/**
* @}
*/
/**
* @defgroup AUDAC_RAMP_RATE audac volume ramp rate
*/
#define AUDAC_RAMP_RATE_FS_2 0
#define AUDAC_RAMP_RATE_FS_4 1
#define AUDAC_RAMP_RATE_FS_8 2
#define AUDAC_RAMP_RATE_FS_16 3
#define AUDAC_RAMP_RATE_FS_32 4
#define AUDAC_RAMP_RATE_FS_64 5
#define AUDAC_RAMP_RATE_FS_128 6
#define AUDAC_RAMP_RATE_FS_256 7
#define AUDAC_RAMP_RATE_FS_512 8
#define AUDAC_RAMP_RATE_FS_1024 9
#define AUDAC_RAMP_RATE_FS_2048 10
/**
* @}
*/
/**
* @defgroup AUDAC_VOLUME_UPDATE_MODE audac volume ramp rate
*/
#define AUDAC_VOLUME_UPDATE_MODE_FORCE 0
#define AUDAC_VOLUME_UPDATE_MODE_RAMP 1
#define AUDAC_VOLUME_UPDATE_MODE_RAMP_ZERO_CROSSING 2
/**
* @}
*/
/** @defgroup AUDAC_INTSTS audac interrupt status definition
* @{
*/
#define AUDAC_INTSTS_VOLUME_RAMP (1 << 0)
#define AUDAC_INTSTS_FIFO_OVER (1 << 1)
#define AUDAC_INTSTS_FIFO_UNDER (1 << 2)
#define AUDAC_INTSTS_FIFO_AVAILABLE (1 << 3)
/** @defgroup AUDAC_CMD audac feature control cmd definition
* @{
*/
#define AUDAC_CMD_PLAY_START (0x01)
#define AUDAC_CMD_PLAY_STOP (0x02)
#define AUDAC_CMD_SET_MUTE (0x03)
#define AUDAC_CMD_SET_VOLUME_VAL (0x04)
#define AUDAC_CMD_CLEAR_TX_FIFO (0x05)
#define AUDAC_CMD_GET_TX_FIFO_CNT (0x06)
/**
* @}
*/
/**
* @brief AUDAC initialization configuration structure
*
* @param sampling_rate AUDAC sampling rate, use @ref AUDAC_SAMPLING_RATE
* @param output_mode AUDAC mode, use @ref AUDAC_OUTPUT_MODE
* @param source_channels_num AUDAC source channels num, use @ref AUDAC_SOURCE_CHANNEL
* @param mixer_mode AUDAC mixer mode, valid only in AUDAC_SOURCE_CHANNEL_DUAL mode, use @ref AUDAC_MIXER_MODE
* @param data_format AUDAC audac data format, use @ref AUDAC_DATA_FORMAT
* @param fifo_threshold AUDAC tx fifo threshold, 0 ~ 15
* @param dma_enable AUDAC dma mode enable, use true or false
*/
struct bflb_audac_init_config_s {
uint8_t sampling_rate;
uint8_t output_mode;
uint8_t source_channels_num;
uint8_t mixer_mode;
uint8_t data_format;
uint8_t fifo_threshold;
};
/**
* @brief AUDAC volume configuration structure
*
* @param mute_ramp_en AUDAC mute mode en, use true or false
* @param mute_up_ramp_rate AUDAC mute up ramp rate, valid when mute_ramp_en is true, use @ref AUDAC_RAMP_RATE
* @param mute_down_ramp_rate AUDAC mute down ramp rate, valid when mute_ramp_en is true, use @ref AUDAC_RAMP_RATE
* @param volume_update_mode AUDAC volume update mode, use @ref AUDAC_VOLUME_UPDATE_MODE
* @param volume_ramp_rate AUDAC volume ramp rate, valid when volume_update_mode is not AUDAC_VOLUME_UPDATE_MODE_FORCE, use @ref AUDAC_RAMP_RATE
* @param volume_zero_cross_timeout AUDAC volume update zero cross timeout period, valid only in AUDAC_VOLUME_UPDATE_MODE_RAMP_ZERO_CROSSING mode
*/
struct bflb_audac_volume_config_s {
bool mute_ramp_en;
uint8_t mute_up_ramp_rate;
uint8_t mute_down_ramp_rate;
uint8_t volume_update_mode;
uint8_t volume_ramp_rate;
uint8_t volume_zero_cross_timeout;
};
int bflb_audac_init(struct bflb_device_s *dev, const struct bflb_audac_init_config_s *config);
int bflb_audac_volume_init(struct bflb_device_s *dev, const struct bflb_audac_volume_config_s *vol_cfg);
int bflb_audac_link_rxdma(struct bflb_device_s *dev, bool enable);
int bflb_audac_int_mask(struct bflb_device_s *dev, uint32_t mask);
int bflb_audac_get_intstatus(struct bflb_device_s *dev);
int bflb_audac_int_clear(struct bflb_device_s *dev, uint32_t int_clear);
int bflb_audac_feature_control(struct bflb_device_s *dev, int cmd, size_t arg);
#endif

4
drivers/soc/bl616/bl616_std/include/bl616_common.h
View file

@ -153,7 +153,7 @@ void check_failed(uint8_t *file, uint32_t line);
#define ARCH_MemSet arch_memset
#define ARCH_MemCmp arch_memcmp
#define ARCH_MemCpy4 arch_memcpy4
#define ARCH_MemCpy_Fast arch_memcpy_fast
#define arch_memcpy_fast arch_memcpy_fast
#define ARCH_MemSet4 arch_memset4
#define BFLB_Soft_CRC32 bflb_soft_crc32
#define CPU_Interrupt_Enable(irq)
@ -173,7 +173,7 @@ void arch_delay_ms(uint32_t cnt);
void *ARCH_MemCpy(void *dst, const void *src, uint32_t n);
uint32_t *ARCH_MemCpy4(uint32_t *dst, const uint32_t *src, uint32_t n);
void *ARCH_MemCpy_Fast(void *pdst, const void *psrc, uint32_t n);
void *arch_memcpy_fast(void *pdst, const void *psrc, uint32_t n);
void *ARCH_MemSet(void *s, uint8_t c, uint32_t n);
uint32_t *ARCH_MemSet4(uint32_t *dst, const uint32_t val, uint32_t n);
int ARCH_MemCmp(const void *s1, const void *s2, uint32_t n);

6
drivers/soc/bl616/bl616_std/include/bl616_ef_cfg.h
View file

@ -1,6 +1,6 @@
/**
******************************************************************************
* @file bl616_ef_ctrl.h
* @file bl616_ef_cfg.h
* @version V1.0
* @date
* @brief This file is the standard driver header file
@ -36,7 +36,7 @@
#ifndef __BL616_EF_CFG_H__
#define __BL616_EF_CFG_H__
#include "ef_ctrl_reg.h"
#include "bflb_ef_ctrl.h"
#include "bl616_common.h"
/** @addtogroup BL616_Peripheral_Driver
@ -56,7 +56,7 @@ typedef struct
uint32_t rsvd : 22; /*!< Reserved */
uint32_t deviceInfo : 2; /*!< Efuse device information */
uint32_t psramInfo : 2; /*!< Efuse psram info 0:no psram, 1:WB 4MB*/
uint32_t memoryInfo : 3; /*!< Efuse memory info 0:no memory, 8:1MB flash */
uint32_t memoryInfo : 3; /*!< Efuse memory info 0:no memory, 1:2MB flash, 2:4MB flash, 3:6MB flash, 4:8MB flash */
uint32_t chipInfo : 3; /*!< Efuse chip revision */
} bflb_efuse_device_info_type;

18
drivers/soc/bl616/bl616_std/include/bl616_glb.h
View file

@ -306,6 +306,14 @@ typedef enum {
GLB_PERI_DMA_GAUGE = 20, /*!< gauge */
GLB_PERI_DMA_GPADC = 22, /*!< gpadc */
GLB_PERI_DMA_GPDAC_TX = 23, /*!< gpdac_tx */
GLB_PERI_DMA_PEC_RX0 = 24, /*!< pec_rx0 */
GLB_PERI_DMA_PEC_RX1 = 25, /*!< pec_rx1 */
GLB_PERI_DMA_PEC_RX2 = 26, /*!< pec_rx2 */
GLB_PERI_DMA_PEC_RX3 = 27, /*!< pec_rx3 */
GLB_PERI_DMA_PEC_TX0 = 28, /*!< pec_tx0 */
GLB_PERI_DMA_PEC_TX1 = 29, /*!< pec_tx1 */
GLB_PERI_DMA_PEC_TX2 = 30, /*!< pec_tx2 */
GLB_PERI_DMA_PEC_TX3 = 31, /*!< pec_tx3 */
} GLB_PERI_DMA_Type;
/**
@ -1115,7 +1123,15 @@ typedef union {
((type) == GLB_PERI_DMA_PADC) || \
((type) == GLB_PERI_DMA_GAUGE) || \
((type) == GLB_PERI_DMA_GPADC) || \
((type) == GLB_PERI_DMA_GPDAC_TX))
((type) == GLB_PERI_DMA_GPDAC_TX) || \
((type) == GLB_PERI_DMA_PEC_RX0) || \
((type) == GLB_PERI_DMA_PEC_RX1) || \
((type) == GLB_PERI_DMA_PEC_RX2) || \
((type) == GLB_PERI_DMA_PEC_RX3) || \
((type) == GLB_PERI_DMA_PEC_TX0) || \
((type) == GLB_PERI_DMA_PEC_TX1) || \
((type) == GLB_PERI_DMA_PEC_TX2) || \
((type) == GLB_PERI_DMA_PEC_TX3))
/** @defgroup GLB_PERI_DMA_CN_SEL_TYPE
* @{

10
drivers/soc/bl616/bl616_std/include/bl616_gpio.h
View file

@ -82,10 +82,10 @@ typedef enum {
#define GPIO_PULL_UP ((uint32_t)0x00000000U) /*!< GPIO pull up */
#define GPIO_PULL_DOWN ((uint32_t)0x00000001U) /*!< GPIO pull down */
#define GPIO_PULL_NONE ((uint32_t)0x00000002U) /*!< GPIO no pull up or down */
#define GPIO_OUTPUT_VALUE_MODE ((uint8_t)0x00U) /*!< GPIO Output by reg_gpio_x_o Value */
#define GPIO_SET_CLR_MODE ((uint8_t)0x01U) /*!< GPIO Output set by reg_gpio_x_set and clear by reg_gpio_x_clr */
#define GPIO_DMA_OUTPUT_VALUE_MODE ((uint8_t)0x02U) /*!< GPIO Output value by gpio_dma_o */
#define GPIO_DMA_SET_CLR_MODE ((uint8_t)0x03U) /*!< GPIO Outout value by gpio_dma_set/gpio_dma_clr */
#define GPIO_OUTPUT_VALUE_MODE ((uint8_t)0x00U) /*!< GPIO Output by reg_gpio_x_o Value */
#define GPIO_SET_CLR_MODE ((uint8_t)0x01U) /*!< GPIO Output set by reg_gpio_x_set and clear by reg_gpio_x_clr */
#define GPIO_DMA_OUTPUT_VALUE_MODE ((uint8_t)0x02U) /*!< GPIO Output value by gpio_dma_o */
#define GPIO_DMA_SET_CLR_MODE ((uint8_t)0x03U) /*!< GPIO Outout value by gpio_dma_set/gpio_dma_clr */
typedef enum {
GPIO_FUN_SDH = 0,
@ -110,7 +110,7 @@ typedef enum {
GPIO_FUN_DBI_B = 22,
GPIO_FUN_DBI_C = 23,
GPIO_FUN_DISP_QSPI = 24,
GPIO_FUN_AUPWM = 25,
GPIO_FUN_AUDAC_PWM = 25,
GPIO_FUN_JTAG = 26,
GPIO_FUN_CLOCK_OUT = 31,

31
drivers/soc/bl616/bl616_std/include/bl616_mfg_efuse.h Normal file
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@ -0,0 +1,31 @@
#ifndef __BL616_MFG_EFUSE_H__
#define __BL616_MFG_EFUSE_H__
#include "stdint.h"
uint8_t mfg_efuse_get_rf_cal_slots(void);
void mfg_efuse_set_rf_cal_slots(uint8_t slots);
uint8_t mfg_efuse_is_xtal_capcode_slot_empty(uint8_t reload);
int mfg_efuse_write_xtal_capcode_pre(uint8_t capcode, uint8_t program);
void mfg_efuse_write_xtal_capcode(void);
int mfg_efuse_read_xtal_capcode(uint8_t *capcode, uint8_t reload);
uint8_t mfg_efuse_is_hp_poweroffset_slot_empty(uint8_t reload);
int mfg_efuse_write_hp_poweroffset_pre(int8_t pwr_offset[14], uint8_t program);
void mfg_efuse_write_hp_poweroffset(void);
int mfg_efuse_read_hp_poweroffset(int8_t pwr_offset[14], uint8_t reload);
uint8_t mfg_efuse_is_lp_poweroffset_slot_empty(uint8_t reload);
int mfg_efuse_write_lp_poweroffset_pre(int8_t pwr_offset[14], uint8_t program);
void mfg_efuse_write_lp_poweroffset(void);
int mfg_efuse_read_lp_poweroffset(int8_t pwr_offset[14], uint8_t reload);
uint8_t mfg_efuse_is_macaddr_slot_empty(uint8_t reload);
int8_t mfg_efuse_write_macaddr_pre(uint8_t mac[6], uint8_t program);
void mfg_efuse_write_macaddr(void);
int8_t mfg_efuse_read_macaddr(uint8_t mac[6], uint8_t reload);
uint8_t mfg_efuse_is_bz_poweroffset_slot_empty(uint8_t reload);
int mfg_efuse_write_bz_poweroffset_pre(int8_t pwr_offset[5], uint8_t program);
void mfg_efuse_write_bz_poweroffset(void);
int mfg_efuse_read_bz_poweroffset(int8_t pwr_offset[20], uint8_t reload);
void mfg_efuse_program(uint32_t addr,uint32_t *pword,uint32_t countInword,uint32_t program);
void mfg_efuse_read(uint32_t addr,uint32_t *pword,uint32_t countInword,uint8_t reload);
#endif /*__BL616_MFG_EFUSE_H__*/

36
drivers/soc/bl616/bl616_std/include/bl616_mfg_flash.h Normal file
View file

@ -0,0 +1,36 @@
#ifndef __BL616_MFG_FLASH_H__
#define __BL616_MFG_FLASH_H__
#include "stdint.h"
#include "bl616_xip_sflash.h"
typedef struct rf_para_flash_tag {
uint32_t magic; //"RFPA"
uint8_t capcode_valid; //0x5A
uint8_t capcode;
uint8_t poweroffset_valid; //0x5A
int8_t poweroffset[3];
uint8_t mac_valid; //0x5A
uint8_t mac[6];
uint8_t rsvd[3];
uint32_t crc32;
} rf_para_flash_t;
int mfg_flash_init(SPI_Flash_Cfg_Type *flashCfg);
int mfg_flash_write_xtal_capcode_pre(uint8_t capcode, uint8_t program);
void mfg_flash_write_xtal_capcode(void);
int mfg_flash_read_xtal_capcode(uint8_t *capcode, uint8_t reload);
int mfg_flash_write_hp_poweroffset_pre(int8_t pwrOffset[14], uint8_t program);
void mfg_flash_write_hp_poweroffset(void);
int mfg_flash_read_hp_poweroffset(int8_t pwrOffset[14], uint8_t reload);
int mfg_flash_write_lp_poweroffset_pre(int8_t pwrOffset[14], uint8_t program);
void mfg_flash_write_lp_poweroffset(void);
int mfg_flash_read_lp_poweroffset(int8_t pwrOffset[14], uint8_t reload);
int mfg_flash_write_macaddr_pre(uint8_t mac[6], uint8_t program);
void mfg_flash_write_macaddr(void);
int mfg_flash_read_macaddr(uint8_t mac[6], uint8_t reload);
int mfg_flash_write_bz_poweroffset_pre(int8_t pwrOffset[5], uint8_t program);
void mfg_flash_write_bz_poweroffset(void);
int mfg_flash_read_bz_poweroffset(int8_t pwrOffset[20], uint8_t reload);
#endif /*__BL616_MFG_FLASH_H__*/

52
drivers/soc/bl616/bl616_std/include/bl616_mfg_media.h Normal file
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@ -0,0 +1,52 @@
#ifndef __BL616_MFG_MEDIA_H__
#define __BL616_MFG_MEDIA_H__
#include "stdint.h"
#include "bl616_mfg_efuse.h"
#include "bl616_mfg_flash.h"
int mfg_media_init_need_lock(SPI_Flash_Cfg_Type *flashCfg);
int mfg_media_init_with_lock(SPI_Flash_Cfg_Type *flashCfg);
uint8_t mfg_media_is_xtal_capcode_slot_empty(uint8_t reload);
int mfg_media_write_xtal_capcode_pre_need_lock(uint8_t capcode, uint8_t program);
int mfg_media_write_xtal_capcode_pre_with_lock(uint8_t capcode, uint8_t program);
void mfg_media_write_xtal_capcode_need_lock(void);
void mfg_media_write_xtal_capcode_with_lock(void);
int mfg_media_read_xtal_capcode_need_lock(uint8_t *capcode, uint8_t reload);
int mfg_media_read_xtal_capcode_with_lock(uint8_t *capcode, uint8_t reload);
int mfg_media_read_xtal_capcode(uint8_t *capcode, uint8_t reload);
uint8_t mfg_media_is_hp_poweroffset_slot_empty(uint8_t reload);
int mfg_media_write_hp_poweroffset_pre_need_lock(int8_t pwrOffset[14], uint8_t program);
int mfg_media_write_hp_poweroffset_pre_with_lock(int8_t pwrOffset[14], uint8_t program);
void mfg_media_write_hp_poweroffset_need_lock(void);
void mfg_media_write_hp_poweroffset_with_lock(void);
int mfg_media_read_hp_poweroffset_need_lock(int8_t pwrOffset[14], uint8_t reload);
int mfg_media_read_hp_poweroffset_with_lock(int8_t pwrOffset[14], uint8_t reload);
int mfg_media_read_hp_poweroffset(int8_t pwrOffset[14], uint8_t reload);
uint8_t mfg_media_is_lp_poweroffset_slot_empty(uint8_t reload);
int mfg_media_write_lp_poweroffset_pre_need_lock(int8_t pwrOffset[14], uint8_t program);
int mfg_media_write_lp_poweroffset_pre_with_lock(int8_t pwrOffset[14], uint8_t program);
void mfg_media_write_lp_poweroffset_need_lock(void);
void mfg_media_write_lp_poweroffset_with_lock(void);
int mfg_media_read_lp_poweroffset_need_lock(int8_t pwrOffset[14], uint8_t reload);
int mfg_media_read_lp_poweroffset_with_lock(int8_t pwrOffset[14], uint8_t reload);
int mfg_media_read_lp_poweroffset(int8_t pwrOffset[14], uint8_t reload);
uint8_t mfg_media_is_macaddr_slot_empty(uint8_t reload);
int mfg_media_write_macaddr_pre_need_lock(uint8_t mac[6], uint8_t program);
int mfg_media_write_macaddr_pre_with_lock(uint8_t mac[6], uint8_t program);
void mfg_media_write_macaddr_need_lock(void);
void mfg_media_write_macaddr_with_lock(void);
int mfg_media_read_macaddr_need_lock(uint8_t mac[6], uint8_t reload);
int mfg_media_read_macaddr_with_lock(uint8_t mac[6], uint8_t reload);
int mfg_media_read_macaddr(uint8_t mac[6], uint8_t reload);
uint8_t mfg_media_is_bz_poweroffset_slot_empty(uint8_t reload);
int mfg_media_write_bz_poweroffset_pre_need_lock(int8_t pwrOffset[5], uint8_t program);
int mfg_media_write_bz_poweroffset_pre_with_lock(int8_t pwrOffset[5], uint8_t program);
void mfg_media_write_bz_poweroffset_need_lock(void);
void mfg_media_write_bz_poweroffset_with_lock(void);
int mfg_media_read_bz_poweroffset_need_lock(int8_t pwrOffset[5], uint8_t reload);
int mfg_media_read_bz_poweroffset_with_lock(int8_t pwrOffset[5], uint8_t reload);
int mfg_media_read_bz_poweroffset(int8_t pwrOffset[5], uint8_t reload);
#endif /*__BL616_MFG_MEDIA_H__*/

1
drivers/soc/bl616/bl616_std/include/bl616_tzc_sec.h
View file

@ -232,6 +232,7 @@ void Tzc_Sec_Flash_Access_Set_Regionx(uint8_t group);
void Tzc_Sec_PSRAMB_Access_Set(uint8_t region, uint32_t startAddr, uint32_t length, uint8_t group);
void Tzc_Sec_PSRAMB_Access_Set_Advance(uint8_t region, uint32_t startAddr, uint32_t length, uint8_t group);
void Tzc_Sec_PSRAMB_Access_Release(void);
void Tzc_Sec_HBNRAM_Access_Set(uint32_t startAddr, uint32_t length);
void Tzc_Sec_Set_Se_Ctrl_Mode(TZC_SEC_SE_Ctrl_Mode mode);
void Tzc_Sec_Set_Sf_Ctrl_Mode(TZC_SEC_SF_Ctrl_Mode mode);
void Tzc_Sec_Set_Se_Group(TZC_SEC_SE_Ctrl_Type slaveType, uint8_t group);

27
drivers/soc/bl616/bl616_std/include/hardware/aon_reg.h
View file

@ -1221,6 +1221,33 @@
#define AON_HBNCORE_RESV1_DATA_MSK (((1U << AON_HBNCORE_RESV1_DATA_LEN) - 1) << AON_HBNCORE_RESV1_DATA_POS)
#define AON_HBNCORE_RESV1_DATA_UMSK (~(((1U << AON_HBNCORE_RESV1_DATA_LEN) - 1) << AON_HBNCORE_RESV1_DATA_POS))
/* 0xf00 : hbnram ctrl */
#define AON_TZC_HBNRAM_CTRL_OFFSET (0xF00)
#define AON_TZC_HBNRAM_R0_EN AON_TZC_HBNRAM_R0_EN
#define AON_TZC_HBNRAM_R0_EN_POS (16U)
#define AON_TZC_HBNRAM_R0_EN_LEN (1U)
#define AON_TZC_HBNRAM_R0_EN_MSK (((1U << AON_TZC_HBNRAM_R0_EN_LEN) - 1) << AON_TZC_HBNRAM_R0_EN_POS)
#define AON_TZC_HBNRAM_R0_EN_UMSK (~(((1U << AON_TZC_HBNRAM_R0_EN_LEN) - 1) << AON_TZC_HBNRAM_R0_EN_POS))
#define AON_TZC_HBNRAM_R0_LOCK AON_TZC_HBNRAM_R0_LOCK
#define AON_TZC_HBNRAM_R0_LOCK_POS (24U)
#define AON_TZC_HBNRAM_R0_LOCK_LEN (1U)
#define AON_TZC_HBNRAM_R0_LOCK_MSK (((1U << AON_TZC_HBNRAM_R0_LOCK_LEN) - 1) << AON_TZC_HBNRAM_R0_LOCK_POS)
#define AON_TZC_HBNRAM_R0_LOCK_UMSK (~(((1U << AON_TZC_HBNRAM_R0_LOCK_LEN) - 1) << AON_TZC_HBNRAM_R0_LOCK_POS))
/* 0xf04 : hbnram r0 */
#define AON_TZC_HBNRAM_R0_OFFSET (0xF04)
#define AON_TZC_HBNRAM_R0_END AON_TZC_HBNRAM_R0_END
#define AON_TZC_HBNRAM_R0_END_POS (0U)
#define AON_TZC_HBNRAM_R0_END_LEN (11U)
#define AON_TZC_HBNRAM_R0_END_MSK (((1U << AON_TZC_HBNRAM_R0_END_LEN) - 1) << AON_TZC_HBNRAM_R0_END_POS)
#define AON_TZC_HBNRAM_R0_END_UMSK (~(((1U << AON_TZC_HBNRAM_R0_END_LEN) - 1) << AON_TZC_HBNRAM_R0_END_POS))
#define AON_TZC_HBNRAM_R0_START AON_TZC_HBNRAM_R0_START
#define AON_TZC_HBNRAM_R0_START_POS (16U)
#define AON_TZC_HBNRAM_R0_START_LEN (11U)
#define AON_TZC_HBNRAM_R0_START_MSK (((1U << AON_TZC_HBNRAM_R0_START_LEN) - 1) << AON_TZC_HBNRAM_R0_START_POS)
#define AON_TZC_HBNRAM_R0_START_UMSK (~(((1U << AON_TZC_HBNRAM_R0_START_LEN) - 1) << AON_TZC_HBNRAM_R0_START_POS))
struct aon_reg {
/* 0x0 reserved */
uint8_t RESERVED0x0[2048];

226
drivers/soc/bl616/bl616_std/include/hardware/auadc_reg.h Normal file
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@ -0,0 +1,226 @@
/**
******************************************************************************
* @file auadc_reg.h
* @version V1.0
* @date 2022-12-03
* @brief This file is the description of.IP register
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __AUADC_REG_H__
#define __AUADC_REG_H__
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define AUADC_AUDPDM_TOP_OFFSET (0xC00) /* audpdm_top */
#define AUADC_AUDPDM_ITF_OFFSET (0xC04) /* audpdm_itf */
#define AUADC_PDM_ADC_0_OFFSET (0xC08) /* pdm_adc_0 */
#define AUADC_PDM_ADC_1_OFFSET (0xC0C) /* pdm_adc_1 */
#define AUADC_PDM_DAC_0_OFFSET (0xC10) /* pdm_dac_0 */
#define AUADC_PDM_PDM_0_OFFSET (0xC1C) /* pdm_pdm_0 */
#define AUADC_PDM_RSVD0_OFFSET (0xC20) /* pdm_rsvd0 */
#define AUADC_PDM_DBG_0_OFFSET (0xC24) /* pdm_dbg_0 */
#define AUADC_PDM_DBG_1_OFFSET (0xC28) /* pdm_dbg_1 */
#define AUADC_PDM_DBG_2_OFFSET (0xC2C) /* pdm_dbg_2 */
#define AUADC_PDM_DBG_3_OFFSET (0xC30) /* pdm_dbg_3 */
#define AUADC_PDM_DBG_4_OFFSET (0xC34) /* pdm_dbg_4 */
#define AUADC_PDM_ADC_S0_OFFSET (0xC38) /* pdm_adc_s0 */
#define AUADC_PDM_ADC_S1_OFFSET (0xC3C) /* pdm_adc_s1 */
#define AUADC_PDM_ADC_S2_OFFSET (0xC40) /* pdm_adc_s2 */
#define AUADC_AUDADC_ANA_CFG1_OFFSET (0xC60) /* audadc_ana_cfg1 */
#define AUADC_AUDADC_ANA_CFG2_OFFSET (0xC64) /* audadc_ana_cfg2 */
#define AUADC_AUDADC_CMD_OFFSET (0xC68) /* audadc_cmd */
#define AUADC_AUDADC_DATA_OFFSET (0xC6C) /* audadc_data */
#define AUADC_AUDADC_RX_FIFO_CTRL_OFFSET (0xC80) /* audadc_rx_fifo_ctrl */
#define AUADC_AUDADC_RX_FIFO_STATUS_OFFSET (0xC84) /* audadc_rx_fifo_status */
#define AUADC_AUDADC_RX_FIFO_DATA_OFFSET (0xC88) /* audadc_rx_fifo_data */
/* Register Bitfield definitions *****************************************************/
/* 0xC00 : audpdm_top */
#define AUADC_AUDIO_CKG_EN (1 << 0U)
#define AUADC_ADC_ITF_INV_SEL (1 << 2U)
#define AUADC_PDM_ITF_INV_SEL (1 << 3U)
#define AUADC_ADC_RATE_SHIFT (28U)
#define AUADC_ADC_RATE_MASK (0xf << AUADC_ADC_RATE_SHIFT)
/* 0xC04 : audpdm_itf */
#define AUADC_ADC_0_EN (1 << 0U)
#define AUADC_ADC_ITF_EN (1 << 30U)
/* 0xC08 : pdm_adc_0 */
#define AUADC_ADC_0_FIR_MODE (1 << 0U)
/* 0xC0C : pdm_adc_1 */
#define AUADC_ADC_0_K1_SHIFT (0U)
#define AUADC_ADC_0_K1_MASK (0xf << AUADC_ADC_0_K1_SHIFT)
#define AUADC_ADC_0_K1_EN (1 << 4U)
#define AUADC_ADC_0_K2_SHIFT (5U)
#define AUADC_ADC_0_K2_MASK (0xf << AUADC_ADC_0_K2_SHIFT)
#define AUADC_ADC_0_K2_EN (1 << 9U)
/* 0xC10 : pdm_dac_0 */
#define AUADC_ADC_PDM_H_SHIFT (0U)
#define AUADC_ADC_PDM_H_MASK (0xf << AUADC_ADC_PDM_H_SHIFT)
#define AUADC_ADC_PDM_L_SHIFT (6U)
#define AUADC_ADC_PDM_L_MASK (0xf << AUADC_ADC_PDM_L_SHIFT)
#define AUADC_ADC_0_SRC (1 << 12U)
/* 0xC1C : pdm_pdm_0 */
#define AUADC_PDM_0_EN (1 << 0U)
#define AUADC_ADC_0_PDM_SEL_SHIFT (3U)
#define AUADC_ADC_0_PDM_SEL_MASK (0x7 << AUADC_ADC_0_PDM_SEL_SHIFT)
/* 0xC20 : pdm_rsvd0 */
/* 0xC24 : pdm_dbg_0 */
#define AUADC_ADC_TEST_CLKIN_EN (1 << 21U)
#define AUADC_ADC_TEST_DIN_EN (1 << 23U)
#define AUADC_AUD_TEST_READ_SEL_SHIFT (24U)
#define AUADC_AUD_TEST_READ_SEL_MASK (0x3f << AUADC_AUD_TEST_READ_SEL_SHIFT)
/* 0xC28 : pdm_dbg_1 */
#define AUADC_AUD_TEST_READ_SHIFT (0U)
#define AUADC_AUD_TEST_READ_MASK (0xffffffff << AUADC_AUD_TEST_READ_SHIFT)
/* 0xC2C : pdm_dbg_2 */
#define AUADC_ADC_FIR_4S_VAL_SHIFT (0U)
#define AUADC_ADC_FIR_4S_VAL_MASK (0xfffff << AUADC_ADC_FIR_4S_VAL_SHIFT)
#define AUADC_ADC_0_FIR_4S_EN (1 << 20U)
/* 0xC30 : pdm_dbg_3 */
/* 0xC34 : pdm_dbg_4 */
/* 0xC38 : pdm_adc_s0 */
#define AUADC_ADC_S0_VOLUME_SHIFT (0U)
#define AUADC_ADC_S0_VOLUME_MASK (0x1ff << AUADC_ADC_S0_VOLUME_SHIFT)
/* 0xC3C : pdm_adc_s1 */
/* 0xC40 : pdm_adc_s2 */
/* 0xC60 : audadc_ana_cfg1 */
#define AUADC_AUDADC_PGA_CHOP_CKSEL (1 << 0U)
#define AUADC_AUDADC_PGA_CHOP_FREQ_SHIFT (1U)
#define AUADC_AUDADC_PGA_CHOP_FREQ_MASK (0x7 << AUADC_AUDADC_PGA_CHOP_FREQ_SHIFT)
#define AUADC_AUDADC_PGA_CHOP_EN (1 << 4U)
#define AUADC_AUDADC_PGA_CHOP_CFG_SHIFT (5U)
#define AUADC_AUDADC_PGA_CHOP_CFG_MASK (0x3 << AUADC_AUDADC_PGA_CHOP_CFG_SHIFT)
#define AUADC_AUDADC_PGA_RHPAS_SEL_SHIFT (8U)
#define AUADC_AUDADC_PGA_RHPAS_SEL_MASK (0x3 << AUADC_AUDADC_PGA_RHPAS_SEL_SHIFT)
#define AUADC_AUDADC_PGA_NOIS_CTRL_SHIFT (12U)
#define AUADC_AUDADC_PGA_NOIS_CTRL_MASK (0x3 << AUADC_AUDADC_PGA_NOIS_CTRL_SHIFT)
#define AUADC_AUDADC_ICTRL_PGA_AAF_SHIFT (16U)
#define AUADC_AUDADC_ICTRL_PGA_AAF_MASK (0x3 << AUADC_AUDADC_ICTRL_PGA_AAF_SHIFT)
#define AUADC_AUDADC_ICTRL_PGA_MIC_SHIFT (20U)
#define AUADC_AUDADC_ICTRL_PGA_MIC_MASK (0x3 << AUADC_AUDADC_ICTRL_PGA_MIC_SHIFT)
#define AUADC_AUDADC_PGA_LP_EN (1 << 24U)
#define AUADC_AUDADC_CKB_EN (1 << 28U)
#define AUADC_AUDADC_SEL_EDGE (1 << 29U)
/* 0xC64 : audadc_ana_cfg2 */
#define AUADC_AUDADC_DITHER_ORDER (1 << 0U)
#define AUADC_AUDADC_DITHER_SEL_SHIFT (1U)
#define AUADC_AUDADC_DITHER_SEL_MASK (0x3 << AUADC_AUDADC_DITHER_SEL_SHIFT)
#define AUADC_AUDADC_DITHER_ENA (1 << 3U)
#define AUADC_AUDADC_QUAN_GAIN_SHIFT (4U)
#define AUADC_AUDADC_QUAN_GAIN_MASK (0x3 << AUADC_AUDADC_QUAN_GAIN_SHIFT)
#define AUADC_AUDADC_DEM_EN (1 << 8U)
#define AUADC_AUDADC_NCTRL_ADC2_SHIFT (12U)
#define AUADC_AUDADC_NCTRL_ADC2_MASK (0x3 << AUADC_AUDADC_NCTRL_ADC2_SHIFT)
#define AUADC_AUDADC_NCTRL_ADC1_SHIFT (16U)
#define AUADC_AUDADC_NCTRL_ADC1_MASK (0x7 << AUADC_AUDADC_NCTRL_ADC1_SHIFT)
#define AUADC_AUDADC_ICTRL_ADC_SHIFT (20U)
#define AUADC_AUDADC_ICTRL_ADC_MASK (0x3 << AUADC_AUDADC_ICTRL_ADC_SHIFT)
#define AUADC_AUDADC_SDM_LP_EN (1 << 24U)
#define AUADC_AUDADC_RESERVED_SHIFT (28U)
#define AUADC_AUDADC_RESERVED_MASK (0x3 << AUADC_AUDADC_RESERVED_SHIFT)
/* 0xC68 : audadc_cmd */
#define AUADC_AUDADC_MEAS_ODR_SEL_SHIFT (0U)
#define AUADC_AUDADC_MEAS_ODR_SEL_MASK (0xf << AUADC_AUDADC_MEAS_ODR_SEL_SHIFT)
#define AUADC_AUDADC_MEAS_FILTER_TYPE (1 << 4U)
#define AUADC_AUDADC_MEAS_FILTER_EN (1 << 5U)
#define AUADC_AUDADC_AUDIO_OSR_SEL (1 << 6U)
#define AUADC_AUDADC_PGA_GAIN_SHIFT (8U)
#define AUADC_AUDADC_PGA_GAIN_MASK (0xf << AUADC_AUDADC_PGA_GAIN_SHIFT)
#define AUADC_AUDADC_PGA_MODE_SHIFT (12U)
#define AUADC_AUDADC_PGA_MODE_MASK (0x3 << AUADC_AUDADC_PGA_MODE_SHIFT)
#define AUADC_AUDADC_CHANNEL_SELN_SHIFT (16U)
#define AUADC_AUDADC_CHANNEL_SELN_MASK (0x7 << AUADC_AUDADC_CHANNEL_SELN_SHIFT)
#define AUADC_AUDADC_CHANNEL_SELP_SHIFT (20U)
#define AUADC_AUDADC_CHANNEL_SELP_MASK (0x7 << AUADC_AUDADC_CHANNEL_SELP_SHIFT)
#define AUADC_AUDADC_CHANNEL_EN_SHIFT (24U)
#define AUADC_AUDADC_CHANNEL_EN_MASK (0x3 << AUADC_AUDADC_CHANNEL_EN_SHIFT)
#define AUADC_AUDADC_CONV (1 << 28U)
#define AUADC_AUDADC_SDM_PU (1 << 29U)
#define AUADC_AUDADC_PGA_PU (1 << 30U)
/* 0xC6C : audadc_data */
#define AUADC_AUDADC_RAW_DATA_SHIFT (0U)
#define AUADC_AUDADC_RAW_DATA_MASK (0xffffff << AUADC_AUDADC_RAW_DATA_SHIFT)
#define AUADC_AUDADC_DATA_RDY (1 << 24U)
#define AUADC_AUDADC_SOFT_RST (1 << 29U)
#define AUADC_AUDADC_VALID_4S_VAL (1 << 30U)
#define AUADC_AUDADC_VALID_4S_EN (1 << 31U)
/* 0xC80 : audadc_rx_fifo_ctrl */
#define AUADC_RX_FIFO_FLUSH (1 << 0U)
#define AUADC_RXO_INT_EN (1 << 1U)
#define AUADC_RXU_INT_EN (1 << 2U)
#define AUADC_RXA_INT_EN (1 << 3U)
#define AUADC_RX_DRQ_EN (1 << 4U)
#define AUADC_RX_DATA_RES_SHIFT (5U)
#define AUADC_RX_DATA_RES_MASK (0x3 << AUADC_RX_DATA_RES_SHIFT)
#define AUADC_RX_CH_EN (1 << 8U)
#define AUADC_RX_DRQ_CNT_SHIFT (14U)
#define AUADC_RX_DRQ_CNT_MASK (0x3 << AUADC_RX_DRQ_CNT_SHIFT)
#define AUADC_RX_TRG_LEVEL_SHIFT (16U)
#define AUADC_RX_TRG_LEVEL_MASK (0xf << AUADC_RX_TRG_LEVEL_SHIFT)
#define AUADC_RX_DATA_MODE_SHIFT (24U)
#define AUADC_RX_DATA_MODE_MASK (0x3 << AUADC_RX_DATA_MODE_SHIFT)
/* 0xC84 : audadc_rx_fifo_status */
#define AUADC_RXO_INT (1 << 1U)
#define AUADC_RXU_INT (1 << 2U)
#define AUADC_RXA_INT (1 << 4U)
#define AUADC_RXA_CNT_SHIFT (16U)
#define AUADC_RXA_CNT_MASK (0xf << AUADC_RXA_CNT_SHIFT)
#define AUADC_RXA (1 << 24U)
/* 0xC88 : audadc_rx_fifo_data */
#define AUADC_RX_DATA_SHIFT (0U)
#define AUADC_RX_DATA_MASK (0xffffffff << AUADC_RX_DATA_SHIFT)
#endif /* __AUADC_REG_H__ */

167
drivers/soc/bl616/bl616_std/include/hardware/audac_reg.h Normal file
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@ -0,0 +1,167 @@
/**
******************************************************************************
* @file audac_reg.h
* @version V1.0
* @date 2022-12-03
* @brief This file is the description of.IP register
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __AUDAC_REG_H__
#define __AUDAC_REG_H__
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define AUDAC_0_OFFSET (0x000) /* audac_0 */
#define AUDAC_STATUS_OFFSET (0x4) /* audac_status */
#define AUDAC_S0_OFFSET (0x8) /* audac_s0 */
#define AUDAC_S0_MISC_OFFSET (0xC) /* audac_s0_misc */
#define AUDAC_ZD_0_OFFSET (0x10) /* audac_zd_0 */
#define AUDAC_1_OFFSET (0x14) /* audac_1 */
#define AUDAC_RSVD_OFFSET (0x18) /* audac_rsvd */
#define AUDAC_TEST_0_OFFSET (0x1C) /* audac_test_0 */
#define AUDAC_TEST_1_OFFSET (0x20) /* audac_test_1 */
#define AUDAC_TEST_2_OFFSET (0x24) /* audac_test_2 */
#define AUDAC_TEST_3_OFFSET (0x28) /* audac_test_3 */
#define AUDAC_FIFO_CTRL_OFFSET (0x8C) /* audac_fifo_ctrl */
#define AUDAC_FIFO_STATUS_OFFSET (0x90) /* audac_fifo_status */
#define AUDAC_FIFO_DATA_OFFSET (0x94) /* audac_fifo_data */
/* Register Bitfield definitions *****************************************************/
/* 0x000 : audac_0 */
#define AUDAC_DAC_0_EN (1 << 0U)
#define AUDAC_DAC_ITF_EN (1 << 1U)
#define AUDAC_CKG_ENA (1 << 27U)
#define AUDAC_AU_PWM_MODE_SHIFT (28U)
#define AUDAC_AU_PWM_MODE_MASK (0xf << AUDAC_AU_PWM_MODE_SHIFT)
/* 0x4 : audac_status */
#define AUDAC_DAC_H0_BUSY (1 << 12U)
#define AUDAC_DAC_H0_MUTE_DONE (1 << 13U)
#define AUDAC_DAC_S0_INT (1 << 16U)
#define AUDAC_DAC_S0_INT_CLR (1 << 17U)
#define AUDAC_ZD_AMUTE (1 << 23U)
#define AUDAC_AUDIO_INT_ALL (1 << 24U)
/* 0x8 : audac_s0 */
#define AUDAC_DAC_S0_CTRL_RMP_RATE_SHIFT (2U)
#define AUDAC_DAC_S0_CTRL_RMP_RATE_MASK (0xf << AUDAC_DAC_S0_CTRL_RMP_RATE_SHIFT)
#define AUDAC_DAC_S0_CTRL_ZCD_RATE_SHIFT (6U)
#define AUDAC_DAC_S0_CTRL_ZCD_RATE_MASK (0xf << AUDAC_DAC_S0_CTRL_ZCD_RATE_SHIFT)
#define AUDAC_DAC_S0_CTRL_MODE_SHIFT (10U)
#define AUDAC_DAC_S0_CTRL_MODE_MASK (0x3 << AUDAC_DAC_S0_CTRL_MODE_SHIFT)
#define AUDAC_DAC_S0_VOLUME_UPDATE (1 << 12U)
#define AUDAC_DAC_S0_VOLUME_SHIFT (13U)
#define AUDAC_DAC_S0_VOLUME_MASK (0x1ff << AUDAC_DAC_S0_VOLUME_SHIFT)
#define AUDAC_DAC_S0_MUTE_RMPUP_RATE_SHIFT (22U)
#define AUDAC_DAC_S0_MUTE_RMPUP_RATE_MASK (0xf << AUDAC_DAC_S0_MUTE_RMPUP_RATE_SHIFT)
#define AUDAC_DAC_S0_MUTE_RMPDN_RATE_SHIFT (26U)
#define AUDAC_DAC_S0_MUTE_RMPDN_RATE_MASK (0xf << AUDAC_DAC_S0_MUTE_RMPDN_RATE_SHIFT)
#define AUDAC_DAC_S0_MUTE_SOFTMODE (1 << 30U)
#define AUDAC_DAC_S0_MUTE (1 << 31U)
/* 0xC : audac_s0_misc */
#define AUDAC_DAC_S0_CTRL_ZCD_TIMEOUT_SHIFT (28U)
#define AUDAC_DAC_S0_CTRL_ZCD_TIMEOUT_MASK (0xf << AUDAC_DAC_S0_CTRL_ZCD_TIMEOUT_SHIFT)
/* 0x10 : audac_zd_0 */
#define AUDAC_ZD_TIME_SHIFT (0U)
#define AUDAC_ZD_TIME_MASK (0x7fff << AUDAC_ZD_TIME_SHIFT)
#define AUDAC_ZD_EN (1 << 16U)
/* 0x14 : audac_1 */
#define AUDAC_DAC_MIX_SEL_SHIFT (0U)
#define AUDAC_DAC_MIX_SEL_MASK (0x3 << AUDAC_DAC_MIX_SEL_SHIFT)
#define AUDAC_DAC_DSM_OUT_FMT (1 << 4U)
#define AUDAC_DAC_DSM_ORDER_SHIFT (5U)
#define AUDAC_DAC_DSM_ORDER_MASK (0x3 << AUDAC_DAC_DSM_ORDER_SHIFT)
#define AUDAC_DAC_DSM_SCALING_MODE_SHIFT (7U)
#define AUDAC_DAC_DSM_SCALING_MODE_MASK (0x3 << AUDAC_DAC_DSM_SCALING_MODE_SHIFT)
#define AUDAC_DAC_DSM_SCALING_EN (1 << 10U)
#define AUDAC_DAC_DSM_DITHER_AMP_SHIFT (11U)
#define AUDAC_DAC_DSM_DITHER_AMP_MASK (0x7 << AUDAC_DAC_DSM_DITHER_AMP_SHIFT)
#define AUDAC_DAC_DSM_DITHER_EN (1 << 14U)
#define AUDAC_DAC_DSM_DITHER_PRBS_MODE_SHIFT (15U)
#define AUDAC_DAC_DSM_DITHER_PRBS_MODE_MASK (0x3 << AUDAC_DAC_DSM_DITHER_PRBS_MODE_SHIFT)
/* 0x18 : audac_rsvd */
#define AUDAC_AU_PWM_RESERVED_SHIFT (0U)
#define AUDAC_AU_PWM_RESERVED_MASK (0xffffffff << AUDAC_AU_PWM_RESERVED_SHIFT)
/* 0x1C : audac_test_0 */
#define AUDAC_DAC_IN_0_SHIFT (0U)
#define AUDAC_DAC_IN_0_MASK (0xffff << AUDAC_DAC_IN_0_SHIFT)
#define AUDAC_DAC_DPGA_0_SHIFT (16U)
#define AUDAC_DAC_DPGA_0_MASK (0xffff << AUDAC_DAC_DPGA_0_SHIFT)
/* 0x20 : audac_test_1 */
#define AUDAC_DAC_FIR_0_SHIFT (0U)
#define AUDAC_DAC_FIR_0_MASK (0x1ffff << AUDAC_DAC_FIR_0_SHIFT)
/* 0x24 : audac_test_2 */
#define AUDAC_DAC_SINC_0_SHIFT (0U)
#define AUDAC_DAC_SINC_0_MASK (0xffff << AUDAC_DAC_SINC_0_SHIFT)
/* 0x28 : audac_test_3 */
#define AUDAC_AU_PWM_TEST_READ_SHIFT (0U)
#define AUDAC_AU_PWM_TEST_READ_MASK (0xffffffff << AUDAC_AU_PWM_TEST_READ_SHIFT)
/* 0x8C : audac_fifo_ctrl */
#define AUDAC_TX_FIFO_FLUSH (1 << 0U)
#define AUDAC_TXO_INT_EN (1 << 1U)
#define AUDAC_TXU_INT_EN (1 << 2U)
#define AUDAC_TXA_INT_EN (1 << 3U)
#define AUDAC_TX_DRQ_EN (1 << 4U)
#define AUDAC_TX_CH_EN_SHIFT (8U)
#define AUDAC_TX_CH_EN_MASK (0x3 << AUDAC_TX_CH_EN_SHIFT)
#define AUDAC_TX_DRQ_CNT_SHIFT (14U)
#define AUDAC_TX_DRQ_CNT_MASK (0x3 << AUDAC_TX_DRQ_CNT_SHIFT)
#define AUDAC_TX_TRG_LEVEL_SHIFT (16U)
#define AUDAC_TX_TRG_LEVEL_MASK (0x1f << AUDAC_TX_TRG_LEVEL_SHIFT)
#define AUDAC_TX_DATA_MODE_SHIFT (24U)
#define AUDAC_TX_DATA_MODE_MASK (0x3 << AUDAC_TX_DATA_MODE_SHIFT)
/* 0x90 : audac_fifo_status */
#define AUDAC_TXO_INT (1 << 1U)
#define AUDAC_TXU_INT (1 << 2U)
#define AUDAC_TXA_INT (1 << 4U)
#define AUDAC_TXA_CNT_SHIFT (16U)
#define AUDAC_TXA_CNT_MASK (0x1f << AUDAC_TXA_CNT_SHIFT)
#define AUDAC_TXA (1 << 24U)
/* 0x94 : audac_fifo_data */
#define AUDAC_TX_DATA_SHIFT (0U)
#define AUDAC_TX_DATA_MASK (0xffffffff << AUDAC_TX_DATA_SHIFT)
#endif /* __AUDAC_REG_H__ */

2
drivers/soc/bl616/bl616_std/include/hardware/bl616.h
View file

@ -227,7 +227,7 @@ typedef enum {
#define AON_BASE ((uint32_t)0x2000f000)
#define MM_MISC_BASE ((uint32_t)0x20050000)
#define PSRAM_CTRL_BASE ((uint32_t)0x20052000)
#define AUPWM_BASE ((uint32_t)0x20055000)
#define AUDAC_BASE ((uint32_t)0x20055000)
#define EFUSE_BASE ((uint32_t)0x20056000)
#define EF_DATA_BASE ((uint32_t)0x20056000)
#define EF_CTRL_BASE ((uint32_t)0x20056000)

357
drivers/soc/bl616/bl616_std/src/bl616_audac.c Normal file
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@ -0,0 +1,357 @@
#include "bl616.h"
#include "bl616_audac.h"
#include "hardware/audac_reg.h"
#include "hardware/dac_reg.h"
static volatile uint32_t g_audac_channel_mode = 0;
int bflb_audac_init(struct bflb_device_s *dev, const struct bflb_audac_init_config_s *config)
{
uint32_t reg_base;
uint32_t regval;
reg_base = dev->reg_base;
/* enable clk, enable dma interface, disable ch0 */
regval = getreg32(reg_base + AUDAC_0_OFFSET);
regval |= AUDAC_CKG_ENA;
regval |= AUDAC_DAC_ITF_EN;
regval |= AUDAC_DAC_0_EN;
/* set output mode and sampling rate */
regval &= ~AUDAC_AU_PWM_MODE_MASK;
if (config->output_mode != AUDAC_OUTPUT_MODE_PWM) {
regval |= (config->sampling_rate + 8) << AUDAC_AU_PWM_MODE_SHIFT;
} else {
regval |= config->sampling_rate << AUDAC_AU_PWM_MODE_SHIFT;
}
putreg32(regval, reg_base + AUDAC_0_OFFSET);
regval = getreg32(reg_base + AUDAC_1_OFFSET);
/* set dsm dither, scaling, and order */
regval &= ~AUDAC_DAC_DSM_SCALING_MODE_MASK;
regval |= 3 << AUDAC_DAC_DSM_SCALING_MODE_SHIFT;
regval &= ~AUDAC_DAC_DSM_ORDER_MASK;
regval |= 1 << AUDAC_DAC_DSM_ORDER_SHIFT;
/* set mixer */
regval &= ~AUDAC_DAC_MIX_SEL_MASK;
if (config->source_channels_num == AUDAC_SOURCE_CHANNEL_DUAL) {
regval |= config->mixer_mode << AUDAC_DAC_MIX_SEL_SHIFT;
}
putreg32(regval, reg_base + AUDAC_1_OFFSET);
regval = getreg32(reg_base + AUDAC_FIFO_CTRL_OFFSET);
/* data format */
regval &= ~AUDAC_TX_DATA_MODE_MASK;
regval |= config->data_format;
/* fifo threshold */
regval &= ~AUDAC_TX_TRG_LEVEL_MASK;
regval |= (config->fifo_threshold << AUDAC_TX_TRG_LEVEL_SHIFT) & AUDAC_TX_TRG_LEVEL_MASK;
regval &= ~AUDAC_TX_DRQ_CNT_MASK;
/* dma disable */
regval &= ~AUDAC_TX_DRQ_EN;
/* source channels num */
regval &= ~AUDAC_TX_CH_EN_MASK;
g_audac_channel_mode = config->source_channels_num;
/* disable fifo int */
regval &= ~AUDAC_TXO_INT_EN;
regval &= ~AUDAC_TXU_INT_EN;
regval &= ~AUDAC_TXA_INT_EN;
/* clear fifo */
regval &= ~AUDAC_TX_FIFO_FLUSH;
putreg32(regval, reg_base + AUDAC_FIFO_CTRL_OFFSET);
/* enable zero delete */
regval = getreg32(reg_base + AUDAC_ZD_0_OFFSET);
regval |= AUDAC_ZD_EN;
regval &= ~AUDAC_ZD_TIME_MASK;
regval |= 512 << AUDAC_ZD_TIME_SHIFT;
putreg32(regval, reg_base + AUDAC_ZD_0_OFFSET);
/* disable volume interrupt */
regval = getreg32(reg_base + AUDAC_STATUS_OFFSET);
regval |= AUDAC_DAC_S0_INT_CLR;
putreg32(regval, reg_base + AUDAC_STATUS_OFFSET);
/* gpdac config */
reg_base = GLB_BASE;
if (config->output_mode != AUDAC_OUTPUT_MODE_PWM) {
/* Select Internal reference */
regval = getreg32(reg_base + GLB_GPDAC_CTRL_OFFSET);
regval |= (GLB_GPDACA_RSTN_ANA | GLB_GPDACB_RSTN_ANA);
regval = getreg32(reg_base + GLB_GPDAC_CTRL_OFFSET);
regval &= ~GLB_GPDAC_REF_SEL;
/* Select the clock and data from aupdac */
regval |= GLB_GPDAC_ANA_CLK_SEL;
if (config->output_mode & AUDAC_OUTPUT_MODE_GPDAC_CH_A) {
regval |= GLB_GPDAC_DAT_CHA_SEL;
}
if (config->output_mode & AUDAC_OUTPUT_MODE_GPDAC_CH_B) {
regval |= GLB_GPDAC_DAT_CHB_SEL;
}
putreg32(regval, reg_base + GLB_GPDAC_CTRL_OFFSET);
if (config->output_mode & AUDAC_OUTPUT_MODE_GPDAC_CH_A) {
/* gpdac enable ch-A */
regval = getreg32(reg_base + GLB_GPDAC_ACTRL_OFFSET);
regval |= (GLB_GPDAC_A_EN | GLB_GPDAC_IOA_EN);
putreg32(regval, reg_base + GLB_GPDAC_ACTRL_OFFSET);
}
if (config->output_mode & AUDAC_OUTPUT_MODE_GPDAC_CH_B) {
/* gpdac enable ch-A */
regval = getreg32(reg_base + GLB_GPDAC_BCTRL_OFFSET);
regval |= (GLB_GPDAC_B_EN | GLB_GPDAC_IOB_EN);
putreg32(regval, reg_base + GLB_GPDAC_BCTRL_OFFSET);
}
}
return 0;
}
int bflb_audac_volume_init(struct bflb_device_s *dev, const struct bflb_audac_volume_config_s *vol_cfg)
{
uint32_t reg_base;
uint32_t regval;
reg_base = dev->reg_base;
/* enable volume update */
regval = getreg32(reg_base + AUDAC_S0_OFFSET);
regval |= AUDAC_DAC_S0_VOLUME_UPDATE;
if (vol_cfg->mute_ramp_en) {
/* mute ramp mode */
regval |= AUDAC_DAC_S0_MUTE_SOFTMODE;
regval &= ~AUDAC_DAC_S0_MUTE_RMPDN_RATE_MASK;
regval |= vol_cfg->mute_down_ramp_rate << AUDAC_DAC_S0_MUTE_RMPDN_RATE_SHIFT;
regval &= ~AUDAC_DAC_S0_MUTE_RMPUP_RATE_MASK;
regval |= vol_cfg->mute_up_ramp_rate << AUDAC_DAC_S0_MUTE_RMPUP_RATE_SHIFT;
} else {
/* mute directly mode */
regval &= ~AUDAC_DAC_S0_MUTE_SOFTMODE;
}
regval &= ~AUDAC_DAC_S0_CTRL_MODE_MASK;
if (vol_cfg->volume_update_mode == AUDAC_VOLUME_UPDATE_MODE_RAMP) {
/* ramp mode */
regval |= 2 << AUDAC_DAC_S0_CTRL_MODE_SHIFT;
regval &= ~AUDAC_DAC_S0_CTRL_RMP_RATE_MASK;
regval |= vol_cfg->volume_ramp_rate << AUDAC_DAC_S0_CTRL_RMP_RATE_SHIFT;
} else if (vol_cfg->volume_update_mode == AUDAC_VOLUME_UPDATE_MODE_RAMP_ZERO_CROSSING) {
/* ramp and zero crossing mode */
regval |= 1 << AUDAC_DAC_S0_CTRL_MODE_SHIFT;
regval &= ~AUDAC_DAC_S0_CTRL_ZCD_RATE_MASK;
regval |= vol_cfg->volume_ramp_rate << AUDAC_DAC_S0_CTRL_ZCD_RATE_SHIFT;
}
putreg32(regval, reg_base + AUDAC_S0_OFFSET);
return 0;
}
int bflb_audac_link_rxdma(struct bflb_device_s *dev, bool enable)
{
uint32_t reg_base;
uint32_t regval;
reg_base = dev->reg_base;
regval = getreg32(reg_base + AUDAC_FIFO_CTRL_OFFSET);
if (enable) {
regval |= AUDAC_TX_DRQ_EN;
} else {
regval &= ~AUDAC_TX_DRQ_EN;
}
putreg32(regval, reg_base + AUDAC_FIFO_CTRL_OFFSET);
return 0;
}
int bflb_audac_int_mask(struct bflb_device_s *dev, uint32_t int_sts)
{
uint32_t reg_base;
uint32_t regval;
reg_base = dev->reg_base;
if (int_sts & AUDAC_INTSTS_VOLUME_RAMP) {
/* volume ramp done int */
regval = getreg32(reg_base + AUDAC_0_OFFSET);
regval &= ~(0x01 << 17);
putreg32(regval, reg_base + AUDAC_0_OFFSET);
int_sts &= ~AUDAC_INTSTS_VOLUME_RAMP;
}
if (int_sts) {
/* fifo int */
regval = getreg32(reg_base + AUDAC_FIFO_CTRL_OFFSET);
regval &= ~int_sts;
putreg32(regval, reg_base + AUDAC_FIFO_CTRL_OFFSET);
}
return 0;
}
int bflb_audac_int_unmask(struct bflb_device_s *dev, uint32_t int_sts)
{
uint32_t reg_base;
uint32_t regval;
reg_base = dev->reg_base;
if (int_sts & AUDAC_INTSTS_VOLUME_RAMP) {
/* volume ramp done int */
regval = getreg32(reg_base + AUDAC_0_OFFSET);
regval |= (0x01 << 17);
putreg32(regval, reg_base + AUDAC_0_OFFSET);
int_sts &= ~AUDAC_INTSTS_VOLUME_RAMP;
}
if (int_sts) {
/* fifo int */
regval = getreg32(reg_base + AUDAC_FIFO_CTRL_OFFSET);
regval |= int_sts;
putreg32(regval, reg_base + AUDAC_FIFO_CTRL_OFFSET);
}
return 0;
}
int bflb_audac_get_intstatus(struct bflb_device_s *dev)
{
uint32_t reg_base;
uint32_t regval;
int32_t int_sts;
reg_base = dev->reg_base;
int_sts = 0;
/* volume ramp done int */
regval = getreg32(reg_base + AUDAC_0_OFFSET);
if (regval & (0x01 << 17)) {
int_sts |= AUDAC_INTSTS_VOLUME_RAMP;
}
/* fifo int */
regval = getreg32(reg_base + AUDAC_FIFO_STATUS_OFFSET);
if (regval | AUDAC_TXO_INT) {
int_sts |= AUDAC_INTSTS_FIFO_OVER;
}
if (regval | AUDAC_TXU_INT) {
int_sts |= AUDAC_INTSTS_FIFO_UNDER;
}
if (regval | AUDAC_TXA_INT) {
int_sts |= AUDAC_INTSTS_FIFO_AVAILABLE;
}
return int_sts;
}
int bflb_audac_int_clear(struct bflb_device_s *dev, uint32_t int_clear)
{
uint32_t reg_base;
uint32_t regval;
uint8_t ramp_int_en;
reg_base = dev->reg_base;
if (int_clear & AUDAC_INTSTS_VOLUME_RAMP) {
/* volume ramp done int */
regval = getreg32(reg_base + AUDAC_0_OFFSET);
if (regval & (0x01 << 17)) {
ramp_int_en = 0;
} else {
ramp_int_en = 1;
}
regval |= (0x01 << 17);
putreg32(regval, reg_base + AUDAC_0_OFFSET);
if (ramp_int_en) {
regval &= ~(0x01 << 17);
}
putreg32(regval, reg_base + AUDAC_0_OFFSET);
}
return 0;
}
int bflb_audac_feature_control(struct bflb_device_s *dev, int cmd, size_t arg)
{
int ret = 0;
uint32_t reg_base;
uint32_t regval;
int16_t volume_val;
reg_base = dev->reg_base;
switch (cmd) {
case AUDAC_CMD_PLAY_START:
/* play start */
regval = getreg32(reg_base + AUDAC_FIFO_CTRL_OFFSET);
regval &= ~AUDAC_TX_CH_EN_MASK;
regval |= g_audac_channel_mode << AUDAC_TX_CH_EN_SHIFT;
putreg32(regval, reg_base + AUDAC_FIFO_CTRL_OFFSET);
g_audac_channel_mode = 0;
break;
case AUDAC_CMD_PLAY_STOP:
/* play stop */
regval = getreg32(reg_base + AUDAC_FIFO_CTRL_OFFSET);
if (g_audac_channel_mode == 0) {
g_audac_channel_mode = (regval & AUDAC_TX_CH_EN_MASK) >> AUDAC_TX_CH_EN_SHIFT;
}
regval &= ~AUDAC_TX_CH_EN_MASK;
putreg32(regval, reg_base + AUDAC_FIFO_CTRL_OFFSET);
break;
case AUDAC_CMD_SET_MUTE:
/* set mute, arg use true or false */
regval = getreg32(reg_base + AUDAC_S0_OFFSET);
if (arg) {
regval |= AUDAC_DAC_S0_MUTE;
} else {
regval &= ~AUDAC_DAC_S0_MUTE;
}
putreg32(regval, reg_base + AUDAC_S0_OFFSET);
break;
case AUDAC_CMD_SET_VOLUME_VAL:
/* set volume value dB, arg range -191 to + 36, 0.5dB step, range -95.5dB to +18dB*/
volume_val = (uint16_t)((int16_t)arg * 2);
regval = getreg32(reg_base + AUDAC_S0_OFFSET);
regval &= ~AUDAC_DAC_S0_VOLUME_MASK;
regval |= (volume_val << AUDAC_DAC_S0_VOLUME_SHIFT) & AUDAC_DAC_S0_VOLUME_MASK;
putreg32(regval, reg_base + AUDAC_S0_OFFSET);
break;
case AUDAC_CMD_CLEAR_TX_FIFO:
/* get tx fifo cnt */
regval = getreg32(reg_base + AUDAC_FIFO_CTRL_OFFSET);
regval |= AUDAC_TX_FIFO_FLUSH;
putreg32(regval, reg_base + AUDAC_FIFO_CTRL_OFFSET);
break;
case AUDAC_CMD_GET_TX_FIFO_CNT:
/* get tx fifo cnt */
regval = getreg32(reg_base + AUDAC_FIFO_STATUS_OFFSET);
ret = (regval & AUDAC_TXA_CNT_MASK) >> AUDAC_TXA_CNT_SHIFT;
break;
default:
break;
}
return ret;
}

266
drivers/soc/bl616/bl616_std/src/bl616_ef_cfg.c
View file

@ -33,35 +33,12 @@
*
******************************************************************************
*/
#include "string.h"
#include "bflb_ef_ctrl.h"
#include "bl616_ef_cfg.h"
#include "hardware/ef_data_reg.h"
/** @addtogroup BL616_Peripheral_Driver
* @{
*/
extern int bflb_efuse_read_mac_address_opt(uint8_t slot, uint8_t mac[6], uint8_t reload);
/** @addtogroup SEC_EF_CTRL
* @{
*/
/** @defgroup SEC_EF_CTRL_Private_Macros
* @{
*/
/*@} end of group SEC_EF_CTRL_Private_Macros */
/** @defgroup SEC_EF_CTRL_Private_Types
* @{
*/
/*@} end of group SEC_EF_CTRL_Private_Types */
/** @defgroup SEC_EF_CTRL_Private_Variables
* @{
*/
static const bflb_ef_ctrl_com_trim_cfg trim_list[] = {
static const bflb_ef_ctrl_com_trim_cfg_t trim_list[] = {
{
.name = "ldo15",
.en_addr = 0x68 * 8 + 31,
@ -302,77 +279,19 @@ static const bflb_ef_ctrl_com_trim_cfg trim_list[] = {
}
};
#define EF_CTRL_DEVICE_INFO_OFFSET 0x18
/* 0x14 : ef_wifi_mac_low */
#define EF_DATA_EF_WIFI_MAC_LOW_OFFSET (0x14)
/* 0x18 : ef_wifi_mac_high */
#define EF_DATA_EF_WIFI_MAC_HIGH_OFFSET (0x18)
/* 0x1C : ef_key_slot_0_w0 */
#define EF_DATA_EF_KEY_SLOT_0_W0_OFFSET (0x1C)
/* 0x20 : ef_key_slot_0_w1 */
#define EF_DATA_EF_KEY_SLOT_0_W1_OFFSET (0x20)
/* 0x24 : ef_key_slot_0_w2 */
#define EF_DATA_EF_KEY_SLOT_0_W2_OFFSET (0x24)
/* 0x28 : ef_key_slot_0_w3 */
#define EF_DATA_EF_KEY_SLOT_0_W3_OFFSET (0x28)
/* 0x2C : ef_key_slot_1_w0 */
#define EF_DATA_EF_KEY_SLOT_1_W0_OFFSET (0x2C)
/* 0x30 : ef_key_slot_1_w1 */
#define EF_DATA_EF_KEY_SLOT_1_W1_OFFSET (0x30)
/* 0x34 : ef_key_slot_1_w2 */
#define EF_DATA_EF_KEY_SLOT_1_W2_OFFSET (0x34)
/* 0x38 : ef_key_slot_1_w3 */
#define EF_DATA_EF_KEY_SLOT_1_W3_OFFSET (0x38)
/* 0x3C : ef_key_slot_2_w0 */
#define EF_DATA_EF_KEY_SLOT_2_W0_OFFSET (0x3C)
/* 0x40 : ef_key_slot_2_w1 */
#define EF_DATA_EF_KEY_SLOT_2_W1_OFFSET (0x40)
/* 0x44 : ef_key_slot_2_w2 */
#define EF_DATA_EF_KEY_SLOT_2_W2_OFFSET (0x44)
/* 0x48 : ef_key_slot_2_w3 */
#define EF_DATA_EF_KEY_SLOT_2_W3_OFFSET (0x48)
/* 0x4C : ef_key_slot_3_w0 */
#define EF_DATA_EF_KEY_SLOT_3_W0_OFFSET (0x4C)
/* 0x50 : ef_key_slot_3_w1 */
#define EF_DATA_EF_KEY_SLOT_3_W1_OFFSET (0x50)
/* 0x54 : ef_key_slot_3_w2 */
#define EF_DATA_EF_KEY_SLOT_3_W2_OFFSET (0x54)
/* 0x58 : ef_key_slot_3_w3 */
#define EF_DATA_EF_KEY_SLOT_3_W3_OFFSET (0x58)
/* 0x5C : ef_sw_usage_0 */
#define EF_DATA_EF_SW_USAGE_0_OFFSET (0x5C)
/* 0x60 : ef_sw_usage_1 */
#define EF_DATA_EF_SW_USAGE_1_OFFSET (0x60)
/* 0x64 : ef_sw_usage_2 */
#define EF_DATA_EF_SW_USAGE_2_OFFSET (0x64)
/* 0x68 : ef_sw_usage_3 */
#define EF_DATA_EF_SW_USAGE_3_OFFSET (0x68)
/* 0x6C : ef_key_slot_11_w0 */
#define EF_DATA_EF_KEY_SLOT_11_W0_OFFSET (0x6C)
/* 0x70 : ef_key_slot_11_w1 */
#define EF_DATA_EF_KEY_SLOT_11_W1_OFFSET (0x70)
/* 0x74 : ef_key_slot_11_w2 */
#define EF_DATA_EF_KEY_SLOT_11_W2_OFFSET (0x74)
/* 0x78 : ef_key_slot_11_w3 */
#define EF_DATA_EF_KEY_SLOT_11_W3_OFFSET (0x78)
/*@} end of group SEC_EF_CTRL_Private_Variables */
/** @defgroup SEC_EF_CTRL_Global_Variables
* @{
*/
/*@} end of group SEC_EF_CTRL_Global_Variables */
/** @defgroup SEC_EF_CTRL_Private_Fun_Declaration
* @{
*/
/*@} end of group SEC_EF_CTRL_Private_Fun_Declaration */
/** @defgroup SEC_EF_CTRL_Private_Functions
* @{
*/
/****************************************************************************/ /**
* @brief Efuse get trim list
*
* @param trim_list: Trim list pointer
*
* @return Trim list count
*
*******************************************************************************/
uint32_t bflb_ef_ctrl_get_common_trim_list(const bflb_ef_ctrl_com_trim_cfg_t **ptrim_list)
{
*ptrim_list = &trim_list[0];
return sizeof(trim_list) / sizeof(trim_list[0]);
}
/****************************************************************************/ /**
* @brief Efuse read device info
@ -386,21 +305,14 @@ void bflb_ef_ctrl_get_device_info(bflb_efuse_device_info_type *deviceInfo)
{
uint32_t *p = (uint32_t *)deviceInfo;
bflb_ef_ctrl_read_direct(NULL, EF_CTRL_DEVICE_INFO_OFFSET, p, 1, 1);
bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_WIFI_MAC_HIGH_OFFSET, p, 1, 1);
}
/****************************************************************************/ /**
* @brief Efuse get trim list
*
* @param trim_list: Trim list pointer
*
* @return Trim list count
*
*******************************************************************************/
uint32_t bflb_ef_ctrl_get_common_trim_list(const bflb_ef_ctrl_com_trim_cfg **ptrim_list)
void bflb_efuse_get_chipid(uint8_t chipid[8])
{
*ptrim_list = &trim_list[0];
return sizeof(trim_list) / sizeof(trim_list[0]);
bflb_efuse_read_mac_address_opt(0, chipid, 1);
chipid[6] = 0;
chipid[7] = 0;
}
/****************************************************************************/ /**
@ -412,7 +324,7 @@ uint32_t bflb_ef_ctrl_get_common_trim_list(const bflb_ef_ctrl_com_trim_cfg **ptr
* @return 0 for all slots full,1 for others
*
*******************************************************************************/
uint8_t EF_Ctrl_Is_MAC_Address_Slot_Empty(uint8_t slot, uint8_t reload)
uint8_t bflb_efuse_is_mac_address_slot_empty(uint8_t slot, uint8_t reload)
{
uint32_t tmp1 = 0xffffffff, tmp2 = 0xffffffff;
uint32_t part1Empty = 0, part2Empty = 0;
@ -441,10 +353,10 @@ uint8_t EF_Ctrl_Is_MAC_Address_Slot_Empty(uint8_t slot, uint8_t reload)
* @param mac[6]: MAC address buffer
* @param program: Whether program
*
* @return SUCCESS or ERROR
* @return 0 or -1
*
*******************************************************************************/
BL_Err_Type EF_Ctrl_Write_MAC_Address_Opt(uint8_t slot, uint8_t mac[6], uint8_t program)
int bflb_efuse_write_mac_address_opt(uint8_t slot, uint8_t mac[6], uint8_t program)
{
uint8_t *maclow = (uint8_t *)mac;
uint8_t *machigh = (uint8_t *)(mac + 4);
@ -452,7 +364,7 @@ BL_Err_Type EF_Ctrl_Write_MAC_Address_Opt(uint8_t slot, uint8_t mac[6], uint8_t
uint32_t i = 0, cnt;
if (slot >= 3) {
return ERROR;
return -1;
}
/* Change to local order */
@ -491,7 +403,7 @@ BL_Err_Type EF_Ctrl_Write_MAC_Address_Opt(uint8_t slot, uint8_t mac[6], uint8_t
bflb_ef_ctrl_write_direct(NULL, EF_DATA_EF_KEY_SLOT_11_W2_OFFSET, &tmpval, 1, program);
}
return SUCCESS;
return 0;
}
/****************************************************************************/ /**
@ -501,10 +413,10 @@ BL_Err_Type EF_Ctrl_Write_MAC_Address_Opt(uint8_t slot, uint8_t mac[6], uint8_t
* @param mac[6]: MAC address buffer
* @param reload: Whether reload
*
* @return SUCCESS or ERROR
* @return 0 or -1
*
*******************************************************************************/
BL_Err_Type EF_Ctrl_Read_MAC_Address_Opt(uint8_t slot, uint8_t mac[6], uint8_t reload)
int bflb_efuse_read_mac_address_opt(uint8_t slot, uint8_t mac[6], uint8_t reload)
{
uint8_t *maclow = (uint8_t *)mac;
uint8_t *machigh = (uint8_t *)(mac + 4);
@ -513,7 +425,7 @@ BL_Err_Type EF_Ctrl_Read_MAC_Address_Opt(uint8_t slot, uint8_t mac[6], uint8_t r
uint32_t cnt = 0;
if (slot >= 3) {
return ERROR;
return -1;
}
if (slot == 0) {
@ -549,14 +461,124 @@ BL_Err_Type EF_Ctrl_Read_MAC_Address_Opt(uint8_t slot, uint8_t mac[6], uint8_t r
mac[i] = mac[5 - i];
mac[5 - i] = tmpval;
}
return SUCCESS;
return 0;
} else {
return ERROR;
return -1;
}
}
/*@} end of group SEC_EF_CTRL_Public_Functions */
float bflb_efuse_get_adc_trim(void)
{
bflb_ef_ctrl_com_trim_t trim;
uint32_t tmp;
/*@} end of group SEC_EF_CTRL */
float coe = 1.0;
/*@} end of group BL616_Peripheral_Driver */
bflb_ef_ctrl_read_common_trim(NULL, "gpadc_gain", &trim, 1);
if (trim.en) {
if (trim.parity == bflb_ef_ctrl_get_trim_parity(trim.value, trim.len)) {
tmp = trim.value;
if (tmp & 0x800) {
tmp = ~tmp;
tmp += 1;
tmp = tmp & 0xfff;
coe = (1.0 + ((float)tmp / 2048.0));
} else {
coe = (1.0 - ((float)tmp / 2048.0));
}
}
}
return coe;
}
uint32_t bflb_efuse_get_adc_tsen_trim(void)
{
bflb_ef_ctrl_com_trim_t trim;
bflb_ef_ctrl_read_common_trim(NULL, "tsen", &trim, 1);
if (trim.en) {
if (trim.parity == bflb_ef_ctrl_get_trim_parity(trim.value, trim.len)) {
return trim.value;
}
}
return 2042;
}
void bflb_efuse_read_secure_boot(uint8_t *sign, uint8_t *aes)
{
uint32_t tmpval = 0;
bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_CFG_0_OFFSET, &tmpval, 1, 1);
*sign = ((tmpval & EF_DATA_EF_SBOOT_SIGN_MODE_MSK) >> EF_DATA_EF_SBOOT_SIGN_MODE_POS) & 0x01;
*aes = ((tmpval & EF_DATA_EF_SF_AES_MODE_MSK) >> EF_DATA_EF_SF_AES_MODE_POS);
}
void bflb_efuse_write_aes_key(uint8_t index, uint8_t *data, uint32_t len)
{
if ((index <= 3) || (index == 11)) {
index = ((index == 11) ? 5 : index);
/* Every key is 4 words len*/
bflb_ef_ctrl_write_direct(NULL, 0x1C + index * 4, (uint32_t *)data, len, 1);
} else if ((index < 11) && (index > 3)) {
index = index - 4;
/* Every key is 4 words len*/
bflb_ef_ctrl_write_direct(NULL, 0x80 + index * 4, (uint32_t *)data, len, 1);
}
}
void bflb_efuse_read_aes_key(uint8_t index, uint8_t *data, uint32_t len)
{
if ((index <= 3) || (index == 11)) {
index = ((index == 11) ? 5 : index);
/* Every key is 4 words len*/
bflb_ef_ctrl_read_direct(NULL, 0x1C + index * 4, (uint32_t *)data, len, 1);
} else if ((index < 11) && (index > 3)) {
index = index - 4;
/* Every key is 4 words len*/
bflb_ef_ctrl_read_direct(NULL, 0x80 + index * 4, (uint32_t *)data, len, 1);
}
}
void bflb_efuse_lock_aes_key_write(uint8_t index)
{
uint32_t lock = 0;
if ((index <= 3) || (index == 11)) {
index = ((index == 11) ? 8 : index);
lock |= (1 << (index + 17));
bflb_ef_ctrl_write_direct(NULL, 0x7c, &lock, 1, 1);
} else if ((index < 11) && (index > 3)) {
index = index - 4;
lock |= (1 << (index + 15));
bflb_ef_ctrl_write_direct(NULL, 0xfc, &lock, 1, 1);
}
}
void bflb_efuse_lock_aes_key_read(uint8_t index)
{
uint32_t lock = 0;
if ((index <= 3) || (index == 11)) {
index = ((index == 11) ? 4 : index);
lock |= (1 << (index + 27));
bflb_ef_ctrl_write_direct(NULL, 0x7c, (uint32_t *)lock, 1, 1);
} else if ((index < 11) && (index > 3)) {
index = index - 4;
lock |= (1 << (index + 25));
bflb_ef_ctrl_write_direct(NULL, 0xfc, (uint32_t *)lock, 1, 1);
}
}
void bflb_efuse_write_sw_usage(uint32_t index, uint32_t usage, uint8_t program)
{
bflb_ef_ctrl_write_direct(NULL, EF_DATA_EF_SW_USAGE_0_OFFSET + index * 4, &usage, 1, program);
}
void bflb_efuse_read_sw_usage(uint32_t index, uint32_t *usage)
{
bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_SW_USAGE_0_OFFSET + index * 4, (uint32_t *)usage, 1, 1);
}

61
drivers/soc/bl616/bl616_std/src/bl616_glb.c
View file

@ -245,7 +245,7 @@ const GLB_SLAVE_GRP_0_TBL_Type ATTR_CLOCK_CONST_SECTION glb_slave_grp_0_table[GL
{ GLB_IR_CFG0_OFFSET, GLB_IR_CLK_EN_POS, 0, GLB_IR_CLK_DIV_POS, GLB_IR_CLK_EN_LEN, 0, GLB_IR_CLK_DIV_LEN },
{ GLB_I2C_CFG0_OFFSET, GLB_I2C_CLK_EN_POS, GLB_I2C_CLK_SEL_POS, GLB_I2C_CLK_DIV_POS, GLB_I2C_CLK_EN_LEN, GLB_I2C_CLK_SEL_LEN, GLB_I2C_CLK_DIV_LEN },
{ GLB_SPI_CFG0_OFFSET, GLB_SPI_CLK_EN_POS, GLB_SPI_CLK_SEL_POS, GLB_SPI_CLK_DIV_POS, GLB_SPI_CLK_EN_LEN, GLB_SPI_CLK_SEL_LEN, GLB_SPI_CLK_DIV_LEN },
{ 0, 0, 0, 0, 0, 0, 0 },
{ GLB_PEC_CFG0_OFFSET, GLB_PEC_CLK_EN_POS, GLB_PEC_CLK_SEL_POS, GLB_PEC_CLK_DIV_POS, GLB_PEC_CLK_EN_LEN, GLB_PEC_CLK_SEL_LEN, GLB_PEC_CLK_DIV_LEN },
{ GLB_DBI_CFG0_OFFSET, GLB_DBI_CLK_EN_POS, GLB_DBI_CLK_SEL_POS, GLB_DBI_CLK_DIV_POS, GLB_DBI_CLK_EN_LEN, GLB_DBI_CLK_SEL_LEN, GLB_DBI_CLK_DIV_LEN },
{ GLB_AUDIO_CFG0_OFFSET, GLB_REG_AUDIO_AUTO_DIV_EN_POS, 0, 0, GLB_REG_AUDIO_AUTO_DIV_EN_LEN, 0, 0 },
{ GLB_AUDIO_CFG0_OFFSET, GLB_REG_AUDIO_ADC_CLK_EN_POS, 0, GLB_REG_AUDIO_ADC_CLK_DIV_POS, GLB_REG_AUDIO_ADC_CLK_EN_LEN, 0, GLB_REG_AUDIO_ADC_CLK_DIV_LEN },
@ -1639,6 +1639,47 @@ BL_Err_Type GLB_SPI_Sig_Swap_Set(GLB_SPI_SIG_SWAP_GRP_Type group, uint8_t swap)
return SUCCESS;
}
/****************************************************************************/ /**
* @brief set PEC clock
*
* @param enable: Enable or disable PEC clock
* @param clkSel: clock selection
* @param div: divider
*
* @return SUCCESS or ERROR
*
*******************************************************************************/
BL_Err_Type GLB_Set_PEC_CLK(uint8_t enable, GLB_PEC_CLK_Type clkSel, uint8_t div)
{
#ifndef BOOTROM
uint32_t tmpVal = 0;
CHECK_PARAM(IS_GLB_PEC_CLK_TYPE(clkSel));
CHECK_PARAM((div <= 0x1F));
tmpVal = BL_RD_REG(GLB_BASE, GLB_PEC_CFG0);
tmpVal >>= 1;
tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_PEC_CLK_EN);
BL_WR_REG(GLB_BASE, GLB_PEC_CFG0, tmpVal);
tmpVal = BL_RD_REG(GLB_BASE, GLB_PEC_CFG0);
tmpVal >>= 1;
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PEC_CLK_DIV, div);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PEC_CLK_SEL, clkSel);
BL_WR_REG(GLB_BASE, GLB_PEC_CFG0, tmpVal);
tmpVal = BL_RD_REG(GLB_BASE, GLB_PEC_CFG0);
tmpVal >>= 1;
if (enable) {
tmpVal = BL_SET_REG_BIT(tmpVal, GLB_PEC_CLK_EN);
} else {
tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_PEC_CLK_EN);
}
BL_WR_REG(GLB_BASE, GLB_PEC_CFG0, tmpVal);
#endif
return SUCCESS;
}
/****************************************************************************/ /**
* @brief set PWM1 clock
*
@ -2856,6 +2897,9 @@ BL_Err_Type GLB_PER_Clock_Gate(uint64_t ips)
case GLB_AHB_CLOCK_IP_DBI:
tmpValCfg1 &= ~(1 << 24);
break;
case GLB_AHB_CLOCK_IP_PEC:
tmpValCfg2 &= ~(1 << 25);
break;
case GLB_AHB_CLOCK_IP_ISO11898:
tmpValCfg1 &= ~(1 << 26);
break;
@ -3042,6 +3086,9 @@ BL_Err_Type GLB_PER_Clock_UnGate(uint64_t ips)
case GLB_AHB_CLOCK_IP_DBI:
tmpValCfg1 |= (1 << 24);
break;
case GLB_AHB_CLOCK_IP_PEC:
tmpValCfg2 |= (1 << 25);
break;
case GLB_AHB_CLOCK_IP_ISO11898:
tmpValCfg1 |= (1 << 26);
break;
@ -3660,17 +3707,17 @@ BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_Slave_Grp_0_CLK(GLB_SLAVE_GRP_0_Type slav
BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_WIFI_PLL(GLB_XTAL_Type xtalType, const GLB_WA_PLL_Cfg_Type * pllCfgList)
{
GLB_PLL_REF_CLK_Type refClk;
if (xtalType == GLB_XTAL_RC32M) {
refClk = GLB_PLL_REFCLK_RC32M;
} else {
refClk = GLB_PLL_REFCLK_XTAL;
}
GLB_Power_Off_WIFIPLL();
GLB_WIFIPLL_Ref_Clk_Sel(refClk);
GLB_Power_On_WIFIPLL(&(pllCfgList[xtalType]), 1);
return SUCCESS;
}
@ -3686,17 +3733,17 @@ BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_WIFI_PLL(GLB_XTAL_Type xtalType, const
BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_AUDIO_PLL(GLB_XTAL_Type xtalType, const GLB_WA_PLL_Cfg_Type * pllCfgList)
{
GLB_PLL_REF_CLK_Type refClk;
if (xtalType == GLB_XTAL_RC32M) {
refClk = GLB_PLL_REFCLK_RC32M;
} else {
refClk = GLB_PLL_REFCLK_XTAL;
}
GLB_Power_Off_AUPLL();
GLB_AUPLL_Ref_Clk_Sel(refClk);
GLB_Power_On_AUPLL(&(pllCfgList[xtalType]), 1);
return SUCCESS;
}

434
drivers/soc/bl616/bl616_std/src/bl616_mfg_efuse.c Normal file
View file

@ -0,0 +1,434 @@
#include "bl616_glb.h"
#include "bl616_mfg_efuse.h"
#include "bflb_ef_ctrl.h"
#include "bflb_efuse.h"
static uint8_t rf_cal_slots = 3;
extern void main(void);
#define RF_CAL_SLOT_CFG_OFFSET (4 * 13)
#define mfg_print printf
uint8_t mfg_efuse_get_rf_cal_slots(void)
{
return rf_cal_slots;
}
void mfg_efuse_set_rf_cal_slots(uint8_t slots)
{
rf_cal_slots = slots;
}
static int mfg_efuse_get_empty_slot(char *name, int *slot, int32_t *last_val, uint8_t reload)
{
bflb_ef_ctrl_com_trim_t trim;
char buf[16] = { 0 };
int len = strlen(name);
*slot = -1;
*last_val = -1;
memcpy(buf, name, len);
buf[len + 1] = '\0';
if (rf_cal_slots >= 1) {
buf[len] = '0';
bflb_ef_ctrl_read_common_trim(NULL, buf, &trim, reload);
if (trim.empty) {
mfg_print("Empty slot:%d\r\n", 0);
*slot = 0;
return 0;
} else {
if (trim.en == 1 && trim.parity == bflb_ef_ctrl_get_trim_parity(trim.value, trim.len)) {
*last_val = (int32_t)trim.value;
}
}
}
if (rf_cal_slots >= 2) {
buf[len] = '1';
bflb_ef_ctrl_read_common_trim(NULL, buf, &trim, reload);
if (trim.empty) {
mfg_print("Empty slot:%d\r\n", 1);
*slot = 1;
return 0;
} else {
if (trim.en == 1 && trim.parity == bflb_ef_ctrl_get_trim_parity(trim.value, trim.len)) {
*last_val = (int32_t)trim.value;
}
}
}
if (rf_cal_slots >= 3) {
buf[len] = '2';
bflb_ef_ctrl_read_common_trim(NULL, buf, &trim, reload);
if (trim.empty) {
mfg_print("Empty slot:%d\r\n", 2);
*slot = 2;
return 0;
} else {
if (trim.en == 1 && trim.parity == bflb_ef_ctrl_get_trim_parity(trim.value, trim.len)) {
*last_val = (int32_t)trim.value;
}
}
}
return -1;
}
uint8_t mfg_efuse_is_xtal_capcode_slot_empty(uint8_t reload)
{
int slot;
int32_t last_val;
mfg_efuse_get_empty_slot("xtal", &slot, &last_val, reload);
if (slot == -1) {
return 0;
} else {
return 1;
}
}
int mfg_efuse_write_xtal_capcode_pre(uint8_t capcode, uint8_t program)
{
int slot;
int32_t last_val;
char buf[16];
mfg_efuse_get_empty_slot("xtal", &slot, &last_val, 1);
if (slot == -1) {
return -1;
} else {
sprintf(buf, "xtal%d", slot);
bflb_ef_ctrl_write_common_trim(NULL, buf, capcode, program);
mfg_print("Write slot:%d\r\n", slot);
return 0;
}
}
int mfg_efuse_read_xtal_capcode(uint8_t *capcode, uint8_t reload)
{
int slot;
int32_t last_val;
mfg_efuse_get_empty_slot("xtal", &slot, &last_val, reload);
if (last_val == -1) {
mfg_print("No written slot found\r\n");
return -1;
} else {
*capcode = (uint8_t)last_val;
return 0;
}
}
static void mfg_efuse_poweroffset_linear(int8_t pwr_offset[14], int8_t pwr_offset_tmp[3])
{
int32_t step = 0;
memset(pwr_offset, 0, 14);
pwr_offset[0] = pwr_offset_tmp[0];
step = (pwr_offset_tmp[1] - pwr_offset_tmp[0]) * 100 / 6;
pwr_offset[1] = (step + 50) / 100 + pwr_offset_tmp[0];
pwr_offset[2] = (step * 2 + 50) / 100 + pwr_offset_tmp[0];
pwr_offset[3] = (step * 3 + 50) / 100 + pwr_offset_tmp[0];
pwr_offset[4] = (step * 4 + 50) / 100 + pwr_offset_tmp[0];
pwr_offset[5] = (step * 5 + 50) / 100 + pwr_offset_tmp[0];
pwr_offset[6] = pwr_offset_tmp[1];
step = (pwr_offset_tmp[2] - pwr_offset_tmp[1]) * 100 / 6;
pwr_offset[7] = (step + 50) / 100 + pwr_offset_tmp[1];
pwr_offset[8] = (step * 2 + 50) / 100 + pwr_offset_tmp[1];
pwr_offset[9] = (step * 3 + 50) / 100 + pwr_offset_tmp[1];
pwr_offset[10] = (step * 4 + 50) / 100 + pwr_offset_tmp[1];
pwr_offset[11] = (step * 5 + 50) / 100 + pwr_offset_tmp[1];
pwr_offset[12] = pwr_offset_tmp[2];
pwr_offset[13] = (step * 7 + 50) / 100 + pwr_offset_tmp[1];
}
uint8_t mfg_efuse_is_hp_poweroffset_slot_empty(uint8_t reload)
{
int slot;
int32_t last_val;
mfg_efuse_get_empty_slot("hp_poffset", &slot, &last_val, reload);
if (slot == -1) {
return 0;
} else {
return 1;
}
}
int mfg_efuse_write_hp_poweroffset_pre(int8_t pwr_offset[14], uint8_t program)
{
int slot;
int32_t last_val;
char buf[32];
uint32_t cur_val = 0;
mfg_efuse_get_empty_slot("hp_poffset", &slot, &last_val, 1);
if (slot == -1) {
return -1;
} else {
sprintf(buf, "hp_poffset%d", slot);
cur_val = (pwr_offset[0] & 0x1f) | ((pwr_offset[6] & 0x1f) << 5) | ((pwr_offset[12] & 0x1f) << 10);
bflb_ef_ctrl_write_common_trim(NULL, buf, cur_val, program);
mfg_print("Write slot:%d\r\n", slot);
return 0;
}
}
void mfg_efuse_write_hp_poweroffset(void)
{
// EF_Ctrl_Program_Direct(0, NULL, 0);
// while (SET == EF_Ctrl_Busy())
// ;
}
int mfg_efuse_read_hp_poweroffset(int8_t pwr_offset[14], uint8_t reload)
{
int slot;
int32_t last_val;
int8_t pwr_offset_tmp[3];
uint32_t tmp = 0, k;
mfg_efuse_get_empty_slot("hp_poffset", &slot, &last_val, reload);
if (last_val == -1) {
mfg_print("No written slot found\r\n");
return -1;
} else {
for (k = 0; k < 3; k++) {
tmp = (last_val >> (k * 5)) & 0x1f;
if (tmp >= 16) {
pwr_offset_tmp[k] = tmp - 32;
} else {
pwr_offset_tmp[k] = tmp;
}
}
mfg_efuse_poweroffset_linear(pwr_offset, pwr_offset_tmp);
return 0;
}
}
uint8_t mfg_efuse_is_lp_poweroffset_slot_empty(uint8_t reload)
{
int slot;
int32_t last_val;
mfg_efuse_get_empty_slot("lp_poffset", &slot, &last_val, reload);
if (slot == -1) {
return 0;
} else {
return 1;
}
}
int mfg_efuse_write_lp_poweroffset_pre(int8_t pwr_offset[14], uint8_t program)
{
int slot;
int32_t last_val;
char buf[32];
uint32_t cur_val = 0;
mfg_efuse_get_empty_slot("lp_poffset", &slot, &last_val, 1);
if (slot == -1) {
return -1;
} else {
sprintf(buf, "lp_poffset%d", slot);
cur_val = (pwr_offset[0] & 0x1f) | ((pwr_offset[6] & 0x1f) << 5) | ((pwr_offset[12] & 0x1f) << 10);
bflb_ef_ctrl_write_common_trim(NULL, buf, cur_val, program);
mfg_print("Write slot:%d\r\n", slot);
return 0;
}
}
void mfg_efuse_write_lp_poweroffset(void)
{
bflb_ef_ctrl_write_direct(NULL, 0, NULL, 0, 1);
}
int mfg_efuse_read_lp_poweroffset(int8_t pwr_offset[14], uint8_t reload)
{
int slot;
int32_t last_val;
int8_t pwr_offset_tmp[3];
uint32_t tmp = 0, k;
mfg_efuse_get_empty_slot("lp_poffset", &slot, &last_val, reload);
if (last_val == -1) {
mfg_print("No written slot found\r\n");
return -1;
} else {
for (k = 0; k < 3; k++) {
tmp = (last_val >> (k * 5)) & 0x1f;
if (tmp >= 16) {
pwr_offset_tmp[k] = tmp - 32;
} else {
pwr_offset_tmp[k] = tmp;
}
}
mfg_efuse_poweroffset_linear(pwr_offset, pwr_offset_tmp);
return 0;
}
}
uint8_t mfg_efuse_is_macaddr_slot_empty(uint8_t reload)
{
uint8_t empty = 0;
if (rf_cal_slots >= 1 && bflb_efuse_is_mac_address_slot_empty(0, reload)) {
empty = 1;
} else if (rf_cal_slots >= 2 && bflb_efuse_is_mac_address_slot_empty(1, reload)) {
empty = 1;
} else if (rf_cal_slots >= 3 && bflb_efuse_is_mac_address_slot_empty(2, reload)) {
empty = 1;
} else {
}
return empty;
}
int8_t mfg_efuse_write_macaddr_pre(uint8_t mac[6], uint8_t program)
{
int ret = -1;
uint8_t slot = 0xff;
if (rf_cal_slots >= 1 && bflb_efuse_is_mac_address_slot_empty(0, 1)) {
slot = 0;
} else if (rf_cal_slots >= 2 && bflb_efuse_is_mac_address_slot_empty(1, 1)) {
slot = 1;
} else if (rf_cal_slots >= 3 && bflb_efuse_is_mac_address_slot_empty(2, 1)) {
slot = 2;
} else {
mfg_print("No empty slot found\r\n");
}
if (slot != 0xff) {
ret = bflb_efuse_write_mac_address_opt(slot, mac, program);
mfg_print("Write slot:%d\r\n", slot);
}
if (ret == 0) {
return 0;
} else {
return -1;
}
}
void mfg_efuse_write_macaddr(void)
{
bflb_ef_ctrl_write_direct(NULL, 0, NULL, 0, 1);
}
int8_t mfg_efuse_read_macaddr(uint8_t mac[6], uint8_t reload)
{
uint8_t slot = 0xff;
int ret = -1;
if (rf_cal_slots >= 3 && (!bflb_efuse_is_mac_address_slot_empty(2, reload))) {
slot = 2;
} else if (rf_cal_slots >= 2 && (!bflb_efuse_is_mac_address_slot_empty(1, reload))) {
slot = 1;
} else if (rf_cal_slots >= 1 && (!bflb_efuse_is_mac_address_slot_empty(0, reload))) {
slot = 0;
}
if (slot != 0xff) {
mfg_print("Read slot:%d\r\n", slot);
ret = bflb_efuse_read_mac_address_opt(slot, mac, reload);
} else {
mfg_print("No written slot found\r\n");
}
if (ret == 0) {
return 0;
} else {
return -1;
}
}
uint8_t mfg_efuse_is_bz_poweroffset_slot_empty(uint8_t reload)
{
int slot;
int32_t last_val;
mfg_efuse_get_empty_slot("bz_poffset", &slot, &last_val, reload);
if (slot == -1) {
return 0;
} else {
return 1;
}
}
int mfg_efuse_write_bz_poweroffset_pre(int8_t pwr_offset[5], uint8_t program)
{
int slot;
int32_t last_val;
char buf[32];
uint32_t cur_val = 0;
mfg_efuse_get_empty_slot("bz_poffset", &slot, &last_val, 1);
if (slot == -1) {
return -1;
} else {
sprintf(buf, "bz_poffset%d", slot);
cur_val = (pwr_offset[0] & 0x1f) | ((pwr_offset[1] & 0x1f) << 5) | ((pwr_offset[2] & 0x1f) << 10) | ((pwr_offset[3] & 0x1f) << 15) | ((pwr_offset[4] & 0x1f) << 20);
bflb_ef_ctrl_write_common_trim(NULL, buf, cur_val, program);
mfg_print("Write slot:%d\r\n", slot);
return 0;
}
}
void mfg_efuse_write_bz_poweroffset(void)
{
bflb_ef_ctrl_write_direct(NULL, 0, NULL, 0, 1);
}
int mfg_efuse_read_bz_poweroffset(int8_t pwr_offset[5], uint8_t reload)
{
int slot;
int32_t last_val;
uint32_t tmp = 0, k;
mfg_efuse_get_empty_slot("bz_poffset", &slot, &last_val, reload);
if (last_val == -1) {
mfg_print("No written slot found\r\n");
return -1;
} else {
for (k = 0; k < 5; k++) {
tmp = (last_val >> (k * 5)) & 0x1f;
if (tmp >= 16) {
pwr_offset[k] = tmp - 32;
} else {
pwr_offset[k] = tmp;
}
}
return 0;
}
}
void mfg_efuse_program(uint32_t addr, uint32_t *pword, uint32_t countInword, uint32_t program)
{
bflb_ef_ctrl_write_direct(NULL, addr, pword, countInword, program);
}
void mfg_efuse_read(uint32_t addr, uint32_t *pword, uint32_t countInword, uint8_t reload)
{
bflb_ef_ctrl_read_direct(NULL, addr, pword, countInword, reload);
}

117
drivers/soc/bl616/bl616_std/src/bl616_mfg_flash.c Normal file
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#include "bl616_mfg_flash.h"
#include "soft_crc.h"
//static rf_para_flash_t rf_para;
//static uint32_t rf_para_addr = 0;
//static SPI_Flash_Cfg_Type *pFlashCfg;
//#define RF_PARA_MAGIC_FLAG 0x41504652
#define RF_PARA_MAGIC_FLAG 0x41
#define RF_PARA_VALID_FLAG 0x5A
#define RF_PARA_PART_NAME "rf_para"
static BL_Err_Type PtTable_Flash_Read(uint32_t addr, uint8_t *data, uint32_t len)
{
return SUCCESS;
}
int mfg_flash_init(SPI_Flash_Cfg_Type *flashCfg)
{
PtTable_Flash_Read(0, NULL, 0);
return -1;
}
static int mfg_flash_program(void)
{
return 0;
}
static int mfg_flash_read(void)
{
return 0;
}
int mfg_flash_write_xtal_capcode_pre(uint8_t capcode, uint8_t program)
{
mfg_flash_program();
return 0;
}
void mfg_flash_write_xtal_capcode(void)
{
mfg_flash_program();
}
int mfg_flash_read_xtal_capcode(uint8_t *capcode, uint8_t reload)
{
mfg_flash_read();
return 0;
}
int mfg_flash_write_hp_poweroffset_pre(int8_t pwrOffset[14], uint8_t program)
{
mfg_flash_program();
return 0;
}
void mfg_flash_write_hp_poweroffset(void)
{
mfg_flash_program();
}
int mfg_flash_read_hp_poweroffset(int8_t pwrOffset[14], uint8_t reload)
{
mfg_flash_read();
return 0;
}
int mfg_flash_write_lp_poweroffset_pre(int8_t pwrOffset[14], uint8_t program)
{
mfg_flash_program();
return 0;
}
void mfg_flash_write_lp_poweroffset(void)
{
mfg_flash_program();
}
int mfg_flash_read_lp_poweroffset(int8_t pwrOffset[14], uint8_t reload)
{
mfg_flash_read();
return 0;
}
int mfg_flash_write_macaddr_pre(uint8_t mac[6], uint8_t program)
{
mfg_flash_program();
return 0;
}
void mfg_flash_write_macaddr(void)
{
mfg_flash_program();
}
int mfg_flash_read_macaddr(uint8_t mac[6], uint8_t reload)
{
mfg_flash_read();
return 0;
}
int mfg_flash_write_bz_poweroffset_pre(int8_t pwrOffset[5], uint8_t program)
{
mfg_flash_program();
return 0;
}
void mfg_flash_write_bz_poweroffset(void)
{
mfg_flash_program();
}
int mfg_flash_read_bz_poweroffset(int8_t pwrOffset[5], uint8_t reload)
{
mfg_flash_read();
return 0;
}

376
drivers/soc/bl616/bl616_std/src/bl616_mfg_media.c Normal file
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#include "bl616_mfg_media.h"
static uint8_t rf_para_on_flash = 0;
int mfg_media_init_need_lock(SPI_Flash_Cfg_Type *flashCfg)
{
if (0 == mfg_flash_init(flashCfg)) {
rf_para_on_flash = 1;
} else {
rf_para_on_flash = 0;
}
return 0;
}
int mfg_media_init_with_lock(SPI_Flash_Cfg_Type *flashCfg)
{
int ret;
__disable_irq();
ret = mfg_media_init_need_lock(flashCfg);
__enable_irq();
return ret;
}
uint8_t mfg_media_is_xtal_capcode_slot_empty(uint8_t reload)
{
if (rf_para_on_flash) {
return 1;
} else {
return mfg_efuse_is_xtal_capcode_slot_empty(reload);
}
}
int mfg_media_write_xtal_capcode_pre_need_lock(uint8_t capcode, uint8_t program)
{
if (rf_para_on_flash) {
return mfg_flash_write_xtal_capcode_pre(capcode, program);
} else {
return mfg_efuse_write_xtal_capcode_pre(capcode, program);
}
}
int mfg_media_write_xtal_capcode_pre_with_lock(uint8_t capcode, uint8_t program)
{
int ret;
__disable_irq();
ret = mfg_media_write_xtal_capcode_pre_need_lock(capcode, program);
__enable_irq();
return ret;
}
void mfg_media_write_xtal_capcode_need_lock(void)
{
if (rf_para_on_flash) {
return mfg_flash_write_xtal_capcode();
} else {
return mfg_efuse_write_xtal_capcode();
}
}
void mfg_media_write_xtal_capcode_with_lock(void)
{
__disable_irq();
mfg_media_write_xtal_capcode_need_lock();
__enable_irq();
}
int mfg_media_read_xtal_capcode_need_lock(uint8_t *capcode, uint8_t reload)
{
if (rf_para_on_flash) {
return mfg_flash_read_xtal_capcode(capcode, reload);
} else {
return mfg_efuse_read_xtal_capcode(capcode, reload);
}
}
int mfg_media_read_xtal_capcode_with_lock(uint8_t *capcode, uint8_t reload)
{
int ret;
__disable_irq();
ret = mfg_media_read_xtal_capcode_need_lock(capcode, reload);
__enable_irq();
return ret;
}
int mfg_media_read_xtal_capcode(uint8_t *capcode, uint8_t reload)
{
return mfg_media_read_xtal_capcode_need_lock(capcode, reload);
}
uint8_t mfg_media_is_hp_poweroffset_slot_empty(uint8_t reload)
{
if (rf_para_on_flash) {
return 1;
} else {
return mfg_efuse_is_hp_poweroffset_slot_empty(reload);
}
}
int mfg_media_write_hp_poweroffset_pre_need_lock(int8_t pwrOffset[14], uint8_t program)
{
if (rf_para_on_flash) {
return mfg_flash_write_hp_poweroffset_pre(pwrOffset, program);
} else {
return mfg_efuse_write_hp_poweroffset_pre(pwrOffset, program);
}
}
int mfg_media_write_hp_poweroffset_pre_with_lock(int8_t pwrOffset[14], uint8_t program)
{
int ret;
__disable_irq();
ret = mfg_media_write_hp_poweroffset_pre_need_lock(pwrOffset, program);
__enable_irq();
return ret;
}
void mfg_media_write_hp_poweroffset_need_lock(void)
{
if (rf_para_on_flash) {
return mfg_flash_write_hp_poweroffset();
} else {
return mfg_efuse_write_hp_poweroffset();
}
}
void mfg_media_write_hp_poweroffset_with_lock(void)
{
__disable_irq();
mfg_media_write_hp_poweroffset_need_lock();
__enable_irq();
}
int mfg_media_read_hp_poweroffset_need_lock(int8_t pwrOffset[14], uint8_t reload)
{
if (rf_para_on_flash) {
return mfg_flash_read_hp_poweroffset(pwrOffset, reload);
} else {
return mfg_efuse_read_hp_poweroffset(pwrOffset, reload);
}
}
int mfg_media_read_hp_poweroffset_with_lock(int8_t pwrOffset[14], uint8_t reload)
{
int ret;
__disable_irq();
ret = mfg_media_read_hp_poweroffset_need_lock(pwrOffset, reload);
__enable_irq();
return ret;
}
int mfg_media_read_hp_poweroffset(int8_t pwrOffset[14], uint8_t reload)
{
return mfg_media_read_hp_poweroffset_need_lock(pwrOffset, reload);
}
uint8_t mfg_media_is_lp_poweroffset_slot_empty(uint8_t reload)
{
if (rf_para_on_flash) {
return 1;
} else {
return mfg_efuse_is_lp_poweroffset_slot_empty(reload);
}
}
int mfg_media_write_lp_poweroffset_pre_need_lock(int8_t pwrOffset[14], uint8_t program)
{
if (rf_para_on_flash) {
return mfg_flash_write_lp_poweroffset_pre(pwrOffset, program);
} else {
return mfg_efuse_write_lp_poweroffset_pre(pwrOffset, program);
}
}
int mfg_media_write_lp_poweroffset_pre_with_lock(int8_t pwrOffset[14], uint8_t program)
{
int ret;
__disable_irq();
ret = mfg_media_write_lp_poweroffset_pre_need_lock(pwrOffset, program);
__enable_irq();
return ret;
}
void mfg_media_write_lp_poweroffset_need_lock(void)
{
if (rf_para_on_flash) {
return mfg_flash_write_lp_poweroffset();
} else {
return mfg_efuse_write_lp_poweroffset();
}
}
void mfg_media_write_lp_poweroffset_with_lock(void)
{
__disable_irq();
mfg_media_write_lp_poweroffset_need_lock();
__enable_irq();
}
int mfg_media_read_lp_poweroffset_need_lock(int8_t pwrOffset[14], uint8_t reload)
{
if (rf_para_on_flash) {
return mfg_flash_read_lp_poweroffset(pwrOffset, reload);
} else {
return mfg_efuse_read_lp_poweroffset(pwrOffset, reload);
}
}
int mfg_media_read_lp_poweroffset_with_lock(int8_t pwrOffset[14], uint8_t reload)
{
int ret;
__disable_irq();
ret = mfg_media_read_lp_poweroffset_need_lock(pwrOffset, reload);
__enable_irq();
return ret;
}
int mfg_media_read_lp_poweroffset(int8_t pwrOffset[14], uint8_t reload)
{
return mfg_media_read_lp_poweroffset_need_lock(pwrOffset, reload);
}
uint8_t mfg_media_is_macaddr_slot_empty(uint8_t reload)
{
if (rf_para_on_flash) {
return 1;
} else {
return mfg_efuse_is_macaddr_slot_empty(reload);
}
}
int mfg_media_write_macaddr_pre_need_lock(uint8_t mac[6], uint8_t program)
{
if (rf_para_on_flash) {
return mfg_flash_write_macaddr_pre(mac, program);
} else {
return mfg_efuse_write_macaddr_pre(mac, program);
}
}
int mfg_media_write_macaddr_pre_with_lock(uint8_t mac[6], uint8_t program)
{
int ret;
__disable_irq();
ret = mfg_media_write_macaddr_pre_need_lock(mac, program);
__enable_irq();
return ret;
}
void mfg_media_write_macaddr_need_lock(void)
{
if (rf_para_on_flash) {
return mfg_flash_write_macaddr();
} else {
return mfg_efuse_write_macaddr();
}
}
void mfg_media_write_macaddr_with_lock(void)
{
__disable_irq();
mfg_media_write_macaddr_need_lock();
__enable_irq();
}
int mfg_media_read_macaddr_need_lock(uint8_t mac[6], uint8_t reload)
{
if (rf_para_on_flash) {
return mfg_flash_read_macaddr(mac, reload);
} else {
return mfg_efuse_read_macaddr(mac, reload);
}
}
int mfg_media_read_macaddr_with_lock(uint8_t mac[6], uint8_t reload)
{
int ret;
__disable_irq();
ret = mfg_media_read_macaddr_need_lock(mac, reload);
__enable_irq();
return ret;
}
int mfg_media_read_macaddr(uint8_t mac[6], uint8_t reload)
{
return mfg_media_read_macaddr_need_lock(mac, reload);
}
uint8_t mfg_media_is_bz_poweroffset_slot_empty(uint8_t reload)
{
if (rf_para_on_flash) {
return 1;
} else {
return mfg_efuse_is_bz_poweroffset_slot_empty(reload);
}
}
int mfg_media_write_bz_poweroffset_pre_need_lock(int8_t pwrOffset[5], uint8_t program)
{
if (rf_para_on_flash) {
return mfg_flash_write_bz_poweroffset_pre(pwrOffset, program);
} else {
return mfg_efuse_write_bz_poweroffset_pre(pwrOffset, program);
}
}
int mfg_media_write_bz_poweroffset_pre_with_lock(int8_t pwrOffset[5], uint8_t program)
{
int ret;
__disable_irq();
ret = mfg_media_write_bz_poweroffset_pre_need_lock(pwrOffset, program);
__enable_irq();
return ret;
}
void mfg_media_write_bz_poweroffset_need_lock(void)
{
if (rf_para_on_flash) {
return mfg_flash_write_bz_poweroffset();
} else {
return mfg_efuse_write_bz_poweroffset();
}
}
void mfg_media_write_bz_poweroffset_with_lock(void)
{
__disable_irq();
mfg_media_write_bz_poweroffset_need_lock();
__enable_irq();
}
int mfg_media_read_bz_poweroffset_need_lock(int8_t pwrOffset[5], uint8_t reload)
{
if (rf_para_on_flash) {
return mfg_flash_read_bz_poweroffset(pwrOffset, reload);
} else {
return mfg_efuse_read_bz_poweroffset(pwrOffset, reload);
}
}
int mfg_media_read_bz_poweroffset_with_lock(int8_t pwrOffset[5], uint8_t reload)
{
int ret;
__disable_irq();
ret = mfg_media_read_bz_poweroffset_need_lock(pwrOffset, reload);
__enable_irq();
return ret;
}
int mfg_media_read_bz_poweroffset(int8_t pwrOffset[5], uint8_t reload)
{
return mfg_media_read_bz_poweroffset_need_lock(pwrOffset, reload);
}

8
drivers/soc/bl616/bl616_std/src/bl616_romapi_patch.c
View file

@ -1098,7 +1098,7 @@ BL_Err_Type ATTR_TCM_SECTION SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(uint32_t flashID
pCrc = (uint32_t *)(buf + 4 + sizeof(SPI_Flash_Cfg_Type));
if (*pCrc == crc) {
ARCH_MemCpy_Fast(pFlashCfg, (uint8_t *)buf + 4, sizeof(SPI_Flash_Cfg_Type));
arch_memcpy_fast(pFlashCfg, (uint8_t *)buf + 4, sizeof(SPI_Flash_Cfg_Type));
return SUCCESS;
}
}
@ -1108,7 +1108,7 @@ BL_Err_Type ATTR_TCM_SECTION SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(uint32_t flashID
}
for (i = 0; i < sizeof(flashInfos) / sizeof(flashInfos[0]); i++) {
if (flashInfos[i].jedecID == flashID) {
ARCH_MemCpy_Fast(pFlashCfg, flashInfos[i].cfg, sizeof(SPI_Flash_Cfg_Type));
arch_memcpy_fast(pFlashCfg, flashInfos[i].cfg, sizeof(SPI_Flash_Cfg_Type));
return SUCCESS;
}
}
@ -1148,7 +1148,7 @@ uint32_t ATTR_TCM_SECTION SF_Cfg_Flash_Identify_Ext(uint8_t callFromFlash, uint8
jdecId = (ret & 0xffffff);
for (i = 0; i < sizeof(flashInfos) / sizeof(flashInfos[0]); i++) {
if (flashInfos[i].jedecID == jdecId) {
ARCH_MemCpy_Fast(pFlashCfg, flashInfos[i].cfg, sizeof(SPI_Flash_Cfg_Type));
arch_memcpy_fast(pFlashCfg, flashInfos[i].cfg, sizeof(SPI_Flash_Cfg_Type));
break;
}
}
@ -1179,7 +1179,7 @@ BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Read_Via_Cache_Need_Lock(uint32_t addr,
offset = SF_Ctrl_Get_Flash_Image_Offset(0, SF_CTRL_FLASH_BANK0);
SF_Ctrl_Set_Flash_Image_Offset(0, 0, SF_CTRL_FLASH_BANK0);
/* Flash read */
ARCH_MemCpy_Fast(data, (void *)(uintptr_t)(addr - SF_Ctrl_Get_Flash_Image_Offset(0, SF_CTRL_FLASH_BANK0)), len);
arch_memcpy_fast(data, (void *)(uintptr_t)(addr - SF_Ctrl_Get_Flash_Image_Offset(0, SF_CTRL_FLASH_BANK0)), len);
SF_Ctrl_Set_Flash_Image_Offset(offset, 0, SF_CTRL_FLASH_BANK0);
return SUCCESS;

8
drivers/soc/bl616/bl616_std/src/bl616_sf_cfg.c
View file

@ -2650,14 +2650,14 @@ BL_Err_Type ATTR_TCM_SECTION SF_Cfg_Get_Flash_Cfg_Need_Lock(uint32_t flashID, SP
pCrc = (uint32_t *)(buf + 4 + sizeof(SPI_Flash_Cfg_Type));
if (*pCrc == crc) {
ARCH_MemCpy_Fast(pFlashCfg, (uint8_t *)buf + 4, sizeof(SPI_Flash_Cfg_Type));
arch_memcpy_fast(pFlashCfg, (uint8_t *)buf + 4, sizeof(SPI_Flash_Cfg_Type));
return SUCCESS;
}
}
} else {
for (i = 0; i < sizeof(flashInfos) / sizeof(flashInfos[0]); i++) {
if (flashInfos[i].jedecID == flashID) {
ARCH_MemCpy_Fast(pFlashCfg, flashInfos[i].cfg, sizeof(SPI_Flash_Cfg_Type));
arch_memcpy_fast(pFlashCfg, flashInfos[i].cfg, sizeof(SPI_Flash_Cfg_Type));
return SUCCESS;
}
}
@ -2784,7 +2784,7 @@ uint32_t ATTR_TCM_SECTION SF_Cfg_Flash_Identify(uint8_t callFromFlash, uint8_t f
autoScan = ((flashPinCfg >> 7) & 1);
flashPin = (flashPinCfg & 0x7F);
ARCH_MemCpy_Fast(pFlashCfg, &flashCfg_Winb_16JV, sizeof(SPI_Flash_Cfg_Type));
arch_memcpy_fast(pFlashCfg, &flashCfg_Winb_16JV, sizeof(SPI_Flash_Cfg_Type));
if (callFromFlash == 1) {
stat = XIP_SFlash_State_Save(pFlashCfg, &offset, group, bank);
@ -2850,7 +2850,7 @@ uint32_t ATTR_TCM_SECTION SF_Cfg_Flash_Identify(uint8_t callFromFlash, uint8_t f
for (i = 0; i < sizeof(flashInfos) / sizeof(flashInfos[0]); i++) {
if (flashInfos[i].jedecID == jdecId) {
ARCH_MemCpy_Fast(pFlashCfg, flashInfos[i].cfg, sizeof(SPI_Flash_Cfg_Type));
arch_memcpy_fast(pFlashCfg, flashInfos[i].cfg, sizeof(SPI_Flash_Cfg_Type));
break;
}
}

4
drivers/soc/bl616/bl616_std/src/bl616_sflash.c
View file

@ -2045,7 +2045,7 @@ BL_Err_Type ATTR_TCM_SECTION SFlash_Read(SPI_Flash_Cfg_Type *flashCfg,
}
}
ARCH_MemCpy_Fast(data, flashCtrlBuf, curLen);
arch_memcpy_fast(data, flashCtrlBuf, curLen);
addr += curLen;
i += curLen;
@ -2122,7 +2122,7 @@ BL_Err_Type ATTR_TCM_SECTION SFlash_Program(SPI_Flash_Cfg_Type *flashCfg,
}
/* Prepare command */
ARCH_MemCpy_Fast(flashCtrlBuf, data, curLen);
arch_memcpy_fast(flashCtrlBuf, data, curLen);
if (is32BitsAddr > 0) {
flashCmd.cmdBuf[0] = (cmd << 24) | (addr >> 8);

42
drivers/soc/bl616/bl616_std/src/bl616_tzc_sec.c
View file

@ -272,7 +272,7 @@ void Tzc_Sec_Set_CPU_Group(uint8_t cpu, uint8_t group)
void Tzc_Sec_ROM_Access_Set(uint8_t region, uint32_t startAddr, uint32_t length, uint8_t group)
{
uint32_t tmpVal = 0;
uint32_t alignEnd = (startAddr+length+1023)&~0x3FF;
uint32_t alignEnd = (startAddr + length + 1023) & ~0x3FF;
/* check the parameter */
CHECK_PARAM(IS_TZC_SEC_GROUP_TYPE(group));
@ -310,7 +310,7 @@ void Tzc_Sec_ROM_Access_Set(uint8_t region, uint32_t startAddr, uint32_t length,
void Tzc_Sec_ROM_Access_Set_Advance(uint8_t region, uint32_t startAddr, uint32_t length, uint8_t group)
{
uint32_t tmpVal = 0;
uint32_t alignEnd = (startAddr+length+1023)&~0x3FF;
uint32_t alignEnd = (startAddr + length + 1023) & ~0x3FF;
/* check the parameter */
CHECK_PARAM(IS_TZC_SEC_GROUP_TYPE(group));
@ -348,7 +348,7 @@ void Tzc_Sec_ROM_Access_Set_Advance(uint8_t region, uint32_t startAddr, uint32_t
void Tzc_Sec_OCRAM_Access_Set_Advance(uint8_t region, uint32_t startAddr, uint32_t length, uint8_t group)
{
uint32_t tmpVal = 0;
uint32_t alignEnd = (startAddr+length+1023)&~0x3FF;
uint32_t alignEnd = (startAddr + length + 1023) & ~0x3FF;
/* check the parameter */
CHECK_PARAM(IS_TZC_SEC_GROUP_TYPE(group));
@ -418,7 +418,7 @@ void Tzc_Sec_OCRAM_Access_Set_Regionx(uint8_t group)
void Tzc_Sec_WRAM_Access_Set_Advance(uint8_t region, uint32_t startAddr, uint32_t length, uint8_t group)
{
uint32_t tmpVal = 0;
uint32_t alignEnd = (startAddr+length+1023)&~0x3FF;
uint32_t alignEnd = (startAddr + length + 1023) & ~0x3FF;
/* check the parameter */
CHECK_PARAM(IS_TZC_SEC_GROUP_TYPE(group));
@ -474,6 +474,32 @@ void Tzc_Sec_WRAM_Access_Set_Regionx(uint8_t group)
BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_WRAM_TZSRG_CTRL, tmpVal);
}
/****************************************************************************/ /**
* @brief TrustZone Security set HBNRAM region access configuration
*
* @param startAddr: HBNRAM region start address
* @param length: HBNRAM region end length
*
* @return None
*
*******************************************************************************/
void Tzc_Sec_HBNRAM_Access_Set(uint32_t startAddr, uint32_t length)
{
uint32_t tmpVal = 0;
uint32_t alignEnd = (startAddr + length + 3) & ~0x3;
tmpVal = BL_RD_REG(AON_BASE, AON_TZC_HBNRAM_R0);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_TZC_HBNRAM_R0_START, ((startAddr >> 2) & 0xffff));
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_TZC_HBNRAM_R0_END, (((alignEnd >> 2) & 0xffff) - 1));
BL_WR_REG(AON_BASE, AON_TZC_HBNRAM_R0, tmpVal);
/* set enable and lock */
tmpVal = BL_RD_REG(AON_BASE, AON_TZC_HBNRAM_CTRL);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_TZC_HBNRAM_R0_EN, 1);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_TZC_HBNRAM_R0_LOCK, 1);
BL_WR_REG(AON_BASE, AON_TZC_HBNRAM_CTRL, tmpVal);
}
/****************************************************************************/ /**
* @brief TrustZone Security set Flash region access configuration
*
@ -489,7 +515,7 @@ void Tzc_Sec_Flash_Access_Set(uint8_t region, uint32_t startAddr, uint32_t lengt
{
uint32_t tmpVal = 0;
uint32_t tmpVal2 = 0;
uint32_t alignEnd = (startAddr+length+1023)&~0x3FF;
uint32_t alignEnd = (startAddr + length + 1023) & ~0x3FF;
/* check the parameter */
CHECK_PARAM(IS_TZC_SEC_GROUP_TYPE(group));
@ -568,7 +594,7 @@ void Tzc_Sec_Flash_Access_Set_Advance(uint8_t region, uint32_t startAddr, uint32
{
uint32_t tmpVal = 0;
uint32_t tmpVal2 = 0;
uint32_t alignEnd = (startAddr+length+1023)&~0x3FF;
uint32_t alignEnd = (startAddr + length + 1023) & ~0x3FF;
/* check the parameter */
CHECK_PARAM(IS_TZC_SEC_GROUP_TYPE(group));
@ -614,7 +640,7 @@ void Tzc_Sec_Flash_Access_Set_Advance(uint8_t region, uint32_t startAddr, uint32
void Tzc_Sec_PSRAMB_Access_Set(uint8_t region, uint32_t startAddr, uint32_t length, uint8_t group)
{
uint32_t tmpVal = 0;
uint32_t alignEnd = (startAddr+length+1023)&~0x3FF;
uint32_t alignEnd = (startAddr + length + 1023) & ~0x3FF;
/* check the parameter */
CHECK_PARAM(IS_TZC_SEC_GROUP_TYPE(group));
@ -666,7 +692,7 @@ void Tzc_Sec_PSRAMB_Access_Release(void)
void Tzc_Sec_PSRAMB_Access_Set_Advance(uint8_t region, uint32_t startAddr, uint32_t length, uint8_t group)
{
uint32_t tmpVal = 0;
uint32_t alignEnd = (startAddr+length+1023)&~0x3FF;
uint32_t alignEnd = (startAddr + length + 1023) & ~0x3FF;
/* check the parameter */
CHECK_PARAM(IS_TZC_SEC_GROUP_TYPE(group));

2
drivers/soc/bl616/bl616_std/src/bl616_xip_sflash.c
View file

@ -420,7 +420,7 @@ BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Read_Via_Cache_Need_Lock(uint32_t addr,
offset = SF_Ctrl_Get_Flash_Image_Offset(0, SF_CTRL_FLASH_BANK0);
SF_Ctrl_Set_Flash_Image_Offset(0, 0, SF_CTRL_FLASH_BANK0);
/* Flash read */
ARCH_MemCpy_Fast(data, (void *)(uintptr_t)(addr - SF_Ctrl_Get_Flash_Image_Offset(0, SF_CTRL_FLASH_BANK0)), len);
arch_memcpy_fast(data, (void *)(uintptr_t)(addr - SF_Ctrl_Get_Flash_Image_Offset(0, SF_CTRL_FLASH_BANK0)), len);
SF_Ctrl_Set_Flash_Image_Offset(offset, 0, SF_CTRL_FLASH_BANK0);
return SUCCESS;

102
drivers/soc/bl616/port/bl616_efuse.c
View file

@ -1,102 +0,0 @@
#include "bflb_ef_ctrl.h"
#include "bflb_efuse.h"
#include "bl616_ef_ctrl.h"
float bflb_efuse_get_adc_trim(void)
{
bflb_ef_ctrl_com_trim_type trim;
uint32_t tmp;
float coe = 1.0;
//EF_Ctrl_Read_ADC_Gain_Trim(&trim);
bflb_ef_ctrl_read_common_trim(NULL, "gpadc_gain", &trim, 1);
if (trim.en) {
if (trim.parity == bflb_ef_ctrl_get_trim_parity(trim.value, trim.len)) {
tmp = trim.value;
if (tmp & 0x800) {
tmp = ~tmp;
tmp += 1;
tmp = tmp & 0xfff;
coe = (1.0 + ((float)tmp / 2048.0));
} else {
coe = (1.0 - ((float)tmp / 2048.0));
}
}
}
return coe;
}
uint32_t bflb_efuse_get_adc_tsen_trim(void)
{
bflb_ef_ctrl_com_trim_type trim;
//EF_Ctrl_Read_TSEN_Trim(&trim);
bflb_ef_ctrl_read_common_trim(NULL, "tsen", &trim, 1);
if (trim.en) {
if (trim.parity == bflb_ef_ctrl_get_trim_parity(trim.value, trim.len)) {
return trim.value;
}
}
return 2042;
}
void bflb_efuse_write_aes_key(uint8_t index, uint8_t *data, uint32_t len)
{
if ((index <= 3) || (index == 11)) {
index = ((index == 11) ? 5 : index);
/* Every key is 4 words len*/
bflb_ef_ctrl_write_direct(NULL, 0x1C + index * 4, (uint32_t *)data, len, 1);
} else if ((index < 11) && (index > 3)) {
index = index - 4;
/* Every key is 4 words len*/
bflb_ef_ctrl_write_direct(NULL, 0x80 + index * 4, (uint32_t *)data, len, 1);
}
}
void bflb_efuse_lock_aes_key_write(uint8_t index)
{
uint32_t lock = 0;
if ((index <= 3) || (index == 11)) {
index = ((index == 11) ? 8 : index);
lock |= (1 << (index + 17));
bflb_ef_ctrl_write_direct(NULL, 0x7c, (uint32_t *)lock, 1, 1);
} else if ((index < 11) && (index > 3)) {
index = index - 4;
lock |= (1 << (index + 15));
bflb_ef_ctrl_write_direct(NULL, 0xfc, (uint32_t *)lock, 1, 1);
}
}
void bflb_efuse_lock_aes_key_read(uint8_t index)
{
uint32_t lock = 0;
if ((index <= 3) || (index == 11)) {
index = ((index == 11) ? 4 : index);
lock |= (1 << (index + 27));
bflb_ef_ctrl_write_direct(NULL, 0x7c, (uint32_t *)lock, 1, 1);
} else if ((index < 11) && (index > 3)) {
index = index - 4;
lock |= (1 << (index + 25));
bflb_ef_ctrl_write_direct(NULL, 0xfc, (uint32_t *)lock, 1, 1);
}
}
void bflb_efuse_read_aes_key(uint8_t index, uint8_t *data, uint32_t len)
{
if ((index <= 3) || (index == 11)) {
index = ((index == 11) ? 5 : index);
/* Every key is 4 words len*/
bflb_ef_ctrl_read_direct(NULL, 0x1C + index * 4, (uint32_t *)data, len, 1);
} else if ((index < 11) && (index > 3)) {
index = index - 4;
/* Every key is 4 words len*/
bflb_ef_ctrl_read_direct(NULL, 0x80 + index * 4, (uint32_t *)data, len, 1);
}
}

227
drivers/soc/bl616/port/bl616_flash.c
View file

@ -8,8 +8,200 @@ static uint32_t flash1_size = 4 * 1024 * 1024;
static uint32_t flash2_size = 2 * 1024 * 1024;
static uint32_t g_jedec_id = 0;
static uint32_t g_jedec_id2 = 0;
static SPI_Flash_Cfg_Type g_flash_cfg;
static SPI_Flash_Cfg_Type g_flash2_cfg;
static SPI_Flash_Cfg_Type g_flash_cfg = {
.resetCreadCmd = 0xff,
.resetCreadCmdSize = 3,
.mid = 0xc8,
.deBurstWrapCmd = 0x77,
.deBurstWrapCmdDmyClk = 0x3,
.deBurstWrapDataMode = SF_CTRL_DATA_4_LINES,
.deBurstWrapData = 0xF0,
/* reg */
.writeEnableCmd = 0x06,
.wrEnableIndex = 0x00,
.wrEnableBit = 0x01,
.wrEnableReadRegLen = 0x01,
.qeIndex = 1,
.qeBit = 0x01,
.qeWriteRegLen = 0x01,
.qeReadRegLen = 0x1,
.busyIndex = 0,
.busyBit = 0x00,
.busyReadRegLen = 0x1,
.releasePowerDown = 0xab,
.readRegCmd[0] = 0x05,
.readRegCmd[1] = 0x35,
.writeRegCmd[0] = 0x01,
.writeRegCmd[1] = 0x31,
.fastReadQioCmd = 0xeb,
.frQioDmyClk = 16 / 8,
.cReadSupport = 0,
.cReadMode = 0x20,
.burstWrapCmd = 0x77,
.burstWrapCmdDmyClk = 0x3,
.burstWrapDataMode = SF_CTRL_DATA_4_LINES,
.burstWrapData = 0x40,
/* erase */
.chipEraseCmd = 0xc7,
.sectorEraseCmd = 0x20,
.blk32EraseCmd = 0x52,
.blk64EraseCmd = 0xd8,
/* write */
.pageProgramCmd = 0x02,
.qpageProgramCmd = 0x32,
.qppAddrMode = SF_CTRL_ADDR_1_LINE,
.ioMode = 0x10,
.clkDelay = 0,
.clkInvert = 0x03,
.resetEnCmd = 0x66,
.resetCmd = 0x99,
.cRExit = 0xff,
.wrEnableWriteRegLen = 0x00,
/* id */
.jedecIdCmd = 0x9f,
.jedecIdCmdDmyClk = 0,
.enter32BitsAddrCmd = 0xb7,
.exit32BitsAddrCmd = 0xe9,
.sectorSize = 4,
.pageSize = 256,
/* read */
.fastReadCmd = 0x0b,
.frDmyClk = 8 / 8,
.qpiFastReadCmd = 0x0b,
.qpiFrDmyClk = 8 / 8,
.fastReadDoCmd = 0x3b,
.frDoDmyClk = 8 / 8,
.fastReadDioCmd = 0xbb,
.frDioDmyClk = 0,
.fastReadQoCmd = 0x6b,
.frQoDmyClk = 8 / 8,
.qpiFastReadQioCmd = 0xeb,
.qpiFrQioDmyClk = 16 / 8,
.qpiPageProgramCmd = 0x02,
.writeVregEnableCmd = 0x50,
/* qpi mode */
.enterQpi = 0x38,
.exitQpi = 0xff,
/* AC */
.timeEsector = 300,
.timeE32k = 1200,
.timeE64k = 1200,
.timePagePgm = 5,
.timeCe = 33 * 1000,
.pdDelay = 20,
.qeData = 0,
};
static SPI_Flash_Cfg_Type g_flash2_cfg = {
.resetCreadCmd = 0xff,
.resetCreadCmdSize = 3,
.mid = 0xc8,
.deBurstWrapCmd = 0x77,
.deBurstWrapCmdDmyClk = 0x3,
.deBurstWrapDataMode = SF_CTRL_DATA_4_LINES,
.deBurstWrapData = 0xF0,
/* reg */
.writeEnableCmd = 0x06,
.wrEnableIndex = 0x00,
.wrEnableBit = 0x01,
.wrEnableReadRegLen = 0x01,
.qeIndex = 1,
.qeBit = 0x01,
.qeWriteRegLen = 0x01,
.qeReadRegLen = 0x1,
.busyIndex = 0,
.busyBit = 0x00,
.busyReadRegLen = 0x1,
.releasePowerDown = 0xab,
.readRegCmd[0] = 0x05,
.readRegCmd[1] = 0x35,
.writeRegCmd[0] = 0x01,
.writeRegCmd[1] = 0x31,
.fastReadQioCmd = 0xeb,
.frQioDmyClk = 16 / 8,
.cReadSupport = 0,
.cReadMode = 0x20,
.burstWrapCmd = 0x77,
.burstWrapCmdDmyClk = 0x3,
.burstWrapDataMode = SF_CTRL_DATA_4_LINES,
.burstWrapData = 0x40,
/* erase */
.chipEraseCmd = 0xc7,
.sectorEraseCmd = 0x20,
.blk32EraseCmd = 0x52,
.blk64EraseCmd = 0xd8,
/* write */
.pageProgramCmd = 0x02,
.qpageProgramCmd = 0x32,
.qppAddrMode = SF_CTRL_ADDR_1_LINE,
.ioMode = 0x10,
.clkDelay = 0,
.clkInvert = 0x03,
.resetEnCmd = 0x66,
.resetCmd = 0x99,
.cRExit = 0xff,
.wrEnableWriteRegLen = 0x00,
/* id */
.jedecIdCmd = 0x9f,
.jedecIdCmdDmyClk = 0,
.enter32BitsAddrCmd = 0xb7,
.exit32BitsAddrCmd = 0xe9,
.sectorSize = 4,
.pageSize = 256,
/* read */
.fastReadCmd = 0x0b,
.frDmyClk = 8 / 8,
.qpiFastReadCmd = 0x0b,
.qpiFrDmyClk = 8 / 8,
.fastReadDoCmd = 0x3b,
.frDoDmyClk = 8 / 8,
.fastReadDioCmd = 0xbb,
.frDioDmyClk = 0,
.fastReadQoCmd = 0x6b,
.frQoDmyClk = 8 / 8,
.qpiFastReadQioCmd = 0xeb,
.qpiFrQioDmyClk = 16 / 8,
.qpiPageProgramCmd = 0x02,
.writeVregEnableCmd = 0x50,
/* qpi mode */
.enterQpi = 0x38,
.exitQpi = 0xff,
/* AC */
.timeEsector = 300,
.timeE32k = 1200,
.timeE64k = 1200,
.timePagePgm = 5,
.timeCe = 33 * 1000,
.pdDelay = 20,
.qeData = 0,
};
static bflb_efuse_device_info_type deviceInfo;
@ -47,6 +239,23 @@ static void flash_get_clock_delay(SPI_Flash_Cfg_Type *cfg)
cfg->clkInvert |= ((BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_IO_0_OE_DLY_SEL) & 7) << 5);
}
static void ATTR_TCM_SECTION flash_set_cmds(SPI_Flash_Cfg_Type *p_flash_cfg)
{
SF_Ctrl_Cmds_Cfg cmds_cfg = {
.ackLatency = 1,
.cmdsCoreEn = 1,
.cmdsEn = 1,
.cmdsWrapMode = 1,
.cmdsWrapLen = 9,
};
if ((p_flash_cfg->ioMode & 0x0f) == SF_CTRL_QO_MODE || (p_flash_cfg->ioMode & 0x0f) == SF_CTRL_QIO_MODE) {
cmds_cfg.cmdsWrapMode = 2;
cmds_cfg.cmdsWrapLen = 2;
}
SF_Ctrl_Cmds_Set(&cmds_cfg, 0);
}
static void ATTR_TCM_SECTION flash_set_qspi_enable(SPI_Flash_Cfg_Type *p_flash_cfg)
{
if ((p_flash_cfg->ioMode & 0x0f) == SF_CTRL_QO_MODE || (p_flash_cfg->ioMode & 0x0f) == SF_CTRL_QIO_MODE) {
@ -95,6 +304,7 @@ static int ATTR_TCM_SECTION flash_config_init(SPI_Flash_Cfg_Type *p_flash_cfg, u
// p_flash_cfg->cReadSupport = 0x00;
/* Set flash controler from p_flash_cfg */
flash_set_cmds(p_flash_cfg);
flash_set_qspi_enable(p_flash_cfg);
flash_set_l1c_wrap(p_flash_cfg);
XIP_SFlash_State_Restore(p_flash_cfg, offset, 0, 0);
@ -188,7 +398,6 @@ int ATTR_TCM_SECTION bflb_flash_init(void)
{
int ret = -1;
uint32_t jedec_id = 0;
uintptr_t flag;
bflb_ef_ctrl_get_device_info(&deviceInfo);
@ -204,19 +413,7 @@ int ATTR_TCM_SECTION bflb_flash_init(void)
}
}
flag = bflb_irq_save();
L1C_ICache_Invalid_All();
SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(0, &g_flash_cfg);
L1C_ICache_Invalid_All();
bflb_irq_restore(flag);
if (g_flash_cfg.mid != 0xff) {
g_flash_cfg.ioMode &= 0x0f;
flash_get_clock_delay(&g_flash_cfg);
flash2_init();
return 0;
}
g_flash_cfg.ioMode &= 0x0f;
ret = flash_config_init(&g_flash_cfg, (uint8_t *)&jedec_id);
g_flash_cfg.ioMode &= 0x0f;

1
drivers/soc/bl616/startup/system_bl616.c
View file

@ -105,6 +105,7 @@ void System_Post_Init(void)
/* Bootrom not use dcache,so ignore this flush*/
#ifndef BOOTROM
csi_dcache_clean();
csi_icache_invalid();
#endif
/* global IRQ enable */

1
drivers/soc/bl702/CMakeLists.txt
View file

@ -29,7 +29,6 @@ sdk_library_add_sources(bl702_std/src/bl702_xip_sflash_ext.c)
sdk_library_add_sources(port/bl702_clock.c)
sdk_library_add_sources(port/bl702_flash.c)
sdk_library_add_sources(port/bl702_efuse.c)
sdk_add_include_directories(
bl702_std/include

4
drivers/soc/bl702/bl702_std/include/bl702_ef_cfg.h
View file

@ -58,7 +58,7 @@ typedef struct
uint32_t rsvd_21_0 : 22; /*!< Reserved */
uint32_t sf_swap_cfg : 2; /*!< 0:swap none, 1:swap SF2_CS & SF2_IO2, 2:swap SF2_IO0 & SF2_IO3, 3:swap both */
uint32_t psram_cfg : 2; /*!< 0:no psram, 1:2MB psram, 2:external psram, 3:reserved */
uint32_t flash_cfg : 3; /*!< 0:external flash SF2, 1:0.5MB flash, 2:1MB flash, 3:external flash SF1 */
uint32_t flash_cfg : 3; /*!< 0:external flash SF2, 1:0.5MB flash, 2:1MB flash, 3:external flash SF1, 5:2MB flash */
uint32_t rsvd_29 : 1; /*!< Reserved */
uint32_t pkg_info : 2; /*!< 0:QFN32, 1:QFN40, 2:QFN48, 3:reserved */
} bflb_efuse_device_info_type;
@ -83,7 +83,7 @@ typedef struct
void bflb_efuse_switch_cpu_clock_save(void);
void bflb_efuse_switch_cpu_clock_restore(void);
void bflb_ef_ctrl_get_device_info(bflb_efuse_device_info_type *deviceInfo);
uint32_t bflb_ef_ctrl_get_common_trim_list(const bflb_ef_ctrl_com_trim_cfg **trim_list);
uint32_t bflb_ef_ctrl_get_common_trim_list(const bflb_ef_ctrl_com_trim_cfg_t **trim_list);
/*@} end of group EF_CTRL_Public_Functions */

762
drivers/soc/bl702/bl702_std/include/hardware/ef_data_reg.h Normal file
View file

@ -0,0 +1,762 @@
/**
******************************************************************************
* @file EF_DATA_reg.h
* @version V1.2
* @date 2020-04-30
* @brief This file is the description of.IP register
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __EF_DATA_REG_H__
#define __EF_DATA_REG_H__
#include "bl702.h"
/* 0x0 : ef_cfg_0 */
#define EF_DATA_EF_CFG_0_OFFSET (0x0)
#define EF_DATA_EF_SF_AES_MODE EF_DATA_EF_SF_AES_MODE
#define EF_DATA_EF_SF_AES_MODE_POS (0U)
#define EF_DATA_EF_SF_AES_MODE_LEN (2U)
#define EF_DATA_EF_SF_AES_MODE_MSK (((1U << EF_DATA_EF_SF_AES_MODE_LEN) - 1) << EF_DATA_EF_SF_AES_MODE_POS)
#define EF_DATA_EF_SF_AES_MODE_UMSK (~(((1U << EF_DATA_EF_SF_AES_MODE_LEN) - 1) << EF_DATA_EF_SF_AES_MODE_POS))
#define EF_DATA_EF_SBOOT_SIGN_MODE EF_DATA_EF_SBOOT_SIGN_MODE
#define EF_DATA_EF_SBOOT_SIGN_MODE_POS (2U)
#define EF_DATA_EF_SBOOT_SIGN_MODE_LEN (2U)
#define EF_DATA_EF_SBOOT_SIGN_MODE_MSK (((1U << EF_DATA_EF_SBOOT_SIGN_MODE_LEN) - 1) << EF_DATA_EF_SBOOT_SIGN_MODE_POS)
#define EF_DATA_EF_SBOOT_SIGN_MODE_UMSK (~(((1U << EF_DATA_EF_SBOOT_SIGN_MODE_LEN) - 1) << EF_DATA_EF_SBOOT_SIGN_MODE_POS))
#define EF_DATA_EF_SBOOT_EN EF_DATA_EF_SBOOT_EN
#define EF_DATA_EF_SBOOT_EN_POS (4U)
#define EF_DATA_EF_SBOOT_EN_LEN (2U)
#define EF_DATA_EF_SBOOT_EN_MSK (((1U << EF_DATA_EF_SBOOT_EN_LEN) - 1) << EF_DATA_EF_SBOOT_EN_POS)
#define EF_DATA_EF_SBOOT_EN_UMSK (~(((1U << EF_DATA_EF_SBOOT_EN_LEN) - 1) << EF_DATA_EF_SBOOT_EN_POS))
#define EF_DATA_EF_CPU0_ENC_EN EF_DATA_EF_CPU0_ENC_EN
#define EF_DATA_EF_CPU0_ENC_EN_POS (7U)
#define EF_DATA_EF_CPU0_ENC_EN_LEN (1U)
#define EF_DATA_EF_CPU0_ENC_EN_MSK (((1U << EF_DATA_EF_CPU0_ENC_EN_LEN) - 1) << EF_DATA_EF_CPU0_ENC_EN_POS)
#define EF_DATA_EF_CPU0_ENC_EN_UMSK (~(((1U << EF_DATA_EF_CPU0_ENC_EN_LEN) - 1) << EF_DATA_EF_CPU0_ENC_EN_POS))
#define EF_DATA_EF_BOOT_SEL EF_DATA_EF_BOOT_SEL
#define EF_DATA_EF_BOOT_SEL_POS (8U)
#define EF_DATA_EF_BOOT_SEL_LEN (4U)
#define EF_DATA_EF_BOOT_SEL_MSK (((1U << EF_DATA_EF_BOOT_SEL_LEN) - 1) << EF_DATA_EF_BOOT_SEL_POS)
#define EF_DATA_EF_BOOT_SEL_UMSK (~(((1U << EF_DATA_EF_BOOT_SEL_LEN) - 1) << EF_DATA_EF_BOOT_SEL_POS))
#define EF_DATA_EF_SF_KEY_0_SEL EF_DATA_EF_SF_KEY_0_SEL
#define EF_DATA_EF_SF_KEY_0_SEL_POS (12U)
#define EF_DATA_EF_SF_KEY_0_SEL_LEN (2U)
#define EF_DATA_EF_SF_KEY_0_SEL_MSK (((1U << EF_DATA_EF_SF_KEY_0_SEL_LEN) - 1) << EF_DATA_EF_SF_KEY_0_SEL_POS)
#define EF_DATA_EF_SF_KEY_0_SEL_UMSK (~(((1U << EF_DATA_EF_SF_KEY_0_SEL_LEN) - 1) << EF_DATA_EF_SF_KEY_0_SEL_POS))
#define EF_DATA_EF_0_KEY_ENC_EN EF_DATA_EF_0_KEY_ENC_EN
#define EF_DATA_EF_0_KEY_ENC_EN_POS (17U)
#define EF_DATA_EF_0_KEY_ENC_EN_LEN (1U)
#define EF_DATA_EF_0_KEY_ENC_EN_MSK (((1U << EF_DATA_EF_0_KEY_ENC_EN_LEN) - 1) << EF_DATA_EF_0_KEY_ENC_EN_POS)
#define EF_DATA_EF_0_KEY_ENC_EN_UMSK (~(((1U << EF_DATA_EF_0_KEY_ENC_EN_LEN) - 1) << EF_DATA_EF_0_KEY_ENC_EN_POS))
#define EF_DATA_EF_DBG_JTAG_0_DIS EF_DATA_EF_DBG_JTAG_0_DIS
#define EF_DATA_EF_DBG_JTAG_0_DIS_POS (26U)
#define EF_DATA_EF_DBG_JTAG_0_DIS_LEN (2U)
#define EF_DATA_EF_DBG_JTAG_0_DIS_MSK (((1U << EF_DATA_EF_DBG_JTAG_0_DIS_LEN) - 1) << EF_DATA_EF_DBG_JTAG_0_DIS_POS)
#define EF_DATA_EF_DBG_JTAG_0_DIS_UMSK (~(((1U << EF_DATA_EF_DBG_JTAG_0_DIS_LEN) - 1) << EF_DATA_EF_DBG_JTAG_0_DIS_POS))
#define EF_DATA_EF_DBG_MODE EF_DATA_EF_DBG_MODE
#define EF_DATA_EF_DBG_MODE_POS (28U)
#define EF_DATA_EF_DBG_MODE_LEN (4U)
#define EF_DATA_EF_DBG_MODE_MSK (((1U << EF_DATA_EF_DBG_MODE_LEN) - 1) << EF_DATA_EF_DBG_MODE_POS)
#define EF_DATA_EF_DBG_MODE_UMSK (~(((1U << EF_DATA_EF_DBG_MODE_LEN) - 1) << EF_DATA_EF_DBG_MODE_POS))
/* 0x4 : ef_dbg_pwd_low */
#define EF_DATA_EF_DBG_PWD_LOW_OFFSET (0x4)
#define EF_DATA_EF_DBG_PWD_LOW EF_DATA_EF_DBG_PWD_LOW
#define EF_DATA_EF_DBG_PWD_LOW_POS (0U)
#define EF_DATA_EF_DBG_PWD_LOW_LEN (32U)
#define EF_DATA_EF_DBG_PWD_LOW_MSK (((1U << EF_DATA_EF_DBG_PWD_LOW_LEN) - 1) << EF_DATA_EF_DBG_PWD_LOW_POS)
#define EF_DATA_EF_DBG_PWD_LOW_UMSK (~(((1U << EF_DATA_EF_DBG_PWD_LOW_LEN) - 1) << EF_DATA_EF_DBG_PWD_LOW_POS))
/* 0x8 : ef_dbg_pwd_high */
#define EF_DATA_EF_DBG_PWD_HIGH_OFFSET (0x8)
#define EF_DATA_EF_DBG_PWD_HIGH EF_DATA_EF_DBG_PWD_HIGH
#define EF_DATA_EF_DBG_PWD_HIGH_POS (0U)
#define EF_DATA_EF_DBG_PWD_HIGH_LEN (32U)
#define EF_DATA_EF_DBG_PWD_HIGH_MSK (((1U << EF_DATA_EF_DBG_PWD_HIGH_LEN) - 1) << EF_DATA_EF_DBG_PWD_HIGH_POS)
#define EF_DATA_EF_DBG_PWD_HIGH_UMSK (~(((1U << EF_DATA_EF_DBG_PWD_HIGH_LEN) - 1) << EF_DATA_EF_DBG_PWD_HIGH_POS))
/* 0xC : ef_ana_trim_0 */
#define EF_DATA_EF_ANA_TRIM_0_OFFSET (0xC)
#define EF_DATA_EF_ANA_TRIM_0 EF_DATA_EF_ANA_TRIM_0
#define EF_DATA_EF_ANA_TRIM_0_POS (0U)
#define EF_DATA_EF_ANA_TRIM_0_LEN (32U)
#define EF_DATA_EF_ANA_TRIM_0_MSK (((1U << EF_DATA_EF_ANA_TRIM_0_LEN) - 1) << EF_DATA_EF_ANA_TRIM_0_POS)
#define EF_DATA_EF_ANA_TRIM_0_UMSK (~(((1U << EF_DATA_EF_ANA_TRIM_0_LEN) - 1) << EF_DATA_EF_ANA_TRIM_0_POS))
/* 0x10 : ef_sw_usage_0 */
#define EF_DATA_EF_SW_USAGE_0_OFFSET (0x10)
#define EF_DATA_EF_SW_USAGE_0 EF_DATA_EF_SW_USAGE_0
#define EF_DATA_EF_SW_USAGE_0_POS (0U)
#define EF_DATA_EF_SW_USAGE_0_LEN (32U)
#define EF_DATA_EF_SW_USAGE_0_MSK (((1U << EF_DATA_EF_SW_USAGE_0_LEN) - 1) << EF_DATA_EF_SW_USAGE_0_POS)
#define EF_DATA_EF_SW_USAGE_0_UMSK (~(((1U << EF_DATA_EF_SW_USAGE_0_LEN) - 1) << EF_DATA_EF_SW_USAGE_0_POS))
/* 0x14 : ef_wifi_mac_low */
#define EF_DATA_EF_WIFI_MAC_LOW_OFFSET (0x14)
#define EF_DATA_EF_WIFI_MAC_LOW EF_DATA_EF_WIFI_MAC_LOW
#define EF_DATA_EF_WIFI_MAC_LOW_POS (0U)
#define EF_DATA_EF_WIFI_MAC_LOW_LEN (32U)
#define EF_DATA_EF_WIFI_MAC_LOW_MSK (((1U << EF_DATA_EF_WIFI_MAC_LOW_LEN) - 1) << EF_DATA_EF_WIFI_MAC_LOW_POS)
#define EF_DATA_EF_WIFI_MAC_LOW_UMSK (~(((1U << EF_DATA_EF_WIFI_MAC_LOW_LEN) - 1) << EF_DATA_EF_WIFI_MAC_LOW_POS))
/* 0x18 : ef_wifi_mac_high */
#define EF_DATA_EF_WIFI_MAC_HIGH_OFFSET (0x18)
#define EF_DATA_EF_WIFI_MAC_HIGH EF_DATA_EF_WIFI_MAC_HIGH
#define EF_DATA_EF_WIFI_MAC_HIGH_POS (0U)
#define EF_DATA_EF_WIFI_MAC_HIGH_LEN (32U)
#define EF_DATA_EF_WIFI_MAC_HIGH_MSK (((1U << EF_DATA_EF_WIFI_MAC_HIGH_LEN) - 1) << EF_DATA_EF_WIFI_MAC_HIGH_POS)
#define EF_DATA_EF_WIFI_MAC_HIGH_UMSK (~(((1U << EF_DATA_EF_WIFI_MAC_HIGH_LEN) - 1) << EF_DATA_EF_WIFI_MAC_HIGH_POS))
/* 0x1C : ef_key_slot_0_w0 */
#define EF_DATA_EF_KEY_SLOT_0_W0_OFFSET (0x1C)
#define EF_DATA_EF_KEY_SLOT_0_W0 EF_DATA_EF_KEY_SLOT_0_W0
#define EF_DATA_EF_KEY_SLOT_0_W0_POS (0U)
#define EF_DATA_EF_KEY_SLOT_0_W0_LEN (32U)
#define EF_DATA_EF_KEY_SLOT_0_W0_MSK (((1U << EF_DATA_EF_KEY_SLOT_0_W0_LEN) - 1) << EF_DATA_EF_KEY_SLOT_0_W0_POS)
#define EF_DATA_EF_KEY_SLOT_0_W0_UMSK (~(((1U << EF_DATA_EF_KEY_SLOT_0_W0_LEN) - 1) << EF_DATA_EF_KEY_SLOT_0_W0_POS))
/* 0x20 : ef_key_slot_0_w1 */
#define EF_DATA_EF_KEY_SLOT_0_W1_OFFSET (0x20)
#define EF_DATA_EF_KEY_SLOT_0_W1 EF_DATA_EF_KEY_SLOT_0_W1
#define EF_DATA_EF_KEY_SLOT_0_W1_POS (0U)
#define EF_DATA_EF_KEY_SLOT_0_W1_LEN (32U)
#define EF_DATA_EF_KEY_SLOT_0_W1_MSK (((1U << EF_DATA_EF_KEY_SLOT_0_W1_LEN) - 1) << EF_DATA_EF_KEY_SLOT_0_W1_POS)
#define EF_DATA_EF_KEY_SLOT_0_W1_UMSK (~(((1U << EF_DATA_EF_KEY_SLOT_0_W1_LEN) - 1) << EF_DATA_EF_KEY_SLOT_0_W1_POS))
/* 0x24 : ef_key_slot_0_w2 */
#define EF_DATA_EF_KEY_SLOT_0_W2_OFFSET (0x24)
#define EF_DATA_EF_KEY_SLOT_0_W2 EF_DATA_EF_KEY_SLOT_0_W2
#define EF_DATA_EF_KEY_SLOT_0_W2_POS (0U)
#define EF_DATA_EF_KEY_SLOT_0_W2_LEN (32U)
#define EF_DATA_EF_KEY_SLOT_0_W2_MSK (((1U << EF_DATA_EF_KEY_SLOT_0_W2_LEN) - 1) << EF_DATA_EF_KEY_SLOT_0_W2_POS)
#define EF_DATA_EF_KEY_SLOT_0_W2_UMSK (~(((1U << EF_DATA_EF_KEY_SLOT_0_W2_LEN) - 1) << EF_DATA_EF_KEY_SLOT_0_W2_POS))
/* 0x28 : ef_key_slot_0_w3 */
#define EF_DATA_EF_KEY_SLOT_0_W3_OFFSET (0x28)
#define EF_DATA_EF_KEY_SLOT_0_W3 EF_DATA_EF_KEY_SLOT_0_W3
#define EF_DATA_EF_KEY_SLOT_0_W3_POS (0U)
#define EF_DATA_EF_KEY_SLOT_0_W3_LEN (32U)
#define EF_DATA_EF_KEY_SLOT_0_W3_MSK (((1U << EF_DATA_EF_KEY_SLOT_0_W3_LEN) - 1) << EF_DATA_EF_KEY_SLOT_0_W3_POS)
#define EF_DATA_EF_KEY_SLOT_0_W3_UMSK (~(((1U << EF_DATA_EF_KEY_SLOT_0_W3_LEN) - 1) << EF_DATA_EF_KEY_SLOT_0_W3_POS))
/* 0x2C : ef_key_slot_1_w0 */
#define EF_DATA_EF_KEY_SLOT_1_W0_OFFSET (0x2C)
#define EF_DATA_EF_KEY_SLOT_1_W0 EF_DATA_EF_KEY_SLOT_1_W0
#define EF_DATA_EF_KEY_SLOT_1_W0_POS (0U)
#define EF_DATA_EF_KEY_SLOT_1_W0_LEN (32U)
#define EF_DATA_EF_KEY_SLOT_1_W0_MSK (((1U << EF_DATA_EF_KEY_SLOT_1_W0_LEN) - 1) << EF_DATA_EF_KEY_SLOT_1_W0_POS)
#define EF_DATA_EF_KEY_SLOT_1_W0_UMSK (~(((1U << EF_DATA_EF_KEY_SLOT_1_W0_LEN) - 1) << EF_DATA_EF_KEY_SLOT_1_W0_POS))
/* 0x30 : ef_key_slot_1_w1 */
#define EF_DATA_EF_KEY_SLOT_1_W1_OFFSET (0x30)
#define EF_DATA_EF_KEY_SLOT_1_W1 EF_DATA_EF_KEY_SLOT_1_W1
#define EF_DATA_EF_KEY_SLOT_1_W1_POS (0U)
#define EF_DATA_EF_KEY_SLOT_1_W1_LEN (32U)
#define EF_DATA_EF_KEY_SLOT_1_W1_MSK (((1U << EF_DATA_EF_KEY_SLOT_1_W1_LEN) - 1) << EF_DATA_EF_KEY_SLOT_1_W1_POS)
#define EF_DATA_EF_KEY_SLOT_1_W1_UMSK (~(((1U << EF_DATA_EF_KEY_SLOT_1_W1_LEN) - 1) << EF_DATA_EF_KEY_SLOT_1_W1_POS))
/* 0x34 : ef_key_slot_1_w2 */
#define EF_DATA_EF_KEY_SLOT_1_W2_OFFSET (0x34)
#define EF_DATA_EF_KEY_SLOT_1_W2 EF_DATA_EF_KEY_SLOT_1_W2
#define EF_DATA_EF_KEY_SLOT_1_W2_POS (0U)
#define EF_DATA_EF_KEY_SLOT_1_W2_LEN (32U)
#define EF_DATA_EF_KEY_SLOT_1_W2_MSK (((1U << EF_DATA_EF_KEY_SLOT_1_W2_LEN) - 1) << EF_DATA_EF_KEY_SLOT_1_W2_POS)
#define EF_DATA_EF_KEY_SLOT_1_W2_UMSK (~(((1U << EF_DATA_EF_KEY_SLOT_1_W2_LEN) - 1) << EF_DATA_EF_KEY_SLOT_1_W2_POS))
/* 0x38 : ef_key_slot_1_w3 */
#define EF_DATA_EF_KEY_SLOT_1_W3_OFFSET (0x38)
#define EF_DATA_EF_KEY_SLOT_1_W3 EF_DATA_EF_KEY_SLOT_1_W3
#define EF_DATA_EF_KEY_SLOT_1_W3_POS (0U)
#define EF_DATA_EF_KEY_SLOT_1_W3_LEN (32U)
#define EF_DATA_EF_KEY_SLOT_1_W3_MSK (((1U << EF_DATA_EF_KEY_SLOT_1_W3_LEN) - 1) << EF_DATA_EF_KEY_SLOT_1_W3_POS)
#define EF_DATA_EF_KEY_SLOT_1_W3_UMSK (~(((1U << EF_DATA_EF_KEY_SLOT_1_W3_LEN) - 1) << EF_DATA_EF_KEY_SLOT_1_W3_POS))
/* 0x3C : ef_key_slot_2_w0 */
#define EF_DATA_EF_KEY_SLOT_2_W0_OFFSET (0x3C)
#define EF_DATA_EF_KEY_SLOT_2_W0 EF_DATA_EF_KEY_SLOT_2_W0
#define EF_DATA_EF_KEY_SLOT_2_W0_POS (0U)
#define EF_DATA_EF_KEY_SLOT_2_W0_LEN (32U)
#define EF_DATA_EF_KEY_SLOT_2_W0_MSK (((1U << EF_DATA_EF_KEY_SLOT_2_W0_LEN) - 1) << EF_DATA_EF_KEY_SLOT_2_W0_POS)
#define EF_DATA_EF_KEY_SLOT_2_W0_UMSK (~(((1U << EF_DATA_EF_KEY_SLOT_2_W0_LEN) - 1) << EF_DATA_EF_KEY_SLOT_2_W0_POS))
/* 0x40 : ef_key_slot_2_w1 */
#define EF_DATA_EF_KEY_SLOT_2_W1_OFFSET (0x40)
#define EF_DATA_EF_KEY_SLOT_2_W1 EF_DATA_EF_KEY_SLOT_2_W1
#define EF_DATA_EF_KEY_SLOT_2_W1_POS (0U)
#define EF_DATA_EF_KEY_SLOT_2_W1_LEN (32U)
#define EF_DATA_EF_KEY_SLOT_2_W1_MSK (((1U << EF_DATA_EF_KEY_SLOT_2_W1_LEN) - 1) << EF_DATA_EF_KEY_SLOT_2_W1_POS)
#define EF_DATA_EF_KEY_SLOT_2_W1_UMSK (~(((1U << EF_DATA_EF_KEY_SLOT_2_W1_LEN) - 1) << EF_DATA_EF_KEY_SLOT_2_W1_POS))
/* 0x44 : ef_key_slot_2_w2 */
#define EF_DATA_EF_KEY_SLOT_2_W2_OFFSET (0x44)
#define EF_DATA_EF_KEY_SLOT_2_W2 EF_DATA_EF_KEY_SLOT_2_W2
#define EF_DATA_EF_KEY_SLOT_2_W2_POS (0U)
#define EF_DATA_EF_KEY_SLOT_2_W2_LEN (32U)
#define EF_DATA_EF_KEY_SLOT_2_W2_MSK (((1U << EF_DATA_EF_KEY_SLOT_2_W2_LEN) - 1) << EF_DATA_EF_KEY_SLOT_2_W2_POS)
#define EF_DATA_EF_KEY_SLOT_2_W2_UMSK (~(((1U << EF_DATA_EF_KEY_SLOT_2_W2_LEN) - 1) << EF_DATA_EF_KEY_SLOT_2_W2_POS))
/* 0x48 : ef_key_slot_2_w3 */
#define EF_DATA_EF_KEY_SLOT_2_W3_OFFSET (0x48)
#define EF_DATA_EF_KEY_SLOT_2_W3 EF_DATA_EF_KEY_SLOT_2_W3
#define EF_DATA_EF_KEY_SLOT_2_W3_POS (0U)
#define EF_DATA_EF_KEY_SLOT_2_W3_LEN (32U)
#define EF_DATA_EF_KEY_SLOT_2_W3_MSK (((1U << EF_DATA_EF_KEY_SLOT_2_W3_LEN) - 1) << EF_DATA_EF_KEY_SLOT_2_W3_POS)
#define EF_DATA_EF_KEY_SLOT_2_W3_UMSK (~(((1U << EF_DATA_EF_KEY_SLOT_2_W3_LEN) - 1) << EF_DATA_EF_KEY_SLOT_2_W3_POS))
/* 0x4C : ef_key_slot_3_w0 */
#define EF_DATA_EF_KEY_SLOT_3_W0_OFFSET (0x4C)
#define EF_DATA_EF_KEY_SLOT_3_W0 EF_DATA_EF_KEY_SLOT_3_W0
#define EF_DATA_EF_KEY_SLOT_3_W0_POS (0U)
#define EF_DATA_EF_KEY_SLOT_3_W0_LEN (32U)
#define EF_DATA_EF_KEY_SLOT_3_W0_MSK (((1U << EF_DATA_EF_KEY_SLOT_3_W0_LEN) - 1) << EF_DATA_EF_KEY_SLOT_3_W0_POS)
#define EF_DATA_EF_KEY_SLOT_3_W0_UMSK (~(((1U << EF_DATA_EF_KEY_SLOT_3_W0_LEN) - 1) << EF_DATA_EF_KEY_SLOT_3_W0_POS))
/* 0x50 : ef_key_slot_3_w1 */
#define EF_DATA_EF_KEY_SLOT_3_W1_OFFSET (0x50)
#define EF_DATA_EF_KEY_SLOT_3_W1 EF_DATA_EF_KEY_SLOT_3_W1
#define EF_DATA_EF_KEY_SLOT_3_W1_POS (0U)
#define EF_DATA_EF_KEY_SLOT_3_W1_LEN (32U)
#define EF_DATA_EF_KEY_SLOT_3_W1_MSK (((1U << EF_DATA_EF_KEY_SLOT_3_W1_LEN) - 1) << EF_DATA_EF_KEY_SLOT_3_W1_POS)
#define EF_DATA_EF_KEY_SLOT_3_W1_UMSK (~(((1U << EF_DATA_EF_KEY_SLOT_3_W1_LEN) - 1) << EF_DATA_EF_KEY_SLOT_3_W1_POS))
/* 0x54 : ef_key_slot_3_w2 */
#define EF_DATA_EF_KEY_SLOT_3_W2_OFFSET (0x54)
#define EF_DATA_EF_KEY_SLOT_3_W2 EF_DATA_EF_KEY_SLOT_3_W2
#define EF_DATA_EF_KEY_SLOT_3_W2_POS (0U)
#define EF_DATA_EF_KEY_SLOT_3_W2_LEN (32U)
#define EF_DATA_EF_KEY_SLOT_3_W2_MSK (((1U << EF_DATA_EF_KEY_SLOT_3_W2_LEN) - 1) << EF_DATA_EF_KEY_SLOT_3_W2_POS)
#define EF_DATA_EF_KEY_SLOT_3_W2_UMSK (~(((1U << EF_DATA_EF_KEY_SLOT_3_W2_LEN) - 1) << EF_DATA_EF_KEY_SLOT_3_W2_POS))
/* 0x58 : ef_key_slot_3_w3 */
#define EF_DATA_EF_KEY_SLOT_3_W3_OFFSET (0x58)
#define EF_DATA_EF_KEY_SLOT_3_W3 EF_DATA_EF_KEY_SLOT_3_W3
#define EF_DATA_EF_KEY_SLOT_3_W3_POS (0U)
#define EF_DATA_EF_KEY_SLOT_3_W3_LEN (32U)
#define EF_DATA_EF_KEY_SLOT_3_W3_MSK (((1U << EF_DATA_EF_KEY_SLOT_3_W3_LEN) - 1) << EF_DATA_EF_KEY_SLOT_3_W3_POS)
#define EF_DATA_EF_KEY_SLOT_3_W3_UMSK (~(((1U << EF_DATA_EF_KEY_SLOT_3_W3_LEN) - 1) << EF_DATA_EF_KEY_SLOT_3_W3_POS))
/* 0x5C : ef_key_slot_4_w0 */
#define EF_DATA_EF_KEY_SLOT_4_W0_OFFSET (0x5C)
#define EF_DATA_EF_KEY_SLOT_4_W0 EF_DATA_EF_KEY_SLOT_4_W0
#define EF_DATA_EF_KEY_SLOT_4_W0_POS (0U)
#define EF_DATA_EF_KEY_SLOT_4_W0_LEN (32U)
#define EF_DATA_EF_KEY_SLOT_4_W0_MSK (((1U << EF_DATA_EF_KEY_SLOT_4_W0_LEN) - 1) << EF_DATA_EF_KEY_SLOT_4_W0_POS)
#define EF_DATA_EF_KEY_SLOT_4_W0_UMSK (~(((1U << EF_DATA_EF_KEY_SLOT_4_W0_LEN) - 1) << EF_DATA_EF_KEY_SLOT_4_W0_POS))
/* 0x60 : ef_key_slot_4_w1 */
#define EF_DATA_EF_KEY_SLOT_4_W1_OFFSET (0x60)
#define EF_DATA_EF_KEY_SLOT_4_W1 EF_DATA_EF_KEY_SLOT_4_W1
#define EF_DATA_EF_KEY_SLOT_4_W1_POS (0U)
#define EF_DATA_EF_KEY_SLOT_4_W1_LEN (32U)
#define EF_DATA_EF_KEY_SLOT_4_W1_MSK (((1U << EF_DATA_EF_KEY_SLOT_4_W1_LEN) - 1) << EF_DATA_EF_KEY_SLOT_4_W1_POS)
#define EF_DATA_EF_KEY_SLOT_4_W1_UMSK (~(((1U << EF_DATA_EF_KEY_SLOT_4_W1_LEN) - 1) << EF_DATA_EF_KEY_SLOT_4_W1_POS))
/* 0x64 : ef_key_slot_4_w2 */
#define EF_DATA_EF_KEY_SLOT_4_W2_OFFSET (0x64)
#define EF_DATA_EF_KEY_SLOT_4_W2 EF_DATA_EF_KEY_SLOT_4_W2
#define EF_DATA_EF_KEY_SLOT_4_W2_POS (0U)
#define EF_DATA_EF_KEY_SLOT_4_W2_LEN (32U)
#define EF_DATA_EF_KEY_SLOT_4_W2_MSK (((1U << EF_DATA_EF_KEY_SLOT_4_W2_LEN) - 1) << EF_DATA_EF_KEY_SLOT_4_W2_POS)
#define EF_DATA_EF_KEY_SLOT_4_W2_UMSK (~(((1U << EF_DATA_EF_KEY_SLOT_4_W2_LEN) - 1) << EF_DATA_EF_KEY_SLOT_4_W2_POS))
/* 0x68 : ef_key_slot_4_w3 */
#define EF_DATA_EF_KEY_SLOT_4_W3_OFFSET (0x68)
#define EF_DATA_EF_KEY_SLOT_4_W3 EF_DATA_EF_KEY_SLOT_4_W3
#define EF_DATA_EF_KEY_SLOT_4_W3_POS (0U)
#define EF_DATA_EF_KEY_SLOT_4_W3_LEN (32U)
#define EF_DATA_EF_KEY_SLOT_4_W3_MSK (((1U << EF_DATA_EF_KEY_SLOT_4_W3_LEN) - 1) << EF_DATA_EF_KEY_SLOT_4_W3_POS)
#define EF_DATA_EF_KEY_SLOT_4_W3_UMSK (~(((1U << EF_DATA_EF_KEY_SLOT_4_W3_LEN) - 1) << EF_DATA_EF_KEY_SLOT_4_W3_POS))
/* 0x6C : ef_key_slot_5_w0 */
#define EF_DATA_EF_KEY_SLOT_5_W0_OFFSET (0x6C)
#define EF_DATA_EF_KEY_SLOT_5_W0 EF_DATA_EF_KEY_SLOT_5_W0
#define EF_DATA_EF_KEY_SLOT_5_W0_POS (0U)
#define EF_DATA_EF_KEY_SLOT_5_W0_LEN (32U)
#define EF_DATA_EF_KEY_SLOT_5_W0_MSK (((1U << EF_DATA_EF_KEY_SLOT_5_W0_LEN) - 1) << EF_DATA_EF_KEY_SLOT_5_W0_POS)
#define EF_DATA_EF_KEY_SLOT_5_W0_UMSK (~(((1U << EF_DATA_EF_KEY_SLOT_5_W0_LEN) - 1) << EF_DATA_EF_KEY_SLOT_5_W0_POS))
/* 0x70 : ef_key_slot_5_w1 */
#define EF_DATA_EF_KEY_SLOT_5_W1_OFFSET (0x70)
#define EF_DATA_EF_KEY_SLOT_5_W1 EF_DATA_EF_KEY_SLOT_5_W1
#define EF_DATA_EF_KEY_SLOT_5_W1_POS (0U)
#define EF_DATA_EF_KEY_SLOT_5_W1_LEN (32U)
#define EF_DATA_EF_KEY_SLOT_5_W1_MSK (((1U << EF_DATA_EF_KEY_SLOT_5_W1_LEN) - 1) << EF_DATA_EF_KEY_SLOT_5_W1_POS)
#define EF_DATA_EF_KEY_SLOT_5_W1_UMSK (~(((1U << EF_DATA_EF_KEY_SLOT_5_W1_LEN) - 1) << EF_DATA_EF_KEY_SLOT_5_W1_POS))
/* 0x74 : ef_key_slot_5_w2 */
#define EF_DATA_EF_KEY_SLOT_5_W2_OFFSET (0x74)
#define EF_DATA_EF_KEY_SLOT_5_W2 EF_DATA_EF_KEY_SLOT_5_W2
#define EF_DATA_EF_KEY_SLOT_5_W2_POS (0U)
#define EF_DATA_EF_KEY_SLOT_5_W2_LEN (32U)
#define EF_DATA_EF_KEY_SLOT_5_W2_MSK (((1U << EF_DATA_EF_KEY_SLOT_5_W2_LEN) - 1) << EF_DATA_EF_KEY_SLOT_5_W2_POS)
#define EF_DATA_EF_KEY_SLOT_5_W2_UMSK (~(((1U << EF_DATA_EF_KEY_SLOT_5_W2_LEN) - 1) << EF_DATA_EF_KEY_SLOT_5_W2_POS))
/* 0x78 : ef_key_slot_5_w3 */
#define EF_DATA_EF_KEY_SLOT_5_W3_OFFSET (0x78)
#define EF_DATA_EF_KEY_SLOT_5_W3 EF_DATA_EF_KEY_SLOT_5_W3
#define EF_DATA_EF_KEY_SLOT_5_W3_POS (0U)
#define EF_DATA_EF_KEY_SLOT_5_W3_LEN (32U)
#define EF_DATA_EF_KEY_SLOT_5_W3_MSK (((1U << EF_DATA_EF_KEY_SLOT_5_W3_LEN) - 1) << EF_DATA_EF_KEY_SLOT_5_W3_POS)
#define EF_DATA_EF_KEY_SLOT_5_W3_UMSK (~(((1U << EF_DATA_EF_KEY_SLOT_5_W3_LEN) - 1) << EF_DATA_EF_KEY_SLOT_5_W3_POS))
/* 0x7C : EF_DATA_lock */
#define EF_DATA_LOCK_OFFSET (0x7C)
#define EF_DATA_EF_ANA_TRIM_1 EF_DATA_EF_ANA_TRIM_1
#define EF_DATA_EF_ANA_TRIM_1_POS (0U)
#define EF_DATA_EF_ANA_TRIM_1_LEN (13U)
#define EF_DATA_EF_ANA_TRIM_1_MSK (((1U << EF_DATA_EF_ANA_TRIM_1_LEN) - 1) << EF_DATA_EF_ANA_TRIM_1_POS)
#define EF_DATA_EF_ANA_TRIM_1_UMSK (~(((1U << EF_DATA_EF_ANA_TRIM_1_LEN) - 1) << EF_DATA_EF_ANA_TRIM_1_POS))
#define EF_DATA_WR_LOCK_KEY_SLOT_4_L EF_DATA_WR_LOCK_KEY_SLOT_4_L
#define EF_DATA_WR_LOCK_KEY_SLOT_4_L_POS (13U)
#define EF_DATA_WR_LOCK_KEY_SLOT_4_L_LEN (1U)
#define EF_DATA_WR_LOCK_KEY_SLOT_4_L_MSK (((1U << EF_DATA_WR_LOCK_KEY_SLOT_4_L_LEN) - 1) << EF_DATA_WR_LOCK_KEY_SLOT_4_L_POS)
#define EF_DATA_WR_LOCK_KEY_SLOT_4_L_UMSK (~(((1U << EF_DATA_WR_LOCK_KEY_SLOT_4_L_LEN) - 1) << EF_DATA_WR_LOCK_KEY_SLOT_4_L_POS))
#define EF_DATA_WR_LOCK_KEY_SLOT_5_L EF_DATA_WR_LOCK_KEY_SLOT_5_L
#define EF_DATA_WR_LOCK_KEY_SLOT_5_L_POS (14U)
#define EF_DATA_WR_LOCK_KEY_SLOT_5_L_LEN (1U)
#define EF_DATA_WR_LOCK_KEY_SLOT_5_L_MSK (((1U << EF_DATA_WR_LOCK_KEY_SLOT_5_L_LEN) - 1) << EF_DATA_WR_LOCK_KEY_SLOT_5_L_POS)
#define EF_DATA_WR_LOCK_KEY_SLOT_5_L_UMSK (~(((1U << EF_DATA_WR_LOCK_KEY_SLOT_5_L_LEN) - 1) << EF_DATA_WR_LOCK_KEY_SLOT_5_L_POS))
#define EF_DATA_WR_LOCK_BOOT_MODE EF_DATA_WR_LOCK_BOOT_MODE
#define EF_DATA_WR_LOCK_BOOT_MODE_POS (15U)
#define EF_DATA_WR_LOCK_BOOT_MODE_LEN (1U)
#define EF_DATA_WR_LOCK_BOOT_MODE_MSK (((1U << EF_DATA_WR_LOCK_BOOT_MODE_LEN) - 1) << EF_DATA_WR_LOCK_BOOT_MODE_POS)
#define EF_DATA_WR_LOCK_BOOT_MODE_UMSK (~(((1U << EF_DATA_WR_LOCK_BOOT_MODE_LEN) - 1) << EF_DATA_WR_LOCK_BOOT_MODE_POS))
#define EF_DATA_WR_LOCK_DBG_PWD EF_DATA_WR_LOCK_DBG_PWD
#define EF_DATA_WR_LOCK_DBG_PWD_POS (16U)
#define EF_DATA_WR_LOCK_DBG_PWD_LEN (1U)
#define EF_DATA_WR_LOCK_DBG_PWD_MSK (((1U << EF_DATA_WR_LOCK_DBG_PWD_LEN) - 1) << EF_DATA_WR_LOCK_DBG_PWD_POS)
#define EF_DATA_WR_LOCK_DBG_PWD_UMSK (~(((1U << EF_DATA_WR_LOCK_DBG_PWD_LEN) - 1) << EF_DATA_WR_LOCK_DBG_PWD_POS))
#define EF_DATA_WR_LOCK_SW_USAGE_0 EF_DATA_WR_LOCK_SW_USAGE_0
#define EF_DATA_WR_LOCK_SW_USAGE_0_POS (17U)
#define EF_DATA_WR_LOCK_SW_USAGE_0_LEN (1U)
#define EF_DATA_WR_LOCK_SW_USAGE_0_MSK (((1U << EF_DATA_WR_LOCK_SW_USAGE_0_LEN) - 1) << EF_DATA_WR_LOCK_SW_USAGE_0_POS)
#define EF_DATA_WR_LOCK_SW_USAGE_0_UMSK (~(((1U << EF_DATA_WR_LOCK_SW_USAGE_0_LEN) - 1) << EF_DATA_WR_LOCK_SW_USAGE_0_POS))
#define EF_DATA_WR_LOCK_WIFI_MAC EF_DATA_WR_LOCK_WIFI_MAC
#define EF_DATA_WR_LOCK_WIFI_MAC_POS (18U)
#define EF_DATA_WR_LOCK_WIFI_MAC_LEN (1U)
#define EF_DATA_WR_LOCK_WIFI_MAC_MSK (((1U << EF_DATA_WR_LOCK_WIFI_MAC_LEN) - 1) << EF_DATA_WR_LOCK_WIFI_MAC_POS)
#define EF_DATA_WR_LOCK_WIFI_MAC_UMSK (~(((1U << EF_DATA_WR_LOCK_WIFI_MAC_LEN) - 1) << EF_DATA_WR_LOCK_WIFI_MAC_POS))
#define EF_DATA_WR_LOCK_KEY_SLOT_0 EF_DATA_WR_LOCK_KEY_SLOT_0
#define EF_DATA_WR_LOCK_KEY_SLOT_0_POS (19U)
#define EF_DATA_WR_LOCK_KEY_SLOT_0_LEN (1U)
#define EF_DATA_WR_LOCK_KEY_SLOT_0_MSK (((1U << EF_DATA_WR_LOCK_KEY_SLOT_0_LEN) - 1) << EF_DATA_WR_LOCK_KEY_SLOT_0_POS)
#define EF_DATA_WR_LOCK_KEY_SLOT_0_UMSK (~(((1U << EF_DATA_WR_LOCK_KEY_SLOT_0_LEN) - 1) << EF_DATA_WR_LOCK_KEY_SLOT_0_POS))
#define EF_DATA_WR_LOCK_KEY_SLOT_1 EF_DATA_WR_LOCK_KEY_SLOT_1
#define EF_DATA_WR_LOCK_KEY_SLOT_1_POS (20U)
#define EF_DATA_WR_LOCK_KEY_SLOT_1_LEN (1U)
#define EF_DATA_WR_LOCK_KEY_SLOT_1_MSK (((1U << EF_DATA_WR_LOCK_KEY_SLOT_1_LEN) - 1) << EF_DATA_WR_LOCK_KEY_SLOT_1_POS)
#define EF_DATA_WR_LOCK_KEY_SLOT_1_UMSK (~(((1U << EF_DATA_WR_LOCK_KEY_SLOT_1_LEN) - 1) << EF_DATA_WR_LOCK_KEY_SLOT_1_POS))
#define EF_DATA_WR_LOCK_KEY_SLOT_2 EF_DATA_WR_LOCK_KEY_SLOT_2
#define EF_DATA_WR_LOCK_KEY_SLOT_2_POS (21U)
#define EF_DATA_WR_LOCK_KEY_SLOT_2_LEN (1U)
#define EF_DATA_WR_LOCK_KEY_SLOT_2_MSK (((1U << EF_DATA_WR_LOCK_KEY_SLOT_2_LEN) - 1) << EF_DATA_WR_LOCK_KEY_SLOT_2_POS)
#define EF_DATA_WR_LOCK_KEY_SLOT_2_UMSK (~(((1U << EF_DATA_WR_LOCK_KEY_SLOT_2_LEN) - 1) << EF_DATA_WR_LOCK_KEY_SLOT_2_POS))
#define EF_DATA_WR_LOCK_KEY_SLOT_3 EF_DATA_WR_LOCK_KEY_SLOT_3
#define EF_DATA_WR_LOCK_KEY_SLOT_3_POS (22U)
#define EF_DATA_WR_LOCK_KEY_SLOT_3_LEN (1U)
#define EF_DATA_WR_LOCK_KEY_SLOT_3_MSK (((1U << EF_DATA_WR_LOCK_KEY_SLOT_3_LEN) - 1) << EF_DATA_WR_LOCK_KEY_SLOT_3_POS)
#define EF_DATA_WR_LOCK_KEY_SLOT_3_UMSK (~(((1U << EF_DATA_WR_LOCK_KEY_SLOT_3_LEN) - 1) << EF_DATA_WR_LOCK_KEY_SLOT_3_POS))
#define EF_DATA_WR_LOCK_KEY_SLOT_4_H EF_DATA_WR_LOCK_KEY_SLOT_4_H
#define EF_DATA_WR_LOCK_KEY_SLOT_4_H_POS (23U)
#define EF_DATA_WR_LOCK_KEY_SLOT_4_H_LEN (1U)
#define EF_DATA_WR_LOCK_KEY_SLOT_4_H_MSK (((1U << EF_DATA_WR_LOCK_KEY_SLOT_4_H_LEN) - 1) << EF_DATA_WR_LOCK_KEY_SLOT_4_H_POS)
#define EF_DATA_WR_LOCK_KEY_SLOT_4_H_UMSK (~(((1U << EF_DATA_WR_LOCK_KEY_SLOT_4_H_LEN) - 1) << EF_DATA_WR_LOCK_KEY_SLOT_4_H_POS))
#define EF_DATA_WR_LOCK_KEY_SLOT_5_H EF_DATA_WR_LOCK_KEY_SLOT_5_H
#define EF_DATA_WR_LOCK_KEY_SLOT_5_H_POS (24U)
#define EF_DATA_WR_LOCK_KEY_SLOT_5_H_LEN (1U)
#define EF_DATA_WR_LOCK_KEY_SLOT_5_H_MSK (((1U << EF_DATA_WR_LOCK_KEY_SLOT_5_H_LEN) - 1) << EF_DATA_WR_LOCK_KEY_SLOT_5_H_POS)
#define EF_DATA_WR_LOCK_KEY_SLOT_5_H_UMSK (~(((1U << EF_DATA_WR_LOCK_KEY_SLOT_5_H_LEN) - 1) << EF_DATA_WR_LOCK_KEY_SLOT_5_H_POS))
#define EF_DATA_RD_LOCK_DBG_PWD EF_DATA_RD_LOCK_DBG_PWD
#define EF_DATA_RD_LOCK_DBG_PWD_POS (25U)
#define EF_DATA_RD_LOCK_DBG_PWD_LEN (1U)
#define EF_DATA_RD_LOCK_DBG_PWD_MSK (((1U << EF_DATA_RD_LOCK_DBG_PWD_LEN) - 1) << EF_DATA_RD_LOCK_DBG_PWD_POS)
#define EF_DATA_RD_LOCK_DBG_PWD_UMSK (~(((1U << EF_DATA_RD_LOCK_DBG_PWD_LEN) - 1) << EF_DATA_RD_LOCK_DBG_PWD_POS))
#define EF_DATA_RD_LOCK_KEY_SLOT_0 EF_DATA_RD_LOCK_KEY_SLOT_0
#define EF_DATA_RD_LOCK_KEY_SLOT_0_POS (26U)
#define EF_DATA_RD_LOCK_KEY_SLOT_0_LEN (1U)
#define EF_DATA_RD_LOCK_KEY_SLOT_0_MSK (((1U << EF_DATA_RD_LOCK_KEY_SLOT_0_LEN) - 1) << EF_DATA_RD_LOCK_KEY_SLOT_0_POS)
#define EF_DATA_RD_LOCK_KEY_SLOT_0_UMSK (~(((1U << EF_DATA_RD_LOCK_KEY_SLOT_0_LEN) - 1) << EF_DATA_RD_LOCK_KEY_SLOT_0_POS))
#define EF_DATA_RD_LOCK_KEY_SLOT_1 EF_DATA_RD_LOCK_KEY_SLOT_1
#define EF_DATA_RD_LOCK_KEY_SLOT_1_POS (27U)
#define EF_DATA_RD_LOCK_KEY_SLOT_1_LEN (1U)
#define EF_DATA_RD_LOCK_KEY_SLOT_1_MSK (((1U << EF_DATA_RD_LOCK_KEY_SLOT_1_LEN) - 1) << EF_DATA_RD_LOCK_KEY_SLOT_1_POS)
#define EF_DATA_RD_LOCK_KEY_SLOT_1_UMSK (~(((1U << EF_DATA_RD_LOCK_KEY_SLOT_1_LEN) - 1) << EF_DATA_RD_LOCK_KEY_SLOT_1_POS))
#define EF_DATA_RD_LOCK_KEY_SLOT_2 EF_DATA_RD_LOCK_KEY_SLOT_2
#define EF_DATA_RD_LOCK_KEY_SLOT_2_POS (28U)
#define EF_DATA_RD_LOCK_KEY_SLOT_2_LEN (1U)
#define EF_DATA_RD_LOCK_KEY_SLOT_2_MSK (((1U << EF_DATA_RD_LOCK_KEY_SLOT_2_LEN) - 1) << EF_DATA_RD_LOCK_KEY_SLOT_2_POS)
#define EF_DATA_RD_LOCK_KEY_SLOT_2_UMSK (~(((1U << EF_DATA_RD_LOCK_KEY_SLOT_2_LEN) - 1) << EF_DATA_RD_LOCK_KEY_SLOT_2_POS))
#define EF_DATA_RD_LOCK_KEY_SLOT_3 EF_DATA_RD_LOCK_KEY_SLOT_3
#define EF_DATA_RD_LOCK_KEY_SLOT_3_POS (29U)
#define EF_DATA_RD_LOCK_KEY_SLOT_3_LEN (1U)
#define EF_DATA_RD_LOCK_KEY_SLOT_3_MSK (((1U << EF_DATA_RD_LOCK_KEY_SLOT_3_LEN) - 1) << EF_DATA_RD_LOCK_KEY_SLOT_3_POS)
#define EF_DATA_RD_LOCK_KEY_SLOT_3_UMSK (~(((1U << EF_DATA_RD_LOCK_KEY_SLOT_3_LEN) - 1) << EF_DATA_RD_LOCK_KEY_SLOT_3_POS))
#define EF_DATA_RD_LOCK_KEY_SLOT_4 EF_DATA_RD_LOCK_KEY_SLOT_4
#define EF_DATA_RD_LOCK_KEY_SLOT_4_POS (30U)
#define EF_DATA_RD_LOCK_KEY_SLOT_4_LEN (1U)
#define EF_DATA_RD_LOCK_KEY_SLOT_4_MSK (((1U << EF_DATA_RD_LOCK_KEY_SLOT_4_LEN) - 1) << EF_DATA_RD_LOCK_KEY_SLOT_4_POS)
#define EF_DATA_RD_LOCK_KEY_SLOT_4_UMSK (~(((1U << EF_DATA_RD_LOCK_KEY_SLOT_4_LEN) - 1) << EF_DATA_RD_LOCK_KEY_SLOT_4_POS))
#define EF_DATA_RD_LOCK_KEY_SLOT_5 EF_DATA_RD_LOCK_KEY_SLOT_5
#define EF_DATA_RD_LOCK_KEY_SLOT_5_POS (31U)
#define EF_DATA_RD_LOCK_KEY_SLOT_5_LEN (1U)
#define EF_DATA_RD_LOCK_KEY_SLOT_5_MSK (((1U << EF_DATA_RD_LOCK_KEY_SLOT_5_LEN) - 1) << EF_DATA_RD_LOCK_KEY_SLOT_5_POS)
#define EF_DATA_RD_LOCK_KEY_SLOT_5_UMSK (~(((1U << EF_DATA_RD_LOCK_KEY_SLOT_5_LEN) - 1) << EF_DATA_RD_LOCK_KEY_SLOT_5_POS))
struct EF_DATA_reg {
/* 0x0 : ef_cfg_0 */
union {
struct
{
uint32_t ef_sf_aes_mode : 2; /* [ 1: 0], r/w, 0x0 */
uint32_t ef_sboot_sign_mode : 2; /* [ 3: 2], r/w, 0x0 */
uint32_t rsvd0 : 2; /* [ 5: 4], r/w, 0x0 */
uint32_t rsvd1 : 1; /* [ 6], r/w, 0x0 */
uint32_t ef_cpu0_enc_en : 1; /* [ 7], r/w, 0x0 */
uint32_t ef_boot_sel : 4; /* [11: 8], r/w, 0x0 */
uint32_t ef_sf_key_0_sel : 2; /* [13:12], r/w, 0x0 */
uint32_t rsvd2 : 1; /* [ 14], r/w, 0x0 */
uint32_t rsvd3 : 1; /* [ 15], r/w, 0x0 */
uint32_t rsvd4 : 1; /* [ 16], r/w, 0x0 */
uint32_t ef_0_key_enc_en : 1; /* [ 17], r/w, 0x0 */
uint32_t rsvd5 : 1; /* [ 18], r/w, 0x0 */
uint32_t rsvd6 : 1; /* [ 19], r/w, 0x0 */
uint32_t rsvd7 : 1; /* [ 20], r/w, 0x0 */
uint32_t rsvd8 : 1; /* [ 21], r/w, 0x0 */
uint32_t rsvd9 : 1; /* [ 22], r/w, 0x0 */
uint32_t rsvd10 : 1; /* [ 23], r/w, 0x0 */
uint32_t rsvd11 : 2; /* [25:24], r/w, 0x0 */
uint32_t ef_dbg_jtag_0_dis : 2; /* [27:26], r/w, 0x0 */
uint32_t ef_dbg_mode : 4; /* [31:28], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_cfg_0;
/* 0x4 : ef_dbg_pwd_low */
union {
struct
{
uint32_t ef_dbg_pwd_low : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_dbg_pwd_low;
/* 0x8 : ef_dbg_pwd_high */
union {
struct
{
uint32_t ef_dbg_pwd_high : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_dbg_pwd_high;
/* 0xC : ef_ana_trim_0 */
union {
struct
{
uint32_t ef_ana_trim_0 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_ana_trim_0;
/* 0x10 : ef_sw_usage_0 */
union {
struct
{
uint32_t ef_sw_usage_0 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_sw_usage_0;
/* 0x14 : ef_wifi_mac_low */
union {
struct
{
uint32_t ef_wifi_mac_low : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_wifi_mac_low;
/* 0x18 : ef_wifi_mac_high */
union {
struct
{
uint32_t ef_wifi_mac_high : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_wifi_mac_high;
/* 0x1C : ef_key_slot_0_w0 */
union {
struct
{
uint32_t ef_key_slot_0_w0 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_0_w0;
/* 0x20 : ef_key_slot_0_w1 */
union {
struct
{
uint32_t ef_key_slot_0_w1 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_0_w1;
/* 0x24 : ef_key_slot_0_w2 */
union {
struct
{
uint32_t ef_key_slot_0_w2 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_0_w2;
/* 0x28 : ef_key_slot_0_w3 */
union {
struct
{
uint32_t ef_key_slot_0_w3 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_0_w3;
/* 0x2C : ef_key_slot_1_w0 */
union {
struct
{
uint32_t ef_key_slot_1_w0 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_1_w0;
/* 0x30 : ef_key_slot_1_w1 */
union {
struct
{
uint32_t ef_key_slot_1_w1 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_1_w1;
/* 0x34 : ef_key_slot_1_w2 */
union {
struct
{
uint32_t ef_key_slot_1_w2 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_1_w2;
/* 0x38 : ef_key_slot_1_w3 */
union {
struct
{
uint32_t ef_key_slot_1_w3 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_1_w3;
/* 0x3C : ef_key_slot_2_w0 */
union {
struct
{
uint32_t ef_key_slot_2_w0 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_2_w0;
/* 0x40 : ef_key_slot_2_w1 */
union {
struct
{
uint32_t ef_key_slot_2_w1 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_2_w1;
/* 0x44 : ef_key_slot_2_w2 */
union {
struct
{
uint32_t ef_key_slot_2_w2 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_2_w2;
/* 0x48 : ef_key_slot_2_w3 */
union {
struct
{
uint32_t ef_key_slot_2_w3 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_2_w3;
/* 0x4C : ef_key_slot_3_w0 */
union {
struct
{
uint32_t ef_key_slot_3_w0 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_3_w0;
/* 0x50 : ef_key_slot_3_w1 */
union {
struct
{
uint32_t ef_key_slot_3_w1 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_3_w1;
/* 0x54 : ef_key_slot_3_w2 */
union {
struct
{
uint32_t ef_key_slot_3_w2 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_3_w2;
/* 0x58 : ef_key_slot_3_w3 */
union {
struct
{
uint32_t ef_key_slot_3_w3 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_3_w3;
/* 0x5C : ef_key_slot_4_w0 */
union {
struct
{
uint32_t ef_key_slot_4_w0 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_4_w0;
/* 0x60 : ef_key_slot_4_w1 */
union {
struct
{
uint32_t ef_key_slot_4_w1 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_4_w1;
/* 0x64 : ef_key_slot_4_w2 */
union {
struct
{
uint32_t ef_key_slot_4_w2 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_4_w2;
/* 0x68 : ef_key_slot_4_w3 */
union {
struct
{
uint32_t ef_key_slot_4_w3 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_4_w3;
/* 0x6C : ef_key_slot_5_w0 */
union {
struct
{
uint32_t ef_key_slot_5_w0 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_5_w0;
/* 0x70 : ef_key_slot_5_w1 */
union {
struct
{
uint32_t ef_key_slot_5_w1 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_5_w1;
/* 0x74 : ef_key_slot_5_w2 */
union {
struct
{
uint32_t ef_key_slot_5_w2 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_5_w2;
/* 0x78 : ef_key_slot_5_w3 */
union {
struct
{
uint32_t ef_key_slot_5_w3 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_5_w3;
/* 0x7C : EF_DATA_lock */
union {
struct
{
uint32_t ef_ana_trim_1 : 13; /* [12: 0], r/w, 0x0 */
uint32_t wr_lock_key_slot_4_l : 1; /* [ 13], r/w, 0x0 */
uint32_t wr_lock_key_slot_5_l : 1; /* [ 14], r/w, 0x0 */
uint32_t wr_lock_boot_mode : 1; /* [ 15], r/w, 0x0 */
uint32_t wr_lock_dbg_pwd : 1; /* [ 16], r/w, 0x0 */
uint32_t wr_lock_sw_usage_0 : 1; /* [ 17], r/w, 0x0 */
uint32_t wr_lock_wifi_mac : 1; /* [ 18], r/w, 0x0 */
uint32_t wr_lock_key_slot_0 : 1; /* [ 19], r/w, 0x0 */
uint32_t wr_lock_key_slot_1 : 1; /* [ 20], r/w, 0x0 */
uint32_t wr_lock_key_slot_2 : 1; /* [ 21], r/w, 0x0 */
uint32_t wr_lock_key_slot_3 : 1; /* [ 22], r/w, 0x0 */
uint32_t wr_lock_key_slot_4_h : 1; /* [ 23], r/w, 0x0 */
uint32_t wr_lock_key_slot_5_h : 1; /* [ 24], r/w, 0x0 */
uint32_t rd_lock_dbg_pwd : 1; /* [ 25], r/w, 0x0 */
uint32_t rd_lock_key_slot_0 : 1; /* [ 26], r/w, 0x0 */
uint32_t rd_lock_key_slot_1 : 1; /* [ 27], r/w, 0x0 */
uint32_t rd_lock_key_slot_2 : 1; /* [ 28], r/w, 0x0 */
uint32_t rd_lock_key_slot_3 : 1; /* [ 29], r/w, 0x0 */
uint32_t rd_lock_key_slot_4 : 1; /* [ 30], r/w, 0x0 */
uint32_t rd_lock_key_slot_5 : 1; /* [ 31], r/w, 0x0 */
} BF;
uint32_t WORD;
} EF_DATA_lock;
};
typedef volatile struct EF_DATA_reg EF_DATA_reg_t;
#endif /* __EF_DATA_REG_H__ */

256
drivers/soc/bl702/bl702_std/include/hardware/tzc_sec_reg.h Normal file
View file

@ -0,0 +1,256 @@
/**
******************************************************************************
* @file tzc_sec_reg.h
* @version V1.2
* @date 2020-03-30
* @brief This file is the description of.IP register
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2019 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __TZC_SEC_REG_H__
#define __TZC_SEC_REG_H__
#include "bl702.h"
/* 0x40 : tzc_rom_ctrl */
#define TZC_SEC_TZC_ROM_CTRL_OFFSET (0x40)
#define TZC_SEC_TZC_ROM0_R0_ID0_EN TZC_SEC_TZC_ROM0_R0_ID0_EN
#define TZC_SEC_TZC_ROM0_R0_ID0_EN_POS (0U)
#define TZC_SEC_TZC_ROM0_R0_ID0_EN_LEN (1U)
#define TZC_SEC_TZC_ROM0_R0_ID0_EN_MSK (((1U << TZC_SEC_TZC_ROM0_R0_ID0_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_ID0_EN_POS)
#define TZC_SEC_TZC_ROM0_R0_ID0_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R0_ID0_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_ID0_EN_POS))
#define TZC_SEC_TZC_ROM0_R1_ID0_EN TZC_SEC_TZC_ROM0_R1_ID0_EN
#define TZC_SEC_TZC_ROM0_R1_ID0_EN_POS (1U)
#define TZC_SEC_TZC_ROM0_R1_ID0_EN_LEN (1U)
#define TZC_SEC_TZC_ROM0_R1_ID0_EN_MSK (((1U << TZC_SEC_TZC_ROM0_R1_ID0_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_ID0_EN_POS)
#define TZC_SEC_TZC_ROM0_R1_ID0_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R1_ID0_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_ID0_EN_POS))
#define TZC_SEC_TZC_ROM1_R0_ID0_EN TZC_SEC_TZC_ROM1_R0_ID0_EN
#define TZC_SEC_TZC_ROM1_R0_ID0_EN_POS (2U)
#define TZC_SEC_TZC_ROM1_R0_ID0_EN_LEN (1U)
#define TZC_SEC_TZC_ROM1_R0_ID0_EN_MSK (((1U << TZC_SEC_TZC_ROM1_R0_ID0_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_ID0_EN_POS)
#define TZC_SEC_TZC_ROM1_R0_ID0_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R0_ID0_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_ID0_EN_POS))
#define TZC_SEC_TZC_ROM1_R1_ID0_EN TZC_SEC_TZC_ROM1_R1_ID0_EN
#define TZC_SEC_TZC_ROM1_R1_ID0_EN_POS (3U)
#define TZC_SEC_TZC_ROM1_R1_ID0_EN_LEN (1U)
#define TZC_SEC_TZC_ROM1_R1_ID0_EN_MSK (((1U << TZC_SEC_TZC_ROM1_R1_ID0_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_ID0_EN_POS)
#define TZC_SEC_TZC_ROM1_R1_ID0_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R1_ID0_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_ID0_EN_POS))
#define TZC_SEC_TZC_ROM0_R0_ID1_EN TZC_SEC_TZC_ROM0_R0_ID1_EN
#define TZC_SEC_TZC_ROM0_R0_ID1_EN_POS (8U)
#define TZC_SEC_TZC_ROM0_R0_ID1_EN_LEN (1U)
#define TZC_SEC_TZC_ROM0_R0_ID1_EN_MSK (((1U << TZC_SEC_TZC_ROM0_R0_ID1_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_ID1_EN_POS)
#define TZC_SEC_TZC_ROM0_R0_ID1_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R0_ID1_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_ID1_EN_POS))
#define TZC_SEC_TZC_ROM0_R1_ID1_EN TZC_SEC_TZC_ROM0_R1_ID1_EN
#define TZC_SEC_TZC_ROM0_R1_ID1_EN_POS (9U)
#define TZC_SEC_TZC_ROM0_R1_ID1_EN_LEN (1U)
#define TZC_SEC_TZC_ROM0_R1_ID1_EN_MSK (((1U << TZC_SEC_TZC_ROM0_R1_ID1_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_ID1_EN_POS)
#define TZC_SEC_TZC_ROM0_R1_ID1_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R1_ID1_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_ID1_EN_POS))
#define TZC_SEC_TZC_ROM1_R0_ID1_EN TZC_SEC_TZC_ROM1_R0_ID1_EN
#define TZC_SEC_TZC_ROM1_R0_ID1_EN_POS (10U)
#define TZC_SEC_TZC_ROM1_R0_ID1_EN_LEN (1U)
#define TZC_SEC_TZC_ROM1_R0_ID1_EN_MSK (((1U << TZC_SEC_TZC_ROM1_R0_ID1_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_ID1_EN_POS)
#define TZC_SEC_TZC_ROM1_R0_ID1_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R0_ID1_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_ID1_EN_POS))
#define TZC_SEC_TZC_ROM1_R1_ID1_EN TZC_SEC_TZC_ROM1_R1_ID1_EN
#define TZC_SEC_TZC_ROM1_R1_ID1_EN_POS (11U)
#define TZC_SEC_TZC_ROM1_R1_ID1_EN_LEN (1U)
#define TZC_SEC_TZC_ROM1_R1_ID1_EN_MSK (((1U << TZC_SEC_TZC_ROM1_R1_ID1_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_ID1_EN_POS)
#define TZC_SEC_TZC_ROM1_R1_ID1_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R1_ID1_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_ID1_EN_POS))
#define TZC_SEC_TZC_ROM0_R0_EN TZC_SEC_TZC_ROM0_R0_EN
#define TZC_SEC_TZC_ROM0_R0_EN_POS (16U)
#define TZC_SEC_TZC_ROM0_R0_EN_LEN (1U)
#define TZC_SEC_TZC_ROM0_R0_EN_MSK (((1U << TZC_SEC_TZC_ROM0_R0_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_EN_POS)
#define TZC_SEC_TZC_ROM0_R0_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R0_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_EN_POS))
#define TZC_SEC_TZC_ROM0_R1_EN TZC_SEC_TZC_ROM0_R1_EN
#define TZC_SEC_TZC_ROM0_R1_EN_POS (17U)
#define TZC_SEC_TZC_ROM0_R1_EN_LEN (1U)
#define TZC_SEC_TZC_ROM0_R1_EN_MSK (((1U << TZC_SEC_TZC_ROM0_R1_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_EN_POS)
#define TZC_SEC_TZC_ROM0_R1_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R1_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_EN_POS))
#define TZC_SEC_TZC_ROM1_R0_EN TZC_SEC_TZC_ROM1_R0_EN
#define TZC_SEC_TZC_ROM1_R0_EN_POS (18U)
#define TZC_SEC_TZC_ROM1_R0_EN_LEN (1U)
#define TZC_SEC_TZC_ROM1_R0_EN_MSK (((1U << TZC_SEC_TZC_ROM1_R0_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_EN_POS)
#define TZC_SEC_TZC_ROM1_R0_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R0_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_EN_POS))
#define TZC_SEC_TZC_ROM1_R1_EN TZC_SEC_TZC_ROM1_R1_EN
#define TZC_SEC_TZC_ROM1_R1_EN_POS (19U)
#define TZC_SEC_TZC_ROM1_R1_EN_LEN (1U)
#define TZC_SEC_TZC_ROM1_R1_EN_MSK (((1U << TZC_SEC_TZC_ROM1_R1_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_EN_POS)
#define TZC_SEC_TZC_ROM1_R1_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R1_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_EN_POS))
#define TZC_SEC_TZC_ROM0_R0_LOCK TZC_SEC_TZC_ROM0_R0_LOCK
#define TZC_SEC_TZC_ROM0_R0_LOCK_POS (24U)
#define TZC_SEC_TZC_ROM0_R0_LOCK_LEN (1U)
#define TZC_SEC_TZC_ROM0_R0_LOCK_MSK (((1U << TZC_SEC_TZC_ROM0_R0_LOCK_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_LOCK_POS)
#define TZC_SEC_TZC_ROM0_R0_LOCK_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R0_LOCK_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_LOCK_POS))
#define TZC_SEC_TZC_ROM0_R1_LOCK TZC_SEC_TZC_ROM0_R1_LOCK
#define TZC_SEC_TZC_ROM0_R1_LOCK_POS (25U)
#define TZC_SEC_TZC_ROM0_R1_LOCK_LEN (1U)
#define TZC_SEC_TZC_ROM0_R1_LOCK_MSK (((1U << TZC_SEC_TZC_ROM0_R1_LOCK_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_LOCK_POS)
#define TZC_SEC_TZC_ROM0_R1_LOCK_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R1_LOCK_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_LOCK_POS))
#define TZC_SEC_TZC_ROM1_R0_LOCK TZC_SEC_TZC_ROM1_R0_LOCK
#define TZC_SEC_TZC_ROM1_R0_LOCK_POS (26U)
#define TZC_SEC_TZC_ROM1_R0_LOCK_LEN (1U)
#define TZC_SEC_TZC_ROM1_R0_LOCK_MSK (((1U << TZC_SEC_TZC_ROM1_R0_LOCK_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_LOCK_POS)
#define TZC_SEC_TZC_ROM1_R0_LOCK_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R0_LOCK_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_LOCK_POS))
#define TZC_SEC_TZC_ROM1_R1_LOCK TZC_SEC_TZC_ROM1_R1_LOCK
#define TZC_SEC_TZC_ROM1_R1_LOCK_POS (27U)
#define TZC_SEC_TZC_ROM1_R1_LOCK_LEN (1U)
#define TZC_SEC_TZC_ROM1_R1_LOCK_MSK (((1U << TZC_SEC_TZC_ROM1_R1_LOCK_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_LOCK_POS)
#define TZC_SEC_TZC_ROM1_R1_LOCK_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R1_LOCK_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_LOCK_POS))
#define TZC_SEC_TZC_SBOOT_DONE TZC_SEC_TZC_SBOOT_DONE
#define TZC_SEC_TZC_SBOOT_DONE_POS (28U)
#define TZC_SEC_TZC_SBOOT_DONE_LEN (4U)
#define TZC_SEC_TZC_SBOOT_DONE_MSK (((1U << TZC_SEC_TZC_SBOOT_DONE_LEN) - 1) << TZC_SEC_TZC_SBOOT_DONE_POS)
#define TZC_SEC_TZC_SBOOT_DONE_UMSK (~(((1U << TZC_SEC_TZC_SBOOT_DONE_LEN) - 1) << TZC_SEC_TZC_SBOOT_DONE_POS))
/* 0x44 : tzc_rom0_r0 */
#define TZC_SEC_TZC_ROM0_R0_OFFSET (0x44)
#define TZC_SEC_TZC_ROM0_R0_END TZC_SEC_TZC_ROM0_R0_END
#define TZC_SEC_TZC_ROM0_R0_END_POS (0U)
#define TZC_SEC_TZC_ROM0_R0_END_LEN (16U)
#define TZC_SEC_TZC_ROM0_R0_END_MSK (((1U << TZC_SEC_TZC_ROM0_R0_END_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_END_POS)
#define TZC_SEC_TZC_ROM0_R0_END_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R0_END_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_END_POS))
#define TZC_SEC_TZC_ROM0_R0_START TZC_SEC_TZC_ROM0_R0_START
#define TZC_SEC_TZC_ROM0_R0_START_POS (16U)
#define TZC_SEC_TZC_ROM0_R0_START_LEN (16U)
#define TZC_SEC_TZC_ROM0_R0_START_MSK (((1U << TZC_SEC_TZC_ROM0_R0_START_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_START_POS)
#define TZC_SEC_TZC_ROM0_R0_START_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R0_START_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_START_POS))
/* 0x48 : tzc_rom0_r1 */
#define TZC_SEC_TZC_ROM0_R1_OFFSET (0x48)
#define TZC_SEC_TZC_ROM0_R1_END TZC_SEC_TZC_ROM0_R1_END
#define TZC_SEC_TZC_ROM0_R1_END_POS (0U)
#define TZC_SEC_TZC_ROM0_R1_END_LEN (16U)
#define TZC_SEC_TZC_ROM0_R1_END_MSK (((1U << TZC_SEC_TZC_ROM0_R1_END_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_END_POS)
#define TZC_SEC_TZC_ROM0_R1_END_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R1_END_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_END_POS))
#define TZC_SEC_TZC_ROM0_R1_START TZC_SEC_TZC_ROM0_R1_START
#define TZC_SEC_TZC_ROM0_R1_START_POS (16U)
#define TZC_SEC_TZC_ROM0_R1_START_LEN (16U)
#define TZC_SEC_TZC_ROM0_R1_START_MSK (((1U << TZC_SEC_TZC_ROM0_R1_START_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_START_POS)
#define TZC_SEC_TZC_ROM0_R1_START_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R1_START_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_START_POS))
/* 0x4C : tzc_rom1_r0 */
#define TZC_SEC_TZC_ROM1_R0_OFFSET (0x4C)
#define TZC_SEC_TZC_ROM1_R0_END TZC_SEC_TZC_ROM1_R0_END
#define TZC_SEC_TZC_ROM1_R0_END_POS (0U)
#define TZC_SEC_TZC_ROM1_R0_END_LEN (16U)
#define TZC_SEC_TZC_ROM1_R0_END_MSK (((1U << TZC_SEC_TZC_ROM1_R0_END_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_END_POS)
#define TZC_SEC_TZC_ROM1_R0_END_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R0_END_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_END_POS))
#define TZC_SEC_TZC_ROM1_R0_START TZC_SEC_TZC_ROM1_R0_START
#define TZC_SEC_TZC_ROM1_R0_START_POS (16U)
#define TZC_SEC_TZC_ROM1_R0_START_LEN (16U)
#define TZC_SEC_TZC_ROM1_R0_START_MSK (((1U << TZC_SEC_TZC_ROM1_R0_START_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_START_POS)
#define TZC_SEC_TZC_ROM1_R0_START_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R0_START_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_START_POS))
/* 0x50 : tzc_rom1_r1 */
#define TZC_SEC_TZC_ROM1_R1_OFFSET (0x50)
#define TZC_SEC_TZC_ROM1_R1_END TZC_SEC_TZC_ROM1_R1_END
#define TZC_SEC_TZC_ROM1_R1_END_POS (0U)
#define TZC_SEC_TZC_ROM1_R1_END_LEN (16U)
#define TZC_SEC_TZC_ROM1_R1_END_MSK (((1U << TZC_SEC_TZC_ROM1_R1_END_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_END_POS)
#define TZC_SEC_TZC_ROM1_R1_END_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R1_END_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_END_POS))
#define TZC_SEC_TZC_ROM1_R1_START TZC_SEC_TZC_ROM1_R1_START
#define TZC_SEC_TZC_ROM1_R1_START_POS (16U)
#define TZC_SEC_TZC_ROM1_R1_START_LEN (16U)
#define TZC_SEC_TZC_ROM1_R1_START_MSK (((1U << TZC_SEC_TZC_ROM1_R1_START_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_START_POS)
#define TZC_SEC_TZC_ROM1_R1_START_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R1_START_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_START_POS))
struct tzc_sec_reg {
/* 0x0 reserved */
uint8_t RESERVED0x0[64];
/* 0x40 : tzc_rom_ctrl */
union {
struct
{
uint32_t tzc_rom0_r0_id0_en : 1; /* [ 0], r/w, 0x1 */
uint32_t tzc_rom0_r1_id0_en : 1; /* [ 1], r/w, 0x1 */
uint32_t tzc_rom1_r0_id0_en : 1; /* [ 2], r/w, 0x1 */
uint32_t tzc_rom1_r1_id0_en : 1; /* [ 3], r/w, 0x1 */
uint32_t reserved_4_7 : 4; /* [ 7: 4], rsvd, 0x0 */
uint32_t tzc_rom0_r0_id1_en : 1; /* [ 8], r/w, 0x1 */
uint32_t tzc_rom0_r1_id1_en : 1; /* [ 9], r/w, 0x1 */
uint32_t tzc_rom1_r0_id1_en : 1; /* [ 10], r/w, 0x1 */
uint32_t tzc_rom1_r1_id1_en : 1; /* [ 11], r/w, 0x1 */
uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */
uint32_t tzc_rom0_r0_en : 1; /* [ 16], r/w, 0x0 */
uint32_t tzc_rom0_r1_en : 1; /* [ 17], r/w, 0x0 */
uint32_t tzc_rom1_r0_en : 1; /* [ 18], r/w, 0x0 */
uint32_t tzc_rom1_r1_en : 1; /* [ 19], r/w, 0x0 */
uint32_t reserved_20_23 : 4; /* [23:20], rsvd, 0x0 */
uint32_t tzc_rom0_r0_lock : 1; /* [ 24], r/w, 0x0 */
uint32_t tzc_rom0_r1_lock : 1; /* [ 25], r/w, 0x0 */
uint32_t tzc_rom1_r0_lock : 1; /* [ 26], r/w, 0x0 */
uint32_t tzc_rom1_r1_lock : 1; /* [ 27], r/w, 0x0 */
uint32_t tzc_sboot_done : 4; /* [31:28], r/w, 0x0 */
} BF;
uint32_t WORD;
} tzc_rom_ctrl;
/* 0x44 : tzc_rom0_r0 */
union {
struct
{
uint32_t tzc_rom0_r0_end : 16; /* [15: 0], r/w, 0xffff */
uint32_t tzc_rom0_r0_start : 16; /* [31:16], r/w, 0x0 */
} BF;
uint32_t WORD;
} tzc_rom0_r0;
/* 0x48 : tzc_rom0_r1 */
union {
struct
{
uint32_t tzc_rom0_r1_end : 16; /* [15: 0], r/w, 0xffff */
uint32_t tzc_rom0_r1_start : 16; /* [31:16], r/w, 0x0 */
} BF;
uint32_t WORD;
} tzc_rom0_r1;
/* 0x4C : tzc_rom1_r0 */
union {
struct
{
uint32_t tzc_rom1_r0_end : 16; /* [15: 0], r/w, 0xffff */
uint32_t tzc_rom1_r0_start : 16; /* [31:16], r/w, 0x0 */
} BF;
uint32_t WORD;
} tzc_rom1_r0;
/* 0x50 : tzc_rom1_r1 */
union {
struct
{
uint32_t tzc_rom1_r1_end : 16; /* [15: 0], r/w, 0xffff */
uint32_t tzc_rom1_r1_start : 16; /* [31:16], r/w, 0x0 */
} BF;
uint32_t WORD;
} tzc_rom1_r1;
};
typedef volatile struct tzc_sec_reg tzc_sec_reg_t;
#endif /* __TZC_SEC_REG_H__ */

387
drivers/soc/bl702/bl702_std/src/bl702_ef_cfg.c
View file

@ -34,35 +34,13 @@
******************************************************************************
*/
#include "string.h"
#include "bflb_ef_ctrl.h"
#include "bl702_ef_cfg.h"
#include "bl702_glb.h"
#include "hardware/ef_data_reg.h"
/** @addtogroup BL702_Peripheral_Driver
* @{
*/
extern int bflb_efuse_read_mac_address_opt(uint8_t slot, uint8_t mac[6], uint8_t reload);
/** @addtogroup SEC_EF_CTRL
* @{
*/
/** @defgroup SEC_EF_CTRL_Private_Macros
* @{
*/
/*@} end of group SEC_EF_CTRL_Private_Macros */
/** @defgroup SEC_EF_CTRL_Private_Types
* @{
*/
/*@} end of group SEC_EF_CTRL_Private_Types */
/** @defgroup SEC_EF_CTRL_Private_Variables
* @{
*/
static const bflb_ef_ctrl_com_trim_cfg trim_list[] = {
static const bflb_ef_ctrl_com_trim_cfg_t trim_list[] = {
{
.name = "rc32m",
.en_addr = 0x78 * 8 + 1,
@ -93,81 +71,9 @@ static const bflb_ef_ctrl_com_trim_cfg trim_list[] = {
}
};
#define EF_CTRL_DEVICE_INFO_OFFSET 0x74
/* 0x14 : ef_wifi_mac_low */
#define EF_DATA_EF_WIFI_MAC_LOW_OFFSET (0x14)
/* 0x18 : ef_wifi_mac_high */
#define EF_DATA_EF_WIFI_MAC_HIGH_OFFSET (0x18)
/* 0x1C : ef_key_slot_0_w0 */
#define EF_DATA_EF_KEY_SLOT_0_W0_OFFSET (0x1C)
/* 0x20 : ef_key_slot_0_w1 */
#define EF_DATA_EF_KEY_SLOT_0_W1_OFFSET (0x20)
/* 0x24 : ef_key_slot_0_w2 */
#define EF_DATA_EF_KEY_SLOT_0_W2_OFFSET (0x24)
/* 0x28 : ef_key_slot_0_w3 */
#define EF_DATA_EF_KEY_SLOT_0_W3_OFFSET (0x28)
/* 0x2C : ef_key_slot_1_w0 */
#define EF_DATA_EF_KEY_SLOT_1_W0_OFFSET (0x2C)
/* 0x30 : ef_key_slot_1_w1 */
#define EF_DATA_EF_KEY_SLOT_1_W1_OFFSET (0x30)
/* 0x34 : ef_key_slot_1_w2 */
#define EF_DATA_EF_KEY_SLOT_1_W2_OFFSET (0x34)
/* 0x38 : ef_key_slot_1_w3 */
#define EF_DATA_EF_KEY_SLOT_1_W3_OFFSET (0x38)
/* 0x3C : ef_key_slot_2_w0 */
#define EF_DATA_EF_KEY_SLOT_2_W0_OFFSET (0x3C)
/* 0x40 : ef_key_slot_2_w1 */
#define EF_DATA_EF_KEY_SLOT_2_W1_OFFSET (0x40)
/* 0x44 : ef_key_slot_2_w2 */
#define EF_DATA_EF_KEY_SLOT_2_W2_OFFSET (0x44)
/* 0x48 : ef_key_slot_2_w3 */
#define EF_DATA_EF_KEY_SLOT_2_W3_OFFSET (0x48)
/* 0x4C : ef_key_slot_3_w0 */
#define EF_DATA_EF_KEY_SLOT_3_W0_OFFSET (0x4C)
/* 0x50 : ef_key_slot_3_w1 */
#define EF_DATA_EF_KEY_SLOT_3_W1_OFFSET (0x50)
/* 0x54 : ef_key_slot_3_w2 */
#define EF_DATA_EF_KEY_SLOT_3_W2_OFFSET (0x54)
/* 0x58 : ef_key_slot_3_w3 */
#define EF_DATA_EF_KEY_SLOT_3_W3_OFFSET (0x58)
/* 0x5C : ef_key_slot_4_w0 */
#define EF_DATA_EF_KEY_SLOT_4_W0_OFFSET (0x5C)
/* 0x60 : ef_key_slot_4_w1 */
#define EF_DATA_EF_KEY_SLOT_4_W1_OFFSET (0x60)
/* 0x64 : ef_key_slot_4_w2 */
#define EF_DATA_EF_KEY_SLOT_4_W2_OFFSET (0x64)
/* 0x68 : ef_key_slot_4_w3 */
#define EF_DATA_EF_KEY_SLOT_4_W3_OFFSET (0x68)
/* 0x6C : ef_key_slot_5_w0 */
#define EF_DATA_EF_KEY_SLOT_5_W0_OFFSET (0x6C)
/* 0x70 : ef_key_slot_5_w1 */
#define EF_DATA_EF_KEY_SLOT_5_W1_OFFSET (0x70)
/* 0x74 : ef_key_slot_5_w2 */
#define EF_DATA_EF_KEY_SLOT_5_W2_OFFSET (0x74)
/* 0x78 : ef_key_slot_5_w3 */
#define EF_DATA_EF_KEY_SLOT_5_W3_OFFSET (0x78)
static GLB_ROOT_CLK_Type rtClk;
static uint8_t bdiv, hdiv;
/*@} end of group SEC_EF_CTRL_Private_Variables */
/** @defgroup SEC_EF_CTRL_Global_Variables
* @{
*/
/*@} end of group SEC_EF_CTRL_Global_Variables */
/** @defgroup SEC_EF_CTRL_Private_Fun_Declaration
* @{
*/
/*@} end of group SEC_EF_CTRL_Private_Fun_Declaration */
/** @defgroup SEC_EF_CTRL_Private_Functions
* @{
*/
/****************************************************************************/ /**
* @brief Efuse read write switch clock save
*
@ -201,6 +107,20 @@ void ATTR_TCM_SECTION bflb_efuse_switch_cpu_clock_restore(void)
HBN_Set_ROOT_CLK_Sel(rtClk);
}
/****************************************************************************/ /**
* @brief Efuse get trim list
*
* @param trim_list: Trim list pointer
*
* @return Trim list count
*
*******************************************************************************/
uint32_t bflb_ef_ctrl_get_common_trim_list(const bflb_ef_ctrl_com_trim_cfg_t **ptrim_list)
{
*ptrim_list = &trim_list[0];
return sizeof(trim_list) / sizeof(trim_list[0]);
}
/****************************************************************************/ /**
* @brief Efuse read device info
*
@ -213,25 +133,278 @@ void bflb_ef_ctrl_get_device_info(bflb_efuse_device_info_type *deviceInfo)
{
uint32_t *p = (uint32_t *)deviceInfo;
bflb_ef_ctrl_read_direct(NULL, EF_CTRL_DEVICE_INFO_OFFSET, p, 1, 1);
bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_WIFI_MAC_HIGH_OFFSET, p, 1, 1);
}
void bflb_efuse_get_chipid(uint8_t chipid[8])
{
bflb_efuse_read_mac_address_opt(0, chipid, 1);
chipid[6] = 0;
chipid[7] = 0;
}
/****************************************************************************/ /**
* @brief Efuse get trim list
* @brief Whether MAC address slot is empty
*
* @param trim_list: Trim list pointer
* @param slot: MAC address slot
* @param reload: whether reload to check
*
* @return Trim list count
* @return 0 for all slots full,1 for others
*
*******************************************************************************/
uint32_t bflb_ef_ctrl_get_common_trim_list(const bflb_ef_ctrl_com_trim_cfg **ptrim_list)
uint8_t bflb_efuse_is_mac_address_slot_empty(uint8_t slot, uint8_t reload)
{
*ptrim_list = &trim_list[0];
return sizeof(trim_list) / sizeof(trim_list[0]);
uint32_t tmp1 = 0xffffffff, tmp2 = 0xffffffff;
uint32_t part1Empty = 0, part2Empty = 0;
if (slot == 0) {
bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_WIFI_MAC_LOW_OFFSET, &tmp1, 1, reload);
bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_WIFI_MAC_HIGH_OFFSET, &tmp2, 1, reload);
} else if (slot == 1) {
bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_KEY_SLOT_5_W0_OFFSET, &tmp1, 1, reload);
bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_KEY_SLOT_5_W1_OFFSET, &tmp2, 1, reload);
} else if (slot == 2) {
bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_DBG_PWD_LOW_OFFSET, &tmp1, 1, reload);
bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_DBG_PWD_HIGH_OFFSET, &tmp2, 1, reload);
}
part1Empty = (bflb_ef_ctrl_is_all_bits_zero(tmp1, 0, 32));
part2Empty = (bflb_ef_ctrl_is_all_bits_zero(tmp2, 0, 22));
return (part1Empty && part2Empty);
}
/*@} end of group SEC_EF_CTRL_Public_Functions */
/****************************************************************************/ /**
* @brief Efuse write optional MAC address
*
* @param slot: MAC address slot
* @param mac[6]: MAC address buffer
* @param program: Whether program
*
* @return 0 or -1
*
*******************************************************************************/
int bflb_efuse_write_mac_address_opt(uint8_t slot, uint8_t mac[6], uint8_t program)
{
uint8_t *maclow = (uint8_t *)mac;
uint8_t *machigh = (uint8_t *)(mac + 4);
uint32_t tmpval;
uint32_t i = 0, cnt;
/*@} end of group SEC_EF_CTRL */
if (slot >= 3) {
return -1;
}
/*@} end of group BL702_Peripheral_Driver */
/* Change to local order */
for (i = 0; i < 3; i++) {
tmpval = mac[i];
mac[i] = mac[5 - i];
mac[5 - i] = tmpval;
}
/* The low 32 bits */
tmpval = BL_RDWD_FRM_BYTEP(maclow);
if (slot == 0) {
bflb_ef_ctrl_write_direct(NULL, EF_DATA_EF_WIFI_MAC_LOW_OFFSET, &tmpval, 1, program);
} else if (slot == 1) {
bflb_ef_ctrl_write_direct(NULL, EF_DATA_EF_KEY_SLOT_5_W0_OFFSET, &tmpval, 1, program);
} else if (slot == 2) {
bflb_ef_ctrl_write_direct(NULL, EF_DATA_EF_DBG_PWD_LOW_OFFSET, &tmpval, 1, program);
}
/* The high 16 bits */
tmpval = machigh[0] + (machigh[1] << 8);
cnt = 0;
for (i = 0; i < 6; i++) {
cnt += bflb_ef_ctrl_get_byte_zero_cnt(mac[i]);
}
tmpval |= ((cnt & 0x3f) << 16);
if (slot == 0) {
bflb_ef_ctrl_write_direct(NULL, EF_DATA_EF_WIFI_MAC_HIGH_OFFSET, &tmpval, 1, program);
} else if (slot == 1) {
bflb_ef_ctrl_write_direct(NULL, EF_DATA_EF_KEY_SLOT_5_W1_OFFSET, &tmpval, 1, program);
} else if (slot == 2) {
bflb_ef_ctrl_write_direct(NULL, EF_DATA_EF_DBG_PWD_HIGH_OFFSET, &tmpval, 1, program);
}
return 0;
}
/****************************************************************************/ /**
* @brief Efuse read optional MAC address
*
* @param slot: MAC address slot
* @param mac[6]: MAC address buffer
* @param reload: Whether reload
*
* @return 0 or -1
*
*******************************************************************************/
int bflb_efuse_read_mac_address_opt(uint8_t slot, uint8_t mac[6], uint8_t reload)
{
uint8_t *maclow = (uint8_t *)mac;
uint8_t *machigh = (uint8_t *)(mac + 4);
uint32_t tmpval = 0;
uint32_t i = 0;
uint32_t cnt = 0;
if (slot >= 3) {
return -1;
}
if (slot == 0) {
bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_WIFI_MAC_LOW_OFFSET, &tmpval, 1, reload);
} else if (slot == 1) {
bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_KEY_SLOT_5_W0_OFFSET, &tmpval, 1, reload);
} else if (slot == 2) {
bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_DBG_PWD_LOW_OFFSET, &tmpval, 1, reload);
}
BL_WRWD_TO_BYTEP(maclow, tmpval);
if (slot == 0) {
bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_WIFI_MAC_HIGH_OFFSET, &tmpval, 1, reload);
} else if (slot == 1) {
bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_KEY_SLOT_5_W1_OFFSET, &tmpval, 1, reload);
} else if (slot == 2) {
bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_DBG_PWD_HIGH_OFFSET, &tmpval, 1, reload);
}
machigh[0] = tmpval & 0xff;
machigh[1] = (tmpval >> 8) & 0xff;
/* Check parity */
for (i = 0; i < 6; i++) {
cnt += bflb_ef_ctrl_get_byte_zero_cnt(mac[i]);
}
if ((cnt & 0x3f) == ((tmpval >> 16) & 0x3f)) {
/* Change to network order */
for (i = 0; i < 3; i++) {
tmpval = mac[i];
mac[i] = mac[5 - i];
mac[5 - i] = tmpval;
}
return 0;
} else {
return -1;
}
}
float bflb_efuse_get_adc_trim(void)
{
bflb_ef_ctrl_com_trim_t trim;
uint32_t tmp;
float coe = 1.0;
bflb_ef_ctrl_read_common_trim(NULL, "gpadc_gain", &trim, 1);
if (trim.en) {
if (trim.parity == bflb_ef_ctrl_get_trim_parity(trim.value, trim.len)) {
tmp = trim.value;
if (tmp & 0x800) {
tmp = ~tmp;
tmp += 1;
tmp = tmp & 0xfff;
coe = (1.0 + ((float)tmp / 2048.0));
} else {
coe = (1.0 - ((float)tmp / 2048.0));
}
}
}
return coe;
}
uint32_t bflb_efuse_get_adc_tsen_trim(void)
{
bflb_ef_ctrl_com_trim_t trim;
bflb_ef_ctrl_read_common_trim(NULL, "tsen", &trim, 1);
if (trim.en) {
if (trim.parity == bflb_ef_ctrl_get_trim_parity(trim.value, trim.len)) {
return trim.value;
}
}
return 2042;
}
void bflb_efuse_read_secure_boot(uint8_t *sign, uint8_t *aes)
{
uint32_t tmpval = 0;
bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_CFG_0_OFFSET, &tmpval, 1, 1);
*sign = ((tmpval & EF_DATA_EF_SBOOT_SIGN_MODE_MSK) >> EF_DATA_EF_SBOOT_SIGN_MODE_POS) & 0x01;
*aes = ((tmpval & EF_DATA_EF_SF_AES_MODE_MSK) >> EF_DATA_EF_SF_AES_MODE_POS);
}
void bflb_efuse_write_aes_key(uint8_t index, uint8_t *data, uint32_t len)
{
if (index > 5) {
return;
}
bflb_ef_ctrl_write_direct(NULL, 0x1C + index * 4, (uint32_t *)data, len, 1);
}
void bflb_efuse_read_aes_key(uint8_t index, uint8_t *data, uint32_t len)
{
if (index > 5) {
return;
}
bflb_ef_ctrl_read_direct(NULL, 0x1C + index * 4, (uint32_t *)data, len, 1);
}
void bflb_efuse_lock_aes_key_write(uint8_t index)
{
uint32_t lock = 0;
if (index > 5) {
return;
}
/* write lock */
if (index <= 3) {
lock |= (1 << (index + 19));
} else {
lock |= (1 << (index + 19));
lock |= (1 << (index - 4 + 13));
}
bflb_ef_ctrl_write_direct(NULL, 0x7c, &lock, 1, 1);
}
void bflb_efuse_lock_aes_key_read(uint8_t index)
{
uint32_t lock = 0;
if (index > 5) {
return;
}
/* read lock */
lock |= (1 << (index + 26));
bflb_ef_ctrl_write_direct(NULL, 0x7c, &lock, 1, 1);
}
void bflb_efuse_write_sw_usage(uint32_t index, uint32_t usage, uint8_t program)
{
if (index != 0) {
return;
}
bflb_ef_ctrl_write_direct(NULL, EF_DATA_EF_SW_USAGE_0_OFFSET + index * 4, &usage, 1, program);
}
void bflb_efuse_read_sw_usage(uint32_t index, uint32_t *usage)
{
if (index != 0) {
return;
}
bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_SW_USAGE_0_OFFSET + index * 4, (uint32_t *)usage, 1, 1);
}

82
drivers/soc/bl702/port/bl702_efuse.c
View file

@ -1,82 +0,0 @@
#include "bflb_efuse.h"
#include "bflb_ef_ctrl.h"
#include "bl702_ef_cfg.h"
float bflb_efuse_get_adc_trim(void)
{
bflb_ef_ctrl_com_trim_type trim;
uint32_t tmp;
float coe = 1.0;
bflb_ef_ctrl_read_common_trim(NULL, "gpadc_gain", &trim, 1);
if (trim.en) {
if (trim.parity == bflb_ef_ctrl_get_trim_parity(trim.value, trim.len)) {
tmp = trim.value;
if (tmp & 0x800) {
tmp = ~tmp;
tmp += 1;
tmp = tmp & 0xfff;
coe = (1.0 + ((float)tmp / 2048.0));
} else {
coe = (1.0 - ((float)tmp / 2048.0));
}
}
}
return coe;
}
uint32_t bflb_efuse_get_adc_tsen_trim(void)
{
bflb_ef_ctrl_com_trim_type trim;
bflb_ef_ctrl_read_common_trim(NULL,"tsen", &trim,1);
if (trim.en) {
if (trim.parity == bflb_ef_ctrl_get_trim_parity(trim.value, trim.len)) {
return trim.value;
}
}
return 2042;
}
void bflb_efuse_write_aes_key(uint8_t index, uint8_t *data, uint32_t len)
{
bflb_ef_ctrl_write_direct(NULL, 0x1C + index * 4, (uint32_t *)data, len, 1);
}
void bflb_efuse_lock_aes_key_write(uint8_t index)
{
uint32_t lock = 0;
if (index > 5) {
return;
}
/* write lock */
if (index <= 3) {
lock |= (1 << (index + 19));
} else {
lock |= (1 << (index + 19));
lock |= (1 << (index - 4 + 13));
}
bflb_ef_ctrl_write_direct(NULL, 0x7c, (uint32_t *)lock, 1, 1);
}
void bflb_efuse_lock_aes_key_read(uint8_t index)
{
uint32_t lock = 0;
if (index > 5) {
return;
}
/* read lock */
lock |= (1 << (index + 26));
bflb_ef_ctrl_write_direct(NULL, 0x7c, (uint32_t *)lock, 1, 1);
}
void bflb_efuse_read_aes_key(uint8_t index, uint8_t *data, uint32_t len)
{
bflb_ef_ctrl_read_direct(NULL, 0x1C + index * 4, (uint32_t *)data, len, 1);
}

1
drivers/soc/bl808/CMakeLists.txt
View file

@ -28,7 +28,6 @@ sdk_library_add_sources(bl808_std/src/bl808_xip_sflash.c)
sdk_library_add_sources(port/bl808_clock.c)
sdk_library_add_sources(port/bl808_flash.c)
sdk_library_add_sources(port/bl808_efuse.c)
sdk_add_include_directories(
bl808_std/include

4
drivers/soc/bl808/bl808_std/include/bl808_common.h
View file

@ -161,7 +161,7 @@ void check_failed(uint8_t *file, uint32_t line);
#define ARCH_MemSet arch_memset
#define ARCH_MemCmp arch_memcmp
#define ARCH_MemCpy4 arch_memcpy4
#define ARCH_MemCpy_Fast arch_memcpy_fast
#define arch_memcpy_fast arch_memcpy_fast
#define ARCH_MemSet4 arch_memset4
#define BFLB_Soft_CRC32 bflb_soft_crc32
#define CPU_Interrupt_Enable(irq)
@ -180,7 +180,7 @@ void arch_delay_ms(uint32_t cnt);
void *ARCH_MemCpy(void *dst, const void *src, uint32_t n);
uint32_t *ARCH_MemCpy4(uint32_t *dst, const uint32_t *src, uint32_t n);
void *ARCH_MemCpy_Fast(void *pdst, const void *psrc, uint32_t n);
void *arch_memcpy_fast(void *pdst, const void *psrc, uint32_t n);
void *ARCH_MemSet(void *s, uint8_t c, uint32_t n);
uint32_t *ARCH_MemSet4(uint32_t *dst, const uint32_t val, uint32_t n);
int ARCH_MemCmp(const void *s1, const void *s2, uint32_t n);

6
drivers/soc/bl808/bl808_std/include/bl808_ef_cfg.h
View file

@ -1,6 +1,6 @@
/**
******************************************************************************
* @file bl808_ef_ctrl.h
* @file bl808_ef_cfg.h
* @version V1.0
* @date
* @brief This file is the standard driver header file
@ -36,7 +36,7 @@
#ifndef __BL808_EF_CFG_H__
#define __BL808_EF_CFG_H__
#include "ef_ctrl_reg.h"
#include "bflb_ef_ctrl.h"
#include "bl808_common.h"
/** @addtogroup BL808_Peripheral_Driver
@ -58,7 +58,7 @@ typedef struct
{
uint8_t chipInfo; /*!< Efuse chip revision */
uint8_t memoryInfo; /*!< Efuse memory info 0:no memory, 8:1MB flash */
uint8_t psramInfo; /*!< Efuse psram info 0:no psram, 1:WB 4MB, 2:UHS 32MB, 3:UHS 64MB, 4:WB 32MB */
uint8_t psramInfo; /*!< Efuse psram info 0:no psram, 1:WB 4MB, 2:UHS 32MB, 3:UHS 64MB, 4:WB 32MB, 5:WB 16MB */
uint8_t deviceInfo; /*!< Efuse device information */
} bflb_efuse_device_info_type;

2
drivers/soc/bl808/bl808_std/src/bl808_aon.c
View file

@ -338,7 +338,7 @@ BL_Err_Type ATTR_CLOCK_SECTION AON_Trim_USB20_RCAL(void)
Efuse_Ana_USB20RCAL_Trim_Type trim;
uint32_t tmpVal = 0;
EF_Ctrl_Read_USB20RCAL_Trim(&trim);
//EF_Ctrl_Read_USB20RCAL_Trim(&trim); //FixZc
if (trim.trimUsb20rcalAonEn) {
if (trim.trimUsb20rcalAonParity == EF_Ctrl_Get_Trim_Parity(trim.trimUsb20rcalAon, 6)) {
tmpVal = BL_RD_REG(AON_BASE, AON_PSW_IRRCV);

398
drivers/soc/bl808/bl808_std/src/bl808_ef_cfg.c
View file

@ -33,24 +33,13 @@
*
******************************************************************************
*/
#include "string.h"
#include "bflb_ef_ctrl.h"
#include "bl808_ef_cfg.h"
#include "hardware/ef_data_0_reg.h"
#include "hardware/ef_data_1_reg.h"
/** @addtogroup BL808_Peripheral_Driver
* @{
*/
extern int bflb_efuse_read_mac_address_opt(uint8_t slot, uint8_t mac[6], uint8_t reload);
/** @addtogroup SEC_EF_CTRL
* @{
*/
/** @defgroup SEC_EF_CTRL_Private_Macros
* @{
*/
static const bflb_ef_ctrl_com_trim_cfg trim_list[] = {
static const bflb_ef_ctrl_com_trim_cfg_t trim_list[] = {
{
.name = "rc32m",
.en_addr = 0x78 * 8 + 1,
@ -78,118 +67,58 @@ static const bflb_ef_ctrl_com_trim_cfg trim_list[] = {
.parity_addr = 0xF0 * 8 + 12,
.value_addr = 0xF0 * 8 + 0,
.value_len = 12,
}
},
{
.name = "usb20",
.en_addr = 0xF8 * 8 + 15,
.parity_addr = 0xF8 * 8 + 14,
.value_addr = 0xF8 * 8 + 8,
.value_len = 6,
},
{
.name = "dcdc11_trim",
.en_addr = 0x78 * 8 + 31,
.parity_addr = 0x78 * 8 + 30,
.value_addr = 0x78 * 8 + 26,
.value_len = 4,
},
{
.name = "dcdc18_trim",
.en_addr = 0x78 * 8 + 25,
.parity_addr = 0x78 * 8 + 24,
.value_addr = 0x78 * 8 + 20,
.value_len = 4,
},
{
.name = "ldo28cis_trim",
.en_addr = 0x78 * 8 + 13,
.parity_addr = 0x78 * 8 + 12,
.value_addr = 0x78 * 8 + 8,
.value_len = 4,
},
{
.name = "ldo15cis_trim",
.en_addr = 0x78 * 8 + 13,
.parity_addr = 0x78 * 8 + 12,
.value_addr = 0x78 * 8 + 8,
.value_len = 4,
},
{
.name = "ldo18flash_trim",
.en_addr = 0xEC * 8 + 31,
.parity_addr = 0xEC * 8 + 30,
.value_addr = 0xEC * 8 + 26,
.value_len = 4,
},
{
.name = "ldo12uhs_trim",
.en_addr = 0xEC * 8 + 25,
.parity_addr = 0xEC * 8 + 24,
.value_addr = 0xEC * 8 + 20,
.value_len = 4,
},
};
#define EF_DATA_EF_CFG_0_OFFSET (0x0)
/* 0x14 : ef_wifi_mac_low */
#define EF_DATA_EF_WIFI_MAC_LOW_OFFSET (0x14)
/* 0x18 : ef_wifi_mac_high */
#define EF_DATA_EF_WIFI_MAC_HIGH_OFFSET (0x18)
/* 0x1C : ef_key_slot_0_w0 */
#define EF_DATA_EF_KEY_SLOT_0_W0_OFFSET (0x1C)
/* 0x20 : ef_key_slot_0_w1 */
#define EF_DATA_EF_KEY_SLOT_0_W1_OFFSET (0x20)
/* 0x24 : ef_key_slot_0_w2 */
#define EF_DATA_EF_KEY_SLOT_0_W2_OFFSET (0x24)
/* 0x28 : ef_key_slot_0_w3 */
#define EF_DATA_EF_KEY_SLOT_0_W3_OFFSET (0x28)
/* 0x2C : ef_key_slot_1_w0 */
#define EF_DATA_EF_KEY_SLOT_1_W0_OFFSET (0x2C)
/* 0x30 : ef_key_slot_1_w1 */
#define EF_DATA_EF_KEY_SLOT_1_W1_OFFSET (0x30)
/* 0x34 : ef_key_slot_1_w2 */
#define EF_DATA_EF_KEY_SLOT_1_W2_OFFSET (0x34)
/* 0x38 : ef_key_slot_1_w3 */
#define EF_DATA_EF_KEY_SLOT_1_W3_OFFSET (0x38)
/* 0x3C : ef_key_slot_2_w0 */
#define EF_DATA_EF_KEY_SLOT_2_W0_OFFSET (0x3C)
/* 0x40 : ef_key_slot_2_w1 */
#define EF_DATA_EF_KEY_SLOT_2_W1_OFFSET (0x40)
/* 0x44 : ef_key_slot_2_w2 */
#define EF_DATA_EF_KEY_SLOT_2_W2_OFFSET (0x44)
/* 0x48 : ef_key_slot_2_w3 */
#define EF_DATA_EF_KEY_SLOT_2_W3_OFFSET (0x48)
/* 0x4C : ef_key_slot_3_w0 */
#define EF_DATA_EF_KEY_SLOT_3_W0_OFFSET (0x4C)
/* 0x50 : ef_key_slot_3_w1 */
#define EF_DATA_EF_KEY_SLOT_3_W1_OFFSET (0x50)
/* 0x54 : ef_key_slot_3_w2 */
#define EF_DATA_EF_KEY_SLOT_3_W2_OFFSET (0x54)
/* 0x58 : ef_key_slot_3_w3 */
#define EF_DATA_EF_KEY_SLOT_3_W3_OFFSET (0x58)
/* 0x5C : ef_sw_usage_0 */
#define EF_DATA_EF_SW_USAGE_0_OFFSET (0x5C)
/* 0x60 : ef_sw_usage_1 */
#define EF_DATA_EF_SW_USAGE_1_OFFSET (0x60)
/* 0x64 : ef_sw_usage_2 */
#define EF_DATA_EF_SW_USAGE_2_OFFSET (0x64)
/* 0x68 : ef_sw_usage_3 */
#define EF_DATA_EF_SW_USAGE_3_OFFSET (0x68)
/* 0x6C : ef_key_slot_11_w0 */
#define EF_DATA_EF_KEY_SLOT_11_W0_OFFSET (0x6C)
/* 0x70 : ef_key_slot_11_w1 */
#define EF_DATA_EF_KEY_SLOT_11_W1_OFFSET (0x70)
/* 0x74 : ef_key_slot_11_w2 */
#define EF_DATA_EF_KEY_SLOT_11_W2_OFFSET (0x74)
/* 0x78 : ef_key_slot_11_w3 */
#define EF_DATA_EF_KEY_SLOT_11_W3_OFFSET (0x78)
/*@} end of group SEC_EF_CTRL_Private_Macros */
/** @defgroup SEC_EF_CTRL_Private_Types
* @{
*/
/*@} end of group SEC_EF_CTRL_Private_Types */
/** @defgroup SEC_EF_CTRL_Private_Variables
* @{
*/
/*@} end of group SEC_EF_CTRL_Private_Variables */
/** @defgroup SEC_EF_CTRL_Global_Variables
* @{
*/
/*@} end of group SEC_EF_CTRL_Global_Variables */
/** @defgroup SEC_EF_CTRL_Private_Fun_Declaration
* @{
*/
/*@} end of group SEC_EF_CTRL_Private_Fun_Declaration */
/** @defgroup SEC_EF_CTRL_Private_Functions
* @{
*/
/****************************************************************************/ /**
* @brief Efuse read device info
*
* @param deviceInfo: info pointer
*
* @return None
*
*******************************************************************************/
void bflb_ef_ctrl_get_device_info(bflb_efuse_device_info_type *chipInfo)
{
uint32_t tmpval;
//tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_HIGH);
bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_WIFI_MAC_HIGH_OFFSET, &tmpval, 1, 1);
chipInfo->chipInfo = (tmpval >> 29) & 0x7;
chipInfo->memoryInfo = (tmpval >> 27) & 0x3;
chipInfo->psramInfo = (tmpval >> 25) & 0x3;
chipInfo->deviceInfo = (tmpval >> 22) & 0x7;
bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_CFG_0_OFFSET, &tmpval, 1, 1);
chipInfo->psramInfo |= ((tmpval >> 20) & 0x1) << 2;
}
/****************************************************************************/ /**
* @brief Efuse get trim list
*
@ -198,12 +127,44 @@ void bflb_ef_ctrl_get_device_info(bflb_efuse_device_info_type *chipInfo)
* @return Trim list count
*
*******************************************************************************/
uint32_t bflb_ef_ctrl_get_common_trim_list(const bflb_ef_ctrl_com_trim_cfg **ptrim_list)
uint32_t bflb_ef_ctrl_get_common_trim_list(const bflb_ef_ctrl_com_trim_cfg_t **ptrim_list)
{
*ptrim_list = &trim_list[0];
return sizeof(trim_list) / sizeof(trim_list[0]);
}
/****************************************************************************/ /**
* @brief Efuse read device info
*
* @param deviceInfo: info pointer
*
* @return None
*
*******************************************************************************/
void bflb_ef_ctrl_get_device_info(bflb_efuse_device_info_type *deviceInfo)
{
uint32_t tmpval;
//tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_HIGH);
bflb_ef_ctrl_read_direct(NULL, EF_DATA_0_EF_WIFI_MAC_HIGH_OFFSET, &tmpval, 1, 1);
deviceInfo->chipInfo = (tmpval >> 29) & 0x7;
deviceInfo->memoryInfo = (tmpval >> 27) & 0x3;
deviceInfo->psramInfo = (tmpval >> 25) & 0x3;
deviceInfo->deviceInfo = (tmpval >> 22) & 0x7;
bflb_ef_ctrl_read_direct(NULL, EF_DATA_0_EF_CFG_0_OFFSET, &tmpval, 1, 1);
deviceInfo->psramInfo |= ((tmpval >> 20) & 0x1) << 2;
}
void bflb_efuse_get_chipid(uint8_t chipid[8])
{
bflb_efuse_read_mac_address_opt(0, chipid, 1);
chipid[6] = 0;
chipid[7] = 0;
}
/****************************************************************************/ /**
* @brief Whether MAC address slot is empty
*
@ -213,26 +174,25 @@ uint32_t bflb_ef_ctrl_get_common_trim_list(const bflb_ef_ctrl_com_trim_cfg **ptr
* @return 0 for all slots full,1 for others
*
*******************************************************************************/
uint8_t EF_Ctrl_Is_MAC_Address_Slot_Empty(uint8_t slot, uint8_t reload)
uint8_t bflb_efuse_is_mac_address_slot_empty(uint8_t slot, uint8_t reload)
{
uint32_t part1Empty = 0, part2Empty = 0;
#if 0
uint32_t tmp1 = 0xffffffff, tmp2 = 0xffffffff;
uint32_t part1Empty = 0, part2Empty = 0;
if (slot == 0) {
bflb_ef_ctrl_read_direct(NULL,EF_DATA_EF_WIFI_MAC_LOW_OFFSET,&tmp1,1,reload);
bflb_ef_ctrl_read_direct(NULL,EF_DATA_EF_WIFI_MAC_HIGH_OFFSET,&tmp2,1,reload);
bflb_ef_ctrl_read_direct(NULL, EF_DATA_0_EF_WIFI_MAC_LOW_OFFSET, &tmp1, 1, reload);
bflb_ef_ctrl_read_direct(NULL, EF_DATA_0_EF_WIFI_MAC_HIGH_OFFSET, &tmp2, 1, reload);
} else if (slot == 1) {
bflb_ef_ctrl_read_direct(NULL,EF_DATA_EF_SW_USAGE_2_OFFSET,&tmp1,1,reload);
bflb_ef_ctrl_read_direct(NULL,EF_DATA_EF_SW_USAGE_3_OFFSET,&tmp2,1,reload);
bflb_ef_ctrl_read_direct(NULL, EF_DATA_0_EF_SW_USAGE_2_OFFSET, &tmp1, 1, reload);
bflb_ef_ctrl_read_direct(NULL, EF_DATA_0_EF_SW_USAGE_3_OFFSET, &tmp2, 1, reload);
} else if (slot == 2) {
bflb_ef_ctrl_read_direct(NULL,EF_DATA_EF_KEY_SLOT_11_W1_OFFSET,&tmp1,1,reload);
bflb_ef_ctrl_read_direct(NULL,EF_DATA_EF_KEY_SLOT_11_W2_OFFSET,&tmp2,1,reload);
bflb_ef_ctrl_read_direct(NULL, EF_DATA_0_EF_KEY_SLOT_11_W1_OFFSET, &tmp1, 1, reload);
bflb_ef_ctrl_read_direct(NULL, EF_DATA_0_EF_KEY_SLOT_11_W2_OFFSET, &tmp2, 1, reload);
}
part1Empty = (bflb_ef_ctrl_is_all_bits_zero(tmp1, 0, 32));
part2Empty = (bflb_ef_ctrl_is_all_bits_zero(tmp2, 0, 22));
#endif
return (part1Empty && part2Empty);
}
@ -243,19 +203,18 @@ uint8_t EF_Ctrl_Is_MAC_Address_Slot_Empty(uint8_t slot, uint8_t reload)
* @param mac[6]: MAC address buffer
* @param program: Whether program
*
* @return SUCCESS or ERROR
* @return 0 or -1
*
*******************************************************************************/
BL_Err_Type EF_Ctrl_Write_MAC_Address_Opt(uint8_t slot, uint8_t mac[6], uint8_t program)
int bflb_efuse_write_mac_address_opt(uint8_t slot, uint8_t mac[6], uint8_t program)
{
#if 0
uint8_t *maclow = (uint8_t *)mac;
uint8_t *machigh = (uint8_t *)(mac + 4);
uint32_t tmpval;
uint32_t i = 0, cnt;
if (slot >= 3) {
return ERROR;
return -1;
}
/* Change to local order */
@ -266,14 +225,14 @@ BL_Err_Type EF_Ctrl_Write_MAC_Address_Opt(uint8_t slot, uint8_t mac[6], uint8_t
}
/* The low 32 bits */
tmpval=BL_RDWD_FRM_BYTEP(maclow);
tmpval = BL_RDWD_FRM_BYTEP(maclow);
if (slot == 0) {
bflb_ef_ctrl_write_direct(NULL,EF_DATA_EF_WIFI_MAC_LOW_OFFSET,&tmpval,1,program);
bflb_ef_ctrl_write_direct(NULL, EF_DATA_0_EF_WIFI_MAC_LOW_OFFSET, &tmpval, 1, program);
} else if (slot == 1) {
bflb_ef_ctrl_write_direct(NULL,EF_DATA_EF_SW_USAGE_2_OFFSET,&tmpval,1,program);
bflb_ef_ctrl_write_direct(NULL, EF_DATA_0_EF_SW_USAGE_2_OFFSET, &tmpval, 1, program);
} else if (slot == 2) {
bflb_ef_ctrl_write_direct(NULL,EF_DATA_EF_KEY_SLOT_11_W1_OFFSET,&tmpval,1,program);
bflb_ef_ctrl_write_direct(NULL, EF_DATA_0_EF_KEY_SLOT_11_W1_OFFSET, &tmpval, 1, program);
}
/* The high 16 bits */
@ -287,14 +246,14 @@ BL_Err_Type EF_Ctrl_Write_MAC_Address_Opt(uint8_t slot, uint8_t mac[6], uint8_t
tmpval |= ((cnt & 0x3f) << 16);
if (slot == 0) {
bflb_ef_ctrl_write_direct(NULL,EF_DATA_EF_WIFI_MAC_HIGH_OFFSET,&tmpval,1,program);
bflb_ef_ctrl_write_direct(NULL, EF_DATA_0_EF_WIFI_MAC_HIGH_OFFSET, &tmpval, 1, program);
} else if (slot == 1) {
bflb_ef_ctrl_write_direct(NULL,EF_DATA_EF_SW_USAGE_3_OFFSET,&tmpval,1,program);
bflb_ef_ctrl_write_direct(NULL, EF_DATA_0_EF_SW_USAGE_3_OFFSET, &tmpval, 1, program);
} else if (slot == 2) {
bflb_ef_ctrl_write_direct(NULL,EF_DATA_EF_KEY_SLOT_11_W2_OFFSET,&tmpval,1,program);
bflb_ef_ctrl_write_direct(NULL, EF_DATA_0_EF_KEY_SLOT_11_W2_OFFSET, &tmpval, 1, program);
}
#endif
return SUCCESS;
return 0;
}
/****************************************************************************/ /**
@ -304,12 +263,11 @@ BL_Err_Type EF_Ctrl_Write_MAC_Address_Opt(uint8_t slot, uint8_t mac[6], uint8_t
* @param mac[6]: MAC address buffer
* @param reload: Whether reload
*
* @return SUCCESS or ERROR
* @return 0 or -1
*
*******************************************************************************/
BL_Err_Type EF_Ctrl_Read_MAC_Address_Opt(uint8_t slot, uint8_t mac[6], uint8_t reload)
int bflb_efuse_read_mac_address_opt(uint8_t slot, uint8_t mac[6], uint8_t reload)
{
#if 0
uint8_t *maclow = (uint8_t *)mac;
uint8_t *machigh = (uint8_t *)(mac + 4);
uint32_t tmpval = 0;
@ -317,25 +275,25 @@ BL_Err_Type EF_Ctrl_Read_MAC_Address_Opt(uint8_t slot, uint8_t mac[6], uint8_t r
uint32_t cnt = 0;
if (slot >= 3) {
return ERROR;
return -1;
}
if (slot == 0) {
bflb_ef_ctrl_read_direct(NULL,EF_DATA_EF_WIFI_MAC_LOW_OFFSET,&tmpval,1,reload);
bflb_ef_ctrl_read_direct(NULL, EF_DATA_0_EF_WIFI_MAC_LOW_OFFSET, &tmpval, 1, reload);
} else if (slot == 1) {
bflb_ef_ctrl_read_direct(NULL,EF_DATA_EF_SW_USAGE_2_OFFSET,&tmpval,1,reload);
bflb_ef_ctrl_read_direct(NULL, EF_DATA_0_EF_SW_USAGE_2_OFFSET, &tmpval, 1, reload);
} else if (slot == 2) {
bflb_ef_ctrl_read_direct(NULL,EF_DATA_EF_KEY_SLOT_11_W1_OFFSET,&tmpval,1,reload);
bflb_ef_ctrl_read_direct(NULL, EF_DATA_0_EF_KEY_SLOT_11_W1_OFFSET, &tmpval, 1, reload);
}
BL_WRWD_TO_BYTEP(maclow, tmpval);
if (slot == 0) {
bflb_ef_ctrl_read_direct(NULL,EF_DATA_EF_WIFI_MAC_HIGH_OFFSET,&tmpval,1,reload);
bflb_ef_ctrl_read_direct(NULL, EF_DATA_0_EF_WIFI_MAC_HIGH_OFFSET, &tmpval, 1, reload);
} else if (slot == 1) {
bflb_ef_ctrl_read_direct(NULL,EF_DATA_EF_SW_USAGE_3_OFFSET,&tmpval,1,reload);
bflb_ef_ctrl_read_direct(NULL, EF_DATA_0_EF_SW_USAGE_3_OFFSET, &tmpval, 1, reload);
} else if (slot == 2) {
bflb_ef_ctrl_read_direct(NULL,EF_DATA_EF_KEY_SLOT_11_W2_OFFSET,&tmpval,1,reload);
bflb_ef_ctrl_read_direct(NULL, EF_DATA_0_EF_KEY_SLOT_11_W2_OFFSET, &tmpval, 1, reload);
}
machigh[0] = tmpval & 0xff;
@ -353,16 +311,124 @@ BL_Err_Type EF_Ctrl_Read_MAC_Address_Opt(uint8_t slot, uint8_t mac[6], uint8_t r
mac[i] = mac[5 - i];
mac[5 - i] = tmpval;
}
return SUCCESS;
return 0;
} else {
return ERROR;
return -1;
}
#endif
return SUCCESS;
}
/*@} end of group SEC_EF_CTRL_Public_Functions */
float bflb_efuse_get_adc_trim(void)
{
bflb_ef_ctrl_com_trim_t trim;
uint32_t tmp;
/*@} end of group SEC_EF_CTRL */
float coe = 1.0;
/*@} end of group BL808_Peripheral_Driver */
bflb_ef_ctrl_read_common_trim(NULL, "gpadc_gain", &trim, 1);
if (trim.en) {
if (trim.parity == bflb_ef_ctrl_get_trim_parity(trim.value, trim.len)) {
tmp = trim.value;
if (tmp & 0x800) {
tmp = ~tmp;
tmp += 1;
tmp = tmp & 0xfff;
coe = (1.0 + ((float)tmp / 2048.0));
} else {
coe = (1.0 - ((float)tmp / 2048.0));
}
}
}
return coe;
}
uint32_t bflb_efuse_get_adc_tsen_trim(void)
{
bflb_ef_ctrl_com_trim_t trim;
bflb_ef_ctrl_read_common_trim(NULL, "tsen", &trim, 1);
if (trim.en) {
if (trim.parity == bflb_ef_ctrl_get_trim_parity(trim.value, trim.len)) {
return trim.value;
}
}
return 2042;
}
void bflb_efuse_read_secure_boot(uint8_t *sign, uint8_t *aes)
{
uint32_t tmpval = 0;
bflb_ef_ctrl_read_direct(NULL, EF_DATA_0_EF_CFG_0_OFFSET, &tmpval, 1, 1);
*sign = ((tmpval & EF_DATA_0_EF_SBOOT_SIGN_MODE_MSK) >> EF_DATA_0_EF_SBOOT_SIGN_MODE_POS) & 0x01;
*aes = ((tmpval & EF_DATA_0_EF_SF_AES_MODE_MSK) >> EF_DATA_0_EF_SF_AES_MODE_POS);
}
void bflb_efuse_write_aes_key(uint8_t index, uint8_t *data, uint32_t len)
{
if ((index <= 3) || (index == 11)) {
index = ((index == 11) ? 5 : index);
/* Every key is 4 words len*/
bflb_ef_ctrl_write_direct(NULL, 0x1C + index * 4, (uint32_t *)data, len, 1);
} else if ((index < 11) && (index > 3)) {
index = index - 4;
/* Every key is 4 words len*/
bflb_ef_ctrl_write_direct(NULL, 0x80 + index * 4, (uint32_t *)data, len, 1);
}
}
void bflb_efuse_read_aes_key(uint8_t index, uint8_t *data, uint32_t len)
{
if ((index <= 3) || (index == 11)) {
index = ((index == 11) ? 5 : index);
/* Every key is 4 words len*/
bflb_ef_ctrl_read_direct(NULL, 0x1C + index * 4, (uint32_t *)data, len, 1);
} else if ((index < 11) && (index > 3)) {
index = index - 4;
/* Every key is 4 words len*/
bflb_ef_ctrl_read_direct(NULL, 0x80 + index * 4, (uint32_t *)data, len, 1);
}
}
void bflb_efuse_lock_aes_key_write(uint8_t index)
{
uint32_t lock = 0;
if ((index <= 3) || (index == 11)) {
index = ((index == 11) ? 8 : index);
lock |= (1 << (index + 17));
bflb_ef_ctrl_write_direct(NULL, 0x7c, (uint32_t *)&lock, 1, 1);
} else if ((index < 11) && (index > 3)) {
index = index - 4;
lock |= (1 << (index + 15));
bflb_ef_ctrl_write_direct(NULL, 0xfc, (uint32_t *)&lock, 1, 1);
}
}
void bflb_efuse_lock_aes_key_read(uint8_t index)
{
uint32_t lock = 0;
if ((index <= 3) || (index == 11)) {
index = ((index == 11) ? 4 : index);
lock |= (1 << (index + 27));
bflb_ef_ctrl_write_direct(NULL, 0x7c, (uint32_t *)lock, 1, 1);
} else if ((index < 11) && (index > 3)) {
index = index - 4;
lock |= (1 << (index + 25));
bflb_ef_ctrl_write_direct(NULL, 0xfc, (uint32_t *)lock, 1, 1);
}
}
void bflb_efuse_write_sw_usage(uint32_t index, uint32_t usage, uint8_t program)
{
bflb_ef_ctrl_write_direct(NULL, EF_DATA_0_EF_SW_USAGE_0_OFFSET + index * 4, &usage, 1, program);
}
void bflb_efuse_read_sw_usage(uint32_t index, uint32_t *usage)
{
bflb_ef_ctrl_read_direct(NULL, EF_DATA_0_EF_SW_USAGE_0_OFFSET + index * 4, (uint32_t *)usage, 1, 1);
}

955
drivers/soc/bl808/bl808_std/src/bl808_glb_gpio.c Normal file
View file

@ -0,0 +1,955 @@
/**
******************************************************************************
* @file bl808_glb_gpio.c
* @version V1.0
* @date
* @brief This file is the standard driver c file
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#include "bl808_clock.h"
#include "bl808_glb.h"
#include "bl808_hbn.h"
#include "bl808_pds.h"
#include "bl808_glb_gpio.h"
/** @addtogroup BL808_Peripheral_Driver
* @{
*/
/** @addtogroup GLB_GPIO
* @{
*/
/** @defgroup GLB_GPIO_Private_Macros
* @{
*/
#define GLB_GPIO_INT0_NUM (GLB_GPIO_PIN_MAX)
#define GLB_GPIO_INT0_CLEAR_TIMEOUT (32)
/*@} end of group GLB_GPIO_Private_Macros */
#define GLB_GPIO_TIMEOUT_COUNT (320 * 1000)
/** @defgroup GLB_GPIO_Private_Types
* @{
*/
/*@} end of group GLB_GPIO_Private_Types */
/** @defgroup GLB_GPIO_Private_Variables
* @{
*/
#ifndef BFLB_USE_HAL_DRIVER
static intCallback_Type *ATTR_TCM_CONST_SECTION glbGpioInt0CbfArra[GLB_GPIO_INT0_NUM] = { NULL };
static intCallback_Type *ATTR_TCM_CONST_SECTION glbGpioFifoCbfArra[GLB_GPIO_FIFO_INT_ALL] = { NULL };
#endif
/*@} end of group GLB_GPIO_Private_Variables */
/** @defgroup GLB_GPIO_Global_Variables
* @{
*/
/*@} end of group GLB_GPIO_Global_Variables */
/** @defgroup GLB_GPIO_Private_Fun_Declaration
* @{
*/
/*@} end of group GLB_GPIO_Private_Fun_Declaration */
/** @defgroup GLB_GPIO_Private_Functions
* @{
*/
/*@} end of group GLB_GPIO_Private_Functions */
/** @defgroup GLB_GPIO_Public_Functions
* @{
*/
/****************************************************************************/ /**
* @brief GPIO initialization
*
* @param cfg: GPIO configuration
*
* @return SUCCESS or ERROR
*
*******************************************************************************/
BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_Init(GLB_GPIO_Cfg_Type *cfg)
{
uint8_t gpioPin = cfg->gpioPin;
uint32_t gpioCfgAddress;
uint32_t tmpVal;
/* drive strength(drive) = 0 <=> 8.0mA @ 3.3V */
/* drive strength(drive) = 1 <=> 9.6mA @ 3.3V */
/* drive strength(drive) = 2 <=> 11.2mA @ 3.3V */
/* drive strength(drive) = 3 <=> 12.8mA @ 3.3V */
gpioCfgAddress = GLB_BASE + GLB_GPIO_CFG0_OFFSET + (gpioPin << 2);
/* Disable output anyway*/
tmpVal = BL_RD_WORD(gpioCfgAddress);
tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_OE);
BL_WR_WORD(gpioCfgAddress, tmpVal);
/* input/output, pull up/down, drive, smt, function */
tmpVal = BL_RD_WORD(gpioCfgAddress);
if (cfg->gpioMode != GPIO_MODE_ANALOG) {
/* not analog mode */
if (cfg->gpioMode == GPIO_MODE_OUTPUT) {
tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE);
tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_OE);
} else {
tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE);
tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_OE);
}
if (cfg->pullType == GPIO_PULL_UP) {
tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_PU);
tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_PD);
} else if (cfg->pullType == GPIO_PULL_DOWN) {
tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_PU);
tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_PD);
} else {
tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_PU);
tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_PD);
}
if (gpioPin == GLB_GPIO_PIN_40) {
*(uint32_t *)(HBN_BASE + HBN_PAD_CTRL_0_OFFSET) &= ~(1 << 27);
} else if (gpioPin == GLB_GPIO_PIN_41) {
*(uint32_t *)(HBN_BASE + HBN_PAD_CTRL_0_OFFSET) &= ~(1 << 28);
}
} else {
/* analog mode */
/* clear ie && oe */
tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE);
tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_OE);
/* clear pu && pd */
tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_PU);
tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_PD);
}
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_DRV, cfg->drive);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_SMT, cfg->smtCtrl);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_FUNC_SEL, cfg->gpioFun);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_MODE, cfg->outputMode);
BL_WR_WORD(gpioCfgAddress, tmpVal);
return SUCCESS;
}
/****************************************************************************/ /**
* @brief init GPIO function in pin list
*
* @param gpioFun: GPIO pin function
* @param pinList: GPIO pin list
* @param cnt: GPIO pin count
*
* @return SUCCESS or ERROR
*
*******************************************************************************/
BL_Err_Type GLB_GPIO_Func_Init(GLB_GPIO_FUNC_Type gpioFun, GLB_GPIO_Type *pinList, uint8_t cnt)
{
GLB_GPIO_Cfg_Type gpioCfg = {
.gpioPin = GLB_GPIO_PIN_0,
.gpioFun = (uint8_t)gpioFun,
.gpioMode = GPIO_MODE_AF,
.pullType = GPIO_PULL_UP,
.drive = 1,
.smtCtrl = 1
};
if (gpioFun == GPIO_FUN_ANALOG) {
gpioCfg.gpioMode = GPIO_MODE_ANALOG;
}
for (uint8_t i = 0; i < cnt; i++) {
gpioCfg.gpioPin = pinList[i];
GLB_GPIO_Init(&gpioCfg);
}
return SUCCESS;
}
/****************************************************************************/ /**
* @brief GPIO set input function enable
*
* @param gpioPin: GPIO pin
*
* @return SUCCESS or ERROR
*
*******************************************************************************/
BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_Input_Enable(GLB_GPIO_Type gpioPin)
{
uint32_t gpioCfgAddress;
uint32_t tmpVal;
gpioCfgAddress = GLB_BASE + GLB_GPIO_CFG0_OFFSET + (gpioPin << 2);
tmpVal = BL_RD_WORD(gpioCfgAddress);
tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE);
BL_WR_WORD(gpioCfgAddress, tmpVal);
return SUCCESS;
}
/****************************************************************************/ /**
* @brief Embedded flash set input function enable
*
* @param gpioPin: GPIO pin
*
* @return SUCCESS or ERROR
*
*******************************************************************************/
BL_Err_Type ATTR_TCM_SECTION GLB_Embedded_Flash_Pad_Enable(void)
{
uint32_t gpioCfgAddress;
uint32_t tmpVal;
uint32_t gpioPin;
for (gpioPin = 48; gpioPin < 52; gpioPin++) {
gpioCfgAddress = GLB_BASE + GLB_GPIO_CFG0_OFFSET + (gpioPin << 2);
tmpVal = BL_RD_WORD(gpioCfgAddress);
tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE);
BL_WR_WORD(gpioCfgAddress, tmpVal);
}
return SUCCESS;
}
/****************************************************************************/ /**
* @brief GPIO set input function disable
*
* @param gpioPin: GPIO pin
*
* @return SUCCESS or ERROR
*
*******************************************************************************/
BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_Input_Disable(GLB_GPIO_Type gpioPin)
{
uint32_t gpioCfgAddress;
uint32_t tmpVal;
gpioCfgAddress = GLB_BASE + GLB_GPIO_CFG0_OFFSET + (gpioPin << 2);
tmpVal = BL_RD_WORD(gpioCfgAddress);
tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE);
BL_WR_WORD(gpioCfgAddress, tmpVal);
return SUCCESS;
}
/****************************************************************************/ /**
* @brief GPIO set output function enable
*
* @param gpioPin: GPIO pin
*
* @return SUCCESS or ERROR
*
*******************************************************************************/
BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_Output_Enable(GLB_GPIO_Type gpioPin)
{
uint32_t gpioCfgAddress;
uint32_t tmpVal;
gpioCfgAddress = GLB_BASE + GLB_GPIO_CFG0_OFFSET + (gpioPin << 2);
tmpVal = BL_RD_WORD(gpioCfgAddress);
tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_OE);
BL_WR_WORD(gpioCfgAddress, tmpVal);
return SUCCESS;
}
/****************************************************************************/ /**
* @brief GPIO set output function disable
*
* @param gpioPin: GPIO pin
*
* @return SUCCESS or ERROR
*
*******************************************************************************/
BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_Output_Disable(GLB_GPIO_Type gpioPin)
{
uint32_t gpioCfgAddress;
uint32_t tmpVal;
gpioCfgAddress = GLB_BASE + GLB_GPIO_CFG0_OFFSET + (gpioPin << 2);
tmpVal = BL_RD_WORD(gpioCfgAddress);
tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_OE);
BL_WR_WORD(gpioCfgAddress, tmpVal);
return SUCCESS;
}
/****************************************************************************/ /**
* @brief GPIO set High-Z
*
* @param gpioPin: GPIO pin
*
* @return SUCCESS or ERROR
*
*******************************************************************************/
BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_Set_HZ(GLB_GPIO_Type gpioPin)
{
uint32_t gpioCfgAddress;
uint32_t tmpVal;
gpioCfgAddress = GLB_BASE + GLB_GPIO_CFG0_OFFSET + (gpioPin << 2);
/* Disable output anyway*/
tmpVal = BL_RD_WORD(gpioCfgAddress);
tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_OE);
BL_WR_WORD(gpioCfgAddress, tmpVal);
/* ie=0, oe=0, drive=0, smt=0, pu=1 (pull up), pd=0, func=swgpio */
tmpVal = BL_RD_WORD(gpioCfgAddress);
tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE);
tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_OE);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_DRV, 0);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_SMT, 0);
tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_PU); /* pull up */
tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_PD);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_FUNC_SEL, 0xB);
BL_WR_WORD(gpioCfgAddress, tmpVal);
return SUCCESS;
}
/****************************************************************************/ /**
* @brief Get GPIO function
*
* @param gpioPin: GPIO type
*
* @return GPIO function
*
*******************************************************************************/
uint8_t ATTR_TCM_SECTION GLB_GPIO_Get_Fun(GLB_GPIO_Type gpioPin)
{
uint32_t gpioCfgAddress;
uint32_t tmpVal;
gpioCfgAddress = GLB_BASE + GLB_GPIO_CFG0_OFFSET + (gpioPin << 2);
tmpVal = BL_RD_WORD(gpioCfgAddress);
return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_FUNC_SEL);
}
/****************************************************************************/ /**
* @brief Read GPIO
*
* @param gpioPin: GPIO type
*
* @return GPIO value
*
*******************************************************************************/
uint32_t ATTR_TCM_SECTION GLB_GPIO_Read(GLB_GPIO_Type gpioPin)
{
uint32_t gpioCfgAddress;
uint32_t tmpVal;
gpioCfgAddress = GLB_BASE + GLB_GPIO_CFG0_OFFSET + (gpioPin << 2);
tmpVal = BL_RD_WORD(gpioCfgAddress);
return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_I) ? SET : RESET;
}
/****************************************************************************/ /**
* @brief Write GPIO
*
* @param gpioPin: GPIO type
* @param val: GPIO value
*
* @return SUCCESS or ERROR
*
*******************************************************************************/
BL_Err_Type GLB_GPIO_Write(GLB_GPIO_Type gpioPin, uint32_t val)
{
uint32_t gpioCfgAddress;
uint32_t tmpVal;
gpioCfgAddress = GLB_BASE + GLB_GPIO_CFG0_OFFSET + (gpioPin << 2);
tmpVal = BL_RD_WORD(gpioCfgAddress);
if (val) {
tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_O);
} else {
tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_O);
}
BL_WR_WORD(gpioCfgAddress, tmpVal);
return SUCCESS;
}
/****************************************************************************/ /**
* @brief turn GPIO output high
*
* @param gpioPin: GPIO type
*
* @return SUCCESS or ERROR
*
*******************************************************************************/
BL_Err_Type GLB_GPIO_Set(GLB_GPIO_Type gpioPin)
{
if (gpioPin < GLB_GPIO_PIN_32) {
BL_WR_WORD(GLB_BASE + GLB_GPIO_CFG138_OFFSET, 1 << gpioPin);
} else {
BL_WR_WORD(GLB_BASE + GLB_GPIO_CFG139_OFFSET, 1 << (gpioPin - GLB_GPIO_PIN_32));
}
return SUCCESS;
}
/****************************************************************************/ /**
* @brief turn GPIO output low
*
* @param gpioPin: GPIO type
*
* @return SUCCESS or ERROR
*
*******************************************************************************/
BL_Err_Type GLB_GPIO_Clr(GLB_GPIO_Type gpioPin)
{
if (gpioPin < GLB_GPIO_PIN_32) {
BL_WR_WORD(GLB_BASE + GLB_GPIO_CFG140_OFFSET, 1 << gpioPin);
} else {
BL_WR_WORD(GLB_BASE + GLB_GPIO_CFG141_OFFSET, 1 << (gpioPin - GLB_GPIO_PIN_32));
}
return SUCCESS;
}
/****************************************************************************/ /**
* @brief GPIO interrupt initialization
*
* @param intCfg: GPIO interrupt configuration
*
* @return SUCCESS or ERROR
*
*******************************************************************************/
BL_Err_Type GLB_GPIO_Int_Init(GLB_GPIO_INT_Cfg_Type *intCfg)
{
uint32_t gpioCfgAddress;
uint32_t tmpVal;
uint32_t gpioPin = intCfg->gpioPin;
gpioCfgAddress = GLB_BASE + GLB_GPIO_CFG0_OFFSET + (gpioPin << 2);
tmpVal = BL_RD_WORD(gpioCfgAddress);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_INT_MODE_SET, intCfg->trig);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_INT_MASK, intCfg->intMask);
BL_WR_WORD(gpioCfgAddress, tmpVal);
return SUCCESS;
}
/****************************************************************************/ /**
* @brief Set GLB GPIO interrupt mask
*
* @param gpioPin: GPIO type
* @param intMask: GPIO interrupt MASK or UNMASK
*
* @return SUCCESS or ERROR
*
*******************************************************************************/
BL_Err_Type GLB_GPIO_IntMask(GLB_GPIO_Type gpioPin, BL_Mask_Type intMask)
{
uint32_t gpioCfgAddress;
uint32_t tmpVal;
gpioCfgAddress = GLB_BASE + GLB_GPIO_CFG0_OFFSET + (gpioPin << 2);
tmpVal = BL_RD_WORD(gpioCfgAddress);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_INT_MASK, intMask);
BL_WR_WORD(gpioCfgAddress, tmpVal);
return SUCCESS;
}
/****************************************************************************/ /**
* @brief Get GLB GPIO interrupt status
*
* @param gpioPin: GPIO type
*
* @return SET or RESET
*
*******************************************************************************/
BL_Sts_Type GLB_Get_GPIO_IntStatus(GLB_GPIO_Type gpioPin)
{
uint32_t gpioCfgAddress;
gpioCfgAddress = GLB_BASE + GLB_GPIO_CFG0_OFFSET + (gpioPin << 2);
return BL_GET_REG_BITS_VAL(BL_RD_WORD(gpioCfgAddress), GLB_GPIO_0_INT_STAT) ? SET : RESET;
}
/****************************************************************************/ /**
* @brief Clear GLB GPIO interrupt status
*
* @param gpioPin: GPIO type
*
* @return SUCCESS or ERROR
*
*******************************************************************************/
BL_Err_Type GLB_Clr_GPIO_IntStatus(GLB_GPIO_Type gpioPin)
{
uint32_t gpioCfgAddress;
uint32_t tmpVal;
gpioCfgAddress = GLB_BASE + GLB_GPIO_CFG0_OFFSET + (gpioPin << 2);
/* clr=1 */
tmpVal = BL_RD_WORD(gpioCfgAddress);
tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_INT_CLR);
BL_WR_WORD(gpioCfgAddress, tmpVal);
/* clr=0 */
tmpVal = BL_RD_WORD(gpioCfgAddress);
tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_INT_CLR);
BL_WR_WORD(gpioCfgAddress, tmpVal);
return SUCCESS;
}
#ifndef BFLB_USE_HAL_DRIVER
void GPIO_FIFO_IRQHandler(void)
{
uint32_t tmpVal;
tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_CFG143);
if (BL_IS_REG_BIT_SET(tmpVal, GLB_R_GPIO_TX_END_INT) && !BL_IS_REG_BIT_SET(tmpVal, GLB_CR_GPIO_TX_END_MASK)) {
if (glbGpioFifoCbfArra[GLB_GPIO_FIFO_INT_END] != NULL) {
glbGpioFifoCbfArra[GLB_GPIO_FIFO_INT_END]();
}
}
if (BL_IS_REG_BIT_SET(tmpVal, GLB_R_GPIO_TX_FER_INT) && !BL_IS_REG_BIT_SET(tmpVal, GLB_CR_GPIO_TX_FER_MASK)) {
if (glbGpioFifoCbfArra[GLB_GPIO_FIFO_INT_FER] != NULL) {
glbGpioFifoCbfArra[GLB_GPIO_FIFO_INT_FER]();
}
}
if (BL_IS_REG_BIT_SET(tmpVal, GLB_R_GPIO_TX_FIFO_INT) && !BL_IS_REG_BIT_SET(tmpVal, GLB_CR_GPIO_TX_FIFO_MASK)) {
if (glbGpioFifoCbfArra[GLB_GPIO_FIFO_INT_FIFO] != NULL) {
glbGpioFifoCbfArra[GLB_GPIO_FIFO_INT_FIFO]();
}
}
}
#endif
/****************************************************************************/ /**
* @brief GPIO INT0 IRQHandler install
*
* @param None
*
* @return SUCCESS or ERROR
*
*******************************************************************************/
BL_Err_Type GLB_GPIO_INT0_IRQHandler_Install(void)
{
#ifndef BFLB_USE_HAL_DRIVER
Interrupt_Handler_Register(GPIO_INT0_IRQn, GPIO_INT0_IRQHandler);
#endif
return SUCCESS;
}
BL_Err_Type GLB_GPIO_FIFO_IRQHandler_Install(void)
{
#ifndef BFLB_USE_HAL_DRIVER
Interrupt_Handler_Register(GPIO_DMA_IRQn, GPIO_FIFO_IRQHandler);
#endif
return SUCCESS;
}
/****************************************************************************/ /**
* @brief GPIO interrupt IRQ handler callback install
*
* @param gpioPin: GPIO pin type
* @param cbFun: callback function
*
* @return SUCCESS or ERROR
*
*******************************************************************************/
#ifndef BFLB_USE_HAL_DRIVER
BL_Err_Type GLB_GPIO_INT0_Callback_Install(GLB_GPIO_Type gpioPin, intCallback_Type *cbFun)
{
if (gpioPin < GLB_GPIO_PIN_MAX) {
glbGpioInt0CbfArra[gpioPin] = cbFun;
}
return SUCCESS;
}
#endif
#ifndef BFLB_USE_HAL_DRIVER
BL_Err_Type GLB_GPIO_Fifo_Callback_Install(GLB_GPIO_FIFO_INT_Type intType, intCallback_Type *cbFun)
{
/* Check the parameters */
CHECK_PARAM(IS_GLB_GPIO_FIFO_INT_TYPE(intType));
glbGpioFifoCbfArra[intType] = cbFun;
return SUCCESS;
}
#endif
/****************************************************************************/ /**
* @brief GPIO interrupt IRQ handler
*
* @param None
*
* @return None
*
*******************************************************************************/
#ifndef BFLB_USE_HAL_DRIVER
void GPIO_INT0_IRQHandler(void)
{
GLB_GPIO_Type gpioPin;
uint32_t timeOut = 0;
for (gpioPin = GLB_GPIO_PIN_0; gpioPin < GLB_GPIO_PIN_MAX; gpioPin++) {
if (SET == GLB_Get_GPIO_IntStatus(gpioPin)) {
GLB_Clr_GPIO_IntStatus(gpioPin);
/* timeout check */
timeOut = GLB_GPIO_INT0_CLEAR_TIMEOUT;
do {
timeOut--;
} while ((SET == GLB_Get_GPIO_IntStatus(gpioPin)) && timeOut);
if (!timeOut) {
//MSG("WARNING: Clear GPIO interrupt status fail.\r\n");
}
if (glbGpioInt0CbfArra[gpioPin] != NULL) {
/* Call the callback function */
glbGpioInt0CbfArra[gpioPin]();
}
}
}
}
#endif
/****************************************************************************/ /**
* @brief GPIO fifo function initialization
*
* @param cfg: GPIO fifo configuration
*
* @return SUCCESS or ERROR
*
*******************************************************************************/
BL_Err_Type GLB_GPIO_Fifo_Init(GLB_GPIO_FIFO_CFG_Type *cfg)
{
uint32_t tmpVal;
/* Check the parameters */
CHECK_PARAM(IS_GLB_GPIO_FIFO_PHASE_Type(cfg->code0Phase));
CHECK_PARAM(IS_GLB_GPIO_FIFO_PHASE_Type(cfg->code1Phase));
CHECK_PARAM(IS_GLB_GPIO_FIFO_PHASE_Type(cfg->latch));
tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_CFG143);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CR_GPIO_DMA_TX_EN, cfg->fifoDmaEnable);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CR_GPIO_TX_FIFO_TH, cfg->fifoDmaThreshold);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CR_GPIO_DMA_OUT_SEL_LATCH, cfg->latch);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CR_GPIO_DMA_PARK_VALUE, cfg->idle);
tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPIO_TX_FIFO_CLR);
tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_GPIO_TX_END_CLR);
BL_WR_REG(GLB_BASE, GLB_GPIO_CFG143, tmpVal);
tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_CFG142);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CR_CODE0_HIGH_TIME, cfg->code0FirstTime);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CR_CODE1_HIGH_TIME, cfg->code1FirstTime);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CR_CODE_TOTAL_TIME, cfg->codeTotalTime);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CR_INVERT_CODE0_HIGH, cfg->code0Phase);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CR_INVERT_CODE1_HIGH, cfg->code1Phase);
tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CR_GPIO_TX_EN);
BL_WR_REG(GLB_BASE, GLB_GPIO_CFG142, tmpVal);
GLB_GPIO_FIFO_IRQHandler_Install();
return SUCCESS;
}
/****************************************************************************/ /**
* @brief Push data to GPIO fifo
*
* @param data: the pointer of data buffer
* @param len: the len of data buffer
*
* @return SUCCESS or ERROR
*
*******************************************************************************/
BL_Err_Type GLB_GPIO_Fifo_Push(uint16_t *data, uint16_t len)
{
uint32_t txLen = 0;
uint32_t timeoutCnt = GLB_GPIO_TIMEOUT_COUNT;
while (txLen < len) {
if (GLB_GPIO_Fifo_GetCount() > 0) {
BL_WR_REG(GLB_BASE, GLB_GPIO_CFG144, data[txLen++]);
timeoutCnt = GLB_GPIO_TIMEOUT_COUNT;
} else {
timeoutCnt--;
if (timeoutCnt == 0) {
return TIMEOUT;
}
}
}
return SUCCESS;
}
/****************************************************************************/ /**
* @brief Get GPIO fifo available count
*
* @param None
*
* @return The count of available count
*
*******************************************************************************/
uint32_t GLB_GPIO_Fifo_GetCount(void)
{
return BL_GET_REG_BITS_VAL(BL_RD_REG(GLB_BASE, GLB_GPIO_CFG143), GLB_GPIO_TX_FIFO_CNT);
}
/****************************************************************************/ /**
* @brief Clear GPIO fifo
*
* @param None
*
* @return SUCCESS
*
*******************************************************************************/
BL_Err_Type GLB_GPIO_Fifo_Clear(void)
{
BL_WR_REG(GLB_BASE, GLB_GPIO_CFG143, BL_SET_REG_BIT(BL_RD_REG(GLB_BASE, GLB_GPIO_CFG143), GLB_GPIO_TX_FIFO_CLR));
return SUCCESS;
}
/****************************************************************************/ /**
* @brief Mask or Unmask GPIO FIFO Interrupt
*
* @param intType: interrupt type
* @param intMask: MASK or UNMASK
*
* @return SUCCESS or ERROR
*
*******************************************************************************/
BL_Err_Type GLB_GPIO_Fifo_IntMask(GLB_GPIO_FIFO_INT_Type intType, BL_Mask_Type intMask)
{
uint32_t tmpVal;
/* Check the parameters */
CHECK_PARAM(IS_GLB_GPIO_FIFO_INT_TYPE(intType));
CHECK_PARAM(IS_BL_MASK_TYPE(intMask));
tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_CFG143);
/* Mask or unmask certain or all interrupt */
if (MASK == intMask) {
switch (intType) {
case GLB_GPIO_FIFO_INT_FER:
tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CR_GPIO_TX_FER_MASK);
break;
case GLB_GPIO_FIFO_INT_FIFO:
tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CR_GPIO_TX_FIFO_MASK);
break;
case GLB_GPIO_FIFO_INT_END:
tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CR_GPIO_TX_END_MASK);
break;
case GLB_GPIO_FIFO_INT_ALL:
tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CR_GPIO_TX_END_MASK);
tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CR_GPIO_TX_FIFO_MASK);
tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CR_GPIO_TX_FER_MASK);
break;
default:
break;
}
} else {
switch (intType) {
case GLB_GPIO_FIFO_INT_FER:
tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CR_GPIO_TX_FER_MASK);
break;
case GLB_GPIO_FIFO_INT_FIFO:
tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CR_GPIO_TX_FIFO_MASK);
break;
case GLB_GPIO_FIFO_INT_END:
tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CR_GPIO_TX_END_MASK);
break;
case GLB_GPIO_FIFO_INT_ALL:
tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CR_GPIO_TX_END_MASK);
tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CR_GPIO_TX_FIFO_MASK);
tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CR_GPIO_TX_FER_MASK);
break;
default:
break;
}
}
/* Write back */
BL_WR_REG(GLB_BASE, GLB_GPIO_CFG143, tmpVal);
return SUCCESS;
}
/****************************************************************************/ /**
* @brief Clear GPIO fifo interrupt
*
* @param intType: interrupt type
*
* @return SUCCESS or ERROR
*
*******************************************************************************/
BL_Err_Type GLB_GPIO_Fifo_IntClear(GLB_GPIO_FIFO_INT_Type intType)
{
uint32_t tmpVal;
/* Check the parameters */
CHECK_PARAM(IS_GLB_GPIO_FIFO_INT_TYPE(intType));
tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_CFG143);
/* Clear certain or all interrupt */
switch (intType) {
case GLB_GPIO_FIFO_INT_FER:
tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPIO_TX_FIFO_CLR);
break;
case GLB_GPIO_FIFO_INT_FIFO:
//tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPIO_TX_FIFO_CLR);
break;
case GLB_GPIO_FIFO_INT_END:
tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPIO_TX_END_CLR);
break;
case GLB_GPIO_FIFO_INT_ALL:
tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPIO_TX_FIFO_CLR);
tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPIO_TX_END_CLR);
break;
default:
break;
}
/* Write back */
BL_WR_REG(GLB_BASE, GLB_GPIO_CFG143, tmpVal);
return SUCCESS;
}
/****************************************************************************/ /**
* @brief Get GPIO fifo interrupt status
*
* @param intType: interrupt type
*
* @return SUCCESS or ERROR
*
*******************************************************************************/
BL_Sts_Type GLB_GPIO_Fifo_GetIntStatus(GLB_GPIO_FIFO_INT_Type intType)
{
uint32_t tmpVal;
/* Check the parameters */
CHECK_PARAM(IS_GLB_GPIO_FIFO_INT_TYPE(intType));
/* Get certain or all interrupt status */
tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_CFG143);
if (GLB_GPIO_FIFO_INT_ALL == intType) {
if (BL_IS_REG_BIT_SET(tmpVal, GLB_R_GPIO_TX_END_INT) ||
BL_IS_REG_BIT_SET(tmpVal, GLB_R_GPIO_TX_FIFO_INT) ||
BL_IS_REG_BIT_SET(tmpVal, GLB_R_GPIO_TX_FER_INT)) {
return SET;
} else {
return RESET;
}
} else {
switch (intType) {
case GLB_GPIO_FIFO_INT_FER:
return BL_IS_REG_BIT_SET(tmpVal, GLB_R_GPIO_TX_FER_INT);
case GLB_GPIO_FIFO_INT_FIFO:
return BL_IS_REG_BIT_SET(tmpVal, GLB_R_GPIO_TX_FIFO_INT);
case GLB_GPIO_FIFO_INT_END:
return BL_IS_REG_BIT_SET(tmpVal, GLB_R_GPIO_TX_END_INT);
default:
return RESET;
}
}
}
BL_Sts_Type GLB_GPIO_Fifo_Enable(void)
{
uint32_t tmpVal;
tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_CFG142);
tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CR_GPIO_TX_EN);
BL_WR_REG(GLB_BASE, GLB_GPIO_CFG142, tmpVal);
return SUCCESS;
}
BL_Sts_Type GLB_GPIO_Fifo_Disable(void)
{
uint32_t tmpVal;
tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_CFG142);
tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CR_GPIO_TX_EN);
BL_WR_REG(GLB_BASE, GLB_GPIO_CFG142, tmpVal);
return SUCCESS;
}
/*@} end of group GLB_GPIO_Public_Functions */
/*@} end of group GLB_GPIO */
/*@} end of group BL808_Peripheral_Driver */

8
drivers/soc/bl808/bl808_std/src/bl808_sf_cfg.c
View file

@ -1359,14 +1359,14 @@ BL_Err_Type ATTR_TCM_SECTION SF_Cfg_Get_Flash_Cfg_Need_Lock(uint32_t flashID, SP
pCrc = (uint32_t *)(buf + 4 + sizeof(SPI_Flash_Cfg_Type));
if (*pCrc == crc) {
ARCH_MemCpy_Fast(pFlashCfg, (uint8_t *)buf + 4, sizeof(SPI_Flash_Cfg_Type));
arch_memcpy_fast(pFlashCfg, (uint8_t *)buf + 4, sizeof(SPI_Flash_Cfg_Type));
return SUCCESS;
}
}
} else {
for (i = 0; i < sizeof(flashInfos) / sizeof(flashInfos[0]); i++) {
if (flashInfos[i].jedecID == flashID) {
ARCH_MemCpy_Fast(pFlashCfg, flashInfos[i].cfg, sizeof(SPI_Flash_Cfg_Type));
arch_memcpy_fast(pFlashCfg, flashInfos[i].cfg, sizeof(SPI_Flash_Cfg_Type));
return SUCCESS;
}
}
@ -1473,7 +1473,7 @@ uint32_t ATTR_TCM_SECTION SF_Cfg_Flash_Identify(uint8_t callFromFlash, uint8_t f
autoScan = ((flashPinCfg >> 7) & 1);
flashPin = (flashPinCfg & 0x7F);
ARCH_MemCpy_Fast(pFlashCfg, &flashCfg_Winb_16JV, sizeof(SPI_Flash_Cfg_Type));
arch_memcpy_fast(pFlashCfg, &flashCfg_Winb_16JV, sizeof(SPI_Flash_Cfg_Type));
if (callFromFlash == 1) {
stat = XIP_SFlash_State_Save(pFlashCfg, &offset, group, bank);
@ -1521,7 +1521,7 @@ uint32_t ATTR_TCM_SECTION SF_Cfg_Flash_Identify(uint8_t callFromFlash, uint8_t f
for (i = 0; i < sizeof(flashInfos) / sizeof(flashInfos[0]); i++) {
if (flashInfos[i].jedecID == jdecId) {
ARCH_MemCpy_Fast(pFlashCfg, flashInfos[i].cfg, sizeof(SPI_Flash_Cfg_Type));
arch_memcpy_fast(pFlashCfg, flashInfos[i].cfg, sizeof(SPI_Flash_Cfg_Type));
break;
}
}

4
drivers/soc/bl808/bl808_std/src/bl808_sflash.c
View file

@ -2045,7 +2045,7 @@ BL_Err_Type ATTR_TCM_SECTION SFlash_Read(SPI_Flash_Cfg_Type *flashCfg,
}
}
ARCH_MemCpy_Fast(data, flashCtrlBuf, curLen);
arch_memcpy_fast(data, flashCtrlBuf, curLen);
addr += curLen;
i += curLen;
@ -2122,7 +2122,7 @@ BL_Err_Type ATTR_TCM_SECTION SFlash_Program(SPI_Flash_Cfg_Type *flashCfg,
}
/* Prepare command */
ARCH_MemCpy_Fast(flashCtrlBuf, data, curLen);
arch_memcpy_fast(flashCtrlBuf, data, curLen);
if (is32BitsAddr > 0) {
flashCmd.cmdBuf[0] = (cmd << 24) | (addr >> 8);

2
drivers/soc/bl808/bl808_std/src/bl808_xip_sflash.c
View file

@ -421,7 +421,7 @@ BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Read_Via_Cache_Need_Lock(uint32_t addr,
offset = SF_Ctrl_Get_Flash_Image_Offset(group, bank);
SF_Ctrl_Set_Flash_Image_Offset(0, group, bank);
/* Flash read */
ARCH_MemCpy_Fast(data, (void *)(uintptr_t)(addr), len);
arch_memcpy_fast(data, (void *)(uintptr_t)(addr), len);
SF_Ctrl_Set_Flash_Image_Offset(offset, group, bank);
return SUCCESS;

100
drivers/soc/bl808/port/bl808_efuse.c
View file

@ -1,100 +0,0 @@
#include "bflb_efuse.h"
#include "bflb_ef_ctrl.h"
float bflb_efuse_get_adc_trim(void)
{
bflb_ef_ctrl_com_trim_type trim;
uint32_t tmp;
float coe = 1.0;
//EF_Ctrl_Read_ADC_Gain_Trim(&trim);
bflb_ef_ctrl_read_common_trim(NULL, "gpadc_gain", &trim, 1);
if (trim.en) {
if (trim.parity == bflb_ef_ctrl_get_trim_parity(trim.value, trim.len)) {
tmp = trim.value;
if (tmp & 0x800) {
tmp = ~tmp;
tmp += 1;
tmp = tmp & 0xfff;
coe = (1.0 + ((float)tmp / 2048.0));
} else {
coe = (1.0 - ((float)tmp / 2048.0));
}
}
}
return coe;
}
uint32_t bflb_efuse_get_adc_tsen_trim(void)
{
bflb_ef_ctrl_com_trim_type trim;
//EF_Ctrl_Read_TSEN_Trim(&trim);
bflb_ef_ctrl_read_common_trim(NULL, "tsen", &trim, 1);
if (trim.en) {
if (trim.parity == bflb_ef_ctrl_get_trim_parity(trim.value, trim.len)) {
return trim.value;
}
}
return 2042;
}
void bflb_efuse_write_aes_key(uint8_t index, uint8_t *data, uint32_t len)
{
if ((index <= 3) || (index == 11)) {
index = ((index == 11) ? 5 : index);
/* Every key is 4 words len*/
bflb_ef_ctrl_write_direct(NULL, 0x1C + index * 4, (uint32_t *)data, len, 1);
} else if ((index < 11) && (index > 3)) {
index = index - 4;
/* Every key is 4 words len*/
bflb_ef_ctrl_write_direct(NULL, 0x80 + index * 4, (uint32_t *)data, len, 1);
}
}
void bflb_efuse_lock_aes_key_write(uint8_t index)
{
uint32_t lock = 0;
if ((index <= 3) || (index == 11)) {
index = ((index == 11) ? 8 : index);
lock |= (1 << (index + 17));
bflb_ef_ctrl_write_direct(NULL, 0x7c, (uint32_t *)lock, 1, 1);
} else if ((index < 11) && (index > 3)) {
index = index - 4;
lock |= (1 << (index + 15));
bflb_ef_ctrl_write_direct(NULL, 0xfc, (uint32_t *)lock, 1, 1);
}
}
void bflb_efuse_lock_aes_key_read(uint8_t index)
{
uint32_t lock = 0;
if ((index <= 3) || (index == 11)) {
index = ((index == 11) ? 4 : index);
lock |= (1 << (index + 27));
bflb_ef_ctrl_write_direct(NULL, 0x7c, (uint32_t *)lock, 1, 1);
} else if ((index < 11) && (index > 3)) {
index = index - 4;
lock |= (1 << (index + 25));
bflb_ef_ctrl_write_direct(NULL, 0xfc, (uint32_t *)lock, 1, 1);
}
}
void bflb_efuse_read_aes_key(uint8_t index, uint8_t *data, uint32_t len)
{
if ((index <= 3) || (index == 11)) {
index = ((index == 11) ? 5 : index);
/* Every key is 4 words len*/
bflb_ef_ctrl_read_direct(NULL, 0x1C + index * 4, (uint32_t *)data, len, 1);
} else if ((index < 11) && (index > 3)) {
index = index - 4;
/* Every key is 4 words len*/
bflb_ef_ctrl_read_direct(NULL, 0x80 + index * 4, (uint32_t *)data, len, 1);
}
}

133
drivers/soc/bl808/port/bl808_flash.c
View file

@ -4,7 +4,103 @@
#include "bflb_flash.h"
static uint32_t g_jedec_id = 0;
static SPI_Flash_Cfg_Type g_flash_cfg;
static SPI_Flash_Cfg_Type g_flash_cfg = {
.resetCreadCmd = 0xff,
.resetCreadCmdSize = 3,
.mid = 0xc8,
.deBurstWrapCmd = 0x77,
.deBurstWrapCmdDmyClk = 0x3,
.deBurstWrapDataMode = SF_CTRL_DATA_4_LINES,
.deBurstWrapData = 0xF0,
/* reg */
.writeEnableCmd = 0x06,
.wrEnableIndex = 0x00,
.wrEnableBit = 0x01,
.wrEnableReadRegLen = 0x01,
.qeIndex = 1,
.qeBit = 0x01,
.qeWriteRegLen = 0x02,
.qeReadRegLen = 0x1,
.busyIndex = 0,
.busyBit = 0x00,
.busyReadRegLen = 0x1,
.releasePowerDown = 0xab,
.readRegCmd[0] = 0x05,
.readRegCmd[1] = 0x35,
.writeRegCmd[0] = 0x01,
.writeRegCmd[1] = 0x01,
.fastReadQioCmd = 0xeb,
.frQioDmyClk = 16 / 8,
.cReadSupport = 0,
.cReadMode = 0xa0,
.burstWrapCmd = 0x77,
.burstWrapCmdDmyClk = 0x3,
.burstWrapDataMode = SF_CTRL_DATA_4_LINES,
.burstWrapData = 0x40,
/* erase */
.chipEraseCmd = 0xc7,
.sectorEraseCmd = 0x20,
.blk32EraseCmd = 0x52,
.blk64EraseCmd = 0xd8,
/* write */
.pageProgramCmd = 0x02,
.qpageProgramCmd = 0x32,
.qppAddrMode = SF_CTRL_ADDR_1_LINE,
.ioMode = 0x10,
.clkDelay = 0,
.clkInvert = 0x03,
.resetEnCmd = 0x66,
.resetCmd = 0x99,
.cRExit = 0xff,
.wrEnableWriteRegLen = 0x00,
/* id */
.jedecIdCmd = 0x9f,
.jedecIdCmdDmyClk = 0,
.enter32BitsAddrCmd = 0xb7,
.exit32BitsAddrCmd = 0xe9,
.sectorSize = 4,
.pageSize = 256,
/* read */
.fastReadCmd = 0x0b,
.frDmyClk = 8 / 8,
.qpiFastReadCmd = 0x0b,
.qpiFrDmyClk = 8 / 8,
.fastReadDoCmd = 0x3b,
.frDoDmyClk = 8 / 8,
.fastReadDioCmd = 0xbb,
.frDioDmyClk = 0,
.fastReadQoCmd = 0x6b,
.frQoDmyClk = 8 / 8,
.qpiFastReadQioCmd = 0xeb,
.qpiFrQioDmyClk = 16 / 8,
.qpiPageProgramCmd = 0x02,
.writeVregEnableCmd = 0x50,
/* qpi mode */
.enterQpi = 0x38,
.exitQpi = 0xff,
/* AC */
.timeEsector = 500,
.timeE32k = 2000,
.timeE64k = 2000,
.timePagePgm = 5,
.timeCe = 33 * 1000,
.pdDelay = 20,
.qeData = 0,
};
/**
* @brief flash_get_clock_delay
@ -39,6 +135,30 @@ static int flash_get_clock_delay(SPI_Flash_Cfg_Type *cfg)
return 0;
}
/**
* @brief flash_set_cmds
*
* @return int
*/
static int ATTR_TCM_SECTION flash_set_cmds(SPI_Flash_Cfg_Type *p_flash_cfg)
{
SF_Ctrl_Cmds_Cfg cmds_cfg = {
.ackLatency = 1,
.cmdsCoreEn = 1,
.cmdsEn = 1,
.cmdsWrapMode = 1,
.cmdsWrapLen = 9,
};
if ((p_flash_cfg->ioMode & 0x0f) == SF_CTRL_QO_MODE || (p_flash_cfg->ioMode & 0x0f) == SF_CTRL_QIO_MODE) {
cmds_cfg.cmdsWrapMode = 2;
cmds_cfg.cmdsWrapLen = 2;
}
SF_Ctrl_Cmds_Set(&cmds_cfg, 0);
return 0;
}
/**
* @brief flash_set_qspi_enable
*
@ -98,6 +218,7 @@ static int ATTR_TCM_SECTION flash_config_init(SPI_Flash_Cfg_Type *p_flash_cfg, u
}
/* Set flash controler from p_flash_cfg */
flash_set_cmds(p_flash_cfg);
flash_set_qspi_enable(p_flash_cfg);
flash_set_l1c_wrap(p_flash_cfg);
XIP_SFlash_State_Restore(p_flash_cfg, offset, 0, 0);
@ -116,7 +237,6 @@ int ATTR_TCM_SECTION bflb_flash_init(void)
{
int ret = -1;
uint32_t jedec_id = 0;
uintptr_t flag;
jedec_id = GLB_Get_Flash_Id_Value();
if (jedec_id != 0) {
@ -128,15 +248,6 @@ int ATTR_TCM_SECTION bflb_flash_init(void)
}
}
flag = bflb_irq_save();
L1C_ICache_Invalid_All();
SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(0, &g_flash_cfg, 0, 0);
L1C_ICache_Invalid_All();
bflb_irq_restore(flag);
if (g_flash_cfg.mid != 0xff) {
flash_get_clock_delay(&g_flash_cfg);
return 0;
}
ret = flash_config_init(&g_flash_cfg, (uint8_t *)&jedec_id);

1
drivers/soc/bl808/startup/d0/system_bl808.c
View file

@ -38,6 +38,7 @@ void SystemInit(void)
void System_Post_Init(void)
{
csi_dcache_clean();
csi_icache_invalid();
/* fix amr setting */
uintptr_t tmpVal = 0;

1
drivers/soc/bl808/startup/m0/system_bl808.c
View file

@ -113,6 +113,7 @@ void SystemInit(void)
void System_Post_Init(void)
{
csi_dcache_clean();
csi_icache_invalid();
PDS_Power_On_MM_System();
/* make D0 all ram avalable for mcu usage */