mirror of
https://github.com/Fishwaldo/bl_mcu_sdk.git
synced 2025-07-23 05:08:45 +00:00
[feat][bl702_driver] add some api and delete unused api
This commit is contained in:
jzlv
parent
ab8a6561b8
commit
13b4ba91f9
26 changed files with 579 additions and 189 deletions
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@ -41,6 +41,14 @@ enum adc_index_type {
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ADC_MAX_INDEX
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};
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enum ADC_event_type {
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ADC_EVENT_FIFO_READY,
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ADC_EVENT_OVERRUN,
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ADC_EVENT_UNDERRUN,
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ADC_EVEN_INT_POS_SATURATION,
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ADC_EVEN_INT_NEG_SATURATION,
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};
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#define adc_channel_start(dev) device_control(dev, DEVICE_CTRL_ADC_CHANNEL_START, NULL)
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#define adc_channel_stop(dev) device_control(dev, DEVICE_CTRL_ADC_CHANNEL_STOP, NULL)
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#define adc_channel_config(dev, list) device_control(dev, DEVICE_CTRL_ADC_CHANNEL_CONFIG, list)
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@ -84,8 +92,8 @@ typedef enum {
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} adc_clk_div_t;
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typedef enum {
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ADC_VREF_3P2V = 0, /* ADC select 3.2V as reference voltage */
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ADC_VREF_2P0V = 1, /* ADC select 2V as reference voltage */
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ADC_VREF_3V2 = 0, /* ADC select 3.2V as reference voltage */
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ADC_VREF_2V = 1, /* ADC select 2V as reference voltage */
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} adc_vref_t;
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/**
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@ -28,6 +28,23 @@
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#include "bl702_cam.h"
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#include "bl702_config.h"
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#define DEVICE_OFLAG_INT 0x01
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#define DEVICE_OFLAG_POLL 0x02
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enum camera_event_type {
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CAM_EVENT_NORMAL_0, /*!< Interleave mode: normal write interrupt, planar mode:even byte normal write interrupt */
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CAM_EVENT_NORMAL_1, /*!< Interleave mode: no use, planar mode:odd byte normal write interrupt */
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CAM_EVENT_MEMORY_OVERWRITE_0, /*!< Interleave mode: memory overwrite interrupt, planar mode:even byte memory overwrite interrupt */
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CAM_EVENT_MEMORY_OVERWRITE_1, /*!< Interleave mode: no use, planar mode:odd byte memory overwrite interrupt */
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CAM_EVENT_FRAME_OVERWRITE_0, /*!< Interleave mode: frame overwrite interrupt, planar mode:even byte frame overwrite interrupt */
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CAM_EVENT_FRAME_OVERWRITE_1, /*!< Interleave mode: no use, planar mode:odd byte frame overwrite interrupt */
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CAM_EVENT_FIFO_OVERWRITE_0, /*!< Interleave mode: fifo overwrite interrupt, planar mode:even byte fifo overwrite interrupt */
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CAM_EVENT_FIFO_OVERWRITE_1, /*!< Interleave mode: no use, planar mode:odd byte fifo overwrite interrupt */
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CAM_EVENT_VSYNC_CNT_ERROR, /*!< Vsync valid line count non-match interrupt */
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CAM_EVENT_HSYNC_CNT_ERROR, /*!< Hsync valid pixel count non-match interrupt */
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CAM_EVENT_ALL, /*!< All of interrupt */
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};
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typedef enum {
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CAM_AUTO_MODE,
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CAM_MANUAL_MODE,
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@ -61,7 +78,7 @@ typedef struct cam_device {
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uint32_t cam_frame_size1;
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} cam_device_t;
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void cam_init(cam_device_t *cam_cfg);
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void cam_init(cam_device_t *cam_cfg, uint16_t oflag);
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void cam_start(void);
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void cam_stop(void);
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uint8_t cam_get_one_frame_interleave(uint8_t **pic, uint32_t *len);
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@ -70,5 +87,7 @@ void cam_drop_one_frame_interleave(void);
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void cam_drop_one_frame_planar(void);
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void cam_hsync_crop(uint16_t start, uint16_t end);
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void cam_vsync_crop(uint16_t start, uint16_t end);
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void cam_hw_mode_wrap(uint8_t enbale);
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void CAM_Int_Callback_set(CAM_INT_Type intType, intCallback_Type *cbFun);
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#endif
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@ -31,39 +31,30 @@
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#define ROOT_CLOCK_SOURCE_RC_32K 0
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#define ROOT_CLOCK_SOURCE_XTAL_32K 1
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#define ROOT_CLOCK_SOURCE_RC_32M 2
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#define ROOT_CLOCK_SOURCE_RC_32M 2
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#define ROOT_CLOCK_SOURCE_XTAL_32M 3
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#define ROOT_CLOCK_SOURCE_PLL_57P6M 4
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#define ROOT_CLOCK_SOURCE_PLL_96M 5
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#define ROOT_CLOCK_SOURCE_PLL_144M 6
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#define ROOT_CLOCK_SOURCE_XCLK ROOT_CLOCK_SOURCE_XTAL_32M
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#define ROOT_CLOCK_SOURCE_FCLK 7
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#define ROOT_CLOCK_SOURCE_HCLK 7
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#define ROOT_CLOCK_SOURCE_BCLK 8
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#define ROOT_CLOCK_SOURCE_32K_CLK ROOT_CLOCK_SOURCE_RC_32K
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#define ROOT_CLOCK_SOURCE_XCLK ROOT_CLOCK_SOURCE_XTAL_32M
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#define ROOT_CLOCK_SOURCE_FCLK 7
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#define ROOT_CLOCK_SOURCE_BCLK 8
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#define ROOT_CLOCK_SOURCE_AUPLL 9
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#define AUDIO_PLL_CLOCK_12288000_HZ 0x90
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#define AUDIO_PLL_CLOCK_11289600_HZ 0x91
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#define AUDIO_PLL_CLOCK_5644800_HZ 0x92
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#define AUDIO_PLL_CLOCK_24576000_HZ 0x93
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#define AUDIO_PLL_CLOCK_24000000_HZ 0x94
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#define OUTPUT_REF_CLOCK_SOURCE_NONE 0
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#define OUTPUT_REF_CLOCK_SOURCE_I2S 1
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#if (BSP_ROOT_CLOCK_SOURCE > 2) && (BSP_ROOT_CLOCK_SOURCE < 7)
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#define CLOCK_XTAL EXTERNAL_XTAL_32M
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#else
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#define CLOCK_XTAL INTERNAL_XTAL_32M
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#endif
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#define ROOT_CLOCK_SOURCE_AUPLL_12288000_HZ 9
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#define ROOT_CLOCK_SOURCE_AUPLL_11289600_HZ 10
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#define ROOT_CLOCK_SOURCE_AUPLL_5644800_HZ 11
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#define ROOT_CLOCK_SOURCE_AUPLL_24576000_HZ 12
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#define ROOT_CLOCK_SOURCE_AUPLL_24000000_HZ 13
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enum system_clock_type {
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SYSTEM_CLOCK_ROOT_CLOCK = 0,
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SYSTEM_CLOCK_FCLK,
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SYSTEM_CLOCK_BCLK,
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SYSTEM_CLOCK_XCLK,
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SYSTEM_CLOCK_32K_CLK,
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SYSTEM_CLOCK_AUPLL,
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};
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enum peripheral_clock_type {
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@ -29,8 +29,9 @@
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int flash_init(void);
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int flash_read_jedec_id(uint8_t *data);
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BL_Err_Type flash_read_via_xip(uint32_t addr, uint8_t *data, uint32_t len);
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BL_Err_Type flash_read_xip(uint32_t addr, uint8_t *data, uint32_t len);
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BL_Err_Type flash_write_xip(uint32_t addr, uint8_t *data, uint32_t len);
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BL_Err_Type flash_erase_xip(uint32_t startaddr, uint32_t endaddr);
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BL_Err_Type flash_erase_xip(uint32_t startaddr, uint32_t len);
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BL_Err_Type flash_set_cache(uint8_t cont_read, uint8_t cache_enable, uint8_t cache_way_disable, uint32_t flash_offset);
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#endif
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@ -58,12 +58,6 @@ enum gpio_pin_type {
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GPIO_PIN_29,
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GPIO_PIN_30,
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GPIO_PIN_31,
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GPIO_PIN_32,
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GPIO_PIN_33,
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GPIO_PIN_34,
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GPIO_PIN_35,
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GPIO_PIN_36,
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GPIO_PIN_37,
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GPIO_PIN_MAX,
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};
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@ -26,10 +26,8 @@
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#include "drv_device.h"
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#include "bl702_config.h"
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#define I2S_GET_TX_FIFO_CMD 0x10
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#define I2S_GET_RX_FIFO_CMD 0x11
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#define DEVICE_CTRL_I2S_ATTACH_TX_DMA 0x12
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#define DEVICE_CTRL_I2S_ATTACH_RX_DMA 0x13
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#define I2S_GET_TX_FIFO_CMD 0x10
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#define I2S_GET_RX_FIFO_CMD 0x11
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enum i2s_index_type {
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#ifdef BSP_USING_I2S0
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@ -49,9 +49,11 @@ enum pwm_index_type {
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PWM_MAX_INDEX
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};
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#define pwm_channel_start(dev) device_control(dev, DEVICE_CTRL_RESUME, NULL)
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#define pwm_channel_stop(dev) device_control(dev, DEVICE_CTRL_SUSPEND, NULL)
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#define pwm_it_pulse_count_update(dev, count) device_control(dev, DEIVCE_CTRL_PWM_IT_PULSE_COUNT_CONFIG, (void *)count)
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#define pwm_channel_start(dev) device_control(dev, DEVICE_CTRL_RESUME, NULL)
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#define pwm_channel_stop(dev) device_control(dev, DEVICE_CTRL_SUSPEND, NULL)
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#define pwm_channel_freq_update(dev, count) device_control(dev, DEIVCE_CTRL_PWM_FREQUENCE_CONFIG, (void *)count)
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#define pwm_channel_dutycycle_update(dev, cfg) device_control(dev, DEIVCE_CTRL_PWM_DUTYCYCLE_CONFIG, cfg)
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#define pwm_it_pulse_count_update(dev, count) device_control(dev, DEIVCE_CTRL_PWM_IT_PULSE_COUNT_CONFIG, (void *)count)
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enum pwm_event_type {
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PWM_EVENT_COMPLETE,
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@ -102,6 +102,50 @@ int adc_close(struct device *dev)
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ADC_Disable();
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return 0;
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}
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/**
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* @brief Check whether Channel Corresponding IO is configed success by Board System
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*
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* @param pos_list pos channel list
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* @param neg_list negative channel list
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* @param channelNum channel number
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*/
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uint8_t adc_check_channel_status(uint8_t *pos_list, uint8_t *neg_list, uint16_t channelNum)
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{
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uint16_t i = 0;
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uint8_t channel_io_reference_table[] = {
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GPIO_PIN_8, /* CH0 IO */
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GPIO_PIN_15, /* CH1 IO */
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GPIO_PIN_17, /* CH2 IO */
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GPIO_PIN_11, /* CH3 IO */
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GPIO_PIN_12, /* CH4 IO */
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GPIO_PIN_14, /* CH5 IO */
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0xff, /* CH6 IO */
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0xff, /* CH7 IO */
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GPIO_PIN_18, /* CH8 IO */
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GPIO_PIN_19, /* CH9 IO */
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GPIO_PIN_20, /* CH10 IO */
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GPIO_PIN_21, /* CH11 IO */
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};
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for (i = 0; i < channelNum; i++) {
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if (pos_list[i] > ADC_CHANNEL11) {
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continue;
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}
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if (channel_io_reference_table[pos_list[i]] == 0xff) {
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return ERROR;
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}
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if (GLB_GPIO_Get_Fun(channel_io_reference_table[pos_list[i]]) != GPIO_FUN_ANALOG) {
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return ERROR;
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}
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}
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return SUCCESS;
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}
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/**
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* @brief
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*
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@ -114,6 +158,7 @@ int adc_control(struct device *dev, int cmd, void *args)
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{
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adc_device_t *adc_device = (adc_device_t *)dev;
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adc_channel_cfg_t *adc_channel_cfg = (adc_channel_cfg_t *)args;
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uint8_t rlt = 0;
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switch (cmd) {
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case DEVICE_CTRL_SET_INT /* constant-expression */:
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@ -135,8 +180,10 @@ int adc_control(struct device *dev, int cmd, void *args)
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case DEVICE_CTRL_ADC_CHANNEL_CONFIG /* constant-expression */:
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if (adc_channel_cfg->num == 1) {
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ADC_Channel_Config(*adc_channel_cfg->pos_channel, *adc_channel_cfg->neg_channel, adc_device->continuous_conv_mode);
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rlt = adc_check_channel_status(adc_channel_cfg->pos_channel, adc_channel_cfg->neg_channel, 1);
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} else {
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ADC_Scan_Channel_Config(adc_channel_cfg->pos_channel, adc_channel_cfg->neg_channel, adc_channel_cfg->num, adc_device->continuous_conv_mode);
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rlt = adc_check_channel_status(adc_channel_cfg->pos_channel, adc_channel_cfg->neg_channel, adc_channel_cfg->num);
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}
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break;
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@ -171,7 +218,7 @@ int adc_control(struct device *dev, int cmd, void *args)
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break;
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}
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return 0;
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return rlt;
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}
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// int adc_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t size)
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// {
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@ -247,3 +294,45 @@ int adc_register(enum adc_index_type index, const char *name, uint16_t flag)
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return device_register(dev, name, flag);
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}
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/**
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* @brief
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*
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* @param handle
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*/
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void adc_isr(adc_device_t *handle)
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{
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if (!handle->parent.callback)
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return;
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if (ADC_GetIntStatus(ADC_INT_POS_SATURATION) == SET && ADC_IntGetMask(ADC_INT_POS_SATURATION) == UNMASK) {
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ADC_IntClr(ADC_INT_POS_SATURATION);
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handle->parent.callback(&handle->parent, NULL, 0, ADC_INT_POS_SATURATION);
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}
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if (ADC_GetIntStatus(ADC_INT_NEG_SATURATION) == SET && ADC_IntGetMask(ADC_INT_NEG_SATURATION) == UNMASK) {
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ADC_IntClr(ADC_INT_NEG_SATURATION);
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handle->parent.callback(&handle->parent, NULL, 0, ADC_INT_NEG_SATURATION);
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}
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if (ADC_GetIntStatus(ADC_INT_FIFO_UNDERRUN) == SET && ADC_IntGetMask(ADC_INT_FIFO_UNDERRUN) == UNMASK) {
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ADC_IntClr(ADC_INT_FIFO_UNDERRUN);
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handle->parent.callback(&handle->parent, NULL, 0, ADC_INT_FIFO_UNDERRUN);
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}
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if (ADC_GetIntStatus(ADC_INT_FIFO_OVERRUN) == SET && ADC_IntGetMask(ADC_INT_FIFO_OVERRUN) == UNMASK) {
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ADC_IntClr(ADC_INT_FIFO_OVERRUN);
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handle->parent.callback(&handle->parent, NULL, 0, ADC_INT_FIFO_OVERRUN);
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}
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if (ADC_GetIntStatus(ADC_INT_FIFO_READY) == SET && ADC_IntGetMask(ADC_INT_FIFO_READY) == UNMASK) {
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ADC_IntClr(ADC_INT_FIFO_READY);
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handle->parent.callback(&handle->parent, NULL, 0, ADC_INT_FIFO_READY);
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}
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}
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#ifdef BSP_USING_ADC0
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void ADC_IRQ(void)
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{
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adc_isr(&adcx_device[ADC0_INDEX]);
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}
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#endif
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@ -25,12 +25,16 @@
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#include "bl702_glb.h"
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#include "hal_cam.h"
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static intCallback_Type *camIntCbfArra[CAM_INT_ALL] = { NULL };
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void CAMERA_IRQ(void);
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/**
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* @brief
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*
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* @param cam_cfg
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*/
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void cam_init(cam_device_t *cam_cfg)
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void cam_init(cam_device_t *cam_cfg, uint16_t oflag)
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{
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CAM_CFG_Type camera_cfg = {
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.swMode = cam_cfg->software_mode,
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@ -51,6 +55,10 @@ void cam_init(cam_device_t *cam_cfg)
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.frameSize1 = cam_cfg->cam_frame_size1,
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};
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CAM_Init(&camera_cfg);
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if (oflag == DEVICE_OFLAG_INT) {
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Interrupt_Handler_Register(CAM_IRQn, CAMERA_IRQ);
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}
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}
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/**
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@ -138,3 +146,101 @@ void cam_vsync_crop(uint16_t start, uint16_t end)
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{
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CAM_Vsync_Crop(start, end);
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}
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void cam_hw_mode_wrap(uint8_t enable)
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{
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CAM_HW_Mode_Wrap(enable);
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}
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void cam_isr(cam_device_t *handle)
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{
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}
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#ifdef BSP_USING_CAM
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void CAM_Int_Callback_set(CAM_INT_Type intType, intCallback_Type *cbFun)
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{
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/* Check the parameters */
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CHECK_PARAM(IS_CAM_INT_TYPE(intType));
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camIntCbfArra[intType] = cbFun;
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}
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void CAMERA_IRQ(void)
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{
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uint32_t tmpVal;
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tmpVal = BL_RD_REG(CAM_BASE, CAM_DVP_STATUS_AND_ERROR);
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if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_NORMAL_INT_0)) {
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CAM_IntClr(CAM_INT_NORMAL_0);
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if (camIntCbfArra[CAM_INT_NORMAL_0] != NULL) {
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/* call the callback function */
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camIntCbfArra[CAM_INT_NORMAL_0]();
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}
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}
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if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_NORMAL_INT_1)) {
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CAM_IntClr(CAM_INT_NORMAL_1);
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if (camIntCbfArra[CAM_INT_NORMAL_1] != NULL) {
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/* call the callback function */
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camIntCbfArra[CAM_INT_NORMAL_1]();
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}
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}
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if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_MEM_INT_0)) {
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CAM_IntClr(CAM_INT_MEMORY_OVERWRITE_0);
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if (camIntCbfArra[CAM_INT_MEMORY_OVERWRITE_0] != NULL) {
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/* call the callback function */
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camIntCbfArra[CAM_INT_MEMORY_OVERWRITE_0]();
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}
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}
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if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_MEM_INT_1)) {
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CAM_IntClr(CAM_INT_MEMORY_OVERWRITE_1);
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if (camIntCbfArra[CAM_INT_MEMORY_OVERWRITE_1] != NULL) {
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/* call the callback function */
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camIntCbfArra[CAM_INT_MEMORY_OVERWRITE_1]();
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}
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}
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if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_FRAME_INT_0)) {
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CAM_IntClr(CAM_INT_FRAME_OVERWRITE_0);
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if (camIntCbfArra[CAM_INT_FRAME_OVERWRITE_0] != NULL) {
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||||
/* call the callback function */
|
||||
camIntCbfArra[CAM_INT_FRAME_OVERWRITE_0]();
|
||||
}
|
||||
}
|
||||
if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_FRAME_INT_1)) {
|
||||
CAM_IntClr(CAM_INT_FRAME_OVERWRITE_1);
|
||||
if (camIntCbfArra[CAM_INT_FRAME_OVERWRITE_1] != NULL) {
|
||||
/* call the callback function */
|
||||
camIntCbfArra[CAM_INT_FRAME_OVERWRITE_1]();
|
||||
}
|
||||
}
|
||||
if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_FIFO_INT_0)) {
|
||||
CAM_IntClr(CAM_INT_FIFO_OVERWRITE_0);
|
||||
if (camIntCbfArra[CAM_INT_FIFO_OVERWRITE_0] != NULL) {
|
||||
/* call the callback function */
|
||||
camIntCbfArra[CAM_INT_FIFO_OVERWRITE_0]();
|
||||
}
|
||||
}
|
||||
if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_FIFO_INT_1)) {
|
||||
CAM_IntClr(CAM_INT_FIFO_OVERWRITE_1);
|
||||
if (camIntCbfArra[CAM_INT_FIFO_OVERWRITE_1] != NULL) {
|
||||
/* call the callback function */
|
||||
camIntCbfArra[CAM_INT_FIFO_OVERWRITE_1]();
|
||||
}
|
||||
}
|
||||
if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_HCNT_INT)) {
|
||||
CAM_IntClr(CAM_INT_HSYNC_CNT_ERROR);
|
||||
if (camIntCbfArra[CAM_INT_HSYNC_CNT_ERROR] != NULL) {
|
||||
/* call the callback function */
|
||||
camIntCbfArra[CAM_INT_HSYNC_CNT_ERROR]();
|
||||
}
|
||||
}
|
||||
if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_VCNT_INT)) {
|
||||
CAM_IntClr(CAM_INT_VSYNC_CNT_ERROR);
|
||||
if (camIntCbfArra[CAM_INT_VSYNC_CNT_ERROR] != NULL) {
|
||||
/* call the callback function */
|
||||
camIntCbfArra[CAM_INT_VSYNC_CNT_ERROR]();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -36,11 +36,11 @@ void system_clock_init(void)
|
|||
/*select root clock*/
|
||||
GLB_Set_System_CLK(CLOCK_XTAL, BSP_ROOT_CLOCK_SOURCE - 2);
|
||||
/*set fclk/hclk and bclk clock*/
|
||||
GLB_Set_System_CLK_Div(BSP_HCLK_DIV, BSP_BCLK_DIV);
|
||||
GLB_Set_System_CLK_Div(BSP_FCLK_DIV, BSP_BCLK_DIV);
|
||||
/* Set MTimer the same frequency as SystemCoreClock */
|
||||
GLB_Set_MTimer_CLK(1, GLB_MTIMER_CLK_BCLK, mtimer_get_clk_src_div());
|
||||
#ifdef BSP_AUDIO_PLL_CLOCK_SOURCE
|
||||
PDS_Set_Audio_PLL_Freq(BSP_AUDIO_PLL_CLOCK_SOURCE & 0x0f);
|
||||
PDS_Set_Audio_PLL_Freq(BSP_AUDIO_PLL_CLOCK_SOURCE - ROOT_CLOCK_SOURCE_AUPLL_12288000_HZ);
|
||||
#endif
|
||||
}
|
||||
void peripheral_clock_init(void)
|
||||
|
|
@ -77,7 +77,7 @@ void peripheral_clock_init(void)
|
|||
uint32_t timeoutCnt = 160 * 1000;
|
||||
uint32_t tmpVal;
|
||||
uint32_t PWMx;
|
||||
#if BSP_PWM_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_RC_32K
|
||||
#if BSP_PWM_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_32K_CLK
|
||||
|
||||
for (int i = 0; i < 5; i++) {
|
||||
PWMx = PWM_BASE + PWM_CHANNEL_OFFSET + (i)*0x20;
|
||||
|
|
@ -149,26 +149,22 @@ void peripheral_clock_init(void)
|
|||
#if defined(BSP_USING_I2S0)
|
||||
GLB_Set_I2S_CLK(ENABLE, GLB_I2S_OUT_REF_CLK_NONE);
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_ADC0)
|
||||
#if BSP_ADC_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_AUPLL
|
||||
#ifdef BSP_AUDIO_PLL_CLOCK_SOURCE
|
||||
#if BSP_ADC_CLOCK_SOURCE >= ROOT_CLOCK_SOURCE_AUPLL_12288000_HZ
|
||||
GLB_Set_ADC_CLK(ENABLE, GLB_ADC_CLK_AUDIO_PLL, BSP_ADC_CLOCK_DIV);
|
||||
#endif
|
||||
#elif BSP_ADC_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK
|
||||
GLB_Set_ADC_CLK(ENABLE, GLB_ADC_CLK_XCLK, BSP_ADC_CLOCK_DIV);
|
||||
#else
|
||||
#error "please select correct adc clock source"
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_DAC0)
|
||||
#if BSP_ADC_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_AUPLL
|
||||
#ifdef BSP_AUDIO_PLL_CLOCK_SOURCE
|
||||
GLB_Set_DAC_CLK(ENABLE, GLB_ADC_CLK_AUDIO_PLL, BSP_DAC_CLOCK_DIV);
|
||||
#endif
|
||||
#elif BSP_ADC_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK
|
||||
GLB_Set_DAC_CLK(ENABLE, GLB_ADC_CLK_XCLK, BSP_DAC_CLOCK_DIV);
|
||||
#if BSP_DAC_CLOCK_SOURCE >= ROOT_CLOCK_SOURCE_AUPLL_12288000_HZ
|
||||
GLB_Set_DAC_CLK(ENABLE, GLB_DAC_CLK_AUDIO_PLL, BSP_DAC_CLOCK_DIV);
|
||||
#elif BSP_DAC_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK
|
||||
GLB_Set_DAC_CLK(ENABLE, GLB_DAC_CLK_XCLK, BSP_DAC_CLOCK_DIV);
|
||||
#else
|
||||
#error "please select correct dac clock source"
|
||||
#endif
|
||||
|
|
@ -178,8 +174,21 @@ void peripheral_clock_init(void)
|
|||
#if BSP_CAM_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_PLL_96M
|
||||
GLB_Set_CAM_CLK(ENABLE, GLB_CAM_CLK_DLL96M, BSP_CAM_CLOCK_DIV);
|
||||
GLB_SWAP_EMAC_CAM_Pin(GLB_EMAC_CAM_PIN_CAM);
|
||||
#elif BSP_CAM_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK
|
||||
GLB_Set_CAM_CLK(ENABLE, GLB_CAM_CLK_XCLK, BSP_CAM_CLOCK_DIV);
|
||||
GLB_SWAP_EMAC_CAM_Pin(GLB_EMAC_CAM_PIN_CAM);
|
||||
#else
|
||||
#error "please select correct cam clock source"
|
||||
#error "please select correct camera clock source"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_QDEC)
|
||||
#if BSP_QDEC_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_32K_CLK
|
||||
GLB_Set_QDEC_CLK(ENABLE, GLB_QDEC_CLK_F32K, BSP_QDEC_CLOCK_DIV);
|
||||
#elif BSP_QDEC_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK
|
||||
GLB_Set_QDEC_CLK(ENABLE, GLB_QDEC_CLK_XCLK, BSP_QDEC_CLOCK_DIV);
|
||||
#else
|
||||
#error "please select correct qdec clock source"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
|
@ -201,23 +210,20 @@ uint32_t system_clock_get(enum system_clock_type type)
|
|||
|
||||
case SYSTEM_CLOCK_XCLK:
|
||||
return 32000000;
|
||||
|
||||
case SYSTEM_CLOCK_32K_CLK:
|
||||
return 32000;
|
||||
case SYSTEM_CLOCK_AUPLL:
|
||||
#ifdef BSP_AUDIO_PLL_CLOCK_SOURCE
|
||||
if (BSP_AUDIO_PLL_CLOCK_SOURCE == AUDIO_PLL_CLOCK_12288000_HZ) {
|
||||
if (BSP_AUDIO_PLL_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_AUPLL_12288000_HZ) {
|
||||
return 12288000;
|
||||
} else if (BSP_AUDIO_PLL_CLOCK_SOURCE == AUDIO_PLL_CLOCK_11289600_HZ) {
|
||||
} else if (BSP_AUDIO_PLL_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_AUPLL_11289600_HZ) {
|
||||
return 11289600;
|
||||
} else if (BSP_AUDIO_PLL_CLOCK_SOURCE == AUDIO_PLL_CLOCK_5644800_HZ) {
|
||||
} else if (BSP_AUDIO_PLL_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_AUPLL_5644800_HZ) {
|
||||
return 5644800;
|
||||
} else if (BSP_AUDIO_PLL_CLOCK_SOURCE == AUDIO_PLL_CLOCK_24576000_HZ) {
|
||||
} else if (BSP_AUDIO_PLL_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_AUPLL_24576000_HZ) {
|
||||
return 24576000;
|
||||
} else if (BSP_AUDIO_PLL_CLOCK_SOURCE == AUDIO_PLL_CLOCK_24000000_HZ) {
|
||||
} else if (BSP_AUDIO_PLL_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_AUPLL_24000000_HZ) {
|
||||
return 24000000;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
|
@ -258,15 +264,15 @@ uint32_t peripheral_clock_get(enum peripheral_clock_type type)
|
|||
#endif
|
||||
|
||||
case PERIPHERAL_CLOCK_I2S:
|
||||
return 0;
|
||||
return system_clock_get(SYSTEM_CLOCK_AUPLL);
|
||||
|
||||
case PERIPHERAL_CLOCK_ADC:
|
||||
#if defined(BSP_USING_ADC0)
|
||||
#if BSP_ADC_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK
|
||||
tmpVal = BL_RD_REG(GLB_BASE, GLB_GPADC_32M_SRC_CTRL);
|
||||
div = BL_GET_REG_BITS_VAL(tmpVal, GLB_GPADC_32M_CLK_DIV);
|
||||
return 32000000 / div;
|
||||
#elif BSP_ADC_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_AUPLL
|
||||
return system_clock_get(SYSTEM_CLOCK_XCLK) / div;
|
||||
#elif BSP_ADC_CLOCK_SOURCE >= ROOT_CLOCK_SOURCE_AUPLL_12288000_HZ
|
||||
tmpVal = BL_RD_REG(GLB_BASE, GLB_GPADC_32M_SRC_CTRL);
|
||||
div = BL_GET_REG_BITS_VAL(tmpVal, GLB_GPADC_32M_CLK_DIV);
|
||||
return system_clock_get(SYSTEM_CLOCK_AUPLL) / div;
|
||||
|
|
@ -278,8 +284,8 @@ uint32_t peripheral_clock_get(enum peripheral_clock_type type)
|
|||
#if BSP_DAC_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK
|
||||
tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL);
|
||||
div = BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_512K_DIV);
|
||||
return 32000000 / (div + 1);
|
||||
#elif BSP_DAC_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_AUPLL
|
||||
return system_clock_get(SYSTEM_CLOCK_XCLK) / (div + 1);
|
||||
#elif BSP_DAC_CLOCK_SOURCE >= ROOT_CLOCK_SOURCE_AUPLL_12288000_HZ
|
||||
tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL);
|
||||
div = BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_512K_DIV);
|
||||
return system_clock_get(SYSTEM_CLOCK_AUPLL) / div;
|
||||
|
|
@ -288,15 +294,15 @@ uint32_t peripheral_clock_get(enum peripheral_clock_type type)
|
|||
|
||||
case PERIPHERAL_CLOCK_PWM:
|
||||
#if defined(BSP_USING_PWM_CH0) || defined(BSP_USING_PWM_CH1) || defined(BSP_USING_PWM_CH2) || defined(BSP_USING_PWM_CH3) || defined(BSP_USING_PWM_CH4) || defined(BSP_USING_PWM_CH5)
|
||||
#if BSP_PWM_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_RC_32K
|
||||
#if BSP_PWM_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_32K_CLK
|
||||
div = BL_RD_REG(PWM_BASE + PWM_CHANNEL_OFFSET, PWM_CLKDIV);
|
||||
return 32000 / div;
|
||||
return system_clock_get(SYSTEM_CLOCK_32K_CLK) / div;
|
||||
#elif BSP_PWM_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_BCLK
|
||||
div = BL_RD_REG(PWM_BASE + PWM_CHANNEL_OFFSET, PWM_CLKDIV);
|
||||
return system_clock_get(SYSTEM_CLOCK_BCLK) / div;
|
||||
#elif BSP_PWM_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK
|
||||
div = BL_RD_REG(PWM_BASE + PWM_CHANNEL_OFFSET, PWM_CLKDIV);
|
||||
return 32000000 / div;
|
||||
return system_clock_get(SYSTEM_CLOCK_XCLK) / div;
|
||||
#endif
|
||||
#endif
|
||||
break;
|
||||
|
|
@ -307,6 +313,10 @@ uint32_t peripheral_clock_get(enum peripheral_clock_type type)
|
|||
tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG1);
|
||||
div = BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_CAM_REF_CLK_DIV);
|
||||
return (96000000 / (div + 1));
|
||||
#elif BSP_CAM_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK
|
||||
tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG1);
|
||||
div = BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_CAM_REF_CLK_DIV);
|
||||
return (system_clock_get(SYSTEM_CLOCK_XCLK) / (div + 1));
|
||||
#endif
|
||||
#endif
|
||||
break;
|
||||
|
|
|
|||
|
|
@ -58,6 +58,23 @@ int flash_read_jedec_id(uint8_t *data)
|
|||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief read flash data via xip
|
||||
*
|
||||
* @param addr
|
||||
* @param data
|
||||
* @param len
|
||||
* @return BL_Err_Type
|
||||
*/
|
||||
BL_Err_Type flash_read_via_xip(uint32_t addr, uint8_t *data, uint32_t len)
|
||||
{
|
||||
L1C_Cache_Flush(0xf);
|
||||
XIP_SFlash_Read_Via_Cache_Need_Lock(addr, data, len);
|
||||
L1C_Cache_Flush(0x0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief read xip data
|
||||
*
|
||||
|
|
@ -68,10 +85,7 @@ int flash_read_jedec_id(uint8_t *data)
|
|||
*/
|
||||
BL_Err_Type flash_read_xip(uint32_t addr, uint8_t *data, uint32_t len)
|
||||
{
|
||||
BL702_MemCpy_Fast(data,
|
||||
(uint8_t *)(BL702_FLASH_XIP_BASE + addr - SF_Ctrl_Get_Flash_Image_Offset()),
|
||||
len);
|
||||
return 0;
|
||||
return XIP_SFlash_Read_With_Lock(&g_boot2_flash_cfg, g_boot2_flash_cfg.ioMode & 0x0f, addr, data, len);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -94,9 +108,9 @@ BL_Err_Type flash_write_xip(uint32_t addr, uint8_t *data, uint32_t len)
|
|||
* @param endaddr
|
||||
* @return BL_Err_Type
|
||||
*/
|
||||
BL_Err_Type flash_erase_xip(uint32_t startaddr, uint32_t endaddr)
|
||||
BL_Err_Type flash_erase_xip(uint32_t startaddr, uint32_t len)
|
||||
{
|
||||
return XIP_SFlash_Erase_With_Lock(&g_boot2_flash_cfg, g_boot2_flash_cfg.ioMode & 0x0f, startaddr, endaddr - startaddr + 1);
|
||||
return XIP_SFlash_Erase_With_Lock(&g_boot2_flash_cfg, g_boot2_flash_cfg.ioMode & 0x0f, startaddr, len);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -272,11 +272,11 @@ int i2s_control(struct device *dev, int cmd, void *args)
|
|||
/* code */
|
||||
break;
|
||||
|
||||
case DEVICE_CTRL_I2S_ATTACH_TX_DMA /* constant-expression */:
|
||||
case DEVICE_CTRL_ATTACH_TX_DMA /* constant-expression */:
|
||||
i2s_device->tx_dma = (struct device *)args;
|
||||
break;
|
||||
|
||||
case DEVICE_CTRL_I2S_ATTACH_RX_DMA /* constant-expression */:
|
||||
case DEVICE_CTRL_ATTACH_RX_DMA /* constant-expression */:
|
||||
i2s_device->rx_dma = (struct device *)args;
|
||||
break;
|
||||
|
||||
|
|
|
|||
|
|
@ -1433,19 +1433,6 @@ int lp_enter_pds(uint32_t sleep_time, void (*preCbFun)(void), void (*postCbFun)(
|
|||
return 0;
|
||||
}
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief Make buf word
|
||||
*
|
||||
* @param data: Data
|
||||
*
|
||||
* @return Word data
|
||||
*
|
||||
*******************************************************************************/
|
||||
static uint32_t put_word_buf(uint8_t data)
|
||||
{
|
||||
return (data << 24) + (data << 16) + (data << 8) + data;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief enter cpu into hbn mode
|
||||
*
|
||||
|
|
|
|||
|
|
@ -95,12 +95,6 @@ int pwm_control(struct device *dev, int cmd, void *args)
|
|||
|
||||
switch (cmd) {
|
||||
case DEVICE_CTRL_CONFIG /* constant-expression */:
|
||||
if (pwm_device->period > peripheral_clock_get(PERIPHERAL_CLOCK_PWM))
|
||||
return -1;
|
||||
|
||||
BL_WR_REG(PWM_BASE + PWM_CHANNEL_OFFSET + (pwm_device->ch) * 0x20, PWM_PERIOD, (uint32_t)args);
|
||||
BL_WR_REG(PWM_BASE + PWM_CHANNEL_OFFSET + (pwm_device->ch) * 0x20, PWM_THRE1, pwm_detycycle_config->threshold_low);
|
||||
BL_WR_REG(PWM_BASE + PWM_CHANNEL_OFFSET + (pwm_device->ch) * 0x20, PWM_THRE2, pwm_detycycle_config->threshold_high);
|
||||
break;
|
||||
case DEVICE_CTRL_RESUME /* constant-expression */:
|
||||
PWM_Channel_Enable(pwm_device->ch);
|
||||
|
|
@ -111,9 +105,9 @@ int pwm_control(struct device *dev, int cmd, void *args)
|
|||
break;
|
||||
case DEIVCE_CTRL_PWM_FREQUENCE_CONFIG:
|
||||
|
||||
if (pwm_device->period > peripheral_clock_get(PERIPHERAL_CLOCK_PWM))
|
||||
if ((uint32_t)args > peripheral_clock_get(PERIPHERAL_CLOCK_PWM))
|
||||
return -1;
|
||||
|
||||
pwm_device->period = (uint32_t)args;
|
||||
BL_WR_REG(PWM_BASE + PWM_CHANNEL_OFFSET + (pwm_device->ch) * 0x20, PWM_PERIOD, (uint32_t)args);
|
||||
break;
|
||||
case DEIVCE_CTRL_PWM_DUTYCYCLE_CONFIG:
|
||||
|
|
|
|||
|
|
@ -304,8 +304,6 @@ int usb_close(struct device *dev)
|
|||
usb_set_power_off();
|
||||
|
||||
usb_xcvr_config(DISABLE);
|
||||
GLB_Set_USB_CLK(DISABLE);
|
||||
|
||||
return 0;
|
||||
}
|
||||
/**
|
||||
|
|
@ -672,7 +670,7 @@ int usb_dc_ep_write(struct device *dev, const uint8_t ep, const uint8_t *data, u
|
|||
if (!usb_ep_is_enabled(ep)) {
|
||||
return -USB_DC_EP_EN_ERR;
|
||||
}
|
||||
|
||||
/* Check if ep free */
|
||||
while (!USB_Is_EPx_RDY_Free(ep_idx)) {
|
||||
timeout--;
|
||||
|
||||
|
|
@ -777,27 +775,13 @@ int usb_dc_ep_read(struct device *dev, const uint8_t ep, uint8_t *data, uint32_t
|
|||
USB_DC_LOG_ERR("Not enabled endpoint\r\n");
|
||||
return -USB_DC_EP_EN_ERR;
|
||||
}
|
||||
/* Check if ep free */
|
||||
while (!USB_Is_EPx_RDY_Free(ep_idx)) {
|
||||
timeout--;
|
||||
|
||||
/*common process for other ep out*/
|
||||
if (ep_idx) {
|
||||
while (!USB_Is_EPx_RDY_Free(ep_idx)) {
|
||||
timeout--;
|
||||
|
||||
if (!timeout) {
|
||||
USB_DC_LOG_ERR("ep%d wait free timeout\r\n", ep);
|
||||
return -USB_DC_EP_TIMEOUT_ERR;
|
||||
}
|
||||
}
|
||||
}
|
||||
/*special process for ep0 out*/
|
||||
else if (read_bytes && data_len && (ep_idx == 0)) {
|
||||
while (((BL_RD_WORD(0x4000D800) & (1 << 28)) >> 28)) {
|
||||
timeout--;
|
||||
|
||||
if (!timeout) {
|
||||
USB_DC_LOG_ERR("ep%d wait free timeout\r\n", ep);
|
||||
return -USB_DC_EP_TIMEOUT_ERR;
|
||||
}
|
||||
if (!timeout) {
|
||||
USB_DC_LOG_ERR("ep%d wait free timeout\r\n", ep);
|
||||
return -USB_DC_EP_TIMEOUT_ERR;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue