GitHub-Mirror/bl_mcu_sdk
2
0
Fork 0
mirror of https://github.com/Fishwaldo/bl_mcu_sdk.git synced 2025-07-07 05:18:34 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

[feat][bl702_driver] add some api and delete unused api

Browse source
This commit is contained in:
jzlv 2021-07-06 16:18:00 +08:00
parent ab8a6561b8
commit 13b4ba91f9
26 changed files with 579 additions and 189 deletions
Download patch file Download diff file Expand all files Collapse all files

5
drivers/bl702_driver/cpu_flags.cmake
View file

@ -1,12 +1,7 @@
SET(CPU_ARCH "RISCV")
SET(MCPU "riscv-e24")
if(${SUPPORT_FLOAT} STREQUAL "y")
SET(MARCH "rv32imafc")
SET(MABI "ilp32f")
else()
SET(MARCH "rv32imac")
SET(MABI "ilp32")
endif()
list(APPEND GLOBAL_C_FLAGS -march=${MARCH} -mabi=${MABI})
list(APPEND GLOBAL_LD_FLAGS -march=${MARCH} -mabi=${MABI})

12
drivers/bl702_driver/hal_drv/inc/hal_adc.h
View file

@ -41,6 +41,14 @@ enum adc_index_type {
ADC_MAX_INDEX
};
enum ADC_event_type {
ADC_EVENT_FIFO_READY,
ADC_EVENT_OVERRUN,
ADC_EVENT_UNDERRUN,
ADC_EVEN_INT_POS_SATURATION,
ADC_EVEN_INT_NEG_SATURATION,
};
#define adc_channel_start(dev) device_control(dev, DEVICE_CTRL_ADC_CHANNEL_START, NULL)
#define adc_channel_stop(dev) device_control(dev, DEVICE_CTRL_ADC_CHANNEL_STOP, NULL)
#define adc_channel_config(dev, list) device_control(dev, DEVICE_CTRL_ADC_CHANNEL_CONFIG, list)
@ -84,8 +92,8 @@ typedef enum {
} adc_clk_div_t;
typedef enum {
ADC_VREF_3P2V = 0, /* ADC select 3.2V as reference voltage */
ADC_VREF_2P0V = 1, /* ADC select 2V as reference voltage */
ADC_VREF_3V2 = 0, /* ADC select 3.2V as reference voltage */
ADC_VREF_2V = 1, /* ADC select 2V as reference voltage */
} adc_vref_t;
/**

21
drivers/bl702_driver/hal_drv/inc/hal_cam.h
View file

@ -28,6 +28,23 @@
#include "bl702_cam.h"
#include "bl702_config.h"
#define DEVICE_OFLAG_INT 0x01
#define DEVICE_OFLAG_POLL 0x02
enum camera_event_type {
CAM_EVENT_NORMAL_0, /*!< Interleave mode: normal write interrupt, planar mode:even byte normal write interrupt */
CAM_EVENT_NORMAL_1, /*!< Interleave mode: no use, planar mode:odd byte normal write interrupt */
CAM_EVENT_MEMORY_OVERWRITE_0, /*!< Interleave mode: memory overwrite interrupt, planar mode:even byte memory overwrite interrupt */
CAM_EVENT_MEMORY_OVERWRITE_1, /*!< Interleave mode: no use, planar mode:odd byte memory overwrite interrupt */
CAM_EVENT_FRAME_OVERWRITE_0, /*!< Interleave mode: frame overwrite interrupt, planar mode:even byte frame overwrite interrupt */
CAM_EVENT_FRAME_OVERWRITE_1, /*!< Interleave mode: no use, planar mode:odd byte frame overwrite interrupt */
CAM_EVENT_FIFO_OVERWRITE_0, /*!< Interleave mode: fifo overwrite interrupt, planar mode:even byte fifo overwrite interrupt */
CAM_EVENT_FIFO_OVERWRITE_1, /*!< Interleave mode: no use, planar mode:odd byte fifo overwrite interrupt */
CAM_EVENT_VSYNC_CNT_ERROR, /*!< Vsync valid line count non-match interrupt */
CAM_EVENT_HSYNC_CNT_ERROR, /*!< Hsync valid pixel count non-match interrupt */
CAM_EVENT_ALL, /*!< All of interrupt */
};
typedef enum {
CAM_AUTO_MODE,
CAM_MANUAL_MODE,
@ -61,7 +78,7 @@ typedef struct cam_device {
uint32_t cam_frame_size1;
} cam_device_t;
void cam_init(cam_device_t *cam_cfg);
void cam_init(cam_device_t *cam_cfg, uint16_t oflag);
void cam_start(void);
void cam_stop(void);
uint8_t cam_get_one_frame_interleave(uint8_t **pic, uint32_t *len);
@ -70,5 +87,7 @@ void cam_drop_one_frame_interleave(void);
void cam_drop_one_frame_planar(void);
void cam_hsync_crop(uint16_t start, uint16_t end);
void cam_vsync_crop(uint16_t start, uint16_t end);
void cam_hw_mode_wrap(uint8_t enbale);
void CAM_Int_Callback_set(CAM_INT_Type intType, intCallback_Type *cbFun);
#endif

31
drivers/bl702_driver/hal_drv/inc/hal_clock.h
View file

@ -31,39 +31,30 @@
#define ROOT_CLOCK_SOURCE_RC_32K 0
#define ROOT_CLOCK_SOURCE_XTAL_32K 1
#define ROOT_CLOCK_SOURCE_RC_32M 2
#define ROOT_CLOCK_SOURCE_RC_32M 2
#define ROOT_CLOCK_SOURCE_XTAL_32M 3
#define ROOT_CLOCK_SOURCE_PLL_57P6M 4
#define ROOT_CLOCK_SOURCE_PLL_96M 5
#define ROOT_CLOCK_SOURCE_PLL_144M 6
#define ROOT_CLOCK_SOURCE_XCLK ROOT_CLOCK_SOURCE_XTAL_32M
#define ROOT_CLOCK_SOURCE_FCLK 7
#define ROOT_CLOCK_SOURCE_HCLK 7
#define ROOT_CLOCK_SOURCE_BCLK 8
#define ROOT_CLOCK_SOURCE_32K_CLK ROOT_CLOCK_SOURCE_RC_32K
#define ROOT_CLOCK_SOURCE_XCLK ROOT_CLOCK_SOURCE_XTAL_32M
#define ROOT_CLOCK_SOURCE_FCLK 7
#define ROOT_CLOCK_SOURCE_BCLK 8
#define ROOT_CLOCK_SOURCE_AUPLL 9
#define AUDIO_PLL_CLOCK_12288000_HZ 0x90
#define AUDIO_PLL_CLOCK_11289600_HZ 0x91
#define AUDIO_PLL_CLOCK_5644800_HZ 0x92
#define AUDIO_PLL_CLOCK_24576000_HZ 0x93
#define AUDIO_PLL_CLOCK_24000000_HZ 0x94
#define OUTPUT_REF_CLOCK_SOURCE_NONE 0
#define OUTPUT_REF_CLOCK_SOURCE_I2S 1
#if (BSP_ROOT_CLOCK_SOURCE > 2) && (BSP_ROOT_CLOCK_SOURCE < 7)
#define CLOCK_XTAL EXTERNAL_XTAL_32M
#else
#define CLOCK_XTAL INTERNAL_XTAL_32M
#endif
#define ROOT_CLOCK_SOURCE_AUPLL_12288000_HZ 9
#define ROOT_CLOCK_SOURCE_AUPLL_11289600_HZ 10
#define ROOT_CLOCK_SOURCE_AUPLL_5644800_HZ 11
#define ROOT_CLOCK_SOURCE_AUPLL_24576000_HZ 12
#define ROOT_CLOCK_SOURCE_AUPLL_24000000_HZ 13
enum system_clock_type {
SYSTEM_CLOCK_ROOT_CLOCK = 0,
SYSTEM_CLOCK_FCLK,
SYSTEM_CLOCK_BCLK,
SYSTEM_CLOCK_XCLK,
SYSTEM_CLOCK_32K_CLK,
SYSTEM_CLOCK_AUPLL,
};
enum peripheral_clock_type {

3
drivers/bl702_driver/hal_drv/inc/hal_flash.h
View file

@ -29,8 +29,9 @@
int flash_init(void);
int flash_read_jedec_id(uint8_t *data);
BL_Err_Type flash_read_via_xip(uint32_t addr, uint8_t *data, uint32_t len);
BL_Err_Type flash_read_xip(uint32_t addr, uint8_t *data, uint32_t len);
BL_Err_Type flash_write_xip(uint32_t addr, uint8_t *data, uint32_t len);
BL_Err_Type flash_erase_xip(uint32_t startaddr, uint32_t endaddr);
BL_Err_Type flash_erase_xip(uint32_t startaddr, uint32_t len);
BL_Err_Type flash_set_cache(uint8_t cont_read, uint8_t cache_enable, uint8_t cache_way_disable, uint32_t flash_offset);
#endif

6
drivers/bl702_driver/hal_drv/inc/hal_gpio.h
View file

@ -58,12 +58,6 @@ enum gpio_pin_type {
GPIO_PIN_29,
GPIO_PIN_30,
GPIO_PIN_31,
GPIO_PIN_32,
GPIO_PIN_33,
GPIO_PIN_34,
GPIO_PIN_35,
GPIO_PIN_36,
GPIO_PIN_37,
GPIO_PIN_MAX,
};

6
drivers/bl702_driver/hal_drv/inc/hal_i2s.h
View file

@ -26,10 +26,8 @@
#include "drv_device.h"
#include "bl702_config.h"
#define I2S_GET_TX_FIFO_CMD 0x10
#define I2S_GET_RX_FIFO_CMD 0x11
#define DEVICE_CTRL_I2S_ATTACH_TX_DMA 0x12
#define DEVICE_CTRL_I2S_ATTACH_RX_DMA 0x13
#define I2S_GET_TX_FIFO_CMD 0x10
#define I2S_GET_RX_FIFO_CMD 0x11
enum i2s_index_type {
#ifdef BSP_USING_I2S0

8
drivers/bl702_driver/hal_drv/inc/hal_pwm.h
View file

@ -49,9 +49,11 @@ enum pwm_index_type {
PWM_MAX_INDEX
};
#define pwm_channel_start(dev) device_control(dev, DEVICE_CTRL_RESUME, NULL)
#define pwm_channel_stop(dev) device_control(dev, DEVICE_CTRL_SUSPEND, NULL)
#define pwm_it_pulse_count_update(dev, count) device_control(dev, DEIVCE_CTRL_PWM_IT_PULSE_COUNT_CONFIG, (void *)count)
#define pwm_channel_start(dev) device_control(dev, DEVICE_CTRL_RESUME, NULL)
#define pwm_channel_stop(dev) device_control(dev, DEVICE_CTRL_SUSPEND, NULL)
#define pwm_channel_freq_update(dev, count) device_control(dev, DEIVCE_CTRL_PWM_FREQUENCE_CONFIG, (void *)count)
#define pwm_channel_dutycycle_update(dev, cfg) device_control(dev, DEIVCE_CTRL_PWM_DUTYCYCLE_CONFIG, cfg)
#define pwm_it_pulse_count_update(dev, count) device_control(dev, DEIVCE_CTRL_PWM_IT_PULSE_COUNT_CONFIG, (void *)count)
enum pwm_event_type {
PWM_EVENT_COMPLETE,

91
drivers/bl702_driver/hal_drv/src/hal_adc.c
View file

@ -102,6 +102,50 @@ int adc_close(struct device *dev)
ADC_Disable();
return 0;
}
/**
* @brief Check whether Channel Corresponding IO is configed success by Board System
*
* @param pos_list pos channel list
* @param neg_list negative channel list
* @param channelNum channel number
*/
uint8_t adc_check_channel_status(uint8_t *pos_list, uint8_t *neg_list, uint16_t channelNum)
{
uint16_t i = 0;
uint8_t channel_io_reference_table[] = {
GPIO_PIN_8, /* CH0 IO */
GPIO_PIN_15, /* CH1 IO */
GPIO_PIN_17, /* CH2 IO */
GPIO_PIN_11, /* CH3 IO */
GPIO_PIN_12, /* CH4 IO */
GPIO_PIN_14, /* CH5 IO */
0xff, /* CH6 IO */
0xff, /* CH7 IO */
GPIO_PIN_18, /* CH8 IO */
GPIO_PIN_19, /* CH9 IO */
GPIO_PIN_20, /* CH10 IO */
GPIO_PIN_21, /* CH11 IO */
};
for (i = 0; i < channelNum; i++) {
if (pos_list[i] > ADC_CHANNEL11) {
continue;
}
if (channel_io_reference_table[pos_list[i]] == 0xff) {
return ERROR;
}
if (GLB_GPIO_Get_Fun(channel_io_reference_table[pos_list[i]]) != GPIO_FUN_ANALOG) {
return ERROR;
}
}
return SUCCESS;
}
/**
* @brief
*
@ -114,6 +158,7 @@ int adc_control(struct device *dev, int cmd, void *args)
{
adc_device_t *adc_device = (adc_device_t *)dev;
adc_channel_cfg_t *adc_channel_cfg = (adc_channel_cfg_t *)args;
uint8_t rlt = 0;
switch (cmd) {
case DEVICE_CTRL_SET_INT /* constant-expression */:
@ -135,8 +180,10 @@ int adc_control(struct device *dev, int cmd, void *args)
case DEVICE_CTRL_ADC_CHANNEL_CONFIG /* constant-expression */:
if (adc_channel_cfg->num == 1) {
ADC_Channel_Config(*adc_channel_cfg->pos_channel, *adc_channel_cfg->neg_channel, adc_device->continuous_conv_mode);
rlt = adc_check_channel_status(adc_channel_cfg->pos_channel, adc_channel_cfg->neg_channel, 1);
} else {
ADC_Scan_Channel_Config(adc_channel_cfg->pos_channel, adc_channel_cfg->neg_channel, adc_channel_cfg->num, adc_device->continuous_conv_mode);
rlt = adc_check_channel_status(adc_channel_cfg->pos_channel, adc_channel_cfg->neg_channel, adc_channel_cfg->num);
}
break;
@ -171,7 +218,7 @@ int adc_control(struct device *dev, int cmd, void *args)
break;
}
return 0;
return rlt;
}
// int adc_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t size)
// {
@ -247,3 +294,45 @@ int adc_register(enum adc_index_type index, const char *name, uint16_t flag)
return device_register(dev, name, flag);
}
/**
* @brief
*
* @param handle
*/
void adc_isr(adc_device_t *handle)
{
if (!handle->parent.callback)
return;
if (ADC_GetIntStatus(ADC_INT_POS_SATURATION) == SET && ADC_IntGetMask(ADC_INT_POS_SATURATION) == UNMASK) {
ADC_IntClr(ADC_INT_POS_SATURATION);
handle->parent.callback(&handle->parent, NULL, 0, ADC_INT_POS_SATURATION);
}
if (ADC_GetIntStatus(ADC_INT_NEG_SATURATION) == SET && ADC_IntGetMask(ADC_INT_NEG_SATURATION) == UNMASK) {
ADC_IntClr(ADC_INT_NEG_SATURATION);
handle->parent.callback(&handle->parent, NULL, 0, ADC_INT_NEG_SATURATION);
}
if (ADC_GetIntStatus(ADC_INT_FIFO_UNDERRUN) == SET && ADC_IntGetMask(ADC_INT_FIFO_UNDERRUN) == UNMASK) {
ADC_IntClr(ADC_INT_FIFO_UNDERRUN);
handle->parent.callback(&handle->parent, NULL, 0, ADC_INT_FIFO_UNDERRUN);
}
if (ADC_GetIntStatus(ADC_INT_FIFO_OVERRUN) == SET && ADC_IntGetMask(ADC_INT_FIFO_OVERRUN) == UNMASK) {
ADC_IntClr(ADC_INT_FIFO_OVERRUN);
handle->parent.callback(&handle->parent, NULL, 0, ADC_INT_FIFO_OVERRUN);
}
if (ADC_GetIntStatus(ADC_INT_FIFO_READY) == SET && ADC_IntGetMask(ADC_INT_FIFO_READY) == UNMASK) {
ADC_IntClr(ADC_INT_FIFO_READY);
handle->parent.callback(&handle->parent, NULL, 0, ADC_INT_FIFO_READY);
}
}
#ifdef BSP_USING_ADC0
void ADC_IRQ(void)
{
adc_isr(&adcx_device[ADC0_INDEX]);
}
#endif

108
drivers/bl702_driver/hal_drv/src/hal_cam.c
View file

@ -25,12 +25,16 @@
#include "bl702_glb.h"
#include "hal_cam.h"
static intCallback_Type *camIntCbfArra[CAM_INT_ALL] = { NULL };
void CAMERA_IRQ(void);
/**
* @brief
*
* @param cam_cfg
*/
void cam_init(cam_device_t *cam_cfg)
void cam_init(cam_device_t *cam_cfg, uint16_t oflag)
{
CAM_CFG_Type camera_cfg = {
.swMode = cam_cfg->software_mode,
@ -51,6 +55,10 @@ void cam_init(cam_device_t *cam_cfg)
.frameSize1 = cam_cfg->cam_frame_size1,
};
CAM_Init(&camera_cfg);
if (oflag == DEVICE_OFLAG_INT) {
Interrupt_Handler_Register(CAM_IRQn, CAMERA_IRQ);
}
}
/**
@ -138,3 +146,101 @@ void cam_vsync_crop(uint16_t start, uint16_t end)
{
CAM_Vsync_Crop(start, end);
}
void cam_hw_mode_wrap(uint8_t enable)
{
CAM_HW_Mode_Wrap(enable);
}
void cam_isr(cam_device_t *handle)
{
}
#ifdef BSP_USING_CAM
void CAM_Int_Callback_set(CAM_INT_Type intType, intCallback_Type *cbFun)
{
/* Check the parameters */
CHECK_PARAM(IS_CAM_INT_TYPE(intType));
camIntCbfArra[intType] = cbFun;
}
void CAMERA_IRQ(void)
{
uint32_t tmpVal;
tmpVal = BL_RD_REG(CAM_BASE, CAM_DVP_STATUS_AND_ERROR);
if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_NORMAL_INT_0)) {
CAM_IntClr(CAM_INT_NORMAL_0);
if (camIntCbfArra[CAM_INT_NORMAL_0] != NULL) {
/* call the callback function */
camIntCbfArra[CAM_INT_NORMAL_0]();
}
}
if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_NORMAL_INT_1)) {
CAM_IntClr(CAM_INT_NORMAL_1);
if (camIntCbfArra[CAM_INT_NORMAL_1] != NULL) {
/* call the callback function */
camIntCbfArra[CAM_INT_NORMAL_1]();
}
}
if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_MEM_INT_0)) {
CAM_IntClr(CAM_INT_MEMORY_OVERWRITE_0);
if (camIntCbfArra[CAM_INT_MEMORY_OVERWRITE_0] != NULL) {
/* call the callback function */
camIntCbfArra[CAM_INT_MEMORY_OVERWRITE_0]();
}
}
if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_MEM_INT_1)) {
CAM_IntClr(CAM_INT_MEMORY_OVERWRITE_1);
if (camIntCbfArra[CAM_INT_MEMORY_OVERWRITE_1] != NULL) {
/* call the callback function */
camIntCbfArra[CAM_INT_MEMORY_OVERWRITE_1]();
}
}
if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_FRAME_INT_0)) {
CAM_IntClr(CAM_INT_FRAME_OVERWRITE_0);
if (camIntCbfArra[CAM_INT_FRAME_OVERWRITE_0] != NULL) {
/* call the callback function */
camIntCbfArra[CAM_INT_FRAME_OVERWRITE_0]();
}
}
if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_FRAME_INT_1)) {
CAM_IntClr(CAM_INT_FRAME_OVERWRITE_1);
if (camIntCbfArra[CAM_INT_FRAME_OVERWRITE_1] != NULL) {
/* call the callback function */
camIntCbfArra[CAM_INT_FRAME_OVERWRITE_1]();
}
}
if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_FIFO_INT_0)) {
CAM_IntClr(CAM_INT_FIFO_OVERWRITE_0);
if (camIntCbfArra[CAM_INT_FIFO_OVERWRITE_0] != NULL) {
/* call the callback function */
camIntCbfArra[CAM_INT_FIFO_OVERWRITE_0]();
}
}
if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_FIFO_INT_1)) {
CAM_IntClr(CAM_INT_FIFO_OVERWRITE_1);
if (camIntCbfArra[CAM_INT_FIFO_OVERWRITE_1] != NULL) {
/* call the callback function */
camIntCbfArra[CAM_INT_FIFO_OVERWRITE_1]();
}
}
if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_HCNT_INT)) {
CAM_IntClr(CAM_INT_HSYNC_CNT_ERROR);
if (camIntCbfArra[CAM_INT_HSYNC_CNT_ERROR] != NULL) {
/* call the callback function */
camIntCbfArra[CAM_INT_HSYNC_CNT_ERROR]();
}
}
if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_VCNT_INT)) {
CAM_IntClr(CAM_INT_VSYNC_CNT_ERROR);
if (camIntCbfArra[CAM_INT_VSYNC_CNT_ERROR] != NULL) {
/* call the callback function */
camIntCbfArra[CAM_INT_VSYNC_CNT_ERROR]();
}
}
}
#endif

74
drivers/bl702_driver/hal_drv/src/hal_clock.c
View file

@ -36,11 +36,11 @@ void system_clock_init(void)
/*select root clock*/
GLB_Set_System_CLK(CLOCK_XTAL, BSP_ROOT_CLOCK_SOURCE - 2);
/*set fclk/hclk and bclk clock*/
GLB_Set_System_CLK_Div(BSP_HCLK_DIV, BSP_BCLK_DIV);
GLB_Set_System_CLK_Div(BSP_FCLK_DIV, BSP_BCLK_DIV);
/* Set MTimer the same frequency as SystemCoreClock */
GLB_Set_MTimer_CLK(1, GLB_MTIMER_CLK_BCLK, mtimer_get_clk_src_div());
#ifdef BSP_AUDIO_PLL_CLOCK_SOURCE
PDS_Set_Audio_PLL_Freq(BSP_AUDIO_PLL_CLOCK_SOURCE & 0x0f);
PDS_Set_Audio_PLL_Freq(BSP_AUDIO_PLL_CLOCK_SOURCE - ROOT_CLOCK_SOURCE_AUPLL_12288000_HZ);
#endif
}
void peripheral_clock_init(void)
@ -77,7 +77,7 @@ void peripheral_clock_init(void)
uint32_t timeoutCnt = 160 * 1000;
uint32_t tmpVal;
uint32_t PWMx;
#if BSP_PWM_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_RC_32K
#if BSP_PWM_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_32K_CLK
for (int i = 0; i < 5; i++) {
PWMx = PWM_BASE + PWM_CHANNEL_OFFSET + (i)*0x20;
@ -149,26 +149,22 @@ void peripheral_clock_init(void)
#if defined(BSP_USING_I2S0)
GLB_Set_I2S_CLK(ENABLE, GLB_I2S_OUT_REF_CLK_NONE);
#endif
#if defined(BSP_USING_ADC0)
#if BSP_ADC_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_AUPLL
#ifdef BSP_AUDIO_PLL_CLOCK_SOURCE
#if BSP_ADC_CLOCK_SOURCE >= ROOT_CLOCK_SOURCE_AUPLL_12288000_HZ
GLB_Set_ADC_CLK(ENABLE, GLB_ADC_CLK_AUDIO_PLL, BSP_ADC_CLOCK_DIV);
#endif
#elif BSP_ADC_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK
GLB_Set_ADC_CLK(ENABLE, GLB_ADC_CLK_XCLK, BSP_ADC_CLOCK_DIV);
#else
#error "please select correct adc clock source"
#endif
#endif
#if defined(BSP_USING_DAC0)
#if BSP_ADC_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_AUPLL
#ifdef BSP_AUDIO_PLL_CLOCK_SOURCE
GLB_Set_DAC_CLK(ENABLE, GLB_ADC_CLK_AUDIO_PLL, BSP_DAC_CLOCK_DIV);
#endif
#elif BSP_ADC_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK
GLB_Set_DAC_CLK(ENABLE, GLB_ADC_CLK_XCLK, BSP_DAC_CLOCK_DIV);
#if BSP_DAC_CLOCK_SOURCE >= ROOT_CLOCK_SOURCE_AUPLL_12288000_HZ
GLB_Set_DAC_CLK(ENABLE, GLB_DAC_CLK_AUDIO_PLL, BSP_DAC_CLOCK_DIV);
#elif BSP_DAC_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK
GLB_Set_DAC_CLK(ENABLE, GLB_DAC_CLK_XCLK, BSP_DAC_CLOCK_DIV);
#else
#error "please select correct dac clock source"
#endif
@ -178,8 +174,21 @@ void peripheral_clock_init(void)
#if BSP_CAM_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_PLL_96M
GLB_Set_CAM_CLK(ENABLE, GLB_CAM_CLK_DLL96M, BSP_CAM_CLOCK_DIV);
GLB_SWAP_EMAC_CAM_Pin(GLB_EMAC_CAM_PIN_CAM);
#elif BSP_CAM_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK
GLB_Set_CAM_CLK(ENABLE, GLB_CAM_CLK_XCLK, BSP_CAM_CLOCK_DIV);
GLB_SWAP_EMAC_CAM_Pin(GLB_EMAC_CAM_PIN_CAM);
#else
#error "please select correct cam clock source"
#error "please select correct camera clock source"
#endif
#endif
#if defined(BSP_USING_QDEC)
#if BSP_QDEC_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_32K_CLK
GLB_Set_QDEC_CLK(ENABLE, GLB_QDEC_CLK_F32K, BSP_QDEC_CLOCK_DIV);
#elif BSP_QDEC_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK
GLB_Set_QDEC_CLK(ENABLE, GLB_QDEC_CLK_XCLK, BSP_QDEC_CLOCK_DIV);
#else
#error "please select correct qdec clock source"
#endif
#endif
@ -201,23 +210,20 @@ uint32_t system_clock_get(enum system_clock_type type)
case SYSTEM_CLOCK_XCLK:
return 32000000;
case SYSTEM_CLOCK_32K_CLK:
return 32000;
case SYSTEM_CLOCK_AUPLL:
#ifdef BSP_AUDIO_PLL_CLOCK_SOURCE
if (BSP_AUDIO_PLL_CLOCK_SOURCE == AUDIO_PLL_CLOCK_12288000_HZ) {
if (BSP_AUDIO_PLL_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_AUPLL_12288000_HZ) {
return 12288000;
} else if (BSP_AUDIO_PLL_CLOCK_SOURCE == AUDIO_PLL_CLOCK_11289600_HZ) {
} else if (BSP_AUDIO_PLL_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_AUPLL_11289600_HZ) {
return 11289600;
} else if (BSP_AUDIO_PLL_CLOCK_SOURCE == AUDIO_PLL_CLOCK_5644800_HZ) {
} else if (BSP_AUDIO_PLL_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_AUPLL_5644800_HZ) {
return 5644800;
} else if (BSP_AUDIO_PLL_CLOCK_SOURCE == AUDIO_PLL_CLOCK_24576000_HZ) {
} else if (BSP_AUDIO_PLL_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_AUPLL_24576000_HZ) {
return 24576000;
} else if (BSP_AUDIO_PLL_CLOCK_SOURCE == AUDIO_PLL_CLOCK_24000000_HZ) {
} else if (BSP_AUDIO_PLL_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_AUPLL_24000000_HZ) {
return 24000000;
}
#endif
default:
break;
}
@ -258,15 +264,15 @@ uint32_t peripheral_clock_get(enum peripheral_clock_type type)
#endif
case PERIPHERAL_CLOCK_I2S:
return 0;
return system_clock_get(SYSTEM_CLOCK_AUPLL);
case PERIPHERAL_CLOCK_ADC:
#if defined(BSP_USING_ADC0)
#if BSP_ADC_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK
tmpVal = BL_RD_REG(GLB_BASE, GLB_GPADC_32M_SRC_CTRL);
div = BL_GET_REG_BITS_VAL(tmpVal, GLB_GPADC_32M_CLK_DIV);
return 32000000 / div;
#elif BSP_ADC_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_AUPLL
return system_clock_get(SYSTEM_CLOCK_XCLK) / div;
#elif BSP_ADC_CLOCK_SOURCE >= ROOT_CLOCK_SOURCE_AUPLL_12288000_HZ
tmpVal = BL_RD_REG(GLB_BASE, GLB_GPADC_32M_SRC_CTRL);
div = BL_GET_REG_BITS_VAL(tmpVal, GLB_GPADC_32M_CLK_DIV);
return system_clock_get(SYSTEM_CLOCK_AUPLL) / div;
@ -278,8 +284,8 @@ uint32_t peripheral_clock_get(enum peripheral_clock_type type)
#if BSP_DAC_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK
tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL);
div = BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_512K_DIV);
return 32000000 / (div + 1);
#elif BSP_DAC_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_AUPLL
return system_clock_get(SYSTEM_CLOCK_XCLK) / (div + 1);
#elif BSP_DAC_CLOCK_SOURCE >= ROOT_CLOCK_SOURCE_AUPLL_12288000_HZ
tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL);
div = BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_512K_DIV);
return system_clock_get(SYSTEM_CLOCK_AUPLL) / div;
@ -288,15 +294,15 @@ uint32_t peripheral_clock_get(enum peripheral_clock_type type)
case PERIPHERAL_CLOCK_PWM:
#if defined(BSP_USING_PWM_CH0) || defined(BSP_USING_PWM_CH1) || defined(BSP_USING_PWM_CH2) || defined(BSP_USING_PWM_CH3) || defined(BSP_USING_PWM_CH4) || defined(BSP_USING_PWM_CH5)
#if BSP_PWM_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_RC_32K
#if BSP_PWM_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_32K_CLK
div = BL_RD_REG(PWM_BASE + PWM_CHANNEL_OFFSET, PWM_CLKDIV);
return 32000 / div;
return system_clock_get(SYSTEM_CLOCK_32K_CLK) / div;
#elif BSP_PWM_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_BCLK
div = BL_RD_REG(PWM_BASE + PWM_CHANNEL_OFFSET, PWM_CLKDIV);
return system_clock_get(SYSTEM_CLOCK_BCLK) / div;
#elif BSP_PWM_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK
div = BL_RD_REG(PWM_BASE + PWM_CHANNEL_OFFSET, PWM_CLKDIV);
return 32000000 / div;
return system_clock_get(SYSTEM_CLOCK_XCLK) / div;
#endif
#endif
break;
@ -307,6 +313,10 @@ uint32_t peripheral_clock_get(enum peripheral_clock_type type)
tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG1);
div = BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_CAM_REF_CLK_DIV);
return (96000000 / (div + 1));
#elif BSP_CAM_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK
tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG1);
div = BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_CAM_REF_CLK_DIV);
return (system_clock_get(SYSTEM_CLOCK_XCLK) / (div + 1));
#endif
#endif
break;

26
drivers/bl702_driver/hal_drv/src/hal_flash.c
View file

@ -58,6 +58,23 @@ int flash_read_jedec_id(uint8_t *data)
return 0;
}
/**
* @brief read flash data via xip
*
* @param addr
* @param data
* @param len
* @return BL_Err_Type
*/
BL_Err_Type flash_read_via_xip(uint32_t addr, uint8_t *data, uint32_t len)
{
L1C_Cache_Flush(0xf);
XIP_SFlash_Read_Via_Cache_Need_Lock(addr, data, len);
L1C_Cache_Flush(0x0);
return 0;
}
/**
* @brief read xip data
*
@ -68,10 +85,7 @@ int flash_read_jedec_id(uint8_t *data)
*/
BL_Err_Type flash_read_xip(uint32_t addr, uint8_t *data, uint32_t len)
{
BL702_MemCpy_Fast(data,
(uint8_t *)(BL702_FLASH_XIP_BASE + addr - SF_Ctrl_Get_Flash_Image_Offset()),
len);
return 0;
return XIP_SFlash_Read_With_Lock(&g_boot2_flash_cfg, g_boot2_flash_cfg.ioMode & 0x0f, addr, data, len);
}
/**
@ -94,9 +108,9 @@ BL_Err_Type flash_write_xip(uint32_t addr, uint8_t *data, uint32_t len)
* @param endaddr
* @return BL_Err_Type
*/
BL_Err_Type flash_erase_xip(uint32_t startaddr, uint32_t endaddr)
BL_Err_Type flash_erase_xip(uint32_t startaddr, uint32_t len)
{
return XIP_SFlash_Erase_With_Lock(&g_boot2_flash_cfg, g_boot2_flash_cfg.ioMode & 0x0f, startaddr, endaddr - startaddr + 1);
return XIP_SFlash_Erase_With_Lock(&g_boot2_flash_cfg, g_boot2_flash_cfg.ioMode & 0x0f, startaddr, len);
}
/**

4
drivers/bl702_driver/hal_drv/src/hal_i2s.c
View file

@ -272,11 +272,11 @@ int i2s_control(struct device *dev, int cmd, void *args)
/* code */
break;
case DEVICE_CTRL_I2S_ATTACH_TX_DMA /* constant-expression */:
case DEVICE_CTRL_ATTACH_TX_DMA /* constant-expression */:
i2s_device->tx_dma = (struct device *)args;
break;
case DEVICE_CTRL_I2S_ATTACH_RX_DMA /* constant-expression */:
case DEVICE_CTRL_ATTACH_RX_DMA /* constant-expression */:
i2s_device->rx_dma = (struct device *)args;
break;

13
drivers/bl702_driver/hal_drv/src/hal_power.c
View file

@ -1433,19 +1433,6 @@ int lp_enter_pds(uint32_t sleep_time, void (*preCbFun)(void), void (*postCbFun)(
return 0;
}
/****************************************************************************/ /**
* @brief Make buf word
*
* @param data: Data
*
* @return Word data
*
*******************************************************************************/
static uint32_t put_word_buf(uint8_t data)
{
return (data << 24) + (data << 16) + (data << 8) + data;
}
/**
* @brief enter cpu into hbn mode
*

10
drivers/bl702_driver/hal_drv/src/hal_pwm.c
View file

@ -95,12 +95,6 @@ int pwm_control(struct device *dev, int cmd, void *args)
switch (cmd) {
case DEVICE_CTRL_CONFIG /* constant-expression */:
if (pwm_device->period > peripheral_clock_get(PERIPHERAL_CLOCK_PWM))
return -1;
BL_WR_REG(PWM_BASE + PWM_CHANNEL_OFFSET + (pwm_device->ch) * 0x20, PWM_PERIOD, (uint32_t)args);
BL_WR_REG(PWM_BASE + PWM_CHANNEL_OFFSET + (pwm_device->ch) * 0x20, PWM_THRE1, pwm_detycycle_config->threshold_low);
BL_WR_REG(PWM_BASE + PWM_CHANNEL_OFFSET + (pwm_device->ch) * 0x20, PWM_THRE2, pwm_detycycle_config->threshold_high);
break;
case DEVICE_CTRL_RESUME /* constant-expression */:
PWM_Channel_Enable(pwm_device->ch);
@ -111,9 +105,9 @@ int pwm_control(struct device *dev, int cmd, void *args)
break;
case DEIVCE_CTRL_PWM_FREQUENCE_CONFIG:
if (pwm_device->period > peripheral_clock_get(PERIPHERAL_CLOCK_PWM))
if ((uint32_t)args > peripheral_clock_get(PERIPHERAL_CLOCK_PWM))
return -1;
pwm_device->period = (uint32_t)args;
BL_WR_REG(PWM_BASE + PWM_CHANNEL_OFFSET + (pwm_device->ch) * 0x20, PWM_PERIOD, (uint32_t)args);
break;
case DEIVCE_CTRL_PWM_DUTYCYCLE_CONFIG:

30
drivers/bl702_driver/hal_drv/src/hal_usb.c
View file

@ -304,8 +304,6 @@ int usb_close(struct device *dev)
usb_set_power_off();
usb_xcvr_config(DISABLE);
GLB_Set_USB_CLK(DISABLE);
return 0;
}
/**
@ -672,7 +670,7 @@ int usb_dc_ep_write(struct device *dev, const uint8_t ep, const uint8_t *data, u
if (!usb_ep_is_enabled(ep)) {
return -USB_DC_EP_EN_ERR;
}
/* Check if ep free */
while (!USB_Is_EPx_RDY_Free(ep_idx)) {
timeout--;
@ -777,27 +775,13 @@ int usb_dc_ep_read(struct device *dev, const uint8_t ep, uint8_t *data, uint32_t
USB_DC_LOG_ERR("Not enabled endpoint\r\n");
return -USB_DC_EP_EN_ERR;
}
/* Check if ep free */
while (!USB_Is_EPx_RDY_Free(ep_idx)) {
timeout--;
/*common process for other ep out*/
if (ep_idx) {
while (!USB_Is_EPx_RDY_Free(ep_idx)) {
timeout--;
if (!timeout) {
USB_DC_LOG_ERR("ep%d wait free timeout\r\n", ep);
return -USB_DC_EP_TIMEOUT_ERR;
}
}
}
/*special process for ep0 out*/
else if (read_bytes && data_len && (ep_idx == 0)) {
while (((BL_RD_WORD(0x4000D800) & (1 << 28)) >> 28)) {
timeout--;
if (!timeout) {
USB_DC_LOG_ERR("ep%d wait free timeout\r\n", ep);
return -USB_DC_EP_TIMEOUT_ERR;
}
if (!timeout) {
USB_DC_LOG_ERR("ep%d wait free timeout\r\n", ep);
return -USB_DC_EP_TIMEOUT_ERR;
}
}

29
drivers/bl702_driver/std_drv/inc/bl702_adc.h
View file

@ -56,18 +56,18 @@
* @brief ADC channel type definition
*/
typedef enum {
ADC_CHAN0, /*!< GPIO 0, ADC channel 0 */
ADC_CHAN1, /*!< GPIO 1, ADC channel 1 */
ADC_CHAN2, /*!< GPIO 2, ADC channel 2 */
ADC_CHAN3, /*!< GPIO 3, ADC channel 3 */
ADC_CHAN4, /*!< GPIO 4, ADC channel 4 */
ADC_CHAN5, /*!< GPIO 5, ADC channel 5 */
ADC_CHAN6, /*!< GPIO 6, ADC channel 6 */
ADC_CHAN7, /*!< GPIO 7, ADC channel 7 */
ADC_CHAN8, /*!< GPIO 8, ADC channel 8 */
ADC_CHAN9, /*!< GPIO 9, ADC channel 9 */
ADC_CHAN10, /*!< GPIO 10, ADC channel 10 */
ADC_CHAN11, /*!< GPIO 11, ADC channel 11 */
ADC_CHAN0, /*!< ADC channel 0 */
ADC_CHAN1, /*!< ADC channel 1 */
ADC_CHAN2, /*!< ADC channel 2 */
ADC_CHAN3, /*!< ADC channel 3 */
ADC_CHAN4, /*!< ADC channel 4 */
ADC_CHAN5, /*!< ADC channel 5 */
ADC_CHAN6, /*!< ADC channel 6 */
ADC_CHAN7, /*!< ADC channel 7 */
ADC_CHAN8, /*!< ADC channel 8 */
ADC_CHAN9, /*!< ADC channel 9 */
ADC_CHAN10, /*!< ADC channel 10 */
ADC_CHAN11, /*!< ADC channel 11 */
ADC_CHAN_DAC_OUTA, /*!< DACA, ADC channel 12 */
ADC_CHAN_DAC_OUTB, /*!< DACB, ADC channel 13 */
ADC_CHAN_TSEN_P, /*!< TSenp, ADC channel 14 */
@ -183,8 +183,8 @@ typedef enum {
* @brief ADC voltage reference type definition
*/
typedef enum {
ADC_VREF_3P3V, /*!< ADC select 3.3V as reference voltage */
ADC_VREF_2V, /*!< ADC select 2V as reference voltage */
ADC_VREF_3P2V, /*!< ADC select 3.2V as reference voltage */
ADC_VREF_2P0V, /*!< ADC select 2V as reference voltage */
} ADC_VREF_Type;
/**
@ -525,6 +525,7 @@ void ADC_FIFO_Clear(void);
uint32_t ADC_Read_FIFO(void);
void ADC_Parse_Result(uint32_t *orgVal, uint32_t len, ADC_Result_Type *result);
void ADC_IntClr(ADC_INT_Type intType);
BL_Mask_Type ADC_IntGetMask(ADC_INT_Type intType);
BL_Sts_Type ADC_GetIntStatus(ADC_INT_Type intType);
void ADC_Int_Callback_Install(ADC_INT_Type intType, intCallback_Type *cbFun);
void ADC_IntMask(ADC_INT_Type intType, BL_Mask_Type intMask);

1
drivers/bl702_driver/std_drv/inc/bl702_cam.h
View file

@ -282,6 +282,7 @@ void CAM_Planar_Pop_Frame(void);
void CAM_IntMask(CAM_INT_Type intType, BL_Mask_Type intMask);
void CAM_IntClr(CAM_INT_Type intType);
void CAM_Int_Callback_Install(CAM_INT_Type intType, intCallback_Type *cbFun);
void CAM_HW_Mode_Wrap(BL_Fun_Type enable);
/*@} end of group CAM_Public_Functions */

2
drivers/bl702_driver/std_drv/inc/bl702_glb.h
View file

@ -791,6 +791,8 @@ BL_Err_Type GLB_GPIO_INPUT_Disable(GLB_GPIO_Type gpioPin);
BL_Err_Type GLB_GPIO_OUTPUT_Enable(GLB_GPIO_Type gpioPin);
BL_Err_Type GLB_GPIO_OUTPUT_Disable(GLB_GPIO_Type gpioPin);
BL_Err_Type GLB_GPIO_Set_HZ(GLB_GPIO_Type gpioPin);
BL_Err_Type GLB_Set_Flash_Pad_HZ(void);
BL_Err_Type GLB_Set_Psram_Pad_HZ(void);
uint8_t GLB_GPIO_Get_Fun(GLB_GPIO_Type gpioPin);
BL_Err_Type GLB_GPIO_Write(GLB_GPIO_Type gpioPin, uint32_t val);
uint32_t GLB_GPIO_Read(GLB_GPIO_Type gpioPin);

2
drivers/bl702_driver/std_drv/inc/bl702_pwm.h
View file

@ -185,6 +185,8 @@ void PWM_Channel_Disable(PWM_CH_ID_Type ch);
void PWM_SW_Mode(PWM_CH_ID_Type ch, BL_Fun_Type enable);
void PWM_SW_Force_Value(PWM_CH_ID_Type ch, uint8_t value);
void PWM_Int_Callback_Install(PWM_CH_ID_Type ch, uint32_t intType, intCallback_Type *cbFun);
BL_Err_Type PWM_Smart_Configure(PWM_CH_ID_Type ch, uint32_t frequency, uint8_t dutyCycle);
/*@} end of group PWM_Public_Functions */

12
drivers/bl702_driver/std_drv/inc/bl702_sf_cfg.h
View file

@ -85,14 +85,14 @@
#define BFLB_EXTFLASH_DATA31_GPIO GLB_GPIO_PIN_26
/* Flash option 2 */
/* Flash CLK */
#define BFLB_EXTFLASH_CLK2_GPIO GLB_GPIO_PIN_36
#define BFLB_EXTFLASH_CLK2_GPIO 38
/* FLASH CS */
#define BFLB_EXTFLASH_CS2_GPIO GLB_GPIO_PIN_35
#define BFLB_EXTFLASH_CS2_GPIO 38
/* FLASH DATA */
#define BFLB_EXTFLASH_DATA02_GPIO GLB_GPIO_PIN_32
#define BFLB_EXTFLASH_DATA12_GPIO GLB_GPIO_PIN_34
#define BFLB_EXTFLASH_DATA22_GPIO GLB_GPIO_PIN_33
#define BFLB_EXTFLASH_DATA32_GPIO GLB_GPIO_PIN_37
#define BFLB_EXTFLASH_DATA02_GPIO 38
#define BFLB_EXTFLASH_DATA12_GPIO 38
#define BFLB_EXTFLASH_DATA22_GPIO 38
#define BFLB_EXTFLASH_DATA32_GPIO 38
#define BFLB_FLASH_CFG_SF2_EXT_23_28 0
#define BFLB_FLASH_CFG_SF2_INT_512K 1
#define BFLB_FLASH_CFG_SF2_INT_1M 2

56
drivers/bl702_driver/std_drv/src/bl702_adc.c
View file

@ -522,8 +522,8 @@ void ADC_Parse_Result(uint32_t *orgVal, uint32_t len, ADC_Result_Type *result)
dataType = BL_GET_REG_BITS_VAL(tmpVal1, AON_GPADC_RES_SEL);
sigType = BL_GET_REG_BITS_VAL(tmpVal2, AON_GPADC_DIFF_MODE);
if (BL_GET_REG_BITS_VAL(tmpVal2, AON_GPADC_VREF_SEL) == ADC_VREF_3P3V) {
ref = 3.3;
if (BL_GET_REG_BITS_VAL(tmpVal2, AON_GPADC_VREF_SEL) == ADC_VREF_3P2V) {
ref = 3.2;
}
if (sigType == ADC_INPUT_SINGLE_END) {
@ -572,6 +572,58 @@ void ADC_Parse_Result(uint32_t *orgVal, uint32_t len, ADC_Result_Type *result)
}
}
/****************************************************************************/ /**
* @brief ADC mask or unmask certain or all interrupt
*
* @param intType: interrupt type
* @param intMask: mask or unmask
*
* @return None
*
*******************************************************************************/
BL_Mask_Type ADC_IntGetMask(ADC_INT_Type intType)
{
uint32_t tmpVal;
/* Check the parameters */
CHECK_PARAM(IS_GPIP_ADC_INT_TYPE(intType));
CHECK_PARAM(IS_BL_MASK_TYPE(intMask));
switch (intType) {
case ADC_INT_POS_SATURATION:
tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR);
return BL_IS_REG_BIT_SET(tmpVal, AON_GPADC_POS_SATUR_MASK);
break;
case ADC_INT_NEG_SATURATION:
tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR);
return BL_IS_REG_BIT_SET(tmpVal, AON_GPADC_NEG_SATUR_MASK);
break;
case ADC_INT_FIFO_UNDERRUN:
tmpVal = BL_RD_REG(AON_BASE, GPIP_GPADC_CONFIG);
return BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_MASK);
break;
case ADC_INT_FIFO_OVERRUN:
tmpVal = BL_RD_REG(AON_BASE, GPIP_GPADC_CONFIG);
return BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_FIFO_OVERRUN_MASK);
break;
case ADC_INT_ADC_READY:
tmpVal = BL_RD_REG(AON_BASE, GPIP_GPADC_CONFIG);
return BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_RDY_MASK);
break;
case ADC_INT_FIFO_READY:
tmpVal = BL_RD_REG(AON_BASE, GPIP_GPADC_CONFIG);
return BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_FIFO_RDY_MASK);
break;
default:
break;
}
}
/****************************************************************************/ /**
* @brief ADC mask or unmask certain or all interrupt
*

16
drivers/bl702_driver/std_drv/src/bl702_cam.c
View file

@ -632,6 +632,22 @@ void CAM_Int_Callback_Install(CAM_INT_Type intType, intCallback_Type *cbFun)
camIntCbfArra[intType] = cbFun;
}
/****************************************************************************/ /**
* @brief CAM hardware mode with frame start address wrap to memory address start function enable or disable
*
* @param enable: Enable or disable
* @return None
*
*******************************************************************************/
void CAM_HW_Mode_Wrap(BL_Fun_Type enable)
{
uint32_t tmpVal;
tmpVal = BL_RD_REG(CAM_BASE, CAM_DVP2AXI_CONFIGUE);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_HW_MODE_FWRAP, enable);
BL_WR_REG(CAM_BASE, CAM_DVP2AXI_CONFIGUE, tmpVal);
}
/****************************************************************************/ /**
* @brief Camera interrupt handler
*

4
drivers/bl702_driver/std_drv/src/bl702_emac.c
View file

@ -260,9 +260,9 @@ BL_Err_Type EMAC_Init(EMAC_CFG_Type *cfg)
EMAC_SetMACAddress(cfg->macAddr);
#ifndef BFLB_USE_HAL_DRIVER
void EMAC_IRQHandler(void);
Interrupt_Handler_Register(EMAC_IRQn, EMAC_IRQHandler);
#endif
return SUCCESS;
}

128
drivers/bl702_driver/std_drv/src/bl702_glb.c
View file

@ -3080,6 +3080,7 @@ BL_Err_Type GLB_IR_LED_Driver_Ibias(uint8_t ibias)
BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_Init(GLB_GPIO_Cfg_Type *cfg)
{
uint8_t gpioPin = cfg->gpioPin;
uint8_t realPin;
uint32_t *pOut;
uint32_t pos;
uint32_t tmpOut;
@ -3099,8 +3100,15 @@ BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_Init(GLB_GPIO_Cfg_Type *cfg)
tmpOut &= (~(1 << pos));
*pOut = tmpOut;
tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpioPin / 2 * 4);
if (gpioPin % 2 == 0) {
realPin = gpioPin;
/* sf pad use exclusive ie/pd/pu/drive/smtctrl */
if (gpioPin >= 23 && gpioPin <= 28) {
if ((BL_RD_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO) & (1 << (gpioPin - 23))) > 0) {
realPin += 9;
}
}
tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + realPin / 2 * 4);
if (realPin % 2 == 0) {
if (cfg->gpioMode != GPIO_MODE_ANALOG) {
/* not analog mode */
@ -3173,7 +3181,7 @@ BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_Init(GLB_GPIO_Cfg_Type *cfg)
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_1_SMT, cfg->smtCtrl);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_1_FUNC_SEL, cfg->gpioFun);
}
BL_WR_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpioPin / 2 * 4, tmpVal);
BL_WR_WORD(GLB_BASE + GLB_GPIO_OFFSET + realPin / 2 * 4, tmpVal);
*pOut = tmpOut;
@ -3200,10 +3208,8 @@ BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_Init(GLB_GPIO_Cfg_Type *cfg)
BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
}
if (gpioPin >= 32 && gpioPin <= 37) {
if (BL_RD_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO) & (1 << (gpioPin - 32))) {
gpioPin -= 9;
if (gpioPin >= 23 && gpioPin <= 28) {
if ((BL_RD_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO) & (1 << (gpioPin - 23))) > 0) {
tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpioPin / 2 * 4);
if (gpioPin % 2 == 0) {
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_FUNC_SEL, cfg->gpioFun);
@ -3212,7 +3218,7 @@ BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_Init(GLB_GPIO_Cfg_Type *cfg)
}
BL_WR_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpioPin / 2 * 4, tmpVal);
/* GPIO32-GPIO37 use GPIO23-GPIO28 pinmux&&outputEn */
/* sf pad use GPIO23-GPIO28 pinmux&&outputEn */
pOut = (uint32_t *)(GLB_BASE + GLB_GPIO_OUTPUT_EN_OFFSET + ((gpioPin >> 5) << 2));
pos = gpioPin % 32;
tmpOut = *pOut;
@ -3352,13 +3358,6 @@ BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_OUTPUT_Enable(GLB_GPIO_Type gpioPin)
{
uint32_t tmpVal;
/* GPIO32-GPIO37 use GPIO23-GPIO28 pinmux&&outputEn */
if (gpioPin >= 32 && gpioPin <= 37) {
if (BL_RD_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO) & (1 << (gpioPin - 32))) {
gpioPin -= 9;
}
}
tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_CFGCTL34);
tmpVal = tmpVal | (1 << gpioPin);
BL_WR_REG(GLB_BASE, GLB_GPIO_CFGCTL34, tmpVal);
@ -3378,13 +3377,6 @@ BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_OUTPUT_Disable(GLB_GPIO_Type gpioPin)
{
uint32_t tmpVal;
/* GPIO32-GPIO37 use GPIO23-GPIO28 pinmux&&outputEn */
if (gpioPin >= 32 && gpioPin <= 37) {
if (BL_RD_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO) & (1 << (gpioPin - 32))) {
gpioPin -= 9;
}
}
tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_CFGCTL34);
tmpVal = tmpVal & ~(1 << gpioPin);
BL_WR_REG(GLB_BASE, GLB_GPIO_CFGCTL34, tmpVal);
@ -3419,7 +3411,7 @@ BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_Set_HZ(GLB_GPIO_Type gpioPin)
}
realPin = gpioPin;
/* GPIO32-GPIO37 use exclusive ie/pd/pu/drive/smtctrl */
/* sf pad use exclusive ie/pd/pu/drive/smtctrl */
if (gpioPin >= 23 && gpioPin <= 28) {
if ((BL_RD_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO) & (1 << (gpioPin - 23))) > 0) {
realPin += 9;
@ -3463,6 +3455,78 @@ BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_Set_HZ(GLB_GPIO_Type gpioPin)
return SUCCESS;
}
BL_Err_Type ATTR_TCM_SECTION GLB_Set_Flash_Pad_HZ(void)
{
uint32_t tmpVal;
uint32_t offset;
for(offset=23; offset<=28; offset++){
tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + offset / 2 * 4);
/* pu=0, pd=0, ie=0 */
if (offset % 2 == 0) {
tmpVal = (tmpVal & 0xffffff00);
} else {
tmpVal = (tmpVal & 0xff00ffff);
}
BL_WR_WORD(GLB_BASE + GLB_GPIO_OFFSET + offset / 2 * 4, tmpVal);
if ((BL_RD_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO) & (1 << (offset - 23))) == 0) {
tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + offset / 2 * 4);
/* func_sel=swgpio */
if (offset % 2 == 0) {
tmpVal = (tmpVal & 0xffff00ff);
tmpVal |= 0x0B00;
} else {
tmpVal = (tmpVal & 0x00ffffff);
tmpVal |= (0x0B00 << 16);
}
BL_WR_WORD(GLB_BASE + GLB_GPIO_OFFSET + offset / 2 * 4, tmpVal);
}
}
tmpVal = BL_RD_WORD(GLB_BASE+GLB_GPIO_OUTPUT_EN_OFFSET);
tmpVal &= 0xE07FFFFF;
BL_WR_WORD(GLB_BASE+GLB_GPIO_OUTPUT_EN_OFFSET, tmpVal);
return SUCCESS;
}
BL_Err_Type ATTR_TCM_SECTION GLB_Set_Psram_Pad_HZ(void)
{
uint32_t tmpVal;
uint32_t offset;
for(offset=32; offset<=37; offset++){
tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + offset / 2 * 4);
/* pu=0, pd=0, ie=0 */
if (offset % 2 == 0) {
tmpVal = (tmpVal & 0xffffff00);
} else {
tmpVal = (tmpVal & 0xff00ffff);
}
BL_WR_WORD(GLB_BASE + GLB_GPIO_OFFSET + offset / 2 * 4, tmpVal);
if ((BL_RD_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO) & (1 << (offset - 32))) > 0) {
tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + (offset-9) / 2 * 4);
/* func_sel=swgpio */
if ((offset-9) % 2 == 0) {
tmpVal = (tmpVal & 0xffff00ff);
tmpVal |= 0x0B00;
} else {
tmpVal = (tmpVal & 0x00ffffff);
tmpVal |= (0x0B00 << 16);
}
BL_WR_WORD(GLB_BASE + GLB_GPIO_OFFSET + (offset-9) / 2 * 4, tmpVal);
}
}
tmpVal = BL_RD_WORD(GLB_BASE+GLB_GPIO_OUTPUT_EN_OFFSET+4);
tmpVal &= 0xFFFFFFC0;
BL_WR_WORD(GLB_BASE+GLB_GPIO_OUTPUT_EN_OFFSET+4, tmpVal);
return SUCCESS;
}
/****************************************************************************/ /**
* @brief Get GPIO function
*
@ -3498,11 +3562,6 @@ uint8_t ATTR_TCM_SECTION GLB_GPIO_Get_Fun(GLB_GPIO_Type gpioPin)
*******************************************************************************/
BL_Err_Type GLB_GPIO_Write(GLB_GPIO_Type gpioPin, uint32_t val)
{
if (gpioPin >= 32 && gpioPin <= 37) {
if (BL_RD_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO) & (1 << (gpioPin - 32))) {
gpioPin -= 9;
}
}
uint32_t *pOut = (uint32_t *)(GLB_BASE + GLB_GPIO_OUTPUT_OFFSET + ((gpioPin >> 5) << 2));
uint32_t pos = gpioPin % 32;
uint32_t tmpOut;
@ -3528,11 +3587,6 @@ BL_Err_Type GLB_GPIO_Write(GLB_GPIO_Type gpioPin, uint32_t val)
*******************************************************************************/
uint32_t GLB_GPIO_Read(GLB_GPIO_Type gpioPin)
{
if (gpioPin >= 32 && gpioPin <= 37) {
if (BL_RD_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO) & (1 << (gpioPin - 32))) {
gpioPin -= 9;
}
}
uint32_t *p = (uint32_t *)(GLB_BASE + GLB_GPIO_INPUT_OFFSET + ((gpioPin >> 5) << 2));
uint32_t pos = gpioPin % 32;
@ -3654,7 +3708,7 @@ BL_Err_Type GLB_Set_GPIO_IntMod(GLB_GPIO_Type gpioPin, GLB_GPIO_INT_CONTROL_Type
tmpVal = (tmpVal & ~(0x7 << (3 * tmpGpioPin))) | (((intCtlMod << 2) | intTrgMod) << (3 * tmpGpioPin));
BL_WR_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET3, tmpVal);
} else {
/* GPIO30 ~ GPIO31, GPIO32 ~ GPIO37 not recommend */
/* GPIO30 ~ GPIO31 not recommend */
tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET4);
tmpGpioPin = gpioPin - GLB_GPIO_PIN_30;
tmpVal = (tmpVal & ~(0x7 << (3 * tmpGpioPin))) | (((intCtlMod << 2) | intTrgMod) << (3 * tmpGpioPin));
@ -3696,7 +3750,7 @@ GLB_GPIO_INT_CONTROL_Type GLB_Get_GPIO_IntCtlMod(GLB_GPIO_Type gpioPin)
tmpVal = (tmpVal & (0x7 << (bitVal * 3))) >> (bitVal * 3);
return (tmpVal >> 2) ? GLB_GPIO_INT_CONTROL_ASYNC : GLB_GPIO_INT_CONTROL_SYNC;
} else {
/* GPIO30 ~ GPIO31, GPIO32 ~ GPIO37 not recommend */
/* GPIO30 ~ GPIO31 not recommend */
bitVal = gpioPin - 30;
tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET4);
tmpVal = (tmpVal & (0x7 << (bitVal * 3))) >> (bitVal * 3);
@ -3815,7 +3869,7 @@ BL_Err_Type GLB_Set_GPIO_Int2Mod(GLB_GPIO_Type gpioPin, GLB_GPIO_INT_CONTROL_Typ
tmpVal = (tmpVal & ~(0x7 << (3 * tmpGpioPin))) | (((intCtlMod << 2) | intTrgMod) << (3 * tmpGpioPin));
BL_WR_REG(GLB_BASE, GLB_GPIO_INT2_MODE_SET3, tmpVal);
} else {
/* GPIO30 ~ GPIO31, GPIO32 ~ GPIO37 not recommend */
/* GPIO30 ~ GPIO31 not recommend */
tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT2_MODE_SET4);
tmpGpioPin = gpioPin - GLB_GPIO_PIN_30;
tmpVal = (tmpVal & ~(0x7 << (3 * tmpGpioPin))) | (((intCtlMod << 2) | intTrgMod) << (3 * tmpGpioPin));
@ -3857,7 +3911,7 @@ GLB_GPIO_INT_CONTROL_Type GLB_Get_GPIO_Int2CtlMod(GLB_GPIO_Type gpioPin)
tmpVal = (tmpVal & (0x7 << (bitVal * 3))) >> (bitVal * 3);
return (tmpVal >> 2) ? GLB_GPIO_INT_CONTROL_ASYNC : GLB_GPIO_INT_CONTROL_SYNC;
} else {
/* GPIO30 ~ GPIO31, GPIO32 ~ GPIO37 not recommend */
/* GPIO30 ~ GPIO31 not recommend */
bitVal = gpioPin - 30;
tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT2_MODE_SET4);
tmpVal = (tmpVal & (0x7 << (bitVal * 3))) >> (bitVal * 3);

70
drivers/bl702_driver/std_drv/src/bl702_pwm.c
View file

@ -522,6 +522,76 @@ void PWM_Int_Callback_Install(PWM_CH_ID_Type ch, uint32_t intType, intCallback_T
PWMIntCbfArra[ch][intType] = cbFun;
}
/****************************************************************************/ /**
* @brief PWM smart configure according to frequency and duty cycle function
*
* @param ch: PWM channel number
* @param frequency: PWM frequency
* @param dutyCycle: PWM duty cycle
*
* @return SUCCESS or TIMEOUT
*
*******************************************************************************/
BL_Err_Type PWM_Smart_Configure(PWM_CH_ID_Type ch, uint32_t frequency, uint8_t dutyCycle)
{
uint32_t tmpVal;
uint16_t clkDiv, period, threshold2;
uint32_t timeoutCnt = PWM_STOP_TIMEOUT_COUNT;
/* Get channel register */
uint32_t PWMx = PWM_Get_Channel_Reg(ch);
if (frequency <= 32) {
clkDiv = 500;
period = 64000 / frequency;
threshold2 = 640 * dutyCycle / frequency;
} else if (frequency <= 62) {
clkDiv = 16;
period = 2000000 / frequency;
threshold2 = 20000 * dutyCycle / frequency;
} else if (frequency <= 124) {
clkDiv = 8;
period = 4000000 / frequency;
threshold2 = 40000 * dutyCycle / frequency;
} else if (frequency <= 246) {
clkDiv = 4;
period = 8000000 / frequency;
threshold2 = 80000 * dutyCycle / frequency;
} else if (frequency <= 490) {
clkDiv = 2;
period = 16000000 / frequency;
threshold2 = 160000 * dutyCycle / frequency;
} else {
clkDiv = 1;
period = 32000000 / frequency;
threshold2 = 320000 * dutyCycle / frequency;
}
tmpVal = BL_RD_REG(PWMx, PWM_CONFIG);
if (BL_GET_REG_BITS_VAL(tmpVal, PWM_REG_CLK_SEL) != PWM_CLK_XCLK) {
BL_WR_REG(PWMx, PWM_CONFIG, BL_SET_REG_BIT(tmpVal, PWM_STOP_EN));
while (!BL_IS_REG_BIT_SET(BL_RD_REG(PWMx, PWM_CONFIG), PWM_STS_TOP)) {
timeoutCnt--;
if (timeoutCnt == 0) {
return TIMEOUT;
}
}
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_REG_CLK_SEL, PWM_CLK_XCLK);
}
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_OUT_INV, PWM_POL_NORMAL);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_STOP_MODE, PWM_STOP_GRACEFUL);
BL_WR_REG(PWMx, PWM_CONFIG, tmpVal);
/* Config pwm division */
BL_WR_REG(PWMx, PWM_CLKDIV, clkDiv);
/* Config pwm period and duty */
BL_WR_REG(PWMx, PWM_PERIOD, period);
BL_WR_REG(PWMx, PWM_THRE1, 0);
BL_WR_REG(PWMx, PWM_THRE2, threshold2);
return SUCCESS;
}
/****************************************************************************/ /**
* @brief PWM interrupt function
*