[sync] sync from internal repo

* use nuttx libc, disable system libc
* use tlsf as default
* update lhal flash driver
* add example readme
* add flash ini for new flash tool
* add fw header for new flash tool
This commit is contained in:
jzlv 2023-01-17 20:54:15 +08:00
parent 89592fc9a3
commit 356f258e83
554 changed files with 79150 additions and 46596 deletions

View file

@ -1,5 +1,8 @@
sdk_add_include_directories(.)
target_sources(app PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/board.c)
# target_sources(app PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/fw_header.c)
sdk_set_linker_script(bl602_flash.ld)
sdk_set_linker_script(bl602_flash.ld)
# sdk_add_link_options(-ufw_header)

View file

@ -22,6 +22,7 @@ HeapSize = 0x1000; /* 4KB */
MEMORY
{
fw_header_memory (rx) : ORIGIN = 0x23000000 - 0x1000, LENGTH = 4K
xip_memory (rx) : ORIGIN = 0x23000000, LENGTH = 1024K
itcm_memory (rx) : ORIGIN = 0x22010000, LENGTH = 16K
dtcm_memory (rx) : ORIGIN = 0x42014000, LENGTH = 48K
@ -32,6 +33,11 @@ SECTIONS
{
PROVIDE(__metal_chicken_bit = 0);
.fw_header :
{
KEEP(*(.fw_header))
} > fw_header_memory
.text :
{
. = ALIGN(4);
@ -189,6 +195,10 @@ SECTIONS
*(.sdata2.*)
. = ALIGN(4);
__bflog_tags_start__ = .;
*(.bflog_tags_array)
. = ALIGN(4);
__bflog_tags_end__ = .;
__ram_data_end__ = .;
} > ram_memory

View file

@ -3,27 +3,16 @@
#include "bflb_clock.h"
#include "bflb_rtc.h"
#include "bflb_flash.h"
#ifdef CONFIG_TLSF
#include "bflb_tlsf.h"
#else
#include "bflb_mmheap.h"
#endif
#include "board.h"
#include "bl602_glb.h"
#include "bl602_sflash.h"
#include "mem.h"
extern void log_start(void);
extern uint32_t __HeapBase;
extern uint32_t __HeapLimit;
#ifndef CONFIG_TLSF
struct heap_info mmheap_root;
static struct heap_region system_mmheap[] = {
{ NULL, 0 },
{ NULL, 0 }, /* Terminates the array. */
};
#endif
static struct bflb_device_s *uart0;
#if defined(CONFIG_BFLOG)
@ -72,7 +61,7 @@ void bl_show_log(void)
void bl_show_flashinfo(void)
{
SPI_Flash_Cfg_Type flashCfg;
spi_flash_cfg_type flashCfg;
uint8_t *pFlashCfg = NULL;
uint32_t flashCfgLen = 0;
uint32_t flashJedecId = 0;
@ -83,17 +72,17 @@ void bl_show_flashinfo(void)
printf("=========== flash cfg ==============\r\n");
printf("jedec id 0x%06X\r\n", flashJedecId);
printf("mid 0x%02X\r\n", flashCfg.mid);
printf("iomode 0x%02X\r\n", flashCfg.ioMode);
printf("clk delay 0x%02X\r\n", flashCfg.clkDelay);
printf("clk invert 0x%02X\r\n", flashCfg.clkInvert);
printf("read reg cmd0 0x%02X\r\n", flashCfg.readRegCmd[0]);
printf("read reg cmd1 0x%02X\r\n", flashCfg.readRegCmd[1]);
printf("write reg cmd0 0x%02X\r\n", flashCfg.writeRegCmd[0]);
printf("write reg cmd1 0x%02X\r\n", flashCfg.writeRegCmd[1]);
printf("qe write len 0x%02X\r\n", flashCfg.qeWriteRegLen);
printf("cread support 0x%02X\r\n", flashCfg.cReadSupport);
printf("cread code 0x%02X\r\n", flashCfg.cReadMode);
printf("burst wrap cmd 0x%02X\r\n", flashCfg.burstWrapCmd);
printf("iomode 0x%02X\r\n", flashCfg.io_mode);
printf("clk delay 0x%02X\r\n", flashCfg.clk_delay);
printf("clk invert 0x%02X\r\n", flashCfg.clk_invert);
printf("read reg cmd0 0x%02X\r\n", flashCfg.read_reg_cmd[0]);
printf("read reg cmd1 0x%02X\r\n", flashCfg.read_reg_cmd[1]);
printf("write reg cmd0 0x%02X\r\n", flashCfg.write_reg_cmd[0]);
printf("write reg cmd1 0x%02X\r\n", flashCfg.write_reg_cmd[1]);
printf("qe write len 0x%02X\r\n", flashCfg.qe_write_reg_len);
printf("cread support 0x%02X\r\n", flashCfg.c_read_support);
printf("cread code 0x%02X\r\n", flashCfg.c_read_mode);
printf("burst wrap cmd 0x%02X\r\n", flashCfg.burst_wrap_cmd);
printf("=====================================\r\n");
}
@ -124,40 +113,38 @@ static void console_init()
void board_init(void)
{
int ret = -1;
uintptr_t flag;
flag = bflb_irq_save();
bflb_flash_init();
ret = bflb_flash_init();
system_clock_init();
peripheral_clock_init();
bflb_irq_initialize();
bflb_irq_restore(flag);
#ifdef CONFIG_TLSF
bflb_mmheap_init((void *)&__HeapBase, ((size_t)&__HeapLimit - (size_t)&__HeapBase));
#else
system_mmheap[0].addr = (uint8_t *)&__HeapBase;
system_mmheap[0].mem_size = ((size_t)&__HeapLimit - (size_t)&__HeapBase);
if (system_mmheap[0].mem_size > 0) {
bflb_mmheap_init(&mmheap_root, system_mmheap);
}
#endif
console_init();
size_t heap_len = ((size_t)&__HeapLimit - (size_t)&__HeapBase);
kmem_init((void *)&__HeapBase, heap_len);
bl_show_log();
if (ret != 0) {
printf("flash init fail!!!\r\n");
}
bl_show_flashinfo();
printf("dynamic memory init success,heap size = %d Kbyte \r\n", ((size_t)&__HeapLimit - (size_t)&__HeapBase) / 1024);
printf("cgen1:%08x\r\n", getreg32(BFLB_GLB_CGEN1_BASE));
log_start();
#if defined(CONFIG_BFLOG)
rtc = bflb_device_get_by_name("rtc");
#endif
bflb_irq_restore(flag);
}
void board_uartx_gpio_init()
@ -251,4 +238,4 @@ __attribute__((weak)) char *bflog_thread(void)
{
return "";
}
#endif
#endif

View file

@ -0,0 +1,118 @@
#include "fw_header.h"
__attribute__((section(".fw_header"))) struct bootheader_t fw_header = {
.magiccode = 0x504e4642,
.rivison = 0x00000001,
/*flash config */
.flash_cfg.magiccode = 0x47464346,
.flash_cfg.cfg.ioMode = 0x11, /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */
.flash_cfg.cfg.cReadSupport = 0x00, /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */
.flash_cfg.cfg.clkDelay = 0x01, /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */
.flash_cfg.cfg.clkInvert = 0x01, /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */
.flash_cfg.cfg.resetEnCmd = 0x66, /*!< Flash enable reset command */
.flash_cfg.cfg.resetCmd = 0x99, /*!< Flash reset command */
.flash_cfg.cfg.resetCreadCmd = 0xff, /*!< Flash reset continuous read command */
.flash_cfg.cfg.resetCreadCmdSize = 0x03, /*!< Flash reset continuous read command size */
.flash_cfg.cfg.jedecIdCmd = 0x9f, /*!< JEDEC ID command */
.flash_cfg.cfg.jedecIdCmdDmyClk = 0x00, /*!< JEDEC ID command dummy clock */
.flash_cfg.cfg.enter32BitsAddrCmd = 0xb7, /*!< Enter 32-bits addr command */
.flash_cfg.cfg.exit32BitsAddrCmd = 0xe9, /*!< Exit 32-bits addr command */
.flash_cfg.cfg.sectorSize = 0x04, /*!< *1024bytes */
.flash_cfg.cfg.mid = 0xff, /*!< Manufacturer ID */
.flash_cfg.cfg.pageSize = 0x100, /*!< Page size */
.flash_cfg.cfg.chipEraseCmd = 0xc7, /*!< Chip erase cmd */
.flash_cfg.cfg.sectorEraseCmd = 0x20, /*!< Sector erase command */
.flash_cfg.cfg.blk32EraseCmd = 0x52, /*!< Block 32K erase command,some Micron not support */
.flash_cfg.cfg.blk64EraseCmd = 0xd8, /*!< Block 64K erase command */
.flash_cfg.cfg.writeEnableCmd = 0x06, /*!< Need before every erase or program */
.flash_cfg.cfg.pageProgramCmd = 0x02, /*!< Page program cmd */
.flash_cfg.cfg.qpageProgramCmd = 0x32, /*!< QIO page program cmd */
.flash_cfg.cfg.qppAddrMode = 0x00, /*!< QIO page program address mode */
.flash_cfg.cfg.fastReadCmd = 0x0b, /*!< Fast read command */
.flash_cfg.cfg.frDmyClk = 0x01, /*!< Fast read command dummy clock */
.flash_cfg.cfg.qpiFastReadCmd = 0x0b, /*!< QPI fast read command */
.flash_cfg.cfg.qpiFrDmyClk = 0x01, /*!< QPI fast read command dummy clock */
.flash_cfg.cfg.fastReadDoCmd = 0x3b, /*!< Fast read dual output command */
.flash_cfg.cfg.frDoDmyClk = 0x01, /*!< Fast read dual output command dummy clock */
.flash_cfg.cfg.fastReadDioCmd = 0xbb, /*!< Fast read dual io comamnd */
.flash_cfg.cfg.frDioDmyClk = 0x00, /*!< Fast read dual io command dummy clock */
.flash_cfg.cfg.fastReadQoCmd = 0x6b, /*!< Fast read quad output comamnd */
.flash_cfg.cfg.frQoDmyClk = 0x01, /*!< Fast read quad output comamnd dummy clock */
.flash_cfg.cfg.fastReadQioCmd = 0xeb, /*!< Fast read quad io comamnd */
.flash_cfg.cfg.frQioDmyClk = 0x02, /*!< Fast read quad io comamnd dummy clock */
.flash_cfg.cfg.qpiFastReadQioCmd = 0xeb, /*!< QPI fast read quad io comamnd */
.flash_cfg.cfg.qpiFrQioDmyClk = 0x02, /*!< QPI fast read QIO dummy clock */
.flash_cfg.cfg.qpiPageProgramCmd = 0x02, /*!< QPI program command */
.flash_cfg.cfg.writeVregEnableCmd = 0x50, /*!< Enable write reg */
.flash_cfg.cfg.wrEnableIndex = 0x00, /*!< Write enable register index */
.flash_cfg.cfg.qeIndex = 0x01, /*!< Quad mode enable register index */
.flash_cfg.cfg.busyIndex = 0x00, /*!< Busy status register index */
.flash_cfg.cfg.wrEnableBit = 0x01, /*!< Write enable bit pos */
.flash_cfg.cfg.qeBit = 0x01, /*!< Quad enable bit pos */
.flash_cfg.cfg.busyBit = 0x00, /*!< Busy status bit pos */
.flash_cfg.cfg.wrEnableWriteRegLen = 0x02, /*!< Register length of write enable */
.flash_cfg.cfg.wrEnableReadRegLen = 0x01, /*!< Register length of write enable status */
.flash_cfg.cfg.qeWriteRegLen = 0x02, /*!< Register length of contain quad enable */
.flash_cfg.cfg.qeReadRegLen = 0x01, /*!< Register length of contain quad enable status */
.flash_cfg.cfg.releasePowerDown = 0xab, /*!< Release power down command */
.flash_cfg.cfg.busyReadRegLen = 0x01, /*!< Register length of contain busy status */
.flash_cfg.cfg.readRegCmd[0] = 0x05, /*!< Read register command buffer */
.flash_cfg.cfg.readRegCmd[1] = 0x35, /*!< Read register command buffer */
.flash_cfg.cfg.readRegCmd[2] = 0x00, /*!< Read register command buffer */
.flash_cfg.cfg.readRegCmd[3] = 0x00, /*!< Read register command buffer */
.flash_cfg.cfg.writeRegCmd[0] = 0x01, /*!< Write register command buffer */
.flash_cfg.cfg.writeRegCmd[1] = 0x01, /*!< Write register command buffer */
.flash_cfg.cfg.writeRegCmd[2] = 0x00, /*!< Write register command buffer */
.flash_cfg.cfg.writeRegCmd[3] = 0x00, /*!< Write register command buffer */
.flash_cfg.cfg.enterQpi = 0x38, /*!< Enter qpi command */
.flash_cfg.cfg.exitQpi = 0xff, /*!< Exit qpi command */
.flash_cfg.cfg.cReadMode = 0xa0, /*!< Config data for continuous read mode */
.flash_cfg.cfg.cRExit = 0xff, /*!< Config data for exit continuous read mode */
.flash_cfg.cfg.burstWrapCmd = 0x77, /*!< Enable burst wrap command */
.flash_cfg.cfg.burstWrapCmdDmyClk = 0x03, /*!< Enable burst wrap command dummy clock */
.flash_cfg.cfg.burstWrapDataMode = 0x02, /*!< Data and address mode for this command */
.flash_cfg.cfg.burstWrapData = 0x40, /*!< Data to enable burst wrap */
.flash_cfg.cfg.deBurstWrapCmd = 0x77, /*!< Disable burst wrap command */
.flash_cfg.cfg.deBurstWrapCmdDmyClk = 0x03, /*!< Disable burst wrap command dummy clock */
.flash_cfg.cfg.deBurstWrapDataMode = 0x02, /*!< Data and address mode for this command */
.flash_cfg.cfg.deBurstWrapData = 0xf0, /*!< Data to disable burst wrap */
.flash_cfg.cfg.timeEsector = 300, /*!< 4K erase time */
.flash_cfg.cfg.timeE32k = 1200, /*!< 32K erase time */
.flash_cfg.cfg.timeE64k = 1200, /*!< 64K erase time */
.flash_cfg.cfg.timePagePgm = 50, /*!< Page program time */
.flash_cfg.cfg.timeCe = 30000, /*!< Chip erase time in ms */
.flash_cfg.cfg.pdDelay = 20, /*!< Release power down command delay time for wake up */
.flash_cfg.cfg.qeData = 0, /*!< QE set data */
.flash_cfg.crc32 = 0xdeadbeef,
/* clock cfg */
.clk_cfg.magiccode = 0x47464350,
.clk_cfg.cfg.xtal_type = 0x04, /*!< 0:None,1:24M,2:32M,3:38.4M,4:40M,5:26M,6:RC32M */
.clk_cfg.cfg.pll_clk = 0x04, /*!< mcu_clk 0:RC32M,1:XTAL,2:PLL 48M,3:PLL 120M,4:PLL 160M,5:PLL 192M */
.clk_cfg.cfg.hclk_div = 0x00,
.clk_cfg.cfg.bclk_div = 0x01,
.clk_cfg.cfg.flash_clk_type = 0x03, /*!< 0:120M,1:XCLK(RC32M or XTAL),2:48M,3:80M,4:BCLK,5:96M */
.clk_cfg.cfg.flash_clk_div = 0x01,
.clk_cfg.crc32 = 0xdeadbeef,
/* boot cfg */
.boot_cfg.bval.sign = 0x0, /* [1: 0] for sign*/
.boot_cfg.bval.encrypt_type = 0x0, /* [3: 2] for encrypt */
.boot_cfg.bval.key_sel = 0x0, /* [5: 4] for key sel in boot interface*/
.boot_cfg.bval.rsvd6_7 = 0x0, /* [7: 6] for encrypt*/
.boot_cfg.bval.no_segment = 0x1, /* [8] no segment info */
.boot_cfg.bval.cache_select = 0x1, /* [9] for cache */
.boot_cfg.bval.notload_in_bootrom = 0x0, /* [10] not load this img in bootrom */
.boot_cfg.bval.aes_region_lock = 0x0, /* [11] aes region lock */
.boot_cfg.bval.cache_way_disable = 0x3, /* [15: 12] cache way disable info*/
.boot_cfg.bval.crc_ignore = 0x1, /* [16] ignore crc */
.boot_cfg.bval.hash_ignore = 0x1, /* [17] hash crc */
.boot_cfg.bval.halt_ap = 0x0, /* [18] halt ap */
.boot_cfg.bval.rsvd19_31 = 0x0, /* [31:19] rsvd */
.img_segment_info.img_len = 0x00010000, /* image length or segment count */
.rsvd0 = 0x00000000,
.img_start.flashoffset = 0x00001000, /* flash controller offset */
.hash = { 0xdeadbeef }, /* hash of the image */
.crc32 = 0xdeadbeef /* 4 */
};

View file

@ -0,0 +1,165 @@
#ifndef __FW_HEADER_H__
#define __FW_HEADER_H__
#include "stdint.h"
#include "stdio.h"
struct __attribute__((packed, aligned(4))) spi_flash_cfg_t {
uint8_t ioMode; /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */
uint8_t cReadSupport; /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */
uint8_t clkDelay; /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */
uint8_t clkInvert; /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */
uint8_t resetEnCmd; /*!< Flash enable reset command */
uint8_t resetCmd; /*!< Flash reset command */
uint8_t resetCreadCmd; /*!< Flash reset continuous read command */
uint8_t resetCreadCmdSize; /*!< Flash reset continuous read command size */
uint8_t jedecIdCmd; /*!< JEDEC ID command */
uint8_t jedecIdCmdDmyClk; /*!< JEDEC ID command dummy clock */
uint8_t enter32BitsAddrCmd; /*!< Enter 32-bits addr command */
uint8_t exit32BitsAddrCmd; /*!< Exit 32-bits addr command */
uint8_t sectorSize; /*!< *1024bytes */
uint8_t mid; /*!< Manufacturer ID */
uint16_t pageSize; /*!< Page size */
uint8_t chipEraseCmd; /*!< Chip erase cmd */
uint8_t sectorEraseCmd; /*!< Sector erase command */
uint8_t blk32EraseCmd; /*!< Block 32K erase command,some Micron not support */
uint8_t blk64EraseCmd; /*!< Block 64K erase command */
uint8_t writeEnableCmd; /*!< Need before every erase or program */
uint8_t pageProgramCmd; /*!< Page program cmd */
uint8_t qpageProgramCmd; /*!< QIO page program cmd */
uint8_t qppAddrMode; /*!< QIO page program address mode */
uint8_t fastReadCmd; /*!< Fast read command */
uint8_t frDmyClk; /*!< Fast read command dummy clock */
uint8_t qpiFastReadCmd; /*!< QPI fast read command */
uint8_t qpiFrDmyClk; /*!< QPI fast read command dummy clock */
uint8_t fastReadDoCmd; /*!< Fast read dual output command */
uint8_t frDoDmyClk; /*!< Fast read dual output command dummy clock */
uint8_t fastReadDioCmd; /*!< Fast read dual io comamnd */
uint8_t frDioDmyClk; /*!< Fast read dual io command dummy clock */
uint8_t fastReadQoCmd; /*!< Fast read quad output comamnd */
uint8_t frQoDmyClk; /*!< Fast read quad output comamnd dummy clock */
uint8_t fastReadQioCmd; /*!< Fast read quad io comamnd */
uint8_t frQioDmyClk; /*!< Fast read quad io comamnd dummy clock */
uint8_t qpiFastReadQioCmd; /*!< QPI fast read quad io comamnd */
uint8_t qpiFrQioDmyClk; /*!< QPI fast read QIO dummy clock */
uint8_t qpiPageProgramCmd; /*!< QPI program command */
uint8_t writeVregEnableCmd; /*!< Enable write reg */
uint8_t wrEnableIndex; /*!< Write enable register index */
uint8_t qeIndex; /*!< Quad mode enable register index */
uint8_t busyIndex; /*!< Busy status register index */
uint8_t wrEnableBit; /*!< Write enable bit pos */
uint8_t qeBit; /*!< Quad enable bit pos */
uint8_t busyBit; /*!< Busy status bit pos */
uint8_t wrEnableWriteRegLen; /*!< Register length of write enable */
uint8_t wrEnableReadRegLen; /*!< Register length of write enable status */
uint8_t qeWriteRegLen; /*!< Register length of contain quad enable */
uint8_t qeReadRegLen; /*!< Register length of contain quad enable status */
uint8_t releasePowerDown; /*!< Release power down command */
uint8_t busyReadRegLen; /*!< Register length of contain busy status */
uint8_t readRegCmd[4]; /*!< Read register command buffer */
uint8_t writeRegCmd[4]; /*!< Write register command buffer */
uint8_t enterQpi; /*!< Enter qpi command */
uint8_t exitQpi; /*!< Exit qpi command */
uint8_t cReadMode; /*!< Config data for continuous read mode */
uint8_t cRExit; /*!< Config data for exit continuous read mode */
uint8_t burstWrapCmd; /*!< Enable burst wrap command */
uint8_t burstWrapCmdDmyClk; /*!< Enable burst wrap command dummy clock */
uint8_t burstWrapDataMode; /*!< Data and address mode for this command */
uint8_t burstWrapData; /*!< Data to enable burst wrap */
uint8_t deBurstWrapCmd; /*!< Disable burst wrap command */
uint8_t deBurstWrapCmdDmyClk; /*!< Disable burst wrap command dummy clock */
uint8_t deBurstWrapDataMode; /*!< Data and address mode for this command */
uint8_t deBurstWrapData; /*!< Data to disable burst wrap */
uint16_t timeEsector; /*!< 4K erase time */
uint16_t timeE32k; /*!< 32K erase time */
uint16_t timeE64k; /*!< 64K erase time */
uint16_t timePagePgm; /*!< Page program time */
uint16_t timeCe; /*!< Chip erase time in ms */
uint8_t pdDelay; /*!< Release power down command delay time for wake up */
uint8_t qeData; /*!< QE set data */
};
struct __attribute__((packed, aligned(4))) boot_flash_cfg_t {
uint32_t magiccode;
struct spi_flash_cfg_t cfg;
uint32_t crc32;
};
struct __attribute__((packed, aligned(4))) sys_clk_cfg_t {
uint8_t xtal_type;
uint8_t pll_clk;
uint8_t hclk_div;
uint8_t bclk_div;
uint8_t flash_clk_type;
uint8_t flash_clk_div;
uint8_t rsvd[2];
};
struct __attribute__((packed, aligned(4))) boot_clk_cfg_t {
uint32_t magiccode;
struct sys_clk_cfg_t cfg;
uint32_t crc32;
};
struct __attribute__((packed, aligned(4))) aesiv_cfg_t {
uint8_t aesiv[16];
uint32_t crc32;
};
struct __attribute__((packed, aligned(4))) pkey_cfg_t {
uint8_t eckeyx[32]; /* ec key in boot header */
uint8_t eckeyy[32]; /* ec key in boot header */
uint32_t crc32;
};
struct __attribute__((packed, aligned(4))) sign_cfg_t {
uint32_t sig_len;
uint8_t signature[32];
uint32_t crc32;
};
struct __attribute__((packed, aligned(4))) bootheader_t {
uint32_t magiccode; /* 4 */
uint32_t rivison; /* 4 */
struct boot_flash_cfg_t flash_cfg; /* 4 + 84 + 4 */
struct boot_clk_cfg_t clk_cfg; /* 4 + 8 + 4 */
union __attribute__((packed, aligned(1))) {
struct __attribute__((packed, aligned(1))) {
uint32_t sign : 2; /* [1: 0] for sign*/
uint32_t encrypt_type : 2; /* [3: 2] for encrypt */
uint32_t key_sel : 2; /* [5: 4] for key sel in boot interface*/
uint32_t rsvd6_7 : 2; /* [7: 6] for encrypt*/
uint32_t no_segment : 1; /* [8] no segment info */
uint32_t cache_select : 1; /* [9] for cache */
uint32_t notload_in_bootrom : 1; /* [10] not load this img in bootrom */
uint32_t aes_region_lock : 1; /* [11] aes region lock */
uint32_t cache_way_disable : 4; /* [15: 12] cache way disable info*/
uint32_t crc_ignore : 1; /* [16] ignore crc */
uint32_t hash_ignore : 1; /* [17] hash crc */
uint32_t halt_ap : 1; /* [18] halt ap */
uint32_t rsvd19_31 : 13; /* [31:19] rsvd */
} bval;
uint32_t wval;
} boot_cfg; /* 4 */
union __attribute__((packed, aligned(1))) {
uint32_t segment_cnt;
uint32_t img_len;
} img_segment_info; /* 4 */
uint32_t rsvd0; /* rsvd */
union __attribute__((packed, aligned(1))) {
uint32_t ramaddr;
uint32_t flashoffset;
} img_start; /* 4 */
uint32_t hash[32 / 4]; /*hash of the image*/
uint32_t rsv1;
uint32_t rsv2;
uint32_t crc32;
};
#endif

View file

@ -1,9 +1,12 @@
sdk_add_include_directories(.)
target_sources(app PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/board.c)
# target_sources(app PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/fw_header.c)
sdk_set_linker_script(bl616_flash.ld)
if(CONFIG_PSRAM)
sdk_add_compile_definitions(-DCONFIG_PSRAM)
endif()
endif()
# sdk_add_link_options(-ufw_header)

View file

@ -17,29 +17,59 @@ INPUT(-lgcc)
/* configure the entry point */
ENTRY(__start)
StackSize = 0x1000; /* 1KB */
StackSize = 0x1000; /* 4KB */
HeapMinSize = 0x1000; /* 4KB */
__EM_SIZE = DEFINED(btble_controller_init) ? 32K : 0K;
__RFTLV_SIZE_OFFSET = 1K;
__RFTLV_SIZE_HOLE = 2K;
__RFTLV_HEAD1_H = (0x46524C42); /* BLRF */
__RFTLV_HEAD1_L = (0x41524150); /* PAPA */
MEMORY
{
fw_header_memory (rx) : ORIGIN = 0xA0000000 - 0x1000, LENGTH = 4K
xip_memory (rx) : ORIGIN = 0xA0000000, LENGTH = 4M
ram_code (wxa) : ORIGIN = 0xA8000000, LENGTH = 4M
itcm_memory (rx) : ORIGIN = 0x62FC0000, LENGTH = 20K
dtcm_memory (rx) : ORIGIN = 0x62FC5000, LENGTH = 4K
nocache_ram_memory (!rx) : ORIGIN = 0x22FC6000, LENGTH = 44K+60K
ram_memory (!rx) : ORIGIN = 0x62FE0000 , LENGTH = 320K+160K-20K-4K-44K-60K
ram_memory (!rx) : ORIGIN = 0x62FE0000, LENGTH = 320K-20K-4K-44K-60K
ram_wifi (wxa) : ORIGIN = 0x23010000, LENGTH = 160K - __EM_SIZE
}
SECTIONS
{
BOOT2_PT_ADDR = 0x63027c00;
.fw_header :
{
KEEP(*(.fw_header))
} > fw_header_memory
.init :
{
*(.text.entry)
KEEP (*(SORT_NONE(.init)))
KEEP (*(SORT_NONE(.vector)))
} > xip_memory
.rftlv.tool :
{
. = ORIGIN(xip_memory) + __RFTLV_SIZE_OFFSET;
PROVIDE( _ld_symbol_rftlv_address = . );
LONG(__RFTLV_HEAD1_H);
LONG(__RFTLV_HEAD1_L);
. = ORIGIN(xip_memory) + __RFTLV_SIZE_OFFSET + __RFTLV_SIZE_HOLE;
} > xip_memory
.text :
{
. = ALIGN(4);
__text_code_start__ = .;
KEEP (*(SORT_NONE(.init)))
KEEP (*(SORT_NONE(.vector)))
*(.text)
*(.text.*)
@ -139,7 +169,9 @@ SECTIONS
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __tcm_data_end__, "region RAM overflowed with stack")
/*************************************************************************/
__nocache_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region);
.nocache_ram_region : AT (__nocache_ram_load_addr)
@ -192,6 +224,10 @@ SECTIONS
*(.sdata2.*)
. = ALIGN(4);
__bflog_tags_start__ = .;
*(.bflog_tags_array)
. = ALIGN(4);
__bflog_tags_end__ = .;
__ram_data_end__ = .;
} > ram_memory
@ -250,5 +286,42 @@ SECTIONS
__HeapLimit = ORIGIN(ram_memory) + LENGTH(ram_memory);
ASSERT(__HeapLimit - __HeapBase >= HeapMinSize, "heap region overflow")
.psmram_data (NOLOAD):
{
. = ALIGN(4);
__psram_data_start__ = .;
/*__end__ = .;*/
/*end = __end__;*/
KEEP(*(.psram_data*))
. = ALIGN(4);
__psram_data_end__ = .;
} > ram_code
.wifibss (NOLOAD) :
{
PROVIDE( __wifi_bss_start = ADDR(.wifibss) );
PROVIDE( __wifi_bss_end = ADDR(.wifibss) + SIZEOF(.wifibss) );
_sshram = . ;
*(SHAREDRAMIPC)
*(SHAREDRAM)
_eshram = . ;
*ipc_shared.o(COMMON)
*sdu_shared.o(COMMON)
*hal_desc.o(COMMON)
*txl_buffer_shared.o(COMMON)
*txl_frame_shared.o(COMMON)
*scan_shared.o(COMMON)
*scanu_shared.o(COMMON)
*mfp_bip.o(COMMON)
*me_mic.o(COMMON)
*(.wifi_ram*)
. = ALIGN(16);
} > ram_wifi
PROVIDE( _heap_wifi_start = . );
PROVIDE( _heap_wifi_size = ORIGIN(ram_wifi) + LENGTH(ram_wifi) - _heap_wifi_start );
}

View file

@ -3,16 +3,12 @@
#include "bflb_clock.h"
#include "bflb_rtc.h"
#include "bflb_flash.h"
#ifdef CONFIG_TLSF
#include "bflb_tlsf.h"
#else
#include "bflb_mmheap.h"
#endif
#include "board.h"
#include "bl616_tzc_sec.h"
#include "bl616_psram.h"
#include "bl616_glb.h"
#include "bl616_sflash.h"
#include "mem.h"
#define WB_4MB_PSRAM (1)
@ -20,18 +16,11 @@
#include "sdh_sdcard.h"
#endif
extern void log_start(void);
extern uint32_t __HeapBase;
extern uint32_t __HeapLimit;
#ifndef CONFIG_TLSF
struct heap_info mmheap_root;
static struct heap_region system_mmheap[] = {
{ NULL, 0 },
{ NULL, 0 }, /* Terminates the array. */
};
#endif
static struct bflb_device_s *uart0;
#if (defined(CONFIG_LUA) || defined(CONFIG_BFLOG) || defined(CONFIG_FATFS))
@ -40,10 +29,18 @@ static struct bflb_device_s *rtc;
static void system_clock_init(void)
{
#if 1
/* wifipll/audiopll */
GLB_Power_On_XTAL_And_PLL_CLK(GLB_XTAL_40M, GLB_PLL_WIFIPLL | GLB_PLL_AUPLL);
GLB_Set_MCU_System_CLK(GLB_MCU_SYS_CLK_TOP_WIFIPLL_320M);
CPU_Set_MTimer_CLK(ENABLE, BL_MTIMER_SOURCE_CLOCK_MCU_CLK, Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MCU_CLK) / 1000000 - 1);
#else
GLB_Set_MCU_System_CLK(GLB_MCU_SYS_CLK_RC32M);
GLB_Power_On_XTAL_And_PLL_CLK(GLB_XTAL_40M, GLB_PLL_WIFIPLL);
GLB_Config_AUDIO_PLL_To_384M();
GLB_Set_MCU_System_CLK(GLB_MCU_SYS_CLK_TOP_AUPLL_DIV1);
GLB_Set_MCU_System_CLK_Div(0, 3);
#endif
CPU_Set_MTimer_CLK(ENABLE, BL_MTIMER_SOURCE_CLOCK_MCU_XCLK, Clock_System_Clock_Get(BL_SYSTEM_CLOCK_XCLK) / 1000000 - 1);
}
static void peripheral_clock_init(void)
@ -110,7 +107,7 @@ static void psram_winbond_default_init(void)
.PASR = PSRAM_PARTIAL_REFRESH_FULL,
.disDeepPowerDownMode = ENABLE,
.fixedLatency = DISABLE,
.brustLen = PSRAM_WINBOND_BURST_LENGTH_32_BYTES,
.brustLen = PSRAM_WINBOND_BURST_LENGTH_64_BYTES,
.brustType = PSRAM_WRAPPED_BURST,
.latency = PSRAM_WINBOND_6_CLOCKS_LATENCY,
.driveStrength = PSRAM_WINBOND_DRIVE_STRENGTH_35_OHMS_FOR_4M_115_OHMS_FOR_8M,
@ -152,7 +149,7 @@ void bl_show_log(void)
void bl_show_flashinfo(void)
{
SPI_Flash_Cfg_Type flashCfg;
spi_flash_cfg_type flashCfg;
uint8_t *pFlashCfg = NULL;
uint32_t flashCfgLen = 0;
uint32_t flashJedecId = 0;
@ -163,17 +160,17 @@ void bl_show_flashinfo(void)
printf("=========== flash cfg ==============\r\n");
printf("jedec id 0x%06X\r\n", flashJedecId);
printf("mid 0x%02X\r\n", flashCfg.mid);
printf("iomode 0x%02X\r\n", flashCfg.ioMode);
printf("clk delay 0x%02X\r\n", flashCfg.clkDelay);
printf("clk invert 0x%02X\r\n", flashCfg.clkInvert);
printf("read reg cmd0 0x%02X\r\n", flashCfg.readRegCmd[0]);
printf("read reg cmd1 0x%02X\r\n", flashCfg.readRegCmd[1]);
printf("write reg cmd0 0x%02X\r\n", flashCfg.writeRegCmd[0]);
printf("write reg cmd1 0x%02X\r\n", flashCfg.writeRegCmd[1]);
printf("qe write len 0x%02X\r\n", flashCfg.qeWriteRegLen);
printf("cread support 0x%02X\r\n", flashCfg.cReadSupport);
printf("cread code 0x%02X\r\n", flashCfg.cReadMode);
printf("burst wrap cmd 0x%02X\r\n", flashCfg.burstWrapCmd);
printf("iomode 0x%02X\r\n", flashCfg.io_mode);
printf("clk delay 0x%02X\r\n", flashCfg.clk_delay);
printf("clk invert 0x%02X\r\n", flashCfg.clk_invert);
printf("read reg cmd0 0x%02X\r\n", flashCfg.read_reg_cmd[0]);
printf("read reg cmd1 0x%02X\r\n", flashCfg.read_reg_cmd[1]);
printf("write reg cmd0 0x%02X\r\n", flashCfg.write_reg_cmd[0]);
printf("write reg cmd1 0x%02X\r\n", flashCfg.write_reg_cmd[1]);
printf("qe write len 0x%02X\r\n", flashCfg.qe_write_reg_len);
printf("cread support 0x%02X\r\n", flashCfg.c_read_support);
printf("cread code 0x%02X\r\n", flashCfg.c_read_mode);
printf("burst wrap cmd 0x%02X\r\n", flashCfg.burst_wrap_cmd);
printf("=====================================\r\n");
}
@ -204,31 +201,26 @@ static void console_init()
void board_init(void)
{
int ret = -1;
uintptr_t flag;
flag = bflb_irq_save();
bflb_flash_init();
ret = bflb_flash_init();
system_clock_init();
peripheral_clock_init();
bflb_irq_initialize();
bflb_irq_restore(flag);
#ifdef CONFIG_TLSF
bflb_mmheap_init((void *)&__HeapBase, ((size_t)&__HeapLimit - (size_t)&__HeapBase));
#else
system_mmheap[0].addr = (uint8_t *)&__HeapBase;
system_mmheap[0].mem_size = ((size_t)&__HeapLimit - (size_t)&__HeapBase);
if (system_mmheap[0].mem_size > 0) {
bflb_mmheap_init(&mmheap_root, system_mmheap);
}
#endif
console_init();
size_t heap_len = ((size_t)&__HeapLimit - (size_t)&__HeapBase);
kmem_init((void *)&__HeapBase, heap_len);
bl_show_log();
if (ret != 0) {
printf("flash init fail!!!\r\n");
}
bl_show_flashinfo();
printf("dynamic memory init success,heap size = %d Kbyte \r\n", ((size_t)&__HeapLimit - (size_t)&__HeapBase) / 1024);
@ -237,6 +229,8 @@ void board_init(void)
printf("sig2:%08x\r\n", BL_RD_REG(GLB_BASE, GLB_UART_CFG2));
printf("cgen1:%08x\r\n", getreg32(BFLB_GLB_CGEN1_BASE));
log_start();
#if (defined(CONFIG_LUA) || defined(CONFIG_BFLOG) || defined(CONFIG_FATFS))
rtc = bflb_device_get_by_name("rtc");
#endif
@ -245,6 +239,8 @@ void board_init(void)
board_psram_x8_init();
Tzc_Sec_PSRAMB_Access_Release();
#endif
bflb_irq_restore(flag);
}
void board_uartx_gpio_init()
@ -438,6 +434,17 @@ void board_dvp_gpio_init(void)
#endif
}
void board_i2s_gpio_init()
{
struct bflb_device_s *gpio;
gpio = bflb_device_get_by_name("gpio");
bflb_gpio_init(gpio, GPIO_PIN_16, GPIO_FUNC_I2S | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
bflb_gpio_init(gpio, GPIO_PIN_17, GPIO_FUNC_I2S | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
bflb_gpio_init(gpio, GPIO_PIN_18, GPIO_FUNC_I2S | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
bflb_gpio_init(gpio, GPIO_PIN_19, GPIO_FUNC_I2S | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
}
void board_iso11898_gpio_init()
{
// struct bflb_device_s *gpio;
@ -494,4 +501,14 @@ __attribute__((weak)) uint32_t get_fattime(void)
| ((uint32_t)tm.min << 5) /* Min 0 */
| ((uint32_t)tm.sec >> 1); /* Sec 0 */
}
#endif
#endif
#ifdef CONFIG_SHELL
#include "shell.h"
static void reboot_cmd(int argc, char **argv)
{
GLB_SW_POR_Reset();
}
SHELL_CMD_EXPORT_ALIAS(reboot_cmd, reboot, reboot);
#endif

View file

@ -13,6 +13,7 @@ void board_emac_gpio_init();
void board_sdh_gpio_init();
void board_ir_gpio_init();
void board_dvp_gpio_init();
void board_i2s_gpio_init();
void board_iso11898_gpio_init();
#define DEFAULT_TEST_UART "uart1"

View file

@ -0,0 +1,165 @@
#include "fw_header.h"
__attribute__((section(".fw_header"))) struct bootheader_t fw_header = {
.magiccode = 0x504e4642,
.rivison = 0x00000001,
/*flash config */
.flash_cfg.magiccode = 0x47464346,
.flash_cfg.cfg.ioMode = 0x11, /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */
.flash_cfg.cfg.cReadSupport = 0x00, /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */
.flash_cfg.cfg.clkDelay = 0x01, /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */
.flash_cfg.cfg.clkInvert = 0x01, /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */
.flash_cfg.cfg.resetEnCmd = 0x66, /*!< Flash enable reset command */
.flash_cfg.cfg.resetCmd = 0x99, /*!< Flash reset command */
.flash_cfg.cfg.resetCreadCmd = 0xff, /*!< Flash reset continuous read command */
.flash_cfg.cfg.resetCreadCmdSize = 0x03, /*!< Flash reset continuous read command size */
.flash_cfg.cfg.jedecIdCmd = 0x9f, /*!< JEDEC ID command */
.flash_cfg.cfg.jedecIdCmdDmyClk = 0x00, /*!< JEDEC ID command dummy clock */
.flash_cfg.cfg.enter32BitsAddrCmd = 0xb7, /*!< Enter 32-bits addr command */
.flash_cfg.cfg.exit32BitsAddrCmd = 0xe9, /*!< Exit 32-bits addr command */
.flash_cfg.cfg.sectorSize = 0x04, /*!< *1024bytes */
.flash_cfg.cfg.mid = 0x00, /*!< Manufacturer ID */
.flash_cfg.cfg.pageSize = 0x100, /*!< Page size */
.flash_cfg.cfg.chipEraseCmd = 0xc7, /*!< Chip erase cmd */
.flash_cfg.cfg.sectorEraseCmd = 0x20, /*!< Sector erase command */
.flash_cfg.cfg.blk32EraseCmd = 0x52, /*!< Block 32K erase command,some Micron not support */
.flash_cfg.cfg.blk64EraseCmd = 0xd8, /*!< Block 64K erase command */
.flash_cfg.cfg.writeEnableCmd = 0x06, /*!< Need before every erase or program */
.flash_cfg.cfg.pageProgramCmd = 0x02, /*!< Page program cmd */
.flash_cfg.cfg.qpageProgramCmd = 0x32, /*!< QIO page program cmd */
.flash_cfg.cfg.qppAddrMode = 0x00, /*!< QIO page program address mode */
.flash_cfg.cfg.fastReadCmd = 0x0b, /*!< Fast read command */
.flash_cfg.cfg.frDmyClk = 0x01, /*!< Fast read command dummy clock */
.flash_cfg.cfg.qpiFastReadCmd = 0x0b, /*!< QPI fast read command */
.flash_cfg.cfg.qpiFrDmyClk = 0x01, /*!< QPI fast read command dummy clock */
.flash_cfg.cfg.fastReadDoCmd = 0x3b, /*!< Fast read dual output command */
.flash_cfg.cfg.frDoDmyClk = 0x01, /*!< Fast read dual output command dummy clock */
.flash_cfg.cfg.fastReadDioCmd = 0xbb, /*!< Fast read dual io comamnd */
.flash_cfg.cfg.frDioDmyClk = 0x00, /*!< Fast read dual io command dummy clock */
.flash_cfg.cfg.fastReadQoCmd = 0x6b, /*!< Fast read quad output comamnd */
.flash_cfg.cfg.frQoDmyClk = 0x01, /*!< Fast read quad output comamnd dummy clock */
.flash_cfg.cfg.fastReadQioCmd = 0xeb, /*!< Fast read quad io comamnd */
.flash_cfg.cfg.frQioDmyClk = 0x02, /*!< Fast read quad io comamnd dummy clock */
.flash_cfg.cfg.qpiFastReadQioCmd = 0xeb, /*!< QPI fast read quad io comamnd */
.flash_cfg.cfg.qpiFrQioDmyClk = 0x02, /*!< QPI fast read QIO dummy clock */
.flash_cfg.cfg.qpiPageProgramCmd = 0x02, /*!< QPI program command */
.flash_cfg.cfg.writeVregEnableCmd = 0x50, /*!< Enable write reg */
.flash_cfg.cfg.wrEnableIndex = 0x00, /*!< Write enable register index */
.flash_cfg.cfg.qeIndex = 0x01, /*!< Quad mode enable register index */
.flash_cfg.cfg.busyIndex = 0x00, /*!< Busy status register index */
.flash_cfg.cfg.wrEnableBit = 0x01, /*!< Write enable bit pos */
.flash_cfg.cfg.qeBit = 0x01, /*!< Quad enable bit pos */
.flash_cfg.cfg.busyBit = 0x00, /*!< Busy status bit pos */
.flash_cfg.cfg.wrEnableWriteRegLen = 0x02, /*!< Register length of write enable */
.flash_cfg.cfg.wrEnableReadRegLen = 0x01, /*!< Register length of write enable status */
.flash_cfg.cfg.qeWriteRegLen = 0x02, /*!< Register length of contain quad enable */
.flash_cfg.cfg.qeReadRegLen = 0x01, /*!< Register length of contain quad enable status */
.flash_cfg.cfg.releasePowerDown = 0xab, /*!< Release power down command */
.flash_cfg.cfg.busyReadRegLen = 0x01, /*!< Register length of contain busy status */
.flash_cfg.cfg.readRegCmd[0] = 0x05, /*!< Read register command buffer */
.flash_cfg.cfg.readRegCmd[1] = 0x35, /*!< Read register command buffer */
.flash_cfg.cfg.readRegCmd[2] = 0x00, /*!< Read register command buffer */
.flash_cfg.cfg.readRegCmd[3] = 0x00, /*!< Read register command buffer */
.flash_cfg.cfg.writeRegCmd[0] = 0x01, /*!< Write register command buffer */
.flash_cfg.cfg.writeRegCmd[1] = 0x01, /*!< Write register command buffer */
.flash_cfg.cfg.writeRegCmd[2] = 0x00, /*!< Write register command buffer */
.flash_cfg.cfg.writeRegCmd[3] = 0x00, /*!< Write register command buffer */
.flash_cfg.cfg.enterQpi = 0x38, /*!< Enter qpi command */
.flash_cfg.cfg.exitQpi = 0xff, /*!< Exit qpi command */
.flash_cfg.cfg.cReadMode = 0x20, /*!< Config data for continuous read mode */
.flash_cfg.cfg.cRExit = 0xf0, /*!< Config data for exit continuous read mode */
.flash_cfg.cfg.burstWrapCmd = 0x77, /*!< Enable burst wrap command */
.flash_cfg.cfg.burstWrapCmdDmyClk = 0x03, /*!< Enable burst wrap command dummy clock */
.flash_cfg.cfg.burstWrapDataMode = 0x02, /*!< Data and address mode for this command */
.flash_cfg.cfg.burstWrapData = 0x40, /*!< Data to enable burst wrap */
.flash_cfg.cfg.deBurstWrapCmd = 0x77, /*!< Disable burst wrap command */
.flash_cfg.cfg.deBurstWrapCmdDmyClk = 0x03, /*!< Disable burst wrap command dummy clock */
.flash_cfg.cfg.deBurstWrapDataMode = 0x02, /*!< Data and address mode for this command */
.flash_cfg.cfg.deBurstWrapData = 0xf0, /*!< Data to disable burst wrap */
.flash_cfg.cfg.timeEsector = 300, /*!< 4K erase time */
.flash_cfg.cfg.timeE32k = 1200, /*!< 32K erase time */
.flash_cfg.cfg.timeE64k = 1200, /*!< 64K erase time */
.flash_cfg.cfg.timePagePgm = 50, /*!< Page program time */
.flash_cfg.cfg.timeCe = 30000, /*!< Chip erase time in ms */
.flash_cfg.cfg.pdDelay = 20, /*!< Release power down command delay time for wake up */
.flash_cfg.cfg.qeData = 0, /*!< QE set data */
.flash_cfg.crc32 = 0xdeadbeef,
/* clock cfg */
.clk_cfg.magiccode = 0x47464350,
.clk_cfg.cfg.xtal_type = 0x07, /*!< 0:None,1:24M,2:32M,3:38.4M,4:40M,5:26M,6:RC32M */
.clk_cfg.cfg.mcu_clk = 0x05, /*!< mcu_clk 0:RC32M;1:XTAL;2:aupll_div2;3:aupll_div1;4:wifipll_240M;5:wifipll_320M */
.clk_cfg.cfg.mcu_clk_div = 0x00, /*!< mcu_clk divider */
.clk_cfg.cfg.mcu_bclk_div = 0x00, /*!< mcu_bclk divider */
.clk_cfg.cfg.mcu_pbclk_div = 0x03, /*!< mcu_pclk divider */
.clk_cfg.cfg.emi_clk = 0x02, /*!< 0:mcu pbclk,1:cpupll 200M,2:wifipll 320M,3:cpupll 400M */
.clk_cfg.cfg.emi_clk_div = 0x01, /*!< emi clock divider */
.clk_cfg.cfg.flash_clk_type = 0x01, /*!< 0:wifipll_120M;1:xtal;2:aupll_div5;3:muxpll_80M;4:bclk;5:wifipll_96M */
.clk_cfg.cfg.flash_clk_div = 0x00,
.clk_cfg.cfg.wifipll_pu = 0x01,
.clk_cfg.cfg.aupll_pu = 0x00,
.clk_cfg.crc32 = 0xdeadbeef,
/* basic cfg */
.basic_cfg.sign_type = 0x0, /* [1: 0] for sign */
.basic_cfg.encrypt_type = 0x0, /* [3: 2] for encrypt */
.basic_cfg.key_sel = 0x0, /* [5: 4] key slot */
.basic_cfg.xts_mode = 0x0, /* [6] for xts mode */
.basic_cfg.aes_region_lock = 0x0, /* [7] rsvd */
.basic_cfg.no_segment = 0x1, /* [8] no segment info */
.basic_cfg.rsvd_0 = 0x0, /* [9] boot2 enable(rsvd_0) */
.basic_cfg.rsvd_1 = 0x0, /* [10] boot2 rollback(rsvd_1) */
.basic_cfg.cpu_master_id = 0x0, /* [14: 11] master id */
.basic_cfg.notload_in_bootrom = 0x0, /* [15] notload in bootrom */
.basic_cfg.crc_ignore = 0x1, /* [16] ignore crc */
.basic_cfg.hash_ignore = 0x1, /* [17] hash ignore */
.basic_cfg.power_on_mm = 0x1, /* [18] power on mm */
.basic_cfg.em_sel = 0x1, /* [21: 19] em_sel */
.basic_cfg.cmds_en = 0x1, /* [22] command spliter enable */
#if 0
# 0 : cmds bypass wrap commands to macro, original mode;
# 1 : cmds handle wrap commands, original mode;
# 2 : cmds bypass wrap commands to macro, cmds force wrap16 * 4 splitted into two wrap8 * 4;
# 3 : cmds handle wrap commands, cmds force wrap16 * 4 splitted into two wrap8 * 4
#endif
.basic_cfg.cmds_wrap_mode = 0x1, /* [24: 23] cmds wrap mode */
#if 0
# 0 : SF_CTRL_WRAP_LEN_8, 1 : SF_CTRL_WRAP_LEN_16, 2 : SF_CTRL_WRAP_LEN_32,
# 3 : SF_CTRL_WRAP_LEN_64, 9 : SF_CTRL_WRAP_LEN_4096
#endif
.basic_cfg.cmds_wrap_len = 0x9, /* [28: 25] cmds wrap len */
.basic_cfg.icache_invalid = 0x1, /* [29] icache invalid */
.basic_cfg.dcache_invalid = 0x1, /* [30] dcache invalid */
.basic_cfg.rsvd_3 = 0x0, /* [31] rsvd_3 */
.basic_cfg.group_image_offset = 0x00001000, /* flash controller offset */
.basic_cfg.aes_region_len = 0x00000000, /* aes region length */
.basic_cfg.img_len_cnt = 0x00010000, /* image length or segment count */
.basic_cfg.hash = { 0xdeadbeef }, /* hash of the image */
/* cpu cfg */
.cpu_cfg.config_enable = 0x01, /* coinfig this cpu */
.cpu_cfg.halt_cpu = 0x0, /* halt this cpu */
.cpu_cfg.cache_enable = 0x0, /* cache setting :only for BL Cache */
.cpu_cfg.cache_wa = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg.cache_wb = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg.cache_wt = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg.cache_way_dis = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg.rsvd = 0x0,
/* image_address_offset */
.cpu_cfg.image_address_offset = 0x0,
.cpu_cfg.rsvd1 = 0xA0000000, /* rsvd */
.cpu_cfg.msp_val = 0x00000000, /* msp value */
/* address of partition table 0 */
.boot2_pt_table_0_rsvd = 0x00000000,
/* address of partition table 1 */
.boot2_pt_table_1_rsvd = 0x00000000,
/* address of flashcfg table list */
.flash_cfg_table_addr = 0x00000000,
/* flashcfg table list len */
.flash_cfg_table_len = 0x00000000,
.crc32 = 0xdeadbeef
};

View file

@ -0,0 +1,197 @@
#ifndef __FW_HEADER_H__
#define __FW_HEADER_H__
#include "stdint.h"
#include "stdio.h"
struct __attribute__((packed, aligned(4))) spi_flash_cfg_t {
uint8_t ioMode; /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */
uint8_t cReadSupport; /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */
uint8_t clkDelay; /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */
uint8_t clkInvert; /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */
uint8_t resetEnCmd; /*!< Flash enable reset command */
uint8_t resetCmd; /*!< Flash reset command */
uint8_t resetCreadCmd; /*!< Flash reset continuous read command */
uint8_t resetCreadCmdSize; /*!< Flash reset continuous read command size */
uint8_t jedecIdCmd; /*!< JEDEC ID command */
uint8_t jedecIdCmdDmyClk; /*!< JEDEC ID command dummy clock */
uint8_t enter32BitsAddrCmd; /*!< Enter 32-bits addr command */
uint8_t exit32BitsAddrCmd; /*!< Exit 32-bits addr command */
uint8_t sectorSize; /*!< *1024bytes */
uint8_t mid; /*!< Manufacturer ID */
uint16_t pageSize; /*!< Page size */
uint8_t chipEraseCmd; /*!< Chip erase cmd */
uint8_t sectorEraseCmd; /*!< Sector erase command */
uint8_t blk32EraseCmd; /*!< Block 32K erase command,some Micron not support */
uint8_t blk64EraseCmd; /*!< Block 64K erase command */
uint8_t writeEnableCmd; /*!< Need before every erase or program */
uint8_t pageProgramCmd; /*!< Page program cmd */
uint8_t qpageProgramCmd; /*!< QIO page program cmd */
uint8_t qppAddrMode; /*!< QIO page program address mode */
uint8_t fastReadCmd; /*!< Fast read command */
uint8_t frDmyClk; /*!< Fast read command dummy clock */
uint8_t qpiFastReadCmd; /*!< QPI fast read command */
uint8_t qpiFrDmyClk; /*!< QPI fast read command dummy clock */
uint8_t fastReadDoCmd; /*!< Fast read dual output command */
uint8_t frDoDmyClk; /*!< Fast read dual output command dummy clock */
uint8_t fastReadDioCmd; /*!< Fast read dual io comamnd */
uint8_t frDioDmyClk; /*!< Fast read dual io command dummy clock */
uint8_t fastReadQoCmd; /*!< Fast read quad output comamnd */
uint8_t frQoDmyClk; /*!< Fast read quad output comamnd dummy clock */
uint8_t fastReadQioCmd; /*!< Fast read quad io comamnd */
uint8_t frQioDmyClk; /*!< Fast read quad io comamnd dummy clock */
uint8_t qpiFastReadQioCmd; /*!< QPI fast read quad io comamnd */
uint8_t qpiFrQioDmyClk; /*!< QPI fast read QIO dummy clock */
uint8_t qpiPageProgramCmd; /*!< QPI program command */
uint8_t writeVregEnableCmd; /*!< Enable write reg */
uint8_t wrEnableIndex; /*!< Write enable register index */
uint8_t qeIndex; /*!< Quad mode enable register index */
uint8_t busyIndex; /*!< Busy status register index */
uint8_t wrEnableBit; /*!< Write enable bit pos */
uint8_t qeBit; /*!< Quad enable bit pos */
uint8_t busyBit; /*!< Busy status bit pos */
uint8_t wrEnableWriteRegLen; /*!< Register length of write enable */
uint8_t wrEnableReadRegLen; /*!< Register length of write enable status */
uint8_t qeWriteRegLen; /*!< Register length of contain quad enable */
uint8_t qeReadRegLen; /*!< Register length of contain quad enable status */
uint8_t releasePowerDown; /*!< Release power down command */
uint8_t busyReadRegLen; /*!< Register length of contain busy status */
uint8_t readRegCmd[4]; /*!< Read register command buffer */
uint8_t writeRegCmd[4]; /*!< Write register command buffer */
uint8_t enterQpi; /*!< Enter qpi command */
uint8_t exitQpi; /*!< Exit qpi command */
uint8_t cReadMode; /*!< Config data for continuous read mode */
uint8_t cRExit; /*!< Config data for exit continuous read mode */
uint8_t burstWrapCmd; /*!< Enable burst wrap command */
uint8_t burstWrapCmdDmyClk; /*!< Enable burst wrap command dummy clock */
uint8_t burstWrapDataMode; /*!< Data and address mode for this command */
uint8_t burstWrapData; /*!< Data to enable burst wrap */
uint8_t deBurstWrapCmd; /*!< Disable burst wrap command */
uint8_t deBurstWrapCmdDmyClk; /*!< Disable burst wrap command dummy clock */
uint8_t deBurstWrapDataMode; /*!< Data and address mode for this command */
uint8_t deBurstWrapData; /*!< Data to disable burst wrap */
uint16_t timeEsector; /*!< 4K erase time */
uint16_t timeE32k; /*!< 32K erase time */
uint16_t timeE64k; /*!< 64K erase time */
uint16_t timePagePgm; /*!< Page program time */
uint16_t timeCe; /*!< Chip erase time in ms */
uint8_t pdDelay; /*!< Release power down command delay time for wake up */
uint8_t qeData; /*!< QE set data */
};
struct __attribute__((packed, aligned(4))) boot_flash_cfg_t {
uint32_t magiccode;
struct spi_flash_cfg_t cfg;
uint32_t crc32;
};
struct __attribute__((packed, aligned(4))) sys_clk_cfg_t {
uint8_t xtal_type;
uint8_t mcu_clk;
uint8_t mcu_clk_div;
uint8_t mcu_bclk_div;
uint8_t mcu_pbclk_div;
uint8_t emi_clk;
uint8_t emi_clk_div;
uint8_t flash_clk_type;
uint8_t flash_clk_div;
uint8_t wifipll_pu;
uint8_t aupll_pu;
uint8_t rsvd0;
};
struct __attribute__((packed, aligned(4))) boot_clk_cfg_t {
uint32_t magiccode;
struct sys_clk_cfg_t cfg;
uint32_t crc32;
};
struct __attribute__((packed, aligned(4))) boot_basic_cfg_t {
uint32_t sign_type : 2; /* [1: 0] for sign */
uint32_t encrypt_type : 2; /* [3: 2] for encrypt */
uint32_t key_sel : 2; /* [5: 4] key slot */
uint32_t xts_mode : 1; /* [6] for xts mode */
uint32_t aes_region_lock : 1; /* [7] rsvd */
uint32_t no_segment : 1; /* [8] no segment info */
uint32_t rsvd_0 : 1; /* [9] boot2 enable(rsvd_0) */
uint32_t rsvd_1 : 1; /* [10] boot2 rollback(rsvd_1) */
uint32_t cpu_master_id : 4; /* [14: 11] master id */
uint32_t notload_in_bootrom : 1; /* [15] notload in bootrom */
uint32_t crc_ignore : 1; /* [16] ignore crc */
uint32_t hash_ignore : 1; /* [17] hash ignore */
uint32_t power_on_mm : 1; /* [18] power on mm */
uint32_t em_sel : 3; /* [21: 19] em_sel */
uint32_t cmds_en : 1; /* [22] command spliter enable */
uint32_t cmds_wrap_mode : 2; /* [24: 23] cmds wrap mode */
uint32_t cmds_wrap_len : 4; /* [28: 25] cmds wrap len */
uint32_t icache_invalid : 1; /* [29] icache invalid */
uint32_t dcache_invalid : 1; /* [30] dcache invalid */
uint32_t rsvd_3 : 1; /* [31] rsvd_3 */
uint32_t group_image_offset; /* flash controller offset */
uint32_t aes_region_len; /* aes region length */
uint32_t img_len_cnt; /* image length or segment count */
uint32_t hash[32 / 4]; /* hash of the image */
};
struct __attribute__((packed, aligned(4))) boot_cpu_cfg_t {
uint8_t config_enable; /* coinfig this cpu */
uint8_t halt_cpu; /* halt this cpu */
uint8_t cache_enable : 1; /* cache setting */
uint8_t cache_wa : 1; /* cache setting */
uint8_t cache_wb : 1; /* cache setting */
uint8_t cache_wt : 1; /* cache setting */
uint8_t cache_way_dis : 4; /* cache setting */
uint8_t rsvd;
uint32_t image_address_offset; /* image_address_offset */
uint32_t rsvd1; /* rsvd */
uint32_t msp_val; /* msp value */
};
struct __attribute__((packed, aligned(4))) aesiv_cfg_t {
uint8_t aesiv[16];
uint32_t crc32;
};
struct __attribute__((packed, aligned(4))) pkey_cfg_t {
uint8_t eckeyx[32]; /* ec key in boot header */
uint8_t eckeyy[32]; /* ec key in boot header */
uint32_t crc32;
};
struct __attribute__((packed, aligned(4))) sign_cfg_t {
uint32_t sig_len;
uint8_t signature[32];
uint32_t crc32;
};
struct __attribute__((packed, aligned(4))) bootheader_t {
uint32_t magiccode; /* 4 */
uint32_t rivison; /* 4 */
struct boot_flash_cfg_t flash_cfg; /* 4 + 84 + 4 */
struct boot_clk_cfg_t clk_cfg; /* 4 + 12 + 4 */
struct boot_basic_cfg_t basic_cfg; /* 4 + 4 + 4 + 4 + 4*8 */
struct boot_cpu_cfg_t cpu_cfg; /* 16 */
uint32_t boot2_pt_table_0_rsvd; /* address of partition table 0 */ /* 4 */
uint32_t boot2_pt_table_1_rsvd; /* address of partition table 1 */ /* 4 */
uint32_t flash_cfg_table_addr; /* address of flashcfg table list */ /* 4 */
uint32_t flash_cfg_table_len; /* flashcfg table list len */ /* 4 */
uint32_t rsvd0[6]; /* rsvd */
uint32_t rsvd1[6]; /* rsvd */
uint32_t rsvd; /* 4 */
uint32_t crc32; /* 4 */
};
#endif

View file

@ -1,9 +1,12 @@
sdk_add_include_directories(.)
target_sources(app PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/board.c)
# target_sources(app PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/fw_header.c)
sdk_set_linker_script(bl702_flash.ld)
if(CONFIG_PSRAM)
sdk_add_compile_definitions(-DCONFIG_PSRAM)
endif()
endif()
# sdk_add_link_options(-ufw_header)

View file

@ -21,6 +21,7 @@ StackSize = 0x1000; /* 4KB */
MEMORY
{
fw_header_memory (rx) : ORIGIN = 0x23000000 - 0x1000, LENGTH = 4K
xip_memory (rx) : ORIGIN = 0x23000000, LENGTH = 1024K
itcm_memory (rx) : ORIGIN = 0x22014000, LENGTH = 12K
dtcm_memory (rx) : ORIGIN = 0x42017000, LENGTH = 4K
@ -32,6 +33,11 @@ SECTIONS
{
PROVIDE(__metal_chicken_bit = 0);
.fw_header :
{
KEEP(*(.fw_header))
} > fw_header_memory
.text :
{
. = ALIGN(4);
@ -183,6 +189,10 @@ SECTIONS
*(.sdata2.*)
. = ALIGN(4);
__bflog_tags_start__ = .;
*(.bflog_tags_array)
. = ALIGN(4);
__bflog_tags_end__ = .;
__ram_data_end__ = .;
} > ram_memory

View file

@ -3,28 +3,17 @@
#include "bflb_clock.h"
#include "bflb_rtc.h"
#include "bflb_flash.h"
#ifdef CONFIG_TLSF
#include "bflb_tlsf.h"
#else
#include "bflb_mmheap.h"
#endif
#include "board.h"
#include "bflb_spi_psram.h"
#include "bl702_glb.h"
#include "bl702_sflash.h"
#include "bl702_psram.h"
#include "board.h"
#include "mem.h"
extern void log_start(void);
extern uint32_t __HeapBase;
extern uint32_t __HeapLimit;
#ifndef CONFIG_TLSF
struct heap_info mmheap_root;
static struct heap_region system_mmheap[] = {
{ NULL, 0 },
{ NULL, 0 }, /* Terminates the array. */
};
#endif
static struct bflb_device_s *uart0;
#if defined(CONFIG_BFLOG)
@ -51,7 +40,7 @@ static void peripheral_clock_init(void)
PERIPHERAL_CLOCK_IR_ENABLE();
PERIPHERAL_CLOCK_I2S_ENABLE();
PERIPHERAL_CLOCK_USB_ENABLE();
GLB_AHB_Slave1_Clock_Gate(DISABLE,BL_AHB_SLAVE1_CAM);
GLB_AHB_Slave1_Clock_Gate(DISABLE, BL_AHB_SLAVE1_CAM);
GLB_Set_UART_CLK(ENABLE, HBN_UART_CLK_96M, 0);
GLB_Set_SPI_CLK(ENABLE, 0);
@ -66,45 +55,46 @@ static void peripheral_clock_init(void)
/* bsp sf psram private variables */
SPI_Psram_Cfg_Type apMemory1604 = {
.readIdCmd = 0x9F,
.readIdDmyClk = 0,
.burstToggleCmd = 0xC0,
.resetEnableCmd = 0x66,
.resetCmd = 0x99,
.enterQuadModeCmd = 0x35,
.exitQuadModeCmd = 0xF5,
.readRegCmd = 0xB5,
.readRegDmyClk = 1,
.writeRegCmd = 0xB1,
.readCmd = 0x03,
.readDmyClk = 0,
.fReadCmd = 0x0B,
.fReadDmyClk = 1,
.fReadQuadCmd = 0xEB,
.fReadQuadDmyClk = 3,
.writeCmd = 0x02,
.quadWriteCmd = 0x38,
.pageSize = 512,
.ctrlMode = PSRAM_SPI_CTRL_MODE,
.driveStrength = PSRAM_DRIVE_STRENGTH_50_OHMS,
.burstLength = PSRAM_BURST_LENGTH_512_BYTES,
struct spi_psram_cfg_type ap_memory1604 = {
.read_id_cmd = 0x9F,
.read_id_dmy_clk = 0,
.burst_toggle_cmd = 0xC0,
.reset_enable_cmd = 0x66,
.reset_cmd = 0x99,
.enter_quad_mode_cmd = 0x35,
.exit_quad_mode_cmd = 0xF5,
.read_reg_cmd = 0xB5,
.read_reg_dmy_clk = 1,
.write_reg_cmd = 0xB1,
.read_cmd = 0x03,
.read_dmy_clk = 0,
.f_read_cmd = 0x0B,
.f_read_dmy_clk = 1,
.f_read_quad_cmd = 0xEB,
.f_read_quad_dmy_clk = 3,
.write_cmd = 0x02,
.quad_write_cmd = 0x38,
.page_size = 512,
.ctrl_mode = PSRAM_SPI_CTRL_MODE,
.drive_strength = PSRAM_DRIVE_STRENGTH_50_OHMS,
.burst_length = PSRAM_BURST_LENGTH_512_BYTES,
};
SF_Ctrl_Cmds_Cfg cmdsCfg = {
.cmdsEn = ENABLE,
.burstToggleEn = ENABLE,
.wrapModeEn = DISABLE,
.wrapLen = SF_CTRL_WRAP_LEN_512,
struct sf_ctrl_cmds_cfg cmds_cfg = {
.cmds_core_en = 1,
.cmds_en = 1,
.burst_toggle_en = 1,
.cmds_wrap_mode = 0,
.cmds_wrap_len = SF_CTRL_WRAP_LEN_512,
};
SF_Ctrl_Psram_Cfg sfCtrlPsramCfg = {
struct sf_ctrl_psram_cfg psram_cfg = {
.owner = SF_CTRL_OWNER_SAHB,
.padSel = SF_CTRL_PAD_SEL_DUAL_CS_SF2,
.bankSel = SF_CTRL_SEL_PSRAM,
.psramRxClkInvertSrc = ENABLE,
.psramRxClkInvertSel = DISABLE,
.psramDelaySrc = ENABLE,
.psramClkDelay = 1,
.pad_sel = SF_CTRL_SEL_DUAL_CS_SF2,
.bank_sel = SF_CTRL_SEL_PSRAM,
.psram_rx_clk_invert_src = 1,
.psram_rx_clk_invert_sel = 0,
.psram_delay_src = 1,
.psram_clk_delay = 1,
};
#define BFLB_EXTFLASH_CS_GPIO GLB_GPIO_PIN_25
@ -156,12 +146,12 @@ void ATTR_TCM_SECTION board_psram_init(void)
{
psram_gpio_init();
Psram_Init(&apMemory1604, &cmdsCfg, &sfCtrlPsramCfg);
bflb_psram_init(&ap_memory1604, &cmds_cfg, &psram_cfg);
Psram_SoftwareReset(&apMemory1604, apMemory1604.ctrlMode);
bflb_psram_softwarereset(&ap_memory1604, ap_memory1604.ctrl_mode);
Psram_ReadId(&apMemory1604, psramId);
Psram_Cache_Write_Set(&apMemory1604, SF_CTRL_QIO_MODE, ENABLE, DISABLE, DISABLE);
bflb_psram_readid(&ap_memory1604, psramId);
bflb_psram_cache_write_set(&ap_memory1604, SF_CTRL_QIO_MODE, ENABLE, DISABLE, DISABLE);
L1C_Cache_Enable_Set(L1C_WAY_DISABLE_NONE);
}
@ -181,7 +171,7 @@ void bl_show_log(void)
void bl_show_flashinfo(void)
{
SPI_Flash_Cfg_Type flashCfg;
spi_flash_cfg_type flashCfg;
uint8_t *pFlashCfg = NULL;
uint32_t flashCfgLen = 0;
uint32_t flashJedecId = 0;
@ -192,17 +182,17 @@ void bl_show_flashinfo(void)
printf("=========== flash cfg ==============\r\n");
printf("jedec id 0x%06X\r\n", flashJedecId);
printf("mid 0x%02X\r\n", flashCfg.mid);
printf("iomode 0x%02X\r\n", flashCfg.ioMode);
printf("clk delay 0x%02X\r\n", flashCfg.clkDelay);
printf("clk invert 0x%02X\r\n", flashCfg.clkInvert);
printf("read reg cmd0 0x%02X\r\n", flashCfg.readRegCmd[0]);
printf("read reg cmd1 0x%02X\r\n", flashCfg.readRegCmd[1]);
printf("write reg cmd0 0x%02X\r\n", flashCfg.writeRegCmd[0]);
printf("write reg cmd1 0x%02X\r\n", flashCfg.writeRegCmd[1]);
printf("qe write len 0x%02X\r\n", flashCfg.qeWriteRegLen);
printf("cread support 0x%02X\r\n", flashCfg.cReadSupport);
printf("cread code 0x%02X\r\n", flashCfg.cReadMode);
printf("burst wrap cmd 0x%02X\r\n", flashCfg.burstWrapCmd);
printf("iomode 0x%02X\r\n", flashCfg.io_mode);
printf("clk delay 0x%02X\r\n", flashCfg.clk_delay);
printf("clk invert 0x%02X\r\n", flashCfg.clk_invert);
printf("read reg cmd0 0x%02X\r\n", flashCfg.read_reg_cmd[0]);
printf("read reg cmd1 0x%02X\r\n", flashCfg.read_reg_cmd[1]);
printf("write reg cmd0 0x%02X\r\n", flashCfg.write_reg_cmd[0]);
printf("write reg cmd1 0x%02X\r\n", flashCfg.write_reg_cmd[1]);
printf("qe write len 0x%02X\r\n", flashCfg.qe_write_reg_len);
printf("cread support 0x%02X\r\n", flashCfg.c_read_support);
printf("cread code 0x%02X\r\n", flashCfg.c_read_mode);
printf("burst wrap cmd 0x%02X\r\n", flashCfg.burst_wrap_cmd);
printf("=====================================\r\n");
}
@ -233,43 +223,41 @@ static void console_init()
void board_init(void)
{
int ret = -1;
uintptr_t flag;
flag = bflb_irq_save();
bflb_flash_init();
ret = bflb_flash_init();
system_clock_init();
peripheral_clock_init();
bflb_irq_initialize();
bflb_irq_restore(flag);
#ifdef CONFIG_TLSF
bflb_mmheap_init((void *)&__HeapBase, ((size_t)&__HeapLimit - (size_t)&__HeapBase));
#else
system_mmheap[0].addr = (uint8_t *)&__HeapBase;
system_mmheap[0].mem_size = ((size_t)&__HeapLimit - (size_t)&__HeapBase);
if (system_mmheap[0].mem_size > 0) {
bflb_mmheap_init(&mmheap_root, system_mmheap);
}
#endif
console_init();
size_t heap_len = ((size_t)&__HeapLimit - (size_t)&__HeapBase);
kmem_init((void *)&__HeapBase, heap_len);
bl_show_log();
if (ret != 0) {
printf("flash init fail!!!\r\n");
}
bl_show_flashinfo();
printf("dynamic memory init success,heap size = %d Kbyte \r\n", ((size_t)&__HeapLimit - (size_t)&__HeapBase) / 1024);
printf("cgen1:%08x\r\n", getreg32(BFLB_GLB_CGEN1_BASE));
log_start();
#if defined(CONFIG_BFLOG)
rtc = bflb_device_get_by_name("rtc");
#endif
#ifdef CONFIG_PSRAM
board_psram_init();
#endif
bflb_irq_restore(flag);
}
void board_uartx_gpio_init()
@ -441,4 +429,4 @@ __attribute__((weak)) char *bflog_thread(void)
{
return "";
}
#endif
#endif

View file

@ -0,0 +1,122 @@
#include "fw_header.h"
__attribute__((section(".fw_header"))) struct bootheader_t fw_header = {
.magiccode = 0x504e4642,
.rivison = 0x00000001,
/*flash config */
.flash_cfg.magiccode = 0x47464346,
.flash_cfg.cfg.ioMode = 0x11, /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */
.flash_cfg.cfg.cReadSupport = 0x00, /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */
.flash_cfg.cfg.clkDelay = 0x01, /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */
.flash_cfg.cfg.clkInvert = 0x01, /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */
.flash_cfg.cfg.resetEnCmd = 0x66, /*!< Flash enable reset command */
.flash_cfg.cfg.resetCmd = 0x99, /*!< Flash reset command */
.flash_cfg.cfg.resetCreadCmd = 0xff, /*!< Flash reset continuous read command */
.flash_cfg.cfg.resetCreadCmdSize = 0x03, /*!< Flash reset continuous read command size */
.flash_cfg.cfg.jedecIdCmd = 0x9f, /*!< JEDEC ID command */
.flash_cfg.cfg.jedecIdCmdDmyClk = 0x00, /*!< JEDEC ID command dummy clock */
.flash_cfg.cfg.enter32BitsAddrCmd = 0xb7, /*!< Enter 32-bits addr command */
.flash_cfg.cfg.exit32BitsAddrCmd = 0xe9, /*!< Exit 32-bits addr command */
.flash_cfg.cfg.sectorSize = 0x04, /*!< *1024bytes */
.flash_cfg.cfg.mid = 0xff, /*!< Manufacturer ID */
.flash_cfg.cfg.pageSize = 0x100, /*!< Page size */
.flash_cfg.cfg.chipEraseCmd = 0xc7, /*!< Chip erase cmd */
.flash_cfg.cfg.sectorEraseCmd = 0x20, /*!< Sector erase command */
.flash_cfg.cfg.blk32EraseCmd = 0x52, /*!< Block 32K erase command,some Micron not support */
.flash_cfg.cfg.blk64EraseCmd = 0xd8, /*!< Block 64K erase command */
.flash_cfg.cfg.writeEnableCmd = 0x06, /*!< Need before every erase or program */
.flash_cfg.cfg.pageProgramCmd = 0x02, /*!< Page program cmd */
.flash_cfg.cfg.qpageProgramCmd = 0x32, /*!< QIO page program cmd */
.flash_cfg.cfg.qppAddrMode = 0x00, /*!< QIO page program address mode */
.flash_cfg.cfg.fastReadCmd = 0x0b, /*!< Fast read command */
.flash_cfg.cfg.frDmyClk = 0x01, /*!< Fast read command dummy clock */
.flash_cfg.cfg.qpiFastReadCmd = 0x0b, /*!< QPI fast read command */
.flash_cfg.cfg.qpiFrDmyClk = 0x01, /*!< QPI fast read command dummy clock */
.flash_cfg.cfg.fastReadDoCmd = 0x3b, /*!< Fast read dual output command */
.flash_cfg.cfg.frDoDmyClk = 0x01, /*!< Fast read dual output command dummy clock */
.flash_cfg.cfg.fastReadDioCmd = 0xbb, /*!< Fast read dual io comamnd */
.flash_cfg.cfg.frDioDmyClk = 0x00, /*!< Fast read dual io command dummy clock */
.flash_cfg.cfg.fastReadQoCmd = 0x6b, /*!< Fast read quad output comamnd */
.flash_cfg.cfg.frQoDmyClk = 0x01, /*!< Fast read quad output comamnd dummy clock */
.flash_cfg.cfg.fastReadQioCmd = 0xeb, /*!< Fast read quad io comamnd */
.flash_cfg.cfg.frQioDmyClk = 0x02, /*!< Fast read quad io comamnd dummy clock */
.flash_cfg.cfg.qpiFastReadQioCmd = 0xeb, /*!< QPI fast read quad io comamnd */
.flash_cfg.cfg.qpiFrQioDmyClk = 0x02, /*!< QPI fast read QIO dummy clock */
.flash_cfg.cfg.qpiPageProgramCmd = 0x02, /*!< QPI program command */
.flash_cfg.cfg.writeVregEnableCmd = 0x50, /*!< Enable write reg */
.flash_cfg.cfg.wrEnableIndex = 0x00, /*!< Write enable register index */
.flash_cfg.cfg.qeIndex = 0x01, /*!< Quad mode enable register index */
.flash_cfg.cfg.busyIndex = 0x00, /*!< Busy status register index */
.flash_cfg.cfg.wrEnableBit = 0x01, /*!< Write enable bit pos */
.flash_cfg.cfg.qeBit = 0x01, /*!< Quad enable bit pos */
.flash_cfg.cfg.busyBit = 0x00, /*!< Busy status bit pos */
.flash_cfg.cfg.wrEnableWriteRegLen = 0x02, /*!< Register length of write enable */
.flash_cfg.cfg.wrEnableReadRegLen = 0x01, /*!< Register length of write enable status */
.flash_cfg.cfg.qeWriteRegLen = 0x02, /*!< Register length of contain quad enable */
.flash_cfg.cfg.qeReadRegLen = 0x01, /*!< Register length of contain quad enable status */
.flash_cfg.cfg.releasePowerDown = 0xab, /*!< Release power down command */
.flash_cfg.cfg.busyReadRegLen = 0x01, /*!< Register length of contain busy status */
.flash_cfg.cfg.readRegCmd[0] = 0x05, /*!< Read register command buffer */
.flash_cfg.cfg.readRegCmd[1] = 0x35, /*!< Read register command buffer */
.flash_cfg.cfg.readRegCmd[2] = 0x00, /*!< Read register command buffer */
.flash_cfg.cfg.readRegCmd[3] = 0x00, /*!< Read register command buffer */
.flash_cfg.cfg.writeRegCmd[0] = 0x01, /*!< Write register command buffer */
.flash_cfg.cfg.writeRegCmd[1] = 0x01, /*!< Write register command buffer */
.flash_cfg.cfg.writeRegCmd[2] = 0x00, /*!< Write register command buffer */
.flash_cfg.cfg.writeRegCmd[3] = 0x00, /*!< Write register command buffer */
.flash_cfg.cfg.enterQpi = 0x38, /*!< Enter qpi command */
.flash_cfg.cfg.exitQpi = 0xff, /*!< Exit qpi command */
.flash_cfg.cfg.cReadMode = 0xa0, /*!< Config data for continuous read mode */
.flash_cfg.cfg.cRExit = 0xff, /*!< Config data for exit continuous read mode */
.flash_cfg.cfg.burstWrapCmd = 0x77, /*!< Enable burst wrap command */
.flash_cfg.cfg.burstWrapCmdDmyClk = 0x03, /*!< Enable burst wrap command dummy clock */
.flash_cfg.cfg.burstWrapDataMode = 0x02, /*!< Data and address mode for this command */
.flash_cfg.cfg.burstWrapData = 0x40, /*!< Data to enable burst wrap */
.flash_cfg.cfg.deBurstWrapCmd = 0x77, /*!< Disable burst wrap command */
.flash_cfg.cfg.deBurstWrapCmdDmyClk = 0x03, /*!< Disable burst wrap command dummy clock */
.flash_cfg.cfg.deBurstWrapDataMode = 0x02, /*!< Data and address mode for this command */
.flash_cfg.cfg.deBurstWrapData = 0xf0, /*!< Data to disable burst wrap */
.flash_cfg.cfg.timeEsector = 300, /*!< 4K erase time */
.flash_cfg.cfg.timeE32k = 1200, /*!< 32K erase time */
.flash_cfg.cfg.timeE64k = 1200, /*!< 64K erase time */
.flash_cfg.cfg.timePagePgm = 50, /*!< Page program time */
.flash_cfg.cfg.timeCe = 30000, /*!< Chip erase time in ms */
.flash_cfg.cfg.pdDelay = 20, /*!< Release power down command delay time for wake up */
.flash_cfg.cfg.qeData = 0, /*!< QE set data */
.flash_cfg.crc32 = 0xdeadbeef,
/* clock cfg */
.clk_cfg.magiccode = 0x47464350,
.clk_cfg.cfg.xtal_type = 0x01, /*!< 0:Not use XTAL to set PLL, 1:XTAL is 32M, 2:XTAL is RC32M */
.clk_cfg.cfg.pll_clk = 0x04, /*!< mcu_clk 0:RC32M, 1:XTAL, 2:PLL 57.6M, 3:PLL 96M, 4:PLL 144M */
.clk_cfg.cfg.hclk_div = 0x00,
.clk_cfg.cfg.bclk_div = 0x01,
.clk_cfg.cfg.flash_clk_type = 0x01, /*!< 0:144M, 1:XCLK(RC32M or XTAL), 2:57.6M, 3:72M, 4:BCLK, 5:96M */
.clk_cfg.cfg.flash_clk_div = 0x00,
.clk_cfg.crc32 = 0xdeadbeef,
/* boot cfg */
.boot_cfg.bval.sign = 0x0, /* [1: 0] for sign*/
.boot_cfg.bval.encrypt_type = 0x0, /* [3: 2] for encrypt */
.boot_cfg.bval.key_sel = 0x01, /* [5: 4] for key sel in boot interface*/
.boot_cfg.bval.rsvd_7_6 = 0x0, /* [7: 6] for encrypt*/
.boot_cfg.bval.no_segment = 0x1, /* [8] no segment info */
.boot_cfg.bval.cache_select = 0x1, /* [9] for cache */
.boot_cfg.bval.notload_in_bootrom = 0x0, /* [10] not load this img in bootrom */
.boot_cfg.bval.aes_region_lock = 0x0, /* [11] aes region lock */
.boot_cfg.bval.cache_way_disable = 0x0, /* [15: 12] cache way disable info*/
.boot_cfg.bval.crc_ignore = 0x1, /* [16] ignore crc */
.boot_cfg.bval.hash_ignore = 0x1, /* [17] hash crc */
.boot_cfg.bval.halt_ap = 0x0, /* [18] halt ap */
.boot_cfg.bval.boot2_enable = 0x00, /* [19] boot2 enable */
.boot_cfg.bval.boot2_rollback = 0x00, /* [20] boot2 rollback */
.boot_cfg.bval.rsvd_31_21 = 0x0, /* [31:21] rsvd */
.img_segment_info.img_len = 0x00010000, /* image length or segment count */
.rsvd0 = 0x00000000,
.img_start.flashoffset = 0x00001000, /* flash controller offset */
.hash = { 0xdeadbeef }, /* hash of the image */
.boot2_pt_table_0 = 0x1000, /* address of partition table 0 */
.boot2_pt_table_1 = 0x2000, /* address of partition table 1 */
.crc32 = 0xdeadbeef /* 4 */
};

View file

@ -0,0 +1,167 @@
#ifndef __FW_HEADER_H__
#define __FW_HEADER_H__
#include "stdint.h"
#include "stdio.h"
struct __attribute__((packed, aligned(4))) spi_flash_cfg_t {
uint8_t ioMode; /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */
uint8_t cReadSupport; /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */
uint8_t clkDelay; /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */
uint8_t clkInvert; /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */
uint8_t resetEnCmd; /*!< Flash enable reset command */
uint8_t resetCmd; /*!< Flash reset command */
uint8_t resetCreadCmd; /*!< Flash reset continuous read command */
uint8_t resetCreadCmdSize; /*!< Flash reset continuous read command size */
uint8_t jedecIdCmd; /*!< JEDEC ID command */
uint8_t jedecIdCmdDmyClk; /*!< JEDEC ID command dummy clock */
uint8_t enter32BitsAddrCmd; /*!< Enter 32-bits addr command */
uint8_t exit32BitsAddrCmd; /*!< Exit 32-bits addr command */
uint8_t sectorSize; /*!< *1024bytes */
uint8_t mid; /*!< Manufacturer ID */
uint16_t pageSize; /*!< Page size */
uint8_t chipEraseCmd; /*!< Chip erase cmd */
uint8_t sectorEraseCmd; /*!< Sector erase command */
uint8_t blk32EraseCmd; /*!< Block 32K erase command,some Micron not support */
uint8_t blk64EraseCmd; /*!< Block 64K erase command */
uint8_t writeEnableCmd; /*!< Need before every erase or program */
uint8_t pageProgramCmd; /*!< Page program cmd */
uint8_t qpageProgramCmd; /*!< QIO page program cmd */
uint8_t qppAddrMode; /*!< QIO page program address mode */
uint8_t fastReadCmd; /*!< Fast read command */
uint8_t frDmyClk; /*!< Fast read command dummy clock */
uint8_t qpiFastReadCmd; /*!< QPI fast read command */
uint8_t qpiFrDmyClk; /*!< QPI fast read command dummy clock */
uint8_t fastReadDoCmd; /*!< Fast read dual output command */
uint8_t frDoDmyClk; /*!< Fast read dual output command dummy clock */
uint8_t fastReadDioCmd; /*!< Fast read dual io comamnd */
uint8_t frDioDmyClk; /*!< Fast read dual io command dummy clock */
uint8_t fastReadQoCmd; /*!< Fast read quad output comamnd */
uint8_t frQoDmyClk; /*!< Fast read quad output comamnd dummy clock */
uint8_t fastReadQioCmd; /*!< Fast read quad io comamnd */
uint8_t frQioDmyClk; /*!< Fast read quad io comamnd dummy clock */
uint8_t qpiFastReadQioCmd; /*!< QPI fast read quad io comamnd */
uint8_t qpiFrQioDmyClk; /*!< QPI fast read QIO dummy clock */
uint8_t qpiPageProgramCmd; /*!< QPI program command */
uint8_t writeVregEnableCmd; /*!< Enable write reg */
uint8_t wrEnableIndex; /*!< Write enable register index */
uint8_t qeIndex; /*!< Quad mode enable register index */
uint8_t busyIndex; /*!< Busy status register index */
uint8_t wrEnableBit; /*!< Write enable bit pos */
uint8_t qeBit; /*!< Quad enable bit pos */
uint8_t busyBit; /*!< Busy status bit pos */
uint8_t wrEnableWriteRegLen; /*!< Register length of write enable */
uint8_t wrEnableReadRegLen; /*!< Register length of write enable status */
uint8_t qeWriteRegLen; /*!< Register length of contain quad enable */
uint8_t qeReadRegLen; /*!< Register length of contain quad enable status */
uint8_t releasePowerDown; /*!< Release power down command */
uint8_t busyReadRegLen; /*!< Register length of contain busy status */
uint8_t readRegCmd[4]; /*!< Read register command buffer */
uint8_t writeRegCmd[4]; /*!< Write register command buffer */
uint8_t enterQpi; /*!< Enter qpi command */
uint8_t exitQpi; /*!< Exit qpi command */
uint8_t cReadMode; /*!< Config data for continuous read mode */
uint8_t cRExit; /*!< Config data for exit continuous read mode */
uint8_t burstWrapCmd; /*!< Enable burst wrap command */
uint8_t burstWrapCmdDmyClk; /*!< Enable burst wrap command dummy clock */
uint8_t burstWrapDataMode; /*!< Data and address mode for this command */
uint8_t burstWrapData; /*!< Data to enable burst wrap */
uint8_t deBurstWrapCmd; /*!< Disable burst wrap command */
uint8_t deBurstWrapCmdDmyClk; /*!< Disable burst wrap command dummy clock */
uint8_t deBurstWrapDataMode; /*!< Data and address mode for this command */
uint8_t deBurstWrapData; /*!< Data to disable burst wrap */
uint16_t timeEsector; /*!< 4K erase time */
uint16_t timeE32k; /*!< 32K erase time */
uint16_t timeE64k; /*!< 64K erase time */
uint16_t timePagePgm; /*!< Page program time */
uint16_t timeCe; /*!< Chip erase time in ms */
uint8_t pdDelay; /*!< Release power down command delay time for wake up */
uint8_t qeData; /*!< QE set data */
};
struct __attribute__((packed, aligned(4))) boot_flash_cfg_t {
uint32_t magiccode;
struct spi_flash_cfg_t cfg;
uint32_t crc32;
};
struct __attribute__((packed, aligned(4))) sys_clk_cfg_t {
uint8_t xtal_type;
uint8_t pll_clk;
uint8_t hclk_div;
uint8_t bclk_div;
uint8_t flash_clk_type;
uint8_t flash_clk_div;
uint8_t rsvd[2];
};
struct __attribute__((packed, aligned(4))) boot_clk_cfg_t {
uint32_t magiccode;
struct sys_clk_cfg_t cfg;
uint32_t crc32;
};
struct __attribute__((packed, aligned(4))) aesiv_cfg_t {
uint8_t aesiv[16];
uint32_t crc32;
};
struct __attribute__((packed, aligned(4))) pkey_cfg_t {
uint8_t eckeyx[32]; /* ec key in boot header */
uint8_t eckeyy[32]; /* ec key in boot header */
uint32_t crc32;
};
struct __attribute__((packed, aligned(4))) sign_cfg_t {
uint32_t sig_len;
uint8_t signature[32];
uint32_t crc32;
};
struct __attribute__((packed, aligned(4))) bootheader_t {
uint32_t magiccode; /*'BFXP'*/
uint32_t rivison;
struct boot_flash_cfg_t flash_cfg;
struct boot_clk_cfg_t clk_cfg;
union __attribute__((packed, aligned(1))) {
struct __attribute__((packed, aligned(1))) {
uint32_t sign : 2; /* [1: 0] for sign */
uint32_t encrypt_type : 2; /* [3: 2] for encrypt */
uint32_t key_sel : 2; /* [5: 4] for key sel in boot interface */
uint32_t rsvd_7_6 : 2; /* [7: 6] rsvd */
uint32_t no_segment : 1; /* [8] no segment info */
uint32_t cache_select : 1; /* [9] cache enable */
uint32_t notload_in_bootrom : 1; /* [10] not load this img in bootrom */
uint32_t aes_region_lock : 1; /* [11] aes region lock */
uint32_t cache_way_disable : 4; /* [15: 12] cache way disable info */
uint32_t crc_ignore : 1; /* [16] ignore crc */
uint32_t hash_ignore : 1; /* [17] ignore hash */
uint32_t halt_ap : 1; /* [18] halt ap */
uint32_t boot2_enable : 1; /* [19] boot2 enable */
uint32_t boot2_rollback : 1; /* [20] boot2 rollback */
uint32_t rsvd_31_21 : 11; /* [31: 21] rsvd */
} bval;
uint32_t wval;
} boot_cfg;
union __attribute__((packed, aligned(1))) {
uint32_t segment_cnt;
uint32_t img_len;
} img_segment_info;
uint32_t rsvd0; /* rsvd */
union __attribute__((packed, aligned(1))) {
uint32_t ramaddr;
uint32_t flashoffset;
} img_start;
uint32_t hash[32 / 4]; /*hash of the image*/
uint32_t boot2_pt_table_0; /* address of partition table 0 */
uint32_t boot2_pt_table_1; /* address of partition table 1 */
uint32_t crc32;
};
#endif

View file

@ -2,7 +2,16 @@ sdk_add_include_directories(.)
target_sources(app PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/board.c)
sdk_set_linker_script(bl808_flash_${CPU_ID}.ld)
if(CONFIG_IOT)
# target_sources(app PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/iot/fw_header.c)
sdk_set_linker_script(iot/bl808_flash_${CPU_ID}.ld)
# sdk_add_link_options(-ufw_header)
else()
# target_sources(app PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/mcu/fw_header.c)
sdk_set_linker_script(mcu/bl808_flash_${CPU_ID}.ld)
# sdk_add_link_options(-ufw_header0)
# sdk_add_link_options(-ufw_header1)
endif()
if(CONFIG_PSRAM)
sdk_add_compile_definitions(-DCONFIG_PSRAM)

View file

@ -3,35 +3,24 @@
#include "bflb_clock.h"
#include "bflb_rtc.h"
#include "bflb_flash.h"
#ifdef CONFIG_TLSF
#include "bflb_tlsf.h"
#else
#include "bflb_mmheap.h"
#endif
#include "bl808_glb.h"
#include "bl808_sflash.h"
#include "bl808_psram_uhs.h"
#include "bl808_tzc_sec.h"
#include "bl808_ef_cfg.h"
#include "bl808_uhs_phy.h"
#include "board.h"
#include "mem.h"
#ifdef CONFIG_BSP_SDH_SDCARD
#include "sdh_sdcard.h"
#endif
extern void log_start(void);
extern uint32_t __HeapBase;
extern uint32_t __HeapLimit;
#ifndef CONFIG_TLSF
struct heap_info mmheap_root;
static struct heap_region system_mmheap[] = {
{ NULL, 0 },
{ NULL, 0 }, /* Terminates the array. */
};
#endif
static struct bflb_device_s *uart0;
#if (defined(CONFIG_LUA) || defined(CONFIG_BFLOG) || defined(CONFIG_FATFS))
@ -94,13 +83,12 @@ static void peripheral_clock_init(void)
BL_WR_REG(PDS_BASE, PDS_CTL5, tmp_val);
GLB_AHB_MCU_Software_Reset(GLB_AHB_MCU_SW_SDH);
#endif
GLB_Set_USB_CLK_From_WIFIPLL(1);
#ifdef CONFIG_BSP_CSI
GLB_CSI_Config_MIPIPLL(2, 0x21000);
GLB_CSI_Power_Up_MIPIPLL();
GLB_Set_DSP_CLK(ENABLE, GLB_DSP_CLK_MUXPLL_160M, 1);
#endif
GLB_Set_USB_CLK_From_WIFIPLL(1);
}
#ifdef CONFIG_PSRAM
@ -175,7 +163,7 @@ void bl_show_log(void)
void bl_show_flashinfo(void)
{
SPI_Flash_Cfg_Type flashCfg;
spi_flash_cfg_type flashCfg;
uint8_t *pFlashCfg = NULL;
uint32_t flashCfgLen = 0;
uint32_t flashJedecId = 0;
@ -186,17 +174,17 @@ void bl_show_flashinfo(void)
printf("=========== flash cfg ==============\r\n");
printf("jedec id 0x%06X\r\n", flashJedecId);
printf("mid 0x%02X\r\n", flashCfg.mid);
printf("iomode 0x%02X\r\n", flashCfg.ioMode);
printf("clk delay 0x%02X\r\n", flashCfg.clkDelay);
printf("clk invert 0x%02X\r\n", flashCfg.clkInvert);
printf("read reg cmd0 0x%02X\r\n", flashCfg.readRegCmd[0]);
printf("read reg cmd1 0x%02X\r\n", flashCfg.readRegCmd[1]);
printf("write reg cmd0 0x%02X\r\n", flashCfg.writeRegCmd[0]);
printf("write reg cmd1 0x%02X\r\n", flashCfg.writeRegCmd[1]);
printf("qe write len 0x%02X\r\n", flashCfg.qeWriteRegLen);
printf("cread support 0x%02X\r\n", flashCfg.cReadSupport);
printf("cread code 0x%02X\r\n", flashCfg.cReadMode);
printf("burst wrap cmd 0x%02X\r\n", flashCfg.burstWrapCmd);
printf("iomode 0x%02X\r\n", flashCfg.io_mode);
printf("clk delay 0x%02X\r\n", flashCfg.clk_delay);
printf("clk invert 0x%02X\r\n", flashCfg.clk_invert);
printf("read reg cmd0 0x%02X\r\n", flashCfg.read_reg_cmd[0]);
printf("read reg cmd1 0x%02X\r\n", flashCfg.read_reg_cmd[1]);
printf("write reg cmd0 0x%02X\r\n", flashCfg.write_reg_cmd[0]);
printf("write reg cmd1 0x%02X\r\n", flashCfg.write_reg_cmd[1]);
printf("qe write len 0x%02X\r\n", flashCfg.qe_write_reg_len);
printf("cread support 0x%02X\r\n", flashCfg.c_read_support);
printf("cread code 0x%02X\r\n", flashCfg.c_read_mode);
printf("burst wrap cmd 0x%02X\r\n", flashCfg.burst_wrap_cmd);
printf("=====================================\r\n");
}
@ -211,8 +199,9 @@ static void console_init()
bflb_gpio_uart_init(gpio, GPIO_PIN_14, GPIO_UART_FUNC_UART0_TX);
bflb_gpio_uart_init(gpio, GPIO_PIN_15, GPIO_UART_FUNC_UART0_RX);
#elif defined(CPU_D0)
bflb_gpio_init(gpio, GPIO_PIN_8, 21 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
//bflb_gpio_init(gpio, GPIO_PIN_9, 21 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
/* sipeed m1s dock */
bflb_gpio_init(gpio, GPIO_PIN_16, 21 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
bflb_gpio_init(gpio, GPIO_PIN_17, 21 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
#endif
struct bflb_uart_config_s cfg;
cfg.baudrate = 2000000;
@ -234,50 +223,37 @@ static void console_init()
#if defined(CPU_M0)
void board_init(void)
{
int ret = -1;
uintptr_t flag;
flag = bflb_irq_save();
bflb_flash_init();
ret = bflb_flash_init();
GLB_Halt_CPU(GLB_CORE_ID_D0);
GLB_Halt_CPU(GLB_CORE_ID_LP);
system_clock_init();
peripheral_clock_init();
bflb_irq_initialize();
GLB_Release_CPU(GLB_CORE_ID_D0);
GLB_Release_CPU(GLB_CORE_ID_LP);
bflb_irq_restore(flag);
#ifdef CONFIG_TLSF
bflb_mmheap_init((void *)&__HeapBase, ((size_t)&__HeapLimit - (size_t)&__HeapBase));
#else
system_mmheap[0].addr = (uint8_t *)&__HeapBase;
system_mmheap[0].mem_size = ((size_t)&__HeapLimit - (size_t)&__HeapBase);
if (system_mmheap[0].mem_size > 0) {
bflb_mmheap_init(&mmheap_root, system_mmheap);
}
#endif
console_init();
size_t heap_len = ((size_t)&__HeapLimit - (size_t)&__HeapBase);
kmem_init((void *)&__HeapBase, heap_len);
bl_show_log();
if (ret != 0) {
printf("flash init fail!!!\r\n");
}
bl_show_flashinfo();
#ifdef CONFIG_TLSF
bflb_tlsf_size_container_t *tlsf_size = bflb_tlsf_stats();
printf("TLSF Dynamic Memory Init Success: Heap Size = %d Kbyte, Used Size = %d Kbyte, Free Size = %d Kbyte\r\n",
tlsf_size->free + tlsf_size->used / 1024, tlsf_size->used / 1024, tlsf_size->free / 1024);
#else
printf("dynamic memory init success,heap size = %d Kbyte \r\n", system_mmheap[0].mem_size / 1024);
#endif
printf("dynamic memory init success,heap size = %d Kbyte \r\n", ((size_t)&__HeapLimit - (size_t)&__HeapBase) / 1024);
printf("sig1:%08x\r\n", BL_RD_REG(GLB_BASE, GLB_UART_CFG1));
printf("sig2:%08x\r\n", BL_RD_REG(GLB_BASE, GLB_UART_CFG2));
log_start();
#if (defined(CONFIG_LUA) || defined(CONFIG_BFLOG) || defined(CONFIG_FATFS))
rtc = bflb_device_get_by_name("rtc");
#endif
@ -288,6 +264,18 @@ void board_init(void)
}
}
#endif
/* set CPU D0 boot XIP address and flash address */
// Tzc_Sec_Set_CPU_Group(GLB_CORE_ID_D0, 1);
// /* D0 boot from 0x58000000 */
// GLB_Set_CPU_Reset_Address(GLB_CORE_ID_D0, 0x58000000);
// /* D0 image offset on flash is 0x100000+0x1000(header) */
// bflb_sf_ctrl_set_flash_image_offset(0x101000, 1, SF_CTRL_FLASH_BANK0);
bflb_irq_restore(flag);
/* we do not check header at 0x10000, just boot */
GLB_Release_CPU(GLB_CORE_ID_D0);
/* release d0 and then do can run */
BL_WR_WORD(IPC_SYNC_ADDR1, IPC_SYNC_FLAG);
BL_WR_WORD(IPC_SYNC_ADDR2, IPC_SYNC_FLAG);
@ -300,16 +288,8 @@ void board_init(void)
bflb_irq_initialize();
#ifdef CONFIG_TLSF
bflb_mmheap_init((void *)&__HeapBase, ((size_t)&__HeapLimit - (size_t)&__HeapBase));
#else
system_mmheap[0].addr = (uint8_t *)&__HeapBase;
system_mmheap[0].mem_size = ((size_t)&__HeapLimit - (size_t)&__HeapBase);
if (system_mmheap[0].mem_size > 0) {
bflb_mmheap_init(&mmheap_root, system_mmheap);
}
#endif
size_t heap_len = ((size_t)&__HeapLimit - (size_t)&__HeapBase);
kmem_init((void *)&__HeapBase, heap_len);
console_init();
@ -320,6 +300,8 @@ void board_init(void)
printf("sig1:%08x\r\n", BL_RD_REG(GLB_BASE, GLB_UART_CFG1));
printf("sig2:%08x\r\n", BL_RD_REG(GLB_BASE, GLB_UART_CFG2));
printf("cgen1:%08x\r\n", getreg32(BFLB_GLB_CGEN1_BASE));
log_start();
}
#endif
@ -502,25 +484,43 @@ void board_csi_gpio_init(void)
gpio = bflb_device_get_by_name("gpio");
GLB_Set_Ldo15cis_Vout(GLB_LDO15CIS_LEVEL_1P20V);
#if 1 /* sipeed m1s dock */
/* I2C GPIO */
bflb_gpio_init(gpio, GPIO_PIN_19, GPIO_FUNC_I2C0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
bflb_gpio_init(gpio, GPIO_PIN_20, GPIO_FUNC_I2C0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
/* Power down GPIO */
bflb_gpio_init(gpio, GPIO_PIN_22, GPIO_OUTPUT | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
bflb_gpio_set(gpio, GPIO_PIN_22);
/* Reset GPIO */
bflb_gpio_init(gpio, GPIO_PIN_21, GPIO_OUTPUT | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
bflb_gpio_set(gpio, GPIO_PIN_21);
bflb_gpio_init(gpio, GPIO_PIN_6, GPIO_FUNC_I2C0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
bflb_gpio_init(gpio, GPIO_PIN_7, GPIO_FUNC_I2C0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
/* MCLK GPIO */
bflb_gpio_init(gpio, GPIO_PIN_23, GPIO_FUNC_CLKOUT | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
bflb_gpio_init(gpio, GPIO_PIN_33, GPIO_FUNC_CLKOUT | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
GLB_Set_Ldo15cis_Vout(GLB_LDO15CIS_LEVEL_1P20V);
/* Power down GPIO */
bflb_gpio_init(gpio, GPIO_PIN_40, GPIO_OUTPUT | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
bflb_gpio_reset(gpio, GPIO_PIN_40);
/* Reset GPIO */
bflb_gpio_init(gpio, GPIO_PIN_41, GPIO_OUTPUT | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
bflb_mtimer_delay_us(20);
bflb_gpio_set(gpio, GPIO_PIN_41);
#else
/* I2C GPIO */
bflb_gpio_init(gpio, GPIO_PIN_21, GPIO_FUNC_I2C0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
bflb_gpio_init(gpio, GPIO_PIN_22, GPIO_FUNC_I2C0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
/* MCLK GPIO */
bflb_gpio_init(gpio, GPIO_PIN_18, GPIO_FUNC_CLKOUT | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
/* Power down GPIO */
bflb_gpio_init(gpio, GPIO_PIN_6, GPIO_OUTPUT | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
bflb_gpio_reset(gpio, GPIO_PIN_6);
/* Reset GPIO */
bflb_gpio_init(gpio, GPIO_PIN_23, GPIO_OUTPUT | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
bflb_mtimer_delay_us(20);
bflb_gpio_set(gpio, GPIO_PIN_23);
#endif
}
void board_iso11898_gpio_init(void)
void board_iso11898_gpio_init()
{
// struct bflb_device_s *gpio;
@ -576,4 +576,4 @@ __attribute__((weak)) uint32_t get_fattime(void)
| ((uint32_t)tm.min << 5) /* Min 0 */
| ((uint32_t)tm.sec >> 1); /* Sec 0 */
}
#endif
#endif

View file

@ -0,0 +1,266 @@
/****************************************************************************************
* @file flash.ld
*
* @brief This file is the link script file (gnuarm or armgcc).
*
* Copyright (C) BouffaloLab 2021
*
****************************************************************************************
*/
/* configure the CPU type */
OUTPUT_ARCH( "riscv" )
/* link with the standard c library */
INPUT(-lc)
/* link with the standard GCC library */
INPUT(-lgcc)
/* configure the entry point */
ENTRY(__start)
StackSize = 0x0400; /* 1KB */
HeapMinSize = 0x1000; /* 4KB */
MEMORY
{
fw_header_memory (rx) : ORIGIN = 0x58000000 - 0x1000, LENGTH = 4K
xip_memory (rx) : ORIGIN = 0x58000000, LENGTH = 32M
itcm_memory (rx) : ORIGIN = 0x3eff0000, LENGTH = 28K
dtcm_memory (rx) : ORIGIN = 0x3eff7000, LENGTH = 4K
nocache_ram_memory (!rx) : ORIGIN = 0x3eff8000, LENGTH = 0K
ram_memory (!rx) : ORIGIN = 0x3eff8000, LENGTH = 32K + 32K
xram_memory (!rx) : ORIGIN = 0x40004000, LENGTH = 16K
}
SECTIONS
{
.fw_header :
{
KEEP(*(.fw_header))
} > fw_header_memory
.text :
{
. = ALIGN(4);
__text_code_start__ = .;
KEEP (*(SORT_NONE(.init)))
*(.text)
*(.text.*)
/* section information for shell */
. = ALIGN(8);
__fsymtab_start = .;
KEEP(*(FSymTab))
__fsymtab_end = .;
. = ALIGN(4);
__vsymtab_start = .;
KEEP(*(VSymTab))
__vsymtab_end = .;
/*put .rodata**/
*(EXCLUDE_FILE( *bl808_glb*.o* \
*bl808_glb_gpio*.o* \
*bl808_pds*.o* \
*bl808_aon*.o* \
*bl808_hbn*.o* \
*bl808_l1c*.o* \
*bl808_common*.o* \
*bl808_clock*.o* \
*bl808_ef_ctrl*.o* \
*bl808_sf_cfg*.o* \
*bl808_sf_ctrl*.o* \
*bl808_sflash*.o* \
*bl808_xip_sflash*.o* \
*bl808_romapi_patch*.o* ) .rodata*)
*(.srodata)
*(.srodata.*)
. = ALIGN(4);
__text_code_end__ = .;
} > xip_memory
. = ALIGN(4);
__itcm_load_addr = .;
.itcm_region : AT (__itcm_load_addr)
{
. = ALIGN(4);
__tcm_code_start__ = .;
*(.tcm_code.*)
*(.tcm_const.*)
*(.sclock_rlt_code.*)
*(.sclock_rlt_const.*)
*bl808_glb*.o*(.rodata*)
*bl808_glb_gpio*.o*(.rodata*)
*bl808_pds*.o*(.rodata*)
*bl808_aon*.o*(.rodata*)
*bl808_hbn*.o*(.rodata*)
*bl808_l1c*.o*(.rodata*)
*bl808_common*.o*(.rodata*)
*bl808_clock*.o*(.rodata*)
*bl808_ef_ctrl*.o*(.rodata*)
*bl808_sf_cfg*.o*(.rodata*)
*bl808_sf_ctrl*.o*(.rodata*)
*bl808_sflash*.o*(.rodata*)
*bl808_xip_sflash*.o*(.rodata*)
*bl808_romapi_patch*.o*(.rodata*)
. = ALIGN(4);
__tcm_code_end__ = .;
} > itcm_memory
__dtcm_load_addr = __itcm_load_addr + SIZEOF(.itcm_region);
.dtcm_region : AT (__dtcm_load_addr)
{
. = ALIGN(4);
__tcm_data_start__ = .;
*(.tcm_data)
/* *finger_print.o(.data*) */
. = ALIGN(4);
__tcm_data_end__ = .;
} > dtcm_memory
/*************************************************************************/
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy (NOLOAD):
{
. = ALIGN(0x4);
. = . + StackSize;
. = ALIGN(0x4);
} > dtcm_memory
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory);
PROVIDE( __freertos_irq_stack_top = __StackTop);
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __tcm_data_end__, "region RAM overflowed with stack")
/*************************************************************************/
__nocache_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region);
.nocache_ram_region (NOLOAD) : AT (__nocache_ram_load_addr)
{
. = ALIGN(4);
__nocache_ram_data_start__ = .;
*(.nocache_ram)
. = ALIGN(4);
__nocache_ram_data_end__ = .;
} > nocache_ram_memory
__system_ram_load_addr = __nocache_ram_load_addr + SIZEOF(.nocache_ram_region);
.system_ram_data_region : AT (__system_ram_load_addr)
{
. = ALIGN(4);
__system_ram_data_start__ = .;
*(.system_ram)
. = ALIGN(4);
__system_ram_data_end__ = .;
} > ram_memory
.system_ram_noinit_data_region (NOLOAD) :
{
. = ALIGN(4);
*(.system_ram_noinit)
. = ALIGN(4);
} > ram_memory
__ram_load_addr = __system_ram_load_addr + SIZEOF(.system_ram_data_region);
/* Data section */
RAM_DATA : AT (__ram_load_addr)
{
. = ALIGN(4);
__ram_data_start__ = .;
PROVIDE( __global_pointer$ = . + 0x800 );
*(.data)
*(.data.*)
*(.sdata)
*(.sdata.*)
*(.sdata2)
*(.sdata2.*)
. = ALIGN(4);
__bflog_tags_start__ = .;
*(.bflog_tags_array)
. = ALIGN(4);
__bflog_tags_end__ = .;
__ram_data_end__ = .;
} > ram_memory
__etext_final = (__ram_load_addr + SIZEOF (RAM_DATA));
ASSERT(__etext_final <= ORIGIN(xip_memory) + LENGTH(xip_memory), "code memory overflow")
.bss (NOLOAD) :
{
. = ALIGN(4);
__bss_start__ = .;
*(.bss*)
*(.sbss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
} > ram_memory
.noinit_data (NOLOAD) :
{
. = ALIGN(4);
__noinit_data_start__ = .;
*(.noinit_data*)
. = ALIGN(4);
__noinit_data_end__ = .;
} > ram_memory
.nocache_noinit_ram_region (NOLOAD) :
{
. = ALIGN(4);
__nocache_ram_data_start__ = .;
*(.nocache_noinit_ram)
. = ALIGN(4);
__nocache_ram_data_end__ = .;
} > nocache_ram_memory
.heap (NOLOAD):
{
. = ALIGN(4);
__HeapBase = .;
/*__end__ = .;*/
/*end = __end__;*/
KEEP(*(.heap*))
. = ALIGN(4);
__HeapLimit = .;
} > ram_memory
__HeapLimit = ORIGIN(ram_memory) + LENGTH(ram_memory);
ASSERT(__HeapLimit - __HeapBase >= HeapMinSize, "heap region overflow")
}

View file

@ -22,6 +22,7 @@ HeapMinSize = 0x1000; /* 4KB */
MEMORY
{
fw_header_memory (rx) : ORIGIN = 0x58000000 - 0x1000, LENGTH = 4K
xip_memory (rx) : ORIGIN = 0x58000000, LENGTH = 32M
itcm_memory (rx) : ORIGIN = 0x62020000, LENGTH = 20K
dtcm_memory (rx) : ORIGIN = 0x62025000, LENGTH = 4K
@ -32,6 +33,10 @@ MEMORY
SECTIONS
{
.fw_header :
{
KEEP(*(.fw_header))
} > fw_header_memory
.text :
{
@ -202,6 +207,10 @@ SECTIONS
*(.sdata2.*)
. = ALIGN(4);
__bflog_tags_start__ = .;
*(.bflog_tags_array)
. = ALIGN(4);
__bflog_tags_end__ = .;
__ram_data_end__ = .;
} > ram_memory

View file

@ -0,0 +1,199 @@
#include "fw_header.h"
__attribute__((section(".fw_header"))) struct bootheader_t fw_header = {
.magiccode = 0x504e4642,
.rivison = 0x00000001,
/*flash config */
.flash_cfg.magiccode = 0x47464346,
.flash_cfg.cfg.ioMode = 0x11, /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */
.flash_cfg.cfg.cReadSupport = 0x00, /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */
.flash_cfg.cfg.clkDelay = 0x01, /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */
.flash_cfg.cfg.clkInvert = 0x01, /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */
.flash_cfg.cfg.resetEnCmd = 0x66, /*!< Flash enable reset command */
.flash_cfg.cfg.resetCmd = 0x99, /*!< Flash reset command */
.flash_cfg.cfg.resetCreadCmd = 0xff, /*!< Flash reset continuous read command */
.flash_cfg.cfg.resetCreadCmdSize = 0x03, /*!< Flash reset continuous read command size */
.flash_cfg.cfg.jedecIdCmd = 0x9f, /*!< JEDEC ID command */
.flash_cfg.cfg.jedecIdCmdDmyClk = 0x00, /*!< JEDEC ID command dummy clock */
.flash_cfg.cfg.enter32BitsAddrCmd = 0xb7, /*!< Enter 32-bits addr command */
.flash_cfg.cfg.exit32BitsAddrCmd = 0xe9, /*!< Exit 32-bits addr command */
.flash_cfg.cfg.sectorSize = 0x04, /*!< *1024bytes */
.flash_cfg.cfg.mid = 0x00, /*!< Manufacturer ID */
.flash_cfg.cfg.pageSize = 0x100, /*!< Page size */
.flash_cfg.cfg.chipEraseCmd = 0xc7, /*!< Chip erase cmd */
.flash_cfg.cfg.sectorEraseCmd = 0x20, /*!< Sector erase command */
.flash_cfg.cfg.blk32EraseCmd = 0x52, /*!< Block 32K erase command,some Micron not support */
.flash_cfg.cfg.blk64EraseCmd = 0xd8, /*!< Block 64K erase command */
.flash_cfg.cfg.writeEnableCmd = 0x06, /*!< Need before every erase or program */
.flash_cfg.cfg.pageProgramCmd = 0x02, /*!< Page program cmd */
.flash_cfg.cfg.qpageProgramCmd = 0x32, /*!< QIO page program cmd */
.flash_cfg.cfg.qppAddrMode = 0x00, /*!< QIO page program address mode */
.flash_cfg.cfg.fastReadCmd = 0x0b, /*!< Fast read command */
.flash_cfg.cfg.frDmyClk = 0x01, /*!< Fast read command dummy clock */
.flash_cfg.cfg.qpiFastReadCmd = 0x0b, /*!< QPI fast read command */
.flash_cfg.cfg.qpiFrDmyClk = 0x01, /*!< QPI fast read command dummy clock */
.flash_cfg.cfg.fastReadDoCmd = 0x3b, /*!< Fast read dual output command */
.flash_cfg.cfg.frDoDmyClk = 0x01, /*!< Fast read dual output command dummy clock */
.flash_cfg.cfg.fastReadDioCmd = 0xbb, /*!< Fast read dual io comamnd */
.flash_cfg.cfg.frDioDmyClk = 0x00, /*!< Fast read dual io command dummy clock */
.flash_cfg.cfg.fastReadQoCmd = 0x6b, /*!< Fast read quad output comamnd */
.flash_cfg.cfg.frQoDmyClk = 0x01, /*!< Fast read quad output comamnd dummy clock */
.flash_cfg.cfg.fastReadQioCmd = 0xeb, /*!< Fast read quad io comamnd */
.flash_cfg.cfg.frQioDmyClk = 0x02, /*!< Fast read quad io comamnd dummy clock */
.flash_cfg.cfg.qpiFastReadQioCmd = 0xeb, /*!< QPI fast read quad io comamnd */
.flash_cfg.cfg.qpiFrQioDmyClk = 0x02, /*!< QPI fast read QIO dummy clock */
.flash_cfg.cfg.qpiPageProgramCmd = 0x02, /*!< QPI program command */
.flash_cfg.cfg.writeVregEnableCmd = 0x50, /*!< Enable write reg */
.flash_cfg.cfg.wrEnableIndex = 0x00, /*!< Write enable register index */
.flash_cfg.cfg.qeIndex = 0x01, /*!< Quad mode enable register index */
.flash_cfg.cfg.busyIndex = 0x00, /*!< Busy status register index */
.flash_cfg.cfg.wrEnableBit = 0x01, /*!< Write enable bit pos */
.flash_cfg.cfg.qeBit = 0x01, /*!< Quad enable bit pos */
.flash_cfg.cfg.busyBit = 0x00, /*!< Busy status bit pos */
.flash_cfg.cfg.wrEnableWriteRegLen = 0x02, /*!< Register length of write enable */
.flash_cfg.cfg.wrEnableReadRegLen = 0x01, /*!< Register length of write enable status */
.flash_cfg.cfg.qeWriteRegLen = 0x02, /*!< Register length of contain quad enable */
.flash_cfg.cfg.qeReadRegLen = 0x01, /*!< Register length of contain quad enable status */
.flash_cfg.cfg.releasePowerDown = 0xab, /*!< Release power down command */
.flash_cfg.cfg.busyReadRegLen = 0x01, /*!< Register length of contain busy status */
.flash_cfg.cfg.readRegCmd[0] = 0x05, /*!< Read register command buffer */
.flash_cfg.cfg.readRegCmd[1] = 0x35, /*!< Read register command buffer */
.flash_cfg.cfg.readRegCmd[2] = 0x00, /*!< Read register command buffer */
.flash_cfg.cfg.readRegCmd[3] = 0x00, /*!< Read register command buffer */
.flash_cfg.cfg.writeRegCmd[0] = 0x01, /*!< Write register command buffer */
.flash_cfg.cfg.writeRegCmd[1] = 0x01, /*!< Write register command buffer */
.flash_cfg.cfg.writeRegCmd[2] = 0x00, /*!< Write register command buffer */
.flash_cfg.cfg.writeRegCmd[3] = 0x00, /*!< Write register command buffer */
.flash_cfg.cfg.enterQpi = 0x38, /*!< Enter qpi command */
.flash_cfg.cfg.exitQpi = 0xff, /*!< Exit qpi command */
.flash_cfg.cfg.cReadMode = 0x20, /*!< Config data for continuous read mode */
.flash_cfg.cfg.cRExit = 0xf0, /*!< Config data for exit continuous read mode */
.flash_cfg.cfg.burstWrapCmd = 0x77, /*!< Enable burst wrap command */
.flash_cfg.cfg.burstWrapCmdDmyClk = 0x03, /*!< Enable burst wrap command dummy clock */
.flash_cfg.cfg.burstWrapDataMode = 0x02, /*!< Data and address mode for this command */
.flash_cfg.cfg.burstWrapData = 0x40, /*!< Data to enable burst wrap */
.flash_cfg.cfg.deBurstWrapCmd = 0x77, /*!< Disable burst wrap command */
.flash_cfg.cfg.deBurstWrapCmdDmyClk = 0x03, /*!< Disable burst wrap command dummy clock */
.flash_cfg.cfg.deBurstWrapDataMode = 0x02, /*!< Data and address mode for this command */
.flash_cfg.cfg.deBurstWrapData = 0xf0, /*!< Data to disable burst wrap */
.flash_cfg.cfg.timeEsector = 300, /*!< 4K erase time */
.flash_cfg.cfg.timeE32k = 1200, /*!< 32K erase time */
.flash_cfg.cfg.timeE64k = 1200, /*!< 64K erase time */
.flash_cfg.cfg.timePagePgm = 50, /*!< Page program time */
.flash_cfg.cfg.timeCe = 30000, /*!< Chip erase time in ms */
.flash_cfg.cfg.pdDelay = 20, /*!< Release power down command delay time for wake up */
.flash_cfg.cfg.qeData = 0, /*!< QE set data */
.flash_cfg.crc32 = 0xdeadbeef,
/* clock cfg */
.clk_cfg.magiccode = 0x47464350,
.clk_cfg.cfg.xtal_type = 0x07, /*!< 0:None,1:24M,2:32M,3:38.4M,4:40M,5:26M,6:RC32M */
.clk_cfg.cfg.mcu_clk = 0x04, /*!< mcu_clk 0:RC32M,1:Xtal,2:cpupll 400M,3:wifipll 192M,4:wifipll 320M */
.clk_cfg.cfg.mcu_clk_div = 0x00,
.clk_cfg.cfg.mcu_bclk_div = 0x00,
.clk_cfg.cfg.mcu_pbclk_div = 0x03,
.clk_cfg.cfg.lp_div = 0x01,
.clk_cfg.cfg.dsp_clk = 0x03, /* 0:RC32M,1:Xtal,2:wifipll 240M,3:wifipll 320M,4:cpupll 400M */
.clk_cfg.cfg.dsp_clk_div = 0x00,
.clk_cfg.cfg.dsp_bclk_div = 0x01,
.clk_cfg.cfg.dsp_pbclk = 0x02, /* 0:RC32M,1:Xtal,2:wifipll 160M,3:cpupll 160M,4:wifipll 240M */
.clk_cfg.cfg.dsp_pbclk_div = 0x00,
.clk_cfg.cfg.emi_clk = 0x02, /*!< 0:mcu pbclk,1:cpupll 200M,2:wifipll 320M,3:cpupll 400M */
.clk_cfg.cfg.emi_clk_div = 0x01,
.clk_cfg.cfg.flash_clk_type = 0x01, /*!< 0:wifipll 120M,1:xtal,2:cpupll 100M,3:wifipll 80M,4:bclk,5:wifipll 96M */
.clk_cfg.cfg.flash_clk_div = 0x00,
.clk_cfg.cfg.wifipll_pu = 0x01,
.clk_cfg.cfg.aupll_pu = 0x01,
.clk_cfg.cfg.cpupll_pu = 0x01,
.clk_cfg.cfg.mipipll_pu = 0x01,
.clk_cfg.cfg.uhspll_pu = 0x01,
.clk_cfg.crc32 = 0xdeadbeef,
/* basic cfg */
.basic_cfg.sign_type = 0x0, /* [1: 0] for sign */
.basic_cfg.encrypt_type = 0x0, /* [3: 2] for encrypt */
.basic_cfg.key_sel = 0x0, /* [5: 4] key slot */
.basic_cfg.xts_mode = 0x0, /* [6] for xts mode */
.basic_cfg.aes_region_lock = 0x0, /* [7] rsvd */
.basic_cfg.no_segment = 0x1, /* [8] no segment info */
.basic_cfg.rsvd_0 = 0x0, /* [9] boot2 enable(rsvd_0) */
.basic_cfg.rsvd_1 = 0x0, /* [10] boot2 rollback(rsvd_1) */
.basic_cfg.cpu_master_id = 0x0, /* [14: 11] master id */
.basic_cfg.notload_in_bootrom = 0x0, /* [15] notload in bootrom */
.basic_cfg.crc_ignore = 0x1, /* [16] ignore crc */
.basic_cfg.hash_ignore = 0x1, /* [17] hash ignore */
.basic_cfg.power_on_mm = 0x1, /* [18] power on mm */
.basic_cfg.em_sel = 0x1, /* [21: 19] em_sel */
.basic_cfg.cmds_en = 0x1, /* [22] command spliter enable */
#if 0
# 0 : cmds bypass wrap commands to macro, original mode;
# 1 : cmds handle wrap commands, original mode;
# 2 : cmds bypass wrap commands to macro, cmds force wrap16 * 4 splitted into two wrap8 * 4;
# 3 : cmds handle wrap commands, cmds force wrap16 * 4 splitted into two wrap8 * 4
#endif
.basic_cfg.cmds_wrap_mode = 0x1, /* [24: 23] cmds wrap mode */
#if 0
# 0 : SF_CTRL_WRAP_LEN_8, 1 : SF_CTRL_WRAP_LEN_16, 2 : SF_CTRL_WRAP_LEN_32,
# 3 : SF_CTRL_WRAP_LEN_64, 9 : SF_CTRL_WRAP_LEN_4096
#endif
.basic_cfg.cmds_wrap_len = 0x9, /* [28: 25] cmds wrap len */
.basic_cfg.icache_invalid = 0x1, /* [29] icache invalid */
.basic_cfg.dcache_invalid = 0x1, /* [30] dcache invalid */
.basic_cfg.rsvd_3 = 0x0, /* [31] rsvd_3 */
.basic_cfg.group_image_offset = 0x00001000, /* flash controller offset */
.basic_cfg.aes_region_len = 0x00000000, /* aes region length */
.basic_cfg.img_len_cnt = 0x00010000, /* image length or segment count */
.basic_cfg.hash = { 0xdeadbeef }, /* hash of the image */
/* cpu cfg */
.cpu_cfg[0].config_enable = 0x01, /* coinfig this cpu */
.cpu_cfg[0].halt_cpu = 0x0, /* halt this cpu */
.cpu_cfg[0].cache_enable = 0x0, /* cache setting :only for BL Cache */
.cpu_cfg[0].cache_wa = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg[0].cache_wb = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg[0].cache_wt = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg[0].cache_way_dis = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg[0].rsvd = 0x0,
.cpu_cfg[0].cache_range_h = 0x00000000,
.cpu_cfg[0].cache_range_l = 0x00000000,
/* image_address_offset */
.cpu_cfg[0].image_address_offset = 0x0,
.cpu_cfg[0].rsvd0 = 0x58000000, /* rsvd0 */
.cpu_cfg[0].msp_val = 0x00000000, /* msp value */
/* cpu cfg */
.cpu_cfg[1].config_enable = 0x01, /* coinfig this cpu */
.cpu_cfg[1].halt_cpu = 0x0, /* halt this cpu */
.cpu_cfg[1].cache_enable = 0x0, /* cache setting :only for BL Cache */
.cpu_cfg[1].cache_wa = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg[1].cache_wb = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg[1].cache_wt = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg[1].cache_way_dis = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg[1].rsvd = 0x0,
.cpu_cfg[1].cache_range_h = 0x00000000,
.cpu_cfg[1].cache_range_l = 0x00000000,
/* image_address_offset */
.cpu_cfg[1].image_address_offset = 0x0,
.cpu_cfg[1].rsvd0 = 0x58000000, /* rsvd0 */
.cpu_cfg[1].msp_val = 0x00000000, /* msp value */
/* address of partition table 0 */ /* 4 */
.boot2_pt_table_0_rsvd = 0x00000000,
/* address of partition table 1 */ /* 4 */
.boot2_pt_table_1_rsvd = 0x00000000,
/* address of flashcfg table list */ /* 4 */
.flash_cfg_table_addr = 0x00000000,
/* flashcfg table list len */ /* 4 */
.flash_cfg_table_len = 0x00000000,
.crc32 = 0xdeadbeef /* 4 */
};

View file

@ -0,0 +1,210 @@
#ifndef __FW_HEADER_H__
#define __FW_HEADER_H__
#include "stdint.h"
#include "stdio.h"
struct __attribute__((packed, aligned(4))) spi_flash_cfg_t {
uint8_t ioMode; /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */
uint8_t cReadSupport; /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */
uint8_t clkDelay; /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */
uint8_t clkInvert; /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */
uint8_t resetEnCmd; /*!< Flash enable reset command */
uint8_t resetCmd; /*!< Flash reset command */
uint8_t resetCreadCmd; /*!< Flash reset continuous read command */
uint8_t resetCreadCmdSize; /*!< Flash reset continuous read command size */
uint8_t jedecIdCmd; /*!< JEDEC ID command */
uint8_t jedecIdCmdDmyClk; /*!< JEDEC ID command dummy clock */
uint8_t enter32BitsAddrCmd; /*!< Enter 32-bits addr command */
uint8_t exit32BitsAddrCmd; /*!< Exit 32-bits addr command */
uint8_t sectorSize; /*!< *1024bytes */
uint8_t mid; /*!< Manufacturer ID */
uint16_t pageSize; /*!< Page size */
uint8_t chipEraseCmd; /*!< Chip erase cmd */
uint8_t sectorEraseCmd; /*!< Sector erase command */
uint8_t blk32EraseCmd; /*!< Block 32K erase command,some Micron not support */
uint8_t blk64EraseCmd; /*!< Block 64K erase command */
uint8_t writeEnableCmd; /*!< Need before every erase or program */
uint8_t pageProgramCmd; /*!< Page program cmd */
uint8_t qpageProgramCmd; /*!< QIO page program cmd */
uint8_t qppAddrMode; /*!< QIO page program address mode */
uint8_t fastReadCmd; /*!< Fast read command */
uint8_t frDmyClk; /*!< Fast read command dummy clock */
uint8_t qpiFastReadCmd; /*!< QPI fast read command */
uint8_t qpiFrDmyClk; /*!< QPI fast read command dummy clock */
uint8_t fastReadDoCmd; /*!< Fast read dual output command */
uint8_t frDoDmyClk; /*!< Fast read dual output command dummy clock */
uint8_t fastReadDioCmd; /*!< Fast read dual io comamnd */
uint8_t frDioDmyClk; /*!< Fast read dual io command dummy clock */
uint8_t fastReadQoCmd; /*!< Fast read quad output comamnd */
uint8_t frQoDmyClk; /*!< Fast read quad output comamnd dummy clock */
uint8_t fastReadQioCmd; /*!< Fast read quad io comamnd */
uint8_t frQioDmyClk; /*!< Fast read quad io comamnd dummy clock */
uint8_t qpiFastReadQioCmd; /*!< QPI fast read quad io comamnd */
uint8_t qpiFrQioDmyClk; /*!< QPI fast read QIO dummy clock */
uint8_t qpiPageProgramCmd; /*!< QPI program command */
uint8_t writeVregEnableCmd; /*!< Enable write reg */
uint8_t wrEnableIndex; /*!< Write enable register index */
uint8_t qeIndex; /*!< Quad mode enable register index */
uint8_t busyIndex; /*!< Busy status register index */
uint8_t wrEnableBit; /*!< Write enable bit pos */
uint8_t qeBit; /*!< Quad enable bit pos */
uint8_t busyBit; /*!< Busy status bit pos */
uint8_t wrEnableWriteRegLen; /*!< Register length of write enable */
uint8_t wrEnableReadRegLen; /*!< Register length of write enable status */
uint8_t qeWriteRegLen; /*!< Register length of contain quad enable */
uint8_t qeReadRegLen; /*!< Register length of contain quad enable status */
uint8_t releasePowerDown; /*!< Release power down command */
uint8_t busyReadRegLen; /*!< Register length of contain busy status */
uint8_t readRegCmd[4]; /*!< Read register command buffer */
uint8_t writeRegCmd[4]; /*!< Write register command buffer */
uint8_t enterQpi; /*!< Enter qpi command */
uint8_t exitQpi; /*!< Exit qpi command */
uint8_t cReadMode; /*!< Config data for continuous read mode */
uint8_t cRExit; /*!< Config data for exit continuous read mode */
uint8_t burstWrapCmd; /*!< Enable burst wrap command */
uint8_t burstWrapCmdDmyClk; /*!< Enable burst wrap command dummy clock */
uint8_t burstWrapDataMode; /*!< Data and address mode for this command */
uint8_t burstWrapData; /*!< Data to enable burst wrap */
uint8_t deBurstWrapCmd; /*!< Disable burst wrap command */
uint8_t deBurstWrapCmdDmyClk; /*!< Disable burst wrap command dummy clock */
uint8_t deBurstWrapDataMode; /*!< Data and address mode for this command */
uint8_t deBurstWrapData; /*!< Data to disable burst wrap */
uint16_t timeEsector; /*!< 4K erase time */
uint16_t timeE32k; /*!< 32K erase time */
uint16_t timeE64k; /*!< 64K erase time */
uint16_t timePagePgm; /*!< Page program time */
uint16_t timeCe; /*!< Chip erase time in ms */
uint8_t pdDelay; /*!< Release power down command delay time for wake up */
uint8_t qeData; /*!< QE set data */
};
struct __attribute__((packed, aligned(4))) boot_flash_cfg_t {
uint32_t magiccode;
struct spi_flash_cfg_t cfg;
uint32_t crc32;
};
struct __attribute__((packed, aligned(4))) sys_clk_cfg_t {
uint8_t xtal_type;
uint8_t mcu_clk;
uint8_t mcu_clk_div;
uint8_t mcu_bclk_div;
uint8_t mcu_pbclk_div;
uint8_t lp_div;
uint8_t dsp_clk;
uint8_t dsp_clk_div;
uint8_t dsp_bclk_div;
uint8_t dsp_pbclk;
uint8_t dsp_pbclk_div;
uint8_t emi_clk;
uint8_t emi_clk_div;
uint8_t flash_clk_type;
uint8_t flash_clk_div;
uint8_t wifipll_pu;
uint8_t aupll_pu;
uint8_t cpupll_pu;
uint8_t mipipll_pu;
uint8_t uhspll_pu;
};
struct __attribute__((packed, aligned(4))) boot_clk_cfg_t {
uint32_t magiccode;
struct sys_clk_cfg_t cfg;
uint32_t crc32;
};
struct __attribute__((packed, aligned(4))) boot_basic_cfg_t {
uint32_t sign_type : 2; /* [1: 0] for sign */
uint32_t encrypt_type : 2; /* [3: 2] for encrypt */
uint32_t key_sel : 2; /* [5: 4] key slot */
uint32_t xts_mode : 1; /* [6] for xts mode */
uint32_t aes_region_lock : 1; /* [7] rsvd */
uint32_t no_segment : 1; /* [8] no segment info */
uint32_t rsvd_0 : 1; /* [9] boot2 enable(rsvd_0) */
uint32_t rsvd_1 : 1; /* [10] boot2 rollback(rsvd_1) */
uint32_t cpu_master_id : 4; /* [14: 11] master id */
uint32_t notload_in_bootrom : 1; /* [15] notload in bootrom */
uint32_t crc_ignore : 1; /* [16] ignore crc */
uint32_t hash_ignore : 1; /* [17] hash ignore */
uint32_t power_on_mm : 1; /* [18] power on mm */
uint32_t em_sel : 3; /* [21: 19] em_sel */
uint32_t cmds_en : 1; /* [22] command spliter enable */
uint32_t cmds_wrap_mode : 2; /* [24: 23] cmds wrap mode */
uint32_t cmds_wrap_len : 4; /* [28: 25] cmds wrap len */
uint32_t icache_invalid : 1; /* [29] icache invalid */
uint32_t dcache_invalid : 1; /* [30] dcache invalid */
uint32_t rsvd_3 : 1; /* [31] rsvd_3 */
uint32_t group_image_offset; /* flash controller offset */
uint32_t aes_region_len; /* aes region length */
uint32_t img_len_cnt; /* image length or segment count */
uint32_t hash[32 / 4]; /* hash of the image */
};
struct __attribute__((packed, aligned(4))) boot_cpu_cfg_t {
uint8_t config_enable; /* coinfig this cpu */
uint8_t halt_cpu; /* halt this cpu */
uint8_t cache_enable : 1; /* cache setting */
uint8_t cache_wa : 1; /* cache setting */
uint8_t cache_wb : 1; /* cache setting */
uint8_t cache_wt : 1; /* cache setting */
uint8_t cache_way_dis : 4; /* cache setting */
uint8_t rsvd;
uint32_t cache_range_h; /* cache range high */
uint32_t cache_range_l; /* cache range low */
uint32_t image_address_offset; /* image_address_offset */
uint32_t rsvd0; /* rsvd0 */
uint32_t msp_val; /* msp value */
};
struct __attribute__((packed, aligned(4))) aesiv_cfg_t {
uint8_t aesiv[16];
uint32_t crc32;
};
struct __attribute__((packed, aligned(4))) pkey_cfg_t {
uint8_t eckeyx[32]; /* ec key in boot header */
uint8_t eckeyy[32]; /* ec key in boot header */
uint32_t crc32;
};
struct __attribute__((packed, aligned(4))) sign_cfg_t {
uint32_t sig_len;
uint8_t signature[32];
uint32_t crc32;
};
struct __attribute__((packed, aligned(4))) bootheader_t {
uint32_t magiccode; /* 4 */
uint32_t rivison; /* 4 */
struct boot_flash_cfg_t flash_cfg; /* 4 + 84 + 4 */
struct boot_clk_cfg_t clk_cfg; /* 4 + 20 + 4 */
struct boot_basic_cfg_t basic_cfg; /* 4 + 4 + 4 + 4 + 4*8 */
struct boot_cpu_cfg_t cpu_cfg[3]; /*24*3 */
uint32_t boot2_pt_table_0_rsvd; /* address of partition table 0 */ /* 4 */
uint32_t boot2_pt_table_1_rsvd; /* address of partition table 1 */ /* 4 */
uint32_t flash_cfg_table_addr; /* address of flashcfg table list */ /* 4 */
uint32_t flash_cfg_table_len; /* flashcfg table list len */ /* 4 */
uint32_t rsvd0[6]; /* rsvd */
uint32_t rsvd1[6]; /* rsvd */
uint32_t rsvd3[5]; /* 4 */
uint32_t crc32; /* 4 */
};
#endif

View file

@ -22,6 +22,7 @@ HeapMinSize = 0x1000; /* 4KB */
MEMORY
{
fw_header_memory (rx) : ORIGIN = 0x58000000 - 0x1000, LENGTH = 4K
xip_memory (rx) : ORIGIN = 0x58000000, LENGTH = 32M
itcm_memory (rx) : ORIGIN = 0x3eff0000, LENGTH = 28K
dtcm_memory (rx) : ORIGIN = 0x3eff7000, LENGTH = 4K
@ -32,6 +33,10 @@ MEMORY
SECTIONS
{
.fw_header :
{
KEEP(*(.fw_header0))
} > fw_header_memory
.text :
{

View file

@ -0,0 +1,314 @@
/****************************************************************************************
* @file flash.ld
*
* @brief This file is the link script file (gnuarm or armgcc).
*
* Copyright (C) BouffaloLab 2021
*
****************************************************************************************
*/
/* configure the CPU type */
OUTPUT_ARCH( "riscv" )
/* link with the standard c library */
INPUT(-lc)
/* link with the standard GCC library */
INPUT(-lgcc)
/* configure the entry point */
ENTRY(__start)
StackSize = 0x0400; /* 1KB */
HeapMinSize = 0x1000; /* 4KB */
MEMORY
{
fw_header_memory0 (rx) : ORIGIN = 0x58000000 - 0x2000, LENGTH = 4K
fw_header_memory1 (rx) : ORIGIN = 0x58000000 - 0x1000, LENGTH = 4K
xip_memory (rx) : ORIGIN = 0x58000000, LENGTH = 32M
itcm_memory (rx) : ORIGIN = 0x62020000, LENGTH = 20K
dtcm_memory (rx) : ORIGIN = 0x62025000, LENGTH = 4K
nocache_ram_memory (!rx) : ORIGIN = 0x22026000, LENGTH = 40K
ram_memory (!rx) : ORIGIN = 0x62030000, LENGTH = 160K + 64K - 20K - 4K - 40K
xram_memory (!rx) : ORIGIN = 0x40000000, LENGTH = 16K
}
SECTIONS
{
.fw_header0 :
{
KEEP(*(.fw_header0))
} > fw_header_memory0
.fw_header1 :
{
KEEP(*(.fw_header1))
} > fw_header_memory1
.text :
{
. = ALIGN(4);
__text_code_start__ = .;
KEEP (*(SORT_NONE(.init)))
KEEP (*(SORT_NONE(.vector)))
*(.text)
*(.text.*)
/* section information for shell */
. = ALIGN(4);
__fsymtab_start = .;
KEEP(*(FSymTab))
__fsymtab_end = .;
. = ALIGN(4);
__vsymtab_start = .;
KEEP(*(VSymTab))
__vsymtab_end = .;
/* section information for usb usbh_class_info */
. = ALIGN(4);
__usbh_class_info_start__ = .;
KEEP(*(.usbh_class_info))
. = ALIGN(4);
__usbh_class_info_end__ = .;
/*put .rodata**/
*(EXCLUDE_FILE( *bl808_glb*.o* \
*bl808_glb_gpio*.o* \
*bl808_pds*.o* \
*bl808_aon*.o* \
*bl808_hbn*.o* \
*bl808_l1c*.o* \
*bl808_common*.o* \
*bl808_clock*.o* \
*bl808_ef_ctrl*.o* \
*bl808_sf_cfg*.o* \
*bl808_sf_ctrl*.o* \
*bl808_sflash*.o* \
*bl808_xip_sflash*.o* \
*bl808_romapi_patch*.o* ) .rodata*)
*(.srodata)
*(.srodata.*)
. = ALIGN(4);
__text_code_end__ = .;
} > xip_memory
. = ALIGN(4);
__itcm_load_addr = .;
.itcm_region : AT (__itcm_load_addr)
{
. = ALIGN(4);
__tcm_code_start__ = .;
*(.tcm_code.*)
*(.tcm_const.*)
*(.sclock_rlt_code.*)
*(.sclock_rlt_const.*)
*bl808_glb*.o*(.rodata*)
*bl808_glb_gpio*.o*(.rodata*)
*bl808_pds*.o*(.rodata*)
*bl808_aon*.o*(.rodata*)
*bl808_hbn*.o*(.rodata*)
*bl808_l1c*.o*(.rodata*)
*bl808_common*.o*(.rodata*)
*bl808_clock*.o*(.rodata*)
*bl808_ef_ctrl*.o*(.rodata*)
*bl808_sf_cfg*.o*(.rodata*)
*bl808_sf_ctrl*.o*(.rodata*)
*bl808_sflash*.o*(.rodata*)
*bl808_xip_sflash*.o*(.rodata*)
*bl808_romapi_patch*.o*(.rodata*)
. = ALIGN(4);
__tcm_code_end__ = .;
} > itcm_memory
__dtcm_load_addr = __itcm_load_addr + SIZEOF(.itcm_region);
.dtcm_region : AT (__dtcm_load_addr)
{
. = ALIGN(4);
__tcm_data_start__ = .;
*(.tcm_data)
/* *finger_print.o(.data*) */
. = ALIGN(4);
__tcm_data_end__ = .;
} > dtcm_memory
/*************************************************************************/
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy (NOLOAD):
{
. = ALIGN(0x4);
. = . + StackSize;
. = ALIGN(0x4);
} > dtcm_memory
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory);
PROVIDE( __freertos_irq_stack_top = __StackTop);
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __tcm_data_end__, "region RAM overflowed with stack")
/*************************************************************************/
__nocache_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region);
.nocache_ram_region : AT (__nocache_ram_load_addr)
{
. = ALIGN(4);
__nocache_ram_data_start__ = .;
*(.nocache_ram)
. = ALIGN(4);
__nocache_ram_data_end__ = .;
} > nocache_ram_memory
__system_ram_load_addr = __nocache_ram_load_addr + SIZEOF(.nocache_ram_region);
.system_ram_data_region : AT (__system_ram_load_addr)
{
. = ALIGN(4);
__system_ram_data_start__ = .;
*(.system_ram)
. = ALIGN(4);
__system_ram_data_end__ = .;
} > ram_memory
.system_ram_noinit_data_region (NOLOAD) :
{
. = ALIGN(4);
*(.system_ram_noinit)
. = ALIGN(4);
} > ram_memory
__ram_load_addr = __system_ram_load_addr + SIZEOF(.system_ram_data_region);
/* Data section */
RAM_DATA : AT (__ram_load_addr)
{
. = ALIGN(4);
__ram_data_start__ = .;
PROVIDE( __global_pointer$ = . + 0x800 );
*(.data)
*(.data.*)
*(.sdata)
*(.sdata.*)
*(.sdata2)
*(.sdata2.*)
. = ALIGN(4);
__ram_data_end__ = .;
} > ram_memory
__etext_final = (__ram_load_addr + SIZEOF (RAM_DATA));
ASSERT(__etext_final <= ORIGIN(xip_memory) + LENGTH(xip_memory), "code memory overflow")
.bss (NOLOAD) :
{
. = ALIGN(4);
__bss_start__ = .;
*(.bss*)
*(.sbss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
} > ram_memory
.noinit_data (NOLOAD) :
{
. = ALIGN(4);
__noinit_data_start__ = .;
*(.noinit_data*)
. = ALIGN(4);
__noinit_data_end__ = .;
} > ram_memory
.nocache_noinit_ram_region (NOLOAD) :
{
. = ALIGN(4);
__nocache_noinit_ram_data_start__ = .;
*(.nocache_noinit_ram)
*(.noncacheable)
. = ALIGN(4);
__nocache_noinit_ram_data_end__ = .;
} > nocache_ram_memory
.heap (NOLOAD):
{
. = ALIGN(4);
__HeapBase = .;
/*__end__ = .;*/
/*end = __end__;*/
KEEP(*(.heap*))
. = ALIGN(4);
__HeapLimit = .;
} > ram_memory
__HeapLimit = ORIGIN(ram_memory) + LENGTH(ram_memory);
ASSERT(__HeapLimit - __HeapBase >= HeapMinSize, "heap region overflow")
.psmram_data (NOLOAD):
{
. = ALIGN(4);
__psram_data_start__ = .;
/*__end__ = .;*/
/*end = __end__;*/
KEEP(*(.psram_data*))
. = ALIGN(4);
__psram_data_end__ = .;
} > ram_code
.wifibss (NOLOAD) :
{
PROVIDE( __wifi_bss_start = ADDR(.wifibss) );
PROVIDE( __wifi_bss_end = ADDR(.wifibss) + SIZEOF(.wifibss) );
_sshram = . ;
*(SHAREDRAMIPC)
*(SHAREDRAM)
_eshram = . ;
*ipc_shared.o(COMMON)
*sdu_shared.o(COMMON)
*hal_desc.o(COMMON)
*txl_buffer_shared.o(COMMON)
*txl_frame_shared.o(COMMON)
*scan_shared.o(COMMON)
*scanu_shared.o(COMMON)
*mfp_bip.o(COMMON)
*me_mic.o(COMMON)
*(.wifi_ram*)
. = ALIGN(16);
} > ram_wifi
PROVIDE( _heap_wifi_start = . );
PROVIDE( _heap_wifi_size = ORIGIN(ram_wifi) + LENGTH(ram_wifi) - _heap_wifi_start );
}

View file

@ -0,0 +1,403 @@
#include "fw_header.h"
__attribute__((section(".fw_header0"))) struct bootheader_t fw_header0 = {
.magiccode = 0x504e4642,
.rivison = 0x00000001,
/*flash config */
.flash_cfg.magiccode = 0x47464346,
.flash_cfg.cfg.ioMode = 0x11, /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */
.flash_cfg.cfg.cReadSupport = 0x00, /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */
.flash_cfg.cfg.clkDelay = 0x01, /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */
.flash_cfg.cfg.clkInvert = 0x01, /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */
.flash_cfg.cfg.resetEnCmd = 0x66, /*!< Flash enable reset command */
.flash_cfg.cfg.resetCmd = 0x99, /*!< Flash reset command */
.flash_cfg.cfg.resetCreadCmd = 0xff, /*!< Flash reset continuous read command */
.flash_cfg.cfg.resetCreadCmdSize = 0x03, /*!< Flash reset continuous read command size */
.flash_cfg.cfg.jedecIdCmd = 0x9f, /*!< JEDEC ID command */
.flash_cfg.cfg.jedecIdCmdDmyClk = 0x00, /*!< JEDEC ID command dummy clock */
.flash_cfg.cfg.enter32BitsAddrCmd = 0xb7, /*!< Enter 32-bits addr command */
.flash_cfg.cfg.exit32BitsAddrCmd = 0xe9, /*!< Exit 32-bits addr command */
.flash_cfg.cfg.sectorSize = 0x04, /*!< *1024bytes */
.flash_cfg.cfg.mid = 0x00, /*!< Manufacturer ID */
.flash_cfg.cfg.pageSize = 0x100, /*!< Page size */
.flash_cfg.cfg.chipEraseCmd = 0xc7, /*!< Chip erase cmd */
.flash_cfg.cfg.sectorEraseCmd = 0x20, /*!< Sector erase command */
.flash_cfg.cfg.blk32EraseCmd = 0x52, /*!< Block 32K erase command,some Micron not support */
.flash_cfg.cfg.blk64EraseCmd = 0xd8, /*!< Block 64K erase command */
.flash_cfg.cfg.writeEnableCmd = 0x06, /*!< Need before every erase or program */
.flash_cfg.cfg.pageProgramCmd = 0x02, /*!< Page program cmd */
.flash_cfg.cfg.qpageProgramCmd = 0x32, /*!< QIO page program cmd */
.flash_cfg.cfg.qppAddrMode = 0x00, /*!< QIO page program address mode */
.flash_cfg.cfg.fastReadCmd = 0x0b, /*!< Fast read command */
.flash_cfg.cfg.frDmyClk = 0x01, /*!< Fast read command dummy clock */
.flash_cfg.cfg.qpiFastReadCmd = 0x0b, /*!< QPI fast read command */
.flash_cfg.cfg.qpiFrDmyClk = 0x01, /*!< QPI fast read command dummy clock */
.flash_cfg.cfg.fastReadDoCmd = 0x3b, /*!< Fast read dual output command */
.flash_cfg.cfg.frDoDmyClk = 0x01, /*!< Fast read dual output command dummy clock */
.flash_cfg.cfg.fastReadDioCmd = 0xbb, /*!< Fast read dual io comamnd */
.flash_cfg.cfg.frDioDmyClk = 0x00, /*!< Fast read dual io command dummy clock */
.flash_cfg.cfg.fastReadQoCmd = 0x6b, /*!< Fast read quad output comamnd */
.flash_cfg.cfg.frQoDmyClk = 0x01, /*!< Fast read quad output comamnd dummy clock */
.flash_cfg.cfg.fastReadQioCmd = 0xeb, /*!< Fast read quad io comamnd */
.flash_cfg.cfg.frQioDmyClk = 0x02, /*!< Fast read quad io comamnd dummy clock */
.flash_cfg.cfg.qpiFastReadQioCmd = 0xeb, /*!< QPI fast read quad io comamnd */
.flash_cfg.cfg.qpiFrQioDmyClk = 0x02, /*!< QPI fast read QIO dummy clock */
.flash_cfg.cfg.qpiPageProgramCmd = 0x02, /*!< QPI program command */
.flash_cfg.cfg.writeVregEnableCmd = 0x50, /*!< Enable write reg */
.flash_cfg.cfg.wrEnableIndex = 0x00, /*!< Write enable register index */
.flash_cfg.cfg.qeIndex = 0x01, /*!< Quad mode enable register index */
.flash_cfg.cfg.busyIndex = 0x00, /*!< Busy status register index */
.flash_cfg.cfg.wrEnableBit = 0x01, /*!< Write enable bit pos */
.flash_cfg.cfg.qeBit = 0x01, /*!< Quad enable bit pos */
.flash_cfg.cfg.busyBit = 0x00, /*!< Busy status bit pos */
.flash_cfg.cfg.wrEnableWriteRegLen = 0x02, /*!< Register length of write enable */
.flash_cfg.cfg.wrEnableReadRegLen = 0x01, /*!< Register length of write enable status */
.flash_cfg.cfg.qeWriteRegLen = 0x02, /*!< Register length of contain quad enable */
.flash_cfg.cfg.qeReadRegLen = 0x01, /*!< Register length of contain quad enable status */
.flash_cfg.cfg.releasePowerDown = 0xab, /*!< Release power down command */
.flash_cfg.cfg.busyReadRegLen = 0x01, /*!< Register length of contain busy status */
.flash_cfg.cfg.readRegCmd[0] = 0x05, /*!< Read register command buffer */
.flash_cfg.cfg.readRegCmd[1] = 0x35, /*!< Read register command buffer */
.flash_cfg.cfg.readRegCmd[2] = 0x00, /*!< Read register command buffer */
.flash_cfg.cfg.readRegCmd[3] = 0x00, /*!< Read register command buffer */
.flash_cfg.cfg.writeRegCmd[0] = 0x01, /*!< Write register command buffer */
.flash_cfg.cfg.writeRegCmd[1] = 0x01, /*!< Write register command buffer */
.flash_cfg.cfg.writeRegCmd[2] = 0x00, /*!< Write register command buffer */
.flash_cfg.cfg.writeRegCmd[3] = 0x00, /*!< Write register command buffer */
.flash_cfg.cfg.enterQpi = 0x38, /*!< Enter qpi command */
.flash_cfg.cfg.exitQpi = 0xff, /*!< Exit qpi command */
.flash_cfg.cfg.cReadMode = 0x20, /*!< Config data for continuous read mode */
.flash_cfg.cfg.cRExit = 0xf0, /*!< Config data for exit continuous read mode */
.flash_cfg.cfg.burstWrapCmd = 0x77, /*!< Enable burst wrap command */
.flash_cfg.cfg.burstWrapCmdDmyClk = 0x03, /*!< Enable burst wrap command dummy clock */
.flash_cfg.cfg.burstWrapDataMode = 0x02, /*!< Data and address mode for this command */
.flash_cfg.cfg.burstWrapData = 0x40, /*!< Data to enable burst wrap */
.flash_cfg.cfg.deBurstWrapCmd = 0x77, /*!< Disable burst wrap command */
.flash_cfg.cfg.deBurstWrapCmdDmyClk = 0x03, /*!< Disable burst wrap command dummy clock */
.flash_cfg.cfg.deBurstWrapDataMode = 0x02, /*!< Data and address mode for this command */
.flash_cfg.cfg.deBurstWrapData = 0xf0, /*!< Data to disable burst wrap */
.flash_cfg.cfg.timeEsector = 300, /*!< 4K erase time */
.flash_cfg.cfg.timeE32k = 1200, /*!< 32K erase time */
.flash_cfg.cfg.timeE64k = 1200, /*!< 64K erase time */
.flash_cfg.cfg.timePagePgm = 50, /*!< Page program time */
.flash_cfg.cfg.timeCe = 30000, /*!< Chip erase time in ms */
.flash_cfg.cfg.pdDelay = 20, /*!< Release power down command delay time for wake up */
.flash_cfg.cfg.qeData = 0, /*!< QE set data */
.flash_cfg.crc32 = 0xdeadbeef,
/* clock cfg */
.clk_cfg.magiccode = 0x47464350,
.clk_cfg.cfg.xtal_type = 0x07, /*!< 0:None,1:24M,2:32M,3:38.4M,4:40M,5:26M,6:RC32M */
.clk_cfg.cfg.mcu_clk = 0x04, /*!< mcu_clk 0:RC32M,1:Xtal,2:cpupll 400M,3:wifipll 192M,4:wifipll 320M */
.clk_cfg.cfg.mcu_clk_div = 0x00,
.clk_cfg.cfg.mcu_bclk_div = 0x00,
.clk_cfg.cfg.mcu_pbclk_div = 0x03,
.clk_cfg.cfg.lp_div = 0x01,
.clk_cfg.cfg.dsp_clk = 0x03, /* 0:RC32M,1:Xtal,2:wifipll 240M,3:wifipll 320M,4:cpupll 400M */
.clk_cfg.cfg.dsp_clk_div = 0x00,
.clk_cfg.cfg.dsp_bclk_div = 0x01,
.clk_cfg.cfg.dsp_pbclk = 0x02, /* 0:RC32M,1:Xtal,2:wifipll 160M,3:cpupll 160M,4:wifipll 240M */
.clk_cfg.cfg.dsp_pbclk_div = 0x00,
.clk_cfg.cfg.emi_clk = 0x02, /*!< 0:mcu pbclk,1:cpupll 200M,2:wifipll 320M,3:cpupll 400M */
.clk_cfg.cfg.emi_clk_div = 0x01,
.clk_cfg.cfg.flash_clk_type = 0x01, /*!< 0:wifipll 120M,1:xtal,2:cpupll 100M,3:wifipll 80M,4:bclk,5:wifipll 96M */
.clk_cfg.cfg.flash_clk_div = 0x00,
.clk_cfg.cfg.wifipll_pu = 0x01,
.clk_cfg.cfg.aupll_pu = 0x01,
.clk_cfg.cfg.cpupll_pu = 0x01,
.clk_cfg.cfg.mipipll_pu = 0x01,
.clk_cfg.cfg.uhspll_pu = 0x01,
.clk_cfg.crc32 = 0xdeadbeef,
/* basic cfg */
.basic_cfg.sign_type = 0x0, /* [1: 0] for sign */
.basic_cfg.encrypt_type = 0x0, /* [3: 2] for encrypt */
.basic_cfg.key_sel = 0x0, /* [5: 4] key slot */
.basic_cfg.xts_mode = 0x0, /* [6] for xts mode */
.basic_cfg.aes_region_lock = 0x0, /* [7] rsvd */
.basic_cfg.no_segment = 0x1, /* [8] no segment info */
.basic_cfg.rsvd_0 = 0x0, /* [9] boot2 enable(rsvd_0) */
.basic_cfg.rsvd_1 = 0x0, /* [10] boot2 rollback(rsvd_1) */
.basic_cfg.cpu_master_id = 0x0, /* [14: 11] master id */
.basic_cfg.notload_in_bootrom = 0x0, /* [15] notload in bootrom */
.basic_cfg.crc_ignore = 0x1, /* [16] ignore crc */
.basic_cfg.hash_ignore = 0x1, /* [17] hash ignore */
.basic_cfg.power_on_mm = 0x1, /* [18] power on mm */
.basic_cfg.em_sel = 0x1, /* [21: 19] em_sel */
.basic_cfg.cmds_en = 0x1, /* [22] command spliter enable */
#if 0
# 0 : cmds bypass wrap commands to macro, original mode;
# 1 : cmds handle wrap commands, original mode;
# 2 : cmds bypass wrap commands to macro, cmds force wrap16 * 4 splitted into two wrap8 * 4;
# 3 : cmds handle wrap commands, cmds force wrap16 * 4 splitted into two wrap8 * 4
#endif
.basic_cfg.cmds_wrap_mode = 0x1, /* [24: 23] cmds wrap mode */
#if 0
# 0 : SF_CTRL_WRAP_LEN_8, 1 : SF_CTRL_WRAP_LEN_16, 2 : SF_CTRL_WRAP_LEN_32,
# 3 : SF_CTRL_WRAP_LEN_64, 9 : SF_CTRL_WRAP_LEN_4096
#endif
.basic_cfg.cmds_wrap_len = 0x9, /* [28: 25] cmds wrap len */
.basic_cfg.icache_invalid = 0x1, /* [29] icache invalid */
.basic_cfg.dcache_invalid = 0x1, /* [30] dcache invalid */
.basic_cfg.rsvd_3 = 0x0, /* [31] rsvd_3 */
.basic_cfg.group_image_offset = 0x00002000, /* flash controller offset */
.basic_cfg.aes_region_len = 0x00000000, /* aes region length */
.basic_cfg.img_len_cnt = 0x00004000, /* image length or segment count */
.basic_cfg.hash = { 0xdeadbeef }, /* hash of the image */
/* cpu cfg */
.cpu_cfg[0].config_enable = 0x01, /* coinfig this cpu */
.cpu_cfg[0].halt_cpu = 0x0, /* halt this cpu */
.cpu_cfg[0].cache_enable = 0x0, /* cache setting :only for BL Cache */
.cpu_cfg[0].cache_wa = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg[0].cache_wb = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg[0].cache_wt = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg[0].cache_way_dis = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg[0].rsvd = 0x0,
.cpu_cfg[0].cache_range_h = 0x00000000,
.cpu_cfg[0].cache_range_l = 0x00000000,
/* image_address_offset */
.cpu_cfg[0].image_address_offset = 0x0,
.cpu_cfg[0].rsvd0 = 0x58000000, /* rsvd0 */
.cpu_cfg[0].msp_val = 0x00000000, /* msp value */
/* cpu cfg */
.cpu_cfg[1].config_enable = 0x00, /* coinfig this cpu */
.cpu_cfg[1].halt_cpu = 0x0, /* halt this cpu */
.cpu_cfg[1].cache_enable = 0x0, /* cache setting :only for BL Cache */
.cpu_cfg[1].cache_wa = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg[1].cache_wb = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg[1].cache_wt = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg[1].cache_way_dis = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg[1].rsvd = 0x0,
.cpu_cfg[1].cache_range_h = 0x00000000,
.cpu_cfg[1].cache_range_l = 0x00000000,
/* image_address_offset */
.cpu_cfg[1].image_address_offset = 0x0,
.cpu_cfg[1].rsvd0 = 0x58000000, /* rsvd0 */
.cpu_cfg[1].msp_val = 0x00000000, /* msp value */
/* address of partition table 0 */ /* 4 */
.boot2_pt_table_0_rsvd = 0x00000000,
/* address of partition table 1 */ /* 4 */
.boot2_pt_table_1_rsvd = 0x00000000,
/* address of flashcfg table list */ /* 4 */
.flash_cfg_table_addr = 0x00000000,
/* flashcfg table list len */ /* 4 */
.flash_cfg_table_len = 0x00000000,
.rsvd1[0] = 0x20000320,
.rsvd1[1] = 0x00000000,
.rsvd1[2] = 0x2000F038,
.rsvd1[3] = 0x18000000,
.crc32 = 0xdeadbeef /* 4 */
};
__attribute__((section(".fw_header1"))) struct bootheader_t fw_header1 = {
.magiccode = 0x50414642,
.rivison = 0x00000001,
/*flash config */
.flash_cfg.magiccode = 0x47464346,
.flash_cfg.cfg.ioMode = 0x10, /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */
.flash_cfg.cfg.cReadSupport = 0x00, /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */
.flash_cfg.cfg.clkDelay = 0x01, /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */
.flash_cfg.cfg.clkInvert = 0x01, /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */
.flash_cfg.cfg.resetEnCmd = 0x66, /*!< Flash enable reset command */
.flash_cfg.cfg.resetCmd = 0x99, /*!< Flash reset command */
.flash_cfg.cfg.resetCreadCmd = 0xff, /*!< Flash reset continuous read command */
.flash_cfg.cfg.resetCreadCmdSize = 0x03, /*!< Flash reset continuous read command size */
.flash_cfg.cfg.jedecIdCmd = 0x9f, /*!< JEDEC ID command */
.flash_cfg.cfg.jedecIdCmdDmyClk = 0x00, /*!< JEDEC ID command dummy clock */
.flash_cfg.cfg.enter32BitsAddrCmd = 0xb7, /*!< Enter 32-bits addr command */
.flash_cfg.cfg.exit32BitsAddrCmd = 0xe9, /*!< Exit 32-bits addr command */
.flash_cfg.cfg.sectorSize = 0x04, /*!< *1024bytes */
.flash_cfg.cfg.mid = 0x00, /*!< Manufacturer ID */
.flash_cfg.cfg.pageSize = 0x100, /*!< Page size */
.flash_cfg.cfg.chipEraseCmd = 0xc7, /*!< Chip erase cmd */
.flash_cfg.cfg.sectorEraseCmd = 0x20, /*!< Sector erase command */
.flash_cfg.cfg.blk32EraseCmd = 0x52, /*!< Block 32K erase command,some Micron not support */
.flash_cfg.cfg.blk64EraseCmd = 0xd8, /*!< Block 64K erase command */
.flash_cfg.cfg.writeEnableCmd = 0x06, /*!< Need before every erase or program */
.flash_cfg.cfg.pageProgramCmd = 0x02, /*!< Page program cmd */
.flash_cfg.cfg.qpageProgramCmd = 0x32, /*!< QIO page program cmd */
.flash_cfg.cfg.qppAddrMode = 0x00, /*!< QIO page program address mode */
.flash_cfg.cfg.fastReadCmd = 0x0b, /*!< Fast read command */
.flash_cfg.cfg.frDmyClk = 0x01, /*!< Fast read command dummy clock */
.flash_cfg.cfg.qpiFastReadCmd = 0x0b, /*!< QPI fast read command */
.flash_cfg.cfg.qpiFrDmyClk = 0x01, /*!< QPI fast read command dummy clock */
.flash_cfg.cfg.fastReadDoCmd = 0x3b, /*!< Fast read dual output command */
.flash_cfg.cfg.frDoDmyClk = 0x01, /*!< Fast read dual output command dummy clock */
.flash_cfg.cfg.fastReadDioCmd = 0xbb, /*!< Fast read dual io comamnd */
.flash_cfg.cfg.frDioDmyClk = 0x00, /*!< Fast read dual io command dummy clock */
.flash_cfg.cfg.fastReadQoCmd = 0x6b, /*!< Fast read quad output comamnd */
.flash_cfg.cfg.frQoDmyClk = 0x01, /*!< Fast read quad output comamnd dummy clock */
.flash_cfg.cfg.fastReadQioCmd = 0xeb, /*!< Fast read quad io comamnd */
.flash_cfg.cfg.frQioDmyClk = 0x02, /*!< Fast read quad io comamnd dummy clock */
.flash_cfg.cfg.qpiFastReadQioCmd = 0xeb, /*!< QPI fast read quad io comamnd */
.flash_cfg.cfg.qpiFrQioDmyClk = 0x02, /*!< QPI fast read QIO dummy clock */
.flash_cfg.cfg.qpiPageProgramCmd = 0x02, /*!< QPI program command */
.flash_cfg.cfg.writeVregEnableCmd = 0x50, /*!< Enable write reg */
.flash_cfg.cfg.wrEnableIndex = 0x00, /*!< Write enable register index */
.flash_cfg.cfg.qeIndex = 0x01, /*!< Quad mode enable register index */
.flash_cfg.cfg.busyIndex = 0x00, /*!< Busy status register index */
.flash_cfg.cfg.wrEnableBit = 0x01, /*!< Write enable bit pos */
.flash_cfg.cfg.qeBit = 0x01, /*!< Quad enable bit pos */
.flash_cfg.cfg.busyBit = 0x00, /*!< Busy status bit pos */
.flash_cfg.cfg.wrEnableWriteRegLen = 0x02, /*!< Register length of write enable */
.flash_cfg.cfg.wrEnableReadRegLen = 0x01, /*!< Register length of write enable status */
.flash_cfg.cfg.qeWriteRegLen = 0x02, /*!< Register length of contain quad enable */
.flash_cfg.cfg.qeReadRegLen = 0x01, /*!< Register length of contain quad enable status */
.flash_cfg.cfg.releasePowerDown = 0xab, /*!< Release power down command */
.flash_cfg.cfg.busyReadRegLen = 0x01, /*!< Register length of contain busy status */
.flash_cfg.cfg.readRegCmd[0] = 0x05, /*!< Read register command buffer */
.flash_cfg.cfg.readRegCmd[1] = 0x35, /*!< Read register command buffer */
.flash_cfg.cfg.readRegCmd[2] = 0x00, /*!< Read register command buffer */
.flash_cfg.cfg.readRegCmd[3] = 0x00, /*!< Read register command buffer */
.flash_cfg.cfg.writeRegCmd[0] = 0x01, /*!< Write register command buffer */
.flash_cfg.cfg.writeRegCmd[1] = 0x01, /*!< Write register command buffer */
.flash_cfg.cfg.writeRegCmd[2] = 0x00, /*!< Write register command buffer */
.flash_cfg.cfg.writeRegCmd[3] = 0x00, /*!< Write register command buffer */
.flash_cfg.cfg.enterQpi = 0x38, /*!< Enter qpi command */
.flash_cfg.cfg.exitQpi = 0xff, /*!< Exit qpi command */
.flash_cfg.cfg.cReadMode = 0x20, /*!< Config data for continuous read mode */
.flash_cfg.cfg.cRExit = 0xf0, /*!< Config data for exit continuous read mode */
.flash_cfg.cfg.burstWrapCmd = 0x77, /*!< Enable burst wrap command */
.flash_cfg.cfg.burstWrapCmdDmyClk = 0x03, /*!< Enable burst wrap command dummy clock */
.flash_cfg.cfg.burstWrapDataMode = 0x02, /*!< Data and address mode for this command */
.flash_cfg.cfg.burstWrapData = 0x40, /*!< Data to enable burst wrap */
.flash_cfg.cfg.deBurstWrapCmd = 0x77, /*!< Disable burst wrap command */
.flash_cfg.cfg.deBurstWrapCmdDmyClk = 0x03, /*!< Disable burst wrap command dummy clock */
.flash_cfg.cfg.deBurstWrapDataMode = 0x02, /*!< Data and address mode for this command */
.flash_cfg.cfg.deBurstWrapData = 0xf0, /*!< Data to disable burst wrap */
.flash_cfg.cfg.timeEsector = 300, /*!< 4K erase time */
.flash_cfg.cfg.timeE32k = 1200, /*!< 32K erase time */
.flash_cfg.cfg.timeE64k = 1200, /*!< 64K erase time */
.flash_cfg.cfg.timePagePgm = 50, /*!< Page program time */
.flash_cfg.cfg.timeCe = 30000, /*!< Chip erase time in ms */
.flash_cfg.cfg.pdDelay = 20, /*!< Release power down command delay time for wake up */
.flash_cfg.cfg.qeData = 0, /*!< QE set data */
.flash_cfg.crc32 = 0xdeadbeef,
/* clock cfg */
.clk_cfg.magiccode = 0x47464350,
.clk_cfg.cfg.xtal_type = 0x07, /*!< 0:None,1:24M,2:32M,3:38.4M,4:40M,5:26M,6:RC32M */
.clk_cfg.cfg.mcu_clk = 0x04, /*!< mcu_clk 0:RC32M,1:Xtal,2:cpupll 400M,3:wifipll 192M,4:wifipll 320M */
.clk_cfg.cfg.mcu_clk_div = 0x00,
.clk_cfg.cfg.mcu_bclk_div = 0x00,
.clk_cfg.cfg.mcu_pbclk_div = 0x03,
.clk_cfg.cfg.lp_div = 0x01,
.clk_cfg.cfg.dsp_clk = 0x03, /* 0:RC32M,1:Xtal,2:wifipll 240M,3:wifipll 320M,4:cpupll 400M */
.clk_cfg.cfg.dsp_clk_div = 0x00,
.clk_cfg.cfg.dsp_bclk_div = 0x01,
.clk_cfg.cfg.dsp_pbclk = 0x02, /* 0:RC32M,1:Xtal,2:wifipll 160M,3:cpupll 160M,4:wifipll 240M */
.clk_cfg.cfg.dsp_pbclk_div = 0x00,
.clk_cfg.cfg.emi_clk = 0x02, /*!< 0:mcu pbclk,1:cpupll 200M,2:wifipll 320M,3:cpupll 400M */
.clk_cfg.cfg.emi_clk_div = 0x01,
.clk_cfg.cfg.flash_clk_type = 0x01, /*!< 0:wifipll 120M,1:xtal,2:cpupll 100M,3:wifipll 80M,4:bclk,5:wifipll 96M */
.clk_cfg.cfg.flash_clk_div = 0x00,
.clk_cfg.cfg.wifipll_pu = 0x01,
.clk_cfg.cfg.aupll_pu = 0x01,
.clk_cfg.cfg.cpupll_pu = 0x01,
.clk_cfg.cfg.mipipll_pu = 0x01,
.clk_cfg.cfg.uhspll_pu = 0x01,
.clk_cfg.crc32 = 0xdeadbeef,
/* basic cfg */
.basic_cfg.sign_type = 0x0, /* [1: 0] for sign */
.basic_cfg.encrypt_type = 0x0, /* [3: 2] for encrypt */
.basic_cfg.key_sel = 0x0, /* [5: 4] key slot */
.basic_cfg.xts_mode = 0x0, /* [6] for xts mode */
.basic_cfg.aes_region_lock = 0x0, /* [7] rsvd */
.basic_cfg.no_segment = 0x1, /* [8] no segment info */
.basic_cfg.rsvd_0 = 0x0, /* [9] boot2 enable(rsvd_0) */
.basic_cfg.rsvd_1 = 0x0, /* [10] boot2 rollback(rsvd_1) */
.basic_cfg.cpu_master_id = 0x0, /* [14: 11] master id */
.basic_cfg.notload_in_bootrom = 0x0, /* [15] notload in bootrom */
.basic_cfg.crc_ignore = 0x1, /* [16] ignore crc */
.basic_cfg.hash_ignore = 0x1, /* [17] hash ignore */
.basic_cfg.power_on_mm = 0x1, /* [18] power on mm */
.basic_cfg.em_sel = 0x1, /* [21: 19] em_sel */
.basic_cfg.cmds_en = 0x1, /* [22] command spliter enable */
#if 0
# 0 : cmds bypass wrap commands to macro, original mode;
# 1 : cmds handle wrap commands, original mode;
# 2 : cmds bypass wrap commands to macro, cmds force wrap16 * 4 splitted into two wrap8 * 4;
# 3 : cmds handle wrap commands, cmds force wrap16 * 4 splitted into two wrap8 * 4
#endif
.basic_cfg.cmds_wrap_mode = 0x1, /* [24: 23] cmds wrap mode */
#if 0
# 0 : SF_CTRL_WRAP_LEN_8, 1 : SF_CTRL_WRAP_LEN_16, 2 : SF_CTRL_WRAP_LEN_32,
# 3 : SF_CTRL_WRAP_LEN_64, 9 : SF_CTRL_WRAP_LEN_4096
#endif
.basic_cfg.cmds_wrap_len = 0x9, /* [28: 25] cmds wrap len */
.basic_cfg.icache_invalid = 0x1, /* [29] icache invalid */
.basic_cfg.dcache_invalid = 0x1, /* [30] dcache invalid */
.basic_cfg.rsvd_3 = 0x0, /* [31] rsvd_3 */
.basic_cfg.group_image_offset = 0x00011000, /* flash controller offset */
.basic_cfg.aes_region_len = 0x00000000, /* aes region length */
.basic_cfg.img_len_cnt = 0x00004000, /* image length or segment count */
.basic_cfg.hash = { 0xdeadbeef }, /* hash of the image */
/* cpu cfg */
.cpu_cfg[0].config_enable = 0x00, /* coinfig this cpu */
.cpu_cfg[0].halt_cpu = 0x0, /* halt this cpu */
.cpu_cfg[0].cache_enable = 0x0, /* cache setting :only for BL Cache */
.cpu_cfg[0].cache_wa = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg[0].cache_wb = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg[0].cache_wt = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg[0].cache_way_dis = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg[0].rsvd = 0x0,
.cpu_cfg[0].cache_range_h = 0x00000000,
.cpu_cfg[0].cache_range_l = 0x00000000,
/* image_address_offset */
.cpu_cfg[0].image_address_offset = 0x0,
.cpu_cfg[0].rsvd0 = 0x58000000, /* rsvd0 */
.cpu_cfg[0].msp_val = 0x00000000, /* msp value */
/* cpu cfg */
.cpu_cfg[1].config_enable = 0x01, /* coinfig this cpu */
.cpu_cfg[1].halt_cpu = 0x0, /* halt this cpu */
.cpu_cfg[1].cache_enable = 0x0, /* cache setting :only for BL Cache */
.cpu_cfg[1].cache_wa = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg[1].cache_wb = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg[1].cache_wt = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg[1].cache_way_dis = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg[1].rsvd = 0x0,
.cpu_cfg[1].cache_range_h = 0x00000000,
.cpu_cfg[1].cache_range_l = 0x00000000,
/* image_address_offset */
.cpu_cfg[1].image_address_offset = 0x0,
.cpu_cfg[1].rsvd0 = 0x58000000, /* rsvd0 */
.cpu_cfg[1].msp_val = 0x00000000, /* msp value */
/* address of partition table 0 */ /* 4 */
.boot2_pt_table_0_rsvd = 0x00000000,
/* address of partition table 1 */ /* 4 */
.boot2_pt_table_1_rsvd = 0x00000000,
/* address of flashcfg table list */ /* 4 */
.flash_cfg_table_addr = 0x00000000,
/* flashcfg table list len */ /* 4 */
.flash_cfg_table_len = 0x00000000,
.crc32 = 0xdeadbeef /* 4 */
};

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@ -0,0 +1,210 @@
#ifndef __FW_HEADER_H__
#define __FW_HEADER_H__
#include "stdint.h"
#include "stdio.h"
struct __attribute__((packed, aligned(4))) spi_flash_cfg_t {
uint8_t ioMode; /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */
uint8_t cReadSupport; /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */
uint8_t clkDelay; /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */
uint8_t clkInvert; /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */
uint8_t resetEnCmd; /*!< Flash enable reset command */
uint8_t resetCmd; /*!< Flash reset command */
uint8_t resetCreadCmd; /*!< Flash reset continuous read command */
uint8_t resetCreadCmdSize; /*!< Flash reset continuous read command size */
uint8_t jedecIdCmd; /*!< JEDEC ID command */
uint8_t jedecIdCmdDmyClk; /*!< JEDEC ID command dummy clock */
uint8_t enter32BitsAddrCmd; /*!< Enter 32-bits addr command */
uint8_t exit32BitsAddrCmd; /*!< Exit 32-bits addr command */
uint8_t sectorSize; /*!< *1024bytes */
uint8_t mid; /*!< Manufacturer ID */
uint16_t pageSize; /*!< Page size */
uint8_t chipEraseCmd; /*!< Chip erase cmd */
uint8_t sectorEraseCmd; /*!< Sector erase command */
uint8_t blk32EraseCmd; /*!< Block 32K erase command,some Micron not support */
uint8_t blk64EraseCmd; /*!< Block 64K erase command */
uint8_t writeEnableCmd; /*!< Need before every erase or program */
uint8_t pageProgramCmd; /*!< Page program cmd */
uint8_t qpageProgramCmd; /*!< QIO page program cmd */
uint8_t qppAddrMode; /*!< QIO page program address mode */
uint8_t fastReadCmd; /*!< Fast read command */
uint8_t frDmyClk; /*!< Fast read command dummy clock */
uint8_t qpiFastReadCmd; /*!< QPI fast read command */
uint8_t qpiFrDmyClk; /*!< QPI fast read command dummy clock */
uint8_t fastReadDoCmd; /*!< Fast read dual output command */
uint8_t frDoDmyClk; /*!< Fast read dual output command dummy clock */
uint8_t fastReadDioCmd; /*!< Fast read dual io comamnd */
uint8_t frDioDmyClk; /*!< Fast read dual io command dummy clock */
uint8_t fastReadQoCmd; /*!< Fast read quad output comamnd */
uint8_t frQoDmyClk; /*!< Fast read quad output comamnd dummy clock */
uint8_t fastReadQioCmd; /*!< Fast read quad io comamnd */
uint8_t frQioDmyClk; /*!< Fast read quad io comamnd dummy clock */
uint8_t qpiFastReadQioCmd; /*!< QPI fast read quad io comamnd */
uint8_t qpiFrQioDmyClk; /*!< QPI fast read QIO dummy clock */
uint8_t qpiPageProgramCmd; /*!< QPI program command */
uint8_t writeVregEnableCmd; /*!< Enable write reg */
uint8_t wrEnableIndex; /*!< Write enable register index */
uint8_t qeIndex; /*!< Quad mode enable register index */
uint8_t busyIndex; /*!< Busy status register index */
uint8_t wrEnableBit; /*!< Write enable bit pos */
uint8_t qeBit; /*!< Quad enable bit pos */
uint8_t busyBit; /*!< Busy status bit pos */
uint8_t wrEnableWriteRegLen; /*!< Register length of write enable */
uint8_t wrEnableReadRegLen; /*!< Register length of write enable status */
uint8_t qeWriteRegLen; /*!< Register length of contain quad enable */
uint8_t qeReadRegLen; /*!< Register length of contain quad enable status */
uint8_t releasePowerDown; /*!< Release power down command */
uint8_t busyReadRegLen; /*!< Register length of contain busy status */
uint8_t readRegCmd[4]; /*!< Read register command buffer */
uint8_t writeRegCmd[4]; /*!< Write register command buffer */
uint8_t enterQpi; /*!< Enter qpi command */
uint8_t exitQpi; /*!< Exit qpi command */
uint8_t cReadMode; /*!< Config data for continuous read mode */
uint8_t cRExit; /*!< Config data for exit continuous read mode */
uint8_t burstWrapCmd; /*!< Enable burst wrap command */
uint8_t burstWrapCmdDmyClk; /*!< Enable burst wrap command dummy clock */
uint8_t burstWrapDataMode; /*!< Data and address mode for this command */
uint8_t burstWrapData; /*!< Data to enable burst wrap */
uint8_t deBurstWrapCmd; /*!< Disable burst wrap command */
uint8_t deBurstWrapCmdDmyClk; /*!< Disable burst wrap command dummy clock */
uint8_t deBurstWrapDataMode; /*!< Data and address mode for this command */
uint8_t deBurstWrapData; /*!< Data to disable burst wrap */
uint16_t timeEsector; /*!< 4K erase time */
uint16_t timeE32k; /*!< 32K erase time */
uint16_t timeE64k; /*!< 64K erase time */
uint16_t timePagePgm; /*!< Page program time */
uint16_t timeCe; /*!< Chip erase time in ms */
uint8_t pdDelay; /*!< Release power down command delay time for wake up */
uint8_t qeData; /*!< QE set data */
};
struct __attribute__((packed, aligned(4))) boot_flash_cfg_t {
uint32_t magiccode;
struct spi_flash_cfg_t cfg;
uint32_t crc32;
};
struct __attribute__((packed, aligned(4))) sys_clk_cfg_t {
uint8_t xtal_type;
uint8_t mcu_clk;
uint8_t mcu_clk_div;
uint8_t mcu_bclk_div;
uint8_t mcu_pbclk_div;
uint8_t lp_div;
uint8_t dsp_clk;
uint8_t dsp_clk_div;
uint8_t dsp_bclk_div;
uint8_t dsp_pbclk;
uint8_t dsp_pbclk_div;
uint8_t emi_clk;
uint8_t emi_clk_div;
uint8_t flash_clk_type;
uint8_t flash_clk_div;
uint8_t wifipll_pu;
uint8_t aupll_pu;
uint8_t cpupll_pu;
uint8_t mipipll_pu;
uint8_t uhspll_pu;
};
struct __attribute__((packed, aligned(4))) boot_clk_cfg_t {
uint32_t magiccode;
struct sys_clk_cfg_t cfg;
uint32_t crc32;
};
struct __attribute__((packed, aligned(4))) boot_basic_cfg_t {
uint32_t sign_type : 2; /* [1: 0] for sign */
uint32_t encrypt_type : 2; /* [3: 2] for encrypt */
uint32_t key_sel : 2; /* [5: 4] key slot */
uint32_t xts_mode : 1; /* [6] for xts mode */
uint32_t aes_region_lock : 1; /* [7] rsvd */
uint32_t no_segment : 1; /* [8] no segment info */
uint32_t rsvd_0 : 1; /* [9] boot2 enable(rsvd_0) */
uint32_t rsvd_1 : 1; /* [10] boot2 rollback(rsvd_1) */
uint32_t cpu_master_id : 4; /* [14: 11] master id */
uint32_t notload_in_bootrom : 1; /* [15] notload in bootrom */
uint32_t crc_ignore : 1; /* [16] ignore crc */
uint32_t hash_ignore : 1; /* [17] hash ignore */
uint32_t power_on_mm : 1; /* [18] power on mm */
uint32_t em_sel : 3; /* [21: 19] em_sel */
uint32_t cmds_en : 1; /* [22] command spliter enable */
uint32_t cmds_wrap_mode : 2; /* [24: 23] cmds wrap mode */
uint32_t cmds_wrap_len : 4; /* [28: 25] cmds wrap len */
uint32_t icache_invalid : 1; /* [29] icache invalid */
uint32_t dcache_invalid : 1; /* [30] dcache invalid */
uint32_t rsvd_3 : 1; /* [31] rsvd_3 */
uint32_t group_image_offset; /* flash controller offset */
uint32_t aes_region_len; /* aes region length */
uint32_t img_len_cnt; /* image length or segment count */
uint32_t hash[32 / 4]; /* hash of the image */
};
struct __attribute__((packed, aligned(4))) boot_cpu_cfg_t {
uint8_t config_enable; /* coinfig this cpu */
uint8_t halt_cpu; /* halt this cpu */
uint8_t cache_enable : 1; /* cache setting */
uint8_t cache_wa : 1; /* cache setting */
uint8_t cache_wb : 1; /* cache setting */
uint8_t cache_wt : 1; /* cache setting */
uint8_t cache_way_dis : 4; /* cache setting */
uint8_t rsvd;
uint32_t cache_range_h; /* cache range high */
uint32_t cache_range_l; /* cache range low */
uint32_t image_address_offset; /* image_address_offset */
uint32_t rsvd0; /* rsvd0 */
uint32_t msp_val; /* msp value */
};
struct __attribute__((packed, aligned(4))) aesiv_cfg_t {
uint8_t aesiv[16];
uint32_t crc32;
};
struct __attribute__((packed, aligned(4))) pkey_cfg_t {
uint8_t eckeyx[32]; /* ec key in boot header */
uint8_t eckeyy[32]; /* ec key in boot header */
uint32_t crc32;
};
struct __attribute__((packed, aligned(4))) sign_cfg_t {
uint32_t sig_len;
uint8_t signature[32];
uint32_t crc32;
};
struct __attribute__((packed, aligned(4))) bootheader_t {
uint32_t magiccode; /* 4 */
uint32_t rivison; /* 4 */
struct boot_flash_cfg_t flash_cfg; /* 4 + 84 + 4 */
struct boot_clk_cfg_t clk_cfg; /* 4 + 20 + 4 */
struct boot_basic_cfg_t basic_cfg; /* 4 + 4 + 4 + 4 + 4*8 */
struct boot_cpu_cfg_t cpu_cfg[3]; /*24*3 */
uint32_t boot2_pt_table_0_rsvd; /* address of partition table 0 */ /* 4 */
uint32_t boot2_pt_table_1_rsvd; /* address of partition table 1 */ /* 4 */
uint32_t flash_cfg_table_addr; /* address of flashcfg table list */ /* 4 */
uint32_t flash_cfg_table_len; /* flashcfg table list len */ /* 4 */
uint32_t rsvd0[6]; /* rsvd */
uint32_t rsvd1[6]; /* rsvd */
uint32_t rsvd3[5]; /* 4 */
uint32_t crc32; /* 4 */
};
#endif

View file

@ -23,6 +23,7 @@ endif()
if(CONFIG_BSP_LCD)
target_sources(app PRIVATE lcd/lcd.c)
target_sources(app PRIVATE lcd/font.c)
target_sources(app PRIVATE lcd/spi/ili9341_spi.c)
target_sources(app PRIVATE lcd/spi/ili9488_spi.c)
target_sources(app PRIVATE lcd/spi/st7796_spi.c)
@ -30,8 +31,19 @@ target_sources(app PRIVATE lcd/spi/st7789v_spi.c)
sdk_add_include_directories(lcd)
endif()
# touch sensor driver
if(CONFIG_BSP_TOUCH)
target_sources(app PRIVATE touch/touch.c)
target_sources(app PRIVATE touch/ft6x36_i2c.c)
target_sources(app PRIVATE touch/gt911_i2c.c)
sdk_add_include_directories(touch)
endif()
# image sensor driver
if(CONFIG_BSP_IMAGE_SENSOR)
target_sources(app PRIVATE image_sensor/image_sensor.c)
sdk_add_include_directories(image_sensor)
if(CONFIG_BSP_CSI)
sdk_add_compile_definitions(-DCONFIG_BSP_CSI)
endif()
endif()

View file

@ -26,6 +26,165 @@
#include "image_sensor.h"
static struct image_sensor_command_s gc2053_init_list[] = {
#ifdef CONFIG_BSP_CSI
{ 0xfe, 0x80 },
{ 0xfe, 0x80 },
{ 0xfe, 0x80 },
{ 0xfe, 0x00 },
{ 0xf2, 0x00 },
{ 0xf3, 0x00 },
{ 0xf4, 0x36 },
{ 0xf5, 0xc0 },
{ 0xf6, 0x84 },
{ 0xf7, 0x11 },
{ 0xf8, 0x37 },
{ 0xf9, 0x82 },
{ 0xfc, 0x8e },
{ 0xfe, 0x00 },//mirror and flip
{ 0x17, 0x83 },
{ 0xfe, 0x00 },
{ 0x87, 0x18 },
{ 0xee, 0x30 },
{ 0xd0, 0xb7 },
{ 0x03, 0x04 },
{ 0x04, 0x60 },
{ 0x05, 0x04 },
{ 0x06, 0x4c },
{ 0x07, 0x00 },
{ 0x08, 0x64 },
{ 0x09, 0x00 },
{ 0x0a, 0x02 },
{ 0x0b, 0x00 },
{ 0x0c, 0x02 },
{ 0x0d, 0x04 },
{ 0x0e, 0x40 },
{ 0x12, 0xe2 },
{ 0x13, 0x16 },
{ 0x19, 0x0a },
{ 0x21, 0x1c },
{ 0x28, 0x0a },
{ 0x29, 0x24 },
{ 0x2b, 0x04 },
{ 0x32, 0xf8 },
{ 0x37, 0x03 },
{ 0x39, 0x15 },
{ 0x43, 0x07 },
{ 0x44, 0x40 },
{ 0x46, 0x0b },
{ 0x4b, 0x20 },
{ 0x4e, 0x08 },
{ 0x55, 0x20 },
{ 0x66, 0x05 },
{ 0x67, 0x05 },
{ 0x77, 0x01 },
{ 0x78, 0x00 },
{ 0x7c, 0x93 },
{ 0x8c, 0x12 },
{ 0x8d, 0x92 },
{ 0x90, 0x00 },
{ 0x41, 0x04 },
{ 0x42, 0xb0 },
{ 0x9d, 0x10 },
{ 0xce, 0x7c },
{ 0xd2, 0x41 },
{ 0xd3, 0xdc },
{ 0xe6, 0x50 },
{ 0xb6, 0xc0 },
{ 0xb0, 0x70 },
{ 0xb1, 0x01 },
{ 0xb2, 0x00 },
{ 0xb3, 0x00 },
{ 0xb4, 0x00 },
{ 0xb8, 0x01 },
{ 0xb9, 0x00 },
{ 0x26, 0x30 },
{ 0xfe, 0x01 },
{ 0x40, 0x23 },
{ 0x55, 0x07 },
{ 0x60, 0x40 },
{ 0xfe, 0x04 },
{ 0x14, 0x78 },
{ 0x15, 0x78 },
{ 0x16, 0x78 },
{ 0x17, 0x78 },
{ 0xfe, 0x01 },
{ 0x92, 0x01 },
{ 0x94, 0x04 },
{ 0x95, 0x04 },
{ 0x96, 0x38 },
{ 0x97, 0x07 },
{ 0x98, 0x80 },
/*skip frame*/
{ 0xfe, 0x01 },
{ 0x83, 0x01 },
{ 0x87, 0x50 },//0x50, skip 0, default:0x53,skip 3
{ 0xfe, 0x00 },
{ 0xfe, 0x01 },
{ 0x01, 0x05 },
{ 0x02, 0x89 },
{ 0x04, 0x00 },//DD_en
{ 0x07, 0xa6 },
{ 0x08, 0xa9 },
{ 0x09, 0xa8 },
{ 0x0a, 0xa7 },
{ 0x0b, 0xff },
{ 0x0c, 0xff },
{ 0x0f, 0x00 },
{ 0x50, 0x1c },
{ 0x89, 0x03 },
{ 0xfe, 0x04 },
{ 0x28, 0x86 },
{ 0x29, 0x86 },
{ 0x2a, 0x86 },
{ 0x2b, 0x68 },
{ 0x2c, 0x68 },
{ 0x2d, 0x68 },
{ 0x2e, 0x68 },
{ 0x2f, 0x68 },
{ 0x30, 0x4f },
{ 0x31, 0x68 },
{ 0x32, 0x67 },
{ 0x33, 0x66 },
{ 0x34, 0x66 },
{ 0x35, 0x66 },
{ 0x36, 0x66 },
{ 0x37, 0x66 },
{ 0x38, 0x62 },
{ 0x39, 0x62 },
{ 0x3a, 0x62 },
{ 0x3b, 0x62 },
{ 0x3c, 0x62 },
{ 0x3d, 0x62 },
{ 0x3e, 0x62 },
{ 0x3f, 0x62 },
{ 0xfe, 0x01 },
//{ 0x8c, 0x01 }, // test mode
{ 0x9a, 0x06 },
{ 0xfe, 0x00 },
{ 0x7b, 0x2a },
//{ 0x22, 0x0a }, // jz tmp
{ 0x23, 0x2d },
{ 0xfe, 0x03 },
{ 0x01, 0x27 },
{ 0x02, 0x56 },
//{ 0x03, 0xb6 }, // default is 0xb6
{ 0x03, 0x8e },
{ 0x12, 0x80 },
{ 0x13, 0x07 },
{ 0x15, 0x12 },
{ 0xfe, 0x01 },
{ 0x8c, 0x10 },
{ 0xfe, 0x00 },
{ 0x3e, 0x91 },
#else
{ 0xfe, 0x80 }, // page select
{ 0xfe, 0x80 },
{ 0xfe, 0x80 },
@ -155,7 +314,7 @@ static struct image_sensor_command_s gc2053_init_list[] = {
{ 0x3f, 0x62 },
/****DVP & MIPI****/
{ 0xfe, 0x01 },
// {0x8c,0x01}, // test mode
//{0x8c,0x01}, // test mode
//{0x9a,0x06}, /* VSYNC low pulse */
{ 0x9a, 0x02 }, /* VSYNC high pulse */
{ 0xfe, 0x00 },
@ -170,6 +329,7 @@ static struct image_sensor_command_s gc2053_init_list[] = {
{ 0xfe, 0x00 },
{ 0x3e, 0x40 },
#endif
};
static struct image_sensor_config_s gc2053_config = {
@ -183,7 +343,11 @@ static struct image_sensor_config_s gc2053_config = {
.resolution_y = 1080,
.id_addr = 0xf0f1,
.id_value = 0x2053,
#ifdef CONFIG_BSP_CSI
.pixel_clock = 66000000,
#else
.pixel_clock = 24000000,
#endif
.init_list_len = sizeof(gc2053_init_list)/sizeof(gc2053_init_list[0]),
.init_list = gc2053_init_list,
};

View file

@ -25,16 +25,18 @@
#include "gc0308.h"
#include "gc0328.h"
#include "gc2053.h"
#include "ov2685.h"
#include "bflb_i2c.h"
static struct image_sensor_config_s *sensor_list[] = {
NULL, &bf2013_config, &gc0308_config, &gc0328_config, &gc2053_config
NULL, &bf2013_config, &gc0308_config, &gc0328_config, &gc2053_config, &ov2685_config
};
void image_sensor_read(struct bflb_device_s *i2c, uint32_t sensor_index, struct image_sensor_command_s *read_list, uint32_t list_len)
{
uint32_t i;
struct bflb_i2c_msg_s msgs[2];
uint8_t buffer[2];
msgs[0].addr = sensor_list[sensor_index]->slave_addr;
msgs[0].flags = I2C_M_NOSTOP;
@ -47,7 +49,14 @@ void image_sensor_read(struct bflb_device_s *i2c, uint32_t sensor_index, struct
msgs[1].length = 1;
for(i=0;i<list_len;i++){
msgs[0].buffer = (uint8_t *)&read_list[i].address;
if (sensor_list[sensor_index]->reg_size == 1) {
buffer[0] = read_list[i].address & 0xff;
} else {
buffer[0] = read_list[i].address >> 8;
buffer[1] = read_list[i].address & 0xff;
}
msgs[0].buffer = buffer;
msgs[1].buffer = &read_list[i].paramete;
bflb_i2c_transfer(i2c, msgs, 2);
}
@ -57,6 +66,7 @@ void image_sensor_write(struct bflb_device_s *i2c, uint32_t sensor_index, struct
{
uint32_t i;
struct bflb_i2c_msg_s msgs[2];
uint8_t buffer[2];
msgs[0].addr = sensor_list[sensor_index]->slave_addr;
msgs[0].flags = I2C_M_NOSTOP;
@ -69,7 +79,14 @@ void image_sensor_write(struct bflb_device_s *i2c, uint32_t sensor_index, struct
msgs[1].length = 1;
for(i=0;i<list_len;i++){
msgs[0].buffer = (uint8_t *)&read_list[i].address;
if (sensor_list[sensor_index]->reg_size == 1) {
buffer[0] = read_list[i].address & 0xff;
} else {
buffer[0] = read_list[i].address >> 8;
buffer[1] = read_list[i].address & 0xff;
}
msgs[0].buffer = buffer;
msgs[1].buffer = &read_list[i].paramete;
bflb_i2c_transfer(i2c, msgs, 2);
}

View file

@ -0,0 +1,296 @@
/**
* @file image_sensor.h
* @brief
*
* Copyright (c) 2022 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#ifndef __OV2685_H__
#define __OV2685_H__
#include "image_sensor.h"
static struct image_sensor_command_s ov2685_init_list[] = {
{0x0103, 0x0001},
{0xffff, 0x0005},
{0x3002, 0x0000},
{0x3016, 0x001c},
{0x3018, 0x0084},
{0x301d, 0x00f0},
{0x3020, 0x0000},
{0x3082, 0x002c},
{0x3083, 0x0003},
{0x3084, 0x0007},
{0x3085, 0x0003},
{0x3086, 0x0000},
{0x3087, 0x0000},
{0x3501, 0x004e},
{0x3502, 0x00e0},
{0x3503, 0x0003},
{0x350b, 0x0036},
{0x3600, 0x00b4},
{0x3603, 0x0035},
{0x3604, 0x0024},
{0x3605, 0x0000},
{0x3620, 0x0024},
{0x3621, 0x0034},
{0x3622, 0x0003},
{0x3628, 0x0010},
{0x3705, 0x003c},
{0x370a, 0x0021},
{0x370c, 0x0050},
{0x370d, 0x00c0},
{0x3717, 0x0058},
{0x3718, 0x0080},
{0x3720, 0x0000},
{0x3721, 0x0009},
{0x3722, 0x0006},
{0x3723, 0x0059},
{0x3738, 0x0099},
{0x3781, 0x0080},
{0x3784, 0x000c},
{0x3789, 0x0060},
{0x3800, 0x0000},
{0x3801, 0x0000},
{0x3802, 0x0000},
{0x3803, 0x0000},
{0x3804, 0x0006},
{0x3805, 0x004f},
{0x3806, 0x0004},
{0x3807, 0x00bf},
{0x3808, 0x0006},
{0x3809, 0x0040},
{0x380a, 0x0004},
{0x380b, 0x00b0},
{0x380c, 0x0006},
{0x380d, 0x00a4},
{0x380e, 0x0005},
{0x380f, 0x000e},
{0x3810, 0x0000},
{0x3811, 0x0008},
{0x3812, 0x0000},
{0x3813, 0x0008},
{0x3814, 0x0011},
{0x3815, 0x0011},
{0x3819, 0x0004},
{0x3820, 0x00c0},
{0x3821, 0x0000},
{0x3a06, 0x0001},
{0x3a07, 0x0084},
{0x3a08, 0x0001},
{0x3a09, 0x0043},
{0x3a0a, 0x0024},
{0x3a0b, 0x0060},
{0x3a0c, 0x0028},
{0x3a0d, 0x0060},
{0x3a0e, 0x0004},
{0x3a0f, 0x008c},
{0x3a10, 0x0005},
{0x3a11, 0x000c},
{0x4000, 0x0081},
{0x4001, 0x0040},
{0x4008, 0x0002},
{0x4009, 0x0009},
{0x4300, 0x0032},//output format
{0x430e, 0x0000},
{0x4602, 0x0002},
{0x4837, 0x001e},
{0x5000, 0x00ff},
{0x5001, 0x0005},
{0x5002, 0x0032},
{0x5003, 0x0004},
{0x5004, 0x00ff},
{0x5005, 0x0012},
//{0x5080, 0x0092},//test pattern
{0x0100, 0x0001},
{0x0101, 0x0001},
{0x1000, 0x0003},
{0x0129, 0x0010},
{0x5180, 0x00f4},
{0x5181, 0x0011},
{0x5182, 0x0041},
{0x5183, 0x0042},
{0x5184, 0x0078},
{0x5185, 0x0058},
{0x5186, 0x00b5},
{0x5187, 0x00b2},
{0x5188, 0x0008},
{0x5189, 0x000e},
{0x518a, 0x000c},
{0x518b, 0x004c},
{0x518c, 0x0038},
{0x518d, 0x00f8},
{0x518e, 0x0004},
{0x518f, 0x007f},
{0x5190, 0x0040},
{0x5191, 0x005f},
{0x5192, 0x0040},
{0x5193, 0x00ff},
{0x5194, 0x0040},
{0x5195, 0x0007},
{0x5196, 0x0004},
{0x5197, 0x0004},
{0x5198, 0x0000},
{0x5199, 0x0005},
{0x519a, 0x00d2},
{0x519b, 0x0010},
{0x5200, 0x0009},
{0x5201, 0x0000},
{0x5202, 0x0006},
{0x5203, 0x0020},
{0x5204, 0x0041},
{0x5205, 0x0016},
{0x5206, 0x0000},
{0x5207, 0x0005},
{0x520b, 0x0030},
{0x520c, 0x0075},
{0x520d, 0x0000},
{0x520e, 0x0030},
{0x520f, 0x0075},
{0x5210, 0x0000},
{0x5280, 0x0014},
{0x5281, 0x0002},
{0x5282, 0x0002},
{0x5283, 0x0004},
{0x5284, 0x0006},
{0x5285, 0x0008},
{0x5286, 0x000c},
{0x5287, 0x0010},
{0x5300, 0x00c5},
{0x5301, 0x00a0},
{0x5302, 0x0006},
{0x5303, 0x000a},
{0x5304, 0x0030},
{0x5305, 0x0060},
{0x5306, 0x0090},
{0x5307, 0x00c0},
{0x5308, 0x0082},
{0x5309, 0x0000},
{0x530a, 0x0026},
{0x530b, 0x0002},
{0x530c, 0x0002},
{0x530d, 0x0000},
{0x530e, 0x000c},
{0x530f, 0x0014},
{0x5310, 0x001a},
{0x5311, 0x0020},
{0x5312, 0x0080},
{0x5313, 0x004b},
{0x5380, 0x0001},
{0x5381, 0x0052},
{0x5382, 0x0000},
{0x5383, 0x004a},
{0x5384, 0x0000},
{0x5385, 0x00b6},
{0x5386, 0x0000},
{0x5387, 0x008d},
{0x5388, 0x0000},
{0x5389, 0x003a},
{0x538a, 0x0000},
{0x538b, 0x00a6},
{0x538c, 0x0000},
{0x5400, 0x000d},
{0x5401, 0x0018},
{0x5402, 0x0031},
{0x5403, 0x005a},
{0x5404, 0x0065},
{0x5405, 0x006f},
{0x5406, 0x0077},
{0x5407, 0x0080},
{0x5408, 0x0087},
{0x5409, 0x008f},
{0x540a, 0x00a2},
{0x540b, 0x00b2},
{0x540c, 0x00cc},
{0x540d, 0x00e4},
{0x540e, 0x00f0},
{0x540f, 0x00a0},
{0x5410, 0x006e},
{0x5411, 0x0006},
{0x5480, 0x0019},
{0x5481, 0x0000},
{0x5482, 0x0009},
{0x5483, 0x0012},
{0x5484, 0x0004},
{0x5485, 0x0006},
{0x5486, 0x0008},
{0x5487, 0x000c},
{0x5488, 0x0010},
{0x5489, 0x0018},
{0x5500, 0x0002},
{0x5501, 0x0003},
{0x5502, 0x0004},
{0x5503, 0x0005},
{0x5504, 0x0006},
{0x5505, 0x0008},
{0x5506, 0x0000},
{0x5600, 0x0002},
{0x5603, 0x0040},
{0x5604, 0x0028},
{0x5609, 0x0020},
{0x560a, 0x0060},
{0x5800, 0x0003},
{0x5801, 0x0024},
{0x5802, 0x0002},
{0x5803, 0x0040},
{0x5804, 0x0034},
{0x5805, 0x0005},
{0x5806, 0x0012},
{0x5807, 0x0005},
{0x5808, 0x0003},
{0x5809, 0x003c},
{0x580a, 0x0002},
{0x580b, 0x0040},
{0x580c, 0x0026},
{0x580d, 0x0005},
{0x580e, 0x0052},
{0x580f, 0x0006},
{0x5810, 0x0003},
{0x5811, 0x0028},
{0x5812, 0x0002},
{0x5813, 0x0040},
{0x5814, 0x0024},
{0x5815, 0x0005},
{0x5816, 0x0042},
{0x5817, 0x0006},
{0x5818, 0x000d},
{0x5819, 0x0040},
{0x581a, 0x0004},
{0x581b, 0x000c},
{0x3a03, 0x004c},
{0x3a04, 0x0040},
{0x3503, 0x0000},
};
static struct image_sensor_config_s ov2685_config = {
.name = "OV2685",
.output_format = IMAGE_SENSOR_FORMAT_YUV422_YUYV,
.slave_addr = 0x3c,
.id_size = 2,
.reg_size = 2,
.h_blank = 0xde,
.resolution_x = 1600,
.resolution_y = 1200,
.id_addr = 0x300a300b,
.id_value = 0x2685,
.pixel_clock = 66000000,
.init_list_len = sizeof(ov2685_init_list)/sizeof(ov2685_init_list[0]),
.init_list = ov2685_init_list,
};
#endif /* __OV2685_H__ */

View file

@ -0,0 +1,165 @@
/**
* @file ft6x36_i2c.c
* @brief
*
* Copyright (c) 2021 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#include "touch.h"
#ifdef TOUCH_I2C_FT6X36
#include "bflb_mtimer.h"
#include "bflb_gpio.h"
#include "bflb_i2c.h"
#include "ft6x36_i2c.h"
static struct bflb_device_s *touch_ft6x36_i2c = NULL;
static void ft6x36_i2c_gpio_init(void)
{
struct bflb_device_s *ft63x6_i2c_gpio = NULL;
ft63x6_i2c_gpio = bflb_device_get_by_name("gpio");
/* I2C0_SCL */
bflb_gpio_init(ft63x6_i2c_gpio, GPIO_PIN_10, GPIO_FUNC_I2C0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_2);
/* I2C0_SDA */
bflb_gpio_init(ft63x6_i2c_gpio, GPIO_PIN_11, GPIO_FUNC_I2C0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_2);
}
static int ft6x36_i2c_peripheral_init(void)
{
touch_ft6x36_i2c = bflb_device_get_by_name("i2c0");
if (touch_ft6x36_i2c) {
// printf("ft6x36 i2c gpio init\r\n");
/* init i2c gpio */
ft6x36_i2c_gpio_init();
/* init i2c 200k */
bflb_i2c_init(touch_ft6x36_i2c, 200000);
} else {
printf("i2c device get fail\r\n");
return -1;
}
return 0;
}
static int ft6x36_i2c_read_byte(uint8_t register_addr, uint8_t *data_buf, uint16_t len)
{
static struct bflb_i2c_msg_s msg[2];
msg[0].addr = FT6236_I2C_SLAVE_ADDR;
msg[0].flags = I2C_M_NOSTOP;
msg[0].buffer = &register_addr;
msg[0].length = 1;
msg[1].flags = I2C_M_READ;
msg[1].buffer = data_buf;
msg[1].length = len;
bflb_i2c_transfer(touch_ft6x36_i2c, msg, 2);
return 0;
}
int ft6x36_get_gesture_id()
{
uint8_t data_buf = FT6X36_GEST_ID_NO_GESTURE;
if (ft6x36_i2c_read_byte(FT6X36_GEST_ID_REG, &data_buf, 1)) {
return -1;
}
return data_buf;
}
int ft6x36_i2c_init(touch_coord_t *max_value)
{
uint8_t data_buf;
printf("ft6x36 i2c init\r\n");
ft6x36_i2c_peripheral_init();
if (ft6x36_i2c_read_byte(FT6X36_PANEL_ID_REG, &data_buf, 1)) {
return -1;
}
printf("Touch Device ID: 0x%02x\r\n", data_buf);
if (ft6x36_i2c_read_byte(FT6X36_CHIPSELECT_REG, &data_buf, 1)) {
return -1;
}
printf("Touch Chip ID: 0x%02x\r\n", data_buf);
if (ft6x36_i2c_read_byte(FT6X36_DEV_MODE_REG, &data_buf, 1)) {
return -1;
}
printf("Touch Device mode: 0x%02x\r\n", data_buf);
if (ft6x36_i2c_read_byte(FT6X36_FIRMWARE_ID_REG, &data_buf, 1)) {
return -1;
}
printf("Touch Firmware ID: 0x%02x\r\n", data_buf);
if (ft6x36_i2c_read_byte(FT6X36_RELEASECODE_REG, &data_buf, 1)) {
return -1;
}
printf("Touch Release code: 0x%02x\r\n", data_buf);
return 0;
}
int ft6x36_i2c_read(uint8_t *point_num, touch_coord_t *touch_coord, uint8_t max_num)
{
uint8_t data_buf[5];
*point_num = 0;
if (point_num == NULL || touch_coord == NULL || max_num == 0) {
return -1;
}
if (ft6x36_i2c_read_byte(FT6X36_TD_STAT_REG, &data_buf[0], 1)) {
return -1;
}
data_buf[0] &= FT6X36_TD_STAT_MASK;
/* no touch or err */
if (data_buf[0] == 0 || data_buf[0] > 2) {
if (data_buf[0] > 2) {
return -2;
} else {
return 0;
}
}
/* Get the first point */
ft6x36_i2c_read_byte(FT6X36_P1_XH_REG, &data_buf[1], 4);
touch_coord[0].coord_x = (data_buf[1] & FT6X36_MSB_MASK) << 8 | (data_buf[2] & FT6X36_LSB_MASK);
touch_coord[0].coord_y = (data_buf[3] & FT6X36_MSB_MASK) << 8 | (data_buf[4] & FT6X36_LSB_MASK);
*point_num = 1;
/* Get the second point */
if (data_buf[0] > 1 && max_num > 1) {
ft6x36_i2c_read_byte(FT6X36_P2_XH_REG, &data_buf[1], 4);
touch_coord[1].coord_x = (data_buf[1] & FT6X36_MSB_MASK) << 8 | (data_buf[2] & FT6X36_LSB_MASK);
touch_coord[1].coord_y = (data_buf[3] & FT6X36_MSB_MASK) << 8 | (data_buf[4] & FT6X36_LSB_MASK);
*point_num = 2;
}
return 0;
}
#endif

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/**
* @file ft6x36_i2c.h
* @brief
*
* Copyright (c) 2021 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#ifndef _FT6X36_I2C_H
#define _FT6X36_I2C_H
#include "bflb_core.h"
#include "touch.h"
#define FT6236_I2C_SLAVE_ADDR 0x38
/* Maximum border values of the touchscreen pad that the chip can handle */
#define FT6X36_MAX_WIDTH ((uint16_t)800)
#define FT6X36_MAX_HEIGHT ((uint16_t)480)
/* Max detectable simultaneous touch points */
#define FT6X36_I2C_MAX_POINT 2
/* Register of the current mode */
#define FT6X36_DEV_MODE_REG 0x00
/* Possible modes as of FT6X36_DEV_MODE_REG */
#define FT6X36_DEV_MODE_WORKING 0x00
#define FT6X36_DEV_MODE_FACTORY 0x04
#define FT6X36_DEV_MODE_MASK 0x70
#define FT6X36_DEV_MODE_SHIFT 4
/* Gesture ID register */
#define FT6X36_GEST_ID_REG 0x01
/* Possible values returned by FT6X36_GEST_ID_REG */
#define FT6X36_GEST_ID_NO_GESTURE 0x00
#define FT6X36_GEST_ID_MOVE_UP 0x10
#define FT6X36_GEST_ID_MOVE_RIGHT 0x14
#define FT6X36_GEST_ID_MOVE_DOWN 0x18
#define FT6X36_GEST_ID_MOVE_LEFT 0x1C
#define FT6X36_GEST_ID_ZOOM_IN 0x48
#define FT6X36_GEST_ID_ZOOM_OUT 0x49
/* Status register: stores number of active touch points (0, 1, 2) */
#define FT6X36_TD_STAT_REG 0x02
#define FT6X36_TD_STAT_MASK 0x0F
#define FT6X36_TD_STAT_SHIFT 0x00
/* Touch events */
#define FT6X36_TOUCH_EVT_FLAG_PRESS_DOWN 0x00
#define FT6X36_TOUCH_EVT_FLAG_LIFT_UP 0x01
#define FT6X36_TOUCH_EVT_FLAG_CONTACT 0x02
#define FT6X36_TOUCH_EVT_FLAG_NO_EVENT 0x03
#define FT6X36_TOUCH_EVT_FLAG_SHIFT 6
#define FT6X36_TOUCH_EVT_FLAG_MASK (3 << FT6X36_TOUCH_EVT_FLAG_SHIFT)
#define FT6X36_MSB_MASK 0x0F
#define FT6X36_MSB_SHIFT 0
#define FT6X36_LSB_MASK 0xFF
#define FT6X36_LSB_SHIFT 0
#define FT6X36_P1_XH_REG 0x03
#define FT6X36_P1_XL_REG 0x04
#define FT6X36_P1_YH_REG 0x05
#define FT6X36_P1_YL_REG 0x06
#define FT6X36_P1_WEIGHT_REG 0x07 /* Register reporting touch pressure - read only */
#define FT6X36_TOUCH_WEIGHT_MASK 0xFF
#define FT6X36_TOUCH_WEIGHT_SHIFT 0
#define FT6X36_P1_MISC_REG 0x08 /* Touch area register */
#define FT6X36_TOUCH_AREA_MASK (0x04 << 4) /* Values related to FT6X36_Pn_MISC_REG */
#define FT6X36_TOUCH_AREA_SHIFT 0x04
#define FT6X36_P2_XH_REG 0x09
#define FT6X36_P2_XL_REG 0x0A
#define FT6X36_P2_YH_REG 0x0B
#define FT6X36_P2_YL_REG 0x0C
#define FT6X36_P2_WEIGHT_REG 0x0D
#define FT6X36_P2_MISC_REG 0x0E
/* Threshold for touch detection */
#define FT6X36_TH_GROUP_REG 0x80
#define FT6X36_THRESHOLD_MASK 0xFF /* Values FT6X36_TH_GROUP_REG : threshold related */
#define FT6X36_THRESHOLD_SHIFT 0
#define FT6X36_TH_DIFF_REG 0x85 /* Filter function coefficients */
#define FT6X36_CTRL_REG 0x86 /* Control register */
#define FT6X36_CTRL_KEEP_ACTIVE_MODE 0x00 /* Will keep the Active mode when there is no touching */
#define FT6X36_CTRL_KEEP_AUTO_SWITCH_MONITOR_MODE 0x01 /* Switching from Active mode to Monitor mode automatically when there is no touching */
#define FT6X36_TIME_ENTER_MONITOR_REG 0x87 /* The time period of switching from Active mode to Monitor mode when there is no touching */
#define FT6X36_PERIOD_ACTIVE_REG 0x88 /* Report rate in Active mode */
#define FT6X36_PERIOD_MONITOR_REG 0x89 /* Report rate in Monitor mode */
#define FT6X36_RADIAN_VALUE_REG 0x91 /* The value of the minimum allowed angle while Rotating gesture mode */
#define FT6X36_OFFSET_LEFT_RIGHT_REG 0x92 /* Maximum offset while Moving Left and Moving Right gesture */
#define FT6X36_OFFSET_UP_DOWN_REG 0x93 /* Maximum offset while Moving Up and Moving Down gesture */
#define FT6X36_DISTANCE_LEFT_RIGHT_REG 0x94 /* Minimum distance while Moving Left and Moving Right gesture */
#define FT6X36_DISTANCE_UP_DOWN_REG 0x95 /* Minimum distance while Moving Up and Moving Down gesture */
#define FT6X36_LIB_VER_H_REG 0xA1 /* High 8-bit of LIB Version info */
#define FT6X36_LIB_VER_L_REG 0xA2 /* Low 8-bit of LIB Version info */
#define FT6X36_CHIPSELECT_REG 0xA3 /* 0x36 for ft6236; 0x06 for ft6206 */
#define FT6X36_POWER_MODE_REG 0xA5
#define FT6X36_FIRMWARE_ID_REG 0xA6
#define FT6X36_RELEASECODE_REG 0xAF
#define FT6X36_PANEL_ID_REG 0xA8
#define FT6X36_OPMODE_REG 0xBC
int ft6x36_i2c_init(touch_coord_t *max_value);
int ft6x36_i2c_get_gesture_id();
int ft6x36_i2c_read(uint8_t *point_num, touch_coord_t *touch_coord, uint8_t max_num);
#endif /* __FT6X36_H */

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/**
* @file gt911_i2c.c
* @brief
*
* Copyright (c) 2022 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#include "touch.h"
#ifdef TOUCH_I2C_GT911
#include "bflb_mtimer.h"
#include "bflb_gpio.h"
#include "bflb_i2c.h"
#include "gt911_i2c.h"
#define BL_RDWD_FRM_BYTEP(p) ((p[3] << 24) | (p[2] << 16) | (p[1] << 8) | (p[0]))
static struct bflb_device_s *touch_gt911_i2c = NULL;
static void gt911_i2c_gpio_init(void)
{
struct bflb_device_s *gt911_i2c_gpio = NULL;
gt911_i2c_gpio = bflb_device_get_by_name("gpio");
/* I2C0_SCL */
bflb_gpio_init(gt911_i2c_gpio, GPIO_PIN_6, GPIO_FUNC_I2C0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_2);
/* I2C0_SDA */
bflb_gpio_init(gt911_i2c_gpio, GPIO_PIN_9, GPIO_FUNC_I2C0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_2);
}
static int gt911_i2c_peripheral_init(void)
{
touch_gt911_i2c = bflb_device_get_by_name("i2c0");
if (touch_gt911_i2c) {
// printf("gt911 i2c gpio init\r\n");
/* init i2c gpio */
gt911_i2c_gpio_init();
/* init i2c 200k */
bflb_i2c_init(touch_gt911_i2c, 200000);
} else {
printf("i2c device get fail\r\n");
return -1;
}
return 0;
}
static int gt911_i2c_read_byte(uint16_t register_addr, uint8_t *data_buf, uint16_t len)
{
static struct bflb_i2c_msg_s msg[2];
msg[0].addr = GT911_I2C_SLAVE_ADDR;
msg[0].flags = I2C_M_NOSTOP;
msg[0].buffer = (uint8_t *)(&register_addr);
msg[0].length = 2;
msg[1].addr = GT911_I2C_SLAVE_ADDR;
msg[1].flags = I2C_M_READ;
msg[1].buffer = data_buf;
msg[1].length = len;
bflb_i2c_transfer(touch_gt911_i2c, msg, 2);
return 0;
}
static int gt911_i2c_write_byte(uint16_t register_addr, uint8_t *data_buf, uint16_t len)
{
static struct bflb_i2c_msg_s msg[2];
msg[0].addr = GT911_I2C_SLAVE_ADDR;
msg[0].flags = I2C_M_NOSTOP;
msg[0].buffer = (uint8_t *)(&register_addr);
msg[0].length = 2;
msg[1].addr = GT911_I2C_SLAVE_ADDR;
msg[1].flags = 0;
msg[1].buffer = data_buf;
msg[1].length = len;
bflb_i2c_transfer(touch_gt911_i2c, msg, 2);
return 0;
}
int gt911_i2c_get_gesture_id()
{
uint8_t data_buf = 0;
if (gt911_i2c_read_byte(GT911_READ_XY_REG, &data_buf, 1)) {
return -1;
}
return data_buf;
}
int gt911_i2c_init(touch_coord_t *max_value)
{
uint8_t data_buf[5] = { 0 };
uint32_t product_id = 0;
uint16_t x_max = 0, y_max = 0;
gt911_i2c_peripheral_init();
if (gt911_i2c_read_byte(GT911_PRODUCT_ID_REG, data_buf, 4)) {
printf("touch i2c read error\r\n");
return -1;
}
product_id = BL_RDWD_FRM_BYTEP(data_buf);
printf("Touch Product ID: 0x%08x\r\n", product_id);
if (product_id == GT911_PRODUCT_ID) {
#if 0
data_buf[0] = 0;
data_buf[1] = (uint8_t)(max_value->coord_x << 8);
data_buf[2] = (uint8_t)(max_value->coord_x);
data_buf[3] = (uint8_t)(max_value->coord_y << 8);
data_buf[4] = (uint8_t)(max_value->coord_y);
if (gt911_i2c_write_byte(GT911_CONFIG_REG, data_buf, 5)) {
return -1;
}
if (gt911_i2c_write_byte(GT911_CONFIG_REG + (0x0005 << 8), (void *)g_gt911_cfg_params + 5, (sizeof(g_gt911_cfg_params) / sizeof(g_gt911_cfg_params[0]) - 5))) {
return -1;
}
#else
if (gt911_i2c_write_byte(GT911_CONFIG_REG, (void *)g_gt911_cfg_params, (sizeof(g_gt911_cfg_params) / sizeof(g_gt911_cfg_params[0])))) {
return -1;
}
#endif
} else {
printf("Touch Product ID read fail!\r\n");
return -1;
}
if (gt911_i2c_read_byte(GT911_FIRMWARE_VERSION_REG, data_buf, 2)) {
return -1;
}
printf("Touch Firmware Version: 0x%04x\r\n", data_buf);
if (gt911_i2c_read_byte(GT911_X_RESOLUTION, data_buf, 4)) {
return -1;
}
x_max = (((uint16_t)data_buf[1] << 8) | data_buf[0]);
y_max = (((uint16_t)data_buf[3] << 8) | data_buf[2]);
printf("Touch Resolution %dx%d \r\n", x_max, y_max);
return 0;
}
int gt911_i2c_read(uint8_t *point_num, touch_coord_t *touch_coord, uint8_t max_num)
{
uint8_t data_buf[8 * GT911_I2C_MAX_POINT] = { 0 };
uint8_t read_num;
*point_num = 0;
if (point_num == NULL || touch_coord == NULL || max_num == 0) {
return -1;
}
if (gt911_i2c_read_byte(GT911_READ_XY_REG, data_buf, 1)) {
return -1;
}
/* no touch */
if (data_buf[0] == 0) {
return 0;
}
if (data_buf[0] > GT911_I2C_MAX_POINT) {
data_buf[0] = GT911_I2C_MAX_POINT;
}
read_num = (data_buf[0] > max_num) ? max_num : data_buf[0];
/* read gt911 reg */
gt911_i2c_read_byte(GT911_READ_XY_REG, data_buf, (8 * read_num));
/* get point coordinates */
for (uint8_t i = 0; i < read_num; i++) {
uint8_t *p_data = &data_buf[i * 8];
touch_coord[i].coord_x = (uint16_t)p_data[3] << 8 | p_data[2];
touch_coord[i].coord_y = (uint16_t)p_data[5] << 8 | p_data[4];
}
*point_num = read_num;
data_buf[0] = 0;
gt911_i2c_write_byte(GT911_READ_XY_REG, data_buf, 1);
return 0;
}
#endif

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/**
* @file gt911_i2c.h
* @brief
*
* Copyright (c) 2022 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#ifndef _GT911_I2C_H
#define _GT911_I2C_H
#include "bflb_core.h"
#include "touch.h"
#define GT911_CUSTOM_CFG (1)
#define GT911_I2C_SLAVE_ADDR (0xBA >> 1) // #define GT911_ADDR (0xBA) //(0x28) /* slave addr */
#define GT911_READ_XY_REG (0x4E81) //(0x814E) /* 坐标寄存器 */
#define GT911_CLEARBUF_REG (0x4E81) //(0x814E) /* 清除坐标寄存器 */
#define GT911_POINT1_REG (0x4F81) //(0x814f) /* point 1 reg */
#define GT911_POINT2_REG (0x5781) //(0x8157) /* point 2 reg */
#define GT911_POINT3_REG (0x5F81) //(0x815f) /* point 3 reg */
#define GT911_POINT4_REG (0x6781) //(0x8167) /* point 4 reg */
#define GT911_POINT5_REG (0x6F81) //(0x816f) /* point 5 reg */
#define GT911_CONFIG_REG (0x4780) //(0x8047) /* 配置参数寄存器 */
#define GT911_COMMAND_REG (0x4080) //(0x8040) /* 实时命令 */
#define GT911_PRODUCT_ID_REG (0x4081) //(0x8140) /* 芯片ID */
#define GT911_VENDOR_ID_REG (0x4A81) //(0x814A) /* 当前模组选项信息 */
#define GT911_CONFIG_VERSION_REG (0x4780) //(0x8047) /* 配置文件版本号 */
#define GT911_CONFIG_CHECKSUM_REG (0xFF80) //(0x80FF) /* 配置文件校验码 */
#define GT911_FIRMWARE_VERSION_REG (0x4481) //(0x8144) /* 固件版本号 */
#define GT911_X_RESOLUTION (0x4681) //(0x8146) /* x 坐标分辨率 */
#define GT911_Y_RESOLUTION (0x4881) //(0x8148) /* y 坐标分辨率 */
#define GT911_PRODUCT_ID (0x00313139)
/* Maximum border values of the touchscreen pad that the chip can handle */
#if GT911_CUSTOM_CFG
#define GT911_MAX_WIDTH ((uint16_t)320)
#define GT911_MAX_HEIGHT ((uint16_t)480)
#define GT911_INT_TRIGGER (0)
#else
#define GT911_MAX_WIDTH ((uint16_t)4096)
#define GT911_MAX_HEIGHT ((uint16_t)4096)
#define GT911_INT_TRIGGER (1)
#endif
/* Max detectable simultaneous touch points */
#define GT911_I2C_MAX_POINT 5
/* GT911 配置参数,一次性写入 */
static const uint8_t g_gt911_cfg_params[] = {
#if 1
/*KDC CFG*/
0x00, 0x40, 0x01, 0xE0, 0x01, 0x0A, 0x05, 0x00,
0x01, 0x08, 0x28, 0x05, 0x50, 0x32, 0x03, 0x05,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x86, 0x26, 0x07, 0x17, 0x15,
0x31, 0x0D, 0x00, 0x00, 0x01, 0xBA, 0x03, 0x1D,
0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x64, 0x32,
0x00, 0x00, 0x00, 0x0F, 0x4B, 0x94, 0xC5, 0x02,
0x07, 0x00, 0x00, 0x04, 0x9B, 0x11, 0x00, 0x72,
0x18, 0x00, 0x57, 0x21, 0x00, 0x42, 0x2E, 0x00,
0x35, 0x40, 0x00, 0x35, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x12, 0x10, 0x0E, 0x0C, 0x0A, 0x08, 0x06, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x22, 0x21,
0x20, 0x1F, 0x1E, 0x1D, 0x00, 0x02, 0x04, 0x06,
0x08, 0x0A, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0xDC, 0x01
#else
0x00, //0x8047 版本号 发送 0x00 初始化为 A
0x40, 0x01, //0x8048/8049 X坐标输出最大值 320
0xE0, 0x01, //0x804a/804b Y坐标输出最大值 480
0x0A, //0x804c 输出触点个数上限
0x05, //0x804d x2y 坐标交换,软件降噪,下降沿触发
0x00, //0x804e reserved
0x01, //0x804f 手指按下去抖动次数
0x08, //0x8050 原始坐标窗口滤波值
0x28, //0x8051 大面积触点个数
0x05, //0x8052 噪声消除值
0x50, //0x8053 屏上触摸点从无到有的阈值
0x32, //0x8054 屏上触摸点从有到无的阈值
0x03, //0x8055 进低功耗时间 s
0x05, //0x8056 坐标上报率
0x00, //0x8057 X坐标输出门上限
0x00, //0x8058 Y坐标输出门上限
0x00, 0X00, //0x8059-0x805a reserved
0x00, //0x805b reserved
0x00, //0x805c reserved
0x00, //0x805d 划线过程中小filter设置
0x00, //0x805e 拉伸区间 1 系数
0x00, //0x805f 拉伸区间 2 系数
0x00, //0x8060 拉伸区间 3 系数
0x00, //0x8061 各拉伸区间基数
0x00, //0x8062 Driver Group A number
0x00, //0x8063 Driver Group B number
0x00, //0x8064 Sensor Group B | A number
0x00, //0x8065 驱动组A的驱动频率倍频系数
0x00, //0x8066 驱动组B的驱动频率倍频系数
0x00, //0x8067 驱动组A、B的基频
0x04, //0x8068
0x00, //0x8069 相邻两次驱动信号输出时间间隔
0x00, //0x806a
0x00, //0x806b 、、
0x02, //0x806c 、、
0x03, //0x806d 原始值放大系数
0x1D, //0x806e 、、
0x00, //0x806f reserved
0x01, //0x8070 、、
0x00, 0x00, //reserved
0x00, //0x8073 、、
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //0x8071 - 0x8079 reserved
0x50, //0x807a 跳频范围的起点频率
0xA0, //0x807b 跳频范围的终点频率
0x94, //0x807c 多次噪声检测后确定噪声量1-63有效
0xD5, //0x807d 噪声检测超时时间
0x02, //0x807e 、、
0x07, //0x807f 判别有干扰的门限
0x00, 0x00, //0x8081 reserved
0x04, //0x8082 跳频检测区间频段1中心点基频适用于驱动A、B
0xA4, //0x8083
0x55, //0x8084 跳频检测区间频段1中心点倍频系数
0x00, //0x8085 跳频检测区间频段2中心点基频(驱动A、B在此基础上换算)
0x91, //0x8086
0x62, //0x8087 跳频检测区间频段2中心点倍频系数
0x00, //0x8088 跳频检测区间频段3中心点基频适用于驱动A、B
0x80, //0x8089
0x71, //0x808a 跳频检测区间频段3中心点倍频系数
0x00, //0x808b 跳频检测区间频段4中心点基频适用于驱动A、B
0x71, //0x808c
0x82, //0x808d 跳频检测区间频段4中心点倍频系数
0x00, //0x808e 跳频检测区间频段5中心点基频适用于驱动A、B
0x65, //0x808f
0x95, //0x8090 跳频检测区间频段5中心点倍频系数
0x00, 0x65, //reserved
0x00, //0x8093 key1位置 0无按键
0x00, //0x8094 key2位置 0无按键
0x00, //0x8095 key3位置 0无按键
0x00, //0x8096 key4位置 0无按键
0x00, //0x8097 reserved
0x00, //0x8098 reserved
0x00, //0x8099 reserved
0x00, //0x809a reserved
0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //0x809b-0x80b2 reserved
0x00, //0x80b3 合框距离
0x00, //0x80b4
0x00, 0x00, //0x80b6 reserved
0x06, //0x80b7
0x08, //0x80b8
0x0A, //0x80b9
0x0C, //0x80ba
0x0E, //0x80bb
0x10, //0x80bc
0x12, //0x80bd
0x14, //0x80be
0x16, //0x80bf
0x18, //0x80c0
0x1A, //0x80c1
0x1C, //0x80c2
0xFF, //0x80c3
0xFF, //0x80c4
0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //0x80c5-0x80d4 reserved
0x00, //0x80d5
0x02, //0x80d6
0x04, //0x80d7
0x06, //0x80d8
0x08, //0x80d9
0x0A, //0x80da
0x0C, //0x80db
0x0F, //0x80dc
0x10, //0x80dd
0x12, //0x80de
0x13, //0x80df
0x14, //0x80e0
0x16, //0x80e1
0x18, //0x80e2
0x1C, //0x80e3
0x1D, //0x80e4
0x1E, //0x80e5
0x1F, //0x80e6
0x20, //0x80e7
0x21, //0x80e8
0xFF, //0x80e9
0xFF, //0x80ea
0xFF, //0x80eb
0xFF, //0x80ec
0xFF, //0x80ed
0xFF, //0x80ee
0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //0x80ef-0x80fe reserved
0x0B, //0x80ff 配置信息校验
0x01 //0x8100 配置以更新标记
#endif
};
typedef struct
{
uint8_t touch_point_flag;
uint8_t touch_key_sts;
uint16_t x0;
uint16_t y0;
uint16_t p0;
uint16_t x1;
uint16_t y1;
uint16_t p1;
uint16_t x2;
uint16_t y2;
uint16_t p2;
uint16_t x3;
uint16_t y3;
uint16_t p3;
uint16_t x4;
uint16_t y4;
uint16_t p4;
} gt911_point_t;
int gt911_i2c_init(touch_coord_t *max_value);
int gt911_i2c_get_gesture_id();
int gt911_i2c_read(uint8_t *point_num, touch_coord_t *touch_coord, uint8_t max_num);
#endif /* __gt911_H */

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bsp/common/touch/touch.c Normal file
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/**
* @file touch.c
* @brief
*
* Copyright (c) 2021 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#include "touch.h"
int touch_init(touch_coord_t *max_value)
{
return _TOUCH_FUNC_DEFINE(init, max_value);
}
int touch_read(uint8_t *point_num, touch_coord_t *touch_coord, uint8_t max_num)
{
return _TOUCH_FUNC_DEFINE(read, point_num, touch_coord, max_num);
}

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/**
* @file touch.h
* @brief
*
* Copyright (c) 2021 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#ifndef _TOUCH_H_
#define _TOUCH_H_
#include "bflb_core.h"
/* spi interface
TOUCH_SPI_XPT2046 // Not currently supported
*/
/* i2c interface
TOUCH_I2C_FT6X36
TOUCH_I2C_GT911
*/
/* Select Touch Type */
#define TOUCH_I2C_FT6X36
#define TOUCH_INTERFACE_SPI 1
#define TOUCH_INTERFACE_I2C 2
typedef struct
{
uint16_t coord_x;
uint16_t coord_y;
} touch_coord_t;
#if defined TOUCH_SPI_XPT2046
#include "xpt2046_spi.h"
#define TOUCH_INTERFACE_TYPE TOUCH_INTERFACE_SPI
#define TOUCH_MAX_POINT XPT2046_MAX_POINT
#define _TOUCH_FUNC_DEFINE(_func, ...) xpt2046_spi_##_func(__VA_ARGS__)
#elif defined TOUCH_I2C_FT6X36
#include "ft6x36_i2c.h"
#define TOUCH_INTERFACE_TYPE TOUCH_INTERFACE_I2C
#define TOUCH_MAX_POINT FT6X36_I2C_MAX_POINT
#define _TOUCH_FUNC_DEFINE(_func, ...) ft6x36_i2c_##_func(__VA_ARGS__)
#elif defined TOUCH_I2C_GT911
#include "gt911_i2c.h"
#define TOUCH_INTERFACE_TYPE TOUCH_INTERFACE_I2C
#define TOUCH_MAX_POINT GT911_I2C_MAX_POINT
#define _TOUCH_FUNC_DEFINE(_func, ...) gt911_i2c_##_func(__VA_ARGS__)
#elif
#error "Please select a touch type"
#endif
int touch_init(touch_coord_t *max_value);
int touch_read(uint8_t *point_num, touch_coord_t *touch_coord, uint8_t max_num);
#endif