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* use nuttx libc, disable system libc
* use tlsf as default
* update lhal flash driver
* add example readme
* add flash ini for new flash tool
* add fw header for new flash tool
This commit is contained in:
jzlv 2023-01-17 20:54:15 +08:00
parent 89592fc9a3
commit 356f258e83
554 changed files with 79150 additions and 46596 deletions
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170
drivers/soc/bl616/std/include/bl616_auadc.h Normal file
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@ -0,0 +1,170 @@
#ifndef _BFLB_AUADC_H
#define _BFLB_AUADC_H
#include "bflb_core.h"
/**
* @defgroup AUADC_SAMPLING_RATE auadc sampling rate
*/
#define AUADC_SAMPLING_RATE_8K 0 /* audio mode */
#define AUADC_SAMPLING_RATE_16K 1 /* audio mode */
#define AUADC_SAMPLING_RATE_24K 2 /* audio mode, same as 22.02K, adjust the AUPLL clock */
#define AUADC_SAMPLING_RATE_32K 3 /* audio mode */
#define AUADC_SAMPLING_RATE_48K 4 /* audio mode, same as 44.1K, adjust the AUPLL clock */
#define AUADC_SAMPLING_RATE_MEASURE_128K 8 /* only used in ADC measurement mode */
#define AUADC_SAMPLING_RATE_MEASURE_256K 9 /* only used in ADC measurement mode */
#define AUADC_SAMPLING_RATE_MEASURE_512K 10 /* only used in ADC measurement mode */
/**
* @}
*/
/**
* @defgroup AUADC_INPUT_MODE auadc input mode
*/
#define AUADC_INPUT_MODE_ADC 0 /* Analog ADC */
#define AUADC_INPUT_MODE_PDM_L 1 /* PDM left channel */
#define AUADC_INPUT_MODE_PDM_R 2 /* PDM right channel */
/**
* @}
*/
/**
* @defgroup AUADC_DATA_FORMAT auadc data format
*/
#define AUADC_DATA_FORMAT_16BIT 3
#define AUADC_DATA_FORMAT_20BIT 2
#define AUADC_DATA_FORMAT_24BIT 1
#define AUADC_DATA_FORMAT_32BIT 0
/**
* @}
*/
/**
* @brief AUADC_ADC_ANALOG_CH auadc adc input ch
*/
#define AUADC_ADC_ANALOG_CH_0 0
#define AUADC_ADC_ANALOG_CH_1 1
#define AUADC_ADC_ANALOG_CH_2 2
#define AUADC_ADC_ANALOG_CH_3 3
#define AUADC_ADC_ANALOG_CH_4 4
#define AUADC_ADC_ANALOG_CH_5 5
#define AUADC_ADC_ANALOG_CH_6 6
#define AUADC_ADC_ANALOG_CH_7 7
/**
* @}
*/
/**
* @brief AUADC_ADC_MEASURE_RATE auadc adc Sampling rate in measurement mode
*/
#define AUADC_ADC_MEASURE_RATE_SPS_2_5 0
#define AUADC_ADC_MEASURE_RATE_SPS_5 1
#define AUADC_ADC_MEASURE_RATE_SPS_10 2
#define AUADC_ADC_MEASURE_RATE_SPS_20 3
#define AUADC_ADC_MEASURE_RATE_SPS_25 4
#define AUADC_ADC_MEASURE_RATE_SPS_50 5
#define AUADC_ADC_MEASURE_RATE_SPS_100 6
#define AUADC_ADC_MEASURE_RATE_SPS_200 7
#define AUADC_ADC_MEASURE_RATE_SPS_400 8
#define AUADC_ADC_MEASURE_RATE_SPS_800 9
#define AUADC_ADC_MEASURE_RATE_SPS_1000 10
#define AUADC_ADC_MEASURE_RATE_SPS_2000 11
#define AUADC_ADC_MEASURE_RATE_SPS_4000 12
/**
* @}
*/
/**
* @brief AUADC_ADC_MODE auadc adc mode
*/
#define AUADC_ADC_MODE_AUDIO 0
#define AUADC_ADC_MODE_MEASURE 1
/**
* @}
*/
/**
* @brief AUADC_ADC_PGA_MODE auadc adc mode, Ac or DC, differential or single
*/
#define AUADC_ADC_PGA_MODE_AC_DIFFER 0
#define AUADC_ADC_PGA_MODE_AC_SINGLE 1
#define AUADC_ADC_PGA_MODE_DC_DIFFER 2
#define AUADC_ADC_PGA_MODE_DC_SINGLE 3
/**
* @}
*/
/** @defgroup AUADC_INTSTS auadc interrupt status definition
* @{
*/
#define AUADC_INTSTS_FIFO_OVER (1 << 1)
#define AUADC_INTSTS_FIFO_UNDER (1 << 2)
#define AUADC_INTSTS_FIFO_AVAILABLE (1 << 3)
/**
* @}
*/
/** @defgroup AUADC_CMD auadc feature control cmd definition
* @{
*/
#define AUADC_CMD_RECORD_START (0x01)
#define AUADC_CMD_RECORD_STOP (0x02)
#define AUADC_CMD_SET_VOLUME_VAL (0x03)
#define AUADC_CMD_SET_PGA_GAIN_VAL (0x04)
#define AUADC_CMD_CLEAR_RX_FIFO (0x05)
#define AUADC_CMD_GET_RX_FIFO_CNT (0x06)
/**
* @}
*/
/**
* @brief auadc initialization configuration structure
*
* @param sampling_rate auadc sampling rate, use @ref AUADC_SAMPLING_RATE
* @param input_mode auadc mode, use @ref AUADC_INPUT_MODE
* @param data_format auadc fifo data format, use @ref AUADC_DATA_FORMAT
* @param fifo_threshold auadc tx fifo threshold, 0 ~ 15
*/
struct bflb_auadc_init_config_s {
uint8_t sampling_rate;
uint8_t input_mode;
uint8_t data_format;
uint8_t fifo_threshold;
};
/**
* @brief auadc adc analog initialization configuration structure
*
* @param analog_adc_en auadc sampling rate, use true or false
* @param adc_mode auadc adc work pattern, use @ref AUADC_ADC_MODE
* @param adc_pga_mode auadc adc PGA mode, use @ref AUADC_ADC_PGA_MODE
* @param adc_pga_posi_ch auadc adc positive channel selection, use @ref AUADC_ADC_ANALOG_CH
* @param adc_pga_nega_ch auadc adc negative channel selection, This channel is valid only when adc_pga_mode is differential, use @ref AUADC_ADC_ANALOG_CH
* @param adc_pga_gain auadc adc PGA Gain control, 6dB ~ 42dB, step by 3db
* @param adc_measure_rate auadc adc sampling rate in measurement mode @256K_measure, use @ref AUADC_ADC_MEASURE_RATE
*/
struct bflb_auadc_adc_init_config_s {
uint8_t auadc_analog_en;
uint8_t adc_mode;
uint8_t adc_pga_mode;
uint8_t adc_pga_posi_ch;
uint8_t adc_pga_nega_ch;
uint8_t adc_pga_gain;
uint8_t adc_measure_rate;
};
int bflb_auadc_init(struct bflb_device_s *dev, const struct bflb_auadc_init_config_s *config);
int bflb_auadc_adc_init(struct bflb_device_s *dev, const struct bflb_auadc_adc_init_config_s *config);
int bflb_auadc_link_rxdma(struct bflb_device_s *dev, bool enable);
int bflb_auadc_int_mask(struct bflb_device_s *dev, uint32_t mask);
int bflb_auadc_get_intstatus(struct bflb_device_s *dev);
int bflb_auadc_feature_control(struct bflb_device_s *dev, int cmd, size_t arg);
#endif

68
drivers/soc/bl616/std/include/bl616_common_s.h
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@ -1,68 +0,0 @@
#ifndef __BL616_COMMON_S_H__
#define __BL616_COMMON_S_H__
#include "bl616.h"
#include "bl616_common.h"
#include "bflb_platform.h"
/** @addtogroup BL616_Peripheral_Driver
* @{
*/
/** @addtogroup COMMON_S
* @{
*/
/** @defgroup COMMON_S_Public_Types
* @{
*/
/*@} end of group COMMON_S_Public_Types */
/** @defgroup COMMON_S_Public_Constants
* @{
*/
/** @defgroup DRIVER_INT_PERIPH
* @{
*/
/*@} end of group DRIVER_INT_PERIPH */
/** @defgroup DRIVER_INT_MASK
* @{
*/
/*@} end of group COMMON_S_Public_Constants */
/** @defgroup COMMON_S_Public_Macros
* @{
*/
/**
* @brief error_number Type definition
*/
typedef enum {
COPY_SUCCESS = 0,
PARAM_ERROR = 1,
BUFFER_OVERLAP = 2,
SIZE_MISMATCHING = 3,
DST_OVERFLOW = 4,
}errno_t;
/**
* @brief Interrupt callback function type
*/
/*@} end of group DRIVER_Public_Macro */
/** @defgroup DRIVER_Public_FunctionDeclaration
* @brief DRIVER functions declaration
* @{
*/
errno_t memcpy_s(void *dst, size_t dstSize, const void *src, size_t count);
/*@} end of group DRIVER_COMMON_S */
#endif /* __BL616_COMMON_S_H__ */

4
drivers/soc/bl616/std/include/bl616_glb.h
View file

@ -42,11 +42,11 @@
#include "pds_reg.h"
#include "bl616_gpio.h"
#include "bl616_hbn.h"
#include "bl616_sf_ctrl.h"
#include "bl616_sf_cfg.h"
#include "bl616_aon.h"
#include "bl616_pds.h"
#include "bl616_common.h"
#include "bflb_sf_ctrl.h"
#include "bflb_sf_cfg.h"
/** @addtogroup BL616_Peripheral_Driver
* @{

3
drivers/soc/bl616/std/include/bl616_glb_gpio.h
View file

@ -41,11 +41,10 @@
#include "pds_reg.h"
#include "bl616_gpio.h"
#include "bl616_hbn.h"
#include "bl616_sf_ctrl.h"
// #include "bl616_sf_cfg.h"
#include "bl616_aon.h"
#include "bl616_pds.h"
#include "bl616_common.h"
#include "bflb_sf_ctrl.h"
/** @addtogroup BL616_Peripheral_Driver
* @{

6
drivers/soc/bl616/std/include/bl616_hbn.h
View file

@ -39,8 +39,8 @@
#include "hbn_reg.h"
#include "bl616_aon.h"
#include "bl616_l1c.h"
#include "bl616_sflash.h"
#include "bl616_common.h"
#include "bflb_sflash.h"
/** @addtogroup BL616_Peripheral_Driver
* @{
@ -293,7 +293,7 @@ typedef struct
uint32_t sleepTime; /*!< HBN sleep time */
uint8_t gpioWakeupSrc; /*!< GPIO Wakeup source */
HBN_GPIO_INT_Trigger_Type gpioTrigType; /*!< GPIO Triger type */
SPI_Flash_Cfg_Type *flashCfg; /*!< Flash config pointer, used when power down flash */
spi_flash_cfg_type *flashCfg; /*!< Flash config pointer, used when power down flash */
HBN_LEVEL_Type hbnLevel; /*!< HBN level */
HBN_LDO_LEVEL_Type ldoLevel; /*!< LDO level */
uint8_t dcdcPuSeq; /*!< power on dcdc sequence */
@ -579,7 +579,7 @@ void HBN_OUT1_IRQHandler(void);
#endif
/*----------*/
void HBN_Mode_Enter(HBN_APP_CFG_Type *cfg);
void HBN_Power_Down_Flash(SPI_Flash_Cfg_Type *flashCfg);
void HBN_Power_Down_Flash(spi_flash_cfg_type *flashCfg);
void HBN_Enable(uint32_t aGPIOIeCfg, HBN_LDO_LEVEL_Type ldoLevel, HBN_LEVEL_Type hbnLevel, uint8_t dcdcPuSeq);
BL_Err_Type HBN_Reset(void);
/*----------*/

4
drivers/soc/bl616/std/include/bl616_mfg_flash.h
View file

@ -2,7 +2,7 @@
#define __BL616_MFG_FLASH_H__
#include "stdint.h"
#include "bl616_xip_sflash.h"
#include "bflb_xip_sflash.h"
typedef struct rf_para_flash_tag {
uint32_t magic; //"RFPA"
@ -16,7 +16,7 @@ typedef struct rf_para_flash_tag {
uint32_t crc32;
} rf_para_flash_t;
int mfg_flash_init(SPI_Flash_Cfg_Type *flashCfg);
int mfg_flash_init(spi_flash_cfg_type *flashCfg);
int mfg_flash_write_xtal_capcode_pre(uint8_t capcode, uint8_t program);
void mfg_flash_write_xtal_capcode(void);
int mfg_flash_read_xtal_capcode(uint8_t *capcode, uint8_t reload);

4
drivers/soc/bl616/std/include/bl616_mfg_media.h
View file

@ -5,8 +5,8 @@
#include "bl616_mfg_efuse.h"
#include "bl616_mfg_flash.h"
int mfg_media_init_need_lock(SPI_Flash_Cfg_Type *flashCfg);
int mfg_media_init_with_lock(SPI_Flash_Cfg_Type *flashCfg);
int mfg_media_init_need_lock(spi_flash_cfg_type *flashCfg);
int mfg_media_init_with_lock(spi_flash_cfg_type *flashCfg);
uint8_t mfg_media_is_xtal_capcode_slot_empty(uint8_t reload);
int mfg_media_write_xtal_capcode_pre_need_lock(uint8_t capcode, uint8_t program);
int mfg_media_write_xtal_capcode_pre_with_lock(uint8_t capcode, uint8_t program);

10
drivers/soc/bl616/std/include/bl616_pds.h
View file

@ -41,10 +41,10 @@
#include "bl616_clock.h"
#include "bl616_aon.h"
#include "bl616_hbn.h"
#include "bl616_sflash.h"
#include "bl616_sf_ctrl.h"
#include "bl616_common.h"
#include "bl616_acomp.h"
#include "bflb_sflash.h"
#include "bflb_sf_ctrl.h"
#define PDS_WAKEUP_BY_PDS_TIMER_EN PDS_WAKEUP_BY_PDS_TIMER_EN
#define PDS_WAKEUP_BY_PDS_TIMER_EN_POS (10U)
@ -445,7 +445,7 @@ typedef struct
uint8_t xtalType; /*!< XTal type, used when user choose turn off PLL, PDS will turn on when exit PDS mode */
uint8_t flashContRead; /*!< Whether enable flash continue read */
uint32_t sleepTime; /*!< PDS sleep time */
SPI_Flash_Cfg_Type *flashCfg; /*!< Flash config pointer, used when power down flash */
spi_flash_cfg_type *flashCfg; /*!< Flash config pointer, used when power down flash */
PDS_LDO_LEVEL_Type ldoLevel; /*!< LDO level */
void (*preCbFun)(void); /*!< Pre callback function */
void (*postCbFun)(void); /*!< Post callback function */
@ -547,8 +547,8 @@ BL_Err_Type PDS_Set_GPIO_Pad_IntMask(GLB_GPIO_Type pad, BL_Mask_Type intMask);
BL_Err_Type PDS_Set_GPIO_Pad_IntMode(PDS_GPIO_INT_SET_Type set, PDS_GPIO_INT_TRIG_Type trig);
BL_Err_Type PDS_Set_GPIO_Pad_IntClr(PDS_GPIO_INT_SET_Type set);
BL_Sts_Type PDS_Get_GPIO_Pad_IntStatus(GLB_GPIO_Type pad);
BL_Err_Type PDS_Set_Flash_Pad_Pull_None(SF_Ctrl_Pin_Select pinCfg);
BL_Err_Type PDS_Set_Flash_Pad_Pull_None_Fast(SF_Ctrl_Pin_Select pinCfg);
BL_Err_Type PDS_Set_Flash_Pad_Pull_None(uint8_t pinCfg);
BL_Err_Type PDS_Set_Flash_Pad_Pull_None_Fast(uint8_t pinCfg);
BL_Err_Type PDS_Disable_GPIO_Keep(void);
BL_Err_Type PDS_Set_MCU0_Clock_Enable(void);
BL_Err_Type PDS_Set_MCU0_Clock_Disable(void);

4
drivers/soc/bl616/std/include/bl616_romapi_patch.h
View file

@ -36,9 +36,9 @@
#ifndef __BL616_ROMAPI_PATCH_H__
#define __BL616_ROMAPI_PATCH_H__
#include "bflb_sflash.h"
#include "bflb_xip_sflash.h"
#include "bl616_pds.h"
#include "bl616_sflash.h"
#include "bl616_xip_sflash.h"
#include "bl616_clock.h"
// #include "bl616_uart.h"

155
drivers/soc/bl616/std/include/bl616_romdriver_e907.h
View file

@ -37,12 +37,15 @@
#define __BL616_ROMDRIVER_E907_H__
#include "bl616_glb.h"
#include "bl616_glb_gpio.h"
#include "bl616_pds.h"
#include "bl616_hbn.h"
#include "bl616_clock.h"
#include "bl616_sflash.h"
#include "bl616_xip_sflash.h"
#include "bl616_ef_ctrl.h"
#include "bflb_sf_ctrl.h"
#include "bflb_sflash.h"
#include "bflb_sf_cfg.h"
#include "bflb_xip_sflash.h"
// #include "bl616_uart.h"
/** @addtogroup bl616_Peripheral_Driver
@ -1393,7 +1396,7 @@ typedef enum {
((void (*) (HBN_APP_CFG_Type *cfg))ROM_APITABLE[ROM_API_INDEX_HBN_Mode_Enter])
#define RomDriver_HBN_Power_Down_Flash \
((void (*) (SPI_Flash_Cfg_Type *flashCfg))ROM_APITABLE[ROM_API_INDEX_HBN_Power_Down_Flash])
((void (*) (spi_flash_cfg_type *flashCfg))ROM_APITABLE[ROM_API_INDEX_HBN_Power_Down_Flash])
#define RomDriver_L1C_DCache_Clean_All \
((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_L1C_DCache_Clean_All])
@ -1462,10 +1465,10 @@ typedef enum {
((BL_Err_Type (*) (PDS_CTRL_RAM1_Type *ram1Cfg, PDS_CTRL_RAM2_Type *ram2Cfg, PDS_CTRL_RAM3_Type *ram3Cfg, PDS_CTRL_RAM4_Type *ram4Cfg))ROM_APITABLE[ROM_API_INDEX_PDS_RAM_Config])
#define RomDriver_PDS_Set_Flash_Pad_Pull_None \
((BL_Err_Type (*) (SF_Ctrl_Pin_Select pinCfg))ROM_APITABLE[ROM_API_INDEX_PDS_Set_Flash_Pad_Pull_None])
((BL_Err_Type (*) (uint8_t pinCfg))ROM_APITABLE[ROM_API_INDEX_PDS_Set_Flash_Pad_Pull_None])
#define RomDriver_PDS_Set_Flash_Pad_Pull_None_Fast \
((BL_Err_Type (*) (SF_Ctrl_Pin_Select pinCfg))ROM_APITABLE[ROM_API_INDEX_PDS_Set_Flash_Pad_Pull_None_Fast])
((BL_Err_Type (*) (uint8_t pinCfg))ROM_APITABLE[ROM_API_INDEX_PDS_Set_Flash_Pad_Pull_None_Fast])
#define RomDriver_PDS_Set_GPIO_Pad_IntClr \
((BL_Err_Type (*) (PDS_GPIO_INT_SET_Type set))ROM_APITABLE[ROM_API_INDEX_PDS_Set_GPIO_Pad_IntClr])
@ -1510,40 +1513,40 @@ typedef enum {
((BL_Sts_Type (*) (PDS_INT_Type intType))ROM_APITABLE[ROM_API_INDEX_PDS_Get_IntStatus])
#define RomDriver_SF_Cfg_Deinit_Ext_Flash_Gpio \
((BL_Err_Type (*) (uint8_t extFlashPin))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Deinit_Ext_Flash_Gpio])
((int (*) (uint8_t extFlashPin))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Deinit_Ext_Flash_Gpio])
#define RomDriver_SF_Cfg_Flash_Init \
((BL_Err_Type (*) (SF_Ctrl_Pin_Select sel, const SF_Ctrl_Cfg_Type *pSfCtrlCfg, const SF_Ctrl_Bank2_Cfg *pBank2Cfg))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Flash_Init])
((int (*) (uint8_t sel, const struct sf_ctrl_cfg_type *pSfCtrlCfg, const struct sf_ctrl_bank2_cfg *pBank2Cfg))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Flash_Init])
#define RomDriver_SF_Cfg_Get_Flash_Cfg_Need_Lock \
((BL_Err_Type (*) (uint32_t flashID, SPI_Flash_Cfg_Type *pFlashCfg))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Get_Flash_Cfg_Need_Lock])
((int (*) (uint32_t flashID, spi_flash_cfg_type *pFlashCfg))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Get_Flash_Cfg_Need_Lock])
#define RomDriver_SF_Cfg_Init_Ext_Flash_Gpio \
((BL_Err_Type (*) (uint8_t extFlashPin))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Init_Ext_Flash_Gpio])
((int (*) (uint8_t extFlashPin))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Init_Ext_Flash_Gpio])
#define RomDriver_SF_Cfg_Init_Flash2_Gpio \
((BL_Err_Type (*) (uint8_t swap))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Init_Flash2_Gpio])
((int (*) (uint8_t swap))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Init_Flash2_Gpio])
#define RomDriver_SF_Cfg_Init_Flash_Gpio \
((BL_Err_Type (*) (SF_Ctrl_Pin_Select flashPinCfg, uint8_t restoreDefault))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Init_Flash_Gpio])
((int (*) (uint8_t flashPinCfg, uint8_t restoreDefault))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Init_Flash_Gpio])
#define RomDriver_SF_Cfg_Sbus2_Flash_Init \
((BL_Err_Type (*) (SF_Ctrl_Pin_Select sel, const SF_Ctrl_Bank2_Cfg *pBank2Cfg))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Sbus2_Flash_Init])
((int (*) (uint8_t sel, const struct sf_ctrl_bank2_cfg *pBank2Cfg))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Sbus2_Flash_Init])
#define RomDriver_SF_Cfg_Flash_Identify \
((uint32_t (*) (uint8_t callFromFlash, uint8_t flashPinCfg, uint8_t restoreDefault, SPI_Flash_Cfg_Type *pFlashCfg, uint8_t group, SF_Ctrl_Bank_Select bank))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Flash_Identify])
((uint32_t (*) (uint8_t callFromFlash, uint8_t flashPinCfg, uint8_t restoreDefault, spi_flash_cfg_type *pFlashCfg, uint8_t group, uint8_t bank))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Flash_Identify])
#define RomDriver_SF_Ctrl_GetBusyState \
((BL_Sts_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_GetBusyState])
((int (*) (void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_GetBusyState])
#define RomDriver_SF_Ctrl_Is_AES_Enable \
((BL_Sts_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Is_AES_Enable])
((int (*) (void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Is_AES_Enable])
#define RomDriver_SF_Ctrl_Is_Sbus2_Enable \
((BL_Sts_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Is_Sbus2_Enable])
((int (*) (void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Is_Sbus2_Enable])
#define RomDriver_SF_Ctrl_Get_Flash_Image_Offset \
((uint32_t (*) (uint8_t group, SF_Ctrl_Bank_Select bank))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Get_Flash_Image_Offset])
((uint32_t (*) (uint8_t group, uint8_t bank))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Get_Flash_Image_Offset])
#define RomDriver_SF_Ctrl_Get_Clock_Delay \
((uint8_t (*) (void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Get_Clock_Delay])
@ -1573,13 +1576,13 @@ typedef enum {
((void (*) (uint8_t region, uint8_t *iv, uint32_t addrOffset))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_IV_BE])
#define RomDriver_SF_Ctrl_AES_Set_Key \
((void (*) (uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_Key])
((void (*) (uint8_t region, uint8_t *key, uint8_t keyType))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_Key])
#define RomDriver_SF_Ctrl_AES_Set_Key_BE \
((void (*) (uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_Key_BE])
((void (*) (uint8_t region, uint8_t *key, uint8_t keyType))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_Key_BE])
#define RomDriver_SF_Ctrl_AES_Set_Mode \
((void (*) (SF_Ctrl_AES_Mode_Type mode))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_Mode])
((void (*) (uint8_t mode))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_Mode])
#define RomDriver_SF_Ctrl_AES_Set_Region \
((void (*) (uint8_t region, uint8_t enable, uint8_t hwKey, uint32_t startAddr, uint32_t endAddr, uint8_t locked))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_Region])
@ -1591,16 +1594,16 @@ typedef enum {
((void (*) (uint8_t region, uint8_t *iv, uint32_t addrOffset))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_XTS_Set_IV_BE])
#define RomDriver_SF_Ctrl_AES_XTS_Set_Key \
((void (*) (uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_XTS_Set_Key])
((void (*) (uint8_t region, uint8_t *key, uint8_t keyType))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_XTS_Set_Key])
#define RomDriver_SF_Ctrl_AES_XTS_Set_Key_BE \
((void (*) (uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_XTS_Set_Key_BE])
((void (*) (uint8_t region, uint8_t *key, uint8_t keyType))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_XTS_Set_Key_BE])
#define RomDriver_SF_Ctrl_Bank2_Enable \
((void (*) (const SF_Ctrl_Bank2_Cfg *bank2Cfg))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Bank2_Enable])
((void (*) (const struct sf_ctrl_bank2_cfg *bank2Cfg))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Bank2_Enable])
#define RomDriver_SF_Ctrl_Cmds_Set \
((void (*) (SF_Ctrl_Cmds_Cfg *cmdsCfg, SF_Ctrl_Bank_Select bank))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Cmds_Set])
((void (*) (struct sf_ctrl_cmds_cfg *cmdsCfg, uint8_t bank))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Cmds_Set])
#define RomDriver_SF_Ctrl_Disable \
((void (*) (void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Disable])
@ -1609,19 +1612,19 @@ typedef enum {
((void (*) (uint8_t disable))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Disable_Wrap_Access])
#define RomDriver_SF_Ctrl_Enable \
((void (*) (const SF_Ctrl_Cfg_Type *cfg))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Enable])
((void (*) (const struct sf_ctrl_cfg_type *cfg))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Enable])
#define RomDriver_SF_Ctrl_Flash2_Read_Icache_Set \
((void (*) (SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Flash2_Read_Icache_Set])
((void (*) (struct sf_ctrl_cmd_cfg_type *cfg, uint8_t cmdValid))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Flash2_Read_Icache_Set])
#define RomDriver_SF_Ctrl_Flash_Read_Icache_Set \
((void (*) (SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Flash_Read_Icache_Set])
((void (*) (struct sf_ctrl_cmd_cfg_type *cfg, uint8_t cmdValid))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Flash_Read_Icache_Set])
#define RomDriver_SF_Ctrl_Lock_Flash_Image_Offset \
((void (*) (uint8_t lock))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Lock_Flash_Image_Offset])
#define RomDriver_SF_Ctrl_Remap_Set \
((void (*) (SF_Ctrl_Remap_Type remap, uint8_t lock))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Remap_Set])
((void (*) (uint8_t remap, uint8_t lock))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Remap_Set])
#define RomDriver_SF_Ctrl_Sbus2_Hold_Sram \
((void (*) (void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Sbus2_Hold_Sram])
@ -1630,7 +1633,7 @@ typedef enum {
((void (*) (void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Sbus2_Release_Sram])
#define RomDriver_SF_Ctrl_Sbus2_Replace \
((void (*) (SF_Ctrl_Pad_Type pad))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Sbus2_Replace])
((void (*) (uint8_t pad))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Sbus2_Replace])
#define RomDriver_SF_Ctrl_Sbus2_Revoke_replace \
((void (*) (void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Sbus2_Revoke_replace])
@ -1639,109 +1642,109 @@ typedef enum {
((void (*) (uint8_t clkDelay, uint8_t rxClkInvert))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Sbus2_Set_Delay])
#define RomDriver_SF_Ctrl_Sbus_Select_Bank \
((void (*) (SF_Ctrl_Bank_Select bank))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Sbus_Select_Bank])
((void (*) (uint8_t bank))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Sbus_Select_Bank])
#define RomDriver_SF_Ctrl_Select_Pad \
((void (*) (SF_Ctrl_Pin_Select sel))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Select_Pad])
((void (*) (uint8_t sel))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Select_Pad])
#define RomDriver_SF_Ctrl_SendCmd \
((void (*) (SF_Ctrl_Cmd_Cfg_Type *cfg))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_SendCmd])
((void (*) (struct sf_ctrl_cmd_cfg_type *cfg))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_SendCmd])
#define RomDriver_SF_Ctrl_Set_Clock_Delay \
((void (*) (uint8_t delay))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Set_Clock_Delay])
#define RomDriver_SF_Ctrl_Set_Flash_Image_Offset \
((void (*) (uint32_t addrOffset, uint8_t group, SF_Ctrl_Bank_Select bank))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Set_Flash_Image_Offset])
((void (*) (uint32_t addrOffset, uint8_t group, uint8_t bank))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Set_Flash_Image_Offset])
#define RomDriver_SF_Ctrl_Set_IO_Delay \
((void (*) (SF_Ctrl_Pad_Type pad, uint8_t doDelay, uint8_t diDelay, uint8_t oeDelay))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Set_IO_Delay])
((void (*) (uint8_t pad, uint8_t doDelay, uint8_t diDelay, uint8_t oeDelay))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Set_IO_Delay])
#define RomDriver_SF_Ctrl_Set_Owner \
((void (*) (SF_Ctrl_Owner_Type owner))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Set_Owner])
((void (*) (uint8_t owner))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Set_Owner])
#define RomDriver_SFlash_Blk32_Erase \
((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum))ROM_APITABLE[ROM_API_INDEX_SFlash_Blk32_Erase])
((int (*) (spi_flash_cfg_type *flashCfg, uint32_t blkNum))ROM_APITABLE[ROM_API_INDEX_SFlash_Blk32_Erase])
#define RomDriver_SFlash_Blk64_Erase \
((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum))ROM_APITABLE[ROM_API_INDEX_SFlash_Blk64_Erase])
((int (*) (spi_flash_cfg_type *flashCfg, uint32_t blkNum))ROM_APITABLE[ROM_API_INDEX_SFlash_Blk64_Erase])
#define RomDriver_SFlash_Chip_Erase \
((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Chip_Erase])
((int (*) (spi_flash_cfg_type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Chip_Erase])
#define RomDriver_SFlash_Erase \
((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg, uint32_t startaddr, uint32_t endaddr))ROM_APITABLE[ROM_API_INDEX_SFlash_Erase])
((int (*) (spi_flash_cfg_type *flashCfg, uint32_t startaddr, uint32_t endaddr))ROM_APITABLE[ROM_API_INDEX_SFlash_Erase])
#define RomDriver_SFlash_Erase_Security_Register \
((BL_Err_Type (*) (SPI_Flash_Cfg_Type *pFlashCfg, SFlash_Sec_Reg_Cfg *pSecRegCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Erase_Security_Register])
((int (*) (spi_flash_cfg_type *pFlashCfg, struct sflash_sec_reg_cfg *pSecRegCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Erase_Security_Register])
#define RomDriver_SFlash_IDbus_Read_Enable \
((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, SF_Ctrl_Bank_Select bank))ROM_APITABLE[ROM_API_INDEX_SFlash_IDbus_Read_Enable])
((int (*) (spi_flash_cfg_type *flashCfg, uint8_t ioMode, uint8_t contRead, uint8_t bank))ROM_APITABLE[ROM_API_INDEX_SFlash_IDbus_Read_Enable])
#define RomDriver_SFlash_Program \
((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *data, uint32_t len))ROM_APITABLE[ROM_API_INDEX_SFlash_Program])
((int (*) (spi_flash_cfg_type *flashCfg, uint8_t ioMode, uint32_t addr, uint8_t *data, uint32_t len))ROM_APITABLE[ROM_API_INDEX_SFlash_Program])
#define RomDriver_SFlash_Program_Security_Register \
((BL_Err_Type (*) (SPI_Flash_Cfg_Type *pFlashCfg, SFlash_Sec_Reg_Cfg *pSecRegCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Program_Security_Register])
((int (*) (spi_flash_cfg_type *pFlashCfg, struct sflash_sec_reg_cfg *pSecRegCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Program_Security_Register])
#define RomDriver_SFlash_Qspi_Disable \
((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Qspi_Disable])
((int (*) (spi_flash_cfg_type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Qspi_Disable])
#define RomDriver_SFlash_Qspi_Enable \
((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Qspi_Enable])
((int (*) (spi_flash_cfg_type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Qspi_Enable])
#define RomDriver_SFlash_RCV_Enable \
((BL_Err_Type (*) (SPI_Flash_Cfg_Type *pFlashCfg, uint8_t rCmd, uint8_t wCmd, uint8_t bitPos))ROM_APITABLE[ROM_API_INDEX_SFlash_RCV_Enable])
((int (*) (spi_flash_cfg_type *pFlashCfg, uint8_t rCmd, uint8_t wCmd, uint8_t bitPos))ROM_APITABLE[ROM_API_INDEX_SFlash_RCV_Enable])
#define RomDriver_SFlash_Read \
((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, uint8_t *data, uint32_t len))ROM_APITABLE[ROM_API_INDEX_SFlash_Read])
((int (*) (spi_flash_cfg_type *flashCfg, uint8_t ioMode, uint8_t contRead, uint32_t addr, uint8_t *data, uint32_t len))ROM_APITABLE[ROM_API_INDEX_SFlash_Read])
#define RomDriver_SFlash_Read_Reg \
((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen))ROM_APITABLE[ROM_API_INDEX_SFlash_Read_Reg])
((int (*) (spi_flash_cfg_type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen))ROM_APITABLE[ROM_API_INDEX_SFlash_Read_Reg])
#define RomDriver_SFlash_Read_Reg_With_Cmd \
((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg, uint8_t readRegCmd, uint8_t *regValue, uint8_t regLen))ROM_APITABLE[ROM_API_INDEX_SFlash_Read_Reg_With_Cmd])
((int (*) (spi_flash_cfg_type *flashCfg, uint8_t readRegCmd, uint8_t *regValue, uint8_t regLen))ROM_APITABLE[ROM_API_INDEX_SFlash_Read_Reg_With_Cmd])
#define RomDriver_SFlash_Read_Security_Register \
((BL_Err_Type (*) (SFlash_Sec_Reg_Cfg *pSecRegCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Read_Security_Register])
((int (*) (struct sflash_sec_reg_cfg *pSecRegCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Read_Security_Register])
#define RomDriver_SFlash_Restore_From_Powerdown \
((BL_Err_Type (*) (SPI_Flash_Cfg_Type *pFlashCfg, uint8_t flashContRead, SF_Ctrl_Bank_Select bank))ROM_APITABLE[ROM_API_INDEX_SFlash_Restore_From_Powerdown])
((int (*) (spi_flash_cfg_type *pFlashCfg, uint8_t flashContRead, uint8_t bank))ROM_APITABLE[ROM_API_INDEX_SFlash_Restore_From_Powerdown])
#define RomDriver_SFlash_Sector_Erase \
((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg, uint32_t secNum))ROM_APITABLE[ROM_API_INDEX_SFlash_Sector_Erase])
((int (*) (spi_flash_cfg_type *flashCfg, uint32_t secNum))ROM_APITABLE[ROM_API_INDEX_SFlash_Sector_Erase])
#define RomDriver_SFlash_Set32BitsAddrMode \
((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg, BL_Fun_Type en32BitsAddr))ROM_APITABLE[ROM_API_INDEX_SFlash_Set32BitsAddrMode])
((int (*) (spi_flash_cfg_type *flashCfg, uint8_t en32BitsAddr))ROM_APITABLE[ROM_API_INDEX_SFlash_Set32BitsAddrMode])
#define RomDriver_SFlash_SetSPIMode \
((BL_Err_Type (*) (SF_Ctrl_Mode_Type mode))ROM_APITABLE[ROM_API_INDEX_SFlash_SetSPIMode])
((int (*) (uint8_t mode))ROM_APITABLE[ROM_API_INDEX_SFlash_SetSPIMode])
#define RomDriver_SFlash_Set_IDbus_Cfg \
((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, uint32_t len, SF_Ctrl_Bank_Select bank))ROM_APITABLE[ROM_API_INDEX_SFlash_Set_IDbus_Cfg])
((int (*) (spi_flash_cfg_type *flashCfg, uint8_t ioMode, uint8_t contRead, uint32_t addr, uint32_t len, uint8_t bank))ROM_APITABLE[ROM_API_INDEX_SFlash_Set_IDbus_Cfg])
#define RomDriver_SFlash_Software_Reset \
((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Software_Reset])
((int (*) (spi_flash_cfg_type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Software_Reset])
#define RomDriver_SFlash_Write_Enable \
((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Write_Enable])
((int (*) (spi_flash_cfg_type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Write_Enable])
#define RomDriver_SFlash_Write_Reg \
((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen))ROM_APITABLE[ROM_API_INDEX_SFlash_Write_Reg])
((int (*) (spi_flash_cfg_type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen))ROM_APITABLE[ROM_API_INDEX_SFlash_Write_Reg])
#define RomDriver_SFlash_Write_Reg_With_Cmd \
((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg, uint8_t writeRegCmd, uint8_t *regValue, uint8_t regLen))ROM_APITABLE[ROM_API_INDEX_SFlash_Write_Reg_With_Cmd])
((int (*) (spi_flash_cfg_type *flashCfg, uint8_t writeRegCmd, uint8_t *regValue, uint8_t regLen))ROM_APITABLE[ROM_API_INDEX_SFlash_Write_Reg_With_Cmd])
#define RomDriver_SFlash_Busy \
((BL_Sts_Type (*) (SPI_Flash_Cfg_Type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Busy])
((int (*) (spi_flash_cfg_type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Busy])
#define RomDriver_SFlash_DisableBurstWrap \
((void (*) (SPI_Flash_Cfg_Type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_DisableBurstWrap])
((void (*) (spi_flash_cfg_type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_DisableBurstWrap])
#define RomDriver_SFlash_GetDeviceId \
((void (*) (uint8_t *data, BL_Fun_Type is32BitsAddr))ROM_APITABLE[ROM_API_INDEX_SFlash_GetDeviceId])
((void (*) (uint8_t *data, uint8_t is32BitsAddr))ROM_APITABLE[ROM_API_INDEX_SFlash_GetDeviceId])
#define RomDriver_SFlash_GetJedecId \
((void (*) (SPI_Flash_Cfg_Type *flashCfg, uint8_t *data))ROM_APITABLE[ROM_API_INDEX_SFlash_GetJedecId])
((void (*) (spi_flash_cfg_type *flashCfg, uint8_t *data))ROM_APITABLE[ROM_API_INDEX_SFlash_GetJedecId])
#define RomDriver_SFlash_GetUniqueId \
((void (*) (uint8_t *data, uint8_t idLen))ROM_APITABLE[ROM_API_INDEX_SFlash_GetUniqueId])
@ -1750,22 +1753,22 @@ typedef enum {
((void (*) (void))ROM_APITABLE[ROM_API_INDEX_SFlash_IDbus_Read_Disable])
#define RomDriver_SFlash_Init \
((void (*) (const SF_Ctrl_Cfg_Type *pSfCtrlCfg, const SF_Ctrl_Bank2_Cfg *pBank2Cfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Init])
((void (*) (const struct sf_ctrl_cfg_type *pSfCtrlCfg, const struct sf_ctrl_bank2_cfg *pBank2Cfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Init])
#define RomDriver_SFlash_Powerdown \
((void (*) (void))ROM_APITABLE[ROM_API_INDEX_SFlash_Powerdown])
#define RomDriver_SFlash_Release_Powerdown \
((void (*) (SPI_Flash_Cfg_Type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Release_Powerdown])
((void (*) (spi_flash_cfg_type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Release_Powerdown])
#define RomDriver_SFlash_Reset_Continue_Read \
((void (*) (SPI_Flash_Cfg_Type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Reset_Continue_Read])
((void (*) (spi_flash_cfg_type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Reset_Continue_Read])
#define RomDriver_SFlash_SetBurstWrap \
((void (*) (SPI_Flash_Cfg_Type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_SetBurstWrap])
((void (*) (spi_flash_cfg_type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_SetBurstWrap])
#define RomDriver_SFlash_Volatile_Reg_Write_Enable \
((void (*) (SPI_Flash_Cfg_Type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Volatile_Reg_Write_Enable])
((void (*) (spi_flash_cfg_type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Volatile_Reg_Write_Enable])
#define RomDriver_UART_AutoBaudDetection \
((BL_Err_Type (*) (UART_ID_Type uartId, BL_Fun_Type autoBaud))ROM_APITABLE[ROM_API_INDEX_UART_AutoBaudDetection])
@ -1876,31 +1879,31 @@ typedef enum {
((uint8_t (*) (UART_ID_Type uartId))ROM_APITABLE[ROM_API_INDEX_UART_GetTxFifoCount])
#define RomDriver_XIP_SFlash_Erase_Need_Lock \
((BL_Err_Type (*) (SPI_Flash_Cfg_Type *pFlashCfg, uint32_t startaddr, int len, uint8_t group, SF_Ctrl_Bank_Select bank))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Erase_Need_Lock])
((BL_Err_Type (*) (spi_flash_cfg_type *pFlashCfg, uint32_t startaddr, int len, uint8_t group, uint8_t bank))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Erase_Need_Lock])
#define RomDriver_XIP_SFlash_GetDeviceId_Need_Lock \
((BL_Err_Type (*) (SPI_Flash_Cfg_Type *pFlashCfg, BL_Fun_Type is32BitsAddr, uint8_t *data, uint8_t group, SF_Ctrl_Bank_Select bank))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_GetDeviceId_Need_Lock])
((BL_Err_Type (*) (spi_flash_cfg_type *pFlashCfg, BL_Fun_Type is32BitsAddr, uint8_t *data, uint8_t group, uint8_t bank))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_GetDeviceId_Need_Lock])
#define RomDriver_XIP_SFlash_GetJedecId_Need_Lock \
((BL_Err_Type (*) (SPI_Flash_Cfg_Type *pFlashCfg, uint8_t *data, uint8_t group, SF_Ctrl_Bank_Select bank))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_GetJedecId_Need_Lock])
((BL_Err_Type (*) (spi_flash_cfg_type *pFlashCfg, uint8_t *data, uint8_t group, uint8_t bank))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_GetJedecId_Need_Lock])
#define RomDriver_XIP_SFlash_GetUniqueId_Need_Lock \
((BL_Err_Type (*) (SPI_Flash_Cfg_Type *pFlashCfg, uint8_t *data, uint8_t idLen, uint8_t group, SF_Ctrl_Bank_Select bank))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_GetUniqueId_Need_Lock])
((BL_Err_Type (*) (spi_flash_cfg_type *pFlashCfg, uint8_t *data, uint8_t idLen, uint8_t group, uint8_t bank))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_GetUniqueId_Need_Lock])
#define RomDriver_XIP_SFlash_Read_Need_Lock \
((BL_Err_Type (*) (SPI_Flash_Cfg_Type *pFlashCfg, uint32_t addr, uint8_t *data, uint32_t len, uint8_t group, SF_Ctrl_Bank_Select bank))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Read_Need_Lock])
((BL_Err_Type (*) (spi_flash_cfg_type *pFlashCfg, uint32_t addr, uint8_t *data, uint32_t len, uint8_t group, uint8_t bank))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Read_Need_Lock])
#define RomDriver_XIP_SFlash_Read_Via_Cache_Need_Lock \
((BL_Err_Type (*) (uint32_t addr, uint8_t *data, uint32_t len))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Read_Via_Cache_Need_Lock])
#define RomDriver_XIP_SFlash_State_Restore \
((BL_Err_Type (*) (SPI_Flash_Cfg_Type *pFlashCfg, uint32_t offset, uint8_t group, SF_Ctrl_Bank_Select bank))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_State_Restore])
((BL_Err_Type (*) (spi_flash_cfg_type *pFlashCfg, uint32_t offset, uint8_t group, uint8_t bank))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_State_Restore])
#define RomDriver_XIP_SFlash_State_Save \
((BL_Err_Type (*) (SPI_Flash_Cfg_Type *pFlashCfg, uint32_t *offset, uint8_t group, SF_Ctrl_Bank_Select bank))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_State_Save])
((BL_Err_Type (*) (spi_flash_cfg_type *pFlashCfg, uint32_t *offset, uint8_t group, uint8_t bank))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_State_Save])
#define RomDriver_XIP_SFlash_Write_Need_Lock \
((BL_Err_Type (*) (SPI_Flash_Cfg_Type *pFlashCfg, uint32_t addr, uint8_t *data, uint32_t len, uint8_t group, SF_Ctrl_Bank_Select bank))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Write_Need_Lock])
((BL_Err_Type (*) (spi_flash_cfg_type *pFlashCfg, uint32_t addr, uint8_t *data, uint32_t len, uint8_t group, uint8_t bank))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Write_Need_Lock])
#define RomDriver_XIP_SFlash_Opt_Enter \
((void (*) (uint8_t *aesEnable))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Opt_Enter])

115
drivers/soc/bl616/std/include/bl616_sf_cfg.h
View file

@ -1,115 +0,0 @@
/**
******************************************************************************
* @file bl616_sf_cfg.h
* @version V1.0
* @date
* @brief This file is the standard driver header file
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __BL616_SF_CFG_H__
#define __BL616_SF_CFG_H__
#include "string.h"
#include "bl616_glb.h"
#include "bl616_glb_gpio.h"
#include "bl616_sflash.h"
#include "bl616_sf_ctrl.h"
/** @addtogroup BL616_Peripheral_Driver
* @{
*/
/** @addtogroup SF_CFG
* @{
*/
/** @defgroup SF_CFG_Public_Types
* @{
*/
/*@} end of group SF_CFG_Public_Types */
/** @defgroup SF_CFG_Public_Constants
* @{
*/
/*@} end of group SF_CFG_Public_Constants */
/** @defgroup SF_CFG_Public_Macros
* @{
*/
/* Flash option sf2 */
/* Flash CLK */
#define BFLB_EXTFLASH_CLK0_GPIO GLB_GPIO_PIN_8
/* FLASH CS */
#define BFLB_EXTFLASH_CS0_GPIO GLB_GPIO_PIN_4
/* FLASH DATA */
#define BFLB_EXTFLASH_DATA00_GPIO GLB_GPIO_PIN_7
#define BFLB_EXTFLASH_DATA10_GPIO GLB_GPIO_PIN_5
#define BFLB_EXTFLASH_DATA20_GPIO GLB_GPIO_PIN_6
#define BFLB_EXTFLASH_DATA30_GPIO GLB_GPIO_PIN_9
/* Flash option sf3 */
/* Flash CLK */
#define BFLB_EXTFLASH_CLK1_GPIO GLB_GPIO_PIN_11
/* FLASH CS */
#define BFLB_EXTFLASH_CS1_GPIO GLB_GPIO_PIN_15
/* FLASH DATA */
#define BFLB_EXTFLASH_DATA01_GPIO GLB_GPIO_PIN_12
#define BFLB_EXTFLASH_DATA11_GPIO GLB_GPIO_PIN_14
#define BFLB_EXTFLASH_DATA21_GPIO GLB_GPIO_PIN_13
#define BFLB_EXTFLASH_DATA31_GPIO GLB_GPIO_PIN_10
#define BFLB_FLASH_ID_VALID_FLAG 0x80000000
#define BFLB_FLASH_ID_VALID_MASK 0x7FFFFFFF
/*@} end of group SF_CFG_Public_Macros */
/** @defgroup SF_CFG_Public_Functions
* @{
*/
BL_Err_Type SF_Cfg_Get_Flash_Cfg_Need_Lock(uint32_t flashID, SPI_Flash_Cfg_Type *pFlashCfg);
BL_Err_Type SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(uint32_t flashID, SPI_Flash_Cfg_Type *pFlashCfg);
BL_Err_Type SF_Cfg_Init_Flash_Gpio(SF_Ctrl_Pin_Select flashPinCfg, uint8_t restoreDefault);
BL_Err_Type SF_Cfg_Init_Flash2_Gpio(uint8_t swap);
BL_Err_Type SF_Cfg_Init_Ext_Flash_Gpio(uint8_t extFlashPin);
BL_Err_Type SF_Cfg_Deinit_Ext_Flash_Gpio(uint8_t extFlashPin);
uint32_t SF_Cfg_Flash_Identify(uint8_t callFromFlash, uint8_t flashPinCfg, uint8_t restoreDefault,
SPI_Flash_Cfg_Type *pFlashCfg, uint8_t group, SF_Ctrl_Bank_Select bank);
uint32_t SF_Cfg_Flash_Identify_Ext(uint8_t callFromFlash, uint8_t flashPinCfg, uint8_t restoreDefault,
SPI_Flash_Cfg_Type *pFlashCfg, uint8_t group, SF_Ctrl_Bank_Select bank);
BL_Err_Type SF_Cfg_Flash_Init(SF_Ctrl_Pin_Select sel, const SF_Ctrl_Cfg_Type *pSfCtrlCfg, const SF_Ctrl_Bank2_Cfg *pBank2Cfg);
BL_Err_Type SF_Cfg_Sbus2_Flash_Init(SF_Ctrl_Pin_Select sel, const SF_Ctrl_Bank2_Cfg *pBank2Cfg);
/*@} end of group SF_CFG_Public_Functions */
/*@} end of group SF_CFG */
/*@} end of group BL616_Peripheral_Driver */
#endif /* __BL616_SF_CFG_H__ */

483
drivers/soc/bl616/std/include/bl616_sf_ctrl.h
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@ -1,483 +0,0 @@
/**
******************************************************************************
* @file bl616_sf_ctrl.h
* @version V1.0
* @date
* @brief This file is the standard driver header file
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __BL616_SF_CTRL_H__
#define __BL616_SF_CTRL_H__
#include "sf_ctrl_reg.h"
#include "bl616_common.h"
/** @addtogroup BL616_Peripheral_Driver
* @{
*/
/** @addtogroup SF_CTRL
* @{
*/
/** @defgroup SF_CTRL_Public_Types
* @{
*/
/**
* @brief Serial flash pad type definition
*/
typedef enum {
SF_CTRL_PAD1, /*!< SF Ctrl pad 1 */
SF_CTRL_PAD2, /*!< SF Ctrl pad 2 */
SF_CTRL_PAD3, /*!< SF Ctrl pad 3 */
} SF_Ctrl_Pad_Type;
/**
* @brief Serial flash config pin select type definition
*/
typedef enum {
SF_IO_EMB_SWAP_IO3IO0 = 0x0, /*!< SF select embedded flash swap io3 with io0 */
SF_IO_EMB_SWAP_IO3IO0_IO2CS = 0x1, /*!< SF select embedded flash swap io3 with io0 and io2 with cs */
SF_IO_EMB_SWAP_NONE = 0x2, /*!< SF select embedded flash no swap */
SF_IO_EMB_SWAP_IO2CS = 0x3, /*!< SF select embedded flash swap io2 with cs */
SF_IO_EXT_SF2_SWAP_IO3IO0 = 0x4, /*!< SF select external flash SF2 use gpio4-9 and SF2 swap io3 with io0 */
SF_IO_EXT_SF3 = 0x8, /*!< SF select external flash SF3 use gpio10-15 */
SF_IO_EMB_SWAP_IO3IO0_AND_SF2_SWAP_IO3IO0 = 0x14, /*!< SF select embedded flash swap io3 with io0 and SF2 swap io3 with io0*/
SF_IO_EMB_SWAP_IO3IO0_IO2CS_AND_SF2_SWAP_IO3IO0 = 0x15, /*!< SF select embedded flash swap io3 with io0、io2 with cs and SF2 swap io3 with io0 */
SF_IO_EMB_SWAP_NONE_AND_SF2_SWAP_IO3IO0 = 0x16, /*!< SF select embedded flash no swap and SF2 swap io3 with io0 */
SF_IO_EMB_SWAP_IO2CS_AND_SF2_SWAP_IO3IO0 = 0x17, /*!< SF select embedded flash swap io2 with cs, and SF2 swap io3 with io0 */
SF_IO_EXT_SF2 = 0x24, /*!< SF select external flash SF2 use gpio4-9 */
SF_IO_EMB_SWAP_IO3IO0_AND_SF2 = 0x34, /*!< SF select embedded flash swap io3 with io0 and SF2 use gpio4-9 */
SF_IO_EMB_SWAP_IO3IO0_IO2CS_AND_SF2 = 0x35, /*!< SF select embedded flash swap io3 with io0、io2 with cs and SF2 use gpio4-9 */
SF_IO_EMB_SWAP_NONE_AND_SF2 = 0x36, /*!< SF select embedded flash no swap and SF2 use gpio4-9 */
SF_IO_EMB_SWAP_IO2CS_AND_SF2 = 0x37, /*!< SF select embedded flash swap io2 with cs and SF2 use gpio4-9 */
} SF_Ctrl_Pin_Select;
/**
* @brief Serial flash select bank control type definition
*/
typedef enum {
SF_CTRL_FLASH_BANK0, /*!< SF Ctrl select flash bank0 */
SF_CTRL_FLASH_BANK1, /*!< SF Ctrl select flash bank1 */
} SF_Ctrl_Bank_Select;
/**
* @brief Serial flash controller wrap mode type definition
*/
typedef enum {
SF_CTRL_WRAP_MODE_0, /*!< Cmds bypass wrap commands to macro, original mode */
SF_CTRL_WRAP_MODE_1, /*!< Cmds handle wrap commands, original mode */
SF_CTRL_WRAP_MODE_2, /*!< Cmds bypass wrap commands to macro, cmds force wrap16*4 splitted into two wrap8*4 */
SF_CTRL_WRAP_MODE_3, /*!< Cmds handle wrap commands, cmds force wrap16*4 splitted into two wrap8*4 */
} SF_Ctrl_Wrap_Mode;
/**
* @brief Serail flash controller wrap mode len type definition
*/
typedef enum {
SF_CTRL_WRAP_LEN_8, /*!< SF Ctrl wrap length: 8 */
SF_CTRL_WRAP_LEN_16, /*!< SF Ctrl wrap length: 16 */
SF_CTRL_WRAP_LEN_32, /*!< SF Ctrl wrap length: 32 */
SF_CTRL_WRAP_LEN_64, /*!< SF Ctrl wrap length: 64 */
SF_CTRL_WRAP_LEN_128, /*!< SF Ctrl wrap length: 128 */
SF_CTRL_WRAP_LEN_256, /*!< SF Ctrl wrap length: 256 */
SF_CTRL_WRAP_LEN_512, /*!< SF Ctrl wrap length: 512 */
SF_CTRL_WRAP_LEN_1024, /*!< SF Ctrl wrap length: 1024 */
SF_CTRL_WRAP_LEN_2048, /*!< SF Ctrl wrap length: 2048 */
SF_CTRL_WRAP_LEN_4096, /*!< SF Ctrl wrap length: 4096 */
} SF_Ctrl_Wrap_Len_Type;
/**
* @brief Serail flash controller memory remap type define
*/
typedef enum {
SF_CTRL_ORIGINAL_MEMORY_MAP, /*!< Remap none, use two addr map when use dual flash */
SF_CTRL_REMAP_16MB, /*!< Remap HADDR>16MB region to psram port HADDR[24] -> HADDR[28] */
SF_CTRL_REMAP_8MB, /*!< Remap HADDR>8MB region to psram port HADDR[23] -> HADDR[28] */
SF_CTRL_REMAP_4MB, /*!< Remap HADDR>4MB region to psram port HADDR[22] -> HADDR[28] */
} SF_Ctrl_Remap_Type;
/**
* @brief Serial flash controller owner type definition
*/
typedef enum {
SF_CTRL_OWNER_SAHB, /*!< System AHB bus control serial flash controller */
SF_CTRL_OWNER_IAHB, /*!< I-Code AHB bus control serial flash controller */
} SF_Ctrl_Owner_Type;
/**
* @brief Read and write type definition
*/
typedef enum {
SF_CTRL_READ, /*!< Serail flash read command flag */
SF_CTRL_WRITE, /*!< Serail flash write command flag */
} SF_Ctrl_RW_Type;
/**
* @brief Serail flash interface IO type definition
*/
typedef enum {
SF_CTRL_NIO_MODE, /*!< Normal IO mode define */
SF_CTRL_DO_MODE, /*!< Dual Output mode define */
SF_CTRL_QO_MODE, /*!< Quad Output mode define */
SF_CTRL_DIO_MODE, /*!< Dual IO mode define */
SF_CTRL_QIO_MODE, /*!< Quad IO mode define */
} SF_Ctrl_IO_Type;
/**
* @brief Serail flash controller interface mode type definition
*/
typedef enum {
SF_CTRL_SPI_MODE, /*!< SPI mode define */
SF_CTRL_QPI_MODE, /*!< QPI mode define */
} SF_Ctrl_Mode_Type;
/**
* @brief Serail flash controller command mode type definition
*/
typedef enum {
SF_CTRL_CMD_1_LINE, /*!< Command in one line mode */
SF_CTRL_CMD_4_LINES, /*!< Command in four lines mode */
} SF_Ctrl_Cmd_Mode_Type;
/**
* @brief Serail flash controller address mode type definition
*/
typedef enum {
SF_CTRL_ADDR_1_LINE, /*!< Address in one line mode */
SF_CTRL_ADDR_2_LINES, /*!< Address in two lines mode */
SF_CTRL_ADDR_4_LINES, /*!< Address in four lines mode */
} SF_Ctrl_Addr_Mode_Type;
/**
* @brief Serail flash controller dummy mode type definition
*/
typedef enum {
SF_CTRL_DUMMY_1_LINE, /*!< Dummy in one line mode */
SF_CTRL_DUMMY_2_LINES, /*!< Dummy in two lines mode */
SF_CTRL_DUMMY_4_LINES, /*!< Dummy in four lines mode */
} SF_Ctrl_Dmy_Mode_Type;
/**
* @brief Serail flash controller data mode type definition
*/
typedef enum {
SF_CTRL_DATA_1_LINE, /*!< Data in one line mode */
SF_CTRL_DATA_2_LINES, /*!< Data in two lines mode */
SF_CTRL_DATA_4_LINES, /*!< Data in four lines mode */
} SF_Ctrl_Data_Mode_Type;
/**
* @brief Serail flash controller AES mode type definition
*/
typedef enum {
SF_CTRL_AES_CTR_MODE, /*!< Serail flash AES CTR mode */
SF_CTRL_AES_XTS_MODE, /*!< Serail flash AES XTS mode */
} SF_Ctrl_AES_Mode_Type;
/**
* @brief Serail flash controller AES key len type definition
*/
typedef enum {
SF_CTRL_AES_128BITS, /*!< Serail flash AES key 128 bits length */
SF_CTRL_AES_256BITS, /*!< Serail flash AES key 256 bits length */
SF_CTRL_AES_192BITS, /*!< Serail flash AES key 192 bits length */
SF_CTRL_AES_128BITS_DOUBLE_KEY, /*!< Serail flash AES key 128 bits length double key */
} SF_Ctrl_AES_Key_Type;
/**
* @brief Serail flash controller configuration structure type definition
*/
typedef struct
{
SF_Ctrl_Owner_Type owner; /*!< Sflash interface bus owner */
BL_Fun_Type en32bAddr; /*!< Sflash enable 32-bits address */
uint8_t clkDelay; /*!< Clock count for read due to pad delay */
uint8_t clkInvert; /*!< Clock invert */
uint8_t rxClkInvert; /*!< RX clock invert */
uint8_t doDelay; /*!< Data out delay */
uint8_t diDelay; /*!< Data in delay */
uint8_t oeDelay; /*!< Output enable delay */
} SF_Ctrl_Cfg_Type;
/**
* @brief SF Ctrl bank2 controller configuration structure type definition
*/
typedef struct
{
BL_Fun_Type sbus2Select; /*!< Select sbus2 as 2nd flash controller */
BL_Fun_Type bank2RxClkInvertSrc; /*!< Select bank2 rx clock invert source */
BL_Fun_Type bank2RxClkInvertSel; /*!< Select inveted bank2 rx clock */
BL_Fun_Type bank2DelaySrc; /*!< Select bank2 read delay source */
uint8_t bank2ClkDelay; /*!< Bank2 read delay cycle = n + 1 */
uint8_t doDelay; /*!< Data out delay */
uint8_t diDelay; /*!< Data in delay */
uint8_t oeDelay; /*!< Output enable delay */
SF_Ctrl_Remap_Type remap; /*!< Select dual flash memory remap set */
uint8_t remapLock; /*!< Select memory remap lock */
} SF_Ctrl_Bank2_Cfg;
/**
* @brief SF Ctrl cmds configuration structure type definition
*/
typedef struct
{
uint8_t ackLatency; /*!< SF Ctrl ack latency cycles */
BL_Fun_Type cmdsCoreEn; /*!< SF Ctrl cmds core enable */
BL_Fun_Type cmdsEn; /*!< SF Ctrl cmds enable */
SF_Ctrl_Wrap_Mode cmdsWrapMode; /*!< SF Ctrl cmds wrap mode */
SF_Ctrl_Wrap_Len_Type cmdsWrapLen; /*!< SF Ctrl cmds wrap length */
} SF_Ctrl_Cmds_Cfg;
/**
* @brief Serail flash command configuration structure type definition
*/
typedef struct
{
uint8_t rwFlag; /*!< Read write flag */
SF_Ctrl_Cmd_Mode_Type cmdMode; /*!< Command mode */
SF_Ctrl_Addr_Mode_Type addrMode; /*!< Address mode */
uint8_t addrSize; /*!< Address size */
uint8_t dummyClks; /*!< Dummy clocks */
SF_Ctrl_Dmy_Mode_Type dummyMode; /*!< Dummy mode */
SF_Ctrl_Data_Mode_Type dataMode; /*!< Data mode */
uint8_t rsv[1]; /*!< */
uint32_t nbData; /*!< Transfer number of bytes */
uint32_t cmdBuf[2]; /*!< Command buffer */
} SF_Ctrl_Cmd_Cfg_Type;
/*@} end of group SF_CTRL_Public_Types */
/** @defgroup SF_CTRL_Public_Constants
* @{
*/
/** @defgroup SF_CTRL_PAD_TYPE
* @{
*/
#define IS_SF_CTRL_PAD_TYPE(type) (((type) == SF_CTRL_PAD1) || \
((type) == SF_CTRL_PAD2) || \
((type) == SF_CTRL_PAD3))
/** @defgroup SF_CTRL_PIN_SELECT
* @{
*/
#define IS_SF_CTRL_PIN_SELECT(type) (((type) == SF_IO_EMB_SWAP_IO3IO0) || \
((type) == SF_IO_EMB_SWAP_IO3IO0_IO2CS) || \
((type) == SF_IO_EMB_SWAP_NONE) || \
((type) == SF_IO_EMB_SWAP_IO2CS) || \
((type) == SF_IO_EXT_SF2_SWAP_IO3IO0) || \
((type) == SF_IO_EXT_SF3) || \
((type) == SF_IO_EMB_SWAP_IO3IO0_AND_SF2_SWAP_IO3IO0) || \
((type) == SF_IO_EMB_SWAP_IO3IO0_IO2CS_AND_SF2_SWAP_IO3IO0) || \
((type) == SF_IO_EMB_SWAP_NONE_AND_SF2_SWAP_IO3IO0) || \
((type) == SF_IO_EMB_SWAP_IO2CS_AND_SF2_SWAP_IO3IO0) || \
((type) == SF_IO_EXT_SF2) || \
((type) == SF_IO_EMB_SWAP_IO3IO0_AND_SF2) || \
((type) == SF_IO_EMB_SWAP_IO3IO0_IO2CS_AND_SF2) || \
((type) == SF_IO_EMB_SWAP_NONE_AND_SF2) || \
((type) == SF_IO_EMB_SWAP_IO2CS_AND_SF2))
/** @defgroup SF_CTRL_BANK_SELECT
* @{
*/
#define IS_SF_CTRL_BANK_SELECT(type) (((type) == SF_CTRL_FLASH_BANK0) || \
((type) == SF_CTRL_FLASH_BANK1))
/** @defgroup SF_CTRL_WRAP_MODE
* @{
*/
#define IS_SF_CTRL_WRAP_MODE(type) (((type) == SF_CTRL_WRAP_MODE_0) || \
((type) == SF_CTRL_WRAP_MODE_1) || \
((type) == SF_CTRL_WRAP_MODE_2) || \
((type) == SF_CTRL_WRAP_MODE_3))
/** @defgroup SF_CTRL_WRAP_LEN_TYPE
* @{
*/
#define IS_SF_CTRL_WRAP_LEN_TYPE(type) (((type) == SF_CTRL_WRAP_LEN_8) || \
((type) == SF_CTRL_WRAP_LEN_16) || \
((type) == SF_CTRL_WRAP_LEN_32) || \
((type) == SF_CTRL_WRAP_LEN_64) || \
((type) == SF_CTRL_WRAP_LEN_128) || \
((type) == SF_CTRL_WRAP_LEN_256) || \
((type) == SF_CTRL_WRAP_LEN_512) || \
((type) == SF_CTRL_WRAP_LEN_1024) || \
((type) == SF_CTRL_WRAP_LEN_2048) || \
((type) == SF_CTRL_WRAP_LEN_4096))
/** @defgroup SF_CTRL_REMAP_TYPE
* @{
*/
#define IS_SF_CTRL_REMAP_TYPE(type) (((type) == SF_CTRL_ORIGINAL_MEMORY_MAP) || \
((type) == SF_CTRL_REMAP_16MB) || \
((type) == SF_CTRL_REMAP_8MB) || \
((type) == SF_CTRL_REMAP_4MB))
/** @defgroup SF_CTRL_OWNER_TYPE
* @{
*/
#define IS_SF_CTRL_OWNER_TYPE(type) (((type) == SF_CTRL_OWNER_SAHB) || \
((type) == SF_CTRL_OWNER_IAHB))
/** @defgroup SF_CTRL_RW_TYPE
* @{
*/
#define IS_SF_CTRL_RW_TYPE(type) (((type) == SF_CTRL_READ) || \
((type) == SF_CTRL_WRITE))
/** @defgroup SF_CTRL_IO_TYPE
* @{
*/
#define IS_SF_CTRL_IO_TYPE(type) (((type) == SF_CTRL_NIO_MODE) || \
((type) == SF_CTRL_DO_MODE) || \
((type) == SF_CTRL_QO_MODE) || \
((type) == SF_CTRL_DIO_MODE) || \
((type) == SF_CTRL_QIO_MODE))
/** @defgroup SF_CTRL_MODE_TYPE
* @{
*/
#define IS_SF_CTRL_MODE_TYPE(type) (((type) == SF_CTRL_SPI_MODE) || \
((type) == SF_CTRL_QPI_MODE))
/** @defgroup SF_CTRL_CMD_MODE_TYPE
* @{
*/
#define IS_SF_CTRL_CMD_MODE_TYPE(type) (((type) == SF_CTRL_CMD_1_LINE) || \
((type) == SF_CTRL_CMD_4_LINES))
/** @defgroup SF_CTRL_ADDR_MODE_TYPE
* @{
*/
#define IS_SF_CTRL_ADDR_MODE_TYPE(type) (((type) == SF_CTRL_ADDR_1_LINE) || \
((type) == SF_CTRL_ADDR_2_LINES) || \
((type) == SF_CTRL_ADDR_4_LINES))
/** @defgroup SF_CTRL_DMY_MODE_TYPE
* @{
*/
#define IS_SF_CTRL_DMY_MODE_TYPE(type) (((type) == SF_CTRL_DUMMY_1_LINE) || \
((type) == SF_CTRL_DUMMY_2_LINES) || \
((type) == SF_CTRL_DUMMY_4_LINES))
/** @defgroup SF_CTRL_DATA_MODE_TYPE
* @{
*/
#define IS_SF_CTRL_DATA_MODE_TYPE(type) (((type) == SF_CTRL_DATA_1_LINE) || \
((type) == SF_CTRL_DATA_2_LINES) || \
((type) == SF_CTRL_DATA_4_LINES))
/** @defgroup SF_CTRL_AES_MODE_TYPE
* @{
*/
#define IS_SF_CTRL_AES_MODE_TYPE(type) (((type) == SF_CTRL_AES_CTR_MODE) || \
((type) == SF_CTRL_AES_XTS_MODE))
/** @defgroup SF_CTRL_AES_KEY_TYPE
* @{
*/
#define IS_SF_CTRL_AES_KEY_TYPE(type) (((type) == SF_CTRL_AES_128BITS) || \
((type) == SF_CTRL_AES_256BITS) || \
((type) == SF_CTRL_AES_192BITS) || \
((type) == SF_CTRL_AES_128BITS_DOUBLE_KEY))
/*@} end of group SF_CTRL_Public_Constants */
/** @defgroup SF_CTRL_Public_Macros
* @{
*/
#define SF_CTRL_NO_ADDRESS 0xFFFFFFFF
#define NOR_FLASH_CTRL_BUF_SIZE 256
#define NAND_FLASH_CTRL_BUF_SIZE 512
/*@} end of group SF_CTRL_Public_Macros */
/** @defgroup SF_CTRL_Public_Functions
* @{
*/
#ifndef BFLB_USE_HAL_DRIVER
void SF_Ctrl_IRQHandler(void);
#endif
void SF_Ctrl_Enable(const SF_Ctrl_Cfg_Type *cfg);
void SF_Ctrl_Bank2_Enable(const SF_Ctrl_Bank2_Cfg *bank2Cfg);
void SF_Ctrl_Set_IO_Delay(SF_Ctrl_Pad_Type pad, uint8_t doDelay, uint8_t diDelay, uint8_t oeDelay);
void SF_Ctrl_Sbus2_Hold_Sram(void);
void SF_Ctrl_Sbus2_Release_Sram(void);
BL_Sts_Type SF_Ctrl_Is_Sbus2_Enable(void);
void SF_Ctrl_Sbus2_Replace(SF_Ctrl_Pad_Type pad);
void SF_Ctrl_Sbus2_Revoke_replace(void);
void SF_Ctrl_Sbus2_Set_Delay(uint8_t clkDelay, uint8_t rxClkInvert);
void SF_Ctrl_32bits_Addr_En(BL_Fun_Type en32BitsAddr);
uint8_t SF_Ctrl_Get_Clock_Delay(void);
void SF_Ctrl_Set_Clock_Delay(uint8_t delay);
uint8_t SF_Ctrl_Get_Wrap_Queue_Value(void);
void SF_Ctrl_Cmds_Set(SF_Ctrl_Cmds_Cfg *cmdsCfg, SF_Ctrl_Bank_Select bank);
void SF_Ctrl_Remap_Set(SF_Ctrl_Remap_Type remap, uint8_t lock);
void SF_Ctrl_Select_Pad(SF_Ctrl_Pin_Select sel);
void SF_Ctrl_Sbus_Select_Bank(SF_Ctrl_Bank_Select bank);
void SF_Ctrl_Set_Owner(SF_Ctrl_Owner_Type owner);
void SF_Ctrl_Disable(void);
void SF_Ctrl_AES_Enable_BE(void);
void SF_Ctrl_AES_Enable_LE(void);
void SF_Ctrl_AES_Set_Region(uint8_t region, uint8_t enable, uint8_t hwKey, uint32_t startAddr, uint32_t endAddr,
uint8_t locked);
void SF_Ctrl_AES_Set_Key(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType);
void SF_Ctrl_AES_Set_Key_BE(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType);
void SF_Ctrl_AES_XTS_Set_Key(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType);
void SF_Ctrl_AES_Set_Key_BE(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType);
void SF_Ctrl_AES_XTS_Set_Key(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType);
void SF_Ctrl_AES_XTS_Set_Key_BE(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType);
void SF_Ctrl_AES_Set_IV(uint8_t region, uint8_t *iv, uint32_t addrOffset);
void SF_Ctrl_AES_XTS_Set_IV(uint8_t region, uint8_t *iv, uint32_t addrOffset);
void SF_Ctrl_AES_Set_IV_BE(uint8_t region, uint8_t *iv, uint32_t addrOffset);
void SF_Ctrl_AES_XTS_Set_IV_BE(uint8_t region, uint8_t *iv, uint32_t addrOffset);
void SF_Ctrl_AES_Set_Mode(SF_Ctrl_AES_Mode_Type mode);
void SF_Ctrl_AES_Enable(void);
void SF_Ctrl_AES_Disable(void);
BL_Sts_Type SF_Ctrl_Is_AES_Enable(void);
void SF_Ctrl_Set_Flash_Image_Offset(uint32_t addrOffset, uint8_t group, SF_Ctrl_Bank_Select bank);
uint32_t SF_Ctrl_Get_Flash_Image_Offset(uint8_t group, SF_Ctrl_Bank_Select bank);
void SF_Ctrl_Lock_Flash_Image_Offset(uint8_t lock);
void SF_Ctrl_SendCmd(SF_Ctrl_Cmd_Cfg_Type *cfg);
void SF_Ctrl_Disable_Wrap_Access(uint8_t disable);
void SF_Ctrl_Flash_Read_Icache_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid);
void SF_Ctrl_Flash2_Read_Icache_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid);
BL_Sts_Type SF_Ctrl_GetBusyState(void);
/*@} end of group SF_CTRL_Public_Functions */
/*@} end of group SF_CTRL */
/*@} end of group BL616_Peripheral_Driver */
#endif /* __BL616_SF_CTRL_H__ */

220
drivers/soc/bl616/std/include/bl616_sflash.h
View file

@ -1,220 +0,0 @@
/**
******************************************************************************
* @file bl616_sflah.h
* @version V1.0
* @date
* @brief This file is the standard driver header file
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __BL616_SFLAH_H__
#define __BL616_SFLAH_H__
#include "bl616_common.h"
#include "bl616_sf_ctrl.h"
/** @addtogroup BL616_Peripheral_Driver
* @{
*/
/** @addtogroup SFLAH
* @{
*/
/** @defgroup SFLAH_Public_Types
* @{
*/
/**
* @brief Serial flash configuration structure type definition
*/
typedef struct
{
uint8_t ioMode; /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap,bit5:32-bits addr mode support */
uint8_t cReadSupport; /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */
uint8_t clkDelay; /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */
uint8_t clkInvert; /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */
uint8_t resetEnCmd; /*!< Flash enable reset command */
uint8_t resetCmd; /*!< Flash reset command */
uint8_t resetCreadCmd; /*!< Flash reset continuous read command */
uint8_t resetCreadCmdSize; /*!< Flash reset continuous read command size */
uint8_t jedecIdCmd; /*!< JEDEC ID command */
uint8_t jedecIdCmdDmyClk; /*!< JEDEC ID command dummy clock */
uint8_t enter32BitsAddrCmd; /*!< Enter 32-bits addr command */
uint8_t exit32BitsAddrCmd; /*!< Exit 32-bits addr command */
uint8_t sectorSize; /*!< *1024bytes */
uint8_t mid; /*!< Manufacturer ID */
uint16_t pageSize; /*!< Page size */
uint8_t chipEraseCmd; /*!< Chip erase cmd */
uint8_t sectorEraseCmd; /*!< Sector erase command */
uint8_t blk32EraseCmd; /*!< Block 32K erase command,some Micron not support */
uint8_t blk64EraseCmd; /*!< Block 64K erase command */
uint8_t writeEnableCmd; /*!< Need before every erase or program */
uint8_t pageProgramCmd; /*!< Page program cmd */
uint8_t qpageProgramCmd; /*!< QIO page program cmd */
uint8_t qppAddrMode; /*!< QIO page program address mode */
uint8_t fastReadCmd; /*!< Fast read command */
uint8_t frDmyClk; /*!< Fast read command dummy clock */
uint8_t qpiFastReadCmd; /*!< QPI fast read command */
uint8_t qpiFrDmyClk; /*!< QPI fast read command dummy clock */
uint8_t fastReadDoCmd; /*!< Fast read dual output command */
uint8_t frDoDmyClk; /*!< Fast read dual output command dummy clock */
uint8_t fastReadDioCmd; /*!< Fast read dual io comamnd */
uint8_t frDioDmyClk; /*!< Fast read dual io command dummy clock */
uint8_t fastReadQoCmd; /*!< Fast read quad output comamnd */
uint8_t frQoDmyClk; /*!< Fast read quad output comamnd dummy clock */
uint8_t fastReadQioCmd; /*!< Fast read quad io comamnd */
uint8_t frQioDmyClk; /*!< Fast read quad io comamnd dummy clock */
uint8_t qpiFastReadQioCmd; /*!< QPI fast read quad io comamnd */
uint8_t qpiFrQioDmyClk; /*!< QPI fast read QIO dummy clock */
uint8_t qpiPageProgramCmd; /*!< QPI program command */
uint8_t writeVregEnableCmd; /*!< Enable write reg */
uint8_t wrEnableIndex; /*!< Write enable register index */
uint8_t qeIndex; /*!< Quad mode enable register index */
uint8_t busyIndex; /*!< Busy status register index */
uint8_t wrEnableBit; /*!< Write enable bit pos */
uint8_t qeBit; /*!< Quad enable bit pos */
uint8_t busyBit; /*!< Busy status bit pos */
uint8_t wrEnableWriteRegLen; /*!< Register length of write enable */
uint8_t wrEnableReadRegLen; /*!< Register length of write enable status */
uint8_t qeWriteRegLen; /*!< Register length of contain quad enable */
uint8_t qeReadRegLen; /*!< Register length of contain quad enable status */
uint8_t releasePowerDown; /*!< Release power down command */
uint8_t busyReadRegLen; /*!< Register length of contain busy status */
uint8_t readRegCmd[4]; /*!< Read register command buffer */
uint8_t writeRegCmd[4]; /*!< Write register command buffer */
uint8_t enterQpi; /*!< Enter qpi command */
uint8_t exitQpi; /*!< Exit qpi command */
uint8_t cReadMode; /*!< Config data for continuous read mode */
uint8_t cRExit; /*!< Config data for exit continuous read mode */
uint8_t burstWrapCmd; /*!< Enable burst wrap command */
uint8_t burstWrapCmdDmyClk; /*!< Enable burst wrap command dummy clock */
uint8_t burstWrapDataMode; /*!< Data and address mode for this command */
uint8_t burstWrapData; /*!< Data to enable burst wrap */
uint8_t deBurstWrapCmd; /*!< Disable burst wrap command */
uint8_t deBurstWrapCmdDmyClk; /*!< Disable burst wrap command dummy clock */
uint8_t deBurstWrapDataMode; /*!< Data and address mode for this command */
uint8_t deBurstWrapData; /*!< Data to disable burst wrap */
uint16_t timeEsector; /*!< 4K erase time */
uint16_t timeE32k; /*!< 32K erase time */
uint16_t timeE64k; /*!< 64K erase time */
uint16_t timePagePgm; /*!< Page program time */
uint16_t timeCe; /*!< Chip erase time in ms */
uint8_t pdDelay; /*!< Release power down command delay time for wake up */
uint8_t qeData; /*!< QE set data */
} __attribute__((packed)) SPI_Flash_Cfg_Type;
/**
* @brief Serial flash security register configuration
*/
typedef struct
{
uint8_t eraseCmd; /*!< Erase security register command */
uint8_t programCmd; /*!< Program security register command */
uint8_t readCmd; /*!< Read security register command */
uint8_t enterSecOptCmd; /*!< Enter security register option mode command */
uint8_t exitSecOptCmd; /*!< Exit security register option mode command */
uint8_t blockNum; /*!< Security register block number */
uint8_t *data; /*!< Data pointer to be program/read */
uint32_t addr; /*!< Start address to be program/read */
uint32_t len; /*!< Data length to be program/read */
} SFlash_Sec_Reg_Cfg;
/*@} end of group SFLAH_Public_Types */
/** @defgroup SFLAH_Public_Constants
* @{
*/
/*@} end of group SFLAH_Public_Constants */
/** @defgroup SFLAH_Public_Macros
* @{
*/
#define BFLB_SPIFLASH_BLK32K_SIZE (32 * 1024)
#define BFLB_SPIFLASH_BLK64K_SIZE (64 * 1024)
#define BFLB_SPIFLASH_CMD_INVALID 0xff
/*@} end of group SFLAH_Public_Macros */
/** @defgroup SFLAH_Public_Functions
* @{
*/
void ATTR_TCM_SECTION SFlash_Init(const SF_Ctrl_Cfg_Type *pSfCtrlCfg, const SF_Ctrl_Bank2_Cfg *pBank2Cfg);
BL_Err_Type SFlash_SetSPIMode(SF_Ctrl_Mode_Type mode);
BL_Err_Type SFlash_Read_Reg(SPI_Flash_Cfg_Type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen);
BL_Err_Type SFlash_Write_Reg(SPI_Flash_Cfg_Type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen);
BL_Err_Type SFlash_Read_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t readRegCmd, uint8_t *regValue,
uint8_t regLen);
BL_Err_Type SFlash_Write_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t writeRegCmd, uint8_t *regValue,
uint8_t regLen);
BL_Sts_Type SFlash_Busy(SPI_Flash_Cfg_Type *flashCfg);
BL_Err_Type SFlash_Write_Enable(SPI_Flash_Cfg_Type *flashCfg);
BL_Err_Type SFlash_Qspi_Enable(SPI_Flash_Cfg_Type *flashCfg);
BL_Err_Type SFlash_Qspi_Disable(SPI_Flash_Cfg_Type *flashCfg);
void SFlash_Volatile_Reg_Write_Enable(SPI_Flash_Cfg_Type *flashCfg);
BL_Err_Type SFlash_Chip_Erase(SPI_Flash_Cfg_Type *flashCfg);
BL_Err_Type SFlash_Sector_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t secNum);
BL_Err_Type SFlash_Blk32_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum);
BL_Err_Type SFlash_Blk64_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum);
BL_Err_Type SFlash_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t startaddr, uint32_t endaddr);
void SFlash_GetUniqueId(uint8_t *data, uint8_t idLen);
void SFlash_GetJedecId(SPI_Flash_Cfg_Type *flashCfg, uint8_t *data);
void SFlash_GetDeviceId(uint8_t *data, BL_Fun_Type is32BitsAddr);
void SFlash_Powerdown(void);
void SFlash_Release_Powerdown(SPI_Flash_Cfg_Type *flashCfg);
BL_Err_Type SFlash_Restore_From_Powerdown(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t flashContRead,
SF_Ctrl_Bank_Select bank);
void SFlash_SetBurstWrap(SPI_Flash_Cfg_Type *flashCfg);
void SFlash_DisableBurstWrap(SPI_Flash_Cfg_Type *flashCfg);
BL_Err_Type SFlash_Set32BitsAddrMode(SPI_Flash_Cfg_Type *flashCfg, BL_Fun_Type en32BitsAddr);
BL_Err_Type SFlash_Software_Reset(SPI_Flash_Cfg_Type *flashCfg);
void SFlash_Reset_Continue_Read(SPI_Flash_Cfg_Type *flashCfg);
BL_Err_Type SFlash_Set_IDbus_Cfg(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr,
uint32_t len, SF_Ctrl_Bank_Select bank);
BL_Err_Type SFlash_IDbus_Read_Enable(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead,
SF_Ctrl_Bank_Select bank);
void SFlash_IDbus_Read_Disable(void);
BL_Err_Type SFlash_RCV_Enable(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t rCmd, uint8_t wCmd, uint8_t bitPos);
BL_Err_Type SFlash_Erase_Security_Register(SPI_Flash_Cfg_Type *pFlashCfg, SFlash_Sec_Reg_Cfg *pSecRegCfg);
BL_Err_Type SFlash_Program_Security_Register(SPI_Flash_Cfg_Type *pFlashCfg,
SFlash_Sec_Reg_Cfg *pSecRegCfg);
BL_Err_Type SFlash_Read_Security_Register(SFlash_Sec_Reg_Cfg *pSecRegCfg);
BL_Err_Type SFlash_Read(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, uint8_t *data,
uint32_t len);
BL_Err_Type SFlash_Program(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *data, uint32_t len);
BL_Err_Type SFlash_Clear_Status_Register(SPI_Flash_Cfg_Type *flashCfg);
/*@} end of group SFLAH_Public_Functions */
/*@} end of group SFLAH */
/*@} end of group BL616_Peripheral_Driver */
#endif /* __BL616_SFLAH_H__ */

100
drivers/soc/bl616/std/include/bl616_xip_sflash.h
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@ -1,100 +0,0 @@
/**
******************************************************************************
* @file bl616_xip_sflash.h
* @version V1.0
* @date
* @brief This file is the standard driver header file
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __BL616_XIP_SFLASH_H__
#define __BL616_XIP_SFLASH_H__
#include "bl616_common.h"
#include "bl616_sflash.h"
/** @addtogroup BL616_Peripheral_Driver
* @{
*/
/** @addtogroup XIP_SFLASH
* @{
*/
/** @defgroup XIP_SFLASH_Public_Types
* @{
*/
/*@} end of group XIP_SFLASH_Public_Types */
/** @defgroup XIP_SFLASH_Public_Constants
* @{
*/
/*@} end of group XIP_SFLASH_Public_Constants */
/** @defgroup XIP_SFLASH_Public_Macros
* @{
*/
/*@} end of group XIP_SFLASH_Public_Macros */
/** @defgroup XIP_SFLASH_Public_Functions
* @{
*/
BL_Err_Type XIP_SFlash_State_Save(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t *offset,
uint8_t group, SF_Ctrl_Bank_Select bank);
BL_Err_Type XIP_SFlash_State_Restore(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t offset,
uint8_t group, SF_Ctrl_Bank_Select bank);
BL_Err_Type XIP_SFlash_Erase_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t startaddr,
int len, uint8_t group, SF_Ctrl_Bank_Select bank);
BL_Err_Type XIP_SFlash_Write_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t addr,
uint8_t *data, uint32_t len, uint8_t group, SF_Ctrl_Bank_Select bank);
BL_Err_Type XIP_SFlash_Read_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t addr,
uint8_t *data, uint32_t len, uint8_t group, SF_Ctrl_Bank_Select bank);
BL_Err_Type XIP_SFlash_GetJedecId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t *data,
uint8_t group, SF_Ctrl_Bank_Select bank);
BL_Err_Type XIP_SFlash_GetDeviceId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, BL_Fun_Type is32BitsAddr,
uint8_t *data, uint8_t group, SF_Ctrl_Bank_Select bank);
BL_Err_Type XIP_SFlash_GetUniqueId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t *data,
uint8_t idLen, uint8_t group, SF_Ctrl_Bank_Select bank);
BL_Err_Type XIP_SFlash_Read_Via_Cache_Need_Lock(uint32_t addr, uint8_t *data, uint32_t len);
void XIP_SFlash_Opt_Enter(uint8_t *aesEnable);
void XIP_SFlash_Opt_Exit(uint8_t aesEnable);
BL_Err_Type XIP_SFlash_Clear_Status_Register_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg,
uint8_t group, SF_Ctrl_Bank_Select bank);
/*@} end of group XIP_SFLASH_Public_Functions */
/*@} end of group XIP_SFLASH */
/*@} end of group BL616_Peripheral_Driver */
#endif /* __BL616_XIP_SFLASH_H__ */

33
drivers/soc/bl616/std/include/hardware/auadc_reg.h
View file

@ -48,15 +48,7 @@
#define AUADC_PDM_ADC_1_OFFSET (0xC0C) /* pdm_adc_1 */
#define AUADC_PDM_DAC_0_OFFSET (0xC10) /* pdm_dac_0 */
#define AUADC_PDM_PDM_0_OFFSET (0xC1C) /* pdm_pdm_0 */
#define AUADC_PDM_RSVD0_OFFSET (0xC20) /* pdm_rsvd0 */
#define AUADC_PDM_DBG_0_OFFSET (0xC24) /* pdm_dbg_0 */
#define AUADC_PDM_DBG_1_OFFSET (0xC28) /* pdm_dbg_1 */
#define AUADC_PDM_DBG_2_OFFSET (0xC2C) /* pdm_dbg_2 */
#define AUADC_PDM_DBG_3_OFFSET (0xC30) /* pdm_dbg_3 */
#define AUADC_PDM_DBG_4_OFFSET (0xC34) /* pdm_dbg_4 */
#define AUADC_PDM_ADC_S0_OFFSET (0xC38) /* pdm_adc_s0 */
#define AUADC_PDM_ADC_S1_OFFSET (0xC3C) /* pdm_adc_s1 */
#define AUADC_PDM_ADC_S2_OFFSET (0xC40) /* pdm_adc_s2 */
#define AUADC_AUDADC_ANA_CFG1_OFFSET (0xC60) /* audadc_ana_cfg1 */
#define AUADC_AUDADC_ANA_CFG2_OFFSET (0xC64) /* audadc_ana_cfg2 */
#define AUADC_AUDADC_CMD_OFFSET (0xC68) /* audadc_cmd */
@ -101,35 +93,10 @@
#define AUADC_ADC_0_PDM_SEL_SHIFT (3U)
#define AUADC_ADC_0_PDM_SEL_MASK (0x7 << AUADC_ADC_0_PDM_SEL_SHIFT)
/* 0xC20 : pdm_rsvd0 */
/* 0xC24 : pdm_dbg_0 */
#define AUADC_ADC_TEST_CLKIN_EN (1 << 21U)
#define AUADC_ADC_TEST_DIN_EN (1 << 23U)
#define AUADC_AUD_TEST_READ_SEL_SHIFT (24U)
#define AUADC_AUD_TEST_READ_SEL_MASK (0x3f << AUADC_AUD_TEST_READ_SEL_SHIFT)
/* 0xC28 : pdm_dbg_1 */
#define AUADC_AUD_TEST_READ_SHIFT (0U)
#define AUADC_AUD_TEST_READ_MASK (0xffffffff << AUADC_AUD_TEST_READ_SHIFT)
/* 0xC2C : pdm_dbg_2 */
#define AUADC_ADC_FIR_4S_VAL_SHIFT (0U)
#define AUADC_ADC_FIR_4S_VAL_MASK (0xfffff << AUADC_ADC_FIR_4S_VAL_SHIFT)
#define AUADC_ADC_0_FIR_4S_EN (1 << 20U)
/* 0xC30 : pdm_dbg_3 */
/* 0xC34 : pdm_dbg_4 */
/* 0xC38 : pdm_adc_s0 */
#define AUADC_ADC_S0_VOLUME_SHIFT (0U)
#define AUADC_ADC_S0_VOLUME_MASK (0x1ff << AUADC_ADC_S0_VOLUME_SHIFT)
/* 0xC3C : pdm_adc_s1 */
/* 0xC40 : pdm_adc_s2 */
/* 0xC60 : audadc_ana_cfg1 */
#define AUADC_AUDADC_PGA_CHOP_CKSEL (1 << 0U)
#define AUADC_AUDADC_PGA_CHOP_FREQ_SHIFT (1U)