mirror of
https://github.com/Fishwaldo/bl_mcu_sdk.git
synced 2025-07-04 03:49:13 +00:00
[sync] sync from internal repo
* use nuttx libc, disable system libc * use tlsf as default * update lhal flash driver * add example readme * add flash ini for new flash tool * add fw header for new flash tool
This commit is contained in:
jzlv
parent
89592fc9a3
commit
356f258e83
554 changed files with 79150 additions and 46596 deletions
43
examples/boot2_isp/README.md
Normal file
43
examples/boot2_isp/README.md
Normal file
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@ -0,0 +1,43 @@
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# boot2_isp
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## Support CHIP
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| CHIP | Remark |
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|:----------------:|:------:|
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|BL602/BL604 | |
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|BL702/BL704/BL706 | |
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|BL616/BL618 | |
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|BL808 | Only for m0 CPU |
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## Compile
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- BL602/BL604
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```
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make CHIP=bl602 BOARD=bl602dk
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```
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- BL702/BL704/BL706
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```
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make CHIP=bl702 BOARD=bl702dk
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```
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- BL616/BL618
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```
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make CHIP=bl616 BOARD=bl616dk
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```
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- BL808
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```
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make CHIP=bl808 BOARD=bl808dk CPU_ID=m0
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```
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## Flash
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```
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make flash CHIP=chip_name COMX=xxx # xxx is your com name
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```
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@ -48,6 +48,8 @@
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#define BFLB_EFLASH_LOADER_CHECK_LEN 2048
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#define BFLB_EFLASH_MAX_SIZE 2 * 1024 * 1024
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// 4bytes、32bit数据大小端转化
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#define L2B32(Little) (((Little & 0xff) << 24) | (((Little) & 0xff00) << 8) | (((Little) & 0xff0000) >> 8) | ((Little >> 24) & 0xff))
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#if BLSP_BOOT2_SUPPORT_EFLASH_LOADER_RAM
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static struct image_cfg_t image_cfg;
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@ -479,9 +481,12 @@ static int32_t bflb_eflash_loader_cmd_read_jedec_id(uint16_t cmd, uint8_t *data,
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/*ack read jedec ID */
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tmp_buf[2] = 4;
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tmp_buf[3] = 0;
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ackdata[0] = bflb_flash_get_jedec_id();
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ackdata[1] = bflb_flash_get_jedec_id();
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ackdata[1] &= 0x00ffffff;
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ackdata[1] |= 0x80000000;
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ackdata[1] = (ackdata[1]) << 8;
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ackdata[1] |= 0x80;
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ackdata[1] = L2B32(ackdata[1]);
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bflb_eflash_loader_if_write((uint32_t *)ackdata, 4 + 4);
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return BFLB_EFLASH_LOADER_SUCCESS;
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}
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@ -120,7 +120,7 @@ struct eflash_loader_cmd_cfg_t {
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__PACKED_STRUCT boot_flash_cfg_t
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{
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uint32_t magiccode; /*'FCFG'*/
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SPI_Flash_Cfg_Type cfg;
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spi_flash_cfg_type cfg;
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uint32_t crc32;
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};
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@ -39,6 +39,7 @@
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#include "partition.h"
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#include "bflb_uart.h"
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#include "bflb_port_boot2.h"
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#include "bflb_uart.h"
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static uint32_t g_detected_baudrate;
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struct bflb_device_s *uartx;
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@ -53,10 +54,39 @@ void bflb_dump_data(uint8_t *buf, uint32_t size)
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}
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LOG_F("\r\n");
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}
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static uint32_t uart_read_all_data(uint8_t *buf,uint32_t maxlen)
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{
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return bflb_uart_get(uartx, buf, maxlen);
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}
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void ATTR_TCM_SECTION uart0_irq_callback(struct device *dev, void *args, uint32_t size, uint32_t state)
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{
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}
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void ATTR_TCM_SECTION uart_isr(int irq, void *arg)
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{
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uint32_t intstatus = bflb_uart_get_intstatus(uartx);
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if (intstatus & UART_INTSTS_RX_FIFO) {
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uint8_t *buf=(uint8_t *)g_eflash_loader_readbuf[g_rx_buf_index];
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g_rx_buf_len+=uart_read_all_data(buf+g_rx_buf_len,
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BFLB_EFLASH_LOADER_READBUF_SIZE-g_rx_buf_len);
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bflb_uart_int_clear(uartx, UART_INTSTS_RX_FIFO);
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}
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if (intstatus & UART_INTSTS_RTO) {
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uint8_t *buf=(uint8_t *)g_eflash_loader_readbuf[g_rx_buf_index];
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g_rx_buf_len+=uart_read_all_data(buf+g_rx_buf_len,
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BFLB_EFLASH_LOADER_READBUF_SIZE-g_rx_buf_len);
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bflb_uart_int_clear(uartx, UART_INTCLR_RTO);
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}
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}
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static void bflb_eflash_loader_usart_if_init(uint32_t bdrate)
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{
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struct bflb_uart_config_s cfg;
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@ -68,8 +98,8 @@ static void bflb_eflash_loader_usart_if_init(uint32_t bdrate)
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cfg.stop_bits = UART_STOP_BITS_1;
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cfg.parity = UART_PARITY_NONE;
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cfg.flow_ctrl = 0;
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cfg.tx_fifo_threshold = 7;
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cfg.rx_fifo_threshold = 7;
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cfg.tx_fifo_threshold = 16;
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cfg.rx_fifo_threshold = 16;
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bflb_uart_init(uartx, &cfg);
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}
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@ -80,7 +110,7 @@ void bflb_eflash_loader_usart_if_enable_int(void)
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void bflb_eflash_loader_usart_if_send(uint8_t *data, uint32_t len)
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{
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uartx = bflb_device_get_by_name("uart0");
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//uartx = bflb_device_get_by_name("uart0");
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bflb_uart_put(uartx, data, len);
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}
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@ -94,6 +124,35 @@ int32_t bflb_eflash_loader_usart_if_wait_tx_idle(uint32_t timeout)
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static uint32_t *bflb_eflash_loader_usart_if_receive(uint32_t *recv_len, uint16_t maxlen, uint16_t timeout)
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{
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uint8_t *buf = (uint8_t *)g_eflash_loader_readbuf[g_rx_buf_index];
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uint16_t datalen = 0;
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uint64_t time_now;
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time_now = bflb_mtimer_get_time_ms();
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do {
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if (g_rx_buf_len >= 4) {
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/* receive cmd id and data len*/
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datalen = buf[2] + (buf[3] << 8);
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if (g_rx_buf_len == datalen + 4) {
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/*receive all the payload,return */
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/* move on to next buffer */
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g_rx_buf_index = (g_rx_buf_index + 1) % 2;
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g_rx_buf_len = 0;
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if (datalen <= BFLB_EFLASH_LOADER_CMD_DATA_MAX_LEN) {
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*recv_len = datalen + 4;
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return (uint32_t *)buf;
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} else {
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*recv_len = 0;
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return NULL;
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}
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}
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}
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} while (bflb_mtimer_get_time_ms() - time_now < timeout);
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*recv_len = 0;
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return NULL;
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}
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@ -118,7 +177,7 @@ int32_t bflb_eflash_loader_uart_handshake_poll(uint32_t timeout)
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uint32_t handshake_count = 0;
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uint32_t rcv_buf_len = 0;
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//rcv_buf_len = UART_ReceiveData(g_uart_if_id,buf,128);
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uartx = bflb_device_get_by_name("uart0");
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//uartx = bflb_device_get_by_name("uart0");
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rcv_buf_len = bflb_uart_get(uartx, buf, UART_FIFO_LEN);
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//while(1)
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@ -167,7 +226,7 @@ int32_t bflb_eflash_loader_uart_handshake_poll(uint32_t timeout)
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}
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} while (bflb_mtimer_get_time_ms() - nowtime < BFLB_EFLASH_LAODER_COMSUME_55_TIMEOUT);
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bflb_eflash_loader_usart_if_send((uint8_t *)"Boot2 ISP Ready", strlen("Boot2 ISP Ready"));
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/*init rx info */
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g_rx_buf_index = 0;
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@ -180,7 +239,10 @@ int32_t bflb_eflash_loader_uart_handshake_poll(uint32_t timeout)
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arch_memset(g_eflash_loader_readbuf[0], 0, BFLB_EFLASH_LOADER_READBUF_SIZE);
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arch_memset(g_eflash_loader_readbuf[1], 0, BFLB_EFLASH_LOADER_READBUF_SIZE);
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bflb_irq_attach(uartx->irq_num, uart_isr, NULL);
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bflb_eflash_loader_usart_if_enable_int();
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bflb_irq_enable(uartx->irq_num);
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bflb_eflash_loader_usart_if_send((uint8_t *)"Boot2 ISP Ready", strlen("Boot2 ISP Ready"));
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#endif
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@ -43,6 +43,7 @@
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#include "blsp_media_boot.h"
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#include "bflb_flash.h"
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#include "bflb_eflash_loader.h"
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#include "bflb_uart.h"
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ATTR_NOCACHE_NOINIT_RAM_SECTION uint8_t g_malloc_buf[BFLB_BOOT2_XZ_MALLOC_BUF_SIZE];
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@ -88,7 +89,7 @@ int32_t blsp_mediaboot_pre_jump(void)
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/* reinit mtimer clock */
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//system_mtimer_clock_reinit();
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bflb_uart_deinit(uartx);
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/* deinit uart */
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hal_boot2_debug_uart_gpio_deinit();
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@ -184,10 +184,10 @@ int32_t ATTR_TCM_SECTION blsp_boot2_set_encrypt(uint8_t index, boot2_image_confi
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len = g_boot_img_cfg->basic_cfg.img_len_cnt;
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if (len != 0) {
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SF_Ctrl_AES_Set_Key_BE(index, NULL, (SF_Ctrl_AES_Key_Type)(g_boot_img_cfg->basic_cfg.encrypt_type - 1));
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SF_Ctrl_AES_Set_IV_BE(index, g_boot_img_cfg->aes_iv, g_boot_img_cfg->basic_cfg.group_image_offset);
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bflb_sf_ctrl_aes_set_key_be(index, NULL, (g_boot_img_cfg->basic_cfg.encrypt_type - 1));
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bflb_sf_ctrl_aes_set_iv_be(index, g_boot_img_cfg->aes_iv, g_boot_img_cfg->basic_cfg.group_image_offset);
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SF_Ctrl_AES_Set_Region(index, 1 /*enable this region*/, 1 /*hardware key*/,
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bflb_sf_ctrl_aes_set_region(index, 1 /*enable this region*/, 1 /*hardware key*/,
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g_boot_img_cfg->basic_cfg.group_image_offset,
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g_boot_img_cfg->basic_cfg.group_image_offset + len - 1,
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g_boot_img_cfg->basic_cfg.aes_region_lock /*lock*/);
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@ -196,8 +196,8 @@ int32_t ATTR_TCM_SECTION blsp_boot2_set_encrypt(uint8_t index, boot2_image_confi
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}
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if (aes_enabled) {
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SF_Ctrl_AES_Enable_BE();
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SF_Ctrl_AES_Enable();
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bflb_sf_ctrl_aes_enable_be();
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bflb_sf_ctrl_aes_enable();
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}
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return BFLB_BOOT2_SUCCESS;
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@ -1,41 +0,0 @@
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/**
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******************************************************************************
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* @file blsp_version.h
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* @version V1.2
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* @date
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* @brief This file is the peripheral case header file
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2018 Bouffalo Lab</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
|
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of Bouffalo Lab nor the names of its contributors
|
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* may be used to endorse or promote products derived from this software
|
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* without specific prior written permission.
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*
|
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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#ifndef __MCU_SDK_VERSION_H__
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#define __MCU_SDK_VERSION_H__
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#define BL_SDK_VER "1.0.0"
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#endif
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11
examples/boot2_isp/flash_prog_cfg.ini
Normal file
11
examples/boot2_isp/flash_prog_cfg.ini
Normal file
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@ -0,0 +1,11 @@
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[cfg]
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# 0: no erase, 1:programmed section erase, 2: chip erase
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erase = 1
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# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated
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skip_mode = 0x0, 0x0
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# 0: not use isp mode, #1: isp mode
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boot2_isp_mode = 0
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[FW]
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filedir = ./build/build_out/boot2_isp_$(CHIPNAME).bin
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address = 0x000000
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@ -362,7 +362,7 @@ int main(void)
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#endif
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uint8_t mfg_mode_flag = 0;
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//boot_clk_config clk_cfg;
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uint8_t flash_cfg_buf[4 + sizeof(SPI_Flash_Cfg_Type) + 4] = { 0 };
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uint8_t flash_cfg_buf[4 + sizeof(spi_flash_cfg_type) + 4] = { 0 };
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uint32_t crc;
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uint8_t *flash_cfg = NULL;
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uint32_t flash_cfg_len = 0;
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@ -3,8 +3,6 @@
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#include "bl602_glb.h"
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#include "bl602_ef_ctrl.h"
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#include "bl602_hbn.h"
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#include "bl602_xip_sflash.h"
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#include "bl602_sf_cfg.h"
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#include "bl602_sf_cfg_ext.h"
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#include "bl602_glb.h"
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#include "bl602_xip_sflash_ext.h"
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@ -502,7 +500,7 @@ void ATTR_TCM_SECTION hal_boot2_release_cpu(uint32_t core, uint32_t boot_addr)
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*******************************************************************************/
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uint32_t hal_boot2_get_xip_addr(uint32_t flash_addr)
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{
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uint32_t img_offset = SF_Ctrl_Get_Flash_Image_Offset();
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uint32_t img_offset = bflb_sf_ctrl_get_flash_image_offset(0,0);
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if (flash_addr >= img_offset) {
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return BL602_FLASH_XIP_BASE + (flash_addr - img_offset);
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} else {
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|
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@ -36,7 +36,6 @@
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#ifndef __BFLB_PORT_BOOT2_H__
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#define __BFLB_PORT_BOOT2_H__
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#include "bl602_sflash.h"
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#include "bl602_glb.h"
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#define BL_TCM_BASE BL602_TCM_BASE
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@ -101,7 +100,7 @@ typedef struct
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struct __attribute__((packed, aligned(4))) hal_flash_config {
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uint32_t magicCode; /*'FCFG'*/
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SPI_Flash_Cfg_Type cfg;
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spi_flash_cfg_type cfg;
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uint32_t crc32;
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};
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|
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|
|
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|
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@ -5,7 +5,6 @@
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#include "bl606p_hbn.h"
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#include "bl606p_glb.h"
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#include "bl606p_pds.h"
|
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#include "bl606p_xip_sflash.h"
|
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#include "bl606p_tzc_sec.h"
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#include "bflb_gpio.h"
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#include "softcrc.h"
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|
|
@ -195,7 +194,7 @@ static uint16_t hal_boot2_x8_psram_calibration(int32_t *psram_dqs_win_num)
|
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|
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LOG_F("r ef:0x%08lx\r\n", g_efuse_cfg.psram_dqs_cfg);
|
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before_ef = g_efuse_cfg.psram_dqs_cfg;
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if ((g_efuse_cfg.psram_dqs_cfg & (0x1000)) && (g_efuse_cfg.psram_dqs_cfg != 0xffff)) {
|
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if (g_efuse_cfg.psram_dqs_cfg != 0xffff) {
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left_flag = ((g_efuse_cfg.psram_dqs_cfg & (0xf0)) >> 0x4);
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right_flag = (g_efuse_cfg.psram_dqs_cfg & (0xf));
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c_val = ((left_flag + right_flag) >> 0x1);
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|
|
@ -225,11 +224,7 @@ static uint16_t hal_boot2_x8_psram_calibration(int32_t *psram_dqs_win_num)
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c_val = ((left_flag + right_flag) >> 1);
|
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|
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g_efuse_cfg.psram_dqs_cfg = (((left_flag << 0x4) | (right_flag)) & (0xff));
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if (bflb_ef_ctrl_get_trim_parity(g_efuse_cfg.psram_dqs_cfg, 11)) {
|
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g_efuse_cfg.psram_dqs_cfg = ((0x1800) | (g_efuse_cfg.psram_dqs_cfg));
|
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} else {
|
||||
g_efuse_cfg.psram_dqs_cfg = ((0x1000) | (g_efuse_cfg.psram_dqs_cfg));
|
||||
}
|
||||
|
||||
LOG_F("c ef:0x%08lx\r\n", g_efuse_cfg.psram_dqs_cfg);
|
||||
*psram_dqs_win_num = right_flag - left_flag;
|
||||
if (((*psram_dqs_win_num) <= 4) || ((*psram_dqs_win_num) > 0xf)) {
|
||||
|
|
@ -364,11 +359,11 @@ uint32_t hal_boot2_custom(void *custom_param)
|
|||
ret = hal_boot2_x8_psram_calibration(&psram_dqs_win_num);
|
||||
if (ret == ERROR) {
|
||||
while (1) {
|
||||
printf("psram:%d\r\n", (int)psram_dqs_win_num);
|
||||
LOG_F("psram:%d\r\n", (int)psram_dqs_win_num);
|
||||
arch_delay_ms(500);
|
||||
}
|
||||
}
|
||||
printf("psram:%d \r\n", (int)psram_dqs_win_num);
|
||||
LOG_F("psram:%d \r\n", (int)psram_dqs_win_num);
|
||||
|
||||
/* Flush i-cache in case branch prediction logic is wrong when
|
||||
psram is not inited by hal_boot2_custom but cpu has already prefetch psram */
|
||||
|
|
@ -449,7 +444,7 @@ void hal_boot2_get_efuse_cfg(boot2_efuse_hw_config *efuse_cfg)
|
|||
}
|
||||
|
||||
/* get device info */
|
||||
//EF_Ctrl_Get_Chip_Info((Efuse_Chip_Info_Type *)&efuse_cfg->dev_info);
|
||||
bflb_ef_ctrl_get_device_info((bflb_efuse_device_info_type *)&efuse_cfg->dev_info);
|
||||
|
||||
/* get chip id */
|
||||
bflb_efuse_get_chipid(efuse_cfg->chip_id);
|
||||
|
|
@ -858,7 +853,7 @@ void ATTR_TCM_SECTION hal_boot2_release_cpu(uint32_t core, uint32_t boot_addr)
|
|||
*******************************************************************************/
|
||||
uint32_t hal_boot2_get_xip_addr(uint32_t flash_addr)
|
||||
{
|
||||
uint32_t img_offset = SF_Ctrl_Get_Flash_Image_Offset(0, SF_CTRL_FLASH_BANK0);
|
||||
uint32_t img_offset = bflb_sf_ctrl_get_flash_image_offset(0, SF_CTRL_FLASH_BANK0);
|
||||
if (flash_addr >= img_offset) {
|
||||
return BL606P_FLASH_XIP_BASE + (flash_addr - img_offset);
|
||||
} else {
|
||||
|
|
|
|||
|
|
@ -36,7 +36,6 @@
|
|||
#ifndef __BFLB_PORT_BOOT2_H__
|
||||
#define __BFLB_PORT_BOOT2_H__
|
||||
|
||||
#include "bl606p_sflash.h"
|
||||
#include "bl606p_glb.h"
|
||||
#include "bl606p_pm.h"
|
||||
|
||||
|
|
@ -167,13 +166,13 @@ typedef struct
|
|||
|
||||
struct __attribute__((packed, aligned(4))) hal_flash_config {
|
||||
uint32_t magicCode; /*'FCFG'*/
|
||||
SPI_Flash_Cfg_Type cfg;
|
||||
spi_flash_cfg_type cfg;
|
||||
uint32_t crc32;
|
||||
};
|
||||
|
||||
struct hal_psram_config {
|
||||
uint32_t magicCode; /*'FCFG'*/
|
||||
SPI_Flash_Cfg_Type cfg;
|
||||
spi_flash_cfg_type cfg;
|
||||
uint32_t crc32;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -23,7 +23,7 @@ HeapMinSize = 0x1000; /* 4KB */
|
|||
PROVIDE(__boot2_pass_param_addr = 0x62047E00);/* 0x62030000+96*1024-512 */
|
||||
MEMORY
|
||||
{
|
||||
xip_memory (rx) : ORIGIN = 0x58000000, LENGTH = 48K
|
||||
xip_memory (rx) : ORIGIN = 0x58000000, LENGTH = 58K
|
||||
itcm_memory (rx) : ORIGIN = 0x62020000, LENGTH = 48K
|
||||
dtcm_memory (rx) : ORIGIN = 0x6202C000, LENGTH = 4K
|
||||
nocache_ram_memory (!rx) : ORIGIN = 0x2202D000, LENGTH = 84K
|
||||
|
|
|
|||
|
|
@ -38,11 +38,11 @@
|
|||
#include "bl616_ef_ctrl.h"
|
||||
#include "bl616_hbn.h"
|
||||
#include "bl616_glb.h"
|
||||
#include "bl616_xip_sflash.h"
|
||||
#include "bl616_tzc_sec.h"
|
||||
#include "softcrc.h"
|
||||
#include "bl616_psram.h"
|
||||
#include "bflb_flash.h"
|
||||
#include "log.h"
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief init boot2 system clock
|
||||
|
|
@ -228,8 +228,7 @@ static uint16_t hal_boot2_x8_psram_calibration(int32_t *psram_dqs_win_num)
|
|||
printf("r ef:0x%08lx\r\n", g_efuse_cfg.psram_dqs_cfg);
|
||||
#endif
|
||||
before_ef = g_efuse_cfg.psram_dqs_cfg;
|
||||
if ((g_efuse_cfg.psram_dqs_cfg & (0x1000)) &&
|
||||
(((g_efuse_cfg.psram_dqs_cfg & 0x800) >> 11) == EF_Ctrl_Get_Trim_Parity(g_efuse_cfg.psram_dqs_cfg, 11))) {
|
||||
if (g_efuse_cfg.psram_dqs_cfg != 0xffff) {
|
||||
left_flag = ((g_efuse_cfg.psram_dqs_cfg & (0xf0)) >> 0x4);
|
||||
right_flag = (g_efuse_cfg.psram_dqs_cfg & (0xf));
|
||||
c_val = ((left_flag + right_flag) >> 0x1);
|
||||
|
|
@ -263,11 +262,7 @@ static uint16_t hal_boot2_x8_psram_calibration(int32_t *psram_dqs_win_num)
|
|||
// printf("window: 0x%02x ~ 0x%02x; c_val: 0x%02x; dqs:0x%04x; code num:%d\r\n", left_flag, right_flag, c_val, dqs_val[c_val], (right_flag - left_flag));
|
||||
|
||||
g_efuse_cfg.psram_dqs_cfg = (((left_flag << 0x4) | (right_flag)) & (0xff));
|
||||
if (EF_Ctrl_Get_Trim_Parity(g_efuse_cfg.psram_dqs_cfg, 11)) {
|
||||
g_efuse_cfg.psram_dqs_cfg = ((0x1800) | (g_efuse_cfg.psram_dqs_cfg));
|
||||
} else {
|
||||
g_efuse_cfg.psram_dqs_cfg = ((0x1000) | (g_efuse_cfg.psram_dqs_cfg));
|
||||
}
|
||||
|
||||
#ifdef CONFIG_DEBUG
|
||||
printf("c ef:0x%08lx\r\n", g_efuse_cfg.psram_dqs_cfg);
|
||||
/* printf("window: 0x%02x ~ 0x%02x; c_val: 0x%02x; dqs:0x%08x; code num:%d\r\n", left_flag, right_flag, c_val, dqs_val[c_val], (right_flag - left_flag)); */
|
||||
|
|
@ -282,7 +277,7 @@ static uint16_t hal_boot2_x8_psram_calibration(int32_t *psram_dqs_win_num)
|
|||
}
|
||||
/* to do write efuse psram dqs delay */
|
||||
if (!(before_ef & 0x1fff)) {
|
||||
// EF_Ctrl_Write_Psram_Trim((Efuse_Psram_Trim_Type *)&g_efuse_cfg.psram_dqs_cfg, ENABLE);
|
||||
bflb_ef_ctrl_write_common_trim(NULL,"psram",g_efuse_cfg.psram_dqs_cfg,1);
|
||||
}
|
||||
}
|
||||
return psram_id;
|
||||
|
|
@ -314,11 +309,11 @@ uint32_t hal_boot2_custom(void *custom_param)
|
|||
__ISB();
|
||||
if (ret == ERROR) {
|
||||
while (1) {
|
||||
printf("psram error:%d\r\n", (int)psram_dqs_win_num);
|
||||
LOG_F("psram error:%d\r\n", (int)psram_dqs_win_num);
|
||||
arch_delay_ms(500);
|
||||
}
|
||||
}
|
||||
printf("psram suss:%d \r\n", (int)psram_dqs_win_num);
|
||||
LOG_F("psram suss:%d \r\n", (int)psram_dqs_win_num);
|
||||
}
|
||||
|
||||
return ret;
|
||||
|
|
@ -790,7 +785,7 @@ void ATTR_TCM_SECTION hal_boot2_release_cpu(uint32_t core, uint32_t boot_addr)
|
|||
*******************************************************************************/
|
||||
uint32_t hal_boot2_get_xip_addr(uint32_t flash_addr)
|
||||
{
|
||||
uint32_t img_offset = SF_Ctrl_Get_Flash_Image_Offset(0, SF_CTRL_FLASH_BANK0);
|
||||
uint32_t img_offset = bflb_sf_ctrl_get_flash_image_offset(0, SF_CTRL_FLASH_BANK0);
|
||||
if (flash_addr >= img_offset) {
|
||||
return BL616_FLASH_XIP_BASE + (flash_addr - img_offset);
|
||||
} else {
|
||||
|
|
|
|||
|
|
@ -36,7 +36,6 @@
|
|||
#ifndef __BFLB_PORT_BOOT2_H__
|
||||
#define __BFLB_PORT_BOOT2_H__
|
||||
|
||||
#include "bl616_sflash.h"
|
||||
#include "bl616_glb.h"
|
||||
#include "bl616_common.h"
|
||||
|
||||
|
|
@ -165,7 +164,7 @@ typedef struct
|
|||
|
||||
struct __attribute__((packed, aligned(4))) hal_flash_config {
|
||||
uint32_t magicCode; /*'FCFG'*/
|
||||
SPI_Flash_Cfg_Type cfg;
|
||||
spi_flash_cfg_type cfg;
|
||||
uint32_t crc32;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -3,7 +3,6 @@
|
|||
#include "bl702_ef_ctrl.h"
|
||||
#include "bl702_hbn.h"
|
||||
#include "bl702_glb.h"
|
||||
#include "bl702_xip_sflash.h"
|
||||
#include "bflb_gpio.h"
|
||||
#include "softcrc.h"
|
||||
#include "bl702_clock.h"
|
||||
|
|
@ -492,7 +491,7 @@ void ATTR_TCM_SECTION hal_boot2_release_cpu(uint32_t core, uint32_t boot_addr)
|
|||
*******************************************************************************/
|
||||
uint32_t hal_boot2_get_xip_addr(uint32_t flash_addr)
|
||||
{
|
||||
uint32_t img_offset = SF_Ctrl_Get_Flash_Image_Offset();
|
||||
uint32_t img_offset = bflb_sf_ctrl_get_flash_image_offset(0,0);
|
||||
if (flash_addr >= img_offset) {
|
||||
return BL702_FLASH_XIP_BASE + (flash_addr - img_offset);
|
||||
} else {
|
||||
|
|
|
|||
|
|
@ -40,7 +40,6 @@
|
|||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "bl702_sflash.h"
|
||||
#include "bl702_glb.h"
|
||||
|
||||
#define BL_TCM_BASE BL702_TCM_BASE
|
||||
|
|
@ -105,7 +104,7 @@ typedef struct
|
|||
|
||||
struct __attribute__((packed, aligned(4))) hal_flash_config {
|
||||
uint32_t magicCode; /*'FCFG'*/
|
||||
SPI_Flash_Cfg_Type cfg;
|
||||
spi_flash_cfg_type cfg;
|
||||
uint32_t crc32;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -4,12 +4,12 @@
|
|||
#include "bl808_ef_cfg.h"
|
||||
#include "bl808_hbn.h"
|
||||
#include "bl808_glb.h"
|
||||
#include "bl808_xip_sflash.h"
|
||||
#include "bl808_tzc_sec.h"
|
||||
#include "bflb_gpio.h"
|
||||
#include "softcrc.h"
|
||||
#include "bl808_psram_uhs.h"
|
||||
#include "bflb_efuse.h"
|
||||
#include "bl808_uhs_phy.h"
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief init clock
|
||||
|
|
@ -38,17 +38,55 @@ void hal_boot2_init_clock(void)
|
|||
*******************************************************************************/
|
||||
uint32_t hal_boot2_custom(void *custom_param)
|
||||
{
|
||||
extern uhs_phy_cal_res_struct* uhs_phy_cal_res;
|
||||
PSRAM_UHS_Cfg_Type psramDefaultCfg = {
|
||||
2000,
|
||||
PSRAM_MEM_SIZE_32MB,
|
||||
PSRAM_PAGE_SIZE_2KB,
|
||||
PSRAM_UHS_NORMAL_TEMP,
|
||||
};
|
||||
bflb_efuse_device_info_type chip_info;
|
||||
|
||||
//EF_Ctrl_Trim_DCDC_And_LDO();
|
||||
AON_Trim_USB20_RCAL();
|
||||
//GLB_Readjust_LDO18IO_Vout();
|
||||
if (((g_efuse_cfg.dev_info & HAL_BOOT2_PSRAM_INFO_MASK) >> HAL_BOOT2_PSRAM_INFO_POS) != 0) {
|
||||
GLB_Config_UHS_PLL(GLB_XTAL_40M, uhsPllCfg_2000M);
|
||||
Psram_UHS_x16_Init(2000);
|
||||
Tzc_Sec_PSRAMA_Access_Release();
|
||||
|
||||
bflb_ef_ctrl_get_device_info(&chip_info);
|
||||
if (chip_info.psramInfo == UHS_32MB_PSRAM) {
|
||||
psramDefaultCfg.psramMemSize = PSRAM_MEM_SIZE_32MB;
|
||||
} else if (chip_info.psramInfo == UHS_64MB_PSRAM) {
|
||||
psramDefaultCfg.psramMemSize = PSRAM_MEM_SIZE_64MB;
|
||||
} else {
|
||||
return 2;
|
||||
}
|
||||
|
||||
/* Flush i-cache in case branch prediction logic is wrong when
|
||||
psram is not inited by hal_boot2_custom but cpu has already prefetch psram */
|
||||
__ISB();
|
||||
//init uhs PLL; Must open uhs pll first, and then initialize uhs psram
|
||||
GLB_Config_UHS_PLL(GLB_XTAL_40M, uhsPllCfg_2000M);
|
||||
//init uhs psram ;
|
||||
// Psram_UHS_x16_Init(Clock_Peripheral_Clock_Get(BL_PERIPHERAL_CLOCK_PSRAMA) / 1000000);
|
||||
Psram_UHS_x16_Init_Override(&psramDefaultCfg);
|
||||
Tzc_Sec_PSRAMA_Access_Release();
|
||||
#if 0
|
||||
// example: 2000Mbps typical cal values
|
||||
uhs_phy_cal_res->rl = 39;
|
||||
uhs_phy_cal_res->rdqs = 3;
|
||||
uhs_phy_cal_res->rdq = 0;
|
||||
uhs_phy_cal_res->wl = 13;
|
||||
uhs_phy_cal_res->wdqs = 4;
|
||||
uhs_phy_cal_res->wdq = 5;
|
||||
uhs_phy_cal_res->ck = 9;
|
||||
/* TODO: use uhs psram trim update */
|
||||
set_uhs_latency_r(uhs_phy_cal_res->rl);
|
||||
cfg_dqs_rx(uhs_phy_cal_res->rdqs);
|
||||
cfg_dq_rx(uhs_phy_cal_res->rdq);
|
||||
set_uhs_latency_w(uhs_phy_cal_res->wl);
|
||||
cfg_dq_drv(uhs_phy_cal_res->wdq);
|
||||
cfg_ck_cen_drv(uhs_phy_cal_res->wdq + 4, uhs_phy_cal_res->wdq + 1);
|
||||
cfg_dqs_drv(uhs_phy_cal_res->wdqs);
|
||||
// set_odt_en();
|
||||
mr_read_back();
|
||||
#endif
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -99,9 +137,8 @@ void hal_boot2_get_efuse_cfg(boot2_efuse_hw_config *efuse_cfg)
|
|||
efuse_cfg->keep_dbg_port_closed = (uint8_t)(sw_cfg0.keep_dbg_port_closed);
|
||||
efuse_cfg->boot_pin_cfg = (uint8_t)(sw_cfg0.boot_pin_cfg);
|
||||
|
||||
/* get device info */ //FixZc
|
||||
//EF_Ctrl_Get_Chip_Info((Efuse_Chip_Info_Type *)&efuse_cfg->dev_info);
|
||||
|
||||
/* get device info */
|
||||
bflb_ef_ctrl_get_device_info((bflb_efuse_device_info_type *)&efuse_cfg->dev_info);
|
||||
/* get chip id */
|
||||
//EF_Ctrl_Read_Chip_ID(efuse_cfg->chip_id);
|
||||
bflb_efuse_get_chipid(efuse_cfg->chip_id);
|
||||
|
|
@ -542,7 +579,7 @@ void ATTR_TCM_SECTION hal_boot2_release_cpu(uint32_t core, uint32_t boot_addr)
|
|||
*******************************************************************************/
|
||||
uint32_t hal_boot2_get_xip_addr(uint32_t flash_addr)
|
||||
{
|
||||
uint32_t img_offset = SF_Ctrl_Get_Flash_Image_Offset(0, SF_CTRL_FLASH_BANK0);
|
||||
uint32_t img_offset = bflb_sf_ctrl_get_flash_image_offset(0, SF_CTRL_FLASH_BANK0);
|
||||
if (flash_addr >= img_offset) {
|
||||
return BL808_FLASH_XIP_BASE + (flash_addr - img_offset);
|
||||
} else {
|
||||
|
|
|
|||
|
|
@ -36,7 +36,6 @@
|
|||
#ifndef __BFLB_PORT_BOOT2_H__
|
||||
#define __BFLB_PORT_BOOT2_H__
|
||||
|
||||
#include "bl808_sflash.h"
|
||||
#include "bl808_glb.h"
|
||||
|
||||
#define HAL_PLL_CFG_MAGICCODE "PCFG"
|
||||
|
|
@ -69,6 +68,12 @@
|
|||
#define HAL_BOOT2_PSRAM_INFO_MASK (0xff0000)
|
||||
#define HAL_BOOT2_PSRAM_INFO_POS (16)
|
||||
|
||||
#define WB_4MB_PSRAM (1)
|
||||
#define UHS_32MB_PSRAM (2)
|
||||
#define UHS_64MB_PSRAM (3)
|
||||
#define WB_32MB_PSRAM (4)
|
||||
#define NONE_UHS_PSRAM (-1)
|
||||
|
||||
typedef enum {
|
||||
HAL_REBOOT_AS_BOOTPIN, /*!< reboot as bootpin level */
|
||||
HAL_REBOOT_FROM_INTERFACE, /*!< reboot from interface, download mode */
|
||||
|
|
@ -160,7 +165,7 @@ typedef struct
|
|||
|
||||
struct __attribute__((packed, aligned(4))) hal_flash_config {
|
||||
uint32_t magicCode; /*'FCFG'*/
|
||||
SPI_Flash_Cfg_Type cfg;
|
||||
spi_flash_cfg_type cfg;
|
||||
uint32_t crc32;
|
||||
};
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue