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* use nuttx libc, disable system libc
* use tlsf as default
* update lhal flash driver
* add example readme
* add flash ini for new flash tool
* add fw header for new flash tool
This commit is contained in:
jzlv 2023-01-17 20:54:15 +08:00
parent 89592fc9a3
commit 356f258e83
554 changed files with 79150 additions and 46596 deletions
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4
examples/boot2_isp/port/bl602/bflb_port_boot2.c
View file

@ -3,8 +3,6 @@
#include "bl602_glb.h"
#include "bl602_ef_ctrl.h"
#include "bl602_hbn.h"
#include "bl602_xip_sflash.h"
#include "bl602_sf_cfg.h"
#include "bl602_sf_cfg_ext.h"
#include "bl602_glb.h"
#include "bl602_xip_sflash_ext.h"
@ -502,7 +500,7 @@ void ATTR_TCM_SECTION hal_boot2_release_cpu(uint32_t core, uint32_t boot_addr)
*******************************************************************************/
uint32_t hal_boot2_get_xip_addr(uint32_t flash_addr)
{
uint32_t img_offset = SF_Ctrl_Get_Flash_Image_Offset();
uint32_t img_offset = bflb_sf_ctrl_get_flash_image_offset(0,0);
if (flash_addr >= img_offset) {
return BL602_FLASH_XIP_BASE + (flash_addr - img_offset);
} else {

3
examples/boot2_isp/port/bl602/bflb_port_boot2.h
View file

@ -36,7 +36,6 @@
#ifndef __BFLB_PORT_BOOT2_H__
#define __BFLB_PORT_BOOT2_H__
#include "bl602_sflash.h"
#include "bl602_glb.h"
#define BL_TCM_BASE BL602_TCM_BASE
@ -101,7 +100,7 @@ typedef struct
struct __attribute__((packed, aligned(4))) hal_flash_config {
uint32_t magicCode; /*'FCFG'*/
SPI_Flash_Cfg_Type cfg;
spi_flash_cfg_type cfg;
uint32_t crc32;
};

17
examples/boot2_isp/port/bl606p/bflb_port_boot2.c
View file

@ -5,7 +5,6 @@
#include "bl606p_hbn.h"
#include "bl606p_glb.h"
#include "bl606p_pds.h"
#include "bl606p_xip_sflash.h"
#include "bl606p_tzc_sec.h"
#include "bflb_gpio.h"
#include "softcrc.h"
@ -195,7 +194,7 @@ static uint16_t hal_boot2_x8_psram_calibration(int32_t *psram_dqs_win_num)
LOG_F("r ef:0x%08lx\r\n", g_efuse_cfg.psram_dqs_cfg);
before_ef = g_efuse_cfg.psram_dqs_cfg;
if ((g_efuse_cfg.psram_dqs_cfg & (0x1000)) && (g_efuse_cfg.psram_dqs_cfg != 0xffff)) {
if (g_efuse_cfg.psram_dqs_cfg != 0xffff) {
left_flag = ((g_efuse_cfg.psram_dqs_cfg & (0xf0)) >> 0x4);
right_flag = (g_efuse_cfg.psram_dqs_cfg & (0xf));
c_val = ((left_flag + right_flag) >> 0x1);
@ -225,11 +224,7 @@ static uint16_t hal_boot2_x8_psram_calibration(int32_t *psram_dqs_win_num)
c_val = ((left_flag + right_flag) >> 1);
g_efuse_cfg.psram_dqs_cfg = (((left_flag << 0x4) | (right_flag)) & (0xff));
if (bflb_ef_ctrl_get_trim_parity(g_efuse_cfg.psram_dqs_cfg, 11)) {
g_efuse_cfg.psram_dqs_cfg = ((0x1800) | (g_efuse_cfg.psram_dqs_cfg));
} else {
g_efuse_cfg.psram_dqs_cfg = ((0x1000) | (g_efuse_cfg.psram_dqs_cfg));
}
LOG_F("c ef:0x%08lx\r\n", g_efuse_cfg.psram_dqs_cfg);
*psram_dqs_win_num = right_flag - left_flag;
if (((*psram_dqs_win_num) <= 4) || ((*psram_dqs_win_num) > 0xf)) {
@ -364,11 +359,11 @@ uint32_t hal_boot2_custom(void *custom_param)
ret = hal_boot2_x8_psram_calibration(&psram_dqs_win_num);
if (ret == ERROR) {
while (1) {
printf("psram:%d\r\n", (int)psram_dqs_win_num);
LOG_F("psram:%d\r\n", (int)psram_dqs_win_num);
arch_delay_ms(500);
}
}
printf("psram:%d \r\n", (int)psram_dqs_win_num);
LOG_F("psram:%d \r\n", (int)psram_dqs_win_num);
/* Flush i-cache in case branch prediction logic is wrong when
psram is not inited by hal_boot2_custom but cpu has already prefetch psram */
@ -449,7 +444,7 @@ void hal_boot2_get_efuse_cfg(boot2_efuse_hw_config *efuse_cfg)
}
/* get device info */
//EF_Ctrl_Get_Chip_Info((Efuse_Chip_Info_Type *)&efuse_cfg->dev_info);
bflb_ef_ctrl_get_device_info((bflb_efuse_device_info_type *)&efuse_cfg->dev_info);
/* get chip id */
bflb_efuse_get_chipid(efuse_cfg->chip_id);
@ -858,7 +853,7 @@ void ATTR_TCM_SECTION hal_boot2_release_cpu(uint32_t core, uint32_t boot_addr)
*******************************************************************************/
uint32_t hal_boot2_get_xip_addr(uint32_t flash_addr)
{
uint32_t img_offset = SF_Ctrl_Get_Flash_Image_Offset(0, SF_CTRL_FLASH_BANK0);
uint32_t img_offset = bflb_sf_ctrl_get_flash_image_offset(0, SF_CTRL_FLASH_BANK0);
if (flash_addr >= img_offset) {
return BL606P_FLASH_XIP_BASE + (flash_addr - img_offset);
} else {

5
examples/boot2_isp/port/bl606p/bflb_port_boot2.h
View file

@ -36,7 +36,6 @@
#ifndef __BFLB_PORT_BOOT2_H__
#define __BFLB_PORT_BOOT2_H__
#include "bl606p_sflash.h"
#include "bl606p_glb.h"
#include "bl606p_pm.h"
@ -167,13 +166,13 @@ typedef struct
struct __attribute__((packed, aligned(4))) hal_flash_config {
uint32_t magicCode; /*'FCFG'*/
SPI_Flash_Cfg_Type cfg;
spi_flash_cfg_type cfg;
uint32_t crc32;
};
struct hal_psram_config {
uint32_t magicCode; /*'FCFG'*/
SPI_Flash_Cfg_Type cfg;
spi_flash_cfg_type cfg;
uint32_t crc32;
};

2
examples/boot2_isp/port/bl606p/blsp_boot2_iap_flash.ld
View file

@ -23,7 +23,7 @@ HeapMinSize = 0x1000; /* 4KB */
PROVIDE(__boot2_pass_param_addr = 0x62047E00);/* 0x62030000+96*1024-512 */
MEMORY
{
xip_memory (rx) : ORIGIN = 0x58000000, LENGTH = 48K
xip_memory (rx) : ORIGIN = 0x58000000, LENGTH = 58K
itcm_memory (rx) : ORIGIN = 0x62020000, LENGTH = 48K
dtcm_memory (rx) : ORIGIN = 0x6202C000, LENGTH = 4K
nocache_ram_memory (!rx) : ORIGIN = 0x2202D000, LENGTH = 84K

19
examples/boot2_isp/port/bl616/bflb_port_boot2.c
View file

@ -38,11 +38,11 @@
#include "bl616_ef_ctrl.h"
#include "bl616_hbn.h"
#include "bl616_glb.h"
#include "bl616_xip_sflash.h"
#include "bl616_tzc_sec.h"
#include "softcrc.h"
#include "bl616_psram.h"
#include "bflb_flash.h"
#include "log.h"
/****************************************************************************/ /**
* @brief init boot2 system clock
@ -228,8 +228,7 @@ static uint16_t hal_boot2_x8_psram_calibration(int32_t *psram_dqs_win_num)
printf("r ef:0x%08lx\r\n", g_efuse_cfg.psram_dqs_cfg);
#endif
before_ef = g_efuse_cfg.psram_dqs_cfg;
if ((g_efuse_cfg.psram_dqs_cfg & (0x1000)) &&
(((g_efuse_cfg.psram_dqs_cfg & 0x800) >> 11) == EF_Ctrl_Get_Trim_Parity(g_efuse_cfg.psram_dqs_cfg, 11))) {
if (g_efuse_cfg.psram_dqs_cfg != 0xffff) {
left_flag = ((g_efuse_cfg.psram_dqs_cfg & (0xf0)) >> 0x4);
right_flag = (g_efuse_cfg.psram_dqs_cfg & (0xf));
c_val = ((left_flag + right_flag) >> 0x1);
@ -263,11 +262,7 @@ static uint16_t hal_boot2_x8_psram_calibration(int32_t *psram_dqs_win_num)
// printf("window: 0x%02x ~ 0x%02x; c_val: 0x%02x; dqs:0x%04x; code num:%d\r\n", left_flag, right_flag, c_val, dqs_val[c_val], (right_flag - left_flag));
g_efuse_cfg.psram_dqs_cfg = (((left_flag << 0x4) | (right_flag)) & (0xff));
if (EF_Ctrl_Get_Trim_Parity(g_efuse_cfg.psram_dqs_cfg, 11)) {
g_efuse_cfg.psram_dqs_cfg = ((0x1800) | (g_efuse_cfg.psram_dqs_cfg));
} else {
g_efuse_cfg.psram_dqs_cfg = ((0x1000) | (g_efuse_cfg.psram_dqs_cfg));
}
#ifdef CONFIG_DEBUG
printf("c ef:0x%08lx\r\n", g_efuse_cfg.psram_dqs_cfg);
/* printf("window: 0x%02x ~ 0x%02x; c_val: 0x%02x; dqs:0x%08x; code num:%d\r\n", left_flag, right_flag, c_val, dqs_val[c_val], (right_flag - left_flag)); */
@ -282,7 +277,7 @@ static uint16_t hal_boot2_x8_psram_calibration(int32_t *psram_dqs_win_num)
}
/* to do write efuse psram dqs delay */
if (!(before_ef & 0x1fff)) {
// EF_Ctrl_Write_Psram_Trim((Efuse_Psram_Trim_Type *)&g_efuse_cfg.psram_dqs_cfg, ENABLE);
bflb_ef_ctrl_write_common_trim(NULL,"psram",g_efuse_cfg.psram_dqs_cfg,1);
}
}
return psram_id;
@ -314,11 +309,11 @@ uint32_t hal_boot2_custom(void *custom_param)
__ISB();
if (ret == ERROR) {
while (1) {
printf("psram error:%d\r\n", (int)psram_dqs_win_num);
LOG_F("psram error:%d\r\n", (int)psram_dqs_win_num);
arch_delay_ms(500);
}
}
printf("psram suss:%d \r\n", (int)psram_dqs_win_num);
LOG_F("psram suss:%d \r\n", (int)psram_dqs_win_num);
}
return ret;
@ -790,7 +785,7 @@ void ATTR_TCM_SECTION hal_boot2_release_cpu(uint32_t core, uint32_t boot_addr)
*******************************************************************************/
uint32_t hal_boot2_get_xip_addr(uint32_t flash_addr)
{
uint32_t img_offset = SF_Ctrl_Get_Flash_Image_Offset(0, SF_CTRL_FLASH_BANK0);
uint32_t img_offset = bflb_sf_ctrl_get_flash_image_offset(0, SF_CTRL_FLASH_BANK0);
if (flash_addr >= img_offset) {
return BL616_FLASH_XIP_BASE + (flash_addr - img_offset);
} else {

3
examples/boot2_isp/port/bl616/bflb_port_boot2.h
View file

@ -36,7 +36,6 @@
#ifndef __BFLB_PORT_BOOT2_H__
#define __BFLB_PORT_BOOT2_H__
#include "bl616_sflash.h"
#include "bl616_glb.h"
#include "bl616_common.h"
@ -165,7 +164,7 @@ typedef struct
struct __attribute__((packed, aligned(4))) hal_flash_config {
uint32_t magicCode; /*'FCFG'*/
SPI_Flash_Cfg_Type cfg;
spi_flash_cfg_type cfg;
uint32_t crc32;
};

3
examples/boot2_isp/port/bl702/bflb_port_boot2.c
View file

@ -3,7 +3,6 @@
#include "bl702_ef_ctrl.h"
#include "bl702_hbn.h"
#include "bl702_glb.h"
#include "bl702_xip_sflash.h"
#include "bflb_gpio.h"
#include "softcrc.h"
#include "bl702_clock.h"
@ -492,7 +491,7 @@ void ATTR_TCM_SECTION hal_boot2_release_cpu(uint32_t core, uint32_t boot_addr)
*******************************************************************************/
uint32_t hal_boot2_get_xip_addr(uint32_t flash_addr)
{
uint32_t img_offset = SF_Ctrl_Get_Flash_Image_Offset();
uint32_t img_offset = bflb_sf_ctrl_get_flash_image_offset(0,0);
if (flash_addr >= img_offset) {
return BL702_FLASH_XIP_BASE + (flash_addr - img_offset);
} else {

3
examples/boot2_isp/port/bl702/bflb_port_boot2.h
View file

@ -40,7 +40,6 @@
extern "C" {
#endif
#include "bl702_sflash.h"
#include "bl702_glb.h"
#define BL_TCM_BASE BL702_TCM_BASE
@ -105,7 +104,7 @@ typedef struct
struct __attribute__((packed, aligned(4))) hal_flash_config {
uint32_t magicCode; /*'FCFG'*/
SPI_Flash_Cfg_Type cfg;
spi_flash_cfg_type cfg;
uint32_t crc32;
};

59
examples/boot2_isp/port/bl808/bflb_port_boot2.c
View file

@ -4,12 +4,12 @@
#include "bl808_ef_cfg.h"
#include "bl808_hbn.h"
#include "bl808_glb.h"
#include "bl808_xip_sflash.h"
#include "bl808_tzc_sec.h"
#include "bflb_gpio.h"
#include "softcrc.h"
#include "bl808_psram_uhs.h"
#include "bflb_efuse.h"
#include "bl808_uhs_phy.h"
/****************************************************************************/ /**
* @brief init clock
@ -38,17 +38,55 @@ void hal_boot2_init_clock(void)
*******************************************************************************/
uint32_t hal_boot2_custom(void *custom_param)
{
extern uhs_phy_cal_res_struct* uhs_phy_cal_res;
PSRAM_UHS_Cfg_Type psramDefaultCfg = {
2000,
PSRAM_MEM_SIZE_32MB,
PSRAM_PAGE_SIZE_2KB,
PSRAM_UHS_NORMAL_TEMP,
};
bflb_efuse_device_info_type chip_info;
//EF_Ctrl_Trim_DCDC_And_LDO();
AON_Trim_USB20_RCAL();
//GLB_Readjust_LDO18IO_Vout();
if (((g_efuse_cfg.dev_info & HAL_BOOT2_PSRAM_INFO_MASK) >> HAL_BOOT2_PSRAM_INFO_POS) != 0) {
GLB_Config_UHS_PLL(GLB_XTAL_40M, uhsPllCfg_2000M);
Psram_UHS_x16_Init(2000);
Tzc_Sec_PSRAMA_Access_Release();
bflb_ef_ctrl_get_device_info(&chip_info);
if (chip_info.psramInfo == UHS_32MB_PSRAM) {
psramDefaultCfg.psramMemSize = PSRAM_MEM_SIZE_32MB;
} else if (chip_info.psramInfo == UHS_64MB_PSRAM) {
psramDefaultCfg.psramMemSize = PSRAM_MEM_SIZE_64MB;
} else {
return 2;
}
/* Flush i-cache in case branch prediction logic is wrong when
psram is not inited by hal_boot2_custom but cpu has already prefetch psram */
__ISB();
//init uhs PLL; Must open uhs pll first, and then initialize uhs psram
GLB_Config_UHS_PLL(GLB_XTAL_40M, uhsPllCfg_2000M);
//init uhs psram ;
// Psram_UHS_x16_Init(Clock_Peripheral_Clock_Get(BL_PERIPHERAL_CLOCK_PSRAMA) / 1000000);
Psram_UHS_x16_Init_Override(&psramDefaultCfg);
Tzc_Sec_PSRAMA_Access_Release();
#if 0
// example: 2000Mbps typical cal values
uhs_phy_cal_res->rl = 39;
uhs_phy_cal_res->rdqs = 3;
uhs_phy_cal_res->rdq = 0;
uhs_phy_cal_res->wl = 13;
uhs_phy_cal_res->wdqs = 4;
uhs_phy_cal_res->wdq = 5;
uhs_phy_cal_res->ck = 9;
/* TODO: use uhs psram trim update */
set_uhs_latency_r(uhs_phy_cal_res->rl);
cfg_dqs_rx(uhs_phy_cal_res->rdqs);
cfg_dq_rx(uhs_phy_cal_res->rdq);
set_uhs_latency_w(uhs_phy_cal_res->wl);
cfg_dq_drv(uhs_phy_cal_res->wdq);
cfg_ck_cen_drv(uhs_phy_cal_res->wdq + 4, uhs_phy_cal_res->wdq + 1);
cfg_dqs_drv(uhs_phy_cal_res->wdqs);
// set_odt_en();
mr_read_back();
#endif
}
return 0;
}
@ -99,9 +137,8 @@ void hal_boot2_get_efuse_cfg(boot2_efuse_hw_config *efuse_cfg)
efuse_cfg->keep_dbg_port_closed = (uint8_t)(sw_cfg0.keep_dbg_port_closed);
efuse_cfg->boot_pin_cfg = (uint8_t)(sw_cfg0.boot_pin_cfg);
/* get device info */ //FixZc
//EF_Ctrl_Get_Chip_Info((Efuse_Chip_Info_Type *)&efuse_cfg->dev_info);
/* get device info */
bflb_ef_ctrl_get_device_info((bflb_efuse_device_info_type *)&efuse_cfg->dev_info);
/* get chip id */
//EF_Ctrl_Read_Chip_ID(efuse_cfg->chip_id);
bflb_efuse_get_chipid(efuse_cfg->chip_id);
@ -542,7 +579,7 @@ void ATTR_TCM_SECTION hal_boot2_release_cpu(uint32_t core, uint32_t boot_addr)
*******************************************************************************/
uint32_t hal_boot2_get_xip_addr(uint32_t flash_addr)
{
uint32_t img_offset = SF_Ctrl_Get_Flash_Image_Offset(0, SF_CTRL_FLASH_BANK0);
uint32_t img_offset = bflb_sf_ctrl_get_flash_image_offset(0, SF_CTRL_FLASH_BANK0);
if (flash_addr >= img_offset) {
return BL808_FLASH_XIP_BASE + (flash_addr - img_offset);
} else {

9
examples/boot2_isp/port/bl808/bflb_port_boot2.h
View file

@ -36,7 +36,6 @@
#ifndef __BFLB_PORT_BOOT2_H__
#define __BFLB_PORT_BOOT2_H__
#include "bl808_sflash.h"
#include "bl808_glb.h"
#define HAL_PLL_CFG_MAGICCODE "PCFG"
@ -69,6 +68,12 @@
#define HAL_BOOT2_PSRAM_INFO_MASK (0xff0000)
#define HAL_BOOT2_PSRAM_INFO_POS (16)
#define WB_4MB_PSRAM (1)
#define UHS_32MB_PSRAM (2)
#define UHS_64MB_PSRAM (3)
#define WB_32MB_PSRAM (4)
#define NONE_UHS_PSRAM (-1)
typedef enum {
HAL_REBOOT_AS_BOOTPIN, /*!< reboot as bootpin level */
HAL_REBOOT_FROM_INTERFACE, /*!< reboot from interface, download mode */
@ -160,7 +165,7 @@ typedef struct
struct __attribute__((packed, aligned(4))) hal_flash_config {
uint32_t magicCode; /*'FCFG'*/
SPI_Flash_Cfg_Type cfg;
spi_flash_cfg_type cfg;
uint32_t crc32;
};