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[update][boot2] update boot2 demo

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jzlv 2022-12-21 20:59:44 +08:00
parent da1fa7a289
commit 4e99ee80f2
31 changed files with 5050 additions and 54 deletions
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553
examples/boot2_isp/port/bl702/bflb_port_boot2.c Normal file
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#include "bflb_port_boot2.h"
#include "bflb_flash.h"
#include "bl702_ef_ctrl.h"
#include "bl702_hbn.h"
#include "bl702_glb.h"
#include "bl702_xip_sflash.h"
#include "bflb_gpio.h"
#include "softcrc.h"
#include "bl702_clock.h"
#include "bflb_efuse.h"
/****************************************************************************/ /**
* @brief init clock
*
* @param None
*
* @return None
*
*******************************************************************************/
static void mtimer_clear_time()
{
*(volatile uint32_t *)(CLIC_CTRL_ADDR + CLIC_MTIME) = 0;
*(volatile uint32_t *)(CLIC_CTRL_ADDR + CLIC_MTIME + 4) = 0;
}
/****************************************************************************/ /**
* @brief init clock
*
* @param None
*
* @return None
*
*******************************************************************************/
void hal_boot2_init_clock(void)
{
uint32_t tmpVal;
mtimer_clear_time();
tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG1);
GLB_Set_MTimer_CLK(1, GLB_MTIMER_CLK_BCLK, Clock_System_Clock_Get(BL_SYSTEM_CLOCK_BCLK) / 1000 / 1000 - 1);
GLB_Set_UART_CLK(ENABLE, HBN_UART_CLK_96M, 0);
BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpVal);
}
/****************************************************************************/ /**
* @brief hal_boot2_custom
*
* @param custom_param
*
* @return 0
*
*******************************************************************************/
uint32_t hal_boot2_custom(void *custom_param)
{
return 0;
}
/****************************************************************************/ /**
* @brief hal_boot2_get_efuse_cfg
*
* @param efuse_cfg
*
* @return None
*
*******************************************************************************/
void hal_boot2_get_efuse_cfg(boot2_efuse_hw_config *efuse_cfg)
{
uint32_t tmp;
uint32_t rootClk;
uint8_t hdiv = 0, bdiv = 0;
/* save bclk fclk div and root clock sel */
bdiv = GLB_Get_BCLK_Div();
hdiv = GLB_Get_HCLK_Div();
rootClk = BL_RD_REG(HBN_BASE, HBN_GLB);
/* change root clock to rc32m for efuse operation */
HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_RC32M);
/* Get sign and aes type*/
//EF_Ctrl_Read_Secure_Boot((EF_Ctrl_Sign_Type *)efuse_cfg->sign, (EF_Ctrl_SF_AES_Type *)efuse_cfg->encrypted);
bflb_efuse_read_secure_boot((uint8_t *)efuse_cfg->sign, (uint8_t *)efuse_cfg->encrypted);
/* Get hash:aes key slot 0 and slot1*/
//EF_Ctrl_Read_AES_Key(0, (uint32_t *)efuse_cfg->pk_hash_cpu0, 8);
bflb_efuse_read_aes_key(0, (uint8_t *)efuse_cfg->pk_hash_cpu0, 8);
//EF_Ctrl_Read_Chip_ID(efuse_cfg->chip_id);
bflb_efuse_get_chipid(efuse_cfg->chip_id);
/* Get HBN check sign config */
//EF_Ctrl_Read_Sw_Usage(0, &tmp);
bflb_efuse_read_sw_usage(0, &tmp);
efuse_cfg->hbn_check_sign = (tmp >> 22) & 0x01;
/* restore bclk fclk div and root clock sel */
GLB_Set_System_CLK_Div(hdiv, bdiv);
BL_WR_REG(HBN_BASE, HBN_GLB, rootClk);
__NOP();
__NOP();
__NOP();
__NOP();
}
/****************************************************************************/ /**
* @brief reset sec eng clock
*
* @param None
*
* @return None
*
*******************************************************************************/
void hal_boot2_reset_sec_eng(void)
{
GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_SEC);
GLB_Set_PKA_CLK_Sel(GLB_PKA_CLK_DLL96M);
}
/****************************************************************************/ /**
* @brief system soft reset
*
* @param None
*
* @return None
*
*******************************************************************************/
void hal_boot2_sw_system_reset(void)
{
GLB_SW_System_Reset();
}
/****************************************************************************/ /**
* @brief hal_boot2_set_psmode_status
*
* @param None
*
* @return None
*
*******************************************************************************/
void hal_boot2_set_psmode_status(uint32_t flag)
{
HBN_Set_Status_Flag(flag);
}
/****************************************************************************/ /**
* @brief hal_boot2_get_psmode_status
*
* @param None
*
* @return status flag
*
*******************************************************************************/
uint32_t hal_boot2_get_psmode_status(void)
{
return HBN_Get_Status_Flag();
}
/****************************************************************************/ /**
* @brief hal_boot2_get_user_fw
*
* @param None
*
* @return None
*
*******************************************************************************/
uint32_t hal_boot2_get_user_fw(void)
{
return BL_RD_WORD(HBN_BASE + HBN_RSV0_OFFSET);
}
/****************************************************************************/ /**
* @brief hal_boot2_clr_user_fw
*
* @param None
*
* @return None
*
*******************************************************************************/
void hal_boot2_clr_user_fw(void)
{
uint32_t *p = (uint32_t *)(HBN_BASE + HBN_RSV0_OFFSET);
*p = 0;
}
/****************************************************************************/ /**
* @brief hal_boot2_sboot_finish
*
* @param None
*
* @return None
*
*******************************************************************************/
void ATTR_TCM_SECTION hal_boot2_sboot_finish(void)
{
#if 0 //FixZc
uint32_t tmp_val;
tmp_val = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_CTRL);
tmp_val = BL_SET_REG_BITS_VAL(tmp_val, TZC_SEC_TZC_SBOOT_DONE, 0xf);
BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_CTRL, tmp_val);
#endif
}
/****************************************************************************/ /**
* @brief uart gpio init
*
* @param None
*
* @return None
*
*******************************************************************************/
void hal_boot2_uart_gpio_init(void)
{
GLB_GPIO_Type gpios[] = { GPIO_PIN_14, GPIO_PIN_15 };
GLB_GPIO_Func_Init(GPIO_FUN_UART, gpios, 2);
GLB_UART_Fun_Sel((GPIO_PIN_14 % 8), GLB_UART_SIG_FUN_UART0_TXD); // GPIO_FUN_UART1_TX
GLB_UART_Fun_Sel((GPIO_PIN_15 % 8), GLB_UART_SIG_FUN_UART0_RXD);
}
/****************************************************************************/ /**
* @brief uart gpio init
*
* @param None
*
* @return None
*
*******************************************************************************/
void hal_boot2_debug_uart_gpio_init(void)
{
GLB_GPIO_Type gpios[] = { GLB_GPIO_PIN_17 };
GLB_GPIO_Func_Init(GPIO_FUN_UART, gpios, 1);
GLB_UART_Fun_Sel((GLB_GPIO_PIN_17 % 8), GLB_UART_SIG_FUN_UART1_TXD);
}
/****************************************************************************/ /**
* @brief usb init
*
* @param None
*
* @return None
*
*******************************************************************************/
#if HAL_BOOT2_SUPPORT_USB_IAP
void hal_boot2_debug_usb_port_init(void)
{
/* must do this , or usb can not be recognized */
cpu_global_irq_disable();
cpu_global_irq_enable();
GLB_GPIO_Type gpios[] = { GLB_GPIO_PIN_7, GLB_GPIO_PIN_8 };
GLB_GPIO_Func_Init(GPIO_FUN_ANALOG, gpios, 2);
}
#endif
/****************************************************************************/ /**
* @brief uart deinit
*
* @param None
*
* @return None
*
*******************************************************************************/
void hal_boot2_debug_uart_gpio_deinit(void)
{
GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_UART0);
GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_UART1);
GLB_UART_Sig_Swap_Set(UART_SIG_SWAP_NONE);
}
/****************************************************************************/ /**
* @brief Check bootheader crc
*
* @param data: bootheader data pointer
*
* @return boot_error_code type
*
*******************************************************************************/
static uint32_t hal_boot_check_bootheader(struct hal_bootheader_t *header)
{
uint32_t crc_pass = 0;
uint32_t crc;
if (header->bootCfg.bval.crcIgnore == 1 && header->crc32 == HAL_BOOT2_DEADBEEF_VAL) {
//MSG("Crc ignored\r\n");
crc_pass = 1;
} else {
crc = BFLB_Soft_CRC32((uint8_t *)header, sizeof(struct hal_bootheader_t) - sizeof(header->crc32));
if (header->crc32 == crc) {
crc_pass = 1;
}
}
return crc_pass;
}
/****************************************************************************/ /**
* @brief Check if the input public key is the same as burned in the efuse
*
* @param g_boot_img_cfg: Boot image config pointer
* @param data: Image data pointer
*
* @return boot_error_code type
*
*******************************************************************************/
int32_t hal_boot_parse_bootheader(boot2_image_config *boot_img_cfg, uint8_t *data)
{
struct hal_bootheader_t *header = (struct hal_bootheader_t *)data;
uint32_t crc_pass = 0;
uint32_t i = 0;
uint32_t *phash = (uint32_t *)header->hash;
crc_pass = hal_boot_check_bootheader(header);
if (!crc_pass) {
//MSG_ERR("bootheader crc error\r\n");
//blsp_dump_data((uint8_t *)&crc, 4);
return 0x0204;
}
if (header->bootCfg.bval.notLoadInBoot) {
return 0x0202;
}
/* Get which CPU's img it is*/
for (i = 0; i < HAL_BOOT2_CPU_MAX; i++) {
if (0 == memcmp((void *)&header->magicCode, HAL_BOOT2_CPU0_MAGIC,
sizeof(header->magicCode))) {
break;
} else if (0 == memcmp((void *)&header->magicCode, HAL_BOOT2_CPU1_MAGIC,
sizeof(header->magicCode))) {
break;
}
}
if (i == HAL_BOOT2_CPU_MAX) {
/* No cpu img magic match */
//MSG_ERR("Magic code error\r\n");
return 0x0203;
}
if (boot_img_cfg == NULL) {
return 0;
}
boot_img_cfg->pk_src = i;
boot_img_cfg->img_valid = 0;
/* Deal with pll config */
/* Encrypt and sign */
boot_img_cfg->basic_cfg.encrypt_type = header->bootCfg.bval.encrypt_type;
boot_img_cfg->basic_cfg.sign_type = header->bootCfg.bval.sign;
boot_img_cfg->basic_cfg.key_sel = header->bootCfg.bval.key_sel;
/* Xip relative */
boot_img_cfg->basic_cfg.no_segment = header->bootCfg.bval.no_segment;
boot_img_cfg->cpu_cfg[0].cache_enable = header->bootCfg.bval.cache_enable;
boot_img_cfg->basic_cfg.aes_region_lock = header->bootCfg.bval.aes_region_lock;
//boot_img_cfg->cpu_cfg[1].halt_cpu = header->bootCfg.bval.halt_cpu1;
boot_img_cfg->cpu_cfg[0].cache_way_dis = header->bootCfg.bval.cache_way_disable;
boot_img_cfg->basic_cfg.hash_ignore = header->bootCfg.bval.hash_ignore;
/* Firmware len*/
boot_img_cfg->basic_cfg.img_len_cnt = header->img_segment_info.img_len;
/* Boot entry and flash offset */
boot_img_cfg->cpu_cfg[0].boot_entry = header->bootEntry;
boot_img_cfg->basic_cfg.group_image_offset = header->img_start.flash_offset;
boot_img_cfg->cpu_cfg[0].config_enable = 1;
boot_img_cfg->cpu_cfg[0].halt_cpu = 0;
//MSG("sign %d,encrypt:%d\r\n", boot_img_cfg->sign_type,boot_img_cfg->encrypt_type);
/* Check encrypt and sign match*/
if (g_efuse_cfg.encrypted[i] != 0) {
if (boot_img_cfg->basic_cfg.encrypt_type == 0) {
//MSG_ERR("Encrypt not fit\r\n");
return 0x0205;
}
}
if (g_efuse_cfg.sign[i] != boot_img_cfg->basic_cfg.sign_type) {
//MSG_ERR("sign not fit\r\n");
boot_img_cfg->basic_cfg.sign_type = g_efuse_cfg.sign[i];
return 0x0206;
}
if (g_ps_mode == 1 && (!g_efuse_cfg.hbn_check_sign)) {
/* In HBN Mode, if user select to ignore hash and sign*/
boot_img_cfg->basic_cfg.hash_ignore = 1;
} else if ((boot_img_cfg->basic_cfg.hash_ignore == 1 && *phash != HAL_BOOT2_DEADBEEF_VAL) ||
g_efuse_cfg.sign[i] != 0) {
/* If signed or user not really want to ignore, hash can't be ignored*/
boot_img_cfg->basic_cfg.hash_ignore = 0;
}
if (g_user_hash_ignored) {
boot_img_cfg->basic_cfg.hash_ignore = 1;
}
arch_memcpy_fast(boot_img_cfg->basic_cfg.hash, header->hash, sizeof(header->hash));
if (boot_img_cfg->basic_cfg.img_len_cnt == 0) {
return 0x0207;
}
return 0;
}
/****************************************************************************/ /**
* @brief clean cache
*
* @param
*
* @return cache set result
*
*******************************************************************************/
void ATTR_TCM_SECTION hal_boot2_clean_cache(void)
{
/* no need clean again since hal_boot2_set_cache will also clean
unused way,and bl702 no data cache except psram */
}
/****************************************************************************/ /**
* @brief set cache
*
* @param cont_read: continue read mode
* boot_img_cfg: cache set param
*
* @return cache set result
*
*******************************************************************************/
BL_Err_Type ATTR_TCM_SECTION hal_boot2_set_cache(uint8_t cont_read, boot2_image_config *boot_img_cfg)
{
return bflb_flash_set_cache(cont_read, boot_img_cfg->cpu_cfg[0].cache_enable,
boot_img_cfg->cpu_cfg[0].cache_way_dis,
boot_img_cfg->basic_cfg.group_image_offset);
}
/****************************************************************************/ /**
* @brief get the ram image name and count
*
* @param img_name: ram image name in partition
* @param ram_img_cnt: ram image count that support boot from flash
*
* @return None
*
*******************************************************************************/
void hal_boot2_get_ram_img_cnt(char *img_name[], uint32_t *ram_img_cnt)
{
*ram_img_cnt = 0;
}
/****************************************************************************/ /**
* @brief get the ram image info
*
* @param data: bootheader information
* @param image_offset: ram image offset in flash(from of bootheader)
* @param img_len: ram image length
* @param hash: pointer to hash pointer
*
* @return None
*
*******************************************************************************/
void hal_boot2_get_img_info(uint8_t *data, uint32_t *image_offset, uint32_t *img_len, uint8_t **hash)
{
*img_len = 0;
}
/****************************************************************************/ /**
* @brief release other cpu to boot up
*
* @param core: core number
* @param boot_addr: boot address
*
* @return None
*
*******************************************************************************/
void ATTR_TCM_SECTION hal_boot2_release_cpu(uint32_t core, uint32_t boot_addr)
{
}
/****************************************************************************/ /**
* @brief get xip address according to flash addr
*
* @param flash_addr: flash address
*
* @return XIP Address
*
*******************************************************************************/
uint32_t hal_boot2_get_xip_addr(uint32_t flash_addr)
{
uint32_t img_offset = SF_Ctrl_Get_Flash_Image_Offset();
if (flash_addr >= img_offset) {
return BL702_FLASH_XIP_BASE + (flash_addr - img_offset);
} else {
return 0;
}
}
/****************************************************************************/ /**
* @brief get multi-group count
*
* @param None
*
* @return 1 for multi-group 0 for not
*
*******************************************************************************/
uint32_t hal_boot2_get_grp_count(void)
{
return 1;
}
/****************************************************************************/ /**
* @brief get cpu count
*
* @param None
*
* @return 1 for multi-group 0 for not
*
*******************************************************************************/
uint32_t hal_boot2_get_cpu_count(void)
{
return 1;
}
/****************************************************************************/ /**
* @brief get cpu count
*
* @param None
*
* @return 1 for multi-group 0 for not
*
*******************************************************************************/
uint32_t ATTR_TCM_SECTION hal_boot2_get_feature_flag(void)
{
return HAL_BOOT2_SP_FLAG;
}
/****************************************************************************/ /**
* @brief get boot header offset
*
* @param None
*
* @return bootheader offset
*
*******************************************************************************/
uint32_t hal_boot2_get_bootheader_offset(void)
{
return 0x00;
}

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examples/boot2_isp/port/bl702/bflb_port_boot2.h Normal file
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/**
* *****************************************************************************
* @file bflb_port_boot2.h
* @version 0.1
* @date 2022-12-13
* @brief
* *****************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* *****************************************************************************
*/
#ifndef __BFLB_PORT_BOOT2_H__
#define __BFLB_PORT_BOOT2_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "bl702_sflash.h"
#include "bl702_glb.h"
#define BL_TCM_BASE BL702_TCM_BASE
#define BL_SYS_CLK_PLL GLB_SYS_CLK_DLL144M
#define BL_SFLASH_CLK GLB_SFLASH_CLK_72M
#define HAL_PLL_CFG_MAGICCODE "PCFG"
#define HAL_BOOT2_PK_HASH_SIZE 256 / 8
#define HAL_BOOT2_IMG_HASH_SIZE 256 / 8
#define HAL_BOOT2_ECC_KEYXSIZE 256 / 8
#define HAL_BOOT2_ECC_KEYYSIZE 256 / 8
#define HAL_BOOT2_SIGN_MAXSIZE (2048 / 8)
#define HAL_BOOT2_DEADBEEF_VAL 0xdeadbeef
#define HAL_BOOT2_CPU0_MAGIC "BFNP"
#define HAL_BOOT2_CPU1_MAGIC "BFAP"
#define HAL_BOOT2_CP_FLAG 0x02
#define HAL_BOOT2_MP_FLAG 0x01
#define HAL_BOOT2_SP_FLAG 0x00
#define HAL_BOOT2_SUPPORT_DECOMPRESS 1 /* 1 support decompress, 0 not support */
#define HAL_BOOT2_SUPPORT_USB_IAP 0 /* 1 support decompress, 0 not support */
#define HAL_BOOT2_SUPPORT_EFLASH_LOADER_RAM 1 /* 1 support decompress, 0 not support */
#define HAL_BOOT2_SUPPORT_EFLASH_LOADER_FLASH 1 /* 1 support decompress, 0 not support */
#define HAL_BOOT2_SUPPORT_SIGN_ENCRYPT 1 /* 1 support sign and encrypt, 0 not support */
#define HAL_BOOT2_CPU_GROUP_MAX 1
#define HAL_BOOT2_CPU_MAX 1
#define HAL_BOOT2_RAM_IMG_COUNT_MAX 0
#define HAL_BOOT2_FW_IMG_OFFSET_AFTER_HEADER 4 * 1024
#define HAL_BOOT2_MFG_START_REQUEST_OFFSET 8 * 1024
#define CLIC_CTRL_ADDR 0x02000000UL
#define CLIC_HART0_ADDR 0x02800000UL
#define CLIC_MSIP 0x0000
#define CLIC_MSIP_size 0x4
#define CLIC_MTIMECMP 0x4000
#define CLIC_MTIMECMP_size 0x8
#define CLIC_MTIME 0xBFF8
#define CLIC_MTIME_size 0x8
#define CLIC_INTIP 0x000
#define CLIC_INTIE 0x400
#define CLIC_INTCFG 0x800
#define CLIC_CFG 0xc00
typedef struct
{
uint32_t encrypted[HAL_BOOT2_CPU_GROUP_MAX];
uint32_t sign[HAL_BOOT2_CPU_GROUP_MAX];
uint8_t hbn_check_sign;
uint8_t rsvd[1];
uint8_t chip_id[8];
uint32_t pk_hash_cpu0[HAL_BOOT2_PK_HASH_SIZE];
uint32_t pk_hash_cpu1[HAL_BOOT2_PK_HASH_SIZE];
uint8_t uart_download_cfg;
uint8_t sf_pin_cfg;
uint8_t keep_dbg_port_closed;
uint8_t boot_pin_cfg;
} boot2_efuse_hw_config;
struct __attribute__((packed, aligned(4))) hal_flash_config {
uint32_t magicCode; /*'FCFG'*/
SPI_Flash_Cfg_Type cfg;
uint32_t crc32;
};
typedef struct
{
uint8_t xtal_type;
uint8_t pll_clk;
uint8_t hclk_div;
uint8_t bclk_div;
uint8_t flash_clk_type;
uint8_t flash_clk_div;
uint8_t rsvd[2];
} hal_sys_clk_config;
typedef struct
{
uint32_t magicCode; /*'PCFG'*/
hal_sys_clk_config cfg;
uint32_t crc32;
} hal_pll_config;
struct __attribute__((packed, aligned(4))) hal_basic_cfg_t {
uint32_t sign_type : 2; /* [1: 0] for sign */
uint32_t encrypt_type : 2; /* [3: 2] for encrypt */
uint32_t key_sel : 2; /* [5: 4] key slot */
uint32_t xts_mode : 1; /* [6] for xts mode */
uint32_t aes_region_lock : 1; /* [7] rsvd */
uint32_t no_segment : 1; /* [8] no segment info */
uint32_t boot2_enable : 1; /* [9] boot2 enable */
uint32_t boot2_rollback : 1; /* [10] boot2 rollback */
uint32_t cpu_master_id : 4; /* [14: 11] master id */
uint32_t notload_in_bootrom : 1; /* [15] notload in bootrom */
uint32_t crc_ignore : 1; /* [16] ignore crc */
uint32_t hash_ignore : 1; /* [17] hash ignore */
uint32_t power_on_mm : 1; /* [18] power on mm */
uint32_t em_sel : 3; /* [21: 19] em_sel */
uint32_t cmds_en : 1; /* [22] command spliter enable */
uint32_t cmds_wrap_mode : 2; /* [24: 23] cmds wrap mode */
uint32_t cmds_wrap_len : 4; /* [28: 25] cmds wrap len */
uint32_t icache_invalid : 1; /* [29] icache invalid */
uint32_t dcache_invalid : 1; /* [30] dcache invalid */
uint32_t fpga_halt_release : 1; /* [31] FPGA halt release function */
uint32_t group_image_offset; /* flash controller offset */
uint32_t aes_region_len; /* aes region length */
uint32_t img_len_cnt; /* image length or segment count */
uint32_t hash[8]; /* hash of the image */
};
struct __attribute__((packed, aligned(4))) hal_cpu_cfg_t {
uint8_t config_enable; /* coinfig this cpu */
uint8_t halt_cpu; /* halt this cpu */
uint8_t cache_enable : 1; /* cache setting */
uint8_t cache_wa : 1; /* cache setting */
uint8_t cache_wb : 1; /* cache setting */
uint8_t cache_wt : 1; /* cache setting */
uint8_t cache_way_dis : 4; /* cache setting */
uint8_t rsvd;
uint32_t image_address_offset; /* image address on flash */
uint32_t boot_entry; /* entry point of the m0 image */
uint32_t msp_val; /* msp value */
};
struct hal_bootheader_t {
uint32_t magicCode; /*'BFXP'*/
uint32_t rivison;
struct hal_flash_config flash_cfg;
hal_pll_config clk_cfg;
__PACKED_UNION
{
__PACKED_STRUCT
{
uint32_t sign : 2; /* [1: 0] for sign*/
uint32_t encrypt_type : 2; /* [3: 2] for encrypt */
uint32_t key_sel : 2; /* [5: 4] for key sel in boot interface*/
uint32_t rsvd6_7 : 2; /* [7: 6] for encrypt*/
uint32_t no_segment : 1; /* [8] no segment info */
uint32_t cache_enable : 1; /* [9] for cache */
uint32_t notLoadInBoot : 1; /* [10] not load this img in bootrom */
uint32_t aes_region_lock : 1; /* [11] aes region lock */
uint32_t cache_way_disable : 4; /* [15: 12] cache way disable info*/
uint32_t crcIgnore : 1; /* [16] ignore crc */
uint32_t hash_ignore : 1; /* [17] hash crc */
uint32_t halt_cpu1 : 1; /* [18] halt ap */
uint32_t rsvd19_31 : 13; /* [31:19] rsvd */
}
bval;
uint32_t wval;
}
bootCfg;
__PACKED_UNION
{
uint32_t segment_cnt;
uint32_t img_len;
}
img_segment_info;
uint32_t bootEntry; /* entry point of the image*/
__PACKED_UNION
{
uint32_t ram_addr;
uint32_t flash_offset;
}
img_start;
uint8_t hash[HAL_BOOT2_IMG_HASH_SIZE]; /*hash of the image*/
uint32_t rsv1;
uint32_t rsv2;
uint32_t crc32;
};
typedef struct
{
uint8_t img_valid;
uint8_t pk_src;
uint8_t rsvd[2];
struct hal_basic_cfg_t basic_cfg;
struct hal_cpu_cfg_t cpu_cfg[HAL_BOOT2_CPU_MAX];
uint8_t aes_iv[16 + 4]; //iv in boot header
uint8_t eckye_x[HAL_BOOT2_ECC_KEYXSIZE]; //ec key in boot header
uint8_t eckey_y[HAL_BOOT2_ECC_KEYYSIZE]; //ec key in boot header
uint8_t eckey_x2[HAL_BOOT2_ECC_KEYXSIZE]; //ec key in boot header
uint8_t eckey_y2[HAL_BOOT2_ECC_KEYYSIZE]; //ec key in boot header
uint8_t signature[HAL_BOOT2_SIGN_MAXSIZE]; //signature in boot header
uint8_t signature2[HAL_BOOT2_SIGN_MAXSIZE]; //signature in boot header
} boot2_image_config;
extern boot2_efuse_hw_config g_efuse_cfg;
extern uint8_t g_ps_mode;
extern uint32_t g_user_hash_ignored;
extern struct device *dev_check_hash;
void hal_boot2_init_clock(void);
uint32_t hal_boot2_custom(void *custom_param);
void hal_boot2_reset_sec_eng(void);
void hal_boot2_sw_system_reset(void);
void hal_boot2_set_psmode_status(uint32_t flag);
uint32_t hal_boot2_get_psmode_status(void);
uint32_t hal_boot2_get_user_fw(void);
void hal_boot2_clr_user_fw(void);
void hal_boot2_get_efuse_cfg(boot2_efuse_hw_config *efuse_cfg);
int32_t hal_boot2_get_clk_cfg(hal_pll_config *cfg);
void hal_boot2_sboot_finish(void);
void hal_boot2_uart_gpio_init(void);
void hal_boot2_debug_uart_gpio_init(void);
#if HAL_BOOT2_SUPPORT_USB_IAP
void hal_boot2_debug_usb_port_init(void);
#endif
void hal_boot2_debug_uart_gpio_deinit(void);
int32_t hal_boot_parse_bootheader(boot2_image_config *boot_img_cfg, uint8_t *data);
void hal_boot2_clean_cache(void);
BL_Err_Type hal_boot2_set_cache(uint8_t cont_read, boot2_image_config *boot_img_cfg);
void hal_boot2_get_ram_img_cnt(char *img_name[], uint32_t *ram_img_cnt);
void hal_boot2_get_img_info(uint8_t *data, uint32_t *image_offset, uint32_t *img_len, uint8_t **hash);
void hal_boot2_release_cpu(uint32_t core, uint32_t boot_addr);
uint32_t hal_boot2_get_xip_addr(uint32_t flash_addr);
uint32_t hal_boot2_get_grp_count(void);
uint32_t hal_boot2_get_cpu_count(void);
uint32_t hal_boot2_get_feature_flag(void);
uint32_t hal_boot2_get_bootheader_offset(void);
#ifdef __cplusplus
}
#endif
#endif

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examples/boot2_isp/port/bl702/blsp_boot2_iap_flash.ld Normal file
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@ -0,0 +1,209 @@
/****************************************************************************************
* @file map.txt
*
* @brief This file is the map file (gnuarm or armgcc).
*
* Copyright (C) BouffaloLab 2018
*
****************************************************************************************
*/
/* configure the CPU type */
OUTPUT_ARCH( "riscv" )
/* link with the standard c library */
INPUT(-lc)
/* link with the standard GCC library */
INPUT(-lgcc)
/* configure the entry point */
ENTRY(__start)
StackSize = 0x1000; /* 4KB */
HeapSize = 0x0; /* 0KB */
PROVIDE(__boot2_pass_param_addr = 0x4202DC00);
MEMORY
{
xip_memory (rx) : ORIGIN = 0x23000000, LENGTH = 64K
itcm_memory (rx) : ORIGIN = 0x22014000, LENGTH = 16K
dtcm_memory (rx) : ORIGIN = 0x42018000, LENGTH = 4K
ram_memory (!rx) : ORIGIN = 0x42019000/*0x42020000*/, LENGTH = 88K
}
SECTIONS
{
PROVIDE(__metal_chicken_bit = 0);
.text :
{
. = ALIGN(4);
__text_code_start__ = .;
KEEP (*(SORT_NONE(.init)))
KEEP (*(SORT_NONE(.vector)))
KEEP (*(.text.metal.init.enter))
/* section information for usb desc */
. = ALIGN(4);
_usb_desc_start = .;
KEEP(*(usb_desc))
. = ALIGN(4);
_usb_desc_end = .;
*(EXCLUDE_FILE ( *bl702_uart*.o* *hal_uart*.o* ) .text*)
*(.rodata)
*(.rodata.*)
*(.srodata)
*(.srodata.*)
. = ALIGN(4);
__text_code_end__ = .;
} > xip_memory
. = ALIGN(4);
__itcm_load_addr = .;
.itcm_region : AT (__itcm_load_addr)
{
. = ALIGN(4);
__tcm_code_start__ = .;
*(.tcm_code.*)
*(.tcm_const.*)
*(.sclock_rlt_code.*)
*(.sclock_rlt_const.*)
*bl702_romapi*.o*(.text)
*bl702_romapi*.o*(.text.*)
*bl702_romapi*.o*(.rodata)
*bl702_romapi*.o*(.rodata.*)
*bl702_romapi*.o*(.srodata)
*bl702_romapi*.o*(.srodata.*)
*bl702_uart*.o* (.text*)
*hal_uart*.o* (.text*)
. = ALIGN(4);
__tcm_code_end__ = .;
} > itcm_memory
__dtcm_load_addr = __itcm_load_addr + SIZEOF(.itcm_region);
.dtcm_region : AT (__dtcm_load_addr)
{
. = ALIGN(4);
__tcm_data_start__ = .;
*(.tcm_data)
/* *finger_print.o(.data*) */
. = ALIGN(4);
__tcm_data_end__ = .;
} > dtcm_memory
/* .heap_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of heap sections, and assign
* values to heap symbols later */
.heap_dummy (NOLOAD):
{
. = ALIGN(0x4);
. = . + HeapSize;
. = ALIGN(0x4);
} > dtcm_memory
__HeapBase = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory) - StackSize - HeapSize;
__HeapSize = HeapSize;
__HeapLimit = __HeapBase + __HeapSize;
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__HeapBase >= __tcm_data_end__, "region RAM overflowed with stack")
/*************************************************************************/
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy (NOLOAD):
{
. = ALIGN(0x4);
. = . + StackSize;
. = ALIGN(0x4);
} > dtcm_memory
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory);
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __tcm_data_end__, "region RAM overflowed with stack")
/*************************************************************************/
__system_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region);
.system_ram_data_region : AT (__system_ram_load_addr)
{
. = ALIGN(4);
__system_ram_data_start__ = .;
*(.system_ram)
. = ALIGN(4);
__system_ram_data_end__ = .;
} > ram_memory
__ram_load_addr = __system_ram_load_addr + SIZEOF(.system_ram_data_region);
/* Data section */
RAM_DATA : AT (__ram_load_addr)
{
. = ALIGN(4);
__ram_data_start__ = .;
PROVIDE( __global_pointer$ = . + 0x800 );
*(.data)
*(.data.*)
*(.sdata)
*(.sdata.*)
*(.sdata2)
*(.sdata2.*)
. = ALIGN(4);
__ram_data_end__ = .;
} > ram_memory
.bss (NOLOAD) :AT(__bss_start__)
{
. = ALIGN(4);
__bss_start__ = .;
*(.bss*)
*(.sbss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
} > ram_memory
.noinit_data (NOLOAD) :AT(__noinit_data_start__)
{
. = ALIGN(4);
__noinit_data_start__ = .;
*(.noinit_data*)
. = ALIGN(4);
__noinit_data_end__ = .;
} > ram_memory
.nocache_noinit_ram_region (NOLOAD) : AT(__nocache_ram_data_start__)
{
. = ALIGN(4);
__nocache_ram_data_start__ = .;
*(.nocache_noinit_ram)
. = ALIGN(4);
__nocache_ram_data_end__ = .;
} > ram_memory
}