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[feat][adc] add adc irq function

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This commit is contained in:
jzlv 2021-07-26 10:43:17 +08:00
parent cc7e3b5d84
commit 56dca947fe
2 changed files with 59 additions and 7 deletions
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11
drivers/bl702_driver/hal_drv/inc/hal_adc.h
View file

@ -41,12 +41,21 @@ enum adc_index_type {
ADC_MAX_INDEX ADC_MAX_INDEX
}; };
enum ADC_event_type { enum adc_event_type {
ADC_EVENT_FIFO_READY, ADC_EVENT_FIFO_READY,
ADC_EVENT_OVERRUN, ADC_EVENT_OVERRUN,
ADC_EVENT_UNDERRUN, ADC_EVENT_UNDERRUN,
ADC_EVEN_INT_POS_SATURATION, ADC_EVEN_INT_POS_SATURATION,
ADC_EVEN_INT_NEG_SATURATION, ADC_EVEN_INT_NEG_SATURATION,
ADC_EVEN_MAX,
};
enum adc_it_type {
ADC_EVENT_FIFO_READY_IT = 1 << 0,
ADC_EVENT_OVERRUN_IT = 1 << 1,
ADC_EVENT_UNDERRUN_IT = 1 << 2,
ADC_EVEN_INT_POS_SATURATION_IT = 1 << 3,
ADC_EVEN_INT_NEG_SATURATION_IT = 1 << 4,
}; };
#define adc_channel_start(dev) device_control(dev, DEVICE_CTRL_ADC_CHANNEL_START, NULL) #define adc_channel_start(dev) device_control(dev, DEVICE_CTRL_ADC_CHANNEL_START, NULL)

55
drivers/bl702_driver/hal_drv/src/hal_adc.c
View file

@ -28,6 +28,10 @@
#include "bl702_adc.h" #include "bl702_adc.h"
#include "adc_config.h" #include "adc_config.h"
#ifdef BSP_USING_ADC0
static void ADC_IRQ(void);
#endif
static adc_device_t adcx_device[ADC_MAX_INDEX] = { static adc_device_t adcx_device[ADC_MAX_INDEX] = {
#ifdef BSP_USING_ADC0 #ifdef BSP_USING_ADC0
ADC0_CONFIG, ADC0_CONFIG,
@ -119,6 +123,10 @@ int adc_open(struct device *dev, uint16_t oflag)
adc_fifo_cfg.fifoThreshold = adc_device->fifo_threshold; adc_fifo_cfg.fifoThreshold = adc_device->fifo_threshold;
#ifdef BSP_USING_ADC0
Interrupt_Handler_Register(GPADC_DMA_IRQn, ADC_IRQ);
#endif
ADC_Disable(); ADC_Disable();
ADC_Enable(); ADC_Enable();
@ -155,13 +163,48 @@ int adc_control(struct device *dev, int cmd, void *args)
adc_device_t *adc_device = (adc_device_t *)dev; adc_device_t *adc_device = (adc_device_t *)dev;
adc_channel_cfg_t *adc_channel_cfg = (adc_channel_cfg_t *)args; adc_channel_cfg_t *adc_channel_cfg = (adc_channel_cfg_t *)args;
uint8_t rlt = 0; uint8_t rlt = 0;
uint32_t mask = 0;
switch (cmd) { switch (cmd) {
case DEVICE_CTRL_SET_INT /* constant-expression */: case DEVICE_CTRL_SET_INT /* constant-expression */:
mask = (uint32_t)args;
if (mask & ADC_EVENT_FIFO_READY_IT) {
ADC_IntMask(ADC_EVENT_FIFO_READY, UNMASK);
}
if (mask & ADC_EVENT_OVERRUN_IT) {
ADC_IntMask(ADC_EVENT_OVERRUN, UNMASK);
}
if (mask & ADC_EVENT_UNDERRUN_IT) {
ADC_IntMask(ADC_EVENT_UNDERRUN, UNMASK);
}
if (mask & ADC_EVEN_INT_POS_SATURATION_IT) {
ADC_IntMask(ADC_EVEN_INT_POS_SATURATION, UNMASK);
}
if (mask & ADC_EVEN_INT_NEG_SATURATION_IT) {
ADC_IntMask(ADC_EVEN_INT_NEG_SATURATION, UNMASK);
}
NVIC_EnableIRQ(GPADC_DMA_IRQn);
break; break;
case DEVICE_CTRL_CLR_INT /* constant-expression */: case DEVICE_CTRL_CLR_INT /* constant-expression */:
mask = (uint32_t)args;
if (mask & ADC_EVENT_FIFO_READY_IT) {
ADC_IntMask(ADC_EVENT_FIFO_READY, MASK);
}
if (mask & ADC_EVENT_OVERRUN_IT) {
ADC_IntMask(ADC_EVENT_OVERRUN, MASK);
}
if (mask & ADC_EVENT_UNDERRUN_IT) {
ADC_IntMask(ADC_EVENT_UNDERRUN, MASK);
}
if (mask & ADC_EVEN_INT_POS_SATURATION_IT) {
ADC_IntMask(ADC_EVEN_INT_POS_SATURATION, MASK);
}
if (mask & ADC_EVEN_INT_NEG_SATURATION_IT) {
ADC_IntMask(ADC_EVEN_INT_NEG_SATURATION, MASK);
}
break; break;
@ -232,7 +275,7 @@ int adc_control(struct device *dev, int cmd, void *args)
*/ */
int adc_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size) int adc_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size)
{ {
if (dev->oflag & DEVICE_OFLAG_STREAM_RX) { if (dev->oflag & DEVICE_OFLAG_STREAM_RX || dev->oflag & DEVICE_OFLAG_INT_RX) {
while (ADC_Get_FIFO_Count() == 0) while (ADC_Get_FIFO_Count() == 0)
; ;
@ -302,28 +345,28 @@ void adc_isr(adc_device_t *handle)
return; return;
if (ADC_GetIntStatus(ADC_INT_POS_SATURATION) == SET && ADC_IntGetMask(ADC_INT_POS_SATURATION) == UNMASK) { if (ADC_GetIntStatus(ADC_INT_POS_SATURATION) == SET && ADC_IntGetMask(ADC_INT_POS_SATURATION) == UNMASK) {
handle->parent.callback(&handle->parent, NULL, 0, ADC_EVEN_INT_POS_SATURATION);
ADC_IntClr(ADC_INT_POS_SATURATION); ADC_IntClr(ADC_INT_POS_SATURATION);
handle->parent.callback(&handle->parent, NULL, 0, ADC_INT_POS_SATURATION);
} }
if (ADC_GetIntStatus(ADC_INT_NEG_SATURATION) == SET && ADC_IntGetMask(ADC_INT_NEG_SATURATION) == UNMASK) { if (ADC_GetIntStatus(ADC_INT_NEG_SATURATION) == SET && ADC_IntGetMask(ADC_INT_NEG_SATURATION) == UNMASK) {
handle->parent.callback(&handle->parent, NULL, 0, ADC_EVEN_INT_NEG_SATURATION);
ADC_IntClr(ADC_INT_NEG_SATURATION); ADC_IntClr(ADC_INT_NEG_SATURATION);
handle->parent.callback(&handle->parent, NULL, 0, ADC_INT_NEG_SATURATION);
} }
if (ADC_GetIntStatus(ADC_INT_FIFO_UNDERRUN) == SET && ADC_IntGetMask(ADC_INT_FIFO_UNDERRUN) == UNMASK) { if (ADC_GetIntStatus(ADC_INT_FIFO_UNDERRUN) == SET && ADC_IntGetMask(ADC_INT_FIFO_UNDERRUN) == UNMASK) {
handle->parent.callback(&handle->parent, NULL, 0, ADC_EVENT_UNDERRUN);
ADC_IntClr(ADC_INT_FIFO_UNDERRUN); ADC_IntClr(ADC_INT_FIFO_UNDERRUN);
handle->parent.callback(&handle->parent, NULL, 0, ADC_INT_FIFO_UNDERRUN);
} }
if (ADC_GetIntStatus(ADC_INT_FIFO_OVERRUN) == SET && ADC_IntGetMask(ADC_INT_FIFO_OVERRUN) == UNMASK) { if (ADC_GetIntStatus(ADC_INT_FIFO_OVERRUN) == SET && ADC_IntGetMask(ADC_INT_FIFO_OVERRUN) == UNMASK) {
handle->parent.callback(&handle->parent, NULL, 0, ADC_EVENT_OVERRUN);
ADC_IntClr(ADC_INT_FIFO_OVERRUN); ADC_IntClr(ADC_INT_FIFO_OVERRUN);
handle->parent.callback(&handle->parent, NULL, 0, ADC_INT_FIFO_OVERRUN);
} }
if (ADC_GetIntStatus(ADC_INT_FIFO_READY) == SET && ADC_IntGetMask(ADC_INT_FIFO_READY) == UNMASK) { if (ADC_GetIntStatus(ADC_INT_FIFO_READY) == SET && ADC_IntGetMask(ADC_INT_FIFO_READY) == UNMASK) {
handle->parent.callback(&handle->parent, NULL, 0, ADC_EVENT_FIFO_READY);
ADC_IntClr(ADC_INT_FIFO_READY); ADC_IntClr(ADC_INT_FIFO_READY);
handle->parent.callback(&handle->parent, NULL, 0, ADC_INT_FIFO_READY);
} }
} }
#ifdef BSP_USING_ADC0 #ifdef BSP_USING_ADC0