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[update][drivers] update bl602 and bl702 std driver

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This commit is contained in:
jzlv 2021-12-10 11:34:49 +08:00
parent 48fbbbbc65
commit 5a29530fbe
12 changed files with 1140 additions and 1175 deletions
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8
drivers/bl602_driver/hal_drv/src/hal_uart.c
View file

@ -268,6 +268,7 @@ int uart_control(struct device *dev, int cmd, void *args)
*/
int uart_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t size)
{
int ret = -1;
uart_device_t *uart_device = (uart_device_t *)dev;
if (dev->oflag & DEVICE_OFLAG_DMA_TX) {
@ -278,14 +279,13 @@ int uart_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t si
}
if (uart_device->id == 0) {
dma_reload(dma_ch, (uint32_t)buffer, (uint32_t)DMA_ADDR_UART0_TDR, size);
ret = dma_reload(dma_ch, (uint32_t)buffer, (uint32_t)DMA_ADDR_UART0_TDR, size);
dma_channel_start(dma_ch);
} else if (uart_device->id == 1) {
dma_reload(dma_ch, (uint32_t)buffer, (uint32_t)DMA_ADDR_UART1_TDR, size);
ret = dma_reload(dma_ch, (uint32_t)buffer, (uint32_t)DMA_ADDR_UART1_TDR, size);
dma_channel_start(dma_ch);
}
return 0;
return ret;
} else if (dev->oflag & DEVICE_OFLAG_INT_TX) {
return -2;
} else

2
drivers/bl602_driver/startup/GCC/entry.S
View file

@ -1,6 +1,6 @@
/* Copyright 2018 SiFive, Inc */
/* SPDX-License-Identifier: Apache-2.0 */
#include "../risc-v/Core/Include/riscv_encoding.h"
#include "risc-v/Core/Include/riscv_encoding.h"
/* This code executes before _start, which is contained inside the C library.
* In embedded systems we want to ensure that _enter, which contains the first

24
drivers/bl602_driver/std_drv/inc/bl602_gpio.h
View file

@ -145,7 +145,7 @@ typedef struct
#define GPIO0_FUN_SDIO_CLK 1
#define GPIO0_FUN_SF_D1 2
#define GPIO0_FUN_UNUSED3 3
#define GPIO0_FUN_SPI_MISO_SPI_MOSI 4
#define GPIO0_FUN_SPI_MOSI_SPI_MISO 4
#define GPIO0_FUN_UNUSED5 5
#define GPIO0_FUN_I2C_SCL 6
#define GPIO0_FUN_UART_SIG0 7
@ -158,7 +158,7 @@ typedef struct
#define GPIO1_FUN_SDIO_CMD 1
#define GPIO1_FUN_SF_D2 2
#define GPIO1_FUN_UNUSED3 3
#define GPIO1_FUN_SPI_MOSI_SPI_MISO 4
#define GPIO1_FUN_SPI_MISO_SPI_MOSI 4
#define GPIO1_FUN_UNUSED5 5
#define GPIO1_FUN_I2C_SDA 6
#define GPIO1_FUN_UART_SIG1 7
@ -197,7 +197,7 @@ typedef struct
#define GPIO4_FUN_SDIO_DAT2 1
#define GPIO4_FUN_UNUSED2 2
#define GPIO4_FUN_UNUSED3 3
#define GPIO4_FUN_SPI_MISO_SPI_MOSI 4
#define GPIO4_FUN_SPI_MOSI_SPI_MISO 4
#define GPIO4_FUN_UNUSED5 5
#define GPIO4_FUN_I2C_SCL 6
#define GPIO4_FUN_UART_SIG4 7
@ -210,7 +210,7 @@ typedef struct
#define GPIO5_FUN_SDIO_DAT3 1
#define GPIO5_FUN_UNUSED2 2
#define GPIO5_FUN_UNUSED3 3
#define GPIO5_FUN_SPI_MOSI_SPI_MISO 4
#define GPIO5_FUN_SPI_MISO_SPI_MOSI 4
#define GPIO5_FUN_UNUSED5 5
#define GPIO5_FUN_I2C_SDA 6
#define GPIO5_FUN_UART_SIG5 7
@ -249,7 +249,7 @@ typedef struct
#define GPIO8_FUN_UNUSED1 1
#define GPIO8_FUN_UNUSED2 2
#define GPIO8_FUN_UNUSED3 3
#define GPIO8_FUN_SPI_MISO_SPI_MOSI 4
#define GPIO8_FUN_SPI_MOSI_SPI_MISO 4
#define GPIO8_FUN_UNUSED5 5
#define GPIO8_FUN_I2C_SCL 6
#define GPIO8_FUN_UART_SIG0 7
@ -262,7 +262,7 @@ typedef struct
#define GPIO9_FUN_UNUSED1 1
#define GPIO9_FUN_UNUSED2 2
#define GPIO9_FUN_UNUSED3 3
#define GPIO9_FUN_SPI_MOSI_SPI_MISO 4
#define GPIO9_FUN_SPI_MISO_SPI_MOSI 4
#define GPIO9_FUN_UNUSED5 5
#define GPIO9_FUN_I2C_SDA 6
#define GPIO9_FUN_UART_SIG1 7
@ -301,7 +301,7 @@ typedef struct
#define GPIO12_FUN_UNUSED1 1
#define GPIO12_FUN_UNUSED2 2
#define GPIO12_FUN_UNUSED3 3
#define GPIO12_FUN_SPI_MISO_SPI_MOSI 4
#define GPIO12_FUN_SPI_MOSI_SPI_MISO 4
#define GPIO12_FUN_UNUSED5 5
#define GPIO12_FUN_I2C_SCL 6
#define GPIO12_FUN_UART_SIG4 7
@ -314,7 +314,7 @@ typedef struct
#define GPIO13_FUN_UNUSED1 1
#define GPIO13_FUN_UNUSED2 2
#define GPIO13_FUN_UNUSED3 3
#define GPIO13_FUN_SPI_MOSI_SPI_MISO 4
#define GPIO13_FUN_SPI_MISO_SPI_MOSI 4
#define GPIO13_FUN_UNUSED5 5
#define GPIO13_FUN_I2C_SDA 6
#define GPIO13_FUN_UART_SIG5 7
@ -353,7 +353,7 @@ typedef struct
#define GPIO16_FUN_UNUSED1 1
#define GPIO16_FUN_UNUSED2 2
#define GPIO16_FUN_UNUSED3 3
#define GPIO16_FUN_SPI_MISO_SPI_MOSI 4
#define GPIO16_FUN_SPI_MOSI_SPI_MISO 4
#define GPIO16_FUN_UNUSED5 5
#define GPIO16_FUN_I2C_SCL 6
#define GPIO16_FUN_UART_SIG0 7
@ -366,7 +366,7 @@ typedef struct
#define GPIO17_FUN_UNUSED1 1
#define GPIO17_FUN_SF_D3 2
#define GPIO17_FUN_UNUSED3 3
#define GPIO17_FUN_SPI_MOSI_SPI_MISO 4
#define GPIO17_FUN_SPI_MISO_SPI_MOSI 4
#define GPIO17_FUN_UNUSED5 5
#define GPIO17_FUN_I2C_SDA 6
#define GPIO17_FUN_UART_SIG1 7
@ -405,7 +405,7 @@ typedef struct
#define GPIO20_FUN_UNUSED1 1
#define GPIO20_FUN_SF_D0 2
#define GPIO20_FUN_UNUSED3 3
#define GPIO20_FUN_SPI_MISO_SPI_MOSI 4
#define GPIO20_FUN_SPI_MOSI_SPI_MISO 4
#define GPIO20_FUN_UNUSED5 5
#define GPIO20_FUN_I2C_SCL 6
#define GPIO20_FUN_UART_SIG4 7
@ -418,7 +418,7 @@ typedef struct
#define GPIO21_FUN_UNUSED1 1
#define GPIO21_FUN_SF_CS 2
#define GPIO21_FUN_UNUSED3 3
#define GPIO21_FUN_SPI_MOSI_SPI_MISO 4
#define GPIO21_FUN_SPI_MISO_SPI_MOSI 4
#define GPIO21_FUN_UNUSED5 5
#define GPIO21_FUN_I2C_SDA 6
#define GPIO21_FUN_UART_SIG5 7

2
drivers/bl702_driver/startup/GCC/entry.S
View file

@ -1,6 +1,6 @@
/* Copyright 2018 SiFive, Inc */
/* SPDX-License-Identifier: Apache-2.0 */
#include "../risc-v/Core/Include/riscv_encoding.h"
#include "risc-v/Core/Include/riscv_encoding.h"
/* This code executes before _start, which is contained inside the C library.
* In embedded systems we want to ensure that _enter, which contains the first

14
drivers/bl702_driver/std_drv/inc/bl702_ef_ctrl.h
View file

@ -291,20 +291,20 @@ BL_Err_Type EF_Ctrl_Read_MAC_Address(uint8_t mac[8]);
BL_Err_Type EF_Ctrl_Read_MAC_Address_Raw(uint8_t mac[7]);
void EF_Ctrl_Writelock_MAC_Address(uint8_t program);
uint8_t EF_Ctrl_Is_MAC_Address_Slot_Empty(uint8_t slot, uint8_t reload);
BL_Err_Type EF_Ctrl_Write_MAC_Address_Opt(uint8_t slot, uint8_t mac[6], uint8_t program);
BL_Err_Type EF_Ctrl_Read_MAC_Address_Opt(uint8_t slot, uint8_t mac[6], uint8_t reload);
BL_Err_Type EF_Ctrl_Write_MAC_Address_Opt(uint8_t slot, uint8_t mac[8], uint8_t program);
BL_Err_Type EF_Ctrl_Read_MAC_Address_Opt(uint8_t slot, uint8_t mac[8], uint8_t reload);
BL_Err_Type EF_Ctrl_Read_Chip_ID(uint8_t id[8]);
/*----------*/
BL_Err_Type EF_Ctrl_Get_Chip_PIDVID(uint16_t pid[1], uint16_t vid[1]);
BL_Err_Type EF_Ctrl_Get_Customer_PIDVID(uint16_t pid[1], uint16_t vid[1]);
/*----------*/
void EF_Ctrl_Read_Device_Info(Efuse_Device_Info_Type *deviceInfo);
uint8_t EF_Ctrl_Is_CapCode_Empty(uint8_t reload);
BL_Err_Type EF_Ctrl_Write_CapCode_Opt(uint8_t code, uint8_t program);
BL_Err_Type EF_Ctrl_Read_CapCode_Opt(uint8_t *code, uint8_t reload);
uint8_t EF_Ctrl_Is_CapCode_Empty(uint8_t slot, uint8_t reload);
BL_Err_Type EF_Ctrl_Write_CapCode_Opt(uint8_t slot, uint8_t code, uint8_t program);
BL_Err_Type EF_Ctrl_Read_CapCode_Opt(uint8_t slot, uint8_t *code, uint8_t reload);
uint8_t EF_Ctrl_Is_PowerOffset_Slot_Empty(uint8_t slot, uint8_t reload);
BL_Err_Type EF_Ctrl_Write_PowerOffset_Opt(uint8_t slot, int8_t pwrOffset[3], uint8_t program);
BL_Err_Type EF_Ctrl_Read_PowerOffset_Opt(uint8_t slot, int8_t pwrOffset[3], uint8_t reload);
BL_Err_Type EF_Ctrl_Write_PowerOffset_Opt(uint8_t slot, int8_t pwrOffset[2], uint8_t program);
BL_Err_Type EF_Ctrl_Read_PowerOffset_Opt(uint8_t slot, int8_t pwrOffset[2], uint8_t reload);
void EF_Ctrl_Write_AES_Key(uint8_t index, uint32_t *keyData, uint32_t len, uint8_t program);
void EF_Ctrl_Read_AES_Key(uint8_t index, uint32_t *keyData, uint32_t len);
void EF_Ctrl_Writelock_AES_Key(uint8_t index, uint8_t program);

1903
drivers/bl702_driver/std_drv/inc/bl702_gpio.h
View file

File diff suppressed because it is too large Load diff

6
drivers/bl702_driver/std_drv/inc/bl702_pds.h
View file

@ -762,7 +762,7 @@ BL_Sts_Type PDS_Get_Reset_Event(PDS_RST_EVENT_Type event);
BL_Err_Type PDS_Set_Vddcore_GPIO_IntCfg(PDS_VDDCORE_GPIO_SRC_Type src,
PDS_AON_GPIO_INT_Trigger_Type mode);
BL_Err_Type PDS_Set_Vddcore_GPIO_IntMask(BL_Mask_Type intMask);
PDS_STS_Type PDS_Get_Vddcore_GPIO_IntStatus(void);
BL_Sts_Type PDS_Get_Vddcore_GPIO_IntStatus(void);
BL_Err_Type PDS_Set_Vddcore_GPIO_IntClear(void);
/*----------*/
BL_Err_Type PDS_WAKEUP_IRQHandler_Install(void);
@ -785,7 +785,9 @@ void PDS_Auto_Time_Config(uint32_t sleepDuration);
void PDS_Auto_Enable(PDS_AUTO_POWER_DOWN_CFG_Type *powerCfg, PDS_AUTO_NORMAL_CFG_Type *normalCfg, BL_Fun_Type enable);
void PDS_Manual_Force_Turn_Off(PDS_FORCE_Type domain);
void PDS_Manual_Force_Turn_On(PDS_FORCE_Type domain);
/*----------*/;
/*----------*/
BL_Err_Type PDS_Set_Clkpll_Top_Ctrl(uint8_t vg11Sel);
/*----------*/
/*@} end of group PDS_Public_Functions */

52
drivers/bl702_driver/std_drv/src/bl702_adc.c
View file

@ -1281,65 +1281,13 @@ uint32_t TSEN_Get_V_Error(void)
*******************************************************************************/
BL_Err_Type ATTR_CLOCK_SECTION ADC_Trim_TSEN(uint16_t *tsen_offset)
{
uint8_t average_index = 0;
uint32_t v_error_sum = 0;
uint32_t tmpVal = 0;
float A1 = 0.0, A2 = 0.0, C = 0.0, delta = 0.0;
Efuse_TSEN_Refcode_Corner_Type trim;
EF_Ctrl_Read_TSEN_Trim(&trim);
if (trim.tsenRefcodeCornerEn) {
if (trim.tsenRefcodeCornerParity == EF_Ctrl_Get_Trim_Parity(trim.tsenRefcodeCorner, 12)) {
MSG("TSEN ATE Version = %d\r\n", trim.tsenRefcodeCornerVersion);
*tsen_offset = trim.tsenRefcodeCorner;
if (trim.tsenRefcodeCornerVersion == 0) {
/* debug advise by ran
* 2020.9.04
*/
//set 4000F90C[19](gpadc_mic2_diff) = 0
tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_MIC2_DIFF, 0);
BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal);
for (average_index = 0; average_index < 50; average_index++) {
v_error_sum += TSEN_Get_V_Error();
}
v_error_sum /= 50;
MSG("A1 = %d\r\n", v_error_sum);
A1 = v_error_sum;
v_error_sum = 0;
//set 4000F90C[19](gpadc_mic2_diff) = 1
tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_MIC2_DIFF, 1);
BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal);
for (average_index = 0; average_index < 50; average_index++) {
v_error_sum += TSEN_Get_V_Error();
}
v_error_sum /= 50;
MSG("A2 = %d\r\n", v_error_sum);
A2 = v_error_sum;
MSG("C = %d\r\n", *tsen_offset);
C = *tsen_offset;
delta = A2 - (7.753 / 5.62 * A1) + 2.133 / 5.62 * C + 72;
MSG("delta=A2-7.753/5.62*A1+2.133/5.62*C+72x; delta = %d\r\n", (uint16_t)delta);
*tsen_offset = delta + C;
}
return SUCCESS;
}
}

270
drivers/bl702_driver/std_drv/src/bl702_ef_ctrl.c
View file

@ -640,8 +640,7 @@ void ATTR_CLOCK_SECTION EF_Ctrl_Read_TSEN_Trim(Efuse_TSEN_Refcode_Corner_Type *t
trim->tsenRefcodeCorner = tmpVal & 0xfff;
trim->tsenRefcodeCornerParity = (tmpVal >> 12) & 0x01;
tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W1);
trim->tsenRefcodeCornerVersion = (tmpVal >> 30) & 0x01;
trim->tsenRefcodeCornerVersion = 0;
}
/****************************************************************************/ /**
@ -968,30 +967,24 @@ uint8_t EF_Ctrl_Is_MAC_Address_Slot_Empty(uint8_t slot, uint8_t reload)
* @brief Efuse write optional MAC address
*
* @param slot: MAC address slot
* @param mac[6]: MAC address buffer
* @param mac[8]: MAC address buffer
* @param program: Whether program
*
* @return SUCCESS or ERROR
*
*******************************************************************************/
BL_Err_Type EF_Ctrl_Write_MAC_Address_Opt(uint8_t slot, uint8_t mac[6], uint8_t program)
BL_Err_Type EF_Ctrl_Write_MAC_Address_Opt(uint8_t slot, uint8_t mac[8], uint8_t program)
{
uint8_t *maclow = (uint8_t *)mac;
uint8_t *machigh = (uint8_t *)(mac + 4);
uint32_t tmpVal;
uint32_t i = 0, cnt;
uint32_t tmpVal = 0;
uint32_t i = 0;
uint32_t cnt = 0;
if (slot >= 3) {
return ERROR;
}
/* Change to local order */
for (i = 0; i < 3; i++) {
tmpVal = mac[i];
mac[i] = mac[5 - i];
mac[5 - i] = tmpVal;
}
if (slot == 2) {
/* Switch to AHB clock */
EF_Ctrl_Sw_AHB_Clk_0();
@ -1009,23 +1002,29 @@ BL_Err_Type EF_Ctrl_Write_MAC_Address_Opt(uint8_t slot, uint8_t mac[6], uint8_t
BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_LOW, BL_RDWD_FRM_BYTEP(maclow));
}
/* The high 16 bits */
tmpVal = machigh[0] + (machigh[1] << 8);
cnt = 0;
/* The high 32 bits */
if (slot == 0) {
BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_HIGH, BL_RDWD_FRM_BYTEP(machigh));
} else if (slot == 1) {
BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W1, BL_RDWD_FRM_BYTEP(machigh));
} else if (slot == 2) {
BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_HIGH, BL_RDWD_FRM_BYTEP(machigh));
}
for (i = 0; i < 6; i++) {
cnt = 0;
for (i = 0; i < 8; i++) {
cnt += EF_Ctrl_Get_Byte_Zero_Cnt(mac[i]);
}
tmpVal |= ((cnt & 0x3f) << 16);
cnt &= 0x3f;
tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W2);
if (slot == 0) {
BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_HIGH, tmpVal);
tmpVal |= (cnt << 0);
} else if (slot == 1) {
BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W1, tmpVal);
tmpVal |= (cnt << 6);
} else if (slot == 2) {
BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_HIGH, tmpVal);
tmpVal |= (cnt << 12);
}
BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W2, tmpVal);
if (program) {
if (slot == 2) {
@ -1034,7 +1033,6 @@ BL_Err_Type EF_Ctrl_Write_MAC_Address_Opt(uint8_t slot, uint8_t mac[6], uint8_t
EF_Ctrl_Program_Efuse_0();
}
}
return SUCCESS;
}
@ -1042,19 +1040,20 @@ BL_Err_Type EF_Ctrl_Write_MAC_Address_Opt(uint8_t slot, uint8_t mac[6], uint8_t
* @brief Efuse read optional MAC address
*
* @param slot: MAC address slot
* @param mac[6]: MAC address buffer
* @param mac[8]: MAC address buffer
* @param reload: Whether reload
*
* @return SUCCESS or ERROR
*
*******************************************************************************/
BL_Err_Type EF_Ctrl_Read_MAC_Address_Opt(uint8_t slot, uint8_t mac[6], uint8_t reload)
BL_Err_Type EF_Ctrl_Read_MAC_Address_Opt(uint8_t slot, uint8_t mac[8], uint8_t reload)
{
uint8_t *maclow = (uint8_t *)mac;
uint8_t *machigh = (uint8_t *)(mac + 4);
uint32_t tmpVal = 0;
uint32_t i = 0;
uint32_t cnt = 0;
uint32_t crc = 0;
if (slot >= 3) {
return ERROR;
@ -1076,7 +1075,6 @@ BL_Err_Type EF_Ctrl_Read_MAC_Address_Opt(uint8_t slot, uint8_t mac[6], uint8_t r
} else if (slot == 2) {
tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_LOW);
}
BL_WRWD_TO_BYTEP(maclow, tmpVal);
if (slot == 0) {
@ -1086,23 +1084,23 @@ BL_Err_Type EF_Ctrl_Read_MAC_Address_Opt(uint8_t slot, uint8_t mac[6], uint8_t r
} else if (slot == 2) {
tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_HIGH);
}
BL_WRWD_TO_BYTEP(machigh, tmpVal);
machigh[0] = tmpVal & 0xff;
machigh[1] = (tmpVal >> 8) & 0xff;
/* Check parity */
for (i = 0; i < 6; i++) {
cnt += EF_Ctrl_Get_Byte_Zero_Cnt(mac[i]);
/* Get original parity */
tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W2);
if (slot == 0) {
crc = ((tmpVal >> 0) & 0x3f);
} else if (slot == 1) {
crc = ((tmpVal >> 6) & 0x3f);
} else if (slot == 2) {
crc = ((tmpVal >> 12) & 0x3f);
}
if ((cnt & 0x3f) == ((tmpVal >> 16) & 0x3f)) {
/* Change to network order */
for (i = 0; i < 3; i++) {
tmpVal = mac[i];
mac[i] = mac[5 - i];
mac[5 - i] = tmpVal;
}
/* Check parity */
for (i = 0; i < 8; i++) {
cnt += EF_Ctrl_Get_Byte_Zero_Cnt(mac[i]);
}
if ((cnt & 0x3f) == crc) {
return SUCCESS;
} else {
return ERROR;
@ -1191,12 +1189,13 @@ void EF_Ctrl_Read_Device_Info(Efuse_Device_Info_Type *deviceInfo)
/****************************************************************************/ /**
* @brief Whether Capcode is empty
*
* @param slot: Cap code slot
* @param reload: Whether reload
*
* @return 0 for all slots full,1 for others
*
*******************************************************************************/
uint8_t EF_Ctrl_Is_CapCode_Empty(uint8_t reload)
uint8_t EF_Ctrl_Is_CapCode_Empty(uint8_t slot, uint8_t reload)
{
uint32_t tmp = 0xffffffff;
@ -1207,40 +1206,60 @@ uint8_t EF_Ctrl_Is_CapCode_Empty(uint8_t reload)
EF_CTRL_LOAD_BEFORE_READ_R0;
}
tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_ANA_TRIM_0);
return (EF_Ctrl_Is_All_Bits_Zero(tmp, 2, 8));
if (slot == 0) {
tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W3);
return (EF_Ctrl_Is_All_Bits_Zero(tmp, 25, 7));
} else if (slot == 1) {
tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_3_W3);
return (EF_Ctrl_Is_All_Bits_Zero(tmp, 9, 7));
} else if (slot == 2) {
tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_3_W3);
return (EF_Ctrl_Is_All_Bits_Zero(tmp, 25, 7));
} else {
return 0;
}
}
/****************************************************************************/ /**
* @brief Efuse write Cap code
*
* @param slot: Cap code slot
* @param code: Cap code value
* @param program: Whether program
*
* @return SUCCESS or ERROR
*
*******************************************************************************/
BL_Err_Type EF_Ctrl_Write_CapCode_Opt(uint8_t code, uint8_t program)
BL_Err_Type EF_Ctrl_Write_CapCode_Opt(uint8_t slot, uint8_t code, uint8_t program)
{
uint32_t tmp;
uint8_t trim;
if (slot >= 3) {
return ERROR;
}
/* Switch to AHB clock */
EF_Ctrl_Sw_AHB_Clk_0();
EF_CTRL_LOAD_BEFORE_READ_R0;
tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_ANA_TRIM_0);
trim = (code << 1);
trim |= (1 << 0);
trim = code;
trim |= ((EF_Ctrl_Get_Trim_Parity(code, 6)) << 6);
trim |= (1 << 7);
BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_ANA_TRIM_0, tmp | (trim << 2));
if (slot == 0) {
tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W3);
BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W3, tmp | (trim << 25));
} else if (slot == 1) {
tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_3_W3);
BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_3_W3, tmp | (trim << 9));
} else if (slot == 2) {
tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_3_W3);
BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_3_W3, tmp | (trim << 25));
}
if (program) {
EF_Ctrl_Program_Efuse_0();
}
while (SET == EF_Ctrl_Busy())
;
@ -1250,16 +1269,17 @@ BL_Err_Type EF_Ctrl_Write_CapCode_Opt(uint8_t code, uint8_t program)
/****************************************************************************/ /**
* @brief Efuse read Cap code
*
* @param slot: Cap code slot
* @param code: Cap code pointer
* @param reload: Whether reload
*
* @return SUCCESS or ERROR
*
*******************************************************************************/
BL_Err_Type EF_Ctrl_Read_CapCode_Opt(uint8_t *code, uint8_t reload)
BL_Err_Type EF_Ctrl_Read_CapCode_Opt(uint8_t slot, uint8_t *code, uint8_t reload)
{
uint32_t tmp;
Efuse_Capcode_Info_Type *trim = (Efuse_Capcode_Info_Type *)&tmp;
uint8_t trim = 0;
/* Switch to AHB clock */
EF_Ctrl_Sw_AHB_Clk_0();
@ -1268,15 +1288,21 @@ BL_Err_Type EF_Ctrl_Read_CapCode_Opt(uint8_t *code, uint8_t reload)
EF_CTRL_LOAD_BEFORE_READ_R0;
}
tmp = (BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_ANA_TRIM_0)) >> 2;
if (trim->en) {
if (trim->parity == EF_Ctrl_Get_Trim_Parity(trim->capCode, 6)) {
*code = trim->capCode;
return SUCCESS;
}
if (slot == 0) {
tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W3);
trim = (tmp >> 25) & 0x7f;
} else if (slot == 1) {
tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_3_W3);
trim = (tmp >> 9) & 0x7f;
} else if (slot == 2) {
tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_3_W3);
trim = (tmp >> 25) & 0x7f;
}
if (trim & 0x01) {
*code = trim >> 1;
return SUCCESS;
}
return ERROR;
}
@ -1303,20 +1329,16 @@ uint8_t EF_Ctrl_Is_PowerOffset_Slot_Empty(uint8_t slot, uint8_t reload)
if (slot == 0) {
tmp1 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W3);
part1Empty = (EF_Ctrl_Is_All_Bits_Zero(tmp1, 15, 17));
part1Empty = (EF_Ctrl_Is_All_Bits_Zero(tmp1, 16, 9));
part2Empty = 1;
} else if (slot == 1) {
tmp1 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_4_W1);
part1Empty = (EF_Ctrl_Is_All_Bits_Zero(tmp1, 0, 16));
tmp1 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_ANA_TRIM_0);
part2Empty = (EF_Ctrl_Is_All_Bits_Zero(tmp1, 0, 1));
tmp1 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_3_W3);
part1Empty = (EF_Ctrl_Is_All_Bits_Zero(tmp1, 0, 9));
part2Empty = 1;
} else if (slot == 2) {
tmp1 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_4_W1);
part1Empty = (EF_Ctrl_Is_All_Bits_Zero(tmp1, 16, 16));
tmp1 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_ANA_TRIM_0);
part2Empty = (EF_Ctrl_Is_All_Bits_Zero(tmp1, 1, 1));
tmp1 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_3_W3);
part1Empty = (EF_Ctrl_Is_All_Bits_Zero(tmp1, 16, 9));
part2Empty = 1;
}
return (part1Empty && part2Empty);
@ -1326,63 +1348,48 @@ uint8_t EF_Ctrl_Is_PowerOffset_Slot_Empty(uint8_t slot, uint8_t reload)
* @brief Efuse write power offset
*
* @param slot: Power offset slot
* @param pwrOffset[3]: Power offset value array
* @param pwrOffset[2]: Power offset value array
* @param program: Whether program
*
* @return SUCCESS or ERROR
*
*******************************************************************************/
BL_Err_Type EF_Ctrl_Write_PowerOffset_Opt(uint8_t slot, int8_t pwrOffset[3], uint8_t program)
BL_Err_Type EF_Ctrl_Write_PowerOffset_Opt(uint8_t slot, int8_t pwrOffset[2], uint8_t program)
{
uint64_t tmp = 0;
uint32_t tmp = 0;
uint32_t k = 0;
uint64_t Value = 0;
uint8_t parity;
uint32_t Value = 0;
if (slot >= 3) {
return ERROR;
}
for (k = 0; k < 3; k++) {
/* Use 5 bits as signed value */
if (pwrOffset[k] > 15) {
pwrOffset[k] = 15;
for (k = 0; k < 2; k++) {
/* Use 4 bits as signed value */
if (pwrOffset[k] > 7) {
pwrOffset[k] = 7;
}
if (pwrOffset[k] < -16) {
pwrOffset[k] = -16;
if (pwrOffset[k] < -8) {
pwrOffset[k] = -8;
}
tmp = ((uint64_t)((pwrOffset[k]) & 0x1f)) << (k * 5);
Value += tmp;
Value += (uint32_t)(pwrOffset[k] & 0x0f) << (k * 4);
}
parity = EF_Ctrl_Get_Trim_Parity(Value, 15);
if (slot == 0) {
tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W3);
tmp |= (Value << 16);
tmp |= (1 << 15);
tmp |= (uint32_t)(parity << 31);
tmp |= (Value << 17);
tmp |= (1 << 16);
BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W3, tmp);
} else if (slot == 1) {
tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_4_W1);
tmp |= (Value << 0);
tmp |= (uint32_t)(parity << 15);
BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_4_W1, tmp);
tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_ANA_TRIM_0);
tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_3_W3);
tmp |= (Value << 1);
tmp |= (1 << 0);
BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_ANA_TRIM_0, tmp);
BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_3_W3, tmp);
} else if (slot == 2) {
tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_4_W1);
tmp |= (Value << 16);
tmp |= (uint32_t)(parity << 31);
BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_4_W1, tmp);
tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_ANA_TRIM_0);
tmp |= (1 << 1);
BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_ANA_TRIM_0, tmp);
tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_3_W3);
tmp |= (Value << 17);
tmp |= (1 << 16);
BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_3_W3, tmp);
}
if (program) {
@ -1399,18 +1406,17 @@ BL_Err_Type EF_Ctrl_Write_PowerOffset_Opt(uint8_t slot, int8_t pwrOffset[3], uin
* @brief Efuse read poweroffset value
*
* @param slot: Power offset slot
* @param pwrOffset[3]: Power offset array
* @param pwrOffset[2]: Power offset array
* @param reload: Whether reload
*
* @return SUCCESS or ERROR
*
*******************************************************************************/
BL_Err_Type EF_Ctrl_Read_PowerOffset_Opt(uint8_t slot, int8_t pwrOffset[3], uint8_t reload)
BL_Err_Type EF_Ctrl_Read_PowerOffset_Opt(uint8_t slot, int8_t pwrOffset[2], uint8_t reload)
{
uint64_t pwrOffsetValue = 0;
uint32_t pwrOffsetValue = 0;
uint32_t tmp = 0, k;
uint8_t en = 0, parity = 0;
uint8_t en = 0;
/* Switch to AHB clock */
EF_Ctrl_Sw_AHB_Clk_0();
@ -1421,41 +1427,29 @@ BL_Err_Type EF_Ctrl_Read_PowerOffset_Opt(uint8_t slot, int8_t pwrOffset[3], uint
if (slot == 0) {
tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W3);
en = (tmp >> 15) & 0x01;
pwrOffsetValue = (tmp >> 16) & 0x7fff;
parity = (tmp >> 31) & 0x01;
en = (tmp >> 16) & 0x01;
pwrOffsetValue = (tmp >> 17) & 0xff;
} else if (slot == 1) {
tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_4_W1);
pwrOffsetValue = (tmp >> 0) & 0x7fff;
parity = (tmp >> 15) & 0x01;
tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_ANA_TRIM_0);
tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_3_W3);
en = (tmp >> 0) & 0x01;
pwrOffsetValue = (tmp >> 1) & 0xff;
} else if (slot == 2) {
tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_4_W1);
pwrOffsetValue = (tmp >> 16) & 0x7fff;
parity = (tmp >> 31) & 0x01;
tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_ANA_TRIM_0);
en = (tmp >> 1) & 0x01;
tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_3_W3);
en = (tmp >> 16) & 0x01;
pwrOffsetValue = (tmp >> 17) & 0xff;
}
if (en) {
if (parity == EF_Ctrl_Get_Trim_Parity(pwrOffsetValue, 15)) {
for (k = 0; k < 3; k++) {
tmp = (pwrOffsetValue >> (k * 5)) & 0x1f;
if (tmp >= 16) {
pwrOffset[k] = tmp - 32;
} else {
pwrOffset[k] = tmp;
}
for (k = 0; k < 2; k++) {
tmp = (pwrOffsetValue >> (k * 4)) & 0x0f;
if (tmp >= 8) {
pwrOffset[k] = tmp - 16;
} else {
pwrOffset[k] = tmp;
}
return SUCCESS;
}
return SUCCESS;
}
return ERROR;
}

8
drivers/bl702_driver/std_drv/src/bl702_glb.c
View file

@ -1894,7 +1894,7 @@ void BMX_ERR_IRQHandler(void)
}
while (1) {
MSG("BMX_ERR_IRQHandler\r\n");
//MSG("BMX_ERR_IRQHandler\r\n");
BL702_Delay_MS(1000);
}
}
@ -1938,7 +1938,7 @@ void BMX_TO_IRQHandler(void)
}
while (1) {
MSG("BMX_TO_IRQHandler\r\n");
//MSG("BMX_TO_IRQHandler\r\n");
BL702_Delay_MS(1000);
}
}
@ -3992,7 +3992,7 @@ void GPIO_INT0_IRQHandler(void)
timeOut--;
} while ((SET == GLB_Get_GPIO_IntStatus(gpioPin)) && timeOut);
if (!timeOut) {
MSG("WARNING: Clear GPIO interrupt status fail.\r\n");
//MSG("WARNING: Clear GPIO interrupt status fail.\r\n");
}
/* if timeOut==0, GPIO interrupt status not cleared */
@ -4012,7 +4012,7 @@ void GPIO_INT0_IRQHandler(void)
timeOut--;
} while ((SET == GLB_Get_GPIO_Int2Status(gpioPin)) && timeOut);
if (!timeOut) {
MSG("WARNING: Clear GPIO interrupt status fail.\r\n");
//MSG("WARNING: Clear GPIO interrupt status fail.\r\n");
}
/* if timeOut==0, GPIO interrupt status not cleared */

4
drivers/bl702_driver/std_drv/src/bl702_l1c.c
View file

@ -608,7 +608,7 @@ void L1C_BMX_ERR_IRQHandler(void)
}
while (1) {
MSG("L1C_BMX_ERR_IRQHandler\r\n");
//MSG("L1C_BMX_ERR_IRQHandler\r\n");
BL702_Delay_MS(1000);
}
}
@ -652,7 +652,7 @@ void L1C_BMX_TO_IRQHandler(void)
}
while (1) {
MSG("L1C_BMX_TO_IRQHandler\r\n");
//MSG("L1C_BMX_TO_IRQHandler\r\n");
BL702_Delay_MS(1000);
}
}

22
drivers/bl702_driver/std_drv/src/bl702_pds.c
View file

@ -632,7 +632,7 @@ BL_Err_Type PDS_Set_Vddcore_GPIO_IntMask(BL_Mask_Type intMask)
* @return SUCCESS or ERROR
*
*******************************************************************************/
PDS_STS_Type PDS_Get_Vddcore_GPIO_IntStatus(void)
BL_Sts_Type PDS_Get_Vddcore_GPIO_IntStatus(void)
{
return BL_GET_REG_BITS_VAL(BL_RD_REG(PDS_BASE, PDS_GPIO_INT), PDS_GPIO_INT_STAT) ? SET : RESET;
}
@ -1328,6 +1328,26 @@ BL_Err_Type PDS_WAKEUP_IRQHandler_Install(void)
return SUCCESS;
}
/****************************************************************************/ /**
* @brief
*
* @param
*
* @return
*
*******************************************************************************/
BL_Err_Type PDS_Set_Clkpll_Top_Ctrl(uint8_t vg11Sel)
{
uint32_t tmpVal = 0;
tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL);
//clkpll_vg11_sel
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_VG11_SEL, vg11Sel);
BL_WR_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL, tmpVal);
return SUCCESS;
}
/*@} end of group PDS_Public_Functions */
/*@} end of group PDS */