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https://github.com/Fishwaldo/bl_mcu_sdk.git
synced 2025-07-11 15:28:53 +00:00
[fix] optimise some function process
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5db2f4abd8
commit
5c31369932
5 changed files with 27 additions and 32 deletions
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@ -142,7 +142,7 @@ void ES8388_Codec_Mode(ES8388_Cfg_Type *cfg)
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ES8388_Write_Reg(0x00, 0x36); //ADC clock is same as DAC . DACMCLK is the chip master clock source
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ES8388_Write_Reg(0x00, 0x36); //ADC clock is same as DAC . DACMCLK is the chip master clock source
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if (cfg->role == ES8388_MASTER) {
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if (cfg->role == ES8388_MASTER) {
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ES8388_Write_Reg(0x08, 0x80);
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ES8388_Write_Reg(0x08, 0x8D);
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} else {
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} else {
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ES8388_Write_Reg(0x08, 0x00);
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ES8388_Write_Reg(0x08, 0x00);
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}
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}
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@ -187,8 +187,8 @@ void ES8388_Codec_Mode(ES8388_Cfg_Type *cfg)
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* default divider is 256 , see datasheet reigster 13
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* default divider is 256 , see datasheet reigster 13
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*/
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*/
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if (cfg->role == ES8388_MASTER) {
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if (cfg->role == ES8388_MASTER) {
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ES8388_Write_Reg(0x0d, 0x02); //ADCLRCK = MCLK/256
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ES8388_Write_Reg(0x0d, 0x06); //ADCLRCK = MCLK/256
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ES8388_Write_Reg(0x18, 0x02); //DACLRCK = MCLK/256
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ES8388_Write_Reg(0x18, 0x06); //DACLRCK = MCLK/256
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}
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}
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/*set ADC/DAC default volume as 0 db */
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/*set ADC/DAC default volume as 0 db */
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@ -443,7 +443,7 @@ BL_Err_Type ES8388_Reg_Dump(void)
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bflb_platform_printf("iic read err\r\n");
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bflb_platform_printf("iic read err\r\n");
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}
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}
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bflb_platform_printf("Reg[%02x]=%02x \n", i, tmp);
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bflb_platform_printf("Reg[%02d]=0x%02x \n", i, tmp);
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}
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}
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return SUCCESS;
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return SUCCESS;
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@ -128,6 +128,11 @@ uint8_t bflb_platform_print_get(void)
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void bflb_platform_deinit(void)
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void bflb_platform_deinit(void)
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{
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{
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struct device *uart = device_find("debug_log");
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if (uart) {
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device_close(uart);
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}
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}
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}
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void bflb_platform_dump(uint8_t *data, uint32_t len)
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void bflb_platform_dump(uint8_t *data, uint32_t len)
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@ -105,6 +105,7 @@ void bflb_platform_delay_ms(uint32_t ms);
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void bflb_platform_delay_us(uint32_t us);
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void bflb_platform_delay_us(uint32_t us);
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void bflb_print_device_list(void);
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void bflb_print_device_list(void);
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int bflb_get_board_config(uint8_t func, uint8_t *pinlist);
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#ifdef __cplusplus
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#ifdef __cplusplus
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}
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}
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@ -24,7 +24,7 @@
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#ifndef __SPI_SD_H__
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#ifndef __SPI_SD_H__
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#define __SPI_SD_H__
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#define __SPI_SD_H__
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#define SPI_PIN_CS GPIO_PIN_16
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#define SPI_PIN_CS GPIO_PIN_10
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//SD传输数据结束后是否释放总线宏定义
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//SD传输数据结束后是否释放总线宏定义
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#define NO_RELEASE 0
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#define NO_RELEASE 0
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@ -47,16 +47,16 @@ void uart_irq_callback(struct device *dev, void *args, uint32_t size, uint32_t s
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if (size && size < Ring_Buffer_Get_Empty_Length(&uart1_rx_rb)) {
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if (size && size < Ring_Buffer_Get_Empty_Length(&uart1_rx_rb)) {
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Ring_Buffer_Write(&uart1_rx_rb, (uint8_t *)args, size);
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Ring_Buffer_Write(&uart1_rx_rb, (uint8_t *)args, size);
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} else {
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} else {
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MSG("RF\r\n");
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MSG("RF OV\r\n");
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}
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}
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} else if (state == UART_EVENT_RTO) {
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} else if (state == UART_EVENT_RTO) {
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if (size && size < Ring_Buffer_Get_Empty_Length(&uart1_rx_rb)) {
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if (size && size < Ring_Buffer_Get_Empty_Length(&uart1_rx_rb)) {
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Ring_Buffer_Write(&uart1_rx_rb, (uint8_t *)args, size);
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Ring_Buffer_Write(&uart1_rx_rb, (uint8_t *)args, size);
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} else {
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} else {
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MSG("RTO\r\n");
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MSG("RTO OV\r\n");
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}
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}
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} else if (state == UART_RX_FER_IT) {
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} else if (state == UART_RX_FER_IT) {
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MSG("ov\r\n");
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MSG("RX ERR\r\n");
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}
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}
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}
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}
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void uart1_init(void)
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void uart1_init(void)
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@ -65,10 +65,9 @@ void uart1_init(void)
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uart1 = device_find("uart1");
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uart1 = device_find("uart1");
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if (uart1) {
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if (uart1) {
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device_open(uart1, DEVICE_OFLAG_DMA_TX | DEVICE_OFLAG_INT_RX); //uart0 tx dma mode
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// device_open(uart1, DEVICE_OFLAG_DMA_TX | DEVICE_OFLAG_INT_RX);
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device_control(uart1, DEVICE_CTRL_SUSPEND, NULL);
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// device_set_callback(uart1, uart_irq_callback);
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device_set_callback(uart1, uart_irq_callback);
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// device_control(uart1, DEVICE_CTRL_SET_INT, (void *)(UART_RX_FIFO_IT | UART_RTO_IT));
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device_control(uart1, DEVICE_CTRL_SET_INT, (void *)(UART_RX_FIFO_IT | UART_RTO_IT));
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}
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}
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dma_register(DMA0_CH2_INDEX, "ch2");
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dma_register(DMA0_CH2_INDEX, "ch2");
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@ -76,31 +75,21 @@ void uart1_init(void)
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if (dma_ch2) {
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if (dma_ch2) {
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device_open(dma_ch2, 0);
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device_open(dma_ch2, 0);
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//device_set_callback(dma_ch2, NULL);
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//device_control(dma_ch2, DEVICE_CTRL_SET_INT, NULL);
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}
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}
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//device_control(uart1, DEVICE_CTRL_ATTACH_TX_DMA, dma_ch2);
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}
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}
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void uart1_config(uint32_t baudrate, uart_databits_t databits, uart_parity_t parity, uart_stopbits_t stopbits)
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void uart1_config(uint32_t baudrate, uart_databits_t databits, uart_parity_t parity, uart_stopbits_t stopbits)
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{
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{
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uart_param_cfg_t cfg;
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device_close(uart1);
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cfg.baudrate = baudrate;
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UART_DEV(uart1)->baudrate = baudrate;
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cfg.stopbits = stopbits;
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UART_DEV(uart1)->stopbits = stopbits;
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cfg.parity = parity;
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UART_DEV(uart1)->parity = parity;
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UART_DEV(uart1)->databits = (databits - 5);
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if (databits == 5) {
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device_open(uart1, DEVICE_OFLAG_DMA_TX | DEVICE_OFLAG_INT_RX);
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cfg.databits = UART_DATA_LEN_5;
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device_set_callback(uart1, uart_irq_callback);
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} else if (databits == 6) {
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device_control(uart1, DEVICE_CTRL_SET_INT, (void *)(UART_RX_FIFO_IT | UART_RTO_IT));
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cfg.databits = UART_DATA_LEN_6;
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Ring_Buffer_Reset(&usb_rx_rb);
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} else if (databits == 7) {
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Ring_Buffer_Reset(&uart1_rx_rb);
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cfg.databits = UART_DATA_LEN_7;
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} else if (databits == 8) {
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cfg.databits = UART_DATA_LEN_8;
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}
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device_control(uart1, DEVICE_CTRL_CONFIG, &cfg);
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}
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}
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static uint8_t uart1_dtr;
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static uint8_t uart1_dtr;
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