GitHub-Mirror/bl_mcu_sdk
2
0
Fork 0
mirror of https://github.com/Fishwaldo/bl_mcu_sdk.git synced 2025-07-11 15:28:53 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

[fix] optimise some function process

Browse source
This commit is contained in:
jzlv 2021-08-25 17:02:02 +08:00
parent 5db2f4abd8
commit 5c31369932
5 changed files with 27 additions and 32 deletions
Download patch file Download diff file Expand all files Collapse all files

8
bsp/bsp_common/es8388/bsp_es8388.c
View file

@ -142,7 +142,7 @@ void ES8388_Codec_Mode(ES8388_Cfg_Type *cfg)
ES8388_Write_Reg(0x00, 0x36); //ADC clock is same as DAC . DACMCLK is the chip master clock source ES8388_Write_Reg(0x00, 0x36); //ADC clock is same as DAC . DACMCLK is the chip master clock source
if (cfg->role == ES8388_MASTER) { if (cfg->role == ES8388_MASTER) {
ES8388_Write_Reg(0x08, 0x80); ES8388_Write_Reg(0x08, 0x8D);
} else { } else {
ES8388_Write_Reg(0x08, 0x00); ES8388_Write_Reg(0x08, 0x00);
} }
@ -187,8 +187,8 @@ void ES8388_Codec_Mode(ES8388_Cfg_Type *cfg)
* default divider is 256 , see datasheet reigster 13 * default divider is 256 , see datasheet reigster 13
*/ */
if (cfg->role == ES8388_MASTER) { if (cfg->role == ES8388_MASTER) {
ES8388_Write_Reg(0x0d, 0x02); //ADCLRCK = MCLK/256 ES8388_Write_Reg(0x0d, 0x06); //ADCLRCK = MCLK/256
ES8388_Write_Reg(0x18, 0x02); //DACLRCK = MCLK/256 ES8388_Write_Reg(0x18, 0x06); //DACLRCK = MCLK/256
} }
/*set ADC/DAC default volume as 0 db */ /*set ADC/DAC default volume as 0 db */
@ -443,7 +443,7 @@ BL_Err_Type ES8388_Reg_Dump(void)
bflb_platform_printf("iic read err\r\n"); bflb_platform_printf("iic read err\r\n");
} }
bflb_platform_printf("Reg[%02x]=%02x \n", i, tmp); bflb_platform_printf("Reg[%02d]=0x%02x \n", i, tmp);
} }
return SUCCESS; return SUCCESS;

5
bsp/bsp_common/platform/bflb_platform.c
View file

@ -128,6 +128,11 @@ uint8_t bflb_platform_print_get(void)
void bflb_platform_deinit(void) void bflb_platform_deinit(void)
{ {
struct device *uart = device_find("debug_log");
if (uart) {
device_close(uart);
}
} }
void bflb_platform_dump(uint8_t *data, uint32_t len) void bflb_platform_dump(uint8_t *data, uint32_t len)

1
bsp/bsp_common/platform/bflb_platform.h
View file

@ -105,6 +105,7 @@ void bflb_platform_delay_ms(uint32_t ms);
void bflb_platform_delay_us(uint32_t us); void bflb_platform_delay_us(uint32_t us);
void bflb_print_device_list(void); void bflb_print_device_list(void);
int bflb_get_board_config(uint8_t func, uint8_t *pinlist);
#ifdef __cplusplus #ifdef __cplusplus
} }

2
bsp/bsp_common/spi_sd/bsp_spi_sd.h
View file

@ -24,7 +24,7 @@
#ifndef __SPI_SD_H__ #ifndef __SPI_SD_H__
#define __SPI_SD_H__ #define __SPI_SD_H__
#define SPI_PIN_CS GPIO_PIN_16 #define SPI_PIN_CS GPIO_PIN_10
//SD传输数据结束后是否释放总线宏定义 //SD传输数据结束后是否释放总线宏定义
#define NO_RELEASE 0 #define NO_RELEASE 0

43
bsp/bsp_common/usb/uart_interface.c
View file

@ -47,16 +47,16 @@ void uart_irq_callback(struct device *dev, void *args, uint32_t size, uint32_t s
if (size && size < Ring_Buffer_Get_Empty_Length(&uart1_rx_rb)) { if (size && size < Ring_Buffer_Get_Empty_Length(&uart1_rx_rb)) {
Ring_Buffer_Write(&uart1_rx_rb, (uint8_t *)args, size); Ring_Buffer_Write(&uart1_rx_rb, (uint8_t *)args, size);
} else { } else {
MSG("RF\r\n"); MSG("RF OV\r\n");
} }
} else if (state == UART_EVENT_RTO) { } else if (state == UART_EVENT_RTO) {
if (size && size < Ring_Buffer_Get_Empty_Length(&uart1_rx_rb)) { if (size && size < Ring_Buffer_Get_Empty_Length(&uart1_rx_rb)) {
Ring_Buffer_Write(&uart1_rx_rb, (uint8_t *)args, size); Ring_Buffer_Write(&uart1_rx_rb, (uint8_t *)args, size);
} else { } else {
MSG("RTO\r\n"); MSG("RTO OV\r\n");
} }
} else if (state == UART_RX_FER_IT) { } else if (state == UART_RX_FER_IT) {
MSG("ov\r\n"); MSG("RX ERR\r\n");
} }
} }
void uart1_init(void) void uart1_init(void)
@ -65,10 +65,9 @@ void uart1_init(void)
uart1 = device_find("uart1"); uart1 = device_find("uart1");
if (uart1) { if (uart1) {
device_open(uart1, DEVICE_OFLAG_DMA_TX | DEVICE_OFLAG_INT_RX); //uart0 tx dma mode // device_open(uart1, DEVICE_OFLAG_DMA_TX | DEVICE_OFLAG_INT_RX);
device_control(uart1, DEVICE_CTRL_SUSPEND, NULL); // device_set_callback(uart1, uart_irq_callback);
device_set_callback(uart1, uart_irq_callback); // device_control(uart1, DEVICE_CTRL_SET_INT, (void *)(UART_RX_FIFO_IT | UART_RTO_IT));
device_control(uart1, DEVICE_CTRL_SET_INT, (void *)(UART_RX_FIFO_IT | UART_RTO_IT));
} }
dma_register(DMA0_CH2_INDEX, "ch2"); dma_register(DMA0_CH2_INDEX, "ch2");
@ -76,31 +75,21 @@ void uart1_init(void)
if (dma_ch2) { if (dma_ch2) {
device_open(dma_ch2, 0); device_open(dma_ch2, 0);
//device_set_callback(dma_ch2, NULL);
//device_control(dma_ch2, DEVICE_CTRL_SET_INT, NULL);
} }
//device_control(uart1, DEVICE_CTRL_ATTACH_TX_DMA, dma_ch2);
} }
void uart1_config(uint32_t baudrate, uart_databits_t databits, uart_parity_t parity, uart_stopbits_t stopbits) void uart1_config(uint32_t baudrate, uart_databits_t databits, uart_parity_t parity, uart_stopbits_t stopbits)
{ {
uart_param_cfg_t cfg; device_close(uart1);
cfg.baudrate = baudrate; UART_DEV(uart1)->baudrate = baudrate;
cfg.stopbits = stopbits; UART_DEV(uart1)->stopbits = stopbits;
cfg.parity = parity; UART_DEV(uart1)->parity = parity;
UART_DEV(uart1)->databits = (databits - 5);
if (databits == 5) { device_open(uart1, DEVICE_OFLAG_DMA_TX | DEVICE_OFLAG_INT_RX);
cfg.databits = UART_DATA_LEN_5; device_set_callback(uart1, uart_irq_callback);
} else if (databits == 6) { device_control(uart1, DEVICE_CTRL_SET_INT, (void *)(UART_RX_FIFO_IT | UART_RTO_IT));
cfg.databits = UART_DATA_LEN_6; Ring_Buffer_Reset(&usb_rx_rb);
} else if (databits == 7) { Ring_Buffer_Reset(&uart1_rx_rb);
cfg.databits = UART_DATA_LEN_7;
} else if (databits == 8) {
cfg.databits = UART_DATA_LEN_8;
}
device_control(uart1, DEVICE_CTRL_CONFIG, &cfg);
} }
static uint8_t uart1_dtr; static uint8_t uart1_dtr;