diff --git a/components/nmsis/CMakeLists.txt b/components/nmsis/CMakeLists.txt new file mode 100644 index 00000000..f067f2bc --- /dev/null +++ b/components/nmsis/CMakeLists.txt @@ -0,0 +1,46 @@ +################# Add global include ################# +list(APPEND ADD_INCLUDE +"${CMAKE_CURRENT_SOURCE_DIR}/core/inc" +"${CMAKE_CURRENT_SOURCE_DIR}/dsp/inc" +"${CMAKE_CURRENT_SOURCE_DIR}/nn/inc" +) +####################################################### + +################# Add private include ################# +list(APPEND ADD_PRIVATE_INCLUDE +"${CMAKE_CURRENT_SOURCE_DIR}/dsp/privateInc" +) +####################################################### + +############## Add current dir source files ########### +file(GLOB_RECURSE sources "${CMAKE_CURRENT_SOURCE_DIR}/dsp/*.c" +"${CMAKE_CURRENT_SOURCE_DIR}/nn/*.c" +) +list(APPEND ADD_SRCS ${sources}) +# aux_source_directory(src ADD_SRCS) +# list(REMOVE_ITEM ADD_SRCS "${CMAKE_CURRENT_SOURCE_DIR}") +####################################################### + +########### Add required/dependent components ######### +# list(APPEND ADD_REQUIREMENTS common) +####################################################### + +############ Add static libs ########################## +#list(APPEND ADD_STATIC_LIB "libxxx.a") +####################################################### + +############ Add dynamic libs ######################### +# list(APPEND ADD_DYNAMIC_LIB "libxxx.so") +####################################################### + +############ Add global compile option ################ +#add components denpend on this component +list(APPEND ADD_DEFINITIONS -D__RISCV_FEATURE_MVE=0 -Wno-incompatible-pointer-types -Wno-parentheses) +####################################################### + +############ Add private compile option ################ +#add compile option for this component that won't affect other modules +# list(APPEND ADD_PRIVATE_DEFINITIONS ) +####################################################### + +generate_library() diff --git a/components/nmsis/core/inc/core_compatiable.h b/components/nmsis/core/inc/core_compatiable.h new file mode 100644 index 00000000..efd7ea85 --- /dev/null +++ b/components/nmsis/core/inc/core_compatiable.h @@ -0,0 +1,226 @@ +/* + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef __CORE_COMPATIABLE_H__ +#define __CORE_COMPATIABLE_H__ +/*! + * @file core_compatiable.h + * @brief ARM compatiable function definitions header file + */ +#ifdef __cplusplus +extern "C" { +#endif + +/* ===== ARM Compatiable Functions ===== */ +/** + * \defgroup NMSIS_Core_ARMCompatiable_Functions ARM Compatiable Functions + * \ingroup NMSIS_Core + * \brief A few functions that compatiable with ARM CMSIS-Core. + * \details + * + * Here we provided a few functions that compatiable with ARM CMSIS-Core, + * mostly used in the DSP and NN library. + * @{ + */ +/** \brief Instruction Synchronization Barrier, compatiable with ARM */ +#define __ISB() __RWMB() + +/** \brief Data Synchronization Barrier, compatiable with ARM */ +#define __DSB() __RWMB() + +/** \brief Data Memory Barrier, compatiable with ARM */ +#define __DMB() __RWMB() + +/** \brief LDRT Unprivileged (8 bit), ARM Compatiable */ +#define __LDRBT(ptr) __LB((ptr)) +/** \brief LDRT Unprivileged (16 bit), ARM Compatiable */ +#define __LDRHT(ptr) __LH((ptr)) +/** \brief LDRT Unprivileged (32 bit), ARM Compatiable */ +#define __LDRT(ptr) __LW((ptr)) + +/** \brief STRT Unprivileged (8 bit), ARM Compatiable */ +#define __STRBT(val, ptr) __SB((ptr), (val)) +/** \brief STRT Unprivileged (16 bit), ARM Compatiable */ +#define __STRHT(val, ptr) __SH((ptr), (val)) +/** \brief STRT Unprivileged (32 bit), ARM Compatiable */ +#define __STRT(val, ptr) __SW((ptr), (val)) + +/* ===== Saturation Operations ===== */ +/** + * \brief Signed Saturate + * \details Saturates a signed value. + * \param [in] value Value to be saturated + * \param [in] sat Bit position to saturate to (1..32) + * \return Saturated value + */ +#if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1) +#define __SSAT(val, sat) __RV_SCLIP32((val), (sat - 1)) +#else +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max; + if (val > max) { + return max; + } else if (val < min) { + return min; + } + } + return val; +} +#endif + +/** + * \brief Unsigned Saturate + * \details Saturates an unsigned value. + * \param [in] value Value to be saturated + * \param [in] sat Bit position to saturate to (0..31) + * \return Saturated value + */ +#if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1) +#define __USAT(val, sat) __RV_UCLIP32((val), (sat)) +#else +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) { + return max; + } else if (val < 0) { + return 0U; + } + } + return (uint32_t)val; +} +#endif +#if 0 +/* ===== Data Processing Operations ===== */ +/** + * \brief Reverse byte order (32 bit) + * \details Reverses the byte order in unsigned integer value. + * For example, 0x12345678 becomes 0x78563412. + * \param [in] value Value to reverse + * \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ + uint32_t result; + + result = ((value & 0xff000000) >> 24) | ((value & 0x00ff0000) >> 8) | ((value & 0x0000ff00) << 8) | ((value & 0x000000ff) << 24); + return result; +} + +/** + * \brief Reverse byte order (16 bit) + * \details Reverses the byte order within each halfword of a word. + * For example, 0x12345678 becomes 0x34127856. + * \param [in] value Value to reverse + * \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + result = ((value & 0xff000000) >> 8) | ((value & 0x00ff00000) << 8) | ((value & 0x0000ff00) >> 8) | ((value & 0x000000ff) << 8); + + return result; +} + +/** + * \brief Reverse byte order (16 bit) + * \details Reverses the byte order in a 16-bit value + * and returns the signed 16-bit result. + * For example, 0x0080 becomes 0x8000. + * \param [in] value Value to reverse + * \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ + int16_t result; + result = ((value & 0xff00) >> 8) | ((value & 0x00ff) << 8); + return result; +} +#endif +/** + * \brief Rotate Right in unsigned value (32 bit) + * \details Rotate Right (immediate) provides the value of + * the contents of a register rotated by a variable number of bits. + * \param [in] op1 Value to rotate + * \param [in] op2 Number of Bits to rotate(0-31) + * \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 = op2 & 0x1F; + if (op2 == 0U) { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + +/** + * \brief Reverse bit order of value + * \details Reverses the bit order of the given value. + * \param [in] value Value to reverse + * \return Reversed value + */ +#if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1) +#define __RBIT(value) __RV_BITREVI((value), 31) +#else +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif /* defined(__DSP_PRESENT) && (__DSP_PRESENT == 1) */ + +/** + * \brief Count leading zeros + * \details Counts the number of leading zeros of a data value. + * \param [in] data Value to count the leading zeros + * \return number of leading zeros in value + */ +#if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1) +#define __CLZ(data) __RV_CLZ32(data) +#else +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t data) +{ + uint8_t ret = 0; + uint32_t temp = ~data; + while (temp & 0x80000000) { + temp <<= 1; + ret++; + } + return ret; +} +#endif /* defined(__DSP_PRESENT) && (__DSP_PRESENT == 1) */ + +/** @} */ /* End of Doxygen Group NMSIS_Core_ARMCompatiable_Functions */ + +#ifdef __cplusplus +} +#endif +#endif /* __CORE_COMPATIABLE_H__ */ diff --git a/components/nmsis/core/inc/core_feature_base.h b/components/nmsis/core/inc/core_feature_base.h new file mode 100644 index 00000000..7bf1ad10 --- /dev/null +++ b/components/nmsis/core/inc/core_feature_base.h @@ -0,0 +1,1407 @@ +/* + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CORE_FEATURE_BASE__ +#define __CORE_FEATURE_BASE__ +/*! + * @file core_feature_base.h + * @brief Base core feature API for Nuclei N/NX Core + */ +#include +#include "riscv_encoding.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \defgroup NMSIS_Core_Registers Register Define and Type Definitions + * \brief Type definitions and defines for core registers. + * + * @{ + */ +#ifndef __RISCV_XLEN +/** \brief Refer to the width of an integer register in bits(either 32 or 64) */ +#ifndef __riscv_xlen +#define __RISCV_XLEN 32 +#else +#define __RISCV_XLEN __riscv_xlen +#endif +#endif /* __RISCV_XLEN */ + +/** \brief Type of Control and Status Register(CSR), depends on the XLEN defined in RISC-V */ +#if __RISCV_XLEN == 32 +typedef uint32_t rv_csr_t; +#elif __RISCV_XLEN == 64 +typedef uint64_t rv_csr_t; +#else +typedef uint32_t rv_csr_t; +#endif +/** @} */ /* End of Doxygen Group NMSIS_Core_Registers */ +/** + * \defgroup NMSIS_Core_Base_Registers Base Register Define and Type Definitions + * \ingroup NMSIS_Core_Registers + * \brief Type definitions and defines for base core registers. + * + * @{ + */ +/** + * \brief Union type to access MISA CSR register. + */ +typedef union { + struct { + rv_csr_t a : 1; /*!< bit: 0 Atomic extension */ + rv_csr_t b : 1; /*!< bit: 1 Tentatively reserved for Bit-Manipulation extension */ + rv_csr_t c : 1; /*!< bit: 2 Compressed extension */ + rv_csr_t d : 1; /*!< bit: 3 Double-precision floating-point extension */ + rv_csr_t e : 1; /*!< bit: 4 RV32E base ISA */ + rv_csr_t f : 1; /*!< bit: 5 Single-precision floating-point extension */ + rv_csr_t g : 1; /*!< bit: 6 Additional standard extensions present */ + rv_csr_t h : 1; /*!< bit: 7 Hypervisor extension */ + rv_csr_t i : 1; /*!< bit: 8 RV32I/64I/128I base ISA */ + rv_csr_t j : 1; /*!< bit: 9 Tentatively reserved for Dynamically Translated Languages extension */ + rv_csr_t _reserved1 : 1; /*!< bit: 10 Reserved */ + rv_csr_t l : 1; /*!< bit: 11 Tentatively reserved for Decimal Floating-Point extension */ + rv_csr_t m : 1; /*!< bit: 12 Integer Multiply/Divide extension */ + rv_csr_t n : 1; /*!< bit: 13 User-level interrupts supported */ + rv_csr_t _reserved2 : 1; /*!< bit: 14 Reserved */ + rv_csr_t p : 1; /*!< bit: 15 Tentatively reserved for Packed-SIMD extension */ + rv_csr_t q : 1; /*!< bit: 16 Quad-precision floating-point extension */ + rv_csr_t _resreved3 : 1; /*!< bit: 17 Reserved */ + rv_csr_t s : 1; /*!< bit: 18 Supervisor mode implemented */ + rv_csr_t t : 1; /*!< bit: 19 Tentatively reserved for Transactional Memory extension */ + rv_csr_t u : 1; /*!< bit: 20 User mode implemented */ + rv_csr_t v : 1; /*!< bit: 21 Tentatively reserved for Vector extension */ + rv_csr_t _reserved4 : 1; /*!< bit: 22 Reserved */ + rv_csr_t x : 1; /*!< bit: 23 Non-standard extensions present */ +#if defined(__RISCV_XLEN) && __RISCV_XLEN == 64 + rv_csr_t _reserved5 : 38; /*!< bit: 24..61 Reserved */ + rv_csr_t mxl : 2; /*!< bit: 62..63 Machine XLEN */ +#else + rv_csr_t _reserved5 : 6; /*!< bit: 24..29 Reserved */ + rv_csr_t mxl : 2; /*!< bit: 30..31 Machine XLEN */ +#endif + } b; /*!< Structure used for bit access */ + rv_csr_t d; /*!< Type used for csr data access */ +} CSR_MISA_Type; + +/** + * \brief Union type to access MSTATUS CSR register. + */ +typedef union { + struct { +#if defined(__RISCV_XLEN) && __RISCV_XLEN == 64 + rv_csr_t _reserved0 : 3; /*!< bit: 0..2 Reserved */ + rv_csr_t mie : 1; /*!< bit: 3 Machine mode interrupt enable flag */ + rv_csr_t _reserved1 : 3; /*!< bit: 4..6 Reserved */ + rv_csr_t mpie : 1; /*!< bit: 7 mirror of MIE flag */ + rv_csr_t _reserved2 : 3; /*!< bit: 8..10 Reserved */ + rv_csr_t mpp : 2; /*!< bit: 11..12 mirror of Privilege Mode */ + rv_csr_t fs : 2; /*!< bit: 13..14 FS status flag */ + rv_csr_t xs : 2; /*!< bit: 15..16 XS status flag */ + rv_csr_t mprv : 1; /*!< bit: Machine mode PMP */ + rv_csr_t _reserved3 : 14; /*!< bit: 18..31 Reserved */ + rv_csr_t uxl : 2; /*!< bit: 32..33 user mode xlen */ + rv_csr_t _reserved6 : 29; /*!< bit: 34..62 Reserved */ + rv_csr_t sd : 1; /*!< bit: Dirty status for XS or FS */ +#else + rv_csr_t _reserved0 : 1; /*!< bit: 0 Reserved */ + rv_csr_t sie : 1; /*!< bit: 1 supervisor interrupt enable flag */ + rv_csr_t _reserved1 : 1; /*!< bit: 2 Reserved */ + rv_csr_t mie : 1; /*!< bit: 3 Machine mode interrupt enable flag */ + rv_csr_t _reserved2 : 1; /*!< bit: 4 Reserved */ + rv_csr_t spie : 1; /*!< bit: 3 Supervisor Privilede mode interrupt enable flag */ + rv_csr_t _reserved3 : 1; /*!< bit: Reserved */ + rv_csr_t mpie : 1; /*!< bit: mirror of MIE flag */ + rv_csr_t _reserved4 : 3; /*!< bit: Reserved */ + rv_csr_t mpp : 2; /*!< bit: mirror of Privilege Mode */ + rv_csr_t fs : 2; /*!< bit: FS status flag */ + rv_csr_t xs : 2; /*!< bit: XS status flag */ + rv_csr_t mprv : 1; /*!< bit: Machine mode PMP */ + rv_csr_t sum : 1; /*!< bit: Supervisor Mode load and store protection */ + rv_csr_t _reserved6 : 12; /*!< bit: 19..30 Reserved */ + rv_csr_t sd : 1; /*!< bit: Dirty status for XS or FS */ +#endif + } b; /*!< Structure used for bit access */ + rv_csr_t d; /*!< Type used for csr data access */ +} CSR_MSTATUS_Type; + +/** + * \brief Union type to access MTVEC CSR register. + */ +typedef union { + struct { + rv_csr_t mode : 6; /*!< bit: 0..5 interrupt mode control */ +#if defined(__RISCV_XLEN) && __RISCV_XLEN == 64 + rv_csr_t addr : 58; /*!< bit: 6..63 mtvec address */ +#else + rv_csr_t addr : 26; /*!< bit: 6..31 mtvec address */ +#endif + } b; /*!< Structure used for bit access */ + rv_csr_t d; /*!< Type used for csr data access */ +} CSR_MTVEC_Type; + +/** + * \brief Union type to access MCAUSE CSR register. + */ +typedef union { + struct { + rv_csr_t exccode : 12; /*!< bit: 11..0 exception or interrupt code */ + rv_csr_t _reserved0 : 4; /*!< bit: 15..12 Reserved */ + rv_csr_t mpil : 8; /*!< bit: 23..16 Previous interrupt level */ + rv_csr_t _reserved1 : 3; /*!< bit: 26..24 Reserved */ + rv_csr_t mpie : 1; /*!< bit: 27 Interrupt enable flag before enter interrupt */ + rv_csr_t mpp : 2; /*!< bit: 29..28 Privilede mode flag before enter interrupt */ + rv_csr_t minhv : 1; /*!< bit: 30 Machine interrupt vector table */ +#if defined(__RISCV_XLEN) && __RISCV_XLEN == 64 + rv_csr_t _reserved2 : 32; /*!< bit: 31..62 Reserved */ + rv_csr_t interrupt : 1; /*!< bit: 63 trap type. 0 means exception and 1 means interrupt */ +#else + rv_csr_t interrupt : 1; /*!< bit: 31 trap type. 0 means exception and 1 means interrupt */ +#endif + } b; /*!< Structure used for bit access */ + rv_csr_t d; /*!< Type used for csr data access */ +} CSR_MCAUSE_Type; + +/** + * \brief Union type to access MCOUNTINHIBIT CSR register. + */ +typedef union { + struct { + rv_csr_t cy : 1; /*!< bit: 0 1 means disable mcycle counter */ + rv_csr_t _reserved0 : 1; /*!< bit: 1 Reserved */ + rv_csr_t ir : 1; /*!< bit: 2 1 means disable minstret counter */ +#if defined(__RISCV_XLEN) && __RISCV_XLEN == 64 + rv_csr_t _reserved1 : 61; /*!< bit: 3..63 Reserved */ +#else + rv_csr_t _reserved1 : 29; /*!< bit: 3..31 Reserved */ +#endif + } b; /*!< Structure used for bit access */ + rv_csr_t d; /*!< Type used for csr data access */ +} CSR_MCOUNTINHIBIT_Type; + +/** + * \brief Union type to access MSUBM CSR register. + */ +typedef union { + struct { + rv_csr_t _reserved0 : 6; /*!< bit: 0..5 Reserved */ + rv_csr_t typ : 2; /*!< bit: 6..7 current trap type */ + rv_csr_t ptyp : 2; /*!< bit: 8..9 previous trap type */ +#if defined(__RISCV_XLEN) && __RISCV_XLEN == 64 + rv_csr_t _reserved1 : 54; /*!< bit: 10..63 Reserved */ +#else + rv_csr_t _reserved1 : 22; /*!< bit: 10..31 Reserved */ +#endif + } b; /*!< Structure used for bit access */ + rv_csr_t d; /*!< Type used for csr data access */ +} CSR_MSUBM_Type; + +/** + * \brief Union type to access MDCAUSE CSR register. + */ +typedef union { + struct { + rv_csr_t mdcause : 2; /*!< bit: 0..1 More detailed exception information as MCAUSE supplement */ + rv_csr_t _reserved0 : __RISCV_XLEN - 2; /*!< bit: 2..XLEN-1 Reserved */ + } b; /*!< Structure used for bit access */ + rv_csr_t d; /*!< Type used for csr data access */ +} CSR_MDCAUSE_Type; + +/** + * \brief Union type to access MMISC_CTRL CSR register. + */ +typedef union { + struct { + rv_csr_t _reserved0 : 3; /*!< bit: 0..2 Reserved */ + rv_csr_t bpu : 1; /*!< bit: 3 dynamic prediction enable flag */ + rv_csr_t _reserved1 : 2; /*!< bit: 4..5 Reserved */ + rv_csr_t misalign : 1; /*!< bit: 6 misaligned access support flag */ + rv_csr_t _reserved2 : 2; /*!< bit: 7..8 Reserved */ + rv_csr_t nmi_cause : 1; /*!< bit: 9 mnvec control and nmi mcase exccode */ +#if defined(__RISCV_XLEN) && __RISCV_XLEN == 64 + rv_csr_t _reserved3 : 54; /*!< bit: 10..63 Reserved */ +#else + rv_csr_t _reserved3 : 22; /*!< bit: 10..31 Reserved */ +#endif + } b; /*!< Structure used for bit access */ + rv_csr_t d; /*!< Type used for csr data access */ +} CSR_MMISCCTRL_Type; + +typedef CSR_MMISCCTRL_Type CSR_MMISCCTL_Type; + +/** + * \brief Union type to access MCACHE_CTL CSR register. + */ +typedef union { + struct { + rv_csr_t ic_en : 1; /*!< I-Cache enable */ + rv_csr_t ic_scpd_mod : 1; /*!< Scratchpad mode, 0: Scratchpad as ICache Data RAM, 1: Scratchpad as ILM SRAM */ + rv_csr_t ic_ecc_en : 1; /*!< I-Cache ECC enable */ + rv_csr_t ic_ecc_excp_en : 1; /*!< I-Cache 2bit ECC error exception enable */ + rv_csr_t ic_rwtecc : 1; /*!< Control I-Cache Tag Ram ECC code injection */ + rv_csr_t ic_rwdecc : 1; /*!< Control I-Cache Data Ram ECC code injection */ + rv_csr_t _reserved0 : 10; + rv_csr_t dc_en : 1; /*!< DCache enable */ + rv_csr_t dc_ecc_en : 1; /*!< D-Cache ECC enable */ + rv_csr_t dc_ecc_excp_en : 1; /*!< D-Cache 2bit ECC error exception enable */ + rv_csr_t dc_rwtecc : 1; /*!< Control D-Cache Tag Ram ECC code injection */ + rv_csr_t dc_rwdecc : 1; /*!< Control D-Cache Data Ram ECC code injection */ + rv_csr_t _reserved1 : __RISCV_XLEN - 21; + } b; /*!< Structure used for bit access */ + rv_csr_t d; /*!< Type used for csr data access */ +} CSR_MCACHECTL_Type; + +/** + * \brief Union type to access MSAVESTATUS CSR register. + */ +typedef union { + struct { + rv_csr_t mpie1 : 1; /*!< bit: 0 interrupt enable flag of fisrt level NMI/exception nestting */ + rv_csr_t mpp1 : 2; /*!< bit: 1..2 privilede mode of fisrt level NMI/exception nestting */ + rv_csr_t _reserved0 : 3; /*!< bit: 3..5 Reserved */ + rv_csr_t ptyp1 : 2; /*!< bit: 6..7 NMI/exception type of before first nestting */ + rv_csr_t mpie2 : 1; /*!< bit: 8 interrupt enable flag of second level NMI/exception nestting */ + rv_csr_t mpp2 : 2; /*!< bit: 9..10 privilede mode of second level NMI/exception nestting */ + rv_csr_t _reserved1 : 3; /*!< bit: 11..13 Reserved */ + rv_csr_t ptyp2 : 2; /*!< bit: 14..15 NMI/exception type of before second nestting */ +#if defined(__RISCV_XLEN) && __RISCV_XLEN == 64 + rv_csr_t _reserved2 : 48; /*!< bit: 16..63 Reserved*/ +#else + rv_csr_t _reserved2 : 16; /*!< bit: 16..31 Reserved*/ +#endif + } b; /*!< Structure used for bit access */ + rv_csr_t w; /*!< Type used for csr data access */ +} CSR_MSAVESTATUS_Type; + +/** + * \brief Union type to access MILM_CTL CSR register. + */ +typedef union { + struct { + rv_csr_t ilm_en : 1; /*!< ILM enable */ + rv_csr_t ilm_ecc_en : 1; /*!< ILM ECC eanble */ + rv_csr_t ilm_ecc_excp_en : 1; /*!< ILM ECC exception enable */ + rv_csr_t ilm_rwecc : 1; /*!< Control mecc_code write to ilm, simulate error injection */ + rv_csr_t _reserved0 : 6; /*!< Reserved */ + rv_csr_t ilm_bpa : __RISCV_XLEN - 10; /*!< ILM base address */ + } b; /*!< Structure used for bit access */ + rv_csr_t d; /*!< Type used for csr data access */ +} CSR_MILMCTL_Type; + +/** + * \brief Union type to access MDLM_CTL CSR register. + */ +typedef union { + struct { + rv_csr_t dlm_en : 1; /*!< DLM enable */ + rv_csr_t dlm_ecc_en : 1; /*!< DLM ECC eanble */ + rv_csr_t dlm_ecc_excp_en : 1; /*!< DLM ECC exception enable */ + rv_csr_t dlm_rwecc : 1; /*!< Control mecc_code write to dlm, simulate error injection */ + rv_csr_t _reserved0 : 6; /*!< Reserved */ + rv_csr_t dlm_bpa : __RISCV_XLEN - 10; /*!< DLM base address */ + } b; /*!< Structure used for bit access */ + rv_csr_t d; /*!< Type used for csr data access */ +} CSR_MDLMCTL_Type; + +/** + * \brief Union type to access MCFG_INFO CSR register. + */ +typedef union { + struct { + rv_csr_t tee : 1; /*!< TEE present */ + rv_csr_t ecc : 1; /*!< ECC present */ + rv_csr_t clic : 1; /*!< CLIC present */ + rv_csr_t plic : 1; /*!< PLIC present */ + rv_csr_t fio : 1; /*!< FIO present */ + rv_csr_t ppi : 1; /*!< PPI present */ + rv_csr_t nice : 1; /*!< NICE present */ + rv_csr_t ilm : 1; /*!< ILM present */ + rv_csr_t dlm : 1; /*!< DLM present */ + rv_csr_t icache : 1; /*!< ICache present */ + rv_csr_t dcache : 1; /*!< DCache present */ + rv_csr_t _reserved0 : __RISCV_XLEN - 11; + } b; /*!< Structure used for bit access */ + rv_csr_t d; /*!< Type used for csr data access */ +} CSR_MCFGINFO_Type; + +/** + * \brief Union type to access MICFG_INFO CSR register. + */ +typedef union { + struct { + rv_csr_t set : 4; /*!< I-Cache sets per way */ + rv_csr_t way : 3; /*!< I-Cache way */ + rv_csr_t lsize : 3; /*!< I-Cache line size */ + rv_csr_t cache_ecc : 1; /*!< I-Cache ECC present */ + rv_csr_t _reserved0 : 5; + rv_csr_t lm_size : 5; /*!< ILM size, need to be 2^n size */ + rv_csr_t lm_xonly : 1; /*!< ILM Execute only permission */ + rv_csr_t lm_ecc : 1; /*!< ILM ECC present */ + rv_csr_t _reserved1 : __RISCV_XLEN - 23; + } b; /*!< Structure used for bit access */ + rv_csr_t d; /*!< Type used for csr data access */ +} CSR_MICFGINFO_Type; + +/** + * \brief Union type to access MDCFG_INFO CSR register. + */ +typedef union { + struct { + rv_csr_t set : 4; /*!< D-Cache sets per way */ + rv_csr_t way : 3; /*!< D-Cache way */ + rv_csr_t lsize : 3; /*!< D-Cache line size */ + rv_csr_t cache_ecc : 1; /*!< D-Cache ECC present */ + rv_csr_t _reserved0 : 5; + rv_csr_t lm_size : 5; /*!< DLM size, need to be 2^n size */ + rv_csr_t lm_xonly : 1; /*!< DLM Execute only permission */ + rv_csr_t lm_ecc : 1; /*!< DLM ECC present */ + rv_csr_t _reserved1 : __RISCV_XLEN - 23; + } b; /*!< Structure used for bit access */ + rv_csr_t d; /*!< Type used for csr data access */ +} CSR_MDCFGINFO_Type; + +/** + * \brief Union type to access MPPICFG_INFO CSR register. + */ +typedef union { + struct { + rv_csr_t _reserved0 : 1; /*!< Reserved */ + rv_csr_t ppi_size : 5; /*!< PPI size, need to be 2^n size */ + rv_csr_t _reserved1 : 4; /*!< Reserved */ + rv_csr_t ppi_bpa : __RISCV_XLEN - 10; /*!< PPI base address */ + } b; /*!< Structure used for bit access */ + rv_csr_t d; /*!< Type used for csr data access */ +} CSR_MPPICFGINFO_Type; + +/** + * \brief Union type to access MFIOCFG_INFO CSR register. + */ +typedef union { + struct { + rv_csr_t _reserved0 : 1; /*!< Reserved */ + rv_csr_t fio_size : 5; /*!< FIO size, need to be 2^n size */ + rv_csr_t _reserved1 : 4; /*!< Reserved */ + rv_csr_t fio_bpa : __RISCV_XLEN - 10; /*!< FIO base address */ + } b; /*!< Structure used for bit access */ + rv_csr_t d; /*!< Type used for csr data access */ +} CSR_MFIOCFGINFO_Type; + +/** + * \brief Union type to access MECC_LOCK CSR register. + */ +typedef union { + struct { + rv_csr_t ecc_lock : 1; /*!< RW permission, ECC Lock configure */ + rv_csr_t _reserved0 : __RISCV_XLEN - 1; /*!< Reserved */ + } b; /*!< Structure used for bit access */ + rv_csr_t d; /*!< Type used for csr data access */ +} CSR_MECCLOCK_Type; + +/** + * \brief Union type to access MECC_CODE CSR register. + */ +typedef union { + struct { + rv_csr_t code : 9; /*!< Used to inject ECC check code */ + rv_csr_t _reserved0 : 7; /*!< Reserved */ + rv_csr_t ramid : 5; /*!< Indicate 2bit ECC error, software can clear these bits */ + rv_csr_t _reserved1 : 3; /*!< Reserved */ + rv_csr_t sramid : 5; /*!< Indicate 1bit ECC error, software can clear these bits */ + rv_csr_t _reserved2 : __RISCV_XLEN - 29; /*!< Reserved */ + } b; /*!< Structure used for bit access */ + rv_csr_t d; /*!< Type used for csr data access */ +} CSR_MECCCODE_Type; + +/** @} */ /* End of Doxygen Group NMSIS_Core_Base_Registers */ + +/* ########################### Core Function Access ########################### */ +/** + * \defgroup NMSIS_Core_CSR_Register_Access Core CSR Register Access + * \ingroup NMSIS_Core + * \brief Functions to access the Core CSR Registers + * \details + * + * The following functions or macros provide access to Core CSR registers. + * - \ref NMSIS_Core_CSR_Encoding + * - \ref NMSIS_Core_CSR_Registers + * @{ + */ + +#ifndef __ASSEMBLY__ + +/** + * \brief CSR operation Macro for csrrw instruction. + * \details + * Read the content of csr register to __v, + * then write content of val into csr register, then return __v + * \param csr CSR macro definition defined in + * \ref NMSIS_Core_CSR_Registers, eg. \ref CSR_MSTATUS + * \param val value to store into the CSR register + * \return the CSR register value before written + */ +#define __RV_CSR_SWAP(csr, val) \ + ({ \ + register rv_csr_t __v = (unsigned long)(val); \ + __ASM volatile("csrrw %0, " STRINGIFY(csr) ", %1" \ + : "=r"(__v) \ + : "rK"(__v) \ + : "memory"); \ + __v; \ + }) + +/** + * \brief CSR operation Macro for csrr instruction. + * \details + * Read the content of csr register to __v and return it + * \param csr CSR macro definition defined in + * \ref NMSIS_Core_CSR_Registers, eg. \ref CSR_MSTATUS + * \return the CSR register value + */ +#define __RV_CSR_READ(csr) \ + ({ \ + register rv_csr_t __v; \ + __ASM volatile("csrr %0, " STRINGIFY(csr) \ + : "=r"(__v) \ + : \ + : "memory"); \ + __v; \ + }) + +/** + * \brief CSR operation Macro for csrw instruction. + * \details + * Write the content of val to csr register + * \param csr CSR macro definition defined in + * \ref NMSIS_Core_CSR_Registers, eg. \ref CSR_MSTATUS + * \param val value to store into the CSR register + */ +#define __RV_CSR_WRITE(csr, val) \ + ({ \ + register rv_csr_t __v = (rv_csr_t)(val); \ + __ASM volatile("csrw " STRINGIFY(csr) ", %0" \ + : \ + : "rK"(__v) \ + : "memory"); \ + }) + +/** + * \brief CSR operation Macro for csrrs instruction. + * \details + * Read the content of csr register to __v, + * then set csr register to be __v | val, then return __v + * \param csr CSR macro definition defined in + * \ref NMSIS_Core_CSR_Registers, eg. \ref CSR_MSTATUS + * \param val Mask value to be used wih csrrs instruction + * \return the CSR register value before written + */ +#define __RV_CSR_READ_SET(csr, val) \ + ({ \ + register rv_csr_t __v = (rv_csr_t)(val); \ + __ASM volatile("csrrs %0, " STRINGIFY(csr) ", %1" \ + : "=r"(__v) \ + : "rK"(__v) \ + : "memory"); \ + __v; \ + }) + +/** + * \brief CSR operation Macro for csrs instruction. + * \details + * Set csr register to be csr_content | val + * \param csr CSR macro definition defined in + * \ref NMSIS_Core_CSR_Registers, eg. \ref CSR_MSTATUS + * \param val Mask value to be used wih csrs instruction + */ +#define __RV_CSR_SET(csr, val) \ + ({ \ + register rv_csr_t __v = (rv_csr_t)(val); \ + __ASM volatile("csrs " STRINGIFY(csr) ", %0" \ + : \ + : "rK"(__v) \ + : "memory"); \ + }) + +/** + * \brief CSR operation Macro for csrrc instruction. + * \details + * Read the content of csr register to __v, + * then set csr register to be __v & ~val, then return __v + * \param csr CSR macro definition defined in + * \ref NMSIS_Core_CSR_Registers, eg. \ref CSR_MSTATUS + * \param val Mask value to be used wih csrrc instruction + * \return the CSR register value before written + */ +#define __RV_CSR_READ_CLEAR(csr, val) \ + ({ \ + register rv_csr_t __v = (rv_csr_t)(val); \ + __ASM volatile("csrrc %0, " STRINGIFY(csr) ", %1" \ + : "=r"(__v) \ + : "rK"(__v) \ + : "memory"); \ + __v; \ + }) + +/** + * \brief CSR operation Macro for csrc instruction. + * \details + * Set csr register to be csr_content & ~val + * \param csr CSR macro definition defined in + * \ref NMSIS_Core_CSR_Registers, eg. \ref CSR_MSTATUS + * \param val Mask value to be used wih csrc instruction + */ +#define __RV_CSR_CLEAR(csr, val) \ + ({ \ + register rv_csr_t __v = (rv_csr_t)(val); \ + __ASM volatile("csrc " STRINGIFY(csr) ", %0" \ + : \ + : "rK"(__v) \ + : "memory"); \ + }) +#endif /* __ASSEMBLY__ */ +#if 0 +/** + * \brief Enable IRQ Interrupts + * \details Enables IRQ interrupts by setting the MIE-bit in the MSTATUS Register. + * \remarks + * Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __RV_CSR_SET(CSR_MSTATUS, MSTATUS_MIE); +} + +/** + * \brief Disable IRQ Interrupts + * \details Disables IRQ interrupts by clearing the MIE-bit in the MSTATUS Register. + * \remarks + * Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __RV_CSR_CLEAR(CSR_MSTATUS, MSTATUS_MIE); +} +#endif +/** + * \brief Read whole 64 bits value of mcycle counter + * \details This function will read the whole 64 bits of MCYCLE register + * \return The whole 64 bits value of MCYCLE + * \remarks It will work for both RV32 and RV64 to get full 64bits value of MCYCLE + */ +__STATIC_FORCEINLINE uint64_t __get_rv_cycle(void) +{ +#if __RISCV_XLEN == 32 + volatile uint32_t high0, low, high; + uint64_t full; + + high0 = __RV_CSR_READ(CSR_MCYCLEH); + low = __RV_CSR_READ(CSR_MCYCLE); + high = __RV_CSR_READ(CSR_MCYCLEH); + if (high0 != high) { + low = __RV_CSR_READ(CSR_MCYCLE); + } + full = (((uint64_t)high) << 32) | low; + return full; +#elif __RISCV_XLEN == 64 + return (uint64_t)__RV_CSR_READ(CSR_MCYCLE); +#else // TODO Need cover for XLEN=128 case in future + return (uint64_t)__RV_CSR_READ(CSR_MCYCLE); +#endif +} + +/** + * \brief Read whole 64 bits value of machine instruction-retired counter + * \details This function will read the whole 64 bits of MINSTRET register + * \return The whole 64 bits value of MINSTRET + * \remarks It will work for both RV32 and RV64 to get full 64bits value of MINSTRET + */ +__STATIC_FORCEINLINE uint64_t __get_rv_instret(void) +{ +#if __RISCV_XLEN == 32 + volatile uint32_t high0, low, high; + uint64_t full; + + high0 = __RV_CSR_READ(CSR_MINSTRETH); + low = __RV_CSR_READ(CSR_MINSTRET); + high = __RV_CSR_READ(CSR_MINSTRETH); + if (high0 != high) { + low = __RV_CSR_READ(CSR_MINSTRET); + } + full = (((uint64_t)high) << 32) | low; + return full; +#elif __RISCV_XLEN == 64 + return (uint64_t)__RV_CSR_READ(CSR_MINSTRET); +#else // TODO Need cover for XLEN=128 case in future + return (uint64_t)__RV_CSR_READ(CSR_MINSTRET); +#endif +} + +/** + * \brief Read whole 64 bits value of real-time clock + * \details This function will read the whole 64 bits of TIME register + * \return The whole 64 bits value of TIME CSR + * \remarks It will work for both RV32 and RV64 to get full 64bits value of TIME + * \attention only available when user mode available + */ +__STATIC_FORCEINLINE uint64_t __get_rv_time(void) +{ +#if __RISCV_XLEN == 32 + volatile uint32_t high0, low, high; + uint64_t full; + + high0 = __RV_CSR_READ(CSR_TIMEH); + low = __RV_CSR_READ(CSR_TIME); + high = __RV_CSR_READ(CSR_TIMEH); + if (high0 != high) { + low = __RV_CSR_READ(CSR_TIME); + } + full = (((uint64_t)high) << 32) | low; + return full; +#elif __RISCV_XLEN == 64 + return (uint64_t)__RV_CSR_READ(CSR_TIME); +#else // TODO Need cover for XLEN=128 case in future + return (uint64_t)__RV_CSR_READ(CSR_TIME); +#endif +} + +/** @} */ /* End of Doxygen Group NMSIS_Core_CSR_Register_Access */ + +/* ########################### CPU Intrinsic Functions ########################### */ +/** + * \defgroup NMSIS_Core_CPU_Intrinsic Intrinsic Functions for CPU Intructions + * \ingroup NMSIS_Core + * \brief Functions that generate RISC-V CPU instructions. + * \details + * + * The following functions generate specified RISC-V instructions that cannot be directly accessed by compiler. + * @{ + */ +#if 0 +/** + * \brief NOP Instruction + * \details + * No Operation does nothing. + * This instruction can be used for code alignment purposes. + */ +__STATIC_FORCEINLINE void __NOP(void) +{ + __ASM volatile("nop"); +} + +/** + * \brief Wait For Interrupt + * \details + * Wait For Interrupt is is executed using CSR_WFE.WFE=0 and WFI instruction. + * It will suspends execution until interrupt, NMI or Debug happened. + * When Core is waked up by interrupt, if + * 1. mstatus.MIE == 1(interrupt enabled), Core will enter ISR code + * 2. mstatus.MIE == 0(interrupt disabled), Core will resume previous execution + */ +__STATIC_FORCEINLINE void __WFI(void) +{ + __RV_CSR_CLEAR(CSR_WFE, WFE_WFE); + __ASM volatile("wfi"); +} + +/** + * \brief Wait For Event + * \details + * Wait For Event is executed using CSR_WFE.WFE=1 and WFI instruction. + * It will suspends execution until event, NMI or Debug happened. + * When Core is waked up, Core will resume previous execution + */ +__STATIC_FORCEINLINE void __WFE(void) +{ + __RV_CSR_SET(CSR_WFE, WFE_WFE); + __ASM volatile("wfi"); + __RV_CSR_CLEAR(CSR_WFE, WFE_WFE); +} + +/** + * \brief Breakpoint Instruction + * \details + * Causes the processor to enter Debug state. + * Debug tools can use this to investigate system state + * when the instruction at a particular address is reached. + */ +__STATIC_FORCEINLINE void __EBREAK(void) +{ + __ASM volatile("ebreak"); +} + +/** + * \brief Environment Call Instruction + * \details + * The ECALL instruction is used to make a service request to + * the execution environment. + */ +__STATIC_FORCEINLINE void __ECALL(void) +{ + __ASM volatile("ecall"); +} +#endif +/** + * \brief WFI Sleep Mode enumeration + */ +typedef enum WFI_SleepMode { + WFI_SHALLOW_SLEEP = 0, /*!< Shallow sleep mode, the core_clk will poweroff */ + WFI_DEEP_SLEEP = 1 /*!< Deep sleep mode, the core_clk and core_ano_clk will poweroff */ +} WFI_SleepMode_Type; + +/** + * \brief Set Sleep mode of WFI + * \details + * Set the SLEEPVALUE CSR register to control the + * WFI Sleep mode. + * \param[in] mode The sleep mode to be set + */ +__STATIC_FORCEINLINE void __set_wfi_sleepmode(WFI_SleepMode_Type mode) +{ + __RV_CSR_WRITE(CSR_SLEEPVALUE, mode); +} + +/** + * \brief Send TX Event + * \details + * Set the CSR TXEVT to control send a TX Event. + * The Core will output signal tx_evt as output event signal. + */ +__STATIC_FORCEINLINE void __TXEVT(void) +{ + __RV_CSR_SET(CSR_TXEVT, 0x1); +} + +/** + * \brief Enable MCYCLE counter + * \details + * Clear the CY bit of MCOUNTINHIBIT to 0 to enable MCYCLE Counter + */ +__STATIC_FORCEINLINE void __enable_mcycle_counter(void) +{ + __RV_CSR_CLEAR(CSR_MCOUNTINHIBIT, MCOUNTINHIBIT_CY); +} + +/** + * \brief Disable MCYCLE counter + * \details + * Set the CY bit of MCOUNTINHIBIT to 1 to disable MCYCLE Counter + */ +__STATIC_FORCEINLINE void __disable_mcycle_counter(void) +{ + __RV_CSR_SET(CSR_MCOUNTINHIBIT, MCOUNTINHIBIT_CY); +} + +/** + * \brief Enable MINSTRET counter + * \details + * Clear the IR bit of MCOUNTINHIBIT to 0 to enable MINSTRET Counter + */ +__STATIC_FORCEINLINE void __enable_minstret_counter(void) +{ + __RV_CSR_CLEAR(CSR_MCOUNTINHIBIT, MCOUNTINHIBIT_IR); +} + +/** + * \brief Disable MINSTRET counter + * \details + * Set the IR bit of MCOUNTINHIBIT to 1 to disable MINSTRET Counter + */ +__STATIC_FORCEINLINE void __disable_minstret_counter(void) +{ + __RV_CSR_SET(CSR_MCOUNTINHIBIT, MCOUNTINHIBIT_IR); +} + +/** + * \brief Enable MCYCLE & MINSTRET counter + * \details + * Clear the IR and CY bit of MCOUNTINHIBIT to 1 to enable MINSTRET & MCYCLE Counter + */ +__STATIC_FORCEINLINE void __enable_all_counter(void) +{ + __RV_CSR_CLEAR(CSR_MCOUNTINHIBIT, MCOUNTINHIBIT_IR | MCOUNTINHIBIT_CY); +} + +/** + * \brief Disable MCYCLE & MINSTRET counter + * \details + * Set the IR and CY bit of MCOUNTINHIBIT to 1 to disable MINSTRET & MCYCLE Counter + */ +__STATIC_FORCEINLINE void __disable_all_counter(void) +{ + __RV_CSR_SET(CSR_MCOUNTINHIBIT, MCOUNTINHIBIT_IR | MCOUNTINHIBIT_CY); +} + +/** + * \brief Execute fence instruction, p -> pred, s -> succ + * \details + * the FENCE instruction ensures that all memory accesses from instructions preceding + * the fence in program order (the `predecessor set`) appear earlier in the global memory order than + * memory accesses from instructions appearing after the fence in program order (the `successor set`). + * For details, please refer to The RISC-V Instruction Set Manual + * \param p predecessor set, such as iorw, rw, r, w + * \param s successor set, such as iorw, rw, r, w + **/ +#define __FENCE(p, s) __ASM volatile("fence " #p "," #s \ + : \ + : \ + : "memory") + +/** + * \brief Fence.i Instruction + * \details + * The FENCE.I instruction is used to synchronize the instruction + * and data streams. + */ +__STATIC_FORCEINLINE void __FENCE_I(void) +{ + __ASM volatile("fence.i"); +} + +/** \brief Read & Write Memory barrier */ +#define __RWMB() __FENCE(iorw, iorw) + +/** \brief Read Memory barrier */ +#define __RMB() __FENCE(ir, ir) + +/** \brief Write Memory barrier */ +#define __WMB() __FENCE(ow, ow) + +/** \brief SMP Read & Write Memory barrier */ +#define __SMP_RWMB() __FENCE(rw, rw) + +/** \brief SMP Read Memory barrier */ +#define __SMP_RMB() __FENCE(r, r) + +/** \brief SMP Write Memory barrier */ +#define __SMP_WMB() __FENCE(w, w) + +/** \brief CPU relax for busy loop */ +#define __CPU_RELAX() __ASM volatile("" \ + : \ + : \ + : "memory") + +/* ===== Load/Store Operations ===== */ +/** + * \brief Load 8bit value from address (8 bit) + * \details Load 8 bit value. + * \param [in] addr Address pointer to data + * \return value of type uint8_t at (*addr) + */ +__STATIC_FORCEINLINE uint8_t __LB(volatile void *addr) +{ + uint8_t result; + + __ASM volatile("lb %0, 0(%1)" + : "=r"(result) + : "r"(addr)); + return result; +} + +/** + * \brief Load 16bit value from address (16 bit) + * \details Load 16 bit value. + * \param [in] addr Address pointer to data + * \return value of type uint16_t at (*addr) + */ +__STATIC_FORCEINLINE uint16_t __LH(volatile void *addr) +{ + uint16_t result; + + __ASM volatile("lh %0, 0(%1)" + : "=r"(result) + : "r"(addr)); + return result; +} + +/** + * \brief Load 32bit value from address (32 bit) + * \details Load 32 bit value. + * \param [in] addr Address pointer to data + * \return value of type uint32_t at (*addr) + */ +__STATIC_FORCEINLINE uint32_t __LW(volatile void *addr) +{ + uint32_t result; + + __ASM volatile("lw %0, 0(%1)" + : "=r"(result) + : "r"(addr)); + return result; +} + +#if __RISCV_XLEN != 32 +/** + * \brief Load 64bit value from address (64 bit) + * \details Load 64 bit value. + * \param [in] addr Address pointer to data + * \return value of type uint64_t at (*addr) + * \remarks RV64 only macro + */ +__STATIC_FORCEINLINE uint64_t __LD(volatile void *addr) +{ + uint64_t result; + __ASM volatile("ld %0, 0(%1)" + : "=r"(result) + : "r"(addr)); + return result; +} +#endif + +/** + * \brief Write 8bit value to address (8 bit) + * \details Write 8 bit value. + * \param [in] addr Address pointer to data + * \param [in] val Value to set + */ +__STATIC_FORCEINLINE void __SB(volatile void *addr, uint8_t val) +{ + __ASM volatile("sb %0, 0(%1)" + : + : "r"(val), "r"(addr)); +} + +/** + * \brief Write 16bit value to address (16 bit) + * \details Write 16 bit value. + * \param [in] addr Address pointer to data + * \param [in] val Value to set + */ +__STATIC_FORCEINLINE void __SH(volatile void *addr, uint16_t val) +{ + __ASM volatile("sh %0, 0(%1)" + : + : "r"(val), "r"(addr)); +} + +/** + * \brief Write 32bit value to address (32 bit) + * \details Write 32 bit value. + * \param [in] addr Address pointer to data + * \param [in] val Value to set + */ +__STATIC_FORCEINLINE void __SW(volatile void *addr, uint32_t val) +{ + __ASM volatile("sw %0, 0(%1)" + : + : "r"(val), "r"(addr)); +} + +#if __RISCV_XLEN != 32 +/** + * \brief Write 64bit value to address (64 bit) + * \details Write 64 bit value. + * \param [in] addr Address pointer to data + * \param [in] val Value to set + */ +__STATIC_FORCEINLINE void __SD(volatile void *addr, uint64_t val) +{ + __ASM volatile("sd %0, 0(%1)" + : + : "r"(val), "r"(addr)); +} +#endif + +/** + * \brief Compare and Swap 32bit value using LR and SC + * \details Compare old value with memory, if identical, + * store new value in memory. Return the initial value in memory. + * Success is indicated by comparing return value with OLD. + * memory address, return 0 if successful, otherwise return !0 + * \param [in] addr Address pointer to data, address need to be 4byte aligned + * \param [in] oldval Old value of the data in address + * \param [in] newval New value to be stored into the address + * \return return the initial value in memory + */ +__STATIC_FORCEINLINE uint32_t __CAS_W(volatile uint32_t *addr, uint32_t oldval, uint32_t newval) +{ + register uint32_t result; + register uint32_t rc; + + __ASM volatile( + "0: lr.w %0, %2 \n" + " bne %0, %z3, 1f \n" + " sc.w %1, %z4, %2 \n" + " bnez %1, 0b \n" + "1:\n" + : "=&r"(result), "=&r"(rc), "+A"(*addr) + : "r"(oldval), "r"(newval) + : "memory"); + return result; +} + +/** + * \brief Atomic Swap 32bit value into memory + * \details Atomically swap new 32bit value into memory using amoswap.d. + * \param [in] addr Address pointer to data, address need to be 4byte aligned + * \param [in] newval New value to be stored into the address + * \return return the original value in memory + */ +__STATIC_FORCEINLINE uint32_t __AMOSWAP_W(volatile uint32_t *addr, uint32_t newval) +{ + register uint32_t result; + + __ASM volatile("amoswap.w %0, %2, %1" + : "=r"(result), "+A"(*addr) + : "r"(newval) + : "memory"); + return result; +} + +/** + * \brief Atomic Add with 32bit value + * \details Atomically ADD 32bit value with value in memory using amoadd.d. + * \param [in] addr Address pointer to data, address need to be 4byte aligned + * \param [in] value value to be ADDed + * \return return memory value + add value + */ +__STATIC_FORCEINLINE int32_t __AMOADD_W(volatile int32_t *addr, int32_t value) +{ + register int32_t result; + + __ASM volatile("amoadd.w %0, %2, %1" + : "=r"(result), "+A"(*addr) + : "r"(value) + : "memory"); + return *addr; +} + +/** + * \brief Atomic And with 32bit value + * \details Atomically AND 32bit value with value in memory using amoand.d. + * \param [in] addr Address pointer to data, address need to be 4byte aligned + * \param [in] value value to be ANDed + * \return return memory value & and value + */ +__STATIC_FORCEINLINE int32_t __AMOAND_W(volatile int32_t *addr, int32_t value) +{ + register int32_t result; + + __ASM volatile("amoand.w %0, %2, %1" + : "=r"(result), "+A"(*addr) + : "r"(value) + : "memory"); + return *addr; +} + +/** + * \brief Atomic OR with 32bit value + * \details Atomically OR 32bit value with value in memory using amoor.d. + * \param [in] addr Address pointer to data, address need to be 4byte aligned + * \param [in] value value to be ORed + * \return return memory value | and value + */ +__STATIC_FORCEINLINE int32_t __AMOOR_W(volatile int32_t *addr, int32_t value) +{ + register int32_t result; + + __ASM volatile("amoor.w %0, %2, %1" + : "=r"(result), "+A"(*addr) + : "r"(value) + : "memory"); + return *addr; +} + +/** + * \brief Atomic XOR with 32bit value + * \details Atomically XOR 32bit value with value in memory using amoxor.d. + * \param [in] addr Address pointer to data, address need to be 4byte aligned + * \param [in] value value to be XORed + * \return return memory value ^ and value + */ +__STATIC_FORCEINLINE int32_t __AMOXOR_W(volatile int32_t *addr, int32_t value) +{ + register int32_t result; + + __ASM volatile("amoxor.w %0, %2, %1" + : "=r"(result), "+A"(*addr) + : "r"(value) + : "memory"); + return *addr; +} + +/** + * \brief Atomic unsigned MAX with 32bit value + * \details Atomically unsigned max compare 32bit value with value in memory using amomaxu.d. + * \param [in] addr Address pointer to data, address need to be 4byte aligned + * \param [in] value value to be compared + * \return return the bigger value + */ +__STATIC_FORCEINLINE uint32_t __AMOMAXU_W(volatile uint32_t *addr, uint32_t value) +{ + register uint32_t result; + + __ASM volatile("amomaxu.w %0, %2, %1" + : "=r"(result), "+A"(*addr) + : "r"(value) + : "memory"); + return *addr; +} + +/** + * \brief Atomic signed MAX with 32bit value + * \details Atomically signed max compare 32bit value with value in memory using amomax.d. + * \param [in] addr Address pointer to data, address need to be 4byte aligned + * \param [in] value value to be compared + * \return the bigger value + */ +__STATIC_FORCEINLINE int32_t __AMOMAX_W(volatile int32_t *addr, int32_t value) +{ + register int32_t result; + + __ASM volatile("amomax.w %0, %2, %1" + : "=r"(result), "+A"(*addr) + : "r"(value) + : "memory"); + return *addr; +} + +/** + * \brief Atomic unsigned MIN with 32bit value + * \details Atomically unsigned min compare 32bit value with value in memory using amominu.d. + * \param [in] addr Address pointer to data, address need to be 4byte aligned + * \param [in] value value to be compared + * \return the smaller value + */ +__STATIC_FORCEINLINE uint32_t __AMOMINU_W(volatile uint32_t *addr, uint32_t value) +{ + register uint32_t result; + + __ASM volatile("amominu.w %0, %2, %1" + : "=r"(result), "+A"(*addr) + : "r"(value) + : "memory"); + return *addr; +} + +/** + * \brief Atomic signed MIN with 32bit value + * \details Atomically signed min compare 32bit value with value in memory using amomin.d. + * \param [in] addr Address pointer to data, address need to be 4byte aligned + * \param [in] value value to be compared + * \return the smaller value + */ +__STATIC_FORCEINLINE int32_t __AMOMIN_W(volatile int32_t *addr, int32_t value) +{ + register int32_t result; + + __ASM volatile("amomin.w %0, %2, %1" + : "=r"(result), "+A"(*addr) + : "r"(value) + : "memory"); + return *addr; +} + +#if __RISCV_XLEN == 64 +/** + * \brief Compare and Swap 64bit value using LR and SC + * \details Compare old value with memory, if identical, + * store new value in memory. Return the initial value in memory. + * Success is indicated by comparing return value with OLD. + * memory address, return 0 if successful, otherwise return !0 + * \param [in] addr Address pointer to data, address need to be 8byte aligned + * \param [in] oldval Old value of the data in address + * \param [in] newval New value to be stored into the address + * \return return the initial value in memory + */ +__STATIC_FORCEINLINE uint64_t __CAS_D(volatile uint64_t *addr, uint64_t oldval, uint64_t newval) +{ + register uint64_t result; + register uint64_t rc; + + __ASM volatile( + "0: lr.d %0, %2 \n" + " bne %0, %z3, 1f \n" + " sc.d %1, %z4, %2 \n" + " bnez %1, 0b \n" + "1:\n" + : "=&r"(result), "=&r"(rc), "+A"(*addr) + : "r"(oldval), "r"(newval) + : "memory"); + return result; +} + +/** + * \brief Atomic Swap 64bit value into memory + * \details Atomically swap new 64bit value into memory using amoswap.d. + * \param [in] addr Address pointer to data, address need to be 8byte aligned + * \param [in] newval New value to be stored into the address + * \return return the original value in memory + */ +__STATIC_FORCEINLINE uint64_t __AMOSWAP_D(volatile uint64_t *addr, uint64_t newval) +{ + register uint64_t result; + + __ASM volatile("amoswap.d %0, %2, %1" + : "=r"(result), "+A"(*addr) + : "r"(newval) + : "memory"); + return result; +} + +/** + * \brief Atomic Add with 64bit value + * \details Atomically ADD 64bit value with value in memory using amoadd.d. + * \param [in] addr Address pointer to data, address need to be 8byte aligned + * \param [in] value value to be ADDed + * \return return memory value + add value + */ +__STATIC_FORCEINLINE int64_t __AMOADD_D(volatile int64_t *addr, int64_t value) +{ + register int64_t result; + + __ASM volatile("amoadd.d %0, %2, %1" + : "=r"(result), "+A"(*addr) + : "r"(value) + : "memory"); + return *addr; +} + +/** + * \brief Atomic And with 64bit value + * \details Atomically AND 64bit value with value in memory using amoand.d. + * \param [in] addr Address pointer to data, address need to be 8byte aligned + * \param [in] value value to be ANDed + * \return return memory value & and value + */ +__STATIC_FORCEINLINE int64_t __AMOAND_D(volatile int64_t *addr, int64_t value) +{ + register int64_t result; + + __ASM volatile("amoand.d %0, %2, %1" + : "=r"(result), "+A"(*addr) + : "r"(value) + : "memory"); + return *addr; +} + +/** + * \brief Atomic OR with 64bit value + * \details Atomically OR 64bit value with value in memory using amoor.d. + * \param [in] addr Address pointer to data, address need to be 8byte aligned + * \param [in] value value to be ORed + * \return return memory value | and value + */ +__STATIC_FORCEINLINE int64_t __AMOOR_D(volatile int64_t *addr, int64_t value) +{ + register int64_t result; + + __ASM volatile("amoor.d %0, %2, %1" + : "=r"(result), "+A"(*addr) + : "r"(value) + : "memory"); + return *addr; +} + +/** + * \brief Atomic XOR with 64bit value + * \details Atomically XOR 64bit value with value in memory using amoxor.d. + * \param [in] addr Address pointer to data, address need to be 8byte aligned + * \param [in] value value to be XORed + * \return return memory value ^ and value + */ +__STATIC_FORCEINLINE int64_t __AMOXOR_D(volatile int64_t *addr, int64_t value) +{ + register int64_t result; + + __ASM volatile("amoxor.d %0, %2, %1" + : "=r"(result), "+A"(*addr) + : "r"(value) + : "memory"); + return *addr; +} + +/** + * \brief Atomic unsigned MAX with 64bit value + * \details Atomically unsigned max compare 64bit value with value in memory using amomaxu.d. + * \param [in] addr Address pointer to data, address need to be 8byte aligned + * \param [in] value value to be compared + * \return return the bigger value + */ +__STATIC_FORCEINLINE uint64_t __AMOMAXU_D(volatile uint64_t *addr, uint64_t value) +{ + register uint64_t result; + + __ASM volatile("amomaxu.d %0, %2, %1" + : "=r"(result), "+A"(*addr) + : "r"(value) + : "memory"); + return *addr; +} + +/** + * \brief Atomic signed MAX with 64bit value + * \details Atomically signed max compare 64bit value with value in memory using amomax.d. + * \param [in] addr Address pointer to data, address need to be 8byte aligned + * \param [in] value value to be compared + * \return the bigger value + */ +__STATIC_FORCEINLINE int64_t __AMOMAX_D(volatile int64_t *addr, int64_t value) +{ + register int64_t result; + + __ASM volatile("amomax.d %0, %2, %1" + : "=r"(result), "+A"(*addr) + : "r"(value) + : "memory"); + return *addr; +} + +/** + * \brief Atomic unsigned MIN with 64bit value + * \details Atomically unsigned min compare 64bit value with value in memory using amominu.d. + * \param [in] addr Address pointer to data, address need to be 8byte aligned + * \param [in] value value to be compared + * \return the smaller value + */ +__STATIC_FORCEINLINE uint64_t __AMOMINU_D(volatile uint64_t *addr, uint64_t value) +{ + register uint64_t result; + + __ASM volatile("amominu.d %0, %2, %1" + : "=r"(result), "+A"(*addr) + : "r"(value) + : "memory"); + return *addr; +} + +/** + * \brief Atomic signed MIN with 64bit value + * \details Atomically signed min compare 64bit value with value in memory using amomin.d. + * \param [in] addr Address pointer to data, address need to be 8byte aligned + * \param [in] value value to be compared + * \return the smaller value + */ +__STATIC_FORCEINLINE int64_t __AMOMIN_D(volatile int64_t *addr, int64_t value) +{ + register int64_t result; + + __ASM volatile("amomin.d %0, %2, %1" + : "=r"(result), "+A"(*addr) + : "r"(value) + : "memory"); + return *addr; +} +#endif /* __RISCV_XLEN == 64 */ + +/** @} */ /* End of Doxygen Group NMSIS_Core_CPU_Intrinsic */ + +#ifdef __cplusplus +} +#endif +#endif /* __CORE_FEATURE_BASE__ */ diff --git a/components/nmsis/core/inc/core_feature_cache.h b/components/nmsis/core/inc/core_feature_cache.h new file mode 100644 index 00000000..8652337d --- /dev/null +++ b/components/nmsis/core/inc/core_feature_cache.h @@ -0,0 +1,1391 @@ +/* + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef __CORE_FEATURE_CACHE_H__ +#define __CORE_FEATURE_CACHE_H__ +/*! + * @file core_feature_cache.h + * @brief Cache feature API header file for Nuclei N/NX Core + */ +/* + * Cache Feature Configuration Macro: + * 1. __ICACHE_PRESENT: Define whether I-Cache Unit is present or not. + * * 0: Not present + * * 1: Present + * 1. __DCACHE_PRESENT: Define whether D-Cache Unit is present or not. + * * 0: Not present + * * 1: Present + */ +#ifdef __cplusplus + extern "C" { +#endif + +#if (defined(__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1)) \ + || (defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1)) + +/* ########################## Cache functions #################################### */ +/** + * \defgroup NMSIS_Core_Cache Cache Functions + * \brief Functions that configure Instruction and Data Cache. + * @{ + * + * Nuclei provide Cache Control and Maintainence(CCM) for software to control and maintain + * the internal L1 I/D Cache of the RISC-V Core, software can manage the cache flexibly to + * meet the actual application scenarios. + * + * The CCM operations have 3 types: by single address, by all and flush pipeline. + * The CCM operations are done via CSR registers, M/S/U mode has its own CSR registers to + * do CCM operations. By default, CCM operations are not allowed in S/U mode, you can execute + * \ref EnableSUCCM in M-Mode to enable it. + * + * * API names started with M, such as \ref MInvalICacheLine must be called in M-Mode only. + * * API names started with S, such as \ref SInvalICacheLine should be called in S-Mode. + * * API names started with U, such as \ref UInvalICacheLine should be called in U-Mode. + * + */ + + +/** + * \brief Cache CCM Operation Fail Info + */ +typedef enum CCM_OP_FINFO { + CCM_OP_SUCCESS = 0x0, /*!< Lock Succeed */ + CCM_OP_EXCEED_ERR = 0x1, /*!< Exceed the the number of lockable ways(N-Way I/D-Cache, lockable is N-1) */ + CCM_OP_PERM_CHECK_ERR = 0x2, /*!< PMP/sPMP/Page-Table X(I-Cache)/R(D-Cache) permission check failed, or belong to Device/Non-Cacheable address range */ + CCM_OP_REFILL_BUS_ERR = 0x3, /*!< Refill has Bus Error */ + CCM_OP_ECC_ERR = 0x4 /*!< ECC Error */ +} CCM_OP_FINFO_Type; + +/** + * \brief Cache CCM Command Types + */ +typedef enum CCM_CMD { + CCM_DC_INVAL = 0x0, /*!< Unlock and invalidate D-Cache line specified by CSR CCM_XBEGINADDR */ + CCM_DC_WB = 0x1, /*!< Flush the specific D-Cache line specified by CSR CCM_XBEGINADDR */ + CCM_DC_WBINVAL = 0x2, /*!< Unlock, flush and invalidate the specific D-Cache line specified by CSR CCM_XBEGINADDR */ + CCM_DC_LOCK = 0x3, /*!< Lock the specific D-Cache line specified by CSR CCM_XBEGINADDR */ + CCM_DC_UNLOCK = 0x4, /*!< Unlock the specific D-Cache line specified by CSR CCM_XBEGINADDR */ + CCM_DC_WBINVAL_ALL = 0x6, /*!< Unlock and flush and invalidate all the valid and dirty D-Cache lines */ + CCM_DC_WB_ALL = 0x7, /*!< Flush all the valid and dirty D-Cache lines */ + CCM_DC_INVAL_ALL = 0x17, /*!< Unlock and invalidate all the D-Cache lines */ + CCM_IC_INVAL = 0x8, /*!< Unlock and invalidate I-Cache line specified by CSR CCM_XBEGINADDR */ + CCM_IC_LOCK = 0xb, /*!< Lock the specific I-Cache line specified by CSR CCM_XBEGINADDR */ + CCM_IC_UNLOCK = 0xc, /*!< Unlock the specific I-Cache line specified by CSR CCM_XBEGINADDR */ + CCM_IC_INVAL_ALL = 0xd /*!< Unlock and invalidate all the I-Cache lines */ +} CCM_CMD_Type; + +/** + * \brief Cache Information Type + */ +typedef struct CacheInfo { + uint32_t linesize; /*!< Cache Line size in bytes */ + uint32_t ways; /*!< Cache ways */ + uint32_t setperway; /*!< Cache set per way */ + uint32_t size; /*!< Cache total size in bytes */ +} CacheInfo_Type; + +#define CCM_SUEN_SUEN_Pos 0U /*!< CSR CCM_SUEN: SUEN bit Position */ +#define CCM_SUEN_SUEN_Msk (1UL << CCM_SUEN_SUEN_Pos) /*!< CSR CCM_SUEN: SUEN Mask */ + +/** + * \brief Enable CCM operation in Supervisor/User Mode + * \details + * This function enable CCM operation in Supervisor/User Mode. + * If enabled, CCM operations in supervisor/user mode will + * be allowed. + * \remarks + * - This function can be called in M-Mode only. + * \sa + * - \ref DisableSUCCM +*/ +__STATIC_FORCEINLINE void EnableSUCCM(void) +{ + __RV_CSR_SET(CSR_CCM_SUEN, CCM_SUEN_SUEN_Msk); +} + +/** + * \brief Disable CCM operation in Supervisor/User Mode + * \details + * This function disable CCM operation in Supervisor/User Mode. + * If not enabled, CCM operations in supervisor/user mode will + * trigger a *illegal intruction* exception. + * \remarks + * - This function can be called in M-Mode only. + * \sa + * - \ref EnableSUCCM +*/ +__STATIC_FORCEINLINE void DisableSUCCM(void) +{ + __RV_CSR_CLEAR(CSR_CCM_SUEN, CCM_SUEN_SUEN_Msk); +} + +/** + * \brief Flush pipeline after CCM operation + * \details + * This function is used to flush pipeline after CCM operations + * on Cache, it will ensure latest instructions or data can be + * seen by pipeline. + * \remarks + * - This function can be called in M/S/U-Mode only. +*/ +__STATIC_FORCEINLINE void FlushPipeCCM(void) +{ + __RV_CSR_WRITE(CSR_CCM_FPIPE, 0x1); +} +/** @} */ /* End of Doxygen Group NMSIS_Core_Cache */ +#endif + +#if defined(__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1) + +/** + * \defgroup NMSIS_Core_ICache I-Cache Functions + * \ingroup NMSIS_Core_Cache + * \brief Functions that configure Instruction Cache. + * @{ + */ + +/** + * \brief Enable ICache + * \details + * This function enable I-Cache + * \remarks + * - This function can be called in M-Mode only. + * - This \ref CSR_MCACHE_CTL register control I Cache enable. + * \sa + * - \ref DisableICache +*/ +__STATIC_FORCEINLINE void EnableICache(void) +{ + __RV_CSR_SET(CSR_MCACHE_CTL, CSR_MCACHE_CTL_IE); +} + +/** + * \brief Disable ICache + * \details + * This function Disable I-Cache + * \remarks + * - This function can be called in M-Mode only. + * - This \ref CSR_MCACHE_CTL register control I Cache enable. + * \sa + * - \ref EnableICache + */ +__STATIC_FORCEINLINE void DisableICache(void) +{ + __RV_CSR_CLEAR(CSR_MCACHE_CTL, CSR_MCACHE_CTL_IE); +} + +/** + * \brief Get I-Cache Information + * \details + * This function get I-Cache Information + * \remarks + * - This function can be called in M-Mode only. + * - You can use this function in combination with cache lines operations + * \sa + * - \ref GetDCacheInfo + */ +__STATIC_FORCEINLINE int32_t GetICacheInfo(CacheInfo_Type *info) +{ + if (info == NULL) { + return -1; + } + CSR_MICFGINFO_Type csr_ccfg = (CSR_MICFGINFO_Type)__RV_CSR_READ(CSR_MICFG_INFO); + uint32_t info->setperway = (1 << csr_ccfg.b.set) << 3; + uint32_t info->ways = (1 + csr_ccfg.b.way); + if (csr_ccfg.b.lsize == 0) { + info->linesize = 0; + } else { + info->linesize = (1 << (csr_ccfg.b.lsize - 1)) << 3; + } + info->size = info->setperway * info->ways * info->linesize; + return 0; +} + +/** + * \brief Get D-Cache Information + * \details + * This function get D-Cache Information + * \remarks + * - This function can be called in M-Mode only. + * - You can use this function in combination with cache lines operations + * \sa + * - \ref GetICacheInfo + */ +__STATIC_FORCEINLINE int32_t GetDCacheInfo(CacheInfo_Type *info) +{ + if (info == NULL) { + return -1; + } + CSR_MDCFGINFO_Type csr_ccfg = (CSR_MDCFGINFO_Type)__RV_CSR_READ(CSR_MDCFG_INFO); + uint32_t info->setperway = (1 << csr_ccfg.b.set) << 3; + uint32_t info->ways = (1 + csr_ccfg.b.way); + if (csr_ccfg.b.lsize == 0) { + info->linesize = 0; + } else { + info->linesize = (1 << (csr_ccfg.b.lsize - 1)) << 3; + } + info->size = info->setperway * info->ways * info->linesize; + return 0; +} + +/** + * \brief Invalidate one I-Cache line specified by address in M-Mode + * \details + * This function unlock and invalidate one I-Cache line specified + * by the address. + * Command \ref CCM_IC_INVAL is written to CSR \ref CSR_CCM_MCOMMAND. + * \remarks + * This function must be executed in M-Mode only. + * \param [in] addr start address to be invalidated + */ +__STATIC_FORCEINLINE void MInvalICacheLine(unsigned long addr) +{ + __RV_CSR_WRITE(CSR_CCM_MBEGINADDR, addr); + __RV_CSR_WRITE(CSR_CCM_MCOMMAND, CCM_IC_INVAL); +} + +/** + * \brief Invalidate several I-Cache lines specified by address in M-Mode + * \details + * This function unlock and invalidate several I-Cache lines specified + * by the address and line count. + * Command \ref CCM_IC_INVAL is written to CSR \ref CSR_CCM_MCOMMAND. + * \remarks + * This function must be executed in M-Mode only. + * \param [in] addr start address to be invalidated + * \param [in] cnt count of cache lines to be invalidated + */ +__STATIC_FORCEINLINE void MInvalICacheLines(unsigned long addr, unsigned long cnt) +{ + if (cnt > 0) { + unsigned long i; + __RV_CSR_WRITE(CSR_CCM_MBEGINADDR, addr); + for (i = 0; i < cnt; i++) { + __RV_CSR_WRITE(CSR_CCM_MCOMMAND, CCM_IC_INVAL); + } + } +} + +/** + * \brief Invalidate one I-Cache line specified by address in S-Mode + * \details + * This function unlock and invalidate one I-Cache line specified + * by the address. + * Command \ref CCM_IC_INVAL is written to CSR \ref CSR_CCM_SCOMMAND. + * \remarks + * This function must be executed in M/S-Mode only. + * \param [in] addr start address to be invalidated + */ +__STATIC_FORCEINLINE void SInvalICacheLine(unsigned long addr) +{ + __RV_CSR_WRITE(CSR_CCM_SBEGINADDR, addr); + __RV_CSR_WRITE(CSR_CCM_SCOMMAND, CCM_IC_INVAL); +} + +/** + * \brief Invalidate several I-Cache lines specified by address in S-Mode + * \details + * This function unlock and invalidate several I-Cache lines specified + * by the address and line count. + * Command \ref CCM_IC_INVAL is written to CSR \ref CSR_CCM_SCOMMAND. + * \remarks + * This function must be executed in M/S-Mode only. + * \param [in] addr start address to be invalidated + * \param [in] cnt count of cache lines to be invalidated + */ +__STATIC_FORCEINLINE void SInvalICacheLines(unsigned long addr, unsigned long cnt) +{ + if (cnt > 0) { + unsigned long i; + __RV_CSR_WRITE(CSR_CCM_SBEGINADDR, addr); + for (i = 0; i < cnt; i++) { + __RV_CSR_WRITE(CSR_CCM_SCOMMAND, CCM_IC_INVAL); + } + } +} + +/** + * \brief Invalidate one I-Cache line specified by address in U-Mode + * \details + * This function unlock and invalidate one I-Cache line specified + * by the address. + * Command \ref CCM_IC_INVAL is written to CSR \ref CSR_CCM_UCOMMAND. + * \remarks + * This function must be executed in M/S/U-Mode only. + * \param [in] addr start address to be invalidated + */ +__STATIC_FORCEINLINE void UInvalICacheLine(unsigned long addr) +{ + __RV_CSR_WRITE(CSR_CCM_UBEGINADDR, addr); + __RV_CSR_WRITE(CSR_CCM_UCOMMAND, CCM_IC_INVAL); +} + +/** + * \brief Invalidate several I-Cache lines specified by address in U-Mode + * \details + * This function unlock and invalidate several I-Cache lines specified + * by the address and line count. + * Command \ref CCM_IC_INVAL is written to CSR \ref CSR_CCM_UCOMMAND. + * \remarks + * This function must be executed in M/S/U-Mode only. + * \param [in] addr start address to be invalidated + * \param [in] cnt count of cache lines to be invalidated + */ +__STATIC_FORCEINLINE void UInvalICacheLines(unsigned long addr, unsigned long cnt) +{ + if (cnt > 0) { + unsigned long i; + __RV_CSR_WRITE(CSR_CCM_UBEGINADDR, addr); + for (i = 0; i < cnt; i++) { + __RV_CSR_WRITE(CSR_CCM_UCOMMAND, CCM_IC_INVAL); + } + } +} + +/** + * \brief Lock one I-Cache line specified by address in M-Mode + * \details + * This function lock one I-Cache line specified by the address. + * Command \ref CCM_IC_LOCK is written to CSR \ref CSR_CCM_MCOMMAND. + * \remarks + * This function must be executed in M-Mode only. + * \param [in] addr start address to be locked + * \return result of CCM lock operation, see enum \ref CCM_OP_FINFO + */ +__STATIC_FORCEINLINE unsigned long MLockICacheLine(unsigned long addr) +{ + __RV_CSR_WRITE(CSR_CCM_MBEGINADDR, addr); + __RV_CSR_WRITE(CSR_CCM_MCOMMAND, CCM_IC_LOCK); + return __RV_CSR_READ(CSR_CCM_MDATA); +} + +/** + * \brief Lock several I-Cache lines specified by address in M-Mode + * \details + * This function lock several I-Cache lines specified by the address + * and line count. + * Command \ref CCM_IC_LOCK is written to CSR \ref CSR_CCM_MCOMMAND. + * \remarks + * This function must be executed in M-Mode only. + * \param [in] addr start address to be locked + * \param [in] cnt count of cache lines to be locked + * \return result of CCM lock operation, see enum \ref CCM_OP_FINFO + */ +__STATIC_FORCEINLINE unsigned long MLockICacheLines(unsigned long addr, unsigned long cnt) +{ + if (cnt > 0) { + unsigned long i; + __RV_CSR_WRITE(CSR_CCM_MBEGINADDR, addr); + for (i = 0; i < cnt; i++) { + __RV_CSR_WRITE(CSR_CCM_MCOMMAND, CCM_IC_LOCK); + } + return __RV_CSR_READ(CSR_CCM_MDATA); + } else { + return 0; + } +} + +/** + * \brief Lock one I-Cache line specified by address in S-Mode + * \details + * This function lock one I-Cache line specified by the address. + * Command \ref CCM_IC_LOCK is written to CSR \ref CSR_CCM_SCOMMAND. + * \remarks + * This function must be executed in M/S-Mode only. + * \param [in] addr start address to be locked + * \return result of CCM lock operation, see enum \ref CCM_OP_FINFO + */ +__STATIC_FORCEINLINE unsigned long SLockICacheLine(unsigned long addr) +{ + __RV_CSR_WRITE(CSR_CCM_SBEGINADDR, addr); + __RV_CSR_WRITE(CSR_CCM_SCOMMAND, CCM_IC_LOCK); + return __RV_CSR_READ(CSR_CCM_SDATA); +} + +/** + * \brief Lock several I-Cache lines specified by address in S-Mode + * \details + * This function lock several I-Cache lines specified by the address + * and line count. + * Command \ref CCM_IC_LOCK is written to CSR \ref CSR_CCM_SCOMMAND. + * \remarks + * This function must be executed in M/S-Mode only. + * \param [in] addr start address to be locked + * \param [in] cnt count of cache lines to be locked + * \return result of CCM lock operation, see enum \ref CCM_OP_FINFO + */ +__STATIC_FORCEINLINE unsigned long SLockICacheLines(unsigned long addr, unsigned long cnt) +{ + if (cnt > 0) { + unsigned long i; + __RV_CSR_WRITE(CSR_CCM_SBEGINADDR, addr); + for (i = 0; i < cnt; i++) { + __RV_CSR_WRITE(CSR_CCM_SCOMMAND, CCM_IC_LOCK); + } + return __RV_CSR_READ(CSR_CCM_SDATA); + } else { + return 0; + } +} + +/** + * \brief Lock one I-Cache line specified by address in U-Mode + * \details + * This function lock one I-Cache line specified by the address. + * Command \ref CCM_IC_LOCK is written to CSR \ref CSR_CCM_UCOMMAND. + * \remarks + * This function must be executed in M/S/U-Mode only. + * \param [in] addr start address to be locked + * \return result of CCM lock operation, see enum \ref CCM_OP_FINFO + */ +__STATIC_FORCEINLINE unsigned long ULockICacheLine(unsigned long addr) +{ + __RV_CSR_WRITE(CSR_CCM_UBEGINADDR, addr); + __RV_CSR_WRITE(CSR_CCM_UCOMMAND, CCM_IC_LOCK); + return __RV_CSR_READ(CSR_CCM_UDATA); +} + +/** + * \brief Lock several I-Cache lines specified by address in U-Mode + * \details + * This function lock several I-Cache lines specified by the address + * and line count. + * Command \ref CCM_IC_LOCK is written to CSR \ref CSR_CCM_UCOMMAND. + * \remarks + * This function must be executed in M/S/U-Mode only. + * \param [in] addr start address to be locked + * \param [in] cnt count of cache lines to be locked + * \return result of CCM lock operation, see enum \ref CCM_OP_FINFO + */ +__STATIC_FORCEINLINE unsigned long ULockICacheLines(unsigned long addr, unsigned long cnt) +{ + if (cnt > 0) { + unsigned long i; + __RV_CSR_WRITE(CSR_CCM_UBEGINADDR, addr); + for (i = 0; i < cnt; i++) { + __RV_CSR_WRITE(CSR_CCM_UCOMMAND, CCM_IC_LOCK); + } + return __RV_CSR_READ(CSR_CCM_UDATA); + } else { + return 0; + } +} + +/** + * \brief Unlock one I-Cache line specified by address in M-Mode + * \details + * This function unlock one I-Cache line specified by the address. + * Command \ref CCM_IC_UNLOCK is written to CSR \ref CSR_CCM_MCOMMAND. + * \remarks + * This function must be executed in M-Mode only. + * \param [in] addr start address to be unlocked + */ +__STATIC_FORCEINLINE void MUnlockICacheLine(unsigned long addr) +{ + __RV_CSR_WRITE(CSR_CCM_MBEGINADDR, addr); + __RV_CSR_WRITE(CSR_CCM_MCOMMAND, CCM_IC_UNLOCK); +} + +/** + * \brief Unlock several I-Cache lines specified by address in M-Mode + * \details + * This function unlock several I-Cache lines specified + * by the address and line count. + * Command \ref CCM_IC_UNLOCK is written to CSR \ref CSR_CCM_MCOMMAND. + * \remarks + * This function must be executed in M-Mode only. + * \param [in] addr start address to be unlocked + * \param [in] cnt count of cache lines to be unlocked + */ +__STATIC_FORCEINLINE void MUnlockICacheLines(unsigned long addr, unsigned long cnt) +{ + if (cnt > 0) { + unsigned long i; + __RV_CSR_WRITE(CSR_CCM_MBEGINADDR, addr); + for (i = 0; i < cnt; i++) { + __RV_CSR_WRITE(CSR_CCM_MCOMMAND, CCM_IC_UNLOCK); + } + } +} + +/** + * \brief Unlock one I-Cache line specified by address in S-Mode + * \details + * This function unlock one I-Cache line specified by the address. + * Command \ref CCM_IC_UNLOCK is written to CSR \ref CSR_CCM_SCOMMAND. + * \remarks + * This function must be executed in M/S-Mode only. + * \param [in] addr start address to be unlocked + */ +__STATIC_FORCEINLINE void SUnlockICacheLine(unsigned long addr) +{ + __RV_CSR_WRITE(CSR_CCM_SBEGINADDR, addr); + __RV_CSR_WRITE(CSR_CCM_SCOMMAND, CCM_IC_UNLOCK); +} + +/** + * \brief Unlock several I-Cache lines specified by address in S-Mode + * \details + * This function unlock several I-Cache lines specified + * by the address and line count. + * Command \ref CCM_IC_UNLOCK is written to CSR \ref CSR_CCM_SCOMMAND. + * \remarks + * This function must be executed in M/S-Mode only. + * \param [in] addr start address to be unlocked + * \param [in] cnt count of cache lines to be unlocked + */ +__STATIC_FORCEINLINE void SUnlockICacheLines(unsigned long addr, unsigned long cnt) +{ + if (cnt > 0) { + unsigned long i; + __RV_CSR_WRITE(CSR_CCM_SBEGINADDR, addr); + for (i = 0; i < cnt; i++) { + __RV_CSR_WRITE(CSR_CCM_SCOMMAND, CCM_IC_UNLOCK); + } + } +} + +/** + * \brief Unlock one I-Cache line specified by address in U-Mode + * \details + * This function unlock one I-Cache line specified by the address. + * Command \ref CCM_IC_UNLOCK is written to CSR \ref CSR_CCM_UCOMMAND. + * \remarks + * This function must be executed in M/S/U-Mode only. + * \param [in] addr start address to be unlocked + */ +__STATIC_FORCEINLINE void UUnlockICacheLine(unsigned long addr) +{ + __RV_CSR_WRITE(CSR_CCM_UBEGINADDR, addr); + __RV_CSR_WRITE(CSR_CCM_UCOMMAND, CCM_IC_UNLOCK); +} + +/** + * \brief Unlock several I-Cache lines specified by address in U-Mode + * \details + * This function unlock several I-Cache lines specified + * by the address and line count. + * Command \ref CCM_IC_UNLOCK is written to CSR \ref CSR_CCM_UCOMMAND. + * \remarks + * This function must be executed in M/S/U-Mode only. + * \param [in] addr start address to be unlocked + * \param [in] cnt count of cache lines to be unlocked + */ +__STATIC_FORCEINLINE void UUnlockICacheLines(unsigned long addr, unsigned long cnt) +{ + if (cnt > 0) { + unsigned long i; + __RV_CSR_WRITE(CSR_CCM_UBEGINADDR, addr); + for (i = 0; i < cnt; i++) { + __RV_CSR_WRITE(CSR_CCM_UCOMMAND, CCM_IC_UNLOCK); + } + } +} + +/** + * \brief Invalidate all I-Cache lines in M-Mode + * \details + * This function invalidate all I-Cache lines. + * Command \ref CCM_IC_INVAL_ALL is written to CSR \ref CSR_CCM_MCOMMAND. + * \remarks + * This function must be executed in M-Mode only. + * \param [in] addr start address to be invalidated + */ +__STATIC_FORCEINLINE void MInvalICache(void) +{ + __RV_CSR_WRITE(CSR_CCM_MCOMMAND, CCM_IC_INVAL_ALL); +} + +/** + * \brief Invalidate all I-Cache lines in S-Mode + * \details + * This function invalidate all I-Cache lines. + * Command \ref CCM_IC_INVAL_ALL is written to CSR \ref CSR_CCM_SCOMMAND. + * \remarks + * This function must be executed in M/S-Mode only. + * \param [in] addr start address to be invalidated + */ +__STATIC_FORCEINLINE void SInvalICache(void) +{ + __RV_CSR_WRITE(CSR_CCM_SCOMMAND, CCM_IC_INVAL_ALL); +} + +/** + * \brief Invalidate all I-Cache lines in U-Mode + * \details + * This function invalidate all I-Cache lines. + * Command \ref CCM_IC_INVAL_ALL is written to CSR \ref CSR_CCM_UCOMMAND. + * \remarks + * This function must be executed in M/S/U-Mode only. + * \param [in] addr start address to be invalidated + */ +__STATIC_FORCEINLINE void UInvalICache(void) +{ + __RV_CSR_WRITE(CSR_CCM_UCOMMAND, CCM_IC_INVAL_ALL); +} + +/** @} */ /* End of Doxygen Group NMSIS_Core_ICache */ +#endif /* defined(__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1) */ + +#if defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1) +/** + * \defgroup NMSIS_Core_DCache D-Cache Functions + * \ingroup NMSIS_Core_Cache + * \brief Functions that configure Data Cache. + * @{ + */ +/** + * \brief Enable DCache + * \details + * This function enable D-Cache + * \remarks + * - This function can be called in M-Mode only. + * - This \ref CSR_MCACHE_CTL register control D Cache enable. + * \sa + * - \ref DisableDCache +*/ +__STATIC_FORCEINLINE void EnableDCache(void) +{ + __RV_CSR_SET(CSR_MCACHE_CTL, CSR_MCACHE_CTL_DE); +} + +/** + * \brief Disable DCache + * \details + * This function Disable D-Cache + * \remarks + * - This function can be called in M-Mode only. + * - This \ref CSR_MCACHE_CTL register control D Cache enable. + * \sa + * - \ref EnableDCache + */ +__STATIC_FORCEINLINE void DisableDCache(void) +{ + __RV_CSR_CLEAR(CSR_MCACHE_CTL, CSR_MCACHE_CTL_DE); +} + +/** + * \brief Invalidate one D-Cache line specified by address in M-Mode + * \details + * This function unlock and invalidate one D-Cache line specified + * by the address. + * Command \ref CCM_DC_INVAL is written to CSR \ref CSR_CCM_MCOMMAND. + * \remarks + * This function must be executed in M-Mode only. + * \param [in] addr start address to be invalidated + */ +__STATIC_FORCEINLINE void MInvalDCacheLine(unsigned long addr) +{ + __RV_CSR_WRITE(CSR_CCM_MBEGINADDR, addr); + __RV_CSR_WRITE(CSR_CCM_MCOMMAND, CCM_DC_INVAL); +} + +/** + * \brief Invalidate several D-Cache lines specified by address in M-Mode + * \details + * This function unlock and invalidate several D-Cache lines specified + * by the address and line count. + * Command \ref CCM_DC_INVAL is written to CSR \ref CSR_CCM_MCOMMAND. + * \remarks + * This function must be executed in M-Mode only. + * \param [in] addr start address to be invalidated + * \param [in] cnt count of cache lines to be invalidated + */ +__STATIC_FORCEINLINE void MInvalDCacheLines(unsigned long addr, unsigned long cnt) +{ + if (cnt > 0) { + unsigned long i; + __RV_CSR_WRITE(CSR_CCM_MBEGINADDR, addr); + for (i = 0; i < cnt; i++) { + __RV_CSR_WRITE(CSR_CCM_MCOMMAND, CCM_DC_INVAL); + } + } +} + +/** + * \brief Invalidate one D-Cache line specified by address in S-Mode + * \details + * This function unlock and invalidate one D-Cache line specified + * by the address. + * Command \ref CCM_DC_INVAL is written to CSR \ref CSR_CCM_MCOMMAND. + * \remarks + * This function must be executed in M/S-Mode only. + * \param [in] addr start address to be invalidated + */ +__STATIC_FORCEINLINE void SInvalDCacheLine(unsigned long addr) +{ + __RV_CSR_WRITE(CSR_CCM_SBEGINADDR, addr); + __RV_CSR_WRITE(CSR_CCM_SCOMMAND, CCM_DC_INVAL); +} + +/** + * \brief Invalidate several D-Cache lines specified by address in S-Mode + * \details + * This function unlock and invalidate several D-Cache lines specified + * by the address and line count. + * Command \ref CCM_DC_INVAL is written to CSR \ref CSR_CCM_SCOMMAND. + * \remarks + * This function must be executed in M/S-Mode only. + * \param [in] addr start address to be invalidated + * \param [in] cnt count of cache lines to be invalidated + */ +__STATIC_FORCEINLINE void SInvalDCacheLines(unsigned long addr, unsigned long cnt) +{ + if (cnt > 0) { + unsigned long i; + __RV_CSR_WRITE(CSR_CCM_SBEGINADDR, addr); + for (i = 0; i < cnt; i++) { + __RV_CSR_WRITE(CSR_CCM_SCOMMAND, CCM_DC_INVAL); + } + } +} + +/** + * \brief Invalidate one D-Cache line specified by address in U-Mode + * \details + * This function unlock and invalidate one D-Cache line specified + * by the address. + * Command \ref CCM_DC_INVAL is written to CSR \ref CSR_CCM_UCOMMAND. + * \remarks + * This function must be executed in M/S/U-Mode only. + * \param [in] addr start address to be invalidated + */ +__STATIC_FORCEINLINE void UInvalDCacheLine(unsigned long addr) +{ + __RV_CSR_WRITE(CSR_CCM_UBEGINADDR, addr); + __RV_CSR_WRITE(CSR_CCM_UCOMMAND, CCM_DC_INVAL); +} + +/** + * \brief Invalidate several D-Cache lines specified by address in U-Mode + * \details + * This function unlock and invalidate several D-Cache lines specified + * by the address and line count. + * Command \ref CCM_DC_INVAL is written to CSR \ref CSR_CCM_UCOMMAND. + * \remarks + * This function must be executed in M/S/U-Mode only. + * \param [in] addr start address to be invalidated + * \param [in] cnt count of cache lines to be invalidated + */ +__STATIC_FORCEINLINE void UInvalDCacheLines(unsigned long addr, unsigned long cnt) +{ + if (cnt > 0) { + unsigned long i; + __RV_CSR_WRITE(CSR_CCM_UBEGINADDR, addr); + for (i = 0; i < cnt; i++) { + __RV_CSR_WRITE(CSR_CCM_UCOMMAND, CCM_DC_INVAL); + } + } +} + +/** + * \brief Flush one D-Cache line specified by address in M-Mode + * \details + * This function flush one D-Cache line specified by the address. + * Command \ref CCM_DC_WB is written to CSR \ref CSR_CCM_MCOMMAND. + * \remarks + * This function must be executed in M-Mode only. + * \param [in] addr start address to be flushed + */ +__STATIC_FORCEINLINE void MFlushDCacheLine(unsigned long addr) +{ + __RV_CSR_WRITE(CSR_CCM_MBEGINADDR, addr); + __RV_CSR_WRITE(CSR_CCM_MCOMMAND, CCM_DC_WB); +} + +/** + * \brief Flush several D-Cache lines specified by address in M-Mode + * \details + * This function flush several D-Cache lines specified + * by the address and line count. + * Command \ref CCM_DC_WB is written to CSR \ref CSR_CCM_MCOMMAND. + * \remarks + * This function must be executed in M-Mode only. + * \param [in] addr start address to be flushed + * \param [in] cnt count of cache lines to be flushed + */ +__STATIC_FORCEINLINE void MFlushDCacheLines(unsigned long addr, unsigned long cnt) +{ + if (cnt > 0) { + unsigned long i; + __RV_CSR_WRITE(CSR_CCM_MBEGINADDR, addr); + for (i = 0; i < cnt; i++) { + __RV_CSR_WRITE(CSR_CCM_MCOMMAND, CCM_DC_WB); + } + } +} + +/** + * \brief Flush one D-Cache line specified by address in S-Mode + * \details + * This function flush one D-Cache line specified by the address. + * Command \ref CCM_DC_WB is written to CSR \ref CSR_CCM_SCOMMAND. + * \remarks + * This function must be executed in M/S-Mode only. + * \param [in] addr start address to be flushed + */ +__STATIC_FORCEINLINE void SFlushDCacheLine(unsigned long addr) +{ + __RV_CSR_WRITE(CSR_CCM_SBEGINADDR, addr); + __RV_CSR_WRITE(CSR_CCM_SCOMMAND, CCM_DC_WB); +} + +/** + * \brief Flush several D-Cache lines specified by address in S-Mode + * \details + * This function flush several D-Cache lines specified + * by the address and line count. + * Command \ref CCM_DC_WB is written to CSR \ref CSR_CCM_SCOMMAND. + * \remarks + * This function must be executed in M/S-Mode only. + * \param [in] addr start address to be flushed + * \param [in] cnt count of cache lines to be flushed + */ +__STATIC_FORCEINLINE void SFlushDCacheLines(unsigned long addr, unsigned long cnt) +{ + if (cnt > 0) { + unsigned long i; + __RV_CSR_WRITE(CSR_CCM_SBEGINADDR, addr); + for (i = 0; i < cnt; i++) { + __RV_CSR_WRITE(CSR_CCM_SCOMMAND, CCM_DC_WB); + } + } +} + +/** + * \brief Flush one D-Cache line specified by address in U-Mode + * \details + * This function flush one D-Cache line specified by the address. + * Command \ref CCM_DC_WB is written to CSR \ref CSR_CCM_UCOMMAND. + * \remarks + * This function must be executed in M/S/U-Mode only. + * \param [in] addr start address to be flushed + */ +__STATIC_FORCEINLINE void UFlushDCacheLine(unsigned long addr) +{ + __RV_CSR_WRITE(CSR_CCM_UBEGINADDR, addr); + __RV_CSR_WRITE(CSR_CCM_UCOMMAND, CCM_DC_WB); +} + +/** + * \brief Flush several D-Cache lines specified by address in U-Mode + * \details + * This function flush several D-Cache lines specified + * by the address and line count. + * Command \ref CCM_DC_WB is written to CSR \ref CSR_CCM_UCOMMAND. + * \remarks + * This function must be executed in M/S/U-Mode only. + * \param [in] addr start address to be flushed + * \param [in] cnt count of cache lines to be flushed + */ +__STATIC_FORCEINLINE void UFlushDCacheLines(unsigned long addr, unsigned long cnt) +{ + if (cnt > 0) { + unsigned long i; + __RV_CSR_WRITE(CSR_CCM_UBEGINADDR, addr); + for (i = 0; i < cnt; i++) { + __RV_CSR_WRITE(CSR_CCM_UCOMMAND, CCM_DC_WB); + } + } +} + +/** + * \brief Flush and invalidate one D-Cache line specified by address in M-Mode + * \details + * This function flush and invalidate one D-Cache line specified by the address. + * Command \ref CCM_DC_WBINVAL is written to CSR \ref CSR_CCM_MCOMMAND. + * \remarks + * This function must be executed in M-Mode only. + * \param [in] addr start address to be flushed and invalidated + */ +__STATIC_FORCEINLINE void MFlushInvalDCacheLine(unsigned long addr) +{ + __RV_CSR_WRITE(CSR_CCM_MBEGINADDR, addr); + __RV_CSR_WRITE(CSR_CCM_MCOMMAND, CCM_DC_WBINVAL); +} + +/** + * \brief Flush and invalidate several D-Cache lines specified by address in M-Mode + * \details + * This function flush and invalidate several D-Cache lines specified + * by the address and line count. + * Command \ref CCM_DC_WBINVAL is written to CSR \ref CSR_CCM_MCOMMAND. + * \remarks + * This function must be executed in M-Mode only. + * \param [in] addr start address to be flushed and invalidated + * \param [in] cnt count of cache lines to be flushed and invalidated + */ +__STATIC_FORCEINLINE void MFlushInvalDCacheLines(unsigned long addr, unsigned long cnt) +{ + if (cnt > 0) { + unsigned long i; + __RV_CSR_WRITE(CSR_CCM_MBEGINADDR, addr); + for (i = 0; i < cnt; i++) { + __RV_CSR_WRITE(CSR_CCM_MCOMMAND, CCM_DC_WBINVAL); + } + } +} + +/** + * \brief Flush and invalidate one D-Cache line specified by address in S-Mode + * \details + * This function flush and invalidate one D-Cache line specified by the address. + * Command \ref CCM_DC_WBINVAL is written to CSR \ref CSR_CCM_SCOMMAND. + * \remarks + * This function must be executed in M/S-Mode only. + * \param [in] addr start address to be flushed and invalidated + */ +__STATIC_FORCEINLINE void SFlushInvalDCacheLine(unsigned long addr) +{ + __RV_CSR_WRITE(CSR_CCM_SBEGINADDR, addr); + __RV_CSR_WRITE(CSR_CCM_SCOMMAND, CCM_DC_WBINVAL); +} + +/** + * \brief Flush and invalidate several D-Cache lines specified by address in S-Mode + * \details + * This function flush and invalidate several D-Cache lines specified + * by the address and line count. + * Command \ref CCM_DC_WBINVAL is written to CSR \ref CSR_CCM_SCOMMAND. + * \remarks + * This function must be executed in M/S-Mode only. + * \param [in] addr start address to be flushed and invalidated + * \param [in] cnt count of cache lines to be flushed and invalidated + */ +__STATIC_FORCEINLINE void SFlushInvalDCacheLines(unsigned long addr, unsigned long cnt) +{ + if (cnt > 0) { + unsigned long i; + __RV_CSR_WRITE(CSR_CCM_SBEGINADDR, addr); + for (i = 0; i < cnt; i++) { + __RV_CSR_WRITE(CSR_CCM_SCOMMAND, CCM_DC_WBINVAL); + } + } +} + +/** + * \brief Flush and invalidate one D-Cache line specified by address in U-Mode + * \details + * This function flush and invalidate one D-Cache line specified by the address. + * Command \ref CCM_DC_WBINVAL is written to CSR \ref CSR_CCM_UCOMMAND. + * \remarks + * This function must be executed in M/S/U-Mode only. + * \param [in] addr start address to be flushed and invalidated + */ +__STATIC_FORCEINLINE void UFlushInvalDCacheLine(unsigned long addr) +{ + __RV_CSR_WRITE(CSR_CCM_UBEGINADDR, addr); + __RV_CSR_WRITE(CSR_CCM_UCOMMAND, CCM_DC_WBINVAL); +} + +/** + * \brief Flush and invalidate several D-Cache lines specified by address in U-Mode + * \details + * This function flush and invalidate several D-Cache lines specified + * by the address and line count. + * Command \ref CCM_DC_WBINVAL is written to CSR \ref CSR_CCM_UCOMMAND. + * \remarks + * This function must be executed in M/S/U-Mode only. + * \param [in] addr start address to be flushed and invalidated + * \param [in] cnt count of cache lines to be flushed and invalidated + */ +__STATIC_FORCEINLINE void UFlushInvalDCacheLines(unsigned long addr, unsigned long cnt) +{ + if (cnt > 0) { + unsigned long i; + __RV_CSR_WRITE(CSR_CCM_UBEGINADDR, addr); + for (i = 0; i < cnt; i++) { + __RV_CSR_WRITE(CSR_CCM_UCOMMAND, CCM_DC_WBINVAL); + } + } +} + +/** + * \brief Lock one D-Cache line specified by address in M-Mode + * \details + * This function lock one D-Cache line specified by the address. + * Command \ref CCM_DC_LOCK is written to CSR \ref CSR_CCM_MCOMMAND. + * \remarks + * This function must be executed in M-Mode only. + * \param [in] addr start address to be locked + * \return result of CCM lock operation, see enum \ref CCM_OP_FINFO + */ +__STATIC_FORCEINLINE unsigned long MLockDCacheLine(unsigned long addr) +{ + __RV_CSR_WRITE(CSR_CCM_MBEGINADDR, addr); + __RV_CSR_WRITE(CSR_CCM_MCOMMAND, CCM_DC_LOCK); + return __RV_CSR_READ(CSR_CCM_MDATA); +} + +/** + * \brief Lock several D-Cache lines specified by address in M-Mode + * \details + * This function lock several D-Cache lines specified by the address + * and line count. + * Command \ref CCM_DC_LOCK is written to CSR \ref CSR_CCM_MCOMMAND. + * \remarks + * This function must be executed in M-Mode only. + * \param [in] addr start address to be locked + * \param [in] cnt count of cache lines to be locked + * \return result of CCM lock operation, see enum \ref CCM_OP_FINFO + */ +__STATIC_FORCEINLINE unsigned long MLockDCacheLines(unsigned long addr, unsigned long cnt) +{ + if (cnt > 0) { + unsigned long i; + __RV_CSR_WRITE(CSR_CCM_MBEGINADDR, addr); + for (i = 0; i < cnt; i++) { + __RV_CSR_WRITE(CSR_CCM_MCOMMAND, CCM_DC_LOCK); + } + return __RV_CSR_READ(CSR_CCM_MDATA); + } else { + return 0; + } +} + +/** + * \brief Lock one D-Cache line specified by address in S-Mode + * \details + * This function lock one D-Cache line specified by the address. + * Command \ref CCM_DC_LOCK is written to CSR \ref CSR_CCM_SCOMMAND. + * \remarks + * This function must be executed in M/S-Mode only. + * \param [in] addr start address to be locked + * \return result of CCM lock operation, see enum \ref CCM_OP_FINFO + */ +__STATIC_FORCEINLINE unsigned long SLockDCacheLine(unsigned long addr) +{ + __RV_CSR_WRITE(CSR_CCM_SBEGINADDR, addr); + __RV_CSR_WRITE(CSR_CCM_SCOMMAND, CCM_DC_LOCK); + return __RV_CSR_READ(CSR_CCM_SDATA); +} + +/** + * \brief Lock several D-Cache lines specified by address in S-Mode + * \details + * This function lock several D-Cache lines specified by the address + * and line count. + * Command \ref CCM_DC_LOCK is written to CSR \ref CSR_CCM_SCOMMAND. + * \remarks + * This function must be executed in M/S-Mode only. + * \param [in] addr start address to be locked + * \param [in] cnt count of cache lines to be locked + * \return result of CCM lock operation, see enum \ref CCM_OP_FINFO + */ +__STATIC_FORCEINLINE unsigned long SLockDCacheLines(unsigned long addr, unsigned long cnt) +{ + if (cnt > 0) { + unsigned long i; + __RV_CSR_WRITE(CSR_CCM_SBEGINADDR, addr); + for (i = 0; i < cnt; i++) { + __RV_CSR_WRITE(CSR_CCM_SCOMMAND, CCM_DC_LOCK); + } + return __RV_CSR_READ(CSR_CCM_SDATA); + } else { + return 0; + } +} + +/** + * \brief Lock one D-Cache line specified by address in U-Mode + * \details + * This function lock one D-Cache line specified by the address. + * Command \ref CCM_DC_LOCK is written to CSR \ref CSR_CCM_UCOMMAND. + * \remarks + * This function must be executed in M/S/U-Mode only. + * \param [in] addr start address to be locked + * \return result of CCM lock operation, see enum \ref CCM_OP_FINFO + */ +__STATIC_FORCEINLINE unsigned long ULockDCacheLine(unsigned long addr) +{ + __RV_CSR_WRITE(CSR_CCM_UBEGINADDR, addr); + __RV_CSR_WRITE(CSR_CCM_UCOMMAND, CCM_DC_LOCK); + return __RV_CSR_READ(CSR_CCM_UDATA); +} + +/** + * \brief Lock several D-Cache lines specified by address in U-Mode + * \details + * This function lock several D-Cache lines specified by the address + * and line count. + * Command \ref CCM_DC_LOCK is written to CSR \ref CSR_CCM_UCOMMAND. + * \remarks + * This function must be executed in M/S/U-Mode only. + * \param [in] addr start address to be locked + * \param [in] cnt count of cache lines to be locked + * \return result of CCM lock operation, see enum \ref CCM_OP_FINFO + */ +__STATIC_FORCEINLINE unsigned long ULockDCacheLines(unsigned long addr, unsigned long cnt) +{ + if (cnt > 0) { + unsigned long i; + __RV_CSR_WRITE(CSR_CCM_UBEGINADDR, addr); + for (i = 0; i < cnt; i++) { + __RV_CSR_WRITE(CSR_CCM_UCOMMAND, CCM_DC_LOCK); + } + return __RV_CSR_READ(CSR_CCM_UDATA); + } else { + return 0; + } +} + +/** + * \brief Unlock one D-Cache line specified by address in M-Mode + * \details + * This function unlock one D-Cache line specified by the address. + * Command \ref CCM_DC_UNLOCK is written to CSR \ref CSR_CCM_MCOMMAND. + * \remarks + * This function must be executed in M-Mode only. + * \param [in] addr start address to be unlocked + */ +__STATIC_FORCEINLINE void MUnlockDCacheLine(unsigned long addr) +{ + __RV_CSR_WRITE(CSR_CCM_MBEGINADDR, addr); + __RV_CSR_WRITE(CSR_CCM_MCOMMAND, CCM_DC_UNLOCK); +} + +/** + * \brief Unlock several D-Cache lines specified by address in M-Mode + * \details + * This function unlock several D-Cache lines specified + * by the address and line count. + * Command \ref CCM_DC_UNLOCK is written to CSR \ref CSR_CCM_MCOMMAND. + * \remarks + * This function must be executed in M-Mode only. + * \param [in] addr start address to be unlocked + * \param [in] cnt count of cache lines to be unlocked + */ +__STATIC_FORCEINLINE void MUnlockDCacheLines(unsigned long addr, unsigned long cnt) +{ + if (cnt > 0) { + unsigned long i; + __RV_CSR_WRITE(CSR_CCM_MBEGINADDR, addr); + for (i = 0; i < cnt; i++) { + __RV_CSR_WRITE(CSR_CCM_MCOMMAND, CCM_DC_UNLOCK); + } + } +} + +/** + * \brief Unlock one D-Cache line specified by address in S-Mode + * \details + * This function unlock one D-Cache line specified by the address. + * Command \ref CCM_DC_UNLOCK is written to CSR \ref CSR_CCM_SCOMMAND. + * \remarks + * This function must be executed in M/S-Mode only. + * \param [in] addr start address to be unlocked + */ +__STATIC_FORCEINLINE void SUnlockDCacheLine(unsigned long addr) +{ + __RV_CSR_WRITE(CSR_CCM_SBEGINADDR, addr); + __RV_CSR_WRITE(CSR_CCM_SCOMMAND, CCM_DC_UNLOCK); +} + +/** + * \brief Unlock several D-Cache lines specified by address in S-Mode + * \details + * This function unlock several D-Cache lines specified + * by the address and line count. + * Command \ref CCM_DC_UNLOCK is written to CSR \ref CSR_CCM_SCOMMAND. + * \remarks + * This function must be executed in M/S-Mode only. + * \param [in] addr start address to be unlocked + * \param [in] cnt count of cache lines to be unlocked + */ +__STATIC_FORCEINLINE void SUnlockDCacheLines(unsigned long addr, unsigned long cnt) +{ + if (cnt > 0) { + unsigned long i; + __RV_CSR_WRITE(CSR_CCM_SBEGINADDR, addr); + for (i = 0; i < cnt; i++) { + __RV_CSR_WRITE(CSR_CCM_SCOMMAND, CCM_DC_UNLOCK); + } + } +} + +/** + * \brief Unlock one D-Cache line specified by address in U-Mode + * \details + * This function unlock one D-Cache line specified by the address. + * Command \ref CCM_DC_UNLOCK is written to CSR \ref CSR_CCM_UCOMMAND. + * \remarks + * This function must be executed in M/S/U-Mode only. + * \param [in] addr start address to be unlocked + */ +__STATIC_FORCEINLINE void UUnlockDCacheLine(unsigned long addr) +{ + __RV_CSR_WRITE(CSR_CCM_UBEGINADDR, addr); + __RV_CSR_WRITE(CSR_CCM_UCOMMAND, CCM_DC_UNLOCK); +} + +/** + * \brief Unlock several D-Cache lines specified by address in U-Mode + * \details + * This function unlock several D-Cache lines specified + * by the address and line count. + * Command \ref CCM_DC_UNLOCK is written to CSR \ref CSR_CCM_UCOMMAND. + * \remarks + * This function must be executed in M/S/U-Mode only. + * \param [in] addr start address to be unlocked + * \param [in] cnt count of cache lines to be unlocked + */ +__STATIC_FORCEINLINE void UUnlockDCacheLines(unsigned long addr, unsigned long cnt) +{ + if (cnt > 0) { + unsigned long i; + __RV_CSR_WRITE(CSR_CCM_UBEGINADDR, addr); + for (i = 0; i < cnt; i++) { + __RV_CSR_WRITE(CSR_CCM_UCOMMAND, CCM_DC_UNLOCK); + } + } +} + +/** + * \brief Invalidate all D-Cache lines in M-Mode + * \details + * This function invalidate all D-Cache lines. + * Command \ref CCM_DC_INVAL_ALL is written to CSR \ref CSR_CCM_MCOMMAND. + * \remarks + * This function must be executed in M-Mode only. + * \param [in] addr start address to be invalidated + */ +__STATIC_FORCEINLINE void MInvalDCache(void) +{ + __RV_CSR_WRITE(CSR_CCM_MCOMMAND, CCM_DC_INVAL_ALL); +} + +/** + * \brief Invalidate all D-Cache lines in S-Mode + * \details + * This function invalidate all D-Cache lines. + * Command \ref CCM_DC_INVAL_ALL is written to CSR \ref CSR_CCM_SCOMMAND. + * \remarks + * This function must be executed in M/S-Mode only. + * \param [in] addr start address to be invalidated + */ +__STATIC_FORCEINLINE void SInvalDCache(void) +{ + __RV_CSR_WRITE(CSR_CCM_SCOMMAND, CCM_DC_INVAL_ALL); +} + +/** + * \brief Invalidate all D-Cache lines in U-Mode + * \details + * This function invalidate all D-Cache lines. + * In U-Mode, this operation will be automatically + * translated to flush and invalidate operations by hardware. + * Command \ref CCM_DC_INVAL_ALL is written to CSR \ref CSR_CCM_UCOMMAND. + * \remarks + * This function must be executed in M/S/U-Mode only. + * \param [in] addr start address to be invalidated + */ +__STATIC_FORCEINLINE void UInvalDCache(void) +{ + __RV_CSR_WRITE(CSR_CCM_UCOMMAND, CCM_DC_INVAL_ALL); +} + +/** + * \brief Flush all D-Cache lines in M-Mode + * \details + * This function flush all D-Cache lines. + * Command \ref CCM_DC_WB_ALL is written to CSR \ref CSR_CCM_MCOMMAND. + * \remarks + * This function must be executed in M-Mode only. + * \param [in] addr start address to be flushed + */ +__STATIC_FORCEINLINE void MFlushDCache(void) +{ + __RV_CSR_WRITE(CSR_CCM_MCOMMAND, CCM_DC_WB_ALL); +} + +/** + * \brief Flush all D-Cache lines in S-Mode + * \details + * This function flush all D-Cache lines. + * Command \ref CCM_DC_WB_ALL is written to CSR \ref CSR_CCM_SCOMMAND. + * \remarks + * This function must be executed in M/S-Mode only. + * \param [in] addr start address to be flushed + */ +__STATIC_FORCEINLINE void SFlushDCache(void) +{ + __RV_CSR_WRITE(CSR_CCM_SCOMMAND, CCM_DC_WB_ALL); +} + +/** + * \brief Flush all D-Cache lines in U-Mode + * \details + * This function flush all D-Cache lines. + * Command \ref CCM_DC_WB_ALL is written to CSR \ref CSR_CCM_UCOMMAND. + * \remarks + * This function must be executed in M/S/U-Mode only. + * \param [in] addr start address to be flushed + */ +__STATIC_FORCEINLINE void UFlushDCache(void) +{ + __RV_CSR_WRITE(CSR_CCM_UCOMMAND, CCM_DC_WB_ALL); +} + +/** + * \brief Flush and invalidate all D-Cache lines in M-Mode + * \details + * This function flush and invalidate all D-Cache lines. + * Command \ref CCM_DC_WBINVAL_ALL is written to CSR \ref CSR_CCM_MCOMMAND. + * \remarks + * This function must be executed in M-Mode only. + * \param [in] addr start address to be flushed and locked + */ +__STATIC_FORCEINLINE void MFlushInvalDCache(void) +{ + __RV_CSR_WRITE(CSR_CCM_MCOMMAND, CCM_DC_WBINVAL_ALL); +} + +/** + * \brief Flush and invalidate all D-Cache lines in S-Mode + * \details + * This function flush and invalidate all D-Cache lines. + * Command \ref CCM_DC_WBINVAL_ALL is written to CSR \ref CSR_CCM_SCOMMAND. + * \remarks + * This function must be executed in M/S-Mode only. + * \param [in] addr start address to be flushed and locked + */ +__STATIC_FORCEINLINE void SFlushInvalDCache(void) +{ + __RV_CSR_WRITE(CSR_CCM_SCOMMAND, CCM_DC_WBINVAL_ALL); +} + +/** + * \brief Flush and invalidate all D-Cache lines in U-Mode + * \details + * This function flush and invalidate all D-Cache lines. + * Command \ref CCM_DC_WBINVAL_ALL is written to CSR \ref CSR_CCM_UCOMMAND. + * \remarks + * This function must be executed in M/S/U-Mode only. + * \param [in] addr start address to be flushed and locked + */ +__STATIC_FORCEINLINE void UFlushInvalDCache(void) +{ + __RV_CSR_WRITE(CSR_CCM_UCOMMAND, CCM_DC_WBINVAL_ALL); +} + +/** @} */ /* End of Doxygen Group NMSIS_Core_DCache */ +#endif /* defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1) */ + +#ifdef __cplusplus +} +#endif +#endif /** __CORE_FEATURE_CACHE_H__ */ diff --git a/components/nmsis/core/inc/core_feature_dsp.h b/components/nmsis/core/inc/core_feature_dsp.h new file mode 100644 index 00000000..42df123c --- /dev/null +++ b/components/nmsis/core/inc/core_feature_dsp.h @@ -0,0 +1,18667 @@ +/* + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef __CORE_FEATURE_DSP__ +#define __CORE_FEATURE_DSP__ + +/*! + * @file core_feature_dsp.h + * @brief DSP feature API header file for Nuclei N/NX Core + */ +/* + * DSP Feature Configuration Macro: + * 1. __DSP_PRESENT: Define whether Digital Signal Processing Unit(DSP) is present or not + * * 0: Not present + * * 1: Present + */ +#ifdef __cplusplus + extern "C" { +#endif + +#if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1) + +/* ########################### CPU SIMD DSP Intrinsic Functions ########################### */ +/** + * \defgroup NMSIS_Core_DSP_Intrinsic Intrinsic Functions for SIMD Instructions + * \ingroup NMSIS_Core + * \brief Functions that generate RISC-V DSP SIMD instructions. + * \details + * + * The following functions generate specified RISC-V SIMD instructions that cannot be directly accessed by compiler. + * * **DSP ISA Extension Instruction Summary** + * + **Shorthand Definitions** + * - r.H == rH1: r[31:16], r.L == r.H0: r[15:0] + * - r.B3: r[31:24], r.B2: r[23:16], r.B1: r[15:8], r.B0: r[7:0] + * - r.B[x]: r[(x*8+7):(x*8+0)] + * - r.H[x]: r[(x*16+7):(x*16+0)] + * - r.W[x]: r[(x*32+31):(x*32+0)] + * - r[xU]: the upper 32-bit of a 64-bit number; xU represents the GPR number that contains this upper part 32-bit value. + * - r[xL]: the lower 32-bit of a 64-bit number; xL represents the GPR number that contains this lower part 32-bit value. + * - r[xU].r[xL]: a 64-bit number that is formed from a pair of GPRs. + * - s>>: signed arithmetic right shift: + * - u>>: unsigned logical right shift + * - SAT.Qn(): Saturate to the range of [-2^n, 2^n-1], if saturation happens, set PSW.OV. + * - SAT.Um(): Saturate to the range of [0, 2^m-1], if saturation happens, set PSW.OV. + * - RUND(): Indicate `rounding`, i.e., add 1 to the most significant discarded bit for right shift or MSW-type multiplication instructions. + * - Sign or Zero Extending functions: + * - SEm(data): Sign-Extend data to m-bit.: + * - ZEm(data): Zero-Extend data to m-bit. + * - ABS(x): Calculate the absolute value of `x`. + * - CONCAT(x,y): Concatinate `x` and `y` to form a value. + * - u<: Unsinged less than comparison. + * - u<=: Unsinged less than & equal comparison. + * - u>: Unsinged greater than comparison. + * - s*: Signed multiplication. + * - u*: Unsigned multiplication. + * + * @{ + */ +/** @} */ /* End of Doxygen Group NMSIS_Core_DSP_Intrinsic */ + + +/** + * \defgroup NMSIS_Core_DSP_Intrinsic_SIMD_DATA_PROCESS SIMD Data Processing Instructions + * \ingroup NMSIS_Core_DSP_Intrinsic + * \brief SIMD Data Processing Instructions + * \details + */ + +/** + * \defgroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB SIMD 16-bit Add/Subtract Instructions + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_DATA_PROCESS + * \brief SIMD 16-bit Add/Subtract Instructions + * \details + * Based on the combination of the types of the two 16-bit arithmetic operations, the SIMD 16-bit + * add/subtract instructions can be classified into 6 main categories: Addition (two 16-bit addition), + * Subtraction (two 16-bit subtraction), Crossed Add & Sub (one addition and one subtraction), and + * Crossed Sub & Add (one subtraction and one addition), Straight Add & Sub (one addition and one + * subtraction), and Straight Sub & Add (one subtraction and one addition). + * Based on the way of how an overflow condition is handled, the SIMD 16-bit add/subtract + * instructions can be classified into 5 groups: Wrap-around (dropping overflow), Signed Halving + * (keeping overflow by dropping 1 LSB bit), Unsigned Halving, Signed Saturation (clipping overflow), + * and Unsigned Saturation. + * Together, there are 30 SIMD 16-bit add/subtract instructions. + */ + +/** + * \defgroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_ADDSUB SIMD 8-bit Addition & Subtraction Instructions + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_DATA_PROCESS + * \brief SIMD 8-bit Addition & Subtraction Instructions + * \details + * Based on the types of the four 8-bit arithmetic operations, the SIMD 8-bit add/subtract instructions + * can be classified into 2 main categories: Addition (four 8-bit addition), and Subtraction (four 8-bit + * subtraction). + * Based on the way of how an overflow condition is handled for singed or unsigned operation, the + * SIMD 8-bit add/subtract instructions can be classified into 5 groups: Wrap-around (dropping + * overflow), Signed Halving (keeping overflow by dropping 1 LSB bit), Unsigned Halving, Signed + * Saturation (clipping overflow), and Unsigned Saturation. + * Together, there are 10 SIMD 8-bit add/subtract instructions. + */ + +/** + * \defgroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_SHIFT SIMD 16-bit Shift Instructions + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_DATA_PROCESS + * \brief SIMD 16-bit Shift Instructions + * \details + * there are 14 SIMD 16-bit shift instructions. + */ + +/** + * \defgroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_SHIFT SIMD 8-bit Shift Instructions + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_DATA_PROCESS + * \brief SIMD 8-bit Shift Instructions + * \details + * there are 14 SIMD 8-bit shift instructions. + */ + +/** + * \defgroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_CMP SIMD 16-bit Compare Instructions + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_DATA_PROCESS + * \brief SIMD 16-bit Compare Instructions + * \details + * there are 5 SIMD 16-bit Compare instructions. + */ + +/** + * \defgroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_CMP SIMD 8-bit Compare Instructions + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_DATA_PROCESS + * \brief SIMD 8-bit Compare Instructions + * \details + * there are 5 SIMD 8-bit Compare instructions. + */ + +/** + * \defgroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_MULTIPLY SIMD 16-bit Multiply Instructions + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_DATA_PROCESS + * \brief SIMD 16-bit Multiply Instructions + * \details + * there are 6 SIMD 16-bit Multiply instructions. + */ + +/** + * \defgroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_MULTIPLY SIMD 8-bit Multiply Instructions + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_DATA_PROCESS + * \brief SIMD 8-bit Multiply Instructions + * \details + * there are 6 SIMD 8-bit Multiply instructions. + */ + +/** + * \defgroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_MISC SIMD 16-bit Miscellaneous Instructions + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_DATA_PROCESS + * \brief SIMD 16-bit Miscellaneous Instructions + * \details + * there are 10 SIMD 16-bit Misc instructions. + */ + +/** + * \defgroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_MISC SIMD 8-bit Miscellaneous Instructions + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_DATA_PROCESS + * \brief SIMD 8-bit Miscellaneous Instructions + * \details + * there are 10 SIMD 8-bit Miscellaneous instructions. + */ + +/** + * \defgroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_UNPACK SIMD 8-bit Unpacking Instructions + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_DATA_PROCESS + * \brief SIMD 8-bit Unpacking Instructions + * \details + * there are 8 SIMD 8-bit Unpacking instructions. + */ + +/** + * \defgroup NMSIS_Core_DSP_Intrinsic_NON_SIMD Non-SIMD Instructions + * \ingroup NMSIS_Core_DSP_Intrinsic + * \brief Non-SIMD Instructions + * \details + */ + +/** + * \defgroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q15_SAT_ALU Non-SIMD Q15 saturation ALU Instructions + * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD + * \brief Non-SIMD Q15 saturation ALU Instructions + * \details + * there are 7 Non-SIMD Q15 saturation ALU Instructions + */ + +/** + * \defgroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q31_SAT_ALU Non-SIMD Q31 saturation ALU Instructions + * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD + * \brief Non-SIMD Q31 saturation ALU Instructions + * \details + * there are Non-SIMD Q31 saturation ALU Instructions + */ + +/** + * \defgroup NMSIS_Core_DSP_Intrinsic_32B_COMPUTATION 32-bit Computation Instructions + * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD + * \brief 32-bit Computation Instructions + * \details + * there are 8 32-bit Computation Instructions + */ + +/** + * \defgroup NMSIS_Core_DSP_Intrinsic_OV_FLAG_SC OV (Overflow) flag Set/Clear Instructions + * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD + * \brief OV (Overflow) flag Set/Clear Instructions + * \details + * The following table lists the user instructions related to Overflow (OV) flag manipulation. there are 2 OV (Overflow) flag Set/Clear Instructions + */ + +/** + * \defgroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_MISC Non-SIMD Miscellaneous Instructions + * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD + * \brief Non-SIMD Miscellaneous Instructions + * \details + * There are 13 Miscellaneous Instructions here. + */ + +/** + * \defgroup NMSIS_Core_DSP_Intrinsic_PART_SIMD_DATA_PROCESS Partial-SIMD Data Processing Instructions + * \ingroup NMSIS_Core_DSP_Intrinsic + * \brief Partial-SIMD Data Processing Instructions + * \details + */ + +/** + * \defgroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_PACK SIMD 16-bit Packing Instructions + * \ingroup NMSIS_Core_DSP_Intrinsic_PART_SIMD_DATA_PROCESS + * \brief SIMD 16-bit Packing Instructions + * \details + * there are 4 SIMD16-bit Packing Instructions. + */ + +/** + * \defgroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X32_MAC Signed MSW 32x32 Multiply and Add Instructions + * \ingroup NMSIS_Core_DSP_Intrinsic_PART_SIMD_DATA_PROCESS + * \brief Signed MSW 32x32 Multiply and Add Instructions + * \details + * there are 8 Signed MSW 32x32 Multiply and Add Instructions + */ + +/** + * \defgroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X16_MAC Signed MSW 32x16 Multiply and Add Instructions + * \ingroup NMSIS_Core_DSP_Intrinsic_PART_SIMD_DATA_PROCESS + * \brief Signed MSW 32x16 Multiply and Add Instructions + * \details + * there are 15 Signed MSW 32x16 Multiply and Add Instructions + */ + +/** + * \defgroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_32B_ADDSUB Signed 16-bit Multiply 32-bit Add/Subtract Instructions + * \ingroup NMSIS_Core_DSP_Intrinsic_PART_SIMD_DATA_PROCESS + * \brief Signed 16-bit Multiply 32-bit Add/Subtract Instructions + * \details + * there are 18 Signed 16-bit Multiply 32-bit Add/Subtract Instructions + */ + +/** + * \defgroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_64B_ADDSUB Signed 16-bit Multiply 64-bit Add/Subtract Instructions + * \ingroup NMSIS_Core_DSP_Intrinsic_PART_SIMD_DATA_PROCESS + * \brief Signed 16-bit Multiply 64-bit Add/Subtract Instructions + * \details + * there is Signed 16-bit Multiply 64-bit Add/Subtract Instructions + */ + +/** + * \defgroup NMSIS_Core_DSP_Intrinsic_PART_SIMD_MISC Partial-SIMD Miscellaneous Instructions + * \ingroup NMSIS_Core_DSP_Intrinsic_PART_SIMD_DATA_PROCESS + * \brief Partial-SIMD Miscellaneous Instructions + * \details + * there are 7 Partial-SIMD Miscellaneous Instructions + */ + +/** + * \defgroup NMSIS_Core_DSP_Intrinsic_8B_MULT_32B_ADD 8-bit Multiply with 32-bit Add Instructions + * \ingroup NMSIS_Core_DSP_Intrinsic_PART_SIMD_DATA_PROCESS + * \brief 8-bit Multiply with 32-bit Add Instructions + * \details + * there are 3 8-bit Multiply with 32-bit Add Instructions + */ + +/** + * \defgroup NMSIS_Core_DSP_Intrinsic_64B_PROFILE 64-bit Profile Instructions + * \ingroup NMSIS_Core_DSP_Intrinsic + * \brief 64-bit Profile Instructions + * \details + */ + +/** + * \defgroup NMSIS_Core_DSP_Intrinsic_64B_ADDSUB 64-bit Addition & Subtraction Instructions + * \ingroup NMSIS_Core_DSP_Intrinsic_64B_PROFILE + * \brief 64-bit Addition & Subtraction Instructions + * \details + * there are 10 64-bit Addition & Subtraction Instructions. + */ + +/** + * \defgroup NMSIS_Core_DSP_Intrinsic_32B_MULT_64B_ADDSUB 32-bit Multiply with 64-bit Add/Subtract Instructions + * \ingroup NMSIS_Core_DSP_Intrinsic_64B_PROFILE + * \brief 32-bit Multiply with 64-bit Add/Subtract Instructions + * \details + * there are 32-bit Multiply 64-bit Add/Subtract Instructions + */ + +/** + * \defgroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_64B_ADDSUB Signed 16-bit Multiply with 64-bit Add/Subtract Instructions + * \ingroup NMSIS_Core_DSP_Intrinsic_64B_PROFILE + * \brief Signed 16-bit Multiply with 64-bit Add/Subtract Instructions + * \details + * there are 10 Signed 16-bit Multiply with 64-bit Add/Subtract Instructions + */ + +/** + * \defgroup NMSIS_Core_DSP_Intrinsic_RV64_ONLY RV64 Only Instructions + * \ingroup NMSIS_Core_DSP_Intrinsic + * \brief RV64 Only Instructions + * \details + */ + +/** + * \defgroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB (RV64 Only) SIMD 32-bit Add/Subtract Instructions + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_ONLY + * \brief (RV64 Only) SIMD 32-bit Add/Subtract Instructions + * \details + * The following tables list instructions that are only present in RV64. + * There are 30 SIMD 32-bit addition or subtraction instructions.there are 4 SIMD16-bit Packing Instructions. + */ + +/** + * \defgroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_SHIFT (RV64 Only) SIMD 32-bit Shift Instructions + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_ONLY + * \brief (RV64 Only) SIMD 32-bit Shift Instructions + * \details + * there are 14 (RV64 Only) SIMD 32-bit Shift Instructions + */ + +/** + * \defgroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_MISC (RV64 Only) SIMD 32-bit Miscellaneous Instructions + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_ONLY + * \brief (RV64 Only) SIMD 32-bit Miscellaneous Instructions + * \details + * there are 5 (RV64 Only) SIMD 32-bit Miscellaneous Instructions + */ + +/** + * \defgroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_Q15_SAT_MULT (RV64 Only) SIMD Q15 Saturating Multiply Instructions + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_ONLY + * \brief (RV64 Only) SIMD Q15 Saturating Multiply Instructions + * \details + * there are 9 (RV64 Only) SIMD Q15 saturating Multiply Instructions + */ + +/** + * \defgroup NMSIS_Core_DSP_Intrinsic_RV64_32B_MULT (RV64 Only) 32-bit Multiply Instructions + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_ONLY + * \brief (RV64 Only) 32-bit Multiply Instructions + * \details + * there is 3 RV64 Only) 32-bit Multiply Instructions + */ + +/** + * \defgroup NMSIS_Core_DSP_Intrinsic_RV64_32B_MULT_ADD (RV64 Only) 32-bit Multiply & Add Instructions + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_ONLY + * \brief (RV64 Only) 32-bit Multiply & Add Instructions + * \details + * there are 3 (RV64 Only) 32-bit Multiply & Add Instructions + */ + +/** + * \defgroup NMSIS_Core_DSP_Intrinsic_RV64_32B_PARALLEL_MAC (RV64 Only) 32-bit Parallel Multiply & Add Instructions + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_ONLY + * \brief (RV64 Only) 32-bit Parallel Multiply & Add Instructions + * \details + * there are 12 (RV64 Only) 32-bit Parallel Multiply & Add Instructions + */ + +/** + * \defgroup NMSIS_Core_DSP_Intrinsic_RV64_NON_SIMD_32B_SHIFT (RV64 Only) Non-SIMD 32-bit Shift Instructions + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_ONLY + * \brief (RV64 Only) Non-SIMD 32-bit Shift Instructions + * \details + * there are 1 (RV64 Only) Non-SIMD 32-bit Shift Instructions + */ + +/** + * \defgroup NMSIS_Core_DSP_Intrinsic_RV64_32B_PACK 32-bit Packing Instructions + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_ONLY + * \brief 32-bit Packing Instructions + * \details + * There are four 32-bit packing instructions here + */ + +/* ===== Inline Function Start for 3.1. ADD8 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_ADDSUB + * \brief ADD8 (SIMD 8-bit Addition) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * ADD8 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 8-bit integer element additions simultaneously. + * + * **Description**:\n + * This instruction adds the 8-bit integer elements in Rs1 with the 8-bit integer elements + * in Rs2, and then writes the 8-bit element results to Rd. + * + * **Note**:\n + * This instruction can be used for either signed or unsigned addition. + * + * **Operations**:\n + * ~~~ + * Rd.B[x] = Rs1.B[x] + Rs2.B[x]; + * for RV32: x=3...0, + * for RV64: x=7...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_ADD8(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("add8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.1. ADD8 ===== */ + +/* ===== Inline Function Start for 3.2. ADD16 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB + * \brief ADD16 (SIMD 16-bit Addition) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * ADD16 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 16-bit integer element additions simultaneously. + * + * **Description**:\n + * This instruction adds the 16-bit integer elements in Rs1 with the 16-bit integer + * elements in Rs2, and then writes the 16-bit element results to Rd. + * + * **Note**:\n + * This instruction can be used for either signed or unsigned addition. + * + * **Operations**:\n + * ~~~ + * Rd.H[x] = Rs1.H[x] + Rs2.H[x]; + * for RV32: x=1...0, + * for RV64: x=3...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_ADD16(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("add16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.2. ADD16 ===== */ + +/* ===== Inline Function Start for 3.3. ADD64 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_64B_ADDSUB + * \brief ADD64 (64-bit Addition) + * \details + * **Type**: 64-bit Profile + * + * **Syntax**:\n + * ~~~ + * ADD64 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Add two 64-bit signed or unsigned integers. + * + * **RV32 Description**:\n + * This instruction adds the 64-bit integer of an even/odd pair of registers specified + * by Rs1(4,1) with the 64-bit integer of an even/odd pair of registers specified by Rs2(4,1), and then + * writes the 64-bit result to an even/odd pair of registers specified by Rd(4,1). + * Rx(4,1), i.e., value d, determines the even/odd pair group of two registers. Specifically, the register + * pair includes register 2d and 2d+1. + * The odd `2d+1` register of the pair contains the high 32-bit of the result and the even `2d` register + * of the pair contains the low 32-bit of the result. + * + * **RV64 Description**:\n + * This instruction has the same behavior as the ADD instruction in RV64I. + * + * **Note**:\n + * This instruction can be used for either signed or unsigned addition. + * + * **Operations**:\n + * ~~~ + * RV32: + * t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1); + * a_L = CONCAT(Rs1(4,1),1'b0); a_H = CONCAT(Rs1(4,1),1'b1); + * b_L = CONCAT(Rs2(4,1),1'b0); b_H = CONCAT(Rs2(4,1),1'b1); + * R[t_H].R[t_L] = R[a_H].R[a_L] + R[b_H].R[b_L]; + * RV64: + * Rd = Rs1 + Rs2; + * ~~~ + * + * \param [in] a unsigned long long type of value stored in a + * \param [in] b unsigned long long type of value stored in b + * \return value stored in unsigned long long type + */ +__STATIC_FORCEINLINE unsigned long long __RV_ADD64(unsigned long long a, unsigned long long b) +{ + register unsigned long long result; + __ASM volatile("add64 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.3. ADD64 ===== */ + +/* ===== Inline Function Start for 3.4. AVE ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_MISC + * \brief AVE (Average with Rounding) + * \details + * **Type**: DSP + * + * **Syntax**:\n + * ~~~ + * AVE Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Calculate the average of the contents of two general registers. + * + * **Description**:\n + * This instruction calculates the average value of two signed integers stored in Rs1 and + * Rs2, rounds up a half-integer result to the nearest integer, and writes the result to Rd. + * + * **Operations**:\n + * ~~~ + * Sum = CONCAT(Rs1[MSB],Rs1[MSB:0]) + CONCAT(Rs2[MSB],Rs2[MSB:0]) + 1; + * Rd = Sum[(MSB+1):1]; + * for RV32: MSB=31, + * for RV64: MSB=63 + * ~~~ + * + * \param [in] a long type of value stored in a + * \param [in] b long type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_AVE(long a, long b) +{ + register long result; + __ASM volatile("ave %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.4. AVE ===== */ + +/* ===== Inline Function Start for 3.5. BITREV ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_MISC + * \brief BITREV (Bit Reverse) + * \details + * **Type**: DSP + * + * **Syntax**:\n + * ~~~ + * BITREV Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Reverse the bit positions of the source operand within a specified width starting from bit + * 0. The reversed width is a variable from a GPR. + * + * **Description**:\n + * This instruction reverses the bit positions of the content of Rs1. The reversed bit width + * is calculated as Rs2[4:0]+1 (RV32) or Rs2[5:0]+1 (RV64). The upper bits beyond the reversed width + * are filled with zeros. After the bit reverse operation, the result is written to Rd. + * + * **Operations**:\n + * ~~~ + * msb = Rs2[4:0]; (for RV32) + * msb = Rs2[5:0]; (for RV64) + * rev[0:msb] = Rs1[msb:0]; + * Rd = ZE(rev[msb:0]); + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_BITREV(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("bitrev %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.5. BITREV ===== */ + +/* ===== Inline Function Start for 3.6. BITREVI ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_MISC + * \brief BITREVI (Bit Reverse Immediate) + * \details + * **Type**: DSP + * + * **Syntax**:\n + * ~~~ + * (RV32) BITREVI Rd, Rs1, imm[4:0] + * (RV64) BITREVI Rd, Rs1, imm[5:0] + * ~~~ + * + * **Purpose**:\n + * Reverse the bit positions of the source operand within a specified width starting from bit + * 0. The reversed width is an immediate value. + * + * **Description**:\n + * This instruction reverses the bit positions of the content of Rs1. The reversed bit width + * is calculated as imm[4:0]+1 (RV32) or imm[5:0]+1 (RV64). The upper bits beyond the reversed width + * are filled with zeros. After the bit reverse operation, the result is written to Rd. + * + * **Operations**:\n + * ~~~ + * msb = imm[4:0]; (RV32) + * msb = imm[5:0]; (RV64) + * rev[0:msb] = Rs1[msb:0]; + * Rd = ZE(rev[msb:0]); + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +#define __RV_BITREVI(a, b) \ + ({ \ + register unsigned long result; \ + register unsigned long __a = (unsigned long)(a); \ + __ASM volatile("bitrevi %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b)); \ + result; \ + }) +/* ===== Inline Function End for 3.6. BITREVI ===== */ + +/* ===== Inline Function Start for 3.7. BPICK ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_MISC + * \brief BPICK (Bit-wise Pick) + * \details + * **Type**: DSP + * + * **Syntax**:\n + * ~~~ + * BPICK Rd, Rs1, Rs2, Rc + * ~~~ + * + * **Purpose**:\n + * Select from two source operands based on a bit mask in the third operand. + * + * **Description**:\n + * This instruction selects individual bits from Rs1 or Rs2, based on the bit mask value in + * Rc. If a bit in Rc is 1, the corresponding bit is from Rs1; otherwise, the corresponding bit is from Rs2. + * The selection results are written to Rd. + * + * **Operations**:\n + * ~~~ + * Rd[x] = Rc[x]? Rs1[x] : Rs2[x]; + * for RV32, x=31...0 + * for RV64, x=63...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \param [in] c unsigned long type of value stored in c + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_BPICK(unsigned long a, unsigned long b, unsigned long c) +{ + register unsigned long result; + __ASM volatile("bpick %0, %1, %2, %3" : "=r"(result) : "r"(a), "r"(b), "r"(c)); + return result; +} +/* ===== Inline Function End for 3.7. BPICK ===== */ + +/* ===== Inline Function Start for 3.8. CLROV ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_OV_FLAG_SC + * \brief CLROV (Clear OV flag) + * \details + * **Type**: DSP + * + * **Syntax**:\n + * ~~~ + * CLROV # pseudo mnemonic + * ~~~ + * + * **Purpose**:\n + * This pseudo instruction is an alias to `CSRRCI x0, ucode, 1` instruction. + * + * + */ +__STATIC_FORCEINLINE void __RV_CLROV(void) +{ + __ASM volatile("clrov "); +} +/* ===== Inline Function End for 3.8. CLROV ===== */ + +/* ===== Inline Function Start for 3.9. CLRS8 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_MISC + * \brief CLRS8 (SIMD 8-bit Count Leading Redundant Sign) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * CLRS8 Rd, Rs1 + * ~~~ + * + * **Purpose**:\n + * Count the number of redundant sign bits of the 8-bit elements of a general register. + * + * **Description**:\n + * Starting from the bits next to the sign bits of the 8-bit elements of Rs1, this instruction + * counts the number of redundant sign bits and writes the result to the corresponding 8-bit elements + * of Rd. + * + * **Operations**:\n + * ~~~ + * snum[x] = Rs1.B[x]; + * cnt[x] = 0; + * for (i = 6 to 0) { + * if (snum[x](i) == snum[x](7)) { + * cnt[x] = cnt[x] + 1; + * } else { + * break; + * } + * } + * Rd.B[x] = cnt[x]; + * for RV32: x=3...0 + * for RV64: x=7...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_CLRS8(unsigned long a) +{ + register unsigned long result; + __ASM volatile("clrs8 %0, %1" : "=r"(result) : "r"(a)); + return result; +} +/* ===== Inline Function End for 3.9. CLRS8 ===== */ + +/* ===== Inline Function Start for 3.10. CLRS16 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_MISC + * \brief CLRS16 (SIMD 16-bit Count Leading Redundant Sign) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * CLRS16 Rd, Rs1 + * ~~~ + * + * **Purpose**:\n + * Count the number of redundant sign bits of the 16-bit elements of a general register. + * + * **Description**:\n + * Starting from the bits next to the sign bits of the 16-bit elements of Rs1, this + * instruction counts the number of redundant sign bits and writes the result to the corresponding 16- + * bit elements of Rd. + * + * **Operations**:\n + * ~~~ + * snum[x] = Rs1.H[x]; + * cnt[x] = 0; + * for (i = 14 to 0) { + * if (snum[x](i) == snum[x](15)) { + * cnt[x] = cnt[x] + 1; + * } else { + * break; + * } + * } + * Rd.H[x] = cnt[x]; + * for RV32: x=1...0 + * for RV64: x=3...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_CLRS16(unsigned long a) +{ + register unsigned long result; + __ASM volatile("clrs16 %0, %1" : "=r"(result) : "r"(a)); + return result; +} +/* ===== Inline Function End for 3.10. CLRS16 ===== */ + +/* ===== Inline Function Start for 3.11. CLRS32 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_PART_SIMD_MISC + * \brief CLRS32 (SIMD 32-bit Count Leading Redundant Sign) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * CLRS32 Rd, Rs1 + * ~~~ + * + * **Purpose**:\n + * Count the number of redundant sign bits of the 32-bit elements of a general register. + * + * **Description**:\n + * Starting from the bits next to the sign bits of the 32-bit elements of Rs1, this + * instruction counts the number of redundant sign bits and writes the result to the corresponding 32- + * bit elements of Rd. + * + * **Operations**:\n + * ~~~ + * snum[x] = Rs1.W[x]; + * cnt[x] = 0; + * for (i = 30 to 0) { + * if (snum[x](i) == snum[x](31)) { + * cnt[x] = cnt[x] + 1; + * } else { + * break; + * } + * } + * Rd.W[x] = cnt[x]; + * for RV32: x=0 + * for RV64: x=1...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_CLRS32(unsigned long a) +{ + register unsigned long result; + __ASM volatile("clrs32 %0, %1" : "=r"(result) : "r"(a)); + return result; +} +/* ===== Inline Function End for 3.11. CLRS32 ===== */ + +/* ===== Inline Function Start for 3.12. CLO8 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_MISC + * \brief CLO8 (SIMD 8-bit Count Leading One) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * CLO8 Rd, Rs1 + * ~~~ + * + * **Purpose**:\n + * Count the number of leading one bits of the 8-bit elements of a general register. + * + * **Description**:\n + * Starting from the most significant bits of the 8-bit elements of Rs1, this instruction + * counts the number of leading one bits and writes the results to the corresponding 8-bit elements of + * Rd. + * + * **Operations**:\n + * ~~~ + * snum[x] = Rs1.B[x]; + * cnt[x] = 0; + * for (i = 7 to 0) { + * if (snum[x](i) == 1) { + * cnt[x] = cnt[x] + 1; + * } else { + * break; + * } + * } + * Rd.B[x] = cnt[x]; + * for RV32: x=3...0 + * for RV64: x=7...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_CLO8(unsigned long a) +{ + register unsigned long result; + __ASM volatile("clo8 %0, %1" : "=r"(result) : "r"(a)); + return result; +} +/* ===== Inline Function End for 3.12. CLO8 ===== */ + +/* ===== Inline Function Start for 3.13. CLO16 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_MISC + * \brief CLO16 (SIMD 16-bit Count Leading One) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * CLO16 Rd, Rs1 + * ~~~ + * + * **Purpose**:\n + * Count the number of leading one bits of the 16-bit elements of a general register. + * + * **Description**:\n + * Starting from the most significant bits of the 16-bit elements of Rs1, this instruction + * counts the number of leading one bits and writes the results to the corresponding 16-bit elements + * of Rd. + * + * **Operations**:\n + * ~~~ + * snum[x] = Rs1.H[x]; + * cnt[x] = 0; + * for (i = 15 to 0) { + * if (snum[x](i) == 1) { + * cnt[x] = cnt[x] + 1; + * } else { + * break; + * } + * } + * Rd.H[x] = cnt[x]; + * for RV32: x=1...0 + * for RV64: x=3...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_CLO16(unsigned long a) +{ + register unsigned long result; + __ASM volatile("clo16 %0, %1" : "=r"(result) : "r"(a)); + return result; +} +/* ===== Inline Function End for 3.13. CLO16 ===== */ + +/* ===== Inline Function Start for 3.14. CLO32 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_PART_SIMD_MISC + * \brief CLO32 (SIMD 32-bit Count Leading One) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * CLO32 Rd, Rs1 + * ~~~ + * + * **Purpose**:\n + * Count the number of leading one bits of the 32-bit elements of a general register. + * + * **Description**:\n + * Starting from the most significant bits of the 32-bit elements of Rs1, this instruction + * counts the number of leading one bits and writes the results to the corresponding 32-bit elements + * of Rd. + * + * **Operations**:\n + * ~~~ + * snum[x] = Rs1.W[x]; + * cnt[x] = 0; + * for (i = 31 to 0) { + * if (snum[x](i) == 1) { + * cnt[x] = cnt[x] + 1; + * } else { + * break; + * } + * } + * Rd.W[x] = cnt[x]; + * for RV32: x=0 + * for RV64: x=1...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_CLO32(unsigned long a) +{ + register unsigned long result; + __ASM volatile("clo32 %0, %1" : "=r"(result) : "r"(a)); + return result; +} +/* ===== Inline Function End for 3.14. CLO32 ===== */ + +/* ===== Inline Function Start for 3.15. CLZ8 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_MISC + * \brief CLZ8 (SIMD 8-bit Count Leading Zero) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * CLZ8 Rd, Rs1 + * ~~~ + * + * **Purpose**:\n + * Count the number of leading zero bits of the 8-bit elements of a general register. + * + * **Description**:\n + * Starting from the most significant bits of the 8-bit elements of Rs1, this instruction + * counts the number of leading zero bits and writes the results to the corresponding 8-bit elements of + * Rd. + * + * **Operations**:\n + * ~~~ + * snum[x] = Rs1.B[x]; + * cnt[x] = 0; + * for (i = 7 to 0) { + * if (snum[x](i) == 0) { + * cnt[x] = cnt[x] + 1; + * } else { + * break; + * } + * } + * Rd.B[x] = cnt[x]; + * for RV32: x=3...0 + * for RV64: x=7...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_CLZ8(unsigned long a) +{ + register unsigned long result; + __ASM volatile("clz8 %0, %1" : "=r"(result) : "r"(a)); + return result; +} +/* ===== Inline Function End for 3.15. CLZ8 ===== */ + +/* ===== Inline Function Start for 3.16. CLZ16 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_MISC + * \brief CLZ16 (SIMD 16-bit Count Leading Zero) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * CLZ16 Rd, Rs1 + * ~~~ + * + * **Purpose**:\n + * Count the number of leading zero bits of the 16-bit elements of a general register. + * + * **Description**:\n + * Starting from the most significant bits of the 16-bit elements of Rs1, this instruction + * counts the number of leading zero bits and writes the results to the corresponding 16-bit elements + * of Rd. + * + * **Operations**:\n + * ~~~ + * snum[x] = Rs1.H[x]; + * cnt[x] = 0; + * for (i = 15 to 0) { + * if (snum[x](i) == 0) { + * cnt[x] = cnt[x] + 1; + * } else { + * break; + * } + * } + * Rd.H[x] = cnt[x]; + * for RV32: x=1...0 + * for RV64: x=3...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_CLZ16(unsigned long a) +{ + register unsigned long result; + __ASM volatile("clz16 %0, %1" : "=r"(result) : "r"(a)); + return result; +} +/* ===== Inline Function End for 3.16. CLZ16 ===== */ + +/* ===== Inline Function Start for 3.17. CLZ32 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_PART_SIMD_MISC + * \brief CLZ32 (SIMD 32-bit Count Leading Zero) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * CLZ32 Rd, Rs1 + * ~~~ + * + * **Purpose**:\n + * Count the number of leading zero bits of the 32-bit elements of a general register. + * + * **Description**:\n + * Starting from the most significant bits of the 32-bit elements of Rs1, this instruction + * counts the number of leading zero bits and writes the results to the corresponding 32-bit elements + * of Rd. + * + * **Operations**:\n + * ~~~ + * snum[x] = Rs1.W[x]; + * cnt[x] = 0; + * for (i = 31 to 0) { + * if (snum[x](i) == 0) { + * cnt[x] = cnt[x] + 1; + * } else { + * break; + * } + * } + * Rd.W[x] = cnt[x]; + * for RV32: x=0 + * for RV64: x=1...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_CLZ32(unsigned long a) +{ + register unsigned long result; + __ASM volatile("clz32 %0, %1" : "=r"(result) : "r"(a)); + return result; +} +/* ===== Inline Function End for 3.17. CLZ32 ===== */ + +/* ===== Inline Function Start for 3.18. CMPEQ8 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_CMP + * \brief CMPEQ8 (SIMD 8-bit Integer Compare Equal) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * CMPEQ8 Rs, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 8-bit integer elements equal comparisons simultaneously. + * + * **Description**:\n + * This instruction compares the 8-bit integer elements in Rs1 with the 8-bit integer + * elements in Rs2 to see if they are equal. If they are equal, the result is 0xFF; otherwise, the result is + * 0x0. The 8-bit element comparison results are written to Rd. + * + * **Note**:\n + * This instruction can be used for either signed or unsigned numbers. + * + * **Operations**:\n + * ~~~ + * Rd.B[x] = (Rs1.B[x] == Rs2.B[x])? 0xff : 0x0; + * for RV32: x=3...0, + * for RV64: x=7...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_CMPEQ8(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("cmpeq8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.18. CMPEQ8 ===== */ + +/* ===== Inline Function Start for 3.19. CMPEQ16 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_CMP + * \brief CMPEQ16 (SIMD 16-bit Integer Compare Equal) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * CMPEQ16 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 16-bit integer elements equal comparisons simultaneously. + * + * **Description**:\n + * This instruction compares the 16-bit integer elements in Rs1 with the 16-bit integer + * elements in Rs2 to see if they are equal. If they are equal, the result is 0xFFFF; otherwise, the result + * is 0x0. The 16-bit element comparison results are written to Rt. + * + * **Note**:\n + * This instruction can be used for either signed or unsigned numbers. + * + * **Operations**:\n + * ~~~ + * Rd.H[x] = (Rs1.H[x] == Rs2.H[x])? 0xffff : 0x0; + * for RV32: x=1...0, + * for RV64: x=3...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_CMPEQ16(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("cmpeq16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.19. CMPEQ16 ===== */ + +/* ===== Inline Function Start for 3.20. CRAS16 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB + * \brief CRAS16 (SIMD 16-bit Cross Addition & Subtraction) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * CRAS16 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 16-bit integer element addition and 16-bit integer element subtraction in a 32-bit + * chunk simultaneously. Operands are from crossed positions in 32-bit chunks. + * + * **Description**:\n + * This instruction adds the 16-bit integer element in [31:16] of 32-bit chunks in Rs1 with + * the 16-bit integer element in [15:0] of 32-bit chunks in Rs2, and writes the result to [31:16] of 32-bit + * chunks in Rd; at the same time, it subtracts the 16-bit integer element in [31:16] of 32-bit chunks in + * Rs2 from the 16-bit integer element in [15:0] of 32-bit chunks, and writes the result to [15:0] of 32- + * bit chunks in Rd. + * + * **Note**:\n + * This instruction can be used for either signed or unsigned operations. + * + * **Operations**:\n + * ~~~ + * Rd.W[x][31:16] = Rs1.W[x][31:16] + Rs2.W[x][15:0]; + * Rd.W[x][15:0] = Rs1.W[x][15:0] - Rs2.W[x][31:16]; + * for RV32, x=0 + * for RV64, x=1...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_CRAS16(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("cras16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.20. CRAS16 ===== */ + +/* ===== Inline Function Start for 3.21. CRSA16 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB + * \brief CRSA16 (SIMD 16-bit Cross Subtraction & Addition) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * CRSA16 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 16-bit integer element subtraction and 16-bit integer element addition in a 32-bit + * chunk simultaneously. Operands are from crossed positions in 32-bit chunks. + * + * **Description**:\n + * This instruction subtracts the 16-bit integer element in [15:0] of 32-bit chunks in Rs2 + * from the 16-bit integer element in [31:16] of 32-bit chunks in Rs1, and writes the result to [31:16] of + * 32-bit chunks in Rd; at the same time, it adds the 16-bit integer element in [31:16] of 32-bit chunks + * in Rs2 with the 16-bit integer element in [15:0] of 32-bit chunks in Rs1, and writes the result to + * [15:0] of 32-bit chunks in Rd. + * + * **Note**:\n + * This instruction can be used for either signed or unsigned operations. + * + * **Operations**:\n + * ~~~ + * Rd.W[x][31:16] = Rs1.W[x][31:16] - Rs2.W[x][15:0]; + * Rd.W[x][15:0] = Rs1.W[x][15:0] + Rs2.W[x][31:16]; + * for RV32, x=0 + * for RV64, x=1...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_CRSA16(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("crsa16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.21. CRSA16 ===== */ + +/* ===== Inline Function Start for 3.22. INSB ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_MISC + * \brief INSB (Insert Byte) + * \details + * **Type**: DSP + * + * **Syntax**:\n + * ~~~ + * (RV32) INSB Rd, Rs1, imm[1:0] + * (RV64) INSB Rd, Rs1, imm[2:0] + * ~~~ + * + * **Purpose**:\n + * Insert byte 0 of a 32-bit or 64-bit register into one of the byte elements of another register. + * + * **Description**:\n + * This instruction inserts byte 0 of Rs1 into byte `imm[1:0]` (RV32) or `imm[2:0]` (RV64) + * of Rd. + * + * **Operations**:\n + * ~~~ + * bpos = imm[1:0]; (RV32) + * bpos = imm[2:0]; (RV64) + * Rd.B[bpos] = Rs1.B[0] + * ~~~ + * + * \param [in] t unsigned long type of value stored in t + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +#define __RV_INSB(t, a, b) \ + ({ \ + register unsigned long __t = (unsigned long)(t); \ + register unsigned long __a = (unsigned long)(a); \ + __ASM volatile("insb %0, %1, %2" : "+r"(__t) : "r"(__a), "K"(b)); \ + __t; \ + }) +/* ===== Inline Function End for 3.22. INSB ===== */ + +/* ===== Inline Function Start for 3.23. KABS8 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_MISC + * \brief KABS8 (SIMD 8-bit Saturating Absolute) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * KABS8 Rd, Rs1 + * ~~~ + * + * **Purpose**:\n + * Get the absolute value of 8-bit signed integer elements simultaneously. + * + * **Description**:\n + * This instruction calculates the absolute value of 8-bit signed integer elements stored + * in Rs1 and writes the element results to Rd. If the input number is 0x80, this instruction generates + * 0x7f as the output and sets the OV bit to 1. + * + * **Operations**:\n + * ~~~ + * src = Rs1.B[x]; + * if (src == 0x80) { + * src = 0x7f; + * OV = 1; + * } else if (src[7] == 1) + * src = -src; + * } + * Rd.B[x] = src; + * for RV32: x=3...0, + * for RV64: x=7...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_KABS8(unsigned long a) +{ + register unsigned long result; + __ASM volatile("kabs8 %0, %1" : "=r"(result) : "r"(a)); + return result; +} +/* ===== Inline Function End for 3.23. KABS8 ===== */ + +/* ===== Inline Function Start for 3.24. KABS16 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_MISC + * \brief KABS16 (SIMD 16-bit Saturating Absolute) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * KABS16 Rd, Rs1 + * ~~~ + * + * **Purpose**:\n + * Get the absolute value of 16-bit signed integer elements simultaneously. + * + * **Description**:\n + * This instruction calculates the absolute value of 16-bit signed integer elements stored + * in Rs1 and writes the element results to Rd. If the input number is 0x8000, this instruction + * generates 0x7fff as the output and sets the OV bit to 1. + * + * **Operations**:\n + * ~~~ + * src = Rs1.H[x]; + * if (src == 0x8000) { + * src = 0x7fff; + * OV = 1; + * } else if (src[15] == 1) + * src = -src; + * } + * Rd.H[x] = src; + * for RV32: x=1...0, + * for RV64: x=3...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_KABS16(unsigned long a) +{ + register unsigned long result; + __ASM volatile("kabs16 %0, %1" : "=r"(result) : "r"(a)); + return result; +} +/* ===== Inline Function End for 3.24. KABS16 ===== */ + +/* ===== Inline Function Start for 3.25. KABSW ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q31_SAT_ALU + * \brief KABSW (Scalar 32-bit Absolute Value with Saturation) + * \details + * **Type**: DSP + * + * **Syntax**:\n + * ~~~ + * KABSW Rd, Rs1 + * ~~~ + * + * **Purpose**:\n + * Get the absolute value of a signed 32-bit integer in a general register. + * + * **Description**:\n + * This instruction calculates the absolute value of a signed 32-bit integer stored in Rs1. + * The result is sign-extended (for RV64) and written to Rd. This instruction with the minimum + * negative integer input of 0x80000000 will produce a saturated output of maximum positive integer + * of 0x7fffffff and the OV flag will be set to 1. + * + * **Operations**:\n + * ~~~ + * if (Rs1.W[0] >= 0) { + * res = Rs1.W[0]; + * } else { + * If (Rs1.W[0] == 0x80000000) { + * res = 0x7fffffff; + * OV = 1; + * } else { + * res = -Rs1.W[0]; + * } + * } + * Rd = SE32(res); + * ~~~ + * + * \param [in] a signed long type of value stored in a + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_KABSW(signed long a) +{ + register unsigned long result; + __ASM volatile("kabsw %0, %1" : "=r"(result) : "r"(a)); + return result; +} +/* ===== Inline Function End for 3.25. KABSW ===== */ + +/* ===== Inline Function Start for 3.26. KADD8 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_ADDSUB + * \brief KADD8 (SIMD 8-bit Signed Saturating Addition) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * KADD8 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 8-bit signed integer element saturating additions simultaneously. + * + * **Description**:\n + * This instruction adds the 8-bit signed integer elements in Rs1 with the 8-bit signed + * integer elements in Rs2. If any of the results are beyond the Q7 number range (-2^7 <= Q7 <= 2^7-1), they + * are saturated to the range and the OV bit is set to 1. The saturated results are written to Rd. + * + * **Operations**:\n + * ~~~ + * res[x] = Rs1.B[x] + Rs2.B[x]; + * if (res[x] > 127) { + * res[x] = 127; + * OV = 1; + * } else if (res[x] < -128) { + * res[x] = -128; + * OV = 1; + * } + * Rd.B[x] = res[x]; + * for RV32: x=3...0, + * for RV64: x=7...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_KADD8(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("kadd8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.26. KADD8 ===== */ + +/* ===== Inline Function Start for 3.27. KADD16 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB + * \brief KADD16 (SIMD 16-bit Signed Saturating Addition) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * KADD16 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 16-bit signed integer element saturating additions simultaneously. + * + * **Description**:\n + * This instruction adds the 16-bit signed integer elements in Rs1 with the 16-bit signed + * integer elements in Rs2. If any of the results are beyond the Q15 number range (-2^15 <= Q15 <= 2^15-1), + * they are saturated to the range and the OV bit is set to 1. The saturated results are written to Rd. + * + * **Operations**:\n + * ~~~ + * res[x] = Rs1.H[x] + Rs2.H[x]; + * if (res[x] > 32767) { + * res[x] = 32767; + * OV = 1; + * } else if (res[x] < -32768) { + * res[x] = -32768; + * OV = 1; + * } + * Rd.H[x] = res[x]; + * for RV32: x=1...0, + * for RV64: x=3...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_KADD16(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("kadd16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.27. KADD16 ===== */ + +/* ===== Inline Function Start for 3.28. KADD64 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_64B_ADDSUB + * \brief KADD64 (64-bit Signed Saturating Addition) + * \details + * **Type**: DSP (64-bit Profile) + * + * **Syntax**:\n + * ~~~ + * KADD64 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Add two 64-bit signed integers. The result is saturated to the Q63 range. + * + * **RV32 Description**:\n + * This instruction adds the 64-bit signed integer of an even/odd pair of registers + * specified by Rs1(4,1) with the 64-bit signed integer of an even/odd pair of registers specified by + * Rs2(4,1). If the 64-bit result is beyond the Q63 number range (-2^63 <= Q63 <= 2^63-1), it is saturated to the + * range and the OV bit is set to 1. The saturated result is written to an even/odd pair of registers + * specified by Rd(4,1). + * Rx(4,1), i.e., value d, determines the even/odd pair group of two registers. Specifically, the register + * pair includes register 2d and 2d+1. + * The odd `2d+1` register of the pair contains the high 32-bit of the result and the even `2d` register + * of the pair contains the low 32-bit of the result. + * + * **RV64 Description**:\n + * This instruction adds the 64-bit signed integer in Rs1 with the 64-bit signed + * integer in Rs2. If the result is beyond the Q63 number range (-2^63 <= Q63 <= 2^63-1), it is saturated to the + * range and the OV bit is set to 1. The saturated result is written to Rd. + * + * **Operations**:\n + * ~~~ + * RV32: + * t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1); + * a_L = CONCAT(Rs1(4,1),1'b0); a_H = CONCAT(Rs1(4,1),1'b1); + * b_L = CONCAT(Rs2(4,1),1'b0); b_H = CONCAT(Rs2(4,1),1'b1); + * result = R[a_H].R[a_L] + R[b_H].R[b_L]; + * if (result > (2^63)-1) { + * result = (2^63)-1; OV = 1; + * } else if (result < -2^63) { + * result = -2^63; OV = 1; + * } + * R[t_H].R[t_L] = result; + * RV64: + * result = Rs1 + Rs2; + * if (result > (2^63)-1) { + * result = (2^63)-1; OV = 1; + * } else if (result < -2^63) { + * result = -2^63; OV = 1; + * } + * Rd = result; + * ~~~ + * + * \param [in] a long long type of value stored in a + * \param [in] b long long type of value stored in b + * \return value stored in long long type + */ +__STATIC_FORCEINLINE long long __RV_KADD64(long long a, long long b) +{ + register long long result; + __ASM volatile("kadd64 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.28. KADD64 ===== */ + +/* ===== Inline Function Start for 3.29. KADDH ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q15_SAT_ALU + * \brief KADDH (Signed Addition with Q15 Saturation) + * \details + * **Type**: DSP + * + * **Syntax**:\n + * ~~~ + * KADDH Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Add the signed lower 32-bit content of two registers with Q15 saturation. + * + * **Description**:\n + * The signed lower 32-bit content of Rs1 is added with the signed lower 32-bit content of + * Rs2. And the result is saturated to the 16-bit signed integer range of [-2^15, 2^15-1] and then sign- + * extended and written to Rd. If saturation happens, this instruction sets the OV flag. + * + * **Operations**:\n + * ~~~ + * tmp = Rs1.W[0] + Rs2.W[0]; + * if (tmp > 32767) { + * res = 32767; + * OV = 1; + * } else if (tmp < -32768) { + * res = -32768; + * OV = 1 + * } else { + * res = tmp; + * } + * Rd = SE(tmp[15:0]); + * ~~~ + * + * \param [in] a int type of value stored in a + * \param [in] b int type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_KADDH(int a, int b) +{ + register long result; + __ASM volatile("kaddh %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.29. KADDH ===== */ + +/* ===== Inline Function Start for 3.30. KADDW ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q31_SAT_ALU + * \brief KADDW (Signed Addition with Q31 Saturation) + * \details + * **Type**: DSP + * + * **Syntax**:\n + * ~~~ + * KADDW Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Add the lower 32-bit signed content of two registers with Q31 saturation. + * + * **Description**:\n + * The lower 32-bit signed content of Rs1 is added with the lower 32-bit signed content of + * Rs2. And the result is saturated to the 32-bit signed integer range of [-2^31, 2^31-1] and then sign- + * extended and written to Rd. If saturation happens, this instruction sets the OV flag. + * + * **Operations**:\n + * ~~~ + * tmp = Rs1.W[0] + Rs2.W[0]; + * if (tmp > (2^31)-1) { + * res = (2^31)-1; + * OV = 1; + * } else if (tmp < -2^31) { + * res = -2^31; + * OV = 1 + * } else { + * res = tmp; + * } + * Rd = res[31:0]; // RV32 + * Rd = SE(res[31:0]) // RV64 + * ~~~ + * + * \param [in] a int type of value stored in a + * \param [in] b int type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_KADDW(int a, int b) +{ + register long result; + __ASM volatile("kaddw %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.30. KADDW ===== */ + +/* ===== Inline Function Start for 3.31. KCRAS16 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB + * \brief KCRAS16 (SIMD 16-bit Signed Saturating Cross Addition & Subtraction) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * KCRAS16 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 16-bit signed integer element saturating addition and 16-bit signed integer element + * saturating subtraction in a 32-bit chunk simultaneously. Operands are from crossed positions in 32- + * bit chunks. + * + * **Description**:\n + * This instruction adds the 16-bit signed integer element in [31:16] of 32-bit chunks in + * Rs1 with the 16-bit signed integer element in [15:0] of 32-bit chunks in Rs2; at the same time, it + * subtracts the 16-bit signed integer element in [31:16] of 32-bit chunks in Rs2 from the 16-bit signed + * integer element in [15:0] of 32-bit chunks in Rs1. If any of the results are beyond the Q15 number + * range (-2^15 <= Q15 <= 2^15-1), they are saturated to the range and the OV bit is set to 1. The saturated + * results are written to [31:16] of 32-bit chunks in Rd for addition and [15:0] of 32-bit chunks in Rd for + * subtraction. + * + * **Operations**:\n + * ~~~ + * res1 = Rs1.W[x][31:16] + Rs2.W[x][15:0]; + * res2 = Rs1.W[x][15:0] - Rs2.W[x][31:16]; + * for (res in [res1, res2]) { + * if (res > (2^15)-1) { + * res = (2^15)-1; + * OV = 1; + * } else if (res < -2^15) { + * res = -2^15; + * OV = 1; + * } + * } + * Rd.W[x][31:16] = res1; + * Rd.W[x][15:0] = res2; + * for RV32, x=0 + * for RV64, x=1...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_KCRAS16(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("kcras16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.31. KCRAS16 ===== */ + +/* ===== Inline Function Start for 3.32. KCRSA16 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB + * \brief KCRSA16 (SIMD 16-bit Signed Saturating Cross Subtraction & Addition) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * KCRSA16 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 16-bit signed integer element saturating subtraction and 16-bit signed integer element + * saturating addition in a 32-bit chunk simultaneously. Operands are from crossed positions in 32-bit + * chunks. + * + * **Description**:\n + * This instruction subtracts the 16-bit signed integer element in [15:0] of 32-bit chunks + * in Rs2 from the 16-bit signed integer element in [31:16] of 32-bit chunks in Rs1; at the same time, it + * adds the 16-bit signed integer element in [31:16] of 32-bit chunks in Rs2 with the 16-bit signed + * integer element in [15:0] of 32-bit chunks in Rs1. If any of the results are beyond the Q15 number + * range (-2^15 <= Q15 <= 2^15-1), they are saturated to the range and the OV bit is set to 1. The saturated + * results are written to [31:16] of 32-bit chunks in Rd for subtraction and [15:0] of 32-bit chunks in Rd + * for addition. + * + * **Operations**:\n + * ~~~ + * res1 = Rs1.W[x][31:16] - Rs2.W[x][15:0]; + * res2 = Rs1.W[x][15:0] + Rs2.W[x][31:16]; + * for (res in [res1, res2]) { + * if (res > (2^15)-1) { + * res = (2^15)-1; + * OV = 1; + * } else if (res < -2^15) { + * res = -2^15; + * OV = 1; + * } + * } + * Rd.W[x][31:16] = res1; + * Rd.W[x][15:0] = res2; + * for RV32, x=0 + * for RV64, x=1...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_KCRSA16(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("kcrsa16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.32. KCRSA16 ===== */ + +/* ===== Inline Function Start for 3.33.1. KDMBB ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q31_SAT_ALU + * \brief KDMBB (Signed Saturating Double Multiply B16 x B16) + * \details + * **Type**: DSP + * + * **Syntax**:\n + * ~~~ + * KDMxy Rd, Rs1, Rs2 (xy = BB, BT, TT) + * ~~~ + * + * **Purpose**:\n + * Multiply the signed Q15 integer contents of two 16-bit data in the corresponding portion + * of the lower 32-bit chunk in registers and then double and saturate the Q31 result. The result is + * written into the destination register for RV32 or sign-extended to 64-bits and written into the + * destination register for RV64. If saturation happens, an overflow flag OV will be set. + * + * **Description**:\n + * Multiply the top or bottom 16-bit Q15 content of the lower 32-bit portion in Rs1 with + * the top or bottom 16-bit Q15 content of the lower 32-bit portion in Rs2. The Q30 result is then + * doubled and saturated into a Q31 value. The Q31 value is then written into Rd (sign-extended in + * RV64). When both the two Q15 inputs are 0x8000, saturation will happen. The result will be + * saturated to 0x7FFFFFFF and the overflow flag OV will be set. + * + * **Operations**:\n + * ~~~ + * aop = Rs1.H[0]; bop = Rs2.H[0]; // KDMBB + * aop = Rs1.H[0]; bop = Rs2.H[1]; // KDMBT + * aop = Rs1.H[1]; bop = Rs2.H[1]; // KDMTT + * If (0x8000 != aop | 0x8000 != bop) { + * Mresult = aop * bop; + * resQ31 = Mresult << 1; + * Rd = resQ31; // RV32 + * Rd = SE(resQ31); // RV64 + * } else { + * resQ31 = 0x7FFFFFFF; + * Rd = resQ31; // RV32 + * Rd = SE(resQ31); // RV64 + * OV = 1; + * } + * ~~~ + * + * \param [in] a unsigned int type of value stored in a + * \param [in] b unsigned int type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_KDMBB(unsigned int a, unsigned int b) +{ + register long result; + __ASM volatile("kdmbb %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.33.1. KDMBB ===== */ + +/* ===== Inline Function Start for 3.33.2. KDMBT ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q31_SAT_ALU + * \brief KDMBT (Signed Saturating Double Multiply B16 x T16) + * \details + * **Type**: DSP + * + * **Syntax**:\n + * ~~~ + * KDMxy Rd, Rs1, Rs2 (xy = BB, BT, TT) + * ~~~ + * + * **Purpose**:\n + * Multiply the signed Q15 integer contents of two 16-bit data in the corresponding portion + * of the lower 32-bit chunk in registers and then double and saturate the Q31 result. The result is + * written into the destination register for RV32 or sign-extended to 64-bits and written into the + * destination register for RV64. If saturation happens, an overflow flag OV will be set. + * + * **Description**:\n + * Multiply the top or bottom 16-bit Q15 content of the lower 32-bit portion in Rs1 with + * the top or bottom 16-bit Q15 content of the lower 32-bit portion in Rs2. The Q30 result is then + * doubled and saturated into a Q31 value. The Q31 value is then written into Rd (sign-extended in + * RV64). When both the two Q15 inputs are 0x8000, saturation will happen. The result will be + * saturated to 0x7FFFFFFF and the overflow flag OV will be set. + * + * **Operations**:\n + * ~~~ + * aop = Rs1.H[0]; bop = Rs2.H[0]; // KDMBB + * aop = Rs1.H[0]; bop = Rs2.H[1]; // KDMBT + * aop = Rs1.H[1]; bop = Rs2.H[1]; // KDMTT + * If (0x8000 != aop | 0x8000 != bop) { + * Mresult = aop * bop; + * resQ31 = Mresult << 1; + * Rd = resQ31; // RV32 + * Rd = SE(resQ31); // RV64 + * } else { + * resQ31 = 0x7FFFFFFF; + * Rd = resQ31; // RV32 + * Rd = SE(resQ31); // RV64 + * OV = 1; + * } + * ~~~ + * + * \param [in] a unsigned int type of value stored in a + * \param [in] b unsigned int type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_KDMBT(unsigned int a, unsigned int b) +{ + register long result; + __ASM volatile("kdmbt %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.33.2. KDMBT ===== */ + +/* ===== Inline Function Start for 3.33.3. KDMTT ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q31_SAT_ALU + * \brief KDMTT (Signed Saturating Double Multiply T16 x T16) + * \details + * **Type**: DSP + * + * **Syntax**:\n + * ~~~ + * KDMxy Rd, Rs1, Rs2 (xy = BB, BT, TT) + * ~~~ + * + * **Purpose**:\n + * Multiply the signed Q15 integer contents of two 16-bit data in the corresponding portion + * of the lower 32-bit chunk in registers and then double and saturate the Q31 result. The result is + * written into the destination register for RV32 or sign-extended to 64-bits and written into the + * destination register for RV64. If saturation happens, an overflow flag OV will be set. + * + * **Description**:\n + * Multiply the top or bottom 16-bit Q15 content of the lower 32-bit portion in Rs1 with + * the top or bottom 16-bit Q15 content of the lower 32-bit portion in Rs2. The Q30 result is then + * doubled and saturated into a Q31 value. The Q31 value is then written into Rd (sign-extended in + * RV64). When both the two Q15 inputs are 0x8000, saturation will happen. The result will be + * saturated to 0x7FFFFFFF and the overflow flag OV will be set. + * + * **Operations**:\n + * ~~~ + * aop = Rs1.H[0]; bop = Rs2.H[0]; // KDMBB + * aop = Rs1.H[0]; bop = Rs2.H[1]; // KDMBT + * aop = Rs1.H[1]; bop = Rs2.H[1]; // KDMTT + * If (0x8000 != aop | 0x8000 != bop) { + * Mresult = aop * bop; + * resQ31 = Mresult << 1; + * Rd = resQ31; // RV32 + * Rd = SE(resQ31); // RV64 + * } else { + * resQ31 = 0x7FFFFFFF; + * Rd = resQ31; // RV32 + * Rd = SE(resQ31); // RV64 + * OV = 1; + * } + * ~~~ + * + * \param [in] a unsigned int type of value stored in a + * \param [in] b unsigned int type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_KDMTT(unsigned int a, unsigned int b) +{ + register long result; + __ASM volatile("kdmtt %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.33.3. KDMTT ===== */ + +/* ===== Inline Function Start for 3.34.1. KDMABB ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q31_SAT_ALU + * \brief KDMABB (Signed Saturating Double Multiply Addition B16 x B16) + * \details + * **Type**: DSP + * + * **Syntax**:\n + * ~~~ + * KDMAxy Rd, Rs1, Rs2 (xy = BB, BT, TT) + * ~~~ + * + * **Purpose**:\n + * Multiply the signed Q15 integer contents of two 16-bit data in the corresponding portion + * of the lower 32-bit chunk in registers and then double and saturate the Q31 result, add the result + * with the sign-extended lower 32-bit chunk destination register and write the saturated addition + * result into the destination register. If saturation happens, an overflow flag OV will be set. + * + * **Description**:\n + * Multiply the top or bottom 16-bit Q15 content of the lower 32-bit portion in Rs1 with + * the top or bottom 16-bit Q15 content of the lower 32-bit portion in Rs2. The Q30 result is then + * doubled and saturated into a Q31 value. The Q31 value is then added with the content of Rd. If the + * addition result is beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), it is saturated to the range and + * the OV flag is set to 1. The result after saturation is written to Rd. + * When both the two Q15 inputs are 0x8000, saturation will happen and the overflow flag OV will be + * set. + * + * **Operations**:\n + * ~~~ + * aop = Rs1.H[0]; bop = Rs2.H[0]; // KDMABB + * aop = Rs1.H[0]; bop = Rs2.H[1]; // KDMABT + * aop = Rs1.H[1]; bop = Rs2.H[1]; // KDMATT + * If (0x8000 != aop | 0x8000 != bop) { + * Mresult = aop * bop; + * resQ31 = Mresult << 1; + * } else { + * resQ31 = 0x7FFFFFFF; + * OV = 1; + * } + * resadd = Rd + resQ31; // RV32 + * resadd = Rd.W[0] + resQ31; // RV64 + * if (resadd > (2^31)-1) { + * resadd = (2^31)-1; + * OV = 1; + * } else if (resadd < -2^31) { + * resadd = -2^31; + * OV = 1; + * } + * Rd = resadd; // RV32 + * Rd = SE(resadd); // RV64 + * ~~~ + * + * \param [in] t long type of value stored in t + * \param [in] a unsigned int type of value stored in a + * \param [in] b unsigned int type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_KDMABB(long t, unsigned int a, unsigned int b) +{ + __ASM volatile("kdmabb %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); + return t; +} +/* ===== Inline Function End for 3.34.1. KDMABB ===== */ + +/* ===== Inline Function Start for 3.34.2. KDMABT ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q31_SAT_ALU + * \brief KDMABT (Signed Saturating Double Multiply Addition B16 x T16) + * \details + * **Type**: DSP + * + * **Syntax**:\n + * ~~~ + * KDMAxy Rd, Rs1, Rs2 (xy = BB, BT, TT) + * ~~~ + * + * **Purpose**:\n + * Multiply the signed Q15 integer contents of two 16-bit data in the corresponding portion + * of the lower 32-bit chunk in registers and then double and saturate the Q31 result, add the result + * with the sign-extended lower 32-bit chunk destination register and write the saturated addition + * result into the destination register. If saturation happens, an overflow flag OV will be set. + * + * **Description**:\n + * Multiply the top or bottom 16-bit Q15 content of the lower 32-bit portion in Rs1 with + * the top or bottom 16-bit Q15 content of the lower 32-bit portion in Rs2. The Q30 result is then + * doubled and saturated into a Q31 value. The Q31 value is then added with the content of Rd. If the + * addition result is beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), it is saturated to the range and + * the OV flag is set to 1. The result after saturation is written to Rd. + * When both the two Q15 inputs are 0x8000, saturation will happen and the overflow flag OV will be + * set. + * + * **Operations**:\n + * ~~~ + * aop = Rs1.H[0]; bop = Rs2.H[0]; // KDMABB + * aop = Rs1.H[0]; bop = Rs2.H[1]; // KDMABT + * aop = Rs1.H[1]; bop = Rs2.H[1]; // KDMATT + * If (0x8000 != aop | 0x8000 != bop) { + * Mresult = aop * bop; + * resQ31 = Mresult << 1; + * } else { + * resQ31 = 0x7FFFFFFF; + * OV = 1; + * } + * resadd = Rd + resQ31; // RV32 + * resadd = Rd.W[0] + resQ31; // RV64 + * if (resadd > (2^31)-1) { + * resadd = (2^31)-1; + * OV = 1; + * } else if (resadd < -2^31) { + * resadd = -2^31; + * OV = 1; + * } + * Rd = resadd; // RV32 + * Rd = SE(resadd); // RV64 + * ~~~ + * + * \param [in] t long type of value stored in t + * \param [in] a unsigned int type of value stored in a + * \param [in] b unsigned int type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_KDMABT(long t, unsigned int a, unsigned int b) +{ + __ASM volatile("kdmabt %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); + return t; +} +/* ===== Inline Function End for 3.34.2. KDMABT ===== */ + +/* ===== Inline Function Start for 3.34.3. KDMATT ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q31_SAT_ALU + * \brief KDMATT (Signed Saturating Double Multiply Addition T16 x T16) + * \details + * **Type**: DSP + * + * **Syntax**:\n + * ~~~ + * KDMAxy Rd, Rs1, Rs2 (xy = BB, BT, TT) + * ~~~ + * + * **Purpose**:\n + * Multiply the signed Q15 integer contents of two 16-bit data in the corresponding portion + * of the lower 32-bit chunk in registers and then double and saturate the Q31 result, add the result + * with the sign-extended lower 32-bit chunk destination register and write the saturated addition + * result into the destination register. If saturation happens, an overflow flag OV will be set. + * + * **Description**:\n + * Multiply the top or bottom 16-bit Q15 content of the lower 32-bit portion in Rs1 with + * the top or bottom 16-bit Q15 content of the lower 32-bit portion in Rs2. The Q30 result is then + * doubled and saturated into a Q31 value. The Q31 value is then added with the content of Rd. If the + * addition result is beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), it is saturated to the range and + * the OV flag is set to 1. The result after saturation is written to Rd. + * When both the two Q15 inputs are 0x8000, saturation will happen and the overflow flag OV will be + * set. + * + * **Operations**:\n + * ~~~ + * aop = Rs1.H[0]; bop = Rs2.H[0]; // KDMABB + * aop = Rs1.H[0]; bop = Rs2.H[1]; // KDMABT + * aop = Rs1.H[1]; bop = Rs2.H[1]; // KDMATT + * If (0x8000 != aop | 0x8000 != bop) { + * Mresult = aop * bop; + * resQ31 = Mresult << 1; + * } else { + * resQ31 = 0x7FFFFFFF; + * OV = 1; + * } + * resadd = Rd + resQ31; // RV32 + * resadd = Rd.W[0] + resQ31; // RV64 + * if (resadd > (2^31)-1) { + * resadd = (2^31)-1; + * OV = 1; + * } else if (resadd < -2^31) { + * resadd = -2^31; + * OV = 1; + * } + * Rd = resadd; // RV32 + * Rd = SE(resadd); // RV64 + * ~~~ + * + * \param [in] t long type of value stored in t + * \param [in] a unsigned int type of value stored in a + * \param [in] b unsigned int type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_KDMATT(long t, unsigned int a, unsigned int b) +{ + __ASM volatile("kdmatt %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); + return t; +} +/* ===== Inline Function End for 3.34.3. KDMATT ===== */ + +/* ===== Inline Function Start for 3.35.1. KHM8 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_MULTIPLY + * \brief KHM8 (SIMD Signed Saturating Q7 Multiply) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * KHM8 Rd, Rs1, Rs2 + * KHMX8 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do Q7xQ7 element multiplications simultaneously. The Q14 results are then reduced to Q7 + * numbers again. + * + * **Description**:\n + * For the `KHM8` instruction, multiply the top 8-bit Q7 content of 16-bit chunks in Rs1 + * with the top 8-bit Q7 content of 16-bit chunks in Rs2. At the same time, multiply the bottom 8-bit Q7 + * content of 16-bit chunks in Rs1 with the bottom 8-bit Q7 content of 16-bit chunks in Rs2. + * For the `KHMX16` instruction, multiply the top 8-bit Q7 content of 16-bit chunks in Rs1 with the + * bottom 8-bit Q7 content of 16-bit chunks in Rs2. At the same time, multiply the bottom 8-bit Q7 + * content of 16-bit chunks in Rs1 with the top 8-bit Q7 content of 16-bit chunks in Rs2. + * The Q14 results are then right-shifted 7-bits and saturated into Q7 values. The Q7 results are then + * written into Rd. When both the two Q7 inputs of a multiplication are 0x80, saturation will happen. + * The result will be saturated to 0x7F and the overflow flag OV will be set. + * + * **Operations**:\n + * ~~~ + * if (is `KHM8`) { + * op1t = Rs1.B[x+1]; op2t = Rs2.B[x+1]; // top + * op1b = Rs1.B[x]; op2b = Rs2.B[x]; // bottom + * } else if (is `KHMX8`) { + * op1t = Rs1.H[x+1]; op2t = Rs2.H[x]; // Rs1 top + * op1b = Rs1.H[x]; op2b = Rs2.H[x+1]; // Rs1 bottom + * } + * for ((aop,bop,res) in [(op1t,op2t,rest), (op1b,op2b,resb)]) { + * if (0x80 != aop | 0x80 != bop) { + * res = (aop s* bop) >> 7; + * } else { + * res= 0x7F; + * OV = 1; + * } + * } + * Rd.H[x/2] = concat(rest, resb); + * for RV32, x=0,2 + * for RV64, x=0,2,4,6 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_KHM8(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("khm8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.35.1. KHM8 ===== */ + +/* ===== Inline Function Start for 3.35.2. KHMX8 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_MULTIPLY + * \brief KHMX8 (SIMD Signed Saturating Crossed Q7 Multiply) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * KHM8 Rd, Rs1, Rs2 + * KHMX8 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do Q7xQ7 element multiplications simultaneously. The Q14 results are then reduced to Q7 + * numbers again. + * + * **Description**:\n + * For the `KHM8` instruction, multiply the top 8-bit Q7 content of 16-bit chunks in Rs1 + * with the top 8-bit Q7 content of 16-bit chunks in Rs2. At the same time, multiply the bottom 8-bit Q7 + * content of 16-bit chunks in Rs1 with the bottom 8-bit Q7 content of 16-bit chunks in Rs2. + * For the `KHMX16` instruction, multiply the top 8-bit Q7 content of 16-bit chunks in Rs1 with the + * bottom 8-bit Q7 content of 16-bit chunks in Rs2. At the same time, multiply the bottom 8-bit Q7 + * content of 16-bit chunks in Rs1 with the top 8-bit Q7 content of 16-bit chunks in Rs2. + * The Q14 results are then right-shifted 7-bits and saturated into Q7 values. The Q7 results are then + * written into Rd. When both the two Q7 inputs of a multiplication are 0x80, saturation will happen. + * The result will be saturated to 0x7F and the overflow flag OV will be set. + * + * **Operations**:\n + * ~~~ + * if (is `KHM8`) { + * op1t = Rs1.B[x+1]; op2t = Rs2.B[x+1]; // top + * op1b = Rs1.B[x]; op2b = Rs2.B[x]; // bottom + * } else if (is `KHMX8`) { + * op1t = Rs1.H[x+1]; op2t = Rs2.H[x]; // Rs1 top + * op1b = Rs1.H[x]; op2b = Rs2.H[x+1]; // Rs1 bottom + * } + * for ((aop,bop,res) in [(op1t,op2t,rest), (op1b,op2b,resb)]) { + * if (0x80 != aop | 0x80 != bop) { + * res = (aop s* bop) >> 7; + * } else { + * res= 0x7F; + * OV = 1; + * } + * } + * Rd.H[x/2] = concat(rest, resb); + * for RV32, x=0,2 + * for RV64, x=0,2,4,6 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_KHMX8(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("khmx8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.35.2. KHMX8 ===== */ + +/* ===== Inline Function Start for 3.36.1. KHM16 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_MULTIPLY + * \brief KHM16 (SIMD Signed Saturating Q15 Multiply) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * KHM16 Rd, Rs1, Rs2 + * KHMX16 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do Q15xQ15 element multiplications simultaneously. The Q30 results are then reduced to + * Q15 numbers again. + * + * **Description**:\n + * For the `KHM16` instruction, multiply the top 16-bit Q15 content of 32-bit chunks in + * Rs1 with the top 16-bit Q15 content of 32-bit chunks in Rs2. At the same time, multiply the bottom + * 16-bit Q15 content of 32-bit chunks in Rs1 with the bottom 16-bit Q15 content of 32-bit chunks in + * Rs2. + * For the `KHMX16` instruction, multiply the top 16-bit Q15 content of 32-bit chunks in Rs1 with the + * bottom 16-bit Q15 content of 32-bit chunks in Rs2. At the same time, multiply the bottom 16-bit Q15 + * content of 32-bit chunks in Rs1 with the top 16-bit Q15 content of 32-bit chunks in Rs2. + * The Q30 results are then right-shifted 15-bits and saturated into Q15 values. The Q15 results are + * then written into Rd. When both the two Q15 inputs of a multiplication are 0x8000, saturation will + * happen. The result will be saturated to 0x7FFF and the overflow flag OV will be set. + * + * **Operations**:\n + * ~~~ + * if (is `KHM16`) { + * op1t = Rs1.H[x+1]; op2t = Rs2.H[x+1]; // top + * op1b = Rs1.H[x]; op2b = Rs2.H[x]; // bottom + * } else if (is `KHMX16`) { + * op1t = Rs1.H[x+1]; op2t = Rs2.H[x]; // Rs1 top + * op1b = Rs1.H[x]; op2b = Rs2.H[x+1]; // Rs1 bottom + * } + * for ((aop,bop,res) in [(op1t,op2t,rest), (op1b,op2b,resb)]) { + * if (0x8000 != aop | 0x8000 != bop) { + * res = (aop s* bop) >> 15; + * } else { + * res= 0x7FFF; + * OV = 1; + * } + * } + * Rd.W[x/2] = concat(rest, resb); + * for RV32: x=0 + * for RV64: x=0,2 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_KHM16(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("khm16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.36.1. KHM16 ===== */ + +/* ===== Inline Function Start for 3.36.2. KHMX16 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_MULTIPLY + * \brief KHMX16 (SIMD Signed Saturating Crossed Q15 Multiply) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * KHM16 Rd, Rs1, Rs2 + * KHMX16 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do Q15xQ15 element multiplications simultaneously. The Q30 results are then reduced to + * Q15 numbers again. + * + * **Description**:\n + * For the `KHM16` instruction, multiply the top 16-bit Q15 content of 32-bit chunks in + * Rs1 with the top 16-bit Q15 content of 32-bit chunks in Rs2. At the same time, multiply the bottom + * 16-bit Q15 content of 32-bit chunks in Rs1 with the bottom 16-bit Q15 content of 32-bit chunks in + * Rs2. + * For the `KHMX16` instruction, multiply the top 16-bit Q15 content of 32-bit chunks in Rs1 with the + * bottom 16-bit Q15 content of 32-bit chunks in Rs2. At the same time, multiply the bottom 16-bit Q15 + * content of 32-bit chunks in Rs1 with the top 16-bit Q15 content of 32-bit chunks in Rs2. + * The Q30 results are then right-shifted 15-bits and saturated into Q15 values. The Q15 results are + * then written into Rd. When both the two Q15 inputs of a multiplication are 0x8000, saturation will + * happen. The result will be saturated to 0x7FFF and the overflow flag OV will be set. + * + * **Operations**:\n + * ~~~ + * if (is `KHM16`) { + * op1t = Rs1.H[x+1]; op2t = Rs2.H[x+1]; // top + * op1b = Rs1.H[x]; op2b = Rs2.H[x]; // bottom + * } else if (is `KHMX16`) { + * op1t = Rs1.H[x+1]; op2t = Rs2.H[x]; // Rs1 top + * op1b = Rs1.H[x]; op2b = Rs2.H[x+1]; // Rs1 bottom + * } + * for ((aop,bop,res) in [(op1t,op2t,rest), (op1b,op2b,resb)]) { + * if (0x8000 != aop | 0x8000 != bop) { + * res = (aop s* bop) >> 15; + * } else { + * res= 0x7FFF; + * OV = 1; + * } + * } + * Rd.W[x/2] = concat(rest, resb); + * for RV32: x=0 + * for RV64: x=0,2 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_KHMX16(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("khmx16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.36.2. KHMX16 ===== */ + +/* ===== Inline Function Start for 3.37.1. KHMBB ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q15_SAT_ALU + * \brief KHMBB (Signed Saturating Half Multiply B16 x B16) + * \details + * **Type**: DSP + * + * **Syntax**:\n + * ~~~ + * KHMxy Rd, Rs1, Rs2 (xy = BB, BT, TT) + * ~~~ + * + * **Purpose**:\n + * Multiply the signed Q15 number contents of two 16-bit data in the corresponding portion + * of the lower 32-bit chunk in registers and then right-shift 15 bits to turn the Q30 result into a Q15 + * number again and saturate the Q15 result into the destination register. If saturation happens, an + * overflow flag OV will be set. + * + * **Description**:\n + * Multiply the top or bottom 16-bit Q15 content of the lower 32-bit portion in Rs1 with + * the top or bottom 16-bit Q15 content of the lower 32-bit portion in Rs2. The Q30 result is then right- + * shifted 15-bits and saturated into a Q15 value. The Q15 value is then sing-extended and written into + * Rd. When both the two Q15 inputs are 0x8000, saturation will happen. The result will be saturated + * to 0x7FFF and the overflow flag OV will be set. + * + * **Operations**:\n + * ~~~ + * aop = Rs1.H[0]; bop = Rs2.H[0]; // KHMBB + * aop = Rs1.H[0]; bop = Rs2.H[1]; // KHMBT + * aop = Rs1.H[1]; bop = Rs2.H[1]; // KHMTT + * If (0x8000 != aop | 0x8000 != bop) { + * Mresult[31:0] = aop * bop; + * res[15:0] = Mresult[30:15]; + * } else { + * res[15:0] = 0x7FFF; + * OV = 1; + * } + * Rd = SE32(res[15:0]); // Rv32 + * Rd = SE64(res[15:0]); // RV64 + * ~~~ + * + * \param [in] a unsigned int type of value stored in a + * \param [in] b unsigned int type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_KHMBB(unsigned int a, unsigned int b) +{ + register long result; + __ASM volatile("khmbb %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.37.1. KHMBB ===== */ + +/* ===== Inline Function Start for 3.37.2. KHMBT ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q15_SAT_ALU + * \brief KHMBT (Signed Saturating Half Multiply B16 x T16) + * \details + * **Type**: DSP + * + * **Syntax**:\n + * ~~~ + * KHMxy Rd, Rs1, Rs2 (xy = BB, BT, TT) + * ~~~ + * + * **Purpose**:\n + * Multiply the signed Q15 number contents of two 16-bit data in the corresponding portion + * of the lower 32-bit chunk in registers and then right-shift 15 bits to turn the Q30 result into a Q15 + * number again and saturate the Q15 result into the destination register. If saturation happens, an + * overflow flag OV will be set. + * + * **Description**:\n + * Multiply the top or bottom 16-bit Q15 content of the lower 32-bit portion in Rs1 with + * the top or bottom 16-bit Q15 content of the lower 32-bit portion in Rs2. The Q30 result is then right- + * shifted 15-bits and saturated into a Q15 value. The Q15 value is then sing-extended and written into + * Rd. When both the two Q15 inputs are 0x8000, saturation will happen. The result will be saturated + * to 0x7FFF and the overflow flag OV will be set. + * + * **Operations**:\n + * ~~~ + * aop = Rs1.H[0]; bop = Rs2.H[0]; // KHMBB + * aop = Rs1.H[0]; bop = Rs2.H[1]; // KHMBT + * aop = Rs1.H[1]; bop = Rs2.H[1]; // KHMTT + * If (0x8000 != aop | 0x8000 != bop) { + * Mresult[31:0] = aop * bop; + * res[15:0] = Mresult[30:15]; + * } else { + * res[15:0] = 0x7FFF; + * OV = 1; + * } + * Rd = SE32(res[15:0]); // Rv32 + * Rd = SE64(res[15:0]); // RV64 + * ~~~ + * + * \param [in] a unsigned int type of value stored in a + * \param [in] b unsigned int type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_KHMBT(unsigned int a, unsigned int b) +{ + register long result; + __ASM volatile("khmbt %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.37.2. KHMBT ===== */ + +/* ===== Inline Function Start for 3.37.3. KHMTT ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q15_SAT_ALU + * \brief KHMTT (Signed Saturating Half Multiply T16 x T16) + * \details + * **Type**: DSP + * + * **Syntax**:\n + * ~~~ + * KHMxy Rd, Rs1, Rs2 (xy = BB, BT, TT) + * ~~~ + * + * **Purpose**:\n + * Multiply the signed Q15 number contents of two 16-bit data in the corresponding portion + * of the lower 32-bit chunk in registers and then right-shift 15 bits to turn the Q30 result into a Q15 + * number again and saturate the Q15 result into the destination register. If saturation happens, an + * overflow flag OV will be set. + * + * **Description**:\n + * Multiply the top or bottom 16-bit Q15 content of the lower 32-bit portion in Rs1 with + * the top or bottom 16-bit Q15 content of the lower 32-bit portion in Rs2. The Q30 result is then right- + * shifted 15-bits and saturated into a Q15 value. The Q15 value is then sing-extended and written into + * Rd. When both the two Q15 inputs are 0x8000, saturation will happen. The result will be saturated + * to 0x7FFF and the overflow flag OV will be set. + * + * **Operations**:\n + * ~~~ + * aop = Rs1.H[0]; bop = Rs2.H[0]; // KHMBB + * aop = Rs1.H[0]; bop = Rs2.H[1]; // KHMBT + * aop = Rs1.H[1]; bop = Rs2.H[1]; // KHMTT + * If (0x8000 != aop | 0x8000 != bop) { + * Mresult[31:0] = aop * bop; + * res[15:0] = Mresult[30:15]; + * } else { + * res[15:0] = 0x7FFF; + * OV = 1; + * } + * Rd = SE32(res[15:0]); // Rv32 + * Rd = SE64(res[15:0]); // RV64 + * ~~~ + * + * \param [in] a unsigned int type of value stored in a + * \param [in] b unsigned int type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_KHMTT(unsigned int a, unsigned int b) +{ + register long result; + __ASM volatile("khmtt %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.37.3. KHMTT ===== */ + +/* ===== Inline Function Start for 3.38.1. KMABB ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_32B_ADDSUB + * \brief KMABB (SIMD Saturating Signed Multiply Bottom Halfs & Add) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * KMABB Rd, Rs1, Rs2 + * KMABT Rd, Rs1, Rs2 + * KMATT Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Multiply the signed 16-bit content of 32-bit elements in a register with the 16-bit content + * of 32-bit elements in another register and add the result to the content of 32-bit elements in the + * third register. The addition result may be saturated and is written to the third register. + * * KMABB: rd.W[x] + bottom*bottom (per 32-bit element) + * * KMABT rd.W[x] + bottom*top (per 32-bit element) + * * KMATT rd.W[x] + top*top (per 32-bit element) + * + * **Description**:\n + * For the `KMABB` instruction, it multiplies the bottom 16-bit content of 32-bit elements in Rs1 with + * the bottom 16-bit content of 32-bit elements in Rs2. + * For the `KMABT` instruction, it multiplies the bottom 16-bit content of 32-bit elements in Rs1 with + * the top 16-bit content of 32-bit elements in Rs2. + * For the `KMATT` instruction, it multiplies the top 16-bit content of 32-bit elements in Rs1 with the + * top 16-bit content of 32-bit elements in Rs2. + * The multiplication result is added to the content of 32-bit elements in Rd. If the addition result is + * beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), it is saturated to the range and the OV bit is set to + * 1. The results after saturation are written to Rd. The 16-bit contents of Rs1 and Rs2 are treated as + * signed integers. + * + * **Operations**:\n + * ~~~ + * res[x] = Rd.W[x] + (Rs1.W[x].H[0] * Rs2.W[x].H[0]); // KMABB + * res[x] = Rd.W[x] + (Rs1.W[x].H[0] * Rs2.W[x].H[1]); // KMABT + * res[x] = Rd.W[x] + (Rs1.W[x].H[1] * Rs2.W[x].H[1]); // KMATT + * if (res[x] > (2^31)-1) { + * res[x] = (2^31)-1; + * OV = 1; + * } else if (res[x] < -2^31) { + * res[x] = -2^31; + * OV = 1; + * } + * Rd.W[x] = res[x]; + * for RV32: x=0 + * for RV64: x=1...0 + * ~~~ + * + * \param [in] t long type of value stored in t + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_KMABB(long t, unsigned long a, unsigned long b) +{ + __ASM volatile("kmabb %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); + return t; +} +/* ===== Inline Function End for 3.38.1. KMABB ===== */ + +/* ===== Inline Function Start for 3.38.2. KMABT ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_32B_ADDSUB + * \brief KMABT (SIMD Saturating Signed Multiply Bottom & Top Halfs & Add) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * KMABB Rd, Rs1, Rs2 + * KMABT Rd, Rs1, Rs2 + * KMATT Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Multiply the signed 16-bit content of 32-bit elements in a register with the 16-bit content + * of 32-bit elements in another register and add the result to the content of 32-bit elements in the + * third register. The addition result may be saturated and is written to the third register. + * * KMABB: rd.W[x] + bottom*bottom (per 32-bit element) + * * KMABT rd.W[x] + bottom*top (per 32-bit element) + * * KMATT rd.W[x] + top*top (per 32-bit element) + * + * **Description**:\n + * For the `KMABB` instruction, it multiplies the bottom 16-bit content of 32-bit elements in Rs1 with + * the bottom 16-bit content of 32-bit elements in Rs2. + * For the `KMABT` instruction, it multiplies the bottom 16-bit content of 32-bit elements in Rs1 with + * the top 16-bit content of 32-bit elements in Rs2. + * For the `KMATT` instruction, it multiplies the top 16-bit content of 32-bit elements in Rs1 with the + * top 16-bit content of 32-bit elements in Rs2. + * The multiplication result is added to the content of 32-bit elements in Rd. If the addition result is + * beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), it is saturated to the range and the OV bit is set to + * 1. The results after saturation are written to Rd. The 16-bit contents of Rs1 and Rs2 are treated as + * signed integers. + * + * **Operations**:\n + * ~~~ + * res[x] = Rd.W[x] + (Rs1.W[x].H[0] * Rs2.W[x].H[0]); // KMABB + * res[x] = Rd.W[x] + (Rs1.W[x].H[0] * Rs2.W[x].H[1]); // KMABT + * res[x] = Rd.W[x] + (Rs1.W[x].H[1] * Rs2.W[x].H[1]); // KMATT + * if (res[x] > (2^31)-1) { + * res[x] = (2^31)-1; + * OV = 1; + * } else if (res[x] < -2^31) { + * res[x] = -2^31; + * OV = 1; + * } + * Rd.W[x] = res[x]; + * for RV32: x=0 + * for RV64: x=1...0 + * ~~~ + * + * \param [in] t long type of value stored in t + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_KMABT(long t, unsigned long a, unsigned long b) +{ + __ASM volatile("kmabt %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); + return t; +} +/* ===== Inline Function End for 3.38.2. KMABT ===== */ + +/* ===== Inline Function Start for 3.38.3. KMATT ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_32B_ADDSUB + * \brief KMATT (SIMD Saturating Signed Multiply Top Halfs & Add) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * KMABB Rd, Rs1, Rs2 + * KMABT Rd, Rs1, Rs2 + * KMATT Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Multiply the signed 16-bit content of 32-bit elements in a register with the 16-bit content + * of 32-bit elements in another register and add the result to the content of 32-bit elements in the + * third register. The addition result may be saturated and is written to the third register. + * * KMABB: rd.W[x] + bottom*bottom (per 32-bit element) + * * KMABT rd.W[x] + bottom*top (per 32-bit element) + * * KMATT rd.W[x] + top*top (per 32-bit element) + * + * **Description**:\n + * For the `KMABB` instruction, it multiplies the bottom 16-bit content of 32-bit elements in Rs1 with + * the bottom 16-bit content of 32-bit elements in Rs2. + * For the `KMABT` instruction, it multiplies the bottom 16-bit content of 32-bit elements in Rs1 with + * the top 16-bit content of 32-bit elements in Rs2. + * For the `KMATT` instruction, it multiplies the top 16-bit content of 32-bit elements in Rs1 with the + * top 16-bit content of 32-bit elements in Rs2. + * The multiplication result is added to the content of 32-bit elements in Rd. If the addition result is + * beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), it is saturated to the range and the OV bit is set to + * 1. The results after saturation are written to Rd. The 16-bit contents of Rs1 and Rs2 are treated as + * signed integers. + * + * **Operations**:\n + * ~~~ + * res[x] = Rd.W[x] + (Rs1.W[x].H[0] * Rs2.W[x].H[0]); // KMABB + * res[x] = Rd.W[x] + (Rs1.W[x].H[0] * Rs2.W[x].H[1]); // KMABT + * res[x] = Rd.W[x] + (Rs1.W[x].H[1] * Rs2.W[x].H[1]); // KMATT + * if (res[x] > (2^31)-1) { + * res[x] = (2^31)-1; + * OV = 1; + * } else if (res[x] < -2^31) { + * res[x] = -2^31; + * OV = 1; + * } + * Rd.W[x] = res[x]; + * for RV32: x=0 + * for RV64: x=1...0 + * ~~~ + * + * \param [in] t long type of value stored in t + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_KMATT(long t, unsigned long a, unsigned long b) +{ + __ASM volatile("kmatt %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); + return t; +} +/* ===== Inline Function End for 3.38.3. KMATT ===== */ + +/* ===== Inline Function Start for 3.39.1. KMADA ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_32B_ADDSUB + * \brief KMADA (SIMD Saturating Signed Multiply Two Halfs and Two Adds) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * KMADA Rd, Rs1, Rs2 + * KMAXDA Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do two signed 16-bit multiplications from 32-bit elements in two registers; and then adds + * the two 32-bit results and 32-bit elements in a third register together. The addition result may be + * saturated. + * * KMADA: rd.W[x] + top*top + bottom*bottom (per 32-bit element) + * * KMAXDA: rd.W[x] + top*bottom + bottom*top (per 32-bit element) + * + * **Description**:\n + * For the `KMADA instruction, it multiplies the bottom 16-bit content of 32-bit elements in Rs1 with + * the bottom 16-bit content of 32-bit elements in Rs2 and then adds the result to the result of + * multiplying the top 16-bit content of 32-bit elements in Rs1 with the top 16-bit content of 32-bit + * elements in Rs2. + * For the `KMAXDA` instruction, it multiplies the top 16-bit content of 32-bit elements in Rs1 with the + * bottom 16-bit content of 32-bit elements in Rs2 and then adds the result to the result of multiplying + * the bottom 16-bit content of 32-bit elements in Rs1 with the top 16-bit content of 32-bit elements in + * Rs2. + * The result is added to the content of 32-bit elements in Rd. If the addition result is beyond the Q31 + * number range (-2^31 <= Q31 <= 2^31-1), it is saturated to the range and the OV bit is set to 1. The 32-bit + * results after saturation are written to Rd. The 16-bit contents of Rs1 and Rs2 are treated as signed + * integers. + * + * **Operations**:\n + * ~~~ + * // KMADA + * res[x] = Rd.W[x] + (Rs1.W[x].H[1] * Rs2.W[x].H[1]) + (Rs1.W[x].H[0] * Rs2.W[x].H[0]); + * // KMAXDA + * res[x] = Rd.W[x] + (Rs1.W[x].H[1] * Rs2.W[x].H[0]) + (Rs1.W[x].H[0] * Rs2.W[x].H[1]); + * if (res[x] > (2^31)-1) { + * res[x] = (2^31)-1; + * OV = 1; + * } else if (res[x] < -2^31) { + * res[x] = -2^31; + * OV = 1; + * } + * Rd.W[x] = res[x]; + * for RV32: x=0 + * for RV64: x=1...0 + * ~~~ + * + * \param [in] t long type of value stored in t + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_KMADA(long t, unsigned long a, unsigned long b) +{ + __ASM volatile("kmada %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); + return t; +} +/* ===== Inline Function End for 3.39.1. KMADA ===== */ + +/* ===== Inline Function Start for 3.39.2. KMAXDA ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_32B_ADDSUB + * \brief KMAXDA (SIMD Saturating Signed Crossed Multiply Two Halfs and Two Adds) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * KMADA Rd, Rs1, Rs2 + * KMAXDA Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do two signed 16-bit multiplications from 32-bit elements in two registers; and then adds + * the two 32-bit results and 32-bit elements in a third register together. The addition result may be + * saturated. + * * KMADA: rd.W[x] + top*top + bottom*bottom (per 32-bit element) + * * KMAXDA: rd.W[x] + top*bottom + bottom*top (per 32-bit element) + * + * **Description**:\n + * For the `KMADA instruction, it multiplies the bottom 16-bit content of 32-bit elements in Rs1 with + * the bottom 16-bit content of 32-bit elements in Rs2 and then adds the result to the result of + * multiplying the top 16-bit content of 32-bit elements in Rs1 with the top 16-bit content of 32-bit + * elements in Rs2. + * For the `KMAXDA` instruction, it multiplies the top 16-bit content of 32-bit elements in Rs1 with the + * bottom 16-bit content of 32-bit elements in Rs2 and then adds the result to the result of multiplying + * the bottom 16-bit content of 32-bit elements in Rs1 with the top 16-bit content of 32-bit elements in + * Rs2. + * The result is added to the content of 32-bit elements in Rd. If the addition result is beyond the Q31 + * number range (-2^31 <= Q31 <= 2^31-1), it is saturated to the range and the OV bit is set to 1. The 32-bit + * results after saturation are written to Rd. The 16-bit contents of Rs1 and Rs2 are treated as signed + * integers. + * + * **Operations**:\n + * ~~~ + * // KMADA + * res[x] = Rd.W[x] + (Rs1.W[x].H[1] * Rs2.W[x].H[1]) + (Rs1.W[x].H[0] * Rs2.W[x].H[0]); + * // KMAXDA + * res[x] = Rd.W[x] + (Rs1.W[x].H[1] * Rs2.W[x].H[0]) + (Rs1.W[x].H[0] * Rs2.W[x].H[1]); + * if (res[x] > (2^31)-1) { + * res[x] = (2^31)-1; + * OV = 1; + * } else if (res[x] < -2^31) { + * res[x] = -2^31; + * OV = 1; + * } + * Rd.W[x] = res[x]; + * for RV32: x=0 + * for RV64: x=1...0 + * ~~~ + * + * \param [in] t long type of value stored in t + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_KMAXDA(long t, unsigned long a, unsigned long b) +{ + __ASM volatile("kmaxda %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); + return t; +} +/* ===== Inline Function End for 3.39.2. KMAXDA ===== */ + +/* ===== Inline Function Start for 3.40.1. KMADS ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_32B_ADDSUB + * \brief KMADS (SIMD Saturating Signed Multiply Two Halfs & Subtract & Add) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * KMADS Rd, Rs1, Rs2 + * KMADRS Rd, Rs1, Rs2 + * KMAXDS Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do two signed 16-bit multiplications from 32-bit elements in two registers; and then + * perform a subtraction operation between the two 32-bit results. Then add the subtraction result to + * the corresponding 32-bit elements in a third register. The addition result may be saturated. + * * KMADS: rd.W[x] + (top*top - bottom*bottom) (per 32-bit element) + * * KMADRS: rd.W[x] + (bottom*bottom - top*top) (per 32-bit element) + * * KMAXDS: rd.W[x] + (top*bottom - bottom*top) (per 32-bit element) + * + * **Description**:\n + * For the `KMADS` instruction, it multiplies the bottom 16-bit content of 32-bit elements in Rs1 with + * the bottom 16-bit content of 32-bit elements in Rs2 and then subtracts the result from the result of + * multiplying the top 16-bit content of 32-bit elements in Rs1 with the top 16-bit content of 32-bit + * elements in Rs2. + * For the `KMADRS` instruction, it multiplies the top 16-bit content of 32-bit elements in Rs1 with the + * top 16-bit content of 32-bit elements in Rs2 and then subtracts the result from the result of + * multiplying the bottom 16-bit content of 32-bit elements in Rs1 with the bottom 16-bit content of 32- + * bit elements in Rs2. + * For the `KMAXDS` instruction, it multiplies the bottom 16-bit content of 32-bit elements in Rs1 with + * the top 16-bit content of 32-bit elements in Rs2 and then subtracts the result from the result of + * multiplying the top 16-bit content of 32-bit elements in Rs1 with the bottom 16-bit content of 32-bit + * elements in Rs2. + * The subtraction result is then added to the content of the corresponding 32-bit elements in Rd. If the + * addition result is beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), it is saturated to the range and + * the OV bit is set to 1. The 32-bit results after saturation are written to Rd. The 16-bit contents of Rs1 + * and Rs2 are treated as signed integers. + * + * **Operations**:\n + * ~~~ + * // KMADS + * res[x] = Rd.W[x] + (Rs1.W[x].H[1] * Rs2.W[x].H[1]) - (Rs1.W[x].H[0] * Rs2.W[x].H[0]); + * // KMADRS + * res[x] = Rd.W[x] + (Rs1.W[x].H[0] * Rs2.W[x].H[0]) - (Rs1.W[x].H[1] * Rs2.W[x].H[1]); + * // KMAXDS + * res[x] = Rd.W[x] + (Rs1.W[x].H[1] * Rs2.W[x].H[0]) - (Rs1.W[x].H[0] * Rs2.W[x].H[1]); + * if (res[x] > (2^31)-1) { + * res[x] = (2^31)-1; + * OV = 1; + * } else if (res[x] < -2^31) { + * res[x] = -2^31; + * OV = 1; + * } + * Rd.W[x] = res[x]; + * for RV32: x=0 + * for RV64: x=1...0 + * ~~~ + * + * \param [in] t long type of value stored in t + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_KMADS(long t, unsigned long a, unsigned long b) +{ + __ASM volatile("kmads %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); + return t; +} +/* ===== Inline Function End for 3.40.1. KMADS ===== */ + +/* ===== Inline Function Start for 3.40.2. KMADRS ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_32B_ADDSUB + * \brief KMADRS (SIMD Saturating Signed Multiply Two Halfs & Reverse Subtract & Add) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * KMADS Rd, Rs1, Rs2 + * KMADRS Rd, Rs1, Rs2 + * KMAXDS Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do two signed 16-bit multiplications from 32-bit elements in two registers; and then + * perform a subtraction operation between the two 32-bit results. Then add the subtraction result to + * the corresponding 32-bit elements in a third register. The addition result may be saturated. + * * KMADS: rd.W[x] + (top*top - bottom*bottom) (per 32-bit element) + * * KMADRS: rd.W[x] + (bottom*bottom - top*top) (per 32-bit element) + * * KMAXDS: rd.W[x] + (top*bottom - bottom*top) (per 32-bit element) + * + * **Description**:\n + * For the `KMADS` instruction, it multiplies the bottom 16-bit content of 32-bit elements in Rs1 with + * the bottom 16-bit content of 32-bit elements in Rs2 and then subtracts the result from the result of + * multiplying the top 16-bit content of 32-bit elements in Rs1 with the top 16-bit content of 32-bit + * elements in Rs2. + * For the `KMADRS` instruction, it multiplies the top 16-bit content of 32-bit elements in Rs1 with the + * top 16-bit content of 32-bit elements in Rs2 and then subtracts the result from the result of + * multiplying the bottom 16-bit content of 32-bit elements in Rs1 with the bottom 16-bit content of 32- + * bit elements in Rs2. + * For the `KMAXDS` instruction, it multiplies the bottom 16-bit content of 32-bit elements in Rs1 with + * the top 16-bit content of 32-bit elements in Rs2 and then subtracts the result from the result of + * multiplying the top 16-bit content of 32-bit elements in Rs1 with the bottom 16-bit content of 32-bit + * elements in Rs2. + * The subtraction result is then added to the content of the corresponding 32-bit elements in Rd. If the + * addition result is beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), it is saturated to the range and + * the OV bit is set to 1. The 32-bit results after saturation are written to Rd. The 16-bit contents of Rs1 + * and Rs2 are treated as signed integers. + * + * **Operations**:\n + * ~~~ + * // KMADS + * res[x] = Rd.W[x] + (Rs1.W[x].H[1] * Rs2.W[x].H[1]) - (Rs1.W[x].H[0] * Rs2.W[x].H[0]); + * // KMADRS + * res[x] = Rd.W[x] + (Rs1.W[x].H[0] * Rs2.W[x].H[0]) - (Rs1.W[x].H[1] * Rs2.W[x].H[1]); + * // KMAXDS + * res[x] = Rd.W[x] + (Rs1.W[x].H[1] * Rs2.W[x].H[0]) - (Rs1.W[x].H[0] * Rs2.W[x].H[1]); + * if (res[x] > (2^31)-1) { + * res[x] = (2^31)-1; + * OV = 1; + * } else if (res[x] < -2^31) { + * res[x] = -2^31; + * OV = 1; + * } + * Rd.W[x] = res[x]; + * for RV32: x=0 + * for RV64: x=1...0 + * ~~~ + * + * \param [in] t long type of value stored in t + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_KMADRS(long t, unsigned long a, unsigned long b) +{ + __ASM volatile("kmadrs %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); + return t; +} +/* ===== Inline Function End for 3.40.2. KMADRS ===== */ + +/* ===== Inline Function Start for 3.40.3. KMAXDS ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_32B_ADDSUB + * \brief KMAXDS (SIMD Saturating Signed Crossed Multiply Two Halfs & Subtract & Add) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * KMADS Rd, Rs1, Rs2 + * KMADRS Rd, Rs1, Rs2 + * KMAXDS Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do two signed 16-bit multiplications from 32-bit elements in two registers; and then + * perform a subtraction operation between the two 32-bit results. Then add the subtraction result to + * the corresponding 32-bit elements in a third register. The addition result may be saturated. + * * KMADS: rd.W[x] + (top*top - bottom*bottom) (per 32-bit element) + * * KMADRS: rd.W[x] + (bottom*bottom - top*top) (per 32-bit element) + * * KMAXDS: rd.W[x] + (top*bottom - bottom*top) (per 32-bit element) + * + * **Description**:\n + * For the `KMADS` instruction, it multiplies the bottom 16-bit content of 32-bit elements in Rs1 with + * the bottom 16-bit content of 32-bit elements in Rs2 and then subtracts the result from the result of + * multiplying the top 16-bit content of 32-bit elements in Rs1 with the top 16-bit content of 32-bit + * elements in Rs2. + * For the `KMADRS` instruction, it multiplies the top 16-bit content of 32-bit elements in Rs1 with the + * top 16-bit content of 32-bit elements in Rs2 and then subtracts the result from the result of + * multiplying the bottom 16-bit content of 32-bit elements in Rs1 with the bottom 16-bit content of 32- + * bit elements in Rs2. + * For the `KMAXDS` instruction, it multiplies the bottom 16-bit content of 32-bit elements in Rs1 with + * the top 16-bit content of 32-bit elements in Rs2 and then subtracts the result from the result of + * multiplying the top 16-bit content of 32-bit elements in Rs1 with the bottom 16-bit content of 32-bit + * elements in Rs2. + * The subtraction result is then added to the content of the corresponding 32-bit elements in Rd. If the + * addition result is beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), it is saturated to the range and + * the OV bit is set to 1. The 32-bit results after saturation are written to Rd. The 16-bit contents of Rs1 + * and Rs2 are treated as signed integers. + * + * **Operations**:\n + * ~~~ + * // KMADS + * res[x] = Rd.W[x] + (Rs1.W[x].H[1] * Rs2.W[x].H[1]) - (Rs1.W[x].H[0] * Rs2.W[x].H[0]); + * // KMADRS + * res[x] = Rd.W[x] + (Rs1.W[x].H[0] * Rs2.W[x].H[0]) - (Rs1.W[x].H[1] * Rs2.W[x].H[1]); + * // KMAXDS + * res[x] = Rd.W[x] + (Rs1.W[x].H[1] * Rs2.W[x].H[0]) - (Rs1.W[x].H[0] * Rs2.W[x].H[1]); + * if (res[x] > (2^31)-1) { + * res[x] = (2^31)-1; + * OV = 1; + * } else if (res[x] < -2^31) { + * res[x] = -2^31; + * OV = 1; + * } + * Rd.W[x] = res[x]; + * for RV32: x=0 + * for RV64: x=1...0 + * ~~~ + * + * \param [in] t long type of value stored in t + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_KMAXDS(long t, unsigned long a, unsigned long b) +{ + __ASM volatile("kmaxds %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); + return t; +} +/* ===== Inline Function End for 3.40.3. KMAXDS ===== */ + +/* ===== Inline Function Start for 3.41. KMAR64 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_32B_MULT_64B_ADDSUB + * \brief KMAR64 (Signed Multiply and Saturating Add to 64-Bit Data) + * \details + * **Type**: DSP (64-bit Profile) + * + * **Syntax**:\n + * ~~~ + * KMAR64 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Multiply the 32-bit signed elements in two registers and add the 64-bit multiplication + * results to the 64-bit signed data of a pair of registers (RV32) or a register (RV64). The result is + * saturated to the Q63 range and written back to the pair of registers (RV32) or the register (RV64). + * + * **RV32 Description**:\n + * This instruction multiplies the 32-bit signed data of Rs1 with that of Rs2. It adds + * the 64-bit multiplication result to the 64-bit signed data of an even/odd pair of registers specified by + * Rd(4,1) with unlimited precision. If the 64-bit addition result is beyond the Q63 number range (-2^63 <= + * Q63 <= 2^63-1), it is saturated to the range and the OV bit is set to 1. The saturated result is written back + * to the even/odd pair of registers specified by Rd(4,1). + * Rx(4,1), i.e., value d, determines the even/odd pair group of two registers. Specifically, the register + * pair includes register 2d and 2d+1. + * The odd `2d+1` register of the pair contains the high 32-bit of the result and the even `2d` register + * of the pair contains the low 32-bit of the result. + * + * **RV64 Description**:\n + * This instruction multiplies the 32-bit signed elements of Rs1 with that of Rs2. It + * adds the 64-bit multiplication results to the 64-bit signed data of Rd with unlimited precision. If the + * 64-bit addition result is beyond the Q63 number range (-2^63 <= Q63 <= 2^63-1), it is saturated to the range + * and the OV bit is set to 1. The saturated result is written back to Rd. + * + * **Operations**:\n + * ~~~ + * RV32: + * t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1); + * result = R[t_H].R[t_L] + (Rs1 * Rs2); + * if (result > (2^63)-1) { + * result = (2^63)-1; OV = 1; + * } else if (result < -2^63) { + * result = -2^63; OV = 1; + * } + * R[t_H].R[t_L] = result; + * RV64: + * // `result` has unlimited precision + * result = Rd + (Rs1.W[0] * Rs2.W[0]) + (Rs1.W[1] * Rs2.W[1]); + * if (result > (2^63)-1) { + * result = (2^63)-1; OV = 1; + * } else if (result < -2^63) { + * result = -2^63; OV = 1; + * } + * Rd = result; + * ~~~ + * + * \param [in] t long long type of value stored in t + * \param [in] a long type of value stored in a + * \param [in] b long type of value stored in b + * \return value stored in long long type + */ +__STATIC_FORCEINLINE long long __RV_KMAR64(long long t, long a, long b) +{ + __ASM volatile("kmar64 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); + return t; +} +/* ===== Inline Function End for 3.41. KMAR64 ===== */ + +/* ===== Inline Function Start for 3.42.1. KMDA ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_32B_ADDSUB + * \brief KMDA (SIMD Signed Multiply Two Halfs and Add) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * KMDA Rd, Rs1, Rs2 + * KMXDA Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do two signed 16-bit multiplications from the 32-bit elements of two registers; and then + * adds the two 32-bit results together. The addition result may be saturated. + * * KMDA: top*top + bottom*bottom (per 32-bit element) + * * KMXDA: top*bottom + bottom*top (per 32-bit element) + * + * **Description**:\n + * For the `KMDA` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 + * with the bottom 16-bit content of the 32-bit elements of Rs2 and then adds the result to the result of + * multiplying the top 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the 32- + * bit elements of Rs2. + * For the `KMXDA` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 + * with the top 16-bit content of the 32-bit elements of Rs2 and then adds the result to the result of + * multiplying the top 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit content of the + * 32-bit elements of Rs2. + * The addition result is checked for saturation. If saturation happens, the result is saturated to 2^31-1. + * The final results are written to Rd. The 16-bit contents are treated as signed integers. + * + * **Operations**:\n + * ~~~ + * if Rs1.W[x] != 0x80008000) or (Rs2.W[x] != 0x80008000 { // KMDA Rd.W[x] = Rs1.W[x].H[1] * + * Rs2.W[x].H[1]) + (Rs1.W[x].H[0] * Rs2.W[x].H[0]; // KMXDA Rd.W[x] = Rs1.W[x].H[1] * Rs2.W[x].H[0]) + * + (Rs1.W[x].H[0] * Rs2.W[x].H[1]; } else { Rd.W[x] = 0x7fffffff; OV = 1; } for RV32: x=0 for RV64: + * x=1...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_KMDA(unsigned long a, unsigned long b) +{ + register long result; + __ASM volatile("kmda %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.42.1. KMDA ===== */ + +/* ===== Inline Function Start for 3.42.2. KMXDA ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_32B_ADDSUB + * \brief KMXDA (SIMD Signed Crossed Multiply Two Halfs and Add) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * KMDA Rd, Rs1, Rs2 + * KMXDA Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do two signed 16-bit multiplications from the 32-bit elements of two registers; and then + * adds the two 32-bit results together. The addition result may be saturated. + * * KMDA: top*top + bottom*bottom (per 32-bit element) + * * KMXDA: top*bottom + bottom*top (per 32-bit element) + * + * **Description**:\n + * For the `KMDA` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 + * with the bottom 16-bit content of the 32-bit elements of Rs2 and then adds the result to the result of + * multiplying the top 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the 32- + * bit elements of Rs2. + * For the `KMXDA` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 + * with the top 16-bit content of the 32-bit elements of Rs2 and then adds the result to the result of + * multiplying the top 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit content of the + * 32-bit elements of Rs2. + * The addition result is checked for saturation. If saturation happens, the result is saturated to 2^31-1. + * The final results are written to Rd. The 16-bit contents are treated as signed integers. + * + * **Operations**:\n + * ~~~ + * if Rs1.W[x] != 0x80008000) or (Rs2.W[x] != 0x80008000 { // KMDA Rd.W[x] = Rs1.W[x].H[1] * + * Rs2.W[x].H[1]) + (Rs1.W[x].H[0] * Rs2.W[x].H[0]; // KMXDA Rd.W[x] = Rs1.W[x].H[1] * Rs2.W[x].H[0]) + * + (Rs1.W[x].H[0] * Rs2.W[x].H[1]; } else { Rd.W[x] = 0x7fffffff; OV = 1; } for RV32: x=0 for RV64: + * x=1...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_KMXDA(unsigned long a, unsigned long b) +{ + register long result; + __ASM volatile("kmxda %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.42.2. KMXDA ===== */ + +/* ===== Inline Function Start for 3.43.1. KMMAC ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X32_MAC + * \brief KMMAC (SIMD Saturating MSW Signed Multiply Word and Add) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * KMMAC Rd, Rs1, Rs2 + * KMMAC.u Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Multiply the signed 32-bit integer elements of two registers and add the most significant + * 32-bit results with the signed 32-bit integer elements of a third register. The addition results are + * saturated first and then written back to the third register. The `.u` form performs an additional + * rounding up operation on the multiplication results before adding the most significant 32-bit part + * of the results. + * + * **Description**:\n + * This instruction multiplies the signed 32-bit elements of Rs1 with the signed 32-bit elements of Rs2 + * and adds the most significant 32-bit multiplication results with the signed 32-bit elements of Rd. If + * the addition result is beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), it is saturated to the range + * and the OV bit is set to 1. The results after saturation are written to Rd. The `.u` form of the + * instruction additionally rounds up the most significant 32-bit of the 64-bit multiplication results by + * adding a 1 to bit 31 of the results. + * + * **Operations**:\n + * ~~~ + * Mres[x][63:0] = Rs1.W[x] * Rs2.W[x]; + * if (`.u` form) { + * Round[x][32:0] = Mres[x][63:31] + 1; + * res[x] = Rd.W[x] + Round[x][32:1]; + * } else { + * res[x] = Rd.W[x] + Mres[x][63:32]; + * } + * if (res[x] > (2^31)-1) { + * res[x] = (2^31)-1; + * OV = 1; + * } else if (res[x] < -2^31) { + * res[x] = -2^31; + * OV = 1; + * } + * Rd.W[x] = res[x]; + * for RV32: x=0 + * for RV64: x=1...0 + * ~~~ + * + * \param [in] t long type of value stored in t + * \param [in] a long type of value stored in a + * \param [in] b long type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_KMMAC(long t, long a, long b) +{ + __ASM volatile("kmmac %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); + return t; +} +/* ===== Inline Function End for 3.43.1. KMMAC ===== */ + +/* ===== Inline Function Start for 3.43.2. KMMAC.u ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X32_MAC + * \brief KMMAC.u (SIMD Saturating MSW Signed Multiply Word and Add with Rounding) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * KMMAC Rd, Rs1, Rs2 + * KMMAC.u Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Multiply the signed 32-bit integer elements of two registers and add the most significant + * 32-bit results with the signed 32-bit integer elements of a third register. The addition results are + * saturated first and then written back to the third register. The `.u` form performs an additional + * rounding up operation on the multiplication results before adding the most significant 32-bit part + * of the results. + * + * **Description**:\n + * This instruction multiplies the signed 32-bit elements of Rs1 with the signed 32-bit elements of Rs2 + * and adds the most significant 32-bit multiplication results with the signed 32-bit elements of Rd. If + * the addition result is beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), it is saturated to the range + * and the OV bit is set to 1. The results after saturation are written to Rd. The `.u` form of the + * instruction additionally rounds up the most significant 32-bit of the 64-bit multiplication results by + * adding a 1 to bit 31 of the results. + * + * **Operations**:\n + * ~~~ + * Mres[x][63:0] = Rs1.W[x] * Rs2.W[x]; + * if (`.u` form) { + * Round[x][32:0] = Mres[x][63:31] + 1; + * res[x] = Rd.W[x] + Round[x][32:1]; + * } else { + * res[x] = Rd.W[x] + Mres[x][63:32]; + * } + * if (res[x] > (2^31)-1) { + * res[x] = (2^31)-1; + * OV = 1; + * } else if (res[x] < -2^31) { + * res[x] = -2^31; + * OV = 1; + * } + * Rd.W[x] = res[x]; + * for RV32: x=0 + * for RV64: x=1...0 + * ~~~ + * + * \param [in] t long type of value stored in t + * \param [in] a long type of value stored in a + * \param [in] b long type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_KMMAC_U(long t, long a, long b) +{ + __ASM volatile("kmmac.u %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); + return t; +} +/* ===== Inline Function End for 3.43.2. KMMAC.u ===== */ + +/* ===== Inline Function Start for 3.44.1. KMMAWB ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X16_MAC + * \brief KMMAWB (SIMD Saturating MSW Signed Multiply Word and Bottom Half and Add) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * KMMAWB Rd, Rs1, Rs2 + * KMMAWB.u Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Multiply the signed 32-bit integer elements of one register and the bottom 16-bit of the + * corresponding 32-bit elements of another register and add the most significant 32-bit results with + * the corresponding signed 32-bit elements of a third register. The addition result is written to the + * corresponding 32-bit elements of the third register. The `.u` form rounds up the multiplication + * results from the most significant discarded bit before the addition operations. + * + * **Description**:\n + * This instruction multiplies the signed 32-bit elements of Rs1 with the signed bottom 16-bit content + * of the corresponding 32-bit elements of Rs2 and adds the most significant 32-bit multiplication + * results with the corresponding signed 32-bit elements of Rd. If the addition result is beyond the Q31 + * number range (-2^31 <= Q31 <= 2^31-1), it is saturated to the range and the OV bit is set to 1. The results + * after saturation are written to the corresponding 32-bit elements of Rd. The `.u` form of the + * instruction rounds up the most significant 32-bit of the 48-bit multiplication results by adding a 1 to + * bit 15 of the result before the addition operations. + * + * **Operations**:\n + * ~~~ + * Mres[x][47:0] = Rs1.W[x] * Rs2.W[x].H[0]; + * if (`.u` form) { + * Round[x][32:0] = Mres[x][47:15] + 1; + * res[x] = Rd.W[x] + Round[x][32:1]; + * } else { + * res[x] = Rd.W[x] + Mres[x][47:16]; + * } + * if (res[x] > (2^31)-1) { + * res[x] = (2^31)-1; + * OV = 1; + * } else if (res[x] < -2^31) { + * res[x] = -2^31; + * OV = 1; + * } + * Rd.W[x] = res[x]; + * for RV32: x=0 + * for RV64: x=1...0 + * ~~~ + * + * \param [in] t long type of value stored in t + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_KMMAWB(long t, unsigned long a, unsigned long b) +{ + __ASM volatile("kmmawb %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); + return t; +} +/* ===== Inline Function End for 3.44.1. KMMAWB ===== */ + +/* ===== Inline Function Start for 3.44.2. KMMAWB.u ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X16_MAC + * \brief KMMAWB.u (SIMD Saturating MSW Signed Multiply Word and Bottom Half and Add with Rounding) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * KMMAWB Rd, Rs1, Rs2 + * KMMAWB.u Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Multiply the signed 32-bit integer elements of one register and the bottom 16-bit of the + * corresponding 32-bit elements of another register and add the most significant 32-bit results with + * the corresponding signed 32-bit elements of a third register. The addition result is written to the + * corresponding 32-bit elements of the third register. The `.u` form rounds up the multiplication + * results from the most significant discarded bit before the addition operations. + * + * **Description**:\n + * This instruction multiplies the signed 32-bit elements of Rs1 with the signed bottom 16-bit content + * of the corresponding 32-bit elements of Rs2 and adds the most significant 32-bit multiplication + * results with the corresponding signed 32-bit elements of Rd. If the addition result is beyond the Q31 + * number range (-2^31 <= Q31 <= 2^31-1), it is saturated to the range and the OV bit is set to 1. The results + * after saturation are written to the corresponding 32-bit elements of Rd. The `.u` form of the + * instruction rounds up the most significant 32-bit of the 48-bit multiplication results by adding a 1 to + * bit 15 of the result before the addition operations. + * + * **Operations**:\n + * ~~~ + * Mres[x][47:0] = Rs1.W[x] * Rs2.W[x].H[0]; + * if (`.u` form) { + * Round[x][32:0] = Mres[x][47:15] + 1; + * res[x] = Rd.W[x] + Round[x][32:1]; + * } else { + * res[x] = Rd.W[x] + Mres[x][47:16]; + * } + * if (res[x] > (2^31)-1) { + * res[x] = (2^31)-1; + * OV = 1; + * } else if (res[x] < -2^31) { + * res[x] = -2^31; + * OV = 1; + * } + * Rd.W[x] = res[x]; + * for RV32: x=0 + * for RV64: x=1...0 + * ~~~ + * + * \param [in] t long type of value stored in t + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_KMMAWB_U(long t, unsigned long a, unsigned long b) +{ + __ASM volatile("kmmawb.u %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); + return t; +} +/* ===== Inline Function End for 3.44.2. KMMAWB.u ===== */ + +/* ===== Inline Function Start for 3.45.1. KMMAWB2 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X16_MAC + * \brief KMMAWB2 (SIMD Saturating MSW Signed Multiply Word and Bottom Half & 2 and Add) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * KMMAWB2 Rd, Rs1, Rs2 + * KMMAWB2.u Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Multiply the signed 32-bit elements of one register and the bottom 16-bit of the + * corresponding 32-bit elements of another register, double the multiplication results and add the + * saturated most significant 32-bit results with the corresponding signed 32-bit elements of a third + * register. The saturated addition result is written to the corresponding 32-bit elements of the third + * register. The `.u` form rounds up the multiplication results from the most significant discarded bit + * before the addition operations. + * + * **Description**:\n + * This instruction multiplies the signed 32-bit Q31 elements of Rs1 with the signed bottom 16-bit Q15 + * content of the corresponding 32-bit elements of Rs2, doubles the Q46 results to Q47 numbers and + * adds the saturated most significant 32-bit Q31 multiplication results with the corresponding signed + * 32-bit elements of Rd. If the addition result is beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), it is + * saturated to the range and the OV bit is set to 1. The results after saturation are written to the + * corresponding 32-bit elements of Rd. The `.u` form of the instruction rounds up the most significant + * 32-bit of the 48-bit Q47 multiplication results by adding a 1 to bit 15 (i.e., bit 14 before doubling) of + * the result before the addition operations. + * + * **Operations**:\n + * ~~~ + * if ((Rs1.W[x] == 0x80000000) & (Rs2.W[x].H[0] == 0x8000)) { + * addop.W[x] = 0x7fffffff; + * OV = 1; + * } else { + * Mres[x][47:0] = Rs1.W[x] s* Rs2.W[x].H[0]; + * if (`.u` form) { + * Mres[x][47:14] = Mres[x][47:14] + 1; + * } + * addop.W[x] = Mres[x][46:15]; // doubling + * } + * res[x] = Rd.W[x] + addop.W[x]; + * if (res[x] > (2^31)-1) { + * res[x] = (2^31)-1; + * OV = 1; + * } else if (res[x] < -2^31) { + * res[x] = -2^31; + * OV = 1; + * } + * Rd.W[x] = res[x]; + * for RV32: x=0 + * for RV64: x=1...0 + * ~~~ + * + * \param [in] t long type of value stored in t + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_KMMAWB2(long t, unsigned long a, unsigned long b) +{ + __ASM volatile("kmmawb2 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); + return t; +} +/* ===== Inline Function End for 3.45.1. KMMAWB2 ===== */ + +/* ===== Inline Function Start for 3.45.2. KMMAWB2.u ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X16_MAC + * \brief KMMAWB2.u (SIMD Saturating MSW Signed Multiply Word and Bottom Half & 2 and Add with Rounding) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * KMMAWB2 Rd, Rs1, Rs2 + * KMMAWB2.u Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Multiply the signed 32-bit elements of one register and the bottom 16-bit of the + * corresponding 32-bit elements of another register, double the multiplication results and add the + * saturated most significant 32-bit results with the corresponding signed 32-bit elements of a third + * register. The saturated addition result is written to the corresponding 32-bit elements of the third + * register. The `.u` form rounds up the multiplication results from the most significant discarded bit + * before the addition operations. + * + * **Description**:\n + * This instruction multiplies the signed 32-bit Q31 elements of Rs1 with the signed bottom 16-bit Q15 + * content of the corresponding 32-bit elements of Rs2, doubles the Q46 results to Q47 numbers and + * adds the saturated most significant 32-bit Q31 multiplication results with the corresponding signed + * 32-bit elements of Rd. If the addition result is beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), it is + * saturated to the range and the OV bit is set to 1. The results after saturation are written to the + * corresponding 32-bit elements of Rd. The `.u` form of the instruction rounds up the most significant + * 32-bit of the 48-bit Q47 multiplication results by adding a 1 to bit 15 (i.e., bit 14 before doubling) of + * the result before the addition operations. + * + * **Operations**:\n + * ~~~ + * if ((Rs1.W[x] == 0x80000000) & (Rs2.W[x].H[0] == 0x8000)) { + * addop.W[x] = 0x7fffffff; + * OV = 1; + * } else { + * Mres[x][47:0] = Rs1.W[x] s* Rs2.W[x].H[0]; + * if (`.u` form) { + * Mres[x][47:14] = Mres[x][47:14] + 1; + * } + * addop.W[x] = Mres[x][46:15]; // doubling + * } + * res[x] = Rd.W[x] + addop.W[x]; + * if (res[x] > (2^31)-1) { + * res[x] = (2^31)-1; + * OV = 1; + * } else if (res[x] < -2^31) { + * res[x] = -2^31; + * OV = 1; + * } + * Rd.W[x] = res[x]; + * for RV32: x=0 + * for RV64: x=1...0 + * ~~~ + * + * \param [in] t long type of value stored in t + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_KMMAWB2_U(long t, unsigned long a, unsigned long b) +{ + __ASM volatile("kmmawb2.u %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); + return t; +} +/* ===== Inline Function End for 3.45.2. KMMAWB2.u ===== */ + +/* ===== Inline Function Start for 3.46.1. KMMAWT ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X16_MAC + * \brief KMMAWT (SIMD Saturating MSW Signed Multiply Word and Top Half and Add) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * KMMAWT Rd, Rs1, Rs2 + * KMMAWT.u Rd Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Multiply the signed 32-bit integer elements of one register and the signed top 16-bit of the + * corresponding 32-bit elements of another register and add the most significant 32-bit results with + * the corresponding signed 32-bit elements of a third register. The addition results are written to the + * corresponding 32-bit elements of the third register. The `.u` form rounds up the multiplication + * results from the most significant discarded bit before the addition operations. + * + * **Description**:\n + * This instruction multiplies the signed 32-bit elements of Rs1 with the signed top 16-bit of the + * corresponding 32-bit elements of Rs2 and adds the most significant 32-bit multiplication results + * with the corresponding signed 32-bit elements of Rd. If the addition result is beyond the Q31 + * number range (-2^31 <= Q31 <= 2^31-1), it is saturated to the range and the OV bit is set to 1. The results + * after saturation are written to the corresponding 32-bit elements of Rd. The `.u` form of the + * instruction rounds up the most significant 32-bit of the 48-bit multiplication results by adding a 1 to + * bit 15 of the result before the addition operations. + * + * **Operations**:\n + * ~~~ + * Mres[x][47:0] = Rs1.W[x] * Rs2.W[x].H[1]; + * if (`.u` form) { + * Round[x][32:0] = Mres[x][47:15] + 1; + * res[x] = Rd.W[x] + Round[x][32:1]; + * } else { + * res[x] = Rd.W[x] + Mres[x][47:16]; + * } + * if (res[x] > (2^31)-1) { + * res[x] = (2^31)-1; + * OV = 1; + * } else if (res[x] < -2^31) { + * res[x] = -2^31; + * OV = 1; + * } + * Rd.W[x] = res[x]; + * for RV32: x=0 + * for RV64: x=1...0 + * ~~~ + * + * \param [in] t long type of value stored in t + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_KMMAWT(long t, unsigned long a, unsigned long b) +{ + __ASM volatile("kmmawt %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); + return t; +} +/* ===== Inline Function End for 3.46.1. KMMAWT ===== */ + +/* ===== Inline Function Start for 3.46.2. KMMAWT.u ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X16_MAC + * \brief KMMAWT.u (SIMD Saturating MSW Signed Multiply Word and Top Half and Add with Rounding) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * KMMAWT Rd, Rs1, Rs2 + * KMMAWT.u Rd Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Multiply the signed 32-bit integer elements of one register and the signed top 16-bit of the + * corresponding 32-bit elements of another register and add the most significant 32-bit results with + * the corresponding signed 32-bit elements of a third register. The addition results are written to the + * corresponding 32-bit elements of the third register. The `.u` form rounds up the multiplication + * results from the most significant discarded bit before the addition operations. + * + * **Description**:\n + * This instruction multiplies the signed 32-bit elements of Rs1 with the signed top 16-bit of the + * corresponding 32-bit elements of Rs2 and adds the most significant 32-bit multiplication results + * with the corresponding signed 32-bit elements of Rd. If the addition result is beyond the Q31 + * number range (-2^31 <= Q31 <= 2^31-1), it is saturated to the range and the OV bit is set to 1. The results + * after saturation are written to the corresponding 32-bit elements of Rd. The `.u` form of the + * instruction rounds up the most significant 32-bit of the 48-bit multiplication results by adding a 1 to + * bit 15 of the result before the addition operations. + * + * **Operations**:\n + * ~~~ + * Mres[x][47:0] = Rs1.W[x] * Rs2.W[x].H[1]; + * if (`.u` form) { + * Round[x][32:0] = Mres[x][47:15] + 1; + * res[x] = Rd.W[x] + Round[x][32:1]; + * } else { + * res[x] = Rd.W[x] + Mres[x][47:16]; + * } + * if (res[x] > (2^31)-1) { + * res[x] = (2^31)-1; + * OV = 1; + * } else if (res[x] < -2^31) { + * res[x] = -2^31; + * OV = 1; + * } + * Rd.W[x] = res[x]; + * for RV32: x=0 + * for RV64: x=1...0 + * ~~~ + * + * \param [in] t long type of value stored in t + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_KMMAWT_U(long t, unsigned long a, unsigned long b) +{ + __ASM volatile("kmmawt.u %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); + return t; +} +/* ===== Inline Function End for 3.46.2. KMMAWT.u ===== */ + +/* ===== Inline Function Start for 3.47.1. KMMAWT2 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X16_MAC + * \brief KMMAWT2 (SIMD Saturating MSW Signed Multiply Word and Top Half & 2 and Add) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * KMMAWT2 Rd, Rs1, Rs2 + * KMMAWT2.u Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Multiply the signed 32-bit elements of one register and the top 16-bit of the + * corresponding 32-bit elements of another register, double the multiplication results and add the + * saturated most significant 32-bit results with the corresponding signed 32-bit elements of a third + * register. The saturated addition result is written to the corresponding 32-bit elements of the third + * register. The `.u` form rounds up the multiplication results from the most significant discarded bit + * before the addition operations. + * + * **Description**:\n + * This instruction multiplies the signed 32-bit Q31 elements of Rs1 with the signed top 16-bit Q15 + * content of the corresponding 32-bit elements of Rs2, doubles the Q46 results to Q47 numbers and + * adds the saturated most significant 32-bit Q31 multiplication results with the corresponding signed + * 32-bit elements of Rd. If the addition result is beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), it is + * saturated to the range and the OV bit is set to 1. The results after saturation are written to the + * corresponding 32-bit elements of Rd. The `.u` form of the instruction rounds up the most significant + * 32-bit of the 48-bit Q47 multiplication results by adding a 1 to bit 15 (i.e., bit 14 before doubling) of + * the result before the addition operations. + * + * **Operations**:\n + * ~~~ + * if ((Rs1.W[x] == 0x80000000) & (Rs2.W[x].H[1] == 0x8000)) { + * addop.W[x] = 0x7fffffff; + * OV = 1; + * } else { + * Mres[x][47:0] = Rs1.W[x] s* Rs2.W[x].H[1]; + * if (`.u` form) { + * Mres[x][47:14] = Mres[x][47:14] + 1; + * } + * addop.W[x] = Mres[x][46:15]; // doubling + * } + * res[x] = Rd.W[x] + addop.W[x]; + * if (res[x] > (2^31)-1) { + * res[x] = (2^31)-1; + * OV = 1; + * } else if (res[x] < -2^31) { + * res[x] = -2^31; + * OV = 1; + * } + * Rd.W[x] = res[x]; + * for RV32: x=0 + * for RV64: x=1...0 + * ~~~ + * + * \param [in] t long type of value stored in t + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_KMMAWT2(long t, unsigned long a, unsigned long b) +{ + __ASM volatile("kmmawt2 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); + return t; +} +/* ===== Inline Function End for 3.47.1. KMMAWT2 ===== */ + +/* ===== Inline Function Start for 3.47.2. KMMAWT2.u ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X16_MAC + * \brief KMMAWT2.u (SIMD Saturating MSW Signed Multiply Word and Top Half & 2 and Add with Rounding) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * KMMAWT2 Rd, Rs1, Rs2 + * KMMAWT2.u Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Multiply the signed 32-bit elements of one register and the top 16-bit of the + * corresponding 32-bit elements of another register, double the multiplication results and add the + * saturated most significant 32-bit results with the corresponding signed 32-bit elements of a third + * register. The saturated addition result is written to the corresponding 32-bit elements of the third + * register. The `.u` form rounds up the multiplication results from the most significant discarded bit + * before the addition operations. + * + * **Description**:\n + * This instruction multiplies the signed 32-bit Q31 elements of Rs1 with the signed top 16-bit Q15 + * content of the corresponding 32-bit elements of Rs2, doubles the Q46 results to Q47 numbers and + * adds the saturated most significant 32-bit Q31 multiplication results with the corresponding signed + * 32-bit elements of Rd. If the addition result is beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), it is + * saturated to the range and the OV bit is set to 1. The results after saturation are written to the + * corresponding 32-bit elements of Rd. The `.u` form of the instruction rounds up the most significant + * 32-bit of the 48-bit Q47 multiplication results by adding a 1 to bit 15 (i.e., bit 14 before doubling) of + * the result before the addition operations. + * + * **Operations**:\n + * ~~~ + * if ((Rs1.W[x] == 0x80000000) & (Rs2.W[x].H[1] == 0x8000)) { + * addop.W[x] = 0x7fffffff; + * OV = 1; + * } else { + * Mres[x][47:0] = Rs1.W[x] s* Rs2.W[x].H[1]; + * if (`.u` form) { + * Mres[x][47:14] = Mres[x][47:14] + 1; + * } + * addop.W[x] = Mres[x][46:15]; // doubling + * } + * res[x] = Rd.W[x] + addop.W[x]; + * if (res[x] > (2^31)-1) { + * res[x] = (2^31)-1; + * OV = 1; + * } else if (res[x] < -2^31) { + * res[x] = -2^31; + * OV = 1; + * } + * Rd.W[x] = res[x]; + * for RV32: x=0 + * for RV64: x=1...0 + * ~~~ + * + * \param [in] t long type of value stored in t + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_KMMAWT2_U(long t, unsigned long a, unsigned long b) +{ + __ASM volatile("kmmawt2.u %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); + return t; +} +/* ===== Inline Function End for 3.47.2. KMMAWT2.u ===== */ + +/* ===== Inline Function Start for 3.48.1. KMMSB ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X32_MAC + * \brief KMMSB (SIMD Saturating MSW Signed Multiply Word and Subtract) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * KMMSB Rd, Rs1, Rs2 + * KMMSB.u Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Multiply the signed 32-bit integer elements of two registers and subtract the most + * significant 32-bit results from the signed 32-bit elements of a third register. The subtraction results + * are written to the third register. The `.u` form performs an additional rounding up operation on + * the multiplication results before subtracting the most significant 32-bit part of the results. + * + * **Description**:\n + * This instruction multiplies the signed 32-bit elements of Rs1 with the signed 32-bit elements of Rs2 + * and subtracts the most significant 32-bit multiplication results from the signed 32-bit elements of + * Rd. If the subtraction result is beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), it is saturated to the + * range and the OV bit is set to 1. The results after saturation are written to Rd. The `.u` form of the + * instruction additionally rounds up the most significant 32-bit of the 64-bit multiplication results by + * adding a 1 to bit 31 of the results. + * + * **Operations**:\n + * ~~~ + * Mres[x][63:0] = Rs1.W[x] * Rs2.W[x]; + * if (`.u` form) { + * Round[x][32:0] = Mres[x][63:31] + 1; + * res[x] = Rd.W[x] - Round[x][32:1]; + * } else { + * res[x] = Rd.W[x] - Mres[x][63:32]; + * } + * if (res[x] > (2^31)-1) { + * res[x] = (2^31)-1; + * OV = 1; + * } else if (res[x] < -2^31) { + * res[x] = -2^31; + * OV = 1; + * } + * Rd.W[x] = res[x]; + * for RV32: x=0 + * for RV64: x=1...0 + * ~~~ + * + * \param [in] t long type of value stored in t + * \param [in] a long type of value stored in a + * \param [in] b long type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_KMMSB(long t, long a, long b) +{ + __ASM volatile("kmmsb %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); + return t; +} +/* ===== Inline Function End for 3.48.1. KMMSB ===== */ + +/* ===== Inline Function Start for 3.48.2. KMMSB.u ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X32_MAC + * \brief KMMSB.u (SIMD Saturating MSW Signed Multiply Word and Subtraction with Rounding) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * KMMSB Rd, Rs1, Rs2 + * KMMSB.u Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Multiply the signed 32-bit integer elements of two registers and subtract the most + * significant 32-bit results from the signed 32-bit elements of a third register. The subtraction results + * are written to the third register. The `.u` form performs an additional rounding up operation on + * the multiplication results before subtracting the most significant 32-bit part of the results. + * + * **Description**:\n + * This instruction multiplies the signed 32-bit elements of Rs1 with the signed 32-bit elements of Rs2 + * and subtracts the most significant 32-bit multiplication results from the signed 32-bit elements of + * Rd. If the subtraction result is beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), it is saturated to the + * range and the OV bit is set to 1. The results after saturation are written to Rd. The `.u` form of the + * instruction additionally rounds up the most significant 32-bit of the 64-bit multiplication results by + * adding a 1 to bit 31 of the results. + * + * **Operations**:\n + * ~~~ + * Mres[x][63:0] = Rs1.W[x] * Rs2.W[x]; + * if (`.u` form) { + * Round[x][32:0] = Mres[x][63:31] + 1; + * res[x] = Rd.W[x] - Round[x][32:1]; + * } else { + * res[x] = Rd.W[x] - Mres[x][63:32]; + * } + * if (res[x] > (2^31)-1) { + * res[x] = (2^31)-1; + * OV = 1; + * } else if (res[x] < -2^31) { + * res[x] = -2^31; + * OV = 1; + * } + * Rd.W[x] = res[x]; + * for RV32: x=0 + * for RV64: x=1...0 + * ~~~ + * + * \param [in] t long type of value stored in t + * \param [in] a long type of value stored in a + * \param [in] b long type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_KMMSB_U(long t, long a, long b) +{ + __ASM volatile("kmmsb.u %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); + return t; +} +/* ===== Inline Function End for 3.48.2. KMMSB.u ===== */ + +/* ===== Inline Function Start for 3.49.1. KMMWB2 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X16_MAC + * \brief KMMWB2 (SIMD Saturating MSW Signed Multiply Word and Bottom Half & 2) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * KMMWB2 Rd, Rs1, Rs2 + * KMMWB2.u Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Multiply the signed 32-bit integer elements of one register and the bottom 16-bit of the + * corresponding 32-bit elements of another register, double the multiplication results and write the + * saturated most significant 32-bit results to the corresponding 32-bit elements of a register. The `.u` + * form rounds up the results from the most significant discarded bit. + * + * **Description**:\n + * This instruction multiplies the signed 32-bit Q31 elements of Rs1 with the signed bottom 16-bit Q15 + * content of the corresponding 32-bit elements of Rs2, doubles the Q46 results to Q47 numbers and + * writes the saturated most significant 32-bit Q31 multiplication results to the corresponding 32-bit + * elements of Rd. The `.u` form of the instruction rounds up the most significant 32-bit of the 48-bit + * Q47 multiplication results by adding a 1 to bit 15 (i.e., bit 14 before doubling) of the results. + * + * **Operations**:\n + * ~~~ + * if ((Rs1.W[x] == 0x80000000) & (Rs2.W[x].H[0] == 0x8000)) { + * Rd.W[x] = 0x7fffffff; + * OV = 1; + * } else { + * Mres[x][47:0] = Rs1.W[x] s* Rs2.W[x].H[0]; + * if (`.u` form) { + * Round[x][32:0] = Mres[x][46:14] + 1; + * Rd.W[x] = Round[x][32:1]; + * } else { + * Rd.W[x] = Mres[x][46:15]; + * } + * } + * for RV32: x=0 + * for RV64: x=1...0 + * ~~~ + * + * \param [in] a long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_KMMWB2(long a, unsigned long b) +{ + register long result; + __ASM volatile("kmmwb2 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.49.1. KMMWB2 ===== */ + +/* ===== Inline Function Start for 3.49.2. KMMWB2.u ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X16_MAC + * \brief KMMWB2.u (SIMD Saturating MSW Signed Multiply Word and Bottom Half & 2 with Rounding) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * KMMWB2 Rd, Rs1, Rs2 + * KMMWB2.u Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Multiply the signed 32-bit integer elements of one register and the bottom 16-bit of the + * corresponding 32-bit elements of another register, double the multiplication results and write the + * saturated most significant 32-bit results to the corresponding 32-bit elements of a register. The `.u` + * form rounds up the results from the most significant discarded bit. + * + * **Description**:\n + * This instruction multiplies the signed 32-bit Q31 elements of Rs1 with the signed bottom 16-bit Q15 + * content of the corresponding 32-bit elements of Rs2, doubles the Q46 results to Q47 numbers and + * writes the saturated most significant 32-bit Q31 multiplication results to the corresponding 32-bit + * elements of Rd. The `.u` form of the instruction rounds up the most significant 32-bit of the 48-bit + * Q47 multiplication results by adding a 1 to bit 15 (i.e., bit 14 before doubling) of the results. + * + * **Operations**:\n + * ~~~ + * if ((Rs1.W[x] == 0x80000000) & (Rs2.W[x].H[0] == 0x8000)) { + * Rd.W[x] = 0x7fffffff; + * OV = 1; + * } else { + * Mres[x][47:0] = Rs1.W[x] s* Rs2.W[x].H[0]; + * if (`.u` form) { + * Round[x][32:0] = Mres[x][46:14] + 1; + * Rd.W[x] = Round[x][32:1]; + * } else { + * Rd.W[x] = Mres[x][46:15]; + * } + * } + * for RV32: x=0 + * for RV64: x=1...0 + * ~~~ + * + * \param [in] a long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_KMMWB2_U(long a, unsigned long b) +{ + register long result; + __ASM volatile("kmmwb2.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.49.2. KMMWB2.u ===== */ + +/* ===== Inline Function Start for 3.50.1. KMMWT2 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X16_MAC + * \brief KMMWT2 (SIMD Saturating MSW Signed Multiply Word and Top Half & 2) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * KMMWT2 Rd, Rs1, Rs2 + * KMMWT2.u Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Multiply the signed 32-bit integer elements of one register and the top 16-bit of the + * corresponding 32-bit elements of another register, double the multiplication results and write the + * saturated most significant 32-bit results to the corresponding 32-bit elements of a register. The `.u` + * form rounds up the results from the most significant discarded bit. + * + * **Description**:\n + * This instruction multiplies the signed 32-bit Q31 elements of Rs1 with the signed top 16-bit Q15 + * content of the corresponding 32-bit elements of Rs2, doubles the Q46 results to Q47 numbers and + * writes the saturated most significant 32-bit Q31 multiplication results to the corresponding 32-bit + * elements of Rd. The `.u` form of the instruction rounds up the most significant 32-bit of the 48-bit + * Q47 multiplication results by adding a 1 to bit 15 (i.e., bit 14 before doubling) of the results. + * + * **Operations**:\n + * ~~~ + * if ((Rs1.W[x] == 0x80000000) & (Rs2.W[x].H[1] == 0x8000)) { + * Rd.W[x] = 0x7fffffff; + * OV = 1; + * } else { + * Mres[x][47:0] = Rs1.W[x] s* Rs2.W[x].H[1]; + * if (`.u` form) { + * Round[x][32:0] = Mres[x][46:14] + 1; + * Rd.W[x] = Round[x][32:1]; + * } else { + * Rd.W[x] = Mres[x][46:15]; + * } + * } + * for RV32: x=0 + * for RV64: x=1...0 + * ~~~ + * + * \param [in] a long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_KMMWT2(long a, unsigned long b) +{ + register long result; + __ASM volatile("kmmwt2 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.50.1. KMMWT2 ===== */ + +/* ===== Inline Function Start for 3.50.2. KMMWT2.u ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X16_MAC + * \brief KMMWT2.u (SIMD Saturating MSW Signed Multiply Word and Top Half & 2 with Rounding) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * KMMWT2 Rd, Rs1, Rs2 + * KMMWT2.u Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Multiply the signed 32-bit integer elements of one register and the top 16-bit of the + * corresponding 32-bit elements of another register, double the multiplication results and write the + * saturated most significant 32-bit results to the corresponding 32-bit elements of a register. The `.u` + * form rounds up the results from the most significant discarded bit. + * + * **Description**:\n + * This instruction multiplies the signed 32-bit Q31 elements of Rs1 with the signed top 16-bit Q15 + * content of the corresponding 32-bit elements of Rs2, doubles the Q46 results to Q47 numbers and + * writes the saturated most significant 32-bit Q31 multiplication results to the corresponding 32-bit + * elements of Rd. The `.u` form of the instruction rounds up the most significant 32-bit of the 48-bit + * Q47 multiplication results by adding a 1 to bit 15 (i.e., bit 14 before doubling) of the results. + * + * **Operations**:\n + * ~~~ + * if ((Rs1.W[x] == 0x80000000) & (Rs2.W[x].H[1] == 0x8000)) { + * Rd.W[x] = 0x7fffffff; + * OV = 1; + * } else { + * Mres[x][47:0] = Rs1.W[x] s* Rs2.W[x].H[1]; + * if (`.u` form) { + * Round[x][32:0] = Mres[x][46:14] + 1; + * Rd.W[x] = Round[x][32:1]; + * } else { + * Rd.W[x] = Mres[x][46:15]; + * } + * } + * for RV32: x=0 + * for RV64: x=1...0 + * ~~~ + * + * \param [in] a long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_KMMWT2_U(long a, unsigned long b) +{ + register long result; + __ASM volatile("kmmwt2.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.50.2. KMMWT2.u ===== */ + +/* ===== Inline Function Start for 3.51.1. KMSDA ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_32B_ADDSUB + * \brief KMSDA (SIMD Saturating Signed Multiply Two Halfs & Add & Subtract) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * KMSDA Rd, Rs1, Rs2 + * KMSXDA Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do two signed 16-bit multiplications from the 32-bit elements of two registers; and then + * subtracts the two 32-bit results from the corresponding 32-bit elements of a third register. The + * subtraction result may be saturated. + * * KMSDA: rd.W[x] - top*top - bottom*bottom (per 32-bit element) + * * KMSXDA: rd.W[x] - top*bottom - bottom*top (per 32-bit element) + * + * **Description**:\n + * For the `KMSDA` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 + * with the bottom 16-bit content of the 32-bit elements of Rs2 and multiplies the top 16-bit content of + * the 32-bit elements of Rs1 with the top 16-bit content of the 32-bit elements of Rs2. + * For the `KMSXDA` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 + * with the top 16-bit content of the 32-bit elements of Rs2 and multiplies the top 16-bit content of the + * 32-bit elements of Rs1 with the bottom 16-bit content of the 32-bit elements of Rs2. + * The two 32-bit multiplication results are then subtracted from the content of the corresponding 32- + * bit elements of Rd. If the subtraction result is beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), it is + * saturated to the range and the OV bit is set to 1. The results after saturation are written to Rd. The + * 16-bit contents are treated as signed integers. + * + * **Operations**:\n + * ~~~ + * // KMSDA + * res[x] = Rd.W[x] - (Rs1.W[x].H[1] * Rs2.W[x].H[1]) - (Rs1.W[x].H[0] * Rs2.W[x].H[0]); + * // KMSXDA + * res[x] = Rd.W[x] - (Rs1.W[x].H[1] * Rs2.W[x].H[0]) - (Rs1.W[x].H[0] * Rs2.W[x].H[1]); + * if (res[x] > (2^31)-1) { + * res[x] = (2^31)-1; + * OV = 1; + * } else if (res[x] < -2^31) { + * res[x] = -2^31; + * OV = 1; + * } + * Rd.W[x] = res[x]; + * for RV32: x=0 + * for RV64: x=1...0 + * ~~~ + * + * \param [in] t long type of value stored in t + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_KMSDA(long t, unsigned long a, unsigned long b) +{ + __ASM volatile("kmsda %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); + return t; +} +/* ===== Inline Function End for 3.51.1. KMSDA ===== */ + +/* ===== Inline Function Start for 3.51.2. KMSXDA ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_32B_ADDSUB + * \brief KMSXDA (SIMD Saturating Signed Crossed Multiply Two Halfs & Add & Subtract) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * KMSDA Rd, Rs1, Rs2 + * KMSXDA Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do two signed 16-bit multiplications from the 32-bit elements of two registers; and then + * subtracts the two 32-bit results from the corresponding 32-bit elements of a third register. The + * subtraction result may be saturated. + * * KMSDA: rd.W[x] - top*top - bottom*bottom (per 32-bit element) + * * KMSXDA: rd.W[x] - top*bottom - bottom*top (per 32-bit element) + * + * **Description**:\n + * For the `KMSDA` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 + * with the bottom 16-bit content of the 32-bit elements of Rs2 and multiplies the top 16-bit content of + * the 32-bit elements of Rs1 with the top 16-bit content of the 32-bit elements of Rs2. + * For the `KMSXDA` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 + * with the top 16-bit content of the 32-bit elements of Rs2 and multiplies the top 16-bit content of the + * 32-bit elements of Rs1 with the bottom 16-bit content of the 32-bit elements of Rs2. + * The two 32-bit multiplication results are then subtracted from the content of the corresponding 32- + * bit elements of Rd. If the subtraction result is beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), it is + * saturated to the range and the OV bit is set to 1. The results after saturation are written to Rd. The + * 16-bit contents are treated as signed integers. + * + * **Operations**:\n + * ~~~ + * // KMSDA + * res[x] = Rd.W[x] - (Rs1.W[x].H[1] * Rs2.W[x].H[1]) - (Rs1.W[x].H[0] * Rs2.W[x].H[0]); + * // KMSXDA + * res[x] = Rd.W[x] - (Rs1.W[x].H[1] * Rs2.W[x].H[0]) - (Rs1.W[x].H[0] * Rs2.W[x].H[1]); + * if (res[x] > (2^31)-1) { + * res[x] = (2^31)-1; + * OV = 1; + * } else if (res[x] < -2^31) { + * res[x] = -2^31; + * OV = 1; + * } + * Rd.W[x] = res[x]; + * for RV32: x=0 + * for RV64: x=1...0 + * ~~~ + * + * \param [in] t long type of value stored in t + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_KMSXDA(long t, unsigned long a, unsigned long b) +{ + __ASM volatile("kmsxda %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); + return t; +} +/* ===== Inline Function End for 3.51.2. KMSXDA ===== */ + +/* ===== Inline Function Start for 3.52. KMSR64 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_32B_MULT_64B_ADDSUB + * \brief KMSR64 (Signed Multiply and Saturating Subtract from 64-Bit Data) + * \details + * **Type**: DSP (64-bit Profile) + * + * **Syntax**:\n + * ~~~ + * KMSR64 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Multiply the 32-bit signed elements in two registers and subtract the 64-bit multiplication + * results from the 64-bit signed data of a pair of registers (RV32) or a register (RV64). The result is + * saturated to the Q63 range and written back to the pair of registers (RV32) or the register (RV64). + * + * **RV32 Description**:\n + * This instruction multiplies the 32-bit signed data of Rs1 with that of Rs2. It + * subtracts the 64-bit multiplication result from the 64-bit signed data of an even/odd pair of registers + * specified by Rd(4,1) with unlimited precision. If the 64-bit subtraction result is beyond the Q63 + * number range (-2^63 <= Q63 <= 2^63-1), it is saturated to the range and the OV bit is set to 1. The saturated + * result is written back to the even/odd pair of registers specified by Rd(4,1). + * Rx(4,1), i.e., d, determines the even/odd pair group of two registers. Specifically, the register pair + * includes register 2d and 2d+1. + * The odd `2d+1` register of the pair contains the high 32-bit of the result and the even `2d` register + * of the pair contains the low 32-bit of the result. + * + * **RV64 Description**:\n + * This instruction multiplies the 32-bit signed elements of Rs1 with that of Rs2. It + * subtracts the 64-bit multiplication results from the 64-bit signed data in Rd with unlimited + * precision. If the 64-bit subtraction result is beyond the Q63 number range (-2^63 <= Q63 <= 2^63-1), it is + * saturated to the range and the OV bit is set to 1. The saturated result is written back to Rd. + * + * **Operations**:\n + * ~~~ + * RV32: + * t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1); + * result = R[t_H].R[t_L] - (Rs1 * Rs2); + * if (result > (2^63)-1) { + * result = (2^63)-1; OV = 1; + * } else if (result < -2^63) { + * result = -2^63; OV = 1; + * } + * R[t_H].R[t_L] = result; + * RV64: + * // `result` has unlimited precision + * result = Rd - (Rs1.W[0] * Rs2.W[0]) - (Rs1.W[1] * Rs2.W[1]); + * if (result > (2^63)-1) { + * result = (2^63)-1; OV = 1; + * } else if (result < -2^63) { + * result = -2^63; OV = 1; + * } + * Rd = result; + * ~~~ + * + * \param [in] t long long type of value stored in t + * \param [in] a long type of value stored in a + * \param [in] b long type of value stored in b + * \return value stored in long long type + */ +__STATIC_FORCEINLINE long long __RV_KMSR64(long long t, long a, long b) +{ + __ASM volatile("kmsr64 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); + return t; +} +/* ===== Inline Function End for 3.52. KMSR64 ===== */ + +/* ===== Inline Function Start for 3.53. KSLLW ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q31_SAT_ALU + * \brief KSLLW (Saturating Shift Left Logical for Word) + * \details + * **Type**: DSP + * + * **Syntax**:\n + * ~~~ + * KSLLW Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do logical left shift operation with saturation on a 32-bit word. The shift amount is a + * variable from a GPR. + * + * **Description**:\n + * The first word data in Rs1 is left-shifted logically. The shifted out bits are filled with + * zero and the shift amount is specified by the low-order 5-bits of the value in the Rs2 register. Any + * shifted value greater than 2^31-1 is saturated to 2^31-1. Any shifted value smaller than -2^31 is saturated + * to -2^31. And the saturated result is sign-extended and written to Rd. If any saturation is performed, + * set OV bit to 1. + * + * **Operations**:\n + * ~~~ + * sa = Rs2[4:0]; + * res[(31+sa):0] = Rs1.W[0] << sa; + * if (res > (2^31)-1) { + * res = 0x7fffffff; OV = 1; + * } else if (res < -2^31) { + * res = 0x80000000; OV = 1; + * } + * Rd[31:0] = res[31:0]; // RV32 + * Rd[63:0] = SE(res[31:0]); // RV64 + * ~~~ + * + * \param [in] a long type of value stored in a + * \param [in] b unsigned int type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_KSLLW(long a, unsigned int b) +{ + register long result; + __ASM volatile("ksllw %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.53. KSLLW ===== */ + +/* ===== Inline Function Start for 3.54. KSLLIW ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q31_SAT_ALU + * \brief KSLLIW (Saturating Shift Left Logical Immediate for Word) + * \details + * **Type**: DSP + * + * **Syntax**:\n + * ~~~ + * KSLLIW Rd, Rs1, imm5u + * ~~~ + * + * **Purpose**:\n + * Do logical left shift operation with saturation on a 32-bit word. The shift amount is an + * immediate value. + * + * **Description**:\n + * The first word data in Rs1 is left-shifted logically. The shifted out bits are filled with + * zero and the shift amount is specified by the imm5u constant. Any shifted value greater than 2^31-1 is + * saturated to 2^31-1. Any shifted value smaller than -2^31 is saturated to -2^31. And the saturated result is + * sign-extended and written to Rd. If any saturation is performed, set OV bit to 1. + * + * **Operations**:\n + * ~~~ + * sa = imm5u; + * res[(31+sa):0] = Rs1.W[0] << sa; + * if (res > (2^31)-1) { + * res = 0x7fffffff; OV = 1; + * } else if (res < -2^31) { + * res = 0x80000000; OV = 1; + * } + * Rd[31:0] = res[31:0]; // RV32 + * Rd[63:0] = SE(res[31:0]); // RV64 + * ~~~ + * + * \param [in] a long type of value stored in a + * \param [in] b unsigned int type of value stored in b + * \return value stored in long type + */ +#define __RV_KSLLIW(a, b) \ + ({ \ + register long result; \ + register long __a = (long)(a); \ + __ASM volatile("kslliw %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b)); \ + result; \ + }) +/* ===== Inline Function End for 3.54. KSLLIW ===== */ + +/* ===== Inline Function Start for 3.55. KSLL8 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_SHIFT + * \brief KSLL8 (SIMD 8-bit Saturating Shift Left Logical) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * KSLL8 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 8-bit elements logical left shift operations with saturation simultaneously. The shift + * amount is a variable from a GPR. + * + * **Description**:\n + * The 8-bit data elements in Rs1 are left-shifted logically. The shifted out bits are filled + * with zero and the shift amount is specified by the low-order 3-bits of the value in the Rs2 register. + * Any shifted value greater than 2^7-1 is saturated to 2^7-1. Any shifted value smaller than -2^7 is + * saturated to -2^7. And the saturated results are written to Rd. If any saturation is performed, set OV + * bit to 1. + * + * **Operations**:\n + * ~~~ + * sa = Rs2[2:0]; + * if (sa != 0) { + * res[(7+sa):0] = Rs1.B[x] << sa; + * if (res > (2^7)-1) { + * res = 0x7f; OV = 1; + * } else if (res < -2^7) { + * res = 0x80; OV = 1; + * } + * Rd.B[x] = res[7:0]; + * } else { + * Rd = Rs1; + * } + * for RV32: x=3...0, + * for RV64: x=7...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned int type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_KSLL8(unsigned long a, unsigned int b) +{ + register unsigned long result; + __ASM volatile("ksll8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.55. KSLL8 ===== */ + +/* ===== Inline Function Start for 3.56. KSLLI8 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_SHIFT + * \brief KSLLI8 (SIMD 8-bit Saturating Shift Left Logical Immediate) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * KSLLI8 Rd, Rs1, imm3u + * ~~~ + * + * **Purpose**:\n + * Do 8-bit elements logical left shift operations with saturation simultaneously. The shift + * amount is an immediate value. + * + * **Description**:\n + * The 8-bit data elements in Rs1 are left-shifted logically. The shifted out bits are filled + * with zero and the shift amount is specified by the imm3u constant. Any shifted value greater than + * 2^7-1 is saturated to 2^7-1. Any shifted value smaller than -2^7 is saturated to -2^7. And the saturated + * results are written to Rd. If any saturation is performed, set OV bit to 1. + * + * **Operations**:\n + * ~~~ + * sa = imm3u[2:0]; + * if (sa != 0) { + * res[(7+sa):0] = Rs1.B[x] << sa; + * if (res > (2^7)-1) { + * res = 0x7f; OV = 1; + * } else if (res < -2^7) { + * res = 0x80; OV = 1; + * } + * Rd.B[x] = res[7:0]; + * } else { + * Rd = Rs1; + * } + * for RV32: x=3...0, + * for RV64: x=7...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned int type of value stored in b + * \return value stored in unsigned long type + */ +#define __RV_KSLLI8(a, b) \ + ({ \ + register unsigned long result; \ + register unsigned long __a = (unsigned long)(a); \ + __ASM volatile("kslli8 %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b)); \ + result; \ + }) +/* ===== Inline Function End for 3.56. KSLLI8 ===== */ + +/* ===== Inline Function Start for 3.57. KSLL16 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_SHIFT + * \brief KSLL16 (SIMD 16-bit Saturating Shift Left Logical) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * KSLL16 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 16-bit elements logical left shift operations with saturation simultaneously. The shift + * amount is a variable from a GPR. + * + * **Description**:\n + * The 16-bit data elements in Rs1 are left-shifted logically. The shifted out bits are filled + * with zero and the shift amount is specified by the low-order 4-bits of the value in the Rs2 register. + * Any shifted value greater than 2^15-1 is saturated to 2^15-1. Any shifted value smaller than -2^15 is + * saturated to -2^15. And the saturated results are written to Rd. If any saturation is performed, set OV + * bit to 1. + * + * **Operations**:\n + * ~~~ + * sa = Rs2[3:0]; + * if (sa != 0) { + * res[(15+sa):0] = Rs1.H[x] << sa; + * if (res > (2^15)-1) { + * res = 0x7fff; OV = 1; + * } else if (res < -2^15) { + * res = 0x8000; OV = 1; + * } + * Rd.H[x] = res[15:0]; + * } else { + * Rd = Rs1; + * } + * for RV32: x=1...0, + * for RV64: x=3...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned int type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_KSLL16(unsigned long a, unsigned int b) +{ + register unsigned long result; + __ASM volatile("ksll16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.57. KSLL16 ===== */ + +/* ===== Inline Function Start for 3.58. KSLLI16 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_SHIFT + * \brief KSLLI16 (SIMD 16-bit Saturating Shift Left Logical Immediate) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * KSLLI16 Rd, Rs1, imm4u + * ~~~ + * + * **Purpose**:\n + * Do 16-bit elements logical left shift operations with saturation simultaneously. The shift + * amount is an immediate value. + * + * **Description**:\n + * The 16-bit data elements in Rs1 are left-shifted logically. The shifted out bits are filled + * with zero and the shift amount is specified by the imm4u constant. Any shifted value greater than + * 2^15-1 is saturated to 2^15-1. Any shifted value smaller than -2^15 is saturated to -2^15. And the saturated + * results are written to Rd. If any saturation is performed, set OV bit to 1. + * + * **Operations**:\n + * ~~~ + * sa = imm4u[3:0]; + * if (sa != 0) { + * res[(15+sa):0] = Rs1.H[x] << sa; + * if (res > (2^15)-1) { + * res = 0x7fff; OV = 1; + * } else if (res < -2^15) { + * res = 0x8000; OV = 1; + * } + * Rd.H[x] = res[15:0]; + * } else { + * Rd = Rs1; + * } + * for RV32: x=1...0, + * for RV64: x=3...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned int type of value stored in b + * \return value stored in unsigned long type + */ +#define __RV_KSLLI16(a, b) \ + ({ \ + register unsigned long result; \ + register unsigned long __a = (unsigned long)(a); \ + __ASM volatile("kslli16 %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b)); \ + result; \ + }) +/* ===== Inline Function End for 3.58. KSLLI16 ===== */ + +/* ===== Inline Function Start for 3.59.1. KSLRA8 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_SHIFT + * \brief KSLRA8 (SIMD 8-bit Shift Left Logical with Saturation or Shift Right Arithmetic) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * KSLRA8 Rd, Rs1, Rs2 + * KSLRA8.u Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 8-bit elements logical left (positive) or arithmetic right (negative) shift operation with + * Q7 saturation for the left shift. The `.u` form performs additional rounding up operations for the + * right shift. + * + * **Description**:\n + * The 8-bit data elements of Rs1 are left-shifted logically or right-shifted arithmetically + * based on the value of Rs2[3:0]. Rs2[3:0] is in the signed range of [-2^3, 2^3-1]. A positive Rs2[3:0] means + * logical left shift and a negative Rs2[3:0] means arithmetic right shift. The shift amount is the + * absolute value of Rs2[3:0]. However, the behavior of `Rs2[3:0]==-2^3 (0x8)` is defined to be + * equivalent to the behavior of `Rs2[3:0]==-(2^3-1) (0x9)`. + * The left-shifted results are saturated to the 8-bit signed integer range of [-2^7, 2^7-1]. For the `.u` form + * of the instruction, the right-shifted results are added a 1 to the most significant discarded bit + * position for rounding effect. After the shift, saturation, or rounding, the final results are written to + * Rd. If any saturation happens, this instruction sets the OV flag. The value of Rs2[31:4] will not affect + * this instruction. + * + * **Operations**:\n + * ~~~ + * if (Rs2[3:0] < 0) { + * sa = -Rs2[3:0]; + * sa = (sa == 8)? 7 : sa; + * if (`.u` form) { + * res[7:-1] = SE9(Rs1.B[x][7:sa-1]) + 1; + * Rd.B[x] = res[7:0]; + * } else { + * Rd.B[x] = SE8(Rs1.B[x][7:sa]); + * } + * } else { + * sa = Rs2[2:0]; + * res[(7+sa):0] = Rs1.B[x] <<(logic) sa; + * if (res > (2^7)-1) { + * res[7:0] = 0x7f; OV = 1; + * } else if (res < -2^7) { + * res[7:0] = 0x80; OV = 1; + * } + * Rd.B[x] = res[7:0]; + * } + * for RV32: x=3...0, + * for RV64: x=7...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b int type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_KSLRA8(unsigned long a, int b) +{ + register unsigned long result; + __ASM volatile("kslra8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.59.1. KSLRA8 ===== */ + +/* ===== Inline Function Start for 3.59.2. KSLRA8.u ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_SHIFT + * \brief KSLRA8.u (SIMD 8-bit Shift Left Logical with Saturation or Rounding Shift Right Arithmetic) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * KSLRA8 Rd, Rs1, Rs2 + * KSLRA8.u Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 8-bit elements logical left (positive) or arithmetic right (negative) shift operation with + * Q7 saturation for the left shift. The `.u` form performs additional rounding up operations for the + * right shift. + * + * **Description**:\n + * The 8-bit data elements of Rs1 are left-shifted logically or right-shifted arithmetically + * based on the value of Rs2[3:0]. Rs2[3:0] is in the signed range of [-2^3, 2^3-1]. A positive Rs2[3:0] means + * logical left shift and a negative Rs2[3:0] means arithmetic right shift. The shift amount is the + * absolute value of Rs2[3:0]. However, the behavior of `Rs2[3:0]==-2^3 (0x8)` is defined to be + * equivalent to the behavior of `Rs2[3:0]==-(2^3-1) (0x9)`. + * The left-shifted results are saturated to the 8-bit signed integer range of [-2^7, 2^7-1]. For the `.u` form + * of the instruction, the right-shifted results are added a 1 to the most significant discarded bit + * position for rounding effect. After the shift, saturation, or rounding, the final results are written to + * Rd. If any saturation happens, this instruction sets the OV flag. The value of Rs2[31:4] will not affect + * this instruction. + * + * **Operations**:\n + * ~~~ + * if (Rs2[3:0] < 0) { + * sa = -Rs2[3:0]; + * sa = (sa == 8)? 7 : sa; + * if (`.u` form) { + * res[7:-1] = SE9(Rs1.B[x][7:sa-1]) + 1; + * Rd.B[x] = res[7:0]; + * } else { + * Rd.B[x] = SE8(Rs1.B[x][7:sa]); + * } + * } else { + * sa = Rs2[2:0]; + * res[(7+sa):0] = Rs1.B[x] <<(logic) sa; + * if (res > (2^7)-1) { + * res[7:0] = 0x7f; OV = 1; + * } else if (res < -2^7) { + * res[7:0] = 0x80; OV = 1; + * } + * Rd.B[x] = res[7:0]; + * } + * for RV32: x=3...0, + * for RV64: x=7...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b int type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_KSLRA8_U(unsigned long a, int b) +{ + register unsigned long result; + __ASM volatile("kslra8.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.59.2. KSLRA8.u ===== */ + +/* ===== Inline Function Start for 3.60.1. KSLRA16 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_SHIFT + * \brief KSLRA16 (SIMD 16-bit Shift Left Logical with Saturation or Shift Right Arithmetic) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * KSLRA16 Rd, Rs1, Rs2 + * KSLRA16.u Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 16-bit elements logical left (positive) or arithmetic right (negative) shift operation with + * Q15 saturation for the left shift. The `.u` form performs additional rounding up operations for the + * right shift. + * + * **Description**:\n + * The 16-bit data elements of Rs1 are left-shifted logically or right-shifted arithmetically + * based on the value of Rs2[4:0]. Rs2[4:0] is in the signed range of [-2^4, 2^4-1]. A positive Rs2[4:0] means + * logical left shift and a negative Rs2[4:0] means arithmetic right shift. The shift amount is the + * absolute value of Rs2[4:0]. However, the behavior of `Rs2[4:0]==-2^4 (0x10)` is defined to be + * equivalent to the behavior of `Rs2[4:0]==-(2^4-1) (0x11)`. + * The left-shifted results are saturated to the 16-bit signed integer range of [-2^15, 2^15-1]. For the `.u` + * form of the instruction, the right-shifted results are added a 1 to the most significant discarded bit + * position for rounding effect. After the shift, saturation, or rounding, the final results are written to + * Rd. If any saturation happens, this instruction sets the OV flag. The value of Rs2[31:5] will not affect + * this instruction. + * + * **Operations**:\n + * ~~~ + * if (Rs2[4:0] < 0) { + * sa = -Rs2[4:0]; + * sa = (sa == 16)? 15 : sa; + * if (`.u` form) { + * res[15:-1] = SE17(Rs1.H[x][15:sa-1]) + 1; + * Rd.H[x] = res[15:0]; + * } else { + * Rd.H[x] = SE16(Rs1.H[x][15:sa]); + * } + * } else { + * sa = Rs2[3:0]; + * res[(15+sa):0] = Rs1.H[x] <<(logic) sa; + * if (res > (2^15)-1) { + * res[15:0] = 0x7fff; OV = 1; + * } else if (res < -2^15) { + * res[15:0] = 0x8000; OV = 1; + * } + * d.H[x] = res[15:0]; + * } + * for RV32: x=1...0, + * for RV64: x=3...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b int type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_KSLRA16(unsigned long a, int b) +{ + register unsigned long result; + __ASM volatile("kslra16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.60.1. KSLRA16 ===== */ + +/* ===== Inline Function Start for 3.60.2. KSLRA16.u ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_SHIFT + * \brief KSLRA16.u (SIMD 16-bit Shift Left Logical with Saturation or Rounding Shift Right Arithmetic) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * KSLRA16 Rd, Rs1, Rs2 + * KSLRA16.u Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 16-bit elements logical left (positive) or arithmetic right (negative) shift operation with + * Q15 saturation for the left shift. The `.u` form performs additional rounding up operations for the + * right shift. + * + * **Description**:\n + * The 16-bit data elements of Rs1 are left-shifted logically or right-shifted arithmetically + * based on the value of Rs2[4:0]. Rs2[4:0] is in the signed range of [-2^4, 2^4-1]. A positive Rs2[4:0] means + * logical left shift and a negative Rs2[4:0] means arithmetic right shift. The shift amount is the + * absolute value of Rs2[4:0]. However, the behavior of `Rs2[4:0]==-2^4 (0x10)` is defined to be + * equivalent to the behavior of `Rs2[4:0]==-(2^4-1) (0x11)`. + * The left-shifted results are saturated to the 16-bit signed integer range of [-2^15, 2^15-1]. For the `.u` + * form of the instruction, the right-shifted results are added a 1 to the most significant discarded bit + * position for rounding effect. After the shift, saturation, or rounding, the final results are written to + * Rd. If any saturation happens, this instruction sets the OV flag. The value of Rs2[31:5] will not affect + * this instruction. + * + * **Operations**:\n + * ~~~ + * if (Rs2[4:0] < 0) { + * sa = -Rs2[4:0]; + * sa = (sa == 16)? 15 : sa; + * if (`.u` form) { + * res[15:-1] = SE17(Rs1.H[x][15:sa-1]) + 1; + * Rd.H[x] = res[15:0]; + * } else { + * Rd.H[x] = SE16(Rs1.H[x][15:sa]); + * } + * } else { + * sa = Rs2[3:0]; + * res[(15+sa):0] = Rs1.H[x] <<(logic) sa; + * if (res > (2^15)-1) { + * res[15:0] = 0x7fff; OV = 1; + * } else if (res < -2^15) { + * res[15:0] = 0x8000; OV = 1; + * } + * d.H[x] = res[15:0]; + * } + * for RV32: x=1...0, + * for RV64: x=3...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b int type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_KSLRA16_U(unsigned long a, int b) +{ + register unsigned long result; + __ASM volatile("kslra16.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.60.2. KSLRA16.u ===== */ + +/* ===== Inline Function Start for 3.61. KSLRAW ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q31_SAT_ALU + * \brief KSLRAW (Shift Left Logical with Q31 Saturation or Shift Right Arithmetic) + * \details + * **Type**: DSP + * + * **Syntax**:\n + * ~~~ + * KSLRAW Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Perform a logical left (positive) or arithmetic right (negative) shift operation with Q31 + * saturation for the left shift on a 32-bit data. + * + * **Description**:\n + * The lower 32-bit content of Rs1 is left-shifted logically or right-shifted arithmetically + * based on the value of Rs2[5:0]. Rs2[5:0] is in the signed range of [-25, 25-1]. A positive Rs2[5:0] means + * logical left shift and a negative Rs2[5:0] means arithmetic right shift. The shift amount is the + * absolute value of Rs2[5:0] clamped to the actual shift range of [0, 31]. + * The left-shifted result is saturated to the 32-bit signed integer range of [-2^31, 2^31-1]. After the shift + * operation, the final result is bit-31 sign-extended and written to Rd. If any saturation happens, this + * instruction sets the OV flag. The value of Rs2[31:6] will not affected the operation of this instruction. + * + * **Operations**:\n + * ~~~ + * if (Rs2[5:0] < 0) { + * sa = -Rs2[5:0]; + * sa = (sa == 32)? 31 : sa; + * res[31:0] = Rs1.W[0] >>(arith) sa; + * } else { + * sa = Rs2[5:0]; + * tmp = Rs1.W[0] <<(logic) sa; + * if (tmp > (2^31)-1) { + * res[31:0] = (2^31)-1; + * OV = 1; + * } else if (tmp < -2^31) { + * res[31:0] = -2^31; + * OV = 1 + * } else { + * res[31:0] = tmp[31:0]; + * } + * } + * Rd = res[31:0]; // RV32 + * Rd = SE64(res[31:0]); // RV64 + * ~~~ + * + * \param [in] a int type of value stored in a + * \param [in] b int type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_KSLRAW(int a, int b) +{ + register long result; + __ASM volatile("kslraw %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.61. KSLRAW ===== */ + +/* ===== Inline Function Start for 3.62. KSLRAW.u ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q31_SAT_ALU + * \brief KSLRAW.u (Shift Left Logical with Q31 Saturation or Rounding Shift Right Arithmetic) + * \details + * **Type**: DSP + * + * **Syntax**:\n + * ~~~ + * KSLRAW.u Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Perform a logical left (positive) or arithmetic right (negative) shift operation with Q31 + * saturation for the left shift and a rounding up operation for the right shift on a 32-bit data. + * + * **Description**:\n + * The lower 32-bit content of Rs1 is left-shifted logically or right-shifted arithmetically + * based on the value of Rs2[5:0]. Rs2[5:0] is in the signed range of [-25, 25-1]. A positive Rs2[5:0] means + * logical left shift and a negative Rs2[5:0] means arithmetic right shift. The shift amount is the + * absolute value of Rs2[5:0] clamped to the actual shift range of [0, 31]. + * The left-shifted result is saturated to the 32-bit signed integer range of [-2^31, 2^31-1]. The right-shifted + * result is added a 1 to the most significant discarded bit position for rounding effect. After the shift, + * saturation, or rounding, the final result is bit-31 sign-extended and written to Rd. If any saturation + * happens, this instruction sets the OV flag. The value of Rs2[31:6] will not affect the operation of this + * instruction. + * + * **Operations**:\n + * ~~~ + * if (Rs2[5:0] < 0) { + * sa = -Rs2[5:0]; + * sa = (sa == 32)? 31 : sa; + * res[31:-1] = SE33(Rs1[31:(sa-1)]) + 1; + * rst[31:0] = res[31:0]; + * } else { + * sa = Rs2[5:0]; + * tmp = Rs1.W[0] <<(logic) sa; + * if (tmp > (2^31)-1) { + * rst[31:0] = (2^31)-1; + * OV = 1; + * } else if (tmp < -2^31) { + * rst[31:0] = -2^31; + * OV = 1 + * } else { + * rst[31:0] = tmp[31:0]; + * } + * } + * Rd = rst[31:0]; // RV32 + * Rd = SE64(rst[31:0]); // RV64 + * ~~~ + * + * \param [in] a int type of value stored in a + * \param [in] b int type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_KSLRAW_U(int a, int b) +{ + register long result; + __ASM volatile("kslraw.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.62. KSLRAW.u ===== */ + +/* ===== Inline Function Start for 3.63. KSTAS16 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB + * \brief KSTAS16 (SIMD 16-bit Signed Saturating Straight Addition & Subtraction) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * KSTAS16 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 16-bit signed integer element saturating addition and 16-bit signed integer element + * saturating subtraction in a 32-bit chunk simultaneously. Operands are from corresponding + * positions in 32-bit chunks. + * + * **Description**:\n + * This instruction adds the 16-bit signed integer element in [31:16] of 32-bit chunks in + * Rs1 with the 16-bit signed integer element in [31:16] of 32-bit chunks in Rs2; at the same time, it + * subtracts the 16-bit signed integer element in [15:0] of 32-bit chunks in Rs2 from the 16-bit signed + * integer element in [15:0] of 32-bit chunks in Rs1. If any of the results are beyond the Q15 number + * range (-2^15 <= Q15 <= 2^15-1), they are saturated to the range and the OV bit is set to 1. The saturated + * results are written to [31:16] of 32-bit chunks in Rd for addition and [15:0] of 32-bit chunks in Rd for + * subtraction. + * + * **Operations**:\n + * ~~~ + * res1 = Rs1.W[x][31:16] + Rs2.W[x][31:16]; + * res2 = Rs1.W[x][15:0] - Rs2.W[x][15:0]; + * for (res in [res1, res2]) { + * if (res > (2^15)-1) { + * res = (2^15)-1; + * OV = 1; + * } else if (res < -2^15) { + * res = -2^15; + * OV = 1; + * } + * } + * Rd.W[x][31:16] = res1; + * Rd.W[x][15:0] = res2; + * for RV32, x=0 + * for RV64, x=1...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_KSTAS16(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("kstas16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.63. KSTAS16 ===== */ + +/* ===== Inline Function Start for 3.64. KSTSA16 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB + * \brief KSTSA16 (SIMD 16-bit Signed Saturating Straight Subtraction & Addition) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * KSTSA16 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 16-bit signed integer element saturating subtraction and 16-bit signed integer element + * saturating addition in a 32-bit chunk simultaneously. Operands are from corresponding positions in + * 32-bit chunks. + * + * **Description**:\n + * This instruction subtracts the 16-bit signed integer element in [31:16] of 32-bit chunks + * in Rs2 from the 16-bit signed integer element in [31:16] of 32-bit chunks in Rs1; at the same time, it + * adds the 16-bit signed integer element in [15:0] of 32-bit chunks in Rs2 with the 16-bit signed integer + * element in [15:0] of 32-bit chunks in Rs1. If any of the results are beyond the Q15 number range (-2^15 + * <= Q15 <= 2^15-1), they are saturated to the range and the OV bit is set to 1. The saturated results are + * written to [31:16] of 32-bit chunks in Rd for subtraction and [15:0] of 32-bit chunks in Rd for + * addition. + * + * **Operations**:\n + * ~~~ + * res1 = Rs1.W[x][31:16] - Rs2.W[x][31:16]; + * res2 = Rs1.W[x][15:0] + Rs2.W[x][15:0]; + * for (res in [res1, res2]) { + * if (res > (2^15)-1) { + * res = (2^15)-1; + * OV = 1; + * } else if (res < -2^15) { + * res = -2^15; + * OV = 1; + * } + * } + * Rd.W[x][31:16] = res1; + * Rd.W[x][15:0] = res2; + * for RV32, x=0 + * for RV64, x=1...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_KSTSA16(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("kstsa16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.64. KSTSA16 ===== */ + +/* ===== Inline Function Start for 3.65. KSUB8 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_ADDSUB + * \brief KSUB8 (SIMD 8-bit Signed Saturating Subtraction) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * KSUB8 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 8-bit signed elements saturating subtractions simultaneously. + * + * **Description**:\n + * This instruction subtracts the 8-bit signed integer elements in Rs2 from the 8-bit + * signed integer elements in Rs1. If any of the results are beyond the Q7 number range (-2^7 <= Q7 <= 27 + * -1), they are saturated to the range and the OV bit is set to 1. The saturated results are written to Rd. + * + * **Operations**:\n + * ~~~ + * res[x] = Rs1.B[x] - Rs2.B[x]; + * if (res[x] > (2^7)-1) { + * res[x] = (2^7)-1; + * OV = 1; + * } else if (res[x] < -2^7) { + * res[x] = -2^7; + * OV = 1; + * } + * Rd.B[x] = res[x]; + * for RV32: x=3...0, + * for RV64: x=7...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_KSUB8(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("ksub8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.65. KSUB8 ===== */ + +/* ===== Inline Function Start for 3.66. KSUB16 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB + * \brief KSUB16 (SIMD 16-bit Signed Saturating Subtraction) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * KSUB16 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 16-bit signed integer elements saturating subtractions simultaneously. + * + * **Description**:\n + * This instruction subtracts the 16-bit signed integer elements in Rs2 from the 16-bit + * signed integer elements in Rs1. If any of the results are beyond the Q15 number range (-2^15 <= Q15 <= + * 2^15-1), they are saturated to the range and the OV bit is set to 1. The saturated results are written to + * Rd. + * + * **Operations**:\n + * ~~~ + * res[x] = Rs1.H[x] - Rs2.H[x]; + * if (res[x] > (2^15)-1) { + * res[x] = (2^15)-1; + * OV = 1; + * } else if (res[x] < -2^15) { + * res[x] = -2^15; + * OV = 1; + * } + * Rd.H[x] = res[x]; + * for RV32: x=1...0, + * for RV64: x=3...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_KSUB16(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("ksub16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.66. KSUB16 ===== */ + +/* ===== Inline Function Start for 3.67. KSUB64 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_64B_ADDSUB + * \brief KSUB64 (64-bit Signed Saturating Subtraction) + * \details + * **Type**: DSP (64-bit Profile) + * + * **Syntax**:\n + * ~~~ + * KSUB64 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Perform a 64-bit signed integer subtraction. The result is saturated to the Q63 range. + * + * **RV32 Description**:\n + * This instruction subtracts the 64-bit signed integer of an even/odd pair of + * registers specified by Rs2(4,1) from the 64-bit signed integer of an even/odd pair of registers + * specified by Rs1(4,1). If the 64-bit result is beyond the Q63 number range (-2^63 <= Q63 <= 2^63-1), it is + * saturated to the range and the OV bit is set to 1. The saturated result is then written to an even/odd + * pair of registers specified by Rd(4,1). + * Rx(4,1), i.e., d, determines the even/odd pair group of two registers. Specifically, the register pair + * includes register 2d and 2d+1. + * The odd `2d+1` register of the pair contains the high 32-bit of the operand and the even `2d` + * register of the pair contains the low 32-bit of the operand. + * + * **RV64 Description**:\n + * This instruction subtracts the 64-bit signed integer of Rs2 from the 64-bit signed + * integer of Rs1. If the 64-bit result is beyond the Q63 number range (-2^63 <= Q63 <= 2^63-1), it is saturated + * to the range and the OV bit is set to 1. The saturated result is then written to Rd. + * + * **Operations**:\n + * ~~~ + * RV32: + * t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1); + * a_L = CONCAT(Rs1(4,1),1'b0); a_H = CONCAT(Rs1(4,1),1'b1); + * b_L = CONCAT(Rs2(4,1),1'b0); b_H = CONCAT(Rs2(4,1),1'b1); + * result = R[a_H].R[a_L] - R[b_H].R[b_L]; + * if (result > (2^63)-1) { + * result = (2^63)-1; OV = 1; + * } else if (result < -2^63) { + * result = -2^63; OV = 1; + * } + * R[t_H].R[t_L] = result; + * RV64: + * result = Rs1 - Rs2; + * if (result > (2^63)-1) { + * result = (2^63)-1; OV = 1; + * } else if (result < -2^63) { + * result = -2^63; OV = 1; + * } + * Rd = result; + * ~~~ + * + * \param [in] a long long type of value stored in a + * \param [in] b long long type of value stored in b + * \return value stored in long long type + */ +__STATIC_FORCEINLINE long long __RV_KSUB64(long long a, long long b) +{ + register long long result; + __ASM volatile("ksub64 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.67. KSUB64 ===== */ + +/* ===== Inline Function Start for 3.68. KSUBH ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q15_SAT_ALU + * \brief KSUBH (Signed Subtraction with Q15 Saturation) + * \details + * **Type**: DSP + * + * **Syntax**:\n + * ~~~ + * KSUBH Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Subtract the signed lower 32-bit content of two registers with Q15 saturation. + * + * **Description**:\n + * The signed lower 32-bit content of Rs2 is subtracted from the signed lower 32-bit + * content of Rs1. And the result is saturated to the 16-bit signed integer range of [-2^15, 2^15-1] and then + * sign-extended and written to Rd. If saturation happens, this instruction sets the OV flag. + * + * **Operations**:\n + * ~~~ + * tmp = Rs1.W[0] - Rs2.W[0]; + * if (tmp > (2^15)-1) { + * res = (2^15)-1; + * OV = 1; + * } else if (tmp < -2^15) { + * res = -2^15; + * OV = 1 + * } else { + * res = tmp; + * } + * Rd = SE(res[15:0]); + * ~~~ + * + * \param [in] a int type of value stored in a + * \param [in] b int type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_KSUBH(int a, int b) +{ + register long result; + __ASM volatile("ksubh %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.68. KSUBH ===== */ + +/* ===== Inline Function Start for 3.69. KSUBW ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q31_SAT_ALU + * \brief KSUBW (Signed Subtraction with Q31 Saturation) + * \details + * **Type**: DSP + * + * **Syntax**:\n + * ~~~ + * KSUBW Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Subtract the signed lower 32-bit content of two registers with Q31 saturation. + * + * **Description**:\n + * The signed lower 32-bit content of Rs2 is subtracted from the signed lower 32-bit + * content of Rs1. And the result is saturated to the 32-bit signed integer range of [-2^31, 2^31-1] and then + * sign-extened and written to Rd. If saturation happens, this instruction sets the OV flag. + * + * **Operations**:\n + * ~~~ + * tmp = Rs1.W[0] - Rs2.W[0]; + * if (tmp > (2^31)-1) { + * res = (2^31)-1; + * OV = 1; + * } else if (tmp < -2^31) { + * res = -2^31; + * OV = 1 + * } else { + * res = tmp; + * } + * Rd = res[31:0]; // RV32 + * Rd = SE(res[31:0]); // RV64 + * ~~~ + * + * \param [in] a int type of value stored in a + * \param [in] b int type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_KSUBW(int a, int b) +{ + register long result; + __ASM volatile("ksubw %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.69. KSUBW ===== */ + +/* ===== Inline Function Start for 3.70.1. KWMMUL ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X32_MAC + * \brief KWMMUL (SIMD Saturating MSW Signed Multiply Word & Double) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * KWMMUL Rd, Rs1, Rs2 + * KWMMUL.u Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Multiply the signed 32-bit integer elements of two registers, shift the results left 1-bit, + * saturate, and write the most significant 32-bit results to a register. The `.u` form additionally + * rounds up the multiplication results from the most signification discarded bit. + * + * **Description**:\n + * This instruction multiplies the 32-bit elements of Rs1 with the 32-bit elements of Rs2. It then shifts + * the multiplication results one bit to the left and takes the most significant 32-bit results. If the + * shifted result is greater than 2^31-1, it is saturated to 2^31-1 and the OV flag is set to 1. The final element + * result is written to Rd. The 32-bit elements of Rs1 and Rs2 are treated as signed integers. The `.u` + * form of the instruction additionally rounds up the 64-bit multiplication results by adding a 1 to bit + * 30 before the shift and saturation operations. + * + * **Operations**:\n + * ~~~ + * if ((0x80000000 != Rs1.W[x]) | (0x80000000 != Rs2.W[x])) { + * Mres[x][63:0] = Rs1.W[x] * Rs2.W[x]; + * if (`.u` form) { + * Round[x][33:0] = Mres[x][63:30] + 1; + * Rd.W[x] = Round[x][32:1]; + * } else { + * Rd.W[x] = Mres[x][62:31]; + * } + * } else { + * Rd.W[x] = 0x7fffffff; + * OV = 1; + * } + * for RV32: x=0 + * for RV64: x=1...0 + * ~~~ + * + * \param [in] a long type of value stored in a + * \param [in] b long type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_KWMMUL(long a, long b) +{ + register long result; + __ASM volatile("kwmmul %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.70.1. KWMMUL ===== */ + +/* ===== Inline Function Start for 3.70.2. KWMMUL.u ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X32_MAC + * \brief KWMMUL.u (SIMD Saturating MSW Signed Multiply Word & Double with Rounding) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * KWMMUL Rd, Rs1, Rs2 + * KWMMUL.u Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Multiply the signed 32-bit integer elements of two registers, shift the results left 1-bit, + * saturate, and write the most significant 32-bit results to a register. The `.u` form additionally + * rounds up the multiplication results from the most signification discarded bit. + * + * **Description**:\n + * This instruction multiplies the 32-bit elements of Rs1 with the 32-bit elements of Rs2. It then shifts + * the multiplication results one bit to the left and takes the most significant 32-bit results. If the + * shifted result is greater than 2^31-1, it is saturated to 2^31-1 and the OV flag is set to 1. The final element + * result is written to Rd. The 32-bit elements of Rs1 and Rs2 are treated as signed integers. The `.u` + * form of the instruction additionally rounds up the 64-bit multiplication results by adding a 1 to bit + * 30 before the shift and saturation operations. + * + * **Operations**:\n + * ~~~ + * if ((0x80000000 != Rs1.W[x]) | (0x80000000 != Rs2.W[x])) { + * Mres[x][63:0] = Rs1.W[x] * Rs2.W[x]; + * if (`.u` form) { + * Round[x][33:0] = Mres[x][63:30] + 1; + * Rd.W[x] = Round[x][32:1]; + * } else { + * Rd.W[x] = Mres[x][62:31]; + * } + * } else { + * Rd.W[x] = 0x7fffffff; + * OV = 1; + * } + * for RV32: x=0 + * for RV64: x=1...0 + * ~~~ + * + * \param [in] a long type of value stored in a + * \param [in] b long type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_KWMMUL_U(long a, long b) +{ + register long result; + __ASM volatile("kwmmul.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.70.2. KWMMUL.u ===== */ + +/* ===== Inline Function Start for 3.71. MADDR32 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_MISC + * \brief MADDR32 (Multiply and Add to 32-Bit Word) + * \details + * **Type**: DSP + * + * **Syntax**:\n + * ~~~ + * MADDR32 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Multiply the 32-bit contents of two registers and add the lower 32-bit multiplication result + * to the 32-bit content of a destination register. Write the final result back to the destination register. + * + * **Description**:\n + * This instruction multiplies the lower 32-bit content of Rs1 with that of Rs2. It adds the + * lower 32-bit multiplication result to the lower 32-bit content of Rd and writes the final result (RV32) + * or sign-extended result (RV64) back to Rd. The contents of Rs1 and Rs2 can be either signed or + * unsigned integers. + * + * **Operations**:\n + * ~~~ + * RV32: + * Mresult = Rs1 * Rs2; + * Rd = Rd + Mresult.W[0]; + * RV64: + * Mresult = Rs1.W[0] * Rs2.W[0]; + * tres[31:0] = Rd.W[0] + Mresult.W[0]; + * Rd = SE64(tres[31:0]); + * ~~~ + * + * \param [in] t unsigned long type of value stored in t + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_MADDR32(unsigned long t, unsigned long a, unsigned long b) +{ + __ASM volatile("maddr32 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); + return t; +} +/* ===== Inline Function End for 3.71. MADDR32 ===== */ + +/* ===== Inline Function Start for 3.72. MAXW ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_32B_COMPUTATION + * \brief MAXW (32-bit Signed Word Maximum) + * \details + * **Type**: DSP + * + * **Syntax**:\n + * ~~~ + * MAXW Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Get the larger value from the 32-bit contents of two general registers. + * + * **Description**:\n + * This instruction compares two signed 32-bit integers stored in Rs1 and Rs2, picks the + * larger value as the result, and writes the result to Rd. + * + * **Operations**:\n + * ~~~ + * if (Rs1.W[0] >= Rs2.W[0]) { + * Rd = SE(Rs1.W[0]); + * } else { + * Rd = SE(Rs2.W[0]); + * } + * ~~~ + * + * \param [in] a int type of value stored in a + * \param [in] b int type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_MAXW(int a, int b) +{ + register long result; + __ASM volatile("maxw %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.72. MAXW ===== */ + +/* ===== Inline Function Start for 3.73. MINW ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_32B_COMPUTATION + * \brief MINW (32-bit Signed Word Minimum) + * \details + * **Type**: DSP + * + * **Syntax**:\n + * ~~~ + * MINW Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Get the smaller value from the 32-bit contents of two general registers. + * + * **Description**:\n + * This instruction compares two signed 32-bit integers stored in Rs1 and Rs2, picks the + * smaller value as the result, and writes the result to Rd. + * + * **Operations**:\n + * ~~~ + * if (Rs1.W[0] >= Rs2.W[0]) { Rd = SE(Rs2.W[0]); } else { Rd = SE(Rs1.W[0]); } + * ~~~ + * + * \param [in] a int type of value stored in a + * \param [in] b int type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_MINW(int a, int b) +{ + register long result; + __ASM volatile("minw %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.73. MINW ===== */ + +/* ===== Inline Function Start for 3.74. MSUBR32 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_MISC + * \brief MSUBR32 (Multiply and Subtract from 32-Bit Word) + * \details + * **Type**: DSP + * + * **Syntax**:\n + * ~~~ + * MSUBR32 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Multiply the 32-bit contents of two registers and subtract the lower 32-bit multiplication + * result from the 32-bit content of a destination register. Write the final result back to the destination + * register. + * + * **Description**:\n + * This instruction multiplies the lower 32-bit content of Rs1 with that of Rs2, subtracts + * the lower 32-bit multiplication result from the lower 32-bit content of Rd, then writes the final + * result (RV32) or sign-extended result (RV64) back to Rd. The contents of Rs1 and Rs2 can be either + * signed or unsigned integers. + * + * **Operations**:\n + * ~~~ + * RV32: + * Mresult = Rs1 * Rs2; + * Rd = Rd - Mresult.W[0]; + * RV64: + * Mresult = Rs1.W[0] * Rs2.W[0]; + * tres[31:0] = Rd.W[0] - Mresult.W[0]; + * Rd = SE64(tres[31:0]); + * ~~~ + * + * \param [in] t unsigned long type of value stored in t + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_MSUBR32(unsigned long t, unsigned long a, unsigned long b) +{ + __ASM volatile("msubr32 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); + return t; +} +/* ===== Inline Function End for 3.74. MSUBR32 ===== */ + +/* ===== Inline Function Start for 3.75. MULR64 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_32B_COMPUTATION + * \brief MULR64 (Multiply Word Unsigned to 64-bit Data) + * \details + * **Type**: DSP + * + * **Syntax**:\n + * ~~~ + * MULR64 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Multiply the 32-bit unsigned integer contents of two registers and write the 64-bit result. + * + * **RV32 Description**:\n + * This instruction multiplies the 32-bit content of Rs1 with that of Rs2 and writes the 64-bit + * multiplication result to an even/odd pair of registers containing Rd. Rd(4,1) index d determines the + * even/odd pair group of the two registers. Specifically, the register pair includes register 2d and + * 2d+1. + * The odd `2d+1` register of the pair contains the high 32-bit of the result and the even `2d` register + * of the pair contains the low 32-bit of the result. + * The lower 32-bit contents of Rs1 and Rs2 are treated as unsigned integers. + * + * **RV64 Description**:\n + * This instruction multiplies the lower 32-bit content of Rs1 with that of Rs2 and writes the 64-bit + * multiplication result to Rd. + * The lower 32-bit contents of Rs1 and Rs2 are treated as unsigned integers. + * + * **Operations**:\n + * ~~~ + * RV32: + * Mresult = CONCAT(1`b0,Rs1) u* CONCAT(1`b0,Rs2); + * R[Rd(4,1).1(0)][31:0] = Mresult[63:32]; + * R[Rd(4,1).0(0)][31:0] = Mresult[31:0]; + * RV64: + * Rd = Mresult[63:0]; + * Mresult = CONCAT(1`b0,Rs1.W[0]) u* CONCAT(1`b0,Rs2.W[0]); + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long long type + */ +__STATIC_FORCEINLINE unsigned long long __RV_MULR64(unsigned long a, unsigned long b) +{ + register unsigned long long result; + __ASM volatile("mulr64 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.75. MULR64 ===== */ + +/* ===== Inline Function Start for 3.76. MULSR64 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_32B_COMPUTATION + * \brief MULSR64 (Multiply Word Signed to 64-bit Data) + * \details + * **Type**: DSP + * + * **Syntax**:\n + * ~~~ + * MULSR64 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Multiply the 32-bit signed integer contents of two registers and write the 64-bit result. + * + * **RV32 Description**:\n + * This instruction multiplies the lower 32-bit content of Rs1 with the lower 32-bit content of Rs2 and + * writes the 64-bit multiplication result to an even/odd pair of registers containing Rd. Rd(4,1) index d + * determines the even/odd pair group of the two registers. Specifically, the register pair includes + * register 2d and 2d+1. + * The odd `2d+1` register of the pair contains the high 32-bit of the result and the even `2d` register + * of the pair contains the low 32-bit of the result. + * The lower 32-bit contents of Rs1 and Rs2 are treated as signed integers. + * + * **RV64 Description**:\n + * This instruction multiplies the lower 32-bit content of Rs1 with the lower 32-bit content of Rs2 and + * writes the 64-bit multiplication result to Rd. + * The lower 32-bit contents of Rs1 and Rs2 are treated as signed integers. + * + * **Operations**:\n + * ~~~ + * RV32: + * Mresult = Ra s* Rb; + * R[Rd(4,1).1(0)][31:0] = Mresult[63:32]; + * R[Rd(4,1).0(0)][31:0] = Mresult[31:0]; + * RV64: + * Mresult = Ra.W[0] s* Rb.W[0]; + * Rd = Mresult[63:0]; + * ~~~ + * + * \param [in] a long type of value stored in a + * \param [in] b long type of value stored in b + * \return value stored in long long type + */ +__STATIC_FORCEINLINE long long __RV_MULSR64(long a, long b) +{ + register long long result; + __ASM volatile("mulsr64 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.76. MULSR64 ===== */ + +/* ===== Inline Function Start for 3.77. PBSAD ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_PART_SIMD_MISC + * \brief PBSAD (Parallel Byte Sum of Absolute Difference) + * \details + * **Type**: DSP + * + * **Syntax**:\n + * ~~~ + * PBSAD Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Calculate the sum of absolute difference of unsigned 8-bit data elements. + * + * **Description**:\n + * This instruction subtracts the un-signed 8-bit elements of Rs2 from those of Rs1. Then + * it adds the absolute value of each difference together and writes the result to Rd. + * + * **Operations**:\n + * ~~~ + * absdiff[x] = ABS(Rs1.B[x] - Rs2.B[x]); + * Rd = SUM(absdiff[x]); + * for RV32: x=3...0, + * for RV64: x=7...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_PBSAD(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("pbsad %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.77. PBSAD ===== */ + +/* ===== Inline Function Start for 3.78. PBSADA ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_PART_SIMD_MISC + * \brief PBSADA (Parallel Byte Sum of Absolute Difference Accum) + * \details + * **Type**: DSP + * + * **Syntax**:\n + * ~~~ + * PBSADA Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Calculate the sum of absolute difference of four unsigned 8-bit data elements and + * accumulate it into a register. + * + * **Description**:\n + * This instruction subtracts the un-signed 8-bit elements of Rs2 from those of Rs1. It + * then adds the absolute value of each difference together along with the content of Rd and writes the + * accumulated result back to Rd. + * + * **Operations**:\n + * ~~~ + * absdiff[x] = ABS(Rs1.B[x] - Rs2.B[x]); + * Rd = Rd + SUM(absdiff[x]); + * for RV32: x=3...0, + * for RV64: x=7...0 + * ~~~ + * + * \param [in] t unsigned long type of value stored in t + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_PBSADA(unsigned long t, unsigned long a, unsigned long b) +{ + __ASM volatile("pbsada %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); + return t; +} +/* ===== Inline Function End for 3.78. PBSADA ===== */ + +/* ===== Inline Function Start for 3.79.1. PKBB16 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_PACK + * \brief PKBB16 (Pack Two 16-bit Data from Both Bottom Half) + * \details + * **Type**: DSP + * + * **Syntax**:\n + * ~~~ + * PKBB16 Rd, Rs1, Rs2 + * PKBT16 Rd, Rs1, Rs2 + * PKTT16 Rd, Rs1, Rs2 + * PKTB16 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Pack 16-bit data from 32-bit chunks in two registers. + * * PKBB16: bottom.bottom + * * PKBT16 bottom.top + * * PKTT16 top.top + * * PKTB16 top.bottom + * + * **Description**:\n + * (PKBB16) moves Rs1.W[x][15:0] to Rd.W[x][31:16] and moves Rs2.W[x] [15:0] to + * Rd.W[x] [15:0]. + * (PKBT16) moves Rs1.W[x] [15:0] to Rd.W[x] [31:16] and moves Rs2.W[x] [31:16] to Rd.W[x] [15:0]. + * (PKTT16) moves Rs1.W[x] [31:16] to Rd.W[x] [31:16] and moves Rs2.W[x] [31:16] to Rd.W[x] [15:0]. + * (PKTB16) moves Rs1.W[x] [31:16] to Rd.W[x] [31:16] and moves Rs2.W[x] [15:0] to Rd.W[x] [15:0]. + * + * **Operations**:\n + * ~~~ + * Rd.W[x][31:0] = CONCAT(Rs1.W[x][15:0], Rs2.W[x][15:0]); // PKBB16 + * Rd.W[x][31:0] = CONCAT(Rs1.W[x][15:0], Rs2.W[x][31:16]); // PKBT16 + * Rd.W[x][31:0] = CONCAT(Rs1.W[x][31:16], Rs2.W[x][15:0]); // PKTB16 + * Rd.W[x][31:0] = CONCAT(Rs1.W[x][31:16], Rs2.W[x][31:16]); // PKTT16 + * for RV32: x=0, + * for RV64: x=1...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_PKBB16(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("pkbb16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.79.1. PKBB16 ===== */ + +/* ===== Inline Function Start for 3.79.2. PKBT16 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_PACK + * \brief PKBT16 (Pack Two 16-bit Data from Bottom and Top Half) + * \details + * **Type**: DSP + * + * **Syntax**:\n + * ~~~ + * PKBB16 Rd, Rs1, Rs2 + * PKBT16 Rd, Rs1, Rs2 + * PKTT16 Rd, Rs1, Rs2 + * PKTB16 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Pack 16-bit data from 32-bit chunks in two registers. + * * PKBB16: bottom.bottom + * * PKBT16 bottom.top + * * PKTT16 top.top + * * PKTB16 top.bottom + * + * **Description**:\n + * (PKBB16) moves Rs1.W[x][15:0] to Rd.W[x][31:16] and moves Rs2.W[x] [15:0] to + * Rd.W[x] [15:0]. + * (PKBT16) moves Rs1.W[x] [15:0] to Rd.W[x] [31:16] and moves Rs2.W[x] [31:16] to Rd.W[x] [15:0]. + * (PKTT16) moves Rs1.W[x] [31:16] to Rd.W[x] [31:16] and moves Rs2.W[x] [31:16] to Rd.W[x] [15:0]. + * (PKTB16) moves Rs1.W[x] [31:16] to Rd.W[x] [31:16] and moves Rs2.W[x] [15:0] to Rd.W[x] [15:0]. + * + * **Operations**:\n + * ~~~ + * Rd.W[x][31:0] = CONCAT(Rs1.W[x][15:0], Rs2.W[x][15:0]); // PKBB16 + * Rd.W[x][31:0] = CONCAT(Rs1.W[x][15:0], Rs2.W[x][31:16]); // PKBT16 + * Rd.W[x][31:0] = CONCAT(Rs1.W[x][31:16], Rs2.W[x][15:0]); // PKTB16 + * Rd.W[x][31:0] = CONCAT(Rs1.W[x][31:16], Rs2.W[x][31:16]); // PKTT16 + * for RV32: x=0, + * for RV64: x=1...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_PKBT16(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("pkbt16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.79.2. PKBT16 ===== */ + +/* ===== Inline Function Start for 3.79.3. PKTT16 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_PACK + * \brief PKTT16 (Pack Two 16-bit Data from Both Top Half) + * \details + * **Type**: DSP + * + * **Syntax**:\n + * ~~~ + * PKBB16 Rd, Rs1, Rs2 + * PKBT16 Rd, Rs1, Rs2 + * PKTT16 Rd, Rs1, Rs2 + * PKTB16 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Pack 16-bit data from 32-bit chunks in two registers. + * * PKBB16: bottom.bottom + * * PKBT16 bottom.top + * * PKTT16 top.top + * * PKTB16 top.bottom + * + * **Description**:\n + * (PKBB16) moves Rs1.W[x][15:0] to Rd.W[x][31:16] and moves Rs2.W[x] [15:0] to + * Rd.W[x] [15:0]. + * (PKBT16) moves Rs1.W[x] [15:0] to Rd.W[x] [31:16] and moves Rs2.W[x] [31:16] to Rd.W[x] [15:0]. + * (PKTT16) moves Rs1.W[x] [31:16] to Rd.W[x] [31:16] and moves Rs2.W[x] [31:16] to Rd.W[x] [15:0]. + * (PKTB16) moves Rs1.W[x] [31:16] to Rd.W[x] [31:16] and moves Rs2.W[x] [15:0] to Rd.W[x] [15:0]. + * + * **Operations**:\n + * ~~~ + * Rd.W[x][31:0] = CONCAT(Rs1.W[x][15:0], Rs2.W[x][15:0]); // PKBB16 + * Rd.W[x][31:0] = CONCAT(Rs1.W[x][15:0], Rs2.W[x][31:16]); // PKBT16 + * Rd.W[x][31:0] = CONCAT(Rs1.W[x][31:16], Rs2.W[x][15:0]); // PKTB16 + * Rd.W[x][31:0] = CONCAT(Rs1.W[x][31:16], Rs2.W[x][31:16]); // PKTT16 + * for RV32: x=0, + * for RV64: x=1...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_PKTT16(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("pktt16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.79.3. PKTT16 ===== */ + +/* ===== Inline Function Start for 3.79.4. PKTB16 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_PACK + * \brief PKTB16 (Pack Two 16-bit Data from Top and Bottom Half) + * \details + * **Type**: DSP + * + * **Syntax**:\n + * ~~~ + * PKBB16 Rd, Rs1, Rs2 + * PKBT16 Rd, Rs1, Rs2 + * PKTT16 Rd, Rs1, Rs2 + * PKTB16 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Pack 16-bit data from 32-bit chunks in two registers. + * * PKBB16: bottom.bottom + * * PKBT16 bottom.top + * * PKTT16 top.top + * * PKTB16 top.bottom + * + * **Description**:\n + * (PKBB16) moves Rs1.W[x][15:0] to Rd.W[x][31:16] and moves Rs2.W[x] [15:0] to + * Rd.W[x] [15:0]. + * (PKBT16) moves Rs1.W[x] [15:0] to Rd.W[x] [31:16] and moves Rs2.W[x] [31:16] to Rd.W[x] [15:0]. + * (PKTT16) moves Rs1.W[x] [31:16] to Rd.W[x] [31:16] and moves Rs2.W[x] [31:16] to Rd.W[x] [15:0]. + * (PKTB16) moves Rs1.W[x] [31:16] to Rd.W[x] [31:16] and moves Rs2.W[x] [15:0] to Rd.W[x] [15:0]. + * + * **Operations**:\n + * ~~~ + * Rd.W[x][31:0] = CONCAT(Rs1.W[x][15:0], Rs2.W[x][15:0]); // PKBB16 + * Rd.W[x][31:0] = CONCAT(Rs1.W[x][15:0], Rs2.W[x][31:16]); // PKBT16 + * Rd.W[x][31:0] = CONCAT(Rs1.W[x][31:16], Rs2.W[x][15:0]); // PKTB16 + * Rd.W[x][31:0] = CONCAT(Rs1.W[x][31:16], Rs2.W[x][31:16]); // PKTT16 + * for RV32: x=0, + * for RV64: x=1...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_PKTB16(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("pktb16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.79.4. PKTB16 ===== */ + +/* ===== Inline Function Start for 3.80. RADD8 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_ADDSUB + * \brief RADD8 (SIMD 8-bit Signed Halving Addition) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * RADD8 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 8-bit signed integer element additions simultaneously. The element results are halved + * to avoid overflow or saturation. + * + * **Description**:\n + * This instruction adds the 8-bit signed integer elements in Rs1 with the 8-bit signed + * integer elements in Rs2. The results are first arithmetically right-shifted by 1 bit and then written to + * Rd. + * + * **Examples**:\n + * ~~~ + * * Rs1 = 0x7F, Rs2 = 0x7F, Rd = 0x7F + * * Rs1 = 0x80, Rs2 = 0x80, Rd = 0x80 + * * Rs1 = 0x40, Rs2 = 0x80, Rd = 0xE0 + * ~~~ + * + * **Operations**:\n + * ~~~ + * Rd.B[x] = (Rs1.B[x] + Rs2.B[x]) s>> 1; for RV32: x=3...0, for RV64: x=7...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_RADD8(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("radd8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.80. RADD8 ===== */ + +/* ===== Inline Function Start for 3.81. RADD16 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB + * \brief RADD16 (SIMD 16-bit Signed Halving Addition) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * RADD16 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 16-bit signed integer element additions simultaneously. The results are halved to avoid + * overflow or saturation. + * + * **Description**:\n + * This instruction adds the 16-bit signed integer elements in Rs1 with the 16-bit signed + * integer elements in Rs2. The results are first arithmetically right-shifted by 1 bit and then written to + * Rd. + * + * **Examples**:\n + * ~~~ + * * Rs1 = 0x7FFF, Rs2 = 0x7FFF, Rd = 0x7FFF + * * Rs1 = 0x8000, Rs2 = 0x8000, Rd = 0x8000 + * * Rs1 = 0x4000, Rs2 = 0x8000, Rd = 0xE000 + * ~~~ + * + * **Operations**:\n + * ~~~ + * Rd.H[x] = (Rs1.H[x] + Rs2.H[x]) s>> 1; for RV32: x=1...0, for RV64: x=3...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_RADD16(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("radd16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.81. RADD16 ===== */ + +/* ===== Inline Function Start for 3.82. RADD64 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_64B_ADDSUB + * \brief RADD64 (64-bit Signed Halving Addition) + * \details + * **Type**: DSP (64-bit Profile) + * + * **Syntax**:\n + * ~~~ + * RADD64 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Add two 64-bit signed integers. The result is halved to avoid overflow or saturation. + * + * **RV32 Description**:\n + * This instruction adds the 64-bit signed integer of an even/odd pair of registers + * specified by Rs1(4,1) with the 64-bit signed integer of an even/odd pair of registers specified by + * Rs2(4,1). The 64-bit addition result is first arithmetically right-shifted by 1 bit and then written to an + * even/odd pair of registers specified by Rd(4,1). + * Rx(4,1), i.e., value d, determines the even/odd pair group of two registers. Specifically, the register + * pair includes register 2d and 2d+1. + * The odd `2d+1` register of the pair contains the high 32-bit of the result and the even `2d` register + * of the pair contains the low 32-bit of the result. + * + * **RV64 Description**:\n + * This instruction adds the 64-bit signed integer in Rs1 with the 64-bit signed + * integer in Rs2. The 64-bit addition result is first arithmetically right-shifted by 1 bit and then + * written to Rd. + * + * **Operations**:\n + * ~~~ + * RV32: + * t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1); + * a_L = CONCAT(Rs1(4,1),1'b0); a_H = CONCAT(Rs1(4,1),1'b1); + * b_L = CONCAT(Rs2(4,1),1'b0); b_H = CONCAT(Rs2(4,1),1'b1); + * R[t_H].R[t_L] = (R[a_H].R[a_L] + R[b_H].R[b_L]) s>> 1; + * RV64: + * Rd = (Rs1 + Rs2) s>> 1; + * ~~~ + * + * \param [in] a long long type of value stored in a + * \param [in] b long long type of value stored in b + * \return value stored in long long type + */ +__STATIC_FORCEINLINE long long __RV_RADD64(long long a, long long b) +{ + register long long result; + __ASM volatile("radd64 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.82. RADD64 ===== */ + +/* ===== Inline Function Start for 3.83. RADDW ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_32B_COMPUTATION + * \brief RADDW (32-bit Signed Halving Addition) + * \details + * **Type**: DSP + * + * **Syntax**:\n + * ~~~ + * RADDW Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Add 32-bit signed integers and the results are halved to avoid overflow or saturation. + * + * **Description**:\n + * This instruction adds the first 32-bit signed integer in Rs1 with the first 32-bit signed + * integer in Rs2. The result is first arithmetically right-shifted by 1 bit and then sign-extended and + * written to Rd. + * + * **Examples**:\n + * ~~~ + * * Rs1 = 0x7FFFFFFF, Rs2 = 0x7FFFFFFF, Rd = 0x7FFFFFFF + * * Rs1 = 0x80000000, Rs2 = 0x80000000, Rd = 0x80000000 + * * Rs1 = 0x40000000, Rs2 = 0x80000000, Rd = 0xE0000000 + * ~~~ + * + * **Operations**:\n + * ~~~ + * RV32: + * Rd[31:0] = (Rs1[31:0] + Rs2[31:0]) s>> 1; + * RV64: + * resw[31:0] = (Rs1[31:0] + Rs2[31:0]) s>> 1; + * Rd[63:0] = SE(resw[31:0]); + * ~~~ + * + * \param [in] a int type of value stored in a + * \param [in] b int type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_RADDW(int a, int b) +{ + register long result; + __ASM volatile("raddw %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.83. RADDW ===== */ + +/* ===== Inline Function Start for 3.84. RCRAS16 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB + * \brief RCRAS16 (SIMD 16-bit Signed Halving Cross Addition & Subtraction) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * RCRAS16 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 16-bit signed integer element addition and 16-bit signed integer element subtraction in + * a 32-bit chunk simultaneously. Operands are from crossed positions in 32-bit chunks. The results + * are halved to avoid overflow or saturation. + * + * **Description**:\n + * This instruction adds the 16-bit signed integer element in [31:16] of 32-bit chunks in + * Rs1 with the 16-bit signed integer element in [15:0] of 32-bit chunks in Rs2, and subtracts the 16-bit + * signed integer element in [31:16] of 32-bit chunks in Rs2 from the 16-bit signed integer element in + * [15:0] of 32-bit chunks in Rs1. The element results are first arithmetically right-shifted by 1 bit and + * then written to [31:16] of 32-bit chunks in Rd and [15:0] of 32-bit chunks in Rd. + * + * **Examples**:\n + * ~~~ + * Please see `RADD16` and `RSUB16` instructions. + * ~~~ + * + * **Operations**:\n + * ~~~ + * Rd.W[x][31:16] = (Rs1.W[x][31:16] + Rs2.W[x][15:0]) s>> 1; + * Rd.W[x][15:0] = (Rs1.W[x][15:0] - Rs2.W[x][31:16]) s>> 1; + * for RV32, x=0 + * for RV64, x=1...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_RCRAS16(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("rcras16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.84. RCRAS16 ===== */ + +/* ===== Inline Function Start for 3.85. RCRSA16 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB + * \brief RCRSA16 (SIMD 16-bit Signed Halving Cross Subtraction & Addition) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * RCRSA16 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 16-bit signed integer element subtraction and 16-bit signed integer element addition in + * a 32-bit chunk simultaneously. Operands are from crossed positions in 32-bit chunks. The results + * are halved to avoid overflow or saturation. + * + * **Description**:\n + * This instruction subtracts the 16-bit signed integer element in [15:0] of 32-bit chunks + * in Rs2 from the 16-bit signed integer element in [31:16] of 32-bit chunks in Rs1, and adds the 16-bit + * signed element integer in [15:0] of 32-bit chunks in Rs1 with the 16-bit signed integer element in + * [31:16] of 32-bit chunks in Rs2. The two results are first arithmetically right-shifted by 1 bit and + * then written to [31:16] of 32-bit chunks in Rd and [15:0] of 32-bit chunks in Rd. + * + * **Examples**:\n + * ~~~ + * Please see `RADD16` and `RSUB16` instructions. + * ~~~ + * + * **Operations**:\n + * ~~~ + * Rd.W[x][31:16] = (Rs1.W[x][31:16] - Rs2.W[x][15:0]) s>> 1; + * Rd.W[x][15:0] = (Rs1.W[x][15:0] + Rs2.W[x][31:16]) s>> 1; + * for RV32, x=0 + * for RV64, x=1...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_RCRSA16(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("rcrsa16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.85. RCRSA16 ===== */ + +/* ===== Inline Function Start for 3.86. RDOV ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_OV_FLAG_SC + * \brief RDOV (Read OV flag) + * \details + * **Type**: DSP + * + * **Syntax**:\n + * ~~~ + * RDOV Rd # pseudo mnemonic + * ~~~ + * + * **Purpose**:\n + * This pseudo instruction is an alias to `CSRR Rd, ucode` instruction which maps to the real + * instruction of `CSRRS Rd, ucode, x0`. + * + * + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_RDOV(void) +{ + register unsigned long result; + __ASM volatile("rdov %0" : "=r"(result)); + return result; +} +/* ===== Inline Function End for 3.86. RDOV ===== */ + +/* ===== Inline Function Start for 3.87. RSTAS16 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB + * \brief RSTAS16 (SIMD 16-bit Signed Halving Straight Addition & Subtraction) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * RSTAS16 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 16-bit signed integer element addition and 16-bit signed integer element subtraction in + * a 32-bit chunk simultaneously. Operands are from corresponding positions in 32-bit chunks. The + * results are halved to avoid overflow or saturation. + * + * **Description**:\n + * This instruction adds the 16-bit signed integer element in [31:16] of 32-bit chunks in + * Rs1 with the 16-bit signed integer element in [31:16] of 32-bit chunks in Rs2, and subtracts the 16-bit + * signed integer element in [15:0] of 32-bit chunks in Rs2 from the 16-bit signed integer element in + * [15:0] of 32-bit chunks in Rs1. The element results are first arithmetically right-shifted by 1 bit and + * then written to [31:16] of 32-bit chunks in Rd and [15:0] of 32-bit chunks in Rd. + * + * **Examples**:\n + * ~~~ + * Please see `RADD16` and `RSUB16` instructions. + * ~~~ + * + * **Operations**:\n + * ~~~ + * Rd.W[x][31:16] = (Rs1.W[x][31:16] + Rs2.W[x][31:16]) s>> 1; + * Rd.W[x][15:0] = (Rs1.W[x][15:0] - Rs2.W[x][15:0]) s>> 1; + * for RV32, x=0 + * for RV64, x=1...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_RSTAS16(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("rstas16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.87. RSTAS16 ===== */ + +/* ===== Inline Function Start for 3.88. RSTSA16 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB + * \brief RSTSA16 (SIMD 16-bit Signed Halving Straight Subtraction & Addition) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * RSTSA16 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 16-bit signed integer element subtraction and 16-bit signed integer element addition in + * a 32-bit chunk simultaneously. Operands are from corresponding positions in 32-bit chunks. The + * results are halved to avoid overflow or saturation. + * + * **Description**:\n + * This instruction subtracts the 16-bit signed integer element in [31:16] of 32-bit chunks + * in Rs2 from the 16-bit signed integer element in [31:16] of 32-bit chunks in Rs1, and adds the 16-bit + * signed element integer in [15:0] of 32-bit chunks in Rs1 with the 16-bit signed integer element in + * [15:0] of 32-bit chunks in Rs2. The two results are first arithmetically right-shifted by 1 bit and then + * written to [31:16] of 32-bit chunks in Rd and [15:0] of 32-bit chunks in Rd. + * + * **Examples**:\n + * ~~~ + * Please see `RADD16` and `RSUB16` instructions. + * ~~~ + * + * **Operations**:\n + * ~~~ + * Rd.W[x][31:16] = (Rs1.W[x][31:16] - Rs2.W[x][31:16]) s>> 1; + * Rd.W[x][15:0] = (Rs1.W[x][15:0] + Rs2.W[x][15:0]) s>> 1; + * for RV32, x=0 + * for RV64, x=1...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_RSTSA16(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("rstsa16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.88. RSTSA16 ===== */ + +/* ===== Inline Function Start for 3.89. RSUB8 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_ADDSUB + * \brief RSUB8 (SIMD 8-bit Signed Halving Subtraction) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * RSUB8 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 8-bit signed integer element subtractions simultaneously. The results are halved to + * avoid overflow or saturation. + * + * **Description**:\n + * This instruction subtracts the 8-bit signed integer elements in Rs2 from the 8-bit + * signed integer elements in Rs1. The results are first arithmetically right-shifted by 1 bit and then + * written to Rd. + * + * **Examples**:\n + * ~~~ + * * Rs1 = 0x7F, Rs2 = 0x80, Rd = 0x7F + * * Rs1 = 0x80, Rs2 = 0x7F, Rd = 0x80 + * * Rs1= 0x80, Rs2 = 0x40, Rd = 0xA0 + * ~~~ + * + * **Operations**:\n + * ~~~ + * Rd.B[x] = (Rs1.B[x] - Rs2.B[x]) s>> 1; + * for RV32: x=3...0, + * for RV64: x=7...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_RSUB8(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("rsub8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.89. RSUB8 ===== */ + +/* ===== Inline Function Start for 3.90. RSUB16 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB + * \brief RSUB16 (SIMD 16-bit Signed Halving Subtraction) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * RSUB16 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 16-bit signed integer element subtractions simultaneously. The results are halved to + * avoid overflow or saturation. + * + * **Description**:\n + * This instruction subtracts the 16-bit signed integer elements in Rs2 from the 16-bit + * signed integer elements in Rs1. The results are first arithmetically right-shifted by 1 bit and then + * written to Rd. + * + * **Examples**:\n + * ~~~ + * * Ra = 0x7FFF, Rb = 0x8000, Rt = 0x7FFF + * * Ra = 0x8000, Rb = 0x7FFF, Rt = 0x8000 + * * Ra = 0x8000, Rb = 0x4000, Rt = 0xA000 + * ~~~ + * + * **Operations**:\n + * ~~~ + * Rd.H[x] = (Rs1.H[x] - Rs2.H[x]) s>> 1; + * for RV32: x=1...0, + * for RV64: x=3...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_RSUB16(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("rsub16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.90. RSUB16 ===== */ + +/* ===== Inline Function Start for 3.91. RSUB64 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_64B_ADDSUB + * \brief RSUB64 (64-bit Signed Halving Subtraction) + * \details + * **Type**: DSP (64-bit Profile) + * + * **Syntax**:\n + * ~~~ + * RSUB64 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Perform a 64-bit signed integer subtraction. The result is halved to avoid overflow or + * saturation. + * + * **RV32 Description**:\n + * This instruction subtracts the 64-bit signed integer of an even/odd pair of + * registers specified by Rb(4,1) from the 64-bit signed integer of an even/odd pair of registers + * specified by Ra(4,1). The subtraction result is first arithmetically right-shifted by 1 bit and then + * written to an even/odd pair of registers specified by Rt(4,1). + * Rx(4,1), i.e., value d, determines the even/odd pair group of two registers. Specifically, the register + * pair includes register 2d and 2d+1. + * The odd `2d+1` register of the pair contains the high 32-bit of the result and the even `2d` register + * of the pair contains the low 32-bit of the result. + * + * **RV64 Description**:\n + * This instruction subtracts the 64-bit signed integer in Rs2 from the 64-bit signed + * integer in Rs1. The 64-bit subtraction result is first arithmetically right-shifted by 1 bit and then + * written to Rd. + * + * **Operations**:\n + * ~~~ + * RV32: + * t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1); + * a_L = CONCAT(Rs1(4,1),1'b0); a_H = CONCAT(Rs1(4,1),1'b1); + * b_L = CONCAT(Rs2(4,1),1'b0); b_H = CONCAT(Rs2(4,1),1'b1); + * R[t_H].R[t_L] = (R[a_H].R[a_L] - R[b_H].R[b_L]) s>> 1; + * RV64: + * Rd = (Rs1 - Rs2) s>> 1; + * ~~~ + * + * \param [in] a long long type of value stored in a + * \param [in] b long long type of value stored in b + * \return value stored in long long type + */ +__STATIC_FORCEINLINE long long __RV_RSUB64(long long a, long long b) +{ + register long long result; + __ASM volatile("rsub64 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.91. RSUB64 ===== */ + +/* ===== Inline Function Start for 3.92. RSUBW ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_32B_COMPUTATION + * \brief RSUBW (32-bit Signed Halving Subtraction) + * \details + * **Type**: DSP + * + * **Syntax**:\n + * ~~~ + * RSUBW Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Subtract 32-bit signed integers and the result is halved to avoid overflow or saturation. + * + * **Description**:\n + * This instruction subtracts the first 32-bit signed integer in Rs2 from the first 32-bit + * signed integer in Rs1. The result is first arithmetically right-shifted by 1 bit and then sign-extended + * and written to Rd. + * + * **Examples**:\n + * ~~~ + * * Rs1 = 0x7FFFFFFF, Rs2 = 0x80000000, Rd = 0x7FFFFFFF + * * Rs1 = 0x80000000, Rs2 = 0x7FFFFFFF, Rd = 0x80000000 + * * Rs1 = 0x80000000, Rs2 = 0x40000000, Rd = 0xA0000000 + * ~~~ + * + * **Operations**:\n + * ~~~ + * RV32: + * Rd[31:0] = (Rs1[31:0] - Rs2[31:0]) s>> 1; + * RV64: + * resw[31:0] = (Rs1[31:0] - Rs2[31:0]) s>> 1; + * Rd[63:0] = SE(resw[31:0]); + * ~~~ + * + * \param [in] a int type of value stored in a + * \param [in] b int type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_RSUBW(int a, int b) +{ + register long result; + __ASM volatile("rsubw %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.92. RSUBW ===== */ + +/* ===== Inline Function Start for 3.93. SCLIP8 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_MISC + * \brief SCLIP8 (SIMD 8-bit Signed Clip Value) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * SCLIP8 Rd, Rs1, imm3u[2:0] + * ~~~ + * + * **Purpose**:\n + * Limit the 8-bit signed integer elements of a register into a signed range simultaneously. + * + * **Description**:\n + * This instruction limits the 8-bit signed integer elements stored in Rs1 into a signed + * integer range between 2^imm3u-1 and -2^imm3u, and writes the limited results to Rd. For example, if + * imm3u is 3, the 8-bit input values should be saturated between 7 and -8. If saturation is performed, + * set OV bit to 1. + * + * **Operations**:\n + * ~~~ + * src = Rs1.B[x]; + * if (src > (2^imm3u)-1) { + * src = (2^imm3u)-1; + * OV = 1; + * } else if (src < -2^imm3u) { + * src = -2^imm3u; + * OV = 1; + * } + * Rd.B[x] = src + * for RV32: x=3...0, + * for RV64: x=7...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned int type of value stored in b + * \return value stored in unsigned long type + */ +#define __RV_SCLIP8(a, b) \ + ({ \ + register unsigned long result; \ + register unsigned long __a = (unsigned long)(a); \ + __ASM volatile("sclip8 %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b)); \ + result; \ + }) +/* ===== Inline Function End for 3.93. SCLIP8 ===== */ + +/* ===== Inline Function Start for 3.94. SCLIP16 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_MISC + * \brief SCLIP16 (SIMD 16-bit Signed Clip Value) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * SCLIP16 Rd, Rs1, imm4u[3:0] + * ~~~ + * + * **Purpose**:\n + * Limit the 16-bit signed integer elements of a register into a signed range simultaneously. + * + * **Description**:\n + * This instruction limits the 16-bit signed integer elements stored in Rs1 into a signed + * integer range between 2imm4u-1 and -2imm4u, and writes the limited results to Rd. For example, if + * imm4u is 3, the 16-bit input values should be saturated between 7 and -8. If saturation is performed, + * set OV bit to 1. + * + * **Operations**:\n + * ~~~ + * src = Rs1.H[x]; + * if (src > (2^imm4u)-1) { + * src = (2^imm4u)-1; + * OV = 1; + * } else if (src < -2^imm4u) { + * src = -2^imm4u; + * OV = 1; + * } + * Rd.H[x] = src + * for RV32: x=1...0, + * for RV64: x=3...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned int type of value stored in b + * \return value stored in unsigned long type + */ +#define __RV_SCLIP16(a, b) \ + ({ \ + register unsigned long result; \ + register unsigned long __a = (unsigned long)(a); \ + __ASM volatile("sclip16 %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b)); \ + result; \ + }) +/* ===== Inline Function End for 3.94. SCLIP16 ===== */ + +/* ===== Inline Function Start for 3.95. SCLIP32 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_PART_SIMD_MISC + * \brief SCLIP32 (SIMD 32-bit Signed Clip Value) + * \details + * **Type**: DSP + * + * **Syntax**:\n + * ~~~ + * SCLIP32 Rd, Rs1, imm5u[4:0] + * ~~~ + * + * **Purpose**:\n + * Limit the 32-bit signed integer elements of a register into a signed range simultaneously. + * + * **Description**:\n + * This instruction limits the 32-bit signed integer elements stored in Rs1 into a signed + * integer range between 2imm5u-1 and -2imm5u, and writes the limited results to Rd. For example, if + * imm5u is 3, the 32-bit input values should be saturated between 7 and -8. If saturation is performed, + * set OV bit to 1. + * + * **Operations**:\n + * ~~~ + * src = Rs1.W[x]; + * if (src > (2^imm5u)-1) { + * src = (2^imm5u)-1; + * OV = 1; + * } else if (src < -2^imm5u) { + * src = -2^imm5u; + * OV = 1; + * } + * Rd.W[x] = src + * for RV32: x=0, + * for RV64: x=1...0 + * ~~~ + * + * \param [in] a long type of value stored in a + * \param [in] b unsigned int type of value stored in b + * \return value stored in long type + */ +#define __RV_SCLIP32(a, b) \ + ({ \ + register long result; \ + register long __a = (long)(a); \ + __ASM volatile("sclip32 %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b)); \ + result; \ + }) +/* ===== Inline Function End for 3.95. SCLIP32 ===== */ + +/* ===== Inline Function Start for 3.96. SCMPLE8 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_CMP + * \brief SCMPLE8 (SIMD 8-bit Signed Compare Less Than & Equal) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * SCMPLE8 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 8-bit signed integer elements less than & equal comparisons simultaneously. + * + * **Description**:\n + * This instruction compares the 8-bit signed integer elements in Rs1 with the 8-bit + * signed integer elements in Rs2 to see if the one in Rs1 is less than or equal to the one in Rs2. If it is + * true, the result is 0xFF; otherwise, the result is 0x0. The element comparison results are written to + * Rd + * + * **Operations**:\n + * ~~~ + * Rd.B[x] = (Rs1.B[x] {le} Rs2.B[x])? 0xff : 0x0; + * for RV32: x=3...0, + * for RV64: x=7...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_SCMPLE8(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("scmple8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.96. SCMPLE8 ===== */ + +/* ===== Inline Function Start for 3.97. SCMPLE16 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_CMP + * \brief SCMPLE16 (SIMD 16-bit Signed Compare Less Than & Equal) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * SCMPLE16 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 16-bit signed integer elements less than & equal comparisons simultaneously. + * + * **Description**:\n + * This instruction compares the 16-bit signed integer elements in Rs1 with the 16-bit + * signed integer elements in Rs2 to see if the one in Rs1 is less than or equal to the one in Rs2. If it is + * true, the result is 0xFFFF; otherwise, the result is 0x0. The element comparison results are written + * to Rd. + * + * **Operations**:\n + * ~~~ + * Rd.H[x] = (Rs1.H[x] {le} Rs2.H[x])? 0xffff : 0x0; + * for RV32: x=1...0, + * for RV64: x=3...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_SCMPLE16(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("scmple16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.97. SCMPLE16 ===== */ + +/* ===== Inline Function Start for 3.98. SCMPLT8 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_CMP + * \brief SCMPLT8 (SIMD 8-bit Signed Compare Less Than) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * SCMPLT8 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 8-bit signed integer elements less than comparisons simultaneously. + * + * **Description**:\n + * This instruction compares the 8-bit signed integer elements in Rs1 with the 8-bit + * signed integer elements in Rs2 to see if the one in Rs1 is less than the one in Rs2. If it is true, the + * result is 0xFF; otherwise, the result is 0x0. The element comparison results are written to Rd. + * + * **Operations**:\n + * ~~~ + * Rd.B[x] = (Rs1.B[x] < Rs2.B[x])? 0xff : 0x0; + * for RV32: x=3...0, + * for RV64: x=7...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_SCMPLT8(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("scmplt8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.98. SCMPLT8 ===== */ + +/* ===== Inline Function Start for 3.99. SCMPLT16 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_CMP + * \brief SCMPLT16 (SIMD 16-bit Signed Compare Less Than) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * SCMPLT16 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 16-bit signed integer elements less than comparisons simultaneously. + * + * **Description**:\n + * This instruction compares the 16-bit signed integer elements in Rs1 with the two 16- + * bit signed integer elements in Rs2 to see if the one in Rs1 is less than the one in Rs2. If it is true, the + * result is 0xFFFF; otherwise, the result is 0x0. The element comparison results are written to Rd. + * + * **Operations**:\n + * ~~~ + * Rd.H[x] = (Rs1.H[x] < Rs2.H[x])? 0xffff : 0x0; + * for RV32: x=1...0, + * for RV64: x=3...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_SCMPLT16(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("scmplt16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.99. SCMPLT16 ===== */ + +/* ===== Inline Function Start for 3.100. SLL8 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_SHIFT + * \brief SLL8 (SIMD 8-bit Shift Left Logical) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * SLL8 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 8-bit elements logical left shift operations simultaneously. The shift amount is a + * variable from a GPR. + * + * **Description**:\n + * The 8-bit elements in Rs1 are left-shifted logically. And the results are written to Rd. + * The shifted out bits are filled with zero and the shift amount is specified by the low-order 3-bits of + * the value in the Rs2 register. + * + * **Operations**:\n + * ~~~ + * sa = Rs2[2:0]; + * Rd.B[x] = Rs1.B[x] << sa; + * for RV32: x=3...0, + * for RV64: x=7...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned int type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_SLL8(unsigned long a, unsigned int b) +{ + register unsigned long result; + __ASM volatile("sll8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.100. SLL8 ===== */ + +/* ===== Inline Function Start for 3.101. SLLI8 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_SHIFT + * \brief SLLI8 (SIMD 8-bit Shift Left Logical Immediate) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * SLLI8 Rd, Rs1, imm3u + * ~~~ + * + * **Purpose**:\n + * Do 8-bit elements logical left shift operations simultaneously. The shift amount is an + * immediate value. + * + * **Description**:\n + * The 8-bit elements in Rs1 are left-shifted logically. And the results are written to Rd. + * The shifted out bits are filled with zero and the shift amount is specified by the imm3u constant. + * + * **Operations**:\n + * ~~~ + * sa = imm3u[2:0]; + * Rd.B[x] = Rs1.B[x] << sa; + * for RV32: x=3...0, + * for RV64: x=7...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned int type of value stored in b + * \return value stored in unsigned long type + */ +#define __RV_SLLI8(a, b) \ + ({ \ + register unsigned long result; \ + register unsigned long __a = (unsigned long)(a); \ + __ASM volatile("slli8 %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b)); \ + result; \ + }) +/* ===== Inline Function End for 3.101. SLLI8 ===== */ + +/* ===== Inline Function Start for 3.102. SLL16 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_SHIFT + * \brief SLL16 (SIMD 16-bit Shift Left Logical) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * SLL16 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 16-bit elements logical left shift operations simultaneously. The shift amount is a + * variable from a GPR. + * + * **Description**:\n + * The 16-bit elements in Rs1 are left-shifted logically. And the results are written to Rd. + * The shifted out bits are filled with zero and the shift amount is specified by the low-order 4-bits of + * the value in the Rs2 register. + * + * **Operations**:\n + * ~~~ + * sa = Rs2[3:0]; + * Rd.H[x] = Rs1.H[x] << sa; + * for RV32: x=1...0, + * for RV64: x=3...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned int type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_SLL16(unsigned long a, unsigned int b) +{ + register unsigned long result; + __ASM volatile("sll16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.102. SLL16 ===== */ + +/* ===== Inline Function Start for 3.103. SLLI16 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_SHIFT + * \brief SLLI16 (SIMD 16-bit Shift Left Logical Immediate) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * SLLI16 Rd, Rs1, imm4[3:0] + * ~~~ + * + * **Purpose**:\n + * Do 16-bit element logical left shift operations simultaneously. The shift amount is an + * immediate value. + * + * **Description**:\n + * The 16-bit elements in Rs1 are left-shifted logically. The shifted out bits are filled with + * zero and the shift amount is specified by the imm4[3:0] constant. And the results are written to Rd. + * + * **Operations**:\n + * ~~~ + * sa = imm4[3:0]; + * Rd.H[x] = Rs1.H[x] << sa; + * for RV32: x=1...0, + * for RV64: x=3...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned int type of value stored in b + * \return value stored in unsigned long type + */ +#define __RV_SLLI16(a, b) \ + ({ \ + register unsigned long result; \ + register unsigned long __a = (unsigned long)(a); \ + __ASM volatile("slli16 %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b)); \ + result; \ + }) +/* ===== Inline Function End for 3.103. SLLI16 ===== */ + +/* ===== Inline Function Start for 3.104. SMAL ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_64B_ADDSUB + * \brief SMAL (Signed Multiply Halfs & Add 64-bit) + * \details + * **Type**: Partial-SIMD + * + * **Syntax**:\n + * ~~~ + * SMAL Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Multiply the signed bottom 16-bit content of the 32-bit elements of a register with the top + * 16-bit content of the same 32-bit elements of the same register, and add the results with a 64-bit + * value of an even/odd pair of registers (RV32) or a register (RV64). The addition result is written back + * to another even/odd pair of registers (RV32) or a register (RV64). + * + * **RV32 Description**:\n + * This instruction multiplies the bottom 16-bit content of the lower 32-bit of Rs2 with the top 16-bit + * content of the lower 32-bit of Rs2 and adds the result with the 64-bit value of an even/odd pair of + * registers specified by Rs1(4,1). The 64-bit addition result is written back to an even/odd pair of + * registers specified by Rd(4,1). The 16-bit values of Rs2, and the 64-bit value of the Rs1(4,1) register- + * pair are treated as signed integers. + * Rx(4,1), i.e., d, determines the even/odd pair group of the two registers. Specifically, the register pair + * includes register 2d and 2d+1. + * The odd `2d+1` register of the pair contains the high 32-bit of the operand and the even `2d` + * register of the pair contains the low 32-bit of the operand. + * + * **RV64 Description**:\n + * This instruction multiplies the bottom 16-bit content of the 32-bit elements of Rs2 with the top 16-bit + * content of the same 32-bit elements of Rs2 and adds the results with the 64-bit value of Rs1. The 64- + * bit addition result is written back to Rd. The 16-bit values of Rs2, and the 64-bit value of Rs1 are + * treated as signed integers. + * + * **Operations**:\n + * ~~~ + * RV32: + * Mres[31:0] = Rs2.H[1] * Rs2.H[0]; + * Idx0 = CONCAT(Rs1(4,1),1'b0); Idx1 = CONCAT(Rs1(4,1),1'b1); + + * Idx2 = CONCAT(Rd(4,1),1'b0); Idx3 = CONCAT(Rd(4,1),1'b1); + * R[Idx3].R[Idx2] = R[Idx1].R[Idx0] + SE64(Mres[31:0]); + * RV64: + * Mres[0][31:0] = Rs2.W[0].H[1] * Rs2.W[0].H[0]; + * Mres[1][31:0] = Rs2.W[1].H[1] * Rs2.W[1].H[0]; + * Rd = Rs1 + SE64(Mres[1][31:0]) + SE64(Mres[0][31:0]); + * ~~~ + * + * \param [in] a long long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in long long type + */ +__STATIC_FORCEINLINE long long __RV_SMAL(long long a, unsigned long b) +{ + register long long result; + __ASM volatile("smal %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.104. SMAL ===== */ + +/* ===== Inline Function Start for 3.105.1. SMALBB ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_64B_ADDSUB + * \brief SMALBB (Signed Multiply Bottom Halfs & Add 64-bit) + * \details + * **Type**: DSP (64-bit Profile) + * + * **Syntax**:\n + * ~~~ + * SMALBB Rd, Rs1, Rs2 + * SMALBT Rd, Rs1, Rs2 + * SMALTT Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Multiply the signed 16-bit content of the 32-bit elements of a register with the 16-bit + * content of the corresponding 32-bit elements of another register and add the results with a 64-bit + * value of an even/odd pair of registers (RV32) or a register (RV64). The addition result is written back + * to the register-pair (RV32) or the register (RV64). + * * SMALBB: rt pair + bottom*bottom (all 32-bit elements) + * * SMALBT rt pair + bottom*top (all 32-bit elements) + * * SMALTT rt pair + top*top (all 32-bit elements) + * + * **RV32 Description**:\n + * For the `SMALBB` instruction, it multiplies the bottom 16-bit content of Rs1 with the bottom 16-bit + * content of Rs2. + * For the `SMALBT` instruction, it multiplies the bottom 16-bit content of Rs1 with the top 16-bit + * content of Rs2. + * For the `SMALTT` instruction, it multiplies the top 16-bit content of Rs1 with the top 16-bit content + * of Rs2. + * The multiplication result is added with the 64-bit value of an even/odd pair of registers specified by + * Rd(4,1). The 64-bit addition result is written back to the register-pair. The 16-bit values of Rs1 and + * Rs2, and the 64-bit value of the register-pair are treated as signed integers. + * Rd(4,1), i.e., d, determines the even/odd pair group of the two registers. Specifically, the register pair + * includes register 2d and 2d+1. + * The odd `2d+1` register of the pair contains the high 32-bit of the operand and the even `2d` + * register of the pair contains the low 32-bit of the operand. + * + * **RV64 Description**:\n + * For the `SMALBB` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 + * with the bottom 16-bit content of the 32-bit elements of Rs2. + * For the `SMALBT` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 + * with the top 16-bit content of the 32-bit elements of Rs2. + * For the `SMALTT` instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1 with + * the top 16-bit content of the 32-bit elements of Rs2. + * The multiplication results are added with the 64-bit value of Rd. The 64-bit addition result is written + * back to Rd. The 16-bit values of Rs1 and Rs2, and the 64-bit value of Rd are treated as signed + * integers. + * + * **Operations**:\n + * ~~~ + * RV32: + * Mres[31:0] = Rs1.H[0] * Rs2.H[0]; // SMALBB + * Mres[31:0] = Rs1.H[0] * Rs2.H[1]; // SMALBT + * Mres[31:0] = Rs1.H[1] * Rs2.H[1]; // SMALTT + * Idx0 = CONCAT(Rd(4,1),1'b0); Idx1 = CONCAT(Rd(4,1),1'b1); + * R[Idx1].R[Idx0] = R[Idx1].R[Idx0] + SE64(Mres[31:0]); + * RV64: + * // SMALBB + * Mres[0][31:0] = Rs1.W[0].H[0] * Rs2.W[0].H[0]; + * Mres[1][31:0] = Rs1.W[1].H[0] * Rs2.W[1].H[0]; + * // SMALBT + * Mres[0][31:0] = Rs1.W[0].H[0] * Rs2.W[0].H[1]; + * Mres[1][31:0] = Rs1.W[1].H[0] * Rs2.W[1].H[1]; + * // SMALTT + * Mres[0][31:0] = Rs1.W[0].H[1] * Rs2.W[0].H[1]; + * Mres[1][31:0] = Rs1.W[1].H[1] * Rs2.W[1].H[1]; + * Rd = Rd + SE64(Mres[0][31:0]) + SE64(Mres[1][31:0]); + * ~~~ + * + * \param [in] t long long type of value stored in t + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in long long type + */ +__STATIC_FORCEINLINE long long __RV_SMALBB(long long t, unsigned long a, unsigned long b) +{ + __ASM volatile("smalbb %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); + return t; +} +/* ===== Inline Function End for 3.105.1. SMALBB ===== */ + +/* ===== Inline Function Start for 3.105.2. SMALBT ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_64B_ADDSUB + * \brief SMALBT (Signed Multiply Bottom Half & Top Half & Add 64-bit) + * \details + * **Type**: DSP (64-bit Profile) + * + * **Syntax**:\n + * ~~~ + * SMALBB Rd, Rs1, Rs2 + * SMALBT Rd, Rs1, Rs2 + * SMALTT Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Multiply the signed 16-bit content of the 32-bit elements of a register with the 16-bit + * content of the corresponding 32-bit elements of another register and add the results with a 64-bit + * value of an even/odd pair of registers (RV32) or a register (RV64). The addition result is written back + * to the register-pair (RV32) or the register (RV64). + * * SMALBB: rt pair + bottom*bottom (all 32-bit elements) + * * SMALBT rt pair + bottom*top (all 32-bit elements) + * * SMALTT rt pair + top*top (all 32-bit elements) + * + * **RV32 Description**:\n + * For the `SMALBB` instruction, it multiplies the bottom 16-bit content of Rs1 with the bottom 16-bit + * content of Rs2. + * For the `SMALBT` instruction, it multiplies the bottom 16-bit content of Rs1 with the top 16-bit + * content of Rs2. + * For the `SMALTT` instruction, it multiplies the top 16-bit content of Rs1 with the top 16-bit content + * of Rs2. + * The multiplication result is added with the 64-bit value of an even/odd pair of registers specified by + * Rd(4,1). The 64-bit addition result is written back to the register-pair. The 16-bit values of Rs1 and + * Rs2, and the 64-bit value of the register-pair are treated as signed integers. + * Rd(4,1), i.e., d, determines the even/odd pair group of the two registers. Specifically, the register pair + * includes register 2d and 2d+1. + * The odd `2d+1` register of the pair contains the high 32-bit of the operand and the even `2d` + * register of the pair contains the low 32-bit of the operand. + * + * **RV64 Description**:\n + * For the `SMALBB` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 + * with the bottom 16-bit content of the 32-bit elements of Rs2. + * For the `SMALBT` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 + * with the top 16-bit content of the 32-bit elements of Rs2. + * For the `SMALTT` instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1 with + * the top 16-bit content of the 32-bit elements of Rs2. + * The multiplication results are added with the 64-bit value of Rd. The 64-bit addition result is written + * back to Rd. The 16-bit values of Rs1 and Rs2, and the 64-bit value of Rd are treated as signed + * integers. + * + * **Operations**:\n + * ~~~ + * RV32: + * Mres[31:0] = Rs1.H[0] * Rs2.H[0]; // SMALBB + * Mres[31:0] = Rs1.H[0] * Rs2.H[1]; // SMALBT + * Mres[31:0] = Rs1.H[1] * Rs2.H[1]; // SMALTT + * Idx0 = CONCAT(Rd(4,1),1'b0); Idx1 = CONCAT(Rd(4,1),1'b1); + * R[Idx1].R[Idx0] = R[Idx1].R[Idx0] + SE64(Mres[31:0]); + * RV64: + * // SMALBB + * Mres[0][31:0] = Rs1.W[0].H[0] * Rs2.W[0].H[0]; + * Mres[1][31:0] = Rs1.W[1].H[0] * Rs2.W[1].H[0]; + * // SMALBT + * Mres[0][31:0] = Rs1.W[0].H[0] * Rs2.W[0].H[1]; + * Mres[1][31:0] = Rs1.W[1].H[0] * Rs2.W[1].H[1]; + * // SMALTT + * Mres[0][31:0] = Rs1.W[0].H[1] * Rs2.W[0].H[1]; + * Mres[1][31:0] = Rs1.W[1].H[1] * Rs2.W[1].H[1]; + * Rd = Rd + SE64(Mres[0][31:0]) + SE64(Mres[1][31:0]); + * ~~~ + * + * \param [in] t long long type of value stored in t + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in long long type + */ +__STATIC_FORCEINLINE long long __RV_SMALBT(long long t, unsigned long a, unsigned long b) +{ + __ASM volatile("smalbt %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); + return t; +} +/* ===== Inline Function End for 3.105.2. SMALBT ===== */ + +/* ===== Inline Function Start for 3.105.3. SMALTT ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_64B_ADDSUB + * \brief SMALTT (Signed Multiply Top Halfs & Add 64-bit) + * \details + * **Type**: DSP (64-bit Profile) + * + * **Syntax**:\n + * ~~~ + * SMALBB Rd, Rs1, Rs2 + * SMALBT Rd, Rs1, Rs2 + * SMALTT Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Multiply the signed 16-bit content of the 32-bit elements of a register with the 16-bit + * content of the corresponding 32-bit elements of another register and add the results with a 64-bit + * value of an even/odd pair of registers (RV32) or a register (RV64). The addition result is written back + * to the register-pair (RV32) or the register (RV64). + * * SMALBB: rt pair + bottom*bottom (all 32-bit elements) + * * SMALBT rt pair + bottom*top (all 32-bit elements) + * * SMALTT rt pair + top*top (all 32-bit elements) + * + * **RV32 Description**:\n + * For the `SMALBB` instruction, it multiplies the bottom 16-bit content of Rs1 with the bottom 16-bit + * content of Rs2. + * For the `SMALBT` instruction, it multiplies the bottom 16-bit content of Rs1 with the top 16-bit + * content of Rs2. + * For the `SMALTT` instruction, it multiplies the top 16-bit content of Rs1 with the top 16-bit content + * of Rs2. + * The multiplication result is added with the 64-bit value of an even/odd pair of registers specified by + * Rd(4,1). The 64-bit addition result is written back to the register-pair. The 16-bit values of Rs1 and + * Rs2, and the 64-bit value of the register-pair are treated as signed integers. + * Rd(4,1), i.e., d, determines the even/odd pair group of the two registers. Specifically, the register pair + * includes register 2d and 2d+1. + * The odd `2d+1` register of the pair contains the high 32-bit of the operand and the even `2d` + * register of the pair contains the low 32-bit of the operand. + * + * **RV64 Description**:\n + * For the `SMALBB` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 + * with the bottom 16-bit content of the 32-bit elements of Rs2. + * For the `SMALBT` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 + * with the top 16-bit content of the 32-bit elements of Rs2. + * For the `SMALTT` instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1 with + * the top 16-bit content of the 32-bit elements of Rs2. + * The multiplication results are added with the 64-bit value of Rd. The 64-bit addition result is written + * back to Rd. The 16-bit values of Rs1 and Rs2, and the 64-bit value of Rd are treated as signed + * integers. + * + * **Operations**:\n + * ~~~ + * RV32: + * Mres[31:0] = Rs1.H[0] * Rs2.H[0]; // SMALBB + * Mres[31:0] = Rs1.H[0] * Rs2.H[1]; // SMALBT + * Mres[31:0] = Rs1.H[1] * Rs2.H[1]; // SMALTT + * Idx0 = CONCAT(Rd(4,1),1'b0); Idx1 = CONCAT(Rd(4,1),1'b1); + * R[Idx1].R[Idx0] = R[Idx1].R[Idx0] + SE64(Mres[31:0]); + * RV64: + * // SMALBB + * Mres[0][31:0] = Rs1.W[0].H[0] * Rs2.W[0].H[0]; + * Mres[1][31:0] = Rs1.W[1].H[0] * Rs2.W[1].H[0]; + * // SMALBT + * Mres[0][31:0] = Rs1.W[0].H[0] * Rs2.W[0].H[1]; + * Mres[1][31:0] = Rs1.W[1].H[0] * Rs2.W[1].H[1]; + * // SMALTT + * Mres[0][31:0] = Rs1.W[0].H[1] * Rs2.W[0].H[1]; + * Mres[1][31:0] = Rs1.W[1].H[1] * Rs2.W[1].H[1]; + * Rd = Rd + SE64(Mres[0][31:0]) + SE64(Mres[1][31:0]); + * ~~~ + * + * \param [in] t long long type of value stored in t + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in long long type + */ +__STATIC_FORCEINLINE long long __RV_SMALTT(long long t, unsigned long a, unsigned long b) +{ + __ASM volatile("smaltt %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); + return t; +} +/* ===== Inline Function End for 3.105.3. SMALTT ===== */ + +/* ===== Inline Function Start for 3.106.1. SMALDA ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_64B_ADDSUB + * \brief SMALDA (Signed Multiply Two Halfs and Two Adds 64-bit) + * \details + * **Type**: DSP (64-bit Profile) + * + * **Syntax**:\n + * ~~~ + * SMALDA Rd, Rs1, Rs2 + * SMALXDA Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do two signed 16-bit multiplications from the 32-bit elements of two registers; and then + * adds the two 32-bit results and the 64-bit value of an even/odd pair of registers together. + * * SMALDA: rt pair+ top*top + bottom*bottom (all 32-bit elements) + * * SMALXDA: rt pair+ top*bottom + bottom*top (all 32-bit elements) + * + * **RV32 Description**:\n + * For the `SMALDA` instruction, it multiplies the bottom 16-bit content of Rs1 with the bottom 16-bit + * content of Rs2 and then adds the result to the result of multiplying the top 16-bit content of Rs1 with + * the top 16-bit content of Rs2 with unlimited precision. + * For the `SMALXDA` instruction, it multiplies the top 16-bit content of Rs1 with the bottom 16-bit + * content of Rs2 and then adds the result to the result of multiplying the bottom 16-bit content of Rs1 + * with the top 16-bit content of Rs2 with unlimited precision. + * The result is added to the 64-bit value of an even/odd pair of registers specified by Rd(4,1). The 64- + * bit addition result is written back to the register-pair. The 16-bit values of Rs1 and Rs2, and the 64- + * bit value of the register-pair are treated as signed integers. + * Rd(4,1), i.e., d, determines the even/odd pair group of the two registers. Specifically, the register pair + * includes register 2d and 2d+1. + * The odd `2d+1` register of the pair contains the high 32-bit of the operand and the even `2d` + * register of the pair contains the low 32-bit of the operand. + * + * **RV64 Description**:\n + * For the `SMALDA` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 + * with the bottom 16-bit content of the 32-bit elements of Rs2 and then adds the result to the result of + * multiplying the top 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the 32- + * bit elements of Rs2 with unlimited precision. + * For the `SMALXDA` instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1 + * with the bottom 16-bit content of the 32-bit elements of Rs2 and then adds the result to the result of + * multiplying the bottom 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the + * 32-bit elements of Rs2 with unlimited precision. + * The results are added to the 64-bit value of Rd. The 64-bit addition result is written back to Rd. The + * 16-bit values of Rs1 and Rs2, and the 64-bit value of Rd are treated as signed integers. + * + * **Operations**:\n + * ~~~ + * RV32: + * // SMALDA + * Mres0[31:0] = (Rs1.H[0] * Rs2.H[0]); + * Mres1[31:0] = (Rs1.H[1] * Rs2.H[1]); + * // SMALXDA + * Mres0[31:0] = (Rs1.H[0] * Rs2.H[1]); + * Mres1[31:0] = (Rs1.H[1] * Rs2.H[0]); + * Idx0 = CONCAT(Rd(4,1),1'b0); Idx1 = CONCAT(Rd(4,1),1'b1); + * R[Idx1].R[Idx0] = R[Idx1].R[Idx0] + SE64(Mres0[31:0]) + SE64(Mres1[31:0]); + * RV64: + * // SMALDA + * Mres0[0][31:0] = (Rs1.W[0].H[0] * Rs2.W[0].H[0]); + * Mres1[0][31:0] = (Rs1.W[0].H[1] * Rs2.W[0].H[1]); + * Mres0[1][31:0] = (Rs1.W[1].H[0] * Rs2.W[1].H[0]); + * Mres1[1][31:0] = (Rs1.W[1].H[1] * Rs2.W[1].H[1]); + * // SMALXDA + * Mres0[0][31:0] = (Rs1.W[0].H[0] * Rs2.W[0].H[1]); + * Mres1[0][31:0] = (Rs1.W[0].H[1] * Rs2.W[0].H[0]); + * Mres0[1][31:0] = (Rs1.W[1].H[0] * Rs2.W[1].H[1]); + * Mres1[1][31:0] = (Rs1.W[1].H[1] * Rs2.W[1].H[0]); + * Rd = Rd + SE64(Mres0[0][31:0]) + SE64(Mres1[0][31:0]) + SE64(Mres0[1][31:0]) + + * SE64(Mres1[1][31:0]); + * ~~~ + * + * \param [in] t long long type of value stored in t + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in long long type + */ +__STATIC_FORCEINLINE long long __RV_SMALDA(long long t, unsigned long a, unsigned long b) +{ + __ASM volatile("smalda %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); + return t; +} +/* ===== Inline Function End for 3.106.1. SMALDA ===== */ + +/* ===== Inline Function Start for 3.106.2. SMALXDA ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_64B_ADDSUB + * \brief SMALXDA (Signed Crossed Multiply Two Halfs and Two Adds 64-bit) + * \details + * **Type**: DSP (64-bit Profile) + * + * **Syntax**:\n + * ~~~ + * SMALDA Rd, Rs1, Rs2 + * SMALXDA Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do two signed 16-bit multiplications from the 32-bit elements of two registers; and then + * adds the two 32-bit results and the 64-bit value of an even/odd pair of registers together. + * * SMALDA: rt pair+ top*top + bottom*bottom (all 32-bit elements) + * * SMALXDA: rt pair+ top*bottom + bottom*top (all 32-bit elements) + * + * **RV32 Description**:\n + * For the `SMALDA` instruction, it multiplies the bottom 16-bit content of Rs1 with the bottom 16-bit + * content of Rs2 and then adds the result to the result of multiplying the top 16-bit content of Rs1 with + * the top 16-bit content of Rs2 with unlimited precision. + * For the `SMALXDA` instruction, it multiplies the top 16-bit content of Rs1 with the bottom 16-bit + * content of Rs2 and then adds the result to the result of multiplying the bottom 16-bit content of Rs1 + * with the top 16-bit content of Rs2 with unlimited precision. + * The result is added to the 64-bit value of an even/odd pair of registers specified by Rd(4,1). The 64- + * bit addition result is written back to the register-pair. The 16-bit values of Rs1 and Rs2, and the 64- + * bit value of the register-pair are treated as signed integers. + * Rd(4,1), i.e., d, determines the even/odd pair group of the two registers. Specifically, the register pair + * includes register 2d and 2d+1. + * The odd `2d+1` register of the pair contains the high 32-bit of the operand and the even `2d` + * register of the pair contains the low 32-bit of the operand. + * + * **RV64 Description**:\n + * For the `SMALDA` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 + * with the bottom 16-bit content of the 32-bit elements of Rs2 and then adds the result to the result of + * multiplying the top 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the 32- + * bit elements of Rs2 with unlimited precision. + * For the `SMALXDA` instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1 + * with the bottom 16-bit content of the 32-bit elements of Rs2 and then adds the result to the result of + * multiplying the bottom 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the + * 32-bit elements of Rs2 with unlimited precision. + * The results are added to the 64-bit value of Rd. The 64-bit addition result is written back to Rd. The + * 16-bit values of Rs1 and Rs2, and the 64-bit value of Rd are treated as signed integers. + * + * **Operations**:\n + * ~~~ + * RV32: + * // SMALDA + * Mres0[31:0] = (Rs1.H[0] * Rs2.H[0]); + * Mres1[31:0] = (Rs1.H[1] * Rs2.H[1]); + * // SMALXDA + * Mres0[31:0] = (Rs1.H[0] * Rs2.H[1]); + * Mres1[31:0] = (Rs1.H[1] * Rs2.H[0]); + * Idx0 = CONCAT(Rd(4,1),1'b0); Idx1 = CONCAT(Rd(4,1),1'b1); + * R[Idx1].R[Idx0] = R[Idx1].R[Idx0] + SE64(Mres0[31:0]) + SE64(Mres1[31:0]); + * RV64: + * // SMALDA + * Mres0[0][31:0] = (Rs1.W[0].H[0] * Rs2.W[0].H[0]); + * Mres1[0][31:0] = (Rs1.W[0].H[1] * Rs2.W[0].H[1]); + * Mres0[1][31:0] = (Rs1.W[1].H[0] * Rs2.W[1].H[0]); + * Mres1[1][31:0] = (Rs1.W[1].H[1] * Rs2.W[1].H[1]); + * // SMALXDA + * Mres0[0][31:0] = (Rs1.W[0].H[0] * Rs2.W[0].H[1]); + * Mres1[0][31:0] = (Rs1.W[0].H[1] * Rs2.W[0].H[0]); + * Mres0[1][31:0] = (Rs1.W[1].H[0] * Rs2.W[1].H[1]); + * Mres1[1][31:0] = (Rs1.W[1].H[1] * Rs2.W[1].H[0]); + * Rd = Rd + SE64(Mres0[0][31:0]) + SE64(Mres1[0][31:0]) + SE64(Mres0[1][31:0]) + + * SE64(Mres1[1][31:0]); + * ~~~ + * + * \param [in] t long long type of value stored in t + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in long long type + */ +__STATIC_FORCEINLINE long long __RV_SMALXDA(long long t, unsigned long a, unsigned long b) +{ + __ASM volatile("smalxda %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); + return t; +} +/* ===== Inline Function End for 3.106.2. SMALXDA ===== */ + +/* ===== Inline Function Start for 3.107.1. SMALDS ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_64B_ADDSUB + * \brief SMALDS (Signed Multiply Two Halfs & Subtract & Add 64-bit) + * \details + * **Type**: DSP (64-bit Profile) + * + * **Syntax**:\n + * ~~~ + * SMALDS Rd, Rs1, Rs2 + * SMALDRS Rd, Rs1, Rs2 + * SMALXDS Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do two signed 16-bit multiplications from the 32-bit elements of two registers; and then + * perform a subtraction operation between the two 32-bit results. Then add the subtraction result to + * the 64-bit value of an even/odd pair of registers (RV32) or a register (RV64). The addition result is + * written back to the register-pair. + * * SMALDS: rt pair + (top*top - bottom*bottom) (all 32-bit elements) + * * SMALDRS: rt pair + (bottom*bottom - top*top) (all 32-bit elements) + * * SMALXDS: rt pair + (top*bottom - bottom*top) (all 32-bit elements) + * + * **RV32 Description**:\n + * For the `SMALDS` instruction, it multiplies the bottom 16-bit content of Rs1 with the bottom 16-bit + * content of Rs2 and then subtracts the result from the result of multiplying the top 16-bit content of + * Rs1 with the top 16-bit content of Rs2. + * For the `SMALDRS` instruction, it multiplies the top 16-bit content of Rs1 with the top 16-bit content + * of Rs2 and then subtracts the result from the result of multiplying the bottom 16-bit content of Rs1 + * with the bottom 16-bit content of Rs2. + * For the `SMALXDS` instruction, it multiplies the bottom 16-bit content of Rs1 with the top 16-bit + * content of Rs2 and then subtracts the result from the result of multiplying the top 16-bit content of + * Rs1 with the bottom 16-bit content of Rs2. + * The subtraction result is then added to the 64-bit value of an even/odd pair of registers specified by + * Rd(4,1). The 64-bit addition result is written back to the register-pair. The 16-bit values of Rs1 and + * Rs2, and the 64-bit value of the register-pair are treated as signed integers. + * Rd(4,1), i.e., d, determines the even/odd pair group of the two registers. Specifically, the register pair + * includes register 2d and 2d+1. + * The odd `2d+1` register of the pair contains the high 32-bit of the operand and the even `2d` + * register of the pair contains the low 32-bit of the operand. + * + * **RV64 Description**:\n + * For the `SMALDS` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 + * with the bottom 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the + * result of multiplying the top 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content + * of the 32-bit elements of Rs2. + * For the `SMALDRS` instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1 with + * the top 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the result of + * multiplying the bottom 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit content of + * the 32-bit elements of Rs2. + * For the `SMALXDS` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 + * with the top 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the + * result of multiplying the top 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit + * content of the 32-bit elements of Rs2. + * The subtraction results are then added to the 64-bit value of Rd. The 64-bit addition result is written + * back to Rd. The 16-bit values of Rs1 and Rs2, and the 64-bit value of Rd are treated as signed + * integers. + * + * **Operations**:\n + * ~~~ + * * RV32: + * Mres[31:0] = (Rs1.H[1] * Rs2.H[1]) - (Rs1.H[0] * Rs2.H[0]); // SMALDS + * Mres[31:0] = (Rs1.H[0] * Rs2.H[0]) - (Rs1.H[1] * Rs2.H[1]); // SMALDRS + * Mres[31:0] = (Rs1.H[1] * Rs2.H[0]) - (Rs1.H[0] * Rs2.H[1]); // SMALXDS + * Idx0 = CONCAT(Rd(4,1),1'b0); Idx1 = CONCAT(Rd(4,1),1'b1); + * R[Idx1].R[Idx0] = R[Idx1].R[Idx0] + SE64(Mres[31:0]); + * * RV64: + * // SMALDS + * Mres[0][31:0] = (Rs1.W[0].H[1] * Rs2.W[0].H[1]) - (Rs1.W[0].H[0] * Rs2.W[0].H[0]); + * Mres[1][31:0] = (Rs1.W[1].H[1] * Rs2.W[0].H[1]) - (Rs1.W[1].H[0] * Rs2.W[1].H[0]); + * // SMALDRS + * Mres[0][31:0] = (Rs1.W[0].H[0] * Rs2.W[0].H[0]) - (Rs1.W[0].H[1] * Rs2.W[0].H[1]); + * Mres[1][31:0] = (Rs1.W[1].H[0] * Rs2.W[0].H[0]) - (Rs1.W[1].H[1] * Rs2.W[1].H[1]); + * // SMALXDS + * Mres[0][31:0] = (Rs1.W[0].H[1] * Rs2.W[0].H[0]) - (Rs1.W[0].H[0] * Rs2.W[0].H[1]); + * Mres[1][31:0] = (Rs1.W[1].H[1] * Rs2.W[0].H[0]) - (Rs1.W[1].H[0] * Rs2.W[1].H[1]); + * Rd = Rd + SE64(Mres[0][31:0]) + SE64(Mres[1][31:0]); + * ~~~ + * + * \param [in] t long long type of value stored in t + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in long long type + */ +__STATIC_FORCEINLINE long long __RV_SMALDS(long long t, unsigned long a, unsigned long b) +{ + __ASM volatile("smalds %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); + return t; +} +/* ===== Inline Function End for 3.107.1. SMALDS ===== */ + +/* ===== Inline Function Start for 3.107.2. SMALDRS ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_64B_ADDSUB + * \brief SMALDRS (Signed Multiply Two Halfs & Reverse Subtract & Add 64- bit) + * \details + * **Type**: DSP (64-bit Profile) + * + * **Syntax**:\n + * ~~~ + * SMALDS Rd, Rs1, Rs2 + * SMALDRS Rd, Rs1, Rs2 + * SMALXDS Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do two signed 16-bit multiplications from the 32-bit elements of two registers; and then + * perform a subtraction operation between the two 32-bit results. Then add the subtraction result to + * the 64-bit value of an even/odd pair of registers (RV32) or a register (RV64). The addition result is + * written back to the register-pair. + * * SMALDS: rt pair + (top*top - bottom*bottom) (all 32-bit elements) + * * SMALDRS: rt pair + (bottom*bottom - top*top) (all 32-bit elements) + * * SMALXDS: rt pair + (top*bottom - bottom*top) (all 32-bit elements) + * + * **RV32 Description**:\n + * For the `SMALDS` instruction, it multiplies the bottom 16-bit content of Rs1 with the bottom 16-bit + * content of Rs2 and then subtracts the result from the result of multiplying the top 16-bit content of + * Rs1 with the top 16-bit content of Rs2. + * For the `SMALDRS` instruction, it multiplies the top 16-bit content of Rs1 with the top 16-bit content + * of Rs2 and then subtracts the result from the result of multiplying the bottom 16-bit content of Rs1 + * with the bottom 16-bit content of Rs2. + * For the `SMALXDS` instruction, it multiplies the bottom 16-bit content of Rs1 with the top 16-bit + * content of Rs2 and then subtracts the result from the result of multiplying the top 16-bit content of + * Rs1 with the bottom 16-bit content of Rs2. + * The subtraction result is then added to the 64-bit value of an even/odd pair of registers specified by + * Rd(4,1). The 64-bit addition result is written back to the register-pair. The 16-bit values of Rs1 and + * Rs2, and the 64-bit value of the register-pair are treated as signed integers. + * Rd(4,1), i.e., d, determines the even/odd pair group of the two registers. Specifically, the register pair + * includes register 2d and 2d+1. + * The odd `2d+1` register of the pair contains the high 32-bit of the operand and the even `2d` + * register of the pair contains the low 32-bit of the operand. + * + * **RV64 Description**:\n + * For the `SMALDS` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 + * with the bottom 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the + * result of multiplying the top 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content + * of the 32-bit elements of Rs2. + * For the `SMALDRS` instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1 with + * the top 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the result of + * multiplying the bottom 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit content of + * the 32-bit elements of Rs2. + * For the `SMALXDS` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 + * with the top 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the + * result of multiplying the top 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit + * content of the 32-bit elements of Rs2. + * The subtraction results are then added to the 64-bit value of Rd. The 64-bit addition result is written + * back to Rd. The 16-bit values of Rs1 and Rs2, and the 64-bit value of Rd are treated as signed + * integers. + * + * **Operations**:\n + * ~~~ + * * RV32: + * Mres[31:0] = (Rs1.H[1] * Rs2.H[1]) - (Rs1.H[0] * Rs2.H[0]); // SMALDS + * Mres[31:0] = (Rs1.H[0] * Rs2.H[0]) - (Rs1.H[1] * Rs2.H[1]); // SMALDRS + * Mres[31:0] = (Rs1.H[1] * Rs2.H[0]) - (Rs1.H[0] * Rs2.H[1]); // SMALXDS + * Idx0 = CONCAT(Rd(4,1),1'b0); Idx1 = CONCAT(Rd(4,1),1'b1); + * R[Idx1].R[Idx0] = R[Idx1].R[Idx0] + SE64(Mres[31:0]); + * * RV64: + * // SMALDS + * Mres[0][31:0] = (Rs1.W[0].H[1] * Rs2.W[0].H[1]) - (Rs1.W[0].H[0] * Rs2.W[0].H[0]); + * Mres[1][31:0] = (Rs1.W[1].H[1] * Rs2.W[0].H[1]) - (Rs1.W[1].H[0] * Rs2.W[1].H[0]); + * // SMALDRS + * Mres[0][31:0] = (Rs1.W[0].H[0] * Rs2.W[0].H[0]) - (Rs1.W[0].H[1] * Rs2.W[0].H[1]); + * Mres[1][31:0] = (Rs1.W[1].H[0] * Rs2.W[0].H[0]) - (Rs1.W[1].H[1] * Rs2.W[1].H[1]); + * // SMALXDS + * Mres[0][31:0] = (Rs1.W[0].H[1] * Rs2.W[0].H[0]) - (Rs1.W[0].H[0] * Rs2.W[0].H[1]); + * Mres[1][31:0] = (Rs1.W[1].H[1] * Rs2.W[0].H[0]) - (Rs1.W[1].H[0] * Rs2.W[1].H[1]); + * Rd = Rd + SE64(Mres[0][31:0]) + SE64(Mres[1][31:0]); + * ~~~ + * + * \param [in] t long long type of value stored in t + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in long long type + */ +__STATIC_FORCEINLINE long long __RV_SMALDRS(long long t, unsigned long a, unsigned long b) +{ + __ASM volatile("smaldrs %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); + return t; +} +/* ===== Inline Function End for 3.107.2. SMALDRS ===== */ + +/* ===== Inline Function Start for 3.107.3. SMALXDS ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_64B_ADDSUB + * \brief SMALXDS (Signed Crossed Multiply Two Halfs & Subtract & Add 64- bit) + * \details + * **Type**: DSP (64-bit Profile) + * + * **Syntax**:\n + * ~~~ + * SMALDS Rd, Rs1, Rs2 + * SMALDRS Rd, Rs1, Rs2 + * SMALXDS Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do two signed 16-bit multiplications from the 32-bit elements of two registers; and then + * perform a subtraction operation between the two 32-bit results. Then add the subtraction result to + * the 64-bit value of an even/odd pair of registers (RV32) or a register (RV64). The addition result is + * written back to the register-pair. + * * SMALDS: rt pair + (top*top - bottom*bottom) (all 32-bit elements) + * * SMALDRS: rt pair + (bottom*bottom - top*top) (all 32-bit elements) + * * SMALXDS: rt pair + (top*bottom - bottom*top) (all 32-bit elements) + * + * **RV32 Description**:\n + * For the `SMALDS` instruction, it multiplies the bottom 16-bit content of Rs1 with the bottom 16-bit + * content of Rs2 and then subtracts the result from the result of multiplying the top 16-bit content of + * Rs1 with the top 16-bit content of Rs2. + * For the `SMALDRS` instruction, it multiplies the top 16-bit content of Rs1 with the top 16-bit content + * of Rs2 and then subtracts the result from the result of multiplying the bottom 16-bit content of Rs1 + * with the bottom 16-bit content of Rs2. + * For the `SMALXDS` instruction, it multiplies the bottom 16-bit content of Rs1 with the top 16-bit + * content of Rs2 and then subtracts the result from the result of multiplying the top 16-bit content of + * Rs1 with the bottom 16-bit content of Rs2. + * The subtraction result is then added to the 64-bit value of an even/odd pair of registers specified by + * Rd(4,1). The 64-bit addition result is written back to the register-pair. The 16-bit values of Rs1 and + * Rs2, and the 64-bit value of the register-pair are treated as signed integers. + * Rd(4,1), i.e., d, determines the even/odd pair group of the two registers. Specifically, the register pair + * includes register 2d and 2d+1. + * The odd `2d+1` register of the pair contains the high 32-bit of the operand and the even `2d` + * register of the pair contains the low 32-bit of the operand. + * + * **RV64 Description**:\n + * For the `SMALDS` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 + * with the bottom 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the + * result of multiplying the top 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content + * of the 32-bit elements of Rs2. + * For the `SMALDRS` instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1 with + * the top 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the result of + * multiplying the bottom 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit content of + * the 32-bit elements of Rs2. + * For the `SMALXDS` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 + * with the top 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the + * result of multiplying the top 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit + * content of the 32-bit elements of Rs2. + * The subtraction results are then added to the 64-bit value of Rd. The 64-bit addition result is written + * back to Rd. The 16-bit values of Rs1 and Rs2, and the 64-bit value of Rd are treated as signed + * integers. + * + * **Operations**:\n + * ~~~ + * * RV32: + * Mres[31:0] = (Rs1.H[1] * Rs2.H[1]) - (Rs1.H[0] * Rs2.H[0]); // SMALDS + * Mres[31:0] = (Rs1.H[0] * Rs2.H[0]) - (Rs1.H[1] * Rs2.H[1]); // SMALDRS + * Mres[31:0] = (Rs1.H[1] * Rs2.H[0]) - (Rs1.H[0] * Rs2.H[1]); // SMALXDS + * Idx0 = CONCAT(Rd(4,1),1'b0); Idx1 = CONCAT(Rd(4,1),1'b1); + * R[Idx1].R[Idx0] = R[Idx1].R[Idx0] + SE64(Mres[31:0]); + * * RV64: + * // SMALDS + * Mres[0][31:0] = (Rs1.W[0].H[1] * Rs2.W[0].H[1]) - (Rs1.W[0].H[0] * Rs2.W[0].H[0]); + * Mres[1][31:0] = (Rs1.W[1].H[1] * Rs2.W[0].H[1]) - (Rs1.W[1].H[0] * Rs2.W[1].H[0]); + * // SMALDRS + * Mres[0][31:0] = (Rs1.W[0].H[0] * Rs2.W[0].H[0]) - (Rs1.W[0].H[1] * Rs2.W[0].H[1]); + * Mres[1][31:0] = (Rs1.W[1].H[0] * Rs2.W[0].H[0]) - (Rs1.W[1].H[1] * Rs2.W[1].H[1]); + * // SMALXDS + * Mres[0][31:0] = (Rs1.W[0].H[1] * Rs2.W[0].H[0]) - (Rs1.W[0].H[0] * Rs2.W[0].H[1]); + * Mres[1][31:0] = (Rs1.W[1].H[1] * Rs2.W[0].H[0]) - (Rs1.W[1].H[0] * Rs2.W[1].H[1]); + * Rd = Rd + SE64(Mres[0][31:0]) + SE64(Mres[1][31:0]); + * ~~~ + * + * \param [in] t long long type of value stored in t + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in long long type + */ +__STATIC_FORCEINLINE long long __RV_SMALXDS(long long t, unsigned long a, unsigned long b) +{ + __ASM volatile("smalxds %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); + return t; +} +/* ===== Inline Function End for 3.107.3. SMALXDS ===== */ + +/* ===== Inline Function Start for 3.108. SMAR64 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_32B_MULT_64B_ADDSUB + * \brief SMAR64 (Signed Multiply and Add to 64-Bit Data) + * \details + * **Type**: DSP (64-bit Profile) + * + * **Syntax**:\n + * ~~~ + * SMAR64 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Multiply the 32-bit signed elements in two registers and add the 64-bit multiplication + * result to the 64-bit signed data of a pair of registers (RV32) or a register (RV64). The result is written + * back to the pair of registers (RV32) or a register (RV64). + * + * **RV32 Description**:\n + * This instruction multiplies the 32-bit signed data of Rs1 with that of Rs2. It adds + * the 64-bit multiplication result to the 64-bit signed data of an even/odd pair of registers specified by + * Rd(4,1). The addition result is written back to the even/odd pair of registers specified by Rd(4,1). + * Rx(4,1), i.e., d, determines the even/odd pair group of two registers. Specifically, the register pair + * includes register 2d and 2d+1. + * The odd `2d+1` register of the pair contains the high 32-bit of the result and the even `2d` register + * of the pair contains the low 32-bit of the result. + * + * **RV64 Description**:\n + * This instruction multiplies the 32-bit signed elements of Rs1 with that of Rs2. It + * adds the 64-bit multiplication results to the 64-bit signed data of Rd. The addition result is written + * back to Rd. + * + * **Operations**:\n + * ~~~ + * * RV32: + * t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1); + * R[t_H].R[t_L] = R[t_H].R[t_L] + (Rs1 * Rs2); + * * RV64: + * Rd = Rd + (Rs1.W[0] * Rs2.W[0]) + (Rs1.W[1] * Rs2.W[1]); + * ~~~ + * + * \param [in] t long long type of value stored in t + * \param [in] a long type of value stored in a + * \param [in] b long type of value stored in b + * \return value stored in long long type + */ +__STATIC_FORCEINLINE long long __RV_SMAR64(long long t, long a, long b) +{ + __ASM volatile("smar64 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); + return t; +} +/* ===== Inline Function End for 3.108. SMAR64 ===== */ + +/* ===== Inline Function Start for 3.109. SMAQA ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_8B_MULT_32B_ADD + * \brief SMAQA (Signed Multiply Four Bytes with 32-bit Adds) + * \details + * **Type**: Partial-SIMD (Reduction) + * + * **Syntax**:\n + * ~~~ + * SMAQA Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do four signed 8-bit multiplications from 32-bit chunks of two registers; and then adds + * the four 16-bit results and the content of corresponding 32-bit chunks of a third register together. + * + * **Description**:\n + * This instruction multiplies the four signed 8-bit elements of 32-bit chunks of Rs1 with the four + * signed 8-bit elements of 32-bit chunks of Rs2 and then adds the four results together with the signed + * content of the corresponding 32-bit chunks of Rd. The final results are written back to the + * corresponding 32-bit chunks in Rd. + * + * **Operations**:\n + * ~~~ + * res[x] = Rd.W[x] + + * (Rs1.W[x].B[3] s* Rs2.W[x].B[3]) + (Rs1.W[x].B[2] s* Rs2.W[x].B[2]) + + * (Rs1.W[x].B[1] s* Rs2.W[x].B[1]) + (Rs1.W[x].B[0] s* Rs2.W[x].B[0]); + * Rd.W[x] = res[x]; + * for RV32: x=0, + * for RV64: x=1,0 + * ~~~ + * + * \param [in] t long type of value stored in t + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_SMAQA(long t, unsigned long a, unsigned long b) +{ + __ASM volatile("smaqa %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); + return t; +} +/* ===== Inline Function End for 3.109. SMAQA ===== */ + +/* ===== Inline Function Start for 3.110. SMAQA.SU ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_8B_MULT_32B_ADD + * \brief SMAQA.SU (Signed and Unsigned Multiply Four Bytes with 32-bit Adds) + * \details + * **Type**: Partial-SIMD (Reduction) + * + * **Syntax**:\n + * ~~~ + * SMAQA.SU Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do four `signed x unsigned` 8-bit multiplications from 32-bit chunks of two registers; and + * then adds the four 16-bit results and the content of corresponding 32-bit chunks of a third register + * together. + * + * **Description**:\n + * This instruction multiplies the four signed 8-bit elements of 32-bit chunks of Rs1 with the four + * unsigned 8-bit elements of 32-bit chunks of Rs2 and then adds the four results together with the + * signed content of the corresponding 32-bit chunks of Rd. The final results are written back to the + * corresponding 32-bit chunks in Rd. + * + * **Operations**:\n + * ~~~ + * res[x] = Rd.W[x] + + * (Rs1.W[x].B[3] su* Rs2.W[x].B[3]) + (Rs1.W[x].B[2] su* Rs2.W[x].B[2]) + + * (Rs1.W[x].B[1] su* Rs2.W[x].B[1]) + (Rs1.W[x].B[0] su* Rs2.W[x].B[0]); + * Rd.W[x] = res[x]; + * for RV32: x=0, + * for RV64: x=1...0 + * ~~~ + * + * \param [in] t long type of value stored in t + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_SMAQA_SU(long t, unsigned long a, unsigned long b) +{ + __ASM volatile("smaqa.su %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); + return t; +} +/* ===== Inline Function End for 3.110. SMAQA.SU ===== */ + +/* ===== Inline Function Start for 3.111. SMAX8 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_MISC + * \brief SMAX8 (SIMD 8-bit Signed Maximum) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * SMAX8 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 8-bit signed integer elements finding maximum operations simultaneously. + * + * **Description**:\n + * This instruction compares the 8-bit signed integer elements in Rs1 with the 8-bit + * signed integer elements in Rs2 and selects the numbers that is greater than the other one. The + * selected results are written to Rd. + * + * **Operations**:\n + * ~~~ + * Rd.B[x] = (Rs1.B[x] > Rs2.B[x])? Rs1.B[x] : Rs2.B[x]; + * for RV32: x=3...0, + * for RV64: x=7...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_SMAX8(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("smax8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.111. SMAX8 ===== */ + +/* ===== Inline Function Start for 3.112. SMAX16 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_MISC + * \brief SMAX16 (SIMD 16-bit Signed Maximum) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * SMAX16 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 16-bit signed integer elements finding maximum operations simultaneously. + * + * **Description**:\n + * This instruction compares the 16-bit signed integer elements in Rs1 with the 16-bit + * signed integer elements in Rs2 and selects the numbers that is greater than the other one. The + * selected results are written to Rd. + * + * **Operations**:\n + * ~~~ + * Rd.H[x] = (Rs1.H[x] > Rs2.H[x])? Rs1.H[x] : Rs2.H[x]; + * for RV32: x=1...0, + * for RV64: x=3...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_SMAX16(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("smax16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.112. SMAX16 ===== */ + +/* ===== Inline Function Start for 3.113.1. SMBB16 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_32B_ADDSUB + * \brief SMBB16 (SIMD Signed Multiply Bottom Half & Bottom Half) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * SMBB16 Rd, Rs1, Rs2 + * SMBT16 Rd, Rs1, Rs2 + * SMTT16 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Multiply the signed 16-bit content of the 32-bit elements of a register with the signed 16- + * bit content of the 32-bit elements of another register and write the result to a third register. + * * SMBB16: W[x].bottom*W[x].bottom + * * SMBT16: W[x].bottom *W[x].top + * * SMTT16: W[x].top * W[x].top + * + * **Description**:\n + * For the `SMBB16` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 + * with the bottom 16-bit content of the 32-bit elements of Rs2. + * For the `SMBT16` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 + * with the top 16-bit content of the 32-bit elements of Rs2. + * For the `SMTT16` instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1 with + * the top 16-bit content of the 32-bit elements of Rs2. + * The multiplication results are written to Rd. The 16-bit contents of Rs1 and Rs2 are treated as signed + * integers. + * + * **Operations**:\n + * ~~~ + * Rd.W[x] = Rs1.W[x].H[0] * Rs2.W[x].H[0]; // SMBB16 + * Rd.W[x] = Rs1.W[x].H[0] * Rs2.W[x].H[1]; // SMBT16 + * Rd.W[x] = Rs1.W[x].H[1] * Rs2.W[x].H[1]; // SMTT16 + * for RV32: x=0, + * for RV64: x=1...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_SMBB16(unsigned long a, unsigned long b) +{ + register long result; + __ASM volatile("smbb16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.113.1. SMBB16 ===== */ + +/* ===== Inline Function Start for 3.113.2. SMBT16 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_32B_ADDSUB + * \brief SMBT16 (SIMD Signed Multiply Bottom Half & Top Half) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * SMBB16 Rd, Rs1, Rs2 + * SMBT16 Rd, Rs1, Rs2 + * SMTT16 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Multiply the signed 16-bit content of the 32-bit elements of a register with the signed 16- + * bit content of the 32-bit elements of another register and write the result to a third register. + * * SMBB16: W[x].bottom*W[x].bottom + * * SMBT16: W[x].bottom *W[x].top + * * SMTT16: W[x].top * W[x].top + * + * **Description**:\n + * For the `SMBB16` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 + * with the bottom 16-bit content of the 32-bit elements of Rs2. + * For the `SMBT16` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 + * with the top 16-bit content of the 32-bit elements of Rs2. + * For the `SMTT16` instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1 with + * the top 16-bit content of the 32-bit elements of Rs2. + * The multiplication results are written to Rd. The 16-bit contents of Rs1 and Rs2 are treated as signed + * integers. + * + * **Operations**:\n + * ~~~ + * Rd.W[x] = Rs1.W[x].H[0] * Rs2.W[x].H[0]; // SMBB16 + * Rd.W[x] = Rs1.W[x].H[0] * Rs2.W[x].H[1]; // SMBT16 + * Rd.W[x] = Rs1.W[x].H[1] * Rs2.W[x].H[1]; // SMTT16 + * for RV32: x=0, + * for RV64: x=1...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_SMBT16(unsigned long a, unsigned long b) +{ + register long result; + __ASM volatile("smbt16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.113.2. SMBT16 ===== */ + +/* ===== Inline Function Start for 3.113.3. SMTT16 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_32B_ADDSUB + * \brief SMTT16 (SIMD Signed Multiply Top Half & Top Half) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * SMBB16 Rd, Rs1, Rs2 + * SMBT16 Rd, Rs1, Rs2 + * SMTT16 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Multiply the signed 16-bit content of the 32-bit elements of a register with the signed 16- + * bit content of the 32-bit elements of another register and write the result to a third register. + * * SMBB16: W[x].bottom*W[x].bottom + * * SMBT16: W[x].bottom *W[x].top + * * SMTT16: W[x].top * W[x].top + * + * **Description**:\n + * For the `SMBB16` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 + * with the bottom 16-bit content of the 32-bit elements of Rs2. + * For the `SMBT16` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 + * with the top 16-bit content of the 32-bit elements of Rs2. + * For the `SMTT16` instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1 with + * the top 16-bit content of the 32-bit elements of Rs2. + * The multiplication results are written to Rd. The 16-bit contents of Rs1 and Rs2 are treated as signed + * integers. + * + * **Operations**:\n + * ~~~ + * Rd.W[x] = Rs1.W[x].H[0] * Rs2.W[x].H[0]; // SMBB16 + * Rd.W[x] = Rs1.W[x].H[0] * Rs2.W[x].H[1]; // SMBT16 + * Rd.W[x] = Rs1.W[x].H[1] * Rs2.W[x].H[1]; // SMTT16 + * for RV32: x=0, + * for RV64: x=1...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_SMTT16(unsigned long a, unsigned long b) +{ + register long result; + __ASM volatile("smtt16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.113.3. SMTT16 ===== */ + +/* ===== Inline Function Start for 3.114.1. SMDS ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_32B_ADDSUB + * \brief SMDS (SIMD Signed Multiply Two Halfs and Subtract) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * SMDS Rd, Rs1, Rs2 + * SMDRS Rd, Rs1, Rs2 + * SMXDS Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do two signed 16-bit multiplications from the 32-bit elements of two registers; and then + * perform a subtraction operation between the two 32-bit results. + * * SMDS: top*top - bottom*bottom (per 32-bit element) + * * SMDRS: bottom*bottom - top*top (per 32-bit element) + * * SMXDS: top*bottom - bottom*top (per 32-bit element) + * + * **Description**:\n + * For the `SMDS` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 with + * the bottom 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the result + * of multiplying the top 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the + * 32-bit elements of Rs2. + * For the `SMDRS` instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1 with + * the top 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the result of + * multiplying the bottom 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit content of + * the 32-bit elements of Rs2. + * For the `SMXDS` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 + * with the top 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the + * result of multiplying the top 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit + * content of the 32-bit elements of Rs2. + * The subtraction result is written to the corresponding 32-bit element of Rd. The 16-bit contents of + * multiplication are treated as signed integers. + * + * **Operations**:\n + * ~~~ + * * SMDS: + * Rd.W[x] = (Rs1.W[x].H[1] * Rs2.W[x].H[1]) - (Rs1.W[x].H[0] * Rs2.W[x].H[0]); + * * SMDRS: + * Rd.W[x] = (Rs1.W[x].H[0] * Rs2.W[x].H[0]) - (Rs1.W[x].H[1] * Rs2.W[x].H[1]); + * * SMXDS: + * Rd.W[x] = (Rs1.W[x].H[1] * Rs2.W[x].H[0]) - (Rs1.W[x].H[0] * Rs2.W[x].H[1]); + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_SMDS(unsigned long a, unsigned long b) +{ + register long result; + __ASM volatile("smds %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.114.1. SMDS ===== */ + +/* ===== Inline Function Start for 3.114.2. SMDRS ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_32B_ADDSUB + * \brief SMDRS (SIMD Signed Multiply Two Halfs and Reverse Subtract) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * SMDS Rd, Rs1, Rs2 + * SMDRS Rd, Rs1, Rs2 + * SMXDS Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do two signed 16-bit multiplications from the 32-bit elements of two registers; and then + * perform a subtraction operation between the two 32-bit results. + * * SMDS: top*top - bottom*bottom (per 32-bit element) + * * SMDRS: bottom*bottom - top*top (per 32-bit element) + * * SMXDS: top*bottom - bottom*top (per 32-bit element) + * + * **Description**:\n + * For the `SMDS` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 with + * the bottom 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the result + * of multiplying the top 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the + * 32-bit elements of Rs2. + * For the `SMDRS` instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1 with + * the top 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the result of + * multiplying the bottom 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit content of + * the 32-bit elements of Rs2. + * For the `SMXDS` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 + * with the top 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the + * result of multiplying the top 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit + * content of the 32-bit elements of Rs2. + * The subtraction result is written to the corresponding 32-bit element of Rd. The 16-bit contents of + * multiplication are treated as signed integers. + * + * **Operations**:\n + * ~~~ + * * SMDS: + * Rd.W[x] = (Rs1.W[x].H[1] * Rs2.W[x].H[1]) - (Rs1.W[x].H[0] * Rs2.W[x].H[0]); + * * SMDRS: + * Rd.W[x] = (Rs1.W[x].H[0] * Rs2.W[x].H[0]) - (Rs1.W[x].H[1] * Rs2.W[x].H[1]); + * * SMXDS: + * Rd.W[x] = (Rs1.W[x].H[1] * Rs2.W[x].H[0]) - (Rs1.W[x].H[0] * Rs2.W[x].H[1]); + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_SMDRS(unsigned long a, unsigned long b) +{ + register long result; + __ASM volatile("smdrs %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.114.2. SMDRS ===== */ + +/* ===== Inline Function Start for 3.114.3. SMXDS ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_32B_ADDSUB + * \brief SMXDS (SIMD Signed Crossed Multiply Two Halfs and Subtract) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * SMDS Rd, Rs1, Rs2 + * SMDRS Rd, Rs1, Rs2 + * SMXDS Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do two signed 16-bit multiplications from the 32-bit elements of two registers; and then + * perform a subtraction operation between the two 32-bit results. + * * SMDS: top*top - bottom*bottom (per 32-bit element) + * * SMDRS: bottom*bottom - top*top (per 32-bit element) + * * SMXDS: top*bottom - bottom*top (per 32-bit element) + * + * **Description**:\n + * For the `SMDS` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 with + * the bottom 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the result + * of multiplying the top 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the + * 32-bit elements of Rs2. + * For the `SMDRS` instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1 with + * the top 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the result of + * multiplying the bottom 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit content of + * the 32-bit elements of Rs2. + * For the `SMXDS` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 + * with the top 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the + * result of multiplying the top 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit + * content of the 32-bit elements of Rs2. + * The subtraction result is written to the corresponding 32-bit element of Rd. The 16-bit contents of + * multiplication are treated as signed integers. + * + * **Operations**:\n + * ~~~ + * * SMDS: + * Rd.W[x] = (Rs1.W[x].H[1] * Rs2.W[x].H[1]) - (Rs1.W[x].H[0] * Rs2.W[x].H[0]); + * * SMDRS: + * Rd.W[x] = (Rs1.W[x].H[0] * Rs2.W[x].H[0]) - (Rs1.W[x].H[1] * Rs2.W[x].H[1]); + * * SMXDS: + * Rd.W[x] = (Rs1.W[x].H[1] * Rs2.W[x].H[0]) - (Rs1.W[x].H[0] * Rs2.W[x].H[1]); + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_SMXDS(unsigned long a, unsigned long b) +{ + register long result; + __ASM volatile("smxds %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.114.3. SMXDS ===== */ + +/* ===== Inline Function Start for 3.115. SMIN8 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_MISC + * \brief SMIN8 (SIMD 8-bit Signed Minimum) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * SMIN8 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 8-bit signed integer elements finding minimum operations simultaneously. + * + * **Description**:\n + * This instruction compares the 8-bit signed integer elements in Rs1 with the 8-bit + * signed integer elements in Rs2 and selects the numbers that is less than the other one. The selected + * results are written to Rd. + * + * **Operations**:\n + * ~~~ + * Rd.B[x] = (Rs1.B[x] < Rs2.B[x])? Rs1.B[x] : Rs2.B[x]; + * for RV32: x=3...0, + * for RV64: x=7...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_SMIN8(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("smin8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.115. SMIN8 ===== */ + +/* ===== Inline Function Start for 3.116. SMIN16 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_MISC + * \brief SMIN16 (SIMD 16-bit Signed Minimum) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * SMIN16 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 16-bit signed integer elements finding minimum operations simultaneously. + * + * **Description**:\n + * This instruction compares the 16-bit signed integer elements in Rs1 with the 16-bit + * signed integer elements in Rs2 and selects the numbers that is less than the other one. The selected + * results are written to Rd. + * + * **Operations**:\n + * ~~~ + * Rd.H[x] = (Rs1.H[x] < Rs2.H[x])? Rs1.H[x] : Rs2.H[x]; + * for RV32: x=1...0, + * for RV64: x=3...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_SMIN16(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("smin16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.116. SMIN16 ===== */ + +/* ===== Inline Function Start for 3.117.1. SMMUL ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X32_MAC + * \brief SMMUL (SIMD MSW Signed Multiply Word) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * SMMUL Rd, Rs1, Rs2 + * SMMUL.u Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Multiply the 32-bit signed integer elements of two registers and write the most significant + * 32-bit results to the corresponding 32-bit elements of a register. The `.u` form performs an + * additional rounding up operation on the multiplication results before taking the most significant + * 32-bit part of the results. + * + * **Description**:\n + * This instruction multiplies the 32-bit elements of Rs1 with the 32-bit elements of Rs2 and writes the + * most significant 32-bit multiplication results to the corresponding 32-bit elements of Rd. The 32-bit + * elements of Rs1 and Rs2 are treated as signed integers. The `.u` form of the instruction rounds up + * the most significant 32-bit of the 64-bit multiplication results by adding a 1 to bit 31 of the results. + * * For `smmul/RV32` instruction, it is an alias to `mulh/RV32` instruction. + * + * **Operations**:\n + * ~~~ + * Mres[x][63:0] = Rs1.W[x] * Rs2.W[x]; + * if (`.u` form) { + * Round[x][32:0] = Mres[x][63:31] + 1; + * Rd.W[x] = Round[x][32:1]; + * } else { + * Rd.W[x] = Mres[x][63:32]; + * } + * for RV32: x=0 + * for RV64: x=1...0 + * ~~~ + * + * \param [in] a long type of value stored in a + * \param [in] b long type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_SMMUL(long a, long b) +{ + register long result; + __ASM volatile("smmul %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.117.1. SMMUL ===== */ + +/* ===== Inline Function Start for 3.117.2. SMMUL.u ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X32_MAC + * \brief SMMUL.u (SIMD MSW Signed Multiply Word with Rounding) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * SMMUL Rd, Rs1, Rs2 + * SMMUL.u Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Multiply the 32-bit signed integer elements of two registers and write the most significant + * 32-bit results to the corresponding 32-bit elements of a register. The `.u` form performs an + * additional rounding up operation on the multiplication results before taking the most significant + * 32-bit part of the results. + * + * **Description**:\n + * This instruction multiplies the 32-bit elements of Rs1 with the 32-bit elements of Rs2 and writes the + * most significant 32-bit multiplication results to the corresponding 32-bit elements of Rd. The 32-bit + * elements of Rs1 and Rs2 are treated as signed integers. The `.u` form of the instruction rounds up + * the most significant 32-bit of the 64-bit multiplication results by adding a 1 to bit 31 of the results. + * * For `smmul/RV32` instruction, it is an alias to `mulh/RV32` instruction. + * + * **Operations**:\n + * ~~~ + * Mres[x][63:0] = Rs1.W[x] * Rs2.W[x]; + * if (`.u` form) { + * Round[x][32:0] = Mres[x][63:31] + 1; + * Rd.W[x] = Round[x][32:1]; + * } else { + * Rd.W[x] = Mres[x][63:32]; + * } + * for RV32: x=0 + * for RV64: x=1...0 + * ~~~ + * + * \param [in] a long type of value stored in a + * \param [in] b long type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_SMMUL_U(long a, long b) +{ + register long result; + __ASM volatile("smmul.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.117.2. SMMUL.u ===== */ + +/* ===== Inline Function Start for 3.118.1. SMMWB ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X16_MAC + * \brief SMMWB (SIMD MSW Signed Multiply Word and Bottom Half) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * SMMWB Rd, Rs1, Rs2 + * SMMWB.u Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Multiply the signed 32-bit integer elements of one register and the bottom 16-bit of the + * corresponding 32-bit elements of another register, and write the most significant 32-bit results to + * the corresponding 32-bit elements of a register. The `.u` form rounds up the results from the most + * significant discarded bit. + * + * **Description**:\n + * This instruction multiplies the signed 32-bit elements of Rs1 with the signed bottom 16-bit content + * of the corresponding 32-bit elements of Rs2 and writes the most significant 32-bit multiplication + * results to the corresponding 32-bit elements of Rd. The `.u` form of the instruction rounds up the + * most significant 32-bit of the 48-bit multiplication results by adding a 1 to bit 15 of the results. + * + * **Operations**:\n + * ~~~ + * Mres[x][47:0] = Rs1.W[x] * Rs2.W[x].H[0]; + * if (`.u` form) { + * Round[x][32:0] = Mres[x][47:15] + 1; + * Rd.W[x] = Round[x][32:1]; + * } else { + * Rd.W[x] = Mres[x][47:16]; + * } + * for RV32: x=0 + * for RV64: x=1...0 + * ~~~ + * + * \param [in] a long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_SMMWB(long a, unsigned long b) +{ + register long result; + __ASM volatile("smmwb %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.118.1. SMMWB ===== */ + +/* ===== Inline Function Start for 3.118.2. SMMWB.u ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X16_MAC + * \brief SMMWB.u (SIMD MSW Signed Multiply Word and Bottom Half with Rounding) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * SMMWB Rd, Rs1, Rs2 + * SMMWB.u Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Multiply the signed 32-bit integer elements of one register and the bottom 16-bit of the + * corresponding 32-bit elements of another register, and write the most significant 32-bit results to + * the corresponding 32-bit elements of a register. The `.u` form rounds up the results from the most + * significant discarded bit. + * + * **Description**:\n + * This instruction multiplies the signed 32-bit elements of Rs1 with the signed bottom 16-bit content + * of the corresponding 32-bit elements of Rs2 and writes the most significant 32-bit multiplication + * results to the corresponding 32-bit elements of Rd. The `.u` form of the instruction rounds up the + * most significant 32-bit of the 48-bit multiplication results by adding a 1 to bit 15 of the results. + * + * **Operations**:\n + * ~~~ + * Mres[x][47:0] = Rs1.W[x] * Rs2.W[x].H[0]; + * if (`.u` form) { + * Round[x][32:0] = Mres[x][47:15] + 1; + * Rd.W[x] = Round[x][32:1]; + * } else { + * Rd.W[x] = Mres[x][47:16]; + * } + * for RV32: x=0 + * for RV64: x=1...0 + * ~~~ + * + * \param [in] a long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_SMMWB_U(long a, unsigned long b) +{ + register long result; + __ASM volatile("smmwb.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.118.2. SMMWB.u ===== */ + +/* ===== Inline Function Start for 3.119.1. SMMWT ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X16_MAC + * \brief SMMWT (SIMD MSW Signed Multiply Word and Top Half) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * SMMWT Rd, Rs1, Rs2 + * SMMWT.u Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Multiply the signed 32-bit integer elements of one register and the top 16-bit of the + * corresponding 32-bit elements of another register, and write the most significant 32-bit results to + * the corresponding 32-bit elements of a register. The `.u` form rounds up the results from the most + * significant discarded bit. + * + * **Description**:\n + * This instruction multiplies the signed 32-bit elements of Rs1 with the top signed 16-bit content of + * the corresponding 32-bit elements of Rs2 and writes the most significant 32-bit multiplication + * results to the corresponding 32-bit elements of Rd. The `.u` form of the instruction rounds up the + * most significant 32-bit of the 48-bit multiplication results by adding a 1 to bit 15 of the results. + * + * **Operations**:\n + * ~~~ + * Mres[x][47:0] = Rs1.W[x] * Rs2.W[x].H[1]; + * if (`.u` form) { + * Round[x][32:0] = Mres[x][47:15] + 1; + * Rd.W[x] = Round[x][32:1]; + * } else { + * Rd.W[x] = Mres[x][47:16]; + * } + * for RV32: x=0 + * for RV64: x=1...0 + * ~~~ + * + * \param [in] a long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_SMMWT(long a, unsigned long b) +{ + register long result; + __ASM volatile("smmwt %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.119.1. SMMWT ===== */ + +/* ===== Inline Function Start for 3.119.2. SMMWT.u ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X16_MAC + * \brief SMMWT.u (SIMD MSW Signed Multiply Word and Top Half with Rounding) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * SMMWT Rd, Rs1, Rs2 + * SMMWT.u Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Multiply the signed 32-bit integer elements of one register and the top 16-bit of the + * corresponding 32-bit elements of another register, and write the most significant 32-bit results to + * the corresponding 32-bit elements of a register. The `.u` form rounds up the results from the most + * significant discarded bit. + * + * **Description**:\n + * This instruction multiplies the signed 32-bit elements of Rs1 with the top signed 16-bit content of + * the corresponding 32-bit elements of Rs2 and writes the most significant 32-bit multiplication + * results to the corresponding 32-bit elements of Rd. The `.u` form of the instruction rounds up the + * most significant 32-bit of the 48-bit multiplication results by adding a 1 to bit 15 of the results. + * + * **Operations**:\n + * ~~~ + * Mres[x][47:0] = Rs1.W[x] * Rs2.W[x].H[1]; + * if (`.u` form) { + * Round[x][32:0] = Mres[x][47:15] + 1; + * Rd.W[x] = Round[x][32:1]; + * } else { + * Rd.W[x] = Mres[x][47:16]; + * } + * for RV32: x=0 + * for RV64: x=1...0 + * ~~~ + * + * \param [in] a long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_SMMWT_U(long a, unsigned long b) +{ + register long result; + __ASM volatile("smmwt.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.119.2. SMMWT.u ===== */ + +/* ===== Inline Function Start for 3.120.1. SMSLDA ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_64B_ADDSUB + * \brief SMSLDA (Signed Multiply Two Halfs & Add & Subtract 64-bit) + * \details + * **Type**: DSP (64-bit Profile) + * + * **Syntax**:\n + * ~~~ + * SMSLDA Rd, Rs1, Rs2 + * SMSLXDA Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do two signed 16-bit multiplications from the 32-bit elements of two registers; and then + * subtracts the two 32-bit results from the 64-bit value of an even/odd pair of registers (RV32) or a + * register (RV64). The subtraction result is written back to the register-pair. + * * SMSLDA: rd pair - top*top - bottom*bottom (all 32-bit elements) + * * SMSLXDA: rd pair - top*bottom - bottom*top (all 32-bit elements) + * + * **RV32 Description**:\n + * For the `SMSLDA` instruction, it multiplies the bottom 16-bit content of Rs1 with the bottom 16-bit + * content Rs2 and multiplies the top 16-bit content of Rs1 with the top 16-bit content of Rs2. + * For the `SMSLXDA` instruction, it multiplies the top 16-bit content of Rs1 with the bottom 16-bit + * content of Rs2 and multiplies the bottom 16-bit content of Rs1 with the top 16-bit content of Rs2. + * The two multiplication results are subtracted from the 64-bit value of an even/odd pair of registers + * specified by Rd(4,1). The 64-bit subtraction result is written back to the register-pair. The 16-bit + * values of Rs1 and Rs2, and the 64-bit value of the register-pair are treated as signed integers. + * Rd(4,1), i.e., d, determines the even/odd pair group of the two registers. Specifically, the register pair + * includes register 2d and 2d+1. + * The odd `2d+1` register of the pair contains the high 32-bit of the result and the even `2d` register + * of the pair contains the low 32-bit of the result. + * + * **RV64 Description**:\n + * For the `SMSLDA` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 + * with the bottom 16-bit content of the 32-bit elements of Rs2 and multiplies the top 16-bit content of + * the 32-bit elements of Rs1 with the top 16-bit content of the 32-bit elements of Rs2. + * For the `SMSLXDA` instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1 with + * the bottom 16-bit content of the 32-bit elements of Rs2 and multiplies the bottom 16-bit content of + * the 32-bit elements of Rs1 with the top 16-bit content of the 32-bit elements of Rs2. + * The four multiplication results are subtracted from the 64-bit value of Rd. The 64-bit subtraction + * result is written back to Rd. The 16-bit values of Rs1 and Rs2, and the 64-bit value of Rd are treated + * as signed integers. + * + * **Operations**:\n + * ~~~ + * * RV32: + * // SMSLDA + * Mres0[31:0] = (Rs1.H[0] * Rs2.H[0]); + * Mres1[31:0] = (Rs1.H[1] * Rs2.H[1]); + * // SMSLXDA + * Mres0[31:0] = (Rs1.H[0] * Rs2.H[1]); + * Mres1[31:0] = (Rs1.H[1] * Rs2.H[0]); + * Idx0 = CONCAT(Rd(4,1),1'b0); Idx1 = CONCAT(Rd(4,1),1'b1); + * R[Idx1].R[Idx0] = R[Idx1].R[Idx0] - SE64(Mres0[31:0]) - SE64(Mres1[31:0]); + * * RV64: + * // SMSLDA + * Mres0[0][31:0] = (Rs1.W[0].H[0] * Rs2.W[0].H[0]); + * Mres1[0][31:0] = (Rs1.W[0].H[1] * Rs2.W[0].H[1]); + * Mres0[1][31:0] = (Rs1.W[1].H[0] * Rs2.W[1].H[0]); + * Mres1[1][31:0] = (Rs1.W[1].H[1] * Rs2.W[1].H[1]); + * // SMSLXDA + * Mres0[0][31:0] = (Rs1.W[0].H[0] * Rs2.W[0].H[1]); + * Mres1[0][31:0] = (Rs1.W[0].H[1] * Rs2.W[0].H[0]); + * Mres0[1][31:0] = (Rs1.W[1].H[0] * Rs2.W[1].H[1]); + * Mres1[1][31:0] = (Rs1.W[1].H[1] * Rs2.W[1].H[0]); + * Rd = Rd - SE64(Mres0[0][31:0]) - SE64(Mres1[0][31:0]) - SE64(Mres0[1][31:0]) - + * SE64(Mres1[1][31:0]); + * ~~~ + * + * \param [in] t long long type of value stored in t + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in long long type + */ +__STATIC_FORCEINLINE long long __RV_SMSLDA(long long t, unsigned long a, unsigned long b) +{ + __ASM volatile("smslda %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); + return t; +} +/* ===== Inline Function End for 3.120.1. SMSLDA ===== */ + +/* ===== Inline Function Start for 3.120.2. SMSLXDA ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_64B_ADDSUB + * \brief SMSLXDA (Signed Crossed Multiply Two Halfs & Add & Subtract 64- bit) + * \details + * **Type**: DSP (64-bit Profile) + * + * **Syntax**:\n + * ~~~ + * SMSLDA Rd, Rs1, Rs2 + * SMSLXDA Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do two signed 16-bit multiplications from the 32-bit elements of two registers; and then + * subtracts the two 32-bit results from the 64-bit value of an even/odd pair of registers (RV32) or a + * register (RV64). The subtraction result is written back to the register-pair. + * * SMSLDA: rd pair - top*top - bottom*bottom (all 32-bit elements) + * * SMSLXDA: rd pair - top*bottom - bottom*top (all 32-bit elements) + * + * **RV32 Description**:\n + * For the `SMSLDA` instruction, it multiplies the bottom 16-bit content of Rs1 with the bottom 16-bit + * content Rs2 and multiplies the top 16-bit content of Rs1 with the top 16-bit content of Rs2. + * For the `SMSLXDA` instruction, it multiplies the top 16-bit content of Rs1 with the bottom 16-bit + * content of Rs2 and multiplies the bottom 16-bit content of Rs1 with the top 16-bit content of Rs2. + * The two multiplication results are subtracted from the 64-bit value of an even/odd pair of registers + * specified by Rd(4,1). The 64-bit subtraction result is written back to the register-pair. The 16-bit + * values of Rs1 and Rs2, and the 64-bit value of the register-pair are treated as signed integers. + * Rd(4,1), i.e., d, determines the even/odd pair group of the two registers. Specifically, the register pair + * includes register 2d and 2d+1. + * The odd `2d+1` register of the pair contains the high 32-bit of the result and the even `2d` register + * of the pair contains the low 32-bit of the result. + * + * **RV64 Description**:\n + * For the `SMSLDA` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 + * with the bottom 16-bit content of the 32-bit elements of Rs2 and multiplies the top 16-bit content of + * the 32-bit elements of Rs1 with the top 16-bit content of the 32-bit elements of Rs2. + * For the `SMSLXDA` instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1 with + * the bottom 16-bit content of the 32-bit elements of Rs2 and multiplies the bottom 16-bit content of + * the 32-bit elements of Rs1 with the top 16-bit content of the 32-bit elements of Rs2. + * The four multiplication results are subtracted from the 64-bit value of Rd. The 64-bit subtraction + * result is written back to Rd. The 16-bit values of Rs1 and Rs2, and the 64-bit value of Rd are treated + * as signed integers. + * + * **Operations**:\n + * ~~~ + * * RV32: + * // SMSLDA + * Mres0[31:0] = (Rs1.H[0] * Rs2.H[0]); + * Mres1[31:0] = (Rs1.H[1] * Rs2.H[1]); + * // SMSLXDA + * Mres0[31:0] = (Rs1.H[0] * Rs2.H[1]); + * Mres1[31:0] = (Rs1.H[1] * Rs2.H[0]); + * Idx0 = CONCAT(Rd(4,1),1'b0); Idx1 = CONCAT(Rd(4,1),1'b1); + * R[Idx1].R[Idx0] = R[Idx1].R[Idx0] - SE64(Mres0[31:0]) - SE64(Mres1[31:0]); + * * RV64: + * // SMSLDA + * Mres0[0][31:0] = (Rs1.W[0].H[0] * Rs2.W[0].H[0]); + * Mres1[0][31:0] = (Rs1.W[0].H[1] * Rs2.W[0].H[1]); + * Mres0[1][31:0] = (Rs1.W[1].H[0] * Rs2.W[1].H[0]); + * Mres1[1][31:0] = (Rs1.W[1].H[1] * Rs2.W[1].H[1]); + * // SMSLXDA + * Mres0[0][31:0] = (Rs1.W[0].H[0] * Rs2.W[0].H[1]); + * Mres1[0][31:0] = (Rs1.W[0].H[1] * Rs2.W[0].H[0]); + * Mres0[1][31:0] = (Rs1.W[1].H[0] * Rs2.W[1].H[1]); + * Mres1[1][31:0] = (Rs1.W[1].H[1] * Rs2.W[1].H[0]); + * Rd = Rd - SE64(Mres0[0][31:0]) - SE64(Mres1[0][31:0]) - SE64(Mres0[1][31:0]) - + * SE64(Mres1[1][31:0]); + * ~~~ + * + * \param [in] t long long type of value stored in t + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in long long type + */ +__STATIC_FORCEINLINE long long __RV_SMSLXDA(long long t, unsigned long a, unsigned long b) +{ + __ASM volatile("smslxda %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); + return t; +} +/* ===== Inline Function End for 3.120.2. SMSLXDA ===== */ + +/* ===== Inline Function Start for 3.121. SMSR64 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_32B_MULT_64B_ADDSUB + * \brief SMSR64 (Signed Multiply and Subtract from 64- Bit Data) + * \details + * **Type**: DSP (64-bit Profile) + * + * **Syntax**:\n + * ~~~ + * SMSR64 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Multiply the 32-bit signed elements in two registers and subtract the 64-bit multiplication + * results from the 64-bit signed data of a pair of registers (RV32) or a register (RV64). The result is + * written back to the pair of registers (RV32) or a register (RV64). + * + * **RV32 Description**:\n + * This instruction multiplies the 32-bit signed data of Rs1 with that of Rs2. It + * subtracts the 64-bit multiplication result from the 64-bit signed data of an even/odd pair of registers + * specified by Rd(4,1). The subtraction result is written back to the even/odd pair of registers + * specified by Rd(4,1). + * Rx(4,1), i.e., d, determines the even/odd pair group of two registers. Specifically, the register pair + * includes register 2d and 2d+1. + * The odd `2d+1` register of the pair contains the high 32-bit of the result and the even `2d` register + * of the pair contains the low 32-bit of the result. + * + * **RV64 Description**:\n + * This instruction multiplies the 32-bit signed elements of Rs1 with that of Rs2. It + * subtracts the 64-bit multiplication results from the 64-bit signed data of Rd. The subtraction result is + * written back to Rd. + * + * **Operations**:\n + * ~~~ + * * RV32: + * t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1); + * R[t_H].R[t_L] = R[t_H].R[t_L] - (Rs1 * Rs2); + * * RV64: + * Rd = Rd - (Rs1.W[0] * Rs2.W[0]) - (Rs1.W[1] * Rs2.W[1]); + * ~~~ + * + * \param [in] t long long type of value stored in t + * \param [in] a long type of value stored in a + * \param [in] b long type of value stored in b + * \return value stored in long long type + */ +__STATIC_FORCEINLINE long long __RV_SMSR64(long long t, long a, long b) +{ + __ASM volatile("smsr64 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); + return t; +} +/* ===== Inline Function End for 3.121. SMSR64 ===== */ + +/* ===== Inline Function Start for 3.122.1. SMUL8 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_MULTIPLY + * \brief SMUL8 (SIMD Signed 8-bit Multiply) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * SMUL8 Rd, Rs1, Rs2 + * SMULX8 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do signed 8-bit multiplications and generate four 16-bit results simultaneously. + * + * **RV32 Description**:\n + * For the `SMUL8` instruction, multiply the 8-bit data elements of Rs1 with the + * corresponding 8-bit data elements of Rs2. + * For the `SMULX8` instruction, multiply the first and second 8-bit data elements of Rs1 with the + * second and first 8-bit data elements of Rs2. At the same time, multiply the third and fourth 8-bit data + * elements of Rs1 with the fourth and third 8-bit data elements of Rs2. + * The four 16-bit results are then written into an even/odd pair of registers specified by Rd(4,1). + * Rd(4,1), i.e., d, determines the even/odd pair group of two registers. Specifically, the register pair + * includes register 2d and 2d+1. + * The odd `2d+1` register of the pair contains the two 16-bit results calculated from the top part of + * Rs1 and the even `2d` register of the pair contains the two 16-bit results calculated from the bottom + * part of Rs1. + * + * **RV64 Description**:\n + * For the `SMUL8` instruction, multiply the 8-bit data elements of Rs1 with the + * corresponding 8-bit data elements of Rs2. + * For the `SMULX8` instruction, multiply the first and second 8-bit data elements of Rs1 with the + * second and first 8-bit data elements of Rs2. At the same time, multiply the third and fourth 8-bit data + * elements of Rs1 with the fourth and third 8-bit data elements of Rs2. + * The four 16-bit results are then written into Rd. The Rd.W[1] contains the two 16-bit results + * calculated from the top part of Rs1 and the Rd.W[0] contains the two 16-bit results calculated from + * the bottom part of Rs1. + * + * **Operations**:\n + * ~~~ + * * RV32: + * if (is `SMUL8`) { + * op1t[x/2] = Rs1.B[x+1]; op2t[x/2] = Rs2.B[x+1]; // top + * op1b[x/2] = Rs1.B[x]; op2b[x/2] = Rs2.B[x]; // bottom + * } else if (is `SMULX8`) { + * op1t[x/2] = Rs1.B[x+1]; op2t[x/2] = Rs2.B[x]; // Rs1 top + * op1b[x/2] = Rs1.B[x]; op2b[x/2] = Rs2.B[x+1]; // Rs1 bottom + * } + * rest[x/2] = op1t[x/2] s* op2t[x/2]; + * resb[x/2] = op1b[x/2] s* op2b[x/2]; + * t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1); + * R[t_H].H[1] = rest[1]; R[t_H].H[0] = resb[1]; + * R[t_L].H[1] = rest[0]; R[t_L].H[0] = resb[0]; + * x = 0 and 2 + * * RV64: + * if (is `SMUL8`) { + * op1t[x/2] = Rs1.B[x+1]; op2t[x/2] = Rs2.B[x+1]; // top + * op1b[x/2] = Rs1.B[x]; op2b[x/2] = Rs2.B[x]; // bottom + * } else if (is `SMULX8`) { + * op1t[x/2] = Rs1.B[x+1]; op2t[x/2] = Rs2.B[x]; // Rs1 top + * op1b[x/2] = Rs1.B[x]; op2b[x/2] = Rs2.B[x+1]; // Rs1 bottom + * } + * rest[x/2] = op1t[x/2] s* op2t[x/2]; + * resb[x/2] = op1b[x/2] s* op2b[x/2]; + * t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1); + * Rd.W[1].H[1] = rest[1]; Rd.W[1].H[0] = resb[1]; + * Rd.W[0].H[1] = rest[0]; Rd.W[0].H[0] = resb[0]; + * x = 0 and 2 + * ~~~ + * + * \param [in] a unsigned int type of value stored in a + * \param [in] b unsigned int type of value stored in b + * \return value stored in unsigned long long type + */ +__STATIC_FORCEINLINE unsigned long long __RV_SMUL8(unsigned int a, unsigned int b) +{ + register unsigned long long result; + __ASM volatile("smul8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.122.1. SMUL8 ===== */ + +/* ===== Inline Function Start for 3.122.2. SMULX8 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_MULTIPLY + * \brief SMULX8 (SIMD Signed Crossed 8-bit Multiply) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * SMUL8 Rd, Rs1, Rs2 + * SMULX8 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do signed 8-bit multiplications and generate four 16-bit results simultaneously. + * + * **RV32 Description**:\n + * For the `SMUL8` instruction, multiply the 8-bit data elements of Rs1 with the + * corresponding 8-bit data elements of Rs2. + * For the `SMULX8` instruction, multiply the first and second 8-bit data elements of Rs1 with the + * second and first 8-bit data elements of Rs2. At the same time, multiply the third and fourth 8-bit data + * elements of Rs1 with the fourth and third 8-bit data elements of Rs2. + * The four 16-bit results are then written into an even/odd pair of registers specified by Rd(4,1). + * Rd(4,1), i.e., d, determines the even/odd pair group of two registers. Specifically, the register pair + * includes register 2d and 2d+1. + * The odd `2d+1` register of the pair contains the two 16-bit results calculated from the top part of + * Rs1 and the even `2d` register of the pair contains the two 16-bit results calculated from the bottom + * part of Rs1. + * + * **RV64 Description**:\n + * For the `SMUL8` instruction, multiply the 8-bit data elements of Rs1 with the + * corresponding 8-bit data elements of Rs2. + * For the `SMULX8` instruction, multiply the first and second 8-bit data elements of Rs1 with the + * second and first 8-bit data elements of Rs2. At the same time, multiply the third and fourth 8-bit data + * elements of Rs1 with the fourth and third 8-bit data elements of Rs2. + * The four 16-bit results are then written into Rd. The Rd.W[1] contains the two 16-bit results + * calculated from the top part of Rs1 and the Rd.W[0] contains the two 16-bit results calculated from + * the bottom part of Rs1. + * + * **Operations**:\n + * ~~~ + * * RV32: + * if (is `SMUL8`) { + * op1t[x/2] = Rs1.B[x+1]; op2t[x/2] = Rs2.B[x+1]; // top + * op1b[x/2] = Rs1.B[x]; op2b[x/2] = Rs2.B[x]; // bottom + * } else if (is `SMULX8`) { + * op1t[x/2] = Rs1.B[x+1]; op2t[x/2] = Rs2.B[x]; // Rs1 top + * op1b[x/2] = Rs1.B[x]; op2b[x/2] = Rs2.B[x+1]; // Rs1 bottom + * } + * rest[x/2] = op1t[x/2] s* op2t[x/2]; + * resb[x/2] = op1b[x/2] s* op2b[x/2]; + * t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1); + * R[t_H].H[1] = rest[1]; R[t_H].H[0] = resb[1]; + * R[t_L].H[1] = rest[0]; R[t_L].H[0] = resb[0]; + * x = 0 and 2 + * * RV64: + * if (is `SMUL8`) { + * op1t[x/2] = Rs1.B[x+1]; op2t[x/2] = Rs2.B[x+1]; // top + * op1b[x/2] = Rs1.B[x]; op2b[x/2] = Rs2.B[x]; // bottom + * } else if (is `SMULX8`) { + * op1t[x/2] = Rs1.B[x+1]; op2t[x/2] = Rs2.B[x]; // Rs1 top + * op1b[x/2] = Rs1.B[x]; op2b[x/2] = Rs2.B[x+1]; // Rs1 bottom + * } + * rest[x/2] = op1t[x/2] s* op2t[x/2]; + * resb[x/2] = op1b[x/2] s* op2b[x/2]; + * t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1); + * Rd.W[1].H[1] = rest[1]; Rd.W[1].H[0] = resb[1]; + * Rd.W[0].H[1] = rest[0]; Rd.W[0].H[0] = resb[0]; + * x = 0 and 2 + * ~~~ + * + * \param [in] a unsigned int type of value stored in a + * \param [in] b unsigned int type of value stored in b + * \return value stored in unsigned long long type + */ +__STATIC_FORCEINLINE unsigned long long __RV_SMULX8(unsigned int a, unsigned int b) +{ + register unsigned long long result; + __ASM volatile("smulx8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.122.2. SMULX8 ===== */ + +/* ===== Inline Function Start for 3.123.1. SMUL16 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_MULTIPLY + * \brief SMUL16 (SIMD Signed 16-bit Multiply) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * SMUL16 Rd, Rs1, Rs2 + * SMULX16 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do signed 16-bit multiplications and generate two 32-bit results simultaneously. + * + * **RV32 Description**:\n + * For the `SMUL16` instruction, multiply the top 16-bit Q15 content of Rs1 with + * the top 16-bit Q15 content of Rs2. At the same time, multiply the bottom 16-bit Q15 content of Rs1 + * with the bottom 16-bit Q15 content of Rs2. + * For the `SMULX16` instruction, multiply the top 16-bit Q15 content of Rs1 with the bottom 16-bit + * Q15 content of Rs2. At the same time, multiply the bottom 16-bit Q15 content of Rs1 with the top 16- + * bit Q15 content of Rs2. + * The two Q30 results are then written into an even/odd pair of registers specified by Rd(4,1). Rd(4,1), + * i.e., d, determines the even/odd pair group of two registers. Specifically, the register pair includes + * register 2d and 2d+1. + * The odd `2d+1` register of the pair contains the 32-bit result calculated from the top part of Rs1 and + * the even `2d` register of the pair contains the 32-bit result calculated from the bottom part of Rs1. + * + * **RV64 Description**:\n + * For the `SMUL16` instruction, multiply the top 16-bit Q15 content of the lower + * 32-bit word in Rs1 with the top 16-bit Q15 content of the lower 32-bit word in Rs2. At the same time, + * multiply the bottom 16-bit Q15 content of the lower 32-bit word in Rs1 with the bottom 16-bit Q15 + * content of the lower 32-bit word in Rs2. + * For the `SMULX16` instruction, multiply the top 16-bit Q15 content of the lower 32-bit word in Rs1 + * with the bottom 16-bit Q15 content of the lower 32-bit word in Rs2. At the same time, multiply the + * bottom 16-bit Q15 content of the lower 32-bit word in Rs1 with the top 16-bit Q15 content of the + * lower 32-bit word in Rs2. + * The two 32-bit Q30 results are then written into Rd. The result calculated from the top 16-bit of the + * lower 32-bit word in Rs1 is written to Rd.W[1]. And the result calculated from the bottom 16-bit of + * the lower 32-bit word in Rs1 is written to Rd.W[0] + * + * **Operations**:\n + * ~~~ + * * RV32: + * if (is `SMUL16`) { + * op1t = Rs1.H[1]; op2t = Rs2.H[1]; // top + * op1b = Rs1.H[0]; op2b = Rs2.H[0]; // bottom + * } else if (is `SMULX16`) { + * op1t = Rs1.H[1]; op2t = Rs2.H[0]; // Rs1 top + * op1b = Rs1.H[0]; op2b = Rs2.H[1]; // Rs1 bottom + * } + * for ((aop,bop,res) in [(op1t,op2t,rest), (op1b,op2b,resb)]) { + * res = aop s* bop; + * } + * t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1); + * R[t_H] = rest; + * R[t_L] = resb; + * * RV64: + * if (is `SMUL16`) { + * op1t = Rs1.H[1]; op2t = Rs2.H[1]; // top + * op1b = Rs1.H[0]; op2b = Rs2.H[0]; // bottom + * } else if (is `SMULX16`) { + * op1t = Rs1.H[1]; op2t = Rs2.H[0]; // Rs1 top + * op1b = Rs1.H[0]; op2b = Rs2.H[1]; // Rs1 bottom + * } + * for ((aop,bop,res) in [(op1t,op2t,rest), (op1b,op2b,resb)]) { + * res = aop s* bop; + * } + * Rd.W[1] = rest; + * Rd.W[0] = resb; + * ~~~ + * + * \param [in] a unsigned int type of value stored in a + * \param [in] b unsigned int type of value stored in b + * \return value stored in unsigned long long type + */ +__STATIC_FORCEINLINE unsigned long long __RV_SMUL16(unsigned int a, unsigned int b) +{ + register unsigned long long result; + __ASM volatile("smul16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.123.1. SMUL16 ===== */ + +/* ===== Inline Function Start for 3.123.2. SMULX16 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_MULTIPLY + * \brief SMULX16 (SIMD Signed Crossed 16-bit Multiply) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * SMUL16 Rd, Rs1, Rs2 + * SMULX16 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do signed 16-bit multiplications and generate two 32-bit results simultaneously. + * + * **RV32 Description**:\n + * For the `SMUL16` instruction, multiply the top 16-bit Q15 content of Rs1 with + * the top 16-bit Q15 content of Rs2. At the same time, multiply the bottom 16-bit Q15 content of Rs1 + * with the bottom 16-bit Q15 content of Rs2. + * For the `SMULX16` instruction, multiply the top 16-bit Q15 content of Rs1 with the bottom 16-bit + * Q15 content of Rs2. At the same time, multiply the bottom 16-bit Q15 content of Rs1 with the top 16- + * bit Q15 content of Rs2. + * The two Q30 results are then written into an even/odd pair of registers specified by Rd(4,1). Rd(4,1), + * i.e., d, determines the even/odd pair group of two registers. Specifically, the register pair includes + * register 2d and 2d+1. + * The odd `2d+1` register of the pair contains the 32-bit result calculated from the top part of Rs1 and + * the even `2d` register of the pair contains the 32-bit result calculated from the bottom part of Rs1. + * + * **RV64 Description**:\n + * For the `SMUL16` instruction, multiply the top 16-bit Q15 content of the lower + * 32-bit word in Rs1 with the top 16-bit Q15 content of the lower 32-bit word in Rs2. At the same time, + * multiply the bottom 16-bit Q15 content of the lower 32-bit word in Rs1 with the bottom 16-bit Q15 + * content of the lower 32-bit word in Rs2. + * For the `SMULX16` instruction, multiply the top 16-bit Q15 content of the lower 32-bit word in Rs1 + * with the bottom 16-bit Q15 content of the lower 32-bit word in Rs2. At the same time, multiply the + * bottom 16-bit Q15 content of the lower 32-bit word in Rs1 with the top 16-bit Q15 content of the + * lower 32-bit word in Rs2. + * The two 32-bit Q30 results are then written into Rd. The result calculated from the top 16-bit of the + * lower 32-bit word in Rs1 is written to Rd.W[1]. And the result calculated from the bottom 16-bit of + * the lower 32-bit word in Rs1 is written to Rd.W[0] + * + * **Operations**:\n + * ~~~ + * * RV32: + * if (is `SMUL16`) { + * op1t = Rs1.H[1]; op2t = Rs2.H[1]; // top + * op1b = Rs1.H[0]; op2b = Rs2.H[0]; // bottom + * } else if (is `SMULX16`) { + * op1t = Rs1.H[1]; op2t = Rs2.H[0]; // Rs1 top + * op1b = Rs1.H[0]; op2b = Rs2.H[1]; // Rs1 bottom + * } + * for ((aop,bop,res) in [(op1t,op2t,rest), (op1b,op2b,resb)]) { + * res = aop s* bop; + * } + * t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1); + * R[t_H] = rest; + * R[t_L] = resb; + * * RV64: + * if (is `SMUL16`) { + * op1t = Rs1.H[1]; op2t = Rs2.H[1]; // top + * op1b = Rs1.H[0]; op2b = Rs2.H[0]; // bottom + * } else if (is `SMULX16`) { + * op1t = Rs1.H[1]; op2t = Rs2.H[0]; // Rs1 top + * op1b = Rs1.H[0]; op2b = Rs2.H[1]; // Rs1 bottom + * } + * for ((aop,bop,res) in [(op1t,op2t,rest), (op1b,op2b,resb)]) { + * res = aop s* bop; + * } + * Rd.W[1] = rest; + * Rd.W[0] = resb; + * ~~~ + * + * \param [in] a unsigned int type of value stored in a + * \param [in] b unsigned int type of value stored in b + * \return value stored in unsigned long long type + */ +__STATIC_FORCEINLINE unsigned long long __RV_SMULX16(unsigned int a, unsigned int b) +{ + register unsigned long long result; + __ASM volatile("smulx16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.123.2. SMULX16 ===== */ + +/* ===== Inline Function Start for 3.124. SRA.u ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_MISC + * \brief SRA.u (Rounding Shift Right Arithmetic) + * \details + * **Type**: DSP + * + * **Syntax**:\n + * ~~~ + * SRA.u Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Perform an arithmetic right shift operation with rounding. The shift amount is a variable + * from a GPR. + * + * **Description**:\n + * This instruction right-shifts the content of Rs1 arithmetically. The shifted out bits are + * filled with the sign-bit and the shift amount is specified by the low-order 5-bits (RV32) or 6-bits + * (RV64) of the Rs2 register. For the rounding operation, a value of 1 is added to the most significant + * discarded bit of the data to calculate the final result. And the result is written to Rd. + * + * **Operations**:\n + * ~~~ + * * RV32: + * sa = Rs2[4:0]; + * if (sa > 0) { + * res[31:-1] = SE33(Rs1[31:(sa-1)]) + 1; + * Rd = res[31:0]; + * } else { + * Rd = Rs1; + * } + * * RV64: + * sa = Rs2[5:0]; + * if (sa > 0) { + * res[63:-1] = SE65(Rs1[63:(sa-1)]) + 1; + * Rd = res[63:0]; + * } else { + * Rd = Rs1; + * } + * ~~~ + * + * \param [in] a long type of value stored in a + * \param [in] b unsigned int type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_SRA_U(long a, unsigned int b) +{ + register long result; + __ASM volatile("sra.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.124. SRA.u ===== */ + +/* ===== Inline Function Start for 3.125. SRAI.u ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_MISC + * \brief SRAI.u (Rounding Shift Right Arithmetic Immediate) + * \details + * **Type**: DSP + * + * **Syntax**:\n + * ~~~ + * SRAI.u Rd, Rs1, imm6u[4:0] (RV32) + * SRAI.u Rd, Rs1, imm6u[5:0] (RV64) + * ~~~ + * + * **Purpose**:\n + * Perform an arithmetic right shift operation with rounding. The shift amount is an + * immediate value. + * + * **Description**:\n + * This instruction right-shifts the content of Rs1 arithmetically. The shifted out bits are + * filled with the sign-bit and the shift amount is specified by the imm6u[4:0] (RV32) or imm6u[5:0] + * (RV64) constant . For the rounding operation, a value of 1 is added to the most significant discarded + * bit of the data to calculate the final result. And the result is written to Rd. + * + * **Operations**:\n + * ~~~ + * * RV32: + * sa = imm6u[4:0]; + * if (sa > 0) { + * res[31:-1] = SE33(Rs1[31:(sa-1)]) + 1; + * Rd = res[31:0]; + * } else { + * Rd = Rs1; + * } + * * RV64: + * sa = imm6u[5:0]; + * if (sa > 0) { + * res[63:-1] = SE65(Rs1[63:(sa-1)]) + 1; + * Rd = res[63:0]; + * } else { + * Rd = Rs1; + * } + * ~~~ + * + * \param [in] a long type of value stored in a + * \param [in] b unsigned int type of value stored in b + * \return value stored in long type + */ +#define __RV_SRAI_U(a, b) \ + ({ \ + register long result; \ + register long __a = (long)(a); \ + __ASM volatile("srai.u %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b)); \ + result; \ + }) +/* ===== Inline Function End for 3.125. SRAI.u ===== */ + +/* ===== Inline Function Start for 3.126.1. SRA8 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_SHIFT + * \brief SRA8 (SIMD 8-bit Shift Right Arithmetic) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * SRA8 Rd, Rs1, Rs2 + * SRA8.u Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 8-bit element arithmetic right shift operations simultaneously. The shift amount is a + * variable from a GPR. The `.u` form performs additional rounding up operations on the shifted + * results. + * + * **Description**:\n + * The 8-bit data elements in Rs1 are right-shifted arithmetically, that is, the shifted out + * bits are filled with the sign-bit of the data elements. The shift amount is specified by the low-order + * 3-bits of the value in the Rs2 register. For the rounding operation of the `.u` form, a value of 1 is + * added to the most significant discarded bit of each 8-bit data element to calculate the final results. + * And the results are written to Rd. + * + * **Operations**:\n + * ~~~ + * sa = Rs2[2:0]; + * if (sa > 0) { + * if (`.u` form) { // SRA8.u + * res[7:-1] = SE9(Rs1.B[x][7:sa-1]) + 1; + * Rd.B[x] = res[7:0]; + * } else { // SRA8 + * Rd.B[x] = SE8(Rd.B[x][7:sa]) + * } + * } else { + * Rd = Rs1; + * } + * for RV32: x=3...0, + * for RV64: x=7...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned int type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_SRA8(unsigned long a, unsigned int b) +{ + register unsigned long result; + __ASM volatile("sra8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.126.1. SRA8 ===== */ + +/* ===== Inline Function Start for 3.126.2. SRA8.u ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_SHIFT + * \brief SRA8.u (SIMD 8-bit Rounding Shift Right Arithmetic) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * SRA8 Rd, Rs1, Rs2 + * SRA8.u Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 8-bit element arithmetic right shift operations simultaneously. The shift amount is a + * variable from a GPR. The `.u` form performs additional rounding up operations on the shifted + * results. + * + * **Description**:\n + * The 8-bit data elements in Rs1 are right-shifted arithmetically, that is, the shifted out + * bits are filled with the sign-bit of the data elements. The shift amount is specified by the low-order + * 3-bits of the value in the Rs2 register. For the rounding operation of the `.u` form, a value of 1 is + * added to the most significant discarded bit of each 8-bit data element to calculate the final results. + * And the results are written to Rd. + * + * **Operations**:\n + * ~~~ + * sa = Rs2[2:0]; + * if (sa > 0) { + * if (`.u` form) { // SRA8.u + * res[7:-1] = SE9(Rs1.B[x][7:sa-1]) + 1; + * Rd.B[x] = res[7:0]; + * } else { // SRA8 + * Rd.B[x] = SE8(Rd.B[x][7:sa]) + * } + * } else { + * Rd = Rs1; + * } + * for RV32: x=3...0, + * for RV64: x=7...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned int type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_SRA8_U(unsigned long a, unsigned int b) +{ + register unsigned long result; + __ASM volatile("sra8.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.126.2. SRA8.u ===== */ + +/* ===== Inline Function Start for 3.127.1. SRAI8 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_SHIFT + * \brief SRAI8 (SIMD 8-bit Shift Right Arithmetic Immediate) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * SRAI8 Rd, Rs1, imm3u + * SRAI8.u Rd, Rs1, imm3u + * ~~~ + * + * **Purpose**:\n + * Do 8-bit element arithmetic right shift operations simultaneously. The shift amount is an + * immediate value. The `.u` form performs additional rounding up operations on the shifted results. + * + * **Description**:\n + * The 8-bit data elements in Rs1 are right-shifted arithmetically, that is, the shifted out + * bits are filled with the sign-bit of the data elements. The shift amount is specified by the imm3u + * constant. For the rounding operation of the `.u` form, a value of 1 is added to the most significant + * discarded bit of each 8-bit data element to calculate the final results. And the results are written to + * Rd. + * + * **Operations**:\n + * ~~~ + * sa = imm3u[2:0]; + * if (sa > 0) { + * if (`.u` form) { // SRA8.u + * res[7:-1] = SE9(Rs1.B[x][7:sa-1]) + 1; + * Rd.B[x] = res[7:0]; + * } else { // SRA8 + * Rd.B[x] = SE8(Rd.B[x][7:sa]) + * } + * } else { + * Rd = Rs1; + * } + * for RV32: x=3...0, + * for RV64: x=7...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned int type of value stored in b + * \return value stored in unsigned long type + */ +#define __RV_SRAI8(a, b) \ + ({ \ + register unsigned long result; \ + register unsigned long __a = (unsigned long)(a); \ + __ASM volatile("srai8 %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b)); \ + result; \ + }) +/* ===== Inline Function End for 3.127.1. SRAI8 ===== */ + +/* ===== Inline Function Start for 3.127.2. SRAI8.u ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_SHIFT + * \brief SRAI8.u (SIMD 8-bit Rounding Shift Right Arithmetic Immediate) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * SRAI8 Rd, Rs1, imm3u + * SRAI8.u Rd, Rs1, imm3u + * ~~~ + * + * **Purpose**:\n + * Do 8-bit element arithmetic right shift operations simultaneously. The shift amount is an + * immediate value. The `.u` form performs additional rounding up operations on the shifted results. + * + * **Description**:\n + * The 8-bit data elements in Rs1 are right-shifted arithmetically, that is, the shifted out + * bits are filled with the sign-bit of the data elements. The shift amount is specified by the imm3u + * constant. For the rounding operation of the `.u` form, a value of 1 is added to the most significant + * discarded bit of each 8-bit data element to calculate the final results. And the results are written to + * Rd. + * + * **Operations**:\n + * ~~~ + * sa = imm3u[2:0]; + * if (sa > 0) { + * if (`.u` form) { // SRA8.u + * res[7:-1] = SE9(Rs1.B[x][7:sa-1]) + 1; + * Rd.B[x] = res[7:0]; + * } else { // SRA8 + * Rd.B[x] = SE8(Rd.B[x][7:sa]) + * } + * } else { + * Rd = Rs1; + * } + * for RV32: x=3...0, + * for RV64: x=7...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned int type of value stored in b + * \return value stored in unsigned long type + */ +#define __RV_SRAI8_U(a, b) \ + ({ \ + register unsigned long result; \ + register unsigned long __a = (unsigned long)(a); \ + __ASM volatile("srai8.u %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b)); \ + result; \ + }) +/* ===== Inline Function End for 3.127.2. SRAI8.u ===== */ + +/* ===== Inline Function Start for 3.128.1. SRA16 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_SHIFT + * \brief SRA16 (SIMD 16-bit Shift Right Arithmetic) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * SRA16 Rd, Rs1, Rs2 + * SRA16.u Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 16-bit element arithmetic right shift operations simultaneously. The shift amount is a + * variable from a GPR. The `.u` form performs additional rounding up operations on the shifted + * results. + * + * **Description**:\n + * The 16-bit data elements in Rs1 are right-shifted arithmetically, that is, the shifted out + * bits are filled with the sign-bit of the data elements. The shift amount is specified by the low-order + * 4-bits of the value in the Rs2 register. For the rounding operation of the `.u` form, a value of 1 is + * added to the most significant discarded bit of each 16-bit data element to calculate the final results. + * And the results are written to Rd. + * + * **Operations**:\n + * ~~~ + * sa = Rs2[3:0]; + * if (sa != 0) { + * if (`.u` form) { // SRA16.u + * res[15:-1] = SE17(Rs1.H[x][15:sa-1]) + 1; + * Rd.H[x] = res[15:0]; + * } else { // SRA16 + * Rd.H[x] = SE16(Rs1.H[x][15:sa]) + * } + * } else { + * Rd = Rs1; + * } + * for RV32: x=1...0, + * for RV64: x=3...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_SRA16(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("sra16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.128.1. SRA16 ===== */ + +/* ===== Inline Function Start for 3.128.2. SRA16.u ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_SHIFT + * \brief SRA16.u (SIMD 16-bit Rounding Shift Right Arithmetic) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * SRA16 Rd, Rs1, Rs2 + * SRA16.u Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 16-bit element arithmetic right shift operations simultaneously. The shift amount is a + * variable from a GPR. The `.u` form performs additional rounding up operations on the shifted + * results. + * + * **Description**:\n + * The 16-bit data elements in Rs1 are right-shifted arithmetically, that is, the shifted out + * bits are filled with the sign-bit of the data elements. The shift amount is specified by the low-order + * 4-bits of the value in the Rs2 register. For the rounding operation of the `.u` form, a value of 1 is + * added to the most significant discarded bit of each 16-bit data element to calculate the final results. + * And the results are written to Rd. + * + * **Operations**:\n + * ~~~ + * sa = Rs2[3:0]; + * if (sa != 0) { + * if (`.u` form) { // SRA16.u + * res[15:-1] = SE17(Rs1.H[x][15:sa-1]) + 1; + * Rd.H[x] = res[15:0]; + * } else { // SRA16 + * Rd.H[x] = SE16(Rs1.H[x][15:sa]) + * } + * } else { + * Rd = Rs1; + * } + * for RV32: x=1...0, + * for RV64: x=3...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_SRA16_U(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("sra16.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.128.2. SRA16.u ===== */ + +/* ===== Inline Function Start for 3.129.1. SRAI16 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_SHIFT + * \brief SRAI16 (SIMD 16-bit Shift Right Arithmetic Immediate) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * SRAI16 Rd, Rs1, imm4u + * SRAI16.u Rd, Rs1, imm4u + * ~~~ + * + * **Purpose**:\n + * Do 16-bit elements arithmetic right shift operations simultaneously. The shift amount is + * an immediate value. The `.u` form performs additional rounding up operations on the shifted + * results. + * + * **Description**:\n + * The 16-bit data elements in Rs1 are right-shifted arithmetically, that is, the shifted out + * bits are filled with the sign-bit of the 16-bit data elements. The shift amount is specified by the + * imm4u constant. For the rounding operation of the `.u` form, a value of 1 is added to the most + * significant discarded bit of each 16-bit data to calculate the final results. And the results are written + * to Rd. + * + * **Operations**:\n + * ~~~ + * sa = imm4u[3:0]; + * if (sa > 0) { + * if (`.u` form) { // SRAI16.u + * res[15:-1] = SE17(Rs1.H[x][15:sa-1]) + 1; + * Rd.H[x] = res[15:0]; + * } else { // SRAI16 + * Rd.H[x] = SE16(Rs1.H[x][15:sa]); + * } + * } else { + * Rd = Rs1; + * } + * for RV32: x=1...0, + * for RV64: x=3...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +#define __RV_SRAI16(a, b) \ + ({ \ + register unsigned long result; \ + register unsigned long __a = (unsigned long)(a); \ + __ASM volatile("srai16 %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b)); \ + result; \ + }) +/* ===== Inline Function End for 3.129.1. SRAI16 ===== */ + +/* ===== Inline Function Start for 3.129.2. SRAI16.u ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_SHIFT + * \brief SRAI16.u (SIMD 16-bit Rounding Shift Right Arithmetic Immediate) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * SRAI16 Rd, Rs1, imm4u + * SRAI16.u Rd, Rs1, imm4u + * ~~~ + * + * **Purpose**:\n + * Do 16-bit elements arithmetic right shift operations simultaneously. The shift amount is + * an immediate value. The `.u` form performs additional rounding up operations on the shifted + * results. + * + * **Description**:\n + * The 16-bit data elements in Rs1 are right-shifted arithmetically, that is, the shifted out + * bits are filled with the sign-bit of the 16-bit data elements. The shift amount is specified by the + * imm4u constant. For the rounding operation of the `.u` form, a value of 1 is added to the most + * significant discarded bit of each 16-bit data to calculate the final results. And the results are written + * to Rd. + * + * **Operations**:\n + * ~~~ + * sa = imm4u[3:0]; + * if (sa > 0) { + * if (`.u` form) { // SRAI16.u + * res[15:-1] = SE17(Rs1.H[x][15:sa-1]) + 1; + * Rd.H[x] = res[15:0]; + * } else { // SRAI16 + * Rd.H[x] = SE16(Rs1.H[x][15:sa]); + * } + * } else { + * Rd = Rs1; + * } + * for RV32: x=1...0, + * for RV64: x=3...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +#define __RV_SRAI16_U(a, b) \ + ({ \ + register unsigned long result; \ + register unsigned long __a = (unsigned long)(a); \ + __ASM volatile("srai16.u %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b)); \ + result; \ + }) +/* ===== Inline Function End for 3.129.2. SRAI16.u ===== */ + +/* ===== Inline Function Start for 3.130.1. SRL8 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_SHIFT + * \brief SRL8 (SIMD 8-bit Shift Right Logical) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * SRL8 Rt, Ra, Rb + * SRL8.u Rt, Ra, Rb + * ~~~ + * + * **Purpose**:\n + * Do 8-bit elements logical right shift operations simultaneously. The shift amount is a + * variable from a GPR. The `.u` form performs additional rounding up operations on the shifted + * results. + * + * **Description**:\n + * The 8-bit data elements in Rs1 are right-shifted logically, that is, the shifted out bits are + * filled with zero. The shift amount is specified by the low-order 3-bits of the value in the Rs2 register. + * For the rounding operation of the `.u` form, a value of 1 is added to the most significant discarded + * bit of each 8-bit data element to calculate the final results. And the results are written to Rd. + * + * **Operations**:\n + * ~~~ + * sa = Rs2[2:0]; + * if (sa > 0) { + * if (`.u` form) { // SRL8.u + * res[8:0] = ZE9(Rs1.B[x][7:sa-1]) + 1; + * Rd.B[x] = res[8:1]; + * } else { // SRL8 + * Rd.B[x] = ZE8(Rs1.B[x][7:sa]); + * } + * } else { + * Rd = Rs1; + * } + * for RV32: x=3...0, + * for RV64: x=7...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned int type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_SRL8(unsigned long a, unsigned int b) +{ + register unsigned long result; + __ASM volatile("srl8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.130.1. SRL8 ===== */ + +/* ===== Inline Function Start for 3.130.2. SRL8.u ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_SHIFT + * \brief SRL8.u (SIMD 8-bit Rounding Shift Right Logical) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * SRL8 Rt, Ra, Rb + * SRL8.u Rt, Ra, Rb + * ~~~ + * + * **Purpose**:\n + * Do 8-bit elements logical right shift operations simultaneously. The shift amount is a + * variable from a GPR. The `.u` form performs additional rounding up operations on the shifted + * results. + * + * **Description**:\n + * The 8-bit data elements in Rs1 are right-shifted logically, that is, the shifted out bits are + * filled with zero. The shift amount is specified by the low-order 3-bits of the value in the Rs2 register. + * For the rounding operation of the `.u` form, a value of 1 is added to the most significant discarded + * bit of each 8-bit data element to calculate the final results. And the results are written to Rd. + * + * **Operations**:\n + * ~~~ + * sa = Rs2[2:0]; + * if (sa > 0) { + * if (`.u` form) { // SRL8.u + * res[8:0] = ZE9(Rs1.B[x][7:sa-1]) + 1; + * Rd.B[x] = res[8:1]; + * } else { // SRL8 + * Rd.B[x] = ZE8(Rs1.B[x][7:sa]); + * } + * } else { + * Rd = Rs1; + * } + * for RV32: x=3...0, + * for RV64: x=7...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned int type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_SRL8_U(unsigned long a, unsigned int b) +{ + register unsigned long result; + __ASM volatile("srl8.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.130.2. SRL8.u ===== */ + +/* ===== Inline Function Start for 3.131.1. SRLI8 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_SHIFT + * \brief SRLI8 (SIMD 8-bit Shift Right Logical Immediate) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * SRLI8 Rt, Ra, imm3u + * SRLI8.u Rt, Ra, imm3u + * ~~~ + * + * **Purpose**:\n + * Do 8-bit elements logical right shift operations simultaneously. The shift amount is an + * immediate value. The `.u` form performs additional rounding up operations on the shifted results. + * + * **Description**:\n + * The 8-bit data elements in Rs1 are right-shifted logically, that is, the shifted out bits are + * filled with zero. The shift amount is specified by the imm3u constant. For the rounding operation of + * the `.u` form, a value of 1 is added to the most significant discarded bit of each 8-bit data element to + * calculate the final results. And the results are written to Rd. + * + * **Operations**:\n + * ~~~ + * sa = imm3u[2:0]; + * if (sa > 0) { + * if (`.u` form) { // SRLI8.u + * res[8:0] = ZE9(Rs1.B[x][7:sa-1]) + 1; + * Rd.B[x] = res[8:1]; + * } else { // SRLI8 + * Rd.B[x] = ZE8(Rs1.B[x][7:sa]); + * } + * } else { + * Rd = Rs1; + * } + * for RV32: x=3...0, + * for RV64: x=7...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned int type of value stored in b + * \return value stored in unsigned long type + */ +#define __RV_SRLI8(a, b) \ + ({ \ + register unsigned long result; \ + register unsigned long __a = (unsigned long)(a); \ + __ASM volatile("srli8 %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b)); \ + result; \ + }) +/* ===== Inline Function End for 3.131.1. SRLI8 ===== */ + +/* ===== Inline Function Start for 3.131.2. SRLI8.u ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_SHIFT + * \brief SRLI8.u (SIMD 8-bit Rounding Shift Right Logical Immediate) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * SRLI8 Rt, Ra, imm3u + * SRLI8.u Rt, Ra, imm3u + * ~~~ + * + * **Purpose**:\n + * Do 8-bit elements logical right shift operations simultaneously. The shift amount is an + * immediate value. The `.u` form performs additional rounding up operations on the shifted results. + * + * **Description**:\n + * The 8-bit data elements in Rs1 are right-shifted logically, that is, the shifted out bits are + * filled with zero. The shift amount is specified by the imm3u constant. For the rounding operation of + * the `.u` form, a value of 1 is added to the most significant discarded bit of each 8-bit data element to + * calculate the final results. And the results are written to Rd. + * + * **Operations**:\n + * ~~~ + * sa = imm3u[2:0]; + * if (sa > 0) { + * if (`.u` form) { // SRLI8.u + * res[8:0] = ZE9(Rs1.B[x][7:sa-1]) + 1; + * Rd.B[x] = res[8:1]; + * } else { // SRLI8 + * Rd.B[x] = ZE8(Rs1.B[x][7:sa]); + * } + * } else { + * Rd = Rs1; + * } + * for RV32: x=3...0, + * for RV64: x=7...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned int type of value stored in b + * \return value stored in unsigned long type + */ +#define __RV_SRLI8_U(a, b) \ + ({ \ + register unsigned long result; \ + register unsigned long __a = (unsigned long)(a); \ + __ASM volatile("srli8.u %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b)); \ + result; \ + }) +/* ===== Inline Function End for 3.131.2. SRLI8.u ===== */ + +/* ===== Inline Function Start for 3.132.1. SRL16 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_SHIFT + * \brief SRL16 (SIMD 16-bit Shift Right Logical) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * SRL16 Rt, Ra, Rb + * SRL16.u Rt, Ra, Rb + * ~~~ + * + * **Purpose**:\n + * Do 16-bit elements logical right shift operations simultaneously. The shift amount is a variable from a GPR. The `.u` form performs additional rounding upoperations on the shifted results. + * + * **Description**:\n + * The 16-bit data elements in Rs1 are right-shifted logically, that is, the shifted out bits + * are filled with zero. The shift amount is specified by the low-order 4-bits of the value in the Rs2 + * register. For the rounding operation of the `.u` form, a value of 1 is added to the most significant + * discarded bit of each 16-bit data element to calculate the final results. And the results are written to + * Rd. + * + * **Operations**:\n + * ~~~ + * sa = Rs2[3:0]; + * if (sa > 0) { + * if (`.u` form) { // SRL16.u + * res[16:0] = ZE17(Rs1.H[x][15:sa-1]) + 1; + * Rd.H[x] = res[16:1]; + * } else { // SRL16 + * Rd.H[x] = ZE16(Rs1.H[x][15:sa]); + * } + * } else { + * Rd = Rs1; + * } + * for RV32: x=1...0, + * for RV64: x=3...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned int type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_SRL16(unsigned long a, unsigned int b) +{ + register unsigned long result; + __ASM volatile("srl16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.132.1. SRL16 ===== */ + +/* ===== Inline Function Start for 3.132.2. SRL16.u ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_SHIFT + * \brief SRL16.u (SIMD 16-bit Rounding Shift Right Logical) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * SRL16 Rt, Ra, Rb + * SRL16.u Rt, Ra, Rb + * ~~~ + * + * **Purpose**:\n + * Do 16-bit elements logical right shift operations simultaneously. The shift amount is a variable from a GPR. The `.u` form performs additional rounding upoperations on the shifted results. + * + * **Description**:\n + * The 16-bit data elements in Rs1 are right-shifted logically, that is, the shifted out bits + * are filled with zero. The shift amount is specified by the low-order 4-bits of the value in the Rs2 + * register. For the rounding operation of the `.u` form, a value of 1 is added to the most significant + * discarded bit of each 16-bit data element to calculate the final results. And the results are written to + * Rd. + * + * **Operations**:\n + * ~~~ + * sa = Rs2[3:0]; + * if (sa > 0) { + * if (`.u` form) { // SRL16.u + * res[16:0] = ZE17(Rs1.H[x][15:sa-1]) + 1; + * Rd.H[x] = res[16:1]; + * } else { // SRL16 + * Rd.H[x] = ZE16(Rs1.H[x][15:sa]); + * } + * } else { + * Rd = Rs1; + * } + * for RV32: x=1...0, + * for RV64: x=3...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned int type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_SRL16_U(unsigned long a, unsigned int b) +{ + register unsigned long result; + __ASM volatile("srl16.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.132.2. SRL16.u ===== */ + +/* ===== Inline Function Start for 3.133.1. SRLI16 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_SHIFT + * \brief SRLI16 (SIMD 16-bit Shift Right Logical Immediate) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * SRLI16 Rt, Ra, imm4u + * SRLI16.u Rt, Ra, imm4u + * ~~~ + * + * **Purpose**:\n + * Do 16-bit elements logical right shift operations simultaneously. The shift amount is an + * immediate value. The `.u` form performs additional rounding up operations on the shifted results. + * + * **Description**:\n + * The 16-bit data elements in Rs1 are right-shifted logically, that is, the shifted out bits + * are filled with zero. The shift amount is specified by the imm4u constant. For the rounding + * operation of the `.u` form, a value of 1 is added to the most significant discarded bit of each 16-bit + * data element to calculate the final results. And the results are written to Rd. + * + * **Operations**:\n + * ~~~ + * sa = imm4u; + * if (sa > 0) { + * if (`.u` form) { // SRLI16.u + * res[16:0] = ZE17(Rs1.H[x][15:sa-1]) + 1; + * Rd.H[x] = res[16:1]; + * } else { // SRLI16 + * Rd.H[x] = ZE16(Rs1.H[x][15:sa]); + * } + * } else { + * Rd = Rs1; + * } + * for RV32: x=1...0, + * for RV64: x=3...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned int type of value stored in b + * \return value stored in unsigned long type + */ +#define __RV_SRLI16(a, b) \ + ({ \ + register unsigned long result; \ + register unsigned long __a = (unsigned long)(a); \ + __ASM volatile("srli16 %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b)); \ + result; \ + }) +/* ===== Inline Function End for 3.133.1. SRLI16 ===== */ + +/* ===== Inline Function Start for 3.133.2. SRLI16.u ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_SHIFT + * \brief SRLI16.u (SIMD 16-bit Rounding Shift Right Logical Immediate) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * SRLI16 Rt, Ra, imm4u + * SRLI16.u Rt, Ra, imm4u + * ~~~ + * + * **Purpose**:\n + * Do 16-bit elements logical right shift operations simultaneously. The shift amount is an + * immediate value. The `.u` form performs additional rounding up operations on the shifted results. + * + * **Description**:\n + * The 16-bit data elements in Rs1 are right-shifted logically, that is, the shifted out bits + * are filled with zero. The shift amount is specified by the imm4u constant. For the rounding + * operation of the `.u` form, a value of 1 is added to the most significant discarded bit of each 16-bit + * data element to calculate the final results. And the results are written to Rd. + * + * **Operations**:\n + * ~~~ + * sa = imm4u; + * if (sa > 0) { + * if (`.u` form) { // SRLI16.u + * res[16:0] = ZE17(Rs1.H[x][15:sa-1]) + 1; + * Rd.H[x] = res[16:1]; + * } else { // SRLI16 + * Rd.H[x] = ZE16(Rs1.H[x][15:sa]); + * } + * } else { + * Rd = Rs1; + * } + * for RV32: x=1...0, + * for RV64: x=3...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned int type of value stored in b + * \return value stored in unsigned long type + */ +#define __RV_SRLI16_U(a, b) \ + ({ \ + register unsigned long result; \ + register unsigned long __a = (unsigned long)(a); \ + __ASM volatile("srli16.u %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b)); \ + result; \ + }) +/* ===== Inline Function End for 3.133.2. SRLI16.u ===== */ + +/* ===== Inline Function Start for 3.134. STAS16 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB + * \brief STAS16 (SIMD 16-bit Straight Addition & Subtraction) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * STAS16 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 16-bit integer element addition and 16-bit integer element subtraction in a 32-bit + * chunk simultaneously. Operands are from corresponding positions in 32-bit chunks. + * + * **Description**:\n + * This instruction adds the 16-bit integer element in [31:16] of 32-bit chunks in Rs1 with + * the 16-bit integer element in [31:16] of 32-bit chunks in Rs2, and writes the result to [31:16] of 32-bit + * chunks in Rd; at the same time, it subtracts the 16-bit integer element in [15:0] of 32-bit chunks in + * Rs2 from the 16-bit integer element in [15:0] of 32-bit chunks, and writes the result to [15:0] of 32- + * bit chunks in Rd. + * + * **Note**:\n + * This instruction can be used for either signed or unsigned operations. + * + * **Operations**:\n + * ~~~ + * Rd.W[x][31:16] = Rs1.W[x][31:16] + Rs2.W[x][31:16]; + * Rd.W[x][15:0] = Rs1.W[x][15:0] - Rs2.W[x][15:0]; + * for RV32, x=0 + * for RV64, x=1...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_STAS16(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("stas16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.134. STAS16 ===== */ + +/* ===== Inline Function Start for 3.135. STSA16 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB + * \brief STSA16 (SIMD 16-bit Straight Subtraction & Addition) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * STSA16 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 16-bit integer element subtraction and 16-bit integer element addition in a 32-bit + * chunk simultaneously. Operands are from corresponding positions in 32-bit chunks. + * + * **Description**:\n + * This instruction subtracts the 16-bit integer element in [31:16] of 32-bit chunks in Rs2 + * from the 16-bit integer element in [31:16] of 32-bit chunks in Rs1, and writes the result to [31:16] of + * 32-bit chunks in Rd; at the same time, it adds the 16-bit integer element in [15:0] of 32-bit chunks in + * Rs2 with the 16-bit integer element in [15:0] of 32-bit chunks in Rs1, and writes the result to [15:0] of + * 32-bit chunks in Rd. + * + * **Note**:\n + * This instruction can be used for either signed or unsigned operations. + * + * **Operations**:\n + * ~~~ + * Rd.W[x][31:16] = Rs1.W[x][31:16] - Rs2.W[x][31:16]; + * Rd.W[x][15:0] = Rs1.W[x][15:0] + Rs2.W[x][15:0]; + * for RV32, x=0 + * for RV64, x=1...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_STSA16(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("stsa16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.135. STSA16 ===== */ + +/* ===== Inline Function Start for 3.136. SUB8 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_ADDSUB + * \brief SUB8 (SIMD 8-bit Subtraction) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * SUB8 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 8-bit integer element subtractions simultaneously. + * + * **Description**:\n + * This instruction subtracts the 8-bit integer elements in Rs2 from the 8-bit integer + * elements in Rs1, and then writes the result to Rd. + * + * **Note**:\n + * This instruction can be used for either signed or unsigned subtraction. + * + * **Operations**:\n + * ~~~ + * Rd.B[x] = Rs1.B[x] - Rs2.B[x]; + * for RV32: x=3...0, + * for RV64: x=7...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_SUB8(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("sub8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.136. SUB8 ===== */ + +/* ===== Inline Function Start for 3.137. SUB16 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB + * \brief SUB16 (SIMD 16-bit Subtraction) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * SUB16 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 16-bit integer element subtractions simultaneously. + * + * **Description**:\n + * This instruction subtracts the 16-bit integer elements in Rs2 from the 16-bit integer + * elements in Rs1, and then writes the result to Rd. + * + * **Note**:\n + * This instruction can be used for either signed or unsigned subtraction. + * + * **Operations**:\n + * ~~~ + * Rd.H[x] = Rs1.H[x] - Rs2.H[x]; + * for RV32: x=1...0, + * for RV64: x=3...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_SUB16(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("sub16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.137. SUB16 ===== */ + +/* ===== Inline Function Start for 3.138. SUB64 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_64B_ADDSUB + * \brief SUB64 (64-bit Subtraction) + * \details + * **Type**: DSP (64-bit Profile) + * + * **Syntax**:\n + * ~~~ + * SUB64 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Perform a 64-bit signed or unsigned integer subtraction. + * + * **RV32 Description**:\n + * This instruction subtracts the 64-bit integer of an even/odd pair of registers + * specified by Rs2(4,1) from the 64-bit integer of an even/odd pair of registers specified by Rs1(4,1), + * and then writes the 64-bit result to an even/odd pair of registers specified by Rd(4,1). + * Rx(4,1), i.e., d, determines the even/odd pair group of two registers. Specifically, the register pair + * includes register 2d and 2d+1. + * The odd `2d+1` register of the pair contains the high 32-bit of the operand and the even `2d` + * register of the pair contains the low 32-bit of the operand. + * + * **RV64 Description**:\n + * This instruction subtracts the 64-bit integer of Rs2 from the 64-bit integer of Rs1, + * and then writes the 64-bit result to Rd. + * + * **Note**:\n + * This instruction can be used for either signed or unsigned subtraction. + * + * **Operations**:\n + * ~~~ + * * RV32: + * t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1); + * a_L = CONCAT(Rs1(4,1),1'b0); a_H = CONCAT(Rs1(4,1),1'b1); + * b_L = CONCAT(Rs2(4,1),1'b0); b_H = CONCAT(Rs2(4,1),1'b1); + * R[t_H].R[t_L] = R[a_H].R[a_L] - R[b_H].R[b_L]; + * * RV64: + * Rd = Rs1 - Rs2; + * ~~~ + * + * \param [in] a unsigned long long type of value stored in a + * \param [in] b unsigned long long type of value stored in b + * \return value stored in unsigned long long type + */ +__STATIC_FORCEINLINE unsigned long long __RV_SUB64(unsigned long long a, unsigned long long b) +{ + register unsigned long long result; + __ASM volatile("sub64 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.138. SUB64 ===== */ + +/* ===== Inline Function Start for 3.139.1. SUNPKD810 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_UNPACK + * \brief SUNPKD810 (Signed Unpacking Bytes 1 & 0) + * \details + * **Type**: DSP + * + * **Syntax**:\n + * ~~~ + * SUNPKD8xy Rd, Rs1 + * xy = {10, 20, 30, 31, 32} + * ~~~ + * + * **Purpose**:\n + * Unpack byte *x and byte y* of 32-bit chunks in a register into two 16-bit signed halfwords + * of 32-bit chunks in a register. + * + * **Description**:\n + * For the `SUNPKD8(x)(*y*)` instruction, it unpacks byte *x and byte y* of 32-bit chunks in Rs1 into + * two 16-bit signed halfwords and writes the results to the top part and the bottom part of 32-bit + * chunks in Rd. + * + * **Operations**:\n + * ~~~ + * Rd.W[m].H[1] = SE16(Rs1.W[m].B[x]) + * Rd.W[m].H[0] = SE16(Rs1.W[m].B[y]) + * // SUNPKD810, x=1,y=0 + * // SUNPKD820, x=2,y=0 + * // SUNPKD830, x=3,y=0 + * // SUNPKD831, x=3,y=1 + * // SUNPKD832, x=3,y=2 + * for RV32: m=0, + * for RV64: m=1...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_SUNPKD810(unsigned long a) +{ + register unsigned long result; + __ASM volatile("sunpkd810 %0, %1" : "=r"(result) : "r"(a)); + return result; +} +/* ===== Inline Function End for 3.139.1. SUNPKD810 ===== */ + +/* ===== Inline Function Start for 3.139.2. SUNPKD820 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_UNPACK + * \brief SUNPKD820 (Signed Unpacking Bytes 2 & 0) + * \details + * **Type**: DSP + * + * **Syntax**:\n + * ~~~ + * SUNPKD8xy Rd, Rs1 + * xy = {10, 20, 30, 31, 32} + * ~~~ + * + * **Purpose**:\n + * Unpack byte *x and byte y* of 32-bit chunks in a register into two 16-bit signed halfwords + * of 32-bit chunks in a register. + * + * **Description**:\n + * For the `SUNPKD8(x)(*y*)` instruction, it unpacks byte *x and byte y* of 32-bit chunks in Rs1 into + * two 16-bit signed halfwords and writes the results to the top part and the bottom part of 32-bit + * chunks in Rd. + * + * **Operations**:\n + * ~~~ + * Rd.W[m].H[1] = SE16(Rs1.W[m].B[x]) + * Rd.W[m].H[0] = SE16(Rs1.W[m].B[y]) + * // SUNPKD810, x=1,y=0 + * // SUNPKD820, x=2,y=0 + * // SUNPKD830, x=3,y=0 + * // SUNPKD831, x=3,y=1 + * // SUNPKD832, x=3,y=2 + * for RV32: m=0, + * for RV64: m=1...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_SUNPKD820(unsigned long a) +{ + register unsigned long result; + __ASM volatile("sunpkd820 %0, %1" : "=r"(result) : "r"(a)); + return result; +} +/* ===== Inline Function End for 3.139.2. SUNPKD820 ===== */ + +/* ===== Inline Function Start for 3.139.3. SUNPKD830 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_UNPACK + * \brief SUNPKD830 (Signed Unpacking Bytes 3 & 0) + * \details + * **Type**: DSP + * + * **Syntax**:\n + * ~~~ + * SUNPKD8xy Rd, Rs1 + * xy = {10, 20, 30, 31, 32} + * ~~~ + * + * **Purpose**:\n + * Unpack byte *x and byte y* of 32-bit chunks in a register into two 16-bit signed halfwords + * of 32-bit chunks in a register. + * + * **Description**:\n + * For the `SUNPKD8(x)(*y*)` instruction, it unpacks byte *x and byte y* of 32-bit chunks in Rs1 into + * two 16-bit signed halfwords and writes the results to the top part and the bottom part of 32-bit + * chunks in Rd. + * + * **Operations**:\n + * ~~~ + * Rd.W[m].H[1] = SE16(Rs1.W[m].B[x]) + * Rd.W[m].H[0] = SE16(Rs1.W[m].B[y]) + * // SUNPKD810, x=1,y=0 + * // SUNPKD820, x=2,y=0 + * // SUNPKD830, x=3,y=0 + * // SUNPKD831, x=3,y=1 + * // SUNPKD832, x=3,y=2 + * for RV32: m=0, + * for RV64: m=1...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_SUNPKD830(unsigned long a) +{ + register unsigned long result; + __ASM volatile("sunpkd830 %0, %1" : "=r"(result) : "r"(a)); + return result; +} +/* ===== Inline Function End for 3.139.3. SUNPKD830 ===== */ + +/* ===== Inline Function Start for 3.139.4. SUNPKD831 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_UNPACK + * \brief SUNPKD831 (Signed Unpacking Bytes 3 & 1) + * \details + * **Type**: DSP + * + * **Syntax**:\n + * ~~~ + * SUNPKD8xy Rd, Rs1 + * xy = {10, 20, 30, 31, 32} + * ~~~ + * + * **Purpose**:\n + * Unpack byte *x and byte y* of 32-bit chunks in a register into two 16-bit signed halfwords + * of 32-bit chunks in a register. + * + * **Description**:\n + * For the `SUNPKD8(x)(*y*)` instruction, it unpacks byte *x and byte y* of 32-bit chunks in Rs1 into + * two 16-bit signed halfwords and writes the results to the top part and the bottom part of 32-bit + * chunks in Rd. + * + * **Operations**:\n + * ~~~ + * Rd.W[m].H[1] = SE16(Rs1.W[m].B[x]) + * Rd.W[m].H[0] = SE16(Rs1.W[m].B[y]) + * // SUNPKD810, x=1,y=0 + * // SUNPKD820, x=2,y=0 + * // SUNPKD830, x=3,y=0 + * // SUNPKD831, x=3,y=1 + * // SUNPKD832, x=3,y=2 + * for RV32: m=0, + * for RV64: m=1...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_SUNPKD831(unsigned long a) +{ + register unsigned long result; + __ASM volatile("sunpkd831 %0, %1" : "=r"(result) : "r"(a)); + return result; +} +/* ===== Inline Function End for 3.139.4. SUNPKD831 ===== */ + +/* ===== Inline Function Start for 3.139.5. SUNPKD832 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_UNPACK + * \brief SUNPKD832 (Signed Unpacking Bytes 3 & 2) + * \details + * **Type**: DSP + * + * **Syntax**:\n + * ~~~ + * SUNPKD8xy Rd, Rs1 + * xy = {10, 20, 30, 31, 32} + * ~~~ + * + * **Purpose**:\n + * Unpack byte *x and byte y* of 32-bit chunks in a register into two 16-bit signed halfwords + * of 32-bit chunks in a register. + * + * **Description**:\n + * For the `SUNPKD8(x)(*y*)` instruction, it unpacks byte *x and byte y* of 32-bit chunks in Rs1 into + * two 16-bit signed halfwords and writes the results to the top part and the bottom part of 32-bit + * chunks in Rd. + * + * **Operations**:\n + * ~~~ + * Rd.W[m].H[1] = SE16(Rs1.W[m].B[x]) + * Rd.W[m].H[0] = SE16(Rs1.W[m].B[y]) + * // SUNPKD810, x=1,y=0 + * // SUNPKD820, x=2,y=0 + * // SUNPKD830, x=3,y=0 + * // SUNPKD831, x=3,y=1 + * // SUNPKD832, x=3,y=2 + * for RV32: m=0, + * for RV64: m=1...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_SUNPKD832(unsigned long a) +{ + register unsigned long result; + __ASM volatile("sunpkd832 %0, %1" : "=r"(result) : "r"(a)); + return result; +} +/* ===== Inline Function End for 3.139.5. SUNPKD832 ===== */ + +/* ===== Inline Function Start for 3.140. SWAP8 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_MISC + * \brief SWAP8 (Swap Byte within Halfword) + * \details + * **Type**: DSP + * + * **Syntax**:\n + * ~~~ + * SWAP8 Rd, Rs1 + * ~~~ + * + * **Purpose**:\n + * Swap the bytes within each halfword of a register. + * + * **Description**:\n + * This instruction swaps the bytes within each halfword of Rs1 and writes the result to + * Rd. + * + * **Operations**:\n + * ~~~ + * Rd.H[x] = CONCAT(Rs1.H[x][7:0],Rs1.H[x][15:8]); + * for RV32: x=1...0, + * for RV64: x=3...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_SWAP8(unsigned long a) +{ + register unsigned long result; + __ASM volatile("swap8 %0, %1" : "=r"(result) : "r"(a)); + return result; +} +/* ===== Inline Function End for 3.140. SWAP8 ===== */ + +/* ===== Inline Function Start for 3.141. SWAP16 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_MISC + * \brief SWAP16 (Swap Halfword within Word) + * \details + * **Type**: DSP + * + * **Syntax**:\n + * ~~~ + * SWAP16 Rd, Rs1 + * ~~~ + * + * **Purpose**:\n + * Swap the 16-bit halfwords within each word of a register. + * + * **Description**:\n + * This instruction swaps the 16-bit halfwords within each word of Rs1 and writes the + * result to Rd. + * + * **Operations**:\n + * ~~~ + * Rd.W[x] = CONCAT(Rs1.W[x][15:0],Rs1.H[x][31:16]); + * for RV32: x=0, + * for RV64: x=1...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_SWAP16(unsigned long a) +{ + register unsigned long result; + __ASM volatile("swap16 %0, %1" : "=r"(result) : "r"(a)); + return result; +} +/* ===== Inline Function End for 3.141. SWAP16 ===== */ + +/* ===== Inline Function Start for 3.142. UCLIP8 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_MISC + * \brief UCLIP8 (SIMD 8-bit Unsigned Clip Value) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * UCLIP8 Rt, Ra, imm3u + * ~~~ + * + * **Purpose**:\n + * Limit the 8-bit signed elements of a register into an unsigned range simultaneously. + * + * **Description**:\n + * This instruction limits the 8-bit signed elements stored in Rs1 into an unsigned integer + * range between 2^imm3u-1 and 0, and writes the limited results to Rd. For example, if imm3u is 3, the 8- + * bit input values should be saturated between 7 and 0. If saturation is performed, set OV bit to 1. + * + * **Operations**:\n + * ~~~ + * src = Rs1.H[x]; + * if (src > (2^imm3u)-1) { + * src = (2^imm3u)-1; + * OV = 1; + * } else if (src < 0) { + * src = 0; + * OV = 1; + * } + * Rd.H[x] = src; + * for RV32: x=3...0, + * for RV64: x=7...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned int type of value stored in b + * \return value stored in unsigned long type + */ +#define __RV_UCLIP8(a, b) \ + ({ \ + register unsigned long result; \ + register unsigned long __a = (unsigned long)(a); \ + __ASM volatile("uclip8 %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b)); \ + result; \ + }) +/* ===== Inline Function End for 3.142. UCLIP8 ===== */ + +/* ===== Inline Function Start for 3.143. UCLIP16 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_MISC + * \brief UCLIP16 (SIMD 16-bit Unsigned Clip Value) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * UCLIP16 Rt, Ra, imm4u + * ~~~ + * + * **Purpose**:\n + * Limit the 16-bit signed elements of a register into an unsigned range simultaneously. + * + * **Description**:\n + * This instruction limits the 16-bit signed elements stored in Rs1 into an unsigned + * integer range between 2imm4u-1 and 0, and writes the limited results to Rd. For example, if imm4u is + * 3, the 16-bit input values should be saturated between 7 and 0. If saturation is performed, set OV bit + * to 1. + * + * **Operations**:\n + * ~~~ + * src = Rs1.H[x]; + * if (src > (2^imm4u)-1) { + * src = (2^imm4u)-1; + * OV = 1; + * } else if (src < 0) { + * src = 0; + * OV = 1; + * } + * Rd.H[x] = src; + * for RV32: x=1...0, + * for RV64: x=3...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned int type of value stored in b + * \return value stored in unsigned long type + */ +#define __RV_UCLIP16(a, b) \ + ({ \ + register unsigned long result; \ + register unsigned long __a = (unsigned long)(a); \ + __ASM volatile("uclip16 %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b)); \ + result; \ + }) +/* ===== Inline Function End for 3.143. UCLIP16 ===== */ + +/* ===== Inline Function Start for 3.144. UCLIP32 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_PART_SIMD_MISC + * \brief UCLIP32 (SIMD 32-bit Unsigned Clip Value) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * UCLIP32 Rd, Rs1, imm5u[4:0] + * ~~~ + * + * **Purpose**:\n + * Limit the 32-bit signed integer elements of a register into an unsigned range + * simultaneously. + * + * **Description**:\n + * This instruction limits the 32-bit signed integer elements stored in Rs1 into an + * unsigned integer range between 2imm5u-1 and 0, and writes the limited results to Rd. For example, if + * imm5u is 3, the 32-bit input values should be saturated between 7 and 0. If saturation is performed, + * set OV bit to 1. + * + * **Operations**:\n + * ~~~ + * src = Rs1.W[x]; + * if (src > (2^imm5u)-1) { + * src = (2^imm5u)-1; + * OV = 1; + * } else if (src < 0) { + * src = 0; + * OV = 1; + * } + * Rd.W[x] = src + * for RV32: x=0, + * for RV64: x=1...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned int type of value stored in b + * \return value stored in unsigned long type + */ +#define __RV_UCLIP32(a, b) \ + ({ \ + register unsigned long result; \ + register unsigned long __a = (unsigned long)(a); \ + __ASM volatile("uclip32 %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b)); \ + result; \ + }) +/* ===== Inline Function End for 3.144. UCLIP32 ===== */ + +/* ===== Inline Function Start for 3.145. UCMPLE8 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_CMP + * \brief UCMPLE8 (SIMD 8-bit Unsigned Compare Less Than & Equal) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * UCMPLE8 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 8-bit unsigned integer elements less than & equal comparisons simultaneously. + * + * **Description**:\n + * This instruction compares the 8-bit unsigned integer elements in Rs1 with the 8-bit + * unsigned integer elements in Rs2 to see if the one in Rs1 is less than or equal to the one in Rs2. If it + * is true, the result is 0xFF; otherwise, the result is 0x0. The four comparison results are written to + * Rd. + * + * **Operations**:\n + * ~~~ + * Rd.B[x] = (Rs1.B[x] <=u Rs2.B[x])? 0xff : 0x0; + * for RV32: x=3...0, + * for RV64: x=7...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_UCMPLE8(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("ucmple8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.145. UCMPLE8 ===== */ + +/* ===== Inline Function Start for 3.146. UCMPLE16 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_CMP + * \brief UCMPLE16 (SIMD 16-bit Unsigned Compare Less Than & Equal) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * UCMPLE16 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 16-bit unsigned integer elements less than & equal comparisons simultaneously. + * + * **Description**:\n + * This instruction compares the 16-bit unsigned integer elements in Rs1 with the 16-bit + * unsigned integer elements in Rs2 to see if the one in Rs1 is less than or equal to the one in Rs2. If it + * is true, the result is 0xFFFF; otherwise, the result is 0x0. The element comparison results are + * written to Rd. + * + * **Operations**:\n + * ~~~ + * Rd.H[x] = (Rs1.H[x] <=u Rs2.H[x])? 0xffff : 0x0; + * for RV32: x=1...0, + * for RV64: x=3...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_UCMPLE16(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("ucmple16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.146. UCMPLE16 ===== */ + +/* ===== Inline Function Start for 3.147. UCMPLT8 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_CMP + * \brief UCMPLT8 (SIMD 8-bit Unsigned Compare Less Than) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * UCMPLT8 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 8-bit unsigned integer elements less than comparisons simultaneously. + * + * **Description**:\n + * This instruction compares the 8-bit unsigned integer elements in Rs1 with the 8-bit + * unsigned integer elements in Rs2 to see if the one in Rs1 is less than the one in Rs2. If it is true, the + * result is 0xFF; otherwise, the result is 0x0. The element comparison results are written to Rd. + * + * **Operations**:\n + * ~~~ + * Rd.B[x] = (Rs1.B[x] (2^8)-1) { + * res[x] = (2^8)-1; + * OV = 1; + * } + * Rd.B[x] = res[x]; + * for RV32: x=3...0, + * for RV64: x=7...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_UKADD8(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("ukadd8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.149. UKADD8 ===== */ + +/* ===== Inline Function Start for 3.150. UKADD16 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB + * \brief UKADD16 (SIMD 16-bit Unsigned Saturating Addition) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * UKADD16 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 16-bit unsigned integer element saturating additions simultaneously. + * + * **Description**:\n + * This instruction adds the 16-bit unsigned integer elements in Rs1 with the 16-bit + * unsigned integer elements in Rs2. If any of the results are beyond the 16-bit unsigned number + * range (0 <= RES <= 2^16-1), they are saturated to the range and the OV bit is set to 1. The saturated + * results are written to Rd. + * + * **Operations**:\n + * ~~~ + * res[x] = Rs1.H[x] + Rs2.H[x]; + * if (res[x] > (2^16)-1) { + * res[x] = (2^16)-1; + * OV = 1; + * } + * Rd.H[x] = res[x]; + * for RV32: x=1...0, + * for RV64: x=3...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_UKADD16(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("ukadd16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.150. UKADD16 ===== */ + +/* ===== Inline Function Start for 3.151. UKADD64 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_64B_ADDSUB + * \brief UKADD64 (64-bit Unsigned Saturating Addition) + * \details + * **Type**: DSP (64-bit Profile) + * + * **Syntax**:\n + * ~~~ + * UKADD64 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Add two 64-bit unsigned integers. The result is saturated to the U64 range. + * + * **RV32 Description**:\n + * This instruction adds the 64-bit unsigned integer of an even/odd pair of registers + * specified by Rs1(4,1) with the 64-bit unsigned integer of an even/odd pair of registers specified by + * Rs2(4,1). If the 64-bit result is beyond the U64 number range (0 <= U64 <= 2^64-1), it is saturated to the + * range and the OV bit is set to 1. The saturated result is written to an even/odd pair of registers + * specified by Rd(4,1). + * Rx(4,1), i.e., d, determines the even/odd pair group of two registers. Specifically, the register pair + * includes register 2d and 2d+1. + * The odd `2d+1` register of the pair contains the high 32-bit of the result and the even `2d` register + * of the pair contains the low 32-bit of the result. + * + * **RV64 Description**:\n + * This instruction adds the 64-bit unsigned integer in Rs1 with the 64-bit unsigned + * integer in Rs2. If the 64-bit result is beyond the U64 number range (0 <= U64 <= 2^64-1), it is saturated to + * the range and the OV bit is set to 1. The saturated result is written to Rd. + * + * **Operations**:\n + * ~~~ + * * RV32: + * t_L = CONCAT(Rt(4,1),1'b0); t_H = CONCAT(Rt(4,1),1'b1); + * a_L = CONCAT(Ra(4,1),1'b0); a_H = CONCAT(Ra(4,1),1'b1); + * b_L = CONCAT(Rb(4,1),1'b0); b_H = CONCAT(Rb(4,1),1'b1); + * result = R[a_H].R[a_L] + R[b_H].R[b_L]; + * if (result > (2^64)-1) { + * result = (2^64)-1; OV = 1; + * } + * R[t_H].R[t_L] = result; + * * RV64: + * result = Rs1 + Rs2; + * if (result > (2^64)-1) { + * result = (2^64)-1; OV = 1; + * } + * Rd = result; + * ~~~ + * + * \param [in] a unsigned long long type of value stored in a + * \param [in] b unsigned long long type of value stored in b + * \return value stored in unsigned long long type + */ +__STATIC_FORCEINLINE unsigned long long __RV_UKADD64(unsigned long long a, unsigned long long b) +{ + register unsigned long long result; + __ASM volatile("ukadd64 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.151. UKADD64 ===== */ + +/* ===== Inline Function Start for 3.152. UKADDH ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q15_SAT_ALU + * \brief UKADDH (Unsigned Addition with U16 Saturation) + * \details + * **Type**: DSP + * + * **Syntax**:\n + * ~~~ + * UKADDH Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Add the unsigned lower 32-bit content of two registers with U16 saturation. + * + * **Description**:\n + * The unsigned lower 32-bit content of Rs1 is added with the unsigned lower 32-bit + * content of Rs2. And the result is saturated to the 16-bit unsigned integer range of [0, 2^16-1] and then + * sign-extended and written to Rd. If saturation happens, this instruction sets the OV flag. + * + * **Operations**:\n + * ~~~ + * tmp = Rs1.W[0] + Rs2.W[0]; + * if (tmp > (2^16)-1) { + * tmp = (2^16)-1; + * OV = 1; + * } + * Rd = SE(tmp[15:0]); + * ~~~ + * + * \param [in] a unsigned int type of value stored in a + * \param [in] b unsigned int type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_UKADDH(unsigned int a, unsigned int b) +{ + register unsigned long result; + __ASM volatile("ukaddh %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.152. UKADDH ===== */ + +/* ===== Inline Function Start for 3.153. UKADDW ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q31_SAT_ALU + * \brief UKADDW (Unsigned Addition with U32 Saturation) + * \details + * **Type**: DSP + * + * **Syntax**:\n + * ~~~ + * UKADDW Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Add the unsigned lower 32-bit content of two registers with U32 saturation. + * + * **Description**:\n + * The unsigned lower 32-bit content of Rs1 is added with the unsigned lower 32-bit + * content of Rs2. And the result is saturated to the 32-bit unsigned integer range of [0, 2^32-1] and then + * sign-extended and written to Rd. If saturation happens, this instruction sets the OV flag. + * + * **Operations**:\n + * ~~~ + * tmp = Rs1.W[0] + Rs2.W[0]; + * if (tmp > (2^32)-1) { + * tmp[31:0] = (2^32)-1; + * OV = 1; + * } + * Rd = tmp[31:0]; // RV32 + * Rd = SE(tmp[31:0]); // RV64 + * ~~~ + * + * \param [in] a unsigned int type of value stored in a + * \param [in] b unsigned int type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_UKADDW(unsigned int a, unsigned int b) +{ + register unsigned long result; + __ASM volatile("ukaddw %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.153. UKADDW ===== */ + +/* ===== Inline Function Start for 3.154. UKCRAS16 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB + * \brief UKCRAS16 (SIMD 16-bit Unsigned Saturating Cross Addition & Subtraction) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * UKCRAS16 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do one 16-bit unsigned integer element saturating addition and one 16-bit unsigned + * integer element saturating subtraction in a 32-bit chunk simultaneously. Operands are from crossed + * positions in 32-bit chunks. + * + * **Description**:\n + * This instruction adds the 16-bit unsigned integer element in [31:16] of 32-bit chunks in + * Rs1 with the 16-bit unsigned integer element in [15:0] of 32-bit chunks in Rs2; at the same time, it + * subtracts the 16-bit unsigned integer element in [31:16] of 32-bit chunks in Rs2 from the 16-bit + * unsigned integer element in [15:0] of 32-bit chunks in Rs1. If any of the results are beyond the 16-bit + * unsigned number range (0 <= RES <= 2^16-1), they are saturated to the range and the OV bit is set to 1. + * The saturated results are written to [31:16] of 32-bit chunks in Rd for addition and [15:0] of 32-bit + * chunks in Rd for subtraction. + * + * **Operations**:\n + * ~~~ + * res1 = Rs1.W[x][31:16] + Rs2.W[x][15:0]; + * res2 = Rs1.W[x][15:0] - Rs2.W[x][31:16]; + * if (res1 > (2^16)-1) { + * res1 = (2^16)-1; + * OV = 1; + * } + * if (res2 < 0) { + * res2 = 0; + * OV = 1; + * } + * Rd.W[x][31:16] = res1; + * Rd.W[x][15:0] = res2; + * for RV32, x=0 + * for RV64, x=1...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_UKCRAS16(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("ukcras16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.154. UKCRAS16 ===== */ + +/* ===== Inline Function Start for 3.155. UKCRSA16 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB + * \brief UKCRSA16 (SIMD 16-bit Unsigned Saturating Cross Subtraction & Addition) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * UKCRSA16 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do one 16-bit unsigned integer element saturating subtraction and one 16-bit unsigned + * integer element saturating addition in a 32-bit chunk simultaneously. Operands are from crossed + * positions in 32-bit chunks. + * + * **Description**:\n + * This instruction subtracts the 16-bit unsigned integer element in [15:0] of 32-bit + * chunks in Rs2 from the 16-bit unsigned integer element in [31:16] of 32-bit chunks in Rs1; at the + * same time, it adds the 16-bit unsigned integer element in [31:16] of 32-bit chunks in Rs2 with the 16- + * bit unsigned integer element in [15:0] of 32-bit chunks in Rs1. If any of the results are beyond the + * 16-bit unsigned number range (0 <= RES <= 2^16-1), they are saturated to the range and the OV bit is set + * to 1. The saturated results are written to [31:16] of 32-bit chunks in Rd for subtraction and [15:0] of + * 32-bit chunks in Rd for addition. + * + * **Operations**:\n + * ~~~ + * res1 = Rs1.W[x][31:16] - Rs2.W[x][15:0]; + * res2 = Rs1.W[x][15:0] + Rs2.W[x][31:16]; + * if (res1 < 0) { + * res1 = 0; + * OV = 1; + * } else if (res2 > (2^16)-1) { + * res2 = (2^16)-1; + * OV = 1; + * } + * Rd.W[x][31:16] = res1; + * Rd.W[x][15:0] = res2; + * for RV32, x=0 + * for RV64, x=1...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_UKCRSA16(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("ukcrsa16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.155. UKCRSA16 ===== */ + +/* ===== Inline Function Start for 3.156. UKMAR64 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_32B_MULT_64B_ADDSUB + * \brief UKMAR64 (Unsigned Multiply and Saturating Add to 64-Bit Data) + * \details + * **Type**: DSP (64-bit Profile) + * + * **Syntax**:\n + * ~~~ + * UKMAR64 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Multiply the 32-bit unsigned elements in two registers and add the 64-bit multiplication + * results to the 64-bit unsigned data of a pair of registers (RV32) or a register (RV64). The result is + * saturated to the U64 range and written back to the pair of registers (RV32) or the register (RV64). + * + * **RV32 Description**:\n + * This instruction multiplies the 32-bit unsigned data of Rs1 with that of Rs2. It + * adds the 64-bit multiplication result to the 64-bit unsigned data of an even/odd pair of registers + * specified by Rd(4,1) with unlimited precision. If the 64-bit addition result is beyond the U64 number + * range (0 <= U64 <= 2^64-1), it is saturated to the range and the OV bit is set to 1. The saturated result is + * written back to the even/odd pair of registers specified by Rd(4,1). + * Rx(4,1), i.e., d, determines the even/odd pair group of two registers. Specifically, the register pair + * includes register 2d and 2d+1. + * The odd `2d+1` register of the pair contains the high 32-bit of the result and the even `2d` register + * of the pair contains the low 32-bit of the result. + * + * **RV64 Description**:\n + * This instruction multiplies the 32-bit unsigned elements of Rs1 with that of Rs2. + * It adds the 64-bit multiplication results to the 64-bit unsigned data in Rd with unlimited precision. If + * the 64-bit addition result is beyond the U64 number range (0 <= U64 <= 2^64-1), it is saturated to the + * range and the OV bit is set to 1. The saturated result is written back to Rd. + * + * **Operations**:\n + * ~~~ + * * RV32: + * t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1); + * result = R[t_H].R[t_L] + (Rs1 * Rs2); + * if (result > (2^64)-1) { + * result = (2^64)-1; OV = 1; + * } + * R[t_H].R[t_L] = result; + * * RV64: + * // `result` has unlimited precision + * result = Rd + (Rs1.W[0] u* Rs2.W[0]) + (Rs1.W[1] u* Rs2.W[1]); + * if (result > (2^64)-1) { + * result = (2^64)-1; OV = 1; + * } + * Rd = result; + * ~~~ + * + * \param [in] t unsigned long long type of value stored in t + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long long type + */ +__STATIC_FORCEINLINE unsigned long long __RV_UKMAR64(unsigned long long t, unsigned long a, unsigned long b) +{ + __ASM volatile("ukmar64 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); + return t; +} +/* ===== Inline Function End for 3.156. UKMAR64 ===== */ + +/* ===== Inline Function Start for 3.157. UKMSR64 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_32B_MULT_64B_ADDSUB + * \brief UKMSR64 (Unsigned Multiply and Saturating Subtract from 64-Bit Data) + * \details + * **Type**: DSP (64-bit Profile) + * + * **Syntax**:\n + * ~~~ + * UKMSR64 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Multiply the 32-bit unsigned elements in two registers and subtract the 64-bit + * multiplication results from the 64-bit unsigned data of a pair of registers (RV32) or a register (RV64). + * The result is saturated to the U64 range and written back to the pair of registers (RV32) or a register + * (RV64). + * + * **RV32 Description**:\n + * This instruction multiplies the 32-bit unsigned data of Rs1 with that of Rs2. It + * subtracts the 64-bit multiplication result from the 64-bit unsigned data of an even/odd pair of + * registers specified by Rd(4,1) with unlimited precision. If the 64-bit subtraction result is beyond the + * U64 number range (0 <= U64 <= 2^64-1), it is saturated to the range and the OV bit is set to 1. The + * saturated result is written back to the even/odd pair of registers specified by Rd(4,1). + * Rx(4,1), i.e., d, determines the even/odd pair group of two registers. Specifically, the register pair + * includes register 2d and 2d+1. + * The odd `2d+1` register of the pair contains the high 32-bit of the result and the even `2d` register + * of the pair contains the low 32-bit of the result. + * + * **RV64 Description**:\n + * This instruction multiplies the 32-bit unsigned elements of Rs1 with that of Rs2. + * It subtracts the 64-bit multiplication results from the 64-bit unsigned data of Rd with unlimited + * precision. If the 64-bit subtraction result is beyond the U64 number range (0 <= U64 <= 2^64-1), it is + * saturated to the range and the OV bit is set to 1. The saturated result is written back to Rd. + * + * **Operations**:\n + * ~~~ + * * RV32: + * t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1); + * result = R[t_H].R[t_L] - (Rs1 u* Rs2); + * if (result < 0) { + * result = 0; OV = 1; + * } + * R[t_H].R[t_L] = result; + * * RV64: + * // `result` has unlimited precision + * result = Rd - (Rs1.W[0] u* Rs2.W[0]) - (Rs1.W[1] u* Rs2.W[1]); + * if (result < 0) { + * result = 0; OV = 1; + * } + * Rd = result; + * ~~~ + * + * \param [in] t unsigned long long type of value stored in t + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long long type + */ +__STATIC_FORCEINLINE unsigned long long __RV_UKMSR64(unsigned long long t, unsigned long a, unsigned long b) +{ + __ASM volatile("ukmsr64 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); + return t; +} +/* ===== Inline Function End for 3.157. UKMSR64 ===== */ + +/* ===== Inline Function Start for 3.158. UKSTAS16 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB + * \brief UKSTAS16 (SIMD 16-bit Unsigned Saturating Straight Addition & Subtraction) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * UKSTAS16 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do one 16-bit unsigned integer element saturating addition and one 16-bit unsigned + * integer element saturating subtraction in a 32-bit chunk simultaneously. Operands are from + * corresponding positions in 32-bit chunks. + * + * **Description**:\n + * This instruction adds the 16-bit unsigned integer element in [31:16] of 32-bit chunks in + * Rs1 with the 16-bit unsigned integer element in [31:16] of 32-bit chunks in Rs2; at the same time, it + * subtracts the 16-bit unsigned integer element in [15:0] of 32-bit chunks in Rs2 from the 16-bit + * unsigned integer element in [15:0] of 32-bit chunks in Rs1. If any of the results are beyond the 16-bit + * unsigned number range (0 <= RES <= 2^16-1), they are saturated to the range and the OV bit is set to 1. + * The saturated results are written to [31:16] of 32-bit chunks in Rd for addition and [15:0] of 32-bit + * chunks in Rd for subtraction. + * + * **Operations**:\n + * ~~~ + * res1 = Rs1.W[x][31:16] + Rs2.W[x][31:16]; + * res2 = Rs1.W[x][15:0] - Rs2.W[x][15:0]; + * if (res1 > (2^16)-1) { + * res1 = (2^16)-1; + * OV = 1; + * } + * if (res2 < 0) { + * res2 = 0; + * OV = 1; + * } + * Rd.W[x][31:16] = res1; + * Rd.W[x][15:0] = res2; + * for RV32, x=0 + * for RV64, x=1...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_UKSTAS16(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("ukstas16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.158. UKSTAS16 ===== */ + +/* ===== Inline Function Start for 3.159. UKSTSA16 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB + * \brief UKSTSA16 (SIMD 16-bit Unsigned Saturating Straight Subtraction & Addition) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * UKSTSA16 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do one 16-bit unsigned integer element saturating subtraction and one 16-bit unsigned + * integer element saturating addition in a 32-bit chunk simultaneously. Operands are from + * corresponding positions in 32-bit chunks. + * + * **Description**:\n + * This instruction subtracts the 16-bit unsigned integer element in [31:16] of 32-bit + * chunks in Rs2 from the 16-bit unsigned integer element in [31:16] of 32-bit chunks in Rs1; at the + * same time, it adds the 16-bit unsigned integer element in [15:0] of 32-bit chunks in Rs2 with the 16- + * bit unsigned integer element in [15:0] of 32-bit chunks in Rs1. If any of the results are beyond the + * 16-bit unsigned number range (0 <= RES <= 2^16-1), they are saturated to the range and the OV bit is set + * to 1. The saturated results are written to [31:16] of 32-bit chunks in Rd for subtraction and [15:0] of + * 32-bit chunks in Rd for addition. + * + * **Operations**:\n + * ~~~ + * res1 = Rs1.W[x][31:16] - Rs2.W[x][31:16]; + * res2 = Rs1.W[x][15:0] + Rs2.W[x][15:0]; + * if (res1 < 0) { + * res1 = 0; + * OV = 1; + * } else if (res2 > (2^16)-1) { + * res2 = (2^16)-1; + * OV = 1; + * } + * Rd.W[x][31:16] = res1; + * Rd.W[x][15:0] = res2; + * for RV32, x=0 + * for RV64, x=1...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_UKSTSA16(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("ukstsa16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.159. UKSTSA16 ===== */ + +/* ===== Inline Function Start for 3.160. UKSUB8 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_ADDSUB + * \brief UKSUB8 (SIMD 8-bit Unsigned Saturating Subtraction) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * UKSUB8 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 8-bit unsigned integer elements saturating subtractions simultaneously. + * + * **Description**:\n + * This instruction subtracts the 8-bit unsigned integer elements in Rs2 from the 8-bit + * unsigned integer elements in Rs1. If any of the results are beyond the 8-bit unsigned number range + * (0 <= RES <= 28-1), they are saturated to the range and the OV bit is set to 1. The saturated results are + * written to Rd. + * + * **Operations**:\n + * ~~~ + * res[x] = Rs1.B[x] - Rs2.B[x]; + * if (res[x] < 0) { + * res[x] = 0; + * OV = 1; + * } + * Rd.B[x] = res[x]; + * for RV32: x=3...0, + * for RV64: x=7...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_UKSUB8(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("uksub8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.160. UKSUB8 ===== */ + +/* ===== Inline Function Start for 3.161. UKSUB16 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB + * \brief UKSUB16 (SIMD 16-bit Unsigned Saturating Subtraction) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * UKSUB16 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 16-bit unsigned integer elements saturating subtractions simultaneously. + * + * **Description**:\n + * This instruction subtracts the 16-bit unsigned integer elements in Rs2 from the 16-bit + * unsigned integer elements in Rs1. If any of the results are beyond the 16-bit unsigned number + * range (0 <= RES <= 2^16-1), they are saturated to the range and the OV bit is set to 1. The saturated + * results are written to Rd. + * + * **Operations**:\n + * ~~~ + * res[x] = Rs1.H[x] - Rs2.H[x]; + * if (res[x] < 0) { + * res[x] = 0; + * OV = 1; + * } + * Rd.H[x] = res[x]; + * for RV32: x=1...0, + * for RV64: x=3...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_UKSUB16(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("uksub16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.161. UKSUB16 ===== */ + +/* ===== Inline Function Start for 3.162. UKSUB64 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_64B_ADDSUB + * \brief UKSUB64 (64-bit Unsigned Saturating Subtraction) + * \details + * **Type**: DSP (64-bit Profile) + * + * **Syntax**:\n + * ~~~ + * UKSUB64 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Perform a 64-bit signed integer subtraction. The result is saturated to the U64 range. + * + * **RV32 Description**:\n + * This instruction subtracts the 64-bit unsigned integer of an even/odd pair of + * registers specified by Rs2(4,1) from the 64-bit unsigned integer of an even/odd pair of registers + * specified by Rs1(4,1). If the 64-bit result is beyond the U64 number range (0 <= U64 <= 2^64-1), it is + * saturated to the range and the OV bit is set to 1. The saturated result is then written to an even/odd + * pair of registers specified by Rd(4,1). + * Rx(4,1), i.e., d, determines the even/odd pair group of two registers. Specifically, the register pair + * includes register 2d and 2d+1. + * The odd `2d+1` register of the pair contains the high 32-bit of the operand and the even `2d` + * register of the pair contains the low 32-bit of the operand. + * + * **RV64 Description**:\n + * This instruction subtracts the 64-bit unsigned integer of Rs2 from the 64-bit + * unsigned integer of an even/odd pair of Rs1. If the 64-bit result is beyond the U64 number range (0 <= + * U64 <= 2^64-1), it is saturated to the range and the OV bit is set to 1. The saturated result is then written + * to Rd. + * + * **Operations**:\n + * ~~~ + * * RV32: + * t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1); + * a_L = CONCAT(Rs1(4,1),1'b0); a_H = CONCAT(Rs1(4,1),1'b1); + * b_L = CONCAT(Rs2(4,1),1'b0); b_H = CONCAT(Rs2(4,1),1'b1); + * result = R[a_H].R[a_L] - R[b_H].R[b_L]; + * if (result < 0) { + * result = 0; OV = 1; + * } + * R[t_H].R[t_L] = result; + * * RV64 + * result = Rs1 - Rs2; + * if (result < 0) { + * result = 0; OV = 1; + * } + * Rd = result; + * ~~~ + * + * \param [in] a unsigned long long type of value stored in a + * \param [in] b unsigned long long type of value stored in b + * \return value stored in unsigned long long type + */ +__STATIC_FORCEINLINE unsigned long long __RV_UKSUB64(unsigned long long a, unsigned long long b) +{ + register unsigned long long result; + __ASM volatile("uksub64 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.162. UKSUB64 ===== */ + +/* ===== Inline Function Start for 3.163. UKSUBH ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q15_SAT_ALU + * \brief UKSUBH (Unsigned Subtraction with U16 Saturation) + * \details + * **Type**: DSP + * + * **Syntax**:\n + * ~~~ + * UKSUBH Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Subtract the unsigned lower 32-bit content of two registers with U16 saturation. + * + * **Description**:\n + * The unsigned lower 32-bit content of Rs2 is subtracted from the unsigned lower 32-bit + * content of Rs1. And the result is saturated to the 16-bit unsigned integer range of [0, 2^16-1] and then + * sign-extended and written to Rd. If saturation happens, this instruction sets the OV flag. + * + * **Operations**:\n + * ~~~ + * tmp = Rs1.W[0] - Rs2.W[0]; + * if (tmp > (2^16)-1) { + * tmp = (2^16)-1; + * OV = 1; + * } + * else if (tmp < 0) { + * tmp = 0; + * OV = 1; + * } + * Rd = SE(tmp[15:0]); + * ~~~ + * + * \param [in] a unsigned int type of value stored in a + * \param [in] b unsigned int type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_UKSUBH(unsigned int a, unsigned int b) +{ + register unsigned long result; + __ASM volatile("uksubh %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.163. UKSUBH ===== */ + +/* ===== Inline Function Start for 3.164. UKSUBW ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q31_SAT_ALU + * \brief UKSUBW (Unsigned Subtraction with U32 Saturation) + * \details + * **Type**: DSP + * + * **Syntax**:\n + * ~~~ + * UKSUBW Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Subtract the unsigned lower 32-bit content of two registers with unsigned 32-bit + * saturation. + * + * **Description**:\n + * The unsigned lower 32-bit content of Rs2 is subtracted from the unsigned lower 32-bit + * content of Rs1. And the result is saturated to the 32-bit unsigned integer range of [0, 2^32-1] and then + * sign-extended and written to Rd. If saturation happens, this instruction sets the OV flag. + * + * **Operations**:\n + * ~~~ + * tmp = Rs1.W[0] - Rs2.W[0]; + * if (tmp < 0) { + * tmp[31:0] = 0; + * OV = 1; + * } + * Rd = tmp[31:0]; // RV32 + * Rd = SE(tmp[31:0]); // RV64 + * ~~~ + * + * \param [in] a unsigned int type of value stored in a + * \param [in] b unsigned int type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_UKSUBW(unsigned int a, unsigned int b) +{ + register unsigned long result; + __ASM volatile("uksubw %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.164. UKSUBW ===== */ + +/* ===== Inline Function Start for 3.165. UMAR64 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_32B_MULT_64B_ADDSUB + * \brief UMAR64 (Unsigned Multiply and Add to 64-Bit Data) + * \details + * **Type**: DSP (64-bit Profile) + * + * **Syntax**:\n + * ~~~ + * UMAR64 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Multiply the 32-bit unsigned elements in two registers and add the 64-bit multiplication + * results to the 64-bit unsigned data of a pair of registers (RV32) or a register (RV64). The result is + * written back to the pair of registers (RV32) or a register (RV64). + * + * **RV32 Description**:\n + * This instruction multiplies the 32-bit unsigned data of Rs1 with that of Rs2. It + * adds the 64-bit multiplication result to the 64-bit unsigned data of an even/odd pair of registers + * specified by Rd(4,1). The addition result is written back to the even/odd pair of registers specified by + * Rd(4,1). + * Rx(4,1), i.e., d, determines the even/odd pair group of two registers. Specifically, the register pair + * includes register 2d and 2d+1. + * The odd `2d+1` register of the pair contains the high 32-bit of the result and the even `2d` register + * of the pair contains the low 32-bit of the result. + * + * **RV64 Description**:\n + * This instruction multiplies the 32-bit unsigned elements of Rs1 with that of Rs2. + * It adds the 64-bit multiplication results to the 64-bit unsigned data of Rd. The addition result is + * written back to Rd. + * + * **Operations**:\n + * ~~~ + * * RV32: + * t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1); + * R[t_H].R[t_L] = R[t_H].R[t_L] + (Rs1 * Rs2); + * * RV64: + * Rd = Rd + (Rs1.W[0] u* Rs2.W[0]) + (Rs1.W[1] u* Rs2.W[1]); + * ~~~ + * + * \param [in] t unsigned long long type of value stored in t + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long long type + */ +__STATIC_FORCEINLINE unsigned long long __RV_UMAR64(unsigned long long t, unsigned long a, unsigned long b) +{ + __ASM volatile("umar64 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); + return t; +} +/* ===== Inline Function End for 3.165. UMAR64 ===== */ + +/* ===== Inline Function Start for 3.166. UMAQA ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_8B_MULT_32B_ADD + * \brief UMAQA (Unsigned Multiply Four Bytes with 32- bit Adds) + * \details + * **Type**: DSP + * + * **Syntax**:\n + * ~~~ + * UMAQA Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do four unsigned 8-bit multiplications from 32-bit chunks of two registers; and then adds + * the four 16-bit results and the content of corresponding 32-bit chunks of a third register together. + * + * **Description**:\n + * This instruction multiplies the four unsigned 8-bit elements of 32-bit chunks of Rs1 with the four + * unsigned 8-bit elements of 32-bit chunks of Rs2 and then adds the four results together with the + * unsigned content of the corresponding 32-bit chunks of Rd. The final results are written back to the + * corresponding 32-bit chunks in Rd. + * + * **Operations**:\n + * ~~~ + * res[x] = Rd.W[x] + (Rs1.W[x].B[3] u* Rs2.W[x].B[3]) + + * (Rs1.W[x].B[2] u* Rs2.W[x].B[2]) + (Rs1.W[x].B[1] u* Rs2.W[x].B[1]) + + * (Rs1.W[x].B[0] u* Rs2.W[x].B[0]); + * Rd.W[x] = res[x]; + * for RV32: x=0, + * for RV64: x=1...0 + * ~~~ + * + * \param [in] t unsigned long type of value stored in t + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_UMAQA(unsigned long t, unsigned long a, unsigned long b) +{ + __ASM volatile("umaqa %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); + return t; +} +/* ===== Inline Function End for 3.166. UMAQA ===== */ + +/* ===== Inline Function Start for 3.167. UMAX8 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_MISC + * \brief UMAX8 (SIMD 8-bit Unsigned Maximum) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * UMAX8 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 8-bit unsigned integer elements finding maximum operations simultaneously. + * + * **Description**:\n + * This instruction compares the 8-bit unsigned integer elements in Rs1 with the four 8- + * bit unsigned integer elements in Rs2 and selects the numbers that is greater than the other one. The + * two selected results are written to Rd. + * + * **Operations**:\n + * ~~~ + * Rd.B[x] = (Rs1.B[x] >u Rs2.B[x])? Rs1.B[x] : Rs2.B[x]; + * for RV32: x=3...0, + * for RV64: x=7...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_UMAX8(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("umax8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.167. UMAX8 ===== */ + +/* ===== Inline Function Start for 3.168. UMAX16 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_MISC + * \brief UMAX16 (SIMD 16-bit Unsigned Maximum) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * UMAX16 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 16-bit unsigned integer elements finding maximum operations simultaneously. + * + * **Description**:\n + * This instruction compares the 16-bit unsigned integer elements in Rs1 with the 16-bit + * unsigned integer elements in Rs2 and selects the numbers that is greater than the other one. The + * selected results are written to Rd. + * + * **Operations**:\n + * ~~~ + * Rd.H[x] = (Rs1.H[x] >u Rs2.H[x])? Rs1.H[x] : Rs2.H[x]; + * for RV32: x=1...0, + * for RV64: x=3...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_UMAX16(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("umax16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.168. UMAX16 ===== */ + +/* ===== Inline Function Start for 3.169. UMIN8 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_MISC + * \brief UMIN8 (SIMD 8-bit Unsigned Minimum) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * UMIN8 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 8-bit unsigned integer elements finding minimum operations simultaneously. + * + * **Description**:\n + * This instruction compares the 8-bit unsigned integer elements in Rs1 with the 8-bit + * unsigned integer elements in Rs2 and selects the numbers that is less than the other one. The + * selected results are written to Rd. + * + * **Operations**:\n + * ~~~ + * Rd.B[x] = (Rs1.B[x] > 1; + * for RV32: x=3...0, + * for RV64: x=7...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_URADD8(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("uradd8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.174. URADD8 ===== */ + +/* ===== Inline Function Start for 3.175. URADD16 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB + * \brief URADD16 (SIMD 16-bit Unsigned Halving Addition) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * URADD16 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 16-bit unsigned integer element additions simultaneously. The results are halved to + * avoid overflow or saturation. + * + * **Description**:\n + * This instruction adds the 16-bit unsigned integer elements in Rs1 with the 16-bit + * unsigned integer elements in Rs2. The results are first logically right-shifted by 1 bit and then + * written to Rd. + * + * **Examples**:\n + * ~~~ + * * Ra = 0x7FFF, Rb = 0x7FFF Rt = 0x7FFF + * * Ra = 0x8000, Rb = 0x8000 Rt = 0x8000 + * * Ra = 0x4000, Rb = 0x8000 Rt = 0x6000 + * ~~~ + * + * **Operations**:\n + * ~~~ + * Rd.H[x] = (Rs1.H[x] + Rs2.H[x]) u>> 1; + * for RV32: x=1...0, + * for RV64: x=3...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_URADD16(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("uradd16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.175. URADD16 ===== */ + +/* ===== Inline Function Start for 3.176. URADD64 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_64B_ADDSUB + * \brief URADD64 (64-bit Unsigned Halving Addition) + * \details + * **Type**: DSP (64-bit Profile) + * + * **Syntax**:\n + * ~~~ + * URADD64 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Add two 64-bit unsigned integers. The result is halved to avoid overflow or saturation. + * + * **RV32 Description**:\n + * This instruction adds the 64-bit unsigned integer of an even/odd pair of registers + * specified by Rs1(4,1) with the 64-bit unsigned integer of an even/odd pair of registers specified by + * Rs2(4,1). The 64-bit addition result is first logically right-shifted by 1 bit and then written to an + * even/odd pair of registers specified by Rd(4,1). + * Rx(4,1), i.e., d, determines the even/odd pair group of two registers. Specifically, the register pair + * includes register 2d and 2d+1. + * The odd `2d+1` register of the pair contains the high 32-bit of the result and the even `2d` register + * of the pair contains the low 32-bit of the result. + * + * **RV64 Description**:\n + * This instruction adds the 64-bit unsigned integer in Rs1 with the 64-bit unsigned + * integer Rs2. The 64-bit addition result is first logically right-shifted by 1 bit and then written to Rd. + * + * **Operations**:\n + * ~~~ + * * RV32: + * t_L = CONCAT(Rt(4,1),1'b0); t_H = CONCAT(Rt(4,1),1'b1); + * a_L = CONCAT(Ra(4,1),1'b0); a_H = CONCAT(Ra(4,1),1'b1); + * b_L = CONCAT(Rb(4,1),1'b0); b_H = CONCAT(Rb(4,1),1'b1); + * R[t_H].R[t_L] = (R[a_H].R[a_L] + R[b_H].R[b_L]) u>> 1; + * * RV64: + * Rd = (Rs1 + Rs2) u>> 1; + * ~~~ + * + * \param [in] a unsigned long long type of value stored in a + * \param [in] b unsigned long long type of value stored in b + * \return value stored in unsigned long long type + */ +__STATIC_FORCEINLINE unsigned long long __RV_URADD64(unsigned long long a, unsigned long long b) +{ + register unsigned long long result; + __ASM volatile("uradd64 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.176. URADD64 ===== */ + +/* ===== Inline Function Start for 3.177. URADDW ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_32B_COMPUTATION + * \brief URADDW (32-bit Unsigned Halving Addition) + * \details + * **Type**: DSP + * + * **Syntax**:\n + * ~~~ + * URADDW Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Add 32-bit unsigned integers and the results are halved to avoid overflow or saturation. + * + * **Description**:\n + * This instruction adds the first 32-bit unsigned integer in Rs1 with the first 32-bit + * unsigned integer in Rs2. The result is first logically right-shifted by 1 bit and then sign-extended and + * written to Rd. + * + * **Examples**:\n + * ~~~ + * * Ra = 0x7FFFFFFF, Rb = 0x7FFFFFFF Rt = 0x7FFFFFFF + * * Ra = 0x80000000, Rb = 0x80000000 Rt = 0x80000000 + * * Ra = 0x40000000, Rb = 0x80000000 Rt = 0x60000000 + * ~~~ + * + * **Operations**:\n + * ~~~ + * * RV32: + * Rd[31:0] = (Rs1[31:0] + Rs2[31:0]) u>> 1; + * * RV64: + * resw[31:0] = (Rs1[31:0] + Rs2[31:0]) u>> 1; + * Rd[63:0] = SE(resw[31:0]); + * ~~~ + * + * \param [in] a unsigned int type of value stored in a + * \param [in] b unsigned int type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_URADDW(unsigned int a, unsigned int b) +{ + register unsigned long result; + __ASM volatile("uraddw %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.177. URADDW ===== */ + +/* ===== Inline Function Start for 3.178. URCRAS16 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB + * \brief URCRAS16 (SIMD 16-bit Unsigned Halving Cross Addition & Subtraction) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * URCRAS16 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 16-bit unsigned integer element addition and 16-bit unsigned integer element + * subtraction in a 32-bit chunk simultaneously. Operands are from crossed positions in 32-bit chunks. + * The results are halved to avoid overflow or saturation. + * + * **Description**:\n + * This instruction adds the 16-bit unsigned integer in [31:16] of 32-bit chunks in Rs1 + * with the 16-bit unsigned integer in [15:0] of 32-bit chunks in Rs2, and subtracts the 16-bit unsigned + * integer in [31:16] of 32-bit chunks in Rs2 from the 16-bit unsigned integer in [15:0] of 32-bit chunks + * in Rs1. The element results are first logically right-shifted by 1 bit and then written to [31:16] of 32- + * bit chunks in Rd and [15:0] of 32-bit chunks in Rd. + * + * **Examples**:\n + * ~~~ + * Please see `URADD16` and `URSUB16` instructions. + * ~~~ + * + * **Operations**:\n + * ~~~ + * Rd.W[x][31:16] = (Rs1.W[x][31:16] + Rs2.W[x][15:0]) u>> 1; + * Rd.W[x][15:0] = (Rs1.W[x][15:0] - Rs2.W[x][31:16]) u>> 1; + * for RV32, x=0 + * for RV64, x=1...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_URCRAS16(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("urcras16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.178. URCRAS16 ===== */ + +/* ===== Inline Function Start for 3.179. URCRSA16 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB + * \brief URCRSA16 (SIMD 16-bit Unsigned Halving Cross Subtraction & Addition) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * URCRSA16 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 16-bit unsigned integer element subtraction and 16-bit unsigned integer element + * addition in a 32-bit chunk simultaneously. Operands are from crossed positions in 32-bit chunks. + * The results are halved to avoid overflow or saturation. + * + * **Description**:\n + * This instruction subtracts the 16-bit unsigned integer in [15:0] of 32-bit chunks in Rs2 + * from the 16-bit unsigned integer in [31:16] of 32-bit chunks in Rs1, and adds the 16-bit unsigned + * integer in [15:0] of 32-bit chunks in Rs1 with the 16-bit unsigned integer in [31:16] of 32-bit chunks + * in Rs2. The two results are first logically right-shifted by 1 bit and then written to [31:16] of 32-bit + * chunks in Rd and [15:0] of 32-bit chunks in Rd. + * + * **Examples**:\n + * ~~~ + * Please see `URADD16` and `URSUB16` instructions. + * ~~~ + * + * **Operations**:\n + * ~~~ + * Rd.W[x][31:16] = (Rs1.W[x][31:16] - Rs2.W[x][15:0]) u>> 1; + * Rd.W[x][15:0] = (Rs1.W[x][15:0] + Rs2.W[x][31:16]) u>> 1; + * for RV32, x=0 + * for RV64, x=1...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_URCRSA16(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("urcrsa16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.179. URCRSA16 ===== */ + +/* ===== Inline Function Start for 3.180. URSTAS16 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB + * \brief URSTAS16 (SIMD 16-bit Unsigned Halving Straight Addition & Subtraction) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * URSTAS16 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 16-bit unsigned integer element addition and 16-bit unsigned integer element + * subtraction in a 32-bit chunk simultaneously. Operands are from corresponding positions in 32-bit + * chunks. The results are halved to avoid overflow or saturation. + * + * **Description**:\n + * This instruction adds the 16-bit unsigned integer in [31:16] of 32-bit chunks in Rs1 + * with the 16-bit unsigned integer in [31:16] of 32-bit chunks in Rs2, and subtracts the 16-bit unsigned + * integer in [15:0] of 32-bit chunks in Rs2 from the 16-bit unsigned integer in [15:0] of 32-bit chunks + * in Rs1. The element results are first logically right-shifted by 1 bit and then written to [31:16] of 32- + * bit chunks in Rd and [15:0] of 32-bit chunks in Rd. + * + * **Examples**:\n + * ~~~ + * Please see `URADD16` and `URSUB16` instructions. + * ~~~ + * + * **Operations**:\n + * ~~~ + * Rd.W[x][31:16] = (Rs1.W[x][31:16] + Rs2.W[x][31:16]) u>> 1; + * Rd.W[x][15:0] = (Rs1.W[x][15:0] - Rs2.W[x][15:0]) u>> 1; + * for RV32, x=0 + * for RV64, x=1...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_URSTAS16(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("urstas16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.180. URSTAS16 ===== */ + +/* ===== Inline Function Start for 3.181. URSTSA16 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB + * \brief URSTSA16 (SIMD 16-bit Unsigned Halving Straight Subtraction & Addition) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * URCRSA16 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 16-bit unsigned integer element subtraction and 16-bit unsigned integer element + * addition in a 32-bit chunk simultaneously. Operands are from corresponding positions in 32-bit + * chunks. The results are halved to avoid overflow or saturation. + * + * **Description**:\n + * This instruction subtracts the 16-bit unsigned integer in [31:16] of 32-bit chunks in Rs2 + * from the 16-bit unsigned integer in [31:16] of 32-bit chunks in Rs1, and adds the 16-bit unsigned + * integer in [15:0] of 32-bit chunks in Rs1 with the 16-bit unsigned integer in [15:0] of 32-bit chunks in + * Rs2. The two results are first logically right-shifted by 1 bit and then written to [31:16] of 32-bit + * chunks in Rd and [15:0] of 32-bit chunks in Rd. + * + * **Examples**:\n + * ~~~ + * Please see `URADD16` and `URSUB16` instructions. + * ~~~ + * + * **Operations**:\n + * ~~~ + * Rd.W[x][31:16] = (Rs1.W[x][31:16] - Rs2.W[x][31:16]) u>> 1; + * Rd.W[x][15:0] = (Rs1.W[x][15:0] + Rs2.W[x][15:0]) u>> 1; + * for RV32, x=0 + * for RV64, x=1...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_URSTSA16(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("urstsa16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.181. URSTSA16 ===== */ + +/* ===== Inline Function Start for 3.182. URSUB8 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_ADDSUB + * \brief URSUB8 (SIMD 8-bit Unsigned Halving Subtraction) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * URSUB8 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 8-bit unsigned integer element subtractions simultaneously. The results are halved to + * avoid overflow or saturation. + * + * **Description**:\n + * This instruction subtracts the 8-bit unsigned integer elements in Rs2 from the 8-bit + * unsigned integer elements in Rs1. The results are first logically right-shifted by 1 bit and then + * written to Rd. + * + * **Examples**:\n + * ~~~ + * * Ra = 0x7F, Rb = 0x80 Rt = 0xFF + * * Ra = 0x80, Rb = 0x7F Rt = 0x00 + * * Ra = 0x80, Rb = 0x40 Rt = 0x20 + * ~~~ + * + * **Operations**:\n + * ~~~ + * Rd.B[x] = (Rs1.B[x] - Rs2.B[x]) u>> 1; + * for RV32: x=3...0, + * for RV64: x=7...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_URSUB8(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("ursub8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.182. URSUB8 ===== */ + +/* ===== Inline Function Start for 3.183. URSUB16 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB + * \brief URSUB16 (SIMD 16-bit Unsigned Halving Subtraction) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * URSUB16 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 16-bit unsigned integer element subtractions simultaneously. The results are halved to + * avoid overflow or saturation. + * + * **Description**:\n + * This instruction subtracts the 16-bit unsigned integer elements in Rs2 from the 16-bit + * unsigned integer elements in Rs1. The results are first logically right-shifted by 1 bit and then + * written to Rd. + * + * **Examples**:\n + * ~~~ + * * Ra = 0x7FFF, Rb = 0x8000 Rt = 0xFFFF + * * Ra = 0x8000, Rb = 0x7FFF Rt = 0x0000 + * * Ra = 0x8000, Rb = 0x4000 Rt = 0x2000 + * ~~~ + * + * **Operations**:\n + * ~~~ + * Rd.H[x] = (Rs1.H[x] - Rs2.H[x]) u>> 1; + * for RV32: x=1...0, + * for RV64: x=3...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_URSUB16(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("ursub16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.183. URSUB16 ===== */ + +/* ===== Inline Function Start for 3.184. URSUB64 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_64B_ADDSUB + * \brief URSUB64 (64-bit Unsigned Halving Subtraction) + * \details + * **Type**: DSP (64-bit Profile) + * + * **Syntax**:\n + * ~~~ + * URSUB64 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Perform a 64-bit unsigned integer subtraction. The result is halved to avoid overflow or + * saturation. + * + * **RV32 Description**:\n + * This instruction subtracts the 64-bit unsigned integer of an even/odd pair of + * registers specified by Rs2(4,1) from the 64-bit unsigned integer of an even/odd pair of registers + * specified by Rs1(4,1). The subtraction result is first logically right-shifted by 1 bit and then written + * to an even/odd pair of registers specified by Rd(4,1). + * Rx(4,1), i.e., d, determines the even/odd pair group of two registers. Specifically, the register pair + * includes register 2d and 2d+1. + * The odd `2d+1` register of the pair contains the high 32-bit of the result and the even `2d` register + * of the pair contains the low 32-bit of the result. + * + * **RV64 Description**:\n + * This instruction subtracts the 64-bit unsigned integer in Rs2 from the 64-bit + * unsigned integer in Rs1. The subtraction result is first logically right-shifted by 1 bit and then + * written to Rd. + * + * **Operations**:\n + * ~~~ + * * RV32: + * t_L = CONCAT(Rt(4,1),1'b0); t_H = CONCAT(Rt(4,1),1'b1); + * a_L = CONCAT(Ra(4,1),1'b0); a_H = CONCAT(Ra(4,1),1'b1); + * b_L = CONCAT(Rb(4,1),1'b0); b_H = CONCAT(Rb(4,1),1'b1); + * R[t_H].R[t_L] = (R[a_H].R[a_L] - R[b_H].R[b_L]) u>> 1; + * * RV64: + * Rd = (Rs1 - Rs2) u>> 1; + * ~~~ + * + * \param [in] a unsigned long long type of value stored in a + * \param [in] b unsigned long long type of value stored in b + * \return value stored in unsigned long long type + */ +__STATIC_FORCEINLINE unsigned long long __RV_URSUB64(unsigned long long a, unsigned long long b) +{ + register unsigned long long result; + __ASM volatile("ursub64 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.184. URSUB64 ===== */ + +/* ===== Inline Function Start for 3.185. URSUBW ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_32B_COMPUTATION + * \brief URSUBW (32-bit Unsigned Halving Subtraction) + * \details + * **Type**: DSP + * + * **Syntax**:\n + * ~~~ + * URSUBW Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Subtract 32-bit unsigned integers and the result is halved to avoid overflow or saturation. + * + * **Description**:\n + * This instruction subtracts the first 32-bit signed integer in Rs2 from the first 32-bit + * signed integer in Rs1. The result is first logically right-shifted by 1 bit and then sign-extended and + * written to Rd. + * + * **Examples**:\n + * ~~~ + * * Ra = 0x7FFFFFFF, Rb = 0x80000000 Rt = 0xFFFFFFFF + * * Ra = 0x80000000, Rb = 0x7FFFFFFF Rt = 0x00000000 + * * Ra = 0x80000000, Rb = 0x40000000 Rt = 0x20000000 + * ~~~ + * + * **Operations**:\n + * ~~~ + * * RV32: + * Rd[31:0] = (Rs1[31:0] - Rs2[31:0]) u>> 1; + * * RV64: + * resw[31:0] = (Rs1[31:0] - Rs2[31:0]) u>> 1; + * Rd[63:0] = SE(resw[31:0]); + * ~~~ + * + * \param [in] a unsigned int type of value stored in a + * \param [in] b unsigned int type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_URSUBW(unsigned int a, unsigned int b) +{ + register unsigned long result; + __ASM volatile("ursubw %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.185. URSUBW ===== */ + +/* ===== Inline Function Start for 3.186. WEXTI ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_MISC + * \brief WEXTI (Extract Word from 64-bit Immediate) + * \details + * **Type**: DSP + * + * **Syntax**:\n + * ~~~ + * WEXTI Rd, Rs1, #LSBloc + * ~~~ + * + * **Purpose**:\n + * Extract a 32-bit word from a 64-bit value stored in an even/odd pair of registers (RV32) or + * a register (RV64) starting from a specified immediate LSB bit position. + * + * **RV32 Description**:\n + * This instruction extracts a 32-bit word from a 64-bit value of an even/odd pair of registers specified + * by Rs1(4,1) starting from a specified immediate LSB bit position, #LSBloc. The extracted word is + * written to Rd. + * Rs1(4,1), i.e., d, determines the even/odd pair group of the two registers. Specifically, the register + * pair includes register 2d and 2d+1. + * The odd `2d+1` register of the pair contains the high 32-bit of the 64-bit value and the even `2d` + * register of the pair contains the low 32-bit of the 64-bit value. + * + * **RV64 Description**:\n + * This instruction extracts a 32-bit word from a 64-bit value in Rs1 starting from a specified + * immediate LSB bit position, #LSBloc. The extracted word is sign-extended and written to lower 32- + * bit of Rd. + * + * **Operations**:\n + * ~~~ + * * RV32: + * Idx0 = CONCAT(Rs1(4,1),1'b0); Idx1 = CONCAT(Rs2(4,1),1'b1); + * src[63:0] = Concat(R[Idx1], R[Idx0]); + * Rd = src[31+LSBloc:LSBloc]; + * * RV64: + * ExtractW = Rs1[31+LSBloc:LSBloc]; + * Rd = SE(ExtractW) + * ~~~ + * + * \param [in] a long long type of value stored in a + * \param [in] b unsigned int type of value stored in b + * \return value stored in unsigned long type + */ +#define __RV_WEXTI(a, b) \ + ({ \ + register unsigned long result; \ + register long long __a = (long long)(a); \ + __ASM volatile("wexti %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b)); \ + result; \ + }) +/* ===== Inline Function End for 3.186. WEXTI ===== */ + +/* ===== Inline Function Start for 3.187. WEXT ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_MISC + * \brief WEXT (Extract Word from 64-bit) + * \details + * **Type**: DSP + * + * **Syntax**:\n + * ~~~ + * WEXT Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Extract a 32-bit word from a 64-bit value stored in an even/odd pair of registers (RV32) or + * a register (RV64) starting from a specified LSB bit position in a register. + * + * **RV32 Description**:\n + * This instruction extracts a 32-bit word from a 64-bit value of an even/odd pair of registers specified + * by Rs1(4,1) starting from a specified LSB bit position, specified in Rs2[4:0]. The extracted word is + * written to Rd. + * Rs1(4,1), i.e., d, determines the even/odd pair group of the two registers. Specifically, the register + * pair includes register 2d and 2d+1. + * The odd `2d+1` register of the pair contains the high 32-bit of the 64-bit value and the even `2d` + * register of the pair contains the low 32-bit of the 64-bit value. + * + * **Operations**:\n + * ~~~ + * * RV32: + * Idx0 = CONCAT(Rs1(4,1),1'b0); Idx1 = CONCAT(Rs1(4,1),1'b1); + * src[63:0] = Concat(R[Idx1], R[Idx0]); + * LSBloc = Rs2[4:0]; + * Rd = src[31+LSBloc:LSBloc]; + * * RV64: + * LSBloc = Rs2[4:0]; + * ExtractW = Rs1[31+LSBloc:LSBloc]; + * Rd = SE(ExtractW) + * ~~~ + * + * \param [in] a long long type of value stored in a + * \param [in] b unsigned int type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_WEXT(long long a, unsigned int b) +{ + register unsigned long result; + __ASM volatile("wext %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 3.187. WEXT ===== */ + +/* ===== Inline Function Start for 3.188.1. ZUNPKD810 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_UNPACK + * \brief ZUNPKD810 (Unsigned Unpacking Bytes 1 & 0) + * \details + * **Type**: DSP + * + * **Syntax**:\n + * ~~~ + * ZUNPKD8xy Rd, Rs1 + * xy = {10, 20, 30, 31, 32} + * ~~~ + * + * **Purpose**:\n + * Unpack byte x and byte y of 32-bit chunks in a register into two 16-bit unsigned + * halfwords of 32-bit chunks in a register. + * + * **Description**:\n + * For the `ZUNPKD8(x)(*y*)` instruction, it unpacks byte *x and byte y* of 32-bit chunks in Rs1 into + * two 16-bit unsigned halfwords and writes the results to the top part and the bottom part of 32-bit + * chunks in Rd. + * + * **Operations**:\n + * ~~~ + * Rd.W[m].H[1] = ZE16(Rs1.W[m].B[x]) + * Rd.W[m].H[0] = ZE16(Rs1.W[m].B[y]) + * // ZUNPKD810, x=1,y=0 + * // ZUNPKD820, x=2,y=0 + * // ZUNPKD830, x=3,y=0 + * // ZUNPKD831, x=3,y=1 + * // ZUNPKD832, x=3,y=2 + * for RV32: m=0, + * for RV64: m=1...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_ZUNPKD810(unsigned long a) +{ + register unsigned long result; + __ASM volatile("zunpkd810 %0, %1" : "=r"(result) : "r"(a)); + return result; +} +/* ===== Inline Function End for 3.188.1. ZUNPKD810 ===== */ + +/* ===== Inline Function Start for 3.188.2. ZUNPKD820 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_UNPACK + * \brief ZUNPKD820 (Unsigned Unpacking Bytes 2 & 0) + * \details + * **Type**: DSP + * + * **Syntax**:\n + * ~~~ + * ZUNPKD8xy Rd, Rs1 + * xy = {10, 20, 30, 31, 32} + * ~~~ + * + * **Purpose**:\n + * Unpack byte x and byte y of 32-bit chunks in a register into two 16-bit unsigned + * halfwords of 32-bit chunks in a register. + * + * **Description**:\n + * For the `ZUNPKD8(x)(*y*)` instruction, it unpacks byte *x and byte y* of 32-bit chunks in Rs1 into + * two 16-bit unsigned halfwords and writes the results to the top part and the bottom part of 32-bit + * chunks in Rd. + * + * **Operations**:\n + * ~~~ + * Rd.W[m].H[1] = ZE16(Rs1.W[m].B[x]) + * Rd.W[m].H[0] = ZE16(Rs1.W[m].B[y]) + * // ZUNPKD810, x=1,y=0 + * // ZUNPKD820, x=2,y=0 + * // ZUNPKD830, x=3,y=0 + * // ZUNPKD831, x=3,y=1 + * // ZUNPKD832, x=3,y=2 + * for RV32: m=0, + * for RV64: m=1...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_ZUNPKD820(unsigned long a) +{ + register unsigned long result; + __ASM volatile("zunpkd820 %0, %1" : "=r"(result) : "r"(a)); + return result; +} +/* ===== Inline Function End for 3.188.2. ZUNPKD820 ===== */ + +/* ===== Inline Function Start for 3.188.3. ZUNPKD830 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_UNPACK + * \brief ZUNPKD830 (Unsigned Unpacking Bytes 3 & 0) + * \details + * **Type**: DSP + * + * **Syntax**:\n + * ~~~ + * ZUNPKD8xy Rd, Rs1 + * xy = {10, 20, 30, 31, 32} + * ~~~ + * + * **Purpose**:\n + * Unpack byte x and byte y of 32-bit chunks in a register into two 16-bit unsigned + * halfwords of 32-bit chunks in a register. + * + * **Description**:\n + * For the `ZUNPKD8(x)(*y*)` instruction, it unpacks byte *x and byte y* of 32-bit chunks in Rs1 into + * two 16-bit unsigned halfwords and writes the results to the top part and the bottom part of 32-bit + * chunks in Rd. + * + * **Operations**:\n + * ~~~ + * Rd.W[m].H[1] = ZE16(Rs1.W[m].B[x]) + * Rd.W[m].H[0] = ZE16(Rs1.W[m].B[y]) + * // ZUNPKD810, x=1,y=0 + * // ZUNPKD820, x=2,y=0 + * // ZUNPKD830, x=3,y=0 + * // ZUNPKD831, x=3,y=1 + * // ZUNPKD832, x=3,y=2 + * for RV32: m=0, + * for RV64: m=1...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_ZUNPKD830(unsigned long a) +{ + register unsigned long result; + __ASM volatile("zunpkd830 %0, %1" : "=r"(result) : "r"(a)); + return result; +} +/* ===== Inline Function End for 3.188.3. ZUNPKD830 ===== */ + +/* ===== Inline Function Start for 3.188.4. ZUNPKD831 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_UNPACK + * \brief ZUNPKD831 (Unsigned Unpacking Bytes 3 & 1) + * \details + * **Type**: DSP + * + * **Syntax**:\n + * ~~~ + * ZUNPKD8xy Rd, Rs1 + * xy = {10, 20, 30, 31, 32} + * ~~~ + * + * **Purpose**:\n + * Unpack byte x and byte y of 32-bit chunks in a register into two 16-bit unsigned + * halfwords of 32-bit chunks in a register. + * + * **Description**:\n + * For the `ZUNPKD8(x)(*y*)` instruction, it unpacks byte *x and byte y* of 32-bit chunks in Rs1 into + * two 16-bit unsigned halfwords and writes the results to the top part and the bottom part of 32-bit + * chunks in Rd. + * + * **Operations**:\n + * ~~~ + * Rd.W[m].H[1] = ZE16(Rs1.W[m].B[x]) + * Rd.W[m].H[0] = ZE16(Rs1.W[m].B[y]) + * // ZUNPKD810, x=1,y=0 + * // ZUNPKD820, x=2,y=0 + * // ZUNPKD830, x=3,y=0 + * // ZUNPKD831, x=3,y=1 + * // ZUNPKD832, x=3,y=2 + * for RV32: m=0, + * for RV64: m=1...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_ZUNPKD831(unsigned long a) +{ + register unsigned long result; + __ASM volatile("zunpkd831 %0, %1" : "=r"(result) : "r"(a)); + return result; +} +/* ===== Inline Function End for 3.188.4. ZUNPKD831 ===== */ + +/* ===== Inline Function Start for 3.188.5. ZUNPKD832 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_UNPACK + * \brief ZUNPKD832 (Unsigned Unpacking Bytes 3 & 2) + * \details + * **Type**: DSP + * + * **Syntax**:\n + * ~~~ + * ZUNPKD8xy Rd, Rs1 + * xy = {10, 20, 30, 31, 32} + * ~~~ + * + * **Purpose**:\n + * Unpack byte x and byte y of 32-bit chunks in a register into two 16-bit unsigned + * halfwords of 32-bit chunks in a register. + * + * **Description**:\n + * For the `ZUNPKD8(x)(*y*)` instruction, it unpacks byte *x and byte y* of 32-bit chunks in Rs1 into + * two 16-bit unsigned halfwords and writes the results to the top part and the bottom part of 32-bit + * chunks in Rd. + * + * **Operations**:\n + * ~~~ + * Rd.W[m].H[1] = ZE16(Rs1.W[m].B[x]) + * Rd.W[m].H[0] = ZE16(Rs1.W[m].B[y]) + * // ZUNPKD810, x=1,y=0 + * // ZUNPKD820, x=2,y=0 + * // ZUNPKD830, x=3,y=0 + * // ZUNPKD831, x=3,y=1 + * // ZUNPKD832, x=3,y=2 + * for RV32: m=0, + * for RV64: m=1...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_ZUNPKD832(unsigned long a) +{ + register unsigned long result; + __ASM volatile("zunpkd832 %0, %1" : "=r"(result) : "r"(a)); + return result; +} +/* ===== Inline Function End for 3.188.5. ZUNPKD832 ===== */ + +#if (__RISCV_XLEN == 64) || defined(__ONLY_FOR_DOXYGEN_DOCUMENT_GENERATION__) + +/* ===== Inline Function Start for 4.1. ADD32 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB + * \brief ADD32 (SIMD 32-bit Addition) + * \details + * **Type**: SIMD (RV64 Only) + * + * **Syntax**:\n + * ~~~ + * ADD32 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 32-bit integer element additions simultaneously. + * + * **Description**:\n + * This instruction adds the 32-bit integer elements in Rs1 with the 32-bit integer + * elements in Rs2, and then writes the 32-bit element results to Rd. + * + * **Note**:\n + * This instruction can be used for either signed or unsigned addition. + * + * **Operations**:\n + * ~~~ + * Rd.W[x] = Rs1.W[x] + Rs2.W[x]; + * for RV64: x=1...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_ADD32(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("add32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 4.1. ADD32 ===== */ + +/* ===== Inline Function Start for 4.2. CRAS32 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB + * \brief CRAS32 (SIMD 32-bit Cross Addition & Subtraction) + * \details + * **Type**: SIMD (RV64 Only) + * + * **Syntax**:\n + * ~~~ + * CRAS32 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 32-bit integer element addition and 32-bit integer element subtraction in a 64-bit + * chunk simultaneously. Operands are from crossed 32-bit elements. + * + * **Description**:\n + * This instruction adds the 32-bit integer element in [63:32] of Rs1 with the 32-bit + * integer element in [31:0] of Rs2, and writes the result to [63:32] of Rd; at the same time, it subtracts + * the 32-bit integer element in [63:32] of Rs2 from the 32-bit integer element in [31:0] of Rs1, and + * writes the result to [31:0] of Rd. + * + * **Note**:\n + * This instruction can be used for either signed or unsigned operations. + * + * **Operations**:\n + * ~~~ + * Rd.W[1] = Rs1.W[1] + Rs2.W[0]; + * Rd.W[0] = Rs1.W[0] - Rs2.W[1]; + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_CRAS32(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("cras32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 4.2. CRAS32 ===== */ + +/* ===== Inline Function Start for 4.3. CRSA32 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB + * \brief CRSA32 (SIMD 32-bit Cross Subtraction & Addition) + * \details + * **Type**: SIMD (RV64 Only) + * + * **Syntax**:\n + * ~~~ + * CRSA32 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 32-bit integer element subtraction and 32-bit integer element addition in a 64-bit + * chunk simultaneously. Operands are from crossed 32-bit elements. + * *Description: * + * This instruction subtracts the 32-bit integer element in [31:0] of Rs2 from the 32-bit integer element + * in [63:32] of Rs1, and writes the result to [63:32] of Rd; at the same time, it adds the 32-bit integer + * element in [31:0] of Rs1 with the 32-bit integer element in [63:32] of Rs2, and writes the result to + * [31:0] of Rd + * + * **Note**:\n + * This instruction can be used for either signed or unsigned operations. + * + * **Operations**:\n + * ~~~ + * Rd.W[1] = Rs1.W[1] - Rs2.W[0]; + * Rd.W[0] = Rs1.W[0] + Rs2.W[1]; + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_CRSA32(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("crsa32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 4.3. CRSA32 ===== */ + +/* ===== Inline Function Start for 4.4. KABS32 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_MISC + * \brief KABS32 (Scalar 32-bit Absolute Value with Saturation) + * \details + * **Type**: DSP (RV64 Only) +24 20 +19 15 +14 12 +11 7 +KABS32 +10010 +Rs1 +000 +Rd +6 0 +GE80B +1111111 + * + * **Syntax**:\n + * ~~~ + * KABS32 Rd, Rs1 + * ~~~ + * + * **Purpose**:\n + * Get the absolute value of signed 32-bit integer elements in a general register. + * + * **Description**:\n + * This instruction calculates the absolute value of signed 32-bit integer elements stored + * in Rs1. The results are written to Rd. This instruction with the minimum negative integer input of + * 0x80000000 will produce a saturated output of maximum positive integer of 0x7fffffff and the OV + * flag will be set to 1. + * + * **Operations**:\n + * ~~~ + * if (Rs1.W[x] >= 0) { + * res[x] = Rs1.W[x]; + * } else { + * If (Rs1.W[x] == 0x80000000) { + * res[x] = 0x7fffffff; + * OV = 1; + * } else { + * res[x] = -Rs1.W[x]; + * } + * } + * Rd.W[x] = res[x]; + * for RV64: x=1...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_KABS32(unsigned long a) +{ + register unsigned long result; + __ASM volatile("kabs32 %0, %1" : "=r"(result) : "r"(a)); + return result; +} +/* ===== Inline Function End for 4.4. KABS32 ===== */ + +/* ===== Inline Function Start for 4.5. KADD32 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB + * \brief KADD32 (SIMD 32-bit Signed Saturating Addition) + * \details + * **Type**: SIMD (RV64 Only) + * + * **Syntax**:\n + * ~~~ + * KADD32 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 32-bit signed integer element saturating additions simultaneously. + * + * **Description**:\n + * This instruction adds the 32-bit signed integer elements in Rs1 with the 32-bit signed + * integer elements in Rs2. If any of the results are beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), + * they are saturated to the range and the OV bit is set to 1. The saturated results are written to Rd. + * + * **Operations**:\n + * ~~~ + * res[x] = Rs1.W[x] + Rs2.W[x]; + * if (res[x] > (2^31)-1) { + * res[x] = (2^31)-1; + * OV = 1; + * } else if (res[x] < -2^31) { + * res[x] = -2^31; + * OV = 1; + * } + * Rd.W[x] = res[x]; + * for RV64: x=1...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_KADD32(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("kadd32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 4.5. KADD32 ===== */ + +/* ===== Inline Function Start for 4.6. KCRAS32 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB + * \brief KCRAS32 (SIMD 32-bit Signed Saturating Cross Addition & Subtraction) + * \details + * **Type**: SIM (RV64 Only) + * + * **Syntax**:\n + * ~~~ + * KCRAS32 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 32-bit signed integer element saturating addition and 32-bit signed integer element + * saturating subtraction in a 64-bit chunk simultaneously. Operands are from crossed 32-bit elements. + * + * **Description**:\n + * This instruction adds the 32-bit integer element in [63:32] of Rs1 with the 32-bit + * integer element in [31:0] of Rs2; at the same time, it subtracts the 32-bit integer element in [63:32] of + * Rs2 from the 32-bit integer element in [31:0] of Rs1. If any of the results are beyond the Q31 number + * range (-2^31 <= Q31 <= 2^31-1), they are saturated to the range and the OV bit is set to 1. The saturated + * results are written to [63:32] of Rd for addition and [31:0] of Rd for subtraction. + * + * **Operations**:\n + * ~~~ + * res[1] = Rs1.W[1] + Rs2.W[0]; + * res[0] = Rs1.W[0] - Rs2.W[1]; + * if (res[x] > (2^31)-1) { + * res[x] = (2^31)-1; + * OV = 1; + * } else if (res < -2^31) { + * res[x] = -2^31; + * OV = 1; + * } + * Rd.W[1] = res[1]; + * Rd.W[0] = res[0]; + * for RV64, x=1...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_KCRAS32(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("kcras32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 4.6. KCRAS32 ===== */ + +/* ===== Inline Function Start for 4.7. KCRSA32 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB + * \brief KCRSA32 (SIMD 32-bit Signed Saturating Cross Subtraction & Addition) + * \details + * **Type**: SIMD (RV64 Only) + * + * **Syntax**:\n + * ~~~ + * KCRSA32 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 32-bit signed integer element saturating subtraction and 32-bit signed integer element + * saturating addition in a 64-bit chunk simultaneously. Operands are from crossed 32-bit elements. + * *Description: * + * This instruction subtracts the 32-bit integer element in [31:0] of Rs2 from the 32-bit integer element + * in [63:32] of Rs1; at the same time, it adds the 32-bit integer element in [31:0] of Rs1 with the 32-bit + * integer element in [63:32] of Rs2. If any of the results are beyond the Q31 number range (-2^31 <= Q31 + * <= 2^31-1), they are saturated to the range and the OV bit is set to 1. The saturated results are written to + * [63:32] of Rd for subtraction and [31:0] of Rd for addition. + * + * **Operations**:\n + * ~~~ + * res[1] = Rs1.W[1] - Rs2.W[0]; + * res[0] = Rs1.W[0] + Rs2.W[1]; + * if (res[x] > (2^31)-1) { + * res[x] = (2^31)-1; + * OV = 1; + * } else if (res < -2^31) { + * res[x] = -2^31; + * OV = 1; + * } + * Rd.W[1] = res[1]; + * Rd.W[0] = res[0]; + * for RV64, x=1...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_KCRSA32(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("kcrsa32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 4.7. KCRSA32 ===== */ + +/* ===== Inline Function Start for 4.8.1. KDMBB16 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_Q15_SAT_MULT + * \brief KDMBB16 (SIMD Signed Saturating Double Multiply B16 x B16) + * \details + * **Type**: SIMD (RV64 only) + * + * **Syntax**:\n + * ~~~ + * KDMxy16 Rd, Rs1, Rs2 (xy = BB, BT, TT) + * ~~~ + * + * **Purpose**:\n + * Multiply the signed Q15 integer contents of two 16-bit data in the corresponding portion + * of the 32-bit chunks in registers and then double and saturate the Q31 results into the 32-bit chunks + * in the destination register. If saturation happens, an overflow flag OV will be set. + * + * **Description**:\n + * Multiply the top or bottom 16-bit Q15 content of the 32-bit portions in Rs1 with the top + * or bottom 16-bit Q15 content of the 32-bit portions in Rs2. The Q30 results are then doubled and + * saturated into Q31 values. The Q31 values are then written into the 32-bit chunks in Rd. When both + * the two Q15 inputs are 0x8000, saturation will happen. The result will be saturated to 0x7FFFFFFF + * and the overflow flag OV will be set. + * + * **Operations**:\n + * ~~~ + * // KDMBB16: (x,y,z)=(0,0,0),(2,2,1) + * // KDMBT16: (x,y,z)=(0,1,0),(2,3,1) + * // KDMTT16: (x,y,z)=(1,1,0),(3,3,1) + * aop[z] = Rs1.H[x]; bop[z] = Rs2.H[y]; + * If (0x8000 != aop[z] | 0x8000 != bop[z]) { + * Mresult[z] = aop[z] * bop[z]; + * resQ31[z] = Mresult[z] << 1; + * } else { + * resQ31[z] = 0x7FFFFFFF; + * OV = 1; + * } + * Rd.W[z] = resQ31[z]; + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_KDMBB16(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("kdmbb16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 4.8.1. KDMBB16 ===== */ + +/* ===== Inline Function Start for 4.8.2. KDMBT16 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_Q15_SAT_MULT + * \brief KDMBT16 (SIMD Signed Saturating Double Multiply B16 x T16) + * \details + * **Type**: SIMD (RV64 only) + * + * **Syntax**:\n + * ~~~ + * KDMxy16 Rd, Rs1, Rs2 (xy = BB, BT, TT) + * ~~~ + * + * **Purpose**:\n + * Multiply the signed Q15 integer contents of two 16-bit data in the corresponding portion + * of the 32-bit chunks in registers and then double and saturate the Q31 results into the 32-bit chunks + * in the destination register. If saturation happens, an overflow flag OV will be set. + * + * **Description**:\n + * Multiply the top or bottom 16-bit Q15 content of the 32-bit portions in Rs1 with the top + * or bottom 16-bit Q15 content of the 32-bit portions in Rs2. The Q30 results are then doubled and + * saturated into Q31 values. The Q31 values are then written into the 32-bit chunks in Rd. When both + * the two Q15 inputs are 0x8000, saturation will happen. The result will be saturated to 0x7FFFFFFF + * and the overflow flag OV will be set. + * + * **Operations**:\n + * ~~~ + * // KDMBB16: (x,y,z)=(0,0,0),(2,2,1) + * // KDMBT16: (x,y,z)=(0,1,0),(2,3,1) + * // KDMTT16: (x,y,z)=(1,1,0),(3,3,1) + * aop[z] = Rs1.H[x]; bop[z] = Rs2.H[y]; + * If (0x8000 != aop[z] | 0x8000 != bop[z]) { + * Mresult[z] = aop[z] * bop[z]; + * resQ31[z] = Mresult[z] << 1; + * } else { + * resQ31[z] = 0x7FFFFFFF; + * OV = 1; + * } + * Rd.W[z] = resQ31[z]; + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_KDMBT16(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("kdmbt16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 4.8.2. KDMBT16 ===== */ + +/* ===== Inline Function Start for 4.8.3. KDMTT16 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_Q15_SAT_MULT + * \brief KDMTT16 (SIMD Signed Saturating Double Multiply T16 x T16) + * \details + * **Type**: SIMD (RV64 only) + * + * **Syntax**:\n + * ~~~ + * KDMxy16 Rd, Rs1, Rs2 (xy = BB, BT, TT) + * ~~~ + * + * **Purpose**:\n + * Multiply the signed Q15 integer contents of two 16-bit data in the corresponding portion + * of the 32-bit chunks in registers and then double and saturate the Q31 results into the 32-bit chunks + * in the destination register. If saturation happens, an overflow flag OV will be set. + * + * **Description**:\n + * Multiply the top or bottom 16-bit Q15 content of the 32-bit portions in Rs1 with the top + * or bottom 16-bit Q15 content of the 32-bit portions in Rs2. The Q30 results are then doubled and + * saturated into Q31 values. The Q31 values are then written into the 32-bit chunks in Rd. When both + * the two Q15 inputs are 0x8000, saturation will happen. The result will be saturated to 0x7FFFFFFF + * and the overflow flag OV will be set. + * + * **Operations**:\n + * ~~~ + * // KDMBB16: (x,y,z)=(0,0,0),(2,2,1) + * // KDMBT16: (x,y,z)=(0,1,0),(2,3,1) + * // KDMTT16: (x,y,z)=(1,1,0),(3,3,1) + * aop[z] = Rs1.H[x]; bop[z] = Rs2.H[y]; + * If (0x8000 != aop[z] | 0x8000 != bop[z]) { + * Mresult[z] = aop[z] * bop[z]; + * resQ31[z] = Mresult[z] << 1; + * } else { + * resQ31[z] = 0x7FFFFFFF; + * OV = 1; + * } + * Rd.W[z] = resQ31[z]; + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_KDMTT16(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("kdmtt16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 4.8.3. KDMTT16 ===== */ + +/* ===== Inline Function Start for 4.9.1. KDMABB16 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_Q15_SAT_MULT + * \brief KDMABB16 (SIMD Signed Saturating Double Multiply Addition B16 x B16) + * \details + * **Type**: SIMD (RV64 only) + * + * **Syntax**:\n + * ~~~ + * KDMAxy16 Rd, Rs1, Rs2 (xy = BB, BT, TT) + * ~~~ + * + * **Purpose**:\n + * Multiply the signed Q15 integer contents of two 16-bit data in the corresponding portion + * of the 32-bit chunks in registers and then double and saturate the Q31 results, add the results with + * the values of the corresponding 32-bit chunks from the destination register and write the saturated + * addition results back into the corresponding 32-bit chunks of the destination register. If saturation + * happens, an overflow flag OV will be set. + * + * **Description**:\n + * Multiply the top or bottom 16-bit Q15 content of the 32-bit portions in Rs1 with the top + * or bottom 16-bit Q15 content of the corresponding 32-bit portions in Rs2. The Q30 results are then + * doubled and saturated into Q31 values. The Q31 values are then added with the content of the + * corresponding 32-bit portions of Rd. If the addition results are beyond the Q31 number range (-2^31 <= + * Q31 <= 2^31-1), they are saturated to the range and the OV flag is set to 1. The results after saturation + * are written back to Rd. + * When both the two Q15 inputs are 0x8000, saturation will happen and the overflow flag OV will be + * set. + * + * **Operations**:\n + * ~~~ + * // KDMABB16: (x,y,z)=(0,0,0),(2,2,1) + * // KDMABT16: (x,y,z)=(0,1,0),(2,3,1) + * // KDMATT16: (x,y,z)=(1,1,0),(3,3,1) + * aop[z] = Rs1.H[x]; bop[z] = Rs2.H[y]; + * If (0x8000 != aop[z] | 0x8000 != bop[z]) { + * Mresult[z] = aop[z] * bop[z]; + * resQ31[z] = Mresult[z] << 1; + * } else { + * resQ31[z] = 0x7FFFFFFF; + * OV = 1; + * } + * resadd[z] = Rd.W[z] + resQ31[z]; + * if (resadd[z] > (2^31)-1) { + * resadd[z] = (2^31)-1; + * OV = 1; + * } else if (resadd[z] < -2^31) { + * resadd[z] = -2^31; + * OV = 1; + * } + * Rd.W[z] = resadd[z]; + * ~~~ + * + * \param [in] t unsigned long type of value stored in t + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_KDMABB16(unsigned long t, unsigned long a, unsigned long b) +{ + __ASM volatile("kdmabb16 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); + return t; +} +/* ===== Inline Function End for 4.9.1. KDMABB16 ===== */ + +/* ===== Inline Function Start for 4.9.2. KDMABT16 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_Q15_SAT_MULT + * \brief KDMABT16 (SIMD Signed Saturating Double Multiply Addition B16 x T16) + * \details + * **Type**: SIMD (RV64 only) + * + * **Syntax**:\n + * ~~~ + * KDMAxy16 Rd, Rs1, Rs2 (xy = BB, BT, TT) + * ~~~ + * + * **Purpose**:\n + * Multiply the signed Q15 integer contents of two 16-bit data in the corresponding portion + * of the 32-bit chunks in registers and then double and saturate the Q31 results, add the results with + * the values of the corresponding 32-bit chunks from the destination register and write the saturated + * addition results back into the corresponding 32-bit chunks of the destination register. If saturation + * happens, an overflow flag OV will be set. + * + * **Description**:\n + * Multiply the top or bottom 16-bit Q15 content of the 32-bit portions in Rs1 with the top + * or bottom 16-bit Q15 content of the corresponding 32-bit portions in Rs2. The Q30 results are then + * doubled and saturated into Q31 values. The Q31 values are then added with the content of the + * corresponding 32-bit portions of Rd. If the addition results are beyond the Q31 number range (-2^31 <= + * Q31 <= 2^31-1), they are saturated to the range and the OV flag is set to 1. The results after saturation + * are written back to Rd. + * When both the two Q15 inputs are 0x8000, saturation will happen and the overflow flag OV will be + * set. + * + * **Operations**:\n + * ~~~ + * // KDMABB16: (x,y,z)=(0,0,0),(2,2,1) + * // KDMABT16: (x,y,z)=(0,1,0),(2,3,1) + * // KDMATT16: (x,y,z)=(1,1,0),(3,3,1) + * aop[z] = Rs1.H[x]; bop[z] = Rs2.H[y]; + * If (0x8000 != aop[z] | 0x8000 != bop[z]) { + * Mresult[z] = aop[z] * bop[z]; + * resQ31[z] = Mresult[z] << 1; + * } else { + * resQ31[z] = 0x7FFFFFFF; + * OV = 1; + * } + * resadd[z] = Rd.W[z] + resQ31[z]; + * if (resadd[z] > (2^31)-1) { + * resadd[z] = (2^31)-1; + * OV = 1; + * } else if (resadd[z] < -2^31) { + * resadd[z] = -2^31; + * OV = 1; + * } + * Rd.W[z] = resadd[z]; + * ~~~ + * + * \param [in] t unsigned long type of value stored in t + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_KDMABT16(unsigned long t, unsigned long a, unsigned long b) +{ + __ASM volatile("kdmabt16 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); + return t; +} +/* ===== Inline Function End for 4.9.2. KDMABT16 ===== */ + +/* ===== Inline Function Start for 4.9.3. KDMATT16 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_Q15_SAT_MULT + * \brief KDMATT16 (SIMD Signed Saturating Double Multiply Addition T16 x T16) + * \details + * **Type**: SIMD (RV64 only) + * + * **Syntax**:\n + * ~~~ + * KDMAxy16 Rd, Rs1, Rs2 (xy = BB, BT, TT) + * ~~~ + * + * **Purpose**:\n + * Multiply the signed Q15 integer contents of two 16-bit data in the corresponding portion + * of the 32-bit chunks in registers and then double and saturate the Q31 results, add the results with + * the values of the corresponding 32-bit chunks from the destination register and write the saturated + * addition results back into the corresponding 32-bit chunks of the destination register. If saturation + * happens, an overflow flag OV will be set. + * + * **Description**:\n + * Multiply the top or bottom 16-bit Q15 content of the 32-bit portions in Rs1 with the top + * or bottom 16-bit Q15 content of the corresponding 32-bit portions in Rs2. The Q30 results are then + * doubled and saturated into Q31 values. The Q31 values are then added with the content of the + * corresponding 32-bit portions of Rd. If the addition results are beyond the Q31 number range (-2^31 <= + * Q31 <= 2^31-1), they are saturated to the range and the OV flag is set to 1. The results after saturation + * are written back to Rd. + * When both the two Q15 inputs are 0x8000, saturation will happen and the overflow flag OV will be + * set. + * + * **Operations**:\n + * ~~~ + * // KDMABB16: (x,y,z)=(0,0,0),(2,2,1) + * // KDMABT16: (x,y,z)=(0,1,0),(2,3,1) + * // KDMATT16: (x,y,z)=(1,1,0),(3,3,1) + * aop[z] = Rs1.H[x]; bop[z] = Rs2.H[y]; + * If (0x8000 != aop[z] | 0x8000 != bop[z]) { + * Mresult[z] = aop[z] * bop[z]; + * resQ31[z] = Mresult[z] << 1; + * } else { + * resQ31[z] = 0x7FFFFFFF; + * OV = 1; + * } + * resadd[z] = Rd.W[z] + resQ31[z]; + * if (resadd[z] > (2^31)-1) { + * resadd[z] = (2^31)-1; + * OV = 1; + * } else if (resadd[z] < -2^31) { + * resadd[z] = -2^31; + * OV = 1; + * } + * Rd.W[z] = resadd[z]; + * ~~~ + * + * \param [in] t unsigned long type of value stored in t + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_KDMATT16(unsigned long t, unsigned long a, unsigned long b) +{ + __ASM volatile("kdmatt16 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); + return t; +} +/* ===== Inline Function End for 4.9.3. KDMATT16 ===== */ + +/* ===== Inline Function Start for 4.10.1. KHMBB16 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_Q15_SAT_MULT + * \brief KHMBB16 (SIMD Signed Saturating Half Multiply B16 x B16) + * \details + * **Type**: SIMD (RV64 Only) + * + * **Syntax**:\n + * ~~~ + * KHMxy16 Rd, Rs1, Rs2 (xy = BB, BT, TT) + * ~~~ + * + * **Purpose**:\n + * Multiply the signed Q15 integer contents of two 16-bit data in the corresponding portion + * of the 32-bit chunks in registers and then right-shift 15 bits to turn the Q30 results into Q15 + * numbers again and saturate the Q15 results into the destination register. If saturation happens, an + * overflow flag OV will be set. + * + * **Description**:\n + * Multiply the top or bottom 16-bit Q15 content of the 32-bit portions in Rs1 with the top + * or bottom 16-bit Q15 content of the 32-bit portion in Rs2. The Q30 results are then right-shifted 15- + * bits and saturated into Q15 values. The 32-bit Q15 values are then written into the 32-bit chunks in + * Rd. When both the two Q15 inputs are 0x8000, saturation will happen. The result will be saturated + * to 0x7FFF and the overflow flag OV will be set. + * + * **Operations**:\n + * ~~~ + * // KHMBB16: (x,y,z)=(0,0,0),(2,2,1) + * // KHMBT16: (x,y,z)=(0,1,0),(2,3,1) + * // KHMTT16: (x,y,z)=(1,1,0),(3,3,1) + * aop = Rs1.H[x]; bop = Rs2.H[y]; + * If (0x8000 != aop | 0x8000 != bop) { + * Mresult[31:0] = aop * bop; + * res[15:0] = Mresult[30:15]; + * } else { + * res[15:0] = 0x7FFF; + * OV = 1; + * } + * Rd.W[z] = SE32(res[15:0]); + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_KHMBB16(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("khmbb16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 4.10.1. KHMBB16 ===== */ + +/* ===== Inline Function Start for 4.10.2. KHMBT16 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_Q15_SAT_MULT + * \brief KHMBT16 (SIMD Signed Saturating Half Multiply B16 x T16) + * \details + * **Type**: SIMD (RV64 Only) + * + * **Syntax**:\n + * ~~~ + * KHMxy16 Rd, Rs1, Rs2 (xy = BB, BT, TT) + * ~~~ + * + * **Purpose**:\n + * Multiply the signed Q15 integer contents of two 16-bit data in the corresponding portion + * of the 32-bit chunks in registers and then right-shift 15 bits to turn the Q30 results into Q15 + * numbers again and saturate the Q15 results into the destination register. If saturation happens, an + * overflow flag OV will be set. + * + * **Description**:\n + * Multiply the top or bottom 16-bit Q15 content of the 32-bit portions in Rs1 with the top + * or bottom 16-bit Q15 content of the 32-bit portion in Rs2. The Q30 results are then right-shifted 15- + * bits and saturated into Q15 values. The 32-bit Q15 values are then written into the 32-bit chunks in + * Rd. When both the two Q15 inputs are 0x8000, saturation will happen. The result will be saturated + * to 0x7FFF and the overflow flag OV will be set. + * + * **Operations**:\n + * ~~~ + * // KHMBB16: (x,y,z)=(0,0,0),(2,2,1) + * // KHMBT16: (x,y,z)=(0,1,0),(2,3,1) + * // KHMTT16: (x,y,z)=(1,1,0),(3,3,1) + * aop = Rs1.H[x]; bop = Rs2.H[y]; + * If (0x8000 != aop | 0x8000 != bop) { + * Mresult[31:0] = aop * bop; + * res[15:0] = Mresult[30:15]; + * } else { + * res[15:0] = 0x7FFF; + * OV = 1; + * } + * Rd.W[z] = SE32(res[15:0]); + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_KHMBT16(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("khmbt16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 4.10.2. KHMBT16 ===== */ + +/* ===== Inline Function Start for 4.10.3. KHMTT16 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_Q15_SAT_MULT + * \brief KHMTT16 (SIMD Signed Saturating Half Multiply T16 x T16) + * \details + * **Type**: SIMD (RV64 Only) + * + * **Syntax**:\n + * ~~~ + * KHMxy16 Rd, Rs1, Rs2 (xy = BB, BT, TT) + * ~~~ + * + * **Purpose**:\n + * Multiply the signed Q15 integer contents of two 16-bit data in the corresponding portion + * of the 32-bit chunks in registers and then right-shift 15 bits to turn the Q30 results into Q15 + * numbers again and saturate the Q15 results into the destination register. If saturation happens, an + * overflow flag OV will be set. + * + * **Description**:\n + * Multiply the top or bottom 16-bit Q15 content of the 32-bit portions in Rs1 with the top + * or bottom 16-bit Q15 content of the 32-bit portion in Rs2. The Q30 results are then right-shifted 15- + * bits and saturated into Q15 values. The 32-bit Q15 values are then written into the 32-bit chunks in + * Rd. When both the two Q15 inputs are 0x8000, saturation will happen. The result will be saturated + * to 0x7FFF and the overflow flag OV will be set. + * + * **Operations**:\n + * ~~~ + * // KHMBB16: (x,y,z)=(0,0,0),(2,2,1) + * // KHMBT16: (x,y,z)=(0,1,0),(2,3,1) + * // KHMTT16: (x,y,z)=(1,1,0),(3,3,1) + * aop = Rs1.H[x]; bop = Rs2.H[y]; + * If (0x8000 != aop | 0x8000 != bop) { + * Mresult[31:0] = aop * bop; + * res[15:0] = Mresult[30:15]; + * } else { + * res[15:0] = 0x7FFF; + * OV = 1; + * } + * Rd.W[z] = SE32(res[15:0]); + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_KHMTT16(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("khmtt16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 4.10.3. KHMTT16 ===== */ + +/* ===== Inline Function Start for 4.11.1. KMABB32 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_MULT_ADD + * \brief KMABB32 (Saturating Signed Multiply Bottom Words & Add) + * \details + * **Type**: DSP (RV64 Only) + * + * **Syntax**:\n + * ~~~ + * KMABB32 Rd, Rs1, Rs2 + * KMABT32 Rd, Rs1, Rs2 + * KMATT32 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Multiply the signed 32-bit element in a register with the 32-bit element in another register + * and add the result to the content of 64-bit data in the third register. The addition result may be + * saturated and is written to the third register. + * * KMABB32: rd + bottom*bottom + * * KMABT32: rd + bottom*top + * * KMATT32: rd + top*top + * + * **Description**:\n + * For the `KMABB32` instruction, it multiplies the bottom 32-bit element in Rs1 with the bottom 32-bit + * element in Rs2. + * For the `KMABT32` instruction, it multiplies the bottom 32-bit element in Rs1 with the top 32-bit + * element in Rs2. + * For the `KMATT32` instruction, it multiplies the top 32-bit element in Rs1 with the top 32-bit + * element in Rs2. + * The multiplication result is added to the content of 64-bit data in Rd. If the addition result is beyond + * the Q63 number range (-2^63 <= Q63 <= 2^63-1), it is saturated to the range and the OV bit is set to 1. The + * result after saturation is written to Rd. The 32-bit contents of Rs1 and Rs2 are treated as signed + * integers. + * + * **Operations**:\n + * ~~~ + * res = Rd + (Rs1.W[0] * Rs2.W[0]); // KMABB32 + * res = Rd + (Rs1.W[0] * Rs2.W[1]); // KMABT32 + * res = Rd + (Rs1.W[1] * Rs2.W[1]); // KMATT32 + * if (res > (2^63)-1) { + * res = (2^63)-1; + * OV = 1; + * } else if (res < -2^63) { + * res = -2^63; + * OV = 1; + * } + * Rd = res; + * *Exceptions:* None + * ~~~ + * + * \param [in] t long type of value stored in t + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_KMABB32(long t, unsigned long a, unsigned long b) +{ + __ASM volatile("kmabb32 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); + return t; +} +/* ===== Inline Function End for 4.11.1. KMABB32 ===== */ + +/* ===== Inline Function Start for 4.11.2. KMABT32 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_MULT_ADD + * \brief KMABT32 (Saturating Signed Multiply Bottom & Top Words & Add) + * \details + * **Type**: DSP (RV64 Only) + * + * **Syntax**:\n + * ~~~ + * KMABB32 Rd, Rs1, Rs2 + * KMABT32 Rd, Rs1, Rs2 + * KMATT32 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Multiply the signed 32-bit element in a register with the 32-bit element in another register + * and add the result to the content of 64-bit data in the third register. The addition result may be + * saturated and is written to the third register. + * * KMABB32: rd + bottom*bottom + * * KMABT32: rd + bottom*top + * * KMATT32: rd + top*top + * + * **Description**:\n + * For the `KMABB32` instruction, it multiplies the bottom 32-bit element in Rs1 with the bottom 32-bit + * element in Rs2. + * For the `KMABT32` instruction, it multiplies the bottom 32-bit element in Rs1 with the top 32-bit + * element in Rs2. + * For the `KMATT32` instruction, it multiplies the top 32-bit element in Rs1 with the top 32-bit + * element in Rs2. + * The multiplication result is added to the content of 64-bit data in Rd. If the addition result is beyond + * the Q63 number range (-2^63 <= Q63 <= 2^63-1), it is saturated to the range and the OV bit is set to 1. The + * result after saturation is written to Rd. The 32-bit contents of Rs1 and Rs2 are treated as signed + * integers. + * + * **Operations**:\n + * ~~~ + * res = Rd + (Rs1.W[0] * Rs2.W[0]); // KMABB32 + * res = Rd + (Rs1.W[0] * Rs2.W[1]); // KMABT32 + * res = Rd + (Rs1.W[1] * Rs2.W[1]); // KMATT32 + * if (res > (2^63)-1) { + * res = (2^63)-1; + * OV = 1; + * } else if (res < -2^63) { + * res = -2^63; + * OV = 1; + * } + * Rd = res; + * *Exceptions:* None + * ~~~ + * + * \param [in] t long type of value stored in t + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_KMABT32(long t, unsigned long a, unsigned long b) +{ + __ASM volatile("kmabt32 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); + return t; +} +/* ===== Inline Function End for 4.11.2. KMABT32 ===== */ + +/* ===== Inline Function Start for 4.11.3. KMATT32 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_MULT_ADD + * \brief KMATT32 (Saturating Signed Multiply Top Words & Add) + * \details + * **Type**: DSP (RV64 Only) + * + * **Syntax**:\n + * ~~~ + * KMABB32 Rd, Rs1, Rs2 + * KMABT32 Rd, Rs1, Rs2 + * KMATT32 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Multiply the signed 32-bit element in a register with the 32-bit element in another register + * and add the result to the content of 64-bit data in the third register. The addition result may be + * saturated and is written to the third register. + * * KMABB32: rd + bottom*bottom + * * KMABT32: rd + bottom*top + * * KMATT32: rd + top*top + * + * **Description**:\n + * For the `KMABB32` instruction, it multiplies the bottom 32-bit element in Rs1 with the bottom 32-bit + * element in Rs2. + * For the `KMABT32` instruction, it multiplies the bottom 32-bit element in Rs1 with the top 32-bit + * element in Rs2. + * For the `KMATT32` instruction, it multiplies the top 32-bit element in Rs1 with the top 32-bit + * element in Rs2. + * The multiplication result is added to the content of 64-bit data in Rd. If the addition result is beyond + * the Q63 number range (-2^63 <= Q63 <= 2^63-1), it is saturated to the range and the OV bit is set to 1. The + * result after saturation is written to Rd. The 32-bit contents of Rs1 and Rs2 are treated as signed + * integers. + * + * **Operations**:\n + * ~~~ + * res = Rd + (Rs1.W[0] * Rs2.W[0]); // KMABB32 + * res = Rd + (Rs1.W[0] * Rs2.W[1]); // KMABT32 + * res = Rd + (Rs1.W[1] * Rs2.W[1]); // KMATT32 + * if (res > (2^63)-1) { + * res = (2^63)-1; + * OV = 1; + * } else if (res < -2^63) { + * res = -2^63; + * OV = 1; + * } + * Rd = res; + * *Exceptions:* None + * ~~~ + * + * \param [in] t long type of value stored in t + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_KMATT32(long t, unsigned long a, unsigned long b) +{ + __ASM volatile("kmatt32 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); + return t; +} +/* ===== Inline Function End for 4.11.3. KMATT32 ===== */ + +/* ===== Inline Function Start for 4.12.1. KMADA32 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_PARALLEL_MAC + * \brief KMADA32 (Saturating Signed Multiply Two Words and Two Adds) + * \details + * **Type**: DSP (RV64 Only) + * + * **Syntax**:\n + * ~~~ + * KMADA32 Rd, Rs1, Rs2 + * KMAXDA32 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do two signed 32-bit multiplications from 32-bit data in two registers; and then adds the + * two 64-bit results and 64-bit data in a third register together. The addition result may be saturated. + * * KMADA32: rd + top*top + bottom*bottom + * * KMAXDA32: rd + top*bottom + bottom*top + * + * **Description**:\n + * For the `KMADA32` instruction, it multiplies the bottom 32-bit element in Rs1 with the bottom 32- + * bit element in Rs2 and then adds the result to the result of multiplying the top 32-bit element in Rs1 + * with the top 32-bit element in Rs2. It is actually an alias of the `KMAR64` instruction. + * For the `KMAXDA32` instruction, it multiplies the top 32-bit element in Rs1 with the bottom 32-bit + * element in Rs2 and then adds the result to the result of multiplying the bottom 32-bit element in Rs1 + * with the top 32-bit element in Rs2. + * The result is added to the content of 64-bit data in Rd. If the addition result is beyond the Q63 + * number range (-2^63 <= Q63 <= 2^63-1), it is saturated to the range and the OV bit is set to 1. The 64-bit + * result is written to Rd. The 32-bit contents of Rs1 and Rs2 are treated as signed integers. + * + * **Operations**:\n + * ~~~ + * res = Rd + (Rs1.W[1] * Rs2.w[1]) + (Rs1.W[0] * Rs2.W[0]); // KMADA32 + * res = Rd + (Rs1.W[1] * Rs2.W[0]) + (Rs1.W[0] * Rs2.W[1]); // KMAXDA32 + * if (res > (2^63)-1) { + * res = (2^63)-1; + * OV = 1; + * } else if (res < -2^63) { + * res = -2^63; + * OV = 1; + * } + * Rd = res; + * ~~~ + * + * \param [in] t long type of value stored in t + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_KMADA32(long t, unsigned long a, unsigned long b) +{ + __ASM volatile("kmada32 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); + return t; +} +/* ===== Inline Function End for 4.12.1. KMADA32 ===== */ + +/* ===== Inline Function Start for 4.12.2. KMAXDA32 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_PARALLEL_MAC + * \brief KMAXDA32 (Saturating Signed Crossed Multiply Two Words and Two Adds) + * \details + * **Type**: DSP (RV64 Only) + * + * **Syntax**:\n + * ~~~ + * KMADA32 Rd, Rs1, Rs2 + * KMAXDA32 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do two signed 32-bit multiplications from 32-bit data in two registers; and then adds the + * two 64-bit results and 64-bit data in a third register together. The addition result may be saturated. + * * KMADA32: rd + top*top + bottom*bottom + * * KMAXDA32: rd + top*bottom + bottom*top + * + * **Description**:\n + * For the `KMADA32` instruction, it multiplies the bottom 32-bit element in Rs1 with the bottom 32- + * bit element in Rs2 and then adds the result to the result of multiplying the top 32-bit element in Rs1 + * with the top 32-bit element in Rs2. It is actually an alias of the `KMAR64` instruction. + * For the `KMAXDA32` instruction, it multiplies the top 32-bit element in Rs1 with the bottom 32-bit + * element in Rs2 and then adds the result to the result of multiplying the bottom 32-bit element in Rs1 + * with the top 32-bit element in Rs2. + * The result is added to the content of 64-bit data in Rd. If the addition result is beyond the Q63 + * number range (-2^63 <= Q63 <= 2^63-1), it is saturated to the range and the OV bit is set to 1. The 64-bit + * result is written to Rd. The 32-bit contents of Rs1 and Rs2 are treated as signed integers. + * + * **Operations**:\n + * ~~~ + * res = Rd + (Rs1.W[1] * Rs2.w[1]) + (Rs1.W[0] * Rs2.W[0]); // KMADA32 + * res = Rd + (Rs1.W[1] * Rs2.W[0]) + (Rs1.W[0] * Rs2.W[1]); // KMAXDA32 + * if (res > (2^63)-1) { + * res = (2^63)-1; + * OV = 1; + * } else if (res < -2^63) { + * res = -2^63; + * OV = 1; + * } + * Rd = res; + * ~~~ + * + * \param [in] t long type of value stored in t + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_KMAXDA32(long t, unsigned long a, unsigned long b) +{ + __ASM volatile("kmaxda32 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); + return t; +} +/* ===== Inline Function End for 4.12.2. KMAXDA32 ===== */ + +/* ===== Inline Function Start for 4.13.1. KMDA32 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_PARALLEL_MAC + * \brief KMDA32 (Signed Multiply Two Words and Add) + * \details + * **Type**: DSP (RV64 Only) + * + * **Syntax**:\n + * ~~~ + * KMDA32 Rd, Rs1, Rs2 + * KMXDA32 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do two signed 32-bit multiplications from the 32-bit element of two registers; and then + * adds the two 64-bit results together. The addition result may be saturated. + * * KMDA32: top*top + bottom*bottom + * * KMXDA32: top*bottom + bottom*top + * + * **Description**:\n + * For the `KMDA32` instruction, it multiplies the bottom 32-bit element of Rs1 with the bottom 32-bit + * element of Rs2 and then adds the result to the result of multiplying the top 32-bit element of Rs1 + * with the top 32-bit element of Rs2. + * For the `KMXDA32` instruction, it multiplies the bottom 32-bit element of Rs1 with the top 32-bit + * element of Rs2 and then adds the result to the result of multiplying the top 32-bit element of Rs1 + * with the bottom 32-bit element of Rs2. + * The addition result is checked for saturation. If saturation happens, the result is saturated to 2^63-1. + * The final result is written to Rd. The 32-bit contents are treated as signed integers. + * + * **Operations**:\n + * ~~~ + * if ((Rs1 != 0x8000000080000000) or (Rs2 != 0x8000000080000000)) { + * Rd = (Rs1.W[1] * Rs2.W[1]) + (Rs1.W[0] * Rs2.W[0]); // KMDA32 + * Rd = (Rs1.W[1] * Rs2.W[0]) + (Rs1.W[0] * Rs2.W[1]); // KMXDA32 + * } else { + * Rd = 0x7fffffffffffffff; + * OV = 1; + * } + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_KMDA32(unsigned long a, unsigned long b) +{ + register long result; + __ASM volatile("kmda32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 4.13.1. KMDA32 ===== */ + +/* ===== Inline Function Start for 4.13.2. KMXDA32 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_PARALLEL_MAC + * \brief KMXDA32 (Signed Crossed Multiply Two Words and Add) + * \details + * **Type**: DSP (RV64 Only) + * + * **Syntax**:\n + * ~~~ + * KMDA32 Rd, Rs1, Rs2 + * KMXDA32 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do two signed 32-bit multiplications from the 32-bit element of two registers; and then + * adds the two 64-bit results together. The addition result may be saturated. + * * KMDA32: top*top + bottom*bottom + * * KMXDA32: top*bottom + bottom*top + * + * **Description**:\n + * For the `KMDA32` instruction, it multiplies the bottom 32-bit element of Rs1 with the bottom 32-bit + * element of Rs2 and then adds the result to the result of multiplying the top 32-bit element of Rs1 + * with the top 32-bit element of Rs2. + * For the `KMXDA32` instruction, it multiplies the bottom 32-bit element of Rs1 with the top 32-bit + * element of Rs2 and then adds the result to the result of multiplying the top 32-bit element of Rs1 + * with the bottom 32-bit element of Rs2. + * The addition result is checked for saturation. If saturation happens, the result is saturated to 2^63-1. + * The final result is written to Rd. The 32-bit contents are treated as signed integers. + * + * **Operations**:\n + * ~~~ + * if ((Rs1 != 0x8000000080000000) or (Rs2 != 0x8000000080000000)) { + * Rd = (Rs1.W[1] * Rs2.W[1]) + (Rs1.W[0] * Rs2.W[0]); // KMDA32 + * Rd = (Rs1.W[1] * Rs2.W[0]) + (Rs1.W[0] * Rs2.W[1]); // KMXDA32 + * } else { + * Rd = 0x7fffffffffffffff; + * OV = 1; + * } + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_KMXDA32(unsigned long a, unsigned long b) +{ + register long result; + __ASM volatile("kmxda32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 4.13.2. KMXDA32 ===== */ + +/* ===== Inline Function Start for 4.14.1. KMADS32 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_PARALLEL_MAC + * \brief KMADS32 (Saturating Signed Multiply Two Words & Subtract & Add) + * \details + * **Type**: DSP (RV64 Only) + * + * **Syntax**:\n + * ~~~ + * KMADS32 Rd, Rs1, Rs2 + * KMADRS32 Rd, Rs1, Rs2 + * KMAXDS32 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do two signed 32-bit multiplications from 32-bit elements in two registers; and then + * perform a subtraction operation between the two 64-bit results. Then add the subtraction result to + * 64-bit data in a third register. The addition result may be saturated. + * * KMADS32: rd + (top*top - bottom*bottom) + * * KMADRS32: rd + (bottom*bottom - top*top) + * * KMAXDS32: rd + (top*bottom - bottom*top) + * + * **Description**:\n + * For the `KMADS32` instruction, it multiplies the bottom 32-bit element in Rs1 with the bottom 32-bit + * element in Rs2 and then subtracts the result from the result of multiplying the top 32-bit element in + * Rs1 with the top 32-bit element in Rs2. + * For the `KMADRS32` instruction, it multiplies the top 32-bit element in Rs1 with the top 32-bit + * element in Rs2 and then subtracts the result from the result of multiplying the bottom 32-bit + * element in Rs1 with the bottom 32-bit element in Rs2. + * For the `KMAXDS32` instruction, it multiplies the bottom 32-bit element in Rs1 with the top 32-bit + * element in Rs2 and then subtracts the result from the result of multiplying the top 32-bit element in + * Rs1 with the bottom 32-bit element in Rs2. + * The subtraction result is then added to the content of 64-bit data in Rd. If the addition result is + * beyond the Q63 number range (-2^63 <= Q63 <= 2^63-1), it is saturated to the range and the OV bit is set to + * 1. The 64-bit result after saturation is written to Rd. The 32-bit contents of Rs1 and Rs2 are treated + * as signed integers. + * + * **Operations**:\n + * ~~~ + * res = Rd + (Rs1.W[1] * Rs2.W[1]) - (Rs1.W[0] * Rs2.W[0]); // KMADS32 + * res = Rd + (Rs1.W[0] * Rs2.W[0]) - (Rs1.W[1] * Rs2.W[1]); // KMADRS32 + * res = Rd + (Rs1.W[1] * Rs2.W[0]) - (Rs1.W[0] * Rs2.W[1]); // KMAXDS32 + * if (res > (2^63)-1) { + * res = (2^63)-1; + * OV = 1; + * } else if (res < -2^63) { + * res = -2^63; + * OV = 1; + * } + * Rd = res; + * ~~~ + * + * \param [in] t long type of value stored in t + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_KMADS32(long t, unsigned long a, unsigned long b) +{ + __ASM volatile("kmads32 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); + return t; +} +/* ===== Inline Function End for 4.14.1. KMADS32 ===== */ + +/* ===== Inline Function Start for 4.14.2. KMADRS32 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_PARALLEL_MAC + * \brief KMADRS32 (Saturating Signed Multiply Two Words & Reverse Subtract & Add) + * \details + * **Type**: DSP (RV64 Only) + * + * **Syntax**:\n + * ~~~ + * KMADS32 Rd, Rs1, Rs2 + * KMADRS32 Rd, Rs1, Rs2 + * KMAXDS32 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do two signed 32-bit multiplications from 32-bit elements in two registers; and then + * perform a subtraction operation between the two 64-bit results. Then add the subtraction result to + * 64-bit data in a third register. The addition result may be saturated. + * * KMADS32: rd + (top*top - bottom*bottom) + * * KMADRS32: rd + (bottom*bottom - top*top) + * * KMAXDS32: rd + (top*bottom - bottom*top) + * + * **Description**:\n + * For the `KMADS32` instruction, it multiplies the bottom 32-bit element in Rs1 with the bottom 32-bit + * element in Rs2 and then subtracts the result from the result of multiplying the top 32-bit element in + * Rs1 with the top 32-bit element in Rs2. + * For the `KMADRS32` instruction, it multiplies the top 32-bit element in Rs1 with the top 32-bit + * element in Rs2 and then subtracts the result from the result of multiplying the bottom 32-bit + * element in Rs1 with the bottom 32-bit element in Rs2. + * For the `KMAXDS32` instruction, it multiplies the bottom 32-bit element in Rs1 with the top 32-bit + * element in Rs2 and then subtracts the result from the result of multiplying the top 32-bit element in + * Rs1 with the bottom 32-bit element in Rs2. + * The subtraction result is then added to the content of 64-bit data in Rd. If the addition result is + * beyond the Q63 number range (-2^63 <= Q63 <= 2^63-1), it is saturated to the range and the OV bit is set to + * 1. The 64-bit result after saturation is written to Rd. The 32-bit contents of Rs1 and Rs2 are treated + * as signed integers. + * + * **Operations**:\n + * ~~~ + * res = Rd + (Rs1.W[1] * Rs2.W[1]) - (Rs1.W[0] * Rs2.W[0]); // KMADS32 + * res = Rd + (Rs1.W[0] * Rs2.W[0]) - (Rs1.W[1] * Rs2.W[1]); // KMADRS32 + * res = Rd + (Rs1.W[1] * Rs2.W[0]) - (Rs1.W[0] * Rs2.W[1]); // KMAXDS32 + * if (res > (2^63)-1) { + * res = (2^63)-1; + * OV = 1; + * } else if (res < -2^63) { + * res = -2^63; + * OV = 1; + * } + * Rd = res; + * ~~~ + * + * \param [in] t long type of value stored in t + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_KMADRS32(long t, unsigned long a, unsigned long b) +{ + __ASM volatile("kmadrs32 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); + return t; +} +/* ===== Inline Function End for 4.14.2. KMADRS32 ===== */ + +/* ===== Inline Function Start for 4.14.3. KMAXDS32 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_PARALLEL_MAC + * \brief KMAXDS32 (Saturating Signed Crossed Multiply Two Words & Subtract & Add) + * \details + * **Type**: DSP (RV64 Only) + * + * **Syntax**:\n + * ~~~ + * KMADS32 Rd, Rs1, Rs2 + * KMADRS32 Rd, Rs1, Rs2 + * KMAXDS32 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do two signed 32-bit multiplications from 32-bit elements in two registers; and then + * perform a subtraction operation between the two 64-bit results. Then add the subtraction result to + * 64-bit data in a third register. The addition result may be saturated. + * * KMADS32: rd + (top*top - bottom*bottom) + * * KMADRS32: rd + (bottom*bottom - top*top) + * * KMAXDS32: rd + (top*bottom - bottom*top) + * + * **Description**:\n + * For the `KMADS32` instruction, it multiplies the bottom 32-bit element in Rs1 with the bottom 32-bit + * element in Rs2 and then subtracts the result from the result of multiplying the top 32-bit element in + * Rs1 with the top 32-bit element in Rs2. + * For the `KMADRS32` instruction, it multiplies the top 32-bit element in Rs1 with the top 32-bit + * element in Rs2 and then subtracts the result from the result of multiplying the bottom 32-bit + * element in Rs1 with the bottom 32-bit element in Rs2. + * For the `KMAXDS32` instruction, it multiplies the bottom 32-bit element in Rs1 with the top 32-bit + * element in Rs2 and then subtracts the result from the result of multiplying the top 32-bit element in + * Rs1 with the bottom 32-bit element in Rs2. + * The subtraction result is then added to the content of 64-bit data in Rd. If the addition result is + * beyond the Q63 number range (-2^63 <= Q63 <= 2^63-1), it is saturated to the range and the OV bit is set to + * 1. The 64-bit result after saturation is written to Rd. The 32-bit contents of Rs1 and Rs2 are treated + * as signed integers. + * + * **Operations**:\n + * ~~~ + * res = Rd + (Rs1.W[1] * Rs2.W[1]) - (Rs1.W[0] * Rs2.W[0]); // KMADS32 + * res = Rd + (Rs1.W[0] * Rs2.W[0]) - (Rs1.W[1] * Rs2.W[1]); // KMADRS32 + * res = Rd + (Rs1.W[1] * Rs2.W[0]) - (Rs1.W[0] * Rs2.W[1]); // KMAXDS32 + * if (res > (2^63)-1) { + * res = (2^63)-1; + * OV = 1; + * } else if (res < -2^63) { + * res = -2^63; + * OV = 1; + * } + * Rd = res; + * ~~~ + * + * \param [in] t long type of value stored in t + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_KMAXDS32(long t, unsigned long a, unsigned long b) +{ + __ASM volatile("kmaxds32 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); + return t; +} +/* ===== Inline Function End for 4.14.3. KMAXDS32 ===== */ + +/* ===== Inline Function Start for 4.15.1. KMSDA32 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_PARALLEL_MAC + * \brief KMSDA32 (Saturating Signed Multiply Two Words & Add & Subtract) + * \details + * **Type**: DSP (RV64 Only) + * + * **Syntax**:\n + * ~~~ + * KMSDA32 Rd, Rs1, Rs2 + * KMSXDA32 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do two signed 32-bit multiplications from the 32-bit element of two registers; and then + * subtracts the two 64-bit results from a third register. The subtraction result may be saturated. + * * KMSDA: rd - top*top - bottom*bottom + * * KMSXDA: rd - top*bottom - bottom*top + * + * **Description**:\n + * For the `KMSDA32` instruction, it multiplies the bottom 32-bit element of Rs1 with the bottom 32-bit + * element of Rs2 and multiplies the top 32-bit element of Rs1 with the top 32-bit element of Rs2. + * For the `KMSXDA32` instruction, it multiplies the bottom 32-bit element of Rs1 with the top 32-bit + * element of Rs2 and multiplies the top 32-bit element of Rs1 with the bottom 32-bit element of Rs2. + * The two 64-bit multiplication results are then subtracted from the content of Rd. If the subtraction + * result is beyond the Q63 number range (-2^63 <= Q63 <= 2^63-1), it is saturated to the range and the OV bit + * is set to 1. The result after saturation is written to Rd. The 32-bit contents are treated as signed + * integers. + * + * **Operations**:\n + * ~~~ + * res = Rd - (Rs1.W[1] * Rs2.W[1]) - (Rs1.W[0] * Rs2.W[0]); // KMSDA32 + * res = Rd - (Rs1.W[1] * Rs2.W[0]) - (Rs1.W[0] * Rs2.W[1]); // KMSXDA32 + * if (res > (2^63)-1) { + * res = (2^63)-1; + * OV = 1; + * } else if (res < -2^63) { + * res = -2^63; + * OV = 1; + * } + * Rd = res; + * ~~~ + * + * \param [in] t long type of value stored in t + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_KMSDA32(long t, unsigned long a, unsigned long b) +{ + __ASM volatile("kmsda32 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); + return t; +} +/* ===== Inline Function End for 4.15.1. KMSDA32 ===== */ + +/* ===== Inline Function Start for 4.15.2. KMSXDA32 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_PARALLEL_MAC + * \brief KMSXDA32 (Saturating Signed Crossed Multiply Two Words & Add & Subtract) + * \details + * **Type**: DSP (RV64 Only) + * + * **Syntax**:\n + * ~~~ + * KMSDA32 Rd, Rs1, Rs2 + * KMSXDA32 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do two signed 32-bit multiplications from the 32-bit element of two registers; and then + * subtracts the two 64-bit results from a third register. The subtraction result may be saturated. + * * KMSDA: rd - top*top - bottom*bottom + * * KMSXDA: rd - top*bottom - bottom*top + * + * **Description**:\n + * For the `KMSDA32` instruction, it multiplies the bottom 32-bit element of Rs1 with the bottom 32-bit + * element of Rs2 and multiplies the top 32-bit element of Rs1 with the top 32-bit element of Rs2. + * For the `KMSXDA32` instruction, it multiplies the bottom 32-bit element of Rs1 with the top 32-bit + * element of Rs2 and multiplies the top 32-bit element of Rs1 with the bottom 32-bit element of Rs2. + * The two 64-bit multiplication results are then subtracted from the content of Rd. If the subtraction + * result is beyond the Q63 number range (-2^63 <= Q63 <= 2^63-1), it is saturated to the range and the OV bit + * is set to 1. The result after saturation is written to Rd. The 32-bit contents are treated as signed + * integers. + * + * **Operations**:\n + * ~~~ + * res = Rd - (Rs1.W[1] * Rs2.W[1]) - (Rs1.W[0] * Rs2.W[0]); // KMSDA32 + * res = Rd - (Rs1.W[1] * Rs2.W[0]) - (Rs1.W[0] * Rs2.W[1]); // KMSXDA32 + * if (res > (2^63)-1) { + * res = (2^63)-1; + * OV = 1; + * } else if (res < -2^63) { + * res = -2^63; + * OV = 1; + * } + * Rd = res; + * ~~~ + * + * \param [in] t long type of value stored in t + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_KMSXDA32(long t, unsigned long a, unsigned long b) +{ + __ASM volatile("kmsxda32 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); + return t; +} +/* ===== Inline Function End for 4.15.2. KMSXDA32 ===== */ + +/* ===== Inline Function Start for 4.16. KSLL32 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_SHIFT + * \brief KSLL32 (SIMD 32-bit Saturating Shift Left Logical) + * \details + * **Type**: SIMD (RV64 Only) + * + * **Syntax**:\n + * ~~~ + * KSLL32 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 32-bit elements logical left shift operations with saturation simultaneously. The shift + * amount is a variable from a GPR. + * + * **Description**:\n + * The 32-bit data elements in Rs1 are left-shifted logically. The shifted out bits are filled + * with zero and the shift amount is specified by the low-order 5-bits of the value in the Rs2 register. + * Any shifted value greater than 2^31-1 is saturated to 2^31-1. Any shifted value smaller than -2^31 is + * saturated to -2^31. And the saturated results are written to Rd. If any saturation is performed, set OV + * bit to 1. + * + * **Operations**:\n + * ~~~ + * sa = Rs2[4:0]; + * if (sa != 0) { + * res[(31+sa):0] = Rs1.W[x] << sa; + * if (res > (2^31)-1) { + * res = 0x7fffffff; OV = 1; + * } else if (res < -2^31) { + * res = 0x80000000; OV = 1; + * } + * Rd.W[x] = res[31:0]; + * } else { + * Rd = Rs1; + * } + * for RV64: x=1...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned int type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_KSLL32(unsigned long a, unsigned int b) +{ + register unsigned long result; + __ASM volatile("ksll32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 4.16. KSLL32 ===== */ + +/* ===== Inline Function Start for 4.17. KSLLI32 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_SHIFT + * \brief KSLLI32 (SIMD 32-bit Saturating Shift Left Logical Immediate) + * \details + * **Type**: SIMD (RV64 Only) + * + * **Syntax**:\n + * ~~~ + * KSLLI32 Rd, Rs1, imm5u + * ~~~ + * + * **Purpose**:\n + * Do 32-bit elements logical left shift operations with saturation simultaneously. The shift + * amount is an immediate value. + * + * **Description**:\n + * The 32-bit data elements in Rs1 are left-shifted logically. The shifted out bits are filled + * with zero and the shift amount is specified by the imm5u constant. Any shifted value greater than + * 2^31-1 is saturated to 2^31-1. Any shifted value smaller than -2^31 is saturated to -2^31. And the saturated + * results are written to Rd. If any saturation is performed, set OV bit to 1. + * + * **Operations**:\n + * ~~~ + * sa = imm5u[4:0]; + * if (sa != 0) { + * res[(31+sa):0] = Rs1.W[x] << sa; + * if (res > (2^31)-1) { + * res = 0x7fffffff; OV = 1; + * } else if (res < -2^31) { + * res = 0x80000000; OV = 1; + * } + * Rd.W[x] = res[31:0]; + * } else { + * Rd = Rs1; + * } + * for RV64: x=1...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned int type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_KSLLI32(unsigned long a, unsigned int b) +{ + register unsigned long result; + __ASM volatile("kslli32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 4.17. KSLLI32 ===== */ + +/* ===== Inline Function Start for 4.18.1. KSLRA32 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_SHIFT + * \brief KSLRA32 (SIMD 32-bit Shift Left Logical with Saturation or Shift Right Arithmetic) + * \details + * **Type**: SIMD (RV64 Only) + * + * **Syntax**:\n + * ~~~ + * KSLRA32 Rd, Rs1, Rs2 + * KSLRA32.u Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 32-bit elements logical left (positive) or arithmetic right (negative) shift operation with + * Q31 saturation for the left shift. The `.u` form performs additional rounding up operations for the + * right shift. + * + * **Description**:\n + * The 32-bit data elements of Rs1 are left-shifted logically or right-shifted arithmetically + * based on the value of Rs2[5:0]. Rs2[5:0] is in the signed range of [-25, 25-1]. A positive Rs2[5:0] means + * logical left shift and a negative Rs2[5:0] means arithmetic right shift. The shift amount is the + * absolute value of Rs2[5:0]. However, the behavior of `Rs2[5:0]==-25 (0x20)` is defined to be + * equivalent to the behavior of `Rs2[5:0]==-(25-1) (0x21)`. + * The left-shifted results are saturated to the 32-bit signed integer range of [-2^31, 2^31-1]. For the `.u` + * form of the instruction, the right-shifted results are added a 1 to the most significant discarded bit + * position for rounding effect. After the shift, saturation, or rounding, the final results are written to + * Rd. If any saturation happens, this instruction sets the OV flag. The value of Rs2[31:6] will not affect + * this instruction. + * + * **Operations**:\n + * ~~~ + * if (Rs2[5:0] < 0) { + * sa = -Rs2[5:0]; + * sa = (sa == 32)? 31 : sa; + * if (`.u` form) { + * res[31:-1] = SE33(Rs1.W[x][31:sa-1]) + 1; + * Rd.W[x] = res[31:0]; + * } else { + * Rd.W[x] = SE32(Rs1.W[x][31:sa]); + * } + * } else { + * sa = Rs2[4:0]; + * res[(31+sa):0] = Rs1.W[x] <<(logic) sa; + * if (res > (2^31)-1) { + * res[31:0] = 0x7fffffff; OV = 1; + * } else if (res < -2^31) { + * res[31:0] = 0x80000000; OV = 1; + * } + * Rd.W[x] = res[31:0]; + * } + * for RV64: x=1...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b int type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_KSLRA32(unsigned long a, int b) +{ + register unsigned long result; + __ASM volatile("kslra32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 4.18.1. KSLRA32 ===== */ + +/* ===== Inline Function Start for 4.18.2. KSLRA32.u ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_SHIFT + * \brief KSLRA32.u (SIMD 32-bit Shift Left Logical with Saturation or Rounding Shift Right Arithmetic) + * \details + * **Type**: SIMD (RV64 Only) + * + * **Syntax**:\n + * ~~~ + * KSLRA32 Rd, Rs1, Rs2 + * KSLRA32.u Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 32-bit elements logical left (positive) or arithmetic right (negative) shift operation with + * Q31 saturation for the left shift. The `.u` form performs additional rounding up operations for the + * right shift. + * + * **Description**:\n + * The 32-bit data elements of Rs1 are left-shifted logically or right-shifted arithmetically + * based on the value of Rs2[5:0]. Rs2[5:0] is in the signed range of [-25, 25-1]. A positive Rs2[5:0] means + * logical left shift and a negative Rs2[5:0] means arithmetic right shift. The shift amount is the + * absolute value of Rs2[5:0]. However, the behavior of `Rs2[5:0]==-25 (0x20)` is defined to be + * equivalent to the behavior of `Rs2[5:0]==-(25-1) (0x21)`. + * The left-shifted results are saturated to the 32-bit signed integer range of [-2^31, 2^31-1]. For the `.u` + * form of the instruction, the right-shifted results are added a 1 to the most significant discarded bit + * position for rounding effect. After the shift, saturation, or rounding, the final results are written to + * Rd. If any saturation happens, this instruction sets the OV flag. The value of Rs2[31:6] will not affect + * this instruction. + * + * **Operations**:\n + * ~~~ + * if (Rs2[5:0] < 0) { + * sa = -Rs2[5:0]; + * sa = (sa == 32)? 31 : sa; + * if (`.u` form) { + * res[31:-1] = SE33(Rs1.W[x][31:sa-1]) + 1; + * Rd.W[x] = res[31:0]; + * } else { + * Rd.W[x] = SE32(Rs1.W[x][31:sa]); + * } + * } else { + * sa = Rs2[4:0]; + * res[(31+sa):0] = Rs1.W[x] <<(logic) sa; + * if (res > (2^31)-1) { + * res[31:0] = 0x7fffffff; OV = 1; + * } else if (res < -2^31) { + * res[31:0] = 0x80000000; OV = 1; + * } + * Rd.W[x] = res[31:0]; + * } + * for RV64: x=1...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b int type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_KSLRA32_U(unsigned long a, int b) +{ + register unsigned long result; + __ASM volatile("kslra32.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 4.18.2. KSLRA32.u ===== */ + +/* ===== Inline Function Start for 4.19. KSTAS32 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB + * \brief KSTAS32 (SIMD 32-bit Signed Saturating Straight Addition & Subtraction) + * \details + * **Type**: SIMD (RV64 Only) + * + * **Syntax**:\n + * ~~~ + * KSTAS32 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 32-bit signed integer element saturating addition and 32-bit signed integer element + * saturating subtraction in a 64-bit chunk simultaneously. Operands are from corresponding 32-bit + * elements. + * + * **Description**:\n + * This instruction adds the 32-bit integer element in [63:32] of Rs1 with the 32-bit + * integer element in [63:32] of Rs2; at the same time, it subtracts the 32-bit integer element in [31:0] of + * Rs2 from the 32-bit integer element in [31:0] of Rs1. If any of the results are beyond the Q31 number + * range (-2^31 <= Q31 <= 2^31-1), they are saturated to the range and the OV bit is set to 1. The saturated + * results are written to [63:32] of Rd for addition and [31:0] of Rd for subtraction. + * + * **Operations**:\n + * ~~~ + * res[1] = Rs1.W[1] + Rs2.W[1]; + * res[0] = Rs1.W[0] - Rs2.W[0]; + * if (res[x] > (2^31)-1) { + * res[x] = (2^31)-1; + * OV = 1; + * } else if (res < -2^31) { + * res[x] = -2^31; + * OV = 1; + * } + * Rd.W[1] = res[1]; + * Rd.W[0] = res[0]; + * for RV64, x=1...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_KSTAS32(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("kstas32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 4.19. KSTAS32 ===== */ + +/* ===== Inline Function Start for 4.20. KSTSA32 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB + * \brief KSTSA32 (SIMD 32-bit Signed Saturating Straight Subtraction & Addition) + * \details + * **Type**: SIM (RV64 Only) + * + * **Syntax**:\n + * ~~~ + * KSTSA32 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 32-bit signed integer element saturating subtraction and 32-bit signed integer element + * saturating addition in a 64-bit chunk simultaneously. Operands are from corresponding 32-bit + * elements. + * *Description: * + * This instruction subtracts the 32-bit integer element in [63:32] of Rs2 from the 32-bit integer + * element in [63:32] of Rs1; at the same time, it adds the 32-bit integer element in [31:0] of Rs1 with + * the 32-bit integer element in [31:0] of Rs2. If any of the results are beyond the Q31 number range (- + * 231 <= Q31 <= 2^31-1), they are saturated to the range and the OV bit is set to 1. The saturated results are + * written to [63:32] of Rd for subtraction and [31:0] of Rd for addition. + * + * **Operations**:\n + * ~~~ + * res[1] = Rs1.W[1] - Rs2.W[1]; + * res[0] = Rs1.W[0] + Rs2.W[0]; + * if (res[x] > (2^31)-1) { + * res[x] = (2^31)-1; + * OV = 1; + * } else if (res < -2^31) { + * res[x] = -2^31; + * OV = 1; + * } + * Rd.W[1] = res[1]; + * Rd.W[0] = res[0]; + * for RV64, x=1...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_KSTSA32(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("kstsa32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 4.20. KSTSA32 ===== */ + +/* ===== Inline Function Start for 4.21. KSUB32 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB + * \brief KSUB32 (SIMD 32-bit Signed Saturating Subtraction) + * \details + * **Type**: SIMD (RV64 Only) + * + * **Syntax**:\n + * ~~~ + * KSUB32 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 32-bit signed integer elements saturating subtractions simultaneously. + * + * **Description**:\n + * This instruction subtracts the 32-bit signed integer elements in Rs2 from the 32-bit + * signed integer elements in Rs1. If any of the results are beyond the Q31 number range (-2^31 <= Q31 <= + * 2^31-1), they are saturated to the range and the OV bit is set to 1. The saturated results are written to + * Rd. + * + * **Operations**:\n + * ~~~ + * res[x] = Rs1.W[x] - Rs2.W[x]; + * if (res[x] > (2^31)-1) { + * res[x] = (2^31)-1; + * OV = 1; + * } else if (res[x] < -2^31) { + * res[x] = -2^31; + * OV = 1; + * } + * Rd.W[x] = res[x]; + * for RV64: x=1...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_KSUB32(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("ksub32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 4.21. KSUB32 ===== */ + +/* ===== Inline Function Start for 4.22.1. PKBB32 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_PACK + * \brief PKBB32 (Pack Two 32-bit Data from Both Bottom Half) + * \details + * **Type**: DSP (RV64 Only) + * + * **Syntax**:\n + * ~~~ + * PKBB32 Rd, Rs1, Rs2 + * PKBT32 Rd, Rs1, Rs2 + * PKTT32 Rd, Rs1, Rs2 + * PKTB32 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Pack 32-bit data from 64-bit chunks in two registers. + * * PKBB32: bottom.bottom + * * PKBT32: bottom.top + * * PKTT32: top.top + * * PKTB32: top.bottom + * + * **Description**:\n + * (PKBB32) moves Rs1.W[0] to Rd.W[1] and moves Rs2.W[0] to Rd.W[0]. + * (PKBT32) moves Rs1.W[0] to Rd.W[1] and moves Rs2.W[1] to Rd.W[0]. + * (PKTT32) moves Rs1.W[1] to Rd.W[1] and moves Rs2.W[1] to Rd.W[0]. + * (PKTB32) moves Rs1.W[1] to Rd.W[1] and moves Rs2.W[0] to Rd.W[0]. + * + * **Operations**:\n + * ~~~ + * Rd = CONCAT(Rs1.W[_*0*_], Rs2.W[_*0*_]); // PKBB32 + * Rd = CONCAT(Rs1.W[_*0*_], Rs2.W[_*1*_]); // PKBT32 + * Rd = CONCAT(Rs1.W[_*1*_], Rs2.W[_*1*_]); // PKTT32 + * Rd = CONCAT(Rs1.W[_*1*_], Rs2.W[_*0*_]); // PKTB32 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_PKBB32(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("pkbb32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 4.22.1. PKBB32 ===== */ + +/* ===== Inline Function Start for 4.22.2. PKBT32 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_PACK + * \brief PKBT32 (Pack Two 32-bit Data from Bottom and Top Half) + * \details + * **Type**: DSP (RV64 Only) + * + * **Syntax**:\n + * ~~~ + * PKBB32 Rd, Rs1, Rs2 + * PKBT32 Rd, Rs1, Rs2 + * PKTT32 Rd, Rs1, Rs2 + * PKTB32 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Pack 32-bit data from 64-bit chunks in two registers. + * * PKBB32: bottom.bottom + * * PKBT32: bottom.top + * * PKTT32: top.top + * * PKTB32: top.bottom + * + * **Description**:\n + * (PKBB32) moves Rs1.W[0] to Rd.W[1] and moves Rs2.W[0] to Rd.W[0]. + * (PKBT32) moves Rs1.W[0] to Rd.W[1] and moves Rs2.W[1] to Rd.W[0]. + * (PKTT32) moves Rs1.W[1] to Rd.W[1] and moves Rs2.W[1] to Rd.W[0]. + * (PKTB32) moves Rs1.W[1] to Rd.W[1] and moves Rs2.W[0] to Rd.W[0]. + * + * **Operations**:\n + * ~~~ + * Rd = CONCAT(Rs1.W[_*0*_], Rs2.W[_*0*_]); // PKBB32 + * Rd = CONCAT(Rs1.W[_*0*_], Rs2.W[_*1*_]); // PKBT32 + * Rd = CONCAT(Rs1.W[_*1*_], Rs2.W[_*1*_]); // PKTT32 + * Rd = CONCAT(Rs1.W[_*1*_], Rs2.W[_*0*_]); // PKTB32 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_PKBT32(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("pkbt32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 4.22.2. PKBT32 ===== */ + +/* ===== Inline Function Start for 4.22.3. PKTT32 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_PACK + * \brief PKTT32 (Pack Two 32-bit Data from Both Top Half) + * \details + * **Type**: DSP (RV64 Only) + * + * **Syntax**:\n + * ~~~ + * PKBB32 Rd, Rs1, Rs2 + * PKBT32 Rd, Rs1, Rs2 + * PKTT32 Rd, Rs1, Rs2 + * PKTB32 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Pack 32-bit data from 64-bit chunks in two registers. + * * PKBB32: bottom.bottom + * * PKBT32: bottom.top + * * PKTT32: top.top + * * PKTB32: top.bottom + * + * **Description**:\n + * (PKBB32) moves Rs1.W[0] to Rd.W[1] and moves Rs2.W[0] to Rd.W[0]. + * (PKBT32) moves Rs1.W[0] to Rd.W[1] and moves Rs2.W[1] to Rd.W[0]. + * (PKTT32) moves Rs1.W[1] to Rd.W[1] and moves Rs2.W[1] to Rd.W[0]. + * (PKTB32) moves Rs1.W[1] to Rd.W[1] and moves Rs2.W[0] to Rd.W[0]. + * + * **Operations**:\n + * ~~~ + * Rd = CONCAT(Rs1.W[_*0*_], Rs2.W[_*0*_]); // PKBB32 + * Rd = CONCAT(Rs1.W[_*0*_], Rs2.W[_*1*_]); // PKBT32 + * Rd = CONCAT(Rs1.W[_*1*_], Rs2.W[_*1*_]); // PKTT32 + * Rd = CONCAT(Rs1.W[_*1*_], Rs2.W[_*0*_]); // PKTB32 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_PKTT32(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("pktt32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 4.22.3. PKTT32 ===== */ + +/* ===== Inline Function Start for 4.22.4. PKTB32 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_PACK + * \brief PKTB32 (Pack Two 32-bit Data from Top and Bottom Half) + * \details + * **Type**: DSP (RV64 Only) + * + * **Syntax**:\n + * ~~~ + * PKBB32 Rd, Rs1, Rs2 + * PKBT32 Rd, Rs1, Rs2 + * PKTT32 Rd, Rs1, Rs2 + * PKTB32 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Pack 32-bit data from 64-bit chunks in two registers. + * * PKBB32: bottom.bottom + * * PKBT32: bottom.top + * * PKTT32: top.top + * * PKTB32: top.bottom + * + * **Description**:\n + * (PKBB32) moves Rs1.W[0] to Rd.W[1] and moves Rs2.W[0] to Rd.W[0]. + * (PKBT32) moves Rs1.W[0] to Rd.W[1] and moves Rs2.W[1] to Rd.W[0]. + * (PKTT32) moves Rs1.W[1] to Rd.W[1] and moves Rs2.W[1] to Rd.W[0]. + * (PKTB32) moves Rs1.W[1] to Rd.W[1] and moves Rs2.W[0] to Rd.W[0]. + * + * **Operations**:\n + * ~~~ + * Rd = CONCAT(Rs1.W[_*0*_], Rs2.W[_*0*_]); // PKBB32 + * Rd = CONCAT(Rs1.W[_*0*_], Rs2.W[_*1*_]); // PKBT32 + * Rd = CONCAT(Rs1.W[_*1*_], Rs2.W[_*1*_]); // PKTT32 + * Rd = CONCAT(Rs1.W[_*1*_], Rs2.W[_*0*_]); // PKTB32 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_PKTB32(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("pktb32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 4.22.4. PKTB32 ===== */ + +/* ===== Inline Function Start for 4.23. RADD32 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB + * \brief RADD32 (SIMD 32-bit Signed Halving Addition) + * \details + * **Type**: SIMD (RV64 Only) + * + * **Syntax**:\n + * ~~~ + * RADD32 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 32-bit signed integer element additions simultaneously. The results are halved to avoid + * overflow or saturation. + * + * **Description**:\n + * This instruction adds the 32-bit signed integer elements in Rs1 with the 32-bit signed + * integer elements in Rs2. The results are first arithmetically right-shifted by 1 bit and then written to + * Rd. + * + * **Examples**:\n + * ~~~ + * * Rs1 = 0x7FFFFFFF, Rs2 = 0x7FFFFFFF Rd = 0x7FFFFFFF + * * Rs1 = 0x80000000, Rs2 = 0x80000000 Rd = 0x80000000 + * * Rs1 = 0x40000000, Rs2 = 0x80000000 Rd = 0xE0000000 + * ~~~ + * + * **Operations**:\n + * ~~~ + * Rd.W[x] = (Rs1.W[x] + Rs2.W[x]) s>> 1; + * for RV64: x=1...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_RADD32(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("radd32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 4.23. RADD32 ===== */ + +/* ===== Inline Function Start for 4.24. RCRAS32 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB + * \brief RCRAS32 (SIMD 32-bit Signed Halving Cross Addition & Subtraction) + * \details + * **Type**: SIMD (RV64 Only) + * + * **Syntax**:\n + * ~~~ + * RCRAS32 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 32-bit signed integer element addition and 32-bit signed integer element subtraction in + * a 64-bit chunk simultaneously. Operands are from crossed 32-bit elements. The results are halved to + * avoid overflow or saturation. + * + * **Description**:\n + * This instruction adds the 32-bit signed integer element in [63:32] of Rs1 with the 32-bit + * signed integer element in [31:0] of Rs2, and subtracts the 32-bit signed integer element in [63:32] of + * Rs2 from the 32-bit signed integer element in [31:0] of Rs1. The element results are first + * arithmetically right-shifted by 1 bit and then written to [63:32] of Rd for addition and [31:0] of Rd + * for subtraction. + * + * **Examples**:\n + * ~~~ + * Please see `RADD32` and `RSUB32` instructions. + * ~~~ + * + * **Operations**:\n + * ~~~ + * Rd.W[1] = (Rs1.W[1] + Rs2.W[0]) s>> 1; + * Rd.W[0] = (Rs1.W[0] - Rs2.W[1]) s>> 1; + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_RCRAS32(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("rcras32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 4.24. RCRAS32 ===== */ + +/* ===== Inline Function Start for 4.25. RCRSA32 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB + * \brief RCRSA32 (SIMD 32-bit Signed Halving Cross Subtraction & Addition) + * \details + * **Type**: SIMD (RV64 Only) + * + * **Syntax**:\n + * ~~~ + * RCRSA32 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 32-bit signed integer element subtraction and 32-bit signed integer element addition in + * a 64-bit chunk simultaneously. Operands are from crossed 32-bit elements. The results are halved to + * avoid overflow or saturation. + * + * **Description**:\n + * This instruction subtracts the 32-bit signed integer element in [31:0] of Rs2 from the + * 32-bit signed integer element in [63:32] of Rs1, and adds the 32-bit signed element integer in [31:0] + * of Rs1 with the 32-bit signed integer element in [63:32] of Rs2. The two results are first + * arithmetically right-shifted by 1 bit and then written to [63:32] of Rd for subtraction and [31:0] of + * Rd for addition. + * + * **Examples**:\n + * ~~~ + * Please see `RADD32` and `RSUB32` instructions. + * ~~~ + * + * **Operations**:\n + * ~~~ + * Rd.W[1] = (Rs1.W[1] - Rs2.W[0]) s>> 1; + * Rd.W[0] = (Rs1.W[0] + Rs2.W[1]) s>> 1; + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_RCRSA32(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("rcrsa32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 4.25. RCRSA32 ===== */ + +/* ===== Inline Function Start for 4.26. RSTAS32 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB + * \brief RSTAS32 (SIMD 32-bit Signed Halving Straight Addition & Subtraction) + * \details + * **Type**: SIMD (RV64 Only) + * + * **Syntax**:\n + * ~~~ + * RSTAS32 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 32-bit signed integer element addition and 32-bit signed integer element subtraction in + * a 64-bit chunk simultaneously. Operands are from corresponding 32-bit elements. The results are + * halved to avoid overflow or saturation. + * + * **Description**:\n + * This instruction adds the 32-bit signed integer element in [63:32] of Rs1 with the 32-bit + * signed integer element in [63:32] of Rs2, and subtracts the 32-bit signed integer element in [31:0] of + * Rs2 from the 32-bit signed integer element in [31:0] of Rs1. The element results are first + * arithmetically right-shifted by 1 bit and then written to [63:32] of Rd for addition and [31:0] of Rd + * for subtraction. + * + * **Examples**:\n + * ~~~ + * Please see `RADD32` and `RSUB32` instructions. + * ~~~ + * + * **Operations**:\n + * ~~~ + * Rd.W[1] = (Rs1.W[1] + Rs2.W[1]) s>> 1; + * Rd.W[0] = (Rs1.W[0] - Rs2.W[0]) s>> 1; + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_RSTAS32(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("rstas32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 4.26. RSTAS32 ===== */ + +/* ===== Inline Function Start for 4.27. RSTSA32 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB + * \brief RSTSA32 (SIMD 32-bit Signed Halving Straight Subtraction & Addition) + * \details + * **Type**: SIMD (RV64 Only) + * + * **Syntax**:\n + * ~~~ + * RSTSA32 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 32-bit signed integer element subtraction and 32-bit signed integer element addition in + * a 64-bit chunk simultaneously. Operands are from corresponding 32-bit elements. The results are + * halved to avoid overflow or saturation. + * + * **Description**:\n + * This instruction subtracts the 32-bit signed integer element in [63:32] of Rs2 from the + * 32-bit signed integer element in [63:32] of Rs1, and adds the 32-bit signed element integer in [31:0] + * of Rs1 with the 32-bit signed integer element in [31:0] of Rs2. The two results are first arithmetically + * right-shifted by 1 bit and then written to [63:32] of Rd for subtraction and [31:0] of Rd for addition. + * + * **Examples**:\n + * ~~~ + * Please see `RADD32` and `RSUB32` instructions. + * ~~~ + * + * **Operations**:\n + * ~~~ + * Rd.W[1] = (Rs1.W[1] - Rs2.W[1]) s>> 1; + * Rd.W[0] = (Rs1.W[0] + Rs2.W[0]) s>> 1; + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_RSTSA32(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("rstsa32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 4.27. RSTSA32 ===== */ + +/* ===== Inline Function Start for 4.28. RSUB32 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB + * \brief RSUB32 (SIMD 32-bit Signed Halving Subtraction) + * \details + * **Type**: SIMD (RV64 Only) + * + * **Syntax**:\n + * ~~~ + * RSUB32 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 32-bit signed integer element subtractions simultaneously. The results are halved to + * avoid overflow or saturation. + * + * **Description**:\n + * This instruction subtracts the 32-bit signed integer elements in Rs2 from the 32-bit + * signed integer elements in Rs1. The results are first arithmetically right-shifted by 1 bit and then + * written to Rd. + * + * **Examples**:\n + * ~~~ + * * Ra = 0x7FFFFFFF, Rb = 0x80000000 Rt = 0x7FFFFFFF + * * Ra = 0x80000000, Rb = 0x7FFFFFFF Rt = 0x80000000 + * * Ra = 0x80000000, Rb = 0x40000000 Rt = 0xA0000000 + * ~~~ + * + * **Operations**:\n + * ~~~ + * Rd.W[x] = (Rs1.W[x] - Rs2.W[x]) s>> 1; + * for RV64: x=1...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_RSUB32(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("rsub32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 4.28. RSUB32 ===== */ + +/* ===== Inline Function Start for 4.29. SLL32 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_SHIFT + * \brief SLL32 (SIMD 32-bit Shift Left Logical) + * \details + * **Type**: SIMD (RV64 Only) + * + * **Syntax**:\n + * ~~~ + * SLL32 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 32-bit elements logical left shift operations simultaneously. The shift amount is a + * variable from a GPR. + * + * **Description**:\n + * The 32-bit elements in Rs1 are left-shifted logically. And the results are written to Rd. + * The shifted out bits are filled with zero and the shift amount is specified by the low-order 5-bits of + * the value in the Rs2 register. + * + * **Operations**:\n + * ~~~ + * sa = Rs2[4:0]; + * Rd.W[x] = Rs1.W[x] << sa; + * for RV64: x=1...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned int type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_SLL32(unsigned long a, unsigned int b) +{ + register unsigned long result; + __ASM volatile("sll32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 4.29. SLL32 ===== */ + +/* ===== Inline Function Start for 4.30. SLLI32 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_SHIFT + * \brief SLLI32 (SIMD 32-bit Shift Left Logical Immediate) + * \details + * **Type**: SIMD (RV64 Only) + * + * **Syntax**:\n + * ~~~ + * SLLI32 Rd, Rs1, imm5u[4:0] + * ~~~ + * + * **Purpose**:\n + * Do 32-bit element logical left shift operations simultaneously. The shift amount is an + * immediate value. + * + * **Description**:\n + * The 32-bit elements in Rs1 are left-shifted logically. The shifted out bits are filled with + * zero and the shift amount is specified by the imm5u[4:0] constant. And the results are written to Rd. + * + * **Operations**:\n + * ~~~ + * sa = imm5u[4:0]; + * Rd.W[x] = Rs1.W[x] << sa; + * for RV64: x=1...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned int type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_SLLI32(unsigned long a, unsigned int b) +{ + register unsigned long result; + __ASM volatile("slli32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 4.30. SLLI32 ===== */ + +/* ===== Inline Function Start for 4.31. SMAX32 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_MISC + * \brief SMAX32 (SIMD 32-bit Signed Maximum) + * \details + * **Type**: SIMD (RV64 Only) + * + * **Syntax**:\n + * ~~~ + * SMAX32 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 32-bit signed integer elements finding maximum operations simultaneously. + * + * **Description**:\n + * This instruction compares the 32-bit signed integer elements in Rs1 with the 32-bit + * signed integer elements in Rs2 and selects the numbers that is greater than the other one. The + * selected results are written to Rd. + * + * **Operations**:\n + * ~~~ + * Rd.W[x] = (Rs1.W[x] > Rs2.W[x])? Rs1.W[x] : Rs2.W[x]; + * for RV64: x=1...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_SMAX32(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("smax32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 4.31. SMAX32 ===== */ + +/* ===== Inline Function Start for 4.32.1. SMBB32 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_MULT + * \brief SMBB32 (Signed Multiply Bottom Word & Bottom Word) + * \details + * **Type**: DSP (RV64 Only) + * + * **Syntax**:\n + * ~~~ + * SMBB32 Rd, Rs1, Rs2 + * SMBT32 Rd, Rs1, Rs2 + * SMTT32 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Multiply the signed 32-bit element of a register with the signed 32-bit element of another + * register and write the 64-bit result to a third register. + * * SMBB32: bottom*bottom + * * SMBT32: bottom*top + * * SMTT32: top*top + * + * **Description**:\n + * For the `SMBB32` instruction, it multiplies the bottom 32-bit element of Rs1 with the bottom 32-bit + * element of Rs2. It is actually an alias of `MULSR64` instruction. + * For the `SMBT32` instruction, it multiplies the bottom 32-bit element of Rs1 with the top 32-bit + * element of Rs2. + * For the `SMTT32` instruction, it multiplies the top 32-bit element of Rs1 with the top 32-bit element + * of Rs2. + * The 64-bit multiplication result is written to Rd. The 32-bit contents of Rs1 and Rs2 are treated as + * signed integers. + * + * **Operations**:\n + * ~~~ + * res = Rs1.W[0] * Rs2.W[0]; // SMBB32 res = Rs1.W[0] * Rs2.w[1]; // SMBT32 res = Rs1.W[1] * Rs2.W[1]; + * // SMTT32 Rd = res; + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_SMBB32(unsigned long a, unsigned long b) +{ + register long result; + __ASM volatile("smbb32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 4.32.1. SMBB32 ===== */ + +/* ===== Inline Function Start for 4.32.2. SMBT32 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_MULT + * \brief SMBT32 (Signed Multiply Bottom Word & Top Word) + * \details + * **Type**: DSP (RV64 Only) + * + * **Syntax**:\n + * ~~~ + * SMBB32 Rd, Rs1, Rs2 + * SMBT32 Rd, Rs1, Rs2 + * SMTT32 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Multiply the signed 32-bit element of a register with the signed 32-bit element of another + * register and write the 64-bit result to a third register. + * * SMBB32: bottom*bottom + * * SMBT32: bottom*top + * * SMTT32: top*top + * + * **Description**:\n + * For the `SMBB32` instruction, it multiplies the bottom 32-bit element of Rs1 with the bottom 32-bit + * element of Rs2. It is actually an alias of `MULSR64` instruction. + * For the `SMBT32` instruction, it multiplies the bottom 32-bit element of Rs1 with the top 32-bit + * element of Rs2. + * For the `SMTT32` instruction, it multiplies the top 32-bit element of Rs1 with the top 32-bit element + * of Rs2. + * The 64-bit multiplication result is written to Rd. The 32-bit contents of Rs1 and Rs2 are treated as + * signed integers. + * + * **Operations**:\n + * ~~~ + * res = Rs1.W[0] * Rs2.W[0]; // SMBB32 res = Rs1.W[0] * Rs2.w[1]; // SMBT32 res = Rs1.W[1] * Rs2.W[1]; + * // SMTT32 Rd = res; + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_SMBT32(unsigned long a, unsigned long b) +{ + register long result; + __ASM volatile("smbt32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 4.32.2. SMBT32 ===== */ + +/* ===== Inline Function Start for 4.32.3. SMTT32 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_MULT + * \brief SMTT32 (Signed Multiply Top Word & Top Word) + * \details + * **Type**: DSP (RV64 Only) + * + * **Syntax**:\n + * ~~~ + * SMBB32 Rd, Rs1, Rs2 + * SMBT32 Rd, Rs1, Rs2 + * SMTT32 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Multiply the signed 32-bit element of a register with the signed 32-bit element of another + * register and write the 64-bit result to a third register. + * * SMBB32: bottom*bottom + * * SMBT32: bottom*top + * * SMTT32: top*top + * + * **Description**:\n + * For the `SMBB32` instruction, it multiplies the bottom 32-bit element of Rs1 with the bottom 32-bit + * element of Rs2. It is actually an alias of `MULSR64` instruction. + * For the `SMBT32` instruction, it multiplies the bottom 32-bit element of Rs1 with the top 32-bit + * element of Rs2. + * For the `SMTT32` instruction, it multiplies the top 32-bit element of Rs1 with the top 32-bit element + * of Rs2. + * The 64-bit multiplication result is written to Rd. The 32-bit contents of Rs1 and Rs2 are treated as + * signed integers. + * + * **Operations**:\n + * ~~~ + * res = Rs1.W[0] * Rs2.W[0]; // SMBB32 res = Rs1.W[0] * Rs2.w[1]; // SMBT32 res = Rs1.W[1] * Rs2.W[1]; + * // SMTT32 Rd = res; + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_SMTT32(unsigned long a, unsigned long b) +{ + register long result; + __ASM volatile("smtt32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 4.32.3. SMTT32 ===== */ + +/* ===== Inline Function Start for 4.33.1. SMDS32 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_PARALLEL_MAC + * \brief SMDS32 (Signed Multiply Two Words and Subtract) + * \details + * **Type**: DSP (RV64 Only) + * + * **Syntax**:\n + * ~~~ + * SMDS32 Rd, Rs1, Rs2 + * SMDRS32 Rd, Rs1, Rs2 + * SMXDS32 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do two signed 32-bit multiplications from the l 32-bit element of two registers; and then + * perform a subtraction operation between the two 64-bit results. + * * SMDS32: top*top - bottom*bottom + * * SMDRS32: bottom*bottom - top*top + * * SMXDS32: top*bottom - bottom*top + * + * **Description**:\n + * For the `SMDS32` instruction, it multiplies the bottom 32-bit element of Rs1 with the bottom 32-bit + * element of Rs2 and then subtracts the result from the result of multiplying the top 32-bit element of + * Rs1 with the top 32-bit element of Rs2. + * For the `SMDRS32` instruction, it multiplies the top 32-bit element of Rs1 with the top 32-bit + * element of Rs2 and then subtracts the result from the result of multiplying the bottom 32-bit + * element of Rs1 with the bottom 32-bit element of Rs2. + * For the `SMXDS32` instruction, it multiplies the bottom 32-bit element of Rs1 with the top 32-bit + * element of Rs2 and then subtracts the result from the result of multiplying the top 32-bit element of + * Rs1 with the bottom 32-bit element of Rs2. + * The subtraction result is written to Rd. The 32-bit contents of Rs1 and Rs2 are treated as signed + * integers. + * + * **Operations**:\n + * ~~~ + * Rt = (Rs1.W[1] * Rs2.W[1]) - (Rs1.W[0] * Rs2.W[0]); // SMDS32 + * Rt = (Rs1.W[0] * Rs2.W[0]) - (Rs1.W[1] * Rs2.W[1]); // SMDRS32 + * Rt = (Rs1.W[1] * Rs2.W[0]) - (Rs1.W[0] * Rs2.W[1]); // SMXDS32 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_SMDS32(unsigned long a, unsigned long b) +{ + register long result; + __ASM volatile("smds32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 4.33.1. SMDS32 ===== */ + +/* ===== Inline Function Start for 4.33.2. SMDRS32 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_PARALLEL_MAC + * \brief SMDRS32 (Signed Multiply Two Words and Reverse Subtract) + * \details + * **Type**: DSP (RV64 Only) + * + * **Syntax**:\n + * ~~~ + * SMDS32 Rd, Rs1, Rs2 + * SMDRS32 Rd, Rs1, Rs2 + * SMXDS32 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do two signed 32-bit multiplications from the l 32-bit element of two registers; and then + * perform a subtraction operation between the two 64-bit results. + * * SMDS32: top*top - bottom*bottom + * * SMDRS32: bottom*bottom - top*top + * * SMXDS32: top*bottom - bottom*top + * + * **Description**:\n + * For the `SMDS32` instruction, it multiplies the bottom 32-bit element of Rs1 with the bottom 32-bit + * element of Rs2 and then subtracts the result from the result of multiplying the top 32-bit element of + * Rs1 with the top 32-bit element of Rs2. + * For the `SMDRS32` instruction, it multiplies the top 32-bit element of Rs1 with the top 32-bit + * element of Rs2 and then subtracts the result from the result of multiplying the bottom 32-bit + * element of Rs1 with the bottom 32-bit element of Rs2. + * For the `SMXDS32` instruction, it multiplies the bottom 32-bit element of Rs1 with the top 32-bit + * element of Rs2 and then subtracts the result from the result of multiplying the top 32-bit element of + * Rs1 with the bottom 32-bit element of Rs2. + * The subtraction result is written to Rd. The 32-bit contents of Rs1 and Rs2 are treated as signed + * integers. + * + * **Operations**:\n + * ~~~ + * Rt = (Rs1.W[1] * Rs2.W[1]) - (Rs1.W[0] * Rs2.W[0]); // SMDS32 + * Rt = (Rs1.W[0] * Rs2.W[0]) - (Rs1.W[1] * Rs2.W[1]); // SMDRS32 + * Rt = (Rs1.W[1] * Rs2.W[0]) - (Rs1.W[0] * Rs2.W[1]); // SMXDS32 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_SMDRS32(unsigned long a, unsigned long b) +{ + register long result; + __ASM volatile("smdrs32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 4.33.2. SMDRS32 ===== */ + +/* ===== Inline Function Start for 4.33.3. SMXDS32 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_PARALLEL_MAC + * \brief SMXDS32 (Signed Crossed Multiply Two Words and Subtract) + * \details + * **Type**: DSP (RV64 Only) + * + * **Syntax**:\n + * ~~~ + * SMDS32 Rd, Rs1, Rs2 + * SMDRS32 Rd, Rs1, Rs2 + * SMXDS32 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do two signed 32-bit multiplications from the l 32-bit element of two registers; and then + * perform a subtraction operation between the two 64-bit results. + * * SMDS32: top*top - bottom*bottom + * * SMDRS32: bottom*bottom - top*top + * * SMXDS32: top*bottom - bottom*top + * + * **Description**:\n + * For the `SMDS32` instruction, it multiplies the bottom 32-bit element of Rs1 with the bottom 32-bit + * element of Rs2 and then subtracts the result from the result of multiplying the top 32-bit element of + * Rs1 with the top 32-bit element of Rs2. + * For the `SMDRS32` instruction, it multiplies the top 32-bit element of Rs1 with the top 32-bit + * element of Rs2 and then subtracts the result from the result of multiplying the bottom 32-bit + * element of Rs1 with the bottom 32-bit element of Rs2. + * For the `SMXDS32` instruction, it multiplies the bottom 32-bit element of Rs1 with the top 32-bit + * element of Rs2 and then subtracts the result from the result of multiplying the top 32-bit element of + * Rs1 with the bottom 32-bit element of Rs2. + * The subtraction result is written to Rd. The 32-bit contents of Rs1 and Rs2 are treated as signed + * integers. + * + * **Operations**:\n + * ~~~ + * Rt = (Rs1.W[1] * Rs2.W[1]) - (Rs1.W[0] * Rs2.W[0]); // SMDS32 + * Rt = (Rs1.W[0] * Rs2.W[0]) - (Rs1.W[1] * Rs2.W[1]); // SMDRS32 + * Rt = (Rs1.W[1] * Rs2.W[0]) - (Rs1.W[0] * Rs2.W[1]); // SMXDS32 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_SMXDS32(unsigned long a, unsigned long b) +{ + register long result; + __ASM volatile("smxds32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 4.33.3. SMXDS32 ===== */ + +/* ===== Inline Function Start for 4.34. SMIN32 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_MISC + * \brief SMIN32 (SIMD 32-bit Signed Minimum) + * \details + * **Type**: SIMD (RV64 Only) + * + * **Syntax**:\n + * ~~~ + * SMIN32 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 32-bit signed integer elements finding minimum operations simultaneously. + * + * **Description**:\n + * This instruction compares the 32-bit signed integer elements in Rs1 with the 32-bit + * signed integer elements in Rs2 and selects the numbers that is less than the other one. The selected + * results are written to Rd. + * + * **Operations**:\n + * ~~~ + * Rd.W[x] = (Rs1.W[x] < Rs2.W[x])? Rs1.W[x] : Rs2.W[x]; + * for RV64: x=1...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_SMIN32(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("smin32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 4.34. SMIN32 ===== */ + +/* ===== Inline Function Start for 4.35.1. SRA32 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_SHIFT + * \brief SRA32 (SIMD 32-bit Shift Right Arithmetic) + * \details + * **Type**: SIMD (RV64 Only) + * + * **Syntax**:\n + * ~~~ + * SRA32 Rd, Rs1, Rs2 + * SRA32.u Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 32-bit element arithmetic right shift operations simultaneously. The shift amount is a + * variable from a GPR. The `.u` form performs additional rounding up operations on the shifted + * results. + * + * **Description**:\n + * The 32-bit data elements in Rs1 are right-shifted arithmetically, that is, the shifted out + * bits are filled with the sign-bit of the data elements. The shift amount is specified by the low-order + * 5-bits of the value in the Rs2 register. For the rounding operation of the `.u` form, a value of 1 is + * added to the most significant discarded bit of each 32-bit data element to calculate the final results. + * And the results are written to Rd. + * + * **Operations**:\n + * ~~~ + * sa = Rs2[4:0]; + * if (sa > 0) { + * if (`.u` form) { // SRA32.u + * res[31:-1] = SE33(Rs1.W[x][31:sa-1]) + 1; + * Rd.W[x] = res[31:0]; + * else { // SRA32 + * Rd.W[x] = SE32(Rs1.W[x][31:sa]) + * } + * } else { + * Rd = Rs1; + * } + * for RV64: x=1...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned int type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_SRA32(unsigned long a, unsigned int b) +{ + register unsigned long result; + __ASM volatile("sra32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 4.35.1. SRA32 ===== */ + +/* ===== Inline Function Start for 4.35.2. SRA32.u ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_SHIFT + * \brief SRA32.u (SIMD 32-bit Rounding Shift Right Arithmetic) + * \details + * **Type**: SIMD (RV64 Only) + * + * **Syntax**:\n + * ~~~ + * SRA32 Rd, Rs1, Rs2 + * SRA32.u Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 32-bit element arithmetic right shift operations simultaneously. The shift amount is a + * variable from a GPR. The `.u` form performs additional rounding up operations on the shifted + * results. + * + * **Description**:\n + * The 32-bit data elements in Rs1 are right-shifted arithmetically, that is, the shifted out + * bits are filled with the sign-bit of the data elements. The shift amount is specified by the low-order + * 5-bits of the value in the Rs2 register. For the rounding operation of the `.u` form, a value of 1 is + * added to the most significant discarded bit of each 32-bit data element to calculate the final results. + * And the results are written to Rd. + * + * **Operations**:\n + * ~~~ + * sa = Rs2[4:0]; + * if (sa > 0) { + * if (`.u` form) { // SRA32.u + * res[31:-1] = SE33(Rs1.W[x][31:sa-1]) + 1; + * Rd.W[x] = res[31:0]; + * else { // SRA32 + * Rd.W[x] = SE32(Rs1.W[x][31:sa]) + * } + * } else { + * Rd = Rs1; + * } + * for RV64: x=1...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned int type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_SRA32_U(unsigned long a, unsigned int b) +{ + register unsigned long result; + __ASM volatile("sra32.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 4.35.2. SRA32.u ===== */ + +/* ===== Inline Function Start for 4.36.1. SRAI32 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_SHIFT + * \brief SRAI32 (SIMD 32-bit Shift Right Arithmetic Immediate) + * \details + * **Type**: DSP (RV64 Only) + * + * **Syntax**:\n + * ~~~ + * SRAI32 Rd, Rs1, imm5u + * SRAI32.u Rd, Rs1, imm5u + * ~~~ + * + * **Purpose**:\n + * Do 32-bit elements arithmetic right shift operations simultaneously. The shift amount is + * an immediate value. The `.u` form performs additional rounding up operations on the shifted + * results. + * + * **Description**:\n + * The 32-bit data elements in Rs1 are right-shifted arithmetically, that is, the shifted out + * bits are filled with the sign-bit of the 32-bit data elements. The shift amount is specified by the + * imm5u constant. For the rounding operation of the `.u` form, a value of 1 is added to the most + * significant discarded bit of each 32-bit data to calculate the final results. And the results are written + * to Rd. + * + * **Operations**:\n + * ~~~ + * sa = imm5u[4:0]; + * if (sa > 0) { + * if (`.u` form) { // SRAI32.u + * res[31:-1] = SE33(Rs1.W[x][31:sa-1]) + 1; + * Rd.W[x] = res[31:0]; + * else { // SRAI32 + * Rd.W[x] = SE32(Rs1.W[x][31:sa]); + * } + * } else { + * Rd = Rs1; + * } + * for RV64: x=1...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned int type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_SRAI32(unsigned long a, unsigned int b) +{ + register unsigned long result; + __ASM volatile("srai32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 4.36.1. SRAI32 ===== */ + +/* ===== Inline Function Start for 4.36.2. SRAI32.u ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_SHIFT + * \brief SRAI32.u (SIMD 32-bit Rounding Shift Right Arithmetic Immediate) + * \details + * **Type**: DSP (RV64 Only) + * + * **Syntax**:\n + * ~~~ + * SRAI32 Rd, Rs1, imm5u + * SRAI32.u Rd, Rs1, imm5u + * ~~~ + * + * **Purpose**:\n + * Do 32-bit elements arithmetic right shift operations simultaneously. The shift amount is + * an immediate value. The `.u` form performs additional rounding up operations on the shifted + * results. + * + * **Description**:\n + * The 32-bit data elements in Rs1 are right-shifted arithmetically, that is, the shifted out + * bits are filled with the sign-bit of the 32-bit data elements. The shift amount is specified by the + * imm5u constant. For the rounding operation of the `.u` form, a value of 1 is added to the most + * significant discarded bit of each 32-bit data to calculate the final results. And the results are written + * to Rd. + * + * **Operations**:\n + * ~~~ + * sa = imm5u[4:0]; + * if (sa > 0) { + * if (`.u` form) { // SRAI32.u + * res[31:-1] = SE33(Rs1.W[x][31:sa-1]) + 1; + * Rd.W[x] = res[31:0]; + * else { // SRAI32 + * Rd.W[x] = SE32(Rs1.W[x][31:sa]); + * } + * } else { + * Rd = Rs1; + * } + * for RV64: x=1...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned int type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_SRAI32_U(unsigned long a, unsigned int b) +{ + register unsigned long result; + __ASM volatile("srai32.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 4.36.2. SRAI32.u ===== */ + +/* ===== Inline Function Start for 4.37. SRAIW.u ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_NON_SIMD_32B_SHIFT + * \brief SRAIW.u (Rounding Shift Right Arithmetic Immediate Word) + * \details + * **Type**: DSP (RV64 only) + * + * **Syntax**:\n + * ~~~ + * SRAIW.u Rd, Rs1, imm5u + * ~~~ + * + * **Purpose**:\n + * Perform a 32-bit arithmetic right shift operation with rounding. The shift amount is an + * immediate value. + * + * **Description**:\n + * This instruction right-shifts the lower 32-bit content of Rs1 arithmetically. The shifted + * out bits are filled with the sign-bit Rs1(31) and the shift amount is specified by the imm5u constant. + * For the rounding operation, a value of 1 is added to the most significant discarded bit of the data to + * calculate the final result. And the result is sign-extended and written to Rd. + * + * **Operations**:\n + * ~~~ + * sa = imm5u; + * if (sa != 0) { + * res[31:-1] = SE33(Rs1[31:(sa-1)]) + 1; + * Rd = SE32(res[31:0]); + * } else { + * Rd = SE32(Rs1.W[0]); + * } + * ~~~ + * + * \param [in] a int type of value stored in a + * \param [in] b unsigned int type of value stored in b + * \return value stored in long type + */ +__STATIC_FORCEINLINE long __RV_SRAIW_U(int a, unsigned int b) +{ + register long result; + __ASM volatile("sraiw.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 4.37. SRAIW.u ===== */ + +/* ===== Inline Function Start for 4.38.1. SRL32 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_SHIFT + * \brief SRL32 (SIMD 32-bit Shift Right Logical) + * \details + * **Type**: SIMD (RV64 Only) + * + * **Syntax**:\n + * ~~~ + * SRL32 Rd, Rs1, Rs2 + * SRL32.u Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 32-bit element logical right shift operations simultaneously. The shift amount is a + * variable from a GPR. The `.u` form performs additional rounding up operations on the shifted + * results. + * + * **Description**:\n + * The 32-bit data elements in Rs1 are right-shifted logically, that is, the shifted out bits + * are filled with zero. The shift amount is specified by the low-order 5-bits of the value in the Rs2 + * register. For the rounding operation of the `.u` form, a value of 1 is added to the most significant + * discarded bit of each 32-bit data element to calculate the final results. And the results are written to + * Rd. + * + * **Operations**:\n + * ~~~ + * sa = Rs2[4:0]; + * if (sa > 0) { + * if (`.u` form) { // SRA32.u + * res[31:-1] = ZE33(Rs1.W[x][31:sa-1]) + 1; + * Rd.W[x] = res[31:0]; + * else { // SRA32 + * Rd.W[x] = ZE32(Rs1.W[x][31:sa]) + * } + * } else { + * Rd = Rs1; + * } + * for RV64: x=1...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned int type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_SRL32(unsigned long a, unsigned int b) +{ + register unsigned long result; + __ASM volatile("srl32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 4.38.1. SRL32 ===== */ + +/* ===== Inline Function Start for 4.38.2. SRL32.u ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_SHIFT + * \brief SRL32.u (SIMD 32-bit Rounding Shift Right Logical) + * \details + * **Type**: SIMD (RV64 Only) + * + * **Syntax**:\n + * ~~~ + * SRL32 Rd, Rs1, Rs2 + * SRL32.u Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 32-bit element logical right shift operations simultaneously. The shift amount is a + * variable from a GPR. The `.u` form performs additional rounding up operations on the shifted + * results. + * + * **Description**:\n + * The 32-bit data elements in Rs1 are right-shifted logically, that is, the shifted out bits + * are filled with zero. The shift amount is specified by the low-order 5-bits of the value in the Rs2 + * register. For the rounding operation of the `.u` form, a value of 1 is added to the most significant + * discarded bit of each 32-bit data element to calculate the final results. And the results are written to + * Rd. + * + * **Operations**:\n + * ~~~ + * sa = Rs2[4:0]; + * if (sa > 0) { + * if (`.u` form) { // SRA32.u + * res[31:-1] = ZE33(Rs1.W[x][31:sa-1]) + 1; + * Rd.W[x] = res[31:0]; + * else { // SRA32 + * Rd.W[x] = ZE32(Rs1.W[x][31:sa]) + * } + * } else { + * Rd = Rs1; + * } + * for RV64: x=1...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned int type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_SRL32_U(unsigned long a, unsigned int b) +{ + register unsigned long result; + __ASM volatile("srl32.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 4.38.2. SRL32.u ===== */ + +/* ===== Inline Function Start for 4.39.1. SRLI32 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_SHIFT + * \brief SRLI32 (SIMD 32-bit Shift Right Logical Immediate) + * \details + * **Type**: SIMD (RV64 Only) + * + * **Syntax**:\n + * ~~~ + * SRLI32 Rd, Rs1, imm5u + * SRLI32.u Rd, Rs1, imm5u + * ~~~ + * + * **Purpose**:\n + * Do 32-bit elements logical right shift operations simultaneously. The shift amount is an + * immediate value. The `.u` form performs additional rounding up operations on the shifted results. + * + * **Description**:\n + * The 32-bit data elements in Rs1 are right-shifted logically, that is, the shifted out bits + * are filled with zero. The shift amount is specified by the imm5u constant. For the rounding + * operation of the `.u` form, a value of 1 is added to the most significant discarded bit of each 32-bit + * data to calculate the final results. And the results are written to Rd. + * + * **Operations**:\n + * ~~~ + * sa = imm5u[4:0]; + * if (sa > 0) { + * if (`.u` form) { // SRLI32.u + * res[31:-1] = ZE33(Rs1.W[x][31:sa-1]) + 1; + * Rd.W[x] = res[31:0]; + * else { // SRLI32 + * Rd.W[x] = ZE32(Rs1.W[x][31:sa]); + * } + * } else { + * Rd = Rs1; + * } + * for RV64: x=1...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned int type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_SRLI32(unsigned long a, unsigned int b) +{ + register unsigned long result; + __ASM volatile("srli32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 4.39.1. SRLI32 ===== */ + +/* ===== Inline Function Start for 4.39.2. SRLI32.u ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_SHIFT + * \brief SRLI32.u (SIMD 32-bit Rounding Shift Right Logical Immediate) + * \details + * **Type**: SIMD (RV64 Only) + * + * **Syntax**:\n + * ~~~ + * SRLI32 Rd, Rs1, imm5u + * SRLI32.u Rd, Rs1, imm5u + * ~~~ + * + * **Purpose**:\n + * Do 32-bit elements logical right shift operations simultaneously. The shift amount is an + * immediate value. The `.u` form performs additional rounding up operations on the shifted results. + * + * **Description**:\n + * The 32-bit data elements in Rs1 are right-shifted logically, that is, the shifted out bits + * are filled with zero. The shift amount is specified by the imm5u constant. For the rounding + * operation of the `.u` form, a value of 1 is added to the most significant discarded bit of each 32-bit + * data to calculate the final results. And the results are written to Rd. + * + * **Operations**:\n + * ~~~ + * sa = imm5u[4:0]; + * if (sa > 0) { + * if (`.u` form) { // SRLI32.u + * res[31:-1] = ZE33(Rs1.W[x][31:sa-1]) + 1; + * Rd.W[x] = res[31:0]; + * else { // SRLI32 + * Rd.W[x] = ZE32(Rs1.W[x][31:sa]); + * } + * } else { + * Rd = Rs1; + * } + * for RV64: x=1...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned int type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_SRLI32_U(unsigned long a, unsigned int b) +{ + register unsigned long result; + __ASM volatile("srli32.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 4.39.2. SRLI32.u ===== */ + +/* ===== Inline Function Start for 4.40. STAS32 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB + * \brief STAS32 (SIMD 32-bit Straight Addition & Subtraction) + * \details + * **Type**: SIMD (RV64 Only) + * + * **Syntax**:\n + * ~~~ + * STAS32 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 32-bit integer element addition and 32-bit integer element subtraction in a 64-bit + * chunk simultaneously. Operands are from corresponding 32-bit elements. + * + * **Description**:\n + * This instruction adds the 32-bit integer element in [63:32] of Rs1 with the 32-bit + * integer element in [63:32] of Rs2, and writes the result to [63:32] of Rd; at the same time, it subtracts + * the 32-bit integer element in [31:0] of Rs2 from the 32-bit integer element in [31:0] of Rs1, and + * writes the result to [31:0] of Rd. + * + * **Note**:\n + * This instruction can be used for either signed or unsigned operations. + * + * **Operations**:\n + * ~~~ + * Rd.W[1] = Rs1.W[1] + Rs2.W[1]; + * Rd.W[0] = Rs1.W[0] - Rs2.W[0]; + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_STAS32(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("stas32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 4.40. STAS32 ===== */ + +/* ===== Inline Function Start for 4.41. STSA32 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB + * \brief STSA32 (SIMD 32-bit Straight Subtraction & Addition) + * \details + * **Type**: SIMD (RV64 Only) + * + * **Syntax**:\n + * ~~~ + * STSA32 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 32-bit integer element subtraction and 32-bit integer element addition in a 64-bit + * chunk simultaneously. Operands are from corresponding 32-bit elements. + * *Description: * + * This instruction subtracts the 32-bit integer element in [63:32] of Rs2 from the 32-bit integer + * element in [63:32] of Rs1, and writes the result to [63:32] of Rd; at the same time, it adds the 32-bit + * integer element in [31:0] of Rs1 with the 32-bit integer element in [31:0] of Rs2, and writes the result + * to [31:0] of Rd + * + * **Note**:\n + * This instruction can be used for either signed or unsigned operations. + * + * **Operations**:\n + * ~~~ + * Rd.W[1] = Rs1.W[1] - Rs2.W[1]; + * Rd.W[0] = Rs1.W[0] + Rs2.W[0]; + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_STSA32(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("stsa32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 4.41. STSA32 ===== */ + +/* ===== Inline Function Start for 4.42. SUB32 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB + * \brief SUB32 (SIMD 32-bit Subtraction) + * \details + * **Type**: DSP (RV64 Only) + * + * **Syntax**:\n + * ~~~ + * SUB32 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 32-bit integer element subtractions simultaneously. + * + * **Description**:\n + * This instruction subtracts the 32-bit integer elements in Rs2 from the 32-bit integer + * elements in Rs1, and then writes the results to Rd. + * + * **Note**:\n + * This instruction can be used for either signed or unsigned subtraction. + * + * **Operations**:\n + * ~~~ + * Rd.W[x] = Rs1.W[x] - Rs2.W[x]; + * for RV64: x=1...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_SUB32(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("sub32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 4.42. SUB32 ===== */ + +/* ===== Inline Function Start for 4.43. UKADD32 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB + * \brief UKADD32 (SIMD 32-bit Unsigned Saturating Addition) + * \details + * **Type**: SIMD (RV64 Only) + * + * **Syntax**:\n + * ~~~ + * UKADD32 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 32-bit unsigned integer element saturating additions simultaneously. + * + * **Description**:\n + * This instruction adds the 32-bit unsigned integer elements in Rs1 with the 32-bit + * unsigned integer elements in Rs2. If any of the results are beyond the 32-bit unsigned number + * range (0 <= RES <= 2^32-1), they are saturated to the range and the OV bit is set to 1. The saturated + * results are written to Rd. + * + * **Operations**:\n + * ~~~ + * res[x] = Rs1.W[x] + Rs2.W[x]; + * if (res[x] > (2^32)-1) { + * res[x] = (2^32)-1; + * OV = 1; + * } + * Rd.W[x] = res[x]; + * for RV64: x=1...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_UKADD32(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("ukadd32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 4.43. UKADD32 ===== */ + +/* ===== Inline Function Start for 4.44. UKCRAS32 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB + * \brief UKCRAS32 (SIMD 32-bit Unsigned Saturating Cross Addition & Subtraction) + * \details + * **Type**: SIMD (RV64 Only) + * + * **Syntax**:\n + * ~~~ + * UKCRAS32 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do one 32-bit unsigned integer element saturating addition and one 32-bit unsigned + * integer element saturating subtraction in a 64-bit chunk simultaneously. Operands are from crossed + * 32-bit elements. + * + * **Description**:\n + * This instruction adds the 32-bit unsigned integer element in [63:32] of Rs1 with the 32- + * bit unsigned integer element in [31:0] of Rs2; at the same time, it subtracts the 32-bit unsigned + * integer element in [63:32] of Rs2 from the 32-bit unsigned integer element in [31:0] Rs1. If any of the + * results are beyond the 32-bit unsigned number range (0 <= RES <= 2^32-1), they are saturated to the + * range and the OV bit is set to 1. The saturated results are written to [63:32] of Rd for addition and + * [31:0] of Rd for subtraction. + * + * **Operations**:\n + * ~~~ + * res1 = Rs1.W[1] + Rs2.W[0]; + * res2 = Rs1.W[0] - Rs2.W[1]; + * if (res1 > (2^32)-1) { + * res1 = (2^32)-1; + * OV = 1; + * } + * if (res2 < 0) { + * res2 = 0; + * OV = 1; + * } + * Rd.W[1] = res1; + * Rd.W[0] = res2; + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_UKCRAS32(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("ukcras32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 4.44. UKCRAS32 ===== */ + +/* ===== Inline Function Start for 4.45. UKCRSA32 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB + * \brief UKCRSA32 (SIMD 32-bit Unsigned Saturating Cross Subtraction & Addition) + * \details + * **Type**: SIMD (RV64 Only) + * + * **Syntax**:\n + * ~~~ + * UKCRSA32 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do one 32-bit unsigned integer element saturating subtraction and one 32-bit unsigned + * integer element saturating addition in a 64-bit chunk simultaneously. Operands are from crossed + * 32-bit elements. + * + * **Description**:\n + * This instruction subtracts the 32-bit unsigned integer element in [31:0] of Rs2 from the + * 32-bit unsigned integer element in [63:32] of Rs1; at the same time, it adds the 32-bit unsigned + * integer element in [63:32] of Rs2 with the 32-bit unsigned integer element in [31:0] Rs1. If any of the + * results are beyond the 32-bit unsigned number range (0 <= RES <= 2^32-1), they are saturated to the + * range and the OV bit is set to 1. The saturated results are written to [63:32] of Rd for subtraction and + * [31:0] of Rd for addition. + * + * **Operations**:\n + * ~~~ + * res1 = Rs1.W[1] - Rs2.W[0]; + * res2 = Rs1.W[0] + Rs2.W[1]; + * if (res1 < 0) { + * res1 = 0; + * OV = 1; + * } else if (res2 > (2^32)-1) { + * res2 = (2^32)-1; + * OV = 1; + * } + * Rd.W[1] = res1; + * Rd.W[0] = res2; + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_UKCRSA32(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("ukcrsa32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 4.45. UKCRSA32 ===== */ + +/* ===== Inline Function Start for 4.46. UKSTAS32 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB + * \brief UKSTAS32 (SIMD 32-bit Unsigned Saturating Straight Addition & Subtraction) + * \details + * **Type**: SIMD (RV64 Only) + * + * **Syntax**:\n + * ~~~ + * UKSTAS32 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do one 32-bit unsigned integer element saturating addition and one 32-bit unsigned + * integer element saturating subtraction in a 64-bit chunk simultaneously. Operands are from + * corresponding 32-bit elements. + * + * **Description**:\n + * This instruction adds the 32-bit unsigned integer element in [63:32] of Rs1 with the 32- + * bit unsigned integer element in [63:32] of Rs2; at the same time, it subtracts the 32-bit unsigned + * integer element in [31:0] of Rs2 from the 32-bit unsigned integer element in [31:0] Rs1. If any of the + * results are beyond the 32-bit unsigned number range (0 <= RES <= 2^32-1), they are saturated to the + * range and the OV bit is set to 1. The saturated results are written to [63:32] of Rd for addition and + * [31:0] of Rd for subtraction. + * + * **Operations**:\n + * ~~~ + * res1 = Rs1.W[1] + Rs2.W[1]; + * res2 = Rs1.W[0] - Rs2.W[0]; + * if (res1 > (2^32)-1) { + * res1 = (2^32)-1; + * OV = 1; + * } + * if (res2 < 0) { + * res2 = 0; + * OV = 1; + * } + * Rd.W[1] = res1; + * Rd.W[0] = res2; + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_UKSTAS32(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("ukstas32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 4.46. UKSTAS32 ===== */ + +/* ===== Inline Function Start for 4.47. UKSTSA32 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB + * \brief UKSTSA32 (SIMD 32-bit Unsigned Saturating Straight Subtraction & Addition) + * \details + * **Type**: SIMD (RV64 Only) + * + * **Syntax**:\n + * ~~~ + * UKSTSA32 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do one 32-bit unsigned integer element saturating subtraction and one 32-bit unsigned + * integer element saturating addition in a 64-bit chunk simultaneously. Operands are from + * corresponding 32-bit elements. + * + * **Description**:\n + * This instruction subtracts the 32-bit unsigned integer element in [63:32] of Rs2 from + * the 32-bit unsigned integer element in [63:32] of Rs1; at the same time, it adds the 32-bit unsigned + * integer element in [31:0] of Rs2 with the 32-bit unsigned integer element in [31:0] Rs1. If any of the + * results are beyond the 32-bit unsigned number range (0 <= RES <= 2^32-1), they are saturated to the + * range and the OV bit is set to 1. The saturated results are written to [63:32] of Rd for subtraction and + * [31:0] of Rd for addition. + * + * **Operations**:\n + * ~~~ + * res1 = Rs1.W[1] - Rs2.W[1]; + * res2 = Rs1.W[0] + Rs2.W[0]; + * if (res1 < 0) { + * res1 = 0; + * OV = 1; + * } else if (res2 > (2^32)-1) { + * res2 = (2^32)-1; + * OV = 1; + * } + * Rd.W[1] = res1; + * Rd.W[0] = res2; + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_UKSTSA32(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("ukstsa32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 4.47. UKSTSA32 ===== */ + +/* ===== Inline Function Start for 4.48. UKSUB32 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB + * \brief UKSUB32 (SIMD 32-bit Unsigned Saturating Subtraction) + * \details + * **Type**: SIMD (RV64 Only) + * + * **Syntax**:\n + * ~~~ + * UKSUB32 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 32-bit unsigned integer elements saturating subtractions simultaneously. + * + * **Description**:\n + * This instruction subtracts the 32-bit unsigned integer elements in Rs2 from the 32-bit + * unsigned integer elements in Rs1. If any of the results are beyond the 32-bit unsigned number + * range (0 <= RES <= 2^32-1), they are saturated to the range and the OV bit is set to 1. The saturated + * results are written to Rd. + * + * **Operations**:\n + * ~~~ + * res[x] = Rs1.W[x] - Rs2.W[x]; + * if (res[x] < 0) { + * res[x] = 0; + * OV = 1; + * } + * Rd.W[x] = res[x]; + * for RV64: x=1...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_UKSUB32(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("uksub32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 4.48. UKSUB32 ===== */ + +/* ===== Inline Function Start for 4.49. UMAX32 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_MISC + * \brief UMAX32 (SIMD 32-bit Unsigned Maximum) + * \details + * **Type**: SIMD (RV64 Only) + * + * **Syntax**:\n + * ~~~ + * UMAX32 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 32-bit unsigned integer elements finding maximum operations simultaneously. + * + * **Description**:\n + * This instruction compares the 32-bit unsigned integer elements in Rs1 with the 32-bit + * unsigned integer elements in Rs2 and selects the numbers that is greater than the other one. The + * selected results are written to Rd. + * + * **Operations**:\n + * ~~~ + * Rd.W[x] = (Rs1.W[x] u> Rs2.W[x])? Rs1.W[x] : Rs2.W[x]; + * for RV64: x=1...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_UMAX32(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("umax32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 4.49. UMAX32 ===== */ + +/* ===== Inline Function Start for 4.50. UMIN32 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_MISC + * \brief UMIN32 (SIMD 32-bit Unsigned Minimum) + * \details + * **Type**: SIMD (RV64 Only) + * + * **Syntax**:\n + * ~~~ + * UMIN32 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 32-bit unsigned integer elements finding minimum operations simultaneously. + * + * **Description**:\n + * This instruction compares the 32-bit unsigned integer elements in Rs1 with the 32-bit + * unsigned integer elements in Rs2 and selects the numbers that is less than the other one. The + * selected results are written to Rd. + * + * **Operations**:\n + * ~~~ + * Rd.W[x] = (Rs1.W[x] > 1; + * for RV64: x=1...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_URADD32(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("uradd32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 4.51. URADD32 ===== */ + +/* ===== Inline Function Start for 4.52. URCRAS32 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB + * \brief URCRAS32 (SIMD 32-bit Unsigned Halving Cross Addition & Subtraction) + * \details + * **Type**: SIMD (RV64 Only) + * + * **Syntax**:\n + * ~~~ + * URCRAS32 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 32-bit unsigned integer element addition and 32-bit unsigned integer element + * subtraction in a 64-bit chunk simultaneously. Operands are from crossed 32-bit elements. The + * results are halved to avoid overflow or saturation. + * + * **Description**:\n + * This instruction adds the 32-bit unsigned integer element in [63:32] of Rs1 with the 32- + * bit unsigned integer element in [31:0] of Rs2, and subtracts the 32-bit unsigned integer element in + * [63:32] of Rs2 from the 32-bit unsigned integer element in [31:0] of Rs1. The element results are first + * logically right-shifted by 1 bit and then written to [63:32] of Rd for addition and [31:0] of Rd for + * subtraction. + * + * **Examples**:\n + * ~~~ + * Please see `URADD32` and `URSUB32` instructions. + * ~~~ + * + * **Operations**:\n + * ~~~ + * Rd.W[1] = (Rs1.W[1] + Rs2.W[0]) u>> 1; + * Rd.W[0] = (Rs1.W[0] - Rs2.W[1]) u>> 1; + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_URCRAS32(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("urcras32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 4.52. URCRAS32 ===== */ + +/* ===== Inline Function Start for 4.53. URCRSA32 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB + * \brief URCRSA32 (SIMD 32-bit Unsigned Halving Cross Subtraction & Addition) + * \details + * **Type**: SIMD (RV64 Only) + * + * **Syntax**:\n + * ~~~ + * URCRSA32 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 32-bit unsigned integer element subtraction and 32-bit unsigned integer element + * addition in a 64-bit chunk simultaneously. Operands are from crossed 32-bit elements. The results + * are halved to avoid overflow or saturation. + * + * **Description**:\n + * This instruction subtracts the 32-bit unsigned integer element in [31:0] of Rs2 from the + * 32-bit unsigned integer element in [63:32] of Rs1, and adds the 32-bit unsigned element integer in + * [31:0] of Rs1 with the 32-bit unsigned integer element in [63:32] of Rs2. The two results are first + * logically right-shifted by 1 bit and then written to [63:32] of Rd for subtraction and [31:0] of Rd for + * addition. + * + * **Examples**:\n + * ~~~ + * Please see `URADD32` and `URSUB32` instructions. + * ~~~ + * + * **Operations**:\n + * ~~~ + * Rd.W[1] = (Rs1.W[1] - Rs2.W[0]) u>> 1; + * Rd.W[0] = (Rs1.W[0] + Rs2.W[1]) u>> 1; + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_URCRSA32(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("urcrsa32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 4.53. URCRSA32 ===== */ + +/* ===== Inline Function Start for 4.54. URSTAS32 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB + * \brief URSTAS32 (SIMD 32-bit Unsigned Halving Straight Addition & Subtraction) + * \details + * **Type**: SIMD (RV64 Only) + * + * **Syntax**:\n + * ~~~ + * URSTAS32 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 32-bit unsigned integer element addition and 32-bit unsigned integer element + * subtraction in a 64-bit chunk simultaneously. Operands are from corresponding 32-bit elements. + * The results are halved to avoid overflow or saturation. + * + * **Description**:\n + * This instruction adds the 32-bit unsigned integer element in [63:32] of Rs1 with the 32- + * bit unsigned integer element in [63:32] of Rs2, and subtracts the 32-bit unsigned integer element in + * [31:0] of Rs2 from the 32-bit unsigned integer element in [31:0] of Rs1. The element results are first + * logically right-shifted by 1 bit and then written to [63:32] of Rd for addition and [31:0] of Rd for + * subtraction. + * + * **Examples**:\n + * ~~~ + * Please see `URADD32` and `URSUB32` instructions. + * ~~~ + * + * **Operations**:\n + * ~~~ + * Rd.W[1] = (Rs1.W[1] + Rs2.W[1]) u>> 1; + * Rd.W[0] = (Rs1.W[0] - Rs2.W[0]) u>> 1; + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_URSTAS32(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("urstas32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 4.54. URSTAS32 ===== */ + +/* ===== Inline Function Start for 4.55. URSTSA32 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB + * \brief URSTSA32 (SIMD 32-bit Unsigned Halving Straight Subtraction & Addition) + * \details + * **Type**: SIMD (RV64 Only) + * + * **Syntax**:\n + * ~~~ + * URSTSA32 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 32-bit unsigned integer element subtraction and 32-bit unsigned integer element + * addition in a 64-bit chunk simultaneously. Operands are from corresponding 32-bit elements. The + * results are halved to avoid overflow or saturation. + * + * **Description**:\n + * This instruction subtracts the 32-bit unsigned integer element in [63:32] of Rs2 from + * the 32-bit unsigned integer element in [63:32] of Rs1, and adds the 32-bit unsigned element integer + * in [31:0] of Rs1 with the 32-bit unsigned integer element in [31:0] of Rs2. The two results are first + * logically right-shifted by 1 bit and then written to [63:32] of Rd for subtraction and [31:0] of Rd for + * addition. + * + * **Examples**:\n + * ~~~ + * Please see `URADD32` and `URSUB32` instructions. + * ~~~ + * + * **Operations**:\n + * ~~~ + * Rd.W[1] = (Rs1.W[1] - Rs2.W[1]) u>> 1; + * Rd.W[0] = (Rs1.W[0] + Rs2.W[0]) u>> 1; + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_URSTSA32(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("urstsa32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 4.55. URSTSA32 ===== */ + +/* ===== Inline Function Start for 4.56. URSUB32 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB + * \brief URSUB32 (SIMD 32-bit Unsigned Halving Subtraction) + * \details + * **Type**: SIMD (RV64 Only) + * + * **Syntax**:\n + * ~~~ + * URSUB32 Rd, Rs1, Rs2 + * ~~~ + * + * **Purpose**:\n + * Do 32-bit unsigned integer element subtractions simultaneously. The results are halved to + * avoid overflow or saturation. + * + * **Description**:\n + * This instruction subtracts the 32-bit unsigned integer elements in Rs2 from the 32-bit + * unsigned integer elements in Rs1. The results are first logically right-shifted by 1 bit and then + * written to Rd. + * + * **Examples**:\n + * ~~~ + * * Ra = 0x7FFFFFFF, Rb = 0x80000000, Rt = 0xFFFFFFFF + * * Ra = 0x80000000, Rb = 0x7FFFFFFF, Rt = 0x00000000 + * * Ra = 0x80000000, Rb = 0x40000000, Rt = 0x20000000 + * ~~~ + * + * **Operations**:\n + * ~~~ + * Rd.W[x] = (Rs1.W[x] - Rs2.W[x]) u>> 1; + * for RV64: x=1...0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \param [in] b unsigned long type of value stored in b + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_URSUB32(unsigned long a, unsigned long b) +{ + register unsigned long result; + __ASM volatile("ursub32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for 4.56. URSUB32 ===== */ + +#endif /* __RISCV_XLEN == 64 */ + + +#if (__RISCV_XLEN == 32) || defined(__ONLY_FOR_DOXYGEN_DOCUMENT_GENERATION__) +/* XXXXX Nuclei Extended DSP Instructions for RV32 XXXXX */ +/** + * \defgroup NMSIS_Core_DSP_Intrinsic_NUCLEI_CUSTOM Nuclei Customized DSP Instructions + * \ingroup NMSIS_Core_DSP_Intrinsic + * \brief (RV32 only)Nuclei Customized DSP Instructions + * \details This is Nuclei customized DSP instructions only for RV32 + */ +/* ===== Inline Function Start for A.1. DKHM8 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_NUCLEI_CUSTOM + * \brief DKHM8 (64-bit SIMD Signed Saturating Q7 Multiply) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * DKHM8 Rd, Rs1, Rs2 + * # Rd, Rs1, Rs2 are all even/odd pair of registers + * ~~~ + * + * **Purpose**:\n + * Do Q7xQ7 element multiplications simultaneously. The Q14 results are then reduced to Q7 + * numbers again. + * + * **Description**:\n + * For the `DKHM8` instruction, multiply the top 8-bit Q7 content of 16-bit chunks in Rs1 + * with the top 8-bit Q7 content of 16-bit chunks in Rs2. At the same time, multiply the bottom 8-bit Q7 + * content of 16-bit chunks in Rs1 with the bottom 8-bit Q7 content of 16-bit chunks in Rs2. + * + * The Q14 results are then right-shifted 7-bits and saturated into Q7 values. The Q7 results are then + * written into Rd. When both the two Q7 inputs of a multiplication are 0x80, saturation will happen. + * The result will be saturated to 0x7F and the overflow flag OV will be set. + * + * **Operations**:\n + * ~~~ + * op1t = Rs1.B[x+1]; op2t = Rs2.B[x+1]; // top + * op1b = Rs1.B[x]; op2b = Rs2.B[x]; // bottom + * for ((aop,bop,res) in [(op1t,op2t,rest), (op1b,op2b,resb)]) { + * if (0x80 != aop | 0x80 != bop) { + * res = (aop s* bop) >> 7; + * } else { + * res= 0x7F; + * OV = 1; + * } + * } + * Rd.H[x/2] = concat(rest, resb); + * for RV32, x=0,2,4,6 + * ~~~ + * + * \param [in] a unsigned long long type of value stored in a + * \param [in] b unsigned long long type of value stored in b + * \return value stored in unsigned long long type + */ +__STATIC_FORCEINLINE unsigned long long __RV_DKHM8(unsigned long long a, unsigned long long b) +{ + unsigned long long result; + __ASM volatile("dkhm8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for A.1. DKHM8 ===== */ + +/* ===== Inline Function Start for A.2. DKHM16 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_NUCLEI_CUSTOM + * \brief DKHM16 (64-bit SIMD Signed Saturating Q15 Multiply) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * DKHM16 Rd, Rs1, Rs2 + * # Rd, Rs1, Rs2 are all even/odd pair of registers + * ~~~ + * + * **Purpose**:\n + * Do Q15xQ15 element multiplications simultaneously. The Q30 results are then reduced to + * Q15 numbers again. + * + * **Description**:\n + * For the `DKHM16` instruction, multiply the top 16-bit Q15 content of 32-bit chunks in + * Rs1 with the top 16-bit Q15 content of 32-bit chunks in Rs2. At the same time, multiply the bottom + * 16-bit Q15 content of 32-bit chunks in Rs1 with the bottom 16-bit Q15 content of 32-bit chunks in + * Rs2. + * + * The Q30 results are then right-shifted 15-bits and saturated into Q15 values. The Q15 results are + * then written into Rd. When both the two Q15 inputs of a multiplication are 0x8000, saturation will + * happen. The result will be saturated to 0x7FFF and the overflow flag OV will be set. + * + * **Operations**:\n + * ~~~ + * op1t = Rs1.H[x+1]; op2t = Rs2.H[x+1]; // top + * op1b = Rs1.H[x]; op2b = Rs2.H[x]; // bottom + * for ((aop,bop,res) in [(op1t,op2t,rest), (op1b,op2b,resb)]) { + * if (0x8000 != aop | 0x8000 != bop) { + * res = (aop s* bop) >> 15; + * } else { + * res= 0x7FFF; + * OV = 1; + * } + * } + * Rd.W[x/2] = concat(rest, resb); + * for RV32: x=0, 2 + * ~~~ + * + * \param [in] a unsigned long long type of value stored in a + * \param [in] b unsigned long long type of value stored in b + * \return value stored in unsigned long long type + */ +__STATIC_FORCEINLINE unsigned long long __RV_DKHM16(unsigned long long a, unsigned long long b) +{ + unsigned long long result; + __ASM volatile("dkhm16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for A.2. DKHM16 ===== */ + +/* ===== Inline Function Start for A.3. DKABS8 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_NUCLEI_CUSTOM + * \brief DKABS8 (64-bit SIMD 8-bit Saturating Absolute) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * DKABS8 Rd, Rs1 + * # Rd, Rs1 are all even/odd pair of registers + * ~~~ + * + * **Purpose**:\n + * Get the absolute value of 8-bit signed integer elements simultaneously. + * + * **Description**:\n + * This instruction calculates the absolute value of 8-bit signed integer elements stored + * in Rs1 and writes the element results to Rd. If the input number is 0x80, this instruction generates + * 0x7f as the output and sets the OV bit to 1. + * + * **Operations**:\n + * ~~~ + * src = Rs1.B[x]; + * if (src == 0x80) { + * src = 0x7f; + * OV = 1; + * } else if (src[7] == 1) + * src = -src; + * } + * Rd.B[x] = src; + * for RV32: x=7...0, + * ~~~ + * + * \param [in] a unsigned long long type of value stored in a + * \return value stored in unsigned long long type + */ +__STATIC_FORCEINLINE unsigned long long __RV_DKABS8(unsigned long long a) +{ + unsigned long long result; + __ASM volatile("dkabs8 %0, %1" : "=r"(result) : "r"(a)); + return result; +} +/* ===== Inline Function End for A.3. DKABS8 ===== */ + +/* ===== Inline Function Start for A.4. DKABS16 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_NUCLEI_CUSTOM + * \brief DKABS16 (64-bit SIMD 16-bit Saturating Absolute) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * DKABS16 Rd, Rs1 + * # Rd, Rs1 are all even/odd pair of registers + * ~~~ + * + * **Purpose**:\n + * Get the absolute value of 16-bit signed integer elements simultaneously. + * + * **Description**:\n + * This instruction calculates the absolute value of 16-bit signed integer elements stored + * in Rs1 and writes the element results to Rd. If the input number is 0x8000, this instruction + * generates 0x7fff as the output and sets the OV bit to 1. + * + * **Operations**:\n + * ~~~ + * src = Rs1.H[x]; + * if (src == 0x8000) { + * src = 0x7fff; + * OV = 1; + * } else if (src[15] == 1) + * src = -src; + * } + * Rd.H[x] = src; + * for RV32: x=3...0, + * ~~~ + * + * \param [in] a unsigned long long type of value stored in a + * \return value stored in unsigned long long type + */ +__STATIC_FORCEINLINE unsigned long long __RV_DKABS16(unsigned long long a) +{ + unsigned long long result; + __ASM volatile("dkabs16 %0, %1" : "=r"(result) : "r"(a)); + return result; +} +/* ===== Inline Function End for A.4. DKABS16 ===== */ + +/* ===== Inline Function Start for A.5. DKSLRA8 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_NUCLEI_CUSTOM + * \brief DKSLRA8 (64-bit SIMD 8-bit Shift Left Logical with Saturation or Shift Right Arithmetic) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * DKSLRA8 Rd, Rs1, Rs2 + * # Rd, Rs1 are all even/odd pair of registers + * ~~~ + * + * **Purpose**:\n + * Do 8-bit elements logical left (positive) or arithmetic right (negative) shift operation with + * Q7 saturation for the left shift. + * + * **Description**:\n + * The 8-bit data elements of Rs1 are left-shifted logically or right-shifted arithmetically + * based on the value of Rs2[3:0]. Rs2[3:0] is in the signed range of [-2^3, 2^3-1]. A positive Rs2[3:0] means + * logical left shift and a negative Rs2[3:0] means arithmetic right shift. The shift amount is the + * absolute value of Rs2[3:0]. However, the behavior of `Rs2[3:0]==-2^3 (0x8)` is defined to be + * equivalent to the behavior of `Rs2[3:0]==-(2^3-1) (0x9)`. + * The left-shifted results are saturated to the 8-bit signed integer range of [-2^7, 2^7-1]. + * If any saturation happens, this instruction sets the OV flag. The value of Rs2[31:4] will not affect + * this instruction. + * + * **Operations**:\n + * ~~~ + * if (Rs2[3:0] < 0) { + * sa = -Rs2[3:0]; + * sa = (sa == 8)? 7 : sa; + * Rd.B[x] = SE8(Rs1.B[x][7:sa]); + * } else { + * sa = Rs2[2:0]; + * res[(7+sa):0] = Rs1.B[x] <<(logic) sa; + * if (res > (2^7)-1) { + * res[7:0] = 0x7f; OV = 1; + * } else if (res < -2^7) { + * res[7:0] = 0x80; OV = 1; + * } + * Rd.B[x] = res[7:0]; + * } + * for RV32: x=7...0, + * ~~~ + * + * \param [in] a unsigned long long type of value stored in a + * \param [in] b int type of value stored in b + * \return value stored in unsigned long long type + */ +__STATIC_FORCEINLINE unsigned long long __RV_DKSLRA8(unsigned long long a, int b) +{ + unsigned long long result; + __ASM volatile("dkslra8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for A.5. DKSLRA8 ===== */ + +/* ===== Inline Function Start for A.6. DKSLRA16 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_NUCLEI_CUSTOM + * \brief DKSLRA16 (64-bit SIMD 16-bit Shift Left Logical with Saturation or Shift Right Arithmetic) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * DKSLRA16 Rd, Rs1, Rs2 + * # Rd, Rs1 are all even/odd pair of registers + * ~~~ + * + * **Purpose**:\n + * Do 16-bit elements logical left (positive) or arithmetic right (negative) shift operation with + * Q15 saturation for the left shift. + * + * **Description**:\n + * The 16-bit data elements of Rs1 are left-shifted logically or right-shifted arithmetically + * based on the value of Rs2[4:0]. Rs2[4:0] is in the signed range of [-2^4, 2^4-1]. A positive Rs2[4:0] means + * logical left shift and a negative Rs2[4:0] means arithmetic right shift. The shift amount is the + * absolute value of Rs2[4:0]. However, the behavior of `Rs2[4:0]==-2^4 (0x10)` is defined to be + * equivalent to the behavior of `Rs2[4:0]==-(2^4-1) (0x11)`. + * The left-shifted results are saturated to the 16-bit signed integer range of [-2^15, 2^15-1]. + * After the shift, saturation, or rounding, the final results are written to + * Rd. If any saturation happens, this instruction sets the OV flag. The value of Rs2[31:5] will not affect + * this instruction. + * + * **Operations**:\n + * ~~~ + * if (Rs2[4:0] < 0) { + * sa = -Rs2[4:0]; + * sa = (sa == 16)? 15 : sa; + * Rd.H[x] = SE16(Rs1.H[x][15:sa]); + * } else { + * sa = Rs2[3:0]; + * res[(15+sa):0] = Rs1.H[x] <<(logic) sa; + * if (res > (2^15)-1) { + * res[15:0] = 0x7fff; OV = 1; + * } else if (res < -2^15) { + * res[15:0] = 0x8000; OV = 1; + * } + * d.H[x] = res[15:0]; + * } + * for RV32: x=3...0, + * ~~~ + * + * \param [in] a unsigned long long type of value stored in a + * \param [in] b int type of value stored in b + * \return value stored in unsigned long long type + */ +__STATIC_FORCEINLINE unsigned long long __RV_DKSLRA16(unsigned long long a, int b) +{ + unsigned long long result; + __ASM volatile("dkslra16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for A.6. DKSLRA16 ===== */ + +/* ===== Inline Function Start for A.7. DKADD8 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_NUCLEI_CUSTOM + * \brief DKADD8 (64-bit SIMD 8-bit Signed Saturating Addition) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * DKADD8 Rd, Rs1, Rs2 + * # Rd, Rs1, Rs2 are all even/odd pair of registers + * ~~~ + * + * **Purpose**:\n + * Do 8-bit signed integer element saturating additions simultaneously. + * + * **Description**:\n + * This instruction adds the 8-bit signed integer elements in Rs1 with the 8-bit signed + * integer elements in Rs2. If any of the results are beyond the Q7 number range (-2^7 <= Q7 <= 2^7-1), they + * are saturated to the range and the OV bit is set to 1. The saturated results are written to Rd. + * + * **Operations**:\n + * ~~~ + * res[x] = Rs1.B[x] + Rs2.B[x]; + * if (res[x] > 127) { + * res[x] = 127; + * OV = 1; + * } else if (res[x] < -128) { + * res[x] = -128; + * OV = 1; + * } + * Rd.B[x] = res[x]; + * for RV32: x=7...0, + * ~~~ + * + * \param [in] a unsigned long long type of value stored in a + * \param [in] b unsigned long long type of value stored in b + * \return value stored in unsigned long long type + */ +__STATIC_FORCEINLINE unsigned long long __RV_DKADD8(unsigned long long a, unsigned long long b) +{ + unsigned long long result; + __ASM volatile("dkadd8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for A.7. DKADD8 ===== */ + +/* ===== Inline Function Start for A.8. DKADD16 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_NUCLEI_CUSTOM + * \brief DKADD16 (64-bit SIMD 16-bit Signed Saturating Addition) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * DKADD16 Rd, Rs1, Rs2 + * # Rd, Rs1, Rs2 are all even/odd pair of registers + * ~~~ + * + * **Purpose**:\n + * Do 16-bit signed integer element saturating additions simultaneously. + * + * **Description**:\n + * This instruction adds the 16-bit signed integer elements in Rs1 with the 16-bit signed + * integer elements in Rs2. If any of the results are beyond the Q15 number range (-2^15 <= Q15 <= 2^15-1), + * they are saturated to the range and the OV bit is set to 1. The saturated results are written to Rd. + * + * **Operations**:\n + * ~~~ + * res[x] = Rs1.H[x] + Rs2.H[x]; + * if (res[x] > 32767) { + * res[x] = 32767; + * OV = 1; + * } else if (res[x] < -32768) { + * res[x] = -32768; + * OV = 1; + * } + * Rd.H[x] = res[x]; + * for RV32: x=3...0, + * ~~~ + * + * \param [in] a unsigned long long type of value stored in a + * \param [in] b unsigned long long type of value stored in b + * \return value stored in unsigned long long type + */ +__STATIC_FORCEINLINE unsigned long long __RV_DKADD16(unsigned long long a, unsigned long long b) +{ + unsigned long long result; + __ASM volatile("dkadd16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for A.8. DKADD16 ===== */ + +/* ===== Inline Function Start for A.10. DKSUB8 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_NUCLEI_CUSTOM + * \brief DKSUB8 (64-bit SIMD 8-bit Signed Saturating Subtraction) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * DKSUB8 Rd, Rs1, Rs2 + * # Rd, Rs1, Rs2 are all even/odd pair of registers + * ~~~ + * + * **Purpose**:\n + * Do 8-bit signed elements saturating subtractions simultaneously. + * + * **Description**:\n + * This instruction subtracts the 8-bit signed integer elements in Rs2 from the 8-bit + * signed integer elements in Rs1. If any of the results are beyond the Q7 number range (-2^7 <= Q7 <= 2^7-1), + * they are saturated to the range and the OV bit is set to 1. The saturated results are written to Rd. + * + * **Operations**:\n + * ~~~ + * res[x] = Rs1.B[x] - Rs2.B[x]; + * if (res[x] > (2^7)-1) { + * res[x] = (2^7)-1; + * OV = 1; + * } else if (res[x] < -2^7) { + * res[x] = -2^7; + * OV = 1; + * } + * Rd.B[x] = res[x]; + * for RV32: x=7...0, + * ~~~ + * + * \param [in] a unsigned long long type of value stored in a + * \param [in] b unsigned long long type of value stored in b + * \return value stored in unsigned long long type + */ +__STATIC_FORCEINLINE unsigned long long __RV_DKSUB8(unsigned long long a, unsigned long long b) +{ + unsigned long long result; + __ASM volatile("dksub8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for A.9. DKSUB8 ===== */ + +/* ===== Inline Function Start for A.10. DKSUB16 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_NUCLEI_CUSTOM + * \brief DKSUB16 (64-bit SIMD 16-bit Signed Saturating Subtraction) + * \details + * **Type**: SIMD + * + * **Syntax**:\n + * ~~~ + * DKSUB16 Rd, Rs1, Rs2 + * # Rd, Rs1, Rs2 are all even/odd pair of registers + * ~~~ + * + * **Purpose**:\n + * Do 16-bit signed integer elements saturating subtractions simultaneously. + * + * **Description**:\n + * This instruction subtracts the 16-bit signed integer elements in Rs2 from the 16-bit + * signed integer elements in Rs1. If any of the results are beyond the Q15 number range (-2^15 <= Q15 <= + * 2^15-1), they are saturated to the range and the OV bit is set to 1. The saturated results are written to + * Rd. + * + * **Operations**:\n + * ~~~ + * res[x] = Rs1.H[x] - Rs2.H[x]; + * if (res[x] > (2^15)-1) { + * res[x] = (2^15)-1; + * OV = 1; + * } else if (res[x] < -2^15) { + * res[x] = -2^15; + * OV = 1; + * } + * Rd.H[x] = res[x]; + * for RV32: x=3...0, + * ~~~ + * + * \param [in] a unsigned long long type of value stored in a + * \param [in] b unsigned long long type of value stored in b + * \return value stored in unsigned long long type + */ +__STATIC_FORCEINLINE unsigned long long __RV_DKSUB16(unsigned long long a, unsigned long long b) +{ + unsigned long long result; + __ASM volatile("dksub16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); + return result; +} +/* ===== Inline Function End for A.10. DKSUB16 ===== */ + +/* ===== Inline Function Start for A.11.1. EXPD80 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_NUCLEI_CUSTOM + * \brief EXPD80 (Expand and Copy Byte 0 to 32bit) + * \details + * **Type**: DSP + * + * **Syntax**:\n + * ~~~ + * EXPD80 Rd, Rs1 + * ~~~ + * + * **Purpose**:\n + * Copy 8-bit data from 32-bit chunks into 4 bytes in a register. + * + * **Description**:\n + * Moves Rs1.B[0][7:0] to Rd.[0][7:0], Rd.[1][7:0], Rd.[2][7:0], Rd.[3][7:0] + * + * **Operations**:\n + * ~~~ + * Rd.W[x][31:0] = CONCAT(Rs1.B[0][7:0], Rs1.B[0][7:0], Rs1.B[0][7:0], Rs1.B[0][7:0]); + * for RV32: x=0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_EXPD80(unsigned long a) +{ + unsigned long result; + __ASM volatile("expd80 %0, %1" : "=r"(result) : "r"(a)); + return result; +} +/* ===== Inline Function End for A11.1. EXPD80 ===== */ + +/* ===== Inline Function Start for A.11.2. EXPD81 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_NUCLEI_CUSTOM + * \brief EXPD81 (Expand and Copy Byte 1 to 32bit) + * \details + * **Type**: DSP + * + * **Syntax**:\n + * ~~~ + * EXPD81 Rd, Rs1 + * ~~~ + * + * **Purpose**:\n + * Copy 8-bit data from 32-bit chunks into 4 bytes in a register. + * + * **Description**:\n + * Moves Rs1.B[1][7:0] to Rd.[0][7:0], Rd.[1][7:0], Rd.[2][7:0], Rd.[3][7:0] + * + * **Operations**:\n + * ~~~ + * Rd.W[x][31:0] = CONCAT(Rs1.B[1][7:0], Rs1.B[1][7:0], Rs1.B[1][7:0], Rs1.B[1][7:0]); + * for RV32: x=0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_EXPD81(unsigned long a) +{ + unsigned long result; + __ASM volatile("expd81 %0, %1" : "=r"(result) : "r"(a)); + return result; +} +/* ===== Inline Function End for A11.2. EXPD81 ===== */ + +/* ===== Inline Function Start for A.11.3. EXPD82 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_NUCLEI_CUSTOM + * \brief EXPD82 (Expand and Copy Byte 2 to 32bit) + * \details + * **Type**: DSP + * + * **Syntax**:\n + * ~~~ + * EXPD82 Rd, Rs1 + * ~~~ + * + * **Purpose**:\n + * Copy 8-bit data from 32-bit chunks into 4 bytes in a register. + * + * **Description**:\n + * Moves Rs1.B[2][7:0] to Rd.[0][7:0], Rd.[1][7:0], Rd.[2][7:0], Rd.[3][7:0] + * + * **Operations**:\n + * ~~~ + * Rd.W[x][31:0] = CONCAT(Rs1.B[2][7:0], Rs1.B[2][7:0], Rs1.B[2][7:0], Rs1.B[2][7:0]); + * for RV32: x=0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_EXPD82(unsigned long a) +{ + unsigned long result; + __ASM volatile("expd82 %0, %1" : "=r"(result) : "r"(a)); + return result; +} +/* ===== Inline Function End for A11.3. EXPD82 ===== */ + +/* ===== Inline Function Start for A.11.4. EXPD83 ===== */ +/** + * \ingroup NMSIS_Core_DSP_Intrinsic_NUCLEI_CUSTOM + * \brief EXPD83 (Expand and Copy Byte 3 to 32bit) + * \details + * **Type**: DSP + * + * **Syntax**:\n + * ~~~ + * EXPD83 Rd, Rs1 + * ~~~ + * + * **Purpose**:\n + * Copy 8-bit data from 32-bit chunks into 4 bytes in a register. + * + * **Description**:\n + * Moves Rs1.B[3][7:0] to Rd.[0][7:0], Rd.[1][7:0], Rd.[2][7:0], Rd.[3][7:0] + * + * **Operations**:\n + * ~~~ + * Rd.W[x][31:0] = CONCAT(Rs1.B[3][7:0], Rs1.B[3][7:0], Rs1.B[3][7:0], Rs1.B[3][7:0]); + * for RV32: x=0 + * ~~~ + * + * \param [in] a unsigned long type of value stored in a + * \return value stored in unsigned long type + */ +__STATIC_FORCEINLINE unsigned long __RV_EXPD83(unsigned long a) +{ + unsigned long result; + __ASM volatile("expd83 %0, %1" : "=r"(result) : "r"(a)); + return result; +} +/* ===== Inline Function End for A11.4. EXPD83 ===== */ +#endif /* __RISCV_XLEN == 32 */ + +#if defined(__RISCV_FEATURE_DSP) && (__RISCV_FEATURE_DSP == 1) +/* XXXXX ARM Compatiable SIMD API XXXXX */ +/** \brief Q setting quad 8-bit saturating addition. */ +#define __QADD8(x, y) __RV_KADD8(x, y) +/** \brief Q setting quad 8-bit saturating subtract. */ +#define __QSUB8(x, y) __RV_KSUB8((x), (y)) +/** \brief Q setting dual 16-bit saturating addition. */ +#define __QADD16(x, y) __RV_KADD16((x), (y)) +/** \brief Dual 16-bit signed addition with halved results. */ +#define __SHADD16(x, y) __RV_RADD16((x), (y)) +/** \brief Q setting dual 16-bit saturating subtract. */ +#define __QSUB16(x, y) __RV_KSUB16((x), (y)) +/** \brief Dual 16-bit signed subtraction with halved results. */ +#define __SHSUB16(x, y) __RV_RSUB16((x), (y)) +/** \brief Q setting dual 16-bit add and subtract with exchange. */ +#define __QASX(x, y) __RV_KCRAS16((x), (y)) +/** \brief Dual 16-bit signed addition and subtraction with halved results.*/ +#define __SHASX(x, y) __RV_RCRAS16((x), (y)) +/** \brief Q setting dual 16-bit subtract and add with exchange. */ +#define __QSAX(x, y) __RV_KCRSA16((x), (y)) +/** \brief Dual 16-bit signed subtraction and addition with halved results.*/ +#define __SHSAX(x, y) __RV_RCRSA16((x), (y)) +/** \brief Dual 16-bit signed multiply with exchange returning difference. */ +#define __SMUSDX(x, y) __RV_SMXDS((y), (x)) +/** \brief Q setting sum of dual 16-bit signed multiply with exchange. */ +__STATIC_FORCEINLINE int32_t __SMUADX (int32_t op1, int32_t op2) +{ + return (int32_t)__RV_KMXDA(op1, op2); +} +/** \brief Q setting saturating add. */ +#define __QADD(x, y) __RV_KADDW((x), (y)) +/** \brief Q setting saturating subtract. */ +#define __QSUB(x, y) __RV_KSUBW((x), (y)) +/** \brief Q setting dual 16-bit signed multiply with single 32-bit accumulator. */ +__STATIC_FORCEINLINE int32_t __SMLAD(int32_t op1, int32_t op2, int32_t op3) +{ + return (int32_t)__RV_KMADA(op3, op1, op2); +} +/** \brief Q setting pre-exchanged dual 16-bit signed multiply with single 32-bit accumulator. */ +__STATIC_FORCEINLINE int32_t __SMLADX(int32_t op1, int32_t op2, int32_t op3) +{ + return (int32_t)__RV_KMAXDA(op3, op1, op2); +} +/** \brief Q setting dual 16-bit signed multiply with exchange subtract with 32-bit accumulate. */ +__STATIC_FORCEINLINE int32_t __SMLSDX(int32_t op1, int32_t op2, int32_t op3) +{ + return (op3 - (int32_t)__RV_SMXDS(op1, op2)); +} +/** \brief Dual 16-bit signed multiply with single 64-bit accumulator. */ +__STATIC_FORCEINLINE int64_t __SMLALD(int32_t op1, int32_t op2, int64_t acc) +{ + return (int64_t)__RV_SMALDA(acc, op1, op2); +} +/** \brief Dual 16-bit signed multiply with exchange with single 64-bit accumulator. */ +__STATIC_FORCEINLINE int64_t __SMLALDX(int32_t op1, int32_t op2, int64_t acc) +{ + return (int64_t)__RV_SMALXDA(acc, op1, op2); +} +/** \brief Q setting sum of dual 16-bit signed multiply. */ +__STATIC_FORCEINLINE int32_t __SMUAD(int32_t op1, int32_t op2) +{ + return (int32_t)__RV_KMDA(op1, op2); +} +/** \brief Dual 16-bit signed multiply returning difference. */ +__STATIC_FORCEINLINE int32_t __SMUSD(int32_t op1, int32_t op2) +{ + return (int32_t)__RV_SMDRS(op1, op2); +} +/** \brief Dual extract 8-bits and sign extend each to 16-bits. */ +#define __SXTB16(x) __RV_SUNPKD820(x) +/** \brief Dual extracted 8-bit to 16-bit signed addition. TODO Need test */ +__STATIC_FORCEINLINE int32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + return __RV_ADD16(op1, __RV_SUNPKD820(op2)); +} +#define __SXTAB16_RORn(ARG1, ARG2, ROTATE) __SXTAB16(ARG1, __ROR(ARG2, ROTATE)) + +/** \brief 32-bit signed multiply with 32-bit truncated accumulator. */ +__STATIC_FORCEINLINE int32_t __SMMLA(int32_t op1, int32_t op2, int32_t op3) +{ + int32_t mul; + mul = (int32_t)__RV_SMMUL(op1, op2); + return (op3 + mul); +} +#define __DKHM8 __RV_DKHM8 +#define __DKHM16 __RV_DKHM16 +#define __DKSUB16 __RV_DKSUB16 +#define __SMAQA __RV_SMAQA +#define __MULSR64 __RV_MULSR64 +#define __DQADD8 __RV_DKADD8 +#define __DQSUB8 __RV_DKSUB8 +#define __DKADD16 __RV_DKADD16 +#define __PKBB16 __RV_PKBB16 +#define __DKSLRA16 __RV_DKSLRA16 +#define __DKSLRA8 __RV_DKSLRA8 +#define __KABSW __RV_KABSW +#define __DKABS8 __RV_DKABS8 +#define __DKABS16 __RV_DKABS16 +#define __SMALDA __RV_SMALDA +#define __SMSLDA __RV_SMSLDA +#define __SMALBB __RV_SMALBB +#define __SUB64 __RV_SUB64 +#define __ADD64 __RV_ADD64 +#define __SMBB16 __RV_SMBB16 +#define __SMBT16 __RV_SMBT16 +#define __SMTT16 __RV_SMTT16 +#define __EXPD80 __RV_EXPD80 +#define __SMAX8 __RV_SMAX8 +#define __SMAX16 __RV_SMAX16 +#define __PKTT16 __RV_PKTT16 +#define __KADD16 __RV_KADD16 +#define __SADD16 __RV_ADD16 +#define __SSUB8 __RV_KSUB8 +#define __SADD8 __RV_KADD8 +#define __USAT16 __RV_UCLIP16 + +/** \brief Halfword packing instruction. Combines bits[15:0] of val1 with bits[31:16] of val2 levitated with the val3. */ +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) +/** \brief Halfword packing instruction. Combines bits[31:16] of val1 with bits[15:0] of val2 right-shifted with the val3. */ +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +/** first rotate then extract. This is more suitable for arm compiler for it can rotate and extract in one command*/ +#define __SXTB16_RORn(ARG1, ARG2) __RV_SUNPKD820(__ROR(ARG1, ARG2)) + +#endif /* (__RISCV_FEATURE_DSP == 1) */ + +#endif /* defined(__DSP_PRESENT) && (__DSP_PRESENT == 1) */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_FEATURE_DSP__ */ diff --git a/components/nmsis/core/inc/core_feature_eclic.h b/components/nmsis/core/inc/core_feature_eclic.h new file mode 100644 index 00000000..cac14ef0 --- /dev/null +++ b/components/nmsis/core/inc/core_feature_eclic.h @@ -0,0 +1,897 @@ +/* + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef __CORE_FEATURE_ECLIC__ +#define __CORE_FEATURE_ECLIC__ +/*! + * @file core_feature_eclic.h + * @brief ECLIC feature API header file for Nuclei N/NX Core + */ +/* + * ECLIC Feature Configuration Macro: + * 1. __ECLIC_PRESENT: Define whether Enhanced Core Local Interrupt Controller (ECLIC) Unit is present or not + * * 0: Not present + * * 1: Present + * 2. __ECLIC_BASEADDR: Base address of the ECLIC unit. + * 3. ECLIC_GetInfoCtlbits(): Define the number of hardware bits are actually implemented in the clicintctl registers. + * Valid number is 1 - 8. + * 4. __ECLIC_INTNUM : Define the external interrupt number of ECLIC Unit + * + */ +#ifdef __cplusplus + extern "C" { +#endif + +#if defined(__ECLIC_PRESENT) && (__ECLIC_PRESENT == 1) +/** + * \defgroup NMSIS_Core_ECLIC_Registers Register Define and Type Definitions Of ECLIC + * \ingroup NMSIS_Core_Registers + * \brief Type definitions and defines for eclic registers. + * + * @{ + */ + +/** + * \brief Union type to access CLICFG configure register. + */ +typedef union +{ + struct { + uint8_t _reserved0:1; /*!< bit: 0 Overflow condition code flag */ + uint8_t nlbits:4; /*!< bit: 29 Carry condition code flag */ + uint8_t _reserved1:2; /*!< bit: 30 Zero condition code flag */ + uint8_t _reserved2:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint8_t w; /*!< Type used for byte access */ +} CLICCFG_Type; + +/** + * \brief Union type to access CLICINFO information register. + */ +typedef union { + struct { + uint32_t numint:13; /*!< bit: 0..12 number of maximum interrupt inputs supported */ + uint32_t version:8; /*!< bit: 13..20 20:17 for architecture version,16:13 for implementation version */ + uint32_t intctlbits:4; /*!< bit: 21..24 specifies how many hardware bits are actually implemented in the clicintctl registers */ + uint32_t _reserved0:7; /*!< bit: 25..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CLICINFO_Type; + +/** + * \brief Access to the structure of a vector interrupt controller. + */ +typedef struct { + __IOM uint8_t INTIP; /*!< Offset: 0x000 (R/W) Interrupt set pending register */ + __IOM uint8_t INTIE; /*!< Offset: 0x001 (R/W) Interrupt set enable register */ + __IOM uint8_t INTATTR; /*!< Offset: 0x002 (R/W) Interrupt set attributes register */ + __IOM uint8_t INTCTRL; /*!< Offset: 0x003 (R/W) Interrupt configure register */ +} CLIC_CTRL_Type; + +typedef struct { + __IOM uint8_t CFG; /*!< Offset: 0x000 (R/W) CLIC configuration register */ + uint8_t RESERVED0[3]; + __IM uint32_t INFO; /*!< Offset: 0x004 (R/ ) CLIC information register */ + uint8_t RESERVED1[3]; + __IOM uint8_t MTH; /*!< Offset: 0x00B (R/W) CLIC machine mode threshold register */ + uint32_t RESERVED2[0x3FD]; + CLIC_CTRL_Type CTRL[4096]; /*!< Offset: 0x1000 (R/W) CLIC register structure for INTIP, INTIE, INTATTR, INTCTL */ +} CLIC_Type; + +#define CLIC_CLICCFG_NLBIT_Pos 1U /*!< CLIC CLICCFG: NLBIT Position */ +#define CLIC_CLICCFG_NLBIT_Msk (0xFUL << CLIC_CLICCFG_NLBIT_Pos) /*!< CLIC CLICCFG: NLBIT Mask */ + +#define CLIC_CLICINFO_CTLBIT_Pos 21U /*!< CLIC INTINFO: __ECLIC_GetInfoCtlbits() Position */ +#define CLIC_CLICINFO_CTLBIT_Msk (0xFUL << CLIC_CLICINFO_CTLBIT_Pos) /*!< CLIC INTINFO: __ECLIC_GetInfoCtlbits() Mask */ + +#define CLIC_CLICINFO_VER_Pos 13U /*!< CLIC CLICINFO: VERSION Position */ +#define CLIC_CLICINFO_VER_Msk (0xFFUL << CLIC_CLICCFG_NLBIT_Pos) /*!< CLIC CLICINFO: VERSION Mask */ + +#define CLIC_CLICINFO_NUM_Pos 0U /*!< CLIC CLICINFO: NUM Position */ +#define CLIC_CLICINFO_NUM_Msk (0xFFFUL << CLIC_CLICINFO_NUM_Pos) /*!< CLIC CLICINFO: NUM Mask */ + +#define CLIC_INTIP_IP_Pos 0U /*!< CLIC INTIP: IP Position */ +#define CLIC_INTIP_IP_Msk (0x1UL << CLIC_INTIP_IP_Pos) /*!< CLIC INTIP: IP Mask */ + +#define CLIC_INTIE_IE_Pos 0U /*!< CLIC INTIE: IE Position */ +#define CLIC_INTIE_IE_Msk (0x1UL << CLIC_INTIE_IE_Pos) /*!< CLIC INTIE: IE Mask */ + +#define CLIC_INTATTR_TRIG_Pos 1U /*!< CLIC INTATTR: TRIG Position */ +#define CLIC_INTATTR_TRIG_Msk (0x3UL << CLIC_INTATTR_TRIG_Pos) /*!< CLIC INTATTR: TRIG Mask */ + +#define CLIC_INTATTR_SHV_Pos 0U /*!< CLIC INTATTR: SHV Position */ +#define CLIC_INTATTR_SHV_Msk (0x1UL << CLIC_INTATTR_SHV_Pos) /*!< CLIC INTATTR: SHV Mask */ + +#define ECLIC_MAX_NLBITS 8U /*!< Max nlbit of the CLICINTCTLBITS */ +#define ECLIC_MODE_MTVEC_Msk 3U /*!< ECLIC Mode mask for MTVT CSR Register */ + +#define ECLIC_NON_VECTOR_INTERRUPT 0x0 /*!< Non-Vector Interrupt Mode of ECLIC */ +#define ECLIC_VECTOR_INTERRUPT 0x1 /*!< Vector Interrupt Mode of ECLIC */ + +/**\brief ECLIC Trigger Enum for different Trigger Type */ +typedef enum ECLIC_TRIGGER { + ECLIC_LEVEL_TRIGGER = 0x0, /*!< Level Triggerred, trig[0] = 0 */ + ECLIC_POSTIVE_EDGE_TRIGGER = 0x1, /*!< Postive/Rising Edge Triggered, trig[0] = 1, trig[1] = 0 */ + ECLIC_NEGTIVE_EDGE_TRIGGER = 0x3, /*!< Negtive/Falling Edge Triggered, trig[0] = 1, trig[1] = 1 */ + ECLIC_MAX_TRIGGER = 0x3 /*!< MAX Supported Trigger Mode */ +} ECLIC_TRIGGER_Type; + +#ifndef __ECLIC_BASEADDR +/* Base address of ECLIC(__ECLIC_BASEADDR) should be defined in */ +#error "__ECLIC_BASEADDR is not defined, please check!" +#endif + +#ifndef __ECLIC_INTCTLBITS +/* Define __ECLIC_INTCTLBITS to get via ECLIC->INFO if not defined */ +#define __ECLIC_INTCTLBITS (__ECLIC_GetInfoCtlbits()) +#endif + +/* ECLIC Memory mapping of Device */ +#define ECLIC_BASE __ECLIC_BASEADDR /*!< ECLIC Base Address */ +#define ECLIC ((CLIC_Type *) ECLIC_BASE) /*!< CLIC configuration struct */ + +/** @} */ /* end of group NMSIS_Core_ECLIC_Registers */ + +/* ########################## ECLIC functions #################################### */ +/** + * \defgroup NMSIS_Core_IntExc Interrupts and Exceptions + * \brief Functions that manage interrupts and exceptions via the ECLIC. + * + * @{ + */ + +/** + * \brief Definition of IRQn numbers + * \details + * The core interrupt enumeration names for IRQn values are defined in the file .h. + * - Interrupt ID(IRQn) from 0 to 18 are reserved for core internal interrupts. + * - Interrupt ID(IRQn) start from 19 represent device-specific external interrupts. + * - The first device-specific interrupt has the IRQn value 19. + * + * The table below describes the core interrupt names and their availability in various Nuclei Cores. + */ +/* The following enum IRQn definition in this file + * is only used for doxygen documentation generation, + * The .h is the real file to define it by vendor + */ +#if defined(__ONLY_FOR_DOXYGEN_DOCUMENT_GENERATION__) +typedef enum IRQn { + /* ========= Nuclei N/NX Core Specific Interrupt Numbers =========== */ + /* Core Internal Interrupt IRQn definitions */ + Reserved0_IRQn = 0, /*!< Internal reserved */ + Reserved1_IRQn = 1, /*!< Internal reserved */ + Reserved2_IRQn = 2, /*!< Internal reserved */ + SysTimerSW_IRQn = 3, /*!< System Timer SW interrupt */ + Reserved3_IRQn = 4, /*!< Internal reserved */ + Reserved4_IRQn = 5, /*!< Internal reserved */ + Reserved5_IRQn = 6, /*!< Internal reserved */ + SysTimer_IRQn = 7, /*!< System Timer Interrupt */ + Reserved6_IRQn = 8, /*!< Internal reserved */ + Reserved7_IRQn = 9, /*!< Internal reserved */ + Reserved8_IRQn = 10, /*!< Internal reserved */ + Reserved9_IRQn = 11, /*!< Internal reserved */ + Reserved10_IRQn = 12, /*!< Internal reserved */ + Reserved11_IRQn = 13, /*!< Internal reserved */ + Reserved12_IRQn = 14, /*!< Internal reserved */ + Reserved13_IRQn = 15, /*!< Internal reserved */ + Reserved14_IRQn = 16, /*!< Internal reserved */ + Reserved15_IRQn = 17, /*!< Internal reserved */ + Reserved16_IRQn = 18, /*!< Internal reserved */ + + /* ========= Device Specific Interrupt Numbers =================== */ + /* ToDo: add here your device specific external interrupt numbers. + * 19~max(NUM_INTERRUPT, 1023) is reserved number for user. + * Maxmum interrupt supported could get from clicinfo.NUM_INTERRUPT. + * According the interrupt handlers defined in startup_Device.S + * eg.: Interrupt for Timer#1 eclic_tim1_handler -> TIM1_IRQn */ + FirstDeviceSpecificInterrupt_IRQn = 19, /*!< First Device Specific Interrupt */ + SOC_INT_MAX, /*!< Number of total interrupts */ +} IRQn_Type; +#endif /* __ONLY_FOR_DOXYGEN_DOCUMENT_GENERATION__ */ + +#ifdef NMSIS_ECLIC_VIRTUAL + #ifndef NMSIS_ECLIC_VIRTUAL_HEADER_FILE + #define NMSIS_ECLIC_VIRTUAL_HEADER_FILE "nmsis_eclic_virtual.h" + #endif + #include NMSIS_ECLIC_VIRTUAL_HEADER_FILE +#else + #define ECLIC_SetCfgNlbits __ECLIC_SetCfgNlbits + #define ECLIC_GetCfgNlbits __ECLIC_GetCfgNlbits + #define ECLIC_GetInfoVer __ECLIC_GetInfoVer + #define ECLIC_GetInfoCtlbits __ECLIC_GetInfoCtlbits + #define ECLIC_GetInfoNum __ECLIC_GetInfoNum + #define ECLIC_SetMth __ECLIC_SetMth + #define ECLIC_GetMth __ECLIC_GetMth + #define ECLIC_EnableIRQ __ECLIC_EnableIRQ + #define ECLIC_GetEnableIRQ __ECLIC_GetEnableIRQ + #define ECLIC_DisableIRQ __ECLIC_DisableIRQ + #define ECLIC_SetPendingIRQ __ECLIC_SetPendingIRQ + #define ECLIC_GetPendingIRQ __ECLIC_GetPendingIRQ + #define ECLIC_ClearPendingIRQ __ECLIC_ClearPendingIRQ + #define ECLIC_SetTrigIRQ __ECLIC_SetTrigIRQ + #define ECLIC_GetTrigIRQ __ECLIC_GetTrigIRQ + #define ECLIC_SetShvIRQ __ECLIC_SetShvIRQ + #define ECLIC_GetShvIRQ __ECLIC_GetShvIRQ + #define ECLIC_SetCtrlIRQ __ECLIC_SetCtrlIRQ + #define ECLIC_GetCtrlIRQ __ECLIC_GetCtrlIRQ + #define ECLIC_SetLevelIRQ __ECLIC_SetLevelIRQ + #define ECLIC_GetLevelIRQ __ECLIC_GetLevelIRQ + #define ECLIC_SetPriorityIRQ __ECLIC_SetPriorityIRQ + #define ECLIC_GetPriorityIRQ __ECLIC_GetPriorityIRQ + +#endif /* NMSIS_ECLIC_VIRTUAL */ + +#ifdef NMSIS_VECTAB_VIRTUAL + #ifndef NMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define NMSIS_VECTAB_VIRTUAL_HEADER_FILE "nmsis_vectab_virtual.h" + #endif + #include NMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define ECLIC_SetVector __ECLIC_SetVector + #define ECLIC_GetVector __ECLIC_GetVector +#endif /* (NMSIS_VECTAB_VIRTUAL) */ + +/** + * \brief Set nlbits value + * \details + * This function set the nlbits value of CLICCFG register. + * \param [in] nlbits nlbits value + * \remarks + * - nlbits is used to set the width of level in the CLICINTCTL[i]. + * \sa + * - \ref ECLIC_GetCfgNlbits + */ +__STATIC_FORCEINLINE void __ECLIC_SetCfgNlbits(uint32_t nlbits) +{ + ECLIC->CFG &= ~CLIC_CLICCFG_NLBIT_Msk; + ECLIC->CFG |= (uint8_t)((nlbits <CFG & CLIC_CLICCFG_NLBIT_Msk) >> CLIC_CLICCFG_NLBIT_Pos)); +} + +/** + * \brief Get the ECLIC version number + * \details + * This function gets the hardware version information from CLICINFO register. + * \return hardware version number in CLICINFO register. + * \remarks + * - This function gets harware version information from CLICINFO register. + * - Bit 20:17 for architecture version, bit 16:13 for implementation version. + * \sa + * - \ref ECLIC_GetInfoNum +*/ +__STATIC_FORCEINLINE uint32_t __ECLIC_GetInfoVer(void) +{ + return ((uint32_t)((ECLIC->INFO & CLIC_CLICINFO_VER_Msk) >> CLIC_CLICINFO_VER_Pos)); +} + +/** + * \brief Get CLICINTCTLBITS + * \details + * This function gets CLICINTCTLBITS from CLICINFO register. + * \return CLICINTCTLBITS from CLICINFO register. + * \remarks + * - In the CLICINTCTL[i] registers, with 2 <= CLICINTCTLBITS <= 8. + * - The implemented bits are kept left-justified in the most-significant bits of each 8-bit + * CLICINTCTL[I] register, with the lower unimplemented bits treated as hardwired to 1. + * \sa + * - \ref ECLIC_GetInfoNum + */ +__STATIC_FORCEINLINE uint32_t __ECLIC_GetInfoCtlbits(void) +{ + return ((uint32_t)((ECLIC->INFO & CLIC_CLICINFO_CTLBIT_Msk) >> CLIC_CLICINFO_CTLBIT_Pos)); +} + +/** + * \brief Get number of maximum interrupt inputs supported + * \details + * This function gets number of maximum interrupt inputs supported from CLICINFO register. + * \return number of maximum interrupt inputs supported from CLICINFO register. + * \remarks + * - This function gets number of maximum interrupt inputs supported from CLICINFO register. + * - The num_interrupt field specifies the actual number of maximum interrupt inputs supported in this implementation. + * \sa + * - \ref ECLIC_GetInfoCtlbits + */ +__STATIC_FORCEINLINE uint32_t __ECLIC_GetInfoNum(void) +{ + return ((uint32_t)((ECLIC->INFO & CLIC_CLICINFO_NUM_Msk) >> CLIC_CLICINFO_NUM_Pos)); +} + +/** + * \brief Set Machine Mode Interrupt Level Threshold + * \details + * This function sets machine mode interrupt level threshold. + * \param [in] mth Interrupt Level Threshold. + * \sa + * - \ref ECLIC_GetMth + */ +__STATIC_FORCEINLINE void __ECLIC_SetMth(uint8_t mth) +{ + ECLIC->MTH = mth; +} + +/** + * \brief Get Machine Mode Interrupt Level Threshold + * \details + * This function gets machine mode interrupt level threshold. + * \return Interrupt Level Threshold. + * \sa + * - \ref ECLIC_SetMth + */ +__STATIC_FORCEINLINE uint8_t __ECLIC_GetMth(void) +{ + return (ECLIC->MTH); +} + + +/** + * \brief Enable a specific interrupt + * \details + * This function enables the specific interrupt \em IRQn. + * \param [in] IRQn Interrupt number + * \remarks + * - IRQn must not be negative. + * \sa + * - \ref ECLIC_DisableIRQ + */ +__STATIC_FORCEINLINE void __ECLIC_EnableIRQ(IRQn_Type IRQn) +{ + ECLIC->CTRL[IRQn].INTIE |= CLIC_INTIE_IE_Msk; +} + +/** + * \brief Get a specific interrupt enable status + * \details + * This function returns the interrupt enable status for the specific interrupt \em IRQn. + * \param [in] IRQn Interrupt number + * \returns + * - 0 Interrupt is not enabled + * - 1 Interrupt is pending + * \remarks + * - IRQn must not be negative. + * \sa + * - \ref ECLIC_EnableIRQ + * - \ref ECLIC_DisableIRQ + */ +__STATIC_FORCEINLINE uint32_t __ECLIC_GetEnableIRQ(IRQn_Type IRQn) +{ + return((uint32_t) (ECLIC->CTRL[IRQn].INTIE) & CLIC_INTIE_IE_Msk); +} + +/** + * \brief Disable a specific interrupt + * \details + * This function disables the specific interrupt \em IRQn. + * \param [in] IRQn Number of the external interrupt to disable + * \remarks + * - IRQn must not be negative. + * \sa + * - \ref ECLIC_EnableIRQ + */ +__STATIC_FORCEINLINE void __ECLIC_DisableIRQ(IRQn_Type IRQn) +{ + ECLIC->CTRL[IRQn].INTIE &= ~CLIC_INTIE_IE_Msk; +} + +/** + * \brief Get the pending specific interrupt + * \details + * This function returns the pending status of the specific interrupt \em IRQn. + * \param [in] IRQn Interrupt number + * \returns + * - 0 Interrupt is not pending + * - 1 Interrupt is pending + * \remarks + * - IRQn must not be negative. + * \sa + * - \ref ECLIC_SetPendingIRQ + * - \ref ECLIC_ClearPendingIRQ + */ +__STATIC_FORCEINLINE int32_t __ECLIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(ECLIC->CTRL[IRQn].INTIP) & CLIC_INTIP_IP_Msk); +} + +/** + * \brief Set a specific interrupt to pending + * \details + * This function sets the pending bit for the specific interrupt \em IRQn. + * \param [in] IRQn Interrupt number + * \remarks + * - IRQn must not be negative. + * \sa + * - \ref ECLIC_GetPendingIRQ + * - \ref ECLIC_ClearPendingIRQ + */ +__STATIC_FORCEINLINE void __ECLIC_SetPendingIRQ(IRQn_Type IRQn) +{ + ECLIC->CTRL[IRQn].INTIP |= CLIC_INTIP_IP_Msk; +} + +/** + * \brief Clear a specific interrupt from pending + * \details + * This function removes the pending state of the specific interrupt \em IRQn. + * \em IRQn cannot be a negative number. + * \param [in] IRQn Interrupt number + * \remarks + * - IRQn must not be negative. + * \sa + * - \ref ECLIC_SetPendingIRQ + * - \ref ECLIC_GetPendingIRQ + */ +__STATIC_FORCEINLINE void __ECLIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + ECLIC->CTRL[IRQn].INTIP &= ~ CLIC_INTIP_IP_Msk; +} + +/** + * \brief Set trigger mode and polarity for a specific interrupt + * \details + * This function set trigger mode and polarity of the specific interrupt \em IRQn. + * \param [in] IRQn Interrupt number + * \param [in] trig + * - 00 level trigger, \ref ECLIC_LEVEL_TRIGGER + * - 01 positive edge trigger, \ref ECLIC_POSTIVE_EDGE_TRIGGER + * - 02 level trigger, \ref ECLIC_LEVEL_TRIGGER + * - 03 negative edge trigger, \ref ECLIC_NEGTIVE_EDGE_TRIGGER + * \remarks + * - IRQn must not be negative. + * + * \sa + * - \ref ECLIC_GetTrigIRQ + */ +__STATIC_FORCEINLINE void __ECLIC_SetTrigIRQ(IRQn_Type IRQn, uint32_t trig) +{ + ECLIC->CTRL[IRQn].INTATTR &= ~CLIC_INTATTR_TRIG_Msk; + ECLIC->CTRL[IRQn].INTATTR |= (uint8_t)(trig<CTRL[IRQn].INTATTR) & CLIC_INTATTR_TRIG_Msk)>>CLIC_INTATTR_TRIG_Pos)); +} + +/** + * \brief Set interrupt working mode for a specific interrupt + * \details + * This function set selective hardware vector or non-vector working mode of the specific interrupt \em IRQn. + * \param [in] IRQn Interrupt number + * \param [in] shv + * - 0 non-vector mode, \ref ECLIC_NON_VECTOR_INTERRUPT + * - 1 vector mode, \ref ECLIC_VECTOR_INTERRUPT + * \remarks + * - IRQn must not be negative. + * \sa + * - \ref ECLIC_GetShvIRQ + */ +__STATIC_FORCEINLINE void __ECLIC_SetShvIRQ(IRQn_Type IRQn, uint32_t shv) +{ + ECLIC->CTRL[IRQn].INTATTR &= ~CLIC_INTATTR_SHV_Msk; + ECLIC->CTRL[IRQn].INTATTR |= (uint8_t)(shv<CTRL[IRQn].INTATTR) & CLIC_INTATTR_SHV_Msk)>>CLIC_INTATTR_SHV_Pos)); +} + +/** + * \brief Modify ECLIC Interrupt Input Control Register for a specific interrupt + * \details + * This function modify ECLIC Interrupt Input Control(CLICINTCTL[i]) register of the specific interrupt \em IRQn. + * \param [in] IRQn Interrupt number + * \param [in] intctrl Set value for CLICINTCTL[i] register + * \remarks + * - IRQn must not be negative. + * \sa + * - \ref ECLIC_GetCtrlIRQ + */ +__STATIC_FORCEINLINE void __ECLIC_SetCtrlIRQ(IRQn_Type IRQn, uint8_t intctrl) +{ + ECLIC->CTRL[IRQn].INTCTRL = intctrl; +} + +/** + * \brief Get ECLIC Interrupt Input Control Register value for a specific interrupt + * \details + * This function modify ECLIC Interrupt Input Control register of the specific interrupt \em IRQn. + * \param [in] IRQn Interrupt number + * \return value of ECLIC Interrupt Input Control register + * \remarks + * - IRQn must not be negative. + * \sa + * - \ref ECLIC_SetCtrlIRQ + */ +__STATIC_FORCEINLINE uint8_t __ECLIC_GetCtrlIRQ(IRQn_Type IRQn) +{ + return (ECLIC->CTRL[IRQn].INTCTRL); +} + +/** + * \brief Set ECLIC Interrupt level of a specific interrupt + * \details + * This function set interrupt level of the specific interrupt \em IRQn. + * \param [in] IRQn Interrupt number + * \param [in] lvl_abs Interrupt level + * \remarks + * - IRQn must not be negative. + * - If lvl_abs to be set is larger than the max level allowed, it will be force to be max level. + * - When you set level value you need use clciinfo.nlbits to get the width of level. + * Then we could know the maximum of level. CLICINTCTLBITS is how many total bits are + * present in the CLICINTCTL register. + * \sa + * - \ref ECLIC_GetLevelIRQ + */ +__STATIC_FORCEINLINE void __ECLIC_SetLevelIRQ(IRQn_Type IRQn, uint8_t lvl_abs) +{ + uint8_t nlbits = __ECLIC_GetCfgNlbits(); + uint8_t intctlbits = (uint8_t)__ECLIC_INTCTLBITS; + + if (nlbits == 0) { + return; + } + + if (nlbits > intctlbits) { + nlbits = intctlbits; + } + uint8_t maxlvl = ((1 << nlbits) - 1); + if (lvl_abs > maxlvl) { + lvl_abs = maxlvl; + } + uint8_t lvl = lvl_abs << (ECLIC_MAX_NLBITS - nlbits); + uint8_t cur_ctrl = __ECLIC_GetCtrlIRQ(IRQn); + cur_ctrl = cur_ctrl << nlbits; + cur_ctrl = cur_ctrl >> nlbits; + __ECLIC_SetCtrlIRQ(IRQn, (cur_ctrl | lvl)); +} + +/** + * \brief Get ECLIC Interrupt level of a specific interrupt + * \details + * This function get interrupt level of the specific interrupt \em IRQn. + * \param [in] IRQn Interrupt number + * \return Interrupt level + * \remarks + * - IRQn must not be negative. + * \sa + * - \ref ECLIC_SetLevelIRQ + */ +__STATIC_FORCEINLINE uint8_t __ECLIC_GetLevelIRQ(IRQn_Type IRQn) +{ + uint8_t nlbits = __ECLIC_GetCfgNlbits(); + uint8_t intctlbits = (uint8_t)__ECLIC_INTCTLBITS; + + if (nlbits == 0) { + return 0; + } + + if (nlbits > intctlbits) { + nlbits = intctlbits; + } + uint8_t intctrl = __ECLIC_GetCtrlIRQ(IRQn); + uint8_t lvl_abs = intctrl >> (ECLIC_MAX_NLBITS - nlbits); + return lvl_abs; +} + +/** + * \brief Get ECLIC Interrupt priority of a specific interrupt + * \details + * This function get interrupt priority of the specific interrupt \em IRQn. + * \param [in] IRQn Interrupt number + * \param [in] pri Interrupt priority + * \remarks + * - IRQn must not be negative. + * - If pri to be set is larger than the max priority allowed, it will be force to be max priority. + * - Priority width is CLICINTCTLBITS minus clciinfo.nlbits if clciinfo.nlbits + * is less than CLICINTCTLBITS. Otherwise priority width is 0. + * \sa + * - \ref ECLIC_GetPriorityIRQ + */ +__STATIC_FORCEINLINE void __ECLIC_SetPriorityIRQ(IRQn_Type IRQn, uint8_t pri) +{ + uint8_t nlbits = __ECLIC_GetCfgNlbits(); + uint8_t intctlbits = (uint8_t)__ECLIC_INTCTLBITS; + if (nlbits < intctlbits) { + uint8_t maxpri = ((1 << (intctlbits - nlbits)) - 1); + if (pri > maxpri) { + pri = maxpri; + } + pri = pri << (ECLIC_MAX_NLBITS - intctlbits); + uint8_t mask = ((uint8_t)(-1)) >> intctlbits; + pri = pri | mask; + uint8_t cur_ctrl = __ECLIC_GetCtrlIRQ(IRQn); + cur_ctrl = cur_ctrl >> (ECLIC_MAX_NLBITS - nlbits); + cur_ctrl = cur_ctrl << (ECLIC_MAX_NLBITS - nlbits); + __ECLIC_SetCtrlIRQ(IRQn, (cur_ctrl | pri)); + } +} + +/** + * \brief Get ECLIC Interrupt priority of a specific interrupt + * \details + * This function get interrupt priority of the specific interrupt \em IRQn. + * \param [in] IRQn Interrupt number + * \return Interrupt priority + * \remarks + * - IRQn must not be negative. + * \sa + * - \ref ECLIC_SetPriorityIRQ + */ +__STATIC_FORCEINLINE uint8_t __ECLIC_GetPriorityIRQ(IRQn_Type IRQn) +{ + uint8_t nlbits = __ECLIC_GetCfgNlbits(); + uint8_t intctlbits = (uint8_t)__ECLIC_INTCTLBITS; + if (nlbits < intctlbits) { + uint8_t cur_ctrl = __ECLIC_GetCtrlIRQ(IRQn); + uint8_t pri = cur_ctrl << nlbits; + pri = pri >> nlbits; + pri = pri >> (ECLIC_MAX_NLBITS - intctlbits); + return pri; + } else { + return 0; + } +} + +/** + * \brief Set Interrupt Vector of a specific interrupt + * \details + * This function set interrupt handler address of the specific interrupt \em IRQn. + * \param [in] IRQn Interrupt number + * \param [in] vector Interrupt handler address + * \remarks + * - IRQn must not be negative. + * - You can set the \ref CSR_CSR_MTVT to set interrupt vector table entry address. + * - If your vector table is placed in readonly section, the vector for IRQn will not be modified. + * For this case, you need to use the correct irq handler name defined in your vector table as + * your irq handler function name. + * - This function will only work correctly when the vector table is placed in an read-write enabled section. + * \sa + * - \ref ECLIC_GetVector + */ +__STATIC_FORCEINLINE void __ECLIC_SetVector(IRQn_Type IRQn, rv_csr_t vector) +{ +#if __RISCV_XLEN == 32 + volatile uint32_t vec_base; + vec_base = ((uint32_t)__RV_CSR_READ(CSR_MTVT)); + (* (unsigned long *) (vec_base + ((int32_t)IRQn) * 4)) = vector; +#elif __RISCV_XLEN == 64 + volatile uint64_t vec_base; + vec_base = ((uint64_t)__RV_CSR_READ(CSR_MTVT)); + (* (unsigned long *) (vec_base + ((int32_t)IRQn) * 8)) = vector; +#else // TODO Need cover for XLEN=128 case in future + volatile uint64_t vec_base; + vec_base = ((uint64_t)__RV_CSR_READ(CSR_MTVT)); + (* (unsigned long *) (vec_base + ((int32_t)IRQn) * 8)) = vector; +#endif +} + +/** + * \brief Get Interrupt Vector of a specific interrupt + * \details + * This function get interrupt handler address of the specific interrupt \em IRQn. + * \param [in] IRQn Interrupt number + * \return Interrupt handler address + * \remarks + * - IRQn must not be negative. + * - You can read \ref CSR_CSR_MTVT to get interrupt vector table entry address. + * \sa + * - \ref ECLIC_SetVector + */ +__STATIC_FORCEINLINE rv_csr_t __ECLIC_GetVector(IRQn_Type IRQn) +{ +#if __RISCV_XLEN == 32 + return (*(uint32_t *)(__RV_CSR_READ(CSR_MTVT)+IRQn*4)); +#elif __RISCV_XLEN == 64 + return (*(uint64_t *)(__RV_CSR_READ(CSR_MTVT)+IRQn*8)); +#else // TODO Need cover for XLEN=128 case in future + return (*(uint64_t *)(__RV_CSR_READ(CSR_MTVT)+IRQn*8)); +#endif +} + +/** + * \brief Set Exception entry address + * \details + * This function set exception handler address to 'CSR_MTVEC'. + * \param [in] addr Exception handler address + * \remarks + * - This function use to set exception handler address to 'CSR_MTVEC'. Address is 4 bytes align. + * \sa + * - \ref __get_exc_entry + */ +__STATIC_FORCEINLINE void __set_exc_entry(rv_csr_t addr) +{ + addr &= (rv_csr_t)(~0x3F); + addr |= ECLIC_MODE_MTVEC_Msk; + __RV_CSR_WRITE(CSR_MTVEC, addr); +} + +/** + * \brief Get Exception entry address + * \details + * This function get exception handler address from 'CSR_MTVEC'. + * \return Exception handler address + * \remarks + * - This function use to get exception handler address from 'CSR_MTVEC'. Address is 4 bytes align + * \sa + * - \ref __set_exc_entry + */ +__STATIC_FORCEINLINE rv_csr_t __get_exc_entry(void) +{ + unsigned long addr = __RV_CSR_READ(CSR_MTVEC); + return (addr & ~ECLIC_MODE_MTVEC_Msk); +} + +/** + * \brief Set Non-vector interrupt entry address + * \details + * This function set Non-vector interrupt address. + * \param [in] addr Non-vector interrupt entry address + * \remarks + * - This function use to set non-vector interrupt entry address to 'CSR_MTVT2' if + * - CSR_MTVT2 bit0 is 1. If 'CSR_MTVT2' bit0 is 0 then set address to 'CSR_MTVEC' + * \sa + * - \ref __get_nonvec_entry + */ +__STATIC_FORCEINLINE void __set_nonvec_entry(rv_csr_t addr) +{ + if (__RV_CSR_READ(CSR_MTVT2) & 0x1){ + __RV_CSR_WRITE(CSR_MTVT2, addr | 0x01); + } else { + addr &= (rv_csr_t)(~0x3F); + addr |= ECLIC_MODE_MTVEC_Msk; + __RV_CSR_WRITE(CSR_MTVEC, addr); + } +} + +/** + * \brief Get Non-vector interrupt entry address + * \details + * This function get Non-vector interrupt address. + * \return Non-vector interrupt handler address + * \remarks + * - This function use to get non-vector interrupt entry address from 'CSR_MTVT2' if + * - CSR_MTVT2 bit0 is 1. If 'CSR_MTVT2' bit0 is 0 then get address from 'CSR_MTVEC'. + * \sa + * - \ref __set_nonvec_entry + */ +__STATIC_FORCEINLINE rv_csr_t __get_nonvec_entry(void) +{ + if (__RV_CSR_READ(CSR_MTVT2) & 0x1) { + return __RV_CSR_READ(CSR_MTVT2) & (~(rv_csr_t)(0x1)); + } else { + rv_csr_t addr = __RV_CSR_READ(CSR_MTVEC); + return (addr & ~ECLIC_MODE_MTVEC_Msk); + } +} + +/** + * \brief Get NMI interrupt entry from 'CSR_MNVEC' + * \details + * This function get NMI interrupt address from 'CSR_MNVEC'. + * \return NMI interrupt handler address + * \remarks + * - This function use to get NMI interrupt handler address from 'CSR_MNVEC'. If CSR_MMISC_CTL[9] = 1 'CSR_MNVEC' + * - will be equal as mtvec. If CSR_MMISC_CTL[9] = 0 'CSR_MNVEC' will be equal as reset vector. + * - NMI entry is defined via \ref CSR_MMISC_CTL, writing to \ref CSR_MNVEC will be ignored. + */ +__STATIC_FORCEINLINE rv_csr_t __get_nmi_entry(void) +{ + return __RV_CSR_READ(CSR_MNVEC); +} + +/** + * \brief Save necessary CSRs into variables for vector interrupt nesting + * \details + * This macro is used to declare variables which are used for saving + * CSRs(MCAUSE, MEPC, MSUB), and it will read these CSR content into + * these variables, it need to be used in a vector-interrupt if nesting + * is required. + * \remarks + * - Interrupt will be enabled after this macro is called + * - It need to be used together with \ref RESTORE_IRQ_CSR_CONTEXT + * - Don't use variable names __mcause, __mpec, __msubm in your ISR code + * - If you want to enable interrupt nesting feature for vector interrupt, + * you can do it like this: + * \code + * // __INTERRUPT attribute will generates function entry and exit sequences suitable + * // for use in an interrupt handler when this attribute is present + * __INTERRUPT void eclic_mtip_handler(void) + * { + * // Must call this to save CSRs + * SAVE_IRQ_CSR_CONTEXT(); + * // !!!Interrupt is enabled here!!! + * // !!!Higher priority interrupt could nest it!!! + * + * // put you own interrupt handling code here + * + * // Must call this to restore CSRs + * RESTORE_IRQ_CSR_CONTEXT(); + * } + * \endcode + */ +#define SAVE_IRQ_CSR_CONTEXT() \ + rv_csr_t __mcause = __RV_CSR_READ(CSR_MCAUSE); \ + rv_csr_t __mepc = __RV_CSR_READ(CSR_MEPC); \ + rv_csr_t __msubm = __RV_CSR_READ(CSR_MSUBM); \ + __enable_irq(); + +/** + * \brief Restore necessary CSRs from variables for vector interrupt nesting + * \details + * This macro is used restore CSRs(MCAUSE, MEPC, MSUB) from pre-defined variables + * in \ref SAVE_IRQ_CSR_CONTEXT macro. + * \remarks + * - Interrupt will be disabled after this macro is called + * - It need to be used together with \ref SAVE_IRQ_CSR_CONTEXT + */ +#define RESTORE_IRQ_CSR_CONTEXT() \ + __disable_irq(); \ + __RV_CSR_WRITE(CSR_MSUBM, __msubm); \ + __RV_CSR_WRITE(CSR_MEPC, __mepc); \ + __RV_CSR_WRITE(CSR_MCAUSE, __mcause); + +/** @} */ /* End of Doxygen Group NMSIS_Core_IntExc */ + +#endif /* defined(__ECLIC_PRESENT) && (__ECLIC_PRESENT == 1) */ + +#ifdef __cplusplus +} +#endif +#endif /** __CORE_FEATURE_ECLIC__ */ diff --git a/components/nmsis/core/inc/core_feature_fpu.h b/components/nmsis/core/inc/core_feature_fpu.h new file mode 100644 index 00000000..c9e13b79 --- /dev/null +++ b/components/nmsis/core/inc/core_feature_fpu.h @@ -0,0 +1,304 @@ +/* + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef __CORE_FEATURE_FPU_H__ +#define __CORE_FEATURE_FPU_H__ +/*! + * @file core_feature_fpu.h + * @brief FPU feature API header file for Nuclei N/NX Core + */ +/* + * FPU Feature Configuration Macro: + * 1. __FPU_PRESENT: Define whether Floating Point Unit(FPU) is present or not + * * 0: Not present + * * 1: Single precision FPU present, __RISCV_FLEN == 32 + * * 2: Double precision FPU present, __RISCV_FLEN == 64 + */ +#ifdef __cplusplus + extern "C" { +#endif + +/* ===== FPU Operations ===== */ +/** + * \defgroup NMSIS_Core_FPU_Functions FPU Functions + * \ingroup NMSIS_Core + * \brief Functions that related to the RISC-V FPU (F and D extension). + * \details + * + * Nuclei provided floating point unit by RISC-V F and D extension. + * * `F extension` adds single-precision floating-point computational + * instructions compliant with the IEEE 754-2008 arithmetic standard, __RISCV_FLEN = 32. + * The F extension adds 32 floating-point registers, f0-f31, each 32 bits wide, + * and a floating-point control and status register fcsr, which contains the + * operating mode and exception status of the floating-point unit. + * * `D extension` adds double-precision floating-point computational instructions + * compliant with the IEEE 754-2008 arithmetic standard. + * The D extension widens the 32 floating-point registers, f0-f31, to 64 bits, __RISCV_FLEN = 64 + * @{ + */ +#if defined(__FPU_PRESENT) && (__FPU_PRESENT > 0) + +#if __FPU_PRESENT == 1 + /** \brief Refer to the width of the floating point register in bits(either 32 or 64) */ + #define __RISCV_FLEN 32 +#elif __FPU_PRESENT == 2 + #define __RISCV_FLEN 64 +#else + #define __RISCV_FLEN __riscv_flen +#endif /* __FPU_PRESENT == 1 */ + +/** \brief Get FCSR CSR Register */ +#define __get_FCSR() __RV_CSR_READ(CSR_FCSR) +/** \brief Set FCSR CSR Register with val */ +#define __set_FCSR(val) __RV_CSR_WRITE(CSR_FCSR, (val)) +/** \brief Get FRM CSR Register */ +#define __get_FRM() __RV_CSR_READ(CSR_FRM) +/** \brief Set FRM CSR Register with val */ +#define __set_FRM(val) __RV_CSR_WRITE(CSR_FRM, (val)) +/** \brief Get FFLAGS CSR Register */ +#define __get_FFLAGS() __RV_CSR_READ(CSR_FFLAGS) +/** \brief Set FFLAGS CSR Register with val */ +#define __set_FFLAGS(val) __RV_CSR_WRITE(CSR_FFLAGS, (val)) + +/** \brief Enable FPU Unit */ +#define __enable_FPU() __RV_CSR_SET(CSR_MSTATUS, MSTATUS_FS) +/** + * \brief Disable FPU Unit + * \details + * * We can save power by disable FPU Unit. + * * When FPU Unit is disabled, any access to FPU related CSR registers + * and FPU instructions will cause illegal Instuction Exception. + * */ +#define __disable_FPU() __RV_CSR_CLEAR(CSR_MSTATUS, MSTATUS_FS) + + +/** + * \brief Load a single-precision value from memory into float point register freg using flw instruction + * \details The FLW instruction loads a single-precision floating point value from memory + * address (addr + ofs) into floating point register freg(f0-f31) + * \param [in] freg The floating point register, eg. FREG(0), f0 + * \param [in] addr The memory base address, 4 byte aligned required + * \param [in] ofs a 12-bit immediate signed byte offset value, should be an const value + * \remarks + * * FLW and FSW operations need to make sure the address is 4 bytes aligned, + * otherwise it will cause exception code 4(Load address misaligned) or 6 (Store/AMO address misaligned) + * * FLW and FSW do not modify the bits being transferred; in particular, the payloads of non-canonical + * NaNs are preserved + * + */ +#define __RV_FLW(freg, addr, ofs) \ + ({ \ + register rv_csr_t __addr = (rv_csr_t)(addr); \ + __ASM volatile("flw " STRINGIFY(freg) ", %0(%1) " \ + : : "I"(ofs), "r"(__addr) \ + : "memory"); \ + }) + +/** + * \brief Store a single-precision value from float point freg into memory using fsw instruction + * \details The FSW instruction stores a single-precision value from floating point register to memory + * \param [in] freg The floating point register(f0-f31), eg. FREG(0), f0 + * \param [in] addr The memory base address, 4 byte aligned required + * \param [in] ofs a 12-bit immediate signed byte offset value, should be an const value + * \remarks + * * FLW and FSW operations need to make sure the address is 4 bytes aligned, + * otherwise it will cause exception code 4(Load address misaligned) or 6 (Store/AMO address misaligned) + * * FLW and FSW do not modify the bits being transferred; in particular, the payloads of non-canonical + * NaNs are preserved + * + */ +#define __RV_FSW(freg, addr, ofs) \ + ({ \ + register rv_csr_t __addr = (rv_csr_t)(addr); \ + __ASM volatile("fsw " STRINGIFY(freg) ", %0(%1) " \ + : : "I"(ofs), "r"(__addr) \ + : "memory"); \ + }) + +/** + * \brief Load a double-precision value from memory into float point register freg using fld instruction + * \details The FLD instruction loads a double-precision floating point value from memory + * address (addr + ofs) into floating point register freg(f0-f31) + * \param [in] freg The floating point register, eg. FREG(0), f0 + * \param [in] addr The memory base address, 8 byte aligned required + * \param [in] ofs a 12-bit immediate signed byte offset value, should be an const value + * \attention + * * Function only available for double precision floating point unit, FLEN = 64 + * \remarks + * * FLD and FSD operations need to make sure the address is 8 bytes aligned, + * otherwise it will cause exception code 4(Load address misaligned) or 6 (Store/AMO address misaligned) + * * FLD and FSD do not modify the bits being transferred; in particular, the payloads of non-canonical + * NaNs are preserved. + */ +#define __RV_FLD(freg, addr, ofs) \ + ({ \ + register rv_csr_t __addr = (rv_csr_t)(addr); \ + __ASM volatile("fld " STRINGIFY(freg) ", %0(%1) " \ + : : "I"(ofs), "r"(__addr) \ + : "memory"); \ + }) + +/** + * \brief Store a double-precision value from float point freg into memory using fsd instruction + * \details The FSD instruction stores double-precision value from floating point register to memory + * \param [in] freg The floating point register(f0-f31), eg. FREG(0), f0 + * \param [in] addr The memory base address, 8 byte aligned required + * \param [in] ofs a 12-bit immediate signed byte offset value, should be an const value + * \attention + * * Function only available for double precision floating point unit, FLEN = 64 + * \remarks + * * FLD and FSD operations need to make sure the address is 8 bytes aligned, + * otherwise it will cause exception code 4(Load address misaligned) or 6 (Store/AMO address misaligned) + * * FLD and FSD do not modify the bits being transferred; in particular, the payloads of non-canonical + * NaNs are preserved. + * + */ +#define __RV_FSD(freg, addr, ofs) \ + ({ \ + register rv_csr_t __addr = (rv_csr_t)(addr); \ + __ASM volatile("fsd " STRINGIFY(freg) ", %0(%1) " \ + : : "I"(ofs), "r"(__addr) \ + : "memory"); \ + }) + +/** + * \def __RV_FLOAD + * \brief Load a float point value from memory into float point register freg using flw/fld instruction + * \details + * * For Single-Precison Floating-Point Mode(__FPU_PRESENT == 1, __RISCV_FLEN == 32): + * It will call \ref __RV_FLW to load a single-precision floating point value from memory to floating point register + * * For Double-Precison Floating-Point Mode(__FPU_PRESENT == 2, __RISCV_FLEN == 64): + * It will call \ref __RV_FLD to load a double-precision floating point value from memory to floating point register + * + * \attention + * Function behaviour is different for __FPU_PRESENT = 1 or 2, please see the real function this macro represent + */ +/** + * \def __RV_FSTORE + * \brief Store a float value from float point freg into memory using fsw/fsd instruction + * \details + * * For Single-Precison Floating-Point Mode(__FPU_PRESENT == 1, __RISCV_FLEN == 32): + * It will call \ref __RV_FSW to store floating point register into memory + * * For Double-Precison Floating-Point Mode(__FPU_PRESENT == 2, __RISCV_FLEN == 64): + * It will call \ref __RV_FSD to store floating point register into memory + * + * \attention + * Function behaviour is different for __FPU_PRESENT = 1 or 2, please see the real function this macro represent + */ +#if __FPU_PRESENT == 1 +#define __RV_FLOAD __RV_FLW +#define __RV_FSTORE __RV_FSW +/** \brief Type of FPU register, depends on the FLEN defined in RISC-V */ +typedef uint32_t rv_fpu_t; +#elif __FPU_PRESENT == 2 +#define __RV_FLOAD __RV_FLD +#define __RV_FSTORE __RV_FSD +/** \brief Type of FPU register, depends on the FLEN defined in RISC-V */ +typedef uint64_t rv_fpu_t; +#endif /* __FPU_PRESENT == 2 */ + +/** + * \brief Save FPU context into variables for interrupt nesting + * \details + * This macro is used to declare variables which are used for saving + * FPU context, and it will store the nessary fpu registers into + * these variables, it need to be used in a interrupt when in this + * interrupt fpu registers are used. + * \remarks + * - It need to be used together with \ref RESTORE_FPU_CONTEXT + * - Don't use variable names __fpu_context in your ISR code + * - If you isr code will use fpu registers, and this interrupt is nested. + * Then you can do it like this: + * \code + * void eclic_mtip_handler(void) + * { + * // !!!Interrupt is enabled here!!! + * // !!!Higher priority interrupt could nest it!!! + * + * // Necessary only when you need to use fpu registers + * // in this isr handler functions + * SAVE_FPU_CONTEXT(); + * + * // put you own interrupt handling code here + * + * // pair of SAVE_FPU_CONTEXT() + * RESTORE_FPU_CONTEXT(); + * } + * \endcode + */ +#define SAVE_FPU_CONTEXT() \ + rv_fpu_t __fpu_context[20]; \ + __RV_FSTORE(FREG(0), __fpu_context, 0 << LOG_FPREGBYTES); \ + __RV_FSTORE(FREG(1), __fpu_context, 1 << LOG_FPREGBYTES); \ + __RV_FSTORE(FREG(2), __fpu_context, 2 << LOG_FPREGBYTES); \ + __RV_FSTORE(FREG(3), __fpu_context, 3 << LOG_FPREGBYTES); \ + __RV_FSTORE(FREG(4), __fpu_context, 4 << LOG_FPREGBYTES); \ + __RV_FSTORE(FREG(5), __fpu_context, 5 << LOG_FPREGBYTES); \ + __RV_FSTORE(FREG(6), __fpu_context, 6 << LOG_FPREGBYTES); \ + __RV_FSTORE(FREG(7), __fpu_context, 7 << LOG_FPREGBYTES); \ + __RV_FSTORE(FREG(10), __fpu_context, 8 << LOG_FPREGBYTES); \ + __RV_FSTORE(FREG(11), __fpu_context, 9 << LOG_FPREGBYTES); \ + __RV_FSTORE(FREG(12), __fpu_context, 10 << LOG_FPREGBYTES); \ + __RV_FSTORE(FREG(13), __fpu_context, 11 << LOG_FPREGBYTES); \ + __RV_FSTORE(FREG(14), __fpu_context, 12 << LOG_FPREGBYTES); \ + __RV_FSTORE(FREG(15), __fpu_context, 13 << LOG_FPREGBYTES); \ + __RV_FSTORE(FREG(16), __fpu_context, 14 << LOG_FPREGBYTES); \ + __RV_FSTORE(FREG(17), __fpu_context, 15 << LOG_FPREGBYTES); \ + __RV_FSTORE(FREG(28), __fpu_context, 16 << LOG_FPREGBYTES); \ + __RV_FSTORE(FREG(29), __fpu_context, 17 << LOG_FPREGBYTES); \ + __RV_FSTORE(FREG(30), __fpu_context, 18 << LOG_FPREGBYTES); \ + __RV_FSTORE(FREG(31), __fpu_context, 19 << LOG_FPREGBYTES); + +/** + * \brief Restore necessary fpu registers from variables for interrupt nesting + * \details + * This macro is used restore necessary fpu registers from pre-defined variables + * in \ref SAVE_FPU_CONTEXT macro. + * \remarks + * - It need to be used together with \ref SAVE_FPU_CONTEXT + */ +#define RESTORE_FPU_CONTEXT() \ + __RV_FLOAD(FREG(0), __fpu_context, 0 << LOG_FPREGBYTES); \ + __RV_FLOAD(FREG(1), __fpu_context, 1 << LOG_FPREGBYTES); \ + __RV_FLOAD(FREG(2), __fpu_context, 2 << LOG_FPREGBYTES); \ + __RV_FLOAD(FREG(3), __fpu_context, 3 << LOG_FPREGBYTES); \ + __RV_FLOAD(FREG(4), __fpu_context, 4 << LOG_FPREGBYTES); \ + __RV_FLOAD(FREG(5), __fpu_context, 5 << LOG_FPREGBYTES); \ + __RV_FLOAD(FREG(6), __fpu_context, 6 << LOG_FPREGBYTES); \ + __RV_FLOAD(FREG(7), __fpu_context, 7 << LOG_FPREGBYTES); \ + __RV_FLOAD(FREG(10), __fpu_context, 8 << LOG_FPREGBYTES); \ + __RV_FLOAD(FREG(11), __fpu_context, 9 << LOG_FPREGBYTES); \ + __RV_FLOAD(FREG(12), __fpu_context, 10 << LOG_FPREGBYTES); \ + __RV_FLOAD(FREG(13), __fpu_context, 11 << LOG_FPREGBYTES); \ + __RV_FLOAD(FREG(14), __fpu_context, 12 << LOG_FPREGBYTES); \ + __RV_FLOAD(FREG(15), __fpu_context, 13 << LOG_FPREGBYTES); \ + __RV_FLOAD(FREG(16), __fpu_context, 14 << LOG_FPREGBYTES); \ + __RV_FLOAD(FREG(17), __fpu_context, 15 << LOG_FPREGBYTES); \ + __RV_FLOAD(FREG(28), __fpu_context, 16 << LOG_FPREGBYTES); \ + __RV_FLOAD(FREG(29), __fpu_context, 17 << LOG_FPREGBYTES); \ + __RV_FLOAD(FREG(30), __fpu_context, 18 << LOG_FPREGBYTES); \ + __RV_FLOAD(FREG(31), __fpu_context, 19 << LOG_FPREGBYTES); +#else +#define SAVE_FPU_CONTEXT() +#define RESTORE_FPU_CONTEXT() +#endif /* __FPU_PRESENT > 0 */ +/** @} */ /* End of Doxygen Group NMSIS_Core_FPU_Functions */ + +#ifdef __cplusplus +} +#endif +#endif /** __RISCV_EXT_FPU_H__ */ diff --git a/components/nmsis/core/inc/core_feature_pmp.h b/components/nmsis/core/inc/core_feature_pmp.h new file mode 100644 index 00000000..997dfaee --- /dev/null +++ b/components/nmsis/core/inc/core_feature_pmp.h @@ -0,0 +1,260 @@ +/* + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef __CORE_FEATURE_PMP_H__ +#define __CORE_FEATURE_PMP_H__ +/*! + * @file core_feature_pmp.h + * @brief PMP feature API header file for Nuclei N/NX Core + */ +/* + * PMP Feature Configuration Macro: + * 1. __PMP_PRESENT: Define whether Physical Memory Protection(PMP) is present or not + * * 0: Not present + * * 1: Present + * 2. __PMP_ENTRY_NUM: Define the number of PMP entries, only 8 or 16 is configurable. + */ +#ifdef __cplusplus + extern "C" { +#endif + +#if defined(__PMP_PRESENT) && (__PMP_PRESENT == 1) +/* ===== PMP Operations ===== */ +/** + * \defgroup NMSIS_Core_PMP_Functions PMP Functions + * \ingroup NMSIS_Core + * \brief Functions that related to the RISCV Phyiscal Memory Protection. + * \details + * Optional physical memory protection (PMP) unit provides per-hart machine-mode + * control registers to allow physical memory access privileges (read, write, execute) + * to be specified for each physical memory region. + * + * The PMP can supports region access control settings as small as four bytes. + * + * @{ + */ +#ifndef __PMP_ENTRY_NUM +/* numbers of PMP entries(__PMP_ENTRY_NUM) should be defined in */ +#error "__PMP_ENTRY_NUM is not defined, please check!" +#endif + +/** + * \brief Get 8bit PMPxCFG Register by PMP entry index + * \details Return the content of the PMPxCFG Register. + * \param [in] idx PMP region index(0-15) + * \return PMPxCFG Register value + */ +__STATIC_INLINE uint8_t __get_PMPxCFG(uint32_t idx) +{ + rv_csr_t pmpcfg = 0; + + if (idx >= __PMP_ENTRY_NUM) return 0; +#if __RISCV_XLEN == 32 + if (idx < 4) { + pmpcfg = __RV_CSR_READ(CSR_PMPCFG0); + } else if ((idx >=4) && (idx < 8)) { + idx -= 4; + pmpcfg = __RV_CSR_READ(CSR_PMPCFG1); + } else if ((idx >=8) && (idx < 12)) { + idx -= 8; + pmpcfg = __RV_CSR_READ(CSR_PMPCFG2); + } else { + idx -= 12; + pmpcfg = __RV_CSR_READ(CSR_PMPCFG3); + } + + idx = idx << 3; + return (uint8_t)((pmpcfg>>idx) & 0xFF); +#elif __RISCV_XLEN == 64 + if (idx < 8) { + pmpcfg = __RV_CSR_READ(CSR_PMPCFG0); + } else { + idx -= 8; + pmpcfg = __RV_CSR_READ(CSR_PMPCFG2); + } + idx = idx << 3; + return (uint8_t)((pmpcfg>>idx) & 0xFF); +#else + // TODO Add RV128 Handling + return 0; +#endif +} + +/** + * \brief Set 8bit PMPxCFG by pmp entry index + * \details Set the given pmpxcfg value to the PMPxCFG Register. + * \param [in] idx PMPx region index(0-15) + * \param [in] pmpxcfg PMPxCFG register value to set + */ +__STATIC_INLINE void __set_PMPxCFG(uint32_t idx, uint8_t pmpxcfg) +{ + rv_csr_t pmpcfgx = 0; + if (idx >= __PMP_ENTRY_NUM) return; + +#if __RISCV_XLEN == 32 + if (idx < 4) { + pmpcfgx = __RV_CSR_READ(CSR_PMPCFG0); + idx = idx << 3; + pmpcfgx = (pmpcfgx & ~(0xFFUL << idx)) | ((rv_csr_t)pmpxcfg << idx); + __RV_CSR_WRITE(CSR_PMPCFG0, pmpcfgx); + } else if ((idx >=4) && (idx < 8)) { + idx -= 4; + pmpcfgx = __RV_CSR_READ(CSR_PMPCFG1); + idx = idx << 3; + pmpcfgx = (pmpcfgx & ~(0xFFUL << idx)) | ((rv_csr_t)pmpxcfg << idx); + __RV_CSR_WRITE(CSR_PMPCFG1, pmpcfgx); + } else if ((idx >=8) && (idx < 12)) { + idx -= 8; + pmpcfgx = __RV_CSR_READ(CSR_PMPCFG2); + idx = idx << 3; + pmpcfgx = (pmpcfgx & ~(0xFFUL << idx)) | ((rv_csr_t)pmpxcfg << idx); + __RV_CSR_WRITE(CSR_PMPCFG2, pmpcfgx); + } else { + idx -= 12; + pmpcfgx = __RV_CSR_READ(CSR_PMPCFG3); + idx = idx << 3; + pmpcfgx = (pmpcfgx & ~(0xFFUL << idx)) | ((rv_csr_t)pmpxcfg << idx); + __RV_CSR_WRITE(CSR_PMPCFG3, pmpcfgx); + } +#elif __RISCV_XLEN == 64 + if (idx < 8) { + pmpcfgx = __RV_CSR_READ(CSR_PMPCFG0); + idx = idx << 3; + pmpcfgx = (pmpcfgx & ~(0xFFULL << idx)) | ((rv_csr_t)pmpxcfg << idx); + __RV_CSR_WRITE(CSR_PMPCFG0, pmpcfgx); + } else { + idx -= 8; + pmpcfgx = __RV_CSR_READ(CSR_PMPCFG2); + idx = idx << 3; + pmpcfgx = (pmpcfgx & ~(0xFFULL << idx)) | ((rv_csr_t)pmpxcfg << idx); + __RV_CSR_WRITE(CSR_PMPCFG2, pmpcfgx); + } +#else + // TODO Add RV128 Handling +#endif +} + +/** + * \brief Get PMPCFGx Register by index + * \details Return the content of the PMPCFGx Register. + * \param [in] idx PMPCFG CSR index(0-3) + * \return PMPCFGx Register value + * \remark + * - For RV64, only idx = 0 and idx = 2 is allowed. + * pmpcfg0 and pmpcfg2 hold the configurations + * for the 16 PMP entries, pmpcfg1 and pmpcfg3 are illegal + * - For RV32, pmpcfg0–pmpcfg3, hold the configurations + * pmp0cfg–pmp15cfg for the 16 PMP entries + */ +__STATIC_INLINE rv_csr_t __get_PMPCFGx(uint32_t idx) +{ + switch (idx) { + case 0: return __RV_CSR_READ(CSR_PMPCFG0); + case 1: return __RV_CSR_READ(CSR_PMPCFG1); + case 2: return __RV_CSR_READ(CSR_PMPCFG2); + case 3: return __RV_CSR_READ(CSR_PMPCFG3); + default: return 0; + } +} + +/** + * \brief Set PMPCFGx by index + * \details Write the given value to the PMPCFGx Register. + * \param [in] idx PMPCFG CSR index(0-3) + * \param [in] pmpcfg PMPCFGx Register value to set + * \remark + * - For RV64, only idx = 0 and idx = 2 is allowed. + * pmpcfg0 and pmpcfg2 hold the configurations + * for the 16 PMP entries, pmpcfg1 and pmpcfg3 are illegal + * - For RV32, pmpcfg0–pmpcfg3, hold the configurations + * pmp0cfg–pmp15cfg for the 16 PMP entries + */ +__STATIC_INLINE void __set_PMPCFGx(uint32_t idx, rv_csr_t pmpcfg) +{ + switch (idx) { + case 0: __RV_CSR_WRITE(CSR_PMPCFG0, pmpcfg); break; + case 1: __RV_CSR_WRITE(CSR_PMPCFG1, pmpcfg); break; + case 2: __RV_CSR_WRITE(CSR_PMPCFG2, pmpcfg); break; + case 3: __RV_CSR_WRITE(CSR_PMPCFG3, pmpcfg); break; + default: return; + } +} + +/** + * \brief Get PMPADDRx Register by index + * \details Return the content of the PMPADDRx Register. + * \param [in] idx PMP region index(0-15) + * \return PMPADDRx Register value + */ +__STATIC_INLINE rv_csr_t __get_PMPADDRx(uint32_t idx) +{ + switch (idx) { + case 0: return __RV_CSR_READ(CSR_PMPADDR0); + case 1: return __RV_CSR_READ(CSR_PMPADDR1); + case 2: return __RV_CSR_READ(CSR_PMPADDR2); + case 3: return __RV_CSR_READ(CSR_PMPADDR3); + case 4: return __RV_CSR_READ(CSR_PMPADDR4); + case 5: return __RV_CSR_READ(CSR_PMPADDR5); + case 6: return __RV_CSR_READ(CSR_PMPADDR6); + case 7: return __RV_CSR_READ(CSR_PMPADDR7); + case 8: return __RV_CSR_READ(CSR_PMPADDR8); + case 9: return __RV_CSR_READ(CSR_PMPADDR9); + case 10: return __RV_CSR_READ(CSR_PMPADDR10); + case 11: return __RV_CSR_READ(CSR_PMPADDR11); + case 12: return __RV_CSR_READ(CSR_PMPADDR12); + case 13: return __RV_CSR_READ(CSR_PMPADDR13); + case 14: return __RV_CSR_READ(CSR_PMPADDR14); + case 15: return __RV_CSR_READ(CSR_PMPADDR15); + default: return 0; + } +} + +/** + * \brief Set PMPADDRx by index + * \details Write the given value to the PMPADDRx Register. + * \param [in] idx PMP region index(0-15) + * \param [in] pmpaddr PMPADDRx Register value to set + */ +__STATIC_INLINE void __set_PMPADDRx(uint32_t idx, rv_csr_t pmpaddr) +{ + switch (idx) { + case 0: __RV_CSR_WRITE(CSR_PMPADDR0, pmpaddr); break; + case 1: __RV_CSR_WRITE(CSR_PMPADDR1, pmpaddr); break; + case 2: __RV_CSR_WRITE(CSR_PMPADDR2, pmpaddr); break; + case 3: __RV_CSR_WRITE(CSR_PMPADDR3, pmpaddr); break; + case 4: __RV_CSR_WRITE(CSR_PMPADDR4, pmpaddr); break; + case 5: __RV_CSR_WRITE(CSR_PMPADDR5, pmpaddr); break; + case 6: __RV_CSR_WRITE(CSR_PMPADDR6, pmpaddr); break; + case 7: __RV_CSR_WRITE(CSR_PMPADDR7, pmpaddr); break; + case 8: __RV_CSR_WRITE(CSR_PMPADDR8, pmpaddr); break; + case 9: __RV_CSR_WRITE(CSR_PMPADDR9, pmpaddr); break; + case 10: __RV_CSR_WRITE(CSR_PMPADDR10, pmpaddr); break; + case 11: __RV_CSR_WRITE(CSR_PMPADDR11, pmpaddr); break; + case 12: __RV_CSR_WRITE(CSR_PMPADDR12, pmpaddr); break; + case 13: __RV_CSR_WRITE(CSR_PMPADDR13, pmpaddr); break; + case 14: __RV_CSR_WRITE(CSR_PMPADDR14, pmpaddr); break; + case 15: __RV_CSR_WRITE(CSR_PMPADDR15, pmpaddr); break; + default: return; + } +} +/** @} */ /* End of Doxygen Group NMSIS_Core_PMP_Functions */ +#endif /* defined(__PMP_PRESENT) && (__PMP_PRESENT == 1) */ + +#ifdef __cplusplus +} +#endif +#endif /** __CORE_FEATURE_PMP_H__ */ diff --git a/components/nmsis/core/inc/core_feature_timer.h b/components/nmsis/core/inc/core_feature_timer.h new file mode 100644 index 00000000..6e9b7af3 --- /dev/null +++ b/components/nmsis/core/inc/core_feature_timer.h @@ -0,0 +1,364 @@ +/* + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef __CORE_FEATURE_TIMER_H__ +#define __CORE_FEATURE_TIMER_H__ +/*! + * @file core_feature_timer.h + * @brief System Timer feature API header file for Nuclei N/NX Core + */ +/* + * System Timer Feature Configuration Macro: + * 1. __SYSTIMER_PRESENT: Define whether Private System Timer is present or not. + * * 0: Not present + * * 1: Present + * 2. __SYSTIMER_BASEADDR: Define the base address of the System Timer. + */ +#ifdef __cplusplus + extern "C" { +#endif + +#if defined(__SYSTIMER_PRESENT) && (__SYSTIMER_PRESENT == 1) +/** + * \defgroup NMSIS_Core_SysTimer_Registers Register Define and Type Definitions Of System Timer + * \ingroup NMSIS_Core_Registers + * \brief Type definitions and defines for system timer registers. + * + * @{ + */ +/** + * \brief Structure type to access the System Timer (SysTimer). + * \details + * Structure definition to access the system timer(SysTimer). + * \remarks + * - MSFTRST register is introduced in Nuclei N Core version 1.3(\ref __NUCLEI_N_REV >= 0x0103) + * - MSTOP register is renamed to MTIMECTL register in Nuclei N Core version 1.4(\ref __NUCLEI_N_REV >= 0x0104) + * - CMPCLREN and CLKSRC bit in MTIMECTL register is introduced in Nuclei N Core version 1.4(\ref __NUCLEI_N_REV >= 0x0104) + */ +typedef struct { + __IOM uint64_t MTIMER; /*!< Offset: 0x000 (R/W) System Timer current value 64bits Register */ + __IOM uint64_t MTIMERCMP; /*!< Offset: 0x008 (R/W) System Timer compare Value 64bits Register */ + __IOM uint32_t RESERVED0[0x3F8]; /*!< Offset: 0x010 - 0xFEC Reserved */ + __IOM uint32_t MSFTRST; /*!< Offset: 0xFF0 (R/W) System Timer Software Core Reset Register */ + __IOM uint32_t RESERVED1; /*!< Offset: 0xFF4 Reserved */ + __IOM uint32_t MTIMECTL; /*!< Offset: 0xFF8 (R/W) System Timer Control Register, previously MSTOP register */ + __IOM uint32_t MSIP; /*!< Offset: 0xFFC (R/W) System Timer SW interrupt Register */ +} SysTimer_Type; + +/* Timer Control / Status Register Definitions */ +#define SysTimer_MTIMECTL_TIMESTOP_Pos 0U /*!< SysTick Timer MTIMECTL: TIMESTOP bit Position */ +#define SysTimer_MTIMECTL_TIMESTOP_Msk (1UL << SysTimer_MTIMECTL_TIMESTOP_Pos) /*!< SysTick Timer MTIMECTL: TIMESTOP Mask */ +#define SysTimer_MTIMECTL_CMPCLREN_Pos 1U /*!< SysTick Timer MTIMECTL: CMPCLREN bit Position */ +#define SysTimer_MTIMECTL_CMPCLREN_Msk (1UL << SysTimer_MTIMECTL_CMPCLREN_Pos) /*!< SysTick Timer MTIMECTL: CMPCLREN Mask */ +#define SysTimer_MTIMECTL_CLKSRC_Pos 2U /*!< SysTick Timer MTIMECTL: CLKSRC bit Position */ +#define SysTimer_MTIMECTL_CLKSRC_Msk (1UL << SysTimer_MTIMECTL_CLKSRC_Pos) /*!< SysTick Timer MTIMECTL: CLKSRC Mask */ + +#define SysTimer_MSIP_MSIP_Pos 0U /*!< SysTick Timer MSIP: MSIP bit Position */ +#define SysTimer_MSIP_MSIP_Msk (1UL << SysTimer_MSIP_MSIP_Pos) /*!< SysTick Timer MSIP: MSIP Mask */ + +#define SysTimer_MTIMER_Msk (0xFFFFFFFFFFFFFFFFULL) /*!< SysTick Timer MTIMER value Mask */ +#define SysTimer_MTIMERCMP_Msk (0xFFFFFFFFFFFFFFFFULL) /*!< SysTick Timer MTIMERCMP value Mask */ +#define SysTimer_MTIMECTL_Msk (0xFFFFFFFFUL) /*!< SysTick Timer MTIMECTL/MSTOP value Mask */ +#define SysTimer_MSIP_Msk (0xFFFFFFFFUL) /*!< SysTick Timer MSIP value Mask */ +#define SysTimer_MSFTRST_Msk (0xFFFFFFFFUL) /*!< SysTick Timer MSFTRST value Mask */ + +#define SysTimer_MSFRST_KEY (0x80000A5FUL) /*!< SysTick Timer Software Reset Request Key */ + +#ifndef __SYSTIMER_BASEADDR +/* Base address of SYSTIMER(__SYSTIMER_BASEADDR) should be defined in */ +#error "__SYSTIMER_BASEADDR is not defined, please check!" +#endif +/* System Timer Memory mapping of Device */ +#define SysTimer_BASE __SYSTIMER_BASEADDR /*!< SysTick Base Address */ +#define SysTimer ((SysTimer_Type *) SysTimer_BASE) /*!< SysTick configuration struct */ +/** @} */ /* end of group NMSIS_Core_SysTimer_Registers */ + +/* ################################## SysTimer function ############################################ */ +/** + * \defgroup NMSIS_Core_SysTimer SysTimer Functions + * \brief Functions that configure the Core System Timer. + * @{ + */ +/** + * \brief Set system timer load value + * \details + * This function set the system timer load value in MTIMER register. + * \param [in] value value to set system timer MTIMER register. + * \remarks + * - Load value is 64bits wide. + * - \ref SysTimer_GetLoadValue + */ +__STATIC_FORCEINLINE void SysTimer_SetLoadValue(uint64_t value) +{ + SysTimer->MTIMER = value; +} + +/** + * \brief Get system timer load value + * \details + * This function get the system timer current value in MTIMER register. + * \return current value(64bit) of system timer MTIMER register. + * \remarks + * - Load value is 64bits wide. + * - \ref SysTimer_SetLoadValue + */ +__STATIC_FORCEINLINE uint64_t SysTimer_GetLoadValue(void) +{ + return SysTimer->MTIMER; +} + +/** + * \brief Set system timer compare value + * \details + * This function set the system Timer compare value in MTIMERCMP register. + * \param [in] value compare value to set system timer MTIMERCMP register. + * \remarks + * - Compare value is 64bits wide. + * - If compare value is larger than current value timer interrupt generate. + * - Modify the load value or compare value less to clear the interrupt. + * - \ref SysTimer_GetCompareValue + */ +__STATIC_FORCEINLINE void SysTimer_SetCompareValue(uint64_t value) +{ + SysTimer->MTIMERCMP = value; +} + +/** + * \brief Get system timer compare value + * \details + * This function get the system timer compare value in MTIMERCMP register. + * \return compare value of system timer MTIMERCMP register. + * \remarks + * - Compare value is 64bits wide. + * - \ref SysTimer_SetCompareValue + */ +__STATIC_FORCEINLINE uint64_t SysTimer_GetCompareValue(void) +{ + return SysTimer->MTIMERCMP; +} + +/** + * \brief Enable system timer counter running + * \details + * Enable system timer counter running by clear + * TIMESTOP bit in MTIMECTL register. + */ +__STATIC_FORCEINLINE void SysTimer_Start(void) +{ + SysTimer->MTIMECTL &= ~(SysTimer_MTIMECTL_TIMESTOP_Msk); +} + +/** + * \brief Stop system timer counter running + * \details + * Stop system timer counter running by set + * TIMESTOP bit in MTIMECTL register. + */ +__STATIC_FORCEINLINE void SysTimer_Stop(void) +{ + SysTimer->MTIMECTL |= SysTimer_MTIMECTL_TIMESTOP_Msk; +} + +/** + * \brief Set system timer control value + * \details + * This function set the system timer MTIMECTL register value. + * \param [in] mctl value to set MTIMECTL register + * \remarks + * - Bit TIMESTOP is used to start and stop timer. + * Clear TIMESTOP bit to 0 to start timer, otherwise to stop timer. + * - Bit CMPCLREN is used to enable auto MTIMER clear to zero when MTIMER >= MTIMERCMP. + * Clear CMPCLREN bit to 0 to stop auto clear MTIMER feature, otherwise to enable it. + * - Bit CLKSRC is used to select timer clock source. + * Clear CLKSRC bit to 0 to use *mtime_toggle_a*, otherwise use *core_clk_aon* + * - \ref SysTimer_GetControlValue + */ +__STATIC_FORCEINLINE void SysTimer_SetControlValue(uint32_t mctl) +{ + SysTimer->MTIMECTL = (mctl & SysTimer_MTIMECTL_Msk); +} + +/** + * \brief Get system timer control value + * \details + * This function get the system timer MTIMECTL register value. + * \return MTIMECTL register value + * \remarks + * - \ref SysTimer_SetControlValue + */ +__STATIC_FORCEINLINE uint32_t SysTimer_GetControlValue(void) +{ + return (SysTimer->MTIMECTL & SysTimer_MTIMECTL_Msk); +} + +/** + * \brief Trigger or set software interrupt via system timer + * \details + * This function set the system timer MSIP bit in MSIP register. + * \remarks + * - Set system timer MSIP bit and generate a SW interrupt. + * - \ref SysTimer_ClearSWIRQ + * - \ref SysTimer_GetMsipValue + */ +__STATIC_FORCEINLINE void SysTimer_SetSWIRQ(void) +{ + SysTimer->MSIP |= SysTimer_MSIP_MSIP_Msk; +} + +/** + * \brief Clear system timer software interrupt pending request + * \details + * This function clear the system timer MSIP bit in MSIP register. + * \remarks + * - Clear system timer MSIP bit in MSIP register to clear the software interrupt pending. + * - \ref SysTimer_SetSWIRQ + * - \ref SysTimer_GetMsipValue + */ +__STATIC_FORCEINLINE void SysTimer_ClearSWIRQ(void) +{ + SysTimer->MSIP &= ~SysTimer_MSIP_MSIP_Msk; +} + +/** + * \brief Get system timer MSIP register value + * \details + * This function get the system timer MSIP register value. + * \return Value of Timer MSIP register. + * \remarks + * - Bit0 is SW interrupt flag. + * Bit0 is 1 then SW interrupt set. Bit0 is 0 then SW interrupt clear. + * - \ref SysTimer_SetSWIRQ + * - \ref SysTimer_ClearSWIRQ + */ +__STATIC_FORCEINLINE uint32_t SysTimer_GetMsipValue(void) +{ + return (uint32_t)(SysTimer->MSIP & SysTimer_MSIP_Msk); +} + +/** + * \brief Set system timer MSIP register value + * \details + * This function set the system timer MSIP register value. + * \param [in] msip value to set MSIP register + */ +__STATIC_FORCEINLINE void SysTimer_SetMsipValue(uint32_t msip) +{ + SysTimer->MSIP = (msip & SysTimer_MSIP_Msk); +} + +/** + * \brief Do software reset request + * \details + * This function will do software reset request through MTIMER + * - Software need to write \ref SysTimer_MSFRST_KEY to generate software reset request + * - The software request flag can be cleared by reset operation to clear + * \remarks + * - The software reset is sent to SoC, SoC need to generate reset signal and send back to Core + * - This function will not return, it will do while(1) to wait the Core reset happened + */ +__STATIC_FORCEINLINE void SysTimer_SoftwareReset(void) +{ + SysTimer->MSFTRST = SysTimer_MSFRST_KEY; + while(1); +} + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) && defined(__ECLIC_PRESENT) && (__ECLIC_PRESENT == 1) +/** + * \brief System Tick Configuration + * \details Initializes the System Timer and its non-vector interrupt, and starts the System Tick Timer. + * + * In our default implementation, the timer counter will be set to zero, and it will start a timer compare non-vector interrupt + * when it matchs the ticks user set, during the timer interrupt user should reload the system tick using \ref SysTick_Reload function + * or similar function written by user, so it can produce period timer interrupt. + * \param [in] ticks Number of ticks between two interrupts. + * \return 0 Function succeeded. + * \return 1 Function failed. + * \remarks + * - For \ref __NUCLEI_N_REV >= 0x0104, the CMPCLREN bit in MTIMECTL is introduced, + * but we assume that the CMPCLREN bit is set to 0, so MTIMER register will not be + * auto cleared to 0 when MTIMER >= MTIMERCMP. + * - When the variable \ref __Vendor_SysTickConfig is set to 1, then the + * function \ref SysTick_Config is not included. + * - In this case, the file .h must contain a vendor-specific implementation + * of this function. + * - If user need this function to start a period timer interrupt, then in timer interrupt handler + * routine code, user should call \ref SysTick_Reload with ticks to reload the timer. + * - This function only available when __SYSTIMER_PRESENT == 1 and __ECLIC_PRESENT == 1 and __Vendor_SysTickConfig == 0 + * \sa + * - \ref SysTimer_SetCompareValue; SysTimer_SetLoadValue + */ +__STATIC_INLINE uint32_t SysTick_Config(uint64_t ticks) +{ + SysTimer_SetLoadValue(0); + SysTimer_SetCompareValue(ticks); + ECLIC_SetShvIRQ(SysTimer_IRQn, ECLIC_NON_VECTOR_INTERRUPT); + ECLIC_SetLevelIRQ(SysTimer_IRQn, 0); + ECLIC_EnableIRQ(SysTimer_IRQn); + return (0UL); +} + +/** + * \brief System Tick Reload + * \details Reload the System Timer Tick when the MTIMECMP reached TIME value + * + * \param [in] ticks Number of ticks between two interrupts. + * \return 0 Function succeeded. + * \return 1 Function failed. + * \remarks + * - For \ref __NUCLEI_N_REV >= 0x0104, the CMPCLREN bit in MTIMECTL is introduced, + * but for this \ref SysTick_Config function, we assume this CMPCLREN bit is set to 0, + * so in interrupt handler function, user still need to set the MTIMERCMP or MTIMER to reload + * the system tick, if vendor want to use this timer's auto clear feature, they can define + * \ref __Vendor_SysTickConfig to 1, and implement \ref SysTick_Config and \ref SysTick_Reload functions. + * - When the variable \ref __Vendor_SysTickConfig is set to 1, then the + * function \ref SysTick_Reload is not included. + * - In this case, the file .h must contain a vendor-specific implementation + * of this function. + * - This function only available when __SYSTIMER_PRESENT == 1 and __ECLIC_PRESENT == 1 and __Vendor_SysTickConfig == 0 + * - Since the MTIMERCMP value might overflow, if overflowed, MTIMER will be set to 0, and MTIMERCMP set to ticks + * \sa + * - \ref SysTimer_SetCompareValue + * - \ref SysTimer_SetLoadValue + */ +__STATIC_FORCEINLINE uint32_t SysTick_Reload(uint64_t ticks) +{ + uint64_t cur_ticks = SysTimer->MTIMER; + uint64_t reload_ticks = ticks + cur_ticks; + + if (__USUALLY(reload_ticks > cur_ticks)) { + SysTimer->MTIMERCMP = reload_ticks; + } else { + /* When added the ticks value, then the MTIMERCMP < TIMER, + * which means the MTIMERCMP is overflowed, + * so we need to reset the counter to zero */ + SysTimer->MTIMER = 0; + SysTimer->MTIMERCMP = ticks; + } + + return (0UL); +} + +#endif /* defined(__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) */ +/** @} */ /* End of Doxygen Group NMSIS_Core_SysTimer */ + +#endif /* defined(__SYSTIMER_PRESENT) && (__SYSTIMER_PRESENT == 1) */ + +#ifdef __cplusplus +} +#endif +#endif /** __CORE_FEATURE_TIMER_H__ */ + diff --git a/components/nmsis/core/inc/nmsis_compiler.h b/components/nmsis/core/inc/nmsis_compiler.h new file mode 100644 index 00000000..c5278db1 --- /dev/null +++ b/components/nmsis/core/inc/nmsis_compiler.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __NMSIS_COMPILER_H +#define __NMSIS_COMPILER_H + +#include + +/*! + * @file nmsis_compiler.h + * @brief NMSIS compiler generic header file + */ +#if defined ( __GNUC__ ) + /** GNU GCC Compiler */ + #include "nmsis_gcc.h" +#else + #error Unknown compiler. +#endif + + +#endif /* __NMSIS_COMPILER_H */ + diff --git a/components/nmsis/core/inc/nmsis_core.h b/components/nmsis/core/inc/nmsis_core.h new file mode 100644 index 00000000..91a8fbcf --- /dev/null +++ b/components/nmsis/core/inc/nmsis_core.h @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * -- Adaptable modifications made for Nuclei Processors. -- + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef __NMSIS_CORE_H__ +#define __NMSIS_CORE_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nmsis_version.h" + +/** + * \ingroup NMSIS_Core_VersionControl + * @{ + */ +/* The following enum __NUCLEI_N_REV/__NUCLEI_NX_REV definition in this file + * is only used for doxygen documentation generation, + * The .h is the real file to define it by vendor + */ +#if defined(__ONLY_FOR_DOXYGEN_DOCUMENT_GENERATION__) +/** + * \brief Nuclei N class core revision number + * \details + * Reversion number format: [15:8] revision number, [7:0] patch number + * \attention + * This define is exclusive with \ref __NUCLEI_NX_REV + */ +#define __NUCLEI_N_REV (0x0104) +/** + * \brief Nuclei NX class core revision number + * \details + * Reversion number format: [15:8] revision number, [7:0] patch number + * \attention + * This define is exclusive with \ref __NUCLEI_N_REV + */ +#define __NUCLEI_NX_REV (0x0100) +#endif /* __ONLY_FOR_DOXYGEN_DOCUMENT_GENERATION__ */ +/** @} */ /* End of Group NMSIS_Core_VersionControl */ + +#include "nmsis_compiler.h" /* NMSIS compiler specific defines */ + +/* === Include Nuclei Core Related Headers === */ +/* Include core base feature header file */ +#include "core_feature_base.h" + +#ifndef __NMSIS_GENERIC +/* Include core eclic feature header file */ +#include "core_feature_eclic.h" +/* Include core systimer feature header file */ +#include "core_feature_timer.h" +#endif + +/* Include core fpu feature header file */ +#include "core_feature_fpu.h" +/* Include core dsp feature header file */ +#include "core_feature_dsp.h" +/* Include core pmp feature header file */ +#include "core_feature_pmp.h" +/* Include core cache feature header file */ +#include "core_feature_cache.h" + +/* Include compatiable functions header file */ +#include "core_compatiable.h" + +#ifdef __cplusplus +} +#endif +#endif /* __NMSIS_CORE_H__ */ diff --git a/components/nmsis/core/inc/nmsis_gcc.h b/components/nmsis/core/inc/nmsis_gcc.h new file mode 100644 index 00000000..ac093e23 --- /dev/null +++ b/components/nmsis/core/inc/nmsis_gcc.h @@ -0,0 +1,269 @@ +/* + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __NMSIS_GCC_H__ +#define __NMSIS_GCC_H__ +/*! + * @file nmsis_gcc.h + * @brief NMSIS compiler GCC header file + */ +#include +#include "riscv_encoding.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ +/** + * \defgroup NMSIS_Core_CompilerControl Compiler Control + * \ingroup NMSIS_Core + * \brief Compiler agnostic \#define symbols for generic c/c++ source code + * \details + * + * The NMSIS-Core provides the header file nmsis_compiler.h with consistent \#define symbols for generate C or C++ source files that should be compiler agnostic. + * Each NMSIS compliant compiler should support the functionality described in this section. + * + * The header file nmsis_compiler.h is also included by each Device Header File so that these definitions are available. + * @{ + */ +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin +#define __has_builtin(x) (0) +#endif + +/* NMSIS compiler specific defines */ +/** \brief Pass information from the compiler to the assembler. */ +#ifndef __ASM +#define __ASM __asm +#endif + +/** \brief Recommend that function should be inlined by the compiler. */ +#ifndef __INLINE +#define __INLINE inline +#endif + +/** \brief Define a static function that may be inlined by the compiler. */ +#ifndef __STATIC_INLINE +#define __STATIC_INLINE static inline +#endif + +/** \brief Define a static function that should be always inlined by the compiler. */ +#ifndef __STATIC_FORCEINLINE +#define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif + +/** \brief Inform the compiler that a function does not return. */ +#ifndef __NO_RETURN +#define __NO_RETURN __attribute__((__noreturn__)) +#endif + +/** \brief Inform that a variable shall be retained in executable image. */ +#ifndef __USED +#define __USED __attribute__((used)) +#endif + +/** \brief restrict pointer qualifier to enable additional optimizations. */ +#ifndef __WEAK +#define __WEAK __attribute__((weak)) +#endif + +/** \brief specified the vector size of the variable, measured in bytes */ +#ifndef __VECTOR_SIZE +#define __VECTOR_SIZE(x) __attribute__((vector_size(x))) +#endif + +/** \brief Request smallest possible alignment. */ +#ifndef __PACKED +#define __PACKED __attribute__((packed, aligned(1))) +#endif + +/** \brief Request smallest possible alignment for a structure. */ +#ifndef __PACKED_STRUCT +#define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif + +/** \brief Request smallest possible alignment for a union. */ +#ifndef __PACKED_UNION +#define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpacked" +#pragma GCC diagnostic ignored "-Wattributes" +/** \brief Packed struct for unaligned uint16_t write access */ +__PACKED_STRUCT T_UINT16_WRITE +{ + uint16_t v; +}; +#pragma GCC diagnostic pop +/** \brief Pointer for unaligned write of a uint16_t variable. */ +#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpacked" +#pragma GCC diagnostic ignored "-Wattributes" +/** \brief Packed struct for unaligned uint16_t read access */ +__PACKED_STRUCT T_UINT16_READ +{ + uint16_t v; +}; +#pragma GCC diagnostic pop +/** \brief Pointer for unaligned read of a uint16_t variable. */ +#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpacked" +#pragma GCC diagnostic ignored "-Wattributes" +/** \brief Packed struct for unaligned uint32_t write access */ +__PACKED_STRUCT T_UINT32_WRITE +{ + uint32_t v; +}; +#pragma GCC diagnostic pop +/** \brief Pointer for unaligned write of a uint32_t variable. */ +#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpacked" +#pragma GCC diagnostic ignored "-Wattributes" +/** \brief Packed struct for unaligned uint32_t read access */ +__PACKED_STRUCT T_UINT32_READ +{ + uint32_t v; +}; +#pragma GCC diagnostic pop +/** \brief Pointer for unaligned read of a uint32_t variable. */ +#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif + +/** \brief Minimum `x` bytes alignment for a variable. */ +#ifndef __ALIGNED +#define __ALIGNED(x) __attribute__((aligned(x))) +#endif + +/** \brief restrict pointer qualifier to enable additional optimizations. */ +#ifndef __RESTRICT +#define __RESTRICT __restrict +#endif + +/** \brief Barrier to prevent compiler from reordering instructions. */ +#ifndef __COMPILER_BARRIER +#define __COMPILER_BARRIER() __ASM volatile("" :: \ + : "memory") +#endif + +/** \brief provide the compiler with branch prediction information, the branch is usually true */ +#ifndef __USUALLY +#define __USUALLY(exp) __builtin_expect((exp), 1) +#endif + +/** \brief provide the compiler with branch prediction information, the branch is rarely true */ +#ifndef __RARELY +#define __RARELY(exp) __builtin_expect((exp), 0) +#endif + +/** \brief Use this attribute to indicate that the specified function is an interrupt handler. */ +#ifndef __INTERRUPT +#define __INTERRUPT __attribute__((interrupt)) +#endif + +/** @} */ /* End of Doxygen Group NMSIS_Core_CompilerControl */ + +/* IO definitions (access restrictions to peripheral registers) */ +/** + * \defgroup NMSIS_Core_PeriphAccess Peripheral Access + * \brief Naming conventions and optional features for accessing peripherals. + * + * The section below describes the naming conventions, requirements, and optional features + * for accessing device specific peripherals. + * Most of the rules also apply to the core peripherals. + * + * The **Device Header File ** contains typically these definition + * and also includes the core specific header files. + * + * @{ + */ +/** \brief Defines 'read only' permissions */ +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif +/** \brief Defines 'write only' permissions */ +#define __O volatile +/** \brief Defines 'read / write' permissions */ +#define __IO volatile + +/* following defines should be used for structure members */ +/** \brief Defines 'read only' structure member permissions */ +#define __IM volatile const +/** \brief Defines 'write only' structure member permissions */ +#define __OM volatile +/** \brief Defines 'read/write' structure member permissions */ +#define __IOM volatile + +/** + * \brief Mask and shift a bit field value for use in a register bit range. + * \details The macro \ref _VAL2FLD uses the #define's _Pos and _Msk of the related bit + * field to shift bit-field values for assigning to a register. + * + * **Example**: + * \code + * ECLIC->CFG = _VAL2FLD(CLIC_CLICCFG_NLBIT, 3); + * \endcode + * \param[in] field Name of the register bit field. + * \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + * \return Masked and shifted value. + */ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field##_Pos) & field##_Msk) + +/** + * \brief Mask and shift a register value to extract a bit filed value. + * \details The macro \ref _FLD2VAL uses the #define's _Pos and _Msk of the related bit + * field to extract the value of a bit field from a register. + * + * **Example**: + * \code + * nlbits = _FLD2VAL(CLIC_CLICCFG_NLBIT, ECLIC->CFG); + * \endcode + * \param[in] field Name of the register bit field. + * \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + * \return Masked and shifted bit field value. + */ +#define _FLD2VAL(field, value) (((uint32_t)(value)&field##_Msk) >> field##_Pos) + + /** @} */ /* end of group NMSIS_Core_PeriphAccess */ + +#ifdef __cplusplus +} +#endif +#endif /* __NMSIS_GCC_H__ */ diff --git a/components/nmsis/core/inc/nmsis_version.h b/components/nmsis/core/inc/nmsis_version.h new file mode 100644 index 00000000..16507998 --- /dev/null +++ b/components/nmsis/core/inc/nmsis_version.h @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef __NMSIS_VERSION_H +#define __NMSIS_VERSION_H + +/** + * \defgroup NMSIS_Core_VersionControl Version Control + * \ingroup NMSIS_Core + * \brief Version \#define symbols for NMSIS release specific C/C++ source code + * \details + * + * We followed the [semantic versioning 2.0.0](https://semver.org/) to control NMSIS version. + * The version format is **MAJOR.MINOR.PATCH**, increment the: + * 1. MAJOR version when you make incompatible API changes, + * 2. MINOR version when you add functionality in a backwards compatible manner, and + * 3. PATCH version when you make backwards compatible bug fixes. + * + * The header file `nmsis_version.h` is included by each core header so that these definitions are available. + * + * **Example Usage for NMSIS Version Check**: + * \code + * #if defined(__NMSIS_VERSION) && (__NMSIS_VERSION >= 0x00010105) + * #warning "Yes, we have NMSIS 1.1.5 or later" + * #else + * #error "We need NMSIS 1.1.5 or later!" + * #endif + * \endcode + * + * @{ + */ + +/*! + * \file nmsis_version.h + * \brief NMSIS Version definitions + **/ + +/** + * \brief Represent the NMSIS major version + * \details + * The NMSIS major version can be used to + * differentiate between NMSIS major releases. + * */ +#define __NMSIS_VERSION_MAJOR (1U) + +/** + * \brief Represent the NMSIS minor version + * \details + * The NMSIS minor version can be used to + * query a NMSIS release update including new features. + * + **/ +#define __NMSIS_VERSION_MINOR (0U) + +/** + * \brief Represent the NMSIS patch version + * \details + * The NMSIS patch version can be used to + * show bug fixes in this package. + **/ +#define __NMSIS_VERSION_PATCH (1U) +/** + * \brief Represent the NMSIS Version + * \details + * NMSIS Version format: **MAJOR.MINOR.PATCH** + * * MAJOR: \ref __NMSIS_VERSION_MAJOR, stored in `bits [31:16]` of \ref __NMSIS_VERSION + * * MINOR: \ref __NMSIS_VERSION_MINOR, stored in `bits [15:8]` of \ref __NMSIS_VERSION + * * PATCH: \ref __NMSIS_VERSION_PATCH, stored in `bits [7:0]` of \ref __NMSIS_VERSION + **/ +#define __NMSIS_VERSION ((__NMSIS_VERSION_MAJOR << 16U) | (__NMSIS_VERSION_MINOR << 8) | __NMSIS_VERSION_PATCH) + +/** @} */ /* End of Doxygen Group NMSIS_Core_VersionControl */ +#endif diff --git a/components/nmsis/core/inc/riscv_bits.h b/components/nmsis/core/inc/riscv_bits.h new file mode 100644 index 00000000..fe0beb95 --- /dev/null +++ b/components/nmsis/core/inc/riscv_bits.h @@ -0,0 +1,94 @@ +/* + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef __RISCV_BITS_H__ +#define __RISCV_BITS_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +#if __riscv_xlen == 64 +# define SLL32 sllw +# define STORE sd +# define LOAD ld +# define LWU lwu +# define LOG_REGBYTES 3 +#else +# define SLL32 sll +# define STORE sw +# define LOAD lw +# define LWU lw +# define LOG_REGBYTES 2 +#endif /* __riscv_xlen */ + +#define REGBYTES (1 << LOG_REGBYTES) + +#if defined(__riscv_flen) +#if __riscv_flen == 64 +# define FPSTORE fsd +# define FPLOAD fld +# define LOG_FPREGBYTES 3 +#else +# define FPSTORE fsw +# define FPLOAD flw +# define LOG_FPREGBYTES 2 +#endif /* __riscv_flen == 64 */ +#define FPREGBYTES (1 << LOG_FPREGBYTES) +#endif /* __riscv_flen */ + +#define __rv_likely(x) __builtin_expect((x), 1) +#define __rv_unlikely(x) __builtin_expect((x), 0) + +#define __RV_ROUNDUP(a, b) ((((a)-1)/(b)+1)*(b)) +#define __RV_ROUNDDOWN(a, b) ((a)/(b)*(b)) + +#define __RV_MAX(a, b) ((a) > (b) ? (a) : (b)) +#define __RV_MIN(a, b) ((a) < (b) ? (a) : (b)) +#define __RV_CLAMP(a, lo, hi) MIN(MAX(a, lo), hi) + +#define __RV_EXTRACT_FIELD(val, which) (((val) & (which)) / ((which) & ~((which)-1))) +#define __RV_INSERT_FIELD(val, which, fieldval) (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1)))) + +#ifdef __ASSEMBLY__ +#define _AC(X,Y) X +#define _AT(T,X) X +#else +#define __AC(X,Y) (X##Y) +#define _AC(X,Y) __AC(X,Y) +#define _AT(T,X) ((T)(X)) +#endif /* __ASSEMBLY__ */ + +#define _UL(x) (_AC(x, UL)) +#define _ULL(x) (_AC(x, ULL)) + +#define _BITUL(x) (_UL(1) << (x)) +#define _BITULL(x) (_ULL(1) << (x)) + +#define UL(x) (_UL(x)) +#define ULL(x) (_ULL(x)) + +#define STR(x) XSTR(x) +#define XSTR(x) #x +#define __STR(s) #s +#define STRINGIFY(s) __STR(s) + +#ifdef __cplusplus +} +#endif + +#endif /** __RISCV_BITS_H__ */ diff --git a/components/nmsis/core/inc/riscv_encoding.h b/components/nmsis/core/inc/riscv_encoding.h new file mode 100644 index 00000000..a0ec9684 --- /dev/null +++ b/components/nmsis/core/inc/riscv_encoding.h @@ -0,0 +1,690 @@ +/* + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef __RISCV_ENCODING_H__ +#define __RISCV_ENCODING_H__ + +#include "riscv_bits.h" +#ifdef __cplusplus + extern "C" { +#endif +/** + * \defgroup NMSIS_Core_CSR_Encoding Core CSR Encodings + * \ingroup NMSIS_Core + * \brief NMSIS Core CSR Encodings + * \details + * + * The following macros are used for CSR encodings + * @{ + */ +/* === Standard CSR bit mask === */ +#define MSTATUS_UIE 0x00000001 +#define MSTATUS_SIE 0x00000002 +#define MSTATUS_HIE 0x00000004 +#define MSTATUS_MIE 0x00000008 +#define MSTATUS_UPIE 0x00000010 +#define MSTATUS_SPIE 0x00000020 +#define MSTATUS_HPIE 0x00000040 +#define MSTATUS_MPIE 0x00000080 +#define MSTATUS_SPP 0x00000100 +#define MSTATUS_MPP 0x00001800 +#define MSTATUS_FS 0x00006000 +#define MSTATUS_XS 0x00018000 +#define MSTATUS_MPRV 0x00020000 +#define MSTATUS_PUM 0x00040000 +#define MSTATUS_MXR 0x00080000 +#define MSTATUS_VM 0x1F000000 +#define MSTATUS32_SD 0x80000000 +#define MSTATUS64_SD 0x8000000000000000 + +#define MSTATUS_FS_INITIAL 0x00002000 +#define MSTATUS_FS_CLEAN 0x00004000 +#define MSTATUS_FS_DIRTY 0x00006000 + +#define SSTATUS_UIE 0x00000001 +#define SSTATUS_SIE 0x00000002 +#define SSTATUS_UPIE 0x00000010 +#define SSTATUS_SPIE 0x00000020 +#define SSTATUS_SPP 0x00000100 +#define SSTATUS_FS 0x00006000 +#define SSTATUS_XS 0x00018000 +#define SSTATUS_PUM 0x00040000 +#define SSTATUS32_SD 0x80000000 +#define SSTATUS64_SD 0x8000000000000000 + +#define CSR_MCACHE_CTL_IE 0x00000001 +#define CSR_MCACHE_CTL_DE 0x00010000 + +#define DCSR_XDEBUGVER (3U<<30) +#define DCSR_NDRESET (1<<29) +#define DCSR_FULLRESET (1<<28) +#define DCSR_EBREAKM (1<<15) +#define DCSR_EBREAKH (1<<14) +#define DCSR_EBREAKS (1<<13) +#define DCSR_EBREAKU (1<<12) +#define DCSR_STOPCYCLE (1<<10) +#define DCSR_STOPTIME (1<<9) +#define DCSR_CAUSE (7<<6) +#define DCSR_DEBUGINT (1<<5) +#define DCSR_HALT (1<<3) +#define DCSR_STEP (1<<2) +#define DCSR_PRV (3<<0) + +#define DCSR_CAUSE_NONE 0 +#define DCSR_CAUSE_SWBP 1 +#define DCSR_CAUSE_HWBP 2 +#define DCSR_CAUSE_DEBUGINT 3 +#define DCSR_CAUSE_STEP 4 +#define DCSR_CAUSE_HALT 5 + +#define MCONTROL_TYPE(xlen) (0xfULL<<((xlen)-4)) +#define MCONTROL_DMODE(xlen) (1ULL<<((xlen)-5)) +#define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11)) + +#define MCONTROL_SELECT (1<<19) +#define MCONTROL_TIMING (1<<18) +#define MCONTROL_ACTION (0x3f<<12) +#define MCONTROL_CHAIN (1<<11) +#define MCONTROL_MATCH (0xf<<7) +#define MCONTROL_M (1<<6) +#define MCONTROL_H (1<<5) +#define MCONTROL_S (1<<4) +#define MCONTROL_U (1<<3) +#define MCONTROL_EXECUTE (1<<2) +#define MCONTROL_STORE (1<<1) +#define MCONTROL_LOAD (1<<0) + +#define MCONTROL_TYPE_NONE 0 +#define MCONTROL_TYPE_MATCH 2 + +#define MCONTROL_ACTION_DEBUG_EXCEPTION 0 +#define MCONTROL_ACTION_DEBUG_MODE 1 +#define MCONTROL_ACTION_TRACE_START 2 +#define MCONTROL_ACTION_TRACE_STOP 3 +#define MCONTROL_ACTION_TRACE_EMIT 4 + +#define MCONTROL_MATCH_EQUAL 0 +#define MCONTROL_MATCH_NAPOT 1 +#define MCONTROL_MATCH_GE 2 +#define MCONTROL_MATCH_LT 3 +#define MCONTROL_MATCH_MASK_LOW 4 +#define MCONTROL_MATCH_MASK_HIGH 5 + +#define MIP_SSIP (1 << IRQ_S_SOFT) +#define MIP_HSIP (1 << IRQ_H_SOFT) +#define MIP_MSIP (1 << IRQ_M_SOFT) +#define MIP_STIP (1 << IRQ_S_TIMER) +#define MIP_HTIP (1 << IRQ_H_TIMER) +#define MIP_MTIP (1 << IRQ_M_TIMER) +#define MIP_SEIP (1 << IRQ_S_EXT) +#define MIP_HEIP (1 << IRQ_H_EXT) +#define MIP_MEIP (1 << IRQ_M_EXT) + +#define MIE_SSIE MIP_SSIP +#define MIE_HSIE MIP_HSIP +#define MIE_MSIE MIP_MSIP +#define MIE_STIE MIP_STIP +#define MIE_HTIE MIP_HTIP +#define MIE_MTIE MIP_MTIP +#define MIE_SEIE MIP_SEIP +#define MIE_HEIE MIP_HEIP +#define MIE_MEIE MIP_MEIP + +/* === P-ext CSR bit mask === */ + +#define UCODE_OV (0x1) + +/* === Nuclei custom CSR bit mask === */ + +#define WFE_WFE (0x1) +#define TXEVT_TXEVT (0x1) +#define SLEEPVALUE_SLEEPVALUE (0x1) + +#define MCOUNTINHIBIT_IR (1<<2) +#define MCOUNTINHIBIT_CY (1<<0) + +#define MILM_CTL_ILM_BPA (((1ULL<<((__riscv_xlen)-10))-1)<<10) +#define MILM_CTL_ILM_RWECC (1<<3) +#define MILM_CTL_ILM_ECC_EXCP_EN (1<<2) +#define MILM_CTL_ILM_ECC_EN (1<<1) +#define MILM_CTL_ILM_EN (1<<0) + +#define MDLM_CTL_DLM_BPA (((1ULL<<((__riscv_xlen)-10))-1)<<10) +#define MDLM_CTL_DLM_RWECC (1<<3) +#define MDLM_CTL_DLM_ECC_EXCP_EN (1<<2) +#define MDLM_CTL_DLM_ECC_EN (1<<1) +#define MDLM_CTL_DLM_EN (1<<0) + +#define MSUBM_PTYP (0x3<<8) +#define MSUBM_TYP (0x3<<6) + +#define MDCAUSE_MDCAUSE (0x3) + +#define MMISC_CTL_NMI_CAUSE_FFF (1<<9) +#define MMISC_CTL_MISALIGN (1<<6) +#define MMISC_CTL_BPU (1<<3) + +#define MCACHE_CTL_IC_EN (1<<0) +#define MCACHE_CTL_IC_SCPD_MOD (1<<1) +#define MCACHE_CTL_IC_ECC_EN (1<<2) +#define MCACHE_CTL_IC_ECC_EXCP_EN (1<<3) +#define MCACHE_CTL_IC_RWTECC (1<<4) +#define MCACHE_CTL_IC_RWDECC (1<<5) +#define MCACHE_CTL_DC_EN (1<<16) +#define MCACHE_CTL_DC_ECC_EN (1<<17) +#define MCACHE_CTL_DC_ECC_EXCP_EN (1<<18) +#define MCACHE_CTL_DC_RWTECC (1<<19) +#define MCACHE_CTL_DC_RWDECC (1<<20) + +#define MTVT2_MTVT2EN (1<<0) +#define MTVT2_COMMON_CODE_ENTRY (((1ULL<<((__riscv_xlen)-2))-1)<<2) + +#define MCFG_INFO_TEE (1<<0) +#define MCFG_INFO_ECC (1<<1) +#define MCFG_INFO_CLIC (1<<2) +#define MCFG_INFO_PLIC (1<<3) +#define MCFG_INFO_FIO (1<<4) +#define MCFG_INFO_PPI (1<<5) +#define MCFG_INFO_NICE (1<<6) +#define MCFG_INFO_ILM (1<<7) +#define MCFG_INFO_DLM (1<<8) +#define MCFG_INFO_ICACHE (1<<9) +#define MCFG_INFO_DCACHE (1<<10) + +#define MICFG_IC_SET (0xF<<0) +#define MICFG_IC_WAY (0x7<<4) +#define MICFG_IC_LSIZE (0x7<<7) +#define MICFG_IC_ECC (0x1<<10) +#define MICFG_ILM_SIZE (0x1F<<16) +#define MICFG_ILM_XONLY (0x1<<21) +#define MICFG_ILM_ECC (0x1<<22) + +#define MDCFG_DC_SET (0xF<<0) +#define MDCFG_DC_WAY (0x7<<4) +#define MDCFG_DC_LSIZE (0x7<<7) +#define MDCFG_DC_ECC (0x1<<10) +#define MDCFG_DLM_SIZE (0x1F<<16) +#define MDCFG_DLM_ECC (0x1<<21) + +#define MPPICFG_INFO_PPI_SIZE (0x1F<<1) +#define MPPICFG_INFO_PPI_BPA (((1ULL<<((__riscv_xlen)-10))-1)<<10) + +#define MFIOCFG_INFO_FIO_SIZE (0x1F<<1) +#define MFIOCFG_INFO_FIO_BPA (((1ULL<<((__riscv_xlen)-10))-1)<<10) + +#define MECC_LOCK_ECC_LOCK (0x1) + +#define MECC_CODE_CODE (0x1FF) +#define MECC_CODE_RAMID (0x1F<<16) +#define MECC_CODE_SRAMID (0x1F<<24) + +#define CCM_SUEN_SUEN (0x1<<0) +#define CCM_DATA_DATA (0x7<<0) +#define CCM_COMMAND_COMMAND (0x1F<<0) + +#define SIP_SSIP MIP_SSIP +#define SIP_STIP MIP_STIP + +#define PRV_U 0 +#define PRV_S 1 +#define PRV_H 2 +#define PRV_M 3 + +#define VM_MBARE 0 +#define VM_MBB 1 +#define VM_MBBID 2 +#define VM_SV32 8 +#define VM_SV39 9 +#define VM_SV48 10 + +#define IRQ_S_SOFT 1 +#define IRQ_H_SOFT 2 +#define IRQ_M_SOFT 3 +#define IRQ_S_TIMER 5 +#define IRQ_H_TIMER 6 +#define IRQ_M_TIMER 7 +#define IRQ_S_EXT 9 +#define IRQ_H_EXT 10 +#define IRQ_M_EXT 11 +#define IRQ_COP 12 +#define IRQ_HOST 13 + + +/* === FPU FRM Rounding Mode === */ +/** FPU Round to Nearest, ties to Even*/ +#define FRM_RNDMODE_RNE 0x0 +/** FPU Round Towards Zero */ +#define FRM_RNDMODE_RTZ 0x1 +/** FPU Round Down (towards -inf) */ +#define FRM_RNDMODE_RDN 0x2 +/** FPU Round Up (towards +inf) */ +#define FRM_RNDMODE_RUP 0x3 +/** FPU Round to nearest, ties to Max Magnitude */ +#define FRM_RNDMODE_RMM 0x4 +/** + * In instruction's rm, selects dynamic rounding mode. + * In Rounding Mode register, Invalid */ +#define FRM_RNDMODE_DYN 0x7 + +/* === FPU FFLAGS Accrued Exceptions === */ +/** FPU Inexact */ +#define FFLAGS_AE_NX (1<<0) +/** FPU Underflow */ +#define FFLAGS_AE_UF (1<<1) +/** FPU Overflow */ +#define FFLAGS_AE_OF (1<<2) +/** FPU Divide by Zero */ +#define FFLAGS_AE_DZ (1<<3) +/** FPU Invalid Operation */ +#define FFLAGS_AE_NV (1<<4) + +/** Floating Point Register f0-f31, eg. f0 -> FREG(0) */ +#define FREG(idx) f##idx + + +/* === PMP CFG Bits === */ +#define PMP_R 0x01 +#define PMP_W 0x02 +#define PMP_X 0x04 +#define PMP_A 0x18 +#define PMP_A_TOR 0x08 +#define PMP_A_NA4 0x10 +#define PMP_A_NAPOT 0x18 +#define PMP_L 0x80 + +#define PMP_SHIFT 2 +#define PMP_COUNT 16 + +// page table entry (PTE) fields +#define PTE_V 0x001 // Valid +#define PTE_R 0x002 // Read +#define PTE_W 0x004 // Write +#define PTE_X 0x008 // Execute +#define PTE_U 0x010 // User +#define PTE_G 0x020 // Global +#define PTE_A 0x040 // Accessed +#define PTE_D 0x080 // Dirty +#define PTE_SOFT 0x300 // Reserved for Software + +#define PTE_PPN_SHIFT 10 + +#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V) + +#ifdef __riscv + +#ifdef __riscv64 +# define MSTATUS_SD MSTATUS64_SD +# define SSTATUS_SD SSTATUS64_SD +# define RISCV_PGLEVEL_BITS 9 +#else +# define MSTATUS_SD MSTATUS32_SD +# define SSTATUS_SD SSTATUS32_SD +# define RISCV_PGLEVEL_BITS 10 +#endif /* __riscv64 */ + +#define RISCV_PGSHIFT 12 +#define RISCV_PGSIZE (1 << RISCV_PGSHIFT) + +#endif /* __riscv */ + +/** + * \defgroup NMSIS_Core_CSR_Registers Core CSR Registers + * \ingroup NMSIS_Core + * \brief NMSIS Core CSR Register Definitions + * \details + * + * The following macros are used for CSR Register Defintions. + * @{ + */ +/* === Standard RISC-V CSR Registers === */ +#define CSR_USTATUS 0x0 +#define CSR_FFLAGS 0x1 +#define CSR_FRM 0x2 +#define CSR_FCSR 0x3 +#define CSR_CYCLE 0xc00 +#define CSR_TIME 0xc01 +#define CSR_INSTRET 0xc02 +#define CSR_HPMCOUNTER3 0xc03 +#define CSR_HPMCOUNTER4 0xc04 +#define CSR_HPMCOUNTER5 0xc05 +#define CSR_HPMCOUNTER6 0xc06 +#define CSR_HPMCOUNTER7 0xc07 +#define CSR_HPMCOUNTER8 0xc08 +#define CSR_HPMCOUNTER9 0xc09 +#define CSR_HPMCOUNTER10 0xc0a +#define CSR_HPMCOUNTER11 0xc0b +#define CSR_HPMCOUNTER12 0xc0c +#define CSR_HPMCOUNTER13 0xc0d +#define CSR_HPMCOUNTER14 0xc0e +#define CSR_HPMCOUNTER15 0xc0f +#define CSR_HPMCOUNTER16 0xc10 +#define CSR_HPMCOUNTER17 0xc11 +#define CSR_HPMCOUNTER18 0xc12 +#define CSR_HPMCOUNTER19 0xc13 +#define CSR_HPMCOUNTER20 0xc14 +#define CSR_HPMCOUNTER21 0xc15 +#define CSR_HPMCOUNTER22 0xc16 +#define CSR_HPMCOUNTER23 0xc17 +#define CSR_HPMCOUNTER24 0xc18 +#define CSR_HPMCOUNTER25 0xc19 +#define CSR_HPMCOUNTER26 0xc1a +#define CSR_HPMCOUNTER27 0xc1b +#define CSR_HPMCOUNTER28 0xc1c +#define CSR_HPMCOUNTER29 0xc1d +#define CSR_HPMCOUNTER30 0xc1e +#define CSR_HPMCOUNTER31 0xc1f +#define CSR_SSTATUS 0x100 +#define CSR_SIE 0x104 +#define CSR_STVEC 0x105 +#define CSR_SSCRATCH 0x140 +#define CSR_SEPC 0x141 +#define CSR_SCAUSE 0x142 +#define CSR_SBADADDR 0x143 +#define CSR_SIP 0x144 +#define CSR_SPTBR 0x180 +#define CSR_MSTATUS 0x300 +#define CSR_MISA 0x301 +#define CSR_MEDELEG 0x302 +#define CSR_MIDELEG 0x303 +#define CSR_MIE 0x304 +#define CSR_MTVEC 0x305 +#define CSR_MCOUNTEREN 0x306 +#define CSR_MSCRATCH 0x340 +#define CSR_MEPC 0x341 +#define CSR_MCAUSE 0x342 +#define CSR_MBADADDR 0x343 +#define CSR_MTVAL 0x343 +#define CSR_MIP 0x344 +#define CSR_PMPCFG0 0x3a0 +#define CSR_PMPCFG1 0x3a1 +#define CSR_PMPCFG2 0x3a2 +#define CSR_PMPCFG3 0x3a3 +#define CSR_PMPADDR0 0x3b0 +#define CSR_PMPADDR1 0x3b1 +#define CSR_PMPADDR2 0x3b2 +#define CSR_PMPADDR3 0x3b3 +#define CSR_PMPADDR4 0x3b4 +#define CSR_PMPADDR5 0x3b5 +#define CSR_PMPADDR6 0x3b6 +#define CSR_PMPADDR7 0x3b7 +#define CSR_PMPADDR8 0x3b8 +#define CSR_PMPADDR9 0x3b9 +#define CSR_PMPADDR10 0x3ba +#define CSR_PMPADDR11 0x3bb +#define CSR_PMPADDR12 0x3bc +#define CSR_PMPADDR13 0x3bd +#define CSR_PMPADDR14 0x3be +#define CSR_PMPADDR15 0x3bf +#define CSR_TSELECT 0x7a0 +#define CSR_TDATA1 0x7a1 +#define CSR_TDATA2 0x7a2 +#define CSR_TDATA3 0x7a3 +#define CSR_DCSR 0x7b0 +#define CSR_DPC 0x7b1 +#define CSR_DSCRATCH 0x7b2 +#define CSR_MCYCLE 0xb00 +#define CSR_MINSTRET 0xb02 +#define CSR_MHPMCOUNTER3 0xb03 +#define CSR_MHPMCOUNTER4 0xb04 +#define CSR_MHPMCOUNTER5 0xb05 +#define CSR_MHPMCOUNTER6 0xb06 +#define CSR_MHPMCOUNTER7 0xb07 +#define CSR_MHPMCOUNTER8 0xb08 +#define CSR_MHPMCOUNTER9 0xb09 +#define CSR_MHPMCOUNTER10 0xb0a +#define CSR_MHPMCOUNTER11 0xb0b +#define CSR_MHPMCOUNTER12 0xb0c +#define CSR_MHPMCOUNTER13 0xb0d +#define CSR_MHPMCOUNTER14 0xb0e +#define CSR_MHPMCOUNTER15 0xb0f +#define CSR_MHPMCOUNTER16 0xb10 +#define CSR_MHPMCOUNTER17 0xb11 +#define CSR_MHPMCOUNTER18 0xb12 +#define CSR_MHPMCOUNTER19 0xb13 +#define CSR_MHPMCOUNTER20 0xb14 +#define CSR_MHPMCOUNTER21 0xb15 +#define CSR_MHPMCOUNTER22 0xb16 +#define CSR_MHPMCOUNTER23 0xb17 +#define CSR_MHPMCOUNTER24 0xb18 +#define CSR_MHPMCOUNTER25 0xb19 +#define CSR_MHPMCOUNTER26 0xb1a +#define CSR_MHPMCOUNTER27 0xb1b +#define CSR_MHPMCOUNTER28 0xb1c +#define CSR_MHPMCOUNTER29 0xb1d +#define CSR_MHPMCOUNTER30 0xb1e +#define CSR_MHPMCOUNTER31 0xb1f +#define CSR_MUCOUNTEREN 0x320 +#define CSR_MSCOUNTEREN 0x321 +#define CSR_MHPMEVENT3 0x323 +#define CSR_MHPMEVENT4 0x324 +#define CSR_MHPMEVENT5 0x325 +#define CSR_MHPMEVENT6 0x326 +#define CSR_MHPMEVENT7 0x327 +#define CSR_MHPMEVENT8 0x328 +#define CSR_MHPMEVENT9 0x329 +#define CSR_MHPMEVENT10 0x32a +#define CSR_MHPMEVENT11 0x32b +#define CSR_MHPMEVENT12 0x32c +#define CSR_MHPMEVENT13 0x32d +#define CSR_MHPMEVENT14 0x32e +#define CSR_MHPMEVENT15 0x32f +#define CSR_MHPMEVENT16 0x330 +#define CSR_MHPMEVENT17 0x331 +#define CSR_MHPMEVENT18 0x332 +#define CSR_MHPMEVENT19 0x333 +#define CSR_MHPMEVENT20 0x334 +#define CSR_MHPMEVENT21 0x335 +#define CSR_MHPMEVENT22 0x336 +#define CSR_MHPMEVENT23 0x337 +#define CSR_MHPMEVENT24 0x338 +#define CSR_MHPMEVENT25 0x339 +#define CSR_MHPMEVENT26 0x33a +#define CSR_MHPMEVENT27 0x33b +#define CSR_MHPMEVENT28 0x33c +#define CSR_MHPMEVENT29 0x33d +#define CSR_MHPMEVENT30 0x33e +#define CSR_MHPMEVENT31 0x33f +#define CSR_MVENDORID 0xf11 +#define CSR_MARCHID 0xf12 +#define CSR_MIMPID 0xf13 +#define CSR_MHARTID 0xf14 +#define CSR_CYCLEH 0xc80 +#define CSR_TIMEH 0xc81 +#define CSR_INSTRETH 0xc82 +#define CSR_HPMCOUNTER3H 0xc83 +#define CSR_HPMCOUNTER4H 0xc84 +#define CSR_HPMCOUNTER5H 0xc85 +#define CSR_HPMCOUNTER6H 0xc86 +#define CSR_HPMCOUNTER7H 0xc87 +#define CSR_HPMCOUNTER8H 0xc88 +#define CSR_HPMCOUNTER9H 0xc89 +#define CSR_HPMCOUNTER10H 0xc8a +#define CSR_HPMCOUNTER11H 0xc8b +#define CSR_HPMCOUNTER12H 0xc8c +#define CSR_HPMCOUNTER13H 0xc8d +#define CSR_HPMCOUNTER14H 0xc8e +#define CSR_HPMCOUNTER15H 0xc8f +#define CSR_HPMCOUNTER16H 0xc90 +#define CSR_HPMCOUNTER17H 0xc91 +#define CSR_HPMCOUNTER18H 0xc92 +#define CSR_HPMCOUNTER19H 0xc93 +#define CSR_HPMCOUNTER20H 0xc94 +#define CSR_HPMCOUNTER21H 0xc95 +#define CSR_HPMCOUNTER22H 0xc96 +#define CSR_HPMCOUNTER23H 0xc97 +#define CSR_HPMCOUNTER24H 0xc98 +#define CSR_HPMCOUNTER25H 0xc99 +#define CSR_HPMCOUNTER26H 0xc9a +#define CSR_HPMCOUNTER27H 0xc9b +#define CSR_HPMCOUNTER28H 0xc9c +#define CSR_HPMCOUNTER29H 0xc9d +#define CSR_HPMCOUNTER30H 0xc9e +#define CSR_HPMCOUNTER31H 0xc9f +#define CSR_MCYCLEH 0xb80 +#define CSR_MINSTRETH 0xb82 +#define CSR_MHPMCOUNTER3H 0xb83 +#define CSR_MHPMCOUNTER4H 0xb84 +#define CSR_MHPMCOUNTER5H 0xb85 +#define CSR_MHPMCOUNTER6H 0xb86 +#define CSR_MHPMCOUNTER7H 0xb87 +#define CSR_MHPMCOUNTER8H 0xb88 +#define CSR_MHPMCOUNTER9H 0xb89 +#define CSR_MHPMCOUNTER10H 0xb8a +#define CSR_MHPMCOUNTER11H 0xb8b +#define CSR_MHPMCOUNTER12H 0xb8c +#define CSR_MHPMCOUNTER13H 0xb8d +#define CSR_MHPMCOUNTER14H 0xb8e +#define CSR_MHPMCOUNTER15H 0xb8f +#define CSR_MHPMCOUNTER16H 0xb90 +#define CSR_MHPMCOUNTER17H 0xb91 +#define CSR_MHPMCOUNTER18H 0xb92 +#define CSR_MHPMCOUNTER19H 0xb93 +#define CSR_MHPMCOUNTER20H 0xb94 +#define CSR_MHPMCOUNTER21H 0xb95 +#define CSR_MHPMCOUNTER22H 0xb96 +#define CSR_MHPMCOUNTER23H 0xb97 +#define CSR_MHPMCOUNTER24H 0xb98 +#define CSR_MHPMCOUNTER25H 0xb99 +#define CSR_MHPMCOUNTER26H 0xb9a +#define CSR_MHPMCOUNTER27H 0xb9b +#define CSR_MHPMCOUNTER28H 0xb9c +#define CSR_MHPMCOUNTER29H 0xb9d +#define CSR_MHPMCOUNTER30H 0xb9e +#define CSR_MHPMCOUNTER31H 0xb9f + +/* === TEE CSR Registers === */ +#define CSR_SPMPCFG0 0x1A0 +#define CSR_SPMPCFG1 0x1A1 +#define CSR_SPMPCFG2 0x1A2 +#define CSR_SPMPCFG3 0x1A3 +#define CSR_SPMPADDR0 0x1B0 +#define CSR_SPMPADDR1 0x1B1 +#define CSR_SPMPADDR2 0x1B2 +#define CSR_SPMPADDR3 0x1B3 +#define CSR_SPMPADDR4 0x1B4 +#define CSR_SPMPADDR5 0x1B5 +#define CSR_SPMPADDR6 0x1B6 +#define CSR_SPMPADDR7 0x1B7 +#define CSR_SPMPADDR8 0x1B8 +#define CSR_SPMPADDR9 0x1B9 +#define CSR_SPMPADDR10 0x1BA +#define CSR_SPMPADDR11 0x1BB +#define CSR_SPMPADDR12 0x1BC +#define CSR_SPMPADDR13 0x1BD +#define CSR_SPMPADDR14 0x1BE +#define CSR_SPMPADDR15 0x1BF + +#define CSR_JALSNXTI 0x947 +#define CSR_STVT2 0x948 +#define CSR_PUSHSCAUSE 0x949 +#define CSR_PUSHSEPC 0x94A + + +/* === CLIC CSR Registers === */ +#define CSR_MTVT 0x307 +#define CSR_MNXTI 0x345 +#define CSR_MINTSTATUS 0x346 +#define CSR_MSCRATCHCSW 0x348 +#define CSR_MSCRATCHCSWL 0x349 +#define CSR_MCLICBASE 0x350 + +/* === P-Extension Registers === */ +#define CSR_UCODE 0x801 + +/* === Nuclei custom CSR Registers === */ +#define CSR_MCOUNTINHIBIT 0x320 +#define CSR_MILM_CTL 0x7C0 +#define CSR_MDLM_CTL 0x7C1 +#define CSR_MECC_CODE 0x7C2 +#define CSR_MNVEC 0x7C3 +#define CSR_MSUBM 0x7C4 +#define CSR_MDCAUSE 0x7C9 +#define CSR_MCACHE_CTL 0x7CA +#define CSR_MMISC_CTL 0x7D0 +#define CSR_MSAVESTATUS 0x7D6 +#define CSR_MSAVEEPC1 0x7D7 +#define CSR_MSAVECAUSE1 0x7D8 +#define CSR_MSAVEEPC2 0x7D9 +#define CSR_MSAVECAUSE2 0x7DA +#define CSR_MSAVEDCAUSE1 0x7DB +#define CSR_MSAVEDCAUSE2 0x7DC +#define CSR_MTLB_CTL 0x7DD +#define CSR_MECC_LOCK 0x7DE +#define CSR_MFP16MODE 0x7E2 +#define CSR_LSTEPFORC 0x7E9 +#define CSR_PUSHMSUBM 0x7EB +#define CSR_MTVT2 0x7EC +#define CSR_JALMNXTI 0x7ED +#define CSR_PUSHMCAUSE 0x7EE +#define CSR_PUSHMEPC 0x7EF +#define CSR_MPPICFG_INFO 0x7F0 +#define CSR_MFIOCFG_INFO 0x7F1 +#define CSR_MSMPCFG_INFO 0x7F7 +#define CSR_SLEEPVALUE 0x811 +#define CSR_TXEVT 0x812 +#define CSR_WFE 0x810 +#define CSR_MICFG_INFO 0xFC0 +#define CSR_MDCFG_INFO 0xFC1 +#define CSR_MCFG_INFO 0xFC2 +#define CSR_MTLBCFG_INFO 0xFC3 + +/* === Nuclei CCM Registers === */ +#define CSR_CCM_MBEGINADDR 0x7CB +#define CSR_CCM_MCOMMAND 0x7CC +#define CSR_CCM_MDATA 0x7CD +#define CSR_CCM_SUEN 0x7CE +#define CSR_CCM_SBEGINADDR 0x5CB +#define CSR_CCM_SCOMMAND 0x5CC +#define CSR_CCM_SDATA 0x5CD +#define CSR_CCM_UBEGINADDR 0x4CB +#define CSR_CCM_UCOMMAND 0x4CC +#define CSR_CCM_UDATA 0x4CD +#define CSR_CCM_FPIPE 0x4CF + +/** @} */ /** End of Doxygen Group NMSIS_Core_CSR_Registers **/ + +/* Exception Code in MCAUSE CSR */ +#define CAUSE_MISALIGNED_FETCH 0x0 +#define CAUSE_FAULT_FETCH 0x1 +#define CAUSE_ILLEGAL_INSTRUCTION 0x2 +#define CAUSE_BREAKPOINT 0x3 +#define CAUSE_MISALIGNED_LOAD 0x4 +#define CAUSE_FAULT_LOAD 0x5 +#define CAUSE_MISALIGNED_STORE 0x6 +#define CAUSE_FAULT_STORE 0x7 +#define CAUSE_USER_ECALL 0x8 +#define CAUSE_SUPERVISOR_ECALL 0x9 +#define CAUSE_HYPERVISOR_ECALL 0xa +#define CAUSE_MACHINE_ECALL 0xb + +/* Exception Subcode in MDCAUSE CSR */ +#define DCAUSE_FAULT_FETCH_PMP 0x1 +#define DCAUSE_FAULT_FETCH_INST 0x2 + +#define DCAUSE_FAULT_LOAD_PMP 0x1 +#define DCAUSE_FAULT_LOAD_INST 0x2 +#define DCAUSE_FAULT_LOAD_NICE 0x3 + +#define DCAUSE_FAULT_STORE_PMP 0x1 +#define DCAUSE_FAULT_STORE_INST 0x2 + +/** @} */ /** End of Doxygen Group NMSIS_Core_CSR_Encoding **/ + +#ifdef __cplusplus +} +#endif +#endif /* __RISCV_ENCODING_H__ */ diff --git a/components/nmsis/dsp/inc/dsp/basic_math_functions.h b/components/nmsis/dsp/inc/dsp/basic_math_functions.h new file mode 100644 index 00000000..3d32e388 --- /dev/null +++ b/components/nmsis/dsp/inc/dsp/basic_math_functions.h @@ -0,0 +1,765 @@ +/****************************************************************************** + * @file basic_math_functions.h + * @brief Public header file for NMSIS DSP Library + * @version V1.9.0 + * @date 23 April 2021 + * Target Processor: RISC-V Cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _BASIC_MATH_FUNCTIONS_H_ +#define _BASIC_MATH_FUNCTIONS_H_ + +#include "riscv_math_types.h" +#include "riscv_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" + + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + * @defgroup groupMath Basic Math Functions + */ + + /** + * @brief Q7 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void riscv_mult_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void riscv_mult_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void riscv_mult_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void riscv_mult_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + + /** + * @brief Floating-point vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void riscv_add_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + + /** + * @brief Q7 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void riscv_add_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void riscv_add_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void riscv_add_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void riscv_sub_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + + /** + * @brief Q7 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void riscv_sub_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void riscv_sub_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void riscv_sub_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void riscv_scale_f32( + const float32_t * pSrc, + float32_t scale, + float32_t * pDst, + uint32_t blockSize); + + + + /** + * @brief Multiplies a Q7 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void riscv_scale_q7( + const q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q15 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void riscv_scale_q15( + const q15_t * pSrc, + q15_t scaleFract, + int8_t shift, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q31 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void riscv_scale_q31( + const q31_t * pSrc, + q31_t scaleFract, + int8_t shift, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void riscv_abs_q7( + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void riscv_abs_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + + + /** + * @brief Q15 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void riscv_abs_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void riscv_abs_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Dot product of floating-point vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void riscv_dot_prod_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + uint32_t blockSize, + float32_t * result); + + + + /** + * @brief Dot product of Q7 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void riscv_dot_prod_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + uint32_t blockSize, + q31_t * result); + + + /** + * @brief Dot product of Q15 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void riscv_dot_prod_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Dot product of Q31 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void riscv_dot_prod_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Shifts the elements of a Q7 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void riscv_shift_q7( + const q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q15 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void riscv_shift_q15( + const q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q31 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void riscv_shift_q31( + const q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void riscv_offset_f32( + const float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize); + + + + /** + * @brief Adds a constant offset to a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void riscv_offset_q7( + const q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void riscv_offset_q15( + const q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void riscv_offset_q31( + const q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void riscv_negate_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void riscv_negate_q7( + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void riscv_negate_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void riscv_negate_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + +/** + * @brief Compute the logical bitwise AND of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void riscv_and_u16( + const uint16_t * pSrcA, + const uint16_t * pSrcB, + uint16_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise AND of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void riscv_and_u32( + const uint32_t * pSrcA, + const uint32_t * pSrcB, + uint32_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise AND of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void riscv_and_u8( + const uint8_t * pSrcA, + const uint8_t * pSrcB, + uint8_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise OR of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void riscv_or_u16( + const uint16_t * pSrcA, + const uint16_t * pSrcB, + uint16_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise OR of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void riscv_or_u32( + const uint32_t * pSrcA, + const uint32_t * pSrcB, + uint32_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise OR of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void riscv_or_u8( + const uint8_t * pSrcA, + const uint8_t * pSrcB, + uint8_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise NOT of a fixed-point vector. + * @param[in] pSrc points to input vector + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void riscv_not_u16( + const uint16_t * pSrc, + uint16_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise NOT of a fixed-point vector. + * @param[in] pSrc points to input vector + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void riscv_not_u32( + const uint32_t * pSrc, + uint32_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise NOT of a fixed-point vector. + * @param[in] pSrc points to input vector + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void riscv_not_u8( + const uint8_t * pSrc, + uint8_t * pDst, + uint32_t blockSize); + +/** + * @brief Compute the logical bitwise XOR of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void riscv_xor_u16( + const uint16_t * pSrcA, + const uint16_t * pSrcB, + uint16_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise XOR of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void riscv_xor_u32( + const uint32_t * pSrcA, + const uint32_t * pSrcB, + uint32_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise XOR of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void riscv_xor_u8( + const uint8_t * pSrcA, + const uint8_t * pSrcB, + uint8_t * pDst, + uint32_t blockSize); + + /** + @brief Elementwise floating-point clipping + @param[in] pSrc points to input values + @param[out] pDst points to output clipped values + @param[in] low lower bound + @param[in] high higher bound + @param[in] numSamples number of samples to clip + @return none + */ + +void riscv_clip_f32(const float32_t * pSrc, + float32_t * pDst, + float32_t low, + float32_t high, + uint32_t numSamples); + + /** + @brief Elementwise fixed-point clipping + @param[in] pSrc points to input values + @param[out] pDst points to output clipped values + @param[in] low lower bound + @param[in] high higher bound + @param[in] numSamples number of samples to clip + @return none + */ + +void riscv_clip_q31(const q31_t * pSrc, + q31_t * pDst, + q31_t low, + q31_t high, + uint32_t numSamples); + + /** + @brief Elementwise fixed-point clipping + @param[in] pSrc points to input values + @param[out] pDst points to output clipped values + @param[in] low lower bound + @param[in] high higher bound + @param[in] numSamples number of samples to clip + @return none + */ + +void riscv_clip_q15(const q15_t * pSrc, + q15_t * pDst, + q15_t low, + q15_t high, + uint32_t numSamples); + + /** + @brief Elementwise fixed-point clipping + @param[in] pSrc points to input values + @param[out] pDst points to output clipped values + @param[in] low lower bound + @param[in] high higher bound + @param[in] numSamples number of samples to clip + @return none + */ + +void riscv_clip_q7(const q7_t * pSrc, + q7_t * pDst, + q7_t low, + q7_t high, + uint32_t numSamples); + + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _BASIC_MATH_FUNCTIONS_H_ */ diff --git a/components/nmsis/dsp/inc/dsp/basic_math_functions_f16.h b/components/nmsis/dsp/inc/dsp/basic_math_functions_f16.h new file mode 100644 index 00000000..c8afbe3d --- /dev/null +++ b/components/nmsis/dsp/inc/dsp/basic_math_functions_f16.h @@ -0,0 +1,169 @@ +/****************************************************************************** + * @file basic_math_functions_f16.h + * @brief Public header file for NMSIS DSP Library + * @version V1.9.0 + * @date 23 April 2021 + * Target Processor: RISC-V Cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _BASIC_MATH_FUNCTIONS_F16_H_ +#define _BASIC_MATH_FUNCTIONS_F16_H_ + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "riscv_math_types_f16.h" +#include "riscv_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" + + +#if defined(RISCV_FLOAT16_SUPPORTED) + + + /** + * @brief Floating-point vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void riscv_add_f16( + const float16_t * pSrcA, + const float16_t * pSrcB, + float16_t * pDst, + uint32_t blockSize); + + /** + * @brief Floating-point vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void riscv_sub_f16( + const float16_t * pSrcA, + const float16_t * pSrcB, + float16_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void riscv_scale_f16( + const float16_t * pSrc, + float16_t scale, + float16_t * pDst, + uint32_t blockSize); + + /** + * @brief Floating-point vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void riscv_abs_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void riscv_offset_f16( + const float16_t * pSrc, + float16_t offset, + float16_t * pDst, + uint32_t blockSize); + + /** + * @brief Dot product of floating-point vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void riscv_dot_prod_f16( + const float16_t * pSrcA, + const float16_t * pSrcB, + uint32_t blockSize, + float16_t * result); + + /** + * @brief Floating-point vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void riscv_mult_f16( + const float16_t * pSrcA, + const float16_t * pSrcB, + float16_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void riscv_negate_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize); + + /** + @brief Elementwise floating-point clipping + @param[in] pSrc points to input values + @param[out] pDst points to output clipped values + @param[in] low lower bound + @param[in] high higher bound + @param[in] numSamples number of samples to clip + @return none + */ + +void riscv_clip_f16(const float16_t * pSrc, + float16_t * pDst, + float16_t low, + float16_t high, + uint32_t numSamples); + +#endif /* defined(RISCV_FLOAT16_SUPPORTED)*/ + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _BASIC_MATH_FUNCTIONS_F16_H_ */ diff --git a/components/nmsis/dsp/inc/dsp/bayes_functions.h b/components/nmsis/dsp/inc/dsp/bayes_functions.h new file mode 100644 index 00000000..63c4de0f --- /dev/null +++ b/components/nmsis/dsp/inc/dsp/bayes_functions.h @@ -0,0 +1,90 @@ +/****************************************************************************** + * @file bayes_functions.h + * @brief Public header file for NMSIS DSP Library + * @version V1.9.0 + * @date 23 April 2021 + * Target Processor: RISC-V Cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _BAYES_FUNCTIONS_H_ +#define _BAYES_FUNCTIONS_H_ + +#include "riscv_math_types.h" +#include "riscv_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" + +#include "dsp/statistics_functions.h" + +/** + * @defgroup groupBayes Bayesian estimators + * + * Implement the naive gaussian Bayes estimator. + * The training must be done from scikit-learn. + * + * The parameters can be easily + * generated from the scikit-learn object. Some examples are given in + * DSP/Testing/PatternGeneration/Bayes.py + */ + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + * @brief Instance structure for Naive Gaussian Bayesian estimator. + */ +typedef struct +{ + uint32_t vectorDimension; /**< Dimension of vector space */ + uint32_t numberOfClasses; /**< Number of different classes */ + const float32_t *theta; /**< Mean values for the Gaussians */ + const float32_t *sigma; /**< Variances for the Gaussians */ + const float32_t *classPriors; /**< Class prior probabilities */ + float32_t epsilon; /**< Additive value to variances */ +} riscv_gaussian_naive_bayes_instance_f32; + +/** + * @brief Naive Gaussian Bayesian Estimator + * + * @param[in] S points to a naive bayes instance structure + * @param[in] in points to the elements of the input vector. + * @param[out] *pOutputProbabilities points to a buffer of length numberOfClasses containing estimated probabilities + * @param[out] *pBufferB points to a temporary buffer of length numberOfClasses + * @return The predicted class + * + */ + + +uint32_t riscv_gaussian_naive_bayes_predict_f32(const riscv_gaussian_naive_bayes_instance_f32 *S, + const float32_t * in, + float32_t *pOutputProbabilities, + float32_t *pBufferB); + + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _BAYES_FUNCTIONS_H_ */ diff --git a/components/nmsis/dsp/inc/dsp/bayes_functions_f16.h b/components/nmsis/dsp/inc/dsp/bayes_functions_f16.h new file mode 100644 index 00000000..c9997c78 --- /dev/null +++ b/components/nmsis/dsp/inc/dsp/bayes_functions_f16.h @@ -0,0 +1,81 @@ +/****************************************************************************** + * @file bayes_functions_f16.h + * @brief Public header file for NMSIS DSP Library + * @version V1.9.0 + * @date 23 April 2021 + * Target Processor: RISC-V Cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _BAYES_FUNCTIONS_F16_H_ +#define _BAYES_FUNCTIONS_F16_H_ + +#include "riscv_math_types_f16.h" +#include "riscv_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" + +#include "dsp/statistics_functions_f16.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if defined(RISCV_FLOAT16_SUPPORTED) + +/** + * @brief Instance structure for Naive Gaussian Bayesian estimator. + */ +typedef struct +{ + uint32_t vectorDimension; /**< Dimension of vector space */ + uint32_t numberOfClasses; /**< Number of different classes */ + const float16_t *theta; /**< Mean values for the Gaussians */ + const float16_t *sigma; /**< Variances for the Gaussians */ + const float16_t *classPriors; /**< Class prior probabilities */ + float16_t epsilon; /**< Additive value to variances */ +} riscv_gaussian_naive_bayes_instance_f16; + +/** + * @brief Naive Gaussian Bayesian Estimator + * + * @param[in] S points to a naive bayes instance structure + * @param[in] in points to the elements of the input vector. + * @param[out] *pOutputProbabilities points to a buffer of length numberOfClasses containing estimated probabilities + * @param[out] *pBufferB points to a temporary buffer of length numberOfClasses + * @return The predicted class + * + */ + + +uint32_t riscv_gaussian_naive_bayes_predict_f16(const riscv_gaussian_naive_bayes_instance_f16 *S, + const float16_t * in, + float16_t *pOutputProbabilities, + float16_t *pBufferB); + +#endif /*defined(RISCV_FLOAT16_SUPPORTED)*/ +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _BAYES_FUNCTIONS_F16_H_ */ diff --git a/components/nmsis/dsp/inc/dsp/complex_math_functions.h b/components/nmsis/dsp/inc/dsp/complex_math_functions.h new file mode 100644 index 00000000..bf323846 --- /dev/null +++ b/components/nmsis/dsp/inc/dsp/complex_math_functions.h @@ -0,0 +1,296 @@ +/****************************************************************************** + * @file complex_math_functions.h + * @brief Public header file for NMSIS DSP Library + * @version V1.9.0 + * @date 23 April 2021 + * Target Processor: RISC-V Cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _COMPLEX_MATH_FUNCTIONS_H_ +#define _COMPLEX_MATH_FUNCTIONS_H_ + +#include "riscv_math_types.h" +#include "riscv_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" +#include "dsp/fast_math_functions.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + * @defgroup groupCmplxMath Complex Math Functions + * This set of functions operates on complex data vectors. + * The data in the complex arrays is stored in an interleaved fashion + * (real, imag, real, imag, ...). + * In the API functions, the number of samples in a complex array refers + * to the number of complex values; the array contains twice this number of + * real values. + */ + + /** + * @brief Floating-point complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void riscv_cmplx_conj_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void riscv_cmplx_conj_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void riscv_cmplx_conj_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void riscv_cmplx_mag_squared_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void riscv_cmplx_mag_squared_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void riscv_cmplx_mag_squared_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + +/** + * @brief Floating-point complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void riscv_cmplx_mag_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void riscv_cmplx_mag_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void riscv_cmplx_mag_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void riscv_cmplx_dot_prod_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + uint32_t numSamples, + q31_t * realResult, + q31_t * imagResult); + + + /** + * @brief Q31 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void riscv_cmplx_dot_prod_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + uint32_t numSamples, + q63_t * realResult, + q63_t * imagResult); + + + /** + * @brief Floating-point complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void riscv_cmplx_dot_prod_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + uint32_t numSamples, + float32_t * realResult, + float32_t * imagResult); + + + /** + * @brief Q15 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void riscv_cmplx_mult_real_q15( + const q15_t * pSrcCmplx, + const q15_t * pSrcReal, + q15_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void riscv_cmplx_mult_real_q31( + const q31_t * pSrcCmplx, + const q31_t * pSrcReal, + q31_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void riscv_cmplx_mult_real_f32( + const float32_t * pSrcCmplx, + const float32_t * pSrcReal, + float32_t * pCmplxDst, + uint32_t numSamples); + + /** + * @brief Q15 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void riscv_cmplx_mult_cmplx_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void riscv_cmplx_mult_cmplx_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void riscv_cmplx_mult_cmplx_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples); + + + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _COMPLEX_MATH_FUNCTIONS_H_ */ diff --git a/components/nmsis/dsp/inc/dsp/complex_math_functions_f16.h b/components/nmsis/dsp/inc/dsp/complex_math_functions_f16.h new file mode 100644 index 00000000..5ee48828 --- /dev/null +++ b/components/nmsis/dsp/inc/dsp/complex_math_functions_f16.h @@ -0,0 +1,124 @@ +/****************************************************************************** + * @file complex_math_functions_f16.h + * @brief Public header file for NMSIS DSP Library + * @version V1.9.0 + * @date 23 April 2021 + * Target Processor: RISC-V Cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _COMPLEX_MATH_FUNCTIONS_F16_H_ +#define _COMPLEX_MATH_FUNCTIONS_F16_H_ + +#include "riscv_math_types_f16.h" +#include "riscv_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" +#include "dsp/fast_math_functions_f16.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if defined(RISCV_FLOAT16_SUPPORTED) + + /** + * @brief Floating-point complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void riscv_cmplx_conj_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t numSamples); + + /** + * @brief Floating-point complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void riscv_cmplx_mag_squared_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t numSamples); + + /** + * @brief Floating-point complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void riscv_cmplx_mag_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t numSamples); + + /** + * @brief Floating-point complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void riscv_cmplx_dot_prod_f16( + const float16_t * pSrcA, + const float16_t * pSrcB, + uint32_t numSamples, + float16_t * realResult, + float16_t * imagResult); + + /** + * @brief Floating-point complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void riscv_cmplx_mult_real_f16( + const float16_t * pSrcCmplx, + const float16_t * pSrcReal, + float16_t * pCmplxDst, + uint32_t numSamples); + + /** + * @brief Floating-point complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void riscv_cmplx_mult_cmplx_f16( + const float16_t * pSrcA, + const float16_t * pSrcB, + float16_t * pDst, + uint32_t numSamples); + +#endif /*defined(RISCV_FLOAT16_SUPPORTED)*/ +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _COMPLEX_MATH_FUNCTIONS_F16_H_ */ diff --git a/components/nmsis/dsp/inc/dsp/controller_functions.h b/components/nmsis/dsp/inc/dsp/controller_functions.h new file mode 100644 index 00000000..9fc71b42 --- /dev/null +++ b/components/nmsis/dsp/inc/dsp/controller_functions.h @@ -0,0 +1,792 @@ +/****************************************************************************** + * @file controller_functions.h + * @brief Public header file for NMSIS DSP Library + * @version V1.9.0 + * @date 23 April 2021 + * Target Processor: RISC-V Cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _CONTROLLER_FUNCTIONS_H_ +#define _CONTROLLER_FUNCTIONS_H_ + +#include "riscv_math_types.h" +#include "riscv_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + + /** + * @brief Macros required for SINE and COSINE Controller functions + */ + +#define CONTROLLER_Q31_SHIFT (32 - 9) + /* 1.31(q31) Fixed value of 2/360 */ + /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ +#define INPUT_SPACING 0xB60B61 + +/** + * @defgroup groupController Controller Functions + */ + + + /** + * @ingroup groupController + */ + + /** + * @addtogroup SinCos + * @{ + */ + +/** + * @brief Floating-point sin_cos function. + * @param[in] theta input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cos output. + */ + void riscv_sin_cos_f32( + float32_t theta, + float32_t * pSinVal, + float32_t * pCosVal); + + + /** + * @brief Q31 sin_cos function. + * @param[in] theta scaled input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cosine output. + */ + void riscv_sin_cos_q31( + q31_t theta, + q31_t * pSinVal, + q31_t * pCosVal); + + /** + * @} end of SinCos group + */ + + /** + * @ingroup groupController + */ + +/** + * @defgroup PID PID Motor Control + * + * A Proportional Integral Derivative (PID) controller is a generic feedback control + * loop mechanism widely used in industrial control systems. + * A PID controller is the most commonly used type of feedback controller. + * + * This set of functions implements (PID) controllers + * for Q15, Q31, and floating-point data types. The functions operate on a single sample + * of data and each call to the function returns a single processed value. + * S points to an instance of the PID control data structure. in + * is the input sample value. The functions return the output value. + * + * \par Algorithm: + * 
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd
+   *
+ * + * \par + * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant + * + * \par + * \image html PID.png "Proportional Integral Derivative Controller" + * + * \par + * The PID controller calculates an "error" value as the difference between + * the measured output and the reference input. + * The controller attempts to minimize the error by adjusting the process control inputs. + * The proportional value determines the reaction to the current error, + * the integral value determines the reaction based on the sum of recent errors, + * and the derivative value determines the reaction based on the rate at which the error has been changing. + * + * \par Instance Structure + * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. + * A separate instance structure must be defined for each PID Controller. + * There are separate instance structure declarations for each of the 3 supported data types. + * + * \par Reset Functions + * There is also an associated reset function for each data type which clears the state array. + * + * \par Initialization Functions + * There is also an associated initialization function for each data type. + * The initialization function performs the following operations: + * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. + * - Zeros out the values in the state buffer. + * + * \par + * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. + * + * \par Fixed-Point Behavior + * Care must be taken when using the fixed-point versions of the PID Controller functions. + * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + + /** + * @brief Instance structure for the Q15 PID Control. + */ + typedef struct + { + q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ +#if !defined (RISCV_MATH_DSP) + q15_t A1; /**< The derived gain A1 = -Kp - 2Kd */ + q15_t A2; /**< The derived gain A1 = Kd. */ +#else + q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ +#endif + q15_t state[3]; /**< The state array of length 3. */ + q15_t Kp; /**< The proportional gain. */ + q15_t Ki; /**< The integral gain. */ + q15_t Kd; /**< The derivative gain. */ + } riscv_pid_instance_q15; + + /** + * @brief Instance structure for the Q31 PID Control. + */ + typedef struct + { + q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + q31_t A2; /**< The derived gain, A2 = Kd . */ + q31_t state[3]; /**< The state array of length 3. */ + q31_t Kp; /**< The proportional gain. */ + q31_t Ki; /**< The integral gain. */ + q31_t Kd; /**< The derivative gain. */ + } riscv_pid_instance_q31; + + /** + * @brief Instance structure for the floating-point PID Control. + */ + typedef struct + { + float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + float32_t A2; /**< The derived gain, A2 = Kd . */ + float32_t state[3]; /**< The state array of length 3. */ + float32_t Kp; /**< The proportional gain. */ + float32_t Ki; /**< The integral gain. */ + float32_t Kd; /**< The derivative gain. */ + } riscv_pid_instance_f32; + + + + /** + * @brief Initialization function for the floating-point PID Control. + * @param[in,out] S points to an instance of the PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void riscv_pid_init_f32( + riscv_pid_instance_f32 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + */ + void riscv_pid_reset_f32( + riscv_pid_instance_f32 * S); + + + /** + * @brief Initialization function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void riscv_pid_init_q31( + riscv_pid_instance_q31 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q31 PID Control structure + */ + + void riscv_pid_reset_q31( + riscv_pid_instance_q31 * S); + + + /** + * @brief Initialization function for the Q15 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void riscv_pid_init_q15( + riscv_pid_instance_q15 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q15 PID Control. + * @param[in,out] S points to an instance of the q15 PID Control structure + */ + void riscv_pid_reset_q15( + riscv_pid_instance_q15 * S); + + + + /** + * @addtogroup PID + * @{ + */ + + /** + * @brief Process function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + * @param[in] in input sample to process + * @return processed output sample. + */ + __STATIC_FORCEINLINE float32_t riscv_pid_f32( + riscv_pid_instance_f32 * S, + float32_t in) + { + float32_t out; + + /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ + out = (S->A0 * in) + + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + +/** + @brief Process function for the Q31 PID Control. + @param[in,out] S points to an instance of the Q31 PID Control structure + @param[in] in input sample to process + @return processed output sample. + + \par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + Thus, if the accumulator result overflows it wraps around rather than clip. + In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. + After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + */ +__STATIC_FORCEINLINE q31_t riscv_pid_q31( + riscv_pid_instance_q31 * S, + q31_t in) + { + q63_t acc; + q31_t out; + + /* acc = A0 * x[n] */ + acc = (q63_t) S->A0 * in; + + /* acc += A1 * x[n-1] */ + acc += (q63_t) S->A1 * S->state[0]; + + /* acc += A2 * x[n-2] */ + acc += (q63_t) S->A2 * S->state[1]; + + /* convert output to 1.31 format to add y[n-1] */ + out = (q31_t) (acc >> 31U); + + /* out += y[n-1] */ + out += S->state[2]; + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + +/** + @brief Process function for the Q15 PID Control. + @param[in,out] S points to an instance of the Q15 PID Control structure + @param[in] in input sample to process + @return processed output sample. + + \par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ +__STATIC_FORCEINLINE q15_t riscv_pid_q15( + riscv_pid_instance_q15 * S, + q15_t in) + { + q63_t acc; + q15_t out; + +#if defined (RISCV_MATH_DSP) + /* Implementation of PID controller */ + + /* acc = A0 * x[n] */ + acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in); + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)read_q15x2 (S->state), (uint64_t)acc); +#else + /* acc = A0 * x[n] */ + acc = ((q31_t) S->A0) * in; + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc += (q31_t) S->A1 * S->state[0]; + acc += (q31_t) S->A2 * S->state[1]; +#endif + + /* acc += y[n-1] */ + acc += (q31_t) S->state[2] << 15; + + /* saturate the output */ + out = (q15_t) (__SSAT((q31_t)(acc >> 15), 16)); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + /** + * @} end of PID group + */ + + /** + * @ingroup groupController + */ + + /** + * @defgroup park Vector Park Transform + * + * Forward Park transform converts the input two-coordinate vector to flux and torque components. + * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents + * from the stationary to the moving reference frame and control the spatial relationship between + * the stator vector current and rotor flux vector. + * If we consider the d axis aligned with the rotor flux, the diagram below shows the + * current vector and the relationship from the two reference frames: + * \image html park.png "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkFormula.png + * where Ialpha and Ibeta are the stator vector components, + * pId and pIq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup park + * @{ + */ + + /** + * @brief Floating-point Park transform + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] pId points to output rotor reference frame d + * @param[out] pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none + * + * The function implements the forward Park transform. + * + */ + __STATIC_FORCEINLINE void riscv_park_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pId, + float32_t * pIq, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ + *pId = Ialpha * cosVal + Ibeta * sinVal; + + /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ + *pIq = -Ialpha * sinVal + Ibeta * cosVal; + } + + +/** + @brief Park transform for Q31 version + @param[in] Ialpha input two-phase vector coordinate alpha + @param[in] Ibeta input two-phase vector coordinate beta + @param[out] pId points to output rotor reference frame d + @param[out] pIq points to output rotor reference frame q + @param[in] sinVal sine value of rotation angle theta + @param[in] cosVal cosine value of rotation angle theta + @return none + + \par Scaling and Overflow Behavior + The function is implemented using an internal 32-bit accumulator. + The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + There is saturation on the addition and subtraction, hence there is no risk of overflow. + */ +__STATIC_FORCEINLINE void riscv_park_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pId, + q31_t * pIq, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Ialpha * cosVal) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * sinVal) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Ialpha * sinVal) */ + product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * cosVal) */ + product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); + + /* Calculate pId by adding the two intermediate products 1 and 2 */ + *pId = __QADD(product1, product2); + + /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ + *pIq = __QSUB(product4, product3); + } + + /** + * @} end of park group + */ + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_park Vector Inverse Park transform + * Inverse Park transform converts the input flux and torque components to two-coordinate vector. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkInvFormula.png + * where pIalpha and pIbeta are the stator vector components, + * Id and Iq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_park + * @{ + */ + + /** + * @brief Floating-point Inverse Park transform + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none + */ + __STATIC_FORCEINLINE void riscv_inv_park_f32( + float32_t Id, + float32_t Iq, + float32_t * pIalpha, + float32_t * pIbeta, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ + *pIalpha = Id * cosVal - Iq * sinVal; + + /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ + *pIbeta = Id * sinVal + Iq * cosVal; + } + + +/** + @brief Inverse Park transform for Q31 version + @param[in] Id input coordinate of rotor reference frame d + @param[in] Iq input coordinate of rotor reference frame q + @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + @param[out] pIbeta points to output two-phase orthogonal vector axis beta + @param[in] sinVal sine value of rotation angle theta + @param[in] cosVal cosine value of rotation angle theta + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 32-bit accumulator. + The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + There is saturation on the addition, hence there is no risk of overflow. + */ +__STATIC_FORCEINLINE void riscv_inv_park_q31( + q31_t Id, + q31_t Iq, + q31_t * pIalpha, + q31_t * pIbeta, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Id * cosVal) */ + product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Iq * sinVal) */ + product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Id * sinVal) */ + product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Iq * cosVal) */ + product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); + + /* Calculate pIalpha by using the two intermediate products 1 and 2 */ + *pIalpha = __QSUB(product1, product2); + + /* Calculate pIbeta by using the two intermediate products 3 and 4 */ + *pIbeta = __QADD(product4, product3); + } + + /** + * @} end of Inverse park group + */ + +/** + * @ingroup groupController + */ + + /** + * @defgroup clarke Vector Clarke Transform + * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. + * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents + * in the two-phase orthogonal stator axis Ialpha and Ibeta. + * When Ialpha is superposed with Ia as shown in the figure below + * \image html clarke.png Stator current space vector and its components in (a,b). + * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta + * can be calculated using only Ia and Ib. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeFormula.png + * where Ia and Ib are the instantaneous stator phases and + * pIalpha and pIbeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup clarke + * @{ + */ + + /** + * + * @brief Floating-point Clarke transform + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @return none + */ + __STATIC_FORCEINLINE void riscv_clarke_f32( + float32_t Ia, + float32_t Ib, + float32_t * pIalpha, + float32_t * pIbeta) + { + /* Calculate pIalpha using the equation, pIalpha = Ia */ + *pIalpha = Ia; + + /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ + *pIbeta = (0.57735026919f * Ia + 1.15470053838f * Ib); + } + + +/** + @brief Clarke transform for Q31 version + @param[in] Ia input three-phase coordinate a + @param[in] Ib input three-phase coordinate b + @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + @param[out] pIbeta points to output two-phase orthogonal vector axis beta + @return none + + \par Scaling and Overflow Behavior + The function is implemented using an internal 32-bit accumulator. + The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + There is saturation on the addition, hence there is no risk of overflow. + */ +__STATIC_FORCEINLINE void riscv_clarke_q31( + q31_t Ia, + q31_t Ib, + q31_t * pIalpha, + q31_t * pIbeta) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIalpha from Ia by equation pIalpha = Ia */ + *pIalpha = Ia; + + /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); + + /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ + product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); + + /* pIbeta is calculated by adding the intermediate products */ + *pIbeta = __QADD(product1, product2); + } + + /** + * @} end of clarke group + */ + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_clarke Vector Inverse Clarke Transform + * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeInvFormula.png + * where pIa and pIb are the instantaneous stator phases and + * Ialpha and Ibeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_clarke + * @{ + */ + + /** + * @brief Floating-point Inverse Clarke transform + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] pIa points to output three-phase coordinate a + * @param[out] pIb points to output three-phase coordinate b + * @return none + */ + __STATIC_FORCEINLINE void riscv_inv_clarke_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pIa, + float32_t * pIb) + { + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ + *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta; + } + + +/** + @brief Inverse Clarke transform for Q31 version + @param[in] Ialpha input two-phase orthogonal vector axis alpha + @param[in] Ibeta input two-phase orthogonal vector axis beta + @param[out] pIa points to output three-phase coordinate a + @param[out] pIb points to output three-phase coordinate b + @return none + + \par Scaling and Overflow Behavior + The function is implemented using an internal 32-bit accumulator. + The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + There is saturation on the subtraction, hence there is no risk of overflow. + */ +__STATIC_FORCEINLINE void riscv_inv_clarke_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pIa, + q31_t * pIb) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); + + /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); + + /* pIb is calculated by subtracting the products */ + *pIb = __QSUB(product2, product1); + } + + /** + * @} end of inv_clarke group + */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _CONTROLLER_FUNCTIONS_H_ */ diff --git a/components/nmsis/dsp/inc/dsp/controller_functions_f16.h b/components/nmsis/dsp/inc/dsp/controller_functions_f16.h new file mode 100644 index 00000000..43bbb971 --- /dev/null +++ b/components/nmsis/dsp/inc/dsp/controller_functions_f16.h @@ -0,0 +1,42 @@ +/****************************************************************************** + * @file controller_functions_f16.h + * @brief Public header file for NMSIS DSP Library + * @version V1.9.0 + * @date 23 April 2021 + * Target Processor: RISC-V Cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _CONTROLLER_FUNCTIONS_F16_H_ +#define _CONTROLLER_FUNCTIONS_F16_H_ + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if defined(RISCV_FLOAT16_SUPPORTED) +#endif /*defined(RISCV_FLOAT16_SUPPORTED)*/ +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _CONTROLLER_FUNCTIONS_F16_H_ */ diff --git a/components/nmsis/dsp/inc/dsp/distance_functions.h b/components/nmsis/dsp/inc/dsp/distance_functions.h new file mode 100644 index 00000000..f66c6a65 --- /dev/null +++ b/components/nmsis/dsp/inc/dsp/distance_functions.h @@ -0,0 +1,293 @@ +/****************************************************************************** + * @file distance_functions.h + * @brief Public header file for NMSIS DSP Library + * @version V1.9.0 + * @date 23 April 2021 + * Target Processor: RISC-V Cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _DISTANCE_FUNCTIONS_H_ +#define _DISTANCE_FUNCTIONS_H_ + +#include "riscv_math_types.h" +#include "riscv_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" + +#include "dsp/statistics_functions.h" +#include "dsp/basic_math_functions.h" +#include "dsp/fast_math_functions.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** + * @defgroup groupDistance Distance functions + * + * Distance functions for use with clustering algorithms. + * There are distance functions for float vectors and boolean vectors. + * + */ + +/* 6.14 bug */ + +/** + * @brief Euclidean distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + +float32_t riscv_euclidean_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize); + +/** + * @brief Bray-Curtis distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float32_t riscv_braycurtis_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize); + +/** + * @brief Canberra distance between two vectors + * + * This function may divide by zero when samples pA[i] and pB[i] are both zero. + * The result of the computation will be correct. So the division per zero may be + * ignored. + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float32_t riscv_canberra_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize); + + +/** + * @brief Chebyshev distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float32_t riscv_chebyshev_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize); + + +/** + * @brief Cityblock (Manhattan) distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float32_t riscv_cityblock_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize); + +/** + * @brief Correlation distance between two vectors + * + * The input vectors are modified in place ! + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float32_t riscv_correlation_distance_f32(float32_t *pA,float32_t *pB, uint32_t blockSize); + +/** + * @brief Cosine distance between two vectors + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + +float32_t riscv_cosine_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize); + +/** + * @brief Jensen-Shannon distance between two vectors + * + * This function is assuming that elements of second vector are > 0 + * and 0 only when the corresponding element of first vector is 0. + * Otherwise the result of the computation does not make sense + * and for speed reasons, the cases returning NaN or Infinity are not + * managed. + * + * When the function is computing x log (x / y) with x 0 and y 0, + * it will compute the right value (0) but a division per zero will occur + * and shoudl be ignored in client code. + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + +float32_t riscv_jensenshannon_distance_f32(const float32_t *pA,const float32_t *pB,uint32_t blockSize); + +/** + * @brief Minkowski distance between two vectors + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] n Norm order (>= 2) + * @param[in] blockSize vector length + * @return distance + * + */ + + + +float32_t riscv_minkowski_distance_f32(const float32_t *pA,const float32_t *pB, int32_t order, uint32_t blockSize); + +/** + * @brief Dice distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] order Distance order + * @param[in] blockSize Number of samples + * @return distance + * + */ + + +float32_t riscv_dice_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + +/** + * @brief Hamming distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t riscv_hamming_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + +/** + * @brief Jaccard distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t riscv_jaccard_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + +/** + * @brief Kulsinski distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t riscv_kulsinski_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + +/** + * @brief Roger Stanimoto distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t riscv_rogerstanimoto_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + +/** + * @brief Russell-Rao distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t riscv_russellrao_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + +/** + * @brief Sokal-Michener distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t riscv_sokalmichener_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + +/** + * @brief Sokal-Sneath distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t riscv_sokalsneath_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + +/** + * @brief Yule distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t riscv_yule_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + + + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _DISTANCE_FUNCTIONS_H_ */ diff --git a/components/nmsis/dsp/inc/dsp/distance_functions_f16.h b/components/nmsis/dsp/inc/dsp/distance_functions_f16.h new file mode 100644 index 00000000..056601eb --- /dev/null +++ b/components/nmsis/dsp/inc/dsp/distance_functions_f16.h @@ -0,0 +1,177 @@ +/****************************************************************************** + * @file distance_functions_f16.h + * @brief Public header file for NMSIS DSP Library + * @version V1.9.0 + * @date 23 April 2021 + * Target Processor: RISC-V Cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _DISTANCE_FUNCTIONS_F16_H_ +#define _DISTANCE_FUNCTIONS_F16_H_ + +#include "riscv_math_types_f16.h" +#include "riscv_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" + +/* 6.14 bug */ + +#include "dsp/statistics_functions_f16.h" +#include "dsp/basic_math_functions_f16.h" + +#include "dsp/fast_math_functions_f16.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if defined(RISCV_FLOAT16_SUPPORTED) + +/** + * @brief Euclidean distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + +float16_t riscv_euclidean_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize); + +/** + * @brief Bray-Curtis distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float16_t riscv_braycurtis_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize); + +/** + * @brief Canberra distance between two vectors + * + * This function may divide by zero when samples pA[i] and pB[i] are both zero. + * The result of the computation will be correct. So the division per zero may be + * ignored. + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float16_t riscv_canberra_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize); + + +/** + * @brief Chebyshev distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float16_t riscv_chebyshev_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize); + + +/** + * @brief Cityblock (Manhattan) distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float16_t riscv_cityblock_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize); + +/** + * @brief Correlation distance between two vectors + * + * The input vectors are modified in place ! + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float16_t riscv_correlation_distance_f16(float16_t *pA,float16_t *pB, uint32_t blockSize); + +/** + * @brief Cosine distance between two vectors + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + +float16_t riscv_cosine_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize); + +/** + * @brief Jensen-Shannon distance between two vectors + * + * This function is assuming that elements of second vector are > 0 + * and 0 only when the corresponding element of first vector is 0. + * Otherwise the result of the computation does not make sense + * and for speed reasons, the cases returning NaN or Infinity are not + * managed. + * + * When the function is computing x log (x / y) with x 0 and y 0, + * it will compute the right value (0) but a division per zero will occur + * and shoudl be ignored in client code. + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + +float16_t riscv_jensenshannon_distance_f16(const float16_t *pA,const float16_t *pB,uint32_t blockSize); + +/** + * @brief Minkowski distance between two vectors + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] n Norm order (>= 2) + * @param[in] blockSize vector length + * @return distance + * + */ + + + +float16_t riscv_minkowski_distance_f16(const float16_t *pA,const float16_t *pB, int32_t order, uint32_t blockSize); + + +#endif /*defined(RISCV_FLOAT16_SUPPORTED)*/ +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _DISTANCE_FUNCTIONS_F16_H_ */ diff --git a/components/nmsis/dsp/inc/dsp/fast_math_functions.h b/components/nmsis/dsp/inc/dsp/fast_math_functions.h new file mode 100644 index 00000000..7191b4b1 --- /dev/null +++ b/components/nmsis/dsp/inc/dsp/fast_math_functions.h @@ -0,0 +1,296 @@ +/****************************************************************************** + * @file fast_math_functions.h + * @brief Public header file for NMSIS DSP Library + * @version V1.9.0 + * @date 23 April 2021 + * Target Processor: RISC-V Cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _FAST_MATH_FUNCTIONS_H_ +#define _FAST_MATH_FUNCTIONS_H_ + +#include "riscv_math_types.h" +#include "riscv_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + + /** + * @brief Macros required for SINE and COSINE Fast math approximations + */ + +#define FAST_MATH_TABLE_SIZE 512 +#define FAST_MATH_Q31_SHIFT (32 - 10) +#define FAST_MATH_Q15_SHIFT (16 - 10) + +#ifndef PI + #define PI 3.14159265358979f +#endif + + +/** + * @defgroup groupFastMath Fast Math Functions + * This set of functions provides a fast approximation to sine, cosine, and square root. + * As compared to most of the other functions in the NMSIS math library, the fast math functions + * operate on individual values and not arrays. + * There are separate functions for Q15, Q31, and floating-point data. + * + */ + + /** + * @ingroup groupFastMath + */ + + +/** + @addtogroup sin + @{ + */ + +/** + * @brief Fast approximation to the trigonometric sine function for floating-point data. + * @param[in] x input value in radians. + * @return sin(x). + */ + float32_t riscv_sin_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q31_t riscv_sin_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q15_t riscv_sin_q15( + q15_t x); + +/** + @} end of sin group + */ + +/** + @addtogroup cos + @{ + */ + + /** + * @brief Fast approximation to the trigonometric cosine function for floating-point data. + * @param[in] x input value in radians. + * @return cos(x). + */ + float32_t riscv_cos_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q31_t riscv_cos_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q15_t riscv_cos_q15( + q15_t x); + +/** + @} end of cos group + */ + + +/** + @brief Floating-point vector of log values. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + void riscv_vlog_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + +/** + @brief Floating-point vector of exp values. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + void riscv_vexp_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @defgroup SQRT Square Root + * + * Computes the square root of a number. + * There are separate functions for Q15, Q31, and floating-point data types. + * The square root function is computed using the Newton-Raphson algorithm. + * This is an iterative algorithm of the form: + * 
+   *      x1 = x0 - f(x0)/f'(x0)
+   *
+ * where x1 is the current estimate, + * x0 is the previous estimate, and + * f'(x0) is the derivative of f() evaluated at x0. + * For the square root function, the algorithm reduces to: + * 
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   *
+ */ + + + /** + * @addtogroup SQRT + * @{ + */ + +/** + @brief Floating-point square root function. + @param[in] in input value + @param[out] pOut square root of input value + @return execution status + - \ref RISCV_MATH_SUCCESS : input value is positive + - \ref RISCV_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0 + */ +__STATIC_FORCEINLINE riscv_status riscv_sqrt_f32( + float32_t in, + float32_t * pOut) + { + if (in >= 0.0f) + { + +#if defined ( __RISCV_FLEN ) + __ASM volatile("fsqrt.s %0, %1" : "=f"(*pOut) : "f"(in)); + +#else + *pOut = sqrtf(in); +#endif + + return (RISCV_MATH_SUCCESS); + } + else + { + *pOut = 0.0f; + return (RISCV_MATH_ARGUMENT_ERROR); + } + } + + +/** + @brief Q31 square root function. + @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF + @param[out] pOut points to square root of input value + @return execution status + - \ref RISCV_MATH_SUCCESS : input value is positive + - \ref RISCV_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0 + */ +riscv_status riscv_sqrt_q31( + q31_t in, + q31_t * pOut); + + +/** + @brief Q15 square root function. + @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF + @param[out] pOut points to square root of input value + @return execution status + - \ref RISCV_MATH_SUCCESS : input value is positive + - \ref RISCV_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0 + */ +riscv_status riscv_sqrt_q15( + q15_t in, + q15_t * pOut); + + /** + * @brief Vector Floating-point square root function. + * @param[in] pIn input vector. + * @param[out] pOut vector of square roots of input elements. + * @param[in] len length of input vector. + * @return The function returns RISCV_MATH_SUCCESS if input value is positive value or RISCV_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + void riscv_vsqrt_f32( + float32_t * pIn, + float32_t * pOut, + uint16_t len); + + void riscv_vsqrt_q31( + q31_t * pIn, + q31_t * pOut, + uint16_t len); + + void riscv_vsqrt_q15( + q15_t * pIn, + q15_t * pOut, + uint16_t len); + + /** + * @} end of SQRT group + */ + + /** + @brief Fixed point division + @param[in] numerator Numerator + @param[in] denominator Denominator + @param[out] quotient Quotient value normalized between -1.0 and 1.0 + @param[out] shift Shift left value to get the unnormalized quotient + @return error status + + When dividing by 0, an error RISCV_MATH_NANINF is returned. And the quotient is forced + to the saturated negative or positive value. + */ + +riscv_status riscv_divide_q15(q15_t numerator, + q15_t denominator, + q15_t *quotient, + int16_t *shift); + + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _FAST_MATH_FUNCTIONS_H_ */ diff --git a/components/nmsis/dsp/inc/dsp/fast_math_functions_f16.h b/components/nmsis/dsp/inc/dsp/fast_math_functions_f16.h new file mode 100644 index 00000000..42ab3ab8 --- /dev/null +++ b/components/nmsis/dsp/inc/dsp/fast_math_functions_f16.h @@ -0,0 +1,117 @@ +/****************************************************************************** + * @file fast_math_functions_f16.h + * @brief Public header file for NMSIS DSP Library + * @version V1.9.0 + * @date 23 April 2021 + * Target Processor: RISC-V Cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _FAST_MATH_FUNCTIONS_F16_H_ +#define _FAST_MATH_FUNCTIONS_F16_H_ + +#include "riscv_math_types_f16.h" +#include "riscv_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" + +/* For sqrt_f32 */ +#include "dsp/fast_math_functions.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if defined(RISCV_FLOAT16_SUPPORTED) + + /** + * @addtogroup SQRT + * @{ + */ + +/** + @brief Floating-point square root function. + @param[in] in input value + @param[out] pOut square root of input value + @return execution status + - \ref RISCV_MATH_SUCCESS : input value is positive + - \ref RISCV_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0 + */ +__STATIC_FORCEINLINE riscv_status riscv_sqrt_f16( + float16_t in, + float16_t * pOut) + { + float32_t r; + riscv_status status; + status=riscv_sqrt_f32((float32_t)in,&r); + *pOut=(float16_t)r; + return(status); + } + + +/** + @} end of SQRT group + */ + +/** + @brief Floating-point vector of log values. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + void riscv_vlog_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize); + +/** + @brief Floating-point vector of exp values. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + void riscv_vexp_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize); + + /** + @brief Floating-point vector of inverse values. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + void riscv_vinverse_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize); + +#endif /*defined(RISCV_FLOAT16_SUPPORTED)*/ +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _FAST_MATH_FUNCTIONS_F16_H_ */ diff --git a/components/nmsis/dsp/inc/dsp/filtering_functions.h b/components/nmsis/dsp/inc/dsp/filtering_functions.h new file mode 100644 index 00000000..3ac56a82 --- /dev/null +++ b/components/nmsis/dsp/inc/dsp/filtering_functions.h @@ -0,0 +1,2446 @@ +/****************************************************************************** + * @file filtering_functions.h + * @brief Public header file for NMSIS DSP Library + * @version V1.9.0 + * @date 23 April 2021 + * Target Processor: RISC-V Cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _FILTERING_FUNCTIONS_H_ +#define _FILTERING_FUNCTIONS_H_ + +#include "riscv_math_types.h" +#include "riscv_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" + +#include "dsp/support_functions.h" +#include "dsp/fast_math_functions.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + + + +#define DELTA_Q31 ((q31_t)(0x100)) +#define DELTA_Q15 ((q15_t)0x5) + +/** + * @defgroup groupFilters Filtering Functions + */ + + /** + * @brief Instance structure for the Q7 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + const q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } riscv_fir_instance_q7; + + /** + * @brief Instance structure for the Q15 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } riscv_fir_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } riscv_fir_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } riscv_fir_instance_f32; + + /** + * @brief Processing function for the Q7 FIR filter. + * @param[in] S points to an instance of the Q7 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void riscv_fir_q7( + const riscv_fir_instance_q7 * S, + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q7 FIR filter. + * @param[in,out] S points to an instance of the Q7 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed. + * + * For the MVE version, the coefficient length must be a multiple of 16. + * You can pad with zeros if you have less coefficients. + */ + void riscv_fir_init_q7( + riscv_fir_instance_q7 * S, + uint16_t numTaps, + const q7_t * pCoeffs, + q7_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q15 FIR filter. + * @param[in] S points to an instance of the Q15 FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void riscv_fir_q15( + const riscv_fir_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the fast Q15 FIR filter (fast version). + * @param[in] S points to an instance of the Q15 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void riscv_fir_fast_q15( + const riscv_fir_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q15 FIR filter. + * @param[in,out] S points to an instance of the Q15 FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return The function returns either + * RISCV_MATH_SUCCESS if initialization was successful or + * RISCV_MATH_ARGUMENT_ERROR if numTaps is not a supported value. + * + * For the MVE version, the coefficient length must be a multiple of 8. + * You can pad with zeros if you have less coefficients. + * + */ + riscv_status riscv_fir_init_q15( + riscv_fir_instance_q15 * S, + uint16_t numTaps, + const q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR filter. + * @param[in] S points to an instance of the Q31 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void riscv_fir_q31( + const riscv_fir_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the fast Q31 FIR filter (fast version). + * @param[in] S points to an instance of the Q31 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void riscv_fir_fast_q31( + const riscv_fir_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 FIR filter. + * @param[in,out] S points to an instance of the Q31 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * + * For the MVE version, the coefficient length must be a multiple of 4. + * You can pad with zeros if you have less coefficients. + */ + void riscv_fir_init_q31( + riscv_fir_instance_q31 * S, + uint16_t numTaps, + const q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the floating-point FIR filter. + * @param[in] S points to an instance of the floating-point FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void riscv_fir_f32( + const riscv_fir_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point FIR filter. + * @param[in,out] S points to an instance of the floating-point FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void riscv_fir_init_f32( + riscv_fir_instance_f32 * S, + uint16_t numTaps, + const float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + /** + * @brief Instance structure for the Q15 Biquad cascade filter. + */ + typedef struct + { + int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + const q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } riscv_biquad_casd_df1_inst_q15; + + /** + * @brief Instance structure for the Q31 Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + const q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } riscv_biquad_casd_df1_inst_q31; + + /** + * @brief Instance structure for the floating-point Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + const float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + } riscv_biquad_casd_df1_inst_f32; + + + /** + * @brief Processing function for the Q15 Biquad cascade filter. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void riscv_biquad_cascade_df1_q15( + const riscv_biquad_casd_df1_inst_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q15 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void riscv_biquad_cascade_df1_init_q15( + riscv_biquad_casd_df1_inst_q15 * S, + uint8_t numStages, + const q15_t * pCoeffs, + q15_t * pState, + int8_t postShift); + + /** + * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for RISC-V Core with DSP enabled. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void riscv_biquad_cascade_df1_fast_q15( + const riscv_biquad_casd_df1_inst_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 Biquad cascade filter + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void riscv_biquad_cascade_df1_q31( + const riscv_biquad_casd_df1_inst_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for RISC-V Core with DSP enabled. + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void riscv_biquad_cascade_df1_fast_q31( + const riscv_biquad_casd_df1_inst_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void riscv_biquad_cascade_df1_init_q31( + riscv_biquad_casd_df1_inst_q31 * S, + uint8_t numStages, + const q31_t * pCoeffs, + q31_t * pState, + int8_t postShift); + + /** + * @brief Processing function for the floating-point Biquad cascade filter. + * @param[in] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void riscv_biquad_cascade_df1_f32( + const riscv_biquad_casd_df1_inst_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point Biquad cascade filter. + * @param[in,out] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pCoeffsMod points to the modified filter coefficients (only MVE version). + * @param[in] pState points to the state buffer. + */ + + void riscv_biquad_cascade_df1_init_f32( + riscv_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + const float32_t * pCoeffs, + float32_t * pState); + + +/** + * @brief Convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void riscv_conv_f32( + const float32_t * pSrcA, + uint32_t srcALen, + const float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void riscv_conv_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void riscv_conv_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for RISC-V Core with DSP enabled + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void riscv_conv_fast_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for RISC-V Core with DSP enabled + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void riscv_conv_fast_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void riscv_conv_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q31 sequences (fast version) for RISC-V Core with DSP enabled + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void riscv_conv_fast_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void riscv_conv_opt_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void riscv_conv_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Partial convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either RISCV_MATH_SUCCESS if the function completed correctly or RISCV_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + riscv_status riscv_conv_partial_f32( + const float32_t * pSrcA, + uint32_t srcALen, + const float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either RISCV_MATH_SUCCESS if the function completed correctly or RISCV_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + riscv_status riscv_conv_partial_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either RISCV_MATH_SUCCESS if the function completed correctly or RISCV_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + riscv_status riscv_conv_partial_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for RISC-V Core with DSP enabled + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either RISCV_MATH_SUCCESS if the function completed correctly or RISCV_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + riscv_status riscv_conv_partial_fast_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for RISC-V Core with DSP enabled + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either RISCV_MATH_SUCCESS if the function completed correctly or RISCV_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + riscv_status riscv_conv_partial_fast_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either RISCV_MATH_SUCCESS if the function completed correctly or RISCV_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + riscv_status riscv_conv_partial_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q31 sequences (fast version) for RISC-V Core with DSP enabled + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either RISCV_MATH_SUCCESS if the function completed correctly or RISCV_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + riscv_status riscv_conv_partial_fast_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q7 sequences + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return Returns either RISCV_MATH_SUCCESS if the function completed correctly or RISCV_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + riscv_status riscv_conv_partial_opt_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Partial convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either RISCV_MATH_SUCCESS if the function completed correctly or RISCV_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + riscv_status riscv_conv_partial_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Instance structure for the Q15 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } riscv_fir_decimate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } riscv_fir_decimate_instance_q31; + +/** + @brief Instance structure for floating-point FIR decimator. + */ +typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } riscv_fir_decimate_instance_f32; + + +/** + @brief Processing function for floating-point FIR decimator. + @param[in] S points to an instance of the floating-point FIR decimator structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + */ +void riscv_fir_decimate_f32( + const riscv_fir_decimate_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + +/** + @brief Initialization function for the floating-point FIR decimator. + @param[in,out] S points to an instance of the floating-point FIR decimator structure + @param[in] numTaps number of coefficients in the filter + @param[in] M decimation factor + @param[in] pCoeffs points to the filter coefficients + @param[in] pState points to the state buffer + @param[in] blockSize number of input samples to process per call + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_LENGTH_ERROR : blockSize is not a multiple of M + */ +riscv_status riscv_fir_decimate_init_f32( + riscv_fir_decimate_instance_f32 * S, + uint16_t numTaps, + uint8_t M, + const float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void riscv_fir_decimate_q15( + const riscv_fir_decimate_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator (fast variant) for RISC-V Core with DSP enabled. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void riscv_fir_decimate_fast_q15( + const riscv_fir_decimate_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR decimator. + * @param[in,out] S points to an instance of the Q15 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns RISCV_MATH_SUCCESS if initialization is successful or RISCV_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + riscv_status riscv_fir_decimate_init_q15( + riscv_fir_decimate_instance_q15 * S, + uint16_t numTaps, + uint8_t M, + const q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR decimator. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void riscv_fir_decimate_q31( + const riscv_fir_decimate_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator (fast variant) for RISC-V Core with DSP enabled. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void riscv_fir_decimate_fast_q31( + const riscv_fir_decimate_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR decimator. + * @param[in,out] S points to an instance of the Q31 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns RISCV_MATH_SUCCESS if initialization is successful or RISCV_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + riscv_status riscv_fir_decimate_init_q31( + riscv_fir_decimate_instance_q31 * S, + uint16_t numTaps, + uint8_t M, + const q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } riscv_fir_interpolate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } riscv_fir_interpolate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ + } riscv_fir_interpolate_instance_f32; + + + /** + * @brief Processing function for the Q15 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void riscv_fir_interpolate_q15( + const riscv_fir_interpolate_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR interpolator. + * @param[in,out] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns RISCV_MATH_SUCCESS if initialization is successful or RISCV_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + riscv_status riscv_fir_interpolate_init_q15( + riscv_fir_interpolate_instance_q15 * S, + uint8_t L, + uint16_t numTaps, + const q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void riscv_fir_interpolate_q31( + const riscv_fir_interpolate_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR interpolator. + * @param[in,out] S points to an instance of the Q31 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns RISCV_MATH_SUCCESS if initialization is successful or RISCV_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + riscv_status riscv_fir_interpolate_init_q31( + riscv_fir_interpolate_instance_q31 * S, + uint8_t L, + uint16_t numTaps, + const q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR interpolator. + * @param[in] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void riscv_fir_interpolate_f32( + const riscv_fir_interpolate_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR interpolator. + * @param[in,out] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns RISCV_MATH_SUCCESS if initialization is successful or RISCV_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + riscv_status riscv_fir_interpolate_init_f32( + riscv_fir_interpolate_instance_f32 * S, + uint8_t L, + uint16_t numTaps, + const float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the high precision Q31 Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + const q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ + } riscv_biquad_cas_df1_32x64_ins_q31; + + + /** + * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void riscv_biquad_cas_df1_32x64_q31( + const riscv_biquad_cas_df1_32x64_ins_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format + */ + void riscv_biquad_cas_df1_32x64_init_q31( + riscv_biquad_cas_df1_32x64_ins_q31 * S, + uint8_t numStages, + const q31_t * pCoeffs, + q63_t * pState, + uint8_t postShift); + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + const float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } riscv_biquad_cascade_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + const float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } riscv_biquad_cascade_stereo_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + const float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } riscv_biquad_cascade_df2T_instance_f64; + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void riscv_biquad_cascade_df2T_f32( + const riscv_biquad_cascade_df2T_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void riscv_biquad_cascade_stereo_df2T_f32( + const riscv_biquad_cascade_stereo_df2T_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void riscv_biquad_cascade_df2T_f64( + const riscv_biquad_cascade_df2T_instance_f64 * S, + const float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void riscv_biquad_cascade_df2T_init_f32( + riscv_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + const float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void riscv_biquad_cascade_stereo_df2T_init_f32( + riscv_biquad_cascade_stereo_df2T_instance_f32 * S, + uint8_t numStages, + const float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void riscv_biquad_cascade_df2T_init_f64( + riscv_biquad_cascade_df2T_instance_f64 * S, + uint8_t numStages, + const float64_t * pCoeffs, + float64_t * pState); + + + /** + * @brief Instance structure for the Q15 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ + const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } riscv_fir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ + const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } riscv_fir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ + const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } riscv_fir_lattice_instance_f32; + + + /** + * @brief Initialization function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void riscv_fir_lattice_init_q15( + riscv_fir_lattice_instance_q15 * S, + uint16_t numStages, + const q15_t * pCoeffs, + q15_t * pState); + + + /** + * @brief Processing function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void riscv_fir_lattice_q15( + const riscv_fir_lattice_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void riscv_fir_lattice_init_q31( + riscv_fir_lattice_instance_q31 * S, + uint16_t numStages, + const q31_t * pCoeffs, + q31_t * pState); + + + /** + * @brief Processing function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void riscv_fir_lattice_q31( + const riscv_fir_lattice_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void riscv_fir_lattice_init_f32( + riscv_fir_lattice_instance_f32 * S, + uint16_t numStages, + const float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Processing function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void riscv_fir_lattice_f32( + const riscv_fir_lattice_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } riscv_iir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } riscv_iir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } riscv_iir_lattice_instance_f32; + + + /** + * @brief Processing function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void riscv_iir_lattice_f32( + const riscv_iir_lattice_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1. + * @param[in] blockSize number of samples to process. + */ + void riscv_iir_lattice_init_f32( + riscv_iir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pkCoeffs, + float32_t * pvCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void riscv_iir_lattice_q31( + const riscv_iir_lattice_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process. + */ + void riscv_iir_lattice_init_q31( + riscv_iir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pkCoeffs, + q31_t * pvCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the Q15 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void riscv_iir_lattice_q15( + const riscv_iir_lattice_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process per call. + */ + void riscv_iir_lattice_init_q15( + riscv_iir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pkCoeffs, + q15_t * pvCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the floating-point LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that controls filter coefficient updates. */ + } riscv_lms_instance_f32; + + + /** + * @brief Processing function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void riscv_lms_f32( + const riscv_lms_instance_f32 * S, + const float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void riscv_lms_init_f32( + riscv_lms_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } riscv_lms_instance_q15; + + + /** + * @brief Initialization function for the Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void riscv_lms_init_q15( + riscv_lms_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Processing function for Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void riscv_lms_q15( + const riscv_lms_instance_q15 * S, + const q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } riscv_lms_instance_q31; + + + /** + * @brief Processing function for Q31 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void riscv_lms_q31( + const riscv_lms_instance_q31 * S, + const q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 LMS filter. + * @param[in] S points to an instance of the Q31 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void riscv_lms_init_q31( + riscv_lms_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Instance structure for the floating-point normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that control filter coefficient updates. */ + float32_t energy; /**< saves previous frame energy. */ + float32_t x0; /**< saves previous input sample. */ + } riscv_lms_norm_instance_f32; + + + /** + * @brief Processing function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void riscv_lms_norm_f32( + riscv_lms_norm_instance_f32 * S, + const float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void riscv_lms_norm_init_f32( + riscv_lms_norm_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + const q31_t *recipTable; /**< points to the reciprocal initial value table. */ + q31_t energy; /**< saves previous frame energy. */ + q31_t x0; /**< saves previous input sample. */ + } riscv_lms_norm_instance_q31; + + + /** + * @brief Processing function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void riscv_lms_norm_q31( + riscv_lms_norm_instance_q31 * S, + const q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void riscv_lms_norm_init_q31( + riscv_lms_norm_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Instance structure for the Q15 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< Number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + const q15_t *recipTable; /**< Points to the reciprocal initial value table. */ + q15_t energy; /**< saves previous frame energy. */ + q15_t x0; /**< saves previous input sample. */ + } riscv_lms_norm_instance_q15; + + + /** + * @brief Processing function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void riscv_lms_norm_q15( + riscv_lms_norm_instance_q15 * S, + const q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void riscv_lms_norm_init_q15( + riscv_lms_norm_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Correlation of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void riscv_correlate_f32( + const float32_t * pSrcA, + uint32_t srcALen, + const float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + +/** + @brief Correlation of Q15 sequences + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. +*/ +void riscv_correlate_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + +/** + @brief Correlation of Q15 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void riscv_correlate_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + +/** + @brief Correlation of Q15 sequences (fast version). + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. + @return none + */ +void riscv_correlate_fast_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + +/** + @brief Correlation of Q15 sequences (fast version). + @param[in] pSrcA points to the first input sequence. + @param[in] srcALen length of the first input sequence. + @param[in] pSrcB points to the second input sequence. + @param[in] srcBLen length of the second input sequence. + @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + */ +void riscv_correlate_fast_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void riscv_correlate_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + +/** + @brief Correlation of Q31 sequences (fast version). + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ +void riscv_correlate_fast_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void riscv_correlate_opt_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void riscv_correlate_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Instance structure for the floating-point sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } riscv_fir_sparse_instance_f32; + + /** + * @brief Instance structure for the Q31 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } riscv_fir_sparse_instance_q31; + + /** + * @brief Instance structure for the Q15 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } riscv_fir_sparse_instance_q15; + + /** + * @brief Instance structure for the Q7 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + const q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } riscv_fir_sparse_instance_q7; + + + /** + * @brief Processing function for the floating-point sparse FIR filter. + * @param[in] S points to an instance of the floating-point sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void riscv_fir_sparse_f32( + riscv_fir_sparse_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + float32_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point sparse FIR filter. + * @param[in,out] S points to an instance of the floating-point sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void riscv_fir_sparse_init_f32( + riscv_fir_sparse_instance_f32 * S, + uint16_t numTaps, + const float32_t * pCoeffs, + float32_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 sparse FIR filter. + * @param[in] S points to an instance of the Q31 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void riscv_fir_sparse_q31( + riscv_fir_sparse_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + q31_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 sparse FIR filter. + * @param[in,out] S points to an instance of the Q31 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void riscv_fir_sparse_init_q31( + riscv_fir_sparse_instance_q31 * S, + uint16_t numTaps, + const q31_t * pCoeffs, + q31_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 sparse FIR filter. + * @param[in] S points to an instance of the Q15 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void riscv_fir_sparse_q15( + riscv_fir_sparse_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + q15_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 sparse FIR filter. + * @param[in,out] S points to an instance of the Q15 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void riscv_fir_sparse_init_q15( + riscv_fir_sparse_instance_q15 * S, + uint16_t numTaps, + const q15_t * pCoeffs, + q15_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q7 sparse FIR filter. + * @param[in] S points to an instance of the Q7 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void riscv_fir_sparse_q7( + riscv_fir_sparse_instance_q7 * S, + const q7_t * pSrc, + q7_t * pDst, + q7_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 sparse FIR filter. + * @param[in,out] S points to an instance of the Q7 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void riscv_fir_sparse_init_q7( + riscv_fir_sparse_instance_q7 * S, + uint16_t numTaps, + const q7_t * pCoeffs, + q7_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + + + + + /** + * @brief floating-point Circular write function. + */ + __STATIC_FORCEINLINE void riscv_circularWrite_f32( + int32_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const int32_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + + /** + * @brief floating-point Circular Read function. + */ + __STATIC_FORCEINLINE void riscv_circularRead_f32( + int32_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + int32_t * dst, + int32_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t rOffset; + int32_t* dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + dst_end = dst_base + dst_length; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q15 Circular write function. + */ + __STATIC_FORCEINLINE void riscv_circularWrite_q15( + q15_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q15_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q15 Circular Read function. + */ + __STATIC_FORCEINLINE void riscv_circularRead_q15( + q15_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q15_t * dst, + q15_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset; + q15_t* dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = dst_base + dst_length; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == dst_end) + { + dst = dst_base; + } + + /* Circularly update wOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q7 Circular write function. + */ + __STATIC_FORCEINLINE void riscv_circularWrite_q7( + q7_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q7_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q7 Circular Read function. + */ + __STATIC_FORCEINLINE void riscv_circularRead_q7( + q7_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q7_t * dst, + q7_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset; + q7_t* dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = dst_base + dst_length; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + +/** + @brief Levinson Durbin + @param[in] phi autocovariance vector starting with lag 0 (length is nbCoefs + 1) + @param[out] a autoregressive coefficients + @param[out] err prediction error (variance) + @param[in] nbCoefs number of autoregressive coefficients + @return none + */ +void riscv_levinson_durbin_f32(const float32_t *phi, + float32_t *a, + float32_t *err, + int nbCoefs); + + +/** + @brief Levinson Durbin + @param[in] phi autocovariance vector starting with lag 0 (length is nbCoefs + 1) + @param[out] a autoregressive coefficients + @param[out] err prediction error (variance) + @param[in] nbCoefs number of autoregressive coefficients + @return none + */ +void riscv_levinson_durbin_q31(const q31_t *phi, + q31_t *a, + q31_t *err, + int nbCoefs); + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _FILTERING_FUNCTIONS_H_ */ diff --git a/components/nmsis/dsp/inc/dsp/filtering_functions_f16.h b/components/nmsis/dsp/inc/dsp/filtering_functions_f16.h new file mode 100644 index 00000000..348088f7 --- /dev/null +++ b/components/nmsis/dsp/inc/dsp/filtering_functions_f16.h @@ -0,0 +1,221 @@ +/****************************************************************************** + * @file filtering_functions_f16.h + * @brief Public header file for NMSIS DSP Library + * @version V1.9.0 + * @date 23 April 2021 + * Target Processor: RISC-V Cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _FILTERING_FUNCTIONS_F16_H_ +#define _FILTERING_FUNCTIONS_F16_H_ + +#include "riscv_math_types_f16.h" +#include "riscv_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" + + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if defined(RISCV_FLOAT16_SUPPORTED) + + /** + * @brief Instance structure for the floating-point FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float16_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + const float16_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } riscv_fir_instance_f16; + + /** + * @brief Initialization function for the floating-point FIR filter. + * @param[in,out] S points to an instance of the floating-point FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void riscv_fir_init_f16( + riscv_fir_instance_f16 * S, + uint16_t numTaps, + const float16_t * pCoeffs, + float16_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the floating-point FIR filter. + * @param[in] S points to an instance of the floating-point FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void riscv_fir_f16( + const riscv_fir_instance_f16 * S, + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the floating-point Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float16_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + const float16_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + } riscv_biquad_casd_df1_inst_f16; + + + /** + * @brief Processing function for the floating-point Biquad cascade filter. + * @param[in] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void riscv_biquad_cascade_df1_f16( + const riscv_biquad_casd_df1_inst_f16 * S, + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize); + + + void riscv_biquad_cascade_df1_init_f16( + riscv_biquad_casd_df1_inst_f16 * S, + uint8_t numStages, + const float16_t * pCoeffs, + float16_t * pState); + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float16_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + const float16_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } riscv_biquad_cascade_df2T_instance_f16; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float16_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + const float16_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } riscv_biquad_cascade_stereo_df2T_instance_f16; + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void riscv_biquad_cascade_df2T_f16( + const riscv_biquad_cascade_df2T_instance_f16 * S, + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void riscv_biquad_cascade_stereo_df2T_f16( + const riscv_biquad_cascade_stereo_df2T_instance_f16 * S, + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void riscv_biquad_cascade_df2T_init_f16( + riscv_biquad_cascade_df2T_instance_f16 * S, + uint8_t numStages, + const float16_t * pCoeffs, + float16_t * pState); + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void riscv_biquad_cascade_stereo_df2T_init_f16( + riscv_biquad_cascade_stereo_df2T_instance_f16 * S, + uint8_t numStages, + const float16_t * pCoeffs, + float16_t * pState); + + /** + * @brief Correlation of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void riscv_correlate_f16( + const float16_t * pSrcA, + uint32_t srcALen, + const float16_t * pSrcB, + uint32_t srcBLen, + float16_t * pDst); + + +/** + @brief Levinson Durbin + @param[in] phi autocovariance vector starting with lag 0 (length is nbCoefs + 1) + @param[out] a autoregressive coefficients + @param[out] err prediction error (variance) + @param[in] nbCoefs number of autoregressive coefficients + @return none + */ +void riscv_levinson_durbin_f16(const float16_t *phi, + float16_t *a, + float16_t *err, + int nbCoefs); + +#endif /*defined(RISCV_FLOAT16_SUPPORTED)*/ +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _FILTERING_FUNCTIONS_F16_H_ */ diff --git a/components/nmsis/dsp/inc/dsp/interpolation_functions.h b/components/nmsis/dsp/inc/dsp/interpolation_functions.h new file mode 100644 index 00000000..6a0e9b57 --- /dev/null +++ b/components/nmsis/dsp/inc/dsp/interpolation_functions.h @@ -0,0 +1,320 @@ +/****************************************************************************** + * @file interpolation_functions.h + * @brief Public header file for NMSIS DSP Library + * @version V1.9.0 + * @date 23 April 2021 + * Target Processor: RISC-V Cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _INTERPOLATION_FUNCTIONS_H_ +#define _INTERPOLATION_FUNCTIONS_H_ + +#include "riscv_math_types.h" +#include "riscv_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** + * @defgroup groupInterpolation Interpolation Functions + * These functions perform 1- and 2-dimensional interpolation of data. + * Linear interpolation is used for 1-dimensional data and + * bilinear interpolation is used for 2-dimensional data. + */ + + + /** + * @brief Instance structure for the floating-point Linear Interpolate function. + */ + typedef struct + { + uint32_t nValues; /**< nValues */ + float32_t x1; /**< x1 */ + float32_t xSpacing; /**< xSpacing */ + float32_t *pYData; /**< pointer to the table of Y values */ + } riscv_linear_interp_instance_f32; + + /** + * @brief Instance structure for the floating-point bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + float32_t *pData; /**< points to the data table. */ + } riscv_bilinear_interp_instance_f32; + + /** + * @brief Instance structure for the Q31 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q31_t *pData; /**< points to the data table. */ + } riscv_bilinear_interp_instance_q31; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q15_t *pData; /**< points to the data table. */ + } riscv_bilinear_interp_instance_q15; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q7_t *pData; /**< points to the data table. */ + } riscv_bilinear_interp_instance_q7; + + + /** + * @brief Struct for specifying cubic spline type + */ + typedef enum + { + RISCV_SPLINE_NATURAL = 0, /**< Natural spline */ + RISCV_SPLINE_PARABOLIC_RUNOUT = 1 /**< Parabolic runout spline */ + } riscv_spline_type; + + /** + * @brief Instance structure for the floating-point cubic spline interpolation. + */ + typedef struct + { + riscv_spline_type type; /**< Type (boundary conditions) */ + const float32_t * x; /**< x values */ + const float32_t * y; /**< y values */ + uint32_t n_x; /**< Number of known data points */ + float32_t * coeffs; /**< Coefficients buffer (b,c, and d) */ + } riscv_spline_instance_f32; + + + + + /** + * @ingroup groupInterpolation + */ + + /** + * @addtogroup SplineInterpolate + * @{ + */ + + + /** + * @brief Processing function for the floating-point cubic spline interpolation. + * @param[in] S points to an instance of the floating-point spline structure. + * @param[in] xq points to the x values ot the interpolated data points. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples of output data. + */ + void riscv_spline_f32( + riscv_spline_instance_f32 * S, + const float32_t * xq, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point cubic spline interpolation. + * @param[in,out] S points to an instance of the floating-point spline structure. + * @param[in] type type of cubic spline interpolation (boundary conditions) + * @param[in] x points to the x values of the known data points. + * @param[in] y points to the y values of the known data points. + * @param[in] n number of known data points. + * @param[in] coeffs coefficients array for b, c, and d + * @param[in] tempBuffer buffer array for internal computations + */ + void riscv_spline_init_f32( + riscv_spline_instance_f32 * S, + riscv_spline_type type, + const float32_t * x, + const float32_t * y, + uint32_t n, + float32_t * coeffs, + float32_t * tempBuffer); + + + /** + * @} end of SplineInterpolate group + */ + + + + /** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ + float32_t riscv_linear_interp_f32( + riscv_linear_interp_instance_f32 * S, + float32_t x); + + /** + * + * @brief Process function for the Q31 Linear Interpolation Function. + * @param[in] pYData pointer to Q31 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + q31_t riscv_linear_interp_q31( + q31_t * pYData, + q31_t x, + uint32_t nValues); + + /** + * + * @brief Process function for the Q15 Linear Interpolation Function. + * @param[in] pYData pointer to Q15 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + q15_t riscv_linear_interp_q15( + q15_t * pYData, + q31_t x, + uint32_t nValues); + + /** + * + * @brief Process function for the Q7 Linear Interpolation Function. + * @param[in] pYData pointer to Q7 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + */ +q7_t riscv_linear_interp_q7( + q7_t * pYData, + q31_t x, + uint32_t nValues); + + /** + * @} end of LinearInterpolate group + */ + + + + + /** + * @ingroup groupInterpolation + */ + + + /** + * @addtogroup BilinearInterpolate + * @{ + */ + + /** + * @brief Floating-point bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate. + * @param[in] Y interpolation coordinate. + * @return out interpolated value. + */ + float32_t riscv_bilinear_interp_f32( + const riscv_bilinear_interp_instance_f32 * S, + float32_t X, + float32_t Y); + + /** + * @brief Q31 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + q31_t riscv_bilinear_interp_q31( + riscv_bilinear_interp_instance_q31 * S, + q31_t X, + q31_t Y); + + + /** + * @brief Q15 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + q15_t riscv_bilinear_interp_q15( + riscv_bilinear_interp_instance_q15 * S, + q31_t X, + q31_t Y); + + /** + * @brief Q7 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + q7_t riscv_bilinear_interp_q7( + riscv_bilinear_interp_instance_q7 * S, + q31_t X, + q31_t Y); + /** + * @} end of BilinearInterpolate group + */ + + + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _INTERPOLATION_FUNCTIONS_H_ */ diff --git a/components/nmsis/dsp/inc/dsp/interpolation_functions_f16.h b/components/nmsis/dsp/inc/dsp/interpolation_functions_f16.h new file mode 100644 index 00000000..0a061f46 --- /dev/null +++ b/components/nmsis/dsp/inc/dsp/interpolation_functions_f16.h @@ -0,0 +1,108 @@ +/****************************************************************************** + * @file interpolation_functions_f16.h + * @brief Public header file for NMSIS DSP Library + * @version V1.9.0 + * @date 23 April 2021 + * Target Processor: RISC-V Cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _INTERPOLATION_FUNCTIONS_F16_H_ +#define _INTERPOLATION_FUNCTIONS_F16_H_ + +#include "riscv_math_types_f16.h" +#include "riscv_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if defined(RISCV_FLOAT16_SUPPORTED) + +typedef struct +{ + uint32_t nValues; /**< nValues */ + float16_t x1; /**< x1 */ + float16_t xSpacing; /**< xSpacing */ + float16_t *pYData; /**< pointer to the table of Y values */ +} riscv_linear_interp_instance_f16; + +/** + * @brief Instance structure for the floating-point bilinear interpolation function. + */ +typedef struct +{ + uint16_t numRows;/**< number of rows in the data table. */ + uint16_t numCols;/**< number of columns in the data table. */ + float16_t *pData; /**< points to the data table. */ +} riscv_bilinear_interp_instance_f16; + + /** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ + float16_t riscv_linear_interp_f16( + riscv_linear_interp_instance_f16 * S, + float16_t x); + + /** + * @} end of LinearInterpolate group + */ + +/** + * @addtogroup BilinearInterpolate + * @{ + */ + + /** + * @brief Floating-point bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate. + * @param[in] Y interpolation coordinate. + * @return out interpolated value. + */ + float16_t riscv_bilinear_interp_f16( + const riscv_bilinear_interp_instance_f16 * S, + float16_t X, + float16_t Y); + + + /** + * @} end of BilinearInterpolate group + */ +#endif /*defined(RISCV_FLOAT16_SUPPORTED)*/ +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _INTERPOLATION_FUNCTIONS_F16_H_ */ diff --git a/components/nmsis/dsp/inc/dsp/matrix_functions.h b/components/nmsis/dsp/inc/dsp/matrix_functions.h new file mode 100644 index 00000000..d55a33cf --- /dev/null +++ b/components/nmsis/dsp/inc/dsp/matrix_functions.h @@ -0,0 +1,743 @@ +/****************************************************************************** + * @file matrix_functions.h + * @brief Public header file for NMSIS DSP Library + * @version V1.9.0 + * @date 23 April 2021 + * Target Processor: RISC-V Cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _MATRIX_FUNCTIONS_H_ +#define _MATRIX_FUNCTIONS_H_ + +#include "riscv_math_types.h" +#include "riscv_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + * @defgroup groupMatrix Matrix Functions + * + * This set of functions provides basic matrix math operations. + * The functions operate on matrix data structures. For example, + * the type + * definition for the floating-point matrix structure is shown + * below: + * 
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } riscv_matrix_instance_f32;
+ *
+ * There are similar definitions for Q15 and Q31 data types. + * + * The structure specifies the size of the matrix and then points to + * an array of data. The array is of size numRows X numCols + * and the values are arranged in row order. That is, the + * matrix element (i, j) is stored at: + * 
+ *     pData[i*numCols + j]
+ *
+ * + * \par Init Functions + * There is an associated initialization function for each type of matrix + * data structure. + * The initialization function sets the values of the internal structure fields. + * Refer to \ref riscv_mat_init_f32(), \ref riscv_mat_init_q31() and \ref riscv_mat_init_q15() + * for floating-point, Q31 and Q15 types, respectively. + * + * \par + * Use of the initialization function is optional. However, if initialization function is used + * then the instance structure cannot be placed into a const data section. + * To place the instance structure in a const data + * section, manually initialize the data structure. For example: + * 
+ * riscv_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * riscv_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * riscv_matrix_instance_q15 S = {nRows, nColumns, pData};
+ *
+ * where nRows specifies the number of rows, nColumns + * specifies the number of columns, and pData points to the + * data array. + * + * \par Size Checking + * By default all of the matrix functions perform size checking on the input and + * output matrices. For example, the matrix addition function verifies that the + * two input matrices and the output matrix all have the same number of rows and + * columns. If the size check fails the functions return: + * 
+ *     RISCV_MATH_SIZE_MISMATCH
+ *
+ * Otherwise the functions return + * 
+ *     RISCV_MATH_SUCCESS
+ *
+ * There is some overhead associated with this matrix size checking. + * The matrix size checking is enabled via the \#define + * 
+ *     RISCV_MATH_MATRIX_CHECK
+ *
+ * within the library project settings. By default this macro is defined + * and size checking is enabled. By changing the project settings and + * undefining this macro size checking is eliminated and the functions + * run a bit faster. With size checking disabled the functions always + * return RISCV_MATH_SUCCESS. + */ + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float32_t *pData; /**< points to the data of the matrix. */ + } riscv_matrix_instance_f32; + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float64_t *pData; /**< points to the data of the matrix. */ + } riscv_matrix_instance_f64; + + /** + * @brief Instance structure for the Q7 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q7_t *pData; /**< points to the data of the matrix. */ + } riscv_matrix_instance_q7; + + /** + * @brief Instance structure for the Q15 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q15_t *pData; /**< points to the data of the matrix. */ + } riscv_matrix_instance_q15; + + /** + * @brief Instance structure for the Q31 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q31_t *pData; /**< points to the data of the matrix. */ + } riscv_matrix_instance_q31; + + /** + * @brief Floating-point matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * RISCV_MATH_SIZE_MISMATCH or RISCV_MATH_SUCCESS based on the outcome of size checking. + */ +riscv_status riscv_mat_add_f32( + const riscv_matrix_instance_f32 * pSrcA, + const riscv_matrix_instance_f32 * pSrcB, + riscv_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * RISCV_MATH_SIZE_MISMATCH or RISCV_MATH_SUCCESS based on the outcome of size checking. + */ +riscv_status riscv_mat_add_q15( + const riscv_matrix_instance_q15 * pSrcA, + const riscv_matrix_instance_q15 * pSrcB, + riscv_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * RISCV_MATH_SIZE_MISMATCH or RISCV_MATH_SUCCESS based on the outcome of size checking. + */ +riscv_status riscv_mat_add_q31( + const riscv_matrix_instance_q31 * pSrcA, + const riscv_matrix_instance_q31 * pSrcB, + riscv_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * RISCV_MATH_SIZE_MISMATCH or RISCV_MATH_SUCCESS based on the outcome of size checking. + */ +riscv_status riscv_mat_cmplx_mult_f32( + const riscv_matrix_instance_f32 * pSrcA, + const riscv_matrix_instance_f32 * pSrcB, + riscv_matrix_instance_f32 * pDst); + + /** + * @brief Q15, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * RISCV_MATH_SIZE_MISMATCH or RISCV_MATH_SUCCESS based on the outcome of size checking. + */ +riscv_status riscv_mat_cmplx_mult_q15( + const riscv_matrix_instance_q15 * pSrcA, + const riscv_matrix_instance_q15 * pSrcB, + riscv_matrix_instance_q15 * pDst, + q15_t * pScratch); + + /** + * @brief Q31, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * RISCV_MATH_SIZE_MISMATCH or RISCV_MATH_SUCCESS based on the outcome of size checking. + */ +riscv_status riscv_mat_cmplx_mult_q31( + const riscv_matrix_instance_q31 * pSrcA, + const riscv_matrix_instance_q31 * pSrcB, + riscv_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either RISCV_MATH_SIZE_MISMATCH + * or RISCV_MATH_SUCCESS based on the outcome of size checking. + */ +riscv_status riscv_mat_trans_f32( + const riscv_matrix_instance_f32 * pSrc, + riscv_matrix_instance_f32 * pDst); + +/** + * @brief Floating-point matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either RISCV_MATH_SIZE_MISMATCH + * or RISCV_MATH_SUCCESS based on the outcome of size checking. + */ +riscv_status riscv_mat_trans_f64( + const riscv_matrix_instance_f64 * pSrc, + riscv_matrix_instance_f64 * pDst); + + /** + * @brief Floating-point complex matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either RISCV_MATH_SIZE_MISMATCH + * or RISCV_MATH_SUCCESS based on the outcome of size checking. + */ +riscv_status riscv_mat_cmplx_trans_f32( + const riscv_matrix_instance_f32 * pSrc, + riscv_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either RISCV_MATH_SIZE_MISMATCH + * or RISCV_MATH_SUCCESS based on the outcome of size checking. + */ +riscv_status riscv_mat_trans_q15( + const riscv_matrix_instance_q15 * pSrc, + riscv_matrix_instance_q15 * pDst); + + /** + * @brief Q15 complex matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either RISCV_MATH_SIZE_MISMATCH + * or RISCV_MATH_SUCCESS based on the outcome of size checking. + */ +riscv_status riscv_mat_cmplx_trans_q15( + const riscv_matrix_instance_q15 * pSrc, + riscv_matrix_instance_q15 * pDst); + + /** + * @brief Q7 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either RISCV_MATH_SIZE_MISMATCH + * or RISCV_MATH_SUCCESS based on the outcome of size checking. + */ +riscv_status riscv_mat_trans_q7( + const riscv_matrix_instance_q7 * pSrc, + riscv_matrix_instance_q7 * pDst); + + /** + * @brief Q31 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either RISCV_MATH_SIZE_MISMATCH + * or RISCV_MATH_SUCCESS based on the outcome of size checking. + */ +riscv_status riscv_mat_trans_q31( + const riscv_matrix_instance_q31 * pSrc, + riscv_matrix_instance_q31 * pDst); + + /** + * @brief Q31 complex matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either RISCV_MATH_SIZE_MISMATCH + * or RISCV_MATH_SUCCESS based on the outcome of size checking. + */ +riscv_status riscv_mat_cmplx_trans_q31( + const riscv_matrix_instance_q31 * pSrc, + riscv_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * RISCV_MATH_SIZE_MISMATCH or RISCV_MATH_SUCCESS based on the outcome of size checking. + */ +riscv_status riscv_mat_mult_f32( + const riscv_matrix_instance_f32 * pSrcA, + const riscv_matrix_instance_f32 * pSrcB, + riscv_matrix_instance_f32 * pDst); + + /** + * @brief Floating-point matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * RISCV_MATH_SIZE_MISMATCH or RISCV_MATH_SUCCESS based on the outcome of size checking. + */ +riscv_status riscv_mat_mult_f64( + const riscv_matrix_instance_f64 * pSrcA, + const riscv_matrix_instance_f64 * pSrcB, + riscv_matrix_instance_f64 * pDst); + + /** + * @brief Floating-point matrix and vector multiplication + * @param[in] pSrcMat points to the input matrix structure + * @param[in] pVec points to vector + * @param[out] pDst points to output vector + */ +void riscv_mat_vec_mult_f32( + const riscv_matrix_instance_f32 *pSrcMat, + const float32_t *pVec, + float32_t *pDst); + + /** + * @brief Q7 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * RISCV_MATH_SIZE_MISMATCH or RISCV_MATH_SUCCESS based on the outcome of size checking. + */ +riscv_status riscv_mat_mult_q7( + const riscv_matrix_instance_q7 * pSrcA, + const riscv_matrix_instance_q7 * pSrcB, + riscv_matrix_instance_q7 * pDst, + q7_t * pState); + + /** + * @brief Q7 matrix and vector multiplication + * @param[in] pSrcMat points to the input matrix structure + * @param[in] pVec points to vector + * @param[out] pDst points to output vector + */ +void riscv_mat_vec_mult_q7( + const riscv_matrix_instance_q7 *pSrcMat, + const q7_t *pVec, + q7_t *pDst); + + /** + * @brief Q15 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * RISCV_MATH_SIZE_MISMATCH or RISCV_MATH_SUCCESS based on the outcome of size checking. + */ +riscv_status riscv_mat_mult_q15( + const riscv_matrix_instance_q15 * pSrcA, + const riscv_matrix_instance_q15 * pSrcB, + riscv_matrix_instance_q15 * pDst, + q15_t * pState); + + /** + * @brief Q15 matrix and vector multiplication + * @param[in] pSrcMat points to the input matrix structure + * @param[in] pVec points to vector + * @param[out] pDst points to output vector + */ +void riscv_mat_vec_mult_q15( + const riscv_matrix_instance_q15 *pSrcMat, + const q15_t *pVec, + q15_t *pDst); + + /** + * @brief Q15 matrix multiplication (fast variant) for RISC-V Core with DSP enabled + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * RISCV_MATH_SIZE_MISMATCH or RISCV_MATH_SUCCESS based on the outcome of size checking. + */ +riscv_status riscv_mat_mult_fast_q15( + const riscv_matrix_instance_q15 * pSrcA, + const riscv_matrix_instance_q15 * pSrcB, + riscv_matrix_instance_q15 * pDst, + q15_t * pState); + + /** + * @brief Q31 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * RISCV_MATH_SIZE_MISMATCH or RISCV_MATH_SUCCESS based on the outcome of size checking. + */ +riscv_status riscv_mat_mult_q31( + const riscv_matrix_instance_q31 * pSrcA, + const riscv_matrix_instance_q31 * pSrcB, + riscv_matrix_instance_q31 * pDst); + + /** + * @brief Q31 matrix and vector multiplication + * @param[in] pSrcMat points to the input matrix structure + * @param[in] pVec points to vector + * @param[out] pDst points to output vector + */ +void riscv_mat_vec_mult_q31( + const riscv_matrix_instance_q31 *pSrcMat, + const q31_t *pVec, + q31_t *pDst); + + /** + * @brief Q31 matrix multiplication (fast variant) for RISC-V Core with DSP enabled + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * RISCV_MATH_SIZE_MISMATCH or RISCV_MATH_SUCCESS based on the outcome of size checking. + */ +riscv_status riscv_mat_mult_fast_q31( + const riscv_matrix_instance_q31 * pSrcA, + const riscv_matrix_instance_q31 * pSrcB, + riscv_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * RISCV_MATH_SIZE_MISMATCH or RISCV_MATH_SUCCESS based on the outcome of size checking. + */ +riscv_status riscv_mat_sub_f32( + const riscv_matrix_instance_f32 * pSrcA, + const riscv_matrix_instance_f32 * pSrcB, + riscv_matrix_instance_f32 * pDst); + + /** + * @brief Floating-point matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * RISCV_MATH_SIZE_MISMATCH or RISCV_MATH_SUCCESS based on the outcome of size checking. + */ +riscv_status riscv_mat_sub_f64( + const riscv_matrix_instance_f64 * pSrcA, + const riscv_matrix_instance_f64 * pSrcB, + riscv_matrix_instance_f64 * pDst); + + /** + * @brief Q15 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * RISCV_MATH_SIZE_MISMATCH or RISCV_MATH_SUCCESS based on the outcome of size checking. + */ +riscv_status riscv_mat_sub_q15( + const riscv_matrix_instance_q15 * pSrcA, + const riscv_matrix_instance_q15 * pSrcB, + riscv_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * RISCV_MATH_SIZE_MISMATCH or RISCV_MATH_SUCCESS based on the outcome of size checking. + */ +riscv_status riscv_mat_sub_q31( + const riscv_matrix_instance_q31 * pSrcA, + const riscv_matrix_instance_q31 * pSrcB, + riscv_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point matrix scaling. + * @param[in] pSrc points to the input matrix + * @param[in] scale scale factor + * @param[out] pDst points to the output matrix + * @return The function returns either + * RISCV_MATH_SIZE_MISMATCH or RISCV_MATH_SUCCESS based on the outcome of size checking. + */ +riscv_status riscv_mat_scale_f32( + const riscv_matrix_instance_f32 * pSrc, + float32_t scale, + riscv_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix + * @return The function returns either + * RISCV_MATH_SIZE_MISMATCH or RISCV_MATH_SUCCESS based on the outcome of size checking. + */ +riscv_status riscv_mat_scale_q15( + const riscv_matrix_instance_q15 * pSrc, + q15_t scaleFract, + int32_t shift, + riscv_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix structure + * @return The function returns either + * RISCV_MATH_SIZE_MISMATCH or RISCV_MATH_SUCCESS based on the outcome of size checking. + */ +riscv_status riscv_mat_scale_q31( + const riscv_matrix_instance_q31 * pSrc, + q31_t scaleFract, + int32_t shift, + riscv_matrix_instance_q31 * pDst); + + /** + * @brief Q31 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ +void riscv_mat_init_q31( + riscv_matrix_instance_q31 * S, + uint16_t nRows, + uint16_t nColumns, + q31_t * pData); + + /** + * @brief Q15 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ +void riscv_mat_init_q15( + riscv_matrix_instance_q15 * S, + uint16_t nRows, + uint16_t nColumns, + q15_t * pData); + + /** + * @brief Floating-point matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ +void riscv_mat_init_f32( + riscv_matrix_instance_f32 * S, + uint16_t nRows, + uint16_t nColumns, + float32_t * pData); + + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns RISCV_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status RISCV_MATH_SINGULAR. + */ + riscv_status riscv_mat_inverse_f32( + const riscv_matrix_instance_f32 * src, + riscv_matrix_instance_f32 * dst); + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns RISCV_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status RISCV_MATH_SINGULAR. + */ + riscv_status riscv_mat_inverse_f64( + const riscv_matrix_instance_f64 * src, + riscv_matrix_instance_f64 * dst); + + /** + * @brief Floating-point Cholesky decomposition of Symmetric Positive Definite Matrix. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns RISCV_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix does not have a decomposition, then the algorithm terminates and returns error status RISCV_MATH_DECOMPOSITION_FAILURE. + * If the matrix is ill conditioned or only semi-definite, then it is better using the LDL^t decomposition. + * The decomposition is returning a lower triangular matrix. + */ + riscv_status riscv_mat_cholesky_f64( + const riscv_matrix_instance_f64 * src, + riscv_matrix_instance_f64 * dst); + + /** + * @brief Floating-point Cholesky decomposition of Symmetric Positive Definite Matrix. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns RISCV_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix does not have a decomposition, then the algorithm terminates and returns error status RISCV_MATH_DECOMPOSITION_FAILURE. + * If the matrix is ill conditioned or only semi-definite, then it is better using the LDL^t decomposition. + * The decomposition is returning a lower triangular matrix. + */ + riscv_status riscv_mat_cholesky_f32( + const riscv_matrix_instance_f32 * src, + riscv_matrix_instance_f32 * dst); + + /** + * @brief Solve UT . X = A where UT is an upper triangular matrix + * @param[in] ut The upper triangular matrix + * @param[in] a The matrix a + * @param[out] dst The solution X of UT . X = A + * @return The function returns RISCV_MATH_SINGULAR, if the system can't be solved. + */ + riscv_status riscv_mat_solve_upper_triangular_f32( + const riscv_matrix_instance_f32 * ut, + const riscv_matrix_instance_f32 * a, + riscv_matrix_instance_f32 * dst); + + /** + * @brief Solve LT . X = A where LT is a lower triangular matrix + * @param[in] lt The lower triangular matrix + * @param[in] a The matrix a + * @param[out] dst The solution X of LT . X = A + * @return The function returns RISCV_MATH_SINGULAR, if the system can't be solved. + */ + riscv_status riscv_mat_solve_lower_triangular_f32( + const riscv_matrix_instance_f32 * lt, + const riscv_matrix_instance_f32 * a, + riscv_matrix_instance_f32 * dst); + + + /** + * @brief Solve UT . X = A where UT is an upper triangular matrix + * @param[in] ut The upper triangular matrix + * @param[in] a The matrix a + * @param[out] dst The solution X of UT . X = A + * @return The function returns RISCV_MATH_SINGULAR, if the system can't be solved. + */ + riscv_status riscv_mat_solve_upper_triangular_f64( + const riscv_matrix_instance_f64 * ut, + const riscv_matrix_instance_f64 * a, + riscv_matrix_instance_f64 * dst); + + /** + * @brief Solve LT . X = A where LT is a lower triangular matrix + * @param[in] lt The lower triangular matrix + * @param[in] a The matrix a + * @param[out] dst The solution X of LT . X = A + * @return The function returns RISCV_MATH_SINGULAR, if the system can't be solved. + */ + riscv_status riscv_mat_solve_lower_triangular_f64( + const riscv_matrix_instance_f64 * lt, + const riscv_matrix_instance_f64 * a, + riscv_matrix_instance_f64 * dst); + + + /** + * @brief Floating-point LDL decomposition of Symmetric Positive Semi-Definite Matrix. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] l points to the instance of the output floating-point triangular matrix structure. + * @param[out] d points to the instance of the output floating-point diagonal matrix structure. + * @param[out] p points to the instance of the output floating-point permutation vector. + * @return The function returns RISCV_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix does not have a decomposition, then the algorithm terminates and returns error status RISCV_MATH_DECOMPOSITION_FAILURE. + * The decomposition is returning a lower triangular matrix. + */ + riscv_status riscv_mat_ldlt_f32( + const riscv_matrix_instance_f32 * src, + riscv_matrix_instance_f32 * l, + riscv_matrix_instance_f32 * d, + uint16_t * pp); + + /** + * @brief Floating-point LDL decomposition of Symmetric Positive Semi-Definite Matrix. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] l points to the instance of the output floating-point triangular matrix structure. + * @param[out] d points to the instance of the output floating-point diagonal matrix structure. + * @param[out] p points to the instance of the output floating-point permutation vector. + * @return The function returns RISCV_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix does not have a decomposition, then the algorithm terminates and returns error status RISCV_MATH_DECOMPOSITION_FAILURE. + * The decomposition is returning a lower triangular matrix. + */ + riscv_status riscv_mat_ldlt_f64( + const riscv_matrix_instance_f64 * src, + riscv_matrix_instance_f64 * l, + riscv_matrix_instance_f64 * d, + uint16_t * pp); + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _MATRIX_FUNCTIONS_H_ */ diff --git a/components/nmsis/dsp/inc/dsp/matrix_functions_f16.h b/components/nmsis/dsp/inc/dsp/matrix_functions_f16.h new file mode 100644 index 00000000..ba5fbf7a --- /dev/null +++ b/components/nmsis/dsp/inc/dsp/matrix_functions_f16.h @@ -0,0 +1,222 @@ +/****************************************************************************** + * @file matrix_functions_f16.h + * @brief Public header file for NMSIS DSP Library + * @version V1.9.0 + * @date 23 April 2021 + * Target Processor: RISC-V Cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _MATRIX_FUNCTIONS_F16_H_ +#define _MATRIX_FUNCTIONS_F16_H_ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +#include "riscv_math_types_f16.h" +#include "riscv_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" + +#if defined(RISCV_FLOAT16_SUPPORTED) + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float16_t *pData; /**< points to the data of the matrix. */ + } riscv_matrix_instance_f16; + + /** + * @brief Floating-point matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * RISCV_MATH_SIZE_MISMATCH or RISCV_MATH_SUCCESS based on the outcome of size checking. + */ +riscv_status riscv_mat_add_f16( + const riscv_matrix_instance_f16 * pSrcA, + const riscv_matrix_instance_f16 * pSrcB, + riscv_matrix_instance_f16 * pDst); + + /** + * @brief Floating-point, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * RISCV_MATH_SIZE_MISMATCH or RISCV_MATH_SUCCESS based on the outcome of size checking. + */ +riscv_status riscv_mat_cmplx_mult_f16( + const riscv_matrix_instance_f16 * pSrcA, + const riscv_matrix_instance_f16 * pSrcB, + riscv_matrix_instance_f16 * pDst); + + /** + * @brief Floating-point matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either RISCV_MATH_SIZE_MISMATCH + * or RISCV_MATH_SUCCESS based on the outcome of size checking. + */ +riscv_status riscv_mat_trans_f16( + const riscv_matrix_instance_f16 * pSrc, + riscv_matrix_instance_f16 * pDst); + + /** + * @brief Floating-point complex matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either RISCV_MATH_SIZE_MISMATCH + * or RISCV_MATH_SUCCESS based on the outcome of size checking. + */ +riscv_status riscv_mat_cmplx_trans_f16( + const riscv_matrix_instance_f16 * pSrc, + riscv_matrix_instance_f16 * pDst); + + /** + * @brief Floating-point matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * RISCV_MATH_SIZE_MISMATCH or RISCV_MATH_SUCCESS based on the outcome of size checking. + */ +riscv_status riscv_mat_mult_f16( + const riscv_matrix_instance_f16 * pSrcA, + const riscv_matrix_instance_f16 * pSrcB, + riscv_matrix_instance_f16 * pDst); + /** + * @brief Floating-point matrix and vector multiplication + * @param[in] pSrcMat points to the input matrix structure + * @param[in] pVec points to vector + * @param[out] pDst points to output vector + */ +void riscv_mat_vec_mult_f16( + const riscv_matrix_instance_f16 *pSrcMat, + const float16_t *pVec, + float16_t *pDst); + + /** + * @brief Floating-point matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * RISCV_MATH_SIZE_MISMATCH or RISCV_MATH_SUCCESS based on the outcome of size checking. + */ +riscv_status riscv_mat_sub_f16( + const riscv_matrix_instance_f16 * pSrcA, + const riscv_matrix_instance_f16 * pSrcB, + riscv_matrix_instance_f16 * pDst); + + /** + * @brief Floating-point matrix scaling. + * @param[in] pSrc points to the input matrix + * @param[in] scale scale factor + * @param[out] pDst points to the output matrix + * @return The function returns either + * RISCV_MATH_SIZE_MISMATCH or RISCV_MATH_SUCCESS based on the outcome of size checking. + */ +riscv_status riscv_mat_scale_f16( + const riscv_matrix_instance_f16 * pSrc, + float16_t scale, + riscv_matrix_instance_f16 * pDst); + + /** + * @brief Floating-point matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ +void riscv_mat_init_f16( + riscv_matrix_instance_f16 * S, + uint16_t nRows, + uint16_t nColumns, + float16_t * pData); + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns RISCV_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status RISCV_MATH_SINGULAR. + */ + riscv_status riscv_mat_inverse_f16( + const riscv_matrix_instance_f16 * src, + riscv_matrix_instance_f16 * dst); + + + /** + * @brief Floating-point Cholesky decomposition of Symmetric Positive Definite Matrix. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns RISCV_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix does not have a decomposition, then the algorithm terminates and returns error status RISCV_MATH_DECOMPOSITION_FAILURE. + * If the matrix is ill conditioned or only semi-definite, then it is better using the LDL^t decomposition. + * The decomposition is returning a lower triangular matrix. + */ + riscv_status riscv_mat_cholesky_f16( + const riscv_matrix_instance_f16 * src, + riscv_matrix_instance_f16 * dst); + + /** + * @brief Solve UT . X = A where UT is an upper triangular matrix + * @param[in] ut The upper triangular matrix + * @param[in] a The matrix a + * @param[out] dst The solution X of UT . X = A + * @return The function returns RISCV_MATH_SINGULAR, if the system can't be solved. + */ + riscv_status riscv_mat_solve_upper_triangular_f16( + const riscv_matrix_instance_f16 * ut, + const riscv_matrix_instance_f16 * a, + riscv_matrix_instance_f16 * dst); + + /** + * @brief Solve LT . X = A where LT is a lower triangular matrix + * @param[in] lt The lower triangular matrix + * @param[in] a The matrix a + * @param[out] dst The solution X of LT . X = A + * @return The function returns RISCV_MATH_SINGULAR, if the system can't be solved. + */ + riscv_status riscv_mat_solve_lower_triangular_f16( + const riscv_matrix_instance_f16 * lt, + const riscv_matrix_instance_f16 * a, + riscv_matrix_instance_f16 * dst); + + + +#endif /*defined(RISCV_FLOAT16_SUPPORTED)*/ +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _MATRIX_FUNCTIONS_F16_H_ */ diff --git a/components/nmsis/dsp/inc/dsp/none.h b/components/nmsis/dsp/inc/dsp/none.h new file mode 100644 index 00000000..f5bba560 --- /dev/null +++ b/components/nmsis/dsp/inc/dsp/none.h @@ -0,0 +1,570 @@ +/****************************************************************************** + * @file none.h + * @brief Intrinsincs when no DSP extension available + * @version V1.9.0 + * @date 20. July 2020 + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + +Definitions in this file are allowing to reuse some versions of the +NMSIS-DSP to build on a core (M0 for instance) or a host where +DSP extension are not available. + +Ideally a pure C version should have been used instead. +But those are not always available or use a restricted set +of intrinsics. + +*/ + +#ifndef _NONE_H_ +#define _NONE_H_ + +#include "riscv_math_types.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + + + +/* + +Normally those kind of definitions are in a compiler file +in Core or Core_A. + +But for MSVC compiler it is a bit special. The goal is very specific +to NMSIS-DSP and only to allow the use of this library from other +systems like Python or Matlab. + +MSVC is not going to be used to cross-compile to ARM. So, having a MSVC +compiler file in Core or Core_A would not make sense. + +*/ +#if defined ( _MSC_VER ) || defined(__GNUC_PYTHON__) + __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } + + /** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +#endif + +/** + * @brief Clips Q63 to Q31 values. + */ + __STATIC_FORCEINLINE q31_t clip_q63_to_q31( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; + } + + /** + * @brief Clips Q63 to Q15 values. + */ + __STATIC_FORCEINLINE q15_t clip_q63_to_q15( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); + } + + /** + * @brief Clips Q31 to Q7 values. + */ + __STATIC_FORCEINLINE q7_t clip_q31_to_q7( + q31_t x) + { + return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? + ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; + } + + /** + * @brief Clips Q31 to Q15 values. + */ + __STATIC_FORCEINLINE q15_t clip_q31_to_q15( + q31_t x) + { + return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? + ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; + } + + /** + * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. + */ + __STATIC_FORCEINLINE q63_t mult32x64( + q63_t x, + q31_t y) + { + return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + + (((q63_t) (x >> 32) * y) ) ); + } + +/* SMMLAR */ +#define multAcc_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMLSR */ +#define multSub_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMULR */ +#define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) + +/* SMMLA */ +#define multAcc_32x32_keep32(a, x, y) \ + a += (q31_t) (((q63_t) x * y) >> 32) + +/* SMMLS */ +#define multSub_32x32_keep32(a, x, y) \ + a -= (q31_t) (((q63_t) x * y) >> 32) + +/* SMMUL */ +#define mult_32x32_keep32(a, x, y) \ + a = (q31_t) (((q63_t) x * y ) >> 32) + +#ifndef RISCV_MATH_DSP + /** + * @brief definition to pack two 16 bit values. + */ + #define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ + (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) + #define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ + (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) +#endif + + /** + * @brief definition to pack four 8 bit values. + */ + #define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) + + + + +/* + * @brief C custom defined intrinsic functions + */ +#if !defined (RISCV_MATH_DSP) + + + /* + * @brief C custom defined QADD8 + */ + __STATIC_FORCEINLINE uint32_t __QADD8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QSUB8 + */ + __STATIC_FORCEINLINE uint32_t __QSUB8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QADD16 + */ + __STATIC_FORCEINLINE uint32_t __QADD16( + uint32_t x, + uint32_t y) + { +/* q31_t r, s; without initialisation 'riscv_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */ + q31_t r = 0, s = 0; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHADD16 + */ + __STATIC_FORCEINLINE uint32_t __SHADD16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSUB16 + */ + __STATIC_FORCEINLINE uint32_t __QSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSUB16 + */ + __STATIC_FORCEINLINE uint32_t __SHSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QASX + */ + __STATIC_FORCEINLINE uint32_t __QASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHASX + */ + __STATIC_FORCEINLINE uint32_t __SHASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSAX + */ + __STATIC_FORCEINLINE uint32_t __QSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSAX + */ + __STATIC_FORCEINLINE uint32_t __SHSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SMUSDX + */ + __STATIC_FORCEINLINE uint32_t __SMUSDX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + /* + * @brief C custom defined SMUADX + */ + __STATIC_FORCEINLINE uint32_t __SMUADX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + + /* + * @brief C custom defined QADD + */ + __STATIC_FORCEINLINE int32_t __QADD( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y))); + } + + + /* + * @brief C custom defined QSUB + */ + __STATIC_FORCEINLINE int32_t __QSUB( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y))); + } + + + /* + * @brief C custom defined SMLAD + */ + __STATIC_FORCEINLINE uint32_t __SMLAD( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLADX + */ + __STATIC_FORCEINLINE uint32_t __SMLADX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLSDX + */ + __STATIC_FORCEINLINE uint32_t __SMLSDX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALD + */ + __STATIC_FORCEINLINE uint64_t __SMLALD( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALDX + */ + __STATIC_FORCEINLINE uint64_t __SMLALDX( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMUAD + */ + __STATIC_FORCEINLINE uint32_t __SMUAD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SMUSD + */ + __STATIC_FORCEINLINE uint32_t __SMUSD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SXTB16 + */ + __STATIC_FORCEINLINE uint32_t __SXTB16( + uint32_t x) + { + return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) | + ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) )); + } + + /* + * @brief C custom defined SMMLA + */ + __STATIC_FORCEINLINE int32_t __SMMLA( + int32_t x, + int32_t y, + int32_t sum) + { + return (sum + (int32_t) (((int64_t) x * y) >> 32)); + } + +#endif /* !defined (RISCV_MATH_DSP) */ + + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _TRANSFORM_FUNCTIONS_H_ */ diff --git a/components/nmsis/dsp/inc/dsp/quaternion_math_functions.h b/components/nmsis/dsp/inc/dsp/quaternion_math_functions.h new file mode 100644 index 00000000..7f26ebd0 --- /dev/null +++ b/components/nmsis/dsp/inc/dsp/quaternion_math_functions.h @@ -0,0 +1,160 @@ +/****************************************************************************** + * @file quaternion_math_functions.h + * @brief Public header file for NMSIS DSP Library + * @version V1.9.0 + * @date 23 April 2021 + * + * Target Processor: RISC-V Cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _QUATERNION_MATH_FUNCTIONS_H_ +#define _QUATERNION_MATH_FUNCTIONS_H_ + +#include "riscv_math_types.h" +#include "riscv_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" + + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + * @defgroup groupQuaternionMath Quaternion Math Functions + * Functions to operates on quaternions and convert between a + * rotation and quaternion representation. + */ + + +/** + @brief Floating-point quaternion Norm. + @param[in] pInputQuaternions points to the input vector of quaternions + @param[out] pNorms points to the output vector of norms + @param[in] nbQuaternions number of quaternions in each vector + @return none + */ + + + +void riscv_quaternion_norm_f32(const float32_t *pInputQuaternions, + float32_t *pNorms, + uint32_t nbQuaternions); + + +/** + @brief Floating-point quaternion inverse. + @param[in] pInputQuaternions points to the input vector of quaternions + @param[out] pInverseQuaternions points to the output vector of inverse quaternions + @param[in] nbQuaternions number of quaternions in each vector + @return none + */ + +void riscv_quaternion_inverse_f32(const float32_t *pInputQuaternions, + float32_t *pInverseQuaternions, + uint32_t nbQuaternions); + +/** + @brief Floating-point quaternion conjugates. + @param[in] pInputQuaternions points to the input vector of quaternions + @param[out] pConjugateQuaternions points to the output vector of conjugate quaternions + @param[in] nbQuaternions number of quaternions in each vector + @return none + */ +void riscv_quaternion_conjugate_f32(const float32_t *inputQuaternions, + float32_t *pConjugateQuaternions, + uint32_t nbQuaternions); + +/** + @brief Floating-point normalization of quaternions. + @param[in] pInputQuaternions points to the input vector of quaternions + @param[out] pNormalizedQuaternions points to the output vector of normalized quaternions + @param[in] nbQuaternions number of quaternions in each vector + @return none + */ +void riscv_quaternion_normalize_f32(const float32_t *inputQuaternions, + float32_t *pNormalizedQuaternions, + uint32_t nbQuaternions); + + +/** + @brief Floating-point product of two quaternions. + @param[in] qa First quaternion + @param[in] qb Second quaternion + @param[out] r Product of two quaternions + @return none + */ +void riscv_quaternion_product_single_f32(const float32_t *qa, + const float32_t *qb, + float32_t *r); + +/** + @brief Floating-point elementwise product two quaternions. + @param[in] qa First array of quaternions + @param[in] qb Second array of quaternions + @param[out] r Elementwise product of quaternions + @param[in] nbQuaternions Number of quaternions in the array + @return none + */ +void riscv_quaternion_product_f32(const float32_t *qa, + const float32_t *qb, + float32_t *r, + uint32_t nbQuaternions); + +/** + * @brief Conversion of quaternion to equivalent rotation matrix. + * @param[in] pInputQuaternions points to an array of normalized quaternions + * @param[out] pOutputRotations points to an array of 3x3 rotations (in row order) + * @param[in] nbQuaternions in the array + * @return none. + * + * Format of rotation matrix + * \par + * The quaternion a + ib + jc + kd is converted into rotation matrix: + * a^2 + b^2 - c^2 - d^2 2bc - 2ad 2bd + 2ac + * 2bc + 2ad a^2 - b^2 + c^2 - d^2 2cd - 2ab + * 2bd - 2ac 2cd + 2ab a^2 - b^2 - c^2 + d^2 + * + * Rotation matrix is saved in row order : R00 R01 R02 R10 R11 R12 R20 R21 R22 + */ +void riscv_quaternion2rotation_f32(const float32_t *pInputQuaternions, + float32_t *pOutputRotations, + uint32_t nbQuaternions); + +/** + * @brief Conversion of a rotation matrix to equivalent quaternion. + * @param[in] pInputRotations points to an array 3x3 rotation matrix (in row order) + * @param[out] pOutputQuaternions points to an array of quaternions + * @param[in] nbQuaternions in the array + * @return none. +*/ +void riscv_rotation2quaternion_f32(const float32_t *pInputRotations, + float32_t *pOutputQuaternions, + uint32_t nbQuaternions); + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _QUATERNION_MATH_FUNCTIONS_H_ */ diff --git a/components/nmsis/dsp/inc/dsp/statistics_functions.h b/components/nmsis/dsp/inc/dsp/statistics_functions.h new file mode 100644 index 00000000..dff31d72 --- /dev/null +++ b/components/nmsis/dsp/inc/dsp/statistics_functions.h @@ -0,0 +1,587 @@ +/****************************************************************************** + * @file statistics_functions.h + * @brief Public header file for NMSIS DSP Library + * @version V1.9.0 + * @date 23 April 2021 + * Target Processor: RISC-V Cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _STATISTICS_FUNCTIONS_H_ +#define _STATISTICS_FUNCTIONS_H_ + +#include "riscv_math_types.h" +#include "riscv_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" + +#include "dsp/basic_math_functions.h" +#include "dsp/fast_math_functions.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** + * @defgroup groupStats Statistics Functions + */ + +/** + * @brief Computation of the LogSumExp + * + * In probabilistic computations, the dynamic of the probability values can be very + * wide because they come from gaussian functions. + * To avoid underflow and overflow issues, the values are represented by their log. + * In this representation, multiplying the original exp values is easy : their logs are added. + * But adding the original exp values is requiring some special handling and it is the + * goal of the LogSumExp function. + * + * If the values are x1...xn, the function is computing: + * + * ln(exp(x1) + ... + exp(xn)) and the computation is done in such a way that + * rounding issues are minimised. + * + * The max xm of the values is extracted and the function is computing: + * xm + ln(exp(x1 - xm) + ... + exp(xn - xm)) + * + * @param[in] *in Pointer to an array of input values. + * @param[in] blockSize Number of samples in the input array. + * @return LogSumExp + * + */ + + +float32_t riscv_logsumexp_f32(const float32_t *in, uint32_t blockSize); + +/** + * @brief Dot product with log arithmetic + * + * Vectors are containing the log of the samples + * + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[in] pTmpBuffer temporary buffer of length blockSize + * @return The log of the dot product . + * + */ + + +float32_t riscv_logsumexp_dot_prod_f32(const float32_t * pSrcA, + const float32_t * pSrcB, + uint32_t blockSize, + float32_t *pTmpBuffer); + +/** + * @brief Entropy + * + * @param[in] pSrcA Array of input values. + * @param[in] blockSize Number of samples in the input array. + * @return Entropy -Sum(p ln p) + * + */ + + +float32_t riscv_entropy_f32(const float32_t * pSrcA,uint32_t blockSize); + + +/** + * @brief Entropy + * + * @param[in] pSrcA Array of input values. + * @param[in] blockSize Number of samples in the input array. + * @return Entropy -Sum(p ln p) + * + */ + + +float64_t riscv_entropy_f64(const float64_t * pSrcA, uint32_t blockSize); + + +/** + * @brief Kullback-Leibler + * + * @param[in] pSrcA Pointer to an array of input values for probability distribution A. + * @param[in] pSrcB Pointer to an array of input values for probability distribution B. + * @param[in] blockSize Number of samples in the input array. + * @return Kullback-Leibler Divergence D(A || B) + * + */ +float32_t riscv_kullback_leibler_f32(const float32_t * pSrcA + ,const float32_t * pSrcB + ,uint32_t blockSize); + + +/** + * @brief Kullback-Leibler + * + * @param[in] pSrcA Pointer to an array of input values for probability distribution A. + * @param[in] pSrcB Pointer to an array of input values for probability distribution B. + * @param[in] blockSize Number of samples in the input array. + * @return Kullback-Leibler Divergence D(A || B) + * + */ +float64_t riscv_kullback_leibler_f64(const float64_t * pSrcA, + const float64_t * pSrcB, + uint32_t blockSize); + + + /** + * @brief Sum of the squares of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void riscv_power_q31( + const q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void riscv_power_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void riscv_power_q15( + const q15_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void riscv_power_q7( + const q7_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void riscv_mean_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult); + + + /** + * @brief Mean value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void riscv_mean_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Mean value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void riscv_mean_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void riscv_mean_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Variance of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void riscv_var_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Variance of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void riscv_var_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Variance of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void riscv_var_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void riscv_rms_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void riscv_rms_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void riscv_rms_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Standard deviation of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void riscv_std_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void riscv_std_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void riscv_std_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + + /** + * @brief Minimum value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] result is output pointer + * @param[in] index is the array index of the minimum value in the input buffer. + */ + void riscv_min_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * result, + uint32_t * index); + + /** + * @brief Minimum value of absolute values of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] result is output pointer + * @param[in] index is the array index of the minimum value in the input buffer. + */ + void riscv_absmin_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * result, + uint32_t * index); + + + /** + * @brief Minimum value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[in] pIndex is the array index of the minimum value in the input buffer. + */ + void riscv_min_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + +/** + * @brief Minimum value of absolute values of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[in] pIndex is the array index of the minimum value in the input buffer. + */ + void riscv_absmin_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Minimum value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void riscv_min_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + /** + * @brief Minimum value of absolute values of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void riscv_absmin_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Minimum value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void riscv_min_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + /** + * @brief Minimum value of absolute values of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void riscv_absmin_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q7 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void riscv_max_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of absolute values of a Q7 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void riscv_absmax_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q15 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void riscv_max_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of absolute values of a Q15 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void riscv_absmax_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a Q31 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void riscv_max_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of absolute values of a Q31 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void riscv_absmax_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a floating-point vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void riscv_max_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of absolute values of a floating-point vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void riscv_absmax_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + /** + @brief Maximum value of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @return none + */ + void riscv_max_no_idx_f32( + const float32_t *pSrc, + uint32_t blockSize, + float32_t *pResult); + + + + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _STATISTICS_FUNCTIONS_H_ */ diff --git a/components/nmsis/dsp/inc/dsp/statistics_functions_f16.h b/components/nmsis/dsp/inc/dsp/statistics_functions_f16.h new file mode 100644 index 00000000..678da419 --- /dev/null +++ b/components/nmsis/dsp/inc/dsp/statistics_functions_f16.h @@ -0,0 +1,219 @@ +/****************************************************************************** + * @file statistics_functions_f16.h + * @brief Public header file for NMSIS DSP Library + * @version V1.9.0 + * @date 23 April 2021 + * Target Processor: RISC-V Cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _STATISTICS_FUNCTIONS_F16_H_ +#define _STATISTICS_FUNCTIONS_F16_H_ + +#include "riscv_math_types_f16.h" +#include "riscv_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" + +#include "dsp/basic_math_functions_f16.h" +#include "dsp/fast_math_functions_f16.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if defined(RISCV_FLOAT16_SUPPORTED) + + /** + * @brief Sum of the squares of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void riscv_power_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult); + + /** + * @brief Mean value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void riscv_mean_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult); + + /** + * @brief Variance of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void riscv_var_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult); + + /** + * @brief Root Mean Square of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void riscv_rms_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult); + + /** + * @brief Standard deviation of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void riscv_std_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult); + + /** + * @brief Minimum value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void riscv_min_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult, + uint32_t * pIndex); + + /** + * @brief Minimum value of absolute values of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void riscv_absmin_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a floating-point vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void riscv_max_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of absolute values of a floating-point vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void riscv_absmax_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult, + uint32_t * pIndex); + +/** + * @brief Entropy + * + * @param[in] pSrcA Array of input values. + * @param[in] blockSize Number of samples in the input array. + * @return Entropy -Sum(p ln p) + * + */ + + +float16_t riscv_entropy_f16(const float16_t * pSrcA,uint32_t blockSize); + +float16_t riscv_logsumexp_f16(const float16_t *in, uint32_t blockSize); + +/** + * @brief Dot product with log arithmetic + * + * Vectors are containing the log of the samples + * + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[in] pTmpBuffer temporary buffer of length blockSize + * @return The log of the dot product . + * + */ + + +float16_t riscv_logsumexp_dot_prod_f16(const float16_t * pSrcA, + const float16_t * pSrcB, + uint32_t blockSize, + float16_t *pTmpBuffer); + +/** + * @brief Kullback-Leibler + * + * @param[in] pSrcA Pointer to an array of input values for probability distribution A. + * @param[in] pSrcB Pointer to an array of input values for probability distribution B. + * @param[in] blockSize Number of samples in the input array. + * @return Kullback-Leibler Divergence D(A || B) + * + */ +float16_t riscv_kullback_leibler_f16(const float16_t * pSrcA + ,const float16_t * pSrcB + ,uint32_t blockSize); + +/** + @brief Maximum value of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @return none + */ + void riscv_max_no_idx_f16( + const float16_t *pSrc, + uint32_t blockSize, + float16_t *pResult); + + + +#endif /*defined(RISCV_FLOAT16_SUPPORTED)*/ +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _STATISTICS_FUNCTIONS_F16_H_ */ diff --git a/components/nmsis/dsp/inc/dsp/support_functions.h b/components/nmsis/dsp/inc/dsp/support_functions.h new file mode 100644 index 00000000..8621b037 --- /dev/null +++ b/components/nmsis/dsp/inc/dsp/support_functions.h @@ -0,0 +1,428 @@ +/****************************************************************************** + * @file support_functions.h + * @brief Public header file for NMSIS DSP Library + * @version V1.9.0 + * @date 23 April 2021 + * Target Processor: RISC-V Cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _SUPPORT_FUNCTIONS_H_ +#define _SUPPORT_FUNCTIONS_H_ + +#include "riscv_math_types.h" +#include "riscv_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + * @defgroup groupSupport Support Functions + */ + + +/** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q31 output vector + * @param[in] blockSize length of the input vector + */ + void riscv_float_to_q31( + const float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q15 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + */ + void riscv_float_to_q15( + const float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q7 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q7 output vector + * @param[in] blockSize length of the input vector + */ + void riscv_float_to_q7( + const float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void riscv_q31_to_float( + const q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q15 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void riscv_q31_to_q15( + const q31_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void riscv_q31_to_q7( + const q31_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void riscv_q15_to_float( + const q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q31 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void riscv_q15_to_q31( + const q15_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void riscv_q15_to_q7( + const q15_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q7 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void riscv_q7_to_float( + const q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q7 vector to Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void riscv_q7_to_q31( + const q7_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q7 vector to Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void riscv_q7_to_q15( + const q7_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + + + + /** + * @brief Struct for specifying sorting algorithm + */ + typedef enum + { + RISCV_SORT_BITONIC = 0, + /**< Bitonic sort */ + RISCV_SORT_BUBBLE = 1, + /**< Bubble sort */ + RISCV_SORT_HEAP = 2, + /**< Heap sort */ + RISCV_SORT_INSERTION = 3, + /**< Insertion sort */ + RISCV_SORT_QUICK = 4, + /**< Quick sort */ + RISCV_SORT_SELECTION = 5 + /**< Selection sort */ + } riscv_sort_alg; + + /** + * @brief Struct for specifying sorting algorithm + */ + typedef enum + { + RISCV_SORT_DESCENDING = 0, + /**< Descending order (9 to 0) */ + RISCV_SORT_ASCENDING = 1 + /**< Ascending order (0 to 9) */ + } riscv_sort_dir; + + /** + * @brief Instance structure for the sorting algorithms. + */ + typedef struct + { + riscv_sort_alg alg; /**< Sorting algorithm selected */ + riscv_sort_dir dir; /**< Sorting order (direction) */ + } riscv_sort_instance_f32; + + /** + * @param[in] S points to an instance of the sorting structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void riscv_sort_f32( + const riscv_sort_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @param[in,out] S points to an instance of the sorting structure. + * @param[in] alg Selected algorithm. + * @param[in] dir Sorting order. + */ + void riscv_sort_init_f32( + riscv_sort_instance_f32 * S, + riscv_sort_alg alg, + riscv_sort_dir dir); + + /** + * @brief Instance structure for the sorting algorithms. + */ + typedef struct + { + riscv_sort_dir dir; /**< Sorting order (direction) */ + float32_t * buffer; /**< Working buffer */ + } riscv_merge_sort_instance_f32; + + /** + * @param[in] S points to an instance of the sorting structure. + * @param[in,out] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void riscv_merge_sort_f32( + const riscv_merge_sort_instance_f32 * S, + float32_t *pSrc, + float32_t *pDst, + uint32_t blockSize); + + /** + * @param[in,out] S points to an instance of the sorting structure. + * @param[in] dir Sorting order. + * @param[in] buffer Working buffer. + */ + void riscv_merge_sort_init_f32( + riscv_merge_sort_instance_f32 * S, + riscv_sort_dir dir, + float32_t * buffer); + + + + /** + * @brief Copies the elements of a floating-point vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void riscv_copy_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q7 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void riscv_copy_q7( + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void riscv_copy_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void riscv_copy_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a floating-point vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void riscv_fill_f32( + float32_t value, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q7 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void riscv_fill_q7( + q7_t value, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q15 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void riscv_fill_q15( + q15_t value, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q31 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void riscv_fill_q31( + q31_t value, + q31_t * pDst, + uint32_t blockSize); + + + + + + + +/** + * @brief Weighted sum + * + * + * @param[in] *in Array of input values. + * @param[in] *weigths Weights + * @param[in] blockSize Number of samples in the input array. + * @return Weighted sum + * + */ +float32_t riscv_weighted_sum_f32(const float32_t *in + , const float32_t *weigths + , uint32_t blockSize); + + +/** + * @brief Barycenter + * + * + * @param[in] in List of vectors + * @param[in] weights Weights of the vectors + * @param[out] out Barycenter + * @param[in] nbVectors Number of vectors + * @param[in] vecDim Dimension of space (vector dimension) + * @return None + * + */ +void riscv_barycenter_f32(const float32_t *in + , const float32_t *weights + , float32_t *out + , uint32_t nbVectors + , uint32_t vecDim); + + + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _SUPPORT_FUNCTIONS_H_ */ diff --git a/components/nmsis/dsp/inc/dsp/support_functions_f16.h b/components/nmsis/dsp/inc/dsp/support_functions_f16.h new file mode 100644 index 00000000..11c10f42 --- /dev/null +++ b/components/nmsis/dsp/inc/dsp/support_functions_f16.h @@ -0,0 +1,130 @@ +/****************************************************************************** + * @file support_functions_f16.h + * @brief Public header file for NMSIS DSP Library + * @version V1.9.0 + * @date 23 April 2021 + * Target Processor: RISC-V Cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _SUPPORT_FUNCTIONS_F16_H_ +#define _SUPPORT_FUNCTIONS_F16_H_ + +#include "riscv_math_types_f16.h" +#include "riscv_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if defined(RISCV_FLOAT16_SUPPORTED) + + /** + * @brief Copies the elements of a floating-point vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ +void riscv_copy_f16(const float16_t * pSrc, float16_t * pDst, uint32_t blockSize); + + /** + * @brief Fills a constant value into a floating-point vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ +void riscv_fill_f16(float16_t value, float16_t * pDst, uint32_t blockSize); + +/** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] pSrc points to the f16 input vector + * @param[out] pDst points to the q15 output vector + * @param[in] blockSize length of the input vector + */ +void riscv_f16_to_q15(const float16_t * pSrc, q15_t * pDst, uint32_t blockSize); + +/** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] pSrc points to the q15 input vector + * @param[out] pDst points to the f16 output vector + * @param[in] blockSize length of the input vector + */ +void riscv_q15_to_f16(const q15_t * pSrc, float16_t * pDst, uint32_t blockSize); + + +/** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] pSrc points to the f32 input vector + * @param[out] pDst points to the f16 output vector + * @param[in] blockSize length of the input vector + */ +void riscv_float_to_f16(const float32_t * pSrc, float16_t * pDst, uint32_t blockSize); + +/** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] pSrc points to the f16 input vector + * @param[out] pDst points to the f32 output vector + * @param[in] blockSize length of the input vector + */ +void riscv_f16_to_float(const float16_t * pSrc, float32_t * pDst, uint32_t blockSize); + +/** + * @brief Weighted sum + * + * + * @param[in] *in Array of input values. + * @param[in] *weigths Weights + * @param[in] blockSize Number of samples in the input array. + * @return Weighted sum + * + */ +float16_t riscv_weighted_sum_f16(const float16_t *in + , const float16_t *weigths + , uint32_t blockSize); + +/** + * @brief Barycenter + * + * + * @param[in] in List of vectors + * @param[in] weights Weights of the vectors + * @param[out] out Barycenter + * @param[in] nbVectors Number of vectors + * @param[in] vecDim Dimension of space (vector dimension) + * @return None + * + */ +void riscv_barycenter_f16(const float16_t *in + , const float16_t *weights + , float16_t *out + , uint32_t nbVectors + , uint32_t vecDim); + +#endif /*defined(RISCV_FLOAT16_SUPPORTED)*/ +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _SUPPORT_FUNCTIONS_F16_H_ */ diff --git a/components/nmsis/dsp/inc/dsp/svm_defines.h b/components/nmsis/dsp/inc/dsp/svm_defines.h new file mode 100644 index 00000000..7f739512 --- /dev/null +++ b/components/nmsis/dsp/inc/dsp/svm_defines.h @@ -0,0 +1,47 @@ +/****************************************************************************** + * @file svm_defines.h + * @brief Public header file for NMSIS DSP Library + * @version V1.9.0 + * @date 23 April 2021 + * + * Target Processor: RISC-V Cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _SVM_DEFINES_H_ +#define _SVM_DEFINES_H_ + +/** + * @brief Struct for specifying SVM Kernel + */ +typedef enum +{ + RISCV_ML_KERNEL_LINEAR = 0, + /**< Linear kernel */ + RISCV_ML_KERNEL_POLYNOMIAL = 1, + /**< Polynomial kernel */ + RISCV_ML_KERNEL_RBF = 2, + /**< Radial Basis Function kernel */ + RISCV_ML_KERNEL_SIGMOID = 3 + /**< Sigmoid kernel */ +} riscv_ml_kernel_type; + +#endif diff --git a/components/nmsis/dsp/inc/dsp/svm_functions.h b/components/nmsis/dsp/inc/dsp/svm_functions.h new file mode 100644 index 00000000..060919ae --- /dev/null +++ b/components/nmsis/dsp/inc/dsp/svm_functions.h @@ -0,0 +1,300 @@ +/****************************************************************************** + * @file svm_functions.h + * @brief Public header file for NMSIS DSP Library + * @version V1.9.0 + * @date 23 April 2021 + * Target Processor: RISC-V Cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _SVM_FUNCTIONS_H_ +#define _SVM_FUNCTIONS_H_ + +#include "riscv_math_types.h" +#include "riscv_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" +#include "dsp/svm_defines.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#define STEP(x) (x) <= 0 ? 0 : 1 + +/** + * @defgroup groupSVM SVM Functions + * This set of functions is implementing SVM classification on 2 classes. + * The training must be done from scikit-learn. The parameters can be easily + * generated from the scikit-learn object. Some examples are given in + * DSP/Testing/PatternGeneration/SVM.py + * + * If more than 2 classes are needed, the functions in this folder + * will have to be used, as building blocks, to do multi-class classification. + * + * No multi-class classification is provided in this SVM folder. + * + */ + +/** + * @brief Integer exponentiation + * @param[in] x value + * @param[in] nb integer exponent >= 1 + * @return x^nb + * + */ +__STATIC_INLINE float32_t riscv_exponent_f32(float32_t x, int32_t nb) +{ + float32_t r = x; + nb --; + while(nb > 0) + { + r = r * x; + nb--; + } + return(r); +} + + + + + +/** + * @brief Instance structure for linear SVM prediction function. + */ +typedef struct +{ + uint32_t nbOfSupportVectors; /**< Number of support vectors */ + uint32_t vectorDimension; /**< Dimension of vector space */ + float32_t intercept; /**< Intercept */ + const float32_t *dualCoefficients; /**< Dual coefficients */ + const float32_t *supportVectors; /**< Support vectors */ + const int32_t *classes; /**< The two SVM classes */ +} riscv_svm_linear_instance_f32; + + +/** + * @brief Instance structure for polynomial SVM prediction function. + */ +typedef struct +{ + uint32_t nbOfSupportVectors; /**< Number of support vectors */ + uint32_t vectorDimension; /**< Dimension of vector space */ + float32_t intercept; /**< Intercept */ + const float32_t *dualCoefficients; /**< Dual coefficients */ + const float32_t *supportVectors; /**< Support vectors */ + const int32_t *classes; /**< The two SVM classes */ + int32_t degree; /**< Polynomial degree */ + float32_t coef0; /**< Polynomial constant */ + float32_t gamma; /**< Gamma factor */ +} riscv_svm_polynomial_instance_f32; + +/** + * @brief Instance structure for rbf SVM prediction function. + */ +typedef struct +{ + uint32_t nbOfSupportVectors; /**< Number of support vectors */ + uint32_t vectorDimension; /**< Dimension of vector space */ + float32_t intercept; /**< Intercept */ + const float32_t *dualCoefficients; /**< Dual coefficients */ + const float32_t *supportVectors; /**< Support vectors */ + const int32_t *classes; /**< The two SVM classes */ + float32_t gamma; /**< Gamma factor */ +} riscv_svm_rbf_instance_f32; + +/** + * @brief Instance structure for sigmoid SVM prediction function. + */ +typedef struct +{ + uint32_t nbOfSupportVectors; /**< Number of support vectors */ + uint32_t vectorDimension; /**< Dimension of vector space */ + float32_t intercept; /**< Intercept */ + const float32_t *dualCoefficients; /**< Dual coefficients */ + const float32_t *supportVectors; /**< Support vectors */ + const int32_t *classes; /**< The two SVM classes */ + float32_t coef0; /**< Independent constant */ + float32_t gamma; /**< Gamma factor */ +} riscv_svm_sigmoid_instance_f32; + +/** + * @brief SVM linear instance init function + * @param[in] S Parameters for SVM functions + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @return none. + * + */ + + +void riscv_svm_linear_init_f32(riscv_svm_linear_instance_f32 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float32_t intercept, + const float32_t *dualCoefficients, + const float32_t *supportVectors, + const int32_t *classes); + +/** + * @brief SVM linear prediction + * @param[in] S Pointer to an instance of the linear SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult Decision value + * @return none. + * + */ + +void riscv_svm_linear_predict_f32(const riscv_svm_linear_instance_f32 *S, + const float32_t * in, + int32_t * pResult); + + +/** + * @brief SVM polynomial instance init function + * @param[in] S points to an instance of the polynomial SVM structure. + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @param[in] degree Polynomial degree + * @param[in] coef0 coeff0 (scikit-learn terminology) + * @param[in] gamma gamma (scikit-learn terminology) + * @return none. + * + */ + + +void riscv_svm_polynomial_init_f32(riscv_svm_polynomial_instance_f32 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float32_t intercept, + const float32_t *dualCoefficients, + const float32_t *supportVectors, + const int32_t *classes, + int32_t degree, + float32_t coef0, + float32_t gamma + ); + +/** + * @brief SVM polynomial prediction + * @param[in] S Pointer to an instance of the polynomial SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult Decision value + * @return none. + * + */ +void riscv_svm_polynomial_predict_f32(const riscv_svm_polynomial_instance_f32 *S, + const float32_t * in, + int32_t * pResult); + + +/** + * @brief SVM radial basis function instance init function + * @param[in] S points to an instance of the polynomial SVM structure. + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @param[in] gamma gamma (scikit-learn terminology) + * @return none. + * + */ + +void riscv_svm_rbf_init_f32(riscv_svm_rbf_instance_f32 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float32_t intercept, + const float32_t *dualCoefficients, + const float32_t *supportVectors, + const int32_t *classes, + float32_t gamma + ); + +/** + * @brief SVM rbf prediction + * @param[in] S Pointer to an instance of the rbf SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult decision value + * @return none. + * + */ +void riscv_svm_rbf_predict_f32(const riscv_svm_rbf_instance_f32 *S, + const float32_t * in, + int32_t * pResult); + +/** + * @brief SVM sigmoid instance init function + * @param[in] S points to an instance of the rbf SVM structure. + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @param[in] coef0 coeff0 (scikit-learn terminology) + * @param[in] gamma gamma (scikit-learn terminology) + * @return none. + * + */ + +void riscv_svm_sigmoid_init_f32(riscv_svm_sigmoid_instance_f32 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float32_t intercept, + const float32_t *dualCoefficients, + const float32_t *supportVectors, + const int32_t *classes, + float32_t coef0, + float32_t gamma + ); + +/** + * @brief SVM sigmoid prediction + * @param[in] S Pointer to an instance of the rbf SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult Decision value + * @return none. + * + */ +void riscv_svm_sigmoid_predict_f32(const riscv_svm_sigmoid_instance_f32 *S, + const float32_t * in, + int32_t * pResult); + + + + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _SVM_FUNCTIONS_H_ */ diff --git a/components/nmsis/dsp/inc/dsp/svm_functions_f16.h b/components/nmsis/dsp/inc/dsp/svm_functions_f16.h new file mode 100644 index 00000000..1c273f94 --- /dev/null +++ b/components/nmsis/dsp/inc/dsp/svm_functions_f16.h @@ -0,0 +1,299 @@ +/****************************************************************************** + * @file svm_functions_f16.h + * @brief Public header file for NMSIS DSP Library + * @version V1.9.0 + * @date 23 April 2021 + * Target Processor: RISC-V Cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _SVM_FUNCTIONS_F16_H_ +#define _SVM_FUNCTIONS_F16_H_ + +#include "riscv_math_types_f16.h" +#include "riscv_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" +#include "dsp/svm_defines.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if defined(RISCV_FLOAT16_SUPPORTED) + +#define STEP(x) (x) <= 0 ? 0 : 1 + +/** + * @defgroup groupSVM SVM Functions + * This set of functions is implementing SVM classification on 2 classes. + * The training must be done from scikit-learn. The parameters can be easily + * generated from the scikit-learn object. Some examples are given in + * DSP/Testing/PatternGeneration/SVM.py + * + * If more than 2 classes are needed, the functions in this folder + * will have to be used, as building blocks, to do multi-class classification. + * + * No multi-class classification is provided in this SVM folder. + * + */ + +/** + * @brief Integer exponentiation + * @param[in] x value + * @param[in] nb integer exponent >= 1 + * @return x^nb + * + */ +__STATIC_INLINE float16_t riscv_exponent_f16(float16_t x, int32_t nb) +{ + float16_t r = x; + nb --; + while(nb > 0) + { + r = r * x; + nb--; + } + return(r); +} + + +/** + * @brief Instance structure for linear SVM prediction function. + */ +typedef struct +{ + uint32_t nbOfSupportVectors; /**< Number of support vectors */ + uint32_t vectorDimension; /**< Dimension of vector space */ + float16_t intercept; /**< Intercept */ + const float16_t *dualCoefficients; /**< Dual coefficients */ + const float16_t *supportVectors; /**< Support vectors */ + const int32_t *classes; /**< The two SVM classes */ +} riscv_svm_linear_instance_f16; + + +/** + * @brief Instance structure for polynomial SVM prediction function. + */ +typedef struct +{ + uint32_t nbOfSupportVectors; /**< Number of support vectors */ + uint32_t vectorDimension; /**< Dimension of vector space */ + float16_t intercept; /**< Intercept */ + const float16_t *dualCoefficients; /**< Dual coefficients */ + const float16_t *supportVectors; /**< Support vectors */ + const int32_t *classes; /**< The two SVM classes */ + int32_t degree; /**< Polynomial degree */ + float16_t coef0; /**< Polynomial constant */ + float16_t gamma; /**< Gamma factor */ +} riscv_svm_polynomial_instance_f16; + +/** + * @brief Instance structure for rbf SVM prediction function. + */ +typedef struct +{ + uint32_t nbOfSupportVectors; /**< Number of support vectors */ + uint32_t vectorDimension; /**< Dimension of vector space */ + float16_t intercept; /**< Intercept */ + const float16_t *dualCoefficients; /**< Dual coefficients */ + const float16_t *supportVectors; /**< Support vectors */ + const int32_t *classes; /**< The two SVM classes */ + float16_t gamma; /**< Gamma factor */ +} riscv_svm_rbf_instance_f16; + +/** + * @brief Instance structure for sigmoid SVM prediction function. + */ +typedef struct +{ + uint32_t nbOfSupportVectors; /**< Number of support vectors */ + uint32_t vectorDimension; /**< Dimension of vector space */ + float16_t intercept; /**< Intercept */ + const float16_t *dualCoefficients; /**< Dual coefficients */ + const float16_t *supportVectors; /**< Support vectors */ + const int32_t *classes; /**< The two SVM classes */ + float16_t coef0; /**< Independent constant */ + float16_t gamma; /**< Gamma factor */ +} riscv_svm_sigmoid_instance_f16; + +/** + * @brief SVM linear instance init function + * @param[in] S Parameters for SVM functions + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @return none. + * + */ + + +void riscv_svm_linear_init_f16(riscv_svm_linear_instance_f16 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float16_t intercept, + const float16_t *dualCoefficients, + const float16_t *supportVectors, + const int32_t *classes); + +/** + * @brief SVM linear prediction + * @param[in] S Pointer to an instance of the linear SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult Decision value + * @return none. + * + */ + +void riscv_svm_linear_predict_f16(const riscv_svm_linear_instance_f16 *S, + const float16_t * in, + int32_t * pResult); + + +/** + * @brief SVM polynomial instance init function + * @param[in] S points to an instance of the polynomial SVM structure. + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @param[in] degree Polynomial degree + * @param[in] coef0 coeff0 (scikit-learn terminology) + * @param[in] gamma gamma (scikit-learn terminology) + * @return none. + * + */ + + +void riscv_svm_polynomial_init_f16(riscv_svm_polynomial_instance_f16 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float16_t intercept, + const float16_t *dualCoefficients, + const float16_t *supportVectors, + const int32_t *classes, + int32_t degree, + float16_t coef0, + float16_t gamma + ); + +/** + * @brief SVM polynomial prediction + * @param[in] S Pointer to an instance of the polynomial SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult Decision value + * @return none. + * + */ +void riscv_svm_polynomial_predict_f16(const riscv_svm_polynomial_instance_f16 *S, + const float16_t * in, + int32_t * pResult); + + +/** + * @brief SVM radial basis function instance init function + * @param[in] S points to an instance of the polynomial SVM structure. + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @param[in] gamma gamma (scikit-learn terminology) + * @return none. + * + */ + +void riscv_svm_rbf_init_f16(riscv_svm_rbf_instance_f16 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float16_t intercept, + const float16_t *dualCoefficients, + const float16_t *supportVectors, + const int32_t *classes, + float16_t gamma + ); + +/** + * @brief SVM rbf prediction + * @param[in] S Pointer to an instance of the rbf SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult decision value + * @return none. + * + */ +void riscv_svm_rbf_predict_f16(const riscv_svm_rbf_instance_f16 *S, + const float16_t * in, + int32_t * pResult); + +/** + * @brief SVM sigmoid instance init function + * @param[in] S points to an instance of the rbf SVM structure. + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @param[in] coef0 coeff0 (scikit-learn terminology) + * @param[in] gamma gamma (scikit-learn terminology) + * @return none. + * + */ + +void riscv_svm_sigmoid_init_f16(riscv_svm_sigmoid_instance_f16 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float16_t intercept, + const float16_t *dualCoefficients, + const float16_t *supportVectors, + const int32_t *classes, + float16_t coef0, + float16_t gamma + ); + +/** + * @brief SVM sigmoid prediction + * @param[in] S Pointer to an instance of the rbf SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult Decision value + * @return none. + * + */ +void riscv_svm_sigmoid_predict_f16(const riscv_svm_sigmoid_instance_f16 *S, + const float16_t * in, + int32_t * pResult); + + + +#endif /*defined(RISCV_FLOAT16_SUPPORTED)*/ +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _SVM_FUNCTIONS_F16_H_ */ diff --git a/components/nmsis/dsp/inc/dsp/transform_functions.h b/components/nmsis/dsp/inc/dsp/transform_functions.h new file mode 100644 index 00000000..6d89ed33 --- /dev/null +++ b/components/nmsis/dsp/inc/dsp/transform_functions.h @@ -0,0 +1,561 @@ +/****************************************************************************** + * @file transform_functions.h + * @brief Public header file for NMSIS DSP Library + * @version V1.9.0 + * @date 23 April 2021 + * Target Processor: RISC-V Cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _TRANSFORM_FUNCTIONS_H_ +#define _TRANSFORM_FUNCTIONS_H_ + +#include "riscv_math_types.h" +#include "riscv_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" + +#include "dsp/basic_math_functions.h" +#include "dsp/complex_math_functions.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** + * @defgroup groupTransforms Transform Functions + */ + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } riscv_cfft_radix2_instance_q15; + +/* Deprecated */ + riscv_status riscv_cfft_radix2_init_q15( + riscv_cfft_radix2_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void riscv_cfft_radix2_q15( + const riscv_cfft_radix2_instance_q15 * S, + q15_t * pSrc); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const q15_t *pTwiddle; /**< points to the twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } riscv_cfft_radix4_instance_q15; + +/* Deprecated */ + riscv_status riscv_cfft_radix4_init_q15( + riscv_cfft_radix4_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void riscv_cfft_radix4_q15( + const riscv_cfft_radix4_instance_q15 * S, + q15_t * pSrc); + + /** + * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } riscv_cfft_radix2_instance_q31; + +/* Deprecated */ + riscv_status riscv_cfft_radix2_init_q31( + riscv_cfft_radix2_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void riscv_cfft_radix2_q31( + const riscv_cfft_radix2_instance_q31 * S, + q31_t * pSrc); + + /** + * @brief Instance structure for the Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const q31_t *pTwiddle; /**< points to the twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } riscv_cfft_radix4_instance_q31; + +/* Deprecated */ + void riscv_cfft_radix4_q31( + const riscv_cfft_radix4_instance_q31 * S, + q31_t * pSrc); + +/* Deprecated */ + riscv_status riscv_cfft_radix4_init_q31( + riscv_cfft_radix4_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } riscv_cfft_radix2_instance_f32; + + +/* Deprecated */ + riscv_status riscv_cfft_radix2_init_f32( + riscv_cfft_radix2_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void riscv_cfft_radix2_f32( + const riscv_cfft_radix2_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } riscv_cfft_radix4_instance_f32; + + + +/* Deprecated */ + riscv_status riscv_cfft_radix4_init_f32( + riscv_cfft_radix4_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void riscv_cfft_radix4_f32( + const riscv_cfft_radix4_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } riscv_cfft_instance_q15; + +riscv_status riscv_cfft_init_q15( + riscv_cfft_instance_q15 * S, + uint16_t fftLen); + +void riscv_cfft_q15( + const riscv_cfft_instance_q15 * S, + q15_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } riscv_cfft_instance_q31; + +riscv_status riscv_cfft_init_q31( + riscv_cfft_instance_q31 * S, + uint16_t fftLen); + +void riscv_cfft_q31( + const riscv_cfft_instance_q31 * S, + q31_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } riscv_cfft_instance_f32; + + + + riscv_status riscv_cfft_init_f32( + riscv_cfft_instance_f32 * S, + uint16_t fftLen); + + void riscv_cfft_f32( + const riscv_cfft_instance_f32 * S, + float32_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + + /** + * @brief Instance structure for the Double Precision Floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const float64_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } riscv_cfft_instance_f64; + + riscv_status riscv_cfft_init_f64( + riscv_cfft_instance_f64 * S, + uint16_t fftLen); + + void riscv_cfft_f64( + const riscv_cfft_instance_f64 * S, + float64_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the Q15 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + const q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + const q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const riscv_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } riscv_rfft_instance_q15; + + riscv_status riscv_rfft_init_q15( + riscv_rfft_instance_q15 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void riscv_rfft_q15( + const riscv_rfft_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst); + + /** + * @brief Instance structure for the Q31 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + const q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + const q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const riscv_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } riscv_rfft_instance_q31; + + riscv_status riscv_rfft_init_q31( + riscv_rfft_instance_q31 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void riscv_rfft_q31( + const riscv_rfft_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint16_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + const float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + const float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + riscv_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } riscv_rfft_instance_f32; + + riscv_status riscv_rfft_init_f32( + riscv_rfft_instance_f32 * S, + riscv_cfft_radix4_instance_f32 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void riscv_rfft_f32( + const riscv_rfft_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst); + + /** + * @brief Instance structure for the Double Precision Floating-point RFFT/RIFFT function. + */ +typedef struct + { + riscv_cfft_instance_f64 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + const float64_t * pTwiddleRFFT; /**< Twiddle factors real stage */ + } riscv_rfft_fast_instance_f64 ; + +riscv_status riscv_rfft_fast_init_f64 ( + riscv_rfft_fast_instance_f64 * S, + uint16_t fftLen); + + +void riscv_rfft_fast_f64( + riscv_rfft_fast_instance_f64 * S, + float64_t * p, float64_t * pOut, + uint8_t ifftFlag); + + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ +typedef struct + { + riscv_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + const float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ + } riscv_rfft_fast_instance_f32 ; + +riscv_status riscv_rfft_fast_init_f32 ( + riscv_rfft_fast_instance_f32 * S, + uint16_t fftLen); + + + void riscv_rfft_fast_f32( + const riscv_rfft_fast_instance_f32 * S, + float32_t * p, float32_t * pOut, + uint8_t ifftFlag); + + /** + * @brief Instance structure for the floating-point DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + float32_t normalize; /**< normalizing factor. */ + const float32_t *pTwiddle; /**< points to the twiddle factor table. */ + const float32_t *pCosFactor; /**< points to the cosFactor table. */ + riscv_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ + riscv_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } riscv_dct4_instance_f32; + + + /** + * @brief Initialization function for the floating-point DCT4/IDCT4. + * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return riscv_status function returns RISCV_MATH_SUCCESS if initialization is successful or RISCV_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. + */ + riscv_status riscv_dct4_init_f32( + riscv_dct4_instance_f32 * S, + riscv_rfft_instance_f32 * S_RFFT, + riscv_cfft_radix4_instance_f32 * S_CFFT, + uint16_t N, + uint16_t Nby2, + float32_t normalize); + + + /** + * @brief Processing function for the floating-point DCT4/IDCT4. + * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void riscv_dct4_f32( + const riscv_dct4_instance_f32 * S, + float32_t * pState, + float32_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q31 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q31_t normalize; /**< normalizing factor. */ + const q31_t *pTwiddle; /**< points to the twiddle factor table. */ + const q31_t *pCosFactor; /**< points to the cosFactor table. */ + riscv_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ + riscv_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } riscv_dct4_instance_q31; + + + /** + * @brief Initialization function for the Q31 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure + * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return riscv_status function returns RISCV_MATH_SUCCESS if initialization is successful or RISCV_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + riscv_status riscv_dct4_init_q31( + riscv_dct4_instance_q31 * S, + riscv_rfft_instance_q31 * S_RFFT, + riscv_cfft_radix4_instance_q31 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize); + + + /** + * @brief Processing function for the Q31 DCT4/IDCT4. + * @param[in] S points to an instance of the Q31 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void riscv_dct4_q31( + const riscv_dct4_instance_q31 * S, + q31_t * pState, + q31_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q15 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q15_t normalize; /**< normalizing factor. */ + const q15_t *pTwiddle; /**< points to the twiddle factor table. */ + const q15_t *pCosFactor; /**< points to the cosFactor table. */ + riscv_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ + riscv_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } riscv_dct4_instance_q15; + + + /** + * @brief Initialization function for the Q15 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return riscv_status function returns RISCV_MATH_SUCCESS if initialization is successful or RISCV_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + riscv_status riscv_dct4_init_q15( + riscv_dct4_instance_q15 * S, + riscv_rfft_instance_q15 * S_RFFT, + riscv_cfft_radix4_instance_q15 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize); + + + /** + * @brief Processing function for the Q15 DCT4/IDCT4. + * @param[in] S points to an instance of the Q15 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void riscv_dct4_q15( + const riscv_dct4_instance_q15 * S, + q15_t * pState, + q15_t * pInlineBuffer); + + + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _TRANSFORM_FUNCTIONS_H_ */ diff --git a/components/nmsis/dsp/inc/dsp/transform_functions_f16.h b/components/nmsis/dsp/inc/dsp/transform_functions_f16.h new file mode 100644 index 00000000..de6a00c0 --- /dev/null +++ b/components/nmsis/dsp/inc/dsp/transform_functions_f16.h @@ -0,0 +1,150 @@ +/****************************************************************************** + * @file transform_functions_f16.h + * @brief Public header file for NMSIS DSP Library + * @version V1.9.0 + * @date 23 April 2021 + * Target Processor: RISC-V Cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _TRANSFORM_FUNCTIONS_F16_H_ +#define _TRANSFORM_FUNCTIONS_F16_H_ + +#include "riscv_math_types_f16.h" +#include "riscv_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + + + +#if defined(RISCV_FLOAT16_SUPPORTED) + + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const float16_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float16_t onebyfftLen; /**< value of 1/fftLen. */ + } riscv_cfft_radix2_instance_f16; + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const float16_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float16_t onebyfftLen; /**< value of 1/fftLen. */ + } riscv_cfft_radix4_instance_f16; + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const float16_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } riscv_cfft_instance_f16; + + + riscv_status riscv_cfft_init_f16( + riscv_cfft_instance_f16 * S, + uint16_t fftLen); + + void riscv_cfft_f16( + const riscv_cfft_instance_f16 * S, + float16_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ +typedef struct + { + riscv_cfft_instance_f16 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + const float16_t * pTwiddleRFFT; /**< Twiddle factors real stage */ + } riscv_rfft_fast_instance_f16 ; + +riscv_status riscv_rfft_fast_init_f16 ( + riscv_rfft_fast_instance_f16 * S, + uint16_t fftLen); + + + void riscv_rfft_fast_f16( + const riscv_rfft_fast_instance_f16 * S, + float16_t * p, float16_t * pOut, + uint8_t ifftFlag); + +/* Deprecated */ + riscv_status riscv_cfft_radix4_init_f16( + riscv_cfft_radix4_instance_f16 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void riscv_cfft_radix4_f16( + const riscv_cfft_radix4_instance_f16 * S, + float16_t * pSrc); + + +/* Deprecated */ + riscv_status riscv_cfft_radix2_init_f16( + riscv_cfft_radix2_instance_f16 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void riscv_cfft_radix2_f16( + const riscv_cfft_radix2_instance_f16 * S, + float16_t * pSrc); + +#endif /* defined(RISCV_FLOAT16_SUPPORTED)*/ + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _TRANSFORM_FUNCTIONS_F16_H_ */ diff --git a/components/nmsis/dsp/inc/dsp/utils.h b/components/nmsis/dsp/inc/dsp/utils.h new file mode 100644 index 00000000..93283615 --- /dev/null +++ b/components/nmsis/dsp/inc/dsp/utils.h @@ -0,0 +1,241 @@ +/****************************************************************************** + * @file riscv_math_utils.h + * @brief Public header file for NMSIS DSP Library + * @version V1.9.0 + * @date 20. July 2020 + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _RISCV_MATH_UTILS_H_ + +#define _RISCV_MATH_UTILS_H_ + +#include "riscv_math_types.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + + /** + * @brief Macros required for reciprocal calculation in Normalized LMS + */ + +#define INDEX_MASK 0x0000003F + + +#define SQ(x) ((x) * (x)) + +#define ROUND_UP(N, S) ((((N) + (S) - 1) / (S)) * (S)) + + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. + */ + __STATIC_FORCEINLINE uint32_t riscv_recip_q31( + q31_t in, + q31_t * dst, + const q31_t * pRecipTable) + { + q31_t out; + uint32_t tempVal; + uint32_t index, i; + uint32_t signBits; + + if (in > 0) + { + signBits = ((uint32_t) (__CLZ( in) - 1)); + } + else + { + signBits = ((uint32_t) (__CLZ(-in) - 1)); + } + + /* Convert input sample to 1.31 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 24); + index = (index & INDEX_MASK); + + /* 1.31 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0U; i < 2U; i++) + { + tempVal = (uint32_t) (((q63_t) in * out) >> 31); + tempVal = 0x7FFFFFFFu - tempVal; + /* 1.31 with exp 1 */ + /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */ + out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1U); + } + + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. + */ + __STATIC_FORCEINLINE uint32_t riscv_recip_q15( + q15_t in, + q15_t * dst, + const q15_t * pRecipTable) + { + q15_t out = 0; + uint32_t tempVal = 0; + uint32_t index = 0, i = 0; + uint32_t signBits = 0; + + if (in > 0) + { + signBits = ((uint32_t)(__CLZ( in) - 17)); + } + else + { + signBits = ((uint32_t)(__CLZ(-in) - 17)); + } + + /* Convert input sample to 1.15 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 8); + index = (index & INDEX_MASK); + + /* 1.15 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0U; i < 2U; i++) + { + tempVal = (uint32_t) (((q31_t) in * out) >> 15); + tempVal = 0x7FFFu - tempVal; + /* 1.15 with exp 1 */ + out = (q15_t) (((q31_t) out * tempVal) >> 14); + /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */ + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1); + } + + +/** + * @brief 64-bit to 32-bit unsigned normalization + * @param[in] in is input unsigned long long value + * @param[out] normalized is the 32-bit normalized value + * @param[out] norm is norm scale + */ +__STATIC_INLINE void riscv_norm_64_to_32u(uint64_t in, int32_t * normalized, int32_t *norm) +{ + int32_t n1; + int32_t hi = (int32_t) (in >> 32); + int32_t lo = (int32_t) ((in << 32) >> 32); + + n1 = __CLZ(hi) - 32; + if (!n1) + { + /* + * input fits in 32-bit + */ + n1 = __CLZ(lo); + if (!n1) + { + /* + * MSB set, need to scale down by 1 + */ + *norm = -1; + *normalized = (((uint32_t) lo) >> 1); + } else + { + if (n1 == 32) + { + /* + * input is zero + */ + *norm = 0; + *normalized = 0; + } else + { + /* + * 32-bit normalization + */ + *norm = n1 - 1; + *normalized = lo << *norm; + } + } + } else + { + /* + * input fits in 64-bit + */ + n1 = 1 - n1; + *norm = -n1; + /* + * 64 bit normalization + */ + *normalized = (((uint32_t) lo) >> n1) | (hi << (32 - n1)); + } +} + +__STATIC_INLINE q31_t riscv_div_q63_to_q31(q63_t num, q31_t den) +{ + q31_t result; + uint64_t absNum; + int32_t normalized; + int32_t norm; + + /* + * if sum fits in 32bits + * avoid costly 64-bit division + */ + absNum = num > 0 ? num : -num; + riscv_norm_64_to_32u(absNum, &normalized, &norm); + if (norm > 0) + /* + * 32-bit division + */ + result = (q31_t) num / den; + else + /* + * 64-bit division + */ + result = (q31_t) (num / den); + + return result; +} + + +#ifdef __cplusplus +} +#endif + +#endif /*ifndef _RISCV_MATH_UTILS_H_ */ diff --git a/components/nmsis/dsp/inc/riscv_common_tables.h b/components/nmsis/dsp/inc/riscv_common_tables.h new file mode 100644 index 00000000..40461d08 --- /dev/null +++ b/components/nmsis/dsp/inc/riscv_common_tables.h @@ -0,0 +1,513 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_common_tables.h + * Description: Extern declaration for common tables + * + * @version V1.9.0 + * @date 23 April 2021 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _RISCV_COMMON_TABLES_H +#define _RISCV_COMMON_TABLES_H + +#include "riscv_math_types.h" +#include "dsp/fast_math_functions.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_FFT_ALLOW_TABLES) + /* Double Precision Float CFFT twiddles */ + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREV_1024) + extern const uint16_t riscvBitRevTable[1024]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_F64_16) + extern const uint64_t twiddleCoefF64_16[32]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_F64_32) + extern const uint64_t twiddleCoefF64_32[64]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_F64_64) + extern const uint64_t twiddleCoefF64_64[128]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_F64_128) + extern const uint64_t twiddleCoefF64_128[256]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_F64_256) + extern const uint64_t twiddleCoefF64_256[512]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_F64_512) + extern const uint64_t twiddleCoefF64_512[1024]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_F64_1024) + extern const uint64_t twiddleCoefF64_1024[2048]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_F64_2048) + extern const uint64_t twiddleCoefF64_2048[4096]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_F64_4096) + extern const uint64_t twiddleCoefF64_4096[8192]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_F32_16) + extern const float32_t twiddleCoef_16[32]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_F32_32) + extern const float32_t twiddleCoef_32[64]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_F32_64) + extern const float32_t twiddleCoef_64[128]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_F32_128) + extern const float32_t twiddleCoef_128[256]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_F32_256) + extern const float32_t twiddleCoef_256[512]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_F32_512) + extern const float32_t twiddleCoef_512[1024]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_F32_1024) + extern const float32_t twiddleCoef_1024[2048]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_F32_2048) + extern const float32_t twiddleCoef_2048[4096]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_F32_4096) + extern const float32_t twiddleCoef_4096[8192]; + #define twiddleCoef twiddleCoef_4096 + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + /* Q31 */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_Q31_16) + extern const q31_t twiddleCoef_16_q31[24]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_Q31_32) + extern const q31_t twiddleCoef_32_q31[48]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_Q31_64) + extern const q31_t twiddleCoef_64_q31[96]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_Q31_128) + extern const q31_t twiddleCoef_128_q31[192]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_Q31_256) + extern const q31_t twiddleCoef_256_q31[384]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_Q31_512) + extern const q31_t twiddleCoef_512_q31[768]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_Q31_1024) + extern const q31_t twiddleCoef_1024_q31[1536]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_Q31_2048) + extern const q31_t twiddleCoef_2048_q31[3072]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_Q31_4096) + extern const q31_t twiddleCoef_4096_q31[6144]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_Q15_16) + extern const q15_t twiddleCoef_16_q15[24]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_Q15_32) + extern const q15_t twiddleCoef_32_q15[48]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_Q15_64) + extern const q15_t twiddleCoef_64_q15[96]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_Q15_128) + extern const q15_t twiddleCoef_128_q15[192]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_Q15_256) + extern const q15_t twiddleCoef_256_q15[384]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_Q15_512) + extern const q15_t twiddleCoef_512_q15[768]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_Q15_1024) + extern const q15_t twiddleCoef_1024_q15[1536]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_Q15_2048) + extern const q15_t twiddleCoef_2048_q15[3072]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_Q15_4096) + extern const q15_t twiddleCoef_4096_q15[6144]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + /* Double Precision Float RFFT twiddles */ + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F64_32) + extern const uint64_t twiddleCoefF64_rfft_32[32]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F64_64) + extern const uint64_t twiddleCoefF64_rfft_64[64]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F64_128) + extern const uint64_t twiddleCoefF64_rfft_128[128]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F64_256) + extern const uint64_t twiddleCoefF64_rfft_256[256]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F64_512) + extern const uint64_t twiddleCoefF64_rfft_512[512]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F64_1024) + extern const uint64_t twiddleCoefF64_rfft_1024[1024]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F64_2048) + extern const uint64_t twiddleCoefF64_rfft_2048[2048]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F64_4096) + extern const uint64_t twiddleCoefF64_rfft_4096[4096]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F32_32) + extern const float32_t twiddleCoef_rfft_32[32]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F32_64) + extern const float32_t twiddleCoef_rfft_64[64]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F32_128) + extern const float32_t twiddleCoef_rfft_128[128]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F32_256) + extern const float32_t twiddleCoef_rfft_256[256]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F32_512) + extern const float32_t twiddleCoef_rfft_512[512]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F32_1024) + extern const float32_t twiddleCoef_rfft_1024[1024]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F32_2048) + extern const float32_t twiddleCoef_rfft_2048[2048]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F32_4096) + extern const float32_t twiddleCoef_rfft_4096[4096]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + + /* Double precision floating-point bit reversal tables */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREVIDX_FLT64_16) + #define RISCVBITREVINDEXTABLEF64_16_TABLE_LENGTH ((uint16_t)12) + extern const uint16_t riscvBitRevIndexTableF64_16[RISCVBITREVINDEXTABLEF64_16_TABLE_LENGTH]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREVIDX_FLT64_32) + #define RISCVBITREVINDEXTABLEF64_32_TABLE_LENGTH ((uint16_t)24) + extern const uint16_t riscvBitRevIndexTableF64_32[RISCVBITREVINDEXTABLEF64_32_TABLE_LENGTH]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREVIDX_FLT64_64) + #define RISCVBITREVINDEXTABLEF64_64_TABLE_LENGTH ((uint16_t)56) + extern const uint16_t riscvBitRevIndexTableF64_64[RISCVBITREVINDEXTABLEF64_64_TABLE_LENGTH]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREVIDX_FLT64_128) + #define RISCVBITREVINDEXTABLEF64_128_TABLE_LENGTH ((uint16_t)112) + extern const uint16_t riscvBitRevIndexTableF64_128[RISCVBITREVINDEXTABLEF64_128_TABLE_LENGTH]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREVIDX_FLT64_256) + #define RISCVBITREVINDEXTABLEF64_256_TABLE_LENGTH ((uint16_t)240) + extern const uint16_t riscvBitRevIndexTableF64_256[RISCVBITREVINDEXTABLEF64_256_TABLE_LENGTH]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREVIDX_FLT64_512) + #define RISCVBITREVINDEXTABLEF64_512_TABLE_LENGTH ((uint16_t)480) + extern const uint16_t riscvBitRevIndexTableF64_512[RISCVBITREVINDEXTABLEF64_512_TABLE_LENGTH]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREVIDX_FLT64_1024) + #define RISCVBITREVINDEXTABLEF64_1024_TABLE_LENGTH ((uint16_t)992) + extern const uint16_t riscvBitRevIndexTableF64_1024[RISCVBITREVINDEXTABLEF64_1024_TABLE_LENGTH]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREVIDX_FLT64_2048) + #define RISCVBITREVINDEXTABLEF64_2048_TABLE_LENGTH ((uint16_t)1984) + extern const uint16_t riscvBitRevIndexTableF64_2048[RISCVBITREVINDEXTABLEF64_2048_TABLE_LENGTH]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREVIDX_FLT64_4096) + #define RISCVBITREVINDEXTABLEF64_4096_TABLE_LENGTH ((uint16_t)4032) + extern const uint16_t riscvBitRevIndexTableF64_4096[RISCVBITREVINDEXTABLEF64_4096_TABLE_LENGTH]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + /* floating-point bit reversal tables */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREVIDX_FLT_16) + #define RISCVBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20) + extern const uint16_t riscvBitRevIndexTable16[RISCVBITREVINDEXTABLE_16_TABLE_LENGTH]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREVIDX_FLT_32) + #define RISCVBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48) + extern const uint16_t riscvBitRevIndexTable32[RISCVBITREVINDEXTABLE_32_TABLE_LENGTH]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREVIDX_FLT_64) + #define RISCVBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56) + extern const uint16_t riscvBitRevIndexTable64[RISCVBITREVINDEXTABLE_64_TABLE_LENGTH]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREVIDX_FLT_128) + #define RISCVBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208) + extern const uint16_t riscvBitRevIndexTable128[RISCVBITREVINDEXTABLE_128_TABLE_LENGTH]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREVIDX_FLT_256) + #define RISCVBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440) + extern const uint16_t riscvBitRevIndexTable256[RISCVBITREVINDEXTABLE_256_TABLE_LENGTH]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREVIDX_FLT_512) + #define RISCVBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448) + extern const uint16_t riscvBitRevIndexTable512[RISCVBITREVINDEXTABLE_512_TABLE_LENGTH]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREVIDX_FLT_1024) + #define RISCVBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800) + extern const uint16_t riscvBitRevIndexTable1024[RISCVBITREVINDEXTABLE_1024_TABLE_LENGTH]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREVIDX_FLT_2048) + #define RISCVBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808) + extern const uint16_t riscvBitRevIndexTable2048[RISCVBITREVINDEXTABLE_2048_TABLE_LENGTH]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREVIDX_FLT_4096) + #define RISCVBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032) + extern const uint16_t riscvBitRevIndexTable4096[RISCVBITREVINDEXTABLE_4096_TABLE_LENGTH]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + + /* fixed-point bit reversal tables */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREVIDX_FXT_16) + #define RISCVBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12) + extern const uint16_t riscvBitRevIndexTable_fixed_16[RISCVBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREVIDX_FXT_32) + #define RISCVBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24) + extern const uint16_t riscvBitRevIndexTable_fixed_32[RISCVBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREVIDX_FXT_64) + #define RISCVBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56) + extern const uint16_t riscvBitRevIndexTable_fixed_64[RISCVBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREVIDX_FXT_128) + #define RISCVBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112) + extern const uint16_t riscvBitRevIndexTable_fixed_128[RISCVBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREVIDX_FXT_256) + #define RISCVBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240) + extern const uint16_t riscvBitRevIndexTable_fixed_256[RISCVBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREVIDX_FXT_512) + #define RISCVBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480) + extern const uint16_t riscvBitRevIndexTable_fixed_512[RISCVBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREVIDX_FXT_1024) + #define RISCVBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992) + extern const uint16_t riscvBitRevIndexTable_fixed_1024[RISCVBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREVIDX_FXT_2048) + #define RISCVBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) + extern const uint16_t riscvBitRevIndexTable_fixed_2048[RISCVBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREVIDX_FXT_4096) + #define RISCVBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) + extern const uint16_t riscvBitRevIndexTable_fixed_4096[RISCVBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_REALCOEF_F32) + extern const float32_t realCoefA[8192]; + extern const float32_t realCoefB[8192]; + #endif + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_REALCOEF_Q31) + extern const q31_t realCoefAQ31[8192]; + extern const q31_t realCoefBQ31[8192]; + #endif + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_REALCOEF_Q15) + extern const q15_t realCoefAQ15[8192]; + extern const q15_t realCoefBQ15[8192]; + #endif + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_DCT4_F32_128) + extern const float32_t Weights_128[256]; + extern const float32_t cos_factors_128[128]; + #endif + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_DCT4_F32_512) + extern const float32_t Weights_512[1024]; + extern const float32_t cos_factors_512[512]; + #endif + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_DCT4_F32_2048) + extern const float32_t Weights_2048[4096]; + extern const float32_t cos_factors_2048[2048]; + #endif + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_DCT4_F32_8192) + extern const float32_t Weights_8192[16384]; + extern const float32_t cos_factors_8192[8192]; + #endif + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_DCT4_Q15_128) + extern const q15_t WeightsQ15_128[256]; + extern const q15_t cos_factorsQ15_128[128]; + #endif + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_DCT4_Q15_512) + extern const q15_t WeightsQ15_512[1024]; + extern const q15_t cos_factorsQ15_512[512]; + #endif + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_DCT4_Q15_2048) + extern const q15_t WeightsQ15_2048[4096]; + extern const q15_t cos_factorsQ15_2048[2048]; + #endif + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_DCT4_Q15_8192) + extern const q15_t WeightsQ15_8192[16384]; + extern const q15_t cos_factorsQ15_8192[8192]; + #endif + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_DCT4_Q31_128) + extern const q31_t WeightsQ31_128[256]; + extern const q31_t cos_factorsQ31_128[128]; + #endif + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_DCT4_Q31_512) + extern const q31_t WeightsQ31_512[1024]; + extern const q31_t cos_factorsQ31_512[512]; + #endif + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_DCT4_Q31_2048) + extern const q31_t WeightsQ31_2048[4096]; + extern const q31_t cos_factorsQ31_2048[2048]; + #endif + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_DCT4_Q31_8192) + extern const q31_t WeightsQ31_8192[16384]; + extern const q31_t cos_factorsQ31_8192[8192]; + #endif + +#endif /* if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_FFT_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_FAST_ALLOW_TABLES) + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FAST_TABLES) || defined(RISCV_TABLE_RECIP_Q15) + extern const q15_t riscvRecipTableQ15[64]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) defined(RISCV_ALL_FAST_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FAST_TABLES) || defined(RISCV_TABLE_RECIP_Q31) + extern const q31_t riscvRecipTableQ31[64]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) defined(RISCV_ALL_FAST_TABLES) */ + + /* Tables for Fast Math Sine and Cosine */ + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FAST_TABLES) || defined(RISCV_TABLE_SIN_F32) + extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) defined(RISCV_ALL_FAST_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FAST_TABLES) || defined(RISCV_TABLE_SIN_Q31) + extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) defined(RISCV_ALL_FAST_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FAST_TABLES) || defined(RISCV_TABLE_SIN_Q15) + extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) defined(RISCV_ALL_FAST_TABLES) */ + + + +#endif /* if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_FAST_TABLES) */ + + + +#ifdef __cplusplus +} +#endif + +#endif /* RISCV_COMMON_TABLES_H */ + diff --git a/components/nmsis/dsp/inc/riscv_common_tables_f16.h b/components/nmsis/dsp/inc/riscv_common_tables_f16.h new file mode 100644 index 00000000..888656c6 --- /dev/null +++ b/components/nmsis/dsp/inc/riscv_common_tables_f16.h @@ -0,0 +1,129 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_common_tables_f16.h + * Description: Extern declaration for common tables + * + * @version V1.9.0 + * @date 23 April 2021 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _RISCV_COMMON_TABLES_F16_H +#define _RISCV_COMMON_TABLES_F16_H + +#include "riscv_math_types_f16.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_FFT_ALLOW_TABLES) + + /* F16 */ + #if defined(RISCV_FLOAT16_SUPPORTED) + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_F16_16) + extern const float16_t twiddleCoefF16_16[32]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_F16_32) + extern const float16_t twiddleCoefF16_32[64]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_F16_64) + extern const float16_t twiddleCoefF16_64[128]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_F16_128) + extern const float16_t twiddleCoefF16_128[256]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_F16_256) + extern const float16_t twiddleCoefF16_256[512]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_F16_512) + extern const float16_t twiddleCoefF16_512[1024]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_F16_1024) + extern const float16_t twiddleCoefF16_1024[2048]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_F16_2048) + extern const float16_t twiddleCoefF16_2048[4096]; + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_F16_4096) + extern const float16_t twiddleCoefF16_4096[8192]; + #define twiddleCoefF16 twiddleCoefF16_4096 + #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F16_32) + extern const float16_t twiddleCoefF16_rfft_32[32]; + #endif + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F16_64) + extern const float16_t twiddleCoefF16_rfft_64[64]; + #endif + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F16_128) + extern const float16_t twiddleCoefF16_rfft_128[128]; + #endif + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F16_256) + extern const float16_t twiddleCoefF16_rfft_256[256]; + #endif + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F16_512) + extern const float16_t twiddleCoefF16_rfft_512[512]; + #endif + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F16_1024) + extern const float16_t twiddleCoefF16_rfft_1024[1024]; + #endif + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F16_2048) + extern const float16_t twiddleCoefF16_rfft_2048[2048]; + #endif + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F16_4096) + extern const float16_t twiddleCoefF16_rfft_4096[4096]; + #endif + + #endif /* ARMAC5 */ + +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_FFT_ALLOW_TABLES) */ + +#if defined(RISCV_FLOAT16_SUPPORTED) + +#endif + + +#ifdef __cplusplus +} +#endif + +#endif /* _RISCV_COMMON_TABLES_F16_H */ + + diff --git a/components/nmsis/dsp/inc/riscv_const_structs.h b/components/nmsis/dsp/inc/riscv_const_structs.h new file mode 100644 index 00000000..1173ce01 --- /dev/null +++ b/components/nmsis/dsp/inc/riscv_const_structs.h @@ -0,0 +1,87 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_const_structs.h + * Description: Constant structs that are initialized for user convenience. + * For example, some can be given as arguments to the riscv_cfft_f32() function. + * + * @version V1.9.0 + * @date 23 April 2021 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _RISCV_CONST_STRUCTS_H +#define _RISCV_CONST_STRUCTS_H + +#include "riscv_math_types.h" +#include "riscv_common_tables.h" +#include "dsp/transform_functions.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + extern const riscv_cfft_instance_f64 riscv_cfft_sR_f64_len16; + extern const riscv_cfft_instance_f64 riscv_cfft_sR_f64_len32; + extern const riscv_cfft_instance_f64 riscv_cfft_sR_f64_len64; + extern const riscv_cfft_instance_f64 riscv_cfft_sR_f64_len128; + extern const riscv_cfft_instance_f64 riscv_cfft_sR_f64_len256; + extern const riscv_cfft_instance_f64 riscv_cfft_sR_f64_len512; + extern const riscv_cfft_instance_f64 riscv_cfft_sR_f64_len1024; + extern const riscv_cfft_instance_f64 riscv_cfft_sR_f64_len2048; + extern const riscv_cfft_instance_f64 riscv_cfft_sR_f64_len4096; + + extern const riscv_cfft_instance_f32 riscv_cfft_sR_f32_len16; + extern const riscv_cfft_instance_f32 riscv_cfft_sR_f32_len32; + extern const riscv_cfft_instance_f32 riscv_cfft_sR_f32_len64; + extern const riscv_cfft_instance_f32 riscv_cfft_sR_f32_len128; + extern const riscv_cfft_instance_f32 riscv_cfft_sR_f32_len256; + extern const riscv_cfft_instance_f32 riscv_cfft_sR_f32_len512; + extern const riscv_cfft_instance_f32 riscv_cfft_sR_f32_len1024; + extern const riscv_cfft_instance_f32 riscv_cfft_sR_f32_len2048; + extern const riscv_cfft_instance_f32 riscv_cfft_sR_f32_len4096; + + extern const riscv_cfft_instance_q31 riscv_cfft_sR_q31_len16; + extern const riscv_cfft_instance_q31 riscv_cfft_sR_q31_len32; + extern const riscv_cfft_instance_q31 riscv_cfft_sR_q31_len64; + extern const riscv_cfft_instance_q31 riscv_cfft_sR_q31_len128; + extern const riscv_cfft_instance_q31 riscv_cfft_sR_q31_len256; + extern const riscv_cfft_instance_q31 riscv_cfft_sR_q31_len512; + extern const riscv_cfft_instance_q31 riscv_cfft_sR_q31_len1024; + extern const riscv_cfft_instance_q31 riscv_cfft_sR_q31_len2048; + extern const riscv_cfft_instance_q31 riscv_cfft_sR_q31_len4096; + + extern const riscv_cfft_instance_q15 riscv_cfft_sR_q15_len16; + extern const riscv_cfft_instance_q15 riscv_cfft_sR_q15_len32; + extern const riscv_cfft_instance_q15 riscv_cfft_sR_q15_len64; + extern const riscv_cfft_instance_q15 riscv_cfft_sR_q15_len128; + extern const riscv_cfft_instance_q15 riscv_cfft_sR_q15_len256; + extern const riscv_cfft_instance_q15 riscv_cfft_sR_q15_len512; + extern const riscv_cfft_instance_q15 riscv_cfft_sR_q15_len1024; + extern const riscv_cfft_instance_q15 riscv_cfft_sR_q15_len2048; + extern const riscv_cfft_instance_q15 riscv_cfft_sR_q15_len4096; + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/components/nmsis/dsp/inc/riscv_const_structs_f16.h b/components/nmsis/dsp/inc/riscv_const_structs_f16.h new file mode 100644 index 00000000..bb2a1a9a --- /dev/null +++ b/components/nmsis/dsp/inc/riscv_const_structs_f16.h @@ -0,0 +1,78 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_const_structs_f16.h + * Description: Constant structs that are initialized for user convenience. + * For example, some can be given as arguments to the riscv_cfft_f16() function. + * + * @version V1.9.0 + * @date 23 April 2021 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _RISCV_CONST_STRUCTS_F16_H +#define _RISCV_CONST_STRUCTS_F16_H + +#include "riscv_math_types_f16.h" +#include "riscv_common_tables.h" +#include "riscv_common_tables_f16.h" +#include "dsp/transform_functions_f16.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if defined(RISCV_FLOAT16_SUPPORTED) + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F16_16) && defined(RISCV_TABLE_BITREVIDX_FLT_16)) + extern const riscv_cfft_instance_f16 riscv_cfft_sR_f16_len16; + #endif + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F16_32) && defined(RISCV_TABLE_BITREVIDX_FLT_32)) + extern const riscv_cfft_instance_f16 riscv_cfft_sR_f16_len32; + #endif + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F16_64) && defined(RISCV_TABLE_BITREVIDX_FLT_64)) + extern const riscv_cfft_instance_f16 riscv_cfft_sR_f16_len64; + #endif + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F16_128) && defined(RISCV_TABLE_BITREVIDX_FLT_128)) + extern const riscv_cfft_instance_f16 riscv_cfft_sR_f16_len128; + #endif + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F16_256) && defined(RISCV_TABLE_BITREVIDX_FLT_256)) + extern const riscv_cfft_instance_f16 riscv_cfft_sR_f16_len256; + #endif + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F16_512) && defined(RISCV_TABLE_BITREVIDX_FLT_512)) + extern const riscv_cfft_instance_f16 riscv_cfft_sR_f16_len512; + #endif + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F16_1024) && defined(RISCV_TABLE_BITREVIDX_FLT_1024)) + extern const riscv_cfft_instance_f16 riscv_cfft_sR_f16_len1024; + #endif + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F16_2048) && defined(RISCV_TABLE_BITREVIDX_FLT_2048)) + extern const riscv_cfft_instance_f16 riscv_cfft_sR_f16_len2048; + #endif + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F16_4096) && defined(RISCV_TABLE_BITREVIDX_FLT_4096)) + extern const riscv_cfft_instance_f16 riscv_cfft_sR_f16_len4096; + #endif +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/components/nmsis/dsp/inc/riscv_helium_utils.h b/components/nmsis/dsp/inc/riscv_helium_utils.h new file mode 100644 index 00000000..090ba2ff --- /dev/null +++ b/components/nmsis/dsp/inc/riscv_helium_utils.h @@ -0,0 +1,75 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_helium_utils.h + * Description: Utility functions for Helium development + * + * @version V1.9.0 + * @date 23 April 2021 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _RISCV_UTILS_HELIUM_H_ +#define _RISCV_UTILS_HELIUM_H_ + + +#ifdef __cplusplus +extern "C" +{ +#endif +/*************************************** + +Definitions available for MVEF and MVEI + +***************************************/ + +/*************************************** + +Definitions available for MVEF only + +***************************************/ + + +/*************************************** + +Definitions available for f16 datatype with HW acceleration only + +***************************************/ +#if defined(RISCV_FLOAT16_SUPPORTED) +#endif + +/*************************************** + +Definitions available for MVEI and MVEF only + +***************************************/ + +/*************************************** + +Definitions available for MVEI only + +***************************************/ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/components/nmsis/dsp/inc/riscv_math.h b/components/nmsis/dsp/inc/riscv_math.h new file mode 100644 index 00000000..1b99d48e --- /dev/null +++ b/components/nmsis/dsp/inc/riscv_math.h @@ -0,0 +1,155 @@ +/****************************************************************************** + * @file riscv_math.h + * @brief Public header file for NMSIS DSP Library + * @version V1.9.0 + * @date 23 April 2021 + * Target Processor: RISC-V Cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + \mainpage NMSIS DSP Software Library + * + * \section intro Introduction + * + * This user manual describes the NMSIS DSP software library, + * a suite of common signal processing functions for use on Nuclei N/NX processor based devices. + * + * The library is divided into a number of functions each covering a specific category: + * - Basic math functions + * - Fast math functions + * - Complex math functions + * - Filtering functions + * - Matrix functions + * - Transform functions + * - Motor control functions + * - Statistical functions + * - Support functions + * - Interpolation functions + * - Support Vector Machine functions (SVM) + * - Bayes classifier functions + * - Distance functions + * - Quaternion functions + * + * The library has generally separate functions for operating on 8-bit integers, 16-bit integers, + * 32-bit integer and 32-bit floating-point values. + * + * The library functions are declared in the public file riscv_math.h which is placed in the Include folder. + * Simply include this file and link the appropriate library in the application and begin calling the library functions. + * The Library supports single public header file riscv_math.h for Nuclei N cores with little endian. + * Same header file will be used for floating point unit(FPU) variants. + * + * \note Please refer to [NMSIS-DSP](../../../dsp/index.html) + * + * \section example Examples + * + * The library ships with a number of examples which demonstrate how to use the library functions. + * + * Toolchain Support + * ----------------- + * + * The library has been developed and tested with nuclei riscv gcc toolchain. + * + * Building the Library + * -------------------- + * + * In NMSIS repo, it contains a Makefile to rebuild libraries on nuclei riscv gcc toolchain in the NMSIS/ folder. + * * In *NMSIS* folder, you can run `make gen_dsp_lib` to build and install DSP library into **NMSIS/Library/DSP/GCC** folder. + * + * Preprocessor Macros + * ------------------- + * + * Each library project have different preprocessor macros. + * + * - RISCV_MATH_MATRIX_CHECK: + * + * Define macro RISCV_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices + * + * - RISCV_MATH_ROUNDING: + * + * Define macro RISCV_MATH_ROUNDING for rounding on support functions + * + * - RISCV_MATH_LOOPUNROLL: + * + * Define macro RISCV_MATH_LOOPUNROLL to enable manual loop unrolling in DSP functions + * + */ + + +/** + * @defgroup groupExamples Examples + */ + + + + +#ifndef _RISCV_MATH_H +#define _RISCV_MATH_H + + +#include "riscv_math_types.h" +#include "riscv_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" + +#include "dsp/basic_math_functions.h" +#include "dsp/interpolation_functions.h" +#include "dsp/bayes_functions.h" +#include "dsp/matrix_functions.h" +#include "dsp/complex_math_functions.h" +#include "dsp/statistics_functions.h" +#include "dsp/controller_functions.h" +#include "dsp/support_functions.h" +#include "dsp/distance_functions.h" +#include "dsp/svm_functions.h" +#include "dsp/fast_math_functions.h" +#include "dsp/transform_functions.h" +#include "dsp/filtering_functions.h" +#include "dsp/quaternion_math_functions.h" + + + +#ifdef __cplusplus +extern "C" +{ +#endif + + + + +//#define TABLE_SPACING_Q31 0x400000 +//#define TABLE_SPACING_Q15 0x80 + + + + + +#ifdef __cplusplus +} +#endif + + +#endif /* _RISCV_MATH_H */ + +/** + * + * End of file. + */ diff --git a/components/nmsis/dsp/inc/riscv_math_f16.h b/components/nmsis/dsp/inc/riscv_math_f16.h new file mode 100644 index 00000000..2b31b27a --- /dev/null +++ b/components/nmsis/dsp/inc/riscv_math_f16.h @@ -0,0 +1,60 @@ +/****************************************************************************** + * @file riscv_math_f16.h + * @brief Public header file for f16 function of the NMSIS DSP Library + * @version V1.9.0 + * @date 23 April 2021 + * Target Processor: RISC-V Cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _RISCV_MATH_F16_H +#define _RISCV_MATH_F16_H + +#include "riscv_math.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "riscv_math_types_f16.h" +#include "dsp/none.h" +#include "dsp/utils.h" +#include "dsp/basic_math_functions_f16.h" +#include "dsp/interpolation_functions_f16.h" +#include "dsp/bayes_functions_f16.h" +#include "dsp/matrix_functions_f16.h" +#include "dsp/complex_math_functions_f16.h" +#include "dsp/statistics_functions_f16.h" +#include "dsp/controller_functions_f16.h" +#include "dsp/support_functions_f16.h" +#include "dsp/distance_functions_f16.h" +#include "dsp/svm_functions_f16.h" +#include "dsp/fast_math_functions_f16.h" +#include "dsp/transform_functions_f16.h" +#include "dsp/filtering_functions_f16.h" + +#ifdef __cplusplus +} +#endif + +#endif /* _RISCV_MATH_F16_H */ + + diff --git a/components/nmsis/dsp/inc/riscv_math_memory.h b/components/nmsis/dsp/inc/riscv_math_memory.h new file mode 100644 index 00000000..800e7e15 --- /dev/null +++ b/components/nmsis/dsp/inc/riscv_math_memory.h @@ -0,0 +1,550 @@ +/****************************************************************************** + * @file riscv_math_memory.h + * @brief Public header file for NMSIS DSP Library + * @version V1.9.0 + * @date 23 April 2021 + * Target Processor: RISC-V Cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _RISCV_MATH_MEMORY_H_ + +#define _RISCV_MATH_MEMORY_H_ + +#include "riscv_math_types.h" + + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + @brief definition to read/write two 16 bit values. + @deprecated + */ +#if defined ( __GNUC__ ) + #define __SIMD32_TYPE int32_t +#elif defined ( __TI_RISCV__ ) + #define __SIMD32_TYPE int32_t +#elif defined ( __CSMC__ ) + #define __SIMD32_TYPE int32_t +#elif defined ( __TASKING__ ) + #define __SIMD32_TYPE __un(aligned) int32_t +#elif defined(_MSC_VER ) + #define __SIMD32_TYPE int32_t +#else + #error Unknown compiler +#endif + +#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) +#define __SIMD32_CONST(addr) ( (__SIMD32_TYPE * ) (addr)) +#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE * ) (addr)) +#define __SIMD64(addr) (*( int64_t **) & (addr)) + + +/* SIMD replacement */ + +/** + @brief Read 2 Q31 from Q31 pointer and increment pointer afterwards. + @param[in] pQ31 points to input value + @return Q63 value + */ +__STATIC_FORCEINLINE q63_t read_q31x2_ia ( + q31_t ** pQ31) +{ + q63_t val; +#ifndef __RISCV_FEATURE_UNALIGNED +#if __RISCV_XLEN == 64 + val = __LD(*pQ31); +#else + val = *((q63_t *)*pQ31); +#endif /* __RISCV_XLEN == 64 */ +#else + memcpy((void *)(&val), (void *)(*pQ31), 8); +#endif + *pQ31 += 2; + return (val); +} + +/** + @brief Read 2 Q31 from Q31 pointer and decrement pointer afterwards. + @param[in] pQ31 points to input value + @return Q63 value + */ +__STATIC_FORCEINLINE q63_t read_q31x2_da ( + q31_t ** pQ31) +{ + q63_t val; +#ifndef __RISCV_FEATURE_UNALIGNED +#if __RISCV_XLEN == 64 + val = __LD(*pQ31); +#else + val = *((q63_t *)*pQ31); +#endif /* __RISCV_XLEN == 64 */ +#else + memcpy((void *)(&val), (void *)(*pQ31), 8); +#endif + *pQ31 -= 2; + return (val); +} + +/** + @brief Read 2 Q31 from Q31 pointer. + @param[in] pQ31 points to input value + @return Q63 value + */ +__STATIC_FORCEINLINE q63_t read_q31x2 ( + q31_t * pQ31) +{ + q63_t val; +#ifndef __RISCV_FEATURE_UNALIGNED +#if __RISCV_XLEN == 64 + val = __LD(pQ31); +#else + val = *((q63_t *)pQ31); +#endif /* __RISCV_XLEN == 64 */ +#else + memcpy((void *)(&val), (void *)(pQ31), 8); +#endif + return (val); +} + +/** + @brief Write 2 Q31 to Q31 pointer and increment pointer afterwards. + @param[in] pQ31 points to input value + @param[in] value Q63 value + @return none + */ +__STATIC_FORCEINLINE void write_q31x2_ia ( + q31_t ** pQ31, + q63_t value) +{ +#ifndef __RISCV_FEATURE_UNALIGNED +#if __RISCV_XLEN == 64 + __SD(*pQ31, value); +#else + *((q63_t *)*pQ31) = value; +#endif /* __RISCV_XLEN == 64 */ +#else + memcpy((void *)(*pQ31), (void *)(&value), 8); +#endif + *pQ31 += 2; +} + +/** + @brief Write 2 Q31 to Q31 pointer. + @param[in] pQ31 points to input value + @param[in] value Q63 value + @return none + */ +__STATIC_FORCEINLINE void write_q31x2 ( + q31_t * pQ31, + q63_t value) +{ +#ifndef __RISCV_FEATURE_UNALIGNED +#if __RISCV_XLEN == 64 + __SD(pQ31, value); +#else + *((q63_t *)pQ31) = value; +#endif /* __RISCV_XLEN == 64 */ +#else + memcpy((void *)(pQ31), (void *)(&value), 8); +#endif +} + +/** + @brief Read 2 Q15 from Q15 pointer. + @param[in] pQ15 points to input value + @return Q31 value + */ +__STATIC_FORCEINLINE q31_t read_q15x2 ( + q15_t * pQ15) +{ + q31_t val; + +#ifdef __RISCV_FEATURE_UNALIGNED + memcpy (&val, pQ15, 4); +#else + val = __LW(pQ15); +#endif + + return (val); +} + +/** + @brief Read 2 Q15 from Q15 pointer and increment pointer afterwards. + @param[in] pQ15 points to input value + @return Q31 value + */ +__STATIC_FORCEINLINE q31_t read_q15x2_ia ( + q15_t ** pQ15) +{ + q31_t val; + +#ifdef __RISCV_FEATURE_UNALIGNED + memcpy (&val, *pQ15, 4); +#else + val = __LW(*pQ15); +#endif + + *pQ15 += 2; + return (val); +} + +/** + @brief Read 2 Q15 from Q15 pointer and decrement pointer afterwards. + @param[in] pQ15 points to input value + @return Q31 value + */ +__STATIC_FORCEINLINE q31_t read_q15x2_da ( + q15_t ** pQ15) +{ + q31_t val; + +#ifdef __RISCV_FEATURE_UNALIGNED + memcpy (&val, *pQ15, 4); +#else + val = __LW(*pQ15); +#endif + + *pQ15 -= 2; + return (val); +} + +/** + @brief Write 2 Q15 to Q15 pointer and increment pointer afterwards. + @param[in] pQ15 points to input value + @param[in] value Q31 value + @return none + */ +__STATIC_FORCEINLINE void write_q15x2_ia ( + q15_t ** pQ15, + q31_t value) +{ +#ifdef __RISCV_FEATURE_UNALIGNED + memcpy (*pQ15, &value, 4); +#else + __SW(*pQ15, value); +#endif + + *pQ15 += 2; +} + +/** + @brief Write 2 Q15 to Q15 pointer. + @param[in] pQ15 points to input value + @param[in] value Q31 value + @return none + */ +__STATIC_FORCEINLINE void write_q15x2 ( + q15_t * pQ15, + q31_t value) +{ +#ifdef __RISCV_FEATURE_UNALIGNED + memcpy (pQ15, &value, 4); +#else + __SW(pQ15, value); +#endif +} + +/** + @brief Write 4 Q15 to Q15 pointer and increment pointer afterwards. + @param[in] pQ15 points to input value + @param[in] value Q31 value + @return none + */ +__STATIC_FORCEINLINE void write_q15x4_ia ( + q15_t ** pQ15, + q63_t value) +{ +#ifndef __RISCV_FEATURE_UNALIGNED +#if __RISCV_XLEN == 64 + __SD(*pQ15, value); +#else + *((q63_t *)*pQ15) = value; +#endif +#else + memcpy((void *)(*pQ15), (void *)(&value), 8); +#endif + *pQ15 += 4; +} + +/** + @brief Write 4 Q15 to Q15 pointer and decrement pointer afterwards. + @param[in] pQ15 points to input value + @param[in] value Q31 value + @return none + */ +__STATIC_FORCEINLINE void write_q15x4_da ( + q15_t ** pQ15, + q63_t value) +{ +#ifndef __RISCV_FEATURE_UNALIGNED +#if __RISCV_XLEN == 64 + __SD(*pQ15, value); +#else + *((q63_t *)*pQ15) = value; +#endif +#else + memcpy((void *)(*pQ15), (void *)(&value), 8); +#endif + *pQ15 -= 4; +} + +/** + @brief Write 4 Q15 to Q15 pointer. + @param[in] pQ15 points to input value + @param[in] value Q31 value + @return none + */ +__STATIC_FORCEINLINE void write_q15x4 ( + q15_t * pQ15, + q63_t value) +{ +#ifndef __RISCV_FEATURE_UNALIGNED +#if __RISCV_XLEN == 64 + __SD(pQ15, value); +#else + *((q63_t *)pQ15) = value; +#endif +#else + memcpy((void *)(pQ15), (void *)(&value), 8); +#endif +} + +/** + @brief Read 4 Q15 from Q15 pointer and increment pointer afterwards. + @param[in] pQ15 points to input value + @return Q63 value + */ +__STATIC_FORCEINLINE q63_t read_q15x4_ia ( + q15_t ** pQ15) +{ + q63_t val; +#ifndef __RISCV_FEATURE_UNALIGNED +#if __RISCV_XLEN == 64 + val = __LD(*pQ15); +#else + val = *((q63_t *)*pQ15); +#endif +#else + memcpy((void *)(&val), (void *)(*pQ15), 8); +#endif + *pQ15 += 4; + + return (val); +} + +/** + @brief Read 4 Q15 from Q15 pointer and decrement pointer afterwards. + @param[in] pQ15 points to input value + @return Q31 value + */ +__STATIC_FORCEINLINE q63_t read_q15x4_da ( + q15_t ** pQ15) +{ + q63_t val; +#ifndef __RISCV_FEATURE_UNALIGNED +#if __RISCV_XLEN == 64 + val = __LD(*pQ15); +#else + val = *((q63_t *)*pQ15); +#endif +#else + memcpy((void *)(&val), (void *)(*pQ15), 8); +#endif + *pQ15 -= 4; + + return (val); +} + +/** + @brief Read 4 Q15 from Q15 pointer. + @param[in] pQ15 points to input value + @return Q63 value + */ +__STATIC_FORCEINLINE q63_t read_q15x4 ( + q15_t * pQ15) +{ + q63_t val; +#ifndef __RISCV_FEATURE_UNALIGNED +#if __RISCV_XLEN == 64 + val = __LD(pQ15); +#else + val = *((q63_t *)pQ15); +#endif /* __RISCV_XLEN == 64 */ +#else + memcpy((void *)(&val), (void *)(pQ15), 8); +#endif + return (val); +} + +/** + @brief Read 4 Q7 from Q7 pointer and increment pointer afterwards. + @param[in] pQ7 points to input value + @return Q31 value + */ +__STATIC_FORCEINLINE q31_t read_q7x4_ia ( + q7_t ** pQ7) +{ + q31_t val; + + +#ifdef __RISCV_FEATURE_UNALIGNED + memcpy (&val, *pQ7, 4); +#else + val = __LW(*pQ7); +#endif + + *pQ7 += 4; + + return (val); +} + +/** + @brief Read 4 Q7 from Q7 pointer and decrement pointer afterwards. + @param[in] pQ7 points to input value + @return Q31 value + */ +__STATIC_FORCEINLINE q31_t read_q7x4_da ( + q7_t ** pQ7) +{ + q31_t val; +#ifdef __RISCV_FEATURE_UNALIGNED + memcpy (&val, *pQ7, 4); +#else + val = __LW(*pQ7); +#endif + *pQ7 -= 4; + + return (val); +} + +/** + @brief Write 4 Q7 to Q7 pointer and increment pointer afterwards. + @param[in] pQ7 points to input value + @param[in] value Q31 value + @return none + */ +__STATIC_FORCEINLINE void write_q7x4_ia ( + q7_t ** pQ7, + q31_t value) +{ +#ifdef __RISCV_FEATURE_UNALIGNED + q31_t val = value; + memcpy (*pQ7, &val, 4); +#else + __SW(*pQ7, value); +#endif + *pQ7 += 4; +} + +/** + @brief Write 4 Q7 to Q7 pointer. + @param[in] pQ7 points to input value + @param[in] value Q31 value + @return none + */ +__STATIC_FORCEINLINE void write_q7x4 ( + q7_t * pQ7, + q31_t value) +{ +#ifdef __RISCV_FEATURE_UNALIGNED + q31_t val = value; + memcpy (pQ7, &val, 4); +#else + __SW(pQ7, value); +#endif +} + +/** + @brief Read 8 Q7 from Q7 pointer and increment pointer afterwards. + @param[in] pQ7 points to input value + @return Q63 value + */ +__STATIC_FORCEINLINE q63_t read_q7x8_ia ( + q7_t ** pQ7) +{ + q63_t val; +#ifndef __RISCV_FEATURE_UNALIGNED +#if __RISCV_XLEN == 64 + val = __LD(*pQ7); +#else + val = *((q63_t *)*pQ7); +#endif +#else + memcpy((void *)(&val), (void *)(*pQ7), 8); +#endif + *pQ7 += 8; + + return val; +} + +/** + @brief Read 8 Q7 from Q7 pointer and decrement pointer afterwards. + @param[in] pQ7 points to input value + @return Q63 value + */ +__STATIC_FORCEINLINE q63_t read_q7x8_da ( + q7_t ** pQ7) +{ + q63_t val; +#ifndef __RISCV_FEATURE_UNALIGNED +#if __RISCV_XLEN == 64 + val = __LD(*pQ7); +#else + val = *((q63_t *)*pQ7); +#endif +#else + memcpy((void *)(&val), (void *)(*pQ7), 8); +#endif + *pQ7 -= 8; + return val; +} + +/** + @brief Write 8 Q7 to Q7 pointer and increment pointer afterwards. + @param[in] pQ7 points to input value + @param[in] value Q63 value + @return none + */ +__STATIC_FORCEINLINE void write_q7x8_ia ( + q7_t ** pQ7, + q63_t value) +{ +#ifndef __RISCV_FEATURE_UNALIGNED +#if __RISCV_XLEN == 64 + __SD(*pQ7,value); +#else + *((q63_t *)*pQ7) = value; +#endif +#else + memcpy((void *)(*pQ7), (void *)(&value), 8); +#endif + *pQ7 += 8; +} + + +#ifdef __cplusplus +} +#endif + +#endif /*ifndef _RISCV_MATH_MEMORY_H_ */ diff --git a/components/nmsis/dsp/inc/riscv_math_types.h b/components/nmsis/dsp/inc/riscv_math_types.h new file mode 100644 index 00000000..dd682c69 --- /dev/null +++ b/components/nmsis/dsp/inc/riscv_math_types.h @@ -0,0 +1,263 @@ +/****************************************************************************** + * @file riscv_math_types.h + * @brief Public header file for NMSIS DSP Library + * @version V1.9.0 + * @date 23 April 2021 + * Target Processor: RISC-V Cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _RISCV_MATH_TYPES_H_ + +#define _RISCV_MATH_TYPES_H_ + +#ifdef __cplusplus +extern "C" +{ +#endif + +/* Compiler specific diagnostic adjustment */ +#if defined ( __GNUC__ ) + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wsign-conversion" + #pragma GCC diagnostic ignored "-Wconversion" + #pragma GCC diagnostic ignored "-Wunused-parameter" + +#elif defined ( __TI_RISCV__ ) + +#elif defined ( __CSMC__ ) + +#elif defined ( __TASKING__ ) + +#elif defined ( _MSC_VER ) + +#else + #error Unknown compiler +#endif + + +/* Included for instrinsics definitions */ +#if defined (_MSC_VER ) +#include +#define __STATIC_FORCEINLINE static __forceinline +#define __STATIC_INLINE static __inline +#define __ALIGNED(x) __declspec(align(x)) + +#elif defined (__GNUC_PYTHON__) +#include +#define __ALIGNED(x) __attribute__((aligned(x))) +#define __STATIC_FORCEINLINE static inline __attribute__((always_inline)) +#define __STATIC_INLINE static inline + +#else +#define __NMSIS_GENERIC +#if (defined (__RISCV_FEATURE_DSP) && (__RISCV_FEATURE_DSP == 1)) + #define __DSP_PRESENT 1 +#endif +#include "nmsis_core.h" +#undef __NMSIS_GENERIC +#endif + +#if (defined (__RISCV_FEATURE_VECTOR) && (__RISCV_FEATURE_VECTOR == 1)) +#define RISCV_VECTOR 1 +#include +#endif + +#include +#include +#include +#include + +/* evaluate RISCV DSP feature */ +#if (defined (__RISCV_FEATURE_DSP) && (__RISCV_FEATURE_DSP == 1)) + #define RISCV_MATH_DSP 1 +#endif + + + + +#if (__RISCV_FEATURE_MVE & 2) + #define RISCV_MATH_MVEF + #define RISCV_MATH_MVE_FLOAT16 +#endif + + + + + + +#if defined ( __GNUC__ ) + #define LOW_OPTIMIZATION_ENTER \ + __attribute__(( optimize("-O1") )) + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __TI_RISCV__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __CSMC__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __TASKING__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( _MSC_VER ) || defined(__GNUC_PYTHON__) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT +#endif + + + +/* Compiler specific diagnostic adjustment */ +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop + +#elif defined ( __TI_RISCV__ ) + +#elif defined ( __CSMC__ ) + +#elif defined ( __TASKING__ ) + +#elif defined ( _MSC_VER ) + +#else + #error Unknown compiler +#endif + +#ifdef __cplusplus +} +#endif + + +#ifdef __cplusplus +extern "C" +{ +#endif + + /** + * @brief 8-bit fractional data type in 1.7 format. + */ + typedef int8_t q7_t; + + /** + * @brief 16-bit fractional data type in 1.15 format. + */ + typedef int16_t q15_t; + + /** + * @brief 32-bit fractional data type in 1.31 format. + */ + typedef int32_t q31_t; + + /** + * @brief 64-bit fractional data type in 1.63 format. + */ + typedef int64_t q63_t; + + /** + * @brief 32-bit floating-point type definition. + */ + typedef float float32_t; + + /** + * @brief 64-bit floating-point type definition. + */ + typedef double float64_t; + + /** + * @brief vector types + */ + + + + + + + +#define F64_MAX ((float64_t)DBL_MAX) +#define F32_MAX ((float32_t)FLT_MAX) + + + +#define F64_MIN (-DBL_MAX) +#define F32_MIN (-FLT_MAX) + + + +#define F64_ABSMAX ((float64_t)DBL_MAX) +#define F32_ABSMAX ((float32_t)FLT_MAX) + + + +#define F64_ABSMIN ((float64_t)0.0) +#define F32_ABSMIN ((float32_t)0.0) + + +#define Q31_MAX ((q31_t)(0x7FFFFFFFL)) +#define Q15_MAX ((q15_t)(0x7FFF)) +#define Q7_MAX ((q7_t)(0x7F)) +#define Q31_MIN ((q31_t)(0x80000000L)) +#define Q15_MIN ((q15_t)(0x8000)) +#define Q7_MIN ((q7_t)(0x80)) + +#define Q31_ABSMAX ((q31_t)(0x7FFFFFFFL)) +#define Q15_ABSMAX ((q15_t)(0x7FFF)) +#define Q7_ABSMAX ((q7_t)(0x7F)) +#define Q31_ABSMIN ((q31_t)0) +#define Q15_ABSMIN ((q15_t)0) +#define Q7_ABSMIN ((q7_t)0) + + /* Dimension C vector space */ + #define CMPLX_DIM 2 + + /** + * @brief Error status returned by some functions in the library. + */ + + typedef enum + { + RISCV_MATH_SUCCESS = 0, /**< No error */ + RISCV_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ + RISCV_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ + RISCV_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation */ + RISCV_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ + RISCV_MATH_SINGULAR = -5, /**< Input matrix is singular and cannot be inverted */ + RISCV_MATH_TEST_FAILURE = -6, /**< Test Failed */ + RISCV_MATH_DECOMPOSITION_FAILURE = -7 /**< Decomposition Failed */ + } riscv_status; + + +#ifdef __cplusplus +} +#endif + +#endif /*ifndef _RISCV_MATH_TYPES_H_ */ diff --git a/components/nmsis/dsp/inc/riscv_math_types_f16.h b/components/nmsis/dsp/inc/riscv_math_types_f16.h new file mode 100644 index 00000000..7736b53f --- /dev/null +++ b/components/nmsis/dsp/inc/riscv_math_types_f16.h @@ -0,0 +1,79 @@ +/****************************************************************************** + * @file riscv_math_types_f16.h + * @brief Public header file for f16 function of the NMSIS DSP Library + * @version V1.9.0 + * @date 23 April 2021 + * Target Processor: RISC-V Cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _RISCV_MATH_TYPES_F16_H +#define _RISCV_MATH_TYPES_F16_H + +#include "riscv_math_types.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** + * @brief 16-bit floating-point type definition. + * This is already defined in riscv_mve.h + * + * This is not fully supported on ARM AC5. + */ + +/* + +Check if the type __fp16 is available. +If it is not available, f16 version of the kernels +won't be built. + +*/ +#if !(__RISCV_FEATURE_MVE & 2) +#else + /* When Vector float16, this flag is always defined and can't be disabled */ + #define RISCV_FLOAT16_SUPPORTED +#endif + + + + + +#if defined(RISCV_FLOAT16_SUPPORTED) +#define F16_MAX ((float16_t)__FLT16_MAX__) +#define F16_MIN (-(float16_t)__FLT16_MAX__) + +#define F16_ABSMAX ((float16_t)__FLT16_MAX__) +#define F16_ABSMIN ((float16_t)0.0f16) + +#define F16INFINITY ((float16_t)__builtin_inf()) + +#endif /* RISCV_FLOAT16_SUPPORTED*/ + +#ifdef __cplusplus +} +#endif + +#endif /* _RISCV_MATH_F16_H */ + + diff --git a/components/nmsis/dsp/inc/riscv_mve_tables.h b/components/nmsis/dsp/inc/riscv_mve_tables.h new file mode 100644 index 00000000..b504bf9e --- /dev/null +++ b/components/nmsis/dsp/inc/riscv_mve_tables.h @@ -0,0 +1,58 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_mve_tables.h + * Description: common tables like fft twiddle factors, Bitreverse, reciprocal etc + * used for MVE implementation only + * + * @version V1.9.0 + * @date 23 April 2021 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + #ifndef _RISCV_MVE_TABLES_H + #define _RISCV_MVE_TABLES_H + +#include "riscv_math_types.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + + + + + + + + + + + + + +#ifdef __cplusplus +} +#endif + +#endif /*_RISCV_MVE_TABLES_H*/ + diff --git a/components/nmsis/dsp/inc/riscv_mve_tables_f16.h b/components/nmsis/dsp/inc/riscv_mve_tables_f16.h new file mode 100644 index 00000000..2eb13719 --- /dev/null +++ b/components/nmsis/dsp/inc/riscv_mve_tables_f16.h @@ -0,0 +1,52 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_mve_tables_f16.h + * Description: common tables like fft twiddle factors, Bitreverse, reciprocal etc + * used for MVE implementation only + * + * @version V1.9.0 + * @date 23 April 2021 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + #ifndef _RISCV_MVE_TABLES_F16_H + #define _RISCV_MVE_TABLES_F16_H + +#include "riscv_math_types_f16.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + + + + + + + +#ifdef __cplusplus +} +#endif + +#endif /*_RISCV_MVE_TABLES_F16_H*/ + diff --git a/components/nmsis/dsp/inc/riscv_vec_math.h b/components/nmsis/dsp/inc/riscv_vec_math.h new file mode 100644 index 00000000..719dd829 --- /dev/null +++ b/components/nmsis/dsp/inc/riscv_vec_math.h @@ -0,0 +1,52 @@ +/****************************************************************************** + * @file riscv_vec_math.h + * @brief Public header file for NMSIS DSP Library + * @version V1.9.0 + * @date 23 April 2021 + * Target Processor: RISC-V Cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _RISCV_VEC_MATH_H +#define _RISCV_VEC_MATH_H + +#include "riscv_math_types.h" +#include "riscv_common_tables.h" +#include "riscv_helium_utils.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + + + + +#ifdef __cplusplus +} +#endif + + +#endif /* _RISCV_VEC_MATH_H */ + +/** + * + * End of file. + */ diff --git a/components/nmsis/dsp/inc/riscv_vec_math_f16.h b/components/nmsis/dsp/inc/riscv_vec_math_f16.h new file mode 100644 index 00000000..f85c8a52 --- /dev/null +++ b/components/nmsis/dsp/inc/riscv_vec_math_f16.h @@ -0,0 +1,56 @@ +/****************************************************************************** + * @file riscv_vec_math_f16.h + * @brief Public header file for NMSIS DSP Library + * @version V1.9.0 + * @date 23 April 2021 + * Target Processor: RISC-V Cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _RISCV_VEC_MATH_F16_H +#define _RISCV_VEC_MATH_F16_H + +#include "riscv_math_types_f16.h" +#include "riscv_common_tables_f16.h" +#include "riscv_helium_utils.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if defined(RISCV_FLOAT16_SUPPORTED) + + + + + +#ifdef __cplusplus +} +#endif + +#endif /* ARM FLOAT16 SUPPORTED */ + +#endif /* _RISCV_VEC_MATH_F16_H */ + +/** + * + * End of file. + */ diff --git a/components/nmsis/dsp/privateInc/riscv_sorting.h b/components/nmsis/dsp/privateInc/riscv_sorting.h new file mode 100644 index 00000000..8ec44dd0 --- /dev/null +++ b/components/nmsis/dsp/privateInc/riscv_sorting.h @@ -0,0 +1,113 @@ +/****************************************************************************** + * @file riscv_sorting.h + * @brief Private header file for NMSIS DSP Library + * @version V1.7.0 + * @date 2019 + ******************************************************************************/ +/* + * Copyright (c) 2010-2019 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _RISCV_SORTING_H_ +#define _RISCV_SORTING_H_ + +#include "riscv_math.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + + /** + * @param[in] S points to an instance of the sorting structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void riscv_bubble_sort_f32( + const riscv_sort_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @param[in] S points to an instance of the sorting structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void riscv_heap_sort_f32( + const riscv_sort_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @param[in] S points to an instance of the sorting structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void riscv_insertion_sort_f32( + const riscv_sort_instance_f32 * S, + float32_t *pSrc, + float32_t* pDst, + uint32_t blockSize); + + /** + * @param[in] S points to an instance of the sorting structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void riscv_quick_sort_f32( + const riscv_sort_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @param[in] S points to an instance of the sorting structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void riscv_selection_sort_f32( + const riscv_sort_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @param[in] S points to an instance of the sorting structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void riscv_bitonic_sort_f32( + const riscv_sort_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + +#ifdef __cplusplus +} +#endif + +#endif /* _RISCV_SORTING_H */ diff --git a/components/nmsis/dsp/privateInc/riscv_vec_fft.h b/components/nmsis/dsp/privateInc/riscv_vec_fft.h new file mode 100644 index 00000000..e7214f09 --- /dev/null +++ b/components/nmsis/dsp/privateInc/riscv_vec_fft.h @@ -0,0 +1,44 @@ +/****************************************************************************** + * @file riscv_vec_fft.h + * @brief Private header file for NMSIS DSP Library + * @version V1.7.0 + * @date 07. January 2020 + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _RISCV_VEC_FFT_H_ +#define _RISCV_VEC_FFT_H_ + +#include "riscv_math.h" +#include "riscv_helium_utils.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + + + +#ifdef __cplusplus +} +#endif + + +#endif /* _RISCV_VEC_FFT_H_ */ diff --git a/components/nmsis/dsp/privateInc/riscv_vec_filtering.h b/components/nmsis/dsp/privateInc/riscv_vec_filtering.h new file mode 100644 index 00000000..5223a12e --- /dev/null +++ b/components/nmsis/dsp/privateInc/riscv_vec_filtering.h @@ -0,0 +1,44 @@ +/****************************************************************************** + * @file riscv_vec_filtering.h + * @brief Private header file for NMSIS DSP Library + * @version V1.7.0 + * @date 30. October 2019 + ******************************************************************************/ +/* + * Copyright (c) 2010-2019 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _RISCV_VEC_FILTERING_H_ +#define _RISCV_VEC_FILTERING_H_ + +#include "riscv_math.h" +#include "riscv_helium_utils.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + + + +#ifdef __cplusplus +} +#endif + + +#endif /* _RISCV_VEC_FILTERING_H_ */ diff --git a/components/nmsis/dsp/src/BasicMathFunctions/BasicMathFunctions.c b/components/nmsis/dsp/src/BasicMathFunctions/BasicMathFunctions.c new file mode 100644 index 00000000..439e10dd --- /dev/null +++ b/components/nmsis/dsp/src/BasicMathFunctions/BasicMathFunctions.c @@ -0,0 +1,80 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: BasicMathFunctions.c + * Description: Combination of all basic math function source files. + * + * $Date: 16. March 2020 + * $Revision: V1.1.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2019-2020 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "riscv_abs_f32.c" +#include "riscv_abs_q15.c" +#include "riscv_abs_q31.c" +#include "riscv_abs_q7.c" +#include "riscv_add_f32.c" +#include "riscv_add_q15.c" +#include "riscv_add_q31.c" +#include "riscv_add_q7.c" +#include "riscv_and_u16.c" +#include "riscv_and_u32.c" +#include "riscv_and_u8.c" +#include "riscv_dot_prod_f32.c" +#include "riscv_dot_prod_q15.c" +#include "riscv_dot_prod_q31.c" +#include "riscv_dot_prod_q7.c" +#include "riscv_mult_f32.c" +#include "riscv_mult_q15.c" +#include "riscv_mult_q31.c" +#include "riscv_mult_q7.c" +#include "riscv_negate_f32.c" +#include "riscv_negate_q15.c" +#include "riscv_negate_q31.c" +#include "riscv_negate_q7.c" +#include "riscv_not_u16.c" +#include "riscv_not_u32.c" +#include "riscv_not_u8.c" +#include "riscv_offset_f32.c" +#include "riscv_offset_q15.c" +#include "riscv_offset_q31.c" +#include "riscv_offset_q7.c" +#include "riscv_or_u16.c" +#include "riscv_or_u32.c" +#include "riscv_or_u8.c" +#include "riscv_scale_f32.c" +#include "riscv_scale_q15.c" +#include "riscv_scale_q31.c" +#include "riscv_scale_q7.c" +#include "riscv_shift_q15.c" +#include "riscv_shift_q31.c" +#include "riscv_shift_q7.c" +#include "riscv_sub_f32.c" +#include "riscv_sub_q15.c" +#include "riscv_sub_q31.c" +#include "riscv_sub_q7.c" +#include "riscv_xor_u16.c" +#include "riscv_xor_u32.c" +#include "riscv_xor_u8.c" +#include "riscv_clip_f32.c" +#include "riscv_clip_q31.c" +#include "riscv_clip_q15.c" +#include "riscv_clip_q7.c" \ No newline at end of file diff --git a/components/nmsis/dsp/src/BasicMathFunctions/BasicMathFunctionsF16.c b/components/nmsis/dsp/src/BasicMathFunctions/BasicMathFunctionsF16.c new file mode 100644 index 00000000..8d4b70aa --- /dev/null +++ b/components/nmsis/dsp/src/BasicMathFunctions/BasicMathFunctionsF16.c @@ -0,0 +1,38 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: BasicMathFunctionsF16.c + * Description: Combination of all basic math function f16 source files. + * + * $Date: 20. April 2020 + * $Revision: V1.1.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2019-2020 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "riscv_abs_f16.c" +#include "riscv_add_f16.c" +#include "riscv_dot_prod_f16.c" +#include "riscv_mult_f16.c" +#include "riscv_negate_f16.c" +#include "riscv_offset_f16.c" +#include "riscv_scale_f16.c" +#include "riscv_sub_f16.c" +#include "riscv_clip_f16.c" diff --git a/components/nmsis/dsp/src/BasicMathFunctions/riscv_abs_f16.c b/components/nmsis/dsp/src/BasicMathFunctions/riscv_abs_f16.c new file mode 100644 index 00000000..60469884 --- /dev/null +++ b/components/nmsis/dsp/src/BasicMathFunctions/riscv_abs_f16.c @@ -0,0 +1,120 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_abs_f16.c + * Description: Floating-point vector absolute value + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions_f16.h" +#include + +/** + @ingroup groupMath + */ + +/** + @defgroup BasicAbs Vector Absolute Value + + Computes the absolute value of a vector on an element-by-element basis. + + 
+      pDst[n] = abs(pSrc[n]),   0 <= n < blockSize.
+
+ + The functions support in-place computation allowing the source and + destination pointers to reference the same memory buffer. + There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + @addtogroup BasicAbs + @{ + */ + +/** + @brief Floating-point vector absolute value. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + + +#if defined(RISCV_FLOAT16_SUPPORTED) +void riscv_abs_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = |A| */ + + /* Calculate absolute and store result in destination buffer. */ + *pDst++ = fabsf(*pSrc++); + + *pDst++ = fabsf(*pSrc++); + + *pDst++ = fabsf(*pSrc++); + + *pDst++ = fabsf(*pSrc++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = |A| */ + + /* Calculate absolute and store result in destination buffer. */ + *pDst++ = fabsf(*pSrc++); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(RISCV_FLOAT16_SUPPORTED */ +/** + @} end of BasicAbs group + */ diff --git a/components/nmsis/dsp/src/BasicMathFunctions/riscv_abs_f32.c b/components/nmsis/dsp/src/BasicMathFunctions/riscv_abs_f32.c new file mode 100644 index 00000000..1b047616 --- /dev/null +++ b/components/nmsis/dsp/src/BasicMathFunctions/riscv_abs_f32.c @@ -0,0 +1,128 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_abs_f32.c + * Description: Floating-point vector absolute value + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" +#include + +/** + @ingroup groupMath + */ + +/** + @defgroup BasicAbs Vector Absolute Value + + Computes the absolute value of a vector on an element-by-element basis. + + 
+      pDst[n] = abs(pSrc[n]),   0 <= n < blockSize.
+
+ + The functions support in-place computation allowing the source and + destination pointers to reference the same memory buffer. + There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + @addtogroup BasicAbs + @{ + */ + +/** + @brief Floating-point vector absolute value. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + + +void riscv_abs_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ +#if defined(RISCV_VECTOR) + vfloat32m8_t vx; + blkCnt = blockSize; + size_t l; + for (; (l = vsetvl_e32m8(blkCnt)) > 0; blkCnt -= l) { + vx = vle32_v_f32m8(pSrc, l); + vse32_v_f32m8 (pDst, vfsgnjx_vv_f32m8(vx, vx, l), l); + pSrc += l; + pDst += l; + } +#else +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = |A| */ + + /* Calculate absolute and store result in destination buffer. */ + *pDst++ = fabsf(*pSrc++); + + *pDst++ = fabsf(*pSrc++); + + *pDst++ = fabsf(*pSrc++); + + *pDst++ = fabsf(*pSrc++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = |A| */ + + /* Calculate absolute and store result in destination buffer. */ + *pDst++ = fabsf(*pSrc++); + + /* Decrement loop counter */ + blkCnt--; + } +#endif +} +/** + @} end of BasicAbs group + */ diff --git a/components/nmsis/dsp/src/BasicMathFunctions/riscv_abs_q15.c b/components/nmsis/dsp/src/BasicMathFunctions/riscv_abs_q15.c new file mode 100644 index 00000000..e86d7f7d --- /dev/null +++ b/components/nmsis/dsp/src/BasicMathFunctions/riscv_abs_q15.c @@ -0,0 +1,126 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_abs_q15.c + * Description: Q15 vector absolute value + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicAbs + @{ + */ + +/** + @brief Q15 vector absolute value. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + The Q15 value -1 (0x8000) will be saturated to the maximum allowable positive value 0x7FFF. + */ + +void riscv_abs_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + q15_t in; /* Temporary input variable */ + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = |A| */ + + /* Calculate absolute of input (if -1 then saturated to 0x7fff) and store result in destination buffer. */ +#if defined (RISCV_MATH_DSP) +#if __RISCV_XLEN == 64 + write_q15x4_ia (&pDst, __RV_KABS16(read_q15x4_ia ((q15_t **) &pSrc))); +#else +#ifdef RISCV_DSP64 + write_q15x4_ia (&pDst, __RV_DKABS16(read_q15x4_ia ((q15_t **) &pSrc))); +#else + write_q15x2_ia (&pDst, __RV_KABS16(read_q15x2_ia ((q15_t **) &pSrc))); + write_q15x2_ia (&pDst, __RV_KABS16(read_q15x2_ia ((q15_t **) &pSrc))); +#endif + in = *pSrc++; + *pDst++ = (in > 0) ? in : ((in == (q15_t) 0x8000) ? 0x7fff : -in); + in = *pSrc++; + *pDst++ = (in > 0) ? in : ((in == (q15_t) 0x8000) ? 0x7fff : -in); + in = *pSrc++; + *pDst++ = (in > 0) ? in : ((in == (q15_t) 0x8000) ? 0x7fff : -in); + in = *pSrc++; + *pDst++ = (in > 0) ? in : ((in == (q15_t) 0x8000) ? 0x7fff : -in); +#endif +#endif /* __RISCV_XLEN == 64 */ + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = |A| */ + + /* Calculate absolute of input (if -1 then saturated to 0x7fff) and store result in destination buffer. */ + in = *pSrc++; +#if defined (RISCV_MATH_DSP) + //*pDst++ = (in > 0) ? in : (q15_t)__QSUB16(0, in); + *pDst++ = (q15_t)__RV_KABSW(in); +#else + *pDst++ = (in > 0) ? in : ((in == (q15_t) 0x8000) ? 0x7fff : -in); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of BasicAbs group + */ diff --git a/components/nmsis/dsp/src/BasicMathFunctions/riscv_abs_q31.c b/components/nmsis/dsp/src/BasicMathFunctions/riscv_abs_q31.c new file mode 100644 index 00000000..577e8dd1 --- /dev/null +++ b/components/nmsis/dsp/src/BasicMathFunctions/riscv_abs_q31.c @@ -0,0 +1,137 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_abs_q31.c + * Description: Q31 vector absolute value + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicAbs + @{ + */ + +/** + @brief Q31 vector absolute value. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + The Q31 value -1 (0x80000000) will be saturated to the maximum allowable positive value 0x7FFFFFFF. + */ + +void riscv_abs_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + q31_t in; /* Temporary variable */ + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = |A| */ +#if __RISCV_XLEN == 64 + write_q31x2_ia (&pDst, __RV_KABS32(read_q31x2_ia ((q31_t **) &pSrc))); + write_q31x2_ia (&pDst, __RV_KABS32(read_q31x2_ia ((q31_t **) &pSrc))); +#else + /* Calculate absolute of input (if -1 then saturated to 0x7fffffff) and store result in destination buffer. */ + in = *pSrc++; +#if defined (RISCV_MATH_DSP) + *pDst++ = __KABSW(in); +#else + *pDst++ = (in > 0) ? in : ((in == INT32_MIN) ? INT32_MAX : -in); +#endif + + in = *pSrc++; +#if defined (RISCV_MATH_DSP) + *pDst++ = __KABSW(in); +#else + *pDst++ = (in > 0) ? in : ((in == INT32_MIN) ? INT32_MAX : -in); +#endif + + in = *pSrc++; +#if defined (RISCV_MATH_DSP) + *pDst++ = __KABSW(in); +#else + *pDst++ = (in > 0) ? in : ((in == INT32_MIN) ? INT32_MAX : -in); +#endif + + in = *pSrc++; +#if defined (RISCV_MATH_DSP) + *pDst++ = __KABSW(in); +#else + *pDst++ = (in > 0) ? in : ((in == INT32_MIN) ? INT32_MAX : -in); +#endif + + /* Decrement loop counter */ +#endif /* __RISCV_XLEN == 64 */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = |A| */ + + /* Calculate absolute of input (if -1 then saturated to 0x7fffffff) and store result in destination buffer. */ + in = *pSrc++; +#if defined (RISCV_MATH_DSP) + //*pDst++ = (in > 0) ? in : (q31_t)__QSUB(0, in); + *pDst++ = __KABSW(in); +#else + *pDst++ = (in > 0) ? in : ((in == INT32_MIN) ? INT32_MAX : -in); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + +} +/** + @} end of BasicAbs group + */ diff --git a/components/nmsis/dsp/src/BasicMathFunctions/riscv_abs_q7.c b/components/nmsis/dsp/src/BasicMathFunctions/riscv_abs_q7.c new file mode 100644 index 00000000..65647deb --- /dev/null +++ b/components/nmsis/dsp/src/BasicMathFunctions/riscv_abs_q7.c @@ -0,0 +1,131 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_abs_q7.c + * Description: Q7 vector absolute value + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicAbs + @{ + */ + +/** + @brief Q7 vector absolute value. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Conditions for optimum performance + Input and output buffers should be aligned by 32-bit + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + The Q7 value -1 (0x80) will be saturated to the maximum allowable positive value 0x7F. + */ + +void riscv_abs_q7( + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + q7_t in; /* Temporary input variable */ + +#if defined (RISCV_MATH_LOOPUNROLL) +#if defined (RISCV_DSP64) || (__RISCV_XLEN == 64) + /* Loop unrolling: Compute 8 outputs at a time */ + blkCnt = blockSize >> 3U; +#else + blkCnt = blockSize >> 2U; +#endif + + while (blkCnt > 0U) + { + /* C = |A| */ + + /* Calculate absolute of input (if -1 then saturated to 0x7f) and store result in destination buffer. */ +#if defined (RISCV_MATH_DSP) +#if __RISCV_XLEN == 64 + write_q7x8_ia (&pDst, __RV_KABS8(read_q7x8_ia ((q7_t **) &pSrc))); +#else +#if defined (RISCV_DSP64) + write_q7x8_ia (&pDst, __RV_DKABS8(read_q7x8_ia ((q7_t **) &pSrc))); +#else + write_q7x4_ia (&pDst, __RV_KABS8(read_q7x4_ia ((q7_t **) &pSrc))); +#endif +#endif /* __RISCV_XLEN == 64 */ +#else + in = *pSrc++; + *pDst++ = (in > 0) ? in : ((in == (q7_t) 0x80) ? (q7_t) 0x7f : -in); + *pDst++ = (in > 0) ? in : ((in == (q7_t) 0x80) ? (q7_t) 0x7f : -in); +#endif /* defined (RISCV_DSP64) || (__RISCV_XLEN == 64) */ + + /* Decrement loop counter */ + blkCnt--; + } + +#if defined (RISCV_DSP64) || (__RISCV_XLEN == 64) + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x8U; +#else + blkCnt = blockSize % 0x4U; +#endif /* defined (RISCV_DSP64) || (__RISCV_XLEN == 64) */ + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = |A| */ + + /* Calculate absolute of input (if -1 then saturated to 0x7f) and store result in destination buffer. */ + in = *pSrc++; +#if defined (RISCV_MATH_DSP) + *pDst++ = (q7_t)__RV_KABSW(in); +#else + *pDst++ = (in > 0) ? in : ((in == (q7_t) 0x80) ? (q7_t) 0x7f : -in); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of BasicAbs group + */ + diff --git a/components/nmsis/dsp/src/BasicMathFunctions/riscv_add_f16.c b/components/nmsis/dsp/src/BasicMathFunctions/riscv_add_f16.c new file mode 100644 index 00000000..ccc67b65 --- /dev/null +++ b/components/nmsis/dsp/src/BasicMathFunctions/riscv_add_f16.c @@ -0,0 +1,116 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_add_f16.c + * Description: Floating-point vector addition + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions_f16.h" + +/** + @ingroup groupMath + */ + +/** + @defgroup BasicAdd Vector Addition + + Element-by-element addition of two vectors. + + 
+      pDst[n] = pSrcA[n] + pSrcB[n],   0 <= n < blockSize.
+
+ + There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + @addtogroup BasicAdd + @{ + */ + +/** + @brief Floating-point vector addition. + @param[in] pSrcA points to first input vector + @param[in] pSrcB points to second input vector + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +#if defined(RISCV_FLOAT16_SUPPORTED) +void riscv_add_f16( + const float16_t * pSrcA, + const float16_t * pSrcB, + float16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A + B */ + + /* Add and store result in destination buffer. */ + *pDst++ = (*pSrcA++) + (*pSrcB++); + *pDst++ = (*pSrcA++) + (*pSrcB++); + *pDst++ = (*pSrcA++) + (*pSrcB++); + *pDst++ = (*pSrcA++) + (*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A + B */ + + /* Add and store result in destination buffer. */ + *pDst++ = (*pSrcA++) + (*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(RISCV_FLOAT16_SUPPORTED) */ + +/** + @} end of BasicAdd group + */ diff --git a/components/nmsis/dsp/src/BasicMathFunctions/riscv_add_f32.c b/components/nmsis/dsp/src/BasicMathFunctions/riscv_add_f32.c new file mode 100644 index 00000000..287174be --- /dev/null +++ b/components/nmsis/dsp/src/BasicMathFunctions/riscv_add_f32.c @@ -0,0 +1,129 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_add_f32.c + * Description: Floating-point vector addition + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @defgroup BasicAdd Vector Addition + + Element-by-element addition of two vectors. + + 
+      pDst[n] = pSrcA[n] + pSrcB[n],   0 <= n < blockSize.
+
+ + There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + @addtogroup BasicAdd + @{ + */ + +/** + @brief Floating-point vector addition. + @param[in] pSrcA points to first input vector + @param[in] pSrcB points to second input vector + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +void riscv_add_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + size_t l; + vfloat32m8_t vx, vy; + + for (; (l = vsetvl_e32m8(blkCnt)) > 0; blkCnt -= l) { + vx = vle32_v_f32m8(pSrcA, l); + pSrcA += l; + vy = vle32_v_f32m8(pSrcB, l); + vse32_v_f32m8 (pDst, vfadd_vv_f32m8(vy, vx, l), l); + pSrcB += l; + pDst += l; + } + +#else + uint32_t blkCnt; /* Loop counter */ + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A + B */ + + /* Add and store result in destination buffer. */ + *pDst++ = (*pSrcA++) + (*pSrcB++); + *pDst++ = (*pSrcA++) + (*pSrcB++); + *pDst++ = (*pSrcA++) + (*pSrcB++); + *pDst++ = (*pSrcA++) + (*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A + B */ + + /* Add and store result in destination buffer. */ + *pDst++ = (*pSrcA++) + (*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } +#endif /*defined(RISCV_VECTOR)*/ +} + +/** + @} end of BasicAdd group + */ diff --git a/components/nmsis/dsp/src/BasicMathFunctions/riscv_add_q15.c b/components/nmsis/dsp/src/BasicMathFunctions/riscv_add_q15.c new file mode 100644 index 00000000..bc3bb88c --- /dev/null +++ b/components/nmsis/dsp/src/BasicMathFunctions/riscv_add_q15.c @@ -0,0 +1,147 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_add_q15.c + * Description: Q15 vector addition + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicAdd + @{ + */ + +/** + @brief Q15 vector addition. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q15 range [0x8000 0x7FFF] are saturated. + */ + +void riscv_add_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + size_t l; + vint16m8_t vx, vy; + + for (; (l = vsetvl_e16m8(blkCnt)) > 0; blkCnt -= l) { + vx = vle16_v_i16m8(pSrcA, l); + pSrcA += l; + vy = vle16_v_i16m8(pSrcB, l); + vse16_v_i16m8 (pDst, vsadd_vv_i16m8(vy, vx, l), l); + pSrcB += l; + pDst += l; + } +#else + uint32_t blkCnt; /* Loop counter */ + +#if defined (RISCV_MATH_LOOPUNROLL) + +#if defined (RISCV_MATH_DSP) + q31_t inA1, inA2; + q31_t inB1, inB2; +#endif + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A + B */ + +#if defined (RISCV_MATH_DSP) + ///* read 2 times 2 samples at a time from sourceA */ + //inA1 = read_q15x2_ia ((q15_t **) &pSrcA); + //inA2 = read_q15x2_ia ((q15_t **) &pSrcA); + ///* read 2 times 2 samples at a time from sourceB */ + //inB1 = read_q15x2_ia ((q15_t **) &pSrcB); + //inB2 = read_q15x2_ia ((q15_t **) &pSrcB); + + ///* Add and store 2 times 2 samples at a time */ + //write_q15x2_ia (&pDst, __QADD16(inA1, inB1)); + //write_q15x2_ia (&pDst, __QADD16(inA2, inB2)); +#if __RISCV_XLEN == 64 + write_q15x4_ia(&pDst, __RV_KADD16(read_q15x4_ia((q15_t **)&pSrcA), read_q15x4_ia((q15_t **)&pSrcB))); +#else +#ifdef RISCV_DSP64 + write_q15x4_ia(&pDst, __RV_DKADD16(read_q15x4_ia((q15_t **)&pSrcA), read_q15x4_ia((q15_t **)&pSrcB))); +#else + write_q15x2_ia(&pDst, __RV_KADD16(read_q15x2_ia((q15_t **)&pSrcA), read_q15x2_ia((q15_t **)&pSrcB))); + write_q15x2_ia(&pDst, __RV_KADD16(read_q15x2_ia((q15_t **)&pSrcA), read_q15x2_ia((q15_t **)&pSrcB))); +#endif +#endif /* __RISCV_XLEN == 64 */ + +#else + *pDst++ = (q15_t) __SSAT(((q31_t) *pSrcA++ + *pSrcB++), 16); + *pDst++ = (q15_t) __SSAT(((q31_t) *pSrcA++ + *pSrcB++), 16); + *pDst++ = (q15_t) __SSAT(((q31_t) *pSrcA++ + *pSrcB++), 16); + *pDst++ = (q15_t) __SSAT(((q31_t) *pSrcA++ + *pSrcB++), 16); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A + B */ + + /* Add and store result in destination buffer. */ + *pDst++ = (q15_t) __QADD16(*pSrcA++, *pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } +#endif /* defined(RISCV_VECTOR) */ +} +/** + @} end of BasicAdd group + */ diff --git a/components/nmsis/dsp/src/BasicMathFunctions/riscv_add_q31.c b/components/nmsis/dsp/src/BasicMathFunctions/riscv_add_q31.c new file mode 100644 index 00000000..4050ceff --- /dev/null +++ b/components/nmsis/dsp/src/BasicMathFunctions/riscv_add_q31.c @@ -0,0 +1,123 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_add_q31.c + * Description: Q31 vector addition + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicAdd + @{ + */ + +/** + @brief Q31 vector addition. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] are saturated. + */ + +void riscv_add_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + size_t l; + vint32m8_t vx, vy; + + for (; (l = vsetvl_e32m8(blkCnt)) > 0; blkCnt -= l) { + vx = vle32_v_i32m8(pSrcA, l); + pSrcA += l; + vy = vle32_v_i32m8(pSrcB, l); + vse32_v_i32m8 (pDst, vsadd_vv_i32m8(vy, vx, l), l); + pSrcB += l; + pDst += l; + } +#else + uint32_t blkCnt; /* Loop counter */ + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A + B */ +#if __RISCV_XLEN == 64 + write_q31x2_ia (&pDst, __RV_KADD32(read_q31x2_ia ((q31_t **) &pSrcA),read_q31x2_ia ((q31_t **) &pSrcB))); + write_q31x2_ia (&pDst, __RV_KADD32(read_q31x2_ia ((q31_t **) &pSrcA),read_q31x2_ia ((q31_t **) &pSrcB))); +#else + /* Add and store result in destination buffer. */ + *pDst++ = __RV_KADDW(*pSrcA++, *pSrcB++); + *pDst++ = __RV_KADDW(*pSrcA++, *pSrcB++); + *pDst++ = __RV_KADDW(*pSrcA++, *pSrcB++); + *pDst++ = __RV_KADDW(*pSrcA++, *pSrcB++); + #endif /* __RISCV_XLEN == 64 */ + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A + B */ + + /* Add and store result in destination buffer. */ + *pDst++ = __QADD(*pSrcA++, *pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of BasicAdd group + */ diff --git a/components/nmsis/dsp/src/BasicMathFunctions/riscv_add_q7.c b/components/nmsis/dsp/src/BasicMathFunctions/riscv_add_q7.c new file mode 100644 index 00000000..5aef2dd2 --- /dev/null +++ b/components/nmsis/dsp/src/BasicMathFunctions/riscv_add_q7.c @@ -0,0 +1,141 @@ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_add_q7.c + * Description: Q7 vector addition + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicAdd + @{ + */ + +/** + @brief Q7 vector addition. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q7 range [0x80 0x7F] are saturated. + */ + +void riscv_add_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + size_t l; + vint8m8_t vx, vy; + + for (; (l = vsetvl_e32m8(blkCnt)) > 0; blkCnt -= l) { + vx = vle8_v_i8m8(pSrcA, l); + pSrcA += l; + vy = vle8_v_i8m8(pSrcB, l); + vse8_v_i8m8 (pDst, vsadd_vv_i8m8(vy, vx, l), l); + pSrcB += l; + pDst += l; + } +#else + uint32_t blkCnt; /* Loop counter */ + +#if defined (RISCV_MATH_LOOPUNROLL) + +#if defined (RISCV_DSP64) || (__RISCV_XLEN == 64) + /* Loop unrolling: Compute 8 outputs at a time */ + blkCnt = blockSize >> 3U; +#else + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; +#endif + + while (blkCnt > 0U) + { + /* C = A + B */ + +#if defined (RISCV_MATH_DSP) +#if __RISCV_XLEN == 64 + write_q7x8_ia (&pDst, __RV_KADD8 (read_q7x8_ia ((q7_t **) &pSrcA), read_q7x8_ia ((q7_t **) &pSrcB))); +#else +#ifdef RISCV_DSP64 + /* Add and store result in destination buffer (4 samples at a time). */ + write_q7x8_ia (&pDst, __RV_DKADD8 (read_q7x8_ia ((q7_t **) &pSrcA), read_q7x8_ia ((q7_t **) &pSrcB))); +#else + write_q7x4_ia (&pDst, __RV_KADD8 (read_q7x4_ia ((q7_t **) &pSrcA), read_q7x4_ia ((q7_t **) &pSrcB))); +#endif +#endif /* __RISCV_XLEN == 64 */ +#else + *pDst++ = (q7_t) __SSAT((q15_t) *pSrcA++ + *pSrcB++, 8); + *pDst++ = (q7_t) __SSAT((q15_t) *pSrcA++ + *pSrcB++, 8); + *pDst++ = (q7_t) __SSAT((q15_t) *pSrcA++ + *pSrcB++, 8); + *pDst++ = (q7_t) __SSAT((q15_t) *pSrcA++ + *pSrcB++, 8); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + +#if defined (RISCV_DSP64) || (__RISCV_XLEN == 64) + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x8U; +#else + blkCnt = blockSize % 0x4U; +#endif + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A + B */ + + /* Add and store result in destination buffer. */ + *pDst++ = (q7_t) __SSAT((q15_t) *pSrcA++ + *pSrcB++, 8); + + /* Decrement loop counter */ + blkCnt--; + } +#endif /* defined(RISCV_VECTOR) */ +} +/** + @} end of BasicAdd group + */ diff --git a/components/nmsis/dsp/src/BasicMathFunctions/riscv_and_u16.c b/components/nmsis/dsp/src/BasicMathFunctions/riscv_and_u16.c new file mode 100644 index 00000000..d3fd820a --- /dev/null +++ b/components/nmsis/dsp/src/BasicMathFunctions/riscv_and_u16.c @@ -0,0 +1,133 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_and_u16.c + * Description: uint16_t bitwise AND + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @defgroup And Vector bitwise AND + + Compute the logical bitwise AND. + + There are separate functions for uint32_t, uint16_t, and uint7_t data types. + */ + +/** + @addtogroup And + @{ + */ + +/** + @brief Compute the logical bitwise AND of two fixed-point vectors. + @param[in] pSrcA points to input vector A + @param[in] pSrcB points to input vector B + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +void riscv_and_u16( + const uint16_t * pSrcA, + const uint16_t * pSrcB, + uint16_t * pDst, + uint32_t blockSize) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + size_t l; + vuint16m8_t vx, vy; + + for (; (l = vsetvl_e16m8(blkCnt)) > 0; blkCnt -= l) { + vx = vle16_v_u16m8(pSrcA, l); + pSrcA += l; + vy = vle16_v_u16m8(pSrcB, l); + vse16_v_u16m8 (pDst, vand_vv_u16m8(vx, vy, l), l); + pSrcB += l; + pDst += l; + } +#else + uint32_t blkCnt; /* Loop counter */ + +#if defined (RISCV_DSP64) || (__RISCV_XLEN == 64) + + uint64_t * pSrcA_temp = pSrcA; + uint64_t * pSrcB_temp = pSrcB; + uint64_t * pDst_temp = pDst; + if(blkCnt = blockSize >> 2) + { + while (blkCnt > 0U) + { + *pDst_temp++ = (*pSrcA_temp++)&(*pSrcB_temp++); + + /* Decrement the loop counter */ + blkCnt--; + } + } + if(blkCnt = blockSize%4) + { + pSrcA = (uint8_t * )(pSrcA_temp-3); + pSrcB = (uint8_t * )(pSrcB_temp-3); + } + +#else + uint32_t * pSrcA_temp = pSrcA; + uint32_t * pSrcB_temp = pSrcB; + uint32_t * pDst_temp = pDst; + if(blkCnt = blockSize >> 1) + { + while (blkCnt > 0U) + { + *pDst_temp++ = (*pSrcA_temp++)&(*pSrcB_temp++); + + /* Decrement the loop counter */ + blkCnt--; + } + } + if(blkCnt = blockSize%2) + { + pSrcA = (uint8_t * )(pSrcA_temp-1); + pSrcB = (uint8_t * )(pSrcB_temp-1); + } +#endif + while (blkCnt > 0U) + { + *pDst++ = (*pSrcA++)&(*pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of And group + */ diff --git a/components/nmsis/dsp/src/BasicMathFunctions/riscv_and_u32.c b/components/nmsis/dsp/src/BasicMathFunctions/riscv_and_u32.c new file mode 100644 index 00000000..c1a0da50 --- /dev/null +++ b/components/nmsis/dsp/src/BasicMathFunctions/riscv_and_u32.c @@ -0,0 +1,109 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_and_u32.c + * Description: uint32_t bitwise AND + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup And + @{ + */ + +/** + @brief Compute the logical bitwise AND of two fixed-point vectors. + @param[in] pSrcA points to input vector A + @param[in] pSrcB points to input vector B + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +void riscv_and_u32( + const uint32_t * pSrcA, + const uint32_t * pSrcB, + uint32_t * pDst, + uint32_t blockSize) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + size_t l; + vuint32m8_t vx, vy; + + for (; (l = vsetvl_e32m8(blkCnt)) > 0; blkCnt -= l) { + vx = vle32_v_u32m8(pSrcA, l); + pSrcA += l; + vy = vle32_v_u32m8(pSrcB, l); + vse32_v_u32m8 (pDst, vand_vv_u32m8(vx, vy, l), l); + pSrcB += l; + pDst += l; + } +#else + uint32_t blkCnt; /* Loop counter */ + +#if defined (RISCV_DSP64) || (__RISCV_XLEN == 64) + + uint64_t * pSrcA_temp = pSrcA; + uint64_t * pSrcB_temp = pSrcB; + uint64_t * pDst_temp = pDst; + if(blkCnt = blockSize >> 1) + { + while (blkCnt > 0U) + { + *pDst_temp++ = (*pSrcA_temp++)&(*pSrcB_temp++); + + /* Decrement the loop counter */ + blkCnt--; + } + } + if(blkCnt = blockSize%2) + { + pSrcA = (uint8_t * )(pSrcA_temp-1); + pSrcB = (uint8_t * )(pSrcB_temp-1); + } + +#else + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; +#endif + while (blkCnt > 0U) + { + *pDst++ = (*pSrcA++)&(*pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of And group + */ diff --git a/components/nmsis/dsp/src/BasicMathFunctions/riscv_and_u8.c b/components/nmsis/dsp/src/BasicMathFunctions/riscv_and_u8.c new file mode 100644 index 00000000..08cabcc8 --- /dev/null +++ b/components/nmsis/dsp/src/BasicMathFunctions/riscv_and_u8.c @@ -0,0 +1,128 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_and_u8.c + * Description: uint8_t bitwise AND + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + + +/** + @addtogroup And + @{ + */ + +/** + @brief Compute the logical bitwise AND of two fixed-point vectors. + @param[in] pSrcA points to input vector A + @param[in] pSrcB points to input vector B + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +void riscv_and_u8( + const uint8_t * pSrcA, + const uint8_t * pSrcB, + uint8_t * pDst, + uint32_t blockSize) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + size_t l; + vuint8m8_t vx, vy; + + for (; (l = vsetvl_e8m8(blkCnt)) > 0; blkCnt -= l) { + vx = vle8_v_u8m8(pSrcA, l); + pSrcA += l; + vy = vle8_v_u8m8(pSrcB, l); + vse8_v_u8m8 (pDst, vand_vv_u8m8(vx, vy, l), l); + pSrcB += l; + pDst += l; + } +#else + uint32_t blkCnt; /* Loop counter */ + +#if defined (RISCV_DSP64) || (__RISCV_XLEN == 64) + + uint64_t * pSrcA_temp = pSrcA; + uint64_t * pSrcB_temp = pSrcB; + uint64_t * pDst_temp = pDst; + if(blkCnt = blockSize >> 3) + { + while (blkCnt > 0U) + { + *pDst_temp++ = (*pSrcA_temp++)&(*pSrcB_temp++); + + /* Decrement the loop counter */ + blkCnt--; + } + } + if(blkCnt = blockSize%8) + { + pSrcA = (uint8_t * )(pSrcA_temp-7); + pSrcB = (uint8_t * )(pSrcB_temp-7); + } + +#else + uint32_t * pSrcA_temp = pSrcA; + uint32_t * pSrcB_temp = pSrcB; + uint32_t * pDst_temp = pDst; + if(blkCnt = blockSize >> 2) + { + while (blkCnt > 0U) + { + *pDst_temp++ = (*pSrcA_temp++)&(*pSrcB_temp++); + + /* Decrement the loop counter */ + blkCnt--; + } + } + if(blkCnt = blockSize%4) + { + pSrcA = (uint8_t * )(pSrcA_temp-3); + pSrcB = (uint8_t * )(pSrcB_temp-3); + } +#endif /*defined (RISCV_DSP64) || (__RISCV_XLEN == 64)*/ + + while (blkCnt > 0U) + { + *pDst++ = (*pSrcA++)&(*pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } + +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of And group + */ diff --git a/components/nmsis/dsp/src/BasicMathFunctions/riscv_clip_f16.c b/components/nmsis/dsp/src/BasicMathFunctions/riscv_clip_f16.c new file mode 100644 index 00000000..6cc29d6a --- /dev/null +++ b/components/nmsis/dsp/src/BasicMathFunctions/riscv_clip_f16.c @@ -0,0 +1,77 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_clip_f16.c + * Description: Floating-point vector addition + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions_f16.h" + +/** + @ingroup groupMath + */ + + +/** + @addtogroup BasicClip + @{ + */ + +/** + @brief Elementwise floating-point clipping + @param[in] pSrc points to input values + @param[out] pDst points to output clipped values + @param[in] low lower bound + @param[in] high higher bound + @param[in] numSamples number of samples to clip + @return none + */ + + +#if defined(RISCV_FLOAT16_SUPPORTED) + +void riscv_clip_f16(const float16_t * pSrc, + float16_t * pDst, + float16_t low, + float16_t high, + uint32_t numSamples) +{ + for (uint32_t i = 0; i < numSamples; i++) + { + if (pSrc[i] > high) + pDst[i] = high; + else if (pSrc[i] < low) + pDst[i] = low; + else + pDst[i] = pSrc[i]; + } +} +#endif /* defined(RISCV_FLOAT16_SUPPORTED */ + + + +/** + @} end of BasicClip group + */ diff --git a/components/nmsis/dsp/src/BasicMathFunctions/riscv_clip_f32.c b/components/nmsis/dsp/src/BasicMathFunctions/riscv_clip_f32.c new file mode 100644 index 00000000..cc4992c5 --- /dev/null +++ b/components/nmsis/dsp/src/BasicMathFunctions/riscv_clip_f32.c @@ -0,0 +1,79 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_clip_f32.c + * Description: Floating-point vector addition + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @defgroup BasicClip Elementwise clipping + + Element-by-element clipping of a value. + + The value is constrained between 2 bounds. + + There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + @addtogroup BasicClip + @{ + */ + +/** + @brief Elementwise floating-point clipping + @param[in] pSrc points to input values + @param[out] pDst points to output clipped values + @param[in] low lower bound + @param[in] high higher bound + @param[in] numSamples number of samples to clip + @return none + */ +void riscv_clip_f32(const float32_t * pSrc, + float32_t * pDst, + float32_t low, + float32_t high, + uint32_t numSamples) +{ + for (uint32_t i = 0; i < numSamples; i++) + { + if (pSrc[i] > high) + pDst[i] = high; + else if (pSrc[i] < low) + pDst[i] = low; + else + pDst[i] = pSrc[i]; + } +} + +/** + @} end of BasicClip group + */ diff --git a/components/nmsis/dsp/src/BasicMathFunctions/riscv_clip_q15.c b/components/nmsis/dsp/src/BasicMathFunctions/riscv_clip_q15.c new file mode 100644 index 00000000..f8864053 --- /dev/null +++ b/components/nmsis/dsp/src/BasicMathFunctions/riscv_clip_q15.c @@ -0,0 +1,70 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_clip_q15.c + * Description: Floating-point vector addition + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + + +/** + @addtogroup BasicClip + @{ + */ + +/** + @brief Elementwise fixed-point clipping + @param[in] pSrc points to input values + @param[out] pDst points to output clipped values + @param[in] low lower bound + @param[in] high higher bound + @param[in] numSamples number of samples to clip + @return none + */ +void riscv_clip_q15(const q15_t * pSrc, + q15_t * pDst, + q15_t low, + q15_t high, + uint32_t numSamples) +{ + for (uint32_t i = 0; i < numSamples; i++) + { + if (pSrc[i] > high) + pDst[i] = high; + else if (pSrc[i] < low) + pDst[i] = low; + else + pDst[i] = pSrc[i]; + } +} + +/** + @} end of BasicClip group + */ diff --git a/components/nmsis/dsp/src/BasicMathFunctions/riscv_clip_q31.c b/components/nmsis/dsp/src/BasicMathFunctions/riscv_clip_q31.c new file mode 100644 index 00000000..f2829f53 --- /dev/null +++ b/components/nmsis/dsp/src/BasicMathFunctions/riscv_clip_q31.c @@ -0,0 +1,70 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_clip_q31.c + * Description: Floating-point vector addition + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + + +/** + @addtogroup BasicClip + @{ + */ + +/** + @brief Elementwise fixed-point clipping + @param[in] pSrc points to input values + @param[out] pDst points to output clipped values + @param[in] low lower bound + @param[in] high higher bound + @param[in] numSamples number of samples to clip + @return none + */ +void riscv_clip_q31(const q31_t * pSrc, + q31_t * pDst, + q31_t low, + q31_t high, + uint32_t numSamples) +{ + for (uint32_t i = 0; i < numSamples; i++) + { + if (pSrc[i] > high) + pDst[i] = high; + else if (pSrc[i] < low) + pDst[i] = low; + else + pDst[i] = pSrc[i]; + } +} + +/** + @} end of BasicClip group + */ diff --git a/components/nmsis/dsp/src/BasicMathFunctions/riscv_clip_q7.c b/components/nmsis/dsp/src/BasicMathFunctions/riscv_clip_q7.c new file mode 100644 index 00000000..15d63355 --- /dev/null +++ b/components/nmsis/dsp/src/BasicMathFunctions/riscv_clip_q7.c @@ -0,0 +1,70 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_clip_q7.c + * Description: Floating-point vector addition + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + + +/** + @addtogroup BasicClip + @{ + */ + +/** + @brief Elementwise fixed-point clipping + @param[in] pSrc points to input values + @param[out] pDst points to output clipped values + @param[in] low lower bound + @param[in] high higher bound + @param[in] numSamples number of samples to clip + @return none + */ +void riscv_clip_q7(const q7_t * pSrc, + q7_t * pDst, + q7_t low, + q7_t high, + uint32_t numSamples) +{ + for (uint32_t i = 0; i < numSamples; i++) + { + if (pSrc[i] > high) + pDst[i] = high; + else if (pSrc[i] < low) + pDst[i] = low; + else + pDst[i] = pSrc[i]; + } +} + +/** + @} end of BasicClip group + */ diff --git a/components/nmsis/dsp/src/BasicMathFunctions/riscv_dot_prod_f16.c b/components/nmsis/dsp/src/BasicMathFunctions/riscv_dot_prod_f16.c new file mode 100644 index 00000000..3e16cc31 --- /dev/null +++ b/components/nmsis/dsp/src/BasicMathFunctions/riscv_dot_prod_f16.c @@ -0,0 +1,125 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_dot_prod_f16.c + * Description: Floating-point dot product + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions_f16.h" + +/** + @ingroup groupMath + */ + +/** + @defgroup BasicDotProd Vector Dot Product + + Computes the dot product of two vectors. + The vectors are multiplied element-by-element and then summed. + + 
+      sum = pSrcA[0]*pSrcB[0] + pSrcA[1]*pSrcB[1] + ... + pSrcA[blockSize-1]*pSrcB[blockSize-1]
+
+ + There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + @addtogroup BasicDotProd + @{ + */ + +/** + @brief Dot product of floating-point vectors. + @param[in] pSrcA points to the first input vector. + @param[in] pSrcB points to the second input vector. + @param[in] blockSize number of samples in each vector. + @param[out] result output result returned here. + @return none + */ + +#if defined(RISCV_FLOAT16_SUPPORTED) +void riscv_dot_prod_f16( + const float16_t * pSrcA, + const float16_t * pSrcB, + uint32_t blockSize, + float16_t * result) +{ + uint32_t blkCnt; /* Loop counter */ + _Float16 sum = 0.0f; /* Temporary return variable */ + + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + + /* Calculate dot product and store result in a temporary buffer. */ + sum += (_Float16)(*pSrcA++) * (_Float16)(*pSrcB++); + + sum += (_Float16)(*pSrcA++) * (_Float16)(*pSrcB++); + + sum += (_Float16)(*pSrcA++) * (_Float16)(*pSrcB++); + + sum += (_Float16)(*pSrcA++) * (_Float16)(*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + + /* Calculate dot product and store result in a temporary buffer. */ + sum += (_Float16)(*pSrcA++) * (_Float16)(*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store result in destination buffer */ + *result = sum; +} +#endif +/** + @} end of BasicDotProd group + */ diff --git a/components/nmsis/dsp/src/BasicMathFunctions/riscv_dot_prod_f32.c b/components/nmsis/dsp/src/BasicMathFunctions/riscv_dot_prod_f32.c new file mode 100644 index 00000000..c85f69a5 --- /dev/null +++ b/components/nmsis/dsp/src/BasicMathFunctions/riscv_dot_prod_f32.c @@ -0,0 +1,144 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_dot_prod_f32.c + * Description: Floating-point dot product + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @defgroup BasicDotProd Vector Dot Product + + Computes the dot product of two vectors. + The vectors are multiplied element-by-element and then summed. + + 
+      sum = pSrcA[0]*pSrcB[0] + pSrcA[1]*pSrcB[1] + ... + pSrcA[blockSize-1]*pSrcB[blockSize-1]
+
+ + There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + @addtogroup BasicDotProd + @{ + */ + +/** + @brief Dot product of floating-point vectors. + @param[in] pSrcA points to the first input vector. + @param[in] pSrcB points to the second input vector. + @param[in] blockSize number of samples in each vector. + @param[out] result output result returned here. + @return none + */ + + +void riscv_dot_prod_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + uint32_t blockSize, + float32_t * result) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + size_t l; + const float32_t * inputA = pSrcA; + const float32_t * inputB = pSrcB; + vfloat32m8_t v_A, v_B; + l = vsetvl_e32m1(1); + vfloat32m1_t v_sum = vfmv_s_f_f32m1(v_sum, 0.0f, l); + for (; (l = vsetvl_e32m8(blkCnt)) > 0; blkCnt -= l) + { + v_A = vle32_v_f32m8(inputA, l); + v_B = vle32_v_f32m8(inputB, l); + inputA += l; + inputB += l; /* Point to the first complex pointer */ + v_sum = vfredsum_vs_f32m8_f32m1(v_sum, vfmul_vv_f32m8(v_A, v_B, l), v_sum, l); + } + l = vsetvl_e32m1(1); + vse32_v_f32m1(result, v_sum, l); +#else + uint32_t blkCnt; /* Loop counter */ + float32_t sum = 0.0f; /* Temporary return variable */ + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + + /* Calculate dot product and store result in a temporary buffer. */ + sum += (*pSrcA++) * (*pSrcB++); + + sum += (*pSrcA++) * (*pSrcB++); + + sum += (*pSrcA++) * (*pSrcB++); + + sum += (*pSrcA++) * (*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + + /* Calculate dot product and store result in a temporary buffer. */ + sum += (*pSrcA++) * (*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store result in destination buffer */ + *result = sum; +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of BasicDotProd group + */ diff --git a/components/nmsis/dsp/src/BasicMathFunctions/riscv_dot_prod_q15.c b/components/nmsis/dsp/src/BasicMathFunctions/riscv_dot_prod_q15.c new file mode 100644 index 00000000..95151e29 --- /dev/null +++ b/components/nmsis/dsp/src/BasicMathFunctions/riscv_dot_prod_q15.c @@ -0,0 +1,152 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_dot_prod_q15.c + * Description: Q15 dot product + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicDotProd + @{ + */ + +/** + @brief Dot product of Q15 vectors. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[in] blockSize number of samples in each vector + @param[out] result output result returned here + @return none + + @par Scaling and Overflow Behavior + The intermediate multiplications are in 1.15 x 1.15 = 2.30 format and these + results are added to a 64-bit accumulator in 34.30 format. + Nonsaturating additions are used and given that there are 33 guard bits in the accumulator + there is no risk of overflow. + The return result is in 34.30 format. + */ +void riscv_dot_prod_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + uint32_t blockSize, + q63_t * result) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + size_t l; + const q15_t * inputA = pSrcA; + const q15_t * inputB = pSrcB; + q63_t * output = result; + vint16m4_t v_inA; + vint16m4_t v_inB; + l = vsetvl_e64m1(1); + vint64m1_t v_sum = vmv_s_x_i64m1(v_sum, 0, l); + for (; (l = vsetvl_e16m4(blkCnt)) > 0; blkCnt -= l) + { + v_inA = vle16_v_i16m4(inputA, l); + v_inB = vle16_v_i16m4(inputB, l); + inputA += l; + inputB += l; + v_sum = vwredsum_vs_i32m8_i64m1(v_sum, vwmul_vv_i32m8(v_inA, v_inB, l), v_sum, l); + } + l = vsetvl_e64m1(1); + vse64_v_i64m1(output, v_sum, l); +#else + uint32_t blkCnt; /* Loop counter */ + volatile q63_t sum = 0; /* Temporary return variable */ + +#if defined (RISCV_MATH_LOOPUNROLL) +#if __RISCV_XLEN == 64 + /* Loop unrolling: Compute 8 outputs at a time */ + blkCnt = blockSize >> 3U; +#else + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; +#endif /* __RISCV_XLEN == 64 */ + while (blkCnt > 0U) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + +#if defined (RISCV_MATH_DSP) +#if __RISCV_XLEN == 64 + sum = __RV_SMALDA(sum, read_q15x4_ia ((q15_t **) &pSrcA), read_q15x4_ia ((q15_t **) &pSrcB)); + sum = __RV_SMALDA(sum, read_q15x4_ia ((q15_t **) &pSrcA), read_q15x4_ia ((q15_t **) &pSrcB)); +#else + /* Calculate dot product and store result in a temporary buffer. */ + //sum = __SMLALD(read_q15x2_ia ((q15_t **) &pSrcA), read_q15x2_ia ((q15_t **) &pSrcB), sum); + //sum = __SMLALD(read_q15x2_ia ((q15_t **) &pSrcA), read_q15x2_ia ((q15_t **) &pSrcB), sum); + sum = __RV_SMALDA(sum, read_q15x2_ia ((q15_t **) &pSrcA), read_q15x2_ia ((q15_t **) &pSrcB)); + sum = __RV_SMALDA(sum, read_q15x2_ia ((q15_t **) &pSrcA), read_q15x2_ia ((q15_t **) &pSrcB)); +#endif /* __RISCV_XLEN == 64 */ +#else + sum += (q63_t)((q31_t) *pSrcA++ * *pSrcB++); + sum += (q63_t)((q31_t) *pSrcA++ * *pSrcB++); + sum += (q63_t)((q31_t) *pSrcA++ * *pSrcB++); + sum += (q63_t)((q31_t) *pSrcA++ * *pSrcB++); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + + /* Calculate dot product and store result in a temporary buffer. */ +#if defined (RISCV_MATH_DSP) + sum = __SMLALD((*pSrcA++) & 0xffff, (*pSrcB++) & 0xffff, sum); +#else + sum += (q63_t)((q31_t) *pSrcA++ * *pSrcB++); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store result in destination buffer in 34.30 format */ + *result = sum; +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of BasicDotProd group + */ diff --git a/components/nmsis/dsp/src/BasicMathFunctions/riscv_dot_prod_q31.c b/components/nmsis/dsp/src/BasicMathFunctions/riscv_dot_prod_q31.c new file mode 100644 index 00000000..6e6a942b --- /dev/null +++ b/components/nmsis/dsp/src/BasicMathFunctions/riscv_dot_prod_q31.c @@ -0,0 +1,158 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_dot_prod_q31.c + * Description: Q31 dot product + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicDotProd + @{ + */ + +/** + @brief Dot product of Q31 vectors. + @param[in] pSrcA points to the first input vector. + @param[in] pSrcB points to the second input vector. + @param[in] blockSize number of samples in each vector. + @param[out] result output result returned here. + @return none + + @par Scaling and Overflow Behavior + The intermediate multiplications are in 1.31 x 1.31 = 2.62 format and these + are truncated to 2.48 format by discarding the lower 14 bits. + The 2.48 result is then added without saturation to a 64-bit accumulator in 16.48 format. + There are 15 guard bits in the accumulator and there is no risk of overflow as long as + the length of the vectors is less than 2^16 elements. + The return result is in 16.48 format. + */ + +void riscv_dot_prod_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + uint32_t blockSize, + q63_t * result) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + size_t l; + const q31_t * inputA = pSrcA; + const q31_t * inputB = pSrcB; + q63_t * output = result; + vint32m4_t v_inA; + vint32m4_t v_inB; + l = vsetvl_e64m1(1); + vint64m1_t v_sum = vmv_s_x_i64m1(v_sum, 0, l); + for (; (l = vsetvl_e32m4(blkCnt)) > 0; blkCnt -= l) + { + v_inA = vle32_v_i32m4(inputA, l); + v_inB = vle32_v_i32m4(inputB, l); + inputA += l; + inputB += l; + v_sum = vredsum_vs_i64m8_i64m1(v_sum, vsra_vx_i64m8(vwmul_vv_i64m8(v_inA, v_inB, l), 14, l), v_sum, l); + } + l = vsetvl_e64m1(1); + vse64_v_i64m1(output, v_sum, l); +#else + uint32_t blkCnt; /* Loop counter */ + q63_t sum = 0; /* Temporary return variable */ + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + + /* Calculate dot product and store result in a temporary buffer. */ +#if defined(RISCV_MATH_DSP) +#if __RISCV_XLEN == 64 + sum += (__RV_MULSR64(*pSrcA++, *pSrcB++) >> 14); + sum += (__RV_MULSR64(*pSrcA++, *pSrcB++) >> 14); + sum += (__RV_MULSR64(*pSrcA++, *pSrcB++) >> 14); + sum += (__RV_MULSR64(*pSrcA++, *pSrcB++) >> 14); +#else + sum += (__RV_MULSR64(*pSrcA++, *pSrcB++) >> 14); + sum += (__RV_MULSR64(*pSrcA++, *pSrcB++) >> 14); + sum += (__RV_MULSR64(*pSrcA++, *pSrcB++) >> 14); + sum += (__RV_MULSR64(*pSrcA++, *pSrcB++) >> 14); +#endif /* __RISCV_XLEN == 64 */ +#else + sum += ((q63_t) *pSrcA++ * *pSrcB++) >> 14U; + sum += ((q63_t) *pSrcA++ * *pSrcB++) >> 14U; + sum += ((q63_t) *pSrcA++ * *pSrcB++) >> 14U; + sum += ((q63_t) *pSrcA++ * *pSrcB++) >> 14U; +#endif + //sum += ((q63_t) *pSrcA++ * *pSrcB++) >> 14U; + //sum += ((q63_t) *pSrcA++ * *pSrcB++) >> 14U; + //sum += ((q63_t) *pSrcA++ * *pSrcB++) >> 14U; + //sum += ((q63_t) *pSrcA++ * *pSrcB++) >> 14U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + + /* Calculate dot product and store result in a temporary buffer. */ +#if defined(RISCV_MATH_DSP) + sum += (__MULSR64(*pSrcA++, *pSrcB++) >> 14); +#else + sum += ((q63_t) *pSrcA++ * *pSrcB++) >> 14U; +#endif + //sum += ((q63_t) *pSrcA++ * *pSrcB++) >> 14U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store result in destination buffer in 16.48 format */ + *result = sum; +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of BasicDotProd group + */ diff --git a/components/nmsis/dsp/src/BasicMathFunctions/riscv_dot_prod_q7.c b/components/nmsis/dsp/src/BasicMathFunctions/riscv_dot_prod_q7.c new file mode 100644 index 00000000..6f120387 --- /dev/null +++ b/components/nmsis/dsp/src/BasicMathFunctions/riscv_dot_prod_q7.c @@ -0,0 +1,182 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_dot_prod_q7.c + * Description: Q7 dot product + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicDotProd + @{ + */ + +/** + @brief Dot product of Q7 vectors. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[in] blockSize number of samples in each vector + @param[out] result output result returned here + @return none + + @par Scaling and Overflow Behavior + The intermediate multiplications are in 1.7 x 1.7 = 2.14 format and these + results are added to an accumulator in 18.14 format. + Nonsaturating additions are used and there is no danger of wrap around as long as + the vectors are less than 2^18 elements long. + The return result is in 18.14 format. + */ + +void riscv_dot_prod_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + uint32_t blockSize, + q31_t * result) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + size_t l; + const q7_t * inputA = pSrcA; + const q7_t * inputB = pSrcB; + q31_t * output = result; + vint8m4_t v_inA; + vint8m4_t v_inB; + l = vsetvl_e32m1(1); + vint32m1_t v_sum = vmv_s_x_i32m1(v_sum, 0, l); + for (; (l = vsetvl_e8m4(blkCnt)) > 0; blkCnt -= l) + { + v_inA = vle8_v_i8m4(inputA, l); + v_inB = vle8_v_i8m4(inputB, l); + inputA += l; + inputB += l; + v_sum = vwredsum_vs_i16m8_i32m1(v_sum, vwmul_vv_i16m8(v_inA, v_inB, l), v_sum, l); + } + l = vsetvl_e32m1(1); + vse32_v_i32m1(output, v_sum, l); +#else + uint32_t blkCnt; /* Loop counter */ + volatile q31_t sum = 0; /* Temporary return variable */ + +#if defined (RISCV_MATH_LOOPUNROLL) + +#if defined (RISCV_MATH_DSP) +#if __RISCV_XLEN == 64 + q63_t input1, input2; /* Temporary variables */ + q63_t sum64 = 0; + /* Loop unrolling: Compute 8 outputs at a time */ + blkCnt = blockSize >> 3U; +#else + q31_t input1, input2; /* Temporary variables */ + //q31_t inA1, inA2, inB1, inB2; /* Temporary variables */ + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; +#endif /* __RISCV_XLEN == 64 */ +#endif + + + while (blkCnt > 0U) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + +#if defined (RISCV_MATH_DSP) +#if __RISCV_XLEN == 64 + /* read 4 samples at a time from sourceA */ + input1 = read_q7x8_ia ((q7_t **) &pSrcA); + /* read 4 samples at a time from sourceB */ + input2 = read_q7x8_ia ((q7_t **) &pSrcB); + sum64 = __RV_SMAQA(sum64, input1, input2); +#else + /* read 4 samples at a time from sourceA */ + input1 = read_q7x4_ia ((q7_t **) &pSrcA); + /* read 4 samples at a time from sourceB */ + input2 = read_q7x4_ia ((q7_t **) &pSrcB); + + ///* extract two q7_t samples to q15_t samples */ + //inA1 = __SXTB16(__ROR(input1, 8)); + ///* extract reminaing two samples */ + //inA2 = __SXTB16(input1); + ///* extract two q7_t samples to q15_t samples */ + //inB1 = __SXTB16(__ROR(input2, 8)); + ///* extract reminaing two samples */ + //inB2 = __SXTB16(input2); + + ///* multiply and accumulate two samples at a time */ + //sum = __SMLAD(inA1, inB1, sum); + //sum = __SMLAD(inA2, inB2, sum); + sum = __RV_SMAQA(sum, input1, input2); +#endif /* __RISCV_XLEN == 64 */ +#else + sum += (q31_t) ((q15_t) *pSrcA++ * *pSrcB++); + sum += (q31_t) ((q15_t) *pSrcA++ * *pSrcB++); + sum += (q31_t) ((q15_t) *pSrcA++ * *pSrcB++); + sum += (q31_t) ((q15_t) *pSrcA++ * *pSrcB++); +#endif + + /* Decrement loop counter */ + blkCnt--; + } +#if __RISCV_XLEN == 64 + sum +=((sum64 + (sum64<<32u))>>32u); + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x8U; +#else + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; +#endif /* __RISCV_XLEN == 64 */ +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + + /* Calculate dot product and store result in a temporary buffer. */ +#if defined (RISCV_MATH_DSP) + sum = __SMLAD((*pSrcA++) & 0xffff, (*pSrcB++) & 0xffff, sum); +#else + sum += (q31_t) ((q15_t) *pSrcA++ * *pSrcB++); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store result in destination buffer in 18.14 format */ + *result = sum; +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of BasicDotProd group + */ diff --git a/components/nmsis/dsp/src/BasicMathFunctions/riscv_mult_f16.c b/components/nmsis/dsp/src/BasicMathFunctions/riscv_mult_f16.c new file mode 100644 index 00000000..a8f0aade --- /dev/null +++ b/components/nmsis/dsp/src/BasicMathFunctions/riscv_mult_f16.c @@ -0,0 +1,120 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_mult_f16.c + * Description: Floating-point vector multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions_f16.h" + +/** + @ingroup groupMath + */ + +/** + @defgroup BasicMult Vector Multiplication + + Element-by-element multiplication of two vectors. + + 
+      pDst[n] = pSrcA[n] * pSrcB[n],   0 <= n < blockSize.
+
+ + There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + @addtogroup BasicMult + @{ + */ + +/** + @brief Floating-point vector multiplication. + @param[in] pSrcA points to the first input vector. + @param[in] pSrcB points to the second input vector. + @param[out] pDst points to the output vector. + @param[in] blockSize number of samples in each vector. + @return none + */ + + +#if defined(RISCV_FLOAT16_SUPPORTED) +void riscv_mult_f16( + const float16_t * pSrcA, + const float16_t * pSrcB, + float16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A * B */ + + /* Multiply inputs and store result in destination buffer. */ + *pDst++ = (*pSrcA++) * (*pSrcB++); + + *pDst++ = (*pSrcA++) * (*pSrcB++); + + *pDst++ = (*pSrcA++) * (*pSrcB++); + + *pDst++ = (*pSrcA++) * (*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A * B */ + + /* Multiply input and store result in destination buffer. */ + *pDst++ = (*pSrcA++) * (*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif + +/** + @} end of BasicMult group + */ diff --git a/components/nmsis/dsp/src/BasicMathFunctions/riscv_mult_f32.c b/components/nmsis/dsp/src/BasicMathFunctions/riscv_mult_f32.c new file mode 100644 index 00000000..38649b8e --- /dev/null +++ b/components/nmsis/dsp/src/BasicMathFunctions/riscv_mult_f32.c @@ -0,0 +1,131 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_mult_f32.c + * Description: Floating-point vector multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @defgroup BasicMult Vector Multiplication + + Element-by-element multiplication of two vectors. + + 
+      pDst[n] = pSrcA[n] * pSrcB[n],   0 <= n < blockSize.
+
+ + There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + @addtogroup BasicMult + @{ + */ + +/** + @brief Floating-point vector multiplication. + @param[in] pSrcA points to the first input vector. + @param[in] pSrcB points to the second input vector. + @param[out] pDst points to the output vector. + @param[in] blockSize number of samples in each vector. + @return none + */ + +void riscv_mult_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + size_t l; + vfloat32m8_t vx, vy; + + for (; (l = vsetvl_e32m8(blkCnt)) > 0; blkCnt -= l) { + vx = vle32_v_f32m8(pSrcA, l); + pSrcA += l; + vy = vle32_v_f32m8(pSrcB, l); + vse32_v_f32m8 (pDst, vfmul_vv_f32m8(vx, vy, l), l); + pSrcB += l; + pDst += l; + } +#else + uint32_t blkCnt; /* Loop counter */ + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A * B */ + + /* Multiply inputs and store result in destination buffer. */ + *pDst++ = (*pSrcA++) * (*pSrcB++); + + *pDst++ = (*pSrcA++) * (*pSrcB++); + + *pDst++ = (*pSrcA++) * (*pSrcB++); + + *pDst++ = (*pSrcA++) * (*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A * B */ + + /* Multiply input and store result in destination buffer. */ + *pDst++ = (*pSrcA++) * (*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of BasicMult group + */ diff --git a/components/nmsis/dsp/src/BasicMathFunctions/riscv_mult_q15.c b/components/nmsis/dsp/src/BasicMathFunctions/riscv_mult_q15.c new file mode 100644 index 00000000..70cf1af4 --- /dev/null +++ b/components/nmsis/dsp/src/BasicMathFunctions/riscv_mult_q15.c @@ -0,0 +1,165 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_mult_q15.c + * Description: Q15 vector multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicMult + @{ + */ + +/** + @brief Q15 vector multiplication + @param[in] pSrcA points to first input vector + @param[in] pSrcB points to second input vector + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q15 range [0x8000 0x7FFF] are saturated. + */ +void riscv_mult_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + size_t l; + vint16m8_t vx, vy; + + for (; (l = vsetvl_e16m8(blkCnt)) > 0; blkCnt -= l) { + vx = vle16_v_i16m8(pSrcA, l); + pSrcA += l; + vy = vle16_v_i16m8(pSrcB, l); + vse16_v_i16m8 (pDst, vsmul_vv_i16m8(vx, vy, l), l); + pSrcB += l; + pDst += l; + } +#else + uint32_t blkCnt; /* Loop counter */ + +#if defined (RISCV_MATH_LOOPUNROLL) + +// #if defined (RISCV_MATH_DSP) +// q31_t inA1, inA2, inB1, inB2; /* Temporary input variables */ +// q15_t out1, out2, out3, out4; /* Temporary output variables */ +// q31_t mul1, mul2, mul3, mul4; /* Temporary variables */ +// q63_t opa, opb; +// #endif + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A * B */ + +#if defined (RISCV_MATH_DSP) + /* read 2 samples at a time from sourceA */ + //inA1 = read_q15x2_ia ((q15_t **) &pSrcA); + ///* read 2 samples at a time from sourceB */ + //inB1 = read_q15x2_ia ((q15_t **) &pSrcB); + ///* read 2 samples at a time from sourceA */ + //inA2 = read_q15x2_ia ((q15_t **) &pSrcA); + ///* read 2 samples at a time from sourceB */ + //inB2 = read_q15x2_ia ((q15_t **) &pSrcB); + + ///* multiply mul = sourceA * sourceB */ + //mul1 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1 >> 16)); + //mul2 = (q31_t) ((q15_t) (inA1 ) * (q15_t) (inB1 )); + //mul3 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) (inB2 >> 16)); + //mul4 = (q31_t) ((q15_t) (inA2 ) * (q15_t) (inB2 )); + + ///* saturate result to 16 bit */ + //out1 = (q15_t) __SSAT(mul1 >> 15, 16); + //out2 = (q15_t) __SSAT(mul2 >> 15, 16); + //out3 = (q15_t) __SSAT(mul3 >> 15, 16); + //out4 = (q15_t) __SSAT(mul4 >> 15, 16); + + ///* store result to destination */ + //write_q15x2_ia (&pDst, __PKHBT(out2, out1, 16)); + //write_q15x2_ia (&pDst, __PKHBT(out4, out3, 16)); + + //write_q15x2_ia (&pDst, __KHM16(inA1, inB1)); + //write_q15x2_ia (&pDst, __KHM16(inA2, inB2)); +#if __RISCV_XLEN == 64 + write_q15x4_ia(&pDst, __RV_KHM16(read_q15x4_ia((q15_t **)& pSrcA), read_q15x4_ia((q15_t**)&pSrcB))); +#else +#ifdef RISCV_DSP64 + write_q15x4_ia(&pDst, __RV_DKHM16(read_q15x4_ia((q15_t **)& pSrcA), read_q15x4_ia((q15_t**)&pSrcB))); +#else + write_q15x2_ia(&pDst, __RV_KHM16(read_q15x2_ia((q15_t **)& pSrcA), read_q15x2_ia((q15_t**)&pSrcB))); + write_q15x2_ia(&pDst, __RV_KHM16(read_q15x2_ia((q15_t **)& pSrcA), read_q15x2_ia((q15_t**)&pSrcB))); +#endif +#endif /* __RISCV_XLEN == 64 */ +#else + *pDst++ = (q15_t) __SSAT((((q31_t) (*pSrcA++) * (*pSrcB++)) >> 15), 16); + *pDst++ = (q15_t) __SSAT((((q31_t) (*pSrcA++) * (*pSrcB++)) >> 15), 16); + *pDst++ = (q15_t) __SSAT((((q31_t) (*pSrcA++) * (*pSrcB++)) >> 15), 16); + *pDst++ = (q15_t) __SSAT((((q31_t) (*pSrcA++) * (*pSrcB++)) >> 15), 16); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A * B */ + + /* Multiply inputs and store result in destination buffer. */ + *pDst++ = (q15_t) __SSAT((((q31_t) (*pSrcA++) * (*pSrcB++)) >> 15), 16); + + /* Decrement loop counter */ + blkCnt--; + } +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of BasicMult group + */ diff --git a/components/nmsis/dsp/src/BasicMathFunctions/riscv_mult_q31.c b/components/nmsis/dsp/src/BasicMathFunctions/riscv_mult_q31.c new file mode 100644 index 00000000..d4528909 --- /dev/null +++ b/components/nmsis/dsp/src/BasicMathFunctions/riscv_mult_q31.c @@ -0,0 +1,155 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_mult_q31.c + * Description: Q31 vector multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicMult + @{ + */ + +/** + @brief Q31 vector multiplication. + @param[in] pSrcA points to the first input vector. + @param[in] pSrcB points to the second input vector. + @param[out] pDst points to the output vector. + @param[in] blockSize number of samples in each vector. + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] are saturated. + */ +void riscv_mult_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + size_t l; + vint32m8_t vx, vy; + + for (; (l = vsetvl_e32m8(blkCnt)) > 0; blkCnt -= l) { + vx = vle32_v_i32m8(pSrcA, l); + pSrcA += l; + vy = vle32_v_i32m8(pSrcB, l); + vse32_v_i32m8 (pDst, vsmul_vv_i32m8(vx, vy, l), l); + pSrcB += l; + pDst += l; + } +#else + uint32_t blkCnt; /* Loop counter */ +#if __RISCV_XLEN == 64 + q63_t temp; /* Temporary output variable */ +#endif + q31_t out; /* Temporary output variable */ + + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A * B */ +#if __RISCV_XLEN == 64 + + temp = __RV_SMMUL(read_q31x2_ia((q31_t **) &pSrcA), read_q31x2_ia((q31_t **) &pSrcB)); + out = __SSAT(temp, 31); + *pDst++ = out << 1U; + + // out = __RV_SMMUL(*pSrcA++, *pSrcB++); + out = __SSAT(temp>>32, 31); + *pDst++ = out << 1U; + + temp = __RV_SMMUL(read_q31x2_ia((q31_t **) &pSrcA), read_q31x2_ia((q31_t **) &pSrcB)); + out = __SSAT(temp, 31); + *pDst++ = out << 1U; + + // out = __RV_SMMUL(*pSrcA++, *pSrcB++); + out = __SSAT(temp>>32, 31); + *pDst++ = out << 1U; +#else + /* Multiply inputs and store result in destination buffer. */ + out = __RV_SMMUL(*pSrcA++, *pSrcB++); + out = __SSAT(out, 31); + *pDst++ = out << 1U; + + out = __RV_SMMUL(*pSrcA++, *pSrcB++); + out = __SSAT(out, 31); + *pDst++ = out << 1U; + + out = __RV_SMMUL(*pSrcA++, *pSrcB++); + out = __SSAT(out, 31); + *pDst++ = out << 1U; + + out = __RV_SMMUL(*pSrcA++, *pSrcB++); + out = __SSAT(out, 31); + *pDst++ = out << 1U; + +#endif /* __RISCV_XLEN == 64 */ + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A * B */ + + /* Multiply inputs and store result in destination buffer. */ + out = ((q63_t) *pSrcA++ * *pSrcB++) >> 32; + out = __SSAT(out, 31); + *pDst++ = out << 1U; + + /* Decrement loop counter */ + blkCnt--; + } +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of BasicMult group + */ diff --git a/components/nmsis/dsp/src/BasicMathFunctions/riscv_mult_q7.c b/components/nmsis/dsp/src/BasicMathFunctions/riscv_mult_q7.c new file mode 100644 index 00000000..2607f15d --- /dev/null +++ b/components/nmsis/dsp/src/BasicMathFunctions/riscv_mult_q7.c @@ -0,0 +1,159 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_mult_q7.c + * Description: Q7 vector multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicMult + @{ + */ + +/** + @brief Q7 vector multiplication + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q7 range [0x80 0x7F] are saturated. + */ +void riscv_mult_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + size_t l; + vint8m8_t vx, vy; + + for (; (l = vsetvl_e8m8(blkCnt)) > 0; blkCnt -= l) { + vx = vle8_v_i8m8(pSrcA, l); + pSrcA += l; + vy = vle8_v_i8m8(pSrcB, l); + vse8_v_i8m8 (pDst, vsmul_vv_i8m8(vx, vy, l), l); + pSrcB += l; + pDst += l; + } +#else + uint32_t blkCnt; /* Loop counter */ + +#if defined (RISCV_MATH_LOOPUNROLL) + +#if defined (RISCV_MATH_DSP) + q7_t out1, out2, out3, out4; /* Temporary output variables */ +#endif + + +#if defined (RISCV_DSP64) || (__RISCV_XLEN == 64) + /* Loop unrolling: Compute 8 outputs at a time */ + blkCnt = blockSize >> 3U; +#else + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; +#endif /* defined (RISCV_DSP64) || (__RISCV_XLEN == 64) */ + + while (blkCnt > 0U) + { + /* C = A * B */ + +#if defined (RISCV_MATH_DSP) + /* Multiply inputs and store results in temporary variables */ + //out1 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8); + //out2 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8); + //out3 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8); + //out4 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8); + + ///* Pack and store result in destination buffer (in single write) */ + //write_q7x4_ia (&pDst, __PACKq7(out1, out2, out3, out4)); + //write_q7x4_ia (&pDst, __KHM8 (read_q7x4_ia ((q7_t **) &pSrcA), read_q7x4_ia ((q7_t **) &pSrcB))); +#if __RISCV_XLEN == 64 + write_q7x8_ia (&pDst, __RV_KHM8 (read_q7x8_ia ((q7_t **) &pSrcA), read_q7x8_ia ((q7_t **) &pSrcB))); +#else +#ifdef RISCV_DSP64 + write_q7x8_ia (&pDst, __RV_DKHM8 (read_q7x8_ia ((q7_t **) &pSrcA), read_q7x8_ia ((q7_t **) &pSrcB))); +#else + write_q7x4_ia (&pDst, __RV_KHM8 (read_q7x4_ia ((q7_t **) &pSrcA), read_q7x4_ia ((q7_t **) &pSrcB))); +#endif +#endif /* __RISCV_XLEN == 64 */ +#else + *pDst++ = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8); + *pDst++ = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8); + *pDst++ = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8); + *pDst++ = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8); +#if defined (RISCV_DSP64) || (__RISCV_XLEN == 64) + *pDst++ = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8); + *pDst++ = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8); + *pDst++ = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8); + *pDst++ = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8); +#endif +#endif + + /* Decrement loop counter */ + blkCnt--; + } + +#if defined (RISCV_DSP64) || (__RISCV_XLEN == 64) + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x8U; +#else + blkCnt = blockSize % 0x4U; +#endif + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A * B */ + + /* Multiply input and store result in destination buffer. */ + *pDst++ = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8); + + /* Decrement loop counter */ + blkCnt--; + } +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of BasicMult group + */ diff --git a/components/nmsis/dsp/src/BasicMathFunctions/riscv_negate_f16.c b/components/nmsis/dsp/src/BasicMathFunctions/riscv_negate_f16.c new file mode 100644 index 00000000..a5b2d1af --- /dev/null +++ b/components/nmsis/dsp/src/BasicMathFunctions/riscv_negate_f16.c @@ -0,0 +1,120 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_negate_f16.c + * Description: Negates floating-point vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions_f16.h" + +/** + @ingroup groupMath + */ + +/** + @defgroup BasicNegate Vector Negate + + Negates the elements of a vector. + + 
+      pDst[n] = -pSrc[n],   0 <= n < blockSize.
+
+ + The functions support in-place computation allowing the source and + destination pointers to reference the same memory buffer. + There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + @addtogroup BasicNegate + @{ + */ + +/** + @brief Negates the elements of a floating-point vector. + @param[in] pSrc points to input vector. + @param[out] pDst points to output vector. + @param[in] blockSize number of samples in each vector. + @return none + */ + +#if defined(RISCV_FLOAT16_SUPPORTED) +void riscv_negate_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = -A */ + + /* Negate and store result in destination buffer. */ + *pDst++ = -*pSrc++; + + *pDst++ = -*pSrc++; + + *pDst++ = -*pSrc++; + + *pDst++ = -*pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = -A */ + + /* Negate and store result in destination buffer. */ + *pDst++ = -*pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif + +/** + @} end of BasicNegate group + */ diff --git a/components/nmsis/dsp/src/BasicMathFunctions/riscv_negate_f32.c b/components/nmsis/dsp/src/BasicMathFunctions/riscv_negate_f32.c new file mode 100644 index 00000000..17632d77 --- /dev/null +++ b/components/nmsis/dsp/src/BasicMathFunctions/riscv_negate_f32.c @@ -0,0 +1,129 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_negate_f32.c + * Description: Negates floating-point vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @defgroup BasicNegate Vector Negate + + Negates the elements of a vector. + + 
+      pDst[n] = -pSrc[n],   0 <= n < blockSize.
+
+ + The functions support in-place computation allowing the source and + destination pointers to reference the same memory buffer. + There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + @addtogroup BasicNegate + @{ + */ + +/** + @brief Negates the elements of a floating-point vector. + @param[in] pSrc points to input vector. + @param[out] pDst points to output vector. + @param[in] blockSize number of samples in each vector. + @return none + */ + +void riscv_negate_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + size_t l; + vfloat32m8_t vx; + + for (; (l = vsetvl_e32m8(blkCnt)) > 0; blkCnt -= l) { + vx = vle32_v_f32m8(pSrc, l); + pSrc += l; + vse32_v_f32m8 (pDst, vfmul_vf_f32m8(vx, -1, l), l); + pDst += l; + } +#else + uint32_t blkCnt; /* Loop counter */ + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = -A */ + + /* Negate and store result in destination buffer. */ + *pDst++ = -*pSrc++; + + *pDst++ = -*pSrc++; + + *pDst++ = -*pSrc++; + + *pDst++ = -*pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = -A */ + + /* Negate and store result in destination buffer. */ + *pDst++ = -*pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of BasicNegate group + */ diff --git a/components/nmsis/dsp/src/BasicMathFunctions/riscv_negate_q15.c b/components/nmsis/dsp/src/BasicMathFunctions/riscv_negate_q15.c new file mode 100644 index 00000000..2809f77b --- /dev/null +++ b/components/nmsis/dsp/src/BasicMathFunctions/riscv_negate_q15.c @@ -0,0 +1,148 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_negate_q15.c + * Description: Negates Q15 vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicNegate + @{ + */ + +/** + @brief Negates the elements of a Q15 vector. + @param[in] pSrc points to the input vector. + @param[out] pDst points to the output vector. + @param[in] blockSize number of samples in each vector. + @return none + + @par Conditions for optimum performance + Input and output buffers should be aligned by 32-bit + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + The Q15 value -1 (0x8000) is saturated to the maximum allowable positive value 0x7FFF. + */ +void riscv_negate_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + size_t l = vsetvl_e16m8(blkCnt); + vint16m8_t vx, vy = vmv_s_x_i16m8(vy, 0, l); + + for (; (l = vsetvl_e16m8(blkCnt)) > 0; blkCnt -= l) { + vx = vle16_v_i16m8(pSrc, l); + pSrc += l; + vse16_v_i16m8 (pDst, vssub_vv_i16m8(vy ,vx, l), l); + pDst += l; + } +#else + uint32_t blkCnt; /* Loop counter */ + q15_t in; /* Temporary input variable */ + +#if defined (RISCV_MATH_LOOPUNROLL) + +#if defined (RISCV_MATH_DSP) + q31_t in1; /* Temporary input variables */ +#endif + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = -A */ + +#if defined (RISCV_MATH_DSP) + /* Negate and store result in destination buffer (2 samples at a time). */ + //in1 = read_q15x2_ia ((q15_t **) &pSrc); + //write_q15x2_ia (&pDst, __QSUB16(0, in1)); + + //in1 = read_q15x2_ia ((q15_t **) &pSrc); + //write_q15x2_ia (&pDst, __QSUB16(0, in1)); +#if __RISCV_XLEN == 64 + write_q15x4_ia(&pDst, __RV_KSUB16(0, read_q15x4_ia((q15_t **)&pSrc))); +#else +#ifdef RISCV_DSP64 + write_q15x4_ia(&pDst, __DKSUB16(0, read_q15x4_ia((q15_t **)&pSrc))); +#else + write_q15x2_ia(&pDst, __RV_KSUB16(0, read_q15x2_ia((q15_t **)&pSrc))); + write_q15x2_ia(&pDst, __RV_KSUB16(0, read_q15x2_ia((q15_t **)&pSrc))); +#endif +#endif /* __RISCV_XLEN == 64 */ +#else + in = *pSrc++; + *pDst++ = (in == (q15_t) 0x8000) ? (q15_t) 0x7fff : -in; + + in = *pSrc++; + *pDst++ = (in == (q15_t) 0x8000) ? (q15_t) 0x7fff : -in; + + in = *pSrc++; + *pDst++ = (in == (q15_t) 0x8000) ? (q15_t) 0x7fff : -in; + + in = *pSrc++; + *pDst++ = (in == (q15_t) 0x8000) ? (q15_t) 0x7fff : -in; +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = -A */ + + /* Negate and store result in destination buffer. */ + in = *pSrc++; + *pDst++ = (in == (q15_t) 0x8000) ? (q15_t) 0x7fff : -in; + + /* Decrement loop counter */ + blkCnt--; + } +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of BasicNegate group + */ diff --git a/components/nmsis/dsp/src/BasicMathFunctions/riscv_negate_q31.c b/components/nmsis/dsp/src/BasicMathFunctions/riscv_negate_q31.c new file mode 100644 index 00000000..f7bf7791 --- /dev/null +++ b/components/nmsis/dsp/src/BasicMathFunctions/riscv_negate_q31.c @@ -0,0 +1,148 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_negate_q31.c + * Description: Negates Q31 vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicNegate + @{ + */ + +/** + @brief Negates the elements of a Q31 vector. + @param[in] pSrc points to the input vector. + @param[out] pDst points to the output vector. + @param[in] blockSize number of samples in each vector. + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + The Q31 value -1 (0x80000000) is saturated to the maximum allowable positive value 0x7FFFFFFF. + */ + +void riscv_negate_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + size_t l = vsetvl_e32m8(blkCnt); + vint32m8_t vx, vy = vmv_s_x_i32m8(vy, 0, l); + + for (; (l = vsetvl_e32m8(blkCnt)) > 0; blkCnt -= l) { + vx = vle32_v_i32m8(pSrc, l); + pSrc += l; + vse32_v_i32m8 (pDst, vssub_vv_i32m8(vy ,vx, l), l); + pDst += l; + } +#else + uint32_t blkCnt; /* Loop counter */ + q31_t in; /* Temporary input variable */ + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = -A */ +#if __RISCV_XLEN == 64 + write_q15x4_ia(&pDst, __RV_KSUB32(0, read_q15x4_ia((q31_t **)&pSrc))); + write_q15x4_ia(&pDst, __RV_KSUB32(0, read_q15x4_ia((q31_t **)&pSrc))); +#else + /* Negate and store result in destination buffer. */ + in = *pSrc++; +#if defined (RISCV_MATH_DSP) + *pDst++ = __QSUB(0, in); +#else + *pDst++ = (in == INT32_MIN) ? INT32_MAX : -in; +#endif + + in = *pSrc++; +#if defined (RISCV_MATH_DSP) + *pDst++ = __QSUB(0, in); +#else + *pDst++ = (in == INT32_MIN) ? INT32_MAX : -in; +#endif + + in = *pSrc++; +#if defined (RISCV_MATH_DSP) + *pDst++ = __QSUB(0, in); +#else + *pDst++ = (in == INT32_MIN) ? INT32_MAX : -in; +#endif + + in = *pSrc++; +#if defined (RISCV_MATH_DSP) + *pDst++ = __QSUB(0, in); +#else + *pDst++ = (in == INT32_MIN) ? INT32_MAX : -in; +#endif +#endif /* __RISCV_XLEN == 64 */ + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = -A */ + + /* Negate and store result in destination buffer. */ + in = *pSrc++; +#if defined (RISCV_MATH_DSP) + *pDst++ = __QSUB(0, in); +#else + *pDst++ = (in == INT32_MIN) ? INT32_MAX : -in; +#endif + + /* Decrement loop counter */ + blkCnt--; + } +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of BasicNegate group + */ diff --git a/components/nmsis/dsp/src/BasicMathFunctions/riscv_negate_q7.c b/components/nmsis/dsp/src/BasicMathFunctions/riscv_negate_q7.c new file mode 100644 index 00000000..a441c106 --- /dev/null +++ b/components/nmsis/dsp/src/BasicMathFunctions/riscv_negate_q7.c @@ -0,0 +1,179 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_negate_q7.c + * Description: Negates Q7 vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicNegate + @{ + */ + +/** + @brief Negates the elements of a Q7 vector. + @param[in] pSrc points to the input vector. + @param[out] pDst points to the output vector. + @param[in] blockSize number of samples in each vector. + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + The Q7 value -1 (0x80) is saturated to the maximum allowable positive value 0x7F. + */ +void riscv_negate_q7( + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + size_t l; + l = vsetvl_e8m8(blkCnt); + vint8m8_t vx,vy = vmv_s_x_i8m8(vy, 0, l); + + for (; (l = vsetvl_e8m8(blkCnt)) > 0; blkCnt -= l) { + vx = vle8_v_i8m8(pSrc, l); + pSrc += l; + vse8_v_i8m8 (pDst, vssub_vv_i8m8(vy ,vx, l), l); + pDst += l; + } +#else + uint32_t blkCnt; /* Loop counter */ + q7_t in; /* Temporary input variable */ + +#if defined (RISCV_MATH_LOOPUNROLL) + +#if defined (RISCV_MATH_DSP) +#ifdef RISCV_DSP64 + q63_t in1; /* Temporary input variable */ +#else + q31_t in1; +#endif +#endif // RISCV_MATH_DSP + +#if defined (RISCV_DSP64) || (__RISCV_XLEN == 64) + /* Loop unrolling: Compute 8 outputs at a time */ + blkCnt = blockSize >> 3U; +#else + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; +#endif // RISCV_DSP64 + + while (blkCnt > 0U) + { + /* C = -A */ + +#if defined (RISCV_MATH_DSP) + /* Negate and store result in destination buffer (4 samples at a time). */ +#if __RISCV_XLEN == 64 + in1 = read_q7x8_ia ((q7_t **) &pSrc); + write_q7x8_ia (&pDst, __RV_KSUB8(0, in1)); +#else +#ifdef RISCV_DSP64 + in1 = read_q7x8_ia ((q7_t **) &pSrc); + write_q7x8_ia (&pDst, __DQSUB8(0, in1)); +#else + in1 = read_q7x4_ia ((q7_t **) &pSrc); + write_q7x4_ia (&pDst, __RV_KSUB8(0, in1)); + +#endif +#endif /* __RISCV_XLEN == 64 */ +#else + in = *pSrc++; + *pDst++ = (in == (q7_t) 0x80) ? (q7_t) 0x7f : -in; + + in = *pSrc++; + *pDst++ = (in == (q7_t) 0x80) ? (q7_t) 0x7f : -in; + + in = *pSrc++; + *pDst++ = (in == (q7_t) 0x80) ? (q7_t) 0x7f : -in; + + in = *pSrc++; + *pDst++ = (in == (q7_t) 0x80) ? (q7_t) 0x7f : -in; + +#if defined (RISCV_DSP64) || (__RISCV_XLEN == 64) + in = *pSrc++; + *pDst++ = (in == (q7_t) 0x80) ? (q7_t) 0x7f : -in; + + in = *pSrc++; + *pDst++ = (in == (q7_t) 0x80) ? (q7_t) 0x7f : -in; + + in = *pSrc++; + *pDst++ = (in == (q7_t) 0x80) ? (q7_t) 0x7f : -in; + + in = *pSrc++; + *pDst++ = (in == (q7_t) 0x80) ? (q7_t) 0x7f : -in; +#endif // RISCV_DSP64 + +#endif + + /* Decrement loop counter */ + blkCnt--; + } + +#if defined (RISCV_DSP64) || (__RISCV_XLEN == 64) + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x8U; +#else + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; +#endif + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = -A */ + + /* Negate and store result in destination buffer. */ + in = *pSrc++; + +#if defined (RISCV_MATH_DSP) + *pDst++ = (q7_t) __QSUB8(0, in); +#else + *pDst++ = (in == (q7_t) 0x80) ? (q7_t) 0x7f : -in; +#endif + + /* Decrement loop counter */ + blkCnt--; + } +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of BasicNegate group + */ diff --git a/components/nmsis/dsp/src/BasicMathFunctions/riscv_not_u16.c b/components/nmsis/dsp/src/BasicMathFunctions/riscv_not_u16.c new file mode 100644 index 00000000..532c6a46 --- /dev/null +++ b/components/nmsis/dsp/src/BasicMathFunctions/riscv_not_u16.c @@ -0,0 +1,126 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_not_u16.c + * Description: uint16_t bitwise NOT + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @defgroup Not Vector bitwise NOT + + Compute the logical bitwise NOT. + + There are separate functions for uint32_t, uint16_t, and uint8_t data types. + */ + +/** + @addtogroup Not + @{ + */ + +/** + @brief Compute the logical bitwise NOT of a fixed-point vector. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +void riscv_not_u16( + const uint16_t * pSrc, + uint16_t * pDst, + uint32_t blockSize) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + size_t l; + vuint16m8_t vx; + + for (; (l = vsetvl_e16m8(blkCnt)) > 0; blkCnt -= l) { + vx = vle16_v_u16m8(pSrc, l); + pSrc += l; + vse16_v_u16m8(pDst,vnot_v_u16m8(vx, l), l); + pDst += l; + } +#else + uint32_t blkCnt; /* Loop counter */ + +#if defined (RISCV_DSP64) || (__RISCV_XLEN == 64) + + uint64_t * pSrc_temp = pSrc; + uint64_t * pDst_temp = pDst; + if(blkCnt = blockSize >> 2) + { + while (blkCnt > 0U) + { + *pDst_temp++ = ~(*pSrc_temp++); + + /* Decrement the loop counter */ + blkCnt--; + } + } + if(blkCnt = blockSize%4) + { + pSrc = (uint8_t * )(pSrc_temp-3); + } + +#else + uint32_t * pSrc_temp = pSrc; + uint32_t * pDst_temp = pDst; + if(blkCnt = blockSize >> 1) + { + while (blkCnt > 0U) + { + *pDst_temp++ = ~(*pSrc_temp++); + + /* Decrement the loop counter */ + blkCnt--; + } + } + if(blkCnt = blockSize%2) + { + pSrc = (uint8_t * )(pSrc_temp-1); + } +#endif + + while (blkCnt > 0U) + { + *pDst++ = ~(*pSrc++); + + /* Decrement the loop counter */ + blkCnt--; + } +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of Not group + */ diff --git a/components/nmsis/dsp/src/BasicMathFunctions/riscv_not_u32.c b/components/nmsis/dsp/src/BasicMathFunctions/riscv_not_u32.c new file mode 100644 index 00000000..944c4911 --- /dev/null +++ b/components/nmsis/dsp/src/BasicMathFunctions/riscv_not_u32.c @@ -0,0 +1,102 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_not_u32.c + * Description: uint32_t bitwise NOT + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup Not + @{ + */ + +/** + @brief Compute the logical bitwise NOT of a fixed-point vector. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +void riscv_not_u32( + const uint32_t * pSrc, + uint32_t * pDst, + uint32_t blockSize) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + size_t l; + vuint32m8_t vx; + + for (; (l = vsetvl_e32m8(blkCnt)) > 0; blkCnt -= l) { + vx = vle32_v_u32m8(pSrc, l); + pSrc += l; + vse32_v_u32m8(pDst,vnot_v_u32m8(vx, l), l); + pDst += l; + } +#else + uint32_t blkCnt; /* Loop counter */ + +#if defined (RISCV_DSP64) || (__RISCV_XLEN == 64) + + uint64_t * pSrc_temp = pSrc; + uint64_t * pDst_temp = pDst; + if(blkCnt = blockSize >> 1) + { + while (blkCnt > 0U) + { + *pDst_temp++ = ~(*pSrc_temp++); + + /* Decrement the loop counter */ + blkCnt--; + } + } + if(blkCnt = blockSize%2) + { + pSrc = (uint8_t * )(pSrc_temp-1); + } +#else + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; +#endif + while (blkCnt > 0U) + { + *pDst++ = ~(*pSrc++); + + /* Decrement the loop counter */ + blkCnt--; + } +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of Not group + */ diff --git a/components/nmsis/dsp/src/BasicMathFunctions/riscv_not_u8.c b/components/nmsis/dsp/src/BasicMathFunctions/riscv_not_u8.c new file mode 100644 index 00000000..44b79c6e --- /dev/null +++ b/components/nmsis/dsp/src/BasicMathFunctions/riscv_not_u8.c @@ -0,0 +1,118 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_not_u8.c + * Description: uint8_t bitwise NOT + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup Not + @{ + */ + +/** + @brief Compute the logical bitwise NOT of a fixed-point vector. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +void riscv_not_u8( + const uint8_t * pSrc, + uint8_t * pDst, + uint32_t blockSize) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + size_t l; + vuint8m8_t vx; + + for (; (l = vsetvl_e8m8(blkCnt)) > 0; blkCnt -= l) { + vx = vle8_v_u8m8(pSrc, l); + pSrc += l; + vse8_v_u8m8(pDst,vnot_v_u8m8(vx, l), l); + pDst += l; + } +#else + uint32_t blkCnt; /* Loop counter */ + +#if defined (RISCV_DSP64) || (__RISCV_XLEN == 64) + + uint64_t * pSrc_temp = pSrc; + uint64_t * pDst_temp = pDst; + if(blkCnt = blockSize >> 3) + { + while (blkCnt > 0U) + { + *pDst_temp++ = ~(*pSrc_temp++); + + /* Decrement the loop counter */ + blkCnt--; + } + } + if(blkCnt = blockSize%8) + { + pSrc = (uint8_t * )(pSrc_temp-7); + } + +#else + uint32_t * pSrc_temp = pSrc; + uint32_t * pDst_temp = pDst; + if(blkCnt = blockSize >> 2) + { + while (blkCnt > 0U) + { + *pDst_temp++ = ~(*pSrc_temp++); + + /* Decrement the loop counter */ + blkCnt--; + } + } + if(blkCnt = blockSize%4) + { + pSrc = (uint8_t * )(pSrc_temp-3); + } +#endif /*defined (RISCV_DSP64) || (__RISCV_XLEN == 64)*/ + + while (blkCnt > 0U) + { + *pDst++ = ~(*pSrc++); + + /* Decrement the loop counter */ + blkCnt--; + } +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of Not group + */ diff --git a/components/nmsis/dsp/src/BasicMathFunctions/riscv_offset_f16.c b/components/nmsis/dsp/src/BasicMathFunctions/riscv_offset_f16.c new file mode 100644 index 00000000..378831c5 --- /dev/null +++ b/components/nmsis/dsp/src/BasicMathFunctions/riscv_offset_f16.c @@ -0,0 +1,122 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_offset_f16.c + * Description: Floating-point vector offset + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions_f16.h" + +/** + @ingroup groupMath + */ + +/** + @defgroup BasicOffset Vector Offset + + Adds a constant offset to each element of a vector. + + 
+      pDst[n] = pSrc[n] + offset,   0 <= n < blockSize.
+
+ + The functions support in-place computation allowing the source and + destination pointers to reference the same memory buffer. + There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + @addtogroup BasicOffset + @{ + */ + +/** + @brief Adds a constant offset to a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] offset is the offset to be added + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +#if defined(RISCV_FLOAT16_SUPPORTED) +void riscv_offset_f16( + const float16_t * pSrc, + float16_t offset, + float16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A + offset */ + + /* Add offset and store result in destination buffer. */ + *pDst++ = (*pSrc++) + offset; + + *pDst++ = (*pSrc++) + offset; + + *pDst++ = (*pSrc++) + offset; + + *pDst++ = (*pSrc++) + offset; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A + offset */ + + /* Add offset and store result in destination buffer. */ + *pDst++ = (*pSrc++) + offset; + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif + +/** + @} end of BasicOffset group + */ diff --git a/components/nmsis/dsp/src/BasicMathFunctions/riscv_offset_f32.c b/components/nmsis/dsp/src/BasicMathFunctions/riscv_offset_f32.c new file mode 100644 index 00000000..47badbac --- /dev/null +++ b/components/nmsis/dsp/src/BasicMathFunctions/riscv_offset_f32.c @@ -0,0 +1,132 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_offset_f32.c + * Description: Floating-point vector offset + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @defgroup BasicOffset Vector Offset + + Adds a constant offset to each element of a vector. + + 
+      pDst[n] = pSrc[n] + offset,   0 <= n < blockSize.
+
+ + The functions support in-place computation allowing the source and + destination pointers to reference the same memory buffer. + There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + @addtogroup BasicOffset + @{ + */ + +/** + @brief Adds a constant offset to a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] offset is the offset to be added + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +void riscv_offset_f32( + const float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + size_t l; + vfloat32m8_t vx; + + for (; (l = vsetvl_e32m8(blkCnt)) > 0; blkCnt -= l) { + vx = vle32_v_f32m8(pSrc, l); + pSrc += l; + vse32_v_f32m8 (pDst, vfadd_vf_f32m8(vx, offset, l), l); + pDst += l; + } + +#else + uint32_t blkCnt; /* Loop counter */ + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A + offset */ + + /* Add offset and store result in destination buffer. */ + *pDst++ = (*pSrc++) + offset; + + *pDst++ = (*pSrc++) + offset; + + *pDst++ = (*pSrc++) + offset; + + *pDst++ = (*pSrc++) + offset; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A + offset */ + + /* Add offset and store result in destination buffer. */ + *pDst++ = (*pSrc++) + offset; + + /* Decrement loop counter */ + blkCnt--; + } +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of BasicOffset group + */ diff --git a/components/nmsis/dsp/src/BasicMathFunctions/riscv_offset_q15.c b/components/nmsis/dsp/src/BasicMathFunctions/riscv_offset_q15.c new file mode 100644 index 00000000..3fa9f84a --- /dev/null +++ b/components/nmsis/dsp/src/BasicMathFunctions/riscv_offset_q15.c @@ -0,0 +1,151 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_offset_q15.c + * Description: Q15 vector offset + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicOffset + @{ + */ + +/** + @brief Adds a constant offset to a Q15 vector. + @param[in] pSrc points to the input vector + @param[in] offset is the offset to be added + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q15 range [0x8000 0x7FFF] are saturated. + */ +void riscv_offset_q15( + const q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + size_t l; + vint16m8_t vx; + + for (; (l = vsetvl_e16m8(blkCnt)) > 0; blkCnt -= l) { + vx = vle16_v_i16m8(pSrc, l); + pSrc += l; + vse16_v_i16m8 (pDst, vsadd_vx_i16m8(vx, offset, l), l); + pDst += l; + } +#else + uint32_t blkCnt; /* Loop counter */ + +#if defined (RISCV_MATH_LOOPUNROLL) + +#if defined (RISCV_MATH_DSP) + + #if defined (RISCV_DSP64) || (__RISCV_XLEN == 64) + q31_t offset_packed[2]; /* Offset packed to 32 bit */ + q63_t offset_all; + /* Offset is packed to 64 bit in order to use SIMD64 for addition */ + offset_packed[0] = __RV_PKBB16(offset, offset); + offset_packed[1] = __RV_PKBB16(offset, offset); + offset_all = *((q63_t *)offset_packed); + #else + q31_t offset_all; + /* Offset is packed to 32 bit in order to use SIMD32 for addition */ + offset_all = __RV_PKBB16(offset, offset); + #endif + +#endif + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A + offset */ + +#if defined (RISCV_MATH_DSP) +#if __RISCV_XLEN == 64 + write_q15x4_ia (&pDst, __RV_KADD32(read_q15x4_ia ((q15_t **) &pSrc), offset_all)); +#else + #ifdef RISCV_DSP64 + write_q15x4_ia (&pDst, __DKADD16(read_q15x4_ia ((q15_t **) &pSrc), offset_all)); + #else + /* Add offset and store result in destination buffer (2 samples at a time). */ + write_q15x2_ia (&pDst, __RV_KADD16(read_q15x2_ia ((q15_t **) &pSrc), offset_all)); + write_q15x2_ia (&pDst, __RV_KADD16(read_q15x2_ia ((q15_t **) &pSrc), offset_all)); + #endif +#endif /* __RISCV_XLEN == 64 */ +#else + *pDst++ = (q15_t) __SSAT(((q31_t) *pSrc++ + offset), 16); + *pDst++ = (q15_t) __SSAT(((q31_t) *pSrc++ + offset), 16); + *pDst++ = (q15_t) __SSAT(((q31_t) *pSrc++ + offset), 16); + *pDst++ = (q15_t) __SSAT(((q31_t) *pSrc++ + offset), 16); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A + offset */ + + /* Add offset and store result in destination buffer. */ +#if defined (RISCV_MATH_DSP) + *pDst++ = (q15_t) __QADD16(*pSrc++, offset); +#else + *pDst++ = (q15_t) __SSAT(((q31_t) *pSrc++ + offset), 16); +#endif + + /* Decrement loop counter */ + blkCnt--; + } +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of BasicOffset group + */ diff --git a/components/nmsis/dsp/src/BasicMathFunctions/riscv_offset_q31.c b/components/nmsis/dsp/src/BasicMathFunctions/riscv_offset_q31.c new file mode 100644 index 00000000..6a2d2540 --- /dev/null +++ b/components/nmsis/dsp/src/BasicMathFunctions/riscv_offset_q31.c @@ -0,0 +1,133 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_offset_q31.c + * Description: Q31 vector offset + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicOffset + @{ + */ + +/** + @brief Adds a constant offset to a Q31 vector. + @param[in] pSrc points to the input vector + @param[in] offset is the offset to be added + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] are saturated. + */ + +void riscv_offset_q31( + const q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + size_t l; + vint32m8_t vx; + + for (; (l = vsetvl_e32m8(blkCnt)) > 0; blkCnt -= l) { + vx = vle32_v_i32m8(pSrc, l); + pSrc += l; + vse32_v_i32m8 (pDst, vsadd_vx_i32m8(vx, offset, l), l); + pDst += l; + } +#else + uint32_t blkCnt; /* Loop counter */ + +#if defined (RISCV_MATH_LOOPUNROLL) +#if __RISCV_XLEN == 64 + q63_t offset_all; + /* Offset is packed to 64 bit in order to use SIMD64 for addition */ + offset_all = __RV_PKBB32(offset, offset); +#endif /* __RISCV_XLEN == 64 */ + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A + offset */ +#if __RISCV_XLEN == 64 + write_q31x2_ia (&pDst, __RV_KADD32(read_q31x2_ia ((q31_t **) &pSrc), offset_all)); + write_q31x2_ia (&pDst, __RV_KADD32(read_q31x2_ia ((q31_t **) &pSrc), offset_all)); +#else + /* Add offset and store result in destination buffer. */ + *pDst++ = __QADD(*pSrc++, offset); + + *pDst++ = __QADD(*pSrc++, offset); + + *pDst++ = __QADD(*pSrc++, offset); + + *pDst++ = __QADD(*pSrc++, offset); + +#endif /* __RISCV_XLEN == 64 */ + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A + offset */ + + /* Add offset and store result in destination buffer. */ +#if defined (RISCV_MATH_DSP) + *pDst++ = __QADD(*pSrc++, offset); +#else + *pDst++ = (q31_t) clip_q63_to_q31((q63_t) * pSrc++ + offset); +#endif + + /* Decrement loop counter */ + blkCnt--; + } +#endif /*defined(RISCV_VECTOR)*/ +} + +/** + @} end of BasicOffset group + */ diff --git a/components/nmsis/dsp/src/BasicMathFunctions/riscv_offset_q7.c b/components/nmsis/dsp/src/BasicMathFunctions/riscv_offset_q7.c new file mode 100644 index 00000000..39c1a2f8 --- /dev/null +++ b/components/nmsis/dsp/src/BasicMathFunctions/riscv_offset_q7.c @@ -0,0 +1,170 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_offset_q7.c + * Description: Q7 vector offset + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicOffset + @{ + */ + +/** + @brief Adds a constant offset to a Q7 vector. + @param[in] pSrc points to the input vector + @param[in] offset is the offset to be added + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q7 range [0x80 0x7F] are saturated. + */ +void riscv_offset_q7( + const q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + size_t l; + vint8m8_t vx, vy; + + for (; (l = vsetvl_e8m8(blkCnt)) > 0; blkCnt -= l) { + vx = vle8_v_i8m8(pSrc, l); + pSrc += l; + vse8_v_i8m8 (pDst, vsadd_vx_i8m8(vx, offset, l), l); + pDst += l; + } +#else + uint32_t blkCnt; /* Loop counter */ + +#if defined (RISCV_MATH_LOOPUNROLL) + +#if defined (RISCV_MATH_DSP) + + #if defined (RISCV_DSP64) || (__RISCV_XLEN == 64) + q63_t offset_packed; /* Offset packed to 32 bit */ + //q31_t offset_packed_32; + q7_t offset_a[8]; + offset_a[0] = offset; + offset_a[1] = offset; + offset_a[2] = offset; + offset_a[3] = offset; + offset_a[4] = offset; + offset_a[5] = offset; + offset_a[6] = offset; + offset_a[7] = offset; + + /* Offset is packed to 64 bit in order to use SIMD64 for addition */ + offset_packed = *((q63_t *)offset_a); + #else + q31_t offset_packed; /* Offset packed to 32 bit */ + /* Offset is packed to 64 bit in order to use SIMD64 for addition */ + //offset_packed = __PACKq7(offset, offset, offset, offset) ; + offset_packed = __EXPD80(offset) ; + #endif +#endif // RISCV_MATH_DSP + +#if defined (RISCV_DSP64) || (__RISCV_XLEN == 64) + /* Loop unrolling: Compute 8 outputs at a time */ + blkCnt = blockSize >> 3U; +#else + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; +#endif + + while (blkCnt > 0U) + { + /* C = A + offset */ + +#if defined (RISCV_MATH_DSP) +#if __RISCV_XLEN == 64 + write_q7x8_ia (&pDst, __RV_KADD8(read_q7x8_ia ((q7_t **) &pSrc), offset_packed)); +#else + #ifdef RISCV_DSP64 + /* Add offset and store result in destination buffer (8 samples at a time). */ + write_q7x8_ia (&pDst, __RV_DKADD8(read_q7x8_ia ((q7_t **) &pSrc), offset_packed)); + #else + write_q7x4_ia (&pDst, __RV_KADD8(read_q7x4_ia ((q7_t **) &pSrc), offset_packed)); + #endif +#endif /* __RISCV_XLEN == 64 */ +#else + *pDst++ = (q7_t) __SSAT(*pSrc++ + offset, 8); + *pDst++ = (q7_t) __SSAT(*pSrc++ + offset, 8); + *pDst++ = (q7_t) __SSAT(*pSrc++ + offset, 8); + *pDst++ = (q7_t) __SSAT(*pSrc++ + offset, 8); + #if defined (RISCV_DSP64) || (__RISCV_XLEN == 64) + *pDst++ = (q7_t) __SSAT(*pSrc++ + offset, 8); + *pDst++ = (q7_t) __SSAT(*pSrc++ + offset, 8); + *pDst++ = (q7_t) __SSAT(*pSrc++ + offset, 8); + *pDst++ = (q7_t) __SSAT(*pSrc++ + offset, 8); + #endif +#endif // RISCV_MATH_DSP + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ +#if defined (RISCV_DSP64) || (__RISCV_XLEN == 64) + blkCnt = blockSize % 0x8U; + #else + blkCnt = blockSize % 0x4U; + #endif + + +#else // RISCV_MATH_LOOPUNROLL + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A + offset */ + + /* Add offset and store result in destination buffer. */ + *pDst++ = (q7_t) __SSAT((q15_t) *pSrc++ + offset, 8); + + /* Decrement loop counter */ + blkCnt--; + } +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of BasicOffset group + */ diff --git a/components/nmsis/dsp/src/BasicMathFunctions/riscv_or_u16.c b/components/nmsis/dsp/src/BasicMathFunctions/riscv_or_u16.c new file mode 100644 index 00000000..392fd0be --- /dev/null +++ b/components/nmsis/dsp/src/BasicMathFunctions/riscv_or_u16.c @@ -0,0 +1,134 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_or_u16.c + * Description: uint16_t bitwise inclusive OR + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @defgroup Or Vector bitwise inclusive OR + + Compute the logical bitwise OR. + + There are separate functions for uint32_t, uint16_t, and uint8_t data types. + */ + +/** + @addtogroup Or + @{ + */ + +/** + @brief Compute the logical bitwise OR of two fixed-point vectors. + @param[in] pSrcA points to input vector A + @param[in] pSrcB points to input vector B + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +void riscv_or_u16( + const uint16_t * pSrcA, + const uint16_t * pSrcB, + uint16_t * pDst, + uint32_t blockSize) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + size_t l; + vuint16m8_t vx, vy; + + for (; (l = vsetvl_e16m8(blkCnt)) > 0; blkCnt -= l) { + vx = vle16_v_u16m8(pSrcA, l); + pSrcA += l; + vy = vle16_v_u16m8(pSrcB, l); + vse16_v_u16m8 (pDst, vor_vv_u16m8(vx, vy, l), l); + pSrcB += l; + pDst += l; + } +#else + uint32_t blkCnt; /* Loop counter */ + +#if defined (RISCV_DSP64) || (__RISCV_XLEN == 64) + + uint64_t * pSrcA_temp = pSrcA; + uint64_t * pSrcB_temp = pSrcB; + uint64_t * pDst_temp = pDst; + if(blkCnt = blockSize >> 2) + { + while (blkCnt > 0U) + { + *pDst_temp++ = (*pSrcA_temp++)|(*pSrcB_temp++); + + /* Decrement the loop counter */ + blkCnt--; + } + } + if(blkCnt = blockSize%4) + { + pSrcA = (uint8_t * )(pSrcA_temp-3); + pSrcB = (uint8_t * )(pSrcB_temp-3); + } + +#else + uint32_t * pSrcA_temp = pSrcA; + uint32_t * pSrcB_temp = pSrcB; + uint32_t * pDst_temp = pDst; + if(blkCnt = blockSize >> 1) + { + while (blkCnt > 0U) + { + *pDst_temp++ = (*pSrcA_temp++)|(*pSrcB_temp++); + + /* Decrement the loop counter */ + blkCnt--; + } + } + if(blkCnt = blockSize%2) + { + pSrcA = (uint8_t * )(pSrcA_temp-1); + pSrcB = (uint8_t * )(pSrcB_temp-1); + } +#endif + + while (blkCnt > 0U) + { + *pDst++ = (*pSrcA++)|(*pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of Or group + */ diff --git a/components/nmsis/dsp/src/BasicMathFunctions/riscv_or_u32.c b/components/nmsis/dsp/src/BasicMathFunctions/riscv_or_u32.c new file mode 100644 index 00000000..e64966f3 --- /dev/null +++ b/components/nmsis/dsp/src/BasicMathFunctions/riscv_or_u32.c @@ -0,0 +1,109 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_or_u32.c + * Description: uint32_t bitwise inclusive OR + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup Or + @{ + */ + +/** + @brief Compute the logical bitwise OR of two fixed-point vectors. + @param[in] pSrcA points to input vector A + @param[in] pSrcB points to input vector B + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +void riscv_or_u32( + const uint32_t * pSrcA, + const uint32_t * pSrcB, + uint32_t * pDst, + uint32_t blockSize) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + size_t l; + vuint32m8_t vx, vy; + + for (; (l = vsetvl_e32m8(blkCnt)) > 0; blkCnt -= l) { + vx = vle32_v_u32m8(pSrcA, l); + pSrcA += l; + vy = vle32_v_u32m8(pSrcB, l); + vse32_v_u32m8 (pDst, vor_vv_u32m8(vx, vy, l), l); + pSrcB += l; + pDst += l; + } +#else + uint32_t blkCnt; /* Loop counter */ + +#if defined (RISCV_DSP64) || (__RISCV_XLEN == 64) + + uint64_t * pSrcA_temp = pSrcA; + uint64_t * pSrcB_temp = pSrcB; + uint64_t * pDst_temp = pDst; + if(blkCnt = blockSize >> 1) + { + while (blkCnt > 0U) + { + *pDst_temp++ = (*pSrcA_temp++)|(*pSrcB_temp++); + + /* Decrement the loop counter */ + blkCnt--; + } + } + if(blkCnt = blockSize%2) + { + pSrcA = (uint8_t * )(pSrcA_temp-1); + pSrcB = (uint8_t * )(pSrcB_temp-1); + } + +#else + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; +#endif + + while (blkCnt > 0U) + { + *pDst++ = (*pSrcA++)|(*pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } +#endif /* defined(RISCV_VECTOR) */ +} +/** + @} end of Or group + */ diff --git a/components/nmsis/dsp/src/BasicMathFunctions/riscv_or_u8.c b/components/nmsis/dsp/src/BasicMathFunctions/riscv_or_u8.c new file mode 100644 index 00000000..87bc87dc --- /dev/null +++ b/components/nmsis/dsp/src/BasicMathFunctions/riscv_or_u8.c @@ -0,0 +1,125 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_or_u8.c + * Description: uint8_t bitwise inclusive OR + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup Or + @{ + */ + +/** + @brief Compute the logical bitwise OR of two fixed-point vectors. + @param[in] pSrcA points to input vector A + @param[in] pSrcB points to input vector B + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +void riscv_or_u8( + const uint8_t * pSrcA, + const uint8_t * pSrcB, + uint8_t * pDst, + uint32_t blockSize) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + size_t l; + vuint8m8_t vx, vy; + + for (; (l = vsetvl_e8m8(blkCnt)) > 0; blkCnt -= l) { + vx = vle8_v_u8m8(pSrcA, l); + pSrcA += l; + vy = vle8_v_u8m8(pSrcB, l); + vse8_v_u8m8 (pDst, vor_vv_u8m8(vx, vy, l), l); + pSrcB += l; + pDst += l; + } +#else + uint32_t blkCnt; /* Loop counter */ + +#if defined (RISCV_DSP64) || (__RISCV_XLEN == 64) + + uint64_t * pSrcA_temp = pSrcA; + uint64_t * pSrcB_temp = pSrcB; + uint64_t * pDst_temp = pDst; + if(blkCnt = blockSize >> 3) + { + while (blkCnt > 0U) + { + *pDst_temp++ = (*pSrcA_temp++)|(*pSrcB_temp++); + + /* Decrement the loop counter */ + blkCnt--; + } + } + if(blkCnt = blockSize%8) + { + pSrcA = (uint8_t * )(pSrcA_temp-7); + pSrcB = (uint8_t * )(pSrcB_temp-7); + } + +#else + uint32_t * pSrcA_temp = pSrcA; + uint32_t * pSrcB_temp = pSrcB; + uint32_t * pDst_temp = pDst; + if(blkCnt = blockSize >> 2) + { + while (blkCnt > 0U) + { + *pDst_temp++ = (*pSrcA_temp++)|(*pSrcB_temp++); + + /* Decrement the loop counter */ + blkCnt--; + } + } + if(blkCnt = blockSize%4) + { + pSrcA = (uint8_t * )(pSrcA_temp-3); + pSrcB = (uint8_t * )(pSrcB_temp-3); + } +#endif /*defined (RISCV_DSP64) || (__RISCV_XLEN == 64)*/ + + while (blkCnt > 0U) + { + *pDst++ = (*pSrcA++)|(*pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } +#endif /* defined(RISCV_VECTOR) */ +} +/** + @} end of Or group + */ diff --git a/components/nmsis/dsp/src/BasicMathFunctions/riscv_scale_f16.c b/components/nmsis/dsp/src/BasicMathFunctions/riscv_scale_f16.c new file mode 100644 index 00000000..d90d85fe --- /dev/null +++ b/components/nmsis/dsp/src/BasicMathFunctions/riscv_scale_f16.c @@ -0,0 +1,134 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_scale_f16.c + * Description: Multiplies a floating-point vector by a scalar + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions_f16.h" + +/** + @ingroup groupMath + */ + +/** + @defgroup BasicScale Vector Scale + + Multiply a vector by a scalar value. For floating-point data, the algorithm used is: + + 
+      pDst[n] = pSrc[n] * scale,   0 <= n < blockSize.
+
+ + In the fixed-point Q7, Q15, and Q31 functions, scale is represented by + a fractional multiplication scaleFract and an arithmetic shift shift. + The shift allows the gain of the scaling operation to exceed 1.0. + The algorithm used with fixed-point data is: + + 
+      pDst[n] = (pSrc[n] * scaleFract) << shift,   0 <= n < blockSize.
+
+ + The overall scale factor applied to the fixed-point data is + 
+      scale = scaleFract * 2^shift.
+
+ + The functions support in-place computation allowing the source and destination + pointers to reference the same memory buffer. + */ + +/** + @addtogroup BasicScale + @{ + */ + +/** + @brief Multiplies a floating-point vector by a scalar. + @param[in] pSrc points to the input vector + @param[in] scale scale factor to be applied + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +#if defined(RISCV_FLOAT16_SUPPORTED) +void riscv_scale_f16( + const float16_t *pSrc, + float16_t scale, + float16_t *pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A * scale */ + + /* Scale input and store result in destination buffer. */ + *pDst++ = (*pSrc++) * scale; + + *pDst++ = (*pSrc++) * scale; + + *pDst++ = (*pSrc++) * scale; + + *pDst++ = (*pSrc++) * scale; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A * scale */ + + /* Scale input and store result in destination buffer. */ + *pDst++ = (*pSrc++) * scale; + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif + +/** + @} end of BasicScale group + */ diff --git a/components/nmsis/dsp/src/BasicMathFunctions/riscv_scale_f32.c b/components/nmsis/dsp/src/BasicMathFunctions/riscv_scale_f32.c new file mode 100644 index 00000000..8fa5556d --- /dev/null +++ b/components/nmsis/dsp/src/BasicMathFunctions/riscv_scale_f32.c @@ -0,0 +1,150 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_scale_f32.c + * Description: Multiplies a floating-point vector by a scalar + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @defgroup BasicScale Vector Scale + + Multiply a vector by a scalar value. For floating-point data, the algorithm used is: + + 
+      pDst[n] = pSrc[n] * scale,   0 <= n < blockSize.
+
+ + In the fixed-point Q7, Q15, and Q31 functions, scale is represented by + a fractional multiplication scaleFract and an arithmetic shift shift. + The shift allows the gain of the scaling operation to exceed 1.0. + The algorithm used with fixed-point data is: + + 
+      pDst[n] = (pSrc[n] * scaleFract) << shift,   0 <= n < blockSize.
+
+ + The overall scale factor applied to the fixed-point data is + 
+      scale = scaleFract * 2^shift.
+
+ + The functions support in-place computation allowing the source and destination + pointers to reference the same memory buffer. + */ + +/** + @addtogroup BasicScale + @{ + */ + +/** + @brief Multiplies a floating-point vector by a scalar. + @param[in] pSrc points to the input vector + @param[in] scale scale factor to be applied + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +void riscv_scale_f32( + const float32_t *pSrc, + float32_t scale, + float32_t *pDst, + uint32_t blockSize) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + size_t l; + vfloat32m8_t vx; + + for (; (l = vsetvl_e32m8(blkCnt)) > 0; blkCnt -= l) { + vx = vle32_v_f32m8(pSrc, l); + pSrc += l; + vse32_v_f32m8 (pDst, vfmul_vf_f32m8(vx, scale, l), l); + pDst += l; + } +#else + uint32_t blkCnt; /* Loop counter */ +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + float32_t in1, in2, in3, in4; + + /* C = A * scale */ + + /* Scale input and store result in destination buffer. */ + in1 = (*pSrc++) * scale; + + in2 = (*pSrc++) * scale; + + in3 = (*pSrc++) * scale; + + in4 = (*pSrc++) * scale; + + *pDst++ = in1; + *pDst++ = in2; + *pDst++ = in3; + *pDst++ = in4; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A * scale */ + + /* Scale input and store result in destination buffer. */ + *pDst++ = (*pSrc++) * scale; + + /* Decrement loop counter */ + blkCnt--; + } +#endif /*defined(RISCV_VECTOR)*/ +} + +/** + @} end of BasicScale group + */ diff --git a/components/nmsis/dsp/src/BasicMathFunctions/riscv_scale_q15.c b/components/nmsis/dsp/src/BasicMathFunctions/riscv_scale_q15.c new file mode 100644 index 00000000..051a030b --- /dev/null +++ b/components/nmsis/dsp/src/BasicMathFunctions/riscv_scale_q15.c @@ -0,0 +1,192 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_scale_q15.c + * Description: Multiplies a Q15 vector by a scalar + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicScale + @{ + */ + +/** + @brief Multiplies a Q15 vector by a scalar. + @param[in] pSrc points to the input vector + @param[in] scaleFract fractional portion of the scale value + @param[in] shift number of bits to shift the result by + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The input data *pSrc and scaleFract are in 1.15 format. + These are multiplied to yield a 2.30 intermediate result and this is shifted with saturation to 1.15 format. + */ + +void riscv_scale_q15( + const q15_t *pSrc, + q15_t scaleFract, + int8_t shift, + q15_t *pDst, + uint32_t blockSize) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + int8_t kShift = 15 - shift; /* Shift to apply after scaling */ + size_t l; + vint16m4_t vx; + + for (; (l = vsetvl_e16m4(blkCnt)) > 0; blkCnt -= l) { + vx = vle16_v_i16m4(pSrc, l); + pSrc += l; + vse16_v_i16m4 (pDst, vnclip_wx_i16m4(vwmul_vx_i32m8(vx, scaleFract, l), kShift, l), l); + pDst += l; + } +#else + uint32_t blkCnt; /* Loop counter */ + int8_t kShift = 15 - shift; /* Shift to apply after scaling */ + +#if defined (RISCV_MATH_LOOPUNROLL) +#if defined (RISCV_MATH_DSP) +#if __RISCV_XLEN == 64 + q63_t inA164, inA264; + q63_t out164, out264, out364, out464; /* Temporary output variables */ + q15_t in164, in264, in364, in464; /* Temporary input variables */ +#endif /* __RISCV_XLEN == 64 */ + q31_t inA1, inA2; + q31_t out1, out2, out3, out4; /* Temporary output variables */ + q15_t in1, in2, in3, in4; /* Temporary input variables */ +#endif +#endif + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A * scale */ + +#if defined (RISCV_MATH_DSP) +#if __RISCV_XLEN == 64 + /* read 2 times 2 samples at a time from source */ + inA164 = read_q15x4_ia ((q15_t **) &pSrc); + // inA2 = read_q15x2_ia ((q15_t **) &pSrc); + + /* Scale inputs and store result in temporary variables + * in single cycle by packing the outputs */ + out1 = (q31_t) ((q15_t) (inA164 >> 16) * scaleFract); + out2 = (q31_t) ((q15_t) (inA164 ) * scaleFract); + out3 = (q31_t) ((q15_t) (inA164 >> 48) * scaleFract); + out4 = (q31_t) ((q15_t) (inA164 >> 32) * scaleFract); + + /* apply shifting */ + out1 = out1 >> kShift; + out2 = out2 >> kShift; + out3 = out3 >> kShift; + out4 = out4 >> kShift; + + /* saturate the output */ + in1 = (q15_t) (__SSAT(out1, 16)); + in2 = (q15_t) (__SSAT(out2, 16)); + in3 = (q15_t) (__SSAT(out3, 16)); + in4 = (q15_t) (__SSAT(out4, 16)); + + /* store result to destination */ + write_q15x2_ia (&pDst, __PKHBT(in2, in1, 16)); + write_q15x2_ia (&pDst, __PKHBT(in4, in3, 16)); +#else + /* read 2 times 2 samples at a time from source */ + inA1 = read_q15x2_ia ((q15_t **) &pSrc); + inA2 = read_q15x2_ia ((q15_t **) &pSrc); + + /* Scale inputs and store result in temporary variables + * in single cycle by packing the outputs */ + out1 = (q31_t) ((q15_t) (inA1 >> 16) * scaleFract); + out2 = (q31_t) ((q15_t) (inA1 ) * scaleFract); + out3 = (q31_t) ((q15_t) (inA2 >> 16) * scaleFract); + out4 = (q31_t) ((q15_t) (inA2 ) * scaleFract); + + /* apply shifting */ + out1 = out1 >> kShift; + out2 = out2 >> kShift; + out3 = out3 >> kShift; + out4 = out4 >> kShift; + + /* saturate the output */ + in1 = (q15_t) (__SSAT(out1, 16)); + in2 = (q15_t) (__SSAT(out2, 16)); + in3 = (q15_t) (__SSAT(out3, 16)); + in4 = (q15_t) (__SSAT(out4, 16)); + + /* store result to destination */ + write_q15x2_ia (&pDst, __PKHBT(in2, in1, 16)); + write_q15x2_ia (&pDst, __PKHBT(in4, in3, 16)); +#endif /* __RISCV_XLEN == 64 */ +#else + *pDst++ = (q15_t) (__SSAT(((q31_t) *pSrc++ * scaleFract) >> kShift, 16)); + *pDst++ = (q15_t) (__SSAT(((q31_t) *pSrc++ * scaleFract) >> kShift, 16)); + *pDst++ = (q15_t) (__SSAT(((q31_t) *pSrc++ * scaleFract) >> kShift, 16)); + *pDst++ = (q15_t) (__SSAT(((q31_t) *pSrc++ * scaleFract) >> kShift, 16)); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A * scale */ + + /* Scale input and store result in destination buffer. */ + *pDst++ = (q15_t) (__SSAT(((q31_t) *pSrc++ * scaleFract) >> kShift, 16)); + + /* Decrement loop counter */ + blkCnt--; + } +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of BasicScale group + */ diff --git a/components/nmsis/dsp/src/BasicMathFunctions/riscv_scale_q31.c b/components/nmsis/dsp/src/BasicMathFunctions/riscv_scale_q31.c new file mode 100644 index 00000000..63ff01d9 --- /dev/null +++ b/components/nmsis/dsp/src/BasicMathFunctions/riscv_scale_q31.c @@ -0,0 +1,230 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_scale_q31.c + * Description: Multiplies a Q31 vector by a scalar + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicScale + @{ + */ + +/** + @brief Multiplies a Q31 vector by a scalar. + @param[in] pSrc points to the input vector + @param[in] scaleFract fractional portion of the scale value + @param[in] shift number of bits to shift the result by + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The input data *pSrc and scaleFract are in 1.31 format. + These are multiplied to yield a 2.62 intermediate result and this is shifted with saturation to 1.31 format. + */ + +void riscv_scale_q31( + const q31_t *pSrc, + q31_t scaleFract, + int8_t shift, + q31_t *pDst, + uint32_t blockSize) +{ +#if defined(RISCV_VECTOR)&&((__XLEN!=32)||(__FLEN!=32)) + uint32_t blkCnt = blockSize; /* Loop counter */ + q31_t in, out; /* Temporary variables */ + int8_t kShift = shift + 1; /* Shift to apply after scaling */ + int8_t sign = (kShift & 0x80); + size_t l; + vint32m4_t v_in; + vint32m4_t v_out; + + /* C = A * scale * + /* Scale input and store result in destination buffer. */ + for (; (l = vsetvl_e32m4(blkCnt)) > 0; blkCnt -= l) { + v_in = vle32_v_i32m4(pSrc, l); + pSrc += l; + /* If the shift value is positive then do right shift else left shiftvmin_vx_i64m8(vmax_vx_i64m8( , 0xffffffff80000000),0x7fffffff)vmerge_vvm_i32m4(vmsne_vv_i32m4_b8(v_in, v_out), vxor_vx_i32m4(vsra_vx_i32m4(v_in, 31U), 0x7FFFFFFF), */ + if (sign == 0U) + { + v_out = vnclip_wx_i32m4(vsll_vx_i64m8(vsra_vx_i64m8(vwmul_vx_i64m8(v_in, scaleFract, l),32U, l), (uint8_t)kShift, l),0, l); + //if (v_in != (vsll_vx_i32m4(v_out, kShift))) + vse32_v_i32m4 (pDst, v_out, l); + /* { + v_out = vxor_vx_i32m4(vsra_vx_i32m4(v_in, 31U), 0x7FFFFFFF); + vse32_v_i32m4 (pDst, v_out); + } */ + pDst += l; + } + else + { + /* C = A * scale */ + /* Scale input and store result in destination buffer. */ + v_in = vnsra_wx_i32m4(vwmul_vx_i64m8(v_in, scaleFract, l), 32U, l); + v_out = vsra_vx_i32m4(v_in, -kShift, l); + vse32_v_i32m4 (pDst, v_out, l); + pDst += l; + } + + } +#else + uint32_t blkCnt; /* Loop counter */ + q31_t in, out; /* Temporary variables */ + int8_t kShift = shift + 1; /* Shift to apply after scaling */ + int8_t sign = (kShift & 0x80); + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + if (sign == 0U) + { + while (blkCnt > 0U) + { + /* C = A * scale */ + + /* Scale input and store result in destination buffer. */ + in = *pSrc++; /* read input from source */ + in = ((q63_t) in * scaleFract) >> 32; /* multiply input with scaler value */ + out = in << kShift; /* apply shifting */ + if (in != (out >> kShift)) /* saturate the result */ + out = 0x7FFFFFFF ^ (in >> 31); + *pDst++ = out; /* Store result destination */ + + in = *pSrc++; + in = ((q63_t) in * scaleFract) >> 32; + out = in << kShift; + if (in != (out >> kShift)) + out = 0x7FFFFFFF ^ (in >> 31); + *pDst++ = out; + + in = *pSrc++; + in = ((q63_t) in * scaleFract) >> 32; + out = in << kShift; + if (in != (out >> kShift)) + out = 0x7FFFFFFF ^ (in >> 31); + *pDst++ = out; + + in = *pSrc++; + in = ((q63_t) in * scaleFract) >> 32; + out = in << kShift; + if (in != (out >> kShift)) + out = 0x7FFFFFFF ^ (in >> 31); + *pDst++ = out; + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + while (blkCnt > 0U) + { + /* C = A * scale */ + + /* Scale input and store result in destination buffer. */ + in = *pSrc++; /* read four inputs from source */ + in = ((q63_t) in * scaleFract) >> 32; /* multiply input with scaler value */ + out = in >> -kShift; /* apply shifting */ + *pDst++ = out; /* Store result destination */ + + in = *pSrc++; + in = ((q63_t) in * scaleFract) >> 32; + out = in >> -kShift; + *pDst++ = out; + + in = *pSrc++; + in = ((q63_t) in * scaleFract) >> 32; + out = in >> -kShift; + *pDst++ = out; + + in = *pSrc++; + in = ((q63_t) in * scaleFract) >> 32; + out = in >> -kShift; + *pDst++ = out; + + /* Decrement loop counter */ + blkCnt--; + } + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + if (sign == 0U) + { + while (blkCnt > 0U) + { + /* C = A * scale */ + + /* Scale input and store result in destination buffer. */ + in = *pSrc++; + in = ((q63_t) in * scaleFract) >> 32; + out = in << kShift; + if (in != (out >> kShift)) + out = 0x7FFFFFFF ^ (in >> 31); + *pDst++ = out; + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + while (blkCnt > 0U) + { + /* C = A * scale */ + + /* Scale input and store result in destination buffer. */ + in = *pSrc++; + in = ((q63_t) in * scaleFract) >> 32; + out = in >> -kShift; + *pDst++ = out; + + /* Decrement loop counter */ + blkCnt--; + } + } +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of BasicScale group + */ diff --git a/components/nmsis/dsp/src/BasicMathFunctions/riscv_scale_q7.c b/components/nmsis/dsp/src/BasicMathFunctions/riscv_scale_q7.c new file mode 100644 index 00000000..5f67095d --- /dev/null +++ b/components/nmsis/dsp/src/BasicMathFunctions/riscv_scale_q7.c @@ -0,0 +1,168 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_scale_q7.c + * Description: Multiplies a Q7 vector by a scalar + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicScale + @{ + */ + +/** + @brief Multiplies a Q7 vector by a scalar. + @param[in] pSrc points to the input vector + @param[in] scaleFract fractional portion of the scale value + @param[in] shift number of bits to shift the result by + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The input data *pSrc and scaleFract are in 1.7 format. + These are multiplied to yield a 2.14 intermediate result and this is shifted with saturation to 1.7 format. + */ + +void riscv_scale_q7( + const q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + int8_t kShift = 7 - shift; /* Shift to apply after scaling */ + size_t l; + vint8m4_t vx; + + for (; (l = vsetvl_e8m4(blkCnt)) > 0; blkCnt -= l) { + vx = vle8_v_i8m4(pSrc, l); + pSrc += l; + vse8_v_i8m4 (pDst, vnclip_wx_i8m4(vwmul_vx_i16m8(vx, scaleFract, l), kShift, l), l); + pDst += l; + } +#else + uint32_t blkCnt; /* Loop counter */ + int8_t kShift = 7 - shift; /* Shift to apply after scaling */ + +#if defined (RISCV_MATH_LOOPUNROLL) + +#if defined (RISCV_MATH_DSP) + q7_t in1, in2, in3, in4; /* Temporary input variables */ + q7_t out1, out2, out3, out4; /* Temporary output variables */ +#endif +// #if __RISCV_XLEN == 64 +// /* Loop unrolling: Compute 8 outputs at a time */ +// blkCnt = blockSize >> 3U; +// #else + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; +// #endif /* __RISCV_XLEN == 64 */ + + while (blkCnt > 0U) + { + /* C = A * scale */ + +#if defined (RISCV_MATH_DSP) +// #if __RISCV_XLEN == 64 +// q63_t scale_packed; /* scale packed to 32 bit */ +// //q31_t scale_packed_32; +// q7_t scale_a[8]; +// scale_a[0] = scaleFract; +// scale_a[1] = scaleFract; +// scale_a[2] = scaleFract; +// scale_a[3] = scaleFract; +// scale_a[4] = scaleFract; +// scale_a[5] = scaleFract; +// scale_a[6] = scaleFract; +// scale_a[7] = scaleFract; + +// /* scale is packed to 64 bit in order to use SIMD64 for addition */ +// scale_packed = *((q63_t *)scale_a); +// write_q7x8_ia (&pDst,__RV_KSLRA8((__RV_SMUL8(read_q7x8_ia ((q7_t **) &pSrc), scale_packed)),shift)); +// #else + /* Reading 4 inputs from memory */ + in1 = *pSrc++; + in2 = *pSrc++; + in3 = *pSrc++; + in4 = *pSrc++; + + /* Scale inputs and store result in the temporary variable. */ + out1 = (q7_t) (__SSAT(((in1) * scaleFract) >> kShift, 8)); + out2 = (q7_t) (__SSAT(((in2) * scaleFract) >> kShift, 8)); + out3 = (q7_t) (__SSAT(((in3) * scaleFract) >> kShift, 8)); + out4 = (q7_t) (__SSAT(((in4) * scaleFract) >> kShift, 8)); + + /* Pack and store result in destination buffer (in single write) */ + write_q7x4_ia (&pDst, __PACKq7(out1, out2, out3, out4)); +// #endif /* __RISCV_XLEN == 64 */ +#else + *pDst++ = (q7_t) (__SSAT((((q15_t) *pSrc++ * scaleFract) >> kShift), 8)); + *pDst++ = (q7_t) (__SSAT((((q15_t) *pSrc++ * scaleFract) >> kShift), 8)); + *pDst++ = (q7_t) (__SSAT((((q15_t) *pSrc++ * scaleFract) >> kShift), 8)); + *pDst++ = (q7_t) (__SSAT((((q15_t) *pSrc++ * scaleFract) >> kShift), 8)); +#endif + + /* Decrement loop counter */ + blkCnt--; + } +// #if __RISCV_XLEN == 64 +// /* Loop unrolling: Compute remaining outputs */ +// blkCnt = blockSize % 0x8U; +// #else + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; +// #endif /* __RISCV_XLEN == 64 */ +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A * scale */ + + /* Scale input and store result in destination buffer. */ + *pDst++ = (q7_t) (__SSAT((((q15_t) *pSrc++ * scaleFract) >> kShift), 8)); + + /* Decrement loop counter */ + blkCnt--; + } +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of BasicScale group + */ diff --git a/components/nmsis/dsp/src/BasicMathFunctions/riscv_shift_q15.c b/components/nmsis/dsp/src/BasicMathFunctions/riscv_shift_q15.c new file mode 100644 index 00000000..6de65c7e --- /dev/null +++ b/components/nmsis/dsp/src/BasicMathFunctions/riscv_shift_q15.c @@ -0,0 +1,145 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_shift_q15.c + * Description: Shifts the elements of a Q15 vector by a specified number of bits + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicShift + @{ + */ + +/** + @brief Shifts the elements of a Q15 vector a specified number of bits + @param[in] pSrc points to the input vector + @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q15 range [0x8000 0x7FFF] are saturated. + */ + +void riscv_shift_q15( + const q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + uint8_t sign = (shiftBits & 0x80); + size_t l; + vint16m4_t vx; + + for (; (l = vsetvl_e16m4(blkCnt)) > 0; blkCnt -= l) { + vx = vle16_v_i16m4(pSrc, l); + pSrc += l; + /* If the shift value is positive then do right shift else left shift */ + if (sign == 0U) + { + vse16_v_i16m4 (pDst, vnclip_wx_i16m4(vsll_vx_i32m8(vwadd_vx_i32m8(vx,0, l), shiftBits, l),0, l), l); + pDst += l; + } + else + { + vse16_v_i16m4 (pDst, vsra_vx_i16m4(vx, -shiftBits, l), l); + pDst += l; + } + } +#else + uint32_t blkCnt; /* Loop counter */ + uint8_t sign = (shiftBits & 0x80); /* Sign of shiftBits */ + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + while(blkCnt > 0U) { + #if __RISCV_XLEN == 64 + write_q15x4_ia(&pDst, __RV_KSLRA16(read_q15x4_ia((q15_t **)&pSrc), shiftBits)); +#else + #ifdef RISCV_DSP64 + write_q15x4_ia(&pDst, __DKSLRA16(read_q15x4_ia((q15_t **)&pSrc), shiftBits)); + #else + write_q15x2_ia(&pDst, __RV_KSLRA16(read_q15x2_ia((q15_t **)&pSrc), shiftBits)); + write_q15x2_ia(&pDst, __RV_KSLRA16(read_q15x2_ia((q15_t **)&pSrc), shiftBits)); + #endif + #endif /* __RISCV_XLEN == 64 */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + /* If the shift value is positive then do right shift else left shift */ + if (sign == 0U) + { + while (blkCnt > 0U) + { + /* C = A << shiftBits */ + + /* Shift input and store result in destination buffer. */ + *pDst++ = __SSAT(((q31_t) *pSrc++ << shiftBits), 16); + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + while (blkCnt > 0U) + { + /* C = A >> shiftBits */ + + /* Shift input and store result in destination buffer. */ + *pDst++ = (*pSrc++ >> -shiftBits); + + /* Decrement loop counter */ + blkCnt--; + } + } +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of BasicShift group + */ diff --git a/components/nmsis/dsp/src/BasicMathFunctions/riscv_shift_q31.c b/components/nmsis/dsp/src/BasicMathFunctions/riscv_shift_q31.c new file mode 100644 index 00000000..98d2c68e --- /dev/null +++ b/components/nmsis/dsp/src/BasicMathFunctions/riscv_shift_q31.c @@ -0,0 +1,168 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_shift_q31.c + * Description: Shifts the elements of a Q31 vector by a specified number of bits + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ +/** + @defgroup BasicShift Vector Shift + + Shifts the elements of a fixed-point vector by a specified number of bits. + There are separate functions for Q7, Q15, and Q31 data types. + The underlying algorithm used is: + + 
+      pDst[n] = pSrc[n] << shift,   0 <= n < blockSize.
+
+ + If shift is positive then the elements of the vector are shifted to the left. + If shift is negative then the elements of the vector are shifted to the right. + + The functions support in-place computation allowing the source and destination + pointers to reference the same memory buffer. + */ + +/** + @addtogroup BasicShift + @{ + */ + +/** + @brief Shifts the elements of a Q31 vector a specified number of bits. + @param[in] pSrc points to the input vector + @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in the vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] are saturated. + */ + +void riscv_shift_q31( + const q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + uint8_t sign = (shiftBits & 0x80); + size_t l; + vint32m4_t vx; + + for (; (l = vsetvl_e32m4(blkCnt)) > 0; blkCnt -= l) { + vx = vle32_v_i32m4(pSrc, l); + pSrc += l; + /* If the shift value is positive then do right shift else left shift */ + if (sign == 0U) + { + vse32_v_i32m4 (pDst, vnclip_wx_i32m4(vsll_vx_i64m8(vwadd_vx_i64m8(vx,0, l), shiftBits, l),0, l), l); + pDst += l; + } + else + { + vse32_v_i32m4 (pDst, vsra_vx_i32m4(vx, -shiftBits, l), l); + pDst += l; + } + } +#else + uint32_t blkCnt; /* Loop counter */ + uint8_t sign = (shiftBits & 0x80); /* Sign of shiftBits */ + +#if defined (RISCV_MATH_LOOPUNROLL) + + q31_t in, out; /* Temporary variables */ + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; +#if __RISCV_XLEN == 64 + while (blkCnt > 0U) + { + write_q31x2_ia(&pDst, __RV_KSLRA32(read_q31x2_ia((q31_t **)&pSrc), shiftBits)); + write_q31x2_ia(&pDst, __RV_KSLRA32(read_q31x2_ia((q31_t **)&pSrc), shiftBits)); + blkCnt--; + } +#else + /* If the shift value is positive then do right shift else left shift */ + while (blkCnt > 0U) + { + *pDst++ = __RV_KSLRAW(*pSrc++, shiftBits); + *pDst++ = __RV_KSLRAW(*pSrc++, shiftBits); + *pDst++ = __RV_KSLRAW(*pSrc++, shiftBits); + *pDst++ = __RV_KSLRAW(*pSrc++, shiftBits); + blkCnt--; + } +#endif /* __RISCV_XLEN == 64 */ + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + /* If the shift value is positive then do right shift else left shift */ + if (sign == 0U) + { + while (blkCnt > 0U) + { + /* C = A << shiftBits */ + + /* Shift input and store result in destination buffer. */ + *pDst++ = clip_q63_to_q31((q63_t) *pSrc++ << shiftBits); + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + while (blkCnt > 0U) + { + /* C = A >> shiftBits */ + + /* Shift input and store result in destination buffer. */ + *pDst++ = (*pSrc++ >> -shiftBits); + + /* Decrement loop counter */ + blkCnt--; + } + } +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of BasicShift group + */ diff --git a/components/nmsis/dsp/src/BasicMathFunctions/riscv_shift_q7.c b/components/nmsis/dsp/src/BasicMathFunctions/riscv_shift_q7.c new file mode 100644 index 00000000..ae9bebfe --- /dev/null +++ b/components/nmsis/dsp/src/BasicMathFunctions/riscv_shift_q7.c @@ -0,0 +1,226 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_shift_q7.c + * Description: Processing function for the Q7 Shifting + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicShift + @{ + */ + +/** + @brief Shifts the elements of a Q7 vector a specified number of bits + @param[in] pSrc points to the input vector + @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par onditions for optimum performance + Input and output buffers should be aligned by 32-bit + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q7 range [0x80 0x7F] are saturated. + */ + +void riscv_shift_q7( + const q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + uint8_t sign = (shiftBits & 0x80); + size_t l; + vint8m4_t vx; + + for (; (l = vsetvl_e8m4(blkCnt)) > 0; blkCnt -= l) { + vx = vle8_v_i8m4(pSrc, l); + pSrc += l; + /* If the shift value is positive then do right shift else left shift */ + if (sign == 0U) + { + vse8_v_i8m4 (pDst, vnclip_wx_i8m4(vsll_vx_i16m8(vwadd_vx_i16m8(vx,0, l), shiftBits, l),0, l), l); + pDst += l; + } + else + { + vse8_v_i8m4 (pDst, vsra_vx_i8m4(vx, -shiftBits, l), l); + pDst += l; + } + } +#else + uint32_t blkCnt; /* Loop counter */ + uint8_t sign = (shiftBits & 0x80); /* Sign of shiftBits */ + +#if defined (RISCV_MATH_LOOPUNROLL) + +//#if defined (RISCV_MATH_DSP) +// q7_t in1, in2, in3, in4; /* Temporary input variables */ +//#endif +#if __RISCV_XLEN == 64 + /* Loop unrolling: Compute 8 outputs at a time */ + blkCnt = blockSize >> 3U; + + while(blkCnt > 0U) { + write_q7x8_ia(&pDst, __RV_KSLRA8(read_q7x8_ia((q7_t **)&pSrc), shiftBits)); + blkCnt--; + } +#else +#ifdef RISCV_DSP64 + /* Loop unrolling: Compute 8 outputs at a time */ + blkCnt = blockSize >> 3U; + + while(blkCnt > 0U) { + write_q7x8_ia(&pDst, __RV_DKSLRA8(read_q7x8_ia((q7_t **)&pSrc), shiftBits)); + blkCnt--; + } +#else + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while(blkCnt > 0U) { + write_q7x4_ia(&pDst, __RV_KSLRA8(read_q7x4_ia((q7_t **)&pSrc), shiftBits)); + blkCnt--; + } +#endif +#endif /* __RISCV_XLEN == 64 */ +// /* If the shift value is positive then do right shift else left shift */ +// if (sign == 0U) +// { +// while (blkCnt > 0U) +// { +// /* C = A << shiftBits */ +// +//#if defined (RISCV_MATH_DSP) +// /* Read 4 inputs */ +// //in1 = *pSrc++; +// //in2 = *pSrc++; +// //in3 = *pSrc++; +// //in4 = *pSrc++; +// +// /* Pack and store result in destination buffer (in single write) */ +// //write_q7x4_ia (&pDst, __PACKq7(__SSAT((in1 << shiftBits), 8), +// // __SSAT((in2 << shiftBits), 8), +// // __SSAT((in3 << shiftBits), 8), +// // __SSAT((in4 << shiftBits), 8) )); +// write_q7x4_ia(&pDst, __KSLRA8(read_q7x4_ia((q7_t **)&pSrc), shiftBits)); +//#else +// *pDst++ = (q7_t) __SSAT(((q15_t) *pSrc++ << shiftBits), 8); +// *pDst++ = (q7_t) __SSAT(((q15_t) *pSrc++ << shiftBits), 8); +// *pDst++ = (q7_t) __SSAT(((q15_t) *pSrc++ << shiftBits), 8); +// *pDst++ = (q7_t) __SSAT(((q15_t) *pSrc++ << shiftBits), 8); +//#endif +// +// /* Decrement loop counter */ +// blkCnt--; +// } +// } +// else +// { +// while (blkCnt > 0U) +// { +// /* C = A >> shiftBits */ +// +//#if defined (RISCV_MATH_DSP) +// /* Read 4 inputs */ +// in1 = *pSrc++; +// in2 = *pSrc++; +// in3 = *pSrc++; +// in4 = *pSrc++; +// +// /* Pack and store result in destination buffer (in single write) */ +// write_q7x4_ia (&pDst, __PACKq7((in1 >> -shiftBits), +// (in2 >> -shiftBits), +// (in3 >> -shiftBits), +// (in4 >> -shiftBits) )); +//#else +// *pDst++ = (*pSrc++ >> -shiftBits); +// *pDst++ = (*pSrc++ >> -shiftBits); +// *pDst++ = (*pSrc++ >> -shiftBits); +// *pDst++ = (*pSrc++ >> -shiftBits); +//#endif +// +// /* Decrement loop counter */ +// blkCnt--; +// } +// } + + /* Loop unrolling: Compute remaining outputs */ +#if defined (RISCV_DSP64) || (__RISCV_XLEN == 64) + blkCnt = blockSize % 0x8U; +#else + blkCnt = blockSize % 0x4U; +#endif + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + /* If the shift value is positive then do right shift else left shift */ + if (sign == 0U) + { + while (blkCnt > 0U) + { + /* C = A << shiftBits */ + + /* Shift input and store result in destination buffer. */ + *pDst++ = (q7_t) __SSAT(((q15_t) *pSrc++ << shiftBits), 8); + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + while (blkCnt > 0U) + { + /* C = A >> shiftBits */ + + /* Shift input and store result in destination buffer. */ + *pDst++ = (*pSrc++ >> -shiftBits); + + /* Decrement loop counter */ + blkCnt--; + } + } +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of BasicShift group + */ diff --git a/components/nmsis/dsp/src/BasicMathFunctions/riscv_sub_f16.c b/components/nmsis/dsp/src/BasicMathFunctions/riscv_sub_f16.c new file mode 100644 index 00000000..bffcb609 --- /dev/null +++ b/components/nmsis/dsp/src/BasicMathFunctions/riscv_sub_f16.c @@ -0,0 +1,119 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_sub_f16.c + * Description: Floating-point vector subtraction + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions_f16.h" + +/** + @ingroup groupMath + */ + +/** + @defgroup BasicSub Vector Subtraction + + Element-by-element subtraction of two vectors. + + 
+      pDst[n] = pSrcA[n] - pSrcB[n],   0 <= n < blockSize.
+
+ + There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + @addtogroup BasicSub + @{ + */ + +/** + @brief Floating-point vector subtraction. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +#if defined(RISCV_FLOAT16_SUPPORTED) +void riscv_sub_f16( + const float16_t * pSrcA, + const float16_t * pSrcB, + float16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A - B */ + + /* Subtract and store result in destination buffer. */ + *pDst++ = (*pSrcA++) - (*pSrcB++); + + *pDst++ = (*pSrcA++) - (*pSrcB++); + + *pDst++ = (*pSrcA++) - (*pSrcB++); + + *pDst++ = (*pSrcA++) - (*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A - B */ + + /* Subtract and store result in destination buffer. */ + *pDst++ = (*pSrcA++) - (*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif + +/** + @} end of BasicSub group + */ diff --git a/components/nmsis/dsp/src/BasicMathFunctions/riscv_sub_f32.c b/components/nmsis/dsp/src/BasicMathFunctions/riscv_sub_f32.c new file mode 100644 index 00000000..c49731cf --- /dev/null +++ b/components/nmsis/dsp/src/BasicMathFunctions/riscv_sub_f32.c @@ -0,0 +1,131 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_sub_f32.c + * Description: Floating-point vector subtraction + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @defgroup BasicSub Vector Subtraction + + Element-by-element subtraction of two vectors. + + 
+      pDst[n] = pSrcA[n] - pSrcB[n],   0 <= n < blockSize.
+
+ + There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + @addtogroup BasicSub + @{ + */ + +/** + @brief Floating-point vector subtraction. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +void riscv_sub_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + size_t l; + vfloat32m8_t vx, vy; + + for (; (l = vsetvl_e32m8(blkCnt)) > 0; blkCnt -= l) { + vx = vle32_v_f32m8(pSrcA, l); + pSrcA += l; + vy = vle32_v_f32m8(pSrcB, l); + vse32_v_f32m8 (pDst, vfsub_vv_f32m8(vx, vy, l), l); + pSrcB += l; + pDst += l; + } +#else + uint32_t blkCnt; /* Loop counter */ + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A - B */ + + /* Subtract and store result in destination buffer. */ + *pDst++ = (*pSrcA++) - (*pSrcB++); + + *pDst++ = (*pSrcA++) - (*pSrcB++); + + *pDst++ = (*pSrcA++) - (*pSrcB++); + + *pDst++ = (*pSrcA++) - (*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A - B */ + + /* Subtract and store result in destination buffer. */ + *pDst++ = (*pSrcA++) - (*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } +#endif /*defined(RISCV_VECTOR)*/ +} + +/** + @} end of BasicSub group + */ diff --git a/components/nmsis/dsp/src/BasicMathFunctions/riscv_sub_q15.c b/components/nmsis/dsp/src/BasicMathFunctions/riscv_sub_q15.c new file mode 100644 index 00000000..227ad106 --- /dev/null +++ b/components/nmsis/dsp/src/BasicMathFunctions/riscv_sub_q15.c @@ -0,0 +1,151 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_sub_q15.c + * Description: Q15 vector subtraction + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicSub + @{ + */ + +/** + @brief Q15 vector subtraction. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q15 range [0x8000 0x7FFF] are saturated. + */ + +void riscv_sub_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + size_t l; + vint16m8_t vx, vy; + + for (; (l = vsetvl_e16m8(blkCnt)) > 0; blkCnt -= l) { + vx = vle16_v_i16m8(pSrcA, l); + pSrcA += l; + vy = vle16_v_i16m8(pSrcB, l); + vse16_v_i16m8 (pDst, vssub_vv_i16m8(vx, vy, l), l); + pSrcB += l; + pDst += l; + } +#else + uint32_t blkCnt; /* Loop counter */ + +#if defined (RISCV_MATH_LOOPUNROLL) + +#if defined (RISCV_MATH_DSP) + q31_t inA1, inA2; + q31_t inB1, inB2; +#endif + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A - B */ + +#if defined (RISCV_MATH_DSP) + /* read 2 times 2 samples at a time from sourceA */ + //inA1 = read_q15x2_ia ((q15_t **) &pSrcA); + //inA2 = read_q15x2_ia ((q15_t **) &pSrcA); + ///* read 2 times 2 samples at a time from sourceB */ + //inB1 = read_q15x2_ia ((q15_t **) &pSrcB); + //inB2 = read_q15x2_ia ((q15_t **) &pSrcB); + + ///* Subtract and store 2 times 2 samples at a time */ + //write_q15x2_ia (&pDst, __QSUB16(inA1, inB1)); + //write_q15x2_ia (&pDst, __QSUB16(inA2, inB2)); +#if __RISCV_XLEN == 64 + write_q15x4_ia(&pDst, __RV_KSUB16(read_q15x4_ia((q15_t**)&pSrcA), read_q15x4_ia((q15_t **)&pSrcB))); +#else +#ifdef RISCV_DSP64 + write_q15x4_ia(&pDst, __DKSUB16(read_q15x4_ia((q15_t**)&pSrcA), read_q15x4_ia((q15_t **)&pSrcB))); +#else + write_q15x2_ia(&pDst, __RV_KSUB16(read_q15x2_ia((q15_t**)&pSrcA), read_q15x2_ia((q15_t **)&pSrcB))); + write_q15x2_ia(&pDst, __RV_KSUB16(read_q15x2_ia((q15_t**)&pSrcA), read_q15x2_ia((q15_t **)&pSrcB))); +#endif +#endif /* __RISCV_XLEN == 64 */ +#else + *pDst++ = (q15_t) __SSAT(((q31_t) *pSrcA++ - *pSrcB++), 16); + *pDst++ = (q15_t) __SSAT(((q31_t) *pSrcA++ - *pSrcB++), 16); + *pDst++ = (q15_t) __SSAT(((q31_t) *pSrcA++ - *pSrcB++), 16); + *pDst++ = (q15_t) __SSAT(((q31_t) *pSrcA++ - *pSrcB++), 16); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A - B */ + + /* Subtract and store result in destination buffer. */ +#if defined (RISCV_MATH_DSP) + *pDst++ = (q15_t) __QSUB16(*pSrcA++, *pSrcB++); +#else + *pDst++ = (q15_t) __SSAT(((q31_t) *pSrcA++ - *pSrcB++), 16); +#endif + + /* Decrement loop counter */ + blkCnt--; + } +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of BasicSub group + */ diff --git a/components/nmsis/dsp/src/BasicMathFunctions/riscv_sub_q31.c b/components/nmsis/dsp/src/BasicMathFunctions/riscv_sub_q31.c new file mode 100644 index 00000000..0a09bc4e --- /dev/null +++ b/components/nmsis/dsp/src/BasicMathFunctions/riscv_sub_q31.c @@ -0,0 +1,123 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_sub_q31.c + * Description: Q31 vector subtraction + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicSub + @{ + */ + +/** + @brief Q31 vector subtraction. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] are saturated. + */ + +void riscv_sub_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + size_t l; + vint32m8_t vx, vy; + + for (; (l = vsetvl_e32m8(blkCnt)) > 0; blkCnt -= l) { + vx = vle32_v_i32m8(pSrcA, l); + pSrcA += l; + vy = vle32_v_i32m8(pSrcB, l); + vse32_v_i32m8 (pDst, vssub_vv_i32m8(vx, vy, l), l); + pSrcB += l; + pDst += l; + } +#else + uint32_t blkCnt; /* Loop counter */ + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + while (blkCnt > 0U) + { + /* C = A - B */ + +#if __RISCV_XLEN == 64 + /* Subtract and store result in destination buffer (8 samples at a time). */ + write_q31x2_ia (&pDst, __RV_KSUB32(read_q31x2_ia ((q31_t **) &pSrcA), read_q31x2_ia ((q31_t **) &pSrcB))); + write_q31x2_ia (&pDst, __RV_KSUB32(read_q31x2_ia ((q31_t **) &pSrcA), read_q31x2_ia ((q31_t **) &pSrcB))); +#else + /* Subtract and store result in destination buffer. */ + *pDst++ = __QSUB(*pSrcA++, *pSrcB++); + *pDst++ = __QSUB(*pSrcA++, *pSrcB++); + *pDst++ = __QSUB(*pSrcA++, *pSrcB++); + *pDst++ = __QSUB(*pSrcA++, *pSrcB++); +#endif /* __RISCV_XLEN == 64 */ + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A - B */ + + /* Subtract and store result in destination buffer. */ + *pDst++ = __QSUB(*pSrcA++, *pSrcB++); + /* Decrement loop counter */ + blkCnt--; + } +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of BasicSub group + */ diff --git a/components/nmsis/dsp/src/BasicMathFunctions/riscv_sub_q7.c b/components/nmsis/dsp/src/BasicMathFunctions/riscv_sub_q7.c new file mode 100644 index 00000000..38fc278c --- /dev/null +++ b/components/nmsis/dsp/src/BasicMathFunctions/riscv_sub_q7.c @@ -0,0 +1,148 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_sub_q7.c + * Description: Q7 vector subtraction + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicSub + @{ + */ + +/** + @brief Q7 vector subtraction. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q7 range [0x80 0x7F] will be saturated. + */ +void riscv_sub_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + size_t l; + vint8m8_t vx, vy; + + for (; (l = vsetvl_e8m8(blkCnt)) > 0; blkCnt -= l) { + vx = vle8_v_i8m8(pSrcA, l); + pSrcA += l; + vy = vle8_v_i8m8(pSrcB, l); + vse8_v_i8m8 (pDst, vssub_vv_i8m8(vx, vy, l), l); + pSrcB += l; + pDst += l; + } +#else + uint32_t blkCnt; /* Loop counter */ + +#if defined (RISCV_MATH_LOOPUNROLL) + +#ifdef RISCV_DSP64 + /* Loop unrolling: Compute 8 outputs at a time */ + blkCnt = blockSize >> 3U; +#else + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; +#endif + + while (blkCnt > 0U) + { + /* C = A - B */ + +#if defined (RISCV_MATH_DSP) +#if __RISCV_XLEN == 64 + /* Subtract and store result in destination buffer (8 samples at a time). */ + write_q7x8_ia (&pDst, __RV_KSUB8(read_q7x8_ia ((q7_t **) &pSrcA), read_q7x8_ia ((q7_t **) &pSrcB))); +#else +#ifdef RISCV_DSP64 + /* Subtract and store result in destination buffer (8 samples at a time). */ + write_q7x8_ia (&pDst, __DQSUB8(read_q7x8_ia ((q7_t **) &pSrcA), read_q7x8_ia ((q7_t **) &pSrcB))); +#else + /* Subtract and store result in destination buffer (4 samples at a time). */ + write_q7x4_ia (&pDst, __RV_KSUB8(read_q7x4_ia ((q7_t **) &pSrcA), read_q7x4_ia ((q7_t **) &pSrcB))); +#endif +#endif /* __RISCV_XLEN == 64 */ +#else + *pDst++ = (q7_t) __SSAT((q15_t) *pSrcA++ - *pSrcB++, 8); + *pDst++ = (q7_t) __SSAT((q15_t) *pSrcA++ - *pSrcB++, 8); + *pDst++ = (q7_t) __SSAT((q15_t) *pSrcA++ - *pSrcB++, 8); + *pDst++ = (q7_t) __SSAT((q15_t) *pSrcA++ - *pSrcB++, 8); +#ifdef RISCV_DSP64 + *pDst++ = (q7_t) __SSAT((q15_t) *pSrcA++ - *pSrcB++, 8); + *pDst++ = (q7_t) __SSAT((q15_t) *pSrcA++ - *pSrcB++, 8); + *pDst++ = (q7_t) __SSAT((q15_t) *pSrcA++ - *pSrcB++, 8); + *pDst++ = (q7_t) __SSAT((q15_t) *pSrcA++ - *pSrcB++, 8); +#endif +#endif + + /* Decrement loop counter */ + blkCnt--; + } + +#ifdef RISCV_DSP64 + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x8U; +#else + blkCnt = blockSize % 0x4U; +#endif + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A - B */ + + /* Subtract and store result in destination buffer. */ + *pDst++ = (q7_t) __SSAT((q15_t) *pSrcA++ - *pSrcB++, 8); + + /* Decrement loop counter */ + blkCnt--; + } +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of BasicSub group + */ diff --git a/components/nmsis/dsp/src/BasicMathFunctions/riscv_xor_u16.c b/components/nmsis/dsp/src/BasicMathFunctions/riscv_xor_u16.c new file mode 100644 index 00000000..6261b575 --- /dev/null +++ b/components/nmsis/dsp/src/BasicMathFunctions/riscv_xor_u16.c @@ -0,0 +1,134 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_xor_u16.c + * Description: uint16_t bitwise exclusive OR + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @defgroup Xor Vector bitwise exclusive OR + + Compute the logical bitwise XOR. + + There are separate functions for uint32_t, uint16_t, and uint8_t data types. + */ + +/** + @addtogroup Xor + @{ + */ + +/** + @brief Compute the logical bitwise XOR of two fixed-point vectors. + @param[in] pSrcA points to input vector A + @param[in] pSrcB points to input vector B + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +void riscv_xor_u16( + const uint16_t * pSrcA, + const uint16_t * pSrcB, + uint16_t * pDst, + uint32_t blockSize) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + size_t l; + vuint16m8_t vx, vy; + + for (; (l = vsetvl_e16m8(blkCnt)) > 0; blkCnt -= l) { + vx = vle16_v_u16m8(pSrcA, l); + pSrcA += l; + vy = vle16_v_u16m8(pSrcB, l); + vse16_v_u16m8 (pDst, vxor_vv_u16m8(vx, vy, l), l); + pSrcB += l; + pDst += l; + } +#else + uint32_t blkCnt; /* Loop counter */ + +#if defined (RISCV_DSP64) || (__RISCV_XLEN == 64) + + uint64_t * pSrcA_temp = pSrcA; + uint64_t * pSrcB_temp = pSrcB; + uint64_t * pDst_temp = pDst; + if(blkCnt = blockSize >> 2) + { + while (blkCnt > 0U) + { + *pDst_temp++ = (*pSrcA_temp++)^(*pSrcB_temp++); + + /* Decrement the loop counter */ + blkCnt--; + } + } + if(blkCnt = blockSize%4) + { + pSrcA = (uint8_t * )(pSrcA_temp-3); + pSrcB = (uint8_t * )(pSrcB_temp-3); + } + +#else + uint32_t * pSrcA_temp = pSrcA; + uint32_t * pSrcB_temp = pSrcB; + uint32_t * pDst_temp = pDst; + if(blkCnt = blockSize >> 1) + { + while (blkCnt > 0U) + { + *pDst_temp++ = (*pSrcA_temp++)^(*pSrcB_temp++); + + /* Decrement the loop counter */ + blkCnt--; + } + } + if(blkCnt = blockSize%2) + { + pSrcA = (uint8_t * )(pSrcA_temp-1); + pSrcB = (uint8_t * )(pSrcB_temp-1); + } +#endif + + while (blkCnt > 0U) + { + *pDst++ = (*pSrcA++)^(*pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of Xor group + */ diff --git a/components/nmsis/dsp/src/BasicMathFunctions/riscv_xor_u32.c b/components/nmsis/dsp/src/BasicMathFunctions/riscv_xor_u32.c new file mode 100644 index 00000000..8779e10c --- /dev/null +++ b/components/nmsis/dsp/src/BasicMathFunctions/riscv_xor_u32.c @@ -0,0 +1,110 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_xor_u32.c + * Description: uint32_t bitwise exclusive OR + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup Xor + @{ + */ + +/** + @brief Compute the logical bitwise XOR of two fixed-point vectors. + @param[in] pSrcA points to input vector A + @param[in] pSrcB points to input vector B + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +void riscv_xor_u32( + const uint32_t * pSrcA, + const uint32_t * pSrcB, + uint32_t * pDst, + uint32_t blockSize) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + size_t l; + vuint32m8_t vx, vy; + + for (; (l = vsetvl_e32m8(blkCnt)) > 0; blkCnt -= l) { + vx = vle32_v_u32m8(pSrcA, l); + pSrcA += l; + vy = vle32_v_u32m8(pSrcB, l); + vse32_v_u32m8 (pDst, vxor_vv_u32m8(vx, vy, l), l); + pSrcB += l; + pDst += l; + } +#else + uint32_t blkCnt; /* Loop counter */ + +#if defined (RISCV_DSP64) || (__RISCV_XLEN == 64) + + uint64_t * pSrcA_temp = pSrcA; + uint64_t * pSrcB_temp = pSrcB; + uint64_t * pDst_temp = pDst; + if(blkCnt = blockSize >> 1) + { + while (blkCnt > 0U) + { + *pDst_temp++ = (*pSrcA_temp++)^(*pSrcB_temp++); + + /* Decrement the loop counter */ + blkCnt--; + } + } + if(blkCnt = blockSize%2) + { + pSrcA = (uint8_t * )(pSrcA_temp-1); + pSrcB = (uint8_t * )(pSrcB_temp-1); + } + +#else + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; +#endif + + while (blkCnt > 0U) + { + *pDst++ = (*pSrcA++)^(*pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of Xor group + */ diff --git a/components/nmsis/dsp/src/BasicMathFunctions/riscv_xor_u8.c b/components/nmsis/dsp/src/BasicMathFunctions/riscv_xor_u8.c new file mode 100644 index 00000000..4af41c8b --- /dev/null +++ b/components/nmsis/dsp/src/BasicMathFunctions/riscv_xor_u8.c @@ -0,0 +1,126 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_xor_u8.c + * Description: uint8_t bitwise exclusive OR + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup Xor + @{ + */ + +/** + @brief Compute the logical bitwise XOR of two fixed-point vectors. + @param[in] pSrcA points to input vector A + @param[in] pSrcB points to input vector B + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +void riscv_xor_u8( + const uint8_t * pSrcA, + const uint8_t * pSrcB, + uint8_t * pDst, + uint32_t blockSize) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + size_t l; + vuint8m8_t vx, vy; + + for (; (l = vsetvl_e8m8(blkCnt)) > 0; blkCnt -= l) { + vx = vle8_v_u8m8(pSrcA, l); + pSrcA += l; + vy = vle8_v_u8m8(pSrcB, l); + vse8_v_u8m8 (pDst, vxor_vv_u8m8(vx, vy, l), l); + pSrcB += l; + pDst += l; + } +#else + uint32_t blkCnt; /* Loop counter */ + +#if defined (RISCV_DSP64) || (__RISCV_XLEN == 64) + + uint64_t * pSrcA_temp = pSrcA; + uint64_t * pSrcB_temp = pSrcB; + uint64_t * pDst_temp = pDst; + if(blkCnt = blockSize >> 3) + { + while (blkCnt > 0U) + { + *pDst_temp++ = (*pSrcA_temp++)^(*pSrcB_temp++); + + /* Decrement the loop counter */ + blkCnt--; + } + } + if(blkCnt = blockSize%8) + { + pSrcA = (uint8_t * )(pSrcA_temp-7); + pSrcB = (uint8_t * )(pSrcB_temp-7); + } + +#else + uint32_t * pSrcA_temp = pSrcA; + uint32_t * pSrcB_temp = pSrcB; + uint32_t * pDst_temp = pDst; + if(blkCnt = blockSize >> 2) + { + while (blkCnt > 0U) + { + *pDst_temp++ = (*pSrcA_temp++)^(*pSrcB_temp++); + + /* Decrement the loop counter */ + blkCnt--; + } + } + if(blkCnt = blockSize%4) + { + pSrcA = (uint8_t * )(pSrcA_temp-3); + pSrcB = (uint8_t * )(pSrcB_temp-3); + } +#endif /*defined (RISCV_DSP64) || (__RISCV_XLEN == 64)*/ + + while (blkCnt > 0U) + { + *pDst++ = (*pSrcA++)^(*pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of Xor group + */ diff --git a/components/nmsis/dsp/src/BayesFunctions/BayesFunctions.c b/components/nmsis/dsp/src/BayesFunctions/BayesFunctions.c new file mode 100644 index 00000000..24af2222 --- /dev/null +++ b/components/nmsis/dsp/src/BayesFunctions/BayesFunctions.c @@ -0,0 +1,30 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: BayesFunctions.c + * Description: Combination of all bayes function source files. + * + * $Date: 16. March 2020 + * $Revision: V1.0.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2020 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "riscv_gaussian_naive_bayes_predict_f32.c" diff --git a/components/nmsis/dsp/src/BayesFunctions/BayesFunctionsF16.c b/components/nmsis/dsp/src/BayesFunctions/BayesFunctionsF16.c new file mode 100644 index 00000000..b5d46341 --- /dev/null +++ b/components/nmsis/dsp/src/BayesFunctions/BayesFunctionsF16.c @@ -0,0 +1,28 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: BayesFunctions.c + * Description: Combination of all bayes function f16 source files. + * + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2020 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "riscv_gaussian_naive_bayes_predict_f16.c" diff --git a/components/nmsis/dsp/src/BayesFunctions/riscv_gaussian_naive_bayes_predict_f16.c b/components/nmsis/dsp/src/BayesFunctions/riscv_gaussian_naive_bayes_predict_f16.c new file mode 100644 index 00000000..e77bfa99 --- /dev/null +++ b/components/nmsis/dsp/src/BayesFunctions/riscv_gaussian_naive_bayes_predict_f16.c @@ -0,0 +1,118 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_naive_gaussian_bayes_predict_f16 + * Description: Naive Gaussian Bayesian Estimator + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/bayes_functions_f16.h" + +#if defined(RISCV_FLOAT16_SUPPORTED) + +#include +#include + +#define PI_F 3.1415926535897932384626433832795f16 + +/** + * @addtogroup groupBayes + * @{ + */ + +/** + * @brief Naive Gaussian Bayesian Estimator + * + * @param[in] *S points to a naive bayes instance structure + * @param[in] *in points to the elements of the input vector. + * @param[out] *pOutputProbabilities points to a buffer of length numberOfClasses containing estimated probabilities + * @param[out] *pBufferB points to a temporary buffer of length numberOfClasses + * @return The predicted class + * + * + */ + + +uint32_t riscv_gaussian_naive_bayes_predict_f16(const riscv_gaussian_naive_bayes_instance_f16 *S, + const float16_t * in, + float16_t *pOutputProbabilities, + float16_t *pBufferB) +{ + uint32_t nbClass; + uint32_t nbDim; + const float16_t *pPrior = S->classPriors; + const float16_t *pTheta = S->theta; + const float16_t *pSigma = S->sigma; + float16_t *buffer = pOutputProbabilities; + const float16_t *pIn=in; + float16_t result; + _Float16 sigma; + _Float16 tmp; + _Float16 acc1,acc2; + uint32_t index; + (void)pBufferB; + + pTheta=S->theta; + pSigma=S->sigma; + + for(nbClass = 0; nbClass < S->numberOfClasses; nbClass++) + { + + + pIn = in; + + tmp = 0.0f16; + acc1 = 0.0f16; + acc2 = 0.0f16; + for(nbDim = 0; nbDim < S->vectorDimension; nbDim++) + { + sigma = *pSigma + S->epsilon; + acc1 += logf(2.0f16 * (_Float16)PI_F * sigma); + acc2 += (*pIn - *pTheta) * (*pIn - *pTheta) / sigma; + + pIn++; + pTheta++; + pSigma++; + } + + tmp = -0.5f16 * acc1; + tmp -= 0.5f16 * acc2; + + + *buffer = tmp + logf(*pPrior++); + buffer++; + } + + riscv_max_f16(pOutputProbabilities,S->numberOfClasses,&result,&index); + + return(index); +} + + +/** + * @} end of groupBayes group + */ + +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ + diff --git a/components/nmsis/dsp/src/BayesFunctions/riscv_gaussian_naive_bayes_predict_f32.c b/components/nmsis/dsp/src/BayesFunctions/riscv_gaussian_naive_bayes_predict_f32.c new file mode 100644 index 00000000..61635f43 --- /dev/null +++ b/components/nmsis/dsp/src/BayesFunctions/riscv_gaussian_naive_bayes_predict_f32.c @@ -0,0 +1,115 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_naive_gaussian_bayes_predict_f32 + * Description: Naive Gaussian Bayesian Estimator + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/bayes_functions.h" +#include +#include + +#define PI_F 3.1415926535897932384626433832795f +#define DPI_F (2.0f*3.1415926535897932384626433832795f) + +/** + * @addtogroup groupBayes + * @{ + */ + +/** + * @brief Naive Gaussian Bayesian Estimator + * + * @param[in] *S points to a naive bayes instance structure + * @param[in] *in points to the elements of the input vector. + * @param[out] *pOutputProbabilities points to a buffer of length numberOfClasses containing estimated probabilities + * @param[out] *pBufferB points to a temporary buffer of length numberOfClasses + * @return The predicted class + * + * + */ + + + +uint32_t riscv_gaussian_naive_bayes_predict_f32(const riscv_gaussian_naive_bayes_instance_f32 *S, + const float32_t * in, + float32_t *pOutputProbabilities, + float32_t *pBufferB) +{ + uint32_t nbClass; + uint32_t nbDim; + const float32_t *pPrior = S->classPriors; + const float32_t *pTheta = S->theta; + const float32_t *pSigma = S->sigma; + float32_t *buffer = pOutputProbabilities; + const float32_t *pIn=in; + float32_t result; + float32_t sigma; + float32_t tmp; + float32_t acc1,acc2; + uint32_t index; + + (void)pBufferB; + + pTheta=S->theta; + pSigma=S->sigma; + + for(nbClass = 0; nbClass < S->numberOfClasses; nbClass++) + { + + + pIn = in; + + tmp = 0.0; + acc1 = 0.0f; + acc2 = 0.0f; + for(nbDim = 0; nbDim < S->vectorDimension; nbDim++) + { + sigma = *pSigma + S->epsilon; + acc1 += logf(2.0f * PI_F * sigma); + acc2 += (*pIn - *pTheta) * (*pIn - *pTheta) / sigma; + + pIn++; + pTheta++; + pSigma++; + } + + tmp = -0.5f * acc1; + tmp -= 0.5f * acc2; + + + *buffer = tmp + logf(*pPrior++); + buffer++; + } + + riscv_max_f32(pOutputProbabilities,S->numberOfClasses,&result,&index); + + return(index); +} + + +/** + * @} end of groupBayes group + */ diff --git a/components/nmsis/dsp/src/CommonTables/CommonTables.c b/components/nmsis/dsp/src/CommonTables/CommonTables.c new file mode 100644 index 00000000..e6c822cf --- /dev/null +++ b/components/nmsis/dsp/src/CommonTables/CommonTables.c @@ -0,0 +1,32 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: CommonTables.c + * Description: Combination of all common table source files. + * + * $Date: 08. January 2020 + * $Revision: V1.1.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2019-2020 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "riscv_common_tables.c" +#include "riscv_const_structs.c" +#include "riscv_mve_tables.c" diff --git a/components/nmsis/dsp/src/CommonTables/CommonTablesF16.c b/components/nmsis/dsp/src/CommonTables/CommonTablesF16.c new file mode 100644 index 00000000..fae61a7e --- /dev/null +++ b/components/nmsis/dsp/src/CommonTables/CommonTablesF16.c @@ -0,0 +1,32 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: CommonTables.c + * Description: Combination of all common table source files. + * + * $Date: 08. January 2020 + * $Revision: V1.1.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2019-2020 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "riscv_common_tables_f16.c" +#include "riscv_const_structs_f16.c" +#include "riscv_mve_tables_f16.c" diff --git a/components/nmsis/dsp/src/CommonTables/riscv_common_tables.c b/components/nmsis/dsp/src/CommonTables/riscv_common_tables.c new file mode 100644 index 00000000..5ab84de8 --- /dev/null +++ b/components/nmsis/dsp/src/CommonTables/riscv_common_tables.c @@ -0,0 +1,70391 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_common_tables.c + * Description: common tables like fft twiddle factors, Bitreverse, reciprocal etc + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "riscv_math_types.h" +#include "riscv_common_tables.h" + +/** + @ingroup ComplexFFT + */ + +/** + @addtogroup CFFT_CIFFT Complex FFT Tables + @{ + */ + +/** + @par + Pseudo code for Generation of Bit reversal Table is + @par + 
for (l = 1; l <= N/4; l++)
+  {
+    for (i = 0; i< logN2; i++)
+    {
+      a[i] = l & (1 << i);
+    }
+    for (j = 0; j < logN2; j++)
+    {
+      if (a[j] != 0)
+      y[l] += (1 << ((logN2 - 1) - j));
+    }
+    y[l] = y[l] >> 1;
+   }
+ @par + where N = 4096, logN2 = 12 + @par + N is the maximum FFT Size supported +*/ + +/** + @brief Table for bit reversal process +*/ +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_FFT_ALLOW_TABLES) + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREV_1024) +const uint16_t riscvBitRevTable[1024] = { + 0x400, 0x200, 0x600, 0x100, 0x500, 0x300, 0x700, 0x080, 0x480, 0x280, + 0x680, 0x180, 0x580, 0x380, 0x780, 0x040, 0x440, 0x240, 0x640, 0x140, + 0x540, 0x340, 0x740, 0x0c0, 0x4c0, 0x2c0, 0x6c0, 0x1c0, 0x5c0, 0x3c0, + 0x7c0, 0x020, 0x420, 0x220, 0x620, 0x120, 0x520, 0x320, 0x720, 0x0a0, + 0x4a0, 0x2a0, 0x6a0, 0x1a0, 0x5a0, 0x3a0, 0x7a0, 0x060, 0x460, 0x260, + 0x660, 0x160, 0x560, 0x360, 0x760, 0x0e0, 0x4e0, 0x2e0, 0x6e0, 0x1e0, + 0x5e0, 0x3e0, 0x7e0, 0x010, 0x410, 0x210, 0x610, 0x110, 0x510, 0x310, + 0x710, 0x090, 0x490, 0x290, 0x690, 0x190, 0x590, 0x390, 0x790, 0x050, + 0x450, 0x250, 0x650, 0x150, 0x550, 0x350, 0x750, 0x0d0, 0x4d0, 0x2d0, + 0x6d0, 0x1d0, 0x5d0, 0x3d0, 0x7d0, 0x030, 0x430, 0x230, 0x630, 0x130, + 0x530, 0x330, 0x730, 0x0b0, 0x4b0, 0x2b0, 0x6b0, 0x1b0, 0x5b0, 0x3b0, + 0x7b0, 0x070, 0x470, 0x270, 0x670, 0x170, 0x570, 0x370, 0x770, 0x0f0, + 0x4f0, 0x2f0, 0x6f0, 0x1f0, 0x5f0, 0x3f0, 0x7f0, 0x008, 0x408, 0x208, + 0x608, 0x108, 0x508, 0x308, 0x708, 0x088, 0x488, 0x288, 0x688, 0x188, + 0x588, 0x388, 0x788, 0x048, 0x448, 0x248, 0x648, 0x148, 0x548, 0x348, + 0x748, 0x0c8, 0x4c8, 0x2c8, 0x6c8, 0x1c8, 0x5c8, 0x3c8, 0x7c8, 0x028, + 0x428, 0x228, 0x628, 0x128, 0x528, 0x328, 0x728, 0x0a8, 0x4a8, 0x2a8, + 0x6a8, 0x1a8, 0x5a8, 0x3a8, 0x7a8, 0x068, 0x468, 0x268, 0x668, 0x168, + 0x568, 0x368, 0x768, 0x0e8, 0x4e8, 0x2e8, 0x6e8, 0x1e8, 0x5e8, 0x3e8, + 0x7e8, 0x018, 0x418, 0x218, 0x618, 0x118, 0x518, 0x318, 0x718, 0x098, + 0x498, 0x298, 0x698, 0x198, 0x598, 0x398, 0x798, 0x058, 0x458, 0x258, + 0x658, 0x158, 0x558, 0x358, 0x758, 0x0d8, 0x4d8, 0x2d8, 0x6d8, 0x1d8, + 0x5d8, 0x3d8, 0x7d8, 0x038, 0x438, 0x238, 0x638, 0x138, 0x538, 0x338, + 0x738, 0x0b8, 0x4b8, 0x2b8, 0x6b8, 0x1b8, 0x5b8, 0x3b8, 0x7b8, 0x078, + 0x478, 0x278, 0x678, 0x178, 0x578, 0x378, 0x778, 0x0f8, 0x4f8, 0x2f8, + 0x6f8, 0x1f8, 0x5f8, 0x3f8, 0x7f8, 0x004, 0x404, 0x204, 0x604, 0x104, + 0x504, 0x304, 0x704, 0x084, 0x484, 0x284, 0x684, 0x184, 0x584, 0x384, + 0x784, 0x044, 0x444, 0x244, 0x644, 0x144, 0x544, 0x344, 0x744, 0x0c4, + 0x4c4, 0x2c4, 0x6c4, 0x1c4, 0x5c4, 0x3c4, 0x7c4, 0x024, 0x424, 0x224, + 0x624, 0x124, 0x524, 0x324, 0x724, 0x0a4, 0x4a4, 0x2a4, 0x6a4, 0x1a4, + 0x5a4, 0x3a4, 0x7a4, 0x064, 0x464, 0x264, 0x664, 0x164, 0x564, 0x364, + 0x764, 0x0e4, 0x4e4, 0x2e4, 0x6e4, 0x1e4, 0x5e4, 0x3e4, 0x7e4, 0x014, + 0x414, 0x214, 0x614, 0x114, 0x514, 0x314, 0x714, 0x094, 0x494, 0x294, + 0x694, 0x194, 0x594, 0x394, 0x794, 0x054, 0x454, 0x254, 0x654, 0x154, + 0x554, 0x354, 0x754, 0x0d4, 0x4d4, 0x2d4, 0x6d4, 0x1d4, 0x5d4, 0x3d4, + 0x7d4, 0x034, 0x434, 0x234, 0x634, 0x134, 0x534, 0x334, 0x734, 0x0b4, + 0x4b4, 0x2b4, 0x6b4, 0x1b4, 0x5b4, 0x3b4, 0x7b4, 0x074, 0x474, 0x274, + 0x674, 0x174, 0x574, 0x374, 0x774, 0x0f4, 0x4f4, 0x2f4, 0x6f4, 0x1f4, + 0x5f4, 0x3f4, 0x7f4, 0x00c, 0x40c, 0x20c, 0x60c, 0x10c, 0x50c, 0x30c, + 0x70c, 0x08c, 0x48c, 0x28c, 0x68c, 0x18c, 0x58c, 0x38c, 0x78c, 0x04c, + 0x44c, 0x24c, 0x64c, 0x14c, 0x54c, 0x34c, 0x74c, 0x0cc, 0x4cc, 0x2cc, + 0x6cc, 0x1cc, 0x5cc, 0x3cc, 0x7cc, 0x02c, 0x42c, 0x22c, 0x62c, 0x12c, + 0x52c, 0x32c, 0x72c, 0x0ac, 0x4ac, 0x2ac, 0x6ac, 0x1ac, 0x5ac, 0x3ac, + 0x7ac, 0x06c, 0x46c, 0x26c, 0x66c, 0x16c, 0x56c, 0x36c, 0x76c, 0x0ec, + 0x4ec, 0x2ec, 0x6ec, 0x1ec, 0x5ec, 0x3ec, 0x7ec, 0x01c, 0x41c, 0x21c, + 0x61c, 0x11c, 0x51c, 0x31c, 0x71c, 0x09c, 0x49c, 0x29c, 0x69c, 0x19c, + 0x59c, 0x39c, 0x79c, 0x05c, 0x45c, 0x25c, 0x65c, 0x15c, 0x55c, 0x35c, + 0x75c, 0x0dc, 0x4dc, 0x2dc, 0x6dc, 0x1dc, 0x5dc, 0x3dc, 0x7dc, 0x03c, + 0x43c, 0x23c, 0x63c, 0x13c, 0x53c, 0x33c, 0x73c, 0x0bc, 0x4bc, 0x2bc, + 0x6bc, 0x1bc, 0x5bc, 0x3bc, 0x7bc, 0x07c, 0x47c, 0x27c, 0x67c, 0x17c, + 0x57c, 0x37c, 0x77c, 0x0fc, 0x4fc, 0x2fc, 0x6fc, 0x1fc, 0x5fc, 0x3fc, + 0x7fc, 0x002, 0x402, 0x202, 0x602, 0x102, 0x502, 0x302, 0x702, 0x082, + 0x482, 0x282, 0x682, 0x182, 0x582, 0x382, 0x782, 0x042, 0x442, 0x242, + 0x642, 0x142, 0x542, 0x342, 0x742, 0x0c2, 0x4c2, 0x2c2, 0x6c2, 0x1c2, + 0x5c2, 0x3c2, 0x7c2, 0x022, 0x422, 0x222, 0x622, 0x122, 0x522, 0x322, + 0x722, 0x0a2, 0x4a2, 0x2a2, 0x6a2, 0x1a2, 0x5a2, 0x3a2, 0x7a2, 0x062, + 0x462, 0x262, 0x662, 0x162, 0x562, 0x362, 0x762, 0x0e2, 0x4e2, 0x2e2, + 0x6e2, 0x1e2, 0x5e2, 0x3e2, 0x7e2, 0x012, 0x412, 0x212, 0x612, 0x112, + 0x512, 0x312, 0x712, 0x092, 0x492, 0x292, 0x692, 0x192, 0x592, 0x392, + 0x792, 0x052, 0x452, 0x252, 0x652, 0x152, 0x552, 0x352, 0x752, 0x0d2, + 0x4d2, 0x2d2, 0x6d2, 0x1d2, 0x5d2, 0x3d2, 0x7d2, 0x032, 0x432, 0x232, + 0x632, 0x132, 0x532, 0x332, 0x732, 0x0b2, 0x4b2, 0x2b2, 0x6b2, 0x1b2, + 0x5b2, 0x3b2, 0x7b2, 0x072, 0x472, 0x272, 0x672, 0x172, 0x572, 0x372, + 0x772, 0x0f2, 0x4f2, 0x2f2, 0x6f2, 0x1f2, 0x5f2, 0x3f2, 0x7f2, 0x00a, + 0x40a, 0x20a, 0x60a, 0x10a, 0x50a, 0x30a, 0x70a, 0x08a, 0x48a, 0x28a, + 0x68a, 0x18a, 0x58a, 0x38a, 0x78a, 0x04a, 0x44a, 0x24a, 0x64a, 0x14a, + 0x54a, 0x34a, 0x74a, 0x0ca, 0x4ca, 0x2ca, 0x6ca, 0x1ca, 0x5ca, 0x3ca, + 0x7ca, 0x02a, 0x42a, 0x22a, 0x62a, 0x12a, 0x52a, 0x32a, 0x72a, 0x0aa, + 0x4aa, 0x2aa, 0x6aa, 0x1aa, 0x5aa, 0x3aa, 0x7aa, 0x06a, 0x46a, 0x26a, + 0x66a, 0x16a, 0x56a, 0x36a, 0x76a, 0x0ea, 0x4ea, 0x2ea, 0x6ea, 0x1ea, + 0x5ea, 0x3ea, 0x7ea, 0x01a, 0x41a, 0x21a, 0x61a, 0x11a, 0x51a, 0x31a, + 0x71a, 0x09a, 0x49a, 0x29a, 0x69a, 0x19a, 0x59a, 0x39a, 0x79a, 0x5a, + 0x45a, 0x25a, 0x65a, 0x15a, 0x55a, 0x35a, 0x75a, 0x0da, 0x4da, 0x2da, + 0x6da, 0x1da, 0x5da, 0x3da, 0x7da, 0x03a, 0x43a, 0x23a, 0x63a, 0x13a, + 0x53a, 0x33a, 0x73a, 0x0ba, 0x4ba, 0x2ba, 0x6ba, 0x1ba, 0x5ba, 0x3ba, + 0x7ba, 0x07a, 0x47a, 0x27a, 0x67a, 0x17a, 0x57a, 0x37a, 0x77a, 0x0fa, + 0x4fa, 0x2fa, 0x6fa, 0x1fa, 0x5fa, 0x3fa, 0x7fa, 0x006, 0x406, 0x206, + 0x606, 0x106, 0x506, 0x306, 0x706, 0x086, 0x486, 0x286, 0x686, 0x186, + 0x586, 0x386, 0x786, 0x046, 0x446, 0x246, 0x646, 0x146, 0x546, 0x346, + 0x746, 0x0c6, 0x4c6, 0x2c6, 0x6c6, 0x1c6, 0x5c6, 0x3c6, 0x7c6, 0x026, + 0x426, 0x226, 0x626, 0x126, 0x526, 0x326, 0x726, 0x0a6, 0x4a6, 0x2a6, + 0x6a6, 0x1a6, 0x5a6, 0x3a6, 0x7a6, 0x066, 0x466, 0x266, 0x666, 0x166, + 0x566, 0x366, 0x766, 0x0e6, 0x4e6, 0x2e6, 0x6e6, 0x1e6, 0x5e6, 0x3e6, + 0x7e6, 0x016, 0x416, 0x216, 0x616, 0x116, 0x516, 0x316, 0x716, 0x096, + 0x496, 0x296, 0x696, 0x196, 0x596, 0x396, 0x796, 0x056, 0x456, 0x256, + 0x656, 0x156, 0x556, 0x356, 0x756, 0x0d6, 0x4d6, 0x2d6, 0x6d6, 0x1d6, + 0x5d6, 0x3d6, 0x7d6, 0x036, 0x436, 0x236, 0x636, 0x136, 0x536, 0x336, + 0x736, 0x0b6, 0x4b6, 0x2b6, 0x6b6, 0x1b6, 0x5b6, 0x3b6, 0x7b6, 0x076, + 0x476, 0x276, 0x676, 0x176, 0x576, 0x376, 0x776, 0x0f6, 0x4f6, 0x2f6, + 0x6f6, 0x1f6, 0x5f6, 0x3f6, 0x7f6, 0x00e, 0x40e, 0x20e, 0x60e, 0x10e, + 0x50e, 0x30e, 0x70e, 0x08e, 0x48e, 0x28e, 0x68e, 0x18e, 0x58e, 0x38e, + 0x78e, 0x04e, 0x44e, 0x24e, 0x64e, 0x14e, 0x54e, 0x34e, 0x74e, 0x0ce, + 0x4ce, 0x2ce, 0x6ce, 0x1ce, 0x5ce, 0x3ce, 0x7ce, 0x02e, 0x42e, 0x22e, + 0x62e, 0x12e, 0x52e, 0x32e, 0x72e, 0x0ae, 0x4ae, 0x2ae, 0x6ae, 0x1ae, + 0x5ae, 0x3ae, 0x7ae, 0x06e, 0x46e, 0x26e, 0x66e, 0x16e, 0x56e, 0x36e, + 0x76e, 0x0ee, 0x4ee, 0x2ee, 0x6ee, 0x1ee, 0x5ee, 0x3ee, 0x7ee, 0x01e, + 0x41e, 0x21e, 0x61e, 0x11e, 0x51e, 0x31e, 0x71e, 0x09e, 0x49e, 0x29e, + 0x69e, 0x19e, 0x59e, 0x39e, 0x79e, 0x05e, 0x45e, 0x25e, 0x65e, 0x15e, + 0x55e, 0x35e, 0x75e, 0x0de, 0x4de, 0x2de, 0x6de, 0x1de, 0x5de, 0x3de, + 0x7de, 0x03e, 0x43e, 0x23e, 0x63e, 0x13e, 0x53e, 0x33e, 0x73e, 0x0be, + 0x4be, 0x2be, 0x6be, 0x1be, 0x5be, 0x3be, 0x7be, 0x07e, 0x47e, 0x27e, + 0x67e, 0x17e, 0x57e, 0x37e, 0x77e, 0x0fe, 0x4fe, 0x2fe, 0x6fe, 0x1fe, + 0x5fe, 0x3fe, 0x7fe, 0x001 +}; +#endif + +/** + @brief Double Precision Floating-point Twiddle factors Table Generation +*/ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_F64_16) +/** + @par + Example code for Double Precision Floating-point Twiddle factors Generation: + @par + 
for (i = 0; i < N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/(double)N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/(double)N);
+  }
+ @par + where N = 16, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const uint64_t twiddleCoefF64_16[32] = { + 0x3ff0000000000000, 0x0000000000000000, // 1, 0' + 0x3fed906bcf328d46, 0x3fd87de2a6aea963, // 0.92388, 0.38268' + 0x3fe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // 0.70711, 0.70711' + 0x3fd87de2a6aea963, 0x3fed906bcf328d46, // 0.38268, 0.92388' + 0x0000000000000000, 0x3ff0000000000000, // 0, 1' + 0xbfd87de2a6aea963, 0x3fed906bcf328d46, //-0.38268, 0.92388' + 0xbfe6a09e667f3bcc, 0x3fe6a09e667f3bcc, //-0.70711, 0.70711' + 0xbfed906bcf328d46, 0x3fd87de2a6aea963, //-0.92388, 0.38268' + 0xbff0000000000000, 0x0000000000000000, // -1, 0' + 0xbfed906bcf328d46, 0xbfd87de2a6aea963, //-0.92388,-0.38268' + 0xbfe6a09e667f3bcc, 0xbfe6a09e667f3bcc, //-0.70711,-0.70711' + 0xbfd87de2a6aea963, 0xbfed906bcf328d46, //-0.38268,-0.92388' + 0x0000000000000000, 0xbff0000000000000, // 0, -1' + 0x3fd87de2a6aea963, 0xbfed906bcf328d46, // 0.38268,-0.92388' + 0x3fe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // 0.70711,-0.70711' + 0x3fed906bcf328d46, 0xbfd87de2a6aea963, // 0.92388,-0.38268' +}; + +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_F64_32) + +/** + @par + Example code for Double Precision Floating-point Twiddle factors Generation: + @par + 
for (i = 0; i< N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/N);
+  }
+ @par + where N = 32, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const uint64_t twiddleCoefF64_32[64] = { + 0x3ff0000000000000, 0x0000000000000000, // 1, 0' + 0x3fef6297cff75cb0, 0x3fc8f8b83c69a60a, // 0.98079, 0.19509' + 0x3fed906bcf328d46, 0x3fd87de2a6aea963, // 0.92388, 0.38268' + 0x3fea9b66290ea1a3, 0x3fe1c73b39ae68c8, // 0.83147, 0.55557' + 0x3fe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // 0.70711, 0.70711' + 0x3fe1c73b39ae68c8, 0x3fea9b66290ea1a3, // 0.55557, 0.83147' + 0x3fd87de2a6aea963, 0x3fed906bcf328d46, // 0.38268, 0.92388' + 0x3fc8f8b83c69a60a, 0x3fef6297cff75cb0, // 0.19509, 0.98079' + 0x0000000000000000, 0x3ff0000000000000, // 0, 1' + 0xbfc8f8b83c69a60a, 0x3fef6297cff75cb0, //-0.19509, 0.98079' + 0xbfd87de2a6aea963, 0x3fed906bcf328d46, //-0.38268, 0.92388' + 0xbfe1c73b39ae68c8, 0x3fea9b66290ea1a3, //-0.55557, 0.83147' + 0xbfe6a09e667f3bcc, 0x3fe6a09e667f3bcc, //-0.70711, 0.70711' + 0xbfea9b66290ea1a3, 0x3fe1c73b39ae68c8, //-0.83147, 0.55557' + 0xbfed906bcf328d46, 0x3fd87de2a6aea963, //-0.92388, 0.38268' + 0xbfef6297cff75cb0, 0x3fc8f8b83c69a60a, //-0.98079, 0.19509' + 0xbff0000000000000, 0x0000000000000000, // -1, 0' + 0xbfef6297cff75cb0, 0xbfc8f8b83c69a60a, //-0.98079,-0.19509' + 0xbfed906bcf328d46, 0xbfd87de2a6aea963, //-0.92388,-0.38268' + 0xbfea9b66290ea1a3, 0xbfe1c73b39ae68c8, //-0.83147,-0.55557' + 0xbfe6a09e667f3bcc, 0xbfe6a09e667f3bcc, //-0.70711,-0.70711' + 0xbfe1c73b39ae68c8, 0xbfea9b66290ea1a3, //-0.55557,-0.83147' + 0xbfd87de2a6aea963, 0xbfed906bcf328d46, //-0.38268,-0.92388' + 0xbfc8f8b83c69a60a, 0xbfef6297cff75cb0, //-0.19509,-0.98079' + 0x0000000000000000, 0xbff0000000000000, // 0, -1' + 0x3fc8f8b83c69a60a, 0xbfef6297cff75cb0, // 0.19509,-0.98079' + 0x3fd87de2a6aea963, 0xbfed906bcf328d46, // 0.38268,-0.92388' + 0x3fe1c73b39ae68c8, 0xbfea9b66290ea1a3, // 0.55557,-0.83147' + 0x3fe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // 0.70711,-0.70711' + 0x3fea9b66290ea1a3, 0xbfe1c73b39ae68c8, // 0.83147,-0.55557' + 0x3fed906bcf328d46, 0xbfd87de2a6aea963, // 0.92388,-0.38268' + 0x3fef6297cff75cb0, 0xbfc8f8b83c69a60a, // 0.98079,-0.19509' +}; + +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_F64_64) +/** + @par + Example code for Double Precision Floating-point Twiddle factors Generation: + @par + 
for(i = 0; i < N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/(float)N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 64, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const uint64_t twiddleCoefF64_64[128] = { + 0x3ff0000000000000, 0x0000000000000000, // 1, 0' + 0x3fefd88da3d12526, 0x3fb917a6bc29b42c, // 0.99518, 0.098017' + 0x3fef6297cff75cb0, 0x3fc8f8b83c69a60a, // 0.98079, 0.19509' + 0x3fee9f4156c62dda, 0x3fd294062ed59f05, // 0.95694, 0.29028' + 0x3fed906bcf328d46, 0x3fd87de2a6aea963, // 0.92388, 0.38268' + 0x3fec38b2f180bdb1, 0x3fde2b5d3806f63b, // 0.88192, 0.4714' + 0x3fea9b66290ea1a3, 0x3fe1c73b39ae68c8, // 0.83147, 0.55557' + 0x3fe8bc806b151741, 0x3fe44cf325091dd6, // 0.77301, 0.63439' + 0x3fe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // 0.70711, 0.70711' + 0x3fe44cf325091dd6, 0x3fe8bc806b151741, // 0.63439, 0.77301' + 0x3fe1c73b39ae68c8, 0x3fea9b66290ea1a3, // 0.55557, 0.83147' + 0x3fde2b5d3806f63b, 0x3fec38b2f180bdb1, // 0.4714, 0.88192' + 0x3fd87de2a6aea963, 0x3fed906bcf328d46, // 0.38268, 0.92388' + 0x3fd294062ed59f05, 0x3fee9f4156c62dda, // 0.29028, 0.95694' + 0x3fc8f8b83c69a60a, 0x3fef6297cff75cb0, // 0.19509, 0.98079' + 0x3fb917a6bc29b42c, 0x3fefd88da3d12526, // 0.098017, 0.99518' + 0x0000000000000000, 0x3ff0000000000000, // 0, 1' + 0xbfb917a6bc29b42c, 0x3fefd88da3d12526, //-0.098017, 0.99518' + 0xbfc8f8b83c69a60a, 0x3fef6297cff75cb0, // -0.19509, 0.98079' + 0xbfd294062ed59f05, 0x3fee9f4156c62dda, // -0.29028, 0.95694' + 0xbfd87de2a6aea963, 0x3fed906bcf328d46, // -0.38268, 0.92388' + 0xbfde2b5d3806f63b, 0x3fec38b2f180bdb1, // -0.4714, 0.88192' + 0xbfe1c73b39ae68c8, 0x3fea9b66290ea1a3, // -0.55557, 0.83147' + 0xbfe44cf325091dd6, 0x3fe8bc806b151741, // -0.63439, 0.77301' + 0xbfe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // -0.70711, 0.70711' + 0xbfe8bc806b151741, 0x3fe44cf325091dd6, // -0.77301, 0.63439' + 0xbfea9b66290ea1a3, 0x3fe1c73b39ae68c8, // -0.83147, 0.55557' + 0xbfec38b2f180bdb1, 0x3fde2b5d3806f63b, // -0.88192, 0.4714' + 0xbfed906bcf328d46, 0x3fd87de2a6aea963, // -0.92388, 0.38268' + 0xbfee9f4156c62dda, 0x3fd294062ed59f05, // -0.95694, 0.29028' + 0xbfef6297cff75cb0, 0x3fc8f8b83c69a60a, // -0.98079, 0.19509' + 0xbfefd88da3d12526, 0x3fb917a6bc29b42c, // -0.99518, 0.098017' + 0xbff0000000000000, 0x0000000000000000, // -1, 0' + 0xbfefd88da3d12526, 0xbfb917a6bc29b42c, // -0.99518,-0.098017' + 0xbfef6297cff75cb0, 0xbfc8f8b83c69a60a, // -0.98079, -0.19509' + 0xbfee9f4156c62dda, 0xbfd294062ed59f05, // -0.95694, -0.29028' + 0xbfed906bcf328d46, 0xbfd87de2a6aea963, // -0.92388, -0.38268' + 0xbfec38b2f180bdb1, 0xbfde2b5d3806f63b, // -0.88192, -0.4714' + 0xbfea9b66290ea1a3, 0xbfe1c73b39ae68c8, // -0.83147, -0.55557' + 0xbfe8bc806b151741, 0xbfe44cf325091dd6, // -0.77301, -0.63439' + 0xbfe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // -0.70711, -0.70711' + 0xbfe44cf325091dd6, 0xbfe8bc806b151741, // -0.63439, -0.77301' + 0xbfe1c73b39ae68c8, 0xbfea9b66290ea1a3, // -0.55557, -0.83147' + 0xbfde2b5d3806f63b, 0xbfec38b2f180bdb1, // -0.4714, -0.88192' + 0xbfd87de2a6aea963, 0xbfed906bcf328d46, // -0.38268, -0.92388' + 0xbfd294062ed59f05, 0xbfee9f4156c62dda, // -0.29028, -0.95694' + 0xbfc8f8b83c69a60a, 0xbfef6297cff75cb0, // -0.19509, -0.98079' + 0xbfb917a6bc29b42c, 0xbfefd88da3d12526, //-0.098017, -0.99518' + 0x0000000000000000, 0xbff0000000000000, // 0, -1' + 0x3fb917a6bc29b42c, 0xbfefd88da3d12526, // 0.098017, -0.99518' + 0x3fc8f8b83c69a60a, 0xbfef6297cff75cb0, // 0.19509, -0.98079' + 0x3fd294062ed59f05, 0xbfee9f4156c62dda, // 0.29028, -0.95694' + 0x3fd87de2a6aea963, 0xbfed906bcf328d46, // 0.38268, -0.92388' + 0x3fde2b5d3806f63b, 0xbfec38b2f180bdb1, // 0.4714, -0.88192' + 0x3fe1c73b39ae68c8, 0xbfea9b66290ea1a3, // 0.55557, -0.83147' + 0x3fe44cf325091dd6, 0xbfe8bc806b151741, // 0.63439, -0.77301' + 0x3fe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // 0.70711, -0.70711' + 0x3fe8bc806b151741, 0xbfe44cf325091dd6, // 0.77301, -0.63439' + 0x3fea9b66290ea1a3, 0xbfe1c73b39ae68c8, // 0.83147, -0.55557' + 0x3fec38b2f180bdb1, 0xbfde2b5d3806f63b, // 0.88192, -0.4714' + 0x3fed906bcf328d46, 0xbfd87de2a6aea963, // 0.92388, -0.38268' + 0x3fee9f4156c62dda, 0xbfd294062ed59f05, // 0.95694, -0.29028' + 0x3fef6297cff75cb0, 0xbfc8f8b83c69a60a, // 0.98079, -0.19509' + 0x3fefd88da3d12526, 0xbfb917a6bc29b42c, // 0.99518,-0.098017' + }; + +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_F64_128) +/** + @par + Example code for Double Precision Floating-point Twiddle factors Generation: + @par + 
for (i = 0; i< N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/(float)N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 128, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const uint64_t twiddleCoefF64_128[256] = { + 0x3ff0000000000000, 0x0000000000000000, // 1, 0' + 0x3feff621e3796d7e, 0x3fa91f65f10dd814, // 0.9988, 0.049068' + 0x3fefd88da3d12526, 0x3fb917a6bc29b42c, // 0.99518, 0.098017' + 0x3fefa7557f08a517, 0x3fc2c8106e8e613a, // 0.98918, 0.14673' + 0x3fef6297cff75cb0, 0x3fc8f8b83c69a60a, // 0.98079, 0.19509' + 0x3fef0a7efb9230d7, 0x3fcf19f97b215f1a, // 0.97003, 0.24298' + 0x3fee9f4156c62dda, 0x3fd294062ed59f05, // 0.95694, 0.29028' + 0x3fee212104f686e5, 0x3fd58f9a75ab1fdd, // 0.94154, 0.33689' + 0x3fed906bcf328d46, 0x3fd87de2a6aea963, // 0.92388, 0.38268' + 0x3feced7af43cc773, 0x3fdb5d1009e15cc0, // 0.90399, 0.42756' + 0x3fec38b2f180bdb1, 0x3fde2b5d3806f63b, // 0.88192, 0.4714' + 0x3feb728345196e3e, 0x3fe073879922ffed, // 0.85773, 0.5141' + 0x3fea9b66290ea1a3, 0x3fe1c73b39ae68c8, // 0.83147, 0.55557' + 0x3fe9b3e047f38741, 0x3fe30ff7fce17035, // 0.80321, 0.5957' + 0x3fe8bc806b151741, 0x3fe44cf325091dd6, // 0.77301, 0.63439' + 0x3fe7b5df226aafb0, 0x3fe57d69348cec9f, // 0.74095, 0.67156' + 0x3fe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // 0.70711, 0.70711' + 0x3fe57d69348cec9f, 0x3fe7b5df226aafb0, // 0.67156, 0.74095' + 0x3fe44cf325091dd6, 0x3fe8bc806b151741, // 0.63439, 0.77301' + 0x3fe30ff7fce17035, 0x3fe9b3e047f38741, // 0.5957, 0.80321' + 0x3fe1c73b39ae68c8, 0x3fea9b66290ea1a3, // 0.55557, 0.83147' + 0x3fe073879922ffed, 0x3feb728345196e3e, // 0.5141, 0.85773' + 0x3fde2b5d3806f63b, 0x3fec38b2f180bdb1, // 0.4714, 0.88192' + 0x3fdb5d1009e15cc0, 0x3feced7af43cc773, // 0.42756, 0.90399' + 0x3fd87de2a6aea963, 0x3fed906bcf328d46, // 0.38268, 0.92388' + 0x3fd58f9a75ab1fdd, 0x3fee212104f686e5, // 0.33689, 0.94154' + 0x3fd294062ed59f05, 0x3fee9f4156c62dda, // 0.29028, 0.95694' + 0x3fcf19f97b215f1a, 0x3fef0a7efb9230d7, // 0.24298, 0.97003' + 0x3fc8f8b83c69a60a, 0x3fef6297cff75cb0, // 0.19509, 0.98079' + 0x3fc2c8106e8e613a, 0x3fefa7557f08a517, // 0.14673, 0.98918' + 0x3fb917a6bc29b42c, 0x3fefd88da3d12526, // 0.098017, 0.99518' + 0x3fa91f65f10dd814, 0x3feff621e3796d7e, // 0.049068, 0.9988' + 0x0000000000000000, 0x3ff0000000000000, // 0, 1' + 0xbfa91f65f10dd814, 0x3feff621e3796d7e, //-0.049068, 0.9988' + 0xbfb917a6bc29b42c, 0x3fefd88da3d12526, //-0.098017, 0.99518' + 0xbfc2c8106e8e613a, 0x3fefa7557f08a517, // -0.14673, 0.98918' + 0xbfc8f8b83c69a60a, 0x3fef6297cff75cb0, // -0.19509, 0.98079' + 0xbfcf19f97b215f1a, 0x3fef0a7efb9230d7, // -0.24298, 0.97003' + 0xbfd294062ed59f05, 0x3fee9f4156c62dda, // -0.29028, 0.95694' + 0xbfd58f9a75ab1fdd, 0x3fee212104f686e5, // -0.33689, 0.94154' + 0xbfd87de2a6aea963, 0x3fed906bcf328d46, // -0.38268, 0.92388' + 0xbfdb5d1009e15cc0, 0x3feced7af43cc773, // -0.42756, 0.90399' + 0xbfde2b5d3806f63b, 0x3fec38b2f180bdb1, // -0.4714, 0.88192' + 0xbfe073879922ffed, 0x3feb728345196e3e, // -0.5141, 0.85773' + 0xbfe1c73b39ae68c8, 0x3fea9b66290ea1a3, // -0.55557, 0.83147' + 0xbfe30ff7fce17035, 0x3fe9b3e047f38741, // -0.5957, 0.80321' + 0xbfe44cf325091dd6, 0x3fe8bc806b151741, // -0.63439, 0.77301' + 0xbfe57d69348cec9f, 0x3fe7b5df226aafb0, // -0.67156, 0.74095' + 0xbfe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // -0.70711, 0.70711' + 0xbfe7b5df226aafb0, 0x3fe57d69348cec9f, // -0.74095, 0.67156' + 0xbfe8bc806b151741, 0x3fe44cf325091dd6, // -0.77301, 0.63439' + 0xbfe9b3e047f38741, 0x3fe30ff7fce17035, // -0.80321, 0.5957' + 0xbfea9b66290ea1a3, 0x3fe1c73b39ae68c8, // -0.83147, 0.55557' + 0xbfeb728345196e3e, 0x3fe073879922ffed, // -0.85773, 0.5141' + 0xbfec38b2f180bdb1, 0x3fde2b5d3806f63b, // -0.88192, 0.4714' + 0xbfeced7af43cc773, 0x3fdb5d1009e15cc0, // -0.90399, 0.42756' + 0xbfed906bcf328d46, 0x3fd87de2a6aea963, // -0.92388, 0.38268' + 0xbfee212104f686e5, 0x3fd58f9a75ab1fdd, // -0.94154, 0.33689' + 0xbfee9f4156c62dda, 0x3fd294062ed59f05, // -0.95694, 0.29028' + 0xbfef0a7efb9230d7, 0x3fcf19f97b215f1a, // -0.97003, 0.24298' + 0xbfef6297cff75cb0, 0x3fc8f8b83c69a60a, // -0.98079, 0.19509' + 0xbfefa7557f08a517, 0x3fc2c8106e8e613a, // -0.98918, 0.14673' + 0xbfefd88da3d12526, 0x3fb917a6bc29b42c, // -0.99518, 0.098017' + 0xbfeff621e3796d7e, 0x3fa91f65f10dd814, // -0.9988, 0.049068' + 0xbff0000000000000, 0x0000000000000000, // -1, 0' + 0xbfeff621e3796d7e, 0xbfa91f65f10dd814, // -0.9988,-0.049068' + 0xbfefd88da3d12526, 0xbfb917a6bc29b42c, // -0.99518,-0.098017' + 0xbfefa7557f08a517, 0xbfc2c8106e8e613a, // -0.98918, -0.14673' + 0xbfef6297cff75cb0, 0xbfc8f8b83c69a60a, // -0.98079, -0.19509' + 0xbfef0a7efb9230d7, 0xbfcf19f97b215f1a, // -0.97003, -0.24298' + 0xbfee9f4156c62dda, 0xbfd294062ed59f05, // -0.95694, -0.29028' + 0xbfee212104f686e5, 0xbfd58f9a75ab1fdd, // -0.94154, -0.33689' + 0xbfed906bcf328d46, 0xbfd87de2a6aea963, // -0.92388, -0.38268' + 0xbfeced7af43cc773, 0xbfdb5d1009e15cc0, // -0.90399, -0.42756' + 0xbfec38b2f180bdb1, 0xbfde2b5d3806f63b, // -0.88192, -0.4714' + 0xbfeb728345196e3e, 0xbfe073879922ffed, // -0.85773, -0.5141' + 0xbfea9b66290ea1a3, 0xbfe1c73b39ae68c8, // -0.83147, -0.55557' + 0xbfe9b3e047f38741, 0xbfe30ff7fce17035, // -0.80321, -0.5957' + 0xbfe8bc806b151741, 0xbfe44cf325091dd6, // -0.77301, -0.63439' + 0xbfe7b5df226aafb0, 0xbfe57d69348cec9f, // -0.74095, -0.67156' + 0xbfe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // -0.70711, -0.70711' + 0xbfe57d69348cec9f, 0xbfe7b5df226aafb0, // -0.67156, -0.74095' + 0xbfe44cf325091dd6, 0xbfe8bc806b151741, // -0.63439, -0.77301' + 0xbfe30ff7fce17035, 0xbfe9b3e047f38741, // -0.5957, -0.80321' + 0xbfe1c73b39ae68c8, 0xbfea9b66290ea1a3, // -0.55557, -0.83147' + 0xbfe073879922ffed, 0xbfeb728345196e3e, // -0.5141, -0.85773' + 0xbfde2b5d3806f63b, 0xbfec38b2f180bdb1, // -0.4714, -0.88192' + 0xbfdb5d1009e15cc0, 0xbfeced7af43cc773, // -0.42756, -0.90399' + 0xbfd87de2a6aea963, 0xbfed906bcf328d46, // -0.38268, -0.92388' + 0xbfd58f9a75ab1fdd, 0xbfee212104f686e5, // -0.33689, -0.94154' + 0xbfd294062ed59f05, 0xbfee9f4156c62dda, // -0.29028, -0.95694' + 0xbfcf19f97b215f1a, 0xbfef0a7efb9230d7, // -0.24298, -0.97003' + 0xbfc8f8b83c69a60a, 0xbfef6297cff75cb0, // -0.19509, -0.98079' + 0xbfc2c8106e8e613a, 0xbfefa7557f08a517, // -0.14673, -0.98918' + 0xbfb917a6bc29b42c, 0xbfefd88da3d12526, //-0.098017, -0.99518' + 0xbfa91f65f10dd814, 0xbfeff621e3796d7e, //-0.049068, -0.9988' + 0x0000000000000000, 0xbff0000000000000, // 0, -1' + 0x3fa91f65f10dd814, 0xbfeff621e3796d7e, // 0.049068, -0.9988' + 0x3fb917a6bc29b42c, 0xbfefd88da3d12526, // 0.098017, -0.99518' + 0x3fc2c8106e8e613a, 0xbfefa7557f08a517, // 0.14673, -0.98918' + 0x3fc8f8b83c69a60a, 0xbfef6297cff75cb0, // 0.19509, -0.98079' + 0x3fcf19f97b215f1a, 0xbfef0a7efb9230d7, // 0.24298, -0.97003' + 0x3fd294062ed59f05, 0xbfee9f4156c62dda, // 0.29028, -0.95694' + 0x3fd58f9a75ab1fdd, 0xbfee212104f686e5, // 0.33689, -0.94154' + 0x3fd87de2a6aea963, 0xbfed906bcf328d46, // 0.38268, -0.92388' + 0x3fdb5d1009e15cc0, 0xbfeced7af43cc773, // 0.42756, -0.90399' + 0x3fde2b5d3806f63b, 0xbfec38b2f180bdb1, // 0.4714, -0.88192' + 0x3fe073879922ffed, 0xbfeb728345196e3e, // 0.5141, -0.85773' + 0x3fe1c73b39ae68c8, 0xbfea9b66290ea1a3, // 0.55557, -0.83147' + 0x3fe30ff7fce17035, 0xbfe9b3e047f38741, // 0.5957, -0.80321' + 0x3fe44cf325091dd6, 0xbfe8bc806b151741, // 0.63439, -0.77301' + 0x3fe57d69348cec9f, 0xbfe7b5df226aafb0, // 0.67156, -0.74095' + 0x3fe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // 0.70711, -0.70711' + 0x3fe7b5df226aafb0, 0xbfe57d69348cec9f, // 0.74095, -0.67156' + 0x3fe8bc806b151741, 0xbfe44cf325091dd6, // 0.77301, -0.63439' + 0x3fe9b3e047f38741, 0xbfe30ff7fce17035, // 0.80321, -0.5957' + 0x3fea9b66290ea1a3, 0xbfe1c73b39ae68c8, // 0.83147, -0.55557' + 0x3feb728345196e3e, 0xbfe073879922ffed, // 0.85773, -0.5141' + 0x3fec38b2f180bdb1, 0xbfde2b5d3806f63b, // 0.88192, -0.4714' + 0x3feced7af43cc773, 0xbfdb5d1009e15cc0, // 0.90399, -0.42756' + 0x3fed906bcf328d46, 0xbfd87de2a6aea963, // 0.92388, -0.38268' + 0x3fee212104f686e5, 0xbfd58f9a75ab1fdd, // 0.94154, -0.33689' + 0x3fee9f4156c62dda, 0xbfd294062ed59f05, // 0.95694, -0.29028' + 0x3fef0a7efb9230d7, 0xbfcf19f97b215f1a, // 0.97003, -0.24298' + 0x3fef6297cff75cb0, 0xbfc8f8b83c69a60a, // 0.98079, -0.19509' + 0x3fefa7557f08a517, 0xbfc2c8106e8e613a, // 0.98918, -0.14673' + 0x3fefd88da3d12526, 0xbfb917a6bc29b42c, // 0.99518,-0.098017' + 0x3feff621e3796d7e, 0xbfa91f65f10dd814, // 0.9988,-0.049068' +}; + +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_F64_256) +/** + @par + Example code for Double Precision Floating-point Twiddle factors Generation: + @par + 
for(i = 0; i< N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/(float)N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 256, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const uint64_t twiddleCoefF64_256[512] = { + 0x3ff0000000000000, 0x0000000000000000, // 1, 0 + 0x3feffd886084cd0d, 0x3f992155f7a3667e, // 0.9997, 0.024541 + 0x3feff621e3796d7e, 0x3fa91f65f10dd814, // 0.9988, 0.049068 + 0x3fefe9cdad01883a, 0x3fb2d52092ce19f6, // 0.99729, 0.073565 + 0x3fefd88da3d12526, 0x3fb917a6bc29b42c, // 0.99518, 0.098017 + 0x3fefc26470e19fd3, 0x3fbf564e56a9730e, // 0.99248, 0.12241 + 0x3fefa7557f08a517, 0x3fc2c8106e8e613a, // 0.98918, 0.14673 + 0x3fef8764fa714ba9, 0x3fc5e214448b3fc6, // 0.98528, 0.17096 + 0x3fef6297cff75cb0, 0x3fc8f8b83c69a60a, // 0.98079, 0.19509 + 0x3fef38f3ac64e589, 0x3fcc0b826a7e4f63, // 0.9757, 0.2191 + 0x3fef0a7efb9230d7, 0x3fcf19f97b215f1a, // 0.97003, 0.24298 + 0x3feed740e7684963, 0x3fd111d262b1f677, // 0.96378, 0.26671 + 0x3fee9f4156c62dda, 0x3fd294062ed59f05, // 0.95694, 0.29028 + 0x3fee6288ec48e112, 0x3fd4135c94176602, // 0.94953, 0.31368 + 0x3fee212104f686e5, 0x3fd58f9a75ab1fdd, // 0.94154, 0.33689 + 0x3feddb13b6ccc23d, 0x3fd7088530fa459e, // 0.93299, 0.3599 + 0x3fed906bcf328d46, 0x3fd87de2a6aea963, // 0.92388, 0.38268 + 0x3fed4134d14dc93a, 0x3fd9ef7943a8ed8a, // 0.91421, 0.40524 + 0x3feced7af43cc773, 0x3fdb5d1009e15cc0, // 0.90399, 0.42756 + 0x3fec954b213411f5, 0x3fdcc66e9931c45d, // 0.89322, 0.44961 + 0x3fec38b2f180bdb1, 0x3fde2b5d3806f63b, // 0.88192, 0.4714 + 0x3febd7c0ac6f952a, 0x3fdf8ba4dbf89aba, // 0.87009, 0.4929 + 0x3feb728345196e3e, 0x3fe073879922ffed, // 0.85773, 0.5141 + 0x3feb090a58150200, 0x3fe11eb3541b4b22, // 0.84485, 0.535 + 0x3fea9b66290ea1a3, 0x3fe1c73b39ae68c8, // 0.83147, 0.55557 + 0x3fea29a7a0462782, 0x3fe26d054cdd12df, // 0.81758, 0.57581 + 0x3fe9b3e047f38741, 0x3fe30ff7fce17035, // 0.80321, 0.5957 + 0x3fe93a22499263fc, 0x3fe3affa292050b9, // 0.78835, 0.61523 + 0x3fe8bc806b151741, 0x3fe44cf325091dd6, // 0.77301, 0.63439 + 0x3fe83b0e0bff976e, 0x3fe4e6cabbe3e5e9, // 0.75721, 0.65317 + 0x3fe7b5df226aafb0, 0x3fe57d69348cec9f, // 0.74095, 0.67156 + 0x3fe72d0837efff97, 0x3fe610b7551d2cde, // 0.72425, 0.68954 + 0x3fe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // 0.70711, 0.70711 + 0x3fe610b7551d2cde, 0x3fe72d0837efff97, // 0.68954, 0.72425 + 0x3fe57d69348cec9f, 0x3fe7b5df226aafb0, // 0.67156, 0.74095 + 0x3fe4e6cabbe3e5e9, 0x3fe83b0e0bff976e, // 0.65317, 0.75721 + 0x3fe44cf325091dd6, 0x3fe8bc806b151741, // 0.63439, 0.77301 + 0x3fe3affa292050b9, 0x3fe93a22499263fc, // 0.61523, 0.78835 + 0x3fe30ff7fce17035, 0x3fe9b3e047f38741, // 0.5957, 0.80321 + 0x3fe26d054cdd12df, 0x3fea29a7a0462782, // 0.57581, 0.81758 + 0x3fe1c73b39ae68c8, 0x3fea9b66290ea1a3, // 0.55557, 0.83147 + 0x3fe11eb3541b4b22, 0x3feb090a58150200, // 0.535, 0.84485 + 0x3fe073879922ffed, 0x3feb728345196e3e, // 0.5141, 0.85773 + 0x3fdf8ba4dbf89aba, 0x3febd7c0ac6f952a, // 0.4929, 0.87009 + 0x3fde2b5d3806f63b, 0x3fec38b2f180bdb1, // 0.4714, 0.88192 + 0x3fdcc66e9931c45d, 0x3fec954b213411f5, // 0.44961, 0.89322 + 0x3fdb5d1009e15cc0, 0x3feced7af43cc773, // 0.42756, 0.90399 + 0x3fd9ef7943a8ed8a, 0x3fed4134d14dc93a, // 0.40524, 0.91421 + 0x3fd87de2a6aea963, 0x3fed906bcf328d46, // 0.38268, 0.92388 + 0x3fd7088530fa459e, 0x3feddb13b6ccc23d, // 0.3599, 0.93299 + 0x3fd58f9a75ab1fdd, 0x3fee212104f686e5, // 0.33689, 0.94154 + 0x3fd4135c94176602, 0x3fee6288ec48e112, // 0.31368, 0.94953 + 0x3fd294062ed59f05, 0x3fee9f4156c62dda, // 0.29028, 0.95694 + 0x3fd111d262b1f677, 0x3feed740e7684963, // 0.26671, 0.96378 + 0x3fcf19f97b215f1a, 0x3fef0a7efb9230d7, // 0.24298, 0.97003 + 0x3fcc0b826a7e4f63, 0x3fef38f3ac64e589, // 0.2191, 0.9757 + 0x3fc8f8b83c69a60a, 0x3fef6297cff75cb0, // 0.19509, 0.98079 + 0x3fc5e214448b3fc6, 0x3fef8764fa714ba9, // 0.17096, 0.98528 + 0x3fc2c8106e8e613a, 0x3fefa7557f08a517, // 0.14673, 0.98918 + 0x3fbf564e56a9730e, 0x3fefc26470e19fd3, // 0.12241, 0.99248 + 0x3fb917a6bc29b42c, 0x3fefd88da3d12526, // 0.098017, 0.99518 + 0x3fb2d52092ce19f6, 0x3fefe9cdad01883a, // 0.073565, 0.99729 + 0x3fa91f65f10dd814, 0x3feff621e3796d7e, // 0.049068, 0.9988 + 0x3f992155f7a3667e, 0x3feffd886084cd0d, // 0.024541, 0.9997 + 0x0000000000000000, 0x3ff0000000000000, // 0, 1 + 0xbf992155f7a3667e, 0x3feffd886084cd0d, //-0.024541, 0.9997 + 0xbfa91f65f10dd814, 0x3feff621e3796d7e, //-0.049068, 0.9988 + 0xbfb2d52092ce19f6, 0x3fefe9cdad01883a, //-0.073565, 0.99729 + 0xbfb917a6bc29b42c, 0x3fefd88da3d12526, //-0.098017, 0.99518 + 0xbfbf564e56a9730e, 0x3fefc26470e19fd3, // -0.12241, 0.99248 + 0xbfc2c8106e8e613a, 0x3fefa7557f08a517, // -0.14673, 0.98918 + 0xbfc5e214448b3fc6, 0x3fef8764fa714ba9, // -0.17096, 0.98528 + 0xbfc8f8b83c69a60a, 0x3fef6297cff75cb0, // -0.19509, 0.98079 + 0xbfcc0b826a7e4f63, 0x3fef38f3ac64e589, // -0.2191, 0.9757 + 0xbfcf19f97b215f1a, 0x3fef0a7efb9230d7, // -0.24298, 0.97003 + 0xbfd111d262b1f677, 0x3feed740e7684963, // -0.26671, 0.96378 + 0xbfd294062ed59f05, 0x3fee9f4156c62dda, // -0.29028, 0.95694 + 0xbfd4135c94176602, 0x3fee6288ec48e112, // -0.31368, 0.94953 + 0xbfd58f9a75ab1fdd, 0x3fee212104f686e5, // -0.33689, 0.94154 + 0xbfd7088530fa459e, 0x3feddb13b6ccc23d, // -0.3599, 0.93299 + 0xbfd87de2a6aea963, 0x3fed906bcf328d46, // -0.38268, 0.92388 + 0xbfd9ef7943a8ed8a, 0x3fed4134d14dc93a, // -0.40524, 0.91421 + 0xbfdb5d1009e15cc0, 0x3feced7af43cc773, // -0.42756, 0.90399 + 0xbfdcc66e9931c45d, 0x3fec954b213411f5, // -0.44961, 0.89322 + 0xbfde2b5d3806f63b, 0x3fec38b2f180bdb1, // -0.4714, 0.88192 + 0xbfdf8ba4dbf89aba, 0x3febd7c0ac6f952a, // -0.4929, 0.87009 + 0xbfe073879922ffed, 0x3feb728345196e3e, // -0.5141, 0.85773 + 0xbfe11eb3541b4b22, 0x3feb090a58150200, // -0.535, 0.84485 + 0xbfe1c73b39ae68c8, 0x3fea9b66290ea1a3, // -0.55557, 0.83147 + 0xbfe26d054cdd12df, 0x3fea29a7a0462782, // -0.57581, 0.81758 + 0xbfe30ff7fce17035, 0x3fe9b3e047f38741, // -0.5957, 0.80321 + 0xbfe3affa292050b9, 0x3fe93a22499263fc, // -0.61523, 0.78835 + 0xbfe44cf325091dd6, 0x3fe8bc806b151741, // -0.63439, 0.77301 + 0xbfe4e6cabbe3e5e9, 0x3fe83b0e0bff976e, // -0.65317, 0.75721 + 0xbfe57d69348cec9f, 0x3fe7b5df226aafb0, // -0.67156, 0.74095 + 0xbfe610b7551d2cde, 0x3fe72d0837efff97, // -0.68954, 0.72425 + 0xbfe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // -0.70711, 0.70711 + 0xbfe72d0837efff97, 0x3fe610b7551d2cde, // -0.72425, 0.68954 + 0xbfe7b5df226aafb0, 0x3fe57d69348cec9f, // -0.74095, 0.67156 + 0xbfe83b0e0bff976e, 0x3fe4e6cabbe3e5e9, // -0.75721, 0.65317 + 0xbfe8bc806b151741, 0x3fe44cf325091dd6, // -0.77301, 0.63439 + 0xbfe93a22499263fc, 0x3fe3affa292050b9, // -0.78835, 0.61523 + 0xbfe9b3e047f38741, 0x3fe30ff7fce17035, // -0.80321, 0.5957 + 0xbfea29a7a0462782, 0x3fe26d054cdd12df, // -0.81758, 0.57581 + 0xbfea9b66290ea1a3, 0x3fe1c73b39ae68c8, // -0.83147, 0.55557 + 0xbfeb090a58150200, 0x3fe11eb3541b4b22, // -0.84485, 0.535 + 0xbfeb728345196e3e, 0x3fe073879922ffed, // -0.85773, 0.5141 + 0xbfebd7c0ac6f952a, 0x3fdf8ba4dbf89aba, // -0.87009, 0.4929 + 0xbfec38b2f180bdb1, 0x3fde2b5d3806f63b, // -0.88192, 0.4714 + 0xbfec954b213411f5, 0x3fdcc66e9931c45d, // -0.89322, 0.44961 + 0xbfeced7af43cc773, 0x3fdb5d1009e15cc0, // -0.90399, 0.42756 + 0xbfed4134d14dc93a, 0x3fd9ef7943a8ed8a, // -0.91421, 0.40524 + 0xbfed906bcf328d46, 0x3fd87de2a6aea963, // -0.92388, 0.38268 + 0xbfeddb13b6ccc23d, 0x3fd7088530fa459e, // -0.93299, 0.3599 + 0xbfee212104f686e5, 0x3fd58f9a75ab1fdd, // -0.94154, 0.33689 + 0xbfee6288ec48e112, 0x3fd4135c94176602, // -0.94953, 0.31368 + 0xbfee9f4156c62dda, 0x3fd294062ed59f05, // -0.95694, 0.29028 + 0xbfeed740e7684963, 0x3fd111d262b1f677, // -0.96378, 0.26671 + 0xbfef0a7efb9230d7, 0x3fcf19f97b215f1a, // -0.97003, 0.24298 + 0xbfef38f3ac64e589, 0x3fcc0b826a7e4f63, // -0.9757, 0.2191 + 0xbfef6297cff75cb0, 0x3fc8f8b83c69a60a, // -0.98079, 0.19509 + 0xbfef8764fa714ba9, 0x3fc5e214448b3fc6, // -0.98528, 0.17096 + 0xbfefa7557f08a517, 0x3fc2c8106e8e613a, // -0.98918, 0.14673 + 0xbfefc26470e19fd3, 0x3fbf564e56a9730e, // -0.99248, 0.12241 + 0xbfefd88da3d12526, 0x3fb917a6bc29b42c, // -0.99518, 0.098017 + 0xbfefe9cdad01883a, 0x3fb2d52092ce19f6, // -0.99729, 0.073565 + 0xbfeff621e3796d7e, 0x3fa91f65f10dd814, // -0.9988, 0.049068 + 0xbfeffd886084cd0d, 0x3f992155f7a3667e, // -0.9997, 0.024541 + 0xbff0000000000000, 0x0000000000000000, // -1, 0 + 0xbfeffd886084cd0d, 0xbf992155f7a3667e, // -0.9997,-0.024541 + 0xbfeff621e3796d7e, 0xbfa91f65f10dd814, // -0.9988,-0.049068 + 0xbfefe9cdad01883a, 0xbfb2d52092ce19f6, // -0.99729,-0.073565 + 0xbfefd88da3d12526, 0xbfb917a6bc29b42c, // -0.99518,-0.098017 + 0xbfefc26470e19fd3, 0xbfbf564e56a9730e, // -0.99248, -0.12241 + 0xbfefa7557f08a517, 0xbfc2c8106e8e613a, // -0.98918, -0.14673 + 0xbfef8764fa714ba9, 0xbfc5e214448b3fc6, // -0.98528, -0.17096 + 0xbfef6297cff75cb0, 0xbfc8f8b83c69a60a, // -0.98079, -0.19509 + 0xbfef38f3ac64e589, 0xbfcc0b826a7e4f63, // -0.9757, -0.2191 + 0xbfef0a7efb9230d7, 0xbfcf19f97b215f1a, // -0.97003, -0.24298 + 0xbfeed740e7684963, 0xbfd111d262b1f677, // -0.96378, -0.26671 + 0xbfee9f4156c62dda, 0xbfd294062ed59f05, // -0.95694, -0.29028 + 0xbfee6288ec48e112, 0xbfd4135c94176602, // -0.94953, -0.31368 + 0xbfee212104f686e5, 0xbfd58f9a75ab1fdd, // -0.94154, -0.33689 + 0xbfeddb13b6ccc23d, 0xbfd7088530fa459e, // -0.93299, -0.3599 + 0xbfed906bcf328d46, 0xbfd87de2a6aea963, // -0.92388, -0.38268 + 0xbfed4134d14dc93a, 0xbfd9ef7943a8ed8a, // -0.91421, -0.40524 + 0xbfeced7af43cc773, 0xbfdb5d1009e15cc0, // -0.90399, -0.42756 + 0xbfec954b213411f5, 0xbfdcc66e9931c45d, // -0.89322, -0.44961 + 0xbfec38b2f180bdb1, 0xbfde2b5d3806f63b, // -0.88192, -0.4714 + 0xbfebd7c0ac6f952a, 0xbfdf8ba4dbf89aba, // -0.87009, -0.4929 + 0xbfeb728345196e3e, 0xbfe073879922ffed, // -0.85773, -0.5141 + 0xbfeb090a58150200, 0xbfe11eb3541b4b22, // -0.84485, -0.535 + 0xbfea9b66290ea1a3, 0xbfe1c73b39ae68c8, // -0.83147, -0.55557 + 0xbfea29a7a0462782, 0xbfe26d054cdd12df, // -0.81758, -0.57581 + 0xbfe9b3e047f38741, 0xbfe30ff7fce17035, // -0.80321, -0.5957 + 0xbfe93a22499263fc, 0xbfe3affa292050b9, // -0.78835, -0.61523 + 0xbfe8bc806b151741, 0xbfe44cf325091dd6, // -0.77301, -0.63439 + 0xbfe83b0e0bff976e, 0xbfe4e6cabbe3e5e9, // -0.75721, -0.65317 + 0xbfe7b5df226aafb0, 0xbfe57d69348cec9f, // -0.74095, -0.67156 + 0xbfe72d0837efff97, 0xbfe610b7551d2cde, // -0.72425, -0.68954 + 0xbfe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // -0.70711, -0.70711 + 0xbfe610b7551d2cde, 0xbfe72d0837efff97, // -0.68954, -0.72425 + 0xbfe57d69348cec9f, 0xbfe7b5df226aafb0, // -0.67156, -0.74095 + 0xbfe4e6cabbe3e5e9, 0xbfe83b0e0bff976e, // -0.65317, -0.75721 + 0xbfe44cf325091dd6, 0xbfe8bc806b151741, // -0.63439, -0.77301 + 0xbfe3affa292050b9, 0xbfe93a22499263fc, // -0.61523, -0.78835 + 0xbfe30ff7fce17035, 0xbfe9b3e047f38741, // -0.5957, -0.80321 + 0xbfe26d054cdd12df, 0xbfea29a7a0462782, // -0.57581, -0.81758 + 0xbfe1c73b39ae68c8, 0xbfea9b66290ea1a3, // -0.55557, -0.83147 + 0xbfe11eb3541b4b22, 0xbfeb090a58150200, // -0.535, -0.84485 + 0xbfe073879922ffed, 0xbfeb728345196e3e, // -0.5141, -0.85773 + 0xbfdf8ba4dbf89aba, 0xbfebd7c0ac6f952a, // -0.4929, -0.87009 + 0xbfde2b5d3806f63b, 0xbfec38b2f180bdb1, // -0.4714, -0.88192 + 0xbfdcc66e9931c45d, 0xbfec954b213411f5, // -0.44961, -0.89322 + 0xbfdb5d1009e15cc0, 0xbfeced7af43cc773, // -0.42756, -0.90399 + 0xbfd9ef7943a8ed8a, 0xbfed4134d14dc93a, // -0.40524, -0.91421 + 0xbfd87de2a6aea963, 0xbfed906bcf328d46, // -0.38268, -0.92388 + 0xbfd7088530fa459e, 0xbfeddb13b6ccc23d, // -0.3599, -0.93299 + 0xbfd58f9a75ab1fdd, 0xbfee212104f686e5, // -0.33689, -0.94154 + 0xbfd4135c94176602, 0xbfee6288ec48e112, // -0.31368, -0.94953 + 0xbfd294062ed59f05, 0xbfee9f4156c62dda, // -0.29028, -0.95694 + 0xbfd111d262b1f677, 0xbfeed740e7684963, // -0.26671, -0.96378 + 0xbfcf19f97b215f1a, 0xbfef0a7efb9230d7, // -0.24298, -0.97003 + 0xbfcc0b826a7e4f63, 0xbfef38f3ac64e589, // -0.2191, -0.9757 + 0xbfc8f8b83c69a60a, 0xbfef6297cff75cb0, // -0.19509, -0.98079 + 0xbfc5e214448b3fc6, 0xbfef8764fa714ba9, // -0.17096, -0.98528 + 0xbfc2c8106e8e613a, 0xbfefa7557f08a517, // -0.14673, -0.98918 + 0xbfbf564e56a9730e, 0xbfefc26470e19fd3, // -0.12241, -0.99248 + 0xbfb917a6bc29b42c, 0xbfefd88da3d12526, //-0.098017, -0.99518 + 0xbfb2d52092ce19f6, 0xbfefe9cdad01883a, //-0.073565, -0.99729 + 0xbfa91f65f10dd814, 0xbfeff621e3796d7e, //-0.049068, -0.9988 + 0xbf992155f7a3667e, 0xbfeffd886084cd0d, //-0.024541, -0.9997 + 0x0000000000000000, 0xbff0000000000000, // 0, -1 + 0x3f992155f7a3667e, 0xbfeffd886084cd0d, // 0.024541, -0.9997 + 0x3fa91f65f10dd814, 0xbfeff621e3796d7e, // 0.049068, -0.9988 + 0x3fb2d52092ce19f6, 0xbfefe9cdad01883a, // 0.073565, -0.99729 + 0x3fb917a6bc29b42c, 0xbfefd88da3d12526, // 0.098017, -0.99518 + 0x3fbf564e56a9730e, 0xbfefc26470e19fd3, // 0.12241, -0.99248 + 0x3fc2c8106e8e613a, 0xbfefa7557f08a517, // 0.14673, -0.98918 + 0x3fc5e214448b3fc6, 0xbfef8764fa714ba9, // 0.17096, -0.98528 + 0x3fc8f8b83c69a60a, 0xbfef6297cff75cb0, // 0.19509, -0.98079 + 0x3fcc0b826a7e4f63, 0xbfef38f3ac64e589, // 0.2191, -0.9757 + 0x3fcf19f97b215f1a, 0xbfef0a7efb9230d7, // 0.24298, -0.97003 + 0x3fd111d262b1f677, 0xbfeed740e7684963, // 0.26671, -0.96378 + 0x3fd294062ed59f05, 0xbfee9f4156c62dda, // 0.29028, -0.95694 + 0x3fd4135c94176602, 0xbfee6288ec48e112, // 0.31368, -0.94953 + 0x3fd58f9a75ab1fdd, 0xbfee212104f686e5, // 0.33689, -0.94154 + 0x3fd7088530fa459e, 0xbfeddb13b6ccc23d, // 0.3599, -0.93299 + 0x3fd87de2a6aea963, 0xbfed906bcf328d46, // 0.38268, -0.92388 + 0x3fd9ef7943a8ed8a, 0xbfed4134d14dc93a, // 0.40524, -0.91421 + 0x3fdb5d1009e15cc0, 0xbfeced7af43cc773, // 0.42756, -0.90399 + 0x3fdcc66e9931c45d, 0xbfec954b213411f5, // 0.44961, -0.89322 + 0x3fde2b5d3806f63b, 0xbfec38b2f180bdb1, // 0.4714, -0.88192 + 0x3fdf8ba4dbf89aba, 0xbfebd7c0ac6f952a, // 0.4929, -0.87009 + 0x3fe073879922ffed, 0xbfeb728345196e3e, // 0.5141, -0.85773 + 0x3fe11eb3541b4b22, 0xbfeb090a58150200, // 0.535, -0.84485 + 0x3fe1c73b39ae68c8, 0xbfea9b66290ea1a3, // 0.55557, -0.83147 + 0x3fe26d054cdd12df, 0xbfea29a7a0462782, // 0.57581, -0.81758 + 0x3fe30ff7fce17035, 0xbfe9b3e047f38741, // 0.5957, -0.80321 + 0x3fe3affa292050b9, 0xbfe93a22499263fc, // 0.61523, -0.78835 + 0x3fe44cf325091dd6, 0xbfe8bc806b151741, // 0.63439, -0.77301 + 0x3fe4e6cabbe3e5e9, 0xbfe83b0e0bff976e, // 0.65317, -0.75721 + 0x3fe57d69348cec9f, 0xbfe7b5df226aafb0, // 0.67156, -0.74095 + 0x3fe610b7551d2cde, 0xbfe72d0837efff97, // 0.68954, -0.72425 + 0x3fe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // 0.70711, -0.70711 + 0x3fe72d0837efff97, 0xbfe610b7551d2cde, // 0.72425, -0.68954 + 0x3fe7b5df226aafb0, 0xbfe57d69348cec9f, // 0.74095, -0.67156 + 0x3fe83b0e0bff976e, 0xbfe4e6cabbe3e5e9, // 0.75721, -0.65317 + 0x3fe8bc806b151741, 0xbfe44cf325091dd6, // 0.77301, -0.63439 + 0x3fe93a22499263fc, 0xbfe3affa292050b9, // 0.78835, -0.61523 + 0x3fe9b3e047f38741, 0xbfe30ff7fce17035, // 0.80321, -0.5957 + 0x3fea29a7a0462782, 0xbfe26d054cdd12df, // 0.81758, -0.57581 + 0x3fea9b66290ea1a3, 0xbfe1c73b39ae68c8, // 0.83147, -0.55557 + 0x3feb090a58150200, 0xbfe11eb3541b4b22, // 0.84485, -0.535 + 0x3feb728345196e3e, 0xbfe073879922ffed, // 0.85773, -0.5141 + 0x3febd7c0ac6f952a, 0xbfdf8ba4dbf89aba, // 0.87009, -0.4929 + 0x3fec38b2f180bdb1, 0xbfde2b5d3806f63b, // 0.88192, -0.4714 + 0x3fec954b213411f5, 0xbfdcc66e9931c45d, // 0.89322, -0.44961 + 0x3feced7af43cc773, 0xbfdb5d1009e15cc0, // 0.90399, -0.42756 + 0x3fed4134d14dc93a, 0xbfd9ef7943a8ed8a, // 0.91421, -0.40524 + 0x3fed906bcf328d46, 0xbfd87de2a6aea963, // 0.92388, -0.38268 + 0x3feddb13b6ccc23d, 0xbfd7088530fa459e, // 0.93299, -0.3599 + 0x3fee212104f686e5, 0xbfd58f9a75ab1fdd, // 0.94154, -0.33689 + 0x3fee6288ec48e112, 0xbfd4135c94176602, // 0.94953, -0.31368 + 0x3fee9f4156c62dda, 0xbfd294062ed59f05, // 0.95694, -0.29028 + 0x3feed740e7684963, 0xbfd111d262b1f677, // 0.96378, -0.26671 + 0x3fef0a7efb9230d7, 0xbfcf19f97b215f1a, // 0.97003, -0.24298 + 0x3fef38f3ac64e589, 0xbfcc0b826a7e4f63, // 0.9757, -0.2191 + 0x3fef6297cff75cb0, 0xbfc8f8b83c69a60a, // 0.98079, -0.19509 + 0x3fef8764fa714ba9, 0xbfc5e214448b3fc6, // 0.98528, -0.17096 + 0x3fefa7557f08a517, 0xbfc2c8106e8e613a, // 0.98918, -0.14673 + 0x3fefc26470e19fd3, 0xbfbf564e56a9730e, // 0.99248, -0.12241 + 0x3fefd88da3d12526, 0xbfb917a6bc29b42c, // 0.99518,-0.098017 + 0x3fefe9cdad01883a, 0xbfb2d52092ce19f6, // 0.99729,-0.073565 + 0x3feff621e3796d7e, 0xbfa91f65f10dd814, // 0.9988,-0.049068 + 0x3feffd886084cd0d, 0xbf992155f7a3667e, // 0.9997,-0.024541 +}; + +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_F64_512) +/** + @par + Example code for Double Precision Floating-point Twiddle factors Generation: + @par + 
for (i = 0; i< N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/(float)N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 512, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const uint64_t twiddleCoefF64_512[1024] = { + 0x3ff0000000000000, 0x0000000000000000, // 1, 0 + 0x3fefff62169b92db, 0x3f8921d1fcdec784, // 0.99992, 0.012272 + 0x3feffd886084cd0d, 0x3f992155f7a3667e, // 0.9997, 0.024541 + 0x3feffa72effef75d, 0x3fa2d865759455cd, // 0.99932, 0.036807 + 0x3feff621e3796d7e, 0x3fa91f65f10dd814, // 0.9988, 0.049068 + 0x3feff095658e71ad, 0x3faf656e79f820e0, // 0.99812, 0.061321 + 0x3fefe9cdad01883a, 0x3fb2d52092ce19f6, // 0.99729, 0.073565 + 0x3fefe1cafcbd5b09, 0x3fb5f6d00a9aa419, // 0.99631, 0.085797 + 0x3fefd88da3d12526, 0x3fb917a6bc29b42c, // 0.99518, 0.098017 + 0x3fefce15fd6da67b, 0x3fbc3785c79ec2d5, // 0.99391, 0.11022 + 0x3fefc26470e19fd3, 0x3fbf564e56a9730e, // 0.99248, 0.12241 + 0x3fefb5797195d741, 0x3fc139f0cedaf576, // 0.9909, 0.13458 + 0x3fefa7557f08a517, 0x3fc2c8106e8e613a, // 0.98918, 0.14673 + 0x3fef97f924c9099b, 0x3fc45576b1293e5a, // 0.9873, 0.15886 + 0x3fef8764fa714ba9, 0x3fc5e214448b3fc6, // 0.98528, 0.17096 + 0x3fef7599a3a12077, 0x3fc76dd9de50bf31, // 0.98311, 0.18304 + 0x3fef6297cff75cb0, 0x3fc8f8b83c69a60a, // 0.98079, 0.19509 + 0x3fef4e603b0b2f2d, 0x3fca82a025b00451, // 0.97832, 0.20711 + 0x3fef38f3ac64e589, 0x3fcc0b826a7e4f63, // 0.9757, 0.2191 + 0x3fef2252f7763ada, 0x3fcd934fe5454311, // 0.97294, 0.23106 + 0x3fef0a7efb9230d7, 0x3fcf19f97b215f1a, // 0.97003, 0.24298 + 0x3feef178a3e473c2, 0x3fd04fb80e37fdae, // 0.96698, 0.25487 + 0x3feed740e7684963, 0x3fd111d262b1f677, // 0.96378, 0.26671 + 0x3feebbd8c8df0b74, 0x3fd1d3443f4cdb3d, // 0.96043, 0.27852 + 0x3fee9f4156c62dda, 0x3fd294062ed59f05, // 0.95694, 0.29028 + 0x3fee817bab4cd10d, 0x3fd35410c2e18152, // 0.95331, 0.30201 + 0x3fee6288ec48e112, 0x3fd4135c94176602, // 0.94953, 0.31368 + 0x3fee426a4b2bc17e, 0x3fd4d1e24278e76a, // 0.94561, 0.32531 + 0x3fee212104f686e5, 0x3fd58f9a75ab1fdd, // 0.94154, 0.33689 + 0x3fedfeae622dbe2b, 0x3fd64c7ddd3f27c6, // 0.93734, 0.34842 + 0x3feddb13b6ccc23d, 0x3fd7088530fa459e, // 0.93299, 0.3599 + 0x3fedb6526238a09b, 0x3fd7c3a9311dcce7, // 0.92851, 0.37132 + 0x3fed906bcf328d46, 0x3fd87de2a6aea963, // 0.92388, 0.38268 + 0x3fed696173c9e68b, 0x3fd9372a63bc93d7, // 0.91911, 0.39399 + 0x3fed4134d14dc93a, 0x3fd9ef7943a8ed8a, // 0.91421, 0.40524 + 0x3fed17e7743e35dc, 0x3fdaa6c82b6d3fc9, // 0.90917, 0.41643 + 0x3feced7af43cc773, 0x3fdb5d1009e15cc0, // 0.90399, 0.42756 + 0x3fecc1f0f3fcfc5c, 0x3fdc1249d8011ee7, // 0.89867, 0.43862 + 0x3fec954b213411f5, 0x3fdcc66e9931c45d, // 0.89322, 0.44961 + 0x3fec678b3488739b, 0x3fdd79775b86e389, // 0.88764, 0.46054 + 0x3fec38b2f180bdb1, 0x3fde2b5d3806f63b, // 0.88192, 0.4714 + 0x3fec08c426725549, 0x3fdedc1952ef78d5, // 0.87607, 0.48218 + 0x3febd7c0ac6f952a, 0x3fdf8ba4dbf89aba, // 0.87009, 0.4929 + 0x3feba5aa673590d2, 0x3fe01cfc874c3eb7, // 0.86397, 0.50354 + 0x3feb728345196e3e, 0x3fe073879922ffed, // 0.85773, 0.5141 + 0x3feb3e4d3ef55712, 0x3fe0c9704d5d898f, // 0.85136, 0.52459 + 0x3feb090a58150200, 0x3fe11eb3541b4b22, // 0.84485, 0.535 + 0x3fead2bc9e21d511, 0x3fe1734d63dedb49, // 0.83822, 0.54532 + 0x3fea9b66290ea1a3, 0x3fe1c73b39ae68c8, // 0.83147, 0.55557 + 0x3fea63091b02fae2, 0x3fe21a799933eb58, // 0.82459, 0.56573 + 0x3fea29a7a0462782, 0x3fe26d054cdd12df, // 0.81758, 0.57581 + 0x3fe9ef43ef29af94, 0x3fe2bedb25faf3ea, // 0.81046, 0.5858 + 0x3fe9b3e047f38741, 0x3fe30ff7fce17035, // 0.80321, 0.5957 + 0x3fe9777ef4c7d742, 0x3fe36058b10659f3, // 0.79584, 0.60551 + 0x3fe93a22499263fc, 0x3fe3affa292050b9, // 0.78835, 0.61523 + 0x3fe8fbcca3ef940d, 0x3fe3fed9534556d4, // 0.78074, 0.62486 + 0x3fe8bc806b151741, 0x3fe44cf325091dd6, // 0.77301, 0.63439 + 0x3fe87c400fba2ebf, 0x3fe49a449b9b0938, // 0.76517, 0.64383 + 0x3fe83b0e0bff976e, 0x3fe4e6cabbe3e5e9, // 0.75721, 0.65317 + 0x3fe7f8ece3571771, 0x3fe5328292a35596, // 0.74914, 0.66242 + 0x3fe7b5df226aafb0, 0x3fe57d69348cec9f, // 0.74095, 0.67156 + 0x3fe771e75f037261, 0x3fe5c77bbe65018c, // 0.73265, 0.6806 + 0x3fe72d0837efff97, 0x3fe610b7551d2cde, // 0.72425, 0.68954 + 0x3fe6e74454eaa8ae, 0x3fe6591925f0783e, // 0.71573, 0.69838 + 0x3fe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // 0.70711, 0.70711 + 0x3fe6591925f0783e, 0x3fe6e74454eaa8ae, // 0.69838, 0.71573 + 0x3fe610b7551d2cde, 0x3fe72d0837efff97, // 0.68954, 0.72425 + 0x3fe5c77bbe65018c, 0x3fe771e75f037261, // 0.6806, 0.73265 + 0x3fe57d69348cec9f, 0x3fe7b5df226aafb0, // 0.67156, 0.74095 + 0x3fe5328292a35596, 0x3fe7f8ece3571771, // 0.66242, 0.74914 + 0x3fe4e6cabbe3e5e9, 0x3fe83b0e0bff976e, // 0.65317, 0.75721 + 0x3fe49a449b9b0938, 0x3fe87c400fba2ebf, // 0.64383, 0.76517 + 0x3fe44cf325091dd6, 0x3fe8bc806b151741, // 0.63439, 0.77301 + 0x3fe3fed9534556d4, 0x3fe8fbcca3ef940d, // 0.62486, 0.78074 + 0x3fe3affa292050b9, 0x3fe93a22499263fc, // 0.61523, 0.78835 + 0x3fe36058b10659f3, 0x3fe9777ef4c7d742, // 0.60551, 0.79584 + 0x3fe30ff7fce17035, 0x3fe9b3e047f38741, // 0.5957, 0.80321 + 0x3fe2bedb25faf3ea, 0x3fe9ef43ef29af94, // 0.5858, 0.81046 + 0x3fe26d054cdd12df, 0x3fea29a7a0462782, // 0.57581, 0.81758 + 0x3fe21a799933eb58, 0x3fea63091b02fae2, // 0.56573, 0.82459 + 0x3fe1c73b39ae68c8, 0x3fea9b66290ea1a3, // 0.55557, 0.83147 + 0x3fe1734d63dedb49, 0x3fead2bc9e21d511, // 0.54532, 0.83822 + 0x3fe11eb3541b4b22, 0x3feb090a58150200, // 0.535, 0.84485 + 0x3fe0c9704d5d898f, 0x3feb3e4d3ef55712, // 0.52459, 0.85136 + 0x3fe073879922ffed, 0x3feb728345196e3e, // 0.5141, 0.85773 + 0x3fe01cfc874c3eb7, 0x3feba5aa673590d2, // 0.50354, 0.86397 + 0x3fdf8ba4dbf89aba, 0x3febd7c0ac6f952a, // 0.4929, 0.87009 + 0x3fdedc1952ef78d5, 0x3fec08c426725549, // 0.48218, 0.87607 + 0x3fde2b5d3806f63b, 0x3fec38b2f180bdb1, // 0.4714, 0.88192 + 0x3fdd79775b86e389, 0x3fec678b3488739b, // 0.46054, 0.88764 + 0x3fdcc66e9931c45d, 0x3fec954b213411f5, // 0.44961, 0.89322 + 0x3fdc1249d8011ee7, 0x3fecc1f0f3fcfc5c, // 0.43862, 0.89867 + 0x3fdb5d1009e15cc0, 0x3feced7af43cc773, // 0.42756, 0.90399 + 0x3fdaa6c82b6d3fc9, 0x3fed17e7743e35dc, // 0.41643, 0.90917 + 0x3fd9ef7943a8ed8a, 0x3fed4134d14dc93a, // 0.40524, 0.91421 + 0x3fd9372a63bc93d7, 0x3fed696173c9e68b, // 0.39399, 0.91911 + 0x3fd87de2a6aea963, 0x3fed906bcf328d46, // 0.38268, 0.92388 + 0x3fd7c3a9311dcce7, 0x3fedb6526238a09b, // 0.37132, 0.92851 + 0x3fd7088530fa459e, 0x3feddb13b6ccc23d, // 0.3599, 0.93299 + 0x3fd64c7ddd3f27c6, 0x3fedfeae622dbe2b, // 0.34842, 0.93734 + 0x3fd58f9a75ab1fdd, 0x3fee212104f686e5, // 0.33689, 0.94154 + 0x3fd4d1e24278e76a, 0x3fee426a4b2bc17e, // 0.32531, 0.94561 + 0x3fd4135c94176602, 0x3fee6288ec48e112, // 0.31368, 0.94953 + 0x3fd35410c2e18152, 0x3fee817bab4cd10d, // 0.30201, 0.95331 + 0x3fd294062ed59f05, 0x3fee9f4156c62dda, // 0.29028, 0.95694 + 0x3fd1d3443f4cdb3d, 0x3feebbd8c8df0b74, // 0.27852, 0.96043 + 0x3fd111d262b1f677, 0x3feed740e7684963, // 0.26671, 0.96378 + 0x3fd04fb80e37fdae, 0x3feef178a3e473c2, // 0.25487, 0.96698 + 0x3fcf19f97b215f1a, 0x3fef0a7efb9230d7, // 0.24298, 0.97003 + 0x3fcd934fe5454311, 0x3fef2252f7763ada, // 0.23106, 0.97294 + 0x3fcc0b826a7e4f63, 0x3fef38f3ac64e589, // 0.2191, 0.9757 + 0x3fca82a025b00451, 0x3fef4e603b0b2f2d, // 0.20711, 0.97832 + 0x3fc8f8b83c69a60a, 0x3fef6297cff75cb0, // 0.19509, 0.98079 + 0x3fc76dd9de50bf31, 0x3fef7599a3a12077, // 0.18304, 0.98311 + 0x3fc5e214448b3fc6, 0x3fef8764fa714ba9, // 0.17096, 0.98528 + 0x3fc45576b1293e5a, 0x3fef97f924c9099b, // 0.15886, 0.9873 + 0x3fc2c8106e8e613a, 0x3fefa7557f08a517, // 0.14673, 0.98918 + 0x3fc139f0cedaf576, 0x3fefb5797195d741, // 0.13458, 0.9909 + 0x3fbf564e56a9730e, 0x3fefc26470e19fd3, // 0.12241, 0.99248 + 0x3fbc3785c79ec2d5, 0x3fefce15fd6da67b, // 0.11022, 0.99391 + 0x3fb917a6bc29b42c, 0x3fefd88da3d12526, // 0.098017, 0.99518 + 0x3fb5f6d00a9aa419, 0x3fefe1cafcbd5b09, // 0.085797, 0.99631 + 0x3fb2d52092ce19f6, 0x3fefe9cdad01883a, // 0.073565, 0.99729 + 0x3faf656e79f820e0, 0x3feff095658e71ad, // 0.061321, 0.99812 + 0x3fa91f65f10dd814, 0x3feff621e3796d7e, // 0.049068, 0.9988 + 0x3fa2d865759455cd, 0x3feffa72effef75d, // 0.036807, 0.99932 + 0x3f992155f7a3667e, 0x3feffd886084cd0d, // 0.024541, 0.9997 + 0x3f8921d1fcdec784, 0x3fefff62169b92db, // 0.012272, 0.99992 + 0x0000000000000000, 0x3ff0000000000000, // 0, 1 + 0xbf8921d1fcdec784, 0x3fefff62169b92db, //-0.012272, 0.99992 + 0xbf992155f7a3667e, 0x3feffd886084cd0d, //-0.024541, 0.9997 + 0xbfa2d865759455cd, 0x3feffa72effef75d, //-0.036807, 0.99932 + 0xbfa91f65f10dd814, 0x3feff621e3796d7e, //-0.049068, 0.9988 + 0xbfaf656e79f820e0, 0x3feff095658e71ad, //-0.061321, 0.99812 + 0xbfb2d52092ce19f6, 0x3fefe9cdad01883a, //-0.073565, 0.99729 + 0xbfb5f6d00a9aa419, 0x3fefe1cafcbd5b09, //-0.085797, 0.99631 + 0xbfb917a6bc29b42c, 0x3fefd88da3d12526, //-0.098017, 0.99518 + 0xbfbc3785c79ec2d5, 0x3fefce15fd6da67b, // -0.11022, 0.99391 + 0xbfbf564e56a9730e, 0x3fefc26470e19fd3, // -0.12241, 0.99248 + 0xbfc139f0cedaf576, 0x3fefb5797195d741, // -0.13458, 0.9909 + 0xbfc2c8106e8e613a, 0x3fefa7557f08a517, // -0.14673, 0.98918 + 0xbfc45576b1293e5a, 0x3fef97f924c9099b, // -0.15886, 0.9873 + 0xbfc5e214448b3fc6, 0x3fef8764fa714ba9, // -0.17096, 0.98528 + 0xbfc76dd9de50bf31, 0x3fef7599a3a12077, // -0.18304, 0.98311 + 0xbfc8f8b83c69a60a, 0x3fef6297cff75cb0, // -0.19509, 0.98079 + 0xbfca82a025b00451, 0x3fef4e603b0b2f2d, // -0.20711, 0.97832 + 0xbfcc0b826a7e4f63, 0x3fef38f3ac64e589, // -0.2191, 0.9757 + 0xbfcd934fe5454311, 0x3fef2252f7763ada, // -0.23106, 0.97294 + 0xbfcf19f97b215f1a, 0x3fef0a7efb9230d7, // -0.24298, 0.97003 + 0xbfd04fb80e37fdae, 0x3feef178a3e473c2, // -0.25487, 0.96698 + 0xbfd111d262b1f677, 0x3feed740e7684963, // -0.26671, 0.96378 + 0xbfd1d3443f4cdb3d, 0x3feebbd8c8df0b74, // -0.27852, 0.96043 + 0xbfd294062ed59f05, 0x3fee9f4156c62dda, // -0.29028, 0.95694 + 0xbfd35410c2e18152, 0x3fee817bab4cd10d, // -0.30201, 0.95331 + 0xbfd4135c94176602, 0x3fee6288ec48e112, // -0.31368, 0.94953 + 0xbfd4d1e24278e76a, 0x3fee426a4b2bc17e, // -0.32531, 0.94561 + 0xbfd58f9a75ab1fdd, 0x3fee212104f686e5, // -0.33689, 0.94154 + 0xbfd64c7ddd3f27c6, 0x3fedfeae622dbe2b, // -0.34842, 0.93734 + 0xbfd7088530fa459e, 0x3feddb13b6ccc23d, // -0.3599, 0.93299 + 0xbfd7c3a9311dcce7, 0x3fedb6526238a09b, // -0.37132, 0.92851 + 0xbfd87de2a6aea963, 0x3fed906bcf328d46, // -0.38268, 0.92388 + 0xbfd9372a63bc93d7, 0x3fed696173c9e68b, // -0.39399, 0.91911 + 0xbfd9ef7943a8ed8a, 0x3fed4134d14dc93a, // -0.40524, 0.91421 + 0xbfdaa6c82b6d3fc9, 0x3fed17e7743e35dc, // -0.41643, 0.90917 + 0xbfdb5d1009e15cc0, 0x3feced7af43cc773, // -0.42756, 0.90399 + 0xbfdc1249d8011ee7, 0x3fecc1f0f3fcfc5c, // -0.43862, 0.89867 + 0xbfdcc66e9931c45d, 0x3fec954b213411f5, // -0.44961, 0.89322 + 0xbfdd79775b86e389, 0x3fec678b3488739b, // -0.46054, 0.88764 + 0xbfde2b5d3806f63b, 0x3fec38b2f180bdb1, // -0.4714, 0.88192 + 0xbfdedc1952ef78d5, 0x3fec08c426725549, // -0.48218, 0.87607 + 0xbfdf8ba4dbf89aba, 0x3febd7c0ac6f952a, // -0.4929, 0.87009 + 0xbfe01cfc874c3eb7, 0x3feba5aa673590d2, // -0.50354, 0.86397 + 0xbfe073879922ffed, 0x3feb728345196e3e, // -0.5141, 0.85773 + 0xbfe0c9704d5d898f, 0x3feb3e4d3ef55712, // -0.52459, 0.85136 + 0xbfe11eb3541b4b22, 0x3feb090a58150200, // -0.535, 0.84485 + 0xbfe1734d63dedb49, 0x3fead2bc9e21d511, // -0.54532, 0.83822 + 0xbfe1c73b39ae68c8, 0x3fea9b66290ea1a3, // -0.55557, 0.83147 + 0xbfe21a799933eb58, 0x3fea63091b02fae2, // -0.56573, 0.82459 + 0xbfe26d054cdd12df, 0x3fea29a7a0462782, // -0.57581, 0.81758 + 0xbfe2bedb25faf3ea, 0x3fe9ef43ef29af94, // -0.5858, 0.81046 + 0xbfe30ff7fce17035, 0x3fe9b3e047f38741, // -0.5957, 0.80321 + 0xbfe36058b10659f3, 0x3fe9777ef4c7d742, // -0.60551, 0.79584 + 0xbfe3affa292050b9, 0x3fe93a22499263fc, // -0.61523, 0.78835 + 0xbfe3fed9534556d4, 0x3fe8fbcca3ef940d, // -0.62486, 0.78074 + 0xbfe44cf325091dd6, 0x3fe8bc806b151741, // -0.63439, 0.77301 + 0xbfe49a449b9b0938, 0x3fe87c400fba2ebf, // -0.64383, 0.76517 + 0xbfe4e6cabbe3e5e9, 0x3fe83b0e0bff976e, // -0.65317, 0.75721 + 0xbfe5328292a35596, 0x3fe7f8ece3571771, // -0.66242, 0.74914 + 0xbfe57d69348cec9f, 0x3fe7b5df226aafb0, // -0.67156, 0.74095 + 0xbfe5c77bbe65018c, 0x3fe771e75f037261, // -0.6806, 0.73265 + 0xbfe610b7551d2cde, 0x3fe72d0837efff97, // -0.68954, 0.72425 + 0xbfe6591925f0783e, 0x3fe6e74454eaa8ae, // -0.69838, 0.71573 + 0xbfe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // -0.70711, 0.70711 + 0xbfe6e74454eaa8ae, 0x3fe6591925f0783e, // -0.71573, 0.69838 + 0xbfe72d0837efff97, 0x3fe610b7551d2cde, // -0.72425, 0.68954 + 0xbfe771e75f037261, 0x3fe5c77bbe65018c, // -0.73265, 0.6806 + 0xbfe7b5df226aafb0, 0x3fe57d69348cec9f, // -0.74095, 0.67156 + 0xbfe7f8ece3571771, 0x3fe5328292a35596, // -0.74914, 0.66242 + 0xbfe83b0e0bff976e, 0x3fe4e6cabbe3e5e9, // -0.75721, 0.65317 + 0xbfe87c400fba2ebf, 0x3fe49a449b9b0938, // -0.76517, 0.64383 + 0xbfe8bc806b151741, 0x3fe44cf325091dd6, // -0.77301, 0.63439 + 0xbfe8fbcca3ef940d, 0x3fe3fed9534556d4, // -0.78074, 0.62486 + 0xbfe93a22499263fc, 0x3fe3affa292050b9, // -0.78835, 0.61523 + 0xbfe9777ef4c7d742, 0x3fe36058b10659f3, // -0.79584, 0.60551 + 0xbfe9b3e047f38741, 0x3fe30ff7fce17035, // -0.80321, 0.5957 + 0xbfe9ef43ef29af94, 0x3fe2bedb25faf3ea, // -0.81046, 0.5858 + 0xbfea29a7a0462782, 0x3fe26d054cdd12df, // -0.81758, 0.57581 + 0xbfea63091b02fae2, 0x3fe21a799933eb58, // -0.82459, 0.56573 + 0xbfea9b66290ea1a3, 0x3fe1c73b39ae68c8, // -0.83147, 0.55557 + 0xbfead2bc9e21d511, 0x3fe1734d63dedb49, // -0.83822, 0.54532 + 0xbfeb090a58150200, 0x3fe11eb3541b4b22, // -0.84485, 0.535 + 0xbfeb3e4d3ef55712, 0x3fe0c9704d5d898f, // -0.85136, 0.52459 + 0xbfeb728345196e3e, 0x3fe073879922ffed, // -0.85773, 0.5141 + 0xbfeba5aa673590d2, 0x3fe01cfc874c3eb7, // -0.86397, 0.50354 + 0xbfebd7c0ac6f952a, 0x3fdf8ba4dbf89aba, // -0.87009, 0.4929 + 0xbfec08c426725549, 0x3fdedc1952ef78d5, // -0.87607, 0.48218 + 0xbfec38b2f180bdb1, 0x3fde2b5d3806f63b, // -0.88192, 0.4714 + 0xbfec678b3488739b, 0x3fdd79775b86e389, // -0.88764, 0.46054 + 0xbfec954b213411f5, 0x3fdcc66e9931c45d, // -0.89322, 0.44961 + 0xbfecc1f0f3fcfc5c, 0x3fdc1249d8011ee7, // -0.89867, 0.43862 + 0xbfeced7af43cc773, 0x3fdb5d1009e15cc0, // -0.90399, 0.42756 + 0xbfed17e7743e35dc, 0x3fdaa6c82b6d3fc9, // -0.90917, 0.41643 + 0xbfed4134d14dc93a, 0x3fd9ef7943a8ed8a, // -0.91421, 0.40524 + 0xbfed696173c9e68b, 0x3fd9372a63bc93d7, // -0.91911, 0.39399 + 0xbfed906bcf328d46, 0x3fd87de2a6aea963, // -0.92388, 0.38268 + 0xbfedb6526238a09b, 0x3fd7c3a9311dcce7, // -0.92851, 0.37132 + 0xbfeddb13b6ccc23d, 0x3fd7088530fa459e, // -0.93299, 0.3599 + 0xbfedfeae622dbe2b, 0x3fd64c7ddd3f27c6, // -0.93734, 0.34842 + 0xbfee212104f686e5, 0x3fd58f9a75ab1fdd, // -0.94154, 0.33689 + 0xbfee426a4b2bc17e, 0x3fd4d1e24278e76a, // -0.94561, 0.32531 + 0xbfee6288ec48e112, 0x3fd4135c94176602, // -0.94953, 0.31368 + 0xbfee817bab4cd10d, 0x3fd35410c2e18152, // -0.95331, 0.30201 + 0xbfee9f4156c62dda, 0x3fd294062ed59f05, // -0.95694, 0.29028 + 0xbfeebbd8c8df0b74, 0x3fd1d3443f4cdb3d, // -0.96043, 0.27852 + 0xbfeed740e7684963, 0x3fd111d262b1f677, // -0.96378, 0.26671 + 0xbfeef178a3e473c2, 0x3fd04fb80e37fdae, // -0.96698, 0.25487 + 0xbfef0a7efb9230d7, 0x3fcf19f97b215f1a, // -0.97003, 0.24298 + 0xbfef2252f7763ada, 0x3fcd934fe5454311, // -0.97294, 0.23106 + 0xbfef38f3ac64e589, 0x3fcc0b826a7e4f63, // -0.9757, 0.2191 + 0xbfef4e603b0b2f2d, 0x3fca82a025b00451, // -0.97832, 0.20711 + 0xbfef6297cff75cb0, 0x3fc8f8b83c69a60a, // -0.98079, 0.19509 + 0xbfef7599a3a12077, 0x3fc76dd9de50bf31, // -0.98311, 0.18304 + 0xbfef8764fa714ba9, 0x3fc5e214448b3fc6, // -0.98528, 0.17096 + 0xbfef97f924c9099b, 0x3fc45576b1293e5a, // -0.9873, 0.15886 + 0xbfefa7557f08a517, 0x3fc2c8106e8e613a, // -0.98918, 0.14673 + 0xbfefb5797195d741, 0x3fc139f0cedaf576, // -0.9909, 0.13458 + 0xbfefc26470e19fd3, 0x3fbf564e56a9730e, // -0.99248, 0.12241 + 0xbfefce15fd6da67b, 0x3fbc3785c79ec2d5, // -0.99391, 0.11022 + 0xbfefd88da3d12526, 0x3fb917a6bc29b42c, // -0.99518, 0.098017 + 0xbfefe1cafcbd5b09, 0x3fb5f6d00a9aa419, // -0.99631, 0.085797 + 0xbfefe9cdad01883a, 0x3fb2d52092ce19f6, // -0.99729, 0.073565 + 0xbfeff095658e71ad, 0x3faf656e79f820e0, // -0.99812, 0.061321 + 0xbfeff621e3796d7e, 0x3fa91f65f10dd814, // -0.9988, 0.049068 + 0xbfeffa72effef75d, 0x3fa2d865759455cd, // -0.99932, 0.036807 + 0xbfeffd886084cd0d, 0x3f992155f7a3667e, // -0.9997, 0.024541 + 0xbfefff62169b92db, 0x3f8921d1fcdec784, // -0.99992, 0.012272 + 0xbff0000000000000, 0x0000000000000000, // -1, 0 + 0xbfefff62169b92db, 0xbf8921d1fcdec784, // -0.99992,-0.012272 + 0xbfeffd886084cd0d, 0xbf992155f7a3667e, // -0.9997,-0.024541 + 0xbfeffa72effef75d, 0xbfa2d865759455cd, // -0.99932,-0.036807 + 0xbfeff621e3796d7e, 0xbfa91f65f10dd814, // -0.9988,-0.049068 + 0xbfeff095658e71ad, 0xbfaf656e79f820e0, // -0.99812,-0.061321 + 0xbfefe9cdad01883a, 0xbfb2d52092ce19f6, // -0.99729,-0.073565 + 0xbfefe1cafcbd5b09, 0xbfb5f6d00a9aa419, // -0.99631,-0.085797 + 0xbfefd88da3d12526, 0xbfb917a6bc29b42c, // -0.99518,-0.098017 + 0xbfefce15fd6da67b, 0xbfbc3785c79ec2d5, // -0.99391, -0.11022 + 0xbfefc26470e19fd3, 0xbfbf564e56a9730e, // -0.99248, -0.12241 + 0xbfefb5797195d741, 0xbfc139f0cedaf576, // -0.9909, -0.13458 + 0xbfefa7557f08a517, 0xbfc2c8106e8e613a, // -0.98918, -0.14673 + 0xbfef97f924c9099b, 0xbfc45576b1293e5a, // -0.9873, -0.15886 + 0xbfef8764fa714ba9, 0xbfc5e214448b3fc6, // -0.98528, -0.17096 + 0xbfef7599a3a12077, 0xbfc76dd9de50bf31, // -0.98311, -0.18304 + 0xbfef6297cff75cb0, 0xbfc8f8b83c69a60a, // -0.98079, -0.19509 + 0xbfef4e603b0b2f2d, 0xbfca82a025b00451, // -0.97832, -0.20711 + 0xbfef38f3ac64e589, 0xbfcc0b826a7e4f63, // -0.9757, -0.2191 + 0xbfef2252f7763ada, 0xbfcd934fe5454311, // -0.97294, -0.23106 + 0xbfef0a7efb9230d7, 0xbfcf19f97b215f1a, // -0.97003, -0.24298 + 0xbfeef178a3e473c2, 0xbfd04fb80e37fdae, // -0.96698, -0.25487 + 0xbfeed740e7684963, 0xbfd111d262b1f677, // -0.96378, -0.26671 + 0xbfeebbd8c8df0b74, 0xbfd1d3443f4cdb3d, // -0.96043, -0.27852 + 0xbfee9f4156c62dda, 0xbfd294062ed59f05, // -0.95694, -0.29028 + 0xbfee817bab4cd10d, 0xbfd35410c2e18152, // -0.95331, -0.30201 + 0xbfee6288ec48e112, 0xbfd4135c94176602, // -0.94953, -0.31368 + 0xbfee426a4b2bc17e, 0xbfd4d1e24278e76a, // -0.94561, -0.32531 + 0xbfee212104f686e5, 0xbfd58f9a75ab1fdd, // -0.94154, -0.33689 + 0xbfedfeae622dbe2b, 0xbfd64c7ddd3f27c6, // -0.93734, -0.34842 + 0xbfeddb13b6ccc23d, 0xbfd7088530fa459e, // -0.93299, -0.3599 + 0xbfedb6526238a09b, 0xbfd7c3a9311dcce7, // -0.92851, -0.37132 + 0xbfed906bcf328d46, 0xbfd87de2a6aea963, // -0.92388, -0.38268 + 0xbfed696173c9e68b, 0xbfd9372a63bc93d7, // -0.91911, -0.39399 + 0xbfed4134d14dc93a, 0xbfd9ef7943a8ed8a, // -0.91421, -0.40524 + 0xbfed17e7743e35dc, 0xbfdaa6c82b6d3fc9, // -0.90917, -0.41643 + 0xbfeced7af43cc773, 0xbfdb5d1009e15cc0, // -0.90399, -0.42756 + 0xbfecc1f0f3fcfc5c, 0xbfdc1249d8011ee7, // -0.89867, -0.43862 + 0xbfec954b213411f5, 0xbfdcc66e9931c45d, // -0.89322, -0.44961 + 0xbfec678b3488739b, 0xbfdd79775b86e389, // -0.88764, -0.46054 + 0xbfec38b2f180bdb1, 0xbfde2b5d3806f63b, // -0.88192, -0.4714 + 0xbfec08c426725549, 0xbfdedc1952ef78d5, // -0.87607, -0.48218 + 0xbfebd7c0ac6f952a, 0xbfdf8ba4dbf89aba, // -0.87009, -0.4929 + 0xbfeba5aa673590d2, 0xbfe01cfc874c3eb7, // -0.86397, -0.50354 + 0xbfeb728345196e3e, 0xbfe073879922ffed, // -0.85773, -0.5141 + 0xbfeb3e4d3ef55712, 0xbfe0c9704d5d898f, // -0.85136, -0.52459 + 0xbfeb090a58150200, 0xbfe11eb3541b4b22, // -0.84485, -0.535 + 0xbfead2bc9e21d511, 0xbfe1734d63dedb49, // -0.83822, -0.54532 + 0xbfea9b66290ea1a3, 0xbfe1c73b39ae68c8, // -0.83147, -0.55557 + 0xbfea63091b02fae2, 0xbfe21a799933eb58, // -0.82459, -0.56573 + 0xbfea29a7a0462782, 0xbfe26d054cdd12df, // -0.81758, -0.57581 + 0xbfe9ef43ef29af94, 0xbfe2bedb25faf3ea, // -0.81046, -0.5858 + 0xbfe9b3e047f38741, 0xbfe30ff7fce17035, // -0.80321, -0.5957 + 0xbfe9777ef4c7d742, 0xbfe36058b10659f3, // -0.79584, -0.60551 + 0xbfe93a22499263fc, 0xbfe3affa292050b9, // -0.78835, -0.61523 + 0xbfe8fbcca3ef940d, 0xbfe3fed9534556d4, // -0.78074, -0.62486 + 0xbfe8bc806b151741, 0xbfe44cf325091dd6, // -0.77301, -0.63439 + 0xbfe87c400fba2ebf, 0xbfe49a449b9b0938, // -0.76517, -0.64383 + 0xbfe83b0e0bff976e, 0xbfe4e6cabbe3e5e9, // -0.75721, -0.65317 + 0xbfe7f8ece3571771, 0xbfe5328292a35596, // -0.74914, -0.66242 + 0xbfe7b5df226aafb0, 0xbfe57d69348cec9f, // -0.74095, -0.67156 + 0xbfe771e75f037261, 0xbfe5c77bbe65018c, // -0.73265, -0.6806 + 0xbfe72d0837efff97, 0xbfe610b7551d2cde, // -0.72425, -0.68954 + 0xbfe6e74454eaa8ae, 0xbfe6591925f0783e, // -0.71573, -0.69838 + 0xbfe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // -0.70711, -0.70711 + 0xbfe6591925f0783e, 0xbfe6e74454eaa8ae, // -0.69838, -0.71573 + 0xbfe610b7551d2cde, 0xbfe72d0837efff97, // -0.68954, -0.72425 + 0xbfe5c77bbe65018c, 0xbfe771e75f037261, // -0.6806, -0.73265 + 0xbfe57d69348cec9f, 0xbfe7b5df226aafb0, // -0.67156, -0.74095 + 0xbfe5328292a35596, 0xbfe7f8ece3571771, // -0.66242, -0.74914 + 0xbfe4e6cabbe3e5e9, 0xbfe83b0e0bff976e, // -0.65317, -0.75721 + 0xbfe49a449b9b0938, 0xbfe87c400fba2ebf, // -0.64383, -0.76517 + 0xbfe44cf325091dd6, 0xbfe8bc806b151741, // -0.63439, -0.77301 + 0xbfe3fed9534556d4, 0xbfe8fbcca3ef940d, // -0.62486, -0.78074 + 0xbfe3affa292050b9, 0xbfe93a22499263fc, // -0.61523, -0.78835 + 0xbfe36058b10659f3, 0xbfe9777ef4c7d742, // -0.60551, -0.79584 + 0xbfe30ff7fce17035, 0xbfe9b3e047f38741, // -0.5957, -0.80321 + 0xbfe2bedb25faf3ea, 0xbfe9ef43ef29af94, // -0.5858, -0.81046 + 0xbfe26d054cdd12df, 0xbfea29a7a0462782, // -0.57581, -0.81758 + 0xbfe21a799933eb58, 0xbfea63091b02fae2, // -0.56573, -0.82459 + 0xbfe1c73b39ae68c8, 0xbfea9b66290ea1a3, // -0.55557, -0.83147 + 0xbfe1734d63dedb49, 0xbfead2bc9e21d511, // -0.54532, -0.83822 + 0xbfe11eb3541b4b22, 0xbfeb090a58150200, // -0.535, -0.84485 + 0xbfe0c9704d5d898f, 0xbfeb3e4d3ef55712, // -0.52459, -0.85136 + 0xbfe073879922ffed, 0xbfeb728345196e3e, // -0.5141, -0.85773 + 0xbfe01cfc874c3eb7, 0xbfeba5aa673590d2, // -0.50354, -0.86397 + 0xbfdf8ba4dbf89aba, 0xbfebd7c0ac6f952a, // -0.4929, -0.87009 + 0xbfdedc1952ef78d5, 0xbfec08c426725549, // -0.48218, -0.87607 + 0xbfde2b5d3806f63b, 0xbfec38b2f180bdb1, // -0.4714, -0.88192 + 0xbfdd79775b86e389, 0xbfec678b3488739b, // -0.46054, -0.88764 + 0xbfdcc66e9931c45d, 0xbfec954b213411f5, // -0.44961, -0.89322 + 0xbfdc1249d8011ee7, 0xbfecc1f0f3fcfc5c, // -0.43862, -0.89867 + 0xbfdb5d1009e15cc0, 0xbfeced7af43cc773, // -0.42756, -0.90399 + 0xbfdaa6c82b6d3fc9, 0xbfed17e7743e35dc, // -0.41643, -0.90917 + 0xbfd9ef7943a8ed8a, 0xbfed4134d14dc93a, // -0.40524, -0.91421 + 0xbfd9372a63bc93d7, 0xbfed696173c9e68b, // -0.39399, -0.91911 + 0xbfd87de2a6aea963, 0xbfed906bcf328d46, // -0.38268, -0.92388 + 0xbfd7c3a9311dcce7, 0xbfedb6526238a09b, // -0.37132, -0.92851 + 0xbfd7088530fa459e, 0xbfeddb13b6ccc23d, // -0.3599, -0.93299 + 0xbfd64c7ddd3f27c6, 0xbfedfeae622dbe2b, // -0.34842, -0.93734 + 0xbfd58f9a75ab1fdd, 0xbfee212104f686e5, // -0.33689, -0.94154 + 0xbfd4d1e24278e76a, 0xbfee426a4b2bc17e, // -0.32531, -0.94561 + 0xbfd4135c94176602, 0xbfee6288ec48e112, // -0.31368, -0.94953 + 0xbfd35410c2e18152, 0xbfee817bab4cd10d, // -0.30201, -0.95331 + 0xbfd294062ed59f05, 0xbfee9f4156c62dda, // -0.29028, -0.95694 + 0xbfd1d3443f4cdb3d, 0xbfeebbd8c8df0b74, // -0.27852, -0.96043 + 0xbfd111d262b1f677, 0xbfeed740e7684963, // -0.26671, -0.96378 + 0xbfd04fb80e37fdae, 0xbfeef178a3e473c2, // -0.25487, -0.96698 + 0xbfcf19f97b215f1a, 0xbfef0a7efb9230d7, // -0.24298, -0.97003 + 0xbfcd934fe5454311, 0xbfef2252f7763ada, // -0.23106, -0.97294 + 0xbfcc0b826a7e4f63, 0xbfef38f3ac64e589, // -0.2191, -0.9757 + 0xbfca82a025b00451, 0xbfef4e603b0b2f2d, // -0.20711, -0.97832 + 0xbfc8f8b83c69a60a, 0xbfef6297cff75cb0, // -0.19509, -0.98079 + 0xbfc76dd9de50bf31, 0xbfef7599a3a12077, // -0.18304, -0.98311 + 0xbfc5e214448b3fc6, 0xbfef8764fa714ba9, // -0.17096, -0.98528 + 0xbfc45576b1293e5a, 0xbfef97f924c9099b, // -0.15886, -0.9873 + 0xbfc2c8106e8e613a, 0xbfefa7557f08a517, // -0.14673, -0.98918 + 0xbfc139f0cedaf576, 0xbfefb5797195d741, // -0.13458, -0.9909 + 0xbfbf564e56a9730e, 0xbfefc26470e19fd3, // -0.12241, -0.99248 + 0xbfbc3785c79ec2d5, 0xbfefce15fd6da67b, // -0.11022, -0.99391 + 0xbfb917a6bc29b42c, 0xbfefd88da3d12526, //-0.098017, -0.99518 + 0xbfb5f6d00a9aa419, 0xbfefe1cafcbd5b09, //-0.085797, -0.99631 + 0xbfb2d52092ce19f6, 0xbfefe9cdad01883a, //-0.073565, -0.99729 + 0xbfaf656e79f820e0, 0xbfeff095658e71ad, //-0.061321, -0.99812 + 0xbfa91f65f10dd814, 0xbfeff621e3796d7e, //-0.049068, -0.9988 + 0xbfa2d865759455cd, 0xbfeffa72effef75d, //-0.036807, -0.99932 + 0xbf992155f7a3667e, 0xbfeffd886084cd0d, //-0.024541, -0.9997 + 0xbf8921d1fcdec784, 0xbfefff62169b92db, //-0.012272, -0.99992 + 0x0000000000000000, 0xbff0000000000000, // 0, -1 + 0x3f8921d1fcdec784, 0xbfefff62169b92db, // 0.012272, -0.99992 + 0x3f992155f7a3667e, 0xbfeffd886084cd0d, // 0.024541, -0.9997 + 0x3fa2d865759455cd, 0xbfeffa72effef75d, // 0.036807, -0.99932 + 0x3fa91f65f10dd814, 0xbfeff621e3796d7e, // 0.049068, -0.9988 + 0x3faf656e79f820e0, 0xbfeff095658e71ad, // 0.061321, -0.99812 + 0x3fb2d52092ce19f6, 0xbfefe9cdad01883a, // 0.073565, -0.99729 + 0x3fb5f6d00a9aa419, 0xbfefe1cafcbd5b09, // 0.085797, -0.99631 + 0x3fb917a6bc29b42c, 0xbfefd88da3d12526, // 0.098017, -0.99518 + 0x3fbc3785c79ec2d5, 0xbfefce15fd6da67b, // 0.11022, -0.99391 + 0x3fbf564e56a9730e, 0xbfefc26470e19fd3, // 0.12241, -0.99248 + 0x3fc139f0cedaf576, 0xbfefb5797195d741, // 0.13458, -0.9909 + 0x3fc2c8106e8e613a, 0xbfefa7557f08a517, // 0.14673, -0.98918 + 0x3fc45576b1293e5a, 0xbfef97f924c9099b, // 0.15886, -0.9873 + 0x3fc5e214448b3fc6, 0xbfef8764fa714ba9, // 0.17096, -0.98528 + 0x3fc76dd9de50bf31, 0xbfef7599a3a12077, // 0.18304, -0.98311 + 0x3fc8f8b83c69a60a, 0xbfef6297cff75cb0, // 0.19509, -0.98079 + 0x3fca82a025b00451, 0xbfef4e603b0b2f2d, // 0.20711, -0.97832 + 0x3fcc0b826a7e4f63, 0xbfef38f3ac64e589, // 0.2191, -0.9757 + 0x3fcd934fe5454311, 0xbfef2252f7763ada, // 0.23106, -0.97294 + 0x3fcf19f97b215f1a, 0xbfef0a7efb9230d7, // 0.24298, -0.97003 + 0x3fd04fb80e37fdae, 0xbfeef178a3e473c2, // 0.25487, -0.96698 + 0x3fd111d262b1f677, 0xbfeed740e7684963, // 0.26671, -0.96378 + 0x3fd1d3443f4cdb3d, 0xbfeebbd8c8df0b74, // 0.27852, -0.96043 + 0x3fd294062ed59f05, 0xbfee9f4156c62dda, // 0.29028, -0.95694 + 0x3fd35410c2e18152, 0xbfee817bab4cd10d, // 0.30201, -0.95331 + 0x3fd4135c94176602, 0xbfee6288ec48e112, // 0.31368, -0.94953 + 0x3fd4d1e24278e76a, 0xbfee426a4b2bc17e, // 0.32531, -0.94561 + 0x3fd58f9a75ab1fdd, 0xbfee212104f686e5, // 0.33689, -0.94154 + 0x3fd64c7ddd3f27c6, 0xbfedfeae622dbe2b, // 0.34842, -0.93734 + 0x3fd7088530fa459e, 0xbfeddb13b6ccc23d, // 0.3599, -0.93299 + 0x3fd7c3a9311dcce7, 0xbfedb6526238a09b, // 0.37132, -0.92851 + 0x3fd87de2a6aea963, 0xbfed906bcf328d46, // 0.38268, -0.92388 + 0x3fd9372a63bc93d7, 0xbfed696173c9e68b, // 0.39399, -0.91911 + 0x3fd9ef7943a8ed8a, 0xbfed4134d14dc93a, // 0.40524, -0.91421 + 0x3fdaa6c82b6d3fc9, 0xbfed17e7743e35dc, // 0.41643, -0.90917 + 0x3fdb5d1009e15cc0, 0xbfeced7af43cc773, // 0.42756, -0.90399 + 0x3fdc1249d8011ee7, 0xbfecc1f0f3fcfc5c, // 0.43862, -0.89867 + 0x3fdcc66e9931c45d, 0xbfec954b213411f5, // 0.44961, -0.89322 + 0x3fdd79775b86e389, 0xbfec678b3488739b, // 0.46054, -0.88764 + 0x3fde2b5d3806f63b, 0xbfec38b2f180bdb1, // 0.4714, -0.88192 + 0x3fdedc1952ef78d5, 0xbfec08c426725549, // 0.48218, -0.87607 + 0x3fdf8ba4dbf89aba, 0xbfebd7c0ac6f952a, // 0.4929, -0.87009 + 0x3fe01cfc874c3eb7, 0xbfeba5aa673590d2, // 0.50354, -0.86397 + 0x3fe073879922ffed, 0xbfeb728345196e3e, // 0.5141, -0.85773 + 0x3fe0c9704d5d898f, 0xbfeb3e4d3ef55712, // 0.52459, -0.85136 + 0x3fe11eb3541b4b22, 0xbfeb090a58150200, // 0.535, -0.84485 + 0x3fe1734d63dedb49, 0xbfead2bc9e21d511, // 0.54532, -0.83822 + 0x3fe1c73b39ae68c8, 0xbfea9b66290ea1a3, // 0.55557, -0.83147 + 0x3fe21a799933eb58, 0xbfea63091b02fae2, // 0.56573, -0.82459 + 0x3fe26d054cdd12df, 0xbfea29a7a0462782, // 0.57581, -0.81758 + 0x3fe2bedb25faf3ea, 0xbfe9ef43ef29af94, // 0.5858, -0.81046 + 0x3fe30ff7fce17035, 0xbfe9b3e047f38741, // 0.5957, -0.80321 + 0x3fe36058b10659f3, 0xbfe9777ef4c7d742, // 0.60551, -0.79584 + 0x3fe3affa292050b9, 0xbfe93a22499263fc, // 0.61523, -0.78835 + 0x3fe3fed9534556d4, 0xbfe8fbcca3ef940d, // 0.62486, -0.78074 + 0x3fe44cf325091dd6, 0xbfe8bc806b151741, // 0.63439, -0.77301 + 0x3fe49a449b9b0938, 0xbfe87c400fba2ebf, // 0.64383, -0.76517 + 0x3fe4e6cabbe3e5e9, 0xbfe83b0e0bff976e, // 0.65317, -0.75721 + 0x3fe5328292a35596, 0xbfe7f8ece3571771, // 0.66242, -0.74914 + 0x3fe57d69348cec9f, 0xbfe7b5df226aafb0, // 0.67156, -0.74095 + 0x3fe5c77bbe65018c, 0xbfe771e75f037261, // 0.6806, -0.73265 + 0x3fe610b7551d2cde, 0xbfe72d0837efff97, // 0.68954, -0.72425 + 0x3fe6591925f0783e, 0xbfe6e74454eaa8ae, // 0.69838, -0.71573 + 0x3fe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // 0.70711, -0.70711 + 0x3fe6e74454eaa8ae, 0xbfe6591925f0783e, // 0.71573, -0.69838 + 0x3fe72d0837efff97, 0xbfe610b7551d2cde, // 0.72425, -0.68954 + 0x3fe771e75f037261, 0xbfe5c77bbe65018c, // 0.73265, -0.6806 + 0x3fe7b5df226aafb0, 0xbfe57d69348cec9f, // 0.74095, -0.67156 + 0x3fe7f8ece3571771, 0xbfe5328292a35596, // 0.74914, -0.66242 + 0x3fe83b0e0bff976e, 0xbfe4e6cabbe3e5e9, // 0.75721, -0.65317 + 0x3fe87c400fba2ebf, 0xbfe49a449b9b0938, // 0.76517, -0.64383 + 0x3fe8bc806b151741, 0xbfe44cf325091dd6, // 0.77301, -0.63439 + 0x3fe8fbcca3ef940d, 0xbfe3fed9534556d4, // 0.78074, -0.62486 + 0x3fe93a22499263fc, 0xbfe3affa292050b9, // 0.78835, -0.61523 + 0x3fe9777ef4c7d742, 0xbfe36058b10659f3, // 0.79584, -0.60551 + 0x3fe9b3e047f38741, 0xbfe30ff7fce17035, // 0.80321, -0.5957 + 0x3fe9ef43ef29af94, 0xbfe2bedb25faf3ea, // 0.81046, -0.5858 + 0x3fea29a7a0462782, 0xbfe26d054cdd12df, // 0.81758, -0.57581 + 0x3fea63091b02fae2, 0xbfe21a799933eb58, // 0.82459, -0.56573 + 0x3fea9b66290ea1a3, 0xbfe1c73b39ae68c8, // 0.83147, -0.55557 + 0x3fead2bc9e21d511, 0xbfe1734d63dedb49, // 0.83822, -0.54532 + 0x3feb090a58150200, 0xbfe11eb3541b4b22, // 0.84485, -0.535 + 0x3feb3e4d3ef55712, 0xbfe0c9704d5d898f, // 0.85136, -0.52459 + 0x3feb728345196e3e, 0xbfe073879922ffed, // 0.85773, -0.5141 + 0x3feba5aa673590d2, 0xbfe01cfc874c3eb7, // 0.86397, -0.50354 + 0x3febd7c0ac6f952a, 0xbfdf8ba4dbf89aba, // 0.87009, -0.4929 + 0x3fec08c426725549, 0xbfdedc1952ef78d5, // 0.87607, -0.48218 + 0x3fec38b2f180bdb1, 0xbfde2b5d3806f63b, // 0.88192, -0.4714 + 0x3fec678b3488739b, 0xbfdd79775b86e389, // 0.88764, -0.46054 + 0x3fec954b213411f5, 0xbfdcc66e9931c45d, // 0.89322, -0.44961 + 0x3fecc1f0f3fcfc5c, 0xbfdc1249d8011ee7, // 0.89867, -0.43862 + 0x3feced7af43cc773, 0xbfdb5d1009e15cc0, // 0.90399, -0.42756 + 0x3fed17e7743e35dc, 0xbfdaa6c82b6d3fc9, // 0.90917, -0.41643 + 0x3fed4134d14dc93a, 0xbfd9ef7943a8ed8a, // 0.91421, -0.40524 + 0x3fed696173c9e68b, 0xbfd9372a63bc93d7, // 0.91911, -0.39399 + 0x3fed906bcf328d46, 0xbfd87de2a6aea963, // 0.92388, -0.38268 + 0x3fedb6526238a09b, 0xbfd7c3a9311dcce7, // 0.92851, -0.37132 + 0x3feddb13b6ccc23d, 0xbfd7088530fa459e, // 0.93299, -0.3599 + 0x3fedfeae622dbe2b, 0xbfd64c7ddd3f27c6, // 0.93734, -0.34842 + 0x3fee212104f686e5, 0xbfd58f9a75ab1fdd, // 0.94154, -0.33689 + 0x3fee426a4b2bc17e, 0xbfd4d1e24278e76a, // 0.94561, -0.32531 + 0x3fee6288ec48e112, 0xbfd4135c94176602, // 0.94953, -0.31368 + 0x3fee817bab4cd10d, 0xbfd35410c2e18152, // 0.95331, -0.30201 + 0x3fee9f4156c62dda, 0xbfd294062ed59f05, // 0.95694, -0.29028 + 0x3feebbd8c8df0b74, 0xbfd1d3443f4cdb3d, // 0.96043, -0.27852 + 0x3feed740e7684963, 0xbfd111d262b1f677, // 0.96378, -0.26671 + 0x3feef178a3e473c2, 0xbfd04fb80e37fdae, // 0.96698, -0.25487 + 0x3fef0a7efb9230d7, 0xbfcf19f97b215f1a, // 0.97003, -0.24298 + 0x3fef2252f7763ada, 0xbfcd934fe5454311, // 0.97294, -0.23106 + 0x3fef38f3ac64e589, 0xbfcc0b826a7e4f63, // 0.9757, -0.2191 + 0x3fef4e603b0b2f2d, 0xbfca82a025b00451, // 0.97832, -0.20711 + 0x3fef6297cff75cb0, 0xbfc8f8b83c69a60a, // 0.98079, -0.19509 + 0x3fef7599a3a12077, 0xbfc76dd9de50bf31, // 0.98311, -0.18304 + 0x3fef8764fa714ba9, 0xbfc5e214448b3fc6, // 0.98528, -0.17096 + 0x3fef97f924c9099b, 0xbfc45576b1293e5a, // 0.9873, -0.15886 + 0x3fefa7557f08a517, 0xbfc2c8106e8e613a, // 0.98918, -0.14673 + 0x3fefb5797195d741, 0xbfc139f0cedaf576, // 0.9909, -0.13458 + 0x3fefc26470e19fd3, 0xbfbf564e56a9730e, // 0.99248, -0.12241 + 0x3fefce15fd6da67b, 0xbfbc3785c79ec2d5, // 0.99391, -0.11022 + 0x3fefd88da3d12526, 0xbfb917a6bc29b42c, // 0.99518,-0.098017 + 0x3fefe1cafcbd5b09, 0xbfb5f6d00a9aa419, // 0.99631,-0.085797 + 0x3fefe9cdad01883a, 0xbfb2d52092ce19f6, // 0.99729,-0.073565 + 0x3feff095658e71ad, 0xbfaf656e79f820e0, // 0.99812,-0.061321 + 0x3feff621e3796d7e, 0xbfa91f65f10dd814, // 0.9988,-0.049068 + 0x3feffa72effef75d, 0xbfa2d865759455cd, // 0.99932,-0.036807 + 0x3feffd886084cd0d, 0xbf992155f7a3667e, // 0.9997,-0.024541 + 0x3fefff62169b92db, 0xbf8921d1fcdec784, // 0.99992,-0.012272 +}; + +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_F64_1024) +/** + @par + Example code for Double Precision Floating-point Twiddle factors Generation: + @par + 
for (i = 0; i< N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/(float)N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 1024, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const uint64_t twiddleCoefF64_1024[2048] = { + 0x3ff0000000000000, 0x0000000000000000, // 1, 0 + 0x3fefffd8858e8a92, 0x3f7921f0fe670071, // 0.99998, 0.0061359 + 0x3fefff62169b92db, 0x3f8921d1fcdec784, // 0.99992, 0.012272 + 0x3feffe9cb44b51a1, 0x3f92d936bbe30efd, // 0.99983, 0.018407 + 0x3feffd886084cd0d, 0x3f992155f7a3667e, // 0.9997, 0.024541 + 0x3feffc251df1d3f8, 0x3f9f693731d1cf01, // 0.99953, 0.030675 + 0x3feffa72effef75d, 0x3fa2d865759455cd, // 0.99932, 0.036807 + 0x3feff871dadb81df, 0x3fa5fc00d290cd43, // 0.99908, 0.042938 + 0x3feff621e3796d7e, 0x3fa91f65f10dd814, // 0.9988, 0.049068 + 0x3feff3830f8d575c, 0x3fac428d12c0d7e3, // 0.99848, 0.055195 + 0x3feff095658e71ad, 0x3faf656e79f820e0, // 0.99812, 0.061321 + 0x3fefed58ecb673c4, 0x3fb1440134d709b2, // 0.99772, 0.067444 + 0x3fefe9cdad01883a, 0x3fb2d52092ce19f6, // 0.99729, 0.073565 + 0x3fefe5f3af2e3940, 0x3fb4661179272096, // 0.99682, 0.079682 + 0x3fefe1cafcbd5b09, 0x3fb5f6d00a9aa419, // 0.99631, 0.085797 + 0x3fefdd539ff1f456, 0x3fb787586a5d5b21, // 0.99577, 0.091909 + 0x3fefd88da3d12526, 0x3fb917a6bc29b42c, // 0.99518, 0.098017 + 0x3fefd37914220b84, 0x3fbaa7b724495c04, // 0.99456, 0.10412 + 0x3fefce15fd6da67b, 0x3fbc3785c79ec2d5, // 0.99391, 0.11022 + 0x3fefc8646cfeb721, 0x3fbdc70ecbae9fc8, // 0.99321, 0.11632 + 0x3fefc26470e19fd3, 0x3fbf564e56a9730e, // 0.99248, 0.12241 + 0x3fefbc1617e44186, 0x3fc072a047ba831d, // 0.99171, 0.1285 + 0x3fefb5797195d741, 0x3fc139f0cedaf576, // 0.9909, 0.13458 + 0x3fefae8e8e46cfbb, 0x3fc20116d4ec7bce, // 0.99006, 0.14066 + 0x3fefa7557f08a517, 0x3fc2c8106e8e613a, // 0.98918, 0.14673 + 0x3fef9fce55adb2c8, 0x3fc38edbb0cd8d14, // 0.98826, 0.1528 + 0x3fef97f924c9099b, 0x3fc45576b1293e5a, // 0.9873, 0.15886 + 0x3fef8fd5ffae41db, 0x3fc51bdf8597c5f2, // 0.98631, 0.16491 + 0x3fef8764fa714ba9, 0x3fc5e214448b3fc6, // 0.98528, 0.17096 + 0x3fef7ea629e63d6e, 0x3fc6a81304f64ab2, // 0.98421, 0.177 + 0x3fef7599a3a12077, 0x3fc76dd9de50bf31, // 0.98311, 0.18304 + 0x3fef6c3f7df5bbb7, 0x3fc83366e89c64c5, // 0.98196, 0.18907 + 0x3fef6297cff75cb0, 0x3fc8f8b83c69a60a, // 0.98079, 0.19509 + 0x3fef58a2b1789e84, 0x3fc9bdcbf2dc4366, // 0.97957, 0.2011 + 0x3fef4e603b0b2f2d, 0x3fca82a025b00451, // 0.97832, 0.20711 + 0x3fef43d085ff92dd, 0x3fcb4732ef3d6722, // 0.97703, 0.21311 + 0x3fef38f3ac64e589, 0x3fcc0b826a7e4f63, // 0.9757, 0.2191 + 0x3fef2dc9c9089a9d, 0x3fcccf8cb312b286, // 0.97434, 0.22508 + 0x3fef2252f7763ada, 0x3fcd934fe5454311, // 0.97294, 0.23106 + 0x3fef168f53f7205d, 0x3fce56ca1e101a1b, // 0.9715, 0.23702 + 0x3fef0a7efb9230d7, 0x3fcf19f97b215f1a, // 0.97003, 0.24298 + 0x3feefe220c0b95ec, 0x3fcfdcdc1adfedf8, // 0.96852, 0.24893 + 0x3feef178a3e473c2, 0x3fd04fb80e37fdae, // 0.96698, 0.25487 + 0x3feee482e25a9dbc, 0x3fd0b0d9cfdbdb90, // 0.96539, 0.26079 + 0x3feed740e7684963, 0x3fd111d262b1f677, // 0.96378, 0.26671 + 0x3feec9b2d3c3bf84, 0x3fd172a0d7765177, // 0.96212, 0.27262 + 0x3feebbd8c8df0b74, 0x3fd1d3443f4cdb3d, // 0.96043, 0.27852 + 0x3feeadb2e8e7a88e, 0x3fd233bbabc3bb72, // 0.9587, 0.28441 + 0x3fee9f4156c62dda, 0x3fd294062ed59f05, // 0.95694, 0.29028 + 0x3fee9084361df7f3, 0x3fd2f422daec0386, // 0.95514, 0.29615 + 0x3fee817bab4cd10d, 0x3fd35410c2e18152, // 0.95331, 0.30201 + 0x3fee7227db6a9744, 0x3fd3b3cefa0414b7, // 0.95144, 0.30785 + 0x3fee6288ec48e112, 0x3fd4135c94176602, // 0.94953, 0.31368 + 0x3fee529f04729ffc, 0x3fd472b8a5571054, // 0.94759, 0.3195 + 0x3fee426a4b2bc17e, 0x3fd4d1e24278e76a, // 0.94561, 0.32531 + 0x3fee31eae870ce25, 0x3fd530d880af3c24, // 0.94359, 0.33111 + 0x3fee212104f686e5, 0x3fd58f9a75ab1fdd, // 0.94154, 0.33689 + 0x3fee100cca2980ac, 0x3fd5ee27379ea693, // 0.93946, 0.34266 + 0x3fedfeae622dbe2b, 0x3fd64c7ddd3f27c6, // 0.93734, 0.34842 + 0x3feded05f7de47da, 0x3fd6aa9d7dc77e16, // 0.93518, 0.35416 + 0x3feddb13b6ccc23d, 0x3fd7088530fa459e, // 0.93299, 0.3599 + 0x3fedc8d7cb410260, 0x3fd766340f2418f6, // 0.93077, 0.36561 + 0x3fedb6526238a09b, 0x3fd7c3a9311dcce7, // 0.92851, 0.37132 + 0x3feda383a9668988, 0x3fd820e3b04eaac4, // 0.92621, 0.37701 + 0x3fed906bcf328d46, 0x3fd87de2a6aea963, // 0.92388, 0.38268 + 0x3fed7d0b02b8ecf9, 0x3fd8daa52ec8a4af, // 0.92151, 0.38835 + 0x3fed696173c9e68b, 0x3fd9372a63bc93d7, // 0.91911, 0.39399 + 0x3fed556f52e93eb1, 0x3fd993716141bdfe, // 0.91668, 0.39962 + 0x3fed4134d14dc93a, 0x3fd9ef7943a8ed8a, // 0.91421, 0.40524 + 0x3fed2cb220e0ef9f, 0x3fda4b4127dea1e4, // 0.91171, 0.41084 + 0x3fed17e7743e35dc, 0x3fdaa6c82b6d3fc9, // 0.90917, 0.41643 + 0x3fed02d4feb2bd92, 0x3fdb020d6c7f4009, // 0.9066, 0.422 + 0x3feced7af43cc773, 0x3fdb5d1009e15cc0, // 0.90399, 0.42756 + 0x3fecd7d9898b32f6, 0x3fdbb7cf2304bd01, // 0.90135, 0.43309 + 0x3fecc1f0f3fcfc5c, 0x3fdc1249d8011ee7, // 0.89867, 0.43862 + 0x3fecabc169a0b901, 0x3fdc6c7f4997000a, // 0.89597, 0.44412 + 0x3fec954b213411f5, 0x3fdcc66e9931c45d, // 0.89322, 0.44961 + 0x3fec7e8e52233cf3, 0x3fdd2016e8e9db5b, // 0.89045, 0.45508 + 0x3fec678b3488739b, 0x3fdd79775b86e389, // 0.88764, 0.46054 + 0x3fec5042012b6907, 0x3fddd28f1481cc58, // 0.8848, 0.46598 + 0x3fec38b2f180bdb1, 0x3fde2b5d3806f63b, // 0.88192, 0.4714 + 0x3fec20de3fa971b0, 0x3fde83e0eaf85113, // 0.87901, 0.4768 + 0x3fec08c426725549, 0x3fdedc1952ef78d5, // 0.87607, 0.48218 + 0x3febf064e15377dd, 0x3fdf3405963fd068, // 0.87309, 0.48755 + 0x3febd7c0ac6f952a, 0x3fdf8ba4dbf89aba, // 0.87009, 0.4929 + 0x3febbed7c49380ea, 0x3fdfe2f64be7120f, // 0.86705, 0.49823 + 0x3feba5aa673590d2, 0x3fe01cfc874c3eb7, // 0.86397, 0.50354 + 0x3feb8c38d27504e9, 0x3fe0485626ae221a, // 0.86087, 0.50883 + 0x3feb728345196e3e, 0x3fe073879922ffed, // 0.85773, 0.5141 + 0x3feb5889fe921405, 0x3fe09e907417c5e1, // 0.85456, 0.51936 + 0x3feb3e4d3ef55712, 0x3fe0c9704d5d898f, // 0.85136, 0.52459 + 0x3feb23cd470013b4, 0x3fe0f426bb2a8e7d, // 0.84812, 0.5298 + 0x3feb090a58150200, 0x3fe11eb3541b4b22, // 0.84485, 0.535 + 0x3feaee04b43c1474, 0x3fe14915af336ceb, // 0.84155, 0.54017 + 0x3fead2bc9e21d511, 0x3fe1734d63dedb49, // 0.83822, 0.54532 + 0x3feab7325916c0d4, 0x3fe19d5a09f2b9b8, // 0.83486, 0.55046 + 0x3fea9b66290ea1a3, 0x3fe1c73b39ae68c8, // 0.83147, 0.55557 + 0x3fea7f58529fe69d, 0x3fe1f0f08bbc861b, // 0.82805, 0.56066 + 0x3fea63091b02fae2, 0x3fe21a799933eb58, // 0.82459, 0.56573 + 0x3fea4678c8119ac8, 0x3fe243d5fb98ac1f, // 0.8211, 0.57078 + 0x3fea29a7a0462782, 0x3fe26d054cdd12df, // 0.81758, 0.57581 + 0x3fea0c95eabaf937, 0x3fe2960727629ca8, // 0.81404, 0.58081 + 0x3fe9ef43ef29af94, 0x3fe2bedb25faf3ea, // 0.81046, 0.5858 + 0x3fe9d1b1f5ea80d6, 0x3fe2e780e3e8ea16, // 0.80685, 0.59076 + 0x3fe9b3e047f38741, 0x3fe30ff7fce17035, // 0.80321, 0.5957 + 0x3fe995cf2ed80d22, 0x3fe338400d0c8e57, // 0.79954, 0.60062 + 0x3fe9777ef4c7d742, 0x3fe36058b10659f3, // 0.79584, 0.60551 + 0x3fe958efe48e6dd7, 0x3fe3884185dfeb22, // 0.79211, 0.61038 + 0x3fe93a22499263fc, 0x3fe3affa292050b9, // 0.78835, 0.61523 + 0x3fe91b166fd49da2, 0x3fe3d78238c58343, // 0.78456, 0.62006 + 0x3fe8fbcca3ef940d, 0x3fe3fed9534556d4, // 0.78074, 0.62486 + 0x3fe8dc45331698cc, 0x3fe425ff178e6bb1, // 0.77689, 0.62964 + 0x3fe8bc806b151741, 0x3fe44cf325091dd6, // 0.77301, 0.63439 + 0x3fe89c7e9a4dd4ab, 0x3fe473b51b987347, // 0.7691, 0.63912 + 0x3fe87c400fba2ebf, 0x3fe49a449b9b0938, // 0.76517, 0.64383 + 0x3fe85bc51ae958cc, 0x3fe4c0a145ec0004, // 0.7612, 0.64851 + 0x3fe83b0e0bff976e, 0x3fe4e6cabbe3e5e9, // 0.75721, 0.65317 + 0x3fe81a1b33b57acc, 0x3fe50cc09f59a09b, // 0.75319, 0.65781 + 0x3fe7f8ece3571771, 0x3fe5328292a35596, // 0.74914, 0.66242 + 0x3fe7d7836cc33db2, 0x3fe5581038975137, // 0.74506, 0.667 + 0x3fe7b5df226aafb0, 0x3fe57d69348cec9f, // 0.74095, 0.67156 + 0x3fe79400574f55e4, 0x3fe5a28d2a5d7250, // 0.73682, 0.67609 + 0x3fe771e75f037261, 0x3fe5c77bbe65018c, // 0.73265, 0.6806 + 0x3fe74f948da8d28d, 0x3fe5ec3495837074, // 0.72846, 0.68508 + 0x3fe72d0837efff97, 0x3fe610b7551d2cde, // 0.72425, 0.68954 + 0x3fe70a42b3176d7a, 0x3fe63503a31c1be8, // 0.72, 0.69397 + 0x3fe6e74454eaa8ae, 0x3fe6591925f0783e, // 0.71573, 0.69838 + 0x3fe6c40d73c18275, 0x3fe67cf78491af10, // 0.71143, 0.70275 + 0x3fe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // 0.70711, 0.70711 + 0x3fe67cf78491af10, 0x3fe6c40d73c18275, // 0.70275, 0.71143 + 0x3fe6591925f0783e, 0x3fe6e74454eaa8ae, // 0.69838, 0.71573 + 0x3fe63503a31c1be8, 0x3fe70a42b3176d7a, // 0.69397, 0.72 + 0x3fe610b7551d2cde, 0x3fe72d0837efff97, // 0.68954, 0.72425 + 0x3fe5ec3495837074, 0x3fe74f948da8d28d, // 0.68508, 0.72846 + 0x3fe5c77bbe65018c, 0x3fe771e75f037261, // 0.6806, 0.73265 + 0x3fe5a28d2a5d7250, 0x3fe79400574f55e4, // 0.67609, 0.73682 + 0x3fe57d69348cec9f, 0x3fe7b5df226aafb0, // 0.67156, 0.74095 + 0x3fe5581038975137, 0x3fe7d7836cc33db2, // 0.667, 0.74506 + 0x3fe5328292a35596, 0x3fe7f8ece3571771, // 0.66242, 0.74914 + 0x3fe50cc09f59a09b, 0x3fe81a1b33b57acc, // 0.65781, 0.75319 + 0x3fe4e6cabbe3e5e9, 0x3fe83b0e0bff976e, // 0.65317, 0.75721 + 0x3fe4c0a145ec0004, 0x3fe85bc51ae958cc, // 0.64851, 0.7612 + 0x3fe49a449b9b0938, 0x3fe87c400fba2ebf, // 0.64383, 0.76517 + 0x3fe473b51b987347, 0x3fe89c7e9a4dd4ab, // 0.63912, 0.7691 + 0x3fe44cf325091dd6, 0x3fe8bc806b151741, // 0.63439, 0.77301 + 0x3fe425ff178e6bb1, 0x3fe8dc45331698cc, // 0.62964, 0.77689 + 0x3fe3fed9534556d4, 0x3fe8fbcca3ef940d, // 0.62486, 0.78074 + 0x3fe3d78238c58343, 0x3fe91b166fd49da2, // 0.62006, 0.78456 + 0x3fe3affa292050b9, 0x3fe93a22499263fc, // 0.61523, 0.78835 + 0x3fe3884185dfeb22, 0x3fe958efe48e6dd7, // 0.61038, 0.79211 + 0x3fe36058b10659f3, 0x3fe9777ef4c7d742, // 0.60551, 0.79584 + 0x3fe338400d0c8e57, 0x3fe995cf2ed80d22, // 0.60062, 0.79954 + 0x3fe30ff7fce17035, 0x3fe9b3e047f38741, // 0.5957, 0.80321 + 0x3fe2e780e3e8ea16, 0x3fe9d1b1f5ea80d6, // 0.59076, 0.80685 + 0x3fe2bedb25faf3ea, 0x3fe9ef43ef29af94, // 0.5858, 0.81046 + 0x3fe2960727629ca8, 0x3fea0c95eabaf937, // 0.58081, 0.81404 + 0x3fe26d054cdd12df, 0x3fea29a7a0462782, // 0.57581, 0.81758 + 0x3fe243d5fb98ac1f, 0x3fea4678c8119ac8, // 0.57078, 0.8211 + 0x3fe21a799933eb58, 0x3fea63091b02fae2, // 0.56573, 0.82459 + 0x3fe1f0f08bbc861b, 0x3fea7f58529fe69d, // 0.56066, 0.82805 + 0x3fe1c73b39ae68c8, 0x3fea9b66290ea1a3, // 0.55557, 0.83147 + 0x3fe19d5a09f2b9b8, 0x3feab7325916c0d4, // 0.55046, 0.83486 + 0x3fe1734d63dedb49, 0x3fead2bc9e21d511, // 0.54532, 0.83822 + 0x3fe14915af336ceb, 0x3feaee04b43c1474, // 0.54017, 0.84155 + 0x3fe11eb3541b4b22, 0x3feb090a58150200, // 0.535, 0.84485 + 0x3fe0f426bb2a8e7d, 0x3feb23cd470013b4, // 0.5298, 0.84812 + 0x3fe0c9704d5d898f, 0x3feb3e4d3ef55712, // 0.52459, 0.85136 + 0x3fe09e907417c5e1, 0x3feb5889fe921405, // 0.51936, 0.85456 + 0x3fe073879922ffed, 0x3feb728345196e3e, // 0.5141, 0.85773 + 0x3fe0485626ae221a, 0x3feb8c38d27504e9, // 0.50883, 0.86087 + 0x3fe01cfc874c3eb7, 0x3feba5aa673590d2, // 0.50354, 0.86397 + 0x3fdfe2f64be7120f, 0x3febbed7c49380ea, // 0.49823, 0.86705 + 0x3fdf8ba4dbf89aba, 0x3febd7c0ac6f952a, // 0.4929, 0.87009 + 0x3fdf3405963fd068, 0x3febf064e15377dd, // 0.48755, 0.87309 + 0x3fdedc1952ef78d5, 0x3fec08c426725549, // 0.48218, 0.87607 + 0x3fde83e0eaf85113, 0x3fec20de3fa971b0, // 0.4768, 0.87901 + 0x3fde2b5d3806f63b, 0x3fec38b2f180bdb1, // 0.4714, 0.88192 + 0x3fddd28f1481cc58, 0x3fec5042012b6907, // 0.46598, 0.8848 + 0x3fdd79775b86e389, 0x3fec678b3488739b, // 0.46054, 0.88764 + 0x3fdd2016e8e9db5b, 0x3fec7e8e52233cf3, // 0.45508, 0.89045 + 0x3fdcc66e9931c45d, 0x3fec954b213411f5, // 0.44961, 0.89322 + 0x3fdc6c7f4997000a, 0x3fecabc169a0b901, // 0.44412, 0.89597 + 0x3fdc1249d8011ee7, 0x3fecc1f0f3fcfc5c, // 0.43862, 0.89867 + 0x3fdbb7cf2304bd01, 0x3fecd7d9898b32f6, // 0.43309, 0.90135 + 0x3fdb5d1009e15cc0, 0x3feced7af43cc773, // 0.42756, 0.90399 + 0x3fdb020d6c7f4009, 0x3fed02d4feb2bd92, // 0.422, 0.9066 + 0x3fdaa6c82b6d3fc9, 0x3fed17e7743e35dc, // 0.41643, 0.90917 + 0x3fda4b4127dea1e4, 0x3fed2cb220e0ef9f, // 0.41084, 0.91171 + 0x3fd9ef7943a8ed8a, 0x3fed4134d14dc93a, // 0.40524, 0.91421 + 0x3fd993716141bdfe, 0x3fed556f52e93eb1, // 0.39962, 0.91668 + 0x3fd9372a63bc93d7, 0x3fed696173c9e68b, // 0.39399, 0.91911 + 0x3fd8daa52ec8a4af, 0x3fed7d0b02b8ecf9, // 0.38835, 0.92151 + 0x3fd87de2a6aea963, 0x3fed906bcf328d46, // 0.38268, 0.92388 + 0x3fd820e3b04eaac4, 0x3feda383a9668988, // 0.37701, 0.92621 + 0x3fd7c3a9311dcce7, 0x3fedb6526238a09b, // 0.37132, 0.92851 + 0x3fd766340f2418f6, 0x3fedc8d7cb410260, // 0.36561, 0.93077 + 0x3fd7088530fa459e, 0x3feddb13b6ccc23d, // 0.3599, 0.93299 + 0x3fd6aa9d7dc77e16, 0x3feded05f7de47da, // 0.35416, 0.93518 + 0x3fd64c7ddd3f27c6, 0x3fedfeae622dbe2b, // 0.34842, 0.93734 + 0x3fd5ee27379ea693, 0x3fee100cca2980ac, // 0.34266, 0.93946 + 0x3fd58f9a75ab1fdd, 0x3fee212104f686e5, // 0.33689, 0.94154 + 0x3fd530d880af3c24, 0x3fee31eae870ce25, // 0.33111, 0.94359 + 0x3fd4d1e24278e76a, 0x3fee426a4b2bc17e, // 0.32531, 0.94561 + 0x3fd472b8a5571054, 0x3fee529f04729ffc, // 0.3195, 0.94759 + 0x3fd4135c94176602, 0x3fee6288ec48e112, // 0.31368, 0.94953 + 0x3fd3b3cefa0414b7, 0x3fee7227db6a9744, // 0.30785, 0.95144 + 0x3fd35410c2e18152, 0x3fee817bab4cd10d, // 0.30201, 0.95331 + 0x3fd2f422daec0386, 0x3fee9084361df7f3, // 0.29615, 0.95514 + 0x3fd294062ed59f05, 0x3fee9f4156c62dda, // 0.29028, 0.95694 + 0x3fd233bbabc3bb72, 0x3feeadb2e8e7a88e, // 0.28441, 0.9587 + 0x3fd1d3443f4cdb3d, 0x3feebbd8c8df0b74, // 0.27852, 0.96043 + 0x3fd172a0d7765177, 0x3feec9b2d3c3bf84, // 0.27262, 0.96212 + 0x3fd111d262b1f677, 0x3feed740e7684963, // 0.26671, 0.96378 + 0x3fd0b0d9cfdbdb90, 0x3feee482e25a9dbc, // 0.26079, 0.96539 + 0x3fd04fb80e37fdae, 0x3feef178a3e473c2, // 0.25487, 0.96698 + 0x3fcfdcdc1adfedf8, 0x3feefe220c0b95ec, // 0.24893, 0.96852 + 0x3fcf19f97b215f1a, 0x3fef0a7efb9230d7, // 0.24298, 0.97003 + 0x3fce56ca1e101a1b, 0x3fef168f53f7205d, // 0.23702, 0.9715 + 0x3fcd934fe5454311, 0x3fef2252f7763ada, // 0.23106, 0.97294 + 0x3fcccf8cb312b286, 0x3fef2dc9c9089a9d, // 0.22508, 0.97434 + 0x3fcc0b826a7e4f63, 0x3fef38f3ac64e589, // 0.2191, 0.9757 + 0x3fcb4732ef3d6722, 0x3fef43d085ff92dd, // 0.21311, 0.97703 + 0x3fca82a025b00451, 0x3fef4e603b0b2f2d, // 0.20711, 0.97832 + 0x3fc9bdcbf2dc4366, 0x3fef58a2b1789e84, // 0.2011, 0.97957 + 0x3fc8f8b83c69a60a, 0x3fef6297cff75cb0, // 0.19509, 0.98079 + 0x3fc83366e89c64c5, 0x3fef6c3f7df5bbb7, // 0.18907, 0.98196 + 0x3fc76dd9de50bf31, 0x3fef7599a3a12077, // 0.18304, 0.98311 + 0x3fc6a81304f64ab2, 0x3fef7ea629e63d6e, // 0.177, 0.98421 + 0x3fc5e214448b3fc6, 0x3fef8764fa714ba9, // 0.17096, 0.98528 + 0x3fc51bdf8597c5f2, 0x3fef8fd5ffae41db, // 0.16491, 0.98631 + 0x3fc45576b1293e5a, 0x3fef97f924c9099b, // 0.15886, 0.9873 + 0x3fc38edbb0cd8d14, 0x3fef9fce55adb2c8, // 0.1528, 0.98826 + 0x3fc2c8106e8e613a, 0x3fefa7557f08a517, // 0.14673, 0.98918 + 0x3fc20116d4ec7bce, 0x3fefae8e8e46cfbb, // 0.14066, 0.99006 + 0x3fc139f0cedaf576, 0x3fefb5797195d741, // 0.13458, 0.9909 + 0x3fc072a047ba831d, 0x3fefbc1617e44186, // 0.1285, 0.99171 + 0x3fbf564e56a9730e, 0x3fefc26470e19fd3, // 0.12241, 0.99248 + 0x3fbdc70ecbae9fc8, 0x3fefc8646cfeb721, // 0.11632, 0.99321 + 0x3fbc3785c79ec2d5, 0x3fefce15fd6da67b, // 0.11022, 0.99391 + 0x3fbaa7b724495c04, 0x3fefd37914220b84, // 0.10412, 0.99456 + 0x3fb917a6bc29b42c, 0x3fefd88da3d12526, // 0.098017, 0.99518 + 0x3fb787586a5d5b21, 0x3fefdd539ff1f456, // 0.091909, 0.99577 + 0x3fb5f6d00a9aa419, 0x3fefe1cafcbd5b09, // 0.085797, 0.99631 + 0x3fb4661179272096, 0x3fefe5f3af2e3940, // 0.079682, 0.99682 + 0x3fb2d52092ce19f6, 0x3fefe9cdad01883a, // 0.073565, 0.99729 + 0x3fb1440134d709b2, 0x3fefed58ecb673c4, // 0.067444, 0.99772 + 0x3faf656e79f820e0, 0x3feff095658e71ad, // 0.061321, 0.99812 + 0x3fac428d12c0d7e3, 0x3feff3830f8d575c, // 0.055195, 0.99848 + 0x3fa91f65f10dd814, 0x3feff621e3796d7e, // 0.049068, 0.9988 + 0x3fa5fc00d290cd43, 0x3feff871dadb81df, // 0.042938, 0.99908 + 0x3fa2d865759455cd, 0x3feffa72effef75d, // 0.036807, 0.99932 + 0x3f9f693731d1cf01, 0x3feffc251df1d3f8, // 0.030675, 0.99953 + 0x3f992155f7a3667e, 0x3feffd886084cd0d, // 0.024541, 0.9997 + 0x3f92d936bbe30efd, 0x3feffe9cb44b51a1, // 0.018407, 0.99983 + 0x3f8921d1fcdec784, 0x3fefff62169b92db, // 0.012272, 0.99992 + 0x3f7921f0fe670071, 0x3fefffd8858e8a92, // 0.0061359, 0.99998 + 0x0000000000000000, 0x3ff0000000000000, // 0, 1 + 0xbf7921f0fe670071, 0x3fefffd8858e8a92, //-0.0061359, 0.99998 + 0xbf8921d1fcdec784, 0x3fefff62169b92db, // -0.012272, 0.99992 + 0xbf92d936bbe30efd, 0x3feffe9cb44b51a1, // -0.018407, 0.99983 + 0xbf992155f7a3667e, 0x3feffd886084cd0d, // -0.024541, 0.9997 + 0xbf9f693731d1cf01, 0x3feffc251df1d3f8, // -0.030675, 0.99953 + 0xbfa2d865759455cd, 0x3feffa72effef75d, // -0.036807, 0.99932 + 0xbfa5fc00d290cd43, 0x3feff871dadb81df, // -0.042938, 0.99908 + 0xbfa91f65f10dd814, 0x3feff621e3796d7e, // -0.049068, 0.9988 + 0xbfac428d12c0d7e3, 0x3feff3830f8d575c, // -0.055195, 0.99848 + 0xbfaf656e79f820e0, 0x3feff095658e71ad, // -0.061321, 0.99812 + 0xbfb1440134d709b2, 0x3fefed58ecb673c4, // -0.067444, 0.99772 + 0xbfb2d52092ce19f6, 0x3fefe9cdad01883a, // -0.073565, 0.99729 + 0xbfb4661179272096, 0x3fefe5f3af2e3940, // -0.079682, 0.99682 + 0xbfb5f6d00a9aa419, 0x3fefe1cafcbd5b09, // -0.085797, 0.99631 + 0xbfb787586a5d5b21, 0x3fefdd539ff1f456, // -0.091909, 0.99577 + 0xbfb917a6bc29b42c, 0x3fefd88da3d12526, // -0.098017, 0.99518 + 0xbfbaa7b724495c04, 0x3fefd37914220b84, // -0.10412, 0.99456 + 0xbfbc3785c79ec2d5, 0x3fefce15fd6da67b, // -0.11022, 0.99391 + 0xbfbdc70ecbae9fc8, 0x3fefc8646cfeb721, // -0.11632, 0.99321 + 0xbfbf564e56a9730e, 0x3fefc26470e19fd3, // -0.12241, 0.99248 + 0xbfc072a047ba831d, 0x3fefbc1617e44186, // -0.1285, 0.99171 + 0xbfc139f0cedaf576, 0x3fefb5797195d741, // -0.13458, 0.9909 + 0xbfc20116d4ec7bce, 0x3fefae8e8e46cfbb, // -0.14066, 0.99006 + 0xbfc2c8106e8e613a, 0x3fefa7557f08a517, // -0.14673, 0.98918 + 0xbfc38edbb0cd8d14, 0x3fef9fce55adb2c8, // -0.1528, 0.98826 + 0xbfc45576b1293e5a, 0x3fef97f924c9099b, // -0.15886, 0.9873 + 0xbfc51bdf8597c5f2, 0x3fef8fd5ffae41db, // -0.16491, 0.98631 + 0xbfc5e214448b3fc6, 0x3fef8764fa714ba9, // -0.17096, 0.98528 + 0xbfc6a81304f64ab2, 0x3fef7ea629e63d6e, // -0.177, 0.98421 + 0xbfc76dd9de50bf31, 0x3fef7599a3a12077, // -0.18304, 0.98311 + 0xbfc83366e89c64c5, 0x3fef6c3f7df5bbb7, // -0.18907, 0.98196 + 0xbfc8f8b83c69a60a, 0x3fef6297cff75cb0, // -0.19509, 0.98079 + 0xbfc9bdcbf2dc4366, 0x3fef58a2b1789e84, // -0.2011, 0.97957 + 0xbfca82a025b00451, 0x3fef4e603b0b2f2d, // -0.20711, 0.97832 + 0xbfcb4732ef3d6722, 0x3fef43d085ff92dd, // -0.21311, 0.97703 + 0xbfcc0b826a7e4f63, 0x3fef38f3ac64e589, // -0.2191, 0.9757 + 0xbfcccf8cb312b286, 0x3fef2dc9c9089a9d, // -0.22508, 0.97434 + 0xbfcd934fe5454311, 0x3fef2252f7763ada, // -0.23106, 0.97294 + 0xbfce56ca1e101a1b, 0x3fef168f53f7205d, // -0.23702, 0.9715 + 0xbfcf19f97b215f1a, 0x3fef0a7efb9230d7, // -0.24298, 0.97003 + 0xbfcfdcdc1adfedf8, 0x3feefe220c0b95ec, // -0.24893, 0.96852 + 0xbfd04fb80e37fdae, 0x3feef178a3e473c2, // -0.25487, 0.96698 + 0xbfd0b0d9cfdbdb90, 0x3feee482e25a9dbc, // -0.26079, 0.96539 + 0xbfd111d262b1f677, 0x3feed740e7684963, // -0.26671, 0.96378 + 0xbfd172a0d7765177, 0x3feec9b2d3c3bf84, // -0.27262, 0.96212 + 0xbfd1d3443f4cdb3d, 0x3feebbd8c8df0b74, // -0.27852, 0.96043 + 0xbfd233bbabc3bb72, 0x3feeadb2e8e7a88e, // -0.28441, 0.9587 + 0xbfd294062ed59f05, 0x3fee9f4156c62dda, // -0.29028, 0.95694 + 0xbfd2f422daec0386, 0x3fee9084361df7f3, // -0.29615, 0.95514 + 0xbfd35410c2e18152, 0x3fee817bab4cd10d, // -0.30201, 0.95331 + 0xbfd3b3cefa0414b7, 0x3fee7227db6a9744, // -0.30785, 0.95144 + 0xbfd4135c94176602, 0x3fee6288ec48e112, // -0.31368, 0.94953 + 0xbfd472b8a5571054, 0x3fee529f04729ffc, // -0.3195, 0.94759 + 0xbfd4d1e24278e76a, 0x3fee426a4b2bc17e, // -0.32531, 0.94561 + 0xbfd530d880af3c24, 0x3fee31eae870ce25, // -0.33111, 0.94359 + 0xbfd58f9a75ab1fdd, 0x3fee212104f686e5, // -0.33689, 0.94154 + 0xbfd5ee27379ea693, 0x3fee100cca2980ac, // -0.34266, 0.93946 + 0xbfd64c7ddd3f27c6, 0x3fedfeae622dbe2b, // -0.34842, 0.93734 + 0xbfd6aa9d7dc77e16, 0x3feded05f7de47da, // -0.35416, 0.93518 + 0xbfd7088530fa459e, 0x3feddb13b6ccc23d, // -0.3599, 0.93299 + 0xbfd766340f2418f6, 0x3fedc8d7cb410260, // -0.36561, 0.93077 + 0xbfd7c3a9311dcce7, 0x3fedb6526238a09b, // -0.37132, 0.92851 + 0xbfd820e3b04eaac4, 0x3feda383a9668988, // -0.37701, 0.92621 + 0xbfd87de2a6aea963, 0x3fed906bcf328d46, // -0.38268, 0.92388 + 0xbfd8daa52ec8a4af, 0x3fed7d0b02b8ecf9, // -0.38835, 0.92151 + 0xbfd9372a63bc93d7, 0x3fed696173c9e68b, // -0.39399, 0.91911 + 0xbfd993716141bdfe, 0x3fed556f52e93eb1, // -0.39962, 0.91668 + 0xbfd9ef7943a8ed8a, 0x3fed4134d14dc93a, // -0.40524, 0.91421 + 0xbfda4b4127dea1e4, 0x3fed2cb220e0ef9f, // -0.41084, 0.91171 + 0xbfdaa6c82b6d3fc9, 0x3fed17e7743e35dc, // -0.41643, 0.90917 + 0xbfdb020d6c7f4009, 0x3fed02d4feb2bd92, // -0.422, 0.9066 + 0xbfdb5d1009e15cc0, 0x3feced7af43cc773, // -0.42756, 0.90399 + 0xbfdbb7cf2304bd01, 0x3fecd7d9898b32f6, // -0.43309, 0.90135 + 0xbfdc1249d8011ee7, 0x3fecc1f0f3fcfc5c, // -0.43862, 0.89867 + 0xbfdc6c7f4997000a, 0x3fecabc169a0b901, // -0.44412, 0.89597 + 0xbfdcc66e9931c45d, 0x3fec954b213411f5, // -0.44961, 0.89322 + 0xbfdd2016e8e9db5b, 0x3fec7e8e52233cf3, // -0.45508, 0.89045 + 0xbfdd79775b86e389, 0x3fec678b3488739b, // -0.46054, 0.88764 + 0xbfddd28f1481cc58, 0x3fec5042012b6907, // -0.46598, 0.8848 + 0xbfde2b5d3806f63b, 0x3fec38b2f180bdb1, // -0.4714, 0.88192 + 0xbfde83e0eaf85113, 0x3fec20de3fa971b0, // -0.4768, 0.87901 + 0xbfdedc1952ef78d5, 0x3fec08c426725549, // -0.48218, 0.87607 + 0xbfdf3405963fd068, 0x3febf064e15377dd, // -0.48755, 0.87309 + 0xbfdf8ba4dbf89aba, 0x3febd7c0ac6f952a, // -0.4929, 0.87009 + 0xbfdfe2f64be7120f, 0x3febbed7c49380ea, // -0.49823, 0.86705 + 0xbfe01cfc874c3eb7, 0x3feba5aa673590d2, // -0.50354, 0.86397 + 0xbfe0485626ae221a, 0x3feb8c38d27504e9, // -0.50883, 0.86087 + 0xbfe073879922ffed, 0x3feb728345196e3e, // -0.5141, 0.85773 + 0xbfe09e907417c5e1, 0x3feb5889fe921405, // -0.51936, 0.85456 + 0xbfe0c9704d5d898f, 0x3feb3e4d3ef55712, // -0.52459, 0.85136 + 0xbfe0f426bb2a8e7d, 0x3feb23cd470013b4, // -0.5298, 0.84812 + 0xbfe11eb3541b4b22, 0x3feb090a58150200, // -0.535, 0.84485 + 0xbfe14915af336ceb, 0x3feaee04b43c1474, // -0.54017, 0.84155 + 0xbfe1734d63dedb49, 0x3fead2bc9e21d511, // -0.54532, 0.83822 + 0xbfe19d5a09f2b9b8, 0x3feab7325916c0d4, // -0.55046, 0.83486 + 0xbfe1c73b39ae68c8, 0x3fea9b66290ea1a3, // -0.55557, 0.83147 + 0xbfe1f0f08bbc861b, 0x3fea7f58529fe69d, // -0.56066, 0.82805 + 0xbfe21a799933eb58, 0x3fea63091b02fae2, // -0.56573, 0.82459 + 0xbfe243d5fb98ac1f, 0x3fea4678c8119ac8, // -0.57078, 0.8211 + 0xbfe26d054cdd12df, 0x3fea29a7a0462782, // -0.57581, 0.81758 + 0xbfe2960727629ca8, 0x3fea0c95eabaf937, // -0.58081, 0.81404 + 0xbfe2bedb25faf3ea, 0x3fe9ef43ef29af94, // -0.5858, 0.81046 + 0xbfe2e780e3e8ea16, 0x3fe9d1b1f5ea80d6, // -0.59076, 0.80685 + 0xbfe30ff7fce17035, 0x3fe9b3e047f38741, // -0.5957, 0.80321 + 0xbfe338400d0c8e57, 0x3fe995cf2ed80d22, // -0.60062, 0.79954 + 0xbfe36058b10659f3, 0x3fe9777ef4c7d742, // -0.60551, 0.79584 + 0xbfe3884185dfeb22, 0x3fe958efe48e6dd7, // -0.61038, 0.79211 + 0xbfe3affa292050b9, 0x3fe93a22499263fc, // -0.61523, 0.78835 + 0xbfe3d78238c58343, 0x3fe91b166fd49da2, // -0.62006, 0.78456 + 0xbfe3fed9534556d4, 0x3fe8fbcca3ef940d, // -0.62486, 0.78074 + 0xbfe425ff178e6bb1, 0x3fe8dc45331698cc, // -0.62964, 0.77689 + 0xbfe44cf325091dd6, 0x3fe8bc806b151741, // -0.63439, 0.77301 + 0xbfe473b51b987347, 0x3fe89c7e9a4dd4ab, // -0.63912, 0.7691 + 0xbfe49a449b9b0938, 0x3fe87c400fba2ebf, // -0.64383, 0.76517 + 0xbfe4c0a145ec0004, 0x3fe85bc51ae958cc, // -0.64851, 0.7612 + 0xbfe4e6cabbe3e5e9, 0x3fe83b0e0bff976e, // -0.65317, 0.75721 + 0xbfe50cc09f59a09b, 0x3fe81a1b33b57acc, // -0.65781, 0.75319 + 0xbfe5328292a35596, 0x3fe7f8ece3571771, // -0.66242, 0.74914 + 0xbfe5581038975137, 0x3fe7d7836cc33db2, // -0.667, 0.74506 + 0xbfe57d69348cec9f, 0x3fe7b5df226aafb0, // -0.67156, 0.74095 + 0xbfe5a28d2a5d7250, 0x3fe79400574f55e4, // -0.67609, 0.73682 + 0xbfe5c77bbe65018c, 0x3fe771e75f037261, // -0.6806, 0.73265 + 0xbfe5ec3495837074, 0x3fe74f948da8d28d, // -0.68508, 0.72846 + 0xbfe610b7551d2cde, 0x3fe72d0837efff97, // -0.68954, 0.72425 + 0xbfe63503a31c1be8, 0x3fe70a42b3176d7a, // -0.69397, 0.72 + 0xbfe6591925f0783e, 0x3fe6e74454eaa8ae, // -0.69838, 0.71573 + 0xbfe67cf78491af10, 0x3fe6c40d73c18275, // -0.70275, 0.71143 + 0xbfe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // -0.70711, 0.70711 + 0xbfe6c40d73c18275, 0x3fe67cf78491af10, // -0.71143, 0.70275 + 0xbfe6e74454eaa8ae, 0x3fe6591925f0783e, // -0.71573, 0.69838 + 0xbfe70a42b3176d7a, 0x3fe63503a31c1be8, // -0.72, 0.69397 + 0xbfe72d0837efff97, 0x3fe610b7551d2cde, // -0.72425, 0.68954 + 0xbfe74f948da8d28d, 0x3fe5ec3495837074, // -0.72846, 0.68508 + 0xbfe771e75f037261, 0x3fe5c77bbe65018c, // -0.73265, 0.6806 + 0xbfe79400574f55e4, 0x3fe5a28d2a5d7250, // -0.73682, 0.67609 + 0xbfe7b5df226aafb0, 0x3fe57d69348cec9f, // -0.74095, 0.67156 + 0xbfe7d7836cc33db2, 0x3fe5581038975137, // -0.74506, 0.667 + 0xbfe7f8ece3571771, 0x3fe5328292a35596, // -0.74914, 0.66242 + 0xbfe81a1b33b57acc, 0x3fe50cc09f59a09b, // -0.75319, 0.65781 + 0xbfe83b0e0bff976e, 0x3fe4e6cabbe3e5e9, // -0.75721, 0.65317 + 0xbfe85bc51ae958cc, 0x3fe4c0a145ec0004, // -0.7612, 0.64851 + 0xbfe87c400fba2ebf, 0x3fe49a449b9b0938, // -0.76517, 0.64383 + 0xbfe89c7e9a4dd4ab, 0x3fe473b51b987347, // -0.7691, 0.63912 + 0xbfe8bc806b151741, 0x3fe44cf325091dd6, // -0.77301, 0.63439 + 0xbfe8dc45331698cc, 0x3fe425ff178e6bb1, // -0.77689, 0.62964 + 0xbfe8fbcca3ef940d, 0x3fe3fed9534556d4, // -0.78074, 0.62486 + 0xbfe91b166fd49da2, 0x3fe3d78238c58343, // -0.78456, 0.62006 + 0xbfe93a22499263fc, 0x3fe3affa292050b9, // -0.78835, 0.61523 + 0xbfe958efe48e6dd7, 0x3fe3884185dfeb22, // -0.79211, 0.61038 + 0xbfe9777ef4c7d742, 0x3fe36058b10659f3, // -0.79584, 0.60551 + 0xbfe995cf2ed80d22, 0x3fe338400d0c8e57, // -0.79954, 0.60062 + 0xbfe9b3e047f38741, 0x3fe30ff7fce17035, // -0.80321, 0.5957 + 0xbfe9d1b1f5ea80d6, 0x3fe2e780e3e8ea16, // -0.80685, 0.59076 + 0xbfe9ef43ef29af94, 0x3fe2bedb25faf3ea, // -0.81046, 0.5858 + 0xbfea0c95eabaf937, 0x3fe2960727629ca8, // -0.81404, 0.58081 + 0xbfea29a7a0462782, 0x3fe26d054cdd12df, // -0.81758, 0.57581 + 0xbfea4678c8119ac8, 0x3fe243d5fb98ac1f, // -0.8211, 0.57078 + 0xbfea63091b02fae2, 0x3fe21a799933eb58, // -0.82459, 0.56573 + 0xbfea7f58529fe69d, 0x3fe1f0f08bbc861b, // -0.82805, 0.56066 + 0xbfea9b66290ea1a3, 0x3fe1c73b39ae68c8, // -0.83147, 0.55557 + 0xbfeab7325916c0d4, 0x3fe19d5a09f2b9b8, // -0.83486, 0.55046 + 0xbfead2bc9e21d511, 0x3fe1734d63dedb49, // -0.83822, 0.54532 + 0xbfeaee04b43c1474, 0x3fe14915af336ceb, // -0.84155, 0.54017 + 0xbfeb090a58150200, 0x3fe11eb3541b4b22, // -0.84485, 0.535 + 0xbfeb23cd470013b4, 0x3fe0f426bb2a8e7d, // -0.84812, 0.5298 + 0xbfeb3e4d3ef55712, 0x3fe0c9704d5d898f, // -0.85136, 0.52459 + 0xbfeb5889fe921405, 0x3fe09e907417c5e1, // -0.85456, 0.51936 + 0xbfeb728345196e3e, 0x3fe073879922ffed, // -0.85773, 0.5141 + 0xbfeb8c38d27504e9, 0x3fe0485626ae221a, // -0.86087, 0.50883 + 0xbfeba5aa673590d2, 0x3fe01cfc874c3eb7, // -0.86397, 0.50354 + 0xbfebbed7c49380ea, 0x3fdfe2f64be7120f, // -0.86705, 0.49823 + 0xbfebd7c0ac6f952a, 0x3fdf8ba4dbf89aba, // -0.87009, 0.4929 + 0xbfebf064e15377dd, 0x3fdf3405963fd068, // -0.87309, 0.48755 + 0xbfec08c426725549, 0x3fdedc1952ef78d5, // -0.87607, 0.48218 + 0xbfec20de3fa971b0, 0x3fde83e0eaf85113, // -0.87901, 0.4768 + 0xbfec38b2f180bdb1, 0x3fde2b5d3806f63b, // -0.88192, 0.4714 + 0xbfec5042012b6907, 0x3fddd28f1481cc58, // -0.8848, 0.46598 + 0xbfec678b3488739b, 0x3fdd79775b86e389, // -0.88764, 0.46054 + 0xbfec7e8e52233cf3, 0x3fdd2016e8e9db5b, // -0.89045, 0.45508 + 0xbfec954b213411f5, 0x3fdcc66e9931c45d, // -0.89322, 0.44961 + 0xbfecabc169a0b901, 0x3fdc6c7f4997000a, // -0.89597, 0.44412 + 0xbfecc1f0f3fcfc5c, 0x3fdc1249d8011ee7, // -0.89867, 0.43862 + 0xbfecd7d9898b32f6, 0x3fdbb7cf2304bd01, // -0.90135, 0.43309 + 0xbfeced7af43cc773, 0x3fdb5d1009e15cc0, // -0.90399, 0.42756 + 0xbfed02d4feb2bd92, 0x3fdb020d6c7f4009, // -0.9066, 0.422 + 0xbfed17e7743e35dc, 0x3fdaa6c82b6d3fc9, // -0.90917, 0.41643 + 0xbfed2cb220e0ef9f, 0x3fda4b4127dea1e4, // -0.91171, 0.41084 + 0xbfed4134d14dc93a, 0x3fd9ef7943a8ed8a, // -0.91421, 0.40524 + 0xbfed556f52e93eb1, 0x3fd993716141bdfe, // -0.91668, 0.39962 + 0xbfed696173c9e68b, 0x3fd9372a63bc93d7, // -0.91911, 0.39399 + 0xbfed7d0b02b8ecf9, 0x3fd8daa52ec8a4af, // -0.92151, 0.38835 + 0xbfed906bcf328d46, 0x3fd87de2a6aea963, // -0.92388, 0.38268 + 0xbfeda383a9668988, 0x3fd820e3b04eaac4, // -0.92621, 0.37701 + 0xbfedb6526238a09b, 0x3fd7c3a9311dcce7, // -0.92851, 0.37132 + 0xbfedc8d7cb410260, 0x3fd766340f2418f6, // -0.93077, 0.36561 + 0xbfeddb13b6ccc23d, 0x3fd7088530fa459e, // -0.93299, 0.3599 + 0xbfeded05f7de47da, 0x3fd6aa9d7dc77e16, // -0.93518, 0.35416 + 0xbfedfeae622dbe2b, 0x3fd64c7ddd3f27c6, // -0.93734, 0.34842 + 0xbfee100cca2980ac, 0x3fd5ee27379ea693, // -0.93946, 0.34266 + 0xbfee212104f686e5, 0x3fd58f9a75ab1fdd, // -0.94154, 0.33689 + 0xbfee31eae870ce25, 0x3fd530d880af3c24, // -0.94359, 0.33111 + 0xbfee426a4b2bc17e, 0x3fd4d1e24278e76a, // -0.94561, 0.32531 + 0xbfee529f04729ffc, 0x3fd472b8a5571054, // -0.94759, 0.3195 + 0xbfee6288ec48e112, 0x3fd4135c94176602, // -0.94953, 0.31368 + 0xbfee7227db6a9744, 0x3fd3b3cefa0414b7, // -0.95144, 0.30785 + 0xbfee817bab4cd10d, 0x3fd35410c2e18152, // -0.95331, 0.30201 + 0xbfee9084361df7f3, 0x3fd2f422daec0386, // -0.95514, 0.29615 + 0xbfee9f4156c62dda, 0x3fd294062ed59f05, // -0.95694, 0.29028 + 0xbfeeadb2e8e7a88e, 0x3fd233bbabc3bb72, // -0.9587, 0.28441 + 0xbfeebbd8c8df0b74, 0x3fd1d3443f4cdb3d, // -0.96043, 0.27852 + 0xbfeec9b2d3c3bf84, 0x3fd172a0d7765177, // -0.96212, 0.27262 + 0xbfeed740e7684963, 0x3fd111d262b1f677, // -0.96378, 0.26671 + 0xbfeee482e25a9dbc, 0x3fd0b0d9cfdbdb90, // -0.96539, 0.26079 + 0xbfeef178a3e473c2, 0x3fd04fb80e37fdae, // -0.96698, 0.25487 + 0xbfeefe220c0b95ec, 0x3fcfdcdc1adfedf8, // -0.96852, 0.24893 + 0xbfef0a7efb9230d7, 0x3fcf19f97b215f1a, // -0.97003, 0.24298 + 0xbfef168f53f7205d, 0x3fce56ca1e101a1b, // -0.9715, 0.23702 + 0xbfef2252f7763ada, 0x3fcd934fe5454311, // -0.97294, 0.23106 + 0xbfef2dc9c9089a9d, 0x3fcccf8cb312b286, // -0.97434, 0.22508 + 0xbfef38f3ac64e589, 0x3fcc0b826a7e4f63, // -0.9757, 0.2191 + 0xbfef43d085ff92dd, 0x3fcb4732ef3d6722, // -0.97703, 0.21311 + 0xbfef4e603b0b2f2d, 0x3fca82a025b00451, // -0.97832, 0.20711 + 0xbfef58a2b1789e84, 0x3fc9bdcbf2dc4366, // -0.97957, 0.2011 + 0xbfef6297cff75cb0, 0x3fc8f8b83c69a60a, // -0.98079, 0.19509 + 0xbfef6c3f7df5bbb7, 0x3fc83366e89c64c5, // -0.98196, 0.18907 + 0xbfef7599a3a12077, 0x3fc76dd9de50bf31, // -0.98311, 0.18304 + 0xbfef7ea629e63d6e, 0x3fc6a81304f64ab2, // -0.98421, 0.177 + 0xbfef8764fa714ba9, 0x3fc5e214448b3fc6, // -0.98528, 0.17096 + 0xbfef8fd5ffae41db, 0x3fc51bdf8597c5f2, // -0.98631, 0.16491 + 0xbfef97f924c9099b, 0x3fc45576b1293e5a, // -0.9873, 0.15886 + 0xbfef9fce55adb2c8, 0x3fc38edbb0cd8d14, // -0.98826, 0.1528 + 0xbfefa7557f08a517, 0x3fc2c8106e8e613a, // -0.98918, 0.14673 + 0xbfefae8e8e46cfbb, 0x3fc20116d4ec7bce, // -0.99006, 0.14066 + 0xbfefb5797195d741, 0x3fc139f0cedaf576, // -0.9909, 0.13458 + 0xbfefbc1617e44186, 0x3fc072a047ba831d, // -0.99171, 0.1285 + 0xbfefc26470e19fd3, 0x3fbf564e56a9730e, // -0.99248, 0.12241 + 0xbfefc8646cfeb721, 0x3fbdc70ecbae9fc8, // -0.99321, 0.11632 + 0xbfefce15fd6da67b, 0x3fbc3785c79ec2d5, // -0.99391, 0.11022 + 0xbfefd37914220b84, 0x3fbaa7b724495c04, // -0.99456, 0.10412 + 0xbfefd88da3d12526, 0x3fb917a6bc29b42c, // -0.99518, 0.098017 + 0xbfefdd539ff1f456, 0x3fb787586a5d5b21, // -0.99577, 0.091909 + 0xbfefe1cafcbd5b09, 0x3fb5f6d00a9aa419, // -0.99631, 0.085797 + 0xbfefe5f3af2e3940, 0x3fb4661179272096, // -0.99682, 0.079682 + 0xbfefe9cdad01883a, 0x3fb2d52092ce19f6, // -0.99729, 0.073565 + 0xbfefed58ecb673c4, 0x3fb1440134d709b2, // -0.99772, 0.067444 + 0xbfeff095658e71ad, 0x3faf656e79f820e0, // -0.99812, 0.061321 + 0xbfeff3830f8d575c, 0x3fac428d12c0d7e3, // -0.99848, 0.055195 + 0xbfeff621e3796d7e, 0x3fa91f65f10dd814, // -0.9988, 0.049068 + 0xbfeff871dadb81df, 0x3fa5fc00d290cd43, // -0.99908, 0.042938 + 0xbfeffa72effef75d, 0x3fa2d865759455cd, // -0.99932, 0.036807 + 0xbfeffc251df1d3f8, 0x3f9f693731d1cf01, // -0.99953, 0.030675 + 0xbfeffd886084cd0d, 0x3f992155f7a3667e, // -0.9997, 0.024541 + 0xbfeffe9cb44b51a1, 0x3f92d936bbe30efd, // -0.99983, 0.018407 + 0xbfefff62169b92db, 0x3f8921d1fcdec784, // -0.99992, 0.012272 + 0xbfefffd8858e8a92, 0x3f7921f0fe670071, // -0.99998, 0.0061359 + 0xbff0000000000000, 0x0000000000000000, // -1, 0 + 0xbfefffd8858e8a92, 0xbf7921f0fe670071, // -0.99998,-0.0061359 + 0xbfefff62169b92db, 0xbf8921d1fcdec784, // -0.99992, -0.012272 + 0xbfeffe9cb44b51a1, 0xbf92d936bbe30efd, // -0.99983, -0.018407 + 0xbfeffd886084cd0d, 0xbf992155f7a3667e, // -0.9997, -0.024541 + 0xbfeffc251df1d3f8, 0xbf9f693731d1cf01, // -0.99953, -0.030675 + 0xbfeffa72effef75d, 0xbfa2d865759455cd, // -0.99932, -0.036807 + 0xbfeff871dadb81df, 0xbfa5fc00d290cd43, // -0.99908, -0.042938 + 0xbfeff621e3796d7e, 0xbfa91f65f10dd814, // -0.9988, -0.049068 + 0xbfeff3830f8d575c, 0xbfac428d12c0d7e3, // -0.99848, -0.055195 + 0xbfeff095658e71ad, 0xbfaf656e79f820e0, // -0.99812, -0.061321 + 0xbfefed58ecb673c4, 0xbfb1440134d709b2, // -0.99772, -0.067444 + 0xbfefe9cdad01883a, 0xbfb2d52092ce19f6, // -0.99729, -0.073565 + 0xbfefe5f3af2e3940, 0xbfb4661179272096, // -0.99682, -0.079682 + 0xbfefe1cafcbd5b09, 0xbfb5f6d00a9aa419, // -0.99631, -0.085797 + 0xbfefdd539ff1f456, 0xbfb787586a5d5b21, // -0.99577, -0.091909 + 0xbfefd88da3d12526, 0xbfb917a6bc29b42c, // -0.99518, -0.098017 + 0xbfefd37914220b84, 0xbfbaa7b724495c04, // -0.99456, -0.10412 + 0xbfefce15fd6da67b, 0xbfbc3785c79ec2d5, // -0.99391, -0.11022 + 0xbfefc8646cfeb721, 0xbfbdc70ecbae9fc8, // -0.99321, -0.11632 + 0xbfefc26470e19fd3, 0xbfbf564e56a9730e, // -0.99248, -0.12241 + 0xbfefbc1617e44186, 0xbfc072a047ba831d, // -0.99171, -0.1285 + 0xbfefb5797195d741, 0xbfc139f0cedaf576, // -0.9909, -0.13458 + 0xbfefae8e8e46cfbb, 0xbfc20116d4ec7bce, // -0.99006, -0.14066 + 0xbfefa7557f08a517, 0xbfc2c8106e8e613a, // -0.98918, -0.14673 + 0xbfef9fce55adb2c8, 0xbfc38edbb0cd8d14, // -0.98826, -0.1528 + 0xbfef97f924c9099b, 0xbfc45576b1293e5a, // -0.9873, -0.15886 + 0xbfef8fd5ffae41db, 0xbfc51bdf8597c5f2, // -0.98631, -0.16491 + 0xbfef8764fa714ba9, 0xbfc5e214448b3fc6, // -0.98528, -0.17096 + 0xbfef7ea629e63d6e, 0xbfc6a81304f64ab2, // -0.98421, -0.177 + 0xbfef7599a3a12077, 0xbfc76dd9de50bf31, // -0.98311, -0.18304 + 0xbfef6c3f7df5bbb7, 0xbfc83366e89c64c5, // -0.98196, -0.18907 + 0xbfef6297cff75cb0, 0xbfc8f8b83c69a60a, // -0.98079, -0.19509 + 0xbfef58a2b1789e84, 0xbfc9bdcbf2dc4366, // -0.97957, -0.2011 + 0xbfef4e603b0b2f2d, 0xbfca82a025b00451, // -0.97832, -0.20711 + 0xbfef43d085ff92dd, 0xbfcb4732ef3d6722, // -0.97703, -0.21311 + 0xbfef38f3ac64e589, 0xbfcc0b826a7e4f63, // -0.9757, -0.2191 + 0xbfef2dc9c9089a9d, 0xbfcccf8cb312b286, // -0.97434, -0.22508 + 0xbfef2252f7763ada, 0xbfcd934fe5454311, // -0.97294, -0.23106 + 0xbfef168f53f7205d, 0xbfce56ca1e101a1b, // -0.9715, -0.23702 + 0xbfef0a7efb9230d7, 0xbfcf19f97b215f1a, // -0.97003, -0.24298 + 0xbfeefe220c0b95ec, 0xbfcfdcdc1adfedf8, // -0.96852, -0.24893 + 0xbfeef178a3e473c2, 0xbfd04fb80e37fdae, // -0.96698, -0.25487 + 0xbfeee482e25a9dbc, 0xbfd0b0d9cfdbdb90, // -0.96539, -0.26079 + 0xbfeed740e7684963, 0xbfd111d262b1f677, // -0.96378, -0.26671 + 0xbfeec9b2d3c3bf84, 0xbfd172a0d7765177, // -0.96212, -0.27262 + 0xbfeebbd8c8df0b74, 0xbfd1d3443f4cdb3d, // -0.96043, -0.27852 + 0xbfeeadb2e8e7a88e, 0xbfd233bbabc3bb72, // -0.9587, -0.28441 + 0xbfee9f4156c62dda, 0xbfd294062ed59f05, // -0.95694, -0.29028 + 0xbfee9084361df7f3, 0xbfd2f422daec0386, // -0.95514, -0.29615 + 0xbfee817bab4cd10d, 0xbfd35410c2e18152, // -0.95331, -0.30201 + 0xbfee7227db6a9744, 0xbfd3b3cefa0414b7, // -0.95144, -0.30785 + 0xbfee6288ec48e112, 0xbfd4135c94176602, // -0.94953, -0.31368 + 0xbfee529f04729ffc, 0xbfd472b8a5571054, // -0.94759, -0.3195 + 0xbfee426a4b2bc17e, 0xbfd4d1e24278e76a, // -0.94561, -0.32531 + 0xbfee31eae870ce25, 0xbfd530d880af3c24, // -0.94359, -0.33111 + 0xbfee212104f686e5, 0xbfd58f9a75ab1fdd, // -0.94154, -0.33689 + 0xbfee100cca2980ac, 0xbfd5ee27379ea693, // -0.93946, -0.34266 + 0xbfedfeae622dbe2b, 0xbfd64c7ddd3f27c6, // -0.93734, -0.34842 + 0xbfeded05f7de47da, 0xbfd6aa9d7dc77e16, // -0.93518, -0.35416 + 0xbfeddb13b6ccc23d, 0xbfd7088530fa459e, // -0.93299, -0.3599 + 0xbfedc8d7cb410260, 0xbfd766340f2418f6, // -0.93077, -0.36561 + 0xbfedb6526238a09b, 0xbfd7c3a9311dcce7, // -0.92851, -0.37132 + 0xbfeda383a9668988, 0xbfd820e3b04eaac4, // -0.92621, -0.37701 + 0xbfed906bcf328d46, 0xbfd87de2a6aea963, // -0.92388, -0.38268 + 0xbfed7d0b02b8ecf9, 0xbfd8daa52ec8a4af, // -0.92151, -0.38835 + 0xbfed696173c9e68b, 0xbfd9372a63bc93d7, // -0.91911, -0.39399 + 0xbfed556f52e93eb1, 0xbfd993716141bdfe, // -0.91668, -0.39962 + 0xbfed4134d14dc93a, 0xbfd9ef7943a8ed8a, // -0.91421, -0.40524 + 0xbfed2cb220e0ef9f, 0xbfda4b4127dea1e4, // -0.91171, -0.41084 + 0xbfed17e7743e35dc, 0xbfdaa6c82b6d3fc9, // -0.90917, -0.41643 + 0xbfed02d4feb2bd92, 0xbfdb020d6c7f4009, // -0.9066, -0.422 + 0xbfeced7af43cc773, 0xbfdb5d1009e15cc0, // -0.90399, -0.42756 + 0xbfecd7d9898b32f6, 0xbfdbb7cf2304bd01, // -0.90135, -0.43309 + 0xbfecc1f0f3fcfc5c, 0xbfdc1249d8011ee7, // -0.89867, -0.43862 + 0xbfecabc169a0b901, 0xbfdc6c7f4997000a, // -0.89597, -0.44412 + 0xbfec954b213411f5, 0xbfdcc66e9931c45d, // -0.89322, -0.44961 + 0xbfec7e8e52233cf3, 0xbfdd2016e8e9db5b, // -0.89045, -0.45508 + 0xbfec678b3488739b, 0xbfdd79775b86e389, // -0.88764, -0.46054 + 0xbfec5042012b6907, 0xbfddd28f1481cc58, // -0.8848, -0.46598 + 0xbfec38b2f180bdb1, 0xbfde2b5d3806f63b, // -0.88192, -0.4714 + 0xbfec20de3fa971b0, 0xbfde83e0eaf85113, // -0.87901, -0.4768 + 0xbfec08c426725549, 0xbfdedc1952ef78d5, // -0.87607, -0.48218 + 0xbfebf064e15377dd, 0xbfdf3405963fd068, // -0.87309, -0.48755 + 0xbfebd7c0ac6f952a, 0xbfdf8ba4dbf89aba, // -0.87009, -0.4929 + 0xbfebbed7c49380ea, 0xbfdfe2f64be7120f, // -0.86705, -0.49823 + 0xbfeba5aa673590d2, 0xbfe01cfc874c3eb7, // -0.86397, -0.50354 + 0xbfeb8c38d27504e9, 0xbfe0485626ae221a, // -0.86087, -0.50883 + 0xbfeb728345196e3e, 0xbfe073879922ffed, // -0.85773, -0.5141 + 0xbfeb5889fe921405, 0xbfe09e907417c5e1, // -0.85456, -0.51936 + 0xbfeb3e4d3ef55712, 0xbfe0c9704d5d898f, // -0.85136, -0.52459 + 0xbfeb23cd470013b4, 0xbfe0f426bb2a8e7d, // -0.84812, -0.5298 + 0xbfeb090a58150200, 0xbfe11eb3541b4b22, // -0.84485, -0.535 + 0xbfeaee04b43c1474, 0xbfe14915af336ceb, // -0.84155, -0.54017 + 0xbfead2bc9e21d511, 0xbfe1734d63dedb49, // -0.83822, -0.54532 + 0xbfeab7325916c0d4, 0xbfe19d5a09f2b9b8, // -0.83486, -0.55046 + 0xbfea9b66290ea1a3, 0xbfe1c73b39ae68c8, // -0.83147, -0.55557 + 0xbfea7f58529fe69d, 0xbfe1f0f08bbc861b, // -0.82805, -0.56066 + 0xbfea63091b02fae2, 0xbfe21a799933eb58, // -0.82459, -0.56573 + 0xbfea4678c8119ac8, 0xbfe243d5fb98ac1f, // -0.8211, -0.57078 + 0xbfea29a7a0462782, 0xbfe26d054cdd12df, // -0.81758, -0.57581 + 0xbfea0c95eabaf937, 0xbfe2960727629ca8, // -0.81404, -0.58081 + 0xbfe9ef43ef29af94, 0xbfe2bedb25faf3ea, // -0.81046, -0.5858 + 0xbfe9d1b1f5ea80d6, 0xbfe2e780e3e8ea16, // -0.80685, -0.59076 + 0xbfe9b3e047f38741, 0xbfe30ff7fce17035, // -0.80321, -0.5957 + 0xbfe995cf2ed80d22, 0xbfe338400d0c8e57, // -0.79954, -0.60062 + 0xbfe9777ef4c7d742, 0xbfe36058b10659f3, // -0.79584, -0.60551 + 0xbfe958efe48e6dd7, 0xbfe3884185dfeb22, // -0.79211, -0.61038 + 0xbfe93a22499263fc, 0xbfe3affa292050b9, // -0.78835, -0.61523 + 0xbfe91b166fd49da2, 0xbfe3d78238c58343, // -0.78456, -0.62006 + 0xbfe8fbcca3ef940d, 0xbfe3fed9534556d4, // -0.78074, -0.62486 + 0xbfe8dc45331698cc, 0xbfe425ff178e6bb1, // -0.77689, -0.62964 + 0xbfe8bc806b151741, 0xbfe44cf325091dd6, // -0.77301, -0.63439 + 0xbfe89c7e9a4dd4ab, 0xbfe473b51b987347, // -0.7691, -0.63912 + 0xbfe87c400fba2ebf, 0xbfe49a449b9b0938, // -0.76517, -0.64383 + 0xbfe85bc51ae958cc, 0xbfe4c0a145ec0004, // -0.7612, -0.64851 + 0xbfe83b0e0bff976e, 0xbfe4e6cabbe3e5e9, // -0.75721, -0.65317 + 0xbfe81a1b33b57acc, 0xbfe50cc09f59a09b, // -0.75319, -0.65781 + 0xbfe7f8ece3571771, 0xbfe5328292a35596, // -0.74914, -0.66242 + 0xbfe7d7836cc33db2, 0xbfe5581038975137, // -0.74506, -0.667 + 0xbfe7b5df226aafb0, 0xbfe57d69348cec9f, // -0.74095, -0.67156 + 0xbfe79400574f55e4, 0xbfe5a28d2a5d7250, // -0.73682, -0.67609 + 0xbfe771e75f037261, 0xbfe5c77bbe65018c, // -0.73265, -0.6806 + 0xbfe74f948da8d28d, 0xbfe5ec3495837074, // -0.72846, -0.68508 + 0xbfe72d0837efff97, 0xbfe610b7551d2cde, // -0.72425, -0.68954 + 0xbfe70a42b3176d7a, 0xbfe63503a31c1be8, // -0.72, -0.69397 + 0xbfe6e74454eaa8ae, 0xbfe6591925f0783e, // -0.71573, -0.69838 + 0xbfe6c40d73c18275, 0xbfe67cf78491af10, // -0.71143, -0.70275 + 0xbfe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // -0.70711, -0.70711 + 0xbfe67cf78491af10, 0xbfe6c40d73c18275, // -0.70275, -0.71143 + 0xbfe6591925f0783e, 0xbfe6e74454eaa8ae, // -0.69838, -0.71573 + 0xbfe63503a31c1be8, 0xbfe70a42b3176d7a, // -0.69397, -0.72 + 0xbfe610b7551d2cde, 0xbfe72d0837efff97, // -0.68954, -0.72425 + 0xbfe5ec3495837074, 0xbfe74f948da8d28d, // -0.68508, -0.72846 + 0xbfe5c77bbe65018c, 0xbfe771e75f037261, // -0.6806, -0.73265 + 0xbfe5a28d2a5d7250, 0xbfe79400574f55e4, // -0.67609, -0.73682 + 0xbfe57d69348cec9f, 0xbfe7b5df226aafb0, // -0.67156, -0.74095 + 0xbfe5581038975137, 0xbfe7d7836cc33db2, // -0.667, -0.74506 + 0xbfe5328292a35596, 0xbfe7f8ece3571771, // -0.66242, -0.74914 + 0xbfe50cc09f59a09b, 0xbfe81a1b33b57acc, // -0.65781, -0.75319 + 0xbfe4e6cabbe3e5e9, 0xbfe83b0e0bff976e, // -0.65317, -0.75721 + 0xbfe4c0a145ec0004, 0xbfe85bc51ae958cc, // -0.64851, -0.7612 + 0xbfe49a449b9b0938, 0xbfe87c400fba2ebf, // -0.64383, -0.76517 + 0xbfe473b51b987347, 0xbfe89c7e9a4dd4ab, // -0.63912, -0.7691 + 0xbfe44cf325091dd6, 0xbfe8bc806b151741, // -0.63439, -0.77301 + 0xbfe425ff178e6bb1, 0xbfe8dc45331698cc, // -0.62964, -0.77689 + 0xbfe3fed9534556d4, 0xbfe8fbcca3ef940d, // -0.62486, -0.78074 + 0xbfe3d78238c58343, 0xbfe91b166fd49da2, // -0.62006, -0.78456 + 0xbfe3affa292050b9, 0xbfe93a22499263fc, // -0.61523, -0.78835 + 0xbfe3884185dfeb22, 0xbfe958efe48e6dd7, // -0.61038, -0.79211 + 0xbfe36058b10659f3, 0xbfe9777ef4c7d742, // -0.60551, -0.79584 + 0xbfe338400d0c8e57, 0xbfe995cf2ed80d22, // -0.60062, -0.79954 + 0xbfe30ff7fce17035, 0xbfe9b3e047f38741, // -0.5957, -0.80321 + 0xbfe2e780e3e8ea16, 0xbfe9d1b1f5ea80d6, // -0.59076, -0.80685 + 0xbfe2bedb25faf3ea, 0xbfe9ef43ef29af94, // -0.5858, -0.81046 + 0xbfe2960727629ca8, 0xbfea0c95eabaf937, // -0.58081, -0.81404 + 0xbfe26d054cdd12df, 0xbfea29a7a0462782, // -0.57581, -0.81758 + 0xbfe243d5fb98ac1f, 0xbfea4678c8119ac8, // -0.57078, -0.8211 + 0xbfe21a799933eb58, 0xbfea63091b02fae2, // -0.56573, -0.82459 + 0xbfe1f0f08bbc861b, 0xbfea7f58529fe69d, // -0.56066, -0.82805 + 0xbfe1c73b39ae68c8, 0xbfea9b66290ea1a3, // -0.55557, -0.83147 + 0xbfe19d5a09f2b9b8, 0xbfeab7325916c0d4, // -0.55046, -0.83486 + 0xbfe1734d63dedb49, 0xbfead2bc9e21d511, // -0.54532, -0.83822 + 0xbfe14915af336ceb, 0xbfeaee04b43c1474, // -0.54017, -0.84155 + 0xbfe11eb3541b4b22, 0xbfeb090a58150200, // -0.535, -0.84485 + 0xbfe0f426bb2a8e7d, 0xbfeb23cd470013b4, // -0.5298, -0.84812 + 0xbfe0c9704d5d898f, 0xbfeb3e4d3ef55712, // -0.52459, -0.85136 + 0xbfe09e907417c5e1, 0xbfeb5889fe921405, // -0.51936, -0.85456 + 0xbfe073879922ffed, 0xbfeb728345196e3e, // -0.5141, -0.85773 + 0xbfe0485626ae221a, 0xbfeb8c38d27504e9, // -0.50883, -0.86087 + 0xbfe01cfc874c3eb7, 0xbfeba5aa673590d2, // -0.50354, -0.86397 + 0xbfdfe2f64be7120f, 0xbfebbed7c49380ea, // -0.49823, -0.86705 + 0xbfdf8ba4dbf89aba, 0xbfebd7c0ac6f952a, // -0.4929, -0.87009 + 0xbfdf3405963fd068, 0xbfebf064e15377dd, // -0.48755, -0.87309 + 0xbfdedc1952ef78d5, 0xbfec08c426725549, // -0.48218, -0.87607 + 0xbfde83e0eaf85113, 0xbfec20de3fa971b0, // -0.4768, -0.87901 + 0xbfde2b5d3806f63b, 0xbfec38b2f180bdb1, // -0.4714, -0.88192 + 0xbfddd28f1481cc58, 0xbfec5042012b6907, // -0.46598, -0.8848 + 0xbfdd79775b86e389, 0xbfec678b3488739b, // -0.46054, -0.88764 + 0xbfdd2016e8e9db5b, 0xbfec7e8e52233cf3, // -0.45508, -0.89045 + 0xbfdcc66e9931c45d, 0xbfec954b213411f5, // -0.44961, -0.89322 + 0xbfdc6c7f4997000a, 0xbfecabc169a0b901, // -0.44412, -0.89597 + 0xbfdc1249d8011ee7, 0xbfecc1f0f3fcfc5c, // -0.43862, -0.89867 + 0xbfdbb7cf2304bd01, 0xbfecd7d9898b32f6, // -0.43309, -0.90135 + 0xbfdb5d1009e15cc0, 0xbfeced7af43cc773, // -0.42756, -0.90399 + 0xbfdb020d6c7f4009, 0xbfed02d4feb2bd92, // -0.422, -0.9066 + 0xbfdaa6c82b6d3fc9, 0xbfed17e7743e35dc, // -0.41643, -0.90917 + 0xbfda4b4127dea1e4, 0xbfed2cb220e0ef9f, // -0.41084, -0.91171 + 0xbfd9ef7943a8ed8a, 0xbfed4134d14dc93a, // -0.40524, -0.91421 + 0xbfd993716141bdfe, 0xbfed556f52e93eb1, // -0.39962, -0.91668 + 0xbfd9372a63bc93d7, 0xbfed696173c9e68b, // -0.39399, -0.91911 + 0xbfd8daa52ec8a4af, 0xbfed7d0b02b8ecf9, // -0.38835, -0.92151 + 0xbfd87de2a6aea963, 0xbfed906bcf328d46, // -0.38268, -0.92388 + 0xbfd820e3b04eaac4, 0xbfeda383a9668988, // -0.37701, -0.92621 + 0xbfd7c3a9311dcce7, 0xbfedb6526238a09b, // -0.37132, -0.92851 + 0xbfd766340f2418f6, 0xbfedc8d7cb410260, // -0.36561, -0.93077 + 0xbfd7088530fa459e, 0xbfeddb13b6ccc23d, // -0.3599, -0.93299 + 0xbfd6aa9d7dc77e16, 0xbfeded05f7de47da, // -0.35416, -0.93518 + 0xbfd64c7ddd3f27c6, 0xbfedfeae622dbe2b, // -0.34842, -0.93734 + 0xbfd5ee27379ea693, 0xbfee100cca2980ac, // -0.34266, -0.93946 + 0xbfd58f9a75ab1fdd, 0xbfee212104f686e5, // -0.33689, -0.94154 + 0xbfd530d880af3c24, 0xbfee31eae870ce25, // -0.33111, -0.94359 + 0xbfd4d1e24278e76a, 0xbfee426a4b2bc17e, // -0.32531, -0.94561 + 0xbfd472b8a5571054, 0xbfee529f04729ffc, // -0.3195, -0.94759 + 0xbfd4135c94176602, 0xbfee6288ec48e112, // -0.31368, -0.94953 + 0xbfd3b3cefa0414b7, 0xbfee7227db6a9744, // -0.30785, -0.95144 + 0xbfd35410c2e18152, 0xbfee817bab4cd10d, // -0.30201, -0.95331 + 0xbfd2f422daec0386, 0xbfee9084361df7f3, // -0.29615, -0.95514 + 0xbfd294062ed59f05, 0xbfee9f4156c62dda, // -0.29028, -0.95694 + 0xbfd233bbabc3bb72, 0xbfeeadb2e8e7a88e, // -0.28441, -0.9587 + 0xbfd1d3443f4cdb3d, 0xbfeebbd8c8df0b74, // -0.27852, -0.96043 + 0xbfd172a0d7765177, 0xbfeec9b2d3c3bf84, // -0.27262, -0.96212 + 0xbfd111d262b1f677, 0xbfeed740e7684963, // -0.26671, -0.96378 + 0xbfd0b0d9cfdbdb90, 0xbfeee482e25a9dbc, // -0.26079, -0.96539 + 0xbfd04fb80e37fdae, 0xbfeef178a3e473c2, // -0.25487, -0.96698 + 0xbfcfdcdc1adfedf8, 0xbfeefe220c0b95ec, // -0.24893, -0.96852 + 0xbfcf19f97b215f1a, 0xbfef0a7efb9230d7, // -0.24298, -0.97003 + 0xbfce56ca1e101a1b, 0xbfef168f53f7205d, // -0.23702, -0.9715 + 0xbfcd934fe5454311, 0xbfef2252f7763ada, // -0.23106, -0.97294 + 0xbfcccf8cb312b286, 0xbfef2dc9c9089a9d, // -0.22508, -0.97434 + 0xbfcc0b826a7e4f63, 0xbfef38f3ac64e589, // -0.2191, -0.9757 + 0xbfcb4732ef3d6722, 0xbfef43d085ff92dd, // -0.21311, -0.97703 + 0xbfca82a025b00451, 0xbfef4e603b0b2f2d, // -0.20711, -0.97832 + 0xbfc9bdcbf2dc4366, 0xbfef58a2b1789e84, // -0.2011, -0.97957 + 0xbfc8f8b83c69a60a, 0xbfef6297cff75cb0, // -0.19509, -0.98079 + 0xbfc83366e89c64c5, 0xbfef6c3f7df5bbb7, // -0.18907, -0.98196 + 0xbfc76dd9de50bf31, 0xbfef7599a3a12077, // -0.18304, -0.98311 + 0xbfc6a81304f64ab2, 0xbfef7ea629e63d6e, // -0.177, -0.98421 + 0xbfc5e214448b3fc6, 0xbfef8764fa714ba9, // -0.17096, -0.98528 + 0xbfc51bdf8597c5f2, 0xbfef8fd5ffae41db, // -0.16491, -0.98631 + 0xbfc45576b1293e5a, 0xbfef97f924c9099b, // -0.15886, -0.9873 + 0xbfc38edbb0cd8d14, 0xbfef9fce55adb2c8, // -0.1528, -0.98826 + 0xbfc2c8106e8e613a, 0xbfefa7557f08a517, // -0.14673, -0.98918 + 0xbfc20116d4ec7bce, 0xbfefae8e8e46cfbb, // -0.14066, -0.99006 + 0xbfc139f0cedaf576, 0xbfefb5797195d741, // -0.13458, -0.9909 + 0xbfc072a047ba831d, 0xbfefbc1617e44186, // -0.1285, -0.99171 + 0xbfbf564e56a9730e, 0xbfefc26470e19fd3, // -0.12241, -0.99248 + 0xbfbdc70ecbae9fc8, 0xbfefc8646cfeb721, // -0.11632, -0.99321 + 0xbfbc3785c79ec2d5, 0xbfefce15fd6da67b, // -0.11022, -0.99391 + 0xbfbaa7b724495c04, 0xbfefd37914220b84, // -0.10412, -0.99456 + 0xbfb917a6bc29b42c, 0xbfefd88da3d12526, // -0.098017, -0.99518 + 0xbfb787586a5d5b21, 0xbfefdd539ff1f456, // -0.091909, -0.99577 + 0xbfb5f6d00a9aa419, 0xbfefe1cafcbd5b09, // -0.085797, -0.99631 + 0xbfb4661179272096, 0xbfefe5f3af2e3940, // -0.079682, -0.99682 + 0xbfb2d52092ce19f6, 0xbfefe9cdad01883a, // -0.073565, -0.99729 + 0xbfb1440134d709b2, 0xbfefed58ecb673c4, // -0.067444, -0.99772 + 0xbfaf656e79f820e0, 0xbfeff095658e71ad, // -0.061321, -0.99812 + 0xbfac428d12c0d7e3, 0xbfeff3830f8d575c, // -0.055195, -0.99848 + 0xbfa91f65f10dd814, 0xbfeff621e3796d7e, // -0.049068, -0.9988 + 0xbfa5fc00d290cd43, 0xbfeff871dadb81df, // -0.042938, -0.99908 + 0xbfa2d865759455cd, 0xbfeffa72effef75d, // -0.036807, -0.99932 + 0xbf9f693731d1cf01, 0xbfeffc251df1d3f8, // -0.030675, -0.99953 + 0xbf992155f7a3667e, 0xbfeffd886084cd0d, // -0.024541, -0.9997 + 0xbf92d936bbe30efd, 0xbfeffe9cb44b51a1, // -0.018407, -0.99983 + 0xbf8921d1fcdec784, 0xbfefff62169b92db, // -0.012272, -0.99992 + 0xbf7921f0fe670071, 0xbfefffd8858e8a92, //-0.0061359, -0.99998 + 0x0000000000000000, 0xbff0000000000000, // 0, -1 + 0x3f7921f0fe670071, 0xbfefffd8858e8a92, // 0.0061359, -0.99998 + 0x3f8921d1fcdec784, 0xbfefff62169b92db, // 0.012272, -0.99992 + 0x3f92d936bbe30efd, 0xbfeffe9cb44b51a1, // 0.018407, -0.99983 + 0x3f992155f7a3667e, 0xbfeffd886084cd0d, // 0.024541, -0.9997 + 0x3f9f693731d1cf01, 0xbfeffc251df1d3f8, // 0.030675, -0.99953 + 0x3fa2d865759455cd, 0xbfeffa72effef75d, // 0.036807, -0.99932 + 0x3fa5fc00d290cd43, 0xbfeff871dadb81df, // 0.042938, -0.99908 + 0x3fa91f65f10dd814, 0xbfeff621e3796d7e, // 0.049068, -0.9988 + 0x3fac428d12c0d7e3, 0xbfeff3830f8d575c, // 0.055195, -0.99848 + 0x3faf656e79f820e0, 0xbfeff095658e71ad, // 0.061321, -0.99812 + 0x3fb1440134d709b2, 0xbfefed58ecb673c4, // 0.067444, -0.99772 + 0x3fb2d52092ce19f6, 0xbfefe9cdad01883a, // 0.073565, -0.99729 + 0x3fb4661179272096, 0xbfefe5f3af2e3940, // 0.079682, -0.99682 + 0x3fb5f6d00a9aa419, 0xbfefe1cafcbd5b09, // 0.085797, -0.99631 + 0x3fb787586a5d5b21, 0xbfefdd539ff1f456, // 0.091909, -0.99577 + 0x3fb917a6bc29b42c, 0xbfefd88da3d12526, // 0.098017, -0.99518 + 0x3fbaa7b724495c04, 0xbfefd37914220b84, // 0.10412, -0.99456 + 0x3fbc3785c79ec2d5, 0xbfefce15fd6da67b, // 0.11022, -0.99391 + 0x3fbdc70ecbae9fc8, 0xbfefc8646cfeb721, // 0.11632, -0.99321 + 0x3fbf564e56a9730e, 0xbfefc26470e19fd3, // 0.12241, -0.99248 + 0x3fc072a047ba831d, 0xbfefbc1617e44186, // 0.1285, -0.99171 + 0x3fc139f0cedaf576, 0xbfefb5797195d741, // 0.13458, -0.9909 + 0x3fc20116d4ec7bce, 0xbfefae8e8e46cfbb, // 0.14066, -0.99006 + 0x3fc2c8106e8e613a, 0xbfefa7557f08a517, // 0.14673, -0.98918 + 0x3fc38edbb0cd8d14, 0xbfef9fce55adb2c8, // 0.1528, -0.98826 + 0x3fc45576b1293e5a, 0xbfef97f924c9099b, // 0.15886, -0.9873 + 0x3fc51bdf8597c5f2, 0xbfef8fd5ffae41db, // 0.16491, -0.98631 + 0x3fc5e214448b3fc6, 0xbfef8764fa714ba9, // 0.17096, -0.98528 + 0x3fc6a81304f64ab2, 0xbfef7ea629e63d6e, // 0.177, -0.98421 + 0x3fc76dd9de50bf31, 0xbfef7599a3a12077, // 0.18304, -0.98311 + 0x3fc83366e89c64c5, 0xbfef6c3f7df5bbb7, // 0.18907, -0.98196 + 0x3fc8f8b83c69a60a, 0xbfef6297cff75cb0, // 0.19509, -0.98079 + 0x3fc9bdcbf2dc4366, 0xbfef58a2b1789e84, // 0.2011, -0.97957 + 0x3fca82a025b00451, 0xbfef4e603b0b2f2d, // 0.20711, -0.97832 + 0x3fcb4732ef3d6722, 0xbfef43d085ff92dd, // 0.21311, -0.97703 + 0x3fcc0b826a7e4f63, 0xbfef38f3ac64e589, // 0.2191, -0.9757 + 0x3fcccf8cb312b286, 0xbfef2dc9c9089a9d, // 0.22508, -0.97434 + 0x3fcd934fe5454311, 0xbfef2252f7763ada, // 0.23106, -0.97294 + 0x3fce56ca1e101a1b, 0xbfef168f53f7205d, // 0.23702, -0.9715 + 0x3fcf19f97b215f1a, 0xbfef0a7efb9230d7, // 0.24298, -0.97003 + 0x3fcfdcdc1adfedf8, 0xbfeefe220c0b95ec, // 0.24893, -0.96852 + 0x3fd04fb80e37fdae, 0xbfeef178a3e473c2, // 0.25487, -0.96698 + 0x3fd0b0d9cfdbdb90, 0xbfeee482e25a9dbc, // 0.26079, -0.96539 + 0x3fd111d262b1f677, 0xbfeed740e7684963, // 0.26671, -0.96378 + 0x3fd172a0d7765177, 0xbfeec9b2d3c3bf84, // 0.27262, -0.96212 + 0x3fd1d3443f4cdb3d, 0xbfeebbd8c8df0b74, // 0.27852, -0.96043 + 0x3fd233bbabc3bb72, 0xbfeeadb2e8e7a88e, // 0.28441, -0.9587 + 0x3fd294062ed59f05, 0xbfee9f4156c62dda, // 0.29028, -0.95694 + 0x3fd2f422daec0386, 0xbfee9084361df7f3, // 0.29615, -0.95514 + 0x3fd35410c2e18152, 0xbfee817bab4cd10d, // 0.30201, -0.95331 + 0x3fd3b3cefa0414b7, 0xbfee7227db6a9744, // 0.30785, -0.95144 + 0x3fd4135c94176602, 0xbfee6288ec48e112, // 0.31368, -0.94953 + 0x3fd472b8a5571054, 0xbfee529f04729ffc, // 0.3195, -0.94759 + 0x3fd4d1e24278e76a, 0xbfee426a4b2bc17e, // 0.32531, -0.94561 + 0x3fd530d880af3c24, 0xbfee31eae870ce25, // 0.33111, -0.94359 + 0x3fd58f9a75ab1fdd, 0xbfee212104f686e5, // 0.33689, -0.94154 + 0x3fd5ee27379ea693, 0xbfee100cca2980ac, // 0.34266, -0.93946 + 0x3fd64c7ddd3f27c6, 0xbfedfeae622dbe2b, // 0.34842, -0.93734 + 0x3fd6aa9d7dc77e16, 0xbfeded05f7de47da, // 0.35416, -0.93518 + 0x3fd7088530fa459e, 0xbfeddb13b6ccc23d, // 0.3599, -0.93299 + 0x3fd766340f2418f6, 0xbfedc8d7cb410260, // 0.36561, -0.93077 + 0x3fd7c3a9311dcce7, 0xbfedb6526238a09b, // 0.37132, -0.92851 + 0x3fd820e3b04eaac4, 0xbfeda383a9668988, // 0.37701, -0.92621 + 0x3fd87de2a6aea963, 0xbfed906bcf328d46, // 0.38268, -0.92388 + 0x3fd8daa52ec8a4af, 0xbfed7d0b02b8ecf9, // 0.38835, -0.92151 + 0x3fd9372a63bc93d7, 0xbfed696173c9e68b, // 0.39399, -0.91911 + 0x3fd993716141bdfe, 0xbfed556f52e93eb1, // 0.39962, -0.91668 + 0x3fd9ef7943a8ed8a, 0xbfed4134d14dc93a, // 0.40524, -0.91421 + 0x3fda4b4127dea1e4, 0xbfed2cb220e0ef9f, // 0.41084, -0.91171 + 0x3fdaa6c82b6d3fc9, 0xbfed17e7743e35dc, // 0.41643, -0.90917 + 0x3fdb020d6c7f4009, 0xbfed02d4feb2bd92, // 0.422, -0.9066 + 0x3fdb5d1009e15cc0, 0xbfeced7af43cc773, // 0.42756, -0.90399 + 0x3fdbb7cf2304bd01, 0xbfecd7d9898b32f6, // 0.43309, -0.90135 + 0x3fdc1249d8011ee7, 0xbfecc1f0f3fcfc5c, // 0.43862, -0.89867 + 0x3fdc6c7f4997000a, 0xbfecabc169a0b901, // 0.44412, -0.89597 + 0x3fdcc66e9931c45d, 0xbfec954b213411f5, // 0.44961, -0.89322 + 0x3fdd2016e8e9db5b, 0xbfec7e8e52233cf3, // 0.45508, -0.89045 + 0x3fdd79775b86e389, 0xbfec678b3488739b, // 0.46054, -0.88764 + 0x3fddd28f1481cc58, 0xbfec5042012b6907, // 0.46598, -0.8848 + 0x3fde2b5d3806f63b, 0xbfec38b2f180bdb1, // 0.4714, -0.88192 + 0x3fde83e0eaf85113, 0xbfec20de3fa971b0, // 0.4768, -0.87901 + 0x3fdedc1952ef78d5, 0xbfec08c426725549, // 0.48218, -0.87607 + 0x3fdf3405963fd068, 0xbfebf064e15377dd, // 0.48755, -0.87309 + 0x3fdf8ba4dbf89aba, 0xbfebd7c0ac6f952a, // 0.4929, -0.87009 + 0x3fdfe2f64be7120f, 0xbfebbed7c49380ea, // 0.49823, -0.86705 + 0x3fe01cfc874c3eb7, 0xbfeba5aa673590d2, // 0.50354, -0.86397 + 0x3fe0485626ae221a, 0xbfeb8c38d27504e9, // 0.50883, -0.86087 + 0x3fe073879922ffed, 0xbfeb728345196e3e, // 0.5141, -0.85773 + 0x3fe09e907417c5e1, 0xbfeb5889fe921405, // 0.51936, -0.85456 + 0x3fe0c9704d5d898f, 0xbfeb3e4d3ef55712, // 0.52459, -0.85136 + 0x3fe0f426bb2a8e7d, 0xbfeb23cd470013b4, // 0.5298, -0.84812 + 0x3fe11eb3541b4b22, 0xbfeb090a58150200, // 0.535, -0.84485 + 0x3fe14915af336ceb, 0xbfeaee04b43c1474, // 0.54017, -0.84155 + 0x3fe1734d63dedb49, 0xbfead2bc9e21d511, // 0.54532, -0.83822 + 0x3fe19d5a09f2b9b8, 0xbfeab7325916c0d4, // 0.55046, -0.83486 + 0x3fe1c73b39ae68c8, 0xbfea9b66290ea1a3, // 0.55557, -0.83147 + 0x3fe1f0f08bbc861b, 0xbfea7f58529fe69d, // 0.56066, -0.82805 + 0x3fe21a799933eb58, 0xbfea63091b02fae2, // 0.56573, -0.82459 + 0x3fe243d5fb98ac1f, 0xbfea4678c8119ac8, // 0.57078, -0.8211 + 0x3fe26d054cdd12df, 0xbfea29a7a0462782, // 0.57581, -0.81758 + 0x3fe2960727629ca8, 0xbfea0c95eabaf937, // 0.58081, -0.81404 + 0x3fe2bedb25faf3ea, 0xbfe9ef43ef29af94, // 0.5858, -0.81046 + 0x3fe2e780e3e8ea16, 0xbfe9d1b1f5ea80d6, // 0.59076, -0.80685 + 0x3fe30ff7fce17035, 0xbfe9b3e047f38741, // 0.5957, -0.80321 + 0x3fe338400d0c8e57, 0xbfe995cf2ed80d22, // 0.60062, -0.79954 + 0x3fe36058b10659f3, 0xbfe9777ef4c7d742, // 0.60551, -0.79584 + 0x3fe3884185dfeb22, 0xbfe958efe48e6dd7, // 0.61038, -0.79211 + 0x3fe3affa292050b9, 0xbfe93a22499263fc, // 0.61523, -0.78835 + 0x3fe3d78238c58343, 0xbfe91b166fd49da2, // 0.62006, -0.78456 + 0x3fe3fed9534556d4, 0xbfe8fbcca3ef940d, // 0.62486, -0.78074 + 0x3fe425ff178e6bb1, 0xbfe8dc45331698cc, // 0.62964, -0.77689 + 0x3fe44cf325091dd6, 0xbfe8bc806b151741, // 0.63439, -0.77301 + 0x3fe473b51b987347, 0xbfe89c7e9a4dd4ab, // 0.63912, -0.7691 + 0x3fe49a449b9b0938, 0xbfe87c400fba2ebf, // 0.64383, -0.76517 + 0x3fe4c0a145ec0004, 0xbfe85bc51ae958cc, // 0.64851, -0.7612 + 0x3fe4e6cabbe3e5e9, 0xbfe83b0e0bff976e, // 0.65317, -0.75721 + 0x3fe50cc09f59a09b, 0xbfe81a1b33b57acc, // 0.65781, -0.75319 + 0x3fe5328292a35596, 0xbfe7f8ece3571771, // 0.66242, -0.74914 + 0x3fe5581038975137, 0xbfe7d7836cc33db2, // 0.667, -0.74506 + 0x3fe57d69348cec9f, 0xbfe7b5df226aafb0, // 0.67156, -0.74095 + 0x3fe5a28d2a5d7250, 0xbfe79400574f55e4, // 0.67609, -0.73682 + 0x3fe5c77bbe65018c, 0xbfe771e75f037261, // 0.6806, -0.73265 + 0x3fe5ec3495837074, 0xbfe74f948da8d28d, // 0.68508, -0.72846 + 0x3fe610b7551d2cde, 0xbfe72d0837efff97, // 0.68954, -0.72425 + 0x3fe63503a31c1be8, 0xbfe70a42b3176d7a, // 0.69397, -0.72 + 0x3fe6591925f0783e, 0xbfe6e74454eaa8ae, // 0.69838, -0.71573 + 0x3fe67cf78491af10, 0xbfe6c40d73c18275, // 0.70275, -0.71143 + 0x3fe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // 0.70711, -0.70711 + 0x3fe6c40d73c18275, 0xbfe67cf78491af10, // 0.71143, -0.70275 + 0x3fe6e74454eaa8ae, 0xbfe6591925f0783e, // 0.71573, -0.69838 + 0x3fe70a42b3176d7a, 0xbfe63503a31c1be8, // 0.72, -0.69397 + 0x3fe72d0837efff97, 0xbfe610b7551d2cde, // 0.72425, -0.68954 + 0x3fe74f948da8d28d, 0xbfe5ec3495837074, // 0.72846, -0.68508 + 0x3fe771e75f037261, 0xbfe5c77bbe65018c, // 0.73265, -0.6806 + 0x3fe79400574f55e4, 0xbfe5a28d2a5d7250, // 0.73682, -0.67609 + 0x3fe7b5df226aafb0, 0xbfe57d69348cec9f, // 0.74095, -0.67156 + 0x3fe7d7836cc33db2, 0xbfe5581038975137, // 0.74506, -0.667 + 0x3fe7f8ece3571771, 0xbfe5328292a35596, // 0.74914, -0.66242 + 0x3fe81a1b33b57acc, 0xbfe50cc09f59a09b, // 0.75319, -0.65781 + 0x3fe83b0e0bff976e, 0xbfe4e6cabbe3e5e9, // 0.75721, -0.65317 + 0x3fe85bc51ae958cc, 0xbfe4c0a145ec0004, // 0.7612, -0.64851 + 0x3fe87c400fba2ebf, 0xbfe49a449b9b0938, // 0.76517, -0.64383 + 0x3fe89c7e9a4dd4ab, 0xbfe473b51b987347, // 0.7691, -0.63912 + 0x3fe8bc806b151741, 0xbfe44cf325091dd6, // 0.77301, -0.63439 + 0x3fe8dc45331698cc, 0xbfe425ff178e6bb1, // 0.77689, -0.62964 + 0x3fe8fbcca3ef940d, 0xbfe3fed9534556d4, // 0.78074, -0.62486 + 0x3fe91b166fd49da2, 0xbfe3d78238c58343, // 0.78456, -0.62006 + 0x3fe93a22499263fc, 0xbfe3affa292050b9, // 0.78835, -0.61523 + 0x3fe958efe48e6dd7, 0xbfe3884185dfeb22, // 0.79211, -0.61038 + 0x3fe9777ef4c7d742, 0xbfe36058b10659f3, // 0.79584, -0.60551 + 0x3fe995cf2ed80d22, 0xbfe338400d0c8e57, // 0.79954, -0.60062 + 0x3fe9b3e047f38741, 0xbfe30ff7fce17035, // 0.80321, -0.5957 + 0x3fe9d1b1f5ea80d6, 0xbfe2e780e3e8ea16, // 0.80685, -0.59076 + 0x3fe9ef43ef29af94, 0xbfe2bedb25faf3ea, // 0.81046, -0.5858 + 0x3fea0c95eabaf937, 0xbfe2960727629ca8, // 0.81404, -0.58081 + 0x3fea29a7a0462782, 0xbfe26d054cdd12df, // 0.81758, -0.57581 + 0x3fea4678c8119ac8, 0xbfe243d5fb98ac1f, // 0.8211, -0.57078 + 0x3fea63091b02fae2, 0xbfe21a799933eb58, // 0.82459, -0.56573 + 0x3fea7f58529fe69d, 0xbfe1f0f08bbc861b, // 0.82805, -0.56066 + 0x3fea9b66290ea1a3, 0xbfe1c73b39ae68c8, // 0.83147, -0.55557 + 0x3feab7325916c0d4, 0xbfe19d5a09f2b9b8, // 0.83486, -0.55046 + 0x3fead2bc9e21d511, 0xbfe1734d63dedb49, // 0.83822, -0.54532 + 0x3feaee04b43c1474, 0xbfe14915af336ceb, // 0.84155, -0.54017 + 0x3feb090a58150200, 0xbfe11eb3541b4b22, // 0.84485, -0.535 + 0x3feb23cd470013b4, 0xbfe0f426bb2a8e7d, // 0.84812, -0.5298 + 0x3feb3e4d3ef55712, 0xbfe0c9704d5d898f, // 0.85136, -0.52459 + 0x3feb5889fe921405, 0xbfe09e907417c5e1, // 0.85456, -0.51936 + 0x3feb728345196e3e, 0xbfe073879922ffed, // 0.85773, -0.5141 + 0x3feb8c38d27504e9, 0xbfe0485626ae221a, // 0.86087, -0.50883 + 0x3feba5aa673590d2, 0xbfe01cfc874c3eb7, // 0.86397, -0.50354 + 0x3febbed7c49380ea, 0xbfdfe2f64be7120f, // 0.86705, -0.49823 + 0x3febd7c0ac6f952a, 0xbfdf8ba4dbf89aba, // 0.87009, -0.4929 + 0x3febf064e15377dd, 0xbfdf3405963fd068, // 0.87309, -0.48755 + 0x3fec08c426725549, 0xbfdedc1952ef78d5, // 0.87607, -0.48218 + 0x3fec20de3fa971b0, 0xbfde83e0eaf85113, // 0.87901, -0.4768 + 0x3fec38b2f180bdb1, 0xbfde2b5d3806f63b, // 0.88192, -0.4714 + 0x3fec5042012b6907, 0xbfddd28f1481cc58, // 0.8848, -0.46598 + 0x3fec678b3488739b, 0xbfdd79775b86e389, // 0.88764, -0.46054 + 0x3fec7e8e52233cf3, 0xbfdd2016e8e9db5b, // 0.89045, -0.45508 + 0x3fec954b213411f5, 0xbfdcc66e9931c45d, // 0.89322, -0.44961 + 0x3fecabc169a0b901, 0xbfdc6c7f4997000a, // 0.89597, -0.44412 + 0x3fecc1f0f3fcfc5c, 0xbfdc1249d8011ee7, // 0.89867, -0.43862 + 0x3fecd7d9898b32f6, 0xbfdbb7cf2304bd01, // 0.90135, -0.43309 + 0x3feced7af43cc773, 0xbfdb5d1009e15cc0, // 0.90399, -0.42756 + 0x3fed02d4feb2bd92, 0xbfdb020d6c7f4009, // 0.9066, -0.422 + 0x3fed17e7743e35dc, 0xbfdaa6c82b6d3fc9, // 0.90917, -0.41643 + 0x3fed2cb220e0ef9f, 0xbfda4b4127dea1e4, // 0.91171, -0.41084 + 0x3fed4134d14dc93a, 0xbfd9ef7943a8ed8a, // 0.91421, -0.40524 + 0x3fed556f52e93eb1, 0xbfd993716141bdfe, // 0.91668, -0.39962 + 0x3fed696173c9e68b, 0xbfd9372a63bc93d7, // 0.91911, -0.39399 + 0x3fed7d0b02b8ecf9, 0xbfd8daa52ec8a4af, // 0.92151, -0.38835 + 0x3fed906bcf328d46, 0xbfd87de2a6aea963, // 0.92388, -0.38268 + 0x3feda383a9668988, 0xbfd820e3b04eaac4, // 0.92621, -0.37701 + 0x3fedb6526238a09b, 0xbfd7c3a9311dcce7, // 0.92851, -0.37132 + 0x3fedc8d7cb410260, 0xbfd766340f2418f6, // 0.93077, -0.36561 + 0x3feddb13b6ccc23d, 0xbfd7088530fa459e, // 0.93299, -0.3599 + 0x3feded05f7de47da, 0xbfd6aa9d7dc77e16, // 0.93518, -0.35416 + 0x3fedfeae622dbe2b, 0xbfd64c7ddd3f27c6, // 0.93734, -0.34842 + 0x3fee100cca2980ac, 0xbfd5ee27379ea693, // 0.93946, -0.34266 + 0x3fee212104f686e5, 0xbfd58f9a75ab1fdd, // 0.94154, -0.33689 + 0x3fee31eae870ce25, 0xbfd530d880af3c24, // 0.94359, -0.33111 + 0x3fee426a4b2bc17e, 0xbfd4d1e24278e76a, // 0.94561, -0.32531 + 0x3fee529f04729ffc, 0xbfd472b8a5571054, // 0.94759, -0.3195 + 0x3fee6288ec48e112, 0xbfd4135c94176602, // 0.94953, -0.31368 + 0x3fee7227db6a9744, 0xbfd3b3cefa0414b7, // 0.95144, -0.30785 + 0x3fee817bab4cd10d, 0xbfd35410c2e18152, // 0.95331, -0.30201 + 0x3fee9084361df7f3, 0xbfd2f422daec0386, // 0.95514, -0.29615 + 0x3fee9f4156c62dda, 0xbfd294062ed59f05, // 0.95694, -0.29028 + 0x3feeadb2e8e7a88e, 0xbfd233bbabc3bb72, // 0.9587, -0.28441 + 0x3feebbd8c8df0b74, 0xbfd1d3443f4cdb3d, // 0.96043, -0.27852 + 0x3feec9b2d3c3bf84, 0xbfd172a0d7765177, // 0.96212, -0.27262 + 0x3feed740e7684963, 0xbfd111d262b1f677, // 0.96378, -0.26671 + 0x3feee482e25a9dbc, 0xbfd0b0d9cfdbdb90, // 0.96539, -0.26079 + 0x3feef178a3e473c2, 0xbfd04fb80e37fdae, // 0.96698, -0.25487 + 0x3feefe220c0b95ec, 0xbfcfdcdc1adfedf8, // 0.96852, -0.24893 + 0x3fef0a7efb9230d7, 0xbfcf19f97b215f1a, // 0.97003, -0.24298 + 0x3fef168f53f7205d, 0xbfce56ca1e101a1b, // 0.9715, -0.23702 + 0x3fef2252f7763ada, 0xbfcd934fe5454311, // 0.97294, -0.23106 + 0x3fef2dc9c9089a9d, 0xbfcccf8cb312b286, // 0.97434, -0.22508 + 0x3fef38f3ac64e589, 0xbfcc0b826a7e4f63, // 0.9757, -0.2191 + 0x3fef43d085ff92dd, 0xbfcb4732ef3d6722, // 0.97703, -0.21311 + 0x3fef4e603b0b2f2d, 0xbfca82a025b00451, // 0.97832, -0.20711 + 0x3fef58a2b1789e84, 0xbfc9bdcbf2dc4366, // 0.97957, -0.2011 + 0x3fef6297cff75cb0, 0xbfc8f8b83c69a60a, // 0.98079, -0.19509 + 0x3fef6c3f7df5bbb7, 0xbfc83366e89c64c5, // 0.98196, -0.18907 + 0x3fef7599a3a12077, 0xbfc76dd9de50bf31, // 0.98311, -0.18304 + 0x3fef7ea629e63d6e, 0xbfc6a81304f64ab2, // 0.98421, -0.177 + 0x3fef8764fa714ba9, 0xbfc5e214448b3fc6, // 0.98528, -0.17096 + 0x3fef8fd5ffae41db, 0xbfc51bdf8597c5f2, // 0.98631, -0.16491 + 0x3fef97f924c9099b, 0xbfc45576b1293e5a, // 0.9873, -0.15886 + 0x3fef9fce55adb2c8, 0xbfc38edbb0cd8d14, // 0.98826, -0.1528 + 0x3fefa7557f08a517, 0xbfc2c8106e8e613a, // 0.98918, -0.14673 + 0x3fefae8e8e46cfbb, 0xbfc20116d4ec7bce, // 0.99006, -0.14066 + 0x3fefb5797195d741, 0xbfc139f0cedaf576, // 0.9909, -0.13458 + 0x3fefbc1617e44186, 0xbfc072a047ba831d, // 0.99171, -0.1285 + 0x3fefc26470e19fd3, 0xbfbf564e56a9730e, // 0.99248, -0.12241 + 0x3fefc8646cfeb721, 0xbfbdc70ecbae9fc8, // 0.99321, -0.11632 + 0x3fefce15fd6da67b, 0xbfbc3785c79ec2d5, // 0.99391, -0.11022 + 0x3fefd37914220b84, 0xbfbaa7b724495c04, // 0.99456, -0.10412 + 0x3fefd88da3d12526, 0xbfb917a6bc29b42c, // 0.99518, -0.098017 + 0x3fefdd539ff1f456, 0xbfb787586a5d5b21, // 0.99577, -0.091909 + 0x3fefe1cafcbd5b09, 0xbfb5f6d00a9aa419, // 0.99631, -0.085797 + 0x3fefe5f3af2e3940, 0xbfb4661179272096, // 0.99682, -0.079682 + 0x3fefe9cdad01883a, 0xbfb2d52092ce19f6, // 0.99729, -0.073565 + 0x3fefed58ecb673c4, 0xbfb1440134d709b2, // 0.99772, -0.067444 + 0x3feff095658e71ad, 0xbfaf656e79f820e0, // 0.99812, -0.061321 + 0x3feff3830f8d575c, 0xbfac428d12c0d7e3, // 0.99848, -0.055195 + 0x3feff621e3796d7e, 0xbfa91f65f10dd814, // 0.9988, -0.049068 + 0x3feff871dadb81df, 0xbfa5fc00d290cd43, // 0.99908, -0.042938 + 0x3feffa72effef75d, 0xbfa2d865759455cd, // 0.99932, -0.036807 + 0x3feffc251df1d3f8, 0xbf9f693731d1cf01, // 0.99953, -0.030675 + 0x3feffd886084cd0d, 0xbf992155f7a3667e, // 0.9997, -0.024541 + 0x3feffe9cb44b51a1, 0xbf92d936bbe30efd, // 0.99983, -0.018407 + 0x3fefff62169b92db, 0xbf8921d1fcdec784, // 0.99992, -0.012272 + 0x3fefffd8858e8a92, 0xbf7921f0fe670071, // 0.99998,-0.0061359 +}; + +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_F64_2048) +/** + @par + Example code for Double Precision Floating-point Twiddle factors Generation: + @par + 
for (i = 0; i< N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/(float)N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 2048, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const uint64_t twiddleCoefF64_2048[4096] = { + 0x3ff0000000000000, 0x0000000000000000, // 1, 0 + 0x3feffff621621d02, 0x3f6921f8becca4ba, // 1, 0.003068 + 0x3fefffd8858e8a92, 0x3f7921f0fe670071, // 0.99998, 0.0061359 + 0x3fefffa72c978c4f, 0x3f82d96b0e509703, // 0.99996, 0.0092038 + 0x3fefff62169b92db, 0x3f8921d1fcdec784, // 0.99992, 0.012272 + 0x3fefff0943c53bd1, 0x3f8f6a296ab997ca, // 0.99988, 0.015339 + 0x3feffe9cb44b51a1, 0x3f92d936bbe30efd, // 0.99983, 0.018407 + 0x3feffe1c6870cb77, 0x3f95fd4d21fab226, // 0.99977, 0.021474 + 0x3feffd886084cd0d, 0x3f992155f7a3667e, // 0.9997, 0.024541 + 0x3feffce09ce2a679, 0x3f9c454f4ce53b1c, // 0.99962, 0.027608 + 0x3feffc251df1d3f8, 0x3f9f693731d1cf01, // 0.99953, 0.030675 + 0x3feffb55e425fdae, 0x3fa14685db42c17e, // 0.99943, 0.033741 + 0x3feffa72effef75d, 0x3fa2d865759455cd, // 0.99932, 0.036807 + 0x3feff97c4208c014, 0x3fa46a396ff86179, // 0.9992, 0.039873 + 0x3feff871dadb81df, 0x3fa5fc00d290cd43, // 0.99908, 0.042938 + 0x3feff753bb1b9164, 0x3fa78dbaa5874685, // 0.99894, 0.046003 + 0x3feff621e3796d7e, 0x3fa91f65f10dd814, // 0.9988, 0.049068 + 0x3feff4dc54b1bed3, 0x3faab101bd5f8317, // 0.99864, 0.052132 + 0x3feff3830f8d575c, 0x3fac428d12c0d7e3, // 0.99848, 0.055195 + 0x3feff21614e131ed, 0x3fadd406f9808ec8, // 0.9983, 0.058258 + 0x3feff095658e71ad, 0x3faf656e79f820e0, // 0.99812, 0.061321 + 0x3fefef0102826191, 0x3fb07b614e463064, // 0.99793, 0.064383 + 0x3fefed58ecb673c4, 0x3fb1440134d709b2, // 0.99772, 0.067444 + 0x3fefeb9d2530410f, 0x3fb20c9674ed444c, // 0.99751, 0.070505 + 0x3fefe9cdad01883a, 0x3fb2d52092ce19f6, // 0.99729, 0.073565 + 0x3fefe7ea85482d60, 0x3fb39d9f12c5a299, // 0.99706, 0.076624 + 0x3fefe5f3af2e3940, 0x3fb4661179272096, // 0.99682, 0.079682 + 0x3fefe3e92be9d886, 0x3fb52e774a4d4d0a, // 0.99657, 0.08274 + 0x3fefe1cafcbd5b09, 0x3fb5f6d00a9aa419, // 0.99631, 0.085797 + 0x3fefdf9922f73307, 0x3fb6bf1b3e79b129, // 0.99604, 0.088854 + 0x3fefdd539ff1f456, 0x3fb787586a5d5b21, // 0.99577, 0.091909 + 0x3fefdafa7514538c, 0x3fb84f8712c130a0, // 0.99548, 0.094963 + 0x3fefd88da3d12526, 0x3fb917a6bc29b42c, // 0.99518, 0.098017 + 0x3fefd60d2da75c9e, 0x3fb9dfb6eb24a85c, // 0.99488, 0.10107 + 0x3fefd37914220b84, 0x3fbaa7b724495c04, // 0.99456, 0.10412 + 0x3fefd0d158d86087, 0x3fbb6fa6ec38f64c, // 0.99424, 0.10717 + 0x3fefce15fd6da67b, 0x3fbc3785c79ec2d5, // 0.99391, 0.11022 + 0x3fefcb4703914354, 0x3fbcff533b307dc1, // 0.99356, 0.11327 + 0x3fefc8646cfeb721, 0x3fbdc70ecbae9fc8, // 0.99321, 0.11632 + 0x3fefc56e3b7d9af6, 0x3fbe8eb7fde4aa3e, // 0.99285, 0.11937 + 0x3fefc26470e19fd3, 0x3fbf564e56a9730e, // 0.99248, 0.12241 + 0x3fefbf470f0a8d88, 0x3fc00ee8ad6fb85b, // 0.9921, 0.12545 + 0x3fefbc1617e44186, 0x3fc072a047ba831d, // 0.99171, 0.1285 + 0x3fefb8d18d66adb7, 0x3fc0d64dbcb26786, // 0.99131, 0.13154 + 0x3fefb5797195d741, 0x3fc139f0cedaf576, // 0.9909, 0.13458 + 0x3fefb20dc681d54d, 0x3fc19d8940be24e7, // 0.99049, 0.13762 + 0x3fefae8e8e46cfbb, 0x3fc20116d4ec7bce, // 0.99006, 0.14066 + 0x3fefaafbcb0cfddc, 0x3fc264994dfd340a, // 0.98962, 0.1437 + 0x3fefa7557f08a517, 0x3fc2c8106e8e613a, // 0.98918, 0.14673 + 0x3fefa39bac7a1791, 0x3fc32b7bf94516a7, // 0.98872, 0.14976 + 0x3fef9fce55adb2c8, 0x3fc38edbb0cd8d14, // 0.98826, 0.1528 + 0x3fef9bed7cfbde29, 0x3fc3f22f57db4893, // 0.98778, 0.15583 + 0x3fef97f924c9099b, 0x3fc45576b1293e5a, // 0.9873, 0.15886 + 0x3fef93f14f85ac08, 0x3fc4b8b17f79fa88, // 0.98681, 0.16189 + 0x3fef8fd5ffae41db, 0x3fc51bdf8597c5f2, // 0.98631, 0.16491 + 0x3fef8ba737cb4b78, 0x3fc57f008654cbde, // 0.9858, 0.16794 + 0x3fef8764fa714ba9, 0x3fc5e214448b3fc6, // 0.98528, 0.17096 + 0x3fef830f4a40c60c, 0x3fc6451a831d830d, // 0.98475, 0.17398 + 0x3fef7ea629e63d6e, 0x3fc6a81304f64ab2, // 0.98421, 0.177 + 0x3fef7a299c1a322a, 0x3fc70afd8d08c4ff, // 0.98366, 0.18002 + 0x3fef7599a3a12077, 0x3fc76dd9de50bf31, // 0.98311, 0.18304 + 0x3fef70f6434b7eb7, 0x3fc7d0a7bbd2cb1b, // 0.98254, 0.18606 + 0x3fef6c3f7df5bbb7, 0x3fc83366e89c64c5, // 0.98196, 0.18907 + 0x3fef677556883cee, 0x3fc8961727c41804, // 0.98138, 0.19208 + 0x3fef6297cff75cb0, 0x3fc8f8b83c69a60a, // 0.98079, 0.19509 + 0x3fef5da6ed43685d, 0x3fc95b49e9b62af9, // 0.98018, 0.1981 + 0x3fef58a2b1789e84, 0x3fc9bdcbf2dc4366, // 0.97957, 0.2011 + 0x3fef538b1faf2d07, 0x3fca203e1b1831da, // 0.97895, 0.20411 + 0x3fef4e603b0b2f2d, 0x3fca82a025b00451, // 0.97832, 0.20711 + 0x3fef492206bcabb4, 0x3fcae4f1d5f3b9ab, // 0.97768, 0.21011 + 0x3fef43d085ff92dd, 0x3fcb4732ef3d6722, // 0.97703, 0.21311 + 0x3fef3e6bbc1bbc65, 0x3fcba96334f15dad, // 0.97637, 0.21611 + 0x3fef38f3ac64e589, 0x3fcc0b826a7e4f63, // 0.9757, 0.2191 + 0x3fef33685a3aaef0, 0x3fcc6d90535d74dc, // 0.97503, 0.22209 + 0x3fef2dc9c9089a9d, 0x3fcccf8cb312b286, // 0.97434, 0.22508 + 0x3fef2817fc4609ce, 0x3fcd31774d2cbdee, // 0.97364, 0.22807 + 0x3fef2252f7763ada, 0x3fcd934fe5454311, // 0.97294, 0.23106 + 0x3fef1c7abe284708, 0x3fcdf5163f01099a, // 0.97223, 0.23404 + 0x3fef168f53f7205d, 0x3fce56ca1e101a1b, // 0.9715, 0.23702 + 0x3fef1090bc898f5f, 0x3fceb86b462de348, // 0.97077, 0.24 + 0x3fef0a7efb9230d7, 0x3fcf19f97b215f1a, // 0.97003, 0.24298 + 0x3fef045a14cf738c, 0x3fcf7b7480bd3801, // 0.96928, 0.24596 + 0x3feefe220c0b95ec, 0x3fcfdcdc1adfedf8, // 0.96852, 0.24893 + 0x3feef7d6e51ca3c0, 0x3fd01f1806b9fdd2, // 0.96775, 0.2519 + 0x3feef178a3e473c2, 0x3fd04fb80e37fdae, // 0.96698, 0.25487 + 0x3feeeb074c50a544, 0x3fd0804e05eb661e, // 0.96619, 0.25783 + 0x3feee482e25a9dbc, 0x3fd0b0d9cfdbdb90, // 0.96539, 0.26079 + 0x3feeddeb6a078651, 0x3fd0e15b4e1749cd, // 0.96459, 0.26375 + 0x3feed740e7684963, 0x3fd111d262b1f677, // 0.96378, 0.26671 + 0x3feed0835e999009, 0x3fd1423eefc69378, // 0.96295, 0.26967 + 0x3feec9b2d3c3bf84, 0x3fd172a0d7765177, // 0.96212, 0.27262 + 0x3feec2cf4b1af6b2, 0x3fd1a2f7fbe8f243, // 0.96128, 0.27557 + 0x3feebbd8c8df0b74, 0x3fd1d3443f4cdb3d, // 0.96043, 0.27852 + 0x3feeb4cf515b8811, 0x3fd2038583d727bd, // 0.95957, 0.28146 + 0x3feeadb2e8e7a88e, 0x3fd233bbabc3bb72, // 0.9587, 0.28441 + 0x3feea68393e65800, 0x3fd263e6995554ba, // 0.95783, 0.28735 + 0x3fee9f4156c62dda, 0x3fd294062ed59f05, // 0.95694, 0.29028 + 0x3fee97ec36016b30, 0x3fd2c41a4e954520, // 0.95605, 0.29322 + 0x3fee9084361df7f3, 0x3fd2f422daec0386, // 0.95514, 0.29615 + 0x3fee89095bad6025, 0x3fd3241fb638baaf, // 0.95423, 0.29908 + 0x3fee817bab4cd10d, 0x3fd35410c2e18152, // 0.95331, 0.30201 + 0x3fee79db29a5165a, 0x3fd383f5e353b6aa, // 0.95238, 0.30493 + 0x3fee7227db6a9744, 0x3fd3b3cefa0414b7, // 0.95144, 0.30785 + 0x3fee6a61c55d53a7, 0x3fd3e39be96ec271, // 0.95049, 0.31077 + 0x3fee6288ec48e112, 0x3fd4135c94176602, // 0.94953, 0.31368 + 0x3fee5a9d550467d3, 0x3fd44310dc8936f0, // 0.94856, 0.31659 + 0x3fee529f04729ffc, 0x3fd472b8a5571054, // 0.94759, 0.3195 + 0x3fee4a8dff81ce5e, 0x3fd4a253d11b82f3, // 0.9466, 0.32241 + 0x3fee426a4b2bc17e, 0x3fd4d1e24278e76a, // 0.94561, 0.32531 + 0x3fee3a33ec75ce85, 0x3fd50163dc197047, // 0.9446, 0.32821 + 0x3fee31eae870ce25, 0x3fd530d880af3c24, // 0.94359, 0.33111 + 0x3fee298f4439197a, 0x3fd5604012f467b4, // 0.94257, 0.334 + 0x3fee212104f686e5, 0x3fd58f9a75ab1fdd, // 0.94154, 0.33689 + 0x3fee18a02fdc66d9, 0x3fd5bee78b9db3b6, // 0.94051, 0.33978 + 0x3fee100cca2980ac, 0x3fd5ee27379ea693, // 0.93946, 0.34266 + 0x3fee0766d9280f54, 0x3fd61d595c88c203, // 0.9384, 0.34554 + 0x3fedfeae622dbe2b, 0x3fd64c7ddd3f27c6, // 0.93734, 0.34842 + 0x3fedf5e36a9ba59c, 0x3fd67b949cad63ca, // 0.93627, 0.35129 + 0x3feded05f7de47da, 0x3fd6aa9d7dc77e16, // 0.93518, 0.35416 + 0x3fede4160f6d8d81, 0x3fd6d998638a0cb5, // 0.93409, 0.35703 + 0x3feddb13b6ccc23d, 0x3fd7088530fa459e, // 0.93299, 0.3599 + 0x3fedd1fef38a915a, 0x3fd73763c9261092, // 0.93188, 0.36276 + 0x3fedc8d7cb410260, 0x3fd766340f2418f6, // 0.93077, 0.36561 + 0x3fedbf9e4395759a, 0x3fd794f5e613dfae, // 0.92964, 0.36847 + 0x3fedb6526238a09b, 0x3fd7c3a9311dcce7, // 0.92851, 0.37132 + 0x3fedacf42ce68ab9, 0x3fd7f24dd37341e3, // 0.92736, 0.37416 + 0x3feda383a9668988, 0x3fd820e3b04eaac4, // 0.92621, 0.37701 + 0x3fed9a00dd8b3d46, 0x3fd84f6aaaf3903f, // 0.92505, 0.37985 + 0x3fed906bcf328d46, 0x3fd87de2a6aea963, // 0.92388, 0.38268 + 0x3fed86c48445a450, 0x3fd8ac4b86d5ed44, // 0.9227, 0.38552 + 0x3fed7d0b02b8ecf9, 0x3fd8daa52ec8a4af, // 0.92151, 0.38835 + 0x3fed733f508c0dff, 0x3fd908ef81ef7bd1, // 0.92032, 0.39117 + 0x3fed696173c9e68b, 0x3fd9372a63bc93d7, // 0.91911, 0.39399 + 0x3fed5f7172888a7f, 0x3fd96555b7ab948f, // 0.9179, 0.39681 + 0x3fed556f52e93eb1, 0x3fd993716141bdfe, // 0.91668, 0.39962 + 0x3fed4b5b1b187524, 0x3fd9c17d440df9f2, // 0.91545, 0.40243 + 0x3fed4134d14dc93a, 0x3fd9ef7943a8ed8a, // 0.91421, 0.40524 + 0x3fed36fc7bcbfbdc, 0x3fda1d6543b50ac0, // 0.91296, 0.40804 + 0x3fed2cb220e0ef9f, 0x3fda4b4127dea1e4, // 0.91171, 0.41084 + 0x3fed2255c6e5a4e1, 0x3fda790cd3dbf31a, // 0.91044, 0.41364 + 0x3fed17e7743e35dc, 0x3fdaa6c82b6d3fc9, // 0.90917, 0.41643 + 0x3fed0d672f59d2b9, 0x3fdad473125cdc08, // 0.90789, 0.41922 + 0x3fed02d4feb2bd92, 0x3fdb020d6c7f4009, // 0.9066, 0.422 + 0x3fecf830e8ce467b, 0x3fdb2f971db31972, // 0.9053, 0.42478 + 0x3feced7af43cc773, 0x3fdb5d1009e15cc0, // 0.90399, 0.42756 + 0x3fece2b32799a060, 0x3fdb8a7814fd5693, // 0.90267, 0.43033 + 0x3fecd7d9898b32f6, 0x3fdbb7cf2304bd01, // 0.90135, 0.43309 + 0x3fecccee20c2de9f, 0x3fdbe51517ffc0d9, // 0.90002, 0.43586 + 0x3fecc1f0f3fcfc5c, 0x3fdc1249d8011ee7, // 0.89867, 0.43862 + 0x3fecb6e20a00da99, 0x3fdc3f6d47263129, // 0.89732, 0.44137 + 0x3fecabc169a0b901, 0x3fdc6c7f4997000a, // 0.89597, 0.44412 + 0x3feca08f19b9c449, 0x3fdc997fc3865388, // 0.8946, 0.44687 + 0x3fec954b213411f5, 0x3fdcc66e9931c45d, // 0.89322, 0.44961 + 0x3fec89f587029c13, 0x3fdcf34baee1cd21, // 0.89184, 0.45235 + 0x3fec7e8e52233cf3, 0x3fdd2016e8e9db5b, // 0.89045, 0.45508 + 0x3fec7315899eaad7, 0x3fdd4cd02ba8609c, // 0.88905, 0.45781 + 0x3fec678b3488739b, 0x3fdd79775b86e389, // 0.88764, 0.46054 + 0x3fec5bef59fef85a, 0x3fdda60c5cfa10d8, // 0.88622, 0.46326 + 0x3fec5042012b6907, 0x3fddd28f1481cc58, // 0.8848, 0.46598 + 0x3fec44833141c004, 0x3fddfeff66a941de, // 0.88336, 0.46869 + 0x3fec38b2f180bdb1, 0x3fde2b5d3806f63b, // 0.88192, 0.4714 + 0x3fec2cd14931e3f1, 0x3fde57a86d3cd824, // 0.88047, 0.4741 + 0x3fec20de3fa971b0, 0x3fde83e0eaf85113, // 0.87901, 0.4768 + 0x3fec14d9dc465e58, 0x3fdeb00695f25620, // 0.87755, 0.47949 + 0x3fec08c426725549, 0x3fdedc1952ef78d5, // 0.87607, 0.48218 + 0x3febfc9d25a1b147, 0x3fdf081906bff7fd, // 0.87459, 0.48487 + 0x3febf064e15377dd, 0x3fdf3405963fd068, // 0.87309, 0.48755 + 0x3febe41b611154c1, 0x3fdf5fdee656cda3, // 0.8716, 0.49023 + 0x3febd7c0ac6f952a, 0x3fdf8ba4dbf89aba, // 0.87009, 0.4929 + 0x3febcb54cb0d2327, 0x3fdfb7575c24d2de, // 0.86857, 0.49557 + 0x3febbed7c49380ea, 0x3fdfe2f64be7120f, // 0.86705, 0.49823 + 0x3febb249a0b6c40d, 0x3fe00740c82b82e0, // 0.86551, 0.50089 + 0x3feba5aa673590d2, 0x3fe01cfc874c3eb7, // 0.86397, 0.50354 + 0x3feb98fa1fd9155e, 0x3fe032ae55edbd95, // 0.86242, 0.50619 + 0x3feb8c38d27504e9, 0x3fe0485626ae221a, // 0.86087, 0.50883 + 0x3feb7f6686e792ea, 0x3fe05df3ec31b8b6, // 0.8593, 0.51147 + 0x3feb728345196e3e, 0x3fe073879922ffed, // 0.85773, 0.5141 + 0x3feb658f14fdbc47, 0x3fe089112032b08c, // 0.85615, 0.51673 + 0x3feb5889fe921405, 0x3fe09e907417c5e1, // 0.85456, 0.51936 + 0x3feb4b7409de7925, 0x3fe0b405878f85ec, // 0.85296, 0.52198 + 0x3feb3e4d3ef55712, 0x3fe0c9704d5d898f, // 0.85136, 0.52459 + 0x3feb3115a5f37bf4, 0x3fe0ded0b84bc4b5, // 0.84974, 0.5272 + 0x3feb23cd470013b4, 0x3fe0f426bb2a8e7d, // 0.84812, 0.5298 + 0x3feb16742a4ca2f5, 0x3fe1097248d0a956, // 0.84649, 0.5324 + 0x3feb090a58150200, 0x3fe11eb3541b4b22, // 0.84485, 0.535 + 0x3feafb8fd89f57b6, 0x3fe133e9cfee254e, // 0.84321, 0.53759 + 0x3feaee04b43c1474, 0x3fe14915af336ceb, // 0.84155, 0.54017 + 0x3feae068f345ecef, 0x3fe15e36e4dbe2bc, // 0.83989, 0.54275 + 0x3fead2bc9e21d511, 0x3fe1734d63dedb49, // 0.83822, 0.54532 + 0x3feac4ffbd3efac8, 0x3fe188591f3a46e5, // 0.83655, 0.54789 + 0x3feab7325916c0d4, 0x3fe19d5a09f2b9b8, // 0.83486, 0.55046 + 0x3feaa9547a2cb98e, 0x3fe1b250171373be, // 0.83317, 0.55302 + 0x3fea9b66290ea1a3, 0x3fe1c73b39ae68c8, // 0.83147, 0.55557 + 0x3fea8d676e545ad2, 0x3fe1dc1b64dc4872, // 0.82976, 0.55812 + 0x3fea7f58529fe69d, 0x3fe1f0f08bbc861b, // 0.82805, 0.56066 + 0x3fea7138de9d60f5, 0x3fe205baa17560d6, // 0.82632, 0.5632 + 0x3fea63091b02fae2, 0x3fe21a799933eb58, // 0.82459, 0.56573 + 0x3fea54c91090f524, 0x3fe22f2d662c13e1, // 0.82285, 0.56826 + 0x3fea4678c8119ac8, 0x3fe243d5fb98ac1f, // 0.8211, 0.57078 + 0x3fea38184a593bc6, 0x3fe258734cbb7110, // 0.81935, 0.5733 + 0x3fea29a7a0462782, 0x3fe26d054cdd12df, // 0.81758, 0.57581 + 0x3fea1b26d2c0a75e, 0x3fe2818bef4d3cba, // 0.81581, 0.57831 + 0x3fea0c95eabaf937, 0x3fe2960727629ca8, // 0.81404, 0.58081 + 0x3fe9fdf4f13149de, 0x3fe2aa76e87aeb58, // 0.81225, 0.58331 + 0x3fe9ef43ef29af94, 0x3fe2bedb25faf3ea, // 0.81046, 0.5858 + 0x3fe9e082edb42472, 0x3fe2d333d34e9bb7, // 0.80866, 0.58828 + 0x3fe9d1b1f5ea80d6, 0x3fe2e780e3e8ea16, // 0.80685, 0.59076 + 0x3fe9c2d110f075c3, 0x3fe2fbc24b441015, // 0.80503, 0.59323 + 0x3fe9b3e047f38741, 0x3fe30ff7fce17035, // 0.80321, 0.5957 + 0x3fe9a4dfa42b06b2, 0x3fe32421ec49a620, // 0.80138, 0.59816 + 0x3fe995cf2ed80d22, 0x3fe338400d0c8e57, // 0.79954, 0.60062 + 0x3fe986aef1457594, 0x3fe34c5252c14de1, // 0.79769, 0.60307 + 0x3fe9777ef4c7d742, 0x3fe36058b10659f3, // 0.79584, 0.60551 + 0x3fe9683f42bd7fe1, 0x3fe374531b817f8d, // 0.79398, 0.60795 + 0x3fe958efe48e6dd7, 0x3fe3884185dfeb22, // 0.79211, 0.61038 + 0x3fe94990e3ac4a6c, 0x3fe39c23e3d63029, // 0.79023, 0.61281 + 0x3fe93a22499263fc, 0x3fe3affa292050b9, // 0.78835, 0.61523 + 0x3fe92aa41fc5a815, 0x3fe3c3c44981c517, // 0.78646, 0.61765 + 0x3fe91b166fd49da2, 0x3fe3d78238c58343, // 0.78456, 0.62006 + 0x3fe90b7943575efe, 0x3fe3eb33eabe0680, // 0.78265, 0.62246 + 0x3fe8fbcca3ef940d, 0x3fe3fed9534556d4, // 0.78074, 0.62486 + 0x3fe8ec109b486c49, 0x3fe41272663d108c, // 0.77882, 0.62725 + 0x3fe8dc45331698cc, 0x3fe425ff178e6bb1, // 0.77689, 0.62964 + 0x3fe8cc6a75184655, 0x3fe4397f5b2a4380, // 0.77495, 0.63202 + 0x3fe8bc806b151741, 0x3fe44cf325091dd6, // 0.77301, 0.63439 + 0x3fe8ac871ede1d88, 0x3fe4605a692b32a2, // 0.77106, 0.63676 + 0x3fe89c7e9a4dd4ab, 0x3fe473b51b987347, // 0.7691, 0.63912 + 0x3fe88c66e7481ba1, 0x3fe48703306091fe, // 0.76714, 0.64148 + 0x3fe87c400fba2ebf, 0x3fe49a449b9b0938, // 0.76517, 0.64383 + 0x3fe86c0a1d9aa195, 0x3fe4ad79516722f0, // 0.76319, 0.64618 + 0x3fe85bc51ae958cc, 0x3fe4c0a145ec0004, // 0.7612, 0.64851 + 0x3fe84b7111af83f9, 0x3fe4d3bc6d589f80, // 0.75921, 0.65085 + 0x3fe83b0e0bff976e, 0x3fe4e6cabbe3e5e9, // 0.75721, 0.65317 + 0x3fe82a9c13f545ff, 0x3fe4f9cc25cca486, // 0.7552, 0.65549 + 0x3fe81a1b33b57acc, 0x3fe50cc09f59a09b, // 0.75319, 0.65781 + 0x3fe8098b756e52fa, 0x3fe51fa81cd99aa6, // 0.75117, 0.66011 + 0x3fe7f8ece3571771, 0x3fe5328292a35596, // 0.74914, 0.66242 + 0x3fe7e83f87b03686, 0x3fe5454ff5159dfb, // 0.7471, 0.66471 + 0x3fe7d7836cc33db2, 0x3fe5581038975137, // 0.74506, 0.667 + 0x3fe7c6b89ce2d333, 0x3fe56ac35197649e, // 0.74301, 0.66928 + 0x3fe7b5df226aafb0, 0x3fe57d69348cec9f, // 0.74095, 0.67156 + 0x3fe7a4f707bf97d2, 0x3fe59001d5f723df, // 0.73889, 0.67383 + 0x3fe79400574f55e4, 0x3fe5a28d2a5d7250, // 0.73682, 0.67609 + 0x3fe782fb1b90b35b, 0x3fe5b50b264f7448, // 0.73474, 0.67835 + 0x3fe771e75f037261, 0x3fe5c77bbe65018c, // 0.73265, 0.6806 + 0x3fe760c52c304764, 0x3fe5d9dee73e345c, // 0.73056, 0.68285 + 0x3fe74f948da8d28d, 0x3fe5ec3495837074, // 0.72846, 0.68508 + 0x3fe73e558e079942, 0x3fe5fe7cbde56a0f, // 0.72636, 0.68732 + 0x3fe72d0837efff97, 0x3fe610b7551d2cde, // 0.72425, 0.68954 + 0x3fe71bac960e41bf, 0x3fe622e44fec22ff, // 0.72213, 0.69176 + 0x3fe70a42b3176d7a, 0x3fe63503a31c1be8, // 0.72, 0.69397 + 0x3fe6f8ca99c95b75, 0x3fe64715437f535b, // 0.71787, 0.69618 + 0x3fe6e74454eaa8ae, 0x3fe6591925f0783e, // 0.71573, 0.69838 + 0x3fe6d5afef4aafcc, 0x3fe66b0f3f52b386, // 0.71358, 0.70057 + 0x3fe6c40d73c18275, 0x3fe67cf78491af10, // 0.71143, 0.70275 + 0x3fe6b25ced2fe29c, 0x3fe68ed1eaa19c71, // 0.70927, 0.70493 + 0x3fe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // 0.70711, 0.70711 + 0x3fe68ed1eaa19c71, 0x3fe6b25ced2fe29c, // 0.70493, 0.70927 + 0x3fe67cf78491af10, 0x3fe6c40d73c18275, // 0.70275, 0.71143 + 0x3fe66b0f3f52b386, 0x3fe6d5afef4aafcc, // 0.70057, 0.71358 + 0x3fe6591925f0783e, 0x3fe6e74454eaa8ae, // 0.69838, 0.71573 + 0x3fe64715437f535b, 0x3fe6f8ca99c95b75, // 0.69618, 0.71787 + 0x3fe63503a31c1be8, 0x3fe70a42b3176d7a, // 0.69397, 0.72 + 0x3fe622e44fec22ff, 0x3fe71bac960e41bf, // 0.69176, 0.72213 + 0x3fe610b7551d2cde, 0x3fe72d0837efff97, // 0.68954, 0.72425 + 0x3fe5fe7cbde56a0f, 0x3fe73e558e079942, // 0.68732, 0.72636 + 0x3fe5ec3495837074, 0x3fe74f948da8d28d, // 0.68508, 0.72846 + 0x3fe5d9dee73e345c, 0x3fe760c52c304764, // 0.68285, 0.73056 + 0x3fe5c77bbe65018c, 0x3fe771e75f037261, // 0.6806, 0.73265 + 0x3fe5b50b264f7448, 0x3fe782fb1b90b35b, // 0.67835, 0.73474 + 0x3fe5a28d2a5d7250, 0x3fe79400574f55e4, // 0.67609, 0.73682 + 0x3fe59001d5f723df, 0x3fe7a4f707bf97d2, // 0.67383, 0.73889 + 0x3fe57d69348cec9f, 0x3fe7b5df226aafb0, // 0.67156, 0.74095 + 0x3fe56ac35197649e, 0x3fe7c6b89ce2d333, // 0.66928, 0.74301 + 0x3fe5581038975137, 0x3fe7d7836cc33db2, // 0.667, 0.74506 + 0x3fe5454ff5159dfb, 0x3fe7e83f87b03686, // 0.66471, 0.7471 + 0x3fe5328292a35596, 0x3fe7f8ece3571771, // 0.66242, 0.74914 + 0x3fe51fa81cd99aa6, 0x3fe8098b756e52fa, // 0.66011, 0.75117 + 0x3fe50cc09f59a09b, 0x3fe81a1b33b57acc, // 0.65781, 0.75319 + 0x3fe4f9cc25cca486, 0x3fe82a9c13f545ff, // 0.65549, 0.7552 + 0x3fe4e6cabbe3e5e9, 0x3fe83b0e0bff976e, // 0.65317, 0.75721 + 0x3fe4d3bc6d589f80, 0x3fe84b7111af83f9, // 0.65085, 0.75921 + 0x3fe4c0a145ec0004, 0x3fe85bc51ae958cc, // 0.64851, 0.7612 + 0x3fe4ad79516722f0, 0x3fe86c0a1d9aa195, // 0.64618, 0.76319 + 0x3fe49a449b9b0938, 0x3fe87c400fba2ebf, // 0.64383, 0.76517 + 0x3fe48703306091fe, 0x3fe88c66e7481ba1, // 0.64148, 0.76714 + 0x3fe473b51b987347, 0x3fe89c7e9a4dd4ab, // 0.63912, 0.7691 + 0x3fe4605a692b32a2, 0x3fe8ac871ede1d88, // 0.63676, 0.77106 + 0x3fe44cf325091dd6, 0x3fe8bc806b151741, // 0.63439, 0.77301 + 0x3fe4397f5b2a4380, 0x3fe8cc6a75184655, // 0.63202, 0.77495 + 0x3fe425ff178e6bb1, 0x3fe8dc45331698cc, // 0.62964, 0.77689 + 0x3fe41272663d108c, 0x3fe8ec109b486c49, // 0.62725, 0.77882 + 0x3fe3fed9534556d4, 0x3fe8fbcca3ef940d, // 0.62486, 0.78074 + 0x3fe3eb33eabe0680, 0x3fe90b7943575efe, // 0.62246, 0.78265 + 0x3fe3d78238c58343, 0x3fe91b166fd49da2, // 0.62006, 0.78456 + 0x3fe3c3c44981c517, 0x3fe92aa41fc5a815, // 0.61765, 0.78646 + 0x3fe3affa292050b9, 0x3fe93a22499263fc, // 0.61523, 0.78835 + 0x3fe39c23e3d63029, 0x3fe94990e3ac4a6c, // 0.61281, 0.79023 + 0x3fe3884185dfeb22, 0x3fe958efe48e6dd7, // 0.61038, 0.79211 + 0x3fe374531b817f8d, 0x3fe9683f42bd7fe1, // 0.60795, 0.79398 + 0x3fe36058b10659f3, 0x3fe9777ef4c7d742, // 0.60551, 0.79584 + 0x3fe34c5252c14de1, 0x3fe986aef1457594, // 0.60307, 0.79769 + 0x3fe338400d0c8e57, 0x3fe995cf2ed80d22, // 0.60062, 0.79954 + 0x3fe32421ec49a620, 0x3fe9a4dfa42b06b2, // 0.59816, 0.80138 + 0x3fe30ff7fce17035, 0x3fe9b3e047f38741, // 0.5957, 0.80321 + 0x3fe2fbc24b441015, 0x3fe9c2d110f075c3, // 0.59323, 0.80503 + 0x3fe2e780e3e8ea16, 0x3fe9d1b1f5ea80d6, // 0.59076, 0.80685 + 0x3fe2d333d34e9bb7, 0x3fe9e082edb42472, // 0.58828, 0.80866 + 0x3fe2bedb25faf3ea, 0x3fe9ef43ef29af94, // 0.5858, 0.81046 + 0x3fe2aa76e87aeb58, 0x3fe9fdf4f13149de, // 0.58331, 0.81225 + 0x3fe2960727629ca8, 0x3fea0c95eabaf937, // 0.58081, 0.81404 + 0x3fe2818bef4d3cba, 0x3fea1b26d2c0a75e, // 0.57831, 0.81581 + 0x3fe26d054cdd12df, 0x3fea29a7a0462782, // 0.57581, 0.81758 + 0x3fe258734cbb7110, 0x3fea38184a593bc6, // 0.5733, 0.81935 + 0x3fe243d5fb98ac1f, 0x3fea4678c8119ac8, // 0.57078, 0.8211 + 0x3fe22f2d662c13e1, 0x3fea54c91090f524, // 0.56826, 0.82285 + 0x3fe21a799933eb58, 0x3fea63091b02fae2, // 0.56573, 0.82459 + 0x3fe205baa17560d6, 0x3fea7138de9d60f5, // 0.5632, 0.82632 + 0x3fe1f0f08bbc861b, 0x3fea7f58529fe69d, // 0.56066, 0.82805 + 0x3fe1dc1b64dc4872, 0x3fea8d676e545ad2, // 0.55812, 0.82976 + 0x3fe1c73b39ae68c8, 0x3fea9b66290ea1a3, // 0.55557, 0.83147 + 0x3fe1b250171373be, 0x3feaa9547a2cb98e, // 0.55302, 0.83317 + 0x3fe19d5a09f2b9b8, 0x3feab7325916c0d4, // 0.55046, 0.83486 + 0x3fe188591f3a46e5, 0x3feac4ffbd3efac8, // 0.54789, 0.83655 + 0x3fe1734d63dedb49, 0x3fead2bc9e21d511, // 0.54532, 0.83822 + 0x3fe15e36e4dbe2bc, 0x3feae068f345ecef, // 0.54275, 0.83989 + 0x3fe14915af336ceb, 0x3feaee04b43c1474, // 0.54017, 0.84155 + 0x3fe133e9cfee254e, 0x3feafb8fd89f57b6, // 0.53759, 0.84321 + 0x3fe11eb3541b4b22, 0x3feb090a58150200, // 0.535, 0.84485 + 0x3fe1097248d0a956, 0x3feb16742a4ca2f5, // 0.5324, 0.84649 + 0x3fe0f426bb2a8e7d, 0x3feb23cd470013b4, // 0.5298, 0.84812 + 0x3fe0ded0b84bc4b5, 0x3feb3115a5f37bf4, // 0.5272, 0.84974 + 0x3fe0c9704d5d898f, 0x3feb3e4d3ef55712, // 0.52459, 0.85136 + 0x3fe0b405878f85ec, 0x3feb4b7409de7925, // 0.52198, 0.85296 + 0x3fe09e907417c5e1, 0x3feb5889fe921405, // 0.51936, 0.85456 + 0x3fe089112032b08c, 0x3feb658f14fdbc47, // 0.51673, 0.85615 + 0x3fe073879922ffed, 0x3feb728345196e3e, // 0.5141, 0.85773 + 0x3fe05df3ec31b8b6, 0x3feb7f6686e792ea, // 0.51147, 0.8593 + 0x3fe0485626ae221a, 0x3feb8c38d27504e9, // 0.50883, 0.86087 + 0x3fe032ae55edbd95, 0x3feb98fa1fd9155e, // 0.50619, 0.86242 + 0x3fe01cfc874c3eb7, 0x3feba5aa673590d2, // 0.50354, 0.86397 + 0x3fe00740c82b82e0, 0x3febb249a0b6c40d, // 0.50089, 0.86551 + 0x3fdfe2f64be7120f, 0x3febbed7c49380ea, // 0.49823, 0.86705 + 0x3fdfb7575c24d2de, 0x3febcb54cb0d2327, // 0.49557, 0.86857 + 0x3fdf8ba4dbf89aba, 0x3febd7c0ac6f952a, // 0.4929, 0.87009 + 0x3fdf5fdee656cda3, 0x3febe41b611154c1, // 0.49023, 0.8716 + 0x3fdf3405963fd068, 0x3febf064e15377dd, // 0.48755, 0.87309 + 0x3fdf081906bff7fd, 0x3febfc9d25a1b147, // 0.48487, 0.87459 + 0x3fdedc1952ef78d5, 0x3fec08c426725549, // 0.48218, 0.87607 + 0x3fdeb00695f25620, 0x3fec14d9dc465e58, // 0.47949, 0.87755 + 0x3fde83e0eaf85113, 0x3fec20de3fa971b0, // 0.4768, 0.87901 + 0x3fde57a86d3cd824, 0x3fec2cd14931e3f1, // 0.4741, 0.88047 + 0x3fde2b5d3806f63b, 0x3fec38b2f180bdb1, // 0.4714, 0.88192 + 0x3fddfeff66a941de, 0x3fec44833141c004, // 0.46869, 0.88336 + 0x3fddd28f1481cc58, 0x3fec5042012b6907, // 0.46598, 0.8848 + 0x3fdda60c5cfa10d8, 0x3fec5bef59fef85a, // 0.46326, 0.88622 + 0x3fdd79775b86e389, 0x3fec678b3488739b, // 0.46054, 0.88764 + 0x3fdd4cd02ba8609c, 0x3fec7315899eaad7, // 0.45781, 0.88905 + 0x3fdd2016e8e9db5b, 0x3fec7e8e52233cf3, // 0.45508, 0.89045 + 0x3fdcf34baee1cd21, 0x3fec89f587029c13, // 0.45235, 0.89184 + 0x3fdcc66e9931c45d, 0x3fec954b213411f5, // 0.44961, 0.89322 + 0x3fdc997fc3865388, 0x3feca08f19b9c449, // 0.44687, 0.8946 + 0x3fdc6c7f4997000a, 0x3fecabc169a0b901, // 0.44412, 0.89597 + 0x3fdc3f6d47263129, 0x3fecb6e20a00da99, // 0.44137, 0.89732 + 0x3fdc1249d8011ee7, 0x3fecc1f0f3fcfc5c, // 0.43862, 0.89867 + 0x3fdbe51517ffc0d9, 0x3fecccee20c2de9f, // 0.43586, 0.90002 + 0x3fdbb7cf2304bd01, 0x3fecd7d9898b32f6, // 0.43309, 0.90135 + 0x3fdb8a7814fd5693, 0x3fece2b32799a060, // 0.43033, 0.90267 + 0x3fdb5d1009e15cc0, 0x3feced7af43cc773, // 0.42756, 0.90399 + 0x3fdb2f971db31972, 0x3fecf830e8ce467b, // 0.42478, 0.9053 + 0x3fdb020d6c7f4009, 0x3fed02d4feb2bd92, // 0.422, 0.9066 + 0x3fdad473125cdc08, 0x3fed0d672f59d2b9, // 0.41922, 0.90789 + 0x3fdaa6c82b6d3fc9, 0x3fed17e7743e35dc, // 0.41643, 0.90917 + 0x3fda790cd3dbf31a, 0x3fed2255c6e5a4e1, // 0.41364, 0.91044 + 0x3fda4b4127dea1e4, 0x3fed2cb220e0ef9f, // 0.41084, 0.91171 + 0x3fda1d6543b50ac0, 0x3fed36fc7bcbfbdc, // 0.40804, 0.91296 + 0x3fd9ef7943a8ed8a, 0x3fed4134d14dc93a, // 0.40524, 0.91421 + 0x3fd9c17d440df9f2, 0x3fed4b5b1b187524, // 0.40243, 0.91545 + 0x3fd993716141bdfe, 0x3fed556f52e93eb1, // 0.39962, 0.91668 + 0x3fd96555b7ab948f, 0x3fed5f7172888a7f, // 0.39681, 0.9179 + 0x3fd9372a63bc93d7, 0x3fed696173c9e68b, // 0.39399, 0.91911 + 0x3fd908ef81ef7bd1, 0x3fed733f508c0dff, // 0.39117, 0.92032 + 0x3fd8daa52ec8a4af, 0x3fed7d0b02b8ecf9, // 0.38835, 0.92151 + 0x3fd8ac4b86d5ed44, 0x3fed86c48445a450, // 0.38552, 0.9227 + 0x3fd87de2a6aea963, 0x3fed906bcf328d46, // 0.38268, 0.92388 + 0x3fd84f6aaaf3903f, 0x3fed9a00dd8b3d46, // 0.37985, 0.92505 + 0x3fd820e3b04eaac4, 0x3feda383a9668988, // 0.37701, 0.92621 + 0x3fd7f24dd37341e3, 0x3fedacf42ce68ab9, // 0.37416, 0.92736 + 0x3fd7c3a9311dcce7, 0x3fedb6526238a09b, // 0.37132, 0.92851 + 0x3fd794f5e613dfae, 0x3fedbf9e4395759a, // 0.36847, 0.92964 + 0x3fd766340f2418f6, 0x3fedc8d7cb410260, // 0.36561, 0.93077 + 0x3fd73763c9261092, 0x3fedd1fef38a915a, // 0.36276, 0.93188 + 0x3fd7088530fa459e, 0x3feddb13b6ccc23d, // 0.3599, 0.93299 + 0x3fd6d998638a0cb5, 0x3fede4160f6d8d81, // 0.35703, 0.93409 + 0x3fd6aa9d7dc77e16, 0x3feded05f7de47da, // 0.35416, 0.93518 + 0x3fd67b949cad63ca, 0x3fedf5e36a9ba59c, // 0.35129, 0.93627 + 0x3fd64c7ddd3f27c6, 0x3fedfeae622dbe2b, // 0.34842, 0.93734 + 0x3fd61d595c88c203, 0x3fee0766d9280f54, // 0.34554, 0.9384 + 0x3fd5ee27379ea693, 0x3fee100cca2980ac, // 0.34266, 0.93946 + 0x3fd5bee78b9db3b6, 0x3fee18a02fdc66d9, // 0.33978, 0.94051 + 0x3fd58f9a75ab1fdd, 0x3fee212104f686e5, // 0.33689, 0.94154 + 0x3fd5604012f467b4, 0x3fee298f4439197a, // 0.334, 0.94257 + 0x3fd530d880af3c24, 0x3fee31eae870ce25, // 0.33111, 0.94359 + 0x3fd50163dc197047, 0x3fee3a33ec75ce85, // 0.32821, 0.9446 + 0x3fd4d1e24278e76a, 0x3fee426a4b2bc17e, // 0.32531, 0.94561 + 0x3fd4a253d11b82f3, 0x3fee4a8dff81ce5e, // 0.32241, 0.9466 + 0x3fd472b8a5571054, 0x3fee529f04729ffc, // 0.3195, 0.94759 + 0x3fd44310dc8936f0, 0x3fee5a9d550467d3, // 0.31659, 0.94856 + 0x3fd4135c94176602, 0x3fee6288ec48e112, // 0.31368, 0.94953 + 0x3fd3e39be96ec271, 0x3fee6a61c55d53a7, // 0.31077, 0.95049 + 0x3fd3b3cefa0414b7, 0x3fee7227db6a9744, // 0.30785, 0.95144 + 0x3fd383f5e353b6aa, 0x3fee79db29a5165a, // 0.30493, 0.95238 + 0x3fd35410c2e18152, 0x3fee817bab4cd10d, // 0.30201, 0.95331 + 0x3fd3241fb638baaf, 0x3fee89095bad6025, // 0.29908, 0.95423 + 0x3fd2f422daec0386, 0x3fee9084361df7f3, // 0.29615, 0.95514 + 0x3fd2c41a4e954520, 0x3fee97ec36016b30, // 0.29322, 0.95605 + 0x3fd294062ed59f05, 0x3fee9f4156c62dda, // 0.29028, 0.95694 + 0x3fd263e6995554ba, 0x3feea68393e65800, // 0.28735, 0.95783 + 0x3fd233bbabc3bb72, 0x3feeadb2e8e7a88e, // 0.28441, 0.9587 + 0x3fd2038583d727bd, 0x3feeb4cf515b8811, // 0.28146, 0.95957 + 0x3fd1d3443f4cdb3d, 0x3feebbd8c8df0b74, // 0.27852, 0.96043 + 0x3fd1a2f7fbe8f243, 0x3feec2cf4b1af6b2, // 0.27557, 0.96128 + 0x3fd172a0d7765177, 0x3feec9b2d3c3bf84, // 0.27262, 0.96212 + 0x3fd1423eefc69378, 0x3feed0835e999009, // 0.26967, 0.96295 + 0x3fd111d262b1f677, 0x3feed740e7684963, // 0.26671, 0.96378 + 0x3fd0e15b4e1749cd, 0x3feeddeb6a078651, // 0.26375, 0.96459 + 0x3fd0b0d9cfdbdb90, 0x3feee482e25a9dbc, // 0.26079, 0.96539 + 0x3fd0804e05eb661e, 0x3feeeb074c50a544, // 0.25783, 0.96619 + 0x3fd04fb80e37fdae, 0x3feef178a3e473c2, // 0.25487, 0.96698 + 0x3fd01f1806b9fdd2, 0x3feef7d6e51ca3c0, // 0.2519, 0.96775 + 0x3fcfdcdc1adfedf8, 0x3feefe220c0b95ec, // 0.24893, 0.96852 + 0x3fcf7b7480bd3801, 0x3fef045a14cf738c, // 0.24596, 0.96928 + 0x3fcf19f97b215f1a, 0x3fef0a7efb9230d7, // 0.24298, 0.97003 + 0x3fceb86b462de348, 0x3fef1090bc898f5f, // 0.24, 0.97077 + 0x3fce56ca1e101a1b, 0x3fef168f53f7205d, // 0.23702, 0.9715 + 0x3fcdf5163f01099a, 0x3fef1c7abe284708, // 0.23404, 0.97223 + 0x3fcd934fe5454311, 0x3fef2252f7763ada, // 0.23106, 0.97294 + 0x3fcd31774d2cbdee, 0x3fef2817fc4609ce, // 0.22807, 0.97364 + 0x3fcccf8cb312b286, 0x3fef2dc9c9089a9d, // 0.22508, 0.97434 + 0x3fcc6d90535d74dc, 0x3fef33685a3aaef0, // 0.22209, 0.97503 + 0x3fcc0b826a7e4f63, 0x3fef38f3ac64e589, // 0.2191, 0.9757 + 0x3fcba96334f15dad, 0x3fef3e6bbc1bbc65, // 0.21611, 0.97637 + 0x3fcb4732ef3d6722, 0x3fef43d085ff92dd, // 0.21311, 0.97703 + 0x3fcae4f1d5f3b9ab, 0x3fef492206bcabb4, // 0.21011, 0.97768 + 0x3fca82a025b00451, 0x3fef4e603b0b2f2d, // 0.20711, 0.97832 + 0x3fca203e1b1831da, 0x3fef538b1faf2d07, // 0.20411, 0.97895 + 0x3fc9bdcbf2dc4366, 0x3fef58a2b1789e84, // 0.2011, 0.97957 + 0x3fc95b49e9b62af9, 0x3fef5da6ed43685d, // 0.1981, 0.98018 + 0x3fc8f8b83c69a60a, 0x3fef6297cff75cb0, // 0.19509, 0.98079 + 0x3fc8961727c41804, 0x3fef677556883cee, // 0.19208, 0.98138 + 0x3fc83366e89c64c5, 0x3fef6c3f7df5bbb7, // 0.18907, 0.98196 + 0x3fc7d0a7bbd2cb1b, 0x3fef70f6434b7eb7, // 0.18606, 0.98254 + 0x3fc76dd9de50bf31, 0x3fef7599a3a12077, // 0.18304, 0.98311 + 0x3fc70afd8d08c4ff, 0x3fef7a299c1a322a, // 0.18002, 0.98366 + 0x3fc6a81304f64ab2, 0x3fef7ea629e63d6e, // 0.177, 0.98421 + 0x3fc6451a831d830d, 0x3fef830f4a40c60c, // 0.17398, 0.98475 + 0x3fc5e214448b3fc6, 0x3fef8764fa714ba9, // 0.17096, 0.98528 + 0x3fc57f008654cbde, 0x3fef8ba737cb4b78, // 0.16794, 0.9858 + 0x3fc51bdf8597c5f2, 0x3fef8fd5ffae41db, // 0.16491, 0.98631 + 0x3fc4b8b17f79fa88, 0x3fef93f14f85ac08, // 0.16189, 0.98681 + 0x3fc45576b1293e5a, 0x3fef97f924c9099b, // 0.15886, 0.9873 + 0x3fc3f22f57db4893, 0x3fef9bed7cfbde29, // 0.15583, 0.98778 + 0x3fc38edbb0cd8d14, 0x3fef9fce55adb2c8, // 0.1528, 0.98826 + 0x3fc32b7bf94516a7, 0x3fefa39bac7a1791, // 0.14976, 0.98872 + 0x3fc2c8106e8e613a, 0x3fefa7557f08a517, // 0.14673, 0.98918 + 0x3fc264994dfd340a, 0x3fefaafbcb0cfddc, // 0.1437, 0.98962 + 0x3fc20116d4ec7bce, 0x3fefae8e8e46cfbb, // 0.14066, 0.99006 + 0x3fc19d8940be24e7, 0x3fefb20dc681d54d, // 0.13762, 0.99049 + 0x3fc139f0cedaf576, 0x3fefb5797195d741, // 0.13458, 0.9909 + 0x3fc0d64dbcb26786, 0x3fefb8d18d66adb7, // 0.13154, 0.99131 + 0x3fc072a047ba831d, 0x3fefbc1617e44186, // 0.1285, 0.99171 + 0x3fc00ee8ad6fb85b, 0x3fefbf470f0a8d88, // 0.12545, 0.9921 + 0x3fbf564e56a9730e, 0x3fefc26470e19fd3, // 0.12241, 0.99248 + 0x3fbe8eb7fde4aa3e, 0x3fefc56e3b7d9af6, // 0.11937, 0.99285 + 0x3fbdc70ecbae9fc8, 0x3fefc8646cfeb721, // 0.11632, 0.99321 + 0x3fbcff533b307dc1, 0x3fefcb4703914354, // 0.11327, 0.99356 + 0x3fbc3785c79ec2d5, 0x3fefce15fd6da67b, // 0.11022, 0.99391 + 0x3fbb6fa6ec38f64c, 0x3fefd0d158d86087, // 0.10717, 0.99424 + 0x3fbaa7b724495c04, 0x3fefd37914220b84, // 0.10412, 0.99456 + 0x3fb9dfb6eb24a85c, 0x3fefd60d2da75c9e, // 0.10107, 0.99488 + 0x3fb917a6bc29b42c, 0x3fefd88da3d12526, // 0.098017, 0.99518 + 0x3fb84f8712c130a0, 0x3fefdafa7514538c, // 0.094963, 0.99548 + 0x3fb787586a5d5b21, 0x3fefdd539ff1f456, // 0.091909, 0.99577 + 0x3fb6bf1b3e79b129, 0x3fefdf9922f73307, // 0.088854, 0.99604 + 0x3fb5f6d00a9aa419, 0x3fefe1cafcbd5b09, // 0.085797, 0.99631 + 0x3fb52e774a4d4d0a, 0x3fefe3e92be9d886, // 0.08274, 0.99657 + 0x3fb4661179272096, 0x3fefe5f3af2e3940, // 0.079682, 0.99682 + 0x3fb39d9f12c5a299, 0x3fefe7ea85482d60, // 0.076624, 0.99706 + 0x3fb2d52092ce19f6, 0x3fefe9cdad01883a, // 0.073565, 0.99729 + 0x3fb20c9674ed444c, 0x3fefeb9d2530410f, // 0.070505, 0.99751 + 0x3fb1440134d709b2, 0x3fefed58ecb673c4, // 0.067444, 0.99772 + 0x3fb07b614e463064, 0x3fefef0102826191, // 0.064383, 0.99793 + 0x3faf656e79f820e0, 0x3feff095658e71ad, // 0.061321, 0.99812 + 0x3fadd406f9808ec8, 0x3feff21614e131ed, // 0.058258, 0.9983 + 0x3fac428d12c0d7e3, 0x3feff3830f8d575c, // 0.055195, 0.99848 + 0x3faab101bd5f8317, 0x3feff4dc54b1bed3, // 0.052132, 0.99864 + 0x3fa91f65f10dd814, 0x3feff621e3796d7e, // 0.049068, 0.9988 + 0x3fa78dbaa5874685, 0x3feff753bb1b9164, // 0.046003, 0.99894 + 0x3fa5fc00d290cd43, 0x3feff871dadb81df, // 0.042938, 0.99908 + 0x3fa46a396ff86179, 0x3feff97c4208c014, // 0.039873, 0.9992 + 0x3fa2d865759455cd, 0x3feffa72effef75d, // 0.036807, 0.99932 + 0x3fa14685db42c17e, 0x3feffb55e425fdae, // 0.033741, 0.99943 + 0x3f9f693731d1cf01, 0x3feffc251df1d3f8, // 0.030675, 0.99953 + 0x3f9c454f4ce53b1c, 0x3feffce09ce2a679, // 0.027608, 0.99962 + 0x3f992155f7a3667e, 0x3feffd886084cd0d, // 0.024541, 0.9997 + 0x3f95fd4d21fab226, 0x3feffe1c6870cb77, // 0.021474, 0.99977 + 0x3f92d936bbe30efd, 0x3feffe9cb44b51a1, // 0.018407, 0.99983 + 0x3f8f6a296ab997ca, 0x3fefff0943c53bd1, // 0.015339, 0.99988 + 0x3f8921d1fcdec784, 0x3fefff62169b92db, // 0.012272, 0.99992 + 0x3f82d96b0e509703, 0x3fefffa72c978c4f, // 0.0092038, 0.99996 + 0x3f7921f0fe670071, 0x3fefffd8858e8a92, // 0.0061359, 0.99998 + 0x3f6921f8becca4ba, 0x3feffff621621d02, // 0.003068, 1 + 0x0000000000000000, 0x3ff0000000000000, // 0, 1 + 0xbf6921f8becca4ba, 0x3feffff621621d02, // -0.003068, 1 + 0xbf7921f0fe670071, 0x3fefffd8858e8a92, //-0.0061359, 0.99998 + 0xbf82d96b0e509703, 0x3fefffa72c978c4f, //-0.0092038, 0.99996 + 0xbf8921d1fcdec784, 0x3fefff62169b92db, // -0.012272, 0.99992 + 0xbf8f6a296ab997ca, 0x3fefff0943c53bd1, // -0.015339, 0.99988 + 0xbf92d936bbe30efd, 0x3feffe9cb44b51a1, // -0.018407, 0.99983 + 0xbf95fd4d21fab226, 0x3feffe1c6870cb77, // -0.021474, 0.99977 + 0xbf992155f7a3667e, 0x3feffd886084cd0d, // -0.024541, 0.9997 + 0xbf9c454f4ce53b1c, 0x3feffce09ce2a679, // -0.027608, 0.99962 + 0xbf9f693731d1cf01, 0x3feffc251df1d3f8, // -0.030675, 0.99953 + 0xbfa14685db42c17e, 0x3feffb55e425fdae, // -0.033741, 0.99943 + 0xbfa2d865759455cd, 0x3feffa72effef75d, // -0.036807, 0.99932 + 0xbfa46a396ff86179, 0x3feff97c4208c014, // -0.039873, 0.9992 + 0xbfa5fc00d290cd43, 0x3feff871dadb81df, // -0.042938, 0.99908 + 0xbfa78dbaa5874685, 0x3feff753bb1b9164, // -0.046003, 0.99894 + 0xbfa91f65f10dd814, 0x3feff621e3796d7e, // -0.049068, 0.9988 + 0xbfaab101bd5f8317, 0x3feff4dc54b1bed3, // -0.052132, 0.99864 + 0xbfac428d12c0d7e3, 0x3feff3830f8d575c, // -0.055195, 0.99848 + 0xbfadd406f9808ec8, 0x3feff21614e131ed, // -0.058258, 0.9983 + 0xbfaf656e79f820e0, 0x3feff095658e71ad, // -0.061321, 0.99812 + 0xbfb07b614e463064, 0x3fefef0102826191, // -0.064383, 0.99793 + 0xbfb1440134d709b2, 0x3fefed58ecb673c4, // -0.067444, 0.99772 + 0xbfb20c9674ed444c, 0x3fefeb9d2530410f, // -0.070505, 0.99751 + 0xbfb2d52092ce19f6, 0x3fefe9cdad01883a, // -0.073565, 0.99729 + 0xbfb39d9f12c5a299, 0x3fefe7ea85482d60, // -0.076624, 0.99706 + 0xbfb4661179272096, 0x3fefe5f3af2e3940, // -0.079682, 0.99682 + 0xbfb52e774a4d4d0a, 0x3fefe3e92be9d886, // -0.08274, 0.99657 + 0xbfb5f6d00a9aa419, 0x3fefe1cafcbd5b09, // -0.085797, 0.99631 + 0xbfb6bf1b3e79b129, 0x3fefdf9922f73307, // -0.088854, 0.99604 + 0xbfb787586a5d5b21, 0x3fefdd539ff1f456, // -0.091909, 0.99577 + 0xbfb84f8712c130a0, 0x3fefdafa7514538c, // -0.094963, 0.99548 + 0xbfb917a6bc29b42c, 0x3fefd88da3d12526, // -0.098017, 0.99518 + 0xbfb9dfb6eb24a85c, 0x3fefd60d2da75c9e, // -0.10107, 0.99488 + 0xbfbaa7b724495c04, 0x3fefd37914220b84, // -0.10412, 0.99456 + 0xbfbb6fa6ec38f64c, 0x3fefd0d158d86087, // -0.10717, 0.99424 + 0xbfbc3785c79ec2d5, 0x3fefce15fd6da67b, // -0.11022, 0.99391 + 0xbfbcff533b307dc1, 0x3fefcb4703914354, // -0.11327, 0.99356 + 0xbfbdc70ecbae9fc8, 0x3fefc8646cfeb721, // -0.11632, 0.99321 + 0xbfbe8eb7fde4aa3e, 0x3fefc56e3b7d9af6, // -0.11937, 0.99285 + 0xbfbf564e56a9730e, 0x3fefc26470e19fd3, // -0.12241, 0.99248 + 0xbfc00ee8ad6fb85b, 0x3fefbf470f0a8d88, // -0.12545, 0.9921 + 0xbfc072a047ba831d, 0x3fefbc1617e44186, // -0.1285, 0.99171 + 0xbfc0d64dbcb26786, 0x3fefb8d18d66adb7, // -0.13154, 0.99131 + 0xbfc139f0cedaf576, 0x3fefb5797195d741, // -0.13458, 0.9909 + 0xbfc19d8940be24e7, 0x3fefb20dc681d54d, // -0.13762, 0.99049 + 0xbfc20116d4ec7bce, 0x3fefae8e8e46cfbb, // -0.14066, 0.99006 + 0xbfc264994dfd340a, 0x3fefaafbcb0cfddc, // -0.1437, 0.98962 + 0xbfc2c8106e8e613a, 0x3fefa7557f08a517, // -0.14673, 0.98918 + 0xbfc32b7bf94516a7, 0x3fefa39bac7a1791, // -0.14976, 0.98872 + 0xbfc38edbb0cd8d14, 0x3fef9fce55adb2c8, // -0.1528, 0.98826 + 0xbfc3f22f57db4893, 0x3fef9bed7cfbde29, // -0.15583, 0.98778 + 0xbfc45576b1293e5a, 0x3fef97f924c9099b, // -0.15886, 0.9873 + 0xbfc4b8b17f79fa88, 0x3fef93f14f85ac08, // -0.16189, 0.98681 + 0xbfc51bdf8597c5f2, 0x3fef8fd5ffae41db, // -0.16491, 0.98631 + 0xbfc57f008654cbde, 0x3fef8ba737cb4b78, // -0.16794, 0.9858 + 0xbfc5e214448b3fc6, 0x3fef8764fa714ba9, // -0.17096, 0.98528 + 0xbfc6451a831d830d, 0x3fef830f4a40c60c, // -0.17398, 0.98475 + 0xbfc6a81304f64ab2, 0x3fef7ea629e63d6e, // -0.177, 0.98421 + 0xbfc70afd8d08c4ff, 0x3fef7a299c1a322a, // -0.18002, 0.98366 + 0xbfc76dd9de50bf31, 0x3fef7599a3a12077, // -0.18304, 0.98311 + 0xbfc7d0a7bbd2cb1b, 0x3fef70f6434b7eb7, // -0.18606, 0.98254 + 0xbfc83366e89c64c5, 0x3fef6c3f7df5bbb7, // -0.18907, 0.98196 + 0xbfc8961727c41804, 0x3fef677556883cee, // -0.19208, 0.98138 + 0xbfc8f8b83c69a60a, 0x3fef6297cff75cb0, // -0.19509, 0.98079 + 0xbfc95b49e9b62af9, 0x3fef5da6ed43685d, // -0.1981, 0.98018 + 0xbfc9bdcbf2dc4366, 0x3fef58a2b1789e84, // -0.2011, 0.97957 + 0xbfca203e1b1831da, 0x3fef538b1faf2d07, // -0.20411, 0.97895 + 0xbfca82a025b00451, 0x3fef4e603b0b2f2d, // -0.20711, 0.97832 + 0xbfcae4f1d5f3b9ab, 0x3fef492206bcabb4, // -0.21011, 0.97768 + 0xbfcb4732ef3d6722, 0x3fef43d085ff92dd, // -0.21311, 0.97703 + 0xbfcba96334f15dad, 0x3fef3e6bbc1bbc65, // -0.21611, 0.97637 + 0xbfcc0b826a7e4f63, 0x3fef38f3ac64e589, // -0.2191, 0.9757 + 0xbfcc6d90535d74dc, 0x3fef33685a3aaef0, // -0.22209, 0.97503 + 0xbfcccf8cb312b286, 0x3fef2dc9c9089a9d, // -0.22508, 0.97434 + 0xbfcd31774d2cbdee, 0x3fef2817fc4609ce, // -0.22807, 0.97364 + 0xbfcd934fe5454311, 0x3fef2252f7763ada, // -0.23106, 0.97294 + 0xbfcdf5163f01099a, 0x3fef1c7abe284708, // -0.23404, 0.97223 + 0xbfce56ca1e101a1b, 0x3fef168f53f7205d, // -0.23702, 0.9715 + 0xbfceb86b462de348, 0x3fef1090bc898f5f, // -0.24, 0.97077 + 0xbfcf19f97b215f1a, 0x3fef0a7efb9230d7, // -0.24298, 0.97003 + 0xbfcf7b7480bd3801, 0x3fef045a14cf738c, // -0.24596, 0.96928 + 0xbfcfdcdc1adfedf8, 0x3feefe220c0b95ec, // -0.24893, 0.96852 + 0xbfd01f1806b9fdd2, 0x3feef7d6e51ca3c0, // -0.2519, 0.96775 + 0xbfd04fb80e37fdae, 0x3feef178a3e473c2, // -0.25487, 0.96698 + 0xbfd0804e05eb661e, 0x3feeeb074c50a544, // -0.25783, 0.96619 + 0xbfd0b0d9cfdbdb90, 0x3feee482e25a9dbc, // -0.26079, 0.96539 + 0xbfd0e15b4e1749cd, 0x3feeddeb6a078651, // -0.26375, 0.96459 + 0xbfd111d262b1f677, 0x3feed740e7684963, // -0.26671, 0.96378 + 0xbfd1423eefc69378, 0x3feed0835e999009, // -0.26967, 0.96295 + 0xbfd172a0d7765177, 0x3feec9b2d3c3bf84, // -0.27262, 0.96212 + 0xbfd1a2f7fbe8f243, 0x3feec2cf4b1af6b2, // -0.27557, 0.96128 + 0xbfd1d3443f4cdb3d, 0x3feebbd8c8df0b74, // -0.27852, 0.96043 + 0xbfd2038583d727bd, 0x3feeb4cf515b8811, // -0.28146, 0.95957 + 0xbfd233bbabc3bb72, 0x3feeadb2e8e7a88e, // -0.28441, 0.9587 + 0xbfd263e6995554ba, 0x3feea68393e65800, // -0.28735, 0.95783 + 0xbfd294062ed59f05, 0x3fee9f4156c62dda, // -0.29028, 0.95694 + 0xbfd2c41a4e954520, 0x3fee97ec36016b30, // -0.29322, 0.95605 + 0xbfd2f422daec0386, 0x3fee9084361df7f3, // -0.29615, 0.95514 + 0xbfd3241fb638baaf, 0x3fee89095bad6025, // -0.29908, 0.95423 + 0xbfd35410c2e18152, 0x3fee817bab4cd10d, // -0.30201, 0.95331 + 0xbfd383f5e353b6aa, 0x3fee79db29a5165a, // -0.30493, 0.95238 + 0xbfd3b3cefa0414b7, 0x3fee7227db6a9744, // -0.30785, 0.95144 + 0xbfd3e39be96ec271, 0x3fee6a61c55d53a7, // -0.31077, 0.95049 + 0xbfd4135c94176602, 0x3fee6288ec48e112, // -0.31368, 0.94953 + 0xbfd44310dc8936f0, 0x3fee5a9d550467d3, // -0.31659, 0.94856 + 0xbfd472b8a5571054, 0x3fee529f04729ffc, // -0.3195, 0.94759 + 0xbfd4a253d11b82f3, 0x3fee4a8dff81ce5e, // -0.32241, 0.9466 + 0xbfd4d1e24278e76a, 0x3fee426a4b2bc17e, // -0.32531, 0.94561 + 0xbfd50163dc197047, 0x3fee3a33ec75ce85, // -0.32821, 0.9446 + 0xbfd530d880af3c24, 0x3fee31eae870ce25, // -0.33111, 0.94359 + 0xbfd5604012f467b4, 0x3fee298f4439197a, // -0.334, 0.94257 + 0xbfd58f9a75ab1fdd, 0x3fee212104f686e5, // -0.33689, 0.94154 + 0xbfd5bee78b9db3b6, 0x3fee18a02fdc66d9, // -0.33978, 0.94051 + 0xbfd5ee27379ea693, 0x3fee100cca2980ac, // -0.34266, 0.93946 + 0xbfd61d595c88c203, 0x3fee0766d9280f54, // -0.34554, 0.9384 + 0xbfd64c7ddd3f27c6, 0x3fedfeae622dbe2b, // -0.34842, 0.93734 + 0xbfd67b949cad63ca, 0x3fedf5e36a9ba59c, // -0.35129, 0.93627 + 0xbfd6aa9d7dc77e16, 0x3feded05f7de47da, // -0.35416, 0.93518 + 0xbfd6d998638a0cb5, 0x3fede4160f6d8d81, // -0.35703, 0.93409 + 0xbfd7088530fa459e, 0x3feddb13b6ccc23d, // -0.3599, 0.93299 + 0xbfd73763c9261092, 0x3fedd1fef38a915a, // -0.36276, 0.93188 + 0xbfd766340f2418f6, 0x3fedc8d7cb410260, // -0.36561, 0.93077 + 0xbfd794f5e613dfae, 0x3fedbf9e4395759a, // -0.36847, 0.92964 + 0xbfd7c3a9311dcce7, 0x3fedb6526238a09b, // -0.37132, 0.92851 + 0xbfd7f24dd37341e3, 0x3fedacf42ce68ab9, // -0.37416, 0.92736 + 0xbfd820e3b04eaac4, 0x3feda383a9668988, // -0.37701, 0.92621 + 0xbfd84f6aaaf3903f, 0x3fed9a00dd8b3d46, // -0.37985, 0.92505 + 0xbfd87de2a6aea963, 0x3fed906bcf328d46, // -0.38268, 0.92388 + 0xbfd8ac4b86d5ed44, 0x3fed86c48445a450, // -0.38552, 0.9227 + 0xbfd8daa52ec8a4af, 0x3fed7d0b02b8ecf9, // -0.38835, 0.92151 + 0xbfd908ef81ef7bd1, 0x3fed733f508c0dff, // -0.39117, 0.92032 + 0xbfd9372a63bc93d7, 0x3fed696173c9e68b, // -0.39399, 0.91911 + 0xbfd96555b7ab948f, 0x3fed5f7172888a7f, // -0.39681, 0.9179 + 0xbfd993716141bdfe, 0x3fed556f52e93eb1, // -0.39962, 0.91668 + 0xbfd9c17d440df9f2, 0x3fed4b5b1b187524, // -0.40243, 0.91545 + 0xbfd9ef7943a8ed8a, 0x3fed4134d14dc93a, // -0.40524, 0.91421 + 0xbfda1d6543b50ac0, 0x3fed36fc7bcbfbdc, // -0.40804, 0.91296 + 0xbfda4b4127dea1e4, 0x3fed2cb220e0ef9f, // -0.41084, 0.91171 + 0xbfda790cd3dbf31a, 0x3fed2255c6e5a4e1, // -0.41364, 0.91044 + 0xbfdaa6c82b6d3fc9, 0x3fed17e7743e35dc, // -0.41643, 0.90917 + 0xbfdad473125cdc08, 0x3fed0d672f59d2b9, // -0.41922, 0.90789 + 0xbfdb020d6c7f4009, 0x3fed02d4feb2bd92, // -0.422, 0.9066 + 0xbfdb2f971db31972, 0x3fecf830e8ce467b, // -0.42478, 0.9053 + 0xbfdb5d1009e15cc0, 0x3feced7af43cc773, // -0.42756, 0.90399 + 0xbfdb8a7814fd5693, 0x3fece2b32799a060, // -0.43033, 0.90267 + 0xbfdbb7cf2304bd01, 0x3fecd7d9898b32f6, // -0.43309, 0.90135 + 0xbfdbe51517ffc0d9, 0x3fecccee20c2de9f, // -0.43586, 0.90002 + 0xbfdc1249d8011ee7, 0x3fecc1f0f3fcfc5c, // -0.43862, 0.89867 + 0xbfdc3f6d47263129, 0x3fecb6e20a00da99, // -0.44137, 0.89732 + 0xbfdc6c7f4997000a, 0x3fecabc169a0b901, // -0.44412, 0.89597 + 0xbfdc997fc3865388, 0x3feca08f19b9c449, // -0.44687, 0.8946 + 0xbfdcc66e9931c45d, 0x3fec954b213411f5, // -0.44961, 0.89322 + 0xbfdcf34baee1cd21, 0x3fec89f587029c13, // -0.45235, 0.89184 + 0xbfdd2016e8e9db5b, 0x3fec7e8e52233cf3, // -0.45508, 0.89045 + 0xbfdd4cd02ba8609c, 0x3fec7315899eaad7, // -0.45781, 0.88905 + 0xbfdd79775b86e389, 0x3fec678b3488739b, // -0.46054, 0.88764 + 0xbfdda60c5cfa10d8, 0x3fec5bef59fef85a, // -0.46326, 0.88622 + 0xbfddd28f1481cc58, 0x3fec5042012b6907, // -0.46598, 0.8848 + 0xbfddfeff66a941de, 0x3fec44833141c004, // -0.46869, 0.88336 + 0xbfde2b5d3806f63b, 0x3fec38b2f180bdb1, // -0.4714, 0.88192 + 0xbfde57a86d3cd824, 0x3fec2cd14931e3f1, // -0.4741, 0.88047 + 0xbfde83e0eaf85113, 0x3fec20de3fa971b0, // -0.4768, 0.87901 + 0xbfdeb00695f25620, 0x3fec14d9dc465e58, // -0.47949, 0.87755 + 0xbfdedc1952ef78d5, 0x3fec08c426725549, // -0.48218, 0.87607 + 0xbfdf081906bff7fd, 0x3febfc9d25a1b147, // -0.48487, 0.87459 + 0xbfdf3405963fd068, 0x3febf064e15377dd, // -0.48755, 0.87309 + 0xbfdf5fdee656cda3, 0x3febe41b611154c1, // -0.49023, 0.8716 + 0xbfdf8ba4dbf89aba, 0x3febd7c0ac6f952a, // -0.4929, 0.87009 + 0xbfdfb7575c24d2de, 0x3febcb54cb0d2327, // -0.49557, 0.86857 + 0xbfdfe2f64be7120f, 0x3febbed7c49380ea, // -0.49823, 0.86705 + 0xbfe00740c82b82e0, 0x3febb249a0b6c40d, // -0.50089, 0.86551 + 0xbfe01cfc874c3eb7, 0x3feba5aa673590d2, // -0.50354, 0.86397 + 0xbfe032ae55edbd95, 0x3feb98fa1fd9155e, // -0.50619, 0.86242 + 0xbfe0485626ae221a, 0x3feb8c38d27504e9, // -0.50883, 0.86087 + 0xbfe05df3ec31b8b6, 0x3feb7f6686e792ea, // -0.51147, 0.8593 + 0xbfe073879922ffed, 0x3feb728345196e3e, // -0.5141, 0.85773 + 0xbfe089112032b08c, 0x3feb658f14fdbc47, // -0.51673, 0.85615 + 0xbfe09e907417c5e1, 0x3feb5889fe921405, // -0.51936, 0.85456 + 0xbfe0b405878f85ec, 0x3feb4b7409de7925, // -0.52198, 0.85296 + 0xbfe0c9704d5d898f, 0x3feb3e4d3ef55712, // -0.52459, 0.85136 + 0xbfe0ded0b84bc4b5, 0x3feb3115a5f37bf4, // -0.5272, 0.84974 + 0xbfe0f426bb2a8e7d, 0x3feb23cd470013b4, // -0.5298, 0.84812 + 0xbfe1097248d0a956, 0x3feb16742a4ca2f5, // -0.5324, 0.84649 + 0xbfe11eb3541b4b22, 0x3feb090a58150200, // -0.535, 0.84485 + 0xbfe133e9cfee254e, 0x3feafb8fd89f57b6, // -0.53759, 0.84321 + 0xbfe14915af336ceb, 0x3feaee04b43c1474, // -0.54017, 0.84155 + 0xbfe15e36e4dbe2bc, 0x3feae068f345ecef, // -0.54275, 0.83989 + 0xbfe1734d63dedb49, 0x3fead2bc9e21d511, // -0.54532, 0.83822 + 0xbfe188591f3a46e5, 0x3feac4ffbd3efac8, // -0.54789, 0.83655 + 0xbfe19d5a09f2b9b8, 0x3feab7325916c0d4, // -0.55046, 0.83486 + 0xbfe1b250171373be, 0x3feaa9547a2cb98e, // -0.55302, 0.83317 + 0xbfe1c73b39ae68c8, 0x3fea9b66290ea1a3, // -0.55557, 0.83147 + 0xbfe1dc1b64dc4872, 0x3fea8d676e545ad2, // -0.55812, 0.82976 + 0xbfe1f0f08bbc861b, 0x3fea7f58529fe69d, // -0.56066, 0.82805 + 0xbfe205baa17560d6, 0x3fea7138de9d60f5, // -0.5632, 0.82632 + 0xbfe21a799933eb58, 0x3fea63091b02fae2, // -0.56573, 0.82459 + 0xbfe22f2d662c13e1, 0x3fea54c91090f524, // -0.56826, 0.82285 + 0xbfe243d5fb98ac1f, 0x3fea4678c8119ac8, // -0.57078, 0.8211 + 0xbfe258734cbb7110, 0x3fea38184a593bc6, // -0.5733, 0.81935 + 0xbfe26d054cdd12df, 0x3fea29a7a0462782, // -0.57581, 0.81758 + 0xbfe2818bef4d3cba, 0x3fea1b26d2c0a75e, // -0.57831, 0.81581 + 0xbfe2960727629ca8, 0x3fea0c95eabaf937, // -0.58081, 0.81404 + 0xbfe2aa76e87aeb58, 0x3fe9fdf4f13149de, // -0.58331, 0.81225 + 0xbfe2bedb25faf3ea, 0x3fe9ef43ef29af94, // -0.5858, 0.81046 + 0xbfe2d333d34e9bb7, 0x3fe9e082edb42472, // -0.58828, 0.80866 + 0xbfe2e780e3e8ea16, 0x3fe9d1b1f5ea80d6, // -0.59076, 0.80685 + 0xbfe2fbc24b441015, 0x3fe9c2d110f075c3, // -0.59323, 0.80503 + 0xbfe30ff7fce17035, 0x3fe9b3e047f38741, // -0.5957, 0.80321 + 0xbfe32421ec49a620, 0x3fe9a4dfa42b06b2, // -0.59816, 0.80138 + 0xbfe338400d0c8e57, 0x3fe995cf2ed80d22, // -0.60062, 0.79954 + 0xbfe34c5252c14de1, 0x3fe986aef1457594, // -0.60307, 0.79769 + 0xbfe36058b10659f3, 0x3fe9777ef4c7d742, // -0.60551, 0.79584 + 0xbfe374531b817f8d, 0x3fe9683f42bd7fe1, // -0.60795, 0.79398 + 0xbfe3884185dfeb22, 0x3fe958efe48e6dd7, // -0.61038, 0.79211 + 0xbfe39c23e3d63029, 0x3fe94990e3ac4a6c, // -0.61281, 0.79023 + 0xbfe3affa292050b9, 0x3fe93a22499263fc, // -0.61523, 0.78835 + 0xbfe3c3c44981c517, 0x3fe92aa41fc5a815, // -0.61765, 0.78646 + 0xbfe3d78238c58343, 0x3fe91b166fd49da2, // -0.62006, 0.78456 + 0xbfe3eb33eabe0680, 0x3fe90b7943575efe, // -0.62246, 0.78265 + 0xbfe3fed9534556d4, 0x3fe8fbcca3ef940d, // -0.62486, 0.78074 + 0xbfe41272663d108c, 0x3fe8ec109b486c49, // -0.62725, 0.77882 + 0xbfe425ff178e6bb1, 0x3fe8dc45331698cc, // -0.62964, 0.77689 + 0xbfe4397f5b2a4380, 0x3fe8cc6a75184655, // -0.63202, 0.77495 + 0xbfe44cf325091dd6, 0x3fe8bc806b151741, // -0.63439, 0.77301 + 0xbfe4605a692b32a2, 0x3fe8ac871ede1d88, // -0.63676, 0.77106 + 0xbfe473b51b987347, 0x3fe89c7e9a4dd4ab, // -0.63912, 0.7691 + 0xbfe48703306091fe, 0x3fe88c66e7481ba1, // -0.64148, 0.76714 + 0xbfe49a449b9b0938, 0x3fe87c400fba2ebf, // -0.64383, 0.76517 + 0xbfe4ad79516722f0, 0x3fe86c0a1d9aa195, // -0.64618, 0.76319 + 0xbfe4c0a145ec0004, 0x3fe85bc51ae958cc, // -0.64851, 0.7612 + 0xbfe4d3bc6d589f80, 0x3fe84b7111af83f9, // -0.65085, 0.75921 + 0xbfe4e6cabbe3e5e9, 0x3fe83b0e0bff976e, // -0.65317, 0.75721 + 0xbfe4f9cc25cca486, 0x3fe82a9c13f545ff, // -0.65549, 0.7552 + 0xbfe50cc09f59a09b, 0x3fe81a1b33b57acc, // -0.65781, 0.75319 + 0xbfe51fa81cd99aa6, 0x3fe8098b756e52fa, // -0.66011, 0.75117 + 0xbfe5328292a35596, 0x3fe7f8ece3571771, // -0.66242, 0.74914 + 0xbfe5454ff5159dfb, 0x3fe7e83f87b03686, // -0.66471, 0.7471 + 0xbfe5581038975137, 0x3fe7d7836cc33db2, // -0.667, 0.74506 + 0xbfe56ac35197649e, 0x3fe7c6b89ce2d333, // -0.66928, 0.74301 + 0xbfe57d69348cec9f, 0x3fe7b5df226aafb0, // -0.67156, 0.74095 + 0xbfe59001d5f723df, 0x3fe7a4f707bf97d2, // -0.67383, 0.73889 + 0xbfe5a28d2a5d7250, 0x3fe79400574f55e4, // -0.67609, 0.73682 + 0xbfe5b50b264f7448, 0x3fe782fb1b90b35b, // -0.67835, 0.73474 + 0xbfe5c77bbe65018c, 0x3fe771e75f037261, // -0.6806, 0.73265 + 0xbfe5d9dee73e345c, 0x3fe760c52c304764, // -0.68285, 0.73056 + 0xbfe5ec3495837074, 0x3fe74f948da8d28d, // -0.68508, 0.72846 + 0xbfe5fe7cbde56a0f, 0x3fe73e558e079942, // -0.68732, 0.72636 + 0xbfe610b7551d2cde, 0x3fe72d0837efff97, // -0.68954, 0.72425 + 0xbfe622e44fec22ff, 0x3fe71bac960e41bf, // -0.69176, 0.72213 + 0xbfe63503a31c1be8, 0x3fe70a42b3176d7a, // -0.69397, 0.72 + 0xbfe64715437f535b, 0x3fe6f8ca99c95b75, // -0.69618, 0.71787 + 0xbfe6591925f0783e, 0x3fe6e74454eaa8ae, // -0.69838, 0.71573 + 0xbfe66b0f3f52b386, 0x3fe6d5afef4aafcc, // -0.70057, 0.71358 + 0xbfe67cf78491af10, 0x3fe6c40d73c18275, // -0.70275, 0.71143 + 0xbfe68ed1eaa19c71, 0x3fe6b25ced2fe29c, // -0.70493, 0.70927 + 0xbfe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // -0.70711, 0.70711 + 0xbfe6b25ced2fe29c, 0x3fe68ed1eaa19c71, // -0.70927, 0.70493 + 0xbfe6c40d73c18275, 0x3fe67cf78491af10, // -0.71143, 0.70275 + 0xbfe6d5afef4aafcc, 0x3fe66b0f3f52b386, // -0.71358, 0.70057 + 0xbfe6e74454eaa8ae, 0x3fe6591925f0783e, // -0.71573, 0.69838 + 0xbfe6f8ca99c95b75, 0x3fe64715437f535b, // -0.71787, 0.69618 + 0xbfe70a42b3176d7a, 0x3fe63503a31c1be8, // -0.72, 0.69397 + 0xbfe71bac960e41bf, 0x3fe622e44fec22ff, // -0.72213, 0.69176 + 0xbfe72d0837efff97, 0x3fe610b7551d2cde, // -0.72425, 0.68954 + 0xbfe73e558e079942, 0x3fe5fe7cbde56a0f, // -0.72636, 0.68732 + 0xbfe74f948da8d28d, 0x3fe5ec3495837074, // -0.72846, 0.68508 + 0xbfe760c52c304764, 0x3fe5d9dee73e345c, // -0.73056, 0.68285 + 0xbfe771e75f037261, 0x3fe5c77bbe65018c, // -0.73265, 0.6806 + 0xbfe782fb1b90b35b, 0x3fe5b50b264f7448, // -0.73474, 0.67835 + 0xbfe79400574f55e4, 0x3fe5a28d2a5d7250, // -0.73682, 0.67609 + 0xbfe7a4f707bf97d2, 0x3fe59001d5f723df, // -0.73889, 0.67383 + 0xbfe7b5df226aafb0, 0x3fe57d69348cec9f, // -0.74095, 0.67156 + 0xbfe7c6b89ce2d333, 0x3fe56ac35197649e, // -0.74301, 0.66928 + 0xbfe7d7836cc33db2, 0x3fe5581038975137, // -0.74506, 0.667 + 0xbfe7e83f87b03686, 0x3fe5454ff5159dfb, // -0.7471, 0.66471 + 0xbfe7f8ece3571771, 0x3fe5328292a35596, // -0.74914, 0.66242 + 0xbfe8098b756e52fa, 0x3fe51fa81cd99aa6, // -0.75117, 0.66011 + 0xbfe81a1b33b57acc, 0x3fe50cc09f59a09b, // -0.75319, 0.65781 + 0xbfe82a9c13f545ff, 0x3fe4f9cc25cca486, // -0.7552, 0.65549 + 0xbfe83b0e0bff976e, 0x3fe4e6cabbe3e5e9, // -0.75721, 0.65317 + 0xbfe84b7111af83f9, 0x3fe4d3bc6d589f80, // -0.75921, 0.65085 + 0xbfe85bc51ae958cc, 0x3fe4c0a145ec0004, // -0.7612, 0.64851 + 0xbfe86c0a1d9aa195, 0x3fe4ad79516722f0, // -0.76319, 0.64618 + 0xbfe87c400fba2ebf, 0x3fe49a449b9b0938, // -0.76517, 0.64383 + 0xbfe88c66e7481ba1, 0x3fe48703306091fe, // -0.76714, 0.64148 + 0xbfe89c7e9a4dd4ab, 0x3fe473b51b987347, // -0.7691, 0.63912 + 0xbfe8ac871ede1d88, 0x3fe4605a692b32a2, // -0.77106, 0.63676 + 0xbfe8bc806b151741, 0x3fe44cf325091dd6, // -0.77301, 0.63439 + 0xbfe8cc6a75184655, 0x3fe4397f5b2a4380, // -0.77495, 0.63202 + 0xbfe8dc45331698cc, 0x3fe425ff178e6bb1, // -0.77689, 0.62964 + 0xbfe8ec109b486c49, 0x3fe41272663d108c, // -0.77882, 0.62725 + 0xbfe8fbcca3ef940d, 0x3fe3fed9534556d4, // -0.78074, 0.62486 + 0xbfe90b7943575efe, 0x3fe3eb33eabe0680, // -0.78265, 0.62246 + 0xbfe91b166fd49da2, 0x3fe3d78238c58343, // -0.78456, 0.62006 + 0xbfe92aa41fc5a815, 0x3fe3c3c44981c517, // -0.78646, 0.61765 + 0xbfe93a22499263fc, 0x3fe3affa292050b9, // -0.78835, 0.61523 + 0xbfe94990e3ac4a6c, 0x3fe39c23e3d63029, // -0.79023, 0.61281 + 0xbfe958efe48e6dd7, 0x3fe3884185dfeb22, // -0.79211, 0.61038 + 0xbfe9683f42bd7fe1, 0x3fe374531b817f8d, // -0.79398, 0.60795 + 0xbfe9777ef4c7d742, 0x3fe36058b10659f3, // -0.79584, 0.60551 + 0xbfe986aef1457594, 0x3fe34c5252c14de1, // -0.79769, 0.60307 + 0xbfe995cf2ed80d22, 0x3fe338400d0c8e57, // -0.79954, 0.60062 + 0xbfe9a4dfa42b06b2, 0x3fe32421ec49a620, // -0.80138, 0.59816 + 0xbfe9b3e047f38741, 0x3fe30ff7fce17035, // -0.80321, 0.5957 + 0xbfe9c2d110f075c3, 0x3fe2fbc24b441015, // -0.80503, 0.59323 + 0xbfe9d1b1f5ea80d6, 0x3fe2e780e3e8ea16, // -0.80685, 0.59076 + 0xbfe9e082edb42472, 0x3fe2d333d34e9bb7, // -0.80866, 0.58828 + 0xbfe9ef43ef29af94, 0x3fe2bedb25faf3ea, // -0.81046, 0.5858 + 0xbfe9fdf4f13149de, 0x3fe2aa76e87aeb58, // -0.81225, 0.58331 + 0xbfea0c95eabaf937, 0x3fe2960727629ca8, // -0.81404, 0.58081 + 0xbfea1b26d2c0a75e, 0x3fe2818bef4d3cba, // -0.81581, 0.57831 + 0xbfea29a7a0462782, 0x3fe26d054cdd12df, // -0.81758, 0.57581 + 0xbfea38184a593bc6, 0x3fe258734cbb7110, // -0.81935, 0.5733 + 0xbfea4678c8119ac8, 0x3fe243d5fb98ac1f, // -0.8211, 0.57078 + 0xbfea54c91090f524, 0x3fe22f2d662c13e1, // -0.82285, 0.56826 + 0xbfea63091b02fae2, 0x3fe21a799933eb58, // -0.82459, 0.56573 + 0xbfea7138de9d60f5, 0x3fe205baa17560d6, // -0.82632, 0.5632 + 0xbfea7f58529fe69d, 0x3fe1f0f08bbc861b, // -0.82805, 0.56066 + 0xbfea8d676e545ad2, 0x3fe1dc1b64dc4872, // -0.82976, 0.55812 + 0xbfea9b66290ea1a3, 0x3fe1c73b39ae68c8, // -0.83147, 0.55557 + 0xbfeaa9547a2cb98e, 0x3fe1b250171373be, // -0.83317, 0.55302 + 0xbfeab7325916c0d4, 0x3fe19d5a09f2b9b8, // -0.83486, 0.55046 + 0xbfeac4ffbd3efac8, 0x3fe188591f3a46e5, // -0.83655, 0.54789 + 0xbfead2bc9e21d511, 0x3fe1734d63dedb49, // -0.83822, 0.54532 + 0xbfeae068f345ecef, 0x3fe15e36e4dbe2bc, // -0.83989, 0.54275 + 0xbfeaee04b43c1474, 0x3fe14915af336ceb, // -0.84155, 0.54017 + 0xbfeafb8fd89f57b6, 0x3fe133e9cfee254e, // -0.84321, 0.53759 + 0xbfeb090a58150200, 0x3fe11eb3541b4b22, // -0.84485, 0.535 + 0xbfeb16742a4ca2f5, 0x3fe1097248d0a956, // -0.84649, 0.5324 + 0xbfeb23cd470013b4, 0x3fe0f426bb2a8e7d, // -0.84812, 0.5298 + 0xbfeb3115a5f37bf4, 0x3fe0ded0b84bc4b5, // -0.84974, 0.5272 + 0xbfeb3e4d3ef55712, 0x3fe0c9704d5d898f, // -0.85136, 0.52459 + 0xbfeb4b7409de7925, 0x3fe0b405878f85ec, // -0.85296, 0.52198 + 0xbfeb5889fe921405, 0x3fe09e907417c5e1, // -0.85456, 0.51936 + 0xbfeb658f14fdbc47, 0x3fe089112032b08c, // -0.85615, 0.51673 + 0xbfeb728345196e3e, 0x3fe073879922ffed, // -0.85773, 0.5141 + 0xbfeb7f6686e792ea, 0x3fe05df3ec31b8b6, // -0.8593, 0.51147 + 0xbfeb8c38d27504e9, 0x3fe0485626ae221a, // -0.86087, 0.50883 + 0xbfeb98fa1fd9155e, 0x3fe032ae55edbd95, // -0.86242, 0.50619 + 0xbfeba5aa673590d2, 0x3fe01cfc874c3eb7, // -0.86397, 0.50354 + 0xbfebb249a0b6c40d, 0x3fe00740c82b82e0, // -0.86551, 0.50089 + 0xbfebbed7c49380ea, 0x3fdfe2f64be7120f, // -0.86705, 0.49823 + 0xbfebcb54cb0d2327, 0x3fdfb7575c24d2de, // -0.86857, 0.49557 + 0xbfebd7c0ac6f952a, 0x3fdf8ba4dbf89aba, // -0.87009, 0.4929 + 0xbfebe41b611154c1, 0x3fdf5fdee656cda3, // -0.8716, 0.49023 + 0xbfebf064e15377dd, 0x3fdf3405963fd068, // -0.87309, 0.48755 + 0xbfebfc9d25a1b147, 0x3fdf081906bff7fd, // -0.87459, 0.48487 + 0xbfec08c426725549, 0x3fdedc1952ef78d5, // -0.87607, 0.48218 + 0xbfec14d9dc465e58, 0x3fdeb00695f25620, // -0.87755, 0.47949 + 0xbfec20de3fa971b0, 0x3fde83e0eaf85113, // -0.87901, 0.4768 + 0xbfec2cd14931e3f1, 0x3fde57a86d3cd824, // -0.88047, 0.4741 + 0xbfec38b2f180bdb1, 0x3fde2b5d3806f63b, // -0.88192, 0.4714 + 0xbfec44833141c004, 0x3fddfeff66a941de, // -0.88336, 0.46869 + 0xbfec5042012b6907, 0x3fddd28f1481cc58, // -0.8848, 0.46598 + 0xbfec5bef59fef85a, 0x3fdda60c5cfa10d8, // -0.88622, 0.46326 + 0xbfec678b3488739b, 0x3fdd79775b86e389, // -0.88764, 0.46054 + 0xbfec7315899eaad7, 0x3fdd4cd02ba8609c, // -0.88905, 0.45781 + 0xbfec7e8e52233cf3, 0x3fdd2016e8e9db5b, // -0.89045, 0.45508 + 0xbfec89f587029c13, 0x3fdcf34baee1cd21, // -0.89184, 0.45235 + 0xbfec954b213411f5, 0x3fdcc66e9931c45d, // -0.89322, 0.44961 + 0xbfeca08f19b9c449, 0x3fdc997fc3865388, // -0.8946, 0.44687 + 0xbfecabc169a0b901, 0x3fdc6c7f4997000a, // -0.89597, 0.44412 + 0xbfecb6e20a00da99, 0x3fdc3f6d47263129, // -0.89732, 0.44137 + 0xbfecc1f0f3fcfc5c, 0x3fdc1249d8011ee7, // -0.89867, 0.43862 + 0xbfecccee20c2de9f, 0x3fdbe51517ffc0d9, // -0.90002, 0.43586 + 0xbfecd7d9898b32f6, 0x3fdbb7cf2304bd01, // -0.90135, 0.43309 + 0xbfece2b32799a060, 0x3fdb8a7814fd5693, // -0.90267, 0.43033 + 0xbfeced7af43cc773, 0x3fdb5d1009e15cc0, // -0.90399, 0.42756 + 0xbfecf830e8ce467b, 0x3fdb2f971db31972, // -0.9053, 0.42478 + 0xbfed02d4feb2bd92, 0x3fdb020d6c7f4009, // -0.9066, 0.422 + 0xbfed0d672f59d2b9, 0x3fdad473125cdc08, // -0.90789, 0.41922 + 0xbfed17e7743e35dc, 0x3fdaa6c82b6d3fc9, // -0.90917, 0.41643 + 0xbfed2255c6e5a4e1, 0x3fda790cd3dbf31a, // -0.91044, 0.41364 + 0xbfed2cb220e0ef9f, 0x3fda4b4127dea1e4, // -0.91171, 0.41084 + 0xbfed36fc7bcbfbdc, 0x3fda1d6543b50ac0, // -0.91296, 0.40804 + 0xbfed4134d14dc93a, 0x3fd9ef7943a8ed8a, // -0.91421, 0.40524 + 0xbfed4b5b1b187524, 0x3fd9c17d440df9f2, // -0.91545, 0.40243 + 0xbfed556f52e93eb1, 0x3fd993716141bdfe, // -0.91668, 0.39962 + 0xbfed5f7172888a7f, 0x3fd96555b7ab948f, // -0.9179, 0.39681 + 0xbfed696173c9e68b, 0x3fd9372a63bc93d7, // -0.91911, 0.39399 + 0xbfed733f508c0dff, 0x3fd908ef81ef7bd1, // -0.92032, 0.39117 + 0xbfed7d0b02b8ecf9, 0x3fd8daa52ec8a4af, // -0.92151, 0.38835 + 0xbfed86c48445a450, 0x3fd8ac4b86d5ed44, // -0.9227, 0.38552 + 0xbfed906bcf328d46, 0x3fd87de2a6aea963, // -0.92388, 0.38268 + 0xbfed9a00dd8b3d46, 0x3fd84f6aaaf3903f, // -0.92505, 0.37985 + 0xbfeda383a9668988, 0x3fd820e3b04eaac4, // -0.92621, 0.37701 + 0xbfedacf42ce68ab9, 0x3fd7f24dd37341e3, // -0.92736, 0.37416 + 0xbfedb6526238a09b, 0x3fd7c3a9311dcce7, // -0.92851, 0.37132 + 0xbfedbf9e4395759a, 0x3fd794f5e613dfae, // -0.92964, 0.36847 + 0xbfedc8d7cb410260, 0x3fd766340f2418f6, // -0.93077, 0.36561 + 0xbfedd1fef38a915a, 0x3fd73763c9261092, // -0.93188, 0.36276 + 0xbfeddb13b6ccc23d, 0x3fd7088530fa459e, // -0.93299, 0.3599 + 0xbfede4160f6d8d81, 0x3fd6d998638a0cb5, // -0.93409, 0.35703 + 0xbfeded05f7de47da, 0x3fd6aa9d7dc77e16, // -0.93518, 0.35416 + 0xbfedf5e36a9ba59c, 0x3fd67b949cad63ca, // -0.93627, 0.35129 + 0xbfedfeae622dbe2b, 0x3fd64c7ddd3f27c6, // -0.93734, 0.34842 + 0xbfee0766d9280f54, 0x3fd61d595c88c203, // -0.9384, 0.34554 + 0xbfee100cca2980ac, 0x3fd5ee27379ea693, // -0.93946, 0.34266 + 0xbfee18a02fdc66d9, 0x3fd5bee78b9db3b6, // -0.94051, 0.33978 + 0xbfee212104f686e5, 0x3fd58f9a75ab1fdd, // -0.94154, 0.33689 + 0xbfee298f4439197a, 0x3fd5604012f467b4, // -0.94257, 0.334 + 0xbfee31eae870ce25, 0x3fd530d880af3c24, // -0.94359, 0.33111 + 0xbfee3a33ec75ce85, 0x3fd50163dc197047, // -0.9446, 0.32821 + 0xbfee426a4b2bc17e, 0x3fd4d1e24278e76a, // -0.94561, 0.32531 + 0xbfee4a8dff81ce5e, 0x3fd4a253d11b82f3, // -0.9466, 0.32241 + 0xbfee529f04729ffc, 0x3fd472b8a5571054, // -0.94759, 0.3195 + 0xbfee5a9d550467d3, 0x3fd44310dc8936f0, // -0.94856, 0.31659 + 0xbfee6288ec48e112, 0x3fd4135c94176602, // -0.94953, 0.31368 + 0xbfee6a61c55d53a7, 0x3fd3e39be96ec271, // -0.95049, 0.31077 + 0xbfee7227db6a9744, 0x3fd3b3cefa0414b7, // -0.95144, 0.30785 + 0xbfee79db29a5165a, 0x3fd383f5e353b6aa, // -0.95238, 0.30493 + 0xbfee817bab4cd10d, 0x3fd35410c2e18152, // -0.95331, 0.30201 + 0xbfee89095bad6025, 0x3fd3241fb638baaf, // -0.95423, 0.29908 + 0xbfee9084361df7f3, 0x3fd2f422daec0386, // -0.95514, 0.29615 + 0xbfee97ec36016b30, 0x3fd2c41a4e954520, // -0.95605, 0.29322 + 0xbfee9f4156c62dda, 0x3fd294062ed59f05, // -0.95694, 0.29028 + 0xbfeea68393e65800, 0x3fd263e6995554ba, // -0.95783, 0.28735 + 0xbfeeadb2e8e7a88e, 0x3fd233bbabc3bb72, // -0.9587, 0.28441 + 0xbfeeb4cf515b8811, 0x3fd2038583d727bd, // -0.95957, 0.28146 + 0xbfeebbd8c8df0b74, 0x3fd1d3443f4cdb3d, // -0.96043, 0.27852 + 0xbfeec2cf4b1af6b2, 0x3fd1a2f7fbe8f243, // -0.96128, 0.27557 + 0xbfeec9b2d3c3bf84, 0x3fd172a0d7765177, // -0.96212, 0.27262 + 0xbfeed0835e999009, 0x3fd1423eefc69378, // -0.96295, 0.26967 + 0xbfeed740e7684963, 0x3fd111d262b1f677, // -0.96378, 0.26671 + 0xbfeeddeb6a078651, 0x3fd0e15b4e1749cd, // -0.96459, 0.26375 + 0xbfeee482e25a9dbc, 0x3fd0b0d9cfdbdb90, // -0.96539, 0.26079 + 0xbfeeeb074c50a544, 0x3fd0804e05eb661e, // -0.96619, 0.25783 + 0xbfeef178a3e473c2, 0x3fd04fb80e37fdae, // -0.96698, 0.25487 + 0xbfeef7d6e51ca3c0, 0x3fd01f1806b9fdd2, // -0.96775, 0.2519 + 0xbfeefe220c0b95ec, 0x3fcfdcdc1adfedf8, // -0.96852, 0.24893 + 0xbfef045a14cf738c, 0x3fcf7b7480bd3801, // -0.96928, 0.24596 + 0xbfef0a7efb9230d7, 0x3fcf19f97b215f1a, // -0.97003, 0.24298 + 0xbfef1090bc898f5f, 0x3fceb86b462de348, // -0.97077, 0.24 + 0xbfef168f53f7205d, 0x3fce56ca1e101a1b, // -0.9715, 0.23702 + 0xbfef1c7abe284708, 0x3fcdf5163f01099a, // -0.97223, 0.23404 + 0xbfef2252f7763ada, 0x3fcd934fe5454311, // -0.97294, 0.23106 + 0xbfef2817fc4609ce, 0x3fcd31774d2cbdee, // -0.97364, 0.22807 + 0xbfef2dc9c9089a9d, 0x3fcccf8cb312b286, // -0.97434, 0.22508 + 0xbfef33685a3aaef0, 0x3fcc6d90535d74dc, // -0.97503, 0.22209 + 0xbfef38f3ac64e589, 0x3fcc0b826a7e4f63, // -0.9757, 0.2191 + 0xbfef3e6bbc1bbc65, 0x3fcba96334f15dad, // -0.97637, 0.21611 + 0xbfef43d085ff92dd, 0x3fcb4732ef3d6722, // -0.97703, 0.21311 + 0xbfef492206bcabb4, 0x3fcae4f1d5f3b9ab, // -0.97768, 0.21011 + 0xbfef4e603b0b2f2d, 0x3fca82a025b00451, // -0.97832, 0.20711 + 0xbfef538b1faf2d07, 0x3fca203e1b1831da, // -0.97895, 0.20411 + 0xbfef58a2b1789e84, 0x3fc9bdcbf2dc4366, // -0.97957, 0.2011 + 0xbfef5da6ed43685d, 0x3fc95b49e9b62af9, // -0.98018, 0.1981 + 0xbfef6297cff75cb0, 0x3fc8f8b83c69a60a, // -0.98079, 0.19509 + 0xbfef677556883cee, 0x3fc8961727c41804, // -0.98138, 0.19208 + 0xbfef6c3f7df5bbb7, 0x3fc83366e89c64c5, // -0.98196, 0.18907 + 0xbfef70f6434b7eb7, 0x3fc7d0a7bbd2cb1b, // -0.98254, 0.18606 + 0xbfef7599a3a12077, 0x3fc76dd9de50bf31, // -0.98311, 0.18304 + 0xbfef7a299c1a322a, 0x3fc70afd8d08c4ff, // -0.98366, 0.18002 + 0xbfef7ea629e63d6e, 0x3fc6a81304f64ab2, // -0.98421, 0.177 + 0xbfef830f4a40c60c, 0x3fc6451a831d830d, // -0.98475, 0.17398 + 0xbfef8764fa714ba9, 0x3fc5e214448b3fc6, // -0.98528, 0.17096 + 0xbfef8ba737cb4b78, 0x3fc57f008654cbde, // -0.9858, 0.16794 + 0xbfef8fd5ffae41db, 0x3fc51bdf8597c5f2, // -0.98631, 0.16491 + 0xbfef93f14f85ac08, 0x3fc4b8b17f79fa88, // -0.98681, 0.16189 + 0xbfef97f924c9099b, 0x3fc45576b1293e5a, // -0.9873, 0.15886 + 0xbfef9bed7cfbde29, 0x3fc3f22f57db4893, // -0.98778, 0.15583 + 0xbfef9fce55adb2c8, 0x3fc38edbb0cd8d14, // -0.98826, 0.1528 + 0xbfefa39bac7a1791, 0x3fc32b7bf94516a7, // -0.98872, 0.14976 + 0xbfefa7557f08a517, 0x3fc2c8106e8e613a, // -0.98918, 0.14673 + 0xbfefaafbcb0cfddc, 0x3fc264994dfd340a, // -0.98962, 0.1437 + 0xbfefae8e8e46cfbb, 0x3fc20116d4ec7bce, // -0.99006, 0.14066 + 0xbfefb20dc681d54d, 0x3fc19d8940be24e7, // -0.99049, 0.13762 + 0xbfefb5797195d741, 0x3fc139f0cedaf576, // -0.9909, 0.13458 + 0xbfefb8d18d66adb7, 0x3fc0d64dbcb26786, // -0.99131, 0.13154 + 0xbfefbc1617e44186, 0x3fc072a047ba831d, // -0.99171, 0.1285 + 0xbfefbf470f0a8d88, 0x3fc00ee8ad6fb85b, // -0.9921, 0.12545 + 0xbfefc26470e19fd3, 0x3fbf564e56a9730e, // -0.99248, 0.12241 + 0xbfefc56e3b7d9af6, 0x3fbe8eb7fde4aa3e, // -0.99285, 0.11937 + 0xbfefc8646cfeb721, 0x3fbdc70ecbae9fc8, // -0.99321, 0.11632 + 0xbfefcb4703914354, 0x3fbcff533b307dc1, // -0.99356, 0.11327 + 0xbfefce15fd6da67b, 0x3fbc3785c79ec2d5, // -0.99391, 0.11022 + 0xbfefd0d158d86087, 0x3fbb6fa6ec38f64c, // -0.99424, 0.10717 + 0xbfefd37914220b84, 0x3fbaa7b724495c04, // -0.99456, 0.10412 + 0xbfefd60d2da75c9e, 0x3fb9dfb6eb24a85c, // -0.99488, 0.10107 + 0xbfefd88da3d12526, 0x3fb917a6bc29b42c, // -0.99518, 0.098017 + 0xbfefdafa7514538c, 0x3fb84f8712c130a0, // -0.99548, 0.094963 + 0xbfefdd539ff1f456, 0x3fb787586a5d5b21, // -0.99577, 0.091909 + 0xbfefdf9922f73307, 0x3fb6bf1b3e79b129, // -0.99604, 0.088854 + 0xbfefe1cafcbd5b09, 0x3fb5f6d00a9aa419, // -0.99631, 0.085797 + 0xbfefe3e92be9d886, 0x3fb52e774a4d4d0a, // -0.99657, 0.08274 + 0xbfefe5f3af2e3940, 0x3fb4661179272096, // -0.99682, 0.079682 + 0xbfefe7ea85482d60, 0x3fb39d9f12c5a299, // -0.99706, 0.076624 + 0xbfefe9cdad01883a, 0x3fb2d52092ce19f6, // -0.99729, 0.073565 + 0xbfefeb9d2530410f, 0x3fb20c9674ed444c, // -0.99751, 0.070505 + 0xbfefed58ecb673c4, 0x3fb1440134d709b2, // -0.99772, 0.067444 + 0xbfefef0102826191, 0x3fb07b614e463064, // -0.99793, 0.064383 + 0xbfeff095658e71ad, 0x3faf656e79f820e0, // -0.99812, 0.061321 + 0xbfeff21614e131ed, 0x3fadd406f9808ec8, // -0.9983, 0.058258 + 0xbfeff3830f8d575c, 0x3fac428d12c0d7e3, // -0.99848, 0.055195 + 0xbfeff4dc54b1bed3, 0x3faab101bd5f8317, // -0.99864, 0.052132 + 0xbfeff621e3796d7e, 0x3fa91f65f10dd814, // -0.9988, 0.049068 + 0xbfeff753bb1b9164, 0x3fa78dbaa5874685, // -0.99894, 0.046003 + 0xbfeff871dadb81df, 0x3fa5fc00d290cd43, // -0.99908, 0.042938 + 0xbfeff97c4208c014, 0x3fa46a396ff86179, // -0.9992, 0.039873 + 0xbfeffa72effef75d, 0x3fa2d865759455cd, // -0.99932, 0.036807 + 0xbfeffb55e425fdae, 0x3fa14685db42c17e, // -0.99943, 0.033741 + 0xbfeffc251df1d3f8, 0x3f9f693731d1cf01, // -0.99953, 0.030675 + 0xbfeffce09ce2a679, 0x3f9c454f4ce53b1c, // -0.99962, 0.027608 + 0xbfeffd886084cd0d, 0x3f992155f7a3667e, // -0.9997, 0.024541 + 0xbfeffe1c6870cb77, 0x3f95fd4d21fab226, // -0.99977, 0.021474 + 0xbfeffe9cb44b51a1, 0x3f92d936bbe30efd, // -0.99983, 0.018407 + 0xbfefff0943c53bd1, 0x3f8f6a296ab997ca, // -0.99988, 0.015339 + 0xbfefff62169b92db, 0x3f8921d1fcdec784, // -0.99992, 0.012272 + 0xbfefffa72c978c4f, 0x3f82d96b0e509703, // -0.99996, 0.0092038 + 0xbfefffd8858e8a92, 0x3f7921f0fe670071, // -0.99998, 0.0061359 + 0xbfeffff621621d02, 0x3f6921f8becca4ba, // -1, 0.003068 + 0xbff0000000000000, 0x0000000000000000, // -1, 0 + 0xbfeffff621621d02, 0xbf6921f8becca4ba, // -1, -0.003068 + 0xbfefffd8858e8a92, 0xbf7921f0fe670071, // -0.99998,-0.0061359 + 0xbfefffa72c978c4f, 0xbf82d96b0e509703, // -0.99996,-0.0092038 + 0xbfefff62169b92db, 0xbf8921d1fcdec784, // -0.99992, -0.012272 + 0xbfefff0943c53bd1, 0xbf8f6a296ab997ca, // -0.99988, -0.015339 + 0xbfeffe9cb44b51a1, 0xbf92d936bbe30efd, // -0.99983, -0.018407 + 0xbfeffe1c6870cb77, 0xbf95fd4d21fab226, // -0.99977, -0.021474 + 0xbfeffd886084cd0d, 0xbf992155f7a3667e, // -0.9997, -0.024541 + 0xbfeffce09ce2a679, 0xbf9c454f4ce53b1c, // -0.99962, -0.027608 + 0xbfeffc251df1d3f8, 0xbf9f693731d1cf01, // -0.99953, -0.030675 + 0xbfeffb55e425fdae, 0xbfa14685db42c17e, // -0.99943, -0.033741 + 0xbfeffa72effef75d, 0xbfa2d865759455cd, // -0.99932, -0.036807 + 0xbfeff97c4208c014, 0xbfa46a396ff86179, // -0.9992, -0.039873 + 0xbfeff871dadb81df, 0xbfa5fc00d290cd43, // -0.99908, -0.042938 + 0xbfeff753bb1b9164, 0xbfa78dbaa5874685, // -0.99894, -0.046003 + 0xbfeff621e3796d7e, 0xbfa91f65f10dd814, // -0.9988, -0.049068 + 0xbfeff4dc54b1bed3, 0xbfaab101bd5f8317, // -0.99864, -0.052132 + 0xbfeff3830f8d575c, 0xbfac428d12c0d7e3, // -0.99848, -0.055195 + 0xbfeff21614e131ed, 0xbfadd406f9808ec8, // -0.9983, -0.058258 + 0xbfeff095658e71ad, 0xbfaf656e79f820e0, // -0.99812, -0.061321 + 0xbfefef0102826191, 0xbfb07b614e463064, // -0.99793, -0.064383 + 0xbfefed58ecb673c4, 0xbfb1440134d709b2, // -0.99772, -0.067444 + 0xbfefeb9d2530410f, 0xbfb20c9674ed444c, // -0.99751, -0.070505 + 0xbfefe9cdad01883a, 0xbfb2d52092ce19f6, // -0.99729, -0.073565 + 0xbfefe7ea85482d60, 0xbfb39d9f12c5a299, // -0.99706, -0.076624 + 0xbfefe5f3af2e3940, 0xbfb4661179272096, // -0.99682, -0.079682 + 0xbfefe3e92be9d886, 0xbfb52e774a4d4d0a, // -0.99657, -0.08274 + 0xbfefe1cafcbd5b09, 0xbfb5f6d00a9aa419, // -0.99631, -0.085797 + 0xbfefdf9922f73307, 0xbfb6bf1b3e79b129, // -0.99604, -0.088854 + 0xbfefdd539ff1f456, 0xbfb787586a5d5b21, // -0.99577, -0.091909 + 0xbfefdafa7514538c, 0xbfb84f8712c130a0, // -0.99548, -0.094963 + 0xbfefd88da3d12526, 0xbfb917a6bc29b42c, // -0.99518, -0.098017 + 0xbfefd60d2da75c9e, 0xbfb9dfb6eb24a85c, // -0.99488, -0.10107 + 0xbfefd37914220b84, 0xbfbaa7b724495c04, // -0.99456, -0.10412 + 0xbfefd0d158d86087, 0xbfbb6fa6ec38f64c, // -0.99424, -0.10717 + 0xbfefce15fd6da67b, 0xbfbc3785c79ec2d5, // -0.99391, -0.11022 + 0xbfefcb4703914354, 0xbfbcff533b307dc1, // -0.99356, -0.11327 + 0xbfefc8646cfeb721, 0xbfbdc70ecbae9fc8, // -0.99321, -0.11632 + 0xbfefc56e3b7d9af6, 0xbfbe8eb7fde4aa3e, // -0.99285, -0.11937 + 0xbfefc26470e19fd3, 0xbfbf564e56a9730e, // -0.99248, -0.12241 + 0xbfefbf470f0a8d88, 0xbfc00ee8ad6fb85b, // -0.9921, -0.12545 + 0xbfefbc1617e44186, 0xbfc072a047ba831d, // -0.99171, -0.1285 + 0xbfefb8d18d66adb7, 0xbfc0d64dbcb26786, // -0.99131, -0.13154 + 0xbfefb5797195d741, 0xbfc139f0cedaf576, // -0.9909, -0.13458 + 0xbfefb20dc681d54d, 0xbfc19d8940be24e7, // -0.99049, -0.13762 + 0xbfefae8e8e46cfbb, 0xbfc20116d4ec7bce, // -0.99006, -0.14066 + 0xbfefaafbcb0cfddc, 0xbfc264994dfd340a, // -0.98962, -0.1437 + 0xbfefa7557f08a517, 0xbfc2c8106e8e613a, // -0.98918, -0.14673 + 0xbfefa39bac7a1791, 0xbfc32b7bf94516a7, // -0.98872, -0.14976 + 0xbfef9fce55adb2c8, 0xbfc38edbb0cd8d14, // -0.98826, -0.1528 + 0xbfef9bed7cfbde29, 0xbfc3f22f57db4893, // -0.98778, -0.15583 + 0xbfef97f924c9099b, 0xbfc45576b1293e5a, // -0.9873, -0.15886 + 0xbfef93f14f85ac08, 0xbfc4b8b17f79fa88, // -0.98681, -0.16189 + 0xbfef8fd5ffae41db, 0xbfc51bdf8597c5f2, // -0.98631, -0.16491 + 0xbfef8ba737cb4b78, 0xbfc57f008654cbde, // -0.9858, -0.16794 + 0xbfef8764fa714ba9, 0xbfc5e214448b3fc6, // -0.98528, -0.17096 + 0xbfef830f4a40c60c, 0xbfc6451a831d830d, // -0.98475, -0.17398 + 0xbfef7ea629e63d6e, 0xbfc6a81304f64ab2, // -0.98421, -0.177 + 0xbfef7a299c1a322a, 0xbfc70afd8d08c4ff, // -0.98366, -0.18002 + 0xbfef7599a3a12077, 0xbfc76dd9de50bf31, // -0.98311, -0.18304 + 0xbfef70f6434b7eb7, 0xbfc7d0a7bbd2cb1b, // -0.98254, -0.18606 + 0xbfef6c3f7df5bbb7, 0xbfc83366e89c64c5, // -0.98196, -0.18907 + 0xbfef677556883cee, 0xbfc8961727c41804, // -0.98138, -0.19208 + 0xbfef6297cff75cb0, 0xbfc8f8b83c69a60a, // -0.98079, -0.19509 + 0xbfef5da6ed43685d, 0xbfc95b49e9b62af9, // -0.98018, -0.1981 + 0xbfef58a2b1789e84, 0xbfc9bdcbf2dc4366, // -0.97957, -0.2011 + 0xbfef538b1faf2d07, 0xbfca203e1b1831da, // -0.97895, -0.20411 + 0xbfef4e603b0b2f2d, 0xbfca82a025b00451, // -0.97832, -0.20711 + 0xbfef492206bcabb4, 0xbfcae4f1d5f3b9ab, // -0.97768, -0.21011 + 0xbfef43d085ff92dd, 0xbfcb4732ef3d6722, // -0.97703, -0.21311 + 0xbfef3e6bbc1bbc65, 0xbfcba96334f15dad, // -0.97637, -0.21611 + 0xbfef38f3ac64e589, 0xbfcc0b826a7e4f63, // -0.9757, -0.2191 + 0xbfef33685a3aaef0, 0xbfcc6d90535d74dc, // -0.97503, -0.22209 + 0xbfef2dc9c9089a9d, 0xbfcccf8cb312b286, // -0.97434, -0.22508 + 0xbfef2817fc4609ce, 0xbfcd31774d2cbdee, // -0.97364, -0.22807 + 0xbfef2252f7763ada, 0xbfcd934fe5454311, // -0.97294, -0.23106 + 0xbfef1c7abe284708, 0xbfcdf5163f01099a, // -0.97223, -0.23404 + 0xbfef168f53f7205d, 0xbfce56ca1e101a1b, // -0.9715, -0.23702 + 0xbfef1090bc898f5f, 0xbfceb86b462de348, // -0.97077, -0.24 + 0xbfef0a7efb9230d7, 0xbfcf19f97b215f1a, // -0.97003, -0.24298 + 0xbfef045a14cf738c, 0xbfcf7b7480bd3801, // -0.96928, -0.24596 + 0xbfeefe220c0b95ec, 0xbfcfdcdc1adfedf8, // -0.96852, -0.24893 + 0xbfeef7d6e51ca3c0, 0xbfd01f1806b9fdd2, // -0.96775, -0.2519 + 0xbfeef178a3e473c2, 0xbfd04fb80e37fdae, // -0.96698, -0.25487 + 0xbfeeeb074c50a544, 0xbfd0804e05eb661e, // -0.96619, -0.25783 + 0xbfeee482e25a9dbc, 0xbfd0b0d9cfdbdb90, // -0.96539, -0.26079 + 0xbfeeddeb6a078651, 0xbfd0e15b4e1749cd, // -0.96459, -0.26375 + 0xbfeed740e7684963, 0xbfd111d262b1f677, // -0.96378, -0.26671 + 0xbfeed0835e999009, 0xbfd1423eefc69378, // -0.96295, -0.26967 + 0xbfeec9b2d3c3bf84, 0xbfd172a0d7765177, // -0.96212, -0.27262 + 0xbfeec2cf4b1af6b2, 0xbfd1a2f7fbe8f243, // -0.96128, -0.27557 + 0xbfeebbd8c8df0b74, 0xbfd1d3443f4cdb3d, // -0.96043, -0.27852 + 0xbfeeb4cf515b8811, 0xbfd2038583d727bd, // -0.95957, -0.28146 + 0xbfeeadb2e8e7a88e, 0xbfd233bbabc3bb72, // -0.9587, -0.28441 + 0xbfeea68393e65800, 0xbfd263e6995554ba, // -0.95783, -0.28735 + 0xbfee9f4156c62dda, 0xbfd294062ed59f05, // -0.95694, -0.29028 + 0xbfee97ec36016b30, 0xbfd2c41a4e954520, // -0.95605, -0.29322 + 0xbfee9084361df7f3, 0xbfd2f422daec0386, // -0.95514, -0.29615 + 0xbfee89095bad6025, 0xbfd3241fb638baaf, // -0.95423, -0.29908 + 0xbfee817bab4cd10d, 0xbfd35410c2e18152, // -0.95331, -0.30201 + 0xbfee79db29a5165a, 0xbfd383f5e353b6aa, // -0.95238, -0.30493 + 0xbfee7227db6a9744, 0xbfd3b3cefa0414b7, // -0.95144, -0.30785 + 0xbfee6a61c55d53a7, 0xbfd3e39be96ec271, // -0.95049, -0.31077 + 0xbfee6288ec48e112, 0xbfd4135c94176602, // -0.94953, -0.31368 + 0xbfee5a9d550467d3, 0xbfd44310dc8936f0, // -0.94856, -0.31659 + 0xbfee529f04729ffc, 0xbfd472b8a5571054, // -0.94759, -0.3195 + 0xbfee4a8dff81ce5e, 0xbfd4a253d11b82f3, // -0.9466, -0.32241 + 0xbfee426a4b2bc17e, 0xbfd4d1e24278e76a, // -0.94561, -0.32531 + 0xbfee3a33ec75ce85, 0xbfd50163dc197047, // -0.9446, -0.32821 + 0xbfee31eae870ce25, 0xbfd530d880af3c24, // -0.94359, -0.33111 + 0xbfee298f4439197a, 0xbfd5604012f467b4, // -0.94257, -0.334 + 0xbfee212104f686e5, 0xbfd58f9a75ab1fdd, // -0.94154, -0.33689 + 0xbfee18a02fdc66d9, 0xbfd5bee78b9db3b6, // -0.94051, -0.33978 + 0xbfee100cca2980ac, 0xbfd5ee27379ea693, // -0.93946, -0.34266 + 0xbfee0766d9280f54, 0xbfd61d595c88c203, // -0.9384, -0.34554 + 0xbfedfeae622dbe2b, 0xbfd64c7ddd3f27c6, // -0.93734, -0.34842 + 0xbfedf5e36a9ba59c, 0xbfd67b949cad63ca, // -0.93627, -0.35129 + 0xbfeded05f7de47da, 0xbfd6aa9d7dc77e16, // -0.93518, -0.35416 + 0xbfede4160f6d8d81, 0xbfd6d998638a0cb5, // -0.93409, -0.35703 + 0xbfeddb13b6ccc23d, 0xbfd7088530fa459e, // -0.93299, -0.3599 + 0xbfedd1fef38a915a, 0xbfd73763c9261092, // -0.93188, -0.36276 + 0xbfedc8d7cb410260, 0xbfd766340f2418f6, // -0.93077, -0.36561 + 0xbfedbf9e4395759a, 0xbfd794f5e613dfae, // -0.92964, -0.36847 + 0xbfedb6526238a09b, 0xbfd7c3a9311dcce7, // -0.92851, -0.37132 + 0xbfedacf42ce68ab9, 0xbfd7f24dd37341e3, // -0.92736, -0.37416 + 0xbfeda383a9668988, 0xbfd820e3b04eaac4, // -0.92621, -0.37701 + 0xbfed9a00dd8b3d46, 0xbfd84f6aaaf3903f, // -0.92505, -0.37985 + 0xbfed906bcf328d46, 0xbfd87de2a6aea963, // -0.92388, -0.38268 + 0xbfed86c48445a450, 0xbfd8ac4b86d5ed44, // -0.9227, -0.38552 + 0xbfed7d0b02b8ecf9, 0xbfd8daa52ec8a4af, // -0.92151, -0.38835 + 0xbfed733f508c0dff, 0xbfd908ef81ef7bd1, // -0.92032, -0.39117 + 0xbfed696173c9e68b, 0xbfd9372a63bc93d7, // -0.91911, -0.39399 + 0xbfed5f7172888a7f, 0xbfd96555b7ab948f, // -0.9179, -0.39681 + 0xbfed556f52e93eb1, 0xbfd993716141bdfe, // -0.91668, -0.39962 + 0xbfed4b5b1b187524, 0xbfd9c17d440df9f2, // -0.91545, -0.40243 + 0xbfed4134d14dc93a, 0xbfd9ef7943a8ed8a, // -0.91421, -0.40524 + 0xbfed36fc7bcbfbdc, 0xbfda1d6543b50ac0, // -0.91296, -0.40804 + 0xbfed2cb220e0ef9f, 0xbfda4b4127dea1e4, // -0.91171, -0.41084 + 0xbfed2255c6e5a4e1, 0xbfda790cd3dbf31a, // -0.91044, -0.41364 + 0xbfed17e7743e35dc, 0xbfdaa6c82b6d3fc9, // -0.90917, -0.41643 + 0xbfed0d672f59d2b9, 0xbfdad473125cdc08, // -0.90789, -0.41922 + 0xbfed02d4feb2bd92, 0xbfdb020d6c7f4009, // -0.9066, -0.422 + 0xbfecf830e8ce467b, 0xbfdb2f971db31972, // -0.9053, -0.42478 + 0xbfeced7af43cc773, 0xbfdb5d1009e15cc0, // -0.90399, -0.42756 + 0xbfece2b32799a060, 0xbfdb8a7814fd5693, // -0.90267, -0.43033 + 0xbfecd7d9898b32f6, 0xbfdbb7cf2304bd01, // -0.90135, -0.43309 + 0xbfecccee20c2de9f, 0xbfdbe51517ffc0d9, // -0.90002, -0.43586 + 0xbfecc1f0f3fcfc5c, 0xbfdc1249d8011ee7, // -0.89867, -0.43862 + 0xbfecb6e20a00da99, 0xbfdc3f6d47263129, // -0.89732, -0.44137 + 0xbfecabc169a0b901, 0xbfdc6c7f4997000a, // -0.89597, -0.44412 + 0xbfeca08f19b9c449, 0xbfdc997fc3865388, // -0.8946, -0.44687 + 0xbfec954b213411f5, 0xbfdcc66e9931c45d, // -0.89322, -0.44961 + 0xbfec89f587029c13, 0xbfdcf34baee1cd21, // -0.89184, -0.45235 + 0xbfec7e8e52233cf3, 0xbfdd2016e8e9db5b, // -0.89045, -0.45508 + 0xbfec7315899eaad7, 0xbfdd4cd02ba8609c, // -0.88905, -0.45781 + 0xbfec678b3488739b, 0xbfdd79775b86e389, // -0.88764, -0.46054 + 0xbfec5bef59fef85a, 0xbfdda60c5cfa10d8, // -0.88622, -0.46326 + 0xbfec5042012b6907, 0xbfddd28f1481cc58, // -0.8848, -0.46598 + 0xbfec44833141c004, 0xbfddfeff66a941de, // -0.88336, -0.46869 + 0xbfec38b2f180bdb1, 0xbfde2b5d3806f63b, // -0.88192, -0.4714 + 0xbfec2cd14931e3f1, 0xbfde57a86d3cd824, // -0.88047, -0.4741 + 0xbfec20de3fa971b0, 0xbfde83e0eaf85113, // -0.87901, -0.4768 + 0xbfec14d9dc465e58, 0xbfdeb00695f25620, // -0.87755, -0.47949 + 0xbfec08c426725549, 0xbfdedc1952ef78d5, // -0.87607, -0.48218 + 0xbfebfc9d25a1b147, 0xbfdf081906bff7fd, // -0.87459, -0.48487 + 0xbfebf064e15377dd, 0xbfdf3405963fd068, // -0.87309, -0.48755 + 0xbfebe41b611154c1, 0xbfdf5fdee656cda3, // -0.8716, -0.49023 + 0xbfebd7c0ac6f952a, 0xbfdf8ba4dbf89aba, // -0.87009, -0.4929 + 0xbfebcb54cb0d2327, 0xbfdfb7575c24d2de, // -0.86857, -0.49557 + 0xbfebbed7c49380ea, 0xbfdfe2f64be7120f, // -0.86705, -0.49823 + 0xbfebb249a0b6c40d, 0xbfe00740c82b82e0, // -0.86551, -0.50089 + 0xbfeba5aa673590d2, 0xbfe01cfc874c3eb7, // -0.86397, -0.50354 + 0xbfeb98fa1fd9155e, 0xbfe032ae55edbd95, // -0.86242, -0.50619 + 0xbfeb8c38d27504e9, 0xbfe0485626ae221a, // -0.86087, -0.50883 + 0xbfeb7f6686e792ea, 0xbfe05df3ec31b8b6, // -0.8593, -0.51147 + 0xbfeb728345196e3e, 0xbfe073879922ffed, // -0.85773, -0.5141 + 0xbfeb658f14fdbc47, 0xbfe089112032b08c, // -0.85615, -0.51673 + 0xbfeb5889fe921405, 0xbfe09e907417c5e1, // -0.85456, -0.51936 + 0xbfeb4b7409de7925, 0xbfe0b405878f85ec, // -0.85296, -0.52198 + 0xbfeb3e4d3ef55712, 0xbfe0c9704d5d898f, // -0.85136, -0.52459 + 0xbfeb3115a5f37bf4, 0xbfe0ded0b84bc4b5, // -0.84974, -0.5272 + 0xbfeb23cd470013b4, 0xbfe0f426bb2a8e7d, // -0.84812, -0.5298 + 0xbfeb16742a4ca2f5, 0xbfe1097248d0a956, // -0.84649, -0.5324 + 0xbfeb090a58150200, 0xbfe11eb3541b4b22, // -0.84485, -0.535 + 0xbfeafb8fd89f57b6, 0xbfe133e9cfee254e, // -0.84321, -0.53759 + 0xbfeaee04b43c1474, 0xbfe14915af336ceb, // -0.84155, -0.54017 + 0xbfeae068f345ecef, 0xbfe15e36e4dbe2bc, // -0.83989, -0.54275 + 0xbfead2bc9e21d511, 0xbfe1734d63dedb49, // -0.83822, -0.54532 + 0xbfeac4ffbd3efac8, 0xbfe188591f3a46e5, // -0.83655, -0.54789 + 0xbfeab7325916c0d4, 0xbfe19d5a09f2b9b8, // -0.83486, -0.55046 + 0xbfeaa9547a2cb98e, 0xbfe1b250171373be, // -0.83317, -0.55302 + 0xbfea9b66290ea1a3, 0xbfe1c73b39ae68c8, // -0.83147, -0.55557 + 0xbfea8d676e545ad2, 0xbfe1dc1b64dc4872, // -0.82976, -0.55812 + 0xbfea7f58529fe69d, 0xbfe1f0f08bbc861b, // -0.82805, -0.56066 + 0xbfea7138de9d60f5, 0xbfe205baa17560d6, // -0.82632, -0.5632 + 0xbfea63091b02fae2, 0xbfe21a799933eb58, // -0.82459, -0.56573 + 0xbfea54c91090f524, 0xbfe22f2d662c13e1, // -0.82285, -0.56826 + 0xbfea4678c8119ac8, 0xbfe243d5fb98ac1f, // -0.8211, -0.57078 + 0xbfea38184a593bc6, 0xbfe258734cbb7110, // -0.81935, -0.5733 + 0xbfea29a7a0462782, 0xbfe26d054cdd12df, // -0.81758, -0.57581 + 0xbfea1b26d2c0a75e, 0xbfe2818bef4d3cba, // -0.81581, -0.57831 + 0xbfea0c95eabaf937, 0xbfe2960727629ca8, // -0.81404, -0.58081 + 0xbfe9fdf4f13149de, 0xbfe2aa76e87aeb58, // -0.81225, -0.58331 + 0xbfe9ef43ef29af94, 0xbfe2bedb25faf3ea, // -0.81046, -0.5858 + 0xbfe9e082edb42472, 0xbfe2d333d34e9bb7, // -0.80866, -0.58828 + 0xbfe9d1b1f5ea80d6, 0xbfe2e780e3e8ea16, // -0.80685, -0.59076 + 0xbfe9c2d110f075c3, 0xbfe2fbc24b441015, // -0.80503, -0.59323 + 0xbfe9b3e047f38741, 0xbfe30ff7fce17035, // -0.80321, -0.5957 + 0xbfe9a4dfa42b06b2, 0xbfe32421ec49a620, // -0.80138, -0.59816 + 0xbfe995cf2ed80d22, 0xbfe338400d0c8e57, // -0.79954, -0.60062 + 0xbfe986aef1457594, 0xbfe34c5252c14de1, // -0.79769, -0.60307 + 0xbfe9777ef4c7d742, 0xbfe36058b10659f3, // -0.79584, -0.60551 + 0xbfe9683f42bd7fe1, 0xbfe374531b817f8d, // -0.79398, -0.60795 + 0xbfe958efe48e6dd7, 0xbfe3884185dfeb22, // -0.79211, -0.61038 + 0xbfe94990e3ac4a6c, 0xbfe39c23e3d63029, // -0.79023, -0.61281 + 0xbfe93a22499263fc, 0xbfe3affa292050b9, // -0.78835, -0.61523 + 0xbfe92aa41fc5a815, 0xbfe3c3c44981c517, // -0.78646, -0.61765 + 0xbfe91b166fd49da2, 0xbfe3d78238c58343, // -0.78456, -0.62006 + 0xbfe90b7943575efe, 0xbfe3eb33eabe0680, // -0.78265, -0.62246 + 0xbfe8fbcca3ef940d, 0xbfe3fed9534556d4, // -0.78074, -0.62486 + 0xbfe8ec109b486c49, 0xbfe41272663d108c, // -0.77882, -0.62725 + 0xbfe8dc45331698cc, 0xbfe425ff178e6bb1, // -0.77689, -0.62964 + 0xbfe8cc6a75184655, 0xbfe4397f5b2a4380, // -0.77495, -0.63202 + 0xbfe8bc806b151741, 0xbfe44cf325091dd6, // -0.77301, -0.63439 + 0xbfe8ac871ede1d88, 0xbfe4605a692b32a2, // -0.77106, -0.63676 + 0xbfe89c7e9a4dd4ab, 0xbfe473b51b987347, // -0.7691, -0.63912 + 0xbfe88c66e7481ba1, 0xbfe48703306091fe, // -0.76714, -0.64148 + 0xbfe87c400fba2ebf, 0xbfe49a449b9b0938, // -0.76517, -0.64383 + 0xbfe86c0a1d9aa195, 0xbfe4ad79516722f0, // -0.76319, -0.64618 + 0xbfe85bc51ae958cc, 0xbfe4c0a145ec0004, // -0.7612, -0.64851 + 0xbfe84b7111af83f9, 0xbfe4d3bc6d589f80, // -0.75921, -0.65085 + 0xbfe83b0e0bff976e, 0xbfe4e6cabbe3e5e9, // -0.75721, -0.65317 + 0xbfe82a9c13f545ff, 0xbfe4f9cc25cca486, // -0.7552, -0.65549 + 0xbfe81a1b33b57acc, 0xbfe50cc09f59a09b, // -0.75319, -0.65781 + 0xbfe8098b756e52fa, 0xbfe51fa81cd99aa6, // -0.75117, -0.66011 + 0xbfe7f8ece3571771, 0xbfe5328292a35596, // -0.74914, -0.66242 + 0xbfe7e83f87b03686, 0xbfe5454ff5159dfb, // -0.7471, -0.66471 + 0xbfe7d7836cc33db2, 0xbfe5581038975137, // -0.74506, -0.667 + 0xbfe7c6b89ce2d333, 0xbfe56ac35197649e, // -0.74301, -0.66928 + 0xbfe7b5df226aafb0, 0xbfe57d69348cec9f, // -0.74095, -0.67156 + 0xbfe7a4f707bf97d2, 0xbfe59001d5f723df, // -0.73889, -0.67383 + 0xbfe79400574f55e4, 0xbfe5a28d2a5d7250, // -0.73682, -0.67609 + 0xbfe782fb1b90b35b, 0xbfe5b50b264f7448, // -0.73474, -0.67835 + 0xbfe771e75f037261, 0xbfe5c77bbe65018c, // -0.73265, -0.6806 + 0xbfe760c52c304764, 0xbfe5d9dee73e345c, // -0.73056, -0.68285 + 0xbfe74f948da8d28d, 0xbfe5ec3495837074, // -0.72846, -0.68508 + 0xbfe73e558e079942, 0xbfe5fe7cbde56a0f, // -0.72636, -0.68732 + 0xbfe72d0837efff97, 0xbfe610b7551d2cde, // -0.72425, -0.68954 + 0xbfe71bac960e41bf, 0xbfe622e44fec22ff, // -0.72213, -0.69176 + 0xbfe70a42b3176d7a, 0xbfe63503a31c1be8, // -0.72, -0.69397 + 0xbfe6f8ca99c95b75, 0xbfe64715437f535b, // -0.71787, -0.69618 + 0xbfe6e74454eaa8ae, 0xbfe6591925f0783e, // -0.71573, -0.69838 + 0xbfe6d5afef4aafcc, 0xbfe66b0f3f52b386, // -0.71358, -0.70057 + 0xbfe6c40d73c18275, 0xbfe67cf78491af10, // -0.71143, -0.70275 + 0xbfe6b25ced2fe29c, 0xbfe68ed1eaa19c71, // -0.70927, -0.70493 + 0xbfe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // -0.70711, -0.70711 + 0xbfe68ed1eaa19c71, 0xbfe6b25ced2fe29c, // -0.70493, -0.70927 + 0xbfe67cf78491af10, 0xbfe6c40d73c18275, // -0.70275, -0.71143 + 0xbfe66b0f3f52b386, 0xbfe6d5afef4aafcc, // -0.70057, -0.71358 + 0xbfe6591925f0783e, 0xbfe6e74454eaa8ae, // -0.69838, -0.71573 + 0xbfe64715437f535b, 0xbfe6f8ca99c95b75, // -0.69618, -0.71787 + 0xbfe63503a31c1be8, 0xbfe70a42b3176d7a, // -0.69397, -0.72 + 0xbfe622e44fec22ff, 0xbfe71bac960e41bf, // -0.69176, -0.72213 + 0xbfe610b7551d2cde, 0xbfe72d0837efff97, // -0.68954, -0.72425 + 0xbfe5fe7cbde56a0f, 0xbfe73e558e079942, // -0.68732, -0.72636 + 0xbfe5ec3495837074, 0xbfe74f948da8d28d, // -0.68508, -0.72846 + 0xbfe5d9dee73e345c, 0xbfe760c52c304764, // -0.68285, -0.73056 + 0xbfe5c77bbe65018c, 0xbfe771e75f037261, // -0.6806, -0.73265 + 0xbfe5b50b264f7448, 0xbfe782fb1b90b35b, // -0.67835, -0.73474 + 0xbfe5a28d2a5d7250, 0xbfe79400574f55e4, // -0.67609, -0.73682 + 0xbfe59001d5f723df, 0xbfe7a4f707bf97d2, // -0.67383, -0.73889 + 0xbfe57d69348cec9f, 0xbfe7b5df226aafb0, // -0.67156, -0.74095 + 0xbfe56ac35197649e, 0xbfe7c6b89ce2d333, // -0.66928, -0.74301 + 0xbfe5581038975137, 0xbfe7d7836cc33db2, // -0.667, -0.74506 + 0xbfe5454ff5159dfb, 0xbfe7e83f87b03686, // -0.66471, -0.7471 + 0xbfe5328292a35596, 0xbfe7f8ece3571771, // -0.66242, -0.74914 + 0xbfe51fa81cd99aa6, 0xbfe8098b756e52fa, // -0.66011, -0.75117 + 0xbfe50cc09f59a09b, 0xbfe81a1b33b57acc, // -0.65781, -0.75319 + 0xbfe4f9cc25cca486, 0xbfe82a9c13f545ff, // -0.65549, -0.7552 + 0xbfe4e6cabbe3e5e9, 0xbfe83b0e0bff976e, // -0.65317, -0.75721 + 0xbfe4d3bc6d589f80, 0xbfe84b7111af83f9, // -0.65085, -0.75921 + 0xbfe4c0a145ec0004, 0xbfe85bc51ae958cc, // -0.64851, -0.7612 + 0xbfe4ad79516722f0, 0xbfe86c0a1d9aa195, // -0.64618, -0.76319 + 0xbfe49a449b9b0938, 0xbfe87c400fba2ebf, // -0.64383, -0.76517 + 0xbfe48703306091fe, 0xbfe88c66e7481ba1, // -0.64148, -0.76714 + 0xbfe473b51b987347, 0xbfe89c7e9a4dd4ab, // -0.63912, -0.7691 + 0xbfe4605a692b32a2, 0xbfe8ac871ede1d88, // -0.63676, -0.77106 + 0xbfe44cf325091dd6, 0xbfe8bc806b151741, // -0.63439, -0.77301 + 0xbfe4397f5b2a4380, 0xbfe8cc6a75184655, // -0.63202, -0.77495 + 0xbfe425ff178e6bb1, 0xbfe8dc45331698cc, // -0.62964, -0.77689 + 0xbfe41272663d108c, 0xbfe8ec109b486c49, // -0.62725, -0.77882 + 0xbfe3fed9534556d4, 0xbfe8fbcca3ef940d, // -0.62486, -0.78074 + 0xbfe3eb33eabe0680, 0xbfe90b7943575efe, // -0.62246, -0.78265 + 0xbfe3d78238c58343, 0xbfe91b166fd49da2, // -0.62006, -0.78456 + 0xbfe3c3c44981c517, 0xbfe92aa41fc5a815, // -0.61765, -0.78646 + 0xbfe3affa292050b9, 0xbfe93a22499263fc, // -0.61523, -0.78835 + 0xbfe39c23e3d63029, 0xbfe94990e3ac4a6c, // -0.61281, -0.79023 + 0xbfe3884185dfeb22, 0xbfe958efe48e6dd7, // -0.61038, -0.79211 + 0xbfe374531b817f8d, 0xbfe9683f42bd7fe1, // -0.60795, -0.79398 + 0xbfe36058b10659f3, 0xbfe9777ef4c7d742, // -0.60551, -0.79584 + 0xbfe34c5252c14de1, 0xbfe986aef1457594, // -0.60307, -0.79769 + 0xbfe338400d0c8e57, 0xbfe995cf2ed80d22, // -0.60062, -0.79954 + 0xbfe32421ec49a620, 0xbfe9a4dfa42b06b2, // -0.59816, -0.80138 + 0xbfe30ff7fce17035, 0xbfe9b3e047f38741, // -0.5957, -0.80321 + 0xbfe2fbc24b441015, 0xbfe9c2d110f075c3, // -0.59323, -0.80503 + 0xbfe2e780e3e8ea16, 0xbfe9d1b1f5ea80d6, // -0.59076, -0.80685 + 0xbfe2d333d34e9bb7, 0xbfe9e082edb42472, // -0.58828, -0.80866 + 0xbfe2bedb25faf3ea, 0xbfe9ef43ef29af94, // -0.5858, -0.81046 + 0xbfe2aa76e87aeb58, 0xbfe9fdf4f13149de, // -0.58331, -0.81225 + 0xbfe2960727629ca8, 0xbfea0c95eabaf937, // -0.58081, -0.81404 + 0xbfe2818bef4d3cba, 0xbfea1b26d2c0a75e, // -0.57831, -0.81581 + 0xbfe26d054cdd12df, 0xbfea29a7a0462782, // -0.57581, -0.81758 + 0xbfe258734cbb7110, 0xbfea38184a593bc6, // -0.5733, -0.81935 + 0xbfe243d5fb98ac1f, 0xbfea4678c8119ac8, // -0.57078, -0.8211 + 0xbfe22f2d662c13e1, 0xbfea54c91090f524, // -0.56826, -0.82285 + 0xbfe21a799933eb58, 0xbfea63091b02fae2, // -0.56573, -0.82459 + 0xbfe205baa17560d6, 0xbfea7138de9d60f5, // -0.5632, -0.82632 + 0xbfe1f0f08bbc861b, 0xbfea7f58529fe69d, // -0.56066, -0.82805 + 0xbfe1dc1b64dc4872, 0xbfea8d676e545ad2, // -0.55812, -0.82976 + 0xbfe1c73b39ae68c8, 0xbfea9b66290ea1a3, // -0.55557, -0.83147 + 0xbfe1b250171373be, 0xbfeaa9547a2cb98e, // -0.55302, -0.83317 + 0xbfe19d5a09f2b9b8, 0xbfeab7325916c0d4, // -0.55046, -0.83486 + 0xbfe188591f3a46e5, 0xbfeac4ffbd3efac8, // -0.54789, -0.83655 + 0xbfe1734d63dedb49, 0xbfead2bc9e21d511, // -0.54532, -0.83822 + 0xbfe15e36e4dbe2bc, 0xbfeae068f345ecef, // -0.54275, -0.83989 + 0xbfe14915af336ceb, 0xbfeaee04b43c1474, // -0.54017, -0.84155 + 0xbfe133e9cfee254e, 0xbfeafb8fd89f57b6, // -0.53759, -0.84321 + 0xbfe11eb3541b4b22, 0xbfeb090a58150200, // -0.535, -0.84485 + 0xbfe1097248d0a956, 0xbfeb16742a4ca2f5, // -0.5324, -0.84649 + 0xbfe0f426bb2a8e7d, 0xbfeb23cd470013b4, // -0.5298, -0.84812 + 0xbfe0ded0b84bc4b5, 0xbfeb3115a5f37bf4, // -0.5272, -0.84974 + 0xbfe0c9704d5d898f, 0xbfeb3e4d3ef55712, // -0.52459, -0.85136 + 0xbfe0b405878f85ec, 0xbfeb4b7409de7925, // -0.52198, -0.85296 + 0xbfe09e907417c5e1, 0xbfeb5889fe921405, // -0.51936, -0.85456 + 0xbfe089112032b08c, 0xbfeb658f14fdbc47, // -0.51673, -0.85615 + 0xbfe073879922ffed, 0xbfeb728345196e3e, // -0.5141, -0.85773 + 0xbfe05df3ec31b8b6, 0xbfeb7f6686e792ea, // -0.51147, -0.8593 + 0xbfe0485626ae221a, 0xbfeb8c38d27504e9, // -0.50883, -0.86087 + 0xbfe032ae55edbd95, 0xbfeb98fa1fd9155e, // -0.50619, -0.86242 + 0xbfe01cfc874c3eb7, 0xbfeba5aa673590d2, // -0.50354, -0.86397 + 0xbfe00740c82b82e0, 0xbfebb249a0b6c40d, // -0.50089, -0.86551 + 0xbfdfe2f64be7120f, 0xbfebbed7c49380ea, // -0.49823, -0.86705 + 0xbfdfb7575c24d2de, 0xbfebcb54cb0d2327, // -0.49557, -0.86857 + 0xbfdf8ba4dbf89aba, 0xbfebd7c0ac6f952a, // -0.4929, -0.87009 + 0xbfdf5fdee656cda3, 0xbfebe41b611154c1, // -0.49023, -0.8716 + 0xbfdf3405963fd068, 0xbfebf064e15377dd, // -0.48755, -0.87309 + 0xbfdf081906bff7fd, 0xbfebfc9d25a1b147, // -0.48487, -0.87459 + 0xbfdedc1952ef78d5, 0xbfec08c426725549, // -0.48218, -0.87607 + 0xbfdeb00695f25620, 0xbfec14d9dc465e58, // -0.47949, -0.87755 + 0xbfde83e0eaf85113, 0xbfec20de3fa971b0, // -0.4768, -0.87901 + 0xbfde57a86d3cd824, 0xbfec2cd14931e3f1, // -0.4741, -0.88047 + 0xbfde2b5d3806f63b, 0xbfec38b2f180bdb1, // -0.4714, -0.88192 + 0xbfddfeff66a941de, 0xbfec44833141c004, // -0.46869, -0.88336 + 0xbfddd28f1481cc58, 0xbfec5042012b6907, // -0.46598, -0.8848 + 0xbfdda60c5cfa10d8, 0xbfec5bef59fef85a, // -0.46326, -0.88622 + 0xbfdd79775b86e389, 0xbfec678b3488739b, // -0.46054, -0.88764 + 0xbfdd4cd02ba8609c, 0xbfec7315899eaad7, // -0.45781, -0.88905 + 0xbfdd2016e8e9db5b, 0xbfec7e8e52233cf3, // -0.45508, -0.89045 + 0xbfdcf34baee1cd21, 0xbfec89f587029c13, // -0.45235, -0.89184 + 0xbfdcc66e9931c45d, 0xbfec954b213411f5, // -0.44961, -0.89322 + 0xbfdc997fc3865388, 0xbfeca08f19b9c449, // -0.44687, -0.8946 + 0xbfdc6c7f4997000a, 0xbfecabc169a0b901, // -0.44412, -0.89597 + 0xbfdc3f6d47263129, 0xbfecb6e20a00da99, // -0.44137, -0.89732 + 0xbfdc1249d8011ee7, 0xbfecc1f0f3fcfc5c, // -0.43862, -0.89867 + 0xbfdbe51517ffc0d9, 0xbfecccee20c2de9f, // -0.43586, -0.90002 + 0xbfdbb7cf2304bd01, 0xbfecd7d9898b32f6, // -0.43309, -0.90135 + 0xbfdb8a7814fd5693, 0xbfece2b32799a060, // -0.43033, -0.90267 + 0xbfdb5d1009e15cc0, 0xbfeced7af43cc773, // -0.42756, -0.90399 + 0xbfdb2f971db31972, 0xbfecf830e8ce467b, // -0.42478, -0.9053 + 0xbfdb020d6c7f4009, 0xbfed02d4feb2bd92, // -0.422, -0.9066 + 0xbfdad473125cdc08, 0xbfed0d672f59d2b9, // -0.41922, -0.90789 + 0xbfdaa6c82b6d3fc9, 0xbfed17e7743e35dc, // -0.41643, -0.90917 + 0xbfda790cd3dbf31a, 0xbfed2255c6e5a4e1, // -0.41364, -0.91044 + 0xbfda4b4127dea1e4, 0xbfed2cb220e0ef9f, // -0.41084, -0.91171 + 0xbfda1d6543b50ac0, 0xbfed36fc7bcbfbdc, // -0.40804, -0.91296 + 0xbfd9ef7943a8ed8a, 0xbfed4134d14dc93a, // -0.40524, -0.91421 + 0xbfd9c17d440df9f2, 0xbfed4b5b1b187524, // -0.40243, -0.91545 + 0xbfd993716141bdfe, 0xbfed556f52e93eb1, // -0.39962, -0.91668 + 0xbfd96555b7ab948f, 0xbfed5f7172888a7f, // -0.39681, -0.9179 + 0xbfd9372a63bc93d7, 0xbfed696173c9e68b, // -0.39399, -0.91911 + 0xbfd908ef81ef7bd1, 0xbfed733f508c0dff, // -0.39117, -0.92032 + 0xbfd8daa52ec8a4af, 0xbfed7d0b02b8ecf9, // -0.38835, -0.92151 + 0xbfd8ac4b86d5ed44, 0xbfed86c48445a450, // -0.38552, -0.9227 + 0xbfd87de2a6aea963, 0xbfed906bcf328d46, // -0.38268, -0.92388 + 0xbfd84f6aaaf3903f, 0xbfed9a00dd8b3d46, // -0.37985, -0.92505 + 0xbfd820e3b04eaac4, 0xbfeda383a9668988, // -0.37701, -0.92621 + 0xbfd7f24dd37341e3, 0xbfedacf42ce68ab9, // -0.37416, -0.92736 + 0xbfd7c3a9311dcce7, 0xbfedb6526238a09b, // -0.37132, -0.92851 + 0xbfd794f5e613dfae, 0xbfedbf9e4395759a, // -0.36847, -0.92964 + 0xbfd766340f2418f6, 0xbfedc8d7cb410260, // -0.36561, -0.93077 + 0xbfd73763c9261092, 0xbfedd1fef38a915a, // -0.36276, -0.93188 + 0xbfd7088530fa459e, 0xbfeddb13b6ccc23d, // -0.3599, -0.93299 + 0xbfd6d998638a0cb5, 0xbfede4160f6d8d81, // -0.35703, -0.93409 + 0xbfd6aa9d7dc77e16, 0xbfeded05f7de47da, // -0.35416, -0.93518 + 0xbfd67b949cad63ca, 0xbfedf5e36a9ba59c, // -0.35129, -0.93627 + 0xbfd64c7ddd3f27c6, 0xbfedfeae622dbe2b, // -0.34842, -0.93734 + 0xbfd61d595c88c203, 0xbfee0766d9280f54, // -0.34554, -0.9384 + 0xbfd5ee27379ea693, 0xbfee100cca2980ac, // -0.34266, -0.93946 + 0xbfd5bee78b9db3b6, 0xbfee18a02fdc66d9, // -0.33978, -0.94051 + 0xbfd58f9a75ab1fdd, 0xbfee212104f686e5, // -0.33689, -0.94154 + 0xbfd5604012f467b4, 0xbfee298f4439197a, // -0.334, -0.94257 + 0xbfd530d880af3c24, 0xbfee31eae870ce25, // -0.33111, -0.94359 + 0xbfd50163dc197047, 0xbfee3a33ec75ce85, // -0.32821, -0.9446 + 0xbfd4d1e24278e76a, 0xbfee426a4b2bc17e, // -0.32531, -0.94561 + 0xbfd4a253d11b82f3, 0xbfee4a8dff81ce5e, // -0.32241, -0.9466 + 0xbfd472b8a5571054, 0xbfee529f04729ffc, // -0.3195, -0.94759 + 0xbfd44310dc8936f0, 0xbfee5a9d550467d3, // -0.31659, -0.94856 + 0xbfd4135c94176602, 0xbfee6288ec48e112, // -0.31368, -0.94953 + 0xbfd3e39be96ec271, 0xbfee6a61c55d53a7, // -0.31077, -0.95049 + 0xbfd3b3cefa0414b7, 0xbfee7227db6a9744, // -0.30785, -0.95144 + 0xbfd383f5e353b6aa, 0xbfee79db29a5165a, // -0.30493, -0.95238 + 0xbfd35410c2e18152, 0xbfee817bab4cd10d, // -0.30201, -0.95331 + 0xbfd3241fb638baaf, 0xbfee89095bad6025, // -0.29908, -0.95423 + 0xbfd2f422daec0386, 0xbfee9084361df7f3, // -0.29615, -0.95514 + 0xbfd2c41a4e954520, 0xbfee97ec36016b30, // -0.29322, -0.95605 + 0xbfd294062ed59f05, 0xbfee9f4156c62dda, // -0.29028, -0.95694 + 0xbfd263e6995554ba, 0xbfeea68393e65800, // -0.28735, -0.95783 + 0xbfd233bbabc3bb72, 0xbfeeadb2e8e7a88e, // -0.28441, -0.9587 + 0xbfd2038583d727bd, 0xbfeeb4cf515b8811, // -0.28146, -0.95957 + 0xbfd1d3443f4cdb3d, 0xbfeebbd8c8df0b74, // -0.27852, -0.96043 + 0xbfd1a2f7fbe8f243, 0xbfeec2cf4b1af6b2, // -0.27557, -0.96128 + 0xbfd172a0d7765177, 0xbfeec9b2d3c3bf84, // -0.27262, -0.96212 + 0xbfd1423eefc69378, 0xbfeed0835e999009, // -0.26967, -0.96295 + 0xbfd111d262b1f677, 0xbfeed740e7684963, // -0.26671, -0.96378 + 0xbfd0e15b4e1749cd, 0xbfeeddeb6a078651, // -0.26375, -0.96459 + 0xbfd0b0d9cfdbdb90, 0xbfeee482e25a9dbc, // -0.26079, -0.96539 + 0xbfd0804e05eb661e, 0xbfeeeb074c50a544, // -0.25783, -0.96619 + 0xbfd04fb80e37fdae, 0xbfeef178a3e473c2, // -0.25487, -0.96698 + 0xbfd01f1806b9fdd2, 0xbfeef7d6e51ca3c0, // -0.2519, -0.96775 + 0xbfcfdcdc1adfedf8, 0xbfeefe220c0b95ec, // -0.24893, -0.96852 + 0xbfcf7b7480bd3801, 0xbfef045a14cf738c, // -0.24596, -0.96928 + 0xbfcf19f97b215f1a, 0xbfef0a7efb9230d7, // -0.24298, -0.97003 + 0xbfceb86b462de348, 0xbfef1090bc898f5f, // -0.24, -0.97077 + 0xbfce56ca1e101a1b, 0xbfef168f53f7205d, // -0.23702, -0.9715 + 0xbfcdf5163f01099a, 0xbfef1c7abe284708, // -0.23404, -0.97223 + 0xbfcd934fe5454311, 0xbfef2252f7763ada, // -0.23106, -0.97294 + 0xbfcd31774d2cbdee, 0xbfef2817fc4609ce, // -0.22807, -0.97364 + 0xbfcccf8cb312b286, 0xbfef2dc9c9089a9d, // -0.22508, -0.97434 + 0xbfcc6d90535d74dc, 0xbfef33685a3aaef0, // -0.22209, -0.97503 + 0xbfcc0b826a7e4f63, 0xbfef38f3ac64e589, // -0.2191, -0.9757 + 0xbfcba96334f15dad, 0xbfef3e6bbc1bbc65, // -0.21611, -0.97637 + 0xbfcb4732ef3d6722, 0xbfef43d085ff92dd, // -0.21311, -0.97703 + 0xbfcae4f1d5f3b9ab, 0xbfef492206bcabb4, // -0.21011, -0.97768 + 0xbfca82a025b00451, 0xbfef4e603b0b2f2d, // -0.20711, -0.97832 + 0xbfca203e1b1831da, 0xbfef538b1faf2d07, // -0.20411, -0.97895 + 0xbfc9bdcbf2dc4366, 0xbfef58a2b1789e84, // -0.2011, -0.97957 + 0xbfc95b49e9b62af9, 0xbfef5da6ed43685d, // -0.1981, -0.98018 + 0xbfc8f8b83c69a60a, 0xbfef6297cff75cb0, // -0.19509, -0.98079 + 0xbfc8961727c41804, 0xbfef677556883cee, // -0.19208, -0.98138 + 0xbfc83366e89c64c5, 0xbfef6c3f7df5bbb7, // -0.18907, -0.98196 + 0xbfc7d0a7bbd2cb1b, 0xbfef70f6434b7eb7, // -0.18606, -0.98254 + 0xbfc76dd9de50bf31, 0xbfef7599a3a12077, // -0.18304, -0.98311 + 0xbfc70afd8d08c4ff, 0xbfef7a299c1a322a, // -0.18002, -0.98366 + 0xbfc6a81304f64ab2, 0xbfef7ea629e63d6e, // -0.177, -0.98421 + 0xbfc6451a831d830d, 0xbfef830f4a40c60c, // -0.17398, -0.98475 + 0xbfc5e214448b3fc6, 0xbfef8764fa714ba9, // -0.17096, -0.98528 + 0xbfc57f008654cbde, 0xbfef8ba737cb4b78, // -0.16794, -0.9858 + 0xbfc51bdf8597c5f2, 0xbfef8fd5ffae41db, // -0.16491, -0.98631 + 0xbfc4b8b17f79fa88, 0xbfef93f14f85ac08, // -0.16189, -0.98681 + 0xbfc45576b1293e5a, 0xbfef97f924c9099b, // -0.15886, -0.9873 + 0xbfc3f22f57db4893, 0xbfef9bed7cfbde29, // -0.15583, -0.98778 + 0xbfc38edbb0cd8d14, 0xbfef9fce55adb2c8, // -0.1528, -0.98826 + 0xbfc32b7bf94516a7, 0xbfefa39bac7a1791, // -0.14976, -0.98872 + 0xbfc2c8106e8e613a, 0xbfefa7557f08a517, // -0.14673, -0.98918 + 0xbfc264994dfd340a, 0xbfefaafbcb0cfddc, // -0.1437, -0.98962 + 0xbfc20116d4ec7bce, 0xbfefae8e8e46cfbb, // -0.14066, -0.99006 + 0xbfc19d8940be24e7, 0xbfefb20dc681d54d, // -0.13762, -0.99049 + 0xbfc139f0cedaf576, 0xbfefb5797195d741, // -0.13458, -0.9909 + 0xbfc0d64dbcb26786, 0xbfefb8d18d66adb7, // -0.13154, -0.99131 + 0xbfc072a047ba831d, 0xbfefbc1617e44186, // -0.1285, -0.99171 + 0xbfc00ee8ad6fb85b, 0xbfefbf470f0a8d88, // -0.12545, -0.9921 + 0xbfbf564e56a9730e, 0xbfefc26470e19fd3, // -0.12241, -0.99248 + 0xbfbe8eb7fde4aa3e, 0xbfefc56e3b7d9af6, // -0.11937, -0.99285 + 0xbfbdc70ecbae9fc8, 0xbfefc8646cfeb721, // -0.11632, -0.99321 + 0xbfbcff533b307dc1, 0xbfefcb4703914354, // -0.11327, -0.99356 + 0xbfbc3785c79ec2d5, 0xbfefce15fd6da67b, // -0.11022, -0.99391 + 0xbfbb6fa6ec38f64c, 0xbfefd0d158d86087, // -0.10717, -0.99424 + 0xbfbaa7b724495c04, 0xbfefd37914220b84, // -0.10412, -0.99456 + 0xbfb9dfb6eb24a85c, 0xbfefd60d2da75c9e, // -0.10107, -0.99488 + 0xbfb917a6bc29b42c, 0xbfefd88da3d12526, // -0.098017, -0.99518 + 0xbfb84f8712c130a0, 0xbfefdafa7514538c, // -0.094963, -0.99548 + 0xbfb787586a5d5b21, 0xbfefdd539ff1f456, // -0.091909, -0.99577 + 0xbfb6bf1b3e79b129, 0xbfefdf9922f73307, // -0.088854, -0.99604 + 0xbfb5f6d00a9aa419, 0xbfefe1cafcbd5b09, // -0.085797, -0.99631 + 0xbfb52e774a4d4d0a, 0xbfefe3e92be9d886, // -0.08274, -0.99657 + 0xbfb4661179272096, 0xbfefe5f3af2e3940, // -0.079682, -0.99682 + 0xbfb39d9f12c5a299, 0xbfefe7ea85482d60, // -0.076624, -0.99706 + 0xbfb2d52092ce19f6, 0xbfefe9cdad01883a, // -0.073565, -0.99729 + 0xbfb20c9674ed444c, 0xbfefeb9d2530410f, // -0.070505, -0.99751 + 0xbfb1440134d709b2, 0xbfefed58ecb673c4, // -0.067444, -0.99772 + 0xbfb07b614e463064, 0xbfefef0102826191, // -0.064383, -0.99793 + 0xbfaf656e79f820e0, 0xbfeff095658e71ad, // -0.061321, -0.99812 + 0xbfadd406f9808ec8, 0xbfeff21614e131ed, // -0.058258, -0.9983 + 0xbfac428d12c0d7e3, 0xbfeff3830f8d575c, // -0.055195, -0.99848 + 0xbfaab101bd5f8317, 0xbfeff4dc54b1bed3, // -0.052132, -0.99864 + 0xbfa91f65f10dd814, 0xbfeff621e3796d7e, // -0.049068, -0.9988 + 0xbfa78dbaa5874685, 0xbfeff753bb1b9164, // -0.046003, -0.99894 + 0xbfa5fc00d290cd43, 0xbfeff871dadb81df, // -0.042938, -0.99908 + 0xbfa46a396ff86179, 0xbfeff97c4208c014, // -0.039873, -0.9992 + 0xbfa2d865759455cd, 0xbfeffa72effef75d, // -0.036807, -0.99932 + 0xbfa14685db42c17e, 0xbfeffb55e425fdae, // -0.033741, -0.99943 + 0xbf9f693731d1cf01, 0xbfeffc251df1d3f8, // -0.030675, -0.99953 + 0xbf9c454f4ce53b1c, 0xbfeffce09ce2a679, // -0.027608, -0.99962 + 0xbf992155f7a3667e, 0xbfeffd886084cd0d, // -0.024541, -0.9997 + 0xbf95fd4d21fab226, 0xbfeffe1c6870cb77, // -0.021474, -0.99977 + 0xbf92d936bbe30efd, 0xbfeffe9cb44b51a1, // -0.018407, -0.99983 + 0xbf8f6a296ab997ca, 0xbfefff0943c53bd1, // -0.015339, -0.99988 + 0xbf8921d1fcdec784, 0xbfefff62169b92db, // -0.012272, -0.99992 + 0xbf82d96b0e509703, 0xbfefffa72c978c4f, //-0.0092038, -0.99996 + 0xbf7921f0fe670071, 0xbfefffd8858e8a92, //-0.0061359, -0.99998 + 0xbf6921f8becca4ba, 0xbfeffff621621d02, // -0.003068, -1 + 0x0000000000000000, 0xbff0000000000000, // 0, -1 + 0x3f6921f8becca4ba, 0xbfeffff621621d02, // 0.003068, -1 + 0x3f7921f0fe670071, 0xbfefffd8858e8a92, // 0.0061359, -0.99998 + 0x3f82d96b0e509703, 0xbfefffa72c978c4f, // 0.0092038, -0.99996 + 0x3f8921d1fcdec784, 0xbfefff62169b92db, // 0.012272, -0.99992 + 0x3f8f6a296ab997ca, 0xbfefff0943c53bd1, // 0.015339, -0.99988 + 0x3f92d936bbe30efd, 0xbfeffe9cb44b51a1, // 0.018407, -0.99983 + 0x3f95fd4d21fab226, 0xbfeffe1c6870cb77, // 0.021474, -0.99977 + 0x3f992155f7a3667e, 0xbfeffd886084cd0d, // 0.024541, -0.9997 + 0x3f9c454f4ce53b1c, 0xbfeffce09ce2a679, // 0.027608, -0.99962 + 0x3f9f693731d1cf01, 0xbfeffc251df1d3f8, // 0.030675, -0.99953 + 0x3fa14685db42c17e, 0xbfeffb55e425fdae, // 0.033741, -0.99943 + 0x3fa2d865759455cd, 0xbfeffa72effef75d, // 0.036807, -0.99932 + 0x3fa46a396ff86179, 0xbfeff97c4208c014, // 0.039873, -0.9992 + 0x3fa5fc00d290cd43, 0xbfeff871dadb81df, // 0.042938, -0.99908 + 0x3fa78dbaa5874685, 0xbfeff753bb1b9164, // 0.046003, -0.99894 + 0x3fa91f65f10dd814, 0xbfeff621e3796d7e, // 0.049068, -0.9988 + 0x3faab101bd5f8317, 0xbfeff4dc54b1bed3, // 0.052132, -0.99864 + 0x3fac428d12c0d7e3, 0xbfeff3830f8d575c, // 0.055195, -0.99848 + 0x3fadd406f9808ec8, 0xbfeff21614e131ed, // 0.058258, -0.9983 + 0x3faf656e79f820e0, 0xbfeff095658e71ad, // 0.061321, -0.99812 + 0x3fb07b614e463064, 0xbfefef0102826191, // 0.064383, -0.99793 + 0x3fb1440134d709b2, 0xbfefed58ecb673c4, // 0.067444, -0.99772 + 0x3fb20c9674ed444c, 0xbfefeb9d2530410f, // 0.070505, -0.99751 + 0x3fb2d52092ce19f6, 0xbfefe9cdad01883a, // 0.073565, -0.99729 + 0x3fb39d9f12c5a299, 0xbfefe7ea85482d60, // 0.076624, -0.99706 + 0x3fb4661179272096, 0xbfefe5f3af2e3940, // 0.079682, -0.99682 + 0x3fb52e774a4d4d0a, 0xbfefe3e92be9d886, // 0.08274, -0.99657 + 0x3fb5f6d00a9aa419, 0xbfefe1cafcbd5b09, // 0.085797, -0.99631 + 0x3fb6bf1b3e79b129, 0xbfefdf9922f73307, // 0.088854, -0.99604 + 0x3fb787586a5d5b21, 0xbfefdd539ff1f456, // 0.091909, -0.99577 + 0x3fb84f8712c130a0, 0xbfefdafa7514538c, // 0.094963, -0.99548 + 0x3fb917a6bc29b42c, 0xbfefd88da3d12526, // 0.098017, -0.99518 + 0x3fb9dfb6eb24a85c, 0xbfefd60d2da75c9e, // 0.10107, -0.99488 + 0x3fbaa7b724495c04, 0xbfefd37914220b84, // 0.10412, -0.99456 + 0x3fbb6fa6ec38f64c, 0xbfefd0d158d86087, // 0.10717, -0.99424 + 0x3fbc3785c79ec2d5, 0xbfefce15fd6da67b, // 0.11022, -0.99391 + 0x3fbcff533b307dc1, 0xbfefcb4703914354, // 0.11327, -0.99356 + 0x3fbdc70ecbae9fc8, 0xbfefc8646cfeb721, // 0.11632, -0.99321 + 0x3fbe8eb7fde4aa3e, 0xbfefc56e3b7d9af6, // 0.11937, -0.99285 + 0x3fbf564e56a9730e, 0xbfefc26470e19fd3, // 0.12241, -0.99248 + 0x3fc00ee8ad6fb85b, 0xbfefbf470f0a8d88, // 0.12545, -0.9921 + 0x3fc072a047ba831d, 0xbfefbc1617e44186, // 0.1285, -0.99171 + 0x3fc0d64dbcb26786, 0xbfefb8d18d66adb7, // 0.13154, -0.99131 + 0x3fc139f0cedaf576, 0xbfefb5797195d741, // 0.13458, -0.9909 + 0x3fc19d8940be24e7, 0xbfefb20dc681d54d, // 0.13762, -0.99049 + 0x3fc20116d4ec7bce, 0xbfefae8e8e46cfbb, // 0.14066, -0.99006 + 0x3fc264994dfd340a, 0xbfefaafbcb0cfddc, // 0.1437, -0.98962 + 0x3fc2c8106e8e613a, 0xbfefa7557f08a517, // 0.14673, -0.98918 + 0x3fc32b7bf94516a7, 0xbfefa39bac7a1791, // 0.14976, -0.98872 + 0x3fc38edbb0cd8d14, 0xbfef9fce55adb2c8, // 0.1528, -0.98826 + 0x3fc3f22f57db4893, 0xbfef9bed7cfbde29, // 0.15583, -0.98778 + 0x3fc45576b1293e5a, 0xbfef97f924c9099b, // 0.15886, -0.9873 + 0x3fc4b8b17f79fa88, 0xbfef93f14f85ac08, // 0.16189, -0.98681 + 0x3fc51bdf8597c5f2, 0xbfef8fd5ffae41db, // 0.16491, -0.98631 + 0x3fc57f008654cbde, 0xbfef8ba737cb4b78, // 0.16794, -0.9858 + 0x3fc5e214448b3fc6, 0xbfef8764fa714ba9, // 0.17096, -0.98528 + 0x3fc6451a831d830d, 0xbfef830f4a40c60c, // 0.17398, -0.98475 + 0x3fc6a81304f64ab2, 0xbfef7ea629e63d6e, // 0.177, -0.98421 + 0x3fc70afd8d08c4ff, 0xbfef7a299c1a322a, // 0.18002, -0.98366 + 0x3fc76dd9de50bf31, 0xbfef7599a3a12077, // 0.18304, -0.98311 + 0x3fc7d0a7bbd2cb1b, 0xbfef70f6434b7eb7, // 0.18606, -0.98254 + 0x3fc83366e89c64c5, 0xbfef6c3f7df5bbb7, // 0.18907, -0.98196 + 0x3fc8961727c41804, 0xbfef677556883cee, // 0.19208, -0.98138 + 0x3fc8f8b83c69a60a, 0xbfef6297cff75cb0, // 0.19509, -0.98079 + 0x3fc95b49e9b62af9, 0xbfef5da6ed43685d, // 0.1981, -0.98018 + 0x3fc9bdcbf2dc4366, 0xbfef58a2b1789e84, // 0.2011, -0.97957 + 0x3fca203e1b1831da, 0xbfef538b1faf2d07, // 0.20411, -0.97895 + 0x3fca82a025b00451, 0xbfef4e603b0b2f2d, // 0.20711, -0.97832 + 0x3fcae4f1d5f3b9ab, 0xbfef492206bcabb4, // 0.21011, -0.97768 + 0x3fcb4732ef3d6722, 0xbfef43d085ff92dd, // 0.21311, -0.97703 + 0x3fcba96334f15dad, 0xbfef3e6bbc1bbc65, // 0.21611, -0.97637 + 0x3fcc0b826a7e4f63, 0xbfef38f3ac64e589, // 0.2191, -0.9757 + 0x3fcc6d90535d74dc, 0xbfef33685a3aaef0, // 0.22209, -0.97503 + 0x3fcccf8cb312b286, 0xbfef2dc9c9089a9d, // 0.22508, -0.97434 + 0x3fcd31774d2cbdee, 0xbfef2817fc4609ce, // 0.22807, -0.97364 + 0x3fcd934fe5454311, 0xbfef2252f7763ada, // 0.23106, -0.97294 + 0x3fcdf5163f01099a, 0xbfef1c7abe284708, // 0.23404, -0.97223 + 0x3fce56ca1e101a1b, 0xbfef168f53f7205d, // 0.23702, -0.9715 + 0x3fceb86b462de348, 0xbfef1090bc898f5f, // 0.24, -0.97077 + 0x3fcf19f97b215f1a, 0xbfef0a7efb9230d7, // 0.24298, -0.97003 + 0x3fcf7b7480bd3801, 0xbfef045a14cf738c, // 0.24596, -0.96928 + 0x3fcfdcdc1adfedf8, 0xbfeefe220c0b95ec, // 0.24893, -0.96852 + 0x3fd01f1806b9fdd2, 0xbfeef7d6e51ca3c0, // 0.2519, -0.96775 + 0x3fd04fb80e37fdae, 0xbfeef178a3e473c2, // 0.25487, -0.96698 + 0x3fd0804e05eb661e, 0xbfeeeb074c50a544, // 0.25783, -0.96619 + 0x3fd0b0d9cfdbdb90, 0xbfeee482e25a9dbc, // 0.26079, -0.96539 + 0x3fd0e15b4e1749cd, 0xbfeeddeb6a078651, // 0.26375, -0.96459 + 0x3fd111d262b1f677, 0xbfeed740e7684963, // 0.26671, -0.96378 + 0x3fd1423eefc69378, 0xbfeed0835e999009, // 0.26967, -0.96295 + 0x3fd172a0d7765177, 0xbfeec9b2d3c3bf84, // 0.27262, -0.96212 + 0x3fd1a2f7fbe8f243, 0xbfeec2cf4b1af6b2, // 0.27557, -0.96128 + 0x3fd1d3443f4cdb3d, 0xbfeebbd8c8df0b74, // 0.27852, -0.96043 + 0x3fd2038583d727bd, 0xbfeeb4cf515b8811, // 0.28146, -0.95957 + 0x3fd233bbabc3bb72, 0xbfeeadb2e8e7a88e, // 0.28441, -0.9587 + 0x3fd263e6995554ba, 0xbfeea68393e65800, // 0.28735, -0.95783 + 0x3fd294062ed59f05, 0xbfee9f4156c62dda, // 0.29028, -0.95694 + 0x3fd2c41a4e954520, 0xbfee97ec36016b30, // 0.29322, -0.95605 + 0x3fd2f422daec0386, 0xbfee9084361df7f3, // 0.29615, -0.95514 + 0x3fd3241fb638baaf, 0xbfee89095bad6025, // 0.29908, -0.95423 + 0x3fd35410c2e18152, 0xbfee817bab4cd10d, // 0.30201, -0.95331 + 0x3fd383f5e353b6aa, 0xbfee79db29a5165a, // 0.30493, -0.95238 + 0x3fd3b3cefa0414b7, 0xbfee7227db6a9744, // 0.30785, -0.95144 + 0x3fd3e39be96ec271, 0xbfee6a61c55d53a7, // 0.31077, -0.95049 + 0x3fd4135c94176602, 0xbfee6288ec48e112, // 0.31368, -0.94953 + 0x3fd44310dc8936f0, 0xbfee5a9d550467d3, // 0.31659, -0.94856 + 0x3fd472b8a5571054, 0xbfee529f04729ffc, // 0.3195, -0.94759 + 0x3fd4a253d11b82f3, 0xbfee4a8dff81ce5e, // 0.32241, -0.9466 + 0x3fd4d1e24278e76a, 0xbfee426a4b2bc17e, // 0.32531, -0.94561 + 0x3fd50163dc197047, 0xbfee3a33ec75ce85, // 0.32821, -0.9446 + 0x3fd530d880af3c24, 0xbfee31eae870ce25, // 0.33111, -0.94359 + 0x3fd5604012f467b4, 0xbfee298f4439197a, // 0.334, -0.94257 + 0x3fd58f9a75ab1fdd, 0xbfee212104f686e5, // 0.33689, -0.94154 + 0x3fd5bee78b9db3b6, 0xbfee18a02fdc66d9, // 0.33978, -0.94051 + 0x3fd5ee27379ea693, 0xbfee100cca2980ac, // 0.34266, -0.93946 + 0x3fd61d595c88c203, 0xbfee0766d9280f54, // 0.34554, -0.9384 + 0x3fd64c7ddd3f27c6, 0xbfedfeae622dbe2b, // 0.34842, -0.93734 + 0x3fd67b949cad63ca, 0xbfedf5e36a9ba59c, // 0.35129, -0.93627 + 0x3fd6aa9d7dc77e16, 0xbfeded05f7de47da, // 0.35416, -0.93518 + 0x3fd6d998638a0cb5, 0xbfede4160f6d8d81, // 0.35703, -0.93409 + 0x3fd7088530fa459e, 0xbfeddb13b6ccc23d, // 0.3599, -0.93299 + 0x3fd73763c9261092, 0xbfedd1fef38a915a, // 0.36276, -0.93188 + 0x3fd766340f2418f6, 0xbfedc8d7cb410260, // 0.36561, -0.93077 + 0x3fd794f5e613dfae, 0xbfedbf9e4395759a, // 0.36847, -0.92964 + 0x3fd7c3a9311dcce7, 0xbfedb6526238a09b, // 0.37132, -0.92851 + 0x3fd7f24dd37341e3, 0xbfedacf42ce68ab9, // 0.37416, -0.92736 + 0x3fd820e3b04eaac4, 0xbfeda383a9668988, // 0.37701, -0.92621 + 0x3fd84f6aaaf3903f, 0xbfed9a00dd8b3d46, // 0.37985, -0.92505 + 0x3fd87de2a6aea963, 0xbfed906bcf328d46, // 0.38268, -0.92388 + 0x3fd8ac4b86d5ed44, 0xbfed86c48445a450, // 0.38552, -0.9227 + 0x3fd8daa52ec8a4af, 0xbfed7d0b02b8ecf9, // 0.38835, -0.92151 + 0x3fd908ef81ef7bd1, 0xbfed733f508c0dff, // 0.39117, -0.92032 + 0x3fd9372a63bc93d7, 0xbfed696173c9e68b, // 0.39399, -0.91911 + 0x3fd96555b7ab948f, 0xbfed5f7172888a7f, // 0.39681, -0.9179 + 0x3fd993716141bdfe, 0xbfed556f52e93eb1, // 0.39962, -0.91668 + 0x3fd9c17d440df9f2, 0xbfed4b5b1b187524, // 0.40243, -0.91545 + 0x3fd9ef7943a8ed8a, 0xbfed4134d14dc93a, // 0.40524, -0.91421 + 0x3fda1d6543b50ac0, 0xbfed36fc7bcbfbdc, // 0.40804, -0.91296 + 0x3fda4b4127dea1e4, 0xbfed2cb220e0ef9f, // 0.41084, -0.91171 + 0x3fda790cd3dbf31a, 0xbfed2255c6e5a4e1, // 0.41364, -0.91044 + 0x3fdaa6c82b6d3fc9, 0xbfed17e7743e35dc, // 0.41643, -0.90917 + 0x3fdad473125cdc08, 0xbfed0d672f59d2b9, // 0.41922, -0.90789 + 0x3fdb020d6c7f4009, 0xbfed02d4feb2bd92, // 0.422, -0.9066 + 0x3fdb2f971db31972, 0xbfecf830e8ce467b, // 0.42478, -0.9053 + 0x3fdb5d1009e15cc0, 0xbfeced7af43cc773, // 0.42756, -0.90399 + 0x3fdb8a7814fd5693, 0xbfece2b32799a060, // 0.43033, -0.90267 + 0x3fdbb7cf2304bd01, 0xbfecd7d9898b32f6, // 0.43309, -0.90135 + 0x3fdbe51517ffc0d9, 0xbfecccee20c2de9f, // 0.43586, -0.90002 + 0x3fdc1249d8011ee7, 0xbfecc1f0f3fcfc5c, // 0.43862, -0.89867 + 0x3fdc3f6d47263129, 0xbfecb6e20a00da99, // 0.44137, -0.89732 + 0x3fdc6c7f4997000a, 0xbfecabc169a0b901, // 0.44412, -0.89597 + 0x3fdc997fc3865388, 0xbfeca08f19b9c449, // 0.44687, -0.8946 + 0x3fdcc66e9931c45d, 0xbfec954b213411f5, // 0.44961, -0.89322 + 0x3fdcf34baee1cd21, 0xbfec89f587029c13, // 0.45235, -0.89184 + 0x3fdd2016e8e9db5b, 0xbfec7e8e52233cf3, // 0.45508, -0.89045 + 0x3fdd4cd02ba8609c, 0xbfec7315899eaad7, // 0.45781, -0.88905 + 0x3fdd79775b86e389, 0xbfec678b3488739b, // 0.46054, -0.88764 + 0x3fdda60c5cfa10d8, 0xbfec5bef59fef85a, // 0.46326, -0.88622 + 0x3fddd28f1481cc58, 0xbfec5042012b6907, // 0.46598, -0.8848 + 0x3fddfeff66a941de, 0xbfec44833141c004, // 0.46869, -0.88336 + 0x3fde2b5d3806f63b, 0xbfec38b2f180bdb1, // 0.4714, -0.88192 + 0x3fde57a86d3cd824, 0xbfec2cd14931e3f1, // 0.4741, -0.88047 + 0x3fde83e0eaf85113, 0xbfec20de3fa971b0, // 0.4768, -0.87901 + 0x3fdeb00695f25620, 0xbfec14d9dc465e58, // 0.47949, -0.87755 + 0x3fdedc1952ef78d5, 0xbfec08c426725549, // 0.48218, -0.87607 + 0x3fdf081906bff7fd, 0xbfebfc9d25a1b147, // 0.48487, -0.87459 + 0x3fdf3405963fd068, 0xbfebf064e15377dd, // 0.48755, -0.87309 + 0x3fdf5fdee656cda3, 0xbfebe41b611154c1, // 0.49023, -0.8716 + 0x3fdf8ba4dbf89aba, 0xbfebd7c0ac6f952a, // 0.4929, -0.87009 + 0x3fdfb7575c24d2de, 0xbfebcb54cb0d2327, // 0.49557, -0.86857 + 0x3fdfe2f64be7120f, 0xbfebbed7c49380ea, // 0.49823, -0.86705 + 0x3fe00740c82b82e0, 0xbfebb249a0b6c40d, // 0.50089, -0.86551 + 0x3fe01cfc874c3eb7, 0xbfeba5aa673590d2, // 0.50354, -0.86397 + 0x3fe032ae55edbd95, 0xbfeb98fa1fd9155e, // 0.50619, -0.86242 + 0x3fe0485626ae221a, 0xbfeb8c38d27504e9, // 0.50883, -0.86087 + 0x3fe05df3ec31b8b6, 0xbfeb7f6686e792ea, // 0.51147, -0.8593 + 0x3fe073879922ffed, 0xbfeb728345196e3e, // 0.5141, -0.85773 + 0x3fe089112032b08c, 0xbfeb658f14fdbc47, // 0.51673, -0.85615 + 0x3fe09e907417c5e1, 0xbfeb5889fe921405, // 0.51936, -0.85456 + 0x3fe0b405878f85ec, 0xbfeb4b7409de7925, // 0.52198, -0.85296 + 0x3fe0c9704d5d898f, 0xbfeb3e4d3ef55712, // 0.52459, -0.85136 + 0x3fe0ded0b84bc4b5, 0xbfeb3115a5f37bf4, // 0.5272, -0.84974 + 0x3fe0f426bb2a8e7d, 0xbfeb23cd470013b4, // 0.5298, -0.84812 + 0x3fe1097248d0a956, 0xbfeb16742a4ca2f5, // 0.5324, -0.84649 + 0x3fe11eb3541b4b22, 0xbfeb090a58150200, // 0.535, -0.84485 + 0x3fe133e9cfee254e, 0xbfeafb8fd89f57b6, // 0.53759, -0.84321 + 0x3fe14915af336ceb, 0xbfeaee04b43c1474, // 0.54017, -0.84155 + 0x3fe15e36e4dbe2bc, 0xbfeae068f345ecef, // 0.54275, -0.83989 + 0x3fe1734d63dedb49, 0xbfead2bc9e21d511, // 0.54532, -0.83822 + 0x3fe188591f3a46e5, 0xbfeac4ffbd3efac8, // 0.54789, -0.83655 + 0x3fe19d5a09f2b9b8, 0xbfeab7325916c0d4, // 0.55046, -0.83486 + 0x3fe1b250171373be, 0xbfeaa9547a2cb98e, // 0.55302, -0.83317 + 0x3fe1c73b39ae68c8, 0xbfea9b66290ea1a3, // 0.55557, -0.83147 + 0x3fe1dc1b64dc4872, 0xbfea8d676e545ad2, // 0.55812, -0.82976 + 0x3fe1f0f08bbc861b, 0xbfea7f58529fe69d, // 0.56066, -0.82805 + 0x3fe205baa17560d6, 0xbfea7138de9d60f5, // 0.5632, -0.82632 + 0x3fe21a799933eb58, 0xbfea63091b02fae2, // 0.56573, -0.82459 + 0x3fe22f2d662c13e1, 0xbfea54c91090f524, // 0.56826, -0.82285 + 0x3fe243d5fb98ac1f, 0xbfea4678c8119ac8, // 0.57078, -0.8211 + 0x3fe258734cbb7110, 0xbfea38184a593bc6, // 0.5733, -0.81935 + 0x3fe26d054cdd12df, 0xbfea29a7a0462782, // 0.57581, -0.81758 + 0x3fe2818bef4d3cba, 0xbfea1b26d2c0a75e, // 0.57831, -0.81581 + 0x3fe2960727629ca8, 0xbfea0c95eabaf937, // 0.58081, -0.81404 + 0x3fe2aa76e87aeb58, 0xbfe9fdf4f13149de, // 0.58331, -0.81225 + 0x3fe2bedb25faf3ea, 0xbfe9ef43ef29af94, // 0.5858, -0.81046 + 0x3fe2d333d34e9bb7, 0xbfe9e082edb42472, // 0.58828, -0.80866 + 0x3fe2e780e3e8ea16, 0xbfe9d1b1f5ea80d6, // 0.59076, -0.80685 + 0x3fe2fbc24b441015, 0xbfe9c2d110f075c3, // 0.59323, -0.80503 + 0x3fe30ff7fce17035, 0xbfe9b3e047f38741, // 0.5957, -0.80321 + 0x3fe32421ec49a620, 0xbfe9a4dfa42b06b2, // 0.59816, -0.80138 + 0x3fe338400d0c8e57, 0xbfe995cf2ed80d22, // 0.60062, -0.79954 + 0x3fe34c5252c14de1, 0xbfe986aef1457594, // 0.60307, -0.79769 + 0x3fe36058b10659f3, 0xbfe9777ef4c7d742, // 0.60551, -0.79584 + 0x3fe374531b817f8d, 0xbfe9683f42bd7fe1, // 0.60795, -0.79398 + 0x3fe3884185dfeb22, 0xbfe958efe48e6dd7, // 0.61038, -0.79211 + 0x3fe39c23e3d63029, 0xbfe94990e3ac4a6c, // 0.61281, -0.79023 + 0x3fe3affa292050b9, 0xbfe93a22499263fc, // 0.61523, -0.78835 + 0x3fe3c3c44981c517, 0xbfe92aa41fc5a815, // 0.61765, -0.78646 + 0x3fe3d78238c58343, 0xbfe91b166fd49da2, // 0.62006, -0.78456 + 0x3fe3eb33eabe0680, 0xbfe90b7943575efe, // 0.62246, -0.78265 + 0x3fe3fed9534556d4, 0xbfe8fbcca3ef940d, // 0.62486, -0.78074 + 0x3fe41272663d108c, 0xbfe8ec109b486c49, // 0.62725, -0.77882 + 0x3fe425ff178e6bb1, 0xbfe8dc45331698cc, // 0.62964, -0.77689 + 0x3fe4397f5b2a4380, 0xbfe8cc6a75184655, // 0.63202, -0.77495 + 0x3fe44cf325091dd6, 0xbfe8bc806b151741, // 0.63439, -0.77301 + 0x3fe4605a692b32a2, 0xbfe8ac871ede1d88, // 0.63676, -0.77106 + 0x3fe473b51b987347, 0xbfe89c7e9a4dd4ab, // 0.63912, -0.7691 + 0x3fe48703306091fe, 0xbfe88c66e7481ba1, // 0.64148, -0.76714 + 0x3fe49a449b9b0938, 0xbfe87c400fba2ebf, // 0.64383, -0.76517 + 0x3fe4ad79516722f0, 0xbfe86c0a1d9aa195, // 0.64618, -0.76319 + 0x3fe4c0a145ec0004, 0xbfe85bc51ae958cc, // 0.64851, -0.7612 + 0x3fe4d3bc6d589f80, 0xbfe84b7111af83f9, // 0.65085, -0.75921 + 0x3fe4e6cabbe3e5e9, 0xbfe83b0e0bff976e, // 0.65317, -0.75721 + 0x3fe4f9cc25cca486, 0xbfe82a9c13f545ff, // 0.65549, -0.7552 + 0x3fe50cc09f59a09b, 0xbfe81a1b33b57acc, // 0.65781, -0.75319 + 0x3fe51fa81cd99aa6, 0xbfe8098b756e52fa, // 0.66011, -0.75117 + 0x3fe5328292a35596, 0xbfe7f8ece3571771, // 0.66242, -0.74914 + 0x3fe5454ff5159dfb, 0xbfe7e83f87b03686, // 0.66471, -0.7471 + 0x3fe5581038975137, 0xbfe7d7836cc33db2, // 0.667, -0.74506 + 0x3fe56ac35197649e, 0xbfe7c6b89ce2d333, // 0.66928, -0.74301 + 0x3fe57d69348cec9f, 0xbfe7b5df226aafb0, // 0.67156, -0.74095 + 0x3fe59001d5f723df, 0xbfe7a4f707bf97d2, // 0.67383, -0.73889 + 0x3fe5a28d2a5d7250, 0xbfe79400574f55e4, // 0.67609, -0.73682 + 0x3fe5b50b264f7448, 0xbfe782fb1b90b35b, // 0.67835, -0.73474 + 0x3fe5c77bbe65018c, 0xbfe771e75f037261, // 0.6806, -0.73265 + 0x3fe5d9dee73e345c, 0xbfe760c52c304764, // 0.68285, -0.73056 + 0x3fe5ec3495837074, 0xbfe74f948da8d28d, // 0.68508, -0.72846 + 0x3fe5fe7cbde56a0f, 0xbfe73e558e079942, // 0.68732, -0.72636 + 0x3fe610b7551d2cde, 0xbfe72d0837efff97, // 0.68954, -0.72425 + 0x3fe622e44fec22ff, 0xbfe71bac960e41bf, // 0.69176, -0.72213 + 0x3fe63503a31c1be8, 0xbfe70a42b3176d7a, // 0.69397, -0.72 + 0x3fe64715437f535b, 0xbfe6f8ca99c95b75, // 0.69618, -0.71787 + 0x3fe6591925f0783e, 0xbfe6e74454eaa8ae, // 0.69838, -0.71573 + 0x3fe66b0f3f52b386, 0xbfe6d5afef4aafcc, // 0.70057, -0.71358 + 0x3fe67cf78491af10, 0xbfe6c40d73c18275, // 0.70275, -0.71143 + 0x3fe68ed1eaa19c71, 0xbfe6b25ced2fe29c, // 0.70493, -0.70927 + 0x3fe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // 0.70711, -0.70711 + 0x3fe6b25ced2fe29c, 0xbfe68ed1eaa19c71, // 0.70927, -0.70493 + 0x3fe6c40d73c18275, 0xbfe67cf78491af10, // 0.71143, -0.70275 + 0x3fe6d5afef4aafcc, 0xbfe66b0f3f52b386, // 0.71358, -0.70057 + 0x3fe6e74454eaa8ae, 0xbfe6591925f0783e, // 0.71573, -0.69838 + 0x3fe6f8ca99c95b75, 0xbfe64715437f535b, // 0.71787, -0.69618 + 0x3fe70a42b3176d7a, 0xbfe63503a31c1be8, // 0.72, -0.69397 + 0x3fe71bac960e41bf, 0xbfe622e44fec22ff, // 0.72213, -0.69176 + 0x3fe72d0837efff97, 0xbfe610b7551d2cde, // 0.72425, -0.68954 + 0x3fe73e558e079942, 0xbfe5fe7cbde56a0f, // 0.72636, -0.68732 + 0x3fe74f948da8d28d, 0xbfe5ec3495837074, // 0.72846, -0.68508 + 0x3fe760c52c304764, 0xbfe5d9dee73e345c, // 0.73056, -0.68285 + 0x3fe771e75f037261, 0xbfe5c77bbe65018c, // 0.73265, -0.6806 + 0x3fe782fb1b90b35b, 0xbfe5b50b264f7448, // 0.73474, -0.67835 + 0x3fe79400574f55e4, 0xbfe5a28d2a5d7250, // 0.73682, -0.67609 + 0x3fe7a4f707bf97d2, 0xbfe59001d5f723df, // 0.73889, -0.67383 + 0x3fe7b5df226aafb0, 0xbfe57d69348cec9f, // 0.74095, -0.67156 + 0x3fe7c6b89ce2d333, 0xbfe56ac35197649e, // 0.74301, -0.66928 + 0x3fe7d7836cc33db2, 0xbfe5581038975137, // 0.74506, -0.667 + 0x3fe7e83f87b03686, 0xbfe5454ff5159dfb, // 0.7471, -0.66471 + 0x3fe7f8ece3571771, 0xbfe5328292a35596, // 0.74914, -0.66242 + 0x3fe8098b756e52fa, 0xbfe51fa81cd99aa6, // 0.75117, -0.66011 + 0x3fe81a1b33b57acc, 0xbfe50cc09f59a09b, // 0.75319, -0.65781 + 0x3fe82a9c13f545ff, 0xbfe4f9cc25cca486, // 0.7552, -0.65549 + 0x3fe83b0e0bff976e, 0xbfe4e6cabbe3e5e9, // 0.75721, -0.65317 + 0x3fe84b7111af83f9, 0xbfe4d3bc6d589f80, // 0.75921, -0.65085 + 0x3fe85bc51ae958cc, 0xbfe4c0a145ec0004, // 0.7612, -0.64851 + 0x3fe86c0a1d9aa195, 0xbfe4ad79516722f0, // 0.76319, -0.64618 + 0x3fe87c400fba2ebf, 0xbfe49a449b9b0938, // 0.76517, -0.64383 + 0x3fe88c66e7481ba1, 0xbfe48703306091fe, // 0.76714, -0.64148 + 0x3fe89c7e9a4dd4ab, 0xbfe473b51b987347, // 0.7691, -0.63912 + 0x3fe8ac871ede1d88, 0xbfe4605a692b32a2, // 0.77106, -0.63676 + 0x3fe8bc806b151741, 0xbfe44cf325091dd6, // 0.77301, -0.63439 + 0x3fe8cc6a75184655, 0xbfe4397f5b2a4380, // 0.77495, -0.63202 + 0x3fe8dc45331698cc, 0xbfe425ff178e6bb1, // 0.77689, -0.62964 + 0x3fe8ec109b486c49, 0xbfe41272663d108c, // 0.77882, -0.62725 + 0x3fe8fbcca3ef940d, 0xbfe3fed9534556d4, // 0.78074, -0.62486 + 0x3fe90b7943575efe, 0xbfe3eb33eabe0680, // 0.78265, -0.62246 + 0x3fe91b166fd49da2, 0xbfe3d78238c58343, // 0.78456, -0.62006 + 0x3fe92aa41fc5a815, 0xbfe3c3c44981c517, // 0.78646, -0.61765 + 0x3fe93a22499263fc, 0xbfe3affa292050b9, // 0.78835, -0.61523 + 0x3fe94990e3ac4a6c, 0xbfe39c23e3d63029, // 0.79023, -0.61281 + 0x3fe958efe48e6dd7, 0xbfe3884185dfeb22, // 0.79211, -0.61038 + 0x3fe9683f42bd7fe1, 0xbfe374531b817f8d, // 0.79398, -0.60795 + 0x3fe9777ef4c7d742, 0xbfe36058b10659f3, // 0.79584, -0.60551 + 0x3fe986aef1457594, 0xbfe34c5252c14de1, // 0.79769, -0.60307 + 0x3fe995cf2ed80d22, 0xbfe338400d0c8e57, // 0.79954, -0.60062 + 0x3fe9a4dfa42b06b2, 0xbfe32421ec49a620, // 0.80138, -0.59816 + 0x3fe9b3e047f38741, 0xbfe30ff7fce17035, // 0.80321, -0.5957 + 0x3fe9c2d110f075c3, 0xbfe2fbc24b441015, // 0.80503, -0.59323 + 0x3fe9d1b1f5ea80d6, 0xbfe2e780e3e8ea16, // 0.80685, -0.59076 + 0x3fe9e082edb42472, 0xbfe2d333d34e9bb7, // 0.80866, -0.58828 + 0x3fe9ef43ef29af94, 0xbfe2bedb25faf3ea, // 0.81046, -0.5858 + 0x3fe9fdf4f13149de, 0xbfe2aa76e87aeb58, // 0.81225, -0.58331 + 0x3fea0c95eabaf937, 0xbfe2960727629ca8, // 0.81404, -0.58081 + 0x3fea1b26d2c0a75e, 0xbfe2818bef4d3cba, // 0.81581, -0.57831 + 0x3fea29a7a0462782, 0xbfe26d054cdd12df, // 0.81758, -0.57581 + 0x3fea38184a593bc6, 0xbfe258734cbb7110, // 0.81935, -0.5733 + 0x3fea4678c8119ac8, 0xbfe243d5fb98ac1f, // 0.8211, -0.57078 + 0x3fea54c91090f524, 0xbfe22f2d662c13e1, // 0.82285, -0.56826 + 0x3fea63091b02fae2, 0xbfe21a799933eb58, // 0.82459, -0.56573 + 0x3fea7138de9d60f5, 0xbfe205baa17560d6, // 0.82632, -0.5632 + 0x3fea7f58529fe69d, 0xbfe1f0f08bbc861b, // 0.82805, -0.56066 + 0x3fea8d676e545ad2, 0xbfe1dc1b64dc4872, // 0.82976, -0.55812 + 0x3fea9b66290ea1a3, 0xbfe1c73b39ae68c8, // 0.83147, -0.55557 + 0x3feaa9547a2cb98e, 0xbfe1b250171373be, // 0.83317, -0.55302 + 0x3feab7325916c0d4, 0xbfe19d5a09f2b9b8, // 0.83486, -0.55046 + 0x3feac4ffbd3efac8, 0xbfe188591f3a46e5, // 0.83655, -0.54789 + 0x3fead2bc9e21d511, 0xbfe1734d63dedb49, // 0.83822, -0.54532 + 0x3feae068f345ecef, 0xbfe15e36e4dbe2bc, // 0.83989, -0.54275 + 0x3feaee04b43c1474, 0xbfe14915af336ceb, // 0.84155, -0.54017 + 0x3feafb8fd89f57b6, 0xbfe133e9cfee254e, // 0.84321, -0.53759 + 0x3feb090a58150200, 0xbfe11eb3541b4b22, // 0.84485, -0.535 + 0x3feb16742a4ca2f5, 0xbfe1097248d0a956, // 0.84649, -0.5324 + 0x3feb23cd470013b4, 0xbfe0f426bb2a8e7d, // 0.84812, -0.5298 + 0x3feb3115a5f37bf4, 0xbfe0ded0b84bc4b5, // 0.84974, -0.5272 + 0x3feb3e4d3ef55712, 0xbfe0c9704d5d898f, // 0.85136, -0.52459 + 0x3feb4b7409de7925, 0xbfe0b405878f85ec, // 0.85296, -0.52198 + 0x3feb5889fe921405, 0xbfe09e907417c5e1, // 0.85456, -0.51936 + 0x3feb658f14fdbc47, 0xbfe089112032b08c, // 0.85615, -0.51673 + 0x3feb728345196e3e, 0xbfe073879922ffed, // 0.85773, -0.5141 + 0x3feb7f6686e792ea, 0xbfe05df3ec31b8b6, // 0.8593, -0.51147 + 0x3feb8c38d27504e9, 0xbfe0485626ae221a, // 0.86087, -0.50883 + 0x3feb98fa1fd9155e, 0xbfe032ae55edbd95, // 0.86242, -0.50619 + 0x3feba5aa673590d2, 0xbfe01cfc874c3eb7, // 0.86397, -0.50354 + 0x3febb249a0b6c40d, 0xbfe00740c82b82e0, // 0.86551, -0.50089 + 0x3febbed7c49380ea, 0xbfdfe2f64be7120f, // 0.86705, -0.49823 + 0x3febcb54cb0d2327, 0xbfdfb7575c24d2de, // 0.86857, -0.49557 + 0x3febd7c0ac6f952a, 0xbfdf8ba4dbf89aba, // 0.87009, -0.4929 + 0x3febe41b611154c1, 0xbfdf5fdee656cda3, // 0.8716, -0.49023 + 0x3febf064e15377dd, 0xbfdf3405963fd068, // 0.87309, -0.48755 + 0x3febfc9d25a1b147, 0xbfdf081906bff7fd, // 0.87459, -0.48487 + 0x3fec08c426725549, 0xbfdedc1952ef78d5, // 0.87607, -0.48218 + 0x3fec14d9dc465e58, 0xbfdeb00695f25620, // 0.87755, -0.47949 + 0x3fec20de3fa971b0, 0xbfde83e0eaf85113, // 0.87901, -0.4768 + 0x3fec2cd14931e3f1, 0xbfde57a86d3cd824, // 0.88047, -0.4741 + 0x3fec38b2f180bdb1, 0xbfde2b5d3806f63b, // 0.88192, -0.4714 + 0x3fec44833141c004, 0xbfddfeff66a941de, // 0.88336, -0.46869 + 0x3fec5042012b6907, 0xbfddd28f1481cc58, // 0.8848, -0.46598 + 0x3fec5bef59fef85a, 0xbfdda60c5cfa10d8, // 0.88622, -0.46326 + 0x3fec678b3488739b, 0xbfdd79775b86e389, // 0.88764, -0.46054 + 0x3fec7315899eaad7, 0xbfdd4cd02ba8609c, // 0.88905, -0.45781 + 0x3fec7e8e52233cf3, 0xbfdd2016e8e9db5b, // 0.89045, -0.45508 + 0x3fec89f587029c13, 0xbfdcf34baee1cd21, // 0.89184, -0.45235 + 0x3fec954b213411f5, 0xbfdcc66e9931c45d, // 0.89322, -0.44961 + 0x3feca08f19b9c449, 0xbfdc997fc3865388, // 0.8946, -0.44687 + 0x3fecabc169a0b901, 0xbfdc6c7f4997000a, // 0.89597, -0.44412 + 0x3fecb6e20a00da99, 0xbfdc3f6d47263129, // 0.89732, -0.44137 + 0x3fecc1f0f3fcfc5c, 0xbfdc1249d8011ee7, // 0.89867, -0.43862 + 0x3fecccee20c2de9f, 0xbfdbe51517ffc0d9, // 0.90002, -0.43586 + 0x3fecd7d9898b32f6, 0xbfdbb7cf2304bd01, // 0.90135, -0.43309 + 0x3fece2b32799a060, 0xbfdb8a7814fd5693, // 0.90267, -0.43033 + 0x3feced7af43cc773, 0xbfdb5d1009e15cc0, // 0.90399, -0.42756 + 0x3fecf830e8ce467b, 0xbfdb2f971db31972, // 0.9053, -0.42478 + 0x3fed02d4feb2bd92, 0xbfdb020d6c7f4009, // 0.9066, -0.422 + 0x3fed0d672f59d2b9, 0xbfdad473125cdc08, // 0.90789, -0.41922 + 0x3fed17e7743e35dc, 0xbfdaa6c82b6d3fc9, // 0.90917, -0.41643 + 0x3fed2255c6e5a4e1, 0xbfda790cd3dbf31a, // 0.91044, -0.41364 + 0x3fed2cb220e0ef9f, 0xbfda4b4127dea1e4, // 0.91171, -0.41084 + 0x3fed36fc7bcbfbdc, 0xbfda1d6543b50ac0, // 0.91296, -0.40804 + 0x3fed4134d14dc93a, 0xbfd9ef7943a8ed8a, // 0.91421, -0.40524 + 0x3fed4b5b1b187524, 0xbfd9c17d440df9f2, // 0.91545, -0.40243 + 0x3fed556f52e93eb1, 0xbfd993716141bdfe, // 0.91668, -0.39962 + 0x3fed5f7172888a7f, 0xbfd96555b7ab948f, // 0.9179, -0.39681 + 0x3fed696173c9e68b, 0xbfd9372a63bc93d7, // 0.91911, -0.39399 + 0x3fed733f508c0dff, 0xbfd908ef81ef7bd1, // 0.92032, -0.39117 + 0x3fed7d0b02b8ecf9, 0xbfd8daa52ec8a4af, // 0.92151, -0.38835 + 0x3fed86c48445a450, 0xbfd8ac4b86d5ed44, // 0.9227, -0.38552 + 0x3fed906bcf328d46, 0xbfd87de2a6aea963, // 0.92388, -0.38268 + 0x3fed9a00dd8b3d46, 0xbfd84f6aaaf3903f, // 0.92505, -0.37985 + 0x3feda383a9668988, 0xbfd820e3b04eaac4, // 0.92621, -0.37701 + 0x3fedacf42ce68ab9, 0xbfd7f24dd37341e3, // 0.92736, -0.37416 + 0x3fedb6526238a09b, 0xbfd7c3a9311dcce7, // 0.92851, -0.37132 + 0x3fedbf9e4395759a, 0xbfd794f5e613dfae, // 0.92964, -0.36847 + 0x3fedc8d7cb410260, 0xbfd766340f2418f6, // 0.93077, -0.36561 + 0x3fedd1fef38a915a, 0xbfd73763c9261092, // 0.93188, -0.36276 + 0x3feddb13b6ccc23d, 0xbfd7088530fa459e, // 0.93299, -0.3599 + 0x3fede4160f6d8d81, 0xbfd6d998638a0cb5, // 0.93409, -0.35703 + 0x3feded05f7de47da, 0xbfd6aa9d7dc77e16, // 0.93518, -0.35416 + 0x3fedf5e36a9ba59c, 0xbfd67b949cad63ca, // 0.93627, -0.35129 + 0x3fedfeae622dbe2b, 0xbfd64c7ddd3f27c6, // 0.93734, -0.34842 + 0x3fee0766d9280f54, 0xbfd61d595c88c203, // 0.9384, -0.34554 + 0x3fee100cca2980ac, 0xbfd5ee27379ea693, // 0.93946, -0.34266 + 0x3fee18a02fdc66d9, 0xbfd5bee78b9db3b6, // 0.94051, -0.33978 + 0x3fee212104f686e5, 0xbfd58f9a75ab1fdd, // 0.94154, -0.33689 + 0x3fee298f4439197a, 0xbfd5604012f467b4, // 0.94257, -0.334 + 0x3fee31eae870ce25, 0xbfd530d880af3c24, // 0.94359, -0.33111 + 0x3fee3a33ec75ce85, 0xbfd50163dc197047, // 0.9446, -0.32821 + 0x3fee426a4b2bc17e, 0xbfd4d1e24278e76a, // 0.94561, -0.32531 + 0x3fee4a8dff81ce5e, 0xbfd4a253d11b82f3, // 0.9466, -0.32241 + 0x3fee529f04729ffc, 0xbfd472b8a5571054, // 0.94759, -0.3195 + 0x3fee5a9d550467d3, 0xbfd44310dc8936f0, // 0.94856, -0.31659 + 0x3fee6288ec48e112, 0xbfd4135c94176602, // 0.94953, -0.31368 + 0x3fee6a61c55d53a7, 0xbfd3e39be96ec271, // 0.95049, -0.31077 + 0x3fee7227db6a9744, 0xbfd3b3cefa0414b7, // 0.95144, -0.30785 + 0x3fee79db29a5165a, 0xbfd383f5e353b6aa, // 0.95238, -0.30493 + 0x3fee817bab4cd10d, 0xbfd35410c2e18152, // 0.95331, -0.30201 + 0x3fee89095bad6025, 0xbfd3241fb638baaf, // 0.95423, -0.29908 + 0x3fee9084361df7f3, 0xbfd2f422daec0386, // 0.95514, -0.29615 + 0x3fee97ec36016b30, 0xbfd2c41a4e954520, // 0.95605, -0.29322 + 0x3fee9f4156c62dda, 0xbfd294062ed59f05, // 0.95694, -0.29028 + 0x3feea68393e65800, 0xbfd263e6995554ba, // 0.95783, -0.28735 + 0x3feeadb2e8e7a88e, 0xbfd233bbabc3bb72, // 0.9587, -0.28441 + 0x3feeb4cf515b8811, 0xbfd2038583d727bd, // 0.95957, -0.28146 + 0x3feebbd8c8df0b74, 0xbfd1d3443f4cdb3d, // 0.96043, -0.27852 + 0x3feec2cf4b1af6b2, 0xbfd1a2f7fbe8f243, // 0.96128, -0.27557 + 0x3feec9b2d3c3bf84, 0xbfd172a0d7765177, // 0.96212, -0.27262 + 0x3feed0835e999009, 0xbfd1423eefc69378, // 0.96295, -0.26967 + 0x3feed740e7684963, 0xbfd111d262b1f677, // 0.96378, -0.26671 + 0x3feeddeb6a078651, 0xbfd0e15b4e1749cd, // 0.96459, -0.26375 + 0x3feee482e25a9dbc, 0xbfd0b0d9cfdbdb90, // 0.96539, -0.26079 + 0x3feeeb074c50a544, 0xbfd0804e05eb661e, // 0.96619, -0.25783 + 0x3feef178a3e473c2, 0xbfd04fb80e37fdae, // 0.96698, -0.25487 + 0x3feef7d6e51ca3c0, 0xbfd01f1806b9fdd2, // 0.96775, -0.2519 + 0x3feefe220c0b95ec, 0xbfcfdcdc1adfedf8, // 0.96852, -0.24893 + 0x3fef045a14cf738c, 0xbfcf7b7480bd3801, // 0.96928, -0.24596 + 0x3fef0a7efb9230d7, 0xbfcf19f97b215f1a, // 0.97003, -0.24298 + 0x3fef1090bc898f5f, 0xbfceb86b462de348, // 0.97077, -0.24 + 0x3fef168f53f7205d, 0xbfce56ca1e101a1b, // 0.9715, -0.23702 + 0x3fef1c7abe284708, 0xbfcdf5163f01099a, // 0.97223, -0.23404 + 0x3fef2252f7763ada, 0xbfcd934fe5454311, // 0.97294, -0.23106 + 0x3fef2817fc4609ce, 0xbfcd31774d2cbdee, // 0.97364, -0.22807 + 0x3fef2dc9c9089a9d, 0xbfcccf8cb312b286, // 0.97434, -0.22508 + 0x3fef33685a3aaef0, 0xbfcc6d90535d74dc, // 0.97503, -0.22209 + 0x3fef38f3ac64e589, 0xbfcc0b826a7e4f63, // 0.9757, -0.2191 + 0x3fef3e6bbc1bbc65, 0xbfcba96334f15dad, // 0.97637, -0.21611 + 0x3fef43d085ff92dd, 0xbfcb4732ef3d6722, // 0.97703, -0.21311 + 0x3fef492206bcabb4, 0xbfcae4f1d5f3b9ab, // 0.97768, -0.21011 + 0x3fef4e603b0b2f2d, 0xbfca82a025b00451, // 0.97832, -0.20711 + 0x3fef538b1faf2d07, 0xbfca203e1b1831da, // 0.97895, -0.20411 + 0x3fef58a2b1789e84, 0xbfc9bdcbf2dc4366, // 0.97957, -0.2011 + 0x3fef5da6ed43685d, 0xbfc95b49e9b62af9, // 0.98018, -0.1981 + 0x3fef6297cff75cb0, 0xbfc8f8b83c69a60a, // 0.98079, -0.19509 + 0x3fef677556883cee, 0xbfc8961727c41804, // 0.98138, -0.19208 + 0x3fef6c3f7df5bbb7, 0xbfc83366e89c64c5, // 0.98196, -0.18907 + 0x3fef70f6434b7eb7, 0xbfc7d0a7bbd2cb1b, // 0.98254, -0.18606 + 0x3fef7599a3a12077, 0xbfc76dd9de50bf31, // 0.98311, -0.18304 + 0x3fef7a299c1a322a, 0xbfc70afd8d08c4ff, // 0.98366, -0.18002 + 0x3fef7ea629e63d6e, 0xbfc6a81304f64ab2, // 0.98421, -0.177 + 0x3fef830f4a40c60c, 0xbfc6451a831d830d, // 0.98475, -0.17398 + 0x3fef8764fa714ba9, 0xbfc5e214448b3fc6, // 0.98528, -0.17096 + 0x3fef8ba737cb4b78, 0xbfc57f008654cbde, // 0.9858, -0.16794 + 0x3fef8fd5ffae41db, 0xbfc51bdf8597c5f2, // 0.98631, -0.16491 + 0x3fef93f14f85ac08, 0xbfc4b8b17f79fa88, // 0.98681, -0.16189 + 0x3fef97f924c9099b, 0xbfc45576b1293e5a, // 0.9873, -0.15886 + 0x3fef9bed7cfbde29, 0xbfc3f22f57db4893, // 0.98778, -0.15583 + 0x3fef9fce55adb2c8, 0xbfc38edbb0cd8d14, // 0.98826, -0.1528 + 0x3fefa39bac7a1791, 0xbfc32b7bf94516a7, // 0.98872, -0.14976 + 0x3fefa7557f08a517, 0xbfc2c8106e8e613a, // 0.98918, -0.14673 + 0x3fefaafbcb0cfddc, 0xbfc264994dfd340a, // 0.98962, -0.1437 + 0x3fefae8e8e46cfbb, 0xbfc20116d4ec7bce, // 0.99006, -0.14066 + 0x3fefb20dc681d54d, 0xbfc19d8940be24e7, // 0.99049, -0.13762 + 0x3fefb5797195d741, 0xbfc139f0cedaf576, // 0.9909, -0.13458 + 0x3fefb8d18d66adb7, 0xbfc0d64dbcb26786, // 0.99131, -0.13154 + 0x3fefbc1617e44186, 0xbfc072a047ba831d, // 0.99171, -0.1285 + 0x3fefbf470f0a8d88, 0xbfc00ee8ad6fb85b, // 0.9921, -0.12545 + 0x3fefc26470e19fd3, 0xbfbf564e56a9730e, // 0.99248, -0.12241 + 0x3fefc56e3b7d9af6, 0xbfbe8eb7fde4aa3e, // 0.99285, -0.11937 + 0x3fefc8646cfeb721, 0xbfbdc70ecbae9fc8, // 0.99321, -0.11632 + 0x3fefcb4703914354, 0xbfbcff533b307dc1, // 0.99356, -0.11327 + 0x3fefce15fd6da67b, 0xbfbc3785c79ec2d5, // 0.99391, -0.11022 + 0x3fefd0d158d86087, 0xbfbb6fa6ec38f64c, // 0.99424, -0.10717 + 0x3fefd37914220b84, 0xbfbaa7b724495c04, // 0.99456, -0.10412 + 0x3fefd60d2da75c9e, 0xbfb9dfb6eb24a85c, // 0.99488, -0.10107 + 0x3fefd88da3d12526, 0xbfb917a6bc29b42c, // 0.99518, -0.098017 + 0x3fefdafa7514538c, 0xbfb84f8712c130a0, // 0.99548, -0.094963 + 0x3fefdd539ff1f456, 0xbfb787586a5d5b21, // 0.99577, -0.091909 + 0x3fefdf9922f73307, 0xbfb6bf1b3e79b129, // 0.99604, -0.088854 + 0x3fefe1cafcbd5b09, 0xbfb5f6d00a9aa419, // 0.99631, -0.085797 + 0x3fefe3e92be9d886, 0xbfb52e774a4d4d0a, // 0.99657, -0.08274 + 0x3fefe5f3af2e3940, 0xbfb4661179272096, // 0.99682, -0.079682 + 0x3fefe7ea85482d60, 0xbfb39d9f12c5a299, // 0.99706, -0.076624 + 0x3fefe9cdad01883a, 0xbfb2d52092ce19f6, // 0.99729, -0.073565 + 0x3fefeb9d2530410f, 0xbfb20c9674ed444c, // 0.99751, -0.070505 + 0x3fefed58ecb673c4, 0xbfb1440134d709b2, // 0.99772, -0.067444 + 0x3fefef0102826191, 0xbfb07b614e463064, // 0.99793, -0.064383 + 0x3feff095658e71ad, 0xbfaf656e79f820e0, // 0.99812, -0.061321 + 0x3feff21614e131ed, 0xbfadd406f9808ec8, // 0.9983, -0.058258 + 0x3feff3830f8d575c, 0xbfac428d12c0d7e3, // 0.99848, -0.055195 + 0x3feff4dc54b1bed3, 0xbfaab101bd5f8317, // 0.99864, -0.052132 + 0x3feff621e3796d7e, 0xbfa91f65f10dd814, // 0.9988, -0.049068 + 0x3feff753bb1b9164, 0xbfa78dbaa5874685, // 0.99894, -0.046003 + 0x3feff871dadb81df, 0xbfa5fc00d290cd43, // 0.99908, -0.042938 + 0x3feff97c4208c014, 0xbfa46a396ff86179, // 0.9992, -0.039873 + 0x3feffa72effef75d, 0xbfa2d865759455cd, // 0.99932, -0.036807 + 0x3feffb55e425fdae, 0xbfa14685db42c17e, // 0.99943, -0.033741 + 0x3feffc251df1d3f8, 0xbf9f693731d1cf01, // 0.99953, -0.030675 + 0x3feffce09ce2a679, 0xbf9c454f4ce53b1c, // 0.99962, -0.027608 + 0x3feffd886084cd0d, 0xbf992155f7a3667e, // 0.9997, -0.024541 + 0x3feffe1c6870cb77, 0xbf95fd4d21fab226, // 0.99977, -0.021474 + 0x3feffe9cb44b51a1, 0xbf92d936bbe30efd, // 0.99983, -0.018407 + 0x3fefff0943c53bd1, 0xbf8f6a296ab997ca, // 0.99988, -0.015339 + 0x3fefff62169b92db, 0xbf8921d1fcdec784, // 0.99992, -0.012272 + 0x3fefffa72c978c4f, 0xbf82d96b0e509703, // 0.99996,-0.0092038 + 0x3fefffd8858e8a92, 0xbf7921f0fe670071, // 0.99998,-0.0061359 + 0x3feffff621621d02, 0xbf6921f8becca4ba, // 1, -0.003068 + +}; + +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_F64_4096) +/** + @par + Example code for Double Precision Floating-point Twiddle factors Generation: + @par + 
for (i = 0; i< N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/(float)N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 4096, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const uint64_t twiddleCoefF64_4096[8192] = { + 0x3ff0000000000000, 0x0000000000000000, // 1, 0 + 0x3feffffd88586ee6, 0x3f5921faaee6472d, // 1, 0.001534 + 0x3feffff621621d02, 0x3f6921f8becca4ba, // 1, 0.003068 + 0x3fefffe9cb1e2e8d, 0x3f72d97822f996bc, // 0.99999, 0.0046019 + 0x3fefffd8858e8a92, 0x3f7921f0fe670071, // 0.99998, 0.0061359 + 0x3fefffc250b5daef, 0x3f7f6a65f9a2a3c5, // 0.99997, 0.0076698 + 0x3fefffa72c978c4f, 0x3f82d96b0e509703, // 0.99996, 0.0092038 + 0x3fefff871937ce2f, 0x3f85fda037ac05e0, // 0.99994, 0.010738 + 0x3fefff62169b92db, 0x3f8921d1fcdec784, // 0.99992, 0.012272 + 0x3fefff3824c88f6f, 0x3f8c45ffe1e48ad9, // 0.9999, 0.013805 + 0x3fefff0943c53bd1, 0x3f8f6a296ab997ca, // 0.99988, 0.015339 + 0x3feffed57398d2b7, 0x3f9147270dad7132, // 0.99986, 0.016873 + 0x3feffe9cb44b51a1, 0x3f92d936bbe30efd, // 0.99983, 0.018407 + 0x3feffe5f05e578db, 0x3f946b4381fce81c, // 0.9998, 0.01994 + 0x3feffe1c6870cb77, 0x3f95fd4d21fab226, // 0.99977, 0.021474 + 0x3feffdd4dbf78f52, 0x3f978f535ddc9f03, // 0.99974, 0.023008 + 0x3feffd886084cd0d, 0x3f992155f7a3667e, // 0.9997, 0.024541 + 0x3feffd36f624500c, 0x3f9ab354b1504fca, // 0.99966, 0.026075 + 0x3feffce09ce2a679, 0x3f9c454f4ce53b1c, // 0.99962, 0.027608 + 0x3feffc8554cd213a, 0x3f9dd7458c64ab39, // 0.99958, 0.029142 + 0x3feffc251df1d3f8, 0x3f9f693731d1cf01, // 0.99953, 0.030675 + 0x3feffbbff85f9515, 0x3fa07d91ff984580, // 0.99948, 0.032208 + 0x3feffb55e425fdae, 0x3fa14685db42c17e, // 0.99943, 0.033741 + 0x3feffae6e1556998, 0x3fa20f770ceb11c6, // 0.99938, 0.035274 + 0x3feffa72effef75d, 0x3fa2d865759455cd, // 0.99932, 0.036807 + 0x3feff9fa10348837, 0x3fa3a150f6421afc, // 0.99926, 0.03834 + 0x3feff97c4208c014, 0x3fa46a396ff86179, // 0.9992, 0.039873 + 0x3feff8f9858f058b, 0x3fa5331ec3bba0eb, // 0.99914, 0.041406 + 0x3feff871dadb81df, 0x3fa5fc00d290cd43, // 0.99908, 0.042938 + 0x3feff7e5420320f9, 0x3fa6c4df7d7d5b84, // 0.99901, 0.044471 + 0x3feff753bb1b9164, 0x3fa78dbaa5874685, // 0.99894, 0.046003 + 0x3feff6bd463b444d, 0x3fa856922bb513c1, // 0.99887, 0.047535 + 0x3feff621e3796d7e, 0x3fa91f65f10dd814, // 0.9988, 0.049068 + 0x3feff58192ee0358, 0x3fa9e835d6993c87, // 0.99872, 0.0506 + 0x3feff4dc54b1bed3, 0x3faab101bd5f8317, // 0.99864, 0.052132 + 0x3feff43228de1b77, 0x3fab79c986698b78, // 0.99856, 0.053664 + 0x3feff3830f8d575c, 0x3fac428d12c0d7e3, // 0.99848, 0.055195 + 0x3feff2cf08da7321, 0x3fad0b4c436f91d0, // 0.99839, 0.056727 + 0x3feff21614e131ed, 0x3fadd406f9808ec8, // 0.9983, 0.058258 + 0x3feff15833be1965, 0x3fae9cbd15ff5527, // 0.99821, 0.05979 + 0x3feff095658e71ad, 0x3faf656e79f820e0, // 0.99812, 0.061321 + 0x3fefefcdaa704562, 0x3fb0170d833bf421, // 0.99802, 0.062852 + 0x3fefef0102826191, 0x3fb07b614e463064, // 0.99793, 0.064383 + 0x3fefee2f6de455ba, 0x3fb0dfb28ea201e6, // 0.99783, 0.065913 + 0x3fefed58ecb673c4, 0x3fb1440134d709b2, // 0.99772, 0.067444 + 0x3fefec7d7f19cffc, 0x3fb1a84d316d4f8a, // 0.99762, 0.068974 + 0x3fefeb9d2530410f, 0x3fb20c9674ed444c, // 0.99751, 0.070505 + 0x3fefeab7df1c6005, 0x3fb270dcefdfc45b, // 0.9974, 0.072035 + 0x3fefe9cdad01883a, 0x3fb2d52092ce19f6, // 0.99729, 0.073565 + 0x3fefe8de8f03d75c, 0x3fb339614e41ffa5, // 0.99718, 0.075094 + 0x3fefe7ea85482d60, 0x3fb39d9f12c5a299, // 0.99706, 0.076624 + 0x3fefe6f18ff42c84, 0x3fb401d9d0e3a507, // 0.99694, 0.078153 + 0x3fefe5f3af2e3940, 0x3fb4661179272096, // 0.99682, 0.079682 + 0x3fefe4f0e31d7a4a, 0x3fb4ca45fc1ba8b6, // 0.9967, 0.081211 + 0x3fefe3e92be9d886, 0x3fb52e774a4d4d0a, // 0.99657, 0.08274 + 0x3fefe2dc89bbff08, 0x3fb592a554489bc8, // 0.99644, 0.084269 + 0x3fefe1cafcbd5b09, 0x3fb5f6d00a9aa419, // 0.99631, 0.085797 + 0x3fefe0b485181be3, 0x3fb65af75dd0f87b, // 0.99618, 0.087326 + 0x3fefdf9922f73307, 0x3fb6bf1b3e79b129, // 0.99604, 0.088854 + 0x3fefde78d68653fd, 0x3fb7233b9d236e71, // 0.99591, 0.090381 + 0x3fefdd539ff1f456, 0x3fb787586a5d5b21, // 0.99577, 0.091909 + 0x3fefdc297f674ba9, 0x3fb7eb7196b72ee4, // 0.99563, 0.093436 + 0x3fefdafa7514538c, 0x3fb84f8712c130a0, // 0.99548, 0.094963 + 0x3fefd9c68127c78c, 0x3fb8b398cf0c38e0, // 0.99533, 0.09649 + 0x3fefd88da3d12526, 0x3fb917a6bc29b42c, // 0.99518, 0.098017 + 0x3fefd74fdd40abbf, 0x3fb97bb0caaba56f, // 0.99503, 0.099544 + 0x3fefd60d2da75c9e, 0x3fb9dfb6eb24a85c, // 0.99488, 0.10107 + 0x3fefd4c59536fae4, 0x3fba43b90e27f3c4, // 0.99472, 0.1026 + 0x3fefd37914220b84, 0x3fbaa7b724495c04, // 0.99456, 0.10412 + 0x3fefd227aa9bd53b, 0x3fbb0bb11e1d5559, // 0.9944, 0.10565 + 0x3fefd0d158d86087, 0x3fbb6fa6ec38f64c, // 0.99424, 0.10717 + 0x3fefcf761f0c77a3, 0x3fbbd3987f31fa0e, // 0.99407, 0.1087 + 0x3fefce15fd6da67b, 0x3fbc3785c79ec2d5, // 0.99391, 0.11022 + 0x3fefccb0f4323aa3, 0x3fbc9b6eb6165c42, // 0.99374, 0.11175 + 0x3fefcb4703914354, 0x3fbcff533b307dc1, // 0.99356, 0.11327 + 0x3fefc9d82bc2915e, 0x3fbd633347858ce4, // 0.99339, 0.11479 + 0x3fefc8646cfeb721, 0x3fbdc70ecbae9fc8, // 0.99321, 0.11632 + 0x3fefc6ebc77f0887, 0x3fbe2ae5b8457f77, // 0.99303, 0.11784 + 0x3fefc56e3b7d9af6, 0x3fbe8eb7fde4aa3e, // 0.99285, 0.11937 + 0x3fefc3ebc935454c, 0x3fbef2858d27561b, // 0.99267, 0.12089 + 0x3fefc26470e19fd3, 0x3fbf564e56a9730e, // 0.99248, 0.12241 + 0x3fefc0d832bf043a, 0x3fbfba124b07ad85, // 0.99229, 0.12393 + 0x3fefbf470f0a8d88, 0x3fc00ee8ad6fb85b, // 0.9921, 0.12545 + 0x3fefbdb106021816, 0x3fc040c5bb67747e, // 0.99191, 0.12698 + 0x3fefbc1617e44186, 0x3fc072a047ba831d, // 0.99171, 0.1285 + 0x3fefba7644f068b5, 0x3fc0a4784ab8bf1d, // 0.99151, 0.13002 + 0x3fefb8d18d66adb7, 0x3fc0d64dbcb26786, // 0.99131, 0.13154 + 0x3fefb727f187f1c7, 0x3fc1082095f820b0, // 0.99111, 0.13306 + 0x3fefb5797195d741, 0x3fc139f0cedaf576, // 0.9909, 0.13458 + 0x3fefb3c60dd2c199, 0x3fc16bbe5fac5865, // 0.9907, 0.1361 + 0x3fefb20dc681d54d, 0x3fc19d8940be24e7, // 0.99049, 0.13762 + 0x3fefb0509be6f7db, 0x3fc1cf516a62a077, // 0.99027, 0.13914 + 0x3fefae8e8e46cfbb, 0x3fc20116d4ec7bce, // 0.99006, 0.14066 + 0x3fefacc79de6c44f, 0x3fc232d978aed413, // 0.98984, 0.14218 + 0x3fefaafbcb0cfddc, 0x3fc264994dfd340a, // 0.98962, 0.1437 + 0x3fefa92b1600657c, 0x3fc296564d2b953e, // 0.9894, 0.14521 + 0x3fefa7557f08a517, 0x3fc2c8106e8e613a, // 0.98918, 0.14673 + 0x3fefa57b066e2754, 0x3fc2f9c7aa7a72af, // 0.98895, 0.14825 + 0x3fefa39bac7a1791, 0x3fc32b7bf94516a7, // 0.98872, 0.14976 + 0x3fefa1b7717661d5, 0x3fc35d2d53440db2, // 0.98849, 0.15128 + 0x3fef9fce55adb2c8, 0x3fc38edbb0cd8d14, // 0.98826, 0.1528 + 0x3fef9de0596b77a3, 0x3fc3c0870a383ff6, // 0.98802, 0.15431 + 0x3fef9bed7cfbde29, 0x3fc3f22f57db4893, // 0.98778, 0.15583 + 0x3fef99f5c0abd496, 0x3fc423d4920e4166, // 0.98754, 0.15734 + 0x3fef97f924c9099b, 0x3fc45576b1293e5a, // 0.9873, 0.15886 + 0x3fef95f7a9a1ec47, 0x3fc48715ad84cdf5, // 0.98706, 0.16037 + 0x3fef93f14f85ac08, 0x3fc4b8b17f79fa88, // 0.98681, 0.16189 + 0x3fef91e616c43891, 0x3fc4ea4a1f624b61, // 0.98656, 0.1634 + 0x3fef8fd5ffae41db, 0x3fc51bdf8597c5f2, // 0.98631, 0.16491 + 0x3fef8dc10a95380d, 0x3fc54d71aa74ef02, // 0.98605, 0.16643 + 0x3fef8ba737cb4b78, 0x3fc57f008654cbde, // 0.9858, 0.16794 + 0x3fef898887a36c84, 0x3fc5b08c1192e381, // 0.98554, 0.16945 + 0x3fef8764fa714ba9, 0x3fc5e214448b3fc6, // 0.98528, 0.17096 + 0x3fef853c9089595e, 0x3fc61399179a6e94, // 0.98501, 0.17247 + 0x3fef830f4a40c60c, 0x3fc6451a831d830d, // 0.98475, 0.17398 + 0x3fef80dd27ed8204, 0x3fc676987f7216b8, // 0.98448, 0.17549 + 0x3fef7ea629e63d6e, 0x3fc6a81304f64ab2, // 0.98421, 0.177 + 0x3fef7c6a50826840, 0x3fc6d98a0c08c8da, // 0.98394, 0.17851 + 0x3fef7a299c1a322a, 0x3fc70afd8d08c4ff, // 0.98366, 0.18002 + 0x3fef77e40d068a90, 0x3fc73c6d8055fe0a, // 0.98339, 0.18153 + 0x3fef7599a3a12077, 0x3fc76dd9de50bf31, // 0.98311, 0.18304 + 0x3fef734a60446279, 0x3fc79f429f59e11d, // 0.98282, 0.18455 + 0x3fef70f6434b7eb7, 0x3fc7d0a7bbd2cb1b, // 0.98254, 0.18606 + 0x3fef6e9d4d1262ca, 0x3fc802092c1d744b, // 0.98225, 0.18756 + 0x3fef6c3f7df5bbb7, 0x3fc83366e89c64c5, // 0.98196, 0.18907 + 0x3fef69dcd652f5de, 0x3fc864c0e9b2b6cf, // 0.98167, 0.19057 + 0x3fef677556883cee, 0x3fc8961727c41804, // 0.98138, 0.19208 + 0x3fef6508fef47bd5, 0x3fc8c7699b34ca7e, // 0.98108, 0.19359 + 0x3fef6297cff75cb0, 0x3fc8f8b83c69a60a, // 0.98079, 0.19509 + 0x3fef6021c9f148c2, 0x3fc92a0303c8194f, // 0.98048, 0.19659 + 0x3fef5da6ed43685d, 0x3fc95b49e9b62af9, // 0.98018, 0.1981 + 0x3fef5b273a4fa2d9, 0x3fc98c8ce69a7aec, // 0.97988, 0.1996 + 0x3fef58a2b1789e84, 0x3fc9bdcbf2dc4366, // 0.97957, 0.2011 + 0x3fef56195321c090, 0x3fc9ef0706e35a35, // 0.97926, 0.20261 + 0x3fef538b1faf2d07, 0x3fca203e1b1831da, // 0.97895, 0.20411 + 0x3fef50f81785c6b9, 0x3fca517127e3dabc, // 0.97863, 0.20561 + 0x3fef4e603b0b2f2d, 0x3fca82a025b00451, // 0.97832, 0.20711 + 0x3fef4bc38aa5c694, 0x3fcab3cb0ce6fe44, // 0.978, 0.20861 + 0x3fef492206bcabb4, 0x3fcae4f1d5f3b9ab, // 0.97768, 0.21011 + 0x3fef467bafb7bbe0, 0x3fcb16147941ca2a, // 0.97735, 0.21161 + 0x3fef43d085ff92dd, 0x3fcb4732ef3d6722, // 0.97703, 0.21311 + 0x3fef412089fd8adc, 0x3fcb784d30536cda, // 0.9767, 0.21461 + 0x3fef3e6bbc1bbc65, 0x3fcba96334f15dad, // 0.97637, 0.21611 + 0x3fef3bb21cc4fe47, 0x3fcbda74f5856330, // 0.97604, 0.2176 + 0x3fef38f3ac64e589, 0x3fcc0b826a7e4f63, // 0.9757, 0.2191 + 0x3fef36306b67c556, 0x3fcc3c8b8c4b9dd7, // 0.97536, 0.2206 + 0x3fef33685a3aaef0, 0x3fcc6d90535d74dc, // 0.97503, 0.22209 + 0x3fef309b794b719f, 0x3fcc9e90b824a6a9, // 0.97468, 0.22359 + 0x3fef2dc9c9089a9d, 0x3fcccf8cb312b286, // 0.97434, 0.22508 + 0x3fef2af349e17507, 0x3fcd00843c99c5f9, // 0.97399, 0.22658 + 0x3fef2817fc4609ce, 0x3fcd31774d2cbdee, // 0.97364, 0.22807 + 0x3fef2537e0a71f9f, 0x3fcd6265dd3f27e3, // 0.97329, 0.22957 + 0x3fef2252f7763ada, 0x3fcd934fe5454311, // 0.97294, 0.23106 + 0x3fef1f6941259d7a, 0x3fcdc4355db40195, // 0.97258, 0.23255 + 0x3fef1c7abe284708, 0x3fcdf5163f01099a, // 0.97223, 0.23404 + 0x3fef19876ef1f486, 0x3fce25f281a2b684, // 0.97187, 0.23553 + 0x3fef168f53f7205d, 0x3fce56ca1e101a1b, // 0.9715, 0.23702 + 0x3fef13926dad024e, 0x3fce879d0cc0fdaf, // 0.97114, 0.23851 + 0x3fef1090bc898f5f, 0x3fceb86b462de348, // 0.97077, 0.24 + 0x3fef0d8a410379c5, 0x3fcee934c2d006c7, // 0.9704, 0.24149 + 0x3fef0a7efb9230d7, 0x3fcf19f97b215f1a, // 0.97003, 0.24298 + 0x3fef076eecade0fa, 0x3fcf4ab9679c9f5c, // 0.96966, 0.24447 + 0x3fef045a14cf738c, 0x3fcf7b7480bd3801, // 0.96928, 0.24596 + 0x3fef014074708ed3, 0x3fcfac2abeff57ff, // 0.9689, 0.24744 + 0x3feefe220c0b95ec, 0x3fcfdcdc1adfedf8, // 0.96852, 0.24893 + 0x3feefafedc1ba8b7, 0x3fd006c4466e54af, // 0.96814, 0.25041 + 0x3feef7d6e51ca3c0, 0x3fd01f1806b9fdd2, // 0.96775, 0.2519 + 0x3feef4aa278b2032, 0x3fd037694a928cac, // 0.96737, 0.25338 + 0x3feef178a3e473c2, 0x3fd04fb80e37fdae, // 0.96698, 0.25487 + 0x3feeee425aa6b09a, 0x3fd068044deab002, // 0.96658, 0.25635 + 0x3feeeb074c50a544, 0x3fd0804e05eb661e, // 0.96619, 0.25783 + 0x3feee7c77961dc9e, 0x3fd09895327b465e, // 0.96579, 0.25931 + 0x3feee482e25a9dbc, 0x3fd0b0d9cfdbdb90, // 0.96539, 0.26079 + 0x3feee13987bbebdc, 0x3fd0c91bda4f158d, // 0.96499, 0.26227 + 0x3feeddeb6a078651, 0x3fd0e15b4e1749cd, // 0.96459, 0.26375 + 0x3feeda9889bfe86a, 0x3fd0f998277733f7, // 0.96418, 0.26523 + 0x3feed740e7684963, 0x3fd111d262b1f677, // 0.96378, 0.26671 + 0x3feed3e483849c51, 0x3fd12a09fc0b1b12, // 0.96337, 0.26819 + 0x3feed0835e999009, 0x3fd1423eefc69378, // 0.96295, 0.26967 + 0x3feecd1d792c8f10, 0x3fd15a713a28b9d9, // 0.96254, 0.27115 + 0x3feec9b2d3c3bf84, 0x3fd172a0d7765177, // 0.96212, 0.27262 + 0x3feec6436ee60309, 0x3fd18acdc3f4873a, // 0.9617, 0.2741 + 0x3feec2cf4b1af6b2, 0x3fd1a2f7fbe8f243, // 0.96128, 0.27557 + 0x3feebf5668eaf2ef, 0x3fd1bb1f7b999480, // 0.96086, 0.27705 + 0x3feebbd8c8df0b74, 0x3fd1d3443f4cdb3d, // 0.96043, 0.27852 + 0x3feeb8566b810f2a, 0x3fd1eb6643499fbb, // 0.96, 0.27999 + 0x3feeb4cf515b8811, 0x3fd2038583d727bd, // 0.95957, 0.28146 + 0x3feeb1437af9bb34, 0x3fd21ba1fd3d2623, // 0.95914, 0.28294 + 0x3feeadb2e8e7a88e, 0x3fd233bbabc3bb72, // 0.9587, 0.28441 + 0x3feeaa1d9bb20af3, 0x3fd24bd28bb37672, // 0.95827, 0.28588 + 0x3feea68393e65800, 0x3fd263e6995554ba, // 0.95783, 0.28735 + 0x3feea2e4d212c000, 0x3fd27bf7d0f2c346, // 0.95738, 0.28882 + 0x3fee9f4156c62dda, 0x3fd294062ed59f05, // 0.95694, 0.29028 + 0x3fee9b99229046f8, 0x3fd2ac11af483572, // 0.95649, 0.29175 + 0x3fee97ec36016b30, 0x3fd2c41a4e954520, // 0.95605, 0.29322 + 0x3fee943a91aab4b4, 0x3fd2dc200907fe51, // 0.95559, 0.29469 + 0x3fee9084361df7f3, 0x3fd2f422daec0386, // 0.95514, 0.29615 + 0x3fee8cc923edc388, 0x3fd30c22c08d6a13, // 0.95469, 0.29762 + 0x3fee89095bad6025, 0x3fd3241fb638baaf, // 0.95423, 0.29908 + 0x3fee8544ddf0d075, 0x3fd33c19b83af207, // 0.95377, 0.30054 + 0x3fee817bab4cd10d, 0x3fd35410c2e18152, // 0.95331, 0.30201 + 0x3fee7dadc456d850, 0x3fd36c04d27a4edf, // 0.95284, 0.30347 + 0x3fee79db29a5165a, 0x3fd383f5e353b6aa, // 0.95238, 0.30493 + 0x3fee7603dbce74e9, 0x3fd39be3f1bc8aef, // 0.95191, 0.30639 + 0x3fee7227db6a9744, 0x3fd3b3cefa0414b7, // 0.95144, 0.30785 + 0x3fee6e472911da27, 0x3fd3cbb6f87a146e, // 0.95096, 0.30931 + 0x3fee6a61c55d53a7, 0x3fd3e39be96ec271, // 0.95049, 0.31077 + 0x3fee6677b0e6d31e, 0x3fd3fb7dc932cfa4, // 0.95001, 0.31222 + 0x3fee6288ec48e112, 0x3fd4135c94176602, // 0.94953, 0.31368 + 0x3fee5e95781ebf1c, 0x3fd42b38466e2928, // 0.94905, 0.31514 + 0x3fee5a9d550467d3, 0x3fd44310dc8936f0, // 0.94856, 0.31659 + 0x3fee56a083968eb1, 0x3fd45ae652bb2800, // 0.94807, 0.31805 + 0x3fee529f04729ffc, 0x3fd472b8a5571054, // 0.94759, 0.3195 + 0x3fee4e98d836c0af, 0x3fd48a87d0b07fd7, // 0.94709, 0.32096 + 0x3fee4a8dff81ce5e, 0x3fd4a253d11b82f3, // 0.9466, 0.32241 + 0x3fee467e7af35f23, 0x3fd4ba1ca2eca31c, // 0.94611, 0.32386 + 0x3fee426a4b2bc17e, 0x3fd4d1e24278e76a, // 0.94561, 0.32531 + 0x3fee3e5170cbfc46, 0x3fd4e9a4ac15d520, // 0.94511, 0.32676 + 0x3fee3a33ec75ce85, 0x3fd50163dc197047, // 0.9446, 0.32821 + 0x3fee3611becbaf69, 0x3fd5191fceda3c35, // 0.9441, 0.32966 + 0x3fee31eae870ce25, 0x3fd530d880af3c24, // 0.94359, 0.33111 + 0x3fee2dbf6a0911d9, 0x3fd5488dedeff3be, // 0.94308, 0.33255 + 0x3fee298f4439197a, 0x3fd5604012f467b4, // 0.94257, 0.334 + 0x3fee255a77a63bb8, 0x3fd577eeec151e47, // 0.94206, 0.33545 + 0x3fee212104f686e5, 0x3fd58f9a75ab1fdd, // 0.94154, 0.33689 + 0x3fee1ce2ecd0c0d8, 0x3fd5a742ac0ff78d, // 0.94103, 0.33833 + 0x3fee18a02fdc66d9, 0x3fd5bee78b9db3b6, // 0.94051, 0.33978 + 0x3fee1458cec1ad83, 0x3fd5d68910aee686, // 0.93998, 0.34122 + 0x3fee100cca2980ac, 0x3fd5ee27379ea693, // 0.93946, 0.34266 + 0x3fee0bbc22bd8349, 0x3fd605c1fcc88f63, // 0.93893, 0.3441 + 0x3fee0766d9280f54, 0x3fd61d595c88c203, // 0.9384, 0.34554 + 0x3fee030cee1435b8, 0x3fd634ed533be58e, // 0.93787, 0.34698 + 0x3fedfeae622dbe2b, 0x3fd64c7ddd3f27c6, // 0.93734, 0.34842 + 0x3fedfa4b3621271d, 0x3fd6640af6f03d9e, // 0.9368, 0.34986 + 0x3fedf5e36a9ba59c, 0x3fd67b949cad63ca, // 0.93627, 0.35129 + 0x3fedf177004b2534, 0x3fd6931acad55f51, // 0.93573, 0.35273 + 0x3feded05f7de47da, 0x3fd6aa9d7dc77e16, // 0.93518, 0.35416 + 0x3fede890520465ce, 0x3fd6c21cb1e39771, // 0.93464, 0.3556 + 0x3fede4160f6d8d81, 0x3fd6d998638a0cb5, // 0.93409, 0.35703 + 0x3feddf9730ca837b, 0x3fd6f1108f1bc9c5, // 0.93354, 0.35846 + 0x3feddb13b6ccc23d, 0x3fd7088530fa459e, // 0.93299, 0.3599 + 0x3fedd68ba2267a25, 0x3fd71ff6458782ec, // 0.93244, 0.36133 + 0x3fedd1fef38a915a, 0x3fd73763c9261092, // 0.93188, 0.36276 + 0x3fedcd6dabaca3a5, 0x3fd74ecdb8390a3e, // 0.93133, 0.36418 + 0x3fedc8d7cb410260, 0x3fd766340f2418f6, // 0.93077, 0.36561 + 0x3fedc43d52fcb453, 0x3fd77d96ca4b73a6, // 0.93021, 0.36704 + 0x3fedbf9e4395759a, 0x3fd794f5e613dfae, // 0.92964, 0.36847 + 0x3fedbafa9dc1b78d, 0x3fd7ac515ee2b172, // 0.92907, 0.36989 + 0x3fedb6526238a09b, 0x3fd7c3a9311dcce7, // 0.92851, 0.37132 + 0x3fedb1a591b20c38, 0x3fd7dafd592ba621, // 0.92794, 0.37274 + 0x3fedacf42ce68ab9, 0x3fd7f24dd37341e3, // 0.92736, 0.37416 + 0x3feda83e348f613b, 0x3fd8099a9c5c362d, // 0.92679, 0.37559 + 0x3feda383a9668988, 0x3fd820e3b04eaac4, // 0.92621, 0.37701 + 0x3fed9ec48c26b1f3, 0x3fd838290bb359c8, // 0.92563, 0.37843 + 0x3fed9a00dd8b3d46, 0x3fd84f6aaaf3903f, // 0.92505, 0.37985 + 0x3fed95389e50429b, 0x3fd866a88a792ea0, // 0.92447, 0.38127 + 0x3fed906bcf328d46, 0x3fd87de2a6aea963, // 0.92388, 0.38268 + 0x3fed8b9a70ef9cb4, 0x3fd89518fbff098e, // 0.92329, 0.3841 + 0x3fed86c48445a450, 0x3fd8ac4b86d5ed44, // 0.9227, 0.38552 + 0x3fed81ea09f38b63, 0x3fd8c37a439f884f, // 0.92211, 0.38693 + 0x3fed7d0b02b8ecf9, 0x3fd8daa52ec8a4af, // 0.92151, 0.38835 + 0x3fed78276f5617c6, 0x3fd8f1cc44bea329, // 0.92092, 0.38976 + 0x3fed733f508c0dff, 0x3fd908ef81ef7bd1, // 0.92032, 0.39117 + 0x3fed6e52a71c8547, 0x3fd9200ee2c9be97, // 0.91972, 0.39258 + 0x3fed696173c9e68b, 0x3fd9372a63bc93d7, // 0.91911, 0.39399 + 0x3fed646bb7574de5, 0x3fd94e420137bce3, // 0.91851, 0.3954 + 0x3fed5f7172888a7f, 0x3fd96555b7ab948f, // 0.9179, 0.39681 + 0x3fed5a72a6221e73, 0x3fd97c6583890fc2, // 0.91729, 0.39822 + 0x3fed556f52e93eb1, 0x3fd993716141bdfe, // 0.91668, 0.39962 + 0x3fed506779a3d2d9, 0x3fd9aa794d47c9ee, // 0.91606, 0.40103 + 0x3fed4b5b1b187524, 0x3fd9c17d440df9f2, // 0.91545, 0.40243 + 0x3fed464a380e7242, 0x3fd9d87d4207b0ab, // 0.91483, 0.40384 + 0x3fed4134d14dc93a, 0x3fd9ef7943a8ed8a, // 0.91421, 0.40524 + 0x3fed3c1ae79f2b4e, 0x3fda067145664d57, // 0.91359, 0.40664 + 0x3fed36fc7bcbfbdc, 0x3fda1d6543b50ac0, // 0.91296, 0.40804 + 0x3fed31d98e9e503a, 0x3fda34553b0afee5, // 0.91234, 0.40944 + 0x3fed2cb220e0ef9f, 0x3fda4b4127dea1e4, // 0.91171, 0.41084 + 0x3fed2786335f52fc, 0x3fda622906a70b63, // 0.91107, 0.41224 + 0x3fed2255c6e5a4e1, 0x3fda790cd3dbf31a, // 0.91044, 0.41364 + 0x3fed1d20dc40c15c, 0x3fda8fec8bf5b166, // 0.90981, 0.41503 + 0x3fed17e7743e35dc, 0x3fdaa6c82b6d3fc9, // 0.90917, 0.41643 + 0x3fed12a98fac410c, 0x3fdabd9faebc3980, // 0.90853, 0.41782 + 0x3fed0d672f59d2b9, 0x3fdad473125cdc08, // 0.90789, 0.41922 + 0x3fed082054168bac, 0x3fdaeb4252ca07ab, // 0.90724, 0.42061 + 0x3fed02d4feb2bd92, 0x3fdb020d6c7f4009, // 0.9066, 0.422 + 0x3fecfd852fff6ad4, 0x3fdb18d45bf8aca6, // 0.90595, 0.42339 + 0x3fecf830e8ce467b, 0x3fdb2f971db31972, // 0.9053, 0.42478 + 0x3fecf2d829f1b40e, 0x3fdb4655ae2bf757, // 0.90464, 0.42617 + 0x3feced7af43cc773, 0x3fdb5d1009e15cc0, // 0.90399, 0.42756 + 0x3fece819488344ce, 0x3fdb73c62d520624, // 0.90333, 0.42894 + 0x3fece2b32799a060, 0x3fdb8a7814fd5693, // 0.90267, 0.43033 + 0x3fecdd489254fe65, 0x3fdba125bd63583e, // 0.90201, 0.43171 + 0x3fecd7d9898b32f6, 0x3fdbb7cf2304bd01, // 0.90135, 0.43309 + 0x3fecd2660e12c1e6, 0x3fdbce744262deee, // 0.90068, 0.43448 + 0x3fecccee20c2de9f, 0x3fdbe51517ffc0d9, // 0.90002, 0.43586 + 0x3fecc771c2736c09, 0x3fdbfbb1a05e0edc, // 0.89935, 0.43724 + 0x3fecc1f0f3fcfc5c, 0x3fdc1249d8011ee7, // 0.89867, 0.43862 + 0x3fecbc6bb638d10b, 0x3fdc28ddbb6cf145, // 0.898, 0.43999 + 0x3fecb6e20a00da99, 0x3fdc3f6d47263129, // 0.89732, 0.44137 + 0x3fecb153f02fb87d, 0x3fdc55f877b23537, // 0.89665, 0.44275 + 0x3fecabc169a0b901, 0x3fdc6c7f4997000a, // 0.89597, 0.44412 + 0x3feca62a772fd919, 0x3fdc8301b95b40c2, // 0.89528, 0.4455 + 0x3feca08f19b9c449, 0x3fdc997fc3865388, // 0.8946, 0.44687 + 0x3fec9aef521bd480, 0x3fdcaff964a0421d, // 0.89391, 0.44824 + 0x3fec954b213411f5, 0x3fdcc66e9931c45d, // 0.89322, 0.44961 + 0x3fec8fa287e13305, 0x3fdcdcdf5dc440ce, // 0.89253, 0.45098 + 0x3fec89f587029c13, 0x3fdcf34baee1cd21, // 0.89184, 0.45235 + 0x3fec84441f785f61, 0x3fdd09b389152ec1, // 0.89115, 0.45372 + 0x3fec7e8e52233cf3, 0x3fdd2016e8e9db5b, // 0.89045, 0.45508 + 0x3fec78d41fe4a267, 0x3fdd3675caebf962, // 0.88975, 0.45645 + 0x3fec7315899eaad7, 0x3fdd4cd02ba8609c, // 0.88905, 0.45781 + 0x3fec6d5290341eb2, 0x3fdd632607ac9aa9, // 0.88835, 0.45918 + 0x3fec678b3488739b, 0x3fdd79775b86e389, // 0.88764, 0.46054 + 0x3fec61bf777fcc48, 0x3fdd8fc423c62a25, // 0.88693, 0.4619 + 0x3fec5bef59fef85a, 0x3fdda60c5cfa10d8, // 0.88622, 0.46326 + 0x3fec561adceb743e, 0x3fddbc5003b2edf8, // 0.88551, 0.46462 + 0x3fec5042012b6907, 0x3fddd28f1481cc58, // 0.8848, 0.46598 + 0x3fec4a64c7a5ac4c, 0x3fdde8c98bf86bd6, // 0.88408, 0.46733 + 0x3fec44833141c004, 0x3fddfeff66a941de, // 0.88336, 0.46869 + 0x3fec3e9d3ee7d262, 0x3fde1530a12779f4, // 0.88264, 0.47004 + 0x3fec38b2f180bdb1, 0x3fde2b5d3806f63b, // 0.88192, 0.4714 + 0x3fec32c449f60831, 0x3fde418527dc4ffa, // 0.8812, 0.47275 + 0x3fec2cd14931e3f1, 0x3fde57a86d3cd824, // 0.88047, 0.4741 + 0x3fec26d9f01f2eaf, 0x3fde6dc704be97e2, // 0.87974, 0.47545 + 0x3fec20de3fa971b0, 0x3fde83e0eaf85113, // 0.87901, 0.4768 + 0x3fec1ade38bce19b, 0x3fde99f61c817eda, // 0.87828, 0.47815 + 0x3fec14d9dc465e58, 0x3fdeb00695f25620, // 0.87755, 0.47949 + 0x3fec0ed12b3372e9, 0x3fdec61253e3c61b, // 0.87681, 0.48084 + 0x3fec08c426725549, 0x3fdedc1952ef78d5, // 0.87607, 0.48218 + 0x3fec02b2cef1e641, 0x3fdef21b8fafd3b5, // 0.87533, 0.48353 + 0x3febfc9d25a1b147, 0x3fdf081906bff7fd, // 0.87459, 0.48487 + 0x3febf6832b71ec5b, 0x3fdf1e11b4bbc35c, // 0.87384, 0.48621 + 0x3febf064e15377dd, 0x3fdf3405963fd068, // 0.87309, 0.48755 + 0x3febea424837de6d, 0x3fdf49f4a7e97729, // 0.87235, 0.48889 + 0x3febe41b611154c1, 0x3fdf5fdee656cda3, // 0.8716, 0.49023 + 0x3febddf02cd2b983, 0x3fdf75c44e26a852, // 0.87084, 0.49156 + 0x3febd7c0ac6f952a, 0x3fdf8ba4dbf89aba, // 0.87009, 0.4929 + 0x3febd18ce0dc19d6, 0x3fdfa1808c6cf7e0, // 0.86933, 0.49423 + 0x3febcb54cb0d2327, 0x3fdfb7575c24d2de, // 0.86857, 0.49557 + 0x3febc5186bf8361d, 0x3fdfcd2947c1ff57, // 0.86781, 0.4969 + 0x3febbed7c49380ea, 0x3fdfe2f64be7120f, // 0.86705, 0.49823 + 0x3febb892d5d5dad5, 0x3fdff8be6537615e, // 0.86628, 0.49956 + 0x3febb249a0b6c40d, 0x3fe00740c82b82e0, // 0.86551, 0.50089 + 0x3febabfc262e6586, 0x3fe0121fe4f56d2c, // 0.86474, 0.50221 + 0x3feba5aa673590d2, 0x3fe01cfc874c3eb7, // 0.86397, 0.50354 + 0x3feb9f5464c5bffc, 0x3fe027d6ad83287e, // 0.8632, 0.50486 + 0x3feb98fa1fd9155e, 0x3fe032ae55edbd95, // 0.86242, 0.50619 + 0x3feb929b996a5b7f, 0x3fe03d837edff370, // 0.86165, 0.50751 + 0x3feb8c38d27504e9, 0x3fe0485626ae221a, // 0.86087, 0.50883 + 0x3feb85d1cbf52c02, 0x3fe053264bad0483, // 0.86009, 0.51015 + 0x3feb7f6686e792ea, 0x3fe05df3ec31b8b6, // 0.8593, 0.51147 + 0x3feb78f70449a34b, 0x3fe068bf0691c028, // 0.85852, 0.51279 + 0x3feb728345196e3e, 0x3fe073879922ffed, // 0.85773, 0.5141 + 0x3feb6c0b4a55ac17, 0x3fe07e4da23bc102, // 0.85694, 0.51542 + 0x3feb658f14fdbc47, 0x3fe089112032b08c, // 0.85615, 0.51673 + 0x3feb5f0ea611a532, 0x3fe093d2115ee018, // 0.85535, 0.51804 + 0x3feb5889fe921405, 0x3fe09e907417c5e1, // 0.85456, 0.51936 + 0x3feb52011f805c92, 0x3fe0a94c46b53d0b, // 0.85376, 0.52067 + 0x3feb4b7409de7925, 0x3fe0b405878f85ec, // 0.85296, 0.52198 + 0x3feb44e2beaf0a61, 0x3fe0bebc34ff4646, // 0.85216, 0.52328 + 0x3feb3e4d3ef55712, 0x3fe0c9704d5d898f, // 0.85136, 0.52459 + 0x3feb37b38bb54c09, 0x3fe0d421cf03c12b, // 0.85055, 0.5259 + 0x3feb3115a5f37bf4, 0x3fe0ded0b84bc4b5, // 0.84974, 0.5272 + 0x3feb2a738eb51f33, 0x3fe0e97d078fd23b, // 0.84893, 0.5285 + 0x3feb23cd470013b4, 0x3fe0f426bb2a8e7d, // 0.84812, 0.5298 + 0x3feb1d22cfdadcc6, 0x3fe0fecdd1770537, // 0.84731, 0.5311 + 0x3feb16742a4ca2f5, 0x3fe1097248d0a956, // 0.84649, 0.5324 + 0x3feb0fc1575d33db, 0x3fe114141f935545, // 0.84567, 0.5337 + 0x3feb090a58150200, 0x3fe11eb3541b4b22, // 0.84485, 0.535 + 0x3feb024f2d7d24a9, 0x3fe1294fe4c5350a, // 0.84403, 0.53629 + 0x3feafb8fd89f57b6, 0x3fe133e9cfee254e, // 0.84321, 0.53759 + 0x3feaf4cc5a85fb73, 0x3fe13e8113f396c1, // 0.84238, 0.53888 + 0x3feaee04b43c1474, 0x3fe14915af336ceb, // 0.84155, 0.54017 + 0x3feae738e6cd4b67, 0x3fe153a7a00bf453, // 0.84073, 0.54146 + 0x3feae068f345ecef, 0x3fe15e36e4dbe2bc, // 0.83989, 0.54275 + 0x3fead994dab2e979, 0x3fe168c37c025764, // 0.83906, 0.54404 + 0x3fead2bc9e21d511, 0x3fe1734d63dedb49, // 0.83822, 0.54532 + 0x3feacbe03ea0e73b, 0x3fe17dd49ad16161, // 0.83739, 0.54661 + 0x3feac4ffbd3efac8, 0x3fe188591f3a46e5, // 0.83655, 0.54789 + 0x3feabe1b1b0b8dac, 0x3fe192daef7a5386, // 0.83571, 0.54918 + 0x3feab7325916c0d4, 0x3fe19d5a09f2b9b8, // 0.83486, 0.55046 + 0x3feab045787157ff, 0x3fe1a7d66d0516e6, // 0.83402, 0.55174 + 0x3feaa9547a2cb98e, 0x3fe1b250171373be, // 0.83317, 0.55302 + 0x3feaa25f5f5aee60, 0x3fe1bcc706804467, // 0.83232, 0.55429 + 0x3fea9b66290ea1a3, 0x3fe1c73b39ae68c8, // 0.83147, 0.55557 + 0x3fea9468d85b20ae, 0x3fe1d1acaf012cc2, // 0.83062, 0.55685 + 0x3fea8d676e545ad2, 0x3fe1dc1b64dc4872, // 0.82976, 0.55812 + 0x3fea8661ec0ee133, 0x3fe1e68759a3e074, // 0.8289, 0.55939 + 0x3fea7f58529fe69d, 0x3fe1f0f08bbc861b, // 0.82805, 0.56066 + 0x3fea784aa31d3f55, 0x3fe1fb56f98b37b8, // 0.82718, 0.56193 + 0x3fea7138de9d60f5, 0x3fe205baa17560d6, // 0.82632, 0.5632 + 0x3fea6a230637623b, 0x3fe2101b81e0da78, // 0.82546, 0.56447 + 0x3fea63091b02fae2, 0x3fe21a799933eb58, // 0.82459, 0.56573 + 0x3fea5beb1e188375, 0x3fe224d4e5d5482e, // 0.82372, 0.567 + 0x3fea54c91090f524, 0x3fe22f2d662c13e1, // 0.82285, 0.56826 + 0x3fea4da2f385e997, 0x3fe23983189fdfd5, // 0.82198, 0.56952 + 0x3fea4678c8119ac8, 0x3fe243d5fb98ac1f, // 0.8211, 0.57078 + 0x3fea3f4a8f4ee2d2, 0x3fe24e260d7ee7c9, // 0.82023, 0.57204 + 0x3fea38184a593bc6, 0x3fe258734cbb7110, // 0.81935, 0.5733 + 0x3fea30e1fa4cbf81, 0x3fe262bdb7b795a2, // 0.81847, 0.57455 + 0x3fea29a7a0462782, 0x3fe26d054cdd12df, // 0.81758, 0.57581 + 0x3fea22693d62ccb9, 0x3fe2774a0a961612, // 0.8167, 0.57706 + 0x3fea1b26d2c0a75e, 0x3fe2818bef4d3cba, // 0.81581, 0.57831 + 0x3fea13e0617e4ec7, 0x3fe28bcaf96d94ba, // 0.81493, 0.57956 + 0x3fea0c95eabaf937, 0x3fe2960727629ca8, // 0.81404, 0.58081 + 0x3fea05476f967bb5, 0x3fe2a040779843fb, // 0.81314, 0.58206 + 0x3fe9fdf4f13149de, 0x3fe2aa76e87aeb58, // 0.81225, 0.58331 + 0x3fe9f69e70ac75bc, 0x3fe2b4aa787764c4, // 0.81135, 0.58455 + 0x3fe9ef43ef29af94, 0x3fe2bedb25faf3ea, // 0.81046, 0.5858 + 0x3fe9e7e56dcb45bd, 0x3fe2c908ef734e57, // 0.80956, 0.58704 + 0x3fe9e082edb42472, 0x3fe2d333d34e9bb7, // 0.80866, 0.58828 + 0x3fe9d91c7007d5a6, 0x3fe2dd5bcffb7616, // 0.80775, 0.58952 + 0x3fe9d1b1f5ea80d6, 0x3fe2e780e3e8ea16, // 0.80685, 0.59076 + 0x3fe9ca438080eadb, 0x3fe2f1a30d86773a, // 0.80594, 0.592 + 0x3fe9c2d110f075c3, 0x3fe2fbc24b441015, // 0.80503, 0.59323 + 0x3fe9bb5aa85f2098, 0x3fe305de9b921a94, // 0.80412, 0.59447 + 0x3fe9b3e047f38741, 0x3fe30ff7fce17035, // 0.80321, 0.5957 + 0x3fe9ac61f0d4e247, 0x3fe31a0e6da35e44, // 0.80229, 0.59693 + 0x3fe9a4dfa42b06b2, 0x3fe32421ec49a620, // 0.80138, 0.59816 + 0x3fe99d59631e65d5, 0x3fe32e3277467d6b, // 0.80046, 0.59939 + 0x3fe995cf2ed80d22, 0x3fe338400d0c8e57, // 0.79954, 0.60062 + 0x3fe98e410881a600, 0x3fe3424aac0ef7d6, // 0.79861, 0.60184 + 0x3fe986aef1457594, 0x3fe34c5252c14de1, // 0.79769, 0.60307 + 0x3fe97f18ea4e5c9e, 0x3fe35656ff9799ae, // 0.79676, 0.60429 + 0x3fe9777ef4c7d742, 0x3fe36058b10659f3, // 0.79584, 0.60551 + 0x3fe96fe111ddfce0, 0x3fe36a576582831b, // 0.79491, 0.60673 + 0x3fe9683f42bd7fe1, 0x3fe374531b817f8d, // 0.79398, 0.60795 + 0x3fe960998893ad8c, 0x3fe37e4bd1792fe2, // 0.79304, 0.60917 + 0x3fe958efe48e6dd7, 0x3fe3884185dfeb22, // 0.79211, 0.61038 + 0x3fe9514257dc4335, 0x3fe39234372c7f04, // 0.79117, 0.6116 + 0x3fe94990e3ac4a6c, 0x3fe39c23e3d63029, // 0.79023, 0.61281 + 0x3fe941db892e3a65, 0x3fe3a6108a54ba58, // 0.78929, 0.61402 + 0x3fe93a22499263fc, 0x3fe3affa292050b9, // 0.78835, 0.61523 + 0x3fe932652609b1cf, 0x3fe3b9e0beb19e18, // 0.7874, 0.61644 + 0x3fe92aa41fc5a815, 0x3fe3c3c44981c517, // 0.78646, 0.61765 + 0x3fe922df37f8646a, 0x3fe3cda4c80a6076, // 0.78551, 0.61885 + 0x3fe91b166fd49da2, 0x3fe3d78238c58343, // 0.78456, 0.62006 + 0x3fe91349c88da398, 0x3fe3e15c9a2db922, // 0.7836, 0.62126 + 0x3fe90b7943575efe, 0x3fe3eb33eabe0680, // 0.78265, 0.62246 + 0x3fe903a4e1665133, 0x3fe3f50828f1e8d2, // 0.78169, 0.62366 + 0x3fe8fbcca3ef940d, 0x3fe3fed9534556d4, // 0.78074, 0.62486 + 0x3fe8f3f08c28d9ac, 0x3fe408a76834c0c0, // 0.77978, 0.62606 + 0x3fe8ec109b486c49, 0x3fe41272663d108c, // 0.77882, 0.62725 + 0x3fe8e42cd2852e0a, 0x3fe41c3a4bdbaa26, // 0.77785, 0.62845 + 0x3fe8dc45331698cc, 0x3fe425ff178e6bb1, // 0.77689, 0.62964 + 0x3fe8d459be34bdfa, 0x3fe42fc0c7d3adbb, // 0.77592, 0.63083 + 0x3fe8cc6a75184655, 0x3fe4397f5b2a4380, // 0.77495, 0.63202 + 0x3fe8c47758fa71cb, 0x3fe4433ad0117b1d, // 0.77398, 0.63321 + 0x3fe8bc806b151741, 0x3fe44cf325091dd6, // 0.77301, 0.63439 + 0x3fe8b485aca2a468, 0x3fe456a858917046, // 0.77204, 0.63558 + 0x3fe8ac871ede1d88, 0x3fe4605a692b32a2, // 0.77106, 0.63676 + 0x3fe8a484c3031d50, 0x3fe46a095557a0f1, // 0.77008, 0.63794 + 0x3fe89c7e9a4dd4ab, 0x3fe473b51b987347, // 0.7691, 0.63912 + 0x3fe89474a5fb0a84, 0x3fe47d5dba6fde01, // 0.76812, 0.6403 + 0x3fe88c66e7481ba1, 0x3fe48703306091fe, // 0.76714, 0.64148 + 0x3fe884555f72fa6b, 0x3fe490a57bedbcdf, // 0.76615, 0.64266 + 0x3fe87c400fba2ebf, 0x3fe49a449b9b0938, // 0.76517, 0.64383 + 0x3fe87426f95cd5bd, 0x3fe4a3e08dec9ed6, // 0.76418, 0.645 + 0x3fe86c0a1d9aa195, 0x3fe4ad79516722f0, // 0.76319, 0.64618 + 0x3fe863e97db3d95a, 0x3fe4b70ee48fb869, // 0.7622, 0.64735 + 0x3fe85bc51ae958cc, 0x3fe4c0a145ec0004, // 0.7612, 0.64851 + 0x3fe8539cf67c9029, 0x3fe4ca30740218a3, // 0.76021, 0.64968 + 0x3fe84b7111af83f9, 0x3fe4d3bc6d589f80, // 0.75921, 0.65085 + 0x3fe843416dc4cce2, 0x3fe4dd453076b064, // 0.75821, 0.65201 + 0x3fe83b0e0bff976e, 0x3fe4e6cabbe3e5e9, // 0.75721, 0.65317 + 0x3fe832d6eda3a3e0, 0x3fe4f04d0e2859aa, // 0.75621, 0.65433 + 0x3fe82a9c13f545ff, 0x3fe4f9cc25cca486, // 0.7552, 0.65549 + 0x3fe8225d803964e5, 0x3fe503480159ded2, // 0.75419, 0.65665 + 0x3fe81a1b33b57acc, 0x3fe50cc09f59a09b, // 0.75319, 0.65781 + 0x3fe811d52faf94dc, 0x3fe51635fe5601d7, // 0.75218, 0.65896 + 0x3fe8098b756e52fa, 0x3fe51fa81cd99aa6, // 0.75117, 0.66011 + 0x3fe8013e0638e795, 0x3fe52916f96f8388, // 0.75015, 0.66127 + 0x3fe7f8ece3571771, 0x3fe5328292a35596, // 0.74914, 0.66242 + 0x3fe7f0980e113978, 0x3fe53beae7012abe, // 0.74812, 0.66356 + 0x3fe7e83f87b03686, 0x3fe5454ff5159dfb, // 0.7471, 0.66471 + 0x3fe7dfe3517d8937, 0x3fe54eb1bb6dcb8f, // 0.74608, 0.66586 + 0x3fe7d7836cc33db2, 0x3fe5581038975137, // 0.74506, 0.667 + 0x3fe7cf1fdacbf179, 0x3fe5616b6b204e6e, // 0.74403, 0.66814 + 0x3fe7c6b89ce2d333, 0x3fe56ac35197649e, // 0.74301, 0.66928 + 0x3fe7be4db453a27c, 0x3fe57417ea8bb75c, // 0.74198, 0.67042 + 0x3fe7b5df226aafb0, 0x3fe57d69348cec9f, // 0.74095, 0.67156 + 0x3fe7ad6ce874dbb6, 0x3fe586b72e2b2cfd, // 0.73992, 0.67269 + 0x3fe7a4f707bf97d2, 0x3fe59001d5f723df, // 0.73889, 0.67383 + 0x3fe79c7d8198e56e, 0x3fe599492a81ffbc, // 0.73785, 0.67496 + 0x3fe79400574f55e4, 0x3fe5a28d2a5d7250, // 0.73682, 0.67609 + 0x3fe78b7f8a320a52, 0x3fe5abcdd41bb0d8, // 0.73578, 0.67722 + 0x3fe782fb1b90b35b, 0x3fe5b50b264f7448, // 0.73474, 0.67835 + 0x3fe77a730cbb9100, 0x3fe5be451f8bf980, // 0.7337, 0.67948 + 0x3fe771e75f037261, 0x3fe5c77bbe65018c, // 0.73265, 0.6806 + 0x3fe7695813b9b594, 0x3fe5d0af016ed1d4, // 0.73161, 0.68172 + 0x3fe760c52c304764, 0x3fe5d9dee73e345c, // 0.73056, 0.68285 + 0x3fe7582ea9b9a329, 0x3fe5e30b6e6877f3, // 0.72951, 0.68397 + 0x3fe74f948da8d28d, 0x3fe5ec3495837074, // 0.72846, 0.68508 + 0x3fe746f6d9516d59, 0x3fe5f55a5b2576f8, // 0.72741, 0.6862 + 0x3fe73e558e079942, 0x3fe5fe7cbde56a0f, // 0.72636, 0.68732 + 0x3fe735b0ad2009b2, 0x3fe6079bbc5aadfa, // 0.7253, 0.68843 + 0x3fe72d0837efff97, 0x3fe610b7551d2cde, // 0.72425, 0.68954 + 0x3fe7245c2fcd492a, 0x3fe619cf86c55702, // 0.72319, 0.69065 + 0x3fe71bac960e41bf, 0x3fe622e44fec22ff, // 0.72213, 0.69176 + 0x3fe712f96c09d18d, 0x3fe62bf5af2b0dfd, // 0.72107, 0.69287 + 0x3fe70a42b3176d7a, 0x3fe63503a31c1be8, // 0.72, 0.69397 + 0x3fe701886c8f16e6, 0x3fe63e0e2a59d7aa, // 0.71894, 0.69508 + 0x3fe6f8ca99c95b75, 0x3fe64715437f535b, // 0.71787, 0.69618 + 0x3fe6f0093c1f54de, 0x3fe65018ed28287f, // 0.7168, 0.69728 + 0x3fe6e74454eaa8ae, 0x3fe6591925f0783e, // 0.71573, 0.69838 + 0x3fe6de7be585881d, 0x3fe66215ec74eb91, // 0.71466, 0.69947 + 0x3fe6d5afef4aafcc, 0x3fe66b0f3f52b386, // 0.71358, 0.70057 + 0x3fe6cce07395679f, 0x3fe674051d27896c, // 0.71251, 0.70166 + 0x3fe6c40d73c18275, 0x3fe67cf78491af10, // 0.71143, 0.70275 + 0x3fe6bb36f12b5e06, 0x3fe685e6742feeef, // 0.71035, 0.70385 + 0x3fe6b25ced2fe29c, 0x3fe68ed1eaa19c71, // 0.70927, 0.70493 + 0x3fe6a97f692c82ea, 0x3fe697b9e686941c, // 0.70819, 0.70602 + 0x3fe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // 0.70711, 0.70711 + 0x3fe697b9e686941c, 0x3fe6a97f692c82ea, // 0.70602, 0.70819 + 0x3fe68ed1eaa19c71, 0x3fe6b25ced2fe29c, // 0.70493, 0.70927 + 0x3fe685e6742feeef, 0x3fe6bb36f12b5e06, // 0.70385, 0.71035 + 0x3fe67cf78491af10, 0x3fe6c40d73c18275, // 0.70275, 0.71143 + 0x3fe674051d27896c, 0x3fe6cce07395679f, // 0.70166, 0.71251 + 0x3fe66b0f3f52b386, 0x3fe6d5afef4aafcc, // 0.70057, 0.71358 + 0x3fe66215ec74eb91, 0x3fe6de7be585881d, // 0.69947, 0.71466 + 0x3fe6591925f0783e, 0x3fe6e74454eaa8ae, // 0.69838, 0.71573 + 0x3fe65018ed28287f, 0x3fe6f0093c1f54de, // 0.69728, 0.7168 + 0x3fe64715437f535b, 0x3fe6f8ca99c95b75, // 0.69618, 0.71787 + 0x3fe63e0e2a59d7aa, 0x3fe701886c8f16e6, // 0.69508, 0.71894 + 0x3fe63503a31c1be8, 0x3fe70a42b3176d7a, // 0.69397, 0.72 + 0x3fe62bf5af2b0dfd, 0x3fe712f96c09d18d, // 0.69287, 0.72107 + 0x3fe622e44fec22ff, 0x3fe71bac960e41bf, // 0.69176, 0.72213 + 0x3fe619cf86c55702, 0x3fe7245c2fcd492a, // 0.69065, 0.72319 + 0x3fe610b7551d2cde, 0x3fe72d0837efff97, // 0.68954, 0.72425 + 0x3fe6079bbc5aadfa, 0x3fe735b0ad2009b2, // 0.68843, 0.7253 + 0x3fe5fe7cbde56a0f, 0x3fe73e558e079942, // 0.68732, 0.72636 + 0x3fe5f55a5b2576f8, 0x3fe746f6d9516d59, // 0.6862, 0.72741 + 0x3fe5ec3495837074, 0x3fe74f948da8d28d, // 0.68508, 0.72846 + 0x3fe5e30b6e6877f3, 0x3fe7582ea9b9a329, // 0.68397, 0.72951 + 0x3fe5d9dee73e345c, 0x3fe760c52c304764, // 0.68285, 0.73056 + 0x3fe5d0af016ed1d4, 0x3fe7695813b9b594, // 0.68172, 0.73161 + 0x3fe5c77bbe65018c, 0x3fe771e75f037261, // 0.6806, 0.73265 + 0x3fe5be451f8bf980, 0x3fe77a730cbb9100, // 0.67948, 0.7337 + 0x3fe5b50b264f7448, 0x3fe782fb1b90b35b, // 0.67835, 0.73474 + 0x3fe5abcdd41bb0d8, 0x3fe78b7f8a320a52, // 0.67722, 0.73578 + 0x3fe5a28d2a5d7250, 0x3fe79400574f55e4, // 0.67609, 0.73682 + 0x3fe599492a81ffbc, 0x3fe79c7d8198e56e, // 0.67496, 0.73785 + 0x3fe59001d5f723df, 0x3fe7a4f707bf97d2, // 0.67383, 0.73889 + 0x3fe586b72e2b2cfd, 0x3fe7ad6ce874dbb6, // 0.67269, 0.73992 + 0x3fe57d69348cec9f, 0x3fe7b5df226aafb0, // 0.67156, 0.74095 + 0x3fe57417ea8bb75c, 0x3fe7be4db453a27c, // 0.67042, 0.74198 + 0x3fe56ac35197649e, 0x3fe7c6b89ce2d333, // 0.66928, 0.74301 + 0x3fe5616b6b204e6e, 0x3fe7cf1fdacbf179, // 0.66814, 0.74403 + 0x3fe5581038975137, 0x3fe7d7836cc33db2, // 0.667, 0.74506 + 0x3fe54eb1bb6dcb8f, 0x3fe7dfe3517d8937, // 0.66586, 0.74608 + 0x3fe5454ff5159dfb, 0x3fe7e83f87b03686, // 0.66471, 0.7471 + 0x3fe53beae7012abe, 0x3fe7f0980e113978, // 0.66356, 0.74812 + 0x3fe5328292a35596, 0x3fe7f8ece3571771, // 0.66242, 0.74914 + 0x3fe52916f96f8388, 0x3fe8013e0638e795, // 0.66127, 0.75015 + 0x3fe51fa81cd99aa6, 0x3fe8098b756e52fa, // 0.66011, 0.75117 + 0x3fe51635fe5601d7, 0x3fe811d52faf94dc, // 0.65896, 0.75218 + 0x3fe50cc09f59a09b, 0x3fe81a1b33b57acc, // 0.65781, 0.75319 + 0x3fe503480159ded2, 0x3fe8225d803964e5, // 0.65665, 0.75419 + 0x3fe4f9cc25cca486, 0x3fe82a9c13f545ff, // 0.65549, 0.7552 + 0x3fe4f04d0e2859aa, 0x3fe832d6eda3a3e0, // 0.65433, 0.75621 + 0x3fe4e6cabbe3e5e9, 0x3fe83b0e0bff976e, // 0.65317, 0.75721 + 0x3fe4dd453076b064, 0x3fe843416dc4cce2, // 0.65201, 0.75821 + 0x3fe4d3bc6d589f80, 0x3fe84b7111af83f9, // 0.65085, 0.75921 + 0x3fe4ca30740218a3, 0x3fe8539cf67c9029, // 0.64968, 0.76021 + 0x3fe4c0a145ec0004, 0x3fe85bc51ae958cc, // 0.64851, 0.7612 + 0x3fe4b70ee48fb869, 0x3fe863e97db3d95a, // 0.64735, 0.7622 + 0x3fe4ad79516722f0, 0x3fe86c0a1d9aa195, // 0.64618, 0.76319 + 0x3fe4a3e08dec9ed6, 0x3fe87426f95cd5bd, // 0.645, 0.76418 + 0x3fe49a449b9b0938, 0x3fe87c400fba2ebf, // 0.64383, 0.76517 + 0x3fe490a57bedbcdf, 0x3fe884555f72fa6b, // 0.64266, 0.76615 + 0x3fe48703306091fe, 0x3fe88c66e7481ba1, // 0.64148, 0.76714 + 0x3fe47d5dba6fde01, 0x3fe89474a5fb0a84, // 0.6403, 0.76812 + 0x3fe473b51b987347, 0x3fe89c7e9a4dd4ab, // 0.63912, 0.7691 + 0x3fe46a095557a0f1, 0x3fe8a484c3031d50, // 0.63794, 0.77008 + 0x3fe4605a692b32a2, 0x3fe8ac871ede1d88, // 0.63676, 0.77106 + 0x3fe456a858917046, 0x3fe8b485aca2a468, // 0.63558, 0.77204 + 0x3fe44cf325091dd6, 0x3fe8bc806b151741, // 0.63439, 0.77301 + 0x3fe4433ad0117b1d, 0x3fe8c47758fa71cb, // 0.63321, 0.77398 + 0x3fe4397f5b2a4380, 0x3fe8cc6a75184655, // 0.63202, 0.77495 + 0x3fe42fc0c7d3adbb, 0x3fe8d459be34bdfa, // 0.63083, 0.77592 + 0x3fe425ff178e6bb1, 0x3fe8dc45331698cc, // 0.62964, 0.77689 + 0x3fe41c3a4bdbaa26, 0x3fe8e42cd2852e0a, // 0.62845, 0.77785 + 0x3fe41272663d108c, 0x3fe8ec109b486c49, // 0.62725, 0.77882 + 0x3fe408a76834c0c0, 0x3fe8f3f08c28d9ac, // 0.62606, 0.77978 + 0x3fe3fed9534556d4, 0x3fe8fbcca3ef940d, // 0.62486, 0.78074 + 0x3fe3f50828f1e8d2, 0x3fe903a4e1665133, // 0.62366, 0.78169 + 0x3fe3eb33eabe0680, 0x3fe90b7943575efe, // 0.62246, 0.78265 + 0x3fe3e15c9a2db922, 0x3fe91349c88da398, // 0.62126, 0.7836 + 0x3fe3d78238c58343, 0x3fe91b166fd49da2, // 0.62006, 0.78456 + 0x3fe3cda4c80a6076, 0x3fe922df37f8646a, // 0.61885, 0.78551 + 0x3fe3c3c44981c517, 0x3fe92aa41fc5a815, // 0.61765, 0.78646 + 0x3fe3b9e0beb19e18, 0x3fe932652609b1cf, // 0.61644, 0.7874 + 0x3fe3affa292050b9, 0x3fe93a22499263fc, // 0.61523, 0.78835 + 0x3fe3a6108a54ba58, 0x3fe941db892e3a65, // 0.61402, 0.78929 + 0x3fe39c23e3d63029, 0x3fe94990e3ac4a6c, // 0.61281, 0.79023 + 0x3fe39234372c7f04, 0x3fe9514257dc4335, // 0.6116, 0.79117 + 0x3fe3884185dfeb22, 0x3fe958efe48e6dd7, // 0.61038, 0.79211 + 0x3fe37e4bd1792fe2, 0x3fe960998893ad8c, // 0.60917, 0.79304 + 0x3fe374531b817f8d, 0x3fe9683f42bd7fe1, // 0.60795, 0.79398 + 0x3fe36a576582831b, 0x3fe96fe111ddfce0, // 0.60673, 0.79491 + 0x3fe36058b10659f3, 0x3fe9777ef4c7d742, // 0.60551, 0.79584 + 0x3fe35656ff9799ae, 0x3fe97f18ea4e5c9e, // 0.60429, 0.79676 + 0x3fe34c5252c14de1, 0x3fe986aef1457594, // 0.60307, 0.79769 + 0x3fe3424aac0ef7d6, 0x3fe98e410881a600, // 0.60184, 0.79861 + 0x3fe338400d0c8e57, 0x3fe995cf2ed80d22, // 0.60062, 0.79954 + 0x3fe32e3277467d6b, 0x3fe99d59631e65d5, // 0.59939, 0.80046 + 0x3fe32421ec49a620, 0x3fe9a4dfa42b06b2, // 0.59816, 0.80138 + 0x3fe31a0e6da35e44, 0x3fe9ac61f0d4e247, // 0.59693, 0.80229 + 0x3fe30ff7fce17035, 0x3fe9b3e047f38741, // 0.5957, 0.80321 + 0x3fe305de9b921a94, 0x3fe9bb5aa85f2098, // 0.59447, 0.80412 + 0x3fe2fbc24b441015, 0x3fe9c2d110f075c3, // 0.59323, 0.80503 + 0x3fe2f1a30d86773a, 0x3fe9ca438080eadb, // 0.592, 0.80594 + 0x3fe2e780e3e8ea16, 0x3fe9d1b1f5ea80d6, // 0.59076, 0.80685 + 0x3fe2dd5bcffb7616, 0x3fe9d91c7007d5a6, // 0.58952, 0.80775 + 0x3fe2d333d34e9bb7, 0x3fe9e082edb42472, // 0.58828, 0.80866 + 0x3fe2c908ef734e57, 0x3fe9e7e56dcb45bd, // 0.58704, 0.80956 + 0x3fe2bedb25faf3ea, 0x3fe9ef43ef29af94, // 0.5858, 0.81046 + 0x3fe2b4aa787764c4, 0x3fe9f69e70ac75bc, // 0.58455, 0.81135 + 0x3fe2aa76e87aeb58, 0x3fe9fdf4f13149de, // 0.58331, 0.81225 + 0x3fe2a040779843fb, 0x3fea05476f967bb5, // 0.58206, 0.81314 + 0x3fe2960727629ca8, 0x3fea0c95eabaf937, // 0.58081, 0.81404 + 0x3fe28bcaf96d94ba, 0x3fea13e0617e4ec7, // 0.57956, 0.81493 + 0x3fe2818bef4d3cba, 0x3fea1b26d2c0a75e, // 0.57831, 0.81581 + 0x3fe2774a0a961612, 0x3fea22693d62ccb9, // 0.57706, 0.8167 + 0x3fe26d054cdd12df, 0x3fea29a7a0462782, // 0.57581, 0.81758 + 0x3fe262bdb7b795a2, 0x3fea30e1fa4cbf81, // 0.57455, 0.81847 + 0x3fe258734cbb7110, 0x3fea38184a593bc6, // 0.5733, 0.81935 + 0x3fe24e260d7ee7c9, 0x3fea3f4a8f4ee2d2, // 0.57204, 0.82023 + 0x3fe243d5fb98ac1f, 0x3fea4678c8119ac8, // 0.57078, 0.8211 + 0x3fe23983189fdfd5, 0x3fea4da2f385e997, // 0.56952, 0.82198 + 0x3fe22f2d662c13e1, 0x3fea54c91090f524, // 0.56826, 0.82285 + 0x3fe224d4e5d5482e, 0x3fea5beb1e188375, // 0.567, 0.82372 + 0x3fe21a799933eb58, 0x3fea63091b02fae2, // 0.56573, 0.82459 + 0x3fe2101b81e0da78, 0x3fea6a230637623b, // 0.56447, 0.82546 + 0x3fe205baa17560d6, 0x3fea7138de9d60f5, // 0.5632, 0.82632 + 0x3fe1fb56f98b37b8, 0x3fea784aa31d3f55, // 0.56193, 0.82718 + 0x3fe1f0f08bbc861b, 0x3fea7f58529fe69d, // 0.56066, 0.82805 + 0x3fe1e68759a3e074, 0x3fea8661ec0ee133, // 0.55939, 0.8289 + 0x3fe1dc1b64dc4872, 0x3fea8d676e545ad2, // 0.55812, 0.82976 + 0x3fe1d1acaf012cc2, 0x3fea9468d85b20ae, // 0.55685, 0.83062 + 0x3fe1c73b39ae68c8, 0x3fea9b66290ea1a3, // 0.55557, 0.83147 + 0x3fe1bcc706804467, 0x3feaa25f5f5aee60, // 0.55429, 0.83232 + 0x3fe1b250171373be, 0x3feaa9547a2cb98e, // 0.55302, 0.83317 + 0x3fe1a7d66d0516e6, 0x3feab045787157ff, // 0.55174, 0.83402 + 0x3fe19d5a09f2b9b8, 0x3feab7325916c0d4, // 0.55046, 0.83486 + 0x3fe192daef7a5386, 0x3feabe1b1b0b8dac, // 0.54918, 0.83571 + 0x3fe188591f3a46e5, 0x3feac4ffbd3efac8, // 0.54789, 0.83655 + 0x3fe17dd49ad16161, 0x3feacbe03ea0e73b, // 0.54661, 0.83739 + 0x3fe1734d63dedb49, 0x3fead2bc9e21d511, // 0.54532, 0.83822 + 0x3fe168c37c025764, 0x3fead994dab2e979, // 0.54404, 0.83906 + 0x3fe15e36e4dbe2bc, 0x3feae068f345ecef, // 0.54275, 0.83989 + 0x3fe153a7a00bf453, 0x3feae738e6cd4b67, // 0.54146, 0.84073 + 0x3fe14915af336ceb, 0x3feaee04b43c1474, // 0.54017, 0.84155 + 0x3fe13e8113f396c1, 0x3feaf4cc5a85fb73, // 0.53888, 0.84238 + 0x3fe133e9cfee254e, 0x3feafb8fd89f57b6, // 0.53759, 0.84321 + 0x3fe1294fe4c5350a, 0x3feb024f2d7d24a9, // 0.53629, 0.84403 + 0x3fe11eb3541b4b22, 0x3feb090a58150200, // 0.535, 0.84485 + 0x3fe114141f935545, 0x3feb0fc1575d33db, // 0.5337, 0.84567 + 0x3fe1097248d0a956, 0x3feb16742a4ca2f5, // 0.5324, 0.84649 + 0x3fe0fecdd1770537, 0x3feb1d22cfdadcc6, // 0.5311, 0.84731 + 0x3fe0f426bb2a8e7d, 0x3feb23cd470013b4, // 0.5298, 0.84812 + 0x3fe0e97d078fd23b, 0x3feb2a738eb51f33, // 0.5285, 0.84893 + 0x3fe0ded0b84bc4b5, 0x3feb3115a5f37bf4, // 0.5272, 0.84974 + 0x3fe0d421cf03c12b, 0x3feb37b38bb54c09, // 0.5259, 0.85055 + 0x3fe0c9704d5d898f, 0x3feb3e4d3ef55712, // 0.52459, 0.85136 + 0x3fe0bebc34ff4646, 0x3feb44e2beaf0a61, // 0.52328, 0.85216 + 0x3fe0b405878f85ec, 0x3feb4b7409de7925, // 0.52198, 0.85296 + 0x3fe0a94c46b53d0b, 0x3feb52011f805c92, // 0.52067, 0.85376 + 0x3fe09e907417c5e1, 0x3feb5889fe921405, // 0.51936, 0.85456 + 0x3fe093d2115ee018, 0x3feb5f0ea611a532, // 0.51804, 0.85535 + 0x3fe089112032b08c, 0x3feb658f14fdbc47, // 0.51673, 0.85615 + 0x3fe07e4da23bc102, 0x3feb6c0b4a55ac17, // 0.51542, 0.85694 + 0x3fe073879922ffed, 0x3feb728345196e3e, // 0.5141, 0.85773 + 0x3fe068bf0691c028, 0x3feb78f70449a34b, // 0.51279, 0.85852 + 0x3fe05df3ec31b8b6, 0x3feb7f6686e792ea, // 0.51147, 0.8593 + 0x3fe053264bad0483, 0x3feb85d1cbf52c02, // 0.51015, 0.86009 + 0x3fe0485626ae221a, 0x3feb8c38d27504e9, // 0.50883, 0.86087 + 0x3fe03d837edff370, 0x3feb929b996a5b7f, // 0.50751, 0.86165 + 0x3fe032ae55edbd95, 0x3feb98fa1fd9155e, // 0.50619, 0.86242 + 0x3fe027d6ad83287e, 0x3feb9f5464c5bffc, // 0.50486, 0.8632 + 0x3fe01cfc874c3eb7, 0x3feba5aa673590d2, // 0.50354, 0.86397 + 0x3fe0121fe4f56d2c, 0x3febabfc262e6586, // 0.50221, 0.86474 + 0x3fe00740c82b82e0, 0x3febb249a0b6c40d, // 0.50089, 0.86551 + 0x3fdff8be6537615e, 0x3febb892d5d5dad5, // 0.49956, 0.86628 + 0x3fdfe2f64be7120f, 0x3febbed7c49380ea, // 0.49823, 0.86705 + 0x3fdfcd2947c1ff57, 0x3febc5186bf8361d, // 0.4969, 0.86781 + 0x3fdfb7575c24d2de, 0x3febcb54cb0d2327, // 0.49557, 0.86857 + 0x3fdfa1808c6cf7e0, 0x3febd18ce0dc19d6, // 0.49423, 0.86933 + 0x3fdf8ba4dbf89aba, 0x3febd7c0ac6f952a, // 0.4929, 0.87009 + 0x3fdf75c44e26a852, 0x3febddf02cd2b983, // 0.49156, 0.87084 + 0x3fdf5fdee656cda3, 0x3febe41b611154c1, // 0.49023, 0.8716 + 0x3fdf49f4a7e97729, 0x3febea424837de6d, // 0.48889, 0.87235 + 0x3fdf3405963fd068, 0x3febf064e15377dd, // 0.48755, 0.87309 + 0x3fdf1e11b4bbc35c, 0x3febf6832b71ec5b, // 0.48621, 0.87384 + 0x3fdf081906bff7fd, 0x3febfc9d25a1b147, // 0.48487, 0.87459 + 0x3fdef21b8fafd3b5, 0x3fec02b2cef1e641, // 0.48353, 0.87533 + 0x3fdedc1952ef78d5, 0x3fec08c426725549, // 0.48218, 0.87607 + 0x3fdec61253e3c61b, 0x3fec0ed12b3372e9, // 0.48084, 0.87681 + 0x3fdeb00695f25620, 0x3fec14d9dc465e58, // 0.47949, 0.87755 + 0x3fde99f61c817eda, 0x3fec1ade38bce19b, // 0.47815, 0.87828 + 0x3fde83e0eaf85113, 0x3fec20de3fa971b0, // 0.4768, 0.87901 + 0x3fde6dc704be97e2, 0x3fec26d9f01f2eaf, // 0.47545, 0.87974 + 0x3fde57a86d3cd824, 0x3fec2cd14931e3f1, // 0.4741, 0.88047 + 0x3fde418527dc4ffa, 0x3fec32c449f60831, // 0.47275, 0.8812 + 0x3fde2b5d3806f63b, 0x3fec38b2f180bdb1, // 0.4714, 0.88192 + 0x3fde1530a12779f4, 0x3fec3e9d3ee7d262, // 0.47004, 0.88264 + 0x3fddfeff66a941de, 0x3fec44833141c004, // 0.46869, 0.88336 + 0x3fdde8c98bf86bd6, 0x3fec4a64c7a5ac4c, // 0.46733, 0.88408 + 0x3fddd28f1481cc58, 0x3fec5042012b6907, // 0.46598, 0.8848 + 0x3fddbc5003b2edf8, 0x3fec561adceb743e, // 0.46462, 0.88551 + 0x3fdda60c5cfa10d8, 0x3fec5bef59fef85a, // 0.46326, 0.88622 + 0x3fdd8fc423c62a25, 0x3fec61bf777fcc48, // 0.4619, 0.88693 + 0x3fdd79775b86e389, 0x3fec678b3488739b, // 0.46054, 0.88764 + 0x3fdd632607ac9aa9, 0x3fec6d5290341eb2, // 0.45918, 0.88835 + 0x3fdd4cd02ba8609c, 0x3fec7315899eaad7, // 0.45781, 0.88905 + 0x3fdd3675caebf962, 0x3fec78d41fe4a267, // 0.45645, 0.88975 + 0x3fdd2016e8e9db5b, 0x3fec7e8e52233cf3, // 0.45508, 0.89045 + 0x3fdd09b389152ec1, 0x3fec84441f785f61, // 0.45372, 0.89115 + 0x3fdcf34baee1cd21, 0x3fec89f587029c13, // 0.45235, 0.89184 + 0x3fdcdcdf5dc440ce, 0x3fec8fa287e13305, // 0.45098, 0.89253 + 0x3fdcc66e9931c45d, 0x3fec954b213411f5, // 0.44961, 0.89322 + 0x3fdcaff964a0421d, 0x3fec9aef521bd480, // 0.44824, 0.89391 + 0x3fdc997fc3865388, 0x3feca08f19b9c449, // 0.44687, 0.8946 + 0x3fdc8301b95b40c2, 0x3feca62a772fd919, // 0.4455, 0.89528 + 0x3fdc6c7f4997000a, 0x3fecabc169a0b901, // 0.44412, 0.89597 + 0x3fdc55f877b23537, 0x3fecb153f02fb87d, // 0.44275, 0.89665 + 0x3fdc3f6d47263129, 0x3fecb6e20a00da99, // 0.44137, 0.89732 + 0x3fdc28ddbb6cf145, 0x3fecbc6bb638d10b, // 0.43999, 0.898 + 0x3fdc1249d8011ee7, 0x3fecc1f0f3fcfc5c, // 0.43862, 0.89867 + 0x3fdbfbb1a05e0edc, 0x3fecc771c2736c09, // 0.43724, 0.89935 + 0x3fdbe51517ffc0d9, 0x3fecccee20c2de9f, // 0.43586, 0.90002 + 0x3fdbce744262deee, 0x3fecd2660e12c1e6, // 0.43448, 0.90068 + 0x3fdbb7cf2304bd01, 0x3fecd7d9898b32f6, // 0.43309, 0.90135 + 0x3fdba125bd63583e, 0x3fecdd489254fe65, // 0.43171, 0.90201 + 0x3fdb8a7814fd5693, 0x3fece2b32799a060, // 0.43033, 0.90267 + 0x3fdb73c62d520624, 0x3fece819488344ce, // 0.42894, 0.90333 + 0x3fdb5d1009e15cc0, 0x3feced7af43cc773, // 0.42756, 0.90399 + 0x3fdb4655ae2bf757, 0x3fecf2d829f1b40e, // 0.42617, 0.90464 + 0x3fdb2f971db31972, 0x3fecf830e8ce467b, // 0.42478, 0.9053 + 0x3fdb18d45bf8aca6, 0x3fecfd852fff6ad4, // 0.42339, 0.90595 + 0x3fdb020d6c7f4009, 0x3fed02d4feb2bd92, // 0.422, 0.9066 + 0x3fdaeb4252ca07ab, 0x3fed082054168bac, // 0.42061, 0.90724 + 0x3fdad473125cdc08, 0x3fed0d672f59d2b9, // 0.41922, 0.90789 + 0x3fdabd9faebc3980, 0x3fed12a98fac410c, // 0.41782, 0.90853 + 0x3fdaa6c82b6d3fc9, 0x3fed17e7743e35dc, // 0.41643, 0.90917 + 0x3fda8fec8bf5b166, 0x3fed1d20dc40c15c, // 0.41503, 0.90981 + 0x3fda790cd3dbf31a, 0x3fed2255c6e5a4e1, // 0.41364, 0.91044 + 0x3fda622906a70b63, 0x3fed2786335f52fc, // 0.41224, 0.91107 + 0x3fda4b4127dea1e4, 0x3fed2cb220e0ef9f, // 0.41084, 0.91171 + 0x3fda34553b0afee5, 0x3fed31d98e9e503a, // 0.40944, 0.91234 + 0x3fda1d6543b50ac0, 0x3fed36fc7bcbfbdc, // 0.40804, 0.91296 + 0x3fda067145664d57, 0x3fed3c1ae79f2b4e, // 0.40664, 0.91359 + 0x3fd9ef7943a8ed8a, 0x3fed4134d14dc93a, // 0.40524, 0.91421 + 0x3fd9d87d4207b0ab, 0x3fed464a380e7242, // 0.40384, 0.91483 + 0x3fd9c17d440df9f2, 0x3fed4b5b1b187524, // 0.40243, 0.91545 + 0x3fd9aa794d47c9ee, 0x3fed506779a3d2d9, // 0.40103, 0.91606 + 0x3fd993716141bdfe, 0x3fed556f52e93eb1, // 0.39962, 0.91668 + 0x3fd97c6583890fc2, 0x3fed5a72a6221e73, // 0.39822, 0.91729 + 0x3fd96555b7ab948f, 0x3fed5f7172888a7f, // 0.39681, 0.9179 + 0x3fd94e420137bce3, 0x3fed646bb7574de5, // 0.3954, 0.91851 + 0x3fd9372a63bc93d7, 0x3fed696173c9e68b, // 0.39399, 0.91911 + 0x3fd9200ee2c9be97, 0x3fed6e52a71c8547, // 0.39258, 0.91972 + 0x3fd908ef81ef7bd1, 0x3fed733f508c0dff, // 0.39117, 0.92032 + 0x3fd8f1cc44bea329, 0x3fed78276f5617c6, // 0.38976, 0.92092 + 0x3fd8daa52ec8a4af, 0x3fed7d0b02b8ecf9, // 0.38835, 0.92151 + 0x3fd8c37a439f884f, 0x3fed81ea09f38b63, // 0.38693, 0.92211 + 0x3fd8ac4b86d5ed44, 0x3fed86c48445a450, // 0.38552, 0.9227 + 0x3fd89518fbff098e, 0x3fed8b9a70ef9cb4, // 0.3841, 0.92329 + 0x3fd87de2a6aea963, 0x3fed906bcf328d46, // 0.38268, 0.92388 + 0x3fd866a88a792ea0, 0x3fed95389e50429b, // 0.38127, 0.92447 + 0x3fd84f6aaaf3903f, 0x3fed9a00dd8b3d46, // 0.37985, 0.92505 + 0x3fd838290bb359c8, 0x3fed9ec48c26b1f3, // 0.37843, 0.92563 + 0x3fd820e3b04eaac4, 0x3feda383a9668988, // 0.37701, 0.92621 + 0x3fd8099a9c5c362d, 0x3feda83e348f613b, // 0.37559, 0.92679 + 0x3fd7f24dd37341e3, 0x3fedacf42ce68ab9, // 0.37416, 0.92736 + 0x3fd7dafd592ba621, 0x3fedb1a591b20c38, // 0.37274, 0.92794 + 0x3fd7c3a9311dcce7, 0x3fedb6526238a09b, // 0.37132, 0.92851 + 0x3fd7ac515ee2b172, 0x3fedbafa9dc1b78d, // 0.36989, 0.92907 + 0x3fd794f5e613dfae, 0x3fedbf9e4395759a, // 0.36847, 0.92964 + 0x3fd77d96ca4b73a6, 0x3fedc43d52fcb453, // 0.36704, 0.93021 + 0x3fd766340f2418f6, 0x3fedc8d7cb410260, // 0.36561, 0.93077 + 0x3fd74ecdb8390a3e, 0x3fedcd6dabaca3a5, // 0.36418, 0.93133 + 0x3fd73763c9261092, 0x3fedd1fef38a915a, // 0.36276, 0.93188 + 0x3fd71ff6458782ec, 0x3fedd68ba2267a25, // 0.36133, 0.93244 + 0x3fd7088530fa459e, 0x3feddb13b6ccc23d, // 0.3599, 0.93299 + 0x3fd6f1108f1bc9c5, 0x3feddf9730ca837b, // 0.35846, 0.93354 + 0x3fd6d998638a0cb5, 0x3fede4160f6d8d81, // 0.35703, 0.93409 + 0x3fd6c21cb1e39771, 0x3fede890520465ce, // 0.3556, 0.93464 + 0x3fd6aa9d7dc77e16, 0x3feded05f7de47da, // 0.35416, 0.93518 + 0x3fd6931acad55f51, 0x3fedf177004b2534, // 0.35273, 0.93573 + 0x3fd67b949cad63ca, 0x3fedf5e36a9ba59c, // 0.35129, 0.93627 + 0x3fd6640af6f03d9e, 0x3fedfa4b3621271d, // 0.34986, 0.9368 + 0x3fd64c7ddd3f27c6, 0x3fedfeae622dbe2b, // 0.34842, 0.93734 + 0x3fd634ed533be58e, 0x3fee030cee1435b8, // 0.34698, 0.93787 + 0x3fd61d595c88c203, 0x3fee0766d9280f54, // 0.34554, 0.9384 + 0x3fd605c1fcc88f63, 0x3fee0bbc22bd8349, // 0.3441, 0.93893 + 0x3fd5ee27379ea693, 0x3fee100cca2980ac, // 0.34266, 0.93946 + 0x3fd5d68910aee686, 0x3fee1458cec1ad83, // 0.34122, 0.93998 + 0x3fd5bee78b9db3b6, 0x3fee18a02fdc66d9, // 0.33978, 0.94051 + 0x3fd5a742ac0ff78d, 0x3fee1ce2ecd0c0d8, // 0.33833, 0.94103 + 0x3fd58f9a75ab1fdd, 0x3fee212104f686e5, // 0.33689, 0.94154 + 0x3fd577eeec151e47, 0x3fee255a77a63bb8, // 0.33545, 0.94206 + 0x3fd5604012f467b4, 0x3fee298f4439197a, // 0.334, 0.94257 + 0x3fd5488dedeff3be, 0x3fee2dbf6a0911d9, // 0.33255, 0.94308 + 0x3fd530d880af3c24, 0x3fee31eae870ce25, // 0.33111, 0.94359 + 0x3fd5191fceda3c35, 0x3fee3611becbaf69, // 0.32966, 0.9441 + 0x3fd50163dc197047, 0x3fee3a33ec75ce85, // 0.32821, 0.9446 + 0x3fd4e9a4ac15d520, 0x3fee3e5170cbfc46, // 0.32676, 0.94511 + 0x3fd4d1e24278e76a, 0x3fee426a4b2bc17e, // 0.32531, 0.94561 + 0x3fd4ba1ca2eca31c, 0x3fee467e7af35f23, // 0.32386, 0.94611 + 0x3fd4a253d11b82f3, 0x3fee4a8dff81ce5e, // 0.32241, 0.9466 + 0x3fd48a87d0b07fd7, 0x3fee4e98d836c0af, // 0.32096, 0.94709 + 0x3fd472b8a5571054, 0x3fee529f04729ffc, // 0.3195, 0.94759 + 0x3fd45ae652bb2800, 0x3fee56a083968eb1, // 0.31805, 0.94807 + 0x3fd44310dc8936f0, 0x3fee5a9d550467d3, // 0.31659, 0.94856 + 0x3fd42b38466e2928, 0x3fee5e95781ebf1c, // 0.31514, 0.94905 + 0x3fd4135c94176602, 0x3fee6288ec48e112, // 0.31368, 0.94953 + 0x3fd3fb7dc932cfa4, 0x3fee6677b0e6d31e, // 0.31222, 0.95001 + 0x3fd3e39be96ec271, 0x3fee6a61c55d53a7, // 0.31077, 0.95049 + 0x3fd3cbb6f87a146e, 0x3fee6e472911da27, // 0.30931, 0.95096 + 0x3fd3b3cefa0414b7, 0x3fee7227db6a9744, // 0.30785, 0.95144 + 0x3fd39be3f1bc8aef, 0x3fee7603dbce74e9, // 0.30639, 0.95191 + 0x3fd383f5e353b6aa, 0x3fee79db29a5165a, // 0.30493, 0.95238 + 0x3fd36c04d27a4edf, 0x3fee7dadc456d850, // 0.30347, 0.95284 + 0x3fd35410c2e18152, 0x3fee817bab4cd10d, // 0.30201, 0.95331 + 0x3fd33c19b83af207, 0x3fee8544ddf0d075, // 0.30054, 0.95377 + 0x3fd3241fb638baaf, 0x3fee89095bad6025, // 0.29908, 0.95423 + 0x3fd30c22c08d6a13, 0x3fee8cc923edc388, // 0.29762, 0.95469 + 0x3fd2f422daec0386, 0x3fee9084361df7f3, // 0.29615, 0.95514 + 0x3fd2dc200907fe51, 0x3fee943a91aab4b4, // 0.29469, 0.95559 + 0x3fd2c41a4e954520, 0x3fee97ec36016b30, // 0.29322, 0.95605 + 0x3fd2ac11af483572, 0x3fee9b99229046f8, // 0.29175, 0.95649 + 0x3fd294062ed59f05, 0x3fee9f4156c62dda, // 0.29028, 0.95694 + 0x3fd27bf7d0f2c346, 0x3feea2e4d212c000, // 0.28882, 0.95738 + 0x3fd263e6995554ba, 0x3feea68393e65800, // 0.28735, 0.95783 + 0x3fd24bd28bb37672, 0x3feeaa1d9bb20af3, // 0.28588, 0.95827 + 0x3fd233bbabc3bb72, 0x3feeadb2e8e7a88e, // 0.28441, 0.9587 + 0x3fd21ba1fd3d2623, 0x3feeb1437af9bb34, // 0.28294, 0.95914 + 0x3fd2038583d727bd, 0x3feeb4cf515b8811, // 0.28146, 0.95957 + 0x3fd1eb6643499fbb, 0x3feeb8566b810f2a, // 0.27999, 0.96 + 0x3fd1d3443f4cdb3d, 0x3feebbd8c8df0b74, // 0.27852, 0.96043 + 0x3fd1bb1f7b999480, 0x3feebf5668eaf2ef, // 0.27705, 0.96086 + 0x3fd1a2f7fbe8f243, 0x3feec2cf4b1af6b2, // 0.27557, 0.96128 + 0x3fd18acdc3f4873a, 0x3feec6436ee60309, // 0.2741, 0.9617 + 0x3fd172a0d7765177, 0x3feec9b2d3c3bf84, // 0.27262, 0.96212 + 0x3fd15a713a28b9d9, 0x3feecd1d792c8f10, // 0.27115, 0.96254 + 0x3fd1423eefc69378, 0x3feed0835e999009, // 0.26967, 0.96295 + 0x3fd12a09fc0b1b12, 0x3feed3e483849c51, // 0.26819, 0.96337 + 0x3fd111d262b1f677, 0x3feed740e7684963, // 0.26671, 0.96378 + 0x3fd0f998277733f7, 0x3feeda9889bfe86a, // 0.26523, 0.96418 + 0x3fd0e15b4e1749cd, 0x3feeddeb6a078651, // 0.26375, 0.96459 + 0x3fd0c91bda4f158d, 0x3feee13987bbebdc, // 0.26227, 0.96499 + 0x3fd0b0d9cfdbdb90, 0x3feee482e25a9dbc, // 0.26079, 0.96539 + 0x3fd09895327b465e, 0x3feee7c77961dc9e, // 0.25931, 0.96579 + 0x3fd0804e05eb661e, 0x3feeeb074c50a544, // 0.25783, 0.96619 + 0x3fd068044deab002, 0x3feeee425aa6b09a, // 0.25635, 0.96658 + 0x3fd04fb80e37fdae, 0x3feef178a3e473c2, // 0.25487, 0.96698 + 0x3fd037694a928cac, 0x3feef4aa278b2032, // 0.25338, 0.96737 + 0x3fd01f1806b9fdd2, 0x3feef7d6e51ca3c0, // 0.2519, 0.96775 + 0x3fd006c4466e54af, 0x3feefafedc1ba8b7, // 0.25041, 0.96814 + 0x3fcfdcdc1adfedf8, 0x3feefe220c0b95ec, // 0.24893, 0.96852 + 0x3fcfac2abeff57ff, 0x3fef014074708ed3, // 0.24744, 0.9689 + 0x3fcf7b7480bd3801, 0x3fef045a14cf738c, // 0.24596, 0.96928 + 0x3fcf4ab9679c9f5c, 0x3fef076eecade0fa, // 0.24447, 0.96966 + 0x3fcf19f97b215f1a, 0x3fef0a7efb9230d7, // 0.24298, 0.97003 + 0x3fcee934c2d006c7, 0x3fef0d8a410379c5, // 0.24149, 0.9704 + 0x3fceb86b462de348, 0x3fef1090bc898f5f, // 0.24, 0.97077 + 0x3fce879d0cc0fdaf, 0x3fef13926dad024e, // 0.23851, 0.97114 + 0x3fce56ca1e101a1b, 0x3fef168f53f7205d, // 0.23702, 0.9715 + 0x3fce25f281a2b684, 0x3fef19876ef1f486, // 0.23553, 0.97187 + 0x3fcdf5163f01099a, 0x3fef1c7abe284708, // 0.23404, 0.97223 + 0x3fcdc4355db40195, 0x3fef1f6941259d7a, // 0.23255, 0.97258 + 0x3fcd934fe5454311, 0x3fef2252f7763ada, // 0.23106, 0.97294 + 0x3fcd6265dd3f27e3, 0x3fef2537e0a71f9f, // 0.22957, 0.97329 + 0x3fcd31774d2cbdee, 0x3fef2817fc4609ce, // 0.22807, 0.97364 + 0x3fcd00843c99c5f9, 0x3fef2af349e17507, // 0.22658, 0.97399 + 0x3fcccf8cb312b286, 0x3fef2dc9c9089a9d, // 0.22508, 0.97434 + 0x3fcc9e90b824a6a9, 0x3fef309b794b719f, // 0.22359, 0.97468 + 0x3fcc6d90535d74dc, 0x3fef33685a3aaef0, // 0.22209, 0.97503 + 0x3fcc3c8b8c4b9dd7, 0x3fef36306b67c556, // 0.2206, 0.97536 + 0x3fcc0b826a7e4f63, 0x3fef38f3ac64e589, // 0.2191, 0.9757 + 0x3fcbda74f5856330, 0x3fef3bb21cc4fe47, // 0.2176, 0.97604 + 0x3fcba96334f15dad, 0x3fef3e6bbc1bbc65, // 0.21611, 0.97637 + 0x3fcb784d30536cda, 0x3fef412089fd8adc, // 0.21461, 0.9767 + 0x3fcb4732ef3d6722, 0x3fef43d085ff92dd, // 0.21311, 0.97703 + 0x3fcb16147941ca2a, 0x3fef467bafb7bbe0, // 0.21161, 0.97735 + 0x3fcae4f1d5f3b9ab, 0x3fef492206bcabb4, // 0.21011, 0.97768 + 0x3fcab3cb0ce6fe44, 0x3fef4bc38aa5c694, // 0.20861, 0.978 + 0x3fca82a025b00451, 0x3fef4e603b0b2f2d, // 0.20711, 0.97832 + 0x3fca517127e3dabc, 0x3fef50f81785c6b9, // 0.20561, 0.97863 + 0x3fca203e1b1831da, 0x3fef538b1faf2d07, // 0.20411, 0.97895 + 0x3fc9ef0706e35a35, 0x3fef56195321c090, // 0.20261, 0.97926 + 0x3fc9bdcbf2dc4366, 0x3fef58a2b1789e84, // 0.2011, 0.97957 + 0x3fc98c8ce69a7aec, 0x3fef5b273a4fa2d9, // 0.1996, 0.97988 + 0x3fc95b49e9b62af9, 0x3fef5da6ed43685d, // 0.1981, 0.98018 + 0x3fc92a0303c8194f, 0x3fef6021c9f148c2, // 0.19659, 0.98048 + 0x3fc8f8b83c69a60a, 0x3fef6297cff75cb0, // 0.19509, 0.98079 + 0x3fc8c7699b34ca7e, 0x3fef6508fef47bd5, // 0.19359, 0.98108 + 0x3fc8961727c41804, 0x3fef677556883cee, // 0.19208, 0.98138 + 0x3fc864c0e9b2b6cf, 0x3fef69dcd652f5de, // 0.19057, 0.98167 + 0x3fc83366e89c64c5, 0x3fef6c3f7df5bbb7, // 0.18907, 0.98196 + 0x3fc802092c1d744b, 0x3fef6e9d4d1262ca, // 0.18756, 0.98225 + 0x3fc7d0a7bbd2cb1b, 0x3fef70f6434b7eb7, // 0.18606, 0.98254 + 0x3fc79f429f59e11d, 0x3fef734a60446279, // 0.18455, 0.98282 + 0x3fc76dd9de50bf31, 0x3fef7599a3a12077, // 0.18304, 0.98311 + 0x3fc73c6d8055fe0a, 0x3fef77e40d068a90, // 0.18153, 0.98339 + 0x3fc70afd8d08c4ff, 0x3fef7a299c1a322a, // 0.18002, 0.98366 + 0x3fc6d98a0c08c8da, 0x3fef7c6a50826840, // 0.17851, 0.98394 + 0x3fc6a81304f64ab2, 0x3fef7ea629e63d6e, // 0.177, 0.98421 + 0x3fc676987f7216b8, 0x3fef80dd27ed8204, // 0.17549, 0.98448 + 0x3fc6451a831d830d, 0x3fef830f4a40c60c, // 0.17398, 0.98475 + 0x3fc61399179a6e94, 0x3fef853c9089595e, // 0.17247, 0.98501 + 0x3fc5e214448b3fc6, 0x3fef8764fa714ba9, // 0.17096, 0.98528 + 0x3fc5b08c1192e381, 0x3fef898887a36c84, // 0.16945, 0.98554 + 0x3fc57f008654cbde, 0x3fef8ba737cb4b78, // 0.16794, 0.9858 + 0x3fc54d71aa74ef02, 0x3fef8dc10a95380d, // 0.16643, 0.98605 + 0x3fc51bdf8597c5f2, 0x3fef8fd5ffae41db, // 0.16491, 0.98631 + 0x3fc4ea4a1f624b61, 0x3fef91e616c43891, // 0.1634, 0.98656 + 0x3fc4b8b17f79fa88, 0x3fef93f14f85ac08, // 0.16189, 0.98681 + 0x3fc48715ad84cdf5, 0x3fef95f7a9a1ec47, // 0.16037, 0.98706 + 0x3fc45576b1293e5a, 0x3fef97f924c9099b, // 0.15886, 0.9873 + 0x3fc423d4920e4166, 0x3fef99f5c0abd496, // 0.15734, 0.98754 + 0x3fc3f22f57db4893, 0x3fef9bed7cfbde29, // 0.15583, 0.98778 + 0x3fc3c0870a383ff6, 0x3fef9de0596b77a3, // 0.15431, 0.98802 + 0x3fc38edbb0cd8d14, 0x3fef9fce55adb2c8, // 0.1528, 0.98826 + 0x3fc35d2d53440db2, 0x3fefa1b7717661d5, // 0.15128, 0.98849 + 0x3fc32b7bf94516a7, 0x3fefa39bac7a1791, // 0.14976, 0.98872 + 0x3fc2f9c7aa7a72af, 0x3fefa57b066e2754, // 0.14825, 0.98895 + 0x3fc2c8106e8e613a, 0x3fefa7557f08a517, // 0.14673, 0.98918 + 0x3fc296564d2b953e, 0x3fefa92b1600657c, // 0.14521, 0.9894 + 0x3fc264994dfd340a, 0x3fefaafbcb0cfddc, // 0.1437, 0.98962 + 0x3fc232d978aed413, 0x3fefacc79de6c44f, // 0.14218, 0.98984 + 0x3fc20116d4ec7bce, 0x3fefae8e8e46cfbb, // 0.14066, 0.99006 + 0x3fc1cf516a62a077, 0x3fefb0509be6f7db, // 0.13914, 0.99027 + 0x3fc19d8940be24e7, 0x3fefb20dc681d54d, // 0.13762, 0.99049 + 0x3fc16bbe5fac5865, 0x3fefb3c60dd2c199, // 0.1361, 0.9907 + 0x3fc139f0cedaf576, 0x3fefb5797195d741, // 0.13458, 0.9909 + 0x3fc1082095f820b0, 0x3fefb727f187f1c7, // 0.13306, 0.99111 + 0x3fc0d64dbcb26786, 0x3fefb8d18d66adb7, // 0.13154, 0.99131 + 0x3fc0a4784ab8bf1d, 0x3fefba7644f068b5, // 0.13002, 0.99151 + 0x3fc072a047ba831d, 0x3fefbc1617e44186, // 0.1285, 0.99171 + 0x3fc040c5bb67747e, 0x3fefbdb106021816, // 0.12698, 0.99191 + 0x3fc00ee8ad6fb85b, 0x3fefbf470f0a8d88, // 0.12545, 0.9921 + 0x3fbfba124b07ad85, 0x3fefc0d832bf043a, // 0.12393, 0.99229 + 0x3fbf564e56a9730e, 0x3fefc26470e19fd3, // 0.12241, 0.99248 + 0x3fbef2858d27561b, 0x3fefc3ebc935454c, // 0.12089, 0.99267 + 0x3fbe8eb7fde4aa3e, 0x3fefc56e3b7d9af6, // 0.11937, 0.99285 + 0x3fbe2ae5b8457f77, 0x3fefc6ebc77f0887, // 0.11784, 0.99303 + 0x3fbdc70ecbae9fc8, 0x3fefc8646cfeb721, // 0.11632, 0.99321 + 0x3fbd633347858ce4, 0x3fefc9d82bc2915e, // 0.11479, 0.99339 + 0x3fbcff533b307dc1, 0x3fefcb4703914354, // 0.11327, 0.99356 + 0x3fbc9b6eb6165c42, 0x3fefccb0f4323aa3, // 0.11175, 0.99374 + 0x3fbc3785c79ec2d5, 0x3fefce15fd6da67b, // 0.11022, 0.99391 + 0x3fbbd3987f31fa0e, 0x3fefcf761f0c77a3, // 0.1087, 0.99407 + 0x3fbb6fa6ec38f64c, 0x3fefd0d158d86087, // 0.10717, 0.99424 + 0x3fbb0bb11e1d5559, 0x3fefd227aa9bd53b, // 0.10565, 0.9944 + 0x3fbaa7b724495c04, 0x3fefd37914220b84, // 0.10412, 0.99456 + 0x3fba43b90e27f3c4, 0x3fefd4c59536fae4, // 0.1026, 0.99472 + 0x3fb9dfb6eb24a85c, 0x3fefd60d2da75c9e, // 0.10107, 0.99488 + 0x3fb97bb0caaba56f, 0x3fefd74fdd40abbf, // 0.099544, 0.99503 + 0x3fb917a6bc29b42c, 0x3fefd88da3d12526, // 0.098017, 0.99518 + 0x3fb8b398cf0c38e0, 0x3fefd9c68127c78c, // 0.09649, 0.99533 + 0x3fb84f8712c130a0, 0x3fefdafa7514538c, // 0.094963, 0.99548 + 0x3fb7eb7196b72ee4, 0x3fefdc297f674ba9, // 0.093436, 0.99563 + 0x3fb787586a5d5b21, 0x3fefdd539ff1f456, // 0.091909, 0.99577 + 0x3fb7233b9d236e71, 0x3fefde78d68653fd, // 0.090381, 0.99591 + 0x3fb6bf1b3e79b129, 0x3fefdf9922f73307, // 0.088854, 0.99604 + 0x3fb65af75dd0f87b, 0x3fefe0b485181be3, // 0.087326, 0.99618 + 0x3fb5f6d00a9aa419, 0x3fefe1cafcbd5b09, // 0.085797, 0.99631 + 0x3fb592a554489bc8, 0x3fefe2dc89bbff08, // 0.084269, 0.99644 + 0x3fb52e774a4d4d0a, 0x3fefe3e92be9d886, // 0.08274, 0.99657 + 0x3fb4ca45fc1ba8b6, 0x3fefe4f0e31d7a4a, // 0.081211, 0.9967 + 0x3fb4661179272096, 0x3fefe5f3af2e3940, // 0.079682, 0.99682 + 0x3fb401d9d0e3a507, 0x3fefe6f18ff42c84, // 0.078153, 0.99694 + 0x3fb39d9f12c5a299, 0x3fefe7ea85482d60, // 0.076624, 0.99706 + 0x3fb339614e41ffa5, 0x3fefe8de8f03d75c, // 0.075094, 0.99718 + 0x3fb2d52092ce19f6, 0x3fefe9cdad01883a, // 0.073565, 0.99729 + 0x3fb270dcefdfc45b, 0x3fefeab7df1c6005, // 0.072035, 0.9974 + 0x3fb20c9674ed444c, 0x3fefeb9d2530410f, // 0.070505, 0.99751 + 0x3fb1a84d316d4f8a, 0x3fefec7d7f19cffc, // 0.068974, 0.99762 + 0x3fb1440134d709b2, 0x3fefed58ecb673c4, // 0.067444, 0.99772 + 0x3fb0dfb28ea201e6, 0x3fefee2f6de455ba, // 0.065913, 0.99783 + 0x3fb07b614e463064, 0x3fefef0102826191, // 0.064383, 0.99793 + 0x3fb0170d833bf421, 0x3fefefcdaa704562, // 0.062852, 0.99802 + 0x3faf656e79f820e0, 0x3feff095658e71ad, // 0.061321, 0.99812 + 0x3fae9cbd15ff5527, 0x3feff15833be1965, // 0.05979, 0.99821 + 0x3fadd406f9808ec8, 0x3feff21614e131ed, // 0.058258, 0.9983 + 0x3fad0b4c436f91d0, 0x3feff2cf08da7321, // 0.056727, 0.99839 + 0x3fac428d12c0d7e3, 0x3feff3830f8d575c, // 0.055195, 0.99848 + 0x3fab79c986698b78, 0x3feff43228de1b77, // 0.053664, 0.99856 + 0x3faab101bd5f8317, 0x3feff4dc54b1bed3, // 0.052132, 0.99864 + 0x3fa9e835d6993c87, 0x3feff58192ee0358, // 0.0506, 0.99872 + 0x3fa91f65f10dd814, 0x3feff621e3796d7e, // 0.049068, 0.9988 + 0x3fa856922bb513c1, 0x3feff6bd463b444d, // 0.047535, 0.99887 + 0x3fa78dbaa5874685, 0x3feff753bb1b9164, // 0.046003, 0.99894 + 0x3fa6c4df7d7d5b84, 0x3feff7e5420320f9, // 0.044471, 0.99901 + 0x3fa5fc00d290cd43, 0x3feff871dadb81df, // 0.042938, 0.99908 + 0x3fa5331ec3bba0eb, 0x3feff8f9858f058b, // 0.041406, 0.99914 + 0x3fa46a396ff86179, 0x3feff97c4208c014, // 0.039873, 0.9992 + 0x3fa3a150f6421afc, 0x3feff9fa10348837, // 0.03834, 0.99926 + 0x3fa2d865759455cd, 0x3feffa72effef75d, // 0.036807, 0.99932 + 0x3fa20f770ceb11c6, 0x3feffae6e1556998, // 0.035274, 0.99938 + 0x3fa14685db42c17e, 0x3feffb55e425fdae, // 0.033741, 0.99943 + 0x3fa07d91ff984580, 0x3feffbbff85f9515, // 0.032208, 0.99948 + 0x3f9f693731d1cf01, 0x3feffc251df1d3f8, // 0.030675, 0.99953 + 0x3f9dd7458c64ab39, 0x3feffc8554cd213a, // 0.029142, 0.99958 + 0x3f9c454f4ce53b1c, 0x3feffce09ce2a679, // 0.027608, 0.99962 + 0x3f9ab354b1504fca, 0x3feffd36f624500c, // 0.026075, 0.99966 + 0x3f992155f7a3667e, 0x3feffd886084cd0d, // 0.024541, 0.9997 + 0x3f978f535ddc9f03, 0x3feffdd4dbf78f52, // 0.023008, 0.99974 + 0x3f95fd4d21fab226, 0x3feffe1c6870cb77, // 0.021474, 0.99977 + 0x3f946b4381fce81c, 0x3feffe5f05e578db, // 0.01994, 0.9998 + 0x3f92d936bbe30efd, 0x3feffe9cb44b51a1, // 0.018407, 0.99983 + 0x3f9147270dad7132, 0x3feffed57398d2b7, // 0.016873, 0.99986 + 0x3f8f6a296ab997ca, 0x3fefff0943c53bd1, // 0.015339, 0.99988 + 0x3f8c45ffe1e48ad9, 0x3fefff3824c88f6f, // 0.013805, 0.9999 + 0x3f8921d1fcdec784, 0x3fefff62169b92db, // 0.012272, 0.99992 + 0x3f85fda037ac05e0, 0x3fefff871937ce2f, // 0.010738, 0.99994 + 0x3f82d96b0e509703, 0x3fefffa72c978c4f, // 0.0092038, 0.99996 + 0x3f7f6a65f9a2a3c5, 0x3fefffc250b5daef, // 0.0076698, 0.99997 + 0x3f7921f0fe670071, 0x3fefffd8858e8a92, // 0.0061359, 0.99998 + 0x3f72d97822f996bc, 0x3fefffe9cb1e2e8d, // 0.0046019, 0.99999 + 0x3f6921f8becca4ba, 0x3feffff621621d02, // 0.003068, 1 + 0x3f5921faaee6472d, 0x3feffffd88586ee6, // 0.001534, 1 + 0x0000000000000000, 0x3ff0000000000000, // 0, 1 + 0xbf5921faaee6472d, 0x3feffffd88586ee6, // -0.001534, 1 + 0xbf6921f8becca4ba, 0x3feffff621621d02, // -0.003068, 1 + 0xbf72d97822f996bc, 0x3fefffe9cb1e2e8d, //-0.0046019, 0.99999 + 0xbf7921f0fe670071, 0x3fefffd8858e8a92, //-0.0061359, 0.99998 + 0xbf7f6a65f9a2a3c5, 0x3fefffc250b5daef, //-0.0076698, 0.99997 + 0xbf82d96b0e509703, 0x3fefffa72c978c4f, //-0.0092038, 0.99996 + 0xbf85fda037ac05e0, 0x3fefff871937ce2f, // -0.010738, 0.99994 + 0xbf8921d1fcdec784, 0x3fefff62169b92db, // -0.012272, 0.99992 + 0xbf8c45ffe1e48ad9, 0x3fefff3824c88f6f, // -0.013805, 0.9999 + 0xbf8f6a296ab997ca, 0x3fefff0943c53bd1, // -0.015339, 0.99988 + 0xbf9147270dad7132, 0x3feffed57398d2b7, // -0.016873, 0.99986 + 0xbf92d936bbe30efd, 0x3feffe9cb44b51a1, // -0.018407, 0.99983 + 0xbf946b4381fce81c, 0x3feffe5f05e578db, // -0.01994, 0.9998 + 0xbf95fd4d21fab226, 0x3feffe1c6870cb77, // -0.021474, 0.99977 + 0xbf978f535ddc9f03, 0x3feffdd4dbf78f52, // -0.023008, 0.99974 + 0xbf992155f7a3667e, 0x3feffd886084cd0d, // -0.024541, 0.9997 + 0xbf9ab354b1504fca, 0x3feffd36f624500c, // -0.026075, 0.99966 + 0xbf9c454f4ce53b1c, 0x3feffce09ce2a679, // -0.027608, 0.99962 + 0xbf9dd7458c64ab39, 0x3feffc8554cd213a, // -0.029142, 0.99958 + 0xbf9f693731d1cf01, 0x3feffc251df1d3f8, // -0.030675, 0.99953 + 0xbfa07d91ff984580, 0x3feffbbff85f9515, // -0.032208, 0.99948 + 0xbfa14685db42c17e, 0x3feffb55e425fdae, // -0.033741, 0.99943 + 0xbfa20f770ceb11c6, 0x3feffae6e1556998, // -0.035274, 0.99938 + 0xbfa2d865759455cd, 0x3feffa72effef75d, // -0.036807, 0.99932 + 0xbfa3a150f6421afc, 0x3feff9fa10348837, // -0.03834, 0.99926 + 0xbfa46a396ff86179, 0x3feff97c4208c014, // -0.039873, 0.9992 + 0xbfa5331ec3bba0eb, 0x3feff8f9858f058b, // -0.041406, 0.99914 + 0xbfa5fc00d290cd43, 0x3feff871dadb81df, // -0.042938, 0.99908 + 0xbfa6c4df7d7d5b84, 0x3feff7e5420320f9, // -0.044471, 0.99901 + 0xbfa78dbaa5874685, 0x3feff753bb1b9164, // -0.046003, 0.99894 + 0xbfa856922bb513c1, 0x3feff6bd463b444d, // -0.047535, 0.99887 + 0xbfa91f65f10dd814, 0x3feff621e3796d7e, // -0.049068, 0.9988 + 0xbfa9e835d6993c87, 0x3feff58192ee0358, // -0.0506, 0.99872 + 0xbfaab101bd5f8317, 0x3feff4dc54b1bed3, // -0.052132, 0.99864 + 0xbfab79c986698b78, 0x3feff43228de1b77, // -0.053664, 0.99856 + 0xbfac428d12c0d7e3, 0x3feff3830f8d575c, // -0.055195, 0.99848 + 0xbfad0b4c436f91d0, 0x3feff2cf08da7321, // -0.056727, 0.99839 + 0xbfadd406f9808ec8, 0x3feff21614e131ed, // -0.058258, 0.9983 + 0xbfae9cbd15ff5527, 0x3feff15833be1965, // -0.05979, 0.99821 + 0xbfaf656e79f820e0, 0x3feff095658e71ad, // -0.061321, 0.99812 + 0xbfb0170d833bf421, 0x3fefefcdaa704562, // -0.062852, 0.99802 + 0xbfb07b614e463064, 0x3fefef0102826191, // -0.064383, 0.99793 + 0xbfb0dfb28ea201e6, 0x3fefee2f6de455ba, // -0.065913, 0.99783 + 0xbfb1440134d709b2, 0x3fefed58ecb673c4, // -0.067444, 0.99772 + 0xbfb1a84d316d4f8a, 0x3fefec7d7f19cffc, // -0.068974, 0.99762 + 0xbfb20c9674ed444c, 0x3fefeb9d2530410f, // -0.070505, 0.99751 + 0xbfb270dcefdfc45b, 0x3fefeab7df1c6005, // -0.072035, 0.9974 + 0xbfb2d52092ce19f6, 0x3fefe9cdad01883a, // -0.073565, 0.99729 + 0xbfb339614e41ffa5, 0x3fefe8de8f03d75c, // -0.075094, 0.99718 + 0xbfb39d9f12c5a299, 0x3fefe7ea85482d60, // -0.076624, 0.99706 + 0xbfb401d9d0e3a507, 0x3fefe6f18ff42c84, // -0.078153, 0.99694 + 0xbfb4661179272096, 0x3fefe5f3af2e3940, // -0.079682, 0.99682 + 0xbfb4ca45fc1ba8b6, 0x3fefe4f0e31d7a4a, // -0.081211, 0.9967 + 0xbfb52e774a4d4d0a, 0x3fefe3e92be9d886, // -0.08274, 0.99657 + 0xbfb592a554489bc8, 0x3fefe2dc89bbff08, // -0.084269, 0.99644 + 0xbfb5f6d00a9aa419, 0x3fefe1cafcbd5b09, // -0.085797, 0.99631 + 0xbfb65af75dd0f87b, 0x3fefe0b485181be3, // -0.087326, 0.99618 + 0xbfb6bf1b3e79b129, 0x3fefdf9922f73307, // -0.088854, 0.99604 + 0xbfb7233b9d236e71, 0x3fefde78d68653fd, // -0.090381, 0.99591 + 0xbfb787586a5d5b21, 0x3fefdd539ff1f456, // -0.091909, 0.99577 + 0xbfb7eb7196b72ee4, 0x3fefdc297f674ba9, // -0.093436, 0.99563 + 0xbfb84f8712c130a0, 0x3fefdafa7514538c, // -0.094963, 0.99548 + 0xbfb8b398cf0c38e0, 0x3fefd9c68127c78c, // -0.09649, 0.99533 + 0xbfb917a6bc29b42c, 0x3fefd88da3d12526, // -0.098017, 0.99518 + 0xbfb97bb0caaba56f, 0x3fefd74fdd40abbf, // -0.099544, 0.99503 + 0xbfb9dfb6eb24a85c, 0x3fefd60d2da75c9e, // -0.10107, 0.99488 + 0xbfba43b90e27f3c4, 0x3fefd4c59536fae4, // -0.1026, 0.99472 + 0xbfbaa7b724495c04, 0x3fefd37914220b84, // -0.10412, 0.99456 + 0xbfbb0bb11e1d5559, 0x3fefd227aa9bd53b, // -0.10565, 0.9944 + 0xbfbb6fa6ec38f64c, 0x3fefd0d158d86087, // -0.10717, 0.99424 + 0xbfbbd3987f31fa0e, 0x3fefcf761f0c77a3, // -0.1087, 0.99407 + 0xbfbc3785c79ec2d5, 0x3fefce15fd6da67b, // -0.11022, 0.99391 + 0xbfbc9b6eb6165c42, 0x3fefccb0f4323aa3, // -0.11175, 0.99374 + 0xbfbcff533b307dc1, 0x3fefcb4703914354, // -0.11327, 0.99356 + 0xbfbd633347858ce4, 0x3fefc9d82bc2915e, // -0.11479, 0.99339 + 0xbfbdc70ecbae9fc8, 0x3fefc8646cfeb721, // -0.11632, 0.99321 + 0xbfbe2ae5b8457f77, 0x3fefc6ebc77f0887, // -0.11784, 0.99303 + 0xbfbe8eb7fde4aa3e, 0x3fefc56e3b7d9af6, // -0.11937, 0.99285 + 0xbfbef2858d27561b, 0x3fefc3ebc935454c, // -0.12089, 0.99267 + 0xbfbf564e56a9730e, 0x3fefc26470e19fd3, // -0.12241, 0.99248 + 0xbfbfba124b07ad85, 0x3fefc0d832bf043a, // -0.12393, 0.99229 + 0xbfc00ee8ad6fb85b, 0x3fefbf470f0a8d88, // -0.12545, 0.9921 + 0xbfc040c5bb67747e, 0x3fefbdb106021816, // -0.12698, 0.99191 + 0xbfc072a047ba831d, 0x3fefbc1617e44186, // -0.1285, 0.99171 + 0xbfc0a4784ab8bf1d, 0x3fefba7644f068b5, // -0.13002, 0.99151 + 0xbfc0d64dbcb26786, 0x3fefb8d18d66adb7, // -0.13154, 0.99131 + 0xbfc1082095f820b0, 0x3fefb727f187f1c7, // -0.13306, 0.99111 + 0xbfc139f0cedaf576, 0x3fefb5797195d741, // -0.13458, 0.9909 + 0xbfc16bbe5fac5865, 0x3fefb3c60dd2c199, // -0.1361, 0.9907 + 0xbfc19d8940be24e7, 0x3fefb20dc681d54d, // -0.13762, 0.99049 + 0xbfc1cf516a62a077, 0x3fefb0509be6f7db, // -0.13914, 0.99027 + 0xbfc20116d4ec7bce, 0x3fefae8e8e46cfbb, // -0.14066, 0.99006 + 0xbfc232d978aed413, 0x3fefacc79de6c44f, // -0.14218, 0.98984 + 0xbfc264994dfd340a, 0x3fefaafbcb0cfddc, // -0.1437, 0.98962 + 0xbfc296564d2b953e, 0x3fefa92b1600657c, // -0.14521, 0.9894 + 0xbfc2c8106e8e613a, 0x3fefa7557f08a517, // -0.14673, 0.98918 + 0xbfc2f9c7aa7a72af, 0x3fefa57b066e2754, // -0.14825, 0.98895 + 0xbfc32b7bf94516a7, 0x3fefa39bac7a1791, // -0.14976, 0.98872 + 0xbfc35d2d53440db2, 0x3fefa1b7717661d5, // -0.15128, 0.98849 + 0xbfc38edbb0cd8d14, 0x3fef9fce55adb2c8, // -0.1528, 0.98826 + 0xbfc3c0870a383ff6, 0x3fef9de0596b77a3, // -0.15431, 0.98802 + 0xbfc3f22f57db4893, 0x3fef9bed7cfbde29, // -0.15583, 0.98778 + 0xbfc423d4920e4166, 0x3fef99f5c0abd496, // -0.15734, 0.98754 + 0xbfc45576b1293e5a, 0x3fef97f924c9099b, // -0.15886, 0.9873 + 0xbfc48715ad84cdf5, 0x3fef95f7a9a1ec47, // -0.16037, 0.98706 + 0xbfc4b8b17f79fa88, 0x3fef93f14f85ac08, // -0.16189, 0.98681 + 0xbfc4ea4a1f624b61, 0x3fef91e616c43891, // -0.1634, 0.98656 + 0xbfc51bdf8597c5f2, 0x3fef8fd5ffae41db, // -0.16491, 0.98631 + 0xbfc54d71aa74ef02, 0x3fef8dc10a95380d, // -0.16643, 0.98605 + 0xbfc57f008654cbde, 0x3fef8ba737cb4b78, // -0.16794, 0.9858 + 0xbfc5b08c1192e381, 0x3fef898887a36c84, // -0.16945, 0.98554 + 0xbfc5e214448b3fc6, 0x3fef8764fa714ba9, // -0.17096, 0.98528 + 0xbfc61399179a6e94, 0x3fef853c9089595e, // -0.17247, 0.98501 + 0xbfc6451a831d830d, 0x3fef830f4a40c60c, // -0.17398, 0.98475 + 0xbfc676987f7216b8, 0x3fef80dd27ed8204, // -0.17549, 0.98448 + 0xbfc6a81304f64ab2, 0x3fef7ea629e63d6e, // -0.177, 0.98421 + 0xbfc6d98a0c08c8da, 0x3fef7c6a50826840, // -0.17851, 0.98394 + 0xbfc70afd8d08c4ff, 0x3fef7a299c1a322a, // -0.18002, 0.98366 + 0xbfc73c6d8055fe0a, 0x3fef77e40d068a90, // -0.18153, 0.98339 + 0xbfc76dd9de50bf31, 0x3fef7599a3a12077, // -0.18304, 0.98311 + 0xbfc79f429f59e11d, 0x3fef734a60446279, // -0.18455, 0.98282 + 0xbfc7d0a7bbd2cb1b, 0x3fef70f6434b7eb7, // -0.18606, 0.98254 + 0xbfc802092c1d744b, 0x3fef6e9d4d1262ca, // -0.18756, 0.98225 + 0xbfc83366e89c64c5, 0x3fef6c3f7df5bbb7, // -0.18907, 0.98196 + 0xbfc864c0e9b2b6cf, 0x3fef69dcd652f5de, // -0.19057, 0.98167 + 0xbfc8961727c41804, 0x3fef677556883cee, // -0.19208, 0.98138 + 0xbfc8c7699b34ca7e, 0x3fef6508fef47bd5, // -0.19359, 0.98108 + 0xbfc8f8b83c69a60a, 0x3fef6297cff75cb0, // -0.19509, 0.98079 + 0xbfc92a0303c8194f, 0x3fef6021c9f148c2, // -0.19659, 0.98048 + 0xbfc95b49e9b62af9, 0x3fef5da6ed43685d, // -0.1981, 0.98018 + 0xbfc98c8ce69a7aec, 0x3fef5b273a4fa2d9, // -0.1996, 0.97988 + 0xbfc9bdcbf2dc4366, 0x3fef58a2b1789e84, // -0.2011, 0.97957 + 0xbfc9ef0706e35a35, 0x3fef56195321c090, // -0.20261, 0.97926 + 0xbfca203e1b1831da, 0x3fef538b1faf2d07, // -0.20411, 0.97895 + 0xbfca517127e3dabc, 0x3fef50f81785c6b9, // -0.20561, 0.97863 + 0xbfca82a025b00451, 0x3fef4e603b0b2f2d, // -0.20711, 0.97832 + 0xbfcab3cb0ce6fe44, 0x3fef4bc38aa5c694, // -0.20861, 0.978 + 0xbfcae4f1d5f3b9ab, 0x3fef492206bcabb4, // -0.21011, 0.97768 + 0xbfcb16147941ca2a, 0x3fef467bafb7bbe0, // -0.21161, 0.97735 + 0xbfcb4732ef3d6722, 0x3fef43d085ff92dd, // -0.21311, 0.97703 + 0xbfcb784d30536cda, 0x3fef412089fd8adc, // -0.21461, 0.9767 + 0xbfcba96334f15dad, 0x3fef3e6bbc1bbc65, // -0.21611, 0.97637 + 0xbfcbda74f5856330, 0x3fef3bb21cc4fe47, // -0.2176, 0.97604 + 0xbfcc0b826a7e4f63, 0x3fef38f3ac64e589, // -0.2191, 0.9757 + 0xbfcc3c8b8c4b9dd7, 0x3fef36306b67c556, // -0.2206, 0.97536 + 0xbfcc6d90535d74dc, 0x3fef33685a3aaef0, // -0.22209, 0.97503 + 0xbfcc9e90b824a6a9, 0x3fef309b794b719f, // -0.22359, 0.97468 + 0xbfcccf8cb312b286, 0x3fef2dc9c9089a9d, // -0.22508, 0.97434 + 0xbfcd00843c99c5f9, 0x3fef2af349e17507, // -0.22658, 0.97399 + 0xbfcd31774d2cbdee, 0x3fef2817fc4609ce, // -0.22807, 0.97364 + 0xbfcd6265dd3f27e3, 0x3fef2537e0a71f9f, // -0.22957, 0.97329 + 0xbfcd934fe5454311, 0x3fef2252f7763ada, // -0.23106, 0.97294 + 0xbfcdc4355db40195, 0x3fef1f6941259d7a, // -0.23255, 0.97258 + 0xbfcdf5163f01099a, 0x3fef1c7abe284708, // -0.23404, 0.97223 + 0xbfce25f281a2b684, 0x3fef19876ef1f486, // -0.23553, 0.97187 + 0xbfce56ca1e101a1b, 0x3fef168f53f7205d, // -0.23702, 0.9715 + 0xbfce879d0cc0fdaf, 0x3fef13926dad024e, // -0.23851, 0.97114 + 0xbfceb86b462de348, 0x3fef1090bc898f5f, // -0.24, 0.97077 + 0xbfcee934c2d006c7, 0x3fef0d8a410379c5, // -0.24149, 0.9704 + 0xbfcf19f97b215f1a, 0x3fef0a7efb9230d7, // -0.24298, 0.97003 + 0xbfcf4ab9679c9f5c, 0x3fef076eecade0fa, // -0.24447, 0.96966 + 0xbfcf7b7480bd3801, 0x3fef045a14cf738c, // -0.24596, 0.96928 + 0xbfcfac2abeff57ff, 0x3fef014074708ed3, // -0.24744, 0.9689 + 0xbfcfdcdc1adfedf8, 0x3feefe220c0b95ec, // -0.24893, 0.96852 + 0xbfd006c4466e54af, 0x3feefafedc1ba8b7, // -0.25041, 0.96814 + 0xbfd01f1806b9fdd2, 0x3feef7d6e51ca3c0, // -0.2519, 0.96775 + 0xbfd037694a928cac, 0x3feef4aa278b2032, // -0.25338, 0.96737 + 0xbfd04fb80e37fdae, 0x3feef178a3e473c2, // -0.25487, 0.96698 + 0xbfd068044deab002, 0x3feeee425aa6b09a, // -0.25635, 0.96658 + 0xbfd0804e05eb661e, 0x3feeeb074c50a544, // -0.25783, 0.96619 + 0xbfd09895327b465e, 0x3feee7c77961dc9e, // -0.25931, 0.96579 + 0xbfd0b0d9cfdbdb90, 0x3feee482e25a9dbc, // -0.26079, 0.96539 + 0xbfd0c91bda4f158d, 0x3feee13987bbebdc, // -0.26227, 0.96499 + 0xbfd0e15b4e1749cd, 0x3feeddeb6a078651, // -0.26375, 0.96459 + 0xbfd0f998277733f7, 0x3feeda9889bfe86a, // -0.26523, 0.96418 + 0xbfd111d262b1f677, 0x3feed740e7684963, // -0.26671, 0.96378 + 0xbfd12a09fc0b1b12, 0x3feed3e483849c51, // -0.26819, 0.96337 + 0xbfd1423eefc69378, 0x3feed0835e999009, // -0.26967, 0.96295 + 0xbfd15a713a28b9d9, 0x3feecd1d792c8f10, // -0.27115, 0.96254 + 0xbfd172a0d7765177, 0x3feec9b2d3c3bf84, // -0.27262, 0.96212 + 0xbfd18acdc3f4873a, 0x3feec6436ee60309, // -0.2741, 0.9617 + 0xbfd1a2f7fbe8f243, 0x3feec2cf4b1af6b2, // -0.27557, 0.96128 + 0xbfd1bb1f7b999480, 0x3feebf5668eaf2ef, // -0.27705, 0.96086 + 0xbfd1d3443f4cdb3d, 0x3feebbd8c8df0b74, // -0.27852, 0.96043 + 0xbfd1eb6643499fbb, 0x3feeb8566b810f2a, // -0.27999, 0.96 + 0xbfd2038583d727bd, 0x3feeb4cf515b8811, // -0.28146, 0.95957 + 0xbfd21ba1fd3d2623, 0x3feeb1437af9bb34, // -0.28294, 0.95914 + 0xbfd233bbabc3bb72, 0x3feeadb2e8e7a88e, // -0.28441, 0.9587 + 0xbfd24bd28bb37672, 0x3feeaa1d9bb20af3, // -0.28588, 0.95827 + 0xbfd263e6995554ba, 0x3feea68393e65800, // -0.28735, 0.95783 + 0xbfd27bf7d0f2c346, 0x3feea2e4d212c000, // -0.28882, 0.95738 + 0xbfd294062ed59f05, 0x3fee9f4156c62dda, // -0.29028, 0.95694 + 0xbfd2ac11af483572, 0x3fee9b99229046f8, // -0.29175, 0.95649 + 0xbfd2c41a4e954520, 0x3fee97ec36016b30, // -0.29322, 0.95605 + 0xbfd2dc200907fe51, 0x3fee943a91aab4b4, // -0.29469, 0.95559 + 0xbfd2f422daec0386, 0x3fee9084361df7f3, // -0.29615, 0.95514 + 0xbfd30c22c08d6a13, 0x3fee8cc923edc388, // -0.29762, 0.95469 + 0xbfd3241fb638baaf, 0x3fee89095bad6025, // -0.29908, 0.95423 + 0xbfd33c19b83af207, 0x3fee8544ddf0d075, // -0.30054, 0.95377 + 0xbfd35410c2e18152, 0x3fee817bab4cd10d, // -0.30201, 0.95331 + 0xbfd36c04d27a4edf, 0x3fee7dadc456d850, // -0.30347, 0.95284 + 0xbfd383f5e353b6aa, 0x3fee79db29a5165a, // -0.30493, 0.95238 + 0xbfd39be3f1bc8aef, 0x3fee7603dbce74e9, // -0.30639, 0.95191 + 0xbfd3b3cefa0414b7, 0x3fee7227db6a9744, // -0.30785, 0.95144 + 0xbfd3cbb6f87a146e, 0x3fee6e472911da27, // -0.30931, 0.95096 + 0xbfd3e39be96ec271, 0x3fee6a61c55d53a7, // -0.31077, 0.95049 + 0xbfd3fb7dc932cfa4, 0x3fee6677b0e6d31e, // -0.31222, 0.95001 + 0xbfd4135c94176602, 0x3fee6288ec48e112, // -0.31368, 0.94953 + 0xbfd42b38466e2928, 0x3fee5e95781ebf1c, // -0.31514, 0.94905 + 0xbfd44310dc8936f0, 0x3fee5a9d550467d3, // -0.31659, 0.94856 + 0xbfd45ae652bb2800, 0x3fee56a083968eb1, // -0.31805, 0.94807 + 0xbfd472b8a5571054, 0x3fee529f04729ffc, // -0.3195, 0.94759 + 0xbfd48a87d0b07fd7, 0x3fee4e98d836c0af, // -0.32096, 0.94709 + 0xbfd4a253d11b82f3, 0x3fee4a8dff81ce5e, // -0.32241, 0.9466 + 0xbfd4ba1ca2eca31c, 0x3fee467e7af35f23, // -0.32386, 0.94611 + 0xbfd4d1e24278e76a, 0x3fee426a4b2bc17e, // -0.32531, 0.94561 + 0xbfd4e9a4ac15d520, 0x3fee3e5170cbfc46, // -0.32676, 0.94511 + 0xbfd50163dc197047, 0x3fee3a33ec75ce85, // -0.32821, 0.9446 + 0xbfd5191fceda3c35, 0x3fee3611becbaf69, // -0.32966, 0.9441 + 0xbfd530d880af3c24, 0x3fee31eae870ce25, // -0.33111, 0.94359 + 0xbfd5488dedeff3be, 0x3fee2dbf6a0911d9, // -0.33255, 0.94308 + 0xbfd5604012f467b4, 0x3fee298f4439197a, // -0.334, 0.94257 + 0xbfd577eeec151e47, 0x3fee255a77a63bb8, // -0.33545, 0.94206 + 0xbfd58f9a75ab1fdd, 0x3fee212104f686e5, // -0.33689, 0.94154 + 0xbfd5a742ac0ff78d, 0x3fee1ce2ecd0c0d8, // -0.33833, 0.94103 + 0xbfd5bee78b9db3b6, 0x3fee18a02fdc66d9, // -0.33978, 0.94051 + 0xbfd5d68910aee686, 0x3fee1458cec1ad83, // -0.34122, 0.93998 + 0xbfd5ee27379ea693, 0x3fee100cca2980ac, // -0.34266, 0.93946 + 0xbfd605c1fcc88f63, 0x3fee0bbc22bd8349, // -0.3441, 0.93893 + 0xbfd61d595c88c203, 0x3fee0766d9280f54, // -0.34554, 0.9384 + 0xbfd634ed533be58e, 0x3fee030cee1435b8, // -0.34698, 0.93787 + 0xbfd64c7ddd3f27c6, 0x3fedfeae622dbe2b, // -0.34842, 0.93734 + 0xbfd6640af6f03d9e, 0x3fedfa4b3621271d, // -0.34986, 0.9368 + 0xbfd67b949cad63ca, 0x3fedf5e36a9ba59c, // -0.35129, 0.93627 + 0xbfd6931acad55f51, 0x3fedf177004b2534, // -0.35273, 0.93573 + 0xbfd6aa9d7dc77e16, 0x3feded05f7de47da, // -0.35416, 0.93518 + 0xbfd6c21cb1e39771, 0x3fede890520465ce, // -0.3556, 0.93464 + 0xbfd6d998638a0cb5, 0x3fede4160f6d8d81, // -0.35703, 0.93409 + 0xbfd6f1108f1bc9c5, 0x3feddf9730ca837b, // -0.35846, 0.93354 + 0xbfd7088530fa459e, 0x3feddb13b6ccc23d, // -0.3599, 0.93299 + 0xbfd71ff6458782ec, 0x3fedd68ba2267a25, // -0.36133, 0.93244 + 0xbfd73763c9261092, 0x3fedd1fef38a915a, // -0.36276, 0.93188 + 0xbfd74ecdb8390a3e, 0x3fedcd6dabaca3a5, // -0.36418, 0.93133 + 0xbfd766340f2418f6, 0x3fedc8d7cb410260, // -0.36561, 0.93077 + 0xbfd77d96ca4b73a6, 0x3fedc43d52fcb453, // -0.36704, 0.93021 + 0xbfd794f5e613dfae, 0x3fedbf9e4395759a, // -0.36847, 0.92964 + 0xbfd7ac515ee2b172, 0x3fedbafa9dc1b78d, // -0.36989, 0.92907 + 0xbfd7c3a9311dcce7, 0x3fedb6526238a09b, // -0.37132, 0.92851 + 0xbfd7dafd592ba621, 0x3fedb1a591b20c38, // -0.37274, 0.92794 + 0xbfd7f24dd37341e3, 0x3fedacf42ce68ab9, // -0.37416, 0.92736 + 0xbfd8099a9c5c362d, 0x3feda83e348f613b, // -0.37559, 0.92679 + 0xbfd820e3b04eaac4, 0x3feda383a9668988, // -0.37701, 0.92621 + 0xbfd838290bb359c8, 0x3fed9ec48c26b1f3, // -0.37843, 0.92563 + 0xbfd84f6aaaf3903f, 0x3fed9a00dd8b3d46, // -0.37985, 0.92505 + 0xbfd866a88a792ea0, 0x3fed95389e50429b, // -0.38127, 0.92447 + 0xbfd87de2a6aea963, 0x3fed906bcf328d46, // -0.38268, 0.92388 + 0xbfd89518fbff098e, 0x3fed8b9a70ef9cb4, // -0.3841, 0.92329 + 0xbfd8ac4b86d5ed44, 0x3fed86c48445a450, // -0.38552, 0.9227 + 0xbfd8c37a439f884f, 0x3fed81ea09f38b63, // -0.38693, 0.92211 + 0xbfd8daa52ec8a4af, 0x3fed7d0b02b8ecf9, // -0.38835, 0.92151 + 0xbfd8f1cc44bea329, 0x3fed78276f5617c6, // -0.38976, 0.92092 + 0xbfd908ef81ef7bd1, 0x3fed733f508c0dff, // -0.39117, 0.92032 + 0xbfd9200ee2c9be97, 0x3fed6e52a71c8547, // -0.39258, 0.91972 + 0xbfd9372a63bc93d7, 0x3fed696173c9e68b, // -0.39399, 0.91911 + 0xbfd94e420137bce3, 0x3fed646bb7574de5, // -0.3954, 0.91851 + 0xbfd96555b7ab948f, 0x3fed5f7172888a7f, // -0.39681, 0.9179 + 0xbfd97c6583890fc2, 0x3fed5a72a6221e73, // -0.39822, 0.91729 + 0xbfd993716141bdfe, 0x3fed556f52e93eb1, // -0.39962, 0.91668 + 0xbfd9aa794d47c9ee, 0x3fed506779a3d2d9, // -0.40103, 0.91606 + 0xbfd9c17d440df9f2, 0x3fed4b5b1b187524, // -0.40243, 0.91545 + 0xbfd9d87d4207b0ab, 0x3fed464a380e7242, // -0.40384, 0.91483 + 0xbfd9ef7943a8ed8a, 0x3fed4134d14dc93a, // -0.40524, 0.91421 + 0xbfda067145664d57, 0x3fed3c1ae79f2b4e, // -0.40664, 0.91359 + 0xbfda1d6543b50ac0, 0x3fed36fc7bcbfbdc, // -0.40804, 0.91296 + 0xbfda34553b0afee5, 0x3fed31d98e9e503a, // -0.40944, 0.91234 + 0xbfda4b4127dea1e4, 0x3fed2cb220e0ef9f, // -0.41084, 0.91171 + 0xbfda622906a70b63, 0x3fed2786335f52fc, // -0.41224, 0.91107 + 0xbfda790cd3dbf31a, 0x3fed2255c6e5a4e1, // -0.41364, 0.91044 + 0xbfda8fec8bf5b166, 0x3fed1d20dc40c15c, // -0.41503, 0.90981 + 0xbfdaa6c82b6d3fc9, 0x3fed17e7743e35dc, // -0.41643, 0.90917 + 0xbfdabd9faebc3980, 0x3fed12a98fac410c, // -0.41782, 0.90853 + 0xbfdad473125cdc08, 0x3fed0d672f59d2b9, // -0.41922, 0.90789 + 0xbfdaeb4252ca07ab, 0x3fed082054168bac, // -0.42061, 0.90724 + 0xbfdb020d6c7f4009, 0x3fed02d4feb2bd92, // -0.422, 0.9066 + 0xbfdb18d45bf8aca6, 0x3fecfd852fff6ad4, // -0.42339, 0.90595 + 0xbfdb2f971db31972, 0x3fecf830e8ce467b, // -0.42478, 0.9053 + 0xbfdb4655ae2bf757, 0x3fecf2d829f1b40e, // -0.42617, 0.90464 + 0xbfdb5d1009e15cc0, 0x3feced7af43cc773, // -0.42756, 0.90399 + 0xbfdb73c62d520624, 0x3fece819488344ce, // -0.42894, 0.90333 + 0xbfdb8a7814fd5693, 0x3fece2b32799a060, // -0.43033, 0.90267 + 0xbfdba125bd63583e, 0x3fecdd489254fe65, // -0.43171, 0.90201 + 0xbfdbb7cf2304bd01, 0x3fecd7d9898b32f6, // -0.43309, 0.90135 + 0xbfdbce744262deee, 0x3fecd2660e12c1e6, // -0.43448, 0.90068 + 0xbfdbe51517ffc0d9, 0x3fecccee20c2de9f, // -0.43586, 0.90002 + 0xbfdbfbb1a05e0edc, 0x3fecc771c2736c09, // -0.43724, 0.89935 + 0xbfdc1249d8011ee7, 0x3fecc1f0f3fcfc5c, // -0.43862, 0.89867 + 0xbfdc28ddbb6cf145, 0x3fecbc6bb638d10b, // -0.43999, 0.898 + 0xbfdc3f6d47263129, 0x3fecb6e20a00da99, // -0.44137, 0.89732 + 0xbfdc55f877b23537, 0x3fecb153f02fb87d, // -0.44275, 0.89665 + 0xbfdc6c7f4997000a, 0x3fecabc169a0b901, // -0.44412, 0.89597 + 0xbfdc8301b95b40c2, 0x3feca62a772fd919, // -0.4455, 0.89528 + 0xbfdc997fc3865388, 0x3feca08f19b9c449, // -0.44687, 0.8946 + 0xbfdcaff964a0421d, 0x3fec9aef521bd480, // -0.44824, 0.89391 + 0xbfdcc66e9931c45d, 0x3fec954b213411f5, // -0.44961, 0.89322 + 0xbfdcdcdf5dc440ce, 0x3fec8fa287e13305, // -0.45098, 0.89253 + 0xbfdcf34baee1cd21, 0x3fec89f587029c13, // -0.45235, 0.89184 + 0xbfdd09b389152ec1, 0x3fec84441f785f61, // -0.45372, 0.89115 + 0xbfdd2016e8e9db5b, 0x3fec7e8e52233cf3, // -0.45508, 0.89045 + 0xbfdd3675caebf962, 0x3fec78d41fe4a267, // -0.45645, 0.88975 + 0xbfdd4cd02ba8609c, 0x3fec7315899eaad7, // -0.45781, 0.88905 + 0xbfdd632607ac9aa9, 0x3fec6d5290341eb2, // -0.45918, 0.88835 + 0xbfdd79775b86e389, 0x3fec678b3488739b, // -0.46054, 0.88764 + 0xbfdd8fc423c62a25, 0x3fec61bf777fcc48, // -0.4619, 0.88693 + 0xbfdda60c5cfa10d8, 0x3fec5bef59fef85a, // -0.46326, 0.88622 + 0xbfddbc5003b2edf8, 0x3fec561adceb743e, // -0.46462, 0.88551 + 0xbfddd28f1481cc58, 0x3fec5042012b6907, // -0.46598, 0.8848 + 0xbfdde8c98bf86bd6, 0x3fec4a64c7a5ac4c, // -0.46733, 0.88408 + 0xbfddfeff66a941de, 0x3fec44833141c004, // -0.46869, 0.88336 + 0xbfde1530a12779f4, 0x3fec3e9d3ee7d262, // -0.47004, 0.88264 + 0xbfde2b5d3806f63b, 0x3fec38b2f180bdb1, // -0.4714, 0.88192 + 0xbfde418527dc4ffa, 0x3fec32c449f60831, // -0.47275, 0.8812 + 0xbfde57a86d3cd824, 0x3fec2cd14931e3f1, // -0.4741, 0.88047 + 0xbfde6dc704be97e2, 0x3fec26d9f01f2eaf, // -0.47545, 0.87974 + 0xbfde83e0eaf85113, 0x3fec20de3fa971b0, // -0.4768, 0.87901 + 0xbfde99f61c817eda, 0x3fec1ade38bce19b, // -0.47815, 0.87828 + 0xbfdeb00695f25620, 0x3fec14d9dc465e58, // -0.47949, 0.87755 + 0xbfdec61253e3c61b, 0x3fec0ed12b3372e9, // -0.48084, 0.87681 + 0xbfdedc1952ef78d5, 0x3fec08c426725549, // -0.48218, 0.87607 + 0xbfdef21b8fafd3b5, 0x3fec02b2cef1e641, // -0.48353, 0.87533 + 0xbfdf081906bff7fd, 0x3febfc9d25a1b147, // -0.48487, 0.87459 + 0xbfdf1e11b4bbc35c, 0x3febf6832b71ec5b, // -0.48621, 0.87384 + 0xbfdf3405963fd068, 0x3febf064e15377dd, // -0.48755, 0.87309 + 0xbfdf49f4a7e97729, 0x3febea424837de6d, // -0.48889, 0.87235 + 0xbfdf5fdee656cda3, 0x3febe41b611154c1, // -0.49023, 0.8716 + 0xbfdf75c44e26a852, 0x3febddf02cd2b983, // -0.49156, 0.87084 + 0xbfdf8ba4dbf89aba, 0x3febd7c0ac6f952a, // -0.4929, 0.87009 + 0xbfdfa1808c6cf7e0, 0x3febd18ce0dc19d6, // -0.49423, 0.86933 + 0xbfdfb7575c24d2de, 0x3febcb54cb0d2327, // -0.49557, 0.86857 + 0xbfdfcd2947c1ff57, 0x3febc5186bf8361d, // -0.4969, 0.86781 + 0xbfdfe2f64be7120f, 0x3febbed7c49380ea, // -0.49823, 0.86705 + 0xbfdff8be6537615e, 0x3febb892d5d5dad5, // -0.49956, 0.86628 + 0xbfe00740c82b82e0, 0x3febb249a0b6c40d, // -0.50089, 0.86551 + 0xbfe0121fe4f56d2c, 0x3febabfc262e6586, // -0.50221, 0.86474 + 0xbfe01cfc874c3eb7, 0x3feba5aa673590d2, // -0.50354, 0.86397 + 0xbfe027d6ad83287e, 0x3feb9f5464c5bffc, // -0.50486, 0.8632 + 0xbfe032ae55edbd95, 0x3feb98fa1fd9155e, // -0.50619, 0.86242 + 0xbfe03d837edff370, 0x3feb929b996a5b7f, // -0.50751, 0.86165 + 0xbfe0485626ae221a, 0x3feb8c38d27504e9, // -0.50883, 0.86087 + 0xbfe053264bad0483, 0x3feb85d1cbf52c02, // -0.51015, 0.86009 + 0xbfe05df3ec31b8b6, 0x3feb7f6686e792ea, // -0.51147, 0.8593 + 0xbfe068bf0691c028, 0x3feb78f70449a34b, // -0.51279, 0.85852 + 0xbfe073879922ffed, 0x3feb728345196e3e, // -0.5141, 0.85773 + 0xbfe07e4da23bc102, 0x3feb6c0b4a55ac17, // -0.51542, 0.85694 + 0xbfe089112032b08c, 0x3feb658f14fdbc47, // -0.51673, 0.85615 + 0xbfe093d2115ee018, 0x3feb5f0ea611a532, // -0.51804, 0.85535 + 0xbfe09e907417c5e1, 0x3feb5889fe921405, // -0.51936, 0.85456 + 0xbfe0a94c46b53d0b, 0x3feb52011f805c92, // -0.52067, 0.85376 + 0xbfe0b405878f85ec, 0x3feb4b7409de7925, // -0.52198, 0.85296 + 0xbfe0bebc34ff4646, 0x3feb44e2beaf0a61, // -0.52328, 0.85216 + 0xbfe0c9704d5d898f, 0x3feb3e4d3ef55712, // -0.52459, 0.85136 + 0xbfe0d421cf03c12b, 0x3feb37b38bb54c09, // -0.5259, 0.85055 + 0xbfe0ded0b84bc4b5, 0x3feb3115a5f37bf4, // -0.5272, 0.84974 + 0xbfe0e97d078fd23b, 0x3feb2a738eb51f33, // -0.5285, 0.84893 + 0xbfe0f426bb2a8e7d, 0x3feb23cd470013b4, // -0.5298, 0.84812 + 0xbfe0fecdd1770537, 0x3feb1d22cfdadcc6, // -0.5311, 0.84731 + 0xbfe1097248d0a956, 0x3feb16742a4ca2f5, // -0.5324, 0.84649 + 0xbfe114141f935545, 0x3feb0fc1575d33db, // -0.5337, 0.84567 + 0xbfe11eb3541b4b22, 0x3feb090a58150200, // -0.535, 0.84485 + 0xbfe1294fe4c5350a, 0x3feb024f2d7d24a9, // -0.53629, 0.84403 + 0xbfe133e9cfee254e, 0x3feafb8fd89f57b6, // -0.53759, 0.84321 + 0xbfe13e8113f396c1, 0x3feaf4cc5a85fb73, // -0.53888, 0.84238 + 0xbfe14915af336ceb, 0x3feaee04b43c1474, // -0.54017, 0.84155 + 0xbfe153a7a00bf453, 0x3feae738e6cd4b67, // -0.54146, 0.84073 + 0xbfe15e36e4dbe2bc, 0x3feae068f345ecef, // -0.54275, 0.83989 + 0xbfe168c37c025764, 0x3fead994dab2e979, // -0.54404, 0.83906 + 0xbfe1734d63dedb49, 0x3fead2bc9e21d511, // -0.54532, 0.83822 + 0xbfe17dd49ad16161, 0x3feacbe03ea0e73b, // -0.54661, 0.83739 + 0xbfe188591f3a46e5, 0x3feac4ffbd3efac8, // -0.54789, 0.83655 + 0xbfe192daef7a5386, 0x3feabe1b1b0b8dac, // -0.54918, 0.83571 + 0xbfe19d5a09f2b9b8, 0x3feab7325916c0d4, // -0.55046, 0.83486 + 0xbfe1a7d66d0516e6, 0x3feab045787157ff, // -0.55174, 0.83402 + 0xbfe1b250171373be, 0x3feaa9547a2cb98e, // -0.55302, 0.83317 + 0xbfe1bcc706804467, 0x3feaa25f5f5aee60, // -0.55429, 0.83232 + 0xbfe1c73b39ae68c8, 0x3fea9b66290ea1a3, // -0.55557, 0.83147 + 0xbfe1d1acaf012cc2, 0x3fea9468d85b20ae, // -0.55685, 0.83062 + 0xbfe1dc1b64dc4872, 0x3fea8d676e545ad2, // -0.55812, 0.82976 + 0xbfe1e68759a3e074, 0x3fea8661ec0ee133, // -0.55939, 0.8289 + 0xbfe1f0f08bbc861b, 0x3fea7f58529fe69d, // -0.56066, 0.82805 + 0xbfe1fb56f98b37b8, 0x3fea784aa31d3f55, // -0.56193, 0.82718 + 0xbfe205baa17560d6, 0x3fea7138de9d60f5, // -0.5632, 0.82632 + 0xbfe2101b81e0da78, 0x3fea6a230637623b, // -0.56447, 0.82546 + 0xbfe21a799933eb58, 0x3fea63091b02fae2, // -0.56573, 0.82459 + 0xbfe224d4e5d5482e, 0x3fea5beb1e188375, // -0.567, 0.82372 + 0xbfe22f2d662c13e1, 0x3fea54c91090f524, // -0.56826, 0.82285 + 0xbfe23983189fdfd5, 0x3fea4da2f385e997, // -0.56952, 0.82198 + 0xbfe243d5fb98ac1f, 0x3fea4678c8119ac8, // -0.57078, 0.8211 + 0xbfe24e260d7ee7c9, 0x3fea3f4a8f4ee2d2, // -0.57204, 0.82023 + 0xbfe258734cbb7110, 0x3fea38184a593bc6, // -0.5733, 0.81935 + 0xbfe262bdb7b795a2, 0x3fea30e1fa4cbf81, // -0.57455, 0.81847 + 0xbfe26d054cdd12df, 0x3fea29a7a0462782, // -0.57581, 0.81758 + 0xbfe2774a0a961612, 0x3fea22693d62ccb9, // -0.57706, 0.8167 + 0xbfe2818bef4d3cba, 0x3fea1b26d2c0a75e, // -0.57831, 0.81581 + 0xbfe28bcaf96d94ba, 0x3fea13e0617e4ec7, // -0.57956, 0.81493 + 0xbfe2960727629ca8, 0x3fea0c95eabaf937, // -0.58081, 0.81404 + 0xbfe2a040779843fb, 0x3fea05476f967bb5, // -0.58206, 0.81314 + 0xbfe2aa76e87aeb58, 0x3fe9fdf4f13149de, // -0.58331, 0.81225 + 0xbfe2b4aa787764c4, 0x3fe9f69e70ac75bc, // -0.58455, 0.81135 + 0xbfe2bedb25faf3ea, 0x3fe9ef43ef29af94, // -0.5858, 0.81046 + 0xbfe2c908ef734e57, 0x3fe9e7e56dcb45bd, // -0.58704, 0.80956 + 0xbfe2d333d34e9bb7, 0x3fe9e082edb42472, // -0.58828, 0.80866 + 0xbfe2dd5bcffb7616, 0x3fe9d91c7007d5a6, // -0.58952, 0.80775 + 0xbfe2e780e3e8ea16, 0x3fe9d1b1f5ea80d6, // -0.59076, 0.80685 + 0xbfe2f1a30d86773a, 0x3fe9ca438080eadb, // -0.592, 0.80594 + 0xbfe2fbc24b441015, 0x3fe9c2d110f075c3, // -0.59323, 0.80503 + 0xbfe305de9b921a94, 0x3fe9bb5aa85f2098, // -0.59447, 0.80412 + 0xbfe30ff7fce17035, 0x3fe9b3e047f38741, // -0.5957, 0.80321 + 0xbfe31a0e6da35e44, 0x3fe9ac61f0d4e247, // -0.59693, 0.80229 + 0xbfe32421ec49a620, 0x3fe9a4dfa42b06b2, // -0.59816, 0.80138 + 0xbfe32e3277467d6b, 0x3fe99d59631e65d5, // -0.59939, 0.80046 + 0xbfe338400d0c8e57, 0x3fe995cf2ed80d22, // -0.60062, 0.79954 + 0xbfe3424aac0ef7d6, 0x3fe98e410881a600, // -0.60184, 0.79861 + 0xbfe34c5252c14de1, 0x3fe986aef1457594, // -0.60307, 0.79769 + 0xbfe35656ff9799ae, 0x3fe97f18ea4e5c9e, // -0.60429, 0.79676 + 0xbfe36058b10659f3, 0x3fe9777ef4c7d742, // -0.60551, 0.79584 + 0xbfe36a576582831b, 0x3fe96fe111ddfce0, // -0.60673, 0.79491 + 0xbfe374531b817f8d, 0x3fe9683f42bd7fe1, // -0.60795, 0.79398 + 0xbfe37e4bd1792fe2, 0x3fe960998893ad8c, // -0.60917, 0.79304 + 0xbfe3884185dfeb22, 0x3fe958efe48e6dd7, // -0.61038, 0.79211 + 0xbfe39234372c7f04, 0x3fe9514257dc4335, // -0.6116, 0.79117 + 0xbfe39c23e3d63029, 0x3fe94990e3ac4a6c, // -0.61281, 0.79023 + 0xbfe3a6108a54ba58, 0x3fe941db892e3a65, // -0.61402, 0.78929 + 0xbfe3affa292050b9, 0x3fe93a22499263fc, // -0.61523, 0.78835 + 0xbfe3b9e0beb19e18, 0x3fe932652609b1cf, // -0.61644, 0.7874 + 0xbfe3c3c44981c517, 0x3fe92aa41fc5a815, // -0.61765, 0.78646 + 0xbfe3cda4c80a6076, 0x3fe922df37f8646a, // -0.61885, 0.78551 + 0xbfe3d78238c58343, 0x3fe91b166fd49da2, // -0.62006, 0.78456 + 0xbfe3e15c9a2db922, 0x3fe91349c88da398, // -0.62126, 0.7836 + 0xbfe3eb33eabe0680, 0x3fe90b7943575efe, // -0.62246, 0.78265 + 0xbfe3f50828f1e8d2, 0x3fe903a4e1665133, // -0.62366, 0.78169 + 0xbfe3fed9534556d4, 0x3fe8fbcca3ef940d, // -0.62486, 0.78074 + 0xbfe408a76834c0c0, 0x3fe8f3f08c28d9ac, // -0.62606, 0.77978 + 0xbfe41272663d108c, 0x3fe8ec109b486c49, // -0.62725, 0.77882 + 0xbfe41c3a4bdbaa26, 0x3fe8e42cd2852e0a, // -0.62845, 0.77785 + 0xbfe425ff178e6bb1, 0x3fe8dc45331698cc, // -0.62964, 0.77689 + 0xbfe42fc0c7d3adbb, 0x3fe8d459be34bdfa, // -0.63083, 0.77592 + 0xbfe4397f5b2a4380, 0x3fe8cc6a75184655, // -0.63202, 0.77495 + 0xbfe4433ad0117b1d, 0x3fe8c47758fa71cb, // -0.63321, 0.77398 + 0xbfe44cf325091dd6, 0x3fe8bc806b151741, // -0.63439, 0.77301 + 0xbfe456a858917046, 0x3fe8b485aca2a468, // -0.63558, 0.77204 + 0xbfe4605a692b32a2, 0x3fe8ac871ede1d88, // -0.63676, 0.77106 + 0xbfe46a095557a0f1, 0x3fe8a484c3031d50, // -0.63794, 0.77008 + 0xbfe473b51b987347, 0x3fe89c7e9a4dd4ab, // -0.63912, 0.7691 + 0xbfe47d5dba6fde01, 0x3fe89474a5fb0a84, // -0.6403, 0.76812 + 0xbfe48703306091fe, 0x3fe88c66e7481ba1, // -0.64148, 0.76714 + 0xbfe490a57bedbcdf, 0x3fe884555f72fa6b, // -0.64266, 0.76615 + 0xbfe49a449b9b0938, 0x3fe87c400fba2ebf, // -0.64383, 0.76517 + 0xbfe4a3e08dec9ed6, 0x3fe87426f95cd5bd, // -0.645, 0.76418 + 0xbfe4ad79516722f0, 0x3fe86c0a1d9aa195, // -0.64618, 0.76319 + 0xbfe4b70ee48fb869, 0x3fe863e97db3d95a, // -0.64735, 0.7622 + 0xbfe4c0a145ec0004, 0x3fe85bc51ae958cc, // -0.64851, 0.7612 + 0xbfe4ca30740218a3, 0x3fe8539cf67c9029, // -0.64968, 0.76021 + 0xbfe4d3bc6d589f80, 0x3fe84b7111af83f9, // -0.65085, 0.75921 + 0xbfe4dd453076b064, 0x3fe843416dc4cce2, // -0.65201, 0.75821 + 0xbfe4e6cabbe3e5e9, 0x3fe83b0e0bff976e, // -0.65317, 0.75721 + 0xbfe4f04d0e2859aa, 0x3fe832d6eda3a3e0, // -0.65433, 0.75621 + 0xbfe4f9cc25cca486, 0x3fe82a9c13f545ff, // -0.65549, 0.7552 + 0xbfe503480159ded2, 0x3fe8225d803964e5, // -0.65665, 0.75419 + 0xbfe50cc09f59a09b, 0x3fe81a1b33b57acc, // -0.65781, 0.75319 + 0xbfe51635fe5601d7, 0x3fe811d52faf94dc, // -0.65896, 0.75218 + 0xbfe51fa81cd99aa6, 0x3fe8098b756e52fa, // -0.66011, 0.75117 + 0xbfe52916f96f8388, 0x3fe8013e0638e795, // -0.66127, 0.75015 + 0xbfe5328292a35596, 0x3fe7f8ece3571771, // -0.66242, 0.74914 + 0xbfe53beae7012abe, 0x3fe7f0980e113978, // -0.66356, 0.74812 + 0xbfe5454ff5159dfb, 0x3fe7e83f87b03686, // -0.66471, 0.7471 + 0xbfe54eb1bb6dcb8f, 0x3fe7dfe3517d8937, // -0.66586, 0.74608 + 0xbfe5581038975137, 0x3fe7d7836cc33db2, // -0.667, 0.74506 + 0xbfe5616b6b204e6e, 0x3fe7cf1fdacbf179, // -0.66814, 0.74403 + 0xbfe56ac35197649e, 0x3fe7c6b89ce2d333, // -0.66928, 0.74301 + 0xbfe57417ea8bb75c, 0x3fe7be4db453a27c, // -0.67042, 0.74198 + 0xbfe57d69348cec9f, 0x3fe7b5df226aafb0, // -0.67156, 0.74095 + 0xbfe586b72e2b2cfd, 0x3fe7ad6ce874dbb6, // -0.67269, 0.73992 + 0xbfe59001d5f723df, 0x3fe7a4f707bf97d2, // -0.67383, 0.73889 + 0xbfe599492a81ffbc, 0x3fe79c7d8198e56e, // -0.67496, 0.73785 + 0xbfe5a28d2a5d7250, 0x3fe79400574f55e4, // -0.67609, 0.73682 + 0xbfe5abcdd41bb0d8, 0x3fe78b7f8a320a52, // -0.67722, 0.73578 + 0xbfe5b50b264f7448, 0x3fe782fb1b90b35b, // -0.67835, 0.73474 + 0xbfe5be451f8bf980, 0x3fe77a730cbb9100, // -0.67948, 0.7337 + 0xbfe5c77bbe65018c, 0x3fe771e75f037261, // -0.6806, 0.73265 + 0xbfe5d0af016ed1d4, 0x3fe7695813b9b594, // -0.68172, 0.73161 + 0xbfe5d9dee73e345c, 0x3fe760c52c304764, // -0.68285, 0.73056 + 0xbfe5e30b6e6877f3, 0x3fe7582ea9b9a329, // -0.68397, 0.72951 + 0xbfe5ec3495837074, 0x3fe74f948da8d28d, // -0.68508, 0.72846 + 0xbfe5f55a5b2576f8, 0x3fe746f6d9516d59, // -0.6862, 0.72741 + 0xbfe5fe7cbde56a0f, 0x3fe73e558e079942, // -0.68732, 0.72636 + 0xbfe6079bbc5aadfa, 0x3fe735b0ad2009b2, // -0.68843, 0.7253 + 0xbfe610b7551d2cde, 0x3fe72d0837efff97, // -0.68954, 0.72425 + 0xbfe619cf86c55702, 0x3fe7245c2fcd492a, // -0.69065, 0.72319 + 0xbfe622e44fec22ff, 0x3fe71bac960e41bf, // -0.69176, 0.72213 + 0xbfe62bf5af2b0dfd, 0x3fe712f96c09d18d, // -0.69287, 0.72107 + 0xbfe63503a31c1be8, 0x3fe70a42b3176d7a, // -0.69397, 0.72 + 0xbfe63e0e2a59d7aa, 0x3fe701886c8f16e6, // -0.69508, 0.71894 + 0xbfe64715437f535b, 0x3fe6f8ca99c95b75, // -0.69618, 0.71787 + 0xbfe65018ed28287f, 0x3fe6f0093c1f54de, // -0.69728, 0.7168 + 0xbfe6591925f0783e, 0x3fe6e74454eaa8ae, // -0.69838, 0.71573 + 0xbfe66215ec74eb91, 0x3fe6de7be585881d, // -0.69947, 0.71466 + 0xbfe66b0f3f52b386, 0x3fe6d5afef4aafcc, // -0.70057, 0.71358 + 0xbfe674051d27896c, 0x3fe6cce07395679f, // -0.70166, 0.71251 + 0xbfe67cf78491af10, 0x3fe6c40d73c18275, // -0.70275, 0.71143 + 0xbfe685e6742feeef, 0x3fe6bb36f12b5e06, // -0.70385, 0.71035 + 0xbfe68ed1eaa19c71, 0x3fe6b25ced2fe29c, // -0.70493, 0.70927 + 0xbfe697b9e686941c, 0x3fe6a97f692c82ea, // -0.70602, 0.70819 + 0xbfe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // -0.70711, 0.70711 + 0xbfe6a97f692c82ea, 0x3fe697b9e686941c, // -0.70819, 0.70602 + 0xbfe6b25ced2fe29c, 0x3fe68ed1eaa19c71, // -0.70927, 0.70493 + 0xbfe6bb36f12b5e06, 0x3fe685e6742feeef, // -0.71035, 0.70385 + 0xbfe6c40d73c18275, 0x3fe67cf78491af10, // -0.71143, 0.70275 + 0xbfe6cce07395679f, 0x3fe674051d27896c, // -0.71251, 0.70166 + 0xbfe6d5afef4aafcc, 0x3fe66b0f3f52b386, // -0.71358, 0.70057 + 0xbfe6de7be585881d, 0x3fe66215ec74eb91, // -0.71466, 0.69947 + 0xbfe6e74454eaa8ae, 0x3fe6591925f0783e, // -0.71573, 0.69838 + 0xbfe6f0093c1f54de, 0x3fe65018ed28287f, // -0.7168, 0.69728 + 0xbfe6f8ca99c95b75, 0x3fe64715437f535b, // -0.71787, 0.69618 + 0xbfe701886c8f16e6, 0x3fe63e0e2a59d7aa, // -0.71894, 0.69508 + 0xbfe70a42b3176d7a, 0x3fe63503a31c1be8, // -0.72, 0.69397 + 0xbfe712f96c09d18d, 0x3fe62bf5af2b0dfd, // -0.72107, 0.69287 + 0xbfe71bac960e41bf, 0x3fe622e44fec22ff, // -0.72213, 0.69176 + 0xbfe7245c2fcd492a, 0x3fe619cf86c55702, // -0.72319, 0.69065 + 0xbfe72d0837efff97, 0x3fe610b7551d2cde, // -0.72425, 0.68954 + 0xbfe735b0ad2009b2, 0x3fe6079bbc5aadfa, // -0.7253, 0.68843 + 0xbfe73e558e079942, 0x3fe5fe7cbde56a0f, // -0.72636, 0.68732 + 0xbfe746f6d9516d59, 0x3fe5f55a5b2576f8, // -0.72741, 0.6862 + 0xbfe74f948da8d28d, 0x3fe5ec3495837074, // -0.72846, 0.68508 + 0xbfe7582ea9b9a329, 0x3fe5e30b6e6877f3, // -0.72951, 0.68397 + 0xbfe760c52c304764, 0x3fe5d9dee73e345c, // -0.73056, 0.68285 + 0xbfe7695813b9b594, 0x3fe5d0af016ed1d4, // -0.73161, 0.68172 + 0xbfe771e75f037261, 0x3fe5c77bbe65018c, // -0.73265, 0.6806 + 0xbfe77a730cbb9100, 0x3fe5be451f8bf980, // -0.7337, 0.67948 + 0xbfe782fb1b90b35b, 0x3fe5b50b264f7448, // -0.73474, 0.67835 + 0xbfe78b7f8a320a52, 0x3fe5abcdd41bb0d8, // -0.73578, 0.67722 + 0xbfe79400574f55e4, 0x3fe5a28d2a5d7250, // -0.73682, 0.67609 + 0xbfe79c7d8198e56e, 0x3fe599492a81ffbc, // -0.73785, 0.67496 + 0xbfe7a4f707bf97d2, 0x3fe59001d5f723df, // -0.73889, 0.67383 + 0xbfe7ad6ce874dbb6, 0x3fe586b72e2b2cfd, // -0.73992, 0.67269 + 0xbfe7b5df226aafb0, 0x3fe57d69348cec9f, // -0.74095, 0.67156 + 0xbfe7be4db453a27c, 0x3fe57417ea8bb75c, // -0.74198, 0.67042 + 0xbfe7c6b89ce2d333, 0x3fe56ac35197649e, // -0.74301, 0.66928 + 0xbfe7cf1fdacbf179, 0x3fe5616b6b204e6e, // -0.74403, 0.66814 + 0xbfe7d7836cc33db2, 0x3fe5581038975137, // -0.74506, 0.667 + 0xbfe7dfe3517d8937, 0x3fe54eb1bb6dcb8f, // -0.74608, 0.66586 + 0xbfe7e83f87b03686, 0x3fe5454ff5159dfb, // -0.7471, 0.66471 + 0xbfe7f0980e113978, 0x3fe53beae7012abe, // -0.74812, 0.66356 + 0xbfe7f8ece3571771, 0x3fe5328292a35596, // -0.74914, 0.66242 + 0xbfe8013e0638e795, 0x3fe52916f96f8388, // -0.75015, 0.66127 + 0xbfe8098b756e52fa, 0x3fe51fa81cd99aa6, // -0.75117, 0.66011 + 0xbfe811d52faf94dc, 0x3fe51635fe5601d7, // -0.75218, 0.65896 + 0xbfe81a1b33b57acc, 0x3fe50cc09f59a09b, // -0.75319, 0.65781 + 0xbfe8225d803964e5, 0x3fe503480159ded2, // -0.75419, 0.65665 + 0xbfe82a9c13f545ff, 0x3fe4f9cc25cca486, // -0.7552, 0.65549 + 0xbfe832d6eda3a3e0, 0x3fe4f04d0e2859aa, // -0.75621, 0.65433 + 0xbfe83b0e0bff976e, 0x3fe4e6cabbe3e5e9, // -0.75721, 0.65317 + 0xbfe843416dc4cce2, 0x3fe4dd453076b064, // -0.75821, 0.65201 + 0xbfe84b7111af83f9, 0x3fe4d3bc6d589f80, // -0.75921, 0.65085 + 0xbfe8539cf67c9029, 0x3fe4ca30740218a3, // -0.76021, 0.64968 + 0xbfe85bc51ae958cc, 0x3fe4c0a145ec0004, // -0.7612, 0.64851 + 0xbfe863e97db3d95a, 0x3fe4b70ee48fb869, // -0.7622, 0.64735 + 0xbfe86c0a1d9aa195, 0x3fe4ad79516722f0, // -0.76319, 0.64618 + 0xbfe87426f95cd5bd, 0x3fe4a3e08dec9ed6, // -0.76418, 0.645 + 0xbfe87c400fba2ebf, 0x3fe49a449b9b0938, // -0.76517, 0.64383 + 0xbfe884555f72fa6b, 0x3fe490a57bedbcdf, // -0.76615, 0.64266 + 0xbfe88c66e7481ba1, 0x3fe48703306091fe, // -0.76714, 0.64148 + 0xbfe89474a5fb0a84, 0x3fe47d5dba6fde01, // -0.76812, 0.6403 + 0xbfe89c7e9a4dd4ab, 0x3fe473b51b987347, // -0.7691, 0.63912 + 0xbfe8a484c3031d50, 0x3fe46a095557a0f1, // -0.77008, 0.63794 + 0xbfe8ac871ede1d88, 0x3fe4605a692b32a2, // -0.77106, 0.63676 + 0xbfe8b485aca2a468, 0x3fe456a858917046, // -0.77204, 0.63558 + 0xbfe8bc806b151741, 0x3fe44cf325091dd6, // -0.77301, 0.63439 + 0xbfe8c47758fa71cb, 0x3fe4433ad0117b1d, // -0.77398, 0.63321 + 0xbfe8cc6a75184655, 0x3fe4397f5b2a4380, // -0.77495, 0.63202 + 0xbfe8d459be34bdfa, 0x3fe42fc0c7d3adbb, // -0.77592, 0.63083 + 0xbfe8dc45331698cc, 0x3fe425ff178e6bb1, // -0.77689, 0.62964 + 0xbfe8e42cd2852e0a, 0x3fe41c3a4bdbaa26, // -0.77785, 0.62845 + 0xbfe8ec109b486c49, 0x3fe41272663d108c, // -0.77882, 0.62725 + 0xbfe8f3f08c28d9ac, 0x3fe408a76834c0c0, // -0.77978, 0.62606 + 0xbfe8fbcca3ef940d, 0x3fe3fed9534556d4, // -0.78074, 0.62486 + 0xbfe903a4e1665133, 0x3fe3f50828f1e8d2, // -0.78169, 0.62366 + 0xbfe90b7943575efe, 0x3fe3eb33eabe0680, // -0.78265, 0.62246 + 0xbfe91349c88da398, 0x3fe3e15c9a2db922, // -0.7836, 0.62126 + 0xbfe91b166fd49da2, 0x3fe3d78238c58343, // -0.78456, 0.62006 + 0xbfe922df37f8646a, 0x3fe3cda4c80a6076, // -0.78551, 0.61885 + 0xbfe92aa41fc5a815, 0x3fe3c3c44981c517, // -0.78646, 0.61765 + 0xbfe932652609b1cf, 0x3fe3b9e0beb19e18, // -0.7874, 0.61644 + 0xbfe93a22499263fc, 0x3fe3affa292050b9, // -0.78835, 0.61523 + 0xbfe941db892e3a65, 0x3fe3a6108a54ba58, // -0.78929, 0.61402 + 0xbfe94990e3ac4a6c, 0x3fe39c23e3d63029, // -0.79023, 0.61281 + 0xbfe9514257dc4335, 0x3fe39234372c7f04, // -0.79117, 0.6116 + 0xbfe958efe48e6dd7, 0x3fe3884185dfeb22, // -0.79211, 0.61038 + 0xbfe960998893ad8c, 0x3fe37e4bd1792fe2, // -0.79304, 0.60917 + 0xbfe9683f42bd7fe1, 0x3fe374531b817f8d, // -0.79398, 0.60795 + 0xbfe96fe111ddfce0, 0x3fe36a576582831b, // -0.79491, 0.60673 + 0xbfe9777ef4c7d742, 0x3fe36058b10659f3, // -0.79584, 0.60551 + 0xbfe97f18ea4e5c9e, 0x3fe35656ff9799ae, // -0.79676, 0.60429 + 0xbfe986aef1457594, 0x3fe34c5252c14de1, // -0.79769, 0.60307 + 0xbfe98e410881a600, 0x3fe3424aac0ef7d6, // -0.79861, 0.60184 + 0xbfe995cf2ed80d22, 0x3fe338400d0c8e57, // -0.79954, 0.60062 + 0xbfe99d59631e65d5, 0x3fe32e3277467d6b, // -0.80046, 0.59939 + 0xbfe9a4dfa42b06b2, 0x3fe32421ec49a620, // -0.80138, 0.59816 + 0xbfe9ac61f0d4e247, 0x3fe31a0e6da35e44, // -0.80229, 0.59693 + 0xbfe9b3e047f38741, 0x3fe30ff7fce17035, // -0.80321, 0.5957 + 0xbfe9bb5aa85f2098, 0x3fe305de9b921a94, // -0.80412, 0.59447 + 0xbfe9c2d110f075c3, 0x3fe2fbc24b441015, // -0.80503, 0.59323 + 0xbfe9ca438080eadb, 0x3fe2f1a30d86773a, // -0.80594, 0.592 + 0xbfe9d1b1f5ea80d6, 0x3fe2e780e3e8ea16, // -0.80685, 0.59076 + 0xbfe9d91c7007d5a6, 0x3fe2dd5bcffb7616, // -0.80775, 0.58952 + 0xbfe9e082edb42472, 0x3fe2d333d34e9bb7, // -0.80866, 0.58828 + 0xbfe9e7e56dcb45bd, 0x3fe2c908ef734e57, // -0.80956, 0.58704 + 0xbfe9ef43ef29af94, 0x3fe2bedb25faf3ea, // -0.81046, 0.5858 + 0xbfe9f69e70ac75bc, 0x3fe2b4aa787764c4, // -0.81135, 0.58455 + 0xbfe9fdf4f13149de, 0x3fe2aa76e87aeb58, // -0.81225, 0.58331 + 0xbfea05476f967bb5, 0x3fe2a040779843fb, // -0.81314, 0.58206 + 0xbfea0c95eabaf937, 0x3fe2960727629ca8, // -0.81404, 0.58081 + 0xbfea13e0617e4ec7, 0x3fe28bcaf96d94ba, // -0.81493, 0.57956 + 0xbfea1b26d2c0a75e, 0x3fe2818bef4d3cba, // -0.81581, 0.57831 + 0xbfea22693d62ccb9, 0x3fe2774a0a961612, // -0.8167, 0.57706 + 0xbfea29a7a0462782, 0x3fe26d054cdd12df, // -0.81758, 0.57581 + 0xbfea30e1fa4cbf81, 0x3fe262bdb7b795a2, // -0.81847, 0.57455 + 0xbfea38184a593bc6, 0x3fe258734cbb7110, // -0.81935, 0.5733 + 0xbfea3f4a8f4ee2d2, 0x3fe24e260d7ee7c9, // -0.82023, 0.57204 + 0xbfea4678c8119ac8, 0x3fe243d5fb98ac1f, // -0.8211, 0.57078 + 0xbfea4da2f385e997, 0x3fe23983189fdfd5, // -0.82198, 0.56952 + 0xbfea54c91090f524, 0x3fe22f2d662c13e1, // -0.82285, 0.56826 + 0xbfea5beb1e188375, 0x3fe224d4e5d5482e, // -0.82372, 0.567 + 0xbfea63091b02fae2, 0x3fe21a799933eb58, // -0.82459, 0.56573 + 0xbfea6a230637623b, 0x3fe2101b81e0da78, // -0.82546, 0.56447 + 0xbfea7138de9d60f5, 0x3fe205baa17560d6, // -0.82632, 0.5632 + 0xbfea784aa31d3f55, 0x3fe1fb56f98b37b8, // -0.82718, 0.56193 + 0xbfea7f58529fe69d, 0x3fe1f0f08bbc861b, // -0.82805, 0.56066 + 0xbfea8661ec0ee133, 0x3fe1e68759a3e074, // -0.8289, 0.55939 + 0xbfea8d676e545ad2, 0x3fe1dc1b64dc4872, // -0.82976, 0.55812 + 0xbfea9468d85b20ae, 0x3fe1d1acaf012cc2, // -0.83062, 0.55685 + 0xbfea9b66290ea1a3, 0x3fe1c73b39ae68c8, // -0.83147, 0.55557 + 0xbfeaa25f5f5aee60, 0x3fe1bcc706804467, // -0.83232, 0.55429 + 0xbfeaa9547a2cb98e, 0x3fe1b250171373be, // -0.83317, 0.55302 + 0xbfeab045787157ff, 0x3fe1a7d66d0516e6, // -0.83402, 0.55174 + 0xbfeab7325916c0d4, 0x3fe19d5a09f2b9b8, // -0.83486, 0.55046 + 0xbfeabe1b1b0b8dac, 0x3fe192daef7a5386, // -0.83571, 0.54918 + 0xbfeac4ffbd3efac8, 0x3fe188591f3a46e5, // -0.83655, 0.54789 + 0xbfeacbe03ea0e73b, 0x3fe17dd49ad16161, // -0.83739, 0.54661 + 0xbfead2bc9e21d511, 0x3fe1734d63dedb49, // -0.83822, 0.54532 + 0xbfead994dab2e979, 0x3fe168c37c025764, // -0.83906, 0.54404 + 0xbfeae068f345ecef, 0x3fe15e36e4dbe2bc, // -0.83989, 0.54275 + 0xbfeae738e6cd4b67, 0x3fe153a7a00bf453, // -0.84073, 0.54146 + 0xbfeaee04b43c1474, 0x3fe14915af336ceb, // -0.84155, 0.54017 + 0xbfeaf4cc5a85fb73, 0x3fe13e8113f396c1, // -0.84238, 0.53888 + 0xbfeafb8fd89f57b6, 0x3fe133e9cfee254e, // -0.84321, 0.53759 + 0xbfeb024f2d7d24a9, 0x3fe1294fe4c5350a, // -0.84403, 0.53629 + 0xbfeb090a58150200, 0x3fe11eb3541b4b22, // -0.84485, 0.535 + 0xbfeb0fc1575d33db, 0x3fe114141f935545, // -0.84567, 0.5337 + 0xbfeb16742a4ca2f5, 0x3fe1097248d0a956, // -0.84649, 0.5324 + 0xbfeb1d22cfdadcc6, 0x3fe0fecdd1770537, // -0.84731, 0.5311 + 0xbfeb23cd470013b4, 0x3fe0f426bb2a8e7d, // -0.84812, 0.5298 + 0xbfeb2a738eb51f33, 0x3fe0e97d078fd23b, // -0.84893, 0.5285 + 0xbfeb3115a5f37bf4, 0x3fe0ded0b84bc4b5, // -0.84974, 0.5272 + 0xbfeb37b38bb54c09, 0x3fe0d421cf03c12b, // -0.85055, 0.5259 + 0xbfeb3e4d3ef55712, 0x3fe0c9704d5d898f, // -0.85136, 0.52459 + 0xbfeb44e2beaf0a61, 0x3fe0bebc34ff4646, // -0.85216, 0.52328 + 0xbfeb4b7409de7925, 0x3fe0b405878f85ec, // -0.85296, 0.52198 + 0xbfeb52011f805c92, 0x3fe0a94c46b53d0b, // -0.85376, 0.52067 + 0xbfeb5889fe921405, 0x3fe09e907417c5e1, // -0.85456, 0.51936 + 0xbfeb5f0ea611a532, 0x3fe093d2115ee018, // -0.85535, 0.51804 + 0xbfeb658f14fdbc47, 0x3fe089112032b08c, // -0.85615, 0.51673 + 0xbfeb6c0b4a55ac17, 0x3fe07e4da23bc102, // -0.85694, 0.51542 + 0xbfeb728345196e3e, 0x3fe073879922ffed, // -0.85773, 0.5141 + 0xbfeb78f70449a34b, 0x3fe068bf0691c028, // -0.85852, 0.51279 + 0xbfeb7f6686e792ea, 0x3fe05df3ec31b8b6, // -0.8593, 0.51147 + 0xbfeb85d1cbf52c02, 0x3fe053264bad0483, // -0.86009, 0.51015 + 0xbfeb8c38d27504e9, 0x3fe0485626ae221a, // -0.86087, 0.50883 + 0xbfeb929b996a5b7f, 0x3fe03d837edff370, // -0.86165, 0.50751 + 0xbfeb98fa1fd9155e, 0x3fe032ae55edbd95, // -0.86242, 0.50619 + 0xbfeb9f5464c5bffc, 0x3fe027d6ad83287e, // -0.8632, 0.50486 + 0xbfeba5aa673590d2, 0x3fe01cfc874c3eb7, // -0.86397, 0.50354 + 0xbfebabfc262e6586, 0x3fe0121fe4f56d2c, // -0.86474, 0.50221 + 0xbfebb249a0b6c40d, 0x3fe00740c82b82e0, // -0.86551, 0.50089 + 0xbfebb892d5d5dad5, 0x3fdff8be6537615e, // -0.86628, 0.49956 + 0xbfebbed7c49380ea, 0x3fdfe2f64be7120f, // -0.86705, 0.49823 + 0xbfebc5186bf8361d, 0x3fdfcd2947c1ff57, // -0.86781, 0.4969 + 0xbfebcb54cb0d2327, 0x3fdfb7575c24d2de, // -0.86857, 0.49557 + 0xbfebd18ce0dc19d6, 0x3fdfa1808c6cf7e0, // -0.86933, 0.49423 + 0xbfebd7c0ac6f952a, 0x3fdf8ba4dbf89aba, // -0.87009, 0.4929 + 0xbfebddf02cd2b983, 0x3fdf75c44e26a852, // -0.87084, 0.49156 + 0xbfebe41b611154c1, 0x3fdf5fdee656cda3, // -0.8716, 0.49023 + 0xbfebea424837de6d, 0x3fdf49f4a7e97729, // -0.87235, 0.48889 + 0xbfebf064e15377dd, 0x3fdf3405963fd068, // -0.87309, 0.48755 + 0xbfebf6832b71ec5b, 0x3fdf1e11b4bbc35c, // -0.87384, 0.48621 + 0xbfebfc9d25a1b147, 0x3fdf081906bff7fd, // -0.87459, 0.48487 + 0xbfec02b2cef1e641, 0x3fdef21b8fafd3b5, // -0.87533, 0.48353 + 0xbfec08c426725549, 0x3fdedc1952ef78d5, // -0.87607, 0.48218 + 0xbfec0ed12b3372e9, 0x3fdec61253e3c61b, // -0.87681, 0.48084 + 0xbfec14d9dc465e58, 0x3fdeb00695f25620, // -0.87755, 0.47949 + 0xbfec1ade38bce19b, 0x3fde99f61c817eda, // -0.87828, 0.47815 + 0xbfec20de3fa971b0, 0x3fde83e0eaf85113, // -0.87901, 0.4768 + 0xbfec26d9f01f2eaf, 0x3fde6dc704be97e2, // -0.87974, 0.47545 + 0xbfec2cd14931e3f1, 0x3fde57a86d3cd824, // -0.88047, 0.4741 + 0xbfec32c449f60831, 0x3fde418527dc4ffa, // -0.8812, 0.47275 + 0xbfec38b2f180bdb1, 0x3fde2b5d3806f63b, // -0.88192, 0.4714 + 0xbfec3e9d3ee7d262, 0x3fde1530a12779f4, // -0.88264, 0.47004 + 0xbfec44833141c004, 0x3fddfeff66a941de, // -0.88336, 0.46869 + 0xbfec4a64c7a5ac4c, 0x3fdde8c98bf86bd6, // -0.88408, 0.46733 + 0xbfec5042012b6907, 0x3fddd28f1481cc58, // -0.8848, 0.46598 + 0xbfec561adceb743e, 0x3fddbc5003b2edf8, // -0.88551, 0.46462 + 0xbfec5bef59fef85a, 0x3fdda60c5cfa10d8, // -0.88622, 0.46326 + 0xbfec61bf777fcc48, 0x3fdd8fc423c62a25, // -0.88693, 0.4619 + 0xbfec678b3488739b, 0x3fdd79775b86e389, // -0.88764, 0.46054 + 0xbfec6d5290341eb2, 0x3fdd632607ac9aa9, // -0.88835, 0.45918 + 0xbfec7315899eaad7, 0x3fdd4cd02ba8609c, // -0.88905, 0.45781 + 0xbfec78d41fe4a267, 0x3fdd3675caebf962, // -0.88975, 0.45645 + 0xbfec7e8e52233cf3, 0x3fdd2016e8e9db5b, // -0.89045, 0.45508 + 0xbfec84441f785f61, 0x3fdd09b389152ec1, // -0.89115, 0.45372 + 0xbfec89f587029c13, 0x3fdcf34baee1cd21, // -0.89184, 0.45235 + 0xbfec8fa287e13305, 0x3fdcdcdf5dc440ce, // -0.89253, 0.45098 + 0xbfec954b213411f5, 0x3fdcc66e9931c45d, // -0.89322, 0.44961 + 0xbfec9aef521bd480, 0x3fdcaff964a0421d, // -0.89391, 0.44824 + 0xbfeca08f19b9c449, 0x3fdc997fc3865388, // -0.8946, 0.44687 + 0xbfeca62a772fd919, 0x3fdc8301b95b40c2, // -0.89528, 0.4455 + 0xbfecabc169a0b901, 0x3fdc6c7f4997000a, // -0.89597, 0.44412 + 0xbfecb153f02fb87d, 0x3fdc55f877b23537, // -0.89665, 0.44275 + 0xbfecb6e20a00da99, 0x3fdc3f6d47263129, // -0.89732, 0.44137 + 0xbfecbc6bb638d10b, 0x3fdc28ddbb6cf145, // -0.898, 0.43999 + 0xbfecc1f0f3fcfc5c, 0x3fdc1249d8011ee7, // -0.89867, 0.43862 + 0xbfecc771c2736c09, 0x3fdbfbb1a05e0edc, // -0.89935, 0.43724 + 0xbfecccee20c2de9f, 0x3fdbe51517ffc0d9, // -0.90002, 0.43586 + 0xbfecd2660e12c1e6, 0x3fdbce744262deee, // -0.90068, 0.43448 + 0xbfecd7d9898b32f6, 0x3fdbb7cf2304bd01, // -0.90135, 0.43309 + 0xbfecdd489254fe65, 0x3fdba125bd63583e, // -0.90201, 0.43171 + 0xbfece2b32799a060, 0x3fdb8a7814fd5693, // -0.90267, 0.43033 + 0xbfece819488344ce, 0x3fdb73c62d520624, // -0.90333, 0.42894 + 0xbfeced7af43cc773, 0x3fdb5d1009e15cc0, // -0.90399, 0.42756 + 0xbfecf2d829f1b40e, 0x3fdb4655ae2bf757, // -0.90464, 0.42617 + 0xbfecf830e8ce467b, 0x3fdb2f971db31972, // -0.9053, 0.42478 + 0xbfecfd852fff6ad4, 0x3fdb18d45bf8aca6, // -0.90595, 0.42339 + 0xbfed02d4feb2bd92, 0x3fdb020d6c7f4009, // -0.9066, 0.422 + 0xbfed082054168bac, 0x3fdaeb4252ca07ab, // -0.90724, 0.42061 + 0xbfed0d672f59d2b9, 0x3fdad473125cdc08, // -0.90789, 0.41922 + 0xbfed12a98fac410c, 0x3fdabd9faebc3980, // -0.90853, 0.41782 + 0xbfed17e7743e35dc, 0x3fdaa6c82b6d3fc9, // -0.90917, 0.41643 + 0xbfed1d20dc40c15c, 0x3fda8fec8bf5b166, // -0.90981, 0.41503 + 0xbfed2255c6e5a4e1, 0x3fda790cd3dbf31a, // -0.91044, 0.41364 + 0xbfed2786335f52fc, 0x3fda622906a70b63, // -0.91107, 0.41224 + 0xbfed2cb220e0ef9f, 0x3fda4b4127dea1e4, // -0.91171, 0.41084 + 0xbfed31d98e9e503a, 0x3fda34553b0afee5, // -0.91234, 0.40944 + 0xbfed36fc7bcbfbdc, 0x3fda1d6543b50ac0, // -0.91296, 0.40804 + 0xbfed3c1ae79f2b4e, 0x3fda067145664d57, // -0.91359, 0.40664 + 0xbfed4134d14dc93a, 0x3fd9ef7943a8ed8a, // -0.91421, 0.40524 + 0xbfed464a380e7242, 0x3fd9d87d4207b0ab, // -0.91483, 0.40384 + 0xbfed4b5b1b187524, 0x3fd9c17d440df9f2, // -0.91545, 0.40243 + 0xbfed506779a3d2d9, 0x3fd9aa794d47c9ee, // -0.91606, 0.40103 + 0xbfed556f52e93eb1, 0x3fd993716141bdfe, // -0.91668, 0.39962 + 0xbfed5a72a6221e73, 0x3fd97c6583890fc2, // -0.91729, 0.39822 + 0xbfed5f7172888a7f, 0x3fd96555b7ab948f, // -0.9179, 0.39681 + 0xbfed646bb7574de5, 0x3fd94e420137bce3, // -0.91851, 0.3954 + 0xbfed696173c9e68b, 0x3fd9372a63bc93d7, // -0.91911, 0.39399 + 0xbfed6e52a71c8547, 0x3fd9200ee2c9be97, // -0.91972, 0.39258 + 0xbfed733f508c0dff, 0x3fd908ef81ef7bd1, // -0.92032, 0.39117 + 0xbfed78276f5617c6, 0x3fd8f1cc44bea329, // -0.92092, 0.38976 + 0xbfed7d0b02b8ecf9, 0x3fd8daa52ec8a4af, // -0.92151, 0.38835 + 0xbfed81ea09f38b63, 0x3fd8c37a439f884f, // -0.92211, 0.38693 + 0xbfed86c48445a450, 0x3fd8ac4b86d5ed44, // -0.9227, 0.38552 + 0xbfed8b9a70ef9cb4, 0x3fd89518fbff098e, // -0.92329, 0.3841 + 0xbfed906bcf328d46, 0x3fd87de2a6aea963, // -0.92388, 0.38268 + 0xbfed95389e50429b, 0x3fd866a88a792ea0, // -0.92447, 0.38127 + 0xbfed9a00dd8b3d46, 0x3fd84f6aaaf3903f, // -0.92505, 0.37985 + 0xbfed9ec48c26b1f3, 0x3fd838290bb359c8, // -0.92563, 0.37843 + 0xbfeda383a9668988, 0x3fd820e3b04eaac4, // -0.92621, 0.37701 + 0xbfeda83e348f613b, 0x3fd8099a9c5c362d, // -0.92679, 0.37559 + 0xbfedacf42ce68ab9, 0x3fd7f24dd37341e3, // -0.92736, 0.37416 + 0xbfedb1a591b20c38, 0x3fd7dafd592ba621, // -0.92794, 0.37274 + 0xbfedb6526238a09b, 0x3fd7c3a9311dcce7, // -0.92851, 0.37132 + 0xbfedbafa9dc1b78d, 0x3fd7ac515ee2b172, // -0.92907, 0.36989 + 0xbfedbf9e4395759a, 0x3fd794f5e613dfae, // -0.92964, 0.36847 + 0xbfedc43d52fcb453, 0x3fd77d96ca4b73a6, // -0.93021, 0.36704 + 0xbfedc8d7cb410260, 0x3fd766340f2418f6, // -0.93077, 0.36561 + 0xbfedcd6dabaca3a5, 0x3fd74ecdb8390a3e, // -0.93133, 0.36418 + 0xbfedd1fef38a915a, 0x3fd73763c9261092, // -0.93188, 0.36276 + 0xbfedd68ba2267a25, 0x3fd71ff6458782ec, // -0.93244, 0.36133 + 0xbfeddb13b6ccc23d, 0x3fd7088530fa459e, // -0.93299, 0.3599 + 0xbfeddf9730ca837b, 0x3fd6f1108f1bc9c5, // -0.93354, 0.35846 + 0xbfede4160f6d8d81, 0x3fd6d998638a0cb5, // -0.93409, 0.35703 + 0xbfede890520465ce, 0x3fd6c21cb1e39771, // -0.93464, 0.3556 + 0xbfeded05f7de47da, 0x3fd6aa9d7dc77e16, // -0.93518, 0.35416 + 0xbfedf177004b2534, 0x3fd6931acad55f51, // -0.93573, 0.35273 + 0xbfedf5e36a9ba59c, 0x3fd67b949cad63ca, // -0.93627, 0.35129 + 0xbfedfa4b3621271d, 0x3fd6640af6f03d9e, // -0.9368, 0.34986 + 0xbfedfeae622dbe2b, 0x3fd64c7ddd3f27c6, // -0.93734, 0.34842 + 0xbfee030cee1435b8, 0x3fd634ed533be58e, // -0.93787, 0.34698 + 0xbfee0766d9280f54, 0x3fd61d595c88c203, // -0.9384, 0.34554 + 0xbfee0bbc22bd8349, 0x3fd605c1fcc88f63, // -0.93893, 0.3441 + 0xbfee100cca2980ac, 0x3fd5ee27379ea693, // -0.93946, 0.34266 + 0xbfee1458cec1ad83, 0x3fd5d68910aee686, // -0.93998, 0.34122 + 0xbfee18a02fdc66d9, 0x3fd5bee78b9db3b6, // -0.94051, 0.33978 + 0xbfee1ce2ecd0c0d8, 0x3fd5a742ac0ff78d, // -0.94103, 0.33833 + 0xbfee212104f686e5, 0x3fd58f9a75ab1fdd, // -0.94154, 0.33689 + 0xbfee255a77a63bb8, 0x3fd577eeec151e47, // -0.94206, 0.33545 + 0xbfee298f4439197a, 0x3fd5604012f467b4, // -0.94257, 0.334 + 0xbfee2dbf6a0911d9, 0x3fd5488dedeff3be, // -0.94308, 0.33255 + 0xbfee31eae870ce25, 0x3fd530d880af3c24, // -0.94359, 0.33111 + 0xbfee3611becbaf69, 0x3fd5191fceda3c35, // -0.9441, 0.32966 + 0xbfee3a33ec75ce85, 0x3fd50163dc197047, // -0.9446, 0.32821 + 0xbfee3e5170cbfc46, 0x3fd4e9a4ac15d520, // -0.94511, 0.32676 + 0xbfee426a4b2bc17e, 0x3fd4d1e24278e76a, // -0.94561, 0.32531 + 0xbfee467e7af35f23, 0x3fd4ba1ca2eca31c, // -0.94611, 0.32386 + 0xbfee4a8dff81ce5e, 0x3fd4a253d11b82f3, // -0.9466, 0.32241 + 0xbfee4e98d836c0af, 0x3fd48a87d0b07fd7, // -0.94709, 0.32096 + 0xbfee529f04729ffc, 0x3fd472b8a5571054, // -0.94759, 0.3195 + 0xbfee56a083968eb1, 0x3fd45ae652bb2800, // -0.94807, 0.31805 + 0xbfee5a9d550467d3, 0x3fd44310dc8936f0, // -0.94856, 0.31659 + 0xbfee5e95781ebf1c, 0x3fd42b38466e2928, // -0.94905, 0.31514 + 0xbfee6288ec48e112, 0x3fd4135c94176602, // -0.94953, 0.31368 + 0xbfee6677b0e6d31e, 0x3fd3fb7dc932cfa4, // -0.95001, 0.31222 + 0xbfee6a61c55d53a7, 0x3fd3e39be96ec271, // -0.95049, 0.31077 + 0xbfee6e472911da27, 0x3fd3cbb6f87a146e, // -0.95096, 0.30931 + 0xbfee7227db6a9744, 0x3fd3b3cefa0414b7, // -0.95144, 0.30785 + 0xbfee7603dbce74e9, 0x3fd39be3f1bc8aef, // -0.95191, 0.30639 + 0xbfee79db29a5165a, 0x3fd383f5e353b6aa, // -0.95238, 0.30493 + 0xbfee7dadc456d850, 0x3fd36c04d27a4edf, // -0.95284, 0.30347 + 0xbfee817bab4cd10d, 0x3fd35410c2e18152, // -0.95331, 0.30201 + 0xbfee8544ddf0d075, 0x3fd33c19b83af207, // -0.95377, 0.30054 + 0xbfee89095bad6025, 0x3fd3241fb638baaf, // -0.95423, 0.29908 + 0xbfee8cc923edc388, 0x3fd30c22c08d6a13, // -0.95469, 0.29762 + 0xbfee9084361df7f3, 0x3fd2f422daec0386, // -0.95514, 0.29615 + 0xbfee943a91aab4b4, 0x3fd2dc200907fe51, // -0.95559, 0.29469 + 0xbfee97ec36016b30, 0x3fd2c41a4e954520, // -0.95605, 0.29322 + 0xbfee9b99229046f8, 0x3fd2ac11af483572, // -0.95649, 0.29175 + 0xbfee9f4156c62dda, 0x3fd294062ed59f05, // -0.95694, 0.29028 + 0xbfeea2e4d212c000, 0x3fd27bf7d0f2c346, // -0.95738, 0.28882 + 0xbfeea68393e65800, 0x3fd263e6995554ba, // -0.95783, 0.28735 + 0xbfeeaa1d9bb20af3, 0x3fd24bd28bb37672, // -0.95827, 0.28588 + 0xbfeeadb2e8e7a88e, 0x3fd233bbabc3bb72, // -0.9587, 0.28441 + 0xbfeeb1437af9bb34, 0x3fd21ba1fd3d2623, // -0.95914, 0.28294 + 0xbfeeb4cf515b8811, 0x3fd2038583d727bd, // -0.95957, 0.28146 + 0xbfeeb8566b810f2a, 0x3fd1eb6643499fbb, // -0.96, 0.27999 + 0xbfeebbd8c8df0b74, 0x3fd1d3443f4cdb3d, // -0.96043, 0.27852 + 0xbfeebf5668eaf2ef, 0x3fd1bb1f7b999480, // -0.96086, 0.27705 + 0xbfeec2cf4b1af6b2, 0x3fd1a2f7fbe8f243, // -0.96128, 0.27557 + 0xbfeec6436ee60309, 0x3fd18acdc3f4873a, // -0.9617, 0.2741 + 0xbfeec9b2d3c3bf84, 0x3fd172a0d7765177, // -0.96212, 0.27262 + 0xbfeecd1d792c8f10, 0x3fd15a713a28b9d9, // -0.96254, 0.27115 + 0xbfeed0835e999009, 0x3fd1423eefc69378, // -0.96295, 0.26967 + 0xbfeed3e483849c51, 0x3fd12a09fc0b1b12, // -0.96337, 0.26819 + 0xbfeed740e7684963, 0x3fd111d262b1f677, // -0.96378, 0.26671 + 0xbfeeda9889bfe86a, 0x3fd0f998277733f7, // -0.96418, 0.26523 + 0xbfeeddeb6a078651, 0x3fd0e15b4e1749cd, // -0.96459, 0.26375 + 0xbfeee13987bbebdc, 0x3fd0c91bda4f158d, // -0.96499, 0.26227 + 0xbfeee482e25a9dbc, 0x3fd0b0d9cfdbdb90, // -0.96539, 0.26079 + 0xbfeee7c77961dc9e, 0x3fd09895327b465e, // -0.96579, 0.25931 + 0xbfeeeb074c50a544, 0x3fd0804e05eb661e, // -0.96619, 0.25783 + 0xbfeeee425aa6b09a, 0x3fd068044deab002, // -0.96658, 0.25635 + 0xbfeef178a3e473c2, 0x3fd04fb80e37fdae, // -0.96698, 0.25487 + 0xbfeef4aa278b2032, 0x3fd037694a928cac, // -0.96737, 0.25338 + 0xbfeef7d6e51ca3c0, 0x3fd01f1806b9fdd2, // -0.96775, 0.2519 + 0xbfeefafedc1ba8b7, 0x3fd006c4466e54af, // -0.96814, 0.25041 + 0xbfeefe220c0b95ec, 0x3fcfdcdc1adfedf8, // -0.96852, 0.24893 + 0xbfef014074708ed3, 0x3fcfac2abeff57ff, // -0.9689, 0.24744 + 0xbfef045a14cf738c, 0x3fcf7b7480bd3801, // -0.96928, 0.24596 + 0xbfef076eecade0fa, 0x3fcf4ab9679c9f5c, // -0.96966, 0.24447 + 0xbfef0a7efb9230d7, 0x3fcf19f97b215f1a, // -0.97003, 0.24298 + 0xbfef0d8a410379c5, 0x3fcee934c2d006c7, // -0.9704, 0.24149 + 0xbfef1090bc898f5f, 0x3fceb86b462de348, // -0.97077, 0.24 + 0xbfef13926dad024e, 0x3fce879d0cc0fdaf, // -0.97114, 0.23851 + 0xbfef168f53f7205d, 0x3fce56ca1e101a1b, // -0.9715, 0.23702 + 0xbfef19876ef1f486, 0x3fce25f281a2b684, // -0.97187, 0.23553 + 0xbfef1c7abe284708, 0x3fcdf5163f01099a, // -0.97223, 0.23404 + 0xbfef1f6941259d7a, 0x3fcdc4355db40195, // -0.97258, 0.23255 + 0xbfef2252f7763ada, 0x3fcd934fe5454311, // -0.97294, 0.23106 + 0xbfef2537e0a71f9f, 0x3fcd6265dd3f27e3, // -0.97329, 0.22957 + 0xbfef2817fc4609ce, 0x3fcd31774d2cbdee, // -0.97364, 0.22807 + 0xbfef2af349e17507, 0x3fcd00843c99c5f9, // -0.97399, 0.22658 + 0xbfef2dc9c9089a9d, 0x3fcccf8cb312b286, // -0.97434, 0.22508 + 0xbfef309b794b719f, 0x3fcc9e90b824a6a9, // -0.97468, 0.22359 + 0xbfef33685a3aaef0, 0x3fcc6d90535d74dc, // -0.97503, 0.22209 + 0xbfef36306b67c556, 0x3fcc3c8b8c4b9dd7, // -0.97536, 0.2206 + 0xbfef38f3ac64e589, 0x3fcc0b826a7e4f63, // -0.9757, 0.2191 + 0xbfef3bb21cc4fe47, 0x3fcbda74f5856330, // -0.97604, 0.2176 + 0xbfef3e6bbc1bbc65, 0x3fcba96334f15dad, // -0.97637, 0.21611 + 0xbfef412089fd8adc, 0x3fcb784d30536cda, // -0.9767, 0.21461 + 0xbfef43d085ff92dd, 0x3fcb4732ef3d6722, // -0.97703, 0.21311 + 0xbfef467bafb7bbe0, 0x3fcb16147941ca2a, // -0.97735, 0.21161 + 0xbfef492206bcabb4, 0x3fcae4f1d5f3b9ab, // -0.97768, 0.21011 + 0xbfef4bc38aa5c694, 0x3fcab3cb0ce6fe44, // -0.978, 0.20861 + 0xbfef4e603b0b2f2d, 0x3fca82a025b00451, // -0.97832, 0.20711 + 0xbfef50f81785c6b9, 0x3fca517127e3dabc, // -0.97863, 0.20561 + 0xbfef538b1faf2d07, 0x3fca203e1b1831da, // -0.97895, 0.20411 + 0xbfef56195321c090, 0x3fc9ef0706e35a35, // -0.97926, 0.20261 + 0xbfef58a2b1789e84, 0x3fc9bdcbf2dc4366, // -0.97957, 0.2011 + 0xbfef5b273a4fa2d9, 0x3fc98c8ce69a7aec, // -0.97988, 0.1996 + 0xbfef5da6ed43685d, 0x3fc95b49e9b62af9, // -0.98018, 0.1981 + 0xbfef6021c9f148c2, 0x3fc92a0303c8194f, // -0.98048, 0.19659 + 0xbfef6297cff75cb0, 0x3fc8f8b83c69a60a, // -0.98079, 0.19509 + 0xbfef6508fef47bd5, 0x3fc8c7699b34ca7e, // -0.98108, 0.19359 + 0xbfef677556883cee, 0x3fc8961727c41804, // -0.98138, 0.19208 + 0xbfef69dcd652f5de, 0x3fc864c0e9b2b6cf, // -0.98167, 0.19057 + 0xbfef6c3f7df5bbb7, 0x3fc83366e89c64c5, // -0.98196, 0.18907 + 0xbfef6e9d4d1262ca, 0x3fc802092c1d744b, // -0.98225, 0.18756 + 0xbfef70f6434b7eb7, 0x3fc7d0a7bbd2cb1b, // -0.98254, 0.18606 + 0xbfef734a60446279, 0x3fc79f429f59e11d, // -0.98282, 0.18455 + 0xbfef7599a3a12077, 0x3fc76dd9de50bf31, // -0.98311, 0.18304 + 0xbfef77e40d068a90, 0x3fc73c6d8055fe0a, // -0.98339, 0.18153 + 0xbfef7a299c1a322a, 0x3fc70afd8d08c4ff, // -0.98366, 0.18002 + 0xbfef7c6a50826840, 0x3fc6d98a0c08c8da, // -0.98394, 0.17851 + 0xbfef7ea629e63d6e, 0x3fc6a81304f64ab2, // -0.98421, 0.177 + 0xbfef80dd27ed8204, 0x3fc676987f7216b8, // -0.98448, 0.17549 + 0xbfef830f4a40c60c, 0x3fc6451a831d830d, // -0.98475, 0.17398 + 0xbfef853c9089595e, 0x3fc61399179a6e94, // -0.98501, 0.17247 + 0xbfef8764fa714ba9, 0x3fc5e214448b3fc6, // -0.98528, 0.17096 + 0xbfef898887a36c84, 0x3fc5b08c1192e381, // -0.98554, 0.16945 + 0xbfef8ba737cb4b78, 0x3fc57f008654cbde, // -0.9858, 0.16794 + 0xbfef8dc10a95380d, 0x3fc54d71aa74ef02, // -0.98605, 0.16643 + 0xbfef8fd5ffae41db, 0x3fc51bdf8597c5f2, // -0.98631, 0.16491 + 0xbfef91e616c43891, 0x3fc4ea4a1f624b61, // -0.98656, 0.1634 + 0xbfef93f14f85ac08, 0x3fc4b8b17f79fa88, // -0.98681, 0.16189 + 0xbfef95f7a9a1ec47, 0x3fc48715ad84cdf5, // -0.98706, 0.16037 + 0xbfef97f924c9099b, 0x3fc45576b1293e5a, // -0.9873, 0.15886 + 0xbfef99f5c0abd496, 0x3fc423d4920e4166, // -0.98754, 0.15734 + 0xbfef9bed7cfbde29, 0x3fc3f22f57db4893, // -0.98778, 0.15583 + 0xbfef9de0596b77a3, 0x3fc3c0870a383ff6, // -0.98802, 0.15431 + 0xbfef9fce55adb2c8, 0x3fc38edbb0cd8d14, // -0.98826, 0.1528 + 0xbfefa1b7717661d5, 0x3fc35d2d53440db2, // -0.98849, 0.15128 + 0xbfefa39bac7a1791, 0x3fc32b7bf94516a7, // -0.98872, 0.14976 + 0xbfefa57b066e2754, 0x3fc2f9c7aa7a72af, // -0.98895, 0.14825 + 0xbfefa7557f08a517, 0x3fc2c8106e8e613a, // -0.98918, 0.14673 + 0xbfefa92b1600657c, 0x3fc296564d2b953e, // -0.9894, 0.14521 + 0xbfefaafbcb0cfddc, 0x3fc264994dfd340a, // -0.98962, 0.1437 + 0xbfefacc79de6c44f, 0x3fc232d978aed413, // -0.98984, 0.14218 + 0xbfefae8e8e46cfbb, 0x3fc20116d4ec7bce, // -0.99006, 0.14066 + 0xbfefb0509be6f7db, 0x3fc1cf516a62a077, // -0.99027, 0.13914 + 0xbfefb20dc681d54d, 0x3fc19d8940be24e7, // -0.99049, 0.13762 + 0xbfefb3c60dd2c199, 0x3fc16bbe5fac5865, // -0.9907, 0.1361 + 0xbfefb5797195d741, 0x3fc139f0cedaf576, // -0.9909, 0.13458 + 0xbfefb727f187f1c7, 0x3fc1082095f820b0, // -0.99111, 0.13306 + 0xbfefb8d18d66adb7, 0x3fc0d64dbcb26786, // -0.99131, 0.13154 + 0xbfefba7644f068b5, 0x3fc0a4784ab8bf1d, // -0.99151, 0.13002 + 0xbfefbc1617e44186, 0x3fc072a047ba831d, // -0.99171, 0.1285 + 0xbfefbdb106021816, 0x3fc040c5bb67747e, // -0.99191, 0.12698 + 0xbfefbf470f0a8d88, 0x3fc00ee8ad6fb85b, // -0.9921, 0.12545 + 0xbfefc0d832bf043a, 0x3fbfba124b07ad85, // -0.99229, 0.12393 + 0xbfefc26470e19fd3, 0x3fbf564e56a9730e, // -0.99248, 0.12241 + 0xbfefc3ebc935454c, 0x3fbef2858d27561b, // -0.99267, 0.12089 + 0xbfefc56e3b7d9af6, 0x3fbe8eb7fde4aa3e, // -0.99285, 0.11937 + 0xbfefc6ebc77f0887, 0x3fbe2ae5b8457f77, // -0.99303, 0.11784 + 0xbfefc8646cfeb721, 0x3fbdc70ecbae9fc8, // -0.99321, 0.11632 + 0xbfefc9d82bc2915e, 0x3fbd633347858ce4, // -0.99339, 0.11479 + 0xbfefcb4703914354, 0x3fbcff533b307dc1, // -0.99356, 0.11327 + 0xbfefccb0f4323aa3, 0x3fbc9b6eb6165c42, // -0.99374, 0.11175 + 0xbfefce15fd6da67b, 0x3fbc3785c79ec2d5, // -0.99391, 0.11022 + 0xbfefcf761f0c77a3, 0x3fbbd3987f31fa0e, // -0.99407, 0.1087 + 0xbfefd0d158d86087, 0x3fbb6fa6ec38f64c, // -0.99424, 0.10717 + 0xbfefd227aa9bd53b, 0x3fbb0bb11e1d5559, // -0.9944, 0.10565 + 0xbfefd37914220b84, 0x3fbaa7b724495c04, // -0.99456, 0.10412 + 0xbfefd4c59536fae4, 0x3fba43b90e27f3c4, // -0.99472, 0.1026 + 0xbfefd60d2da75c9e, 0x3fb9dfb6eb24a85c, // -0.99488, 0.10107 + 0xbfefd74fdd40abbf, 0x3fb97bb0caaba56f, // -0.99503, 0.099544 + 0xbfefd88da3d12526, 0x3fb917a6bc29b42c, // -0.99518, 0.098017 + 0xbfefd9c68127c78c, 0x3fb8b398cf0c38e0, // -0.99533, 0.09649 + 0xbfefdafa7514538c, 0x3fb84f8712c130a0, // -0.99548, 0.094963 + 0xbfefdc297f674ba9, 0x3fb7eb7196b72ee4, // -0.99563, 0.093436 + 0xbfefdd539ff1f456, 0x3fb787586a5d5b21, // -0.99577, 0.091909 + 0xbfefde78d68653fd, 0x3fb7233b9d236e71, // -0.99591, 0.090381 + 0xbfefdf9922f73307, 0x3fb6bf1b3e79b129, // -0.99604, 0.088854 + 0xbfefe0b485181be3, 0x3fb65af75dd0f87b, // -0.99618, 0.087326 + 0xbfefe1cafcbd5b09, 0x3fb5f6d00a9aa419, // -0.99631, 0.085797 + 0xbfefe2dc89bbff08, 0x3fb592a554489bc8, // -0.99644, 0.084269 + 0xbfefe3e92be9d886, 0x3fb52e774a4d4d0a, // -0.99657, 0.08274 + 0xbfefe4f0e31d7a4a, 0x3fb4ca45fc1ba8b6, // -0.9967, 0.081211 + 0xbfefe5f3af2e3940, 0x3fb4661179272096, // -0.99682, 0.079682 + 0xbfefe6f18ff42c84, 0x3fb401d9d0e3a507, // -0.99694, 0.078153 + 0xbfefe7ea85482d60, 0x3fb39d9f12c5a299, // -0.99706, 0.076624 + 0xbfefe8de8f03d75c, 0x3fb339614e41ffa5, // -0.99718, 0.075094 + 0xbfefe9cdad01883a, 0x3fb2d52092ce19f6, // -0.99729, 0.073565 + 0xbfefeab7df1c6005, 0x3fb270dcefdfc45b, // -0.9974, 0.072035 + 0xbfefeb9d2530410f, 0x3fb20c9674ed444c, // -0.99751, 0.070505 + 0xbfefec7d7f19cffc, 0x3fb1a84d316d4f8a, // -0.99762, 0.068974 + 0xbfefed58ecb673c4, 0x3fb1440134d709b2, // -0.99772, 0.067444 + 0xbfefee2f6de455ba, 0x3fb0dfb28ea201e6, // -0.99783, 0.065913 + 0xbfefef0102826191, 0x3fb07b614e463064, // -0.99793, 0.064383 + 0xbfefefcdaa704562, 0x3fb0170d833bf421, // -0.99802, 0.062852 + 0xbfeff095658e71ad, 0x3faf656e79f820e0, // -0.99812, 0.061321 + 0xbfeff15833be1965, 0x3fae9cbd15ff5527, // -0.99821, 0.05979 + 0xbfeff21614e131ed, 0x3fadd406f9808ec8, // -0.9983, 0.058258 + 0xbfeff2cf08da7321, 0x3fad0b4c436f91d0, // -0.99839, 0.056727 + 0xbfeff3830f8d575c, 0x3fac428d12c0d7e3, // -0.99848, 0.055195 + 0xbfeff43228de1b77, 0x3fab79c986698b78, // -0.99856, 0.053664 + 0xbfeff4dc54b1bed3, 0x3faab101bd5f8317, // -0.99864, 0.052132 + 0xbfeff58192ee0358, 0x3fa9e835d6993c87, // -0.99872, 0.0506 + 0xbfeff621e3796d7e, 0x3fa91f65f10dd814, // -0.9988, 0.049068 + 0xbfeff6bd463b444d, 0x3fa856922bb513c1, // -0.99887, 0.047535 + 0xbfeff753bb1b9164, 0x3fa78dbaa5874685, // -0.99894, 0.046003 + 0xbfeff7e5420320f9, 0x3fa6c4df7d7d5b84, // -0.99901, 0.044471 + 0xbfeff871dadb81df, 0x3fa5fc00d290cd43, // -0.99908, 0.042938 + 0xbfeff8f9858f058b, 0x3fa5331ec3bba0eb, // -0.99914, 0.041406 + 0xbfeff97c4208c014, 0x3fa46a396ff86179, // -0.9992, 0.039873 + 0xbfeff9fa10348837, 0x3fa3a150f6421afc, // -0.99926, 0.03834 + 0xbfeffa72effef75d, 0x3fa2d865759455cd, // -0.99932, 0.036807 + 0xbfeffae6e1556998, 0x3fa20f770ceb11c6, // -0.99938, 0.035274 + 0xbfeffb55e425fdae, 0x3fa14685db42c17e, // -0.99943, 0.033741 + 0xbfeffbbff85f9515, 0x3fa07d91ff984580, // -0.99948, 0.032208 + 0xbfeffc251df1d3f8, 0x3f9f693731d1cf01, // -0.99953, 0.030675 + 0xbfeffc8554cd213a, 0x3f9dd7458c64ab39, // -0.99958, 0.029142 + 0xbfeffce09ce2a679, 0x3f9c454f4ce53b1c, // -0.99962, 0.027608 + 0xbfeffd36f624500c, 0x3f9ab354b1504fca, // -0.99966, 0.026075 + 0xbfeffd886084cd0d, 0x3f992155f7a3667e, // -0.9997, 0.024541 + 0xbfeffdd4dbf78f52, 0x3f978f535ddc9f03, // -0.99974, 0.023008 + 0xbfeffe1c6870cb77, 0x3f95fd4d21fab226, // -0.99977, 0.021474 + 0xbfeffe5f05e578db, 0x3f946b4381fce81c, // -0.9998, 0.01994 + 0xbfeffe9cb44b51a1, 0x3f92d936bbe30efd, // -0.99983, 0.018407 + 0xbfeffed57398d2b7, 0x3f9147270dad7132, // -0.99986, 0.016873 + 0xbfefff0943c53bd1, 0x3f8f6a296ab997ca, // -0.99988, 0.015339 + 0xbfefff3824c88f6f, 0x3f8c45ffe1e48ad9, // -0.9999, 0.013805 + 0xbfefff62169b92db, 0x3f8921d1fcdec784, // -0.99992, 0.012272 + 0xbfefff871937ce2f, 0x3f85fda037ac05e0, // -0.99994, 0.010738 + 0xbfefffa72c978c4f, 0x3f82d96b0e509703, // -0.99996, 0.0092038 + 0xbfefffc250b5daef, 0x3f7f6a65f9a2a3c5, // -0.99997, 0.0076698 + 0xbfefffd8858e8a92, 0x3f7921f0fe670071, // -0.99998, 0.0061359 + 0xbfefffe9cb1e2e8d, 0x3f72d97822f996bc, // -0.99999, 0.0046019 + 0xbfeffff621621d02, 0x3f6921f8becca4ba, // -1, 0.003068 + 0xbfeffffd88586ee6, 0x3f5921faaee6472d, // -1, 0.001534 + 0xbff0000000000000, 0x0000000000000000, // -1, 0 + 0xbfeffffd88586ee6, 0xbf5921faaee6472d, // -1, -0.001534 + 0xbfeffff621621d02, 0xbf6921f8becca4ba, // -1, -0.003068 + 0xbfefffe9cb1e2e8d, 0xbf72d97822f996bc, // -0.99999,-0.0046019 + 0xbfefffd8858e8a92, 0xbf7921f0fe670071, // -0.99998,-0.0061359 + 0xbfefffc250b5daef, 0xbf7f6a65f9a2a3c5, // -0.99997,-0.0076698 + 0xbfefffa72c978c4f, 0xbf82d96b0e509703, // -0.99996,-0.0092038 + 0xbfefff871937ce2f, 0xbf85fda037ac05e0, // -0.99994, -0.010738 + 0xbfefff62169b92db, 0xbf8921d1fcdec784, // -0.99992, -0.012272 + 0xbfefff3824c88f6f, 0xbf8c45ffe1e48ad9, // -0.9999, -0.013805 + 0xbfefff0943c53bd1, 0xbf8f6a296ab997ca, // -0.99988, -0.015339 + 0xbfeffed57398d2b7, 0xbf9147270dad7132, // -0.99986, -0.016873 + 0xbfeffe9cb44b51a1, 0xbf92d936bbe30efd, // -0.99983, -0.018407 + 0xbfeffe5f05e578db, 0xbf946b4381fce81c, // -0.9998, -0.01994 + 0xbfeffe1c6870cb77, 0xbf95fd4d21fab226, // -0.99977, -0.021474 + 0xbfeffdd4dbf78f52, 0xbf978f535ddc9f03, // -0.99974, -0.023008 + 0xbfeffd886084cd0d, 0xbf992155f7a3667e, // -0.9997, -0.024541 + 0xbfeffd36f624500c, 0xbf9ab354b1504fca, // -0.99966, -0.026075 + 0xbfeffce09ce2a679, 0xbf9c454f4ce53b1c, // -0.99962, -0.027608 + 0xbfeffc8554cd213a, 0xbf9dd7458c64ab39, // -0.99958, -0.029142 + 0xbfeffc251df1d3f8, 0xbf9f693731d1cf01, // -0.99953, -0.030675 + 0xbfeffbbff85f9515, 0xbfa07d91ff984580, // -0.99948, -0.032208 + 0xbfeffb55e425fdae, 0xbfa14685db42c17e, // -0.99943, -0.033741 + 0xbfeffae6e1556998, 0xbfa20f770ceb11c6, // -0.99938, -0.035274 + 0xbfeffa72effef75d, 0xbfa2d865759455cd, // -0.99932, -0.036807 + 0xbfeff9fa10348837, 0xbfa3a150f6421afc, // -0.99926, -0.03834 + 0xbfeff97c4208c014, 0xbfa46a396ff86179, // -0.9992, -0.039873 + 0xbfeff8f9858f058b, 0xbfa5331ec3bba0eb, // -0.99914, -0.041406 + 0xbfeff871dadb81df, 0xbfa5fc00d290cd43, // -0.99908, -0.042938 + 0xbfeff7e5420320f9, 0xbfa6c4df7d7d5b84, // -0.99901, -0.044471 + 0xbfeff753bb1b9164, 0xbfa78dbaa5874685, // -0.99894, -0.046003 + 0xbfeff6bd463b444d, 0xbfa856922bb513c1, // -0.99887, -0.047535 + 0xbfeff621e3796d7e, 0xbfa91f65f10dd814, // -0.9988, -0.049068 + 0xbfeff58192ee0358, 0xbfa9e835d6993c87, // -0.99872, -0.0506 + 0xbfeff4dc54b1bed3, 0xbfaab101bd5f8317, // -0.99864, -0.052132 + 0xbfeff43228de1b77, 0xbfab79c986698b78, // -0.99856, -0.053664 + 0xbfeff3830f8d575c, 0xbfac428d12c0d7e3, // -0.99848, -0.055195 + 0xbfeff2cf08da7321, 0xbfad0b4c436f91d0, // -0.99839, -0.056727 + 0xbfeff21614e131ed, 0xbfadd406f9808ec8, // -0.9983, -0.058258 + 0xbfeff15833be1965, 0xbfae9cbd15ff5527, // -0.99821, -0.05979 + 0xbfeff095658e71ad, 0xbfaf656e79f820e0, // -0.99812, -0.061321 + 0xbfefefcdaa704562, 0xbfb0170d833bf421, // -0.99802, -0.062852 + 0xbfefef0102826191, 0xbfb07b614e463064, // -0.99793, -0.064383 + 0xbfefee2f6de455ba, 0xbfb0dfb28ea201e6, // -0.99783, -0.065913 + 0xbfefed58ecb673c4, 0xbfb1440134d709b2, // -0.99772, -0.067444 + 0xbfefec7d7f19cffc, 0xbfb1a84d316d4f8a, // -0.99762, -0.068974 + 0xbfefeb9d2530410f, 0xbfb20c9674ed444c, // -0.99751, -0.070505 + 0xbfefeab7df1c6005, 0xbfb270dcefdfc45b, // -0.9974, -0.072035 + 0xbfefe9cdad01883a, 0xbfb2d52092ce19f6, // -0.99729, -0.073565 + 0xbfefe8de8f03d75c, 0xbfb339614e41ffa5, // -0.99718, -0.075094 + 0xbfefe7ea85482d60, 0xbfb39d9f12c5a299, // -0.99706, -0.076624 + 0xbfefe6f18ff42c84, 0xbfb401d9d0e3a507, // -0.99694, -0.078153 + 0xbfefe5f3af2e3940, 0xbfb4661179272096, // -0.99682, -0.079682 + 0xbfefe4f0e31d7a4a, 0xbfb4ca45fc1ba8b6, // -0.9967, -0.081211 + 0xbfefe3e92be9d886, 0xbfb52e774a4d4d0a, // -0.99657, -0.08274 + 0xbfefe2dc89bbff08, 0xbfb592a554489bc8, // -0.99644, -0.084269 + 0xbfefe1cafcbd5b09, 0xbfb5f6d00a9aa419, // -0.99631, -0.085797 + 0xbfefe0b485181be3, 0xbfb65af75dd0f87b, // -0.99618, -0.087326 + 0xbfefdf9922f73307, 0xbfb6bf1b3e79b129, // -0.99604, -0.088854 + 0xbfefde78d68653fd, 0xbfb7233b9d236e71, // -0.99591, -0.090381 + 0xbfefdd539ff1f456, 0xbfb787586a5d5b21, // -0.99577, -0.091909 + 0xbfefdc297f674ba9, 0xbfb7eb7196b72ee4, // -0.99563, -0.093436 + 0xbfefdafa7514538c, 0xbfb84f8712c130a0, // -0.99548, -0.094963 + 0xbfefd9c68127c78c, 0xbfb8b398cf0c38e0, // -0.99533, -0.09649 + 0xbfefd88da3d12526, 0xbfb917a6bc29b42c, // -0.99518, -0.098017 + 0xbfefd74fdd40abbf, 0xbfb97bb0caaba56f, // -0.99503, -0.099544 + 0xbfefd60d2da75c9e, 0xbfb9dfb6eb24a85c, // -0.99488, -0.10107 + 0xbfefd4c59536fae4, 0xbfba43b90e27f3c4, // -0.99472, -0.1026 + 0xbfefd37914220b84, 0xbfbaa7b724495c04, // -0.99456, -0.10412 + 0xbfefd227aa9bd53b, 0xbfbb0bb11e1d5559, // -0.9944, -0.10565 + 0xbfefd0d158d86087, 0xbfbb6fa6ec38f64c, // -0.99424, -0.10717 + 0xbfefcf761f0c77a3, 0xbfbbd3987f31fa0e, // -0.99407, -0.1087 + 0xbfefce15fd6da67b, 0xbfbc3785c79ec2d5, // -0.99391, -0.11022 + 0xbfefccb0f4323aa3, 0xbfbc9b6eb6165c42, // -0.99374, -0.11175 + 0xbfefcb4703914354, 0xbfbcff533b307dc1, // -0.99356, -0.11327 + 0xbfefc9d82bc2915e, 0xbfbd633347858ce4, // -0.99339, -0.11479 + 0xbfefc8646cfeb721, 0xbfbdc70ecbae9fc8, // -0.99321, -0.11632 + 0xbfefc6ebc77f0887, 0xbfbe2ae5b8457f77, // -0.99303, -0.11784 + 0xbfefc56e3b7d9af6, 0xbfbe8eb7fde4aa3e, // -0.99285, -0.11937 + 0xbfefc3ebc935454c, 0xbfbef2858d27561b, // -0.99267, -0.12089 + 0xbfefc26470e19fd3, 0xbfbf564e56a9730e, // -0.99248, -0.12241 + 0xbfefc0d832bf043a, 0xbfbfba124b07ad85, // -0.99229, -0.12393 + 0xbfefbf470f0a8d88, 0xbfc00ee8ad6fb85b, // -0.9921, -0.12545 + 0xbfefbdb106021816, 0xbfc040c5bb67747e, // -0.99191, -0.12698 + 0xbfefbc1617e44186, 0xbfc072a047ba831d, // -0.99171, -0.1285 + 0xbfefba7644f068b5, 0xbfc0a4784ab8bf1d, // -0.99151, -0.13002 + 0xbfefb8d18d66adb7, 0xbfc0d64dbcb26786, // -0.99131, -0.13154 + 0xbfefb727f187f1c7, 0xbfc1082095f820b0, // -0.99111, -0.13306 + 0xbfefb5797195d741, 0xbfc139f0cedaf576, // -0.9909, -0.13458 + 0xbfefb3c60dd2c199, 0xbfc16bbe5fac5865, // -0.9907, -0.1361 + 0xbfefb20dc681d54d, 0xbfc19d8940be24e7, // -0.99049, -0.13762 + 0xbfefb0509be6f7db, 0xbfc1cf516a62a077, // -0.99027, -0.13914 + 0xbfefae8e8e46cfbb, 0xbfc20116d4ec7bce, // -0.99006, -0.14066 + 0xbfefacc79de6c44f, 0xbfc232d978aed413, // -0.98984, -0.14218 + 0xbfefaafbcb0cfddc, 0xbfc264994dfd340a, // -0.98962, -0.1437 + 0xbfefa92b1600657c, 0xbfc296564d2b953e, // -0.9894, -0.14521 + 0xbfefa7557f08a517, 0xbfc2c8106e8e613a, // -0.98918, -0.14673 + 0xbfefa57b066e2754, 0xbfc2f9c7aa7a72af, // -0.98895, -0.14825 + 0xbfefa39bac7a1791, 0xbfc32b7bf94516a7, // -0.98872, -0.14976 + 0xbfefa1b7717661d5, 0xbfc35d2d53440db2, // -0.98849, -0.15128 + 0xbfef9fce55adb2c8, 0xbfc38edbb0cd8d14, // -0.98826, -0.1528 + 0xbfef9de0596b77a3, 0xbfc3c0870a383ff6, // -0.98802, -0.15431 + 0xbfef9bed7cfbde29, 0xbfc3f22f57db4893, // -0.98778, -0.15583 + 0xbfef99f5c0abd496, 0xbfc423d4920e4166, // -0.98754, -0.15734 + 0xbfef97f924c9099b, 0xbfc45576b1293e5a, // -0.9873, -0.15886 + 0xbfef95f7a9a1ec47, 0xbfc48715ad84cdf5, // -0.98706, -0.16037 + 0xbfef93f14f85ac08, 0xbfc4b8b17f79fa88, // -0.98681, -0.16189 + 0xbfef91e616c43891, 0xbfc4ea4a1f624b61, // -0.98656, -0.1634 + 0xbfef8fd5ffae41db, 0xbfc51bdf8597c5f2, // -0.98631, -0.16491 + 0xbfef8dc10a95380d, 0xbfc54d71aa74ef02, // -0.98605, -0.16643 + 0xbfef8ba737cb4b78, 0xbfc57f008654cbde, // -0.9858, -0.16794 + 0xbfef898887a36c84, 0xbfc5b08c1192e381, // -0.98554, -0.16945 + 0xbfef8764fa714ba9, 0xbfc5e214448b3fc6, // -0.98528, -0.17096 + 0xbfef853c9089595e, 0xbfc61399179a6e94, // -0.98501, -0.17247 + 0xbfef830f4a40c60c, 0xbfc6451a831d830d, // -0.98475, -0.17398 + 0xbfef80dd27ed8204, 0xbfc676987f7216b8, // -0.98448, -0.17549 + 0xbfef7ea629e63d6e, 0xbfc6a81304f64ab2, // -0.98421, -0.177 + 0xbfef7c6a50826840, 0xbfc6d98a0c08c8da, // -0.98394, -0.17851 + 0xbfef7a299c1a322a, 0xbfc70afd8d08c4ff, // -0.98366, -0.18002 + 0xbfef77e40d068a90, 0xbfc73c6d8055fe0a, // -0.98339, -0.18153 + 0xbfef7599a3a12077, 0xbfc76dd9de50bf31, // -0.98311, -0.18304 + 0xbfef734a60446279, 0xbfc79f429f59e11d, // -0.98282, -0.18455 + 0xbfef70f6434b7eb7, 0xbfc7d0a7bbd2cb1b, // -0.98254, -0.18606 + 0xbfef6e9d4d1262ca, 0xbfc802092c1d744b, // -0.98225, -0.18756 + 0xbfef6c3f7df5bbb7, 0xbfc83366e89c64c5, // -0.98196, -0.18907 + 0xbfef69dcd652f5de, 0xbfc864c0e9b2b6cf, // -0.98167, -0.19057 + 0xbfef677556883cee, 0xbfc8961727c41804, // -0.98138, -0.19208 + 0xbfef6508fef47bd5, 0xbfc8c7699b34ca7e, // -0.98108, -0.19359 + 0xbfef6297cff75cb0, 0xbfc8f8b83c69a60a, // -0.98079, -0.19509 + 0xbfef6021c9f148c2, 0xbfc92a0303c8194f, // -0.98048, -0.19659 + 0xbfef5da6ed43685d, 0xbfc95b49e9b62af9, // -0.98018, -0.1981 + 0xbfef5b273a4fa2d9, 0xbfc98c8ce69a7aec, // -0.97988, -0.1996 + 0xbfef58a2b1789e84, 0xbfc9bdcbf2dc4366, // -0.97957, -0.2011 + 0xbfef56195321c090, 0xbfc9ef0706e35a35, // -0.97926, -0.20261 + 0xbfef538b1faf2d07, 0xbfca203e1b1831da, // -0.97895, -0.20411 + 0xbfef50f81785c6b9, 0xbfca517127e3dabc, // -0.97863, -0.20561 + 0xbfef4e603b0b2f2d, 0xbfca82a025b00451, // -0.97832, -0.20711 + 0xbfef4bc38aa5c694, 0xbfcab3cb0ce6fe44, // -0.978, -0.20861 + 0xbfef492206bcabb4, 0xbfcae4f1d5f3b9ab, // -0.97768, -0.21011 + 0xbfef467bafb7bbe0, 0xbfcb16147941ca2a, // -0.97735, -0.21161 + 0xbfef43d085ff92dd, 0xbfcb4732ef3d6722, // -0.97703, -0.21311 + 0xbfef412089fd8adc, 0xbfcb784d30536cda, // -0.9767, -0.21461 + 0xbfef3e6bbc1bbc65, 0xbfcba96334f15dad, // -0.97637, -0.21611 + 0xbfef3bb21cc4fe47, 0xbfcbda74f5856330, // -0.97604, -0.2176 + 0xbfef38f3ac64e589, 0xbfcc0b826a7e4f63, // -0.9757, -0.2191 + 0xbfef36306b67c556, 0xbfcc3c8b8c4b9dd7, // -0.97536, -0.2206 + 0xbfef33685a3aaef0, 0xbfcc6d90535d74dc, // -0.97503, -0.22209 + 0xbfef309b794b719f, 0xbfcc9e90b824a6a9, // -0.97468, -0.22359 + 0xbfef2dc9c9089a9d, 0xbfcccf8cb312b286, // -0.97434, -0.22508 + 0xbfef2af349e17507, 0xbfcd00843c99c5f9, // -0.97399, -0.22658 + 0xbfef2817fc4609ce, 0xbfcd31774d2cbdee, // -0.97364, -0.22807 + 0xbfef2537e0a71f9f, 0xbfcd6265dd3f27e3, // -0.97329, -0.22957 + 0xbfef2252f7763ada, 0xbfcd934fe5454311, // -0.97294, -0.23106 + 0xbfef1f6941259d7a, 0xbfcdc4355db40195, // -0.97258, -0.23255 + 0xbfef1c7abe284708, 0xbfcdf5163f01099a, // -0.97223, -0.23404 + 0xbfef19876ef1f486, 0xbfce25f281a2b684, // -0.97187, -0.23553 + 0xbfef168f53f7205d, 0xbfce56ca1e101a1b, // -0.9715, -0.23702 + 0xbfef13926dad024e, 0xbfce879d0cc0fdaf, // -0.97114, -0.23851 + 0xbfef1090bc898f5f, 0xbfceb86b462de348, // -0.97077, -0.24 + 0xbfef0d8a410379c5, 0xbfcee934c2d006c7, // -0.9704, -0.24149 + 0xbfef0a7efb9230d7, 0xbfcf19f97b215f1a, // -0.97003, -0.24298 + 0xbfef076eecade0fa, 0xbfcf4ab9679c9f5c, // -0.96966, -0.24447 + 0xbfef045a14cf738c, 0xbfcf7b7480bd3801, // -0.96928, -0.24596 + 0xbfef014074708ed3, 0xbfcfac2abeff57ff, // -0.9689, -0.24744 + 0xbfeefe220c0b95ec, 0xbfcfdcdc1adfedf8, // -0.96852, -0.24893 + 0xbfeefafedc1ba8b7, 0xbfd006c4466e54af, // -0.96814, -0.25041 + 0xbfeef7d6e51ca3c0, 0xbfd01f1806b9fdd2, // -0.96775, -0.2519 + 0xbfeef4aa278b2032, 0xbfd037694a928cac, // -0.96737, -0.25338 + 0xbfeef178a3e473c2, 0xbfd04fb80e37fdae, // -0.96698, -0.25487 + 0xbfeeee425aa6b09a, 0xbfd068044deab002, // -0.96658, -0.25635 + 0xbfeeeb074c50a544, 0xbfd0804e05eb661e, // -0.96619, -0.25783 + 0xbfeee7c77961dc9e, 0xbfd09895327b465e, // -0.96579, -0.25931 + 0xbfeee482e25a9dbc, 0xbfd0b0d9cfdbdb90, // -0.96539, -0.26079 + 0xbfeee13987bbebdc, 0xbfd0c91bda4f158d, // -0.96499, -0.26227 + 0xbfeeddeb6a078651, 0xbfd0e15b4e1749cd, // -0.96459, -0.26375 + 0xbfeeda9889bfe86a, 0xbfd0f998277733f7, // -0.96418, -0.26523 + 0xbfeed740e7684963, 0xbfd111d262b1f677, // -0.96378, -0.26671 + 0xbfeed3e483849c51, 0xbfd12a09fc0b1b12, // -0.96337, -0.26819 + 0xbfeed0835e999009, 0xbfd1423eefc69378, // -0.96295, -0.26967 + 0xbfeecd1d792c8f10, 0xbfd15a713a28b9d9, // -0.96254, -0.27115 + 0xbfeec9b2d3c3bf84, 0xbfd172a0d7765177, // -0.96212, -0.27262 + 0xbfeec6436ee60309, 0xbfd18acdc3f4873a, // -0.9617, -0.2741 + 0xbfeec2cf4b1af6b2, 0xbfd1a2f7fbe8f243, // -0.96128, -0.27557 + 0xbfeebf5668eaf2ef, 0xbfd1bb1f7b999480, // -0.96086, -0.27705 + 0xbfeebbd8c8df0b74, 0xbfd1d3443f4cdb3d, // -0.96043, -0.27852 + 0xbfeeb8566b810f2a, 0xbfd1eb6643499fbb, // -0.96, -0.27999 + 0xbfeeb4cf515b8811, 0xbfd2038583d727bd, // -0.95957, -0.28146 + 0xbfeeb1437af9bb34, 0xbfd21ba1fd3d2623, // -0.95914, -0.28294 + 0xbfeeadb2e8e7a88e, 0xbfd233bbabc3bb72, // -0.9587, -0.28441 + 0xbfeeaa1d9bb20af3, 0xbfd24bd28bb37672, // -0.95827, -0.28588 + 0xbfeea68393e65800, 0xbfd263e6995554ba, // -0.95783, -0.28735 + 0xbfeea2e4d212c000, 0xbfd27bf7d0f2c346, // -0.95738, -0.28882 + 0xbfee9f4156c62dda, 0xbfd294062ed59f05, // -0.95694, -0.29028 + 0xbfee9b99229046f8, 0xbfd2ac11af483572, // -0.95649, -0.29175 + 0xbfee97ec36016b30, 0xbfd2c41a4e954520, // -0.95605, -0.29322 + 0xbfee943a91aab4b4, 0xbfd2dc200907fe51, // -0.95559, -0.29469 + 0xbfee9084361df7f3, 0xbfd2f422daec0386, // -0.95514, -0.29615 + 0xbfee8cc923edc388, 0xbfd30c22c08d6a13, // -0.95469, -0.29762 + 0xbfee89095bad6025, 0xbfd3241fb638baaf, // -0.95423, -0.29908 + 0xbfee8544ddf0d075, 0xbfd33c19b83af207, // -0.95377, -0.30054 + 0xbfee817bab4cd10d, 0xbfd35410c2e18152, // -0.95331, -0.30201 + 0xbfee7dadc456d850, 0xbfd36c04d27a4edf, // -0.95284, -0.30347 + 0xbfee79db29a5165a, 0xbfd383f5e353b6aa, // -0.95238, -0.30493 + 0xbfee7603dbce74e9, 0xbfd39be3f1bc8aef, // -0.95191, -0.30639 + 0xbfee7227db6a9744, 0xbfd3b3cefa0414b7, // -0.95144, -0.30785 + 0xbfee6e472911da27, 0xbfd3cbb6f87a146e, // -0.95096, -0.30931 + 0xbfee6a61c55d53a7, 0xbfd3e39be96ec271, // -0.95049, -0.31077 + 0xbfee6677b0e6d31e, 0xbfd3fb7dc932cfa4, // -0.95001, -0.31222 + 0xbfee6288ec48e112, 0xbfd4135c94176602, // -0.94953, -0.31368 + 0xbfee5e95781ebf1c, 0xbfd42b38466e2928, // -0.94905, -0.31514 + 0xbfee5a9d550467d3, 0xbfd44310dc8936f0, // -0.94856, -0.31659 + 0xbfee56a083968eb1, 0xbfd45ae652bb2800, // -0.94807, -0.31805 + 0xbfee529f04729ffc, 0xbfd472b8a5571054, // -0.94759, -0.3195 + 0xbfee4e98d836c0af, 0xbfd48a87d0b07fd7, // -0.94709, -0.32096 + 0xbfee4a8dff81ce5e, 0xbfd4a253d11b82f3, // -0.9466, -0.32241 + 0xbfee467e7af35f23, 0xbfd4ba1ca2eca31c, // -0.94611, -0.32386 + 0xbfee426a4b2bc17e, 0xbfd4d1e24278e76a, // -0.94561, -0.32531 + 0xbfee3e5170cbfc46, 0xbfd4e9a4ac15d520, // -0.94511, -0.32676 + 0xbfee3a33ec75ce85, 0xbfd50163dc197047, // -0.9446, -0.32821 + 0xbfee3611becbaf69, 0xbfd5191fceda3c35, // -0.9441, -0.32966 + 0xbfee31eae870ce25, 0xbfd530d880af3c24, // -0.94359, -0.33111 + 0xbfee2dbf6a0911d9, 0xbfd5488dedeff3be, // -0.94308, -0.33255 + 0xbfee298f4439197a, 0xbfd5604012f467b4, // -0.94257, -0.334 + 0xbfee255a77a63bb8, 0xbfd577eeec151e47, // -0.94206, -0.33545 + 0xbfee212104f686e5, 0xbfd58f9a75ab1fdd, // -0.94154, -0.33689 + 0xbfee1ce2ecd0c0d8, 0xbfd5a742ac0ff78d, // -0.94103, -0.33833 + 0xbfee18a02fdc66d9, 0xbfd5bee78b9db3b6, // -0.94051, -0.33978 + 0xbfee1458cec1ad83, 0xbfd5d68910aee686, // -0.93998, -0.34122 + 0xbfee100cca2980ac, 0xbfd5ee27379ea693, // -0.93946, -0.34266 + 0xbfee0bbc22bd8349, 0xbfd605c1fcc88f63, // -0.93893, -0.3441 + 0xbfee0766d9280f54, 0xbfd61d595c88c203, // -0.9384, -0.34554 + 0xbfee030cee1435b8, 0xbfd634ed533be58e, // -0.93787, -0.34698 + 0xbfedfeae622dbe2b, 0xbfd64c7ddd3f27c6, // -0.93734, -0.34842 + 0xbfedfa4b3621271d, 0xbfd6640af6f03d9e, // -0.9368, -0.34986 + 0xbfedf5e36a9ba59c, 0xbfd67b949cad63ca, // -0.93627, -0.35129 + 0xbfedf177004b2534, 0xbfd6931acad55f51, // -0.93573, -0.35273 + 0xbfeded05f7de47da, 0xbfd6aa9d7dc77e16, // -0.93518, -0.35416 + 0xbfede890520465ce, 0xbfd6c21cb1e39771, // -0.93464, -0.3556 + 0xbfede4160f6d8d81, 0xbfd6d998638a0cb5, // -0.93409, -0.35703 + 0xbfeddf9730ca837b, 0xbfd6f1108f1bc9c5, // -0.93354, -0.35846 + 0xbfeddb13b6ccc23d, 0xbfd7088530fa459e, // -0.93299, -0.3599 + 0xbfedd68ba2267a25, 0xbfd71ff6458782ec, // -0.93244, -0.36133 + 0xbfedd1fef38a915a, 0xbfd73763c9261092, // -0.93188, -0.36276 + 0xbfedcd6dabaca3a5, 0xbfd74ecdb8390a3e, // -0.93133, -0.36418 + 0xbfedc8d7cb410260, 0xbfd766340f2418f6, // -0.93077, -0.36561 + 0xbfedc43d52fcb453, 0xbfd77d96ca4b73a6, // -0.93021, -0.36704 + 0xbfedbf9e4395759a, 0xbfd794f5e613dfae, // -0.92964, -0.36847 + 0xbfedbafa9dc1b78d, 0xbfd7ac515ee2b172, // -0.92907, -0.36989 + 0xbfedb6526238a09b, 0xbfd7c3a9311dcce7, // -0.92851, -0.37132 + 0xbfedb1a591b20c38, 0xbfd7dafd592ba621, // -0.92794, -0.37274 + 0xbfedacf42ce68ab9, 0xbfd7f24dd37341e3, // -0.92736, -0.37416 + 0xbfeda83e348f613b, 0xbfd8099a9c5c362d, // -0.92679, -0.37559 + 0xbfeda383a9668988, 0xbfd820e3b04eaac4, // -0.92621, -0.37701 + 0xbfed9ec48c26b1f3, 0xbfd838290bb359c8, // -0.92563, -0.37843 + 0xbfed9a00dd8b3d46, 0xbfd84f6aaaf3903f, // -0.92505, -0.37985 + 0xbfed95389e50429b, 0xbfd866a88a792ea0, // -0.92447, -0.38127 + 0xbfed906bcf328d46, 0xbfd87de2a6aea963, // -0.92388, -0.38268 + 0xbfed8b9a70ef9cb4, 0xbfd89518fbff098e, // -0.92329, -0.3841 + 0xbfed86c48445a450, 0xbfd8ac4b86d5ed44, // -0.9227, -0.38552 + 0xbfed81ea09f38b63, 0xbfd8c37a439f884f, // -0.92211, -0.38693 + 0xbfed7d0b02b8ecf9, 0xbfd8daa52ec8a4af, // -0.92151, -0.38835 + 0xbfed78276f5617c6, 0xbfd8f1cc44bea329, // -0.92092, -0.38976 + 0xbfed733f508c0dff, 0xbfd908ef81ef7bd1, // -0.92032, -0.39117 + 0xbfed6e52a71c8547, 0xbfd9200ee2c9be97, // -0.91972, -0.39258 + 0xbfed696173c9e68b, 0xbfd9372a63bc93d7, // -0.91911, -0.39399 + 0xbfed646bb7574de5, 0xbfd94e420137bce3, // -0.91851, -0.3954 + 0xbfed5f7172888a7f, 0xbfd96555b7ab948f, // -0.9179, -0.39681 + 0xbfed5a72a6221e73, 0xbfd97c6583890fc2, // -0.91729, -0.39822 + 0xbfed556f52e93eb1, 0xbfd993716141bdfe, // -0.91668, -0.39962 + 0xbfed506779a3d2d9, 0xbfd9aa794d47c9ee, // -0.91606, -0.40103 + 0xbfed4b5b1b187524, 0xbfd9c17d440df9f2, // -0.91545, -0.40243 + 0xbfed464a380e7242, 0xbfd9d87d4207b0ab, // -0.91483, -0.40384 + 0xbfed4134d14dc93a, 0xbfd9ef7943a8ed8a, // -0.91421, -0.40524 + 0xbfed3c1ae79f2b4e, 0xbfda067145664d57, // -0.91359, -0.40664 + 0xbfed36fc7bcbfbdc, 0xbfda1d6543b50ac0, // -0.91296, -0.40804 + 0xbfed31d98e9e503a, 0xbfda34553b0afee5, // -0.91234, -0.40944 + 0xbfed2cb220e0ef9f, 0xbfda4b4127dea1e4, // -0.91171, -0.41084 + 0xbfed2786335f52fc, 0xbfda622906a70b63, // -0.91107, -0.41224 + 0xbfed2255c6e5a4e1, 0xbfda790cd3dbf31a, // -0.91044, -0.41364 + 0xbfed1d20dc40c15c, 0xbfda8fec8bf5b166, // -0.90981, -0.41503 + 0xbfed17e7743e35dc, 0xbfdaa6c82b6d3fc9, // -0.90917, -0.41643 + 0xbfed12a98fac410c, 0xbfdabd9faebc3980, // -0.90853, -0.41782 + 0xbfed0d672f59d2b9, 0xbfdad473125cdc08, // -0.90789, -0.41922 + 0xbfed082054168bac, 0xbfdaeb4252ca07ab, // -0.90724, -0.42061 + 0xbfed02d4feb2bd92, 0xbfdb020d6c7f4009, // -0.9066, -0.422 + 0xbfecfd852fff6ad4, 0xbfdb18d45bf8aca6, // -0.90595, -0.42339 + 0xbfecf830e8ce467b, 0xbfdb2f971db31972, // -0.9053, -0.42478 + 0xbfecf2d829f1b40e, 0xbfdb4655ae2bf757, // -0.90464, -0.42617 + 0xbfeced7af43cc773, 0xbfdb5d1009e15cc0, // -0.90399, -0.42756 + 0xbfece819488344ce, 0xbfdb73c62d520624, // -0.90333, -0.42894 + 0xbfece2b32799a060, 0xbfdb8a7814fd5693, // -0.90267, -0.43033 + 0xbfecdd489254fe65, 0xbfdba125bd63583e, // -0.90201, -0.43171 + 0xbfecd7d9898b32f6, 0xbfdbb7cf2304bd01, // -0.90135, -0.43309 + 0xbfecd2660e12c1e6, 0xbfdbce744262deee, // -0.90068, -0.43448 + 0xbfecccee20c2de9f, 0xbfdbe51517ffc0d9, // -0.90002, -0.43586 + 0xbfecc771c2736c09, 0xbfdbfbb1a05e0edc, // -0.89935, -0.43724 + 0xbfecc1f0f3fcfc5c, 0xbfdc1249d8011ee7, // -0.89867, -0.43862 + 0xbfecbc6bb638d10b, 0xbfdc28ddbb6cf145, // -0.898, -0.43999 + 0xbfecb6e20a00da99, 0xbfdc3f6d47263129, // -0.89732, -0.44137 + 0xbfecb153f02fb87d, 0xbfdc55f877b23537, // -0.89665, -0.44275 + 0xbfecabc169a0b901, 0xbfdc6c7f4997000a, // -0.89597, -0.44412 + 0xbfeca62a772fd919, 0xbfdc8301b95b40c2, // -0.89528, -0.4455 + 0xbfeca08f19b9c449, 0xbfdc997fc3865388, // -0.8946, -0.44687 + 0xbfec9aef521bd480, 0xbfdcaff964a0421d, // -0.89391, -0.44824 + 0xbfec954b213411f5, 0xbfdcc66e9931c45d, // -0.89322, -0.44961 + 0xbfec8fa287e13305, 0xbfdcdcdf5dc440ce, // -0.89253, -0.45098 + 0xbfec89f587029c13, 0xbfdcf34baee1cd21, // -0.89184, -0.45235 + 0xbfec84441f785f61, 0xbfdd09b389152ec1, // -0.89115, -0.45372 + 0xbfec7e8e52233cf3, 0xbfdd2016e8e9db5b, // -0.89045, -0.45508 + 0xbfec78d41fe4a267, 0xbfdd3675caebf962, // -0.88975, -0.45645 + 0xbfec7315899eaad7, 0xbfdd4cd02ba8609c, // -0.88905, -0.45781 + 0xbfec6d5290341eb2, 0xbfdd632607ac9aa9, // -0.88835, -0.45918 + 0xbfec678b3488739b, 0xbfdd79775b86e389, // -0.88764, -0.46054 + 0xbfec61bf777fcc48, 0xbfdd8fc423c62a25, // -0.88693, -0.4619 + 0xbfec5bef59fef85a, 0xbfdda60c5cfa10d8, // -0.88622, -0.46326 + 0xbfec561adceb743e, 0xbfddbc5003b2edf8, // -0.88551, -0.46462 + 0xbfec5042012b6907, 0xbfddd28f1481cc58, // -0.8848, -0.46598 + 0xbfec4a64c7a5ac4c, 0xbfdde8c98bf86bd6, // -0.88408, -0.46733 + 0xbfec44833141c004, 0xbfddfeff66a941de, // -0.88336, -0.46869 + 0xbfec3e9d3ee7d262, 0xbfde1530a12779f4, // -0.88264, -0.47004 + 0xbfec38b2f180bdb1, 0xbfde2b5d3806f63b, // -0.88192, -0.4714 + 0xbfec32c449f60831, 0xbfde418527dc4ffa, // -0.8812, -0.47275 + 0xbfec2cd14931e3f1, 0xbfde57a86d3cd824, // -0.88047, -0.4741 + 0xbfec26d9f01f2eaf, 0xbfde6dc704be97e2, // -0.87974, -0.47545 + 0xbfec20de3fa971b0, 0xbfde83e0eaf85113, // -0.87901, -0.4768 + 0xbfec1ade38bce19b, 0xbfde99f61c817eda, // -0.87828, -0.47815 + 0xbfec14d9dc465e58, 0xbfdeb00695f25620, // -0.87755, -0.47949 + 0xbfec0ed12b3372e9, 0xbfdec61253e3c61b, // -0.87681, -0.48084 + 0xbfec08c426725549, 0xbfdedc1952ef78d5, // -0.87607, -0.48218 + 0xbfec02b2cef1e641, 0xbfdef21b8fafd3b5, // -0.87533, -0.48353 + 0xbfebfc9d25a1b147, 0xbfdf081906bff7fd, // -0.87459, -0.48487 + 0xbfebf6832b71ec5b, 0xbfdf1e11b4bbc35c, // -0.87384, -0.48621 + 0xbfebf064e15377dd, 0xbfdf3405963fd068, // -0.87309, -0.48755 + 0xbfebea424837de6d, 0xbfdf49f4a7e97729, // -0.87235, -0.48889 + 0xbfebe41b611154c1, 0xbfdf5fdee656cda3, // -0.8716, -0.49023 + 0xbfebddf02cd2b983, 0xbfdf75c44e26a852, // -0.87084, -0.49156 + 0xbfebd7c0ac6f952a, 0xbfdf8ba4dbf89aba, // -0.87009, -0.4929 + 0xbfebd18ce0dc19d6, 0xbfdfa1808c6cf7e0, // -0.86933, -0.49423 + 0xbfebcb54cb0d2327, 0xbfdfb7575c24d2de, // -0.86857, -0.49557 + 0xbfebc5186bf8361d, 0xbfdfcd2947c1ff57, // -0.86781, -0.4969 + 0xbfebbed7c49380ea, 0xbfdfe2f64be7120f, // -0.86705, -0.49823 + 0xbfebb892d5d5dad5, 0xbfdff8be6537615e, // -0.86628, -0.49956 + 0xbfebb249a0b6c40d, 0xbfe00740c82b82e0, // -0.86551, -0.50089 + 0xbfebabfc262e6586, 0xbfe0121fe4f56d2c, // -0.86474, -0.50221 + 0xbfeba5aa673590d2, 0xbfe01cfc874c3eb7, // -0.86397, -0.50354 + 0xbfeb9f5464c5bffc, 0xbfe027d6ad83287e, // -0.8632, -0.50486 + 0xbfeb98fa1fd9155e, 0xbfe032ae55edbd95, // -0.86242, -0.50619 + 0xbfeb929b996a5b7f, 0xbfe03d837edff370, // -0.86165, -0.50751 + 0xbfeb8c38d27504e9, 0xbfe0485626ae221a, // -0.86087, -0.50883 + 0xbfeb85d1cbf52c02, 0xbfe053264bad0483, // -0.86009, -0.51015 + 0xbfeb7f6686e792ea, 0xbfe05df3ec31b8b6, // -0.8593, -0.51147 + 0xbfeb78f70449a34b, 0xbfe068bf0691c028, // -0.85852, -0.51279 + 0xbfeb728345196e3e, 0xbfe073879922ffed, // -0.85773, -0.5141 + 0xbfeb6c0b4a55ac17, 0xbfe07e4da23bc102, // -0.85694, -0.51542 + 0xbfeb658f14fdbc47, 0xbfe089112032b08c, // -0.85615, -0.51673 + 0xbfeb5f0ea611a532, 0xbfe093d2115ee018, // -0.85535, -0.51804 + 0xbfeb5889fe921405, 0xbfe09e907417c5e1, // -0.85456, -0.51936 + 0xbfeb52011f805c92, 0xbfe0a94c46b53d0b, // -0.85376, -0.52067 + 0xbfeb4b7409de7925, 0xbfe0b405878f85ec, // -0.85296, -0.52198 + 0xbfeb44e2beaf0a61, 0xbfe0bebc34ff4646, // -0.85216, -0.52328 + 0xbfeb3e4d3ef55712, 0xbfe0c9704d5d898f, // -0.85136, -0.52459 + 0xbfeb37b38bb54c09, 0xbfe0d421cf03c12b, // -0.85055, -0.5259 + 0xbfeb3115a5f37bf4, 0xbfe0ded0b84bc4b5, // -0.84974, -0.5272 + 0xbfeb2a738eb51f33, 0xbfe0e97d078fd23b, // -0.84893, -0.5285 + 0xbfeb23cd470013b4, 0xbfe0f426bb2a8e7d, // -0.84812, -0.5298 + 0xbfeb1d22cfdadcc6, 0xbfe0fecdd1770537, // -0.84731, -0.5311 + 0xbfeb16742a4ca2f5, 0xbfe1097248d0a956, // -0.84649, -0.5324 + 0xbfeb0fc1575d33db, 0xbfe114141f935545, // -0.84567, -0.5337 + 0xbfeb090a58150200, 0xbfe11eb3541b4b22, // -0.84485, -0.535 + 0xbfeb024f2d7d24a9, 0xbfe1294fe4c5350a, // -0.84403, -0.53629 + 0xbfeafb8fd89f57b6, 0xbfe133e9cfee254e, // -0.84321, -0.53759 + 0xbfeaf4cc5a85fb73, 0xbfe13e8113f396c1, // -0.84238, -0.53888 + 0xbfeaee04b43c1474, 0xbfe14915af336ceb, // -0.84155, -0.54017 + 0xbfeae738e6cd4b67, 0xbfe153a7a00bf453, // -0.84073, -0.54146 + 0xbfeae068f345ecef, 0xbfe15e36e4dbe2bc, // -0.83989, -0.54275 + 0xbfead994dab2e979, 0xbfe168c37c025764, // -0.83906, -0.54404 + 0xbfead2bc9e21d511, 0xbfe1734d63dedb49, // -0.83822, -0.54532 + 0xbfeacbe03ea0e73b, 0xbfe17dd49ad16161, // -0.83739, -0.54661 + 0xbfeac4ffbd3efac8, 0xbfe188591f3a46e5, // -0.83655, -0.54789 + 0xbfeabe1b1b0b8dac, 0xbfe192daef7a5386, // -0.83571, -0.54918 + 0xbfeab7325916c0d4, 0xbfe19d5a09f2b9b8, // -0.83486, -0.55046 + 0xbfeab045787157ff, 0xbfe1a7d66d0516e6, // -0.83402, -0.55174 + 0xbfeaa9547a2cb98e, 0xbfe1b250171373be, // -0.83317, -0.55302 + 0xbfeaa25f5f5aee60, 0xbfe1bcc706804467, // -0.83232, -0.55429 + 0xbfea9b66290ea1a3, 0xbfe1c73b39ae68c8, // -0.83147, -0.55557 + 0xbfea9468d85b20ae, 0xbfe1d1acaf012cc2, // -0.83062, -0.55685 + 0xbfea8d676e545ad2, 0xbfe1dc1b64dc4872, // -0.82976, -0.55812 + 0xbfea8661ec0ee133, 0xbfe1e68759a3e074, // -0.8289, -0.55939 + 0xbfea7f58529fe69d, 0xbfe1f0f08bbc861b, // -0.82805, -0.56066 + 0xbfea784aa31d3f55, 0xbfe1fb56f98b37b8, // -0.82718, -0.56193 + 0xbfea7138de9d60f5, 0xbfe205baa17560d6, // -0.82632, -0.5632 + 0xbfea6a230637623b, 0xbfe2101b81e0da78, // -0.82546, -0.56447 + 0xbfea63091b02fae2, 0xbfe21a799933eb58, // -0.82459, -0.56573 + 0xbfea5beb1e188375, 0xbfe224d4e5d5482e, // -0.82372, -0.567 + 0xbfea54c91090f524, 0xbfe22f2d662c13e1, // -0.82285, -0.56826 + 0xbfea4da2f385e997, 0xbfe23983189fdfd5, // -0.82198, -0.56952 + 0xbfea4678c8119ac8, 0xbfe243d5fb98ac1f, // -0.8211, -0.57078 + 0xbfea3f4a8f4ee2d2, 0xbfe24e260d7ee7c9, // -0.82023, -0.57204 + 0xbfea38184a593bc6, 0xbfe258734cbb7110, // -0.81935, -0.5733 + 0xbfea30e1fa4cbf81, 0xbfe262bdb7b795a2, // -0.81847, -0.57455 + 0xbfea29a7a0462782, 0xbfe26d054cdd12df, // -0.81758, -0.57581 + 0xbfea22693d62ccb9, 0xbfe2774a0a961612, // -0.8167, -0.57706 + 0xbfea1b26d2c0a75e, 0xbfe2818bef4d3cba, // -0.81581, -0.57831 + 0xbfea13e0617e4ec7, 0xbfe28bcaf96d94ba, // -0.81493, -0.57956 + 0xbfea0c95eabaf937, 0xbfe2960727629ca8, // -0.81404, -0.58081 + 0xbfea05476f967bb5, 0xbfe2a040779843fb, // -0.81314, -0.58206 + 0xbfe9fdf4f13149de, 0xbfe2aa76e87aeb58, // -0.81225, -0.58331 + 0xbfe9f69e70ac75bc, 0xbfe2b4aa787764c4, // -0.81135, -0.58455 + 0xbfe9ef43ef29af94, 0xbfe2bedb25faf3ea, // -0.81046, -0.5858 + 0xbfe9e7e56dcb45bd, 0xbfe2c908ef734e57, // -0.80956, -0.58704 + 0xbfe9e082edb42472, 0xbfe2d333d34e9bb7, // -0.80866, -0.58828 + 0xbfe9d91c7007d5a6, 0xbfe2dd5bcffb7616, // -0.80775, -0.58952 + 0xbfe9d1b1f5ea80d6, 0xbfe2e780e3e8ea16, // -0.80685, -0.59076 + 0xbfe9ca438080eadb, 0xbfe2f1a30d86773a, // -0.80594, -0.592 + 0xbfe9c2d110f075c3, 0xbfe2fbc24b441015, // -0.80503, -0.59323 + 0xbfe9bb5aa85f2098, 0xbfe305de9b921a94, // -0.80412, -0.59447 + 0xbfe9b3e047f38741, 0xbfe30ff7fce17035, // -0.80321, -0.5957 + 0xbfe9ac61f0d4e247, 0xbfe31a0e6da35e44, // -0.80229, -0.59693 + 0xbfe9a4dfa42b06b2, 0xbfe32421ec49a620, // -0.80138, -0.59816 + 0xbfe99d59631e65d5, 0xbfe32e3277467d6b, // -0.80046, -0.59939 + 0xbfe995cf2ed80d22, 0xbfe338400d0c8e57, // -0.79954, -0.60062 + 0xbfe98e410881a600, 0xbfe3424aac0ef7d6, // -0.79861, -0.60184 + 0xbfe986aef1457594, 0xbfe34c5252c14de1, // -0.79769, -0.60307 + 0xbfe97f18ea4e5c9e, 0xbfe35656ff9799ae, // -0.79676, -0.60429 + 0xbfe9777ef4c7d742, 0xbfe36058b10659f3, // -0.79584, -0.60551 + 0xbfe96fe111ddfce0, 0xbfe36a576582831b, // -0.79491, -0.60673 + 0xbfe9683f42bd7fe1, 0xbfe374531b817f8d, // -0.79398, -0.60795 + 0xbfe960998893ad8c, 0xbfe37e4bd1792fe2, // -0.79304, -0.60917 + 0xbfe958efe48e6dd7, 0xbfe3884185dfeb22, // -0.79211, -0.61038 + 0xbfe9514257dc4335, 0xbfe39234372c7f04, // -0.79117, -0.6116 + 0xbfe94990e3ac4a6c, 0xbfe39c23e3d63029, // -0.79023, -0.61281 + 0xbfe941db892e3a65, 0xbfe3a6108a54ba58, // -0.78929, -0.61402 + 0xbfe93a22499263fc, 0xbfe3affa292050b9, // -0.78835, -0.61523 + 0xbfe932652609b1cf, 0xbfe3b9e0beb19e18, // -0.7874, -0.61644 + 0xbfe92aa41fc5a815, 0xbfe3c3c44981c517, // -0.78646, -0.61765 + 0xbfe922df37f8646a, 0xbfe3cda4c80a6076, // -0.78551, -0.61885 + 0xbfe91b166fd49da2, 0xbfe3d78238c58343, // -0.78456, -0.62006 + 0xbfe91349c88da398, 0xbfe3e15c9a2db922, // -0.7836, -0.62126 + 0xbfe90b7943575efe, 0xbfe3eb33eabe0680, // -0.78265, -0.62246 + 0xbfe903a4e1665133, 0xbfe3f50828f1e8d2, // -0.78169, -0.62366 + 0xbfe8fbcca3ef940d, 0xbfe3fed9534556d4, // -0.78074, -0.62486 + 0xbfe8f3f08c28d9ac, 0xbfe408a76834c0c0, // -0.77978, -0.62606 + 0xbfe8ec109b486c49, 0xbfe41272663d108c, // -0.77882, -0.62725 + 0xbfe8e42cd2852e0a, 0xbfe41c3a4bdbaa26, // -0.77785, -0.62845 + 0xbfe8dc45331698cc, 0xbfe425ff178e6bb1, // -0.77689, -0.62964 + 0xbfe8d459be34bdfa, 0xbfe42fc0c7d3adbb, // -0.77592, -0.63083 + 0xbfe8cc6a75184655, 0xbfe4397f5b2a4380, // -0.77495, -0.63202 + 0xbfe8c47758fa71cb, 0xbfe4433ad0117b1d, // -0.77398, -0.63321 + 0xbfe8bc806b151741, 0xbfe44cf325091dd6, // -0.77301, -0.63439 + 0xbfe8b485aca2a468, 0xbfe456a858917046, // -0.77204, -0.63558 + 0xbfe8ac871ede1d88, 0xbfe4605a692b32a2, // -0.77106, -0.63676 + 0xbfe8a484c3031d50, 0xbfe46a095557a0f1, // -0.77008, -0.63794 + 0xbfe89c7e9a4dd4ab, 0xbfe473b51b987347, // -0.7691, -0.63912 + 0xbfe89474a5fb0a84, 0xbfe47d5dba6fde01, // -0.76812, -0.6403 + 0xbfe88c66e7481ba1, 0xbfe48703306091fe, // -0.76714, -0.64148 + 0xbfe884555f72fa6b, 0xbfe490a57bedbcdf, // -0.76615, -0.64266 + 0xbfe87c400fba2ebf, 0xbfe49a449b9b0938, // -0.76517, -0.64383 + 0xbfe87426f95cd5bd, 0xbfe4a3e08dec9ed6, // -0.76418, -0.645 + 0xbfe86c0a1d9aa195, 0xbfe4ad79516722f0, // -0.76319, -0.64618 + 0xbfe863e97db3d95a, 0xbfe4b70ee48fb869, // -0.7622, -0.64735 + 0xbfe85bc51ae958cc, 0xbfe4c0a145ec0004, // -0.7612, -0.64851 + 0xbfe8539cf67c9029, 0xbfe4ca30740218a3, // -0.76021, -0.64968 + 0xbfe84b7111af83f9, 0xbfe4d3bc6d589f80, // -0.75921, -0.65085 + 0xbfe843416dc4cce2, 0xbfe4dd453076b064, // -0.75821, -0.65201 + 0xbfe83b0e0bff976e, 0xbfe4e6cabbe3e5e9, // -0.75721, -0.65317 + 0xbfe832d6eda3a3e0, 0xbfe4f04d0e2859aa, // -0.75621, -0.65433 + 0xbfe82a9c13f545ff, 0xbfe4f9cc25cca486, // -0.7552, -0.65549 + 0xbfe8225d803964e5, 0xbfe503480159ded2, // -0.75419, -0.65665 + 0xbfe81a1b33b57acc, 0xbfe50cc09f59a09b, // -0.75319, -0.65781 + 0xbfe811d52faf94dc, 0xbfe51635fe5601d7, // -0.75218, -0.65896 + 0xbfe8098b756e52fa, 0xbfe51fa81cd99aa6, // -0.75117, -0.66011 + 0xbfe8013e0638e795, 0xbfe52916f96f8388, // -0.75015, -0.66127 + 0xbfe7f8ece3571771, 0xbfe5328292a35596, // -0.74914, -0.66242 + 0xbfe7f0980e113978, 0xbfe53beae7012abe, // -0.74812, -0.66356 + 0xbfe7e83f87b03686, 0xbfe5454ff5159dfb, // -0.7471, -0.66471 + 0xbfe7dfe3517d8937, 0xbfe54eb1bb6dcb8f, // -0.74608, -0.66586 + 0xbfe7d7836cc33db2, 0xbfe5581038975137, // -0.74506, -0.667 + 0xbfe7cf1fdacbf179, 0xbfe5616b6b204e6e, // -0.74403, -0.66814 + 0xbfe7c6b89ce2d333, 0xbfe56ac35197649e, // -0.74301, -0.66928 + 0xbfe7be4db453a27c, 0xbfe57417ea8bb75c, // -0.74198, -0.67042 + 0xbfe7b5df226aafb0, 0xbfe57d69348cec9f, // -0.74095, -0.67156 + 0xbfe7ad6ce874dbb6, 0xbfe586b72e2b2cfd, // -0.73992, -0.67269 + 0xbfe7a4f707bf97d2, 0xbfe59001d5f723df, // -0.73889, -0.67383 + 0xbfe79c7d8198e56e, 0xbfe599492a81ffbc, // -0.73785, -0.67496 + 0xbfe79400574f55e4, 0xbfe5a28d2a5d7250, // -0.73682, -0.67609 + 0xbfe78b7f8a320a52, 0xbfe5abcdd41bb0d8, // -0.73578, -0.67722 + 0xbfe782fb1b90b35b, 0xbfe5b50b264f7448, // -0.73474, -0.67835 + 0xbfe77a730cbb9100, 0xbfe5be451f8bf980, // -0.7337, -0.67948 + 0xbfe771e75f037261, 0xbfe5c77bbe65018c, // -0.73265, -0.6806 + 0xbfe7695813b9b594, 0xbfe5d0af016ed1d4, // -0.73161, -0.68172 + 0xbfe760c52c304764, 0xbfe5d9dee73e345c, // -0.73056, -0.68285 + 0xbfe7582ea9b9a329, 0xbfe5e30b6e6877f3, // -0.72951, -0.68397 + 0xbfe74f948da8d28d, 0xbfe5ec3495837074, // -0.72846, -0.68508 + 0xbfe746f6d9516d59, 0xbfe5f55a5b2576f8, // -0.72741, -0.6862 + 0xbfe73e558e079942, 0xbfe5fe7cbde56a0f, // -0.72636, -0.68732 + 0xbfe735b0ad2009b2, 0xbfe6079bbc5aadfa, // -0.7253, -0.68843 + 0xbfe72d0837efff97, 0xbfe610b7551d2cde, // -0.72425, -0.68954 + 0xbfe7245c2fcd492a, 0xbfe619cf86c55702, // -0.72319, -0.69065 + 0xbfe71bac960e41bf, 0xbfe622e44fec22ff, // -0.72213, -0.69176 + 0xbfe712f96c09d18d, 0xbfe62bf5af2b0dfd, // -0.72107, -0.69287 + 0xbfe70a42b3176d7a, 0xbfe63503a31c1be8, // -0.72, -0.69397 + 0xbfe701886c8f16e6, 0xbfe63e0e2a59d7aa, // -0.71894, -0.69508 + 0xbfe6f8ca99c95b75, 0xbfe64715437f535b, // -0.71787, -0.69618 + 0xbfe6f0093c1f54de, 0xbfe65018ed28287f, // -0.7168, -0.69728 + 0xbfe6e74454eaa8ae, 0xbfe6591925f0783e, // -0.71573, -0.69838 + 0xbfe6de7be585881d, 0xbfe66215ec74eb91, // -0.71466, -0.69947 + 0xbfe6d5afef4aafcc, 0xbfe66b0f3f52b386, // -0.71358, -0.70057 + 0xbfe6cce07395679f, 0xbfe674051d27896c, // -0.71251, -0.70166 + 0xbfe6c40d73c18275, 0xbfe67cf78491af10, // -0.71143, -0.70275 + 0xbfe6bb36f12b5e06, 0xbfe685e6742feeef, // -0.71035, -0.70385 + 0xbfe6b25ced2fe29c, 0xbfe68ed1eaa19c71, // -0.70927, -0.70493 + 0xbfe6a97f692c82ea, 0xbfe697b9e686941c, // -0.70819, -0.70602 + 0xbfe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // -0.70711, -0.70711 + 0xbfe697b9e686941c, 0xbfe6a97f692c82ea, // -0.70602, -0.70819 + 0xbfe68ed1eaa19c71, 0xbfe6b25ced2fe29c, // -0.70493, -0.70927 + 0xbfe685e6742feeef, 0xbfe6bb36f12b5e06, // -0.70385, -0.71035 + 0xbfe67cf78491af10, 0xbfe6c40d73c18275, // -0.70275, -0.71143 + 0xbfe674051d27896c, 0xbfe6cce07395679f, // -0.70166, -0.71251 + 0xbfe66b0f3f52b386, 0xbfe6d5afef4aafcc, // -0.70057, -0.71358 + 0xbfe66215ec74eb91, 0xbfe6de7be585881d, // -0.69947, -0.71466 + 0xbfe6591925f0783e, 0xbfe6e74454eaa8ae, // -0.69838, -0.71573 + 0xbfe65018ed28287f, 0xbfe6f0093c1f54de, // -0.69728, -0.7168 + 0xbfe64715437f535b, 0xbfe6f8ca99c95b75, // -0.69618, -0.71787 + 0xbfe63e0e2a59d7aa, 0xbfe701886c8f16e6, // -0.69508, -0.71894 + 0xbfe63503a31c1be8, 0xbfe70a42b3176d7a, // -0.69397, -0.72 + 0xbfe62bf5af2b0dfd, 0xbfe712f96c09d18d, // -0.69287, -0.72107 + 0xbfe622e44fec22ff, 0xbfe71bac960e41bf, // -0.69176, -0.72213 + 0xbfe619cf86c55702, 0xbfe7245c2fcd492a, // -0.69065, -0.72319 + 0xbfe610b7551d2cde, 0xbfe72d0837efff97, // -0.68954, -0.72425 + 0xbfe6079bbc5aadfa, 0xbfe735b0ad2009b2, // -0.68843, -0.7253 + 0xbfe5fe7cbde56a0f, 0xbfe73e558e079942, // -0.68732, -0.72636 + 0xbfe5f55a5b2576f8, 0xbfe746f6d9516d59, // -0.6862, -0.72741 + 0xbfe5ec3495837074, 0xbfe74f948da8d28d, // -0.68508, -0.72846 + 0xbfe5e30b6e6877f3, 0xbfe7582ea9b9a329, // -0.68397, -0.72951 + 0xbfe5d9dee73e345c, 0xbfe760c52c304764, // -0.68285, -0.73056 + 0xbfe5d0af016ed1d4, 0xbfe7695813b9b594, // -0.68172, -0.73161 + 0xbfe5c77bbe65018c, 0xbfe771e75f037261, // -0.6806, -0.73265 + 0xbfe5be451f8bf980, 0xbfe77a730cbb9100, // -0.67948, -0.7337 + 0xbfe5b50b264f7448, 0xbfe782fb1b90b35b, // -0.67835, -0.73474 + 0xbfe5abcdd41bb0d8, 0xbfe78b7f8a320a52, // -0.67722, -0.73578 + 0xbfe5a28d2a5d7250, 0xbfe79400574f55e4, // -0.67609, -0.73682 + 0xbfe599492a81ffbc, 0xbfe79c7d8198e56e, // -0.67496, -0.73785 + 0xbfe59001d5f723df, 0xbfe7a4f707bf97d2, // -0.67383, -0.73889 + 0xbfe586b72e2b2cfd, 0xbfe7ad6ce874dbb6, // -0.67269, -0.73992 + 0xbfe57d69348cec9f, 0xbfe7b5df226aafb0, // -0.67156, -0.74095 + 0xbfe57417ea8bb75c, 0xbfe7be4db453a27c, // -0.67042, -0.74198 + 0xbfe56ac35197649e, 0xbfe7c6b89ce2d333, // -0.66928, -0.74301 + 0xbfe5616b6b204e6e, 0xbfe7cf1fdacbf179, // -0.66814, -0.74403 + 0xbfe5581038975137, 0xbfe7d7836cc33db2, // -0.667, -0.74506 + 0xbfe54eb1bb6dcb8f, 0xbfe7dfe3517d8937, // -0.66586, -0.74608 + 0xbfe5454ff5159dfb, 0xbfe7e83f87b03686, // -0.66471, -0.7471 + 0xbfe53beae7012abe, 0xbfe7f0980e113978, // -0.66356, -0.74812 + 0xbfe5328292a35596, 0xbfe7f8ece3571771, // -0.66242, -0.74914 + 0xbfe52916f96f8388, 0xbfe8013e0638e795, // -0.66127, -0.75015 + 0xbfe51fa81cd99aa6, 0xbfe8098b756e52fa, // -0.66011, -0.75117 + 0xbfe51635fe5601d7, 0xbfe811d52faf94dc, // -0.65896, -0.75218 + 0xbfe50cc09f59a09b, 0xbfe81a1b33b57acc, // -0.65781, -0.75319 + 0xbfe503480159ded2, 0xbfe8225d803964e5, // -0.65665, -0.75419 + 0xbfe4f9cc25cca486, 0xbfe82a9c13f545ff, // -0.65549, -0.7552 + 0xbfe4f04d0e2859aa, 0xbfe832d6eda3a3e0, // -0.65433, -0.75621 + 0xbfe4e6cabbe3e5e9, 0xbfe83b0e0bff976e, // -0.65317, -0.75721 + 0xbfe4dd453076b064, 0xbfe843416dc4cce2, // -0.65201, -0.75821 + 0xbfe4d3bc6d589f80, 0xbfe84b7111af83f9, // -0.65085, -0.75921 + 0xbfe4ca30740218a3, 0xbfe8539cf67c9029, // -0.64968, -0.76021 + 0xbfe4c0a145ec0004, 0xbfe85bc51ae958cc, // -0.64851, -0.7612 + 0xbfe4b70ee48fb869, 0xbfe863e97db3d95a, // -0.64735, -0.7622 + 0xbfe4ad79516722f0, 0xbfe86c0a1d9aa195, // -0.64618, -0.76319 + 0xbfe4a3e08dec9ed6, 0xbfe87426f95cd5bd, // -0.645, -0.76418 + 0xbfe49a449b9b0938, 0xbfe87c400fba2ebf, // -0.64383, -0.76517 + 0xbfe490a57bedbcdf, 0xbfe884555f72fa6b, // -0.64266, -0.76615 + 0xbfe48703306091fe, 0xbfe88c66e7481ba1, // -0.64148, -0.76714 + 0xbfe47d5dba6fde01, 0xbfe89474a5fb0a84, // -0.6403, -0.76812 + 0xbfe473b51b987347, 0xbfe89c7e9a4dd4ab, // -0.63912, -0.7691 + 0xbfe46a095557a0f1, 0xbfe8a484c3031d50, // -0.63794, -0.77008 + 0xbfe4605a692b32a2, 0xbfe8ac871ede1d88, // -0.63676, -0.77106 + 0xbfe456a858917046, 0xbfe8b485aca2a468, // -0.63558, -0.77204 + 0xbfe44cf325091dd6, 0xbfe8bc806b151741, // -0.63439, -0.77301 + 0xbfe4433ad0117b1d, 0xbfe8c47758fa71cb, // -0.63321, -0.77398 + 0xbfe4397f5b2a4380, 0xbfe8cc6a75184655, // -0.63202, -0.77495 + 0xbfe42fc0c7d3adbb, 0xbfe8d459be34bdfa, // -0.63083, -0.77592 + 0xbfe425ff178e6bb1, 0xbfe8dc45331698cc, // -0.62964, -0.77689 + 0xbfe41c3a4bdbaa26, 0xbfe8e42cd2852e0a, // -0.62845, -0.77785 + 0xbfe41272663d108c, 0xbfe8ec109b486c49, // -0.62725, -0.77882 + 0xbfe408a76834c0c0, 0xbfe8f3f08c28d9ac, // -0.62606, -0.77978 + 0xbfe3fed9534556d4, 0xbfe8fbcca3ef940d, // -0.62486, -0.78074 + 0xbfe3f50828f1e8d2, 0xbfe903a4e1665133, // -0.62366, -0.78169 + 0xbfe3eb33eabe0680, 0xbfe90b7943575efe, // -0.62246, -0.78265 + 0xbfe3e15c9a2db922, 0xbfe91349c88da398, // -0.62126, -0.7836 + 0xbfe3d78238c58343, 0xbfe91b166fd49da2, // -0.62006, -0.78456 + 0xbfe3cda4c80a6076, 0xbfe922df37f8646a, // -0.61885, -0.78551 + 0xbfe3c3c44981c517, 0xbfe92aa41fc5a815, // -0.61765, -0.78646 + 0xbfe3b9e0beb19e18, 0xbfe932652609b1cf, // -0.61644, -0.7874 + 0xbfe3affa292050b9, 0xbfe93a22499263fc, // -0.61523, -0.78835 + 0xbfe3a6108a54ba58, 0xbfe941db892e3a65, // -0.61402, -0.78929 + 0xbfe39c23e3d63029, 0xbfe94990e3ac4a6c, // -0.61281, -0.79023 + 0xbfe39234372c7f04, 0xbfe9514257dc4335, // -0.6116, -0.79117 + 0xbfe3884185dfeb22, 0xbfe958efe48e6dd7, // -0.61038, -0.79211 + 0xbfe37e4bd1792fe2, 0xbfe960998893ad8c, // -0.60917, -0.79304 + 0xbfe374531b817f8d, 0xbfe9683f42bd7fe1, // -0.60795, -0.79398 + 0xbfe36a576582831b, 0xbfe96fe111ddfce0, // -0.60673, -0.79491 + 0xbfe36058b10659f3, 0xbfe9777ef4c7d742, // -0.60551, -0.79584 + 0xbfe35656ff9799ae, 0xbfe97f18ea4e5c9e, // -0.60429, -0.79676 + 0xbfe34c5252c14de1, 0xbfe986aef1457594, // -0.60307, -0.79769 + 0xbfe3424aac0ef7d6, 0xbfe98e410881a600, // -0.60184, -0.79861 + 0xbfe338400d0c8e57, 0xbfe995cf2ed80d22, // -0.60062, -0.79954 + 0xbfe32e3277467d6b, 0xbfe99d59631e65d5, // -0.59939, -0.80046 + 0xbfe32421ec49a620, 0xbfe9a4dfa42b06b2, // -0.59816, -0.80138 + 0xbfe31a0e6da35e44, 0xbfe9ac61f0d4e247, // -0.59693, -0.80229 + 0xbfe30ff7fce17035, 0xbfe9b3e047f38741, // -0.5957, -0.80321 + 0xbfe305de9b921a94, 0xbfe9bb5aa85f2098, // -0.59447, -0.80412 + 0xbfe2fbc24b441015, 0xbfe9c2d110f075c3, // -0.59323, -0.80503 + 0xbfe2f1a30d86773a, 0xbfe9ca438080eadb, // -0.592, -0.80594 + 0xbfe2e780e3e8ea16, 0xbfe9d1b1f5ea80d6, // -0.59076, -0.80685 + 0xbfe2dd5bcffb7616, 0xbfe9d91c7007d5a6, // -0.58952, -0.80775 + 0xbfe2d333d34e9bb7, 0xbfe9e082edb42472, // -0.58828, -0.80866 + 0xbfe2c908ef734e57, 0xbfe9e7e56dcb45bd, // -0.58704, -0.80956 + 0xbfe2bedb25faf3ea, 0xbfe9ef43ef29af94, // -0.5858, -0.81046 + 0xbfe2b4aa787764c4, 0xbfe9f69e70ac75bc, // -0.58455, -0.81135 + 0xbfe2aa76e87aeb58, 0xbfe9fdf4f13149de, // -0.58331, -0.81225 + 0xbfe2a040779843fb, 0xbfea05476f967bb5, // -0.58206, -0.81314 + 0xbfe2960727629ca8, 0xbfea0c95eabaf937, // -0.58081, -0.81404 + 0xbfe28bcaf96d94ba, 0xbfea13e0617e4ec7, // -0.57956, -0.81493 + 0xbfe2818bef4d3cba, 0xbfea1b26d2c0a75e, // -0.57831, -0.81581 + 0xbfe2774a0a961612, 0xbfea22693d62ccb9, // -0.57706, -0.8167 + 0xbfe26d054cdd12df, 0xbfea29a7a0462782, // -0.57581, -0.81758 + 0xbfe262bdb7b795a2, 0xbfea30e1fa4cbf81, // -0.57455, -0.81847 + 0xbfe258734cbb7110, 0xbfea38184a593bc6, // -0.5733, -0.81935 + 0xbfe24e260d7ee7c9, 0xbfea3f4a8f4ee2d2, // -0.57204, -0.82023 + 0xbfe243d5fb98ac1f, 0xbfea4678c8119ac8, // -0.57078, -0.8211 + 0xbfe23983189fdfd5, 0xbfea4da2f385e997, // -0.56952, -0.82198 + 0xbfe22f2d662c13e1, 0xbfea54c91090f524, // -0.56826, -0.82285 + 0xbfe224d4e5d5482e, 0xbfea5beb1e188375, // -0.567, -0.82372 + 0xbfe21a799933eb58, 0xbfea63091b02fae2, // -0.56573, -0.82459 + 0xbfe2101b81e0da78, 0xbfea6a230637623b, // -0.56447, -0.82546 + 0xbfe205baa17560d6, 0xbfea7138de9d60f5, // -0.5632, -0.82632 + 0xbfe1fb56f98b37b8, 0xbfea784aa31d3f55, // -0.56193, -0.82718 + 0xbfe1f0f08bbc861b, 0xbfea7f58529fe69d, // -0.56066, -0.82805 + 0xbfe1e68759a3e074, 0xbfea8661ec0ee133, // -0.55939, -0.8289 + 0xbfe1dc1b64dc4872, 0xbfea8d676e545ad2, // -0.55812, -0.82976 + 0xbfe1d1acaf012cc2, 0xbfea9468d85b20ae, // -0.55685, -0.83062 + 0xbfe1c73b39ae68c8, 0xbfea9b66290ea1a3, // -0.55557, -0.83147 + 0xbfe1bcc706804467, 0xbfeaa25f5f5aee60, // -0.55429, -0.83232 + 0xbfe1b250171373be, 0xbfeaa9547a2cb98e, // -0.55302, -0.83317 + 0xbfe1a7d66d0516e6, 0xbfeab045787157ff, // -0.55174, -0.83402 + 0xbfe19d5a09f2b9b8, 0xbfeab7325916c0d4, // -0.55046, -0.83486 + 0xbfe192daef7a5386, 0xbfeabe1b1b0b8dac, // -0.54918, -0.83571 + 0xbfe188591f3a46e5, 0xbfeac4ffbd3efac8, // -0.54789, -0.83655 + 0xbfe17dd49ad16161, 0xbfeacbe03ea0e73b, // -0.54661, -0.83739 + 0xbfe1734d63dedb49, 0xbfead2bc9e21d511, // -0.54532, -0.83822 + 0xbfe168c37c025764, 0xbfead994dab2e979, // -0.54404, -0.83906 + 0xbfe15e36e4dbe2bc, 0xbfeae068f345ecef, // -0.54275, -0.83989 + 0xbfe153a7a00bf453, 0xbfeae738e6cd4b67, // -0.54146, -0.84073 + 0xbfe14915af336ceb, 0xbfeaee04b43c1474, // -0.54017, -0.84155 + 0xbfe13e8113f396c1, 0xbfeaf4cc5a85fb73, // -0.53888, -0.84238 + 0xbfe133e9cfee254e, 0xbfeafb8fd89f57b6, // -0.53759, -0.84321 + 0xbfe1294fe4c5350a, 0xbfeb024f2d7d24a9, // -0.53629, -0.84403 + 0xbfe11eb3541b4b22, 0xbfeb090a58150200, // -0.535, -0.84485 + 0xbfe114141f935545, 0xbfeb0fc1575d33db, // -0.5337, -0.84567 + 0xbfe1097248d0a956, 0xbfeb16742a4ca2f5, // -0.5324, -0.84649 + 0xbfe0fecdd1770537, 0xbfeb1d22cfdadcc6, // -0.5311, -0.84731 + 0xbfe0f426bb2a8e7d, 0xbfeb23cd470013b4, // -0.5298, -0.84812 + 0xbfe0e97d078fd23b, 0xbfeb2a738eb51f33, // -0.5285, -0.84893 + 0xbfe0ded0b84bc4b5, 0xbfeb3115a5f37bf4, // -0.5272, -0.84974 + 0xbfe0d421cf03c12b, 0xbfeb37b38bb54c09, // -0.5259, -0.85055 + 0xbfe0c9704d5d898f, 0xbfeb3e4d3ef55712, // -0.52459, -0.85136 + 0xbfe0bebc34ff4646, 0xbfeb44e2beaf0a61, // -0.52328, -0.85216 + 0xbfe0b405878f85ec, 0xbfeb4b7409de7925, // -0.52198, -0.85296 + 0xbfe0a94c46b53d0b, 0xbfeb52011f805c92, // -0.52067, -0.85376 + 0xbfe09e907417c5e1, 0xbfeb5889fe921405, // -0.51936, -0.85456 + 0xbfe093d2115ee018, 0xbfeb5f0ea611a532, // -0.51804, -0.85535 + 0xbfe089112032b08c, 0xbfeb658f14fdbc47, // -0.51673, -0.85615 + 0xbfe07e4da23bc102, 0xbfeb6c0b4a55ac17, // -0.51542, -0.85694 + 0xbfe073879922ffed, 0xbfeb728345196e3e, // -0.5141, -0.85773 + 0xbfe068bf0691c028, 0xbfeb78f70449a34b, // -0.51279, -0.85852 + 0xbfe05df3ec31b8b6, 0xbfeb7f6686e792ea, // -0.51147, -0.8593 + 0xbfe053264bad0483, 0xbfeb85d1cbf52c02, // -0.51015, -0.86009 + 0xbfe0485626ae221a, 0xbfeb8c38d27504e9, // -0.50883, -0.86087 + 0xbfe03d837edff370, 0xbfeb929b996a5b7f, // -0.50751, -0.86165 + 0xbfe032ae55edbd95, 0xbfeb98fa1fd9155e, // -0.50619, -0.86242 + 0xbfe027d6ad83287e, 0xbfeb9f5464c5bffc, // -0.50486, -0.8632 + 0xbfe01cfc874c3eb7, 0xbfeba5aa673590d2, // -0.50354, -0.86397 + 0xbfe0121fe4f56d2c, 0xbfebabfc262e6586, // -0.50221, -0.86474 + 0xbfe00740c82b82e0, 0xbfebb249a0b6c40d, // -0.50089, -0.86551 + 0xbfdff8be6537615e, 0xbfebb892d5d5dad5, // -0.49956, -0.86628 + 0xbfdfe2f64be7120f, 0xbfebbed7c49380ea, // -0.49823, -0.86705 + 0xbfdfcd2947c1ff57, 0xbfebc5186bf8361d, // -0.4969, -0.86781 + 0xbfdfb7575c24d2de, 0xbfebcb54cb0d2327, // -0.49557, -0.86857 + 0xbfdfa1808c6cf7e0, 0xbfebd18ce0dc19d6, // -0.49423, -0.86933 + 0xbfdf8ba4dbf89aba, 0xbfebd7c0ac6f952a, // -0.4929, -0.87009 + 0xbfdf75c44e26a852, 0xbfebddf02cd2b983, // -0.49156, -0.87084 + 0xbfdf5fdee656cda3, 0xbfebe41b611154c1, // -0.49023, -0.8716 + 0xbfdf49f4a7e97729, 0xbfebea424837de6d, // -0.48889, -0.87235 + 0xbfdf3405963fd068, 0xbfebf064e15377dd, // -0.48755, -0.87309 + 0xbfdf1e11b4bbc35c, 0xbfebf6832b71ec5b, // -0.48621, -0.87384 + 0xbfdf081906bff7fd, 0xbfebfc9d25a1b147, // -0.48487, -0.87459 + 0xbfdef21b8fafd3b5, 0xbfec02b2cef1e641, // -0.48353, -0.87533 + 0xbfdedc1952ef78d5, 0xbfec08c426725549, // -0.48218, -0.87607 + 0xbfdec61253e3c61b, 0xbfec0ed12b3372e9, // -0.48084, -0.87681 + 0xbfdeb00695f25620, 0xbfec14d9dc465e58, // -0.47949, -0.87755 + 0xbfde99f61c817eda, 0xbfec1ade38bce19b, // -0.47815, -0.87828 + 0xbfde83e0eaf85113, 0xbfec20de3fa971b0, // -0.4768, -0.87901 + 0xbfde6dc704be97e2, 0xbfec26d9f01f2eaf, // -0.47545, -0.87974 + 0xbfde57a86d3cd824, 0xbfec2cd14931e3f1, // -0.4741, -0.88047 + 0xbfde418527dc4ffa, 0xbfec32c449f60831, // -0.47275, -0.8812 + 0xbfde2b5d3806f63b, 0xbfec38b2f180bdb1, // -0.4714, -0.88192 + 0xbfde1530a12779f4, 0xbfec3e9d3ee7d262, // -0.47004, -0.88264 + 0xbfddfeff66a941de, 0xbfec44833141c004, // -0.46869, -0.88336 + 0xbfdde8c98bf86bd6, 0xbfec4a64c7a5ac4c, // -0.46733, -0.88408 + 0xbfddd28f1481cc58, 0xbfec5042012b6907, // -0.46598, -0.8848 + 0xbfddbc5003b2edf8, 0xbfec561adceb743e, // -0.46462, -0.88551 + 0xbfdda60c5cfa10d8, 0xbfec5bef59fef85a, // -0.46326, -0.88622 + 0xbfdd8fc423c62a25, 0xbfec61bf777fcc48, // -0.4619, -0.88693 + 0xbfdd79775b86e389, 0xbfec678b3488739b, // -0.46054, -0.88764 + 0xbfdd632607ac9aa9, 0xbfec6d5290341eb2, // -0.45918, -0.88835 + 0xbfdd4cd02ba8609c, 0xbfec7315899eaad7, // -0.45781, -0.88905 + 0xbfdd3675caebf962, 0xbfec78d41fe4a267, // -0.45645, -0.88975 + 0xbfdd2016e8e9db5b, 0xbfec7e8e52233cf3, // -0.45508, -0.89045 + 0xbfdd09b389152ec1, 0xbfec84441f785f61, // -0.45372, -0.89115 + 0xbfdcf34baee1cd21, 0xbfec89f587029c13, // -0.45235, -0.89184 + 0xbfdcdcdf5dc440ce, 0xbfec8fa287e13305, // -0.45098, -0.89253 + 0xbfdcc66e9931c45d, 0xbfec954b213411f5, // -0.44961, -0.89322 + 0xbfdcaff964a0421d, 0xbfec9aef521bd480, // -0.44824, -0.89391 + 0xbfdc997fc3865388, 0xbfeca08f19b9c449, // -0.44687, -0.8946 + 0xbfdc8301b95b40c2, 0xbfeca62a772fd919, // -0.4455, -0.89528 + 0xbfdc6c7f4997000a, 0xbfecabc169a0b901, // -0.44412, -0.89597 + 0xbfdc55f877b23537, 0xbfecb153f02fb87d, // -0.44275, -0.89665 + 0xbfdc3f6d47263129, 0xbfecb6e20a00da99, // -0.44137, -0.89732 + 0xbfdc28ddbb6cf145, 0xbfecbc6bb638d10b, // -0.43999, -0.898 + 0xbfdc1249d8011ee7, 0xbfecc1f0f3fcfc5c, // -0.43862, -0.89867 + 0xbfdbfbb1a05e0edc, 0xbfecc771c2736c09, // -0.43724, -0.89935 + 0xbfdbe51517ffc0d9, 0xbfecccee20c2de9f, // -0.43586, -0.90002 + 0xbfdbce744262deee, 0xbfecd2660e12c1e6, // -0.43448, -0.90068 + 0xbfdbb7cf2304bd01, 0xbfecd7d9898b32f6, // -0.43309, -0.90135 + 0xbfdba125bd63583e, 0xbfecdd489254fe65, // -0.43171, -0.90201 + 0xbfdb8a7814fd5693, 0xbfece2b32799a060, // -0.43033, -0.90267 + 0xbfdb73c62d520624, 0xbfece819488344ce, // -0.42894, -0.90333 + 0xbfdb5d1009e15cc0, 0xbfeced7af43cc773, // -0.42756, -0.90399 + 0xbfdb4655ae2bf757, 0xbfecf2d829f1b40e, // -0.42617, -0.90464 + 0xbfdb2f971db31972, 0xbfecf830e8ce467b, // -0.42478, -0.9053 + 0xbfdb18d45bf8aca6, 0xbfecfd852fff6ad4, // -0.42339, -0.90595 + 0xbfdb020d6c7f4009, 0xbfed02d4feb2bd92, // -0.422, -0.9066 + 0xbfdaeb4252ca07ab, 0xbfed082054168bac, // -0.42061, -0.90724 + 0xbfdad473125cdc08, 0xbfed0d672f59d2b9, // -0.41922, -0.90789 + 0xbfdabd9faebc3980, 0xbfed12a98fac410c, // -0.41782, -0.90853 + 0xbfdaa6c82b6d3fc9, 0xbfed17e7743e35dc, // -0.41643, -0.90917 + 0xbfda8fec8bf5b166, 0xbfed1d20dc40c15c, // -0.41503, -0.90981 + 0xbfda790cd3dbf31a, 0xbfed2255c6e5a4e1, // -0.41364, -0.91044 + 0xbfda622906a70b63, 0xbfed2786335f52fc, // -0.41224, -0.91107 + 0xbfda4b4127dea1e4, 0xbfed2cb220e0ef9f, // -0.41084, -0.91171 + 0xbfda34553b0afee5, 0xbfed31d98e9e503a, // -0.40944, -0.91234 + 0xbfda1d6543b50ac0, 0xbfed36fc7bcbfbdc, // -0.40804, -0.91296 + 0xbfda067145664d57, 0xbfed3c1ae79f2b4e, // -0.40664, -0.91359 + 0xbfd9ef7943a8ed8a, 0xbfed4134d14dc93a, // -0.40524, -0.91421 + 0xbfd9d87d4207b0ab, 0xbfed464a380e7242, // -0.40384, -0.91483 + 0xbfd9c17d440df9f2, 0xbfed4b5b1b187524, // -0.40243, -0.91545 + 0xbfd9aa794d47c9ee, 0xbfed506779a3d2d9, // -0.40103, -0.91606 + 0xbfd993716141bdfe, 0xbfed556f52e93eb1, // -0.39962, -0.91668 + 0xbfd97c6583890fc2, 0xbfed5a72a6221e73, // -0.39822, -0.91729 + 0xbfd96555b7ab948f, 0xbfed5f7172888a7f, // -0.39681, -0.9179 + 0xbfd94e420137bce3, 0xbfed646bb7574de5, // -0.3954, -0.91851 + 0xbfd9372a63bc93d7, 0xbfed696173c9e68b, // -0.39399, -0.91911 + 0xbfd9200ee2c9be97, 0xbfed6e52a71c8547, // -0.39258, -0.91972 + 0xbfd908ef81ef7bd1, 0xbfed733f508c0dff, // -0.39117, -0.92032 + 0xbfd8f1cc44bea329, 0xbfed78276f5617c6, // -0.38976, -0.92092 + 0xbfd8daa52ec8a4af, 0xbfed7d0b02b8ecf9, // -0.38835, -0.92151 + 0xbfd8c37a439f884f, 0xbfed81ea09f38b63, // -0.38693, -0.92211 + 0xbfd8ac4b86d5ed44, 0xbfed86c48445a450, // -0.38552, -0.9227 + 0xbfd89518fbff098e, 0xbfed8b9a70ef9cb4, // -0.3841, -0.92329 + 0xbfd87de2a6aea963, 0xbfed906bcf328d46, // -0.38268, -0.92388 + 0xbfd866a88a792ea0, 0xbfed95389e50429b, // -0.38127, -0.92447 + 0xbfd84f6aaaf3903f, 0xbfed9a00dd8b3d46, // -0.37985, -0.92505 + 0xbfd838290bb359c8, 0xbfed9ec48c26b1f3, // -0.37843, -0.92563 + 0xbfd820e3b04eaac4, 0xbfeda383a9668988, // -0.37701, -0.92621 + 0xbfd8099a9c5c362d, 0xbfeda83e348f613b, // -0.37559, -0.92679 + 0xbfd7f24dd37341e3, 0xbfedacf42ce68ab9, // -0.37416, -0.92736 + 0xbfd7dafd592ba621, 0xbfedb1a591b20c38, // -0.37274, -0.92794 + 0xbfd7c3a9311dcce7, 0xbfedb6526238a09b, // -0.37132, -0.92851 + 0xbfd7ac515ee2b172, 0xbfedbafa9dc1b78d, // -0.36989, -0.92907 + 0xbfd794f5e613dfae, 0xbfedbf9e4395759a, // -0.36847, -0.92964 + 0xbfd77d96ca4b73a6, 0xbfedc43d52fcb453, // -0.36704, -0.93021 + 0xbfd766340f2418f6, 0xbfedc8d7cb410260, // -0.36561, -0.93077 + 0xbfd74ecdb8390a3e, 0xbfedcd6dabaca3a5, // -0.36418, -0.93133 + 0xbfd73763c9261092, 0xbfedd1fef38a915a, // -0.36276, -0.93188 + 0xbfd71ff6458782ec, 0xbfedd68ba2267a25, // -0.36133, -0.93244 + 0xbfd7088530fa459e, 0xbfeddb13b6ccc23d, // -0.3599, -0.93299 + 0xbfd6f1108f1bc9c5, 0xbfeddf9730ca837b, // -0.35846, -0.93354 + 0xbfd6d998638a0cb5, 0xbfede4160f6d8d81, // -0.35703, -0.93409 + 0xbfd6c21cb1e39771, 0xbfede890520465ce, // -0.3556, -0.93464 + 0xbfd6aa9d7dc77e16, 0xbfeded05f7de47da, // -0.35416, -0.93518 + 0xbfd6931acad55f51, 0xbfedf177004b2534, // -0.35273, -0.93573 + 0xbfd67b949cad63ca, 0xbfedf5e36a9ba59c, // -0.35129, -0.93627 + 0xbfd6640af6f03d9e, 0xbfedfa4b3621271d, // -0.34986, -0.9368 + 0xbfd64c7ddd3f27c6, 0xbfedfeae622dbe2b, // -0.34842, -0.93734 + 0xbfd634ed533be58e, 0xbfee030cee1435b8, // -0.34698, -0.93787 + 0xbfd61d595c88c203, 0xbfee0766d9280f54, // -0.34554, -0.9384 + 0xbfd605c1fcc88f63, 0xbfee0bbc22bd8349, // -0.3441, -0.93893 + 0xbfd5ee27379ea693, 0xbfee100cca2980ac, // -0.34266, -0.93946 + 0xbfd5d68910aee686, 0xbfee1458cec1ad83, // -0.34122, -0.93998 + 0xbfd5bee78b9db3b6, 0xbfee18a02fdc66d9, // -0.33978, -0.94051 + 0xbfd5a742ac0ff78d, 0xbfee1ce2ecd0c0d8, // -0.33833, -0.94103 + 0xbfd58f9a75ab1fdd, 0xbfee212104f686e5, // -0.33689, -0.94154 + 0xbfd577eeec151e47, 0xbfee255a77a63bb8, // -0.33545, -0.94206 + 0xbfd5604012f467b4, 0xbfee298f4439197a, // -0.334, -0.94257 + 0xbfd5488dedeff3be, 0xbfee2dbf6a0911d9, // -0.33255, -0.94308 + 0xbfd530d880af3c24, 0xbfee31eae870ce25, // -0.33111, -0.94359 + 0xbfd5191fceda3c35, 0xbfee3611becbaf69, // -0.32966, -0.9441 + 0xbfd50163dc197047, 0xbfee3a33ec75ce85, // -0.32821, -0.9446 + 0xbfd4e9a4ac15d520, 0xbfee3e5170cbfc46, // -0.32676, -0.94511 + 0xbfd4d1e24278e76a, 0xbfee426a4b2bc17e, // -0.32531, -0.94561 + 0xbfd4ba1ca2eca31c, 0xbfee467e7af35f23, // -0.32386, -0.94611 + 0xbfd4a253d11b82f3, 0xbfee4a8dff81ce5e, // -0.32241, -0.9466 + 0xbfd48a87d0b07fd7, 0xbfee4e98d836c0af, // -0.32096, -0.94709 + 0xbfd472b8a5571054, 0xbfee529f04729ffc, // -0.3195, -0.94759 + 0xbfd45ae652bb2800, 0xbfee56a083968eb1, // -0.31805, -0.94807 + 0xbfd44310dc8936f0, 0xbfee5a9d550467d3, // -0.31659, -0.94856 + 0xbfd42b38466e2928, 0xbfee5e95781ebf1c, // -0.31514, -0.94905 + 0xbfd4135c94176602, 0xbfee6288ec48e112, // -0.31368, -0.94953 + 0xbfd3fb7dc932cfa4, 0xbfee6677b0e6d31e, // -0.31222, -0.95001 + 0xbfd3e39be96ec271, 0xbfee6a61c55d53a7, // -0.31077, -0.95049 + 0xbfd3cbb6f87a146e, 0xbfee6e472911da27, // -0.30931, -0.95096 + 0xbfd3b3cefa0414b7, 0xbfee7227db6a9744, // -0.30785, -0.95144 + 0xbfd39be3f1bc8aef, 0xbfee7603dbce74e9, // -0.30639, -0.95191 + 0xbfd383f5e353b6aa, 0xbfee79db29a5165a, // -0.30493, -0.95238 + 0xbfd36c04d27a4edf, 0xbfee7dadc456d850, // -0.30347, -0.95284 + 0xbfd35410c2e18152, 0xbfee817bab4cd10d, // -0.30201, -0.95331 + 0xbfd33c19b83af207, 0xbfee8544ddf0d075, // -0.30054, -0.95377 + 0xbfd3241fb638baaf, 0xbfee89095bad6025, // -0.29908, -0.95423 + 0xbfd30c22c08d6a13, 0xbfee8cc923edc388, // -0.29762, -0.95469 + 0xbfd2f422daec0386, 0xbfee9084361df7f3, // -0.29615, -0.95514 + 0xbfd2dc200907fe51, 0xbfee943a91aab4b4, // -0.29469, -0.95559 + 0xbfd2c41a4e954520, 0xbfee97ec36016b30, // -0.29322, -0.95605 + 0xbfd2ac11af483572, 0xbfee9b99229046f8, // -0.29175, -0.95649 + 0xbfd294062ed59f05, 0xbfee9f4156c62dda, // -0.29028, -0.95694 + 0xbfd27bf7d0f2c346, 0xbfeea2e4d212c000, // -0.28882, -0.95738 + 0xbfd263e6995554ba, 0xbfeea68393e65800, // -0.28735, -0.95783 + 0xbfd24bd28bb37672, 0xbfeeaa1d9bb20af3, // -0.28588, -0.95827 + 0xbfd233bbabc3bb72, 0xbfeeadb2e8e7a88e, // -0.28441, -0.9587 + 0xbfd21ba1fd3d2623, 0xbfeeb1437af9bb34, // -0.28294, -0.95914 + 0xbfd2038583d727bd, 0xbfeeb4cf515b8811, // -0.28146, -0.95957 + 0xbfd1eb6643499fbb, 0xbfeeb8566b810f2a, // -0.27999, -0.96 + 0xbfd1d3443f4cdb3d, 0xbfeebbd8c8df0b74, // -0.27852, -0.96043 + 0xbfd1bb1f7b999480, 0xbfeebf5668eaf2ef, // -0.27705, -0.96086 + 0xbfd1a2f7fbe8f243, 0xbfeec2cf4b1af6b2, // -0.27557, -0.96128 + 0xbfd18acdc3f4873a, 0xbfeec6436ee60309, // -0.2741, -0.9617 + 0xbfd172a0d7765177, 0xbfeec9b2d3c3bf84, // -0.27262, -0.96212 + 0xbfd15a713a28b9d9, 0xbfeecd1d792c8f10, // -0.27115, -0.96254 + 0xbfd1423eefc69378, 0xbfeed0835e999009, // -0.26967, -0.96295 + 0xbfd12a09fc0b1b12, 0xbfeed3e483849c51, // -0.26819, -0.96337 + 0xbfd111d262b1f677, 0xbfeed740e7684963, // -0.26671, -0.96378 + 0xbfd0f998277733f7, 0xbfeeda9889bfe86a, // -0.26523, -0.96418 + 0xbfd0e15b4e1749cd, 0xbfeeddeb6a078651, // -0.26375, -0.96459 + 0xbfd0c91bda4f158d, 0xbfeee13987bbebdc, // -0.26227, -0.96499 + 0xbfd0b0d9cfdbdb90, 0xbfeee482e25a9dbc, // -0.26079, -0.96539 + 0xbfd09895327b465e, 0xbfeee7c77961dc9e, // -0.25931, -0.96579 + 0xbfd0804e05eb661e, 0xbfeeeb074c50a544, // -0.25783, -0.96619 + 0xbfd068044deab002, 0xbfeeee425aa6b09a, // -0.25635, -0.96658 + 0xbfd04fb80e37fdae, 0xbfeef178a3e473c2, // -0.25487, -0.96698 + 0xbfd037694a928cac, 0xbfeef4aa278b2032, // -0.25338, -0.96737 + 0xbfd01f1806b9fdd2, 0xbfeef7d6e51ca3c0, // -0.2519, -0.96775 + 0xbfd006c4466e54af, 0xbfeefafedc1ba8b7, // -0.25041, -0.96814 + 0xbfcfdcdc1adfedf8, 0xbfeefe220c0b95ec, // -0.24893, -0.96852 + 0xbfcfac2abeff57ff, 0xbfef014074708ed3, // -0.24744, -0.9689 + 0xbfcf7b7480bd3801, 0xbfef045a14cf738c, // -0.24596, -0.96928 + 0xbfcf4ab9679c9f5c, 0xbfef076eecade0fa, // -0.24447, -0.96966 + 0xbfcf19f97b215f1a, 0xbfef0a7efb9230d7, // -0.24298, -0.97003 + 0xbfcee934c2d006c7, 0xbfef0d8a410379c5, // -0.24149, -0.9704 + 0xbfceb86b462de348, 0xbfef1090bc898f5f, // -0.24, -0.97077 + 0xbfce879d0cc0fdaf, 0xbfef13926dad024e, // -0.23851, -0.97114 + 0xbfce56ca1e101a1b, 0xbfef168f53f7205d, // -0.23702, -0.9715 + 0xbfce25f281a2b684, 0xbfef19876ef1f486, // -0.23553, -0.97187 + 0xbfcdf5163f01099a, 0xbfef1c7abe284708, // -0.23404, -0.97223 + 0xbfcdc4355db40195, 0xbfef1f6941259d7a, // -0.23255, -0.97258 + 0xbfcd934fe5454311, 0xbfef2252f7763ada, // -0.23106, -0.97294 + 0xbfcd6265dd3f27e3, 0xbfef2537e0a71f9f, // -0.22957, -0.97329 + 0xbfcd31774d2cbdee, 0xbfef2817fc4609ce, // -0.22807, -0.97364 + 0xbfcd00843c99c5f9, 0xbfef2af349e17507, // -0.22658, -0.97399 + 0xbfcccf8cb312b286, 0xbfef2dc9c9089a9d, // -0.22508, -0.97434 + 0xbfcc9e90b824a6a9, 0xbfef309b794b719f, // -0.22359, -0.97468 + 0xbfcc6d90535d74dc, 0xbfef33685a3aaef0, // -0.22209, -0.97503 + 0xbfcc3c8b8c4b9dd7, 0xbfef36306b67c556, // -0.2206, -0.97536 + 0xbfcc0b826a7e4f63, 0xbfef38f3ac64e589, // -0.2191, -0.9757 + 0xbfcbda74f5856330, 0xbfef3bb21cc4fe47, // -0.2176, -0.97604 + 0xbfcba96334f15dad, 0xbfef3e6bbc1bbc65, // -0.21611, -0.97637 + 0xbfcb784d30536cda, 0xbfef412089fd8adc, // -0.21461, -0.9767 + 0xbfcb4732ef3d6722, 0xbfef43d085ff92dd, // -0.21311, -0.97703 + 0xbfcb16147941ca2a, 0xbfef467bafb7bbe0, // -0.21161, -0.97735 + 0xbfcae4f1d5f3b9ab, 0xbfef492206bcabb4, // -0.21011, -0.97768 + 0xbfcab3cb0ce6fe44, 0xbfef4bc38aa5c694, // -0.20861, -0.978 + 0xbfca82a025b00451, 0xbfef4e603b0b2f2d, // -0.20711, -0.97832 + 0xbfca517127e3dabc, 0xbfef50f81785c6b9, // -0.20561, -0.97863 + 0xbfca203e1b1831da, 0xbfef538b1faf2d07, // -0.20411, -0.97895 + 0xbfc9ef0706e35a35, 0xbfef56195321c090, // -0.20261, -0.97926 + 0xbfc9bdcbf2dc4366, 0xbfef58a2b1789e84, // -0.2011, -0.97957 + 0xbfc98c8ce69a7aec, 0xbfef5b273a4fa2d9, // -0.1996, -0.97988 + 0xbfc95b49e9b62af9, 0xbfef5da6ed43685d, // -0.1981, -0.98018 + 0xbfc92a0303c8194f, 0xbfef6021c9f148c2, // -0.19659, -0.98048 + 0xbfc8f8b83c69a60a, 0xbfef6297cff75cb0, // -0.19509, -0.98079 + 0xbfc8c7699b34ca7e, 0xbfef6508fef47bd5, // -0.19359, -0.98108 + 0xbfc8961727c41804, 0xbfef677556883cee, // -0.19208, -0.98138 + 0xbfc864c0e9b2b6cf, 0xbfef69dcd652f5de, // -0.19057, -0.98167 + 0xbfc83366e89c64c5, 0xbfef6c3f7df5bbb7, // -0.18907, -0.98196 + 0xbfc802092c1d744b, 0xbfef6e9d4d1262ca, // -0.18756, -0.98225 + 0xbfc7d0a7bbd2cb1b, 0xbfef70f6434b7eb7, // -0.18606, -0.98254 + 0xbfc79f429f59e11d, 0xbfef734a60446279, // -0.18455, -0.98282 + 0xbfc76dd9de50bf31, 0xbfef7599a3a12077, // -0.18304, -0.98311 + 0xbfc73c6d8055fe0a, 0xbfef77e40d068a90, // -0.18153, -0.98339 + 0xbfc70afd8d08c4ff, 0xbfef7a299c1a322a, // -0.18002, -0.98366 + 0xbfc6d98a0c08c8da, 0xbfef7c6a50826840, // -0.17851, -0.98394 + 0xbfc6a81304f64ab2, 0xbfef7ea629e63d6e, // -0.177, -0.98421 + 0xbfc676987f7216b8, 0xbfef80dd27ed8204, // -0.17549, -0.98448 + 0xbfc6451a831d830d, 0xbfef830f4a40c60c, // -0.17398, -0.98475 + 0xbfc61399179a6e94, 0xbfef853c9089595e, // -0.17247, -0.98501 + 0xbfc5e214448b3fc6, 0xbfef8764fa714ba9, // -0.17096, -0.98528 + 0xbfc5b08c1192e381, 0xbfef898887a36c84, // -0.16945, -0.98554 + 0xbfc57f008654cbde, 0xbfef8ba737cb4b78, // -0.16794, -0.9858 + 0xbfc54d71aa74ef02, 0xbfef8dc10a95380d, // -0.16643, -0.98605 + 0xbfc51bdf8597c5f2, 0xbfef8fd5ffae41db, // -0.16491, -0.98631 + 0xbfc4ea4a1f624b61, 0xbfef91e616c43891, // -0.1634, -0.98656 + 0xbfc4b8b17f79fa88, 0xbfef93f14f85ac08, // -0.16189, -0.98681 + 0xbfc48715ad84cdf5, 0xbfef95f7a9a1ec47, // -0.16037, -0.98706 + 0xbfc45576b1293e5a, 0xbfef97f924c9099b, // -0.15886, -0.9873 + 0xbfc423d4920e4166, 0xbfef99f5c0abd496, // -0.15734, -0.98754 + 0xbfc3f22f57db4893, 0xbfef9bed7cfbde29, // -0.15583, -0.98778 + 0xbfc3c0870a383ff6, 0xbfef9de0596b77a3, // -0.15431, -0.98802 + 0xbfc38edbb0cd8d14, 0xbfef9fce55adb2c8, // -0.1528, -0.98826 + 0xbfc35d2d53440db2, 0xbfefa1b7717661d5, // -0.15128, -0.98849 + 0xbfc32b7bf94516a7, 0xbfefa39bac7a1791, // -0.14976, -0.98872 + 0xbfc2f9c7aa7a72af, 0xbfefa57b066e2754, // -0.14825, -0.98895 + 0xbfc2c8106e8e613a, 0xbfefa7557f08a517, // -0.14673, -0.98918 + 0xbfc296564d2b953e, 0xbfefa92b1600657c, // -0.14521, -0.9894 + 0xbfc264994dfd340a, 0xbfefaafbcb0cfddc, // -0.1437, -0.98962 + 0xbfc232d978aed413, 0xbfefacc79de6c44f, // -0.14218, -0.98984 + 0xbfc20116d4ec7bce, 0xbfefae8e8e46cfbb, // -0.14066, -0.99006 + 0xbfc1cf516a62a077, 0xbfefb0509be6f7db, // -0.13914, -0.99027 + 0xbfc19d8940be24e7, 0xbfefb20dc681d54d, // -0.13762, -0.99049 + 0xbfc16bbe5fac5865, 0xbfefb3c60dd2c199, // -0.1361, -0.9907 + 0xbfc139f0cedaf576, 0xbfefb5797195d741, // -0.13458, -0.9909 + 0xbfc1082095f820b0, 0xbfefb727f187f1c7, // -0.13306, -0.99111 + 0xbfc0d64dbcb26786, 0xbfefb8d18d66adb7, // -0.13154, -0.99131 + 0xbfc0a4784ab8bf1d, 0xbfefba7644f068b5, // -0.13002, -0.99151 + 0xbfc072a047ba831d, 0xbfefbc1617e44186, // -0.1285, -0.99171 + 0xbfc040c5bb67747e, 0xbfefbdb106021816, // -0.12698, -0.99191 + 0xbfc00ee8ad6fb85b, 0xbfefbf470f0a8d88, // -0.12545, -0.9921 + 0xbfbfba124b07ad85, 0xbfefc0d832bf043a, // -0.12393, -0.99229 + 0xbfbf564e56a9730e, 0xbfefc26470e19fd3, // -0.12241, -0.99248 + 0xbfbef2858d27561b, 0xbfefc3ebc935454c, // -0.12089, -0.99267 + 0xbfbe8eb7fde4aa3e, 0xbfefc56e3b7d9af6, // -0.11937, -0.99285 + 0xbfbe2ae5b8457f77, 0xbfefc6ebc77f0887, // -0.11784, -0.99303 + 0xbfbdc70ecbae9fc8, 0xbfefc8646cfeb721, // -0.11632, -0.99321 + 0xbfbd633347858ce4, 0xbfefc9d82bc2915e, // -0.11479, -0.99339 + 0xbfbcff533b307dc1, 0xbfefcb4703914354, // -0.11327, -0.99356 + 0xbfbc9b6eb6165c42, 0xbfefccb0f4323aa3, // -0.11175, -0.99374 + 0xbfbc3785c79ec2d5, 0xbfefce15fd6da67b, // -0.11022, -0.99391 + 0xbfbbd3987f31fa0e, 0xbfefcf761f0c77a3, // -0.1087, -0.99407 + 0xbfbb6fa6ec38f64c, 0xbfefd0d158d86087, // -0.10717, -0.99424 + 0xbfbb0bb11e1d5559, 0xbfefd227aa9bd53b, // -0.10565, -0.9944 + 0xbfbaa7b724495c04, 0xbfefd37914220b84, // -0.10412, -0.99456 + 0xbfba43b90e27f3c4, 0xbfefd4c59536fae4, // -0.1026, -0.99472 + 0xbfb9dfb6eb24a85c, 0xbfefd60d2da75c9e, // -0.10107, -0.99488 + 0xbfb97bb0caaba56f, 0xbfefd74fdd40abbf, // -0.099544, -0.99503 + 0xbfb917a6bc29b42c, 0xbfefd88da3d12526, // -0.098017, -0.99518 + 0xbfb8b398cf0c38e0, 0xbfefd9c68127c78c, // -0.09649, -0.99533 + 0xbfb84f8712c130a0, 0xbfefdafa7514538c, // -0.094963, -0.99548 + 0xbfb7eb7196b72ee4, 0xbfefdc297f674ba9, // -0.093436, -0.99563 + 0xbfb787586a5d5b21, 0xbfefdd539ff1f456, // -0.091909, -0.99577 + 0xbfb7233b9d236e71, 0xbfefde78d68653fd, // -0.090381, -0.99591 + 0xbfb6bf1b3e79b129, 0xbfefdf9922f73307, // -0.088854, -0.99604 + 0xbfb65af75dd0f87b, 0xbfefe0b485181be3, // -0.087326, -0.99618 + 0xbfb5f6d00a9aa419, 0xbfefe1cafcbd5b09, // -0.085797, -0.99631 + 0xbfb592a554489bc8, 0xbfefe2dc89bbff08, // -0.084269, -0.99644 + 0xbfb52e774a4d4d0a, 0xbfefe3e92be9d886, // -0.08274, -0.99657 + 0xbfb4ca45fc1ba8b6, 0xbfefe4f0e31d7a4a, // -0.081211, -0.9967 + 0xbfb4661179272096, 0xbfefe5f3af2e3940, // -0.079682, -0.99682 + 0xbfb401d9d0e3a507, 0xbfefe6f18ff42c84, // -0.078153, -0.99694 + 0xbfb39d9f12c5a299, 0xbfefe7ea85482d60, // -0.076624, -0.99706 + 0xbfb339614e41ffa5, 0xbfefe8de8f03d75c, // -0.075094, -0.99718 + 0xbfb2d52092ce19f6, 0xbfefe9cdad01883a, // -0.073565, -0.99729 + 0xbfb270dcefdfc45b, 0xbfefeab7df1c6005, // -0.072035, -0.9974 + 0xbfb20c9674ed444c, 0xbfefeb9d2530410f, // -0.070505, -0.99751 + 0xbfb1a84d316d4f8a, 0xbfefec7d7f19cffc, // -0.068974, -0.99762 + 0xbfb1440134d709b2, 0xbfefed58ecb673c4, // -0.067444, -0.99772 + 0xbfb0dfb28ea201e6, 0xbfefee2f6de455ba, // -0.065913, -0.99783 + 0xbfb07b614e463064, 0xbfefef0102826191, // -0.064383, -0.99793 + 0xbfb0170d833bf421, 0xbfefefcdaa704562, // -0.062852, -0.99802 + 0xbfaf656e79f820e0, 0xbfeff095658e71ad, // -0.061321, -0.99812 + 0xbfae9cbd15ff5527, 0xbfeff15833be1965, // -0.05979, -0.99821 + 0xbfadd406f9808ec8, 0xbfeff21614e131ed, // -0.058258, -0.9983 + 0xbfad0b4c436f91d0, 0xbfeff2cf08da7321, // -0.056727, -0.99839 + 0xbfac428d12c0d7e3, 0xbfeff3830f8d575c, // -0.055195, -0.99848 + 0xbfab79c986698b78, 0xbfeff43228de1b77, // -0.053664, -0.99856 + 0xbfaab101bd5f8317, 0xbfeff4dc54b1bed3, // -0.052132, -0.99864 + 0xbfa9e835d6993c87, 0xbfeff58192ee0358, // -0.0506, -0.99872 + 0xbfa91f65f10dd814, 0xbfeff621e3796d7e, // -0.049068, -0.9988 + 0xbfa856922bb513c1, 0xbfeff6bd463b444d, // -0.047535, -0.99887 + 0xbfa78dbaa5874685, 0xbfeff753bb1b9164, // -0.046003, -0.99894 + 0xbfa6c4df7d7d5b84, 0xbfeff7e5420320f9, // -0.044471, -0.99901 + 0xbfa5fc00d290cd43, 0xbfeff871dadb81df, // -0.042938, -0.99908 + 0xbfa5331ec3bba0eb, 0xbfeff8f9858f058b, // -0.041406, -0.99914 + 0xbfa46a396ff86179, 0xbfeff97c4208c014, // -0.039873, -0.9992 + 0xbfa3a150f6421afc, 0xbfeff9fa10348837, // -0.03834, -0.99926 + 0xbfa2d865759455cd, 0xbfeffa72effef75d, // -0.036807, -0.99932 + 0xbfa20f770ceb11c6, 0xbfeffae6e1556998, // -0.035274, -0.99938 + 0xbfa14685db42c17e, 0xbfeffb55e425fdae, // -0.033741, -0.99943 + 0xbfa07d91ff984580, 0xbfeffbbff85f9515, // -0.032208, -0.99948 + 0xbf9f693731d1cf01, 0xbfeffc251df1d3f8, // -0.030675, -0.99953 + 0xbf9dd7458c64ab39, 0xbfeffc8554cd213a, // -0.029142, -0.99958 + 0xbf9c454f4ce53b1c, 0xbfeffce09ce2a679, // -0.027608, -0.99962 + 0xbf9ab354b1504fca, 0xbfeffd36f624500c, // -0.026075, -0.99966 + 0xbf992155f7a3667e, 0xbfeffd886084cd0d, // -0.024541, -0.9997 + 0xbf978f535ddc9f03, 0xbfeffdd4dbf78f52, // -0.023008, -0.99974 + 0xbf95fd4d21fab226, 0xbfeffe1c6870cb77, // -0.021474, -0.99977 + 0xbf946b4381fce81c, 0xbfeffe5f05e578db, // -0.01994, -0.9998 + 0xbf92d936bbe30efd, 0xbfeffe9cb44b51a1, // -0.018407, -0.99983 + 0xbf9147270dad7132, 0xbfeffed57398d2b7, // -0.016873, -0.99986 + 0xbf8f6a296ab997ca, 0xbfefff0943c53bd1, // -0.015339, -0.99988 + 0xbf8c45ffe1e48ad9, 0xbfefff3824c88f6f, // -0.013805, -0.9999 + 0xbf8921d1fcdec784, 0xbfefff62169b92db, // -0.012272, -0.99992 + 0xbf85fda037ac05e0, 0xbfefff871937ce2f, // -0.010738, -0.99994 + 0xbf82d96b0e509703, 0xbfefffa72c978c4f, //-0.0092038, -0.99996 + 0xbf7f6a65f9a2a3c5, 0xbfefffc250b5daef, //-0.0076698, -0.99997 + 0xbf7921f0fe670071, 0xbfefffd8858e8a92, //-0.0061359, -0.99998 + 0xbf72d97822f996bc, 0xbfefffe9cb1e2e8d, //-0.0046019, -0.99999 + 0xbf6921f8becca4ba, 0xbfeffff621621d02, // -0.003068, -1 + 0xbf5921faaee6472d, 0xbfeffffd88586ee6, // -0.001534, -1 + 0x0000000000000000, 0xbff0000000000000, // 0, -1 + 0x3f5921faaee6472d, 0xbfeffffd88586ee6, // 0.001534, -1 + 0x3f6921f8becca4ba, 0xbfeffff621621d02, // 0.003068, -1 + 0x3f72d97822f996bc, 0xbfefffe9cb1e2e8d, // 0.0046019, -0.99999 + 0x3f7921f0fe670071, 0xbfefffd8858e8a92, // 0.0061359, -0.99998 + 0x3f7f6a65f9a2a3c5, 0xbfefffc250b5daef, // 0.0076698, -0.99997 + 0x3f82d96b0e509703, 0xbfefffa72c978c4f, // 0.0092038, -0.99996 + 0x3f85fda037ac05e0, 0xbfefff871937ce2f, // 0.010738, -0.99994 + 0x3f8921d1fcdec784, 0xbfefff62169b92db, // 0.012272, -0.99992 + 0x3f8c45ffe1e48ad9, 0xbfefff3824c88f6f, // 0.013805, -0.9999 + 0x3f8f6a296ab997ca, 0xbfefff0943c53bd1, // 0.015339, -0.99988 + 0x3f9147270dad7132, 0xbfeffed57398d2b7, // 0.016873, -0.99986 + 0x3f92d936bbe30efd, 0xbfeffe9cb44b51a1, // 0.018407, -0.99983 + 0x3f946b4381fce81c, 0xbfeffe5f05e578db, // 0.01994, -0.9998 + 0x3f95fd4d21fab226, 0xbfeffe1c6870cb77, // 0.021474, -0.99977 + 0x3f978f535ddc9f03, 0xbfeffdd4dbf78f52, // 0.023008, -0.99974 + 0x3f992155f7a3667e, 0xbfeffd886084cd0d, // 0.024541, -0.9997 + 0x3f9ab354b1504fca, 0xbfeffd36f624500c, // 0.026075, -0.99966 + 0x3f9c454f4ce53b1c, 0xbfeffce09ce2a679, // 0.027608, -0.99962 + 0x3f9dd7458c64ab39, 0xbfeffc8554cd213a, // 0.029142, -0.99958 + 0x3f9f693731d1cf01, 0xbfeffc251df1d3f8, // 0.030675, -0.99953 + 0x3fa07d91ff984580, 0xbfeffbbff85f9515, // 0.032208, -0.99948 + 0x3fa14685db42c17e, 0xbfeffb55e425fdae, // 0.033741, -0.99943 + 0x3fa20f770ceb11c6, 0xbfeffae6e1556998, // 0.035274, -0.99938 + 0x3fa2d865759455cd, 0xbfeffa72effef75d, // 0.036807, -0.99932 + 0x3fa3a150f6421afc, 0xbfeff9fa10348837, // 0.03834, -0.99926 + 0x3fa46a396ff86179, 0xbfeff97c4208c014, // 0.039873, -0.9992 + 0x3fa5331ec3bba0eb, 0xbfeff8f9858f058b, // 0.041406, -0.99914 + 0x3fa5fc00d290cd43, 0xbfeff871dadb81df, // 0.042938, -0.99908 + 0x3fa6c4df7d7d5b84, 0xbfeff7e5420320f9, // 0.044471, -0.99901 + 0x3fa78dbaa5874685, 0xbfeff753bb1b9164, // 0.046003, -0.99894 + 0x3fa856922bb513c1, 0xbfeff6bd463b444d, // 0.047535, -0.99887 + 0x3fa91f65f10dd814, 0xbfeff621e3796d7e, // 0.049068, -0.9988 + 0x3fa9e835d6993c87, 0xbfeff58192ee0358, // 0.0506, -0.99872 + 0x3faab101bd5f8317, 0xbfeff4dc54b1bed3, // 0.052132, -0.99864 + 0x3fab79c986698b78, 0xbfeff43228de1b77, // 0.053664, -0.99856 + 0x3fac428d12c0d7e3, 0xbfeff3830f8d575c, // 0.055195, -0.99848 + 0x3fad0b4c436f91d0, 0xbfeff2cf08da7321, // 0.056727, -0.99839 + 0x3fadd406f9808ec8, 0xbfeff21614e131ed, // 0.058258, -0.9983 + 0x3fae9cbd15ff5527, 0xbfeff15833be1965, // 0.05979, -0.99821 + 0x3faf656e79f820e0, 0xbfeff095658e71ad, // 0.061321, -0.99812 + 0x3fb0170d833bf421, 0xbfefefcdaa704562, // 0.062852, -0.99802 + 0x3fb07b614e463064, 0xbfefef0102826191, // 0.064383, -0.99793 + 0x3fb0dfb28ea201e6, 0xbfefee2f6de455ba, // 0.065913, -0.99783 + 0x3fb1440134d709b2, 0xbfefed58ecb673c4, // 0.067444, -0.99772 + 0x3fb1a84d316d4f8a, 0xbfefec7d7f19cffc, // 0.068974, -0.99762 + 0x3fb20c9674ed444c, 0xbfefeb9d2530410f, // 0.070505, -0.99751 + 0x3fb270dcefdfc45b, 0xbfefeab7df1c6005, // 0.072035, -0.9974 + 0x3fb2d52092ce19f6, 0xbfefe9cdad01883a, // 0.073565, -0.99729 + 0x3fb339614e41ffa5, 0xbfefe8de8f03d75c, // 0.075094, -0.99718 + 0x3fb39d9f12c5a299, 0xbfefe7ea85482d60, // 0.076624, -0.99706 + 0x3fb401d9d0e3a507, 0xbfefe6f18ff42c84, // 0.078153, -0.99694 + 0x3fb4661179272096, 0xbfefe5f3af2e3940, // 0.079682, -0.99682 + 0x3fb4ca45fc1ba8b6, 0xbfefe4f0e31d7a4a, // 0.081211, -0.9967 + 0x3fb52e774a4d4d0a, 0xbfefe3e92be9d886, // 0.08274, -0.99657 + 0x3fb592a554489bc8, 0xbfefe2dc89bbff08, // 0.084269, -0.99644 + 0x3fb5f6d00a9aa419, 0xbfefe1cafcbd5b09, // 0.085797, -0.99631 + 0x3fb65af75dd0f87b, 0xbfefe0b485181be3, // 0.087326, -0.99618 + 0x3fb6bf1b3e79b129, 0xbfefdf9922f73307, // 0.088854, -0.99604 + 0x3fb7233b9d236e71, 0xbfefde78d68653fd, // 0.090381, -0.99591 + 0x3fb787586a5d5b21, 0xbfefdd539ff1f456, // 0.091909, -0.99577 + 0x3fb7eb7196b72ee4, 0xbfefdc297f674ba9, // 0.093436, -0.99563 + 0x3fb84f8712c130a0, 0xbfefdafa7514538c, // 0.094963, -0.99548 + 0x3fb8b398cf0c38e0, 0xbfefd9c68127c78c, // 0.09649, -0.99533 + 0x3fb917a6bc29b42c, 0xbfefd88da3d12526, // 0.098017, -0.99518 + 0x3fb97bb0caaba56f, 0xbfefd74fdd40abbf, // 0.099544, -0.99503 + 0x3fb9dfb6eb24a85c, 0xbfefd60d2da75c9e, // 0.10107, -0.99488 + 0x3fba43b90e27f3c4, 0xbfefd4c59536fae4, // 0.1026, -0.99472 + 0x3fbaa7b724495c04, 0xbfefd37914220b84, // 0.10412, -0.99456 + 0x3fbb0bb11e1d5559, 0xbfefd227aa9bd53b, // 0.10565, -0.9944 + 0x3fbb6fa6ec38f64c, 0xbfefd0d158d86087, // 0.10717, -0.99424 + 0x3fbbd3987f31fa0e, 0xbfefcf761f0c77a3, // 0.1087, -0.99407 + 0x3fbc3785c79ec2d5, 0xbfefce15fd6da67b, // 0.11022, -0.99391 + 0x3fbc9b6eb6165c42, 0xbfefccb0f4323aa3, // 0.11175, -0.99374 + 0x3fbcff533b307dc1, 0xbfefcb4703914354, // 0.11327, -0.99356 + 0x3fbd633347858ce4, 0xbfefc9d82bc2915e, // 0.11479, -0.99339 + 0x3fbdc70ecbae9fc8, 0xbfefc8646cfeb721, // 0.11632, -0.99321 + 0x3fbe2ae5b8457f77, 0xbfefc6ebc77f0887, // 0.11784, -0.99303 + 0x3fbe8eb7fde4aa3e, 0xbfefc56e3b7d9af6, // 0.11937, -0.99285 + 0x3fbef2858d27561b, 0xbfefc3ebc935454c, // 0.12089, -0.99267 + 0x3fbf564e56a9730e, 0xbfefc26470e19fd3, // 0.12241, -0.99248 + 0x3fbfba124b07ad85, 0xbfefc0d832bf043a, // 0.12393, -0.99229 + 0x3fc00ee8ad6fb85b, 0xbfefbf470f0a8d88, // 0.12545, -0.9921 + 0x3fc040c5bb67747e, 0xbfefbdb106021816, // 0.12698, -0.99191 + 0x3fc072a047ba831d, 0xbfefbc1617e44186, // 0.1285, -0.99171 + 0x3fc0a4784ab8bf1d, 0xbfefba7644f068b5, // 0.13002, -0.99151 + 0x3fc0d64dbcb26786, 0xbfefb8d18d66adb7, // 0.13154, -0.99131 + 0x3fc1082095f820b0, 0xbfefb727f187f1c7, // 0.13306, -0.99111 + 0x3fc139f0cedaf576, 0xbfefb5797195d741, // 0.13458, -0.9909 + 0x3fc16bbe5fac5865, 0xbfefb3c60dd2c199, // 0.1361, -0.9907 + 0x3fc19d8940be24e7, 0xbfefb20dc681d54d, // 0.13762, -0.99049 + 0x3fc1cf516a62a077, 0xbfefb0509be6f7db, // 0.13914, -0.99027 + 0x3fc20116d4ec7bce, 0xbfefae8e8e46cfbb, // 0.14066, -0.99006 + 0x3fc232d978aed413, 0xbfefacc79de6c44f, // 0.14218, -0.98984 + 0x3fc264994dfd340a, 0xbfefaafbcb0cfddc, // 0.1437, -0.98962 + 0x3fc296564d2b953e, 0xbfefa92b1600657c, // 0.14521, -0.9894 + 0x3fc2c8106e8e613a, 0xbfefa7557f08a517, // 0.14673, -0.98918 + 0x3fc2f9c7aa7a72af, 0xbfefa57b066e2754, // 0.14825, -0.98895 + 0x3fc32b7bf94516a7, 0xbfefa39bac7a1791, // 0.14976, -0.98872 + 0x3fc35d2d53440db2, 0xbfefa1b7717661d5, // 0.15128, -0.98849 + 0x3fc38edbb0cd8d14, 0xbfef9fce55adb2c8, // 0.1528, -0.98826 + 0x3fc3c0870a383ff6, 0xbfef9de0596b77a3, // 0.15431, -0.98802 + 0x3fc3f22f57db4893, 0xbfef9bed7cfbde29, // 0.15583, -0.98778 + 0x3fc423d4920e4166, 0xbfef99f5c0abd496, // 0.15734, -0.98754 + 0x3fc45576b1293e5a, 0xbfef97f924c9099b, // 0.15886, -0.9873 + 0x3fc48715ad84cdf5, 0xbfef95f7a9a1ec47, // 0.16037, -0.98706 + 0x3fc4b8b17f79fa88, 0xbfef93f14f85ac08, // 0.16189, -0.98681 + 0x3fc4ea4a1f624b61, 0xbfef91e616c43891, // 0.1634, -0.98656 + 0x3fc51bdf8597c5f2, 0xbfef8fd5ffae41db, // 0.16491, -0.98631 + 0x3fc54d71aa74ef02, 0xbfef8dc10a95380d, // 0.16643, -0.98605 + 0x3fc57f008654cbde, 0xbfef8ba737cb4b78, // 0.16794, -0.9858 + 0x3fc5b08c1192e381, 0xbfef898887a36c84, // 0.16945, -0.98554 + 0x3fc5e214448b3fc6, 0xbfef8764fa714ba9, // 0.17096, -0.98528 + 0x3fc61399179a6e94, 0xbfef853c9089595e, // 0.17247, -0.98501 + 0x3fc6451a831d830d, 0xbfef830f4a40c60c, // 0.17398, -0.98475 + 0x3fc676987f7216b8, 0xbfef80dd27ed8204, // 0.17549, -0.98448 + 0x3fc6a81304f64ab2, 0xbfef7ea629e63d6e, // 0.177, -0.98421 + 0x3fc6d98a0c08c8da, 0xbfef7c6a50826840, // 0.17851, -0.98394 + 0x3fc70afd8d08c4ff, 0xbfef7a299c1a322a, // 0.18002, -0.98366 + 0x3fc73c6d8055fe0a, 0xbfef77e40d068a90, // 0.18153, -0.98339 + 0x3fc76dd9de50bf31, 0xbfef7599a3a12077, // 0.18304, -0.98311 + 0x3fc79f429f59e11d, 0xbfef734a60446279, // 0.18455, -0.98282 + 0x3fc7d0a7bbd2cb1b, 0xbfef70f6434b7eb7, // 0.18606, -0.98254 + 0x3fc802092c1d744b, 0xbfef6e9d4d1262ca, // 0.18756, -0.98225 + 0x3fc83366e89c64c5, 0xbfef6c3f7df5bbb7, // 0.18907, -0.98196 + 0x3fc864c0e9b2b6cf, 0xbfef69dcd652f5de, // 0.19057, -0.98167 + 0x3fc8961727c41804, 0xbfef677556883cee, // 0.19208, -0.98138 + 0x3fc8c7699b34ca7e, 0xbfef6508fef47bd5, // 0.19359, -0.98108 + 0x3fc8f8b83c69a60a, 0xbfef6297cff75cb0, // 0.19509, -0.98079 + 0x3fc92a0303c8194f, 0xbfef6021c9f148c2, // 0.19659, -0.98048 + 0x3fc95b49e9b62af9, 0xbfef5da6ed43685d, // 0.1981, -0.98018 + 0x3fc98c8ce69a7aec, 0xbfef5b273a4fa2d9, // 0.1996, -0.97988 + 0x3fc9bdcbf2dc4366, 0xbfef58a2b1789e84, // 0.2011, -0.97957 + 0x3fc9ef0706e35a35, 0xbfef56195321c090, // 0.20261, -0.97926 + 0x3fca203e1b1831da, 0xbfef538b1faf2d07, // 0.20411, -0.97895 + 0x3fca517127e3dabc, 0xbfef50f81785c6b9, // 0.20561, -0.97863 + 0x3fca82a025b00451, 0xbfef4e603b0b2f2d, // 0.20711, -0.97832 + 0x3fcab3cb0ce6fe44, 0xbfef4bc38aa5c694, // 0.20861, -0.978 + 0x3fcae4f1d5f3b9ab, 0xbfef492206bcabb4, // 0.21011, -0.97768 + 0x3fcb16147941ca2a, 0xbfef467bafb7bbe0, // 0.21161, -0.97735 + 0x3fcb4732ef3d6722, 0xbfef43d085ff92dd, // 0.21311, -0.97703 + 0x3fcb784d30536cda, 0xbfef412089fd8adc, // 0.21461, -0.9767 + 0x3fcba96334f15dad, 0xbfef3e6bbc1bbc65, // 0.21611, -0.97637 + 0x3fcbda74f5856330, 0xbfef3bb21cc4fe47, // 0.2176, -0.97604 + 0x3fcc0b826a7e4f63, 0xbfef38f3ac64e589, // 0.2191, -0.9757 + 0x3fcc3c8b8c4b9dd7, 0xbfef36306b67c556, // 0.2206, -0.97536 + 0x3fcc6d90535d74dc, 0xbfef33685a3aaef0, // 0.22209, -0.97503 + 0x3fcc9e90b824a6a9, 0xbfef309b794b719f, // 0.22359, -0.97468 + 0x3fcccf8cb312b286, 0xbfef2dc9c9089a9d, // 0.22508, -0.97434 + 0x3fcd00843c99c5f9, 0xbfef2af349e17507, // 0.22658, -0.97399 + 0x3fcd31774d2cbdee, 0xbfef2817fc4609ce, // 0.22807, -0.97364 + 0x3fcd6265dd3f27e3, 0xbfef2537e0a71f9f, // 0.22957, -0.97329 + 0x3fcd934fe5454311, 0xbfef2252f7763ada, // 0.23106, -0.97294 + 0x3fcdc4355db40195, 0xbfef1f6941259d7a, // 0.23255, -0.97258 + 0x3fcdf5163f01099a, 0xbfef1c7abe284708, // 0.23404, -0.97223 + 0x3fce25f281a2b684, 0xbfef19876ef1f486, // 0.23553, -0.97187 + 0x3fce56ca1e101a1b, 0xbfef168f53f7205d, // 0.23702, -0.9715 + 0x3fce879d0cc0fdaf, 0xbfef13926dad024e, // 0.23851, -0.97114 + 0x3fceb86b462de348, 0xbfef1090bc898f5f, // 0.24, -0.97077 + 0x3fcee934c2d006c7, 0xbfef0d8a410379c5, // 0.24149, -0.9704 + 0x3fcf19f97b215f1a, 0xbfef0a7efb9230d7, // 0.24298, -0.97003 + 0x3fcf4ab9679c9f5c, 0xbfef076eecade0fa, // 0.24447, -0.96966 + 0x3fcf7b7480bd3801, 0xbfef045a14cf738c, // 0.24596, -0.96928 + 0x3fcfac2abeff57ff, 0xbfef014074708ed3, // 0.24744, -0.9689 + 0x3fcfdcdc1adfedf8, 0xbfeefe220c0b95ec, // 0.24893, -0.96852 + 0x3fd006c4466e54af, 0xbfeefafedc1ba8b7, // 0.25041, -0.96814 + 0x3fd01f1806b9fdd2, 0xbfeef7d6e51ca3c0, // 0.2519, -0.96775 + 0x3fd037694a928cac, 0xbfeef4aa278b2032, // 0.25338, -0.96737 + 0x3fd04fb80e37fdae, 0xbfeef178a3e473c2, // 0.25487, -0.96698 + 0x3fd068044deab002, 0xbfeeee425aa6b09a, // 0.25635, -0.96658 + 0x3fd0804e05eb661e, 0xbfeeeb074c50a544, // 0.25783, -0.96619 + 0x3fd09895327b465e, 0xbfeee7c77961dc9e, // 0.25931, -0.96579 + 0x3fd0b0d9cfdbdb90, 0xbfeee482e25a9dbc, // 0.26079, -0.96539 + 0x3fd0c91bda4f158d, 0xbfeee13987bbebdc, // 0.26227, -0.96499 + 0x3fd0e15b4e1749cd, 0xbfeeddeb6a078651, // 0.26375, -0.96459 + 0x3fd0f998277733f7, 0xbfeeda9889bfe86a, // 0.26523, -0.96418 + 0x3fd111d262b1f677, 0xbfeed740e7684963, // 0.26671, -0.96378 + 0x3fd12a09fc0b1b12, 0xbfeed3e483849c51, // 0.26819, -0.96337 + 0x3fd1423eefc69378, 0xbfeed0835e999009, // 0.26967, -0.96295 + 0x3fd15a713a28b9d9, 0xbfeecd1d792c8f10, // 0.27115, -0.96254 + 0x3fd172a0d7765177, 0xbfeec9b2d3c3bf84, // 0.27262, -0.96212 + 0x3fd18acdc3f4873a, 0xbfeec6436ee60309, // 0.2741, -0.9617 + 0x3fd1a2f7fbe8f243, 0xbfeec2cf4b1af6b2, // 0.27557, -0.96128 + 0x3fd1bb1f7b999480, 0xbfeebf5668eaf2ef, // 0.27705, -0.96086 + 0x3fd1d3443f4cdb3d, 0xbfeebbd8c8df0b74, // 0.27852, -0.96043 + 0x3fd1eb6643499fbb, 0xbfeeb8566b810f2a, // 0.27999, -0.96 + 0x3fd2038583d727bd, 0xbfeeb4cf515b8811, // 0.28146, -0.95957 + 0x3fd21ba1fd3d2623, 0xbfeeb1437af9bb34, // 0.28294, -0.95914 + 0x3fd233bbabc3bb72, 0xbfeeadb2e8e7a88e, // 0.28441, -0.9587 + 0x3fd24bd28bb37672, 0xbfeeaa1d9bb20af3, // 0.28588, -0.95827 + 0x3fd263e6995554ba, 0xbfeea68393e65800, // 0.28735, -0.95783 + 0x3fd27bf7d0f2c346, 0xbfeea2e4d212c000, // 0.28882, -0.95738 + 0x3fd294062ed59f05, 0xbfee9f4156c62dda, // 0.29028, -0.95694 + 0x3fd2ac11af483572, 0xbfee9b99229046f8, // 0.29175, -0.95649 + 0x3fd2c41a4e954520, 0xbfee97ec36016b30, // 0.29322, -0.95605 + 0x3fd2dc200907fe51, 0xbfee943a91aab4b4, // 0.29469, -0.95559 + 0x3fd2f422daec0386, 0xbfee9084361df7f3, // 0.29615, -0.95514 + 0x3fd30c22c08d6a13, 0xbfee8cc923edc388, // 0.29762, -0.95469 + 0x3fd3241fb638baaf, 0xbfee89095bad6025, // 0.29908, -0.95423 + 0x3fd33c19b83af207, 0xbfee8544ddf0d075, // 0.30054, -0.95377 + 0x3fd35410c2e18152, 0xbfee817bab4cd10d, // 0.30201, -0.95331 + 0x3fd36c04d27a4edf, 0xbfee7dadc456d850, // 0.30347, -0.95284 + 0x3fd383f5e353b6aa, 0xbfee79db29a5165a, // 0.30493, -0.95238 + 0x3fd39be3f1bc8aef, 0xbfee7603dbce74e9, // 0.30639, -0.95191 + 0x3fd3b3cefa0414b7, 0xbfee7227db6a9744, // 0.30785, -0.95144 + 0x3fd3cbb6f87a146e, 0xbfee6e472911da27, // 0.30931, -0.95096 + 0x3fd3e39be96ec271, 0xbfee6a61c55d53a7, // 0.31077, -0.95049 + 0x3fd3fb7dc932cfa4, 0xbfee6677b0e6d31e, // 0.31222, -0.95001 + 0x3fd4135c94176602, 0xbfee6288ec48e112, // 0.31368, -0.94953 + 0x3fd42b38466e2928, 0xbfee5e95781ebf1c, // 0.31514, -0.94905 + 0x3fd44310dc8936f0, 0xbfee5a9d550467d3, // 0.31659, -0.94856 + 0x3fd45ae652bb2800, 0xbfee56a083968eb1, // 0.31805, -0.94807 + 0x3fd472b8a5571054, 0xbfee529f04729ffc, // 0.3195, -0.94759 + 0x3fd48a87d0b07fd7, 0xbfee4e98d836c0af, // 0.32096, -0.94709 + 0x3fd4a253d11b82f3, 0xbfee4a8dff81ce5e, // 0.32241, -0.9466 + 0x3fd4ba1ca2eca31c, 0xbfee467e7af35f23, // 0.32386, -0.94611 + 0x3fd4d1e24278e76a, 0xbfee426a4b2bc17e, // 0.32531, -0.94561 + 0x3fd4e9a4ac15d520, 0xbfee3e5170cbfc46, // 0.32676, -0.94511 + 0x3fd50163dc197047, 0xbfee3a33ec75ce85, // 0.32821, -0.9446 + 0x3fd5191fceda3c35, 0xbfee3611becbaf69, // 0.32966, -0.9441 + 0x3fd530d880af3c24, 0xbfee31eae870ce25, // 0.33111, -0.94359 + 0x3fd5488dedeff3be, 0xbfee2dbf6a0911d9, // 0.33255, -0.94308 + 0x3fd5604012f467b4, 0xbfee298f4439197a, // 0.334, -0.94257 + 0x3fd577eeec151e47, 0xbfee255a77a63bb8, // 0.33545, -0.94206 + 0x3fd58f9a75ab1fdd, 0xbfee212104f686e5, // 0.33689, -0.94154 + 0x3fd5a742ac0ff78d, 0xbfee1ce2ecd0c0d8, // 0.33833, -0.94103 + 0x3fd5bee78b9db3b6, 0xbfee18a02fdc66d9, // 0.33978, -0.94051 + 0x3fd5d68910aee686, 0xbfee1458cec1ad83, // 0.34122, -0.93998 + 0x3fd5ee27379ea693, 0xbfee100cca2980ac, // 0.34266, -0.93946 + 0x3fd605c1fcc88f63, 0xbfee0bbc22bd8349, // 0.3441, -0.93893 + 0x3fd61d595c88c203, 0xbfee0766d9280f54, // 0.34554, -0.9384 + 0x3fd634ed533be58e, 0xbfee030cee1435b8, // 0.34698, -0.93787 + 0x3fd64c7ddd3f27c6, 0xbfedfeae622dbe2b, // 0.34842, -0.93734 + 0x3fd6640af6f03d9e, 0xbfedfa4b3621271d, // 0.34986, -0.9368 + 0x3fd67b949cad63ca, 0xbfedf5e36a9ba59c, // 0.35129, -0.93627 + 0x3fd6931acad55f51, 0xbfedf177004b2534, // 0.35273, -0.93573 + 0x3fd6aa9d7dc77e16, 0xbfeded05f7de47da, // 0.35416, -0.93518 + 0x3fd6c21cb1e39771, 0xbfede890520465ce, // 0.3556, -0.93464 + 0x3fd6d998638a0cb5, 0xbfede4160f6d8d81, // 0.35703, -0.93409 + 0x3fd6f1108f1bc9c5, 0xbfeddf9730ca837b, // 0.35846, -0.93354 + 0x3fd7088530fa459e, 0xbfeddb13b6ccc23d, // 0.3599, -0.93299 + 0x3fd71ff6458782ec, 0xbfedd68ba2267a25, // 0.36133, -0.93244 + 0x3fd73763c9261092, 0xbfedd1fef38a915a, // 0.36276, -0.93188 + 0x3fd74ecdb8390a3e, 0xbfedcd6dabaca3a5, // 0.36418, -0.93133 + 0x3fd766340f2418f6, 0xbfedc8d7cb410260, // 0.36561, -0.93077 + 0x3fd77d96ca4b73a6, 0xbfedc43d52fcb453, // 0.36704, -0.93021 + 0x3fd794f5e613dfae, 0xbfedbf9e4395759a, // 0.36847, -0.92964 + 0x3fd7ac515ee2b172, 0xbfedbafa9dc1b78d, // 0.36989, -0.92907 + 0x3fd7c3a9311dcce7, 0xbfedb6526238a09b, // 0.37132, -0.92851 + 0x3fd7dafd592ba621, 0xbfedb1a591b20c38, // 0.37274, -0.92794 + 0x3fd7f24dd37341e3, 0xbfedacf42ce68ab9, // 0.37416, -0.92736 + 0x3fd8099a9c5c362d, 0xbfeda83e348f613b, // 0.37559, -0.92679 + 0x3fd820e3b04eaac4, 0xbfeda383a9668988, // 0.37701, -0.92621 + 0x3fd838290bb359c8, 0xbfed9ec48c26b1f3, // 0.37843, -0.92563 + 0x3fd84f6aaaf3903f, 0xbfed9a00dd8b3d46, // 0.37985, -0.92505 + 0x3fd866a88a792ea0, 0xbfed95389e50429b, // 0.38127, -0.92447 + 0x3fd87de2a6aea963, 0xbfed906bcf328d46, // 0.38268, -0.92388 + 0x3fd89518fbff098e, 0xbfed8b9a70ef9cb4, // 0.3841, -0.92329 + 0x3fd8ac4b86d5ed44, 0xbfed86c48445a450, // 0.38552, -0.9227 + 0x3fd8c37a439f884f, 0xbfed81ea09f38b63, // 0.38693, -0.92211 + 0x3fd8daa52ec8a4af, 0xbfed7d0b02b8ecf9, // 0.38835, -0.92151 + 0x3fd8f1cc44bea329, 0xbfed78276f5617c6, // 0.38976, -0.92092 + 0x3fd908ef81ef7bd1, 0xbfed733f508c0dff, // 0.39117, -0.92032 + 0x3fd9200ee2c9be97, 0xbfed6e52a71c8547, // 0.39258, -0.91972 + 0x3fd9372a63bc93d7, 0xbfed696173c9e68b, // 0.39399, -0.91911 + 0x3fd94e420137bce3, 0xbfed646bb7574de5, // 0.3954, -0.91851 + 0x3fd96555b7ab948f, 0xbfed5f7172888a7f, // 0.39681, -0.9179 + 0x3fd97c6583890fc2, 0xbfed5a72a6221e73, // 0.39822, -0.91729 + 0x3fd993716141bdfe, 0xbfed556f52e93eb1, // 0.39962, -0.91668 + 0x3fd9aa794d47c9ee, 0xbfed506779a3d2d9, // 0.40103, -0.91606 + 0x3fd9c17d440df9f2, 0xbfed4b5b1b187524, // 0.40243, -0.91545 + 0x3fd9d87d4207b0ab, 0xbfed464a380e7242, // 0.40384, -0.91483 + 0x3fd9ef7943a8ed8a, 0xbfed4134d14dc93a, // 0.40524, -0.91421 + 0x3fda067145664d57, 0xbfed3c1ae79f2b4e, // 0.40664, -0.91359 + 0x3fda1d6543b50ac0, 0xbfed36fc7bcbfbdc, // 0.40804, -0.91296 + 0x3fda34553b0afee5, 0xbfed31d98e9e503a, // 0.40944, -0.91234 + 0x3fda4b4127dea1e4, 0xbfed2cb220e0ef9f, // 0.41084, -0.91171 + 0x3fda622906a70b63, 0xbfed2786335f52fc, // 0.41224, -0.91107 + 0x3fda790cd3dbf31a, 0xbfed2255c6e5a4e1, // 0.41364, -0.91044 + 0x3fda8fec8bf5b166, 0xbfed1d20dc40c15c, // 0.41503, -0.90981 + 0x3fdaa6c82b6d3fc9, 0xbfed17e7743e35dc, // 0.41643, -0.90917 + 0x3fdabd9faebc3980, 0xbfed12a98fac410c, // 0.41782, -0.90853 + 0x3fdad473125cdc08, 0xbfed0d672f59d2b9, // 0.41922, -0.90789 + 0x3fdaeb4252ca07ab, 0xbfed082054168bac, // 0.42061, -0.90724 + 0x3fdb020d6c7f4009, 0xbfed02d4feb2bd92, // 0.422, -0.9066 + 0x3fdb18d45bf8aca6, 0xbfecfd852fff6ad4, // 0.42339, -0.90595 + 0x3fdb2f971db31972, 0xbfecf830e8ce467b, // 0.42478, -0.9053 + 0x3fdb4655ae2bf757, 0xbfecf2d829f1b40e, // 0.42617, -0.90464 + 0x3fdb5d1009e15cc0, 0xbfeced7af43cc773, // 0.42756, -0.90399 + 0x3fdb73c62d520624, 0xbfece819488344ce, // 0.42894, -0.90333 + 0x3fdb8a7814fd5693, 0xbfece2b32799a060, // 0.43033, -0.90267 + 0x3fdba125bd63583e, 0xbfecdd489254fe65, // 0.43171, -0.90201 + 0x3fdbb7cf2304bd01, 0xbfecd7d9898b32f6, // 0.43309, -0.90135 + 0x3fdbce744262deee, 0xbfecd2660e12c1e6, // 0.43448, -0.90068 + 0x3fdbe51517ffc0d9, 0xbfecccee20c2de9f, // 0.43586, -0.90002 + 0x3fdbfbb1a05e0edc, 0xbfecc771c2736c09, // 0.43724, -0.89935 + 0x3fdc1249d8011ee7, 0xbfecc1f0f3fcfc5c, // 0.43862, -0.89867 + 0x3fdc28ddbb6cf145, 0xbfecbc6bb638d10b, // 0.43999, -0.898 + 0x3fdc3f6d47263129, 0xbfecb6e20a00da99, // 0.44137, -0.89732 + 0x3fdc55f877b23537, 0xbfecb153f02fb87d, // 0.44275, -0.89665 + 0x3fdc6c7f4997000a, 0xbfecabc169a0b901, // 0.44412, -0.89597 + 0x3fdc8301b95b40c2, 0xbfeca62a772fd919, // 0.4455, -0.89528 + 0x3fdc997fc3865388, 0xbfeca08f19b9c449, // 0.44687, -0.8946 + 0x3fdcaff964a0421d, 0xbfec9aef521bd480, // 0.44824, -0.89391 + 0x3fdcc66e9931c45d, 0xbfec954b213411f5, // 0.44961, -0.89322 + 0x3fdcdcdf5dc440ce, 0xbfec8fa287e13305, // 0.45098, -0.89253 + 0x3fdcf34baee1cd21, 0xbfec89f587029c13, // 0.45235, -0.89184 + 0x3fdd09b389152ec1, 0xbfec84441f785f61, // 0.45372, -0.89115 + 0x3fdd2016e8e9db5b, 0xbfec7e8e52233cf3, // 0.45508, -0.89045 + 0x3fdd3675caebf962, 0xbfec78d41fe4a267, // 0.45645, -0.88975 + 0x3fdd4cd02ba8609c, 0xbfec7315899eaad7, // 0.45781, -0.88905 + 0x3fdd632607ac9aa9, 0xbfec6d5290341eb2, // 0.45918, -0.88835 + 0x3fdd79775b86e389, 0xbfec678b3488739b, // 0.46054, -0.88764 + 0x3fdd8fc423c62a25, 0xbfec61bf777fcc48, // 0.4619, -0.88693 + 0x3fdda60c5cfa10d8, 0xbfec5bef59fef85a, // 0.46326, -0.88622 + 0x3fddbc5003b2edf8, 0xbfec561adceb743e, // 0.46462, -0.88551 + 0x3fddd28f1481cc58, 0xbfec5042012b6907, // 0.46598, -0.8848 + 0x3fdde8c98bf86bd6, 0xbfec4a64c7a5ac4c, // 0.46733, -0.88408 + 0x3fddfeff66a941de, 0xbfec44833141c004, // 0.46869, -0.88336 + 0x3fde1530a12779f4, 0xbfec3e9d3ee7d262, // 0.47004, -0.88264 + 0x3fde2b5d3806f63b, 0xbfec38b2f180bdb1, // 0.4714, -0.88192 + 0x3fde418527dc4ffa, 0xbfec32c449f60831, // 0.47275, -0.8812 + 0x3fde57a86d3cd824, 0xbfec2cd14931e3f1, // 0.4741, -0.88047 + 0x3fde6dc704be97e2, 0xbfec26d9f01f2eaf, // 0.47545, -0.87974 + 0x3fde83e0eaf85113, 0xbfec20de3fa971b0, // 0.4768, -0.87901 + 0x3fde99f61c817eda, 0xbfec1ade38bce19b, // 0.47815, -0.87828 + 0x3fdeb00695f25620, 0xbfec14d9dc465e58, // 0.47949, -0.87755 + 0x3fdec61253e3c61b, 0xbfec0ed12b3372e9, // 0.48084, -0.87681 + 0x3fdedc1952ef78d5, 0xbfec08c426725549, // 0.48218, -0.87607 + 0x3fdef21b8fafd3b5, 0xbfec02b2cef1e641, // 0.48353, -0.87533 + 0x3fdf081906bff7fd, 0xbfebfc9d25a1b147, // 0.48487, -0.87459 + 0x3fdf1e11b4bbc35c, 0xbfebf6832b71ec5b, // 0.48621, -0.87384 + 0x3fdf3405963fd068, 0xbfebf064e15377dd, // 0.48755, -0.87309 + 0x3fdf49f4a7e97729, 0xbfebea424837de6d, // 0.48889, -0.87235 + 0x3fdf5fdee656cda3, 0xbfebe41b611154c1, // 0.49023, -0.8716 + 0x3fdf75c44e26a852, 0xbfebddf02cd2b983, // 0.49156, -0.87084 + 0x3fdf8ba4dbf89aba, 0xbfebd7c0ac6f952a, // 0.4929, -0.87009 + 0x3fdfa1808c6cf7e0, 0xbfebd18ce0dc19d6, // 0.49423, -0.86933 + 0x3fdfb7575c24d2de, 0xbfebcb54cb0d2327, // 0.49557, -0.86857 + 0x3fdfcd2947c1ff57, 0xbfebc5186bf8361d, // 0.4969, -0.86781 + 0x3fdfe2f64be7120f, 0xbfebbed7c49380ea, // 0.49823, -0.86705 + 0x3fdff8be6537615e, 0xbfebb892d5d5dad5, // 0.49956, -0.86628 + 0x3fe00740c82b82e0, 0xbfebb249a0b6c40d, // 0.50089, -0.86551 + 0x3fe0121fe4f56d2c, 0xbfebabfc262e6586, // 0.50221, -0.86474 + 0x3fe01cfc874c3eb7, 0xbfeba5aa673590d2, // 0.50354, -0.86397 + 0x3fe027d6ad83287e, 0xbfeb9f5464c5bffc, // 0.50486, -0.8632 + 0x3fe032ae55edbd95, 0xbfeb98fa1fd9155e, // 0.50619, -0.86242 + 0x3fe03d837edff370, 0xbfeb929b996a5b7f, // 0.50751, -0.86165 + 0x3fe0485626ae221a, 0xbfeb8c38d27504e9, // 0.50883, -0.86087 + 0x3fe053264bad0483, 0xbfeb85d1cbf52c02, // 0.51015, -0.86009 + 0x3fe05df3ec31b8b6, 0xbfeb7f6686e792ea, // 0.51147, -0.8593 + 0x3fe068bf0691c028, 0xbfeb78f70449a34b, // 0.51279, -0.85852 + 0x3fe073879922ffed, 0xbfeb728345196e3e, // 0.5141, -0.85773 + 0x3fe07e4da23bc102, 0xbfeb6c0b4a55ac17, // 0.51542, -0.85694 + 0x3fe089112032b08c, 0xbfeb658f14fdbc47, // 0.51673, -0.85615 + 0x3fe093d2115ee018, 0xbfeb5f0ea611a532, // 0.51804, -0.85535 + 0x3fe09e907417c5e1, 0xbfeb5889fe921405, // 0.51936, -0.85456 + 0x3fe0a94c46b53d0b, 0xbfeb52011f805c92, // 0.52067, -0.85376 + 0x3fe0b405878f85ec, 0xbfeb4b7409de7925, // 0.52198, -0.85296 + 0x3fe0bebc34ff4646, 0xbfeb44e2beaf0a61, // 0.52328, -0.85216 + 0x3fe0c9704d5d898f, 0xbfeb3e4d3ef55712, // 0.52459, -0.85136 + 0x3fe0d421cf03c12b, 0xbfeb37b38bb54c09, // 0.5259, -0.85055 + 0x3fe0ded0b84bc4b5, 0xbfeb3115a5f37bf4, // 0.5272, -0.84974 + 0x3fe0e97d078fd23b, 0xbfeb2a738eb51f33, // 0.5285, -0.84893 + 0x3fe0f426bb2a8e7d, 0xbfeb23cd470013b4, // 0.5298, -0.84812 + 0x3fe0fecdd1770537, 0xbfeb1d22cfdadcc6, // 0.5311, -0.84731 + 0x3fe1097248d0a956, 0xbfeb16742a4ca2f5, // 0.5324, -0.84649 + 0x3fe114141f935545, 0xbfeb0fc1575d33db, // 0.5337, -0.84567 + 0x3fe11eb3541b4b22, 0xbfeb090a58150200, // 0.535, -0.84485 + 0x3fe1294fe4c5350a, 0xbfeb024f2d7d24a9, // 0.53629, -0.84403 + 0x3fe133e9cfee254e, 0xbfeafb8fd89f57b6, // 0.53759, -0.84321 + 0x3fe13e8113f396c1, 0xbfeaf4cc5a85fb73, // 0.53888, -0.84238 + 0x3fe14915af336ceb, 0xbfeaee04b43c1474, // 0.54017, -0.84155 + 0x3fe153a7a00bf453, 0xbfeae738e6cd4b67, // 0.54146, -0.84073 + 0x3fe15e36e4dbe2bc, 0xbfeae068f345ecef, // 0.54275, -0.83989 + 0x3fe168c37c025764, 0xbfead994dab2e979, // 0.54404, -0.83906 + 0x3fe1734d63dedb49, 0xbfead2bc9e21d511, // 0.54532, -0.83822 + 0x3fe17dd49ad16161, 0xbfeacbe03ea0e73b, // 0.54661, -0.83739 + 0x3fe188591f3a46e5, 0xbfeac4ffbd3efac8, // 0.54789, -0.83655 + 0x3fe192daef7a5386, 0xbfeabe1b1b0b8dac, // 0.54918, -0.83571 + 0x3fe19d5a09f2b9b8, 0xbfeab7325916c0d4, // 0.55046, -0.83486 + 0x3fe1a7d66d0516e6, 0xbfeab045787157ff, // 0.55174, -0.83402 + 0x3fe1b250171373be, 0xbfeaa9547a2cb98e, // 0.55302, -0.83317 + 0x3fe1bcc706804467, 0xbfeaa25f5f5aee60, // 0.55429, -0.83232 + 0x3fe1c73b39ae68c8, 0xbfea9b66290ea1a3, // 0.55557, -0.83147 + 0x3fe1d1acaf012cc2, 0xbfea9468d85b20ae, // 0.55685, -0.83062 + 0x3fe1dc1b64dc4872, 0xbfea8d676e545ad2, // 0.55812, -0.82976 + 0x3fe1e68759a3e074, 0xbfea8661ec0ee133, // 0.55939, -0.8289 + 0x3fe1f0f08bbc861b, 0xbfea7f58529fe69d, // 0.56066, -0.82805 + 0x3fe1fb56f98b37b8, 0xbfea784aa31d3f55, // 0.56193, -0.82718 + 0x3fe205baa17560d6, 0xbfea7138de9d60f5, // 0.5632, -0.82632 + 0x3fe2101b81e0da78, 0xbfea6a230637623b, // 0.56447, -0.82546 + 0x3fe21a799933eb58, 0xbfea63091b02fae2, // 0.56573, -0.82459 + 0x3fe224d4e5d5482e, 0xbfea5beb1e188375, // 0.567, -0.82372 + 0x3fe22f2d662c13e1, 0xbfea54c91090f524, // 0.56826, -0.82285 + 0x3fe23983189fdfd5, 0xbfea4da2f385e997, // 0.56952, -0.82198 + 0x3fe243d5fb98ac1f, 0xbfea4678c8119ac8, // 0.57078, -0.8211 + 0x3fe24e260d7ee7c9, 0xbfea3f4a8f4ee2d2, // 0.57204, -0.82023 + 0x3fe258734cbb7110, 0xbfea38184a593bc6, // 0.5733, -0.81935 + 0x3fe262bdb7b795a2, 0xbfea30e1fa4cbf81, // 0.57455, -0.81847 + 0x3fe26d054cdd12df, 0xbfea29a7a0462782, // 0.57581, -0.81758 + 0x3fe2774a0a961612, 0xbfea22693d62ccb9, // 0.57706, -0.8167 + 0x3fe2818bef4d3cba, 0xbfea1b26d2c0a75e, // 0.57831, -0.81581 + 0x3fe28bcaf96d94ba, 0xbfea13e0617e4ec7, // 0.57956, -0.81493 + 0x3fe2960727629ca8, 0xbfea0c95eabaf937, // 0.58081, -0.81404 + 0x3fe2a040779843fb, 0xbfea05476f967bb5, // 0.58206, -0.81314 + 0x3fe2aa76e87aeb58, 0xbfe9fdf4f13149de, // 0.58331, -0.81225 + 0x3fe2b4aa787764c4, 0xbfe9f69e70ac75bc, // 0.58455, -0.81135 + 0x3fe2bedb25faf3ea, 0xbfe9ef43ef29af94, // 0.5858, -0.81046 + 0x3fe2c908ef734e57, 0xbfe9e7e56dcb45bd, // 0.58704, -0.80956 + 0x3fe2d333d34e9bb7, 0xbfe9e082edb42472, // 0.58828, -0.80866 + 0x3fe2dd5bcffb7616, 0xbfe9d91c7007d5a6, // 0.58952, -0.80775 + 0x3fe2e780e3e8ea16, 0xbfe9d1b1f5ea80d6, // 0.59076, -0.80685 + 0x3fe2f1a30d86773a, 0xbfe9ca438080eadb, // 0.592, -0.80594 + 0x3fe2fbc24b441015, 0xbfe9c2d110f075c3, // 0.59323, -0.80503 + 0x3fe305de9b921a94, 0xbfe9bb5aa85f2098, // 0.59447, -0.80412 + 0x3fe30ff7fce17035, 0xbfe9b3e047f38741, // 0.5957, -0.80321 + 0x3fe31a0e6da35e44, 0xbfe9ac61f0d4e247, // 0.59693, -0.80229 + 0x3fe32421ec49a620, 0xbfe9a4dfa42b06b2, // 0.59816, -0.80138 + 0x3fe32e3277467d6b, 0xbfe99d59631e65d5, // 0.59939, -0.80046 + 0x3fe338400d0c8e57, 0xbfe995cf2ed80d22, // 0.60062, -0.79954 + 0x3fe3424aac0ef7d6, 0xbfe98e410881a600, // 0.60184, -0.79861 + 0x3fe34c5252c14de1, 0xbfe986aef1457594, // 0.60307, -0.79769 + 0x3fe35656ff9799ae, 0xbfe97f18ea4e5c9e, // 0.60429, -0.79676 + 0x3fe36058b10659f3, 0xbfe9777ef4c7d742, // 0.60551, -0.79584 + 0x3fe36a576582831b, 0xbfe96fe111ddfce0, // 0.60673, -0.79491 + 0x3fe374531b817f8d, 0xbfe9683f42bd7fe1, // 0.60795, -0.79398 + 0x3fe37e4bd1792fe2, 0xbfe960998893ad8c, // 0.60917, -0.79304 + 0x3fe3884185dfeb22, 0xbfe958efe48e6dd7, // 0.61038, -0.79211 + 0x3fe39234372c7f04, 0xbfe9514257dc4335, // 0.6116, -0.79117 + 0x3fe39c23e3d63029, 0xbfe94990e3ac4a6c, // 0.61281, -0.79023 + 0x3fe3a6108a54ba58, 0xbfe941db892e3a65, // 0.61402, -0.78929 + 0x3fe3affa292050b9, 0xbfe93a22499263fc, // 0.61523, -0.78835 + 0x3fe3b9e0beb19e18, 0xbfe932652609b1cf, // 0.61644, -0.7874 + 0x3fe3c3c44981c517, 0xbfe92aa41fc5a815, // 0.61765, -0.78646 + 0x3fe3cda4c80a6076, 0xbfe922df37f8646a, // 0.61885, -0.78551 + 0x3fe3d78238c58343, 0xbfe91b166fd49da2, // 0.62006, -0.78456 + 0x3fe3e15c9a2db922, 0xbfe91349c88da398, // 0.62126, -0.7836 + 0x3fe3eb33eabe0680, 0xbfe90b7943575efe, // 0.62246, -0.78265 + 0x3fe3f50828f1e8d2, 0xbfe903a4e1665133, // 0.62366, -0.78169 + 0x3fe3fed9534556d4, 0xbfe8fbcca3ef940d, // 0.62486, -0.78074 + 0x3fe408a76834c0c0, 0xbfe8f3f08c28d9ac, // 0.62606, -0.77978 + 0x3fe41272663d108c, 0xbfe8ec109b486c49, // 0.62725, -0.77882 + 0x3fe41c3a4bdbaa26, 0xbfe8e42cd2852e0a, // 0.62845, -0.77785 + 0x3fe425ff178e6bb1, 0xbfe8dc45331698cc, // 0.62964, -0.77689 + 0x3fe42fc0c7d3adbb, 0xbfe8d459be34bdfa, // 0.63083, -0.77592 + 0x3fe4397f5b2a4380, 0xbfe8cc6a75184655, // 0.63202, -0.77495 + 0x3fe4433ad0117b1d, 0xbfe8c47758fa71cb, // 0.63321, -0.77398 + 0x3fe44cf325091dd6, 0xbfe8bc806b151741, // 0.63439, -0.77301 + 0x3fe456a858917046, 0xbfe8b485aca2a468, // 0.63558, -0.77204 + 0x3fe4605a692b32a2, 0xbfe8ac871ede1d88, // 0.63676, -0.77106 + 0x3fe46a095557a0f1, 0xbfe8a484c3031d50, // 0.63794, -0.77008 + 0x3fe473b51b987347, 0xbfe89c7e9a4dd4ab, // 0.63912, -0.7691 + 0x3fe47d5dba6fde01, 0xbfe89474a5fb0a84, // 0.6403, -0.76812 + 0x3fe48703306091fe, 0xbfe88c66e7481ba1, // 0.64148, -0.76714 + 0x3fe490a57bedbcdf, 0xbfe884555f72fa6b, // 0.64266, -0.76615 + 0x3fe49a449b9b0938, 0xbfe87c400fba2ebf, // 0.64383, -0.76517 + 0x3fe4a3e08dec9ed6, 0xbfe87426f95cd5bd, // 0.645, -0.76418 + 0x3fe4ad79516722f0, 0xbfe86c0a1d9aa195, // 0.64618, -0.76319 + 0x3fe4b70ee48fb869, 0xbfe863e97db3d95a, // 0.64735, -0.7622 + 0x3fe4c0a145ec0004, 0xbfe85bc51ae958cc, // 0.64851, -0.7612 + 0x3fe4ca30740218a3, 0xbfe8539cf67c9029, // 0.64968, -0.76021 + 0x3fe4d3bc6d589f80, 0xbfe84b7111af83f9, // 0.65085, -0.75921 + 0x3fe4dd453076b064, 0xbfe843416dc4cce2, // 0.65201, -0.75821 + 0x3fe4e6cabbe3e5e9, 0xbfe83b0e0bff976e, // 0.65317, -0.75721 + 0x3fe4f04d0e2859aa, 0xbfe832d6eda3a3e0, // 0.65433, -0.75621 + 0x3fe4f9cc25cca486, 0xbfe82a9c13f545ff, // 0.65549, -0.7552 + 0x3fe503480159ded2, 0xbfe8225d803964e5, // 0.65665, -0.75419 + 0x3fe50cc09f59a09b, 0xbfe81a1b33b57acc, // 0.65781, -0.75319 + 0x3fe51635fe5601d7, 0xbfe811d52faf94dc, // 0.65896, -0.75218 + 0x3fe51fa81cd99aa6, 0xbfe8098b756e52fa, // 0.66011, -0.75117 + 0x3fe52916f96f8388, 0xbfe8013e0638e795, // 0.66127, -0.75015 + 0x3fe5328292a35596, 0xbfe7f8ece3571771, // 0.66242, -0.74914 + 0x3fe53beae7012abe, 0xbfe7f0980e113978, // 0.66356, -0.74812 + 0x3fe5454ff5159dfb, 0xbfe7e83f87b03686, // 0.66471, -0.7471 + 0x3fe54eb1bb6dcb8f, 0xbfe7dfe3517d8937, // 0.66586, -0.74608 + 0x3fe5581038975137, 0xbfe7d7836cc33db2, // 0.667, -0.74506 + 0x3fe5616b6b204e6e, 0xbfe7cf1fdacbf179, // 0.66814, -0.74403 + 0x3fe56ac35197649e, 0xbfe7c6b89ce2d333, // 0.66928, -0.74301 + 0x3fe57417ea8bb75c, 0xbfe7be4db453a27c, // 0.67042, -0.74198 + 0x3fe57d69348cec9f, 0xbfe7b5df226aafb0, // 0.67156, -0.74095 + 0x3fe586b72e2b2cfd, 0xbfe7ad6ce874dbb6, // 0.67269, -0.73992 + 0x3fe59001d5f723df, 0xbfe7a4f707bf97d2, // 0.67383, -0.73889 + 0x3fe599492a81ffbc, 0xbfe79c7d8198e56e, // 0.67496, -0.73785 + 0x3fe5a28d2a5d7250, 0xbfe79400574f55e4, // 0.67609, -0.73682 + 0x3fe5abcdd41bb0d8, 0xbfe78b7f8a320a52, // 0.67722, -0.73578 + 0x3fe5b50b264f7448, 0xbfe782fb1b90b35b, // 0.67835, -0.73474 + 0x3fe5be451f8bf980, 0xbfe77a730cbb9100, // 0.67948, -0.7337 + 0x3fe5c77bbe65018c, 0xbfe771e75f037261, // 0.6806, -0.73265 + 0x3fe5d0af016ed1d4, 0xbfe7695813b9b594, // 0.68172, -0.73161 + 0x3fe5d9dee73e345c, 0xbfe760c52c304764, // 0.68285, -0.73056 + 0x3fe5e30b6e6877f3, 0xbfe7582ea9b9a329, // 0.68397, -0.72951 + 0x3fe5ec3495837074, 0xbfe74f948da8d28d, // 0.68508, -0.72846 + 0x3fe5f55a5b2576f8, 0xbfe746f6d9516d59, // 0.6862, -0.72741 + 0x3fe5fe7cbde56a0f, 0xbfe73e558e079942, // 0.68732, -0.72636 + 0x3fe6079bbc5aadfa, 0xbfe735b0ad2009b2, // 0.68843, -0.7253 + 0x3fe610b7551d2cde, 0xbfe72d0837efff97, // 0.68954, -0.72425 + 0x3fe619cf86c55702, 0xbfe7245c2fcd492a, // 0.69065, -0.72319 + 0x3fe622e44fec22ff, 0xbfe71bac960e41bf, // 0.69176, -0.72213 + 0x3fe62bf5af2b0dfd, 0xbfe712f96c09d18d, // 0.69287, -0.72107 + 0x3fe63503a31c1be8, 0xbfe70a42b3176d7a, // 0.69397, -0.72 + 0x3fe63e0e2a59d7aa, 0xbfe701886c8f16e6, // 0.69508, -0.71894 + 0x3fe64715437f535b, 0xbfe6f8ca99c95b75, // 0.69618, -0.71787 + 0x3fe65018ed28287f, 0xbfe6f0093c1f54de, // 0.69728, -0.7168 + 0x3fe6591925f0783e, 0xbfe6e74454eaa8ae, // 0.69838, -0.71573 + 0x3fe66215ec74eb91, 0xbfe6de7be585881d, // 0.69947, -0.71466 + 0x3fe66b0f3f52b386, 0xbfe6d5afef4aafcc, // 0.70057, -0.71358 + 0x3fe674051d27896c, 0xbfe6cce07395679f, // 0.70166, -0.71251 + 0x3fe67cf78491af10, 0xbfe6c40d73c18275, // 0.70275, -0.71143 + 0x3fe685e6742feeef, 0xbfe6bb36f12b5e06, // 0.70385, -0.71035 + 0x3fe68ed1eaa19c71, 0xbfe6b25ced2fe29c, // 0.70493, -0.70927 + 0x3fe697b9e686941c, 0xbfe6a97f692c82ea, // 0.70602, -0.70819 + 0x3fe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // 0.70711, -0.70711 + 0x3fe6a97f692c82ea, 0xbfe697b9e686941c, // 0.70819, -0.70602 + 0x3fe6b25ced2fe29c, 0xbfe68ed1eaa19c71, // 0.70927, -0.70493 + 0x3fe6bb36f12b5e06, 0xbfe685e6742feeef, // 0.71035, -0.70385 + 0x3fe6c40d73c18275, 0xbfe67cf78491af10, // 0.71143, -0.70275 + 0x3fe6cce07395679f, 0xbfe674051d27896c, // 0.71251, -0.70166 + 0x3fe6d5afef4aafcc, 0xbfe66b0f3f52b386, // 0.71358, -0.70057 + 0x3fe6de7be585881d, 0xbfe66215ec74eb91, // 0.71466, -0.69947 + 0x3fe6e74454eaa8ae, 0xbfe6591925f0783e, // 0.71573, -0.69838 + 0x3fe6f0093c1f54de, 0xbfe65018ed28287f, // 0.7168, -0.69728 + 0x3fe6f8ca99c95b75, 0xbfe64715437f535b, // 0.71787, -0.69618 + 0x3fe701886c8f16e6, 0xbfe63e0e2a59d7aa, // 0.71894, -0.69508 + 0x3fe70a42b3176d7a, 0xbfe63503a31c1be8, // 0.72, -0.69397 + 0x3fe712f96c09d18d, 0xbfe62bf5af2b0dfd, // 0.72107, -0.69287 + 0x3fe71bac960e41bf, 0xbfe622e44fec22ff, // 0.72213, -0.69176 + 0x3fe7245c2fcd492a, 0xbfe619cf86c55702, // 0.72319, -0.69065 + 0x3fe72d0837efff97, 0xbfe610b7551d2cde, // 0.72425, -0.68954 + 0x3fe735b0ad2009b2, 0xbfe6079bbc5aadfa, // 0.7253, -0.68843 + 0x3fe73e558e079942, 0xbfe5fe7cbde56a0f, // 0.72636, -0.68732 + 0x3fe746f6d9516d59, 0xbfe5f55a5b2576f8, // 0.72741, -0.6862 + 0x3fe74f948da8d28d, 0xbfe5ec3495837074, // 0.72846, -0.68508 + 0x3fe7582ea9b9a329, 0xbfe5e30b6e6877f3, // 0.72951, -0.68397 + 0x3fe760c52c304764, 0xbfe5d9dee73e345c, // 0.73056, -0.68285 + 0x3fe7695813b9b594, 0xbfe5d0af016ed1d4, // 0.73161, -0.68172 + 0x3fe771e75f037261, 0xbfe5c77bbe65018c, // 0.73265, -0.6806 + 0x3fe77a730cbb9100, 0xbfe5be451f8bf980, // 0.7337, -0.67948 + 0x3fe782fb1b90b35b, 0xbfe5b50b264f7448, // 0.73474, -0.67835 + 0x3fe78b7f8a320a52, 0xbfe5abcdd41bb0d8, // 0.73578, -0.67722 + 0x3fe79400574f55e4, 0xbfe5a28d2a5d7250, // 0.73682, -0.67609 + 0x3fe79c7d8198e56e, 0xbfe599492a81ffbc, // 0.73785, -0.67496 + 0x3fe7a4f707bf97d2, 0xbfe59001d5f723df, // 0.73889, -0.67383 + 0x3fe7ad6ce874dbb6, 0xbfe586b72e2b2cfd, // 0.73992, -0.67269 + 0x3fe7b5df226aafb0, 0xbfe57d69348cec9f, // 0.74095, -0.67156 + 0x3fe7be4db453a27c, 0xbfe57417ea8bb75c, // 0.74198, -0.67042 + 0x3fe7c6b89ce2d333, 0xbfe56ac35197649e, // 0.74301, -0.66928 + 0x3fe7cf1fdacbf179, 0xbfe5616b6b204e6e, // 0.74403, -0.66814 + 0x3fe7d7836cc33db2, 0xbfe5581038975137, // 0.74506, -0.667 + 0x3fe7dfe3517d8937, 0xbfe54eb1bb6dcb8f, // 0.74608, -0.66586 + 0x3fe7e83f87b03686, 0xbfe5454ff5159dfb, // 0.7471, -0.66471 + 0x3fe7f0980e113978, 0xbfe53beae7012abe, // 0.74812, -0.66356 + 0x3fe7f8ece3571771, 0xbfe5328292a35596, // 0.74914, -0.66242 + 0x3fe8013e0638e795, 0xbfe52916f96f8388, // 0.75015, -0.66127 + 0x3fe8098b756e52fa, 0xbfe51fa81cd99aa6, // 0.75117, -0.66011 + 0x3fe811d52faf94dc, 0xbfe51635fe5601d7, // 0.75218, -0.65896 + 0x3fe81a1b33b57acc, 0xbfe50cc09f59a09b, // 0.75319, -0.65781 + 0x3fe8225d803964e5, 0xbfe503480159ded2, // 0.75419, -0.65665 + 0x3fe82a9c13f545ff, 0xbfe4f9cc25cca486, // 0.7552, -0.65549 + 0x3fe832d6eda3a3e0, 0xbfe4f04d0e2859aa, // 0.75621, -0.65433 + 0x3fe83b0e0bff976e, 0xbfe4e6cabbe3e5e9, // 0.75721, -0.65317 + 0x3fe843416dc4cce2, 0xbfe4dd453076b064, // 0.75821, -0.65201 + 0x3fe84b7111af83f9, 0xbfe4d3bc6d589f80, // 0.75921, -0.65085 + 0x3fe8539cf67c9029, 0xbfe4ca30740218a3, // 0.76021, -0.64968 + 0x3fe85bc51ae958cc, 0xbfe4c0a145ec0004, // 0.7612, -0.64851 + 0x3fe863e97db3d95a, 0xbfe4b70ee48fb869, // 0.7622, -0.64735 + 0x3fe86c0a1d9aa195, 0xbfe4ad79516722f0, // 0.76319, -0.64618 + 0x3fe87426f95cd5bd, 0xbfe4a3e08dec9ed6, // 0.76418, -0.645 + 0x3fe87c400fba2ebf, 0xbfe49a449b9b0938, // 0.76517, -0.64383 + 0x3fe884555f72fa6b, 0xbfe490a57bedbcdf, // 0.76615, -0.64266 + 0x3fe88c66e7481ba1, 0xbfe48703306091fe, // 0.76714, -0.64148 + 0x3fe89474a5fb0a84, 0xbfe47d5dba6fde01, // 0.76812, -0.6403 + 0x3fe89c7e9a4dd4ab, 0xbfe473b51b987347, // 0.7691, -0.63912 + 0x3fe8a484c3031d50, 0xbfe46a095557a0f1, // 0.77008, -0.63794 + 0x3fe8ac871ede1d88, 0xbfe4605a692b32a2, // 0.77106, -0.63676 + 0x3fe8b485aca2a468, 0xbfe456a858917046, // 0.77204, -0.63558 + 0x3fe8bc806b151741, 0xbfe44cf325091dd6, // 0.77301, -0.63439 + 0x3fe8c47758fa71cb, 0xbfe4433ad0117b1d, // 0.77398, -0.63321 + 0x3fe8cc6a75184655, 0xbfe4397f5b2a4380, // 0.77495, -0.63202 + 0x3fe8d459be34bdfa, 0xbfe42fc0c7d3adbb, // 0.77592, -0.63083 + 0x3fe8dc45331698cc, 0xbfe425ff178e6bb1, // 0.77689, -0.62964 + 0x3fe8e42cd2852e0a, 0xbfe41c3a4bdbaa26, // 0.77785, -0.62845 + 0x3fe8ec109b486c49, 0xbfe41272663d108c, // 0.77882, -0.62725 + 0x3fe8f3f08c28d9ac, 0xbfe408a76834c0c0, // 0.77978, -0.62606 + 0x3fe8fbcca3ef940d, 0xbfe3fed9534556d4, // 0.78074, -0.62486 + 0x3fe903a4e1665133, 0xbfe3f50828f1e8d2, // 0.78169, -0.62366 + 0x3fe90b7943575efe, 0xbfe3eb33eabe0680, // 0.78265, -0.62246 + 0x3fe91349c88da398, 0xbfe3e15c9a2db922, // 0.7836, -0.62126 + 0x3fe91b166fd49da2, 0xbfe3d78238c58343, // 0.78456, -0.62006 + 0x3fe922df37f8646a, 0xbfe3cda4c80a6076, // 0.78551, -0.61885 + 0x3fe92aa41fc5a815, 0xbfe3c3c44981c517, // 0.78646, -0.61765 + 0x3fe932652609b1cf, 0xbfe3b9e0beb19e18, // 0.7874, -0.61644 + 0x3fe93a22499263fc, 0xbfe3affa292050b9, // 0.78835, -0.61523 + 0x3fe941db892e3a65, 0xbfe3a6108a54ba58, // 0.78929, -0.61402 + 0x3fe94990e3ac4a6c, 0xbfe39c23e3d63029, // 0.79023, -0.61281 + 0x3fe9514257dc4335, 0xbfe39234372c7f04, // 0.79117, -0.6116 + 0x3fe958efe48e6dd7, 0xbfe3884185dfeb22, // 0.79211, -0.61038 + 0x3fe960998893ad8c, 0xbfe37e4bd1792fe2, // 0.79304, -0.60917 + 0x3fe9683f42bd7fe1, 0xbfe374531b817f8d, // 0.79398, -0.60795 + 0x3fe96fe111ddfce0, 0xbfe36a576582831b, // 0.79491, -0.60673 + 0x3fe9777ef4c7d742, 0xbfe36058b10659f3, // 0.79584, -0.60551 + 0x3fe97f18ea4e5c9e, 0xbfe35656ff9799ae, // 0.79676, -0.60429 + 0x3fe986aef1457594, 0xbfe34c5252c14de1, // 0.79769, -0.60307 + 0x3fe98e410881a600, 0xbfe3424aac0ef7d6, // 0.79861, -0.60184 + 0x3fe995cf2ed80d22, 0xbfe338400d0c8e57, // 0.79954, -0.60062 + 0x3fe99d59631e65d5, 0xbfe32e3277467d6b, // 0.80046, -0.59939 + 0x3fe9a4dfa42b06b2, 0xbfe32421ec49a620, // 0.80138, -0.59816 + 0x3fe9ac61f0d4e247, 0xbfe31a0e6da35e44, // 0.80229, -0.59693 + 0x3fe9b3e047f38741, 0xbfe30ff7fce17035, // 0.80321, -0.5957 + 0x3fe9bb5aa85f2098, 0xbfe305de9b921a94, // 0.80412, -0.59447 + 0x3fe9c2d110f075c3, 0xbfe2fbc24b441015, // 0.80503, -0.59323 + 0x3fe9ca438080eadb, 0xbfe2f1a30d86773a, // 0.80594, -0.592 + 0x3fe9d1b1f5ea80d6, 0xbfe2e780e3e8ea16, // 0.80685, -0.59076 + 0x3fe9d91c7007d5a6, 0xbfe2dd5bcffb7616, // 0.80775, -0.58952 + 0x3fe9e082edb42472, 0xbfe2d333d34e9bb7, // 0.80866, -0.58828 + 0x3fe9e7e56dcb45bd, 0xbfe2c908ef734e57, // 0.80956, -0.58704 + 0x3fe9ef43ef29af94, 0xbfe2bedb25faf3ea, // 0.81046, -0.5858 + 0x3fe9f69e70ac75bc, 0xbfe2b4aa787764c4, // 0.81135, -0.58455 + 0x3fe9fdf4f13149de, 0xbfe2aa76e87aeb58, // 0.81225, -0.58331 + 0x3fea05476f967bb5, 0xbfe2a040779843fb, // 0.81314, -0.58206 + 0x3fea0c95eabaf937, 0xbfe2960727629ca8, // 0.81404, -0.58081 + 0x3fea13e0617e4ec7, 0xbfe28bcaf96d94ba, // 0.81493, -0.57956 + 0x3fea1b26d2c0a75e, 0xbfe2818bef4d3cba, // 0.81581, -0.57831 + 0x3fea22693d62ccb9, 0xbfe2774a0a961612, // 0.8167, -0.57706 + 0x3fea29a7a0462782, 0xbfe26d054cdd12df, // 0.81758, -0.57581 + 0x3fea30e1fa4cbf81, 0xbfe262bdb7b795a2, // 0.81847, -0.57455 + 0x3fea38184a593bc6, 0xbfe258734cbb7110, // 0.81935, -0.5733 + 0x3fea3f4a8f4ee2d2, 0xbfe24e260d7ee7c9, // 0.82023, -0.57204 + 0x3fea4678c8119ac8, 0xbfe243d5fb98ac1f, // 0.8211, -0.57078 + 0x3fea4da2f385e997, 0xbfe23983189fdfd5, // 0.82198, -0.56952 + 0x3fea54c91090f524, 0xbfe22f2d662c13e1, // 0.82285, -0.56826 + 0x3fea5beb1e188375, 0xbfe224d4e5d5482e, // 0.82372, -0.567 + 0x3fea63091b02fae2, 0xbfe21a799933eb58, // 0.82459, -0.56573 + 0x3fea6a230637623b, 0xbfe2101b81e0da78, // 0.82546, -0.56447 + 0x3fea7138de9d60f5, 0xbfe205baa17560d6, // 0.82632, -0.5632 + 0x3fea784aa31d3f55, 0xbfe1fb56f98b37b8, // 0.82718, -0.56193 + 0x3fea7f58529fe69d, 0xbfe1f0f08bbc861b, // 0.82805, -0.56066 + 0x3fea8661ec0ee133, 0xbfe1e68759a3e074, // 0.8289, -0.55939 + 0x3fea8d676e545ad2, 0xbfe1dc1b64dc4872, // 0.82976, -0.55812 + 0x3fea9468d85b20ae, 0xbfe1d1acaf012cc2, // 0.83062, -0.55685 + 0x3fea9b66290ea1a3, 0xbfe1c73b39ae68c8, // 0.83147, -0.55557 + 0x3feaa25f5f5aee60, 0xbfe1bcc706804467, // 0.83232, -0.55429 + 0x3feaa9547a2cb98e, 0xbfe1b250171373be, // 0.83317, -0.55302 + 0x3feab045787157ff, 0xbfe1a7d66d0516e6, // 0.83402, -0.55174 + 0x3feab7325916c0d4, 0xbfe19d5a09f2b9b8, // 0.83486, -0.55046 + 0x3feabe1b1b0b8dac, 0xbfe192daef7a5386, // 0.83571, -0.54918 + 0x3feac4ffbd3efac8, 0xbfe188591f3a46e5, // 0.83655, -0.54789 + 0x3feacbe03ea0e73b, 0xbfe17dd49ad16161, // 0.83739, -0.54661 + 0x3fead2bc9e21d511, 0xbfe1734d63dedb49, // 0.83822, -0.54532 + 0x3fead994dab2e979, 0xbfe168c37c025764, // 0.83906, -0.54404 + 0x3feae068f345ecef, 0xbfe15e36e4dbe2bc, // 0.83989, -0.54275 + 0x3feae738e6cd4b67, 0xbfe153a7a00bf453, // 0.84073, -0.54146 + 0x3feaee04b43c1474, 0xbfe14915af336ceb, // 0.84155, -0.54017 + 0x3feaf4cc5a85fb73, 0xbfe13e8113f396c1, // 0.84238, -0.53888 + 0x3feafb8fd89f57b6, 0xbfe133e9cfee254e, // 0.84321, -0.53759 + 0x3feb024f2d7d24a9, 0xbfe1294fe4c5350a, // 0.84403, -0.53629 + 0x3feb090a58150200, 0xbfe11eb3541b4b22, // 0.84485, -0.535 + 0x3feb0fc1575d33db, 0xbfe114141f935545, // 0.84567, -0.5337 + 0x3feb16742a4ca2f5, 0xbfe1097248d0a956, // 0.84649, -0.5324 + 0x3feb1d22cfdadcc6, 0xbfe0fecdd1770537, // 0.84731, -0.5311 + 0x3feb23cd470013b4, 0xbfe0f426bb2a8e7d, // 0.84812, -0.5298 + 0x3feb2a738eb51f33, 0xbfe0e97d078fd23b, // 0.84893, -0.5285 + 0x3feb3115a5f37bf4, 0xbfe0ded0b84bc4b5, // 0.84974, -0.5272 + 0x3feb37b38bb54c09, 0xbfe0d421cf03c12b, // 0.85055, -0.5259 + 0x3feb3e4d3ef55712, 0xbfe0c9704d5d898f, // 0.85136, -0.52459 + 0x3feb44e2beaf0a61, 0xbfe0bebc34ff4646, // 0.85216, -0.52328 + 0x3feb4b7409de7925, 0xbfe0b405878f85ec, // 0.85296, -0.52198 + 0x3feb52011f805c92, 0xbfe0a94c46b53d0b, // 0.85376, -0.52067 + 0x3feb5889fe921405, 0xbfe09e907417c5e1, // 0.85456, -0.51936 + 0x3feb5f0ea611a532, 0xbfe093d2115ee018, // 0.85535, -0.51804 + 0x3feb658f14fdbc47, 0xbfe089112032b08c, // 0.85615, -0.51673 + 0x3feb6c0b4a55ac17, 0xbfe07e4da23bc102, // 0.85694, -0.51542 + 0x3feb728345196e3e, 0xbfe073879922ffed, // 0.85773, -0.5141 + 0x3feb78f70449a34b, 0xbfe068bf0691c028, // 0.85852, -0.51279 + 0x3feb7f6686e792ea, 0xbfe05df3ec31b8b6, // 0.8593, -0.51147 + 0x3feb85d1cbf52c02, 0xbfe053264bad0483, // 0.86009, -0.51015 + 0x3feb8c38d27504e9, 0xbfe0485626ae221a, // 0.86087, -0.50883 + 0x3feb929b996a5b7f, 0xbfe03d837edff370, // 0.86165, -0.50751 + 0x3feb98fa1fd9155e, 0xbfe032ae55edbd95, // 0.86242, -0.50619 + 0x3feb9f5464c5bffc, 0xbfe027d6ad83287e, // 0.8632, -0.50486 + 0x3feba5aa673590d2, 0xbfe01cfc874c3eb7, // 0.86397, -0.50354 + 0x3febabfc262e6586, 0xbfe0121fe4f56d2c, // 0.86474, -0.50221 + 0x3febb249a0b6c40d, 0xbfe00740c82b82e0, // 0.86551, -0.50089 + 0x3febb892d5d5dad5, 0xbfdff8be6537615e, // 0.86628, -0.49956 + 0x3febbed7c49380ea, 0xbfdfe2f64be7120f, // 0.86705, -0.49823 + 0x3febc5186bf8361d, 0xbfdfcd2947c1ff57, // 0.86781, -0.4969 + 0x3febcb54cb0d2327, 0xbfdfb7575c24d2de, // 0.86857, -0.49557 + 0x3febd18ce0dc19d6, 0xbfdfa1808c6cf7e0, // 0.86933, -0.49423 + 0x3febd7c0ac6f952a, 0xbfdf8ba4dbf89aba, // 0.87009, -0.4929 + 0x3febddf02cd2b983, 0xbfdf75c44e26a852, // 0.87084, -0.49156 + 0x3febe41b611154c1, 0xbfdf5fdee656cda3, // 0.8716, -0.49023 + 0x3febea424837de6d, 0xbfdf49f4a7e97729, // 0.87235, -0.48889 + 0x3febf064e15377dd, 0xbfdf3405963fd068, // 0.87309, -0.48755 + 0x3febf6832b71ec5b, 0xbfdf1e11b4bbc35c, // 0.87384, -0.48621 + 0x3febfc9d25a1b147, 0xbfdf081906bff7fd, // 0.87459, -0.48487 + 0x3fec02b2cef1e641, 0xbfdef21b8fafd3b5, // 0.87533, -0.48353 + 0x3fec08c426725549, 0xbfdedc1952ef78d5, // 0.87607, -0.48218 + 0x3fec0ed12b3372e9, 0xbfdec61253e3c61b, // 0.87681, -0.48084 + 0x3fec14d9dc465e58, 0xbfdeb00695f25620, // 0.87755, -0.47949 + 0x3fec1ade38bce19b, 0xbfde99f61c817eda, // 0.87828, -0.47815 + 0x3fec20de3fa971b0, 0xbfde83e0eaf85113, // 0.87901, -0.4768 + 0x3fec26d9f01f2eaf, 0xbfde6dc704be97e2, // 0.87974, -0.47545 + 0x3fec2cd14931e3f1, 0xbfde57a86d3cd824, // 0.88047, -0.4741 + 0x3fec32c449f60831, 0xbfde418527dc4ffa, // 0.8812, -0.47275 + 0x3fec38b2f180bdb1, 0xbfde2b5d3806f63b, // 0.88192, -0.4714 + 0x3fec3e9d3ee7d262, 0xbfde1530a12779f4, // 0.88264, -0.47004 + 0x3fec44833141c004, 0xbfddfeff66a941de, // 0.88336, -0.46869 + 0x3fec4a64c7a5ac4c, 0xbfdde8c98bf86bd6, // 0.88408, -0.46733 + 0x3fec5042012b6907, 0xbfddd28f1481cc58, // 0.8848, -0.46598 + 0x3fec561adceb743e, 0xbfddbc5003b2edf8, // 0.88551, -0.46462 + 0x3fec5bef59fef85a, 0xbfdda60c5cfa10d8, // 0.88622, -0.46326 + 0x3fec61bf777fcc48, 0xbfdd8fc423c62a25, // 0.88693, -0.4619 + 0x3fec678b3488739b, 0xbfdd79775b86e389, // 0.88764, -0.46054 + 0x3fec6d5290341eb2, 0xbfdd632607ac9aa9, // 0.88835, -0.45918 + 0x3fec7315899eaad7, 0xbfdd4cd02ba8609c, // 0.88905, -0.45781 + 0x3fec78d41fe4a267, 0xbfdd3675caebf962, // 0.88975, -0.45645 + 0x3fec7e8e52233cf3, 0xbfdd2016e8e9db5b, // 0.89045, -0.45508 + 0x3fec84441f785f61, 0xbfdd09b389152ec1, // 0.89115, -0.45372 + 0x3fec89f587029c13, 0xbfdcf34baee1cd21, // 0.89184, -0.45235 + 0x3fec8fa287e13305, 0xbfdcdcdf5dc440ce, // 0.89253, -0.45098 + 0x3fec954b213411f5, 0xbfdcc66e9931c45d, // 0.89322, -0.44961 + 0x3fec9aef521bd480, 0xbfdcaff964a0421d, // 0.89391, -0.44824 + 0x3feca08f19b9c449, 0xbfdc997fc3865388, // 0.8946, -0.44687 + 0x3feca62a772fd919, 0xbfdc8301b95b40c2, // 0.89528, -0.4455 + 0x3fecabc169a0b901, 0xbfdc6c7f4997000a, // 0.89597, -0.44412 + 0x3fecb153f02fb87d, 0xbfdc55f877b23537, // 0.89665, -0.44275 + 0x3fecb6e20a00da99, 0xbfdc3f6d47263129, // 0.89732, -0.44137 + 0x3fecbc6bb638d10b, 0xbfdc28ddbb6cf145, // 0.898, -0.43999 + 0x3fecc1f0f3fcfc5c, 0xbfdc1249d8011ee7, // 0.89867, -0.43862 + 0x3fecc771c2736c09, 0xbfdbfbb1a05e0edc, // 0.89935, -0.43724 + 0x3fecccee20c2de9f, 0xbfdbe51517ffc0d9, // 0.90002, -0.43586 + 0x3fecd2660e12c1e6, 0xbfdbce744262deee, // 0.90068, -0.43448 + 0x3fecd7d9898b32f6, 0xbfdbb7cf2304bd01, // 0.90135, -0.43309 + 0x3fecdd489254fe65, 0xbfdba125bd63583e, // 0.90201, -0.43171 + 0x3fece2b32799a060, 0xbfdb8a7814fd5693, // 0.90267, -0.43033 + 0x3fece819488344ce, 0xbfdb73c62d520624, // 0.90333, -0.42894 + 0x3feced7af43cc773, 0xbfdb5d1009e15cc0, // 0.90399, -0.42756 + 0x3fecf2d829f1b40e, 0xbfdb4655ae2bf757, // 0.90464, -0.42617 + 0x3fecf830e8ce467b, 0xbfdb2f971db31972, // 0.9053, -0.42478 + 0x3fecfd852fff6ad4, 0xbfdb18d45bf8aca6, // 0.90595, -0.42339 + 0x3fed02d4feb2bd92, 0xbfdb020d6c7f4009, // 0.9066, -0.422 + 0x3fed082054168bac, 0xbfdaeb4252ca07ab, // 0.90724, -0.42061 + 0x3fed0d672f59d2b9, 0xbfdad473125cdc08, // 0.90789, -0.41922 + 0x3fed12a98fac410c, 0xbfdabd9faebc3980, // 0.90853, -0.41782 + 0x3fed17e7743e35dc, 0xbfdaa6c82b6d3fc9, // 0.90917, -0.41643 + 0x3fed1d20dc40c15c, 0xbfda8fec8bf5b166, // 0.90981, -0.41503 + 0x3fed2255c6e5a4e1, 0xbfda790cd3dbf31a, // 0.91044, -0.41364 + 0x3fed2786335f52fc, 0xbfda622906a70b63, // 0.91107, -0.41224 + 0x3fed2cb220e0ef9f, 0xbfda4b4127dea1e4, // 0.91171, -0.41084 + 0x3fed31d98e9e503a, 0xbfda34553b0afee5, // 0.91234, -0.40944 + 0x3fed36fc7bcbfbdc, 0xbfda1d6543b50ac0, // 0.91296, -0.40804 + 0x3fed3c1ae79f2b4e, 0xbfda067145664d57, // 0.91359, -0.40664 + 0x3fed4134d14dc93a, 0xbfd9ef7943a8ed8a, // 0.91421, -0.40524 + 0x3fed464a380e7242, 0xbfd9d87d4207b0ab, // 0.91483, -0.40384 + 0x3fed4b5b1b187524, 0xbfd9c17d440df9f2, // 0.91545, -0.40243 + 0x3fed506779a3d2d9, 0xbfd9aa794d47c9ee, // 0.91606, -0.40103 + 0x3fed556f52e93eb1, 0xbfd993716141bdfe, // 0.91668, -0.39962 + 0x3fed5a72a6221e73, 0xbfd97c6583890fc2, // 0.91729, -0.39822 + 0x3fed5f7172888a7f, 0xbfd96555b7ab948f, // 0.9179, -0.39681 + 0x3fed646bb7574de5, 0xbfd94e420137bce3, // 0.91851, -0.3954 + 0x3fed696173c9e68b, 0xbfd9372a63bc93d7, // 0.91911, -0.39399 + 0x3fed6e52a71c8547, 0xbfd9200ee2c9be97, // 0.91972, -0.39258 + 0x3fed733f508c0dff, 0xbfd908ef81ef7bd1, // 0.92032, -0.39117 + 0x3fed78276f5617c6, 0xbfd8f1cc44bea329, // 0.92092, -0.38976 + 0x3fed7d0b02b8ecf9, 0xbfd8daa52ec8a4af, // 0.92151, -0.38835 + 0x3fed81ea09f38b63, 0xbfd8c37a439f884f, // 0.92211, -0.38693 + 0x3fed86c48445a450, 0xbfd8ac4b86d5ed44, // 0.9227, -0.38552 + 0x3fed8b9a70ef9cb4, 0xbfd89518fbff098e, // 0.92329, -0.3841 + 0x3fed906bcf328d46, 0xbfd87de2a6aea963, // 0.92388, -0.38268 + 0x3fed95389e50429b, 0xbfd866a88a792ea0, // 0.92447, -0.38127 + 0x3fed9a00dd8b3d46, 0xbfd84f6aaaf3903f, // 0.92505, -0.37985 + 0x3fed9ec48c26b1f3, 0xbfd838290bb359c8, // 0.92563, -0.37843 + 0x3feda383a9668988, 0xbfd820e3b04eaac4, // 0.92621, -0.37701 + 0x3feda83e348f613b, 0xbfd8099a9c5c362d, // 0.92679, -0.37559 + 0x3fedacf42ce68ab9, 0xbfd7f24dd37341e3, // 0.92736, -0.37416 + 0x3fedb1a591b20c38, 0xbfd7dafd592ba621, // 0.92794, -0.37274 + 0x3fedb6526238a09b, 0xbfd7c3a9311dcce7, // 0.92851, -0.37132 + 0x3fedbafa9dc1b78d, 0xbfd7ac515ee2b172, // 0.92907, -0.36989 + 0x3fedbf9e4395759a, 0xbfd794f5e613dfae, // 0.92964, -0.36847 + 0x3fedc43d52fcb453, 0xbfd77d96ca4b73a6, // 0.93021, -0.36704 + 0x3fedc8d7cb410260, 0xbfd766340f2418f6, // 0.93077, -0.36561 + 0x3fedcd6dabaca3a5, 0xbfd74ecdb8390a3e, // 0.93133, -0.36418 + 0x3fedd1fef38a915a, 0xbfd73763c9261092, // 0.93188, -0.36276 + 0x3fedd68ba2267a25, 0xbfd71ff6458782ec, // 0.93244, -0.36133 + 0x3feddb13b6ccc23d, 0xbfd7088530fa459e, // 0.93299, -0.3599 + 0x3feddf9730ca837b, 0xbfd6f1108f1bc9c5, // 0.93354, -0.35846 + 0x3fede4160f6d8d81, 0xbfd6d998638a0cb5, // 0.93409, -0.35703 + 0x3fede890520465ce, 0xbfd6c21cb1e39771, // 0.93464, -0.3556 + 0x3feded05f7de47da, 0xbfd6aa9d7dc77e16, // 0.93518, -0.35416 + 0x3fedf177004b2534, 0xbfd6931acad55f51, // 0.93573, -0.35273 + 0x3fedf5e36a9ba59c, 0xbfd67b949cad63ca, // 0.93627, -0.35129 + 0x3fedfa4b3621271d, 0xbfd6640af6f03d9e, // 0.9368, -0.34986 + 0x3fedfeae622dbe2b, 0xbfd64c7ddd3f27c6, // 0.93734, -0.34842 + 0x3fee030cee1435b8, 0xbfd634ed533be58e, // 0.93787, -0.34698 + 0x3fee0766d9280f54, 0xbfd61d595c88c203, // 0.9384, -0.34554 + 0x3fee0bbc22bd8349, 0xbfd605c1fcc88f63, // 0.93893, -0.3441 + 0x3fee100cca2980ac, 0xbfd5ee27379ea693, // 0.93946, -0.34266 + 0x3fee1458cec1ad83, 0xbfd5d68910aee686, // 0.93998, -0.34122 + 0x3fee18a02fdc66d9, 0xbfd5bee78b9db3b6, // 0.94051, -0.33978 + 0x3fee1ce2ecd0c0d8, 0xbfd5a742ac0ff78d, // 0.94103, -0.33833 + 0x3fee212104f686e5, 0xbfd58f9a75ab1fdd, // 0.94154, -0.33689 + 0x3fee255a77a63bb8, 0xbfd577eeec151e47, // 0.94206, -0.33545 + 0x3fee298f4439197a, 0xbfd5604012f467b4, // 0.94257, -0.334 + 0x3fee2dbf6a0911d9, 0xbfd5488dedeff3be, // 0.94308, -0.33255 + 0x3fee31eae870ce25, 0xbfd530d880af3c24, // 0.94359, -0.33111 + 0x3fee3611becbaf69, 0xbfd5191fceda3c35, // 0.9441, -0.32966 + 0x3fee3a33ec75ce85, 0xbfd50163dc197047, // 0.9446, -0.32821 + 0x3fee3e5170cbfc46, 0xbfd4e9a4ac15d520, // 0.94511, -0.32676 + 0x3fee426a4b2bc17e, 0xbfd4d1e24278e76a, // 0.94561, -0.32531 + 0x3fee467e7af35f23, 0xbfd4ba1ca2eca31c, // 0.94611, -0.32386 + 0x3fee4a8dff81ce5e, 0xbfd4a253d11b82f3, // 0.9466, -0.32241 + 0x3fee4e98d836c0af, 0xbfd48a87d0b07fd7, // 0.94709, -0.32096 + 0x3fee529f04729ffc, 0xbfd472b8a5571054, // 0.94759, -0.3195 + 0x3fee56a083968eb1, 0xbfd45ae652bb2800, // 0.94807, -0.31805 + 0x3fee5a9d550467d3, 0xbfd44310dc8936f0, // 0.94856, -0.31659 + 0x3fee5e95781ebf1c, 0xbfd42b38466e2928, // 0.94905, -0.31514 + 0x3fee6288ec48e112, 0xbfd4135c94176602, // 0.94953, -0.31368 + 0x3fee6677b0e6d31e, 0xbfd3fb7dc932cfa4, // 0.95001, -0.31222 + 0x3fee6a61c55d53a7, 0xbfd3e39be96ec271, // 0.95049, -0.31077 + 0x3fee6e472911da27, 0xbfd3cbb6f87a146e, // 0.95096, -0.30931 + 0x3fee7227db6a9744, 0xbfd3b3cefa0414b7, // 0.95144, -0.30785 + 0x3fee7603dbce74e9, 0xbfd39be3f1bc8aef, // 0.95191, -0.30639 + 0x3fee79db29a5165a, 0xbfd383f5e353b6aa, // 0.95238, -0.30493 + 0x3fee7dadc456d850, 0xbfd36c04d27a4edf, // 0.95284, -0.30347 + 0x3fee817bab4cd10d, 0xbfd35410c2e18152, // 0.95331, -0.30201 + 0x3fee8544ddf0d075, 0xbfd33c19b83af207, // 0.95377, -0.30054 + 0x3fee89095bad6025, 0xbfd3241fb638baaf, // 0.95423, -0.29908 + 0x3fee8cc923edc388, 0xbfd30c22c08d6a13, // 0.95469, -0.29762 + 0x3fee9084361df7f3, 0xbfd2f422daec0386, // 0.95514, -0.29615 + 0x3fee943a91aab4b4, 0xbfd2dc200907fe51, // 0.95559, -0.29469 + 0x3fee97ec36016b30, 0xbfd2c41a4e954520, // 0.95605, -0.29322 + 0x3fee9b99229046f8, 0xbfd2ac11af483572, // 0.95649, -0.29175 + 0x3fee9f4156c62dda, 0xbfd294062ed59f05, // 0.95694, -0.29028 + 0x3feea2e4d212c000, 0xbfd27bf7d0f2c346, // 0.95738, -0.28882 + 0x3feea68393e65800, 0xbfd263e6995554ba, // 0.95783, -0.28735 + 0x3feeaa1d9bb20af3, 0xbfd24bd28bb37672, // 0.95827, -0.28588 + 0x3feeadb2e8e7a88e, 0xbfd233bbabc3bb72, // 0.9587, -0.28441 + 0x3feeb1437af9bb34, 0xbfd21ba1fd3d2623, // 0.95914, -0.28294 + 0x3feeb4cf515b8811, 0xbfd2038583d727bd, // 0.95957, -0.28146 + 0x3feeb8566b810f2a, 0xbfd1eb6643499fbb, // 0.96, -0.27999 + 0x3feebbd8c8df0b74, 0xbfd1d3443f4cdb3d, // 0.96043, -0.27852 + 0x3feebf5668eaf2ef, 0xbfd1bb1f7b999480, // 0.96086, -0.27705 + 0x3feec2cf4b1af6b2, 0xbfd1a2f7fbe8f243, // 0.96128, -0.27557 + 0x3feec6436ee60309, 0xbfd18acdc3f4873a, // 0.9617, -0.2741 + 0x3feec9b2d3c3bf84, 0xbfd172a0d7765177, // 0.96212, -0.27262 + 0x3feecd1d792c8f10, 0xbfd15a713a28b9d9, // 0.96254, -0.27115 + 0x3feed0835e999009, 0xbfd1423eefc69378, // 0.96295, -0.26967 + 0x3feed3e483849c51, 0xbfd12a09fc0b1b12, // 0.96337, -0.26819 + 0x3feed740e7684963, 0xbfd111d262b1f677, // 0.96378, -0.26671 + 0x3feeda9889bfe86a, 0xbfd0f998277733f7, // 0.96418, -0.26523 + 0x3feeddeb6a078651, 0xbfd0e15b4e1749cd, // 0.96459, -0.26375 + 0x3feee13987bbebdc, 0xbfd0c91bda4f158d, // 0.96499, -0.26227 + 0x3feee482e25a9dbc, 0xbfd0b0d9cfdbdb90, // 0.96539, -0.26079 + 0x3feee7c77961dc9e, 0xbfd09895327b465e, // 0.96579, -0.25931 + 0x3feeeb074c50a544, 0xbfd0804e05eb661e, // 0.96619, -0.25783 + 0x3feeee425aa6b09a, 0xbfd068044deab002, // 0.96658, -0.25635 + 0x3feef178a3e473c2, 0xbfd04fb80e37fdae, // 0.96698, -0.25487 + 0x3feef4aa278b2032, 0xbfd037694a928cac, // 0.96737, -0.25338 + 0x3feef7d6e51ca3c0, 0xbfd01f1806b9fdd2, // 0.96775, -0.2519 + 0x3feefafedc1ba8b7, 0xbfd006c4466e54af, // 0.96814, -0.25041 + 0x3feefe220c0b95ec, 0xbfcfdcdc1adfedf8, // 0.96852, -0.24893 + 0x3fef014074708ed3, 0xbfcfac2abeff57ff, // 0.9689, -0.24744 + 0x3fef045a14cf738c, 0xbfcf7b7480bd3801, // 0.96928, -0.24596 + 0x3fef076eecade0fa, 0xbfcf4ab9679c9f5c, // 0.96966, -0.24447 + 0x3fef0a7efb9230d7, 0xbfcf19f97b215f1a, // 0.97003, -0.24298 + 0x3fef0d8a410379c5, 0xbfcee934c2d006c7, // 0.9704, -0.24149 + 0x3fef1090bc898f5f, 0xbfceb86b462de348, // 0.97077, -0.24 + 0x3fef13926dad024e, 0xbfce879d0cc0fdaf, // 0.97114, -0.23851 + 0x3fef168f53f7205d, 0xbfce56ca1e101a1b, // 0.9715, -0.23702 + 0x3fef19876ef1f486, 0xbfce25f281a2b684, // 0.97187, -0.23553 + 0x3fef1c7abe284708, 0xbfcdf5163f01099a, // 0.97223, -0.23404 + 0x3fef1f6941259d7a, 0xbfcdc4355db40195, // 0.97258, -0.23255 + 0x3fef2252f7763ada, 0xbfcd934fe5454311, // 0.97294, -0.23106 + 0x3fef2537e0a71f9f, 0xbfcd6265dd3f27e3, // 0.97329, -0.22957 + 0x3fef2817fc4609ce, 0xbfcd31774d2cbdee, // 0.97364, -0.22807 + 0x3fef2af349e17507, 0xbfcd00843c99c5f9, // 0.97399, -0.22658 + 0x3fef2dc9c9089a9d, 0xbfcccf8cb312b286, // 0.97434, -0.22508 + 0x3fef309b794b719f, 0xbfcc9e90b824a6a9, // 0.97468, -0.22359 + 0x3fef33685a3aaef0, 0xbfcc6d90535d74dc, // 0.97503, -0.22209 + 0x3fef36306b67c556, 0xbfcc3c8b8c4b9dd7, // 0.97536, -0.2206 + 0x3fef38f3ac64e589, 0xbfcc0b826a7e4f63, // 0.9757, -0.2191 + 0x3fef3bb21cc4fe47, 0xbfcbda74f5856330, // 0.97604, -0.2176 + 0x3fef3e6bbc1bbc65, 0xbfcba96334f15dad, // 0.97637, -0.21611 + 0x3fef412089fd8adc, 0xbfcb784d30536cda, // 0.9767, -0.21461 + 0x3fef43d085ff92dd, 0xbfcb4732ef3d6722, // 0.97703, -0.21311 + 0x3fef467bafb7bbe0, 0xbfcb16147941ca2a, // 0.97735, -0.21161 + 0x3fef492206bcabb4, 0xbfcae4f1d5f3b9ab, // 0.97768, -0.21011 + 0x3fef4bc38aa5c694, 0xbfcab3cb0ce6fe44, // 0.978, -0.20861 + 0x3fef4e603b0b2f2d, 0xbfca82a025b00451, // 0.97832, -0.20711 + 0x3fef50f81785c6b9, 0xbfca517127e3dabc, // 0.97863, -0.20561 + 0x3fef538b1faf2d07, 0xbfca203e1b1831da, // 0.97895, -0.20411 + 0x3fef56195321c090, 0xbfc9ef0706e35a35, // 0.97926, -0.20261 + 0x3fef58a2b1789e84, 0xbfc9bdcbf2dc4366, // 0.97957, -0.2011 + 0x3fef5b273a4fa2d9, 0xbfc98c8ce69a7aec, // 0.97988, -0.1996 + 0x3fef5da6ed43685d, 0xbfc95b49e9b62af9, // 0.98018, -0.1981 + 0x3fef6021c9f148c2, 0xbfc92a0303c8194f, // 0.98048, -0.19659 + 0x3fef6297cff75cb0, 0xbfc8f8b83c69a60a, // 0.98079, -0.19509 + 0x3fef6508fef47bd5, 0xbfc8c7699b34ca7e, // 0.98108, -0.19359 + 0x3fef677556883cee, 0xbfc8961727c41804, // 0.98138, -0.19208 + 0x3fef69dcd652f5de, 0xbfc864c0e9b2b6cf, // 0.98167, -0.19057 + 0x3fef6c3f7df5bbb7, 0xbfc83366e89c64c5, // 0.98196, -0.18907 + 0x3fef6e9d4d1262ca, 0xbfc802092c1d744b, // 0.98225, -0.18756 + 0x3fef70f6434b7eb7, 0xbfc7d0a7bbd2cb1b, // 0.98254, -0.18606 + 0x3fef734a60446279, 0xbfc79f429f59e11d, // 0.98282, -0.18455 + 0x3fef7599a3a12077, 0xbfc76dd9de50bf31, // 0.98311, -0.18304 + 0x3fef77e40d068a90, 0xbfc73c6d8055fe0a, // 0.98339, -0.18153 + 0x3fef7a299c1a322a, 0xbfc70afd8d08c4ff, // 0.98366, -0.18002 + 0x3fef7c6a50826840, 0xbfc6d98a0c08c8da, // 0.98394, -0.17851 + 0x3fef7ea629e63d6e, 0xbfc6a81304f64ab2, // 0.98421, -0.177 + 0x3fef80dd27ed8204, 0xbfc676987f7216b8, // 0.98448, -0.17549 + 0x3fef830f4a40c60c, 0xbfc6451a831d830d, // 0.98475, -0.17398 + 0x3fef853c9089595e, 0xbfc61399179a6e94, // 0.98501, -0.17247 + 0x3fef8764fa714ba9, 0xbfc5e214448b3fc6, // 0.98528, -0.17096 + 0x3fef898887a36c84, 0xbfc5b08c1192e381, // 0.98554, -0.16945 + 0x3fef8ba737cb4b78, 0xbfc57f008654cbde, // 0.9858, -0.16794 + 0x3fef8dc10a95380d, 0xbfc54d71aa74ef02, // 0.98605, -0.16643 + 0x3fef8fd5ffae41db, 0xbfc51bdf8597c5f2, // 0.98631, -0.16491 + 0x3fef91e616c43891, 0xbfc4ea4a1f624b61, // 0.98656, -0.1634 + 0x3fef93f14f85ac08, 0xbfc4b8b17f79fa88, // 0.98681, -0.16189 + 0x3fef95f7a9a1ec47, 0xbfc48715ad84cdf5, // 0.98706, -0.16037 + 0x3fef97f924c9099b, 0xbfc45576b1293e5a, // 0.9873, -0.15886 + 0x3fef99f5c0abd496, 0xbfc423d4920e4166, // 0.98754, -0.15734 + 0x3fef9bed7cfbde29, 0xbfc3f22f57db4893, // 0.98778, -0.15583 + 0x3fef9de0596b77a3, 0xbfc3c0870a383ff6, // 0.98802, -0.15431 + 0x3fef9fce55adb2c8, 0xbfc38edbb0cd8d14, // 0.98826, -0.1528 + 0x3fefa1b7717661d5, 0xbfc35d2d53440db2, // 0.98849, -0.15128 + 0x3fefa39bac7a1791, 0xbfc32b7bf94516a7, // 0.98872, -0.14976 + 0x3fefa57b066e2754, 0xbfc2f9c7aa7a72af, // 0.98895, -0.14825 + 0x3fefa7557f08a517, 0xbfc2c8106e8e613a, // 0.98918, -0.14673 + 0x3fefa92b1600657c, 0xbfc296564d2b953e, // 0.9894, -0.14521 + 0x3fefaafbcb0cfddc, 0xbfc264994dfd340a, // 0.98962, -0.1437 + 0x3fefacc79de6c44f, 0xbfc232d978aed413, // 0.98984, -0.14218 + 0x3fefae8e8e46cfbb, 0xbfc20116d4ec7bce, // 0.99006, -0.14066 + 0x3fefb0509be6f7db, 0xbfc1cf516a62a077, // 0.99027, -0.13914 + 0x3fefb20dc681d54d, 0xbfc19d8940be24e7, // 0.99049, -0.13762 + 0x3fefb3c60dd2c199, 0xbfc16bbe5fac5865, // 0.9907, -0.1361 + 0x3fefb5797195d741, 0xbfc139f0cedaf576, // 0.9909, -0.13458 + 0x3fefb727f187f1c7, 0xbfc1082095f820b0, // 0.99111, -0.13306 + 0x3fefb8d18d66adb7, 0xbfc0d64dbcb26786, // 0.99131, -0.13154 + 0x3fefba7644f068b5, 0xbfc0a4784ab8bf1d, // 0.99151, -0.13002 + 0x3fefbc1617e44186, 0xbfc072a047ba831d, // 0.99171, -0.1285 + 0x3fefbdb106021816, 0xbfc040c5bb67747e, // 0.99191, -0.12698 + 0x3fefbf470f0a8d88, 0xbfc00ee8ad6fb85b, // 0.9921, -0.12545 + 0x3fefc0d832bf043a, 0xbfbfba124b07ad85, // 0.99229, -0.12393 + 0x3fefc26470e19fd3, 0xbfbf564e56a9730e, // 0.99248, -0.12241 + 0x3fefc3ebc935454c, 0xbfbef2858d27561b, // 0.99267, -0.12089 + 0x3fefc56e3b7d9af6, 0xbfbe8eb7fde4aa3e, // 0.99285, -0.11937 + 0x3fefc6ebc77f0887, 0xbfbe2ae5b8457f77, // 0.99303, -0.11784 + 0x3fefc8646cfeb721, 0xbfbdc70ecbae9fc8, // 0.99321, -0.11632 + 0x3fefc9d82bc2915e, 0xbfbd633347858ce4, // 0.99339, -0.11479 + 0x3fefcb4703914354, 0xbfbcff533b307dc1, // 0.99356, -0.11327 + 0x3fefccb0f4323aa3, 0xbfbc9b6eb6165c42, // 0.99374, -0.11175 + 0x3fefce15fd6da67b, 0xbfbc3785c79ec2d5, // 0.99391, -0.11022 + 0x3fefcf761f0c77a3, 0xbfbbd3987f31fa0e, // 0.99407, -0.1087 + 0x3fefd0d158d86087, 0xbfbb6fa6ec38f64c, // 0.99424, -0.10717 + 0x3fefd227aa9bd53b, 0xbfbb0bb11e1d5559, // 0.9944, -0.10565 + 0x3fefd37914220b84, 0xbfbaa7b724495c04, // 0.99456, -0.10412 + 0x3fefd4c59536fae4, 0xbfba43b90e27f3c4, // 0.99472, -0.1026 + 0x3fefd60d2da75c9e, 0xbfb9dfb6eb24a85c, // 0.99488, -0.10107 + 0x3fefd74fdd40abbf, 0xbfb97bb0caaba56f, // 0.99503, -0.099544 + 0x3fefd88da3d12526, 0xbfb917a6bc29b42c, // 0.99518, -0.098017 + 0x3fefd9c68127c78c, 0xbfb8b398cf0c38e0, // 0.99533, -0.09649 + 0x3fefdafa7514538c, 0xbfb84f8712c130a0, // 0.99548, -0.094963 + 0x3fefdc297f674ba9, 0xbfb7eb7196b72ee4, // 0.99563, -0.093436 + 0x3fefdd539ff1f456, 0xbfb787586a5d5b21, // 0.99577, -0.091909 + 0x3fefde78d68653fd, 0xbfb7233b9d236e71, // 0.99591, -0.090381 + 0x3fefdf9922f73307, 0xbfb6bf1b3e79b129, // 0.99604, -0.088854 + 0x3fefe0b485181be3, 0xbfb65af75dd0f87b, // 0.99618, -0.087326 + 0x3fefe1cafcbd5b09, 0xbfb5f6d00a9aa419, // 0.99631, -0.085797 + 0x3fefe2dc89bbff08, 0xbfb592a554489bc8, // 0.99644, -0.084269 + 0x3fefe3e92be9d886, 0xbfb52e774a4d4d0a, // 0.99657, -0.08274 + 0x3fefe4f0e31d7a4a, 0xbfb4ca45fc1ba8b6, // 0.9967, -0.081211 + 0x3fefe5f3af2e3940, 0xbfb4661179272096, // 0.99682, -0.079682 + 0x3fefe6f18ff42c84, 0xbfb401d9d0e3a507, // 0.99694, -0.078153 + 0x3fefe7ea85482d60, 0xbfb39d9f12c5a299, // 0.99706, -0.076624 + 0x3fefe8de8f03d75c, 0xbfb339614e41ffa5, // 0.99718, -0.075094 + 0x3fefe9cdad01883a, 0xbfb2d52092ce19f6, // 0.99729, -0.073565 + 0x3fefeab7df1c6005, 0xbfb270dcefdfc45b, // 0.9974, -0.072035 + 0x3fefeb9d2530410f, 0xbfb20c9674ed444c, // 0.99751, -0.070505 + 0x3fefec7d7f19cffc, 0xbfb1a84d316d4f8a, // 0.99762, -0.068974 + 0x3fefed58ecb673c4, 0xbfb1440134d709b2, // 0.99772, -0.067444 + 0x3fefee2f6de455ba, 0xbfb0dfb28ea201e6, // 0.99783, -0.065913 + 0x3fefef0102826191, 0xbfb07b614e463064, // 0.99793, -0.064383 + 0x3fefefcdaa704562, 0xbfb0170d833bf421, // 0.99802, -0.062852 + 0x3feff095658e71ad, 0xbfaf656e79f820e0, // 0.99812, -0.061321 + 0x3feff15833be1965, 0xbfae9cbd15ff5527, // 0.99821, -0.05979 + 0x3feff21614e131ed, 0xbfadd406f9808ec8, // 0.9983, -0.058258 + 0x3feff2cf08da7321, 0xbfad0b4c436f91d0, // 0.99839, -0.056727 + 0x3feff3830f8d575c, 0xbfac428d12c0d7e3, // 0.99848, -0.055195 + 0x3feff43228de1b77, 0xbfab79c986698b78, // 0.99856, -0.053664 + 0x3feff4dc54b1bed3, 0xbfaab101bd5f8317, // 0.99864, -0.052132 + 0x3feff58192ee0358, 0xbfa9e835d6993c87, // 0.99872, -0.0506 + 0x3feff621e3796d7e, 0xbfa91f65f10dd814, // 0.9988, -0.049068 + 0x3feff6bd463b444d, 0xbfa856922bb513c1, // 0.99887, -0.047535 + 0x3feff753bb1b9164, 0xbfa78dbaa5874685, // 0.99894, -0.046003 + 0x3feff7e5420320f9, 0xbfa6c4df7d7d5b84, // 0.99901, -0.044471 + 0x3feff871dadb81df, 0xbfa5fc00d290cd43, // 0.99908, -0.042938 + 0x3feff8f9858f058b, 0xbfa5331ec3bba0eb, // 0.99914, -0.041406 + 0x3feff97c4208c014, 0xbfa46a396ff86179, // 0.9992, -0.039873 + 0x3feff9fa10348837, 0xbfa3a150f6421afc, // 0.99926, -0.03834 + 0x3feffa72effef75d, 0xbfa2d865759455cd, // 0.99932, -0.036807 + 0x3feffae6e1556998, 0xbfa20f770ceb11c6, // 0.99938, -0.035274 + 0x3feffb55e425fdae, 0xbfa14685db42c17e, // 0.99943, -0.033741 + 0x3feffbbff85f9515, 0xbfa07d91ff984580, // 0.99948, -0.032208 + 0x3feffc251df1d3f8, 0xbf9f693731d1cf01, // 0.99953, -0.030675 + 0x3feffc8554cd213a, 0xbf9dd7458c64ab39, // 0.99958, -0.029142 + 0x3feffce09ce2a679, 0xbf9c454f4ce53b1c, // 0.99962, -0.027608 + 0x3feffd36f624500c, 0xbf9ab354b1504fca, // 0.99966, -0.026075 + 0x3feffd886084cd0d, 0xbf992155f7a3667e, // 0.9997, -0.024541 + 0x3feffdd4dbf78f52, 0xbf978f535ddc9f03, // 0.99974, -0.023008 + 0x3feffe1c6870cb77, 0xbf95fd4d21fab226, // 0.99977, -0.021474 + 0x3feffe5f05e578db, 0xbf946b4381fce81c, // 0.9998, -0.01994 + 0x3feffe9cb44b51a1, 0xbf92d936bbe30efd, // 0.99983, -0.018407 + 0x3feffed57398d2b7, 0xbf9147270dad7132, // 0.99986, -0.016873 + 0x3fefff0943c53bd1, 0xbf8f6a296ab997ca, // 0.99988, -0.015339 + 0x3fefff3824c88f6f, 0xbf8c45ffe1e48ad9, // 0.9999, -0.013805 + 0x3fefff62169b92db, 0xbf8921d1fcdec784, // 0.99992, -0.012272 + 0x3fefff871937ce2f, 0xbf85fda037ac05e0, // 0.99994, -0.010738 + 0x3fefffa72c978c4f, 0xbf82d96b0e509703, // 0.99996,-0.0092038 + 0x3fefffc250b5daef, 0xbf7f6a65f9a2a3c5, // 0.99997,-0.0076698 + 0x3fefffd8858e8a92, 0xbf7921f0fe670071, // 0.99998,-0.0061359 + 0x3fefffe9cb1e2e8d, 0xbf72d97822f996bc, // 0.99999,-0.0046019 + 0x3feffff621621d02, 0xbf6921f8becca4ba, // 1, -0.003068 + 0x3feffffd88586ee6, 0xbf5921faaee6472d, // 1, -0.001534 + + +}; + +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_F32_16) +/** + @par + Example code for Floating-point Twiddle factors Generation: + @par + 
for (i = 0; i < N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/(float)N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 16, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const float32_t twiddleCoef_16[32] = { + 1.000000000f, 0.000000000f, + 0.923879533f, 0.382683432f, + 0.707106781f, 0.707106781f, + 0.382683432f, 0.923879533f, + 0.000000000f, 1.000000000f, + -0.382683432f, 0.923879533f, + -0.707106781f, 0.707106781f, + -0.923879533f, 0.382683432f, + -1.000000000f, 0.000000000f, + -0.923879533f, -0.382683432f, + -0.707106781f, -0.707106781f, + -0.382683432f, -0.923879533f, + -0.000000000f, -1.000000000f, + 0.382683432f, -0.923879533f, + 0.707106781f, -0.707106781f, + 0.923879533f, -0.382683432f +}; + +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_F32_32) + +/** + @par + Example code for Floating-point Twiddle factors Generation: + @par + 
for (i = 0; i< N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/(float)N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 32, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const float32_t twiddleCoef_32[64] = { + 1.000000000f, 0.000000000f, + 0.980785280f, 0.195090322f, + 0.923879533f, 0.382683432f, + 0.831469612f, 0.555570233f, + 0.707106781f, 0.707106781f, + 0.555570233f, 0.831469612f, + 0.382683432f, 0.923879533f, + 0.195090322f, 0.980785280f, + 0.000000000f, 1.000000000f, + -0.195090322f, 0.980785280f, + -0.382683432f, 0.923879533f, + -0.555570233f, 0.831469612f, + -0.707106781f, 0.707106781f, + -0.831469612f, 0.555570233f, + -0.923879533f, 0.382683432f, + -0.980785280f, 0.195090322f, + -1.000000000f, 0.000000000f, + -0.980785280f, -0.195090322f, + -0.923879533f, -0.382683432f, + -0.831469612f, -0.555570233f, + -0.707106781f, -0.707106781f, + -0.555570233f, -0.831469612f, + -0.382683432f, -0.923879533f, + -0.195090322f, -0.980785280f, + -0.000000000f, -1.000000000f, + 0.195090322f, -0.980785280f, + 0.382683432f, -0.923879533f, + 0.555570233f, -0.831469612f, + 0.707106781f, -0.707106781f, + 0.831469612f, -0.555570233f, + 0.923879533f, -0.382683432f, + 0.980785280f, -0.195090322f +}; + +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_F32_64) +/** + @par + Example code for Floating-point Twiddle factors Generation: + @par + 
for(i = 0; i < N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/(float)N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 64, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const float32_t twiddleCoef_64[128] = { + 1.000000000f, 0.000000000f, + 0.995184727f, 0.098017140f, + 0.980785280f, 0.195090322f, + 0.956940336f, 0.290284677f, + 0.923879533f, 0.382683432f, + 0.881921264f, 0.471396737f, + 0.831469612f, 0.555570233f, + 0.773010453f, 0.634393284f, + 0.707106781f, 0.707106781f, + 0.634393284f, 0.773010453f, + 0.555570233f, 0.831469612f, + 0.471396737f, 0.881921264f, + 0.382683432f, 0.923879533f, + 0.290284677f, 0.956940336f, + 0.195090322f, 0.980785280f, + 0.098017140f, 0.995184727f, + 0.000000000f, 1.000000000f, + -0.098017140f, 0.995184727f, + -0.195090322f, 0.980785280f, + -0.290284677f, 0.956940336f, + -0.382683432f, 0.923879533f, + -0.471396737f, 0.881921264f, + -0.555570233f, 0.831469612f, + -0.634393284f, 0.773010453f, + -0.707106781f, 0.707106781f, + -0.773010453f, 0.634393284f, + -0.831469612f, 0.555570233f, + -0.881921264f, 0.471396737f, + -0.923879533f, 0.382683432f, + -0.956940336f, 0.290284677f, + -0.980785280f, 0.195090322f, + -0.995184727f, 0.098017140f, + -1.000000000f, 0.000000000f, + -0.995184727f, -0.098017140f, + -0.980785280f, -0.195090322f, + -0.956940336f, -0.290284677f, + -0.923879533f, -0.382683432f, + -0.881921264f, -0.471396737f, + -0.831469612f, -0.555570233f, + -0.773010453f, -0.634393284f, + -0.707106781f, -0.707106781f, + -0.634393284f, -0.773010453f, + -0.555570233f, -0.831469612f, + -0.471396737f, -0.881921264f, + -0.382683432f, -0.923879533f, + -0.290284677f, -0.956940336f, + -0.195090322f, -0.980785280f, + -0.098017140f, -0.995184727f, + -0.000000000f, -1.000000000f, + 0.098017140f, -0.995184727f, + 0.195090322f, -0.980785280f, + 0.290284677f, -0.956940336f, + 0.382683432f, -0.923879533f, + 0.471396737f, -0.881921264f, + 0.555570233f, -0.831469612f, + 0.634393284f, -0.773010453f, + 0.707106781f, -0.707106781f, + 0.773010453f, -0.634393284f, + 0.831469612f, -0.555570233f, + 0.881921264f, -0.471396737f, + 0.923879533f, -0.382683432f, + 0.956940336f, -0.290284677f, + 0.980785280f, -0.195090322f, + 0.995184727f, -0.098017140f +}; + +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_F32_128) +/** + @par + Example code for Floating-point Twiddle factors Generation: + @par + 
for (i = 0; i< N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/(float)N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 128, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const float32_t twiddleCoef_128[256] = { + 1.000000000f, 0.000000000f, + 0.998795456f, 0.049067674f, + 0.995184727f, 0.098017140f, + 0.989176510f, 0.146730474f, + 0.980785280f, 0.195090322f, + 0.970031253f, 0.242980180f, + 0.956940336f, 0.290284677f, + 0.941544065f, 0.336889853f, + 0.923879533f, 0.382683432f, + 0.903989293f, 0.427555093f, + 0.881921264f, 0.471396737f, + 0.857728610f, 0.514102744f, + 0.831469612f, 0.555570233f, + 0.803207531f, 0.595699304f, + 0.773010453f, 0.634393284f, + 0.740951125f, 0.671558955f, + 0.707106781f, 0.707106781f, + 0.671558955f, 0.740951125f, + 0.634393284f, 0.773010453f, + 0.595699304f, 0.803207531f, + 0.555570233f, 0.831469612f, + 0.514102744f, 0.857728610f, + 0.471396737f, 0.881921264f, + 0.427555093f, 0.903989293f, + 0.382683432f, 0.923879533f, + 0.336889853f, 0.941544065f, + 0.290284677f, 0.956940336f, + 0.242980180f, 0.970031253f, + 0.195090322f, 0.980785280f, + 0.146730474f, 0.989176510f, + 0.098017140f, 0.995184727f, + 0.049067674f, 0.998795456f, + 0.000000000f, 1.000000000f, + -0.049067674f, 0.998795456f, + -0.098017140f, 0.995184727f, + -0.146730474f, 0.989176510f, + -0.195090322f, 0.980785280f, + -0.242980180f, 0.970031253f, + -0.290284677f, 0.956940336f, + -0.336889853f, 0.941544065f, + -0.382683432f, 0.923879533f, + -0.427555093f, 0.903989293f, + -0.471396737f, 0.881921264f, + -0.514102744f, 0.857728610f, + -0.555570233f, 0.831469612f, + -0.595699304f, 0.803207531f, + -0.634393284f, 0.773010453f, + -0.671558955f, 0.740951125f, + -0.707106781f, 0.707106781f, + -0.740951125f, 0.671558955f, + -0.773010453f, 0.634393284f, + -0.803207531f, 0.595699304f, + -0.831469612f, 0.555570233f, + -0.857728610f, 0.514102744f, + -0.881921264f, 0.471396737f, + -0.903989293f, 0.427555093f, + -0.923879533f, 0.382683432f, + -0.941544065f, 0.336889853f, + -0.956940336f, 0.290284677f, + -0.970031253f, 0.242980180f, + -0.980785280f, 0.195090322f, + -0.989176510f, 0.146730474f, + -0.995184727f, 0.098017140f, + -0.998795456f, 0.049067674f, + -1.000000000f, 0.000000000f, + -0.998795456f, -0.049067674f, + -0.995184727f, -0.098017140f, + -0.989176510f, -0.146730474f, + -0.980785280f, -0.195090322f, + -0.970031253f, -0.242980180f, + -0.956940336f, -0.290284677f, + -0.941544065f, -0.336889853f, + -0.923879533f, -0.382683432f, + -0.903989293f, -0.427555093f, + -0.881921264f, -0.471396737f, + -0.857728610f, -0.514102744f, + -0.831469612f, -0.555570233f, + -0.803207531f, -0.595699304f, + -0.773010453f, -0.634393284f, + -0.740951125f, -0.671558955f, + -0.707106781f, -0.707106781f, + -0.671558955f, -0.740951125f, + -0.634393284f, -0.773010453f, + -0.595699304f, -0.803207531f, + -0.555570233f, -0.831469612f, + -0.514102744f, -0.857728610f, + -0.471396737f, -0.881921264f, + -0.427555093f, -0.903989293f, + -0.382683432f, -0.923879533f, + -0.336889853f, -0.941544065f, + -0.290284677f, -0.956940336f, + -0.242980180f, -0.970031253f, + -0.195090322f, -0.980785280f, + -0.146730474f, -0.989176510f, + -0.098017140f, -0.995184727f, + -0.049067674f, -0.998795456f, + -0.000000000f, -1.000000000f, + 0.049067674f, -0.998795456f, + 0.098017140f, -0.995184727f, + 0.146730474f, -0.989176510f, + 0.195090322f, -0.980785280f, + 0.242980180f, -0.970031253f, + 0.290284677f, -0.956940336f, + 0.336889853f, -0.941544065f, + 0.382683432f, -0.923879533f, + 0.427555093f, -0.903989293f, + 0.471396737f, -0.881921264f, + 0.514102744f, -0.857728610f, + 0.555570233f, -0.831469612f, + 0.595699304f, -0.803207531f, + 0.634393284f, -0.773010453f, + 0.671558955f, -0.740951125f, + 0.707106781f, -0.707106781f, + 0.740951125f, -0.671558955f, + 0.773010453f, -0.634393284f, + 0.803207531f, -0.595699304f, + 0.831469612f, -0.555570233f, + 0.857728610f, -0.514102744f, + 0.881921264f, -0.471396737f, + 0.903989293f, -0.427555093f, + 0.923879533f, -0.382683432f, + 0.941544065f, -0.336889853f, + 0.956940336f, -0.290284677f, + 0.970031253f, -0.242980180f, + 0.980785280f, -0.195090322f, + 0.989176510f, -0.146730474f, + 0.995184727f, -0.098017140f, + 0.998795456f, -0.049067674f +}; + +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_F32_256) +/** + @par + Example code for Floating-point Twiddle factors Generation: + @par + 
for(i = 0; i< N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/(float)N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 256, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const float32_t twiddleCoef_256[512] = { + 1.000000000f, 0.000000000f, + 0.999698819f, 0.024541229f, + 0.998795456f, 0.049067674f, + 0.997290457f, 0.073564564f, + 0.995184727f, 0.098017140f, + 0.992479535f, 0.122410675f, + 0.989176510f, 0.146730474f, + 0.985277642f, 0.170961889f, + 0.980785280f, 0.195090322f, + 0.975702130f, 0.219101240f, + 0.970031253f, 0.242980180f, + 0.963776066f, 0.266712757f, + 0.956940336f, 0.290284677f, + 0.949528181f, 0.313681740f, + 0.941544065f, 0.336889853f, + 0.932992799f, 0.359895037f, + 0.923879533f, 0.382683432f, + 0.914209756f, 0.405241314f, + 0.903989293f, 0.427555093f, + 0.893224301f, 0.449611330f, + 0.881921264f, 0.471396737f, + 0.870086991f, 0.492898192f, + 0.857728610f, 0.514102744f, + 0.844853565f, 0.534997620f, + 0.831469612f, 0.555570233f, + 0.817584813f, 0.575808191f, + 0.803207531f, 0.595699304f, + 0.788346428f, 0.615231591f, + 0.773010453f, 0.634393284f, + 0.757208847f, 0.653172843f, + 0.740951125f, 0.671558955f, + 0.724247083f, 0.689540545f, + 0.707106781f, 0.707106781f, + 0.689540545f, 0.724247083f, + 0.671558955f, 0.740951125f, + 0.653172843f, 0.757208847f, + 0.634393284f, 0.773010453f, + 0.615231591f, 0.788346428f, + 0.595699304f, 0.803207531f, + 0.575808191f, 0.817584813f, + 0.555570233f, 0.831469612f, + 0.534997620f, 0.844853565f, + 0.514102744f, 0.857728610f, + 0.492898192f, 0.870086991f, + 0.471396737f, 0.881921264f, + 0.449611330f, 0.893224301f, + 0.427555093f, 0.903989293f, + 0.405241314f, 0.914209756f, + 0.382683432f, 0.923879533f, + 0.359895037f, 0.932992799f, + 0.336889853f, 0.941544065f, + 0.313681740f, 0.949528181f, + 0.290284677f, 0.956940336f, + 0.266712757f, 0.963776066f, + 0.242980180f, 0.970031253f, + 0.219101240f, 0.975702130f, + 0.195090322f, 0.980785280f, + 0.170961889f, 0.985277642f, + 0.146730474f, 0.989176510f, + 0.122410675f, 0.992479535f, + 0.098017140f, 0.995184727f, + 0.073564564f, 0.997290457f, + 0.049067674f, 0.998795456f, + 0.024541229f, 0.999698819f, + 0.000000000f, 1.000000000f, + -0.024541229f, 0.999698819f, + -0.049067674f, 0.998795456f, + -0.073564564f, 0.997290457f, + -0.098017140f, 0.995184727f, + -0.122410675f, 0.992479535f, + -0.146730474f, 0.989176510f, + -0.170961889f, 0.985277642f, + -0.195090322f, 0.980785280f, + -0.219101240f, 0.975702130f, + -0.242980180f, 0.970031253f, + -0.266712757f, 0.963776066f, + -0.290284677f, 0.956940336f, + -0.313681740f, 0.949528181f, + -0.336889853f, 0.941544065f, + -0.359895037f, 0.932992799f, + -0.382683432f, 0.923879533f, + -0.405241314f, 0.914209756f, + -0.427555093f, 0.903989293f, + -0.449611330f, 0.893224301f, + -0.471396737f, 0.881921264f, + -0.492898192f, 0.870086991f, + -0.514102744f, 0.857728610f, + -0.534997620f, 0.844853565f, + -0.555570233f, 0.831469612f, + -0.575808191f, 0.817584813f, + -0.595699304f, 0.803207531f, + -0.615231591f, 0.788346428f, + -0.634393284f, 0.773010453f, + -0.653172843f, 0.757208847f, + -0.671558955f, 0.740951125f, + -0.689540545f, 0.724247083f, + -0.707106781f, 0.707106781f, + -0.724247083f, 0.689540545f, + -0.740951125f, 0.671558955f, + -0.757208847f, 0.653172843f, + -0.773010453f, 0.634393284f, + -0.788346428f, 0.615231591f, + -0.803207531f, 0.595699304f, + -0.817584813f, 0.575808191f, + -0.831469612f, 0.555570233f, + -0.844853565f, 0.534997620f, + -0.857728610f, 0.514102744f, + -0.870086991f, 0.492898192f, + -0.881921264f, 0.471396737f, + -0.893224301f, 0.449611330f, + -0.903989293f, 0.427555093f, + -0.914209756f, 0.405241314f, + -0.923879533f, 0.382683432f, + -0.932992799f, 0.359895037f, + -0.941544065f, 0.336889853f, + -0.949528181f, 0.313681740f, + -0.956940336f, 0.290284677f, + -0.963776066f, 0.266712757f, + -0.970031253f, 0.242980180f, + -0.975702130f, 0.219101240f, + -0.980785280f, 0.195090322f, + -0.985277642f, 0.170961889f, + -0.989176510f, 0.146730474f, + -0.992479535f, 0.122410675f, + -0.995184727f, 0.098017140f, + -0.997290457f, 0.073564564f, + -0.998795456f, 0.049067674f, + -0.999698819f, 0.024541229f, + -1.000000000f, 0.000000000f, + -0.999698819f, -0.024541229f, + -0.998795456f, -0.049067674f, + -0.997290457f, -0.073564564f, + -0.995184727f, -0.098017140f, + -0.992479535f, -0.122410675f, + -0.989176510f, -0.146730474f, + -0.985277642f, -0.170961889f, + -0.980785280f, -0.195090322f, + -0.975702130f, -0.219101240f, + -0.970031253f, -0.242980180f, + -0.963776066f, -0.266712757f, + -0.956940336f, -0.290284677f, + -0.949528181f, -0.313681740f, + -0.941544065f, -0.336889853f, + -0.932992799f, -0.359895037f, + -0.923879533f, -0.382683432f, + -0.914209756f, -0.405241314f, + -0.903989293f, -0.427555093f, + -0.893224301f, -0.449611330f, + -0.881921264f, -0.471396737f, + -0.870086991f, -0.492898192f, + -0.857728610f, -0.514102744f, + -0.844853565f, -0.534997620f, + -0.831469612f, -0.555570233f, + -0.817584813f, -0.575808191f, + -0.803207531f, -0.595699304f, + -0.788346428f, -0.615231591f, + -0.773010453f, -0.634393284f, + -0.757208847f, -0.653172843f, + -0.740951125f, -0.671558955f, + -0.724247083f, -0.689540545f, + -0.707106781f, -0.707106781f, + -0.689540545f, -0.724247083f, + -0.671558955f, -0.740951125f, + -0.653172843f, -0.757208847f, + -0.634393284f, -0.773010453f, + -0.615231591f, -0.788346428f, + -0.595699304f, -0.803207531f, + -0.575808191f, -0.817584813f, + -0.555570233f, -0.831469612f, + -0.534997620f, -0.844853565f, + -0.514102744f, -0.857728610f, + -0.492898192f, -0.870086991f, + -0.471396737f, -0.881921264f, + -0.449611330f, -0.893224301f, + -0.427555093f, -0.903989293f, + -0.405241314f, -0.914209756f, + -0.382683432f, -0.923879533f, + -0.359895037f, -0.932992799f, + -0.336889853f, -0.941544065f, + -0.313681740f, -0.949528181f, + -0.290284677f, -0.956940336f, + -0.266712757f, -0.963776066f, + -0.242980180f, -0.970031253f, + -0.219101240f, -0.975702130f, + -0.195090322f, -0.980785280f, + -0.170961889f, -0.985277642f, + -0.146730474f, -0.989176510f, + -0.122410675f, -0.992479535f, + -0.098017140f, -0.995184727f, + -0.073564564f, -0.997290457f, + -0.049067674f, -0.998795456f, + -0.024541229f, -0.999698819f, + -0.000000000f, -1.000000000f, + 0.024541229f, -0.999698819f, + 0.049067674f, -0.998795456f, + 0.073564564f, -0.997290457f, + 0.098017140f, -0.995184727f, + 0.122410675f, -0.992479535f, + 0.146730474f, -0.989176510f, + 0.170961889f, -0.985277642f, + 0.195090322f, -0.980785280f, + 0.219101240f, -0.975702130f, + 0.242980180f, -0.970031253f, + 0.266712757f, -0.963776066f, + 0.290284677f, -0.956940336f, + 0.313681740f, -0.949528181f, + 0.336889853f, -0.941544065f, + 0.359895037f, -0.932992799f, + 0.382683432f, -0.923879533f, + 0.405241314f, -0.914209756f, + 0.427555093f, -0.903989293f, + 0.449611330f, -0.893224301f, + 0.471396737f, -0.881921264f, + 0.492898192f, -0.870086991f, + 0.514102744f, -0.857728610f, + 0.534997620f, -0.844853565f, + 0.555570233f, -0.831469612f, + 0.575808191f, -0.817584813f, + 0.595699304f, -0.803207531f, + 0.615231591f, -0.788346428f, + 0.634393284f, -0.773010453f, + 0.653172843f, -0.757208847f, + 0.671558955f, -0.740951125f, + 0.689540545f, -0.724247083f, + 0.707106781f, -0.707106781f, + 0.724247083f, -0.689540545f, + 0.740951125f, -0.671558955f, + 0.757208847f, -0.653172843f, + 0.773010453f, -0.634393284f, + 0.788346428f, -0.615231591f, + 0.803207531f, -0.595699304f, + 0.817584813f, -0.575808191f, + 0.831469612f, -0.555570233f, + 0.844853565f, -0.534997620f, + 0.857728610f, -0.514102744f, + 0.870086991f, -0.492898192f, + 0.881921264f, -0.471396737f, + 0.893224301f, -0.449611330f, + 0.903989293f, -0.427555093f, + 0.914209756f, -0.405241314f, + 0.923879533f, -0.382683432f, + 0.932992799f, -0.359895037f, + 0.941544065f, -0.336889853f, + 0.949528181f, -0.313681740f, + 0.956940336f, -0.290284677f, + 0.963776066f, -0.266712757f, + 0.970031253f, -0.242980180f, + 0.975702130f, -0.219101240f, + 0.980785280f, -0.195090322f, + 0.985277642f, -0.170961889f, + 0.989176510f, -0.146730474f, + 0.992479535f, -0.122410675f, + 0.995184727f, -0.098017140f, + 0.997290457f, -0.073564564f, + 0.998795456f, -0.049067674f, + 0.999698819f, -0.024541229f +}; + +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_F32_512) +/** + @par + Example code for Floating-point Twiddle factors Generation: + @par + 
for (i = 0; i< N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/(float)N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 512, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const float32_t twiddleCoef_512[1024] = { + 1.000000000f, 0.000000000f, + 0.999924702f, 0.012271538f, + 0.999698819f, 0.024541229f, + 0.999322385f, 0.036807223f, + 0.998795456f, 0.049067674f, + 0.998118113f, 0.061320736f, + 0.997290457f, 0.073564564f, + 0.996312612f, 0.085797312f, + 0.995184727f, 0.098017140f, + 0.993906970f, 0.110222207f, + 0.992479535f, 0.122410675f, + 0.990902635f, 0.134580709f, + 0.989176510f, 0.146730474f, + 0.987301418f, 0.158858143f, + 0.985277642f, 0.170961889f, + 0.983105487f, 0.183039888f, + 0.980785280f, 0.195090322f, + 0.978317371f, 0.207111376f, + 0.975702130f, 0.219101240f, + 0.972939952f, 0.231058108f, + 0.970031253f, 0.242980180f, + 0.966976471f, 0.254865660f, + 0.963776066f, 0.266712757f, + 0.960430519f, 0.278519689f, + 0.956940336f, 0.290284677f, + 0.953306040f, 0.302005949f, + 0.949528181f, 0.313681740f, + 0.945607325f, 0.325310292f, + 0.941544065f, 0.336889853f, + 0.937339012f, 0.348418680f, + 0.932992799f, 0.359895037f, + 0.928506080f, 0.371317194f, + 0.923879533f, 0.382683432f, + 0.919113852f, 0.393992040f, + 0.914209756f, 0.405241314f, + 0.909167983f, 0.416429560f, + 0.903989293f, 0.427555093f, + 0.898674466f, 0.438616239f, + 0.893224301f, 0.449611330f, + 0.887639620f, 0.460538711f, + 0.881921264f, 0.471396737f, + 0.876070094f, 0.482183772f, + 0.870086991f, 0.492898192f, + 0.863972856f, 0.503538384f, + 0.857728610f, 0.514102744f, + 0.851355193f, 0.524589683f, + 0.844853565f, 0.534997620f, + 0.838224706f, 0.545324988f, + 0.831469612f, 0.555570233f, + 0.824589303f, 0.565731811f, + 0.817584813f, 0.575808191f, + 0.810457198f, 0.585797857f, + 0.803207531f, 0.595699304f, + 0.795836905f, 0.605511041f, + 0.788346428f, 0.615231591f, + 0.780737229f, 0.624859488f, + 0.773010453f, 0.634393284f, + 0.765167266f, 0.643831543f, + 0.757208847f, 0.653172843f, + 0.749136395f, 0.662415778f, + 0.740951125f, 0.671558955f, + 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0.405241314f, 0.914209756f, + 0.393992040f, 0.919113852f, + 0.382683432f, 0.923879533f, + 0.371317194f, 0.928506080f, + 0.359895037f, 0.932992799f, + 0.348418680f, 0.937339012f, + 0.336889853f, 0.941544065f, + 0.325310292f, 0.945607325f, + 0.313681740f, 0.949528181f, + 0.302005949f, 0.953306040f, + 0.290284677f, 0.956940336f, + 0.278519689f, 0.960430519f, + 0.266712757f, 0.963776066f, + 0.254865660f, 0.966976471f, + 0.242980180f, 0.970031253f, + 0.231058108f, 0.972939952f, + 0.219101240f, 0.975702130f, + 0.207111376f, 0.978317371f, + 0.195090322f, 0.980785280f, + 0.183039888f, 0.983105487f, + 0.170961889f, 0.985277642f, + 0.158858143f, 0.987301418f, + 0.146730474f, 0.989176510f, + 0.134580709f, 0.990902635f, + 0.122410675f, 0.992479535f, + 0.110222207f, 0.993906970f, + 0.098017140f, 0.995184727f, + 0.085797312f, 0.996312612f, + 0.073564564f, 0.997290457f, + 0.061320736f, 0.998118113f, + 0.049067674f, 0.998795456f, + 0.036807223f, 0.999322385f, + 0.024541229f, 0.999698819f, + 0.012271538f, 0.999924702f, + 0.000000000f, 1.000000000f, + -0.012271538f, 0.999924702f, + -0.024541229f, 0.999698819f, + -0.036807223f, 0.999322385f, + -0.049067674f, 0.998795456f, + -0.061320736f, 0.998118113f, + -0.073564564f, 0.997290457f, + -0.085797312f, 0.996312612f, + -0.098017140f, 0.995184727f, + -0.110222207f, 0.993906970f, + -0.122410675f, 0.992479535f, + -0.134580709f, 0.990902635f, + -0.146730474f, 0.989176510f, + -0.158858143f, 0.987301418f, + -0.170961889f, 0.985277642f, + -0.183039888f, 0.983105487f, + -0.195090322f, 0.980785280f, + -0.207111376f, 0.978317371f, + -0.219101240f, 0.975702130f, + -0.231058108f, 0.972939952f, + -0.242980180f, 0.970031253f, + -0.254865660f, 0.966976471f, + -0.266712757f, 0.963776066f, + -0.278519689f, 0.960430519f, + -0.290284677f, 0.956940336f, + -0.302005949f, 0.953306040f, + -0.313681740f, 0.949528181f, + -0.325310292f, 0.945607325f, + -0.336889853f, 0.941544065f, + -0.348418680f, 0.937339012f, + -0.359895037f, 0.932992799f, + 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0.998118113f, -0.061320736f, + 0.998795456f, -0.049067674f, + 0.999322385f, -0.036807223f, + 0.999698819f, -0.024541229f, + 0.999924702f, -0.012271538f +}; + +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_F32_1024) +/** + @par + Example code for Floating-point Twiddle factors Generation: + @par + 
for (i = 0; i< N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/(float)N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 1024, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const float32_t twiddleCoef_1024[2048] = { + 1.000000000f, 0.000000000f, + 0.999981175f, 0.006135885f, + 0.999924702f, 0.012271538f, + 0.999830582f, 0.018406730f, + 0.999698819f, 0.024541229f, + 0.999529418f, 0.030674803f, + 0.999322385f, 0.036807223f, + 0.999077728f, 0.042938257f, + 0.998795456f, 0.049067674f, + 0.998475581f, 0.055195244f, + 0.998118113f, 0.061320736f, + 0.997723067f, 0.067443920f, + 0.997290457f, 0.073564564f, + 0.996820299f, 0.079682438f, + 0.996312612f, 0.085797312f, + 0.995767414f, 0.091908956f, + 0.995184727f, 0.098017140f, + 0.994564571f, 0.104121634f, + 0.993906970f, 0.110222207f, + 0.993211949f, 0.116318631f, + 0.992479535f, 0.122410675f, + 0.991709754f, 0.128498111f, + 0.990902635f, 0.134580709f, + 0.990058210f, 0.140658239f, + 0.989176510f, 0.146730474f, + 0.988257568f, 0.152797185f, + 0.987301418f, 0.158858143f, + 0.986308097f, 0.164913120f, + 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0.999529418f, -0.030674803f, + 0.999698819f, -0.024541229f, + 0.999830582f, -0.018406730f, + 0.999924702f, -0.012271538f, + 0.999981175f, -0.006135885f +}; + +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_F32_2048) +/** + @par + Example code for Floating-point Twiddle factors Generation: + @par + 
for (i = 0; i< N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/(float)N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 2048, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const float32_t twiddleCoef_2048[4096] = { + 1.000000000f, 0.000000000f, + 0.999995294f, 0.003067957f, + 0.999981175f, 0.006135885f, + 0.999957645f, 0.009203755f, + 0.999924702f, 0.012271538f, + 0.999882347f, 0.015339206f, + 0.999830582f, 0.018406730f, + 0.999769405f, 0.021474080f, + 0.999698819f, 0.024541229f, + 0.999618822f, 0.027608146f, + 0.999529418f, 0.030674803f, + 0.999430605f, 0.033741172f, + 0.999322385f, 0.036807223f, + 0.999204759f, 0.039872928f, + 0.999077728f, 0.042938257f, + 0.998941293f, 0.046003182f, + 0.998795456f, 0.049067674f, + 0.998640218f, 0.052131705f, + 0.998475581f, 0.055195244f, + 0.998301545f, 0.058258265f, + 0.998118113f, 0.061320736f, + 0.997925286f, 0.064382631f, + 0.997723067f, 0.067443920f, + 0.997511456f, 0.070504573f, + 0.997290457f, 0.073564564f, + 0.997060070f, 0.076623861f, + 0.996820299f, 0.079682438f, + 0.996571146f, 0.082740265f, + 0.996312612f, 0.085797312f, + 0.996044701f, 0.088853553f, + 0.995767414f, 0.091908956f, + 0.995480755f, 0.094963495f, + 0.995184727f, 0.098017140f, + 0.994879331f, 0.101069863f, + 0.994564571f, 0.104121634f, + 0.994240449f, 0.107172425f, + 0.993906970f, 0.110222207f, + 0.993564136f, 0.113270952f, + 0.993211949f, 0.116318631f, + 0.992850414f, 0.119365215f, + 0.992479535f, 0.122410675f, + 0.992099313f, 0.125454983f, + 0.991709754f, 0.128498111f, + 0.991310860f, 0.131540029f, + 0.990902635f, 0.134580709f, + 0.990485084f, 0.137620122f, + 0.990058210f, 0.140658239f, + 0.989622017f, 0.143695033f, + 0.989176510f, 0.146730474f, + 0.988721692f, 0.149764535f, + 0.988257568f, 0.152797185f, + 0.987784142f, 0.155828398f, + 0.987301418f, 0.158858143f, + 0.986809402f, 0.161886394f, + 0.986308097f, 0.164913120f, + 0.985797509f, 0.167938295f, + 0.985277642f, 0.170961889f, + 0.984748502f, 0.173983873f, + 0.984210092f, 0.177004220f, + 0.983662419f, 0.180022901f, + 0.983105487f, 0.183039888f, + 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for (i = 0; i< N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/(float)N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 4096, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const float32_t twiddleCoef_4096[8192] = { + 1.000000000f, 0.000000000f, + 0.999998823f, 0.001533980f, + 0.999995294f, 0.003067957f, + 0.999989411f, 0.004601926f, + 0.999981175f, 0.006135885f, + 0.999970586f, 0.007669829f, + 0.999957645f, 0.009203755f, + 0.999942350f, 0.010737659f, + 0.999924702f, 0.012271538f, + 0.999904701f, 0.013805389f, + 0.999882347f, 0.015339206f, + 0.999857641f, 0.016872988f, + 0.999830582f, 0.018406730f, + 0.999801170f, 0.019940429f, + 0.999769405f, 0.021474080f, + 0.999735288f, 0.023007681f, + 0.999698819f, 0.024541229f, + 0.999659997f, 0.026074718f, + 0.999618822f, 0.027608146f, + 0.999575296f, 0.029141509f, + 0.999529418f, 0.030674803f, + 0.999481187f, 0.032208025f, + 0.999430605f, 0.033741172f, + 0.999377670f, 0.035274239f, + 0.999322385f, 0.036807223f, + 0.999264747f, 0.038340120f, + 0.999204759f, 0.039872928f, + 0.999142419f, 0.041405641f, + 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0.999957645f, -0.009203755f, + 0.999970586f, -0.007669829f, + 0.999981175f, -0.006135885f, + 0.999989411f, -0.004601926f, + 0.999995294f, -0.003067957f, + 0.999998823f, -0.001533980f +}; + +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + + +/** + @brief Q31 Twiddle factors Table +*/ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_Q31_16) +/** + @par + Example code for Q31 Twiddle factors Generation:: + @par + 
 for(i = 0; i< 3N/4; i++)
+  {
+     twiddleCoefQ31[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefQ31[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 16, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to Q31(Fixed point 1.31): + round(twiddleCoefQ31(i) * pow(2, 31)) + */ +const q31_t twiddleCoef_16_q31[24] = { + (q31_t)0x7FFFFFFF, (q31_t)0x00000000, + (q31_t)0x7641AF3C, (q31_t)0x30FBC54D, + (q31_t)0x5A82799A, (q31_t)0x5A82799A, + (q31_t)0x30FBC54D, (q31_t)0x7641AF3C, + (q31_t)0x00000000, (q31_t)0x7FFFFFFF, + (q31_t)0xCF043AB2, (q31_t)0x7641AF3C, + (q31_t)0xA57D8666, (q31_t)0x5A82799A, + (q31_t)0x89BE50C3, (q31_t)0x30FBC54D, + (q31_t)0x80000000, (q31_t)0x00000000, + (q31_t)0x89BE50C3, (q31_t)0xCF043AB2, + (q31_t)0xA57D8666, (q31_t)0xA57D8666, + (q31_t)0xCF043AB2, (q31_t)0x89BE50C3 +}; + +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_Q31_32) +/** + @par + Example code for Q31 Twiddle factors Generation:: + @par + 
for (i = 0; i< 3N/4; i++)
+  {
+     twiddleCoefQ31[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefQ31[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 32, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to Q31(Fixed point 1.31): + round(twiddleCoefQ31(i) * pow(2, 31)) + */ +const q31_t twiddleCoef_32_q31[48] = { + (q31_t)0x7FFFFFFF, (q31_t)0x00000000, + (q31_t)0x7D8A5F3F, (q31_t)0x18F8B83C, + (q31_t)0x7641AF3C, (q31_t)0x30FBC54D, + (q31_t)0x6A6D98A4, (q31_t)0x471CECE6, + (q31_t)0x5A82799A, (q31_t)0x5A82799A, + (q31_t)0x471CECE6, (q31_t)0x6A6D98A4, + (q31_t)0x30FBC54D, (q31_t)0x7641AF3C, + (q31_t)0x18F8B83C, (q31_t)0x7D8A5F3F, + (q31_t)0x00000000, (q31_t)0x7FFFFFFF, + (q31_t)0xE70747C3, (q31_t)0x7D8A5F3F, + (q31_t)0xCF043AB2, (q31_t)0x7641AF3C, + (q31_t)0xB8E31319, (q31_t)0x6A6D98A4, + (q31_t)0xA57D8666, (q31_t)0x5A82799A, + (q31_t)0x9592675B, (q31_t)0x471CECE6, + (q31_t)0x89BE50C3, (q31_t)0x30FBC54D, + (q31_t)0x8275A0C0, (q31_t)0x18F8B83C, + (q31_t)0x80000000, (q31_t)0x00000000, + (q31_t)0x8275A0C0, (q31_t)0xE70747C3, + (q31_t)0x89BE50C3, (q31_t)0xCF043AB2, + (q31_t)0x9592675B, (q31_t)0xB8E31319, + (q31_t)0xA57D8666, (q31_t)0xA57D8666, + (q31_t)0xB8E31319, (q31_t)0x9592675B, + (q31_t)0xCF043AB2, (q31_t)0x89BE50C3, + (q31_t)0xE70747C3, (q31_t)0x8275A0C0 +}; + +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_Q31_64) +/** + @par + Example code for Q31 Twiddle factors Generation:: + @par + 
for (i = 0; i< 3N/4; i++)
+  {
+     twiddleCoefQ31[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefQ31[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 64, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to Q31(Fixed point 1.31): + round(twiddleCoefQ31(i) * pow(2, 31)) + */ +const q31_t twiddleCoef_64_q31[96] = { + (q31_t)0x7FFFFFFF, (q31_t)0x00000000, (q31_t)0x7F62368F, + (q31_t)0x0C8BD35E, (q31_t)0x7D8A5F3F, (q31_t)0x18F8B83C, + (q31_t)0x7A7D055B, (q31_t)0x25280C5D, (q31_t)0x7641AF3C, + (q31_t)0x30FBC54D, (q31_t)0x70E2CBC6, (q31_t)0x3C56BA70, + (q31_t)0x6A6D98A4, (q31_t)0x471CECE6, (q31_t)0x62F201AC, + (q31_t)0x5133CC94, (q31_t)0x5A82799A, (q31_t)0x5A82799A, + (q31_t)0x5133CC94, (q31_t)0x62F201AC, (q31_t)0x471CECE6, + (q31_t)0x6A6D98A4, (q31_t)0x3C56BA70, (q31_t)0x70E2CBC6, + (q31_t)0x30FBC54D, (q31_t)0x7641AF3C, (q31_t)0x25280C5D, + (q31_t)0x7A7D055B, (q31_t)0x18F8B83C, (q31_t)0x7D8A5F3F, + (q31_t)0x0C8BD35E, (q31_t)0x7F62368F, (q31_t)0x00000000, + (q31_t)0x7FFFFFFF, (q31_t)0xF3742CA1, (q31_t)0x7F62368F, + (q31_t)0xE70747C3, (q31_t)0x7D8A5F3F, (q31_t)0xDAD7F3A2, + (q31_t)0x7A7D055B, (q31_t)0xCF043AB2, (q31_t)0x7641AF3C, + (q31_t)0xC3A9458F, (q31_t)0x70E2CBC6, (q31_t)0xB8E31319, + (q31_t)0x6A6D98A4, (q31_t)0xAECC336B, (q31_t)0x62F201AC, + (q31_t)0xA57D8666, (q31_t)0x5A82799A, (q31_t)0x9D0DFE53, + (q31_t)0x5133CC94, (q31_t)0x9592675B, (q31_t)0x471CECE6, + (q31_t)0x8F1D343A, (q31_t)0x3C56BA70, (q31_t)0x89BE50C3, + (q31_t)0x30FBC54D, (q31_t)0x8582FAA4, (q31_t)0x25280C5D, + (q31_t)0x8275A0C0, (q31_t)0x18F8B83C, (q31_t)0x809DC970, + (q31_t)0x0C8BD35E, (q31_t)0x80000000, (q31_t)0x00000000, + (q31_t)0x809DC970, (q31_t)0xF3742CA1, (q31_t)0x8275A0C0, + (q31_t)0xE70747C3, (q31_t)0x8582FAA4, (q31_t)0xDAD7F3A2, + (q31_t)0x89BE50C3, (q31_t)0xCF043AB2, (q31_t)0x8F1D343A, + (q31_t)0xC3A9458F, (q31_t)0x9592675B, (q31_t)0xB8E31319, + (q31_t)0x9D0DFE53, (q31_t)0xAECC336B, (q31_t)0xA57D8666, + (q31_t)0xA57D8666, (q31_t)0xAECC336B, (q31_t)0x9D0DFE53, + (q31_t)0xB8E31319, (q31_t)0x9592675B, (q31_t)0xC3A9458F, + (q31_t)0x8F1D343A, (q31_t)0xCF043AB2, (q31_t)0x89BE50C3, + (q31_t)0xDAD7F3A2, (q31_t)0x8582FAA4, (q31_t)0xE70747C3, + (q31_t)0x8275A0C0, (q31_t)0xF3742CA1, (q31_t)0x809DC970 +}; + +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_Q31_128) +/** + @par + Example code for Q31 Twiddle factors Generation:: + @par + 
for (i = 0; i < 3N/4; i++)
+  {
+     twiddleCoefQ31[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefQ31[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 128, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to Q31(Fixed point 1.31): + round(twiddleCoefQ31(i) * pow(2, 31)) + */ +const q31_t twiddleCoef_128_q31[192] = { + (q31_t)0x7FFFFFFF, (q31_t)0x00000000, (q31_t)0x7FD8878D, + (q31_t)0x0647D97C, (q31_t)0x7F62368F, (q31_t)0x0C8BD35E, + (q31_t)0x7E9D55FC, (q31_t)0x12C8106E, (q31_t)0x7D8A5F3F, + (q31_t)0x18F8B83C, (q31_t)0x7C29FBEE, (q31_t)0x1F19F97B, + (q31_t)0x7A7D055B, (q31_t)0x25280C5D, (q31_t)0x78848413, + (q31_t)0x2B1F34EB, (q31_t)0x7641AF3C, (q31_t)0x30FBC54D, + (q31_t)0x73B5EBD0, (q31_t)0x36BA2013, (q31_t)0x70E2CBC6, + (q31_t)0x3C56BA70, (q31_t)0x6DCA0D14, (q31_t)0x41CE1E64, + (q31_t)0x6A6D98A4, (q31_t)0x471CECE6, (q31_t)0x66CF811F, + (q31_t)0x4C3FDFF3, (q31_t)0x62F201AC, (q31_t)0x5133CC94, + (q31_t)0x5ED77C89, (q31_t)0x55F5A4D2, (q31_t)0x5A82799A, + (q31_t)0x5A82799A, (q31_t)0x55F5A4D2, (q31_t)0x5ED77C89, + (q31_t)0x5133CC94, (q31_t)0x62F201AC, (q31_t)0x4C3FDFF3, + (q31_t)0x66CF811F, (q31_t)0x471CECE6, (q31_t)0x6A6D98A4, + (q31_t)0x41CE1E64, (q31_t)0x6DCA0D14, (q31_t)0x3C56BA70, + (q31_t)0x70E2CBC6, (q31_t)0x36BA2013, (q31_t)0x73B5EBD0, + (q31_t)0x30FBC54D, (q31_t)0x7641AF3C, (q31_t)0x2B1F34EB, + (q31_t)0x78848413, (q31_t)0x25280C5D, (q31_t)0x7A7D055B, + (q31_t)0x1F19F97B, (q31_t)0x7C29FBEE, (q31_t)0x18F8B83C, + (q31_t)0x7D8A5F3F, (q31_t)0x12C8106E, (q31_t)0x7E9D55FC, + (q31_t)0x0C8BD35E, (q31_t)0x7F62368F, (q31_t)0x0647D97C, + (q31_t)0x7FD8878D, (q31_t)0x00000000, (q31_t)0x7FFFFFFF, + (q31_t)0xF9B82683, (q31_t)0x7FD8878D, (q31_t)0xF3742CA1, + (q31_t)0x7F62368F, (q31_t)0xED37EF91, (q31_t)0x7E9D55FC, + (q31_t)0xE70747C3, (q31_t)0x7D8A5F3F, (q31_t)0xE0E60684, + (q31_t)0x7C29FBEE, (q31_t)0xDAD7F3A2, (q31_t)0x7A7D055B, + (q31_t)0xD4E0CB14, (q31_t)0x78848413, (q31_t)0xCF043AB2, + (q31_t)0x7641AF3C, (q31_t)0xC945DFEC, (q31_t)0x73B5EBD0, + (q31_t)0xC3A9458F, (q31_t)0x70E2CBC6, (q31_t)0xBE31E19B, + (q31_t)0x6DCA0D14, (q31_t)0xB8E31319, (q31_t)0x6A6D98A4, + (q31_t)0xB3C0200C, (q31_t)0x66CF811F, (q31_t)0xAECC336B, + (q31_t)0x62F201AC, (q31_t)0xAA0A5B2D, (q31_t)0x5ED77C89, + (q31_t)0xA57D8666, (q31_t)0x5A82799A, (q31_t)0xA1288376, + (q31_t)0x55F5A4D2, (q31_t)0x9D0DFE53, (q31_t)0x5133CC94, + (q31_t)0x99307EE0, (q31_t)0x4C3FDFF3, (q31_t)0x9592675B, + (q31_t)0x471CECE6, (q31_t)0x9235F2EB, (q31_t)0x41CE1E64, + (q31_t)0x8F1D343A, (q31_t)0x3C56BA70, (q31_t)0x8C4A142F, + (q31_t)0x36BA2013, (q31_t)0x89BE50C3, (q31_t)0x30FBC54D, + (q31_t)0x877B7BEC, (q31_t)0x2B1F34EB, (q31_t)0x8582FAA4, + (q31_t)0x25280C5D, (q31_t)0x83D60411, (q31_t)0x1F19F97B, + (q31_t)0x8275A0C0, (q31_t)0x18F8B83C, (q31_t)0x8162AA03, + (q31_t)0x12C8106E, (q31_t)0x809DC970, (q31_t)0x0C8BD35E, + (q31_t)0x80277872, (q31_t)0x0647D97C, (q31_t)0x80000000, + (q31_t)0x00000000, (q31_t)0x80277872, (q31_t)0xF9B82683, + (q31_t)0x809DC970, (q31_t)0xF3742CA1, (q31_t)0x8162AA03, + (q31_t)0xED37EF91, (q31_t)0x8275A0C0, (q31_t)0xE70747C3, + (q31_t)0x83D60411, (q31_t)0xE0E60684, (q31_t)0x8582FAA4, + (q31_t)0xDAD7F3A2, (q31_t)0x877B7BEC, (q31_t)0xD4E0CB14, + (q31_t)0x89BE50C3, (q31_t)0xCF043AB2, (q31_t)0x8C4A142F, + (q31_t)0xC945DFEC, (q31_t)0x8F1D343A, (q31_t)0xC3A9458F, + (q31_t)0x9235F2EB, (q31_t)0xBE31E19B, (q31_t)0x9592675B, + (q31_t)0xB8E31319, (q31_t)0x99307EE0, (q31_t)0xB3C0200C, + (q31_t)0x9D0DFE53, (q31_t)0xAECC336B, (q31_t)0xA1288376, + (q31_t)0xAA0A5B2D, (q31_t)0xA57D8666, (q31_t)0xA57D8666, + (q31_t)0xAA0A5B2D, (q31_t)0xA1288376, (q31_t)0xAECC336B, + (q31_t)0x9D0DFE53, (q31_t)0xB3C0200C, (q31_t)0x99307EE0, + (q31_t)0xB8E31319, (q31_t)0x9592675B, (q31_t)0xBE31E19B, + (q31_t)0x9235F2EB, (q31_t)0xC3A9458F, (q31_t)0x8F1D343A, + (q31_t)0xC945DFEC, (q31_t)0x8C4A142F, (q31_t)0xCF043AB2, + (q31_t)0x89BE50C3, (q31_t)0xD4E0CB14, (q31_t)0x877B7BEC, + (q31_t)0xDAD7F3A2, (q31_t)0x8582FAA4, (q31_t)0xE0E60684, + (q31_t)0x83D60411, (q31_t)0xE70747C3, (q31_t)0x8275A0C0, + (q31_t)0xED37EF91, (q31_t)0x8162AA03, (q31_t)0xF3742CA1, + (q31_t)0x809DC970, (q31_t)0xF9B82683, (q31_t)0x80277872 +}; + +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_Q31_256) +/** + @par + Example code for Q31 Twiddle factors Generation:: + @par + 
for (i = 0; i< 3N/4; i++)
+  {
+     twiddleCoefQ31[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefQ31[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 256, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to Q31(Fixed point 1.31): + round(twiddleCoefQ31(i) * pow(2, 31)) + + */ +const q31_t twiddleCoef_256_q31[384] = { + (q31_t)0x7FFFFFFF, (q31_t)0x00000000, (q31_t)0x7FF62182, + (q31_t)0x03242ABF, (q31_t)0x7FD8878D, (q31_t)0x0647D97C, + (q31_t)0x7FA736B4, (q31_t)0x096A9049, (q31_t)0x7F62368F, + (q31_t)0x0C8BD35E, (q31_t)0x7F0991C3, (q31_t)0x0FAB272B, + (q31_t)0x7E9D55FC, (q31_t)0x12C8106E, (q31_t)0x7E1D93E9, + (q31_t)0x15E21444, (q31_t)0x7D8A5F3F, (q31_t)0x18F8B83C, + (q31_t)0x7CE3CEB1, (q31_t)0x1C0B826A, (q31_t)0x7C29FBEE, + (q31_t)0x1F19F97B, (q31_t)0x7B5D039D, (q31_t)0x2223A4C5, + (q31_t)0x7A7D055B, (q31_t)0x25280C5D, (q31_t)0x798A23B1, + (q31_t)0x2826B928, (q31_t)0x78848413, (q31_t)0x2B1F34EB, + (q31_t)0x776C4EDB, (q31_t)0x2E110A62, (q31_t)0x7641AF3C, + (q31_t)0x30FBC54D, (q31_t)0x7504D345, (q31_t)0x33DEF287, + (q31_t)0x73B5EBD0, (q31_t)0x36BA2013, (q31_t)0x72552C84, + (q31_t)0x398CDD32, (q31_t)0x70E2CBC6, (q31_t)0x3C56BA70, + (q31_t)0x6F5F02B1, (q31_t)0x3F1749B7, (q31_t)0x6DCA0D14, + (q31_t)0x41CE1E64, (q31_t)0x6C242960, (q31_t)0x447ACD50, + (q31_t)0x6A6D98A4, (q31_t)0x471CECE6, (q31_t)0x68A69E81, + (q31_t)0x49B41533, (q31_t)0x66CF811F, (q31_t)0x4C3FDFF3, + (q31_t)0x64E88926, (q31_t)0x4EBFE8A4, (q31_t)0x62F201AC, + (q31_t)0x5133CC94, (q31_t)0x60EC3830, (q31_t)0x539B2AEF, + (q31_t)0x5ED77C89, (q31_t)0x55F5A4D2, (q31_t)0x5CB420DF, + (q31_t)0x5842DD54, (q31_t)0x5A82799A, (q31_t)0x5A82799A, + (q31_t)0x5842DD54, (q31_t)0x5CB420DF, (q31_t)0x55F5A4D2, + (q31_t)0x5ED77C89, (q31_t)0x539B2AEF, (q31_t)0x60EC3830, + (q31_t)0x5133CC94, (q31_t)0x62F201AC, (q31_t)0x4EBFE8A4, + (q31_t)0x64E88926, (q31_t)0x4C3FDFF3, (q31_t)0x66CF811F, + (q31_t)0x49B41533, (q31_t)0x68A69E81, (q31_t)0x471CECE6, + (q31_t)0x6A6D98A4, (q31_t)0x447ACD50, (q31_t)0x6C242960, + (q31_t)0x41CE1E64, (q31_t)0x6DCA0D14, (q31_t)0x3F1749B7, + (q31_t)0x6F5F02B1, (q31_t)0x3C56BA70, (q31_t)0x70E2CBC6, + (q31_t)0x398CDD32, (q31_t)0x72552C84, (q31_t)0x36BA2013, + (q31_t)0x73B5EBD0, (q31_t)0x33DEF287, (q31_t)0x7504D345, + (q31_t)0x30FBC54D, (q31_t)0x7641AF3C, (q31_t)0x2E110A62, + (q31_t)0x776C4EDB, (q31_t)0x2B1F34EB, (q31_t)0x78848413, + (q31_t)0x2826B928, (q31_t)0x798A23B1, (q31_t)0x25280C5D, + (q31_t)0x7A7D055B, (q31_t)0x2223A4C5, (q31_t)0x7B5D039D, + (q31_t)0x1F19F97B, (q31_t)0x7C29FBEE, (q31_t)0x1C0B826A, + (q31_t)0x7CE3CEB1, (q31_t)0x18F8B83C, (q31_t)0x7D8A5F3F, + (q31_t)0x15E21444, (q31_t)0x7E1D93E9, (q31_t)0x12C8106E, + (q31_t)0x7E9D55FC, (q31_t)0x0FAB272B, (q31_t)0x7F0991C3, + (q31_t)0x0C8BD35E, (q31_t)0x7F62368F, (q31_t)0x096A9049, + (q31_t)0x7FA736B4, (q31_t)0x0647D97C, (q31_t)0x7FD8878D, + (q31_t)0x03242ABF, (q31_t)0x7FF62182, (q31_t)0x00000000, + (q31_t)0x7FFFFFFF, (q31_t)0xFCDBD541, (q31_t)0x7FF62182, + (q31_t)0xF9B82683, (q31_t)0x7FD8878D, (q31_t)0xF6956FB6, + (q31_t)0x7FA736B4, (q31_t)0xF3742CA1, (q31_t)0x7F62368F, + (q31_t)0xF054D8D4, (q31_t)0x7F0991C3, (q31_t)0xED37EF91, + (q31_t)0x7E9D55FC, (q31_t)0xEA1DEBBB, (q31_t)0x7E1D93E9, + (q31_t)0xE70747C3, (q31_t)0x7D8A5F3F, (q31_t)0xE3F47D95, + (q31_t)0x7CE3CEB1, (q31_t)0xE0E60684, (q31_t)0x7C29FBEE, + (q31_t)0xDDDC5B3A, (q31_t)0x7B5D039D, (q31_t)0xDAD7F3A2, + (q31_t)0x7A7D055B, (q31_t)0xD7D946D7, (q31_t)0x798A23B1, + (q31_t)0xD4E0CB14, (q31_t)0x78848413, (q31_t)0xD1EEF59E, + (q31_t)0x776C4EDB, (q31_t)0xCF043AB2, (q31_t)0x7641AF3C, + (q31_t)0xCC210D78, (q31_t)0x7504D345, (q31_t)0xC945DFEC, + (q31_t)0x73B5EBD0, (q31_t)0xC67322CD, (q31_t)0x72552C84, + (q31_t)0xC3A9458F, (q31_t)0x70E2CBC6, (q31_t)0xC0E8B648, + (q31_t)0x6F5F02B1, (q31_t)0xBE31E19B, (q31_t)0x6DCA0D14, + (q31_t)0xBB8532AF, (q31_t)0x6C242960, (q31_t)0xB8E31319, + (q31_t)0x6A6D98A4, (q31_t)0xB64BEACC, (q31_t)0x68A69E81, + (q31_t)0xB3C0200C, (q31_t)0x66CF811F, (q31_t)0xB140175B, + (q31_t)0x64E88926, (q31_t)0xAECC336B, (q31_t)0x62F201AC, + (q31_t)0xAC64D510, (q31_t)0x60EC3830, (q31_t)0xAA0A5B2D, + (q31_t)0x5ED77C89, (q31_t)0xA7BD22AB, (q31_t)0x5CB420DF, + (q31_t)0xA57D8666, (q31_t)0x5A82799A, (q31_t)0xA34BDF20, + (q31_t)0x5842DD54, (q31_t)0xA1288376, (q31_t)0x55F5A4D2, + (q31_t)0x9F13C7D0, (q31_t)0x539B2AEF, (q31_t)0x9D0DFE53, + (q31_t)0x5133CC94, (q31_t)0x9B1776D9, (q31_t)0x4EBFE8A4, + (q31_t)0x99307EE0, (q31_t)0x4C3FDFF3, (q31_t)0x9759617E, + (q31_t)0x49B41533, (q31_t)0x9592675B, (q31_t)0x471CECE6, + (q31_t)0x93DBD69F, (q31_t)0x447ACD50, (q31_t)0x9235F2EB, + (q31_t)0x41CE1E64, (q31_t)0x90A0FD4E, (q31_t)0x3F1749B7, + (q31_t)0x8F1D343A, (q31_t)0x3C56BA70, (q31_t)0x8DAAD37B, + (q31_t)0x398CDD32, (q31_t)0x8C4A142F, (q31_t)0x36BA2013, + (q31_t)0x8AFB2CBA, (q31_t)0x33DEF287, (q31_t)0x89BE50C3, + (q31_t)0x30FBC54D, (q31_t)0x8893B124, (q31_t)0x2E110A62, + (q31_t)0x877B7BEC, (q31_t)0x2B1F34EB, (q31_t)0x8675DC4E, + (q31_t)0x2826B928, (q31_t)0x8582FAA4, (q31_t)0x25280C5D, + (q31_t)0x84A2FC62, (q31_t)0x2223A4C5, (q31_t)0x83D60411, + (q31_t)0x1F19F97B, (q31_t)0x831C314E, (q31_t)0x1C0B826A, + (q31_t)0x8275A0C0, (q31_t)0x18F8B83C, (q31_t)0x81E26C16, + (q31_t)0x15E21444, (q31_t)0x8162AA03, (q31_t)0x12C8106E, + (q31_t)0x80F66E3C, (q31_t)0x0FAB272B, (q31_t)0x809DC970, + (q31_t)0x0C8BD35E, (q31_t)0x8058C94C, (q31_t)0x096A9049, + (q31_t)0x80277872, (q31_t)0x0647D97C, (q31_t)0x8009DE7D, + (q31_t)0x03242ABF, (q31_t)0x80000000, (q31_t)0x00000000, + (q31_t)0x8009DE7D, (q31_t)0xFCDBD541, (q31_t)0x80277872, + (q31_t)0xF9B82683, (q31_t)0x8058C94C, (q31_t)0xF6956FB6, + (q31_t)0x809DC970, (q31_t)0xF3742CA1, (q31_t)0x80F66E3C, + (q31_t)0xF054D8D4, (q31_t)0x8162AA03, (q31_t)0xED37EF91, + (q31_t)0x81E26C16, (q31_t)0xEA1DEBBB, (q31_t)0x8275A0C0, + (q31_t)0xE70747C3, (q31_t)0x831C314E, (q31_t)0xE3F47D95, + (q31_t)0x83D60411, (q31_t)0xE0E60684, (q31_t)0x84A2FC62, + (q31_t)0xDDDC5B3A, (q31_t)0x8582FAA4, (q31_t)0xDAD7F3A2, + (q31_t)0x8675DC4E, (q31_t)0xD7D946D7, (q31_t)0x877B7BEC, + (q31_t)0xD4E0CB14, (q31_t)0x8893B124, (q31_t)0xD1EEF59E, + (q31_t)0x89BE50C3, (q31_t)0xCF043AB2, (q31_t)0x8AFB2CBA, + (q31_t)0xCC210D78, (q31_t)0x8C4A142F, (q31_t)0xC945DFEC, + (q31_t)0x8DAAD37B, (q31_t)0xC67322CD, (q31_t)0x8F1D343A, + (q31_t)0xC3A9458F, (q31_t)0x90A0FD4E, (q31_t)0xC0E8B648, + (q31_t)0x9235F2EB, (q31_t)0xBE31E19B, (q31_t)0x93DBD69F, + (q31_t)0xBB8532AF, (q31_t)0x9592675B, (q31_t)0xB8E31319, + (q31_t)0x9759617E, (q31_t)0xB64BEACC, (q31_t)0x99307EE0, + (q31_t)0xB3C0200C, (q31_t)0x9B1776D9, (q31_t)0xB140175B, + (q31_t)0x9D0DFE53, (q31_t)0xAECC336B, (q31_t)0x9F13C7D0, + (q31_t)0xAC64D510, (q31_t)0xA1288376, (q31_t)0xAA0A5B2D, + (q31_t)0xA34BDF20, (q31_t)0xA7BD22AB, (q31_t)0xA57D8666, + (q31_t)0xA57D8666, (q31_t)0xA7BD22AB, (q31_t)0xA34BDF20, + (q31_t)0xAA0A5B2D, (q31_t)0xA1288376, (q31_t)0xAC64D510, + (q31_t)0x9F13C7D0, (q31_t)0xAECC336B, (q31_t)0x9D0DFE53, + (q31_t)0xB140175B, (q31_t)0x9B1776D9, (q31_t)0xB3C0200C, + (q31_t)0x99307EE0, (q31_t)0xB64BEACC, (q31_t)0x9759617E, + (q31_t)0xB8E31319, (q31_t)0x9592675B, (q31_t)0xBB8532AF, + (q31_t)0x93DBD69F, (q31_t)0xBE31E19B, (q31_t)0x9235F2EB, + (q31_t)0xC0E8B648, (q31_t)0x90A0FD4E, (q31_t)0xC3A9458F, + (q31_t)0x8F1D343A, (q31_t)0xC67322CD, (q31_t)0x8DAAD37B, + (q31_t)0xC945DFEC, (q31_t)0x8C4A142F, (q31_t)0xCC210D78, + (q31_t)0x8AFB2CBA, (q31_t)0xCF043AB2, (q31_t)0x89BE50C3, + (q31_t)0xD1EEF59E, (q31_t)0x8893B124, (q31_t)0xD4E0CB14, + (q31_t)0x877B7BEC, (q31_t)0xD7D946D7, (q31_t)0x8675DC4E, + (q31_t)0xDAD7F3A2, (q31_t)0x8582FAA4, (q31_t)0xDDDC5B3A, + (q31_t)0x84A2FC62, (q31_t)0xE0E60684, (q31_t)0x83D60411, + (q31_t)0xE3F47D95, (q31_t)0x831C314E, (q31_t)0xE70747C3, + (q31_t)0x8275A0C0, (q31_t)0xEA1DEBBB, (q31_t)0x81E26C16, + (q31_t)0xED37EF91, (q31_t)0x8162AA03, (q31_t)0xF054D8D4, + (q31_t)0x80F66E3C, (q31_t)0xF3742CA1, (q31_t)0x809DC970, + (q31_t)0xF6956FB6, (q31_t)0x8058C94C, (q31_t)0xF9B82683, + (q31_t)0x80277872, (q31_t)0xFCDBD541, (q31_t)0x8009DE7D +}; + +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_Q31_512) +/** + @par + Example code for Q31 Twiddle factors Generation:: + @par + 
for (i = 0; i< 3N/4; i++)
+  {
+     twiddleCoefQ31[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefQ31[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 512, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to Q31(Fixed point 1.31): + round(twiddleCoefQ31(i) * pow(2, 31)) + + */ +const q31_t twiddleCoef_512_q31[768] = { + (q31_t)0x7FFFFFFF, (q31_t)0x00000000, (q31_t)0x7FFD885A, + (q31_t)0x01921D1F, (q31_t)0x7FF62182, (q31_t)0x03242ABF, + (q31_t)0x7FE9CBC0, (q31_t)0x04B6195D, (q31_t)0x7FD8878D, + (q31_t)0x0647D97C, (q31_t)0x7FC25596, (q31_t)0x07D95B9E, + (q31_t)0x7FA736B4, (q31_t)0x096A9049, (q31_t)0x7F872BF3, + (q31_t)0x0AFB6805, (q31_t)0x7F62368F, (q31_t)0x0C8BD35E, + (q31_t)0x7F3857F5, (q31_t)0x0E1BC2E3, (q31_t)0x7F0991C3, + (q31_t)0x0FAB272B, (q31_t)0x7ED5E5C6, (q31_t)0x1139F0CE, + (q31_t)0x7E9D55FC, (q31_t)0x12C8106E, (q31_t)0x7E5FE493, + (q31_t)0x145576B1, (q31_t)0x7E1D93E9, (q31_t)0x15E21444, + (q31_t)0x7DD6668E, (q31_t)0x176DD9DE, (q31_t)0x7D8A5F3F, + (q31_t)0x18F8B83C, (q31_t)0x7D3980EC, (q31_t)0x1A82A025, + (q31_t)0x7CE3CEB1, (q31_t)0x1C0B826A, (q31_t)0x7C894BDD, + (q31_t)0x1D934FE5, (q31_t)0x7C29FBEE, (q31_t)0x1F19F97B, + (q31_t)0x7BC5E28F, (q31_t)0x209F701C, (q31_t)0x7B5D039D, + (q31_t)0x2223A4C5, (q31_t)0x7AEF6323, (q31_t)0x23A6887E, + (q31_t)0x7A7D055B, (q31_t)0x25280C5D, (q31_t)0x7A05EEAD, + (q31_t)0x26A82185, (q31_t)0x798A23B1, (q31_t)0x2826B928, + (q31_t)0x7909A92C, (q31_t)0x29A3C484, (q31_t)0x78848413, + (q31_t)0x2B1F34EB, (q31_t)0x77FAB988, (q31_t)0x2C98FBBA, + (q31_t)0x776C4EDB, (q31_t)0x2E110A62, (q31_t)0x76D94988, + (q31_t)0x2F875262, (q31_t)0x7641AF3C, (q31_t)0x30FBC54D, + (q31_t)0x75A585CF, (q31_t)0x326E54C7, (q31_t)0x7504D345, + (q31_t)0x33DEF287, (q31_t)0x745F9DD1, (q31_t)0x354D9056, + (q31_t)0x73B5EBD0, (q31_t)0x36BA2013, (q31_t)0x7307C3D0, + (q31_t)0x382493B0, (q31_t)0x72552C84, (q31_t)0x398CDD32, + (q31_t)0x719E2CD2, (q31_t)0x3AF2EEB7, (q31_t)0x70E2CBC6, + (q31_t)0x3C56BA70, (q31_t)0x70231099, (q31_t)0x3DB832A5, + (q31_t)0x6F5F02B1, (q31_t)0x3F1749B7, (q31_t)0x6E96A99C, + (q31_t)0x4073F21D, (q31_t)0x6DCA0D14, (q31_t)0x41CE1E64, + (q31_t)0x6CF934FB, (q31_t)0x4325C135, (q31_t)0x6C242960, + (q31_t)0x447ACD50, (q31_t)0x6B4AF278, (q31_t)0x45CD358F, + (q31_t)0x6A6D98A4, (q31_t)0x471CECE6, (q31_t)0x698C246C, + (q31_t)0x4869E664, (q31_t)0x68A69E81, (q31_t)0x49B41533, + (q31_t)0x67BD0FBC, (q31_t)0x4AFB6C97, (q31_t)0x66CF811F, + (q31_t)0x4C3FDFF3, (q31_t)0x65DDFBD3, (q31_t)0x4D8162C4, + (q31_t)0x64E88926, (q31_t)0x4EBFE8A4, (q31_t)0x63EF328F, + (q31_t)0x4FFB654D, (q31_t)0x62F201AC, (q31_t)0x5133CC94, + (q31_t)0x61F1003E, (q31_t)0x5269126E, (q31_t)0x60EC3830, + (q31_t)0x539B2AEF, (q31_t)0x5FE3B38D, (q31_t)0x54CA0A4A, + (q31_t)0x5ED77C89, (q31_t)0x55F5A4D2, (q31_t)0x5DC79D7C, + (q31_t)0x571DEEF9, (q31_t)0x5CB420DF, (q31_t)0x5842DD54, + (q31_t)0x5B9D1153, (q31_t)0x59646497, (q31_t)0x5A82799A, + (q31_t)0x5A82799A, (q31_t)0x59646497, (q31_t)0x5B9D1153, + (q31_t)0x5842DD54, (q31_t)0x5CB420DF, (q31_t)0x571DEEF9, + (q31_t)0x5DC79D7C, (q31_t)0x55F5A4D2, (q31_t)0x5ED77C89, + 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(q31_t)0x812A1A39, (q31_t)0x1139F0CE, + (q31_t)0x80F66E3C, (q31_t)0x0FAB272B, (q31_t)0x80C7A80A, + (q31_t)0x0E1BC2E3, (q31_t)0x809DC970, (q31_t)0x0C8BD35E, + (q31_t)0x8078D40D, (q31_t)0x0AFB6805, (q31_t)0x8058C94C, + (q31_t)0x096A9049, (q31_t)0x803DAA69, (q31_t)0x07D95B9E, + (q31_t)0x80277872, (q31_t)0x0647D97C, (q31_t)0x80163440, + (q31_t)0x04B6195D, (q31_t)0x8009DE7D, (q31_t)0x03242ABF, + (q31_t)0x800277A5, (q31_t)0x01921D1F, (q31_t)0x80000000, + (q31_t)0x00000000, (q31_t)0x800277A5, (q31_t)0xFE6DE2E0, + (q31_t)0x8009DE7D, (q31_t)0xFCDBD541, (q31_t)0x80163440, + (q31_t)0xFB49E6A2, (q31_t)0x80277872, (q31_t)0xF9B82683, + (q31_t)0x803DAA69, (q31_t)0xF826A461, (q31_t)0x8058C94C, + (q31_t)0xF6956FB6, (q31_t)0x8078D40D, (q31_t)0xF50497FA, + (q31_t)0x809DC970, (q31_t)0xF3742CA1, (q31_t)0x80C7A80A, + (q31_t)0xF1E43D1C, (q31_t)0x80F66E3C, (q31_t)0xF054D8D4, + (q31_t)0x812A1A39, (q31_t)0xEEC60F31, (q31_t)0x8162AA03, + (q31_t)0xED37EF91, (q31_t)0x81A01B6C, (q31_t)0xEBAA894E, + (q31_t)0x81E26C16, (q31_t)0xEA1DEBBB, (q31_t)0x82299971, + (q31_t)0xE8922621, (q31_t)0x8275A0C0, (q31_t)0xE70747C3, + (q31_t)0x82C67F13, (q31_t)0xE57D5FDA, (q31_t)0x831C314E, + (q31_t)0xE3F47D95, (q31_t)0x8376B422, (q31_t)0xE26CB01A, + (q31_t)0x83D60411, (q31_t)0xE0E60684, (q31_t)0x843A1D70, + (q31_t)0xDF608FE3, (q31_t)0x84A2FC62, (q31_t)0xDDDC5B3A, + (q31_t)0x85109CDC, (q31_t)0xDC597781, (q31_t)0x8582FAA4, + (q31_t)0xDAD7F3A2, (q31_t)0x85FA1152, (q31_t)0xD957DE7A, + (q31_t)0x8675DC4E, (q31_t)0xD7D946D7, (q31_t)0x86F656D3, + (q31_t)0xD65C3B7B, (q31_t)0x877B7BEC, (q31_t)0xD4E0CB14, + (q31_t)0x88054677, (q31_t)0xD3670445, (q31_t)0x8893B124, + (q31_t)0xD1EEF59E, (q31_t)0x8926B677, (q31_t)0xD078AD9D, + (q31_t)0x89BE50C3, (q31_t)0xCF043AB2, (q31_t)0x8A5A7A30, + (q31_t)0xCD91AB38, (q31_t)0x8AFB2CBA, (q31_t)0xCC210D78, + (q31_t)0x8BA0622F, (q31_t)0xCAB26FA9, (q31_t)0x8C4A142F, + (q31_t)0xC945DFEC, (q31_t)0x8CF83C30, (q31_t)0xC7DB6C50, + (q31_t)0x8DAAD37B, (q31_t)0xC67322CD, (q31_t)0x8E61D32D, + (q31_t)0xC50D1148, (q31_t)0x8F1D343A, (q31_t)0xC3A9458F, + (q31_t)0x8FDCEF66, (q31_t)0xC247CD5A, (q31_t)0x90A0FD4E, + (q31_t)0xC0E8B648, (q31_t)0x91695663, (q31_t)0xBF8C0DE2, + (q31_t)0x9235F2EB, (q31_t)0xBE31E19B, (q31_t)0x9306CB04, + (q31_t)0xBCDA3ECA, (q31_t)0x93DBD69F, (q31_t)0xBB8532AF, + (q31_t)0x94B50D87, (q31_t)0xBA32CA70, (q31_t)0x9592675B, + (q31_t)0xB8E31319, (q31_t)0x9673DB94, (q31_t)0xB796199B, + (q31_t)0x9759617E, (q31_t)0xB64BEACC, (q31_t)0x9842F043, + (q31_t)0xB5049368, (q31_t)0x99307EE0, (q31_t)0xB3C0200C, + (q31_t)0x9A22042C, (q31_t)0xB27E9D3B, (q31_t)0x9B1776D9, + (q31_t)0xB140175B, (q31_t)0x9C10CD70, (q31_t)0xB0049AB2, + (q31_t)0x9D0DFE53, (q31_t)0xAECC336B, (q31_t)0x9E0EFFC1, + (q31_t)0xAD96ED91, (q31_t)0x9F13C7D0, (q31_t)0xAC64D510, + (q31_t)0xA01C4C72, (q31_t)0xAB35F5B5, (q31_t)0xA1288376, + (q31_t)0xAA0A5B2D, (q31_t)0xA2386283, (q31_t)0xA8E21106, + (q31_t)0xA34BDF20, (q31_t)0xA7BD22AB, (q31_t)0xA462EEAC, + (q31_t)0xA69B9B68, (q31_t)0xA57D8666, (q31_t)0xA57D8666, + (q31_t)0xA69B9B68, (q31_t)0xA462EEAC, (q31_t)0xA7BD22AB, + (q31_t)0xA34BDF20, (q31_t)0xA8E21106, (q31_t)0xA2386283, + (q31_t)0xAA0A5B2D, (q31_t)0xA1288376, (q31_t)0xAB35F5B5, + (q31_t)0xA01C4C72, (q31_t)0xAC64D510, (q31_t)0x9F13C7D0, + (q31_t)0xAD96ED91, (q31_t)0x9E0EFFC1, (q31_t)0xAECC336B, + (q31_t)0x9D0DFE53, (q31_t)0xB0049AB2, (q31_t)0x9C10CD70, + (q31_t)0xB140175B, (q31_t)0x9B1776D9, (q31_t)0xB27E9D3B, + (q31_t)0x9A22042C, (q31_t)0xB3C0200C, (q31_t)0x99307EE0, + (q31_t)0xB5049368, (q31_t)0x9842F043, (q31_t)0xB64BEACC, + (q31_t)0x9759617E, (q31_t)0xB796199B, (q31_t)0x9673DB94, + (q31_t)0xB8E31319, (q31_t)0x9592675B, (q31_t)0xBA32CA70, + (q31_t)0x94B50D87, (q31_t)0xBB8532AF, (q31_t)0x93DBD69F, + (q31_t)0xBCDA3ECA, (q31_t)0x9306CB04, (q31_t)0xBE31E19B, + (q31_t)0x9235F2EB, (q31_t)0xBF8C0DE2, (q31_t)0x91695663, + (q31_t)0xC0E8B648, (q31_t)0x90A0FD4E, (q31_t)0xC247CD5A, + (q31_t)0x8FDCEF66, (q31_t)0xC3A9458F, (q31_t)0x8F1D343A, + (q31_t)0xC50D1148, (q31_t)0x8E61D32D, (q31_t)0xC67322CD, + (q31_t)0x8DAAD37B, (q31_t)0xC7DB6C50, (q31_t)0x8CF83C30, + (q31_t)0xC945DFEC, (q31_t)0x8C4A142F, (q31_t)0xCAB26FA9, + (q31_t)0x8BA0622F, (q31_t)0xCC210D78, (q31_t)0x8AFB2CBA, + (q31_t)0xCD91AB38, (q31_t)0x8A5A7A30, (q31_t)0xCF043AB2, + (q31_t)0x89BE50C3, (q31_t)0xD078AD9D, (q31_t)0x8926B677, + (q31_t)0xD1EEF59E, (q31_t)0x8893B124, (q31_t)0xD3670445, + (q31_t)0x88054677, (q31_t)0xD4E0CB14, (q31_t)0x877B7BEC, + (q31_t)0xD65C3B7B, (q31_t)0x86F656D3, (q31_t)0xD7D946D7, + (q31_t)0x8675DC4E, (q31_t)0xD957DE7A, (q31_t)0x85FA1152, + (q31_t)0xDAD7F3A2, (q31_t)0x8582FAA4, (q31_t)0xDC597781, + (q31_t)0x85109CDC, (q31_t)0xDDDC5B3A, (q31_t)0x84A2FC62, + (q31_t)0xDF608FE3, (q31_t)0x843A1D70, (q31_t)0xE0E60684, + (q31_t)0x83D60411, (q31_t)0xE26CB01A, (q31_t)0x8376B422, + (q31_t)0xE3F47D95, (q31_t)0x831C314E, (q31_t)0xE57D5FDA, + (q31_t)0x82C67F13, (q31_t)0xE70747C3, (q31_t)0x8275A0C0, + (q31_t)0xE8922621, (q31_t)0x82299971, (q31_t)0xEA1DEBBB, + (q31_t)0x81E26C16, (q31_t)0xEBAA894E, (q31_t)0x81A01B6C, + (q31_t)0xED37EF91, (q31_t)0x8162AA03, (q31_t)0xEEC60F31, + (q31_t)0x812A1A39, (q31_t)0xF054D8D4, (q31_t)0x80F66E3C, + (q31_t)0xF1E43D1C, (q31_t)0x80C7A80A, (q31_t)0xF3742CA1, + (q31_t)0x809DC970, (q31_t)0xF50497FA, (q31_t)0x8078D40D, + (q31_t)0xF6956FB6, (q31_t)0x8058C94C, (q31_t)0xF826A461, + (q31_t)0x803DAA69, (q31_t)0xF9B82683, (q31_t)0x80277872, + (q31_t)0xFB49E6A2, (q31_t)0x80163440, (q31_t)0xFCDBD541, + (q31_t)0x8009DE7D, (q31_t)0xFE6DE2E0, (q31_t)0x800277A5 +}; + +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_Q31_1024) +/** + @par + Example code for Q31 Twiddle factors Generation:: + @par + 
for (i = 0; i< 3N/4; i++)
+  {
+     twiddleCoefQ31[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefQ31[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 1024, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to Q31(Fixed point 1.31): + round(twiddleCoefQ31(i) * pow(2, 31)) + + */ +const q31_t twiddleCoef_1024_q31[1536] = { + (q31_t)0x7FFFFFFF, (q31_t)0x00000000, (q31_t)0x7FFF6216, + (q31_t)0x00C90F88, (q31_t)0x7FFD885A, (q31_t)0x01921D1F, + (q31_t)0x7FFA72D1, (q31_t)0x025B26D7, (q31_t)0x7FF62182, + (q31_t)0x03242ABF, (q31_t)0x7FF09477, (q31_t)0x03ED26E6, + (q31_t)0x7FE9CBC0, (q31_t)0x04B6195D, (q31_t)0x7FE1C76B, + (q31_t)0x057F0034, (q31_t)0x7FD8878D, (q31_t)0x0647D97C, + (q31_t)0x7FCE0C3E, (q31_t)0x0710A344, (q31_t)0x7FC25596, + (q31_t)0x07D95B9E, (q31_t)0x7FB563B2, (q31_t)0x08A2009A, + (q31_t)0x7FA736B4, (q31_t)0x096A9049, (q31_t)0x7F97CEBC, + (q31_t)0x0A3308BC, (q31_t)0x7F872BF3, (q31_t)0x0AFB6805, + (q31_t)0x7F754E7F, (q31_t)0x0BC3AC35, (q31_t)0x7F62368F, + (q31_t)0x0C8BD35E, (q31_t)0x7F4DE450, (q31_t)0x0D53DB92, + (q31_t)0x7F3857F5, (q31_t)0x0E1BC2E3, (q31_t)0x7F2191B4, + (q31_t)0x0EE38765, (q31_t)0x7F0991C3, (q31_t)0x0FAB272B, + (q31_t)0x7EF0585F, (q31_t)0x1072A047, (q31_t)0x7ED5E5C6, + (q31_t)0x1139F0CE, (q31_t)0x7EBA3A39, (q31_t)0x120116D4, + (q31_t)0x7E9D55FC, (q31_t)0x12C8106E, (q31_t)0x7E7F3956, + (q31_t)0x138EDBB0, (q31_t)0x7E5FE493, (q31_t)0x145576B1, + (q31_t)0x7E3F57FE, (q31_t)0x151BDF85, (q31_t)0x7E1D93E9, + (q31_t)0x15E21444, (q31_t)0x7DFA98A7, (q31_t)0x16A81305, + (q31_t)0x7DD6668E, (q31_t)0x176DD9DE, (q31_t)0x7DB0FDF7, + (q31_t)0x183366E8, (q31_t)0x7D8A5F3F, (q31_t)0x18F8B83C, + (q31_t)0x7D628AC5, (q31_t)0x19BDCBF2, (q31_t)0x7D3980EC, + (q31_t)0x1A82A025, (q31_t)0x7D0F4218, (q31_t)0x1B4732EF, + (q31_t)0x7CE3CEB1, (q31_t)0x1C0B826A, (q31_t)0x7CB72724, + (q31_t)0x1CCF8CB3, (q31_t)0x7C894BDD, (q31_t)0x1D934FE5, + (q31_t)0x7C5A3D4F, (q31_t)0x1E56CA1E, (q31_t)0x7C29FBEE, + (q31_t)0x1F19F97B, (q31_t)0x7BF88830, (q31_t)0x1FDCDC1A, + (q31_t)0x7BC5E28F, (q31_t)0x209F701C, (q31_t)0x7B920B89, + (q31_t)0x2161B39F, (q31_t)0x7B5D039D, (q31_t)0x2223A4C5, + (q31_t)0x7B26CB4F, (q31_t)0x22E541AE, (q31_t)0x7AEF6323, + (q31_t)0x23A6887E, (q31_t)0x7AB6CBA3, (q31_t)0x24677757, + (q31_t)0x7A7D055B, (q31_t)0x25280C5D, (q31_t)0x7A4210D8, + (q31_t)0x25E845B5, (q31_t)0x7A05EEAD, (q31_t)0x26A82185, + (q31_t)0x79C89F6D, (q31_t)0x27679DF4, (q31_t)0x798A23B1, + (q31_t)0x2826B928, (q31_t)0x794A7C11, (q31_t)0x28E5714A, + (q31_t)0x7909A92C, (q31_t)0x29A3C484, (q31_t)0x78C7ABA1, + (q31_t)0x2A61B101, (q31_t)0x78848413, (q31_t)0x2B1F34EB, + (q31_t)0x78403328, (q31_t)0x2BDC4E6F, (q31_t)0x77FAB988, + (q31_t)0x2C98FBBA, (q31_t)0x77B417DF, (q31_t)0x2D553AFB, + (q31_t)0x776C4EDB, (q31_t)0x2E110A62, (q31_t)0x77235F2D, + (q31_t)0x2ECC681E, (q31_t)0x76D94988, (q31_t)0x2F875262, + (q31_t)0x768E0EA5, (q31_t)0x3041C760, (q31_t)0x7641AF3C, + (q31_t)0x30FBC54D, (q31_t)0x75F42C0A, (q31_t)0x31B54A5D, + (q31_t)0x75A585CF, (q31_t)0x326E54C7, (q31_t)0x7555BD4B, + (q31_t)0x3326E2C2, (q31_t)0x7504D345, (q31_t)0x33DEF287, + (q31_t)0x74B2C883, (q31_t)0x3496824F, (q31_t)0x745F9DD1, + (q31_t)0x354D9056, (q31_t)0x740B53FA, (q31_t)0x36041AD9, + (q31_t)0x73B5EBD0, (q31_t)0x36BA2013, (q31_t)0x735F6626, + (q31_t)0x376F9E46, (q31_t)0x7307C3D0, (q31_t)0x382493B0, + (q31_t)0x72AF05A6, (q31_t)0x38D8FE93, (q31_t)0x72552C84, + (q31_t)0x398CDD32, (q31_t)0x71FA3948, (q31_t)0x3A402DD1, + (q31_t)0x719E2CD2, (q31_t)0x3AF2EEB7, (q31_t)0x71410804, + (q31_t)0x3BA51E29, (q31_t)0x70E2CBC6, (q31_t)0x3C56BA70, + (q31_t)0x708378FE, (q31_t)0x3D07C1D5, (q31_t)0x70231099, + (q31_t)0x3DB832A5, (q31_t)0x6FC19385, (q31_t)0x3E680B2C, + (q31_t)0x6F5F02B1, (q31_t)0x3F1749B7, (q31_t)0x6EFB5F12, + (q31_t)0x3FC5EC97, (q31_t)0x6E96A99C, (q31_t)0x4073F21D, + (q31_t)0x6E30E349, (q31_t)0x4121589A, (q31_t)0x6DCA0D14, + (q31_t)0x41CE1E64, (q31_t)0x6D6227FA, (q31_t)0x427A41D0, + (q31_t)0x6CF934FB, (q31_t)0x4325C135, (q31_t)0x6C8F351C, + (q31_t)0x43D09AEC, (q31_t)0x6C242960, (q31_t)0x447ACD50, + (q31_t)0x6BB812D0, (q31_t)0x452456BC, (q31_t)0x6B4AF278, + (q31_t)0x45CD358F, (q31_t)0x6ADCC964, (q31_t)0x46756827, + (q31_t)0x6A6D98A4, (q31_t)0x471CECE6, (q31_t)0x69FD614A, + (q31_t)0x47C3C22E, (q31_t)0x698C246C, (q31_t)0x4869E664, + (q31_t)0x6919E320, (q31_t)0x490F57EE, (q31_t)0x68A69E81, + (q31_t)0x49B41533, (q31_t)0x683257AA, (q31_t)0x4A581C9D, + (q31_t)0x67BD0FBC, (q31_t)0x4AFB6C97, (q31_t)0x6746C7D7, + (q31_t)0x4B9E038F, (q31_t)0x66CF811F, (q31_t)0x4C3FDFF3, + (q31_t)0x66573CBB, (q31_t)0x4CE10034, (q31_t)0x65DDFBD3, + (q31_t)0x4D8162C4, (q31_t)0x6563BF92, (q31_t)0x4E210617, + (q31_t)0x64E88926, (q31_t)0x4EBFE8A4, (q31_t)0x646C59BF, + (q31_t)0x4F5E08E3, (q31_t)0x63EF328F, (q31_t)0x4FFB654D, + (q31_t)0x637114CC, (q31_t)0x5097FC5E, (q31_t)0x62F201AC, + (q31_t)0x5133CC94, (q31_t)0x6271FA69, (q31_t)0x51CED46E, + (q31_t)0x61F1003E, (q31_t)0x5269126E, (q31_t)0x616F146B, + (q31_t)0x53028517, (q31_t)0x60EC3830, (q31_t)0x539B2AEF, + (q31_t)0x60686CCE, (q31_t)0x5433027D, (q31_t)0x5FE3B38D, + (q31_t)0x54CA0A4A, (q31_t)0x5F5E0DB3, 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(q31_t)0xF8EF5CBB, + (q31_t)0x803DAA69, (q31_t)0xF826A461, (q31_t)0x804A9C4D, + (q31_t)0xF75DFF65, (q31_t)0x8058C94C, (q31_t)0xF6956FB6, + (q31_t)0x80683143, (q31_t)0xF5CCF743, (q31_t)0x8078D40D, + (q31_t)0xF50497FA, (q31_t)0x808AB180, (q31_t)0xF43C53CA, + (q31_t)0x809DC970, (q31_t)0xF3742CA1, (q31_t)0x80B21BAF, + (q31_t)0xF2AC246D, (q31_t)0x80C7A80A, (q31_t)0xF1E43D1C, + (q31_t)0x80DE6E4C, (q31_t)0xF11C789A, (q31_t)0x80F66E3C, + (q31_t)0xF054D8D4, (q31_t)0x810FA7A0, (q31_t)0xEF8D5FB8, + (q31_t)0x812A1A39, (q31_t)0xEEC60F31, (q31_t)0x8145C5C6, + (q31_t)0xEDFEE92B, (q31_t)0x8162AA03, (q31_t)0xED37EF91, + (q31_t)0x8180C6A9, (q31_t)0xEC71244F, (q31_t)0x81A01B6C, + (q31_t)0xEBAA894E, (q31_t)0x81C0A801, (q31_t)0xEAE4207A, + (q31_t)0x81E26C16, (q31_t)0xEA1DEBBB, (q31_t)0x82056758, + (q31_t)0xE957ECFB, (q31_t)0x82299971, (q31_t)0xE8922621, + (q31_t)0x824F0208, (q31_t)0xE7CC9917, (q31_t)0x8275A0C0, + (q31_t)0xE70747C3, (q31_t)0x829D753A, (q31_t)0xE642340D, + (q31_t)0x82C67F13, (q31_t)0xE57D5FDA, (q31_t)0x82F0BDE8, + (q31_t)0xE4B8CD10, (q31_t)0x831C314E, (q31_t)0xE3F47D95, + (q31_t)0x8348D8DB, (q31_t)0xE330734C, (q31_t)0x8376B422, + (q31_t)0xE26CB01A, (q31_t)0x83A5C2B0, (q31_t)0xE1A935E1, + (q31_t)0x83D60411, (q31_t)0xE0E60684, (q31_t)0x840777CF, + (q31_t)0xE02323E5, (q31_t)0x843A1D70, (q31_t)0xDF608FE3, + (q31_t)0x846DF476, (q31_t)0xDE9E4C60, (q31_t)0x84A2FC62, + (q31_t)0xDDDC5B3A, (q31_t)0x84D934B0, (q31_t)0xDD1ABE51, + (q31_t)0x85109CDC, (q31_t)0xDC597781, (q31_t)0x8549345C, + (q31_t)0xDB9888A8, (q31_t)0x8582FAA4, (q31_t)0xDAD7F3A2, + (q31_t)0x85BDEF27, (q31_t)0xDA17BA4A, (q31_t)0x85FA1152, + (q31_t)0xD957DE7A, (q31_t)0x86376092, (q31_t)0xD898620C, + (q31_t)0x8675DC4E, (q31_t)0xD7D946D7, (q31_t)0x86B583EE, + (q31_t)0xD71A8EB5, (q31_t)0x86F656D3, (q31_t)0xD65C3B7B, + (q31_t)0x8738545E, (q31_t)0xD59E4EFE, (q31_t)0x877B7BEC, + (q31_t)0xD4E0CB14, (q31_t)0x87BFCCD7, (q31_t)0xD423B190, + (q31_t)0x88054677, (q31_t)0xD3670445, (q31_t)0x884BE820, + (q31_t)0xD2AAC504, (q31_t)0x8893B124, (q31_t)0xD1EEF59E, + (q31_t)0x88DCA0D3, (q31_t)0xD13397E1, (q31_t)0x8926B677, + (q31_t)0xD078AD9D, (q31_t)0x8971F15A, (q31_t)0xCFBE389F, + (q31_t)0x89BE50C3, (q31_t)0xCF043AB2, (q31_t)0x8A0BD3F5, + (q31_t)0xCE4AB5A2, (q31_t)0x8A5A7A30, (q31_t)0xCD91AB38, + (q31_t)0x8AAA42B4, (q31_t)0xCCD91D3D, (q31_t)0x8AFB2CBA, + (q31_t)0xCC210D78, (q31_t)0x8B4D377C, (q31_t)0xCB697DB0, + (q31_t)0x8BA0622F, (q31_t)0xCAB26FA9, (q31_t)0x8BF4AC05, + (q31_t)0xC9FBE527, (q31_t)0x8C4A142F, (q31_t)0xC945DFEC, + (q31_t)0x8CA099D9, (q31_t)0xC89061BA, (q31_t)0x8CF83C30, + (q31_t)0xC7DB6C50, (q31_t)0x8D50FA59, (q31_t)0xC727016C, + (q31_t)0x8DAAD37B, (q31_t)0xC67322CD, (q31_t)0x8E05C6B7, + (q31_t)0xC5BFD22E, (q31_t)0x8E61D32D, (q31_t)0xC50D1148, + (q31_t)0x8EBEF7FB, (q31_t)0xC45AE1D7, (q31_t)0x8F1D343A, + (q31_t)0xC3A9458F, (q31_t)0x8F7C8701, (q31_t)0xC2F83E2A, + (q31_t)0x8FDCEF66, (q31_t)0xC247CD5A, (q31_t)0x903E6C7A, + (q31_t)0xC197F4D3, (q31_t)0x90A0FD4E, (q31_t)0xC0E8B648, + (q31_t)0x9104A0ED, (q31_t)0xC03A1368, (q31_t)0x91695663, + (q31_t)0xBF8C0DE2, (q31_t)0x91CF1CB6, (q31_t)0xBEDEA765, + (q31_t)0x9235F2EB, (q31_t)0xBE31E19B, (q31_t)0x929DD805, + (q31_t)0xBD85BE2F, (q31_t)0x9306CB04, (q31_t)0xBCDA3ECA, + (q31_t)0x9370CAE4, (q31_t)0xBC2F6513, (q31_t)0x93DBD69F, + (q31_t)0xBB8532AF, (q31_t)0x9447ED2F, (q31_t)0xBADBA943, + (q31_t)0x94B50D87, (q31_t)0xBA32CA70, (q31_t)0x9523369B, + (q31_t)0xB98A97D8, (q31_t)0x9592675B, (q31_t)0xB8E31319, + (q31_t)0x96029EB5, (q31_t)0xB83C3DD1, (q31_t)0x9673DB94, + (q31_t)0xB796199B, (q31_t)0x96E61CDF, (q31_t)0xB6F0A811, + (q31_t)0x9759617E, (q31_t)0xB64BEACC, (q31_t)0x97CDA855, + (q31_t)0xB5A7E362, (q31_t)0x9842F043, (q31_t)0xB5049368, + (q31_t)0x98B93828, (q31_t)0xB461FC70, (q31_t)0x99307EE0, + (q31_t)0xB3C0200C, (q31_t)0x99A8C344, (q31_t)0xB31EFFCB, + (q31_t)0x9A22042C, (q31_t)0xB27E9D3B, (q31_t)0x9A9C406D, + (q31_t)0xB1DEF9E8, (q31_t)0x9B1776D9, (q31_t)0xB140175B, + (q31_t)0x9B93A640, (q31_t)0xB0A1F71C, (q31_t)0x9C10CD70, + (q31_t)0xB0049AB2, (q31_t)0x9C8EEB33, (q31_t)0xAF6803A1, + (q31_t)0x9D0DFE53, (q31_t)0xAECC336B, (q31_t)0x9D8E0596, + (q31_t)0xAE312B91, (q31_t)0x9E0EFFC1, (q31_t)0xAD96ED91, + (q31_t)0x9E90EB94, (q31_t)0xACFD7AE8, (q31_t)0x9F13C7D0, + (q31_t)0xAC64D510, (q31_t)0x9F979331, (q31_t)0xABCCFD82, + (q31_t)0xA01C4C72, (q31_t)0xAB35F5B5, (q31_t)0xA0A1F24C, + (q31_t)0xAA9FBF1D, (q31_t)0xA1288376, (q31_t)0xAA0A5B2D, + (q31_t)0xA1AFFEA2, (q31_t)0xA975CB56, (q31_t)0xA2386283, + (q31_t)0xA8E21106, (q31_t)0xA2C1ADC9, (q31_t)0xA84F2DA9, + (q31_t)0xA34BDF20, (q31_t)0xA7BD22AB, (q31_t)0xA3D6F533, + (q31_t)0xA72BF173, (q31_t)0xA462EEAC, (q31_t)0xA69B9B68, + (q31_t)0xA4EFCA31, (q31_t)0xA60C21ED, (q31_t)0xA57D8666, + (q31_t)0xA57D8666, (q31_t)0xA60C21ED, (q31_t)0xA4EFCA31, + (q31_t)0xA69B9B68, (q31_t)0xA462EEAC, (q31_t)0xA72BF173, + (q31_t)0xA3D6F533, (q31_t)0xA7BD22AB, (q31_t)0xA34BDF20, + (q31_t)0xA84F2DA9, (q31_t)0xA2C1ADC9, (q31_t)0xA8E21106, + (q31_t)0xA2386283, (q31_t)0xA975CB56, (q31_t)0xA1AFFEA2, + (q31_t)0xAA0A5B2D, (q31_t)0xA1288376, (q31_t)0xAA9FBF1D, + (q31_t)0xA0A1F24C, (q31_t)0xAB35F5B5, (q31_t)0xA01C4C72, + (q31_t)0xABCCFD82, (q31_t)0x9F979331, (q31_t)0xAC64D510, + (q31_t)0x9F13C7D0, (q31_t)0xACFD7AE8, (q31_t)0x9E90EB94, + (q31_t)0xAD96ED91, (q31_t)0x9E0EFFC1, (q31_t)0xAE312B91, + (q31_t)0x9D8E0596, (q31_t)0xAECC336B, (q31_t)0x9D0DFE53, + (q31_t)0xAF6803A1, (q31_t)0x9C8EEB33, (q31_t)0xB0049AB2, + (q31_t)0x9C10CD70, (q31_t)0xB0A1F71C, (q31_t)0x9B93A640, + (q31_t)0xB140175B, (q31_t)0x9B1776D9, (q31_t)0xB1DEF9E8, + (q31_t)0x9A9C406D, (q31_t)0xB27E9D3B, (q31_t)0x9A22042C, + (q31_t)0xB31EFFCB, (q31_t)0x99A8C344, (q31_t)0xB3C0200C, + (q31_t)0x99307EE0, (q31_t)0xB461FC70, (q31_t)0x98B93828, + (q31_t)0xB5049368, (q31_t)0x9842F043, (q31_t)0xB5A7E362, + (q31_t)0x97CDA855, (q31_t)0xB64BEACC, (q31_t)0x9759617E, + (q31_t)0xB6F0A811, (q31_t)0x96E61CDF, (q31_t)0xB796199B, + (q31_t)0x9673DB94, (q31_t)0xB83C3DD1, (q31_t)0x96029EB5, + (q31_t)0xB8E31319, (q31_t)0x9592675B, (q31_t)0xB98A97D8, + (q31_t)0x9523369B, (q31_t)0xBA32CA70, (q31_t)0x94B50D87, + (q31_t)0xBADBA943, (q31_t)0x9447ED2F, (q31_t)0xBB8532AF, + (q31_t)0x93DBD69F, (q31_t)0xBC2F6513, (q31_t)0x9370CAE4, + (q31_t)0xBCDA3ECA, (q31_t)0x9306CB04, (q31_t)0xBD85BE2F, + (q31_t)0x929DD805, (q31_t)0xBE31E19B, (q31_t)0x9235F2EB, + (q31_t)0xBEDEA765, (q31_t)0x91CF1CB6, (q31_t)0xBF8C0DE2, + (q31_t)0x91695663, (q31_t)0xC03A1368, (q31_t)0x9104A0ED, + (q31_t)0xC0E8B648, (q31_t)0x90A0FD4E, (q31_t)0xC197F4D3, + (q31_t)0x903E6C7A, (q31_t)0xC247CD5A, (q31_t)0x8FDCEF66, + (q31_t)0xC2F83E2A, (q31_t)0x8F7C8701, (q31_t)0xC3A9458F, + (q31_t)0x8F1D343A, (q31_t)0xC45AE1D7, (q31_t)0x8EBEF7FB, + (q31_t)0xC50D1148, (q31_t)0x8E61D32D, (q31_t)0xC5BFD22E, + (q31_t)0x8E05C6B7, (q31_t)0xC67322CD, (q31_t)0x8DAAD37B, + (q31_t)0xC727016C, (q31_t)0x8D50FA59, (q31_t)0xC7DB6C50, + (q31_t)0x8CF83C30, (q31_t)0xC89061BA, (q31_t)0x8CA099D9, + (q31_t)0xC945DFEC, (q31_t)0x8C4A142F, (q31_t)0xC9FBE527, + (q31_t)0x8BF4AC05, (q31_t)0xCAB26FA9, (q31_t)0x8BA0622F, + (q31_t)0xCB697DB0, (q31_t)0x8B4D377C, (q31_t)0xCC210D78, + (q31_t)0x8AFB2CBA, (q31_t)0xCCD91D3D, (q31_t)0x8AAA42B4, + (q31_t)0xCD91AB38, (q31_t)0x8A5A7A30, (q31_t)0xCE4AB5A2, + (q31_t)0x8A0BD3F5, (q31_t)0xCF043AB2, (q31_t)0x89BE50C3, + (q31_t)0xCFBE389F, (q31_t)0x8971F15A, (q31_t)0xD078AD9D, + (q31_t)0x8926B677, (q31_t)0xD13397E1, (q31_t)0x88DCA0D3, + (q31_t)0xD1EEF59E, (q31_t)0x8893B124, (q31_t)0xD2AAC504, + (q31_t)0x884BE820, (q31_t)0xD3670445, (q31_t)0x88054677, + (q31_t)0xD423B190, (q31_t)0x87BFCCD7, (q31_t)0xD4E0CB14, + (q31_t)0x877B7BEC, (q31_t)0xD59E4EFE, (q31_t)0x8738545E, + (q31_t)0xD65C3B7B, (q31_t)0x86F656D3, (q31_t)0xD71A8EB5, + (q31_t)0x86B583EE, (q31_t)0xD7D946D7, (q31_t)0x8675DC4E, + (q31_t)0xD898620C, (q31_t)0x86376092, (q31_t)0xD957DE7A, + (q31_t)0x85FA1152, (q31_t)0xDA17BA4A, (q31_t)0x85BDEF27, + (q31_t)0xDAD7F3A2, (q31_t)0x8582FAA4, (q31_t)0xDB9888A8, + (q31_t)0x8549345C, (q31_t)0xDC597781, (q31_t)0x85109CDC, + (q31_t)0xDD1ABE51, (q31_t)0x84D934B0, (q31_t)0xDDDC5B3A, + (q31_t)0x84A2FC62, (q31_t)0xDE9E4C60, (q31_t)0x846DF476, + (q31_t)0xDF608FE3, (q31_t)0x843A1D70, (q31_t)0xE02323E5, + (q31_t)0x840777CF, (q31_t)0xE0E60684, (q31_t)0x83D60411, + (q31_t)0xE1A935E1, (q31_t)0x83A5C2B0, (q31_t)0xE26CB01A, + (q31_t)0x8376B422, (q31_t)0xE330734C, (q31_t)0x8348D8DB, + (q31_t)0xE3F47D95, (q31_t)0x831C314E, (q31_t)0xE4B8CD10, + (q31_t)0x82F0BDE8, (q31_t)0xE57D5FDA, (q31_t)0x82C67F13, + (q31_t)0xE642340D, (q31_t)0x829D753A, (q31_t)0xE70747C3, + (q31_t)0x8275A0C0, (q31_t)0xE7CC9917, (q31_t)0x824F0208, + (q31_t)0xE8922621, (q31_t)0x82299971, (q31_t)0xE957ECFB, + (q31_t)0x82056758, (q31_t)0xEA1DEBBB, (q31_t)0x81E26C16, + (q31_t)0xEAE4207A, (q31_t)0x81C0A801, (q31_t)0xEBAA894E, + (q31_t)0x81A01B6C, (q31_t)0xEC71244F, (q31_t)0x8180C6A9, + (q31_t)0xED37EF91, (q31_t)0x8162AA03, (q31_t)0xEDFEE92B, + (q31_t)0x8145C5C6, (q31_t)0xEEC60F31, (q31_t)0x812A1A39, + (q31_t)0xEF8D5FB8, (q31_t)0x810FA7A0, (q31_t)0xF054D8D4, + (q31_t)0x80F66E3C, (q31_t)0xF11C789A, (q31_t)0x80DE6E4C, + (q31_t)0xF1E43D1C, (q31_t)0x80C7A80A, (q31_t)0xF2AC246D, + (q31_t)0x80B21BAF, (q31_t)0xF3742CA1, (q31_t)0x809DC970, + (q31_t)0xF43C53CA, (q31_t)0x808AB180, (q31_t)0xF50497FA, + (q31_t)0x8078D40D, (q31_t)0xF5CCF743, (q31_t)0x80683143, + (q31_t)0xF6956FB6, (q31_t)0x8058C94C, (q31_t)0xF75DFF65, + (q31_t)0x804A9C4D, (q31_t)0xF826A461, (q31_t)0x803DAA69, + (q31_t)0xF8EF5CBB, (q31_t)0x8031F3C1, (q31_t)0xF9B82683, + (q31_t)0x80277872, (q31_t)0xFA80FFCB, (q31_t)0x801E3894, + (q31_t)0xFB49E6A2, (q31_t)0x80163440, (q31_t)0xFC12D919, + (q31_t)0x800F6B88, (q31_t)0xFCDBD541, (q31_t)0x8009DE7D, + (q31_t)0xFDA4D928, (q31_t)0x80058D2E, (q31_t)0xFE6DE2E0, + (q31_t)0x800277A5, (q31_t)0xFF36F078, (q31_t)0x80009DE9 +}; + +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_Q31_2048) +/** + @par + Example code for Q31 Twiddle factors Generation:: + @par + 
for (i = 0; i< 3N/4; i++)
+  {
+     twiddleCoefQ31[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefQ31[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 2048, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to Q31(Fixed point 1.31): + round(twiddleCoefQ31(i) * pow(2, 31)) + */ +const q31_t twiddleCoef_2048_q31[3072] = { + (q31_t)0x7FFFFFFF, (q31_t)0x00000000, (q31_t)0x7FFFD885, + (q31_t)0x006487E3, (q31_t)0x7FFF6216, (q31_t)0x00C90F88, + (q31_t)0x7FFE9CB2, (q31_t)0x012D96B0, (q31_t)0x7FFD885A, + (q31_t)0x01921D1F, (q31_t)0x7FFC250F, (q31_t)0x01F6A296, + (q31_t)0x7FFA72D1, (q31_t)0x025B26D7, (q31_t)0x7FF871A1, + (q31_t)0x02BFA9A4, (q31_t)0x7FF62182, (q31_t)0x03242ABF, + (q31_t)0x7FF38273, (q31_t)0x0388A9E9, (q31_t)0x7FF09477, + (q31_t)0x03ED26E6, (q31_t)0x7FED5790, (q31_t)0x0451A176, + (q31_t)0x7FE9CBC0, (q31_t)0x04B6195D, (q31_t)0x7FE5F108, + (q31_t)0x051A8E5C, (q31_t)0x7FE1C76B, (q31_t)0x057F0034, + (q31_t)0x7FDD4EEC, (q31_t)0x05E36EA9, (q31_t)0x7FD8878D, + (q31_t)0x0647D97C, (q31_t)0x7FD37152, (q31_t)0x06AC406F, + (q31_t)0x7FCE0C3E, (q31_t)0x0710A344, (q31_t)0x7FC85853, + (q31_t)0x077501BE, (q31_t)0x7FC25596, (q31_t)0x07D95B9E, + (q31_t)0x7FBC040A, (q31_t)0x083DB0A7, (q31_t)0x7FB563B2, + (q31_t)0x08A2009A, (q31_t)0x7FAE7494, (q31_t)0x09064B3A, + (q31_t)0x7FA736B4, (q31_t)0x096A9049, (q31_t)0x7F9FAA15, + (q31_t)0x09CECF89, (q31_t)0x7F97CEBC, (q31_t)0x0A3308BC, + (q31_t)0x7F8FA4AF, (q31_t)0x0A973BA5, (q31_t)0x7F872BF3, + (q31_t)0x0AFB6805, (q31_t)0x7F7E648B, (q31_t)0x0B5F8D9F, + (q31_t)0x7F754E7F, (q31_t)0x0BC3AC35, (q31_t)0x7F6BE9D4, + (q31_t)0x0C27C389, (q31_t)0x7F62368F, (q31_t)0x0C8BD35E, + (q31_t)0x7F5834B6, (q31_t)0x0CEFDB75, (q31_t)0x7F4DE450, + (q31_t)0x0D53DB92, (q31_t)0x7F434563, (q31_t)0x0DB7D376, + (q31_t)0x7F3857F5, (q31_t)0x0E1BC2E3, (q31_t)0x7F2D1C0E, + (q31_t)0x0E7FA99D, (q31_t)0x7F2191B4, (q31_t)0x0EE38765, + (q31_t)0x7F15B8EE, (q31_t)0x0F475BFE, (q31_t)0x7F0991C3, + (q31_t)0x0FAB272B, (q31_t)0x7EFD1C3C, (q31_t)0x100EE8AD, + (q31_t)0x7EF0585F, (q31_t)0x1072A047, (q31_t)0x7EE34635, + (q31_t)0x10D64DBC, (q31_t)0x7ED5E5C6, (q31_t)0x1139F0CE, + (q31_t)0x7EC8371A, (q31_t)0x119D8940, (q31_t)0x7EBA3A39, + (q31_t)0x120116D4, (q31_t)0x7EABEF2C, (q31_t)0x1264994E, + (q31_t)0x7E9D55FC, (q31_t)0x12C8106E, (q31_t)0x7E8E6EB1, + (q31_t)0x132B7BF9, (q31_t)0x7E7F3956, (q31_t)0x138EDBB0, + (q31_t)0x7E6FB5F3, (q31_t)0x13F22F57, (q31_t)0x7E5FE493, + (q31_t)0x145576B1, (q31_t)0x7E4FC53E, (q31_t)0x14B8B17F, + (q31_t)0x7E3F57FE, (q31_t)0x151BDF85, (q31_t)0x7E2E9CDF, + (q31_t)0x157F0086, (q31_t)0x7E1D93E9, (q31_t)0x15E21444, + (q31_t)0x7E0C3D29, (q31_t)0x16451A83, (q31_t)0x7DFA98A7, + (q31_t)0x16A81305, (q31_t)0x7DE8A670, (q31_t)0x170AFD8D, + (q31_t)0x7DD6668E, (q31_t)0x176DD9DE, (q31_t)0x7DC3D90D, + (q31_t)0x17D0A7BB, (q31_t)0x7DB0FDF7, (q31_t)0x183366E8, + (q31_t)0x7D9DD55A, (q31_t)0x18961727, (q31_t)0x7D8A5F3F, + (q31_t)0x18F8B83C, (q31_t)0x7D769BB5, (q31_t)0x195B49E9, + (q31_t)0x7D628AC5, (q31_t)0x19BDCBF2, (q31_t)0x7D4E2C7E, + (q31_t)0x1A203E1B, (q31_t)0x7D3980EC, (q31_t)0x1A82A025, + (q31_t)0x7D24881A, (q31_t)0x1AE4F1D6, (q31_t)0x7D0F4218, + (q31_t)0x1B4732EF, (q31_t)0x7CF9AEF0, (q31_t)0x1BA96334, + (q31_t)0x7CE3CEB1, (q31_t)0x1C0B826A, (q31_t)0x7CCDA168, + (q31_t)0x1C6D9053, (q31_t)0x7CB72724, (q31_t)0x1CCF8CB3, + (q31_t)0x7CA05FF1, (q31_t)0x1D31774D, (q31_t)0x7C894BDD, + (q31_t)0x1D934FE5, (q31_t)0x7C71EAF8, (q31_t)0x1DF5163F, + (q31_t)0x7C5A3D4F, (q31_t)0x1E56CA1E, (q31_t)0x7C4242F2, + (q31_t)0x1EB86B46, (q31_t)0x7C29FBEE, (q31_t)0x1F19F97B, + (q31_t)0x7C116853, (q31_t)0x1F7B7480, (q31_t)0x7BF88830, + (q31_t)0x1FDCDC1A, (q31_t)0x7BDF5B94, (q31_t)0x203E300D, + (q31_t)0x7BC5E28F, (q31_t)0x209F701C, (q31_t)0x7BAC1D31, + (q31_t)0x21009C0B, (q31_t)0x7B920B89, (q31_t)0x2161B39F, + (q31_t)0x7B77ADA8, (q31_t)0x21C2B69C, (q31_t)0x7B5D039D, + (q31_t)0x2223A4C5, (q31_t)0x7B420D7A, (q31_t)0x22847DDF, + (q31_t)0x7B26CB4F, (q31_t)0x22E541AE, (q31_t)0x7B0B3D2C, + (q31_t)0x2345EFF7, (q31_t)0x7AEF6323, (q31_t)0x23A6887E, + (q31_t)0x7AD33D45, (q31_t)0x24070B07, (q31_t)0x7AB6CBA3, + (q31_t)0x24677757, (q31_t)0x7A9A0E4F, (q31_t)0x24C7CD32, + (q31_t)0x7A7D055B, (q31_t)0x25280C5D, (q31_t)0x7A5FB0D8, + (q31_t)0x2588349D, (q31_t)0x7A4210D8, (q31_t)0x25E845B5, + (q31_t)0x7A24256E, (q31_t)0x26483F6C, (q31_t)0x7A05EEAD, + (q31_t)0x26A82185, (q31_t)0x79E76CA6, (q31_t)0x2707EBC6, + (q31_t)0x79C89F6D, (q31_t)0x27679DF4, (q31_t)0x79A98715, + (q31_t)0x27C737D2, (q31_t)0x798A23B1, (q31_t)0x2826B928, + (q31_t)0x796A7554, (q31_t)0x288621B9, (q31_t)0x794A7C11, + (q31_t)0x28E5714A, (q31_t)0x792A37FE, (q31_t)0x2944A7A2, + (q31_t)0x7909A92C, (q31_t)0x29A3C484, (q31_t)0x78E8CFB1, + (q31_t)0x2A02C7B8, (q31_t)0x78C7ABA1, (q31_t)0x2A61B101, + (q31_t)0x78A63D10, (q31_t)0x2AC08025, (q31_t)0x78848413, + (q31_t)0x2B1F34EB, (q31_t)0x786280BF, (q31_t)0x2B7DCF17, + (q31_t)0x78403328, (q31_t)0x2BDC4E6F, (q31_t)0x781D9B64, + (q31_t)0x2C3AB2B9, (q31_t)0x77FAB988, (q31_t)0x2C98FBBA, + (q31_t)0x77D78DAA, (q31_t)0x2CF72939, (q31_t)0x77B417DF, + (q31_t)0x2D553AFB, (q31_t)0x7790583D, (q31_t)0x2DB330C7, + (q31_t)0x776C4EDB, (q31_t)0x2E110A62, (q31_t)0x7747FBCE, + (q31_t)0x2E6EC792, (q31_t)0x77235F2D, (q31_t)0x2ECC681E, + (q31_t)0x76FE790E, (q31_t)0x2F29EBCC, (q31_t)0x76D94988, + (q31_t)0x2F875262, (q31_t)0x76B3D0B3, (q31_t)0x2FE49BA6, + (q31_t)0x768E0EA5, (q31_t)0x3041C760, (q31_t)0x76680376, + (q31_t)0x309ED555, (q31_t)0x7641AF3C, (q31_t)0x30FBC54D, + (q31_t)0x761B1211, (q31_t)0x3158970D, (q31_t)0x75F42C0A, + (q31_t)0x31B54A5D, (q31_t)0x75CCFD42, (q31_t)0x3211DF03, + (q31_t)0x75A585CF, (q31_t)0x326E54C7, (q31_t)0x757DC5CA, + (q31_t)0x32CAAB6F, (q31_t)0x7555BD4B, (q31_t)0x3326E2C2, + (q31_t)0x752D6C6C, (q31_t)0x3382FA88, (q31_t)0x7504D345, + (q31_t)0x33DEF287, (q31_t)0x74DBF1EF, (q31_t)0x343ACA87, + (q31_t)0x74B2C883, (q31_t)0x3496824F, (q31_t)0x7489571B, + (q31_t)0x34F219A7, (q31_t)0x745F9DD1, (q31_t)0x354D9056, + (q31_t)0x74359CBD, (q31_t)0x35A8E624, (q31_t)0x740B53FA, + (q31_t)0x36041AD9, (q31_t)0x73E0C3A3, (q31_t)0x365F2E3B, + (q31_t)0x73B5EBD0, (q31_t)0x36BA2013, (q31_t)0x738ACC9E, + (q31_t)0x3714F02A, (q31_t)0x735F6626, (q31_t)0x376F9E46, + (q31_t)0x7333B883, (q31_t)0x37CA2A30, (q31_t)0x7307C3D0, + (q31_t)0x382493B0, (q31_t)0x72DB8828, (q31_t)0x387EDA8E, + (q31_t)0x72AF05A6, (q31_t)0x38D8FE93, (q31_t)0x72823C66, + (q31_t)0x3932FF87, (q31_t)0x72552C84, (q31_t)0x398CDD32, + (q31_t)0x7227D61C, (q31_t)0x39E6975D, (q31_t)0x71FA3948, + (q31_t)0x3A402DD1, (q31_t)0x71CC5626, (q31_t)0x3A99A057, + (q31_t)0x719E2CD2, (q31_t)0x3AF2EEB7, (q31_t)0x716FBD68, + (q31_t)0x3B4C18BA, (q31_t)0x71410804, (q31_t)0x3BA51E29, + (q31_t)0x71120CC5, (q31_t)0x3BFDFECD, (q31_t)0x70E2CBC6, + (q31_t)0x3C56BA70, (q31_t)0x70B34524, (q31_t)0x3CAF50DA, + (q31_t)0x708378FE, (q31_t)0x3D07C1D5, (q31_t)0x70536771, + (q31_t)0x3D600D2B, (q31_t)0x70231099, (q31_t)0x3DB832A5, + (q31_t)0x6FF27496, (q31_t)0x3E10320D, (q31_t)0x6FC19385, + (q31_t)0x3E680B2C, (q31_t)0x6F906D84, (q31_t)0x3EBFBDCC, + (q31_t)0x6F5F02B1, (q31_t)0x3F1749B7, (q31_t)0x6F2D532C, + (q31_t)0x3F6EAEB8, (q31_t)0x6EFB5F12, (q31_t)0x3FC5EC97, + (q31_t)0x6EC92682, (q31_t)0x401D0320, (q31_t)0x6E96A99C, + (q31_t)0x4073F21D, (q31_t)0x6E63E87F, (q31_t)0x40CAB957, + (q31_t)0x6E30E349, (q31_t)0x4121589A, (q31_t)0x6DFD9A1B, + (q31_t)0x4177CFB0, (q31_t)0x6DCA0D14, (q31_t)0x41CE1E64, + (q31_t)0x6D963C54, (q31_t)0x42244480, (q31_t)0x6D6227FA, + (q31_t)0x427A41D0, (q31_t)0x6D2DD027, (q31_t)0x42D0161E, + (q31_t)0x6CF934FB, (q31_t)0x4325C135, (q31_t)0x6CC45697, + (q31_t)0x437B42E1, (q31_t)0x6C8F351C, (q31_t)0x43D09AEC, + (q31_t)0x6C59D0A9, (q31_t)0x4425C923, (q31_t)0x6C242960, + (q31_t)0x447ACD50, (q31_t)0x6BEE3F62, (q31_t)0x44CFA73F, + (q31_t)0x6BB812D0, (q31_t)0x452456BC, (q31_t)0x6B81A3CD, + (q31_t)0x4578DB93, (q31_t)0x6B4AF278, (q31_t)0x45CD358F, + (q31_t)0x6B13FEF5, (q31_t)0x4621647C, (q31_t)0x6ADCC964, + (q31_t)0x46756827, (q31_t)0x6AA551E8, (q31_t)0x46C9405C, + (q31_t)0x6A6D98A4, (q31_t)0x471CECE6, (q31_t)0x6A359DB9, + (q31_t)0x47706D93, (q31_t)0x69FD614A, (q31_t)0x47C3C22E, + (q31_t)0x69C4E37A, (q31_t)0x4816EA85, (q31_t)0x698C246C, + (q31_t)0x4869E664, (q31_t)0x69532442, (q31_t)0x48BCB598, + (q31_t)0x6919E320, (q31_t)0x490F57EE, (q31_t)0x68E06129, + (q31_t)0x4961CD32, (q31_t)0x68A69E81, (q31_t)0x49B41533, + (q31_t)0x686C9B4B, (q31_t)0x4A062FBD, (q31_t)0x683257AA, + (q31_t)0x4A581C9D, (q31_t)0x67F7D3C4, (q31_t)0x4AA9DBA1, + (q31_t)0x67BD0FBC, (q31_t)0x4AFB6C97, (q31_t)0x67820BB6, + (q31_t)0x4B4CCF4D, (q31_t)0x6746C7D7, (q31_t)0x4B9E038F, + (q31_t)0x670B4443, (q31_t)0x4BEF092D, (q31_t)0x66CF811F, + (q31_t)0x4C3FDFF3, (q31_t)0x66937E90, (q31_t)0x4C9087B1, + (q31_t)0x66573CBB, (q31_t)0x4CE10034, (q31_t)0x661ABBC5, + (q31_t)0x4D31494B, (q31_t)0x65DDFBD3, (q31_t)0x4D8162C4, + (q31_t)0x65A0FD0B, (q31_t)0x4DD14C6E, (q31_t)0x6563BF92, + (q31_t)0x4E210617, (q31_t)0x6526438E, (q31_t)0x4E708F8F, + (q31_t)0x64E88926, (q31_t)0x4EBFE8A4, (q31_t)0x64AA907F, + (q31_t)0x4F0F1126, (q31_t)0x646C59BF, (q31_t)0x4F5E08E3, + (q31_t)0x642DE50D, (q31_t)0x4FACCFAB, (q31_t)0x63EF328F, + (q31_t)0x4FFB654D, (q31_t)0x63B0426D, (q31_t)0x5049C999, + (q31_t)0x637114CC, (q31_t)0x5097FC5E, (q31_t)0x6331A9D4, + (q31_t)0x50E5FD6C, (q31_t)0x62F201AC, (q31_t)0x5133CC94, + (q31_t)0x62B21C7B, (q31_t)0x518169A4, (q31_t)0x6271FA69, + (q31_t)0x51CED46E, (q31_t)0x62319B9D, (q31_t)0x521C0CC1, + (q31_t)0x61F1003E, (q31_t)0x5269126E, (q31_t)0x61B02876, + (q31_t)0x52B5E545, (q31_t)0x616F146B, (q31_t)0x53028517, + (q31_t)0x612DC446, (q31_t)0x534EF1B5, (q31_t)0x60EC3830, + (q31_t)0x539B2AEF, (q31_t)0x60AA704F, (q31_t)0x53E73097, + (q31_t)0x60686CCE, (q31_t)0x5433027D, (q31_t)0x60262DD5, + (q31_t)0x547EA073, (q31_t)0x5FE3B38D, (q31_t)0x54CA0A4A, + (q31_t)0x5FA0FE1E, (q31_t)0x55153FD4, (q31_t)0x5F5E0DB3, + (q31_t)0x556040E2, (q31_t)0x5F1AE273, (q31_t)0x55AB0D46, + (q31_t)0x5ED77C89, (q31_t)0x55F5A4D2, (q31_t)0x5E93DC1F, + (q31_t)0x56400757, (q31_t)0x5E50015D, (q31_t)0x568A34A9, + (q31_t)0x5E0BEC6E, (q31_t)0x56D42C99, (q31_t)0x5DC79D7C, + (q31_t)0x571DEEF9, (q31_t)0x5D8314B0, (q31_t)0x57677B9D, + (q31_t)0x5D3E5236, (q31_t)0x57B0D256, (q31_t)0x5CF95638, + (q31_t)0x57F9F2F7, (q31_t)0x5CB420DF, (q31_t)0x5842DD54, + (q31_t)0x5C6EB258, (q31_t)0x588B913F, (q31_t)0x5C290ACC, + (q31_t)0x58D40E8C, (q31_t)0x5BE32A67, (q31_t)0x591C550E, + (q31_t)0x5B9D1153, (q31_t)0x59646497, (q31_t)0x5B56BFBD, + (q31_t)0x59AC3CFD, (q31_t)0x5B1035CF, (q31_t)0x59F3DE12, + (q31_t)0x5AC973B4, (q31_t)0x5A3B47AA, (q31_t)0x5A82799A, + (q31_t)0x5A82799A, (q31_t)0x5A3B47AA, (q31_t)0x5AC973B4, + (q31_t)0x59F3DE12, (q31_t)0x5B1035CF, (q31_t)0x59AC3CFD, + (q31_t)0x5B56BFBD, (q31_t)0x59646497, (q31_t)0x5B9D1153, + (q31_t)0x591C550E, (q31_t)0x5BE32A67, (q31_t)0x58D40E8C, + (q31_t)0x5C290ACC, (q31_t)0x588B913F, (q31_t)0x5C6EB258, + (q31_t)0x5842DD54, (q31_t)0x5CB420DF, (q31_t)0x57F9F2F7, + (q31_t)0x5CF95638, (q31_t)0x57B0D256, (q31_t)0x5D3E5236, + (q31_t)0x57677B9D, (q31_t)0x5D8314B0, (q31_t)0x571DEEF9, + (q31_t)0x5DC79D7C, (q31_t)0x56D42C99, (q31_t)0x5E0BEC6E, + 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(q31_t)0x9447ED2F, (q31_t)0xBB3058C0, + (q31_t)0x9411C09D, (q31_t)0xBB8532AF, (q31_t)0x93DBD69F, + (q31_t)0xBBDA36DC, (q31_t)0x93A62F56, (q31_t)0xBC2F6513, + (q31_t)0x9370CAE4, (q31_t)0xBC84BD1E, (q31_t)0x933BA968, + (q31_t)0xBCDA3ECA, (q31_t)0x9306CB04, (q31_t)0xBD2FE9E1, + (q31_t)0x92D22FD8, (q31_t)0xBD85BE2F, (q31_t)0x929DD805, + (q31_t)0xBDDBBB7F, (q31_t)0x9269C3AC, (q31_t)0xBE31E19B, + (q31_t)0x9235F2EB, (q31_t)0xBE88304F, (q31_t)0x920265E4, + (q31_t)0xBEDEA765, (q31_t)0x91CF1CB6, (q31_t)0xBF3546A8, + (q31_t)0x919C1780, (q31_t)0xBF8C0DE2, (q31_t)0x91695663, + (q31_t)0xBFE2FCDF, (q31_t)0x9136D97D, (q31_t)0xC03A1368, + (q31_t)0x9104A0ED, (q31_t)0xC0915147, (q31_t)0x90D2ACD3, + (q31_t)0xC0E8B648, (q31_t)0x90A0FD4E, (q31_t)0xC1404233, + (q31_t)0x906F927B, (q31_t)0xC197F4D3, (q31_t)0x903E6C7A, + (q31_t)0xC1EFCDF2, (q31_t)0x900D8B69, (q31_t)0xC247CD5A, + (q31_t)0x8FDCEF66, (q31_t)0xC29FF2D4, (q31_t)0x8FAC988E, + (q31_t)0xC2F83E2A, (q31_t)0x8F7C8701, (q31_t)0xC350AF25, + (q31_t)0x8F4CBADB, (q31_t)0xC3A9458F, (q31_t)0x8F1D343A, + (q31_t)0xC4020132, (q31_t)0x8EEDF33B, (q31_t)0xC45AE1D7, + (q31_t)0x8EBEF7FB, (q31_t)0xC4B3E746, (q31_t)0x8E904298, + (q31_t)0xC50D1148, (q31_t)0x8E61D32D, (q31_t)0xC5665FA8, + (q31_t)0x8E33A9D9, (q31_t)0xC5BFD22E, (q31_t)0x8E05C6B7, + (q31_t)0xC61968A2, (q31_t)0x8DD829E4, (q31_t)0xC67322CD, + (q31_t)0x8DAAD37B, (q31_t)0xC6CD0079, (q31_t)0x8D7DC399, + (q31_t)0xC727016C, (q31_t)0x8D50FA59, (q31_t)0xC7812571, + (q31_t)0x8D2477D8, (q31_t)0xC7DB6C50, (q31_t)0x8CF83C30, + (q31_t)0xC835D5D0, (q31_t)0x8CCC477D, (q31_t)0xC89061BA, + (q31_t)0x8CA099D9, (q31_t)0xC8EB0FD6, (q31_t)0x8C753361, + (q31_t)0xC945DFEC, (q31_t)0x8C4A142F, (q31_t)0xC9A0D1C4, + (q31_t)0x8C1F3C5C, (q31_t)0xC9FBE527, (q31_t)0x8BF4AC05, + (q31_t)0xCA5719DB, (q31_t)0x8BCA6342, (q31_t)0xCAB26FA9, + (q31_t)0x8BA0622F, (q31_t)0xCB0DE658, (q31_t)0x8B76A8E4, + (q31_t)0xCB697DB0, (q31_t)0x8B4D377C, (q31_t)0xCBC53578, + (q31_t)0x8B240E10, (q31_t)0xCC210D78, (q31_t)0x8AFB2CBA, + (q31_t)0xCC7D0577, (q31_t)0x8AD29393, (q31_t)0xCCD91D3D, + (q31_t)0x8AAA42B4, (q31_t)0xCD355490, (q31_t)0x8A823A35, + (q31_t)0xCD91AB38, (q31_t)0x8A5A7A30, (q31_t)0xCDEE20FC, + (q31_t)0x8A3302BD, (q31_t)0xCE4AB5A2, (q31_t)0x8A0BD3F5, + (q31_t)0xCEA768F2, (q31_t)0x89E4EDEE, (q31_t)0xCF043AB2, + (q31_t)0x89BE50C3, (q31_t)0xCF612AAA, (q31_t)0x8997FC89, + (q31_t)0xCFBE389F, (q31_t)0x8971F15A, (q31_t)0xD01B6459, + (q31_t)0x894C2F4C, (q31_t)0xD078AD9D, (q31_t)0x8926B677, + (q31_t)0xD0D61433, (q31_t)0x890186F1, (q31_t)0xD13397E1, + (q31_t)0x88DCA0D3, (q31_t)0xD191386D, (q31_t)0x88B80431, + (q31_t)0xD1EEF59E, (q31_t)0x8893B124, (q31_t)0xD24CCF38, + (q31_t)0x886FA7C2, (q31_t)0xD2AAC504, (q31_t)0x884BE820, + (q31_t)0xD308D6C6, (q31_t)0x88287255, (q31_t)0xD3670445, + (q31_t)0x88054677, (q31_t)0xD3C54D46, (q31_t)0x87E2649B, + (q31_t)0xD423B190, (q31_t)0x87BFCCD7, (q31_t)0xD48230E8, + (q31_t)0x879D7F40, (q31_t)0xD4E0CB14, (q31_t)0x877B7BEC, + (q31_t)0xD53F7FDA, (q31_t)0x8759C2EF, (q31_t)0xD59E4EFE, + (q31_t)0x8738545E, (q31_t)0xD5FD3847, (q31_t)0x8717304E, + (q31_t)0xD65C3B7B, (q31_t)0x86F656D3, (q31_t)0xD6BB585D, + (q31_t)0x86D5C802, (q31_t)0xD71A8EB5, (q31_t)0x86B583EE, + (q31_t)0xD779DE46, (q31_t)0x86958AAB, (q31_t)0xD7D946D7, + (q31_t)0x8675DC4E, (q31_t)0xD838C82D, (q31_t)0x865678EA, + (q31_t)0xD898620C, (q31_t)0x86376092, (q31_t)0xD8F81439, + (q31_t)0x86189359, (q31_t)0xD957DE7A, (q31_t)0x85FA1152, + (q31_t)0xD9B7C093, (q31_t)0x85DBDA91, (q31_t)0xDA17BA4A, + (q31_t)0x85BDEF27, (q31_t)0xDA77CB62, (q31_t)0x85A04F28, + (q31_t)0xDAD7F3A2, (q31_t)0x8582FAA4, (q31_t)0xDB3832CD, + (q31_t)0x8565F1B0, (q31_t)0xDB9888A8, (q31_t)0x8549345C, + (q31_t)0xDBF8F4F8, (q31_t)0x852CC2BA, (q31_t)0xDC597781, + (q31_t)0x85109CDC, (q31_t)0xDCBA1008, (q31_t)0x84F4C2D3, + (q31_t)0xDD1ABE51, (q31_t)0x84D934B0, (q31_t)0xDD7B8220, + (q31_t)0x84BDF285, (q31_t)0xDDDC5B3A, (q31_t)0x84A2FC62, + (q31_t)0xDE3D4963, (q31_t)0x84885257, (q31_t)0xDE9E4C60, + (q31_t)0x846DF476, (q31_t)0xDEFF63F4, (q31_t)0x8453E2CE, + (q31_t)0xDF608FE3, (q31_t)0x843A1D70, (q31_t)0xDFC1CFF2, + (q31_t)0x8420A46B, (q31_t)0xE02323E5, (q31_t)0x840777CF, + (q31_t)0xE0848B7F, (q31_t)0x83EE97AC, (q31_t)0xE0E60684, + (q31_t)0x83D60411, (q31_t)0xE14794B9, (q31_t)0x83BDBD0D, + (q31_t)0xE1A935E1, (q31_t)0x83A5C2B0, (q31_t)0xE20AE9C1, + (q31_t)0x838E1507, (q31_t)0xE26CB01A, (q31_t)0x8376B422, + (q31_t)0xE2CE88B2, (q31_t)0x835FA00E, (q31_t)0xE330734C, + (q31_t)0x8348D8DB, (q31_t)0xE3926FAC, (q31_t)0x83325E97, + (q31_t)0xE3F47D95, (q31_t)0x831C314E, (q31_t)0xE4569CCB, + (q31_t)0x8306510F, (q31_t)0xE4B8CD10, (q31_t)0x82F0BDE8, + (q31_t)0xE51B0E2A, (q31_t)0x82DB77E5, (q31_t)0xE57D5FDA, + (q31_t)0x82C67F13, (q31_t)0xE5DFC1E4, (q31_t)0x82B1D381, + (q31_t)0xE642340D, (q31_t)0x829D753A, (q31_t)0xE6A4B616, + (q31_t)0x8289644A, (q31_t)0xE70747C3, (q31_t)0x8275A0C0, + (q31_t)0xE769E8D8, (q31_t)0x82622AA5, (q31_t)0xE7CC9917, + (q31_t)0x824F0208, (q31_t)0xE82F5844, (q31_t)0x823C26F2, + (q31_t)0xE8922621, (q31_t)0x82299971, (q31_t)0xE8F50273, + (q31_t)0x8217598F, (q31_t)0xE957ECFB, (q31_t)0x82056758, + (q31_t)0xE9BAE57C, (q31_t)0x81F3C2D7, (q31_t)0xEA1DEBBB, + (q31_t)0x81E26C16, (q31_t)0xEA80FF79, (q31_t)0x81D16320, + (q31_t)0xEAE4207A, (q31_t)0x81C0A801, (q31_t)0xEB474E80, + (q31_t)0x81B03AC1, (q31_t)0xEBAA894E, (q31_t)0x81A01B6C, + (q31_t)0xEC0DD0A8, (q31_t)0x81904A0C, (q31_t)0xEC71244F, + (q31_t)0x8180C6A9, (q31_t)0xECD48406, (q31_t)0x8171914E, + (q31_t)0xED37EF91, (q31_t)0x8162AA03, (q31_t)0xED9B66B2, + (q31_t)0x815410D3, (q31_t)0xEDFEE92B, (q31_t)0x8145C5C6, + (q31_t)0xEE6276BF, (q31_t)0x8137C8E6, (q31_t)0xEEC60F31, + (q31_t)0x812A1A39, (q31_t)0xEF29B243, (q31_t)0x811CB9CA, + (q31_t)0xEF8D5FB8, (q31_t)0x810FA7A0, (q31_t)0xEFF11752, + (q31_t)0x8102E3C3, (q31_t)0xF054D8D4, (q31_t)0x80F66E3C, + (q31_t)0xF0B8A401, (q31_t)0x80EA4712, (q31_t)0xF11C789A, + (q31_t)0x80DE6E4C, (q31_t)0xF1805662, (q31_t)0x80D2E3F1, + (q31_t)0xF1E43D1C, (q31_t)0x80C7A80A, (q31_t)0xF2482C89, + (q31_t)0x80BCBA9C, (q31_t)0xF2AC246D, (q31_t)0x80B21BAF, + (q31_t)0xF310248A, (q31_t)0x80A7CB49, (q31_t)0xF3742CA1, + (q31_t)0x809DC970, (q31_t)0xF3D83C76, (q31_t)0x8094162B, + (q31_t)0xF43C53CA, (q31_t)0x808AB180, (q31_t)0xF4A07260, + (q31_t)0x80819B74, (q31_t)0xF50497FA, (q31_t)0x8078D40D, + (q31_t)0xF568C45A, (q31_t)0x80705B50, (q31_t)0xF5CCF743, + (q31_t)0x80683143, (q31_t)0xF6313076, (q31_t)0x806055EA, + (q31_t)0xF6956FB6, (q31_t)0x8058C94C, (q31_t)0xF6F9B4C5, + (q31_t)0x80518B6B, (q31_t)0xF75DFF65, (q31_t)0x804A9C4D, + (q31_t)0xF7C24F58, (q31_t)0x8043FBF6, (q31_t)0xF826A461, + (q31_t)0x803DAA69, (q31_t)0xF88AFE41, (q31_t)0x8037A7AC, + (q31_t)0xF8EF5CBB, (q31_t)0x8031F3C1, (q31_t)0xF953BF90, + (q31_t)0x802C8EAD, (q31_t)0xF9B82683, (q31_t)0x80277872, + (q31_t)0xFA1C9156, (q31_t)0x8022B113, (q31_t)0xFA80FFCB, + (q31_t)0x801E3894, (q31_t)0xFAE571A4, (q31_t)0x801A0EF7, + (q31_t)0xFB49E6A2, (q31_t)0x80163440, (q31_t)0xFBAE5E89, + (q31_t)0x8012A86F, (q31_t)0xFC12D919, (q31_t)0x800F6B88, + (q31_t)0xFC775616, (q31_t)0x800C7D8C, (q31_t)0xFCDBD541, + (q31_t)0x8009DE7D, (q31_t)0xFD40565B, (q31_t)0x80078E5E, + (q31_t)0xFDA4D928, (q31_t)0x80058D2E, (q31_t)0xFE095D69, + (q31_t)0x8003DAF0, (q31_t)0xFE6DE2E0, (q31_t)0x800277A5, + (q31_t)0xFED2694F, (q31_t)0x8001634D, (q31_t)0xFF36F078, + (q31_t)0x80009DE9, (q31_t)0xFF9B781D, (q31_t)0x8000277A +}; +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_Q31_4096) +/** + @par + Example code for Q31 Twiddle factors Generation:: + @par + 
for (i = 0; i< 3N/4; i++)
+  {
+     twiddleCoefQ31[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefQ31[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 4096, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to Q31(Fixed point 1.31): + round(twiddleCoefQ31(i) * pow(2, 31)) + */ +const q31_t twiddleCoef_4096_q31[6144] = +{ + (q31_t)0x7FFFFFFF, (q31_t)0x00000000, (q31_t)0x7FFFF621, + (q31_t)0x003243F5, (q31_t)0x7FFFD885, (q31_t)0x006487E3, + (q31_t)0x7FFFA72C, (q31_t)0x0096CBC1, (q31_t)0x7FFF6216, + (q31_t)0x00C90F88, (q31_t)0x7FFF0942, (q31_t)0x00FB532F, + (q31_t)0x7FFE9CB2, (q31_t)0x012D96B0, (q31_t)0x7FFE1C64, + (q31_t)0x015FDA03, (q31_t)0x7FFD885A, (q31_t)0x01921D1F, + (q31_t)0x7FFCE093, (q31_t)0x01C45FFE, (q31_t)0x7FFC250F, + (q31_t)0x01F6A296, (q31_t)0x7FFB55CE, (q31_t)0x0228E4E1, + (q31_t)0x7FFA72D1, (q31_t)0x025B26D7, (q31_t)0x7FF97C17, + (q31_t)0x028D6870, (q31_t)0x7FF871A1, (q31_t)0x02BFA9A4, + (q31_t)0x7FF7536F, (q31_t)0x02F1EA6B, (q31_t)0x7FF62182, + (q31_t)0x03242ABF, (q31_t)0x7FF4DBD8, (q31_t)0x03566A96, + (q31_t)0x7FF38273, (q31_t)0x0388A9E9, (q31_t)0x7FF21553, + (q31_t)0x03BAE8B1, (q31_t)0x7FF09477, (q31_t)0x03ED26E6, + (q31_t)0x7FEEFFE1, (q31_t)0x041F647F, (q31_t)0x7FED5790, + (q31_t)0x0451A176, (q31_t)0x7FEB9B85, (q31_t)0x0483DDC3, + (q31_t)0x7FE9CBC0, (q31_t)0x04B6195D, (q31_t)0x7FE7E840, + (q31_t)0x04E8543D, (q31_t)0x7FE5F108, (q31_t)0x051A8E5C, + (q31_t)0x7FE3E616, (q31_t)0x054CC7B0, (q31_t)0x7FE1C76B, + (q31_t)0x057F0034, (q31_t)0x7FDF9508, (q31_t)0x05B137DF, + (q31_t)0x7FDD4EEC, (q31_t)0x05E36EA9, (q31_t)0x7FDAF518, + (q31_t)0x0615A48A, (q31_t)0x7FD8878D, (q31_t)0x0647D97C, + (q31_t)0x7FD6064B, (q31_t)0x067A0D75, (q31_t)0x7FD37152, + (q31_t)0x06AC406F, (q31_t)0x7FD0C8A3, (q31_t)0x06DE7261, + (q31_t)0x7FCE0C3E, (q31_t)0x0710A344, (q31_t)0x7FCB3C23, + (q31_t)0x0742D310, (q31_t)0x7FC85853, (q31_t)0x077501BE, + (q31_t)0x7FC560CF, (q31_t)0x07A72F45, (q31_t)0x7FC25596, + (q31_t)0x07D95B9E, (q31_t)0x7FBF36A9, (q31_t)0x080B86C1, + (q31_t)0x7FBC040A, (q31_t)0x083DB0A7, (q31_t)0x7FB8BDB7, + (q31_t)0x086FD947, (q31_t)0x7FB563B2, (q31_t)0x08A2009A, + (q31_t)0x7FB1F5FC, (q31_t)0x08D42698, (q31_t)0x7FAE7494, + (q31_t)0x09064B3A, (q31_t)0x7FAADF7C, (q31_t)0x09386E77, + (q31_t)0x7FA736B4, (q31_t)0x096A9049, (q31_t)0x7FA37A3C, + (q31_t)0x099CB0A7, (q31_t)0x7F9FAA15, (q31_t)0x09CECF89, + (q31_t)0x7F9BC63F, (q31_t)0x0A00ECE8, (q31_t)0x7F97CEBC, + (q31_t)0x0A3308BC, (q31_t)0x7F93C38C, (q31_t)0x0A6522FE, + (q31_t)0x7F8FA4AF, (q31_t)0x0A973BA5, (q31_t)0x7F8B7226, + (q31_t)0x0AC952AA, (q31_t)0x7F872BF3, (q31_t)0x0AFB6805, + (q31_t)0x7F82D214, (q31_t)0x0B2D7BAE, (q31_t)0x7F7E648B, + (q31_t)0x0B5F8D9F, (q31_t)0x7F79E35A, (q31_t)0x0B919DCE, + (q31_t)0x7F754E7F, (q31_t)0x0BC3AC35, (q31_t)0x7F70A5FD, + (q31_t)0x0BF5B8CB, (q31_t)0x7F6BE9D4, (q31_t)0x0C27C389, + (q31_t)0x7F671A04, (q31_t)0x0C59CC67, (q31_t)0x7F62368F, + (q31_t)0x0C8BD35E, (q31_t)0x7F5D3F75, (q31_t)0x0CBDD865, + (q31_t)0x7F5834B6, (q31_t)0x0CEFDB75, (q31_t)0x7F531654, + (q31_t)0x0D21DC87, (q31_t)0x7F4DE450, (q31_t)0x0D53DB92, + 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(q31_t)0x81F3C2D7, (q31_t)0xE9EC66E8, + (q31_t)0x81EB0DBD, (q31_t)0xEA1DEBBB, (q31_t)0x81E26C16, + (q31_t)0xEA4F73EE, (q31_t)0x81D9DDE1, (q31_t)0xEA80FF79, + (q31_t)0x81D16320, (q31_t)0xEAB28E55, (q31_t)0x81C8FBD5, + (q31_t)0xEAE4207A, (q31_t)0x81C0A801, (q31_t)0xEB15B5E0, + (q31_t)0x81B867A4, (q31_t)0xEB474E80, (q31_t)0x81B03AC1, + (q31_t)0xEB78EA52, (q31_t)0x81A82159, (q31_t)0xEBAA894E, + (q31_t)0x81A01B6C, (q31_t)0xEBDC2B6D, (q31_t)0x819828FD, + (q31_t)0xEC0DD0A8, (q31_t)0x81904A0C, (q31_t)0xEC3F78F5, + (q31_t)0x81887E9A, (q31_t)0xEC71244F, (q31_t)0x8180C6A9, + (q31_t)0xECA2D2AC, (q31_t)0x8179223A, (q31_t)0xECD48406, + (q31_t)0x8171914E, (q31_t)0xED063855, (q31_t)0x816A13E6, + (q31_t)0xED37EF91, (q31_t)0x8162AA03, (q31_t)0xED69A9B2, + (q31_t)0x815B53A8, (q31_t)0xED9B66B2, (q31_t)0x815410D3, + (q31_t)0xEDCD2687, (q31_t)0x814CE188, (q31_t)0xEDFEE92B, + (q31_t)0x8145C5C6, (q31_t)0xEE30AE95, (q31_t)0x813EBD90, + (q31_t)0xEE6276BF, (q31_t)0x8137C8E6, (q31_t)0xEE9441A0, + (q31_t)0x8130E7C8, (q31_t)0xEEC60F31, (q31_t)0x812A1A39, + (q31_t)0xEEF7DF6A, (q31_t)0x81236039, (q31_t)0xEF29B243, + (q31_t)0x811CB9CA, (q31_t)0xEF5B87B5, (q31_t)0x811626EC, + (q31_t)0xEF8D5FB8, (q31_t)0x810FA7A0, (q31_t)0xEFBF3A44, + (q31_t)0x81093BE8, (q31_t)0xEFF11752, (q31_t)0x8102E3C3, + (q31_t)0xF022F6DA, (q31_t)0x80FC9F35, (q31_t)0xF054D8D4, + (q31_t)0x80F66E3C, (q31_t)0xF086BD39, (q31_t)0x80F050DB, + (q31_t)0xF0B8A401, (q31_t)0x80EA4712, (q31_t)0xF0EA8D23, + (q31_t)0x80E450E2, (q31_t)0xF11C789A, (q31_t)0x80DE6E4C, + (q31_t)0xF14E665C, (q31_t)0x80D89F51, (q31_t)0xF1805662, + (q31_t)0x80D2E3F1, (q31_t)0xF1B248A5, (q31_t)0x80CD3C2F, + (q31_t)0xF1E43D1C, (q31_t)0x80C7A80A, (q31_t)0xF21633C0, + (q31_t)0x80C22783, (q31_t)0xF2482C89, (q31_t)0x80BCBA9C, + (q31_t)0xF27A2770, (q31_t)0x80B76155, (q31_t)0xF2AC246D, + (q31_t)0x80B21BAF, (q31_t)0xF2DE2378, (q31_t)0x80ACE9AB, + (q31_t)0xF310248A, (q31_t)0x80A7CB49, (q31_t)0xF342279A, + (q31_t)0x80A2C08B, (q31_t)0xF3742CA1, (q31_t)0x809DC970, + (q31_t)0xF3A63398, (q31_t)0x8098E5FB, (q31_t)0xF3D83C76, + (q31_t)0x8094162B, (q31_t)0xF40A4734, (q31_t)0x808F5A02, + (q31_t)0xF43C53CA, (q31_t)0x808AB180, (q31_t)0xF46E6231, + (q31_t)0x80861CA5, (q31_t)0xF4A07260, (q31_t)0x80819B74, + (q31_t)0xF4D28451, (q31_t)0x807D2DEB, (q31_t)0xF50497FA, + (q31_t)0x8078D40D, (q31_t)0xF536AD55, (q31_t)0x80748DD9, + (q31_t)0xF568C45A, (q31_t)0x80705B50, (q31_t)0xF59ADD01, + (q31_t)0x806C3C73, (q31_t)0xF5CCF743, (q31_t)0x80683143, + (q31_t)0xF5FF1317, (q31_t)0x806439C0, (q31_t)0xF6313076, + (q31_t)0x806055EA, (q31_t)0xF6634F58, (q31_t)0x805C85C3, + (q31_t)0xF6956FB6, (q31_t)0x8058C94C, (q31_t)0xF6C79188, + (q31_t)0x80552083, (q31_t)0xF6F9B4C5, (q31_t)0x80518B6B, + (q31_t)0xF72BD967, (q31_t)0x804E0A03, (q31_t)0xF75DFF65, + (q31_t)0x804A9C4D, (q31_t)0xF79026B8, (q31_t)0x80474248, + (q31_t)0xF7C24F58, (q31_t)0x8043FBF6, (q31_t)0xF7F4793E, + (q31_t)0x8040C956, (q31_t)0xF826A461, (q31_t)0x803DAA69, + (q31_t)0xF858D0BA, (q31_t)0x803A9F31, (q31_t)0xF88AFE41, + (q31_t)0x8037A7AC, (q31_t)0xF8BD2CEF, (q31_t)0x8034C3DC, + (q31_t)0xF8EF5CBB, (q31_t)0x8031F3C1, (q31_t)0xF9218D9E, + (q31_t)0x802F375C, (q31_t)0xF953BF90, (q31_t)0x802C8EAD, + (q31_t)0xF985F28A, (q31_t)0x8029F9B4, (q31_t)0xF9B82683, + (q31_t)0x80277872, (q31_t)0xF9EA5B75, (q31_t)0x80250AE7, + (q31_t)0xFA1C9156, (q31_t)0x8022B113, (q31_t)0xFA4EC820, + (q31_t)0x80206AF8, (q31_t)0xFA80FFCB, (q31_t)0x801E3894, + (q31_t)0xFAB3384F, (q31_t)0x801C19E9, (q31_t)0xFAE571A4, + (q31_t)0x801A0EF7, (q31_t)0xFB17ABC2, (q31_t)0x801817BF, + (q31_t)0xFB49E6A2, (q31_t)0x80163440, (q31_t)0xFB7C223C, + (q31_t)0x8014647A, (q31_t)0xFBAE5E89, (q31_t)0x8012A86F, + (q31_t)0xFBE09B80, (q31_t)0x8011001E, (q31_t)0xFC12D919, + (q31_t)0x800F6B88, (q31_t)0xFC45174E, (q31_t)0x800DEAAC, + (q31_t)0xFC775616, (q31_t)0x800C7D8C, (q31_t)0xFCA99569, + (q31_t)0x800B2427, (q31_t)0xFCDBD541, (q31_t)0x8009DE7D, + (q31_t)0xFD0E1594, (q31_t)0x8008AC90, (q31_t)0xFD40565B, + (q31_t)0x80078E5E, (q31_t)0xFD72978F, (q31_t)0x800683E8, + (q31_t)0xFDA4D928, (q31_t)0x80058D2E, (q31_t)0xFDD71B1E, + (q31_t)0x8004AA31, (q31_t)0xFE095D69, (q31_t)0x8003DAF0, + (q31_t)0xFE3BA001, (q31_t)0x80031F6C, (q31_t)0xFE6DE2E0, + (q31_t)0x800277A5, (q31_t)0xFEA025FC, (q31_t)0x8001E39B, + (q31_t)0xFED2694F, (q31_t)0x8001634D, (q31_t)0xFF04ACD0, + (q31_t)0x8000F6BD, (q31_t)0xFF36F078, (q31_t)0x80009DE9, + (q31_t)0xFF69343E, (q31_t)0x800058D3, (q31_t)0xFF9B781D, + (q31_t)0x8000277A, (q31_t)0xFFCDBC0A, (q31_t)0x800009DE +}; + +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + +/** + @brief q15 Twiddle factors Table +*/ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_Q15_16) + +/** + @par + Example code for q15 Twiddle factors Generation:: + @par + 
fori = 0; i< 3N/4; i++)
+  {
+     twiddleCoefq15[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefq15[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 16, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to q15(Fixed point 1.15): + round(twiddleCoefq15(i) * pow(2, 15)) + */ +const q15_t twiddleCoef_16_q15[24] = { + (q15_t)0x7FFF, (q15_t)0x0000, + (q15_t)0x7641, (q15_t)0x30FB, + (q15_t)0x5A82, (q15_t)0x5A82, + (q15_t)0x30FB, (q15_t)0x7641, + (q15_t)0x0000, (q15_t)0x7FFF, + (q15_t)0xCF04, (q15_t)0x7641, + (q15_t)0xA57D, (q15_t)0x5A82, + (q15_t)0x89BE, (q15_t)0x30FB, + (q15_t)0x8000, (q15_t)0x0000, + (q15_t)0x89BE, (q15_t)0xCF04, + (q15_t)0xA57D, (q15_t)0xA57D, + (q15_t)0xCF04, (q15_t)0x89BE +}; +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_Q15_32) +/** + @par + Example code for q15 Twiddle factors Generation:: + @par + 
for (i = 0; i< 3N/4; i++)
+  {
+     twiddleCoefq15[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefq15[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 32, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to q15(Fixed point 1.15): + round(twiddleCoefq15(i) * pow(2, 15)) + */ +const q15_t twiddleCoef_32_q15[48] = { + (q15_t)0x7FFF, (q15_t)0x0000, + (q15_t)0x7D8A, (q15_t)0x18F8, + (q15_t)0x7641, (q15_t)0x30FB, + (q15_t)0x6A6D, (q15_t)0x471C, + (q15_t)0x5A82, (q15_t)0x5A82, + (q15_t)0x471C, (q15_t)0x6A6D, + (q15_t)0x30FB, (q15_t)0x7641, + (q15_t)0x18F8, (q15_t)0x7D8A, + (q15_t)0x0000, (q15_t)0x7FFF, + (q15_t)0xE707, (q15_t)0x7D8A, + (q15_t)0xCF04, (q15_t)0x7641, + (q15_t)0xB8E3, (q15_t)0x6A6D, + (q15_t)0xA57D, (q15_t)0x5A82, + (q15_t)0x9592, (q15_t)0x471C, + (q15_t)0x89BE, (q15_t)0x30FB, + (q15_t)0x8275, (q15_t)0x18F8, + (q15_t)0x8000, (q15_t)0x0000, + (q15_t)0x8275, (q15_t)0xE707, + (q15_t)0x89BE, (q15_t)0xCF04, + (q15_t)0x9592, (q15_t)0xB8E3, + (q15_t)0xA57D, (q15_t)0xA57D, + (q15_t)0xB8E3, (q15_t)0x9592, + (q15_t)0xCF04, (q15_t)0x89BE, + (q15_t)0xE707, (q15_t)0x8275 +}; +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_Q15_64) +/** + @par + Example code for q15 Twiddle factors Generation:: + @par + 
for (i = 0; i< 3N/4; i++)
+  {
+     twiddleCoefq15[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefq15[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 64, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to q15(Fixed point 1.15): + round(twiddleCoefq15(i) * pow(2, 15)) + */ +const q15_t twiddleCoef_64_q15[96] = { + (q15_t)0x7FFF, (q15_t)0x0000, (q15_t)0x7F62, (q15_t)0x0C8B, + (q15_t)0x7D8A, (q15_t)0x18F8, (q15_t)0x7A7D, (q15_t)0x2528, + (q15_t)0x7641, (q15_t)0x30FB, (q15_t)0x70E2, (q15_t)0x3C56, + (q15_t)0x6A6D, (q15_t)0x471C, (q15_t)0x62F2, (q15_t)0x5133, + (q15_t)0x5A82, (q15_t)0x5A82, (q15_t)0x5133, (q15_t)0x62F2, + (q15_t)0x471C, (q15_t)0x6A6D, (q15_t)0x3C56, (q15_t)0x70E2, + (q15_t)0x30FB, (q15_t)0x7641, (q15_t)0x2528, (q15_t)0x7A7D, + (q15_t)0x18F8, (q15_t)0x7D8A, (q15_t)0x0C8B, (q15_t)0x7F62, + (q15_t)0x0000, (q15_t)0x7FFF, (q15_t)0xF374, (q15_t)0x7F62, + (q15_t)0xE707, (q15_t)0x7D8A, (q15_t)0xDAD7, (q15_t)0x7A7D, + (q15_t)0xCF04, (q15_t)0x7641, (q15_t)0xC3A9, (q15_t)0x70E2, + (q15_t)0xB8E3, (q15_t)0x6A6D, (q15_t)0xAECC, (q15_t)0x62F2, + (q15_t)0xA57D, (q15_t)0x5A82, (q15_t)0x9D0D, (q15_t)0x5133, + (q15_t)0x9592, (q15_t)0x471C, (q15_t)0x8F1D, (q15_t)0x3C56, + (q15_t)0x89BE, (q15_t)0x30FB, (q15_t)0x8582, (q15_t)0x2528, + (q15_t)0x8275, (q15_t)0x18F8, (q15_t)0x809D, (q15_t)0x0C8B, + (q15_t)0x8000, (q15_t)0x0000, (q15_t)0x809D, (q15_t)0xF374, + (q15_t)0x8275, (q15_t)0xE707, (q15_t)0x8582, (q15_t)0xDAD7, + (q15_t)0x89BE, (q15_t)0xCF04, (q15_t)0x8F1D, (q15_t)0xC3A9, + (q15_t)0x9592, (q15_t)0xB8E3, (q15_t)0x9D0D, (q15_t)0xAECC, + (q15_t)0xA57D, (q15_t)0xA57D, (q15_t)0xAECC, (q15_t)0x9D0D, + (q15_t)0xB8E3, (q15_t)0x9592, (q15_t)0xC3A9, (q15_t)0x8F1D, + (q15_t)0xCF04, (q15_t)0x89BE, (q15_t)0xDAD7, (q15_t)0x8582, + (q15_t)0xE707, (q15_t)0x8275, (q15_t)0xF374, (q15_t)0x809D +}; +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_Q15_128) +/** + @par + Example code for q15 Twiddle factors Generation:: + @par + 
for (i = 0; i< 3N/4; i++)
+  {
+     twiddleCoefq15[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefq15[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 128, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to q15(Fixed point 1.15): + round(twiddleCoefq15(i) * pow(2, 15)) + */ +const q15_t twiddleCoef_128_q15[192] = { + (q15_t)0x7FFF, (q15_t)0x0000, (q15_t)0x7FD8, (q15_t)0x0647, + (q15_t)0x7F62, (q15_t)0x0C8B, (q15_t)0x7E9D, (q15_t)0x12C8, + (q15_t)0x7D8A, (q15_t)0x18F8, (q15_t)0x7C29, (q15_t)0x1F19, + (q15_t)0x7A7D, (q15_t)0x2528, (q15_t)0x7884, (q15_t)0x2B1F, + (q15_t)0x7641, (q15_t)0x30FB, (q15_t)0x73B5, (q15_t)0x36BA, + (q15_t)0x70E2, (q15_t)0x3C56, (q15_t)0x6DCA, (q15_t)0x41CE, + (q15_t)0x6A6D, (q15_t)0x471C, (q15_t)0x66CF, (q15_t)0x4C3F, + (q15_t)0x62F2, (q15_t)0x5133, (q15_t)0x5ED7, (q15_t)0x55F5, + (q15_t)0x5A82, (q15_t)0x5A82, (q15_t)0x55F5, (q15_t)0x5ED7, + (q15_t)0x5133, (q15_t)0x62F2, (q15_t)0x4C3F, (q15_t)0x66CF, + (q15_t)0x471C, (q15_t)0x6A6D, (q15_t)0x41CE, (q15_t)0x6DCA, + (q15_t)0x3C56, (q15_t)0x70E2, (q15_t)0x36BA, (q15_t)0x73B5, + (q15_t)0x30FB, (q15_t)0x7641, (q15_t)0x2B1F, (q15_t)0x7884, + (q15_t)0x2528, (q15_t)0x7A7D, (q15_t)0x1F19, (q15_t)0x7C29, + (q15_t)0x18F8, (q15_t)0x7D8A, (q15_t)0x12C8, (q15_t)0x7E9D, + (q15_t)0x0C8B, (q15_t)0x7F62, (q15_t)0x0647, (q15_t)0x7FD8, + (q15_t)0x0000, (q15_t)0x7FFF, (q15_t)0xF9B8, (q15_t)0x7FD8, + (q15_t)0xF374, (q15_t)0x7F62, (q15_t)0xED37, (q15_t)0x7E9D, + (q15_t)0xE707, (q15_t)0x7D8A, (q15_t)0xE0E6, (q15_t)0x7C29, + (q15_t)0xDAD7, (q15_t)0x7A7D, (q15_t)0xD4E0, (q15_t)0x7884, + (q15_t)0xCF04, (q15_t)0x7641, (q15_t)0xC945, (q15_t)0x73B5, + (q15_t)0xC3A9, (q15_t)0x70E2, (q15_t)0xBE31, (q15_t)0x6DCA, + (q15_t)0xB8E3, (q15_t)0x6A6D, (q15_t)0xB3C0, (q15_t)0x66CF, + (q15_t)0xAECC, (q15_t)0x62F2, (q15_t)0xAA0A, (q15_t)0x5ED7, + (q15_t)0xA57D, (q15_t)0x5A82, (q15_t)0xA128, (q15_t)0x55F5, + (q15_t)0x9D0D, (q15_t)0x5133, (q15_t)0x9930, (q15_t)0x4C3F, + (q15_t)0x9592, (q15_t)0x471C, (q15_t)0x9235, (q15_t)0x41CE, + (q15_t)0x8F1D, (q15_t)0x3C56, (q15_t)0x8C4A, (q15_t)0x36BA, + (q15_t)0x89BE, (q15_t)0x30FB, (q15_t)0x877B, (q15_t)0x2B1F, + (q15_t)0x8582, (q15_t)0x2528, (q15_t)0x83D6, (q15_t)0x1F19, + (q15_t)0x8275, (q15_t)0x18F8, (q15_t)0x8162, (q15_t)0x12C8, + (q15_t)0x809D, (q15_t)0x0C8B, (q15_t)0x8027, (q15_t)0x0647, + (q15_t)0x8000, (q15_t)0x0000, (q15_t)0x8027, (q15_t)0xF9B8, + (q15_t)0x809D, (q15_t)0xF374, (q15_t)0x8162, (q15_t)0xED37, + (q15_t)0x8275, (q15_t)0xE707, (q15_t)0x83D6, (q15_t)0xE0E6, + (q15_t)0x8582, (q15_t)0xDAD7, (q15_t)0x877B, (q15_t)0xD4E0, + (q15_t)0x89BE, (q15_t)0xCF04, (q15_t)0x8C4A, (q15_t)0xC945, + (q15_t)0x8F1D, (q15_t)0xC3A9, (q15_t)0x9235, (q15_t)0xBE31, + (q15_t)0x9592, (q15_t)0xB8E3, (q15_t)0x9930, (q15_t)0xB3C0, + (q15_t)0x9D0D, (q15_t)0xAECC, (q15_t)0xA128, (q15_t)0xAA0A, + (q15_t)0xA57D, (q15_t)0xA57D, (q15_t)0xAA0A, (q15_t)0xA128, + (q15_t)0xAECC, (q15_t)0x9D0D, (q15_t)0xB3C0, (q15_t)0x9930, + (q15_t)0xB8E3, (q15_t)0x9592, (q15_t)0xBE31, (q15_t)0x9235, + (q15_t)0xC3A9, (q15_t)0x8F1D, (q15_t)0xC945, (q15_t)0x8C4A, + (q15_t)0xCF04, (q15_t)0x89BE, (q15_t)0xD4E0, (q15_t)0x877B, + (q15_t)0xDAD7, (q15_t)0x8582, (q15_t)0xE0E6, (q15_t)0x83D6, + (q15_t)0xE707, (q15_t)0x8275, (q15_t)0xED37, (q15_t)0x8162, + (q15_t)0xF374, (q15_t)0x809D, (q15_t)0xF9B8, (q15_t)0x8027 +}; +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_Q15_256) +/** + @par + Example code for q15 Twiddle factors Generation:: + @par + 
for (i = 0; i< 3N/4; i++)
+  {
+     twiddleCoefq15[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefq15[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 256, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to q15(Fixed point 1.15): + round(twiddleCoefq15(i) * pow(2, 15)) + */ +const q15_t twiddleCoef_256_q15[384] = { + (q15_t)0x7FFF, (q15_t)0x0000, (q15_t)0x7FF6, (q15_t)0x0324, + (q15_t)0x7FD8, (q15_t)0x0647, (q15_t)0x7FA7, (q15_t)0x096A, + (q15_t)0x7F62, (q15_t)0x0C8B, (q15_t)0x7F09, (q15_t)0x0FAB, + (q15_t)0x7E9D, (q15_t)0x12C8, (q15_t)0x7E1D, (q15_t)0x15E2, + (q15_t)0x7D8A, (q15_t)0x18F8, (q15_t)0x7CE3, (q15_t)0x1C0B, + (q15_t)0x7C29, (q15_t)0x1F19, (q15_t)0x7B5D, (q15_t)0x2223, + (q15_t)0x7A7D, (q15_t)0x2528, (q15_t)0x798A, (q15_t)0x2826, + (q15_t)0x7884, (q15_t)0x2B1F, (q15_t)0x776C, (q15_t)0x2E11, + (q15_t)0x7641, (q15_t)0x30FB, (q15_t)0x7504, (q15_t)0x33DE, + (q15_t)0x73B5, (q15_t)0x36BA, (q15_t)0x7255, (q15_t)0x398C, + (q15_t)0x70E2, (q15_t)0x3C56, (q15_t)0x6F5F, (q15_t)0x3F17, + (q15_t)0x6DCA, (q15_t)0x41CE, (q15_t)0x6C24, (q15_t)0x447A, + (q15_t)0x6A6D, (q15_t)0x471C, (q15_t)0x68A6, (q15_t)0x49B4, + (q15_t)0x66CF, (q15_t)0x4C3F, (q15_t)0x64E8, (q15_t)0x4EBF, + (q15_t)0x62F2, (q15_t)0x5133, (q15_t)0x60EC, (q15_t)0x539B, + (q15_t)0x5ED7, (q15_t)0x55F5, (q15_t)0x5CB4, (q15_t)0x5842, + (q15_t)0x5A82, (q15_t)0x5A82, (q15_t)0x5842, (q15_t)0x5CB4, + (q15_t)0x55F5, (q15_t)0x5ED7, (q15_t)0x539B, (q15_t)0x60EC, + (q15_t)0x5133, (q15_t)0x62F2, (q15_t)0x4EBF, (q15_t)0x64E8, + (q15_t)0x4C3F, (q15_t)0x66CF, (q15_t)0x49B4, (q15_t)0x68A6, + (q15_t)0x471C, (q15_t)0x6A6D, (q15_t)0x447A, (q15_t)0x6C24, + (q15_t)0x41CE, (q15_t)0x6DCA, (q15_t)0x3F17, (q15_t)0x6F5F, + (q15_t)0x3C56, (q15_t)0x70E2, (q15_t)0x398C, (q15_t)0x7255, + (q15_t)0x36BA, (q15_t)0x73B5, (q15_t)0x33DE, (q15_t)0x7504, + (q15_t)0x30FB, (q15_t)0x7641, (q15_t)0x2E11, (q15_t)0x776C, + (q15_t)0x2B1F, (q15_t)0x7884, (q15_t)0x2826, (q15_t)0x798A, + (q15_t)0x2528, (q15_t)0x7A7D, (q15_t)0x2223, (q15_t)0x7B5D, + (q15_t)0x1F19, (q15_t)0x7C29, (q15_t)0x1C0B, (q15_t)0x7CE3, + (q15_t)0x18F8, (q15_t)0x7D8A, (q15_t)0x15E2, (q15_t)0x7E1D, + (q15_t)0x12C8, (q15_t)0x7E9D, (q15_t)0x0FAB, (q15_t)0x7F09, + (q15_t)0x0C8B, (q15_t)0x7F62, (q15_t)0x096A, (q15_t)0x7FA7, + (q15_t)0x0647, (q15_t)0x7FD8, (q15_t)0x0324, (q15_t)0x7FF6, + (q15_t)0x0000, (q15_t)0x7FFF, (q15_t)0xFCDB, (q15_t)0x7FF6, + (q15_t)0xF9B8, (q15_t)0x7FD8, (q15_t)0xF695, (q15_t)0x7FA7, + (q15_t)0xF374, (q15_t)0x7F62, (q15_t)0xF054, (q15_t)0x7F09, + (q15_t)0xED37, (q15_t)0x7E9D, (q15_t)0xEA1D, (q15_t)0x7E1D, + (q15_t)0xE707, (q15_t)0x7D8A, (q15_t)0xE3F4, (q15_t)0x7CE3, + (q15_t)0xE0E6, (q15_t)0x7C29, (q15_t)0xDDDC, (q15_t)0x7B5D, + (q15_t)0xDAD7, (q15_t)0x7A7D, (q15_t)0xD7D9, (q15_t)0x798A, + (q15_t)0xD4E0, (q15_t)0x7884, (q15_t)0xD1EE, (q15_t)0x776C, + (q15_t)0xCF04, (q15_t)0x7641, (q15_t)0xCC21, (q15_t)0x7504, + (q15_t)0xC945, (q15_t)0x73B5, (q15_t)0xC673, (q15_t)0x7255, + (q15_t)0xC3A9, (q15_t)0x70E2, (q15_t)0xC0E8, (q15_t)0x6F5F, + (q15_t)0xBE31, (q15_t)0x6DCA, (q15_t)0xBB85, (q15_t)0x6C24, + (q15_t)0xB8E3, (q15_t)0x6A6D, (q15_t)0xB64B, (q15_t)0x68A6, + (q15_t)0xB3C0, (q15_t)0x66CF, (q15_t)0xB140, (q15_t)0x64E8, + (q15_t)0xAECC, (q15_t)0x62F2, (q15_t)0xAC64, (q15_t)0x60EC, + (q15_t)0xAA0A, (q15_t)0x5ED7, (q15_t)0xA7BD, (q15_t)0x5CB4, + (q15_t)0xA57D, (q15_t)0x5A82, (q15_t)0xA34B, (q15_t)0x5842, + (q15_t)0xA128, (q15_t)0x55F5, (q15_t)0x9F13, (q15_t)0x539B, + (q15_t)0x9D0D, (q15_t)0x5133, (q15_t)0x9B17, (q15_t)0x4EBF, + (q15_t)0x9930, (q15_t)0x4C3F, (q15_t)0x9759, (q15_t)0x49B4, + (q15_t)0x9592, (q15_t)0x471C, (q15_t)0x93DB, (q15_t)0x447A, + (q15_t)0x9235, (q15_t)0x41CE, (q15_t)0x90A0, (q15_t)0x3F17, + (q15_t)0x8F1D, (q15_t)0x3C56, (q15_t)0x8DAA, (q15_t)0x398C, + (q15_t)0x8C4A, (q15_t)0x36BA, (q15_t)0x8AFB, (q15_t)0x33DE, + (q15_t)0x89BE, (q15_t)0x30FB, (q15_t)0x8893, (q15_t)0x2E11, + (q15_t)0x877B, (q15_t)0x2B1F, (q15_t)0x8675, (q15_t)0x2826, + (q15_t)0x8582, (q15_t)0x2528, (q15_t)0x84A2, (q15_t)0x2223, + (q15_t)0x83D6, (q15_t)0x1F19, (q15_t)0x831C, (q15_t)0x1C0B, + (q15_t)0x8275, (q15_t)0x18F8, (q15_t)0x81E2, (q15_t)0x15E2, + (q15_t)0x8162, (q15_t)0x12C8, (q15_t)0x80F6, (q15_t)0x0FAB, + (q15_t)0x809D, (q15_t)0x0C8B, (q15_t)0x8058, (q15_t)0x096A, + (q15_t)0x8027, (q15_t)0x0647, (q15_t)0x8009, (q15_t)0x0324, + (q15_t)0x8000, (q15_t)0x0000, (q15_t)0x8009, (q15_t)0xFCDB, + (q15_t)0x8027, (q15_t)0xF9B8, (q15_t)0x8058, (q15_t)0xF695, + (q15_t)0x809D, (q15_t)0xF374, (q15_t)0x80F6, (q15_t)0xF054, + (q15_t)0x8162, (q15_t)0xED37, (q15_t)0x81E2, (q15_t)0xEA1D, + (q15_t)0x8275, (q15_t)0xE707, (q15_t)0x831C, (q15_t)0xE3F4, + (q15_t)0x83D6, (q15_t)0xE0E6, (q15_t)0x84A2, (q15_t)0xDDDC, + (q15_t)0x8582, (q15_t)0xDAD7, (q15_t)0x8675, (q15_t)0xD7D9, + (q15_t)0x877B, (q15_t)0xD4E0, (q15_t)0x8893, (q15_t)0xD1EE, + (q15_t)0x89BE, (q15_t)0xCF04, (q15_t)0x8AFB, (q15_t)0xCC21, + (q15_t)0x8C4A, (q15_t)0xC945, (q15_t)0x8DAA, (q15_t)0xC673, + (q15_t)0x8F1D, (q15_t)0xC3A9, (q15_t)0x90A0, (q15_t)0xC0E8, + (q15_t)0x9235, (q15_t)0xBE31, (q15_t)0x93DB, (q15_t)0xBB85, + (q15_t)0x9592, (q15_t)0xB8E3, (q15_t)0x9759, (q15_t)0xB64B, + (q15_t)0x9930, (q15_t)0xB3C0, (q15_t)0x9B17, (q15_t)0xB140, + (q15_t)0x9D0D, (q15_t)0xAECC, (q15_t)0x9F13, (q15_t)0xAC64, + (q15_t)0xA128, (q15_t)0xAA0A, (q15_t)0xA34B, (q15_t)0xA7BD, + (q15_t)0xA57D, (q15_t)0xA57D, (q15_t)0xA7BD, (q15_t)0xA34B, + (q15_t)0xAA0A, (q15_t)0xA128, (q15_t)0xAC64, (q15_t)0x9F13, + (q15_t)0xAECC, (q15_t)0x9D0D, (q15_t)0xB140, (q15_t)0x9B17, + (q15_t)0xB3C0, (q15_t)0x9930, (q15_t)0xB64B, (q15_t)0x9759, + (q15_t)0xB8E3, (q15_t)0x9592, (q15_t)0xBB85, (q15_t)0x93DB, + (q15_t)0xBE31, (q15_t)0x9235, (q15_t)0xC0E8, (q15_t)0x90A0, + (q15_t)0xC3A9, (q15_t)0x8F1D, (q15_t)0xC673, (q15_t)0x8DAA, + (q15_t)0xC945, (q15_t)0x8C4A, (q15_t)0xCC21, (q15_t)0x8AFB, + (q15_t)0xCF04, (q15_t)0x89BE, (q15_t)0xD1EE, (q15_t)0x8893, + (q15_t)0xD4E0, (q15_t)0x877B, (q15_t)0xD7D9, (q15_t)0x8675, + (q15_t)0xDAD7, (q15_t)0x8582, (q15_t)0xDDDC, (q15_t)0x84A2, + (q15_t)0xE0E6, (q15_t)0x83D6, (q15_t)0xE3F4, (q15_t)0x831C, + (q15_t)0xE707, (q15_t)0x8275, (q15_t)0xEA1D, (q15_t)0x81E2, + (q15_t)0xED37, (q15_t)0x8162, (q15_t)0xF054, (q15_t)0x80F6, + (q15_t)0xF374, (q15_t)0x809D, (q15_t)0xF695, (q15_t)0x8058, + (q15_t)0xF9B8, (q15_t)0x8027, (q15_t)0xFCDB, (q15_t)0x8009 +}; +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_Q15_512) +/** + @par + Example code for q15 Twiddle factors Generation:: + @par + 
for (i = 0; i< 3N/4; i++)
+  {
+     twiddleCoefq15[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefq15[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 512, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to q15(Fixed point 1.15): + round(twiddleCoefq15(i) * pow(2, 15)) + */ +const q15_t twiddleCoef_512_q15[768] = { + (q15_t)0x7FFF, (q15_t)0x0000, (q15_t)0x7FFD, (q15_t)0x0192, + (q15_t)0x7FF6, (q15_t)0x0324, (q15_t)0x7FE9, (q15_t)0x04B6, + (q15_t)0x7FD8, (q15_t)0x0647, (q15_t)0x7FC2, (q15_t)0x07D9, + (q15_t)0x7FA7, (q15_t)0x096A, (q15_t)0x7F87, (q15_t)0x0AFB, + (q15_t)0x7F62, (q15_t)0x0C8B, (q15_t)0x7F38, (q15_t)0x0E1B, + (q15_t)0x7F09, (q15_t)0x0FAB, (q15_t)0x7ED5, (q15_t)0x1139, + (q15_t)0x7E9D, (q15_t)0x12C8, (q15_t)0x7E5F, (q15_t)0x1455, + (q15_t)0x7E1D, (q15_t)0x15E2, (q15_t)0x7DD6, (q15_t)0x176D, + (q15_t)0x7D8A, (q15_t)0x18F8, (q15_t)0x7D39, (q15_t)0x1A82, + (q15_t)0x7CE3, (q15_t)0x1C0B, (q15_t)0x7C89, (q15_t)0x1D93, + (q15_t)0x7C29, (q15_t)0x1F19, (q15_t)0x7BC5, (q15_t)0x209F, + (q15_t)0x7B5D, (q15_t)0x2223, (q15_t)0x7AEF, (q15_t)0x23A6, + (q15_t)0x7A7D, (q15_t)0x2528, (q15_t)0x7A05, (q15_t)0x26A8, + (q15_t)0x798A, (q15_t)0x2826, (q15_t)0x7909, (q15_t)0x29A3, + (q15_t)0x7884, (q15_t)0x2B1F, (q15_t)0x77FA, (q15_t)0x2C98, + (q15_t)0x776C, (q15_t)0x2E11, (q15_t)0x76D9, (q15_t)0x2F87, + (q15_t)0x7641, (q15_t)0x30FB, (q15_t)0x75A5, (q15_t)0x326E, + (q15_t)0x7504, (q15_t)0x33DE, (q15_t)0x745F, (q15_t)0x354D, + (q15_t)0x73B5, (q15_t)0x36BA, (q15_t)0x7307, (q15_t)0x3824, + (q15_t)0x7255, (q15_t)0x398C, (q15_t)0x719E, (q15_t)0x3AF2, + (q15_t)0x70E2, (q15_t)0x3C56, (q15_t)0x7023, (q15_t)0x3DB8, + (q15_t)0x6F5F, (q15_t)0x3F17, (q15_t)0x6E96, (q15_t)0x4073, + (q15_t)0x6DCA, (q15_t)0x41CE, (q15_t)0x6CF9, (q15_t)0x4325, + (q15_t)0x6C24, (q15_t)0x447A, (q15_t)0x6B4A, (q15_t)0x45CD, + (q15_t)0x6A6D, (q15_t)0x471C, (q15_t)0x698C, (q15_t)0x4869, + (q15_t)0x68A6, (q15_t)0x49B4, (q15_t)0x67BD, (q15_t)0x4AFB, + (q15_t)0x66CF, (q15_t)0x4C3F, (q15_t)0x65DD, (q15_t)0x4D81, + (q15_t)0x64E8, (q15_t)0x4EBF, (q15_t)0x63EF, (q15_t)0x4FFB, + (q15_t)0x62F2, (q15_t)0x5133, (q15_t)0x61F1, (q15_t)0x5269, + (q15_t)0x60EC, (q15_t)0x539B, (q15_t)0x5FE3, (q15_t)0x54CA, + (q15_t)0x5ED7, (q15_t)0x55F5, (q15_t)0x5DC7, (q15_t)0x571D, + (q15_t)0x5CB4, (q15_t)0x5842, (q15_t)0x5B9D, (q15_t)0x5964, + (q15_t)0x5A82, (q15_t)0x5A82, (q15_t)0x5964, (q15_t)0x5B9D, + (q15_t)0x5842, (q15_t)0x5CB4, (q15_t)0x571D, (q15_t)0x5DC7, + (q15_t)0x55F5, (q15_t)0x5ED7, (q15_t)0x54CA, (q15_t)0x5FE3, + (q15_t)0x539B, (q15_t)0x60EC, (q15_t)0x5269, (q15_t)0x61F1, + (q15_t)0x5133, (q15_t)0x62F2, (q15_t)0x4FFB, (q15_t)0x63EF, + (q15_t)0x4EBF, (q15_t)0x64E8, (q15_t)0x4D81, (q15_t)0x65DD, + (q15_t)0x4C3F, (q15_t)0x66CF, (q15_t)0x4AFB, (q15_t)0x67BD, + (q15_t)0x49B4, (q15_t)0x68A6, (q15_t)0x4869, (q15_t)0x698C, + (q15_t)0x471C, (q15_t)0x6A6D, (q15_t)0x45CD, (q15_t)0x6B4A, + (q15_t)0x447A, (q15_t)0x6C24, (q15_t)0x4325, (q15_t)0x6CF9, + (q15_t)0x41CE, (q15_t)0x6DCA, (q15_t)0x4073, (q15_t)0x6E96, + (q15_t)0x3F17, (q15_t)0x6F5F, (q15_t)0x3DB8, (q15_t)0x7023, + (q15_t)0x3C56, (q15_t)0x70E2, (q15_t)0x3AF2, (q15_t)0x719E, + (q15_t)0x398C, (q15_t)0x7255, (q15_t)0x3824, (q15_t)0x7307, + (q15_t)0x36BA, (q15_t)0x73B5, (q15_t)0x354D, (q15_t)0x745F, + (q15_t)0x33DE, (q15_t)0x7504, (q15_t)0x326E, (q15_t)0x75A5, + (q15_t)0x30FB, (q15_t)0x7641, (q15_t)0x2F87, (q15_t)0x76D9, + (q15_t)0x2E11, (q15_t)0x776C, (q15_t)0x2C98, (q15_t)0x77FA, + (q15_t)0x2B1F, (q15_t)0x7884, (q15_t)0x29A3, (q15_t)0x7909, + (q15_t)0x2826, (q15_t)0x798A, (q15_t)0x26A8, (q15_t)0x7A05, + (q15_t)0x2528, (q15_t)0x7A7D, (q15_t)0x23A6, (q15_t)0x7AEF, + (q15_t)0x2223, (q15_t)0x7B5D, (q15_t)0x209F, (q15_t)0x7BC5, + (q15_t)0x1F19, (q15_t)0x7C29, (q15_t)0x1D93, (q15_t)0x7C89, + (q15_t)0x1C0B, (q15_t)0x7CE3, (q15_t)0x1A82, (q15_t)0x7D39, + (q15_t)0x18F8, (q15_t)0x7D8A, (q15_t)0x176D, (q15_t)0x7DD6, + (q15_t)0x15E2, (q15_t)0x7E1D, (q15_t)0x1455, (q15_t)0x7E5F, + (q15_t)0x12C8, (q15_t)0x7E9D, (q15_t)0x1139, (q15_t)0x7ED5, + (q15_t)0x0FAB, (q15_t)0x7F09, (q15_t)0x0E1B, (q15_t)0x7F38, + (q15_t)0x0C8B, (q15_t)0x7F62, (q15_t)0x0AFB, (q15_t)0x7F87, + (q15_t)0x096A, (q15_t)0x7FA7, (q15_t)0x07D9, (q15_t)0x7FC2, + (q15_t)0x0647, (q15_t)0x7FD8, (q15_t)0x04B6, (q15_t)0x7FE9, + (q15_t)0x0324, (q15_t)0x7FF6, (q15_t)0x0192, (q15_t)0x7FFD, + (q15_t)0x0000, (q15_t)0x7FFF, (q15_t)0xFE6D, (q15_t)0x7FFD, + (q15_t)0xFCDB, (q15_t)0x7FF6, (q15_t)0xFB49, (q15_t)0x7FE9, + (q15_t)0xF9B8, (q15_t)0x7FD8, (q15_t)0xF826, (q15_t)0x7FC2, + (q15_t)0xF695, (q15_t)0x7FA7, (q15_t)0xF504, (q15_t)0x7F87, + (q15_t)0xF374, (q15_t)0x7F62, (q15_t)0xF1E4, (q15_t)0x7F38, + (q15_t)0xF054, (q15_t)0x7F09, (q15_t)0xEEC6, (q15_t)0x7ED5, + (q15_t)0xED37, (q15_t)0x7E9D, (q15_t)0xEBAA, (q15_t)0x7E5F, + (q15_t)0xEA1D, (q15_t)0x7E1D, (q15_t)0xE892, (q15_t)0x7DD6, + (q15_t)0xE707, (q15_t)0x7D8A, (q15_t)0xE57D, (q15_t)0x7D39, + (q15_t)0xE3F4, (q15_t)0x7CE3, (q15_t)0xE26C, (q15_t)0x7C89, + (q15_t)0xE0E6, (q15_t)0x7C29, (q15_t)0xDF60, (q15_t)0x7BC5, + (q15_t)0xDDDC, (q15_t)0x7B5D, (q15_t)0xDC59, (q15_t)0x7AEF, + (q15_t)0xDAD7, (q15_t)0x7A7D, (q15_t)0xD957, (q15_t)0x7A05, + (q15_t)0xD7D9, (q15_t)0x798A, (q15_t)0xD65C, (q15_t)0x7909, + (q15_t)0xD4E0, (q15_t)0x7884, (q15_t)0xD367, (q15_t)0x77FA, + (q15_t)0xD1EE, (q15_t)0x776C, (q15_t)0xD078, (q15_t)0x76D9, + (q15_t)0xCF04, (q15_t)0x7641, (q15_t)0xCD91, (q15_t)0x75A5, + (q15_t)0xCC21, (q15_t)0x7504, (q15_t)0xCAB2, (q15_t)0x745F, + (q15_t)0xC945, (q15_t)0x73B5, (q15_t)0xC7DB, (q15_t)0x7307, + (q15_t)0xC673, (q15_t)0x7255, (q15_t)0xC50D, (q15_t)0x719E, + (q15_t)0xC3A9, (q15_t)0x70E2, (q15_t)0xC247, (q15_t)0x7023, + (q15_t)0xC0E8, (q15_t)0x6F5F, (q15_t)0xBF8C, (q15_t)0x6E96, + (q15_t)0xBE31, (q15_t)0x6DCA, (q15_t)0xBCDA, (q15_t)0x6CF9, + (q15_t)0xBB85, (q15_t)0x6C24, (q15_t)0xBA32, (q15_t)0x6B4A, + (q15_t)0xB8E3, (q15_t)0x6A6D, (q15_t)0xB796, (q15_t)0x698C, + (q15_t)0xB64B, (q15_t)0x68A6, (q15_t)0xB504, (q15_t)0x67BD, + (q15_t)0xB3C0, (q15_t)0x66CF, (q15_t)0xB27E, (q15_t)0x65DD, + (q15_t)0xB140, (q15_t)0x64E8, (q15_t)0xB004, (q15_t)0x63EF, + (q15_t)0xAECC, (q15_t)0x62F2, (q15_t)0xAD96, (q15_t)0x61F1, + (q15_t)0xAC64, (q15_t)0x60EC, (q15_t)0xAB35, (q15_t)0x5FE3, + (q15_t)0xAA0A, (q15_t)0x5ED7, (q15_t)0xA8E2, (q15_t)0x5DC7, + (q15_t)0xA7BD, (q15_t)0x5CB4, (q15_t)0xA69B, (q15_t)0x5B9D, + (q15_t)0xA57D, (q15_t)0x5A82, (q15_t)0xA462, (q15_t)0x5964, + (q15_t)0xA34B, (q15_t)0x5842, (q15_t)0xA238, (q15_t)0x571D, + (q15_t)0xA128, (q15_t)0x55F5, (q15_t)0xA01C, (q15_t)0x54CA, + (q15_t)0x9F13, (q15_t)0x539B, (q15_t)0x9E0E, (q15_t)0x5269, + (q15_t)0x9D0D, (q15_t)0x5133, (q15_t)0x9C10, (q15_t)0x4FFB, + (q15_t)0x9B17, (q15_t)0x4EBF, (q15_t)0x9A22, (q15_t)0x4D81, + (q15_t)0x9930, (q15_t)0x4C3F, (q15_t)0x9842, (q15_t)0x4AFB, + (q15_t)0x9759, (q15_t)0x49B4, (q15_t)0x9673, (q15_t)0x4869, + (q15_t)0x9592, (q15_t)0x471C, (q15_t)0x94B5, (q15_t)0x45CD, + (q15_t)0x93DB, (q15_t)0x447A, (q15_t)0x9306, (q15_t)0x4325, + (q15_t)0x9235, (q15_t)0x41CE, (q15_t)0x9169, (q15_t)0x4073, + (q15_t)0x90A0, (q15_t)0x3F17, (q15_t)0x8FDC, (q15_t)0x3DB8, + (q15_t)0x8F1D, (q15_t)0x3C56, (q15_t)0x8E61, (q15_t)0x3AF2, + (q15_t)0x8DAA, (q15_t)0x398C, (q15_t)0x8CF8, (q15_t)0x3824, + (q15_t)0x8C4A, (q15_t)0x36BA, (q15_t)0x8BA0, (q15_t)0x354D, + (q15_t)0x8AFB, (q15_t)0x33DE, (q15_t)0x8A5A, (q15_t)0x326E, + (q15_t)0x89BE, (q15_t)0x30FB, (q15_t)0x8926, (q15_t)0x2F87, + (q15_t)0x8893, (q15_t)0x2E11, (q15_t)0x8805, (q15_t)0x2C98, + (q15_t)0x877B, (q15_t)0x2B1F, (q15_t)0x86F6, (q15_t)0x29A3, + (q15_t)0x8675, (q15_t)0x2826, (q15_t)0x85FA, (q15_t)0x26A8, + (q15_t)0x8582, (q15_t)0x2528, (q15_t)0x8510, (q15_t)0x23A6, + (q15_t)0x84A2, (q15_t)0x2223, (q15_t)0x843A, (q15_t)0x209F, + (q15_t)0x83D6, (q15_t)0x1F19, (q15_t)0x8376, (q15_t)0x1D93, + (q15_t)0x831C, (q15_t)0x1C0B, (q15_t)0x82C6, (q15_t)0x1A82, + (q15_t)0x8275, (q15_t)0x18F8, (q15_t)0x8229, (q15_t)0x176D, + (q15_t)0x81E2, (q15_t)0x15E2, (q15_t)0x81A0, (q15_t)0x1455, + (q15_t)0x8162, (q15_t)0x12C8, (q15_t)0x812A, (q15_t)0x1139, + (q15_t)0x80F6, (q15_t)0x0FAB, (q15_t)0x80C7, (q15_t)0x0E1B, + (q15_t)0x809D, (q15_t)0x0C8B, (q15_t)0x8078, (q15_t)0x0AFB, + (q15_t)0x8058, (q15_t)0x096A, (q15_t)0x803D, (q15_t)0x07D9, + (q15_t)0x8027, (q15_t)0x0647, (q15_t)0x8016, (q15_t)0x04B6, + (q15_t)0x8009, (q15_t)0x0324, (q15_t)0x8002, (q15_t)0x0192, + (q15_t)0x8000, (q15_t)0x0000, (q15_t)0x8002, (q15_t)0xFE6D, + (q15_t)0x8009, (q15_t)0xFCDB, (q15_t)0x8016, (q15_t)0xFB49, + (q15_t)0x8027, (q15_t)0xF9B8, (q15_t)0x803D, (q15_t)0xF826, + (q15_t)0x8058, (q15_t)0xF695, (q15_t)0x8078, (q15_t)0xF504, + (q15_t)0x809D, (q15_t)0xF374, (q15_t)0x80C7, (q15_t)0xF1E4, + (q15_t)0x80F6, (q15_t)0xF054, (q15_t)0x812A, (q15_t)0xEEC6, + (q15_t)0x8162, (q15_t)0xED37, (q15_t)0x81A0, (q15_t)0xEBAA, + (q15_t)0x81E2, (q15_t)0xEA1D, (q15_t)0x8229, (q15_t)0xE892, + (q15_t)0x8275, (q15_t)0xE707, (q15_t)0x82C6, (q15_t)0xE57D, + (q15_t)0x831C, (q15_t)0xE3F4, (q15_t)0x8376, (q15_t)0xE26C, + (q15_t)0x83D6, (q15_t)0xE0E6, (q15_t)0x843A, (q15_t)0xDF60, + (q15_t)0x84A2, (q15_t)0xDDDC, (q15_t)0x8510, (q15_t)0xDC59, + (q15_t)0x8582, (q15_t)0xDAD7, (q15_t)0x85FA, (q15_t)0xD957, + (q15_t)0x8675, (q15_t)0xD7D9, (q15_t)0x86F6, (q15_t)0xD65C, + (q15_t)0x877B, (q15_t)0xD4E0, (q15_t)0x8805, (q15_t)0xD367, + (q15_t)0x8893, (q15_t)0xD1EE, (q15_t)0x8926, (q15_t)0xD078, + (q15_t)0x89BE, (q15_t)0xCF04, (q15_t)0x8A5A, (q15_t)0xCD91, + (q15_t)0x8AFB, (q15_t)0xCC21, (q15_t)0x8BA0, (q15_t)0xCAB2, + (q15_t)0x8C4A, (q15_t)0xC945, (q15_t)0x8CF8, (q15_t)0xC7DB, + (q15_t)0x8DAA, (q15_t)0xC673, (q15_t)0x8E61, (q15_t)0xC50D, + (q15_t)0x8F1D, (q15_t)0xC3A9, (q15_t)0x8FDC, (q15_t)0xC247, + (q15_t)0x90A0, (q15_t)0xC0E8, (q15_t)0x9169, (q15_t)0xBF8C, + (q15_t)0x9235, (q15_t)0xBE31, (q15_t)0x9306, (q15_t)0xBCDA, + (q15_t)0x93DB, (q15_t)0xBB85, (q15_t)0x94B5, (q15_t)0xBA32, + (q15_t)0x9592, (q15_t)0xB8E3, (q15_t)0x9673, (q15_t)0xB796, + (q15_t)0x9759, (q15_t)0xB64B, (q15_t)0x9842, (q15_t)0xB504, + (q15_t)0x9930, (q15_t)0xB3C0, (q15_t)0x9A22, (q15_t)0xB27E, + (q15_t)0x9B17, (q15_t)0xB140, (q15_t)0x9C10, (q15_t)0xB004, + (q15_t)0x9D0D, (q15_t)0xAECC, (q15_t)0x9E0E, (q15_t)0xAD96, + (q15_t)0x9F13, (q15_t)0xAC64, (q15_t)0xA01C, (q15_t)0xAB35, + (q15_t)0xA128, (q15_t)0xAA0A, (q15_t)0xA238, (q15_t)0xA8E2, + (q15_t)0xA34B, (q15_t)0xA7BD, (q15_t)0xA462, (q15_t)0xA69B, + (q15_t)0xA57D, (q15_t)0xA57D, (q15_t)0xA69B, (q15_t)0xA462, + (q15_t)0xA7BD, (q15_t)0xA34B, (q15_t)0xA8E2, (q15_t)0xA238, + (q15_t)0xAA0A, (q15_t)0xA128, (q15_t)0xAB35, (q15_t)0xA01C, + (q15_t)0xAC64, (q15_t)0x9F13, (q15_t)0xAD96, (q15_t)0x9E0E, + (q15_t)0xAECC, (q15_t)0x9D0D, (q15_t)0xB004, (q15_t)0x9C10, + (q15_t)0xB140, (q15_t)0x9B17, (q15_t)0xB27E, (q15_t)0x9A22, + (q15_t)0xB3C0, (q15_t)0x9930, (q15_t)0xB504, (q15_t)0x9842, + (q15_t)0xB64B, (q15_t)0x9759, (q15_t)0xB796, (q15_t)0x9673, + (q15_t)0xB8E3, (q15_t)0x9592, (q15_t)0xBA32, (q15_t)0x94B5, + (q15_t)0xBB85, (q15_t)0x93DB, (q15_t)0xBCDA, (q15_t)0x9306, + (q15_t)0xBE31, (q15_t)0x9235, (q15_t)0xBF8C, (q15_t)0x9169, + (q15_t)0xC0E8, (q15_t)0x90A0, (q15_t)0xC247, (q15_t)0x8FDC, + (q15_t)0xC3A9, (q15_t)0x8F1D, (q15_t)0xC50D, (q15_t)0x8E61, + (q15_t)0xC673, (q15_t)0x8DAA, (q15_t)0xC7DB, (q15_t)0x8CF8, + (q15_t)0xC945, (q15_t)0x8C4A, (q15_t)0xCAB2, (q15_t)0x8BA0, + (q15_t)0xCC21, (q15_t)0x8AFB, (q15_t)0xCD91, (q15_t)0x8A5A, + (q15_t)0xCF04, (q15_t)0x89BE, (q15_t)0xD078, (q15_t)0x8926, + (q15_t)0xD1EE, (q15_t)0x8893, (q15_t)0xD367, (q15_t)0x8805, + (q15_t)0xD4E0, (q15_t)0x877B, (q15_t)0xD65C, (q15_t)0x86F6, + (q15_t)0xD7D9, (q15_t)0x8675, (q15_t)0xD957, (q15_t)0x85FA, + (q15_t)0xDAD7, (q15_t)0x8582, (q15_t)0xDC59, (q15_t)0x8510, + (q15_t)0xDDDC, (q15_t)0x84A2, (q15_t)0xDF60, (q15_t)0x843A, + (q15_t)0xE0E6, (q15_t)0x83D6, (q15_t)0xE26C, (q15_t)0x8376, + (q15_t)0xE3F4, (q15_t)0x831C, (q15_t)0xE57D, (q15_t)0x82C6, + (q15_t)0xE707, (q15_t)0x8275, (q15_t)0xE892, (q15_t)0x8229, + (q15_t)0xEA1D, (q15_t)0x81E2, (q15_t)0xEBAA, (q15_t)0x81A0, + (q15_t)0xED37, (q15_t)0x8162, (q15_t)0xEEC6, (q15_t)0x812A, + (q15_t)0xF054, (q15_t)0x80F6, (q15_t)0xF1E4, (q15_t)0x80C7, + (q15_t)0xF374, (q15_t)0x809D, (q15_t)0xF504, (q15_t)0x8078, + (q15_t)0xF695, (q15_t)0x8058, (q15_t)0xF826, (q15_t)0x803D, + (q15_t)0xF9B8, (q15_t)0x8027, (q15_t)0xFB49, (q15_t)0x8016, + (q15_t)0xFCDB, (q15_t)0x8009, (q15_t)0xFE6D, (q15_t)0x8002 +}; +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_Q15_1024) +/** + @par + Example code for q15 Twiddle factors Generation:: + @par + 
for (i = 0; i< 3N/4; i++)
+  {
+     twiddleCoefq15[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefq15[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 1024, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to q15(Fixed point 1.15): + round(twiddleCoefq15(i) * pow(2, 15)) + + */ +const q15_t twiddleCoef_1024_q15[1536] = { + (q15_t)0x7FFF, (q15_t)0x0000, (q15_t)0x7FFF, (q15_t)0x00C9, + (q15_t)0x7FFD, (q15_t)0x0192, (q15_t)0x7FFA, (q15_t)0x025B, + (q15_t)0x7FF6, (q15_t)0x0324, (q15_t)0x7FF0, (q15_t)0x03ED, + (q15_t)0x7FE9, (q15_t)0x04B6, (q15_t)0x7FE1, (q15_t)0x057F, + (q15_t)0x7FD8, (q15_t)0x0647, (q15_t)0x7FCE, (q15_t)0x0710, + (q15_t)0x7FC2, (q15_t)0x07D9, (q15_t)0x7FB5, (q15_t)0x08A2, + (q15_t)0x7FA7, (q15_t)0x096A, (q15_t)0x7F97, (q15_t)0x0A33, + (q15_t)0x7F87, (q15_t)0x0AFB, (q15_t)0x7F75, (q15_t)0x0BC3, + (q15_t)0x7F62, (q15_t)0x0C8B, (q15_t)0x7F4D, (q15_t)0x0D53, + (q15_t)0x7F38, (q15_t)0x0E1B, (q15_t)0x7F21, (q15_t)0x0EE3, + (q15_t)0x7F09, (q15_t)0x0FAB, (q15_t)0x7EF0, (q15_t)0x1072, + (q15_t)0x7ED5, (q15_t)0x1139, (q15_t)0x7EBA, (q15_t)0x1201, + (q15_t)0x7E9D, (q15_t)0x12C8, (q15_t)0x7E7F, (q15_t)0x138E, + (q15_t)0x7E5F, (q15_t)0x1455, (q15_t)0x7E3F, (q15_t)0x151B, + (q15_t)0x7E1D, (q15_t)0x15E2, (q15_t)0x7DFA, (q15_t)0x16A8, + (q15_t)0x7DD6, (q15_t)0x176D, (q15_t)0x7DB0, (q15_t)0x1833, + (q15_t)0x7D8A, (q15_t)0x18F8, (q15_t)0x7D62, (q15_t)0x19BD, + (q15_t)0x7D39, (q15_t)0x1A82, (q15_t)0x7D0F, (q15_t)0x1B47, + (q15_t)0x7CE3, (q15_t)0x1C0B, (q15_t)0x7CB7, (q15_t)0x1CCF, + (q15_t)0x7C89, (q15_t)0x1D93, (q15_t)0x7C5A, (q15_t)0x1E56, + (q15_t)0x7C29, (q15_t)0x1F19, (q15_t)0x7BF8, (q15_t)0x1FDC, + (q15_t)0x7BC5, (q15_t)0x209F, (q15_t)0x7B92, (q15_t)0x2161, + (q15_t)0x7B5D, (q15_t)0x2223, (q15_t)0x7B26, (q15_t)0x22E5, + (q15_t)0x7AEF, (q15_t)0x23A6, (q15_t)0x7AB6, (q15_t)0x2467, + (q15_t)0x7A7D, (q15_t)0x2528, (q15_t)0x7A42, (q15_t)0x25E8, + (q15_t)0x7A05, (q15_t)0x26A8, (q15_t)0x79C8, (q15_t)0x2767, + (q15_t)0x798A, (q15_t)0x2826, (q15_t)0x794A, (q15_t)0x28E5, + (q15_t)0x7909, (q15_t)0x29A3, (q15_t)0x78C7, (q15_t)0x2A61, + (q15_t)0x7884, (q15_t)0x2B1F, (q15_t)0x7840, (q15_t)0x2BDC, + (q15_t)0x77FA, (q15_t)0x2C98, (q15_t)0x77B4, (q15_t)0x2D55, + (q15_t)0x776C, (q15_t)0x2E11, (q15_t)0x7723, (q15_t)0x2ECC, + (q15_t)0x76D9, (q15_t)0x2F87, (q15_t)0x768E, (q15_t)0x3041, + (q15_t)0x7641, (q15_t)0x30FB, (q15_t)0x75F4, (q15_t)0x31B5, + (q15_t)0x75A5, (q15_t)0x326E, (q15_t)0x7555, (q15_t)0x3326, + (q15_t)0x7504, (q15_t)0x33DE, (q15_t)0x74B2, (q15_t)0x3496, + (q15_t)0x745F, (q15_t)0x354D, (q15_t)0x740B, (q15_t)0x3604, + (q15_t)0x73B5, (q15_t)0x36BA, (q15_t)0x735F, (q15_t)0x376F, + (q15_t)0x7307, (q15_t)0x3824, (q15_t)0x72AF, (q15_t)0x38D8, + (q15_t)0x7255, (q15_t)0x398C, (q15_t)0x71FA, (q15_t)0x3A40, + (q15_t)0x719E, (q15_t)0x3AF2, (q15_t)0x7141, (q15_t)0x3BA5, + (q15_t)0x70E2, (q15_t)0x3C56, (q15_t)0x7083, (q15_t)0x3D07, + (q15_t)0x7023, (q15_t)0x3DB8, (q15_t)0x6FC1, (q15_t)0x3E68, + (q15_t)0x6F5F, (q15_t)0x3F17, (q15_t)0x6EFB, (q15_t)0x3FC5, + (q15_t)0x6E96, (q15_t)0x4073, (q15_t)0x6E30, (q15_t)0x4121, + (q15_t)0x6DCA, (q15_t)0x41CE, (q15_t)0x6D62, (q15_t)0x427A, + (q15_t)0x6CF9, (q15_t)0x4325, (q15_t)0x6C8F, (q15_t)0x43D0, + (q15_t)0x6C24, (q15_t)0x447A, (q15_t)0x6BB8, (q15_t)0x4524, + (q15_t)0x6B4A, (q15_t)0x45CD, (q15_t)0x6ADC, (q15_t)0x4675, + (q15_t)0x6A6D, (q15_t)0x471C, (q15_t)0x69FD, (q15_t)0x47C3, + (q15_t)0x698C, (q15_t)0x4869, (q15_t)0x6919, (q15_t)0x490F, + (q15_t)0x68A6, (q15_t)0x49B4, (q15_t)0x6832, (q15_t)0x4A58, + (q15_t)0x67BD, (q15_t)0x4AFB, (q15_t)0x6746, (q15_t)0x4B9E, + (q15_t)0x66CF, (q15_t)0x4C3F, (q15_t)0x6657, (q15_t)0x4CE1, + (q15_t)0x65DD, (q15_t)0x4D81, (q15_t)0x6563, (q15_t)0x4E21, + (q15_t)0x64E8, (q15_t)0x4EBF, (q15_t)0x646C, (q15_t)0x4F5E, + (q15_t)0x63EF, (q15_t)0x4FFB, (q15_t)0x6371, (q15_t)0x5097, + (q15_t)0x62F2, (q15_t)0x5133, (q15_t)0x6271, (q15_t)0x51CE, + (q15_t)0x61F1, (q15_t)0x5269, (q15_t)0x616F, (q15_t)0x5302, + (q15_t)0x60EC, (q15_t)0x539B, (q15_t)0x6068, (q15_t)0x5433, + (q15_t)0x5FE3, (q15_t)0x54CA, (q15_t)0x5F5E, (q15_t)0x5560, + (q15_t)0x5ED7, (q15_t)0x55F5, (q15_t)0x5E50, (q15_t)0x568A, + (q15_t)0x5DC7, (q15_t)0x571D, (q15_t)0x5D3E, (q15_t)0x57B0, + (q15_t)0x5CB4, (q15_t)0x5842, (q15_t)0x5C29, (q15_t)0x58D4, + (q15_t)0x5B9D, (q15_t)0x5964, (q15_t)0x5B10, (q15_t)0x59F3, + (q15_t)0x5A82, (q15_t)0x5A82, (q15_t)0x59F3, (q15_t)0x5B10, + (q15_t)0x5964, (q15_t)0x5B9D, (q15_t)0x58D4, (q15_t)0x5C29, + (q15_t)0x5842, (q15_t)0x5CB4, (q15_t)0x57B0, (q15_t)0x5D3E, + (q15_t)0x571D, (q15_t)0x5DC7, (q15_t)0x568A, (q15_t)0x5E50, + (q15_t)0x55F5, (q15_t)0x5ED7, (q15_t)0x5560, (q15_t)0x5F5E, + (q15_t)0x54CA, (q15_t)0x5FE3, (q15_t)0x5433, (q15_t)0x6068, + (q15_t)0x539B, (q15_t)0x60EC, (q15_t)0x5302, (q15_t)0x616F, + (q15_t)0x5269, (q15_t)0x61F1, (q15_t)0x51CE, (q15_t)0x6271, + (q15_t)0x5133, (q15_t)0x62F2, (q15_t)0x5097, (q15_t)0x6371, + (q15_t)0x4FFB, (q15_t)0x63EF, (q15_t)0x4F5E, (q15_t)0x646C, + (q15_t)0x4EBF, (q15_t)0x64E8, (q15_t)0x4E21, (q15_t)0x6563, + (q15_t)0x4D81, (q15_t)0x65DD, (q15_t)0x4CE1, (q15_t)0x6657, + (q15_t)0x4C3F, (q15_t)0x66CF, (q15_t)0x4B9E, (q15_t)0x6746, + (q15_t)0x4AFB, (q15_t)0x67BD, (q15_t)0x4A58, (q15_t)0x6832, + (q15_t)0x49B4, (q15_t)0x68A6, (q15_t)0x490F, (q15_t)0x6919, + (q15_t)0x4869, (q15_t)0x698C, (q15_t)0x47C3, (q15_t)0x69FD, + (q15_t)0x471C, (q15_t)0x6A6D, (q15_t)0x4675, (q15_t)0x6ADC, + (q15_t)0x45CD, (q15_t)0x6B4A, (q15_t)0x4524, (q15_t)0x6BB8, + (q15_t)0x447A, (q15_t)0x6C24, (q15_t)0x43D0, (q15_t)0x6C8F, + (q15_t)0x4325, (q15_t)0x6CF9, (q15_t)0x427A, (q15_t)0x6D62, + (q15_t)0x41CE, (q15_t)0x6DCA, (q15_t)0x4121, (q15_t)0x6E30, + (q15_t)0x4073, (q15_t)0x6E96, (q15_t)0x3FC5, (q15_t)0x6EFB, + (q15_t)0x3F17, (q15_t)0x6F5F, (q15_t)0x3E68, (q15_t)0x6FC1, + (q15_t)0x3DB8, (q15_t)0x7023, (q15_t)0x3D07, (q15_t)0x7083, + (q15_t)0x3C56, (q15_t)0x70E2, (q15_t)0x3BA5, (q15_t)0x7141, + (q15_t)0x3AF2, (q15_t)0x719E, (q15_t)0x3A40, (q15_t)0x71FA, + (q15_t)0x398C, (q15_t)0x7255, (q15_t)0x38D8, (q15_t)0x72AF, + (q15_t)0x3824, (q15_t)0x7307, (q15_t)0x376F, (q15_t)0x735F, + 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(q15_t)0xA128, (q15_t)0xAA0A, (q15_t)0xA1AF, (q15_t)0xA975, + (q15_t)0xA238, (q15_t)0xA8E2, (q15_t)0xA2C1, (q15_t)0xA84F, + (q15_t)0xA34B, (q15_t)0xA7BD, (q15_t)0xA3D6, (q15_t)0xA72B, + (q15_t)0xA462, (q15_t)0xA69B, (q15_t)0xA4EF, (q15_t)0xA60C, + (q15_t)0xA57D, (q15_t)0xA57D, (q15_t)0xA60C, (q15_t)0xA4EF, + (q15_t)0xA69B, (q15_t)0xA462, (q15_t)0xA72B, (q15_t)0xA3D6, + (q15_t)0xA7BD, (q15_t)0xA34B, (q15_t)0xA84F, (q15_t)0xA2C1, + (q15_t)0xA8E2, (q15_t)0xA238, (q15_t)0xA975, (q15_t)0xA1AF, + (q15_t)0xAA0A, (q15_t)0xA128, (q15_t)0xAA9F, (q15_t)0xA0A1, + (q15_t)0xAB35, (q15_t)0xA01C, (q15_t)0xABCC, (q15_t)0x9F97, + (q15_t)0xAC64, (q15_t)0x9F13, (q15_t)0xACFD, (q15_t)0x9E90, + (q15_t)0xAD96, (q15_t)0x9E0E, (q15_t)0xAE31, (q15_t)0x9D8E, + (q15_t)0xAECC, (q15_t)0x9D0D, (q15_t)0xAF68, (q15_t)0x9C8E, + (q15_t)0xB004, (q15_t)0x9C10, (q15_t)0xB0A1, (q15_t)0x9B93, + (q15_t)0xB140, (q15_t)0x9B17, (q15_t)0xB1DE, (q15_t)0x9A9C, + (q15_t)0xB27E, (q15_t)0x9A22, (q15_t)0xB31E, (q15_t)0x99A8, + (q15_t)0xB3C0, (q15_t)0x9930, (q15_t)0xB461, (q15_t)0x98B9, + (q15_t)0xB504, (q15_t)0x9842, (q15_t)0xB5A7, (q15_t)0x97CD, + (q15_t)0xB64B, (q15_t)0x9759, (q15_t)0xB6F0, (q15_t)0x96E6, + (q15_t)0xB796, (q15_t)0x9673, (q15_t)0xB83C, (q15_t)0x9602, + (q15_t)0xB8E3, (q15_t)0x9592, (q15_t)0xB98A, (q15_t)0x9523, + (q15_t)0xBA32, (q15_t)0x94B5, (q15_t)0xBADB, (q15_t)0x9447, + (q15_t)0xBB85, (q15_t)0x93DB, (q15_t)0xBC2F, (q15_t)0x9370, + (q15_t)0xBCDA, (q15_t)0x9306, (q15_t)0xBD85, (q15_t)0x929D, + (q15_t)0xBE31, (q15_t)0x9235, (q15_t)0xBEDE, (q15_t)0x91CF, + (q15_t)0xBF8C, (q15_t)0x9169, (q15_t)0xC03A, (q15_t)0x9104, + (q15_t)0xC0E8, (q15_t)0x90A0, (q15_t)0xC197, (q15_t)0x903E, + (q15_t)0xC247, (q15_t)0x8FDC, (q15_t)0xC2F8, (q15_t)0x8F7C, + (q15_t)0xC3A9, (q15_t)0x8F1D, (q15_t)0xC45A, (q15_t)0x8EBE, + (q15_t)0xC50D, (q15_t)0x8E61, (q15_t)0xC5BF, (q15_t)0x8E05, + (q15_t)0xC673, (q15_t)0x8DAA, (q15_t)0xC727, (q15_t)0x8D50, + (q15_t)0xC7DB, (q15_t)0x8CF8, (q15_t)0xC890, (q15_t)0x8CA0, + (q15_t)0xC945, (q15_t)0x8C4A, (q15_t)0xC9FB, (q15_t)0x8BF4, + (q15_t)0xCAB2, (q15_t)0x8BA0, (q15_t)0xCB69, (q15_t)0x8B4D, + (q15_t)0xCC21, (q15_t)0x8AFB, (q15_t)0xCCD9, (q15_t)0x8AAA, + (q15_t)0xCD91, (q15_t)0x8A5A, (q15_t)0xCE4A, (q15_t)0x8A0B, + (q15_t)0xCF04, (q15_t)0x89BE, (q15_t)0xCFBE, (q15_t)0x8971, + (q15_t)0xD078, (q15_t)0x8926, (q15_t)0xD133, (q15_t)0x88DC, + (q15_t)0xD1EE, (q15_t)0x8893, (q15_t)0xD2AA, (q15_t)0x884B, + (q15_t)0xD367, (q15_t)0x8805, (q15_t)0xD423, (q15_t)0x87BF, + (q15_t)0xD4E0, (q15_t)0x877B, (q15_t)0xD59E, (q15_t)0x8738, + (q15_t)0xD65C, (q15_t)0x86F6, (q15_t)0xD71A, (q15_t)0x86B5, + (q15_t)0xD7D9, (q15_t)0x8675, (q15_t)0xD898, (q15_t)0x8637, + (q15_t)0xD957, (q15_t)0x85FA, (q15_t)0xDA17, (q15_t)0x85BD, + (q15_t)0xDAD7, (q15_t)0x8582, (q15_t)0xDB98, (q15_t)0x8549, + (q15_t)0xDC59, (q15_t)0x8510, (q15_t)0xDD1A, (q15_t)0x84D9, + (q15_t)0xDDDC, (q15_t)0x84A2, (q15_t)0xDE9E, (q15_t)0x846D, + (q15_t)0xDF60, (q15_t)0x843A, (q15_t)0xE023, (q15_t)0x8407, + (q15_t)0xE0E6, (q15_t)0x83D6, (q15_t)0xE1A9, (q15_t)0x83A5, + (q15_t)0xE26C, (q15_t)0x8376, (q15_t)0xE330, (q15_t)0x8348, + (q15_t)0xE3F4, (q15_t)0x831C, (q15_t)0xE4B8, (q15_t)0x82F0, + (q15_t)0xE57D, (q15_t)0x82C6, (q15_t)0xE642, (q15_t)0x829D, + (q15_t)0xE707, (q15_t)0x8275, (q15_t)0xE7CC, (q15_t)0x824F, + (q15_t)0xE892, (q15_t)0x8229, (q15_t)0xE957, (q15_t)0x8205, + (q15_t)0xEA1D, (q15_t)0x81E2, (q15_t)0xEAE4, (q15_t)0x81C0, + (q15_t)0xEBAA, (q15_t)0x81A0, (q15_t)0xEC71, (q15_t)0x8180, + (q15_t)0xED37, (q15_t)0x8162, (q15_t)0xEDFE, (q15_t)0x8145, + (q15_t)0xEEC6, (q15_t)0x812A, (q15_t)0xEF8D, (q15_t)0x810F, + (q15_t)0xF054, (q15_t)0x80F6, (q15_t)0xF11C, (q15_t)0x80DE, + (q15_t)0xF1E4, (q15_t)0x80C7, (q15_t)0xF2AC, (q15_t)0x80B2, + (q15_t)0xF374, (q15_t)0x809D, (q15_t)0xF43C, (q15_t)0x808A, + (q15_t)0xF504, (q15_t)0x8078, (q15_t)0xF5CC, (q15_t)0x8068, + (q15_t)0xF695, (q15_t)0x8058, (q15_t)0xF75D, (q15_t)0x804A, + (q15_t)0xF826, (q15_t)0x803D, (q15_t)0xF8EF, (q15_t)0x8031, + (q15_t)0xF9B8, (q15_t)0x8027, (q15_t)0xFA80, (q15_t)0x801E, + (q15_t)0xFB49, (q15_t)0x8016, (q15_t)0xFC12, (q15_t)0x800F, + (q15_t)0xFCDB, (q15_t)0x8009, (q15_t)0xFDA4, (q15_t)0x8005, + (q15_t)0xFE6D, (q15_t)0x8002, (q15_t)0xFF36, (q15_t)0x8000 +}; +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_Q15_2048) +/** + @par + Example code for q15 Twiddle factors Generation:: + @par + 
for (i = 0; i< 3N/4; i++)
+  {
+     twiddleCoefq15[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefq15[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 2048, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to q15(Fixed point 1.15): + round(twiddleCoefq15(i) * pow(2, 15)) + */ +const q15_t twiddleCoef_2048_q15[3072] = { + (q15_t)0x7FFF, (q15_t)0x0000, (q15_t)0x7FFF, (q15_t)0x0064, + (q15_t)0x7FFF, (q15_t)0x00C9, (q15_t)0x7FFE, (q15_t)0x012D, + (q15_t)0x7FFD, (q15_t)0x0192, (q15_t)0x7FFC, (q15_t)0x01F6, + (q15_t)0x7FFA, (q15_t)0x025B, (q15_t)0x7FF8, (q15_t)0x02BF, + (q15_t)0x7FF6, (q15_t)0x0324, (q15_t)0x7FF3, (q15_t)0x0388, + (q15_t)0x7FF0, (q15_t)0x03ED, (q15_t)0x7FED, (q15_t)0x0451, + (q15_t)0x7FE9, (q15_t)0x04B6, (q15_t)0x7FE5, (q15_t)0x051A, + (q15_t)0x7FE1, (q15_t)0x057F, (q15_t)0x7FDD, (q15_t)0x05E3, + (q15_t)0x7FD8, (q15_t)0x0647, (q15_t)0x7FD3, (q15_t)0x06AC, + (q15_t)0x7FCE, (q15_t)0x0710, (q15_t)0x7FC8, (q15_t)0x0775, + (q15_t)0x7FC2, (q15_t)0x07D9, (q15_t)0x7FBC, (q15_t)0x083D, + (q15_t)0x7FB5, (q15_t)0x08A2, (q15_t)0x7FAE, (q15_t)0x0906, + (q15_t)0x7FA7, (q15_t)0x096A, (q15_t)0x7F9F, (q15_t)0x09CE, + (q15_t)0x7F97, (q15_t)0x0A33, (q15_t)0x7F8F, (q15_t)0x0A97, + (q15_t)0x7F87, (q15_t)0x0AFB, (q15_t)0x7F7E, (q15_t)0x0B5F, + (q15_t)0x7F75, (q15_t)0x0BC3, (q15_t)0x7F6B, (q15_t)0x0C27, + (q15_t)0x7F62, (q15_t)0x0C8B, (q15_t)0x7F58, (q15_t)0x0CEF, + (q15_t)0x7F4D, (q15_t)0x0D53, (q15_t)0x7F43, (q15_t)0x0DB7, + (q15_t)0x7F38, (q15_t)0x0E1B, (q15_t)0x7F2D, (q15_t)0x0E7F, + (q15_t)0x7F21, (q15_t)0x0EE3, (q15_t)0x7F15, (q15_t)0x0F47, + (q15_t)0x7F09, (q15_t)0x0FAB, (q15_t)0x7EFD, (q15_t)0x100E, + (q15_t)0x7EF0, (q15_t)0x1072, (q15_t)0x7EE3, (q15_t)0x10D6, + (q15_t)0x7ED5, (q15_t)0x1139, (q15_t)0x7EC8, (q15_t)0x119D, + (q15_t)0x7EBA, (q15_t)0x1201, (q15_t)0x7EAB, (q15_t)0x1264, + (q15_t)0x7E9D, (q15_t)0x12C8, (q15_t)0x7E8E, (q15_t)0x132B, + (q15_t)0x7E7F, (q15_t)0x138E, (q15_t)0x7E6F, (q15_t)0x13F2, + (q15_t)0x7E5F, (q15_t)0x1455, (q15_t)0x7E4F, (q15_t)0x14B8, + (q15_t)0x7E3F, (q15_t)0x151B, (q15_t)0x7E2E, (q15_t)0x157F, + (q15_t)0x7E1D, (q15_t)0x15E2, (q15_t)0x7E0C, (q15_t)0x1645, + (q15_t)0x7DFA, (q15_t)0x16A8, (q15_t)0x7DE8, (q15_t)0x170A, + (q15_t)0x7DD6, (q15_t)0x176D, (q15_t)0x7DC3, (q15_t)0x17D0, + (q15_t)0x7DB0, (q15_t)0x1833, (q15_t)0x7D9D, (q15_t)0x1896, + (q15_t)0x7D8A, (q15_t)0x18F8, (q15_t)0x7D76, (q15_t)0x195B, + (q15_t)0x7D62, (q15_t)0x19BD, (q15_t)0x7D4E, (q15_t)0x1A20, + (q15_t)0x7D39, (q15_t)0x1A82, (q15_t)0x7D24, (q15_t)0x1AE4, + (q15_t)0x7D0F, (q15_t)0x1B47, (q15_t)0x7CF9, (q15_t)0x1BA9, + (q15_t)0x7CE3, (q15_t)0x1C0B, (q15_t)0x7CCD, (q15_t)0x1C6D, + (q15_t)0x7CB7, (q15_t)0x1CCF, (q15_t)0x7CA0, (q15_t)0x1D31, + (q15_t)0x7C89, (q15_t)0x1D93, (q15_t)0x7C71, (q15_t)0x1DF5, + (q15_t)0x7C5A, (q15_t)0x1E56, (q15_t)0x7C42, (q15_t)0x1EB8, + (q15_t)0x7C29, (q15_t)0x1F19, (q15_t)0x7C11, (q15_t)0x1F7B, + (q15_t)0x7BF8, (q15_t)0x1FDC, (q15_t)0x7BDF, (q15_t)0x203E, + (q15_t)0x7BC5, (q15_t)0x209F, (q15_t)0x7BAC, (q15_t)0x2100, + (q15_t)0x7B92, (q15_t)0x2161, (q15_t)0x7B77, (q15_t)0x21C2, + (q15_t)0x7B5D, (q15_t)0x2223, (q15_t)0x7B42, (q15_t)0x2284, + (q15_t)0x7B26, (q15_t)0x22E5, (q15_t)0x7B0B, (q15_t)0x2345, + (q15_t)0x7AEF, (q15_t)0x23A6, (q15_t)0x7AD3, (q15_t)0x2407, + (q15_t)0x7AB6, (q15_t)0x2467, (q15_t)0x7A9A, (q15_t)0x24C7, + (q15_t)0x7A7D, (q15_t)0x2528, (q15_t)0x7A5F, (q15_t)0x2588, + (q15_t)0x7A42, (q15_t)0x25E8, (q15_t)0x7A24, (q15_t)0x2648, + (q15_t)0x7A05, (q15_t)0x26A8, (q15_t)0x79E7, (q15_t)0x2707, + (q15_t)0x79C8, (q15_t)0x2767, (q15_t)0x79A9, (q15_t)0x27C7, + (q15_t)0x798A, (q15_t)0x2826, (q15_t)0x796A, (q15_t)0x2886, + (q15_t)0x794A, (q15_t)0x28E5, (q15_t)0x792A, (q15_t)0x2944, + (q15_t)0x7909, (q15_t)0x29A3, (q15_t)0x78E8, (q15_t)0x2A02, + (q15_t)0x78C7, (q15_t)0x2A61, (q15_t)0x78A6, (q15_t)0x2AC0, + (q15_t)0x7884, (q15_t)0x2B1F, (q15_t)0x7862, (q15_t)0x2B7D, + (q15_t)0x7840, (q15_t)0x2BDC, (q15_t)0x781D, (q15_t)0x2C3A, + (q15_t)0x77FA, (q15_t)0x2C98, (q15_t)0x77D7, (q15_t)0x2CF7, + (q15_t)0x77B4, (q15_t)0x2D55, (q15_t)0x7790, (q15_t)0x2DB3, + (q15_t)0x776C, (q15_t)0x2E11, (q15_t)0x7747, (q15_t)0x2E6E, + (q15_t)0x7723, (q15_t)0x2ECC, (q15_t)0x76FE, (q15_t)0x2F29, + (q15_t)0x76D9, (q15_t)0x2F87, (q15_t)0x76B3, (q15_t)0x2FE4, + (q15_t)0x768E, (q15_t)0x3041, (q15_t)0x7668, (q15_t)0x309E, + (q15_t)0x7641, (q15_t)0x30FB, (q15_t)0x761B, (q15_t)0x3158, + (q15_t)0x75F4, (q15_t)0x31B5, (q15_t)0x75CC, (q15_t)0x3211, + (q15_t)0x75A5, (q15_t)0x326E, (q15_t)0x757D, (q15_t)0x32CA, + (q15_t)0x7555, (q15_t)0x3326, (q15_t)0x752D, (q15_t)0x3382, + (q15_t)0x7504, (q15_t)0x33DE, (q15_t)0x74DB, (q15_t)0x343A, + (q15_t)0x74B2, (q15_t)0x3496, (q15_t)0x7489, (q15_t)0x34F2, + (q15_t)0x745F, (q15_t)0x354D, (q15_t)0x7435, (q15_t)0x35A8, + (q15_t)0x740B, (q15_t)0x3604, (q15_t)0x73E0, (q15_t)0x365F, + (q15_t)0x73B5, (q15_t)0x36BA, (q15_t)0x738A, (q15_t)0x3714, + (q15_t)0x735F, (q15_t)0x376F, (q15_t)0x7333, (q15_t)0x37CA, + (q15_t)0x7307, (q15_t)0x3824, (q15_t)0x72DB, (q15_t)0x387E, + (q15_t)0x72AF, (q15_t)0x38D8, (q15_t)0x7282, (q15_t)0x3932, + (q15_t)0x7255, (q15_t)0x398C, (q15_t)0x7227, (q15_t)0x39E6, + (q15_t)0x71FA, (q15_t)0x3A40, (q15_t)0x71CC, (q15_t)0x3A99, + (q15_t)0x719E, (q15_t)0x3AF2, (q15_t)0x716F, (q15_t)0x3B4C, + (q15_t)0x7141, (q15_t)0x3BA5, (q15_t)0x7112, (q15_t)0x3BFD, + (q15_t)0x70E2, (q15_t)0x3C56, (q15_t)0x70B3, (q15_t)0x3CAF, + (q15_t)0x7083, (q15_t)0x3D07, (q15_t)0x7053, (q15_t)0x3D60, + (q15_t)0x7023, (q15_t)0x3DB8, (q15_t)0x6FF2, (q15_t)0x3E10, + (q15_t)0x6FC1, (q15_t)0x3E68, (q15_t)0x6F90, (q15_t)0x3EBF, + (q15_t)0x6F5F, (q15_t)0x3F17, (q15_t)0x6F2D, (q15_t)0x3F6E, + (q15_t)0x6EFB, (q15_t)0x3FC5, (q15_t)0x6EC9, (q15_t)0x401D, + (q15_t)0x6E96, (q15_t)0x4073, (q15_t)0x6E63, (q15_t)0x40CA, + (q15_t)0x6E30, (q15_t)0x4121, (q15_t)0x6DFD, (q15_t)0x4177, + (q15_t)0x6DCA, (q15_t)0x41CE, (q15_t)0x6D96, (q15_t)0x4224, + (q15_t)0x6D62, (q15_t)0x427A, (q15_t)0x6D2D, (q15_t)0x42D0, + (q15_t)0x6CF9, (q15_t)0x4325, (q15_t)0x6CC4, (q15_t)0x437B, + (q15_t)0x6C8F, (q15_t)0x43D0, (q15_t)0x6C59, (q15_t)0x4425, + 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(q15_t)0xE3F4, (q15_t)0x831C, (q15_t)0xE456, (q15_t)0x8306, + (q15_t)0xE4B8, (q15_t)0x82F0, (q15_t)0xE51B, (q15_t)0x82DB, + (q15_t)0xE57D, (q15_t)0x82C6, (q15_t)0xE5DF, (q15_t)0x82B1, + (q15_t)0xE642, (q15_t)0x829D, (q15_t)0xE6A4, (q15_t)0x8289, + (q15_t)0xE707, (q15_t)0x8275, (q15_t)0xE769, (q15_t)0x8262, + (q15_t)0xE7CC, (q15_t)0x824F, (q15_t)0xE82F, (q15_t)0x823C, + (q15_t)0xE892, (q15_t)0x8229, (q15_t)0xE8F5, (q15_t)0x8217, + (q15_t)0xE957, (q15_t)0x8205, (q15_t)0xE9BA, (q15_t)0x81F3, + (q15_t)0xEA1D, (q15_t)0x81E2, (q15_t)0xEA80, (q15_t)0x81D1, + (q15_t)0xEAE4, (q15_t)0x81C0, (q15_t)0xEB47, (q15_t)0x81B0, + (q15_t)0xEBAA, (q15_t)0x81A0, (q15_t)0xEC0D, (q15_t)0x8190, + (q15_t)0xEC71, (q15_t)0x8180, (q15_t)0xECD4, (q15_t)0x8171, + (q15_t)0xED37, (q15_t)0x8162, (q15_t)0xED9B, (q15_t)0x8154, + (q15_t)0xEDFE, (q15_t)0x8145, (q15_t)0xEE62, (q15_t)0x8137, + (q15_t)0xEEC6, (q15_t)0x812A, (q15_t)0xEF29, (q15_t)0x811C, + (q15_t)0xEF8D, (q15_t)0x810F, (q15_t)0xEFF1, (q15_t)0x8102, + (q15_t)0xF054, (q15_t)0x80F6, (q15_t)0xF0B8, (q15_t)0x80EA, + (q15_t)0xF11C, (q15_t)0x80DE, (q15_t)0xF180, (q15_t)0x80D2, + (q15_t)0xF1E4, (q15_t)0x80C7, (q15_t)0xF248, (q15_t)0x80BC, + (q15_t)0xF2AC, (q15_t)0x80B2, (q15_t)0xF310, (q15_t)0x80A7, + (q15_t)0xF374, (q15_t)0x809D, (q15_t)0xF3D8, (q15_t)0x8094, + (q15_t)0xF43C, (q15_t)0x808A, (q15_t)0xF4A0, (q15_t)0x8081, + (q15_t)0xF504, (q15_t)0x8078, (q15_t)0xF568, (q15_t)0x8070, + (q15_t)0xF5CC, (q15_t)0x8068, (q15_t)0xF631, (q15_t)0x8060, + (q15_t)0xF695, (q15_t)0x8058, (q15_t)0xF6F9, (q15_t)0x8051, + (q15_t)0xF75D, (q15_t)0x804A, (q15_t)0xF7C2, (q15_t)0x8043, + (q15_t)0xF826, (q15_t)0x803D, (q15_t)0xF88A, (q15_t)0x8037, + (q15_t)0xF8EF, (q15_t)0x8031, (q15_t)0xF953, (q15_t)0x802C, + (q15_t)0xF9B8, (q15_t)0x8027, (q15_t)0xFA1C, (q15_t)0x8022, + (q15_t)0xFA80, (q15_t)0x801E, (q15_t)0xFAE5, (q15_t)0x801A, + (q15_t)0xFB49, (q15_t)0x8016, (q15_t)0xFBAE, (q15_t)0x8012, + (q15_t)0xFC12, (q15_t)0x800F, (q15_t)0xFC77, (q15_t)0x800C, + (q15_t)0xFCDB, (q15_t)0x8009, (q15_t)0xFD40, (q15_t)0x8007, + (q15_t)0xFDA4, (q15_t)0x8005, (q15_t)0xFE09, (q15_t)0x8003, + (q15_t)0xFE6D, (q15_t)0x8002, (q15_t)0xFED2, (q15_t)0x8001, + (q15_t)0xFF36, (q15_t)0x8000, (q15_t)0xFF9B, (q15_t)0x8000 +}; +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_Q15_4096) +/** + @par + Example code for q15 Twiddle factors Generation:: + @par + 
for (i = 0; i< 3N/4; i++)
+  {
+     twiddleCoefq15[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefq15[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 4096, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to q15(Fixed point 1.15): + round(twiddleCoefq15(i) * pow(2, 15)) + */ +const q15_t twiddleCoef_4096_q15[6144] = +{ + (q15_t)0x7FFF, (q15_t)0x0000, (q15_t)0x7FFF, (q15_t)0x0032, + (q15_t)0x7FFF, (q15_t)0x0064, (q15_t)0x7FFF, (q15_t)0x0096, + (q15_t)0x7FFF, (q15_t)0x00C9, (q15_t)0x7FFF, (q15_t)0x00FB, + (q15_t)0x7FFE, (q15_t)0x012D, (q15_t)0x7FFE, (q15_t)0x015F, + (q15_t)0x7FFD, (q15_t)0x0192, (q15_t)0x7FFC, (q15_t)0x01C4, + (q15_t)0x7FFC, (q15_t)0x01F6, (q15_t)0x7FFB, (q15_t)0x0228, + (q15_t)0x7FFA, (q15_t)0x025B, (q15_t)0x7FF9, (q15_t)0x028D, + (q15_t)0x7FF8, (q15_t)0x02BF, (q15_t)0x7FF7, (q15_t)0x02F1, + (q15_t)0x7FF6, (q15_t)0x0324, (q15_t)0x7FF4, (q15_t)0x0356, + (q15_t)0x7FF3, (q15_t)0x0388, (q15_t)0x7FF2, (q15_t)0x03BA, + (q15_t)0x7FF0, (q15_t)0x03ED, (q15_t)0x7FEE, (q15_t)0x041F, + (q15_t)0x7FED, (q15_t)0x0451, (q15_t)0x7FEB, (q15_t)0x0483, + (q15_t)0x7FE9, (q15_t)0x04B6, (q15_t)0x7FE7, (q15_t)0x04E8, + (q15_t)0x7FE5, (q15_t)0x051A, (q15_t)0x7FE3, (q15_t)0x054C, + (q15_t)0x7FE1, (q15_t)0x057F, (q15_t)0x7FDF, (q15_t)0x05B1, + (q15_t)0x7FDD, (q15_t)0x05E3, (q15_t)0x7FDA, (q15_t)0x0615, + (q15_t)0x7FD8, (q15_t)0x0647, (q15_t)0x7FD6, (q15_t)0x067A, + (q15_t)0x7FD3, (q15_t)0x06AC, (q15_t)0x7FD0, (q15_t)0x06DE, + (q15_t)0x7FCE, (q15_t)0x0710, (q15_t)0x7FCB, (q15_t)0x0742, + (q15_t)0x7FC8, (q15_t)0x0775, (q15_t)0x7FC5, (q15_t)0x07A7, + (q15_t)0x7FC2, (q15_t)0x07D9, (q15_t)0x7FBF, (q15_t)0x080B, + (q15_t)0x7FBC, (q15_t)0x083D, (q15_t)0x7FB8, (q15_t)0x086F, + (q15_t)0x7FB5, (q15_t)0x08A2, (q15_t)0x7FB1, (q15_t)0x08D4, + (q15_t)0x7FAE, (q15_t)0x0906, (q15_t)0x7FAA, (q15_t)0x0938, + (q15_t)0x7FA7, (q15_t)0x096A, (q15_t)0x7FA3, (q15_t)0x099C, + (q15_t)0x7F9F, (q15_t)0x09CE, (q15_t)0x7F9B, (q15_t)0x0A00, + (q15_t)0x7F97, (q15_t)0x0A33, (q15_t)0x7F93, (q15_t)0x0A65, + (q15_t)0x7F8F, (q15_t)0x0A97, (q15_t)0x7F8B, (q15_t)0x0AC9, + (q15_t)0x7F87, (q15_t)0x0AFB, (q15_t)0x7F82, (q15_t)0x0B2D, + (q15_t)0x7F7E, (q15_t)0x0B5F, (q15_t)0x7F79, (q15_t)0x0B91, + (q15_t)0x7F75, (q15_t)0x0BC3, (q15_t)0x7F70, (q15_t)0x0BF5, + (q15_t)0x7F6B, (q15_t)0x0C27, (q15_t)0x7F67, (q15_t)0x0C59, + (q15_t)0x7F62, (q15_t)0x0C8B, (q15_t)0x7F5D, (q15_t)0x0CBD, + (q15_t)0x7F58, (q15_t)0x0CEF, (q15_t)0x7F53, (q15_t)0x0D21, + (q15_t)0x7F4D, (q15_t)0x0D53, (q15_t)0x7F48, (q15_t)0x0D85, + (q15_t)0x7F43, (q15_t)0x0DB7, (q15_t)0x7F3D, (q15_t)0x0DE9, + (q15_t)0x7F38, (q15_t)0x0E1B, (q15_t)0x7F32, (q15_t)0x0E4D, + (q15_t)0x7F2D, (q15_t)0x0E7F, (q15_t)0x7F27, (q15_t)0x0EB1, + (q15_t)0x7F21, (q15_t)0x0EE3, (q15_t)0x7F1B, (q15_t)0x0F15, + (q15_t)0x7F15, (q15_t)0x0F47, (q15_t)0x7F0F, (q15_t)0x0F79, + (q15_t)0x7F09, (q15_t)0x0FAB, (q15_t)0x7F03, (q15_t)0x0FDD, + (q15_t)0x7EFD, (q15_t)0x100E, (q15_t)0x7EF6, (q15_t)0x1040, + (q15_t)0x7EF0, (q15_t)0x1072, (q15_t)0x7EE9, (q15_t)0x10A4, + (q15_t)0x7EE3, (q15_t)0x10D6, (q15_t)0x7EDC, (q15_t)0x1108, + (q15_t)0x7ED5, (q15_t)0x1139, (q15_t)0x7ECF, (q15_t)0x116B, + (q15_t)0x7EC8, (q15_t)0x119D, (q15_t)0x7EC1, (q15_t)0x11CF, + (q15_t)0x7EBA, (q15_t)0x1201, (q15_t)0x7EB3, (q15_t)0x1232, + (q15_t)0x7EAB, (q15_t)0x1264, (q15_t)0x7EA4, (q15_t)0x1296, + (q15_t)0x7E9D, (q15_t)0x12C8, (q15_t)0x7E95, (q15_t)0x12F9, + (q15_t)0x7E8E, (q15_t)0x132B, (q15_t)0x7E86, (q15_t)0x135D, + (q15_t)0x7E7F, (q15_t)0x138E, (q15_t)0x7E77, (q15_t)0x13C0, + (q15_t)0x7E6F, (q15_t)0x13F2, (q15_t)0x7E67, (q15_t)0x1423, + (q15_t)0x7E5F, (q15_t)0x1455, (q15_t)0x7E57, (q15_t)0x1487, + (q15_t)0x7E4F, (q15_t)0x14B8, (q15_t)0x7E47, (q15_t)0x14EA, + (q15_t)0x7E3F, (q15_t)0x151B, (q15_t)0x7E37, (q15_t)0x154D, + (q15_t)0x7E2E, (q15_t)0x157F, (q15_t)0x7E26, (q15_t)0x15B0, + (q15_t)0x7E1D, (q15_t)0x15E2, (q15_t)0x7E14, (q15_t)0x1613, + (q15_t)0x7E0C, (q15_t)0x1645, (q15_t)0x7E03, (q15_t)0x1676, + (q15_t)0x7DFA, (q15_t)0x16A8, (q15_t)0x7DF1, (q15_t)0x16D9, + (q15_t)0x7DE8, (q15_t)0x170A, (q15_t)0x7DDF, (q15_t)0x173C, + (q15_t)0x7DD6, (q15_t)0x176D, (q15_t)0x7DCD, (q15_t)0x179F, + (q15_t)0x7DC3, (q15_t)0x17D0, (q15_t)0x7DBA, (q15_t)0x1802, + (q15_t)0x7DB0, (q15_t)0x1833, (q15_t)0x7DA7, (q15_t)0x1864, + (q15_t)0x7D9D, (q15_t)0x1896, (q15_t)0x7D94, (q15_t)0x18C7, + (q15_t)0x7D8A, (q15_t)0x18F8, (q15_t)0x7D80, (q15_t)0x192A, + (q15_t)0x7D76, (q15_t)0x195B, (q15_t)0x7D6C, (q15_t)0x198C, + (q15_t)0x7D62, (q15_t)0x19BD, (q15_t)0x7D58, (q15_t)0x19EF, + (q15_t)0x7D4E, (q15_t)0x1A20, (q15_t)0x7D43, (q15_t)0x1A51, + (q15_t)0x7D39, (q15_t)0x1A82, (q15_t)0x7D2F, (q15_t)0x1AB3, + (q15_t)0x7D24, (q15_t)0x1AE4, (q15_t)0x7D19, (q15_t)0x1B16, + (q15_t)0x7D0F, (q15_t)0x1B47, (q15_t)0x7D04, (q15_t)0x1B78, + (q15_t)0x7CF9, (q15_t)0x1BA9, (q15_t)0x7CEE, (q15_t)0x1BDA, + (q15_t)0x7CE3, (q15_t)0x1C0B, (q15_t)0x7CD8, (q15_t)0x1C3C, + (q15_t)0x7CCD, (q15_t)0x1C6D, (q15_t)0x7CC2, (q15_t)0x1C9E, + (q15_t)0x7CB7, (q15_t)0x1CCF, (q15_t)0x7CAB, (q15_t)0x1D00, + (q15_t)0x7CA0, (q15_t)0x1D31, (q15_t)0x7C94, (q15_t)0x1D62, + (q15_t)0x7C89, (q15_t)0x1D93, (q15_t)0x7C7D, (q15_t)0x1DC4, + (q15_t)0x7C71, (q15_t)0x1DF5, (q15_t)0x7C66, (q15_t)0x1E25, + (q15_t)0x7C5A, (q15_t)0x1E56, (q15_t)0x7C4E, (q15_t)0x1E87, + (q15_t)0x7C42, (q15_t)0x1EB8, (q15_t)0x7C36, (q15_t)0x1EE9, + (q15_t)0x7C29, (q15_t)0x1F19, (q15_t)0x7C1D, (q15_t)0x1F4A, + (q15_t)0x7C11, (q15_t)0x1F7B, (q15_t)0x7C05, (q15_t)0x1FAC, + (q15_t)0x7BF8, (q15_t)0x1FDC, (q15_t)0x7BEB, (q15_t)0x200D, + (q15_t)0x7BDF, (q15_t)0x203E, (q15_t)0x7BD2, (q15_t)0x206E, + (q15_t)0x7BC5, (q15_t)0x209F, (q15_t)0x7BB9, (q15_t)0x20D0, + (q15_t)0x7BAC, (q15_t)0x2100, (q15_t)0x7B9F, (q15_t)0x2131, + (q15_t)0x7B92, (q15_t)0x2161, (q15_t)0x7B84, (q15_t)0x2192, + (q15_t)0x7B77, (q15_t)0x21C2, (q15_t)0x7B6A, (q15_t)0x21F3, + (q15_t)0x7B5D, (q15_t)0x2223, (q15_t)0x7B4F, (q15_t)0x2254, + (q15_t)0x7B42, (q15_t)0x2284, (q15_t)0x7B34, (q15_t)0x22B4, + (q15_t)0x7B26, (q15_t)0x22E5, (q15_t)0x7B19, (q15_t)0x2315, + (q15_t)0x7B0B, (q15_t)0x2345, (q15_t)0x7AFD, (q15_t)0x2376, + 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(q15_t)0x9842, (q15_t)0xB504, (q15_t)0x9860, (q15_t)0xB4DB, + (q15_t)0x987D, (q15_t)0xB4B3, (q15_t)0x989B, (q15_t)0xB48A, + (q15_t)0x98B9, (q15_t)0xB461, (q15_t)0x98D6, (q15_t)0xB439, + (q15_t)0x98F4, (q15_t)0xB410, (q15_t)0x9912, (q15_t)0xB3E8, + (q15_t)0x9930, (q15_t)0xB3C0, (q15_t)0x994E, (q15_t)0xB397, + (q15_t)0x996C, (q15_t)0xB36F, (q15_t)0x998A, (q15_t)0xB347, + (q15_t)0x99A8, (q15_t)0xB31E, (q15_t)0x99C6, (q15_t)0xB2F6, + (q15_t)0x99E5, (q15_t)0xB2CE, (q15_t)0x9A03, (q15_t)0xB2A6, + (q15_t)0x9A22, (q15_t)0xB27E, (q15_t)0x9A40, (q15_t)0xB256, + (q15_t)0x9A5F, (q15_t)0xB22E, (q15_t)0x9A7D, (q15_t)0xB206, + (q15_t)0x9A9C, (q15_t)0xB1DE, (q15_t)0x9ABA, (q15_t)0xB1B7, + (q15_t)0x9AD9, (q15_t)0xB18F, (q15_t)0x9AF8, (q15_t)0xB167, + (q15_t)0x9B17, (q15_t)0xB140, (q15_t)0x9B36, (q15_t)0xB118, + (q15_t)0x9B55, (q15_t)0xB0F0, (q15_t)0x9B74, (q15_t)0xB0C9, + (q15_t)0x9B93, (q15_t)0xB0A1, (q15_t)0x9BB2, (q15_t)0xB07A, + (q15_t)0x9BD2, (q15_t)0xB053, (q15_t)0x9BF1, (q15_t)0xB02B, + (q15_t)0x9C10, (q15_t)0xB004, (q15_t)0x9C30, (q15_t)0xAFDD, + (q15_t)0x9C4F, (q15_t)0xAFB6, (q15_t)0x9C6F, (q15_t)0xAF8F, + (q15_t)0x9C8E, (q15_t)0xAF68, (q15_t)0x9CAE, (q15_t)0xAF40, + (q15_t)0x9CCE, (q15_t)0xAF1A, (q15_t)0x9CEE, (q15_t)0xAEF3, + (q15_t)0x9D0D, (q15_t)0xAECC, (q15_t)0x9D2D, (q15_t)0xAEA5, + (q15_t)0x9D4D, (q15_t)0xAE7E, (q15_t)0x9D6D, (q15_t)0xAE57, + (q15_t)0x9D8E, (q15_t)0xAE31, (q15_t)0x9DAE, (q15_t)0xAE0A, + (q15_t)0x9DCE, (q15_t)0xADE3, (q15_t)0x9DEE, (q15_t)0xADBD, + (q15_t)0x9E0E, (q15_t)0xAD96, (q15_t)0x9E2F, (q15_t)0xAD70, + (q15_t)0x9E4F, (q15_t)0xAD4A, (q15_t)0x9E70, (q15_t)0xAD23, + (q15_t)0x9E90, (q15_t)0xACFD, (q15_t)0x9EB1, (q15_t)0xACD7, + (q15_t)0x9ED2, (q15_t)0xACB1, (q15_t)0x9EF2, (q15_t)0xAC8A, + (q15_t)0x9F13, (q15_t)0xAC64, (q15_t)0x9F34, (q15_t)0xAC3E, + (q15_t)0x9F55, (q15_t)0xAC18, (q15_t)0x9F76, (q15_t)0xABF2, + (q15_t)0x9F97, (q15_t)0xABCC, (q15_t)0x9FB8, (q15_t)0xABA7, + (q15_t)0x9FD9, (q15_t)0xAB81, (q15_t)0x9FFB, (q15_t)0xAB5B, + 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(q15_t)0xB796, (q15_t)0x9673, (q15_t)0xB7BF, (q15_t)0x9657, + (q15_t)0xB7E9, (q15_t)0x963B, (q15_t)0xB812, (q15_t)0x961E, + (q15_t)0xB83C, (q15_t)0x9602, (q15_t)0xB865, (q15_t)0x95E6, + (q15_t)0xB88F, (q15_t)0x95CA, (q15_t)0xB8B9, (q15_t)0x95AE, + (q15_t)0xB8E3, (q15_t)0x9592, (q15_t)0xB90C, (q15_t)0x9576, + (q15_t)0xB936, (q15_t)0x955A, (q15_t)0xB960, (q15_t)0x953E, + (q15_t)0xB98A, (q15_t)0x9523, (q15_t)0xB9B4, (q15_t)0x9507, + (q15_t)0xB9DE, (q15_t)0x94EC, (q15_t)0xBA08, (q15_t)0x94D0, + (q15_t)0xBA32, (q15_t)0x94B5, (q15_t)0xBA5C, (q15_t)0x9499, + (q15_t)0xBA87, (q15_t)0x947E, (q15_t)0xBAB1, (q15_t)0x9463, + (q15_t)0xBADB, (q15_t)0x9447, (q15_t)0xBB05, (q15_t)0x942C, + (q15_t)0xBB30, (q15_t)0x9411, (q15_t)0xBB5A, (q15_t)0x93F6, + (q15_t)0xBB85, (q15_t)0x93DB, (q15_t)0xBBAF, (q15_t)0x93C0, + (q15_t)0xBBDA, (q15_t)0x93A6, (q15_t)0xBC04, (q15_t)0x938B, + (q15_t)0xBC2F, (q15_t)0x9370, (q15_t)0xBC5A, (q15_t)0x9356, + (q15_t)0xBC84, (q15_t)0x933B, (q15_t)0xBCAF, (q15_t)0x9321, + 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(q15_t)0xD367, (q15_t)0x8805, (q15_t)0xD396, (q15_t)0x87F3, + (q15_t)0xD3C5, (q15_t)0x87E2, (q15_t)0xD3F4, (q15_t)0x87D1, + (q15_t)0xD423, (q15_t)0x87BF, (q15_t)0xD452, (q15_t)0x87AE, + (q15_t)0xD482, (q15_t)0x879D, (q15_t)0xD4B1, (q15_t)0x878C, + (q15_t)0xD4E0, (q15_t)0x877B, (q15_t)0xD510, (q15_t)0x876A, + (q15_t)0xD53F, (q15_t)0x8759, (q15_t)0xD56E, (q15_t)0x8749, + (q15_t)0xD59E, (q15_t)0x8738, (q15_t)0xD5CD, (q15_t)0x8727, + (q15_t)0xD5FD, (q15_t)0x8717, (q15_t)0xD62C, (q15_t)0x8706, + (q15_t)0xD65C, (q15_t)0x86F6, (q15_t)0xD68B, (q15_t)0x86E6, + (q15_t)0xD6BB, (q15_t)0x86D5, (q15_t)0xD6EA, (q15_t)0x86C5, + (q15_t)0xD71A, (q15_t)0x86B5, (q15_t)0xD74A, (q15_t)0x86A5, + (q15_t)0xD779, (q15_t)0x8695, (q15_t)0xD7A9, (q15_t)0x8685, + (q15_t)0xD7D9, (q15_t)0x8675, (q15_t)0xD809, (q15_t)0x8666, + (q15_t)0xD838, (q15_t)0x8656, (q15_t)0xD868, (q15_t)0x8646, + (q15_t)0xD898, (q15_t)0x8637, (q15_t)0xD8C8, (q15_t)0x8627, + (q15_t)0xD8F8, (q15_t)0x8618, (q15_t)0xD927, (q15_t)0x8609, + (q15_t)0xD957, (q15_t)0x85FA, (q15_t)0xD987, (q15_t)0x85EA, + (q15_t)0xD9B7, (q15_t)0x85DB, (q15_t)0xD9E7, (q15_t)0x85CC, + (q15_t)0xDA17, (q15_t)0x85BD, (q15_t)0xDA47, (q15_t)0x85AF, + (q15_t)0xDA77, (q15_t)0x85A0, (q15_t)0xDAA7, (q15_t)0x8591, + (q15_t)0xDAD7, (q15_t)0x8582, (q15_t)0xDB08, (q15_t)0x8574, + (q15_t)0xDB38, (q15_t)0x8565, (q15_t)0xDB68, (q15_t)0x8557, + (q15_t)0xDB98, (q15_t)0x8549, (q15_t)0xDBC8, (q15_t)0x853A, + (q15_t)0xDBF8, (q15_t)0x852C, (q15_t)0xDC29, (q15_t)0x851E, + (q15_t)0xDC59, (q15_t)0x8510, (q15_t)0xDC89, (q15_t)0x8502, + (q15_t)0xDCBA, (q15_t)0x84F4, (q15_t)0xDCEA, (q15_t)0x84E6, + (q15_t)0xDD1A, (q15_t)0x84D9, (q15_t)0xDD4B, (q15_t)0x84CB, + (q15_t)0xDD7B, (q15_t)0x84BD, (q15_t)0xDDAB, (q15_t)0x84B0, + (q15_t)0xDDDC, (q15_t)0x84A2, (q15_t)0xDE0C, (q15_t)0x8495, + (q15_t)0xDE3D, (q15_t)0x8488, (q15_t)0xDE6D, (q15_t)0x847B, + (q15_t)0xDE9E, (q15_t)0x846D, (q15_t)0xDECE, (q15_t)0x8460, + (q15_t)0xDEFF, (q15_t)0x8453, (q15_t)0xDF2F, (q15_t)0x8446, + (q15_t)0xDF60, (q15_t)0x843A, (q15_t)0xDF91, (q15_t)0x842D, + (q15_t)0xDFC1, (q15_t)0x8420, (q15_t)0xDFF2, (q15_t)0x8414, + (q15_t)0xE023, (q15_t)0x8407, (q15_t)0xE053, (q15_t)0x83FA, + (q15_t)0xE084, (q15_t)0x83EE, (q15_t)0xE0B5, (q15_t)0x83E2, + (q15_t)0xE0E6, (q15_t)0x83D6, (q15_t)0xE116, (q15_t)0x83C9, + (q15_t)0xE147, (q15_t)0x83BD, (q15_t)0xE178, (q15_t)0x83B1, + (q15_t)0xE1A9, (q15_t)0x83A5, (q15_t)0xE1DA, (q15_t)0x8399, + (q15_t)0xE20A, (q15_t)0x838E, (q15_t)0xE23B, (q15_t)0x8382, + (q15_t)0xE26C, (q15_t)0x8376, (q15_t)0xE29D, (q15_t)0x836B, + (q15_t)0xE2CE, (q15_t)0x835F, (q15_t)0xE2FF, (q15_t)0x8354, + (q15_t)0xE330, (q15_t)0x8348, (q15_t)0xE361, (q15_t)0x833D, + (q15_t)0xE392, (q15_t)0x8332, (q15_t)0xE3C3, (q15_t)0x8327, + (q15_t)0xE3F4, (q15_t)0x831C, (q15_t)0xE425, (q15_t)0x8311, + (q15_t)0xE456, (q15_t)0x8306, (q15_t)0xE487, (q15_t)0x82FB, + (q15_t)0xE4B8, (q15_t)0x82F0, (q15_t)0xE4E9, (q15_t)0x82E6, + (q15_t)0xE51B, (q15_t)0x82DB, (q15_t)0xE54C, (q15_t)0x82D0, + (q15_t)0xE57D, (q15_t)0x82C6, (q15_t)0xE5AE, (q15_t)0x82BC, + (q15_t)0xE5DF, (q15_t)0x82B1, (q15_t)0xE610, (q15_t)0x82A7, + (q15_t)0xE642, (q15_t)0x829D, (q15_t)0xE673, (q15_t)0x8293, + (q15_t)0xE6A4, (q15_t)0x8289, (q15_t)0xE6D5, (q15_t)0x827F, + (q15_t)0xE707, (q15_t)0x8275, (q15_t)0xE738, (q15_t)0x826B, + (q15_t)0xE769, (q15_t)0x8262, (q15_t)0xE79B, (q15_t)0x8258, + (q15_t)0xE7CC, (q15_t)0x824F, (q15_t)0xE7FD, (q15_t)0x8245, + (q15_t)0xE82F, (q15_t)0x823C, (q15_t)0xE860, (q15_t)0x8232, + (q15_t)0xE892, (q15_t)0x8229, (q15_t)0xE8C3, (q15_t)0x8220, + (q15_t)0xE8F5, (q15_t)0x8217, (q15_t)0xE926, (q15_t)0x820E, + (q15_t)0xE957, (q15_t)0x8205, (q15_t)0xE989, (q15_t)0x81FC, + (q15_t)0xE9BA, (q15_t)0x81F3, (q15_t)0xE9EC, (q15_t)0x81EB, + (q15_t)0xEA1D, (q15_t)0x81E2, (q15_t)0xEA4F, (q15_t)0x81D9, + (q15_t)0xEA80, (q15_t)0x81D1, (q15_t)0xEAB2, (q15_t)0x81C8, + (q15_t)0xEAE4, (q15_t)0x81C0, (q15_t)0xEB15, (q15_t)0x81B8, + (q15_t)0xEB47, (q15_t)0x81B0, (q15_t)0xEB78, (q15_t)0x81A8, + (q15_t)0xEBAA, (q15_t)0x81A0, (q15_t)0xEBDC, (q15_t)0x8198, + (q15_t)0xEC0D, (q15_t)0x8190, (q15_t)0xEC3F, (q15_t)0x8188, + (q15_t)0xEC71, (q15_t)0x8180, (q15_t)0xECA2, (q15_t)0x8179, + (q15_t)0xECD4, (q15_t)0x8171, (q15_t)0xED06, (q15_t)0x816A, + (q15_t)0xED37, (q15_t)0x8162, (q15_t)0xED69, (q15_t)0x815B, + (q15_t)0xED9B, (q15_t)0x8154, (q15_t)0xEDCD, (q15_t)0x814C, + (q15_t)0xEDFE, (q15_t)0x8145, (q15_t)0xEE30, (q15_t)0x813E, + (q15_t)0xEE62, (q15_t)0x8137, (q15_t)0xEE94, (q15_t)0x8130, + (q15_t)0xEEC6, (q15_t)0x812A, (q15_t)0xEEF7, (q15_t)0x8123, + (q15_t)0xEF29, (q15_t)0x811C, (q15_t)0xEF5B, (q15_t)0x8116, + (q15_t)0xEF8D, (q15_t)0x810F, (q15_t)0xEFBF, (q15_t)0x8109, + (q15_t)0xEFF1, (q15_t)0x8102, (q15_t)0xF022, (q15_t)0x80FC, + (q15_t)0xF054, (q15_t)0x80F6, (q15_t)0xF086, (q15_t)0x80F0, + (q15_t)0xF0B8, (q15_t)0x80EA, (q15_t)0xF0EA, (q15_t)0x80E4, + (q15_t)0xF11C, (q15_t)0x80DE, (q15_t)0xF14E, (q15_t)0x80D8, + (q15_t)0xF180, (q15_t)0x80D2, (q15_t)0xF1B2, (q15_t)0x80CD, + (q15_t)0xF1E4, (q15_t)0x80C7, (q15_t)0xF216, (q15_t)0x80C2, + (q15_t)0xF248, (q15_t)0x80BC, (q15_t)0xF27A, (q15_t)0x80B7, + (q15_t)0xF2AC, (q15_t)0x80B2, (q15_t)0xF2DE, (q15_t)0x80AC, + (q15_t)0xF310, (q15_t)0x80A7, (q15_t)0xF342, (q15_t)0x80A2, + (q15_t)0xF374, (q15_t)0x809D, (q15_t)0xF3A6, (q15_t)0x8098, + (q15_t)0xF3D8, (q15_t)0x8094, (q15_t)0xF40A, (q15_t)0x808F, + (q15_t)0xF43C, (q15_t)0x808A, (q15_t)0xF46E, (q15_t)0x8086, + (q15_t)0xF4A0, (q15_t)0x8081, (q15_t)0xF4D2, (q15_t)0x807D, + (q15_t)0xF504, (q15_t)0x8078, (q15_t)0xF536, (q15_t)0x8074, + (q15_t)0xF568, (q15_t)0x8070, (q15_t)0xF59A, (q15_t)0x806C, + (q15_t)0xF5CC, (q15_t)0x8068, (q15_t)0xF5FF, (q15_t)0x8064, + (q15_t)0xF631, (q15_t)0x8060, (q15_t)0xF663, (q15_t)0x805C, + (q15_t)0xF695, (q15_t)0x8058, (q15_t)0xF6C7, (q15_t)0x8055, + (q15_t)0xF6F9, (q15_t)0x8051, (q15_t)0xF72B, (q15_t)0x804E, + (q15_t)0xF75D, (q15_t)0x804A, (q15_t)0xF790, (q15_t)0x8047, + (q15_t)0xF7C2, (q15_t)0x8043, (q15_t)0xF7F4, (q15_t)0x8040, + (q15_t)0xF826, (q15_t)0x803D, (q15_t)0xF858, (q15_t)0x803A, + (q15_t)0xF88A, (q15_t)0x8037, (q15_t)0xF8BD, (q15_t)0x8034, + (q15_t)0xF8EF, (q15_t)0x8031, (q15_t)0xF921, (q15_t)0x802F, + (q15_t)0xF953, (q15_t)0x802C, (q15_t)0xF985, (q15_t)0x8029, + (q15_t)0xF9B8, (q15_t)0x8027, (q15_t)0xF9EA, (q15_t)0x8025, + (q15_t)0xFA1C, (q15_t)0x8022, (q15_t)0xFA4E, (q15_t)0x8020, + (q15_t)0xFA80, (q15_t)0x801E, (q15_t)0xFAB3, (q15_t)0x801C, + (q15_t)0xFAE5, (q15_t)0x801A, (q15_t)0xFB17, (q15_t)0x8018, + (q15_t)0xFB49, (q15_t)0x8016, (q15_t)0xFB7C, (q15_t)0x8014, + (q15_t)0xFBAE, (q15_t)0x8012, (q15_t)0xFBE0, (q15_t)0x8011, + (q15_t)0xFC12, (q15_t)0x800F, (q15_t)0xFC45, (q15_t)0x800D, + (q15_t)0xFC77, (q15_t)0x800C, (q15_t)0xFCA9, (q15_t)0x800B, + (q15_t)0xFCDB, (q15_t)0x8009, (q15_t)0xFD0E, (q15_t)0x8008, + (q15_t)0xFD40, (q15_t)0x8007, (q15_t)0xFD72, (q15_t)0x8006, + (q15_t)0xFDA4, (q15_t)0x8005, (q15_t)0xFDD7, (q15_t)0x8004, + (q15_t)0xFE09, (q15_t)0x8003, (q15_t)0xFE3B, (q15_t)0x8003, + (q15_t)0xFE6D, (q15_t)0x8002, (q15_t)0xFEA0, (q15_t)0x8001, + (q15_t)0xFED2, (q15_t)0x8001, (q15_t)0xFF04, (q15_t)0x8000, + (q15_t)0xFF36, (q15_t)0x8000, (q15_t)0xFF69, (q15_t)0x8000, + (q15_t)0xFF9B, (q15_t)0x8000, (q15_t)0xFFCD, (q15_t)0x8000 +}; + +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + +/** + @} end of CFFT_CIFFT group +*/ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREVIDX_FLT64_16) + +const uint16_t riscvBitRevIndexTableF64_16[RISCVBITREVINDEXTABLEF64_16_TABLE_LENGTH] = +{ + /* radix 4, size 12 */ + 8,64, 16,32, 24,96, 40,80, 56,112, 88,104 +}; +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREVIDX_FLT64_32) +const uint16_t riscvBitRevIndexTableF64_32[RISCVBITREVINDEXTABLEF64_32_TABLE_LENGTH] = +{ + /* 4x2, size 24 */ + 8,128, 16,64, 24,192, 40,160, 48,96, 56,224, 72,144, + 88,208, 104,176, 120,240, 152,200, 184,232 +}; +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREVIDX_FLT64_64) +const uint16_t riscvBitRevIndexTableF64_64[RISCVBITREVINDEXTABLEF64_64_TABLE_LENGTH] = +{ + /* radix 4, size 56 */ + 8,256, 16,128, 24,384, 32,64, 40,320, 48,192, 56,448, 72,288, 80,160, 88,416, 104,352, + 112,224, 120,480, 136,272, 152,400, 168,336, 176,208, 184,464, 200,304, 216,432, + 232,368, 248,496, 280,392, 296,328, 312,456, 344,424, 376,488, 440,472 +}; +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREVIDX_FLT64_128) +const uint16_t riscvBitRevIndexTableF64_128[RISCVBITREVINDEXTABLEF64_128_TABLE_LENGTH] = +{ + /* 4x2, size 112 */ + 8,512, 16,256, 24,768, 32,128, 40,640, 48,384, 56,896, 72,576, 80,320, 88,832, 96,192, + 104,704, 112,448, 120,960, 136,544, 144,288, 152,800, 168,672, 176,416, 184,928, 200,608, + 208,352, 216,864, 232,736, 240,480, 248,992, 264,528, 280,784, 296,656, 304,400, 312,912, + 328,592, 344,848, 360,720, 368,464, 376,976, 392,560, 408,816, 424,688, 440,944, 456,624, + 472,880, 488,752, 504,1008, 536,776, 552,648, 568,904, 600,840, 616,712, 632,968, + 664,808, 696,936, 728,872, 760,1000, 824,920, 888,984 +}; +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREVIDX_FLT64_256) +const uint16_t riscvBitRevIndexTableF64_256[RISCVBITREVINDEXTABLEF64_256_TABLE_LENGTH] = +{ + /* radix 4, size 240 */ + 8,1024, 16,512, 24,1536, 32,256, 40,1280, 48,768, 56,1792, 64,128, 72,1152, 80,640, + 88,1664, 96,384, 104,1408, 112,896, 120,1920, 136,1088, 144,576, 152,1600, 160,320, + 168,1344, 176,832, 184,1856, 200,1216, 208,704, 216,1728, 224,448, 232,1472, 240,960, + 248,1984, 264,1056, 272,544, 280,1568, 296,1312, 304,800, 312,1824, 328,1184, 336,672, + 344,1696, 352,416, 360,1440, 368,928, 376,1952, 392,1120, 400,608, 408,1632, 424,1376, + 432,864, 440,1888, 456,1248, 464,736, 472,1760, 488,1504, 496,992, 504,2016, 520,1040, + 536,1552, 552,1296, 560,784, 568,1808, 584,1168, 592,656, 600,1680, 616,1424, 624,912, + 632,1936, 648,1104, 664,1616, 680,1360, 688,848, 696,1872, 712,1232, 728,1744, 744,1488, + 752,976, 760,2000, 776,1072, 792,1584, 808,1328, 824,1840, 840,1200, 856,1712, 872,1456, + 880,944, 888,1968, 904,1136, 920,1648, 936,1392, 952,1904, 968,1264, 984,1776, 1000,1520, + 1016,2032, 1048,1544, 1064,1288, 1080,1800, 1096,1160, 1112,1672, 1128,1416, 1144,1928, + 1176,1608, 1192,1352, 1208,1864, 1240,1736, 1256,1480, 1272,1992, 1304,1576, 1336,1832, + 1368,1704, 1384,1448, 1400,1960, 1432,1640, 1464,1896, 1496,1768, 1528,2024, 1592,1816, + 1624,1688, 1656,1944, 1720,1880, 1784,2008, 1912,1976 +}; +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREVIDX_FLT64_512) +const uint16_t riscvBitRevIndexTableF64_512[RISCVBITREVINDEXTABLEF64_512_TABLE_LENGTH] = +{ + /* 4x2, size 480 */ + 8,2048, 16,1024, 24,3072, 32,512, 40,2560, 48,1536, 56,3584, 64,256, 72,2304, 80,1280, + 88,3328, 96,768, 104,2816, 112,1792, 120,3840, 136,2176, 144,1152, 152,3200, 160,640, + 168,2688, 176,1664, 184,3712, 192,384, 200,2432, 208,1408, 216,3456, 224,896, 232,2944, + 240,1920, 248,3968, 264,2112, 272,1088, 280,3136, 288,576, 296,2624, 304,1600, 312,3648, + 328,2368, 336,1344, 344,3392, 352,832, 360,2880, 368,1856, 376,3904, 392,2240, 400,1216, + 408,3264, 416,704, 424,2752, 432,1728, 440,3776, 456,2496, 464,1472, 472,3520, 480,960, + 488,3008, 496,1984, 504,4032, 520,2080, 528,1056, 536,3104, 552,2592, 560,1568, 568,3616, + 584,2336, 592,1312, 600,3360, 608,800, 616,2848, 624,1824, 632,3872, 648,2208, 656,1184, + 664,3232, 680,2720, 688,1696, 696,3744, 712,2464, 720,1440, 728,3488, 736,928, 744,2976, + 752,1952, 760,4000, 776,2144, 784,1120, 792,3168, 808,2656, 816,1632, 824,3680, 840,2400, + 848,1376, 856,3424, 872,2912, 880,1888, 888,3936, 904,2272, 912,1248, 920,3296, 936,2784, + 944,1760, 952,3808, 968,2528, 976,1504, 984,3552, 1000,3040, 1008,2016, 1016,4064, + 1032,2064, 1048,3088, 1064,2576, 1072,1552, 1080,3600, 1096,2320, 1104,1296, 1112,3344, + 1128,2832, 1136,1808, 1144,3856, 1160,2192, 1176,3216, 1192,2704, 1200,1680, 1208,3728, + 1224,2448, 1232,1424, 1240,3472, 1256,2960, 1264,1936, 1272,3984, 1288,2128, 1304,3152, + 1320,2640, 1328,1616, 1336,3664, 1352,2384, 1368,3408, 1384,2896, 1392,1872, 1400,3920, + 1416,2256, 1432,3280, 1448,2768, 1456,1744, 1464,3792, 1480,2512, 1496,3536, 1512,3024, + 1520,2000, 1528,4048, 1544,2096, 1560,3120, 1576,2608, 1592,3632, 1608,2352, 1624,3376, + 1640,2864, 1648,1840, 1656,3888, 1672,2224, 1688,3248, 1704,2736, 1720,3760, 1736,2480, + 1752,3504, 1768,2992, 1776,1968, 1784,4016, 1800,2160, 1816,3184, 1832,2672, 1848,3696, + 1864,2416, 1880,3440, 1896,2928, 1912,3952, 1928,2288, 1944,3312, 1960,2800, 1976,3824, + 1992,2544, 2008,3568, 2024,3056, 2040,4080, 2072,3080, 2088,2568, 2104,3592, 2120,2312, + 2136,3336, 2152,2824, 2168,3848, 2200,3208, 2216,2696, 2232,3720, 2248,2440, 2264,3464, + 2280,2952, 2296,3976, 2328,3144, 2344,2632, 2360,3656, 2392,3400, 2408,2888, 2424,3912, + 2456,3272, 2472,2760, 2488,3784, 2520,3528, 2536,3016, 2552,4040, 2584,3112, 2616,3624, + 2648,3368, 2664,2856, 2680,3880, 2712,3240, 2744,3752, 2776,3496, 2792,2984, 2808,4008, + 2840,3176, 2872,3688, 2904,3432, 2936,3944, 2968,3304, 3000,3816, 3032,3560, 3064,4072, + 3128,3608, 3160,3352, 3192,3864, 3256,3736, 3288,3480, 3320,3992, 3384,3672, 3448,3928, + 3512,3800, 3576,4056, 3704,3896, 3832,4024 +}; +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREVIDX_FLT64_1024) +const uint16_t riscvBitRevIndexTableF64_1024[RISCVBITREVINDEXTABLEF64_1024_TABLE_LENGTH] = +{ + /* radix 4, size 992 */ + 8,4096, 16,2048, 24,6144, 32,1024, 40,5120, 48,3072, 56,7168, 64,512, 72,4608, + 80,2560, 88,6656, 96,1536, 104,5632, 112,3584, 120,7680, 128,256, 136,4352, + 144,2304, 152,6400, 160,1280, 168,5376, 176,3328, 184,7424, 192,768, 200,4864, + 208,2816, 216,6912, 224,1792, 232,5888, 240,3840, 248,7936, 264,4224, 272,2176, + 280,6272, 288,1152, 296,5248, 304,3200, 312,7296, 320,640, 328,4736, 336,2688, + 344,6784, 352,1664, 360,5760, 368,3712, 376,7808, 392,4480, 400,2432, 408,6528, + 416,1408, 424,5504, 432,3456, 440,7552, 448,896, 456,4992, 464,2944, 472,7040, + 480,1920, 488,6016, 496,3968, 504,8064, 520,4160, 528,2112, 536,6208, 544,1088, + 552,5184, 560,3136, 568,7232, 584,4672, 592,2624, 600,6720, 608,1600, 616,5696, + 624,3648, 632,7744, 648,4416, 656,2368, 664,6464, 672,1344, 680,5440, 688,3392, + 696,7488, 704,832, 712,4928, 720,2880, 728,6976, 736,1856, 744,5952, 752,3904, + 760,8000, 776,4288, 784,2240, 792,6336, 800,1216, 808,5312, 816,3264, 824,7360, + 840,4800, 848,2752, 856,6848, 864,1728, 872,5824, 880,3776, 888,7872, 904,4544, + 912,2496, 920,6592, 928,1472, 936,5568, 944,3520, 952,7616, 968,5056, 976,3008, + 984,7104, 992,1984, 1000,6080, 1008,4032, 1016,8128, 1032,4128, 1040,2080, + 1048,6176, 1064,5152, 1072,3104, 1080,7200, 1096,4640, 1104,2592, 1112,6688, + 1120,1568, 1128,5664, 1136,3616, 1144,7712, 1160,4384, 1168,2336, 1176,6432, + 1184,1312, 1192,5408, 1200,3360, 1208,7456, 1224,4896, 1232,2848, 1240,6944, + 1248,1824, 1256,5920, 1264,3872, 1272,7968, 1288,4256, 1296,2208, 1304,6304, + 1320,5280, 1328,3232, 1336,7328, 1352,4768, 1360,2720, 1368,6816, 1376,1696, + 1384,5792, 1392,3744, 1400,7840, 1416,4512, 1424,2464, 1432,6560, 1448,5536, + 1456,3488, 1464,7584, 1480,5024, 1488,2976, 1496,7072, 1504,1952, 1512,6048, + 1520,4000, 1528,8096, 1544,4192, 1552,2144, 1560,6240, 1576,5216, 1584,3168, + 1592,7264, 1608,4704, 1616,2656, 1624,6752, 1640,5728, 1648,3680, 1656,7776, + 1672,4448, 1680,2400, 1688,6496, 1704,5472, 1712,3424, 1720,7520, 1736,4960, + 1744,2912, 1752,7008, 1760,1888, 1768,5984, 1776,3936, 1784,8032, 1800,4320, + 1808,2272, 1816,6368, 1832,5344, 1840,3296, 1848,7392, 1864,4832, 1872,2784, + 1880,6880, 1896,5856, 1904,3808, 1912,7904, 1928,4576, 1936,2528, 1944,6624, + 1960,5600, 1968,3552, 1976,7648, 1992,5088, 2000,3040, 2008,7136, 2024,6112, + 2032,4064, 2040,8160, 2056,4112, 2072,6160, 2088,5136, 2096,3088, 2104,7184, + 2120,4624, 2128,2576, 2136,6672, 2152,5648, 2160,3600, 2168,7696, 2184,4368, + 2192,2320, 2200,6416, 2216,5392, 2224,3344, 2232,7440, 2248,4880, 2256,2832, + 2264,6928, 2280,5904, 2288,3856, 2296,7952, 2312,4240, 2328,6288, 2344,5264, + 2352,3216, 2360,7312, 2376,4752, 2384,2704, 2392,6800, 2408,5776, 2416,3728, + 2424,7824, 2440,4496, 2456,6544, 2472,5520, 2480,3472, 2488,7568, 2504,5008, + 2512,2960, 2520,7056, 2536,6032, 2544,3984, 2552,8080, 2568,4176, 2584,6224, + 2600,5200, 2608,3152, 2616,7248, 2632,4688, 2648,6736, 2664,5712, 2672,3664, + 2680,7760, 2696,4432, 2712,6480, 2728,5456, 2736,3408, 2744,7504, 2760,4944, + 2768,2896, 2776,6992, 2792,5968, 2800,3920, 2808,8016, 2824,4304, 2840,6352, + 2856,5328, 2864,3280, 2872,7376, 2888,4816, 2904,6864, 2920,5840, 2928,3792, + 2936,7888, 2952,4560, 2968,6608, 2984,5584, 2992,3536, 3000,7632, 3016,5072, + 3032,7120, 3048,6096, 3056,4048, 3064,8144, 3080,4144, 3096,6192, 3112,5168, + 3128,7216, 3144,4656, 3160,6704, 3176,5680, 3184,3632, 3192,7728, 3208,4400, + 3224,6448, 3240,5424, 3248,3376, 3256,7472, 3272,4912, 3288,6960, 3304,5936, + 3312,3888, 3320,7984, 3336,4272, 3352,6320, 3368,5296, 3384,7344, 3400,4784, + 3416,6832, 3432,5808, 3440,3760, 3448,7856, 3464,4528, 3480,6576, 3496,5552, + 3512,7600, 3528,5040, 3544,7088, 3560,6064, 3568,4016, 3576,8112, 3592,4208, + 3608,6256, 3624,5232, 3640,7280, 3656,4720, 3672,6768, 3688,5744, 3704,7792, + 3720,4464, 3736,6512, 3752,5488, 3768,7536, 3784,4976, 3800,7024, 3816,6000, + 3824,3952, 3832,8048, 3848,4336, 3864,6384, 3880,5360, 3896,7408, 3912,4848, + 3928,6896, 3944,5872, 3960,7920, 3976,4592, 3992,6640, 4008,5616, 4024,7664, + 4040,5104, 4056,7152, 4072,6128, 4088,8176, 4120,6152, 4136,5128, 4152,7176, + 4168,4616, 4184,6664, 4200,5640, 4216,7688, 4232,4360, 4248,6408, 4264,5384, + 4280,7432, 4296,4872, 4312,6920, 4328,5896, 4344,7944, 4376,6280, 4392,5256, + 4408,7304, 4424,4744, 4440,6792, 4456,5768, 4472,7816, 4504,6536, 4520,5512, + 4536,7560, 4552,5000, 4568,7048, 4584,6024, 4600,8072, 4632,6216, 4648,5192, + 4664,7240, 4696,6728, 4712,5704, 4728,7752, 4760,6472, 4776,5448, 4792,7496, + 4808,4936, 4824,6984, 4840,5960, 4856,8008, 4888,6344, 4904,5320, 4920,7368, + 4952,6856, 4968,5832, 4984,7880, 5016,6600, 5032,5576, 5048,7624, 5080,7112, + 5096,6088, 5112,8136, 5144,6184, 5176,7208, 5208,6696, 5224,5672, 5240,7720, + 5272,6440, 5288,5416, 5304,7464, 5336,6952, 5352,5928, 5368,7976, 5400,6312, + 5432,7336, 5464,6824, 5480,5800, 5496,7848, 5528,6568, 5560,7592, 5592,7080, + 5608,6056, 5624,8104, 5656,6248, 5688,7272, 5720,6760, 5752,7784, 5784,6504, + 5816,7528, 5848,7016, 5864,5992, 5880,8040, 5912,6376, 5944,7400, 5976,6888, + 6008,7912, 6040,6632, 6072,7656, 6104,7144, 6136,8168, 6200,7192, 6232,6680, + 6264,7704, 6296,6424, 6328,7448, 6360,6936, 6392,7960, 6456,7320, 6488,6808, + 6520,7832, 6584,7576, 6616,7064, 6648,8088, 6712,7256, 6776,7768, 6840,7512, + 6872,7000, 6904,8024, 6968,7384, 7032,7896, 7096,7640, 7160,8152, 7288,7736, + 7352,7480, 7416,7992, 7544,7864, 7672,8120, 7928,8056 +}; +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREVIDX_FLT64_2048) +const uint16_t riscvBitRevIndexTableF64_2048[RISCVBITREVINDEXTABLEF64_2048_TABLE_LENGTH] = +{ + /* 4x2, size 1984 */ + 8,8192, 16,4096, 24,12288, 32,2048, 40,10240, 48,6144, 56,14336, 64,1024, + 72,9216, 80,5120, 88,13312, 96,3072, 104,11264, 112,7168, 120,15360, 128,512, + 136,8704, 144,4608, 152,12800, 160,2560, 168,10752, 176,6656, 184,14848, + 192,1536, 200,9728, 208,5632, 216,13824, 224,3584, 232,11776, 240,7680, + 248,15872, 264,8448, 272,4352, 280,12544, 288,2304, 296,10496, 304,6400, + 312,14592, 320,1280, 328,9472, 336,5376, 344,13568, 352,3328, 360,11520, + 368,7424, 376,15616, 384,768, 392,8960, 400,4864, 408,13056, 416,2816, + 424,11008, 432,6912, 440,15104, 448,1792, 456,9984, 464,5888, 472,14080, + 480,3840, 488,12032, 496,7936, 504,16128, 520,8320, 528,4224, 536,12416, + 544,2176, 552,10368, 560,6272, 568,14464, 576,1152, 584,9344, 592,5248, + 600,13440, 608,3200, 616,11392, 624,7296, 632,15488, 648,8832, 656,4736, + 664,12928, 672,2688, 680,10880, 688,6784, 696,14976, 704,1664, 712,9856, + 720,5760, 728,13952, 736,3712, 744,11904, 752,7808, 760,16000, 776,8576, + 784,4480, 792,12672, 800,2432, 808,10624, 816,6528, 824,14720, 832,1408, + 840,9600, 848,5504, 856,13696, 864,3456, 872,11648, 880,7552, 888,15744, + 904,9088, 912,4992, 920,13184, 928,2944, 936,11136, 944,7040, 952,15232, + 960,1920, 968,10112, 976,6016, 984,14208, 992,3968, 1000,12160, 1008,8064, + 1016,16256, 1032,8256, 1040,4160, 1048,12352, 1056,2112, 1064,10304, 1072,6208, + 1080,14400, 1096,9280, 1104,5184, 1112,13376, 1120,3136, 1128,11328, 1136,7232, + 1144,15424, 1160,8768, 1168,4672, 1176,12864, 1184,2624, 1192,10816, 1200,6720, + 1208,14912, 1216,1600, 1224,9792, 1232,5696, 1240,13888, 1248,3648, 1256,11840, + 1264,7744, 1272,15936, 1288,8512, 1296,4416, 1304,12608, 1312,2368, 1320,10560, + 1328,6464, 1336,14656, 1352,9536, 1360,5440, 1368,13632, 1376,3392, 1384,11584, + 1392,7488, 1400,15680, 1416,9024, 1424,4928, 1432,13120, 1440,2880, 1448,11072, + 1456,6976, 1464,15168, 1472,1856, 1480,10048, 1488,5952, 1496,14144, 1504,3904, + 1512,12096, 1520,8000, 1528,16192, 1544,8384, 1552,4288, 1560,12480, 1568,2240, + 1576,10432, 1584,6336, 1592,14528, 1608,9408, 1616,5312, 1624,13504, 1632,3264, + 1640,11456, 1648,7360, 1656,15552, 1672,8896, 1680,4800, 1688,12992, 1696,2752, + 1704,10944, 1712,6848, 1720,15040, 1736,9920, 1744,5824, 1752,14016, 1760,3776, + 1768,11968, 1776,7872, 1784,16064, 1800,8640, 1808,4544, 1816,12736, 1824,2496, + 1832,10688, 1840,6592, 1848,14784, 1864,9664, 1872,5568, 1880,13760, 1888,3520, + 1896,11712, 1904,7616, 1912,15808, 1928,9152, 1936,5056, 1944,13248, 1952,3008, + 1960,11200, 1968,7104, 1976,15296, 1992,10176, 2000,6080, 2008,14272, 2016,4032, + 2024,12224, 2032,8128, 2040,16320, 2056,8224, 2064,4128, 2072,12320, 2088,10272, + 2096,6176, 2104,14368, 2120,9248, 2128,5152, 2136,13344, 2144,3104, 2152,11296, + 2160,7200, 2168,15392, 2184,8736, 2192,4640, 2200,12832, 2208,2592, 2216,10784, + 2224,6688, 2232,14880, 2248,9760, 2256,5664, 2264,13856, 2272,3616, 2280,11808, + 2288,7712, 2296,15904, 2312,8480, 2320,4384, 2328,12576, 2344,10528, 2352,6432, + 2360,14624, 2376,9504, 2384,5408, 2392,13600, 2400,3360, 2408,11552, 2416,7456, + 2424,15648, 2440,8992, 2448,4896, 2456,13088, 2464,2848, 2472,11040, 2480,6944, + 2488,15136, 2504,10016, 2512,5920, 2520,14112, 2528,3872, 2536,12064, 2544,7968, + 2552,16160, 2568,8352, 2576,4256, 2584,12448, 2600,10400, 2608,6304, 2616,14496, + 2632,9376, 2640,5280, 2648,13472, 2656,3232, 2664,11424, 2672,7328, 2680,15520, + 2696,8864, 2704,4768, 2712,12960, 2728,10912, 2736,6816, 2744,15008, 2760,9888, + 2768,5792, 2776,13984, 2784,3744, 2792,11936, 2800,7840, 2808,16032, 2824,8608, + 2832,4512, 2840,12704, 2856,10656, 2864,6560, 2872,14752, 2888,9632, 2896,5536, + 2904,13728, 2912,3488, 2920,11680, 2928,7584, 2936,15776, 2952,9120, 2960,5024, + 2968,13216, 2984,11168, 2992,7072, 3000,15264, 3016,10144, 3024,6048, + 3032,14240, 3040,4000, 3048,12192, 3056,8096, 3064,16288, 3080,8288, 3088,4192, + 3096,12384, 3112,10336, 3120,6240, 3128,14432, 3144,9312, 3152,5216, 3160,13408, + 3176,11360, 3184,7264, 3192,15456, 3208,8800, 3216,4704, 3224,12896, 3240,10848, + 3248,6752, 3256,14944, 3272,9824, 3280,5728, 3288,13920, 3296,3680, 3304,11872, + 3312,7776, 3320,15968, 3336,8544, 3344,4448, 3352,12640, 3368,10592, 3376,6496, + 3384,14688, 3400,9568, 3408,5472, 3416,13664, 3432,11616, 3440,7520, 3448,15712, + 3464,9056, 3472,4960, 3480,13152, 3496,11104, 3504,7008, 3512,15200, 3528,10080, + 3536,5984, 3544,14176, 3552,3936, 3560,12128, 3568,8032, 3576,16224, 3592,8416, + 3600,4320, 3608,12512, 3624,10464, 3632,6368, 3640,14560, 3656,9440, 3664,5344, + 3672,13536, 3688,11488, 3696,7392, 3704,15584, 3720,8928, 3728,4832, 3736,13024, + 3752,10976, 3760,6880, 3768,15072, 3784,9952, 3792,5856, 3800,14048, 3816,12000, + 3824,7904, 3832,16096, 3848,8672, 3856,4576, 3864,12768, 3880,10720, 3888,6624, + 3896,14816, 3912,9696, 3920,5600, 3928,13792, 3944,11744, 3952,7648, 3960,15840, + 3976,9184, 3984,5088, 3992,13280, 4008,11232, 4016,7136, 4024,15328, 4040,10208, + 4048,6112, 4056,14304, 4072,12256, 4080,8160, 4088,16352, 4104,8208, 4120,12304, + 4136,10256, 4144,6160, 4152,14352, 4168,9232, 4176,5136, 4184,13328, 4200,11280, + 4208,7184, 4216,15376, 4232,8720, 4240,4624, 4248,12816, 4264,10768, 4272,6672, + 4280,14864, 4296,9744, 4304,5648, 4312,13840, 4328,11792, 4336,7696, 4344,15888, + 4360,8464, 4376,12560, 4392,10512, 4400,6416, 4408,14608, 4424,9488, 4432,5392, + 4440,13584, 4456,11536, 4464,7440, 4472,15632, 4488,8976, 4496,4880, 4504,13072, + 4520,11024, 4528,6928, 4536,15120, 4552,10000, 4560,5904, 4568,14096, + 4584,12048, 4592,7952, 4600,16144, 4616,8336, 4632,12432, 4648,10384, 4656,6288, + 4664,14480, 4680,9360, 4688,5264, 4696,13456, 4712,11408, 4720,7312, 4728,15504, + 4744,8848, 4760,12944, 4776,10896, 4784,6800, 4792,14992, 4808,9872, 4816,5776, + 4824,13968, 4840,11920, 4848,7824, 4856,16016, 4872,8592, 4888,12688, + 4904,10640, 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15864,16248 +}; +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREVIDX_FLT64_4096) +const uint16_t riscvBitRevIndexTableF64_4096[RISCVBITREVINDEXTABLEF64_4096_TABLE_LENGTH] = +{ + /* radix 4, size 4032 */ + 8,16384, 16,8192, 24,24576, 32,4096, 40,20480, 48,12288, 56,28672, 64,2048, + 72,18432, 80,10240, 88,26624, 96,6144, 104,22528, 112,14336, 120,30720, + 128,1024, 136,17408, 144,9216, 152,25600, 160,5120, 168,21504, 176,13312, + 184,29696, 192,3072, 200,19456, 208,11264, 216,27648, 224,7168, 232,23552, + 240,15360, 248,31744, 256,512, 264,16896, 272,8704, 280,25088, 288,4608, + 296,20992, 304,12800, 312,29184, 320,2560, 328,18944, 336,10752, 344,27136, + 352,6656, 360,23040, 368,14848, 376,31232, 384,1536, 392,17920, 400,9728, + 408,26112, 416,5632, 424,22016, 432,13824, 440,30208, 448,3584, 456,19968, + 464,11776, 472,28160, 480,7680, 488,24064, 496,15872, 504,32256, 520,16640, + 528,8448, 536,24832, 544,4352, 552,20736, 560,12544, 568,28928, 576,2304, + 584,18688, 592,10496, 600,26880, 608,6400, 616,22784, 624,14592, 632,30976, + 640,1280, 648,17664, 656,9472, 664,25856, 672,5376, 680,21760, 688,13568, + 696,29952, 704,3328, 712,19712, 720,11520, 728,27904, 736,7424, 744,23808, + 752,15616, 760,32000, 776,17152, 784,8960, 792,25344, 800,4864, 808,21248, + 816,13056, 824,29440, 832,2816, 840,19200, 848,11008, 856,27392, 864,6912, + 872,23296, 880,15104, 888,31488, 896,1792, 904,18176, 912,9984, 920,26368, + 928,5888, 936,22272, 944,14080, 952,30464, 960,3840, 968,20224, 976,12032, + 984,28416, 992,7936, 1000,24320, 1008,16128, 1016,32512, 1032,16512, 1040,8320, + 1048,24704, 1056,4224, 1064,20608, 1072,12416, 1080,28800, 1088,2176, + 1096,18560, 1104,10368, 1112,26752, 1120,6272, 1128,22656, 1136,14464, + 1144,30848, 1160,17536, 1168,9344, 1176,25728, 1184,5248, 1192,21632, + 1200,13440, 1208,29824, 1216,3200, 1224,19584, 1232,11392, 1240,27776, + 1248,7296, 1256,23680, 1264,15488, 1272,31872, 1288,17024, 1296,8832, + 1304,25216, 1312,4736, 1320,21120, 1328,12928, 1336,29312, 1344,2688, + 1352,19072, 1360,10880, 1368,27264, 1376,6784, 1384,23168, 1392,14976, + 1400,31360, 1408,1664, 1416,18048, 1424,9856, 1432,26240, 1440,5760, 1448,22144, + 1456,13952, 1464,30336, 1472,3712, 1480,20096, 1488,11904, 1496,28288, + 1504,7808, 1512,24192, 1520,16000, 1528,32384, 1544,16768, 1552,8576, + 1560,24960, 1568,4480, 1576,20864, 1584,12672, 1592,29056, 1600,2432, + 1608,18816, 1616,10624, 1624,27008, 1632,6528, 1640,22912, 1648,14720, + 1656,31104, 1672,17792, 1680,9600, 1688,25984, 1696,5504, 1704,21888, + 1712,13696, 1720,30080, 1728,3456, 1736,19840, 1744,11648, 1752,28032, + 1760,7552, 1768,23936, 1776,15744, 1784,32128, 1800,17280, 1808,9088, + 1816,25472, 1824,4992, 1832,21376, 1840,13184, 1848,29568, 1856,2944, + 1864,19328, 1872,11136, 1880,27520, 1888,7040, 1896,23424, 1904,15232, + 1912,31616, 1928,18304, 1936,10112, 1944,26496, 1952,6016, 1960,22400, + 1968,14208, 1976,30592, 1984,3968, 1992,20352, 2000,12160, 2008,28544, + 2016,8064, 2024,24448, 2032,16256, 2040,32640, 2056,16448, 2064,8256, + 2072,24640, 2080,4160, 2088,20544, 2096,12352, 2104,28736, 2120,18496, + 2128,10304, 2136,26688, 2144,6208, 2152,22592, 2160,14400, 2168,30784, + 2184,17472, 2192,9280, 2200,25664, 2208,5184, 2216,21568, 2224,13376, + 2232,29760, 2240,3136, 2248,19520, 2256,11328, 2264,27712, 2272,7232, + 2280,23616, 2288,15424, 2296,31808, 2312,16960, 2320,8768, 2328,25152, + 2336,4672, 2344,21056, 2352,12864, 2360,29248, 2368,2624, 2376,19008, + 2384,10816, 2392,27200, 2400,6720, 2408,23104, 2416,14912, 2424,31296, + 2440,17984, 2448,9792, 2456,26176, 2464,5696, 2472,22080, 2480,13888, + 2488,30272, 2496,3648, 2504,20032, 2512,11840, 2520,28224, 2528,7744, + 2536,24128, 2544,15936, 2552,32320, 2568,16704, 2576,8512, 2584,24896, + 2592,4416, 2600,20800, 2608,12608, 2616,28992, 2632,18752, 2640,10560, + 2648,26944, 2656,6464, 2664,22848, 2672,14656, 2680,31040, 2696,17728, + 2704,9536, 2712,25920, 2720,5440, 2728,21824, 2736,13632, 2744,30016, 2752,3392, + 2760,19776, 2768,11584, 2776,27968, 2784,7488, 2792,23872, 2800,15680, + 2808,32064, 2824,17216, 2832,9024, 2840,25408, 2848,4928, 2856,21312, + 2864,13120, 2872,29504, 2888,19264, 2896,11072, 2904,27456, 2912,6976, + 2920,23360, 2928,15168, 2936,31552, 2952,18240, 2960,10048, 2968,26432, + 2976,5952, 2984,22336, 2992,14144, 3000,30528, 3008,3904, 3016,20288, + 3024,12096, 3032,28480, 3040,8000, 3048,24384, 3056,16192, 3064,32576, + 3080,16576, 3088,8384, 3096,24768, 3104,4288, 3112,20672, 3120,12480, + 3128,28864, 3144,18624, 3152,10432, 3160,26816, 3168,6336, 3176,22720, + 3184,14528, 3192,30912, 3208,17600, 3216,9408, 3224,25792, 3232,5312, + 3240,21696, 3248,13504, 3256,29888, 3272,19648, 3280,11456, 3288,27840, + 3296,7360, 3304,23744, 3312,15552, 3320,31936, 3336,17088, 3344,8896, + 3352,25280, 3360,4800, 3368,21184, 3376,12992, 3384,29376, 3400,19136, + 3408,10944, 3416,27328, 3424,6848, 3432,23232, 3440,15040, 3448,31424, + 3464,18112, 3472,9920, 3480,26304, 3488,5824, 3496,22208, 3504,14016, + 3512,30400, 3520,3776, 3528,20160, 3536,11968, 3544,28352, 3552,7872, + 3560,24256, 3568,16064, 3576,32448, 3592,16832, 3600,8640, 3608,25024, + 3616,4544, 3624,20928, 3632,12736, 3640,29120, 3656,18880, 3664,10688, + 3672,27072, 3680,6592, 3688,22976, 3696,14784, 3704,31168, 3720,17856, + 3728,9664, 3736,26048, 3744,5568, 3752,21952, 3760,13760, 3768,30144, + 3784,19904, 3792,11712, 3800,28096, 3808,7616, 3816,24000, 3824,15808, + 3832,32192, 3848,17344, 3856,9152, 3864,25536, 3872,5056, 3880,21440, + 3888,13248, 3896,29632, 3912,19392, 3920,11200, 3928,27584, 3936,7104, + 3944,23488, 3952,15296, 3960,31680, 3976,18368, 3984,10176, 3992,26560, + 4000,6080, 4008,22464, 4016,14272, 4024,30656, 4040,20416, 4048,12224, + 4056,28608, 4064,8128, 4072,24512, 4080,16320, 4088,32704, 4104,16416, + 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21848,27304, 21864,23208, 21880,31400, 21912,26280, 21928,22184, 21944,30376, + 21976,28328, 21992,24232, 22008,32424, 22040,25000, 22072,29096, 22104,27048, + 22120,22952, 22136,31144, 22168,26024, 22200,30120, 22232,28072, 22248,23976, + 22264,32168, 22296,25512, 22328,29608, 22360,27560, 22376,23464, 22392,31656, + 22424,26536, 22456,30632, 22488,28584, 22504,24488, 22520,32680, 22552,24680, + 22584,28776, 22616,26728, 22648,30824, 22680,25704, 22712,29800, 22744,27752, + 22760,23656, 22776,31848, 22808,25192, 22840,29288, 22872,27240, 22888,23144, + 22904,31336, 22936,26216, 22968,30312, 23000,28264, 23016,24168, 23032,32360, + 23064,24936, 23096,29032, 23128,26984, 23160,31080, 23192,25960, 23224,30056, + 23256,28008, 23272,23912, 23288,32104, 23320,25448, 23352,29544, 23384,27496, + 23416,31592, 23448,26472, 23480,30568, 23512,28520, 23528,24424, 23544,32616, + 23576,24808, 23608,28904, 23640,26856, 23672,30952, 23704,25832, 23736,29928, + 23768,27880, 23800,31976, 23832,25320, 23864,29416, 23896,27368, 23928,31464, + 23960,26344, 23992,30440, 24024,28392, 24040,24296, 24056,32488, 24088,25064, + 24120,29160, 24152,27112, 24184,31208, 24216,26088, 24248,30184, 24280,28136, + 24312,32232, 24344,25576, 24376,29672, 24408,27624, 24440,31720, 24472,26600, + 24504,30696, 24536,28648, 24568,32744, 24632,28696, 24664,26648, 24696,30744, + 24728,25624, 24760,29720, 24792,27672, 24824,31768, 24856,25112, 24888,29208, + 24920,27160, 24952,31256, 24984,26136, 25016,30232, 25048,28184, 25080,32280, + 25144,28952, 25176,26904, 25208,31000, 25240,25880, 25272,29976, 25304,27928, + 25336,32024, 25400,29464, 25432,27416, 25464,31512, 25496,26392, 25528,30488, + 25560,28440, 25592,32536, 25656,28824, 25688,26776, 25720,30872, 25784,29848, + 25816,27800, 25848,31896, 25912,29336, 25944,27288, 25976,31384, 26008,26264, + 26040,30360, 26072,28312, 26104,32408, 26168,29080, 26200,27032, 26232,31128, + 26296,30104, 26328,28056, 26360,32152, 26424,29592, 26456,27544, 26488,31640, + 26552,30616, 26584,28568, 26616,32664, 26680,28760, 26744,30808, 26808,29784, + 26840,27736, 26872,31832, 26936,29272, 26968,27224, 27000,31320, 27064,30296, + 27096,28248, 27128,32344, 27192,29016, 27256,31064, 27320,30040, 27352,27992, + 27384,32088, 27448,29528, 27512,31576, 27576,30552, 27608,28504, 27640,32600, + 27704,28888, 27768,30936, 27832,29912, 27896,31960, 27960,29400, 28024,31448, + 28088,30424, 28120,28376, 28152,32472, 28216,29144, 28280,31192, 28344,30168, + 28408,32216, 28472,29656, 28536,31704, 28600,30680, 28664,32728, 28792,30776, + 28856,29752, 28920,31800, 28984,29240, 29048,31288, 29112,30264, 29176,32312, + 29304,31032, 29368,30008, 29432,32056, 29560,31544, 29624,30520, 29688,32568, + 29816,30904, 29944,31928, 30072,31416, 30136,30392, 30200,32440, 30328,31160, + 30456,32184, 30584,31672, 30712,32696, 30968,31864, 31096,31352, 31224,32376, + 31480,32120, 31736,32632, 32248,32504 +}; +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREVIDX_FLT_16) + +const uint16_t riscvBitRevIndexTable16[RISCVBITREVINDEXTABLE_16_TABLE_LENGTH] = +{ + /* 8x2, size 20 */ + 8,64, 24,72, 16,64, 40,80, 32,64, 56,88, 48,72, 88,104, 72,96, 104,112 +}; + +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREVIDX_FLT_32) + +const uint16_t riscvBitRevIndexTable32[RISCVBITREVINDEXTABLE_32_TABLE_LENGTH] = +{ + /* 8x4, size 48 */ + 8,64, 16,128, 24,192, 32,64, 40,72, 48,136, 56,200, 64,128, 72,80, 88,208, + 80,144, 96,192, 104,208, 112,152, 120,216, 136,192, 144,160, 168,208, + 152,224, 176,208, 184,232, 216,240, 200,224, 232,240 +}; + +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREVIDX_FLT_64) + +const uint16_t riscvBitRevIndexTable64[RISCVBITREVINDEXTABLE_64_TABLE_LENGTH] = +{ + /* radix 8, size 56 */ + 8,64, 16,128, 24,192, 32,256, 40,320, 48,384, 56,448, 80,136, 88,200, + 96,264, 104,328, 112,392, 120,456, 152,208, 160,272, 168,336, 176,400, + 184,464, 224,280, 232,344, 240,408, 248,472, 296,352, 304,416, 312,480, + 368,424, 376,488, 440,496 +}; + +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREVIDX_FLT_128) + +const uint16_t riscvBitRevIndexTable128[RISCVBITREVINDEXTABLE_128_TABLE_LENGTH] = +{ + /* 8x2, size 208 */ + 8,512, 16,64, 24,576, 32,128, 40,640, 48,192, 56,704, 64,256, 72,768, + 80,320, 88,832, 96,384, 104,896, 112,448, 120,960, 128,512, 136,520, + 144,768, 152,584, 160,520, 168,648, 176,200, 184,712, 192,264, 200,776, + 208,328, 216,840, 224,392, 232,904, 240,456, 248,968, 264,528, 272,320, + 280,592, 288,768, 296,656, 304,328, 312,720, 328,784, 344,848, 352,400, + 360,912, 368,464, 376,976, 384,576, 392,536, 400,832, 408,600, 416,584, + 424,664, 432,840, 440,728, 448,592, 456,792, 464,848, 472,856, 480,600, + 488,920, 496,856, 504,984, 520,544, 528,576, 536,608, 552,672, 560,608, + 568,736, 576,768, 584,800, 592,832, 600,864, 608,800, 616,928, 624,864, + 632,992, 648,672, 656,896, 664,928, 688,904, 696,744, 704,896, 712,808, + 720,912, 728,872, 736,928, 744,936, 752,920, 760,1000, 776,800, 784,832, + 792,864, 808,904, 816,864, 824,920, 840,864, 856,880, 872,944, 888,1008, + 904,928, 912,960, 920,992, 944,968, 952,1000, 968,992, 984,1008 +}; + +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREVIDX_FLT_256) + +const uint16_t riscvBitRevIndexTable256[RISCVBITREVINDEXTABLE_256_TABLE_LENGTH] = +{ + /* 8x4, size 440 */ + 8,512, 16,1024, 24,1536, 32,64, 40,576, 48,1088, 56,1600, 64,128, 72,640, + 80,1152, 88,1664, 96,192, 104,704, 112,1216, 120,1728, 128,256, 136,768, + 144,1280, 152,1792, 160,320, 168,832, 176,1344, 184,1856, 192,384, + 200,896, 208,1408, 216,1920, 224,448, 232,960, 240,1472, 248,1984, + 256,512, 264,520, 272,1032, 280,1544, 288,640, 296,584, 304,1096, 312,1608, + 320,768, 328,648, 336,1160, 344,1672, 352,896, 360,712, 368,1224, 376,1736, + 384,520, 392,776, 400,1288, 408,1800, 416,648, 424,840, 432,1352, 440,1864, + 448,776, 456,904, 464,1416, 472,1928, 480,904, 488,968, 496,1480, 504,1992, + 520,528, 512,1024, 528,1040, 536,1552, 544,1152, 552,592, 560,1104, + 568,1616, 576,1280, 584,656, 592,1168, 600,1680, 608,1408, 616,720, + 624,1232, 632,1744, 640,1032, 648,784, 656,1296, 664,1808, 672,1160, + 680,848, 688,1360, 696,1872, 704,1288, 712,912, 720,1424, 728,1936, + 736,1416, 744,976, 752,1488, 760,2000, 768,1536, 776,1552, 784,1048, + 792,1560, 800,1664, 808,1680, 816,1112, 824,1624, 832,1792, 840,1808, + 848,1176, 856,1688, 864,1920, 872,1936, 880,1240, 888,1752, 896,1544, + 904,1560, 912,1304, 920,1816, 928,1672, 936,1688, 944,1368, 952,1880, + 960,1800, 968,1816, 976,1432, 984,1944, 992,1928, 1000,1944, 1008,1496, + 1016,2008, 1032,1152, 1040,1056, 1048,1568, 1064,1408, 1072,1120, + 1080,1632, 1088,1536, 1096,1160, 1104,1184, 1112,1696, 1120,1552, + 1128,1416, 1136,1248, 1144,1760, 1160,1664, 1168,1312, 1176,1824, + 1184,1544, 1192,1920, 1200,1376, 1208,1888, 1216,1568, 1224,1672, + 1232,1440, 1240,1952, 1248,1560, 1256,1928, 1264,1504, 1272,2016, + 1288,1312, 1296,1408, 1304,1576, 1320,1424, 1328,1416, 1336,1640, + 1344,1792, 1352,1824, 1360,1920, 1368,1704, 1376,1800, 1384,1432, + 1392,1928, 1400,1768, 1416,1680, 1432,1832, 1440,1576, 1448,1936, + 1456,1832, 1464,1896, 1472,1808, 1480,1688, 1488,1936, 1496,1960, + 1504,1816, 1512,1944, 1520,1944, 1528,2024, 1560,1584, 1592,1648, + 1600,1792, 1608,1920, 1616,1800, 1624,1712, 1632,1808, 1640,1936, + 1648,1816, 1656,1776, 1672,1696, 1688,1840, 1704,1952, 1712,1928, + 1720,1904, 1728,1824, 1736,1952, 1744,1832, 1752,1968, 1760,1840, + 1768,1960, 1776,1944, 1784,2032, 1864,1872, 1848,1944, 1872,1888, + 1880,1904, 1888,1984, 1896,2000, 1912,2032, 1904,2016, 1976,2032, + 1960,1968, 2008,2032, 1992,2016, 2024,2032 +}; + +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREVIDX_FLT_512) + +const uint16_t riscvBitRevIndexTable512[RISCVBITREVINDEXTABLE_512_TABLE_LENGTH] = +{ + /* radix 8, size 448 */ + 8,512, 16,1024, 24,1536, 32,2048, 40,2560, 48,3072, 56,3584, 72,576, + 80,1088, 88,1600, 96,2112, 104,2624, 112,3136, 120,3648, 136,640, 144,1152, + 152,1664, 160,2176, 168,2688, 176,3200, 184,3712, 200,704, 208,1216, + 216,1728, 224,2240, 232,2752, 240,3264, 248,3776, 264,768, 272,1280, + 280,1792, 288,2304, 296,2816, 304,3328, 312,3840, 328,832, 336,1344, + 344,1856, 352,2368, 360,2880, 368,3392, 376,3904, 392,896, 400,1408, + 408,1920, 416,2432, 424,2944, 432,3456, 440,3968, 456,960, 464,1472, + 472,1984, 480,2496, 488,3008, 496,3520, 504,4032, 528,1032, 536,1544, + 544,2056, 552,2568, 560,3080, 568,3592, 592,1096, 600,1608, 608,2120, + 616,2632, 624,3144, 632,3656, 656,1160, 664,1672, 672,2184, 680,2696, + 688,3208, 696,3720, 720,1224, 728,1736, 736,2248, 744,2760, 752,3272, + 760,3784, 784,1288, 792,1800, 800,2312, 808,2824, 816,3336, 824,3848, + 848,1352, 856,1864, 864,2376, 872,2888, 880,3400, 888,3912, 912,1416, + 920,1928, 928,2440, 936,2952, 944,3464, 952,3976, 976,1480, 984,1992, + 992,2504, 1000,3016, 1008,3528, 1016,4040, 1048,1552, 1056,2064, 1064,2576, + 1072,3088, 1080,3600, 1112,1616, 1120,2128, 1128,2640, 1136,3152, + 1144,3664, 1176,1680, 1184,2192, 1192,2704, 1200,3216, 1208,3728, + 1240,1744, 1248,2256, 1256,2768, 1264,3280, 1272,3792, 1304,1808, + 1312,2320, 1320,2832, 1328,3344, 1336,3856, 1368,1872, 1376,2384, + 1384,2896, 1392,3408, 1400,3920, 1432,1936, 1440,2448, 1448,2960, + 1456,3472, 1464,3984, 1496,2000, 1504,2512, 1512,3024, 1520,3536, + 1528,4048, 1568,2072, 1576,2584, 1584,3096, 1592,3608, 1632,2136, + 1640,2648, 1648,3160, 1656,3672, 1696,2200, 1704,2712, 1712,3224, + 1720,3736, 1760,2264, 1768,2776, 1776,3288, 1784,3800, 1824,2328, + 1832,2840, 1840,3352, 1848,3864, 1888,2392, 1896,2904, 1904,3416, + 1912,3928, 1952,2456, 1960,2968, 1968,3480, 1976,3992, 2016,2520, + 2024,3032, 2032,3544, 2040,4056, 2088,2592, 2096,3104, 2104,3616, + 2152,2656, 2160,3168, 2168,3680, 2216,2720, 2224,3232, 2232,3744, + 2280,2784, 2288,3296, 2296,3808, 2344,2848, 2352,3360, 2360,3872, + 2408,2912, 2416,3424, 2424,3936, 2472,2976, 2480,3488, 2488,4000, + 2536,3040, 2544,3552, 2552,4064, 2608,3112, 2616,3624, 2672,3176, + 2680,3688, 2736,3240, 2744,3752, 2800,3304, 2808,3816, 2864,3368, + 2872,3880, 2928,3432, 2936,3944, 2992,3496, 3000,4008, 3056,3560, + 3064,4072, 3128,3632, 3192,3696, 3256,3760, 3320,3824, 3384,3888, + 3448,3952, 3512,4016, 3576,4080 +}; + +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREVIDX_FLT_1024) + +const uint16_t riscvBitRevIndexTable1024[RISCVBITREVINDEXTABLE_1024_TABLE_LENGTH] = +{ + /* 8x2, size 1800 */ + 8,4096, 16,512, 24,4608, 32,1024, 40,5120, 48,1536, 56,5632, 64,2048, + 72,6144, 80,2560, 88,6656, 96,3072, 104,7168, 112,3584, 120,7680, 128,2048, + 136,4160, 144,576, 152,4672, 160,1088, 168,5184, 176,1600, 184,5696, + 192,2112, 200,6208, 208,2624, 216,6720, 224,3136, 232,7232, 240,3648, + 248,7744, 256,2048, 264,4224, 272,640, 280,4736, 288,1152, 296,5248, + 304,1664, 312,5760, 320,2176, 328,6272, 336,2688, 344,6784, 352,3200, + 360,7296, 368,3712, 376,7808, 384,2112, 392,4288, 400,704, 408,4800, + 416,1216, 424,5312, 432,1728, 440,5824, 448,2240, 456,6336, 464,2752, + 472,6848, 480,3264, 488,7360, 496,3776, 504,7872, 512,2048, 520,4352, + 528,768, 536,4864, 544,1280, 552,5376, 560,1792, 568,5888, 576,2304, + 584,6400, 592,2816, 600,6912, 608,3328, 616,7424, 624,3840, 632,7936, + 640,2176, 648,4416, 656,832, 664,4928, 672,1344, 680,5440, 688,1856, + 696,5952, 704,2368, 712,6464, 720,2880, 728,6976, 736,3392, 744,7488, + 752,3904, 760,8000, 768,2112, 776,4480, 784,896, 792,4992, 800,1408, + 808,5504, 816,1920, 824,6016, 832,2432, 840,6528, 848,2944, 856,7040, + 864,3456, 872,7552, 880,3968, 888,8064, 896,2240, 904,4544, 912,960, + 920,5056, 928,1472, 936,5568, 944,1984, 952,6080, 960,2496, 968,6592, + 976,3008, 984,7104, 992,3520, 1000,7616, 1008,4032, 1016,8128, 1024,4096, + 1032,4104, 1040,4352, 1048,4616, 1056,4104, 1064,5128, 1072,1544, + 1080,5640, 1088,2056, 1096,6152, 1104,2568, 1112,6664, 1120,3080, + 1128,7176, 1136,3592, 1144,7688, 1152,6144, 1160,4168, 1168,6400, + 1176,4680, 1184,6152, 1192,5192, 1200,1608, 1208,5704, 1216,2120, + 1224,6216, 1232,2632, 1240,6728, 1248,3144, 1256,7240, 1264,3656, + 1272,7752, 1280,4160, 1288,4232, 1296,4416, 1304,4744, 1312,4168, + 1320,5256, 1328,1672, 1336,5768, 1344,2184, 1352,6280, 1360,2696, + 1368,6792, 1376,3208, 1384,7304, 1392,3720, 1400,7816, 1408,6208, + 1416,4296, 1424,6464, 1432,4808, 1440,6216, 1448,5320, 1456,1736, + 1464,5832, 1472,2248, 1480,6344, 1488,2760, 1496,6856, 1504,3272, + 1512,7368, 1520,3784, 1528,7880, 1536,4224, 1544,4360, 1552,4480, + 1560,4872, 1568,4232, 1576,5384, 1584,1800, 1592,5896, 1600,2312, + 1608,6408, 1616,2824, 1624,6920, 1632,3336, 1640,7432, 1648,3848, + 1656,7944, 1664,6272, 1672,4424, 1680,6528, 1688,4936, 1696,6280, + 1704,5448, 1712,1864, 1720,5960, 1728,2376, 1736,6472, 1744,2888, + 1752,6984, 1760,3400, 1768,7496, 1776,3912, 1784,8008, 1792,4288, + 1800,4488, 1808,4544, 1816,5000, 1824,4296, 1832,5512, 1840,1928, + 1848,6024, 1856,2440, 1864,6536, 1872,2952, 1880,7048, 1888,3464, + 1896,7560, 1904,3976, 1912,8072, 1920,6336, 1928,4552, 1936,6592, + 1944,5064, 1952,6344, 1960,5576, 1968,1992, 1976,6088, 1984,2504, + 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6520,7856, 6528,6720, 6536,6728, 6544,6976, 6552,7008, 6560,6752, + 6568,7448, 6576,7008, 6584,7576, 6592,6736, 6600,6744, 6608,6992, + 6616,6896, 6624,6936, 6632,7408, 6640,7064, 6648,7920, 6712,7280, + 6744,6960, 6760,7472, 6768,6936, 6776,7984, 6800,6848, 6808,6856, + 6832,6880, 6840,6888, 6848,7040, 6856,7048, 6864,7104, 6872,7024, + 6880,7072, 6888,7536, 6896,7136, 6904,8048, 6952,7496, 6968,7624, + 6984,7008, 7000,7088, 7016,7600, 7024,7112, 7032,8112, 7056,7104, + 7064,7112, 7080,7512, 7088,7136, 7096,7640, 7128,7152, 7144,7664, + 7160,8176, 7176,7200, 7192,7216, 7224,7272, 7240,7264, 7256,7280, + 7288,7736, 7296,7680, 7304,7712, 7312,7936, 7320,7968, 7328,7688, + 7336,7720, 7344,7944, 7352,7976, 7360,7696, 7368,7728, 7376,7952, + 7384,7984, 7392,7704, 7400,7736, 7408,7960, 7416,7800, 7432,7456, + 7448,7472, 7480,7592, 7496,7520, 7512,7536, 7528,7976, 7544,7864, + 7552,7744, 7560,7776, 7568,8000, 7576,8032, 7584,7752, 7592,7784, + 7600,8008, 7608,8040, 7616,7760, 7624,7792, 7632,8016, 7640,8048, + 7648,7768, 7656,7800, 7664,8024, 7672,7928, 7688,7712, 7704,7728, + 7752,7776, 7768,7792, 7800,7992, 7816,7840, 7824,8064, 7832,8096, + 7856,8072, 7864,8104, 7872,8064, 7880,8072, 7888,8080, 7896,8112, + 7904,8096, 7912,8104, 7920,8088, 7928,8056, 7944,7968, 7960,7984, + 8008,8032, 8024,8048, 8056,8120, 8072,8096, 8080,8128, 8088,8160, + 8112,8136, 8120,8168, 8136,8160, 8152,8176 +}; + +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREVIDX_FLT_2048) + +const uint16_t riscvBitRevIndexTable2048[RISCVBITREVINDEXTABLE_2048_TABLE_LENGTH] = +{ + /* 8x2, size 3808 */ + 8,4096, 16,8192, 24,12288, 32,512, 40,4608, 48,8704, 56,12800, 64,1024, + 72,5120, 80,9216, 88,13312, 96,1536, 104,5632, 112,9728, 120,13824, + 128,2048, 136,6144, 144,10240, 152,14336, 160,2560, 168,6656, 176,10752, + 184,14848, 192,3072, 200,7168, 208,11264, 216,15360, 224,3584, 232,7680, + 240,11776, 248,15872, 256,1024, 264,4160, 272,8256, 280,12352, 288,576, + 296,4672, 304,8768, 312,12864, 320,1088, 328,5184, 336,9280, 344,13376, + 352,1600, 360,5696, 368,9792, 376,13888, 384,2112, 392,6208, 400,10304, + 408,14400, 416,2624, 424,6720, 432,10816, 440,14912, 448,3136, 456,7232, + 464,11328, 472,15424, 480,3648, 488,7744, 496,11840, 504,15936, 512,2048, + 520,4224, 528,8320, 536,12416, 544,640, 552,4736, 560,8832, 568,12928, + 576,1152, 584,5248, 592,9344, 600,13440, 608,1664, 616,5760, 624,9856, + 632,13952, 640,2176, 648,6272, 656,10368, 664,14464, 672,2688, 680,6784, + 688,10880, 696,14976, 704,3200, 712,7296, 720,11392, 728,15488, 736,3712, + 744,7808, 752,11904, 760,16000, 768,3072, 776,4288, 784,8384, 792,12480, + 800,3200, 808,4800, 816,8896, 824,12992, 832,1216, 840,5312, 848,9408, + 856,13504, 864,1728, 872,5824, 880,9920, 888,14016, 896,2240, 904,6336, + 912,10432, 920,14528, 928,2752, 936,6848, 944,10944, 952,15040, 960,3264, + 968,7360, 976,11456, 984,15552, 992,3776, 1000,7872, 1008,11968, 1016,16064, + 1032,4352, 1040,8448, 1048,12544, 1056,3072, 1064,4864, 1072,8960, + 1080,13056, 1088,1280, 1096,5376, 1104,9472, 1112,13568, 1120,1792, + 1128,5888, 1136,9984, 1144,14080, 1152,2304, 1160,6400, 1168,10496, + 1176,14592, 1184,2816, 1192,6912, 1200,11008, 1208,15104, 1216,3328, + 1224,7424, 1232,11520, 1240,15616, 1248,3840, 1256,7936, 1264,12032, + 1272,16128, 1288,4416, 1296,8512, 1304,12608, 1312,3328, 1320,4928, + 1328,9024, 1336,13120, 1352,5440, 1360,9536, 1368,13632, 1376,1856, + 1384,5952, 1392,10048, 1400,14144, 1408,2368, 1416,6464, 1424,10560, + 1432,14656, 1440,2880, 1448,6976, 1456,11072, 1464,15168, 1472,3392, + 1480,7488, 1488,11584, 1496,15680, 1504,3904, 1512,8000, 1520,12096, + 1528,16192, 1536,2112, 1544,4480, 1552,8576, 1560,12672, 1568,2240, + 1576,4992, 1584,9088, 1592,13184, 1600,2368, 1608,5504, 1616,9600, + 1624,13696, 1632,1920, 1640,6016, 1648,10112, 1656,14208, 1664,2432, + 1672,6528, 1680,10624, 1688,14720, 1696,2944, 1704,7040, 1712,11136, + 1720,15232, 1728,3456, 1736,7552, 1744,11648, 1752,15744, 1760,3968, + 1768,8064, 1776,12160, 1784,16256, 1792,3136, 1800,4544, 1808,8640, + 1816,12736, 1824,3264, 1832,5056, 1840,9152, 1848,13248, 1856,3392, + 1864,5568, 1872,9664, 1880,13760, 1888,1984, 1896,6080, 1904,10176, + 1912,14272, 1920,2496, 1928,6592, 1936,10688, 1944,14784, 1952,3008, + 1960,7104, 1968,11200, 1976,15296, 1984,3520, 1992,7616, 2000,11712, + 2008,15808, 2016,4032, 2024,8128, 2032,12224, 2040,16320, 2048,4096, + 2056,4104, 2064,8200, 2072,12296, 2080,4224, 2088,4616, 2096,8712, + 2104,12808, 2112,4352, 2120,5128, 2128,9224, 2136,13320, 2144,4480, + 2152,5640, 2160,9736, 2168,13832, 2176,4104, 2184,6152, 2192,10248, + 2200,14344, 2208,2568, 2216,6664, 2224,10760, 2232,14856, 2240,3080, + 2248,7176, 2256,11272, 2264,15368, 2272,3592, 2280,7688, 2288,11784, + 2296,15880, 2304,5120, 2312,4168, 2320,8264, 2328,12360, 2336,5248, + 2344,4680, 2352,8776, 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12952,14512, 12960,14384, 12968,14504, 12976,14488, + 12984,15024, 12992,14432, 13000,14560, 13008,14440, 13016,15536, + 13024,14448, 13032,14568, 13040,14744, 13048,16048, 13056,14592, + 13064,14720, 13072,14600, 13080,14728, 13088,14608, 13096,14736, + 13104,14616, 13112,14744, 13120,14656, 13128,14784, 13136,14664, + 13144,13552, 13152,14672, 13160,14800, 13168,14680, 13176,14064, + 13184,14624, 13192,14752, 13200,14632, 13208,14576, 13216,13464, + 13224,14760, 13232,15512, 13240,15088, 13248,14688, 13256,14816, + 13264,14696, 13272,15600, 13280,13720, 13288,14824, 13296,15768, + 13304,16112, 13336,13360, 13368,14616, 13376,13568, 13384,13576, + 13392,13584, 13400,13616, 13408,13600, 13416,13608, 13424,13592, + 13432,14128, 13448,13472, 13464,14640, 13480,15520, 13488,14536, + 13496,15152, 13504,13696, 13512,13536, 13520,13712, 13528,15664, + 13536,13704, 13544,15584, 13552,14792, 13560,16176, 13592,13616, + 13624,14680, 13656,13680, 13688,14192, 13704,13728, 13720,14704, + 13736,15776, 13744,15560, 13752,15216, 13768,13792, 13784,15728, + 13800,15840, 13808,15816, 13816,16240, 13824,15360, 13832,15488, + 13840,15368, 13848,15496, 13856,15376, 13864,15504, 13872,15384, + 13880,15512, 13888,15424, 13896,15552, 13904,15432, 13912,15560, + 13920,15440, 13928,15568, 13936,15448, 13944,14256, 13952,15392, + 13960,15520, 13968,15400, 13976,14768, 13984,15408, 13992,15528, + 14000,14552, 14008,15280, 14016,15456, 14024,15584, 14032,15464, + 14040,15792, 14048,15472, 14056,15592, 14064,14808, 14072,16304, + 14080,15616, 14088,15744, 14096,15624, 14104,15752, 14112,15632, + 14120,15760, 14128,15640, 14136,15768, 14144,15680, 14152,15808, + 14160,15688, 14168,15816, 14176,15696, 14184,15824, 14192,15704, + 14200,14320, 14208,15648, 14216,15776, 14224,15656, 14232,14832, + 14240,15664, 14248,15784, 14256,15576, 14264,15344, 14272,15712, + 14280,15840, 14288,15720, 14296,15856, 14304,15728, 14312,15848, + 14320,15832, 14328,16368, 14392,14488, 14400,14592, 14408,14600, + 14416,14608, 14424,14616, 14432,14624, 14440,14632, 14448,14640, + 14456,15512, 14504,14512, 14520,14904, 14528,14720, 14536,14728, + 14544,14736, 14552,15416, 14560,14752, 14568,14576, 14584,15928, + 14576,14760, 14592,15360, 14600,15368, 14608,15376, 14616,15384, + 14624,15392, 14632,15400, 14640,15408, 14648,15416, 14656,15616, + 14664,15624, 14672,15632, 14680,15640, 14688,15648, 14696,15656, + 14704,15664, 14712,15576, 14720,15488, 14728,15496, 14736,15504, + 14744,15512, 14752,15520, 14760,14768, 14776,14968, 14768,15528, + 14784,15744, 14792,15752, 14800,15760, 14808,15480, 14816,15776, + 14824,14832, 14840,15992, 14832,15784, 14856,14864, 14864,14880, + 14872,14896, 14880,14976, 14888,14992, 14896,15008, 14904,15024, + 14912,15104, 14920,15120, 14928,15136, 14936,15152, 14944,15232, + 14952,15248, 14960,15264, 14968,15280, 14984,15008, 15000,15024, + 15016,15024, 15040,15112, 15048,15128, 15056,15144, 15064,15544, + 15072,15240, 15080,15256, 15088,15272, 15096,16056, 15104,15872, + 15112,15888, 15120,15904, 15128,15920, 15136,16000, 15144,16016, + 15152,16032, 15160,16048, 15168,16128, 15176,16144, 15184,16160, + 15192,16176, 15200,16256, 15208,16272, 15216,16288, 15224,16304, + 15232,15880, 15240,15896, 15248,15912, 15256,15928, 15264,16008, + 15272,16024, 15280,16040, 15288,16056, 15296,16136, 15304,16152, + 15312,16168, 15320,15608, 15328,16264, 15336,16280, 15344,16296, + 15352,16120, 15416,15512, 15424,15616, 15432,15624, 15440,15632, + 15448,15640, 15456,15648, 15464,15656, 15472,15664, 15480,15768, + 15528,15536, 15544,16048, 15552,15744, 15560,15752, 15568,15760, + 15576,15672, 15584,15776, 15592,15600, 15600,15784, 15608,16184, + 15672,15768, 15736,15832, 15784,15792, 15800,16304, 15848,15856, + 15880,16000, 15864,16248, 15888,16000, 15896,16008, 15904,16000, + 15912,16016, 15920,16008, 15928,16024, 15936,16128, 15944,16160, + 15952,16256, 15960,16288, 15968,16136, 15976,16168, 15984,16264, + 15992,16296, 16008,16032, 16024,16040, 16064,16144, 16040,16048, + 16072,16176, 16080,16272, 16088,16304, 16096,16152, 16104,16184, + 16112,16280, 16136,16256, 16120,16312, 16144,16256, 16152,16264, + 16160,16256, 16168,16272, 16176,16264, 16184,16280, 16200,16208, + 16208,16224, 16216,16240, 16224,16320, 16232,16336, 16240,16352, + 16248,16368, 16264,16288, 16280,16296, 16296,16304, 16344,16368, + 16328,16352, 16360,16368 +}; +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREVIDX_FLT_4096) + +const uint16_t riscvBitRevIndexTable4096[RISCVBITREVINDEXTABLE_4096_TABLE_LENGTH] = +{ + /* radix 8, size 4032 */ + 8,4096, 16,8192, 24,12288, 32,16384, 40,20480, 48,24576, 56,28672, 64,512, + 72,4608, 80,8704, 88,12800, 96,16896, 104,20992, 112,25088, 120,29184, + 128,1024, 136,5120, 144,9216, 152,13312, 160,17408, 168,21504, 176,25600, + 184,29696, 192,1536, 200,5632, 208,9728, 216,13824, 224,17920, 232,22016, + 240,26112, 248,30208, 256,2048, 264,6144, 272,10240, 280,14336, 288,18432, + 296,22528, 304,26624, 312,30720, 320,2560, 328,6656, 336,10752, 344,14848, + 352,18944, 360,23040, 368,27136, 376,31232, 384,3072, 392,7168, 400,11264, + 408,15360, 416,19456, 424,23552, 432,27648, 440,31744, 448,3584, 456,7680, + 464,11776, 472,15872, 480,19968, 488,24064, 496,28160, 504,32256, 520,4160, + 528,8256, 536,12352, 544,16448, 552,20544, 560,24640, 568,28736, 584,4672, + 592,8768, 600,12864, 608,16960, 616,21056, 624,25152, 632,29248, 640,1088, + 648,5184, 656,9280, 664,13376, 672,17472, 680,21568, 688,25664, 696,29760, + 704,1600, 712,5696, 720,9792, 728,13888, 736,17984, 744,22080, 752,26176, + 760,30272, 768,2112, 776,6208, 784,10304, 792,14400, 800,18496, 808,22592, + 816,26688, 824,30784, 832,2624, 840,6720, 848,10816, 856,14912, 864,19008, + 872,23104, 880,27200, 888,31296, 896,3136, 904,7232, 912,11328, 920,15424, + 928,19520, 936,23616, 944,27712, 952,31808, 960,3648, 968,7744, 976,11840, + 984,15936, 992,20032, 1000,24128, 1008,28224, 1016,32320, 1032,4224, + 1040,8320, 1048,12416, 1056,16512, 1064,20608, 1072,24704, 1080,28800, + 1096,4736, 1104,8832, 1112,12928, 1120,17024, 1128,21120, 1136,25216, + 1144,29312, 1160,5248, 1168,9344, 1176,13440, 1184,17536, 1192,21632, + 1200,25728, 1208,29824, 1216,1664, 1224,5760, 1232,9856, 1240,13952, + 1248,18048, 1256,22144, 1264,26240, 1272,30336, 1280,2176, 1288,6272, + 1296,10368, 1304,14464, 1312,18560, 1320,22656, 1328,26752, 1336,30848, + 1344,2688, 1352,6784, 1360,10880, 1368,14976, 1376,19072, 1384,23168, + 1392,27264, 1400,31360, 1408,3200, 1416,7296, 1424,11392, 1432,15488, + 1440,19584, 1448,23680, 1456,27776, 1464,31872, 1472,3712, 1480,7808, + 1488,11904, 1496,16000, 1504,20096, 1512,24192, 1520,28288, 1528,32384, + 1544,4288, 1552,8384, 1560,12480, 1568,16576, 1576,20672, 1584,24768, + 1592,28864, 1608,4800, 1616,8896, 1624,12992, 1632,17088, 1640,21184, + 1648,25280, 1656,29376, 1672,5312, 1680,9408, 1688,13504, 1696,17600, + 1704,21696, 1712,25792, 1720,29888, 1736,5824, 1744,9920, 1752,14016, + 1760,18112, 1768,22208, 1776,26304, 1784,30400, 1792,2240, 1800,6336, + 1808,10432, 1816,14528, 1824,18624, 1832,22720, 1840,26816, 1848,30912, + 1856,2752, 1864,6848, 1872,10944, 1880,15040, 1888,19136, 1896,23232, + 1904,27328, 1912,31424, 1920,3264, 1928,7360, 1936,11456, 1944,15552, + 1952,19648, 1960,23744, 1968,27840, 1976,31936, 1984,3776, 1992,7872, + 2000,11968, 2008,16064, 2016,20160, 2024,24256, 2032,28352, 2040,32448, + 2056,4352, 2064,8448, 2072,12544, 2080,16640, 2088,20736, 2096,24832, + 2104,28928, 2120,4864, 2128,8960, 2136,13056, 2144,17152, 2152,21248, + 2160,25344, 2168,29440, 2184,5376, 2192,9472, 2200,13568, 2208,17664, + 2216,21760, 2224,25856, 2232,29952, 2248,5888, 2256,9984, 2264,14080, + 2272,18176, 2280,22272, 2288,26368, 2296,30464, 2312,6400, 2320,10496, + 2328,14592, 2336,18688, 2344,22784, 2352,26880, 2360,30976, 2368,2816, + 2376,6912, 2384,11008, 2392,15104, 2400,19200, 2408,23296, 2416,27392, + 2424,31488, 2432,3328, 2440,7424, 2448,11520, 2456,15616, 2464,19712, + 2472,23808, 2480,27904, 2488,32000, 2496,3840, 2504,7936, 2512,12032, + 2520,16128, 2528,20224, 2536,24320, 2544,28416, 2552,32512, 2568,4416, + 2576,8512, 2584,12608, 2592,16704, 2600,20800, 2608,24896, 2616,28992, + 2632,4928, 2640,9024, 2648,13120, 2656,17216, 2664,21312, 2672,25408, + 2680,29504, 2696,5440, 2704,9536, 2712,13632, 2720,17728, 2728,21824, + 2736,25920, 2744,30016, 2760,5952, 2768,10048, 2776,14144, 2784,18240, + 2792,22336, 2800,26432, 2808,30528, 2824,6464, 2832,10560, 2840,14656, + 2848,18752, 2856,22848, 2864,26944, 2872,31040, 2888,6976, 2896,11072, + 2904,15168, 2912,19264, 2920,23360, 2928,27456, 2936,31552, 2944,3392, + 2952,7488, 2960,11584, 2968,15680, 2976,19776, 2984,23872, 2992,27968, + 3000,32064, 3008,3904, 3016,8000, 3024,12096, 3032,16192, 3040,20288, + 3048,24384, 3056,28480, 3064,32576, 3080,4480, 3088,8576, 3096,12672, + 3104,16768, 3112,20864, 3120,24960, 3128,29056, 3144,4992, 3152,9088, + 3160,13184, 3168,17280, 3176,21376, 3184,25472, 3192,29568, 3208,5504, + 3216,9600, 3224,13696, 3232,17792, 3240,21888, 3248,25984, 3256,30080, + 3272,6016, 3280,10112, 3288,14208, 3296,18304, 3304,22400, 3312,26496, + 3320,30592, 3336,6528, 3344,10624, 3352,14720, 3360,18816, 3368,22912, + 3376,27008, 3384,31104, 3400,7040, 3408,11136, 3416,15232, 3424,19328, + 3432,23424, 3440,27520, 3448,31616, 3464,7552, 3472,11648, 3480,15744, + 3488,19840, 3496,23936, 3504,28032, 3512,32128, 3520,3968, 3528,8064, + 3536,12160, 3544,16256, 3552,20352, 3560,24448, 3568,28544, 3576,32640, + 3592,4544, 3600,8640, 3608,12736, 3616,16832, 3624,20928, 3632,25024, + 3640,29120, 3656,5056, 3664,9152, 3672,13248, 3680,17344, 3688,21440, + 3696,25536, 3704,29632, 3720,5568, 3728,9664, 3736,13760, 3744,17856, + 3752,21952, 3760,26048, 3768,30144, 3784,6080, 3792,10176, 3800,14272, + 3808,18368, 3816,22464, 3824,26560, 3832,30656, 3848,6592, 3856,10688, + 3864,14784, 3872,18880, 3880,22976, 3888,27072, 3896,31168, 3912,7104, + 3920,11200, 3928,15296, 3936,19392, 3944,23488, 3952,27584, 3960,31680, + 3976,7616, 3984,11712, 3992,15808, 4000,19904, 4008,24000, 4016,28096, + 4024,32192, 4040,8128, 4048,12224, 4056,16320, 4064,20416, 4072,24512, + 4080,28608, 4088,32704, 4112,8200, 4120,12296, 4128,16392, 4136,20488, + 4144,24584, 4152,28680, 4168,4616, 4176,8712, 4184,12808, 4192,16904, + 4200,21000, 4208,25096, 4216,29192, 4232,5128, 4240,9224, 4248,13320, + 4256,17416, 4264,21512, 4272,25608, 4280,29704, 4296,5640, 4304,9736, + 4312,13832, 4320,17928, 4328,22024, 4336,26120, 4344,30216, 4360,6152, + 4368,10248, 4376,14344, 4384,18440, 4392,22536, 4400,26632, 4408,30728, + 4424,6664, 4432,10760, 4440,14856, 4448,18952, 4456,23048, 4464,27144, + 4472,31240, 4488,7176, 4496,11272, 4504,15368, 4512,19464, 4520,23560, + 4528,27656, 4536,31752, 4552,7688, 4560,11784, 4568,15880, 4576,19976, + 4584,24072, 4592,28168, 4600,32264, 4624,8264, 4632,12360, 4640,16456, + 4648,20552, 4656,24648, 4664,28744, 4688,8776, 4696,12872, 4704,16968, + 4712,21064, 4720,25160, 4728,29256, 4744,5192, 4752,9288, 4760,13384, + 4768,17480, 4776,21576, 4784,25672, 4792,29768, 4808,5704, 4816,9800, + 4824,13896, 4832,17992, 4840,22088, 4848,26184, 4856,30280, 4872,6216, + 4880,10312, 4888,14408, 4896,18504, 4904,22600, 4912,26696, 4920,30792, + 4936,6728, 4944,10824, 4952,14920, 4960,19016, 4968,23112, 4976,27208, + 4984,31304, 5000,7240, 5008,11336, 5016,15432, 5024,19528, 5032,23624, + 5040,27720, 5048,31816, 5064,7752, 5072,11848, 5080,15944, 5088,20040, + 5096,24136, 5104,28232, 5112,32328, 5136,8328, 5144,12424, 5152,16520, + 5160,20616, 5168,24712, 5176,28808, 5200,8840, 5208,12936, 5216,17032, + 5224,21128, 5232,25224, 5240,29320, 5264,9352, 5272,13448, 5280,17544, + 5288,21640, 5296,25736, 5304,29832, 5320,5768, 5328,9864, 5336,13960, + 5344,18056, 5352,22152, 5360,26248, 5368,30344, 5384,6280, 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25072,28208, + 25080,32304, 25144,28784, 25208,29296, 25264,25712, 25272,29808, + 25328,26224, 25336,30320, 25392,26736, 25400,30832, 25456,27248, + 25464,31344, 25520,27760, 25528,31856, 25584,28272, 25592,32368, + 25656,28848, 25720,29360, 25784,29872, 25840,26288, 25848,30384, + 25904,26800, 25912,30896, 25968,27312, 25976,31408, 26032,27824, + 26040,31920, 26096,28336, 26104,32432, 26168,28912, 26232,29424, + 26296,29936, 26360,30448, 26416,26864, 26424,30960, 26480,27376, + 26488,31472, 26544,27888, 26552,31984, 26608,28400, 26616,32496, + 26680,28976, 26744,29488, 26808,30000, 26872,30512, 26936,31024, + 26992,27440, 27000,31536, 27056,27952, 27064,32048, 27120,28464, + 27128,32560, 27192,29040, 27256,29552, 27320,30064, 27384,30576, + 27448,31088, 27512,31600, 27568,28016, 27576,32112, 27632,28528, + 27640,32624, 27704,29104, 27768,29616, 27832,30128, 27896,30640, + 27960,31152, 28024,31664, 28088,32176, 28144,28592, 28152,32688, + 28216,29168, 28280,29680, 28344,30192, 28408,30704, 28472,31216, + 28536,31728, 28600,32240, 28664,32752, 28792,29240, 28856,29752, + 28920,30264, 28984,30776, 29048,31288, 29112,31800, 29176,32312, + 29368,29816, 29432,30328, 29496,30840, 29560,31352, 29624,31864, + 29688,32376, 29944,30392, 30008,30904, 30072,31416, 30136,31928, + 30200,32440, 30520,30968, 30584,31480, 30648,31992, 30712,32504, + 31096,31544, 31160,32056, 31224,32568, 31672,32120, 31736,32632, + 32248,32696 +}; +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREVIDX_FXT_16) + +const uint16_t riscvBitRevIndexTable_fixed_16[RISCVBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH] = +{ + /* radix 4, size 12 */ + 8,64, 16,32, 24,96, 40,80, 56,112, 88,104 +}; +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREVIDX_FXT_32) +const uint16_t riscvBitRevIndexTable_fixed_32[RISCVBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH] = +{ + /* 4x2, size 24 */ + 8,128, 16,64, 24,192, 40,160, 48,96, 56,224, 72,144, + 88,208, 104,176, 120,240, 152,200, 184,232 +}; +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREVIDX_FXT_64) +const uint16_t riscvBitRevIndexTable_fixed_64[RISCVBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH] = +{ + /* radix 4, size 56 */ + 8,256, 16,128, 24,384, 32,64, 40,320, 48,192, 56,448, 72,288, 80,160, 88,416, 104,352, + 112,224, 120,480, 136,272, 152,400, 168,336, 176,208, 184,464, 200,304, 216,432, + 232,368, 248,496, 280,392, 296,328, 312,456, 344,424, 376,488, 440,472 +}; +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREVIDX_FXT_128) +const uint16_t riscvBitRevIndexTable_fixed_128[RISCVBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH] = +{ + /* 4x2, size 112 */ + 8,512, 16,256, 24,768, 32,128, 40,640, 48,384, 56,896, 72,576, 80,320, 88,832, 96,192, + 104,704, 112,448, 120,960, 136,544, 144,288, 152,800, 168,672, 176,416, 184,928, 200,608, + 208,352, 216,864, 232,736, 240,480, 248,992, 264,528, 280,784, 296,656, 304,400, 312,912, + 328,592, 344,848, 360,720, 368,464, 376,976, 392,560, 408,816, 424,688, 440,944, 456,624, + 472,880, 488,752, 504,1008, 536,776, 552,648, 568,904, 600,840, 616,712, 632,968, + 664,808, 696,936, 728,872, 760,1000, 824,920, 888,984 +}; +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREVIDX_FXT_256) +const uint16_t riscvBitRevIndexTable_fixed_256[RISCVBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH] = +{ + /* radix 4, size 240 */ + 8,1024, 16,512, 24,1536, 32,256, 40,1280, 48,768, 56,1792, 64,128, 72,1152, 80,640, + 88,1664, 96,384, 104,1408, 112,896, 120,1920, 136,1088, 144,576, 152,1600, 160,320, + 168,1344, 176,832, 184,1856, 200,1216, 208,704, 216,1728, 224,448, 232,1472, 240,960, + 248,1984, 264,1056, 272,544, 280,1568, 296,1312, 304,800, 312,1824, 328,1184, 336,672, + 344,1696, 352,416, 360,1440, 368,928, 376,1952, 392,1120, 400,608, 408,1632, 424,1376, + 432,864, 440,1888, 456,1248, 464,736, 472,1760, 488,1504, 496,992, 504,2016, 520,1040, + 536,1552, 552,1296, 560,784, 568,1808, 584,1168, 592,656, 600,1680, 616,1424, 624,912, + 632,1936, 648,1104, 664,1616, 680,1360, 688,848, 696,1872, 712,1232, 728,1744, 744,1488, + 752,976, 760,2000, 776,1072, 792,1584, 808,1328, 824,1840, 840,1200, 856,1712, 872,1456, + 880,944, 888,1968, 904,1136, 920,1648, 936,1392, 952,1904, 968,1264, 984,1776, 1000,1520, + 1016,2032, 1048,1544, 1064,1288, 1080,1800, 1096,1160, 1112,1672, 1128,1416, 1144,1928, + 1176,1608, 1192,1352, 1208,1864, 1240,1736, 1256,1480, 1272,1992, 1304,1576, 1336,1832, + 1368,1704, 1384,1448, 1400,1960, 1432,1640, 1464,1896, 1496,1768, 1528,2024, 1592,1816, + 1624,1688, 1656,1944, 1720,1880, 1784,2008, 1912,1976 +}; +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREVIDX_FXT_512) +const uint16_t riscvBitRevIndexTable_fixed_512[RISCVBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH] = +{ + /* 4x2, size 480 */ + 8,2048, 16,1024, 24,3072, 32,512, 40,2560, 48,1536, 56,3584, 64,256, 72,2304, 80,1280, + 88,3328, 96,768, 104,2816, 112,1792, 120,3840, 136,2176, 144,1152, 152,3200, 160,640, + 168,2688, 176,1664, 184,3712, 192,384, 200,2432, 208,1408, 216,3456, 224,896, 232,2944, + 240,1920, 248,3968, 264,2112, 272,1088, 280,3136, 288,576, 296,2624, 304,1600, 312,3648, + 328,2368, 336,1344, 344,3392, 352,832, 360,2880, 368,1856, 376,3904, 392,2240, 400,1216, + 408,3264, 416,704, 424,2752, 432,1728, 440,3776, 456,2496, 464,1472, 472,3520, 480,960, + 488,3008, 496,1984, 504,4032, 520,2080, 528,1056, 536,3104, 552,2592, 560,1568, 568,3616, + 584,2336, 592,1312, 600,3360, 608,800, 616,2848, 624,1824, 632,3872, 648,2208, 656,1184, + 664,3232, 680,2720, 688,1696, 696,3744, 712,2464, 720,1440, 728,3488, 736,928, 744,2976, + 752,1952, 760,4000, 776,2144, 784,1120, 792,3168, 808,2656, 816,1632, 824,3680, 840,2400, + 848,1376, 856,3424, 872,2912, 880,1888, 888,3936, 904,2272, 912,1248, 920,3296, 936,2784, + 944,1760, 952,3808, 968,2528, 976,1504, 984,3552, 1000,3040, 1008,2016, 1016,4064, + 1032,2064, 1048,3088, 1064,2576, 1072,1552, 1080,3600, 1096,2320, 1104,1296, 1112,3344, + 1128,2832, 1136,1808, 1144,3856, 1160,2192, 1176,3216, 1192,2704, 1200,1680, 1208,3728, + 1224,2448, 1232,1424, 1240,3472, 1256,2960, 1264,1936, 1272,3984, 1288,2128, 1304,3152, + 1320,2640, 1328,1616, 1336,3664, 1352,2384, 1368,3408, 1384,2896, 1392,1872, 1400,3920, + 1416,2256, 1432,3280, 1448,2768, 1456,1744, 1464,3792, 1480,2512, 1496,3536, 1512,3024, + 1520,2000, 1528,4048, 1544,2096, 1560,3120, 1576,2608, 1592,3632, 1608,2352, 1624,3376, + 1640,2864, 1648,1840, 1656,3888, 1672,2224, 1688,3248, 1704,2736, 1720,3760, 1736,2480, + 1752,3504, 1768,2992, 1776,1968, 1784,4016, 1800,2160, 1816,3184, 1832,2672, 1848,3696, + 1864,2416, 1880,3440, 1896,2928, 1912,3952, 1928,2288, 1944,3312, 1960,2800, 1976,3824, + 1992,2544, 2008,3568, 2024,3056, 2040,4080, 2072,3080, 2088,2568, 2104,3592, 2120,2312, + 2136,3336, 2152,2824, 2168,3848, 2200,3208, 2216,2696, 2232,3720, 2248,2440, 2264,3464, + 2280,2952, 2296,3976, 2328,3144, 2344,2632, 2360,3656, 2392,3400, 2408,2888, 2424,3912, + 2456,3272, 2472,2760, 2488,3784, 2520,3528, 2536,3016, 2552,4040, 2584,3112, 2616,3624, + 2648,3368, 2664,2856, 2680,3880, 2712,3240, 2744,3752, 2776,3496, 2792,2984, 2808,4008, + 2840,3176, 2872,3688, 2904,3432, 2936,3944, 2968,3304, 3000,3816, 3032,3560, 3064,4072, + 3128,3608, 3160,3352, 3192,3864, 3256,3736, 3288,3480, 3320,3992, 3384,3672, 3448,3928, + 3512,3800, 3576,4056, 3704,3896, 3832,4024 +}; +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREVIDX_FXT_1024) +const uint16_t riscvBitRevIndexTable_fixed_1024[RISCVBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH] = +{ + /* radix 4, size 992 */ + 8,4096, 16,2048, 24,6144, 32,1024, 40,5120, 48,3072, 56,7168, 64,512, 72,4608, + 80,2560, 88,6656, 96,1536, 104,5632, 112,3584, 120,7680, 128,256, 136,4352, + 144,2304, 152,6400, 160,1280, 168,5376, 176,3328, 184,7424, 192,768, 200,4864, + 208,2816, 216,6912, 224,1792, 232,5888, 240,3840, 248,7936, 264,4224, 272,2176, + 280,6272, 288,1152, 296,5248, 304,3200, 312,7296, 320,640, 328,4736, 336,2688, + 344,6784, 352,1664, 360,5760, 368,3712, 376,7808, 392,4480, 400,2432, 408,6528, + 416,1408, 424,5504, 432,3456, 440,7552, 448,896, 456,4992, 464,2944, 472,7040, + 480,1920, 488,6016, 496,3968, 504,8064, 520,4160, 528,2112, 536,6208, 544,1088, + 552,5184, 560,3136, 568,7232, 584,4672, 592,2624, 600,6720, 608,1600, 616,5696, + 624,3648, 632,7744, 648,4416, 656,2368, 664,6464, 672,1344, 680,5440, 688,3392, + 696,7488, 704,832, 712,4928, 720,2880, 728,6976, 736,1856, 744,5952, 752,3904, + 760,8000, 776,4288, 784,2240, 792,6336, 800,1216, 808,5312, 816,3264, 824,7360, + 840,4800, 848,2752, 856,6848, 864,1728, 872,5824, 880,3776, 888,7872, 904,4544, + 912,2496, 920,6592, 928,1472, 936,5568, 944,3520, 952,7616, 968,5056, 976,3008, + 984,7104, 992,1984, 1000,6080, 1008,4032, 1016,8128, 1032,4128, 1040,2080, + 1048,6176, 1064,5152, 1072,3104, 1080,7200, 1096,4640, 1104,2592, 1112,6688, + 1120,1568, 1128,5664, 1136,3616, 1144,7712, 1160,4384, 1168,2336, 1176,6432, + 1184,1312, 1192,5408, 1200,3360, 1208,7456, 1224,4896, 1232,2848, 1240,6944, + 1248,1824, 1256,5920, 1264,3872, 1272,7968, 1288,4256, 1296,2208, 1304,6304, + 1320,5280, 1328,3232, 1336,7328, 1352,4768, 1360,2720, 1368,6816, 1376,1696, + 1384,5792, 1392,3744, 1400,7840, 1416,4512, 1424,2464, 1432,6560, 1448,5536, + 1456,3488, 1464,7584, 1480,5024, 1488,2976, 1496,7072, 1504,1952, 1512,6048, + 1520,4000, 1528,8096, 1544,4192, 1552,2144, 1560,6240, 1576,5216, 1584,3168, + 1592,7264, 1608,4704, 1616,2656, 1624,6752, 1640,5728, 1648,3680, 1656,7776, + 1672,4448, 1680,2400, 1688,6496, 1704,5472, 1712,3424, 1720,7520, 1736,4960, + 1744,2912, 1752,7008, 1760,1888, 1768,5984, 1776,3936, 1784,8032, 1800,4320, + 1808,2272, 1816,6368, 1832,5344, 1840,3296, 1848,7392, 1864,4832, 1872,2784, + 1880,6880, 1896,5856, 1904,3808, 1912,7904, 1928,4576, 1936,2528, 1944,6624, + 1960,5600, 1968,3552, 1976,7648, 1992,5088, 2000,3040, 2008,7136, 2024,6112, + 2032,4064, 2040,8160, 2056,4112, 2072,6160, 2088,5136, 2096,3088, 2104,7184, + 2120,4624, 2128,2576, 2136,6672, 2152,5648, 2160,3600, 2168,7696, 2184,4368, + 2192,2320, 2200,6416, 2216,5392, 2224,3344, 2232,7440, 2248,4880, 2256,2832, + 2264,6928, 2280,5904, 2288,3856, 2296,7952, 2312,4240, 2328,6288, 2344,5264, + 2352,3216, 2360,7312, 2376,4752, 2384,2704, 2392,6800, 2408,5776, 2416,3728, + 2424,7824, 2440,4496, 2456,6544, 2472,5520, 2480,3472, 2488,7568, 2504,5008, + 2512,2960, 2520,7056, 2536,6032, 2544,3984, 2552,8080, 2568,4176, 2584,6224, + 2600,5200, 2608,3152, 2616,7248, 2632,4688, 2648,6736, 2664,5712, 2672,3664, + 2680,7760, 2696,4432, 2712,6480, 2728,5456, 2736,3408, 2744,7504, 2760,4944, + 2768,2896, 2776,6992, 2792,5968, 2800,3920, 2808,8016, 2824,4304, 2840,6352, + 2856,5328, 2864,3280, 2872,7376, 2888,4816, 2904,6864, 2920,5840, 2928,3792, + 2936,7888, 2952,4560, 2968,6608, 2984,5584, 2992,3536, 3000,7632, 3016,5072, + 3032,7120, 3048,6096, 3056,4048, 3064,8144, 3080,4144, 3096,6192, 3112,5168, + 3128,7216, 3144,4656, 3160,6704, 3176,5680, 3184,3632, 3192,7728, 3208,4400, + 3224,6448, 3240,5424, 3248,3376, 3256,7472, 3272,4912, 3288,6960, 3304,5936, + 3312,3888, 3320,7984, 3336,4272, 3352,6320, 3368,5296, 3384,7344, 3400,4784, + 3416,6832, 3432,5808, 3440,3760, 3448,7856, 3464,4528, 3480,6576, 3496,5552, + 3512,7600, 3528,5040, 3544,7088, 3560,6064, 3568,4016, 3576,8112, 3592,4208, + 3608,6256, 3624,5232, 3640,7280, 3656,4720, 3672,6768, 3688,5744, 3704,7792, + 3720,4464, 3736,6512, 3752,5488, 3768,7536, 3784,4976, 3800,7024, 3816,6000, + 3824,3952, 3832,8048, 3848,4336, 3864,6384, 3880,5360, 3896,7408, 3912,4848, + 3928,6896, 3944,5872, 3960,7920, 3976,4592, 3992,6640, 4008,5616, 4024,7664, + 4040,5104, 4056,7152, 4072,6128, 4088,8176, 4120,6152, 4136,5128, 4152,7176, + 4168,4616, 4184,6664, 4200,5640, 4216,7688, 4232,4360, 4248,6408, 4264,5384, + 4280,7432, 4296,4872, 4312,6920, 4328,5896, 4344,7944, 4376,6280, 4392,5256, + 4408,7304, 4424,4744, 4440,6792, 4456,5768, 4472,7816, 4504,6536, 4520,5512, + 4536,7560, 4552,5000, 4568,7048, 4584,6024, 4600,8072, 4632,6216, 4648,5192, + 4664,7240, 4696,6728, 4712,5704, 4728,7752, 4760,6472, 4776,5448, 4792,7496, + 4808,4936, 4824,6984, 4840,5960, 4856,8008, 4888,6344, 4904,5320, 4920,7368, + 4952,6856, 4968,5832, 4984,7880, 5016,6600, 5032,5576, 5048,7624, 5080,7112, + 5096,6088, 5112,8136, 5144,6184, 5176,7208, 5208,6696, 5224,5672, 5240,7720, + 5272,6440, 5288,5416, 5304,7464, 5336,6952, 5352,5928, 5368,7976, 5400,6312, + 5432,7336, 5464,6824, 5480,5800, 5496,7848, 5528,6568, 5560,7592, 5592,7080, + 5608,6056, 5624,8104, 5656,6248, 5688,7272, 5720,6760, 5752,7784, 5784,6504, + 5816,7528, 5848,7016, 5864,5992, 5880,8040, 5912,6376, 5944,7400, 5976,6888, + 6008,7912, 6040,6632, 6072,7656, 6104,7144, 6136,8168, 6200,7192, 6232,6680, + 6264,7704, 6296,6424, 6328,7448, 6360,6936, 6392,7960, 6456,7320, 6488,6808, + 6520,7832, 6584,7576, 6616,7064, 6648,8088, 6712,7256, 6776,7768, 6840,7512, + 6872,7000, 6904,8024, 6968,7384, 7032,7896, 7096,7640, 7160,8152, 7288,7736, + 7352,7480, 7416,7992, 7544,7864, 7672,8120, 7928,8056 +}; +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREVIDX_FXT_2048) +const uint16_t riscvBitRevIndexTable_fixed_2048[RISCVBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH] = +{ + /* 4x2, size 1984 */ + 8,8192, 16,4096, 24,12288, 32,2048, 40,10240, 48,6144, 56,14336, 64,1024, + 72,9216, 80,5120, 88,13312, 96,3072, 104,11264, 112,7168, 120,15360, 128,512, + 136,8704, 144,4608, 152,12800, 160,2560, 168,10752, 176,6656, 184,14848, + 192,1536, 200,9728, 208,5632, 216,13824, 224,3584, 232,11776, 240,7680, + 248,15872, 264,8448, 272,4352, 280,12544, 288,2304, 296,10496, 304,6400, + 312,14592, 320,1280, 328,9472, 336,5376, 344,13568, 352,3328, 360,11520, + 368,7424, 376,15616, 384,768, 392,8960, 400,4864, 408,13056, 416,2816, + 424,11008, 432,6912, 440,15104, 448,1792, 456,9984, 464,5888, 472,14080, + 480,3840, 488,12032, 496,7936, 504,16128, 520,8320, 528,4224, 536,12416, + 544,2176, 552,10368, 560,6272, 568,14464, 576,1152, 584,9344, 592,5248, + 600,13440, 608,3200, 616,11392, 624,7296, 632,15488, 648,8832, 656,4736, + 664,12928, 672,2688, 680,10880, 688,6784, 696,14976, 704,1664, 712,9856, + 720,5760, 728,13952, 736,3712, 744,11904, 752,7808, 760,16000, 776,8576, + 784,4480, 792,12672, 800,2432, 808,10624, 816,6528, 824,14720, 832,1408, + 840,9600, 848,5504, 856,13696, 864,3456, 872,11648, 880,7552, 888,15744, + 904,9088, 912,4992, 920,13184, 928,2944, 936,11136, 944,7040, 952,15232, + 960,1920, 968,10112, 976,6016, 984,14208, 992,3968, 1000,12160, 1008,8064, + 1016,16256, 1032,8256, 1040,4160, 1048,12352, 1056,2112, 1064,10304, 1072,6208, + 1080,14400, 1096,9280, 1104,5184, 1112,13376, 1120,3136, 1128,11328, 1136,7232, + 1144,15424, 1160,8768, 1168,4672, 1176,12864, 1184,2624, 1192,10816, 1200,6720, + 1208,14912, 1216,1600, 1224,9792, 1232,5696, 1240,13888, 1248,3648, 1256,11840, + 1264,7744, 1272,15936, 1288,8512, 1296,4416, 1304,12608, 1312,2368, 1320,10560, + 1328,6464, 1336,14656, 1352,9536, 1360,5440, 1368,13632, 1376,3392, 1384,11584, + 1392,7488, 1400,15680, 1416,9024, 1424,4928, 1432,13120, 1440,2880, 1448,11072, + 1456,6976, 1464,15168, 1472,1856, 1480,10048, 1488,5952, 1496,14144, 1504,3904, + 1512,12096, 1520,8000, 1528,16192, 1544,8384, 1552,4288, 1560,12480, 1568,2240, + 1576,10432, 1584,6336, 1592,14528, 1608,9408, 1616,5312, 1624,13504, 1632,3264, + 1640,11456, 1648,7360, 1656,15552, 1672,8896, 1680,4800, 1688,12992, 1696,2752, + 1704,10944, 1712,6848, 1720,15040, 1736,9920, 1744,5824, 1752,14016, 1760,3776, + 1768,11968, 1776,7872, 1784,16064, 1800,8640, 1808,4544, 1816,12736, 1824,2496, + 1832,10688, 1840,6592, 1848,14784, 1864,9664, 1872,5568, 1880,13760, 1888,3520, + 1896,11712, 1904,7616, 1912,15808, 1928,9152, 1936,5056, 1944,13248, 1952,3008, + 1960,11200, 1968,7104, 1976,15296, 1992,10176, 2000,6080, 2008,14272, 2016,4032, + 2024,12224, 2032,8128, 2040,16320, 2056,8224, 2064,4128, 2072,12320, 2088,10272, + 2096,6176, 2104,14368, 2120,9248, 2128,5152, 2136,13344, 2144,3104, 2152,11296, + 2160,7200, 2168,15392, 2184,8736, 2192,4640, 2200,12832, 2208,2592, 2216,10784, + 2224,6688, 2232,14880, 2248,9760, 2256,5664, 2264,13856, 2272,3616, 2280,11808, + 2288,7712, 2296,15904, 2312,8480, 2320,4384, 2328,12576, 2344,10528, 2352,6432, + 2360,14624, 2376,9504, 2384,5408, 2392,13600, 2400,3360, 2408,11552, 2416,7456, + 2424,15648, 2440,8992, 2448,4896, 2456,13088, 2464,2848, 2472,11040, 2480,6944, + 2488,15136, 2504,10016, 2512,5920, 2520,14112, 2528,3872, 2536,12064, 2544,7968, + 2552,16160, 2568,8352, 2576,4256, 2584,12448, 2600,10400, 2608,6304, 2616,14496, + 2632,9376, 2640,5280, 2648,13472, 2656,3232, 2664,11424, 2672,7328, 2680,15520, + 2696,8864, 2704,4768, 2712,12960, 2728,10912, 2736,6816, 2744,15008, 2760,9888, + 2768,5792, 2776,13984, 2784,3744, 2792,11936, 2800,7840, 2808,16032, 2824,8608, + 2832,4512, 2840,12704, 2856,10656, 2864,6560, 2872,14752, 2888,9632, 2896,5536, + 2904,13728, 2912,3488, 2920,11680, 2928,7584, 2936,15776, 2952,9120, 2960,5024, + 2968,13216, 2984,11168, 2992,7072, 3000,15264, 3016,10144, 3024,6048, + 3032,14240, 3040,4000, 3048,12192, 3056,8096, 3064,16288, 3080,8288, 3088,4192, + 3096,12384, 3112,10336, 3120,6240, 3128,14432, 3144,9312, 3152,5216, 3160,13408, + 3176,11360, 3184,7264, 3192,15456, 3208,8800, 3216,4704, 3224,12896, 3240,10848, + 3248,6752, 3256,14944, 3272,9824, 3280,5728, 3288,13920, 3296,3680, 3304,11872, + 3312,7776, 3320,15968, 3336,8544, 3344,4448, 3352,12640, 3368,10592, 3376,6496, + 3384,14688, 3400,9568, 3408,5472, 3416,13664, 3432,11616, 3440,7520, 3448,15712, + 3464,9056, 3472,4960, 3480,13152, 3496,11104, 3504,7008, 3512,15200, 3528,10080, + 3536,5984, 3544,14176, 3552,3936, 3560,12128, 3568,8032, 3576,16224, 3592,8416, + 3600,4320, 3608,12512, 3624,10464, 3632,6368, 3640,14560, 3656,9440, 3664,5344, + 3672,13536, 3688,11488, 3696,7392, 3704,15584, 3720,8928, 3728,4832, 3736,13024, + 3752,10976, 3760,6880, 3768,15072, 3784,9952, 3792,5856, 3800,14048, 3816,12000, + 3824,7904, 3832,16096, 3848,8672, 3856,4576, 3864,12768, 3880,10720, 3888,6624, + 3896,14816, 3912,9696, 3920,5600, 3928,13792, 3944,11744, 3952,7648, 3960,15840, + 3976,9184, 3984,5088, 3992,13280, 4008,11232, 4016,7136, 4024,15328, 4040,10208, + 4048,6112, 4056,14304, 4072,12256, 4080,8160, 4088,16352, 4104,8208, 4120,12304, + 4136,10256, 4144,6160, 4152,14352, 4168,9232, 4176,5136, 4184,13328, 4200,11280, + 4208,7184, 4216,15376, 4232,8720, 4240,4624, 4248,12816, 4264,10768, 4272,6672, + 4280,14864, 4296,9744, 4304,5648, 4312,13840, 4328,11792, 4336,7696, 4344,15888, + 4360,8464, 4376,12560, 4392,10512, 4400,6416, 4408,14608, 4424,9488, 4432,5392, + 4440,13584, 4456,11536, 4464,7440, 4472,15632, 4488,8976, 4496,4880, 4504,13072, + 4520,11024, 4528,6928, 4536,15120, 4552,10000, 4560,5904, 4568,14096, + 4584,12048, 4592,7952, 4600,16144, 4616,8336, 4632,12432, 4648,10384, 4656,6288, + 4664,14480, 4680,9360, 4688,5264, 4696,13456, 4712,11408, 4720,7312, 4728,15504, + 4744,8848, 4760,12944, 4776,10896, 4784,6800, 4792,14992, 4808,9872, 4816,5776, + 4824,13968, 4840,11920, 4848,7824, 4856,16016, 4872,8592, 4888,12688, + 4904,10640, 4912,6544, 4920,14736, 4936,9616, 4944,5520, 4952,13712, 4968,11664, + 4976,7568, 4984,15760, 5000,9104, 5016,13200, 5032,11152, 5040,7056, 5048,15248, + 5064,10128, 5072,6032, 5080,14224, 5096,12176, 5104,8080, 5112,16272, 5128,8272, + 5144,12368, 5160,10320, 5168,6224, 5176,14416, 5192,9296, 5208,13392, + 5224,11344, 5232,7248, 5240,15440, 5256,8784, 5272,12880, 5288,10832, 5296,6736, + 5304,14928, 5320,9808, 5328,5712, 5336,13904, 5352,11856, 5360,7760, 5368,15952, + 5384,8528, 5400,12624, 5416,10576, 5424,6480, 5432,14672, 5448,9552, 5464,13648, + 5480,11600, 5488,7504, 5496,15696, 5512,9040, 5528,13136, 5544,11088, 5552,6992, + 5560,15184, 5576,10064, 5584,5968, 5592,14160, 5608,12112, 5616,8016, + 5624,16208, 5640,8400, 5656,12496, 5672,10448, 5680,6352, 5688,14544, 5704,9424, + 5720,13520, 5736,11472, 5744,7376, 5752,15568, 5768,8912, 5784,13008, + 5800,10960, 5808,6864, 5816,15056, 5832,9936, 5848,14032, 5864,11984, 5872,7888, + 5880,16080, 5896,8656, 5912,12752, 5928,10704, 5936,6608, 5944,14800, 5960,9680, + 5976,13776, 5992,11728, 6000,7632, 6008,15824, 6024,9168, 6040,13264, + 6056,11216, 6064,7120, 6072,15312, 6088,10192, 6104,14288, 6120,12240, + 6128,8144, 6136,16336, 6152,8240, 6168,12336, 6184,10288, 6200,14384, 6216,9264, + 6232,13360, 6248,11312, 6256,7216, 6264,15408, 6280,8752, 6296,12848, + 6312,10800, 6320,6704, 6328,14896, 6344,9776, 6360,13872, 6376,11824, 6384,7728, + 6392,15920, 6408,8496, 6424,12592, 6440,10544, 6456,14640, 6472,9520, + 6488,13616, 6504,11568, 6512,7472, 6520,15664, 6536,9008, 6552,13104, + 6568,11056, 6576,6960, 6584,15152, 6600,10032, 6616,14128, 6632,12080, + 6640,7984, 6648,16176, 6664,8368, 6680,12464, 6696,10416, 6712,14512, 6728,9392, + 6744,13488, 6760,11440, 6768,7344, 6776,15536, 6792,8880, 6808,12976, + 6824,10928, 6840,15024, 6856,9904, 6872,14000, 6888,11952, 6896,7856, + 6904,16048, 6920,8624, 6936,12720, 6952,10672, 6968,14768, 6984,9648, + 7000,13744, 7016,11696, 7024,7600, 7032,15792, 7048,9136, 7064,13232, + 7080,11184, 7096,15280, 7112,10160, 7128,14256, 7144,12208, 7152,8112, + 7160,16304, 7176,8304, 7192,12400, 7208,10352, 7224,14448, 7240,9328, + 7256,13424, 7272,11376, 7288,15472, 7304,8816, 7320,12912, 7336,10864, + 7352,14960, 7368,9840, 7384,13936, 7400,11888, 7408,7792, 7416,15984, 7432,8560, + 7448,12656, 7464,10608, 7480,14704, 7496,9584, 7512,13680, 7528,11632, + 7544,15728, 7560,9072, 7576,13168, 7592,11120, 7608,15216, 7624,10096, + 7640,14192, 7656,12144, 7664,8048, 7672,16240, 7688,8432, 7704,12528, + 7720,10480, 7736,14576, 7752,9456, 7768,13552, 7784,11504, 7800,15600, + 7816,8944, 7832,13040, 7848,10992, 7864,15088, 7880,9968, 7896,14064, + 7912,12016, 7928,16112, 7944,8688, 7960,12784, 7976,10736, 7992,14832, + 8008,9712, 8024,13808, 8040,11760, 8056,15856, 8072,9200, 8088,13296, + 8104,11248, 8120,15344, 8136,10224, 8152,14320, 8168,12272, 8184,16368, + 8216,12296, 8232,10248, 8248,14344, 8264,9224, 8280,13320, 8296,11272, + 8312,15368, 8328,8712, 8344,12808, 8360,10760, 8376,14856, 8392,9736, + 8408,13832, 8424,11784, 8440,15880, 8472,12552, 8488,10504, 8504,14600, + 8520,9480, 8536,13576, 8552,11528, 8568,15624, 8584,8968, 8600,13064, + 8616,11016, 8632,15112, 8648,9992, 8664,14088, 8680,12040, 8696,16136, + 8728,12424, 8744,10376, 8760,14472, 8776,9352, 8792,13448, 8808,11400, + 8824,15496, 8856,12936, 8872,10888, 8888,14984, 8904,9864, 8920,13960, + 8936,11912, 8952,16008, 8984,12680, 9000,10632, 9016,14728, 9032,9608, + 9048,13704, 9064,11656, 9080,15752, 9112,13192, 9128,11144, 9144,15240, + 9160,10120, 9176,14216, 9192,12168, 9208,16264, 9240,12360, 9256,10312, + 9272,14408, 9304,13384, 9320,11336, 9336,15432, 9368,12872, 9384,10824, + 9400,14920, 9416,9800, 9432,13896, 9448,11848, 9464,15944, 9496,12616, + 9512,10568, 9528,14664, 9560,13640, 9576,11592, 9592,15688, 9624,13128, + 9640,11080, 9656,15176, 9672,10056, 9688,14152, 9704,12104, 9720,16200, + 9752,12488, 9768,10440, 9784,14536, 9816,13512, 9832,11464, 9848,15560, + 9880,13000, 9896,10952, 9912,15048, 9944,14024, 9960,11976, 9976,16072, + 10008,12744, 10024,10696, 10040,14792, 10072,13768, 10088,11720, 10104,15816, + 10136,13256, 10152,11208, 10168,15304, 10200,14280, 10216,12232, 10232,16328, + 10264,12328, 10296,14376, 10328,13352, 10344,11304, 10360,15400, 10392,12840, + 10408,10792, 10424,14888, 10456,13864, 10472,11816, 10488,15912, 10520,12584, + 10552,14632, 10584,13608, 10600,11560, 10616,15656, 10648,13096, 10664,11048, + 10680,15144, 10712,14120, 10728,12072, 10744,16168, 10776,12456, 10808,14504, + 10840,13480, 10856,11432, 10872,15528, 10904,12968, 10936,15016, 10968,13992, + 10984,11944, 11000,16040, 11032,12712, 11064,14760, 11096,13736, 11112,11688, + 11128,15784, 11160,13224, 11192,15272, 11224,14248, 11240,12200, 11256,16296, + 11288,12392, 11320,14440, 11352,13416, 11384,15464, 11416,12904, 11448,14952, + 11480,13928, 11496,11880, 11512,15976, 11544,12648, 11576,14696, 11608,13672, + 11640,15720, 11672,13160, 11704,15208, 11736,14184, 11752,12136, 11768,16232, + 11800,12520, 11832,14568, 11864,13544, 11896,15592, 11928,13032, 11960,15080, + 11992,14056, 12024,16104, 12056,12776, 12088,14824, 12120,13800, 12152,15848, + 12184,13288, 12216,15336, 12248,14312, 12280,16360, 12344,14360, 12376,13336, + 12408,15384, 12440,12824, 12472,14872, 12504,13848, 12536,15896, 12600,14616, + 12632,13592, 12664,15640, 12696,13080, 12728,15128, 12760,14104, 12792,16152, + 12856,14488, 12888,13464, 12920,15512, 12984,15000, 13016,13976, 13048,16024, + 13112,14744, 13144,13720, 13176,15768, 13240,15256, 13272,14232, 13304,16280, + 13368,14424, 13432,15448, 13496,14936, 13528,13912, 13560,15960, 13624,14680, + 13688,15704, 13752,15192, 13784,14168, 13816,16216, 13880,14552, 13944,15576, + 14008,15064, 14072,16088, 14136,14808, 14200,15832, 14264,15320, 14328,16344, + 14456,15416, 14520,14904, 14584,15928, 14712,15672, 14776,15160, 14840,16184, + 14968,15544, 15096,16056, 15224,15800, 15352,16312, 15608,15992, 15864,16248 +}; +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREVIDX_FXT_4096) +const uint16_t riscvBitRevIndexTable_fixed_4096[RISCVBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH] = +{ + /* radix 4, size 4032 */ + 8,16384, 16,8192, 24,24576, 32,4096, 40,20480, 48,12288, 56,28672, 64,2048, + 72,18432, 80,10240, 88,26624, 96,6144, 104,22528, 112,14336, 120,30720, + 128,1024, 136,17408, 144,9216, 152,25600, 160,5120, 168,21504, 176,13312, + 184,29696, 192,3072, 200,19456, 208,11264, 216,27648, 224,7168, 232,23552, + 240,15360, 248,31744, 256,512, 264,16896, 272,8704, 280,25088, 288,4608, + 296,20992, 304,12800, 312,29184, 320,2560, 328,18944, 336,10752, 344,27136, + 352,6656, 360,23040, 368,14848, 376,31232, 384,1536, 392,17920, 400,9728, + 408,26112, 416,5632, 424,22016, 432,13824, 440,30208, 448,3584, 456,19968, + 464,11776, 472,28160, 480,7680, 488,24064, 496,15872, 504,32256, 520,16640, + 528,8448, 536,24832, 544,4352, 552,20736, 560,12544, 568,28928, 576,2304, + 584,18688, 592,10496, 600,26880, 608,6400, 616,22784, 624,14592, 632,30976, + 640,1280, 648,17664, 656,9472, 664,25856, 672,5376, 680,21760, 688,13568, + 696,29952, 704,3328, 712,19712, 720,11520, 728,27904, 736,7424, 744,23808, + 752,15616, 760,32000, 776,17152, 784,8960, 792,25344, 800,4864, 808,21248, + 816,13056, 824,29440, 832,2816, 840,19200, 848,11008, 856,27392, 864,6912, + 872,23296, 880,15104, 888,31488, 896,1792, 904,18176, 912,9984, 920,26368, + 928,5888, 936,22272, 944,14080, 952,30464, 960,3840, 968,20224, 976,12032, + 984,28416, 992,7936, 1000,24320, 1008,16128, 1016,32512, 1032,16512, 1040,8320, + 1048,24704, 1056,4224, 1064,20608, 1072,12416, 1080,28800, 1088,2176, + 1096,18560, 1104,10368, 1112,26752, 1120,6272, 1128,22656, 1136,14464, + 1144,30848, 1160,17536, 1168,9344, 1176,25728, 1184,5248, 1192,21632, + 1200,13440, 1208,29824, 1216,3200, 1224,19584, 1232,11392, 1240,27776, + 1248,7296, 1256,23680, 1264,15488, 1272,31872, 1288,17024, 1296,8832, + 1304,25216, 1312,4736, 1320,21120, 1328,12928, 1336,29312, 1344,2688, + 1352,19072, 1360,10880, 1368,27264, 1376,6784, 1384,23168, 1392,14976, + 1400,31360, 1408,1664, 1416,18048, 1424,9856, 1432,26240, 1440,5760, 1448,22144, + 1456,13952, 1464,30336, 1472,3712, 1480,20096, 1488,11904, 1496,28288, + 1504,7808, 1512,24192, 1520,16000, 1528,32384, 1544,16768, 1552,8576, + 1560,24960, 1568,4480, 1576,20864, 1584,12672, 1592,29056, 1600,2432, + 1608,18816, 1616,10624, 1624,27008, 1632,6528, 1640,22912, 1648,14720, + 1656,31104, 1672,17792, 1680,9600, 1688,25984, 1696,5504, 1704,21888, + 1712,13696, 1720,30080, 1728,3456, 1736,19840, 1744,11648, 1752,28032, + 1760,7552, 1768,23936, 1776,15744, 1784,32128, 1800,17280, 1808,9088, + 1816,25472, 1824,4992, 1832,21376, 1840,13184, 1848,29568, 1856,2944, + 1864,19328, 1872,11136, 1880,27520, 1888,7040, 1896,23424, 1904,15232, + 1912,31616, 1928,18304, 1936,10112, 1944,26496, 1952,6016, 1960,22400, + 1968,14208, 1976,30592, 1984,3968, 1992,20352, 2000,12160, 2008,28544, + 2016,8064, 2024,24448, 2032,16256, 2040,32640, 2056,16448, 2064,8256, + 2072,24640, 2080,4160, 2088,20544, 2096,12352, 2104,28736, 2120,18496, + 2128,10304, 2136,26688, 2144,6208, 2152,22592, 2160,14400, 2168,30784, + 2184,17472, 2192,9280, 2200,25664, 2208,5184, 2216,21568, 2224,13376, + 2232,29760, 2240,3136, 2248,19520, 2256,11328, 2264,27712, 2272,7232, + 2280,23616, 2288,15424, 2296,31808, 2312,16960, 2320,8768, 2328,25152, + 2336,4672, 2344,21056, 2352,12864, 2360,29248, 2368,2624, 2376,19008, + 2384,10816, 2392,27200, 2400,6720, 2408,23104, 2416,14912, 2424,31296, + 2440,17984, 2448,9792, 2456,26176, 2464,5696, 2472,22080, 2480,13888, + 2488,30272, 2496,3648, 2504,20032, 2512,11840, 2520,28224, 2528,7744, + 2536,24128, 2544,15936, 2552,32320, 2568,16704, 2576,8512, 2584,24896, + 2592,4416, 2600,20800, 2608,12608, 2616,28992, 2632,18752, 2640,10560, + 2648,26944, 2656,6464, 2664,22848, 2672,14656, 2680,31040, 2696,17728, + 2704,9536, 2712,25920, 2720,5440, 2728,21824, 2736,13632, 2744,30016, 2752,3392, + 2760,19776, 2768,11584, 2776,27968, 2784,7488, 2792,23872, 2800,15680, + 2808,32064, 2824,17216, 2832,9024, 2840,25408, 2848,4928, 2856,21312, + 2864,13120, 2872,29504, 2888,19264, 2896,11072, 2904,27456, 2912,6976, + 2920,23360, 2928,15168, 2936,31552, 2952,18240, 2960,10048, 2968,26432, + 2976,5952, 2984,22336, 2992,14144, 3000,30528, 3008,3904, 3016,20288, + 3024,12096, 3032,28480, 3040,8000, 3048,24384, 3056,16192, 3064,32576, + 3080,16576, 3088,8384, 3096,24768, 3104,4288, 3112,20672, 3120,12480, + 3128,28864, 3144,18624, 3152,10432, 3160,26816, 3168,6336, 3176,22720, + 3184,14528, 3192,30912, 3208,17600, 3216,9408, 3224,25792, 3232,5312, + 3240,21696, 3248,13504, 3256,29888, 3272,19648, 3280,11456, 3288,27840, + 3296,7360, 3304,23744, 3312,15552, 3320,31936, 3336,17088, 3344,8896, + 3352,25280, 3360,4800, 3368,21184, 3376,12992, 3384,29376, 3400,19136, + 3408,10944, 3416,27328, 3424,6848, 3432,23232, 3440,15040, 3448,31424, + 3464,18112, 3472,9920, 3480,26304, 3488,5824, 3496,22208, 3504,14016, + 3512,30400, 3520,3776, 3528,20160, 3536,11968, 3544,28352, 3552,7872, + 3560,24256, 3568,16064, 3576,32448, 3592,16832, 3600,8640, 3608,25024, + 3616,4544, 3624,20928, 3632,12736, 3640,29120, 3656,18880, 3664,10688, + 3672,27072, 3680,6592, 3688,22976, 3696,14784, 3704,31168, 3720,17856, + 3728,9664, 3736,26048, 3744,5568, 3752,21952, 3760,13760, 3768,30144, + 3784,19904, 3792,11712, 3800,28096, 3808,7616, 3816,24000, 3824,15808, + 3832,32192, 3848,17344, 3856,9152, 3864,25536, 3872,5056, 3880,21440, + 3888,13248, 3896,29632, 3912,19392, 3920,11200, 3928,27584, 3936,7104, + 3944,23488, 3952,15296, 3960,31680, 3976,18368, 3984,10176, 3992,26560, + 4000,6080, 4008,22464, 4016,14272, 4024,30656, 4040,20416, 4048,12224, + 4056,28608, 4064,8128, 4072,24512, 4080,16320, 4088,32704, 4104,16416, + 4112,8224, 4120,24608, 4136,20512, 4144,12320, 4152,28704, 4168,18464, + 4176,10272, 4184,26656, 4192,6176, 4200,22560, 4208,14368, 4216,30752, + 4232,17440, 4240,9248, 4248,25632, 4256,5152, 4264,21536, 4272,13344, + 4280,29728, 4296,19488, 4304,11296, 4312,27680, 4320,7200, 4328,23584, + 4336,15392, 4344,31776, 4360,16928, 4368,8736, 4376,25120, 4384,4640, + 4392,21024, 4400,12832, 4408,29216, 4424,18976, 4432,10784, 4440,27168, + 4448,6688, 4456,23072, 4464,14880, 4472,31264, 4488,17952, 4496,9760, + 4504,26144, 4512,5664, 4520,22048, 4528,13856, 4536,30240, 4552,20000, + 4560,11808, 4568,28192, 4576,7712, 4584,24096, 4592,15904, 4600,32288, + 4616,16672, 4624,8480, 4632,24864, 4648,20768, 4656,12576, 4664,28960, + 4680,18720, 4688,10528, 4696,26912, 4704,6432, 4712,22816, 4720,14624, + 4728,31008, 4744,17696, 4752,9504, 4760,25888, 4768,5408, 4776,21792, + 4784,13600, 4792,29984, 4808,19744, 4816,11552, 4824,27936, 4832,7456, + 4840,23840, 4848,15648, 4856,32032, 4872,17184, 4880,8992, 4888,25376, + 4904,21280, 4912,13088, 4920,29472, 4936,19232, 4944,11040, 4952,27424, + 4960,6944, 4968,23328, 4976,15136, 4984,31520, 5000,18208, 5008,10016, + 5016,26400, 5024,5920, 5032,22304, 5040,14112, 5048,30496, 5064,20256, + 5072,12064, 5080,28448, 5088,7968, 5096,24352, 5104,16160, 5112,32544, + 5128,16544, 5136,8352, 5144,24736, 5160,20640, 5168,12448, 5176,28832, + 5192,18592, 5200,10400, 5208,26784, 5216,6304, 5224,22688, 5232,14496, + 5240,30880, 5256,17568, 5264,9376, 5272,25760, 5288,21664, 5296,13472, + 5304,29856, 5320,19616, 5328,11424, 5336,27808, 5344,7328, 5352,23712, + 5360,15520, 5368,31904, 5384,17056, 5392,8864, 5400,25248, 5416,21152, + 5424,12960, 5432,29344, 5448,19104, 5456,10912, 5464,27296, 5472,6816, + 5480,23200, 5488,15008, 5496,31392, 5512,18080, 5520,9888, 5528,26272, + 5536,5792, 5544,22176, 5552,13984, 5560,30368, 5576,20128, 5584,11936, + 5592,28320, 5600,7840, 5608,24224, 5616,16032, 5624,32416, 5640,16800, + 5648,8608, 5656,24992, 5672,20896, 5680,12704, 5688,29088, 5704,18848, + 5712,10656, 5720,27040, 5728,6560, 5736,22944, 5744,14752, 5752,31136, + 5768,17824, 5776,9632, 5784,26016, 5800,21920, 5808,13728, 5816,30112, + 5832,19872, 5840,11680, 5848,28064, 5856,7584, 5864,23968, 5872,15776, + 5880,32160, 5896,17312, 5904,9120, 5912,25504, 5928,21408, 5936,13216, + 5944,29600, 5960,19360, 5968,11168, 5976,27552, 5984,7072, 5992,23456, + 6000,15264, 6008,31648, 6024,18336, 6032,10144, 6040,26528, 6056,22432, + 6064,14240, 6072,30624, 6088,20384, 6096,12192, 6104,28576, 6112,8096, + 6120,24480, 6128,16288, 6136,32672, 6152,16480, 6160,8288, 6168,24672, + 6184,20576, 6192,12384, 6200,28768, 6216,18528, 6224,10336, 6232,26720, + 6248,22624, 6256,14432, 6264,30816, 6280,17504, 6288,9312, 6296,25696, + 6312,21600, 6320,13408, 6328,29792, 6344,19552, 6352,11360, 6360,27744, + 6368,7264, 6376,23648, 6384,15456, 6392,31840, 6408,16992, 6416,8800, + 6424,25184, 6440,21088, 6448,12896, 6456,29280, 6472,19040, 6480,10848, + 6488,27232, 6496,6752, 6504,23136, 6512,14944, 6520,31328, 6536,18016, + 6544,9824, 6552,26208, 6568,22112, 6576,13920, 6584,30304, 6600,20064, + 6608,11872, 6616,28256, 6624,7776, 6632,24160, 6640,15968, 6648,32352, + 6664,16736, 6672,8544, 6680,24928, 6696,20832, 6704,12640, 6712,29024, + 6728,18784, 6736,10592, 6744,26976, 6760,22880, 6768,14688, 6776,31072, + 6792,17760, 6800,9568, 6808,25952, 6824,21856, 6832,13664, 6840,30048, + 6856,19808, 6864,11616, 6872,28000, 6880,7520, 6888,23904, 6896,15712, + 6904,32096, 6920,17248, 6928,9056, 6936,25440, 6952,21344, 6960,13152, + 6968,29536, 6984,19296, 6992,11104, 7000,27488, 7016,23392, 7024,15200, + 7032,31584, 7048,18272, 7056,10080, 7064,26464, 7080,22368, 7088,14176, + 7096,30560, 7112,20320, 7120,12128, 7128,28512, 7136,8032, 7144,24416, + 7152,16224, 7160,32608, 7176,16608, 7184,8416, 7192,24800, 7208,20704, + 7216,12512, 7224,28896, 7240,18656, 7248,10464, 7256,26848, 7272,22752, + 7280,14560, 7288,30944, 7304,17632, 7312,9440, 7320,25824, 7336,21728, + 7344,13536, 7352,29920, 7368,19680, 7376,11488, 7384,27872, 7400,23776, + 7408,15584, 7416,31968, 7432,17120, 7440,8928, 7448,25312, 7464,21216, + 7472,13024, 7480,29408, 7496,19168, 7504,10976, 7512,27360, 7528,23264, + 7536,15072, 7544,31456, 7560,18144, 7568,9952, 7576,26336, 7592,22240, + 7600,14048, 7608,30432, 7624,20192, 7632,12000, 7640,28384, 7648,7904, + 7656,24288, 7664,16096, 7672,32480, 7688,16864, 7696,8672, 7704,25056, + 7720,20960, 7728,12768, 7736,29152, 7752,18912, 7760,10720, 7768,27104, + 7784,23008, 7792,14816, 7800,31200, 7816,17888, 7824,9696, 7832,26080, + 7848,21984, 7856,13792, 7864,30176, 7880,19936, 7888,11744, 7896,28128, + 7912,24032, 7920,15840, 7928,32224, 7944,17376, 7952,9184, 7960,25568, + 7976,21472, 7984,13280, 7992,29664, 8008,19424, 8016,11232, 8024,27616, + 8040,23520, 8048,15328, 8056,31712, 8072,18400, 8080,10208, 8088,26592, + 8104,22496, 8112,14304, 8120,30688, 8136,20448, 8144,12256, 8152,28640, + 8168,24544, 8176,16352, 8184,32736, 8200,16400, 8216,24592, 8232,20496, + 8240,12304, 8248,28688, 8264,18448, 8272,10256, 8280,26640, 8296,22544, + 8304,14352, 8312,30736, 8328,17424, 8336,9232, 8344,25616, 8360,21520, + 8368,13328, 8376,29712, 8392,19472, 8400,11280, 8408,27664, 8424,23568, + 8432,15376, 8440,31760, 8456,16912, 8464,8720, 8472,25104, 8488,21008, + 8496,12816, 8504,29200, 8520,18960, 8528,10768, 8536,27152, 8552,23056, + 8560,14864, 8568,31248, 8584,17936, 8592,9744, 8600,26128, 8616,22032, + 8624,13840, 8632,30224, 8648,19984, 8656,11792, 8664,28176, 8680,24080, + 8688,15888, 8696,32272, 8712,16656, 8728,24848, 8744,20752, 8752,12560, + 8760,28944, 8776,18704, 8784,10512, 8792,26896, 8808,22800, 8816,14608, + 8824,30992, 8840,17680, 8848,9488, 8856,25872, 8872,21776, 8880,13584, + 8888,29968, 8904,19728, 8912,11536, 8920,27920, 8936,23824, 8944,15632, + 8952,32016, 8968,17168, 8984,25360, 9000,21264, 9008,13072, 9016,29456, + 9032,19216, 9040,11024, 9048,27408, 9064,23312, 9072,15120, 9080,31504, + 9096,18192, 9104,10000, 9112,26384, 9128,22288, 9136,14096, 9144,30480, + 9160,20240, 9168,12048, 9176,28432, 9192,24336, 9200,16144, 9208,32528, + 9224,16528, 9240,24720, 9256,20624, 9264,12432, 9272,28816, 9288,18576, + 9296,10384, 9304,26768, 9320,22672, 9328,14480, 9336,30864, 9352,17552, + 9368,25744, 9384,21648, 9392,13456, 9400,29840, 9416,19600, 9424,11408, + 9432,27792, 9448,23696, 9456,15504, 9464,31888, 9480,17040, 9496,25232, + 9512,21136, 9520,12944, 9528,29328, 9544,19088, 9552,10896, 9560,27280, + 9576,23184, 9584,14992, 9592,31376, 9608,18064, 9616,9872, 9624,26256, + 9640,22160, 9648,13968, 9656,30352, 9672,20112, 9680,11920, 9688,28304, + 9704,24208, 9712,16016, 9720,32400, 9736,16784, 9752,24976, 9768,20880, + 9776,12688, 9784,29072, 9800,18832, 9808,10640, 9816,27024, 9832,22928, + 9840,14736, 9848,31120, 9864,17808, 9880,26000, 9896,21904, 9904,13712, + 9912,30096, 9928,19856, 9936,11664, 9944,28048, 9960,23952, 9968,15760, + 9976,32144, 9992,17296, 10008,25488, 10024,21392, 10032,13200, 10040,29584, + 10056,19344, 10064,11152, 10072,27536, 10088,23440, 10096,15248, 10104,31632, + 10120,18320, 10136,26512, 10152,22416, 10160,14224, 10168,30608, 10184,20368, + 10192,12176, 10200,28560, 10216,24464, 10224,16272, 10232,32656, 10248,16464, + 10264,24656, 10280,20560, 10288,12368, 10296,28752, 10312,18512, 10328,26704, + 10344,22608, 10352,14416, 10360,30800, 10376,17488, 10392,25680, 10408,21584, + 10416,13392, 10424,29776, 10440,19536, 10448,11344, 10456,27728, 10472,23632, + 10480,15440, 10488,31824, 10504,16976, 10520,25168, 10536,21072, 10544,12880, + 10552,29264, 10568,19024, 10576,10832, 10584,27216, 10600,23120, 10608,14928, + 10616,31312, 10632,18000, 10648,26192, 10664,22096, 10672,13904, 10680,30288, + 10696,20048, 10704,11856, 10712,28240, 10728,24144, 10736,15952, 10744,32336, + 10760,16720, 10776,24912, 10792,20816, 10800,12624, 10808,29008, 10824,18768, + 10840,26960, 10856,22864, 10864,14672, 10872,31056, 10888,17744, 10904,25936, + 10920,21840, 10928,13648, 10936,30032, 10952,19792, 10960,11600, 10968,27984, + 10984,23888, 10992,15696, 11000,32080, 11016,17232, 11032,25424, 11048,21328, + 11056,13136, 11064,29520, 11080,19280, 11096,27472, 11112,23376, 11120,15184, + 11128,31568, 11144,18256, 11160,26448, 11176,22352, 11184,14160, 11192,30544, + 11208,20304, 11216,12112, 11224,28496, 11240,24400, 11248,16208, 11256,32592, + 11272,16592, 11288,24784, 11304,20688, 11312,12496, 11320,28880, 11336,18640, + 11352,26832, 11368,22736, 11376,14544, 11384,30928, 11400,17616, 11416,25808, + 11432,21712, 11440,13520, 11448,29904, 11464,19664, 11480,27856, 11496,23760, + 11504,15568, 11512,31952, 11528,17104, 11544,25296, 11560,21200, 11568,13008, + 11576,29392, 11592,19152, 11608,27344, 11624,23248, 11632,15056, 11640,31440, + 11656,18128, 11672,26320, 11688,22224, 11696,14032, 11704,30416, 11720,20176, + 11728,11984, 11736,28368, 11752,24272, 11760,16080, 11768,32464, 11784,16848, + 11800,25040, 11816,20944, 11824,12752, 11832,29136, 11848,18896, 11864,27088, + 11880,22992, 11888,14800, 11896,31184, 11912,17872, 11928,26064, 11944,21968, + 11952,13776, 11960,30160, 11976,19920, 11992,28112, 12008,24016, 12016,15824, + 12024,32208, 12040,17360, 12056,25552, 12072,21456, 12080,13264, 12088,29648, + 12104,19408, 12120,27600, 12136,23504, 12144,15312, 12152,31696, 12168,18384, + 12184,26576, 12200,22480, 12208,14288, 12216,30672, 12232,20432, 12248,28624, + 12264,24528, 12272,16336, 12280,32720, 12296,16432, 12312,24624, 12328,20528, + 12344,28720, 12360,18480, 12376,26672, 12392,22576, 12400,14384, 12408,30768, + 12424,17456, 12440,25648, 12456,21552, 12464,13360, 12472,29744, 12488,19504, + 12504,27696, 12520,23600, 12528,15408, 12536,31792, 12552,16944, 12568,25136, + 12584,21040, 12592,12848, 12600,29232, 12616,18992, 12632,27184, 12648,23088, + 12656,14896, 12664,31280, 12680,17968, 12696,26160, 12712,22064, 12720,13872, + 12728,30256, 12744,20016, 12760,28208, 12776,24112, 12784,15920, 12792,32304, + 12808,16688, 12824,24880, 12840,20784, 12856,28976, 12872,18736, 12888,26928, + 12904,22832, 12912,14640, 12920,31024, 12936,17712, 12952,25904, 12968,21808, + 12976,13616, 12984,30000, 13000,19760, 13016,27952, 13032,23856, 13040,15664, + 13048,32048, 13064,17200, 13080,25392, 13096,21296, 13112,29488, 13128,19248, + 13144,27440, 13160,23344, 13168,15152, 13176,31536, 13192,18224, 13208,26416, + 13224,22320, 13232,14128, 13240,30512, 13256,20272, 13272,28464, 13288,24368, + 13296,16176, 13304,32560, 13320,16560, 13336,24752, 13352,20656, 13368,28848, + 13384,18608, 13400,26800, 13416,22704, 13424,14512, 13432,30896, 13448,17584, + 13464,25776, 13480,21680, 13496,29872, 13512,19632, 13528,27824, 13544,23728, + 13552,15536, 13560,31920, 13576,17072, 13592,25264, 13608,21168, 13624,29360, + 13640,19120, 13656,27312, 13672,23216, 13680,15024, 13688,31408, 13704,18096, + 13720,26288, 13736,22192, 13744,14000, 13752,30384, 13768,20144, 13784,28336, + 13800,24240, 13808,16048, 13816,32432, 13832,16816, 13848,25008, 13864,20912, + 13880,29104, 13896,18864, 13912,27056, 13928,22960, 13936,14768, 13944,31152, + 13960,17840, 13976,26032, 13992,21936, 14008,30128, 14024,19888, 14040,28080, + 14056,23984, 14064,15792, 14072,32176, 14088,17328, 14104,25520, 14120,21424, + 14136,29616, 14152,19376, 14168,27568, 14184,23472, 14192,15280, 14200,31664, + 14216,18352, 14232,26544, 14248,22448, 14264,30640, 14280,20400, 14296,28592, + 14312,24496, 14320,16304, 14328,32688, 14344,16496, 14360,24688, 14376,20592, + 14392,28784, 14408,18544, 14424,26736, 14440,22640, 14456,30832, 14472,17520, + 14488,25712, 14504,21616, 14520,29808, 14536,19568, 14552,27760, 14568,23664, + 14576,15472, 14584,31856, 14600,17008, 14616,25200, 14632,21104, 14648,29296, + 14664,19056, 14680,27248, 14696,23152, 14704,14960, 14712,31344, 14728,18032, + 14744,26224, 14760,22128, 14776,30320, 14792,20080, 14808,28272, 14824,24176, + 14832,15984, 14840,32368, 14856,16752, 14872,24944, 14888,20848, 14904,29040, + 14920,18800, 14936,26992, 14952,22896, 14968,31088, 14984,17776, 15000,25968, + 15016,21872, 15032,30064, 15048,19824, 15064,28016, 15080,23920, 15088,15728, + 15096,32112, 15112,17264, 15128,25456, 15144,21360, 15160,29552, 15176,19312, + 15192,27504, 15208,23408, 15224,31600, 15240,18288, 15256,26480, 15272,22384, + 15288,30576, 15304,20336, 15320,28528, 15336,24432, 15344,16240, 15352,32624, + 15368,16624, 15384,24816, 15400,20720, 15416,28912, 15432,18672, 15448,26864, + 15464,22768, 15480,30960, 15496,17648, 15512,25840, 15528,21744, 15544,29936, + 15560,19696, 15576,27888, 15592,23792, 15608,31984, 15624,17136, 15640,25328, + 15656,21232, 15672,29424, 15688,19184, 15704,27376, 15720,23280, 15736,31472, + 15752,18160, 15768,26352, 15784,22256, 15800,30448, 15816,20208, 15832,28400, + 15848,24304, 15856,16112, 15864,32496, 15880,16880, 15896,25072, 15912,20976, + 15928,29168, 15944,18928, 15960,27120, 15976,23024, 15992,31216, 16008,17904, + 16024,26096, 16040,22000, 16056,30192, 16072,19952, 16088,28144, 16104,24048, + 16120,32240, 16136,17392, 16152,25584, 16168,21488, 16184,29680, 16200,19440, + 16216,27632, 16232,23536, 16248,31728, 16264,18416, 16280,26608, 16296,22512, + 16312,30704, 16328,20464, 16344,28656, 16360,24560, 16376,32752, 16408,24584, + 16424,20488, 16440,28680, 16456,18440, 16472,26632, 16488,22536, 16504,30728, + 16520,17416, 16536,25608, 16552,21512, 16568,29704, 16584,19464, 16600,27656, + 16616,23560, 16632,31752, 16648,16904, 16664,25096, 16680,21000, 16696,29192, + 16712,18952, 16728,27144, 16744,23048, 16760,31240, 16776,17928, 16792,26120, + 16808,22024, 16824,30216, 16840,19976, 16856,28168, 16872,24072, 16888,32264, + 16920,24840, 16936,20744, 16952,28936, 16968,18696, 16984,26888, 17000,22792, + 17016,30984, 17032,17672, 17048,25864, 17064,21768, 17080,29960, 17096,19720, + 17112,27912, 17128,23816, 17144,32008, 17176,25352, 17192,21256, 17208,29448, + 17224,19208, 17240,27400, 17256,23304, 17272,31496, 17288,18184, 17304,26376, + 17320,22280, 17336,30472, 17352,20232, 17368,28424, 17384,24328, 17400,32520, + 17432,24712, 17448,20616, 17464,28808, 17480,18568, 17496,26760, 17512,22664, + 17528,30856, 17560,25736, 17576,21640, 17592,29832, 17608,19592, 17624,27784, + 17640,23688, 17656,31880, 17688,25224, 17704,21128, 17720,29320, 17736,19080, + 17752,27272, 17768,23176, 17784,31368, 17800,18056, 17816,26248, 17832,22152, + 17848,30344, 17864,20104, 17880,28296, 17896,24200, 17912,32392, 17944,24968, + 17960,20872, 17976,29064, 17992,18824, 18008,27016, 18024,22920, 18040,31112, + 18072,25992, 18088,21896, 18104,30088, 18120,19848, 18136,28040, 18152,23944, + 18168,32136, 18200,25480, 18216,21384, 18232,29576, 18248,19336, 18264,27528, + 18280,23432, 18296,31624, 18328,26504, 18344,22408, 18360,30600, 18376,20360, + 18392,28552, 18408,24456, 18424,32648, 18456,24648, 18472,20552, 18488,28744, + 18520,26696, 18536,22600, 18552,30792, 18584,25672, 18600,21576, 18616,29768, + 18632,19528, 18648,27720, 18664,23624, 18680,31816, 18712,25160, 18728,21064, + 18744,29256, 18760,19016, 18776,27208, 18792,23112, 18808,31304, 18840,26184, + 18856,22088, 18872,30280, 18888,20040, 18904,28232, 18920,24136, 18936,32328, + 18968,24904, 18984,20808, 19000,29000, 19032,26952, 19048,22856, 19064,31048, + 19096,25928, 19112,21832, 19128,30024, 19144,19784, 19160,27976, 19176,23880, + 19192,32072, 19224,25416, 19240,21320, 19256,29512, 19288,27464, 19304,23368, + 19320,31560, 19352,26440, 19368,22344, 19384,30536, 19400,20296, 19416,28488, + 19432,24392, 19448,32584, 19480,24776, 19496,20680, 19512,28872, 19544,26824, + 19560,22728, 19576,30920, 19608,25800, 19624,21704, 19640,29896, 19672,27848, + 19688,23752, 19704,31944, 19736,25288, 19752,21192, 19768,29384, 19800,27336, + 19816,23240, 19832,31432, 19864,26312, 19880,22216, 19896,30408, 19912,20168, + 19928,28360, 19944,24264, 19960,32456, 19992,25032, 20008,20936, 20024,29128, + 20056,27080, 20072,22984, 20088,31176, 20120,26056, 20136,21960, 20152,30152, + 20184,28104, 20200,24008, 20216,32200, 20248,25544, 20264,21448, 20280,29640, + 20312,27592, 20328,23496, 20344,31688, 20376,26568, 20392,22472, 20408,30664, + 20440,28616, 20456,24520, 20472,32712, 20504,24616, 20536,28712, 20568,26664, + 20584,22568, 20600,30760, 20632,25640, 20648,21544, 20664,29736, 20696,27688, + 20712,23592, 20728,31784, 20760,25128, 20776,21032, 20792,29224, 20824,27176, + 20840,23080, 20856,31272, 20888,26152, 20904,22056, 20920,30248, 20952,28200, + 20968,24104, 20984,32296, 21016,24872, 21048,28968, 21080,26920, 21096,22824, + 21112,31016, 21144,25896, 21160,21800, 21176,29992, 21208,27944, 21224,23848, + 21240,32040, 21272,25384, 21304,29480, 21336,27432, 21352,23336, 21368,31528, + 21400,26408, 21416,22312, 21432,30504, 21464,28456, 21480,24360, 21496,32552, + 21528,24744, 21560,28840, 21592,26792, 21608,22696, 21624,30888, 21656,25768, + 21688,29864, 21720,27816, 21736,23720, 21752,31912, 21784,25256, 21816,29352, + 21848,27304, 21864,23208, 21880,31400, 21912,26280, 21928,22184, 21944,30376, + 21976,28328, 21992,24232, 22008,32424, 22040,25000, 22072,29096, 22104,27048, + 22120,22952, 22136,31144, 22168,26024, 22200,30120, 22232,28072, 22248,23976, + 22264,32168, 22296,25512, 22328,29608, 22360,27560, 22376,23464, 22392,31656, + 22424,26536, 22456,30632, 22488,28584, 22504,24488, 22520,32680, 22552,24680, + 22584,28776, 22616,26728, 22648,30824, 22680,25704, 22712,29800, 22744,27752, + 22760,23656, 22776,31848, 22808,25192, 22840,29288, 22872,27240, 22888,23144, + 22904,31336, 22936,26216, 22968,30312, 23000,28264, 23016,24168, 23032,32360, + 23064,24936, 23096,29032, 23128,26984, 23160,31080, 23192,25960, 23224,30056, + 23256,28008, 23272,23912, 23288,32104, 23320,25448, 23352,29544, 23384,27496, + 23416,31592, 23448,26472, 23480,30568, 23512,28520, 23528,24424, 23544,32616, + 23576,24808, 23608,28904, 23640,26856, 23672,30952, 23704,25832, 23736,29928, + 23768,27880, 23800,31976, 23832,25320, 23864,29416, 23896,27368, 23928,31464, + 23960,26344, 23992,30440, 24024,28392, 24040,24296, 24056,32488, 24088,25064, + 24120,29160, 24152,27112, 24184,31208, 24216,26088, 24248,30184, 24280,28136, + 24312,32232, 24344,25576, 24376,29672, 24408,27624, 24440,31720, 24472,26600, + 24504,30696, 24536,28648, 24568,32744, 24632,28696, 24664,26648, 24696,30744, + 24728,25624, 24760,29720, 24792,27672, 24824,31768, 24856,25112, 24888,29208, + 24920,27160, 24952,31256, 24984,26136, 25016,30232, 25048,28184, 25080,32280, + 25144,28952, 25176,26904, 25208,31000, 25240,25880, 25272,29976, 25304,27928, + 25336,32024, 25400,29464, 25432,27416, 25464,31512, 25496,26392, 25528,30488, + 25560,28440, 25592,32536, 25656,28824, 25688,26776, 25720,30872, 25784,29848, + 25816,27800, 25848,31896, 25912,29336, 25944,27288, 25976,31384, 26008,26264, + 26040,30360, 26072,28312, 26104,32408, 26168,29080, 26200,27032, 26232,31128, + 26296,30104, 26328,28056, 26360,32152, 26424,29592, 26456,27544, 26488,31640, + 26552,30616, 26584,28568, 26616,32664, 26680,28760, 26744,30808, 26808,29784, + 26840,27736, 26872,31832, 26936,29272, 26968,27224, 27000,31320, 27064,30296, + 27096,28248, 27128,32344, 27192,29016, 27256,31064, 27320,30040, 27352,27992, + 27384,32088, 27448,29528, 27512,31576, 27576,30552, 27608,28504, 27640,32600, + 27704,28888, 27768,30936, 27832,29912, 27896,31960, 27960,29400, 28024,31448, + 28088,30424, 28120,28376, 28152,32472, 28216,29144, 28280,31192, 28344,30168, + 28408,32216, 28472,29656, 28536,31704, 28600,30680, 28664,32728, 28792,30776, + 28856,29752, 28920,31800, 28984,29240, 29048,31288, 29112,30264, 29176,32312, + 29304,31032, 29368,30008, 29432,32056, 29560,31544, 29624,30520, 29688,32568, + 29816,30904, 29944,31928, 30072,31416, 30136,30392, 30200,32440, 30328,31160, + 30456,32184, 30584,31672, 30712,32696, 30968,31864, 31096,31352, 31224,32376, + 31480,32120, 31736,32632, 32248,32504 +}; +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F64_32) +/** + @par + Example code for Double Precision Floating-point RFFT Twiddle factors Generation: + @par + 
TW = exp(pi/2*i-2*pi*i*[0:L/2-1]/L).'
+ @par + Real and Imag values are in interleaved fashion +*/ +const uint64_t twiddleCoefF64_rfft_32[32] = { + 0x0000000000000000, 0x3ff0000000000000, // 0, 1 + 0x3fc8f8b83c69a60a, 0x3fef6297cff75cb0, //0.19509, 0.98079 + 0x3fd87de2a6aea963, 0x3fed906bcf328d46, //0.38268, 0.92388 + 0x3fe1c73b39ae68c8, 0x3fea9b66290ea1a3, //0.55557, 0.83147 + 0x3fe6a09e667f3bcc, 0x3fe6a09e667f3bcc, //0.70711, 0.70711 + 0x3fea9b66290ea1a3, 0x3fe1c73b39ae68c8, //0.83147, 0.55557 + 0x3fed906bcf328d46, 0x3fd87de2a6aea963, //0.92388, 0.38268 + 0x3fef6297cff75cb0, 0x3fc8f8b83c69a60a, //0.98079, 0.19509 + 0x3ff0000000000000, 0x0000000000000000, // 1, 0 + 0x3fef6297cff75cb0, 0xbfc8f8b83c69a60a, //0.98079,-0.19509 + 0x3fed906bcf328d46, 0xbfd87de2a6aea963, //0.92388,-0.38268 + 0x3fea9b66290ea1a3, 0xbfe1c73b39ae68c8, //0.83147,-0.55557 + 0x3fe6a09e667f3bcc, 0xbfe6a09e667f3bcc, //0.70711,-0.70711 + 0x3fe1c73b39ae68c8, 0xbfea9b66290ea1a3, //0.55557,-0.83147 + 0x3fd87de2a6aea963, 0xbfed906bcf328d46, //0.38268,-0.92388 + 0x3fc8f8b83c69a60a, 0xbfef6297cff75cb0, //0.19509,-0.98079 +}; +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F64_64) +const uint64_t twiddleCoefF64_rfft_64[64] = { + 0x0000000000000000, 0x3ff0000000000000, // 0, 1' + 0x3fb917a6bc29b42c, 0x3fefd88da3d12526, //0.098017, 0.99518' + 0x3fc8f8b83c69a60a, 0x3fef6297cff75cb0, // 0.19509, 0.98079' + 0x3fd294062ed59f05, 0x3fee9f4156c62dda, // 0.29028, 0.95694' + 0x3fd87de2a6aea963, 0x3fed906bcf328d46, // 0.38268, 0.92388' + 0x3fde2b5d3806f63b, 0x3fec38b2f180bdb1, // 0.4714, 0.88192' + 0x3fe1c73b39ae68c8, 0x3fea9b66290ea1a3, // 0.55557, 0.83147' + 0x3fe44cf325091dd6, 0x3fe8bc806b151741, // 0.63439, 0.77301' + 0x3fe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // 0.70711, 0.70711' + 0x3fe8bc806b151741, 0x3fe44cf325091dd6, // 0.77301, 0.63439' + 0x3fea9b66290ea1a3, 0x3fe1c73b39ae68c8, // 0.83147, 0.55557' + 0x3fec38b2f180bdb1, 0x3fde2b5d3806f63b, // 0.88192, 0.4714' + 0x3fed906bcf328d46, 0x3fd87de2a6aea963, // 0.92388, 0.38268' + 0x3fee9f4156c62dda, 0x3fd294062ed59f05, // 0.95694, 0.29028' + 0x3fef6297cff75cb0, 0x3fc8f8b83c69a60a, // 0.98079, 0.19509' + 0x3fefd88da3d12526, 0x3fb917a6bc29b42c, // 0.99518, 0.098017' + 0x3ff0000000000000, 0x0000000000000000, // 1, 0' + 0x3fefd88da3d12526, 0xbfb917a6bc29b42c, // 0.99518,-0.098017' + 0x3fef6297cff75cb0, 0xbfc8f8b83c69a60a, // 0.98079, -0.19509' + 0x3fee9f4156c62dda, 0xbfd294062ed59f05, // 0.95694, -0.29028' + 0x3fed906bcf328d46, 0xbfd87de2a6aea963, // 0.92388, -0.38268' + 0x3fec38b2f180bdb1, 0xbfde2b5d3806f63b, // 0.88192, -0.4714' + 0x3fea9b66290ea1a3, 0xbfe1c73b39ae68c8, // 0.83147, -0.55557' + 0x3fe8bc806b151741, 0xbfe44cf325091dd6, // 0.77301, -0.63439' + 0x3fe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // 0.70711, -0.70711' + 0x3fe44cf325091dd6, 0xbfe8bc806b151741, // 0.63439, -0.77301' + 0x3fe1c73b39ae68c8, 0xbfea9b66290ea1a3, // 0.55557, -0.83147' + 0x3fde2b5d3806f63b, 0xbfec38b2f180bdb1, // 0.4714, -0.88192' + 0x3fd87de2a6aea963, 0xbfed906bcf328d46, // 0.38268, -0.92388' + 0x3fd294062ed59f05, 0xbfee9f4156c62dda, // 0.29028, -0.95694' + 0x3fc8f8b83c69a60a, 0xbfef6297cff75cb0, // 0.19509, -0.98079' + 0x3fb917a6bc29b42c, 0xbfefd88da3d12526, //0.098017, -0.99518' +}; +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F64_128) +const uint64_t twiddleCoefF64_rfft_128[128] = { + 0x0000000000000000, 0x3ff0000000000000, // 0, 1' + 0x3fa91f65f10dd814, 0x3feff621e3796d7e, //0.049068, 0.9988' + 0x3fb917a6bc29b42c, 0x3fefd88da3d12526, //0.098017, 0.99518' + 0x3fc2c8106e8e613a, 0x3fefa7557f08a517, // 0.14673, 0.98918' + 0x3fc8f8b83c69a60a, 0x3fef6297cff75cb0, // 0.19509, 0.98079' + 0x3fcf19f97b215f1a, 0x3fef0a7efb9230d7, // 0.24298, 0.97003' + 0x3fd294062ed59f05, 0x3fee9f4156c62dda, // 0.29028, 0.95694' + 0x3fd58f9a75ab1fdd, 0x3fee212104f686e5, // 0.33689, 0.94154' + 0x3fd87de2a6aea963, 0x3fed906bcf328d46, // 0.38268, 0.92388' + 0x3fdb5d1009e15cc0, 0x3feced7af43cc773, // 0.42756, 0.90399' + 0x3fde2b5d3806f63b, 0x3fec38b2f180bdb1, // 0.4714, 0.88192' + 0x3fe073879922ffed, 0x3feb728345196e3e, // 0.5141, 0.85773' + 0x3fe1c73b39ae68c8, 0x3fea9b66290ea1a3, // 0.55557, 0.83147' + 0x3fe30ff7fce17035, 0x3fe9b3e047f38741, // 0.5957, 0.80321' + 0x3fe44cf325091dd6, 0x3fe8bc806b151741, // 0.63439, 0.77301' + 0x3fe57d69348cec9f, 0x3fe7b5df226aafb0, // 0.67156, 0.74095' + 0x3fe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // 0.70711, 0.70711' + 0x3fe7b5df226aafb0, 0x3fe57d69348cec9f, // 0.74095, 0.67156' + 0x3fe8bc806b151741, 0x3fe44cf325091dd6, // 0.77301, 0.63439' + 0x3fe9b3e047f38741, 0x3fe30ff7fce17035, // 0.80321, 0.5957' + 0x3fea9b66290ea1a3, 0x3fe1c73b39ae68c8, // 0.83147, 0.55557' + 0x3feb728345196e3e, 0x3fe073879922ffed, // 0.85773, 0.5141' + 0x3fec38b2f180bdb1, 0x3fde2b5d3806f63b, // 0.88192, 0.4714' + 0x3feced7af43cc773, 0x3fdb5d1009e15cc0, // 0.90399, 0.42756' + 0x3fed906bcf328d46, 0x3fd87de2a6aea963, // 0.92388, 0.38268' + 0x3fee212104f686e5, 0x3fd58f9a75ab1fdd, // 0.94154, 0.33689' + 0x3fee9f4156c62dda, 0x3fd294062ed59f05, // 0.95694, 0.29028' + 0x3fef0a7efb9230d7, 0x3fcf19f97b215f1a, // 0.97003, 0.24298' + 0x3fef6297cff75cb0, 0x3fc8f8b83c69a60a, // 0.98079, 0.19509' + 0x3fefa7557f08a517, 0x3fc2c8106e8e613a, // 0.98918, 0.14673' + 0x3fefd88da3d12526, 0x3fb917a6bc29b42c, // 0.99518, 0.098017' + 0x3feff621e3796d7e, 0x3fa91f65f10dd814, // 0.9988, 0.049068' + 0x3ff0000000000000, 0x0000000000000000, // 1, 0' + 0x3feff621e3796d7e, 0xbfa91f65f10dd814, // 0.9988,-0.049068' + 0x3fefd88da3d12526, 0xbfb917a6bc29b42c, // 0.99518,-0.098017' + 0x3fefa7557f08a517, 0xbfc2c8106e8e613a, // 0.98918, -0.14673' + 0x3fef6297cff75cb0, 0xbfc8f8b83c69a60a, // 0.98079, -0.19509' + 0x3fef0a7efb9230d7, 0xbfcf19f97b215f1a, // 0.97003, -0.24298' + 0x3fee9f4156c62dda, 0xbfd294062ed59f05, // 0.95694, -0.29028' + 0x3fee212104f686e5, 0xbfd58f9a75ab1fdd, // 0.94154, -0.33689' + 0x3fed906bcf328d46, 0xbfd87de2a6aea963, // 0.92388, -0.38268' + 0x3feced7af43cc773, 0xbfdb5d1009e15cc0, // 0.90399, -0.42756' + 0x3fec38b2f180bdb1, 0xbfde2b5d3806f63b, // 0.88192, -0.4714' + 0x3feb728345196e3e, 0xbfe073879922ffed, // 0.85773, -0.5141' + 0x3fea9b66290ea1a3, 0xbfe1c73b39ae68c8, // 0.83147, -0.55557' + 0x3fe9b3e047f38741, 0xbfe30ff7fce17035, // 0.80321, -0.5957' + 0x3fe8bc806b151741, 0xbfe44cf325091dd6, // 0.77301, -0.63439' + 0x3fe7b5df226aafb0, 0xbfe57d69348cec9f, // 0.74095, -0.67156' + 0x3fe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // 0.70711, -0.70711' + 0x3fe57d69348cec9f, 0xbfe7b5df226aafb0, // 0.67156, -0.74095' + 0x3fe44cf325091dd6, 0xbfe8bc806b151741, // 0.63439, -0.77301' + 0x3fe30ff7fce17035, 0xbfe9b3e047f38741, // 0.5957, -0.80321' + 0x3fe1c73b39ae68c8, 0xbfea9b66290ea1a3, // 0.55557, -0.83147' + 0x3fe073879922ffed, 0xbfeb728345196e3e, // 0.5141, -0.85773' + 0x3fde2b5d3806f63b, 0xbfec38b2f180bdb1, // 0.4714, -0.88192' + 0x3fdb5d1009e15cc0, 0xbfeced7af43cc773, // 0.42756, -0.90399' + 0x3fd87de2a6aea963, 0xbfed906bcf328d46, // 0.38268, -0.92388' + 0x3fd58f9a75ab1fdd, 0xbfee212104f686e5, // 0.33689, -0.94154' + 0x3fd294062ed59f05, 0xbfee9f4156c62dda, // 0.29028, -0.95694' + 0x3fcf19f97b215f1a, 0xbfef0a7efb9230d7, // 0.24298, -0.97003' + 0x3fc8f8b83c69a60a, 0xbfef6297cff75cb0, // 0.19509, -0.98079' + 0x3fc2c8106e8e613a, 0xbfefa7557f08a517, // 0.14673, -0.98918' + 0x3fb917a6bc29b42c, 0xbfefd88da3d12526, //0.098017, -0.99518' + 0x3fa91f65f10dd814, 0xbfeff621e3796d7e, //0.049068, -0.9988' +}; +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F64_256) +const uint64_t twiddleCoefF64_rfft_256[256] = { + 0x0000000000000000, 0x3ff0000000000000, // 0, 1 + 0x3f992155f7a3667e, 0x3feffd886084cd0d, //0.024541, 0.9997 + 0x3fa91f65f10dd814, 0x3feff621e3796d7e, //0.049068, 0.9988 + 0x3fb2d52092ce19f6, 0x3fefe9cdad01883a, //0.073565, 0.99729 + 0x3fb917a6bc29b42c, 0x3fefd88da3d12526, //0.098017, 0.99518 + 0x3fbf564e56a9730e, 0x3fefc26470e19fd3, // 0.12241, 0.99248 + 0x3fc2c8106e8e613a, 0x3fefa7557f08a517, // 0.14673, 0.98918 + 0x3fc5e214448b3fc6, 0x3fef8764fa714ba9, // 0.17096, 0.98528 + 0x3fc8f8b83c69a60a, 0x3fef6297cff75cb0, // 0.19509, 0.98079 + 0x3fcc0b826a7e4f63, 0x3fef38f3ac64e589, // 0.2191, 0.9757 + 0x3fcf19f97b215f1a, 0x3fef0a7efb9230d7, // 0.24298, 0.97003 + 0x3fd111d262b1f677, 0x3feed740e7684963, // 0.26671, 0.96378 + 0x3fd294062ed59f05, 0x3fee9f4156c62dda, // 0.29028, 0.95694 + 0x3fd4135c94176602, 0x3fee6288ec48e112, // 0.31368, 0.94953 + 0x3fd58f9a75ab1fdd, 0x3fee212104f686e5, // 0.33689, 0.94154 + 0x3fd7088530fa459e, 0x3feddb13b6ccc23d, // 0.3599, 0.93299 + 0x3fd87de2a6aea963, 0x3fed906bcf328d46, // 0.38268, 0.92388 + 0x3fd9ef7943a8ed8a, 0x3fed4134d14dc93a, // 0.40524, 0.91421 + 0x3fdb5d1009e15cc0, 0x3feced7af43cc773, // 0.42756, 0.90399 + 0x3fdcc66e9931c45d, 0x3fec954b213411f5, // 0.44961, 0.89322 + 0x3fde2b5d3806f63b, 0x3fec38b2f180bdb1, // 0.4714, 0.88192 + 0x3fdf8ba4dbf89aba, 0x3febd7c0ac6f952a, // 0.4929, 0.87009 + 0x3fe073879922ffed, 0x3feb728345196e3e, // 0.5141, 0.85773 + 0x3fe11eb3541b4b22, 0x3feb090a58150200, // 0.535, 0.84485 + 0x3fe1c73b39ae68c8, 0x3fea9b66290ea1a3, // 0.55557, 0.83147 + 0x3fe26d054cdd12df, 0x3fea29a7a0462782, // 0.57581, 0.81758 + 0x3fe30ff7fce17035, 0x3fe9b3e047f38741, // 0.5957, 0.80321 + 0x3fe3affa292050b9, 0x3fe93a22499263fc, // 0.61523, 0.78835 + 0x3fe44cf325091dd6, 0x3fe8bc806b151741, // 0.63439, 0.77301 + 0x3fe4e6cabbe3e5e9, 0x3fe83b0e0bff976e, // 0.65317, 0.75721 + 0x3fe57d69348cec9f, 0x3fe7b5df226aafb0, // 0.67156, 0.74095 + 0x3fe610b7551d2cde, 0x3fe72d0837efff97, // 0.68954, 0.72425 + 0x3fe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // 0.70711, 0.70711 + 0x3fe72d0837efff97, 0x3fe610b7551d2cde, // 0.72425, 0.68954 + 0x3fe7b5df226aafb0, 0x3fe57d69348cec9f, // 0.74095, 0.67156 + 0x3fe83b0e0bff976e, 0x3fe4e6cabbe3e5e9, // 0.75721, 0.65317 + 0x3fe8bc806b151741, 0x3fe44cf325091dd6, // 0.77301, 0.63439 + 0x3fe93a22499263fc, 0x3fe3affa292050b9, // 0.78835, 0.61523 + 0x3fe9b3e047f38741, 0x3fe30ff7fce17035, // 0.80321, 0.5957 + 0x3fea29a7a0462782, 0x3fe26d054cdd12df, // 0.81758, 0.57581 + 0x3fea9b66290ea1a3, 0x3fe1c73b39ae68c8, // 0.83147, 0.55557 + 0x3feb090a58150200, 0x3fe11eb3541b4b22, // 0.84485, 0.535 + 0x3feb728345196e3e, 0x3fe073879922ffed, // 0.85773, 0.5141 + 0x3febd7c0ac6f952a, 0x3fdf8ba4dbf89aba, // 0.87009, 0.4929 + 0x3fec38b2f180bdb1, 0x3fde2b5d3806f63b, // 0.88192, 0.4714 + 0x3fec954b213411f5, 0x3fdcc66e9931c45d, // 0.89322, 0.44961 + 0x3feced7af43cc773, 0x3fdb5d1009e15cc0, // 0.90399, 0.42756 + 0x3fed4134d14dc93a, 0x3fd9ef7943a8ed8a, // 0.91421, 0.40524 + 0x3fed906bcf328d46, 0x3fd87de2a6aea963, // 0.92388, 0.38268 + 0x3feddb13b6ccc23d, 0x3fd7088530fa459e, // 0.93299, 0.3599 + 0x3fee212104f686e5, 0x3fd58f9a75ab1fdd, // 0.94154, 0.33689 + 0x3fee6288ec48e112, 0x3fd4135c94176602, // 0.94953, 0.31368 + 0x3fee9f4156c62dda, 0x3fd294062ed59f05, // 0.95694, 0.29028 + 0x3feed740e7684963, 0x3fd111d262b1f677, // 0.96378, 0.26671 + 0x3fef0a7efb9230d7, 0x3fcf19f97b215f1a, // 0.97003, 0.24298 + 0x3fef38f3ac64e589, 0x3fcc0b826a7e4f63, // 0.9757, 0.2191 + 0x3fef6297cff75cb0, 0x3fc8f8b83c69a60a, // 0.98079, 0.19509 + 0x3fef8764fa714ba9, 0x3fc5e214448b3fc6, // 0.98528, 0.17096 + 0x3fefa7557f08a517, 0x3fc2c8106e8e613a, // 0.98918, 0.14673 + 0x3fefc26470e19fd3, 0x3fbf564e56a9730e, // 0.99248, 0.12241 + 0x3fefd88da3d12526, 0x3fb917a6bc29b42c, // 0.99518, 0.098017 + 0x3fefe9cdad01883a, 0x3fb2d52092ce19f6, // 0.99729, 0.073565 + 0x3feff621e3796d7e, 0x3fa91f65f10dd814, // 0.9988, 0.049068 + 0x3feffd886084cd0d, 0x3f992155f7a3667e, // 0.9997, 0.024541 + 0x3ff0000000000000, 0x0000000000000000, // 1, 0 + 0x3feffd886084cd0d, 0xbf992155f7a3667e, // 0.9997,-0.024541 + 0x3feff621e3796d7e, 0xbfa91f65f10dd814, // 0.9988,-0.049068 + 0x3fefe9cdad01883a, 0xbfb2d52092ce19f6, // 0.99729,-0.073565 + 0x3fefd88da3d12526, 0xbfb917a6bc29b42c, // 0.99518,-0.098017 + 0x3fefc26470e19fd3, 0xbfbf564e56a9730e, // 0.99248, -0.12241 + 0x3fefa7557f08a517, 0xbfc2c8106e8e613a, // 0.98918, -0.14673 + 0x3fef8764fa714ba9, 0xbfc5e214448b3fc6, // 0.98528, -0.17096 + 0x3fef6297cff75cb0, 0xbfc8f8b83c69a60a, // 0.98079, -0.19509 + 0x3fef38f3ac64e589, 0xbfcc0b826a7e4f63, // 0.9757, -0.2191 + 0x3fef0a7efb9230d7, 0xbfcf19f97b215f1a, // 0.97003, -0.24298 + 0x3feed740e7684963, 0xbfd111d262b1f677, // 0.96378, -0.26671 + 0x3fee9f4156c62dda, 0xbfd294062ed59f05, // 0.95694, -0.29028 + 0x3fee6288ec48e112, 0xbfd4135c94176602, // 0.94953, -0.31368 + 0x3fee212104f686e5, 0xbfd58f9a75ab1fdd, // 0.94154, -0.33689 + 0x3feddb13b6ccc23d, 0xbfd7088530fa459e, // 0.93299, -0.3599 + 0x3fed906bcf328d46, 0xbfd87de2a6aea963, // 0.92388, -0.38268 + 0x3fed4134d14dc93a, 0xbfd9ef7943a8ed8a, // 0.91421, -0.40524 + 0x3feced7af43cc773, 0xbfdb5d1009e15cc0, // 0.90399, -0.42756 + 0x3fec954b213411f5, 0xbfdcc66e9931c45d, // 0.89322, -0.44961 + 0x3fec38b2f180bdb1, 0xbfde2b5d3806f63b, // 0.88192, -0.4714 + 0x3febd7c0ac6f952a, 0xbfdf8ba4dbf89aba, // 0.87009, -0.4929 + 0x3feb728345196e3e, 0xbfe073879922ffed, // 0.85773, -0.5141 + 0x3feb090a58150200, 0xbfe11eb3541b4b22, // 0.84485, -0.535 + 0x3fea9b66290ea1a3, 0xbfe1c73b39ae68c8, // 0.83147, -0.55557 + 0x3fea29a7a0462782, 0xbfe26d054cdd12df, // 0.81758, -0.57581 + 0x3fe9b3e047f38741, 0xbfe30ff7fce17035, // 0.80321, -0.5957 + 0x3fe93a22499263fc, 0xbfe3affa292050b9, // 0.78835, -0.61523 + 0x3fe8bc806b151741, 0xbfe44cf325091dd6, // 0.77301, -0.63439 + 0x3fe83b0e0bff976e, 0xbfe4e6cabbe3e5e9, // 0.75721, -0.65317 + 0x3fe7b5df226aafb0, 0xbfe57d69348cec9f, // 0.74095, -0.67156 + 0x3fe72d0837efff97, 0xbfe610b7551d2cde, // 0.72425, -0.68954 + 0x3fe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // 0.70711, -0.70711 + 0x3fe610b7551d2cde, 0xbfe72d0837efff97, // 0.68954, -0.72425 + 0x3fe57d69348cec9f, 0xbfe7b5df226aafb0, // 0.67156, -0.74095 + 0x3fe4e6cabbe3e5e9, 0xbfe83b0e0bff976e, // 0.65317, -0.75721 + 0x3fe44cf325091dd6, 0xbfe8bc806b151741, // 0.63439, -0.77301 + 0x3fe3affa292050b9, 0xbfe93a22499263fc, // 0.61523, -0.78835 + 0x3fe30ff7fce17035, 0xbfe9b3e047f38741, // 0.5957, -0.80321 + 0x3fe26d054cdd12df, 0xbfea29a7a0462782, // 0.57581, -0.81758 + 0x3fe1c73b39ae68c8, 0xbfea9b66290ea1a3, // 0.55557, -0.83147 + 0x3fe11eb3541b4b22, 0xbfeb090a58150200, // 0.535, -0.84485 + 0x3fe073879922ffed, 0xbfeb728345196e3e, // 0.5141, -0.85773 + 0x3fdf8ba4dbf89aba, 0xbfebd7c0ac6f952a, // 0.4929, -0.87009 + 0x3fde2b5d3806f63b, 0xbfec38b2f180bdb1, // 0.4714, -0.88192 + 0x3fdcc66e9931c45d, 0xbfec954b213411f5, // 0.44961, -0.89322 + 0x3fdb5d1009e15cc0, 0xbfeced7af43cc773, // 0.42756, -0.90399 + 0x3fd9ef7943a8ed8a, 0xbfed4134d14dc93a, // 0.40524, -0.91421 + 0x3fd87de2a6aea963, 0xbfed906bcf328d46, // 0.38268, -0.92388 + 0x3fd7088530fa459e, 0xbfeddb13b6ccc23d, // 0.3599, -0.93299 + 0x3fd58f9a75ab1fdd, 0xbfee212104f686e5, // 0.33689, -0.94154 + 0x3fd4135c94176602, 0xbfee6288ec48e112, // 0.31368, -0.94953 + 0x3fd294062ed59f05, 0xbfee9f4156c62dda, // 0.29028, -0.95694 + 0x3fd111d262b1f677, 0xbfeed740e7684963, // 0.26671, -0.96378 + 0x3fcf19f97b215f1a, 0xbfef0a7efb9230d7, // 0.24298, -0.97003 + 0x3fcc0b826a7e4f63, 0xbfef38f3ac64e589, // 0.2191, -0.9757 + 0x3fc8f8b83c69a60a, 0xbfef6297cff75cb0, // 0.19509, -0.98079 + 0x3fc5e214448b3fc6, 0xbfef8764fa714ba9, // 0.17096, -0.98528 + 0x3fc2c8106e8e613a, 0xbfefa7557f08a517, // 0.14673, -0.98918 + 0x3fbf564e56a9730e, 0xbfefc26470e19fd3, // 0.12241, -0.99248 + 0x3fb917a6bc29b42c, 0xbfefd88da3d12526, //0.098017, -0.99518 + 0x3fb2d52092ce19f6, 0xbfefe9cdad01883a, //0.073565, -0.99729 + 0x3fa91f65f10dd814, 0xbfeff621e3796d7e, //0.049068, -0.9988' + 0x3f992155f7a3667e, 0xbfeffd886084cd0d, //0.024541, -0.9997 + + +}; +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F64_512) +const uint64_t twiddleCoefF64_rfft_512[512] = { + 0x0000000000000000, 0x3ff0000000000000, // 0, 1' + 0x3f8921d1fcdec784, 0x3fefff62169b92db, //0.012272, 0.99992' + 0x3f992155f7a3667e, 0x3feffd886084cd0d, //0.024541, 0.9997' + 0x3fa2d865759455cd, 0x3feffa72effef75d, //0.036807, 0.99932' + 0x3fa91f65f10dd814, 0x3feff621e3796d7e, //0.049068, 0.9988' + 0x3faf656e79f820e0, 0x3feff095658e71ad, //0.061321, 0.99812' + 0x3fb2d52092ce19f6, 0x3fefe9cdad01883a, //0.073565, 0.99729' + 0x3fb5f6d00a9aa419, 0x3fefe1cafcbd5b09, //0.085797, 0.99631' + 0x3fb917a6bc29b42c, 0x3fefd88da3d12526, //0.098017, 0.99518' + 0x3fbc3785c79ec2d5, 0x3fefce15fd6da67b, // 0.11022, 0.99391' + 0x3fbf564e56a9730e, 0x3fefc26470e19fd3, // 0.12241, 0.99248' + 0x3fc139f0cedaf576, 0x3fefb5797195d741, // 0.13458, 0.9909' + 0x3fc2c8106e8e613a, 0x3fefa7557f08a517, // 0.14673, 0.98918' + 0x3fc45576b1293e5a, 0x3fef97f924c9099b, // 0.15886, 0.9873' + 0x3fc5e214448b3fc6, 0x3fef8764fa714ba9, // 0.17096, 0.98528' + 0x3fc76dd9de50bf31, 0x3fef7599a3a12077, // 0.18304, 0.98311' + 0x3fc8f8b83c69a60a, 0x3fef6297cff75cb0, // 0.19509, 0.98079' + 0x3fca82a025b00451, 0x3fef4e603b0b2f2d, // 0.20711, 0.97832' + 0x3fcc0b826a7e4f63, 0x3fef38f3ac64e589, // 0.2191, 0.9757' + 0x3fcd934fe5454311, 0x3fef2252f7763ada, // 0.23106, 0.97294' + 0x3fcf19f97b215f1a, 0x3fef0a7efb9230d7, // 0.24298, 0.97003' + 0x3fd04fb80e37fdae, 0x3feef178a3e473c2, // 0.25487, 0.96698' + 0x3fd111d262b1f677, 0x3feed740e7684963, // 0.26671, 0.96378' + 0x3fd1d3443f4cdb3d, 0x3feebbd8c8df0b74, // 0.27852, 0.96043' + 0x3fd294062ed59f05, 0x3fee9f4156c62dda, // 0.29028, 0.95694' + 0x3fd35410c2e18152, 0x3fee817bab4cd10d, // 0.30201, 0.95331' + 0x3fd4135c94176602, 0x3fee6288ec48e112, // 0.31368, 0.94953' + 0x3fd4d1e24278e76a, 0x3fee426a4b2bc17e, // 0.32531, 0.94561' + 0x3fd58f9a75ab1fdd, 0x3fee212104f686e5, // 0.33689, 0.94154' + 0x3fd64c7ddd3f27c6, 0x3fedfeae622dbe2b, // 0.34842, 0.93734' + 0x3fd7088530fa459e, 0x3feddb13b6ccc23d, // 0.3599, 0.93299' + 0x3fd7c3a9311dcce7, 0x3fedb6526238a09b, // 0.37132, 0.92851' + 0x3fd87de2a6aea963, 0x3fed906bcf328d46, // 0.38268, 0.92388' + 0x3fd9372a63bc93d7, 0x3fed696173c9e68b, // 0.39399, 0.91911' + 0x3fd9ef7943a8ed8a, 0x3fed4134d14dc93a, // 0.40524, 0.91421' + 0x3fdaa6c82b6d3fc9, 0x3fed17e7743e35dc, // 0.41643, 0.90917' + 0x3fdb5d1009e15cc0, 0x3feced7af43cc773, // 0.42756, 0.90399' + 0x3fdc1249d8011ee7, 0x3fecc1f0f3fcfc5c, // 0.43862, 0.89867' + 0x3fdcc66e9931c45d, 0x3fec954b213411f5, // 0.44961, 0.89322' + 0x3fdd79775b86e389, 0x3fec678b3488739b, // 0.46054, 0.88764' + 0x3fde2b5d3806f63b, 0x3fec38b2f180bdb1, // 0.4714, 0.88192' + 0x3fdedc1952ef78d5, 0x3fec08c426725549, // 0.48218, 0.87607' + 0x3fdf8ba4dbf89aba, 0x3febd7c0ac6f952a, // 0.4929, 0.87009' + 0x3fe01cfc874c3eb7, 0x3feba5aa673590d2, // 0.50354, 0.86397' + 0x3fe073879922ffed, 0x3feb728345196e3e, // 0.5141, 0.85773' + 0x3fe0c9704d5d898f, 0x3feb3e4d3ef55712, // 0.52459, 0.85136' + 0x3fe11eb3541b4b22, 0x3feb090a58150200, // 0.535, 0.84485' + 0x3fe1734d63dedb49, 0x3fead2bc9e21d511, // 0.54532, 0.83822' + 0x3fe1c73b39ae68c8, 0x3fea9b66290ea1a3, // 0.55557, 0.83147' + 0x3fe21a799933eb58, 0x3fea63091b02fae2, // 0.56573, 0.82459' + 0x3fe26d054cdd12df, 0x3fea29a7a0462782, // 0.57581, 0.81758' + 0x3fe2bedb25faf3ea, 0x3fe9ef43ef29af94, // 0.5858, 0.81046' + 0x3fe30ff7fce17035, 0x3fe9b3e047f38741, // 0.5957, 0.80321' + 0x3fe36058b10659f3, 0x3fe9777ef4c7d742, // 0.60551, 0.79584' + 0x3fe3affa292050b9, 0x3fe93a22499263fc, // 0.61523, 0.78835' + 0x3fe3fed9534556d4, 0x3fe8fbcca3ef940d, // 0.62486, 0.78074' + 0x3fe44cf325091dd6, 0x3fe8bc806b151741, // 0.63439, 0.77301' + 0x3fe49a449b9b0938, 0x3fe87c400fba2ebf, // 0.64383, 0.76517' + 0x3fe4e6cabbe3e5e9, 0x3fe83b0e0bff976e, // 0.65317, 0.75721' + 0x3fe5328292a35596, 0x3fe7f8ece3571771, // 0.66242, 0.74914' + 0x3fe57d69348cec9f, 0x3fe7b5df226aafb0, // 0.67156, 0.74095' + 0x3fe5c77bbe65018c, 0x3fe771e75f037261, // 0.6806, 0.73265' + 0x3fe610b7551d2cde, 0x3fe72d0837efff97, // 0.68954, 0.72425' + 0x3fe6591925f0783e, 0x3fe6e74454eaa8ae, // 0.69838, 0.71573' + 0x3fe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // 0.70711, 0.70711' + 0x3fe6e74454eaa8ae, 0x3fe6591925f0783e, // 0.71573, 0.69838' + 0x3fe72d0837efff97, 0x3fe610b7551d2cde, // 0.72425, 0.68954' + 0x3fe771e75f037261, 0x3fe5c77bbe65018c, // 0.73265, 0.6806' + 0x3fe7b5df226aafb0, 0x3fe57d69348cec9f, // 0.74095, 0.67156' + 0x3fe7f8ece3571771, 0x3fe5328292a35596, // 0.74914, 0.66242' + 0x3fe83b0e0bff976e, 0x3fe4e6cabbe3e5e9, // 0.75721, 0.65317' + 0x3fe87c400fba2ebf, 0x3fe49a449b9b0938, // 0.76517, 0.64383' + 0x3fe8bc806b151741, 0x3fe44cf325091dd6, // 0.77301, 0.63439' + 0x3fe8fbcca3ef940d, 0x3fe3fed9534556d4, // 0.78074, 0.62486' + 0x3fe93a22499263fc, 0x3fe3affa292050b9, // 0.78835, 0.61523' + 0x3fe9777ef4c7d742, 0x3fe36058b10659f3, // 0.79584, 0.60551' + 0x3fe9b3e047f38741, 0x3fe30ff7fce17035, // 0.80321, 0.5957' + 0x3fe9ef43ef29af94, 0x3fe2bedb25faf3ea, // 0.81046, 0.5858' + 0x3fea29a7a0462782, 0x3fe26d054cdd12df, // 0.81758, 0.57581' + 0x3fea63091b02fae2, 0x3fe21a799933eb58, // 0.82459, 0.56573' + 0x3fea9b66290ea1a3, 0x3fe1c73b39ae68c8, // 0.83147, 0.55557' + 0x3fead2bc9e21d511, 0x3fe1734d63dedb49, // 0.83822, 0.54532' + 0x3feb090a58150200, 0x3fe11eb3541b4b22, // 0.84485, 0.535' + 0x3feb3e4d3ef55712, 0x3fe0c9704d5d898f, // 0.85136, 0.52459' + 0x3feb728345196e3e, 0x3fe073879922ffed, // 0.85773, 0.5141' + 0x3feba5aa673590d2, 0x3fe01cfc874c3eb7, // 0.86397, 0.50354' + 0x3febd7c0ac6f952a, 0x3fdf8ba4dbf89aba, // 0.87009, 0.4929' + 0x3fec08c426725549, 0x3fdedc1952ef78d5, // 0.87607, 0.48218' + 0x3fec38b2f180bdb1, 0x3fde2b5d3806f63b, // 0.88192, 0.4714' + 0x3fec678b3488739b, 0x3fdd79775b86e389, // 0.88764, 0.46054' + 0x3fec954b213411f5, 0x3fdcc66e9931c45d, // 0.89322, 0.44961' + 0x3fecc1f0f3fcfc5c, 0x3fdc1249d8011ee7, // 0.89867, 0.43862' + 0x3feced7af43cc773, 0x3fdb5d1009e15cc0, // 0.90399, 0.42756' + 0x3fed17e7743e35dc, 0x3fdaa6c82b6d3fc9, // 0.90917, 0.41643' + 0x3fed4134d14dc93a, 0x3fd9ef7943a8ed8a, // 0.91421, 0.40524' + 0x3fed696173c9e68b, 0x3fd9372a63bc93d7, // 0.91911, 0.39399' + 0x3fed906bcf328d46, 0x3fd87de2a6aea963, // 0.92388, 0.38268' + 0x3fedb6526238a09b, 0x3fd7c3a9311dcce7, // 0.92851, 0.37132' + 0x3feddb13b6ccc23d, 0x3fd7088530fa459e, // 0.93299, 0.3599' + 0x3fedfeae622dbe2b, 0x3fd64c7ddd3f27c6, // 0.93734, 0.34842' + 0x3fee212104f686e5, 0x3fd58f9a75ab1fdd, // 0.94154, 0.33689' + 0x3fee426a4b2bc17e, 0x3fd4d1e24278e76a, // 0.94561, 0.32531' + 0x3fee6288ec48e112, 0x3fd4135c94176602, // 0.94953, 0.31368' + 0x3fee817bab4cd10d, 0x3fd35410c2e18152, // 0.95331, 0.30201' + 0x3fee9f4156c62dda, 0x3fd294062ed59f05, // 0.95694, 0.29028' + 0x3feebbd8c8df0b74, 0x3fd1d3443f4cdb3d, // 0.96043, 0.27852' + 0x3feed740e7684963, 0x3fd111d262b1f677, // 0.96378, 0.26671' + 0x3feef178a3e473c2, 0x3fd04fb80e37fdae, // 0.96698, 0.25487' + 0x3fef0a7efb9230d7, 0x3fcf19f97b215f1a, // 0.97003, 0.24298' + 0x3fef2252f7763ada, 0x3fcd934fe5454311, // 0.97294, 0.23106' + 0x3fef38f3ac64e589, 0x3fcc0b826a7e4f63, // 0.9757, 0.2191' + 0x3fef4e603b0b2f2d, 0x3fca82a025b00451, // 0.97832, 0.20711' + 0x3fef6297cff75cb0, 0x3fc8f8b83c69a60a, // 0.98079, 0.19509' + 0x3fef7599a3a12077, 0x3fc76dd9de50bf31, // 0.98311, 0.18304' + 0x3fef8764fa714ba9, 0x3fc5e214448b3fc6, // 0.98528, 0.17096' + 0x3fef97f924c9099b, 0x3fc45576b1293e5a, // 0.9873, 0.15886' + 0x3fefa7557f08a517, 0x3fc2c8106e8e613a, // 0.98918, 0.14673' + 0x3fefb5797195d741, 0x3fc139f0cedaf576, // 0.9909, 0.13458' + 0x3fefc26470e19fd3, 0x3fbf564e56a9730e, // 0.99248, 0.12241' + 0x3fefce15fd6da67b, 0x3fbc3785c79ec2d5, // 0.99391, 0.11022' + 0x3fefd88da3d12526, 0x3fb917a6bc29b42c, // 0.99518, 0.098017' + 0x3fefe1cafcbd5b09, 0x3fb5f6d00a9aa419, // 0.99631, 0.085797' + 0x3fefe9cdad01883a, 0x3fb2d52092ce19f6, // 0.99729, 0.073565' + 0x3feff095658e71ad, 0x3faf656e79f820e0, // 0.99812, 0.061321' + 0x3feff621e3796d7e, 0x3fa91f65f10dd814, // 0.9988, 0.049068' + 0x3feffa72effef75d, 0x3fa2d865759455cd, // 0.99932, 0.036807' + 0x3feffd886084cd0d, 0x3f992155f7a3667e, // 0.9997, 0.024541' + 0x3fefff62169b92db, 0x3f8921d1fcdec784, // 0.99992, 0.012272' + 0x3ff0000000000000, 0x0000000000000000, // 1, 0' + 0x3fefff62169b92db, 0xbf8921d1fcdec784, // 0.99992,-0.012272' + 0x3feffd886084cd0d, 0xbf992155f7a3667e, // 0.9997,-0.024541' + 0x3feffa72effef75d, 0xbfa2d865759455cd, // 0.99932,-0.036807' + 0x3feff621e3796d7e, 0xbfa91f65f10dd814, // 0.9988,-0.049068' + 0x3feff095658e71ad, 0xbfaf656e79f820e0, // 0.99812,-0.061321' + 0x3fefe9cdad01883a, 0xbfb2d52092ce19f6, // 0.99729,-0.073565' + 0x3fefe1cafcbd5b09, 0xbfb5f6d00a9aa419, // 0.99631,-0.085797' + 0x3fefd88da3d12526, 0xbfb917a6bc29b42c, // 0.99518,-0.098017' + 0x3fefce15fd6da67b, 0xbfbc3785c79ec2d5, // 0.99391, -0.11022' + 0x3fefc26470e19fd3, 0xbfbf564e56a9730e, // 0.99248, -0.12241' + 0x3fefb5797195d741, 0xbfc139f0cedaf576, // 0.9909, -0.13458' + 0x3fefa7557f08a517, 0xbfc2c8106e8e613a, // 0.98918, -0.14673' + 0x3fef97f924c9099b, 0xbfc45576b1293e5a, // 0.9873, -0.15886' + 0x3fef8764fa714ba9, 0xbfc5e214448b3fc6, // 0.98528, -0.17096' + 0x3fef7599a3a12077, 0xbfc76dd9de50bf31, // 0.98311, -0.18304' + 0x3fef6297cff75cb0, 0xbfc8f8b83c69a60a, // 0.98079, -0.19509' + 0x3fef4e603b0b2f2d, 0xbfca82a025b00451, // 0.97832, -0.20711' + 0x3fef38f3ac64e589, 0xbfcc0b826a7e4f63, // 0.9757, -0.2191' + 0x3fef2252f7763ada, 0xbfcd934fe5454311, // 0.97294, -0.23106' + 0x3fef0a7efb9230d7, 0xbfcf19f97b215f1a, // 0.97003, -0.24298' + 0x3feef178a3e473c2, 0xbfd04fb80e37fdae, // 0.96698, -0.25487' + 0x3feed740e7684963, 0xbfd111d262b1f677, // 0.96378, -0.26671' + 0x3feebbd8c8df0b74, 0xbfd1d3443f4cdb3d, // 0.96043, -0.27852' + 0x3fee9f4156c62dda, 0xbfd294062ed59f05, // 0.95694, -0.29028' + 0x3fee817bab4cd10d, 0xbfd35410c2e18152, // 0.95331, -0.30201' + 0x3fee6288ec48e112, 0xbfd4135c94176602, // 0.94953, -0.31368' + 0x3fee426a4b2bc17e, 0xbfd4d1e24278e76a, // 0.94561, -0.32531' + 0x3fee212104f686e5, 0xbfd58f9a75ab1fdd, // 0.94154, -0.33689' + 0x3fedfeae622dbe2b, 0xbfd64c7ddd3f27c6, // 0.93734, -0.34842' + 0x3feddb13b6ccc23d, 0xbfd7088530fa459e, // 0.93299, -0.3599' + 0x3fedb6526238a09b, 0xbfd7c3a9311dcce7, // 0.92851, -0.37132' + 0x3fed906bcf328d46, 0xbfd87de2a6aea963, // 0.92388, -0.38268' + 0x3fed696173c9e68b, 0xbfd9372a63bc93d7, // 0.91911, -0.39399' + 0x3fed4134d14dc93a, 0xbfd9ef7943a8ed8a, // 0.91421, -0.40524' + 0x3fed17e7743e35dc, 0xbfdaa6c82b6d3fc9, // 0.90917, -0.41643' + 0x3feced7af43cc773, 0xbfdb5d1009e15cc0, // 0.90399, -0.42756' + 0x3fecc1f0f3fcfc5c, 0xbfdc1249d8011ee7, // 0.89867, -0.43862' + 0x3fec954b213411f5, 0xbfdcc66e9931c45d, // 0.89322, -0.44961' + 0x3fec678b3488739b, 0xbfdd79775b86e389, // 0.88764, -0.46054' + 0x3fec38b2f180bdb1, 0xbfde2b5d3806f63b, // 0.88192, -0.4714' + 0x3fec08c426725549, 0xbfdedc1952ef78d5, // 0.87607, -0.48218' + 0x3febd7c0ac6f952a, 0xbfdf8ba4dbf89aba, // 0.87009, -0.4929' + 0x3feba5aa673590d2, 0xbfe01cfc874c3eb7, // 0.86397, -0.50354' + 0x3feb728345196e3e, 0xbfe073879922ffed, // 0.85773, -0.5141' + 0x3feb3e4d3ef55712, 0xbfe0c9704d5d898f, // 0.85136, -0.52459' + 0x3feb090a58150200, 0xbfe11eb3541b4b22, // 0.84485, -0.535' + 0x3fead2bc9e21d511, 0xbfe1734d63dedb49, // 0.83822, -0.54532' + 0x3fea9b66290ea1a3, 0xbfe1c73b39ae68c8, // 0.83147, -0.55557' + 0x3fea63091b02fae2, 0xbfe21a799933eb58, // 0.82459, -0.56573' + 0x3fea29a7a0462782, 0xbfe26d054cdd12df, // 0.81758, -0.57581' + 0x3fe9ef43ef29af94, 0xbfe2bedb25faf3ea, // 0.81046, -0.5858' + 0x3fe9b3e047f38741, 0xbfe30ff7fce17035, // 0.80321, -0.5957' + 0x3fe9777ef4c7d742, 0xbfe36058b10659f3, // 0.79584, -0.60551' + 0x3fe93a22499263fc, 0xbfe3affa292050b9, // 0.78835, -0.61523' + 0x3fe8fbcca3ef940d, 0xbfe3fed9534556d4, // 0.78074, -0.62486' + 0x3fe8bc806b151741, 0xbfe44cf325091dd6, // 0.77301, -0.63439' + 0x3fe87c400fba2ebf, 0xbfe49a449b9b0938, // 0.76517, -0.64383' + 0x3fe83b0e0bff976e, 0xbfe4e6cabbe3e5e9, // 0.75721, -0.65317' + 0x3fe7f8ece3571771, 0xbfe5328292a35596, // 0.74914, -0.66242' + 0x3fe7b5df226aafb0, 0xbfe57d69348cec9f, // 0.74095, -0.67156' + 0x3fe771e75f037261, 0xbfe5c77bbe65018c, // 0.73265, -0.6806' + 0x3fe72d0837efff97, 0xbfe610b7551d2cde, // 0.72425, -0.68954' + 0x3fe6e74454eaa8ae, 0xbfe6591925f0783e, // 0.71573, -0.69838' + 0x3fe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // 0.70711, -0.70711' + 0x3fe6591925f0783e, 0xbfe6e74454eaa8ae, // 0.69838, -0.71573' + 0x3fe610b7551d2cde, 0xbfe72d0837efff97, // 0.68954, -0.72425' + 0x3fe5c77bbe65018c, 0xbfe771e75f037261, // 0.6806, -0.73265' + 0x3fe57d69348cec9f, 0xbfe7b5df226aafb0, // 0.67156, -0.74095' + 0x3fe5328292a35596, 0xbfe7f8ece3571771, // 0.66242, -0.74914' + 0x3fe4e6cabbe3e5e9, 0xbfe83b0e0bff976e, // 0.65317, -0.75721' + 0x3fe49a449b9b0938, 0xbfe87c400fba2ebf, // 0.64383, -0.76517' + 0x3fe44cf325091dd6, 0xbfe8bc806b151741, // 0.63439, -0.77301' + 0x3fe3fed9534556d4, 0xbfe8fbcca3ef940d, // 0.62486, -0.78074' + 0x3fe3affa292050b9, 0xbfe93a22499263fc, // 0.61523, -0.78835' + 0x3fe36058b10659f3, 0xbfe9777ef4c7d742, // 0.60551, -0.79584' + 0x3fe30ff7fce17035, 0xbfe9b3e047f38741, // 0.5957, -0.80321' + 0x3fe2bedb25faf3ea, 0xbfe9ef43ef29af94, // 0.5858, -0.81046' + 0x3fe26d054cdd12df, 0xbfea29a7a0462782, // 0.57581, -0.81758' + 0x3fe21a799933eb58, 0xbfea63091b02fae2, // 0.56573, -0.82459' + 0x3fe1c73b39ae68c8, 0xbfea9b66290ea1a3, // 0.55557, -0.83147' + 0x3fe1734d63dedb49, 0xbfead2bc9e21d511, // 0.54532, -0.83822' + 0x3fe11eb3541b4b22, 0xbfeb090a58150200, // 0.535, -0.84485' + 0x3fe0c9704d5d898f, 0xbfeb3e4d3ef55712, // 0.52459, -0.85136' + 0x3fe073879922ffed, 0xbfeb728345196e3e, // 0.5141, -0.85773' + 0x3fe01cfc874c3eb7, 0xbfeba5aa673590d2, // 0.50354, -0.86397' + 0x3fdf8ba4dbf89aba, 0xbfebd7c0ac6f952a, // 0.4929, -0.87009' + 0x3fdedc1952ef78d5, 0xbfec08c426725549, // 0.48218, -0.87607' + 0x3fde2b5d3806f63b, 0xbfec38b2f180bdb1, // 0.4714, -0.88192' + 0x3fdd79775b86e389, 0xbfec678b3488739b, // 0.46054, -0.88764' + 0x3fdcc66e9931c45d, 0xbfec954b213411f5, // 0.44961, -0.89322' + 0x3fdc1249d8011ee7, 0xbfecc1f0f3fcfc5c, // 0.43862, -0.89867' + 0x3fdb5d1009e15cc0, 0xbfeced7af43cc773, // 0.42756, -0.90399' + 0x3fdaa6c82b6d3fc9, 0xbfed17e7743e35dc, // 0.41643, -0.90917' + 0x3fd9ef7943a8ed8a, 0xbfed4134d14dc93a, // 0.40524, -0.91421' + 0x3fd9372a63bc93d7, 0xbfed696173c9e68b, // 0.39399, -0.91911' + 0x3fd87de2a6aea963, 0xbfed906bcf328d46, // 0.38268, -0.92388' + 0x3fd7c3a9311dcce7, 0xbfedb6526238a09b, // 0.37132, -0.92851' + 0x3fd7088530fa459e, 0xbfeddb13b6ccc23d, // 0.3599, -0.93299' + 0x3fd64c7ddd3f27c6, 0xbfedfeae622dbe2b, // 0.34842, -0.93734' + 0x3fd58f9a75ab1fdd, 0xbfee212104f686e5, // 0.33689, -0.94154' + 0x3fd4d1e24278e76a, 0xbfee426a4b2bc17e, // 0.32531, -0.94561' + 0x3fd4135c94176602, 0xbfee6288ec48e112, // 0.31368, -0.94953' + 0x3fd35410c2e18152, 0xbfee817bab4cd10d, // 0.30201, -0.95331' + 0x3fd294062ed59f05, 0xbfee9f4156c62dda, // 0.29028, -0.95694' + 0x3fd1d3443f4cdb3d, 0xbfeebbd8c8df0b74, // 0.27852, -0.96043' + 0x3fd111d262b1f677, 0xbfeed740e7684963, // 0.26671, -0.96378' + 0x3fd04fb80e37fdae, 0xbfeef178a3e473c2, // 0.25487, -0.96698' + 0x3fcf19f97b215f1a, 0xbfef0a7efb9230d7, // 0.24298, -0.97003' + 0x3fcd934fe5454311, 0xbfef2252f7763ada, // 0.23106, -0.97294' + 0x3fcc0b826a7e4f63, 0xbfef38f3ac64e589, // 0.2191, -0.9757' + 0x3fca82a025b00451, 0xbfef4e603b0b2f2d, // 0.20711, -0.97832' + 0x3fc8f8b83c69a60a, 0xbfef6297cff75cb0, // 0.19509, -0.98079' + 0x3fc76dd9de50bf31, 0xbfef7599a3a12077, // 0.18304, -0.98311' + 0x3fc5e214448b3fc6, 0xbfef8764fa714ba9, // 0.17096, -0.98528' + 0x3fc45576b1293e5a, 0xbfef97f924c9099b, // 0.15886, -0.9873' + 0x3fc2c8106e8e613a, 0xbfefa7557f08a517, // 0.14673, -0.98918' + 0x3fc139f0cedaf576, 0xbfefb5797195d741, // 0.13458, -0.9909' + 0x3fbf564e56a9730e, 0xbfefc26470e19fd3, // 0.12241, -0.99248' + 0x3fbc3785c79ec2d5, 0xbfefce15fd6da67b, // 0.11022, -0.99391' + 0x3fb917a6bc29b42c, 0xbfefd88da3d12526, //0.098017, -0.99518' + 0x3fb5f6d00a9aa419, 0xbfefe1cafcbd5b09, //0.085797, -0.99631' + 0x3fb2d52092ce19f6, 0xbfefe9cdad01883a, //0.073565, -0.99729' + 0x3faf656e79f820e0, 0xbfeff095658e71ad, //0.061321, -0.99812' + 0x3fa91f65f10dd814, 0xbfeff621e3796d7e, //0.049068, -0.9988' + 0x3fa2d865759455cd, 0xbfeffa72effef75d, //0.036807, -0.99932' + 0x3f992155f7a3667e, 0xbfeffd886084cd0d, //0.024541, -0.9997' + 0x3f8921d1fcdec784, 0xbfefff62169b92db, //0.012272, -0.99992' + + +}; +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F64_1024) +const uint64_t twiddleCoefF64_rfft_1024[1024] = { + 0x0000000000000000, 0x3ff0000000000000, // 0, 1' + 0x3f7921f0fe670071, 0x3fefffd8858e8a92, //0.0061359, 0.99998' + 0x3f8921d1fcdec784, 0x3fefff62169b92db, // 0.012272, 0.99992' + 0x3f92d936bbe30efd, 0x3feffe9cb44b51a1, // 0.018407, 0.99983' + 0x3f992155f7a3667e, 0x3feffd886084cd0d, // 0.024541, 0.9997' + 0x3f9f693731d1cf01, 0x3feffc251df1d3f8, // 0.030675, 0.99953' + 0x3fa2d865759455cd, 0x3feffa72effef75d, // 0.036807, 0.99932' + 0x3fa5fc00d290cd43, 0x3feff871dadb81df, // 0.042938, 0.99908' + 0x3fa91f65f10dd814, 0x3feff621e3796d7e, // 0.049068, 0.9988' + 0x3fac428d12c0d7e3, 0x3feff3830f8d575c, // 0.055195, 0.99848' + 0x3faf656e79f820e0, 0x3feff095658e71ad, // 0.061321, 0.99812' + 0x3fb1440134d709b2, 0x3fefed58ecb673c4, // 0.067444, 0.99772' + 0x3fb2d52092ce19f6, 0x3fefe9cdad01883a, // 0.073565, 0.99729' + 0x3fb4661179272096, 0x3fefe5f3af2e3940, // 0.079682, 0.99682' + 0x3fb5f6d00a9aa419, 0x3fefe1cafcbd5b09, // 0.085797, 0.99631' + 0x3fb787586a5d5b21, 0x3fefdd539ff1f456, // 0.091909, 0.99577' + 0x3fb917a6bc29b42c, 0x3fefd88da3d12526, // 0.098017, 0.99518' + 0x3fbaa7b724495c04, 0x3fefd37914220b84, // 0.10412, 0.99456' + 0x3fbc3785c79ec2d5, 0x3fefce15fd6da67b, // 0.11022, 0.99391' + 0x3fbdc70ecbae9fc8, 0x3fefc8646cfeb721, // 0.11632, 0.99321' + 0x3fbf564e56a9730e, 0x3fefc26470e19fd3, // 0.12241, 0.99248' + 0x3fc072a047ba831d, 0x3fefbc1617e44186, // 0.1285, 0.99171' + 0x3fc139f0cedaf576, 0x3fefb5797195d741, // 0.13458, 0.9909' + 0x3fc20116d4ec7bce, 0x3fefae8e8e46cfbb, // 0.14066, 0.99006' + 0x3fc2c8106e8e613a, 0x3fefa7557f08a517, // 0.14673, 0.98918' + 0x3fc38edbb0cd8d14, 0x3fef9fce55adb2c8, // 0.1528, 0.98826' + 0x3fc45576b1293e5a, 0x3fef97f924c9099b, // 0.15886, 0.9873' + 0x3fc51bdf8597c5f2, 0x3fef8fd5ffae41db, // 0.16491, 0.98631' + 0x3fc5e214448b3fc6, 0x3fef8764fa714ba9, // 0.17096, 0.98528' + 0x3fc6a81304f64ab2, 0x3fef7ea629e63d6e, // 0.177, 0.98421' + 0x3fc76dd9de50bf31, 0x3fef7599a3a12077, // 0.18304, 0.98311' + 0x3fc83366e89c64c5, 0x3fef6c3f7df5bbb7, // 0.18907, 0.98196' + 0x3fc8f8b83c69a60a, 0x3fef6297cff75cb0, // 0.19509, 0.98079' + 0x3fc9bdcbf2dc4366, 0x3fef58a2b1789e84, // 0.2011, 0.97957' + 0x3fca82a025b00451, 0x3fef4e603b0b2f2d, // 0.20711, 0.97832' + 0x3fcb4732ef3d6722, 0x3fef43d085ff92dd, // 0.21311, 0.97703' + 0x3fcc0b826a7e4f63, 0x3fef38f3ac64e589, // 0.2191, 0.9757' + 0x3fcccf8cb312b286, 0x3fef2dc9c9089a9d, // 0.22508, 0.97434' + 0x3fcd934fe5454311, 0x3fef2252f7763ada, // 0.23106, 0.97294' + 0x3fce56ca1e101a1b, 0x3fef168f53f7205d, // 0.23702, 0.9715' + 0x3fcf19f97b215f1a, 0x3fef0a7efb9230d7, // 0.24298, 0.97003' + 0x3fcfdcdc1adfedf8, 0x3feefe220c0b95ec, // 0.24893, 0.96852' + 0x3fd04fb80e37fdae, 0x3feef178a3e473c2, // 0.25487, 0.96698' + 0x3fd0b0d9cfdbdb90, 0x3feee482e25a9dbc, // 0.26079, 0.96539' + 0x3fd111d262b1f677, 0x3feed740e7684963, // 0.26671, 0.96378' + 0x3fd172a0d7765177, 0x3feec9b2d3c3bf84, // 0.27262, 0.96212' + 0x3fd1d3443f4cdb3d, 0x3feebbd8c8df0b74, // 0.27852, 0.96043' + 0x3fd233bbabc3bb72, 0x3feeadb2e8e7a88e, // 0.28441, 0.9587' + 0x3fd294062ed59f05, 0x3fee9f4156c62dda, // 0.29028, 0.95694' + 0x3fd2f422daec0386, 0x3fee9084361df7f3, // 0.29615, 0.95514' + 0x3fd35410c2e18152, 0x3fee817bab4cd10d, // 0.30201, 0.95331' + 0x3fd3b3cefa0414b7, 0x3fee7227db6a9744, // 0.30785, 0.95144' + 0x3fd4135c94176602, 0x3fee6288ec48e112, // 0.31368, 0.94953' + 0x3fd472b8a5571054, 0x3fee529f04729ffc, // 0.3195, 0.94759' + 0x3fd4d1e24278e76a, 0x3fee426a4b2bc17e, // 0.32531, 0.94561' + 0x3fd530d880af3c24, 0x3fee31eae870ce25, // 0.33111, 0.94359' + 0x3fd58f9a75ab1fdd, 0x3fee212104f686e5, // 0.33689, 0.94154' + 0x3fd5ee27379ea693, 0x3fee100cca2980ac, // 0.34266, 0.93946' + 0x3fd64c7ddd3f27c6, 0x3fedfeae622dbe2b, // 0.34842, 0.93734' + 0x3fd6aa9d7dc77e16, 0x3feded05f7de47da, // 0.35416, 0.93518' + 0x3fd7088530fa459e, 0x3feddb13b6ccc23d, // 0.3599, 0.93299' + 0x3fd766340f2418f6, 0x3fedc8d7cb410260, // 0.36561, 0.93077' + 0x3fd7c3a9311dcce7, 0x3fedb6526238a09b, // 0.37132, 0.92851' + 0x3fd820e3b04eaac4, 0x3feda383a9668988, // 0.37701, 0.92621' + 0x3fd87de2a6aea963, 0x3fed906bcf328d46, // 0.38268, 0.92388' + 0x3fd8daa52ec8a4af, 0x3fed7d0b02b8ecf9, // 0.38835, 0.92151' + 0x3fd9372a63bc93d7, 0x3fed696173c9e68b, // 0.39399, 0.91911' + 0x3fd993716141bdfe, 0x3fed556f52e93eb1, // 0.39962, 0.91668' + 0x3fd9ef7943a8ed8a, 0x3fed4134d14dc93a, // 0.40524, 0.91421' + 0x3fda4b4127dea1e4, 0x3fed2cb220e0ef9f, // 0.41084, 0.91171' + 0x3fdaa6c82b6d3fc9, 0x3fed17e7743e35dc, // 0.41643, 0.90917' + 0x3fdb020d6c7f4009, 0x3fed02d4feb2bd92, // 0.422, 0.9066' + 0x3fdb5d1009e15cc0, 0x3feced7af43cc773, // 0.42756, 0.90399' + 0x3fdbb7cf2304bd01, 0x3fecd7d9898b32f6, // 0.43309, 0.90135' + 0x3fdc1249d8011ee7, 0x3fecc1f0f3fcfc5c, // 0.43862, 0.89867' + 0x3fdc6c7f4997000a, 0x3fecabc169a0b901, // 0.44412, 0.89597' + 0x3fdcc66e9931c45d, 0x3fec954b213411f5, // 0.44961, 0.89322' + 0x3fdd2016e8e9db5b, 0x3fec7e8e52233cf3, // 0.45508, 0.89045' + 0x3fdd79775b86e389, 0x3fec678b3488739b, // 0.46054, 0.88764' + 0x3fddd28f1481cc58, 0x3fec5042012b6907, // 0.46598, 0.8848' + 0x3fde2b5d3806f63b, 0x3fec38b2f180bdb1, // 0.4714, 0.88192' + 0x3fde83e0eaf85113, 0x3fec20de3fa971b0, // 0.4768, 0.87901' + 0x3fdedc1952ef78d5, 0x3fec08c426725549, // 0.48218, 0.87607' + 0x3fdf3405963fd068, 0x3febf064e15377dd, // 0.48755, 0.87309' + 0x3fdf8ba4dbf89aba, 0x3febd7c0ac6f952a, // 0.4929, 0.87009' + 0x3fdfe2f64be7120f, 0x3febbed7c49380ea, // 0.49823, 0.86705' + 0x3fe01cfc874c3eb7, 0x3feba5aa673590d2, // 0.50354, 0.86397' + 0x3fe0485626ae221a, 0x3feb8c38d27504e9, // 0.50883, 0.86087' + 0x3fe073879922ffed, 0x3feb728345196e3e, // 0.5141, 0.85773' + 0x3fe09e907417c5e1, 0x3feb5889fe921405, // 0.51936, 0.85456' + 0x3fe0c9704d5d898f, 0x3feb3e4d3ef55712, // 0.52459, 0.85136' + 0x3fe0f426bb2a8e7d, 0x3feb23cd470013b4, // 0.5298, 0.84812' + 0x3fe11eb3541b4b22, 0x3feb090a58150200, // 0.535, 0.84485' + 0x3fe14915af336ceb, 0x3feaee04b43c1474, // 0.54017, 0.84155' + 0x3fe1734d63dedb49, 0x3fead2bc9e21d511, // 0.54532, 0.83822' + 0x3fe19d5a09f2b9b8, 0x3feab7325916c0d4, // 0.55046, 0.83486' + 0x3fe1c73b39ae68c8, 0x3fea9b66290ea1a3, // 0.55557, 0.83147' + 0x3fe1f0f08bbc861b, 0x3fea7f58529fe69d, // 0.56066, 0.82805' + 0x3fe21a799933eb58, 0x3fea63091b02fae2, // 0.56573, 0.82459' + 0x3fe243d5fb98ac1f, 0x3fea4678c8119ac8, // 0.57078, 0.8211' + 0x3fe26d054cdd12df, 0x3fea29a7a0462782, // 0.57581, 0.81758' + 0x3fe2960727629ca8, 0x3fea0c95eabaf937, // 0.58081, 0.81404' + 0x3fe2bedb25faf3ea, 0x3fe9ef43ef29af94, // 0.5858, 0.81046' + 0x3fe2e780e3e8ea16, 0x3fe9d1b1f5ea80d6, // 0.59076, 0.80685' + 0x3fe30ff7fce17035, 0x3fe9b3e047f38741, // 0.5957, 0.80321' + 0x3fe338400d0c8e57, 0x3fe995cf2ed80d22, // 0.60062, 0.79954' + 0x3fe36058b10659f3, 0x3fe9777ef4c7d742, // 0.60551, 0.79584' + 0x3fe3884185dfeb22, 0x3fe958efe48e6dd7, // 0.61038, 0.79211' + 0x3fe3affa292050b9, 0x3fe93a22499263fc, // 0.61523, 0.78835' + 0x3fe3d78238c58343, 0x3fe91b166fd49da2, // 0.62006, 0.78456' + 0x3fe3fed9534556d4, 0x3fe8fbcca3ef940d, // 0.62486, 0.78074' + 0x3fe425ff178e6bb1, 0x3fe8dc45331698cc, // 0.62964, 0.77689' + 0x3fe44cf325091dd6, 0x3fe8bc806b151741, // 0.63439, 0.77301' + 0x3fe473b51b987347, 0x3fe89c7e9a4dd4ab, // 0.63912, 0.7691' + 0x3fe49a449b9b0938, 0x3fe87c400fba2ebf, // 0.64383, 0.76517' + 0x3fe4c0a145ec0004, 0x3fe85bc51ae958cc, // 0.64851, 0.7612' + 0x3fe4e6cabbe3e5e9, 0x3fe83b0e0bff976e, // 0.65317, 0.75721' + 0x3fe50cc09f59a09b, 0x3fe81a1b33b57acc, // 0.65781, 0.75319' + 0x3fe5328292a35596, 0x3fe7f8ece3571771, // 0.66242, 0.74914' + 0x3fe5581038975137, 0x3fe7d7836cc33db2, // 0.667, 0.74506' + 0x3fe57d69348cec9f, 0x3fe7b5df226aafb0, // 0.67156, 0.74095' + 0x3fe5a28d2a5d7250, 0x3fe79400574f55e4, // 0.67609, 0.73682' + 0x3fe5c77bbe65018c, 0x3fe771e75f037261, // 0.6806, 0.73265' + 0x3fe5ec3495837074, 0x3fe74f948da8d28d, // 0.68508, 0.72846' + 0x3fe610b7551d2cde, 0x3fe72d0837efff97, // 0.68954, 0.72425' + 0x3fe63503a31c1be8, 0x3fe70a42b3176d7a, // 0.69397, 0.72' + 0x3fe6591925f0783e, 0x3fe6e74454eaa8ae, // 0.69838, 0.71573' + 0x3fe67cf78491af10, 0x3fe6c40d73c18275, // 0.70275, 0.71143' + 0x3fe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // 0.70711, 0.70711' + 0x3fe6c40d73c18275, 0x3fe67cf78491af10, // 0.71143, 0.70275' + 0x3fe6e74454eaa8ae, 0x3fe6591925f0783e, // 0.71573, 0.69838' + 0x3fe70a42b3176d7a, 0x3fe63503a31c1be8, // 0.72, 0.69397' + 0x3fe72d0837efff97, 0x3fe610b7551d2cde, // 0.72425, 0.68954' + 0x3fe74f948da8d28d, 0x3fe5ec3495837074, // 0.72846, 0.68508' + 0x3fe771e75f037261, 0x3fe5c77bbe65018c, // 0.73265, 0.6806' + 0x3fe79400574f55e4, 0x3fe5a28d2a5d7250, // 0.73682, 0.67609' + 0x3fe7b5df226aafb0, 0x3fe57d69348cec9f, // 0.74095, 0.67156' + 0x3fe7d7836cc33db2, 0x3fe5581038975137, // 0.74506, 0.667' + 0x3fe7f8ece3571771, 0x3fe5328292a35596, // 0.74914, 0.66242' + 0x3fe81a1b33b57acc, 0x3fe50cc09f59a09b, // 0.75319, 0.65781' + 0x3fe83b0e0bff976e, 0x3fe4e6cabbe3e5e9, // 0.75721, 0.65317' + 0x3fe85bc51ae958cc, 0x3fe4c0a145ec0004, // 0.7612, 0.64851' + 0x3fe87c400fba2ebf, 0x3fe49a449b9b0938, // 0.76517, 0.64383' + 0x3fe89c7e9a4dd4ab, 0x3fe473b51b987347, // 0.7691, 0.63912' + 0x3fe8bc806b151741, 0x3fe44cf325091dd6, // 0.77301, 0.63439' + 0x3fe8dc45331698cc, 0x3fe425ff178e6bb1, // 0.77689, 0.62964' + 0x3fe8fbcca3ef940d, 0x3fe3fed9534556d4, // 0.78074, 0.62486' + 0x3fe91b166fd49da2, 0x3fe3d78238c58343, // 0.78456, 0.62006' + 0x3fe93a22499263fc, 0x3fe3affa292050b9, // 0.78835, 0.61523' + 0x3fe958efe48e6dd7, 0x3fe3884185dfeb22, // 0.79211, 0.61038' + 0x3fe9777ef4c7d742, 0x3fe36058b10659f3, // 0.79584, 0.60551' + 0x3fe995cf2ed80d22, 0x3fe338400d0c8e57, // 0.79954, 0.60062' + 0x3fe9b3e047f38741, 0x3fe30ff7fce17035, // 0.80321, 0.5957' + 0x3fe9d1b1f5ea80d6, 0x3fe2e780e3e8ea16, // 0.80685, 0.59076' + 0x3fe9ef43ef29af94, 0x3fe2bedb25faf3ea, // 0.81046, 0.5858' + 0x3fea0c95eabaf937, 0x3fe2960727629ca8, // 0.81404, 0.58081' + 0x3fea29a7a0462782, 0x3fe26d054cdd12df, // 0.81758, 0.57581' + 0x3fea4678c8119ac8, 0x3fe243d5fb98ac1f, // 0.8211, 0.57078' + 0x3fea63091b02fae2, 0x3fe21a799933eb58, // 0.82459, 0.56573' + 0x3fea7f58529fe69d, 0x3fe1f0f08bbc861b, // 0.82805, 0.56066' + 0x3fea9b66290ea1a3, 0x3fe1c73b39ae68c8, // 0.83147, 0.55557' + 0x3feab7325916c0d4, 0x3fe19d5a09f2b9b8, // 0.83486, 0.55046' + 0x3fead2bc9e21d511, 0x3fe1734d63dedb49, // 0.83822, 0.54532' + 0x3feaee04b43c1474, 0x3fe14915af336ceb, // 0.84155, 0.54017' + 0x3feb090a58150200, 0x3fe11eb3541b4b22, // 0.84485, 0.535' + 0x3feb23cd470013b4, 0x3fe0f426bb2a8e7d, // 0.84812, 0.5298' + 0x3feb3e4d3ef55712, 0x3fe0c9704d5d898f, // 0.85136, 0.52459' + 0x3feb5889fe921405, 0x3fe09e907417c5e1, // 0.85456, 0.51936' + 0x3feb728345196e3e, 0x3fe073879922ffed, // 0.85773, 0.5141' + 0x3feb8c38d27504e9, 0x3fe0485626ae221a, // 0.86087, 0.50883' + 0x3feba5aa673590d2, 0x3fe01cfc874c3eb7, // 0.86397, 0.50354' + 0x3febbed7c49380ea, 0x3fdfe2f64be7120f, // 0.86705, 0.49823' + 0x3febd7c0ac6f952a, 0x3fdf8ba4dbf89aba, // 0.87009, 0.4929' + 0x3febf064e15377dd, 0x3fdf3405963fd068, // 0.87309, 0.48755' + 0x3fec08c426725549, 0x3fdedc1952ef78d5, // 0.87607, 0.48218' + 0x3fec20de3fa971b0, 0x3fde83e0eaf85113, // 0.87901, 0.4768' + 0x3fec38b2f180bdb1, 0x3fde2b5d3806f63b, // 0.88192, 0.4714' + 0x3fec5042012b6907, 0x3fddd28f1481cc58, // 0.8848, 0.46598' + 0x3fec678b3488739b, 0x3fdd79775b86e389, // 0.88764, 0.46054' + 0x3fec7e8e52233cf3, 0x3fdd2016e8e9db5b, // 0.89045, 0.45508' + 0x3fec954b213411f5, 0x3fdcc66e9931c45d, // 0.89322, 0.44961' + 0x3fecabc169a0b901, 0x3fdc6c7f4997000a, // 0.89597, 0.44412' + 0x3fecc1f0f3fcfc5c, 0x3fdc1249d8011ee7, // 0.89867, 0.43862' + 0x3fecd7d9898b32f6, 0x3fdbb7cf2304bd01, // 0.90135, 0.43309' + 0x3feced7af43cc773, 0x3fdb5d1009e15cc0, // 0.90399, 0.42756' + 0x3fed02d4feb2bd92, 0x3fdb020d6c7f4009, // 0.9066, 0.422' + 0x3fed17e7743e35dc, 0x3fdaa6c82b6d3fc9, // 0.90917, 0.41643' + 0x3fed2cb220e0ef9f, 0x3fda4b4127dea1e4, // 0.91171, 0.41084' + 0x3fed4134d14dc93a, 0x3fd9ef7943a8ed8a, // 0.91421, 0.40524' + 0x3fed556f52e93eb1, 0x3fd993716141bdfe, // 0.91668, 0.39962' + 0x3fed696173c9e68b, 0x3fd9372a63bc93d7, // 0.91911, 0.39399' + 0x3fed7d0b02b8ecf9, 0x3fd8daa52ec8a4af, // 0.92151, 0.38835' + 0x3fed906bcf328d46, 0x3fd87de2a6aea963, // 0.92388, 0.38268' + 0x3feda383a9668988, 0x3fd820e3b04eaac4, // 0.92621, 0.37701' + 0x3fedb6526238a09b, 0x3fd7c3a9311dcce7, // 0.92851, 0.37132' + 0x3fedc8d7cb410260, 0x3fd766340f2418f6, // 0.93077, 0.36561' + 0x3feddb13b6ccc23d, 0x3fd7088530fa459e, // 0.93299, 0.3599' + 0x3feded05f7de47da, 0x3fd6aa9d7dc77e16, // 0.93518, 0.35416' + 0x3fedfeae622dbe2b, 0x3fd64c7ddd3f27c6, // 0.93734, 0.34842' + 0x3fee100cca2980ac, 0x3fd5ee27379ea693, // 0.93946, 0.34266' + 0x3fee212104f686e5, 0x3fd58f9a75ab1fdd, // 0.94154, 0.33689' + 0x3fee31eae870ce25, 0x3fd530d880af3c24, // 0.94359, 0.33111' + 0x3fee426a4b2bc17e, 0x3fd4d1e24278e76a, // 0.94561, 0.32531' + 0x3fee529f04729ffc, 0x3fd472b8a5571054, // 0.94759, 0.3195' + 0x3fee6288ec48e112, 0x3fd4135c94176602, // 0.94953, 0.31368' + 0x3fee7227db6a9744, 0x3fd3b3cefa0414b7, // 0.95144, 0.30785' + 0x3fee817bab4cd10d, 0x3fd35410c2e18152, // 0.95331, 0.30201' + 0x3fee9084361df7f3, 0x3fd2f422daec0386, // 0.95514, 0.29615' + 0x3fee9f4156c62dda, 0x3fd294062ed59f05, // 0.95694, 0.29028' + 0x3feeadb2e8e7a88e, 0x3fd233bbabc3bb72, // 0.9587, 0.28441' + 0x3feebbd8c8df0b74, 0x3fd1d3443f4cdb3d, // 0.96043, 0.27852' + 0x3feec9b2d3c3bf84, 0x3fd172a0d7765177, // 0.96212, 0.27262' + 0x3feed740e7684963, 0x3fd111d262b1f677, // 0.96378, 0.26671' + 0x3feee482e25a9dbc, 0x3fd0b0d9cfdbdb90, // 0.96539, 0.26079' + 0x3feef178a3e473c2, 0x3fd04fb80e37fdae, // 0.96698, 0.25487' + 0x3feefe220c0b95ec, 0x3fcfdcdc1adfedf8, // 0.96852, 0.24893' + 0x3fef0a7efb9230d7, 0x3fcf19f97b215f1a, // 0.97003, 0.24298' + 0x3fef168f53f7205d, 0x3fce56ca1e101a1b, // 0.9715, 0.23702' + 0x3fef2252f7763ada, 0x3fcd934fe5454311, // 0.97294, 0.23106' + 0x3fef2dc9c9089a9d, 0x3fcccf8cb312b286, // 0.97434, 0.22508' + 0x3fef38f3ac64e589, 0x3fcc0b826a7e4f63, // 0.9757, 0.2191' + 0x3fef43d085ff92dd, 0x3fcb4732ef3d6722, // 0.97703, 0.21311' + 0x3fef4e603b0b2f2d, 0x3fca82a025b00451, // 0.97832, 0.20711' + 0x3fef58a2b1789e84, 0x3fc9bdcbf2dc4366, // 0.97957, 0.2011' + 0x3fef6297cff75cb0, 0x3fc8f8b83c69a60a, // 0.98079, 0.19509' + 0x3fef6c3f7df5bbb7, 0x3fc83366e89c64c5, // 0.98196, 0.18907' + 0x3fef7599a3a12077, 0x3fc76dd9de50bf31, // 0.98311, 0.18304' + 0x3fef7ea629e63d6e, 0x3fc6a81304f64ab2, // 0.98421, 0.177' + 0x3fef8764fa714ba9, 0x3fc5e214448b3fc6, // 0.98528, 0.17096' + 0x3fef8fd5ffae41db, 0x3fc51bdf8597c5f2, // 0.98631, 0.16491' + 0x3fef97f924c9099b, 0x3fc45576b1293e5a, // 0.9873, 0.15886' + 0x3fef9fce55adb2c8, 0x3fc38edbb0cd8d14, // 0.98826, 0.1528' + 0x3fefa7557f08a517, 0x3fc2c8106e8e613a, // 0.98918, 0.14673' + 0x3fefae8e8e46cfbb, 0x3fc20116d4ec7bce, // 0.99006, 0.14066' + 0x3fefb5797195d741, 0x3fc139f0cedaf576, // 0.9909, 0.13458' + 0x3fefbc1617e44186, 0x3fc072a047ba831d, // 0.99171, 0.1285' + 0x3fefc26470e19fd3, 0x3fbf564e56a9730e, // 0.99248, 0.12241' + 0x3fefc8646cfeb721, 0x3fbdc70ecbae9fc8, // 0.99321, 0.11632' + 0x3fefce15fd6da67b, 0x3fbc3785c79ec2d5, // 0.99391, 0.11022' + 0x3fefd37914220b84, 0x3fbaa7b724495c04, // 0.99456, 0.10412' + 0x3fefd88da3d12526, 0x3fb917a6bc29b42c, // 0.99518, 0.098017' + 0x3fefdd539ff1f456, 0x3fb787586a5d5b21, // 0.99577, 0.091909' + 0x3fefe1cafcbd5b09, 0x3fb5f6d00a9aa419, // 0.99631, 0.085797' + 0x3fefe5f3af2e3940, 0x3fb4661179272096, // 0.99682, 0.079682' + 0x3fefe9cdad01883a, 0x3fb2d52092ce19f6, // 0.99729, 0.073565' + 0x3fefed58ecb673c4, 0x3fb1440134d709b2, // 0.99772, 0.067444' + 0x3feff095658e71ad, 0x3faf656e79f820e0, // 0.99812, 0.061321' + 0x3feff3830f8d575c, 0x3fac428d12c0d7e3, // 0.99848, 0.055195' + 0x3feff621e3796d7e, 0x3fa91f65f10dd814, // 0.9988, 0.049068' + 0x3feff871dadb81df, 0x3fa5fc00d290cd43, // 0.99908, 0.042938' + 0x3feffa72effef75d, 0x3fa2d865759455cd, // 0.99932, 0.036807' + 0x3feffc251df1d3f8, 0x3f9f693731d1cf01, // 0.99953, 0.030675' + 0x3feffd886084cd0d, 0x3f992155f7a3667e, // 0.9997, 0.024541' + 0x3feffe9cb44b51a1, 0x3f92d936bbe30efd, // 0.99983, 0.018407' + 0x3fefff62169b92db, 0x3f8921d1fcdec784, // 0.99992, 0.012272' + 0x3fefffd8858e8a92, 0x3f7921f0fe670071, // 0.99998, 0.0061359' + 0x3ff0000000000000, 0x0000000000000000, // 1, 0' + 0x3fefffd8858e8a92, 0xbf7921f0fe670071, // 0.99998,-0.0061359' + 0x3fefff62169b92db, 0xbf8921d1fcdec784, // 0.99992, -0.012272' + 0x3feffe9cb44b51a1, 0xbf92d936bbe30efd, // 0.99983, -0.018407' + 0x3feffd886084cd0d, 0xbf992155f7a3667e, // 0.9997, -0.024541' + 0x3feffc251df1d3f8, 0xbf9f693731d1cf01, // 0.99953, -0.030675' + 0x3feffa72effef75d, 0xbfa2d865759455cd, // 0.99932, -0.036807' + 0x3feff871dadb81df, 0xbfa5fc00d290cd43, // 0.99908, -0.042938' + 0x3feff621e3796d7e, 0xbfa91f65f10dd814, // 0.9988, -0.049068' + 0x3feff3830f8d575c, 0xbfac428d12c0d7e3, // 0.99848, -0.055195' + 0x3feff095658e71ad, 0xbfaf656e79f820e0, // 0.99812, -0.061321' + 0x3fefed58ecb673c4, 0xbfb1440134d709b2, // 0.99772, -0.067444' + 0x3fefe9cdad01883a, 0xbfb2d52092ce19f6, // 0.99729, -0.073565' + 0x3fefe5f3af2e3940, 0xbfb4661179272096, // 0.99682, -0.079682' + 0x3fefe1cafcbd5b09, 0xbfb5f6d00a9aa419, // 0.99631, -0.085797' + 0x3fefdd539ff1f456, 0xbfb787586a5d5b21, // 0.99577, -0.091909' + 0x3fefd88da3d12526, 0xbfb917a6bc29b42c, // 0.99518, -0.098017' + 0x3fefd37914220b84, 0xbfbaa7b724495c04, // 0.99456, -0.10412' + 0x3fefce15fd6da67b, 0xbfbc3785c79ec2d5, // 0.99391, -0.11022' + 0x3fefc8646cfeb721, 0xbfbdc70ecbae9fc8, // 0.99321, -0.11632' + 0x3fefc26470e19fd3, 0xbfbf564e56a9730e, // 0.99248, -0.12241' + 0x3fefbc1617e44186, 0xbfc072a047ba831d, // 0.99171, -0.1285' + 0x3fefb5797195d741, 0xbfc139f0cedaf576, // 0.9909, -0.13458' + 0x3fefae8e8e46cfbb, 0xbfc20116d4ec7bce, // 0.99006, -0.14066' + 0x3fefa7557f08a517, 0xbfc2c8106e8e613a, // 0.98918, -0.14673' + 0x3fef9fce55adb2c8, 0xbfc38edbb0cd8d14, // 0.98826, -0.1528' + 0x3fef97f924c9099b, 0xbfc45576b1293e5a, // 0.9873, -0.15886' + 0x3fef8fd5ffae41db, 0xbfc51bdf8597c5f2, // 0.98631, -0.16491' + 0x3fef8764fa714ba9, 0xbfc5e214448b3fc6, // 0.98528, -0.17096' + 0x3fef7ea629e63d6e, 0xbfc6a81304f64ab2, // 0.98421, -0.177' + 0x3fef7599a3a12077, 0xbfc76dd9de50bf31, // 0.98311, -0.18304' + 0x3fef6c3f7df5bbb7, 0xbfc83366e89c64c5, // 0.98196, -0.18907' + 0x3fef6297cff75cb0, 0xbfc8f8b83c69a60a, // 0.98079, -0.19509' + 0x3fef58a2b1789e84, 0xbfc9bdcbf2dc4366, // 0.97957, -0.2011' + 0x3fef4e603b0b2f2d, 0xbfca82a025b00451, // 0.97832, -0.20711' + 0x3fef43d085ff92dd, 0xbfcb4732ef3d6722, // 0.97703, -0.21311' + 0x3fef38f3ac64e589, 0xbfcc0b826a7e4f63, // 0.9757, -0.2191' + 0x3fef2dc9c9089a9d, 0xbfcccf8cb312b286, // 0.97434, -0.22508' + 0x3fef2252f7763ada, 0xbfcd934fe5454311, // 0.97294, -0.23106' + 0x3fef168f53f7205d, 0xbfce56ca1e101a1b, // 0.9715, -0.23702' + 0x3fef0a7efb9230d7, 0xbfcf19f97b215f1a, // 0.97003, -0.24298' + 0x3feefe220c0b95ec, 0xbfcfdcdc1adfedf8, // 0.96852, -0.24893' + 0x3feef178a3e473c2, 0xbfd04fb80e37fdae, // 0.96698, -0.25487' + 0x3feee482e25a9dbc, 0xbfd0b0d9cfdbdb90, // 0.96539, -0.26079' + 0x3feed740e7684963, 0xbfd111d262b1f677, // 0.96378, -0.26671' + 0x3feec9b2d3c3bf84, 0xbfd172a0d7765177, // 0.96212, -0.27262' + 0x3feebbd8c8df0b74, 0xbfd1d3443f4cdb3d, // 0.96043, -0.27852' + 0x3feeadb2e8e7a88e, 0xbfd233bbabc3bb72, // 0.9587, -0.28441' + 0x3fee9f4156c62dda, 0xbfd294062ed59f05, // 0.95694, -0.29028' + 0x3fee9084361df7f3, 0xbfd2f422daec0386, // 0.95514, -0.29615' + 0x3fee817bab4cd10d, 0xbfd35410c2e18152, // 0.95331, -0.30201' + 0x3fee7227db6a9744, 0xbfd3b3cefa0414b7, // 0.95144, -0.30785' + 0x3fee6288ec48e112, 0xbfd4135c94176602, // 0.94953, -0.31368' + 0x3fee529f04729ffc, 0xbfd472b8a5571054, // 0.94759, -0.3195' + 0x3fee426a4b2bc17e, 0xbfd4d1e24278e76a, // 0.94561, -0.32531' + 0x3fee31eae870ce25, 0xbfd530d880af3c24, // 0.94359, -0.33111' + 0x3fee212104f686e5, 0xbfd58f9a75ab1fdd, // 0.94154, -0.33689' + 0x3fee100cca2980ac, 0xbfd5ee27379ea693, // 0.93946, -0.34266' + 0x3fedfeae622dbe2b, 0xbfd64c7ddd3f27c6, // 0.93734, -0.34842' + 0x3feded05f7de47da, 0xbfd6aa9d7dc77e16, // 0.93518, -0.35416' + 0x3feddb13b6ccc23d, 0xbfd7088530fa459e, // 0.93299, -0.3599' + 0x3fedc8d7cb410260, 0xbfd766340f2418f6, // 0.93077, -0.36561' + 0x3fedb6526238a09b, 0xbfd7c3a9311dcce7, // 0.92851, -0.37132' + 0x3feda383a9668988, 0xbfd820e3b04eaac4, // 0.92621, -0.37701' + 0x3fed906bcf328d46, 0xbfd87de2a6aea963, // 0.92388, -0.38268' + 0x3fed7d0b02b8ecf9, 0xbfd8daa52ec8a4af, // 0.92151, -0.38835' + 0x3fed696173c9e68b, 0xbfd9372a63bc93d7, // 0.91911, -0.39399' + 0x3fed556f52e93eb1, 0xbfd993716141bdfe, // 0.91668, -0.39962' + 0x3fed4134d14dc93a, 0xbfd9ef7943a8ed8a, // 0.91421, -0.40524' + 0x3fed2cb220e0ef9f, 0xbfda4b4127dea1e4, // 0.91171, -0.41084' + 0x3fed17e7743e35dc, 0xbfdaa6c82b6d3fc9, // 0.90917, -0.41643' + 0x3fed02d4feb2bd92, 0xbfdb020d6c7f4009, // 0.9066, -0.422' + 0x3feced7af43cc773, 0xbfdb5d1009e15cc0, // 0.90399, -0.42756' + 0x3fecd7d9898b32f6, 0xbfdbb7cf2304bd01, // 0.90135, -0.43309' + 0x3fecc1f0f3fcfc5c, 0xbfdc1249d8011ee7, // 0.89867, -0.43862' + 0x3fecabc169a0b901, 0xbfdc6c7f4997000a, // 0.89597, -0.44412' + 0x3fec954b213411f5, 0xbfdcc66e9931c45d, // 0.89322, -0.44961' + 0x3fec7e8e52233cf3, 0xbfdd2016e8e9db5b, // 0.89045, -0.45508' + 0x3fec678b3488739b, 0xbfdd79775b86e389, // 0.88764, -0.46054' + 0x3fec5042012b6907, 0xbfddd28f1481cc58, // 0.8848, -0.46598' + 0x3fec38b2f180bdb1, 0xbfde2b5d3806f63b, // 0.88192, -0.4714' + 0x3fec20de3fa971b0, 0xbfde83e0eaf85113, // 0.87901, -0.4768' + 0x3fec08c426725549, 0xbfdedc1952ef78d5, // 0.87607, -0.48218' + 0x3febf064e15377dd, 0xbfdf3405963fd068, // 0.87309, -0.48755' + 0x3febd7c0ac6f952a, 0xbfdf8ba4dbf89aba, // 0.87009, -0.4929' + 0x3febbed7c49380ea, 0xbfdfe2f64be7120f, // 0.86705, -0.49823' + 0x3feba5aa673590d2, 0xbfe01cfc874c3eb7, // 0.86397, -0.50354' + 0x3feb8c38d27504e9, 0xbfe0485626ae221a, // 0.86087, -0.50883' + 0x3feb728345196e3e, 0xbfe073879922ffed, // 0.85773, -0.5141' + 0x3feb5889fe921405, 0xbfe09e907417c5e1, // 0.85456, -0.51936' + 0x3feb3e4d3ef55712, 0xbfe0c9704d5d898f, // 0.85136, -0.52459' + 0x3feb23cd470013b4, 0xbfe0f426bb2a8e7d, // 0.84812, -0.5298' + 0x3feb090a58150200, 0xbfe11eb3541b4b22, // 0.84485, -0.535' + 0x3feaee04b43c1474, 0xbfe14915af336ceb, // 0.84155, -0.54017' + 0x3fead2bc9e21d511, 0xbfe1734d63dedb49, // 0.83822, -0.54532' + 0x3feab7325916c0d4, 0xbfe19d5a09f2b9b8, // 0.83486, -0.55046' + 0x3fea9b66290ea1a3, 0xbfe1c73b39ae68c8, // 0.83147, -0.55557' + 0x3fea7f58529fe69d, 0xbfe1f0f08bbc861b, // 0.82805, -0.56066' + 0x3fea63091b02fae2, 0xbfe21a799933eb58, // 0.82459, -0.56573' + 0x3fea4678c8119ac8, 0xbfe243d5fb98ac1f, // 0.8211, -0.57078' + 0x3fea29a7a0462782, 0xbfe26d054cdd12df, // 0.81758, -0.57581' + 0x3fea0c95eabaf937, 0xbfe2960727629ca8, // 0.81404, -0.58081' + 0x3fe9ef43ef29af94, 0xbfe2bedb25faf3ea, // 0.81046, -0.5858' + 0x3fe9d1b1f5ea80d6, 0xbfe2e780e3e8ea16, // 0.80685, -0.59076' + 0x3fe9b3e047f38741, 0xbfe30ff7fce17035, // 0.80321, -0.5957' + 0x3fe995cf2ed80d22, 0xbfe338400d0c8e57, // 0.79954, -0.60062' + 0x3fe9777ef4c7d742, 0xbfe36058b10659f3, // 0.79584, -0.60551' + 0x3fe958efe48e6dd7, 0xbfe3884185dfeb22, // 0.79211, -0.61038' + 0x3fe93a22499263fc, 0xbfe3affa292050b9, // 0.78835, -0.61523' + 0x3fe91b166fd49da2, 0xbfe3d78238c58343, // 0.78456, -0.62006' + 0x3fe8fbcca3ef940d, 0xbfe3fed9534556d4, // 0.78074, -0.62486' + 0x3fe8dc45331698cc, 0xbfe425ff178e6bb1, // 0.77689, -0.62964' + 0x3fe8bc806b151741, 0xbfe44cf325091dd6, // 0.77301, -0.63439' + 0x3fe89c7e9a4dd4ab, 0xbfe473b51b987347, // 0.7691, -0.63912' + 0x3fe87c400fba2ebf, 0xbfe49a449b9b0938, // 0.76517, -0.64383' + 0x3fe85bc51ae958cc, 0xbfe4c0a145ec0004, // 0.7612, -0.64851' + 0x3fe83b0e0bff976e, 0xbfe4e6cabbe3e5e9, // 0.75721, -0.65317' + 0x3fe81a1b33b57acc, 0xbfe50cc09f59a09b, // 0.75319, -0.65781' + 0x3fe7f8ece3571771, 0xbfe5328292a35596, // 0.74914, -0.66242' + 0x3fe7d7836cc33db2, 0xbfe5581038975137, // 0.74506, -0.667' + 0x3fe7b5df226aafb0, 0xbfe57d69348cec9f, // 0.74095, -0.67156' + 0x3fe79400574f55e4, 0xbfe5a28d2a5d7250, // 0.73682, -0.67609' + 0x3fe771e75f037261, 0xbfe5c77bbe65018c, // 0.73265, -0.6806' + 0x3fe74f948da8d28d, 0xbfe5ec3495837074, // 0.72846, -0.68508' + 0x3fe72d0837efff97, 0xbfe610b7551d2cde, // 0.72425, -0.68954' + 0x3fe70a42b3176d7a, 0xbfe63503a31c1be8, // 0.72, -0.69397' + 0x3fe6e74454eaa8ae, 0xbfe6591925f0783e, // 0.71573, -0.69838' + 0x3fe6c40d73c18275, 0xbfe67cf78491af10, // 0.71143, -0.70275' + 0x3fe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // 0.70711, -0.70711' + 0x3fe67cf78491af10, 0xbfe6c40d73c18275, // 0.70275, -0.71143' + 0x3fe6591925f0783e, 0xbfe6e74454eaa8ae, // 0.69838, -0.71573' + 0x3fe63503a31c1be8, 0xbfe70a42b3176d7a, // 0.69397, -0.72' + 0x3fe610b7551d2cde, 0xbfe72d0837efff97, // 0.68954, -0.72425' + 0x3fe5ec3495837074, 0xbfe74f948da8d28d, // 0.68508, -0.72846' + 0x3fe5c77bbe65018c, 0xbfe771e75f037261, // 0.6806, -0.73265' + 0x3fe5a28d2a5d7250, 0xbfe79400574f55e4, // 0.67609, -0.73682' + 0x3fe57d69348cec9f, 0xbfe7b5df226aafb0, // 0.67156, -0.74095' + 0x3fe5581038975137, 0xbfe7d7836cc33db2, // 0.667, -0.74506' + 0x3fe5328292a35596, 0xbfe7f8ece3571771, // 0.66242, -0.74914' + 0x3fe50cc09f59a09b, 0xbfe81a1b33b57acc, // 0.65781, -0.75319' + 0x3fe4e6cabbe3e5e9, 0xbfe83b0e0bff976e, // 0.65317, -0.75721' + 0x3fe4c0a145ec0004, 0xbfe85bc51ae958cc, // 0.64851, -0.7612' + 0x3fe49a449b9b0938, 0xbfe87c400fba2ebf, // 0.64383, -0.76517' + 0x3fe473b51b987347, 0xbfe89c7e9a4dd4ab, // 0.63912, -0.7691' + 0x3fe44cf325091dd6, 0xbfe8bc806b151741, // 0.63439, -0.77301' + 0x3fe425ff178e6bb1, 0xbfe8dc45331698cc, // 0.62964, -0.77689' + 0x3fe3fed9534556d4, 0xbfe8fbcca3ef940d, // 0.62486, -0.78074' + 0x3fe3d78238c58343, 0xbfe91b166fd49da2, // 0.62006, -0.78456' + 0x3fe3affa292050b9, 0xbfe93a22499263fc, // 0.61523, -0.78835' + 0x3fe3884185dfeb22, 0xbfe958efe48e6dd7, // 0.61038, -0.79211' + 0x3fe36058b10659f3, 0xbfe9777ef4c7d742, // 0.60551, -0.79584' + 0x3fe338400d0c8e57, 0xbfe995cf2ed80d22, // 0.60062, -0.79954' + 0x3fe30ff7fce17035, 0xbfe9b3e047f38741, // 0.5957, -0.80321' + 0x3fe2e780e3e8ea16, 0xbfe9d1b1f5ea80d6, // 0.59076, -0.80685' + 0x3fe2bedb25faf3ea, 0xbfe9ef43ef29af94, // 0.5858, -0.81046' + 0x3fe2960727629ca8, 0xbfea0c95eabaf937, // 0.58081, -0.81404' + 0x3fe26d054cdd12df, 0xbfea29a7a0462782, // 0.57581, -0.81758' + 0x3fe243d5fb98ac1f, 0xbfea4678c8119ac8, // 0.57078, -0.8211' + 0x3fe21a799933eb58, 0xbfea63091b02fae2, // 0.56573, -0.82459' + 0x3fe1f0f08bbc861b, 0xbfea7f58529fe69d, // 0.56066, -0.82805' + 0x3fe1c73b39ae68c8, 0xbfea9b66290ea1a3, // 0.55557, -0.83147' + 0x3fe19d5a09f2b9b8, 0xbfeab7325916c0d4, // 0.55046, -0.83486' + 0x3fe1734d63dedb49, 0xbfead2bc9e21d511, // 0.54532, -0.83822' + 0x3fe14915af336ceb, 0xbfeaee04b43c1474, // 0.54017, -0.84155' + 0x3fe11eb3541b4b22, 0xbfeb090a58150200, // 0.535, -0.84485' + 0x3fe0f426bb2a8e7d, 0xbfeb23cd470013b4, // 0.5298, -0.84812' + 0x3fe0c9704d5d898f, 0xbfeb3e4d3ef55712, // 0.52459, -0.85136' + 0x3fe09e907417c5e1, 0xbfeb5889fe921405, // 0.51936, -0.85456' + 0x3fe073879922ffed, 0xbfeb728345196e3e, // 0.5141, -0.85773' + 0x3fe0485626ae221a, 0xbfeb8c38d27504e9, // 0.50883, -0.86087' + 0x3fe01cfc874c3eb7, 0xbfeba5aa673590d2, // 0.50354, -0.86397' + 0x3fdfe2f64be7120f, 0xbfebbed7c49380ea, // 0.49823, -0.86705' + 0x3fdf8ba4dbf89aba, 0xbfebd7c0ac6f952a, // 0.4929, -0.87009' + 0x3fdf3405963fd068, 0xbfebf064e15377dd, // 0.48755, -0.87309' + 0x3fdedc1952ef78d5, 0xbfec08c426725549, // 0.48218, -0.87607' + 0x3fde83e0eaf85113, 0xbfec20de3fa971b0, // 0.4768, -0.87901' + 0x3fde2b5d3806f63b, 0xbfec38b2f180bdb1, // 0.4714, -0.88192' + 0x3fddd28f1481cc58, 0xbfec5042012b6907, // 0.46598, -0.8848' + 0x3fdd79775b86e389, 0xbfec678b3488739b, // 0.46054, -0.88764' + 0x3fdd2016e8e9db5b, 0xbfec7e8e52233cf3, // 0.45508, -0.89045' + 0x3fdcc66e9931c45d, 0xbfec954b213411f5, // 0.44961, -0.89322' + 0x3fdc6c7f4997000a, 0xbfecabc169a0b901, // 0.44412, -0.89597' + 0x3fdc1249d8011ee7, 0xbfecc1f0f3fcfc5c, // 0.43862, -0.89867' + 0x3fdbb7cf2304bd01, 0xbfecd7d9898b32f6, // 0.43309, -0.90135' + 0x3fdb5d1009e15cc0, 0xbfeced7af43cc773, // 0.42756, -0.90399' + 0x3fdb020d6c7f4009, 0xbfed02d4feb2bd92, // 0.422, -0.9066' + 0x3fdaa6c82b6d3fc9, 0xbfed17e7743e35dc, // 0.41643, -0.90917' + 0x3fda4b4127dea1e4, 0xbfed2cb220e0ef9f, // 0.41084, -0.91171' + 0x3fd9ef7943a8ed8a, 0xbfed4134d14dc93a, // 0.40524, -0.91421' + 0x3fd993716141bdfe, 0xbfed556f52e93eb1, // 0.39962, -0.91668' + 0x3fd9372a63bc93d7, 0xbfed696173c9e68b, // 0.39399, -0.91911' + 0x3fd8daa52ec8a4af, 0xbfed7d0b02b8ecf9, // 0.38835, -0.92151' + 0x3fd87de2a6aea963, 0xbfed906bcf328d46, // 0.38268, -0.92388' + 0x3fd820e3b04eaac4, 0xbfeda383a9668988, // 0.37701, -0.92621' + 0x3fd7c3a9311dcce7, 0xbfedb6526238a09b, // 0.37132, -0.92851' + 0x3fd766340f2418f6, 0xbfedc8d7cb410260, // 0.36561, -0.93077' + 0x3fd7088530fa459e, 0xbfeddb13b6ccc23d, // 0.3599, -0.93299' + 0x3fd6aa9d7dc77e16, 0xbfeded05f7de47da, // 0.35416, -0.93518' + 0x3fd64c7ddd3f27c6, 0xbfedfeae622dbe2b, // 0.34842, -0.93734' + 0x3fd5ee27379ea693, 0xbfee100cca2980ac, // 0.34266, -0.93946' + 0x3fd58f9a75ab1fdd, 0xbfee212104f686e5, // 0.33689, -0.94154' + 0x3fd530d880af3c24, 0xbfee31eae870ce25, // 0.33111, -0.94359' + 0x3fd4d1e24278e76a, 0xbfee426a4b2bc17e, // 0.32531, -0.94561' + 0x3fd472b8a5571054, 0xbfee529f04729ffc, // 0.3195, -0.94759' + 0x3fd4135c94176602, 0xbfee6288ec48e112, // 0.31368, -0.94953' + 0x3fd3b3cefa0414b7, 0xbfee7227db6a9744, // 0.30785, -0.95144' + 0x3fd35410c2e18152, 0xbfee817bab4cd10d, // 0.30201, -0.95331' + 0x3fd2f422daec0386, 0xbfee9084361df7f3, // 0.29615, -0.95514' + 0x3fd294062ed59f05, 0xbfee9f4156c62dda, // 0.29028, -0.95694' + 0x3fd233bbabc3bb72, 0xbfeeadb2e8e7a88e, // 0.28441, -0.9587' + 0x3fd1d3443f4cdb3d, 0xbfeebbd8c8df0b74, // 0.27852, -0.96043' + 0x3fd172a0d7765177, 0xbfeec9b2d3c3bf84, // 0.27262, -0.96212' + 0x3fd111d262b1f677, 0xbfeed740e7684963, // 0.26671, -0.96378' + 0x3fd0b0d9cfdbdb90, 0xbfeee482e25a9dbc, // 0.26079, -0.96539' + 0x3fd04fb80e37fdae, 0xbfeef178a3e473c2, // 0.25487, -0.96698' + 0x3fcfdcdc1adfedf8, 0xbfeefe220c0b95ec, // 0.24893, -0.96852' + 0x3fcf19f97b215f1a, 0xbfef0a7efb9230d7, // 0.24298, -0.97003' + 0x3fce56ca1e101a1b, 0xbfef168f53f7205d, // 0.23702, -0.9715' + 0x3fcd934fe5454311, 0xbfef2252f7763ada, // 0.23106, -0.97294' + 0x3fcccf8cb312b286, 0xbfef2dc9c9089a9d, // 0.22508, -0.97434' + 0x3fcc0b826a7e4f63, 0xbfef38f3ac64e589, // 0.2191, -0.9757' + 0x3fcb4732ef3d6722, 0xbfef43d085ff92dd, // 0.21311, -0.97703' + 0x3fca82a025b00451, 0xbfef4e603b0b2f2d, // 0.20711, -0.97832' + 0x3fc9bdcbf2dc4366, 0xbfef58a2b1789e84, // 0.2011, -0.97957' + 0x3fc8f8b83c69a60a, 0xbfef6297cff75cb0, // 0.19509, -0.98079' + 0x3fc83366e89c64c5, 0xbfef6c3f7df5bbb7, // 0.18907, -0.98196' + 0x3fc76dd9de50bf31, 0xbfef7599a3a12077, // 0.18304, -0.98311' + 0x3fc6a81304f64ab2, 0xbfef7ea629e63d6e, // 0.177, -0.98421' + 0x3fc5e214448b3fc6, 0xbfef8764fa714ba9, // 0.17096, -0.98528' + 0x3fc51bdf8597c5f2, 0xbfef8fd5ffae41db, // 0.16491, -0.98631' + 0x3fc45576b1293e5a, 0xbfef97f924c9099b, // 0.15886, -0.9873' + 0x3fc38edbb0cd8d14, 0xbfef9fce55adb2c8, // 0.1528, -0.98826' + 0x3fc2c8106e8e613a, 0xbfefa7557f08a517, // 0.14673, -0.98918' + 0x3fc20116d4ec7bce, 0xbfefae8e8e46cfbb, // 0.14066, -0.99006' + 0x3fc139f0cedaf576, 0xbfefb5797195d741, // 0.13458, -0.9909' + 0x3fc072a047ba831d, 0xbfefbc1617e44186, // 0.1285, -0.99171' + 0x3fbf564e56a9730e, 0xbfefc26470e19fd3, // 0.12241, -0.99248' + 0x3fbdc70ecbae9fc8, 0xbfefc8646cfeb721, // 0.11632, -0.99321' + 0x3fbc3785c79ec2d5, 0xbfefce15fd6da67b, // 0.11022, -0.99391' + 0x3fbaa7b724495c04, 0xbfefd37914220b84, // 0.10412, -0.99456' + 0x3fb917a6bc29b42c, 0xbfefd88da3d12526, // 0.098017, -0.99518' + 0x3fb787586a5d5b21, 0xbfefdd539ff1f456, // 0.091909, -0.99577' + 0x3fb5f6d00a9aa419, 0xbfefe1cafcbd5b09, // 0.085797, -0.99631' + 0x3fb4661179272096, 0xbfefe5f3af2e3940, // 0.079682, -0.99682' + 0x3fb2d52092ce19f6, 0xbfefe9cdad01883a, // 0.073565, -0.99729' + 0x3fb1440134d709b2, 0xbfefed58ecb673c4, // 0.067444, -0.99772' + 0x3faf656e79f820e0, 0xbfeff095658e71ad, // 0.061321, -0.99812' + 0x3fac428d12c0d7e3, 0xbfeff3830f8d575c, // 0.055195, -0.99848' + 0x3fa91f65f10dd814, 0xbfeff621e3796d7e, // 0.049068, -0.9988' + 0x3fa5fc00d290cd43, 0xbfeff871dadb81df, // 0.042938, -0.99908' + 0x3fa2d865759455cd, 0xbfeffa72effef75d, // 0.036807, -0.99932' + 0x3f9f693731d1cf01, 0xbfeffc251df1d3f8, // 0.030675, -0.99953' + 0x3f992155f7a3667e, 0xbfeffd886084cd0d, // 0.024541, -0.9997' + 0x3f92d936bbe30efd, 0xbfeffe9cb44b51a1, // 0.018407, -0.99983' + 0x3f8921d1fcdec784, 0xbfefff62169b92db, // 0.012272, -0.99992' + 0x3f7921f0fe670071, 0xbfefffd8858e8a92, //0.0061359, -0.99998' +}; + +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F64_2048) +const uint64_t twiddleCoefF64_rfft_2048[2048] = { + 0x0000000000000000, 0x3ff0000000000000, // 0, 1 + 0x3f6921f8becca4ba, 0x3feffff621621d02, // 0.003068, 1 + 0x3f7921f0fe670071, 0x3fefffd8858e8a92, //0.0061359, 0.99998 + 0x3f82d96b0e509703, 0x3fefffa72c978c4f, //0.0092038, 0.99996 + 0x3f8921d1fcdec784, 0x3fefff62169b92db, // 0.012272, 0.99992 + 0x3f8f6a296ab997ca, 0x3fefff0943c53bd1, // 0.015339, 0.99988 + 0x3f92d936bbe30efd, 0x3feffe9cb44b51a1, // 0.018407, 0.99983 + 0x3f95fd4d21fab226, 0x3feffe1c6870cb77, // 0.021474, 0.99977 + 0x3f992155f7a3667e, 0x3feffd886084cd0d, // 0.024541, 0.9997 + 0x3f9c454f4ce53b1c, 0x3feffce09ce2a679, // 0.027608, 0.99962 + 0x3f9f693731d1cf01, 0x3feffc251df1d3f8, // 0.030675, 0.99953 + 0x3fa14685db42c17e, 0x3feffb55e425fdae, // 0.033741, 0.99943 + 0x3fa2d865759455cd, 0x3feffa72effef75d, // 0.036807, 0.99932 + 0x3fa46a396ff86179, 0x3feff97c4208c014, // 0.039873, 0.9992 + 0x3fa5fc00d290cd43, 0x3feff871dadb81df, // 0.042938, 0.99908 + 0x3fa78dbaa5874685, 0x3feff753bb1b9164, // 0.046003, 0.99894 + 0x3fa91f65f10dd814, 0x3feff621e3796d7e, // 0.049068, 0.9988 + 0x3faab101bd5f8317, 0x3feff4dc54b1bed3, // 0.052132, 0.99864 + 0x3fac428d12c0d7e3, 0x3feff3830f8d575c, // 0.055195, 0.99848 + 0x3fadd406f9808ec8, 0x3feff21614e131ed, // 0.058258, 0.9983 + 0x3faf656e79f820e0, 0x3feff095658e71ad, // 0.061321, 0.99812 + 0x3fb07b614e463064, 0x3fefef0102826191, // 0.064383, 0.99793 + 0x3fb1440134d709b2, 0x3fefed58ecb673c4, // 0.067444, 0.99772 + 0x3fb20c9674ed444c, 0x3fefeb9d2530410f, // 0.070505, 0.99751 + 0x3fb2d52092ce19f6, 0x3fefe9cdad01883a, // 0.073565, 0.99729 + 0x3fb39d9f12c5a299, 0x3fefe7ea85482d60, // 0.076624, 0.99706 + 0x3fb4661179272096, 0x3fefe5f3af2e3940, // 0.079682, 0.99682 + 0x3fb52e774a4d4d0a, 0x3fefe3e92be9d886, // 0.08274, 0.99657 + 0x3fb5f6d00a9aa419, 0x3fefe1cafcbd5b09, // 0.085797, 0.99631 + 0x3fb6bf1b3e79b129, 0x3fefdf9922f73307, // 0.088854, 0.99604 + 0x3fb787586a5d5b21, 0x3fefdd539ff1f456, // 0.091909, 0.99577 + 0x3fb84f8712c130a0, 0x3fefdafa7514538c, // 0.094963, 0.99548 + 0x3fb917a6bc29b42c, 0x3fefd88da3d12526, // 0.098017, 0.99518 + 0x3fb9dfb6eb24a85c, 0x3fefd60d2da75c9e, // 0.10107, 0.99488 + 0x3fbaa7b724495c04, 0x3fefd37914220b84, // 0.10412, 0.99456 + 0x3fbb6fa6ec38f64c, 0x3fefd0d158d86087, // 0.10717, 0.99424 + 0x3fbc3785c79ec2d5, 0x3fefce15fd6da67b, // 0.11022, 0.99391 + 0x3fbcff533b307dc1, 0x3fefcb4703914354, // 0.11327, 0.99356 + 0x3fbdc70ecbae9fc8, 0x3fefc8646cfeb721, // 0.11632, 0.99321 + 0x3fbe8eb7fde4aa3e, 0x3fefc56e3b7d9af6, // 0.11937, 0.99285 + 0x3fbf564e56a9730e, 0x3fefc26470e19fd3, // 0.12241, 0.99248 + 0x3fc00ee8ad6fb85b, 0x3fefbf470f0a8d88, // 0.12545, 0.9921 + 0x3fc072a047ba831d, 0x3fefbc1617e44186, // 0.1285, 0.99171 + 0x3fc0d64dbcb26786, 0x3fefb8d18d66adb7, // 0.13154, 0.99131 + 0x3fc139f0cedaf576, 0x3fefb5797195d741, // 0.13458, 0.9909 + 0x3fc19d8940be24e7, 0x3fefb20dc681d54d, // 0.13762, 0.99049 + 0x3fc20116d4ec7bce, 0x3fefae8e8e46cfbb, // 0.14066, 0.99006 + 0x3fc264994dfd340a, 0x3fefaafbcb0cfddc, // 0.1437, 0.98962 + 0x3fc2c8106e8e613a, 0x3fefa7557f08a517, // 0.14673, 0.98918 + 0x3fc32b7bf94516a7, 0x3fefa39bac7a1791, // 0.14976, 0.98872 + 0x3fc38edbb0cd8d14, 0x3fef9fce55adb2c8, // 0.1528, 0.98826 + 0x3fc3f22f57db4893, 0x3fef9bed7cfbde29, // 0.15583, 0.98778 + 0x3fc45576b1293e5a, 0x3fef97f924c9099b, // 0.15886, 0.9873 + 0x3fc4b8b17f79fa88, 0x3fef93f14f85ac08, // 0.16189, 0.98681 + 0x3fc51bdf8597c5f2, 0x3fef8fd5ffae41db, // 0.16491, 0.98631 + 0x3fc57f008654cbde, 0x3fef8ba737cb4b78, // 0.16794, 0.9858 + 0x3fc5e214448b3fc6, 0x3fef8764fa714ba9, // 0.17096, 0.98528 + 0x3fc6451a831d830d, 0x3fef830f4a40c60c, // 0.17398, 0.98475 + 0x3fc6a81304f64ab2, 0x3fef7ea629e63d6e, // 0.177, 0.98421 + 0x3fc70afd8d08c4ff, 0x3fef7a299c1a322a, // 0.18002, 0.98366 + 0x3fc76dd9de50bf31, 0x3fef7599a3a12077, // 0.18304, 0.98311 + 0x3fc7d0a7bbd2cb1b, 0x3fef70f6434b7eb7, // 0.18606, 0.98254 + 0x3fc83366e89c64c5, 0x3fef6c3f7df5bbb7, // 0.18907, 0.98196 + 0x3fc8961727c41804, 0x3fef677556883cee, // 0.19208, 0.98138 + 0x3fc8f8b83c69a60a, 0x3fef6297cff75cb0, // 0.19509, 0.98079 + 0x3fc95b49e9b62af9, 0x3fef5da6ed43685d, // 0.1981, 0.98018 + 0x3fc9bdcbf2dc4366, 0x3fef58a2b1789e84, // 0.2011, 0.97957 + 0x3fca203e1b1831da, 0x3fef538b1faf2d07, // 0.20411, 0.97895 + 0x3fca82a025b00451, 0x3fef4e603b0b2f2d, // 0.20711, 0.97832 + 0x3fcae4f1d5f3b9ab, 0x3fef492206bcabb4, // 0.21011, 0.97768 + 0x3fcb4732ef3d6722, 0x3fef43d085ff92dd, // 0.21311, 0.97703 + 0x3fcba96334f15dad, 0x3fef3e6bbc1bbc65, // 0.21611, 0.97637 + 0x3fcc0b826a7e4f63, 0x3fef38f3ac64e589, // 0.2191, 0.9757 + 0x3fcc6d90535d74dc, 0x3fef33685a3aaef0, // 0.22209, 0.97503 + 0x3fcccf8cb312b286, 0x3fef2dc9c9089a9d, // 0.22508, 0.97434 + 0x3fcd31774d2cbdee, 0x3fef2817fc4609ce, // 0.22807, 0.97364 + 0x3fcd934fe5454311, 0x3fef2252f7763ada, // 0.23106, 0.97294 + 0x3fcdf5163f01099a, 0x3fef1c7abe284708, // 0.23404, 0.97223 + 0x3fce56ca1e101a1b, 0x3fef168f53f7205d, // 0.23702, 0.9715 + 0x3fceb86b462de348, 0x3fef1090bc898f5f, // 0.24, 0.97077 + 0x3fcf19f97b215f1a, 0x3fef0a7efb9230d7, // 0.24298, 0.97003 + 0x3fcf7b7480bd3801, 0x3fef045a14cf738c, // 0.24596, 0.96928 + 0x3fcfdcdc1adfedf8, 0x3feefe220c0b95ec, // 0.24893, 0.96852 + 0x3fd01f1806b9fdd2, 0x3feef7d6e51ca3c0, // 0.2519, 0.96775 + 0x3fd04fb80e37fdae, 0x3feef178a3e473c2, // 0.25487, 0.96698 + 0x3fd0804e05eb661e, 0x3feeeb074c50a544, // 0.25783, 0.96619 + 0x3fd0b0d9cfdbdb90, 0x3feee482e25a9dbc, // 0.26079, 0.96539 + 0x3fd0e15b4e1749cd, 0x3feeddeb6a078651, // 0.26375, 0.96459 + 0x3fd111d262b1f677, 0x3feed740e7684963, // 0.26671, 0.96378 + 0x3fd1423eefc69378, 0x3feed0835e999009, // 0.26967, 0.96295 + 0x3fd172a0d7765177, 0x3feec9b2d3c3bf84, // 0.27262, 0.96212 + 0x3fd1a2f7fbe8f243, 0x3feec2cf4b1af6b2, // 0.27557, 0.96128 + 0x3fd1d3443f4cdb3d, 0x3feebbd8c8df0b74, // 0.27852, 0.96043 + 0x3fd2038583d727bd, 0x3feeb4cf515b8811, // 0.28146, 0.95957 + 0x3fd233bbabc3bb72, 0x3feeadb2e8e7a88e, // 0.28441, 0.9587 + 0x3fd263e6995554ba, 0x3feea68393e65800, // 0.28735, 0.95783 + 0x3fd294062ed59f05, 0x3fee9f4156c62dda, // 0.29028, 0.95694 + 0x3fd2c41a4e954520, 0x3fee97ec36016b30, // 0.29322, 0.95605 + 0x3fd2f422daec0386, 0x3fee9084361df7f3, // 0.29615, 0.95514 + 0x3fd3241fb638baaf, 0x3fee89095bad6025, // 0.29908, 0.95423 + 0x3fd35410c2e18152, 0x3fee817bab4cd10d, // 0.30201, 0.95331 + 0x3fd383f5e353b6aa, 0x3fee79db29a5165a, // 0.30493, 0.95238 + 0x3fd3b3cefa0414b7, 0x3fee7227db6a9744, // 0.30785, 0.95144 + 0x3fd3e39be96ec271, 0x3fee6a61c55d53a7, // 0.31077, 0.95049 + 0x3fd4135c94176602, 0x3fee6288ec48e112, // 0.31368, 0.94953 + 0x3fd44310dc8936f0, 0x3fee5a9d550467d3, // 0.31659, 0.94856 + 0x3fd472b8a5571054, 0x3fee529f04729ffc, // 0.3195, 0.94759 + 0x3fd4a253d11b82f3, 0x3fee4a8dff81ce5e, // 0.32241, 0.9466 + 0x3fd4d1e24278e76a, 0x3fee426a4b2bc17e, // 0.32531, 0.94561 + 0x3fd50163dc197047, 0x3fee3a33ec75ce85, // 0.32821, 0.9446 + 0x3fd530d880af3c24, 0x3fee31eae870ce25, // 0.33111, 0.94359 + 0x3fd5604012f467b4, 0x3fee298f4439197a, // 0.334, 0.94257 + 0x3fd58f9a75ab1fdd, 0x3fee212104f686e5, // 0.33689, 0.94154 + 0x3fd5bee78b9db3b6, 0x3fee18a02fdc66d9, // 0.33978, 0.94051 + 0x3fd5ee27379ea693, 0x3fee100cca2980ac, // 0.34266, 0.93946 + 0x3fd61d595c88c203, 0x3fee0766d9280f54, // 0.34554, 0.9384 + 0x3fd64c7ddd3f27c6, 0x3fedfeae622dbe2b, // 0.34842, 0.93734 + 0x3fd67b949cad63ca, 0x3fedf5e36a9ba59c, // 0.35129, 0.93627 + 0x3fd6aa9d7dc77e16, 0x3feded05f7de47da, // 0.35416, 0.93518 + 0x3fd6d998638a0cb5, 0x3fede4160f6d8d81, // 0.35703, 0.93409 + 0x3fd7088530fa459e, 0x3feddb13b6ccc23d, // 0.3599, 0.93299 + 0x3fd73763c9261092, 0x3fedd1fef38a915a, // 0.36276, 0.93188 + 0x3fd766340f2418f6, 0x3fedc8d7cb410260, // 0.36561, 0.93077 + 0x3fd794f5e613dfae, 0x3fedbf9e4395759a, // 0.36847, 0.92964 + 0x3fd7c3a9311dcce7, 0x3fedb6526238a09b, // 0.37132, 0.92851 + 0x3fd7f24dd37341e3, 0x3fedacf42ce68ab9, // 0.37416, 0.92736 + 0x3fd820e3b04eaac4, 0x3feda383a9668988, // 0.37701, 0.92621 + 0x3fd84f6aaaf3903f, 0x3fed9a00dd8b3d46, // 0.37985, 0.92505 + 0x3fd87de2a6aea963, 0x3fed906bcf328d46, // 0.38268, 0.92388 + 0x3fd8ac4b86d5ed44, 0x3fed86c48445a450, // 0.38552, 0.9227 + 0x3fd8daa52ec8a4af, 0x3fed7d0b02b8ecf9, // 0.38835, 0.92151 + 0x3fd908ef81ef7bd1, 0x3fed733f508c0dff, // 0.39117, 0.92032 + 0x3fd9372a63bc93d7, 0x3fed696173c9e68b, // 0.39399, 0.91911 + 0x3fd96555b7ab948f, 0x3fed5f7172888a7f, // 0.39681, 0.9179 + 0x3fd993716141bdfe, 0x3fed556f52e93eb1, // 0.39962, 0.91668 + 0x3fd9c17d440df9f2, 0x3fed4b5b1b187524, // 0.40243, 0.91545 + 0x3fd9ef7943a8ed8a, 0x3fed4134d14dc93a, // 0.40524, 0.91421 + 0x3fda1d6543b50ac0, 0x3fed36fc7bcbfbdc, // 0.40804, 0.91296 + 0x3fda4b4127dea1e4, 0x3fed2cb220e0ef9f, // 0.41084, 0.91171 + 0x3fda790cd3dbf31a, 0x3fed2255c6e5a4e1, // 0.41364, 0.91044 + 0x3fdaa6c82b6d3fc9, 0x3fed17e7743e35dc, // 0.41643, 0.90917 + 0x3fdad473125cdc08, 0x3fed0d672f59d2b9, // 0.41922, 0.90789 + 0x3fdb020d6c7f4009, 0x3fed02d4feb2bd92, // 0.422, 0.9066 + 0x3fdb2f971db31972, 0x3fecf830e8ce467b, // 0.42478, 0.9053 + 0x3fdb5d1009e15cc0, 0x3feced7af43cc773, // 0.42756, 0.90399 + 0x3fdb8a7814fd5693, 0x3fece2b32799a060, // 0.43033, 0.90267 + 0x3fdbb7cf2304bd01, 0x3fecd7d9898b32f6, // 0.43309, 0.90135 + 0x3fdbe51517ffc0d9, 0x3fecccee20c2de9f, // 0.43586, 0.90002 + 0x3fdc1249d8011ee7, 0x3fecc1f0f3fcfc5c, // 0.43862, 0.89867 + 0x3fdc3f6d47263129, 0x3fecb6e20a00da99, // 0.44137, 0.89732 + 0x3fdc6c7f4997000a, 0x3fecabc169a0b901, // 0.44412, 0.89597 + 0x3fdc997fc3865388, 0x3feca08f19b9c449, // 0.44687, 0.8946 + 0x3fdcc66e9931c45d, 0x3fec954b213411f5, // 0.44961, 0.89322 + 0x3fdcf34baee1cd21, 0x3fec89f587029c13, // 0.45235, 0.89184 + 0x3fdd2016e8e9db5b, 0x3fec7e8e52233cf3, // 0.45508, 0.89045 + 0x3fdd4cd02ba8609c, 0x3fec7315899eaad7, // 0.45781, 0.88905 + 0x3fdd79775b86e389, 0x3fec678b3488739b, // 0.46054, 0.88764 + 0x3fdda60c5cfa10d8, 0x3fec5bef59fef85a, // 0.46326, 0.88622 + 0x3fddd28f1481cc58, 0x3fec5042012b6907, // 0.46598, 0.8848 + 0x3fddfeff66a941de, 0x3fec44833141c004, // 0.46869, 0.88336 + 0x3fde2b5d3806f63b, 0x3fec38b2f180bdb1, // 0.4714, 0.88192 + 0x3fde57a86d3cd824, 0x3fec2cd14931e3f1, // 0.4741, 0.88047 + 0x3fde83e0eaf85113, 0x3fec20de3fa971b0, // 0.4768, 0.87901 + 0x3fdeb00695f25620, 0x3fec14d9dc465e58, // 0.47949, 0.87755 + 0x3fdedc1952ef78d5, 0x3fec08c426725549, // 0.48218, 0.87607 + 0x3fdf081906bff7fd, 0x3febfc9d25a1b147, // 0.48487, 0.87459 + 0x3fdf3405963fd068, 0x3febf064e15377dd, // 0.48755, 0.87309 + 0x3fdf5fdee656cda3, 0x3febe41b611154c1, // 0.49023, 0.8716 + 0x3fdf8ba4dbf89aba, 0x3febd7c0ac6f952a, // 0.4929, 0.87009 + 0x3fdfb7575c24d2de, 0x3febcb54cb0d2327, // 0.49557, 0.86857 + 0x3fdfe2f64be7120f, 0x3febbed7c49380ea, // 0.49823, 0.86705 + 0x3fe00740c82b82e0, 0x3febb249a0b6c40d, // 0.50089, 0.86551 + 0x3fe01cfc874c3eb7, 0x3feba5aa673590d2, // 0.50354, 0.86397 + 0x3fe032ae55edbd95, 0x3feb98fa1fd9155e, // 0.50619, 0.86242 + 0x3fe0485626ae221a, 0x3feb8c38d27504e9, // 0.50883, 0.86087 + 0x3fe05df3ec31b8b6, 0x3feb7f6686e792ea, // 0.51147, 0.8593 + 0x3fe073879922ffed, 0x3feb728345196e3e, // 0.5141, 0.85773 + 0x3fe089112032b08c, 0x3feb658f14fdbc47, // 0.51673, 0.85615 + 0x3fe09e907417c5e1, 0x3feb5889fe921405, // 0.51936, 0.85456 + 0x3fe0b405878f85ec, 0x3feb4b7409de7925, // 0.52198, 0.85296 + 0x3fe0c9704d5d898f, 0x3feb3e4d3ef55712, // 0.52459, 0.85136 + 0x3fe0ded0b84bc4b5, 0x3feb3115a5f37bf4, // 0.5272, 0.84974 + 0x3fe0f426bb2a8e7d, 0x3feb23cd470013b4, // 0.5298, 0.84812 + 0x3fe1097248d0a956, 0x3feb16742a4ca2f5, // 0.5324, 0.84649 + 0x3fe11eb3541b4b22, 0x3feb090a58150200, // 0.535, 0.84485 + 0x3fe133e9cfee254e, 0x3feafb8fd89f57b6, // 0.53759, 0.84321 + 0x3fe14915af336ceb, 0x3feaee04b43c1474, // 0.54017, 0.84155 + 0x3fe15e36e4dbe2bc, 0x3feae068f345ecef, // 0.54275, 0.83989 + 0x3fe1734d63dedb49, 0x3fead2bc9e21d511, // 0.54532, 0.83822 + 0x3fe188591f3a46e5, 0x3feac4ffbd3efac8, // 0.54789, 0.83655 + 0x3fe19d5a09f2b9b8, 0x3feab7325916c0d4, // 0.55046, 0.83486 + 0x3fe1b250171373be, 0x3feaa9547a2cb98e, // 0.55302, 0.83317 + 0x3fe1c73b39ae68c8, 0x3fea9b66290ea1a3, // 0.55557, 0.83147 + 0x3fe1dc1b64dc4872, 0x3fea8d676e545ad2, // 0.55812, 0.82976 + 0x3fe1f0f08bbc861b, 0x3fea7f58529fe69d, // 0.56066, 0.82805 + 0x3fe205baa17560d6, 0x3fea7138de9d60f5, // 0.5632, 0.82632 + 0x3fe21a799933eb58, 0x3fea63091b02fae2, // 0.56573, 0.82459 + 0x3fe22f2d662c13e1, 0x3fea54c91090f524, // 0.56826, 0.82285 + 0x3fe243d5fb98ac1f, 0x3fea4678c8119ac8, // 0.57078, 0.8211 + 0x3fe258734cbb7110, 0x3fea38184a593bc6, // 0.5733, 0.81935 + 0x3fe26d054cdd12df, 0x3fea29a7a0462782, // 0.57581, 0.81758 + 0x3fe2818bef4d3cba, 0x3fea1b26d2c0a75e, // 0.57831, 0.81581 + 0x3fe2960727629ca8, 0x3fea0c95eabaf937, // 0.58081, 0.81404 + 0x3fe2aa76e87aeb58, 0x3fe9fdf4f13149de, // 0.58331, 0.81225 + 0x3fe2bedb25faf3ea, 0x3fe9ef43ef29af94, // 0.5858, 0.81046 + 0x3fe2d333d34e9bb7, 0x3fe9e082edb42472, // 0.58828, 0.80866 + 0x3fe2e780e3e8ea16, 0x3fe9d1b1f5ea80d6, // 0.59076, 0.80685 + 0x3fe2fbc24b441015, 0x3fe9c2d110f075c3, // 0.59323, 0.80503 + 0x3fe30ff7fce17035, 0x3fe9b3e047f38741, // 0.5957, 0.80321 + 0x3fe32421ec49a620, 0x3fe9a4dfa42b06b2, // 0.59816, 0.80138 + 0x3fe338400d0c8e57, 0x3fe995cf2ed80d22, // 0.60062, 0.79954 + 0x3fe34c5252c14de1, 0x3fe986aef1457594, // 0.60307, 0.79769 + 0x3fe36058b10659f3, 0x3fe9777ef4c7d742, // 0.60551, 0.79584 + 0x3fe374531b817f8d, 0x3fe9683f42bd7fe1, // 0.60795, 0.79398 + 0x3fe3884185dfeb22, 0x3fe958efe48e6dd7, // 0.61038, 0.79211 + 0x3fe39c23e3d63029, 0x3fe94990e3ac4a6c, // 0.61281, 0.79023 + 0x3fe3affa292050b9, 0x3fe93a22499263fc, // 0.61523, 0.78835 + 0x3fe3c3c44981c517, 0x3fe92aa41fc5a815, // 0.61765, 0.78646 + 0x3fe3d78238c58343, 0x3fe91b166fd49da2, // 0.62006, 0.78456 + 0x3fe3eb33eabe0680, 0x3fe90b7943575efe, // 0.62246, 0.78265 + 0x3fe3fed9534556d4, 0x3fe8fbcca3ef940d, // 0.62486, 0.78074 + 0x3fe41272663d108c, 0x3fe8ec109b486c49, // 0.62725, 0.77882 + 0x3fe425ff178e6bb1, 0x3fe8dc45331698cc, // 0.62964, 0.77689 + 0x3fe4397f5b2a4380, 0x3fe8cc6a75184655, // 0.63202, 0.77495 + 0x3fe44cf325091dd6, 0x3fe8bc806b151741, // 0.63439, 0.77301 + 0x3fe4605a692b32a2, 0x3fe8ac871ede1d88, // 0.63676, 0.77106 + 0x3fe473b51b987347, 0x3fe89c7e9a4dd4ab, // 0.63912, 0.7691 + 0x3fe48703306091fe, 0x3fe88c66e7481ba1, // 0.64148, 0.76714 + 0x3fe49a449b9b0938, 0x3fe87c400fba2ebf, // 0.64383, 0.76517 + 0x3fe4ad79516722f0, 0x3fe86c0a1d9aa195, // 0.64618, 0.76319 + 0x3fe4c0a145ec0004, 0x3fe85bc51ae958cc, // 0.64851, 0.7612 + 0x3fe4d3bc6d589f80, 0x3fe84b7111af83f9, // 0.65085, 0.75921 + 0x3fe4e6cabbe3e5e9, 0x3fe83b0e0bff976e, // 0.65317, 0.75721 + 0x3fe4f9cc25cca486, 0x3fe82a9c13f545ff, // 0.65549, 0.7552 + 0x3fe50cc09f59a09b, 0x3fe81a1b33b57acc, // 0.65781, 0.75319 + 0x3fe51fa81cd99aa6, 0x3fe8098b756e52fa, // 0.66011, 0.75117 + 0x3fe5328292a35596, 0x3fe7f8ece3571771, // 0.66242, 0.74914 + 0x3fe5454ff5159dfb, 0x3fe7e83f87b03686, // 0.66471, 0.7471 + 0x3fe5581038975137, 0x3fe7d7836cc33db2, // 0.667, 0.74506 + 0x3fe56ac35197649e, 0x3fe7c6b89ce2d333, // 0.66928, 0.74301 + 0x3fe57d69348cec9f, 0x3fe7b5df226aafb0, // 0.67156, 0.74095 + 0x3fe59001d5f723df, 0x3fe7a4f707bf97d2, // 0.67383, 0.73889 + 0x3fe5a28d2a5d7250, 0x3fe79400574f55e4, // 0.67609, 0.73682 + 0x3fe5b50b264f7448, 0x3fe782fb1b90b35b, // 0.67835, 0.73474 + 0x3fe5c77bbe65018c, 0x3fe771e75f037261, // 0.6806, 0.73265 + 0x3fe5d9dee73e345c, 0x3fe760c52c304764, // 0.68285, 0.73056 + 0x3fe5ec3495837074, 0x3fe74f948da8d28d, // 0.68508, 0.72846 + 0x3fe5fe7cbde56a0f, 0x3fe73e558e079942, // 0.68732, 0.72636 + 0x3fe610b7551d2cde, 0x3fe72d0837efff97, // 0.68954, 0.72425 + 0x3fe622e44fec22ff, 0x3fe71bac960e41bf, // 0.69176, 0.72213 + 0x3fe63503a31c1be8, 0x3fe70a42b3176d7a, // 0.69397, 0.72 + 0x3fe64715437f535b, 0x3fe6f8ca99c95b75, // 0.69618, 0.71787 + 0x3fe6591925f0783e, 0x3fe6e74454eaa8ae, // 0.69838, 0.71573 + 0x3fe66b0f3f52b386, 0x3fe6d5afef4aafcc, // 0.70057, 0.71358 + 0x3fe67cf78491af10, 0x3fe6c40d73c18275, // 0.70275, 0.71143 + 0x3fe68ed1eaa19c71, 0x3fe6b25ced2fe29c, // 0.70493, 0.70927 + 0x3fe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // 0.70711, 0.70711 + 0x3fe6b25ced2fe29c, 0x3fe68ed1eaa19c71, // 0.70927, 0.70493 + 0x3fe6c40d73c18275, 0x3fe67cf78491af10, // 0.71143, 0.70275 + 0x3fe6d5afef4aafcc, 0x3fe66b0f3f52b386, // 0.71358, 0.70057 + 0x3fe6e74454eaa8ae, 0x3fe6591925f0783e, // 0.71573, 0.69838 + 0x3fe6f8ca99c95b75, 0x3fe64715437f535b, // 0.71787, 0.69618 + 0x3fe70a42b3176d7a, 0x3fe63503a31c1be8, // 0.72, 0.69397 + 0x3fe71bac960e41bf, 0x3fe622e44fec22ff, // 0.72213, 0.69176 + 0x3fe72d0837efff97, 0x3fe610b7551d2cde, // 0.72425, 0.68954 + 0x3fe73e558e079942, 0x3fe5fe7cbde56a0f, // 0.72636, 0.68732 + 0x3fe74f948da8d28d, 0x3fe5ec3495837074, // 0.72846, 0.68508 + 0x3fe760c52c304764, 0x3fe5d9dee73e345c, // 0.73056, 0.68285 + 0x3fe771e75f037261, 0x3fe5c77bbe65018c, // 0.73265, 0.6806 + 0x3fe782fb1b90b35b, 0x3fe5b50b264f7448, // 0.73474, 0.67835 + 0x3fe79400574f55e4, 0x3fe5a28d2a5d7250, // 0.73682, 0.67609 + 0x3fe7a4f707bf97d2, 0x3fe59001d5f723df, // 0.73889, 0.67383 + 0x3fe7b5df226aafb0, 0x3fe57d69348cec9f, // 0.74095, 0.67156 + 0x3fe7c6b89ce2d333, 0x3fe56ac35197649e, // 0.74301, 0.66928 + 0x3fe7d7836cc33db2, 0x3fe5581038975137, // 0.74506, 0.667 + 0x3fe7e83f87b03686, 0x3fe5454ff5159dfb, // 0.7471, 0.66471 + 0x3fe7f8ece3571771, 0x3fe5328292a35596, // 0.74914, 0.66242 + 0x3fe8098b756e52fa, 0x3fe51fa81cd99aa6, // 0.75117, 0.66011 + 0x3fe81a1b33b57acc, 0x3fe50cc09f59a09b, // 0.75319, 0.65781 + 0x3fe82a9c13f545ff, 0x3fe4f9cc25cca486, // 0.7552, 0.65549 + 0x3fe83b0e0bff976e, 0x3fe4e6cabbe3e5e9, // 0.75721, 0.65317 + 0x3fe84b7111af83f9, 0x3fe4d3bc6d589f80, // 0.75921, 0.65085 + 0x3fe85bc51ae958cc, 0x3fe4c0a145ec0004, // 0.7612, 0.64851 + 0x3fe86c0a1d9aa195, 0x3fe4ad79516722f0, // 0.76319, 0.64618 + 0x3fe87c400fba2ebf, 0x3fe49a449b9b0938, // 0.76517, 0.64383 + 0x3fe88c66e7481ba1, 0x3fe48703306091fe, // 0.76714, 0.64148 + 0x3fe89c7e9a4dd4ab, 0x3fe473b51b987347, // 0.7691, 0.63912 + 0x3fe8ac871ede1d88, 0x3fe4605a692b32a2, // 0.77106, 0.63676 + 0x3fe8bc806b151741, 0x3fe44cf325091dd6, // 0.77301, 0.63439 + 0x3fe8cc6a75184655, 0x3fe4397f5b2a4380, // 0.77495, 0.63202 + 0x3fe8dc45331698cc, 0x3fe425ff178e6bb1, // 0.77689, 0.62964 + 0x3fe8ec109b486c49, 0x3fe41272663d108c, // 0.77882, 0.62725 + 0x3fe8fbcca3ef940d, 0x3fe3fed9534556d4, // 0.78074, 0.62486 + 0x3fe90b7943575efe, 0x3fe3eb33eabe0680, // 0.78265, 0.62246 + 0x3fe91b166fd49da2, 0x3fe3d78238c58343, // 0.78456, 0.62006 + 0x3fe92aa41fc5a815, 0x3fe3c3c44981c517, // 0.78646, 0.61765 + 0x3fe93a22499263fc, 0x3fe3affa292050b9, // 0.78835, 0.61523 + 0x3fe94990e3ac4a6c, 0x3fe39c23e3d63029, // 0.79023, 0.61281 + 0x3fe958efe48e6dd7, 0x3fe3884185dfeb22, // 0.79211, 0.61038 + 0x3fe9683f42bd7fe1, 0x3fe374531b817f8d, // 0.79398, 0.60795 + 0x3fe9777ef4c7d742, 0x3fe36058b10659f3, // 0.79584, 0.60551 + 0x3fe986aef1457594, 0x3fe34c5252c14de1, // 0.79769, 0.60307 + 0x3fe995cf2ed80d22, 0x3fe338400d0c8e57, // 0.79954, 0.60062 + 0x3fe9a4dfa42b06b2, 0x3fe32421ec49a620, // 0.80138, 0.59816 + 0x3fe9b3e047f38741, 0x3fe30ff7fce17035, // 0.80321, 0.5957 + 0x3fe9c2d110f075c3, 0x3fe2fbc24b441015, // 0.80503, 0.59323 + 0x3fe9d1b1f5ea80d6, 0x3fe2e780e3e8ea16, // 0.80685, 0.59076 + 0x3fe9e082edb42472, 0x3fe2d333d34e9bb7, // 0.80866, 0.58828 + 0x3fe9ef43ef29af94, 0x3fe2bedb25faf3ea, // 0.81046, 0.5858 + 0x3fe9fdf4f13149de, 0x3fe2aa76e87aeb58, // 0.81225, 0.58331 + 0x3fea0c95eabaf937, 0x3fe2960727629ca8, // 0.81404, 0.58081 + 0x3fea1b26d2c0a75e, 0x3fe2818bef4d3cba, // 0.81581, 0.57831 + 0x3fea29a7a0462782, 0x3fe26d054cdd12df, // 0.81758, 0.57581 + 0x3fea38184a593bc6, 0x3fe258734cbb7110, // 0.81935, 0.5733 + 0x3fea4678c8119ac8, 0x3fe243d5fb98ac1f, // 0.8211, 0.57078 + 0x3fea54c91090f524, 0x3fe22f2d662c13e1, // 0.82285, 0.56826 + 0x3fea63091b02fae2, 0x3fe21a799933eb58, // 0.82459, 0.56573 + 0x3fea7138de9d60f5, 0x3fe205baa17560d6, // 0.82632, 0.5632 + 0x3fea7f58529fe69d, 0x3fe1f0f08bbc861b, // 0.82805, 0.56066 + 0x3fea8d676e545ad2, 0x3fe1dc1b64dc4872, // 0.82976, 0.55812 + 0x3fea9b66290ea1a3, 0x3fe1c73b39ae68c8, // 0.83147, 0.55557 + 0x3feaa9547a2cb98e, 0x3fe1b250171373be, // 0.83317, 0.55302 + 0x3feab7325916c0d4, 0x3fe19d5a09f2b9b8, // 0.83486, 0.55046 + 0x3feac4ffbd3efac8, 0x3fe188591f3a46e5, // 0.83655, 0.54789 + 0x3fead2bc9e21d511, 0x3fe1734d63dedb49, // 0.83822, 0.54532 + 0x3feae068f345ecef, 0x3fe15e36e4dbe2bc, // 0.83989, 0.54275 + 0x3feaee04b43c1474, 0x3fe14915af336ceb, // 0.84155, 0.54017 + 0x3feafb8fd89f57b6, 0x3fe133e9cfee254e, // 0.84321, 0.53759 + 0x3feb090a58150200, 0x3fe11eb3541b4b22, // 0.84485, 0.535 + 0x3feb16742a4ca2f5, 0x3fe1097248d0a956, // 0.84649, 0.5324 + 0x3feb23cd470013b4, 0x3fe0f426bb2a8e7d, // 0.84812, 0.5298 + 0x3feb3115a5f37bf4, 0x3fe0ded0b84bc4b5, // 0.84974, 0.5272 + 0x3feb3e4d3ef55712, 0x3fe0c9704d5d898f, // 0.85136, 0.52459 + 0x3feb4b7409de7925, 0x3fe0b405878f85ec, // 0.85296, 0.52198 + 0x3feb5889fe921405, 0x3fe09e907417c5e1, // 0.85456, 0.51936 + 0x3feb658f14fdbc47, 0x3fe089112032b08c, // 0.85615, 0.51673 + 0x3feb728345196e3e, 0x3fe073879922ffed, // 0.85773, 0.5141 + 0x3feb7f6686e792ea, 0x3fe05df3ec31b8b6, // 0.8593, 0.51147 + 0x3feb8c38d27504e9, 0x3fe0485626ae221a, // 0.86087, 0.50883 + 0x3feb98fa1fd9155e, 0x3fe032ae55edbd95, // 0.86242, 0.50619 + 0x3feba5aa673590d2, 0x3fe01cfc874c3eb7, // 0.86397, 0.50354 + 0x3febb249a0b6c40d, 0x3fe00740c82b82e0, // 0.86551, 0.50089 + 0x3febbed7c49380ea, 0x3fdfe2f64be7120f, // 0.86705, 0.49823 + 0x3febcb54cb0d2327, 0x3fdfb7575c24d2de, // 0.86857, 0.49557 + 0x3febd7c0ac6f952a, 0x3fdf8ba4dbf89aba, // 0.87009, 0.4929 + 0x3febe41b611154c1, 0x3fdf5fdee656cda3, // 0.8716, 0.49023 + 0x3febf064e15377dd, 0x3fdf3405963fd068, // 0.87309, 0.48755 + 0x3febfc9d25a1b147, 0x3fdf081906bff7fd, // 0.87459, 0.48487 + 0x3fec08c426725549, 0x3fdedc1952ef78d5, // 0.87607, 0.48218 + 0x3fec14d9dc465e58, 0x3fdeb00695f25620, // 0.87755, 0.47949 + 0x3fec20de3fa971b0, 0x3fde83e0eaf85113, // 0.87901, 0.4768 + 0x3fec2cd14931e3f1, 0x3fde57a86d3cd824, // 0.88047, 0.4741 + 0x3fec38b2f180bdb1, 0x3fde2b5d3806f63b, // 0.88192, 0.4714 + 0x3fec44833141c004, 0x3fddfeff66a941de, // 0.88336, 0.46869 + 0x3fec5042012b6907, 0x3fddd28f1481cc58, // 0.8848, 0.46598 + 0x3fec5bef59fef85a, 0x3fdda60c5cfa10d8, // 0.88622, 0.46326 + 0x3fec678b3488739b, 0x3fdd79775b86e389, // 0.88764, 0.46054 + 0x3fec7315899eaad7, 0x3fdd4cd02ba8609c, // 0.88905, 0.45781 + 0x3fec7e8e52233cf3, 0x3fdd2016e8e9db5b, // 0.89045, 0.45508 + 0x3fec89f587029c13, 0x3fdcf34baee1cd21, // 0.89184, 0.45235 + 0x3fec954b213411f5, 0x3fdcc66e9931c45d, // 0.89322, 0.44961 + 0x3feca08f19b9c449, 0x3fdc997fc3865388, // 0.8946, 0.44687 + 0x3fecabc169a0b901, 0x3fdc6c7f4997000a, // 0.89597, 0.44412 + 0x3fecb6e20a00da99, 0x3fdc3f6d47263129, // 0.89732, 0.44137 + 0x3fecc1f0f3fcfc5c, 0x3fdc1249d8011ee7, // 0.89867, 0.43862 + 0x3fecccee20c2de9f, 0x3fdbe51517ffc0d9, // 0.90002, 0.43586 + 0x3fecd7d9898b32f6, 0x3fdbb7cf2304bd01, // 0.90135, 0.43309 + 0x3fece2b32799a060, 0x3fdb8a7814fd5693, // 0.90267, 0.43033 + 0x3feced7af43cc773, 0x3fdb5d1009e15cc0, // 0.90399, 0.42756 + 0x3fecf830e8ce467b, 0x3fdb2f971db31972, // 0.9053, 0.42478 + 0x3fed02d4feb2bd92, 0x3fdb020d6c7f4009, // 0.9066, 0.422 + 0x3fed0d672f59d2b9, 0x3fdad473125cdc08, // 0.90789, 0.41922 + 0x3fed17e7743e35dc, 0x3fdaa6c82b6d3fc9, // 0.90917, 0.41643 + 0x3fed2255c6e5a4e1, 0x3fda790cd3dbf31a, // 0.91044, 0.41364 + 0x3fed2cb220e0ef9f, 0x3fda4b4127dea1e4, // 0.91171, 0.41084 + 0x3fed36fc7bcbfbdc, 0x3fda1d6543b50ac0, // 0.91296, 0.40804 + 0x3fed4134d14dc93a, 0x3fd9ef7943a8ed8a, // 0.91421, 0.40524 + 0x3fed4b5b1b187524, 0x3fd9c17d440df9f2, // 0.91545, 0.40243 + 0x3fed556f52e93eb1, 0x3fd993716141bdfe, // 0.91668, 0.39962 + 0x3fed5f7172888a7f, 0x3fd96555b7ab948f, // 0.9179, 0.39681 + 0x3fed696173c9e68b, 0x3fd9372a63bc93d7, // 0.91911, 0.39399 + 0x3fed733f508c0dff, 0x3fd908ef81ef7bd1, // 0.92032, 0.39117 + 0x3fed7d0b02b8ecf9, 0x3fd8daa52ec8a4af, // 0.92151, 0.38835 + 0x3fed86c48445a450, 0x3fd8ac4b86d5ed44, // 0.9227, 0.38552 + 0x3fed906bcf328d46, 0x3fd87de2a6aea963, // 0.92388, 0.38268 + 0x3fed9a00dd8b3d46, 0x3fd84f6aaaf3903f, // 0.92505, 0.37985 + 0x3feda383a9668988, 0x3fd820e3b04eaac4, // 0.92621, 0.37701 + 0x3fedacf42ce68ab9, 0x3fd7f24dd37341e3, // 0.92736, 0.37416 + 0x3fedb6526238a09b, 0x3fd7c3a9311dcce7, // 0.92851, 0.37132 + 0x3fedbf9e4395759a, 0x3fd794f5e613dfae, // 0.92964, 0.36847 + 0x3fedc8d7cb410260, 0x3fd766340f2418f6, // 0.93077, 0.36561 + 0x3fedd1fef38a915a, 0x3fd73763c9261092, // 0.93188, 0.36276 + 0x3feddb13b6ccc23d, 0x3fd7088530fa459e, // 0.93299, 0.3599 + 0x3fede4160f6d8d81, 0x3fd6d998638a0cb5, // 0.93409, 0.35703 + 0x3feded05f7de47da, 0x3fd6aa9d7dc77e16, // 0.93518, 0.35416 + 0x3fedf5e36a9ba59c, 0x3fd67b949cad63ca, // 0.93627, 0.35129 + 0x3fedfeae622dbe2b, 0x3fd64c7ddd3f27c6, // 0.93734, 0.34842 + 0x3fee0766d9280f54, 0x3fd61d595c88c203, // 0.9384, 0.34554 + 0x3fee100cca2980ac, 0x3fd5ee27379ea693, // 0.93946, 0.34266 + 0x3fee18a02fdc66d9, 0x3fd5bee78b9db3b6, // 0.94051, 0.33978 + 0x3fee212104f686e5, 0x3fd58f9a75ab1fdd, // 0.94154, 0.33689 + 0x3fee298f4439197a, 0x3fd5604012f467b4, // 0.94257, 0.334 + 0x3fee31eae870ce25, 0x3fd530d880af3c24, // 0.94359, 0.33111 + 0x3fee3a33ec75ce85, 0x3fd50163dc197047, // 0.9446, 0.32821 + 0x3fee426a4b2bc17e, 0x3fd4d1e24278e76a, // 0.94561, 0.32531 + 0x3fee4a8dff81ce5e, 0x3fd4a253d11b82f3, // 0.9466, 0.32241 + 0x3fee529f04729ffc, 0x3fd472b8a5571054, // 0.94759, 0.3195 + 0x3fee5a9d550467d3, 0x3fd44310dc8936f0, // 0.94856, 0.31659 + 0x3fee6288ec48e112, 0x3fd4135c94176602, // 0.94953, 0.31368 + 0x3fee6a61c55d53a7, 0x3fd3e39be96ec271, // 0.95049, 0.31077 + 0x3fee7227db6a9744, 0x3fd3b3cefa0414b7, // 0.95144, 0.30785 + 0x3fee79db29a5165a, 0x3fd383f5e353b6aa, // 0.95238, 0.30493 + 0x3fee817bab4cd10d, 0x3fd35410c2e18152, // 0.95331, 0.30201 + 0x3fee89095bad6025, 0x3fd3241fb638baaf, // 0.95423, 0.29908 + 0x3fee9084361df7f3, 0x3fd2f422daec0386, // 0.95514, 0.29615 + 0x3fee97ec36016b30, 0x3fd2c41a4e954520, // 0.95605, 0.29322 + 0x3fee9f4156c62dda, 0x3fd294062ed59f05, // 0.95694, 0.29028 + 0x3feea68393e65800, 0x3fd263e6995554ba, // 0.95783, 0.28735 + 0x3feeadb2e8e7a88e, 0x3fd233bbabc3bb72, // 0.9587, 0.28441 + 0x3feeb4cf515b8811, 0x3fd2038583d727bd, // 0.95957, 0.28146 + 0x3feebbd8c8df0b74, 0x3fd1d3443f4cdb3d, // 0.96043, 0.27852 + 0x3feec2cf4b1af6b2, 0x3fd1a2f7fbe8f243, // 0.96128, 0.27557 + 0x3feec9b2d3c3bf84, 0x3fd172a0d7765177, // 0.96212, 0.27262 + 0x3feed0835e999009, 0x3fd1423eefc69378, // 0.96295, 0.26967 + 0x3feed740e7684963, 0x3fd111d262b1f677, // 0.96378, 0.26671 + 0x3feeddeb6a078651, 0x3fd0e15b4e1749cd, // 0.96459, 0.26375 + 0x3feee482e25a9dbc, 0x3fd0b0d9cfdbdb90, // 0.96539, 0.26079 + 0x3feeeb074c50a544, 0x3fd0804e05eb661e, // 0.96619, 0.25783 + 0x3feef178a3e473c2, 0x3fd04fb80e37fdae, // 0.96698, 0.25487 + 0x3feef7d6e51ca3c0, 0x3fd01f1806b9fdd2, // 0.96775, 0.2519 + 0x3feefe220c0b95ec, 0x3fcfdcdc1adfedf8, // 0.96852, 0.24893 + 0x3fef045a14cf738c, 0x3fcf7b7480bd3801, // 0.96928, 0.24596 + 0x3fef0a7efb9230d7, 0x3fcf19f97b215f1a, // 0.97003, 0.24298 + 0x3fef1090bc898f5f, 0x3fceb86b462de348, // 0.97077, 0.24 + 0x3fef168f53f7205d, 0x3fce56ca1e101a1b, // 0.9715, 0.23702 + 0x3fef1c7abe284708, 0x3fcdf5163f01099a, // 0.97223, 0.23404 + 0x3fef2252f7763ada, 0x3fcd934fe5454311, // 0.97294, 0.23106 + 0x3fef2817fc4609ce, 0x3fcd31774d2cbdee, // 0.97364, 0.22807 + 0x3fef2dc9c9089a9d, 0x3fcccf8cb312b286, // 0.97434, 0.22508 + 0x3fef33685a3aaef0, 0x3fcc6d90535d74dc, // 0.97503, 0.22209 + 0x3fef38f3ac64e589, 0x3fcc0b826a7e4f63, // 0.9757, 0.2191 + 0x3fef3e6bbc1bbc65, 0x3fcba96334f15dad, // 0.97637, 0.21611 + 0x3fef43d085ff92dd, 0x3fcb4732ef3d6722, // 0.97703, 0.21311 + 0x3fef492206bcabb4, 0x3fcae4f1d5f3b9ab, // 0.97768, 0.21011 + 0x3fef4e603b0b2f2d, 0x3fca82a025b00451, // 0.97832, 0.20711 + 0x3fef538b1faf2d07, 0x3fca203e1b1831da, // 0.97895, 0.20411 + 0x3fef58a2b1789e84, 0x3fc9bdcbf2dc4366, // 0.97957, 0.2011 + 0x3fef5da6ed43685d, 0x3fc95b49e9b62af9, // 0.98018, 0.1981 + 0x3fef6297cff75cb0, 0x3fc8f8b83c69a60a, // 0.98079, 0.19509 + 0x3fef677556883cee, 0x3fc8961727c41804, // 0.98138, 0.19208 + 0x3fef6c3f7df5bbb7, 0x3fc83366e89c64c5, // 0.98196, 0.18907 + 0x3fef70f6434b7eb7, 0x3fc7d0a7bbd2cb1b, // 0.98254, 0.18606 + 0x3fef7599a3a12077, 0x3fc76dd9de50bf31, // 0.98311, 0.18304 + 0x3fef7a299c1a322a, 0x3fc70afd8d08c4ff, // 0.98366, 0.18002 + 0x3fef7ea629e63d6e, 0x3fc6a81304f64ab2, // 0.98421, 0.177 + 0x3fef830f4a40c60c, 0x3fc6451a831d830d, // 0.98475, 0.17398 + 0x3fef8764fa714ba9, 0x3fc5e214448b3fc6, // 0.98528, 0.17096 + 0x3fef8ba737cb4b78, 0x3fc57f008654cbde, // 0.9858, 0.16794 + 0x3fef8fd5ffae41db, 0x3fc51bdf8597c5f2, // 0.98631, 0.16491 + 0x3fef93f14f85ac08, 0x3fc4b8b17f79fa88, // 0.98681, 0.16189 + 0x3fef97f924c9099b, 0x3fc45576b1293e5a, // 0.9873, 0.15886 + 0x3fef9bed7cfbde29, 0x3fc3f22f57db4893, // 0.98778, 0.15583 + 0x3fef9fce55adb2c8, 0x3fc38edbb0cd8d14, // 0.98826, 0.1528 + 0x3fefa39bac7a1791, 0x3fc32b7bf94516a7, // 0.98872, 0.14976 + 0x3fefa7557f08a517, 0x3fc2c8106e8e613a, // 0.98918, 0.14673 + 0x3fefaafbcb0cfddc, 0x3fc264994dfd340a, // 0.98962, 0.1437 + 0x3fefae8e8e46cfbb, 0x3fc20116d4ec7bce, // 0.99006, 0.14066 + 0x3fefb20dc681d54d, 0x3fc19d8940be24e7, // 0.99049, 0.13762 + 0x3fefb5797195d741, 0x3fc139f0cedaf576, // 0.9909, 0.13458 + 0x3fefb8d18d66adb7, 0x3fc0d64dbcb26786, // 0.99131, 0.13154 + 0x3fefbc1617e44186, 0x3fc072a047ba831d, // 0.99171, 0.1285 + 0x3fefbf470f0a8d88, 0x3fc00ee8ad6fb85b, // 0.9921, 0.12545 + 0x3fefc26470e19fd3, 0x3fbf564e56a9730e, // 0.99248, 0.12241 + 0x3fefc56e3b7d9af6, 0x3fbe8eb7fde4aa3e, // 0.99285, 0.11937 + 0x3fefc8646cfeb721, 0x3fbdc70ecbae9fc8, // 0.99321, 0.11632 + 0x3fefcb4703914354, 0x3fbcff533b307dc1, // 0.99356, 0.11327 + 0x3fefce15fd6da67b, 0x3fbc3785c79ec2d5, // 0.99391, 0.11022 + 0x3fefd0d158d86087, 0x3fbb6fa6ec38f64c, // 0.99424, 0.10717 + 0x3fefd37914220b84, 0x3fbaa7b724495c04, // 0.99456, 0.10412 + 0x3fefd60d2da75c9e, 0x3fb9dfb6eb24a85c, // 0.99488, 0.10107 + 0x3fefd88da3d12526, 0x3fb917a6bc29b42c, // 0.99518, 0.098017 + 0x3fefdafa7514538c, 0x3fb84f8712c130a0, // 0.99548, 0.094963 + 0x3fefdd539ff1f456, 0x3fb787586a5d5b21, // 0.99577, 0.091909 + 0x3fefdf9922f73307, 0x3fb6bf1b3e79b129, // 0.99604, 0.088854 + 0x3fefe1cafcbd5b09, 0x3fb5f6d00a9aa419, // 0.99631, 0.085797 + 0x3fefe3e92be9d886, 0x3fb52e774a4d4d0a, // 0.99657, 0.08274 + 0x3fefe5f3af2e3940, 0x3fb4661179272096, // 0.99682, 0.079682 + 0x3fefe7ea85482d60, 0x3fb39d9f12c5a299, // 0.99706, 0.076624 + 0x3fefe9cdad01883a, 0x3fb2d52092ce19f6, // 0.99729, 0.073565 + 0x3fefeb9d2530410f, 0x3fb20c9674ed444c, // 0.99751, 0.070505 + 0x3fefed58ecb673c4, 0x3fb1440134d709b2, // 0.99772, 0.067444 + 0x3fefef0102826191, 0x3fb07b614e463064, // 0.99793, 0.064383 + 0x3feff095658e71ad, 0x3faf656e79f820e0, // 0.99812, 0.061321 + 0x3feff21614e131ed, 0x3fadd406f9808ec8, // 0.9983, 0.058258 + 0x3feff3830f8d575c, 0x3fac428d12c0d7e3, // 0.99848, 0.055195 + 0x3feff4dc54b1bed3, 0x3faab101bd5f8317, // 0.99864, 0.052132 + 0x3feff621e3796d7e, 0x3fa91f65f10dd814, // 0.9988, 0.049068 + 0x3feff753bb1b9164, 0x3fa78dbaa5874685, // 0.99894, 0.046003 + 0x3feff871dadb81df, 0x3fa5fc00d290cd43, // 0.99908, 0.042938 + 0x3feff97c4208c014, 0x3fa46a396ff86179, // 0.9992, 0.039873 + 0x3feffa72effef75d, 0x3fa2d865759455cd, // 0.99932, 0.036807 + 0x3feffb55e425fdae, 0x3fa14685db42c17e, // 0.99943, 0.033741 + 0x3feffc251df1d3f8, 0x3f9f693731d1cf01, // 0.99953, 0.030675 + 0x3feffce09ce2a679, 0x3f9c454f4ce53b1c, // 0.99962, 0.027608 + 0x3feffd886084cd0d, 0x3f992155f7a3667e, // 0.9997, 0.024541 + 0x3feffe1c6870cb77, 0x3f95fd4d21fab226, // 0.99977, 0.021474 + 0x3feffe9cb44b51a1, 0x3f92d936bbe30efd, // 0.99983, 0.018407 + 0x3fefff0943c53bd1, 0x3f8f6a296ab997ca, // 0.99988, 0.015339 + 0x3fefff62169b92db, 0x3f8921d1fcdec784, // 0.99992, 0.012272 + 0x3fefffa72c978c4f, 0x3f82d96b0e509703, // 0.99996, 0.0092038 + 0x3fefffd8858e8a92, 0x3f7921f0fe670071, // 0.99998, 0.0061359 + 0x3feffff621621d02, 0x3f6921f8becca4ba, // 1, 0.003068 + 0x3ff0000000000000, 0x0000000000000000, // 1, 0 + 0x3feffff621621d02, 0xbf6921f8becca4ba, // 1, -0.003068 + 0x3fefffd8858e8a92, 0xbf7921f0fe670071, // 0.99998,-0.0061359 + 0x3fefffa72c978c4f, 0xbf82d96b0e509703, // 0.99996,-0.0092038 + 0x3fefff62169b92db, 0xbf8921d1fcdec784, // 0.99992, -0.012272 + 0x3fefff0943c53bd1, 0xbf8f6a296ab997ca, // 0.99988, -0.015339 + 0x3feffe9cb44b51a1, 0xbf92d936bbe30efd, // 0.99983, -0.018407 + 0x3feffe1c6870cb77, 0xbf95fd4d21fab226, // 0.99977, -0.021474 + 0x3feffd886084cd0d, 0xbf992155f7a3667e, // 0.9997, -0.024541 + 0x3feffce09ce2a679, 0xbf9c454f4ce53b1c, // 0.99962, -0.027608 + 0x3feffc251df1d3f8, 0xbf9f693731d1cf01, // 0.99953, -0.030675 + 0x3feffb55e425fdae, 0xbfa14685db42c17e, // 0.99943, -0.033741 + 0x3feffa72effef75d, 0xbfa2d865759455cd, // 0.99932, -0.036807 + 0x3feff97c4208c014, 0xbfa46a396ff86179, // 0.9992, -0.039873 + 0x3feff871dadb81df, 0xbfa5fc00d290cd43, // 0.99908, -0.042938 + 0x3feff753bb1b9164, 0xbfa78dbaa5874685, // 0.99894, -0.046003 + 0x3feff621e3796d7e, 0xbfa91f65f10dd814, // 0.9988, -0.049068 + 0x3feff4dc54b1bed3, 0xbfaab101bd5f8317, // 0.99864, -0.052132 + 0x3feff3830f8d575c, 0xbfac428d12c0d7e3, // 0.99848, -0.055195 + 0x3feff21614e131ed, 0xbfadd406f9808ec8, // 0.9983, -0.058258 + 0x3feff095658e71ad, 0xbfaf656e79f820e0, // 0.99812, -0.061321 + 0x3fefef0102826191, 0xbfb07b614e463064, // 0.99793, -0.064383 + 0x3fefed58ecb673c4, 0xbfb1440134d709b2, // 0.99772, -0.067444 + 0x3fefeb9d2530410f, 0xbfb20c9674ed444c, // 0.99751, -0.070505 + 0x3fefe9cdad01883a, 0xbfb2d52092ce19f6, // 0.99729, -0.073565 + 0x3fefe7ea85482d60, 0xbfb39d9f12c5a299, // 0.99706, -0.076624 + 0x3fefe5f3af2e3940, 0xbfb4661179272096, // 0.99682, -0.079682 + 0x3fefe3e92be9d886, 0xbfb52e774a4d4d0a, // 0.99657, -0.08274 + 0x3fefe1cafcbd5b09, 0xbfb5f6d00a9aa419, // 0.99631, -0.085797 + 0x3fefdf9922f73307, 0xbfb6bf1b3e79b129, // 0.99604, -0.088854 + 0x3fefdd539ff1f456, 0xbfb787586a5d5b21, // 0.99577, -0.091909 + 0x3fefdafa7514538c, 0xbfb84f8712c130a0, // 0.99548, -0.094963 + 0x3fefd88da3d12526, 0xbfb917a6bc29b42c, // 0.99518, -0.098017 + 0x3fefd60d2da75c9e, 0xbfb9dfb6eb24a85c, // 0.99488, -0.10107 + 0x3fefd37914220b84, 0xbfbaa7b724495c04, // 0.99456, -0.10412 + 0x3fefd0d158d86087, 0xbfbb6fa6ec38f64c, // 0.99424, -0.10717 + 0x3fefce15fd6da67b, 0xbfbc3785c79ec2d5, // 0.99391, -0.11022 + 0x3fefcb4703914354, 0xbfbcff533b307dc1, // 0.99356, -0.11327 + 0x3fefc8646cfeb721, 0xbfbdc70ecbae9fc8, // 0.99321, -0.11632 + 0x3fefc56e3b7d9af6, 0xbfbe8eb7fde4aa3e, // 0.99285, -0.11937 + 0x3fefc26470e19fd3, 0xbfbf564e56a9730e, // 0.99248, -0.12241 + 0x3fefbf470f0a8d88, 0xbfc00ee8ad6fb85b, // 0.9921, -0.12545 + 0x3fefbc1617e44186, 0xbfc072a047ba831d, // 0.99171, -0.1285 + 0x3fefb8d18d66adb7, 0xbfc0d64dbcb26786, // 0.99131, -0.13154 + 0x3fefb5797195d741, 0xbfc139f0cedaf576, // 0.9909, -0.13458 + 0x3fefb20dc681d54d, 0xbfc19d8940be24e7, // 0.99049, -0.13762 + 0x3fefae8e8e46cfbb, 0xbfc20116d4ec7bce, // 0.99006, -0.14066 + 0x3fefaafbcb0cfddc, 0xbfc264994dfd340a, // 0.98962, -0.1437 + 0x3fefa7557f08a517, 0xbfc2c8106e8e613a, // 0.98918, -0.14673 + 0x3fefa39bac7a1791, 0xbfc32b7bf94516a7, // 0.98872, -0.14976 + 0x3fef9fce55adb2c8, 0xbfc38edbb0cd8d14, // 0.98826, -0.1528 + 0x3fef9bed7cfbde29, 0xbfc3f22f57db4893, // 0.98778, -0.15583 + 0x3fef97f924c9099b, 0xbfc45576b1293e5a, // 0.9873, -0.15886 + 0x3fef93f14f85ac08, 0xbfc4b8b17f79fa88, // 0.98681, -0.16189 + 0x3fef8fd5ffae41db, 0xbfc51bdf8597c5f2, // 0.98631, -0.16491 + 0x3fef8ba737cb4b78, 0xbfc57f008654cbde, // 0.9858, -0.16794 + 0x3fef8764fa714ba9, 0xbfc5e214448b3fc6, // 0.98528, -0.17096 + 0x3fef830f4a40c60c, 0xbfc6451a831d830d, // 0.98475, -0.17398 + 0x3fef7ea629e63d6e, 0xbfc6a81304f64ab2, // 0.98421, -0.177 + 0x3fef7a299c1a322a, 0xbfc70afd8d08c4ff, // 0.98366, -0.18002 + 0x3fef7599a3a12077, 0xbfc76dd9de50bf31, // 0.98311, -0.18304 + 0x3fef70f6434b7eb7, 0xbfc7d0a7bbd2cb1b, // 0.98254, -0.18606 + 0x3fef6c3f7df5bbb7, 0xbfc83366e89c64c5, // 0.98196, -0.18907 + 0x3fef677556883cee, 0xbfc8961727c41804, // 0.98138, -0.19208 + 0x3fef6297cff75cb0, 0xbfc8f8b83c69a60a, // 0.98079, -0.19509 + 0x3fef5da6ed43685d, 0xbfc95b49e9b62af9, // 0.98018, -0.1981 + 0x3fef58a2b1789e84, 0xbfc9bdcbf2dc4366, // 0.97957, -0.2011 + 0x3fef538b1faf2d07, 0xbfca203e1b1831da, // 0.97895, -0.20411 + 0x3fef4e603b0b2f2d, 0xbfca82a025b00451, // 0.97832, -0.20711 + 0x3fef492206bcabb4, 0xbfcae4f1d5f3b9ab, // 0.97768, -0.21011 + 0x3fef43d085ff92dd, 0xbfcb4732ef3d6722, // 0.97703, -0.21311 + 0x3fef3e6bbc1bbc65, 0xbfcba96334f15dad, // 0.97637, -0.21611 + 0x3fef38f3ac64e589, 0xbfcc0b826a7e4f63, // 0.9757, -0.2191 + 0x3fef33685a3aaef0, 0xbfcc6d90535d74dc, // 0.97503, -0.22209 + 0x3fef2dc9c9089a9d, 0xbfcccf8cb312b286, // 0.97434, -0.22508 + 0x3fef2817fc4609ce, 0xbfcd31774d2cbdee, // 0.97364, -0.22807 + 0x3fef2252f7763ada, 0xbfcd934fe5454311, // 0.97294, -0.23106 + 0x3fef1c7abe284708, 0xbfcdf5163f01099a, // 0.97223, -0.23404 + 0x3fef168f53f7205d, 0xbfce56ca1e101a1b, // 0.9715, -0.23702 + 0x3fef1090bc898f5f, 0xbfceb86b462de348, // 0.97077, -0.24 + 0x3fef0a7efb9230d7, 0xbfcf19f97b215f1a, // 0.97003, -0.24298 + 0x3fef045a14cf738c, 0xbfcf7b7480bd3801, // 0.96928, -0.24596 + 0x3feefe220c0b95ec, 0xbfcfdcdc1adfedf8, // 0.96852, -0.24893 + 0x3feef7d6e51ca3c0, 0xbfd01f1806b9fdd2, // 0.96775, -0.2519 + 0x3feef178a3e473c2, 0xbfd04fb80e37fdae, // 0.96698, -0.25487 + 0x3feeeb074c50a544, 0xbfd0804e05eb661e, // 0.96619, -0.25783 + 0x3feee482e25a9dbc, 0xbfd0b0d9cfdbdb90, // 0.96539, -0.26079 + 0x3feeddeb6a078651, 0xbfd0e15b4e1749cd, // 0.96459, -0.26375 + 0x3feed740e7684963, 0xbfd111d262b1f677, // 0.96378, -0.26671 + 0x3feed0835e999009, 0xbfd1423eefc69378, // 0.96295, -0.26967 + 0x3feec9b2d3c3bf84, 0xbfd172a0d7765177, // 0.96212, -0.27262 + 0x3feec2cf4b1af6b2, 0xbfd1a2f7fbe8f243, // 0.96128, -0.27557 + 0x3feebbd8c8df0b74, 0xbfd1d3443f4cdb3d, // 0.96043, -0.27852 + 0x3feeb4cf515b8811, 0xbfd2038583d727bd, // 0.95957, -0.28146 + 0x3feeadb2e8e7a88e, 0xbfd233bbabc3bb72, // 0.9587, -0.28441 + 0x3feea68393e65800, 0xbfd263e6995554ba, // 0.95783, -0.28735 + 0x3fee9f4156c62dda, 0xbfd294062ed59f05, // 0.95694, -0.29028 + 0x3fee97ec36016b30, 0xbfd2c41a4e954520, // 0.95605, -0.29322 + 0x3fee9084361df7f3, 0xbfd2f422daec0386, // 0.95514, -0.29615 + 0x3fee89095bad6025, 0xbfd3241fb638baaf, // 0.95423, -0.29908 + 0x3fee817bab4cd10d, 0xbfd35410c2e18152, // 0.95331, -0.30201 + 0x3fee79db29a5165a, 0xbfd383f5e353b6aa, // 0.95238, -0.30493 + 0x3fee7227db6a9744, 0xbfd3b3cefa0414b7, // 0.95144, -0.30785 + 0x3fee6a61c55d53a7, 0xbfd3e39be96ec271, // 0.95049, -0.31077 + 0x3fee6288ec48e112, 0xbfd4135c94176602, // 0.94953, -0.31368 + 0x3fee5a9d550467d3, 0xbfd44310dc8936f0, // 0.94856, -0.31659 + 0x3fee529f04729ffc, 0xbfd472b8a5571054, // 0.94759, -0.3195 + 0x3fee4a8dff81ce5e, 0xbfd4a253d11b82f3, // 0.9466, -0.32241 + 0x3fee426a4b2bc17e, 0xbfd4d1e24278e76a, // 0.94561, -0.32531 + 0x3fee3a33ec75ce85, 0xbfd50163dc197047, // 0.9446, -0.32821 + 0x3fee31eae870ce25, 0xbfd530d880af3c24, // 0.94359, -0.33111 + 0x3fee298f4439197a, 0xbfd5604012f467b4, // 0.94257, -0.334 + 0x3fee212104f686e5, 0xbfd58f9a75ab1fdd, // 0.94154, -0.33689 + 0x3fee18a02fdc66d9, 0xbfd5bee78b9db3b6, // 0.94051, -0.33978 + 0x3fee100cca2980ac, 0xbfd5ee27379ea693, // 0.93946, -0.34266 + 0x3fee0766d9280f54, 0xbfd61d595c88c203, // 0.9384, -0.34554 + 0x3fedfeae622dbe2b, 0xbfd64c7ddd3f27c6, // 0.93734, -0.34842 + 0x3fedf5e36a9ba59c, 0xbfd67b949cad63ca, // 0.93627, -0.35129 + 0x3feded05f7de47da, 0xbfd6aa9d7dc77e16, // 0.93518, -0.35416 + 0x3fede4160f6d8d81, 0xbfd6d998638a0cb5, // 0.93409, -0.35703 + 0x3feddb13b6ccc23d, 0xbfd7088530fa459e, // 0.93299, -0.3599 + 0x3fedd1fef38a915a, 0xbfd73763c9261092, // 0.93188, -0.36276 + 0x3fedc8d7cb410260, 0xbfd766340f2418f6, // 0.93077, -0.36561 + 0x3fedbf9e4395759a, 0xbfd794f5e613dfae, // 0.92964, -0.36847 + 0x3fedb6526238a09b, 0xbfd7c3a9311dcce7, // 0.92851, -0.37132 + 0x3fedacf42ce68ab9, 0xbfd7f24dd37341e3, // 0.92736, -0.37416 + 0x3feda383a9668988, 0xbfd820e3b04eaac4, // 0.92621, -0.37701 + 0x3fed9a00dd8b3d46, 0xbfd84f6aaaf3903f, // 0.92505, -0.37985 + 0x3fed906bcf328d46, 0xbfd87de2a6aea963, // 0.92388, -0.38268 + 0x3fed86c48445a450, 0xbfd8ac4b86d5ed44, // 0.9227, -0.38552 + 0x3fed7d0b02b8ecf9, 0xbfd8daa52ec8a4af, // 0.92151, -0.38835 + 0x3fed733f508c0dff, 0xbfd908ef81ef7bd1, // 0.92032, -0.39117 + 0x3fed696173c9e68b, 0xbfd9372a63bc93d7, // 0.91911, -0.39399 + 0x3fed5f7172888a7f, 0xbfd96555b7ab948f, // 0.9179, -0.39681 + 0x3fed556f52e93eb1, 0xbfd993716141bdfe, // 0.91668, -0.39962 + 0x3fed4b5b1b187524, 0xbfd9c17d440df9f2, // 0.91545, -0.40243 + 0x3fed4134d14dc93a, 0xbfd9ef7943a8ed8a, // 0.91421, -0.40524 + 0x3fed36fc7bcbfbdc, 0xbfda1d6543b50ac0, // 0.91296, -0.40804 + 0x3fed2cb220e0ef9f, 0xbfda4b4127dea1e4, // 0.91171, -0.41084 + 0x3fed2255c6e5a4e1, 0xbfda790cd3dbf31a, // 0.91044, -0.41364 + 0x3fed17e7743e35dc, 0xbfdaa6c82b6d3fc9, // 0.90917, -0.41643 + 0x3fed0d672f59d2b9, 0xbfdad473125cdc08, // 0.90789, -0.41922 + 0x3fed02d4feb2bd92, 0xbfdb020d6c7f4009, // 0.9066, -0.422 + 0x3fecf830e8ce467b, 0xbfdb2f971db31972, // 0.9053, -0.42478 + 0x3feced7af43cc773, 0xbfdb5d1009e15cc0, // 0.90399, -0.42756 + 0x3fece2b32799a060, 0xbfdb8a7814fd5693, // 0.90267, -0.43033 + 0x3fecd7d9898b32f6, 0xbfdbb7cf2304bd01, // 0.90135, -0.43309 + 0x3fecccee20c2de9f, 0xbfdbe51517ffc0d9, // 0.90002, -0.43586 + 0x3fecc1f0f3fcfc5c, 0xbfdc1249d8011ee7, // 0.89867, -0.43862 + 0x3fecb6e20a00da99, 0xbfdc3f6d47263129, // 0.89732, -0.44137 + 0x3fecabc169a0b901, 0xbfdc6c7f4997000a, // 0.89597, -0.44412 + 0x3feca08f19b9c449, 0xbfdc997fc3865388, // 0.8946, -0.44687 + 0x3fec954b213411f5, 0xbfdcc66e9931c45d, // 0.89322, -0.44961 + 0x3fec89f587029c13, 0xbfdcf34baee1cd21, // 0.89184, -0.45235 + 0x3fec7e8e52233cf3, 0xbfdd2016e8e9db5b, // 0.89045, -0.45508 + 0x3fec7315899eaad7, 0xbfdd4cd02ba8609c, // 0.88905, -0.45781 + 0x3fec678b3488739b, 0xbfdd79775b86e389, // 0.88764, -0.46054 + 0x3fec5bef59fef85a, 0xbfdda60c5cfa10d8, // 0.88622, -0.46326 + 0x3fec5042012b6907, 0xbfddd28f1481cc58, // 0.8848, -0.46598 + 0x3fec44833141c004, 0xbfddfeff66a941de, // 0.88336, -0.46869 + 0x3fec38b2f180bdb1, 0xbfde2b5d3806f63b, // 0.88192, -0.4714 + 0x3fec2cd14931e3f1, 0xbfde57a86d3cd824, // 0.88047, -0.4741 + 0x3fec20de3fa971b0, 0xbfde83e0eaf85113, // 0.87901, -0.4768 + 0x3fec14d9dc465e58, 0xbfdeb00695f25620, // 0.87755, -0.47949 + 0x3fec08c426725549, 0xbfdedc1952ef78d5, // 0.87607, -0.48218 + 0x3febfc9d25a1b147, 0xbfdf081906bff7fd, // 0.87459, -0.48487 + 0x3febf064e15377dd, 0xbfdf3405963fd068, // 0.87309, -0.48755 + 0x3febe41b611154c1, 0xbfdf5fdee656cda3, // 0.8716, -0.49023 + 0x3febd7c0ac6f952a, 0xbfdf8ba4dbf89aba, // 0.87009, -0.4929 + 0x3febcb54cb0d2327, 0xbfdfb7575c24d2de, // 0.86857, -0.49557 + 0x3febbed7c49380ea, 0xbfdfe2f64be7120f, // 0.86705, -0.49823 + 0x3febb249a0b6c40d, 0xbfe00740c82b82e0, // 0.86551, -0.50089 + 0x3feba5aa673590d2, 0xbfe01cfc874c3eb7, // 0.86397, -0.50354 + 0x3feb98fa1fd9155e, 0xbfe032ae55edbd95, // 0.86242, -0.50619 + 0x3feb8c38d27504e9, 0xbfe0485626ae221a, // 0.86087, -0.50883 + 0x3feb7f6686e792ea, 0xbfe05df3ec31b8b6, // 0.8593, -0.51147 + 0x3feb728345196e3e, 0xbfe073879922ffed, // 0.85773, -0.5141 + 0x3feb658f14fdbc47, 0xbfe089112032b08c, // 0.85615, -0.51673 + 0x3feb5889fe921405, 0xbfe09e907417c5e1, // 0.85456, -0.51936 + 0x3feb4b7409de7925, 0xbfe0b405878f85ec, // 0.85296, -0.52198 + 0x3feb3e4d3ef55712, 0xbfe0c9704d5d898f, // 0.85136, -0.52459 + 0x3feb3115a5f37bf4, 0xbfe0ded0b84bc4b5, // 0.84974, -0.5272 + 0x3feb23cd470013b4, 0xbfe0f426bb2a8e7d, // 0.84812, -0.5298 + 0x3feb16742a4ca2f5, 0xbfe1097248d0a956, // 0.84649, -0.5324 + 0x3feb090a58150200, 0xbfe11eb3541b4b22, // 0.84485, -0.535 + 0x3feafb8fd89f57b6, 0xbfe133e9cfee254e, // 0.84321, -0.53759 + 0x3feaee04b43c1474, 0xbfe14915af336ceb, // 0.84155, -0.54017 + 0x3feae068f345ecef, 0xbfe15e36e4dbe2bc, // 0.83989, -0.54275 + 0x3fead2bc9e21d511, 0xbfe1734d63dedb49, // 0.83822, -0.54532 + 0x3feac4ffbd3efac8, 0xbfe188591f3a46e5, // 0.83655, -0.54789 + 0x3feab7325916c0d4, 0xbfe19d5a09f2b9b8, // 0.83486, -0.55046 + 0x3feaa9547a2cb98e, 0xbfe1b250171373be, // 0.83317, -0.55302 + 0x3fea9b66290ea1a3, 0xbfe1c73b39ae68c8, // 0.83147, -0.55557 + 0x3fea8d676e545ad2, 0xbfe1dc1b64dc4872, // 0.82976, -0.55812 + 0x3fea7f58529fe69d, 0xbfe1f0f08bbc861b, // 0.82805, -0.56066 + 0x3fea7138de9d60f5, 0xbfe205baa17560d6, // 0.82632, -0.5632 + 0x3fea63091b02fae2, 0xbfe21a799933eb58, // 0.82459, -0.56573 + 0x3fea54c91090f524, 0xbfe22f2d662c13e1, // 0.82285, -0.56826 + 0x3fea4678c8119ac8, 0xbfe243d5fb98ac1f, // 0.8211, -0.57078 + 0x3fea38184a593bc6, 0xbfe258734cbb7110, // 0.81935, -0.5733 + 0x3fea29a7a0462782, 0xbfe26d054cdd12df, // 0.81758, -0.57581 + 0x3fea1b26d2c0a75e, 0xbfe2818bef4d3cba, // 0.81581, -0.57831 + 0x3fea0c95eabaf937, 0xbfe2960727629ca8, // 0.81404, -0.58081 + 0x3fe9fdf4f13149de, 0xbfe2aa76e87aeb58, // 0.81225, -0.58331 + 0x3fe9ef43ef29af94, 0xbfe2bedb25faf3ea, // 0.81046, -0.5858 + 0x3fe9e082edb42472, 0xbfe2d333d34e9bb7, // 0.80866, -0.58828 + 0x3fe9d1b1f5ea80d6, 0xbfe2e780e3e8ea16, // 0.80685, -0.59076 + 0x3fe9c2d110f075c3, 0xbfe2fbc24b441015, // 0.80503, -0.59323 + 0x3fe9b3e047f38741, 0xbfe30ff7fce17035, // 0.80321, -0.5957 + 0x3fe9a4dfa42b06b2, 0xbfe32421ec49a620, // 0.80138, -0.59816 + 0x3fe995cf2ed80d22, 0xbfe338400d0c8e57, // 0.79954, -0.60062 + 0x3fe986aef1457594, 0xbfe34c5252c14de1, // 0.79769, -0.60307 + 0x3fe9777ef4c7d742, 0xbfe36058b10659f3, // 0.79584, -0.60551 + 0x3fe9683f42bd7fe1, 0xbfe374531b817f8d, // 0.79398, -0.60795 + 0x3fe958efe48e6dd7, 0xbfe3884185dfeb22, // 0.79211, -0.61038 + 0x3fe94990e3ac4a6c, 0xbfe39c23e3d63029, // 0.79023, -0.61281 + 0x3fe93a22499263fc, 0xbfe3affa292050b9, // 0.78835, -0.61523 + 0x3fe92aa41fc5a815, 0xbfe3c3c44981c517, // 0.78646, -0.61765 + 0x3fe91b166fd49da2, 0xbfe3d78238c58343, // 0.78456, -0.62006 + 0x3fe90b7943575efe, 0xbfe3eb33eabe0680, // 0.78265, -0.62246 + 0x3fe8fbcca3ef940d, 0xbfe3fed9534556d4, // 0.78074, -0.62486 + 0x3fe8ec109b486c49, 0xbfe41272663d108c, // 0.77882, -0.62725 + 0x3fe8dc45331698cc, 0xbfe425ff178e6bb1, // 0.77689, -0.62964 + 0x3fe8cc6a75184655, 0xbfe4397f5b2a4380, // 0.77495, -0.63202 + 0x3fe8bc806b151741, 0xbfe44cf325091dd6, // 0.77301, -0.63439 + 0x3fe8ac871ede1d88, 0xbfe4605a692b32a2, // 0.77106, -0.63676 + 0x3fe89c7e9a4dd4ab, 0xbfe473b51b987347, // 0.7691, -0.63912 + 0x3fe88c66e7481ba1, 0xbfe48703306091fe, // 0.76714, -0.64148 + 0x3fe87c400fba2ebf, 0xbfe49a449b9b0938, // 0.76517, -0.64383 + 0x3fe86c0a1d9aa195, 0xbfe4ad79516722f0, // 0.76319, -0.64618 + 0x3fe85bc51ae958cc, 0xbfe4c0a145ec0004, // 0.7612, -0.64851 + 0x3fe84b7111af83f9, 0xbfe4d3bc6d589f80, // 0.75921, -0.65085 + 0x3fe83b0e0bff976e, 0xbfe4e6cabbe3e5e9, // 0.75721, -0.65317 + 0x3fe82a9c13f545ff, 0xbfe4f9cc25cca486, // 0.7552, -0.65549 + 0x3fe81a1b33b57acc, 0xbfe50cc09f59a09b, // 0.75319, -0.65781 + 0x3fe8098b756e52fa, 0xbfe51fa81cd99aa6, // 0.75117, -0.66011 + 0x3fe7f8ece3571771, 0xbfe5328292a35596, // 0.74914, -0.66242 + 0x3fe7e83f87b03686, 0xbfe5454ff5159dfb, // 0.7471, -0.66471 + 0x3fe7d7836cc33db2, 0xbfe5581038975137, // 0.74506, -0.667 + 0x3fe7c6b89ce2d333, 0xbfe56ac35197649e, // 0.74301, -0.66928 + 0x3fe7b5df226aafb0, 0xbfe57d69348cec9f, // 0.74095, -0.67156 + 0x3fe7a4f707bf97d2, 0xbfe59001d5f723df, // 0.73889, -0.67383 + 0x3fe79400574f55e4, 0xbfe5a28d2a5d7250, // 0.73682, -0.67609 + 0x3fe782fb1b90b35b, 0xbfe5b50b264f7448, // 0.73474, -0.67835 + 0x3fe771e75f037261, 0xbfe5c77bbe65018c, // 0.73265, -0.6806 + 0x3fe760c52c304764, 0xbfe5d9dee73e345c, // 0.73056, -0.68285 + 0x3fe74f948da8d28d, 0xbfe5ec3495837074, // 0.72846, -0.68508 + 0x3fe73e558e079942, 0xbfe5fe7cbde56a0f, // 0.72636, -0.68732 + 0x3fe72d0837efff97, 0xbfe610b7551d2cde, // 0.72425, -0.68954 + 0x3fe71bac960e41bf, 0xbfe622e44fec22ff, // 0.72213, -0.69176 + 0x3fe70a42b3176d7a, 0xbfe63503a31c1be8, // 0.72, -0.69397 + 0x3fe6f8ca99c95b75, 0xbfe64715437f535b, // 0.71787, -0.69618 + 0x3fe6e74454eaa8ae, 0xbfe6591925f0783e, // 0.71573, -0.69838 + 0x3fe6d5afef4aafcc, 0xbfe66b0f3f52b386, // 0.71358, -0.70057 + 0x3fe6c40d73c18275, 0xbfe67cf78491af10, // 0.71143, -0.70275 + 0x3fe6b25ced2fe29c, 0xbfe68ed1eaa19c71, // 0.70927, -0.70493 + 0x3fe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // 0.70711, -0.70711 + 0x3fe68ed1eaa19c71, 0xbfe6b25ced2fe29c, // 0.70493, -0.70927 + 0x3fe67cf78491af10, 0xbfe6c40d73c18275, // 0.70275, -0.71143 + 0x3fe66b0f3f52b386, 0xbfe6d5afef4aafcc, // 0.70057, -0.71358 + 0x3fe6591925f0783e, 0xbfe6e74454eaa8ae, // 0.69838, -0.71573 + 0x3fe64715437f535b, 0xbfe6f8ca99c95b75, // 0.69618, -0.71787 + 0x3fe63503a31c1be8, 0xbfe70a42b3176d7a, // 0.69397, -0.72 + 0x3fe622e44fec22ff, 0xbfe71bac960e41bf, // 0.69176, -0.72213 + 0x3fe610b7551d2cde, 0xbfe72d0837efff97, // 0.68954, -0.72425 + 0x3fe5fe7cbde56a0f, 0xbfe73e558e079942, // 0.68732, -0.72636 + 0x3fe5ec3495837074, 0xbfe74f948da8d28d, // 0.68508, -0.72846 + 0x3fe5d9dee73e345c, 0xbfe760c52c304764, // 0.68285, -0.73056 + 0x3fe5c77bbe65018c, 0xbfe771e75f037261, // 0.6806, -0.73265 + 0x3fe5b50b264f7448, 0xbfe782fb1b90b35b, // 0.67835, -0.73474 + 0x3fe5a28d2a5d7250, 0xbfe79400574f55e4, // 0.67609, -0.73682 + 0x3fe59001d5f723df, 0xbfe7a4f707bf97d2, // 0.67383, -0.73889 + 0x3fe57d69348cec9f, 0xbfe7b5df226aafb0, // 0.67156, -0.74095 + 0x3fe56ac35197649e, 0xbfe7c6b89ce2d333, // 0.66928, -0.74301 + 0x3fe5581038975137, 0xbfe7d7836cc33db2, // 0.667, -0.74506 + 0x3fe5454ff5159dfb, 0xbfe7e83f87b03686, // 0.66471, -0.7471 + 0x3fe5328292a35596, 0xbfe7f8ece3571771, // 0.66242, -0.74914 + 0x3fe51fa81cd99aa6, 0xbfe8098b756e52fa, // 0.66011, -0.75117 + 0x3fe50cc09f59a09b, 0xbfe81a1b33b57acc, // 0.65781, -0.75319 + 0x3fe4f9cc25cca486, 0xbfe82a9c13f545ff, // 0.65549, -0.7552 + 0x3fe4e6cabbe3e5e9, 0xbfe83b0e0bff976e, // 0.65317, -0.75721 + 0x3fe4d3bc6d589f80, 0xbfe84b7111af83f9, // 0.65085, -0.75921 + 0x3fe4c0a145ec0004, 0xbfe85bc51ae958cc, // 0.64851, -0.7612 + 0x3fe4ad79516722f0, 0xbfe86c0a1d9aa195, // 0.64618, -0.76319 + 0x3fe49a449b9b0938, 0xbfe87c400fba2ebf, // 0.64383, -0.76517 + 0x3fe48703306091fe, 0xbfe88c66e7481ba1, // 0.64148, -0.76714 + 0x3fe473b51b987347, 0xbfe89c7e9a4dd4ab, // 0.63912, -0.7691 + 0x3fe4605a692b32a2, 0xbfe8ac871ede1d88, // 0.63676, -0.77106 + 0x3fe44cf325091dd6, 0xbfe8bc806b151741, // 0.63439, -0.77301 + 0x3fe4397f5b2a4380, 0xbfe8cc6a75184655, // 0.63202, -0.77495 + 0x3fe425ff178e6bb1, 0xbfe8dc45331698cc, // 0.62964, -0.77689 + 0x3fe41272663d108c, 0xbfe8ec109b486c49, // 0.62725, -0.77882 + 0x3fe3fed9534556d4, 0xbfe8fbcca3ef940d, // 0.62486, -0.78074 + 0x3fe3eb33eabe0680, 0xbfe90b7943575efe, // 0.62246, -0.78265 + 0x3fe3d78238c58343, 0xbfe91b166fd49da2, // 0.62006, -0.78456 + 0x3fe3c3c44981c517, 0xbfe92aa41fc5a815, // 0.61765, -0.78646 + 0x3fe3affa292050b9, 0xbfe93a22499263fc, // 0.61523, -0.78835 + 0x3fe39c23e3d63029, 0xbfe94990e3ac4a6c, // 0.61281, -0.79023 + 0x3fe3884185dfeb22, 0xbfe958efe48e6dd7, // 0.61038, -0.79211 + 0x3fe374531b817f8d, 0xbfe9683f42bd7fe1, // 0.60795, -0.79398 + 0x3fe36058b10659f3, 0xbfe9777ef4c7d742, // 0.60551, -0.79584 + 0x3fe34c5252c14de1, 0xbfe986aef1457594, // 0.60307, -0.79769 + 0x3fe338400d0c8e57, 0xbfe995cf2ed80d22, // 0.60062, -0.79954 + 0x3fe32421ec49a620, 0xbfe9a4dfa42b06b2, // 0.59816, -0.80138 + 0x3fe30ff7fce17035, 0xbfe9b3e047f38741, // 0.5957, -0.80321 + 0x3fe2fbc24b441015, 0xbfe9c2d110f075c3, // 0.59323, -0.80503 + 0x3fe2e780e3e8ea16, 0xbfe9d1b1f5ea80d6, // 0.59076, -0.80685 + 0x3fe2d333d34e9bb7, 0xbfe9e082edb42472, // 0.58828, -0.80866 + 0x3fe2bedb25faf3ea, 0xbfe9ef43ef29af94, // 0.5858, -0.81046 + 0x3fe2aa76e87aeb58, 0xbfe9fdf4f13149de, // 0.58331, -0.81225 + 0x3fe2960727629ca8, 0xbfea0c95eabaf937, // 0.58081, -0.81404 + 0x3fe2818bef4d3cba, 0xbfea1b26d2c0a75e, // 0.57831, -0.81581 + 0x3fe26d054cdd12df, 0xbfea29a7a0462782, // 0.57581, -0.81758 + 0x3fe258734cbb7110, 0xbfea38184a593bc6, // 0.5733, -0.81935 + 0x3fe243d5fb98ac1f, 0xbfea4678c8119ac8, // 0.57078, -0.8211 + 0x3fe22f2d662c13e1, 0xbfea54c91090f524, // 0.56826, -0.82285 + 0x3fe21a799933eb58, 0xbfea63091b02fae2, // 0.56573, -0.82459 + 0x3fe205baa17560d6, 0xbfea7138de9d60f5, // 0.5632, -0.82632 + 0x3fe1f0f08bbc861b, 0xbfea7f58529fe69d, // 0.56066, -0.82805 + 0x3fe1dc1b64dc4872, 0xbfea8d676e545ad2, // 0.55812, -0.82976 + 0x3fe1c73b39ae68c8, 0xbfea9b66290ea1a3, // 0.55557, -0.83147 + 0x3fe1b250171373be, 0xbfeaa9547a2cb98e, // 0.55302, -0.83317 + 0x3fe19d5a09f2b9b8, 0xbfeab7325916c0d4, // 0.55046, -0.83486 + 0x3fe188591f3a46e5, 0xbfeac4ffbd3efac8, // 0.54789, -0.83655 + 0x3fe1734d63dedb49, 0xbfead2bc9e21d511, // 0.54532, -0.83822 + 0x3fe15e36e4dbe2bc, 0xbfeae068f345ecef, // 0.54275, -0.83989 + 0x3fe14915af336ceb, 0xbfeaee04b43c1474, // 0.54017, -0.84155 + 0x3fe133e9cfee254e, 0xbfeafb8fd89f57b6, // 0.53759, -0.84321 + 0x3fe11eb3541b4b22, 0xbfeb090a58150200, // 0.535, -0.84485 + 0x3fe1097248d0a956, 0xbfeb16742a4ca2f5, // 0.5324, -0.84649 + 0x3fe0f426bb2a8e7d, 0xbfeb23cd470013b4, // 0.5298, -0.84812 + 0x3fe0ded0b84bc4b5, 0xbfeb3115a5f37bf4, // 0.5272, -0.84974 + 0x3fe0c9704d5d898f, 0xbfeb3e4d3ef55712, // 0.52459, -0.85136 + 0x3fe0b405878f85ec, 0xbfeb4b7409de7925, // 0.52198, -0.85296 + 0x3fe09e907417c5e1, 0xbfeb5889fe921405, // 0.51936, -0.85456 + 0x3fe089112032b08c, 0xbfeb658f14fdbc47, // 0.51673, -0.85615 + 0x3fe073879922ffed, 0xbfeb728345196e3e, // 0.5141, -0.85773 + 0x3fe05df3ec31b8b6, 0xbfeb7f6686e792ea, // 0.51147, -0.8593 + 0x3fe0485626ae221a, 0xbfeb8c38d27504e9, // 0.50883, -0.86087 + 0x3fe032ae55edbd95, 0xbfeb98fa1fd9155e, // 0.50619, -0.86242 + 0x3fe01cfc874c3eb7, 0xbfeba5aa673590d2, // 0.50354, -0.86397 + 0x3fe00740c82b82e0, 0xbfebb249a0b6c40d, // 0.50089, -0.86551 + 0x3fdfe2f64be7120f, 0xbfebbed7c49380ea, // 0.49823, -0.86705 + 0x3fdfb7575c24d2de, 0xbfebcb54cb0d2327, // 0.49557, -0.86857 + 0x3fdf8ba4dbf89aba, 0xbfebd7c0ac6f952a, // 0.4929, -0.87009 + 0x3fdf5fdee656cda3, 0xbfebe41b611154c1, // 0.49023, -0.8716 + 0x3fdf3405963fd068, 0xbfebf064e15377dd, // 0.48755, -0.87309 + 0x3fdf081906bff7fd, 0xbfebfc9d25a1b147, // 0.48487, -0.87459 + 0x3fdedc1952ef78d5, 0xbfec08c426725549, // 0.48218, -0.87607 + 0x3fdeb00695f25620, 0xbfec14d9dc465e58, // 0.47949, -0.87755 + 0x3fde83e0eaf85113, 0xbfec20de3fa971b0, // 0.4768, -0.87901 + 0x3fde57a86d3cd824, 0xbfec2cd14931e3f1, // 0.4741, -0.88047 + 0x3fde2b5d3806f63b, 0xbfec38b2f180bdb1, // 0.4714, -0.88192 + 0x3fddfeff66a941de, 0xbfec44833141c004, // 0.46869, -0.88336 + 0x3fddd28f1481cc58, 0xbfec5042012b6907, // 0.46598, -0.8848 + 0x3fdda60c5cfa10d8, 0xbfec5bef59fef85a, // 0.46326, -0.88622 + 0x3fdd79775b86e389, 0xbfec678b3488739b, // 0.46054, -0.88764 + 0x3fdd4cd02ba8609c, 0xbfec7315899eaad7, // 0.45781, -0.88905 + 0x3fdd2016e8e9db5b, 0xbfec7e8e52233cf3, // 0.45508, -0.89045 + 0x3fdcf34baee1cd21, 0xbfec89f587029c13, // 0.45235, -0.89184 + 0x3fdcc66e9931c45d, 0xbfec954b213411f5, // 0.44961, -0.89322 + 0x3fdc997fc3865388, 0xbfeca08f19b9c449, // 0.44687, -0.8946 + 0x3fdc6c7f4997000a, 0xbfecabc169a0b901, // 0.44412, -0.89597 + 0x3fdc3f6d47263129, 0xbfecb6e20a00da99, // 0.44137, -0.89732 + 0x3fdc1249d8011ee7, 0xbfecc1f0f3fcfc5c, // 0.43862, -0.89867 + 0x3fdbe51517ffc0d9, 0xbfecccee20c2de9f, // 0.43586, -0.90002 + 0x3fdbb7cf2304bd01, 0xbfecd7d9898b32f6, // 0.43309, -0.90135 + 0x3fdb8a7814fd5693, 0xbfece2b32799a060, // 0.43033, -0.90267 + 0x3fdb5d1009e15cc0, 0xbfeced7af43cc773, // 0.42756, -0.90399 + 0x3fdb2f971db31972, 0xbfecf830e8ce467b, // 0.42478, -0.9053 + 0x3fdb020d6c7f4009, 0xbfed02d4feb2bd92, // 0.422, -0.9066 + 0x3fdad473125cdc08, 0xbfed0d672f59d2b9, // 0.41922, -0.90789 + 0x3fdaa6c82b6d3fc9, 0xbfed17e7743e35dc, // 0.41643, -0.90917 + 0x3fda790cd3dbf31a, 0xbfed2255c6e5a4e1, // 0.41364, -0.91044 + 0x3fda4b4127dea1e4, 0xbfed2cb220e0ef9f, // 0.41084, -0.91171 + 0x3fda1d6543b50ac0, 0xbfed36fc7bcbfbdc, // 0.40804, -0.91296 + 0x3fd9ef7943a8ed8a, 0xbfed4134d14dc93a, // 0.40524, -0.91421 + 0x3fd9c17d440df9f2, 0xbfed4b5b1b187524, // 0.40243, -0.91545 + 0x3fd993716141bdfe, 0xbfed556f52e93eb1, // 0.39962, -0.91668 + 0x3fd96555b7ab948f, 0xbfed5f7172888a7f, // 0.39681, -0.9179 + 0x3fd9372a63bc93d7, 0xbfed696173c9e68b, // 0.39399, -0.91911 + 0x3fd908ef81ef7bd1, 0xbfed733f508c0dff, // 0.39117, -0.92032 + 0x3fd8daa52ec8a4af, 0xbfed7d0b02b8ecf9, // 0.38835, -0.92151 + 0x3fd8ac4b86d5ed44, 0xbfed86c48445a450, // 0.38552, -0.9227 + 0x3fd87de2a6aea963, 0xbfed906bcf328d46, // 0.38268, -0.92388 + 0x3fd84f6aaaf3903f, 0xbfed9a00dd8b3d46, // 0.37985, -0.92505 + 0x3fd820e3b04eaac4, 0xbfeda383a9668988, // 0.37701, -0.92621 + 0x3fd7f24dd37341e3, 0xbfedacf42ce68ab9, // 0.37416, -0.92736 + 0x3fd7c3a9311dcce7, 0xbfedb6526238a09b, // 0.37132, -0.92851 + 0x3fd794f5e613dfae, 0xbfedbf9e4395759a, // 0.36847, -0.92964 + 0x3fd766340f2418f6, 0xbfedc8d7cb410260, // 0.36561, -0.93077 + 0x3fd73763c9261092, 0xbfedd1fef38a915a, // 0.36276, -0.93188 + 0x3fd7088530fa459e, 0xbfeddb13b6ccc23d, // 0.3599, -0.93299 + 0x3fd6d998638a0cb5, 0xbfede4160f6d8d81, // 0.35703, -0.93409 + 0x3fd6aa9d7dc77e16, 0xbfeded05f7de47da, // 0.35416, -0.93518 + 0x3fd67b949cad63ca, 0xbfedf5e36a9ba59c, // 0.35129, -0.93627 + 0x3fd64c7ddd3f27c6, 0xbfedfeae622dbe2b, // 0.34842, -0.93734 + 0x3fd61d595c88c203, 0xbfee0766d9280f54, // 0.34554, -0.9384 + 0x3fd5ee27379ea693, 0xbfee100cca2980ac, // 0.34266, -0.93946 + 0x3fd5bee78b9db3b6, 0xbfee18a02fdc66d9, // 0.33978, -0.94051 + 0x3fd58f9a75ab1fdd, 0xbfee212104f686e5, // 0.33689, -0.94154 + 0x3fd5604012f467b4, 0xbfee298f4439197a, // 0.334, -0.94257 + 0x3fd530d880af3c24, 0xbfee31eae870ce25, // 0.33111, -0.94359 + 0x3fd50163dc197047, 0xbfee3a33ec75ce85, // 0.32821, -0.9446 + 0x3fd4d1e24278e76a, 0xbfee426a4b2bc17e, // 0.32531, -0.94561 + 0x3fd4a253d11b82f3, 0xbfee4a8dff81ce5e, // 0.32241, -0.9466 + 0x3fd472b8a5571054, 0xbfee529f04729ffc, // 0.3195, -0.94759 + 0x3fd44310dc8936f0, 0xbfee5a9d550467d3, // 0.31659, -0.94856 + 0x3fd4135c94176602, 0xbfee6288ec48e112, // 0.31368, -0.94953 + 0x3fd3e39be96ec271, 0xbfee6a61c55d53a7, // 0.31077, -0.95049 + 0x3fd3b3cefa0414b7, 0xbfee7227db6a9744, // 0.30785, -0.95144 + 0x3fd383f5e353b6aa, 0xbfee79db29a5165a, // 0.30493, -0.95238 + 0x3fd35410c2e18152, 0xbfee817bab4cd10d, // 0.30201, -0.95331 + 0x3fd3241fb638baaf, 0xbfee89095bad6025, // 0.29908, -0.95423 + 0x3fd2f422daec0386, 0xbfee9084361df7f3, // 0.29615, -0.95514 + 0x3fd2c41a4e954520, 0xbfee97ec36016b30, // 0.29322, -0.95605 + 0x3fd294062ed59f05, 0xbfee9f4156c62dda, // 0.29028, -0.95694 + 0x3fd263e6995554ba, 0xbfeea68393e65800, // 0.28735, -0.95783 + 0x3fd233bbabc3bb72, 0xbfeeadb2e8e7a88e, // 0.28441, -0.9587 + 0x3fd2038583d727bd, 0xbfeeb4cf515b8811, // 0.28146, -0.95957 + 0x3fd1d3443f4cdb3d, 0xbfeebbd8c8df0b74, // 0.27852, -0.96043 + 0x3fd1a2f7fbe8f243, 0xbfeec2cf4b1af6b2, // 0.27557, -0.96128 + 0x3fd172a0d7765177, 0xbfeec9b2d3c3bf84, // 0.27262, -0.96212 + 0x3fd1423eefc69378, 0xbfeed0835e999009, // 0.26967, -0.96295 + 0x3fd111d262b1f677, 0xbfeed740e7684963, // 0.26671, -0.96378 + 0x3fd0e15b4e1749cd, 0xbfeeddeb6a078651, // 0.26375, -0.96459 + 0x3fd0b0d9cfdbdb90, 0xbfeee482e25a9dbc, // 0.26079, -0.96539 + 0x3fd0804e05eb661e, 0xbfeeeb074c50a544, // 0.25783, -0.96619 + 0x3fd04fb80e37fdae, 0xbfeef178a3e473c2, // 0.25487, -0.96698 + 0x3fd01f1806b9fdd2, 0xbfeef7d6e51ca3c0, // 0.2519, -0.96775 + 0x3fcfdcdc1adfedf8, 0xbfeefe220c0b95ec, // 0.24893, -0.96852 + 0x3fcf7b7480bd3801, 0xbfef045a14cf738c, // 0.24596, -0.96928 + 0x3fcf19f97b215f1a, 0xbfef0a7efb9230d7, // 0.24298, -0.97003 + 0x3fceb86b462de348, 0xbfef1090bc898f5f, // 0.24, -0.97077 + 0x3fce56ca1e101a1b, 0xbfef168f53f7205d, // 0.23702, -0.9715 + 0x3fcdf5163f01099a, 0xbfef1c7abe284708, // 0.23404, -0.97223 + 0x3fcd934fe5454311, 0xbfef2252f7763ada, // 0.23106, -0.97294 + 0x3fcd31774d2cbdee, 0xbfef2817fc4609ce, // 0.22807, -0.97364 + 0x3fcccf8cb312b286, 0xbfef2dc9c9089a9d, // 0.22508, -0.97434 + 0x3fcc6d90535d74dc, 0xbfef33685a3aaef0, // 0.22209, -0.97503 + 0x3fcc0b826a7e4f63, 0xbfef38f3ac64e589, // 0.2191, -0.9757 + 0x3fcba96334f15dad, 0xbfef3e6bbc1bbc65, // 0.21611, -0.97637 + 0x3fcb4732ef3d6722, 0xbfef43d085ff92dd, // 0.21311, -0.97703 + 0x3fcae4f1d5f3b9ab, 0xbfef492206bcabb4, // 0.21011, -0.97768 + 0x3fca82a025b00451, 0xbfef4e603b0b2f2d, // 0.20711, -0.97832 + 0x3fca203e1b1831da, 0xbfef538b1faf2d07, // 0.20411, -0.97895 + 0x3fc9bdcbf2dc4366, 0xbfef58a2b1789e84, // 0.2011, -0.97957 + 0x3fc95b49e9b62af9, 0xbfef5da6ed43685d, // 0.1981, -0.98018 + 0x3fc8f8b83c69a60a, 0xbfef6297cff75cb0, // 0.19509, -0.98079 + 0x3fc8961727c41804, 0xbfef677556883cee, // 0.19208, -0.98138 + 0x3fc83366e89c64c5, 0xbfef6c3f7df5bbb7, // 0.18907, -0.98196 + 0x3fc7d0a7bbd2cb1b, 0xbfef70f6434b7eb7, // 0.18606, -0.98254 + 0x3fc76dd9de50bf31, 0xbfef7599a3a12077, // 0.18304, -0.98311 + 0x3fc70afd8d08c4ff, 0xbfef7a299c1a322a, // 0.18002, -0.98366 + 0x3fc6a81304f64ab2, 0xbfef7ea629e63d6e, // 0.177, -0.98421 + 0x3fc6451a831d830d, 0xbfef830f4a40c60c, // 0.17398, -0.98475 + 0x3fc5e214448b3fc6, 0xbfef8764fa714ba9, // 0.17096, -0.98528 + 0x3fc57f008654cbde, 0xbfef8ba737cb4b78, // 0.16794, -0.9858 + 0x3fc51bdf8597c5f2, 0xbfef8fd5ffae41db, // 0.16491, -0.98631 + 0x3fc4b8b17f79fa88, 0xbfef93f14f85ac08, // 0.16189, -0.98681 + 0x3fc45576b1293e5a, 0xbfef97f924c9099b, // 0.15886, -0.9873 + 0x3fc3f22f57db4893, 0xbfef9bed7cfbde29, // 0.15583, -0.98778 + 0x3fc38edbb0cd8d14, 0xbfef9fce55adb2c8, // 0.1528, -0.98826 + 0x3fc32b7bf94516a7, 0xbfefa39bac7a1791, // 0.14976, -0.98872 + 0x3fc2c8106e8e613a, 0xbfefa7557f08a517, // 0.14673, -0.98918 + 0x3fc264994dfd340a, 0xbfefaafbcb0cfddc, // 0.1437, -0.98962 + 0x3fc20116d4ec7bce, 0xbfefae8e8e46cfbb, // 0.14066, -0.99006 + 0x3fc19d8940be24e7, 0xbfefb20dc681d54d, // 0.13762, -0.99049 + 0x3fc139f0cedaf576, 0xbfefb5797195d741, // 0.13458, -0.9909 + 0x3fc0d64dbcb26786, 0xbfefb8d18d66adb7, // 0.13154, -0.99131 + 0x3fc072a047ba831d, 0xbfefbc1617e44186, // 0.1285, -0.99171 + 0x3fc00ee8ad6fb85b, 0xbfefbf470f0a8d88, // 0.12545, -0.9921 + 0x3fbf564e56a9730e, 0xbfefc26470e19fd3, // 0.12241, -0.99248 + 0x3fbe8eb7fde4aa3e, 0xbfefc56e3b7d9af6, // 0.11937, -0.99285 + 0x3fbdc70ecbae9fc8, 0xbfefc8646cfeb721, // 0.11632, -0.99321 + 0x3fbcff533b307dc1, 0xbfefcb4703914354, // 0.11327, -0.99356 + 0x3fbc3785c79ec2d5, 0xbfefce15fd6da67b, // 0.11022, -0.99391 + 0x3fbb6fa6ec38f64c, 0xbfefd0d158d86087, // 0.10717, -0.99424 + 0x3fbaa7b724495c04, 0xbfefd37914220b84, // 0.10412, -0.99456 + 0x3fb9dfb6eb24a85c, 0xbfefd60d2da75c9e, // 0.10107, -0.99488 + 0x3fb917a6bc29b42c, 0xbfefd88da3d12526, // 0.098017, -0.99518 + 0x3fb84f8712c130a0, 0xbfefdafa7514538c, // 0.094963, -0.99548 + 0x3fb787586a5d5b21, 0xbfefdd539ff1f456, // 0.091909, -0.99577 + 0x3fb6bf1b3e79b129, 0xbfefdf9922f73307, // 0.088854, -0.99604 + 0x3fb5f6d00a9aa419, 0xbfefe1cafcbd5b09, // 0.085797, -0.99631 + 0x3fb52e774a4d4d0a, 0xbfefe3e92be9d886, // 0.08274, -0.99657 + 0x3fb4661179272096, 0xbfefe5f3af2e3940, // 0.079682, -0.99682 + 0x3fb39d9f12c5a299, 0xbfefe7ea85482d60, // 0.076624, -0.99706 + 0x3fb2d52092ce19f6, 0xbfefe9cdad01883a, // 0.073565, -0.99729 + 0x3fb20c9674ed444c, 0xbfefeb9d2530410f, // 0.070505, -0.99751 + 0x3fb1440134d709b2, 0xbfefed58ecb673c4, // 0.067444, -0.99772 + 0x3fb07b614e463064, 0xbfefef0102826191, // 0.064383, -0.99793 + 0x3faf656e79f820e0, 0xbfeff095658e71ad, // 0.061321, -0.99812 + 0x3fadd406f9808ec8, 0xbfeff21614e131ed, // 0.058258, -0.9983 + 0x3fac428d12c0d7e3, 0xbfeff3830f8d575c, // 0.055195, -0.99848 + 0x3faab101bd5f8317, 0xbfeff4dc54b1bed3, // 0.052132, -0.99864 + 0x3fa91f65f10dd814, 0xbfeff621e3796d7e, // 0.049068, -0.9988 + 0x3fa78dbaa5874685, 0xbfeff753bb1b9164, // 0.046003, -0.99894 + 0x3fa5fc00d290cd43, 0xbfeff871dadb81df, // 0.042938, -0.99908 + 0x3fa46a396ff86179, 0xbfeff97c4208c014, // 0.039873, -0.9992 + 0x3fa2d865759455cd, 0xbfeffa72effef75d, // 0.036807, -0.99932 + 0x3fa14685db42c17e, 0xbfeffb55e425fdae, // 0.033741, -0.99943 + 0x3f9f693731d1cf01, 0xbfeffc251df1d3f8, // 0.030675, -0.99953 + 0x3f9c454f4ce53b1c, 0xbfeffce09ce2a679, // 0.027608, -0.99962 + 0x3f992155f7a3667e, 0xbfeffd886084cd0d, // 0.024541, -0.9997 + 0x3f95fd4d21fab226, 0xbfeffe1c6870cb77, // 0.021474, -0.99977 + 0x3f92d936bbe30efd, 0xbfeffe9cb44b51a1, // 0.018407, -0.99983 + 0x3f8f6a296ab997ca, 0xbfefff0943c53bd1, // 0.015339, -0.99988 + 0x3f8921d1fcdec784, 0xbfefff62169b92db, // 0.012272, -0.99992 + 0x3f82d96b0e509703, 0xbfefffa72c978c4f, //0.0092038, -0.99996 + 0x3f7921f0fe670071, 0xbfefffd8858e8a92, //0.0061359, -0.99998 + 0x3f6921f8becca4ba, 0xbfeffff621621d02, // 0.003068, -1 +}; +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F64_4096) +const uint64_t twiddleCoefF64_rfft_4096[4096] = { + 0x0000000000000000, 0x3ff0000000000000, // 0, 1 + 0x3f5921faaee6472d, 0x3feffffd88586ee6, // 0.001534, 1 + 0x3f6921f8becca4ba, 0x3feffff621621d02, // 0.003068, 1 + 0x3f72d97822f996bc, 0x3fefffe9cb1e2e8d, //0.0046019, 0.99999 + 0x3f7921f0fe670071, 0x3fefffd8858e8a92, //0.0061359, 0.99998 + 0x3f7f6a65f9a2a3c5, 0x3fefffc250b5daef, //0.0076698, 0.99997 + 0x3f82d96b0e509703, 0x3fefffa72c978c4f, //0.0092038, 0.99996 + 0x3f85fda037ac05e0, 0x3fefff871937ce2f, // 0.010738, 0.99994 + 0x3f8921d1fcdec784, 0x3fefff62169b92db, // 0.012272, 0.99992 + 0x3f8c45ffe1e48ad9, 0x3fefff3824c88f6f, // 0.013805, 0.9999 + 0x3f8f6a296ab997ca, 0x3fefff0943c53bd1, // 0.015339, 0.99988 + 0x3f9147270dad7132, 0x3feffed57398d2b7, // 0.016873, 0.99986 + 0x3f92d936bbe30efd, 0x3feffe9cb44b51a1, // 0.018407, 0.99983 + 0x3f946b4381fce81c, 0x3feffe5f05e578db, // 0.01994, 0.9998 + 0x3f95fd4d21fab226, 0x3feffe1c6870cb77, // 0.021474, 0.99977 + 0x3f978f535ddc9f03, 0x3feffdd4dbf78f52, // 0.023008, 0.99974 + 0x3f992155f7a3667e, 0x3feffd886084cd0d, // 0.024541, 0.9997 + 0x3f9ab354b1504fca, 0x3feffd36f624500c, // 0.026075, 0.99966 + 0x3f9c454f4ce53b1c, 0x3feffce09ce2a679, // 0.027608, 0.99962 + 0x3f9dd7458c64ab39, 0x3feffc8554cd213a, // 0.029142, 0.99958 + 0x3f9f693731d1cf01, 0x3feffc251df1d3f8, // 0.030675, 0.99953 + 0x3fa07d91ff984580, 0x3feffbbff85f9515, // 0.032208, 0.99948 + 0x3fa14685db42c17e, 0x3feffb55e425fdae, // 0.033741, 0.99943 + 0x3fa20f770ceb11c6, 0x3feffae6e1556998, // 0.035274, 0.99938 + 0x3fa2d865759455cd, 0x3feffa72effef75d, // 0.036807, 0.99932 + 0x3fa3a150f6421afc, 0x3feff9fa10348837, // 0.03834, 0.99926 + 0x3fa46a396ff86179, 0x3feff97c4208c014, // 0.039873, 0.9992 + 0x3fa5331ec3bba0eb, 0x3feff8f9858f058b, // 0.041406, 0.99914 + 0x3fa5fc00d290cd43, 0x3feff871dadb81df, // 0.042938, 0.99908 + 0x3fa6c4df7d7d5b84, 0x3feff7e5420320f9, // 0.044471, 0.99901 + 0x3fa78dbaa5874685, 0x3feff753bb1b9164, // 0.046003, 0.99894 + 0x3fa856922bb513c1, 0x3feff6bd463b444d, // 0.047535, 0.99887 + 0x3fa91f65f10dd814, 0x3feff621e3796d7e, // 0.049068, 0.9988 + 0x3fa9e835d6993c87, 0x3feff58192ee0358, // 0.0506, 0.99872 + 0x3faab101bd5f8317, 0x3feff4dc54b1bed3, // 0.052132, 0.99864 + 0x3fab79c986698b78, 0x3feff43228de1b77, // 0.053664, 0.99856 + 0x3fac428d12c0d7e3, 0x3feff3830f8d575c, // 0.055195, 0.99848 + 0x3fad0b4c436f91d0, 0x3feff2cf08da7321, // 0.056727, 0.99839 + 0x3fadd406f9808ec8, 0x3feff21614e131ed, // 0.058258, 0.9983 + 0x3fae9cbd15ff5527, 0x3feff15833be1965, // 0.05979, 0.99821 + 0x3faf656e79f820e0, 0x3feff095658e71ad, // 0.061321, 0.99812 + 0x3fb0170d833bf421, 0x3fefefcdaa704562, // 0.062852, 0.99802 + 0x3fb07b614e463064, 0x3fefef0102826191, // 0.064383, 0.99793 + 0x3fb0dfb28ea201e6, 0x3fefee2f6de455ba, // 0.065913, 0.99783 + 0x3fb1440134d709b2, 0x3fefed58ecb673c4, // 0.067444, 0.99772 + 0x3fb1a84d316d4f8a, 0x3fefec7d7f19cffc, // 0.068974, 0.99762 + 0x3fb20c9674ed444c, 0x3fefeb9d2530410f, // 0.070505, 0.99751 + 0x3fb270dcefdfc45b, 0x3fefeab7df1c6005, // 0.072035, 0.9974 + 0x3fb2d52092ce19f6, 0x3fefe9cdad01883a, // 0.073565, 0.99729 + 0x3fb339614e41ffa5, 0x3fefe8de8f03d75c, // 0.075094, 0.99718 + 0x3fb39d9f12c5a299, 0x3fefe7ea85482d60, // 0.076624, 0.99706 + 0x3fb401d9d0e3a507, 0x3fefe6f18ff42c84, // 0.078153, 0.99694 + 0x3fb4661179272096, 0x3fefe5f3af2e3940, // 0.079682, 0.99682 + 0x3fb4ca45fc1ba8b6, 0x3fefe4f0e31d7a4a, // 0.081211, 0.9967 + 0x3fb52e774a4d4d0a, 0x3fefe3e92be9d886, // 0.08274, 0.99657 + 0x3fb592a554489bc8, 0x3fefe2dc89bbff08, // 0.084269, 0.99644 + 0x3fb5f6d00a9aa419, 0x3fefe1cafcbd5b09, // 0.085797, 0.99631 + 0x3fb65af75dd0f87b, 0x3fefe0b485181be3, // 0.087326, 0.99618 + 0x3fb6bf1b3e79b129, 0x3fefdf9922f73307, // 0.088854, 0.99604 + 0x3fb7233b9d236e71, 0x3fefde78d68653fd, // 0.090381, 0.99591 + 0x3fb787586a5d5b21, 0x3fefdd539ff1f456, // 0.091909, 0.99577 + 0x3fb7eb7196b72ee4, 0x3fefdc297f674ba9, // 0.093436, 0.99563 + 0x3fb84f8712c130a0, 0x3fefdafa7514538c, // 0.094963, 0.99548 + 0x3fb8b398cf0c38e0, 0x3fefd9c68127c78c, // 0.09649, 0.99533 + 0x3fb917a6bc29b42c, 0x3fefd88da3d12526, // 0.098017, 0.99518 + 0x3fb97bb0caaba56f, 0x3fefd74fdd40abbf, // 0.099544, 0.99503 + 0x3fb9dfb6eb24a85c, 0x3fefd60d2da75c9e, // 0.10107, 0.99488 + 0x3fba43b90e27f3c4, 0x3fefd4c59536fae4, // 0.1026, 0.99472 + 0x3fbaa7b724495c04, 0x3fefd37914220b84, // 0.10412, 0.99456 + 0x3fbb0bb11e1d5559, 0x3fefd227aa9bd53b, // 0.10565, 0.9944 + 0x3fbb6fa6ec38f64c, 0x3fefd0d158d86087, // 0.10717, 0.99424 + 0x3fbbd3987f31fa0e, 0x3fefcf761f0c77a3, // 0.1087, 0.99407 + 0x3fbc3785c79ec2d5, 0x3fefce15fd6da67b, // 0.11022, 0.99391 + 0x3fbc9b6eb6165c42, 0x3fefccb0f4323aa3, // 0.11175, 0.99374 + 0x3fbcff533b307dc1, 0x3fefcb4703914354, // 0.11327, 0.99356 + 0x3fbd633347858ce4, 0x3fefc9d82bc2915e, // 0.11479, 0.99339 + 0x3fbdc70ecbae9fc8, 0x3fefc8646cfeb721, // 0.11632, 0.99321 + 0x3fbe2ae5b8457f77, 0x3fefc6ebc77f0887, // 0.11784, 0.99303 + 0x3fbe8eb7fde4aa3e, 0x3fefc56e3b7d9af6, // 0.11937, 0.99285 + 0x3fbef2858d27561b, 0x3fefc3ebc935454c, // 0.12089, 0.99267 + 0x3fbf564e56a9730e, 0x3fefc26470e19fd3, // 0.12241, 0.99248 + 0x3fbfba124b07ad85, 0x3fefc0d832bf043a, // 0.12393, 0.99229 + 0x3fc00ee8ad6fb85b, 0x3fefbf470f0a8d88, // 0.12545, 0.9921 + 0x3fc040c5bb67747e, 0x3fefbdb106021816, // 0.12698, 0.99191 + 0x3fc072a047ba831d, 0x3fefbc1617e44186, // 0.1285, 0.99171 + 0x3fc0a4784ab8bf1d, 0x3fefba7644f068b5, // 0.13002, 0.99151 + 0x3fc0d64dbcb26786, 0x3fefb8d18d66adb7, // 0.13154, 0.99131 + 0x3fc1082095f820b0, 0x3fefb727f187f1c7, // 0.13306, 0.99111 + 0x3fc139f0cedaf576, 0x3fefb5797195d741, // 0.13458, 0.9909 + 0x3fc16bbe5fac5865, 0x3fefb3c60dd2c199, // 0.1361, 0.9907 + 0x3fc19d8940be24e7, 0x3fefb20dc681d54d, // 0.13762, 0.99049 + 0x3fc1cf516a62a077, 0x3fefb0509be6f7db, // 0.13914, 0.99027 + 0x3fc20116d4ec7bce, 0x3fefae8e8e46cfbb, // 0.14066, 0.99006 + 0x3fc232d978aed413, 0x3fefacc79de6c44f, // 0.14218, 0.98984 + 0x3fc264994dfd340a, 0x3fefaafbcb0cfddc, // 0.1437, 0.98962 + 0x3fc296564d2b953e, 0x3fefa92b1600657c, // 0.14521, 0.9894 + 0x3fc2c8106e8e613a, 0x3fefa7557f08a517, // 0.14673, 0.98918 + 0x3fc2f9c7aa7a72af, 0x3fefa57b066e2754, // 0.14825, 0.98895 + 0x3fc32b7bf94516a7, 0x3fefa39bac7a1791, // 0.14976, 0.98872 + 0x3fc35d2d53440db2, 0x3fefa1b7717661d5, // 0.15128, 0.98849 + 0x3fc38edbb0cd8d14, 0x3fef9fce55adb2c8, // 0.1528, 0.98826 + 0x3fc3c0870a383ff6, 0x3fef9de0596b77a3, // 0.15431, 0.98802 + 0x3fc3f22f57db4893, 0x3fef9bed7cfbde29, // 0.15583, 0.98778 + 0x3fc423d4920e4166, 0x3fef99f5c0abd496, // 0.15734, 0.98754 + 0x3fc45576b1293e5a, 0x3fef97f924c9099b, // 0.15886, 0.9873 + 0x3fc48715ad84cdf5, 0x3fef95f7a9a1ec47, // 0.16037, 0.98706 + 0x3fc4b8b17f79fa88, 0x3fef93f14f85ac08, // 0.16189, 0.98681 + 0x3fc4ea4a1f624b61, 0x3fef91e616c43891, // 0.1634, 0.98656 + 0x3fc51bdf8597c5f2, 0x3fef8fd5ffae41db, // 0.16491, 0.98631 + 0x3fc54d71aa74ef02, 0x3fef8dc10a95380d, // 0.16643, 0.98605 + 0x3fc57f008654cbde, 0x3fef8ba737cb4b78, // 0.16794, 0.9858 + 0x3fc5b08c1192e381, 0x3fef898887a36c84, // 0.16945, 0.98554 + 0x3fc5e214448b3fc6, 0x3fef8764fa714ba9, // 0.17096, 0.98528 + 0x3fc61399179a6e94, 0x3fef853c9089595e, // 0.17247, 0.98501 + 0x3fc6451a831d830d, 0x3fef830f4a40c60c, // 0.17398, 0.98475 + 0x3fc676987f7216b8, 0x3fef80dd27ed8204, // 0.17549, 0.98448 + 0x3fc6a81304f64ab2, 0x3fef7ea629e63d6e, // 0.177, 0.98421 + 0x3fc6d98a0c08c8da, 0x3fef7c6a50826840, // 0.17851, 0.98394 + 0x3fc70afd8d08c4ff, 0x3fef7a299c1a322a, // 0.18002, 0.98366 + 0x3fc73c6d8055fe0a, 0x3fef77e40d068a90, // 0.18153, 0.98339 + 0x3fc76dd9de50bf31, 0x3fef7599a3a12077, // 0.18304, 0.98311 + 0x3fc79f429f59e11d, 0x3fef734a60446279, // 0.18455, 0.98282 + 0x3fc7d0a7bbd2cb1b, 0x3fef70f6434b7eb7, // 0.18606, 0.98254 + 0x3fc802092c1d744b, 0x3fef6e9d4d1262ca, // 0.18756, 0.98225 + 0x3fc83366e89c64c5, 0x3fef6c3f7df5bbb7, // 0.18907, 0.98196 + 0x3fc864c0e9b2b6cf, 0x3fef69dcd652f5de, // 0.19057, 0.98167 + 0x3fc8961727c41804, 0x3fef677556883cee, // 0.19208, 0.98138 + 0x3fc8c7699b34ca7e, 0x3fef6508fef47bd5, // 0.19359, 0.98108 + 0x3fc8f8b83c69a60a, 0x3fef6297cff75cb0, // 0.19509, 0.98079 + 0x3fc92a0303c8194f, 0x3fef6021c9f148c2, // 0.19659, 0.98048 + 0x3fc95b49e9b62af9, 0x3fef5da6ed43685d, // 0.1981, 0.98018 + 0x3fc98c8ce69a7aec, 0x3fef5b273a4fa2d9, // 0.1996, 0.97988 + 0x3fc9bdcbf2dc4366, 0x3fef58a2b1789e84, // 0.2011, 0.97957 + 0x3fc9ef0706e35a35, 0x3fef56195321c090, // 0.20261, 0.97926 + 0x3fca203e1b1831da, 0x3fef538b1faf2d07, // 0.20411, 0.97895 + 0x3fca517127e3dabc, 0x3fef50f81785c6b9, // 0.20561, 0.97863 + 0x3fca82a025b00451, 0x3fef4e603b0b2f2d, // 0.20711, 0.97832 + 0x3fcab3cb0ce6fe44, 0x3fef4bc38aa5c694, // 0.20861, 0.978 + 0x3fcae4f1d5f3b9ab, 0x3fef492206bcabb4, // 0.21011, 0.97768 + 0x3fcb16147941ca2a, 0x3fef467bafb7bbe0, // 0.21161, 0.97735 + 0x3fcb4732ef3d6722, 0x3fef43d085ff92dd, // 0.21311, 0.97703 + 0x3fcb784d30536cda, 0x3fef412089fd8adc, // 0.21461, 0.9767 + 0x3fcba96334f15dad, 0x3fef3e6bbc1bbc65, // 0.21611, 0.97637 + 0x3fcbda74f5856330, 0x3fef3bb21cc4fe47, // 0.2176, 0.97604 + 0x3fcc0b826a7e4f63, 0x3fef38f3ac64e589, // 0.2191, 0.9757 + 0x3fcc3c8b8c4b9dd7, 0x3fef36306b67c556, // 0.2206, 0.97536 + 0x3fcc6d90535d74dc, 0x3fef33685a3aaef0, // 0.22209, 0.97503 + 0x3fcc9e90b824a6a9, 0x3fef309b794b719f, // 0.22359, 0.97468 + 0x3fcccf8cb312b286, 0x3fef2dc9c9089a9d, // 0.22508, 0.97434 + 0x3fcd00843c99c5f9, 0x3fef2af349e17507, // 0.22658, 0.97399 + 0x3fcd31774d2cbdee, 0x3fef2817fc4609ce, // 0.22807, 0.97364 + 0x3fcd6265dd3f27e3, 0x3fef2537e0a71f9f, // 0.22957, 0.97329 + 0x3fcd934fe5454311, 0x3fef2252f7763ada, // 0.23106, 0.97294 + 0x3fcdc4355db40195, 0x3fef1f6941259d7a, // 0.23255, 0.97258 + 0x3fcdf5163f01099a, 0x3fef1c7abe284708, // 0.23404, 0.97223 + 0x3fce25f281a2b684, 0x3fef19876ef1f486, // 0.23553, 0.97187 + 0x3fce56ca1e101a1b, 0x3fef168f53f7205d, // 0.23702, 0.9715 + 0x3fce879d0cc0fdaf, 0x3fef13926dad024e, // 0.23851, 0.97114 + 0x3fceb86b462de348, 0x3fef1090bc898f5f, // 0.24, 0.97077 + 0x3fcee934c2d006c7, 0x3fef0d8a410379c5, // 0.24149, 0.9704 + 0x3fcf19f97b215f1a, 0x3fef0a7efb9230d7, // 0.24298, 0.97003 + 0x3fcf4ab9679c9f5c, 0x3fef076eecade0fa, // 0.24447, 0.96966 + 0x3fcf7b7480bd3801, 0x3fef045a14cf738c, // 0.24596, 0.96928 + 0x3fcfac2abeff57ff, 0x3fef014074708ed3, // 0.24744, 0.9689 + 0x3fcfdcdc1adfedf8, 0x3feefe220c0b95ec, // 0.24893, 0.96852 + 0x3fd006c4466e54af, 0x3feefafedc1ba8b7, // 0.25041, 0.96814 + 0x3fd01f1806b9fdd2, 0x3feef7d6e51ca3c0, // 0.2519, 0.96775 + 0x3fd037694a928cac, 0x3feef4aa278b2032, // 0.25338, 0.96737 + 0x3fd04fb80e37fdae, 0x3feef178a3e473c2, // 0.25487, 0.96698 + 0x3fd068044deab002, 0x3feeee425aa6b09a, // 0.25635, 0.96658 + 0x3fd0804e05eb661e, 0x3feeeb074c50a544, // 0.25783, 0.96619 + 0x3fd09895327b465e, 0x3feee7c77961dc9e, // 0.25931, 0.96579 + 0x3fd0b0d9cfdbdb90, 0x3feee482e25a9dbc, // 0.26079, 0.96539 + 0x3fd0c91bda4f158d, 0x3feee13987bbebdc, // 0.26227, 0.96499 + 0x3fd0e15b4e1749cd, 0x3feeddeb6a078651, // 0.26375, 0.96459 + 0x3fd0f998277733f7, 0x3feeda9889bfe86a, // 0.26523, 0.96418 + 0x3fd111d262b1f677, 0x3feed740e7684963, // 0.26671, 0.96378 + 0x3fd12a09fc0b1b12, 0x3feed3e483849c51, // 0.26819, 0.96337 + 0x3fd1423eefc69378, 0x3feed0835e999009, // 0.26967, 0.96295 + 0x3fd15a713a28b9d9, 0x3feecd1d792c8f10, // 0.27115, 0.96254 + 0x3fd172a0d7765177, 0x3feec9b2d3c3bf84, // 0.27262, 0.96212 + 0x3fd18acdc3f4873a, 0x3feec6436ee60309, // 0.2741, 0.9617 + 0x3fd1a2f7fbe8f243, 0x3feec2cf4b1af6b2, // 0.27557, 0.96128 + 0x3fd1bb1f7b999480, 0x3feebf5668eaf2ef, // 0.27705, 0.96086 + 0x3fd1d3443f4cdb3d, 0x3feebbd8c8df0b74, // 0.27852, 0.96043 + 0x3fd1eb6643499fbb, 0x3feeb8566b810f2a, // 0.27999, 0.96 + 0x3fd2038583d727bd, 0x3feeb4cf515b8811, // 0.28146, 0.95957 + 0x3fd21ba1fd3d2623, 0x3feeb1437af9bb34, // 0.28294, 0.95914 + 0x3fd233bbabc3bb72, 0x3feeadb2e8e7a88e, // 0.28441, 0.9587 + 0x3fd24bd28bb37672, 0x3feeaa1d9bb20af3, // 0.28588, 0.95827 + 0x3fd263e6995554ba, 0x3feea68393e65800, // 0.28735, 0.95783 + 0x3fd27bf7d0f2c346, 0x3feea2e4d212c000, // 0.28882, 0.95738 + 0x3fd294062ed59f05, 0x3fee9f4156c62dda, // 0.29028, 0.95694 + 0x3fd2ac11af483572, 0x3fee9b99229046f8, // 0.29175, 0.95649 + 0x3fd2c41a4e954520, 0x3fee97ec36016b30, // 0.29322, 0.95605 + 0x3fd2dc200907fe51, 0x3fee943a91aab4b4, // 0.29469, 0.95559 + 0x3fd2f422daec0386, 0x3fee9084361df7f3, // 0.29615, 0.95514 + 0x3fd30c22c08d6a13, 0x3fee8cc923edc388, // 0.29762, 0.95469 + 0x3fd3241fb638baaf, 0x3fee89095bad6025, // 0.29908, 0.95423 + 0x3fd33c19b83af207, 0x3fee8544ddf0d075, // 0.30054, 0.95377 + 0x3fd35410c2e18152, 0x3fee817bab4cd10d, // 0.30201, 0.95331 + 0x3fd36c04d27a4edf, 0x3fee7dadc456d850, // 0.30347, 0.95284 + 0x3fd383f5e353b6aa, 0x3fee79db29a5165a, // 0.30493, 0.95238 + 0x3fd39be3f1bc8aef, 0x3fee7603dbce74e9, // 0.30639, 0.95191 + 0x3fd3b3cefa0414b7, 0x3fee7227db6a9744, // 0.30785, 0.95144 + 0x3fd3cbb6f87a146e, 0x3fee6e472911da27, // 0.30931, 0.95096 + 0x3fd3e39be96ec271, 0x3fee6a61c55d53a7, // 0.31077, 0.95049 + 0x3fd3fb7dc932cfa4, 0x3fee6677b0e6d31e, // 0.31222, 0.95001 + 0x3fd4135c94176602, 0x3fee6288ec48e112, // 0.31368, 0.94953 + 0x3fd42b38466e2928, 0x3fee5e95781ebf1c, // 0.31514, 0.94905 + 0x3fd44310dc8936f0, 0x3fee5a9d550467d3, // 0.31659, 0.94856 + 0x3fd45ae652bb2800, 0x3fee56a083968eb1, // 0.31805, 0.94807 + 0x3fd472b8a5571054, 0x3fee529f04729ffc, // 0.3195, 0.94759 + 0x3fd48a87d0b07fd7, 0x3fee4e98d836c0af, // 0.32096, 0.94709 + 0x3fd4a253d11b82f3, 0x3fee4a8dff81ce5e, // 0.32241, 0.9466 + 0x3fd4ba1ca2eca31c, 0x3fee467e7af35f23, // 0.32386, 0.94611 + 0x3fd4d1e24278e76a, 0x3fee426a4b2bc17e, // 0.32531, 0.94561 + 0x3fd4e9a4ac15d520, 0x3fee3e5170cbfc46, // 0.32676, 0.94511 + 0x3fd50163dc197047, 0x3fee3a33ec75ce85, // 0.32821, 0.9446 + 0x3fd5191fceda3c35, 0x3fee3611becbaf69, // 0.32966, 0.9441 + 0x3fd530d880af3c24, 0x3fee31eae870ce25, // 0.33111, 0.94359 + 0x3fd5488dedeff3be, 0x3fee2dbf6a0911d9, // 0.33255, 0.94308 + 0x3fd5604012f467b4, 0x3fee298f4439197a, // 0.334, 0.94257 + 0x3fd577eeec151e47, 0x3fee255a77a63bb8, // 0.33545, 0.94206 + 0x3fd58f9a75ab1fdd, 0x3fee212104f686e5, // 0.33689, 0.94154 + 0x3fd5a742ac0ff78d, 0x3fee1ce2ecd0c0d8, // 0.33833, 0.94103 + 0x3fd5bee78b9db3b6, 0x3fee18a02fdc66d9, // 0.33978, 0.94051 + 0x3fd5d68910aee686, 0x3fee1458cec1ad83, // 0.34122, 0.93998 + 0x3fd5ee27379ea693, 0x3fee100cca2980ac, // 0.34266, 0.93946 + 0x3fd605c1fcc88f63, 0x3fee0bbc22bd8349, // 0.3441, 0.93893 + 0x3fd61d595c88c203, 0x3fee0766d9280f54, // 0.34554, 0.9384 + 0x3fd634ed533be58e, 0x3fee030cee1435b8, // 0.34698, 0.93787 + 0x3fd64c7ddd3f27c6, 0x3fedfeae622dbe2b, // 0.34842, 0.93734 + 0x3fd6640af6f03d9e, 0x3fedfa4b3621271d, // 0.34986, 0.9368 + 0x3fd67b949cad63ca, 0x3fedf5e36a9ba59c, // 0.35129, 0.93627 + 0x3fd6931acad55f51, 0x3fedf177004b2534, // 0.35273, 0.93573 + 0x3fd6aa9d7dc77e16, 0x3feded05f7de47da, // 0.35416, 0.93518 + 0x3fd6c21cb1e39771, 0x3fede890520465ce, // 0.3556, 0.93464 + 0x3fd6d998638a0cb5, 0x3fede4160f6d8d81, // 0.35703, 0.93409 + 0x3fd6f1108f1bc9c5, 0x3feddf9730ca837b, // 0.35846, 0.93354 + 0x3fd7088530fa459e, 0x3feddb13b6ccc23d, // 0.3599, 0.93299 + 0x3fd71ff6458782ec, 0x3fedd68ba2267a25, // 0.36133, 0.93244 + 0x3fd73763c9261092, 0x3fedd1fef38a915a, // 0.36276, 0.93188 + 0x3fd74ecdb8390a3e, 0x3fedcd6dabaca3a5, // 0.36418, 0.93133 + 0x3fd766340f2418f6, 0x3fedc8d7cb410260, // 0.36561, 0.93077 + 0x3fd77d96ca4b73a6, 0x3fedc43d52fcb453, // 0.36704, 0.93021 + 0x3fd794f5e613dfae, 0x3fedbf9e4395759a, // 0.36847, 0.92964 + 0x3fd7ac515ee2b172, 0x3fedbafa9dc1b78d, // 0.36989, 0.92907 + 0x3fd7c3a9311dcce7, 0x3fedb6526238a09b, // 0.37132, 0.92851 + 0x3fd7dafd592ba621, 0x3fedb1a591b20c38, // 0.37274, 0.92794 + 0x3fd7f24dd37341e3, 0x3fedacf42ce68ab9, // 0.37416, 0.92736 + 0x3fd8099a9c5c362d, 0x3feda83e348f613b, // 0.37559, 0.92679 + 0x3fd820e3b04eaac4, 0x3feda383a9668988, // 0.37701, 0.92621 + 0x3fd838290bb359c8, 0x3fed9ec48c26b1f3, // 0.37843, 0.92563 + 0x3fd84f6aaaf3903f, 0x3fed9a00dd8b3d46, // 0.37985, 0.92505 + 0x3fd866a88a792ea0, 0x3fed95389e50429b, // 0.38127, 0.92447 + 0x3fd87de2a6aea963, 0x3fed906bcf328d46, // 0.38268, 0.92388 + 0x3fd89518fbff098e, 0x3fed8b9a70ef9cb4, // 0.3841, 0.92329 + 0x3fd8ac4b86d5ed44, 0x3fed86c48445a450, // 0.38552, 0.9227 + 0x3fd8c37a439f884f, 0x3fed81ea09f38b63, // 0.38693, 0.92211 + 0x3fd8daa52ec8a4af, 0x3fed7d0b02b8ecf9, // 0.38835, 0.92151 + 0x3fd8f1cc44bea329, 0x3fed78276f5617c6, // 0.38976, 0.92092 + 0x3fd908ef81ef7bd1, 0x3fed733f508c0dff, // 0.39117, 0.92032 + 0x3fd9200ee2c9be97, 0x3fed6e52a71c8547, // 0.39258, 0.91972 + 0x3fd9372a63bc93d7, 0x3fed696173c9e68b, // 0.39399, 0.91911 + 0x3fd94e420137bce3, 0x3fed646bb7574de5, // 0.3954, 0.91851 + 0x3fd96555b7ab948f, 0x3fed5f7172888a7f, // 0.39681, 0.9179 + 0x3fd97c6583890fc2, 0x3fed5a72a6221e73, // 0.39822, 0.91729 + 0x3fd993716141bdfe, 0x3fed556f52e93eb1, // 0.39962, 0.91668 + 0x3fd9aa794d47c9ee, 0x3fed506779a3d2d9, // 0.40103, 0.91606 + 0x3fd9c17d440df9f2, 0x3fed4b5b1b187524, // 0.40243, 0.91545 + 0x3fd9d87d4207b0ab, 0x3fed464a380e7242, // 0.40384, 0.91483 + 0x3fd9ef7943a8ed8a, 0x3fed4134d14dc93a, // 0.40524, 0.91421 + 0x3fda067145664d57, 0x3fed3c1ae79f2b4e, // 0.40664, 0.91359 + 0x3fda1d6543b50ac0, 0x3fed36fc7bcbfbdc, // 0.40804, 0.91296 + 0x3fda34553b0afee5, 0x3fed31d98e9e503a, // 0.40944, 0.91234 + 0x3fda4b4127dea1e4, 0x3fed2cb220e0ef9f, // 0.41084, 0.91171 + 0x3fda622906a70b63, 0x3fed2786335f52fc, // 0.41224, 0.91107 + 0x3fda790cd3dbf31a, 0x3fed2255c6e5a4e1, // 0.41364, 0.91044 + 0x3fda8fec8bf5b166, 0x3fed1d20dc40c15c, // 0.41503, 0.90981 + 0x3fdaa6c82b6d3fc9, 0x3fed17e7743e35dc, // 0.41643, 0.90917 + 0x3fdabd9faebc3980, 0x3fed12a98fac410c, // 0.41782, 0.90853 + 0x3fdad473125cdc08, 0x3fed0d672f59d2b9, // 0.41922, 0.90789 + 0x3fdaeb4252ca07ab, 0x3fed082054168bac, // 0.42061, 0.90724 + 0x3fdb020d6c7f4009, 0x3fed02d4feb2bd92, // 0.422, 0.9066 + 0x3fdb18d45bf8aca6, 0x3fecfd852fff6ad4, // 0.42339, 0.90595 + 0x3fdb2f971db31972, 0x3fecf830e8ce467b, // 0.42478, 0.9053 + 0x3fdb4655ae2bf757, 0x3fecf2d829f1b40e, // 0.42617, 0.90464 + 0x3fdb5d1009e15cc0, 0x3feced7af43cc773, // 0.42756, 0.90399 + 0x3fdb73c62d520624, 0x3fece819488344ce, // 0.42894, 0.90333 + 0x3fdb8a7814fd5693, 0x3fece2b32799a060, // 0.43033, 0.90267 + 0x3fdba125bd63583e, 0x3fecdd489254fe65, // 0.43171, 0.90201 + 0x3fdbb7cf2304bd01, 0x3fecd7d9898b32f6, // 0.43309, 0.90135 + 0x3fdbce744262deee, 0x3fecd2660e12c1e6, // 0.43448, 0.90068 + 0x3fdbe51517ffc0d9, 0x3fecccee20c2de9f, // 0.43586, 0.90002 + 0x3fdbfbb1a05e0edc, 0x3fecc771c2736c09, // 0.43724, 0.89935 + 0x3fdc1249d8011ee7, 0x3fecc1f0f3fcfc5c, // 0.43862, 0.89867 + 0x3fdc28ddbb6cf145, 0x3fecbc6bb638d10b, // 0.43999, 0.898 + 0x3fdc3f6d47263129, 0x3fecb6e20a00da99, // 0.44137, 0.89732 + 0x3fdc55f877b23537, 0x3fecb153f02fb87d, // 0.44275, 0.89665 + 0x3fdc6c7f4997000a, 0x3fecabc169a0b901, // 0.44412, 0.89597 + 0x3fdc8301b95b40c2, 0x3feca62a772fd919, // 0.4455, 0.89528 + 0x3fdc997fc3865388, 0x3feca08f19b9c449, // 0.44687, 0.8946 + 0x3fdcaff964a0421d, 0x3fec9aef521bd480, // 0.44824, 0.89391 + 0x3fdcc66e9931c45d, 0x3fec954b213411f5, // 0.44961, 0.89322 + 0x3fdcdcdf5dc440ce, 0x3fec8fa287e13305, // 0.45098, 0.89253 + 0x3fdcf34baee1cd21, 0x3fec89f587029c13, // 0.45235, 0.89184 + 0x3fdd09b389152ec1, 0x3fec84441f785f61, // 0.45372, 0.89115 + 0x3fdd2016e8e9db5b, 0x3fec7e8e52233cf3, // 0.45508, 0.89045 + 0x3fdd3675caebf962, 0x3fec78d41fe4a267, // 0.45645, 0.88975 + 0x3fdd4cd02ba8609c, 0x3fec7315899eaad7, // 0.45781, 0.88905 + 0x3fdd632607ac9aa9, 0x3fec6d5290341eb2, // 0.45918, 0.88835 + 0x3fdd79775b86e389, 0x3fec678b3488739b, // 0.46054, 0.88764 + 0x3fdd8fc423c62a25, 0x3fec61bf777fcc48, // 0.4619, 0.88693 + 0x3fdda60c5cfa10d8, 0x3fec5bef59fef85a, // 0.46326, 0.88622 + 0x3fddbc5003b2edf8, 0x3fec561adceb743e, // 0.46462, 0.88551 + 0x3fddd28f1481cc58, 0x3fec5042012b6907, // 0.46598, 0.8848 + 0x3fdde8c98bf86bd6, 0x3fec4a64c7a5ac4c, // 0.46733, 0.88408 + 0x3fddfeff66a941de, 0x3fec44833141c004, // 0.46869, 0.88336 + 0x3fde1530a12779f4, 0x3fec3e9d3ee7d262, // 0.47004, 0.88264 + 0x3fde2b5d3806f63b, 0x3fec38b2f180bdb1, // 0.4714, 0.88192 + 0x3fde418527dc4ffa, 0x3fec32c449f60831, // 0.47275, 0.8812 + 0x3fde57a86d3cd824, 0x3fec2cd14931e3f1, // 0.4741, 0.88047 + 0x3fde6dc704be97e2, 0x3fec26d9f01f2eaf, // 0.47545, 0.87974 + 0x3fde83e0eaf85113, 0x3fec20de3fa971b0, // 0.4768, 0.87901 + 0x3fde99f61c817eda, 0x3fec1ade38bce19b, // 0.47815, 0.87828 + 0x3fdeb00695f25620, 0x3fec14d9dc465e58, // 0.47949, 0.87755 + 0x3fdec61253e3c61b, 0x3fec0ed12b3372e9, // 0.48084, 0.87681 + 0x3fdedc1952ef78d5, 0x3fec08c426725549, // 0.48218, 0.87607 + 0x3fdef21b8fafd3b5, 0x3fec02b2cef1e641, // 0.48353, 0.87533 + 0x3fdf081906bff7fd, 0x3febfc9d25a1b147, // 0.48487, 0.87459 + 0x3fdf1e11b4bbc35c, 0x3febf6832b71ec5b, // 0.48621, 0.87384 + 0x3fdf3405963fd068, 0x3febf064e15377dd, // 0.48755, 0.87309 + 0x3fdf49f4a7e97729, 0x3febea424837de6d, // 0.48889, 0.87235 + 0x3fdf5fdee656cda3, 0x3febe41b611154c1, // 0.49023, 0.8716 + 0x3fdf75c44e26a852, 0x3febddf02cd2b983, // 0.49156, 0.87084 + 0x3fdf8ba4dbf89aba, 0x3febd7c0ac6f952a, // 0.4929, 0.87009 + 0x3fdfa1808c6cf7e0, 0x3febd18ce0dc19d6, // 0.49423, 0.86933 + 0x3fdfb7575c24d2de, 0x3febcb54cb0d2327, // 0.49557, 0.86857 + 0x3fdfcd2947c1ff57, 0x3febc5186bf8361d, // 0.4969, 0.86781 + 0x3fdfe2f64be7120f, 0x3febbed7c49380ea, // 0.49823, 0.86705 + 0x3fdff8be6537615e, 0x3febb892d5d5dad5, // 0.49956, 0.86628 + 0x3fe00740c82b82e0, 0x3febb249a0b6c40d, // 0.50089, 0.86551 + 0x3fe0121fe4f56d2c, 0x3febabfc262e6586, // 0.50221, 0.86474 + 0x3fe01cfc874c3eb7, 0x3feba5aa673590d2, // 0.50354, 0.86397 + 0x3fe027d6ad83287e, 0x3feb9f5464c5bffc, // 0.50486, 0.8632 + 0x3fe032ae55edbd95, 0x3feb98fa1fd9155e, // 0.50619, 0.86242 + 0x3fe03d837edff370, 0x3feb929b996a5b7f, // 0.50751, 0.86165 + 0x3fe0485626ae221a, 0x3feb8c38d27504e9, // 0.50883, 0.86087 + 0x3fe053264bad0483, 0x3feb85d1cbf52c02, // 0.51015, 0.86009 + 0x3fe05df3ec31b8b6, 0x3feb7f6686e792ea, // 0.51147, 0.8593 + 0x3fe068bf0691c028, 0x3feb78f70449a34b, // 0.51279, 0.85852 + 0x3fe073879922ffed, 0x3feb728345196e3e, // 0.5141, 0.85773 + 0x3fe07e4da23bc102, 0x3feb6c0b4a55ac17, // 0.51542, 0.85694 + 0x3fe089112032b08c, 0x3feb658f14fdbc47, // 0.51673, 0.85615 + 0x3fe093d2115ee018, 0x3feb5f0ea611a532, // 0.51804, 0.85535 + 0x3fe09e907417c5e1, 0x3feb5889fe921405, // 0.51936, 0.85456 + 0x3fe0a94c46b53d0b, 0x3feb52011f805c92, // 0.52067, 0.85376 + 0x3fe0b405878f85ec, 0x3feb4b7409de7925, // 0.52198, 0.85296 + 0x3fe0bebc34ff4646, 0x3feb44e2beaf0a61, // 0.52328, 0.85216 + 0x3fe0c9704d5d898f, 0x3feb3e4d3ef55712, // 0.52459, 0.85136 + 0x3fe0d421cf03c12b, 0x3feb37b38bb54c09, // 0.5259, 0.85055 + 0x3fe0ded0b84bc4b5, 0x3feb3115a5f37bf4, // 0.5272, 0.84974 + 0x3fe0e97d078fd23b, 0x3feb2a738eb51f33, // 0.5285, 0.84893 + 0x3fe0f426bb2a8e7d, 0x3feb23cd470013b4, // 0.5298, 0.84812 + 0x3fe0fecdd1770537, 0x3feb1d22cfdadcc6, // 0.5311, 0.84731 + 0x3fe1097248d0a956, 0x3feb16742a4ca2f5, // 0.5324, 0.84649 + 0x3fe114141f935545, 0x3feb0fc1575d33db, // 0.5337, 0.84567 + 0x3fe11eb3541b4b22, 0x3feb090a58150200, // 0.535, 0.84485 + 0x3fe1294fe4c5350a, 0x3feb024f2d7d24a9, // 0.53629, 0.84403 + 0x3fe133e9cfee254e, 0x3feafb8fd89f57b6, // 0.53759, 0.84321 + 0x3fe13e8113f396c1, 0x3feaf4cc5a85fb73, // 0.53888, 0.84238 + 0x3fe14915af336ceb, 0x3feaee04b43c1474, // 0.54017, 0.84155 + 0x3fe153a7a00bf453, 0x3feae738e6cd4b67, // 0.54146, 0.84073 + 0x3fe15e36e4dbe2bc, 0x3feae068f345ecef, // 0.54275, 0.83989 + 0x3fe168c37c025764, 0x3fead994dab2e979, // 0.54404, 0.83906 + 0x3fe1734d63dedb49, 0x3fead2bc9e21d511, // 0.54532, 0.83822 + 0x3fe17dd49ad16161, 0x3feacbe03ea0e73b, // 0.54661, 0.83739 + 0x3fe188591f3a46e5, 0x3feac4ffbd3efac8, // 0.54789, 0.83655 + 0x3fe192daef7a5386, 0x3feabe1b1b0b8dac, // 0.54918, 0.83571 + 0x3fe19d5a09f2b9b8, 0x3feab7325916c0d4, // 0.55046, 0.83486 + 0x3fe1a7d66d0516e6, 0x3feab045787157ff, // 0.55174, 0.83402 + 0x3fe1b250171373be, 0x3feaa9547a2cb98e, // 0.55302, 0.83317 + 0x3fe1bcc706804467, 0x3feaa25f5f5aee60, // 0.55429, 0.83232 + 0x3fe1c73b39ae68c8, 0x3fea9b66290ea1a3, // 0.55557, 0.83147 + 0x3fe1d1acaf012cc2, 0x3fea9468d85b20ae, // 0.55685, 0.83062 + 0x3fe1dc1b64dc4872, 0x3fea8d676e545ad2, // 0.55812, 0.82976 + 0x3fe1e68759a3e074, 0x3fea8661ec0ee133, // 0.55939, 0.8289 + 0x3fe1f0f08bbc861b, 0x3fea7f58529fe69d, // 0.56066, 0.82805 + 0x3fe1fb56f98b37b8, 0x3fea784aa31d3f55, // 0.56193, 0.82718 + 0x3fe205baa17560d6, 0x3fea7138de9d60f5, // 0.5632, 0.82632 + 0x3fe2101b81e0da78, 0x3fea6a230637623b, // 0.56447, 0.82546 + 0x3fe21a799933eb58, 0x3fea63091b02fae2, // 0.56573, 0.82459 + 0x3fe224d4e5d5482e, 0x3fea5beb1e188375, // 0.567, 0.82372 + 0x3fe22f2d662c13e1, 0x3fea54c91090f524, // 0.56826, 0.82285 + 0x3fe23983189fdfd5, 0x3fea4da2f385e997, // 0.56952, 0.82198 + 0x3fe243d5fb98ac1f, 0x3fea4678c8119ac8, // 0.57078, 0.8211 + 0x3fe24e260d7ee7c9, 0x3fea3f4a8f4ee2d2, // 0.57204, 0.82023 + 0x3fe258734cbb7110, 0x3fea38184a593bc6, // 0.5733, 0.81935 + 0x3fe262bdb7b795a2, 0x3fea30e1fa4cbf81, // 0.57455, 0.81847 + 0x3fe26d054cdd12df, 0x3fea29a7a0462782, // 0.57581, 0.81758 + 0x3fe2774a0a961612, 0x3fea22693d62ccb9, // 0.57706, 0.8167 + 0x3fe2818bef4d3cba, 0x3fea1b26d2c0a75e, // 0.57831, 0.81581 + 0x3fe28bcaf96d94ba, 0x3fea13e0617e4ec7, // 0.57956, 0.81493 + 0x3fe2960727629ca8, 0x3fea0c95eabaf937, // 0.58081, 0.81404 + 0x3fe2a040779843fb, 0x3fea05476f967bb5, // 0.58206, 0.81314 + 0x3fe2aa76e87aeb58, 0x3fe9fdf4f13149de, // 0.58331, 0.81225 + 0x3fe2b4aa787764c4, 0x3fe9f69e70ac75bc, // 0.58455, 0.81135 + 0x3fe2bedb25faf3ea, 0x3fe9ef43ef29af94, // 0.5858, 0.81046 + 0x3fe2c908ef734e57, 0x3fe9e7e56dcb45bd, // 0.58704, 0.80956 + 0x3fe2d333d34e9bb7, 0x3fe9e082edb42472, // 0.58828, 0.80866 + 0x3fe2dd5bcffb7616, 0x3fe9d91c7007d5a6, // 0.58952, 0.80775 + 0x3fe2e780e3e8ea16, 0x3fe9d1b1f5ea80d6, // 0.59076, 0.80685 + 0x3fe2f1a30d86773a, 0x3fe9ca438080eadb, // 0.592, 0.80594 + 0x3fe2fbc24b441015, 0x3fe9c2d110f075c3, // 0.59323, 0.80503 + 0x3fe305de9b921a94, 0x3fe9bb5aa85f2098, // 0.59447, 0.80412 + 0x3fe30ff7fce17035, 0x3fe9b3e047f38741, // 0.5957, 0.80321 + 0x3fe31a0e6da35e44, 0x3fe9ac61f0d4e247, // 0.59693, 0.80229 + 0x3fe32421ec49a620, 0x3fe9a4dfa42b06b2, // 0.59816, 0.80138 + 0x3fe32e3277467d6b, 0x3fe99d59631e65d5, // 0.59939, 0.80046 + 0x3fe338400d0c8e57, 0x3fe995cf2ed80d22, // 0.60062, 0.79954 + 0x3fe3424aac0ef7d6, 0x3fe98e410881a600, // 0.60184, 0.79861 + 0x3fe34c5252c14de1, 0x3fe986aef1457594, // 0.60307, 0.79769 + 0x3fe35656ff9799ae, 0x3fe97f18ea4e5c9e, // 0.60429, 0.79676 + 0x3fe36058b10659f3, 0x3fe9777ef4c7d742, // 0.60551, 0.79584 + 0x3fe36a576582831b, 0x3fe96fe111ddfce0, // 0.60673, 0.79491 + 0x3fe374531b817f8d, 0x3fe9683f42bd7fe1, // 0.60795, 0.79398 + 0x3fe37e4bd1792fe2, 0x3fe960998893ad8c, // 0.60917, 0.79304 + 0x3fe3884185dfeb22, 0x3fe958efe48e6dd7, // 0.61038, 0.79211 + 0x3fe39234372c7f04, 0x3fe9514257dc4335, // 0.6116, 0.79117 + 0x3fe39c23e3d63029, 0x3fe94990e3ac4a6c, // 0.61281, 0.79023 + 0x3fe3a6108a54ba58, 0x3fe941db892e3a65, // 0.61402, 0.78929 + 0x3fe3affa292050b9, 0x3fe93a22499263fc, // 0.61523, 0.78835 + 0x3fe3b9e0beb19e18, 0x3fe932652609b1cf, // 0.61644, 0.7874 + 0x3fe3c3c44981c517, 0x3fe92aa41fc5a815, // 0.61765, 0.78646 + 0x3fe3cda4c80a6076, 0x3fe922df37f8646a, // 0.61885, 0.78551 + 0x3fe3d78238c58343, 0x3fe91b166fd49da2, // 0.62006, 0.78456 + 0x3fe3e15c9a2db922, 0x3fe91349c88da398, // 0.62126, 0.7836 + 0x3fe3eb33eabe0680, 0x3fe90b7943575efe, // 0.62246, 0.78265 + 0x3fe3f50828f1e8d2, 0x3fe903a4e1665133, // 0.62366, 0.78169 + 0x3fe3fed9534556d4, 0x3fe8fbcca3ef940d, // 0.62486, 0.78074 + 0x3fe408a76834c0c0, 0x3fe8f3f08c28d9ac, // 0.62606, 0.77978 + 0x3fe41272663d108c, 0x3fe8ec109b486c49, // 0.62725, 0.77882 + 0x3fe41c3a4bdbaa26, 0x3fe8e42cd2852e0a, // 0.62845, 0.77785 + 0x3fe425ff178e6bb1, 0x3fe8dc45331698cc, // 0.62964, 0.77689 + 0x3fe42fc0c7d3adbb, 0x3fe8d459be34bdfa, // 0.63083, 0.77592 + 0x3fe4397f5b2a4380, 0x3fe8cc6a75184655, // 0.63202, 0.77495 + 0x3fe4433ad0117b1d, 0x3fe8c47758fa71cb, // 0.63321, 0.77398 + 0x3fe44cf325091dd6, 0x3fe8bc806b151741, // 0.63439, 0.77301 + 0x3fe456a858917046, 0x3fe8b485aca2a468, // 0.63558, 0.77204 + 0x3fe4605a692b32a2, 0x3fe8ac871ede1d88, // 0.63676, 0.77106 + 0x3fe46a095557a0f1, 0x3fe8a484c3031d50, // 0.63794, 0.77008 + 0x3fe473b51b987347, 0x3fe89c7e9a4dd4ab, // 0.63912, 0.7691 + 0x3fe47d5dba6fde01, 0x3fe89474a5fb0a84, // 0.6403, 0.76812 + 0x3fe48703306091fe, 0x3fe88c66e7481ba1, // 0.64148, 0.76714 + 0x3fe490a57bedbcdf, 0x3fe884555f72fa6b, // 0.64266, 0.76615 + 0x3fe49a449b9b0938, 0x3fe87c400fba2ebf, // 0.64383, 0.76517 + 0x3fe4a3e08dec9ed6, 0x3fe87426f95cd5bd, // 0.645, 0.76418 + 0x3fe4ad79516722f0, 0x3fe86c0a1d9aa195, // 0.64618, 0.76319 + 0x3fe4b70ee48fb869, 0x3fe863e97db3d95a, // 0.64735, 0.7622 + 0x3fe4c0a145ec0004, 0x3fe85bc51ae958cc, // 0.64851, 0.7612 + 0x3fe4ca30740218a3, 0x3fe8539cf67c9029, // 0.64968, 0.76021 + 0x3fe4d3bc6d589f80, 0x3fe84b7111af83f9, // 0.65085, 0.75921 + 0x3fe4dd453076b064, 0x3fe843416dc4cce2, // 0.65201, 0.75821 + 0x3fe4e6cabbe3e5e9, 0x3fe83b0e0bff976e, // 0.65317, 0.75721 + 0x3fe4f04d0e2859aa, 0x3fe832d6eda3a3e0, // 0.65433, 0.75621 + 0x3fe4f9cc25cca486, 0x3fe82a9c13f545ff, // 0.65549, 0.7552 + 0x3fe503480159ded2, 0x3fe8225d803964e5, // 0.65665, 0.75419 + 0x3fe50cc09f59a09b, 0x3fe81a1b33b57acc, // 0.65781, 0.75319 + 0x3fe51635fe5601d7, 0x3fe811d52faf94dc, // 0.65896, 0.75218 + 0x3fe51fa81cd99aa6, 0x3fe8098b756e52fa, // 0.66011, 0.75117 + 0x3fe52916f96f8388, 0x3fe8013e0638e795, // 0.66127, 0.75015 + 0x3fe5328292a35596, 0x3fe7f8ece3571771, // 0.66242, 0.74914 + 0x3fe53beae7012abe, 0x3fe7f0980e113978, // 0.66356, 0.74812 + 0x3fe5454ff5159dfb, 0x3fe7e83f87b03686, // 0.66471, 0.7471 + 0x3fe54eb1bb6dcb8f, 0x3fe7dfe3517d8937, // 0.66586, 0.74608 + 0x3fe5581038975137, 0x3fe7d7836cc33db2, // 0.667, 0.74506 + 0x3fe5616b6b204e6e, 0x3fe7cf1fdacbf179, // 0.66814, 0.74403 + 0x3fe56ac35197649e, 0x3fe7c6b89ce2d333, // 0.66928, 0.74301 + 0x3fe57417ea8bb75c, 0x3fe7be4db453a27c, // 0.67042, 0.74198 + 0x3fe57d69348cec9f, 0x3fe7b5df226aafb0, // 0.67156, 0.74095 + 0x3fe586b72e2b2cfd, 0x3fe7ad6ce874dbb6, // 0.67269, 0.73992 + 0x3fe59001d5f723df, 0x3fe7a4f707bf97d2, // 0.67383, 0.73889 + 0x3fe599492a81ffbc, 0x3fe79c7d8198e56e, // 0.67496, 0.73785 + 0x3fe5a28d2a5d7250, 0x3fe79400574f55e4, // 0.67609, 0.73682 + 0x3fe5abcdd41bb0d8, 0x3fe78b7f8a320a52, // 0.67722, 0.73578 + 0x3fe5b50b264f7448, 0x3fe782fb1b90b35b, // 0.67835, 0.73474 + 0x3fe5be451f8bf980, 0x3fe77a730cbb9100, // 0.67948, 0.7337 + 0x3fe5c77bbe65018c, 0x3fe771e75f037261, // 0.6806, 0.73265 + 0x3fe5d0af016ed1d4, 0x3fe7695813b9b594, // 0.68172, 0.73161 + 0x3fe5d9dee73e345c, 0x3fe760c52c304764, // 0.68285, 0.73056 + 0x3fe5e30b6e6877f3, 0x3fe7582ea9b9a329, // 0.68397, 0.72951 + 0x3fe5ec3495837074, 0x3fe74f948da8d28d, // 0.68508, 0.72846 + 0x3fe5f55a5b2576f8, 0x3fe746f6d9516d59, // 0.6862, 0.72741 + 0x3fe5fe7cbde56a0f, 0x3fe73e558e079942, // 0.68732, 0.72636 + 0x3fe6079bbc5aadfa, 0x3fe735b0ad2009b2, // 0.68843, 0.7253 + 0x3fe610b7551d2cde, 0x3fe72d0837efff97, // 0.68954, 0.72425 + 0x3fe619cf86c55702, 0x3fe7245c2fcd492a, // 0.69065, 0.72319 + 0x3fe622e44fec22ff, 0x3fe71bac960e41bf, // 0.69176, 0.72213 + 0x3fe62bf5af2b0dfd, 0x3fe712f96c09d18d, // 0.69287, 0.72107 + 0x3fe63503a31c1be8, 0x3fe70a42b3176d7a, // 0.69397, 0.72 + 0x3fe63e0e2a59d7aa, 0x3fe701886c8f16e6, // 0.69508, 0.71894 + 0x3fe64715437f535b, 0x3fe6f8ca99c95b75, // 0.69618, 0.71787 + 0x3fe65018ed28287f, 0x3fe6f0093c1f54de, // 0.69728, 0.7168 + 0x3fe6591925f0783e, 0x3fe6e74454eaa8ae, // 0.69838, 0.71573 + 0x3fe66215ec74eb91, 0x3fe6de7be585881d, // 0.69947, 0.71466 + 0x3fe66b0f3f52b386, 0x3fe6d5afef4aafcc, // 0.70057, 0.71358 + 0x3fe674051d27896c, 0x3fe6cce07395679f, // 0.70166, 0.71251 + 0x3fe67cf78491af10, 0x3fe6c40d73c18275, // 0.70275, 0.71143 + 0x3fe685e6742feeef, 0x3fe6bb36f12b5e06, // 0.70385, 0.71035 + 0x3fe68ed1eaa19c71, 0x3fe6b25ced2fe29c, // 0.70493, 0.70927 + 0x3fe697b9e686941c, 0x3fe6a97f692c82ea, // 0.70602, 0.70819 + 0x3fe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // 0.70711, 0.70711 + 0x3fe6a97f692c82ea, 0x3fe697b9e686941c, // 0.70819, 0.70602 + 0x3fe6b25ced2fe29c, 0x3fe68ed1eaa19c71, // 0.70927, 0.70493 + 0x3fe6bb36f12b5e06, 0x3fe685e6742feeef, // 0.71035, 0.70385 + 0x3fe6c40d73c18275, 0x3fe67cf78491af10, // 0.71143, 0.70275 + 0x3fe6cce07395679f, 0x3fe674051d27896c, // 0.71251, 0.70166 + 0x3fe6d5afef4aafcc, 0x3fe66b0f3f52b386, // 0.71358, 0.70057 + 0x3fe6de7be585881d, 0x3fe66215ec74eb91, // 0.71466, 0.69947 + 0x3fe6e74454eaa8ae, 0x3fe6591925f0783e, // 0.71573, 0.69838 + 0x3fe6f0093c1f54de, 0x3fe65018ed28287f, // 0.7168, 0.69728 + 0x3fe6f8ca99c95b75, 0x3fe64715437f535b, // 0.71787, 0.69618 + 0x3fe701886c8f16e6, 0x3fe63e0e2a59d7aa, // 0.71894, 0.69508 + 0x3fe70a42b3176d7a, 0x3fe63503a31c1be8, // 0.72, 0.69397 + 0x3fe712f96c09d18d, 0x3fe62bf5af2b0dfd, // 0.72107, 0.69287 + 0x3fe71bac960e41bf, 0x3fe622e44fec22ff, // 0.72213, 0.69176 + 0x3fe7245c2fcd492a, 0x3fe619cf86c55702, // 0.72319, 0.69065 + 0x3fe72d0837efff97, 0x3fe610b7551d2cde, // 0.72425, 0.68954 + 0x3fe735b0ad2009b2, 0x3fe6079bbc5aadfa, // 0.7253, 0.68843 + 0x3fe73e558e079942, 0x3fe5fe7cbde56a0f, // 0.72636, 0.68732 + 0x3fe746f6d9516d59, 0x3fe5f55a5b2576f8, // 0.72741, 0.6862 + 0x3fe74f948da8d28d, 0x3fe5ec3495837074, // 0.72846, 0.68508 + 0x3fe7582ea9b9a329, 0x3fe5e30b6e6877f3, // 0.72951, 0.68397 + 0x3fe760c52c304764, 0x3fe5d9dee73e345c, // 0.73056, 0.68285 + 0x3fe7695813b9b594, 0x3fe5d0af016ed1d4, // 0.73161, 0.68172 + 0x3fe771e75f037261, 0x3fe5c77bbe65018c, // 0.73265, 0.6806 + 0x3fe77a730cbb9100, 0x3fe5be451f8bf980, // 0.7337, 0.67948 + 0x3fe782fb1b90b35b, 0x3fe5b50b264f7448, // 0.73474, 0.67835 + 0x3fe78b7f8a320a52, 0x3fe5abcdd41bb0d8, // 0.73578, 0.67722 + 0x3fe79400574f55e4, 0x3fe5a28d2a5d7250, // 0.73682, 0.67609 + 0x3fe79c7d8198e56e, 0x3fe599492a81ffbc, // 0.73785, 0.67496 + 0x3fe7a4f707bf97d2, 0x3fe59001d5f723df, // 0.73889, 0.67383 + 0x3fe7ad6ce874dbb6, 0x3fe586b72e2b2cfd, // 0.73992, 0.67269 + 0x3fe7b5df226aafb0, 0x3fe57d69348cec9f, // 0.74095, 0.67156 + 0x3fe7be4db453a27c, 0x3fe57417ea8bb75c, // 0.74198, 0.67042 + 0x3fe7c6b89ce2d333, 0x3fe56ac35197649e, // 0.74301, 0.66928 + 0x3fe7cf1fdacbf179, 0x3fe5616b6b204e6e, // 0.74403, 0.66814 + 0x3fe7d7836cc33db2, 0x3fe5581038975137, // 0.74506, 0.667 + 0x3fe7dfe3517d8937, 0x3fe54eb1bb6dcb8f, // 0.74608, 0.66586 + 0x3fe7e83f87b03686, 0x3fe5454ff5159dfb, // 0.7471, 0.66471 + 0x3fe7f0980e113978, 0x3fe53beae7012abe, // 0.74812, 0.66356 + 0x3fe7f8ece3571771, 0x3fe5328292a35596, // 0.74914, 0.66242 + 0x3fe8013e0638e795, 0x3fe52916f96f8388, // 0.75015, 0.66127 + 0x3fe8098b756e52fa, 0x3fe51fa81cd99aa6, // 0.75117, 0.66011 + 0x3fe811d52faf94dc, 0x3fe51635fe5601d7, // 0.75218, 0.65896 + 0x3fe81a1b33b57acc, 0x3fe50cc09f59a09b, // 0.75319, 0.65781 + 0x3fe8225d803964e5, 0x3fe503480159ded2, // 0.75419, 0.65665 + 0x3fe82a9c13f545ff, 0x3fe4f9cc25cca486, // 0.7552, 0.65549 + 0x3fe832d6eda3a3e0, 0x3fe4f04d0e2859aa, // 0.75621, 0.65433 + 0x3fe83b0e0bff976e, 0x3fe4e6cabbe3e5e9, // 0.75721, 0.65317 + 0x3fe843416dc4cce2, 0x3fe4dd453076b064, // 0.75821, 0.65201 + 0x3fe84b7111af83f9, 0x3fe4d3bc6d589f80, // 0.75921, 0.65085 + 0x3fe8539cf67c9029, 0x3fe4ca30740218a3, // 0.76021, 0.64968 + 0x3fe85bc51ae958cc, 0x3fe4c0a145ec0004, // 0.7612, 0.64851 + 0x3fe863e97db3d95a, 0x3fe4b70ee48fb869, // 0.7622, 0.64735 + 0x3fe86c0a1d9aa195, 0x3fe4ad79516722f0, // 0.76319, 0.64618 + 0x3fe87426f95cd5bd, 0x3fe4a3e08dec9ed6, // 0.76418, 0.645 + 0x3fe87c400fba2ebf, 0x3fe49a449b9b0938, // 0.76517, 0.64383 + 0x3fe884555f72fa6b, 0x3fe490a57bedbcdf, // 0.76615, 0.64266 + 0x3fe88c66e7481ba1, 0x3fe48703306091fe, // 0.76714, 0.64148 + 0x3fe89474a5fb0a84, 0x3fe47d5dba6fde01, // 0.76812, 0.6403 + 0x3fe89c7e9a4dd4ab, 0x3fe473b51b987347, // 0.7691, 0.63912 + 0x3fe8a484c3031d50, 0x3fe46a095557a0f1, // 0.77008, 0.63794 + 0x3fe8ac871ede1d88, 0x3fe4605a692b32a2, // 0.77106, 0.63676 + 0x3fe8b485aca2a468, 0x3fe456a858917046, // 0.77204, 0.63558 + 0x3fe8bc806b151741, 0x3fe44cf325091dd6, // 0.77301, 0.63439 + 0x3fe8c47758fa71cb, 0x3fe4433ad0117b1d, // 0.77398, 0.63321 + 0x3fe8cc6a75184655, 0x3fe4397f5b2a4380, // 0.77495, 0.63202 + 0x3fe8d459be34bdfa, 0x3fe42fc0c7d3adbb, // 0.77592, 0.63083 + 0x3fe8dc45331698cc, 0x3fe425ff178e6bb1, // 0.77689, 0.62964 + 0x3fe8e42cd2852e0a, 0x3fe41c3a4bdbaa26, // 0.77785, 0.62845 + 0x3fe8ec109b486c49, 0x3fe41272663d108c, // 0.77882, 0.62725 + 0x3fe8f3f08c28d9ac, 0x3fe408a76834c0c0, // 0.77978, 0.62606 + 0x3fe8fbcca3ef940d, 0x3fe3fed9534556d4, // 0.78074, 0.62486 + 0x3fe903a4e1665133, 0x3fe3f50828f1e8d2, // 0.78169, 0.62366 + 0x3fe90b7943575efe, 0x3fe3eb33eabe0680, // 0.78265, 0.62246 + 0x3fe91349c88da398, 0x3fe3e15c9a2db922, // 0.7836, 0.62126 + 0x3fe91b166fd49da2, 0x3fe3d78238c58343, // 0.78456, 0.62006 + 0x3fe922df37f8646a, 0x3fe3cda4c80a6076, // 0.78551, 0.61885 + 0x3fe92aa41fc5a815, 0x3fe3c3c44981c517, // 0.78646, 0.61765 + 0x3fe932652609b1cf, 0x3fe3b9e0beb19e18, // 0.7874, 0.61644 + 0x3fe93a22499263fc, 0x3fe3affa292050b9, // 0.78835, 0.61523 + 0x3fe941db892e3a65, 0x3fe3a6108a54ba58, // 0.78929, 0.61402 + 0x3fe94990e3ac4a6c, 0x3fe39c23e3d63029, // 0.79023, 0.61281 + 0x3fe9514257dc4335, 0x3fe39234372c7f04, // 0.79117, 0.6116 + 0x3fe958efe48e6dd7, 0x3fe3884185dfeb22, // 0.79211, 0.61038 + 0x3fe960998893ad8c, 0x3fe37e4bd1792fe2, // 0.79304, 0.60917 + 0x3fe9683f42bd7fe1, 0x3fe374531b817f8d, // 0.79398, 0.60795 + 0x3fe96fe111ddfce0, 0x3fe36a576582831b, // 0.79491, 0.60673 + 0x3fe9777ef4c7d742, 0x3fe36058b10659f3, // 0.79584, 0.60551 + 0x3fe97f18ea4e5c9e, 0x3fe35656ff9799ae, // 0.79676, 0.60429 + 0x3fe986aef1457594, 0x3fe34c5252c14de1, // 0.79769, 0.60307 + 0x3fe98e410881a600, 0x3fe3424aac0ef7d6, // 0.79861, 0.60184 + 0x3fe995cf2ed80d22, 0x3fe338400d0c8e57, // 0.79954, 0.60062 + 0x3fe99d59631e65d5, 0x3fe32e3277467d6b, // 0.80046, 0.59939 + 0x3fe9a4dfa42b06b2, 0x3fe32421ec49a620, // 0.80138, 0.59816 + 0x3fe9ac61f0d4e247, 0x3fe31a0e6da35e44, // 0.80229, 0.59693 + 0x3fe9b3e047f38741, 0x3fe30ff7fce17035, // 0.80321, 0.5957 + 0x3fe9bb5aa85f2098, 0x3fe305de9b921a94, // 0.80412, 0.59447 + 0x3fe9c2d110f075c3, 0x3fe2fbc24b441015, // 0.80503, 0.59323 + 0x3fe9ca438080eadb, 0x3fe2f1a30d86773a, // 0.80594, 0.592 + 0x3fe9d1b1f5ea80d6, 0x3fe2e780e3e8ea16, // 0.80685, 0.59076 + 0x3fe9d91c7007d5a6, 0x3fe2dd5bcffb7616, // 0.80775, 0.58952 + 0x3fe9e082edb42472, 0x3fe2d333d34e9bb7, // 0.80866, 0.58828 + 0x3fe9e7e56dcb45bd, 0x3fe2c908ef734e57, // 0.80956, 0.58704 + 0x3fe9ef43ef29af94, 0x3fe2bedb25faf3ea, // 0.81046, 0.5858 + 0x3fe9f69e70ac75bc, 0x3fe2b4aa787764c4, // 0.81135, 0.58455 + 0x3fe9fdf4f13149de, 0x3fe2aa76e87aeb58, // 0.81225, 0.58331 + 0x3fea05476f967bb5, 0x3fe2a040779843fb, // 0.81314, 0.58206 + 0x3fea0c95eabaf937, 0x3fe2960727629ca8, // 0.81404, 0.58081 + 0x3fea13e0617e4ec7, 0x3fe28bcaf96d94ba, // 0.81493, 0.57956 + 0x3fea1b26d2c0a75e, 0x3fe2818bef4d3cba, // 0.81581, 0.57831 + 0x3fea22693d62ccb9, 0x3fe2774a0a961612, // 0.8167, 0.57706 + 0x3fea29a7a0462782, 0x3fe26d054cdd12df, // 0.81758, 0.57581 + 0x3fea30e1fa4cbf81, 0x3fe262bdb7b795a2, // 0.81847, 0.57455 + 0x3fea38184a593bc6, 0x3fe258734cbb7110, // 0.81935, 0.5733 + 0x3fea3f4a8f4ee2d2, 0x3fe24e260d7ee7c9, // 0.82023, 0.57204 + 0x3fea4678c8119ac8, 0x3fe243d5fb98ac1f, // 0.8211, 0.57078 + 0x3fea4da2f385e997, 0x3fe23983189fdfd5, // 0.82198, 0.56952 + 0x3fea54c91090f524, 0x3fe22f2d662c13e1, // 0.82285, 0.56826 + 0x3fea5beb1e188375, 0x3fe224d4e5d5482e, // 0.82372, 0.567 + 0x3fea63091b02fae2, 0x3fe21a799933eb58, // 0.82459, 0.56573 + 0x3fea6a230637623b, 0x3fe2101b81e0da78, // 0.82546, 0.56447 + 0x3fea7138de9d60f5, 0x3fe205baa17560d6, // 0.82632, 0.5632 + 0x3fea784aa31d3f55, 0x3fe1fb56f98b37b8, // 0.82718, 0.56193 + 0x3fea7f58529fe69d, 0x3fe1f0f08bbc861b, // 0.82805, 0.56066 + 0x3fea8661ec0ee133, 0x3fe1e68759a3e074, // 0.8289, 0.55939 + 0x3fea8d676e545ad2, 0x3fe1dc1b64dc4872, // 0.82976, 0.55812 + 0x3fea9468d85b20ae, 0x3fe1d1acaf012cc2, // 0.83062, 0.55685 + 0x3fea9b66290ea1a3, 0x3fe1c73b39ae68c8, // 0.83147, 0.55557 + 0x3feaa25f5f5aee60, 0x3fe1bcc706804467, // 0.83232, 0.55429 + 0x3feaa9547a2cb98e, 0x3fe1b250171373be, // 0.83317, 0.55302 + 0x3feab045787157ff, 0x3fe1a7d66d0516e6, // 0.83402, 0.55174 + 0x3feab7325916c0d4, 0x3fe19d5a09f2b9b8, // 0.83486, 0.55046 + 0x3feabe1b1b0b8dac, 0x3fe192daef7a5386, // 0.83571, 0.54918 + 0x3feac4ffbd3efac8, 0x3fe188591f3a46e5, // 0.83655, 0.54789 + 0x3feacbe03ea0e73b, 0x3fe17dd49ad16161, // 0.83739, 0.54661 + 0x3fead2bc9e21d511, 0x3fe1734d63dedb49, // 0.83822, 0.54532 + 0x3fead994dab2e979, 0x3fe168c37c025764, // 0.83906, 0.54404 + 0x3feae068f345ecef, 0x3fe15e36e4dbe2bc, // 0.83989, 0.54275 + 0x3feae738e6cd4b67, 0x3fe153a7a00bf453, // 0.84073, 0.54146 + 0x3feaee04b43c1474, 0x3fe14915af336ceb, // 0.84155, 0.54017 + 0x3feaf4cc5a85fb73, 0x3fe13e8113f396c1, // 0.84238, 0.53888 + 0x3feafb8fd89f57b6, 0x3fe133e9cfee254e, // 0.84321, 0.53759 + 0x3feb024f2d7d24a9, 0x3fe1294fe4c5350a, // 0.84403, 0.53629 + 0x3feb090a58150200, 0x3fe11eb3541b4b22, // 0.84485, 0.535 + 0x3feb0fc1575d33db, 0x3fe114141f935545, // 0.84567, 0.5337 + 0x3feb16742a4ca2f5, 0x3fe1097248d0a956, // 0.84649, 0.5324 + 0x3feb1d22cfdadcc6, 0x3fe0fecdd1770537, // 0.84731, 0.5311 + 0x3feb23cd470013b4, 0x3fe0f426bb2a8e7d, // 0.84812, 0.5298 + 0x3feb2a738eb51f33, 0x3fe0e97d078fd23b, // 0.84893, 0.5285 + 0x3feb3115a5f37bf4, 0x3fe0ded0b84bc4b5, // 0.84974, 0.5272 + 0x3feb37b38bb54c09, 0x3fe0d421cf03c12b, // 0.85055, 0.5259 + 0x3feb3e4d3ef55712, 0x3fe0c9704d5d898f, // 0.85136, 0.52459 + 0x3feb44e2beaf0a61, 0x3fe0bebc34ff4646, // 0.85216, 0.52328 + 0x3feb4b7409de7925, 0x3fe0b405878f85ec, // 0.85296, 0.52198 + 0x3feb52011f805c92, 0x3fe0a94c46b53d0b, // 0.85376, 0.52067 + 0x3feb5889fe921405, 0x3fe09e907417c5e1, // 0.85456, 0.51936 + 0x3feb5f0ea611a532, 0x3fe093d2115ee018, // 0.85535, 0.51804 + 0x3feb658f14fdbc47, 0x3fe089112032b08c, // 0.85615, 0.51673 + 0x3feb6c0b4a55ac17, 0x3fe07e4da23bc102, // 0.85694, 0.51542 + 0x3feb728345196e3e, 0x3fe073879922ffed, // 0.85773, 0.5141 + 0x3feb78f70449a34b, 0x3fe068bf0691c028, // 0.85852, 0.51279 + 0x3feb7f6686e792ea, 0x3fe05df3ec31b8b6, // 0.8593, 0.51147 + 0x3feb85d1cbf52c02, 0x3fe053264bad0483, // 0.86009, 0.51015 + 0x3feb8c38d27504e9, 0x3fe0485626ae221a, // 0.86087, 0.50883 + 0x3feb929b996a5b7f, 0x3fe03d837edff370, // 0.86165, 0.50751 + 0x3feb98fa1fd9155e, 0x3fe032ae55edbd95, // 0.86242, 0.50619 + 0x3feb9f5464c5bffc, 0x3fe027d6ad83287e, // 0.8632, 0.50486 + 0x3feba5aa673590d2, 0x3fe01cfc874c3eb7, // 0.86397, 0.50354 + 0x3febabfc262e6586, 0x3fe0121fe4f56d2c, // 0.86474, 0.50221 + 0x3febb249a0b6c40d, 0x3fe00740c82b82e0, // 0.86551, 0.50089 + 0x3febb892d5d5dad5, 0x3fdff8be6537615e, // 0.86628, 0.49956 + 0x3febbed7c49380ea, 0x3fdfe2f64be7120f, // 0.86705, 0.49823 + 0x3febc5186bf8361d, 0x3fdfcd2947c1ff57, // 0.86781, 0.4969 + 0x3febcb54cb0d2327, 0x3fdfb7575c24d2de, // 0.86857, 0.49557 + 0x3febd18ce0dc19d6, 0x3fdfa1808c6cf7e0, // 0.86933, 0.49423 + 0x3febd7c0ac6f952a, 0x3fdf8ba4dbf89aba, // 0.87009, 0.4929 + 0x3febddf02cd2b983, 0x3fdf75c44e26a852, // 0.87084, 0.49156 + 0x3febe41b611154c1, 0x3fdf5fdee656cda3, // 0.8716, 0.49023 + 0x3febea424837de6d, 0x3fdf49f4a7e97729, // 0.87235, 0.48889 + 0x3febf064e15377dd, 0x3fdf3405963fd068, // 0.87309, 0.48755 + 0x3febf6832b71ec5b, 0x3fdf1e11b4bbc35c, // 0.87384, 0.48621 + 0x3febfc9d25a1b147, 0x3fdf081906bff7fd, // 0.87459, 0.48487 + 0x3fec02b2cef1e641, 0x3fdef21b8fafd3b5, // 0.87533, 0.48353 + 0x3fec08c426725549, 0x3fdedc1952ef78d5, // 0.87607, 0.48218 + 0x3fec0ed12b3372e9, 0x3fdec61253e3c61b, // 0.87681, 0.48084 + 0x3fec14d9dc465e58, 0x3fdeb00695f25620, // 0.87755, 0.47949 + 0x3fec1ade38bce19b, 0x3fde99f61c817eda, // 0.87828, 0.47815 + 0x3fec20de3fa971b0, 0x3fde83e0eaf85113, // 0.87901, 0.4768 + 0x3fec26d9f01f2eaf, 0x3fde6dc704be97e2, // 0.87974, 0.47545 + 0x3fec2cd14931e3f1, 0x3fde57a86d3cd824, // 0.88047, 0.4741 + 0x3fec32c449f60831, 0x3fde418527dc4ffa, // 0.8812, 0.47275 + 0x3fec38b2f180bdb1, 0x3fde2b5d3806f63b, // 0.88192, 0.4714 + 0x3fec3e9d3ee7d262, 0x3fde1530a12779f4, // 0.88264, 0.47004 + 0x3fec44833141c004, 0x3fddfeff66a941de, // 0.88336, 0.46869 + 0x3fec4a64c7a5ac4c, 0x3fdde8c98bf86bd6, // 0.88408, 0.46733 + 0x3fec5042012b6907, 0x3fddd28f1481cc58, // 0.8848, 0.46598 + 0x3fec561adceb743e, 0x3fddbc5003b2edf8, // 0.88551, 0.46462 + 0x3fec5bef59fef85a, 0x3fdda60c5cfa10d8, // 0.88622, 0.46326 + 0x3fec61bf777fcc48, 0x3fdd8fc423c62a25, // 0.88693, 0.4619 + 0x3fec678b3488739b, 0x3fdd79775b86e389, // 0.88764, 0.46054 + 0x3fec6d5290341eb2, 0x3fdd632607ac9aa9, // 0.88835, 0.45918 + 0x3fec7315899eaad7, 0x3fdd4cd02ba8609c, // 0.88905, 0.45781 + 0x3fec78d41fe4a267, 0x3fdd3675caebf962, // 0.88975, 0.45645 + 0x3fec7e8e52233cf3, 0x3fdd2016e8e9db5b, // 0.89045, 0.45508 + 0x3fec84441f785f61, 0x3fdd09b389152ec1, // 0.89115, 0.45372 + 0x3fec89f587029c13, 0x3fdcf34baee1cd21, // 0.89184, 0.45235 + 0x3fec8fa287e13305, 0x3fdcdcdf5dc440ce, // 0.89253, 0.45098 + 0x3fec954b213411f5, 0x3fdcc66e9931c45d, // 0.89322, 0.44961 + 0x3fec9aef521bd480, 0x3fdcaff964a0421d, // 0.89391, 0.44824 + 0x3feca08f19b9c449, 0x3fdc997fc3865388, // 0.8946, 0.44687 + 0x3feca62a772fd919, 0x3fdc8301b95b40c2, // 0.89528, 0.4455 + 0x3fecabc169a0b901, 0x3fdc6c7f4997000a, // 0.89597, 0.44412 + 0x3fecb153f02fb87d, 0x3fdc55f877b23537, // 0.89665, 0.44275 + 0x3fecb6e20a00da99, 0x3fdc3f6d47263129, // 0.89732, 0.44137 + 0x3fecbc6bb638d10b, 0x3fdc28ddbb6cf145, // 0.898, 0.43999 + 0x3fecc1f0f3fcfc5c, 0x3fdc1249d8011ee7, // 0.89867, 0.43862 + 0x3fecc771c2736c09, 0x3fdbfbb1a05e0edc, // 0.89935, 0.43724 + 0x3fecccee20c2de9f, 0x3fdbe51517ffc0d9, // 0.90002, 0.43586 + 0x3fecd2660e12c1e6, 0x3fdbce744262deee, // 0.90068, 0.43448 + 0x3fecd7d9898b32f6, 0x3fdbb7cf2304bd01, // 0.90135, 0.43309 + 0x3fecdd489254fe65, 0x3fdba125bd63583e, // 0.90201, 0.43171 + 0x3fece2b32799a060, 0x3fdb8a7814fd5693, // 0.90267, 0.43033 + 0x3fece819488344ce, 0x3fdb73c62d520624, // 0.90333, 0.42894 + 0x3feced7af43cc773, 0x3fdb5d1009e15cc0, // 0.90399, 0.42756 + 0x3fecf2d829f1b40e, 0x3fdb4655ae2bf757, // 0.90464, 0.42617 + 0x3fecf830e8ce467b, 0x3fdb2f971db31972, // 0.9053, 0.42478 + 0x3fecfd852fff6ad4, 0x3fdb18d45bf8aca6, // 0.90595, 0.42339 + 0x3fed02d4feb2bd92, 0x3fdb020d6c7f4009, // 0.9066, 0.422 + 0x3fed082054168bac, 0x3fdaeb4252ca07ab, // 0.90724, 0.42061 + 0x3fed0d672f59d2b9, 0x3fdad473125cdc08, // 0.90789, 0.41922 + 0x3fed12a98fac410c, 0x3fdabd9faebc3980, // 0.90853, 0.41782 + 0x3fed17e7743e35dc, 0x3fdaa6c82b6d3fc9, // 0.90917, 0.41643 + 0x3fed1d20dc40c15c, 0x3fda8fec8bf5b166, // 0.90981, 0.41503 + 0x3fed2255c6e5a4e1, 0x3fda790cd3dbf31a, // 0.91044, 0.41364 + 0x3fed2786335f52fc, 0x3fda622906a70b63, // 0.91107, 0.41224 + 0x3fed2cb220e0ef9f, 0x3fda4b4127dea1e4, // 0.91171, 0.41084 + 0x3fed31d98e9e503a, 0x3fda34553b0afee5, // 0.91234, 0.40944 + 0x3fed36fc7bcbfbdc, 0x3fda1d6543b50ac0, // 0.91296, 0.40804 + 0x3fed3c1ae79f2b4e, 0x3fda067145664d57, // 0.91359, 0.40664 + 0x3fed4134d14dc93a, 0x3fd9ef7943a8ed8a, // 0.91421, 0.40524 + 0x3fed464a380e7242, 0x3fd9d87d4207b0ab, // 0.91483, 0.40384 + 0x3fed4b5b1b187524, 0x3fd9c17d440df9f2, // 0.91545, 0.40243 + 0x3fed506779a3d2d9, 0x3fd9aa794d47c9ee, // 0.91606, 0.40103 + 0x3fed556f52e93eb1, 0x3fd993716141bdfe, // 0.91668, 0.39962 + 0x3fed5a72a6221e73, 0x3fd97c6583890fc2, // 0.91729, 0.39822 + 0x3fed5f7172888a7f, 0x3fd96555b7ab948f, // 0.9179, 0.39681 + 0x3fed646bb7574de5, 0x3fd94e420137bce3, // 0.91851, 0.3954 + 0x3fed696173c9e68b, 0x3fd9372a63bc93d7, // 0.91911, 0.39399 + 0x3fed6e52a71c8547, 0x3fd9200ee2c9be97, // 0.91972, 0.39258 + 0x3fed733f508c0dff, 0x3fd908ef81ef7bd1, // 0.92032, 0.39117 + 0x3fed78276f5617c6, 0x3fd8f1cc44bea329, // 0.92092, 0.38976 + 0x3fed7d0b02b8ecf9, 0x3fd8daa52ec8a4af, // 0.92151, 0.38835 + 0x3fed81ea09f38b63, 0x3fd8c37a439f884f, // 0.92211, 0.38693 + 0x3fed86c48445a450, 0x3fd8ac4b86d5ed44, // 0.9227, 0.38552 + 0x3fed8b9a70ef9cb4, 0x3fd89518fbff098e, // 0.92329, 0.3841 + 0x3fed906bcf328d46, 0x3fd87de2a6aea963, // 0.92388, 0.38268 + 0x3fed95389e50429b, 0x3fd866a88a792ea0, // 0.92447, 0.38127 + 0x3fed9a00dd8b3d46, 0x3fd84f6aaaf3903f, // 0.92505, 0.37985 + 0x3fed9ec48c26b1f3, 0x3fd838290bb359c8, // 0.92563, 0.37843 + 0x3feda383a9668988, 0x3fd820e3b04eaac4, // 0.92621, 0.37701 + 0x3feda83e348f613b, 0x3fd8099a9c5c362d, // 0.92679, 0.37559 + 0x3fedacf42ce68ab9, 0x3fd7f24dd37341e3, // 0.92736, 0.37416 + 0x3fedb1a591b20c38, 0x3fd7dafd592ba621, // 0.92794, 0.37274 + 0x3fedb6526238a09b, 0x3fd7c3a9311dcce7, // 0.92851, 0.37132 + 0x3fedbafa9dc1b78d, 0x3fd7ac515ee2b172, // 0.92907, 0.36989 + 0x3fedbf9e4395759a, 0x3fd794f5e613dfae, // 0.92964, 0.36847 + 0x3fedc43d52fcb453, 0x3fd77d96ca4b73a6, // 0.93021, 0.36704 + 0x3fedc8d7cb410260, 0x3fd766340f2418f6, // 0.93077, 0.36561 + 0x3fedcd6dabaca3a5, 0x3fd74ecdb8390a3e, // 0.93133, 0.36418 + 0x3fedd1fef38a915a, 0x3fd73763c9261092, // 0.93188, 0.36276 + 0x3fedd68ba2267a25, 0x3fd71ff6458782ec, // 0.93244, 0.36133 + 0x3feddb13b6ccc23d, 0x3fd7088530fa459e, // 0.93299, 0.3599 + 0x3feddf9730ca837b, 0x3fd6f1108f1bc9c5, // 0.93354, 0.35846 + 0x3fede4160f6d8d81, 0x3fd6d998638a0cb5, // 0.93409, 0.35703 + 0x3fede890520465ce, 0x3fd6c21cb1e39771, // 0.93464, 0.3556 + 0x3feded05f7de47da, 0x3fd6aa9d7dc77e16, // 0.93518, 0.35416 + 0x3fedf177004b2534, 0x3fd6931acad55f51, // 0.93573, 0.35273 + 0x3fedf5e36a9ba59c, 0x3fd67b949cad63ca, // 0.93627, 0.35129 + 0x3fedfa4b3621271d, 0x3fd6640af6f03d9e, // 0.9368, 0.34986 + 0x3fedfeae622dbe2b, 0x3fd64c7ddd3f27c6, // 0.93734, 0.34842 + 0x3fee030cee1435b8, 0x3fd634ed533be58e, // 0.93787, 0.34698 + 0x3fee0766d9280f54, 0x3fd61d595c88c203, // 0.9384, 0.34554 + 0x3fee0bbc22bd8349, 0x3fd605c1fcc88f63, // 0.93893, 0.3441 + 0x3fee100cca2980ac, 0x3fd5ee27379ea693, // 0.93946, 0.34266 + 0x3fee1458cec1ad83, 0x3fd5d68910aee686, // 0.93998, 0.34122 + 0x3fee18a02fdc66d9, 0x3fd5bee78b9db3b6, // 0.94051, 0.33978 + 0x3fee1ce2ecd0c0d8, 0x3fd5a742ac0ff78d, // 0.94103, 0.33833 + 0x3fee212104f686e5, 0x3fd58f9a75ab1fdd, // 0.94154, 0.33689 + 0x3fee255a77a63bb8, 0x3fd577eeec151e47, // 0.94206, 0.33545 + 0x3fee298f4439197a, 0x3fd5604012f467b4, // 0.94257, 0.334 + 0x3fee2dbf6a0911d9, 0x3fd5488dedeff3be, // 0.94308, 0.33255 + 0x3fee31eae870ce25, 0x3fd530d880af3c24, // 0.94359, 0.33111 + 0x3fee3611becbaf69, 0x3fd5191fceda3c35, // 0.9441, 0.32966 + 0x3fee3a33ec75ce85, 0x3fd50163dc197047, // 0.9446, 0.32821 + 0x3fee3e5170cbfc46, 0x3fd4e9a4ac15d520, // 0.94511, 0.32676 + 0x3fee426a4b2bc17e, 0x3fd4d1e24278e76a, // 0.94561, 0.32531 + 0x3fee467e7af35f23, 0x3fd4ba1ca2eca31c, // 0.94611, 0.32386 + 0x3fee4a8dff81ce5e, 0x3fd4a253d11b82f3, // 0.9466, 0.32241 + 0x3fee4e98d836c0af, 0x3fd48a87d0b07fd7, // 0.94709, 0.32096 + 0x3fee529f04729ffc, 0x3fd472b8a5571054, // 0.94759, 0.3195 + 0x3fee56a083968eb1, 0x3fd45ae652bb2800, // 0.94807, 0.31805 + 0x3fee5a9d550467d3, 0x3fd44310dc8936f0, // 0.94856, 0.31659 + 0x3fee5e95781ebf1c, 0x3fd42b38466e2928, // 0.94905, 0.31514 + 0x3fee6288ec48e112, 0x3fd4135c94176602, // 0.94953, 0.31368 + 0x3fee6677b0e6d31e, 0x3fd3fb7dc932cfa4, // 0.95001, 0.31222 + 0x3fee6a61c55d53a7, 0x3fd3e39be96ec271, // 0.95049, 0.31077 + 0x3fee6e472911da27, 0x3fd3cbb6f87a146e, // 0.95096, 0.30931 + 0x3fee7227db6a9744, 0x3fd3b3cefa0414b7, // 0.95144, 0.30785 + 0x3fee7603dbce74e9, 0x3fd39be3f1bc8aef, // 0.95191, 0.30639 + 0x3fee79db29a5165a, 0x3fd383f5e353b6aa, // 0.95238, 0.30493 + 0x3fee7dadc456d850, 0x3fd36c04d27a4edf, // 0.95284, 0.30347 + 0x3fee817bab4cd10d, 0x3fd35410c2e18152, // 0.95331, 0.30201 + 0x3fee8544ddf0d075, 0x3fd33c19b83af207, // 0.95377, 0.30054 + 0x3fee89095bad6025, 0x3fd3241fb638baaf, // 0.95423, 0.29908 + 0x3fee8cc923edc388, 0x3fd30c22c08d6a13, // 0.95469, 0.29762 + 0x3fee9084361df7f3, 0x3fd2f422daec0386, // 0.95514, 0.29615 + 0x3fee943a91aab4b4, 0x3fd2dc200907fe51, // 0.95559, 0.29469 + 0x3fee97ec36016b30, 0x3fd2c41a4e954520, // 0.95605, 0.29322 + 0x3fee9b99229046f8, 0x3fd2ac11af483572, // 0.95649, 0.29175 + 0x3fee9f4156c62dda, 0x3fd294062ed59f05, // 0.95694, 0.29028 + 0x3feea2e4d212c000, 0x3fd27bf7d0f2c346, // 0.95738, 0.28882 + 0x3feea68393e65800, 0x3fd263e6995554ba, // 0.95783, 0.28735 + 0x3feeaa1d9bb20af3, 0x3fd24bd28bb37672, // 0.95827, 0.28588 + 0x3feeadb2e8e7a88e, 0x3fd233bbabc3bb72, // 0.9587, 0.28441 + 0x3feeb1437af9bb34, 0x3fd21ba1fd3d2623, // 0.95914, 0.28294 + 0x3feeb4cf515b8811, 0x3fd2038583d727bd, // 0.95957, 0.28146 + 0x3feeb8566b810f2a, 0x3fd1eb6643499fbb, // 0.96, 0.27999 + 0x3feebbd8c8df0b74, 0x3fd1d3443f4cdb3d, // 0.96043, 0.27852 + 0x3feebf5668eaf2ef, 0x3fd1bb1f7b999480, // 0.96086, 0.27705 + 0x3feec2cf4b1af6b2, 0x3fd1a2f7fbe8f243, // 0.96128, 0.27557 + 0x3feec6436ee60309, 0x3fd18acdc3f4873a, // 0.9617, 0.2741 + 0x3feec9b2d3c3bf84, 0x3fd172a0d7765177, // 0.96212, 0.27262 + 0x3feecd1d792c8f10, 0x3fd15a713a28b9d9, // 0.96254, 0.27115 + 0x3feed0835e999009, 0x3fd1423eefc69378, // 0.96295, 0.26967 + 0x3feed3e483849c51, 0x3fd12a09fc0b1b12, // 0.96337, 0.26819 + 0x3feed740e7684963, 0x3fd111d262b1f677, // 0.96378, 0.26671 + 0x3feeda9889bfe86a, 0x3fd0f998277733f7, // 0.96418, 0.26523 + 0x3feeddeb6a078651, 0x3fd0e15b4e1749cd, // 0.96459, 0.26375 + 0x3feee13987bbebdc, 0x3fd0c91bda4f158d, // 0.96499, 0.26227 + 0x3feee482e25a9dbc, 0x3fd0b0d9cfdbdb90, // 0.96539, 0.26079 + 0x3feee7c77961dc9e, 0x3fd09895327b465e, // 0.96579, 0.25931 + 0x3feeeb074c50a544, 0x3fd0804e05eb661e, // 0.96619, 0.25783 + 0x3feeee425aa6b09a, 0x3fd068044deab002, // 0.96658, 0.25635 + 0x3feef178a3e473c2, 0x3fd04fb80e37fdae, // 0.96698, 0.25487 + 0x3feef4aa278b2032, 0x3fd037694a928cac, // 0.96737, 0.25338 + 0x3feef7d6e51ca3c0, 0x3fd01f1806b9fdd2, // 0.96775, 0.2519 + 0x3feefafedc1ba8b7, 0x3fd006c4466e54af, // 0.96814, 0.25041 + 0x3feefe220c0b95ec, 0x3fcfdcdc1adfedf8, // 0.96852, 0.24893 + 0x3fef014074708ed3, 0x3fcfac2abeff57ff, // 0.9689, 0.24744 + 0x3fef045a14cf738c, 0x3fcf7b7480bd3801, // 0.96928, 0.24596 + 0x3fef076eecade0fa, 0x3fcf4ab9679c9f5c, // 0.96966, 0.24447 + 0x3fef0a7efb9230d7, 0x3fcf19f97b215f1a, // 0.97003, 0.24298 + 0x3fef0d8a410379c5, 0x3fcee934c2d006c7, // 0.9704, 0.24149 + 0x3fef1090bc898f5f, 0x3fceb86b462de348, // 0.97077, 0.24 + 0x3fef13926dad024e, 0x3fce879d0cc0fdaf, // 0.97114, 0.23851 + 0x3fef168f53f7205d, 0x3fce56ca1e101a1b, // 0.9715, 0.23702 + 0x3fef19876ef1f486, 0x3fce25f281a2b684, // 0.97187, 0.23553 + 0x3fef1c7abe284708, 0x3fcdf5163f01099a, // 0.97223, 0.23404 + 0x3fef1f6941259d7a, 0x3fcdc4355db40195, // 0.97258, 0.23255 + 0x3fef2252f7763ada, 0x3fcd934fe5454311, // 0.97294, 0.23106 + 0x3fef2537e0a71f9f, 0x3fcd6265dd3f27e3, // 0.97329, 0.22957 + 0x3fef2817fc4609ce, 0x3fcd31774d2cbdee, // 0.97364, 0.22807 + 0x3fef2af349e17507, 0x3fcd00843c99c5f9, // 0.97399, 0.22658 + 0x3fef2dc9c9089a9d, 0x3fcccf8cb312b286, // 0.97434, 0.22508 + 0x3fef309b794b719f, 0x3fcc9e90b824a6a9, // 0.97468, 0.22359 + 0x3fef33685a3aaef0, 0x3fcc6d90535d74dc, // 0.97503, 0.22209 + 0x3fef36306b67c556, 0x3fcc3c8b8c4b9dd7, // 0.97536, 0.2206 + 0x3fef38f3ac64e589, 0x3fcc0b826a7e4f63, // 0.9757, 0.2191 + 0x3fef3bb21cc4fe47, 0x3fcbda74f5856330, // 0.97604, 0.2176 + 0x3fef3e6bbc1bbc65, 0x3fcba96334f15dad, // 0.97637, 0.21611 + 0x3fef412089fd8adc, 0x3fcb784d30536cda, // 0.9767, 0.21461 + 0x3fef43d085ff92dd, 0x3fcb4732ef3d6722, // 0.97703, 0.21311 + 0x3fef467bafb7bbe0, 0x3fcb16147941ca2a, // 0.97735, 0.21161 + 0x3fef492206bcabb4, 0x3fcae4f1d5f3b9ab, // 0.97768, 0.21011 + 0x3fef4bc38aa5c694, 0x3fcab3cb0ce6fe44, // 0.978, 0.20861 + 0x3fef4e603b0b2f2d, 0x3fca82a025b00451, // 0.97832, 0.20711 + 0x3fef50f81785c6b9, 0x3fca517127e3dabc, // 0.97863, 0.20561 + 0x3fef538b1faf2d07, 0x3fca203e1b1831da, // 0.97895, 0.20411 + 0x3fef56195321c090, 0x3fc9ef0706e35a35, // 0.97926, 0.20261 + 0x3fef58a2b1789e84, 0x3fc9bdcbf2dc4366, // 0.97957, 0.2011 + 0x3fef5b273a4fa2d9, 0x3fc98c8ce69a7aec, // 0.97988, 0.1996 + 0x3fef5da6ed43685d, 0x3fc95b49e9b62af9, // 0.98018, 0.1981 + 0x3fef6021c9f148c2, 0x3fc92a0303c8194f, // 0.98048, 0.19659 + 0x3fef6297cff75cb0, 0x3fc8f8b83c69a60a, // 0.98079, 0.19509 + 0x3fef6508fef47bd5, 0x3fc8c7699b34ca7e, // 0.98108, 0.19359 + 0x3fef677556883cee, 0x3fc8961727c41804, // 0.98138, 0.19208 + 0x3fef69dcd652f5de, 0x3fc864c0e9b2b6cf, // 0.98167, 0.19057 + 0x3fef6c3f7df5bbb7, 0x3fc83366e89c64c5, // 0.98196, 0.18907 + 0x3fef6e9d4d1262ca, 0x3fc802092c1d744b, // 0.98225, 0.18756 + 0x3fef70f6434b7eb7, 0x3fc7d0a7bbd2cb1b, // 0.98254, 0.18606 + 0x3fef734a60446279, 0x3fc79f429f59e11d, // 0.98282, 0.18455 + 0x3fef7599a3a12077, 0x3fc76dd9de50bf31, // 0.98311, 0.18304 + 0x3fef77e40d068a90, 0x3fc73c6d8055fe0a, // 0.98339, 0.18153 + 0x3fef7a299c1a322a, 0x3fc70afd8d08c4ff, // 0.98366, 0.18002 + 0x3fef7c6a50826840, 0x3fc6d98a0c08c8da, // 0.98394, 0.17851 + 0x3fef7ea629e63d6e, 0x3fc6a81304f64ab2, // 0.98421, 0.177 + 0x3fef80dd27ed8204, 0x3fc676987f7216b8, // 0.98448, 0.17549 + 0x3fef830f4a40c60c, 0x3fc6451a831d830d, // 0.98475, 0.17398 + 0x3fef853c9089595e, 0x3fc61399179a6e94, // 0.98501, 0.17247 + 0x3fef8764fa714ba9, 0x3fc5e214448b3fc6, // 0.98528, 0.17096 + 0x3fef898887a36c84, 0x3fc5b08c1192e381, // 0.98554, 0.16945 + 0x3fef8ba737cb4b78, 0x3fc57f008654cbde, // 0.9858, 0.16794 + 0x3fef8dc10a95380d, 0x3fc54d71aa74ef02, // 0.98605, 0.16643 + 0x3fef8fd5ffae41db, 0x3fc51bdf8597c5f2, // 0.98631, 0.16491 + 0x3fef91e616c43891, 0x3fc4ea4a1f624b61, // 0.98656, 0.1634 + 0x3fef93f14f85ac08, 0x3fc4b8b17f79fa88, // 0.98681, 0.16189 + 0x3fef95f7a9a1ec47, 0x3fc48715ad84cdf5, // 0.98706, 0.16037 + 0x3fef97f924c9099b, 0x3fc45576b1293e5a, // 0.9873, 0.15886 + 0x3fef99f5c0abd496, 0x3fc423d4920e4166, // 0.98754, 0.15734 + 0x3fef9bed7cfbde29, 0x3fc3f22f57db4893, // 0.98778, 0.15583 + 0x3fef9de0596b77a3, 0x3fc3c0870a383ff6, // 0.98802, 0.15431 + 0x3fef9fce55adb2c8, 0x3fc38edbb0cd8d14, // 0.98826, 0.1528 + 0x3fefa1b7717661d5, 0x3fc35d2d53440db2, // 0.98849, 0.15128 + 0x3fefa39bac7a1791, 0x3fc32b7bf94516a7, // 0.98872, 0.14976 + 0x3fefa57b066e2754, 0x3fc2f9c7aa7a72af, // 0.98895, 0.14825 + 0x3fefa7557f08a517, 0x3fc2c8106e8e613a, // 0.98918, 0.14673 + 0x3fefa92b1600657c, 0x3fc296564d2b953e, // 0.9894, 0.14521 + 0x3fefaafbcb0cfddc, 0x3fc264994dfd340a, // 0.98962, 0.1437 + 0x3fefacc79de6c44f, 0x3fc232d978aed413, // 0.98984, 0.14218 + 0x3fefae8e8e46cfbb, 0x3fc20116d4ec7bce, // 0.99006, 0.14066 + 0x3fefb0509be6f7db, 0x3fc1cf516a62a077, // 0.99027, 0.13914 + 0x3fefb20dc681d54d, 0x3fc19d8940be24e7, // 0.99049, 0.13762 + 0x3fefb3c60dd2c199, 0x3fc16bbe5fac5865, // 0.9907, 0.1361 + 0x3fefb5797195d741, 0x3fc139f0cedaf576, // 0.9909, 0.13458 + 0x3fefb727f187f1c7, 0x3fc1082095f820b0, // 0.99111, 0.13306 + 0x3fefb8d18d66adb7, 0x3fc0d64dbcb26786, // 0.99131, 0.13154 + 0x3fefba7644f068b5, 0x3fc0a4784ab8bf1d, // 0.99151, 0.13002 + 0x3fefbc1617e44186, 0x3fc072a047ba831d, // 0.99171, 0.1285 + 0x3fefbdb106021816, 0x3fc040c5bb67747e, // 0.99191, 0.12698 + 0x3fefbf470f0a8d88, 0x3fc00ee8ad6fb85b, // 0.9921, 0.12545 + 0x3fefc0d832bf043a, 0x3fbfba124b07ad85, // 0.99229, 0.12393 + 0x3fefc26470e19fd3, 0x3fbf564e56a9730e, // 0.99248, 0.12241 + 0x3fefc3ebc935454c, 0x3fbef2858d27561b, // 0.99267, 0.12089 + 0x3fefc56e3b7d9af6, 0x3fbe8eb7fde4aa3e, // 0.99285, 0.11937 + 0x3fefc6ebc77f0887, 0x3fbe2ae5b8457f77, // 0.99303, 0.11784 + 0x3fefc8646cfeb721, 0x3fbdc70ecbae9fc8, // 0.99321, 0.11632 + 0x3fefc9d82bc2915e, 0x3fbd633347858ce4, // 0.99339, 0.11479 + 0x3fefcb4703914354, 0x3fbcff533b307dc1, // 0.99356, 0.11327 + 0x3fefccb0f4323aa3, 0x3fbc9b6eb6165c42, // 0.99374, 0.11175 + 0x3fefce15fd6da67b, 0x3fbc3785c79ec2d5, // 0.99391, 0.11022 + 0x3fefcf761f0c77a3, 0x3fbbd3987f31fa0e, // 0.99407, 0.1087 + 0x3fefd0d158d86087, 0x3fbb6fa6ec38f64c, // 0.99424, 0.10717 + 0x3fefd227aa9bd53b, 0x3fbb0bb11e1d5559, // 0.9944, 0.10565 + 0x3fefd37914220b84, 0x3fbaa7b724495c04, // 0.99456, 0.10412 + 0x3fefd4c59536fae4, 0x3fba43b90e27f3c4, // 0.99472, 0.1026 + 0x3fefd60d2da75c9e, 0x3fb9dfb6eb24a85c, // 0.99488, 0.10107 + 0x3fefd74fdd40abbf, 0x3fb97bb0caaba56f, // 0.99503, 0.099544 + 0x3fefd88da3d12526, 0x3fb917a6bc29b42c, // 0.99518, 0.098017 + 0x3fefd9c68127c78c, 0x3fb8b398cf0c38e0, // 0.99533, 0.09649 + 0x3fefdafa7514538c, 0x3fb84f8712c130a0, // 0.99548, 0.094963 + 0x3fefdc297f674ba9, 0x3fb7eb7196b72ee4, // 0.99563, 0.093436 + 0x3fefdd539ff1f456, 0x3fb787586a5d5b21, // 0.99577, 0.091909 + 0x3fefde78d68653fd, 0x3fb7233b9d236e71, // 0.99591, 0.090381 + 0x3fefdf9922f73307, 0x3fb6bf1b3e79b129, // 0.99604, 0.088854 + 0x3fefe0b485181be3, 0x3fb65af75dd0f87b, // 0.99618, 0.087326 + 0x3fefe1cafcbd5b09, 0x3fb5f6d00a9aa419, // 0.99631, 0.085797 + 0x3fefe2dc89bbff08, 0x3fb592a554489bc8, // 0.99644, 0.084269 + 0x3fefe3e92be9d886, 0x3fb52e774a4d4d0a, // 0.99657, 0.08274 + 0x3fefe4f0e31d7a4a, 0x3fb4ca45fc1ba8b6, // 0.9967, 0.081211 + 0x3fefe5f3af2e3940, 0x3fb4661179272096, // 0.99682, 0.079682 + 0x3fefe6f18ff42c84, 0x3fb401d9d0e3a507, // 0.99694, 0.078153 + 0x3fefe7ea85482d60, 0x3fb39d9f12c5a299, // 0.99706, 0.076624 + 0x3fefe8de8f03d75c, 0x3fb339614e41ffa5, // 0.99718, 0.075094 + 0x3fefe9cdad01883a, 0x3fb2d52092ce19f6, // 0.99729, 0.073565 + 0x3fefeab7df1c6005, 0x3fb270dcefdfc45b, // 0.9974, 0.072035 + 0x3fefeb9d2530410f, 0x3fb20c9674ed444c, // 0.99751, 0.070505 + 0x3fefec7d7f19cffc, 0x3fb1a84d316d4f8a, // 0.99762, 0.068974 + 0x3fefed58ecb673c4, 0x3fb1440134d709b2, // 0.99772, 0.067444 + 0x3fefee2f6de455ba, 0x3fb0dfb28ea201e6, // 0.99783, 0.065913 + 0x3fefef0102826191, 0x3fb07b614e463064, // 0.99793, 0.064383 + 0x3fefefcdaa704562, 0x3fb0170d833bf421, // 0.99802, 0.062852 + 0x3feff095658e71ad, 0x3faf656e79f820e0, // 0.99812, 0.061321 + 0x3feff15833be1965, 0x3fae9cbd15ff5527, // 0.99821, 0.05979 + 0x3feff21614e131ed, 0x3fadd406f9808ec8, // 0.9983, 0.058258 + 0x3feff2cf08da7321, 0x3fad0b4c436f91d0, // 0.99839, 0.056727 + 0x3feff3830f8d575c, 0x3fac428d12c0d7e3, // 0.99848, 0.055195 + 0x3feff43228de1b77, 0x3fab79c986698b78, // 0.99856, 0.053664 + 0x3feff4dc54b1bed3, 0x3faab101bd5f8317, // 0.99864, 0.052132 + 0x3feff58192ee0358, 0x3fa9e835d6993c87, // 0.99872, 0.0506 + 0x3feff621e3796d7e, 0x3fa91f65f10dd814, // 0.9988, 0.049068 + 0x3feff6bd463b444d, 0x3fa856922bb513c1, // 0.99887, 0.047535 + 0x3feff753bb1b9164, 0x3fa78dbaa5874685, // 0.99894, 0.046003 + 0x3feff7e5420320f9, 0x3fa6c4df7d7d5b84, // 0.99901, 0.044471 + 0x3feff871dadb81df, 0x3fa5fc00d290cd43, // 0.99908, 0.042938 + 0x3feff8f9858f058b, 0x3fa5331ec3bba0eb, // 0.99914, 0.041406 + 0x3feff97c4208c014, 0x3fa46a396ff86179, // 0.9992, 0.039873 + 0x3feff9fa10348837, 0x3fa3a150f6421afc, // 0.99926, 0.03834 + 0x3feffa72effef75d, 0x3fa2d865759455cd, // 0.99932, 0.036807 + 0x3feffae6e1556998, 0x3fa20f770ceb11c6, // 0.99938, 0.035274 + 0x3feffb55e425fdae, 0x3fa14685db42c17e, // 0.99943, 0.033741 + 0x3feffbbff85f9515, 0x3fa07d91ff984580, // 0.99948, 0.032208 + 0x3feffc251df1d3f8, 0x3f9f693731d1cf01, // 0.99953, 0.030675 + 0x3feffc8554cd213a, 0x3f9dd7458c64ab39, // 0.99958, 0.029142 + 0x3feffce09ce2a679, 0x3f9c454f4ce53b1c, // 0.99962, 0.027608 + 0x3feffd36f624500c, 0x3f9ab354b1504fca, // 0.99966, 0.026075 + 0x3feffd886084cd0d, 0x3f992155f7a3667e, // 0.9997, 0.024541 + 0x3feffdd4dbf78f52, 0x3f978f535ddc9f03, // 0.99974, 0.023008 + 0x3feffe1c6870cb77, 0x3f95fd4d21fab226, // 0.99977, 0.021474 + 0x3feffe5f05e578db, 0x3f946b4381fce81c, // 0.9998, 0.01994 + 0x3feffe9cb44b51a1, 0x3f92d936bbe30efd, // 0.99983, 0.018407 + 0x3feffed57398d2b7, 0x3f9147270dad7132, // 0.99986, 0.016873 + 0x3fefff0943c53bd1, 0x3f8f6a296ab997ca, // 0.99988, 0.015339 + 0x3fefff3824c88f6f, 0x3f8c45ffe1e48ad9, // 0.9999, 0.013805 + 0x3fefff62169b92db, 0x3f8921d1fcdec784, // 0.99992, 0.012272 + 0x3fefff871937ce2f, 0x3f85fda037ac05e0, // 0.99994, 0.010738 + 0x3fefffa72c978c4f, 0x3f82d96b0e509703, // 0.99996, 0.0092038 + 0x3fefffc250b5daef, 0x3f7f6a65f9a2a3c5, // 0.99997, 0.0076698 + 0x3fefffd8858e8a92, 0x3f7921f0fe670071, // 0.99998, 0.0061359 + 0x3fefffe9cb1e2e8d, 0x3f72d97822f996bc, // 0.99999, 0.0046019 + 0x3feffff621621d02, 0x3f6921f8becca4ba, // 1, 0.003068 + 0x3feffffd88586ee6, 0x3f5921faaee6472d, // 1, 0.001534 + 0x3ff0000000000000, 0x0000000000000000, // 1, 0 + 0x3feffffd88586ee6, 0xbf5921faaee6472d, // 1, -0.001534 + 0x3feffff621621d02, 0xbf6921f8becca4ba, // 1, -0.003068 + 0x3fefffe9cb1e2e8d, 0xbf72d97822f996bc, // 0.99999,-0.0046019 + 0x3fefffd8858e8a92, 0xbf7921f0fe670071, // 0.99998,-0.0061359 + 0x3fefffc250b5daef, 0xbf7f6a65f9a2a3c5, // 0.99997,-0.0076698 + 0x3fefffa72c978c4f, 0xbf82d96b0e509703, // 0.99996,-0.0092038 + 0x3fefff871937ce2f, 0xbf85fda037ac05e0, // 0.99994, -0.010738 + 0x3fefff62169b92db, 0xbf8921d1fcdec784, // 0.99992, -0.012272 + 0x3fefff3824c88f6f, 0xbf8c45ffe1e48ad9, // 0.9999, -0.013805 + 0x3fefff0943c53bd1, 0xbf8f6a296ab997ca, // 0.99988, -0.015339 + 0x3feffed57398d2b7, 0xbf9147270dad7132, // 0.99986, -0.016873 + 0x3feffe9cb44b51a1, 0xbf92d936bbe30efd, // 0.99983, -0.018407 + 0x3feffe5f05e578db, 0xbf946b4381fce81c, // 0.9998, -0.01994 + 0x3feffe1c6870cb77, 0xbf95fd4d21fab226, // 0.99977, -0.021474 + 0x3feffdd4dbf78f52, 0xbf978f535ddc9f03, // 0.99974, -0.023008 + 0x3feffd886084cd0d, 0xbf992155f7a3667e, // 0.9997, -0.024541 + 0x3feffd36f624500c, 0xbf9ab354b1504fca, // 0.99966, -0.026075 + 0x3feffce09ce2a679, 0xbf9c454f4ce53b1c, // 0.99962, -0.027608 + 0x3feffc8554cd213a, 0xbf9dd7458c64ab39, // 0.99958, -0.029142 + 0x3feffc251df1d3f8, 0xbf9f693731d1cf01, // 0.99953, -0.030675 + 0x3feffbbff85f9515, 0xbfa07d91ff984580, // 0.99948, -0.032208 + 0x3feffb55e425fdae, 0xbfa14685db42c17e, // 0.99943, -0.033741 + 0x3feffae6e1556998, 0xbfa20f770ceb11c6, // 0.99938, -0.035274 + 0x3feffa72effef75d, 0xbfa2d865759455cd, // 0.99932, -0.036807 + 0x3feff9fa10348837, 0xbfa3a150f6421afc, // 0.99926, -0.03834 + 0x3feff97c4208c014, 0xbfa46a396ff86179, // 0.9992, -0.039873 + 0x3feff8f9858f058b, 0xbfa5331ec3bba0eb, // 0.99914, -0.041406 + 0x3feff871dadb81df, 0xbfa5fc00d290cd43, // 0.99908, -0.042938 + 0x3feff7e5420320f9, 0xbfa6c4df7d7d5b84, // 0.99901, -0.044471 + 0x3feff753bb1b9164, 0xbfa78dbaa5874685, // 0.99894, -0.046003 + 0x3feff6bd463b444d, 0xbfa856922bb513c1, // 0.99887, -0.047535 + 0x3feff621e3796d7e, 0xbfa91f65f10dd814, // 0.9988, -0.049068 + 0x3feff58192ee0358, 0xbfa9e835d6993c87, // 0.99872, -0.0506 + 0x3feff4dc54b1bed3, 0xbfaab101bd5f8317, // 0.99864, -0.052132 + 0x3feff43228de1b77, 0xbfab79c986698b78, // 0.99856, -0.053664 + 0x3feff3830f8d575c, 0xbfac428d12c0d7e3, // 0.99848, -0.055195 + 0x3feff2cf08da7321, 0xbfad0b4c436f91d0, // 0.99839, -0.056727 + 0x3feff21614e131ed, 0xbfadd406f9808ec8, // 0.9983, -0.058258 + 0x3feff15833be1965, 0xbfae9cbd15ff5527, // 0.99821, -0.05979 + 0x3feff095658e71ad, 0xbfaf656e79f820e0, // 0.99812, -0.061321 + 0x3fefefcdaa704562, 0xbfb0170d833bf421, // 0.99802, -0.062852 + 0x3fefef0102826191, 0xbfb07b614e463064, // 0.99793, -0.064383 + 0x3fefee2f6de455ba, 0xbfb0dfb28ea201e6, // 0.99783, -0.065913 + 0x3fefed58ecb673c4, 0xbfb1440134d709b2, // 0.99772, -0.067444 + 0x3fefec7d7f19cffc, 0xbfb1a84d316d4f8a, // 0.99762, -0.068974 + 0x3fefeb9d2530410f, 0xbfb20c9674ed444c, // 0.99751, -0.070505 + 0x3fefeab7df1c6005, 0xbfb270dcefdfc45b, // 0.9974, -0.072035 + 0x3fefe9cdad01883a, 0xbfb2d52092ce19f6, // 0.99729, -0.073565 + 0x3fefe8de8f03d75c, 0xbfb339614e41ffa5, // 0.99718, -0.075094 + 0x3fefe7ea85482d60, 0xbfb39d9f12c5a299, // 0.99706, -0.076624 + 0x3fefe6f18ff42c84, 0xbfb401d9d0e3a507, // 0.99694, -0.078153 + 0x3fefe5f3af2e3940, 0xbfb4661179272096, // 0.99682, -0.079682 + 0x3fefe4f0e31d7a4a, 0xbfb4ca45fc1ba8b6, // 0.9967, -0.081211 + 0x3fefe3e92be9d886, 0xbfb52e774a4d4d0a, // 0.99657, -0.08274 + 0x3fefe2dc89bbff08, 0xbfb592a554489bc8, // 0.99644, -0.084269 + 0x3fefe1cafcbd5b09, 0xbfb5f6d00a9aa419, // 0.99631, -0.085797 + 0x3fefe0b485181be3, 0xbfb65af75dd0f87b, // 0.99618, -0.087326 + 0x3fefdf9922f73307, 0xbfb6bf1b3e79b129, // 0.99604, -0.088854 + 0x3fefde78d68653fd, 0xbfb7233b9d236e71, // 0.99591, -0.090381 + 0x3fefdd539ff1f456, 0xbfb787586a5d5b21, // 0.99577, -0.091909 + 0x3fefdc297f674ba9, 0xbfb7eb7196b72ee4, // 0.99563, -0.093436 + 0x3fefdafa7514538c, 0xbfb84f8712c130a0, // 0.99548, -0.094963 + 0x3fefd9c68127c78c, 0xbfb8b398cf0c38e0, // 0.99533, -0.09649 + 0x3fefd88da3d12526, 0xbfb917a6bc29b42c, // 0.99518, -0.098017 + 0x3fefd74fdd40abbf, 0xbfb97bb0caaba56f, // 0.99503, -0.099544 + 0x3fefd60d2da75c9e, 0xbfb9dfb6eb24a85c, // 0.99488, -0.10107 + 0x3fefd4c59536fae4, 0xbfba43b90e27f3c4, // 0.99472, -0.1026 + 0x3fefd37914220b84, 0xbfbaa7b724495c04, // 0.99456, -0.10412 + 0x3fefd227aa9bd53b, 0xbfbb0bb11e1d5559, // 0.9944, -0.10565 + 0x3fefd0d158d86087, 0xbfbb6fa6ec38f64c, // 0.99424, -0.10717 + 0x3fefcf761f0c77a3, 0xbfbbd3987f31fa0e, // 0.99407, -0.1087 + 0x3fefce15fd6da67b, 0xbfbc3785c79ec2d5, // 0.99391, -0.11022 + 0x3fefccb0f4323aa3, 0xbfbc9b6eb6165c42, // 0.99374, -0.11175 + 0x3fefcb4703914354, 0xbfbcff533b307dc1, // 0.99356, -0.11327 + 0x3fefc9d82bc2915e, 0xbfbd633347858ce4, // 0.99339, -0.11479 + 0x3fefc8646cfeb721, 0xbfbdc70ecbae9fc8, // 0.99321, -0.11632 + 0x3fefc6ebc77f0887, 0xbfbe2ae5b8457f77, // 0.99303, -0.11784 + 0x3fefc56e3b7d9af6, 0xbfbe8eb7fde4aa3e, // 0.99285, -0.11937 + 0x3fefc3ebc935454c, 0xbfbef2858d27561b, // 0.99267, -0.12089 + 0x3fefc26470e19fd3, 0xbfbf564e56a9730e, // 0.99248, -0.12241 + 0x3fefc0d832bf043a, 0xbfbfba124b07ad85, // 0.99229, -0.12393 + 0x3fefbf470f0a8d88, 0xbfc00ee8ad6fb85b, // 0.9921, -0.12545 + 0x3fefbdb106021816, 0xbfc040c5bb67747e, // 0.99191, -0.12698 + 0x3fefbc1617e44186, 0xbfc072a047ba831d, // 0.99171, -0.1285 + 0x3fefba7644f068b5, 0xbfc0a4784ab8bf1d, // 0.99151, -0.13002 + 0x3fefb8d18d66adb7, 0xbfc0d64dbcb26786, // 0.99131, -0.13154 + 0x3fefb727f187f1c7, 0xbfc1082095f820b0, // 0.99111, -0.13306 + 0x3fefb5797195d741, 0xbfc139f0cedaf576, // 0.9909, -0.13458 + 0x3fefb3c60dd2c199, 0xbfc16bbe5fac5865, // 0.9907, -0.1361 + 0x3fefb20dc681d54d, 0xbfc19d8940be24e7, // 0.99049, -0.13762 + 0x3fefb0509be6f7db, 0xbfc1cf516a62a077, // 0.99027, -0.13914 + 0x3fefae8e8e46cfbb, 0xbfc20116d4ec7bce, // 0.99006, -0.14066 + 0x3fefacc79de6c44f, 0xbfc232d978aed413, // 0.98984, -0.14218 + 0x3fefaafbcb0cfddc, 0xbfc264994dfd340a, // 0.98962, -0.1437 + 0x3fefa92b1600657c, 0xbfc296564d2b953e, // 0.9894, -0.14521 + 0x3fefa7557f08a517, 0xbfc2c8106e8e613a, // 0.98918, -0.14673 + 0x3fefa57b066e2754, 0xbfc2f9c7aa7a72af, // 0.98895, -0.14825 + 0x3fefa39bac7a1791, 0xbfc32b7bf94516a7, // 0.98872, -0.14976 + 0x3fefa1b7717661d5, 0xbfc35d2d53440db2, // 0.98849, -0.15128 + 0x3fef9fce55adb2c8, 0xbfc38edbb0cd8d14, // 0.98826, -0.1528 + 0x3fef9de0596b77a3, 0xbfc3c0870a383ff6, // 0.98802, -0.15431 + 0x3fef9bed7cfbde29, 0xbfc3f22f57db4893, // 0.98778, -0.15583 + 0x3fef99f5c0abd496, 0xbfc423d4920e4166, // 0.98754, -0.15734 + 0x3fef97f924c9099b, 0xbfc45576b1293e5a, // 0.9873, -0.15886 + 0x3fef95f7a9a1ec47, 0xbfc48715ad84cdf5, // 0.98706, -0.16037 + 0x3fef93f14f85ac08, 0xbfc4b8b17f79fa88, // 0.98681, -0.16189 + 0x3fef91e616c43891, 0xbfc4ea4a1f624b61, // 0.98656, -0.1634 + 0x3fef8fd5ffae41db, 0xbfc51bdf8597c5f2, // 0.98631, -0.16491 + 0x3fef8dc10a95380d, 0xbfc54d71aa74ef02, // 0.98605, -0.16643 + 0x3fef8ba737cb4b78, 0xbfc57f008654cbde, // 0.9858, -0.16794 + 0x3fef898887a36c84, 0xbfc5b08c1192e381, // 0.98554, -0.16945 + 0x3fef8764fa714ba9, 0xbfc5e214448b3fc6, // 0.98528, -0.17096 + 0x3fef853c9089595e, 0xbfc61399179a6e94, // 0.98501, -0.17247 + 0x3fef830f4a40c60c, 0xbfc6451a831d830d, // 0.98475, -0.17398 + 0x3fef80dd27ed8204, 0xbfc676987f7216b8, // 0.98448, -0.17549 + 0x3fef7ea629e63d6e, 0xbfc6a81304f64ab2, // 0.98421, -0.177 + 0x3fef7c6a50826840, 0xbfc6d98a0c08c8da, // 0.98394, -0.17851 + 0x3fef7a299c1a322a, 0xbfc70afd8d08c4ff, // 0.98366, -0.18002 + 0x3fef77e40d068a90, 0xbfc73c6d8055fe0a, // 0.98339, -0.18153 + 0x3fef7599a3a12077, 0xbfc76dd9de50bf31, // 0.98311, -0.18304 + 0x3fef734a60446279, 0xbfc79f429f59e11d, // 0.98282, -0.18455 + 0x3fef70f6434b7eb7, 0xbfc7d0a7bbd2cb1b, // 0.98254, -0.18606 + 0x3fef6e9d4d1262ca, 0xbfc802092c1d744b, // 0.98225, -0.18756 + 0x3fef6c3f7df5bbb7, 0xbfc83366e89c64c5, // 0.98196, -0.18907 + 0x3fef69dcd652f5de, 0xbfc864c0e9b2b6cf, // 0.98167, -0.19057 + 0x3fef677556883cee, 0xbfc8961727c41804, // 0.98138, -0.19208 + 0x3fef6508fef47bd5, 0xbfc8c7699b34ca7e, // 0.98108, -0.19359 + 0x3fef6297cff75cb0, 0xbfc8f8b83c69a60a, // 0.98079, -0.19509 + 0x3fef6021c9f148c2, 0xbfc92a0303c8194f, // 0.98048, -0.19659 + 0x3fef5da6ed43685d, 0xbfc95b49e9b62af9, // 0.98018, -0.1981 + 0x3fef5b273a4fa2d9, 0xbfc98c8ce69a7aec, // 0.97988, -0.1996 + 0x3fef58a2b1789e84, 0xbfc9bdcbf2dc4366, // 0.97957, -0.2011 + 0x3fef56195321c090, 0xbfc9ef0706e35a35, // 0.97926, -0.20261 + 0x3fef538b1faf2d07, 0xbfca203e1b1831da, // 0.97895, -0.20411 + 0x3fef50f81785c6b9, 0xbfca517127e3dabc, // 0.97863, -0.20561 + 0x3fef4e603b0b2f2d, 0xbfca82a025b00451, // 0.97832, -0.20711 + 0x3fef4bc38aa5c694, 0xbfcab3cb0ce6fe44, // 0.978, -0.20861 + 0x3fef492206bcabb4, 0xbfcae4f1d5f3b9ab, // 0.97768, -0.21011 + 0x3fef467bafb7bbe0, 0xbfcb16147941ca2a, // 0.97735, -0.21161 + 0x3fef43d085ff92dd, 0xbfcb4732ef3d6722, // 0.97703, -0.21311 + 0x3fef412089fd8adc, 0xbfcb784d30536cda, // 0.9767, -0.21461 + 0x3fef3e6bbc1bbc65, 0xbfcba96334f15dad, // 0.97637, -0.21611 + 0x3fef3bb21cc4fe47, 0xbfcbda74f5856330, // 0.97604, -0.2176 + 0x3fef38f3ac64e589, 0xbfcc0b826a7e4f63, // 0.9757, -0.2191 + 0x3fef36306b67c556, 0xbfcc3c8b8c4b9dd7, // 0.97536, -0.2206 + 0x3fef33685a3aaef0, 0xbfcc6d90535d74dc, // 0.97503, -0.22209 + 0x3fef309b794b719f, 0xbfcc9e90b824a6a9, // 0.97468, -0.22359 + 0x3fef2dc9c9089a9d, 0xbfcccf8cb312b286, // 0.97434, -0.22508 + 0x3fef2af349e17507, 0xbfcd00843c99c5f9, // 0.97399, -0.22658 + 0x3fef2817fc4609ce, 0xbfcd31774d2cbdee, // 0.97364, -0.22807 + 0x3fef2537e0a71f9f, 0xbfcd6265dd3f27e3, // 0.97329, -0.22957 + 0x3fef2252f7763ada, 0xbfcd934fe5454311, // 0.97294, -0.23106 + 0x3fef1f6941259d7a, 0xbfcdc4355db40195, // 0.97258, -0.23255 + 0x3fef1c7abe284708, 0xbfcdf5163f01099a, // 0.97223, -0.23404 + 0x3fef19876ef1f486, 0xbfce25f281a2b684, // 0.97187, -0.23553 + 0x3fef168f53f7205d, 0xbfce56ca1e101a1b, // 0.9715, -0.23702 + 0x3fef13926dad024e, 0xbfce879d0cc0fdaf, // 0.97114, -0.23851 + 0x3fef1090bc898f5f, 0xbfceb86b462de348, // 0.97077, -0.24 + 0x3fef0d8a410379c5, 0xbfcee934c2d006c7, // 0.9704, -0.24149 + 0x3fef0a7efb9230d7, 0xbfcf19f97b215f1a, // 0.97003, -0.24298 + 0x3fef076eecade0fa, 0xbfcf4ab9679c9f5c, // 0.96966, -0.24447 + 0x3fef045a14cf738c, 0xbfcf7b7480bd3801, // 0.96928, -0.24596 + 0x3fef014074708ed3, 0xbfcfac2abeff57ff, // 0.9689, -0.24744 + 0x3feefe220c0b95ec, 0xbfcfdcdc1adfedf8, // 0.96852, -0.24893 + 0x3feefafedc1ba8b7, 0xbfd006c4466e54af, // 0.96814, -0.25041 + 0x3feef7d6e51ca3c0, 0xbfd01f1806b9fdd2, // 0.96775, -0.2519 + 0x3feef4aa278b2032, 0xbfd037694a928cac, // 0.96737, -0.25338 + 0x3feef178a3e473c2, 0xbfd04fb80e37fdae, // 0.96698, -0.25487 + 0x3feeee425aa6b09a, 0xbfd068044deab002, // 0.96658, -0.25635 + 0x3feeeb074c50a544, 0xbfd0804e05eb661e, // 0.96619, -0.25783 + 0x3feee7c77961dc9e, 0xbfd09895327b465e, // 0.96579, -0.25931 + 0x3feee482e25a9dbc, 0xbfd0b0d9cfdbdb90, // 0.96539, -0.26079 + 0x3feee13987bbebdc, 0xbfd0c91bda4f158d, // 0.96499, -0.26227 + 0x3feeddeb6a078651, 0xbfd0e15b4e1749cd, // 0.96459, -0.26375 + 0x3feeda9889bfe86a, 0xbfd0f998277733f7, // 0.96418, -0.26523 + 0x3feed740e7684963, 0xbfd111d262b1f677, // 0.96378, -0.26671 + 0x3feed3e483849c51, 0xbfd12a09fc0b1b12, // 0.96337, -0.26819 + 0x3feed0835e999009, 0xbfd1423eefc69378, // 0.96295, -0.26967 + 0x3feecd1d792c8f10, 0xbfd15a713a28b9d9, // 0.96254, -0.27115 + 0x3feec9b2d3c3bf84, 0xbfd172a0d7765177, // 0.96212, -0.27262 + 0x3feec6436ee60309, 0xbfd18acdc3f4873a, // 0.9617, -0.2741 + 0x3feec2cf4b1af6b2, 0xbfd1a2f7fbe8f243, // 0.96128, -0.27557 + 0x3feebf5668eaf2ef, 0xbfd1bb1f7b999480, // 0.96086, -0.27705 + 0x3feebbd8c8df0b74, 0xbfd1d3443f4cdb3d, // 0.96043, -0.27852 + 0x3feeb8566b810f2a, 0xbfd1eb6643499fbb, // 0.96, -0.27999 + 0x3feeb4cf515b8811, 0xbfd2038583d727bd, // 0.95957, -0.28146 + 0x3feeb1437af9bb34, 0xbfd21ba1fd3d2623, // 0.95914, -0.28294 + 0x3feeadb2e8e7a88e, 0xbfd233bbabc3bb72, // 0.9587, -0.28441 + 0x3feeaa1d9bb20af3, 0xbfd24bd28bb37672, // 0.95827, -0.28588 + 0x3feea68393e65800, 0xbfd263e6995554ba, // 0.95783, -0.28735 + 0x3feea2e4d212c000, 0xbfd27bf7d0f2c346, // 0.95738, -0.28882 + 0x3fee9f4156c62dda, 0xbfd294062ed59f05, // 0.95694, -0.29028 + 0x3fee9b99229046f8, 0xbfd2ac11af483572, // 0.95649, -0.29175 + 0x3fee97ec36016b30, 0xbfd2c41a4e954520, // 0.95605, -0.29322 + 0x3fee943a91aab4b4, 0xbfd2dc200907fe51, // 0.95559, -0.29469 + 0x3fee9084361df7f3, 0xbfd2f422daec0386, // 0.95514, -0.29615 + 0x3fee8cc923edc388, 0xbfd30c22c08d6a13, // 0.95469, -0.29762 + 0x3fee89095bad6025, 0xbfd3241fb638baaf, // 0.95423, -0.29908 + 0x3fee8544ddf0d075, 0xbfd33c19b83af207, // 0.95377, -0.30054 + 0x3fee817bab4cd10d, 0xbfd35410c2e18152, // 0.95331, -0.30201 + 0x3fee7dadc456d850, 0xbfd36c04d27a4edf, // 0.95284, -0.30347 + 0x3fee79db29a5165a, 0xbfd383f5e353b6aa, // 0.95238, -0.30493 + 0x3fee7603dbce74e9, 0xbfd39be3f1bc8aef, // 0.95191, -0.30639 + 0x3fee7227db6a9744, 0xbfd3b3cefa0414b7, // 0.95144, -0.30785 + 0x3fee6e472911da27, 0xbfd3cbb6f87a146e, // 0.95096, -0.30931 + 0x3fee6a61c55d53a7, 0xbfd3e39be96ec271, // 0.95049, -0.31077 + 0x3fee6677b0e6d31e, 0xbfd3fb7dc932cfa4, // 0.95001, -0.31222 + 0x3fee6288ec48e112, 0xbfd4135c94176602, // 0.94953, -0.31368 + 0x3fee5e95781ebf1c, 0xbfd42b38466e2928, // 0.94905, -0.31514 + 0x3fee5a9d550467d3, 0xbfd44310dc8936f0, // 0.94856, -0.31659 + 0x3fee56a083968eb1, 0xbfd45ae652bb2800, // 0.94807, -0.31805 + 0x3fee529f04729ffc, 0xbfd472b8a5571054, // 0.94759, -0.3195 + 0x3fee4e98d836c0af, 0xbfd48a87d0b07fd7, // 0.94709, -0.32096 + 0x3fee4a8dff81ce5e, 0xbfd4a253d11b82f3, // 0.9466, -0.32241 + 0x3fee467e7af35f23, 0xbfd4ba1ca2eca31c, // 0.94611, -0.32386 + 0x3fee426a4b2bc17e, 0xbfd4d1e24278e76a, // 0.94561, -0.32531 + 0x3fee3e5170cbfc46, 0xbfd4e9a4ac15d520, // 0.94511, -0.32676 + 0x3fee3a33ec75ce85, 0xbfd50163dc197047, // 0.9446, -0.32821 + 0x3fee3611becbaf69, 0xbfd5191fceda3c35, // 0.9441, -0.32966 + 0x3fee31eae870ce25, 0xbfd530d880af3c24, // 0.94359, -0.33111 + 0x3fee2dbf6a0911d9, 0xbfd5488dedeff3be, // 0.94308, -0.33255 + 0x3fee298f4439197a, 0xbfd5604012f467b4, // 0.94257, -0.334 + 0x3fee255a77a63bb8, 0xbfd577eeec151e47, // 0.94206, -0.33545 + 0x3fee212104f686e5, 0xbfd58f9a75ab1fdd, // 0.94154, -0.33689 + 0x3fee1ce2ecd0c0d8, 0xbfd5a742ac0ff78d, // 0.94103, -0.33833 + 0x3fee18a02fdc66d9, 0xbfd5bee78b9db3b6, // 0.94051, -0.33978 + 0x3fee1458cec1ad83, 0xbfd5d68910aee686, // 0.93998, -0.34122 + 0x3fee100cca2980ac, 0xbfd5ee27379ea693, // 0.93946, -0.34266 + 0x3fee0bbc22bd8349, 0xbfd605c1fcc88f63, // 0.93893, -0.3441 + 0x3fee0766d9280f54, 0xbfd61d595c88c203, // 0.9384, -0.34554 + 0x3fee030cee1435b8, 0xbfd634ed533be58e, // 0.93787, -0.34698 + 0x3fedfeae622dbe2b, 0xbfd64c7ddd3f27c6, // 0.93734, -0.34842 + 0x3fedfa4b3621271d, 0xbfd6640af6f03d9e, // 0.9368, -0.34986 + 0x3fedf5e36a9ba59c, 0xbfd67b949cad63ca, // 0.93627, -0.35129 + 0x3fedf177004b2534, 0xbfd6931acad55f51, // 0.93573, -0.35273 + 0x3feded05f7de47da, 0xbfd6aa9d7dc77e16, // 0.93518, -0.35416 + 0x3fede890520465ce, 0xbfd6c21cb1e39771, // 0.93464, -0.3556 + 0x3fede4160f6d8d81, 0xbfd6d998638a0cb5, // 0.93409, -0.35703 + 0x3feddf9730ca837b, 0xbfd6f1108f1bc9c5, // 0.93354, -0.35846 + 0x3feddb13b6ccc23d, 0xbfd7088530fa459e, // 0.93299, -0.3599 + 0x3fedd68ba2267a25, 0xbfd71ff6458782ec, // 0.93244, -0.36133 + 0x3fedd1fef38a915a, 0xbfd73763c9261092, // 0.93188, -0.36276 + 0x3fedcd6dabaca3a5, 0xbfd74ecdb8390a3e, // 0.93133, -0.36418 + 0x3fedc8d7cb410260, 0xbfd766340f2418f6, // 0.93077, -0.36561 + 0x3fedc43d52fcb453, 0xbfd77d96ca4b73a6, // 0.93021, -0.36704 + 0x3fedbf9e4395759a, 0xbfd794f5e613dfae, // 0.92964, -0.36847 + 0x3fedbafa9dc1b78d, 0xbfd7ac515ee2b172, // 0.92907, -0.36989 + 0x3fedb6526238a09b, 0xbfd7c3a9311dcce7, // 0.92851, -0.37132 + 0x3fedb1a591b20c38, 0xbfd7dafd592ba621, // 0.92794, -0.37274 + 0x3fedacf42ce68ab9, 0xbfd7f24dd37341e3, // 0.92736, -0.37416 + 0x3feda83e348f613b, 0xbfd8099a9c5c362d, // 0.92679, -0.37559 + 0x3feda383a9668988, 0xbfd820e3b04eaac4, // 0.92621, -0.37701 + 0x3fed9ec48c26b1f3, 0xbfd838290bb359c8, // 0.92563, -0.37843 + 0x3fed9a00dd8b3d46, 0xbfd84f6aaaf3903f, // 0.92505, -0.37985 + 0x3fed95389e50429b, 0xbfd866a88a792ea0, // 0.92447, -0.38127 + 0x3fed906bcf328d46, 0xbfd87de2a6aea963, // 0.92388, -0.38268 + 0x3fed8b9a70ef9cb4, 0xbfd89518fbff098e, // 0.92329, -0.3841 + 0x3fed86c48445a450, 0xbfd8ac4b86d5ed44, // 0.9227, -0.38552 + 0x3fed81ea09f38b63, 0xbfd8c37a439f884f, // 0.92211, -0.38693 + 0x3fed7d0b02b8ecf9, 0xbfd8daa52ec8a4af, // 0.92151, -0.38835 + 0x3fed78276f5617c6, 0xbfd8f1cc44bea329, // 0.92092, -0.38976 + 0x3fed733f508c0dff, 0xbfd908ef81ef7bd1, // 0.92032, -0.39117 + 0x3fed6e52a71c8547, 0xbfd9200ee2c9be97, // 0.91972, -0.39258 + 0x3fed696173c9e68b, 0xbfd9372a63bc93d7, // 0.91911, -0.39399 + 0x3fed646bb7574de5, 0xbfd94e420137bce3, // 0.91851, -0.3954 + 0x3fed5f7172888a7f, 0xbfd96555b7ab948f, // 0.9179, -0.39681 + 0x3fed5a72a6221e73, 0xbfd97c6583890fc2, // 0.91729, -0.39822 + 0x3fed556f52e93eb1, 0xbfd993716141bdfe, // 0.91668, -0.39962 + 0x3fed506779a3d2d9, 0xbfd9aa794d47c9ee, // 0.91606, -0.40103 + 0x3fed4b5b1b187524, 0xbfd9c17d440df9f2, // 0.91545, -0.40243 + 0x3fed464a380e7242, 0xbfd9d87d4207b0ab, // 0.91483, -0.40384 + 0x3fed4134d14dc93a, 0xbfd9ef7943a8ed8a, // 0.91421, -0.40524 + 0x3fed3c1ae79f2b4e, 0xbfda067145664d57, // 0.91359, -0.40664 + 0x3fed36fc7bcbfbdc, 0xbfda1d6543b50ac0, // 0.91296, -0.40804 + 0x3fed31d98e9e503a, 0xbfda34553b0afee5, // 0.91234, -0.40944 + 0x3fed2cb220e0ef9f, 0xbfda4b4127dea1e4, // 0.91171, -0.41084 + 0x3fed2786335f52fc, 0xbfda622906a70b63, // 0.91107, -0.41224 + 0x3fed2255c6e5a4e1, 0xbfda790cd3dbf31a, // 0.91044, -0.41364 + 0x3fed1d20dc40c15c, 0xbfda8fec8bf5b166, // 0.90981, -0.41503 + 0x3fed17e7743e35dc, 0xbfdaa6c82b6d3fc9, // 0.90917, -0.41643 + 0x3fed12a98fac410c, 0xbfdabd9faebc3980, // 0.90853, -0.41782 + 0x3fed0d672f59d2b9, 0xbfdad473125cdc08, // 0.90789, -0.41922 + 0x3fed082054168bac, 0xbfdaeb4252ca07ab, // 0.90724, -0.42061 + 0x3fed02d4feb2bd92, 0xbfdb020d6c7f4009, // 0.9066, -0.422 + 0x3fecfd852fff6ad4, 0xbfdb18d45bf8aca6, // 0.90595, -0.42339 + 0x3fecf830e8ce467b, 0xbfdb2f971db31972, // 0.9053, -0.42478 + 0x3fecf2d829f1b40e, 0xbfdb4655ae2bf757, // 0.90464, -0.42617 + 0x3feced7af43cc773, 0xbfdb5d1009e15cc0, // 0.90399, -0.42756 + 0x3fece819488344ce, 0xbfdb73c62d520624, // 0.90333, -0.42894 + 0x3fece2b32799a060, 0xbfdb8a7814fd5693, // 0.90267, -0.43033 + 0x3fecdd489254fe65, 0xbfdba125bd63583e, // 0.90201, -0.43171 + 0x3fecd7d9898b32f6, 0xbfdbb7cf2304bd01, // 0.90135, -0.43309 + 0x3fecd2660e12c1e6, 0xbfdbce744262deee, // 0.90068, -0.43448 + 0x3fecccee20c2de9f, 0xbfdbe51517ffc0d9, // 0.90002, -0.43586 + 0x3fecc771c2736c09, 0xbfdbfbb1a05e0edc, // 0.89935, -0.43724 + 0x3fecc1f0f3fcfc5c, 0xbfdc1249d8011ee7, // 0.89867, -0.43862 + 0x3fecbc6bb638d10b, 0xbfdc28ddbb6cf145, // 0.898, -0.43999 + 0x3fecb6e20a00da99, 0xbfdc3f6d47263129, // 0.89732, -0.44137 + 0x3fecb153f02fb87d, 0xbfdc55f877b23537, // 0.89665, -0.44275 + 0x3fecabc169a0b901, 0xbfdc6c7f4997000a, // 0.89597, -0.44412 + 0x3feca62a772fd919, 0xbfdc8301b95b40c2, // 0.89528, -0.4455 + 0x3feca08f19b9c449, 0xbfdc997fc3865388, // 0.8946, -0.44687 + 0x3fec9aef521bd480, 0xbfdcaff964a0421d, // 0.89391, -0.44824 + 0x3fec954b213411f5, 0xbfdcc66e9931c45d, // 0.89322, -0.44961 + 0x3fec8fa287e13305, 0xbfdcdcdf5dc440ce, // 0.89253, -0.45098 + 0x3fec89f587029c13, 0xbfdcf34baee1cd21, // 0.89184, -0.45235 + 0x3fec84441f785f61, 0xbfdd09b389152ec1, // 0.89115, -0.45372 + 0x3fec7e8e52233cf3, 0xbfdd2016e8e9db5b, // 0.89045, -0.45508 + 0x3fec78d41fe4a267, 0xbfdd3675caebf962, // 0.88975, -0.45645 + 0x3fec7315899eaad7, 0xbfdd4cd02ba8609c, // 0.88905, -0.45781 + 0x3fec6d5290341eb2, 0xbfdd632607ac9aa9, // 0.88835, -0.45918 + 0x3fec678b3488739b, 0xbfdd79775b86e389, // 0.88764, -0.46054 + 0x3fec61bf777fcc48, 0xbfdd8fc423c62a25, // 0.88693, -0.4619 + 0x3fec5bef59fef85a, 0xbfdda60c5cfa10d8, // 0.88622, -0.46326 + 0x3fec561adceb743e, 0xbfddbc5003b2edf8, // 0.88551, -0.46462 + 0x3fec5042012b6907, 0xbfddd28f1481cc58, // 0.8848, -0.46598 + 0x3fec4a64c7a5ac4c, 0xbfdde8c98bf86bd6, // 0.88408, -0.46733 + 0x3fec44833141c004, 0xbfddfeff66a941de, // 0.88336, -0.46869 + 0x3fec3e9d3ee7d262, 0xbfde1530a12779f4, // 0.88264, -0.47004 + 0x3fec38b2f180bdb1, 0xbfde2b5d3806f63b, // 0.88192, -0.4714 + 0x3fec32c449f60831, 0xbfde418527dc4ffa, // 0.8812, -0.47275 + 0x3fec2cd14931e3f1, 0xbfde57a86d3cd824, // 0.88047, -0.4741 + 0x3fec26d9f01f2eaf, 0xbfde6dc704be97e2, // 0.87974, -0.47545 + 0x3fec20de3fa971b0, 0xbfde83e0eaf85113, // 0.87901, -0.4768 + 0x3fec1ade38bce19b, 0xbfde99f61c817eda, // 0.87828, -0.47815 + 0x3fec14d9dc465e58, 0xbfdeb00695f25620, // 0.87755, -0.47949 + 0x3fec0ed12b3372e9, 0xbfdec61253e3c61b, // 0.87681, -0.48084 + 0x3fec08c426725549, 0xbfdedc1952ef78d5, // 0.87607, -0.48218 + 0x3fec02b2cef1e641, 0xbfdef21b8fafd3b5, // 0.87533, -0.48353 + 0x3febfc9d25a1b147, 0xbfdf081906bff7fd, // 0.87459, -0.48487 + 0x3febf6832b71ec5b, 0xbfdf1e11b4bbc35c, // 0.87384, -0.48621 + 0x3febf064e15377dd, 0xbfdf3405963fd068, // 0.87309, -0.48755 + 0x3febea424837de6d, 0xbfdf49f4a7e97729, // 0.87235, -0.48889 + 0x3febe41b611154c1, 0xbfdf5fdee656cda3, // 0.8716, -0.49023 + 0x3febddf02cd2b983, 0xbfdf75c44e26a852, // 0.87084, -0.49156 + 0x3febd7c0ac6f952a, 0xbfdf8ba4dbf89aba, // 0.87009, -0.4929 + 0x3febd18ce0dc19d6, 0xbfdfa1808c6cf7e0, // 0.86933, -0.49423 + 0x3febcb54cb0d2327, 0xbfdfb7575c24d2de, // 0.86857, -0.49557 + 0x3febc5186bf8361d, 0xbfdfcd2947c1ff57, // 0.86781, -0.4969 + 0x3febbed7c49380ea, 0xbfdfe2f64be7120f, // 0.86705, -0.49823 + 0x3febb892d5d5dad5, 0xbfdff8be6537615e, // 0.86628, -0.49956 + 0x3febb249a0b6c40d, 0xbfe00740c82b82e0, // 0.86551, -0.50089 + 0x3febabfc262e6586, 0xbfe0121fe4f56d2c, // 0.86474, -0.50221 + 0x3feba5aa673590d2, 0xbfe01cfc874c3eb7, // 0.86397, -0.50354 + 0x3feb9f5464c5bffc, 0xbfe027d6ad83287e, // 0.8632, -0.50486 + 0x3feb98fa1fd9155e, 0xbfe032ae55edbd95, // 0.86242, -0.50619 + 0x3feb929b996a5b7f, 0xbfe03d837edff370, // 0.86165, -0.50751 + 0x3feb8c38d27504e9, 0xbfe0485626ae221a, // 0.86087, -0.50883 + 0x3feb85d1cbf52c02, 0xbfe053264bad0483, // 0.86009, -0.51015 + 0x3feb7f6686e792ea, 0xbfe05df3ec31b8b6, // 0.8593, -0.51147 + 0x3feb78f70449a34b, 0xbfe068bf0691c028, // 0.85852, -0.51279 + 0x3feb728345196e3e, 0xbfe073879922ffed, // 0.85773, -0.5141 + 0x3feb6c0b4a55ac17, 0xbfe07e4da23bc102, // 0.85694, -0.51542 + 0x3feb658f14fdbc47, 0xbfe089112032b08c, // 0.85615, -0.51673 + 0x3feb5f0ea611a532, 0xbfe093d2115ee018, // 0.85535, -0.51804 + 0x3feb5889fe921405, 0xbfe09e907417c5e1, // 0.85456, -0.51936 + 0x3feb52011f805c92, 0xbfe0a94c46b53d0b, // 0.85376, -0.52067 + 0x3feb4b7409de7925, 0xbfe0b405878f85ec, // 0.85296, -0.52198 + 0x3feb44e2beaf0a61, 0xbfe0bebc34ff4646, // 0.85216, -0.52328 + 0x3feb3e4d3ef55712, 0xbfe0c9704d5d898f, // 0.85136, -0.52459 + 0x3feb37b38bb54c09, 0xbfe0d421cf03c12b, // 0.85055, -0.5259 + 0x3feb3115a5f37bf4, 0xbfe0ded0b84bc4b5, // 0.84974, -0.5272 + 0x3feb2a738eb51f33, 0xbfe0e97d078fd23b, // 0.84893, -0.5285 + 0x3feb23cd470013b4, 0xbfe0f426bb2a8e7d, // 0.84812, -0.5298 + 0x3feb1d22cfdadcc6, 0xbfe0fecdd1770537, // 0.84731, -0.5311 + 0x3feb16742a4ca2f5, 0xbfe1097248d0a956, // 0.84649, -0.5324 + 0x3feb0fc1575d33db, 0xbfe114141f935545, // 0.84567, -0.5337 + 0x3feb090a58150200, 0xbfe11eb3541b4b22, // 0.84485, -0.535 + 0x3feb024f2d7d24a9, 0xbfe1294fe4c5350a, // 0.84403, -0.53629 + 0x3feafb8fd89f57b6, 0xbfe133e9cfee254e, // 0.84321, -0.53759 + 0x3feaf4cc5a85fb73, 0xbfe13e8113f396c1, // 0.84238, -0.53888 + 0x3feaee04b43c1474, 0xbfe14915af336ceb, // 0.84155, -0.54017 + 0x3feae738e6cd4b67, 0xbfe153a7a00bf453, // 0.84073, -0.54146 + 0x3feae068f345ecef, 0xbfe15e36e4dbe2bc, // 0.83989, -0.54275 + 0x3fead994dab2e979, 0xbfe168c37c025764, // 0.83906, -0.54404 + 0x3fead2bc9e21d511, 0xbfe1734d63dedb49, // 0.83822, -0.54532 + 0x3feacbe03ea0e73b, 0xbfe17dd49ad16161, // 0.83739, -0.54661 + 0x3feac4ffbd3efac8, 0xbfe188591f3a46e5, // 0.83655, -0.54789 + 0x3feabe1b1b0b8dac, 0xbfe192daef7a5386, // 0.83571, -0.54918 + 0x3feab7325916c0d4, 0xbfe19d5a09f2b9b8, // 0.83486, -0.55046 + 0x3feab045787157ff, 0xbfe1a7d66d0516e6, // 0.83402, -0.55174 + 0x3feaa9547a2cb98e, 0xbfe1b250171373be, // 0.83317, -0.55302 + 0x3feaa25f5f5aee60, 0xbfe1bcc706804467, // 0.83232, -0.55429 + 0x3fea9b66290ea1a3, 0xbfe1c73b39ae68c8, // 0.83147, -0.55557 + 0x3fea9468d85b20ae, 0xbfe1d1acaf012cc2, // 0.83062, -0.55685 + 0x3fea8d676e545ad2, 0xbfe1dc1b64dc4872, // 0.82976, -0.55812 + 0x3fea8661ec0ee133, 0xbfe1e68759a3e074, // 0.8289, -0.55939 + 0x3fea7f58529fe69d, 0xbfe1f0f08bbc861b, // 0.82805, -0.56066 + 0x3fea784aa31d3f55, 0xbfe1fb56f98b37b8, // 0.82718, -0.56193 + 0x3fea7138de9d60f5, 0xbfe205baa17560d6, // 0.82632, -0.5632 + 0x3fea6a230637623b, 0xbfe2101b81e0da78, // 0.82546, -0.56447 + 0x3fea63091b02fae2, 0xbfe21a799933eb58, // 0.82459, -0.56573 + 0x3fea5beb1e188375, 0xbfe224d4e5d5482e, // 0.82372, -0.567 + 0x3fea54c91090f524, 0xbfe22f2d662c13e1, // 0.82285, -0.56826 + 0x3fea4da2f385e997, 0xbfe23983189fdfd5, // 0.82198, -0.56952 + 0x3fea4678c8119ac8, 0xbfe243d5fb98ac1f, // 0.8211, -0.57078 + 0x3fea3f4a8f4ee2d2, 0xbfe24e260d7ee7c9, // 0.82023, -0.57204 + 0x3fea38184a593bc6, 0xbfe258734cbb7110, // 0.81935, -0.5733 + 0x3fea30e1fa4cbf81, 0xbfe262bdb7b795a2, // 0.81847, -0.57455 + 0x3fea29a7a0462782, 0xbfe26d054cdd12df, // 0.81758, -0.57581 + 0x3fea22693d62ccb9, 0xbfe2774a0a961612, // 0.8167, -0.57706 + 0x3fea1b26d2c0a75e, 0xbfe2818bef4d3cba, // 0.81581, -0.57831 + 0x3fea13e0617e4ec7, 0xbfe28bcaf96d94ba, // 0.81493, -0.57956 + 0x3fea0c95eabaf937, 0xbfe2960727629ca8, // 0.81404, -0.58081 + 0x3fea05476f967bb5, 0xbfe2a040779843fb, // 0.81314, -0.58206 + 0x3fe9fdf4f13149de, 0xbfe2aa76e87aeb58, // 0.81225, -0.58331 + 0x3fe9f69e70ac75bc, 0xbfe2b4aa787764c4, // 0.81135, -0.58455 + 0x3fe9ef43ef29af94, 0xbfe2bedb25faf3ea, // 0.81046, -0.5858 + 0x3fe9e7e56dcb45bd, 0xbfe2c908ef734e57, // 0.80956, -0.58704 + 0x3fe9e082edb42472, 0xbfe2d333d34e9bb7, // 0.80866, -0.58828 + 0x3fe9d91c7007d5a6, 0xbfe2dd5bcffb7616, // 0.80775, -0.58952 + 0x3fe9d1b1f5ea80d6, 0xbfe2e780e3e8ea16, // 0.80685, -0.59076 + 0x3fe9ca438080eadb, 0xbfe2f1a30d86773a, // 0.80594, -0.592 + 0x3fe9c2d110f075c3, 0xbfe2fbc24b441015, // 0.80503, -0.59323 + 0x3fe9bb5aa85f2098, 0xbfe305de9b921a94, // 0.80412, -0.59447 + 0x3fe9b3e047f38741, 0xbfe30ff7fce17035, // 0.80321, -0.5957 + 0x3fe9ac61f0d4e247, 0xbfe31a0e6da35e44, // 0.80229, -0.59693 + 0x3fe9a4dfa42b06b2, 0xbfe32421ec49a620, // 0.80138, -0.59816 + 0x3fe99d59631e65d5, 0xbfe32e3277467d6b, // 0.80046, -0.59939 + 0x3fe995cf2ed80d22, 0xbfe338400d0c8e57, // 0.79954, -0.60062 + 0x3fe98e410881a600, 0xbfe3424aac0ef7d6, // 0.79861, -0.60184 + 0x3fe986aef1457594, 0xbfe34c5252c14de1, // 0.79769, -0.60307 + 0x3fe97f18ea4e5c9e, 0xbfe35656ff9799ae, // 0.79676, -0.60429 + 0x3fe9777ef4c7d742, 0xbfe36058b10659f3, // 0.79584, -0.60551 + 0x3fe96fe111ddfce0, 0xbfe36a576582831b, // 0.79491, -0.60673 + 0x3fe9683f42bd7fe1, 0xbfe374531b817f8d, // 0.79398, -0.60795 + 0x3fe960998893ad8c, 0xbfe37e4bd1792fe2, // 0.79304, -0.60917 + 0x3fe958efe48e6dd7, 0xbfe3884185dfeb22, // 0.79211, -0.61038 + 0x3fe9514257dc4335, 0xbfe39234372c7f04, // 0.79117, -0.6116 + 0x3fe94990e3ac4a6c, 0xbfe39c23e3d63029, // 0.79023, -0.61281 + 0x3fe941db892e3a65, 0xbfe3a6108a54ba58, // 0.78929, -0.61402 + 0x3fe93a22499263fc, 0xbfe3affa292050b9, // 0.78835, -0.61523 + 0x3fe932652609b1cf, 0xbfe3b9e0beb19e18, // 0.7874, -0.61644 + 0x3fe92aa41fc5a815, 0xbfe3c3c44981c517, // 0.78646, -0.61765 + 0x3fe922df37f8646a, 0xbfe3cda4c80a6076, // 0.78551, -0.61885 + 0x3fe91b166fd49da2, 0xbfe3d78238c58343, // 0.78456, -0.62006 + 0x3fe91349c88da398, 0xbfe3e15c9a2db922, // 0.7836, -0.62126 + 0x3fe90b7943575efe, 0xbfe3eb33eabe0680, // 0.78265, -0.62246 + 0x3fe903a4e1665133, 0xbfe3f50828f1e8d2, // 0.78169, -0.62366 + 0x3fe8fbcca3ef940d, 0xbfe3fed9534556d4, // 0.78074, -0.62486 + 0x3fe8f3f08c28d9ac, 0xbfe408a76834c0c0, // 0.77978, -0.62606 + 0x3fe8ec109b486c49, 0xbfe41272663d108c, // 0.77882, -0.62725 + 0x3fe8e42cd2852e0a, 0xbfe41c3a4bdbaa26, // 0.77785, -0.62845 + 0x3fe8dc45331698cc, 0xbfe425ff178e6bb1, // 0.77689, -0.62964 + 0x3fe8d459be34bdfa, 0xbfe42fc0c7d3adbb, // 0.77592, -0.63083 + 0x3fe8cc6a75184655, 0xbfe4397f5b2a4380, // 0.77495, -0.63202 + 0x3fe8c47758fa71cb, 0xbfe4433ad0117b1d, // 0.77398, -0.63321 + 0x3fe8bc806b151741, 0xbfe44cf325091dd6, // 0.77301, -0.63439 + 0x3fe8b485aca2a468, 0xbfe456a858917046, // 0.77204, -0.63558 + 0x3fe8ac871ede1d88, 0xbfe4605a692b32a2, // 0.77106, -0.63676 + 0x3fe8a484c3031d50, 0xbfe46a095557a0f1, // 0.77008, -0.63794 + 0x3fe89c7e9a4dd4ab, 0xbfe473b51b987347, // 0.7691, -0.63912 + 0x3fe89474a5fb0a84, 0xbfe47d5dba6fde01, // 0.76812, -0.6403 + 0x3fe88c66e7481ba1, 0xbfe48703306091fe, // 0.76714, -0.64148 + 0x3fe884555f72fa6b, 0xbfe490a57bedbcdf, // 0.76615, -0.64266 + 0x3fe87c400fba2ebf, 0xbfe49a449b9b0938, // 0.76517, -0.64383 + 0x3fe87426f95cd5bd, 0xbfe4a3e08dec9ed6, // 0.76418, -0.645 + 0x3fe86c0a1d9aa195, 0xbfe4ad79516722f0, // 0.76319, -0.64618 + 0x3fe863e97db3d95a, 0xbfe4b70ee48fb869, // 0.7622, -0.64735 + 0x3fe85bc51ae958cc, 0xbfe4c0a145ec0004, // 0.7612, -0.64851 + 0x3fe8539cf67c9029, 0xbfe4ca30740218a3, // 0.76021, -0.64968 + 0x3fe84b7111af83f9, 0xbfe4d3bc6d589f80, // 0.75921, -0.65085 + 0x3fe843416dc4cce2, 0xbfe4dd453076b064, // 0.75821, -0.65201 + 0x3fe83b0e0bff976e, 0xbfe4e6cabbe3e5e9, // 0.75721, -0.65317 + 0x3fe832d6eda3a3e0, 0xbfe4f04d0e2859aa, // 0.75621, -0.65433 + 0x3fe82a9c13f545ff, 0xbfe4f9cc25cca486, // 0.7552, -0.65549 + 0x3fe8225d803964e5, 0xbfe503480159ded2, // 0.75419, -0.65665 + 0x3fe81a1b33b57acc, 0xbfe50cc09f59a09b, // 0.75319, -0.65781 + 0x3fe811d52faf94dc, 0xbfe51635fe5601d7, // 0.75218, -0.65896 + 0x3fe8098b756e52fa, 0xbfe51fa81cd99aa6, // 0.75117, -0.66011 + 0x3fe8013e0638e795, 0xbfe52916f96f8388, // 0.75015, -0.66127 + 0x3fe7f8ece3571771, 0xbfe5328292a35596, // 0.74914, -0.66242 + 0x3fe7f0980e113978, 0xbfe53beae7012abe, // 0.74812, -0.66356 + 0x3fe7e83f87b03686, 0xbfe5454ff5159dfb, // 0.7471, -0.66471 + 0x3fe7dfe3517d8937, 0xbfe54eb1bb6dcb8f, // 0.74608, -0.66586 + 0x3fe7d7836cc33db2, 0xbfe5581038975137, // 0.74506, -0.667 + 0x3fe7cf1fdacbf179, 0xbfe5616b6b204e6e, // 0.74403, -0.66814 + 0x3fe7c6b89ce2d333, 0xbfe56ac35197649e, // 0.74301, -0.66928 + 0x3fe7be4db453a27c, 0xbfe57417ea8bb75c, // 0.74198, -0.67042 + 0x3fe7b5df226aafb0, 0xbfe57d69348cec9f, // 0.74095, -0.67156 + 0x3fe7ad6ce874dbb6, 0xbfe586b72e2b2cfd, // 0.73992, -0.67269 + 0x3fe7a4f707bf97d2, 0xbfe59001d5f723df, // 0.73889, -0.67383 + 0x3fe79c7d8198e56e, 0xbfe599492a81ffbc, // 0.73785, -0.67496 + 0x3fe79400574f55e4, 0xbfe5a28d2a5d7250, // 0.73682, -0.67609 + 0x3fe78b7f8a320a52, 0xbfe5abcdd41bb0d8, // 0.73578, -0.67722 + 0x3fe782fb1b90b35b, 0xbfe5b50b264f7448, // 0.73474, -0.67835 + 0x3fe77a730cbb9100, 0xbfe5be451f8bf980, // 0.7337, -0.67948 + 0x3fe771e75f037261, 0xbfe5c77bbe65018c, // 0.73265, -0.6806 + 0x3fe7695813b9b594, 0xbfe5d0af016ed1d4, // 0.73161, -0.68172 + 0x3fe760c52c304764, 0xbfe5d9dee73e345c, // 0.73056, -0.68285 + 0x3fe7582ea9b9a329, 0xbfe5e30b6e6877f3, // 0.72951, -0.68397 + 0x3fe74f948da8d28d, 0xbfe5ec3495837074, // 0.72846, -0.68508 + 0x3fe746f6d9516d59, 0xbfe5f55a5b2576f8, // 0.72741, -0.6862 + 0x3fe73e558e079942, 0xbfe5fe7cbde56a0f, // 0.72636, -0.68732 + 0x3fe735b0ad2009b2, 0xbfe6079bbc5aadfa, // 0.7253, -0.68843 + 0x3fe72d0837efff97, 0xbfe610b7551d2cde, // 0.72425, -0.68954 + 0x3fe7245c2fcd492a, 0xbfe619cf86c55702, // 0.72319, -0.69065 + 0x3fe71bac960e41bf, 0xbfe622e44fec22ff, // 0.72213, -0.69176 + 0x3fe712f96c09d18d, 0xbfe62bf5af2b0dfd, // 0.72107, -0.69287 + 0x3fe70a42b3176d7a, 0xbfe63503a31c1be8, // 0.72, -0.69397 + 0x3fe701886c8f16e6, 0xbfe63e0e2a59d7aa, // 0.71894, -0.69508 + 0x3fe6f8ca99c95b75, 0xbfe64715437f535b, // 0.71787, -0.69618 + 0x3fe6f0093c1f54de, 0xbfe65018ed28287f, // 0.7168, -0.69728 + 0x3fe6e74454eaa8ae, 0xbfe6591925f0783e, // 0.71573, -0.69838 + 0x3fe6de7be585881d, 0xbfe66215ec74eb91, // 0.71466, -0.69947 + 0x3fe6d5afef4aafcc, 0xbfe66b0f3f52b386, // 0.71358, -0.70057 + 0x3fe6cce07395679f, 0xbfe674051d27896c, // 0.71251, -0.70166 + 0x3fe6c40d73c18275, 0xbfe67cf78491af10, // 0.71143, -0.70275 + 0x3fe6bb36f12b5e06, 0xbfe685e6742feeef, // 0.71035, -0.70385 + 0x3fe6b25ced2fe29c, 0xbfe68ed1eaa19c71, // 0.70927, -0.70493 + 0x3fe6a97f692c82ea, 0xbfe697b9e686941c, // 0.70819, -0.70602 + 0x3fe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // 0.70711, -0.70711 + 0x3fe697b9e686941c, 0xbfe6a97f692c82ea, // 0.70602, -0.70819 + 0x3fe68ed1eaa19c71, 0xbfe6b25ced2fe29c, // 0.70493, -0.70927 + 0x3fe685e6742feeef, 0xbfe6bb36f12b5e06, // 0.70385, -0.71035 + 0x3fe67cf78491af10, 0xbfe6c40d73c18275, // 0.70275, -0.71143 + 0x3fe674051d27896c, 0xbfe6cce07395679f, // 0.70166, -0.71251 + 0x3fe66b0f3f52b386, 0xbfe6d5afef4aafcc, // 0.70057, -0.71358 + 0x3fe66215ec74eb91, 0xbfe6de7be585881d, // 0.69947, -0.71466 + 0x3fe6591925f0783e, 0xbfe6e74454eaa8ae, // 0.69838, -0.71573 + 0x3fe65018ed28287f, 0xbfe6f0093c1f54de, // 0.69728, -0.7168 + 0x3fe64715437f535b, 0xbfe6f8ca99c95b75, // 0.69618, -0.71787 + 0x3fe63e0e2a59d7aa, 0xbfe701886c8f16e6, // 0.69508, -0.71894 + 0x3fe63503a31c1be8, 0xbfe70a42b3176d7a, // 0.69397, -0.72 + 0x3fe62bf5af2b0dfd, 0xbfe712f96c09d18d, // 0.69287, -0.72107 + 0x3fe622e44fec22ff, 0xbfe71bac960e41bf, // 0.69176, -0.72213 + 0x3fe619cf86c55702, 0xbfe7245c2fcd492a, // 0.69065, -0.72319 + 0x3fe610b7551d2cde, 0xbfe72d0837efff97, // 0.68954, -0.72425 + 0x3fe6079bbc5aadfa, 0xbfe735b0ad2009b2, // 0.68843, -0.7253 + 0x3fe5fe7cbde56a0f, 0xbfe73e558e079942, // 0.68732, -0.72636 + 0x3fe5f55a5b2576f8, 0xbfe746f6d9516d59, // 0.6862, -0.72741 + 0x3fe5ec3495837074, 0xbfe74f948da8d28d, // 0.68508, -0.72846 + 0x3fe5e30b6e6877f3, 0xbfe7582ea9b9a329, // 0.68397, -0.72951 + 0x3fe5d9dee73e345c, 0xbfe760c52c304764, // 0.68285, -0.73056 + 0x3fe5d0af016ed1d4, 0xbfe7695813b9b594, // 0.68172, -0.73161 + 0x3fe5c77bbe65018c, 0xbfe771e75f037261, // 0.6806, -0.73265 + 0x3fe5be451f8bf980, 0xbfe77a730cbb9100, // 0.67948, -0.7337 + 0x3fe5b50b264f7448, 0xbfe782fb1b90b35b, // 0.67835, -0.73474 + 0x3fe5abcdd41bb0d8, 0xbfe78b7f8a320a52, // 0.67722, -0.73578 + 0x3fe5a28d2a5d7250, 0xbfe79400574f55e4, // 0.67609, -0.73682 + 0x3fe599492a81ffbc, 0xbfe79c7d8198e56e, // 0.67496, -0.73785 + 0x3fe59001d5f723df, 0xbfe7a4f707bf97d2, // 0.67383, -0.73889 + 0x3fe586b72e2b2cfd, 0xbfe7ad6ce874dbb6, // 0.67269, -0.73992 + 0x3fe57d69348cec9f, 0xbfe7b5df226aafb0, // 0.67156, -0.74095 + 0x3fe57417ea8bb75c, 0xbfe7be4db453a27c, // 0.67042, -0.74198 + 0x3fe56ac35197649e, 0xbfe7c6b89ce2d333, // 0.66928, -0.74301 + 0x3fe5616b6b204e6e, 0xbfe7cf1fdacbf179, // 0.66814, -0.74403 + 0x3fe5581038975137, 0xbfe7d7836cc33db2, // 0.667, -0.74506 + 0x3fe54eb1bb6dcb8f, 0xbfe7dfe3517d8937, // 0.66586, -0.74608 + 0x3fe5454ff5159dfb, 0xbfe7e83f87b03686, // 0.66471, -0.7471 + 0x3fe53beae7012abe, 0xbfe7f0980e113978, // 0.66356, -0.74812 + 0x3fe5328292a35596, 0xbfe7f8ece3571771, // 0.66242, -0.74914 + 0x3fe52916f96f8388, 0xbfe8013e0638e795, // 0.66127, -0.75015 + 0x3fe51fa81cd99aa6, 0xbfe8098b756e52fa, // 0.66011, -0.75117 + 0x3fe51635fe5601d7, 0xbfe811d52faf94dc, // 0.65896, -0.75218 + 0x3fe50cc09f59a09b, 0xbfe81a1b33b57acc, // 0.65781, -0.75319 + 0x3fe503480159ded2, 0xbfe8225d803964e5, // 0.65665, -0.75419 + 0x3fe4f9cc25cca486, 0xbfe82a9c13f545ff, // 0.65549, -0.7552 + 0x3fe4f04d0e2859aa, 0xbfe832d6eda3a3e0, // 0.65433, -0.75621 + 0x3fe4e6cabbe3e5e9, 0xbfe83b0e0bff976e, // 0.65317, -0.75721 + 0x3fe4dd453076b064, 0xbfe843416dc4cce2, // 0.65201, -0.75821 + 0x3fe4d3bc6d589f80, 0xbfe84b7111af83f9, // 0.65085, -0.75921 + 0x3fe4ca30740218a3, 0xbfe8539cf67c9029, // 0.64968, -0.76021 + 0x3fe4c0a145ec0004, 0xbfe85bc51ae958cc, // 0.64851, -0.7612 + 0x3fe4b70ee48fb869, 0xbfe863e97db3d95a, // 0.64735, -0.7622 + 0x3fe4ad79516722f0, 0xbfe86c0a1d9aa195, // 0.64618, -0.76319 + 0x3fe4a3e08dec9ed6, 0xbfe87426f95cd5bd, // 0.645, -0.76418 + 0x3fe49a449b9b0938, 0xbfe87c400fba2ebf, // 0.64383, -0.76517 + 0x3fe490a57bedbcdf, 0xbfe884555f72fa6b, // 0.64266, -0.76615 + 0x3fe48703306091fe, 0xbfe88c66e7481ba1, // 0.64148, -0.76714 + 0x3fe47d5dba6fde01, 0xbfe89474a5fb0a84, // 0.6403, -0.76812 + 0x3fe473b51b987347, 0xbfe89c7e9a4dd4ab, // 0.63912, -0.7691 + 0x3fe46a095557a0f1, 0xbfe8a484c3031d50, // 0.63794, -0.77008 + 0x3fe4605a692b32a2, 0xbfe8ac871ede1d88, // 0.63676, -0.77106 + 0x3fe456a858917046, 0xbfe8b485aca2a468, // 0.63558, -0.77204 + 0x3fe44cf325091dd6, 0xbfe8bc806b151741, // 0.63439, -0.77301 + 0x3fe4433ad0117b1d, 0xbfe8c47758fa71cb, // 0.63321, -0.77398 + 0x3fe4397f5b2a4380, 0xbfe8cc6a75184655, // 0.63202, -0.77495 + 0x3fe42fc0c7d3adbb, 0xbfe8d459be34bdfa, // 0.63083, -0.77592 + 0x3fe425ff178e6bb1, 0xbfe8dc45331698cc, // 0.62964, -0.77689 + 0x3fe41c3a4bdbaa26, 0xbfe8e42cd2852e0a, // 0.62845, -0.77785 + 0x3fe41272663d108c, 0xbfe8ec109b486c49, // 0.62725, -0.77882 + 0x3fe408a76834c0c0, 0xbfe8f3f08c28d9ac, // 0.62606, -0.77978 + 0x3fe3fed9534556d4, 0xbfe8fbcca3ef940d, // 0.62486, -0.78074 + 0x3fe3f50828f1e8d2, 0xbfe903a4e1665133, // 0.62366, -0.78169 + 0x3fe3eb33eabe0680, 0xbfe90b7943575efe, // 0.62246, -0.78265 + 0x3fe3e15c9a2db922, 0xbfe91349c88da398, // 0.62126, -0.7836 + 0x3fe3d78238c58343, 0xbfe91b166fd49da2, // 0.62006, -0.78456 + 0x3fe3cda4c80a6076, 0xbfe922df37f8646a, // 0.61885, -0.78551 + 0x3fe3c3c44981c517, 0xbfe92aa41fc5a815, // 0.61765, -0.78646 + 0x3fe3b9e0beb19e18, 0xbfe932652609b1cf, // 0.61644, -0.7874 + 0x3fe3affa292050b9, 0xbfe93a22499263fc, // 0.61523, -0.78835 + 0x3fe3a6108a54ba58, 0xbfe941db892e3a65, // 0.61402, -0.78929 + 0x3fe39c23e3d63029, 0xbfe94990e3ac4a6c, // 0.61281, -0.79023 + 0x3fe39234372c7f04, 0xbfe9514257dc4335, // 0.6116, -0.79117 + 0x3fe3884185dfeb22, 0xbfe958efe48e6dd7, // 0.61038, -0.79211 + 0x3fe37e4bd1792fe2, 0xbfe960998893ad8c, // 0.60917, -0.79304 + 0x3fe374531b817f8d, 0xbfe9683f42bd7fe1, // 0.60795, -0.79398 + 0x3fe36a576582831b, 0xbfe96fe111ddfce0, // 0.60673, -0.79491 + 0x3fe36058b10659f3, 0xbfe9777ef4c7d742, // 0.60551, -0.79584 + 0x3fe35656ff9799ae, 0xbfe97f18ea4e5c9e, // 0.60429, -0.79676 + 0x3fe34c5252c14de1, 0xbfe986aef1457594, // 0.60307, -0.79769 + 0x3fe3424aac0ef7d6, 0xbfe98e410881a600, // 0.60184, -0.79861 + 0x3fe338400d0c8e57, 0xbfe995cf2ed80d22, // 0.60062, -0.79954 + 0x3fe32e3277467d6b, 0xbfe99d59631e65d5, // 0.59939, -0.80046 + 0x3fe32421ec49a620, 0xbfe9a4dfa42b06b2, // 0.59816, -0.80138 + 0x3fe31a0e6da35e44, 0xbfe9ac61f0d4e247, // 0.59693, -0.80229 + 0x3fe30ff7fce17035, 0xbfe9b3e047f38741, // 0.5957, -0.80321 + 0x3fe305de9b921a94, 0xbfe9bb5aa85f2098, // 0.59447, -0.80412 + 0x3fe2fbc24b441015, 0xbfe9c2d110f075c3, // 0.59323, -0.80503 + 0x3fe2f1a30d86773a, 0xbfe9ca438080eadb, // 0.592, -0.80594 + 0x3fe2e780e3e8ea16, 0xbfe9d1b1f5ea80d6, // 0.59076, -0.80685 + 0x3fe2dd5bcffb7616, 0xbfe9d91c7007d5a6, // 0.58952, -0.80775 + 0x3fe2d333d34e9bb7, 0xbfe9e082edb42472, // 0.58828, -0.80866 + 0x3fe2c908ef734e57, 0xbfe9e7e56dcb45bd, // 0.58704, -0.80956 + 0x3fe2bedb25faf3ea, 0xbfe9ef43ef29af94, // 0.5858, -0.81046 + 0x3fe2b4aa787764c4, 0xbfe9f69e70ac75bc, // 0.58455, -0.81135 + 0x3fe2aa76e87aeb58, 0xbfe9fdf4f13149de, // 0.58331, -0.81225 + 0x3fe2a040779843fb, 0xbfea05476f967bb5, // 0.58206, -0.81314 + 0x3fe2960727629ca8, 0xbfea0c95eabaf937, // 0.58081, -0.81404 + 0x3fe28bcaf96d94ba, 0xbfea13e0617e4ec7, // 0.57956, -0.81493 + 0x3fe2818bef4d3cba, 0xbfea1b26d2c0a75e, // 0.57831, -0.81581 + 0x3fe2774a0a961612, 0xbfea22693d62ccb9, // 0.57706, -0.8167 + 0x3fe26d054cdd12df, 0xbfea29a7a0462782, // 0.57581, -0.81758 + 0x3fe262bdb7b795a2, 0xbfea30e1fa4cbf81, // 0.57455, -0.81847 + 0x3fe258734cbb7110, 0xbfea38184a593bc6, // 0.5733, -0.81935 + 0x3fe24e260d7ee7c9, 0xbfea3f4a8f4ee2d2, // 0.57204, -0.82023 + 0x3fe243d5fb98ac1f, 0xbfea4678c8119ac8, // 0.57078, -0.8211 + 0x3fe23983189fdfd5, 0xbfea4da2f385e997, // 0.56952, -0.82198 + 0x3fe22f2d662c13e1, 0xbfea54c91090f524, // 0.56826, -0.82285 + 0x3fe224d4e5d5482e, 0xbfea5beb1e188375, // 0.567, -0.82372 + 0x3fe21a799933eb58, 0xbfea63091b02fae2, // 0.56573, -0.82459 + 0x3fe2101b81e0da78, 0xbfea6a230637623b, // 0.56447, -0.82546 + 0x3fe205baa17560d6, 0xbfea7138de9d60f5, // 0.5632, -0.82632 + 0x3fe1fb56f98b37b8, 0xbfea784aa31d3f55, // 0.56193, -0.82718 + 0x3fe1f0f08bbc861b, 0xbfea7f58529fe69d, // 0.56066, -0.82805 + 0x3fe1e68759a3e074, 0xbfea8661ec0ee133, // 0.55939, -0.8289 + 0x3fe1dc1b64dc4872, 0xbfea8d676e545ad2, // 0.55812, -0.82976 + 0x3fe1d1acaf012cc2, 0xbfea9468d85b20ae, // 0.55685, -0.83062 + 0x3fe1c73b39ae68c8, 0xbfea9b66290ea1a3, // 0.55557, -0.83147 + 0x3fe1bcc706804467, 0xbfeaa25f5f5aee60, // 0.55429, -0.83232 + 0x3fe1b250171373be, 0xbfeaa9547a2cb98e, // 0.55302, -0.83317 + 0x3fe1a7d66d0516e6, 0xbfeab045787157ff, // 0.55174, -0.83402 + 0x3fe19d5a09f2b9b8, 0xbfeab7325916c0d4, // 0.55046, -0.83486 + 0x3fe192daef7a5386, 0xbfeabe1b1b0b8dac, // 0.54918, -0.83571 + 0x3fe188591f3a46e5, 0xbfeac4ffbd3efac8, // 0.54789, -0.83655 + 0x3fe17dd49ad16161, 0xbfeacbe03ea0e73b, // 0.54661, -0.83739 + 0x3fe1734d63dedb49, 0xbfead2bc9e21d511, // 0.54532, -0.83822 + 0x3fe168c37c025764, 0xbfead994dab2e979, // 0.54404, -0.83906 + 0x3fe15e36e4dbe2bc, 0xbfeae068f345ecef, // 0.54275, -0.83989 + 0x3fe153a7a00bf453, 0xbfeae738e6cd4b67, // 0.54146, -0.84073 + 0x3fe14915af336ceb, 0xbfeaee04b43c1474, // 0.54017, -0.84155 + 0x3fe13e8113f396c1, 0xbfeaf4cc5a85fb73, // 0.53888, -0.84238 + 0x3fe133e9cfee254e, 0xbfeafb8fd89f57b6, // 0.53759, -0.84321 + 0x3fe1294fe4c5350a, 0xbfeb024f2d7d24a9, // 0.53629, -0.84403 + 0x3fe11eb3541b4b22, 0xbfeb090a58150200, // 0.535, -0.84485 + 0x3fe114141f935545, 0xbfeb0fc1575d33db, // 0.5337, -0.84567 + 0x3fe1097248d0a956, 0xbfeb16742a4ca2f5, // 0.5324, -0.84649 + 0x3fe0fecdd1770537, 0xbfeb1d22cfdadcc6, // 0.5311, -0.84731 + 0x3fe0f426bb2a8e7d, 0xbfeb23cd470013b4, // 0.5298, -0.84812 + 0x3fe0e97d078fd23b, 0xbfeb2a738eb51f33, // 0.5285, -0.84893 + 0x3fe0ded0b84bc4b5, 0xbfeb3115a5f37bf4, // 0.5272, -0.84974 + 0x3fe0d421cf03c12b, 0xbfeb37b38bb54c09, // 0.5259, -0.85055 + 0x3fe0c9704d5d898f, 0xbfeb3e4d3ef55712, // 0.52459, -0.85136 + 0x3fe0bebc34ff4646, 0xbfeb44e2beaf0a61, // 0.52328, -0.85216 + 0x3fe0b405878f85ec, 0xbfeb4b7409de7925, // 0.52198, -0.85296 + 0x3fe0a94c46b53d0b, 0xbfeb52011f805c92, // 0.52067, -0.85376 + 0x3fe09e907417c5e1, 0xbfeb5889fe921405, // 0.51936, -0.85456 + 0x3fe093d2115ee018, 0xbfeb5f0ea611a532, // 0.51804, -0.85535 + 0x3fe089112032b08c, 0xbfeb658f14fdbc47, // 0.51673, -0.85615 + 0x3fe07e4da23bc102, 0xbfeb6c0b4a55ac17, // 0.51542, -0.85694 + 0x3fe073879922ffed, 0xbfeb728345196e3e, // 0.5141, -0.85773 + 0x3fe068bf0691c028, 0xbfeb78f70449a34b, // 0.51279, -0.85852 + 0x3fe05df3ec31b8b6, 0xbfeb7f6686e792ea, // 0.51147, -0.8593 + 0x3fe053264bad0483, 0xbfeb85d1cbf52c02, // 0.51015, -0.86009 + 0x3fe0485626ae221a, 0xbfeb8c38d27504e9, // 0.50883, -0.86087 + 0x3fe03d837edff370, 0xbfeb929b996a5b7f, // 0.50751, -0.86165 + 0x3fe032ae55edbd95, 0xbfeb98fa1fd9155e, // 0.50619, -0.86242 + 0x3fe027d6ad83287e, 0xbfeb9f5464c5bffc, // 0.50486, -0.8632 + 0x3fe01cfc874c3eb7, 0xbfeba5aa673590d2, // 0.50354, -0.86397 + 0x3fe0121fe4f56d2c, 0xbfebabfc262e6586, // 0.50221, -0.86474 + 0x3fe00740c82b82e0, 0xbfebb249a0b6c40d, // 0.50089, -0.86551 + 0x3fdff8be6537615e, 0xbfebb892d5d5dad5, // 0.49956, -0.86628 + 0x3fdfe2f64be7120f, 0xbfebbed7c49380ea, // 0.49823, -0.86705 + 0x3fdfcd2947c1ff57, 0xbfebc5186bf8361d, // 0.4969, -0.86781 + 0x3fdfb7575c24d2de, 0xbfebcb54cb0d2327, // 0.49557, -0.86857 + 0x3fdfa1808c6cf7e0, 0xbfebd18ce0dc19d6, // 0.49423, -0.86933 + 0x3fdf8ba4dbf89aba, 0xbfebd7c0ac6f952a, // 0.4929, -0.87009 + 0x3fdf75c44e26a852, 0xbfebddf02cd2b983, // 0.49156, -0.87084 + 0x3fdf5fdee656cda3, 0xbfebe41b611154c1, // 0.49023, -0.8716 + 0x3fdf49f4a7e97729, 0xbfebea424837de6d, // 0.48889, -0.87235 + 0x3fdf3405963fd068, 0xbfebf064e15377dd, // 0.48755, -0.87309 + 0x3fdf1e11b4bbc35c, 0xbfebf6832b71ec5b, // 0.48621, -0.87384 + 0x3fdf081906bff7fd, 0xbfebfc9d25a1b147, // 0.48487, -0.87459 + 0x3fdef21b8fafd3b5, 0xbfec02b2cef1e641, // 0.48353, -0.87533 + 0x3fdedc1952ef78d5, 0xbfec08c426725549, // 0.48218, -0.87607 + 0x3fdec61253e3c61b, 0xbfec0ed12b3372e9, // 0.48084, -0.87681 + 0x3fdeb00695f25620, 0xbfec14d9dc465e58, // 0.47949, -0.87755 + 0x3fde99f61c817eda, 0xbfec1ade38bce19b, // 0.47815, -0.87828 + 0x3fde83e0eaf85113, 0xbfec20de3fa971b0, // 0.4768, -0.87901 + 0x3fde6dc704be97e2, 0xbfec26d9f01f2eaf, // 0.47545, -0.87974 + 0x3fde57a86d3cd824, 0xbfec2cd14931e3f1, // 0.4741, -0.88047 + 0x3fde418527dc4ffa, 0xbfec32c449f60831, // 0.47275, -0.8812 + 0x3fde2b5d3806f63b, 0xbfec38b2f180bdb1, // 0.4714, -0.88192 + 0x3fde1530a12779f4, 0xbfec3e9d3ee7d262, // 0.47004, -0.88264 + 0x3fddfeff66a941de, 0xbfec44833141c004, // 0.46869, -0.88336 + 0x3fdde8c98bf86bd6, 0xbfec4a64c7a5ac4c, // 0.46733, -0.88408 + 0x3fddd28f1481cc58, 0xbfec5042012b6907, // 0.46598, -0.8848 + 0x3fddbc5003b2edf8, 0xbfec561adceb743e, // 0.46462, -0.88551 + 0x3fdda60c5cfa10d8, 0xbfec5bef59fef85a, // 0.46326, -0.88622 + 0x3fdd8fc423c62a25, 0xbfec61bf777fcc48, // 0.4619, -0.88693 + 0x3fdd79775b86e389, 0xbfec678b3488739b, // 0.46054, -0.88764 + 0x3fdd632607ac9aa9, 0xbfec6d5290341eb2, // 0.45918, -0.88835 + 0x3fdd4cd02ba8609c, 0xbfec7315899eaad7, // 0.45781, -0.88905 + 0x3fdd3675caebf962, 0xbfec78d41fe4a267, // 0.45645, -0.88975 + 0x3fdd2016e8e9db5b, 0xbfec7e8e52233cf3, // 0.45508, -0.89045 + 0x3fdd09b389152ec1, 0xbfec84441f785f61, // 0.45372, -0.89115 + 0x3fdcf34baee1cd21, 0xbfec89f587029c13, // 0.45235, -0.89184 + 0x3fdcdcdf5dc440ce, 0xbfec8fa287e13305, // 0.45098, -0.89253 + 0x3fdcc66e9931c45d, 0xbfec954b213411f5, // 0.44961, -0.89322 + 0x3fdcaff964a0421d, 0xbfec9aef521bd480, // 0.44824, -0.89391 + 0x3fdc997fc3865388, 0xbfeca08f19b9c449, // 0.44687, -0.8946 + 0x3fdc8301b95b40c2, 0xbfeca62a772fd919, // 0.4455, -0.89528 + 0x3fdc6c7f4997000a, 0xbfecabc169a0b901, // 0.44412, -0.89597 + 0x3fdc55f877b23537, 0xbfecb153f02fb87d, // 0.44275, -0.89665 + 0x3fdc3f6d47263129, 0xbfecb6e20a00da99, // 0.44137, -0.89732 + 0x3fdc28ddbb6cf145, 0xbfecbc6bb638d10b, // 0.43999, -0.898 + 0x3fdc1249d8011ee7, 0xbfecc1f0f3fcfc5c, // 0.43862, -0.89867 + 0x3fdbfbb1a05e0edc, 0xbfecc771c2736c09, // 0.43724, -0.89935 + 0x3fdbe51517ffc0d9, 0xbfecccee20c2de9f, // 0.43586, -0.90002 + 0x3fdbce744262deee, 0xbfecd2660e12c1e6, // 0.43448, -0.90068 + 0x3fdbb7cf2304bd01, 0xbfecd7d9898b32f6, // 0.43309, -0.90135 + 0x3fdba125bd63583e, 0xbfecdd489254fe65, // 0.43171, -0.90201 + 0x3fdb8a7814fd5693, 0xbfece2b32799a060, // 0.43033, -0.90267 + 0x3fdb73c62d520624, 0xbfece819488344ce, // 0.42894, -0.90333 + 0x3fdb5d1009e15cc0, 0xbfeced7af43cc773, // 0.42756, -0.90399 + 0x3fdb4655ae2bf757, 0xbfecf2d829f1b40e, // 0.42617, -0.90464 + 0x3fdb2f971db31972, 0xbfecf830e8ce467b, // 0.42478, -0.9053 + 0x3fdb18d45bf8aca6, 0xbfecfd852fff6ad4, // 0.42339, -0.90595 + 0x3fdb020d6c7f4009, 0xbfed02d4feb2bd92, // 0.422, -0.9066 + 0x3fdaeb4252ca07ab, 0xbfed082054168bac, // 0.42061, -0.90724 + 0x3fdad473125cdc08, 0xbfed0d672f59d2b9, // 0.41922, -0.90789 + 0x3fdabd9faebc3980, 0xbfed12a98fac410c, // 0.41782, -0.90853 + 0x3fdaa6c82b6d3fc9, 0xbfed17e7743e35dc, // 0.41643, -0.90917 + 0x3fda8fec8bf5b166, 0xbfed1d20dc40c15c, // 0.41503, -0.90981 + 0x3fda790cd3dbf31a, 0xbfed2255c6e5a4e1, // 0.41364, -0.91044 + 0x3fda622906a70b63, 0xbfed2786335f52fc, // 0.41224, -0.91107 + 0x3fda4b4127dea1e4, 0xbfed2cb220e0ef9f, // 0.41084, -0.91171 + 0x3fda34553b0afee5, 0xbfed31d98e9e503a, // 0.40944, -0.91234 + 0x3fda1d6543b50ac0, 0xbfed36fc7bcbfbdc, // 0.40804, -0.91296 + 0x3fda067145664d57, 0xbfed3c1ae79f2b4e, // 0.40664, -0.91359 + 0x3fd9ef7943a8ed8a, 0xbfed4134d14dc93a, // 0.40524, -0.91421 + 0x3fd9d87d4207b0ab, 0xbfed464a380e7242, // 0.40384, -0.91483 + 0x3fd9c17d440df9f2, 0xbfed4b5b1b187524, // 0.40243, -0.91545 + 0x3fd9aa794d47c9ee, 0xbfed506779a3d2d9, // 0.40103, -0.91606 + 0x3fd993716141bdfe, 0xbfed556f52e93eb1, // 0.39962, -0.91668 + 0x3fd97c6583890fc2, 0xbfed5a72a6221e73, // 0.39822, -0.91729 + 0x3fd96555b7ab948f, 0xbfed5f7172888a7f, // 0.39681, -0.9179 + 0x3fd94e420137bce3, 0xbfed646bb7574de5, // 0.3954, -0.91851 + 0x3fd9372a63bc93d7, 0xbfed696173c9e68b, // 0.39399, -0.91911 + 0x3fd9200ee2c9be97, 0xbfed6e52a71c8547, // 0.39258, -0.91972 + 0x3fd908ef81ef7bd1, 0xbfed733f508c0dff, // 0.39117, -0.92032 + 0x3fd8f1cc44bea329, 0xbfed78276f5617c6, // 0.38976, -0.92092 + 0x3fd8daa52ec8a4af, 0xbfed7d0b02b8ecf9, // 0.38835, -0.92151 + 0x3fd8c37a439f884f, 0xbfed81ea09f38b63, // 0.38693, -0.92211 + 0x3fd8ac4b86d5ed44, 0xbfed86c48445a450, // 0.38552, -0.9227 + 0x3fd89518fbff098e, 0xbfed8b9a70ef9cb4, // 0.3841, -0.92329 + 0x3fd87de2a6aea963, 0xbfed906bcf328d46, // 0.38268, -0.92388 + 0x3fd866a88a792ea0, 0xbfed95389e50429b, // 0.38127, -0.92447 + 0x3fd84f6aaaf3903f, 0xbfed9a00dd8b3d46, // 0.37985, -0.92505 + 0x3fd838290bb359c8, 0xbfed9ec48c26b1f3, // 0.37843, -0.92563 + 0x3fd820e3b04eaac4, 0xbfeda383a9668988, // 0.37701, -0.92621 + 0x3fd8099a9c5c362d, 0xbfeda83e348f613b, // 0.37559, -0.92679 + 0x3fd7f24dd37341e3, 0xbfedacf42ce68ab9, // 0.37416, -0.92736 + 0x3fd7dafd592ba621, 0xbfedb1a591b20c38, // 0.37274, -0.92794 + 0x3fd7c3a9311dcce7, 0xbfedb6526238a09b, // 0.37132, -0.92851 + 0x3fd7ac515ee2b172, 0xbfedbafa9dc1b78d, // 0.36989, -0.92907 + 0x3fd794f5e613dfae, 0xbfedbf9e4395759a, // 0.36847, -0.92964 + 0x3fd77d96ca4b73a6, 0xbfedc43d52fcb453, // 0.36704, -0.93021 + 0x3fd766340f2418f6, 0xbfedc8d7cb410260, // 0.36561, -0.93077 + 0x3fd74ecdb8390a3e, 0xbfedcd6dabaca3a5, // 0.36418, -0.93133 + 0x3fd73763c9261092, 0xbfedd1fef38a915a, // 0.36276, -0.93188 + 0x3fd71ff6458782ec, 0xbfedd68ba2267a25, // 0.36133, -0.93244 + 0x3fd7088530fa459e, 0xbfeddb13b6ccc23d, // 0.3599, -0.93299 + 0x3fd6f1108f1bc9c5, 0xbfeddf9730ca837b, // 0.35846, -0.93354 + 0x3fd6d998638a0cb5, 0xbfede4160f6d8d81, // 0.35703, -0.93409 + 0x3fd6c21cb1e39771, 0xbfede890520465ce, // 0.3556, -0.93464 + 0x3fd6aa9d7dc77e16, 0xbfeded05f7de47da, // 0.35416, -0.93518 + 0x3fd6931acad55f51, 0xbfedf177004b2534, // 0.35273, -0.93573 + 0x3fd67b949cad63ca, 0xbfedf5e36a9ba59c, // 0.35129, -0.93627 + 0x3fd6640af6f03d9e, 0xbfedfa4b3621271d, // 0.34986, -0.9368 + 0x3fd64c7ddd3f27c6, 0xbfedfeae622dbe2b, // 0.34842, -0.93734 + 0x3fd634ed533be58e, 0xbfee030cee1435b8, // 0.34698, -0.93787 + 0x3fd61d595c88c203, 0xbfee0766d9280f54, // 0.34554, -0.9384 + 0x3fd605c1fcc88f63, 0xbfee0bbc22bd8349, // 0.3441, -0.93893 + 0x3fd5ee27379ea693, 0xbfee100cca2980ac, // 0.34266, -0.93946 + 0x3fd5d68910aee686, 0xbfee1458cec1ad83, // 0.34122, -0.93998 + 0x3fd5bee78b9db3b6, 0xbfee18a02fdc66d9, // 0.33978, -0.94051 + 0x3fd5a742ac0ff78d, 0xbfee1ce2ecd0c0d8, // 0.33833, -0.94103 + 0x3fd58f9a75ab1fdd, 0xbfee212104f686e5, // 0.33689, -0.94154 + 0x3fd577eeec151e47, 0xbfee255a77a63bb8, // 0.33545, -0.94206 + 0x3fd5604012f467b4, 0xbfee298f4439197a, // 0.334, -0.94257 + 0x3fd5488dedeff3be, 0xbfee2dbf6a0911d9, // 0.33255, -0.94308 + 0x3fd530d880af3c24, 0xbfee31eae870ce25, // 0.33111, -0.94359 + 0x3fd5191fceda3c35, 0xbfee3611becbaf69, // 0.32966, -0.9441 + 0x3fd50163dc197047, 0xbfee3a33ec75ce85, // 0.32821, -0.9446 + 0x3fd4e9a4ac15d520, 0xbfee3e5170cbfc46, // 0.32676, -0.94511 + 0x3fd4d1e24278e76a, 0xbfee426a4b2bc17e, // 0.32531, -0.94561 + 0x3fd4ba1ca2eca31c, 0xbfee467e7af35f23, // 0.32386, -0.94611 + 0x3fd4a253d11b82f3, 0xbfee4a8dff81ce5e, // 0.32241, -0.9466 + 0x3fd48a87d0b07fd7, 0xbfee4e98d836c0af, // 0.32096, -0.94709 + 0x3fd472b8a5571054, 0xbfee529f04729ffc, // 0.3195, -0.94759 + 0x3fd45ae652bb2800, 0xbfee56a083968eb1, // 0.31805, -0.94807 + 0x3fd44310dc8936f0, 0xbfee5a9d550467d3, // 0.31659, -0.94856 + 0x3fd42b38466e2928, 0xbfee5e95781ebf1c, // 0.31514, -0.94905 + 0x3fd4135c94176602, 0xbfee6288ec48e112, // 0.31368, -0.94953 + 0x3fd3fb7dc932cfa4, 0xbfee6677b0e6d31e, // 0.31222, -0.95001 + 0x3fd3e39be96ec271, 0xbfee6a61c55d53a7, // 0.31077, -0.95049 + 0x3fd3cbb6f87a146e, 0xbfee6e472911da27, // 0.30931, -0.95096 + 0x3fd3b3cefa0414b7, 0xbfee7227db6a9744, // 0.30785, -0.95144 + 0x3fd39be3f1bc8aef, 0xbfee7603dbce74e9, // 0.30639, -0.95191 + 0x3fd383f5e353b6aa, 0xbfee79db29a5165a, // 0.30493, -0.95238 + 0x3fd36c04d27a4edf, 0xbfee7dadc456d850, // 0.30347, -0.95284 + 0x3fd35410c2e18152, 0xbfee817bab4cd10d, // 0.30201, -0.95331 + 0x3fd33c19b83af207, 0xbfee8544ddf0d075, // 0.30054, -0.95377 + 0x3fd3241fb638baaf, 0xbfee89095bad6025, // 0.29908, -0.95423 + 0x3fd30c22c08d6a13, 0xbfee8cc923edc388, // 0.29762, -0.95469 + 0x3fd2f422daec0386, 0xbfee9084361df7f3, // 0.29615, -0.95514 + 0x3fd2dc200907fe51, 0xbfee943a91aab4b4, // 0.29469, -0.95559 + 0x3fd2c41a4e954520, 0xbfee97ec36016b30, // 0.29322, -0.95605 + 0x3fd2ac11af483572, 0xbfee9b99229046f8, // 0.29175, -0.95649 + 0x3fd294062ed59f05, 0xbfee9f4156c62dda, // 0.29028, -0.95694 + 0x3fd27bf7d0f2c346, 0xbfeea2e4d212c000, // 0.28882, -0.95738 + 0x3fd263e6995554ba, 0xbfeea68393e65800, // 0.28735, -0.95783 + 0x3fd24bd28bb37672, 0xbfeeaa1d9bb20af3, // 0.28588, -0.95827 + 0x3fd233bbabc3bb72, 0xbfeeadb2e8e7a88e, // 0.28441, -0.9587 + 0x3fd21ba1fd3d2623, 0xbfeeb1437af9bb34, // 0.28294, -0.95914 + 0x3fd2038583d727bd, 0xbfeeb4cf515b8811, // 0.28146, -0.95957 + 0x3fd1eb6643499fbb, 0xbfeeb8566b810f2a, // 0.27999, -0.96 + 0x3fd1d3443f4cdb3d, 0xbfeebbd8c8df0b74, // 0.27852, -0.96043 + 0x3fd1bb1f7b999480, 0xbfeebf5668eaf2ef, // 0.27705, -0.96086 + 0x3fd1a2f7fbe8f243, 0xbfeec2cf4b1af6b2, // 0.27557, -0.96128 + 0x3fd18acdc3f4873a, 0xbfeec6436ee60309, // 0.2741, -0.9617 + 0x3fd172a0d7765177, 0xbfeec9b2d3c3bf84, // 0.27262, -0.96212 + 0x3fd15a713a28b9d9, 0xbfeecd1d792c8f10, // 0.27115, -0.96254 + 0x3fd1423eefc69378, 0xbfeed0835e999009, // 0.26967, -0.96295 + 0x3fd12a09fc0b1b12, 0xbfeed3e483849c51, // 0.26819, -0.96337 + 0x3fd111d262b1f677, 0xbfeed740e7684963, // 0.26671, -0.96378 + 0x3fd0f998277733f7, 0xbfeeda9889bfe86a, // 0.26523, -0.96418 + 0x3fd0e15b4e1749cd, 0xbfeeddeb6a078651, // 0.26375, -0.96459 + 0x3fd0c91bda4f158d, 0xbfeee13987bbebdc, // 0.26227, -0.96499 + 0x3fd0b0d9cfdbdb90, 0xbfeee482e25a9dbc, // 0.26079, -0.96539 + 0x3fd09895327b465e, 0xbfeee7c77961dc9e, // 0.25931, -0.96579 + 0x3fd0804e05eb661e, 0xbfeeeb074c50a544, // 0.25783, -0.96619 + 0x3fd068044deab002, 0xbfeeee425aa6b09a, // 0.25635, -0.96658 + 0x3fd04fb80e37fdae, 0xbfeef178a3e473c2, // 0.25487, -0.96698 + 0x3fd037694a928cac, 0xbfeef4aa278b2032, // 0.25338, -0.96737 + 0x3fd01f1806b9fdd2, 0xbfeef7d6e51ca3c0, // 0.2519, -0.96775 + 0x3fd006c4466e54af, 0xbfeefafedc1ba8b7, // 0.25041, -0.96814 + 0x3fcfdcdc1adfedf8, 0xbfeefe220c0b95ec, // 0.24893, -0.96852 + 0x3fcfac2abeff57ff, 0xbfef014074708ed3, // 0.24744, -0.9689 + 0x3fcf7b7480bd3801, 0xbfef045a14cf738c, // 0.24596, -0.96928 + 0x3fcf4ab9679c9f5c, 0xbfef076eecade0fa, // 0.24447, -0.96966 + 0x3fcf19f97b215f1a, 0xbfef0a7efb9230d7, // 0.24298, -0.97003 + 0x3fcee934c2d006c7, 0xbfef0d8a410379c5, // 0.24149, -0.9704 + 0x3fceb86b462de348, 0xbfef1090bc898f5f, // 0.24, -0.97077 + 0x3fce879d0cc0fdaf, 0xbfef13926dad024e, // 0.23851, -0.97114 + 0x3fce56ca1e101a1b, 0xbfef168f53f7205d, // 0.23702, -0.9715 + 0x3fce25f281a2b684, 0xbfef19876ef1f486, // 0.23553, -0.97187 + 0x3fcdf5163f01099a, 0xbfef1c7abe284708, // 0.23404, -0.97223 + 0x3fcdc4355db40195, 0xbfef1f6941259d7a, // 0.23255, -0.97258 + 0x3fcd934fe5454311, 0xbfef2252f7763ada, // 0.23106, -0.97294 + 0x3fcd6265dd3f27e3, 0xbfef2537e0a71f9f, // 0.22957, -0.97329 + 0x3fcd31774d2cbdee, 0xbfef2817fc4609ce, // 0.22807, -0.97364 + 0x3fcd00843c99c5f9, 0xbfef2af349e17507, // 0.22658, -0.97399 + 0x3fcccf8cb312b286, 0xbfef2dc9c9089a9d, // 0.22508, -0.97434 + 0x3fcc9e90b824a6a9, 0xbfef309b794b719f, // 0.22359, -0.97468 + 0x3fcc6d90535d74dc, 0xbfef33685a3aaef0, // 0.22209, -0.97503 + 0x3fcc3c8b8c4b9dd7, 0xbfef36306b67c556, // 0.2206, -0.97536 + 0x3fcc0b826a7e4f63, 0xbfef38f3ac64e589, // 0.2191, -0.9757 + 0x3fcbda74f5856330, 0xbfef3bb21cc4fe47, // 0.2176, -0.97604 + 0x3fcba96334f15dad, 0xbfef3e6bbc1bbc65, // 0.21611, -0.97637 + 0x3fcb784d30536cda, 0xbfef412089fd8adc, // 0.21461, -0.9767 + 0x3fcb4732ef3d6722, 0xbfef43d085ff92dd, // 0.21311, -0.97703 + 0x3fcb16147941ca2a, 0xbfef467bafb7bbe0, // 0.21161, -0.97735 + 0x3fcae4f1d5f3b9ab, 0xbfef492206bcabb4, // 0.21011, -0.97768 + 0x3fcab3cb0ce6fe44, 0xbfef4bc38aa5c694, // 0.20861, -0.978 + 0x3fca82a025b00451, 0xbfef4e603b0b2f2d, // 0.20711, -0.97832 + 0x3fca517127e3dabc, 0xbfef50f81785c6b9, // 0.20561, -0.97863 + 0x3fca203e1b1831da, 0xbfef538b1faf2d07, // 0.20411, -0.97895 + 0x3fc9ef0706e35a35, 0xbfef56195321c090, // 0.20261, -0.97926 + 0x3fc9bdcbf2dc4366, 0xbfef58a2b1789e84, // 0.2011, -0.97957 + 0x3fc98c8ce69a7aec, 0xbfef5b273a4fa2d9, // 0.1996, -0.97988 + 0x3fc95b49e9b62af9, 0xbfef5da6ed43685d, // 0.1981, -0.98018 + 0x3fc92a0303c8194f, 0xbfef6021c9f148c2, // 0.19659, -0.98048 + 0x3fc8f8b83c69a60a, 0xbfef6297cff75cb0, // 0.19509, -0.98079 + 0x3fc8c7699b34ca7e, 0xbfef6508fef47bd5, // 0.19359, -0.98108 + 0x3fc8961727c41804, 0xbfef677556883cee, // 0.19208, -0.98138 + 0x3fc864c0e9b2b6cf, 0xbfef69dcd652f5de, // 0.19057, -0.98167 + 0x3fc83366e89c64c5, 0xbfef6c3f7df5bbb7, // 0.18907, -0.98196 + 0x3fc802092c1d744b, 0xbfef6e9d4d1262ca, // 0.18756, -0.98225 + 0x3fc7d0a7bbd2cb1b, 0xbfef70f6434b7eb7, // 0.18606, -0.98254 + 0x3fc79f429f59e11d, 0xbfef734a60446279, // 0.18455, -0.98282 + 0x3fc76dd9de50bf31, 0xbfef7599a3a12077, // 0.18304, -0.98311 + 0x3fc73c6d8055fe0a, 0xbfef77e40d068a90, // 0.18153, -0.98339 + 0x3fc70afd8d08c4ff, 0xbfef7a299c1a322a, // 0.18002, -0.98366 + 0x3fc6d98a0c08c8da, 0xbfef7c6a50826840, // 0.17851, -0.98394 + 0x3fc6a81304f64ab2, 0xbfef7ea629e63d6e, // 0.177, -0.98421 + 0x3fc676987f7216b8, 0xbfef80dd27ed8204, // 0.17549, -0.98448 + 0x3fc6451a831d830d, 0xbfef830f4a40c60c, // 0.17398, -0.98475 + 0x3fc61399179a6e94, 0xbfef853c9089595e, // 0.17247, -0.98501 + 0x3fc5e214448b3fc6, 0xbfef8764fa714ba9, // 0.17096, -0.98528 + 0x3fc5b08c1192e381, 0xbfef898887a36c84, // 0.16945, -0.98554 + 0x3fc57f008654cbde, 0xbfef8ba737cb4b78, // 0.16794, -0.9858 + 0x3fc54d71aa74ef02, 0xbfef8dc10a95380d, // 0.16643, -0.98605 + 0x3fc51bdf8597c5f2, 0xbfef8fd5ffae41db, // 0.16491, -0.98631 + 0x3fc4ea4a1f624b61, 0xbfef91e616c43891, // 0.1634, -0.98656 + 0x3fc4b8b17f79fa88, 0xbfef93f14f85ac08, // 0.16189, -0.98681 + 0x3fc48715ad84cdf5, 0xbfef95f7a9a1ec47, // 0.16037, -0.98706 + 0x3fc45576b1293e5a, 0xbfef97f924c9099b, // 0.15886, -0.9873 + 0x3fc423d4920e4166, 0xbfef99f5c0abd496, // 0.15734, -0.98754 + 0x3fc3f22f57db4893, 0xbfef9bed7cfbde29, // 0.15583, -0.98778 + 0x3fc3c0870a383ff6, 0xbfef9de0596b77a3, // 0.15431, -0.98802 + 0x3fc38edbb0cd8d14, 0xbfef9fce55adb2c8, // 0.1528, -0.98826 + 0x3fc35d2d53440db2, 0xbfefa1b7717661d5, // 0.15128, -0.98849 + 0x3fc32b7bf94516a7, 0xbfefa39bac7a1791, // 0.14976, -0.98872 + 0x3fc2f9c7aa7a72af, 0xbfefa57b066e2754, // 0.14825, -0.98895 + 0x3fc2c8106e8e613a, 0xbfefa7557f08a517, // 0.14673, -0.98918 + 0x3fc296564d2b953e, 0xbfefa92b1600657c, // 0.14521, -0.9894 + 0x3fc264994dfd340a, 0xbfefaafbcb0cfddc, // 0.1437, -0.98962 + 0x3fc232d978aed413, 0xbfefacc79de6c44f, // 0.14218, -0.98984 + 0x3fc20116d4ec7bce, 0xbfefae8e8e46cfbb, // 0.14066, -0.99006 + 0x3fc1cf516a62a077, 0xbfefb0509be6f7db, // 0.13914, -0.99027 + 0x3fc19d8940be24e7, 0xbfefb20dc681d54d, // 0.13762, -0.99049 + 0x3fc16bbe5fac5865, 0xbfefb3c60dd2c199, // 0.1361, -0.9907 + 0x3fc139f0cedaf576, 0xbfefb5797195d741, // 0.13458, -0.9909 + 0x3fc1082095f820b0, 0xbfefb727f187f1c7, // 0.13306, -0.99111 + 0x3fc0d64dbcb26786, 0xbfefb8d18d66adb7, // 0.13154, -0.99131 + 0x3fc0a4784ab8bf1d, 0xbfefba7644f068b5, // 0.13002, -0.99151 + 0x3fc072a047ba831d, 0xbfefbc1617e44186, // 0.1285, -0.99171 + 0x3fc040c5bb67747e, 0xbfefbdb106021816, // 0.12698, -0.99191 + 0x3fc00ee8ad6fb85b, 0xbfefbf470f0a8d88, // 0.12545, -0.9921 + 0x3fbfba124b07ad85, 0xbfefc0d832bf043a, // 0.12393, -0.99229 + 0x3fbf564e56a9730e, 0xbfefc26470e19fd3, // 0.12241, -0.99248 + 0x3fbef2858d27561b, 0xbfefc3ebc935454c, // 0.12089, -0.99267 + 0x3fbe8eb7fde4aa3e, 0xbfefc56e3b7d9af6, // 0.11937, -0.99285 + 0x3fbe2ae5b8457f77, 0xbfefc6ebc77f0887, // 0.11784, -0.99303 + 0x3fbdc70ecbae9fc8, 0xbfefc8646cfeb721, // 0.11632, -0.99321 + 0x3fbd633347858ce4, 0xbfefc9d82bc2915e, // 0.11479, -0.99339 + 0x3fbcff533b307dc1, 0xbfefcb4703914354, // 0.11327, -0.99356 + 0x3fbc9b6eb6165c42, 0xbfefccb0f4323aa3, // 0.11175, -0.99374 + 0x3fbc3785c79ec2d5, 0xbfefce15fd6da67b, // 0.11022, -0.99391 + 0x3fbbd3987f31fa0e, 0xbfefcf761f0c77a3, // 0.1087, -0.99407 + 0x3fbb6fa6ec38f64c, 0xbfefd0d158d86087, // 0.10717, -0.99424 + 0x3fbb0bb11e1d5559, 0xbfefd227aa9bd53b, // 0.10565, -0.9944 + 0x3fbaa7b724495c04, 0xbfefd37914220b84, // 0.10412, -0.99456 + 0x3fba43b90e27f3c4, 0xbfefd4c59536fae4, // 0.1026, -0.99472 + 0x3fb9dfb6eb24a85c, 0xbfefd60d2da75c9e, // 0.10107, -0.99488 + 0x3fb97bb0caaba56f, 0xbfefd74fdd40abbf, // 0.099544, -0.99503 + 0x3fb917a6bc29b42c, 0xbfefd88da3d12526, // 0.098017, -0.99518 + 0x3fb8b398cf0c38e0, 0xbfefd9c68127c78c, // 0.09649, -0.99533 + 0x3fb84f8712c130a0, 0xbfefdafa7514538c, // 0.094963, -0.99548 + 0x3fb7eb7196b72ee4, 0xbfefdc297f674ba9, // 0.093436, -0.99563 + 0x3fb787586a5d5b21, 0xbfefdd539ff1f456, // 0.091909, -0.99577 + 0x3fb7233b9d236e71, 0xbfefde78d68653fd, // 0.090381, -0.99591 + 0x3fb6bf1b3e79b129, 0xbfefdf9922f73307, // 0.088854, -0.99604 + 0x3fb65af75dd0f87b, 0xbfefe0b485181be3, // 0.087326, -0.99618 + 0x3fb5f6d00a9aa419, 0xbfefe1cafcbd5b09, // 0.085797, -0.99631 + 0x3fb592a554489bc8, 0xbfefe2dc89bbff08, // 0.084269, -0.99644 + 0x3fb52e774a4d4d0a, 0xbfefe3e92be9d886, // 0.08274, -0.99657 + 0x3fb4ca45fc1ba8b6, 0xbfefe4f0e31d7a4a, // 0.081211, -0.9967 + 0x3fb4661179272096, 0xbfefe5f3af2e3940, // 0.079682, -0.99682 + 0x3fb401d9d0e3a507, 0xbfefe6f18ff42c84, // 0.078153, -0.99694 + 0x3fb39d9f12c5a299, 0xbfefe7ea85482d60, // 0.076624, -0.99706 + 0x3fb339614e41ffa5, 0xbfefe8de8f03d75c, // 0.075094, -0.99718 + 0x3fb2d52092ce19f6, 0xbfefe9cdad01883a, // 0.073565, -0.99729 + 0x3fb270dcefdfc45b, 0xbfefeab7df1c6005, // 0.072035, -0.9974 + 0x3fb20c9674ed444c, 0xbfefeb9d2530410f, // 0.070505, -0.99751 + 0x3fb1a84d316d4f8a, 0xbfefec7d7f19cffc, // 0.068974, -0.99762 + 0x3fb1440134d709b2, 0xbfefed58ecb673c4, // 0.067444, -0.99772 + 0x3fb0dfb28ea201e6, 0xbfefee2f6de455ba, // 0.065913, -0.99783 + 0x3fb07b614e463064, 0xbfefef0102826191, // 0.064383, -0.99793 + 0x3fb0170d833bf421, 0xbfefefcdaa704562, // 0.062852, -0.99802 + 0x3faf656e79f820e0, 0xbfeff095658e71ad, // 0.061321, -0.99812 + 0x3fae9cbd15ff5527, 0xbfeff15833be1965, // 0.05979, -0.99821 + 0x3fadd406f9808ec8, 0xbfeff21614e131ed, // 0.058258, -0.9983 + 0x3fad0b4c436f91d0, 0xbfeff2cf08da7321, // 0.056727, -0.99839 + 0x3fac428d12c0d7e3, 0xbfeff3830f8d575c, // 0.055195, -0.99848 + 0x3fab79c986698b78, 0xbfeff43228de1b77, // 0.053664, -0.99856 + 0x3faab101bd5f8317, 0xbfeff4dc54b1bed3, // 0.052132, -0.99864 + 0x3fa9e835d6993c87, 0xbfeff58192ee0358, // 0.0506, -0.99872 + 0x3fa91f65f10dd814, 0xbfeff621e3796d7e, // 0.049068, -0.9988 + 0x3fa856922bb513c1, 0xbfeff6bd463b444d, // 0.047535, -0.99887 + 0x3fa78dbaa5874685, 0xbfeff753bb1b9164, // 0.046003, -0.99894 + 0x3fa6c4df7d7d5b84, 0xbfeff7e5420320f9, // 0.044471, -0.99901 + 0x3fa5fc00d290cd43, 0xbfeff871dadb81df, // 0.042938, -0.99908 + 0x3fa5331ec3bba0eb, 0xbfeff8f9858f058b, // 0.041406, -0.99914 + 0x3fa46a396ff86179, 0xbfeff97c4208c014, // 0.039873, -0.9992 + 0x3fa3a150f6421afc, 0xbfeff9fa10348837, // 0.03834, -0.99926 + 0x3fa2d865759455cd, 0xbfeffa72effef75d, // 0.036807, -0.99932 + 0x3fa20f770ceb11c6, 0xbfeffae6e1556998, // 0.035274, -0.99938 + 0x3fa14685db42c17e, 0xbfeffb55e425fdae, // 0.033741, -0.99943 + 0x3fa07d91ff984580, 0xbfeffbbff85f9515, // 0.032208, -0.99948 + 0x3f9f693731d1cf01, 0xbfeffc251df1d3f8, // 0.030675, -0.99953 + 0x3f9dd7458c64ab39, 0xbfeffc8554cd213a, // 0.029142, -0.99958 + 0x3f9c454f4ce53b1c, 0xbfeffce09ce2a679, // 0.027608, -0.99962 + 0x3f9ab354b1504fca, 0xbfeffd36f624500c, // 0.026075, -0.99966 + 0x3f992155f7a3667e, 0xbfeffd886084cd0d, // 0.024541, -0.9997 + 0x3f978f535ddc9f03, 0xbfeffdd4dbf78f52, // 0.023008, -0.99974 + 0x3f95fd4d21fab226, 0xbfeffe1c6870cb77, // 0.021474, -0.99977 + 0x3f946b4381fce81c, 0xbfeffe5f05e578db, // 0.01994, -0.9998 + 0x3f92d936bbe30efd, 0xbfeffe9cb44b51a1, // 0.018407, -0.99983 + 0x3f9147270dad7132, 0xbfeffed57398d2b7, // 0.016873, -0.99986 + 0x3f8f6a296ab997ca, 0xbfefff0943c53bd1, // 0.015339, -0.99988 + 0x3f8c45ffe1e48ad9, 0xbfefff3824c88f6f, // 0.013805, -0.9999 + 0x3f8921d1fcdec784, 0xbfefff62169b92db, // 0.012272, -0.99992 + 0x3f85fda037ac05e0, 0xbfefff871937ce2f, // 0.010738, -0.99994 + 0x3f82d96b0e509703, 0xbfefffa72c978c4f, //0.0092038, -0.99996 + 0x3f7f6a65f9a2a3c5, 0xbfefffc250b5daef, //0.0076698, -0.99997 + 0x3f7921f0fe670071, 0xbfefffd8858e8a92, //0.0061359, -0.99998 + 0x3f72d97822f996bc, 0xbfefffe9cb1e2e8d, //0.0046019, -0.99999 + 0x3f6921f8becca4ba, 0xbfeffff621621d02, // 0.003068, -1 + 0x3f5921faaee6472d, 0xbfeffffd88586ee6, // 0.001534, -1 +}; + +#endif + + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F32_32) +/** + @par + Example code for Floating-point RFFT Twiddle factors Generation: + @par + 
TW = exp(pi/2*i-2*pi*i*[0:L/2-1]/L).'
+ @par + Real and Imag values are in interleaved fashion +*/ +const float32_t twiddleCoef_rfft_32[32] = { + 0.000000000f, 1.000000000f, + 0.195090322f, 0.980785280f, + 0.382683432f, 0.923879533f, + 0.555570233f, 0.831469612f, + 0.707106781f, 0.707106781f, + 0.831469612f, 0.555570233f, + 0.923879533f, 0.382683432f, + 0.980785280f, 0.195090322f, + 1.000000000f, 0.000000000f, + 0.980785280f, -0.195090322f, + 0.923879533f, -0.382683432f, + 0.831469612f, -0.555570233f, + 0.707106781f, -0.707106781f, + 0.555570233f, -0.831469612f, + 0.382683432f, -0.923879533f, + 0.195090322f, -0.980785280f +}; +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F32_64) +const float32_t twiddleCoef_rfft_64[64] = { + 0.000000000000000f, 1.000000000000000f, + 0.098017140329561f, 0.995184726672197f, + 0.195090322016128f, 0.980785280403230f, + 0.290284677254462f, 0.956940335732209f, + 0.382683432365090f, 0.923879532511287f, + 0.471396736825998f, 0.881921264348355f, + 0.555570233019602f, 0.831469612302545f, + 0.634393284163645f, 0.773010453362737f, + 0.707106781186547f, 0.707106781186548f, + 0.773010453362737f, 0.634393284163645f, + 0.831469612302545f, 0.555570233019602f, + 0.881921264348355f, 0.471396736825998f, + 0.923879532511287f, 0.382683432365090f, + 0.956940335732209f, 0.290284677254462f, + 0.980785280403230f, 0.195090322016128f, + 0.995184726672197f, 0.098017140329561f, + 1.000000000000000f, 0.000000000000000f, + 0.995184726672197f, -0.098017140329561f, + 0.980785280403230f, -0.195090322016128f, + 0.956940335732209f, -0.290284677254462f, + 0.923879532511287f, -0.382683432365090f, + 0.881921264348355f, -0.471396736825998f, + 0.831469612302545f, -0.555570233019602f, + 0.773010453362737f, -0.634393284163645f, + 0.707106781186548f, -0.707106781186547f, + 0.634393284163645f, -0.773010453362737f, + 0.555570233019602f, -0.831469612302545f, + 0.471396736825998f, -0.881921264348355f, + 0.382683432365090f, -0.923879532511287f, + 0.290284677254462f, -0.956940335732209f, + 0.195090322016129f, -0.980785280403230f, + 0.098017140329561f, -0.995184726672197f +}; +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F32_128) +const float32_t twiddleCoef_rfft_128[128] = { + 0.000000000f, 1.000000000f, + 0.049067674f, 0.998795456f, + 0.098017140f, 0.995184727f, + 0.146730474f, 0.989176510f, + 0.195090322f, 0.980785280f, + 0.242980180f, 0.970031253f, + 0.290284677f, 0.956940336f, + 0.336889853f, 0.941544065f, + 0.382683432f, 0.923879533f, + 0.427555093f, 0.903989293f, + 0.471396737f, 0.881921264f, + 0.514102744f, 0.857728610f, + 0.555570233f, 0.831469612f, + 0.595699304f, 0.803207531f, + 0.634393284f, 0.773010453f, + 0.671558955f, 0.740951125f, + 0.707106781f, 0.707106781f, + 0.740951125f, 0.671558955f, + 0.773010453f, 0.634393284f, + 0.803207531f, 0.595699304f, + 0.831469612f, 0.555570233f, + 0.857728610f, 0.514102744f, + 0.881921264f, 0.471396737f, + 0.903989293f, 0.427555093f, + 0.923879533f, 0.382683432f, + 0.941544065f, 0.336889853f, + 0.956940336f, 0.290284677f, + 0.970031253f, 0.242980180f, + 0.980785280f, 0.195090322f, + 0.989176510f, 0.146730474f, + 0.995184727f, 0.098017140f, + 0.998795456f, 0.049067674f, + 1.000000000f, 0.000000000f, + 0.998795456f, -0.049067674f, + 0.995184727f, -0.098017140f, + 0.989176510f, -0.146730474f, + 0.980785280f, -0.195090322f, + 0.970031253f, -0.242980180f, + 0.956940336f, -0.290284677f, + 0.941544065f, -0.336889853f, + 0.923879533f, -0.382683432f, + 0.903989293f, -0.427555093f, + 0.881921264f, -0.471396737f, + 0.857728610f, -0.514102744f, + 0.831469612f, -0.555570233f, + 0.803207531f, -0.595699304f, + 0.773010453f, -0.634393284f, + 0.740951125f, -0.671558955f, + 0.707106781f, -0.707106781f, + 0.671558955f, -0.740951125f, + 0.634393284f, -0.773010453f, + 0.595699304f, -0.803207531f, + 0.555570233f, -0.831469612f, + 0.514102744f, -0.857728610f, + 0.471396737f, -0.881921264f, + 0.427555093f, -0.903989293f, + 0.382683432f, -0.923879533f, + 0.336889853f, -0.941544065f, + 0.290284677f, -0.956940336f, + 0.242980180f, -0.970031253f, + 0.195090322f, -0.980785280f, + 0.146730474f, -0.989176510f, + 0.098017140f, -0.995184727f, + 0.049067674f, -0.998795456f +}; +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F32_256) +const float32_t twiddleCoef_rfft_256[256] = { + 0.000000000f, 1.000000000f, + 0.024541229f, 0.999698819f, + 0.049067674f, 0.998795456f, + 0.073564564f, 0.997290457f, + 0.098017140f, 0.995184727f, + 0.122410675f, 0.992479535f, + 0.146730474f, 0.989176510f, + 0.170961889f, 0.985277642f, + 0.195090322f, 0.980785280f, + 0.219101240f, 0.975702130f, + 0.242980180f, 0.970031253f, + 0.266712757f, 0.963776066f, + 0.290284677f, 0.956940336f, + 0.313681740f, 0.949528181f, + 0.336889853f, 0.941544065f, + 0.359895037f, 0.932992799f, + 0.382683432f, 0.923879533f, + 0.405241314f, 0.914209756f, + 0.427555093f, 0.903989293f, + 0.449611330f, 0.893224301f, + 0.471396737f, 0.881921264f, + 0.492898192f, 0.870086991f, + 0.514102744f, 0.857728610f, + 0.534997620f, 0.844853565f, + 0.555570233f, 0.831469612f, + 0.575808191f, 0.817584813f, + 0.595699304f, 0.803207531f, + 0.615231591f, 0.788346428f, + 0.634393284f, 0.773010453f, + 0.653172843f, 0.757208847f, + 0.671558955f, 0.740951125f, + 0.689540545f, 0.724247083f, + 0.707106781f, 0.707106781f, + 0.724247083f, 0.689540545f, + 0.740951125f, 0.671558955f, + 0.757208847f, 0.653172843f, + 0.773010453f, 0.634393284f, + 0.788346428f, 0.615231591f, + 0.803207531f, 0.595699304f, + 0.817584813f, 0.575808191f, + 0.831469612f, 0.555570233f, + 0.844853565f, 0.534997620f, + 0.857728610f, 0.514102744f, + 0.870086991f, 0.492898192f, + 0.881921264f, 0.471396737f, + 0.893224301f, 0.449611330f, + 0.903989293f, 0.427555093f, + 0.914209756f, 0.405241314f, + 0.923879533f, 0.382683432f, + 0.932992799f, 0.359895037f, + 0.941544065f, 0.336889853f, + 0.949528181f, 0.313681740f, + 0.956940336f, 0.290284677f, + 0.963776066f, 0.266712757f, + 0.970031253f, 0.242980180f, + 0.975702130f, 0.219101240f, + 0.980785280f, 0.195090322f, + 0.985277642f, 0.170961889f, + 0.989176510f, 0.146730474f, + 0.992479535f, 0.122410675f, + 0.995184727f, 0.098017140f, + 0.997290457f, 0.073564564f, + 0.998795456f, 0.049067674f, + 0.999698819f, 0.024541229f, + 1.000000000f, 0.000000000f, + 0.999698819f, -0.024541229f, + 0.998795456f, -0.049067674f, + 0.997290457f, -0.073564564f, + 0.995184727f, -0.098017140f, + 0.992479535f, -0.122410675f, + 0.989176510f, -0.146730474f, + 0.985277642f, -0.170961889f, + 0.980785280f, -0.195090322f, + 0.975702130f, -0.219101240f, + 0.970031253f, -0.242980180f, + 0.963776066f, -0.266712757f, + 0.956940336f, -0.290284677f, + 0.949528181f, -0.313681740f, + 0.941544065f, -0.336889853f, + 0.932992799f, -0.359895037f, + 0.923879533f, -0.382683432f, + 0.914209756f, -0.405241314f, + 0.903989293f, -0.427555093f, + 0.893224301f, -0.449611330f, + 0.881921264f, -0.471396737f, + 0.870086991f, -0.492898192f, + 0.857728610f, -0.514102744f, + 0.844853565f, -0.534997620f, + 0.831469612f, -0.555570233f, + 0.817584813f, -0.575808191f, + 0.803207531f, -0.595699304f, + 0.788346428f, -0.615231591f, + 0.773010453f, -0.634393284f, + 0.757208847f, -0.653172843f, + 0.740951125f, -0.671558955f, + 0.724247083f, -0.689540545f, + 0.707106781f, -0.707106781f, + 0.689540545f, -0.724247083f, + 0.671558955f, -0.740951125f, + 0.653172843f, -0.757208847f, + 0.634393284f, -0.773010453f, + 0.615231591f, -0.788346428f, + 0.595699304f, -0.803207531f, + 0.575808191f, -0.817584813f, + 0.555570233f, -0.831469612f, + 0.534997620f, -0.844853565f, + 0.514102744f, -0.857728610f, + 0.492898192f, -0.870086991f, + 0.471396737f, -0.881921264f, + 0.449611330f, -0.893224301f, + 0.427555093f, -0.903989293f, + 0.405241314f, -0.914209756f, + 0.382683432f, -0.923879533f, + 0.359895037f, -0.932992799f, + 0.336889853f, -0.941544065f, + 0.313681740f, -0.949528181f, + 0.290284677f, -0.956940336f, + 0.266712757f, -0.963776066f, + 0.242980180f, -0.970031253f, + 0.219101240f, -0.975702130f, + 0.195090322f, -0.980785280f, + 0.170961889f, -0.985277642f, + 0.146730474f, -0.989176510f, + 0.122410675f, -0.992479535f, + 0.098017140f, -0.995184727f, + 0.073564564f, -0.997290457f, + 0.049067674f, -0.998795456f, + 0.024541229f, -0.999698819f +}; +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F32_512) +const float32_t twiddleCoef_rfft_512[512] = { + 0.000000000f, 1.000000000f, + 0.012271538f, 0.999924702f, + 0.024541229f, 0.999698819f, + 0.036807223f, 0.999322385f, + 0.049067674f, 0.998795456f, + 0.061320736f, 0.998118113f, + 0.073564564f, 0.997290457f, + 0.085797312f, 0.996312612f, + 0.098017140f, 0.995184727f, + 0.110222207f, 0.993906970f, + 0.122410675f, 0.992479535f, + 0.134580709f, 0.990902635f, + 0.146730474f, 0.989176510f, + 0.158858143f, 0.987301418f, + 0.170961889f, 0.985277642f, + 0.183039888f, 0.983105487f, + 0.195090322f, 0.980785280f, + 0.207111376f, 0.978317371f, + 0.219101240f, 0.975702130f, + 0.231058108f, 0.972939952f, + 0.242980180f, 0.970031253f, + 0.254865660f, 0.966976471f, + 0.266712757f, 0.963776066f, + 0.278519689f, 0.960430519f, + 0.290284677f, 0.956940336f, + 0.302005949f, 0.953306040f, + 0.313681740f, 0.949528181f, + 0.325310292f, 0.945607325f, + 0.336889853f, 0.941544065f, + 0.348418680f, 0.937339012f, + 0.359895037f, 0.932992799f, + 0.371317194f, 0.928506080f, + 0.382683432f, 0.923879533f, + 0.393992040f, 0.919113852f, + 0.405241314f, 0.914209756f, + 0.416429560f, 0.909167983f, + 0.427555093f, 0.903989293f, + 0.438616239f, 0.898674466f, + 0.449611330f, 0.893224301f, + 0.460538711f, 0.887639620f, + 0.471396737f, 0.881921264f, + 0.482183772f, 0.876070094f, + 0.492898192f, 0.870086991f, + 0.503538384f, 0.863972856f, + 0.514102744f, 0.857728610f, + 0.524589683f, 0.851355193f, + 0.534997620f, 0.844853565f, + 0.545324988f, 0.838224706f, + 0.555570233f, 0.831469612f, + 0.565731811f, 0.824589303f, + 0.575808191f, 0.817584813f, + 0.585797857f, 0.810457198f, + 0.595699304f, 0.803207531f, + 0.605511041f, 0.795836905f, + 0.615231591f, 0.788346428f, + 0.624859488f, 0.780737229f, + 0.634393284f, 0.773010453f, + 0.643831543f, 0.765167266f, + 0.653172843f, 0.757208847f, + 0.662415778f, 0.749136395f, + 0.671558955f, 0.740951125f, + 0.680600998f, 0.732654272f, + 0.689540545f, 0.724247083f, + 0.698376249f, 0.715730825f, + 0.707106781f, 0.707106781f, + 0.715730825f, 0.698376249f, + 0.724247083f, 0.689540545f, + 0.732654272f, 0.680600998f, + 0.740951125f, 0.671558955f, + 0.749136395f, 0.662415778f, + 0.757208847f, 0.653172843f, + 0.765167266f, 0.643831543f, + 0.773010453f, 0.634393284f, + 0.780737229f, 0.624859488f, + 0.788346428f, 0.615231591f, + 0.795836905f, 0.605511041f, + 0.803207531f, 0.595699304f, + 0.810457198f, 0.585797857f, + 0.817584813f, 0.575808191f, + 0.824589303f, 0.565731811f, + 0.831469612f, 0.555570233f, + 0.838224706f, 0.545324988f, + 0.844853565f, 0.534997620f, + 0.851355193f, 0.524589683f, + 0.857728610f, 0.514102744f, + 0.863972856f, 0.503538384f, + 0.870086991f, 0.492898192f, + 0.876070094f, 0.482183772f, + 0.881921264f, 0.471396737f, + 0.887639620f, 0.460538711f, + 0.893224301f, 0.449611330f, + 0.898674466f, 0.438616239f, + 0.903989293f, 0.427555093f, + 0.909167983f, 0.416429560f, + 0.914209756f, 0.405241314f, + 0.919113852f, 0.393992040f, + 0.923879533f, 0.382683432f, + 0.928506080f, 0.371317194f, + 0.932992799f, 0.359895037f, + 0.937339012f, 0.348418680f, + 0.941544065f, 0.336889853f, + 0.945607325f, 0.325310292f, + 0.949528181f, 0.313681740f, + 0.953306040f, 0.302005949f, + 0.956940336f, 0.290284677f, + 0.960430519f, 0.278519689f, + 0.963776066f, 0.266712757f, + 0.966976471f, 0.254865660f, + 0.970031253f, 0.242980180f, + 0.972939952f, 0.231058108f, + 0.975702130f, 0.219101240f, + 0.978317371f, 0.207111376f, + 0.980785280f, 0.195090322f, + 0.983105487f, 0.183039888f, + 0.985277642f, 0.170961889f, + 0.987301418f, 0.158858143f, + 0.989176510f, 0.146730474f, + 0.990902635f, 0.134580709f, + 0.992479535f, 0.122410675f, + 0.993906970f, 0.110222207f, + 0.995184727f, 0.098017140f, + 0.996312612f, 0.085797312f, + 0.997290457f, 0.073564564f, + 0.998118113f, 0.061320736f, + 0.998795456f, 0.049067674f, + 0.999322385f, 0.036807223f, + 0.999698819f, 0.024541229f, + 0.999924702f, 0.012271538f, + 1.000000000f, 0.000000000f, + 0.999924702f, -0.012271538f, + 0.999698819f, -0.024541229f, + 0.999322385f, -0.036807223f, + 0.998795456f, -0.049067674f, + 0.998118113f, -0.061320736f, + 0.997290457f, -0.073564564f, + 0.996312612f, -0.085797312f, + 0.995184727f, -0.098017140f, + 0.993906970f, -0.110222207f, + 0.992479535f, -0.122410675f, + 0.990902635f, -0.134580709f, + 0.989176510f, -0.146730474f, + 0.987301418f, -0.158858143f, + 0.985277642f, -0.170961889f, + 0.983105487f, -0.183039888f, + 0.980785280f, -0.195090322f, + 0.978317371f, -0.207111376f, + 0.975702130f, -0.219101240f, + 0.972939952f, -0.231058108f, + 0.970031253f, -0.242980180f, + 0.966976471f, -0.254865660f, + 0.963776066f, -0.266712757f, + 0.960430519f, -0.278519689f, + 0.956940336f, -0.290284677f, + 0.953306040f, -0.302005949f, + 0.949528181f, -0.313681740f, + 0.945607325f, -0.325310292f, + 0.941544065f, -0.336889853f, + 0.937339012f, -0.348418680f, + 0.932992799f, -0.359895037f, + 0.928506080f, -0.371317194f, + 0.923879533f, -0.382683432f, + 0.919113852f, -0.393992040f, + 0.914209756f, -0.405241314f, + 0.909167983f, -0.416429560f, + 0.903989293f, -0.427555093f, + 0.898674466f, -0.438616239f, + 0.893224301f, -0.449611330f, + 0.887639620f, -0.460538711f, + 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-0.999204759f, + 0.038340120f, -0.999264747f, + 0.036807223f, -0.999322385f, + 0.035274239f, -0.999377670f, + 0.033741172f, -0.999430605f, + 0.032208025f, -0.999481187f, + 0.030674803f, -0.999529418f, + 0.029141509f, -0.999575296f, + 0.027608146f, -0.999618822f, + 0.026074718f, -0.999659997f, + 0.024541229f, -0.999698819f, + 0.023007681f, -0.999735288f, + 0.021474080f, -0.999769405f, + 0.019940429f, -0.999801170f, + 0.018406730f, -0.999830582f, + 0.016872988f, -0.999857641f, + 0.015339206f, -0.999882347f, + 0.013805389f, -0.999904701f, + 0.012271538f, -0.999924702f, + 0.010737659f, -0.999942350f, + 0.009203755f, -0.999957645f, + 0.007669829f, -0.999970586f, + 0.006135885f, -0.999981175f, + 0.004601926f, -0.999989411f, + 0.003067957f, -0.999995294f, + 0.001533980f, -0.999998823f +}; + +#endif /* if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_FFT_ALL_TABLES) */ + +/** + @ingroup RealFFT + */ + +/** + @addtogroup RealFFT_Table Real FFT Tables + @{ + */ + +/** + @par + Generation of realCoefA array: + @par + n = 4096 + 
for (i = 0; i < n; i++)
+  {
+     pATable[2 * i]     = 0.5 * ( 1.0 - sin (2 * PI / (double) (2 * n) * (double) i));
+     pATable[2 * i + 1] = 0.5 * (-1.0 * cos (2 * PI / (double) (2 * n) * (double) i));
+  }
+ */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_REALCOEF_F32) +const float32_t realCoefA[8192] = { + 0.500000000000000f, -0.500000000000000f, 0.499616503715515f, -0.499999850988388f, + 0.499233007431030f, -0.499999403953552f, 0.498849511146545f, -0.499998688697815f, + 0.498466014862061f, -0.499997645616531f, 0.498082518577576f, -0.499996334314346f, + 0.497699022293091f, -0.499994695186615f, 0.497315555810928f, -0.499992787837982f, + 0.496932059526443f, -0.499990582466125f, 0.496548563241959f, -0.499988079071045f, + 0.496165096759796f, -0.499985307455063f, 0.495781600475311f, -0.499982208013535f, + 0.495398133993149f, -0.499978810548782f, 0.495014637708664f, -0.499975144863129f, + 0.494631171226501f, -0.499971181154251f, 0.494247704744339f, -0.499966919422150f, + 0.493864238262177f, -0.499962359666824f, 0.493480771780014f, -0.499957501888275f, + 0.493097305297852f, -0.499952346086502f, 0.492713838815689f, -0.499946922063828f, + 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0.485045909881592f, 0.499776333570480f, + 0.485429257154465f, 0.499787658452988f, 0.485812574625015f, 0.499798685312271f, + 0.486195921897888f, 0.499809414148331f, 0.486579269170761f, 0.499819844961166f, + 0.486962646245956f, 0.499830007553101f, 0.487346023321152f, 0.499839842319489f, + 0.487729400396347f, 0.499849408864975f, 0.488112777471542f, 0.499858677387238f, + 0.488496154546738f, 0.499867647886276f, 0.488879561424255f, 0.499876320362091f, + 0.489262968301773f, 0.499884694814682f, 0.489646375179291f, 0.499892801046371f, + 0.490029782056808f, 0.499900579452515f, 0.490413218736649f, 0.499908089637756f, + 0.490796625614166f, 0.499915301799774f, 0.491180062294006f, 0.499922215938568f, + 0.491563498973846f, 0.499928832054138f, 0.491946935653687f, 0.499935150146484f, + 0.492330402135849f, 0.499941170215607f, 0.492713838815689f, 0.499946922063828f, + 0.493097305297852f, 0.499952346086502f, 0.493480771780014f, 0.499957501888275f, + 0.493864238262177f, 0.499962359666824f, 0.494247704744339f, 0.499966919422150f, + 0.494631171226501f, 0.499971181154251f, 0.495014637708664f, 0.499975144863129f, + 0.495398133993149f, 0.499978810548782f, 0.495781600475311f, 0.499982208013535f, + 0.496165096759796f, 0.499985307455063f, 0.496548563241959f, 0.499988079071045f, + 0.496932059526443f, 0.499990582466125f, 0.497315555810928f, 0.499992787837982f, + 0.497699022293091f, 0.499994695186615f, 0.498082518577576f, 0.499996334314346f, + 0.498466014862061f, 0.499997645616531f, 0.498849511146545f, 0.499998688697815f, + 0.499233007431030f, 0.499999403953552f, 0.499616503715515f, 0.499999850988388f, +}; + + +/** + @par + Generation of realCoefB array: + @par + n = 4096 + 
for (i = 0; i < n; i++)
+  {
+     pBTable[2 * i]     = 0.5 * (1.0 + sin (2 * PI / (double) (2 * n) * (double) i));
+     pBTable[2 * i + 1] = 0.5 * (1.0 * cos (2 * PI / (double) (2 * n) * (double) i));
+  }
+ */ + +const float32_t realCoefB[8192] = { + 0.500000000000000f, 0.500000000000000f, 0.500383496284485f, 0.499999850988388f, + 0.500766992568970f, 0.499999403953552f, 0.501150488853455f, 0.499998688697815f, + 0.501533985137939f, 0.499997645616531f, 0.501917481422424f, 0.499996334314346f, + 0.502300977706909f, 0.499994695186615f, 0.502684473991394f, 0.499992787837982f, + 0.503067970275879f, 0.499990582466125f, 0.503451406955719f, 0.499988079071045f, + 0.503834903240204f, 0.499985307455063f, 0.504218399524689f, 0.499982208013535f, + 0.504601895809174f, 0.499978810548782f, 0.504985332489014f, 0.499975144863129f, + 0.505368828773499f, 0.499971181154251f, 0.505752325057983f, 0.499966919422150f, + 0.506135761737823f, 0.499962359666824f, 0.506519258022308f, 0.499957501888275f, + 0.506902694702148f, 0.499952346086502f, 0.507286131381989f, 0.499946922063828f, + 0.507669627666473f, 0.499941170215607f, 0.508053064346313f, 0.499935150146484f, + 0.508436501026154f, 0.499928832054138f, 0.508819937705994f, 0.499922215938568f, + 0.509203374385834f, 0.499915301799774f, 0.509586811065674f, 0.499908089637756f, + 0.509970188140869f, 0.499900579452515f, 0.510353624820709f, 0.499892801046371f, + 0.510737061500549f, 0.499884694814682f, 0.511120438575745f, 0.499876320362091f, + 0.511503815650940f, 0.499867647886276f, 0.511887252330780f, 0.499858677387238f, + 0.512270629405975f, 0.499849408864975f, 0.512654006481171f, 0.499839842319489f, + 0.513037383556366f, 0.499830007553101f, 0.513420701026917f, 0.499819844961166f, + 0.513804078102112f, 0.499809414148331f, 0.514187395572662f, 0.499798685312271f, + 0.514570772647858f, 0.499787658452988f, 0.514954090118408f, 0.499776333570480f, + 0.515337407588959f, 0.499764710664749f, 0.515720725059509f, 0.499752789735794f, + 0.516103982925415f, 0.499740600585938f, 0.516487300395966f, 0.499728083610535f, + 0.516870558261871f, 0.499715298414230f, 0.517253875732422f, 0.499702215194702f, + 0.517637133598328f, 0.499688833951950f, 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for (i = 0; i < n; i++)
+  {
+     pATable[2 * i]     = 0.5 * ( 1.0 - sin (2 * PI / (double) (2 * n) * (double) i));
+     pATable[2 * i + 1] = 0.5 * (-1.0 * cos (2 * PI / (double) (2 * n) * (double) i));
+  }
+ @par + Convert to fixed point Q31 format + round(pATable[i] * pow(2, 31)) +*/ +const q31_t realCoefAQ31[8192] = { + (q31_t)0x40000000, (q31_t)0xc0000000, (q31_t)0x3ff36f02, (q31_t)0xc000013c, + (q31_t)0x3fe6de05, (q31_t)0xc00004ef, (q31_t)0x3fda4d09, (q31_t)0xc0000b1a, + (q31_t)0x3fcdbc0f, (q31_t)0xc00013bd, (q31_t)0x3fc12b16, (q31_t)0xc0001ed8, + (q31_t)0x3fb49a1f, (q31_t)0xc0002c6a, (q31_t)0x3fa8092c, (q31_t)0xc0003c74, + (q31_t)0x3f9b783c, (q31_t)0xc0004ef5, (q31_t)0x3f8ee750, (q31_t)0xc00063ee, + (q31_t)0x3f825668, (q31_t)0xc0007b5f, (q31_t)0x3f75c585, (q31_t)0xc0009547, + (q31_t)0x3f6934a8, (q31_t)0xc000b1a7, (q31_t)0x3f5ca3d0, (q31_t)0xc000d07e, + (q31_t)0x3f5012fe, (q31_t)0xc000f1ce, (q31_t)0x3f438234, (q31_t)0xc0011594, + (q31_t)0x3f36f170, (q31_t)0xc0013bd3, (q31_t)0x3f2a60b4, (q31_t)0xc0016489, + (q31_t)0x3f1dd001, (q31_t)0xc0018fb6, (q31_t)0x3f113f56, (q31_t)0xc001bd5c, + (q31_t)0x3f04aeb5, (q31_t)0xc001ed78, (q31_t)0x3ef81e1d, (q31_t)0xc002200d, + (q31_t)0x3eeb8d8f, (q31_t)0xc0025519, (q31_t)0x3edefd0c, (q31_t)0xc0028c9c, + (q31_t)0x3ed26c94, (q31_t)0xc002c697, (q31_t)0x3ec5dc28, (q31_t)0xc003030a, + (q31_t)0x3eb94bc8, (q31_t)0xc00341f4, (q31_t)0x3eacbb74, (q31_t)0xc0038356, + (q31_t)0x3ea02b2e, (q31_t)0xc003c72f, (q31_t)0x3e939af5, (q31_t)0xc0040d80, + (q31_t)0x3e870aca, (q31_t)0xc0045648, (q31_t)0x3e7a7aae, (q31_t)0xc004a188, + (q31_t)0x3e6deaa1, (q31_t)0xc004ef3f, (q31_t)0x3e615aa3, (q31_t)0xc0053f6e, + (q31_t)0x3e54cab5, (q31_t)0xc0059214, (q31_t)0x3e483ad8, (q31_t)0xc005e731, + (q31_t)0x3e3bab0b, (q31_t)0xc0063ec6, (q31_t)0x3e2f1b50, (q31_t)0xc00698d3, + (q31_t)0x3e228ba7, (q31_t)0xc006f556, (q31_t)0x3e15fc11, (q31_t)0xc0075452, + (q31_t)0x3e096c8d, (q31_t)0xc007b5c4, (q31_t)0x3dfcdd1d, (q31_t)0xc00819ae, + (q31_t)0x3df04dc0, (q31_t)0xc008800f, (q31_t)0x3de3be78, (q31_t)0xc008e8e8, + (q31_t)0x3dd72f45, (q31_t)0xc0095438, (q31_t)0x3dcaa027, (q31_t)0xc009c1ff, + (q31_t)0x3dbe111e, (q31_t)0xc00a323d, (q31_t)0x3db1822c, (q31_t)0xc00aa4f3, + (q31_t)0x3da4f351, (q31_t)0xc00b1a20, (q31_t)0x3d98648d, (q31_t)0xc00b91c4, + (q31_t)0x3d8bd5e1, (q31_t)0xc00c0be0, (q31_t)0x3d7f474d, (q31_t)0xc00c8872, + (q31_t)0x3d72b8d2, (q31_t)0xc00d077c, (q31_t)0x3d662a70, (q31_t)0xc00d88fd, + (q31_t)0x3d599c28, (q31_t)0xc00e0cf5, (q31_t)0x3d4d0df9, (q31_t)0xc00e9364, + (q31_t)0x3d407fe6, (q31_t)0xc00f1c4a, (q31_t)0x3d33f1ed, (q31_t)0xc00fa7a8, + (q31_t)0x3d276410, (q31_t)0xc010357c, (q31_t)0x3d1ad650, (q31_t)0xc010c5c7, + (q31_t)0x3d0e48ab, (q31_t)0xc011588a, (q31_t)0x3d01bb24, (q31_t)0xc011edc3, + (q31_t)0x3cf52dbb, (q31_t)0xc0128574, (q31_t)0x3ce8a06f, (q31_t)0xc0131f9b, + (q31_t)0x3cdc1342, (q31_t)0xc013bc39, (q31_t)0x3ccf8634, (q31_t)0xc0145b4e, + (q31_t)0x3cc2f945, (q31_t)0xc014fcda, (q31_t)0x3cb66c77, (q31_t)0xc015a0dd, + (q31_t)0x3ca9dfc8, (q31_t)0xc0164757, (q31_t)0x3c9d533b, (q31_t)0xc016f047, + (q31_t)0x3c90c6cf, (q31_t)0xc0179bae, (q31_t)0x3c843a85, (q31_t)0xc018498c, + (q31_t)0x3c77ae5e, (q31_t)0xc018f9e1, (q31_t)0x3c6b2259, (q31_t)0xc019acac, + (q31_t)0x3c5e9678, (q31_t)0xc01a61ee, (q31_t)0x3c520aba, (q31_t)0xc01b19a7, + (q31_t)0x3c457f21, (q31_t)0xc01bd3d6, (q31_t)0x3c38f3ac, (q31_t)0xc01c907c, + (q31_t)0x3c2c685d, (q31_t)0xc01d4f99, (q31_t)0x3c1fdd34, (q31_t)0xc01e112b, + (q31_t)0x3c135231, (q31_t)0xc01ed535, (q31_t)0x3c06c754, (q31_t)0xc01f9bb5, + (q31_t)0x3bfa3c9f, (q31_t)0xc02064ab, (q31_t)0x3bedb212, (q31_t)0xc0213018, + (q31_t)0x3be127ac, (q31_t)0xc021fdfb, (q31_t)0x3bd49d70, (q31_t)0xc022ce54, + (q31_t)0x3bc8135c, (q31_t)0xc023a124, (q31_t)0x3bbb8973, (q31_t)0xc024766a, + (q31_t)0x3baeffb3, (q31_t)0xc0254e27, (q31_t)0x3ba2761e, (q31_t)0xc0262859, + (q31_t)0x3b95ecb4, (q31_t)0xc0270502, (q31_t)0x3b896375, (q31_t)0xc027e421, + (q31_t)0x3b7cda63, (q31_t)0xc028c5b6, (q31_t)0x3b70517d, (q31_t)0xc029a9c1, + (q31_t)0x3b63c8c4, (q31_t)0xc02a9042, (q31_t)0x3b574039, (q31_t)0xc02b7939, + (q31_t)0x3b4ab7db, (q31_t)0xc02c64a6, (q31_t)0x3b3e2fac, (q31_t)0xc02d5289, + (q31_t)0x3b31a7ac, (q31_t)0xc02e42e2, (q31_t)0x3b251fdc, (q31_t)0xc02f35b1, + (q31_t)0x3b18983b, (q31_t)0xc0302af5, (q31_t)0x3b0c10cb, (q31_t)0xc03122b0, + (q31_t)0x3aff898c, (q31_t)0xc0321ce0, (q31_t)0x3af3027e, (q31_t)0xc0331986, + (q31_t)0x3ae67ba2, (q31_t)0xc03418a2, (q31_t)0x3ad9f4f8, (q31_t)0xc0351a33, + (q31_t)0x3acd6e81, (q31_t)0xc0361e3a, (q31_t)0x3ac0e83d, (q31_t)0xc03724b6, + (q31_t)0x3ab4622d, (q31_t)0xc0382da8, (q31_t)0x3aa7dc52, (q31_t)0xc0393910, + (q31_t)0x3a9b56ab, (q31_t)0xc03a46ed, (q31_t)0x3a8ed139, (q31_t)0xc03b573f, + (q31_t)0x3a824bfd, (q31_t)0xc03c6a07, (q31_t)0x3a75c6f8, (q31_t)0xc03d7f44, + (q31_t)0x3a694229, (q31_t)0xc03e96f6, (q31_t)0x3a5cbd91, (q31_t)0xc03fb11d, + (q31_t)0x3a503930, (q31_t)0xc040cdba, (q31_t)0x3a43b508, (q31_t)0xc041eccc, + (q31_t)0x3a373119, (q31_t)0xc0430e53, (q31_t)0x3a2aad62, (q31_t)0xc044324f, + (q31_t)0x3a1e29e5, (q31_t)0xc04558c0, (q31_t)0x3a11a6a3, (q31_t)0xc04681a6, + (q31_t)0x3a05239a, (q31_t)0xc047ad01, (q31_t)0x39f8a0cd, (q31_t)0xc048dad1, + (q31_t)0x39ec1e3b, (q31_t)0xc04a0b16, (q31_t)0x39df9be6, (q31_t)0xc04b3dcf, + (q31_t)0x39d319cc, (q31_t)0xc04c72fe, (q31_t)0x39c697f0, (q31_t)0xc04daaa1, + (q31_t)0x39ba1651, (q31_t)0xc04ee4b8, (q31_t)0x39ad94f0, (q31_t)0xc0502145, + (q31_t)0x39a113cd, (q31_t)0xc0516045, (q31_t)0x399492ea, (q31_t)0xc052a1bb, + (q31_t)0x39881245, (q31_t)0xc053e5a5, (q31_t)0x397b91e1, (q31_t)0xc0552c03, + (q31_t)0x396f11bc, (q31_t)0xc05674d6, (q31_t)0x396291d9, (q31_t)0xc057c01d, + (q31_t)0x39561237, (q31_t)0xc0590dd8, (q31_t)0x394992d7, (q31_t)0xc05a5e07, + (q31_t)0x393d13b8, (q31_t)0xc05bb0ab, (q31_t)0x393094dd, (q31_t)0xc05d05c3, + (q31_t)0x39241645, (q31_t)0xc05e5d4e, (q31_t)0x391797f0, (q31_t)0xc05fb74e, + (q31_t)0x390b19e0, (q31_t)0xc06113c2, (q31_t)0x38fe9c15, (q31_t)0xc06272aa, + (q31_t)0x38f21e8e, (q31_t)0xc063d405, (q31_t)0x38e5a14d, (q31_t)0xc06537d4, + (q31_t)0x38d92452, (q31_t)0xc0669e18, (q31_t)0x38cca79e, (q31_t)0xc06806ce, + (q31_t)0x38c02b31, (q31_t)0xc06971f9, (q31_t)0x38b3af0c, (q31_t)0xc06adf97, + (q31_t)0x38a7332e, (q31_t)0xc06c4fa8, (q31_t)0x389ab799, (q31_t)0xc06dc22e, + (q31_t)0x388e3c4d, (q31_t)0xc06f3726, (q31_t)0x3881c14b, (q31_t)0xc070ae92, + (q31_t)0x38754692, (q31_t)0xc0722871, (q31_t)0x3868cc24, (q31_t)0xc073a4c3, + (q31_t)0x385c5201, (q31_t)0xc0752389, (q31_t)0x384fd829, (q31_t)0xc076a4c2, + (q31_t)0x38435e9d, (q31_t)0xc078286e, (q31_t)0x3836e55d, (q31_t)0xc079ae8c, + (q31_t)0x382a6c6a, (q31_t)0xc07b371e, (q31_t)0x381df3c5, (q31_t)0xc07cc223, + (q31_t)0x38117b6d, (q31_t)0xc07e4f9b, (q31_t)0x38050364, (q31_t)0xc07fdf85, + (q31_t)0x37f88ba9, (q31_t)0xc08171e2, (q31_t)0x37ec143e, (q31_t)0xc08306b2, + (q31_t)0x37df9d22, (q31_t)0xc0849df4, (q31_t)0x37d32657, (q31_t)0xc08637a9, + (q31_t)0x37c6afdc, (q31_t)0xc087d3d0, (q31_t)0x37ba39b3, (q31_t)0xc089726a, + (q31_t)0x37adc3db, (q31_t)0xc08b1376, (q31_t)0x37a14e55, (q31_t)0xc08cb6f5, + (q31_t)0x3794d922, (q31_t)0xc08e5ce5, (q31_t)0x37886442, (q31_t)0xc0900548, + (q31_t)0x377befb5, (q31_t)0xc091b01d, (q31_t)0x376f7b7d, (q31_t)0xc0935d64, + (q31_t)0x37630799, (q31_t)0xc0950d1d, (q31_t)0x3756940a, (q31_t)0xc096bf48, + (q31_t)0x374a20d0, (q31_t)0xc09873e4, (q31_t)0x373daded, (q31_t)0xc09a2af3, + (q31_t)0x37313b60, (q31_t)0xc09be473, (q31_t)0x3724c92a, (q31_t)0xc09da065, + (q31_t)0x3718574b, (q31_t)0xc09f5ec8, (q31_t)0x370be5c4, (q31_t)0xc0a11f9d, + (q31_t)0x36ff7496, (q31_t)0xc0a2e2e3, (q31_t)0x36f303c0, (q31_t)0xc0a4a89b, + (q31_t)0x36e69344, (q31_t)0xc0a670c4, (q31_t)0x36da2321, (q31_t)0xc0a83b5e, + (q31_t)0x36cdb359, (q31_t)0xc0aa086a, (q31_t)0x36c143ec, (q31_t)0xc0abd7e6, + (q31_t)0x36b4d4d9, (q31_t)0xc0ada9d4, (q31_t)0x36a86623, (q31_t)0xc0af7e33, + (q31_t)0x369bf7c9, (q31_t)0xc0b15502, (q31_t)0x368f89cb, (q31_t)0xc0b32e42, + (q31_t)0x36831c2b, (q31_t)0xc0b509f3, (q31_t)0x3676aee8, (q31_t)0xc0b6e815, + (q31_t)0x366a4203, (q31_t)0xc0b8c8a7, (q31_t)0x365dd57d, (q31_t)0xc0baabaa, + (q31_t)0x36516956, (q31_t)0xc0bc911d, (q31_t)0x3644fd8f, (q31_t)0xc0be7901, + (q31_t)0x36389228, (q31_t)0xc0c06355, (q31_t)0x362c2721, (q31_t)0xc0c25019, + (q31_t)0x361fbc7b, (q31_t)0xc0c43f4d, (q31_t)0x36135237, (q31_t)0xc0c630f2, + (q31_t)0x3606e854, (q31_t)0xc0c82506, (q31_t)0x35fa7ed4, (q31_t)0xc0ca1b8a, + (q31_t)0x35ee15b7, (q31_t)0xc0cc147f, (q31_t)0x35e1acfd, (q31_t)0xc0ce0fe3, + (q31_t)0x35d544a7, (q31_t)0xc0d00db6, (q31_t)0x35c8dcb6, (q31_t)0xc0d20dfa, + (q31_t)0x35bc7529, (q31_t)0xc0d410ad, (q31_t)0x35b00e02, (q31_t)0xc0d615cf, + (q31_t)0x35a3a740, (q31_t)0xc0d81d61, (q31_t)0x359740e5, (q31_t)0xc0da2762, + (q31_t)0x358adaf0, (q31_t)0xc0dc33d2, (q31_t)0x357e7563, (q31_t)0xc0de42b2, + (q31_t)0x3572103d, (q31_t)0xc0e05401, (q31_t)0x3565ab80, (q31_t)0xc0e267be, + (q31_t)0x3559472b, (q31_t)0xc0e47deb, (q31_t)0x354ce33f, (q31_t)0xc0e69686, + (q31_t)0x35407fbd, (q31_t)0xc0e8b190, (q31_t)0x35341ca5, (q31_t)0xc0eacf09, + (q31_t)0x3527b9f7, (q31_t)0xc0eceef1, (q31_t)0x351b57b5, (q31_t)0xc0ef1147, + (q31_t)0x350ef5de, (q31_t)0xc0f1360b, (q31_t)0x35029473, (q31_t)0xc0f35d3e, + (q31_t)0x34f63374, (q31_t)0xc0f586df, (q31_t)0x34e9d2e3, (q31_t)0xc0f7b2ee, + (q31_t)0x34dd72be, (q31_t)0xc0f9e16b, (q31_t)0x34d11308, (q31_t)0xc0fc1257, + (q31_t)0x34c4b3c0, (q31_t)0xc0fe45b0, (q31_t)0x34b854e7, (q31_t)0xc1007b77, + (q31_t)0x34abf67e, (q31_t)0xc102b3ac, (q31_t)0x349f9884, (q31_t)0xc104ee4f, + (q31_t)0x34933afa, (q31_t)0xc1072b5f, (q31_t)0x3486dde1, (q31_t)0xc1096add, + (q31_t)0x347a8139, (q31_t)0xc10bacc8, (q31_t)0x346e2504, (q31_t)0xc10df120, + (q31_t)0x3461c940, (q31_t)0xc11037e6, (q31_t)0x34556def, (q31_t)0xc1128119, + (q31_t)0x34491311, (q31_t)0xc114ccb9, (q31_t)0x343cb8a7, (q31_t)0xc1171ac6, + (q31_t)0x34305eb0, (q31_t)0xc1196b3f, (q31_t)0x3424052f, (q31_t)0xc11bbe26, + (q31_t)0x3417ac22, (q31_t)0xc11e1379, (q31_t)0x340b538b, (q31_t)0xc1206b39, + (q31_t)0x33fefb6a, (q31_t)0xc122c566, (q31_t)0x33f2a3bf, (q31_t)0xc12521ff, + (q31_t)0x33e64c8c, (q31_t)0xc1278104, (q31_t)0x33d9f5cf, (q31_t)0xc129e276, + (q31_t)0x33cd9f8b, (q31_t)0xc12c4653, (q31_t)0x33c149bf, (q31_t)0xc12eac9d, + (q31_t)0x33b4f46c, (q31_t)0xc1311553, (q31_t)0x33a89f92, (q31_t)0xc1338075, + (q31_t)0x339c4b32, (q31_t)0xc135ee02, (q31_t)0x338ff74d, (q31_t)0xc1385dfb, + (q31_t)0x3383a3e2, (q31_t)0xc13ad060, (q31_t)0x337750f2, (q31_t)0xc13d4530, + (q31_t)0x336afe7e, (q31_t)0xc13fbc6c, (q31_t)0x335eac86, (q31_t)0xc1423613, + (q31_t)0x33525b0b, (q31_t)0xc144b225, (q31_t)0x33460a0d, (q31_t)0xc14730a3, + (q31_t)0x3339b98d, (q31_t)0xc149b18b, (q31_t)0x332d698a, (q31_t)0xc14c34df, + (q31_t)0x33211a07, (q31_t)0xc14eba9d, (q31_t)0x3314cb02, (q31_t)0xc15142c6, + (q31_t)0x33087c7d, (q31_t)0xc153cd5a, (q31_t)0x32fc2e77, (q31_t)0xc1565a58, + (q31_t)0x32efe0f2, (q31_t)0xc158e9c1, (q31_t)0x32e393ef, (q31_t)0xc15b7b94, + (q31_t)0x32d7476c, (q31_t)0xc15e0fd1, (q31_t)0x32cafb6b, (q31_t)0xc160a678, + (q31_t)0x32beafed, (q31_t)0xc1633f8a, (q31_t)0x32b264f2, (q31_t)0xc165db05, + (q31_t)0x32a61a7a, (q31_t)0xc16878eb, (q31_t)0x3299d085, (q31_t)0xc16b193a, + (q31_t)0x328d8715, (q31_t)0xc16dbbf3, (q31_t)0x32813e2a, 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(q31_t)0x3acd6e81, (q31_t)0x3fc9e1c6, (q31_t)0x3ad9f4f8, (q31_t)0x3fcae5cd, + (q31_t)0x3ae67ba2, (q31_t)0x3fcbe75e, (q31_t)0x3af3027e, (q31_t)0x3fcce67a, + (q31_t)0x3aff898c, (q31_t)0x3fcde320, (q31_t)0x3b0c10cb, (q31_t)0x3fcedd50, + (q31_t)0x3b18983b, (q31_t)0x3fcfd50b, (q31_t)0x3b251fdc, (q31_t)0x3fd0ca4f, + (q31_t)0x3b31a7ac, (q31_t)0x3fd1bd1e, (q31_t)0x3b3e2fac, (q31_t)0x3fd2ad77, + (q31_t)0x3b4ab7db, (q31_t)0x3fd39b5a, (q31_t)0x3b574039, (q31_t)0x3fd486c7, + (q31_t)0x3b63c8c4, (q31_t)0x3fd56fbe, (q31_t)0x3b70517d, (q31_t)0x3fd6563f, + (q31_t)0x3b7cda63, (q31_t)0x3fd73a4a, (q31_t)0x3b896375, (q31_t)0x3fd81bdf, + (q31_t)0x3b95ecb4, (q31_t)0x3fd8fafe, (q31_t)0x3ba2761e, (q31_t)0x3fd9d7a7, + (q31_t)0x3baeffb3, (q31_t)0x3fdab1d9, (q31_t)0x3bbb8973, (q31_t)0x3fdb8996, + (q31_t)0x3bc8135c, (q31_t)0x3fdc5edc, (q31_t)0x3bd49d70, (q31_t)0x3fdd31ac, + (q31_t)0x3be127ac, (q31_t)0x3fde0205, (q31_t)0x3bedb212, (q31_t)0x3fdecfe8, + (q31_t)0x3bfa3c9f, (q31_t)0x3fdf9b55, (q31_t)0x3c06c754, (q31_t)0x3fe0644b, + (q31_t)0x3c135231, (q31_t)0x3fe12acb, (q31_t)0x3c1fdd34, (q31_t)0x3fe1eed5, + (q31_t)0x3c2c685d, (q31_t)0x3fe2b067, (q31_t)0x3c38f3ac, (q31_t)0x3fe36f84, + (q31_t)0x3c457f21, (q31_t)0x3fe42c2a, (q31_t)0x3c520aba, (q31_t)0x3fe4e659, + (q31_t)0x3c5e9678, (q31_t)0x3fe59e12, (q31_t)0x3c6b2259, (q31_t)0x3fe65354, + (q31_t)0x3c77ae5e, (q31_t)0x3fe7061f, (q31_t)0x3c843a85, (q31_t)0x3fe7b674, + (q31_t)0x3c90c6cf, (q31_t)0x3fe86452, (q31_t)0x3c9d533b, (q31_t)0x3fe90fb9, + (q31_t)0x3ca9dfc8, (q31_t)0x3fe9b8a9, (q31_t)0x3cb66c77, (q31_t)0x3fea5f23, + (q31_t)0x3cc2f945, (q31_t)0x3feb0326, (q31_t)0x3ccf8634, (q31_t)0x3feba4b2, + (q31_t)0x3cdc1342, (q31_t)0x3fec43c7, (q31_t)0x3ce8a06f, (q31_t)0x3fece065, + (q31_t)0x3cf52dbb, (q31_t)0x3fed7a8c, (q31_t)0x3d01bb24, (q31_t)0x3fee123d, + (q31_t)0x3d0e48ab, (q31_t)0x3feea776, (q31_t)0x3d1ad650, (q31_t)0x3fef3a39, + (q31_t)0x3d276410, (q31_t)0x3fefca84, (q31_t)0x3d33f1ed, (q31_t)0x3ff05858, + (q31_t)0x3d407fe6, (q31_t)0x3ff0e3b6, (q31_t)0x3d4d0df9, (q31_t)0x3ff16c9c, + (q31_t)0x3d599c28, (q31_t)0x3ff1f30b, (q31_t)0x3d662a70, (q31_t)0x3ff27703, + (q31_t)0x3d72b8d2, (q31_t)0x3ff2f884, (q31_t)0x3d7f474d, (q31_t)0x3ff3778e, + (q31_t)0x3d8bd5e1, (q31_t)0x3ff3f420, (q31_t)0x3d98648d, (q31_t)0x3ff46e3c, + (q31_t)0x3da4f351, (q31_t)0x3ff4e5e0, (q31_t)0x3db1822c, (q31_t)0x3ff55b0d, + (q31_t)0x3dbe111e, (q31_t)0x3ff5cdc3, (q31_t)0x3dcaa027, (q31_t)0x3ff63e01, + (q31_t)0x3dd72f45, (q31_t)0x3ff6abc8, (q31_t)0x3de3be78, (q31_t)0x3ff71718, + (q31_t)0x3df04dc0, (q31_t)0x3ff77ff1, (q31_t)0x3dfcdd1d, (q31_t)0x3ff7e652, + (q31_t)0x3e096c8d, (q31_t)0x3ff84a3c, (q31_t)0x3e15fc11, (q31_t)0x3ff8abae, + (q31_t)0x3e228ba7, (q31_t)0x3ff90aaa, (q31_t)0x3e2f1b50, (q31_t)0x3ff9672d, + (q31_t)0x3e3bab0b, (q31_t)0x3ff9c13a, (q31_t)0x3e483ad8, (q31_t)0x3ffa18cf, + (q31_t)0x3e54cab5, (q31_t)0x3ffa6dec, (q31_t)0x3e615aa3, (q31_t)0x3ffac092, + (q31_t)0x3e6deaa1, (q31_t)0x3ffb10c1, (q31_t)0x3e7a7aae, (q31_t)0x3ffb5e78, + (q31_t)0x3e870aca, (q31_t)0x3ffba9b8, (q31_t)0x3e939af5, (q31_t)0x3ffbf280, + (q31_t)0x3ea02b2e, (q31_t)0x3ffc38d1, (q31_t)0x3eacbb74, (q31_t)0x3ffc7caa, + (q31_t)0x3eb94bc8, (q31_t)0x3ffcbe0c, (q31_t)0x3ec5dc28, (q31_t)0x3ffcfcf6, + (q31_t)0x3ed26c94, (q31_t)0x3ffd3969, (q31_t)0x3edefd0c, (q31_t)0x3ffd7364, + (q31_t)0x3eeb8d8f, (q31_t)0x3ffdaae7, (q31_t)0x3ef81e1d, (q31_t)0x3ffddff3, + (q31_t)0x3f04aeb5, (q31_t)0x3ffe1288, (q31_t)0x3f113f56, (q31_t)0x3ffe42a4, + (q31_t)0x3f1dd001, (q31_t)0x3ffe704a, (q31_t)0x3f2a60b4, (q31_t)0x3ffe9b77, + (q31_t)0x3f36f170, (q31_t)0x3ffec42d, (q31_t)0x3f438234, (q31_t)0x3ffeea6c, + (q31_t)0x3f5012fe, (q31_t)0x3fff0e32, (q31_t)0x3f5ca3d0, (q31_t)0x3fff2f82, + (q31_t)0x3f6934a8, (q31_t)0x3fff4e59, (q31_t)0x3f75c585, (q31_t)0x3fff6ab9, + (q31_t)0x3f825668, (q31_t)0x3fff84a1, (q31_t)0x3f8ee750, (q31_t)0x3fff9c12, + (q31_t)0x3f9b783c, (q31_t)0x3fffb10b, (q31_t)0x3fa8092c, (q31_t)0x3fffc38c, + (q31_t)0x3fb49a1f, (q31_t)0x3fffd396, (q31_t)0x3fc12b16, (q31_t)0x3fffe128, + (q31_t)0x3fcdbc0f, (q31_t)0x3fffec43, (q31_t)0x3fda4d09, (q31_t)0x3ffff4e6, + (q31_t)0x3fe6de05, (q31_t)0x3ffffb11, (q31_t)0x3ff36f02, (q31_t)0x3ffffec4, +}; + + +/** + @par + Generation of realCoefBQ31 array: + @par + n = 4096 + 
for (i = 0; i < n; i++)
+  {
+     pBTable[2 * i]     = 0.5 * (1.0 + sin (2 * PI / (double) (2 * n) * (double) i));
+     pBTable[2 * i + 1] = 0.5 * (1.0 * cos (2 * PI / (double) (2 * n) * (double) i));
+  }
+ @par + Convert to fixed point Q31 format + round(pBTable[i] * pow(2, 31)) + */ + +const q31_t realCoefBQ31[8192] = { + (q31_t)0x40000000, (q31_t)0x40000000, (q31_t)0x400c90fe, (q31_t)0x3ffffec4, + (q31_t)0x401921fb, (q31_t)0x3ffffb11, (q31_t)0x4025b2f7, (q31_t)0x3ffff4e6, + (q31_t)0x403243f1, (q31_t)0x3fffec43, (q31_t)0x403ed4ea, (q31_t)0x3fffe128, + (q31_t)0x404b65e1, (q31_t)0x3fffd396, (q31_t)0x4057f6d4, (q31_t)0x3fffc38c, + (q31_t)0x406487c4, (q31_t)0x3fffb10b, (q31_t)0x407118b0, (q31_t)0x3fff9c12, + (q31_t)0x407da998, (q31_t)0x3fff84a1, (q31_t)0x408a3a7b, (q31_t)0x3fff6ab9, + (q31_t)0x4096cb58, (q31_t)0x3fff4e59, (q31_t)0x40a35c30, (q31_t)0x3fff2f82, + (q31_t)0x40afed02, (q31_t)0x3fff0e32, (q31_t)0x40bc7dcc, (q31_t)0x3ffeea6c, + (q31_t)0x40c90e90, (q31_t)0x3ffec42d, (q31_t)0x40d59f4c, (q31_t)0x3ffe9b77, + (q31_t)0x40e22fff, (q31_t)0x3ffe704a, (q31_t)0x40eec0aa, (q31_t)0x3ffe42a4, + (q31_t)0x40fb514b, (q31_t)0x3ffe1288, (q31_t)0x4107e1e3, (q31_t)0x3ffddff3, + (q31_t)0x41147271, (q31_t)0x3ffdaae7, (q31_t)0x412102f4, (q31_t)0x3ffd7364, + (q31_t)0x412d936c, (q31_t)0x3ffd3969, (q31_t)0x413a23d8, (q31_t)0x3ffcfcf6, + (q31_t)0x4146b438, (q31_t)0x3ffcbe0c, (q31_t)0x4153448c, (q31_t)0x3ffc7caa, + (q31_t)0x415fd4d2, (q31_t)0x3ffc38d1, (q31_t)0x416c650b, (q31_t)0x3ffbf280, + (q31_t)0x4178f536, (q31_t)0x3ffba9b8, (q31_t)0x41858552, (q31_t)0x3ffb5e78, + (q31_t)0x4192155f, (q31_t)0x3ffb10c1, (q31_t)0x419ea55d, (q31_t)0x3ffac092, + (q31_t)0x41ab354b, (q31_t)0x3ffa6dec, (q31_t)0x41b7c528, (q31_t)0x3ffa18cf, + (q31_t)0x41c454f5, (q31_t)0x3ff9c13a, (q31_t)0x41d0e4b0, (q31_t)0x3ff9672d, + (q31_t)0x41dd7459, (q31_t)0x3ff90aaa, (q31_t)0x41ea03ef, (q31_t)0x3ff8abae, + (q31_t)0x41f69373, (q31_t)0x3ff84a3c, (q31_t)0x420322e3, (q31_t)0x3ff7e652, + (q31_t)0x420fb240, (q31_t)0x3ff77ff1, (q31_t)0x421c4188, (q31_t)0x3ff71718, + (q31_t)0x4228d0bb, (q31_t)0x3ff6abc8, (q31_t)0x42355fd9, (q31_t)0x3ff63e01, + (q31_t)0x4241eee2, (q31_t)0x3ff5cdc3, (q31_t)0x424e7dd4, (q31_t)0x3ff55b0d, + (q31_t)0x425b0caf, (q31_t)0x3ff4e5e0, (q31_t)0x42679b73, (q31_t)0x3ff46e3c, + (q31_t)0x42742a1f, (q31_t)0x3ff3f420, (q31_t)0x4280b8b3, (q31_t)0x3ff3778e, + (q31_t)0x428d472e, (q31_t)0x3ff2f884, (q31_t)0x4299d590, (q31_t)0x3ff27703, + (q31_t)0x42a663d8, (q31_t)0x3ff1f30b, (q31_t)0x42b2f207, (q31_t)0x3ff16c9c, + (q31_t)0x42bf801a, (q31_t)0x3ff0e3b6, (q31_t)0x42cc0e13, (q31_t)0x3ff05858, + (q31_t)0x42d89bf0, (q31_t)0x3fefca84, (q31_t)0x42e529b0, (q31_t)0x3fef3a39, + (q31_t)0x42f1b755, (q31_t)0x3feea776, (q31_t)0x42fe44dc, (q31_t)0x3fee123d, + (q31_t)0x430ad245, (q31_t)0x3fed7a8c, (q31_t)0x43175f91, (q31_t)0x3fece065, + (q31_t)0x4323ecbe, (q31_t)0x3fec43c7, (q31_t)0x433079cc, (q31_t)0x3feba4b2, + (q31_t)0x433d06bb, (q31_t)0x3feb0326, (q31_t)0x43499389, (q31_t)0x3fea5f23, + (q31_t)0x43562038, (q31_t)0x3fe9b8a9, (q31_t)0x4362acc5, (q31_t)0x3fe90fb9, + (q31_t)0x436f3931, (q31_t)0x3fe86452, (q31_t)0x437bc57b, (q31_t)0x3fe7b674, + (q31_t)0x438851a2, (q31_t)0x3fe7061f, (q31_t)0x4394dda7, (q31_t)0x3fe65354, + (q31_t)0x43a16988, (q31_t)0x3fe59e12, (q31_t)0x43adf546, (q31_t)0x3fe4e659, + (q31_t)0x43ba80df, (q31_t)0x3fe42c2a, (q31_t)0x43c70c54, (q31_t)0x3fe36f84, + (q31_t)0x43d397a3, (q31_t)0x3fe2b067, (q31_t)0x43e022cc, (q31_t)0x3fe1eed5, + (q31_t)0x43ecadcf, (q31_t)0x3fe12acb, (q31_t)0x43f938ac, (q31_t)0x3fe0644b, + (q31_t)0x4405c361, (q31_t)0x3fdf9b55, (q31_t)0x44124dee, (q31_t)0x3fdecfe8, + (q31_t)0x441ed854, (q31_t)0x3fde0205, (q31_t)0x442b6290, (q31_t)0x3fdd31ac, + (q31_t)0x4437eca4, (q31_t)0x3fdc5edc, (q31_t)0x4444768d, (q31_t)0x3fdb8996, + (q31_t)0x4451004d, (q31_t)0x3fdab1d9, (q31_t)0x445d89e2, (q31_t)0x3fd9d7a7, + (q31_t)0x446a134c, (q31_t)0x3fd8fafe, (q31_t)0x44769c8b, (q31_t)0x3fd81bdf, + (q31_t)0x4483259d, (q31_t)0x3fd73a4a, (q31_t)0x448fae83, (q31_t)0x3fd6563f, + (q31_t)0x449c373c, (q31_t)0x3fd56fbe, (q31_t)0x44a8bfc7, (q31_t)0x3fd486c7, + (q31_t)0x44b54825, (q31_t)0x3fd39b5a, (q31_t)0x44c1d054, (q31_t)0x3fd2ad77, + (q31_t)0x44ce5854, (q31_t)0x3fd1bd1e, (q31_t)0x44dae024, (q31_t)0x3fd0ca4f, + (q31_t)0x44e767c5, (q31_t)0x3fcfd50b, (q31_t)0x44f3ef35, (q31_t)0x3fcedd50, + (q31_t)0x45007674, (q31_t)0x3fcde320, (q31_t)0x450cfd82, (q31_t)0x3fcce67a, + (q31_t)0x4519845e, (q31_t)0x3fcbe75e, (q31_t)0x45260b08, (q31_t)0x3fcae5cd, + (q31_t)0x4532917f, (q31_t)0x3fc9e1c6, (q31_t)0x453f17c3, (q31_t)0x3fc8db4a, + (q31_t)0x454b9dd3, (q31_t)0x3fc7d258, (q31_t)0x455823ae, (q31_t)0x3fc6c6f0, + (q31_t)0x4564a955, (q31_t)0x3fc5b913, (q31_t)0x45712ec7, (q31_t)0x3fc4a8c1, + (q31_t)0x457db403, (q31_t)0x3fc395f9, (q31_t)0x458a3908, (q31_t)0x3fc280bc, + (q31_t)0x4596bdd7, (q31_t)0x3fc1690a, (q31_t)0x45a3426f, (q31_t)0x3fc04ee3, + (q31_t)0x45afc6d0, (q31_t)0x3fbf3246, (q31_t)0x45bc4af8, (q31_t)0x3fbe1334, + (q31_t)0x45c8cee7, (q31_t)0x3fbcf1ad, (q31_t)0x45d5529e, (q31_t)0x3fbbcdb1, + (q31_t)0x45e1d61b, (q31_t)0x3fbaa740, (q31_t)0x45ee595d, (q31_t)0x3fb97e5a, + (q31_t)0x45fadc66, (q31_t)0x3fb852ff, (q31_t)0x46075f33, (q31_t)0x3fb7252f, + (q31_t)0x4613e1c5, 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(q31_t)0x4596bdd7, (q31_t)0xc03e96f6, (q31_t)0x458a3908, (q31_t)0xc03d7f44, + (q31_t)0x457db403, (q31_t)0xc03c6a07, (q31_t)0x45712ec7, (q31_t)0xc03b573f, + (q31_t)0x4564a955, (q31_t)0xc03a46ed, (q31_t)0x455823ae, (q31_t)0xc0393910, + (q31_t)0x454b9dd3, (q31_t)0xc0382da8, (q31_t)0x453f17c3, (q31_t)0xc03724b6, + (q31_t)0x4532917f, (q31_t)0xc0361e3a, (q31_t)0x45260b08, (q31_t)0xc0351a33, + (q31_t)0x4519845e, (q31_t)0xc03418a2, (q31_t)0x450cfd82, (q31_t)0xc0331986, + (q31_t)0x45007674, (q31_t)0xc0321ce0, (q31_t)0x44f3ef35, (q31_t)0xc03122b0, + (q31_t)0x44e767c5, (q31_t)0xc0302af5, (q31_t)0x44dae024, (q31_t)0xc02f35b1, + (q31_t)0x44ce5854, (q31_t)0xc02e42e2, (q31_t)0x44c1d054, (q31_t)0xc02d5289, + (q31_t)0x44b54825, (q31_t)0xc02c64a6, (q31_t)0x44a8bfc7, (q31_t)0xc02b7939, + (q31_t)0x449c373c, (q31_t)0xc02a9042, (q31_t)0x448fae83, (q31_t)0xc029a9c1, + (q31_t)0x4483259d, (q31_t)0xc028c5b6, (q31_t)0x44769c8b, (q31_t)0xc027e421, + (q31_t)0x446a134c, (q31_t)0xc0270502, (q31_t)0x445d89e2, (q31_t)0xc0262859, + (q31_t)0x4451004d, (q31_t)0xc0254e27, (q31_t)0x4444768d, (q31_t)0xc024766a, + (q31_t)0x4437eca4, (q31_t)0xc023a124, (q31_t)0x442b6290, (q31_t)0xc022ce54, + (q31_t)0x441ed854, (q31_t)0xc021fdfb, (q31_t)0x44124dee, (q31_t)0xc0213018, + (q31_t)0x4405c361, (q31_t)0xc02064ab, (q31_t)0x43f938ac, (q31_t)0xc01f9bb5, + (q31_t)0x43ecadcf, (q31_t)0xc01ed535, (q31_t)0x43e022cc, (q31_t)0xc01e112b, + (q31_t)0x43d397a3, (q31_t)0xc01d4f99, (q31_t)0x43c70c54, (q31_t)0xc01c907c, + (q31_t)0x43ba80df, (q31_t)0xc01bd3d6, (q31_t)0x43adf546, (q31_t)0xc01b19a7, + (q31_t)0x43a16988, (q31_t)0xc01a61ee, (q31_t)0x4394dda7, (q31_t)0xc019acac, + (q31_t)0x438851a2, (q31_t)0xc018f9e1, (q31_t)0x437bc57b, (q31_t)0xc018498c, + (q31_t)0x436f3931, (q31_t)0xc0179bae, (q31_t)0x4362acc5, (q31_t)0xc016f047, + (q31_t)0x43562038, (q31_t)0xc0164757, (q31_t)0x43499389, (q31_t)0xc015a0dd, + (q31_t)0x433d06bb, (q31_t)0xc014fcda, (q31_t)0x433079cc, (q31_t)0xc0145b4e, + (q31_t)0x4323ecbe, (q31_t)0xc013bc39, (q31_t)0x43175f91, (q31_t)0xc0131f9b, + (q31_t)0x430ad245, (q31_t)0xc0128574, (q31_t)0x42fe44dc, (q31_t)0xc011edc3, + (q31_t)0x42f1b755, (q31_t)0xc011588a, (q31_t)0x42e529b0, (q31_t)0xc010c5c7, + (q31_t)0x42d89bf0, (q31_t)0xc010357c, (q31_t)0x42cc0e13, (q31_t)0xc00fa7a8, + (q31_t)0x42bf801a, (q31_t)0xc00f1c4a, (q31_t)0x42b2f207, (q31_t)0xc00e9364, + (q31_t)0x42a663d8, (q31_t)0xc00e0cf5, (q31_t)0x4299d590, (q31_t)0xc00d88fd, + (q31_t)0x428d472e, (q31_t)0xc00d077c, (q31_t)0x4280b8b3, (q31_t)0xc00c8872, + (q31_t)0x42742a1f, (q31_t)0xc00c0be0, (q31_t)0x42679b73, (q31_t)0xc00b91c4, + (q31_t)0x425b0caf, (q31_t)0xc00b1a20, (q31_t)0x424e7dd4, (q31_t)0xc00aa4f3, + (q31_t)0x4241eee2, (q31_t)0xc00a323d, (q31_t)0x42355fd9, (q31_t)0xc009c1ff, + (q31_t)0x4228d0bb, (q31_t)0xc0095438, (q31_t)0x421c4188, (q31_t)0xc008e8e8, + (q31_t)0x420fb240, (q31_t)0xc008800f, (q31_t)0x420322e3, (q31_t)0xc00819ae, + (q31_t)0x41f69373, (q31_t)0xc007b5c4, (q31_t)0x41ea03ef, (q31_t)0xc0075452, + (q31_t)0x41dd7459, (q31_t)0xc006f556, (q31_t)0x41d0e4b0, (q31_t)0xc00698d3, + (q31_t)0x41c454f5, (q31_t)0xc0063ec6, (q31_t)0x41b7c528, (q31_t)0xc005e731, + (q31_t)0x41ab354b, (q31_t)0xc0059214, (q31_t)0x419ea55d, (q31_t)0xc0053f6e, + (q31_t)0x4192155f, (q31_t)0xc004ef3f, (q31_t)0x41858552, (q31_t)0xc004a188, + (q31_t)0x4178f536, (q31_t)0xc0045648, (q31_t)0x416c650b, (q31_t)0xc0040d80, + (q31_t)0x415fd4d2, (q31_t)0xc003c72f, (q31_t)0x4153448c, (q31_t)0xc0038356, + (q31_t)0x4146b438, (q31_t)0xc00341f4, (q31_t)0x413a23d8, (q31_t)0xc003030a, + (q31_t)0x412d936c, (q31_t)0xc002c697, (q31_t)0x412102f4, (q31_t)0xc0028c9c, + (q31_t)0x41147271, (q31_t)0xc0025519, (q31_t)0x4107e1e3, (q31_t)0xc002200d, + (q31_t)0x40fb514b, (q31_t)0xc001ed78, (q31_t)0x40eec0aa, (q31_t)0xc001bd5c, + (q31_t)0x40e22fff, (q31_t)0xc0018fb6, (q31_t)0x40d59f4c, (q31_t)0xc0016489, + (q31_t)0x40c90e90, (q31_t)0xc0013bd3, (q31_t)0x40bc7dcc, (q31_t)0xc0011594, + (q31_t)0x40afed02, (q31_t)0xc000f1ce, (q31_t)0x40a35c30, (q31_t)0xc000d07e, + (q31_t)0x4096cb58, (q31_t)0xc000b1a7, (q31_t)0x408a3a7b, (q31_t)0xc0009547, + (q31_t)0x407da998, (q31_t)0xc0007b5f, (q31_t)0x407118b0, (q31_t)0xc00063ee, + (q31_t)0x406487c4, (q31_t)0xc0004ef5, (q31_t)0x4057f6d4, (q31_t)0xc0003c74, + (q31_t)0x404b65e1, (q31_t)0xc0002c6a, (q31_t)0x403ed4ea, (q31_t)0xc0001ed8, + (q31_t)0x403243f1, (q31_t)0xc00013bd, (q31_t)0x4025b2f7, (q31_t)0xc0000b1a, + (q31_t)0x401921fb, (q31_t)0xc00004ef, (q31_t)0x400c90fe, (q31_t)0xc000013c, +}; +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_REALCOEF_Q15) +/** + @par + Generation fixed-point realCoefAQ15 array in Q15 format: + @par + n = 4096 + 
for (i = 0; i < n; i++)
+  {
+     pATable[2 * i]     = 0.5 * ( 1.0 - sin (2 * PI / (double) (2 * n) * (double) i));
+     pATable[2 * i + 1] = 0.5 * (-1.0 * cos (2 * PI / (double) (2 * n) * (double) i));
+  }
+ @par + Convert to fixed point Q15 format + round(pATable[i] * pow(2, 15)) + */ +const q15_t __ALIGNED(4) realCoefAQ15[8192] = { + (q15_t)0x4000, (q15_t)0xc000, (q15_t)0x3ff3, (q15_t)0xc000, (q15_t)0x3fe7, (q15_t)0xc000, (q15_t)0x3fda, (q15_t)0xc000, + (q15_t)0x3fce, (q15_t)0xc000, (q15_t)0x3fc1, (q15_t)0xc000, (q15_t)0x3fb5, (q15_t)0xc000, (q15_t)0x3fa8, (q15_t)0xc000, + (q15_t)0x3f9b, (q15_t)0xc000, (q15_t)0x3f8f, (q15_t)0xc000, (q15_t)0x3f82, (q15_t)0xc000, (q15_t)0x3f76, (q15_t)0xc001, + (q15_t)0x3f69, (q15_t)0xc001, (q15_t)0x3f5d, (q15_t)0xc001, (q15_t)0x3f50, (q15_t)0xc001, (q15_t)0x3f44, (q15_t)0xc001, + (q15_t)0x3f37, (q15_t)0xc001, (q15_t)0x3f2a, (q15_t)0xc001, (q15_t)0x3f1e, (q15_t)0xc002, (q15_t)0x3f11, (q15_t)0xc002, + (q15_t)0x3f05, (q15_t)0xc002, (q15_t)0x3ef8, (q15_t)0xc002, (q15_t)0x3eec, (q15_t)0xc002, (q15_t)0x3edf, (q15_t)0xc003, + (q15_t)0x3ed2, (q15_t)0xc003, (q15_t)0x3ec6, (q15_t)0xc003, (q15_t)0x3eb9, (q15_t)0xc003, (q15_t)0x3ead, (q15_t)0xc004, + (q15_t)0x3ea0, (q15_t)0xc004, (q15_t)0x3e94, (q15_t)0xc004, (q15_t)0x3e87, (q15_t)0xc004, (q15_t)0x3e7a, (q15_t)0xc005, + (q15_t)0x3e6e, (q15_t)0xc005, (q15_t)0x3e61, (q15_t)0xc005, (q15_t)0x3e55, (q15_t)0xc006, (q15_t)0x3e48, (q15_t)0xc006, + (q15_t)0x3e3c, (q15_t)0xc006, (q15_t)0x3e2f, (q15_t)0xc007, (q15_t)0x3e23, (q15_t)0xc007, (q15_t)0x3e16, (q15_t)0xc007, + (q15_t)0x3e09, (q15_t)0xc008, (q15_t)0x3dfd, (q15_t)0xc008, (q15_t)0x3df0, (q15_t)0xc009, (q15_t)0x3de4, (q15_t)0xc009, + (q15_t)0x3dd7, (q15_t)0xc009, (q15_t)0x3dcb, (q15_t)0xc00a, (q15_t)0x3dbe, (q15_t)0xc00a, (q15_t)0x3db2, (q15_t)0xc00b, + (q15_t)0x3da5, (q15_t)0xc00b, (q15_t)0x3d98, (q15_t)0xc00c, (q15_t)0x3d8c, (q15_t)0xc00c, (q15_t)0x3d7f, (q15_t)0xc00d, + (q15_t)0x3d73, (q15_t)0xc00d, (q15_t)0x3d66, (q15_t)0xc00e, (q15_t)0x3d5a, (q15_t)0xc00e, (q15_t)0x3d4d, (q15_t)0xc00f, + (q15_t)0x3d40, (q15_t)0xc00f, (q15_t)0x3d34, (q15_t)0xc010, (q15_t)0x3d27, (q15_t)0xc010, (q15_t)0x3d1b, (q15_t)0xc011, + (q15_t)0x3d0e, (q15_t)0xc011, (q15_t)0x3d02, (q15_t)0xc012, (q15_t)0x3cf5, (q15_t)0xc013, (q15_t)0x3ce9, (q15_t)0xc013, + (q15_t)0x3cdc, (q15_t)0xc014, (q15_t)0x3cd0, (q15_t)0xc014, (q15_t)0x3cc3, (q15_t)0xc015, (q15_t)0x3cb6, (q15_t)0xc016, + (q15_t)0x3caa, (q15_t)0xc016, (q15_t)0x3c9d, (q15_t)0xc017, (q15_t)0x3c91, (q15_t)0xc018, (q15_t)0x3c84, (q15_t)0xc018, + (q15_t)0x3c78, (q15_t)0xc019, (q15_t)0x3c6b, (q15_t)0xc01a, (q15_t)0x3c5f, (q15_t)0xc01a, (q15_t)0x3c52, (q15_t)0xc01b, + (q15_t)0x3c45, (q15_t)0xc01c, (q15_t)0x3c39, (q15_t)0xc01d, (q15_t)0x3c2c, (q15_t)0xc01d, (q15_t)0x3c20, (q15_t)0xc01e, + (q15_t)0x3c13, (q15_t)0xc01f, (q15_t)0x3c07, (q15_t)0xc020, (q15_t)0x3bfa, (q15_t)0xc020, (q15_t)0x3bee, (q15_t)0xc021, + (q15_t)0x3be1, (q15_t)0xc022, (q15_t)0x3bd5, (q15_t)0xc023, (q15_t)0x3bc8, (q15_t)0xc024, (q15_t)0x3bbc, (q15_t)0xc024, + (q15_t)0x3baf, (q15_t)0xc025, (q15_t)0x3ba2, (q15_t)0xc026, (q15_t)0x3b96, (q15_t)0xc027, (q15_t)0x3b89, (q15_t)0xc028, + (q15_t)0x3b7d, (q15_t)0xc029, (q15_t)0x3b70, (q15_t)0xc02a, (q15_t)0x3b64, (q15_t)0xc02b, (q15_t)0x3b57, (q15_t)0xc02b, + (q15_t)0x3b4b, (q15_t)0xc02c, (q15_t)0x3b3e, (q15_t)0xc02d, (q15_t)0x3b32, (q15_t)0xc02e, (q15_t)0x3b25, (q15_t)0xc02f, + (q15_t)0x3b19, (q15_t)0xc030, (q15_t)0x3b0c, (q15_t)0xc031, (q15_t)0x3b00, (q15_t)0xc032, (q15_t)0x3af3, (q15_t)0xc033, + (q15_t)0x3ae6, (q15_t)0xc034, (q15_t)0x3ada, (q15_t)0xc035, (q15_t)0x3acd, (q15_t)0xc036, (q15_t)0x3ac1, (q15_t)0xc037, + (q15_t)0x3ab4, (q15_t)0xc038, (q15_t)0x3aa8, (q15_t)0xc039, (q15_t)0x3a9b, (q15_t)0xc03a, (q15_t)0x3a8f, (q15_t)0xc03b, + (q15_t)0x3a82, (q15_t)0xc03c, (q15_t)0x3a76, (q15_t)0xc03d, (q15_t)0x3a69, (q15_t)0xc03f, (q15_t)0x3a5d, (q15_t)0xc040, + (q15_t)0x3a50, (q15_t)0xc041, (q15_t)0x3a44, (q15_t)0xc042, (q15_t)0x3a37, (q15_t)0xc043, (q15_t)0x3a2b, (q15_t)0xc044, + (q15_t)0x3a1e, (q15_t)0xc045, (q15_t)0x3a12, (q15_t)0xc047, (q15_t)0x3a05, (q15_t)0xc048, (q15_t)0x39f9, (q15_t)0xc049, + (q15_t)0x39ec, (q15_t)0xc04a, (q15_t)0x39e0, (q15_t)0xc04b, (q15_t)0x39d3, (q15_t)0xc04c, (q15_t)0x39c7, (q15_t)0xc04e, + (q15_t)0x39ba, (q15_t)0xc04f, (q15_t)0x39ae, (q15_t)0xc050, (q15_t)0x39a1, (q15_t)0xc051, (q15_t)0x3995, (q15_t)0xc053, + (q15_t)0x3988, (q15_t)0xc054, (q15_t)0x397c, (q15_t)0xc055, (q15_t)0x396f, (q15_t)0xc056, (q15_t)0x3963, (q15_t)0xc058, + (q15_t)0x3956, (q15_t)0xc059, (q15_t)0x394a, (q15_t)0xc05a, (q15_t)0x393d, (q15_t)0xc05c, (q15_t)0x3931, (q15_t)0xc05d, + (q15_t)0x3924, (q15_t)0xc05e, (q15_t)0x3918, (q15_t)0xc060, (q15_t)0x390b, (q15_t)0xc061, (q15_t)0x38ff, (q15_t)0xc062, + (q15_t)0x38f2, (q15_t)0xc064, (q15_t)0x38e6, (q15_t)0xc065, (q15_t)0x38d9, (q15_t)0xc067, (q15_t)0x38cd, (q15_t)0xc068, + (q15_t)0x38c0, (q15_t)0xc069, (q15_t)0x38b4, (q15_t)0xc06b, (q15_t)0x38a7, (q15_t)0xc06c, (q15_t)0x389b, (q15_t)0xc06e, + (q15_t)0x388e, (q15_t)0xc06f, (q15_t)0x3882, (q15_t)0xc071, (q15_t)0x3875, (q15_t)0xc072, (q15_t)0x3869, (q15_t)0xc074, + (q15_t)0x385c, (q15_t)0xc075, (q15_t)0x3850, (q15_t)0xc077, (q15_t)0x3843, (q15_t)0xc078, (q15_t)0x3837, (q15_t)0xc07a, + (q15_t)0x382a, (q15_t)0xc07b, (q15_t)0x381e, (q15_t)0xc07d, (q15_t)0x3811, (q15_t)0xc07e, (q15_t)0x3805, (q15_t)0xc080, + (q15_t)0x37f9, (q15_t)0xc081, (q15_t)0x37ec, (q15_t)0xc083, (q15_t)0x37e0, (q15_t)0xc085, (q15_t)0x37d3, (q15_t)0xc086, + (q15_t)0x37c7, (q15_t)0xc088, (q15_t)0x37ba, (q15_t)0xc089, (q15_t)0x37ae, (q15_t)0xc08b, (q15_t)0x37a1, (q15_t)0xc08d, + (q15_t)0x3795, (q15_t)0xc08e, (q15_t)0x3788, (q15_t)0xc090, (q15_t)0x377c, (q15_t)0xc092, (q15_t)0x376f, (q15_t)0xc093, + (q15_t)0x3763, (q15_t)0xc095, (q15_t)0x3757, (q15_t)0xc097, (q15_t)0x374a, (q15_t)0xc098, (q15_t)0x373e, (q15_t)0xc09a, + (q15_t)0x3731, (q15_t)0xc09c, (q15_t)0x3725, (q15_t)0xc09e, (q15_t)0x3718, (q15_t)0xc09f, (q15_t)0x370c, (q15_t)0xc0a1, + (q15_t)0x36ff, (q15_t)0xc0a3, (q15_t)0x36f3, (q15_t)0xc0a5, (q15_t)0x36e7, (q15_t)0xc0a6, (q15_t)0x36da, (q15_t)0xc0a8, + (q15_t)0x36ce, (q15_t)0xc0aa, (q15_t)0x36c1, (q15_t)0xc0ac, (q15_t)0x36b5, (q15_t)0xc0ae, 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(q15_t)0x3fc6, (q15_t)0x3aa8, (q15_t)0x3fc7, + (q15_t)0x3ab4, (q15_t)0x3fc8, (q15_t)0x3ac1, (q15_t)0x3fc9, (q15_t)0x3acd, (q15_t)0x3fca, (q15_t)0x3ada, (q15_t)0x3fcb, + (q15_t)0x3ae6, (q15_t)0x3fcc, (q15_t)0x3af3, (q15_t)0x3fcd, (q15_t)0x3b00, (q15_t)0x3fce, (q15_t)0x3b0c, (q15_t)0x3fcf, + (q15_t)0x3b19, (q15_t)0x3fd0, (q15_t)0x3b25, (q15_t)0x3fd1, (q15_t)0x3b32, (q15_t)0x3fd2, (q15_t)0x3b3e, (q15_t)0x3fd3, + (q15_t)0x3b4b, (q15_t)0x3fd4, (q15_t)0x3b57, (q15_t)0x3fd5, (q15_t)0x3b64, (q15_t)0x3fd5, (q15_t)0x3b70, (q15_t)0x3fd6, + (q15_t)0x3b7d, (q15_t)0x3fd7, (q15_t)0x3b89, (q15_t)0x3fd8, (q15_t)0x3b96, (q15_t)0x3fd9, (q15_t)0x3ba2, (q15_t)0x3fda, + (q15_t)0x3baf, (q15_t)0x3fdb, (q15_t)0x3bbc, (q15_t)0x3fdc, (q15_t)0x3bc8, (q15_t)0x3fdc, (q15_t)0x3bd5, (q15_t)0x3fdd, + (q15_t)0x3be1, (q15_t)0x3fde, (q15_t)0x3bee, (q15_t)0x3fdf, (q15_t)0x3bfa, (q15_t)0x3fe0, (q15_t)0x3c07, (q15_t)0x3fe0, + (q15_t)0x3c13, (q15_t)0x3fe1, (q15_t)0x3c20, (q15_t)0x3fe2, (q15_t)0x3c2c, (q15_t)0x3fe3, (q15_t)0x3c39, (q15_t)0x3fe3, + (q15_t)0x3c45, (q15_t)0x3fe4, (q15_t)0x3c52, (q15_t)0x3fe5, (q15_t)0x3c5f, (q15_t)0x3fe6, (q15_t)0x3c6b, (q15_t)0x3fe6, + (q15_t)0x3c78, (q15_t)0x3fe7, (q15_t)0x3c84, (q15_t)0x3fe8, (q15_t)0x3c91, (q15_t)0x3fe8, (q15_t)0x3c9d, (q15_t)0x3fe9, + (q15_t)0x3caa, (q15_t)0x3fea, (q15_t)0x3cb6, (q15_t)0x3fea, (q15_t)0x3cc3, (q15_t)0x3feb, (q15_t)0x3cd0, (q15_t)0x3fec, + (q15_t)0x3cdc, (q15_t)0x3fec, (q15_t)0x3ce9, (q15_t)0x3fed, (q15_t)0x3cf5, (q15_t)0x3fed, (q15_t)0x3d02, (q15_t)0x3fee, + (q15_t)0x3d0e, (q15_t)0x3fef, (q15_t)0x3d1b, (q15_t)0x3fef, (q15_t)0x3d27, (q15_t)0x3ff0, (q15_t)0x3d34, (q15_t)0x3ff0, + (q15_t)0x3d40, (q15_t)0x3ff1, (q15_t)0x3d4d, (q15_t)0x3ff1, (q15_t)0x3d5a, (q15_t)0x3ff2, (q15_t)0x3d66, (q15_t)0x3ff2, + (q15_t)0x3d73, (q15_t)0x3ff3, (q15_t)0x3d7f, (q15_t)0x3ff3, (q15_t)0x3d8c, (q15_t)0x3ff4, (q15_t)0x3d98, (q15_t)0x3ff4, + (q15_t)0x3da5, (q15_t)0x3ff5, (q15_t)0x3db2, (q15_t)0x3ff5, (q15_t)0x3dbe, (q15_t)0x3ff6, (q15_t)0x3dcb, (q15_t)0x3ff6, + (q15_t)0x3dd7, (q15_t)0x3ff7, (q15_t)0x3de4, (q15_t)0x3ff7, (q15_t)0x3df0, (q15_t)0x3ff7, (q15_t)0x3dfd, (q15_t)0x3ff8, + (q15_t)0x3e09, (q15_t)0x3ff8, (q15_t)0x3e16, (q15_t)0x3ff9, (q15_t)0x3e23, (q15_t)0x3ff9, (q15_t)0x3e2f, (q15_t)0x3ff9, + (q15_t)0x3e3c, (q15_t)0x3ffa, (q15_t)0x3e48, (q15_t)0x3ffa, (q15_t)0x3e55, (q15_t)0x3ffa, (q15_t)0x3e61, (q15_t)0x3ffb, + (q15_t)0x3e6e, (q15_t)0x3ffb, (q15_t)0x3e7a, (q15_t)0x3ffb, (q15_t)0x3e87, (q15_t)0x3ffc, (q15_t)0x3e94, (q15_t)0x3ffc, + (q15_t)0x3ea0, (q15_t)0x3ffc, (q15_t)0x3ead, (q15_t)0x3ffc, (q15_t)0x3eb9, (q15_t)0x3ffd, (q15_t)0x3ec6, (q15_t)0x3ffd, + (q15_t)0x3ed2, (q15_t)0x3ffd, (q15_t)0x3edf, (q15_t)0x3ffd, (q15_t)0x3eec, (q15_t)0x3ffe, (q15_t)0x3ef8, (q15_t)0x3ffe, + (q15_t)0x3f05, (q15_t)0x3ffe, (q15_t)0x3f11, (q15_t)0x3ffe, (q15_t)0x3f1e, (q15_t)0x3ffe, (q15_t)0x3f2a, (q15_t)0x3fff, + (q15_t)0x3f37, (q15_t)0x3fff, (q15_t)0x3f44, (q15_t)0x3fff, (q15_t)0x3f50, (q15_t)0x3fff, (q15_t)0x3f5d, (q15_t)0x3fff, + (q15_t)0x3f69, (q15_t)0x3fff, (q15_t)0x3f76, (q15_t)0x3fff, (q15_t)0x3f82, (q15_t)0x4000, (q15_t)0x3f8f, (q15_t)0x4000, + (q15_t)0x3f9b, (q15_t)0x4000, (q15_t)0x3fa8, (q15_t)0x4000, (q15_t)0x3fb5, (q15_t)0x4000, (q15_t)0x3fc1, (q15_t)0x4000, + (q15_t)0x3fce, (q15_t)0x4000, (q15_t)0x3fda, (q15_t)0x4000, (q15_t)0x3fe7, (q15_t)0x4000, (q15_t)0x3ff3, (q15_t)0x4000, +}; + +/** + @par + Generation of real_CoefB array: + @par + n = 4096 + 
for (i = 0; i < n; i++)
+  {
+     pBTable[2 * i]     = 0.5 * (1.0 + sin (2 * PI / (double) (2 * n) * (double) i));
+     pBTable[2 * i + 1] = 0.5 * (1.0 * cos (2 * PI / (double) (2 * n) * (double) i));
+  }
+ @par + Convert to fixed point Q15 format + round(pBTable[i] * pow(2, 15)) +*/ +const q15_t __ALIGNED(4) realCoefBQ15[8192] = { + (q15_t)0x4000, (q15_t)0x4000, (q15_t)0x400d, (q15_t)0x4000, (q15_t)0x4019, (q15_t)0x4000, (q15_t)0x4026, (q15_t)0x4000, + (q15_t)0x4032, (q15_t)0x4000, (q15_t)0x403f, (q15_t)0x4000, (q15_t)0x404b, (q15_t)0x4000, (q15_t)0x4058, (q15_t)0x4000, + (q15_t)0x4065, (q15_t)0x4000, (q15_t)0x4071, (q15_t)0x4000, (q15_t)0x407e, (q15_t)0x4000, (q15_t)0x408a, (q15_t)0x3fff, + (q15_t)0x4097, (q15_t)0x3fff, (q15_t)0x40a3, (q15_t)0x3fff, (q15_t)0x40b0, (q15_t)0x3fff, (q15_t)0x40bc, (q15_t)0x3fff, + (q15_t)0x40c9, (q15_t)0x3fff, (q15_t)0x40d6, (q15_t)0x3fff, (q15_t)0x40e2, (q15_t)0x3ffe, (q15_t)0x40ef, (q15_t)0x3ffe, + (q15_t)0x40fb, (q15_t)0x3ffe, (q15_t)0x4108, (q15_t)0x3ffe, (q15_t)0x4114, (q15_t)0x3ffe, (q15_t)0x4121, (q15_t)0x3ffd, + (q15_t)0x412e, (q15_t)0x3ffd, (q15_t)0x413a, (q15_t)0x3ffd, (q15_t)0x4147, (q15_t)0x3ffd, (q15_t)0x4153, (q15_t)0x3ffc, + (q15_t)0x4160, (q15_t)0x3ffc, (q15_t)0x416c, (q15_t)0x3ffc, (q15_t)0x4179, (q15_t)0x3ffc, (q15_t)0x4186, (q15_t)0x3ffb, + (q15_t)0x4192, (q15_t)0x3ffb, (q15_t)0x419f, (q15_t)0x3ffb, (q15_t)0x41ab, (q15_t)0x3ffa, (q15_t)0x41b8, (q15_t)0x3ffa, + (q15_t)0x41c4, (q15_t)0x3ffa, (q15_t)0x41d1, (q15_t)0x3ff9, (q15_t)0x41dd, (q15_t)0x3ff9, (q15_t)0x41ea, (q15_t)0x3ff9, + (q15_t)0x41f7, (q15_t)0x3ff8, (q15_t)0x4203, (q15_t)0x3ff8, (q15_t)0x4210, (q15_t)0x3ff7, (q15_t)0x421c, (q15_t)0x3ff7, + (q15_t)0x4229, (q15_t)0x3ff7, (q15_t)0x4235, (q15_t)0x3ff6, (q15_t)0x4242, (q15_t)0x3ff6, (q15_t)0x424e, (q15_t)0x3ff5, + (q15_t)0x425b, (q15_t)0x3ff5, (q15_t)0x4268, (q15_t)0x3ff4, (q15_t)0x4274, (q15_t)0x3ff4, (q15_t)0x4281, (q15_t)0x3ff3, + (q15_t)0x428d, (q15_t)0x3ff3, (q15_t)0x429a, (q15_t)0x3ff2, (q15_t)0x42a6, (q15_t)0x3ff2, (q15_t)0x42b3, (q15_t)0x3ff1, + (q15_t)0x42c0, (q15_t)0x3ff1, (q15_t)0x42cc, (q15_t)0x3ff0, (q15_t)0x42d9, (q15_t)0x3ff0, (q15_t)0x42e5, (q15_t)0x3fef, + (q15_t)0x42f2, (q15_t)0x3fef, (q15_t)0x42fe, (q15_t)0x3fee, (q15_t)0x430b, (q15_t)0x3fed, (q15_t)0x4317, (q15_t)0x3fed, + (q15_t)0x4324, (q15_t)0x3fec, (q15_t)0x4330, (q15_t)0x3fec, (q15_t)0x433d, (q15_t)0x3feb, (q15_t)0x434a, (q15_t)0x3fea, + (q15_t)0x4356, (q15_t)0x3fea, (q15_t)0x4363, (q15_t)0x3fe9, (q15_t)0x436f, (q15_t)0x3fe8, (q15_t)0x437c, (q15_t)0x3fe8, + (q15_t)0x4388, (q15_t)0x3fe7, (q15_t)0x4395, (q15_t)0x3fe6, (q15_t)0x43a1, (q15_t)0x3fe6, (q15_t)0x43ae, (q15_t)0x3fe5, + (q15_t)0x43bb, (q15_t)0x3fe4, (q15_t)0x43c7, (q15_t)0x3fe3, (q15_t)0x43d4, (q15_t)0x3fe3, (q15_t)0x43e0, (q15_t)0x3fe2, + (q15_t)0x43ed, (q15_t)0x3fe1, (q15_t)0x43f9, (q15_t)0x3fe0, (q15_t)0x4406, (q15_t)0x3fe0, (q15_t)0x4412, (q15_t)0x3fdf, + (q15_t)0x441f, (q15_t)0x3fde, (q15_t)0x442b, (q15_t)0x3fdd, (q15_t)0x4438, (q15_t)0x3fdc, (q15_t)0x4444, (q15_t)0x3fdc, + (q15_t)0x4451, (q15_t)0x3fdb, (q15_t)0x445e, (q15_t)0x3fda, (q15_t)0x446a, (q15_t)0x3fd9, (q15_t)0x4477, (q15_t)0x3fd8, + (q15_t)0x4483, (q15_t)0x3fd7, (q15_t)0x4490, (q15_t)0x3fd6, (q15_t)0x449c, (q15_t)0x3fd5, (q15_t)0x44a9, (q15_t)0x3fd5, + (q15_t)0x44b5, (q15_t)0x3fd4, (q15_t)0x44c2, (q15_t)0x3fd3, (q15_t)0x44ce, (q15_t)0x3fd2, (q15_t)0x44db, (q15_t)0x3fd1, + (q15_t)0x44e7, (q15_t)0x3fd0, (q15_t)0x44f4, (q15_t)0x3fcf, (q15_t)0x4500, (q15_t)0x3fce, (q15_t)0x450d, (q15_t)0x3fcd, + (q15_t)0x451a, (q15_t)0x3fcc, (q15_t)0x4526, (q15_t)0x3fcb, (q15_t)0x4533, (q15_t)0x3fca, (q15_t)0x453f, (q15_t)0x3fc9, + (q15_t)0x454c, (q15_t)0x3fc8, (q15_t)0x4558, (q15_t)0x3fc7, (q15_t)0x4565, (q15_t)0x3fc6, (q15_t)0x4571, (q15_t)0x3fc5, + (q15_t)0x457e, (q15_t)0x3fc4, (q15_t)0x458a, (q15_t)0x3fc3, (q15_t)0x4597, (q15_t)0x3fc1, (q15_t)0x45a3, (q15_t)0x3fc0, + (q15_t)0x45b0, (q15_t)0x3fbf, (q15_t)0x45bc, (q15_t)0x3fbe, (q15_t)0x45c9, (q15_t)0x3fbd, (q15_t)0x45d5, (q15_t)0x3fbc, + (q15_t)0x45e2, (q15_t)0x3fbb, (q15_t)0x45ee, (q15_t)0x3fb9, (q15_t)0x45fb, (q15_t)0x3fb8, (q15_t)0x4607, (q15_t)0x3fb7, + (q15_t)0x4614, (q15_t)0x3fb6, (q15_t)0x4620, (q15_t)0x3fb5, (q15_t)0x462d, (q15_t)0x3fb4, (q15_t)0x4639, (q15_t)0x3fb2, + (q15_t)0x4646, (q15_t)0x3fb1, (q15_t)0x4652, (q15_t)0x3fb0, (q15_t)0x465f, (q15_t)0x3faf, (q15_t)0x466b, (q15_t)0x3fad, + (q15_t)0x4678, (q15_t)0x3fac, (q15_t)0x4684, (q15_t)0x3fab, (q15_t)0x4691, (q15_t)0x3faa, (q15_t)0x469d, (q15_t)0x3fa8, + (q15_t)0x46aa, (q15_t)0x3fa7, (q15_t)0x46b6, (q15_t)0x3fa6, (q15_t)0x46c3, (q15_t)0x3fa4, (q15_t)0x46cf, (q15_t)0x3fa3, + (q15_t)0x46dc, (q15_t)0x3fa2, (q15_t)0x46e8, (q15_t)0x3fa0, (q15_t)0x46f5, (q15_t)0x3f9f, (q15_t)0x4701, (q15_t)0x3f9e, + (q15_t)0x470e, (q15_t)0x3f9c, (q15_t)0x471a, (q15_t)0x3f9b, (q15_t)0x4727, (q15_t)0x3f99, (q15_t)0x4733, (q15_t)0x3f98, + (q15_t)0x4740, (q15_t)0x3f97, (q15_t)0x474c, (q15_t)0x3f95, (q15_t)0x4759, (q15_t)0x3f94, (q15_t)0x4765, (q15_t)0x3f92, + (q15_t)0x4772, (q15_t)0x3f91, (q15_t)0x477e, (q15_t)0x3f8f, (q15_t)0x478b, (q15_t)0x3f8e, (q15_t)0x4797, (q15_t)0x3f8c, + (q15_t)0x47a4, (q15_t)0x3f8b, (q15_t)0x47b0, (q15_t)0x3f89, (q15_t)0x47bd, (q15_t)0x3f88, (q15_t)0x47c9, (q15_t)0x3f86, + (q15_t)0x47d6, (q15_t)0x3f85, (q15_t)0x47e2, (q15_t)0x3f83, (q15_t)0x47ef, (q15_t)0x3f82, (q15_t)0x47fb, (q15_t)0x3f80, + (q15_t)0x4807, (q15_t)0x3f7f, (q15_t)0x4814, (q15_t)0x3f7d, (q15_t)0x4820, (q15_t)0x3f7b, (q15_t)0x482d, (q15_t)0x3f7a, + (q15_t)0x4839, (q15_t)0x3f78, (q15_t)0x4846, (q15_t)0x3f77, (q15_t)0x4852, (q15_t)0x3f75, (q15_t)0x485f, (q15_t)0x3f73, + (q15_t)0x486b, (q15_t)0x3f72, (q15_t)0x4878, (q15_t)0x3f70, (q15_t)0x4884, (q15_t)0x3f6e, (q15_t)0x4891, (q15_t)0x3f6d, + (q15_t)0x489d, (q15_t)0x3f6b, (q15_t)0x48a9, (q15_t)0x3f69, (q15_t)0x48b6, (q15_t)0x3f68, (q15_t)0x48c2, (q15_t)0x3f66, + (q15_t)0x48cf, (q15_t)0x3f64, (q15_t)0x48db, (q15_t)0x3f62, (q15_t)0x48e8, (q15_t)0x3f61, (q15_t)0x48f4, (q15_t)0x3f5f, + (q15_t)0x4901, (q15_t)0x3f5d, (q15_t)0x490d, (q15_t)0x3f5b, (q15_t)0x4919, (q15_t)0x3f5a, (q15_t)0x4926, (q15_t)0x3f58, + (q15_t)0x4932, (q15_t)0x3f56, (q15_t)0x493f, (q15_t)0x3f54, (q15_t)0x494b, (q15_t)0x3f52, (q15_t)0x4958, (q15_t)0x3f51, + (q15_t)0x4964, (q15_t)0x3f4f, (q15_t)0x4970, (q15_t)0x3f4d, (q15_t)0x497d, (q15_t)0x3f4b, (q15_t)0x4989, (q15_t)0x3f49, + (q15_t)0x4996, (q15_t)0x3f47, (q15_t)0x49a2, (q15_t)0x3f45, (q15_t)0x49af, (q15_t)0x3f43, (q15_t)0x49bb, (q15_t)0x3f42, + (q15_t)0x49c7, (q15_t)0x3f40, (q15_t)0x49d4, (q15_t)0x3f3e, (q15_t)0x49e0, (q15_t)0x3f3c, (q15_t)0x49ed, (q15_t)0x3f3a, + (q15_t)0x49f9, (q15_t)0x3f38, (q15_t)0x4a06, (q15_t)0x3f36, (q15_t)0x4a12, (q15_t)0x3f34, (q15_t)0x4a1e, (q15_t)0x3f32, + (q15_t)0x4a2b, (q15_t)0x3f30, (q15_t)0x4a37, (q15_t)0x3f2e, (q15_t)0x4a44, (q15_t)0x3f2c, (q15_t)0x4a50, (q15_t)0x3f2a, + (q15_t)0x4a5c, (q15_t)0x3f28, (q15_t)0x4a69, (q15_t)0x3f26, (q15_t)0x4a75, (q15_t)0x3f24, (q15_t)0x4a82, (q15_t)0x3f22, + (q15_t)0x4a8e, (q15_t)0x3f20, (q15_t)0x4a9a, (q15_t)0x3f1e, (q15_t)0x4aa7, (q15_t)0x3f1c, (q15_t)0x4ab3, (q15_t)0x3f19, + (q15_t)0x4ac0, (q15_t)0x3f17, (q15_t)0x4acc, (q15_t)0x3f15, (q15_t)0x4ad8, (q15_t)0x3f13, (q15_t)0x4ae5, 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(q15_t)0x493f, (q15_t)0xc0ac, + (q15_t)0x4932, (q15_t)0xc0aa, (q15_t)0x4926, (q15_t)0xc0a8, (q15_t)0x4919, (q15_t)0xc0a6, (q15_t)0x490d, (q15_t)0xc0a5, + (q15_t)0x4901, (q15_t)0xc0a3, (q15_t)0x48f4, (q15_t)0xc0a1, (q15_t)0x48e8, (q15_t)0xc09f, (q15_t)0x48db, (q15_t)0xc09e, + (q15_t)0x48cf, (q15_t)0xc09c, (q15_t)0x48c2, (q15_t)0xc09a, (q15_t)0x48b6, (q15_t)0xc098, (q15_t)0x48a9, (q15_t)0xc097, + (q15_t)0x489d, (q15_t)0xc095, (q15_t)0x4891, (q15_t)0xc093, (q15_t)0x4884, (q15_t)0xc092, (q15_t)0x4878, (q15_t)0xc090, + (q15_t)0x486b, (q15_t)0xc08e, (q15_t)0x485f, (q15_t)0xc08d, (q15_t)0x4852, (q15_t)0xc08b, (q15_t)0x4846, (q15_t)0xc089, + (q15_t)0x4839, (q15_t)0xc088, (q15_t)0x482d, (q15_t)0xc086, (q15_t)0x4820, (q15_t)0xc085, (q15_t)0x4814, (q15_t)0xc083, + (q15_t)0x4807, (q15_t)0xc081, (q15_t)0x47fb, (q15_t)0xc080, (q15_t)0x47ef, (q15_t)0xc07e, (q15_t)0x47e2, (q15_t)0xc07d, + (q15_t)0x47d6, (q15_t)0xc07b, (q15_t)0x47c9, (q15_t)0xc07a, (q15_t)0x47bd, (q15_t)0xc078, (q15_t)0x47b0, (q15_t)0xc077, + (q15_t)0x47a4, (q15_t)0xc075, (q15_t)0x4797, (q15_t)0xc074, (q15_t)0x478b, (q15_t)0xc072, (q15_t)0x477e, (q15_t)0xc071, + (q15_t)0x4772, (q15_t)0xc06f, (q15_t)0x4765, (q15_t)0xc06e, (q15_t)0x4759, (q15_t)0xc06c, (q15_t)0x474c, (q15_t)0xc06b, + (q15_t)0x4740, (q15_t)0xc069, (q15_t)0x4733, (q15_t)0xc068, (q15_t)0x4727, (q15_t)0xc067, (q15_t)0x471a, (q15_t)0xc065, + (q15_t)0x470e, (q15_t)0xc064, (q15_t)0x4701, (q15_t)0xc062, (q15_t)0x46f5, (q15_t)0xc061, (q15_t)0x46e8, (q15_t)0xc060, + (q15_t)0x46dc, (q15_t)0xc05e, (q15_t)0x46cf, (q15_t)0xc05d, (q15_t)0x46c3, (q15_t)0xc05c, (q15_t)0x46b6, (q15_t)0xc05a, + (q15_t)0x46aa, (q15_t)0xc059, (q15_t)0x469d, (q15_t)0xc058, (q15_t)0x4691, (q15_t)0xc056, (q15_t)0x4684, (q15_t)0xc055, + (q15_t)0x4678, (q15_t)0xc054, (q15_t)0x466b, (q15_t)0xc053, (q15_t)0x465f, (q15_t)0xc051, (q15_t)0x4652, (q15_t)0xc050, + (q15_t)0x4646, (q15_t)0xc04f, (q15_t)0x4639, (q15_t)0xc04e, (q15_t)0x462d, (q15_t)0xc04c, (q15_t)0x4620, (q15_t)0xc04b, + (q15_t)0x4614, (q15_t)0xc04a, (q15_t)0x4607, (q15_t)0xc049, (q15_t)0x45fb, (q15_t)0xc048, (q15_t)0x45ee, (q15_t)0xc047, + (q15_t)0x45e2, (q15_t)0xc045, (q15_t)0x45d5, (q15_t)0xc044, (q15_t)0x45c9, (q15_t)0xc043, (q15_t)0x45bc, (q15_t)0xc042, + (q15_t)0x45b0, (q15_t)0xc041, (q15_t)0x45a3, (q15_t)0xc040, (q15_t)0x4597, (q15_t)0xc03f, (q15_t)0x458a, (q15_t)0xc03d, + (q15_t)0x457e, (q15_t)0xc03c, (q15_t)0x4571, (q15_t)0xc03b, (q15_t)0x4565, (q15_t)0xc03a, (q15_t)0x4558, (q15_t)0xc039, + (q15_t)0x454c, (q15_t)0xc038, (q15_t)0x453f, (q15_t)0xc037, (q15_t)0x4533, (q15_t)0xc036, (q15_t)0x4526, (q15_t)0xc035, + (q15_t)0x451a, (q15_t)0xc034, (q15_t)0x450d, (q15_t)0xc033, (q15_t)0x4500, (q15_t)0xc032, (q15_t)0x44f4, (q15_t)0xc031, + (q15_t)0x44e7, (q15_t)0xc030, (q15_t)0x44db, (q15_t)0xc02f, (q15_t)0x44ce, (q15_t)0xc02e, (q15_t)0x44c2, (q15_t)0xc02d, + (q15_t)0x44b5, (q15_t)0xc02c, (q15_t)0x44a9, (q15_t)0xc02b, (q15_t)0x449c, (q15_t)0xc02b, (q15_t)0x4490, (q15_t)0xc02a, + (q15_t)0x4483, (q15_t)0xc029, (q15_t)0x4477, (q15_t)0xc028, (q15_t)0x446a, (q15_t)0xc027, (q15_t)0x445e, (q15_t)0xc026, + (q15_t)0x4451, (q15_t)0xc025, (q15_t)0x4444, (q15_t)0xc024, (q15_t)0x4438, (q15_t)0xc024, (q15_t)0x442b, (q15_t)0xc023, + (q15_t)0x441f, (q15_t)0xc022, (q15_t)0x4412, (q15_t)0xc021, (q15_t)0x4406, (q15_t)0xc020, (q15_t)0x43f9, (q15_t)0xc020, + (q15_t)0x43ed, (q15_t)0xc01f, (q15_t)0x43e0, (q15_t)0xc01e, (q15_t)0x43d4, (q15_t)0xc01d, (q15_t)0x43c7, (q15_t)0xc01d, + (q15_t)0x43bb, (q15_t)0xc01c, (q15_t)0x43ae, (q15_t)0xc01b, (q15_t)0x43a1, (q15_t)0xc01a, (q15_t)0x4395, (q15_t)0xc01a, + (q15_t)0x4388, (q15_t)0xc019, (q15_t)0x437c, (q15_t)0xc018, (q15_t)0x436f, (q15_t)0xc018, (q15_t)0x4363, (q15_t)0xc017, + (q15_t)0x4356, (q15_t)0xc016, (q15_t)0x434a, (q15_t)0xc016, (q15_t)0x433d, (q15_t)0xc015, (q15_t)0x4330, (q15_t)0xc014, + (q15_t)0x4324, (q15_t)0xc014, (q15_t)0x4317, (q15_t)0xc013, (q15_t)0x430b, (q15_t)0xc013, (q15_t)0x42fe, (q15_t)0xc012, + (q15_t)0x42f2, (q15_t)0xc011, (q15_t)0x42e5, (q15_t)0xc011, (q15_t)0x42d9, (q15_t)0xc010, (q15_t)0x42cc, (q15_t)0xc010, + (q15_t)0x42c0, (q15_t)0xc00f, (q15_t)0x42b3, (q15_t)0xc00f, (q15_t)0x42a6, (q15_t)0xc00e, (q15_t)0x429a, (q15_t)0xc00e, + (q15_t)0x428d, (q15_t)0xc00d, (q15_t)0x4281, (q15_t)0xc00d, (q15_t)0x4274, (q15_t)0xc00c, (q15_t)0x4268, (q15_t)0xc00c, + (q15_t)0x425b, (q15_t)0xc00b, (q15_t)0x424e, (q15_t)0xc00b, (q15_t)0x4242, (q15_t)0xc00a, (q15_t)0x4235, (q15_t)0xc00a, + (q15_t)0x4229, (q15_t)0xc009, (q15_t)0x421c, (q15_t)0xc009, (q15_t)0x4210, (q15_t)0xc009, (q15_t)0x4203, (q15_t)0xc008, + (q15_t)0x41f7, (q15_t)0xc008, (q15_t)0x41ea, (q15_t)0xc007, (q15_t)0x41dd, (q15_t)0xc007, (q15_t)0x41d1, (q15_t)0xc007, + (q15_t)0x41c4, (q15_t)0xc006, (q15_t)0x41b8, (q15_t)0xc006, (q15_t)0x41ab, (q15_t)0xc006, (q15_t)0x419f, (q15_t)0xc005, + (q15_t)0x4192, (q15_t)0xc005, (q15_t)0x4186, (q15_t)0xc005, (q15_t)0x4179, (q15_t)0xc004, (q15_t)0x416c, (q15_t)0xc004, + (q15_t)0x4160, (q15_t)0xc004, (q15_t)0x4153, (q15_t)0xc004, (q15_t)0x4147, (q15_t)0xc003, (q15_t)0x413a, (q15_t)0xc003, + (q15_t)0x412e, (q15_t)0xc003, (q15_t)0x4121, (q15_t)0xc003, (q15_t)0x4114, (q15_t)0xc002, (q15_t)0x4108, (q15_t)0xc002, + (q15_t)0x40fb, (q15_t)0xc002, (q15_t)0x40ef, (q15_t)0xc002, (q15_t)0x40e2, (q15_t)0xc002, (q15_t)0x40d6, (q15_t)0xc001, + (q15_t)0x40c9, (q15_t)0xc001, (q15_t)0x40bc, (q15_t)0xc001, (q15_t)0x40b0, (q15_t)0xc001, (q15_t)0x40a3, (q15_t)0xc001, + (q15_t)0x4097, (q15_t)0xc001, (q15_t)0x408a, (q15_t)0xc001, (q15_t)0x407e, (q15_t)0xc000, (q15_t)0x4071, (q15_t)0xc000, + (q15_t)0x4065, (q15_t)0xc000, (q15_t)0x4058, (q15_t)0xc000, (q15_t)0x404b, (q15_t)0xc000, (q15_t)0x403f, (q15_t)0xc000, + (q15_t)0x4032, (q15_t)0xc000, (q15_t)0x4026, (q15_t)0xc000, (q15_t)0x4019, (q15_t)0xc000, (q15_t)0x400d, (q15_t)0xc000, +}; + +#endif +/** + @} end of RealFFT_Table group + */ + +/** + @ingroup DCT4_IDCT4 + */ + +/** + @addtogroup DCT4_IDCT4_Table DCT Type IV Tables + @{ + */ + +/** + @brief Weights Table + */ + +/** + @par + Weights tables are generated using the formula : 
weights[n] = e^(-j*n*pi/(2*N))
+ @par + C command to generate the table + 
+  for(i = 0; i< N; i++)
+  {
+    weights[(2*i)]   =  cos (i*c);
+    weights[(2*i)+1] = -sin (i*c);
+  }
+ @par + where N is the Number of weights to be calculated and c is pi/(2*N) + @par + In the tables below the real and imaginary values are placed alternatively, hence the + array length is 2*N. + */ + + +/** + @par + cosFactor tables are generated using the formula : 
cos_factors[n] = 2 * cos((2n+1)*pi/(4*N))
+ @par + C command to generate the table + @par + 
 for(i = 0; i< N; i++)
+  {
+     cos_factors[i]= 2 * cos((2*i+1)*c/2);
+  }
+ @par + where N is the number of factors to generate and c is pi/(2*N) +*/ + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_DCT4_F32_128) + const float32_t Weights_128[256] = { + 1.000000000000000000f, 0.000000000000000000f, 0.999924701839144500f, -0.012271538285719925f, + 0.999698818696204250f, -0.024541228522912288f, 0.999322384588349540f, -0.036807222941358832f, + 0.998795456205172410f, -0.049067674327418015f, 0.998118112900149180f, -0.061320736302208578f, + 0.997290456678690210f, -0.073564563599667426f, 0.996312612182778000f, -0.085797312344439894f, + 0.995184726672196930f, -0.098017140329560604f, 0.993906970002356060f, -0.110222207293883060f, + 0.992479534598709970f, -0.122410675199216200f, 0.990902635427780010f, -0.134580708507126170f, + 0.989176509964781010f, -0.146730474455361750f, 0.987301418157858430f, -0.158858143333861450f, + 0.985277642388941220f, -0.170961888760301220f, 0.983105487431216290f, -0.183039887955140950f, + 0.980785280403230430f, -0.195090322016128250f, 0.978317370719627650f, -0.207111376192218560f, + 0.975702130038528570f, -0.219101240156869800f, 0.972939952205560180f, -0.231058108280671110f, + 0.970031253194543970f, -0.242980179903263870f, 0.966976471044852070f, -0.254865659604514570f, + 0.963776065795439840f, -0.266712757474898370f, 0.960430519415565790f, -0.278519689385053060f, + 0.956940335732208820f, -0.290284677254462330f, 0.953306040354193860f, -0.302005949319228080f, + 0.949528180593036670f, -0.313681740398891520f, 0.945607325380521280f, -0.325310292162262930f, + 0.941544065183020810f, -0.336889853392220050f, 0.937339011912574960f, -0.348418680249434560f, + 0.932992798834738960f, -0.359895036534988110f, 0.928506080473215590f, -0.371317193951837540f, + 0.923879532511286740f, -0.382683432365089780f, 0.919113851690057770f, -0.393992040061048100f, + 0.914209755703530690f, -0.405241314004989860f, 0.909167983090522380f, -0.416429560097637150f, + 0.903989293123443340f, -0.427555093430282080f, 0.898674465693953820f, -0.438616238538527660f, + 0.893224301195515320f, -0.449611329654606540f, 0.887639620402853930f, -0.460538710958240010f, + 0.881921264348355050f, -0.471396736825997640f, 0.876070094195406600f, -0.482183772079122720f, + 0.870086991108711460f, -0.492898192229784040f, 0.863972856121586810f, -0.503538383725717580f, + 0.857728610000272120f, -0.514102744193221660f, 0.851355193105265200f, -0.524589682678468950f, + 0.844853565249707120f, -0.534997619887097150f, 0.838224705554838080f, -0.545324988422046460f, + 0.831469612302545240f, -0.555570233019602180f, 0.824589302785025290f, -0.565731810783613120f, + 0.817584813151583710f, -0.575808191417845340f, 0.810457198252594770f, -0.585797857456438860f, + 0.803207531480644940f, -0.595699304492433360f, 0.795836904608883570f, -0.605511041404325550f, + 0.788346427626606340f, -0.615231590580626820f, 0.780737228572094490f, -0.624859488142386340f, + 0.773010453362736990f, -0.634393284163645490f, 0.765167265622458960f, -0.643831542889791390f, + 0.757208846506484570f, -0.653172842953776760f, 0.749136394523459370f, -0.662415777590171780f, + 0.740951125354959110f, -0.671558954847018330f, 0.732654271672412820f, -0.680600997795453020f, + 0.724247082951467000f, -0.689540544737066830f, 0.715730825283818590f, -0.698376249408972920f, + 0.707106781186547570f, -0.707106781186547460f, 0.698376249408972920f, -0.715730825283818590f, + 0.689540544737066940f, -0.724247082951466890f, 0.680600997795453130f, -0.732654271672412820f, + 0.671558954847018330f, -0.740951125354959110f, 0.662415777590171780f, -0.749136394523459260f, + 0.653172842953776760f, -0.757208846506484460f, 0.643831542889791500f, -0.765167265622458960f, + 0.634393284163645490f, -0.773010453362736990f, 0.624859488142386450f, -0.780737228572094380f, + 0.615231590580626820f, -0.788346427626606230f, 0.605511041404325550f, -0.795836904608883460f, + 0.595699304492433470f, -0.803207531480644830f, 0.585797857456438860f, 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0.359895036534988280f, -0.932992798834738850f, 0.348418680249434510f, -0.937339011912574960f, + 0.336889853392220050f, -0.941544065183020810f, 0.325310292162262980f, -0.945607325380521280f, + 0.313681740398891570f, -0.949528180593036670f, 0.302005949319228200f, -0.953306040354193750f, + 0.290284677254462330f, -0.956940335732208940f, 0.278519689385053060f, -0.960430519415565790f, + 0.266712757474898420f, -0.963776065795439840f, 0.254865659604514630f, -0.966976471044852070f, + 0.242980179903263980f, -0.970031253194543970f, 0.231058108280671280f, -0.972939952205560070f, + 0.219101240156869770f, -0.975702130038528570f, 0.207111376192218560f, -0.978317370719627650f, + 0.195090322016128330f, -0.980785280403230430f, 0.183039887955141060f, -0.983105487431216290f, + 0.170961888760301360f, -0.985277642388941220f, 0.158858143333861390f, -0.987301418157858430f, + 0.146730474455361750f, -0.989176509964781010f, 0.134580708507126220f, -0.990902635427780010f, + 0.122410675199216280f, -0.992479534598709970f, 0.110222207293883180f, -0.993906970002356060f, + 0.098017140329560770f, -0.995184726672196820f, 0.085797312344439880f, -0.996312612182778000f, + 0.073564563599667454f, -0.997290456678690210f, 0.061320736302208648f, -0.998118112900149180f, + 0.049067674327418126f, -0.998795456205172410f, 0.036807222941358991f, -0.999322384588349540f, + 0.024541228522912264f, -0.999698818696204250f, 0.012271538285719944f, -0.999924701839144500f +}; + + const float32_t cos_factors_128[128] = { + 0.999981175282601110f, 0.999830581795823400f, 0.999529417501093140f, + 0.999077727752645360f, + 0.998475580573294770f, 0.997723066644191640f, 0.996820299291165670f, + 0.995767414467659820f, + 0.994564570734255420f, 0.993211949234794500f, 0.991709753669099530f, + 0.990058210262297120f, + 0.988257567730749460f, 0.986308097244598670f, 0.984210092386929030f, + 0.981963869109555240f, + 0.979569765685440520f, 0.977028142657754390f, 0.974339382785575860f, + 0.971503890986251780f, + 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0.000958737955710053f, 0.000575242787525925f, + 0.000191747598192208f +}; + #endif + +/** + @brief Weights Table + */ + +/** + @par + Weights tables are generated using the formula : 
weights[n] = e^(-j*n*pi/(2*N))
+ @par + C command to generate the table + 
+  for(i = 0; i< N; i++)
+  { 
+    weights[(2*i)]   =  cos(i*c);
+    weights[(2*i)+1] = -sin(i*c);
+  }
+ @par + where N is the Number of weights to be calculated and c is pi/(2*N) + @par + Converted the output to q15 format by multiplying with 2^31 and saturated if required. + @par + In the tables below the real and imaginary values are placed alternatively, hence the + array length is 2*N. + */ + +/** + @par + cosFactor tables are generated using the formula : 
 cos_factors[n] = 2 * cos((2n+1)*pi/(4*N))
+ @par + C command to generate the table + 
+  for (i = 0; i< N; i++)
+  {
+    cos_factors[i] = 2 * cos((2*i+1)*c/2);
+  }
+ @par + where N is the number of factors to generate and c is pi/(2*N) + @par + Then converted to q15 format by multiplying with 2^31 and saturated if required. +*/ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_DCT4_Q15_128) + + const q15_t __ALIGNED(4) WeightsQ15_128[256] = { + (q15_t)0x7fff, (q15_t)0x0, (q15_t)0x7ffd, (q15_t)0xfe6e, (q15_t)0x7ff6, (q15_t)0xfcdc, (q15_t)0x7fe9, (q15_t)0xfb4a, + (q15_t)0x7fd8, (q15_t)0xf9b9, (q15_t)0x7fc2, (q15_t)0xf827, (q15_t)0x7fa7, (q15_t)0xf696, (q15_t)0x7f87, (q15_t)0xf505, + (q15_t)0x7f62, (q15_t)0xf375, (q15_t)0x7f38, (q15_t)0xf1e5, (q15_t)0x7f09, (q15_t)0xf055, (q15_t)0x7ed5, (q15_t)0xeec7, + (q15_t)0x7e9d, (q15_t)0xed38, (q15_t)0x7e5f, (q15_t)0xebab, (q15_t)0x7e1d, (q15_t)0xea1e, (q15_t)0x7dd6, (q15_t)0xe893, + (q15_t)0x7d8a, (q15_t)0xe708, (q15_t)0x7d39, (q15_t)0xe57e, (q15_t)0x7ce3, (q15_t)0xe3f5, (q15_t)0x7c89, (q15_t)0xe26d, + (q15_t)0x7c29, (q15_t)0xe0e7, (q15_t)0x7bc5, (q15_t)0xdf61, (q15_t)0x7b5d, (q15_t)0xdddd, (q15_t)0x7aef, (q15_t)0xdc5a, + (q15_t)0x7a7d, (q15_t)0xdad8, (q15_t)0x7a05, (q15_t)0xd958, (q15_t)0x798a, (q15_t)0xd7da, (q15_t)0x7909, (q15_t)0xd65d, + (q15_t)0x7884, (q15_t)0xd4e1, (q15_t)0x77fa, (q15_t)0xd368, (q15_t)0x776c, (q15_t)0xd1ef, (q15_t)0x76d9, (q15_t)0xd079, + (q15_t)0x7641, (q15_t)0xcf05, (q15_t)0x75a5, (q15_t)0xcd92, (q15_t)0x7504, (q15_t)0xcc22, (q15_t)0x745f, (q15_t)0xcab3, + (q15_t)0x73b5, (q15_t)0xc946, (q15_t)0x7307, (q15_t)0xc7dc, (q15_t)0x7255, (q15_t)0xc674, (q15_t)0x719e, (q15_t)0xc50e, + (q15_t)0x70e2, (q15_t)0xc3aa, (q15_t)0x7023, (q15_t)0xc248, (q15_t)0x6f5f, (q15_t)0xc0e9, (q15_t)0x6e96, (q15_t)0xbf8d, + (q15_t)0x6dca, (q15_t)0xbe32, (q15_t)0x6cf9, (q15_t)0xbcdb, (q15_t)0x6c24, (q15_t)0xbb86, (q15_t)0x6b4a, (q15_t)0xba33, + (q15_t)0x6a6d, (q15_t)0xb8e4, (q15_t)0x698c, (q15_t)0xb797, (q15_t)0x68a6, (q15_t)0xb64c, (q15_t)0x67bd, (q15_t)0xb505, + (q15_t)0x66cf, (q15_t)0xb3c1, (q15_t)0x65dd, (q15_t)0xb27f, (q15_t)0x64e8, (q15_t)0xb141, (q15_t)0x63ef, (q15_t)0xb005, + (q15_t)0x62f2, (q15_t)0xaecd, (q15_t)0x61f1, (q15_t)0xad97, (q15_t)0x60ec, (q15_t)0xac65, (q15_t)0x5fe3, (q15_t)0xab36, + (q15_t)0x5ed7, (q15_t)0xaa0b, (q15_t)0x5dc7, (q15_t)0xa8e3, (q15_t)0x5cb4, (q15_t)0xa7be, (q15_t)0x5b9d, (q15_t)0xa69c, + (q15_t)0x5a82, (q15_t)0xa57e, (q15_t)0x5964, (q15_t)0xa463, (q15_t)0x5842, (q15_t)0xa34c, (q15_t)0x571d, (q15_t)0xa239, + (q15_t)0x55f5, (q15_t)0xa129, (q15_t)0x54ca, (q15_t)0xa01d, (q15_t)0x539b, (q15_t)0x9f14, (q15_t)0x5269, (q15_t)0x9e0f, + (q15_t)0x5133, (q15_t)0x9d0e, (q15_t)0x4ffb, (q15_t)0x9c11, (q15_t)0x4ebf, (q15_t)0x9b18, (q15_t)0x4d81, (q15_t)0x9a23, + (q15_t)0x4c3f, (q15_t)0x9931, (q15_t)0x4afb, (q15_t)0x9843, (q15_t)0x49b4, (q15_t)0x975a, (q15_t)0x4869, (q15_t)0x9674, + (q15_t)0x471c, (q15_t)0x9593, (q15_t)0x45cd, (q15_t)0x94b6, (q15_t)0x447a, (q15_t)0x93dc, (q15_t)0x4325, (q15_t)0x9307, + (q15_t)0x41ce, (q15_t)0x9236, (q15_t)0x4073, (q15_t)0x916a, (q15_t)0x3f17, (q15_t)0x90a1, (q15_t)0x3db8, (q15_t)0x8fdd, + (q15_t)0x3c56, (q15_t)0x8f1e, (q15_t)0x3af2, (q15_t)0x8e62, (q15_t)0x398c, (q15_t)0x8dab, (q15_t)0x3824, (q15_t)0x8cf9, + (q15_t)0x36ba, (q15_t)0x8c4b, (q15_t)0x354d, (q15_t)0x8ba1, (q15_t)0x33de, (q15_t)0x8afc, (q15_t)0x326e, (q15_t)0x8a5b, + (q15_t)0x30fb, (q15_t)0x89bf, (q15_t)0x2f87, (q15_t)0x8927, (q15_t)0x2e11, (q15_t)0x8894, (q15_t)0x2c98, (q15_t)0x8806, + (q15_t)0x2b1f, (q15_t)0x877c, (q15_t)0x29a3, (q15_t)0x86f7, (q15_t)0x2826, (q15_t)0x8676, (q15_t)0x26a8, (q15_t)0x85fb, + (q15_t)0x2528, (q15_t)0x8583, (q15_t)0x23a6, (q15_t)0x8511, (q15_t)0x2223, (q15_t)0x84a3, (q15_t)0x209f, (q15_t)0x843b, + (q15_t)0x1f19, (q15_t)0x83d7, (q15_t)0x1d93, (q15_t)0x8377, (q15_t)0x1c0b, (q15_t)0x831d, (q15_t)0x1a82, (q15_t)0x82c7, + (q15_t)0x18f8, (q15_t)0x8276, (q15_t)0x176d, (q15_t)0x822a, (q15_t)0x15e2, (q15_t)0x81e3, (q15_t)0x1455, (q15_t)0x81a1, + (q15_t)0x12c8, (q15_t)0x8163, (q15_t)0x1139, (q15_t)0x812b, (q15_t)0xfab, (q15_t)0x80f7, (q15_t)0xe1b, (q15_t)0x80c8, + (q15_t)0xc8b, (q15_t)0x809e, (q15_t)0xafb, (q15_t)0x8079, (q15_t)0x96a, (q15_t)0x8059, (q15_t)0x7d9, (q15_t)0x803e, + (q15_t)0x647, (q15_t)0x8028, (q15_t)0x4b6, (q15_t)0x8017, (q15_t)0x324, (q15_t)0x800a, (q15_t)0x192, (q15_t)0x8003 +}; + const q15_t __ALIGNED(4) cos_factorsQ15_128[128] = { + (q15_t)0x7fff, (q15_t)0x7ffa, (q15_t)0x7ff0, (q15_t)0x7fe1, (q15_t)0x7fce, (q15_t)0x7fb5, (q15_t)0x7f97, (q15_t)0x7f75, + (q15_t)0x7f4d, (q15_t)0x7f21, (q15_t)0x7ef0, (q15_t)0x7eba, (q15_t)0x7e7f, (q15_t)0x7e3f, (q15_t)0x7dfa, (q15_t)0x7db0, + (q15_t)0x7d62, (q15_t)0x7d0f, (q15_t)0x7cb7, (q15_t)0x7c5a, (q15_t)0x7bf8, (q15_t)0x7b92, (q15_t)0x7b26, (q15_t)0x7ab6, + (q15_t)0x7a42, (q15_t)0x79c8, (q15_t)0x794a, (q15_t)0x78c7, (q15_t)0x7840, (q15_t)0x77b4, (q15_t)0x7723, (q15_t)0x768e, + (q15_t)0x75f4, (q15_t)0x7555, (q15_t)0x74b2, (q15_t)0x740b, (q15_t)0x735f, (q15_t)0x72af, (q15_t)0x71fa, (q15_t)0x7141, + (q15_t)0x7083, (q15_t)0x6fc1, (q15_t)0x6efb, (q15_t)0x6e30, (q15_t)0x6d62, (q15_t)0x6c8f, (q15_t)0x6bb8, (q15_t)0x6adc, + (q15_t)0x69fd, (q15_t)0x6919, (q15_t)0x6832, (q15_t)0x6746, (q15_t)0x6657, (q15_t)0x6563, (q15_t)0x646c, (q15_t)0x6371, + (q15_t)0x6271, (q15_t)0x616f, (q15_t)0x6068, (q15_t)0x5f5e, (q15_t)0x5e50, (q15_t)0x5d3e, (q15_t)0x5c29, (q15_t)0x5b10, + (q15_t)0x59f3, (q15_t)0x58d4, (q15_t)0x57b0, (q15_t)0x568a, (q15_t)0x5560, (q15_t)0x5433, (q15_t)0x5302, (q15_t)0x51ce, + (q15_t)0x5097, (q15_t)0x4f5e, (q15_t)0x4e21, (q15_t)0x4ce1, (q15_t)0x4b9e, (q15_t)0x4a58, (q15_t)0x490f, (q15_t)0x47c3, + (q15_t)0x4675, (q15_t)0x4524, (q15_t)0x43d0, (q15_t)0x427a, (q15_t)0x4121, (q15_t)0x3fc5, (q15_t)0x3e68, (q15_t)0x3d07, + (q15_t)0x3ba5, (q15_t)0x3a40, (q15_t)0x38d8, (q15_t)0x376f, (q15_t)0x3604, (q15_t)0x3496, (q15_t)0x3326, (q15_t)0x31b5, + (q15_t)0x3041, (q15_t)0x2ecc, (q15_t)0x2d55, (q15_t)0x2bdc, (q15_t)0x2a61, (q15_t)0x28e5, (q15_t)0x2767, (q15_t)0x25e8, + (q15_t)0x2467, (q15_t)0x22e5, (q15_t)0x2161, (q15_t)0x1fdc, (q15_t)0x1e56, (q15_t)0x1ccf, (q15_t)0x1b47, (q15_t)0x19bd, + (q15_t)0x1833, (q15_t)0x16a8, (q15_t)0x151b, (q15_t)0x138e, (q15_t)0x1201, (q15_t)0x1072, (q15_t)0xee3, (q15_t)0xd53, + (q15_t)0xbc3, (q15_t)0xa33, (q15_t)0x8a2, (q15_t)0x710, (q15_t)0x57f, (q15_t)0x3ed, (q15_t)0x25b, (q15_t)0xc9 +}; + #endif + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_DCT4_Q15_512) + const q15_t __ALIGNED(4) WeightsQ15_512[1024] = { + (q15_t)0x7fff, (q15_t)0x0, (q15_t)0x7fff, (q15_t)0xff9c, (q15_t)0x7fff, (q15_t)0xff37, (q15_t)0x7ffe, (q15_t)0xfed3, + (q15_t)0x7ffd, (q15_t)0xfe6e, (q15_t)0x7ffc, (q15_t)0xfe0a, (q15_t)0x7ffa, (q15_t)0xfda5, (q15_t)0x7ff8, (q15_t)0xfd41, + (q15_t)0x7ff6, (q15_t)0xfcdc, (q15_t)0x7ff3, (q15_t)0xfc78, (q15_t)0x7ff0, (q15_t)0xfc13, (q15_t)0x7fed, (q15_t)0xfbaf, + (q15_t)0x7fe9, (q15_t)0xfb4a, (q15_t)0x7fe5, (q15_t)0xfae6, (q15_t)0x7fe1, (q15_t)0xfa81, (q15_t)0x7fdd, (q15_t)0xfa1d, + (q15_t)0x7fd8, (q15_t)0xf9b9, (q15_t)0x7fd3, (q15_t)0xf954, (q15_t)0x7fce, (q15_t)0xf8f0, (q15_t)0x7fc8, (q15_t)0xf88b, + (q15_t)0x7fc2, (q15_t)0xf827, (q15_t)0x7fbc, (q15_t)0xf7c3, (q15_t)0x7fb5, (q15_t)0xf75e, (q15_t)0x7fae, (q15_t)0xf6fa, + (q15_t)0x7fa7, (q15_t)0xf696, (q15_t)0x7f9f, (q15_t)0xf632, (q15_t)0x7f97, (q15_t)0xf5cd, (q15_t)0x7f8f, (q15_t)0xf569, + (q15_t)0x7f87, (q15_t)0xf505, (q15_t)0x7f7e, (q15_t)0xf4a1, (q15_t)0x7f75, (q15_t)0xf43d, (q15_t)0x7f6b, (q15_t)0xf3d9, + (q15_t)0x7f62, (q15_t)0xf375, (q15_t)0x7f58, (q15_t)0xf311, (q15_t)0x7f4d, (q15_t)0xf2ad, (q15_t)0x7f43, (q15_t)0xf249, + (q15_t)0x7f38, (q15_t)0xf1e5, (q15_t)0x7f2d, (q15_t)0xf181, (q15_t)0x7f21, (q15_t)0xf11d, (q15_t)0x7f15, (q15_t)0xf0b9, + (q15_t)0x7f09, (q15_t)0xf055, (q15_t)0x7efd, (q15_t)0xeff2, (q15_t)0x7ef0, (q15_t)0xef8e, (q15_t)0x7ee3, (q15_t)0xef2a, + (q15_t)0x7ed5, (q15_t)0xeec7, (q15_t)0x7ec8, (q15_t)0xee63, (q15_t)0x7eba, (q15_t)0xedff, (q15_t)0x7eab, (q15_t)0xed9c, + (q15_t)0x7e9d, (q15_t)0xed38, (q15_t)0x7e8e, (q15_t)0xecd5, (q15_t)0x7e7f, (q15_t)0xec72, (q15_t)0x7e6f, (q15_t)0xec0e, + (q15_t)0x7e5f, (q15_t)0xebab, (q15_t)0x7e4f, (q15_t)0xeb48, (q15_t)0x7e3f, (q15_t)0xeae5, (q15_t)0x7e2e, (q15_t)0xea81, + (q15_t)0x7e1d, (q15_t)0xea1e, (q15_t)0x7e0c, (q15_t)0xe9bb, (q15_t)0x7dfa, (q15_t)0xe958, (q15_t)0x7de8, (q15_t)0xe8f6, + (q15_t)0x7dd6, (q15_t)0xe893, (q15_t)0x7dc3, (q15_t)0xe830, (q15_t)0x7db0, (q15_t)0xe7cd, (q15_t)0x7d9d, (q15_t)0xe76a, + (q15_t)0x7d8a, (q15_t)0xe708, (q15_t)0x7d76, (q15_t)0xe6a5, (q15_t)0x7d62, (q15_t)0xe643, (q15_t)0x7d4e, (q15_t)0xe5e0, + (q15_t)0x7d39, (q15_t)0xe57e, (q15_t)0x7d24, (q15_t)0xe51c, (q15_t)0x7d0f, (q15_t)0xe4b9, (q15_t)0x7cf9, (q15_t)0xe457, + (q15_t)0x7ce3, (q15_t)0xe3f5, (q15_t)0x7ccd, (q15_t)0xe393, (q15_t)0x7cb7, (q15_t)0xe331, (q15_t)0x7ca0, (q15_t)0xe2cf, + (q15_t)0x7c89, (q15_t)0xe26d, (q15_t)0x7c71, (q15_t)0xe20b, (q15_t)0x7c5a, (q15_t)0xe1aa, (q15_t)0x7c42, (q15_t)0xe148, + (q15_t)0x7c29, (q15_t)0xe0e7, (q15_t)0x7c11, (q15_t)0xe085, (q15_t)0x7bf8, (q15_t)0xe024, (q15_t)0x7bdf, (q15_t)0xdfc2, + (q15_t)0x7bc5, (q15_t)0xdf61, (q15_t)0x7bac, (q15_t)0xdf00, (q15_t)0x7b92, (q15_t)0xde9f, (q15_t)0x7b77, (q15_t)0xde3e, + (q15_t)0x7b5d, (q15_t)0xdddd, (q15_t)0x7b42, (q15_t)0xdd7c, (q15_t)0x7b26, (q15_t)0xdd1b, (q15_t)0x7b0b, (q15_t)0xdcbb, + (q15_t)0x7aef, (q15_t)0xdc5a, (q15_t)0x7ad3, (q15_t)0xdbf9, (q15_t)0x7ab6, (q15_t)0xdb99, (q15_t)0x7a9a, (q15_t)0xdb39, + (q15_t)0x7a7d, (q15_t)0xdad8, (q15_t)0x7a5f, (q15_t)0xda78, (q15_t)0x7a42, (q15_t)0xda18, (q15_t)0x7a24, (q15_t)0xd9b8, + (q15_t)0x7a05, (q15_t)0xd958, (q15_t)0x79e7, (q15_t)0xd8f9, (q15_t)0x79c8, (q15_t)0xd899, (q15_t)0x79a9, (q15_t)0xd839, + (q15_t)0x798a, (q15_t)0xd7da, (q15_t)0x796a, (q15_t)0xd77a, (q15_t)0x794a, (q15_t)0xd71b, (q15_t)0x792a, (q15_t)0xd6bc, + (q15_t)0x7909, (q15_t)0xd65d, (q15_t)0x78e8, (q15_t)0xd5fe, (q15_t)0x78c7, (q15_t)0xd59f, (q15_t)0x78a6, (q15_t)0xd540, + (q15_t)0x7884, (q15_t)0xd4e1, (q15_t)0x7862, (q15_t)0xd483, (q15_t)0x7840, (q15_t)0xd424, (q15_t)0x781d, (q15_t)0xd3c6, + (q15_t)0x77fa, (q15_t)0xd368, (q15_t)0x77d7, (q15_t)0xd309, (q15_t)0x77b4, (q15_t)0xd2ab, (q15_t)0x7790, (q15_t)0xd24d, + (q15_t)0x776c, (q15_t)0xd1ef, (q15_t)0x7747, (q15_t)0xd192, (q15_t)0x7723, (q15_t)0xd134, (q15_t)0x76fe, (q15_t)0xd0d7, + (q15_t)0x76d9, (q15_t)0xd079, (q15_t)0x76b3, (q15_t)0xd01c, (q15_t)0x768e, (q15_t)0xcfbf, (q15_t)0x7668, (q15_t)0xcf62, + (q15_t)0x7641, (q15_t)0xcf05, (q15_t)0x761b, (q15_t)0xcea8, (q15_t)0x75f4, (q15_t)0xce4b, (q15_t)0x75cc, (q15_t)0xcdef, + (q15_t)0x75a5, (q15_t)0xcd92, (q15_t)0x757d, (q15_t)0xcd36, (q15_t)0x7555, (q15_t)0xccda, (q15_t)0x752d, (q15_t)0xcc7e, + (q15_t)0x7504, (q15_t)0xcc22, (q15_t)0x74db, (q15_t)0xcbc6, (q15_t)0x74b2, (q15_t)0xcb6a, (q15_t)0x7489, (q15_t)0xcb0e, + (q15_t)0x745f, (q15_t)0xcab3, (q15_t)0x7435, (q15_t)0xca58, (q15_t)0x740b, (q15_t)0xc9fc, (q15_t)0x73e0, (q15_t)0xc9a1, + (q15_t)0x73b5, (q15_t)0xc946, (q15_t)0x738a, (q15_t)0xc8ec, (q15_t)0x735f, (q15_t)0xc891, (q15_t)0x7333, (q15_t)0xc836, + (q15_t)0x7307, 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(q15_t)0x90d3, + (q15_t)0x3f17, (q15_t)0x90a1, (q15_t)0x3ebf, (q15_t)0x9070, (q15_t)0x3e68, (q15_t)0x903f, (q15_t)0x3e10, (q15_t)0x900e, + (q15_t)0x3db8, (q15_t)0x8fdd, (q15_t)0x3d60, (q15_t)0x8fad, (q15_t)0x3d07, (q15_t)0x8f7d, (q15_t)0x3caf, (q15_t)0x8f4d, + (q15_t)0x3c56, (q15_t)0x8f1e, (q15_t)0x3bfd, (q15_t)0x8eee, (q15_t)0x3ba5, (q15_t)0x8ebf, (q15_t)0x3b4c, (q15_t)0x8e91, + (q15_t)0x3af2, (q15_t)0x8e62, (q15_t)0x3a99, (q15_t)0x8e34, (q15_t)0x3a40, (q15_t)0x8e06, (q15_t)0x39e6, (q15_t)0x8dd9, + (q15_t)0x398c, (q15_t)0x8dab, (q15_t)0x3932, (q15_t)0x8d7e, (q15_t)0x38d8, (q15_t)0x8d51, (q15_t)0x387e, (q15_t)0x8d25, + (q15_t)0x3824, (q15_t)0x8cf9, (q15_t)0x37ca, (q15_t)0x8ccd, (q15_t)0x376f, (q15_t)0x8ca1, (q15_t)0x3714, (q15_t)0x8c76, + (q15_t)0x36ba, (q15_t)0x8c4b, (q15_t)0x365f, (q15_t)0x8c20, (q15_t)0x3604, (q15_t)0x8bf5, (q15_t)0x35a8, (q15_t)0x8bcb, + (q15_t)0x354d, (q15_t)0x8ba1, (q15_t)0x34f2, (q15_t)0x8b77, (q15_t)0x3496, (q15_t)0x8b4e, (q15_t)0x343a, (q15_t)0x8b25, + (q15_t)0x33de, (q15_t)0x8afc, (q15_t)0x3382, (q15_t)0x8ad3, (q15_t)0x3326, (q15_t)0x8aab, (q15_t)0x32ca, (q15_t)0x8a83, + (q15_t)0x326e, (q15_t)0x8a5b, (q15_t)0x3211, (q15_t)0x8a34, (q15_t)0x31b5, (q15_t)0x8a0c, (q15_t)0x3158, (q15_t)0x89e5, + (q15_t)0x30fb, (q15_t)0x89bf, (q15_t)0x309e, (q15_t)0x8998, (q15_t)0x3041, (q15_t)0x8972, (q15_t)0x2fe4, (q15_t)0x894d, + (q15_t)0x2f87, (q15_t)0x8927, (q15_t)0x2f29, (q15_t)0x8902, (q15_t)0x2ecc, (q15_t)0x88dd, (q15_t)0x2e6e, (q15_t)0x88b9, + (q15_t)0x2e11, (q15_t)0x8894, (q15_t)0x2db3, (q15_t)0x8870, (q15_t)0x2d55, (q15_t)0x884c, (q15_t)0x2cf7, (q15_t)0x8829, + (q15_t)0x2c98, (q15_t)0x8806, (q15_t)0x2c3a, (q15_t)0x87e3, (q15_t)0x2bdc, (q15_t)0x87c0, (q15_t)0x2b7d, (q15_t)0x879e, + (q15_t)0x2b1f, (q15_t)0x877c, (q15_t)0x2ac0, (q15_t)0x875a, (q15_t)0x2a61, (q15_t)0x8739, (q15_t)0x2a02, (q15_t)0x8718, + (q15_t)0x29a3, (q15_t)0x86f7, (q15_t)0x2944, (q15_t)0x86d6, (q15_t)0x28e5, (q15_t)0x86b6, (q15_t)0x2886, (q15_t)0x8696, + (q15_t)0x2826, (q15_t)0x8676, (q15_t)0x27c7, (q15_t)0x8657, (q15_t)0x2767, (q15_t)0x8638, (q15_t)0x2707, (q15_t)0x8619, + (q15_t)0x26a8, (q15_t)0x85fb, (q15_t)0x2648, (q15_t)0x85dc, (q15_t)0x25e8, (q15_t)0x85be, (q15_t)0x2588, (q15_t)0x85a1, + (q15_t)0x2528, (q15_t)0x8583, (q15_t)0x24c7, (q15_t)0x8566, (q15_t)0x2467, (q15_t)0x854a, (q15_t)0x2407, (q15_t)0x852d, + (q15_t)0x23a6, (q15_t)0x8511, (q15_t)0x2345, (q15_t)0x84f5, (q15_t)0x22e5, (q15_t)0x84da, (q15_t)0x2284, (q15_t)0x84be, + (q15_t)0x2223, (q15_t)0x84a3, (q15_t)0x21c2, (q15_t)0x8489, (q15_t)0x2161, (q15_t)0x846e, (q15_t)0x2100, (q15_t)0x8454, + (q15_t)0x209f, (q15_t)0x843b, (q15_t)0x203e, (q15_t)0x8421, (q15_t)0x1fdc, (q15_t)0x8408, (q15_t)0x1f7b, (q15_t)0x83ef, + (q15_t)0x1f19, (q15_t)0x83d7, (q15_t)0x1eb8, (q15_t)0x83be, (q15_t)0x1e56, (q15_t)0x83a6, (q15_t)0x1df5, (q15_t)0x838f, + (q15_t)0x1d93, (q15_t)0x8377, (q15_t)0x1d31, (q15_t)0x8360, (q15_t)0x1ccf, (q15_t)0x8349, (q15_t)0x1c6d, (q15_t)0x8333, + (q15_t)0x1c0b, (q15_t)0x831d, (q15_t)0x1ba9, (q15_t)0x8307, (q15_t)0x1b47, (q15_t)0x82f1, (q15_t)0x1ae4, (q15_t)0x82dc, + (q15_t)0x1a82, (q15_t)0x82c7, (q15_t)0x1a20, (q15_t)0x82b2, (q15_t)0x19bd, (q15_t)0x829e, (q15_t)0x195b, (q15_t)0x828a, + (q15_t)0x18f8, (q15_t)0x8276, (q15_t)0x1896, (q15_t)0x8263, (q15_t)0x1833, (q15_t)0x8250, (q15_t)0x17d0, (q15_t)0x823d, + (q15_t)0x176d, (q15_t)0x822a, (q15_t)0x170a, (q15_t)0x8218, (q15_t)0x16a8, (q15_t)0x8206, (q15_t)0x1645, (q15_t)0x81f4, + (q15_t)0x15e2, (q15_t)0x81e3, (q15_t)0x157f, (q15_t)0x81d2, (q15_t)0x151b, (q15_t)0x81c1, (q15_t)0x14b8, (q15_t)0x81b1, + (q15_t)0x1455, (q15_t)0x81a1, (q15_t)0x13f2, (q15_t)0x8191, (q15_t)0x138e, (q15_t)0x8181, (q15_t)0x132b, (q15_t)0x8172, + (q15_t)0x12c8, (q15_t)0x8163, (q15_t)0x1264, (q15_t)0x8155, (q15_t)0x1201, (q15_t)0x8146, (q15_t)0x119d, (q15_t)0x8138, + (q15_t)0x1139, (q15_t)0x812b, (q15_t)0x10d6, (q15_t)0x811d, (q15_t)0x1072, (q15_t)0x8110, (q15_t)0x100e, (q15_t)0x8103, + (q15_t)0xfab, (q15_t)0x80f7, (q15_t)0xf47, (q15_t)0x80eb, (q15_t)0xee3, (q15_t)0x80df, (q15_t)0xe7f, (q15_t)0x80d3, + (q15_t)0xe1b, (q15_t)0x80c8, (q15_t)0xdb7, (q15_t)0x80bd, (q15_t)0xd53, (q15_t)0x80b3, (q15_t)0xcef, (q15_t)0x80a8, + (q15_t)0xc8b, (q15_t)0x809e, (q15_t)0xc27, (q15_t)0x8095, (q15_t)0xbc3, (q15_t)0x808b, (q15_t)0xb5f, (q15_t)0x8082, + (q15_t)0xafb, (q15_t)0x8079, (q15_t)0xa97, (q15_t)0x8071, (q15_t)0xa33, (q15_t)0x8069, (q15_t)0x9ce, (q15_t)0x8061, + (q15_t)0x96a, (q15_t)0x8059, (q15_t)0x906, (q15_t)0x8052, (q15_t)0x8a2, (q15_t)0x804b, (q15_t)0x83d, (q15_t)0x8044, + (q15_t)0x7d9, (q15_t)0x803e, (q15_t)0x775, (q15_t)0x8038, (q15_t)0x710, (q15_t)0x8032, (q15_t)0x6ac, (q15_t)0x802d, + (q15_t)0x647, (q15_t)0x8028, (q15_t)0x5e3, (q15_t)0x8023, (q15_t)0x57f, (q15_t)0x801f, (q15_t)0x51a, (q15_t)0x801b, + (q15_t)0x4b6, (q15_t)0x8017, (q15_t)0x451, (q15_t)0x8013, (q15_t)0x3ed, (q15_t)0x8010, (q15_t)0x388, (q15_t)0x800d, + (q15_t)0x324, (q15_t)0x800a, (q15_t)0x2bf, (q15_t)0x8008, (q15_t)0x25b, (q15_t)0x8006, (q15_t)0x1f6, (q15_t)0x8004, + (q15_t)0x192, (q15_t)0x8003, (q15_t)0x12d, (q15_t)0x8002, (q15_t)0xc9, (q15_t)0x8001, (q15_t)0x64, (q15_t)0x8001 +}; + + const q15_t __ALIGNED(4) cos_factorsQ15_512[512] = { + (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7ffe, (q15_t)0x7ffc, (q15_t)0x7ffb, (q15_t)0x7ff9, (q15_t)0x7ff7, + (q15_t)0x7ff4, (q15_t)0x7ff2, (q15_t)0x7fee, (q15_t)0x7feb, (q15_t)0x7fe7, (q15_t)0x7fe3, (q15_t)0x7fdf, (q15_t)0x7fda, + (q15_t)0x7fd6, (q15_t)0x7fd0, (q15_t)0x7fcb, (q15_t)0x7fc5, (q15_t)0x7fbf, (q15_t)0x7fb8, (q15_t)0x7fb1, (q15_t)0x7faa, + (q15_t)0x7fa3, (q15_t)0x7f9b, (q15_t)0x7f93, (q15_t)0x7f8b, (q15_t)0x7f82, (q15_t)0x7f79, (q15_t)0x7f70, (q15_t)0x7f67, + (q15_t)0x7f5d, (q15_t)0x7f53, (q15_t)0x7f48, (q15_t)0x7f3d, (q15_t)0x7f32, (q15_t)0x7f27, (q15_t)0x7f1b, (q15_t)0x7f0f, + (q15_t)0x7f03, (q15_t)0x7ef6, (q15_t)0x7ee9, (q15_t)0x7edc, (q15_t)0x7ecf, (q15_t)0x7ec1, (q15_t)0x7eb3, (q15_t)0x7ea4, + (q15_t)0x7e95, (q15_t)0x7e86, (q15_t)0x7e77, (q15_t)0x7e67, (q15_t)0x7e57, (q15_t)0x7e47, (q15_t)0x7e37, (q15_t)0x7e26, + (q15_t)0x7e14, (q15_t)0x7e03, (q15_t)0x7df1, (q15_t)0x7ddf, (q15_t)0x7dcd, (q15_t)0x7dba, (q15_t)0x7da7, (q15_t)0x7d94, + (q15_t)0x7d80, (q15_t)0x7d6c, (q15_t)0x7d58, (q15_t)0x7d43, (q15_t)0x7d2f, (q15_t)0x7d19, (q15_t)0x7d04, (q15_t)0x7cee, + (q15_t)0x7cd8, (q15_t)0x7cc2, (q15_t)0x7cab, (q15_t)0x7c94, (q15_t)0x7c7d, (q15_t)0x7c66, (q15_t)0x7c4e, (q15_t)0x7c36, + (q15_t)0x7c1d, (q15_t)0x7c05, (q15_t)0x7beb, (q15_t)0x7bd2, (q15_t)0x7bb9, (q15_t)0x7b9f, (q15_t)0x7b84, (q15_t)0x7b6a, + (q15_t)0x7b4f, (q15_t)0x7b34, (q15_t)0x7b19, (q15_t)0x7afd, (q15_t)0x7ae1, (q15_t)0x7ac5, (q15_t)0x7aa8, (q15_t)0x7a8b, + (q15_t)0x7a6e, (q15_t)0x7a50, (q15_t)0x7a33, (q15_t)0x7a15, (q15_t)0x79f6, (q15_t)0x79d8, (q15_t)0x79b9, (q15_t)0x7999, + (q15_t)0x797a, (q15_t)0x795a, (q15_t)0x793a, (q15_t)0x7919, (q15_t)0x78f9, (q15_t)0x78d8, (q15_t)0x78b6, (q15_t)0x7895, + (q15_t)0x7873, (q15_t)0x7851, (q15_t)0x782e, (q15_t)0x780c, (q15_t)0x77e9, (q15_t)0x77c5, (q15_t)0x77a2, (q15_t)0x777e, + (q15_t)0x775a, (q15_t)0x7735, (q15_t)0x7710, (q15_t)0x76eb, (q15_t)0x76c6, (q15_t)0x76a0, (q15_t)0x767b, (q15_t)0x7654, + (q15_t)0x762e, (q15_t)0x7607, (q15_t)0x75e0, (q15_t)0x75b9, (q15_t)0x7591, (q15_t)0x7569, (q15_t)0x7541, (q15_t)0x7519, + (q15_t)0x74f0, (q15_t)0x74c7, (q15_t)0x749e, (q15_t)0x7474, (q15_t)0x744a, (q15_t)0x7420, (q15_t)0x73f6, (q15_t)0x73cb, + (q15_t)0x73a0, (q15_t)0x7375, (q15_t)0x7349, (q15_t)0x731d, (q15_t)0x72f1, (q15_t)0x72c5, (q15_t)0x7298, (q15_t)0x726b, + (q15_t)0x723e, (q15_t)0x7211, (q15_t)0x71e3, (q15_t)0x71b5, (q15_t)0x7186, (q15_t)0x7158, (q15_t)0x7129, (q15_t)0x70fa, + (q15_t)0x70cb, (q15_t)0x709b, (q15_t)0x706b, (q15_t)0x703b, (q15_t)0x700a, (q15_t)0x6fda, (q15_t)0x6fa9, (q15_t)0x6f77, + (q15_t)0x6f46, (q15_t)0x6f14, (q15_t)0x6ee2, (q15_t)0x6eaf, (q15_t)0x6e7d, (q15_t)0x6e4a, (q15_t)0x6e17, (q15_t)0x6de3, + (q15_t)0x6db0, (q15_t)0x6d7c, (q15_t)0x6d48, (q15_t)0x6d13, (q15_t)0x6cde, (q15_t)0x6ca9, (q15_t)0x6c74, (q15_t)0x6c3f, + (q15_t)0x6c09, (q15_t)0x6bd3, (q15_t)0x6b9c, (q15_t)0x6b66, (q15_t)0x6b2f, (q15_t)0x6af8, (q15_t)0x6ac1, (q15_t)0x6a89, + (q15_t)0x6a51, (q15_t)0x6a19, (q15_t)0x69e1, (q15_t)0x69a8, (q15_t)0x696f, (q15_t)0x6936, (q15_t)0x68fd, (q15_t)0x68c3, + (q15_t)0x6889, (q15_t)0x684f, (q15_t)0x6815, (q15_t)0x67da, (q15_t)0x679f, (q15_t)0x6764, (q15_t)0x6729, (q15_t)0x66ed, + (q15_t)0x66b1, (q15_t)0x6675, (q15_t)0x6639, (q15_t)0x65fc, (q15_t)0x65bf, (q15_t)0x6582, (q15_t)0x6545, (q15_t)0x6507, + (q15_t)0x64c9, (q15_t)0x648b, (q15_t)0x644d, (q15_t)0x640e, (q15_t)0x63cf, (q15_t)0x6390, (q15_t)0x6351, (q15_t)0x6311, + (q15_t)0x62d2, (q15_t)0x6292, (q15_t)0x6251, (q15_t)0x6211, (q15_t)0x61d0, (q15_t)0x618f, (q15_t)0x614e, (q15_t)0x610d, + (q15_t)0x60cb, (q15_t)0x6089, (q15_t)0x6047, (q15_t)0x6004, (q15_t)0x5fc2, (q15_t)0x5f7f, (q15_t)0x5f3c, (q15_t)0x5ef9, + (q15_t)0x5eb5, (q15_t)0x5e71, (q15_t)0x5e2d, (q15_t)0x5de9, (q15_t)0x5da5, (q15_t)0x5d60, (q15_t)0x5d1b, (q15_t)0x5cd6, + (q15_t)0x5c91, (q15_t)0x5c4b, (q15_t)0x5c06, (q15_t)0x5bc0, (q15_t)0x5b79, (q15_t)0x5b33, (q15_t)0x5aec, (q15_t)0x5aa5, + (q15_t)0x5a5e, (q15_t)0x5a17, (q15_t)0x59d0, (q15_t)0x5988, (q15_t)0x5940, (q15_t)0x58f8, (q15_t)0x58af, (q15_t)0x5867, + (q15_t)0x581e, (q15_t)0x57d5, (q15_t)0x578c, (q15_t)0x5742, (q15_t)0x56f9, (q15_t)0x56af, (q15_t)0x5665, (q15_t)0x561a, + (q15_t)0x55d0, (q15_t)0x5585, (q15_t)0x553a, (q15_t)0x54ef, (q15_t)0x54a4, (q15_t)0x5458, (q15_t)0x540d, (q15_t)0x53c1, + (q15_t)0x5375, (q15_t)0x5328, (q15_t)0x52dc, (q15_t)0x528f, (q15_t)0x5242, (q15_t)0x51f5, (q15_t)0x51a8, (q15_t)0x515a, + (q15_t)0x510c, (q15_t)0x50bf, (q15_t)0x5070, (q15_t)0x5022, (q15_t)0x4fd4, (q15_t)0x4f85, (q15_t)0x4f36, (q15_t)0x4ee7, + (q15_t)0x4e98, (q15_t)0x4e48, (q15_t)0x4df9, (q15_t)0x4da9, (q15_t)0x4d59, (q15_t)0x4d09, (q15_t)0x4cb8, (q15_t)0x4c68, + (q15_t)0x4c17, (q15_t)0x4bc6, (q15_t)0x4b75, (q15_t)0x4b24, (q15_t)0x4ad2, (q15_t)0x4a81, (q15_t)0x4a2f, (q15_t)0x49dd, + (q15_t)0x498a, (q15_t)0x4938, (q15_t)0x48e6, (q15_t)0x4893, (q15_t)0x4840, (q15_t)0x47ed, (q15_t)0x479a, (q15_t)0x4746, + (q15_t)0x46f3, (q15_t)0x469f, (q15_t)0x464b, (q15_t)0x45f7, (q15_t)0x45a3, (q15_t)0x454e, (q15_t)0x44fa, (q15_t)0x44a5, + (q15_t)0x4450, (q15_t)0x43fb, (q15_t)0x43a5, (q15_t)0x4350, (q15_t)0x42fa, (q15_t)0x42a5, (q15_t)0x424f, (q15_t)0x41f9, + (q15_t)0x41a2, (q15_t)0x414c, (q15_t)0x40f6, (q15_t)0x409f, (q15_t)0x4048, (q15_t)0x3ff1, (q15_t)0x3f9a, (q15_t)0x3f43, + (q15_t)0x3eeb, (q15_t)0x3e93, (q15_t)0x3e3c, (q15_t)0x3de4, (q15_t)0x3d8c, (q15_t)0x3d33, (q15_t)0x3cdb, (q15_t)0x3c83, + (q15_t)0x3c2a, (q15_t)0x3bd1, (q15_t)0x3b78, (q15_t)0x3b1f, (q15_t)0x3ac6, (q15_t)0x3a6c, (q15_t)0x3a13, (q15_t)0x39b9, + (q15_t)0x395f, (q15_t)0x3906, (q15_t)0x38ab, (q15_t)0x3851, (q15_t)0x37f7, (q15_t)0x379c, (q15_t)0x3742, (q15_t)0x36e7, + (q15_t)0x368c, (q15_t)0x3631, (q15_t)0x35d6, (q15_t)0x357b, (q15_t)0x351f, (q15_t)0x34c4, (q15_t)0x3468, (q15_t)0x340c, + (q15_t)0x33b0, (q15_t)0x3354, (q15_t)0x32f8, (q15_t)0x329c, (q15_t)0x3240, (q15_t)0x31e3, (q15_t)0x3186, (q15_t)0x312a, + (q15_t)0x30cd, (q15_t)0x3070, (q15_t)0x3013, (q15_t)0x2fb5, (q15_t)0x2f58, (q15_t)0x2efb, (q15_t)0x2e9d, (q15_t)0x2e3f, + (q15_t)0x2de2, (q15_t)0x2d84, (q15_t)0x2d26, (q15_t)0x2cc8, (q15_t)0x2c69, (q15_t)0x2c0b, (q15_t)0x2bad, (q15_t)0x2b4e, + (q15_t)0x2aef, (q15_t)0x2a91, (q15_t)0x2a32, (q15_t)0x29d3, (q15_t)0x2974, (q15_t)0x2915, (q15_t)0x28b5, (q15_t)0x2856, + (q15_t)0x27f6, (q15_t)0x2797, (q15_t)0x2737, (q15_t)0x26d8, (q15_t)0x2678, (q15_t)0x2618, (q15_t)0x25b8, (q15_t)0x2558, + (q15_t)0x24f7, (q15_t)0x2497, (q15_t)0x2437, (q15_t)0x23d6, (q15_t)0x2376, (q15_t)0x2315, (q15_t)0x22b4, (q15_t)0x2254, + (q15_t)0x21f3, (q15_t)0x2192, (q15_t)0x2131, (q15_t)0x20d0, (q15_t)0x206e, (q15_t)0x200d, (q15_t)0x1fac, (q15_t)0x1f4a, + (q15_t)0x1ee9, (q15_t)0x1e87, (q15_t)0x1e25, (q15_t)0x1dc4, (q15_t)0x1d62, (q15_t)0x1d00, (q15_t)0x1c9e, (q15_t)0x1c3c, + (q15_t)0x1bda, (q15_t)0x1b78, (q15_t)0x1b16, (q15_t)0x1ab3, (q15_t)0x1a51, (q15_t)0x19ef, (q15_t)0x198c, (q15_t)0x192a, + (q15_t)0x18c7, (q15_t)0x1864, (q15_t)0x1802, (q15_t)0x179f, (q15_t)0x173c, (q15_t)0x16d9, (q15_t)0x1676, (q15_t)0x1613, + (q15_t)0x15b0, (q15_t)0x154d, (q15_t)0x14ea, (q15_t)0x1487, (q15_t)0x1423, (q15_t)0x13c0, (q15_t)0x135d, (q15_t)0x12f9, + (q15_t)0x1296, (q15_t)0x1232, (q15_t)0x11cf, (q15_t)0x116b, (q15_t)0x1108, (q15_t)0x10a4, (q15_t)0x1040, (q15_t)0xfdd, + (q15_t)0xf79, (q15_t)0xf15, (q15_t)0xeb1, (q15_t)0xe4d, (q15_t)0xde9, (q15_t)0xd85, (q15_t)0xd21, (q15_t)0xcbd, + (q15_t)0xc59, (q15_t)0xbf5, (q15_t)0xb91, (q15_t)0xb2d, (q15_t)0xac9, (q15_t)0xa65, (q15_t)0xa00, (q15_t)0x99c, + (q15_t)0x938, (q15_t)0x8d4, (q15_t)0x86f, (q15_t)0x80b, (q15_t)0x7a7, (q15_t)0x742, (q15_t)0x6de, (q15_t)0x67a, + (q15_t)0x615, (q15_t)0x5b1, (q15_t)0x54c, (q15_t)0x4e8, (q15_t)0x483, (q15_t)0x41f, (q15_t)0x3ba, (q15_t)0x356, + (q15_t)0x2f1, (q15_t)0x28d, (q15_t)0x228, (q15_t)0x1c4, (q15_t)0x15f, (q15_t)0xfb, (q15_t)0x96, (q15_t)0x32 +}; + + #endif + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_DCT4_Q15_2048) + const q15_t __ALIGNED(4) WeightsQ15_2048[4096] = { + (q15_t)0x7fff, (q15_t)0x0, (q15_t)0x7fff, (q15_t)0xffe7, (q15_t)0x7fff, (q15_t)0xffce, (q15_t)0x7fff, (q15_t)0xffb5, + (q15_t)0x7fff, (q15_t)0xff9c, (q15_t)0x7fff, (q15_t)0xff83, (q15_t)0x7fff, (q15_t)0xff6a, (q15_t)0x7fff, (q15_t)0xff51, + (q15_t)0x7fff, (q15_t)0xff37, (q15_t)0x7fff, (q15_t)0xff1e, (q15_t)0x7fff, (q15_t)0xff05, (q15_t)0x7ffe, (q15_t)0xfeec, + (q15_t)0x7ffe, (q15_t)0xfed3, (q15_t)0x7ffe, (q15_t)0xfeba, (q15_t)0x7ffe, (q15_t)0xfea1, (q15_t)0x7ffd, (q15_t)0xfe88, + (q15_t)0x7ffd, (q15_t)0xfe6e, (q15_t)0x7ffd, (q15_t)0xfe55, (q15_t)0x7ffc, (q15_t)0xfe3c, (q15_t)0x7ffc, (q15_t)0xfe23, + (q15_t)0x7ffc, (q15_t)0xfe0a, (q15_t)0x7ffb, (q15_t)0xfdf1, (q15_t)0x7ffb, (q15_t)0xfdd8, (q15_t)0x7ffa, (q15_t)0xfdbe, + (q15_t)0x7ffa, (q15_t)0xfda5, (q15_t)0x7ff9, (q15_t)0xfd8c, (q15_t)0x7ff9, (q15_t)0xfd73, (q15_t)0x7ff8, (q15_t)0xfd5a, + (q15_t)0x7ff8, (q15_t)0xfd41, (q15_t)0x7ff7, (q15_t)0xfd28, (q15_t)0x7ff7, (q15_t)0xfd0f, (q15_t)0x7ff6, (q15_t)0xfcf5, + (q15_t)0x7ff6, (q15_t)0xfcdc, (q15_t)0x7ff5, (q15_t)0xfcc3, (q15_t)0x7ff4, (q15_t)0xfcaa, (q15_t)0x7ff4, (q15_t)0xfc91, + (q15_t)0x7ff3, (q15_t)0xfc78, (q15_t)0x7ff2, (q15_t)0xfc5f, (q15_t)0x7ff2, (q15_t)0xfc46, (q15_t)0x7ff1, (q15_t)0xfc2c, + (q15_t)0x7ff0, (q15_t)0xfc13, (q15_t)0x7fef, (q15_t)0xfbfa, (q15_t)0x7fee, (q15_t)0xfbe1, (q15_t)0x7fee, (q15_t)0xfbc8, + (q15_t)0x7fed, (q15_t)0xfbaf, (q15_t)0x7fec, (q15_t)0xfb96, (q15_t)0x7feb, (q15_t)0xfb7d, (q15_t)0x7fea, (q15_t)0xfb64, + (q15_t)0x7fe9, (q15_t)0xfb4a, (q15_t)0x7fe8, (q15_t)0xfb31, (q15_t)0x7fe7, (q15_t)0xfb18, (q15_t)0x7fe6, (q15_t)0xfaff, + (q15_t)0x7fe5, (q15_t)0xfae6, (q15_t)0x7fe4, (q15_t)0xfacd, (q15_t)0x7fe3, (q15_t)0xfab4, (q15_t)0x7fe2, (q15_t)0xfa9b, + (q15_t)0x7fe1, (q15_t)0xfa81, (q15_t)0x7fe0, (q15_t)0xfa68, (q15_t)0x7fdf, (q15_t)0xfa4f, (q15_t)0x7fde, (q15_t)0xfa36, + (q15_t)0x7fdd, (q15_t)0xfa1d, (q15_t)0x7fdc, (q15_t)0xfa04, (q15_t)0x7fda, (q15_t)0xf9eb, (q15_t)0x7fd9, (q15_t)0xf9d2, + (q15_t)0x7fd8, (q15_t)0xf9b9, (q15_t)0x7fd7, (q15_t)0xf9a0, (q15_t)0x7fd6, (q15_t)0xf986, (q15_t)0x7fd4, (q15_t)0xf96d, + (q15_t)0x7fd3, (q15_t)0xf954, (q15_t)0x7fd2, (q15_t)0xf93b, (q15_t)0x7fd0, (q15_t)0xf922, (q15_t)0x7fcf, (q15_t)0xf909, + (q15_t)0x7fce, (q15_t)0xf8f0, (q15_t)0x7fcc, (q15_t)0xf8d7, (q15_t)0x7fcb, (q15_t)0xf8be, (q15_t)0x7fc9, (q15_t)0xf8a5, + (q15_t)0x7fc8, (q15_t)0xf88b, (q15_t)0x7fc6, (q15_t)0xf872, (q15_t)0x7fc5, (q15_t)0xf859, (q15_t)0x7fc3, (q15_t)0xf840, + (q15_t)0x7fc2, (q15_t)0xf827, (q15_t)0x7fc0, (q15_t)0xf80e, (q15_t)0x7fbf, (q15_t)0xf7f5, (q15_t)0x7fbd, (q15_t)0xf7dc, + (q15_t)0x7fbc, (q15_t)0xf7c3, (q15_t)0x7fba, (q15_t)0xf7aa, (q15_t)0x7fb8, (q15_t)0xf791, (q15_t)0x7fb7, (q15_t)0xf778, + (q15_t)0x7fb5, (q15_t)0xf75e, (q15_t)0x7fb3, (q15_t)0xf745, (q15_t)0x7fb1, (q15_t)0xf72c, (q15_t)0x7fb0, (q15_t)0xf713, + (q15_t)0x7fae, (q15_t)0xf6fa, (q15_t)0x7fac, (q15_t)0xf6e1, (q15_t)0x7faa, (q15_t)0xf6c8, (q15_t)0x7fa9, (q15_t)0xf6af, + (q15_t)0x7fa7, (q15_t)0xf696, (q15_t)0x7fa5, (q15_t)0xf67d, (q15_t)0x7fa3, (q15_t)0xf664, (q15_t)0x7fa1, (q15_t)0xf64b, + (q15_t)0x7f9f, (q15_t)0xf632, (q15_t)0x7f9d, (q15_t)0xf619, (q15_t)0x7f9b, (q15_t)0xf600, (q15_t)0x7f99, (q15_t)0xf5e7, + (q15_t)0x7f97, (q15_t)0xf5cd, (q15_t)0x7f95, (q15_t)0xf5b4, (q15_t)0x7f93, (q15_t)0xf59b, (q15_t)0x7f91, (q15_t)0xf582, + (q15_t)0x7f8f, (q15_t)0xf569, (q15_t)0x7f8d, (q15_t)0xf550, (q15_t)0x7f8b, (q15_t)0xf537, (q15_t)0x7f89, (q15_t)0xf51e, + (q15_t)0x7f87, (q15_t)0xf505, (q15_t)0x7f85, (q15_t)0xf4ec, (q15_t)0x7f82, (q15_t)0xf4d3, (q15_t)0x7f80, (q15_t)0xf4ba, + (q15_t)0x7f7e, (q15_t)0xf4a1, (q15_t)0x7f7c, (q15_t)0xf488, (q15_t)0x7f79, (q15_t)0xf46f, (q15_t)0x7f77, (q15_t)0xf456, + (q15_t)0x7f75, (q15_t)0xf43d, (q15_t)0x7f72, (q15_t)0xf424, (q15_t)0x7f70, (q15_t)0xf40b, (q15_t)0x7f6e, (q15_t)0xf3f2, + (q15_t)0x7f6b, (q15_t)0xf3d9, (q15_t)0x7f69, (q15_t)0xf3c0, (q15_t)0x7f67, (q15_t)0xf3a7, (q15_t)0x7f64, (q15_t)0xf38e, + (q15_t)0x7f62, (q15_t)0xf375, (q15_t)0x7f5f, (q15_t)0xf35c, (q15_t)0x7f5d, (q15_t)0xf343, (q15_t)0x7f5a, (q15_t)0xf32a, + (q15_t)0x7f58, (q15_t)0xf311, (q15_t)0x7f55, (q15_t)0xf2f8, (q15_t)0x7f53, (q15_t)0xf2df, (q15_t)0x7f50, (q15_t)0xf2c6, + (q15_t)0x7f4d, (q15_t)0xf2ad, (q15_t)0x7f4b, (q15_t)0xf294, (q15_t)0x7f48, (q15_t)0xf27b, (q15_t)0x7f45, (q15_t)0xf262, + (q15_t)0x7f43, (q15_t)0xf249, (q15_t)0x7f40, (q15_t)0xf230, (q15_t)0x7f3d, (q15_t)0xf217, (q15_t)0x7f3b, (q15_t)0xf1fe, + (q15_t)0x7f38, (q15_t)0xf1e5, (q15_t)0x7f35, (q15_t)0xf1cc, (q15_t)0x7f32, (q15_t)0xf1b3, (q15_t)0x7f2f, (q15_t)0xf19a, + (q15_t)0x7f2d, (q15_t)0xf181, (q15_t)0x7f2a, (q15_t)0xf168, (q15_t)0x7f27, (q15_t)0xf14f, (q15_t)0x7f24, (q15_t)0xf136, + (q15_t)0x7f21, (q15_t)0xf11d, (q15_t)0x7f1e, (q15_t)0xf104, (q15_t)0x7f1b, (q15_t)0xf0eb, (q15_t)0x7f18, (q15_t)0xf0d2, + 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(q15_t)0x8067, (q15_t)0xa00, (q15_t)0x8065, (q15_t)0x9e7, (q15_t)0x8063, + (q15_t)0x9ce, (q15_t)0x8061, (q15_t)0x9b5, (q15_t)0x805f, (q15_t)0x99c, (q15_t)0x805d, (q15_t)0x983, (q15_t)0x805b, + (q15_t)0x96a, (q15_t)0x8059, (q15_t)0x951, (q15_t)0x8057, (q15_t)0x938, (q15_t)0x8056, (q15_t)0x91f, (q15_t)0x8054, + (q15_t)0x906, (q15_t)0x8052, (q15_t)0x8ed, (q15_t)0x8050, (q15_t)0x8d4, (q15_t)0x804f, (q15_t)0x8bb, (q15_t)0x804d, + (q15_t)0x8a2, (q15_t)0x804b, (q15_t)0x888, (q15_t)0x8049, (q15_t)0x86f, (q15_t)0x8048, (q15_t)0x856, (q15_t)0x8046, + (q15_t)0x83d, (q15_t)0x8044, (q15_t)0x824, (q15_t)0x8043, (q15_t)0x80b, (q15_t)0x8041, (q15_t)0x7f2, (q15_t)0x8040, + (q15_t)0x7d9, (q15_t)0x803e, (q15_t)0x7c0, (q15_t)0x803d, (q15_t)0x7a7, (q15_t)0x803b, (q15_t)0x78e, (q15_t)0x803a, + (q15_t)0x775, (q15_t)0x8038, (q15_t)0x75b, (q15_t)0x8037, (q15_t)0x742, (q15_t)0x8035, (q15_t)0x729, (q15_t)0x8034, + (q15_t)0x710, (q15_t)0x8032, (q15_t)0x6f7, (q15_t)0x8031, (q15_t)0x6de, (q15_t)0x8030, (q15_t)0x6c5, (q15_t)0x802e, + (q15_t)0x6ac, (q15_t)0x802d, (q15_t)0x693, (q15_t)0x802c, (q15_t)0x67a, (q15_t)0x802a, (q15_t)0x660, (q15_t)0x8029, + (q15_t)0x647, (q15_t)0x8028, (q15_t)0x62e, (q15_t)0x8027, (q15_t)0x615, (q15_t)0x8026, (q15_t)0x5fc, (q15_t)0x8024, + (q15_t)0x5e3, (q15_t)0x8023, (q15_t)0x5ca, (q15_t)0x8022, (q15_t)0x5b1, (q15_t)0x8021, (q15_t)0x598, (q15_t)0x8020, + (q15_t)0x57f, (q15_t)0x801f, (q15_t)0x565, (q15_t)0x801e, (q15_t)0x54c, (q15_t)0x801d, (q15_t)0x533, (q15_t)0x801c, + (q15_t)0x51a, (q15_t)0x801b, (q15_t)0x501, (q15_t)0x801a, (q15_t)0x4e8, (q15_t)0x8019, (q15_t)0x4cf, (q15_t)0x8018, + (q15_t)0x4b6, (q15_t)0x8017, (q15_t)0x49c, (q15_t)0x8016, (q15_t)0x483, (q15_t)0x8015, (q15_t)0x46a, (q15_t)0x8014, + (q15_t)0x451, (q15_t)0x8013, (q15_t)0x438, (q15_t)0x8012, (q15_t)0x41f, (q15_t)0x8012, (q15_t)0x406, (q15_t)0x8011, + (q15_t)0x3ed, (q15_t)0x8010, (q15_t)0x3d4, (q15_t)0x800f, (q15_t)0x3ba, (q15_t)0x800e, (q15_t)0x3a1, (q15_t)0x800e, + (q15_t)0x388, (q15_t)0x800d, (q15_t)0x36f, (q15_t)0x800c, (q15_t)0x356, (q15_t)0x800c, (q15_t)0x33d, (q15_t)0x800b, + (q15_t)0x324, (q15_t)0x800a, (q15_t)0x30b, (q15_t)0x800a, (q15_t)0x2f1, (q15_t)0x8009, (q15_t)0x2d8, (q15_t)0x8009, + (q15_t)0x2bf, (q15_t)0x8008, (q15_t)0x2a6, (q15_t)0x8008, (q15_t)0x28d, (q15_t)0x8007, (q15_t)0x274, (q15_t)0x8007, + (q15_t)0x25b, (q15_t)0x8006, (q15_t)0x242, (q15_t)0x8006, (q15_t)0x228, (q15_t)0x8005, (q15_t)0x20f, (q15_t)0x8005, + (q15_t)0x1f6, (q15_t)0x8004, (q15_t)0x1dd, (q15_t)0x8004, (q15_t)0x1c4, (q15_t)0x8004, (q15_t)0x1ab, (q15_t)0x8003, + (q15_t)0x192, (q15_t)0x8003, (q15_t)0x178, (q15_t)0x8003, (q15_t)0x15f, (q15_t)0x8002, (q15_t)0x146, (q15_t)0x8002, + (q15_t)0x12d, (q15_t)0x8002, (q15_t)0x114, (q15_t)0x8002, (q15_t)0xfb, (q15_t)0x8001, (q15_t)0xe2, (q15_t)0x8001, + (q15_t)0xc9, (q15_t)0x8001, (q15_t)0xaf, (q15_t)0x8001, (q15_t)0x96, (q15_t)0x8001, (q15_t)0x7d, (q15_t)0x8001, + (q15_t)0x64, (q15_t)0x8001, (q15_t)0x4b, (q15_t)0x8001, (q15_t)0x32, (q15_t)0x8001, (q15_t)0x19, (q15_t)0x8001 +}; + const q15_t __ALIGNED(4) cos_factorsQ15_2048[2048] = { + (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, + (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffd, (q15_t)0x7ffd, + (q15_t)0x7ffd, (q15_t)0x7ffd, (q15_t)0x7ffc, (q15_t)0x7ffc, (q15_t)0x7ffb, (q15_t)0x7ffb, (q15_t)0x7ffb, (q15_t)0x7ffa, + (q15_t)0x7ffa, (q15_t)0x7ff9, (q15_t)0x7ff9, (q15_t)0x7ff8, (q15_t)0x7ff8, (q15_t)0x7ff7, (q15_t)0x7ff7, (q15_t)0x7ff6, + (q15_t)0x7ff5, (q15_t)0x7ff5, (q15_t)0x7ff4, (q15_t)0x7ff3, (q15_t)0x7ff3, (q15_t)0x7ff2, (q15_t)0x7ff1, (q15_t)0x7ff0, + (q15_t)0x7ff0, (q15_t)0x7fef, (q15_t)0x7fee, (q15_t)0x7fed, (q15_t)0x7fec, (q15_t)0x7fec, (q15_t)0x7feb, (q15_t)0x7fea, + (q15_t)0x7fe9, (q15_t)0x7fe8, (q15_t)0x7fe7, (q15_t)0x7fe6, (q15_t)0x7fe5, (q15_t)0x7fe4, (q15_t)0x7fe3, (q15_t)0x7fe2, + (q15_t)0x7fe1, (q15_t)0x7fe0, (q15_t)0x7fdf, (q15_t)0x7fdd, (q15_t)0x7fdc, (q15_t)0x7fdb, (q15_t)0x7fda, (q15_t)0x7fd9, + (q15_t)0x7fd7, (q15_t)0x7fd6, (q15_t)0x7fd5, (q15_t)0x7fd4, (q15_t)0x7fd2, (q15_t)0x7fd1, (q15_t)0x7fd0, (q15_t)0x7fce, + (q15_t)0x7fcd, (q15_t)0x7fcb, (q15_t)0x7fca, (q15_t)0x7fc9, (q15_t)0x7fc7, (q15_t)0x7fc6, (q15_t)0x7fc4, (q15_t)0x7fc3, + (q15_t)0x7fc1, (q15_t)0x7fc0, (q15_t)0x7fbe, (q15_t)0x7fbc, (q15_t)0x7fbb, (q15_t)0x7fb9, (q15_t)0x7fb7, (q15_t)0x7fb6, + (q15_t)0x7fb4, (q15_t)0x7fb2, (q15_t)0x7fb1, (q15_t)0x7faf, (q15_t)0x7fad, (q15_t)0x7fab, (q15_t)0x7fa9, (q15_t)0x7fa8, + (q15_t)0x7fa6, (q15_t)0x7fa4, (q15_t)0x7fa2, (q15_t)0x7fa0, (q15_t)0x7f9e, (q15_t)0x7f9c, (q15_t)0x7f9a, (q15_t)0x7f98, + (q15_t)0x7f96, (q15_t)0x7f94, (q15_t)0x7f92, (q15_t)0x7f90, (q15_t)0x7f8e, (q15_t)0x7f8c, (q15_t)0x7f8a, (q15_t)0x7f88, + (q15_t)0x7f86, (q15_t)0x7f83, (q15_t)0x7f81, (q15_t)0x7f7f, (q15_t)0x7f7d, (q15_t)0x7f7b, (q15_t)0x7f78, (q15_t)0x7f76, + (q15_t)0x7f74, (q15_t)0x7f71, (q15_t)0x7f6f, (q15_t)0x7f6d, (q15_t)0x7f6a, (q15_t)0x7f68, (q15_t)0x7f65, (q15_t)0x7f63, + (q15_t)0x7f60, (q15_t)0x7f5e, (q15_t)0x7f5b, (q15_t)0x7f59, (q15_t)0x7f56, (q15_t)0x7f54, (q15_t)0x7f51, (q15_t)0x7f4f, + (q15_t)0x7f4c, (q15_t)0x7f49, (q15_t)0x7f47, (q15_t)0x7f44, (q15_t)0x7f41, (q15_t)0x7f3f, (q15_t)0x7f3c, (q15_t)0x7f39, + (q15_t)0x7f36, (q15_t)0x7f34, (q15_t)0x7f31, (q15_t)0x7f2e, (q15_t)0x7f2b, (q15_t)0x7f28, (q15_t)0x7f25, (q15_t)0x7f23, + (q15_t)0x7f20, (q15_t)0x7f1d, (q15_t)0x7f1a, (q15_t)0x7f17, (q15_t)0x7f14, (q15_t)0x7f11, (q15_t)0x7f0e, (q15_t)0x7f0b, + (q15_t)0x7f08, (q15_t)0x7f04, (q15_t)0x7f01, (q15_t)0x7efe, (q15_t)0x7efb, (q15_t)0x7ef8, (q15_t)0x7ef5, (q15_t)0x7ef1, + (q15_t)0x7eee, (q15_t)0x7eeb, (q15_t)0x7ee8, (q15_t)0x7ee4, (q15_t)0x7ee1, (q15_t)0x7ede, (q15_t)0x7eda, (q15_t)0x7ed7, + (q15_t)0x7ed4, (q15_t)0x7ed0, (q15_t)0x7ecd, (q15_t)0x7ec9, (q15_t)0x7ec6, (q15_t)0x7ec3, (q15_t)0x7ebf, (q15_t)0x7ebb, + (q15_t)0x7eb8, (q15_t)0x7eb4, (q15_t)0x7eb1, (q15_t)0x7ead, (q15_t)0x7eaa, (q15_t)0x7ea6, (q15_t)0x7ea2, (q15_t)0x7e9f, + (q15_t)0x7e9b, (q15_t)0x7e97, (q15_t)0x7e94, (q15_t)0x7e90, (q15_t)0x7e8c, (q15_t)0x7e88, (q15_t)0x7e84, (q15_t)0x7e81, + (q15_t)0x7e7d, (q15_t)0x7e79, (q15_t)0x7e75, (q15_t)0x7e71, (q15_t)0x7e6d, (q15_t)0x7e69, (q15_t)0x7e65, (q15_t)0x7e61, + (q15_t)0x7e5d, (q15_t)0x7e59, (q15_t)0x7e55, (q15_t)0x7e51, (q15_t)0x7e4d, (q15_t)0x7e49, (q15_t)0x7e45, (q15_t)0x7e41, + (q15_t)0x7e3d, (q15_t)0x7e39, (q15_t)0x7e34, (q15_t)0x7e30, (q15_t)0x7e2c, (q15_t)0x7e28, (q15_t)0x7e24, (q15_t)0x7e1f, + (q15_t)0x7e1b, (q15_t)0x7e17, (q15_t)0x7e12, (q15_t)0x7e0e, (q15_t)0x7e0a, (q15_t)0x7e05, (q15_t)0x7e01, (q15_t)0x7dfc, + (q15_t)0x7df8, (q15_t)0x7df3, (q15_t)0x7def, (q15_t)0x7dea, (q15_t)0x7de6, (q15_t)0x7de1, (q15_t)0x7ddd, (q15_t)0x7dd8, + (q15_t)0x7dd4, (q15_t)0x7dcf, (q15_t)0x7dca, (q15_t)0x7dc6, (q15_t)0x7dc1, (q15_t)0x7dbc, (q15_t)0x7db8, (q15_t)0x7db3, + (q15_t)0x7dae, (q15_t)0x7da9, (q15_t)0x7da5, (q15_t)0x7da0, (q15_t)0x7d9b, (q15_t)0x7d96, (q15_t)0x7d91, (q15_t)0x7d8c, + (q15_t)0x7d87, (q15_t)0x7d82, (q15_t)0x7d7e, (q15_t)0x7d79, (q15_t)0x7d74, (q15_t)0x7d6f, (q15_t)0x7d6a, (q15_t)0x7d65, + (q15_t)0x7d60, (q15_t)0x7d5a, (q15_t)0x7d55, (q15_t)0x7d50, (q15_t)0x7d4b, (q15_t)0x7d46, (q15_t)0x7d41, (q15_t)0x7d3c, + (q15_t)0x7d36, (q15_t)0x7d31, (q15_t)0x7d2c, (q15_t)0x7d27, (q15_t)0x7d21, (q15_t)0x7d1c, (q15_t)0x7d17, (q15_t)0x7d11, + (q15_t)0x7d0c, (q15_t)0x7d07, (q15_t)0x7d01, (q15_t)0x7cfc, (q15_t)0x7cf6, (q15_t)0x7cf1, (q15_t)0x7cec, (q15_t)0x7ce6, + (q15_t)0x7ce1, (q15_t)0x7cdb, (q15_t)0x7cd5, (q15_t)0x7cd0, (q15_t)0x7cca, (q15_t)0x7cc5, (q15_t)0x7cbf, (q15_t)0x7cb9, + (q15_t)0x7cb4, (q15_t)0x7cae, (q15_t)0x7ca8, (q15_t)0x7ca3, (q15_t)0x7c9d, (q15_t)0x7c97, (q15_t)0x7c91, (q15_t)0x7c8c, + (q15_t)0x7c86, (q15_t)0x7c80, (q15_t)0x7c7a, (q15_t)0x7c74, (q15_t)0x7c6e, (q15_t)0x7c69, (q15_t)0x7c63, (q15_t)0x7c5d, + (q15_t)0x7c57, (q15_t)0x7c51, (q15_t)0x7c4b, (q15_t)0x7c45, (q15_t)0x7c3f, (q15_t)0x7c39, (q15_t)0x7c33, (q15_t)0x7c2d, + (q15_t)0x7c26, (q15_t)0x7c20, (q15_t)0x7c1a, (q15_t)0x7c14, (q15_t)0x7c0e, (q15_t)0x7c08, (q15_t)0x7c01, (q15_t)0x7bfb, + (q15_t)0x7bf5, (q15_t)0x7bef, (q15_t)0x7be8, (q15_t)0x7be2, (q15_t)0x7bdc, (q15_t)0x7bd5, (q15_t)0x7bcf, (q15_t)0x7bc9, + (q15_t)0x7bc2, (q15_t)0x7bbc, (q15_t)0x7bb5, (q15_t)0x7baf, (q15_t)0x7ba8, (q15_t)0x7ba2, (q15_t)0x7b9b, (q15_t)0x7b95, + (q15_t)0x7b8e, (q15_t)0x7b88, (q15_t)0x7b81, (q15_t)0x7b7a, (q15_t)0x7b74, (q15_t)0x7b6d, (q15_t)0x7b67, (q15_t)0x7b60, + (q15_t)0x7b59, (q15_t)0x7b52, (q15_t)0x7b4c, (q15_t)0x7b45, (q15_t)0x7b3e, (q15_t)0x7b37, (q15_t)0x7b31, (q15_t)0x7b2a, + (q15_t)0x7b23, (q15_t)0x7b1c, (q15_t)0x7b15, (q15_t)0x7b0e, (q15_t)0x7b07, (q15_t)0x7b00, (q15_t)0x7af9, (q15_t)0x7af2, + (q15_t)0x7aeb, (q15_t)0x7ae4, (q15_t)0x7add, (q15_t)0x7ad6, (q15_t)0x7acf, (q15_t)0x7ac8, (q15_t)0x7ac1, (q15_t)0x7aba, + (q15_t)0x7ab3, (q15_t)0x7aac, (q15_t)0x7aa4, (q15_t)0x7a9d, (q15_t)0x7a96, (q15_t)0x7a8f, (q15_t)0x7a87, (q15_t)0x7a80, + (q15_t)0x7a79, (q15_t)0x7a72, (q15_t)0x7a6a, (q15_t)0x7a63, (q15_t)0x7a5c, (q15_t)0x7a54, (q15_t)0x7a4d, (q15_t)0x7a45, + (q15_t)0x7a3e, (q15_t)0x7a36, (q15_t)0x7a2f, (q15_t)0x7a27, (q15_t)0x7a20, (q15_t)0x7a18, (q15_t)0x7a11, (q15_t)0x7a09, + (q15_t)0x7a02, (q15_t)0x79fa, (q15_t)0x79f2, (q15_t)0x79eb, (q15_t)0x79e3, (q15_t)0x79db, (q15_t)0x79d4, (q15_t)0x79cc, + (q15_t)0x79c4, (q15_t)0x79bc, (q15_t)0x79b5, (q15_t)0x79ad, (q15_t)0x79a5, (q15_t)0x799d, (q15_t)0x7995, (q15_t)0x798e, + (q15_t)0x7986, (q15_t)0x797e, (q15_t)0x7976, (q15_t)0x796e, (q15_t)0x7966, (q15_t)0x795e, (q15_t)0x7956, (q15_t)0x794e, + (q15_t)0x7946, (q15_t)0x793e, (q15_t)0x7936, (q15_t)0x792e, (q15_t)0x7926, (q15_t)0x791e, (q15_t)0x7915, (q15_t)0x790d, + (q15_t)0x7905, (q15_t)0x78fd, (q15_t)0x78f5, (q15_t)0x78ec, (q15_t)0x78e4, (q15_t)0x78dc, (q15_t)0x78d4, (q15_t)0x78cb, + (q15_t)0x78c3, (q15_t)0x78bb, (q15_t)0x78b2, (q15_t)0x78aa, (q15_t)0x78a2, (q15_t)0x7899, (q15_t)0x7891, (q15_t)0x7888, + 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(q15_t)0x1098, (q15_t)0x107f, + (q15_t)0x1066, (q15_t)0x104d, (q15_t)0x1034, (q15_t)0x101b, (q15_t)0x1002, (q15_t)0xfe9, (q15_t)0xfd0, (q15_t)0xfb7, + (q15_t)0xf9e, (q15_t)0xf85, (q15_t)0xf6c, (q15_t)0xf53, (q15_t)0xf3a, (q15_t)0xf21, (q15_t)0xf08, (q15_t)0xef0, + (q15_t)0xed7, (q15_t)0xebe, (q15_t)0xea5, (q15_t)0xe8c, (q15_t)0xe73, (q15_t)0xe5a, (q15_t)0xe41, (q15_t)0xe28, + (q15_t)0xe0f, (q15_t)0xdf6, (q15_t)0xddd, (q15_t)0xdc4, (q15_t)0xdab, (q15_t)0xd92, (q15_t)0xd79, (q15_t)0xd60, + (q15_t)0xd47, (q15_t)0xd2e, (q15_t)0xd15, (q15_t)0xcfc, (q15_t)0xce3, (q15_t)0xcca, (q15_t)0xcb1, (q15_t)0xc98, + (q15_t)0xc7f, (q15_t)0xc66, (q15_t)0xc4d, (q15_t)0xc34, (q15_t)0xc1b, (q15_t)0xc02, (q15_t)0xbe9, (q15_t)0xbd0, + (q15_t)0xbb7, (q15_t)0xb9e, (q15_t)0xb85, (q15_t)0xb6c, (q15_t)0xb53, (q15_t)0xb3a, (q15_t)0xb20, (q15_t)0xb07, + (q15_t)0xaee, (q15_t)0xad5, (q15_t)0xabc, (q15_t)0xaa3, (q15_t)0xa8a, (q15_t)0xa71, (q15_t)0xa58, (q15_t)0xa3f, + (q15_t)0xa26, (q15_t)0xa0d, (q15_t)0x9f4, (q15_t)0x9db, (q15_t)0x9c2, (q15_t)0x9a9, (q15_t)0x990, (q15_t)0x977, + (q15_t)0x95e, (q15_t)0x944, (q15_t)0x92b, (q15_t)0x912, (q15_t)0x8f9, (q15_t)0x8e0, (q15_t)0x8c7, (q15_t)0x8ae, + (q15_t)0x895, (q15_t)0x87c, (q15_t)0x863, (q15_t)0x84a, (q15_t)0x831, (q15_t)0x818, (q15_t)0x7fe, (q15_t)0x7e5, + (q15_t)0x7cc, (q15_t)0x7b3, (q15_t)0x79a, (q15_t)0x781, (q15_t)0x768, (q15_t)0x74f, (q15_t)0x736, (q15_t)0x71d, + (q15_t)0x704, (q15_t)0x6ea, (q15_t)0x6d1, (q15_t)0x6b8, (q15_t)0x69f, (q15_t)0x686, (q15_t)0x66d, (q15_t)0x654, + (q15_t)0x63b, (q15_t)0x622, (q15_t)0x609, (q15_t)0x5ef, (q15_t)0x5d6, (q15_t)0x5bd, (q15_t)0x5a4, (q15_t)0x58b, + (q15_t)0x572, (q15_t)0x559, (q15_t)0x540, (q15_t)0x527, (q15_t)0x50d, (q15_t)0x4f4, (q15_t)0x4db, (q15_t)0x4c2, + (q15_t)0x4a9, (q15_t)0x490, (q15_t)0x477, (q15_t)0x45e, (q15_t)0x445, (q15_t)0x42b, (q15_t)0x412, (q15_t)0x3f9, + (q15_t)0x3e0, (q15_t)0x3c7, (q15_t)0x3ae, (q15_t)0x395, (q15_t)0x37c, (q15_t)0x362, (q15_t)0x349, (q15_t)0x330, + (q15_t)0x317, (q15_t)0x2fe, (q15_t)0x2e5, (q15_t)0x2cc, (q15_t)0x2b3, (q15_t)0x299, (q15_t)0x280, (q15_t)0x267, + (q15_t)0x24e, (q15_t)0x235, (q15_t)0x21c, (q15_t)0x203, (q15_t)0x1ea, (q15_t)0x1d0, (q15_t)0x1b7, (q15_t)0x19e, + (q15_t)0x185, (q15_t)0x16c, (q15_t)0x153, (q15_t)0x13a, (q15_t)0x121, (q15_t)0x107, (q15_t)0xee, (q15_t)0xd5, + (q15_t)0xbc, (q15_t)0xa3, (q15_t)0x8a, (q15_t)0x71, (q15_t)0x57, (q15_t)0x3e, (q15_t)0x25, (q15_t)0xc + +}; + #endif + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_DCT4_Q15_8192) + const q15_t __ALIGNED(4) WeightsQ15_8192[16384] = { + (q15_t)0x7fff, (q15_t)0x0, (q15_t)0x7fff, (q15_t)0xfffa, (q15_t)0x7fff, (q15_t)0xfff4, (q15_t)0x7fff, (q15_t)0xffee, + (q15_t)0x7fff, (q15_t)0xffe7, (q15_t)0x7fff, (q15_t)0xffe1, (q15_t)0x7fff, (q15_t)0xffdb, (q15_t)0x7fff, (q15_t)0xffd5, + (q15_t)0x7fff, (q15_t)0xffce, (q15_t)0x7fff, (q15_t)0xffc8, (q15_t)0x7fff, (q15_t)0xffc2, (q15_t)0x7fff, (q15_t)0xffbb, + (q15_t)0x7fff, (q15_t)0xffb5, (q15_t)0x7fff, (q15_t)0xffaf, (q15_t)0x7fff, (q15_t)0xffa9, (q15_t)0x7fff, (q15_t)0xffa2, + (q15_t)0x7fff, (q15_t)0xff9c, (q15_t)0x7fff, (q15_t)0xff96, (q15_t)0x7fff, (q15_t)0xff8f, (q15_t)0x7fff, (q15_t)0xff89, + (q15_t)0x7fff, (q15_t)0xff83, (q15_t)0x7fff, (q15_t)0xff7d, (q15_t)0x7fff, (q15_t)0xff76, (q15_t)0x7fff, (q15_t)0xff70, + (q15_t)0x7fff, (q15_t)0xff6a, (q15_t)0x7fff, (q15_t)0xff63, (q15_t)0x7fff, (q15_t)0xff5d, (q15_t)0x7fff, (q15_t)0xff57, + (q15_t)0x7fff, (q15_t)0xff51, (q15_t)0x7fff, (q15_t)0xff4a, (q15_t)0x7fff, (q15_t)0xff44, (q15_t)0x7fff, (q15_t)0xff3e, + (q15_t)0x7fff, (q15_t)0xff37, (q15_t)0x7fff, (q15_t)0xff31, (q15_t)0x7fff, (q15_t)0xff2b, (q15_t)0x7fff, (q15_t)0xff25, + (q15_t)0x7fff, (q15_t)0xff1e, (q15_t)0x7fff, (q15_t)0xff18, (q15_t)0x7fff, (q15_t)0xff12, (q15_t)0x7fff, (q15_t)0xff0b, + (q15_t)0x7fff, (q15_t)0xff05, (q15_t)0x7ffe, (q15_t)0xfeff, (q15_t)0x7ffe, (q15_t)0xfef9, (q15_t)0x7ffe, (q15_t)0xfef2, + (q15_t)0x7ffe, (q15_t)0xfeec, (q15_t)0x7ffe, (q15_t)0xfee6, (q15_t)0x7ffe, (q15_t)0xfedf, (q15_t)0x7ffe, (q15_t)0xfed9, + (q15_t)0x7ffe, (q15_t)0xfed3, (q15_t)0x7ffe, (q15_t)0xfecd, (q15_t)0x7ffe, (q15_t)0xfec6, (q15_t)0x7ffe, (q15_t)0xfec0, + (q15_t)0x7ffe, (q15_t)0xfeba, (q15_t)0x7ffe, (q15_t)0xfeb3, (q15_t)0x7ffe, (q15_t)0xfead, (q15_t)0x7ffe, (q15_t)0xfea7, + (q15_t)0x7ffe, (q15_t)0xfea1, (q15_t)0x7ffe, (q15_t)0xfe9a, (q15_t)0x7ffd, (q15_t)0xfe94, (q15_t)0x7ffd, (q15_t)0xfe8e, + (q15_t)0x7ffd, (q15_t)0xfe88, (q15_t)0x7ffd, (q15_t)0xfe81, (q15_t)0x7ffd, (q15_t)0xfe7b, (q15_t)0x7ffd, (q15_t)0xfe75, + (q15_t)0x7ffd, (q15_t)0xfe6e, (q15_t)0x7ffd, (q15_t)0xfe68, (q15_t)0x7ffd, (q15_t)0xfe62, (q15_t)0x7ffd, (q15_t)0xfe5c, + (q15_t)0x7ffd, (q15_t)0xfe55, (q15_t)0x7ffd, (q15_t)0xfe4f, (q15_t)0x7ffd, (q15_t)0xfe49, (q15_t)0x7ffc, (q15_t)0xfe42, + (q15_t)0x7ffc, (q15_t)0xfe3c, (q15_t)0x7ffc, (q15_t)0xfe36, (q15_t)0x7ffc, (q15_t)0xfe30, (q15_t)0x7ffc, (q15_t)0xfe29, + (q15_t)0x7ffc, (q15_t)0xfe23, (q15_t)0x7ffc, (q15_t)0xfe1d, (q15_t)0x7ffc, (q15_t)0xfe16, (q15_t)0x7ffc, (q15_t)0xfe10, + (q15_t)0x7ffc, (q15_t)0xfe0a, (q15_t)0x7ffc, (q15_t)0xfe04, (q15_t)0x7ffb, (q15_t)0xfdfd, (q15_t)0x7ffb, (q15_t)0xfdf7, + (q15_t)0x7ffb, (q15_t)0xfdf1, (q15_t)0x7ffb, (q15_t)0xfdea, (q15_t)0x7ffb, (q15_t)0xfde4, (q15_t)0x7ffb, (q15_t)0xfdde, + (q15_t)0x7ffb, (q15_t)0xfdd8, (q15_t)0x7ffb, (q15_t)0xfdd1, (q15_t)0x7ffb, (q15_t)0xfdcb, (q15_t)0x7ffb, (q15_t)0xfdc5, + (q15_t)0x7ffa, (q15_t)0xfdbe, (q15_t)0x7ffa, (q15_t)0xfdb8, (q15_t)0x7ffa, (q15_t)0xfdb2, (q15_t)0x7ffa, (q15_t)0xfdac, + (q15_t)0x7ffa, (q15_t)0xfda5, (q15_t)0x7ffa, (q15_t)0xfd9f, (q15_t)0x7ffa, (q15_t)0xfd99, (q15_t)0x7ffa, (q15_t)0xfd93, + (q15_t)0x7ff9, (q15_t)0xfd8c, (q15_t)0x7ff9, (q15_t)0xfd86, (q15_t)0x7ff9, (q15_t)0xfd80, (q15_t)0x7ff9, (q15_t)0xfd79, + (q15_t)0x7ff9, (q15_t)0xfd73, (q15_t)0x7ff9, (q15_t)0xfd6d, (q15_t)0x7ff9, (q15_t)0xfd67, (q15_t)0x7ff9, (q15_t)0xfd60, + (q15_t)0x7ff8, (q15_t)0xfd5a, (q15_t)0x7ff8, (q15_t)0xfd54, (q15_t)0x7ff8, (q15_t)0xfd4d, (q15_t)0x7ff8, (q15_t)0xfd47, + (q15_t)0x7ff8, (q15_t)0xfd41, (q15_t)0x7ff8, (q15_t)0xfd3b, (q15_t)0x7ff8, (q15_t)0xfd34, (q15_t)0x7ff8, (q15_t)0xfd2e, + (q15_t)0x7ff7, (q15_t)0xfd28, (q15_t)0x7ff7, (q15_t)0xfd21, (q15_t)0x7ff7, (q15_t)0xfd1b, (q15_t)0x7ff7, (q15_t)0xfd15, + (q15_t)0x7ff7, (q15_t)0xfd0f, (q15_t)0x7ff7, (q15_t)0xfd08, (q15_t)0x7ff7, (q15_t)0xfd02, (q15_t)0x7ff6, (q15_t)0xfcfc, + (q15_t)0x7ff6, (q15_t)0xfcf5, (q15_t)0x7ff6, (q15_t)0xfcef, (q15_t)0x7ff6, (q15_t)0xfce9, (q15_t)0x7ff6, (q15_t)0xfce3, + (q15_t)0x7ff6, (q15_t)0xfcdc, (q15_t)0x7ff5, (q15_t)0xfcd6, (q15_t)0x7ff5, (q15_t)0xfcd0, (q15_t)0x7ff5, (q15_t)0xfcc9, + (q15_t)0x7ff5, (q15_t)0xfcc3, (q15_t)0x7ff5, (q15_t)0xfcbd, (q15_t)0x7ff5, (q15_t)0xfcb7, (q15_t)0x7ff5, (q15_t)0xfcb0, + (q15_t)0x7ff4, (q15_t)0xfcaa, (q15_t)0x7ff4, (q15_t)0xfca4, (q15_t)0x7ff4, (q15_t)0xfc9e, (q15_t)0x7ff4, (q15_t)0xfc97, + (q15_t)0x7ff4, (q15_t)0xfc91, (q15_t)0x7ff4, (q15_t)0xfc8b, (q15_t)0x7ff3, (q15_t)0xfc84, (q15_t)0x7ff3, (q15_t)0xfc7e, + (q15_t)0x7ff3, (q15_t)0xfc78, (q15_t)0x7ff3, (q15_t)0xfc72, (q15_t)0x7ff3, (q15_t)0xfc6b, (q15_t)0x7ff2, (q15_t)0xfc65, + (q15_t)0x7ff2, (q15_t)0xfc5f, (q15_t)0x7ff2, (q15_t)0xfc58, (q15_t)0x7ff2, (q15_t)0xfc52, (q15_t)0x7ff2, (q15_t)0xfc4c, + (q15_t)0x7ff2, (q15_t)0xfc46, (q15_t)0x7ff1, (q15_t)0xfc3f, (q15_t)0x7ff1, (q15_t)0xfc39, (q15_t)0x7ff1, (q15_t)0xfc33, + (q15_t)0x7ff1, (q15_t)0xfc2c, (q15_t)0x7ff1, (q15_t)0xfc26, (q15_t)0x7ff0, (q15_t)0xfc20, (q15_t)0x7ff0, (q15_t)0xfc1a, + (q15_t)0x7ff0, (q15_t)0xfc13, (q15_t)0x7ff0, (q15_t)0xfc0d, (q15_t)0x7ff0, (q15_t)0xfc07, (q15_t)0x7fef, (q15_t)0xfc01, + (q15_t)0x7fef, (q15_t)0xfbfa, (q15_t)0x7fef, (q15_t)0xfbf4, (q15_t)0x7fef, (q15_t)0xfbee, (q15_t)0x7fef, (q15_t)0xfbe7, + (q15_t)0x7fee, (q15_t)0xfbe1, (q15_t)0x7fee, (q15_t)0xfbdb, (q15_t)0x7fee, (q15_t)0xfbd5, (q15_t)0x7fee, (q15_t)0xfbce, + (q15_t)0x7fee, (q15_t)0xfbc8, (q15_t)0x7fed, (q15_t)0xfbc2, (q15_t)0x7fed, (q15_t)0xfbbb, (q15_t)0x7fed, (q15_t)0xfbb5, + (q15_t)0x7fed, (q15_t)0xfbaf, (q15_t)0x7fed, (q15_t)0xfba9, (q15_t)0x7fec, (q15_t)0xfba2, (q15_t)0x7fec, (q15_t)0xfb9c, + (q15_t)0x7fec, (q15_t)0xfb96, (q15_t)0x7fec, (q15_t)0xfb8f, (q15_t)0x7fec, (q15_t)0xfb89, (q15_t)0x7feb, (q15_t)0xfb83, + (q15_t)0x7feb, (q15_t)0xfb7d, (q15_t)0x7feb, (q15_t)0xfb76, (q15_t)0x7feb, (q15_t)0xfb70, (q15_t)0x7fea, (q15_t)0xfb6a, + (q15_t)0x7fea, (q15_t)0xfb64, (q15_t)0x7fea, (q15_t)0xfb5d, (q15_t)0x7fea, (q15_t)0xfb57, (q15_t)0x7fea, (q15_t)0xfb51, + (q15_t)0x7fe9, (q15_t)0xfb4a, (q15_t)0x7fe9, (q15_t)0xfb44, (q15_t)0x7fe9, (q15_t)0xfb3e, (q15_t)0x7fe9, (q15_t)0xfb38, + (q15_t)0x7fe8, (q15_t)0xfb31, (q15_t)0x7fe8, (q15_t)0xfb2b, (q15_t)0x7fe8, (q15_t)0xfb25, (q15_t)0x7fe8, (q15_t)0xfb1e, + (q15_t)0x7fe7, (q15_t)0xfb18, (q15_t)0x7fe7, (q15_t)0xfb12, (q15_t)0x7fe7, (q15_t)0xfb0c, (q15_t)0x7fe7, (q15_t)0xfb05, + (q15_t)0x7fe6, (q15_t)0xfaff, (q15_t)0x7fe6, (q15_t)0xfaf9, (q15_t)0x7fe6, (q15_t)0xfaf3, (q15_t)0x7fe6, (q15_t)0xfaec, + (q15_t)0x7fe5, (q15_t)0xfae6, (q15_t)0x7fe5, (q15_t)0xfae0, (q15_t)0x7fe5, (q15_t)0xfad9, (q15_t)0x7fe5, (q15_t)0xfad3, + (q15_t)0x7fe4, (q15_t)0xfacd, (q15_t)0x7fe4, (q15_t)0xfac7, (q15_t)0x7fe4, (q15_t)0xfac0, (q15_t)0x7fe4, (q15_t)0xfaba, + (q15_t)0x7fe3, (q15_t)0xfab4, (q15_t)0x7fe3, (q15_t)0xfaad, (q15_t)0x7fe3, (q15_t)0xfaa7, (q15_t)0x7fe3, (q15_t)0xfaa1, + (q15_t)0x7fe2, (q15_t)0xfa9b, (q15_t)0x7fe2, (q15_t)0xfa94, (q15_t)0x7fe2, (q15_t)0xfa8e, (q15_t)0x7fe2, (q15_t)0xfa88, + (q15_t)0x7fe1, (q15_t)0xfa81, (q15_t)0x7fe1, (q15_t)0xfa7b, (q15_t)0x7fe1, (q15_t)0xfa75, (q15_t)0x7fe0, (q15_t)0xfa6f, + (q15_t)0x7fe0, (q15_t)0xfa68, (q15_t)0x7fe0, (q15_t)0xfa62, (q15_t)0x7fe0, (q15_t)0xfa5c, (q15_t)0x7fdf, (q15_t)0xfa56, + (q15_t)0x7fdf, (q15_t)0xfa4f, (q15_t)0x7fdf, (q15_t)0xfa49, (q15_t)0x7fdf, (q15_t)0xfa43, (q15_t)0x7fde, (q15_t)0xfa3c, + (q15_t)0x7fde, (q15_t)0xfa36, (q15_t)0x7fde, (q15_t)0xfa30, (q15_t)0x7fdd, (q15_t)0xfa2a, (q15_t)0x7fdd, (q15_t)0xfa23, + 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(q15_t)0x800c, + (q15_t)0x356, (q15_t)0x800c, (q15_t)0x350, (q15_t)0x800b, (q15_t)0x349, (q15_t)0x800b, (q15_t)0x343, (q15_t)0x800b, + (q15_t)0x33d, (q15_t)0x800b, (q15_t)0x337, (q15_t)0x800b, (q15_t)0x330, (q15_t)0x800b, (q15_t)0x32a, (q15_t)0x800b, + (q15_t)0x324, (q15_t)0x800a, (q15_t)0x31d, (q15_t)0x800a, (q15_t)0x317, (q15_t)0x800a, (q15_t)0x311, (q15_t)0x800a, + (q15_t)0x30b, (q15_t)0x800a, (q15_t)0x304, (q15_t)0x800a, (q15_t)0x2fe, (q15_t)0x8009, (q15_t)0x2f8, (q15_t)0x8009, + (q15_t)0x2f1, (q15_t)0x8009, (q15_t)0x2eb, (q15_t)0x8009, (q15_t)0x2e5, (q15_t)0x8009, (q15_t)0x2df, (q15_t)0x8009, + (q15_t)0x2d8, (q15_t)0x8009, (q15_t)0x2d2, (q15_t)0x8008, (q15_t)0x2cc, (q15_t)0x8008, (q15_t)0x2c5, (q15_t)0x8008, + (q15_t)0x2bf, (q15_t)0x8008, (q15_t)0x2b9, (q15_t)0x8008, (q15_t)0x2b3, (q15_t)0x8008, (q15_t)0x2ac, (q15_t)0x8008, + (q15_t)0x2a6, (q15_t)0x8008, (q15_t)0x2a0, (q15_t)0x8007, (q15_t)0x299, (q15_t)0x8007, (q15_t)0x293, (q15_t)0x8007, + (q15_t)0x28d, (q15_t)0x8007, (q15_t)0x287, (q15_t)0x8007, (q15_t)0x280, (q15_t)0x8007, (q15_t)0x27a, (q15_t)0x8007, + (q15_t)0x274, (q15_t)0x8007, (q15_t)0x26d, (q15_t)0x8006, (q15_t)0x267, (q15_t)0x8006, (q15_t)0x261, (q15_t)0x8006, + (q15_t)0x25b, (q15_t)0x8006, (q15_t)0x254, (q15_t)0x8006, (q15_t)0x24e, (q15_t)0x8006, (q15_t)0x248, (q15_t)0x8006, + (q15_t)0x242, (q15_t)0x8006, (q15_t)0x23b, (q15_t)0x8005, (q15_t)0x235, (q15_t)0x8005, (q15_t)0x22f, (q15_t)0x8005, + (q15_t)0x228, (q15_t)0x8005, (q15_t)0x222, (q15_t)0x8005, (q15_t)0x21c, (q15_t)0x8005, (q15_t)0x216, (q15_t)0x8005, + (q15_t)0x20f, (q15_t)0x8005, (q15_t)0x209, (q15_t)0x8005, (q15_t)0x203, (q15_t)0x8005, (q15_t)0x1fc, (q15_t)0x8004, + (q15_t)0x1f6, (q15_t)0x8004, (q15_t)0x1f0, (q15_t)0x8004, (q15_t)0x1ea, (q15_t)0x8004, (q15_t)0x1e3, (q15_t)0x8004, + (q15_t)0x1dd, (q15_t)0x8004, (q15_t)0x1d7, (q15_t)0x8004, (q15_t)0x1d0, (q15_t)0x8004, (q15_t)0x1ca, (q15_t)0x8004, + (q15_t)0x1c4, (q15_t)0x8004, (q15_t)0x1be, (q15_t)0x8004, (q15_t)0x1b7, (q15_t)0x8003, (q15_t)0x1b1, (q15_t)0x8003, + (q15_t)0x1ab, (q15_t)0x8003, (q15_t)0x1a4, (q15_t)0x8003, (q15_t)0x19e, (q15_t)0x8003, (q15_t)0x198, (q15_t)0x8003, + (q15_t)0x192, (q15_t)0x8003, (q15_t)0x18b, (q15_t)0x8003, (q15_t)0x185, (q15_t)0x8003, (q15_t)0x17f, (q15_t)0x8003, + (q15_t)0x178, (q15_t)0x8003, (q15_t)0x172, (q15_t)0x8003, (q15_t)0x16c, (q15_t)0x8003, (q15_t)0x166, (q15_t)0x8002, + (q15_t)0x15f, (q15_t)0x8002, (q15_t)0x159, (q15_t)0x8002, (q15_t)0x153, (q15_t)0x8002, (q15_t)0x14d, (q15_t)0x8002, + (q15_t)0x146, (q15_t)0x8002, (q15_t)0x140, (q15_t)0x8002, (q15_t)0x13a, (q15_t)0x8002, (q15_t)0x133, (q15_t)0x8002, + (q15_t)0x12d, (q15_t)0x8002, (q15_t)0x127, (q15_t)0x8002, (q15_t)0x121, (q15_t)0x8002, (q15_t)0x11a, (q15_t)0x8002, + (q15_t)0x114, (q15_t)0x8002, (q15_t)0x10e, (q15_t)0x8002, (q15_t)0x107, (q15_t)0x8002, (q15_t)0x101, (q15_t)0x8002, + (q15_t)0xfb, (q15_t)0x8001, (q15_t)0xf5, (q15_t)0x8001, (q15_t)0xee, (q15_t)0x8001, (q15_t)0xe8, (q15_t)0x8001, + (q15_t)0xe2, (q15_t)0x8001, (q15_t)0xdb, (q15_t)0x8001, (q15_t)0xd5, (q15_t)0x8001, (q15_t)0xcf, (q15_t)0x8001, + (q15_t)0xc9, (q15_t)0x8001, (q15_t)0xc2, (q15_t)0x8001, (q15_t)0xbc, (q15_t)0x8001, (q15_t)0xb6, (q15_t)0x8001, + (q15_t)0xaf, (q15_t)0x8001, (q15_t)0xa9, (q15_t)0x8001, (q15_t)0xa3, (q15_t)0x8001, (q15_t)0x9d, (q15_t)0x8001, + (q15_t)0x96, (q15_t)0x8001, (q15_t)0x90, (q15_t)0x8001, (q15_t)0x8a, (q15_t)0x8001, (q15_t)0x83, (q15_t)0x8001, + (q15_t)0x7d, (q15_t)0x8001, (q15_t)0x77, (q15_t)0x8001, (q15_t)0x71, (q15_t)0x8001, (q15_t)0x6a, (q15_t)0x8001, + (q15_t)0x64, (q15_t)0x8001, (q15_t)0x5e, (q15_t)0x8001, (q15_t)0x57, (q15_t)0x8001, (q15_t)0x51, (q15_t)0x8001, + (q15_t)0x4b, (q15_t)0x8001, (q15_t)0x45, (q15_t)0x8001, (q15_t)0x3e, (q15_t)0x8001, (q15_t)0x38, (q15_t)0x8001, + (q15_t)0x32, (q15_t)0x8001, (q15_t)0x2b, (q15_t)0x8001, (q15_t)0x25, (q15_t)0x8001, (q15_t)0x1f, (q15_t)0x8001, + (q15_t)0x19, (q15_t)0x8001, (q15_t)0x12, (q15_t)0x8001, (q15_t)0xc, (q15_t)0x8001, (q15_t)0x6, (q15_t)0x8001 +}; + + const q15_t __ALIGNED(4) cos_factorsQ15_8192[8192] = { + (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, + (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, + (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, + (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, + (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, + (q15_t)0x7fff, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, + (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, + (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffd, (q15_t)0x7ffd, (q15_t)0x7ffd, (q15_t)0x7ffd, (q15_t)0x7ffd, (q15_t)0x7ffd, + (q15_t)0x7ffd, (q15_t)0x7ffd, (q15_t)0x7ffd, (q15_t)0x7ffd, (q15_t)0x7ffd, (q15_t)0x7ffd, (q15_t)0x7ffd, (q15_t)0x7ffc, + (q15_t)0x7ffc, (q15_t)0x7ffc, (q15_t)0x7ffc, (q15_t)0x7ffc, (q15_t)0x7ffc, (q15_t)0x7ffc, (q15_t)0x7ffc, (q15_t)0x7ffc, + (q15_t)0x7ffc, (q15_t)0x7ffb, (q15_t)0x7ffb, (q15_t)0x7ffb, (q15_t)0x7ffb, (q15_t)0x7ffb, (q15_t)0x7ffb, (q15_t)0x7ffb, + (q15_t)0x7ffb, (q15_t)0x7ffb, (q15_t)0x7ffb, (q15_t)0x7ffa, (q15_t)0x7ffa, (q15_t)0x7ffa, (q15_t)0x7ffa, (q15_t)0x7ffa, + (q15_t)0x7ffa, (q15_t)0x7ffa, (q15_t)0x7ffa, (q15_t)0x7ffa, (q15_t)0x7ff9, (q15_t)0x7ff9, (q15_t)0x7ff9, (q15_t)0x7ff9, + (q15_t)0x7ff9, (q15_t)0x7ff9, (q15_t)0x7ff9, (q15_t)0x7ff9, (q15_t)0x7ff8, (q15_t)0x7ff8, (q15_t)0x7ff8, (q15_t)0x7ff8, + (q15_t)0x7ff8, (q15_t)0x7ff8, (q15_t)0x7ff8, (q15_t)0x7ff7, (q15_t)0x7ff7, (q15_t)0x7ff7, (q15_t)0x7ff7, (q15_t)0x7ff7, + (q15_t)0x7ff7, (q15_t)0x7ff7, (q15_t)0x7ff6, (q15_t)0x7ff6, (q15_t)0x7ff6, (q15_t)0x7ff6, (q15_t)0x7ff6, (q15_t)0x7ff6, + (q15_t)0x7ff6, (q15_t)0x7ff5, (q15_t)0x7ff5, (q15_t)0x7ff5, (q15_t)0x7ff5, (q15_t)0x7ff5, (q15_t)0x7ff5, (q15_t)0x7ff4, + (q15_t)0x7ff4, (q15_t)0x7ff4, (q15_t)0x7ff4, (q15_t)0x7ff4, (q15_t)0x7ff4, (q15_t)0x7ff3, (q15_t)0x7ff3, (q15_t)0x7ff3, + (q15_t)0x7ff3, (q15_t)0x7ff3, (q15_t)0x7ff3, (q15_t)0x7ff2, (q15_t)0x7ff2, (q15_t)0x7ff2, (q15_t)0x7ff2, (q15_t)0x7ff2, + (q15_t)0x7ff1, (q15_t)0x7ff1, (q15_t)0x7ff1, (q15_t)0x7ff1, (q15_t)0x7ff1, (q15_t)0x7ff1, (q15_t)0x7ff0, (q15_t)0x7ff0, + (q15_t)0x7ff0, (q15_t)0x7ff0, (q15_t)0x7ff0, (q15_t)0x7fef, (q15_t)0x7fef, (q15_t)0x7fef, (q15_t)0x7fef, (q15_t)0x7fef, + (q15_t)0x7fee, (q15_t)0x7fee, (q15_t)0x7fee, (q15_t)0x7fee, (q15_t)0x7fee, (q15_t)0x7fed, (q15_t)0x7fed, (q15_t)0x7fed, + (q15_t)0x7fed, (q15_t)0x7fed, (q15_t)0x7fec, (q15_t)0x7fec, (q15_t)0x7fec, (q15_t)0x7fec, (q15_t)0x7feb, (q15_t)0x7feb, + (q15_t)0x7feb, (q15_t)0x7feb, (q15_t)0x7feb, (q15_t)0x7fea, (q15_t)0x7fea, (q15_t)0x7fea, (q15_t)0x7fea, (q15_t)0x7fe9, + (q15_t)0x7fe9, (q15_t)0x7fe9, (q15_t)0x7fe9, (q15_t)0x7fe8, (q15_t)0x7fe8, (q15_t)0x7fe8, (q15_t)0x7fe8, (q15_t)0x7fe8, + (q15_t)0x7fe7, (q15_t)0x7fe7, (q15_t)0x7fe7, (q15_t)0x7fe7, (q15_t)0x7fe6, (q15_t)0x7fe6, (q15_t)0x7fe6, (q15_t)0x7fe6, + (q15_t)0x7fe5, (q15_t)0x7fe5, (q15_t)0x7fe5, (q15_t)0x7fe5, (q15_t)0x7fe4, (q15_t)0x7fe4, (q15_t)0x7fe4, (q15_t)0x7fe4, + (q15_t)0x7fe3, (q15_t)0x7fe3, (q15_t)0x7fe3, (q15_t)0x7fe2, (q15_t)0x7fe2, (q15_t)0x7fe2, (q15_t)0x7fe2, (q15_t)0x7fe1, + (q15_t)0x7fe1, (q15_t)0x7fe1, (q15_t)0x7fe1, (q15_t)0x7fe0, (q15_t)0x7fe0, (q15_t)0x7fe0, (q15_t)0x7fdf, (q15_t)0x7fdf, + (q15_t)0x7fdf, (q15_t)0x7fdf, (q15_t)0x7fde, (q15_t)0x7fde, (q15_t)0x7fde, (q15_t)0x7fde, (q15_t)0x7fdd, (q15_t)0x7fdd, + (q15_t)0x7fdd, (q15_t)0x7fdc, (q15_t)0x7fdc, (q15_t)0x7fdc, (q15_t)0x7fdb, (q15_t)0x7fdb, (q15_t)0x7fdb, (q15_t)0x7fdb, + (q15_t)0x7fda, (q15_t)0x7fda, (q15_t)0x7fda, (q15_t)0x7fd9, (q15_t)0x7fd9, (q15_t)0x7fd9, (q15_t)0x7fd8, (q15_t)0x7fd8, + (q15_t)0x7fd8, (q15_t)0x7fd8, (q15_t)0x7fd7, (q15_t)0x7fd7, (q15_t)0x7fd7, (q15_t)0x7fd6, (q15_t)0x7fd6, (q15_t)0x7fd6, + (q15_t)0x7fd5, (q15_t)0x7fd5, (q15_t)0x7fd5, (q15_t)0x7fd4, (q15_t)0x7fd4, (q15_t)0x7fd4, (q15_t)0x7fd3, (q15_t)0x7fd3, + (q15_t)0x7fd3, (q15_t)0x7fd2, (q15_t)0x7fd2, (q15_t)0x7fd2, (q15_t)0x7fd1, (q15_t)0x7fd1, (q15_t)0x7fd1, (q15_t)0x7fd0, + (q15_t)0x7fd0, (q15_t)0x7fd0, (q15_t)0x7fcf, (q15_t)0x7fcf, (q15_t)0x7fcf, (q15_t)0x7fce, (q15_t)0x7fce, (q15_t)0x7fce, + (q15_t)0x7fcd, (q15_t)0x7fcd, (q15_t)0x7fcd, (q15_t)0x7fcc, (q15_t)0x7fcc, (q15_t)0x7fcc, (q15_t)0x7fcb, (q15_t)0x7fcb, + (q15_t)0x7fcb, (q15_t)0x7fca, (q15_t)0x7fca, (q15_t)0x7fc9, (q15_t)0x7fc9, (q15_t)0x7fc9, (q15_t)0x7fc8, (q15_t)0x7fc8, + (q15_t)0x7fc8, (q15_t)0x7fc7, (q15_t)0x7fc7, (q15_t)0x7fc7, (q15_t)0x7fc6, (q15_t)0x7fc6, (q15_t)0x7fc5, (q15_t)0x7fc5, + (q15_t)0x7fc5, (q15_t)0x7fc4, (q15_t)0x7fc4, (q15_t)0x7fc4, (q15_t)0x7fc3, (q15_t)0x7fc3, (q15_t)0x7fc2, (q15_t)0x7fc2, + (q15_t)0x7fc2, (q15_t)0x7fc1, (q15_t)0x7fc1, (q15_t)0x7fc0, (q15_t)0x7fc0, (q15_t)0x7fc0, (q15_t)0x7fbf, (q15_t)0x7fbf, + (q15_t)0x7fbf, (q15_t)0x7fbe, (q15_t)0x7fbe, (q15_t)0x7fbd, (q15_t)0x7fbd, (q15_t)0x7fbd, (q15_t)0x7fbc, (q15_t)0x7fbc, + (q15_t)0x7fbb, (q15_t)0x7fbb, (q15_t)0x7fbb, (q15_t)0x7fba, (q15_t)0x7fba, (q15_t)0x7fb9, (q15_t)0x7fb9, (q15_t)0x7fb8, + (q15_t)0x7fb8, (q15_t)0x7fb8, (q15_t)0x7fb7, (q15_t)0x7fb7, (q15_t)0x7fb6, (q15_t)0x7fb6, (q15_t)0x7fb6, (q15_t)0x7fb5, + (q15_t)0x7fb5, (q15_t)0x7fb4, (q15_t)0x7fb4, (q15_t)0x7fb3, (q15_t)0x7fb3, (q15_t)0x7fb3, (q15_t)0x7fb2, (q15_t)0x7fb2, + (q15_t)0x7fb1, (q15_t)0x7fb1, (q15_t)0x7fb0, (q15_t)0x7fb0, (q15_t)0x7faf, (q15_t)0x7faf, (q15_t)0x7faf, (q15_t)0x7fae, + (q15_t)0x7fae, (q15_t)0x7fad, (q15_t)0x7fad, (q15_t)0x7fac, (q15_t)0x7fac, (q15_t)0x7fac, (q15_t)0x7fab, (q15_t)0x7fab, + (q15_t)0x7faa, (q15_t)0x7faa, (q15_t)0x7fa9, (q15_t)0x7fa9, (q15_t)0x7fa8, (q15_t)0x7fa8, (q15_t)0x7fa7, (q15_t)0x7fa7, + (q15_t)0x7fa6, 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(q15_t)0xe5d, (q15_t)0xe57, (q15_t)0xe50, + (q15_t)0xe4a, (q15_t)0xe44, (q15_t)0xe3e, (q15_t)0xe37, (q15_t)0xe31, (q15_t)0xe2b, (q15_t)0xe25, (q15_t)0xe1e, + (q15_t)0xe18, (q15_t)0xe12, (q15_t)0xe0c, (q15_t)0xe05, (q15_t)0xdff, (q15_t)0xdf9, (q15_t)0xdf3, (q15_t)0xdec, + (q15_t)0xde6, (q15_t)0xde0, (q15_t)0xdda, (q15_t)0xdd3, (q15_t)0xdcd, (q15_t)0xdc7, (q15_t)0xdc1, (q15_t)0xdba, + (q15_t)0xdb4, (q15_t)0xdae, (q15_t)0xda8, (q15_t)0xda1, (q15_t)0xd9b, (q15_t)0xd95, (q15_t)0xd8f, (q15_t)0xd88, + (q15_t)0xd82, (q15_t)0xd7c, (q15_t)0xd76, (q15_t)0xd6f, (q15_t)0xd69, (q15_t)0xd63, (q15_t)0xd5d, (q15_t)0xd56, + (q15_t)0xd50, (q15_t)0xd4a, (q15_t)0xd44, (q15_t)0xd3d, (q15_t)0xd37, (q15_t)0xd31, (q15_t)0xd2b, (q15_t)0xd24, + (q15_t)0xd1e, (q15_t)0xd18, (q15_t)0xd12, (q15_t)0xd0b, (q15_t)0xd05, (q15_t)0xcff, (q15_t)0xcf9, (q15_t)0xcf2, + (q15_t)0xcec, (q15_t)0xce6, (q15_t)0xce0, (q15_t)0xcd9, (q15_t)0xcd3, (q15_t)0xccd, (q15_t)0xcc7, (q15_t)0xcc0, + (q15_t)0xcba, (q15_t)0xcb4, (q15_t)0xcae, (q15_t)0xca7, (q15_t)0xca1, (q15_t)0xc9b, (q15_t)0xc95, (q15_t)0xc8e, + (q15_t)0xc88, (q15_t)0xc82, (q15_t)0xc7c, (q15_t)0xc75, (q15_t)0xc6f, (q15_t)0xc69, (q15_t)0xc63, (q15_t)0xc5c, + (q15_t)0xc56, (q15_t)0xc50, (q15_t)0xc4a, (q15_t)0xc43, (q15_t)0xc3d, (q15_t)0xc37, (q15_t)0xc31, (q15_t)0xc2a, + (q15_t)0xc24, (q15_t)0xc1e, (q15_t)0xc18, (q15_t)0xc11, (q15_t)0xc0b, (q15_t)0xc05, (q15_t)0xbff, (q15_t)0xbf8, + (q15_t)0xbf2, (q15_t)0xbec, (q15_t)0xbe6, (q15_t)0xbdf, (q15_t)0xbd9, (q15_t)0xbd3, (q15_t)0xbcd, (q15_t)0xbc6, + (q15_t)0xbc0, (q15_t)0xbba, (q15_t)0xbb4, (q15_t)0xbad, (q15_t)0xba7, (q15_t)0xba1, (q15_t)0xb9b, (q15_t)0xb94, + (q15_t)0xb8e, (q15_t)0xb88, (q15_t)0xb81, (q15_t)0xb7b, (q15_t)0xb75, (q15_t)0xb6f, (q15_t)0xb68, (q15_t)0xb62, + (q15_t)0xb5c, (q15_t)0xb56, (q15_t)0xb4f, (q15_t)0xb49, (q15_t)0xb43, (q15_t)0xb3d, (q15_t)0xb36, (q15_t)0xb30, + (q15_t)0xb2a, (q15_t)0xb24, (q15_t)0xb1d, (q15_t)0xb17, (q15_t)0xb11, (q15_t)0xb0b, (q15_t)0xb04, (q15_t)0xafe, + (q15_t)0xaf8, (q15_t)0xaf2, (q15_t)0xaeb, (q15_t)0xae5, (q15_t)0xadf, (q15_t)0xad8, (q15_t)0xad2, (q15_t)0xacc, + (q15_t)0xac6, (q15_t)0xabf, (q15_t)0xab9, (q15_t)0xab3, (q15_t)0xaad, (q15_t)0xaa6, (q15_t)0xaa0, (q15_t)0xa9a, + (q15_t)0xa94, (q15_t)0xa8d, (q15_t)0xa87, (q15_t)0xa81, (q15_t)0xa7b, (q15_t)0xa74, (q15_t)0xa6e, (q15_t)0xa68, + (q15_t)0xa62, (q15_t)0xa5b, (q15_t)0xa55, (q15_t)0xa4f, (q15_t)0xa48, (q15_t)0xa42, (q15_t)0xa3c, (q15_t)0xa36, + (q15_t)0xa2f, (q15_t)0xa29, (q15_t)0xa23, (q15_t)0xa1d, (q15_t)0xa16, (q15_t)0xa10, (q15_t)0xa0a, (q15_t)0xa04, + (q15_t)0x9fd, (q15_t)0x9f7, (q15_t)0x9f1, (q15_t)0x9eb, (q15_t)0x9e4, (q15_t)0x9de, (q15_t)0x9d8, (q15_t)0x9d1, + (q15_t)0x9cb, (q15_t)0x9c5, (q15_t)0x9bf, (q15_t)0x9b8, (q15_t)0x9b2, (q15_t)0x9ac, (q15_t)0x9a6, (q15_t)0x99f, + (q15_t)0x999, (q15_t)0x993, (q15_t)0x98d, (q15_t)0x986, (q15_t)0x980, (q15_t)0x97a, (q15_t)0x973, (q15_t)0x96d, + (q15_t)0x967, (q15_t)0x961, (q15_t)0x95a, (q15_t)0x954, (q15_t)0x94e, (q15_t)0x948, (q15_t)0x941, (q15_t)0x93b, + (q15_t)0x935, (q15_t)0x92f, (q15_t)0x928, (q15_t)0x922, (q15_t)0x91c, (q15_t)0x915, (q15_t)0x90f, (q15_t)0x909, + (q15_t)0x903, (q15_t)0x8fc, (q15_t)0x8f6, (q15_t)0x8f0, (q15_t)0x8ea, (q15_t)0x8e3, (q15_t)0x8dd, (q15_t)0x8d7, + (q15_t)0x8d1, (q15_t)0x8ca, (q15_t)0x8c4, (q15_t)0x8be, (q15_t)0x8b7, (q15_t)0x8b1, (q15_t)0x8ab, (q15_t)0x8a5, + (q15_t)0x89e, (q15_t)0x898, (q15_t)0x892, (q15_t)0x88c, (q15_t)0x885, (q15_t)0x87f, (q15_t)0x879, (q15_t)0x872, + (q15_t)0x86c, (q15_t)0x866, (q15_t)0x860, (q15_t)0x859, (q15_t)0x853, (q15_t)0x84d, (q15_t)0x847, (q15_t)0x840, + (q15_t)0x83a, (q15_t)0x834, (q15_t)0x82e, (q15_t)0x827, (q15_t)0x821, (q15_t)0x81b, (q15_t)0x814, (q15_t)0x80e, + (q15_t)0x808, (q15_t)0x802, (q15_t)0x7fb, (q15_t)0x7f5, (q15_t)0x7ef, (q15_t)0x7e9, (q15_t)0x7e2, (q15_t)0x7dc, + (q15_t)0x7d6, (q15_t)0x7cf, (q15_t)0x7c9, (q15_t)0x7c3, (q15_t)0x7bd, (q15_t)0x7b6, (q15_t)0x7b0, (q15_t)0x7aa, + (q15_t)0x7a4, (q15_t)0x79d, (q15_t)0x797, (q15_t)0x791, (q15_t)0x78a, (q15_t)0x784, (q15_t)0x77e, (q15_t)0x778, + (q15_t)0x771, (q15_t)0x76b, (q15_t)0x765, (q15_t)0x75f, (q15_t)0x758, (q15_t)0x752, (q15_t)0x74c, (q15_t)0x745, + (q15_t)0x73f, (q15_t)0x739, (q15_t)0x733, (q15_t)0x72c, (q15_t)0x726, (q15_t)0x720, (q15_t)0x71a, (q15_t)0x713, + (q15_t)0x70d, (q15_t)0x707, (q15_t)0x700, (q15_t)0x6fa, (q15_t)0x6f4, (q15_t)0x6ee, (q15_t)0x6e7, (q15_t)0x6e1, + (q15_t)0x6db, (q15_t)0x6d5, (q15_t)0x6ce, (q15_t)0x6c8, (q15_t)0x6c2, (q15_t)0x6bb, (q15_t)0x6b5, (q15_t)0x6af, + (q15_t)0x6a9, (q15_t)0x6a2, (q15_t)0x69c, (q15_t)0x696, (q15_t)0x690, (q15_t)0x689, (q15_t)0x683, (q15_t)0x67d, + (q15_t)0x676, (q15_t)0x670, (q15_t)0x66a, (q15_t)0x664, (q15_t)0x65d, (q15_t)0x657, (q15_t)0x651, (q15_t)0x64a, + (q15_t)0x644, (q15_t)0x63e, (q15_t)0x638, (q15_t)0x631, (q15_t)0x62b, (q15_t)0x625, (q15_t)0x61f, (q15_t)0x618, + (q15_t)0x612, (q15_t)0x60c, (q15_t)0x605, (q15_t)0x5ff, (q15_t)0x5f9, (q15_t)0x5f3, (q15_t)0x5ec, (q15_t)0x5e6, + (q15_t)0x5e0, (q15_t)0x5da, (q15_t)0x5d3, (q15_t)0x5cd, (q15_t)0x5c7, (q15_t)0x5c0, (q15_t)0x5ba, (q15_t)0x5b4, + (q15_t)0x5ae, (q15_t)0x5a7, (q15_t)0x5a1, (q15_t)0x59b, (q15_t)0x594, (q15_t)0x58e, (q15_t)0x588, (q15_t)0x582, + (q15_t)0x57b, (q15_t)0x575, (q15_t)0x56f, (q15_t)0x569, (q15_t)0x562, (q15_t)0x55c, (q15_t)0x556, (q15_t)0x54f, + (q15_t)0x549, (q15_t)0x543, (q15_t)0x53d, (q15_t)0x536, (q15_t)0x530, (q15_t)0x52a, (q15_t)0x523, (q15_t)0x51d, + (q15_t)0x517, (q15_t)0x511, (q15_t)0x50a, (q15_t)0x504, (q15_t)0x4fe, (q15_t)0x4f8, (q15_t)0x4f1, (q15_t)0x4eb, + (q15_t)0x4e5, (q15_t)0x4de, (q15_t)0x4d8, (q15_t)0x4d2, (q15_t)0x4cc, (q15_t)0x4c5, (q15_t)0x4bf, (q15_t)0x4b9, + (q15_t)0x4b2, (q15_t)0x4ac, (q15_t)0x4a6, (q15_t)0x4a0, (q15_t)0x499, (q15_t)0x493, (q15_t)0x48d, (q15_t)0x487, + (q15_t)0x480, (q15_t)0x47a, (q15_t)0x474, (q15_t)0x46d, (q15_t)0x467, (q15_t)0x461, (q15_t)0x45b, (q15_t)0x454, + (q15_t)0x44e, (q15_t)0x448, (q15_t)0x441, (q15_t)0x43b, (q15_t)0x435, (q15_t)0x42f, (q15_t)0x428, (q15_t)0x422, + (q15_t)0x41c, (q15_t)0x415, (q15_t)0x40f, (q15_t)0x409, (q15_t)0x403, (q15_t)0x3fc, (q15_t)0x3f6, (q15_t)0x3f0, + (q15_t)0x3ea, (q15_t)0x3e3, (q15_t)0x3dd, (q15_t)0x3d7, (q15_t)0x3d0, (q15_t)0x3ca, (q15_t)0x3c4, (q15_t)0x3be, + (q15_t)0x3b7, (q15_t)0x3b1, (q15_t)0x3ab, (q15_t)0x3a4, (q15_t)0x39e, (q15_t)0x398, (q15_t)0x392, (q15_t)0x38b, + (q15_t)0x385, (q15_t)0x37f, (q15_t)0x378, (q15_t)0x372, (q15_t)0x36c, (q15_t)0x366, (q15_t)0x35f, (q15_t)0x359, + (q15_t)0x353, (q15_t)0x34c, (q15_t)0x346, (q15_t)0x340, (q15_t)0x33a, (q15_t)0x333, (q15_t)0x32d, (q15_t)0x327, + (q15_t)0x321, (q15_t)0x31a, (q15_t)0x314, (q15_t)0x30e, (q15_t)0x307, (q15_t)0x301, (q15_t)0x2fb, (q15_t)0x2f5, + (q15_t)0x2ee, (q15_t)0x2e8, (q15_t)0x2e2, (q15_t)0x2db, (q15_t)0x2d5, (q15_t)0x2cf, (q15_t)0x2c9, (q15_t)0x2c2, + (q15_t)0x2bc, (q15_t)0x2b6, (q15_t)0x2af, (q15_t)0x2a9, (q15_t)0x2a3, (q15_t)0x29d, (q15_t)0x296, (q15_t)0x290, + (q15_t)0x28a, (q15_t)0x283, (q15_t)0x27d, (q15_t)0x277, (q15_t)0x271, (q15_t)0x26a, (q15_t)0x264, (q15_t)0x25e, + (q15_t)0x258, (q15_t)0x251, (q15_t)0x24b, (q15_t)0x245, (q15_t)0x23e, (q15_t)0x238, (q15_t)0x232, (q15_t)0x22c, + (q15_t)0x225, (q15_t)0x21f, (q15_t)0x219, (q15_t)0x212, (q15_t)0x20c, (q15_t)0x206, (q15_t)0x200, (q15_t)0x1f9, + (q15_t)0x1f3, (q15_t)0x1ed, (q15_t)0x1e6, (q15_t)0x1e0, (q15_t)0x1da, (q15_t)0x1d4, (q15_t)0x1cd, (q15_t)0x1c7, + (q15_t)0x1c1, (q15_t)0x1ba, (q15_t)0x1b4, (q15_t)0x1ae, (q15_t)0x1a8, (q15_t)0x1a1, (q15_t)0x19b, (q15_t)0x195, + (q15_t)0x18e, (q15_t)0x188, (q15_t)0x182, (q15_t)0x17c, (q15_t)0x175, (q15_t)0x16f, (q15_t)0x169, (q15_t)0x162, + (q15_t)0x15c, (q15_t)0x156, (q15_t)0x150, (q15_t)0x149, (q15_t)0x143, (q15_t)0x13d, (q15_t)0x137, (q15_t)0x130, + (q15_t)0x12a, (q15_t)0x124, (q15_t)0x11d, (q15_t)0x117, (q15_t)0x111, (q15_t)0x10b, (q15_t)0x104, (q15_t)0xfe, + (q15_t)0xf8, (q15_t)0xf1, (q15_t)0xeb, (q15_t)0xe5, (q15_t)0xdf, (q15_t)0xd8, (q15_t)0xd2, (q15_t)0xcc, + (q15_t)0xc5, (q15_t)0xbf, (q15_t)0xb9, (q15_t)0xb3, (q15_t)0xac, (q15_t)0xa6, (q15_t)0xa0, (q15_t)0x99, + (q15_t)0x93, (q15_t)0x8d, (q15_t)0x87, (q15_t)0x80, (q15_t)0x7a, (q15_t)0x74, (q15_t)0x6d, (q15_t)0x67, + (q15_t)0x61, (q15_t)0x5b, (q15_t)0x54, (q15_t)0x4e, (q15_t)0x48, (q15_t)0x41, (q15_t)0x3b, (q15_t)0x35, + (q15_t)0x2f, (q15_t)0x28, (q15_t)0x22, (q15_t)0x1c, (q15_t)0x15, (q15_t)0xf, (q15_t)0x9, (q15_t)0x3 +}; + #endif + +/** + @par + Weights tables are generated using the formula : 
weights[n] = e^(-j*n*pi/(2*N))
+ @par + C command to generate the table + 
+  for (i = 0; i< N; i++)
+  {
+    weights[(2*i)]   =  cos(i*c);
+    weights[(2*i)+1] = -sin(i*c);
+  }
+ @par + where N is the Number of weights to be calculated and c is pi/(2*N) + @par + Convert the output to q31 format by multiplying with 2^31 and saturated if required. + @par + In the tables below the real and imaginary values are placed alternatively, hence the + array length is 2*N. + */ + +/** + @par + cosFactor tables are generated using the formula : 
cos_factors[n] = 2 * cos((2n+1)*pi/(4*N))
+ @par + C command to generate the table + 
+  for (i = 0; i< N; i++)
+  {
+    cos_factors[i] = 2 * cos((2*i+1)*c/2);
+  }
+ @par + where N is the number of factors to generate and c is pi/(2*N) + @par + Then converted to q31 format by multiplying with 2^31 and saturated if required. +*/ + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_DCT4_Q31_128) + const q31_t WeightsQ31_128[256] = { + (q31_t)0x7fffffff, (q31_t)0x00000000, (q31_t)0x7ffd885a, (q31_t)0xfe6de2e0, (q31_t)0x7ff62182, (q31_t)0xfcdbd541, (q31_t)0x7fe9cbc0, (q31_t)0xfb49e6a3, + (q31_t)0x7fd8878e, (q31_t)0xf9b82684, (q31_t)0x7fc25596, (q31_t)0xf826a462, (q31_t)0x7fa736b4, (q31_t)0xf6956fb7, (q31_t)0x7f872bf3, (q31_t)0xf50497fb, + (q31_t)0x7f62368f, (q31_t)0xf3742ca2, (q31_t)0x7f3857f6, (q31_t)0xf1e43d1c, (q31_t)0x7f0991c4, (q31_t)0xf054d8d5, (q31_t)0x7ed5e5c6, (q31_t)0xeec60f31, + (q31_t)0x7e9d55fc, (q31_t)0xed37ef91, (q31_t)0x7e5fe493, (q31_t)0xebaa894f, (q31_t)0x7e1d93ea, (q31_t)0xea1debbb, (q31_t)0x7dd6668f, (q31_t)0xe8922622, + (q31_t)0x7d8a5f40, (q31_t)0xe70747c4, (q31_t)0x7d3980ec, (q31_t)0xe57d5fda, (q31_t)0x7ce3ceb2, (q31_t)0xe3f47d96, (q31_t)0x7c894bde, (q31_t)0xe26cb01b, + (q31_t)0x7c29fbee, (q31_t)0xe0e60685, (q31_t)0x7bc5e290, (q31_t)0xdf608fe4, (q31_t)0x7b5d039e, (q31_t)0xdddc5b3b, (q31_t)0x7aef6323, (q31_t)0xdc597781, + (q31_t)0x7a7d055b, (q31_t)0xdad7f3a2, (q31_t)0x7a05eead, (q31_t)0xd957de7a, (q31_t)0x798a23b1, (q31_t)0xd7d946d8, (q31_t)0x7909a92d, (q31_t)0xd65c3b7b, + (q31_t)0x78848414, (q31_t)0xd4e0cb15, (q31_t)0x77fab989, (q31_t)0xd3670446, (q31_t)0x776c4edb, (q31_t)0xd1eef59e, (q31_t)0x76d94989, (q31_t)0xd078ad9e, + (q31_t)0x7641af3d, (q31_t)0xcf043ab3, (q31_t)0x75a585cf, (q31_t)0xcd91ab39, (q31_t)0x7504d345, (q31_t)0xcc210d79, (q31_t)0x745f9dd1, (q31_t)0xcab26fa9, + (q31_t)0x73b5ebd1, (q31_t)0xc945dfec, (q31_t)0x7307c3d0, (q31_t)0xc7db6c50, (q31_t)0x72552c85, (q31_t)0xc67322ce, (q31_t)0x719e2cd2, (q31_t)0xc50d1149, + (q31_t)0x70e2cbc6, (q31_t)0xc3a94590, (q31_t)0x7023109a, (q31_t)0xc247cd5a, (q31_t)0x6f5f02b2, (q31_t)0xc0e8b648, (q31_t)0x6e96a99d, (q31_t)0xbf8c0de3, + (q31_t)0x6dca0d14, (q31_t)0xbe31e19b, (q31_t)0x6cf934fc, (q31_t)0xbcda3ecb, (q31_t)0x6c242960, (q31_t)0xbb8532b0, (q31_t)0x6b4af279, (q31_t)0xba32ca71, + (q31_t)0x6a6d98a4, (q31_t)0xb8e31319, (q31_t)0x698c246c, (q31_t)0xb796199b, (q31_t)0x68a69e81, (q31_t)0xb64beacd, (q31_t)0x67bd0fbd, (q31_t)0xb5049368, + (q31_t)0x66cf8120, (q31_t)0xb3c0200c, (q31_t)0x65ddfbd3, (q31_t)0xb27e9d3c, (q31_t)0x64e88926, (q31_t)0xb140175b, (q31_t)0x63ef3290, (q31_t)0xb0049ab3, + (q31_t)0x62f201ac, (q31_t)0xaecc336c, (q31_t)0x61f1003f, (q31_t)0xad96ed92, (q31_t)0x60ec3830, (q31_t)0xac64d510, (q31_t)0x5fe3b38d, (q31_t)0xab35f5b5, + (q31_t)0x5ed77c8a, (q31_t)0xaa0a5b2e, (q31_t)0x5dc79d7c, (q31_t)0xa8e21106, (q31_t)0x5cb420e0, (q31_t)0xa7bd22ac, (q31_t)0x5b9d1154, (q31_t)0xa69b9b68, + (q31_t)0x5a82799a, (q31_t)0xa57d8666, (q31_t)0x59646498, (q31_t)0xa462eeac, (q31_t)0x5842dd54, (q31_t)0xa34bdf20, (q31_t)0x571deefa, (q31_t)0xa2386284, + (q31_t)0x55f5a4d2, (q31_t)0xa1288376, (q31_t)0x54ca0a4b, (q31_t)0xa01c4c73, (q31_t)0x539b2af0, (q31_t)0x9f13c7d0, (q31_t)0x5269126e, (q31_t)0x9e0effc1, + (q31_t)0x5133cc94, (q31_t)0x9d0dfe54, (q31_t)0x4ffb654d, (q31_t)0x9c10cd70, (q31_t)0x4ebfe8a5, (q31_t)0x9b1776da, (q31_t)0x4d8162c4, (q31_t)0x9a22042d, + (q31_t)0x4c3fdff4, (q31_t)0x99307ee0, (q31_t)0x4afb6c98, (q31_t)0x9842f043, (q31_t)0x49b41533, (q31_t)0x9759617f, (q31_t)0x4869e665, (q31_t)0x9673db94, + (q31_t)0x471cece7, (q31_t)0x9592675c, (q31_t)0x45cd358f, (q31_t)0x94b50d87, (q31_t)0x447acd50, (q31_t)0x93dbd6a0, (q31_t)0x4325c135, (q31_t)0x9306cb04, + (q31_t)0x41ce1e65, (q31_t)0x9235f2ec, (q31_t)0x4073f21d, (q31_t)0x91695663, (q31_t)0x3f1749b8, (q31_t)0x90a0fd4e, (q31_t)0x3db832a6, (q31_t)0x8fdcef66, + (q31_t)0x3c56ba70, (q31_t)0x8f1d343a, (q31_t)0x3af2eeb7, (q31_t)0x8e61d32e, (q31_t)0x398cdd32, (q31_t)0x8daad37b, (q31_t)0x382493b0, (q31_t)0x8cf83c30, + (q31_t)0x36ba2014, (q31_t)0x8c4a142f, (q31_t)0x354d9057, (q31_t)0x8ba0622f, (q31_t)0x33def287, (q31_t)0x8afb2cbb, (q31_t)0x326e54c7, (q31_t)0x8a5a7a31, + (q31_t)0x30fbc54d, (q31_t)0x89be50c3, (q31_t)0x2f875262, (q31_t)0x8926b677, (q31_t)0x2e110a62, (q31_t)0x8893b125, (q31_t)0x2c98fbba, (q31_t)0x88054677, + (q31_t)0x2b1f34eb, (q31_t)0x877b7bec, (q31_t)0x29a3c485, (q31_t)0x86f656d3, (q31_t)0x2826b928, (q31_t)0x8675dc4f, (q31_t)0x26a82186, (q31_t)0x85fa1153, + (q31_t)0x25280c5e, (q31_t)0x8582faa5, (q31_t)0x23a6887f, (q31_t)0x85109cdd, (q31_t)0x2223a4c5, (q31_t)0x84a2fc62, (q31_t)0x209f701c, (q31_t)0x843a1d70, + (q31_t)0x1f19f97b, (q31_t)0x83d60412, (q31_t)0x1d934fe5, (q31_t)0x8376b422, (q31_t)0x1c0b826a, (q31_t)0x831c314e, (q31_t)0x1a82a026, (q31_t)0x82c67f14, + (q31_t)0x18f8b83c, (q31_t)0x8275a0c0, (q31_t)0x176dd9de, (q31_t)0x82299971, (q31_t)0x15e21445, (q31_t)0x81e26c16, (q31_t)0x145576b1, (q31_t)0x81a01b6d, + (q31_t)0x12c8106f, (q31_t)0x8162aa04, (q31_t)0x1139f0cf, (q31_t)0x812a1a3a, (q31_t)0x0fab272b, (q31_t)0x80f66e3c, (q31_t)0x0e1bc2e4, (q31_t)0x80c7a80a, + (q31_t)0x0c8bd35e, (q31_t)0x809dc971, (q31_t)0x0afb6805, (q31_t)0x8078d40d, (q31_t)0x096a9049, (q31_t)0x8058c94c, (q31_t)0x07d95b9e, (q31_t)0x803daa6a, + (q31_t)0x0647d97c, (q31_t)0x80277872, (q31_t)0x04b6195d, (q31_t)0x80163440, (q31_t)0x03242abf, (q31_t)0x8009de7e, (q31_t)0x01921d20, (q31_t)0x800277a6 +}; + const q31_t cos_factorsQ31_128[128] = { + (q31_t)0x7fff6216, (q31_t)0x7ffa72d1, (q31_t)0x7ff09478, (q31_t)0x7fe1c76b, (q31_t)0x7fce0c3e, (q31_t)0x7fb563b3, + (q31_t)0x7f97cebd, (q31_t)0x7f754e80, + (q31_t)0x7f4de451, (q31_t)0x7f2191b4, (q31_t)0x7ef05860, (q31_t)0x7eba3a39, (q31_t)0x7e7f3957, (q31_t)0x7e3f57ff, + (q31_t)0x7dfa98a8, (q31_t)0x7db0fdf8, + (q31_t)0x7d628ac6, (q31_t)0x7d0f4218, (q31_t)0x7cb72724, (q31_t)0x7c5a3d50, (q31_t)0x7bf88830, (q31_t)0x7b920b89, + (q31_t)0x7b26cb4f, (q31_t)0x7ab6cba4, + (q31_t)0x7a4210d8, (q31_t)0x79c89f6e, (q31_t)0x794a7c12, (q31_t)0x78c7aba2, (q31_t)0x78403329, (q31_t)0x77b417df, + (q31_t)0x77235f2d, (q31_t)0x768e0ea6, + (q31_t)0x75f42c0b, (q31_t)0x7555bd4c, (q31_t)0x74b2c884, (q31_t)0x740b53fb, (q31_t)0x735f6626, (q31_t)0x72af05a7, + (q31_t)0x71fa3949, (q31_t)0x71410805, + (q31_t)0x708378ff, (q31_t)0x6fc19385, (q31_t)0x6efb5f12, (q31_t)0x6e30e34a, (q31_t)0x6d6227fa, (q31_t)0x6c8f351c, + (q31_t)0x6bb812d1, (q31_t)0x6adcc964, + (q31_t)0x69fd614a, (q31_t)0x6919e320, (q31_t)0x683257ab, (q31_t)0x6746c7d8, (q31_t)0x66573cbb, (q31_t)0x6563bf92, + (q31_t)0x646c59bf, (q31_t)0x637114cc, + (q31_t)0x6271fa69, (q31_t)0x616f146c, (q31_t)0x60686ccf, (q31_t)0x5f5e0db3, (q31_t)0x5e50015d, (q31_t)0x5d3e5237, + (q31_t)0x5c290acc, (q31_t)0x5b1035cf, + (q31_t)0x59f3de12, (q31_t)0x58d40e8c, (q31_t)0x57b0d256, (q31_t)0x568a34a9, (q31_t)0x556040e2, (q31_t)0x5433027d, + (q31_t)0x53028518, (q31_t)0x51ced46e, + (q31_t)0x5097fc5e, (q31_t)0x4f5e08e3, (q31_t)0x4e210617, (q31_t)0x4ce10034, (q31_t)0x4b9e0390, (q31_t)0x4a581c9e, + (q31_t)0x490f57ee, (q31_t)0x47c3c22f, + (q31_t)0x46756828, (q31_t)0x452456bd, (q31_t)0x43d09aed, (q31_t)0x427a41d0, (q31_t)0x4121589b, (q31_t)0x3fc5ec98, + (q31_t)0x3e680b2c, (q31_t)0x3d07c1d6, + (q31_t)0x3ba51e29, (q31_t)0x3a402dd2, (q31_t)0x38d8fe93, (q31_t)0x376f9e46, (q31_t)0x36041ad9, (q31_t)0x34968250, + (q31_t)0x3326e2c3, (q31_t)0x31b54a5e, + (q31_t)0x3041c761, (q31_t)0x2ecc681e, (q31_t)0x2d553afc, (q31_t)0x2bdc4e6f, (q31_t)0x2a61b101, (q31_t)0x28e5714b, + (q31_t)0x27679df4, (q31_t)0x25e845b6, + (q31_t)0x24677758, (q31_t)0x22e541af, (q31_t)0x2161b3a0, (q31_t)0x1fdcdc1b, (q31_t)0x1e56ca1e, (q31_t)0x1ccf8cb3, + (q31_t)0x1b4732ef, (q31_t)0x19bdcbf3, + (q31_t)0x183366e9, (q31_t)0x16a81305, (q31_t)0x151bdf86, (q31_t)0x138edbb1, (q31_t)0x120116d5, (q31_t)0x1072a048, + (q31_t)0xee38766, (q31_t)0xd53db92, + (q31_t)0xbc3ac35, (q31_t)0xa3308bd, (q31_t)0x8a2009a, (q31_t)0x710a345, (q31_t)0x57f0035, (q31_t)0x3ed26e6, (q31_t)0x25b26d7, + (q31_t)0xc90f88 +}; + #endif + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_DCT4_Q31_512) + const q31_t WeightsQ31_512[1024] = { + (q31_t)0x7fffffff, (q31_t)0x00000000, (q31_t)0x7fffd886, (q31_t)0xff9b781d, (q31_t)0x7fff6216, (q31_t)0xff36f078, (q31_t)0x7ffe9cb2, (q31_t)0xfed2694f, + (q31_t)0x7ffd885a, (q31_t)0xfe6de2e0, (q31_t)0x7ffc250f, (q31_t)0xfe095d69, (q31_t)0x7ffa72d1, (q31_t)0xfda4d929, (q31_t)0x7ff871a2, (q31_t)0xfd40565c, + (q31_t)0x7ff62182, (q31_t)0xfcdbd541, (q31_t)0x7ff38274, (q31_t)0xfc775616, (q31_t)0x7ff09478, (q31_t)0xfc12d91a, (q31_t)0x7fed5791, (q31_t)0xfbae5e89, + (q31_t)0x7fe9cbc0, (q31_t)0xfb49e6a3, (q31_t)0x7fe5f108, (q31_t)0xfae571a4, (q31_t)0x7fe1c76b, (q31_t)0xfa80ffcb, (q31_t)0x7fdd4eec, (q31_t)0xfa1c9157, + (q31_t)0x7fd8878e, (q31_t)0xf9b82684, (q31_t)0x7fd37153, (q31_t)0xf953bf91, (q31_t)0x7fce0c3e, (q31_t)0xf8ef5cbb, (q31_t)0x7fc85854, (q31_t)0xf88afe42, + (q31_t)0x7fc25596, (q31_t)0xf826a462, (q31_t)0x7fbc040a, (q31_t)0xf7c24f59, (q31_t)0x7fb563b3, (q31_t)0xf75dff66, (q31_t)0x7fae7495, (q31_t)0xf6f9b4c6, + (q31_t)0x7fa736b4, (q31_t)0xf6956fb7, (q31_t)0x7f9faa15, (q31_t)0xf6313077, (q31_t)0x7f97cebd, (q31_t)0xf5ccf743, (q31_t)0x7f8fa4b0, (q31_t)0xf568c45b, + (q31_t)0x7f872bf3, (q31_t)0xf50497fb, (q31_t)0x7f7e648c, (q31_t)0xf4a07261, (q31_t)0x7f754e80, (q31_t)0xf43c53cb, (q31_t)0x7f6be9d4, (q31_t)0xf3d83c77, + (q31_t)0x7f62368f, (q31_t)0xf3742ca2, (q31_t)0x7f5834b7, (q31_t)0xf310248a, (q31_t)0x7f4de451, (q31_t)0xf2ac246e, (q31_t)0x7f434563, (q31_t)0xf2482c8a, + (q31_t)0x7f3857f6, (q31_t)0xf1e43d1c, (q31_t)0x7f2d1c0e, (q31_t)0xf1805662, (q31_t)0x7f2191b4, (q31_t)0xf11c789a, (q31_t)0x7f15b8ee, (q31_t)0xf0b8a401, + (q31_t)0x7f0991c4, (q31_t)0xf054d8d5, (q31_t)0x7efd1c3c, (q31_t)0xeff11753, (q31_t)0x7ef05860, (q31_t)0xef8d5fb8, (q31_t)0x7ee34636, (q31_t)0xef29b243, + (q31_t)0x7ed5e5c6, (q31_t)0xeec60f31, (q31_t)0x7ec8371a, (q31_t)0xee6276bf, (q31_t)0x7eba3a39, (q31_t)0xedfee92b, (q31_t)0x7eabef2c, (q31_t)0xed9b66b2, + (q31_t)0x7e9d55fc, (q31_t)0xed37ef91, (q31_t)0x7e8e6eb2, (q31_t)0xecd48407, (q31_t)0x7e7f3957, (q31_t)0xec71244f, (q31_t)0x7e6fb5f4, (q31_t)0xec0dd0a8, + (q31_t)0x7e5fe493, (q31_t)0xebaa894f, (q31_t)0x7e4fc53e, (q31_t)0xeb474e81, (q31_t)0x7e3f57ff, (q31_t)0xeae4207a, (q31_t)0x7e2e9cdf, (q31_t)0xea80ff7a, + (q31_t)0x7e1d93ea, (q31_t)0xea1debbb, (q31_t)0x7e0c3d29, (q31_t)0xe9bae57d, (q31_t)0x7dfa98a8, (q31_t)0xe957ecfb, (q31_t)0x7de8a670, (q31_t)0xe8f50273, + (q31_t)0x7dd6668f, (q31_t)0xe8922622, (q31_t)0x7dc3d90d, (q31_t)0xe82f5844, (q31_t)0x7db0fdf8, (q31_t)0xe7cc9917, (q31_t)0x7d9dd55a, (q31_t)0xe769e8d8, + (q31_t)0x7d8a5f40, (q31_t)0xe70747c4, (q31_t)0x7d769bb5, (q31_t)0xe6a4b616, (q31_t)0x7d628ac6, (q31_t)0xe642340d, (q31_t)0x7d4e2c7f, (q31_t)0xe5dfc1e5, + (q31_t)0x7d3980ec, (q31_t)0xe57d5fda, (q31_t)0x7d24881b, (q31_t)0xe51b0e2a, (q31_t)0x7d0f4218, (q31_t)0xe4b8cd11, (q31_t)0x7cf9aef0, (q31_t)0xe4569ccb, + (q31_t)0x7ce3ceb2, (q31_t)0xe3f47d96, (q31_t)0x7ccda169, (q31_t)0xe3926fad, (q31_t)0x7cb72724, (q31_t)0xe330734d, (q31_t)0x7ca05ff1, (q31_t)0xe2ce88b3, + (q31_t)0x7c894bde, (q31_t)0xe26cb01b, (q31_t)0x7c71eaf9, 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(q31_t)0x59f3de12, (q31_t)0xa4efca31, (q31_t)0x59ac3cfd, (q31_t)0xa4a94043, + (q31_t)0x59646498, (q31_t)0xa462eeac, (q31_t)0x591c550e, (q31_t)0xa41cd599, (q31_t)0x58d40e8c, (q31_t)0xa3d6f534, (q31_t)0x588b9140, (q31_t)0xa3914da8, + (q31_t)0x5842dd54, (q31_t)0xa34bdf20, (q31_t)0x57f9f2f8, (q31_t)0xa306a9c8, (q31_t)0x57b0d256, (q31_t)0xa2c1adc9, (q31_t)0x57677b9d, (q31_t)0xa27ceb4f, + (q31_t)0x571deefa, (q31_t)0xa2386284, (q31_t)0x56d42c99, (q31_t)0xa1f41392, (q31_t)0x568a34a9, (q31_t)0xa1affea3, (q31_t)0x56400758, (q31_t)0xa16c23e1, + (q31_t)0x55f5a4d2, (q31_t)0xa1288376, (q31_t)0x55ab0d46, (q31_t)0xa0e51d8c, (q31_t)0x556040e2, (q31_t)0xa0a1f24d, (q31_t)0x55153fd4, (q31_t)0xa05f01e1, + (q31_t)0x54ca0a4b, (q31_t)0xa01c4c73, (q31_t)0x547ea073, (q31_t)0x9fd9d22a, (q31_t)0x5433027d, (q31_t)0x9f979331, (q31_t)0x53e73097, (q31_t)0x9f558fb0, + (q31_t)0x539b2af0, (q31_t)0x9f13c7d0, (q31_t)0x534ef1b5, (q31_t)0x9ed23bb9, (q31_t)0x53028518, (q31_t)0x9e90eb94, (q31_t)0x52b5e546, (q31_t)0x9e4fd78a, + (q31_t)0x5269126e, (q31_t)0x9e0effc1, (q31_t)0x521c0cc2, (q31_t)0x9dce6463, (q31_t)0x51ced46e, (q31_t)0x9d8e0597, (q31_t)0x518169a5, (q31_t)0x9d4de385, + (q31_t)0x5133cc94, (q31_t)0x9d0dfe54, (q31_t)0x50e5fd6d, (q31_t)0x9cce562c, (q31_t)0x5097fc5e, (q31_t)0x9c8eeb34, (q31_t)0x5049c999, (q31_t)0x9c4fbd93, + (q31_t)0x4ffb654d, (q31_t)0x9c10cd70, (q31_t)0x4faccfab, (q31_t)0x9bd21af3, (q31_t)0x4f5e08e3, (q31_t)0x9b93a641, (q31_t)0x4f0f1126, (q31_t)0x9b556f81, + (q31_t)0x4ebfe8a5, (q31_t)0x9b1776da, (q31_t)0x4e708f8f, (q31_t)0x9ad9bc71, (q31_t)0x4e210617, (q31_t)0x9a9c406e, (q31_t)0x4dd14c6e, (q31_t)0x9a5f02f5, + (q31_t)0x4d8162c4, (q31_t)0x9a22042d, (q31_t)0x4d31494b, (q31_t)0x99e5443b, (q31_t)0x4ce10034, (q31_t)0x99a8c345, (q31_t)0x4c9087b1, (q31_t)0x996c816f, + (q31_t)0x4c3fdff4, (q31_t)0x99307ee0, (q31_t)0x4bef092d, (q31_t)0x98f4bbbc, (q31_t)0x4b9e0390, (q31_t)0x98b93828, (q31_t)0x4b4ccf4d, (q31_t)0x987df449, + (q31_t)0x4afb6c98, (q31_t)0x9842f043, (q31_t)0x4aa9dba2, (q31_t)0x98082c3b, (q31_t)0x4a581c9e, (q31_t)0x97cda855, (q31_t)0x4a062fbd, (q31_t)0x979364b5, + (q31_t)0x49b41533, (q31_t)0x9759617f, (q31_t)0x4961cd33, (q31_t)0x971f9ed7, (q31_t)0x490f57ee, (q31_t)0x96e61ce0, (q31_t)0x48bcb599, (q31_t)0x96acdbbe, + (q31_t)0x4869e665, (q31_t)0x9673db94, (q31_t)0x4816ea86, (q31_t)0x963b1c86, (q31_t)0x47c3c22f, (q31_t)0x96029eb6, (q31_t)0x47706d93, (q31_t)0x95ca6247, + (q31_t)0x471cece7, (q31_t)0x9592675c, (q31_t)0x46c9405c, (q31_t)0x955aae17, (q31_t)0x46756828, (q31_t)0x9523369c, (q31_t)0x4621647d, (q31_t)0x94ec010b, + (q31_t)0x45cd358f, (q31_t)0x94b50d87, (q31_t)0x4578db93, (q31_t)0x947e5c33, (q31_t)0x452456bd, (q31_t)0x9447ed2f, (q31_t)0x44cfa740, (q31_t)0x9411c09e, + (q31_t)0x447acd50, (q31_t)0x93dbd6a0, (q31_t)0x4425c923, (q31_t)0x93a62f57, (q31_t)0x43d09aed, (q31_t)0x9370cae4, (q31_t)0x437b42e1, (q31_t)0x933ba968, + (q31_t)0x4325c135, (q31_t)0x9306cb04, (q31_t)0x42d0161e, (q31_t)0x92d22fd9, (q31_t)0x427a41d0, (q31_t)0x929dd806, (q31_t)0x42244481, (q31_t)0x9269c3ac, + (q31_t)0x41ce1e65, (q31_t)0x9235f2ec, (q31_t)0x4177cfb1, (q31_t)0x920265e4, (q31_t)0x4121589b, (q31_t)0x91cf1cb6, (q31_t)0x40cab958, (q31_t)0x919c1781, + (q31_t)0x4073f21d, (q31_t)0x91695663, (q31_t)0x401d0321, (q31_t)0x9136d97d, (q31_t)0x3fc5ec98, (q31_t)0x9104a0ee, (q31_t)0x3f6eaeb8, (q31_t)0x90d2acd4, + (q31_t)0x3f1749b8, (q31_t)0x90a0fd4e, (q31_t)0x3ebfbdcd, (q31_t)0x906f927c, (q31_t)0x3e680b2c, (q31_t)0x903e6c7b, (q31_t)0x3e10320d, (q31_t)0x900d8b69, + (q31_t)0x3db832a6, (q31_t)0x8fdcef66, (q31_t)0x3d600d2c, (q31_t)0x8fac988f, (q31_t)0x3d07c1d6, (q31_t)0x8f7c8701, (q31_t)0x3caf50da, (q31_t)0x8f4cbadb, + (q31_t)0x3c56ba70, (q31_t)0x8f1d343a, (q31_t)0x3bfdfecd, (q31_t)0x8eedf33b, (q31_t)0x3ba51e29, (q31_t)0x8ebef7fb, (q31_t)0x3b4c18ba, (q31_t)0x8e904298, + (q31_t)0x3af2eeb7, (q31_t)0x8e61d32e, (q31_t)0x3a99a057, (q31_t)0x8e33a9da, (q31_t)0x3a402dd2, (q31_t)0x8e05c6b7, (q31_t)0x39e6975e, (q31_t)0x8dd829e4, + (q31_t)0x398cdd32, (q31_t)0x8daad37b, (q31_t)0x3932ff87, (q31_t)0x8d7dc399, (q31_t)0x38d8fe93, (q31_t)0x8d50fa59, (q31_t)0x387eda8e, (q31_t)0x8d2477d8, + (q31_t)0x382493b0, (q31_t)0x8cf83c30, (q31_t)0x37ca2a30, (q31_t)0x8ccc477d, (q31_t)0x376f9e46, (q31_t)0x8ca099da, (q31_t)0x3714f02a, (q31_t)0x8c753362, + (q31_t)0x36ba2014, (q31_t)0x8c4a142f, (q31_t)0x365f2e3b, (q31_t)0x8c1f3c5d, (q31_t)0x36041ad9, (q31_t)0x8bf4ac05, (q31_t)0x35a8e625, (q31_t)0x8bca6343, + (q31_t)0x354d9057, (q31_t)0x8ba0622f, (q31_t)0x34f219a8, (q31_t)0x8b76a8e4, (q31_t)0x34968250, (q31_t)0x8b4d377c, (q31_t)0x343aca87, (q31_t)0x8b240e11, + (q31_t)0x33def287, (q31_t)0x8afb2cbb, (q31_t)0x3382fa88, (q31_t)0x8ad29394, (q31_t)0x3326e2c3, (q31_t)0x8aaa42b4, (q31_t)0x32caab6f, (q31_t)0x8a823a36, + (q31_t)0x326e54c7, (q31_t)0x8a5a7a31, (q31_t)0x3211df04, (q31_t)0x8a3302be, (q31_t)0x31b54a5e, (q31_t)0x8a0bd3f5, (q31_t)0x3158970e, (q31_t)0x89e4edef, + (q31_t)0x30fbc54d, (q31_t)0x89be50c3, (q31_t)0x309ed556, (q31_t)0x8997fc8a, (q31_t)0x3041c761, (q31_t)0x8971f15a, (q31_t)0x2fe49ba7, (q31_t)0x894c2f4c, + (q31_t)0x2f875262, (q31_t)0x8926b677, (q31_t)0x2f29ebcc, (q31_t)0x890186f2, (q31_t)0x2ecc681e, (q31_t)0x88dca0d3, (q31_t)0x2e6ec792, (q31_t)0x88b80432, + (q31_t)0x2e110a62, (q31_t)0x8893b125, (q31_t)0x2db330c7, (q31_t)0x886fa7c2, (q31_t)0x2d553afc, (q31_t)0x884be821, (q31_t)0x2cf72939, (q31_t)0x88287256, + (q31_t)0x2c98fbba, (q31_t)0x88054677, (q31_t)0x2c3ab2b9, (q31_t)0x87e2649b, (q31_t)0x2bdc4e6f, (q31_t)0x87bfccd7, (q31_t)0x2b7dcf17, (q31_t)0x879d7f41, + (q31_t)0x2b1f34eb, (q31_t)0x877b7bec, (q31_t)0x2ac08026, (q31_t)0x8759c2ef, (q31_t)0x2a61b101, (q31_t)0x8738545e, (q31_t)0x2a02c7b8, (q31_t)0x8717304e, + (q31_t)0x29a3c485, (q31_t)0x86f656d3, (q31_t)0x2944a7a2, (q31_t)0x86d5c802, (q31_t)0x28e5714b, (q31_t)0x86b583ee, (q31_t)0x288621b9, (q31_t)0x86958aac, + (q31_t)0x2826b928, (q31_t)0x8675dc4f, (q31_t)0x27c737d3, (q31_t)0x865678eb, (q31_t)0x27679df4, (q31_t)0x86376092, (q31_t)0x2707ebc7, (q31_t)0x86189359, + (q31_t)0x26a82186, (q31_t)0x85fa1153, (q31_t)0x26483f6c, (q31_t)0x85dbda91, (q31_t)0x25e845b6, (q31_t)0x85bdef28, (q31_t)0x2588349d, (q31_t)0x85a04f28, + (q31_t)0x25280c5e, (q31_t)0x8582faa5, (q31_t)0x24c7cd33, (q31_t)0x8565f1b0, (q31_t)0x24677758, (q31_t)0x8549345c, (q31_t)0x24070b08, (q31_t)0x852cc2bb, + (q31_t)0x23a6887f, (q31_t)0x85109cdd, (q31_t)0x2345eff8, (q31_t)0x84f4c2d4, (q31_t)0x22e541af, (q31_t)0x84d934b1, (q31_t)0x22847de0, (q31_t)0x84bdf286, + (q31_t)0x2223a4c5, (q31_t)0x84a2fc62, (q31_t)0x21c2b69c, (q31_t)0x84885258, (q31_t)0x2161b3a0, (q31_t)0x846df477, (q31_t)0x21009c0c, (q31_t)0x8453e2cf, + (q31_t)0x209f701c, (q31_t)0x843a1d70, (q31_t)0x203e300d, (q31_t)0x8420a46c, (q31_t)0x1fdcdc1b, (q31_t)0x840777d0, (q31_t)0x1f7b7481, (q31_t)0x83ee97ad, + (q31_t)0x1f19f97b, (q31_t)0x83d60412, (q31_t)0x1eb86b46, (q31_t)0x83bdbd0e, (q31_t)0x1e56ca1e, (q31_t)0x83a5c2b0, (q31_t)0x1df5163f, (q31_t)0x838e1507, + (q31_t)0x1d934fe5, (q31_t)0x8376b422, (q31_t)0x1d31774d, (q31_t)0x835fa00f, (q31_t)0x1ccf8cb3, (q31_t)0x8348d8dc, (q31_t)0x1c6d9053, (q31_t)0x83325e97, + (q31_t)0x1c0b826a, (q31_t)0x831c314e, (q31_t)0x1ba96335, (q31_t)0x83065110, (q31_t)0x1b4732ef, (q31_t)0x82f0bde8, (q31_t)0x1ae4f1d6, (q31_t)0x82db77e5, + (q31_t)0x1a82a026, (q31_t)0x82c67f14, (q31_t)0x1a203e1b, (q31_t)0x82b1d381, (q31_t)0x19bdcbf3, (q31_t)0x829d753a, (q31_t)0x195b49ea, (q31_t)0x8289644b, + (q31_t)0x18f8b83c, (q31_t)0x8275a0c0, (q31_t)0x18961728, (q31_t)0x82622aa6, (q31_t)0x183366e9, (q31_t)0x824f0208, (q31_t)0x17d0a7bc, (q31_t)0x823c26f3, + (q31_t)0x176dd9de, (q31_t)0x82299971, (q31_t)0x170afd8d, (q31_t)0x82175990, (q31_t)0x16a81305, (q31_t)0x82056758, (q31_t)0x16451a83, (q31_t)0x81f3c2d7, + (q31_t)0x15e21445, (q31_t)0x81e26c16, (q31_t)0x157f0086, (q31_t)0x81d16321, (q31_t)0x151bdf86, (q31_t)0x81c0a801, (q31_t)0x14b8b17f, (q31_t)0x81b03ac2, + (q31_t)0x145576b1, (q31_t)0x81a01b6d, (q31_t)0x13f22f58, (q31_t)0x81904a0c, (q31_t)0x138edbb1, (q31_t)0x8180c6a9, (q31_t)0x132b7bf9, (q31_t)0x8171914e, + (q31_t)0x12c8106f, (q31_t)0x8162aa04, (q31_t)0x1264994e, (q31_t)0x815410d4, (q31_t)0x120116d5, (q31_t)0x8145c5c7, (q31_t)0x119d8941, (q31_t)0x8137c8e6, + (q31_t)0x1139f0cf, (q31_t)0x812a1a3a, (q31_t)0x10d64dbd, (q31_t)0x811cb9ca, (q31_t)0x1072a048, (q31_t)0x810fa7a0, (q31_t)0x100ee8ad, (q31_t)0x8102e3c4, + (q31_t)0x0fab272b, (q31_t)0x80f66e3c, (q31_t)0x0f475bff, (q31_t)0x80ea4712, (q31_t)0x0ee38766, (q31_t)0x80de6e4c, (q31_t)0x0e7fa99e, (q31_t)0x80d2e3f2, + (q31_t)0x0e1bc2e4, (q31_t)0x80c7a80a, (q31_t)0x0db7d376, (q31_t)0x80bcba9d, (q31_t)0x0d53db92, (q31_t)0x80b21baf, (q31_t)0x0cefdb76, (q31_t)0x80a7cb49, + (q31_t)0x0c8bd35e, (q31_t)0x809dc971, (q31_t)0x0c27c389, (q31_t)0x8094162c, (q31_t)0x0bc3ac35, (q31_t)0x808ab180, (q31_t)0x0b5f8d9f, (q31_t)0x80819b74, + (q31_t)0x0afb6805, (q31_t)0x8078d40d, (q31_t)0x0a973ba5, (q31_t)0x80705b50, (q31_t)0x0a3308bd, (q31_t)0x80683143, (q31_t)0x09cecf89, (q31_t)0x806055eb, + (q31_t)0x096a9049, (q31_t)0x8058c94c, (q31_t)0x09064b3a, (q31_t)0x80518b6b, (q31_t)0x08a2009a, (q31_t)0x804a9c4d, (q31_t)0x083db0a7, (q31_t)0x8043fbf6, + (q31_t)0x07d95b9e, (q31_t)0x803daa6a, (q31_t)0x077501be, (q31_t)0x8037a7ac, (q31_t)0x0710a345, (q31_t)0x8031f3c2, (q31_t)0x06ac406f, (q31_t)0x802c8ead, + (q31_t)0x0647d97c, (q31_t)0x80277872, (q31_t)0x05e36ea9, (q31_t)0x8022b114, (q31_t)0x057f0035, (q31_t)0x801e3895, (q31_t)0x051a8e5c, (q31_t)0x801a0ef8, + (q31_t)0x04b6195d, (q31_t)0x80163440, (q31_t)0x0451a177, (q31_t)0x8012a86f, (q31_t)0x03ed26e6, (q31_t)0x800f6b88, (q31_t)0x0388a9ea, (q31_t)0x800c7d8c, + (q31_t)0x03242abf, (q31_t)0x8009de7e, (q31_t)0x02bfa9a4, (q31_t)0x80078e5e, (q31_t)0x025b26d7, (q31_t)0x80058d2f, (q31_t)0x01f6a297, (q31_t)0x8003daf1, + (q31_t)0x01921d20, (q31_t)0x800277a6, (q31_t)0x012d96b1, (q31_t)0x8001634e, (q31_t)0x00c90f88, (q31_t)0x80009dea, (q31_t)0x006487e3, (q31_t)0x8000277a +}; + const q31_t cos_factorsQ31_512[512] = { + (q31_t)0x7ffff621, (q31_t)0x7fffa72c, (q31_t)0x7fff0943, (q31_t)0x7ffe1c65, (q31_t)0x7ffce093, (q31_t)0x7ffb55ce, + (q31_t)0x7ff97c18, (q31_t)0x7ff75370, + (q31_t)0x7ff4dbd9, (q31_t)0x7ff21553, (q31_t)0x7feeffe1, (q31_t)0x7feb9b85, (q31_t)0x7fe7e841, (q31_t)0x7fe3e616, + (q31_t)0x7fdf9508, (q31_t)0x7fdaf519, + (q31_t)0x7fd6064c, (q31_t)0x7fd0c8a3, (q31_t)0x7fcb3c23, (q31_t)0x7fc560cf, (q31_t)0x7fbf36aa, (q31_t)0x7fb8bdb8, + (q31_t)0x7fb1f5fc, (q31_t)0x7faadf7c, + (q31_t)0x7fa37a3c, (q31_t)0x7f9bc640, (q31_t)0x7f93c38c, (q31_t)0x7f8b7227, (q31_t)0x7f82d214, (q31_t)0x7f79e35a, + (q31_t)0x7f70a5fe, (q31_t)0x7f671a05, + (q31_t)0x7f5d3f75, (q31_t)0x7f531655, (q31_t)0x7f489eaa, (q31_t)0x7f3dd87c, (q31_t)0x7f32c3d1, (q31_t)0x7f2760af, + (q31_t)0x7f1baf1e, (q31_t)0x7f0faf25, + (q31_t)0x7f0360cb, (q31_t)0x7ef6c418, (q31_t)0x7ee9d914, (q31_t)0x7edc9fc6, (q31_t)0x7ecf1837, (q31_t)0x7ec14270, + (q31_t)0x7eb31e78, (q31_t)0x7ea4ac58, + (q31_t)0x7e95ec1a, (q31_t)0x7e86ddc6, (q31_t)0x7e778166, (q31_t)0x7e67d703, (q31_t)0x7e57dea7, (q31_t)0x7e47985b, + (q31_t)0x7e37042a, (q31_t)0x7e26221f, + (q31_t)0x7e14f242, (q31_t)0x7e0374a0, (q31_t)0x7df1a942, (q31_t)0x7ddf9034, (q31_t)0x7dcd2981, (q31_t)0x7dba7534, + (q31_t)0x7da77359, (q31_t)0x7d9423fc, + (q31_t)0x7d808728, (q31_t)0x7d6c9ce9, (q31_t)0x7d58654d, (q31_t)0x7d43e05e, (q31_t)0x7d2f0e2b, (q31_t)0x7d19eebf, + (q31_t)0x7d048228, (q31_t)0x7ceec873, + (q31_t)0x7cd8c1ae, (q31_t)0x7cc26de5, (q31_t)0x7cabcd28, (q31_t)0x7c94df83, (q31_t)0x7c7da505, (q31_t)0x7c661dbc, + (q31_t)0x7c4e49b7, (q31_t)0x7c362904, + (q31_t)0x7c1dbbb3, (q31_t)0x7c0501d2, (q31_t)0x7bebfb70, (q31_t)0x7bd2a89e, (q31_t)0x7bb9096b, (q31_t)0x7b9f1de6, + (q31_t)0x7b84e61f, (q31_t)0x7b6a6227, + (q31_t)0x7b4f920e, (q31_t)0x7b3475e5, (q31_t)0x7b190dbc, (q31_t)0x7afd59a4, (q31_t)0x7ae159ae, (q31_t)0x7ac50dec, + (q31_t)0x7aa8766f, (q31_t)0x7a8b9348, + (q31_t)0x7a6e648a, (q31_t)0x7a50ea47, (q31_t)0x7a332490, (q31_t)0x7a151378, (q31_t)0x79f6b711, (q31_t)0x79d80f6f, + (q31_t)0x79b91ca4, (q31_t)0x7999dec4, + (q31_t)0x797a55e0, (q31_t)0x795a820e, (q31_t)0x793a6361, (q31_t)0x7919f9ec, (q31_t)0x78f945c3, (q31_t)0x78d846fb, + (q31_t)0x78b6fda8, (q31_t)0x789569df, + (q31_t)0x78738bb3, (q31_t)0x7851633b, (q31_t)0x782ef08b, (q31_t)0x780c33b8, (q31_t)0x77e92cd9, (q31_t)0x77c5dc01, + (q31_t)0x77a24148, (q31_t)0x777e5cc3, + (q31_t)0x775a2e89, (q31_t)0x7735b6af, (q31_t)0x7710f54c, (q31_t)0x76ebea77, (q31_t)0x76c69647, (q31_t)0x76a0f8d2, + (q31_t)0x767b1231, (q31_t)0x7654e279, + (q31_t)0x762e69c4, (q31_t)0x7607a828, (q31_t)0x75e09dbd, (q31_t)0x75b94a9c, (q31_t)0x7591aedd, (q31_t)0x7569ca99, + (q31_t)0x75419de7, (q31_t)0x751928e0, + (q31_t)0x74f06b9e, (q31_t)0x74c7663a, (q31_t)0x749e18cd, (q31_t)0x74748371, (q31_t)0x744aa63f, (q31_t)0x74208150, + (q31_t)0x73f614c0, (q31_t)0x73cb60a8, + (q31_t)0x73a06522, (q31_t)0x73752249, (q31_t)0x73499838, (q31_t)0x731dc70a, (q31_t)0x72f1aed9, (q31_t)0x72c54fc1, + (q31_t)0x7298a9dd, (q31_t)0x726bbd48, + (q31_t)0x723e8a20, (q31_t)0x7211107e, (q31_t)0x71e35080, (q31_t)0x71b54a41, (q31_t)0x7186fdde, (q31_t)0x71586b74, + (q31_t)0x7129931f, (q31_t)0x70fa74fc, + (q31_t)0x70cb1128, (q31_t)0x709b67c0, (q31_t)0x706b78e3, (q31_t)0x703b44ad, (q31_t)0x700acb3c, (q31_t)0x6fda0cae, + (q31_t)0x6fa90921, (q31_t)0x6f77c0b3, + (q31_t)0x6f463383, (q31_t)0x6f1461b0, (q31_t)0x6ee24b57, (q31_t)0x6eaff099, (q31_t)0x6e7d5193, (q31_t)0x6e4a6e66, + (q31_t)0x6e174730, (q31_t)0x6de3dc11, + (q31_t)0x6db02d29, (q31_t)0x6d7c3a98, (q31_t)0x6d48047e, (q31_t)0x6d138afb, (q31_t)0x6cdece2f, (q31_t)0x6ca9ce3b, + (q31_t)0x6c748b3f, (q31_t)0x6c3f055d, + (q31_t)0x6c093cb6, (q31_t)0x6bd3316a, (q31_t)0x6b9ce39b, (q31_t)0x6b66536b, (q31_t)0x6b2f80fb, (q31_t)0x6af86c6c, + (q31_t)0x6ac115e2, (q31_t)0x6a897d7d, + (q31_t)0x6a51a361, (q31_t)0x6a1987b0, (q31_t)0x69e12a8c, (q31_t)0x69a88c19, (q31_t)0x696fac78, (q31_t)0x69368bce, + (q31_t)0x68fd2a3d, (q31_t)0x68c387e9, + (q31_t)0x6889a4f6, (q31_t)0x684f8186, (q31_t)0x68151dbe, (q31_t)0x67da79c3, (q31_t)0x679f95b7, (q31_t)0x676471c0, + (q31_t)0x67290e02, (q31_t)0x66ed6aa1, + (q31_t)0x66b187c3, (q31_t)0x6675658c, (q31_t)0x66390422, (q31_t)0x65fc63a9, (q31_t)0x65bf8447, (q31_t)0x65826622, + (q31_t)0x6545095f, (q31_t)0x65076e25, + (q31_t)0x64c99498, (q31_t)0x648b7ce0, (q31_t)0x644d2722, (q31_t)0x640e9386, (q31_t)0x63cfc231, (q31_t)0x6390b34a, + (q31_t)0x635166f9, (q31_t)0x6311dd64, + (q31_t)0x62d216b3, (q31_t)0x6292130c, (q31_t)0x6251d298, (q31_t)0x6211557e, (q31_t)0x61d09be5, (q31_t)0x618fa5f7, + (q31_t)0x614e73da, (q31_t)0x610d05b7, + (q31_t)0x60cb5bb7, (q31_t)0x60897601, (q31_t)0x604754bf, (q31_t)0x6004f819, (q31_t)0x5fc26038, (q31_t)0x5f7f8d46, + (q31_t)0x5f3c7f6b, (q31_t)0x5ef936d1, + (q31_t)0x5eb5b3a2, (q31_t)0x5e71f606, (q31_t)0x5e2dfe29, (q31_t)0x5de9cc33, (q31_t)0x5da5604f, (q31_t)0x5d60baa7, + (q31_t)0x5d1bdb65, (q31_t)0x5cd6c2b5, + (q31_t)0x5c9170bf, (q31_t)0x5c4be5b0, (q31_t)0x5c0621b2, (q31_t)0x5bc024f0, (q31_t)0x5b79ef96, (q31_t)0x5b3381ce, + (q31_t)0x5aecdbc5, (q31_t)0x5aa5fda5, + (q31_t)0x5a5ee79a, (q31_t)0x5a1799d1, (q31_t)0x59d01475, (q31_t)0x598857b2, (q31_t)0x594063b5, (q31_t)0x58f838a9, + (q31_t)0x58afd6bd, (q31_t)0x58673e1b, + (q31_t)0x581e6ef1, (q31_t)0x57d5696d, (q31_t)0x578c2dba, (q31_t)0x5742bc06, (q31_t)0x56f9147e, (q31_t)0x56af3750, + (q31_t)0x566524aa, (q31_t)0x561adcb9, + (q31_t)0x55d05faa, (q31_t)0x5585adad, (q31_t)0x553ac6ee, (q31_t)0x54efab9c, (q31_t)0x54a45be6, (q31_t)0x5458d7f9, + (q31_t)0x540d2005, (q31_t)0x53c13439, + (q31_t)0x537514c2, (q31_t)0x5328c1d0, (q31_t)0x52dc3b92, (q31_t)0x528f8238, (q31_t)0x524295f0, (q31_t)0x51f576ea, + (q31_t)0x51a82555, (q31_t)0x515aa162, + (q31_t)0x510ceb40, (q31_t)0x50bf031f, (q31_t)0x5070e92f, (q31_t)0x50229da1, (q31_t)0x4fd420a4, (q31_t)0x4f857269, + (q31_t)0x4f369320, (q31_t)0x4ee782fb, + (q31_t)0x4e984229, (q31_t)0x4e48d0dd, (q31_t)0x4df92f46, (q31_t)0x4da95d96, (q31_t)0x4d595bfe, (q31_t)0x4d092ab0, + (q31_t)0x4cb8c9dd, (q31_t)0x4c6839b7, + (q31_t)0x4c177a6e, (q31_t)0x4bc68c36, (q31_t)0x4b756f40, (q31_t)0x4b2423be, (q31_t)0x4ad2a9e2, (q31_t)0x4a8101de, + (q31_t)0x4a2f2be6, (q31_t)0x49dd282a, + (q31_t)0x498af6df, (q31_t)0x49389836, (q31_t)0x48e60c62, (q31_t)0x48935397, (q31_t)0x48406e08, (q31_t)0x47ed5be6, + (q31_t)0x479a1d67, (q31_t)0x4746b2bc, + (q31_t)0x46f31c1a, (q31_t)0x469f59b4, (q31_t)0x464b6bbe, (q31_t)0x45f7526b, (q31_t)0x45a30df0, (q31_t)0x454e9e80, + (q31_t)0x44fa0450, (q31_t)0x44a53f93, + (q31_t)0x4450507e, (q31_t)0x43fb3746, (q31_t)0x43a5f41e, (q31_t)0x4350873c, (q31_t)0x42faf0d4, (q31_t)0x42a5311b, + (q31_t)0x424f4845, (q31_t)0x41f93689, + (q31_t)0x41a2fc1a, (q31_t)0x414c992f, (q31_t)0x40f60dfb, (q31_t)0x409f5ab6, (q31_t)0x40487f94, (q31_t)0x3ff17cca, + (q31_t)0x3f9a5290, (q31_t)0x3f430119, + (q31_t)0x3eeb889c, (q31_t)0x3e93e950, (q31_t)0x3e3c2369, (q31_t)0x3de4371f, (q31_t)0x3d8c24a8, (q31_t)0x3d33ec39, + (q31_t)0x3cdb8e09, (q31_t)0x3c830a50, + (q31_t)0x3c2a6142, (q31_t)0x3bd19318, (q31_t)0x3b78a007, (q31_t)0x3b1f8848, (q31_t)0x3ac64c0f, (q31_t)0x3a6ceb96, + (q31_t)0x3a136712, (q31_t)0x39b9bebc, + (q31_t)0x395ff2c9, (q31_t)0x39060373, (q31_t)0x38abf0ef, (q31_t)0x3851bb77, (q31_t)0x37f76341, (q31_t)0x379ce885, + (q31_t)0x37424b7b, (q31_t)0x36e78c5b, + (q31_t)0x368cab5c, (q31_t)0x3631a8b8, (q31_t)0x35d684a6, (q31_t)0x357b3f5d, (q31_t)0x351fd918, (q31_t)0x34c4520d, + (q31_t)0x3468aa76, (q31_t)0x340ce28b, + (q31_t)0x33b0fa84, (q31_t)0x3354f29b, (q31_t)0x32f8cb07, (q31_t)0x329c8402, (q31_t)0x32401dc6, (q31_t)0x31e39889, + (q31_t)0x3186f487, (q31_t)0x312a31f8, + (q31_t)0x30cd5115, (q31_t)0x30705217, (q31_t)0x30133539, (q31_t)0x2fb5fab2, (q31_t)0x2f58a2be, (q31_t)0x2efb2d95, + (q31_t)0x2e9d9b70, (q31_t)0x2e3fec8b, + (q31_t)0x2de2211e, (q31_t)0x2d843964, (q31_t)0x2d263596, (q31_t)0x2cc815ee, (q31_t)0x2c69daa6, (q31_t)0x2c0b83fa, + (q31_t)0x2bad1221, (q31_t)0x2b4e8558, + (q31_t)0x2aefddd8, (q31_t)0x2a911bdc, (q31_t)0x2a323f9e, (q31_t)0x29d34958, (q31_t)0x29743946, (q31_t)0x29150fa1, + (q31_t)0x28b5cca5, (q31_t)0x2856708d, + (q31_t)0x27f6fb92, (q31_t)0x27976df1, (q31_t)0x2737c7e3, (q31_t)0x26d809a5, (q31_t)0x26783370, (q31_t)0x26184581, + (q31_t)0x25b84012, (q31_t)0x2558235f, + (q31_t)0x24f7efa2, (q31_t)0x2497a517, (q31_t)0x243743fa, (q31_t)0x23d6cc87, (q31_t)0x23763ef7, (q31_t)0x23159b88, + (q31_t)0x22b4e274, (q31_t)0x225413f8, + (q31_t)0x21f3304f, (q31_t)0x219237b5, (q31_t)0x21312a65, (q31_t)0x20d0089c, (q31_t)0x206ed295, (q31_t)0x200d888d, + (q31_t)0x1fac2abf, (q31_t)0x1f4ab968, + (q31_t)0x1ee934c3, (q31_t)0x1e879d0d, (q31_t)0x1e25f282, (q31_t)0x1dc4355e, (q31_t)0x1d6265dd, (q31_t)0x1d00843d, + (q31_t)0x1c9e90b8, (q31_t)0x1c3c8b8c, + (q31_t)0x1bda74f6, (q31_t)0x1b784d30, (q31_t)0x1b161479, (q31_t)0x1ab3cb0d, (q31_t)0x1a517128, (q31_t)0x19ef0707, + (q31_t)0x198c8ce7, (q31_t)0x192a0304, + (q31_t)0x18c7699b, (q31_t)0x1864c0ea, (q31_t)0x1802092c, (q31_t)0x179f429f, (q31_t)0x173c6d80, (q31_t)0x16d98a0c, + (q31_t)0x1676987f, (q31_t)0x16139918, + (q31_t)0x15b08c12, (q31_t)0x154d71aa, (q31_t)0x14ea4a1f, (q31_t)0x148715ae, (q31_t)0x1423d492, (q31_t)0x13c0870a, + (q31_t)0x135d2d53, (q31_t)0x12f9c7aa, + (q31_t)0x1296564d, (q31_t)0x1232d979, (q31_t)0x11cf516a, (q31_t)0x116bbe60, (q31_t)0x11082096, (q31_t)0x10a4784b, + (q31_t)0x1040c5bb, (q31_t)0xfdd0926, + (q31_t)0xf7942c7, (q31_t)0xf1572dc, (q31_t)0xeb199a4, (q31_t)0xe4db75b, (q31_t)0xde9cc40, (q31_t)0xd85d88f, (q31_t)0xd21dc87, + (q31_t)0xcbdd865, + (q31_t)0xc59cc68, (q31_t)0xbf5b8cb, (q31_t)0xb919dcf, (q31_t)0xb2d7baf, (q31_t)0xac952aa, (q31_t)0xa6522fe, (q31_t)0xa00ece8, + (q31_t)0x99cb0a7, + (q31_t)0x9386e78, (q31_t)0x8d42699, (q31_t)0x86fd947, (q31_t)0x80b86c2, (q31_t)0x7a72f45, (q31_t)0x742d311, (q31_t)0x6de7262, + (q31_t)0x67a0d76, + (q31_t)0x615a48b, (q31_t)0x5b137df, (q31_t)0x54cc7b1, (q31_t)0x4e8543e, (q31_t)0x483ddc3, (q31_t)0x41f6480, (q31_t)0x3bae8b2, + (q31_t)0x3566a96, + (q31_t)0x2f1ea6c, (q31_t)0x28d6870, (q31_t)0x228e4e2, (q31_t)0x1c45ffe, (q31_t)0x15fda03, (q31_t)0xfb5330, (q31_t)0x96cbc1, + (q31_t)0x3243f5 +}; + #endif + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_DCT4_Q31_2048) + const q31_t WeightsQ31_2048[4096] = { + (q31_t)0x7fffffff, (q31_t)0x00000000, (q31_t)0x7ffffd88, (q31_t)0xffe6de05, (q31_t)0x7ffff621, (q31_t)0xffcdbc0b, (q31_t)0x7fffe9cb, (q31_t)0xffb49a12, + (q31_t)0x7fffd886, (q31_t)0xff9b781d, (q31_t)0x7fffc251, (q31_t)0xff82562c, (q31_t)0x7fffa72c, (q31_t)0xff69343f, (q31_t)0x7fff8719, (q31_t)0xff501258, + (q31_t)0x7fff6216, (q31_t)0xff36f078, (q31_t)0x7fff3824, (q31_t)0xff1dcea0, (q31_t)0x7fff0943, (q31_t)0xff04acd0, (q31_t)0x7ffed572, (q31_t)0xfeeb8b0a, + (q31_t)0x7ffe9cb2, (q31_t)0xfed2694f, (q31_t)0x7ffe5f03, (q31_t)0xfeb947a0, (q31_t)0x7ffe1c65, (q31_t)0xfea025fd, (q31_t)0x7ffdd4d7, (q31_t)0xfe870467, + (q31_t)0x7ffd885a, (q31_t)0xfe6de2e0, (q31_t)0x7ffd36ee, (q31_t)0xfe54c169, (q31_t)0x7ffce093, (q31_t)0xfe3ba002, (q31_t)0x7ffc8549, (q31_t)0xfe227eac, + (q31_t)0x7ffc250f, (q31_t)0xfe095d69, (q31_t)0x7ffbbfe6, (q31_t)0xfdf03c3a, (q31_t)0x7ffb55ce, (q31_t)0xfdd71b1e, (q31_t)0x7ffae6c7, (q31_t)0xfdbdfa18, + (q31_t)0x7ffa72d1, (q31_t)0xfda4d929, (q31_t)0x7ff9f9ec, (q31_t)0xfd8bb850, (q31_t)0x7ff97c18, (q31_t)0xfd729790, (q31_t)0x7ff8f954, (q31_t)0xfd5976e9, + (q31_t)0x7ff871a2, (q31_t)0xfd40565c, (q31_t)0x7ff7e500, (q31_t)0xfd2735ea, (q31_t)0x7ff75370, (q31_t)0xfd0e1594, (q31_t)0x7ff6bcf0, (q31_t)0xfcf4f55c, + (q31_t)0x7ff62182, (q31_t)0xfcdbd541, (q31_t)0x7ff58125, (q31_t)0xfcc2b545, (q31_t)0x7ff4dbd9, (q31_t)0xfca9956a, (q31_t)0x7ff4319d, (q31_t)0xfc9075af, + (q31_t)0x7ff38274, (q31_t)0xfc775616, (q31_t)0x7ff2ce5b, (q31_t)0xfc5e36a0, (q31_t)0x7ff21553, (q31_t)0xfc45174e, (q31_t)0x7ff1575d, (q31_t)0xfc2bf821, + (q31_t)0x7ff09478, (q31_t)0xfc12d91a, (q31_t)0x7fefcca4, (q31_t)0xfbf9ba39, (q31_t)0x7feeffe1, (q31_t)0xfbe09b80, (q31_t)0x7fee2e30, (q31_t)0xfbc77cf0, + (q31_t)0x7fed5791, (q31_t)0xfbae5e89, (q31_t)0x7fec7c02, (q31_t)0xfb95404d, (q31_t)0x7feb9b85, (q31_t)0xfb7c223d, (q31_t)0x7feab61a, (q31_t)0xfb630459, + (q31_t)0x7fe9cbc0, (q31_t)0xfb49e6a3, (q31_t)0x7fe8dc78, (q31_t)0xfb30c91b, (q31_t)0x7fe7e841, (q31_t)0xfb17abc2, (q31_t)0x7fe6ef1c, (q31_t)0xfafe8e9b, + (q31_t)0x7fe5f108, (q31_t)0xfae571a4, (q31_t)0x7fe4ee06, (q31_t)0xfacc54e0, (q31_t)0x7fe3e616, (q31_t)0xfab3384f, (q31_t)0x7fe2d938, (q31_t)0xfa9a1bf3, + (q31_t)0x7fe1c76b, (q31_t)0xfa80ffcb, (q31_t)0x7fe0b0b1, (q31_t)0xfa67e3da, (q31_t)0x7fdf9508, (q31_t)0xfa4ec821, (q31_t)0x7fde7471, (q31_t)0xfa35ac9f, + (q31_t)0x7fdd4eec, (q31_t)0xfa1c9157, (q31_t)0x7fdc247a, (q31_t)0xfa037648, (q31_t)0x7fdaf519, (q31_t)0xf9ea5b75, (q31_t)0x7fd9c0ca, (q31_t)0xf9d140de, + (q31_t)0x7fd8878e, (q31_t)0xf9b82684, (q31_t)0x7fd74964, (q31_t)0xf99f0c68, (q31_t)0x7fd6064c, (q31_t)0xf985f28a, (q31_t)0x7fd4be46, (q31_t)0xf96cd8ed, + (q31_t)0x7fd37153, (q31_t)0xf953bf91, (q31_t)0x7fd21f72, (q31_t)0xf93aa676, (q31_t)0x7fd0c8a3, (q31_t)0xf9218d9e, (q31_t)0x7fcf6ce8, (q31_t)0xf908750a, + (q31_t)0x7fce0c3e, (q31_t)0xf8ef5cbb, (q31_t)0x7fcca6a7, (q31_t)0xf8d644b2, (q31_t)0x7fcb3c23, (q31_t)0xf8bd2cef, (q31_t)0x7fc9ccb2, (q31_t)0xf8a41574, + (q31_t)0x7fc85854, (q31_t)0xf88afe42, (q31_t)0x7fc6df08, (q31_t)0xf871e759, (q31_t)0x7fc560cf, (q31_t)0xf858d0bb, (q31_t)0x7fc3dda9, (q31_t)0xf83fba68, + (q31_t)0x7fc25596, (q31_t)0xf826a462, (q31_t)0x7fc0c896, (q31_t)0xf80d8ea9, (q31_t)0x7fbf36aa, (q31_t)0xf7f4793e, (q31_t)0x7fbd9fd0, (q31_t)0xf7db6423, + (q31_t)0x7fbc040a, (q31_t)0xf7c24f59, (q31_t)0x7fba6357, (q31_t)0xf7a93ae0, (q31_t)0x7fb8bdb8, (q31_t)0xf79026b9, (q31_t)0x7fb7132b, (q31_t)0xf77712e5, + (q31_t)0x7fb563b3, (q31_t)0xf75dff66, (q31_t)0x7fb3af4e, (q31_t)0xf744ec3b, (q31_t)0x7fb1f5fc, (q31_t)0xf72bd967, (q31_t)0x7fb037bf, (q31_t)0xf712c6ea, + (q31_t)0x7fae7495, (q31_t)0xf6f9b4c6, (q31_t)0x7facac7f, (q31_t)0xf6e0a2fa, (q31_t)0x7faadf7c, (q31_t)0xf6c79188, (q31_t)0x7fa90d8e, (q31_t)0xf6ae8071, + (q31_t)0x7fa736b4, (q31_t)0xf6956fb7, (q31_t)0x7fa55aee, (q31_t)0xf67c5f59, (q31_t)0x7fa37a3c, (q31_t)0xf6634f59, (q31_t)0x7fa1949e, (q31_t)0xf64a3fb8, + (q31_t)0x7f9faa15, (q31_t)0xf6313077, (q31_t)0x7f9dbaa0, (q31_t)0xf6182196, (q31_t)0x7f9bc640, (q31_t)0xf5ff1318, (q31_t)0x7f99ccf4, (q31_t)0xf5e604fc, + (q31_t)0x7f97cebd, (q31_t)0xf5ccf743, (q31_t)0x7f95cb9a, (q31_t)0xf5b3e9f0, (q31_t)0x7f93c38c, (q31_t)0xf59add02, (q31_t)0x7f91b694, (q31_t)0xf581d07b, + (q31_t)0x7f8fa4b0, (q31_t)0xf568c45b, (q31_t)0x7f8d8de1, (q31_t)0xf54fb8a4, (q31_t)0x7f8b7227, (q31_t)0xf536ad56, (q31_t)0x7f895182, (q31_t)0xf51da273, + (q31_t)0x7f872bf3, (q31_t)0xf50497fb, (q31_t)0x7f850179, (q31_t)0xf4eb8def, (q31_t)0x7f82d214, (q31_t)0xf4d28451, (q31_t)0x7f809dc5, (q31_t)0xf4b97b21, + (q31_t)0x7f7e648c, (q31_t)0xf4a07261, (q31_t)0x7f7c2668, (q31_t)0xf4876a10, (q31_t)0x7f79e35a, (q31_t)0xf46e6231, (q31_t)0x7f779b62, (q31_t)0xf4555ac5, + (q31_t)0x7f754e80, (q31_t)0xf43c53cb, (q31_t)0x7f72fcb4, (q31_t)0xf4234d45, (q31_t)0x7f70a5fe, (q31_t)0xf40a4735, (q31_t)0x7f6e4a5e, (q31_t)0xf3f1419a, + (q31_t)0x7f6be9d4, (q31_t)0xf3d83c77, (q31_t)0x7f698461, (q31_t)0xf3bf37cb, (q31_t)0x7f671a05, (q31_t)0xf3a63398, (q31_t)0x7f64aabf, (q31_t)0xf38d2fe0, + (q31_t)0x7f62368f, (q31_t)0xf3742ca2, (q31_t)0x7f5fbd77, (q31_t)0xf35b29e0, (q31_t)0x7f5d3f75, (q31_t)0xf342279b, (q31_t)0x7f5abc8a, (q31_t)0xf32925d3, + (q31_t)0x7f5834b7, (q31_t)0xf310248a, (q31_t)0x7f55a7fa, (q31_t)0xf2f723c1, (q31_t)0x7f531655, (q31_t)0xf2de2379, (q31_t)0x7f507fc7, (q31_t)0xf2c523b2, + (q31_t)0x7f4de451, (q31_t)0xf2ac246e, (q31_t)0x7f4b43f2, (q31_t)0xf29325ad, (q31_t)0x7f489eaa, (q31_t)0xf27a2771, (q31_t)0x7f45f47b, (q31_t)0xf26129ba, + (q31_t)0x7f434563, (q31_t)0xf2482c8a, (q31_t)0x7f409164, (q31_t)0xf22f2fe1, (q31_t)0x7f3dd87c, (q31_t)0xf21633c0, (q31_t)0x7f3b1aad, (q31_t)0xf1fd3829, + (q31_t)0x7f3857f6, (q31_t)0xf1e43d1c, (q31_t)0x7f359057, (q31_t)0xf1cb429a, (q31_t)0x7f32c3d1, (q31_t)0xf1b248a5, (q31_t)0x7f2ff263, (q31_t)0xf1994f3d, + (q31_t)0x7f2d1c0e, (q31_t)0xf1805662, (q31_t)0x7f2a40d2, (q31_t)0xf1675e17, (q31_t)0x7f2760af, (q31_t)0xf14e665c, (q31_t)0x7f247ba5, (q31_t)0xf1356f32, + (q31_t)0x7f2191b4, (q31_t)0xf11c789a, (q31_t)0x7f1ea2dc, (q31_t)0xf1038295, (q31_t)0x7f1baf1e, (q31_t)0xf0ea8d24, (q31_t)0x7f18b679, (q31_t)0xf0d19848, + (q31_t)0x7f15b8ee, (q31_t)0xf0b8a401, (q31_t)0x7f12b67c, (q31_t)0xf09fb051, (q31_t)0x7f0faf25, (q31_t)0xf086bd39, (q31_t)0x7f0ca2e7, (q31_t)0xf06dcaba, + (q31_t)0x7f0991c4, (q31_t)0xf054d8d5, (q31_t)0x7f067bba, (q31_t)0xf03be78a, (q31_t)0x7f0360cb, (q31_t)0xf022f6da, (q31_t)0x7f0040f6, (q31_t)0xf00a06c8, + (q31_t)0x7efd1c3c, (q31_t)0xeff11753, (q31_t)0x7ef9f29d, (q31_t)0xefd8287c, (q31_t)0x7ef6c418, (q31_t)0xefbf3a45, (q31_t)0x7ef390ae, (q31_t)0xefa64cae, + (q31_t)0x7ef05860, (q31_t)0xef8d5fb8, (q31_t)0x7eed1b2c, (q31_t)0xef747365, (q31_t)0x7ee9d914, (q31_t)0xef5b87b5, (q31_t)0x7ee69217, (q31_t)0xef429caa, + (q31_t)0x7ee34636, (q31_t)0xef29b243, (q31_t)0x7edff570, (q31_t)0xef10c883, (q31_t)0x7edc9fc6, (q31_t)0xeef7df6a, (q31_t)0x7ed94538, (q31_t)0xeedef6f9, + (q31_t)0x7ed5e5c6, (q31_t)0xeec60f31, (q31_t)0x7ed28171, (q31_t)0xeead2813, (q31_t)0x7ecf1837, (q31_t)0xee9441a0, (q31_t)0x7ecbaa1a, (q31_t)0xee7b5bd9, + (q31_t)0x7ec8371a, (q31_t)0xee6276bf, (q31_t)0x7ec4bf36, (q31_t)0xee499253, (q31_t)0x7ec14270, (q31_t)0xee30ae96, (q31_t)0x7ebdc0c6, (q31_t)0xee17cb88, + (q31_t)0x7eba3a39, (q31_t)0xedfee92b, (q31_t)0x7eb6aeca, (q31_t)0xede60780, (q31_t)0x7eb31e78, (q31_t)0xedcd2687, (q31_t)0x7eaf8943, (q31_t)0xedb44642, + (q31_t)0x7eabef2c, (q31_t)0xed9b66b2, (q31_t)0x7ea85033, (q31_t)0xed8287d7, (q31_t)0x7ea4ac58, (q31_t)0xed69a9b3, (q31_t)0x7ea1039b, (q31_t)0xed50cc46, + (q31_t)0x7e9d55fc, (q31_t)0xed37ef91, (q31_t)0x7e99a37c, (q31_t)0xed1f1396, (q31_t)0x7e95ec1a, (q31_t)0xed063856, (q31_t)0x7e922fd6, (q31_t)0xeced5dd0, + (q31_t)0x7e8e6eb2, (q31_t)0xecd48407, (q31_t)0x7e8aa8ac, (q31_t)0xecbbaafb, (q31_t)0x7e86ddc6, (q31_t)0xeca2d2ad, (q31_t)0x7e830dff, (q31_t)0xec89fb1e, + (q31_t)0x7e7f3957, (q31_t)0xec71244f, (q31_t)0x7e7b5fce, (q31_t)0xec584e41, (q31_t)0x7e778166, (q31_t)0xec3f78f6, (q31_t)0x7e739e1d, (q31_t)0xec26a46d, + (q31_t)0x7e6fb5f4, (q31_t)0xec0dd0a8, (q31_t)0x7e6bc8eb, (q31_t)0xebf4fda8, (q31_t)0x7e67d703, (q31_t)0xebdc2b6e, (q31_t)0x7e63e03b, (q31_t)0xebc359fb, + (q31_t)0x7e5fe493, (q31_t)0xebaa894f, (q31_t)0x7e5be40c, (q31_t)0xeb91b96c, (q31_t)0x7e57dea7, (q31_t)0xeb78ea52, (q31_t)0x7e53d462, (q31_t)0xeb601c04, + (q31_t)0x7e4fc53e, (q31_t)0xeb474e81, (q31_t)0x7e4bb13c, (q31_t)0xeb2e81ca, (q31_t)0x7e47985b, (q31_t)0xeb15b5e1, (q31_t)0x7e437a9c, (q31_t)0xeafceac6, + (q31_t)0x7e3f57ff, (q31_t)0xeae4207a, (q31_t)0x7e3b3083, (q31_t)0xeacb56ff, (q31_t)0x7e37042a, (q31_t)0xeab28e56, (q31_t)0x7e32d2f4, (q31_t)0xea99c67e, + (q31_t)0x7e2e9cdf, (q31_t)0xea80ff7a, (q31_t)0x7e2a61ed, (q31_t)0xea683949, (q31_t)0x7e26221f, (q31_t)0xea4f73ee, (q31_t)0x7e21dd73, (q31_t)0xea36af69, + (q31_t)0x7e1d93ea, (q31_t)0xea1debbb, (q31_t)0x7e194584, (q31_t)0xea0528e5, (q31_t)0x7e14f242, (q31_t)0xe9ec66e8, (q31_t)0x7e109a24, (q31_t)0xe9d3a5c5, + (q31_t)0x7e0c3d29, (q31_t)0xe9bae57d, (q31_t)0x7e07db52, (q31_t)0xe9a22610, (q31_t)0x7e0374a0, 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(q31_t)0x17e958ea, (q31_t)0x8240d673, + (q31_t)0x17d0a7bc, (q31_t)0x823c26f3, (q31_t)0x17b7f5a3, (q31_t)0x82377c4c, (q31_t)0x179f429f, (q31_t)0x8232d67f, (q31_t)0x17868eb3, (q31_t)0x822e358b, + (q31_t)0x176dd9de, (q31_t)0x82299971, (q31_t)0x17552422, (q31_t)0x82250232, (q31_t)0x173c6d80, (q31_t)0x82206fcc, (q31_t)0x1723b5f9, (q31_t)0x821be240, + (q31_t)0x170afd8d, (q31_t)0x82175990, (q31_t)0x16f2443e, (q31_t)0x8212d5b9, (q31_t)0x16d98a0c, (q31_t)0x820e56be, (q31_t)0x16c0cef9, (q31_t)0x8209dc9e, + (q31_t)0x16a81305, (q31_t)0x82056758, (q31_t)0x168f5632, (q31_t)0x8200f6ef, (q31_t)0x1676987f, (q31_t)0x81fc8b60, (q31_t)0x165dd9f0, (q31_t)0x81f824ae, + (q31_t)0x16451a83, (q31_t)0x81f3c2d7, (q31_t)0x162c5a3b, (q31_t)0x81ef65dc, (q31_t)0x16139918, (q31_t)0x81eb0dbe, (q31_t)0x15fad71b, (q31_t)0x81e6ba7c, + (q31_t)0x15e21445, (q31_t)0x81e26c16, (q31_t)0x15c95097, (q31_t)0x81de228d, (q31_t)0x15b08c12, (q31_t)0x81d9dde1, (q31_t)0x1597c6b7, (q31_t)0x81d59e13, + (q31_t)0x157f0086, (q31_t)0x81d16321, (q31_t)0x15663982, (q31_t)0x81cd2d0c, (q31_t)0x154d71aa, (q31_t)0x81c8fbd6, (q31_t)0x1534a901, (q31_t)0x81c4cf7d, + (q31_t)0x151bdf86, (q31_t)0x81c0a801, (q31_t)0x1503153a, (q31_t)0x81bc8564, (q31_t)0x14ea4a1f, (q31_t)0x81b867a5, (q31_t)0x14d17e36, (q31_t)0x81b44ec4, + (q31_t)0x14b8b17f, (q31_t)0x81b03ac2, (q31_t)0x149fe3fc, (q31_t)0x81ac2b9e, (q31_t)0x148715ae, (q31_t)0x81a82159, (q31_t)0x146e4694, (q31_t)0x81a41bf4, + (q31_t)0x145576b1, (q31_t)0x81a01b6d, (q31_t)0x143ca605, (q31_t)0x819c1fc5, (q31_t)0x1423d492, (q31_t)0x819828fd, (q31_t)0x140b0258, (q31_t)0x81943715, + (q31_t)0x13f22f58, (q31_t)0x81904a0c, (q31_t)0x13d95b93, (q31_t)0x818c61e3, (q31_t)0x13c0870a, (q31_t)0x81887e9a, (q31_t)0x13a7b1bf, (q31_t)0x8184a032, + (q31_t)0x138edbb1, (q31_t)0x8180c6a9, (q31_t)0x137604e2, (q31_t)0x817cf201, (q31_t)0x135d2d53, (q31_t)0x8179223a, (q31_t)0x13445505, (q31_t)0x81755754, + (q31_t)0x132b7bf9, (q31_t)0x8171914e, (q31_t)0x1312a230, (q31_t)0x816dd02a, (q31_t)0x12f9c7aa, (q31_t)0x816a13e6, (q31_t)0x12e0ec6a, (q31_t)0x81665c84, + (q31_t)0x12c8106f, (q31_t)0x8162aa04, (q31_t)0x12af33ba, (q31_t)0x815efc65, (q31_t)0x1296564d, (q31_t)0x815b53a8, (q31_t)0x127d7829, (q31_t)0x8157afcd, + (q31_t)0x1264994e, (q31_t)0x815410d4, (q31_t)0x124bb9be, (q31_t)0x815076bd, (q31_t)0x1232d979, (q31_t)0x814ce188, (q31_t)0x1219f880, (q31_t)0x81495136, + (q31_t)0x120116d5, (q31_t)0x8145c5c7, (q31_t)0x11e83478, (q31_t)0x81423f3a, (q31_t)0x11cf516a, (q31_t)0x813ebd90, (q31_t)0x11b66dad, (q31_t)0x813b40ca, + (q31_t)0x119d8941, (q31_t)0x8137c8e6, (q31_t)0x1184a427, (q31_t)0x813455e6, (q31_t)0x116bbe60, (q31_t)0x8130e7c9, (q31_t)0x1152d7ed, (q31_t)0x812d7e8f, + (q31_t)0x1139f0cf, (q31_t)0x812a1a3a, (q31_t)0x11210907, (q31_t)0x8126bac8, (q31_t)0x11082096, (q31_t)0x8123603a, (q31_t)0x10ef377d, (q31_t)0x81200a90, + (q31_t)0x10d64dbd, (q31_t)0x811cb9ca, (q31_t)0x10bd6356, (q31_t)0x81196de9, (q31_t)0x10a4784b, (q31_t)0x811626ec, (q31_t)0x108b8c9b, (q31_t)0x8112e4d4, + (q31_t)0x1072a048, (q31_t)0x810fa7a0, (q31_t)0x1059b352, (q31_t)0x810c6f52, (q31_t)0x1040c5bb, (q31_t)0x81093be8, (q31_t)0x1027d784, (q31_t)0x81060d63, + (q31_t)0x100ee8ad, (q31_t)0x8102e3c4, (q31_t)0xff5f938, (q31_t)0x80ffbf0a, (q31_t)0xfdd0926, (q31_t)0x80fc9f35, (q31_t)0xfc41876, (q31_t)0x80f98446, + (q31_t)0xfab272b, (q31_t)0x80f66e3c, (q31_t)0xf923546, (q31_t)0x80f35d19, (q31_t)0xf7942c7, (q31_t)0x80f050db, (q31_t)0xf604faf, (q31_t)0x80ed4984, + (q31_t)0xf475bff, (q31_t)0x80ea4712, (q31_t)0xf2e67b8, (q31_t)0x80e74987, (q31_t)0xf1572dc, (q31_t)0x80e450e2, (q31_t)0xefc7d6b, (q31_t)0x80e15d24, + (q31_t)0xee38766, (q31_t)0x80de6e4c, (q31_t)0xeca90ce, (q31_t)0x80db845b, (q31_t)0xeb199a4, (q31_t)0x80d89f51, (q31_t)0xe98a1e9, (q31_t)0x80d5bf2e, + (q31_t)0xe7fa99e, (q31_t)0x80d2e3f2, (q31_t)0xe66b0c3, (q31_t)0x80d00d9d, (q31_t)0xe4db75b, (q31_t)0x80cd3c2f, (q31_t)0xe34bd66, (q31_t)0x80ca6fa9, + (q31_t)0xe1bc2e4, (q31_t)0x80c7a80a, (q31_t)0xe02c7d7, (q31_t)0x80c4e553, (q31_t)0xde9cc40, (q31_t)0x80c22784, (q31_t)0xdd0d01f, (q31_t)0x80bf6e9c, + (q31_t)0xdb7d376, (q31_t)0x80bcba9d, (q31_t)0xd9ed646, (q31_t)0x80ba0b85, (q31_t)0xd85d88f, (q31_t)0x80b76156, (q31_t)0xd6cda53, (q31_t)0x80b4bc0e, + (q31_t)0xd53db92, (q31_t)0x80b21baf, (q31_t)0xd3adc4e, (q31_t)0x80af8039, (q31_t)0xd21dc87, (q31_t)0x80ace9ab, (q31_t)0xd08dc3f, (q31_t)0x80aa5806, + (q31_t)0xcefdb76, (q31_t)0x80a7cb49, (q31_t)0xcd6da2d, (q31_t)0x80a54376, (q31_t)0xcbdd865, (q31_t)0x80a2c08b, (q31_t)0xca4d620, (q31_t)0x80a04289, + (q31_t)0xc8bd35e, (q31_t)0x809dc971, (q31_t)0xc72d020, (q31_t)0x809b5541, (q31_t)0xc59cc68, (q31_t)0x8098e5fb, (q31_t)0xc40c835, (q31_t)0x80967b9f, + (q31_t)0xc27c389, (q31_t)0x8094162c, (q31_t)0xc0ebe66, (q31_t)0x8091b5a2, (q31_t)0xbf5b8cb, (q31_t)0x808f5a02, (q31_t)0xbdcb2bb, (q31_t)0x808d034c, + (q31_t)0xbc3ac35, (q31_t)0x808ab180, (q31_t)0xbaaa53b, (q31_t)0x8088649e, (q31_t)0xb919dcf, (q31_t)0x80861ca6, (q31_t)0xb7895f0, (q31_t)0x8083d998, + (q31_t)0xb5f8d9f, (q31_t)0x80819b74, (q31_t)0xb4684df, (q31_t)0x807f623b, (q31_t)0xb2d7baf, (q31_t)0x807d2dec, (q31_t)0xb147211, (q31_t)0x807afe87, + (q31_t)0xafb6805, (q31_t)0x8078d40d, (q31_t)0xae25d8d, (q31_t)0x8076ae7e, (q31_t)0xac952aa, (q31_t)0x80748dd9, (q31_t)0xab0475c, (q31_t)0x8072721f, + (q31_t)0xa973ba5, (q31_t)0x80705b50, (q31_t)0xa7e2f85, (q31_t)0x806e496c, (q31_t)0xa6522fe, (q31_t)0x806c3c74, (q31_t)0xa4c1610, (q31_t)0x806a3466, + (q31_t)0xa3308bd, (q31_t)0x80683143, (q31_t)0xa19fb04, (q31_t)0x8066330c, (q31_t)0xa00ece8, (q31_t)0x806439c0, (q31_t)0x9e7de6a, (q31_t)0x80624560, + (q31_t)0x9cecf89, (q31_t)0x806055eb, (q31_t)0x9b5c048, (q31_t)0x805e6b62, (q31_t)0x99cb0a7, (q31_t)0x805c85c4, (q31_t)0x983a0a7, (q31_t)0x805aa512, + (q31_t)0x96a9049, (q31_t)0x8058c94c, (q31_t)0x9517f8f, (q31_t)0x8056f272, (q31_t)0x9386e78, (q31_t)0x80552084, (q31_t)0x91f5d06, (q31_t)0x80535381, + (q31_t)0x9064b3a, (q31_t)0x80518b6b, (q31_t)0x8ed3916, (q31_t)0x804fc841, (q31_t)0x8d42699, (q31_t)0x804e0a04, (q31_t)0x8bb13c5, (q31_t)0x804c50b2, + (q31_t)0x8a2009a, (q31_t)0x804a9c4d, (q31_t)0x888ed1b, (q31_t)0x8048ecd5, (q31_t)0x86fd947, (q31_t)0x80474248, (q31_t)0x856c520, (q31_t)0x80459ca9, + (q31_t)0x83db0a7, (q31_t)0x8043fbf6, (q31_t)0x8249bdd, (q31_t)0x80426030, (q31_t)0x80b86c2, (q31_t)0x8040c956, (q31_t)0x7f27157, (q31_t)0x803f376a, + (q31_t)0x7d95b9e, (q31_t)0x803daa6a, (q31_t)0x7c04598, (q31_t)0x803c2257, (q31_t)0x7a72f45, (q31_t)0x803a9f31, (q31_t)0x78e18a7, (q31_t)0x803920f8, + (q31_t)0x77501be, (q31_t)0x8037a7ac, (q31_t)0x75bea8c, (q31_t)0x8036334e, (q31_t)0x742d311, (q31_t)0x8034c3dd, (q31_t)0x729bb4e, (q31_t)0x80335959, + (q31_t)0x710a345, (q31_t)0x8031f3c2, (q31_t)0x6f78af6, (q31_t)0x80309318, (q31_t)0x6de7262, (q31_t)0x802f375d, (q31_t)0x6c5598a, (q31_t)0x802de08e, + (q31_t)0x6ac406f, (q31_t)0x802c8ead, (q31_t)0x6932713, (q31_t)0x802b41ba, (q31_t)0x67a0d76, (q31_t)0x8029f9b4, (q31_t)0x660f398, (q31_t)0x8028b69c, + (q31_t)0x647d97c, (q31_t)0x80277872, (q31_t)0x62ebf22, (q31_t)0x80263f36, (q31_t)0x615a48b, (q31_t)0x80250ae7, (q31_t)0x5fc89b8, (q31_t)0x8023db86, + (q31_t)0x5e36ea9, (q31_t)0x8022b114, (q31_t)0x5ca5361, (q31_t)0x80218b8f, (q31_t)0x5b137df, (q31_t)0x80206af8, (q31_t)0x5981c26, (q31_t)0x801f4f4f, + (q31_t)0x57f0035, (q31_t)0x801e3895, (q31_t)0x565e40d, (q31_t)0x801d26c8, (q31_t)0x54cc7b1, (q31_t)0x801c19ea, (q31_t)0x533ab20, (q31_t)0x801b11fa, + (q31_t)0x51a8e5c, (q31_t)0x801a0ef8, (q31_t)0x5017165, (q31_t)0x801910e4, (q31_t)0x4e8543e, (q31_t)0x801817bf, (q31_t)0x4cf36e5, (q31_t)0x80172388, + (q31_t)0x4b6195d, (q31_t)0x80163440, (q31_t)0x49cfba7, (q31_t)0x801549e6, (q31_t)0x483ddc3, (q31_t)0x8014647b, (q31_t)0x46abfb3, (q31_t)0x801383fe, + (q31_t)0x451a177, (q31_t)0x8012a86f, (q31_t)0x4388310, (q31_t)0x8011d1d0, (q31_t)0x41f6480, (q31_t)0x8011001f, (q31_t)0x40645c7, (q31_t)0x8010335c, + (q31_t)0x3ed26e6, (q31_t)0x800f6b88, (q31_t)0x3d407df, (q31_t)0x800ea8a3, (q31_t)0x3bae8b2, (q31_t)0x800deaad, (q31_t)0x3a1c960, (q31_t)0x800d31a5, + (q31_t)0x388a9ea, (q31_t)0x800c7d8c, (q31_t)0x36f8a51, (q31_t)0x800bce63, (q31_t)0x3566a96, (q31_t)0x800b2427, (q31_t)0x33d4abb, (q31_t)0x800a7edb, + (q31_t)0x3242abf, (q31_t)0x8009de7e, (q31_t)0x30b0aa4, (q31_t)0x80094310, (q31_t)0x2f1ea6c, (q31_t)0x8008ac90, (q31_t)0x2d8ca16, (q31_t)0x80081b00, + (q31_t)0x2bfa9a4, (q31_t)0x80078e5e, (q31_t)0x2a68917, (q31_t)0x800706ac, (q31_t)0x28d6870, (q31_t)0x800683e8, (q31_t)0x27447b0, (q31_t)0x80060614, + (q31_t)0x25b26d7, (q31_t)0x80058d2f, (q31_t)0x24205e8, (q31_t)0x80051939, (q31_t)0x228e4e2, (q31_t)0x8004aa32, (q31_t)0x20fc3c6, (q31_t)0x8004401a, + (q31_t)0x1f6a297, (q31_t)0x8003daf1, (q31_t)0x1dd8154, (q31_t)0x80037ab7, (q31_t)0x1c45ffe, (q31_t)0x80031f6d, (q31_t)0x1ab3e97, (q31_t)0x8002c912, + (q31_t)0x1921d20, (q31_t)0x800277a6, (q31_t)0x178fb99, (q31_t)0x80022b29, (q31_t)0x15fda03, (q31_t)0x8001e39b, (q31_t)0x146b860, (q31_t)0x8001a0fd, + (q31_t)0x12d96b1, (q31_t)0x8001634e, (q31_t)0x11474f6, (q31_t)0x80012a8e, (q31_t)0x0fb5330, (q31_t)0x8000f6bd, (q31_t)0xe23160, (q31_t)0x8000c7dc, + (q31_t)0x0c90f88, (q31_t)0x80009dea, (q31_t)0x0afeda8, (q31_t)0x800078e7, (q31_t)0x096cbc1, (q31_t)0x800058d4, (q31_t)0x7da9d4, (q31_t)0x80003daf, + (q31_t)0x06487e3, (q31_t)0x8000277a, (q31_t)0x04b65ee, (q31_t)0x80001635, (q31_t)0x03243f5, (q31_t)0x800009df, (q31_t)0x1921fb, (q31_t)0x80000278 +}; + const q31_t cos_factorsQ31_2048[2048] = { + (q31_t)0x7fffff62, (q31_t)0x7ffffa73, (q31_t)0x7ffff094, (q31_t)0x7fffe1c6, (q31_t)0x7fffce09, (q31_t)0x7fffb55c, + (q31_t)0x7fff97c1, (q31_t)0x7fff7536, + (q31_t)0x7fff4dbb, (q31_t)0x7fff2151, (q31_t)0x7ffeeff8, (q31_t)0x7ffeb9b0, (q31_t)0x7ffe7e79, (q31_t)0x7ffe3e52, + (q31_t)0x7ffdf93c, (q31_t)0x7ffdaf37, + (q31_t)0x7ffd6042, (q31_t)0x7ffd0c5f, (q31_t)0x7ffcb38c, (q31_t)0x7ffc55ca, (q31_t)0x7ffbf319, (q31_t)0x7ffb8b78, + (q31_t)0x7ffb1ee9, (q31_t)0x7ffaad6a, + (q31_t)0x7ffa36fc, (q31_t)0x7ff9bba0, (q31_t)0x7ff93b54, (q31_t)0x7ff8b619, (q31_t)0x7ff82bef, (q31_t)0x7ff79cd6, + (q31_t)0x7ff708ce, (q31_t)0x7ff66fd7, + (q31_t)0x7ff5d1f1, (q31_t)0x7ff52f1d, (q31_t)0x7ff48759, (q31_t)0x7ff3daa6, (q31_t)0x7ff32905, (q31_t)0x7ff27275, + (q31_t)0x7ff1b6f6, (q31_t)0x7ff0f688, + (q31_t)0x7ff0312c, (q31_t)0x7fef66e1, (q31_t)0x7fee97a7, (q31_t)0x7fedc37e, (q31_t)0x7fecea67, (q31_t)0x7fec0c62, + (q31_t)0x7feb296d, (q31_t)0x7fea418b, + (q31_t)0x7fe954ba, (q31_t)0x7fe862fa, (q31_t)0x7fe76c4c, (q31_t)0x7fe670b0, (q31_t)0x7fe57025, (q31_t)0x7fe46aac, + (q31_t)0x7fe36045, (q31_t)0x7fe250ef, + (q31_t)0x7fe13cac, (q31_t)0x7fe0237a, (q31_t)0x7fdf055a, (q31_t)0x7fdde24d, (q31_t)0x7fdcba51, (q31_t)0x7fdb8d67, + (q31_t)0x7fda5b8f, (q31_t)0x7fd924ca, + (q31_t)0x7fd7e917, (q31_t)0x7fd6a875, (q31_t)0x7fd562e7, (q31_t)0x7fd4186a, (q31_t)0x7fd2c900, (q31_t)0x7fd174a8, + (q31_t)0x7fd01b63, (q31_t)0x7fcebd31, + (q31_t)0x7fcd5a11, (q31_t)0x7fcbf203, (q31_t)0x7fca8508, (q31_t)0x7fc91320, (q31_t)0x7fc79c4b, (q31_t)0x7fc62089, + (q31_t)0x7fc49fda, (q31_t)0x7fc31a3d, + (q31_t)0x7fc18fb4, (q31_t)0x7fc0003e, (q31_t)0x7fbe6bdb, (q31_t)0x7fbcd28b, (q31_t)0x7fbb344e, (q31_t)0x7fb99125, + (q31_t)0x7fb7e90f, (q31_t)0x7fb63c0d, + (q31_t)0x7fb48a1e, (q31_t)0x7fb2d343, (q31_t)0x7fb1177b, (q31_t)0x7faf56c7, (q31_t)0x7fad9127, (q31_t)0x7fabc69b, + (q31_t)0x7fa9f723, (q31_t)0x7fa822bf, + (q31_t)0x7fa6496e, (q31_t)0x7fa46b32, (q31_t)0x7fa2880b, (q31_t)0x7fa09ff7, (q31_t)0x7f9eb2f8, (q31_t)0x7f9cc10d, + (q31_t)0x7f9aca37, (q31_t)0x7f98ce76, + (q31_t)0x7f96cdc9, (q31_t)0x7f94c831, (q31_t)0x7f92bdad, (q31_t)0x7f90ae3f, (q31_t)0x7f8e99e6, (q31_t)0x7f8c80a1, + (q31_t)0x7f8a6272, (q31_t)0x7f883f58, + (q31_t)0x7f861753, (q31_t)0x7f83ea64, (q31_t)0x7f81b88a, (q31_t)0x7f7f81c6, (q31_t)0x7f7d4617, (q31_t)0x7f7b057e, + (q31_t)0x7f78bffb, (q31_t)0x7f76758e, + (q31_t)0x7f742637, (q31_t)0x7f71d1f6, (q31_t)0x7f6f78cb, (q31_t)0x7f6d1ab6, (q31_t)0x7f6ab7b8, (q31_t)0x7f684fd0, + (q31_t)0x7f65e2ff, (q31_t)0x7f637144, + (q31_t)0x7f60faa0, (q31_t)0x7f5e7f13, (q31_t)0x7f5bfe9d, (q31_t)0x7f59793e, (q31_t)0x7f56eef5, (q31_t)0x7f545fc5, + (q31_t)0x7f51cbab, (q31_t)0x7f4f32a9, + (q31_t)0x7f4c94be, (q31_t)0x7f49f1eb, (q31_t)0x7f474a30, (q31_t)0x7f449d8c, (q31_t)0x7f41ec01, (q31_t)0x7f3f358d, + (q31_t)0x7f3c7a31, (q31_t)0x7f39b9ee, + (q31_t)0x7f36f4c3, (q31_t)0x7f342ab1, (q31_t)0x7f315bb7, (q31_t)0x7f2e87d6, (q31_t)0x7f2baf0d, (q31_t)0x7f28d15d, + (q31_t)0x7f25eec7, (q31_t)0x7f230749, + (q31_t)0x7f201ae5, (q31_t)0x7f1d299a, (q31_t)0x7f1a3368, (q31_t)0x7f173850, (q31_t)0x7f143852, (q31_t)0x7f11336d, + (q31_t)0x7f0e29a3, (q31_t)0x7f0b1af2, + (q31_t)0x7f08075c, (q31_t)0x7f04eedf, (q31_t)0x7f01d17d, (q31_t)0x7efeaf36, (q31_t)0x7efb8809, (q31_t)0x7ef85bf7, + (q31_t)0x7ef52b00, (q31_t)0x7ef1f524, + (q31_t)0x7eeeba62, (q31_t)0x7eeb7abc, (q31_t)0x7ee83632, (q31_t)0x7ee4ecc3, (q31_t)0x7ee19e6f, (q31_t)0x7ede4b38, + (q31_t)0x7edaf31c, (q31_t)0x7ed7961c, + (q31_t)0x7ed43438, (q31_t)0x7ed0cd70, (q31_t)0x7ecd61c5, (q31_t)0x7ec9f137, (q31_t)0x7ec67bc5, (q31_t)0x7ec3016f, + (q31_t)0x7ebf8237, (q31_t)0x7ebbfe1c, + (q31_t)0x7eb8751e, (q31_t)0x7eb4e73d, (q31_t)0x7eb1547a, (q31_t)0x7eadbcd4, (q31_t)0x7eaa204c, (q31_t)0x7ea67ee2, + (q31_t)0x7ea2d896, (q31_t)0x7e9f2d68, + (q31_t)0x7e9b7d58, (q31_t)0x7e97c867, (q31_t)0x7e940e94, (q31_t)0x7e904fe0, (q31_t)0x7e8c8c4b, (q31_t)0x7e88c3d5, + (q31_t)0x7e84f67e, (q31_t)0x7e812447, + (q31_t)0x7e7d4d2f, (q31_t)0x7e797136, (q31_t)0x7e75905d, (q31_t)0x7e71aaa4, (q31_t)0x7e6dc00c, (q31_t)0x7e69d093, + (q31_t)0x7e65dc3b, (q31_t)0x7e61e303, + (q31_t)0x7e5de4ec, (q31_t)0x7e59e1f5, (q31_t)0x7e55da20, (q31_t)0x7e51cd6c, (q31_t)0x7e4dbbd9, (q31_t)0x7e49a567, + (q31_t)0x7e458a17, (q31_t)0x7e4169e9, + (q31_t)0x7e3d44dd, (q31_t)0x7e391af3, (q31_t)0x7e34ec2b, (q31_t)0x7e30b885, (q31_t)0x7e2c8002, (q31_t)0x7e2842a2, + (q31_t)0x7e240064, (q31_t)0x7e1fb94a, + (q31_t)0x7e1b6d53, (q31_t)0x7e171c7f, (q31_t)0x7e12c6ce, (q31_t)0x7e0e6c42, (q31_t)0x7e0a0cd9, (q31_t)0x7e05a894, + (q31_t)0x7e013f74, (q31_t)0x7dfcd178, + (q31_t)0x7df85ea0, (q31_t)0x7df3e6ee, (q31_t)0x7def6a60, (q31_t)0x7deae8f7, (q31_t)0x7de662b3, (q31_t)0x7de1d795, + (q31_t)0x7ddd479d, (q31_t)0x7dd8b2ca, + (q31_t)0x7dd4191d, (q31_t)0x7dcf7a96, (q31_t)0x7dcad736, (q31_t)0x7dc62efc, (q31_t)0x7dc181e8, (q31_t)0x7dbccffc, + (q31_t)0x7db81936, (q31_t)0x7db35d98, + (q31_t)0x7dae9d21, (q31_t)0x7da9d7d2, (q31_t)0x7da50dab, (q31_t)0x7da03eab, (q31_t)0x7d9b6ad3, (q31_t)0x7d969224, + (q31_t)0x7d91b49e, (q31_t)0x7d8cd240, + (q31_t)0x7d87eb0a, (q31_t)0x7d82fefe, (q31_t)0x7d7e0e1c, (q31_t)0x7d791862, (q31_t)0x7d741dd2, (q31_t)0x7d6f1e6c, + (q31_t)0x7d6a1a31, (q31_t)0x7d65111f, + (q31_t)0x7d600338, (q31_t)0x7d5af07b, (q31_t)0x7d55d8e9, (q31_t)0x7d50bc82, (q31_t)0x7d4b9b46, (q31_t)0x7d467536, + (q31_t)0x7d414a51, (q31_t)0x7d3c1a98, + (q31_t)0x7d36e60b, (q31_t)0x7d31acaa, (q31_t)0x7d2c6e76, (q31_t)0x7d272b6e, (q31_t)0x7d21e393, (q31_t)0x7d1c96e5, + (q31_t)0x7d174564, (q31_t)0x7d11ef11, + (q31_t)0x7d0c93eb, (q31_t)0x7d0733f3, (q31_t)0x7d01cf29, (q31_t)0x7cfc658d, (q31_t)0x7cf6f720, (q31_t)0x7cf183e1, + (q31_t)0x7cec0bd1, (q31_t)0x7ce68ef0, + (q31_t)0x7ce10d3f, (q31_t)0x7cdb86bd, (q31_t)0x7cd5fb6a, (q31_t)0x7cd06b48, (q31_t)0x7ccad656, (q31_t)0x7cc53c94, + (q31_t)0x7cbf9e03, (q31_t)0x7cb9faa2, + (q31_t)0x7cb45272, (q31_t)0x7caea574, (q31_t)0x7ca8f3a7, (q31_t)0x7ca33d0c, (q31_t)0x7c9d81a3, (q31_t)0x7c97c16b, + (q31_t)0x7c91fc66, (q31_t)0x7c8c3294, + (q31_t)0x7c8663f4, (q31_t)0x7c809088, (q31_t)0x7c7ab84e, (q31_t)0x7c74db48, (q31_t)0x7c6ef976, (q31_t)0x7c6912d7, + (q31_t)0x7c63276d, (q31_t)0x7c5d3737, + (q31_t)0x7c574236, (q31_t)0x7c514869, (q31_t)0x7c4b49d2, (q31_t)0x7c45466f, (q31_t)0x7c3f3e42, (q31_t)0x7c39314b, + (q31_t)0x7c331f8a, (q31_t)0x7c2d08ff, + (q31_t)0x7c26edab, (q31_t)0x7c20cd8d, (q31_t)0x7c1aa8a6, (q31_t)0x7c147ef6, (q31_t)0x7c0e507e, (q31_t)0x7c081d3d, + (q31_t)0x7c01e534, (q31_t)0x7bfba863, + (q31_t)0x7bf566cb, (q31_t)0x7bef206b, (q31_t)0x7be8d544, (q31_t)0x7be28556, (q31_t)0x7bdc30a1, (q31_t)0x7bd5d726, + (q31_t)0x7bcf78e5, (q31_t)0x7bc915dd, + (q31_t)0x7bc2ae10, (q31_t)0x7bbc417e, (q31_t)0x7bb5d026, (q31_t)0x7baf5a09, (q31_t)0x7ba8df28, (q31_t)0x7ba25f82, + (q31_t)0x7b9bdb18, (q31_t)0x7b9551ea, + (q31_t)0x7b8ec3f8, (q31_t)0x7b883143, (q31_t)0x7b8199ca, (q31_t)0x7b7afd8f, (q31_t)0x7b745c91, (q31_t)0x7b6db6d0, + (q31_t)0x7b670c4d, (q31_t)0x7b605d09, + (q31_t)0x7b59a902, (q31_t)0x7b52f03a, (q31_t)0x7b4c32b1, (q31_t)0x7b457068, (q31_t)0x7b3ea95d, (q31_t)0x7b37dd92, + (q31_t)0x7b310d07, (q31_t)0x7b2a37bc, + (q31_t)0x7b235db2, (q31_t)0x7b1c7ee8, (q31_t)0x7b159b5f, (q31_t)0x7b0eb318, (q31_t)0x7b07c612, (q31_t)0x7b00d44d, + (q31_t)0x7af9ddcb, (q31_t)0x7af2e28b, + (q31_t)0x7aebe28d, (q31_t)0x7ae4ddd2, (q31_t)0x7addd45b, (q31_t)0x7ad6c626, (q31_t)0x7acfb336, (q31_t)0x7ac89b89, + (q31_t)0x7ac17f20, (q31_t)0x7aba5dfc, + (q31_t)0x7ab3381d, (q31_t)0x7aac0d82, (q31_t)0x7aa4de2d, (q31_t)0x7a9daa1d, (q31_t)0x7a967153, (q31_t)0x7a8f33d0, + (q31_t)0x7a87f192, (q31_t)0x7a80aa9c, + (q31_t)0x7a795eec, (q31_t)0x7a720e84, (q31_t)0x7a6ab963, (q31_t)0x7a635f8a, (q31_t)0x7a5c00f9, (q31_t)0x7a549db0, + (q31_t)0x7a4d35b0, (q31_t)0x7a45c8f9, + (q31_t)0x7a3e578b, (q31_t)0x7a36e166, (q31_t)0x7a2f668c, (q31_t)0x7a27e6fb, (q31_t)0x7a2062b5, (q31_t)0x7a18d9b9, + (q31_t)0x7a114c09, (q31_t)0x7a09b9a4, + (q31_t)0x7a02228a, (q31_t)0x79fa86bc, (q31_t)0x79f2e63a, (q31_t)0x79eb4105, (q31_t)0x79e3971c, (q31_t)0x79dbe880, + (q31_t)0x79d43532, (q31_t)0x79cc7d31, + (q31_t)0x79c4c07e, (q31_t)0x79bcff19, (q31_t)0x79b53903, (q31_t)0x79ad6e3c, (q31_t)0x79a59ec3, (q31_t)0x799dca9a, + (q31_t)0x7995f1c1, (q31_t)0x798e1438, + (q31_t)0x798631ff, (q31_t)0x797e4b16, (q31_t)0x79765f7f, (q31_t)0x796e6f39, (q31_t)0x79667a44, (q31_t)0x795e80a1, + (q31_t)0x79568250, (q31_t)0x794e7f52, + (q31_t)0x794677a6, (q31_t)0x793e6b4e, (q31_t)0x79365a49, (q31_t)0x792e4497, (q31_t)0x79262a3a, (q31_t)0x791e0b31, + (q31_t)0x7915e77c, (q31_t)0x790dbf1d, + (q31_t)0x79059212, (q31_t)0x78fd605d, (q31_t)0x78f529fe, (q31_t)0x78eceef6, (q31_t)0x78e4af44, (q31_t)0x78dc6ae8, + (q31_t)0x78d421e4, (q31_t)0x78cbd437, + (q31_t)0x78c381e2, (q31_t)0x78bb2ae5, (q31_t)0x78b2cf41, (q31_t)0x78aa6ef5, (q31_t)0x78a20a03, (q31_t)0x7899a06a, + (q31_t)0x7891322a, (q31_t)0x7888bf45, + (q31_t)0x788047ba, (q31_t)0x7877cb89, (q31_t)0x786f4ab4, (q31_t)0x7866c53a, (q31_t)0x785e3b1c, (q31_t)0x7855ac5a, + (q31_t)0x784d18f4, (q31_t)0x784480ea, + (q31_t)0x783be43e, (q31_t)0x783342ef, (q31_t)0x782a9cfe, (q31_t)0x7821f26b, (q31_t)0x78194336, (q31_t)0x78108f60, + (q31_t)0x7807d6e9, (q31_t)0x77ff19d1, + (q31_t)0x77f65819, (q31_t)0x77ed91c0, (q31_t)0x77e4c6c9, (q31_t)0x77dbf732, (q31_t)0x77d322fc, (q31_t)0x77ca4a27, + (q31_t)0x77c16cb4, (q31_t)0x77b88aa3, + (q31_t)0x77afa3f5, (q31_t)0x77a6b8a9, (q31_t)0x779dc8c0, (q31_t)0x7794d43b, (q31_t)0x778bdb19, (q31_t)0x7782dd5c, + (q31_t)0x7779db03, (q31_t)0x7770d40f, + (q31_t)0x7767c880, (q31_t)0x775eb857, (q31_t)0x7755a394, (q31_t)0x774c8a36, (q31_t)0x77436c40, (q31_t)0x773a49b0, + (q31_t)0x77312287, (q31_t)0x7727f6c6, + (q31_t)0x771ec66e, (q31_t)0x7715917d, (q31_t)0x770c57f5, (q31_t)0x770319d6, (q31_t)0x76f9d721, (q31_t)0x76f08fd5, + (q31_t)0x76e743f4, (q31_t)0x76ddf37c, + (q31_t)0x76d49e70, (q31_t)0x76cb44cf, (q31_t)0x76c1e699, (q31_t)0x76b883d0, (q31_t)0x76af1c72, (q31_t)0x76a5b082, + (q31_t)0x769c3ffe, (q31_t)0x7692cae8, + (q31_t)0x7689513f, (q31_t)0x767fd304, (q31_t)0x76765038, (q31_t)0x766cc8db, (q31_t)0x76633ced, (q31_t)0x7659ac6f, + (q31_t)0x76501760, (q31_t)0x76467dc2, + (q31_t)0x763cdf94, (q31_t)0x76333cd8, (q31_t)0x7629958c, (q31_t)0x761fe9b3, (q31_t)0x7616394c, (q31_t)0x760c8457, + (q31_t)0x7602cad5, (q31_t)0x75f90cc7, + (q31_t)0x75ef4a2c, (q31_t)0x75e58305, (q31_t)0x75dbb753, (q31_t)0x75d1e715, (q31_t)0x75c8124d, (q31_t)0x75be38fa, + (q31_t)0x75b45b1d, (q31_t)0x75aa78b6, + (q31_t)0x75a091c6, (q31_t)0x7596a64d, (q31_t)0x758cb64c, (q31_t)0x7582c1c2, (q31_t)0x7578c8b0, (q31_t)0x756ecb18, + (q31_t)0x7564c8f8, (q31_t)0x755ac251, + (q31_t)0x7550b725, (q31_t)0x7546a772, (q31_t)0x753c933a, (q31_t)0x75327a7d, (q31_t)0x75285d3b, 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(q31_t)0x169bb4b7, (q31_t)0x1682f774, (q31_t)0x166a3953, (q31_t)0x16517a55, (q31_t)0x1638ba7a, (q31_t)0x161ff9c4, + (q31_t)0x16073834, (q31_t)0x15ee75cb, + (q31_t)0x15d5b288, (q31_t)0x15bcee6f, (q31_t)0x15a4297f, (q31_t)0x158b63b9, (q31_t)0x15729d1f, (q31_t)0x1559d5b1, + (q31_t)0x15410d70, (q31_t)0x1528445d, + (q31_t)0x150f7a7a, (q31_t)0x14f6afc7, (q31_t)0x14dde445, (q31_t)0x14c517f4, (q31_t)0x14ac4ad7, (q31_t)0x14937cee, + (q31_t)0x147aae3a, (q31_t)0x1461debc, + (q31_t)0x14490e74, (q31_t)0x14303d65, (q31_t)0x14176b8e, (q31_t)0x13fe98f1, (q31_t)0x13e5c58e, (q31_t)0x13ccf167, + (q31_t)0x13b41c7d, (q31_t)0x139b46d0, + (q31_t)0x13827062, (q31_t)0x13699933, (q31_t)0x1350c144, (q31_t)0x1337e897, (q31_t)0x131f0f2c, (q31_t)0x13063505, + (q31_t)0x12ed5a21, (q31_t)0x12d47e83, + (q31_t)0x12bba22b, (q31_t)0x12a2c51b, (q31_t)0x1289e752, (q31_t)0x127108d2, (q31_t)0x1258299c, (q31_t)0x123f49b2, + (q31_t)0x12266913, (q31_t)0x120d87c1, + (q31_t)0x11f4a5bd, (q31_t)0x11dbc307, (q31_t)0x11c2dfa2, (q31_t)0x11a9fb8d, (q31_t)0x119116c9, (q31_t)0x11783159, + (q31_t)0x115f4b3c, (q31_t)0x11466473, + (q31_t)0x112d7d00, (q31_t)0x111494e4, (q31_t)0x10fbac1e, (q31_t)0x10e2c2b2, (q31_t)0x10c9d89e, (q31_t)0x10b0ede5, + (q31_t)0x10980287, (q31_t)0x107f1686, + (q31_t)0x106629e1, (q31_t)0x104d3c9b, (q31_t)0x10344eb4, (q31_t)0x101b602d, (q31_t)0x10027107, (q31_t)0xfe98143, + (q31_t)0xfd090e1, (q31_t)0xfb79fe4, + (q31_t)0xf9eae4c, (q31_t)0xf85bc19, (q31_t)0xf6cc94e, (q31_t)0xf53d5ea, (q31_t)0xf3ae1ee, (q31_t)0xf21ed5d, (q31_t)0xf08f836, + (q31_t)0xef0027b, + (q31_t)0xed70c2c, (q31_t)0xebe154b, (q31_t)0xea51dd8, (q31_t)0xe8c25d5, (q31_t)0xe732d42, (q31_t)0xe5a3421, (q31_t)0xe413a72, + (q31_t)0xe284036, + (q31_t)0xe0f456f, (q31_t)0xdf64a1c, (q31_t)0xddd4e40, (q31_t)0xdc451dc, (q31_t)0xdab54ef, (q31_t)0xd92577b, (q31_t)0xd795982, + (q31_t)0xd605b03, + (q31_t)0xd475c00, (q31_t)0xd2e5c7b, (q31_t)0xd155c73, (q31_t)0xcfc5bea, (q31_t)0xce35ae1, (q31_t)0xcca5959, (q31_t)0xcb15752, + (q31_t)0xc9854cf, + (q31_t)0xc7f51cf, (q31_t)0xc664e53, (q31_t)0xc4d4a5d, (q31_t)0xc3445ee, (q31_t)0xc1b4107, (q31_t)0xc023ba7, (q31_t)0xbe935d2, + (q31_t)0xbd02f87, + (q31_t)0xbb728c7, (q31_t)0xb9e2193, (q31_t)0xb8519ed, (q31_t)0xb6c11d5, (q31_t)0xb53094d, (q31_t)0xb3a0055, (q31_t)0xb20f6ee, + (q31_t)0xb07ed19, + (q31_t)0xaeee2d7, (q31_t)0xad5d829, (q31_t)0xabccd11, (q31_t)0xaa3c18e, (q31_t)0xa8ab5a2, (q31_t)0xa71a94f, (q31_t)0xa589c94, + (q31_t)0xa3f8f73, + (q31_t)0xa2681ed, (q31_t)0xa0d7403, (q31_t)0x9f465b5, (q31_t)0x9db5706, (q31_t)0x9c247f5, (q31_t)0x9a93884, (q31_t)0x99028b3, + (q31_t)0x9771884, + (q31_t)0x95e07f8, (q31_t)0x944f70f, (q31_t)0x92be5ca, (q31_t)0x912d42c, (q31_t)0x8f9c233, (q31_t)0x8e0afe2, (q31_t)0x8c79d3a, + (q31_t)0x8ae8a3a, + (q31_t)0x89576e5, (q31_t)0x87c633c, (q31_t)0x8634f3e, (q31_t)0x84a3aee, (q31_t)0x831264c, (q31_t)0x8181159, (q31_t)0x7fefc16, + (q31_t)0x7e5e685, + (q31_t)0x7ccd0a5, (q31_t)0x7b3ba78, (q31_t)0x79aa400, (q31_t)0x7818d3c, (q31_t)0x768762e, (q31_t)0x74f5ed7, (q31_t)0x7364738, + (q31_t)0x71d2f52, + (q31_t)0x7041726, (q31_t)0x6eafeb4, (q31_t)0x6d1e5fe, (q31_t)0x6b8cd05, (q31_t)0x69fb3c9, (q31_t)0x6869a4c, (q31_t)0x66d808f, + (q31_t)0x6546692, + (q31_t)0x63b4c57, (q31_t)0x62231de, (q31_t)0x6091729, (q31_t)0x5effc38, (q31_t)0x5d6e10c, (q31_t)0x5bdc5a7, (q31_t)0x5a4aa09, + (q31_t)0x58b8e34, + (q31_t)0x5727228, (q31_t)0x55955e6, (q31_t)0x540396f, (q31_t)0x5271cc4, (q31_t)0x50dffe7, (q31_t)0x4f4e2d8, (q31_t)0x4dbc597, + (q31_t)0x4c2a827, + (q31_t)0x4a98a88, (q31_t)0x4906cbb, (q31_t)0x4774ec1, (q31_t)0x45e309a, (q31_t)0x4451249, (q31_t)0x42bf3cd, (q31_t)0x412d528, + (q31_t)0x3f9b65b, + (q31_t)0x3e09767, (q31_t)0x3c7784d, (q31_t)0x3ae590d, (q31_t)0x39539a9, (q31_t)0x37c1a22, (q31_t)0x362fa78, (q31_t)0x349daac, + (q31_t)0x330bac1, + (q31_t)0x3179ab5, (q31_t)0x2fe7a8c, (q31_t)0x2e55a44, (q31_t)0x2cc39e1, (q31_t)0x2b31961, (q31_t)0x299f8c7, (q31_t)0x280d813, + (q31_t)0x267b747, + (q31_t)0x24e9662, (q31_t)0x2357567, (q31_t)0x21c5457, (q31_t)0x2033331, (q31_t)0x1ea11f7, (q31_t)0x1d0f0ab, (q31_t)0x1b7cf4d, + (q31_t)0x19eaddd, + (q31_t)0x1858c5e, (q31_t)0x16c6ad0, (q31_t)0x1534934, (q31_t)0x13a278a, (q31_t)0x12105d5, (q31_t)0x107e414, (q31_t)0xeec249, + (q31_t)0xd5a075, + (q31_t)0xbc7e99, (q31_t)0xa35cb5, (q31_t)0x8a3acb, (q31_t)0x7118dc, (q31_t)0x57f6e9, (q31_t)0x3ed4f2, (q31_t)0x25b2f8, + (q31_t)0xc90fe +}; + #endif + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_DCT4_Q31_8192) + const q31_t WeightsQ31_8192[16384] = { + (q31_t)0x7fffffff, (q31_t)0x00000000, (q31_t)0x7fffffd9, (q31_t)0xfff9b781, (q31_t)0x7fffff62, (q31_t)0xfff36f02, (q31_t)0x7ffffe9d, (q31_t)0xffed2684, + (q31_t)0x7ffffd88, (q31_t)0xffe6de05, (q31_t)0x7ffffc25, (q31_t)0xffe09586, (q31_t)0x7ffffa73, (q31_t)0xffda4d08, (q31_t)0x7ffff872, (q31_t)0xffd40489, + (q31_t)0x7ffff621, (q31_t)0xffcdbc0b, (q31_t)0x7ffff382, (q31_t)0xffc7738c, (q31_t)0x7ffff094, (q31_t)0xffc12b0e, (q31_t)0x7fffed57, (q31_t)0xffbae290, + (q31_t)0x7fffe9cb, (q31_t)0xffb49a12, (q31_t)0x7fffe5f0, (q31_t)0xffae5195, (q31_t)0x7fffe1c6, (q31_t)0xffa80917, (q31_t)0x7fffdd4d, (q31_t)0xffa1c09a, + (q31_t)0x7fffd886, (q31_t)0xff9b781d, (q31_t)0x7fffd36f, (q31_t)0xff952fa0, (q31_t)0x7fffce09, (q31_t)0xff8ee724, (q31_t)0x7fffc854, (q31_t)0xff889ea7, + (q31_t)0x7fffc251, (q31_t)0xff82562c, (q31_t)0x7fffbbfe, (q31_t)0xff7c0db0, (q31_t)0x7fffb55c, (q31_t)0xff75c535, (q31_t)0x7fffae6c, (q31_t)0xff6f7cba, + (q31_t)0x7fffa72c, (q31_t)0xff69343f, (q31_t)0x7fff9f9e, (q31_t)0xff62ebc5, (q31_t)0x7fff97c1, (q31_t)0xff5ca34b, (q31_t)0x7fff8f94, (q31_t)0xff565ad1, + (q31_t)0x7fff8719, (q31_t)0xff501258, (q31_t)0x7fff7e4f, (q31_t)0xff49c9df, (q31_t)0x7fff7536, (q31_t)0xff438167, (q31_t)0x7fff6bcd, (q31_t)0xff3d38ef, + (q31_t)0x7fff6216, (q31_t)0xff36f078, (q31_t)0x7fff5810, (q31_t)0xff30a801, (q31_t)0x7fff4dbb, (q31_t)0xff2a5f8b, (q31_t)0x7fff4317, (q31_t)0xff241715, + (q31_t)0x7fff3824, (q31_t)0xff1dcea0, (q31_t)0x7fff2ce2, (q31_t)0xff17862b, (q31_t)0x7fff2151, (q31_t)0xff113db7, (q31_t)0x7fff1572, (q31_t)0xff0af543, + (q31_t)0x7fff0943, (q31_t)0xff04acd0, (q31_t)0x7ffefcc5, (q31_t)0xfefe645e, (q31_t)0x7ffeeff8, (q31_t)0xfef81bec, (q31_t)0x7ffee2dd, (q31_t)0xfef1d37b, + (q31_t)0x7ffed572, (q31_t)0xfeeb8b0a, (q31_t)0x7ffec7b9, (q31_t)0xfee5429a, (q31_t)0x7ffeb9b0, (q31_t)0xfedefa2b, (q31_t)0x7ffeab59, (q31_t)0xfed8b1bd, + (q31_t)0x7ffe9cb2, (q31_t)0xfed2694f, (q31_t)0x7ffe8dbd, (q31_t)0xfecc20e2, (q31_t)0x7ffe7e79, (q31_t)0xfec5d876, (q31_t)0x7ffe6ee5, (q31_t)0xfebf900a, + (q31_t)0x7ffe5f03, (q31_t)0xfeb947a0, (q31_t)0x7ffe4ed2, (q31_t)0xfeb2ff36, (q31_t)0x7ffe3e52, (q31_t)0xfeacb6cc, (q31_t)0x7ffe2d83, (q31_t)0xfea66e64, + (q31_t)0x7ffe1c65, (q31_t)0xfea025fd, (q31_t)0x7ffe0af8, (q31_t)0xfe99dd96, (q31_t)0x7ffdf93c, (q31_t)0xfe939530, (q31_t)0x7ffde731, (q31_t)0xfe8d4ccb, + (q31_t)0x7ffdd4d7, (q31_t)0xfe870467, (q31_t)0x7ffdc22e, (q31_t)0xfe80bc04, (q31_t)0x7ffdaf37, (q31_t)0xfe7a73a2, (q31_t)0x7ffd9bf0, (q31_t)0xfe742b41, + (q31_t)0x7ffd885a, (q31_t)0xfe6de2e0, (q31_t)0x7ffd7476, (q31_t)0xfe679a81, (q31_t)0x7ffd6042, (q31_t)0xfe615223, (q31_t)0x7ffd4bc0, (q31_t)0xfe5b09c5, + (q31_t)0x7ffd36ee, (q31_t)0xfe54c169, (q31_t)0x7ffd21ce, (q31_t)0xfe4e790d, (q31_t)0x7ffd0c5f, (q31_t)0xfe4830b3, (q31_t)0x7ffcf6a0, (q31_t)0xfe41e85a, + (q31_t)0x7ffce093, (q31_t)0xfe3ba002, (q31_t)0x7ffcca37, (q31_t)0xfe3557ab, (q31_t)0x7ffcb38c, (q31_t)0xfe2f0f55, (q31_t)0x7ffc9c92, (q31_t)0xfe28c700, + (q31_t)0x7ffc8549, (q31_t)0xfe227eac, (q31_t)0x7ffc6db1, (q31_t)0xfe1c365a, (q31_t)0x7ffc55ca, (q31_t)0xfe15ee09, (q31_t)0x7ffc3d94, (q31_t)0xfe0fa5b8, + (q31_t)0x7ffc250f, (q31_t)0xfe095d69, (q31_t)0x7ffc0c3b, (q31_t)0xfe03151c, (q31_t)0x7ffbf319, (q31_t)0xfdfccccf, (q31_t)0x7ffbd9a7, (q31_t)0xfdf68484, + (q31_t)0x7ffbbfe6, (q31_t)0xfdf03c3a, (q31_t)0x7ffba5d7, (q31_t)0xfde9f3f1, (q31_t)0x7ffb8b78, (q31_t)0xfde3aba9, (q31_t)0x7ffb70cb, (q31_t)0xfddd6363, + (q31_t)0x7ffb55ce, (q31_t)0xfdd71b1e, (q31_t)0x7ffb3a83, (q31_t)0xfdd0d2db, (q31_t)0x7ffb1ee9, (q31_t)0xfdca8a99, (q31_t)0x7ffb0300, (q31_t)0xfdc44258, + (q31_t)0x7ffae6c7, (q31_t)0xfdbdfa18, (q31_t)0x7ffaca40, (q31_t)0xfdb7b1da, (q31_t)0x7ffaad6a, (q31_t)0xfdb1699e, (q31_t)0x7ffa9045, (q31_t)0xfdab2162, + (q31_t)0x7ffa72d1, (q31_t)0xfda4d929, (q31_t)0x7ffa550e, (q31_t)0xfd9e90f0, (q31_t)0x7ffa36fc, (q31_t)0xfd9848b9, (q31_t)0x7ffa189c, (q31_t)0xfd920084, + (q31_t)0x7ff9f9ec, (q31_t)0xfd8bb850, (q31_t)0x7ff9daed, (q31_t)0xfd85701e, (q31_t)0x7ff9bba0, (q31_t)0xfd7f27ed, (q31_t)0x7ff99c03, (q31_t)0xfd78dfbd, + (q31_t)0x7ff97c18, (q31_t)0xfd729790, (q31_t)0x7ff95bdd, (q31_t)0xfd6c4f64, (q31_t)0x7ff93b54, (q31_t)0xfd660739, (q31_t)0x7ff91a7b, (q31_t)0xfd5fbf10, + (q31_t)0x7ff8f954, (q31_t)0xfd5976e9, (q31_t)0x7ff8d7de, (q31_t)0xfd532ec3, (q31_t)0x7ff8b619, (q31_t)0xfd4ce69f, (q31_t)0x7ff89405, (q31_t)0xfd469e7c, + (q31_t)0x7ff871a2, (q31_t)0xfd40565c, (q31_t)0x7ff84ef0, (q31_t)0xfd3a0e3d, (q31_t)0x7ff82bef, (q31_t)0xfd33c61f, (q31_t)0x7ff8089f, (q31_t)0xfd2d7e04, + (q31_t)0x7ff7e500, (q31_t)0xfd2735ea, (q31_t)0x7ff7c113, (q31_t)0xfd20edd2, (q31_t)0x7ff79cd6, (q31_t)0xfd1aa5bc, (q31_t)0x7ff7784a, (q31_t)0xfd145da7, + (q31_t)0x7ff75370, (q31_t)0xfd0e1594, (q31_t)0x7ff72e46, (q31_t)0xfd07cd83, (q31_t)0x7ff708ce, (q31_t)0xfd018574, (q31_t)0x7ff6e307, (q31_t)0xfcfb3d67, + (q31_t)0x7ff6bcf0, (q31_t)0xfcf4f55c, (q31_t)0x7ff6968b, (q31_t)0xfceead52, (q31_t)0x7ff66fd7, (q31_t)0xfce8654b, (q31_t)0x7ff648d4, (q31_t)0xfce21d45, + (q31_t)0x7ff62182, (q31_t)0xfcdbd541, (q31_t)0x7ff5f9e1, (q31_t)0xfcd58d3f, (q31_t)0x7ff5d1f1, (q31_t)0xfccf453f, (q31_t)0x7ff5a9b2, (q31_t)0xfcc8fd41, + (q31_t)0x7ff58125, (q31_t)0xfcc2b545, (q31_t)0x7ff55848, (q31_t)0xfcbc6d4c, (q31_t)0x7ff52f1d, (q31_t)0xfcb62554, (q31_t)0x7ff505a2, (q31_t)0xfcafdd5e, + (q31_t)0x7ff4dbd9, (q31_t)0xfca9956a, (q31_t)0x7ff4b1c0, (q31_t)0xfca34d78, (q31_t)0x7ff48759, (q31_t)0xfc9d0588, (q31_t)0x7ff45ca3, (q31_t)0xfc96bd9b, + (q31_t)0x7ff4319d, (q31_t)0xfc9075af, (q31_t)0x7ff40649, (q31_t)0xfc8a2dc6, (q31_t)0x7ff3daa6, (q31_t)0xfc83e5de, (q31_t)0x7ff3aeb4, (q31_t)0xfc7d9df9, + (q31_t)0x7ff38274, (q31_t)0xfc775616, (q31_t)0x7ff355e4, (q31_t)0xfc710e36, (q31_t)0x7ff32905, (q31_t)0xfc6ac657, (q31_t)0x7ff2fbd7, (q31_t)0xfc647e7b, + (q31_t)0x7ff2ce5b, (q31_t)0xfc5e36a0, (q31_t)0x7ff2a08f, (q31_t)0xfc57eec9, (q31_t)0x7ff27275, (q31_t)0xfc51a6f3, (q31_t)0x7ff2440b, (q31_t)0xfc4b5f20, + (q31_t)0x7ff21553, (q31_t)0xfc45174e, (q31_t)0x7ff1e64c, (q31_t)0xfc3ecf80, (q31_t)0x7ff1b6f6, (q31_t)0xfc3887b3, (q31_t)0x7ff18751, (q31_t)0xfc323fe9, + (q31_t)0x7ff1575d, (q31_t)0xfc2bf821, (q31_t)0x7ff1271a, (q31_t)0xfc25b05c, (q31_t)0x7ff0f688, (q31_t)0xfc1f6899, (q31_t)0x7ff0c5a7, (q31_t)0xfc1920d8, + (q31_t)0x7ff09478, (q31_t)0xfc12d91a, (q31_t)0x7ff062f9, (q31_t)0xfc0c915e, (q31_t)0x7ff0312c, (q31_t)0xfc0649a5, (q31_t)0x7fefff0f, (q31_t)0xfc0001ee, + (q31_t)0x7fefcca4, (q31_t)0xfbf9ba39, (q31_t)0x7fef99ea, (q31_t)0xfbf37287, (q31_t)0x7fef66e1, (q31_t)0xfbed2ad8, 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(q31_t)0x4f4e2d8, (q31_t)0x801893b4, (q31_t)0x4ee9b8c, (q31_t)0x80185592, + (q31_t)0x4e8543e, (q31_t)0x801817bf, (q31_t)0x4e20cec, (q31_t)0x8017da3b, (q31_t)0x4dbc597, (q31_t)0x80179d06, (q31_t)0x4d57e40, (q31_t)0x80176020, + (q31_t)0x4cf36e5, (q31_t)0x80172388, (q31_t)0x4c8ef88, (q31_t)0x8016e740, (q31_t)0x4c2a827, (q31_t)0x8016ab46, (q31_t)0x4bc60c4, (q31_t)0x80166f9c, + (q31_t)0x4b6195d, (q31_t)0x80163440, (q31_t)0x4afd1f4, (q31_t)0x8015f933, (q31_t)0x4a98a88, (q31_t)0x8015be75, (q31_t)0x4a34319, (q31_t)0x80158406, + (q31_t)0x49cfba7, (q31_t)0x801549e6, (q31_t)0x496b432, (q31_t)0x80151015, (q31_t)0x4906cbb, (q31_t)0x8014d693, (q31_t)0x48a2540, (q31_t)0x80149d5f, + (q31_t)0x483ddc3, (q31_t)0x8014647b, (q31_t)0x47d9643, (q31_t)0x80142be5, (q31_t)0x4774ec1, (q31_t)0x8013f39e, (q31_t)0x471073b, (q31_t)0x8013bba7, + (q31_t)0x46abfb3, (q31_t)0x801383fe, (q31_t)0x4647828, (q31_t)0x80134ca4, (q31_t)0x45e309a, (q31_t)0x80131599, (q31_t)0x457e90a, (q31_t)0x8012dedd, + (q31_t)0x451a177, (q31_t)0x8012a86f, (q31_t)0x44b59e1, (q31_t)0x80127251, (q31_t)0x4451249, (q31_t)0x80123c82, (q31_t)0x43ecaae, (q31_t)0x80120701, + (q31_t)0x4388310, (q31_t)0x8011d1d0, (q31_t)0x4323b70, (q31_t)0x80119ced, (q31_t)0x42bf3cd, (q31_t)0x80116859, (q31_t)0x425ac28, (q31_t)0x80113414, + (q31_t)0x41f6480, (q31_t)0x8011001f, (q31_t)0x4191cd5, (q31_t)0x8010cc78, (q31_t)0x412d528, (q31_t)0x8010991f, (q31_t)0x40c8d79, (q31_t)0x80106616, + (q31_t)0x40645c7, (q31_t)0x8010335c, (q31_t)0x3fffe12, (q31_t)0x801000f1, (q31_t)0x3f9b65b, (q31_t)0x800fced4, (q31_t)0x3f36ea2, (q31_t)0x800f9d07, + (q31_t)0x3ed26e6, (q31_t)0x800f6b88, (q31_t)0x3e6df28, (q31_t)0x800f3a59, (q31_t)0x3e09767, (q31_t)0x800f0978, (q31_t)0x3da4fa4, (q31_t)0x800ed8e6, + (q31_t)0x3d407df, (q31_t)0x800ea8a3, (q31_t)0x3cdc017, (q31_t)0x800e78af, (q31_t)0x3c7784d, (q31_t)0x800e490a, (q31_t)0x3c13080, (q31_t)0x800e19b4, + (q31_t)0x3bae8b2, (q31_t)0x800deaad, (q31_t)0x3b4a0e0, (q31_t)0x800dbbf5, (q31_t)0x3ae590d, (q31_t)0x800d8d8b, (q31_t)0x3a81137, (q31_t)0x800d5f71, + (q31_t)0x3a1c960, (q31_t)0x800d31a5, (q31_t)0x39b8185, (q31_t)0x800d0429, (q31_t)0x39539a9, (q31_t)0x800cd6fb, (q31_t)0x38ef1ca, (q31_t)0x800caa1c, + (q31_t)0x388a9ea, (q31_t)0x800c7d8c, (q31_t)0x3826207, (q31_t)0x800c514c, (q31_t)0x37c1a22, (q31_t)0x800c255a, (q31_t)0x375d23a, (q31_t)0x800bf9b7, + (q31_t)0x36f8a51, (q31_t)0x800bce63, (q31_t)0x3694265, (q31_t)0x800ba35d, (q31_t)0x362fa78, (q31_t)0x800b78a7, (q31_t)0x35cb288, (q31_t)0x800b4e40, + (q31_t)0x3566a96, (q31_t)0x800b2427, (q31_t)0x35022a2, (q31_t)0x800afa5e, (q31_t)0x349daac, (q31_t)0x800ad0e3, (q31_t)0x34392b4, (q31_t)0x800aa7b8, + (q31_t)0x33d4abb, (q31_t)0x800a7edb, (q31_t)0x33702bf, (q31_t)0x800a564e, (q31_t)0x330bac1, (q31_t)0x800a2e0f, (q31_t)0x32a72c1, (q31_t)0x800a061f, + (q31_t)0x3242abf, (q31_t)0x8009de7e, (q31_t)0x31de2bb, (q31_t)0x8009b72c, (q31_t)0x3179ab5, (q31_t)0x80099029, (q31_t)0x31152ae, (q31_t)0x80096975, + (q31_t)0x30b0aa4, (q31_t)0x80094310, (q31_t)0x304c299, (q31_t)0x80091cf9, (q31_t)0x2fe7a8c, (q31_t)0x8008f732, (q31_t)0x2f8327d, (q31_t)0x8008d1ba, + (q31_t)0x2f1ea6c, (q31_t)0x8008ac90, (q31_t)0x2eba259, (q31_t)0x800887b6, (q31_t)0x2e55a44, (q31_t)0x8008632a, (q31_t)0x2df122e, (q31_t)0x80083eed, + (q31_t)0x2d8ca16, (q31_t)0x80081b00, (q31_t)0x2d281fc, (q31_t)0x8007f761, (q31_t)0x2cc39e1, (q31_t)0x8007d411, (q31_t)0x2c5f1c3, (q31_t)0x8007b110, + (q31_t)0x2bfa9a4, (q31_t)0x80078e5e, (q31_t)0x2b96184, (q31_t)0x80076bfb, (q31_t)0x2b31961, (q31_t)0x800749e7, (q31_t)0x2acd13d, (q31_t)0x80072822, + (q31_t)0x2a68917, (q31_t)0x800706ac, (q31_t)0x2a040f0, (q31_t)0x8006e585, (q31_t)0x299f8c7, (q31_t)0x8006c4ac, (q31_t)0x293b09c, (q31_t)0x8006a423, + (q31_t)0x28d6870, (q31_t)0x800683e8, (q31_t)0x2872043, (q31_t)0x800663fd, (q31_t)0x280d813, (q31_t)0x80064460, (q31_t)0x27a8fe2, (q31_t)0x80062513, + (q31_t)0x27447b0, (q31_t)0x80060614, (q31_t)0x26dff7c, (q31_t)0x8005e764, (q31_t)0x267b747, (q31_t)0x8005c904, (q31_t)0x2616f10, (q31_t)0x8005aaf2, + (q31_t)0x25b26d7, (q31_t)0x80058d2f, (q31_t)0x254de9e, (q31_t)0x80056fbb, (q31_t)0x24e9662, (q31_t)0x80055296, (q31_t)0x2484e26, (q31_t)0x800535c0, + (q31_t)0x24205e8, (q31_t)0x80051939, (q31_t)0x23bbda8, (q31_t)0x8004fd00, (q31_t)0x2357567, (q31_t)0x8004e117, (q31_t)0x22f2d25, (q31_t)0x8004c57d, + (q31_t)0x228e4e2, (q31_t)0x8004aa32, (q31_t)0x2229c9d, (q31_t)0x80048f35, (q31_t)0x21c5457, (q31_t)0x80047488, (q31_t)0x2160c0f, (q31_t)0x80045a29, + (q31_t)0x20fc3c6, (q31_t)0x8004401a, (q31_t)0x2097b7c, (q31_t)0x80042659, (q31_t)0x2033331, (q31_t)0x80040ce7, (q31_t)0x1fceae4, (q31_t)0x8003f3c5, + (q31_t)0x1f6a297, (q31_t)0x8003daf1, (q31_t)0x1f05a48, (q31_t)0x8003c26c, (q31_t)0x1ea11f7, (q31_t)0x8003aa36, (q31_t)0x1e3c9a6, (q31_t)0x8003924f, + (q31_t)0x1dd8154, (q31_t)0x80037ab7, (q31_t)0x1d73900, (q31_t)0x8003636e, (q31_t)0x1d0f0ab, (q31_t)0x80034c74, (q31_t)0x1caa855, (q31_t)0x800335c9, + (q31_t)0x1c45ffe, (q31_t)0x80031f6d, (q31_t)0x1be17a6, (q31_t)0x80030960, (q31_t)0x1b7cf4d, (q31_t)0x8002f3a1, (q31_t)0x1b186f3, (q31_t)0x8002de32, + (q31_t)0x1ab3e97, (q31_t)0x8002c912, (q31_t)0x1a4f63b, (q31_t)0x8002b440, (q31_t)0x19eaddd, (q31_t)0x80029fbe, (q31_t)0x198657f, (q31_t)0x80028b8a, + (q31_t)0x1921d20, (q31_t)0x800277a6, (q31_t)0x18bd4bf, (q31_t)0x80026410, (q31_t)0x1858c5e, (q31_t)0x800250c9, (q31_t)0x17f43fc, (q31_t)0x80023dd2, + (q31_t)0x178fb99, (q31_t)0x80022b29, (q31_t)0x172b335, (q31_t)0x800218cf, (q31_t)0x16c6ad0, (q31_t)0x800206c4, (q31_t)0x166226a, (q31_t)0x8001f508, + (q31_t)0x15fda03, (q31_t)0x8001e39b, (q31_t)0x159919c, (q31_t)0x8001d27d, (q31_t)0x1534934, (q31_t)0x8001c1ae, (q31_t)0x14d00ca, (q31_t)0x8001b12e, + (q31_t)0x146b860, (q31_t)0x8001a0fd, (q31_t)0x1406ff6, (q31_t)0x8001911b, (q31_t)0x13a278a, (q31_t)0x80018187, (q31_t)0x133df1e, (q31_t)0x80017243, + (q31_t)0x12d96b1, (q31_t)0x8001634e, (q31_t)0x1274e43, (q31_t)0x800154a7, (q31_t)0x12105d5, (q31_t)0x80014650, (q31_t)0x11abd66, (q31_t)0x80013847, + (q31_t)0x11474f6, (q31_t)0x80012a8e, (q31_t)0x10e2c85, (q31_t)0x80011d23, (q31_t)0x107e414, (q31_t)0x80011008, (q31_t)0x1019ba2, (q31_t)0x8001033b, + (q31_t)0x0fb5330, (q31_t)0x8000f6bd, (q31_t)0x0f50abd, (q31_t)0x8000ea8e, (q31_t)0x0eec249, (q31_t)0x8000deaf, (q31_t)0x0e879d5, (q31_t)0x8000d31e, + (q31_t)0x0e23160, (q31_t)0x8000c7dc, (q31_t)0x0dbe8eb, (q31_t)0x8000bce9, (q31_t)0x0d5a075, (q31_t)0x8000b245, (q31_t)0x0cf57ff, (q31_t)0x8000a7f0, + (q31_t)0x0c90f88, (q31_t)0x80009dea, (q31_t)0x0c2c711, (q31_t)0x80009433, (q31_t)0x0bc7e99, (q31_t)0x80008aca, (q31_t)0x0b63621, (q31_t)0x800081b1, + (q31_t)0x0afeda8, (q31_t)0x800078e7, (q31_t)0x0a9a52f, (q31_t)0x8000706c, (q31_t)0x0a35cb5, (q31_t)0x8000683f, (q31_t)0x09d143b, (q31_t)0x80006062, + (q31_t)0x096cbc1, (q31_t)0x800058d4, (q31_t)0x0908346, (q31_t)0x80005194, (q31_t)0x08a3acb, (q31_t)0x80004aa4, (q31_t)0x083f250, (q31_t)0x80004402, + (q31_t)0x07da9d4, (q31_t)0x80003daf, (q31_t)0x0776159, (q31_t)0x800037ac, (q31_t)0x07118dc, (q31_t)0x800031f7, (q31_t)0x06ad060, (q31_t)0x80002c91, + (q31_t)0x06487e3, (q31_t)0x8000277a, (q31_t)0x05e3f66, (q31_t)0x800022b3, (q31_t)0x057f6e9, (q31_t)0x80001e3a, (q31_t)0x051ae6b, (q31_t)0x80001a10, + (q31_t)0x04b65ee, (q31_t)0x80001635, (q31_t)0x0451d70, (q31_t)0x800012a9, (q31_t)0x03ed4f2, (q31_t)0x80000f6c, (q31_t)0x0388c74, (q31_t)0x80000c7e, + (q31_t)0x03243f5, (q31_t)0x800009df, (q31_t)0x02bfb77, (q31_t)0x8000078e, (q31_t)0x025b2f8, (q31_t)0x8000058d, (q31_t)0x01f6a7a, (q31_t)0x800003db, + (q31_t)0x01921fb, (q31_t)0x80000278, (q31_t)0x012d97c, (q31_t)0x80000163, (q31_t)0x00c90fe, (q31_t)0x8000009e, (q31_t)0x006487f, (q31_t)0x80000027 +}; + const q31_t cos_factorsQ31_8192[8192] = { + (q31_t)0x7ffffff6, (q31_t)0x7fffffa7, (q31_t)0x7fffff09, (q31_t)0x7ffffe1c, (q31_t)0x7ffffce1, (q31_t)0x7ffffb56, (q31_t)0x7ffff97c, (q31_t)0x7ffff753, + (q31_t)0x7ffff4dc, (q31_t)0x7ffff215, (q31_t)0x7fffef00, (q31_t)0x7fffeb9b, (q31_t)0x7fffe7e8, (q31_t)0x7fffe3e5, (q31_t)0x7fffdf94, (q31_t)0x7fffdaf3, + (q31_t)0x7fffd604, (q31_t)0x7fffd0c6, (q31_t)0x7fffcb39, (q31_t)0x7fffc55c, (q31_t)0x7fffbf31, (q31_t)0x7fffb8b7, (q31_t)0x7fffb1ee, (q31_t)0x7fffaad6, + (q31_t)0x7fffa36f, (q31_t)0x7fff9bb9, (q31_t)0x7fff93b4, (q31_t)0x7fff8b61, (q31_t)0x7fff82be, (q31_t)0x7fff79cc, (q31_t)0x7fff708b, (q31_t)0x7fff66fc, + (q31_t)0x7fff5d1d, (q31_t)0x7fff52ef, (q31_t)0x7fff4873, (q31_t)0x7fff3da8, (q31_t)0x7fff328d, (q31_t)0x7fff2724, (q31_t)0x7fff1b6b, (q31_t)0x7fff0f64, + (q31_t)0x7fff030e, (q31_t)0x7ffef669, (q31_t)0x7ffee975, (q31_t)0x7ffedc31, (q31_t)0x7ffece9f, (q31_t)0x7ffec0be, (q31_t)0x7ffeb28e, (q31_t)0x7ffea40f, + (q31_t)0x7ffe9542, (q31_t)0x7ffe8625, (q31_t)0x7ffe76b9, (q31_t)0x7ffe66fe, (q31_t)0x7ffe56f5, (q31_t)0x7ffe469c, (q31_t)0x7ffe35f4, (q31_t)0x7ffe24fe, + (q31_t)0x7ffe13b8, (q31_t)0x7ffe0224, (q31_t)0x7ffdf040, (q31_t)0x7ffdde0e, (q31_t)0x7ffdcb8d, (q31_t)0x7ffdb8bc, (q31_t)0x7ffda59d, (q31_t)0x7ffd922f, + (q31_t)0x7ffd7e72, (q31_t)0x7ffd6a66, (q31_t)0x7ffd560b, (q31_t)0x7ffd4161, (q31_t)0x7ffd2c68, (q31_t)0x7ffd1720, (q31_t)0x7ffd0189, (q31_t)0x7ffceba4, + (q31_t)0x7ffcd56f, (q31_t)0x7ffcbeeb, (q31_t)0x7ffca819, (q31_t)0x7ffc90f7, (q31_t)0x7ffc7987, (q31_t)0x7ffc61c7, (q31_t)0x7ffc49b9, (q31_t)0x7ffc315b, + (q31_t)0x7ffc18af, (q31_t)0x7ffbffb4, (q31_t)0x7ffbe66a, (q31_t)0x7ffbccd0, (q31_t)0x7ffbb2e8, (q31_t)0x7ffb98b1, (q31_t)0x7ffb7e2b, (q31_t)0x7ffb6356, + (q31_t)0x7ffb4833, (q31_t)0x7ffb2cc0, (q31_t)0x7ffb10fe, (q31_t)0x7ffaf4ed, (q31_t)0x7ffad88e, (q31_t)0x7ffabbdf, (q31_t)0x7ffa9ee2, (q31_t)0x7ffa8195, + (q31_t)0x7ffa63fa, (q31_t)0x7ffa460f, (q31_t)0x7ffa27d6, (q31_t)0x7ffa094e, (q31_t)0x7ff9ea76, (q31_t)0x7ff9cb50, (q31_t)0x7ff9abdb, (q31_t)0x7ff98c17, + (q31_t)0x7ff96c04, (q31_t)0x7ff94ba2, (q31_t)0x7ff92af1, (q31_t)0x7ff909f2, (q31_t)0x7ff8e8a3, (q31_t)0x7ff8c705, (q31_t)0x7ff8a519, (q31_t)0x7ff882dd, + (q31_t)0x7ff86053, (q31_t)0x7ff83d79, (q31_t)0x7ff81a51, (q31_t)0x7ff7f6da, (q31_t)0x7ff7d313, (q31_t)0x7ff7aefe, (q31_t)0x7ff78a9a, (q31_t)0x7ff765e7, + (q31_t)0x7ff740e5, (q31_t)0x7ff71b94, (q31_t)0x7ff6f5f4, (q31_t)0x7ff6d005, (q31_t)0x7ff6a9c8, (q31_t)0x7ff6833b, (q31_t)0x7ff65c5f, (q31_t)0x7ff63535, + (q31_t)0x7ff60dbb, (q31_t)0x7ff5e5f3, (q31_t)0x7ff5bddc, (q31_t)0x7ff59576, (q31_t)0x7ff56cc0, (q31_t)0x7ff543bc, (q31_t)0x7ff51a69, (q31_t)0x7ff4f0c7, + (q31_t)0x7ff4c6d6, (q31_t)0x7ff49c96, (q31_t)0x7ff47208, (q31_t)0x7ff4472a, (q31_t)0x7ff41bfd, (q31_t)0x7ff3f082, (q31_t)0x7ff3c4b7, (q31_t)0x7ff3989e, + (q31_t)0x7ff36c36, (q31_t)0x7ff33f7e, (q31_t)0x7ff31278, (q31_t)0x7ff2e523, (q31_t)0x7ff2b77f, (q31_t)0x7ff2898c, (q31_t)0x7ff25b4a, (q31_t)0x7ff22cb9, + (q31_t)0x7ff1fdd9, (q31_t)0x7ff1ceab, (q31_t)0x7ff19f2d, (q31_t)0x7ff16f61, (q31_t)0x7ff13f45, (q31_t)0x7ff10edb, (q31_t)0x7ff0de22, (q31_t)0x7ff0ad19, + (q31_t)0x7ff07bc2, (q31_t)0x7ff04a1c, (q31_t)0x7ff01827, (q31_t)0x7fefe5e4, (q31_t)0x7fefb351, (q31_t)0x7fef806f, (q31_t)0x7fef4d3e, (q31_t)0x7fef19bf, + (q31_t)0x7feee5f0, (q31_t)0x7feeb1d3, (q31_t)0x7fee7d67, (q31_t)0x7fee48ac, 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(q31_t)0x93b90a0, + (q31_t)0x9354c4f, (q31_t)0x92f07f8, (q31_t)0x928c39b, (q31_t)0x9227f39, (q31_t)0x91c3ad2, (q31_t)0x915f664, (q31_t)0x90fb1f1, (q31_t)0x9096d79, + (q31_t)0x90328fb, (q31_t)0x8fce477, (q31_t)0x8f69fee, (q31_t)0x8f05b5f, (q31_t)0x8ea16cb, (q31_t)0x8e3d231, (q31_t)0x8dd8d92, (q31_t)0x8d748ed, + (q31_t)0x8d10443, (q31_t)0x8cabf93, (q31_t)0x8c47ade, (q31_t)0x8be3624, (q31_t)0x8b7f164, (q31_t)0x8b1ac9f, (q31_t)0x8ab67d4, (q31_t)0x8a52304, + (q31_t)0x89ede2f, (q31_t)0x8989955, (q31_t)0x8925475, (q31_t)0x88c0f90, (q31_t)0x885caa5, (q31_t)0x87f85b5, (q31_t)0x87940c1, (q31_t)0x872fbc6, + (q31_t)0x86cb6c7, (q31_t)0x86671c2, (q31_t)0x8602cb9, (q31_t)0x859e7aa, (q31_t)0x853a296, (q31_t)0x84d5d7d, (q31_t)0x847185e, (q31_t)0x840d33b, + (q31_t)0x83a8e12, (q31_t)0x83448e5, (q31_t)0x82e03b2, (q31_t)0x827be7a, (q31_t)0x821793e, (q31_t)0x81b33fc, (q31_t)0x814eeb5, (q31_t)0x80ea969, + (q31_t)0x8086419, (q31_t)0x8021ec3, (q31_t)0x7fbd968, (q31_t)0x7f59409, (q31_t)0x7ef4ea4, (q31_t)0x7e9093b, (q31_t)0x7e2c3cd, (q31_t)0x7dc7e5a, + (q31_t)0x7d638e2, (q31_t)0x7cff365, (q31_t)0x7c9ade4, (q31_t)0x7c3685d, (q31_t)0x7bd22d2, (q31_t)0x7b6dd42, (q31_t)0x7b097ad, (q31_t)0x7aa5214, + (q31_t)0x7a40c76, (q31_t)0x79dc6d3, (q31_t)0x797812b, (q31_t)0x7913b7f, (q31_t)0x78af5ce, (q31_t)0x784b019, (q31_t)0x77e6a5e, (q31_t)0x77824a0, + (q31_t)0x771dedc, (q31_t)0x76b9914, (q31_t)0x7655347, (q31_t)0x75f0d76, (q31_t)0x758c7a1, (q31_t)0x75281c6, (q31_t)0x74c3be7, (q31_t)0x745f604, + (q31_t)0x73fb01c, (q31_t)0x7396a30, (q31_t)0x733243f, (q31_t)0x72cde4a, (q31_t)0x7269851, (q31_t)0x7205253, (q31_t)0x71a0c50, (q31_t)0x713c64a, + (q31_t)0x70d803f, (q31_t)0x7073a2f, (q31_t)0x700f41b, (q31_t)0x6faae03, (q31_t)0x6f467e7, (q31_t)0x6ee21c6, (q31_t)0x6e7dba1, (q31_t)0x6e19578, + (q31_t)0x6db4f4a, (q31_t)0x6d50919, (q31_t)0x6cec2e3, (q31_t)0x6c87ca9, (q31_t)0x6c2366a, (q31_t)0x6bbf028, (q31_t)0x6b5a9e1, (q31_t)0x6af6396, + (q31_t)0x6a91d47, (q31_t)0x6a2d6f4, (q31_t)0x69c909d, (q31_t)0x6964a42, (q31_t)0x69003e3, (q31_t)0x689bd80, (q31_t)0x6837718, (q31_t)0x67d30ad, + (q31_t)0x676ea3d, (q31_t)0x670a3ca, (q31_t)0x66a5d53, (q31_t)0x66416d8, (q31_t)0x65dd058, (q31_t)0x65789d5, (q31_t)0x651434e, (q31_t)0x64afcc3, + (q31_t)0x644b634, (q31_t)0x63e6fa2, (q31_t)0x638290b, (q31_t)0x631e271, (q31_t)0x62b9bd3, (q31_t)0x6255531, (q31_t)0x61f0e8b, (q31_t)0x618c7e1, + (q31_t)0x6128134, (q31_t)0x60c3a83, (q31_t)0x605f3ce, (q31_t)0x5ffad15, (q31_t)0x5f96659, (q31_t)0x5f31f99, (q31_t)0x5ecd8d6, (q31_t)0x5e6920e, + (q31_t)0x5e04b43, (q31_t)0x5da0475, (q31_t)0x5d3bda3, (q31_t)0x5cd76cd, (q31_t)0x5c72ff4, (q31_t)0x5c0e917, (q31_t)0x5baa237, (q31_t)0x5b45b53, + (q31_t)0x5ae146b, (q31_t)0x5a7cd80, (q31_t)0x5a18692, (q31_t)0x59b3fa0, (q31_t)0x594f8aa, (q31_t)0x58eb1b2, (q31_t)0x5886ab5, (q31_t)0x58223b6, + (q31_t)0x57bdcb3, (q31_t)0x57595ac, (q31_t)0x56f4ea2, (q31_t)0x5690795, (q31_t)0x562c085, (q31_t)0x55c7971, (q31_t)0x556325a, (q31_t)0x54feb3f, + (q31_t)0x549a422, (q31_t)0x5435d01, (q31_t)0x53d15dd, (q31_t)0x536ceb5, (q31_t)0x530878a, (q31_t)0x52a405d, (q31_t)0x523f92c, (q31_t)0x51db1f7, + (q31_t)0x5176ac0, (q31_t)0x5112385, (q31_t)0x50adc48, (q31_t)0x5049507, (q31_t)0x4fe4dc3, (q31_t)0x4f8067c, (q31_t)0x4f1bf32, (q31_t)0x4eb77e5, + (q31_t)0x4e53095, (q31_t)0x4dee942, (q31_t)0x4d8a1ec, (q31_t)0x4d25a93, (q31_t)0x4cc1337, (q31_t)0x4c5cbd8, (q31_t)0x4bf8476, (q31_t)0x4b93d11, + (q31_t)0x4b2f5a9, (q31_t)0x4acae3e, (q31_t)0x4a666d1, (q31_t)0x4a01f60, (q31_t)0x499d7ed, (q31_t)0x4939077, (q31_t)0x48d48fe, (q31_t)0x4870182, + (q31_t)0x480ba04, (q31_t)0x47a7282, (q31_t)0x4742afe, (q31_t)0x46de377, (q31_t)0x4679bee, (q31_t)0x4615461, (q31_t)0x45b0cd2, (q31_t)0x454c541, + (q31_t)0x44e7dac, (q31_t)0x4483615, (q31_t)0x441ee7c, (q31_t)0x43ba6df, (q31_t)0x4355f40, (q31_t)0x42f179f, (q31_t)0x428cffb, (q31_t)0x4228854, + (q31_t)0x41c40ab, (q31_t)0x415f8ff, (q31_t)0x40fb151, (q31_t)0x40969a0, (q31_t)0x40321ed, (q31_t)0x3fcda37, (q31_t)0x3f6927f, (q31_t)0x3f04ac4, + (q31_t)0x3ea0307, (q31_t)0x3e3bb48, (q31_t)0x3dd7386, (q31_t)0x3d72bc2, (q31_t)0x3d0e3fb, (q31_t)0x3ca9c32, (q31_t)0x3c45467, (q31_t)0x3be0c99, + (q31_t)0x3b7c4c9, (q31_t)0x3b17cf7, (q31_t)0x3ab3523, (q31_t)0x3a4ed4c, (q31_t)0x39ea573, (q31_t)0x3985d97, (q31_t)0x39215ba, (q31_t)0x38bcdda, + (q31_t)0x38585f8, (q31_t)0x37f3e14, (q31_t)0x378f62e, (q31_t)0x372ae46, (q31_t)0x36c665b, (q31_t)0x3661e6f, (q31_t)0x35fd680, (q31_t)0x3598e8f, + (q31_t)0x353469c, (q31_t)0x34cfea8, (q31_t)0x346b6b1, (q31_t)0x3406eb8, (q31_t)0x33a26bd, (q31_t)0x333dec0, (q31_t)0x32d96c1, (q31_t)0x3274ec0, + (q31_t)0x32106bd, (q31_t)0x31abeb9, (q31_t)0x31476b2, (q31_t)0x30e2ea9, (q31_t)0x307e69f, (q31_t)0x3019e93, (q31_t)0x2fb5684, (q31_t)0x2f50e74, + (q31_t)0x2eec663, (q31_t)0x2e87e4f, (q31_t)0x2e2363a, (q31_t)0x2dbee22, (q31_t)0x2d5a609, (q31_t)0x2cf5def, (q31_t)0x2c915d2, (q31_t)0x2c2cdb4, + (q31_t)0x2bc8594, (q31_t)0x2b63d73, (q31_t)0x2aff54f, (q31_t)0x2a9ad2a, (q31_t)0x2a36504, (q31_t)0x29d1cdc, (q31_t)0x296d4b2, (q31_t)0x2908c87, + (q31_t)0x28a445a, (q31_t)0x283fc2b, (q31_t)0x27db3fb, (q31_t)0x2776bc9, (q31_t)0x2712396, (q31_t)0x26adb62, (q31_t)0x264932b, (q31_t)0x25e4af4, + (q31_t)0x25802bb, (q31_t)0x251ba80, (q31_t)0x24b7244, (q31_t)0x2452a07, (q31_t)0x23ee1c8, (q31_t)0x2389988, (q31_t)0x2325147, (q31_t)0x22c0904, + (q31_t)0x225c0bf, (q31_t)0x21f787a, (q31_t)0x2193033, (q31_t)0x212e7eb, (q31_t)0x20c9fa1, (q31_t)0x2065757, (q31_t)0x2000f0b, (q31_t)0x1f9c6be, + (q31_t)0x1f37e6f, (q31_t)0x1ed3620, (q31_t)0x1e6edcf, (q31_t)0x1e0a57d, (q31_t)0x1da5d2a, (q31_t)0x1d414d6, (q31_t)0x1cdcc80, (q31_t)0x1c7842a, + (q31_t)0x1c13bd2, (q31_t)0x1baf37a, (q31_t)0x1b4ab20, (q31_t)0x1ae62c5, (q31_t)0x1a81a69, (q31_t)0x1a1d20c, (q31_t)0x19b89ae, (q31_t)0x1954150, + (q31_t)0x18ef8f0, (q31_t)0x188b08f, (q31_t)0x182682d, (q31_t)0x17c1fcb, (q31_t)0x175d767, (q31_t)0x16f8f03, (q31_t)0x169469d, (q31_t)0x162fe37, + (q31_t)0x15cb5d0, (q31_t)0x1566d68, (q31_t)0x15024ff, (q31_t)0x149dc96, (q31_t)0x143942b, (q31_t)0x13d4bc0, (q31_t)0x1370354, (q31_t)0x130bae7, + (q31_t)0x12a727a, (q31_t)0x1242a0c, (q31_t)0x11de19d, (q31_t)0x117992e, (q31_t)0x11150be, (q31_t)0x10b084d, (q31_t)0x104bfdb, (q31_t)0xfe7769, + (q31_t)0xf82ef6, (q31_t)0xf1e683, (q31_t)0xeb9e0f, (q31_t)0xe5559b, (q31_t)0xdf0d26, (q31_t)0xd8c4b0, (q31_t)0xd27c3a, (q31_t)0xcc33c3, + (q31_t)0xc5eb4c, (q31_t)0xbfa2d5, (q31_t)0xb95a5d, (q31_t)0xb311e4, (q31_t)0xacc96b, (q31_t)0xa680f2, (q31_t)0xa03878, (q31_t)0x99effe, + (q31_t)0x93a784, (q31_t)0x8d5f09, (q31_t)0x87168e, (q31_t)0x80ce12, (q31_t)0x7a8597, (q31_t)0x743d1a, (q31_t)0x6df49e, (q31_t)0x67ac21, + (q31_t)0x6163a5, (q31_t)0x5b1b27, (q31_t)0x54d2aa, (q31_t)0x4e8a2c, (q31_t)0x4841af, (q31_t)0x41f931, (q31_t)0x3bb0b3, (q31_t)0x356835, + (q31_t)0x2f1fb6, (q31_t)0x28d738, (q31_t)0x228eb9, (q31_t)0x1c463b, (q31_t)0x15fdbc, (q31_t)0xfb53d, (q31_t)0x96cbe, (q31_t)0x3243f +}; + #endif + +/** + @} end of DCT4_IDCT4_Table group + */ + +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_FFT_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_FAST_ALLOW_TABLES) + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FAST_TABLES) || defined(RISCV_TABLE_RECIP_Q15) +/** + @brief Q15 table for reciprocal +*/ +const q15_t __ALIGNED(4) riscvRecipTableQ15[64] = { + 0x7F03, 0x7D13, 0x7B31, 0x795E, 0x7798, 0x75E0, + 0x7434, 0x7294, 0x70FF, 0x6F76, 0x6DF6, 0x6C82, + 0x6B16, 0x69B5, 0x685C, 0x670C, 0x65C4, 0x6484, + 0x634C, 0x621C, 0x60F3, 0x5FD0, 0x5EB5, 0x5DA0, + 0x5C91, 0x5B88, 0x5A85, 0x5988, 0x5890, 0x579E, + 0x56B0, 0x55C8, 0x54E4, 0x5405, 0x532B, 0x5255, + 0x5183, 0x50B6, 0x4FEC, 0x4F26, 0x4E64, 0x4DA6, + 0x4CEC, 0x4C34, 0x4B81, 0x4AD0, 0x4A23, 0x4978, + 0x48D1, 0x482D, 0x478C, 0x46ED, 0x4651, 0x45B8, + 0x4521, 0x448D, 0x43FC, 0x436C, 0x42DF, 0x4255, + 0x41CC, 0x4146, 0x40C2, 0x4040 +}; + +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FAST_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FAST_TABLES) || defined(RISCV_TABLE_RECIP_Q31) + +/** + @brief Q31 table for reciprocal +*/ +const q31_t riscvRecipTableQ31[64] = { + 0x7F03F03F, 0x7D137420, 0x7B31E739, 0x795E9F94, 0x7798FD29, 0x75E06928, + 0x7434554D, 0x72943B4B, 0x70FF9C40, 0x6F760031, 0x6DF6F593, 0x6C8210E3, + 0x6B16EC3A, 0x69B526F6, 0x685C655F, 0x670C505D, 0x65C4952D, 0x6484E519, + 0x634CF53E, 0x621C7E4F, 0x60F33C61, 0x5FD0EEB3, 0x5EB55785, 0x5DA03BEB, + 0x5C9163A1, 0x5B8898E6, 0x5A85A85A, 0x598860DF, 0x58909373, 0x579E1318, + 0x56B0B4B8, 0x55C84F0B, 0x54E4BA80, 0x5405D124, 0x532B6E8F, 0x52556FD0, + 0x5183B35A, 0x50B618F3, 0x4FEC81A2, 0x4F26CFA2, 0x4E64E64E, 0x4DA6AA1D, + 0x4CEC008B, 0x4C34D010, 0x4B810016, 0x4AD078EF, 0x4A2323C4, 0x4978EA96, + 0x48D1B827, 0x482D77FE, 0x478C1657, 0x46ED801D, 0x4651A2E5, 0x45B86CE2, + 0x4521CCE1, 0x448DB244, 0x43FC0CFA, 0x436CCD78, 0x42DFE4B4, 0x42554426, + 0x41CCDDB6, 0x4146A3C6, 0x40C28923, 0x40408102 +}; + +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FAST_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FAST_TABLES) || defined(RISCV_TABLE_SIN_F32) +/** + @par + Example code for the generation of the floating-point sine table: + 
+  tableSize = 512;
+  for (n = 0; n < (tableSize + 1); n++)
+  {
+ 	sinTable[n] = sin(2*PI*n/tableSize);
+  }
+ @par + where PI value is 3.14159265358979 + */ +const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1] = { + 0.00000000f, 0.01227154f, 0.02454123f, 0.03680722f, 0.04906767f, 0.06132074f, + 0.07356456f, 0.08579731f, 0.09801714f, 0.11022221f, 0.12241068f, 0.13458071f, + 0.14673047f, 0.15885814f, 0.17096189f, 0.18303989f, 0.19509032f, 0.20711138f, + 0.21910124f, 0.23105811f, 0.24298018f, 0.25486566f, 0.26671276f, 0.27851969f, + 0.29028468f, 0.30200595f, 0.31368174f, 0.32531029f, 0.33688985f, 0.34841868f, + 0.35989504f, 0.37131719f, 0.38268343f, 0.39399204f, 0.40524131f, 0.41642956f, + 0.42755509f, 0.43861624f, 0.44961133f, 0.46053871f, 0.47139674f, 0.48218377f, + 0.49289819f, 0.50353838f, 0.51410274f, 0.52458968f, 0.53499762f, 0.54532499f, + 0.55557023f, 0.56573181f, 0.57580819f, 0.58579786f, 0.59569930f, 0.60551104f, + 0.61523159f, 0.62485949f, 0.63439328f, 0.64383154f, 0.65317284f, 0.66241578f, + 0.67155895f, 0.68060100f, 0.68954054f, 0.69837625f, 0.70710678f, 0.71573083f, + 0.72424708f, 0.73265427f, 0.74095113f, 0.74913639f, 0.75720885f, 0.76516727f, + 0.77301045f, 0.78073723f, 0.78834643f, 0.79583690f, 0.80320753f, 0.81045720f, + 0.81758481f, 0.82458930f, 0.83146961f, 0.83822471f, 0.84485357f, 0.85135519f, + 0.85772861f, 0.86397286f, 0.87008699f, 0.87607009f, 0.88192126f, 0.88763962f, + 0.89322430f, 0.89867447f, 0.90398929f, 0.90916798f, 0.91420976f, 0.91911385f, + 0.92387953f, 0.92850608f, 0.93299280f, 0.93733901f, 0.94154407f, 0.94560733f, + 0.94952818f, 0.95330604f, 0.95694034f, 0.96043052f, 0.96377607f, 0.96697647f, + 0.97003125f, 0.97293995f, 0.97570213f, 0.97831737f, 0.98078528f, 0.98310549f, + 0.98527764f, 0.98730142f, 0.98917651f, 0.99090264f, 0.99247953f, 0.99390697f, + 0.99518473f, 0.99631261f, 0.99729046f, 0.99811811f, 0.99879546f, 0.99932238f, + 0.99969882f, 0.99992470f, 1.00000000f, 0.99992470f, 0.99969882f, 0.99932238f, + 0.99879546f, 0.99811811f, 0.99729046f, 0.99631261f, 0.99518473f, 0.99390697f, + 0.99247953f, 0.99090264f, 0.98917651f, 0.98730142f, 0.98527764f, 0.98310549f, + 0.98078528f, 0.97831737f, 0.97570213f, 0.97293995f, 0.97003125f, 0.96697647f, + 0.96377607f, 0.96043052f, 0.95694034f, 0.95330604f, 0.94952818f, 0.94560733f, + 0.94154407f, 0.93733901f, 0.93299280f, 0.92850608f, 0.92387953f, 0.91911385f, + 0.91420976f, 0.90916798f, 0.90398929f, 0.89867447f, 0.89322430f, 0.88763962f, + 0.88192126f, 0.87607009f, 0.87008699f, 0.86397286f, 0.85772861f, 0.85135519f, + 0.84485357f, 0.83822471f, 0.83146961f, 0.82458930f, 0.81758481f, 0.81045720f, + 0.80320753f, 0.79583690f, 0.78834643f, 0.78073723f, 0.77301045f, 0.76516727f, + 0.75720885f, 0.74913639f, 0.74095113f, 0.73265427f, 0.72424708f, 0.71573083f, + 0.70710678f, 0.69837625f, 0.68954054f, 0.68060100f, 0.67155895f, 0.66241578f, + 0.65317284f, 0.64383154f, 0.63439328f, 0.62485949f, 0.61523159f, 0.60551104f, + 0.59569930f, 0.58579786f, 0.57580819f, 0.56573181f, 0.55557023f, 0.54532499f, + 0.53499762f, 0.52458968f, 0.51410274f, 0.50353838f, 0.49289819f, 0.48218377f, + 0.47139674f, 0.46053871f, 0.44961133f, 0.43861624f, 0.42755509f, 0.41642956f, + 0.40524131f, 0.39399204f, 0.38268343f, 0.37131719f, 0.35989504f, 0.34841868f, + 0.33688985f, 0.32531029f, 0.31368174f, 0.30200595f, 0.29028468f, 0.27851969f, + 0.26671276f, 0.25486566f, 0.24298018f, 0.23105811f, 0.21910124f, 0.20711138f, + 0.19509032f, 0.18303989f, 0.17096189f, 0.15885814f, 0.14673047f, 0.13458071f, + 0.12241068f, 0.11022221f, 0.09801714f, 0.08579731f, 0.07356456f, 0.06132074f, + 0.04906767f, 0.03680722f, 0.02454123f, 0.01227154f, 0.00000000f, -0.01227154f, + -0.02454123f, -0.03680722f, -0.04906767f, -0.06132074f, -0.07356456f, + -0.08579731f, -0.09801714f, -0.11022221f, -0.12241068f, -0.13458071f, + -0.14673047f, -0.15885814f, -0.17096189f, -0.18303989f, -0.19509032f, + -0.20711138f, -0.21910124f, -0.23105811f, -0.24298018f, -0.25486566f, + -0.26671276f, -0.27851969f, -0.29028468f, -0.30200595f, -0.31368174f, + -0.32531029f, -0.33688985f, -0.34841868f, -0.35989504f, -0.37131719f, + -0.38268343f, -0.39399204f, -0.40524131f, -0.41642956f, -0.42755509f, + -0.43861624f, -0.44961133f, -0.46053871f, -0.47139674f, -0.48218377f, + -0.49289819f, -0.50353838f, -0.51410274f, -0.52458968f, -0.53499762f, + -0.54532499f, -0.55557023f, -0.56573181f, -0.57580819f, -0.58579786f, + -0.59569930f, -0.60551104f, -0.61523159f, -0.62485949f, -0.63439328f, + -0.64383154f, -0.65317284f, -0.66241578f, -0.67155895f, -0.68060100f, + -0.68954054f, -0.69837625f, -0.70710678f, -0.71573083f, -0.72424708f, + -0.73265427f, -0.74095113f, -0.74913639f, -0.75720885f, -0.76516727f, + -0.77301045f, -0.78073723f, -0.78834643f, -0.79583690f, -0.80320753f, + -0.81045720f, -0.81758481f, -0.82458930f, -0.83146961f, -0.83822471f, + -0.84485357f, -0.85135519f, -0.85772861f, -0.86397286f, -0.87008699f, + -0.87607009f, -0.88192126f, -0.88763962f, -0.89322430f, -0.89867447f, + -0.90398929f, -0.90916798f, -0.91420976f, -0.91911385f, -0.92387953f, + -0.92850608f, -0.93299280f, -0.93733901f, -0.94154407f, -0.94560733f, + -0.94952818f, -0.95330604f, -0.95694034f, -0.96043052f, -0.96377607f, + -0.96697647f, -0.97003125f, -0.97293995f, -0.97570213f, -0.97831737f, + -0.98078528f, -0.98310549f, -0.98527764f, -0.98730142f, -0.98917651f, + -0.99090264f, -0.99247953f, -0.99390697f, -0.99518473f, -0.99631261f, + -0.99729046f, -0.99811811f, -0.99879546f, -0.99932238f, -0.99969882f, + -0.99992470f, -1.00000000f, -0.99992470f, -0.99969882f, -0.99932238f, + -0.99879546f, -0.99811811f, -0.99729046f, -0.99631261f, -0.99518473f, + -0.99390697f, -0.99247953f, -0.99090264f, -0.98917651f, -0.98730142f, + -0.98527764f, -0.98310549f, -0.98078528f, -0.97831737f, -0.97570213f, + -0.97293995f, -0.97003125f, -0.96697647f, -0.96377607f, -0.96043052f, + -0.95694034f, -0.95330604f, -0.94952818f, -0.94560733f, -0.94154407f, + -0.93733901f, -0.93299280f, -0.92850608f, -0.92387953f, -0.91911385f, + -0.91420976f, -0.90916798f, -0.90398929f, -0.89867447f, -0.89322430f, + -0.88763962f, -0.88192126f, -0.87607009f, -0.87008699f, -0.86397286f, + -0.85772861f, -0.85135519f, -0.84485357f, -0.83822471f, -0.83146961f, + -0.82458930f, -0.81758481f, -0.81045720f, -0.80320753f, -0.79583690f, + -0.78834643f, -0.78073723f, -0.77301045f, -0.76516727f, -0.75720885f, + -0.74913639f, -0.74095113f, -0.73265427f, -0.72424708f, -0.71573083f, + -0.70710678f, -0.69837625f, -0.68954054f, -0.68060100f, -0.67155895f, + -0.66241578f, -0.65317284f, -0.64383154f, -0.63439328f, -0.62485949f, + -0.61523159f, -0.60551104f, -0.59569930f, -0.58579786f, -0.57580819f, + -0.56573181f, -0.55557023f, -0.54532499f, -0.53499762f, -0.52458968f, + -0.51410274f, -0.50353838f, -0.49289819f, -0.48218377f, -0.47139674f, + -0.46053871f, -0.44961133f, -0.43861624f, -0.42755509f, -0.41642956f, + -0.40524131f, -0.39399204f, -0.38268343f, -0.37131719f, -0.35989504f, + -0.34841868f, -0.33688985f, -0.32531029f, -0.31368174f, -0.30200595f, + -0.29028468f, -0.27851969f, -0.26671276f, -0.25486566f, -0.24298018f, + -0.23105811f, -0.21910124f, -0.20711138f, -0.19509032f, -0.18303989f, + -0.17096189f, -0.15885814f, -0.14673047f, -0.13458071f, -0.12241068f, + -0.11022221f, -0.09801714f, -0.08579731f, -0.07356456f, -0.06132074f, + -0.04906767f, -0.03680722f, -0.02454123f, -0.01227154f, -0.00000000f +}; +#endif /* defined(RISCV_ALL_FAST_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FAST_TABLES) || defined(RISCV_TABLE_SIN_Q31) +/** + @par + Table values are in Q31 (1.31 fixed-point format) and generation is done in + three steps. First, generate sin values in floating point: + 
+  tableSize = 512;
+  for (n = 0; n < (tableSize + 1); n++)
+  {
+ 	sinTable[n] = sin(2*PI*n/tableSize);
+  }
+ where PI value is 3.14159265358979 + @par + Second, convert floating-point to Q31 (Fixed point): + (sinTable[i] * pow(2, 31)) + @par + Finally, round to the nearest integer value: + sinTable[i] += (sinTable[i] > 0 ? 0.5 : -0.5); + */ +const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1] = { + 0L, 26352928L, 52701887L, 79042909L, 105372028L, 131685278L, 157978697L, + 184248325L, 210490206L, 236700388L, 262874923L, 289009871L, 315101295L, + 341145265L, 367137861L, 393075166L, 418953276L, 444768294L, 470516330L, + 496193509L, 521795963L, 547319836L, 572761285L, 598116479L, 623381598L, + 648552838L, 673626408L, 698598533L, 723465451L, 748223418L, 772868706L, + 797397602L, 821806413L, 846091463L, 870249095L, 894275671L, 918167572L, + 941921200L, 965532978L, 988999351L, 1012316784L, 1035481766L, 1058490808L, + 1081340445L, 1104027237L, 1126547765L, 1148898640L, 1171076495L, 1193077991L, + 1214899813L, 1236538675L, 1257991320L, 1279254516L, 1300325060L, 1321199781L, + 1341875533L, 1362349204L, 1382617710L, 1402678000L, 1422527051L, 1442161874L, + 1461579514L, 1480777044L, 1499751576L, 1518500250L, 1537020244L, 1555308768L, + 1573363068L, 1591180426L, 1608758157L, 1626093616L, 1643184191L, 1660027308L, + 1676620432L, 1692961062L, 1709046739L, 1724875040L, 1740443581L, 1755750017L, + 1770792044L, 1785567396L, 1800073849L, 1814309216L, 1828271356L, 1841958164L, + 1855367581L, 1868497586L, 1881346202L, 1893911494L, 1906191570L, 1918184581L, + 1929888720L, 1941302225L, 1952423377L, 1963250501L, 1973781967L, 1984016189L, + 1993951625L, 2003586779L, 2012920201L, 2021950484L, 2030676269L, 2039096241L, + 2047209133L, 2055013723L, 2062508835L, 2069693342L, 2076566160L, 2083126254L, + 2089372638L, 2095304370L, 2100920556L, 2106220352L, 2111202959L, 2115867626L, + 2120213651L, 2124240380L, 2127947206L, 2131333572L, 2134398966L, 2137142927L, + 2139565043L, 2141664948L, 2143442326L, 2144896910L, 2146028480L, 2146836866L, + 2147321946L, 2147483647L, 2147321946L, 2146836866L, 2146028480L, 2144896910L, + 2143442326L, 2141664948L, 2139565043L, 2137142927L, 2134398966L, 2131333572L, + 2127947206L, 2124240380L, 2120213651L, 2115867626L, 2111202959L, 2106220352L, + 2100920556L, 2095304370L, 2089372638L, 2083126254L, 2076566160L, 2069693342L, + 2062508835L, 2055013723L, 2047209133L, 2039096241L, 2030676269L, 2021950484L, + 2012920201L, 2003586779L, 1993951625L, 1984016189L, 1973781967L, 1963250501L, + 1952423377L, 1941302225L, 1929888720L, 1918184581L, 1906191570L, 1893911494L, + 1881346202L, 1868497586L, 1855367581L, 1841958164L, 1828271356L, 1814309216L, + 1800073849L, 1785567396L, 1770792044L, 1755750017L, 1740443581L, 1724875040L, + 1709046739L, 1692961062L, 1676620432L, 1660027308L, 1643184191L, 1626093616L, + 1608758157L, 1591180426L, 1573363068L, 1555308768L, 1537020244L, 1518500250L, + 1499751576L, 1480777044L, 1461579514L, 1442161874L, 1422527051L, 1402678000L, + 1382617710L, 1362349204L, 1341875533L, 1321199781L, 1300325060L, 1279254516L, + 1257991320L, 1236538675L, 1214899813L, 1193077991L, 1171076495L, 1148898640L, + 1126547765L, 1104027237L, 1081340445L, 1058490808L, 1035481766L, 1012316784L, + 988999351L, 965532978L, 941921200L, 918167572L, 894275671L, 870249095L, + 846091463L, 821806413L, 797397602L, 772868706L, 748223418L, 723465451L, + 698598533L, 673626408L, 648552838L, 623381598L, 598116479L, 572761285L, + 547319836L, 521795963L, 496193509L, 470516330L, 444768294L, 418953276L, + 393075166L, 367137861L, 341145265L, 315101295L, 289009871L, 262874923L, + 236700388L, 210490206L, 184248325L, 157978697L, 131685278L, 105372028L, + 79042909L, 52701887L, 26352928L, 0L, -26352928L, -52701887L, -79042909L, + -105372028L, -131685278L, -157978697L, -184248325L, -210490206L, -236700388L, + -262874923L, -289009871L, -315101295L, -341145265L, -367137861L, -393075166L, + -418953276L, -444768294L, -470516330L, -496193509L, -521795963L, -547319836L, + -572761285L, -598116479L, -623381598L, -648552838L, -673626408L, -698598533L, + -723465451L, -748223418L, -772868706L, -797397602L, -821806413L, -846091463L, + -870249095L, -894275671L, -918167572L, -941921200L, -965532978L, -988999351L, + -1012316784L, -1035481766L, -1058490808L, -1081340445L, -1104027237L, + -1126547765L, -1148898640L, -1171076495L, -1193077991L, -1214899813L, + -1236538675L, -1257991320L, -1279254516L, -1300325060L, -1321199781L, + -1341875533L, -1362349204L, -1382617710L, -1402678000L, -1422527051L, + -1442161874L, -1461579514L, -1480777044L, -1499751576L, -1518500250L, + -1537020244L, -1555308768L, -1573363068L, -1591180426L, -1608758157L, + -1626093616L, -1643184191L, -1660027308L, -1676620432L, -1692961062L, + -1709046739L, -1724875040L, -1740443581L, -1755750017L, -1770792044L, + -1785567396L, -1800073849L, -1814309216L, -1828271356L, -1841958164L, + -1855367581L, -1868497586L, -1881346202L, -1893911494L, -1906191570L, + -1918184581L, -1929888720L, -1941302225L, -1952423377L, -1963250501L, + -1973781967L, -1984016189L, -1993951625L, -2003586779L, -2012920201L, + -2021950484L, -2030676269L, -2039096241L, -2047209133L, -2055013723L, + -2062508835L, -2069693342L, -2076566160L, -2083126254L, -2089372638L, + -2095304370L, -2100920556L, -2106220352L, -2111202959L, -2115867626L, + -2120213651L, -2124240380L, -2127947206L, -2131333572L, -2134398966L, + -2137142927L, -2139565043L, -2141664948L, -2143442326L, -2144896910L, + -2146028480L, -2146836866L, -2147321946L, (q31_t)0x80000000, -2147321946L, + -2146836866L, -2146028480L, -2144896910L, -2143442326L, -2141664948L, + -2139565043L, -2137142927L, -2134398966L, -2131333572L, -2127947206L, + -2124240380L, -2120213651L, -2115867626L, -2111202959L, -2106220352L, + -2100920556L, -2095304370L, -2089372638L, -2083126254L, -2076566160L, + -2069693342L, -2062508835L, -2055013723L, -2047209133L, -2039096241L, + -2030676269L, -2021950484L, -2012920201L, -2003586779L, -1993951625L, + -1984016189L, -1973781967L, -1963250501L, -1952423377L, -1941302225L, + -1929888720L, -1918184581L, -1906191570L, -1893911494L, -1881346202L, + -1868497586L, -1855367581L, -1841958164L, -1828271356L, -1814309216L, + -1800073849L, -1785567396L, -1770792044L, -1755750017L, -1740443581L, + -1724875040L, -1709046739L, -1692961062L, -1676620432L, -1660027308L, + -1643184191L, -1626093616L, -1608758157L, -1591180426L, -1573363068L, + -1555308768L, -1537020244L, -1518500250L, -1499751576L, -1480777044L, + -1461579514L, -1442161874L, -1422527051L, -1402678000L, -1382617710L, + -1362349204L, -1341875533L, -1321199781L, -1300325060L, -1279254516L, + -1257991320L, -1236538675L, -1214899813L, -1193077991L, -1171076495L, + -1148898640L, -1126547765L, -1104027237L, -1081340445L, -1058490808L, + -1035481766L, -1012316784L, -988999351L, -965532978L, -941921200L, + -918167572L, -894275671L, -870249095L, -846091463L, -821806413L, -797397602L, + -772868706L, -748223418L, -723465451L, -698598533L, -673626408L, -648552838L, + -623381598L, -598116479L, -572761285L, -547319836L, -521795963L, -496193509L, + -470516330L, -444768294L, -418953276L, -393075166L, -367137861L, -341145265L, + -315101295L, -289009871L, -262874923L, -236700388L, -210490206L, -184248325L, + -157978697L, -131685278L, -105372028L, -79042909L, -52701887L, -26352928L, 0 +}; + +#endif /* defined(RISCV_ALL_FAST_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FAST_TABLES) || defined(RISCV_TABLE_SIN_Q15) +/** + @par + Table values are in Q15 (1.15 fixed-point format) and generation is done in + three steps. First, generate sin values in floating point: + 
+  tableSize = 512;
+  for (n = 0; n < (tableSize + 1); n++)
+  {
+ 	sinTable[n] = sin(2*PI*n/tableSize);
+  }
+ where PI value is 3.14159265358979 + @par + Second, convert floating-point to Q15 (Fixed point): + (sinTable[i] * pow(2, 15)) + @par + Finally, round to the nearest integer value: + sinTable[i] += (sinTable[i] > 0 ? 0.5 :-0.5); + */ +const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1] = { + 0, 402, 804, 1206, 1608, 2009, 2411, 2811, 3212, 3612, 4011, 4410, 4808, + 5205, 5602, 5998, 6393, 6787, 7180, 7571, 7962, 8351, 8740, 9127, 9512, + 9896, 10279, 10660, 11039, 11417, 11793, 12167, 12540, 12910, 13279, + 13646, 14010, 14373, 14733, 15091, 15447, 15800, 16151, 16500, 16846, + 17190, 17531, 17869, 18205, 18538, 18868, 19195, 19520, 19841, 20160, + 20475, 20788, 21097, 21403, 21706, 22006, 22302, 22595, 22884, 23170, + 23453, 23732, 24008, 24279, 24548, 24812, 25073, 25330, 25583, 25833, + 26078, 26320, 26557, 26791, 27020, 27246, 27467, 27684, 27897, 28106, + 28311, 28511, 28707, 28899, 29086, 29269, 29448, 29622, 29792, 29957, + 30118, 30274, 30425, 30572, 30715, 30853, 30986, 31114, 31238, 31357, + 31471, 31581, 31686, 31786, 31881, 31972, 32058, 32138, 32214, 32286, + 32352, 32413, 32470, 32522, 32568, 32610, 32647, 32679, 32706, 32729, + 32746, 32758, 32766, 32767, 32766, 32758, 32746, 32729, 32706, 32679, + 32647, 32610, 32568, 32522, 32470, 32413, 32352, 32286, 32214, 32138, + 32058, 31972, 31881, 31786, 31686, 31581, 31471, 31357, 31238, 31114, + 30986, 30853, 30715, 30572, 30425, 30274, 30118, 29957, 29792, 29622, + 29448, 29269, 29086, 28899, 28707, 28511, 28311, 28106, 27897, 27684, + 27467, 27246, 27020, 26791, 26557, 26320, 26078, 25833, 25583, 25330, + 25073, 24812, 24548, 24279, 24008, 23732, 23453, 23170, 22884, 22595, + 22302, 22006, 21706, 21403, 21097, 20788, 20475, 20160, 19841, 19520, + 19195, 18868, 18538, 18205, 17869, 17531, 17190, 16846, 16500, 16151, + 15800, 15447, 15091, 14733, 14373, 14010, 13646, 13279, 12910, 12540, + 12167, 11793, 11417, 11039, 10660, 10279, 9896, 9512, 9127, 8740, 8351, + 7962, 7571, 7180, 6787, 6393, 5998, 5602, 5205, 4808, 4410, 4011, 3612, + 3212, 2811, 2411, 2009, 1608, 1206, 804, 402, 0, -402, -804, -1206, + -1608, -2009, -2411, -2811, -3212, -3612, -4011, -4410, -4808, -5205, + -5602, -5998, -6393, -6787, -7180, -7571, -7962, -8351, -8740, -9127, + -9512, -9896, -10279, -10660, -11039, -11417, -11793, -12167, -12540, + -12910, -13279, -13646, -14010, -14373, -14733, -15091, -15447, -15800, + -16151, -16500, -16846, -17190, -17531, -17869, -18205, -18538, -18868, + -19195, -19520, -19841, -20160, -20475, -20788, -21097, -21403, -21706, + -22006, -22302, -22595, -22884, -23170, -23453, -23732, -24008, -24279, + -24548, -24812, -25073, -25330, -25583, -25833, -26078, -26320, -26557, + -26791, -27020, -27246, -27467, -27684, -27897, -28106, -28311, -28511, + -28707, -28899, -29086, -29269, -29448, -29622, -29792, -29957, -30118, + -30274, -30425, -30572, -30715, -30853, -30986, -31114, -31238, -31357, + -31471, -31581, -31686, -31786, -31881, -31972, -32058, -32138, -32214, + -32286, -32352, -32413, -32470, -32522, -32568, -32610, -32647, -32679, + -32706, -32729, -32746, -32758, -32766, -32768, -32766, -32758, -32746, + -32729, -32706, -32679, -32647, -32610, -32568, -32522, -32470, -32413, + -32352, -32286, -32214, -32138, -32058, -31972, -31881, -31786, -31686, + -31581, -31471, -31357, -31238, -31114, -30986, -30853, -30715, -30572, + -30425, -30274, -30118, -29957, -29792, -29622, -29448, -29269, -29086, + -28899, -28707, -28511, -28311, -28106, -27897, -27684, -27467, -27246, + -27020, -26791, -26557, -26320, -26078, -25833, -25583, -25330, -25073, + -24812, -24548, -24279, -24008, -23732, -23453, -23170, -22884, -22595, + -22302, -22006, -21706, -21403, -21097, -20788, -20475, -20160, -19841, + -19520, -19195, -18868, -18538, -18205, -17869, -17531, -17190, -16846, + -16500, -16151, -15800, -15447, -15091, -14733, -14373, -14010, -13646, + -13279, -12910, -12540, -12167, -11793, -11417, -11039, -10660, -10279, + -9896, -9512, -9127, -8740, -8351, -7962, -7571, -7180, -6787, -6393, + -5998, -5602, -5205, -4808, -4410, -4011, -3612, -3212, -2811, -2411, + -2009, -1608, -1206, -804, -402, 0 +}; +#endif /* defined(RISCV_ALL_FAST_TABLES) */ + + + +#endif /* if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_FAST_TABLES) */ + + diff --git a/components/nmsis/dsp/src/CommonTables/riscv_common_tables_f16.c b/components/nmsis/dsp/src/CommonTables/riscv_common_tables_f16.c new file mode 100644 index 00000000..1bfa0a73 --- /dev/null +++ b/components/nmsis/dsp/src/CommonTables/riscv_common_tables_f16.c @@ -0,0 +1,12561 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_common_tables_f16.c + * Description: common tables like fft twiddle factors, Bitreverse, reciprocal etc + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "riscv_math_types_f16.h" +/** + @ingroup ComplexFFT + */ + +/** + @addtogroup CFFT_CIFFT Complex FFT Tables + @{ + */ + + +/** + @brief Floating-point Twiddle factors Table Generation +*/ + +/* F16 */ + +#if defined(RISCV_FLOAT16_SUPPORTED) + +#include "riscv_common_tables_f16.h" + + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_FFT_ALLOW_TABLES) + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_F16_16) + +/** +* \par +* Example code for Floating-point Twiddle factors Generation: +* \par +* 
for(i = 0; i< N/; i++)
+* {
+* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par +* where N = 16 and PI = 3.14159265358979 +* \par +* Cos and Sin values are in interleaved fashion +* +*/ +const float16_t twiddleCoefF16_16[32] = { + (float16_t)1.000000000f, (float16_t)0.000000000f, + (float16_t)0.923879533f, (float16_t)0.382683432f, + (float16_t)0.707106781f, (float16_t)0.707106781f, + (float16_t)0.382683432f, (float16_t)0.923879533f, + (float16_t)0.000000000f, (float16_t)1.000000000f, + (float16_t)-0.382683432f, (float16_t)0.923879533f, + (float16_t)-0.707106781f, (float16_t)0.707106781f, + (float16_t)-0.923879533f, (float16_t)0.382683432f, + (float16_t)-1.000000000f, (float16_t)0.000000000f, + (float16_t)-0.923879533f, (float16_t)-0.382683432f, + (float16_t)-0.707106781f, (float16_t)-0.707106781f, + (float16_t)-0.382683432f, (float16_t)-0.923879533f, + (float16_t)-0.000000000f, (float16_t)-1.000000000f, + (float16_t)0.382683432f, (float16_t)-0.923879533f, + (float16_t)0.707106781f, (float16_t)-0.707106781f, + (float16_t)0.923879533f, (float16_t)-0.382683432f +}; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_F16_32) + +/** +* \par +* Example code for Floating-point Twiddle factors Generation: +* \par +* 
for(i = 0; i< N/; i++)
+* {
+* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par +* where N = 32 and PI = 3.14159265358979 +* \par +* Cos and Sin values are in interleaved fashion +* +*/ +const float16_t twiddleCoefF16_32[64] = { + (float16_t)1.000000000f, (float16_t)0.000000000f, + (float16_t)0.980785280f, (float16_t)0.195090322f, + (float16_t)0.923879533f, (float16_t)0.382683432f, + (float16_t)0.831469612f, (float16_t)0.555570233f, + (float16_t)0.707106781f, (float16_t)0.707106781f, + (float16_t)0.555570233f, (float16_t)0.831469612f, + (float16_t)0.382683432f, (float16_t)0.923879533f, + (float16_t)0.195090322f, (float16_t)0.980785280f, + (float16_t)0.000000000f, (float16_t)1.000000000f, + (float16_t)-0.195090322f, (float16_t)0.980785280f, + (float16_t)-0.382683432f, (float16_t)0.923879533f, + (float16_t)-0.555570233f, (float16_t)0.831469612f, + (float16_t)-0.707106781f, (float16_t)0.707106781f, + (float16_t)-0.831469612f, (float16_t)0.555570233f, + (float16_t)-0.923879533f, (float16_t)0.382683432f, + (float16_t)-0.980785280f, (float16_t)0.195090322f, + (float16_t)-1.000000000f, (float16_t)0.000000000f, + (float16_t)-0.980785280f, (float16_t)-0.195090322f, + (float16_t)-0.923879533f, (float16_t)-0.382683432f, + (float16_t)-0.831469612f, (float16_t)-0.555570233f, + (float16_t)-0.707106781f, (float16_t)-0.707106781f, + (float16_t)-0.555570233f, (float16_t)-0.831469612f, + (float16_t)-0.382683432f, (float16_t)-0.923879533f, + (float16_t)-0.195090322f, (float16_t)-0.980785280f, + (float16_t)-0.000000000f, (float16_t)-1.000000000f, + (float16_t)0.195090322f, (float16_t)-0.980785280f, + (float16_t)0.382683432f, (float16_t)-0.923879533f, + (float16_t)0.555570233f, (float16_t)-0.831469612f, + (float16_t)0.707106781f, (float16_t)-0.707106781f, + (float16_t)0.831469612f, (float16_t)-0.555570233f, + (float16_t)0.923879533f, (float16_t)-0.382683432f, + (float16_t)0.980785280f, (float16_t)-0.195090322f +}; + +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_F16_64) + +/** +* \par +* Example code for Floating-point Twiddle factors Generation: +* \par +* 
for(i = 0; i< N/; i++)
+* {
+* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par +* where N = 64 and PI = 3.14159265358979 +* \par +* Cos and Sin values are in interleaved fashion +* +*/ +const float16_t twiddleCoefF16_64[128] = { + (float16_t)1.000000000f, (float16_t)0.000000000f, + (float16_t)0.995184727f, (float16_t)0.098017140f, + (float16_t)0.980785280f, (float16_t)0.195090322f, + (float16_t)0.956940336f, (float16_t)0.290284677f, + (float16_t)0.923879533f, (float16_t)0.382683432f, + (float16_t)0.881921264f, (float16_t)0.471396737f, + (float16_t)0.831469612f, (float16_t)0.555570233f, + (float16_t)0.773010453f, (float16_t)0.634393284f, + (float16_t)0.707106781f, (float16_t)0.707106781f, + (float16_t)0.634393284f, (float16_t)0.773010453f, + (float16_t)0.555570233f, (float16_t)0.831469612f, + (float16_t)0.471396737f, (float16_t)0.881921264f, + (float16_t)0.382683432f, (float16_t)0.923879533f, + (float16_t)0.290284677f, (float16_t)0.956940336f, + (float16_t)0.195090322f, (float16_t)0.980785280f, + (float16_t)0.098017140f, (float16_t)0.995184727f, + (float16_t)0.000000000f, (float16_t)1.000000000f, + (float16_t)-0.098017140f, (float16_t)0.995184727f, + (float16_t)-0.195090322f, (float16_t)0.980785280f, + (float16_t)-0.290284677f, (float16_t)0.956940336f, + (float16_t)-0.382683432f, (float16_t)0.923879533f, + (float16_t)-0.471396737f, (float16_t)0.881921264f, + (float16_t)-0.555570233f, (float16_t)0.831469612f, + (float16_t)-0.634393284f, (float16_t)0.773010453f, + (float16_t)-0.707106781f, (float16_t)0.707106781f, + (float16_t)-0.773010453f, (float16_t)0.634393284f, + (float16_t)-0.831469612f, (float16_t)0.555570233f, + (float16_t)-0.881921264f, (float16_t)0.471396737f, + (float16_t)-0.923879533f, (float16_t)0.382683432f, + (float16_t)-0.956940336f, (float16_t)0.290284677f, + (float16_t)-0.980785280f, (float16_t)0.195090322f, + (float16_t)-0.995184727f, (float16_t)0.098017140f, + (float16_t)-1.000000000f, (float16_t)0.000000000f, + (float16_t)-0.995184727f, (float16_t)-0.098017140f, + (float16_t)-0.980785280f, (float16_t)-0.195090322f, + (float16_t)-0.956940336f, (float16_t)-0.290284677f, + (float16_t)-0.923879533f, (float16_t)-0.382683432f, + (float16_t)-0.881921264f, (float16_t)-0.471396737f, + (float16_t)-0.831469612f, (float16_t)-0.555570233f, + (float16_t)-0.773010453f, (float16_t)-0.634393284f, + (float16_t)-0.707106781f, (float16_t)-0.707106781f, + (float16_t)-0.634393284f, (float16_t)-0.773010453f, + (float16_t)-0.555570233f, (float16_t)-0.831469612f, + (float16_t)-0.471396737f, (float16_t)-0.881921264f, + (float16_t)-0.382683432f, (float16_t)-0.923879533f, + (float16_t)-0.290284677f, (float16_t)-0.956940336f, + (float16_t)-0.195090322f, (float16_t)-0.980785280f, + (float16_t)-0.098017140f, (float16_t)-0.995184727f, + (float16_t)-0.000000000f, (float16_t)-1.000000000f, + (float16_t)0.098017140f, (float16_t)-0.995184727f, + (float16_t)0.195090322f, (float16_t)-0.980785280f, + (float16_t)0.290284677f, (float16_t)-0.956940336f, + (float16_t)0.382683432f, (float16_t)-0.923879533f, + (float16_t)0.471396737f, (float16_t)-0.881921264f, + (float16_t)0.555570233f, (float16_t)-0.831469612f, + (float16_t)0.634393284f, (float16_t)-0.773010453f, + (float16_t)0.707106781f, (float16_t)-0.707106781f, + (float16_t)0.773010453f, (float16_t)-0.634393284f, + (float16_t)0.831469612f, (float16_t)-0.555570233f, + (float16_t)0.881921264f, (float16_t)-0.471396737f, + (float16_t)0.923879533f, (float16_t)-0.382683432f, + (float16_t)0.956940336f, (float16_t)-0.290284677f, + (float16_t)0.980785280f, (float16_t)-0.195090322f, + (float16_t)0.995184727f, (float16_t)-0.098017140f +}; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_F16_128) + +/** +* \par +* Example code for Floating-point Twiddle factors Generation: +* \par +* 
for(i = 0; i< N/; i++)
+* {
+* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par +* where N = 128 and PI = 3.14159265358979 +* \par +* Cos and Sin values are in interleaved fashion +* +*/ + +const float16_t twiddleCoefF16_128[256] = { + (float16_t)1.000000000f, (float16_t)0.000000000f, + (float16_t)0.998795456f, (float16_t)0.049067674f, + (float16_t)0.995184727f, (float16_t)0.098017140f, + (float16_t)0.989176510f, (float16_t)0.146730474f, + (float16_t)0.980785280f, (float16_t)0.195090322f, + (float16_t)0.970031253f, (float16_t)0.242980180f, + (float16_t)0.956940336f, (float16_t)0.290284677f, + (float16_t)0.941544065f, (float16_t)0.336889853f, + (float16_t)0.923879533f, (float16_t)0.382683432f, + (float16_t)0.903989293f, (float16_t)0.427555093f, + (float16_t)0.881921264f, (float16_t)0.471396737f, + (float16_t)0.857728610f, (float16_t)0.514102744f, + (float16_t)0.831469612f, (float16_t)0.555570233f, + (float16_t)0.803207531f, (float16_t)0.595699304f, + (float16_t)0.773010453f, (float16_t)0.634393284f, + (float16_t)0.740951125f, (float16_t)0.671558955f, + (float16_t)0.707106781f, (float16_t)0.707106781f, + (float16_t)0.671558955f, (float16_t)0.740951125f, + (float16_t)0.634393284f, (float16_t)0.773010453f, + (float16_t)0.595699304f, (float16_t)0.803207531f, + (float16_t)0.555570233f, (float16_t)0.831469612f, + (float16_t)0.514102744f, (float16_t)0.857728610f, + (float16_t)0.471396737f, (float16_t)0.881921264f, + (float16_t)0.427555093f, (float16_t)0.903989293f, + (float16_t)0.382683432f, (float16_t)0.923879533f, + (float16_t)0.336889853f, (float16_t)0.941544065f, + (float16_t)0.290284677f, (float16_t)0.956940336f, + (float16_t)0.242980180f, (float16_t)0.970031253f, + (float16_t)0.195090322f, (float16_t)0.980785280f, + (float16_t)0.146730474f, (float16_t)0.989176510f, + (float16_t)0.098017140f, (float16_t)0.995184727f, + (float16_t)0.049067674f, (float16_t)0.998795456f, + (float16_t)0.000000000f, (float16_t)1.000000000f, + (float16_t)-0.049067674f, (float16_t)0.998795456f, + (float16_t)-0.098017140f, (float16_t)0.995184727f, + (float16_t)-0.146730474f, (float16_t)0.989176510f, + (float16_t)-0.195090322f, (float16_t)0.980785280f, + (float16_t)-0.242980180f, (float16_t)0.970031253f, + (float16_t)-0.290284677f, (float16_t)0.956940336f, + (float16_t)-0.336889853f, (float16_t)0.941544065f, + (float16_t)-0.382683432f, (float16_t)0.923879533f, + (float16_t)-0.427555093f, (float16_t)0.903989293f, + (float16_t)-0.471396737f, (float16_t)0.881921264f, + (float16_t)-0.514102744f, (float16_t)0.857728610f, + (float16_t)-0.555570233f, (float16_t)0.831469612f, + (float16_t)-0.595699304f, (float16_t)0.803207531f, + (float16_t)-0.634393284f, (float16_t)0.773010453f, + (float16_t)-0.671558955f, (float16_t)0.740951125f, + (float16_t)-0.707106781f, (float16_t)0.707106781f, + (float16_t)-0.740951125f, (float16_t)0.671558955f, + (float16_t)-0.773010453f, (float16_t)0.634393284f, + (float16_t)-0.803207531f, (float16_t)0.595699304f, + (float16_t)-0.831469612f, (float16_t)0.555570233f, + (float16_t)-0.857728610f, (float16_t)0.514102744f, + (float16_t)-0.881921264f, (float16_t)0.471396737f, + (float16_t)-0.903989293f, (float16_t)0.427555093f, + (float16_t)-0.923879533f, (float16_t)0.382683432f, + (float16_t)-0.941544065f, (float16_t)0.336889853f, + (float16_t)-0.956940336f, (float16_t)0.290284677f, + (float16_t)-0.970031253f, (float16_t)0.242980180f, + (float16_t)-0.980785280f, (float16_t)0.195090322f, + (float16_t)-0.989176510f, (float16_t)0.146730474f, + (float16_t)-0.995184727f, (float16_t)0.098017140f, + (float16_t)-0.998795456f, (float16_t)0.049067674f, + (float16_t)-1.000000000f, (float16_t)0.000000000f, + (float16_t)-0.998795456f, (float16_t)-0.049067674f, + (float16_t)-0.995184727f, (float16_t)-0.098017140f, + (float16_t)-0.989176510f, (float16_t)-0.146730474f, + (float16_t)-0.980785280f, (float16_t)-0.195090322f, + (float16_t)-0.970031253f, (float16_t)-0.242980180f, + (float16_t)-0.956940336f, (float16_t)-0.290284677f, + (float16_t)-0.941544065f, (float16_t)-0.336889853f, + (float16_t)-0.923879533f, (float16_t)-0.382683432f, + (float16_t)-0.903989293f, (float16_t)-0.427555093f, + (float16_t)-0.881921264f, (float16_t)-0.471396737f, + (float16_t)-0.857728610f, (float16_t)-0.514102744f, + (float16_t)-0.831469612f, (float16_t)-0.555570233f, + (float16_t)-0.803207531f, (float16_t)-0.595699304f, + (float16_t)-0.773010453f, (float16_t)-0.634393284f, + (float16_t)-0.740951125f, (float16_t)-0.671558955f, + (float16_t)-0.707106781f, (float16_t)-0.707106781f, + (float16_t)-0.671558955f, (float16_t)-0.740951125f, + (float16_t)-0.634393284f, (float16_t)-0.773010453f, + (float16_t)-0.595699304f, (float16_t)-0.803207531f, + (float16_t)-0.555570233f, (float16_t)-0.831469612f, + (float16_t)-0.514102744f, (float16_t)-0.857728610f, + (float16_t)-0.471396737f, (float16_t)-0.881921264f, + (float16_t)-0.427555093f, (float16_t)-0.903989293f, + (float16_t)-0.382683432f, (float16_t)-0.923879533f, + (float16_t)-0.336889853f, (float16_t)-0.941544065f, + (float16_t)-0.290284677f, (float16_t)-0.956940336f, + (float16_t)-0.242980180f, (float16_t)-0.970031253f, + (float16_t)-0.195090322f, (float16_t)-0.980785280f, + (float16_t)-0.146730474f, (float16_t)-0.989176510f, + (float16_t)-0.098017140f, (float16_t)-0.995184727f, + (float16_t)-0.049067674f, (float16_t)-0.998795456f, + (float16_t)-0.000000000f, (float16_t)-1.000000000f, + (float16_t)0.049067674f, (float16_t)-0.998795456f, + (float16_t)0.098017140f, (float16_t)-0.995184727f, + (float16_t)0.146730474f, (float16_t)-0.989176510f, + (float16_t)0.195090322f, (float16_t)-0.980785280f, + (float16_t)0.242980180f, (float16_t)-0.970031253f, + (float16_t)0.290284677f, (float16_t)-0.956940336f, + (float16_t)0.336889853f, (float16_t)-0.941544065f, + (float16_t)0.382683432f, (float16_t)-0.923879533f, + (float16_t)0.427555093f, (float16_t)-0.903989293f, + (float16_t)0.471396737f, (float16_t)-0.881921264f, + (float16_t)0.514102744f, (float16_t)-0.857728610f, + (float16_t)0.555570233f, (float16_t)-0.831469612f, + (float16_t)0.595699304f, (float16_t)-0.803207531f, + (float16_t)0.634393284f, (float16_t)-0.773010453f, + (float16_t)0.671558955f, (float16_t)-0.740951125f, + (float16_t)0.707106781f, (float16_t)-0.707106781f, + (float16_t)0.740951125f, (float16_t)-0.671558955f, + (float16_t)0.773010453f, (float16_t)-0.634393284f, + (float16_t)0.803207531f, (float16_t)-0.595699304f, + (float16_t)0.831469612f, (float16_t)-0.555570233f, + (float16_t)0.857728610f, (float16_t)-0.514102744f, + (float16_t)0.881921264f, (float16_t)-0.471396737f, + (float16_t)0.903989293f, (float16_t)-0.427555093f, + (float16_t)0.923879533f, (float16_t)-0.382683432f, + (float16_t)0.941544065f, (float16_t)-0.336889853f, + (float16_t)0.956940336f, (float16_t)-0.290284677f, + (float16_t)0.970031253f, (float16_t)-0.242980180f, + (float16_t)0.980785280f, (float16_t)-0.195090322f, + (float16_t)0.989176510f, (float16_t)-0.146730474f, + (float16_t)0.995184727f, (float16_t)-0.098017140f, + (float16_t)0.998795456f, (float16_t)-0.049067674f +}; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_F16_256) + +/** +* \par +* Example code for Floating-point Twiddle factors Generation: +* \par +* 
for(i = 0; i< N/; i++)
+* {
+* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par +* where N = 256 and PI = 3.14159265358979 +* \par +* Cos and Sin values are in interleaved fashion +* +*/ +const float16_t twiddleCoefF16_256[512] = { + (float16_t)1.000000000f, (float16_t)0.000000000f, + (float16_t)0.999698819f, (float16_t)0.024541229f, + (float16_t)0.998795456f, (float16_t)0.049067674f, + (float16_t)0.997290457f, (float16_t)0.073564564f, + (float16_t)0.995184727f, (float16_t)0.098017140f, + (float16_t)0.992479535f, (float16_t)0.122410675f, + (float16_t)0.989176510f, (float16_t)0.146730474f, + (float16_t)0.985277642f, (float16_t)0.170961889f, + (float16_t)0.980785280f, (float16_t)0.195090322f, + (float16_t)0.975702130f, (float16_t)0.219101240f, + (float16_t)0.970031253f, (float16_t)0.242980180f, + (float16_t)0.963776066f, (float16_t)0.266712757f, + (float16_t)0.956940336f, (float16_t)0.290284677f, + (float16_t)0.949528181f, (float16_t)0.313681740f, + (float16_t)0.941544065f, (float16_t)0.336889853f, + (float16_t)0.932992799f, (float16_t)0.359895037f, + (float16_t)0.923879533f, (float16_t)0.382683432f, + (float16_t)0.914209756f, (float16_t)0.405241314f, + (float16_t)0.903989293f, (float16_t)0.427555093f, + (float16_t)0.893224301f, (float16_t)0.449611330f, + (float16_t)0.881921264f, (float16_t)0.471396737f, + (float16_t)0.870086991f, (float16_t)0.492898192f, + (float16_t)0.857728610f, (float16_t)0.514102744f, + (float16_t)0.844853565f, (float16_t)0.534997620f, + (float16_t)0.831469612f, (float16_t)0.555570233f, + (float16_t)0.817584813f, (float16_t)0.575808191f, + (float16_t)0.803207531f, (float16_t)0.595699304f, + (float16_t)0.788346428f, (float16_t)0.615231591f, + (float16_t)0.773010453f, (float16_t)0.634393284f, + (float16_t)0.757208847f, (float16_t)0.653172843f, + (float16_t)0.740951125f, (float16_t)0.671558955f, + (float16_t)0.724247083f, (float16_t)0.689540545f, + (float16_t)0.707106781f, (float16_t)0.707106781f, + (float16_t)0.689540545f, (float16_t)0.724247083f, + (float16_t)0.671558955f, (float16_t)0.740951125f, + (float16_t)0.653172843f, (float16_t)0.757208847f, + (float16_t)0.634393284f, (float16_t)0.773010453f, + (float16_t)0.615231591f, (float16_t)0.788346428f, + (float16_t)0.595699304f, (float16_t)0.803207531f, + (float16_t)0.575808191f, (float16_t)0.817584813f, + (float16_t)0.555570233f, (float16_t)0.831469612f, + (float16_t)0.534997620f, (float16_t)0.844853565f, + (float16_t)0.514102744f, (float16_t)0.857728610f, + (float16_t)0.492898192f, (float16_t)0.870086991f, + (float16_t)0.471396737f, (float16_t)0.881921264f, + (float16_t)0.449611330f, (float16_t)0.893224301f, + (float16_t)0.427555093f, (float16_t)0.903989293f, + (float16_t)0.405241314f, (float16_t)0.914209756f, + (float16_t)0.382683432f, (float16_t)0.923879533f, + (float16_t)0.359895037f, (float16_t)0.932992799f, + (float16_t)0.336889853f, (float16_t)0.941544065f, + (float16_t)0.313681740f, (float16_t)0.949528181f, + (float16_t)0.290284677f, (float16_t)0.956940336f, + (float16_t)0.266712757f, (float16_t)0.963776066f, + (float16_t)0.242980180f, (float16_t)0.970031253f, + (float16_t)0.219101240f, (float16_t)0.975702130f, + (float16_t)0.195090322f, (float16_t)0.980785280f, + (float16_t)0.170961889f, (float16_t)0.985277642f, + (float16_t)0.146730474f, (float16_t)0.989176510f, + (float16_t)0.122410675f, (float16_t)0.992479535f, + (float16_t)0.098017140f, (float16_t)0.995184727f, + (float16_t)0.073564564f, (float16_t)0.997290457f, + (float16_t)0.049067674f, (float16_t)0.998795456f, + (float16_t)0.024541229f, (float16_t)0.999698819f, + (float16_t)0.000000000f, (float16_t)1.000000000f, + (float16_t)-0.024541229f, (float16_t)0.999698819f, + (float16_t)-0.049067674f, (float16_t)0.998795456f, + (float16_t)-0.073564564f, (float16_t)0.997290457f, + (float16_t)-0.098017140f, (float16_t)0.995184727f, + (float16_t)-0.122410675f, (float16_t)0.992479535f, + (float16_t)-0.146730474f, (float16_t)0.989176510f, + (float16_t)-0.170961889f, (float16_t)0.985277642f, + (float16_t)-0.195090322f, (float16_t)0.980785280f, + (float16_t)-0.219101240f, (float16_t)0.975702130f, + (float16_t)-0.242980180f, (float16_t)0.970031253f, + (float16_t)-0.266712757f, (float16_t)0.963776066f, + (float16_t)-0.290284677f, (float16_t)0.956940336f, + (float16_t)-0.313681740f, (float16_t)0.949528181f, + (float16_t)-0.336889853f, (float16_t)0.941544065f, + (float16_t)-0.359895037f, (float16_t)0.932992799f, + (float16_t)-0.382683432f, (float16_t)0.923879533f, + (float16_t)-0.405241314f, (float16_t)0.914209756f, + (float16_t)-0.427555093f, (float16_t)0.903989293f, + (float16_t)-0.449611330f, (float16_t)0.893224301f, + (float16_t)-0.471396737f, (float16_t)0.881921264f, + (float16_t)-0.492898192f, (float16_t)0.870086991f, + (float16_t)-0.514102744f, (float16_t)0.857728610f, + (float16_t)-0.534997620f, (float16_t)0.844853565f, + (float16_t)-0.555570233f, (float16_t)0.831469612f, + (float16_t)-0.575808191f, (float16_t)0.817584813f, + (float16_t)-0.595699304f, (float16_t)0.803207531f, + (float16_t)-0.615231591f, (float16_t)0.788346428f, + (float16_t)-0.634393284f, (float16_t)0.773010453f, + (float16_t)-0.653172843f, (float16_t)0.757208847f, + (float16_t)-0.671558955f, (float16_t)0.740951125f, + (float16_t)-0.689540545f, (float16_t)0.724247083f, + (float16_t)-0.707106781f, (float16_t)0.707106781f, + (float16_t)-0.724247083f, (float16_t)0.689540545f, + (float16_t)-0.740951125f, (float16_t)0.671558955f, + (float16_t)-0.757208847f, (float16_t)0.653172843f, + (float16_t)-0.773010453f, (float16_t)0.634393284f, + (float16_t)-0.788346428f, (float16_t)0.615231591f, + (float16_t)-0.803207531f, (float16_t)0.595699304f, + (float16_t)-0.817584813f, (float16_t)0.575808191f, + (float16_t)-0.831469612f, (float16_t)0.555570233f, + (float16_t)-0.844853565f, (float16_t)0.534997620f, + (float16_t)-0.857728610f, (float16_t)0.514102744f, + (float16_t)-0.870086991f, (float16_t)0.492898192f, + (float16_t)-0.881921264f, (float16_t)0.471396737f, + (float16_t)-0.893224301f, (float16_t)0.449611330f, + (float16_t)-0.903989293f, (float16_t)0.427555093f, + (float16_t)-0.914209756f, (float16_t)0.405241314f, + (float16_t)-0.923879533f, (float16_t)0.382683432f, + (float16_t)-0.932992799f, (float16_t)0.359895037f, + (float16_t)-0.941544065f, (float16_t)0.336889853f, + (float16_t)-0.949528181f, (float16_t)0.313681740f, + (float16_t)-0.956940336f, (float16_t)0.290284677f, + (float16_t)-0.963776066f, (float16_t)0.266712757f, + (float16_t)-0.970031253f, (float16_t)0.242980180f, + (float16_t)-0.975702130f, (float16_t)0.219101240f, + (float16_t)-0.980785280f, (float16_t)0.195090322f, + (float16_t)-0.985277642f, (float16_t)0.170961889f, + (float16_t)-0.989176510f, (float16_t)0.146730474f, + (float16_t)-0.992479535f, (float16_t)0.122410675f, + (float16_t)-0.995184727f, (float16_t)0.098017140f, + (float16_t)-0.997290457f, (float16_t)0.073564564f, + (float16_t)-0.998795456f, (float16_t)0.049067674f, + (float16_t)-0.999698819f, (float16_t)0.024541229f, + (float16_t)-1.000000000f, (float16_t)0.000000000f, + (float16_t)-0.999698819f, (float16_t)-0.024541229f, + (float16_t)-0.998795456f, (float16_t)-0.049067674f, + (float16_t)-0.997290457f, (float16_t)-0.073564564f, + (float16_t)-0.995184727f, (float16_t)-0.098017140f, + (float16_t)-0.992479535f, (float16_t)-0.122410675f, + (float16_t)-0.989176510f, (float16_t)-0.146730474f, + (float16_t)-0.985277642f, (float16_t)-0.170961889f, + (float16_t)-0.980785280f, (float16_t)-0.195090322f, + (float16_t)-0.975702130f, (float16_t)-0.219101240f, + (float16_t)-0.970031253f, (float16_t)-0.242980180f, + (float16_t)-0.963776066f, (float16_t)-0.266712757f, + (float16_t)-0.956940336f, (float16_t)-0.290284677f, + (float16_t)-0.949528181f, (float16_t)-0.313681740f, + (float16_t)-0.941544065f, (float16_t)-0.336889853f, + (float16_t)-0.932992799f, (float16_t)-0.359895037f, + (float16_t)-0.923879533f, (float16_t)-0.382683432f, + (float16_t)-0.914209756f, (float16_t)-0.405241314f, + (float16_t)-0.903989293f, (float16_t)-0.427555093f, + (float16_t)-0.893224301f, (float16_t)-0.449611330f, + (float16_t)-0.881921264f, (float16_t)-0.471396737f, + (float16_t)-0.870086991f, (float16_t)-0.492898192f, + (float16_t)-0.857728610f, (float16_t)-0.514102744f, + (float16_t)-0.844853565f, (float16_t)-0.534997620f, + (float16_t)-0.831469612f, (float16_t)-0.555570233f, + (float16_t)-0.817584813f, (float16_t)-0.575808191f, + (float16_t)-0.803207531f, (float16_t)-0.595699304f, + (float16_t)-0.788346428f, (float16_t)-0.615231591f, + (float16_t)-0.773010453f, (float16_t)-0.634393284f, + (float16_t)-0.757208847f, (float16_t)-0.653172843f, + (float16_t)-0.740951125f, (float16_t)-0.671558955f, + (float16_t)-0.724247083f, (float16_t)-0.689540545f, + (float16_t)-0.707106781f, (float16_t)-0.707106781f, + (float16_t)-0.689540545f, (float16_t)-0.724247083f, + (float16_t)-0.671558955f, (float16_t)-0.740951125f, + (float16_t)-0.653172843f, (float16_t)-0.757208847f, + (float16_t)-0.634393284f, (float16_t)-0.773010453f, + (float16_t)-0.615231591f, (float16_t)-0.788346428f, + (float16_t)-0.595699304f, (float16_t)-0.803207531f, + (float16_t)-0.575808191f, (float16_t)-0.817584813f, + (float16_t)-0.555570233f, (float16_t)-0.831469612f, + (float16_t)-0.534997620f, (float16_t)-0.844853565f, + (float16_t)-0.514102744f, (float16_t)-0.857728610f, + (float16_t)-0.492898192f, (float16_t)-0.870086991f, + (float16_t)-0.471396737f, (float16_t)-0.881921264f, + (float16_t)-0.449611330f, (float16_t)-0.893224301f, + (float16_t)-0.427555093f, (float16_t)-0.903989293f, + (float16_t)-0.405241314f, (float16_t)-0.914209756f, + (float16_t)-0.382683432f, (float16_t)-0.923879533f, + (float16_t)-0.359895037f, (float16_t)-0.932992799f, + (float16_t)-0.336889853f, (float16_t)-0.941544065f, + (float16_t)-0.313681740f, (float16_t)-0.949528181f, + (float16_t)-0.290284677f, (float16_t)-0.956940336f, + (float16_t)-0.266712757f, (float16_t)-0.963776066f, + (float16_t)-0.242980180f, (float16_t)-0.970031253f, + (float16_t)-0.219101240f, (float16_t)-0.975702130f, + (float16_t)-0.195090322f, (float16_t)-0.980785280f, + (float16_t)-0.170961889f, (float16_t)-0.985277642f, + (float16_t)-0.146730474f, (float16_t)-0.989176510f, + (float16_t)-0.122410675f, (float16_t)-0.992479535f, + (float16_t)-0.098017140f, (float16_t)-0.995184727f, + (float16_t)-0.073564564f, (float16_t)-0.997290457f, + (float16_t)-0.049067674f, (float16_t)-0.998795456f, + (float16_t)-0.024541229f, (float16_t)-0.999698819f, + (float16_t)-0.000000000f, (float16_t)-1.000000000f, + (float16_t)0.024541229f, (float16_t)-0.999698819f, + (float16_t)0.049067674f, (float16_t)-0.998795456f, + (float16_t)0.073564564f, (float16_t)-0.997290457f, + (float16_t)0.098017140f, (float16_t)-0.995184727f, + (float16_t)0.122410675f, (float16_t)-0.992479535f, + (float16_t)0.146730474f, (float16_t)-0.989176510f, + (float16_t)0.170961889f, (float16_t)-0.985277642f, + (float16_t)0.195090322f, (float16_t)-0.980785280f, + (float16_t)0.219101240f, (float16_t)-0.975702130f, + (float16_t)0.242980180f, (float16_t)-0.970031253f, + (float16_t)0.266712757f, (float16_t)-0.963776066f, + (float16_t)0.290284677f, (float16_t)-0.956940336f, + (float16_t)0.313681740f, (float16_t)-0.949528181f, + (float16_t)0.336889853f, (float16_t)-0.941544065f, + (float16_t)0.359895037f, (float16_t)-0.932992799f, + (float16_t)0.382683432f, (float16_t)-0.923879533f, + (float16_t)0.405241314f, (float16_t)-0.914209756f, + (float16_t)0.427555093f, (float16_t)-0.903989293f, + (float16_t)0.449611330f, (float16_t)-0.893224301f, + (float16_t)0.471396737f, (float16_t)-0.881921264f, + (float16_t)0.492898192f, (float16_t)-0.870086991f, + (float16_t)0.514102744f, (float16_t)-0.857728610f, + (float16_t)0.534997620f, (float16_t)-0.844853565f, + (float16_t)0.555570233f, (float16_t)-0.831469612f, + (float16_t)0.575808191f, (float16_t)-0.817584813f, + (float16_t)0.595699304f, (float16_t)-0.803207531f, + (float16_t)0.615231591f, (float16_t)-0.788346428f, + (float16_t)0.634393284f, (float16_t)-0.773010453f, + (float16_t)0.653172843f, (float16_t)-0.757208847f, + (float16_t)0.671558955f, (float16_t)-0.740951125f, + (float16_t)0.689540545f, (float16_t)-0.724247083f, + (float16_t)0.707106781f, (float16_t)-0.707106781f, + (float16_t)0.724247083f, (float16_t)-0.689540545f, + (float16_t)0.740951125f, (float16_t)-0.671558955f, + (float16_t)0.757208847f, (float16_t)-0.653172843f, + (float16_t)0.773010453f, (float16_t)-0.634393284f, + (float16_t)0.788346428f, (float16_t)-0.615231591f, + (float16_t)0.803207531f, (float16_t)-0.595699304f, + (float16_t)0.817584813f, (float16_t)-0.575808191f, + (float16_t)0.831469612f, (float16_t)-0.555570233f, + (float16_t)0.844853565f, (float16_t)-0.534997620f, + (float16_t)0.857728610f, (float16_t)-0.514102744f, + (float16_t)0.870086991f, (float16_t)-0.492898192f, + (float16_t)0.881921264f, (float16_t)-0.471396737f, + (float16_t)0.893224301f, (float16_t)-0.449611330f, + (float16_t)0.903989293f, (float16_t)-0.427555093f, + (float16_t)0.914209756f, (float16_t)-0.405241314f, + (float16_t)0.923879533f, (float16_t)-0.382683432f, + (float16_t)0.932992799f, (float16_t)-0.359895037f, + (float16_t)0.941544065f, (float16_t)-0.336889853f, + (float16_t)0.949528181f, (float16_t)-0.313681740f, + (float16_t)0.956940336f, (float16_t)-0.290284677f, + (float16_t)0.963776066f, (float16_t)-0.266712757f, + (float16_t)0.970031253f, (float16_t)-0.242980180f, + (float16_t)0.975702130f, (float16_t)-0.219101240f, + (float16_t)0.980785280f, (float16_t)-0.195090322f, + (float16_t)0.985277642f, (float16_t)-0.170961889f, + (float16_t)0.989176510f, (float16_t)-0.146730474f, + (float16_t)0.992479535f, (float16_t)-0.122410675f, + (float16_t)0.995184727f, (float16_t)-0.098017140f, + (float16_t)0.997290457f, (float16_t)-0.073564564f, + (float16_t)0.998795456f, (float16_t)-0.049067674f, + (float16_t)0.999698819f, (float16_t)-0.024541229f +}; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_F16_512) + +/** +* \par +* Example code for Floating-point Twiddle factors Generation: +* \par +* 
for(i = 0; i< N/; i++)
+* {
+* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par +* where N = 512 and PI = 3.14159265358979 +* \par +* Cos and Sin values are in interleaved fashion +* +*/ +const float16_t twiddleCoefF16_512[1024] = { + (float16_t)1.000000000f, (float16_t)0.000000000f, + (float16_t)0.999924702f, (float16_t)0.012271538f, + (float16_t)0.999698819f, (float16_t)0.024541229f, + (float16_t)0.999322385f, (float16_t)0.036807223f, + (float16_t)0.998795456f, (float16_t)0.049067674f, + (float16_t)0.998118113f, (float16_t)0.061320736f, + (float16_t)0.997290457f, (float16_t)0.073564564f, + (float16_t)0.996312612f, (float16_t)0.085797312f, + (float16_t)0.995184727f, (float16_t)0.098017140f, + (float16_t)0.993906970f, (float16_t)0.110222207f, + (float16_t)0.992479535f, (float16_t)0.122410675f, + (float16_t)0.990902635f, (float16_t)0.134580709f, + (float16_t)0.989176510f, (float16_t)0.146730474f, + (float16_t)0.987301418f, (float16_t)0.158858143f, + (float16_t)0.985277642f, (float16_t)0.170961889f, + (float16_t)0.983105487f, (float16_t)0.183039888f, + (float16_t)0.980785280f, (float16_t)0.195090322f, + (float16_t)0.978317371f, (float16_t)0.207111376f, + (float16_t)0.975702130f, (float16_t)0.219101240f, + (float16_t)0.972939952f, (float16_t)0.231058108f, + (float16_t)0.970031253f, (float16_t)0.242980180f, + (float16_t)0.966976471f, (float16_t)0.254865660f, + (float16_t)0.963776066f, (float16_t)0.266712757f, + (float16_t)0.960430519f, (float16_t)0.278519689f, + (float16_t)0.956940336f, (float16_t)0.290284677f, + (float16_t)0.953306040f, (float16_t)0.302005949f, + (float16_t)0.949528181f, (float16_t)0.313681740f, + (float16_t)0.945607325f, (float16_t)0.325310292f, + (float16_t)0.941544065f, (float16_t)0.336889853f, + (float16_t)0.937339012f, (float16_t)0.348418680f, + (float16_t)0.932992799f, (float16_t)0.359895037f, + (float16_t)0.928506080f, (float16_t)0.371317194f, + (float16_t)0.923879533f, (float16_t)0.382683432f, + (float16_t)0.919113852f, (float16_t)0.393992040f, + (float16_t)0.914209756f, (float16_t)0.405241314f, + (float16_t)0.909167983f, (float16_t)0.416429560f, + (float16_t)0.903989293f, (float16_t)0.427555093f, + (float16_t)0.898674466f, (float16_t)0.438616239f, + (float16_t)0.893224301f, (float16_t)0.449611330f, + (float16_t)0.887639620f, (float16_t)0.460538711f, + (float16_t)0.881921264f, (float16_t)0.471396737f, + (float16_t)0.876070094f, (float16_t)0.482183772f, + (float16_t)0.870086991f, (float16_t)0.492898192f, + (float16_t)0.863972856f, (float16_t)0.503538384f, + (float16_t)0.857728610f, (float16_t)0.514102744f, + (float16_t)0.851355193f, (float16_t)0.524589683f, + (float16_t)0.844853565f, (float16_t)0.534997620f, + (float16_t)0.838224706f, (float16_t)0.545324988f, + (float16_t)0.831469612f, (float16_t)0.555570233f, + (float16_t)0.824589303f, (float16_t)0.565731811f, + (float16_t)0.817584813f, (float16_t)0.575808191f, + (float16_t)0.810457198f, (float16_t)0.585797857f, + (float16_t)0.803207531f, (float16_t)0.595699304f, + (float16_t)0.795836905f, (float16_t)0.605511041f, + (float16_t)0.788346428f, (float16_t)0.615231591f, + (float16_t)0.780737229f, (float16_t)0.624859488f, + (float16_t)0.773010453f, (float16_t)0.634393284f, + (float16_t)0.765167266f, (float16_t)0.643831543f, + (float16_t)0.757208847f, (float16_t)0.653172843f, + (float16_t)0.749136395f, (float16_t)0.662415778f, + (float16_t)0.740951125f, (float16_t)0.671558955f, + (float16_t)0.732654272f, (float16_t)0.680600998f, + (float16_t)0.724247083f, (float16_t)0.689540545f, + (float16_t)0.715730825f, (float16_t)0.698376249f, + (float16_t)0.707106781f, (float16_t)0.707106781f, + (float16_t)0.698376249f, (float16_t)0.715730825f, + (float16_t)0.689540545f, (float16_t)0.724247083f, + (float16_t)0.680600998f, (float16_t)0.732654272f, + (float16_t)0.671558955f, (float16_t)0.740951125f, + (float16_t)0.662415778f, (float16_t)0.749136395f, + (float16_t)0.653172843f, (float16_t)0.757208847f, + (float16_t)0.643831543f, (float16_t)0.765167266f, + (float16_t)0.634393284f, (float16_t)0.773010453f, + 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(float16_t)-0.382683432f, (float16_t)-0.923879533f, + (float16_t)-0.371317194f, (float16_t)-0.928506080f, + (float16_t)-0.359895037f, (float16_t)-0.932992799f, + (float16_t)-0.348418680f, (float16_t)-0.937339012f, + (float16_t)-0.336889853f, (float16_t)-0.941544065f, + (float16_t)-0.325310292f, (float16_t)-0.945607325f, + (float16_t)-0.313681740f, (float16_t)-0.949528181f, + (float16_t)-0.302005949f, (float16_t)-0.953306040f, + (float16_t)-0.290284677f, (float16_t)-0.956940336f, + (float16_t)-0.278519689f, (float16_t)-0.960430519f, + (float16_t)-0.266712757f, (float16_t)-0.963776066f, + (float16_t)-0.254865660f, (float16_t)-0.966976471f, + (float16_t)-0.242980180f, (float16_t)-0.970031253f, + (float16_t)-0.231058108f, (float16_t)-0.972939952f, + (float16_t)-0.219101240f, (float16_t)-0.975702130f, + (float16_t)-0.207111376f, (float16_t)-0.978317371f, + (float16_t)-0.195090322f, (float16_t)-0.980785280f, + (float16_t)-0.183039888f, (float16_t)-0.983105487f, + (float16_t)-0.170961889f, (float16_t)-0.985277642f, + (float16_t)-0.158858143f, (float16_t)-0.987301418f, + (float16_t)-0.146730474f, (float16_t)-0.989176510f, + (float16_t)-0.134580709f, (float16_t)-0.990902635f, + (float16_t)-0.122410675f, (float16_t)-0.992479535f, + (float16_t)-0.110222207f, (float16_t)-0.993906970f, + (float16_t)-0.098017140f, (float16_t)-0.995184727f, + (float16_t)-0.085797312f, (float16_t)-0.996312612f, + (float16_t)-0.073564564f, (float16_t)-0.997290457f, + (float16_t)-0.061320736f, (float16_t)-0.998118113f, + (float16_t)-0.049067674f, (float16_t)-0.998795456f, + (float16_t)-0.036807223f, (float16_t)-0.999322385f, + (float16_t)-0.024541229f, (float16_t)-0.999698819f, + (float16_t)-0.012271538f, (float16_t)-0.999924702f, + (float16_t)-0.000000000f, (float16_t)-1.000000000f, + (float16_t)0.012271538f, (float16_t)-0.999924702f, + (float16_t)0.024541229f, (float16_t)-0.999698819f, + (float16_t)0.036807223f, (float16_t)-0.999322385f, + (float16_t)0.049067674f, (float16_t)-0.998795456f, + (float16_t)0.061320736f, (float16_t)-0.998118113f, + (float16_t)0.073564564f, (float16_t)-0.997290457f, + (float16_t)0.085797312f, (float16_t)-0.996312612f, + (float16_t)0.098017140f, (float16_t)-0.995184727f, + (float16_t)0.110222207f, (float16_t)-0.993906970f, + (float16_t)0.122410675f, (float16_t)-0.992479535f, + (float16_t)0.134580709f, (float16_t)-0.990902635f, + (float16_t)0.146730474f, (float16_t)-0.989176510f, + (float16_t)0.158858143f, (float16_t)-0.987301418f, + (float16_t)0.170961889f, (float16_t)-0.985277642f, + (float16_t)0.183039888f, (float16_t)-0.983105487f, + (float16_t)0.195090322f, (float16_t)-0.980785280f, + (float16_t)0.207111376f, (float16_t)-0.978317371f, + (float16_t)0.219101240f, (float16_t)-0.975702130f, + (float16_t)0.231058108f, (float16_t)-0.972939952f, + (float16_t)0.242980180f, (float16_t)-0.970031253f, + (float16_t)0.254865660f, (float16_t)-0.966976471f, + (float16_t)0.266712757f, (float16_t)-0.963776066f, + (float16_t)0.278519689f, (float16_t)-0.960430519f, + (float16_t)0.290284677f, (float16_t)-0.956940336f, + (float16_t)0.302005949f, (float16_t)-0.953306040f, + (float16_t)0.313681740f, (float16_t)-0.949528181f, + (float16_t)0.325310292f, (float16_t)-0.945607325f, + (float16_t)0.336889853f, (float16_t)-0.941544065f, + (float16_t)0.348418680f, (float16_t)-0.937339012f, + (float16_t)0.359895037f, (float16_t)-0.932992799f, + (float16_t)0.371317194f, (float16_t)-0.928506080f, + (float16_t)0.382683432f, (float16_t)-0.923879533f, + (float16_t)0.393992040f, (float16_t)-0.919113852f, + (float16_t)0.405241314f, (float16_t)-0.914209756f, + (float16_t)0.416429560f, (float16_t)-0.909167983f, + (float16_t)0.427555093f, (float16_t)-0.903989293f, + (float16_t)0.438616239f, (float16_t)-0.898674466f, + (float16_t)0.449611330f, (float16_t)-0.893224301f, + (float16_t)0.460538711f, (float16_t)-0.887639620f, + (float16_t)0.471396737f, (float16_t)-0.881921264f, + (float16_t)0.482183772f, (float16_t)-0.876070094f, + (float16_t)0.492898192f, (float16_t)-0.870086991f, + (float16_t)0.503538384f, (float16_t)-0.863972856f, + (float16_t)0.514102744f, (float16_t)-0.857728610f, + (float16_t)0.524589683f, (float16_t)-0.851355193f, + (float16_t)0.534997620f, (float16_t)-0.844853565f, + (float16_t)0.545324988f, (float16_t)-0.838224706f, + (float16_t)0.555570233f, (float16_t)-0.831469612f, + (float16_t)0.565731811f, (float16_t)-0.824589303f, + (float16_t)0.575808191f, (float16_t)-0.817584813f, + (float16_t)0.585797857f, (float16_t)-0.810457198f, + (float16_t)0.595699304f, (float16_t)-0.803207531f, + (float16_t)0.605511041f, (float16_t)-0.795836905f, + (float16_t)0.615231591f, (float16_t)-0.788346428f, + (float16_t)0.624859488f, (float16_t)-0.780737229f, + (float16_t)0.634393284f, (float16_t)-0.773010453f, + (float16_t)0.643831543f, (float16_t)-0.765167266f, + (float16_t)0.653172843f, (float16_t)-0.757208847f, + (float16_t)0.662415778f, (float16_t)-0.749136395f, + (float16_t)0.671558955f, (float16_t)-0.740951125f, + (float16_t)0.680600998f, (float16_t)-0.732654272f, + (float16_t)0.689540545f, (float16_t)-0.724247083f, + (float16_t)0.698376249f, (float16_t)-0.715730825f, + (float16_t)0.707106781f, (float16_t)-0.707106781f, + (float16_t)0.715730825f, (float16_t)-0.698376249f, + (float16_t)0.724247083f, (float16_t)-0.689540545f, + (float16_t)0.732654272f, (float16_t)-0.680600998f, + (float16_t)0.740951125f, (float16_t)-0.671558955f, + (float16_t)0.749136395f, (float16_t)-0.662415778f, + (float16_t)0.757208847f, (float16_t)-0.653172843f, + (float16_t)0.765167266f, (float16_t)-0.643831543f, + (float16_t)0.773010453f, (float16_t)-0.634393284f, + (float16_t)0.780737229f, (float16_t)-0.624859488f, + (float16_t)0.788346428f, (float16_t)-0.615231591f, + (float16_t)0.795836905f, (float16_t)-0.605511041f, + (float16_t)0.803207531f, (float16_t)-0.595699304f, + (float16_t)0.810457198f, (float16_t)-0.585797857f, + (float16_t)0.817584813f, (float16_t)-0.575808191f, + (float16_t)0.824589303f, (float16_t)-0.565731811f, + (float16_t)0.831469612f, (float16_t)-0.555570233f, + (float16_t)0.838224706f, (float16_t)-0.545324988f, + (float16_t)0.844853565f, (float16_t)-0.534997620f, + (float16_t)0.851355193f, (float16_t)-0.524589683f, + (float16_t)0.857728610f, (float16_t)-0.514102744f, + (float16_t)0.863972856f, (float16_t)-0.503538384f, + (float16_t)0.870086991f, (float16_t)-0.492898192f, + (float16_t)0.876070094f, (float16_t)-0.482183772f, + (float16_t)0.881921264f, (float16_t)-0.471396737f, + (float16_t)0.887639620f, (float16_t)-0.460538711f, + (float16_t)0.893224301f, (float16_t)-0.449611330f, + (float16_t)0.898674466f, (float16_t)-0.438616239f, + (float16_t)0.903989293f, (float16_t)-0.427555093f, + (float16_t)0.909167983f, (float16_t)-0.416429560f, + (float16_t)0.914209756f, (float16_t)-0.405241314f, + (float16_t)0.919113852f, (float16_t)-0.393992040f, + (float16_t)0.923879533f, (float16_t)-0.382683432f, + (float16_t)0.928506080f, (float16_t)-0.371317194f, + (float16_t)0.932992799f, (float16_t)-0.359895037f, + (float16_t)0.937339012f, (float16_t)-0.348418680f, + (float16_t)0.941544065f, (float16_t)-0.336889853f, + (float16_t)0.945607325f, (float16_t)-0.325310292f, + (float16_t)0.949528181f, (float16_t)-0.313681740f, + (float16_t)0.953306040f, (float16_t)-0.302005949f, + (float16_t)0.956940336f, (float16_t)-0.290284677f, + (float16_t)0.960430519f, (float16_t)-0.278519689f, + (float16_t)0.963776066f, (float16_t)-0.266712757f, + (float16_t)0.966976471f, (float16_t)-0.254865660f, + (float16_t)0.970031253f, (float16_t)-0.242980180f, + (float16_t)0.972939952f, (float16_t)-0.231058108f, + (float16_t)0.975702130f, (float16_t)-0.219101240f, + (float16_t)0.978317371f, (float16_t)-0.207111376f, + (float16_t)0.980785280f, (float16_t)-0.195090322f, + (float16_t)0.983105487f, (float16_t)-0.183039888f, + (float16_t)0.985277642f, (float16_t)-0.170961889f, + (float16_t)0.987301418f, (float16_t)-0.158858143f, + (float16_t)0.989176510f, (float16_t)-0.146730474f, + (float16_t)0.990902635f, (float16_t)-0.134580709f, + (float16_t)0.992479535f, (float16_t)-0.122410675f, + (float16_t)0.993906970f, (float16_t)-0.110222207f, + (float16_t)0.995184727f, (float16_t)-0.098017140f, + (float16_t)0.996312612f, (float16_t)-0.085797312f, + (float16_t)0.997290457f, (float16_t)-0.073564564f, + (float16_t)0.998118113f, (float16_t)-0.061320736f, + (float16_t)0.998795456f, (float16_t)-0.049067674f, + (float16_t)0.999322385f, (float16_t)-0.036807223f, + (float16_t)0.999698819f, (float16_t)-0.024541229f, + (float16_t)0.999924702f, (float16_t)-0.012271538f +}; + +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_F16_1024) + +/** +* \par +* Example code for Floating-point Twiddle factors Generation: +* \par +* 
for(i = 0; i< N/; i++)
+* {
+* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par +* where N = 1024 and PI = 3.14159265358979 +* \par +* Cos and Sin values are in interleaved fashion +* +*/ +const float16_t twiddleCoefF16_1024[2048] = { + (float16_t)1.000000000f, (float16_t)0.000000000f, + (float16_t)0.999981175f, (float16_t)0.006135885f, + (float16_t)0.999924702f, (float16_t)0.012271538f, + (float16_t)0.999830582f, (float16_t)0.018406730f, + (float16_t)0.999698819f, (float16_t)0.024541229f, + (float16_t)0.999529418f, (float16_t)0.030674803f, + (float16_t)0.999322385f, (float16_t)0.036807223f, + (float16_t)0.999077728f, (float16_t)0.042938257f, + (float16_t)0.998795456f, (float16_t)0.049067674f, + (float16_t)0.998475581f, (float16_t)0.055195244f, + (float16_t)0.998118113f, (float16_t)0.061320736f, + (float16_t)0.997723067f, (float16_t)0.067443920f, + (float16_t)0.997290457f, (float16_t)0.073564564f, + (float16_t)0.996820299f, (float16_t)0.079682438f, + (float16_t)0.996312612f, (float16_t)0.085797312f, + (float16_t)0.995767414f, (float16_t)0.091908956f, + (float16_t)0.995184727f, (float16_t)0.098017140f, + (float16_t)0.994564571f, (float16_t)0.104121634f, + (float16_t)0.993906970f, (float16_t)0.110222207f, + (float16_t)0.993211949f, (float16_t)0.116318631f, + (float16_t)0.992479535f, (float16_t)0.122410675f, + (float16_t)0.991709754f, (float16_t)0.128498111f, + (float16_t)0.990902635f, (float16_t)0.134580709f, + (float16_t)0.990058210f, (float16_t)0.140658239f, + (float16_t)0.989176510f, (float16_t)0.146730474f, + (float16_t)0.988257568f, (float16_t)0.152797185f, + (float16_t)0.987301418f, (float16_t)0.158858143f, + (float16_t)0.986308097f, (float16_t)0.164913120f, + (float16_t)0.985277642f, (float16_t)0.170961889f, + (float16_t)0.984210092f, (float16_t)0.177004220f, + (float16_t)0.983105487f, (float16_t)0.183039888f, + (float16_t)0.981963869f, (float16_t)0.189068664f, + (float16_t)0.980785280f, (float16_t)0.195090322f, + (float16_t)0.979569766f, (float16_t)0.201104635f, + (float16_t)0.978317371f, (float16_t)0.207111376f, + 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(float16_t)0.937339012f, (float16_t)-0.348418680f, + (float16_t)0.939459224f, (float16_t)-0.342660717f, + (float16_t)0.941544065f, (float16_t)-0.336889853f, + (float16_t)0.943593458f, (float16_t)-0.331106306f, + (float16_t)0.945607325f, (float16_t)-0.325310292f, + (float16_t)0.947585591f, (float16_t)-0.319502031f, + (float16_t)0.949528181f, (float16_t)-0.313681740f, + (float16_t)0.951435021f, (float16_t)-0.307849640f, + (float16_t)0.953306040f, (float16_t)-0.302005949f, + (float16_t)0.955141168f, (float16_t)-0.296150888f, + (float16_t)0.956940336f, (float16_t)-0.290284677f, + (float16_t)0.958703475f, (float16_t)-0.284407537f, + (float16_t)0.960430519f, (float16_t)-0.278519689f, + (float16_t)0.962121404f, (float16_t)-0.272621355f, + (float16_t)0.963776066f, (float16_t)-0.266712757f, + (float16_t)0.965394442f, (float16_t)-0.260794118f, + (float16_t)0.966976471f, (float16_t)-0.254865660f, + (float16_t)0.968522094f, (float16_t)-0.248927606f, + (float16_t)0.970031253f, (float16_t)-0.242980180f, + (float16_t)0.971503891f, (float16_t)-0.237023606f, + (float16_t)0.972939952f, (float16_t)-0.231058108f, + (float16_t)0.974339383f, (float16_t)-0.225083911f, + (float16_t)0.975702130f, (float16_t)-0.219101240f, + (float16_t)0.977028143f, (float16_t)-0.213110320f, + (float16_t)0.978317371f, (float16_t)-0.207111376f, + (float16_t)0.979569766f, (float16_t)-0.201104635f, + (float16_t)0.980785280f, (float16_t)-0.195090322f, + (float16_t)0.981963869f, (float16_t)-0.189068664f, + (float16_t)0.983105487f, (float16_t)-0.183039888f, + (float16_t)0.984210092f, (float16_t)-0.177004220f, + (float16_t)0.985277642f, (float16_t)-0.170961889f, + (float16_t)0.986308097f, (float16_t)-0.164913120f, + (float16_t)0.987301418f, (float16_t)-0.158858143f, + (float16_t)0.988257568f, (float16_t)-0.152797185f, + (float16_t)0.989176510f, (float16_t)-0.146730474f, + (float16_t)0.990058210f, (float16_t)-0.140658239f, + (float16_t)0.990902635f, (float16_t)-0.134580709f, + (float16_t)0.991709754f, (float16_t)-0.128498111f, + (float16_t)0.992479535f, (float16_t)-0.122410675f, + (float16_t)0.993211949f, (float16_t)-0.116318631f, + (float16_t)0.993906970f, (float16_t)-0.110222207f, + (float16_t)0.994564571f, (float16_t)-0.104121634f, + (float16_t)0.995184727f, (float16_t)-0.098017140f, + (float16_t)0.995767414f, (float16_t)-0.091908956f, + (float16_t)0.996312612f, (float16_t)-0.085797312f, + (float16_t)0.996820299f, (float16_t)-0.079682438f, + (float16_t)0.997290457f, (float16_t)-0.073564564f, + (float16_t)0.997723067f, (float16_t)-0.067443920f, + (float16_t)0.998118113f, (float16_t)-0.061320736f, + (float16_t)0.998475581f, (float16_t)-0.055195244f, + (float16_t)0.998795456f, (float16_t)-0.049067674f, + (float16_t)0.999077728f, (float16_t)-0.042938257f, + (float16_t)0.999322385f, (float16_t)-0.036807223f, + (float16_t)0.999529418f, (float16_t)-0.030674803f, + (float16_t)0.999698819f, (float16_t)-0.024541229f, + (float16_t)0.999830582f, (float16_t)-0.018406730f, + (float16_t)0.999924702f, (float16_t)-0.012271538f, + (float16_t)0.999981175f, (float16_t)-0.006135885f +}; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_F16_2048) + +/** +* \par +* Example code for Floating-point Twiddle factors Generation: +* \par +* 
for(i = 0; i< N/; i++)
+* {
+* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par +* where N = 2048 and PI = 3.14159265358979 +* \par +* Cos and Sin values are in interleaved fashion +* +*/ +const float16_t twiddleCoefF16_2048[4096] = { + (float16_t)1.000000000f, (float16_t)0.000000000f, + (float16_t)0.999995294f, (float16_t)0.003067957f, + (float16_t)0.999981175f, (float16_t)0.006135885f, + (float16_t)0.999957645f, (float16_t)0.009203755f, + (float16_t)0.999924702f, (float16_t)0.012271538f, + (float16_t)0.999882347f, (float16_t)0.015339206f, + (float16_t)0.999830582f, (float16_t)0.018406730f, + (float16_t)0.999769405f, (float16_t)0.021474080f, + (float16_t)0.999698819f, (float16_t)0.024541229f, + (float16_t)0.999618822f, (float16_t)0.027608146f, + (float16_t)0.999529418f, (float16_t)0.030674803f, + (float16_t)0.999430605f, (float16_t)0.033741172f, + (float16_t)0.999322385f, (float16_t)0.036807223f, + (float16_t)0.999204759f, (float16_t)0.039872928f, + (float16_t)0.999077728f, (float16_t)0.042938257f, + (float16_t)0.998941293f, (float16_t)0.046003182f, + (float16_t)0.998795456f, (float16_t)0.049067674f, + (float16_t)0.998640218f, (float16_t)0.052131705f, + (float16_t)0.998475581f, (float16_t)0.055195244f, + (float16_t)0.998301545f, (float16_t)0.058258265f, + (float16_t)0.998118113f, (float16_t)0.061320736f, + (float16_t)0.997925286f, (float16_t)0.064382631f, + (float16_t)0.997723067f, (float16_t)0.067443920f, + (float16_t)0.997511456f, (float16_t)0.070504573f, + (float16_t)0.997290457f, (float16_t)0.073564564f, + (float16_t)0.997060070f, (float16_t)0.076623861f, + (float16_t)0.996820299f, (float16_t)0.079682438f, + (float16_t)0.996571146f, (float16_t)0.082740265f, + (float16_t)0.996312612f, (float16_t)0.085797312f, + (float16_t)0.996044701f, (float16_t)0.088853553f, + (float16_t)0.995767414f, (float16_t)0.091908956f, + (float16_t)0.995480755f, (float16_t)0.094963495f, + (float16_t)0.995184727f, (float16_t)0.098017140f, + (float16_t)0.994879331f, (float16_t)0.101069863f, + (float16_t)0.994564571f, (float16_t)0.104121634f, + (float16_t)0.994240449f, (float16_t)0.107172425f, + (float16_t)0.993906970f, (float16_t)0.110222207f, + (float16_t)0.993564136f, (float16_t)0.113270952f, + (float16_t)0.993211949f, (float16_t)0.116318631f, + (float16_t)0.992850414f, (float16_t)0.119365215f, + (float16_t)0.992479535f, (float16_t)0.122410675f, + (float16_t)0.992099313f, (float16_t)0.125454983f, + (float16_t)0.991709754f, (float16_t)0.128498111f, + (float16_t)0.991310860f, (float16_t)0.131540029f, + (float16_t)0.990902635f, (float16_t)0.134580709f, + (float16_t)0.990485084f, (float16_t)0.137620122f, + (float16_t)0.990058210f, (float16_t)0.140658239f, + (float16_t)0.989622017f, (float16_t)0.143695033f, + (float16_t)0.989176510f, (float16_t)0.146730474f, + (float16_t)0.988721692f, (float16_t)0.149764535f, + (float16_t)0.988257568f, (float16_t)0.152797185f, + (float16_t)0.987784142f, (float16_t)0.155828398f, + (float16_t)0.987301418f, (float16_t)0.158858143f, + (float16_t)0.986809402f, (float16_t)0.161886394f, + (float16_t)0.986308097f, (float16_t)0.164913120f, + (float16_t)0.985797509f, (float16_t)0.167938295f, + (float16_t)0.985277642f, (float16_t)0.170961889f, + (float16_t)0.984748502f, (float16_t)0.173983873f, + (float16_t)0.984210092f, (float16_t)0.177004220f, + (float16_t)0.983662419f, (float16_t)0.180022901f, + (float16_t)0.983105487f, (float16_t)0.183039888f, + (float16_t)0.982539302f, (float16_t)0.186055152f, + (float16_t)0.981963869f, (float16_t)0.189068664f, + (float16_t)0.981379193f, (float16_t)0.192080397f, + (float16_t)0.980785280f, (float16_t)0.195090322f, + (float16_t)0.980182136f, (float16_t)0.198098411f, + (float16_t)0.979569766f, (float16_t)0.201104635f, + (float16_t)0.978948175f, (float16_t)0.204108966f, + (float16_t)0.978317371f, (float16_t)0.207111376f, + (float16_t)0.977677358f, (float16_t)0.210111837f, + (float16_t)0.977028143f, (float16_t)0.213110320f, + (float16_t)0.976369731f, (float16_t)0.216106797f, + (float16_t)0.975702130f, (float16_t)0.219101240f, + (float16_t)0.975025345f, (float16_t)0.222093621f, + (float16_t)0.974339383f, (float16_t)0.225083911f, + (float16_t)0.973644250f, (float16_t)0.228072083f, + (float16_t)0.972939952f, (float16_t)0.231058108f, + (float16_t)0.972226497f, (float16_t)0.234041959f, + (float16_t)0.971503891f, (float16_t)0.237023606f, + (float16_t)0.970772141f, (float16_t)0.240003022f, + (float16_t)0.970031253f, (float16_t)0.242980180f, + (float16_t)0.969281235f, (float16_t)0.245955050f, + (float16_t)0.968522094f, (float16_t)0.248927606f, + (float16_t)0.967753837f, (float16_t)0.251897818f, + (float16_t)0.966976471f, (float16_t)0.254865660f, + (float16_t)0.966190003f, (float16_t)0.257831102f, + (float16_t)0.965394442f, (float16_t)0.260794118f, + (float16_t)0.964589793f, (float16_t)0.263754679f, + (float16_t)0.963776066f, (float16_t)0.266712757f, + (float16_t)0.962953267f, (float16_t)0.269668326f, + (float16_t)0.962121404f, (float16_t)0.272621355f, + (float16_t)0.961280486f, (float16_t)0.275571819f, + (float16_t)0.960430519f, (float16_t)0.278519689f, + (float16_t)0.959571513f, (float16_t)0.281464938f, + (float16_t)0.958703475f, (float16_t)0.284407537f, + (float16_t)0.957826413f, (float16_t)0.287347460f, + (float16_t)0.956940336f, (float16_t)0.290284677f, + (float16_t)0.956045251f, (float16_t)0.293219163f, + (float16_t)0.955141168f, (float16_t)0.296150888f, + (float16_t)0.954228095f, (float16_t)0.299079826f, + (float16_t)0.953306040f, (float16_t)0.302005949f, + (float16_t)0.952375013f, (float16_t)0.304929230f, + (float16_t)0.951435021f, (float16_t)0.307849640f, + (float16_t)0.950486074f, (float16_t)0.310767153f, + (float16_t)0.949528181f, (float16_t)0.313681740f, + (float16_t)0.948561350f, (float16_t)0.316593376f, + (float16_t)0.947585591f, (float16_t)0.319502031f, + (float16_t)0.946600913f, (float16_t)0.322407679f, + (float16_t)0.945607325f, (float16_t)0.325310292f, + (float16_t)0.944604837f, (float16_t)0.328209844f, + (float16_t)0.943593458f, (float16_t)0.331106306f, + (float16_t)0.942573198f, (float16_t)0.333999651f, + (float16_t)0.941544065f, (float16_t)0.336889853f, + (float16_t)0.940506071f, (float16_t)0.339776884f, + (float16_t)0.939459224f, (float16_t)0.342660717f, + (float16_t)0.938403534f, (float16_t)0.345541325f, + (float16_t)0.937339012f, (float16_t)0.348418680f, + (float16_t)0.936265667f, (float16_t)0.351292756f, + (float16_t)0.935183510f, (float16_t)0.354163525f, + (float16_t)0.934092550f, (float16_t)0.357030961f, + (float16_t)0.932992799f, (float16_t)0.359895037f, + (float16_t)0.931884266f, (float16_t)0.362755724f, + (float16_t)0.930766961f, (float16_t)0.365612998f, + (float16_t)0.929640896f, (float16_t)0.368466830f, + (float16_t)0.928506080f, (float16_t)0.371317194f, + (float16_t)0.927362526f, (float16_t)0.374164063f, + (float16_t)0.926210242f, (float16_t)0.377007410f, + (float16_t)0.925049241f, (float16_t)0.379847209f, + (float16_t)0.923879533f, (float16_t)0.382683432f, + (float16_t)0.922701128f, (float16_t)0.385516054f, + (float16_t)0.921514039f, (float16_t)0.388345047f, + (float16_t)0.920318277f, (float16_t)0.391170384f, + (float16_t)0.919113852f, (float16_t)0.393992040f, + (float16_t)0.917900776f, (float16_t)0.396809987f, + (float16_t)0.916679060f, (float16_t)0.399624200f, + (float16_t)0.915448716f, (float16_t)0.402434651f, + (float16_t)0.914209756f, (float16_t)0.405241314f, + (float16_t)0.912962190f, (float16_t)0.408044163f, + (float16_t)0.911706032f, (float16_t)0.410843171f, + (float16_t)0.910441292f, (float16_t)0.413638312f, + (float16_t)0.909167983f, (float16_t)0.416429560f, + (float16_t)0.907886116f, (float16_t)0.419216888f, + (float16_t)0.906595705f, (float16_t)0.422000271f, + (float16_t)0.905296759f, (float16_t)0.424779681f, + (float16_t)0.903989293f, (float16_t)0.427555093f, + (float16_t)0.902673318f, (float16_t)0.430326481f, + (float16_t)0.901348847f, (float16_t)0.433093819f, + (float16_t)0.900015892f, (float16_t)0.435857080f, + (float16_t)0.898674466f, (float16_t)0.438616239f, + (float16_t)0.897324581f, (float16_t)0.441371269f, + (float16_t)0.895966250f, (float16_t)0.444122145f, + (float16_t)0.894599486f, (float16_t)0.446868840f, + (float16_t)0.893224301f, (float16_t)0.449611330f, + (float16_t)0.891840709f, (float16_t)0.452349587f, + (float16_t)0.890448723f, (float16_t)0.455083587f, + (float16_t)0.889048356f, (float16_t)0.457813304f, + (float16_t)0.887639620f, (float16_t)0.460538711f, + (float16_t)0.886222530f, (float16_t)0.463259784f, + (float16_t)0.884797098f, (float16_t)0.465976496f, + (float16_t)0.883363339f, (float16_t)0.468688822f, + (float16_t)0.881921264f, (float16_t)0.471396737f, + (float16_t)0.880470889f, (float16_t)0.474100215f, + (float16_t)0.879012226f, (float16_t)0.476799230f, + (float16_t)0.877545290f, (float16_t)0.479493758f, + (float16_t)0.876070094f, (float16_t)0.482183772f, + (float16_t)0.874586652f, (float16_t)0.484869248f, + (float16_t)0.873094978f, (float16_t)0.487550160f, + (float16_t)0.871595087f, (float16_t)0.490226483f, + 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(float16_t)0.839893794f, (float16_t)0.542750785f, + (float16_t)0.838224706f, (float16_t)0.545324988f, + (float16_t)0.836547727f, (float16_t)0.547894059f, + (float16_t)0.834862875f, (float16_t)0.550457973f, + (float16_t)0.833170165f, (float16_t)0.553016706f, + (float16_t)0.831469612f, (float16_t)0.555570233f, + (float16_t)0.829761234f, (float16_t)0.558118531f, + (float16_t)0.828045045f, (float16_t)0.560661576f, + (float16_t)0.826321063f, (float16_t)0.563199344f, + (float16_t)0.824589303f, (float16_t)0.565731811f, + (float16_t)0.822849781f, (float16_t)0.568258953f, + (float16_t)0.821102515f, (float16_t)0.570780746f, + (float16_t)0.819347520f, (float16_t)0.573297167f, + (float16_t)0.817584813f, (float16_t)0.575808191f, + (float16_t)0.815814411f, (float16_t)0.578313796f, + (float16_t)0.814036330f, (float16_t)0.580813958f, + (float16_t)0.812250587f, (float16_t)0.583308653f, + (float16_t)0.810457198f, (float16_t)0.585797857f, + (float16_t)0.808656182f, (float16_t)0.588281548f, + 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(float16_t)0.919113852f, (float16_t)-0.393992040f, + (float16_t)0.920318277f, (float16_t)-0.391170384f, + (float16_t)0.921514039f, (float16_t)-0.388345047f, + (float16_t)0.922701128f, (float16_t)-0.385516054f, + (float16_t)0.923879533f, (float16_t)-0.382683432f, + (float16_t)0.925049241f, (float16_t)-0.379847209f, + (float16_t)0.926210242f, (float16_t)-0.377007410f, + (float16_t)0.927362526f, (float16_t)-0.374164063f, + (float16_t)0.928506080f, (float16_t)-0.371317194f, + (float16_t)0.929640896f, (float16_t)-0.368466830f, + (float16_t)0.930766961f, (float16_t)-0.365612998f, + (float16_t)0.931884266f, (float16_t)-0.362755724f, + (float16_t)0.932992799f, (float16_t)-0.359895037f, + (float16_t)0.934092550f, (float16_t)-0.357030961f, + (float16_t)0.935183510f, (float16_t)-0.354163525f, + (float16_t)0.936265667f, (float16_t)-0.351292756f, + (float16_t)0.937339012f, (float16_t)-0.348418680f, + (float16_t)0.938403534f, (float16_t)-0.345541325f, + (float16_t)0.939459224f, (float16_t)-0.342660717f, + (float16_t)0.940506071f, (float16_t)-0.339776884f, + (float16_t)0.941544065f, (float16_t)-0.336889853f, + (float16_t)0.942573198f, (float16_t)-0.333999651f, + (float16_t)0.943593458f, (float16_t)-0.331106306f, + (float16_t)0.944604837f, (float16_t)-0.328209844f, + (float16_t)0.945607325f, (float16_t)-0.325310292f, + (float16_t)0.946600913f, (float16_t)-0.322407679f, + (float16_t)0.947585591f, (float16_t)-0.319502031f, + (float16_t)0.948561350f, (float16_t)-0.316593376f, + (float16_t)0.949528181f, (float16_t)-0.313681740f, + (float16_t)0.950486074f, (float16_t)-0.310767153f, + (float16_t)0.951435021f, (float16_t)-0.307849640f, + (float16_t)0.952375013f, (float16_t)-0.304929230f, + (float16_t)0.953306040f, (float16_t)-0.302005949f, + (float16_t)0.954228095f, (float16_t)-0.299079826f, + (float16_t)0.955141168f, (float16_t)-0.296150888f, + (float16_t)0.956045251f, (float16_t)-0.293219163f, + (float16_t)0.956940336f, (float16_t)-0.290284677f, + (float16_t)0.957826413f, (float16_t)-0.287347460f, + (float16_t)0.958703475f, (float16_t)-0.284407537f, + (float16_t)0.959571513f, (float16_t)-0.281464938f, + (float16_t)0.960430519f, (float16_t)-0.278519689f, + (float16_t)0.961280486f, (float16_t)-0.275571819f, + (float16_t)0.962121404f, (float16_t)-0.272621355f, + (float16_t)0.962953267f, (float16_t)-0.269668326f, + (float16_t)0.963776066f, (float16_t)-0.266712757f, + (float16_t)0.964589793f, (float16_t)-0.263754679f, + (float16_t)0.965394442f, (float16_t)-0.260794118f, + (float16_t)0.966190003f, (float16_t)-0.257831102f, + (float16_t)0.966976471f, (float16_t)-0.254865660f, + (float16_t)0.967753837f, (float16_t)-0.251897818f, + (float16_t)0.968522094f, (float16_t)-0.248927606f, + (float16_t)0.969281235f, (float16_t)-0.245955050f, + (float16_t)0.970031253f, (float16_t)-0.242980180f, + (float16_t)0.970772141f, (float16_t)-0.240003022f, + (float16_t)0.971503891f, (float16_t)-0.237023606f, + (float16_t)0.972226497f, (float16_t)-0.234041959f, + (float16_t)0.972939952f, (float16_t)-0.231058108f, + (float16_t)0.973644250f, (float16_t)-0.228072083f, + (float16_t)0.974339383f, (float16_t)-0.225083911f, + (float16_t)0.975025345f, (float16_t)-0.222093621f, + (float16_t)0.975702130f, (float16_t)-0.219101240f, + (float16_t)0.976369731f, (float16_t)-0.216106797f, + (float16_t)0.977028143f, (float16_t)-0.213110320f, + (float16_t)0.977677358f, (float16_t)-0.210111837f, + (float16_t)0.978317371f, (float16_t)-0.207111376f, + (float16_t)0.978948175f, (float16_t)-0.204108966f, + (float16_t)0.979569766f, (float16_t)-0.201104635f, + (float16_t)0.980182136f, (float16_t)-0.198098411f, + (float16_t)0.980785280f, (float16_t)-0.195090322f, + (float16_t)0.981379193f, (float16_t)-0.192080397f, + (float16_t)0.981963869f, (float16_t)-0.189068664f, + (float16_t)0.982539302f, (float16_t)-0.186055152f, + (float16_t)0.983105487f, (float16_t)-0.183039888f, + (float16_t)0.983662419f, (float16_t)-0.180022901f, + (float16_t)0.984210092f, (float16_t)-0.177004220f, + (float16_t)0.984748502f, (float16_t)-0.173983873f, + (float16_t)0.985277642f, (float16_t)-0.170961889f, + (float16_t)0.985797509f, (float16_t)-0.167938295f, + (float16_t)0.986308097f, (float16_t)-0.164913120f, + (float16_t)0.986809402f, (float16_t)-0.161886394f, + (float16_t)0.987301418f, (float16_t)-0.158858143f, + (float16_t)0.987784142f, (float16_t)-0.155828398f, + (float16_t)0.988257568f, (float16_t)-0.152797185f, + (float16_t)0.988721692f, (float16_t)-0.149764535f, + (float16_t)0.989176510f, (float16_t)-0.146730474f, + (float16_t)0.989622017f, (float16_t)-0.143695033f, + (float16_t)0.990058210f, (float16_t)-0.140658239f, + (float16_t)0.990485084f, (float16_t)-0.137620122f, + (float16_t)0.990902635f, (float16_t)-0.134580709f, + (float16_t)0.991310860f, (float16_t)-0.131540029f, + (float16_t)0.991709754f, (float16_t)-0.128498111f, + (float16_t)0.992099313f, (float16_t)-0.125454983f, + (float16_t)0.992479535f, (float16_t)-0.122410675f, + (float16_t)0.992850414f, (float16_t)-0.119365215f, + (float16_t)0.993211949f, (float16_t)-0.116318631f, + (float16_t)0.993564136f, (float16_t)-0.113270952f, + (float16_t)0.993906970f, (float16_t)-0.110222207f, + (float16_t)0.994240449f, (float16_t)-0.107172425f, + (float16_t)0.994564571f, (float16_t)-0.104121634f, + (float16_t)0.994879331f, (float16_t)-0.101069863f, + (float16_t)0.995184727f, (float16_t)-0.098017140f, + (float16_t)0.995480755f, (float16_t)-0.094963495f, + (float16_t)0.995767414f, (float16_t)-0.091908956f, + (float16_t)0.996044701f, (float16_t)-0.088853553f, + (float16_t)0.996312612f, (float16_t)-0.085797312f, + (float16_t)0.996571146f, (float16_t)-0.082740265f, + (float16_t)0.996820299f, (float16_t)-0.079682438f, + (float16_t)0.997060070f, (float16_t)-0.076623861f, + (float16_t)0.997290457f, (float16_t)-0.073564564f, + (float16_t)0.997511456f, (float16_t)-0.070504573f, + (float16_t)0.997723067f, (float16_t)-0.067443920f, + (float16_t)0.997925286f, (float16_t)-0.064382631f, + (float16_t)0.998118113f, (float16_t)-0.061320736f, + (float16_t)0.998301545f, (float16_t)-0.058258265f, + (float16_t)0.998475581f, (float16_t)-0.055195244f, + (float16_t)0.998640218f, (float16_t)-0.052131705f, + (float16_t)0.998795456f, (float16_t)-0.049067674f, + (float16_t)0.998941293f, (float16_t)-0.046003182f, + (float16_t)0.999077728f, (float16_t)-0.042938257f, + (float16_t)0.999204759f, (float16_t)-0.039872928f, + (float16_t)0.999322385f, (float16_t)-0.036807223f, + (float16_t)0.999430605f, (float16_t)-0.033741172f, + (float16_t)0.999529418f, (float16_t)-0.030674803f, + (float16_t)0.999618822f, (float16_t)-0.027608146f, + (float16_t)0.999698819f, (float16_t)-0.024541229f, + (float16_t)0.999769405f, (float16_t)-0.021474080f, + (float16_t)0.999830582f, (float16_t)-0.018406730f, + (float16_t)0.999882347f, (float16_t)-0.015339206f, + (float16_t)0.999924702f, (float16_t)-0.012271538f, + (float16_t)0.999957645f, (float16_t)-0.009203755f, + (float16_t)0.999981175f, (float16_t)-0.006135885f, + (float16_t)0.999995294f, (float16_t)-0.003067957f +}; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_F16_4096) + +/** +* \par +* Example code for Floating-point Twiddle factors Generation: +* \par +* 
for(i = 0; i< N/; i++)
+* {
+* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par +* where N = 4096 and PI = 3.14159265358979 +* \par +* Cos and Sin values are in interleaved fashion +* +*/ +const float16_t twiddleCoefF16_4096[8192] = { + (float16_t)1.000000000f, (float16_t)0.000000000f, + (float16_t)0.999998823f, (float16_t)0.001533980f, + (float16_t)0.999995294f, (float16_t)0.003067957f, + (float16_t)0.999989411f, (float16_t)0.004601926f, + (float16_t)0.999981175f, (float16_t)0.006135885f, + (float16_t)0.999970586f, (float16_t)0.007669829f, + (float16_t)0.999957645f, (float16_t)0.009203755f, + (float16_t)0.999942350f, (float16_t)0.010737659f, + (float16_t)0.999924702f, (float16_t)0.012271538f, + (float16_t)0.999904701f, (float16_t)0.013805389f, + (float16_t)0.999882347f, (float16_t)0.015339206f, + (float16_t)0.999857641f, (float16_t)0.016872988f, + (float16_t)0.999830582f, (float16_t)0.018406730f, + (float16_t)0.999801170f, (float16_t)0.019940429f, + (float16_t)0.999769405f, (float16_t)0.021474080f, + (float16_t)0.999735288f, (float16_t)0.023007681f, + (float16_t)0.999698819f, (float16_t)0.024541229f, + (float16_t)0.999659997f, (float16_t)0.026074718f, + (float16_t)0.999618822f, (float16_t)0.027608146f, + (float16_t)0.999575296f, (float16_t)0.029141509f, + (float16_t)0.999529418f, (float16_t)0.030674803f, + (float16_t)0.999481187f, (float16_t)0.032208025f, + (float16_t)0.999430605f, (float16_t)0.033741172f, + (float16_t)0.999377670f, (float16_t)0.035274239f, + (float16_t)0.999322385f, (float16_t)0.036807223f, + (float16_t)0.999264747f, (float16_t)0.038340120f, + (float16_t)0.999204759f, (float16_t)0.039872928f, + (float16_t)0.999142419f, (float16_t)0.041405641f, + (float16_t)0.999077728f, (float16_t)0.042938257f, + (float16_t)0.999010686f, (float16_t)0.044470772f, + (float16_t)0.998941293f, (float16_t)0.046003182f, + (float16_t)0.998869550f, (float16_t)0.047535484f, + (float16_t)0.998795456f, (float16_t)0.049067674f, + (float16_t)0.998719012f, (float16_t)0.050599749f, + (float16_t)0.998640218f, (float16_t)0.052131705f, + (float16_t)0.998559074f, (float16_t)0.053663538f, + (float16_t)0.998475581f, (float16_t)0.055195244f, + (float16_t)0.998389737f, (float16_t)0.056726821f, + (float16_t)0.998301545f, (float16_t)0.058258265f, + (float16_t)0.998211003f, (float16_t)0.059789571f, + (float16_t)0.998118113f, (float16_t)0.061320736f, + (float16_t)0.998022874f, (float16_t)0.062851758f, + (float16_t)0.997925286f, (float16_t)0.064382631f, + (float16_t)0.997825350f, (float16_t)0.065913353f, + (float16_t)0.997723067f, (float16_t)0.067443920f, + (float16_t)0.997618435f, (float16_t)0.068974328f, + (float16_t)0.997511456f, (float16_t)0.070504573f, + (float16_t)0.997402130f, (float16_t)0.072034653f, + (float16_t)0.997290457f, (float16_t)0.073564564f, + (float16_t)0.997176437f, (float16_t)0.075094301f, + (float16_t)0.997060070f, (float16_t)0.076623861f, + (float16_t)0.996941358f, (float16_t)0.078153242f, + (float16_t)0.996820299f, (float16_t)0.079682438f, + (float16_t)0.996696895f, (float16_t)0.081211447f, + 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(float16_t)-0.310767153f, + (float16_t)0.950961666f, (float16_t)-0.309308760f, + (float16_t)0.951435021f, (float16_t)-0.307849640f, + (float16_t)0.951906137f, (float16_t)-0.306389795f, + (float16_t)0.952375013f, (float16_t)-0.304929230f, + (float16_t)0.952841648f, (float16_t)-0.303467947f, + (float16_t)0.953306040f, (float16_t)-0.302005949f, + (float16_t)0.953768190f, (float16_t)-0.300543241f, + (float16_t)0.954228095f, (float16_t)-0.299079826f, + (float16_t)0.954685755f, (float16_t)-0.297615707f, + (float16_t)0.955141168f, (float16_t)-0.296150888f, + (float16_t)0.955594334f, (float16_t)-0.294685372f, + (float16_t)0.956045251f, (float16_t)-0.293219163f, + (float16_t)0.956493919f, (float16_t)-0.291752263f, + (float16_t)0.956940336f, (float16_t)-0.290284677f, + (float16_t)0.957384501f, (float16_t)-0.288816408f, + (float16_t)0.957826413f, (float16_t)-0.287347460f, + (float16_t)0.958266071f, (float16_t)-0.285877835f, + (float16_t)0.958703475f, (float16_t)-0.284407537f, + (float16_t)0.959138622f, (float16_t)-0.282936570f, + (float16_t)0.959571513f, (float16_t)-0.281464938f, + (float16_t)0.960002146f, (float16_t)-0.279992643f, + (float16_t)0.960430519f, (float16_t)-0.278519689f, + (float16_t)0.960856633f, (float16_t)-0.277046080f, + (float16_t)0.961280486f, (float16_t)-0.275571819f, + (float16_t)0.961702077f, (float16_t)-0.274096910f, + (float16_t)0.962121404f, (float16_t)-0.272621355f, + (float16_t)0.962538468f, (float16_t)-0.271145160f, + (float16_t)0.962953267f, (float16_t)-0.269668326f, + (float16_t)0.963365800f, (float16_t)-0.268190857f, + (float16_t)0.963776066f, (float16_t)-0.266712757f, + (float16_t)0.964184064f, (float16_t)-0.265234030f, + (float16_t)0.964589793f, (float16_t)-0.263754679f, + (float16_t)0.964993253f, (float16_t)-0.262274707f, + (float16_t)0.965394442f, (float16_t)-0.260794118f, + (float16_t)0.965793359f, (float16_t)-0.259312915f, + (float16_t)0.966190003f, (float16_t)-0.257831102f, + (float16_t)0.966584374f, (float16_t)-0.256348682f, + (float16_t)0.966976471f, (float16_t)-0.254865660f, + (float16_t)0.967366292f, (float16_t)-0.253382037f, + (float16_t)0.967753837f, (float16_t)-0.251897818f, + (float16_t)0.968139105f, (float16_t)-0.250413007f, + (float16_t)0.968522094f, (float16_t)-0.248927606f, + (float16_t)0.968902805f, (float16_t)-0.247441619f, + (float16_t)0.969281235f, (float16_t)-0.245955050f, + (float16_t)0.969657385f, (float16_t)-0.244467903f, + (float16_t)0.970031253f, (float16_t)-0.242980180f, + (float16_t)0.970402839f, (float16_t)-0.241491885f, + (float16_t)0.970772141f, (float16_t)-0.240003022f, + (float16_t)0.971139158f, (float16_t)-0.238513595f, + (float16_t)0.971503891f, (float16_t)-0.237023606f, + (float16_t)0.971866337f, (float16_t)-0.235533059f, + (float16_t)0.972226497f, (float16_t)-0.234041959f, + (float16_t)0.972584369f, (float16_t)-0.232550307f, + (float16_t)0.972939952f, (float16_t)-0.231058108f, + (float16_t)0.973293246f, (float16_t)-0.229565366f, + (float16_t)0.973644250f, (float16_t)-0.228072083f, + (float16_t)0.973992962f, (float16_t)-0.226578264f, + (float16_t)0.974339383f, (float16_t)-0.225083911f, + (float16_t)0.974683511f, (float16_t)-0.223589029f, + (float16_t)0.975025345f, (float16_t)-0.222093621f, + (float16_t)0.975364885f, (float16_t)-0.220597690f, + (float16_t)0.975702130f, (float16_t)-0.219101240f, + (float16_t)0.976037079f, (float16_t)-0.217604275f, + (float16_t)0.976369731f, (float16_t)-0.216106797f, + (float16_t)0.976700086f, (float16_t)-0.214608811f, + (float16_t)0.977028143f, (float16_t)-0.213110320f, + (float16_t)0.977353900f, (float16_t)-0.211611327f, + (float16_t)0.977677358f, (float16_t)-0.210111837f, + (float16_t)0.977998515f, (float16_t)-0.208611852f, + (float16_t)0.978317371f, (float16_t)-0.207111376f, + (float16_t)0.978633924f, (float16_t)-0.205610413f, + (float16_t)0.978948175f, (float16_t)-0.204108966f, + (float16_t)0.979260123f, (float16_t)-0.202607039f, + (float16_t)0.979569766f, (float16_t)-0.201104635f, + (float16_t)0.979877104f, (float16_t)-0.199601758f, + (float16_t)0.980182136f, (float16_t)-0.198098411f, + (float16_t)0.980484862f, (float16_t)-0.196594598f, + (float16_t)0.980785280f, (float16_t)-0.195090322f, + (float16_t)0.981083391f, (float16_t)-0.193585587f, + (float16_t)0.981379193f, (float16_t)-0.192080397f, + (float16_t)0.981672686f, (float16_t)-0.190574755f, + (float16_t)0.981963869f, (float16_t)-0.189068664f, + (float16_t)0.982252741f, (float16_t)-0.187562129f, + (float16_t)0.982539302f, (float16_t)-0.186055152f, + (float16_t)0.982823551f, (float16_t)-0.184547737f, + (float16_t)0.983105487f, (float16_t)-0.183039888f, + (float16_t)0.983385110f, (float16_t)-0.181531608f, + (float16_t)0.983662419f, (float16_t)-0.180022901f, + (float16_t)0.983937413f, (float16_t)-0.178513771f, + (float16_t)0.984210092f, (float16_t)-0.177004220f, + (float16_t)0.984480455f, (float16_t)-0.175494253f, + (float16_t)0.984748502f, (float16_t)-0.173983873f, + (float16_t)0.985014231f, (float16_t)-0.172473084f, + (float16_t)0.985277642f, (float16_t)-0.170961889f, + (float16_t)0.985538735f, (float16_t)-0.169450291f, + (float16_t)0.985797509f, (float16_t)-0.167938295f, + (float16_t)0.986053963f, (float16_t)-0.166425904f, + (float16_t)0.986308097f, (float16_t)-0.164913120f, + (float16_t)0.986559910f, (float16_t)-0.163399949f, + (float16_t)0.986809402f, (float16_t)-0.161886394f, + (float16_t)0.987056571f, (float16_t)-0.160372457f, + (float16_t)0.987301418f, (float16_t)-0.158858143f, + (float16_t)0.987543942f, (float16_t)-0.157343456f, + (float16_t)0.987784142f, (float16_t)-0.155828398f, + (float16_t)0.988022017f, (float16_t)-0.154312973f, + (float16_t)0.988257568f, (float16_t)-0.152797185f, + (float16_t)0.988490793f, (float16_t)-0.151281038f, + (float16_t)0.988721692f, (float16_t)-0.149764535f, + (float16_t)0.988950265f, (float16_t)-0.148247679f, + (float16_t)0.989176510f, (float16_t)-0.146730474f, + (float16_t)0.989400428f, (float16_t)-0.145212925f, + (float16_t)0.989622017f, (float16_t)-0.143695033f, + (float16_t)0.989841278f, (float16_t)-0.142176804f, + (float16_t)0.990058210f, (float16_t)-0.140658239f, + (float16_t)0.990272812f, (float16_t)-0.139139344f, + (float16_t)0.990485084f, (float16_t)-0.137620122f, + (float16_t)0.990695025f, (float16_t)-0.136100575f, + (float16_t)0.990902635f, (float16_t)-0.134580709f, + (float16_t)0.991107914f, (float16_t)-0.133060525f, + (float16_t)0.991310860f, (float16_t)-0.131540029f, + (float16_t)0.991511473f, (float16_t)-0.130019223f, + (float16_t)0.991709754f, (float16_t)-0.128498111f, + (float16_t)0.991905700f, (float16_t)-0.126976696f, + (float16_t)0.992099313f, (float16_t)-0.125454983f, + (float16_t)0.992290591f, (float16_t)-0.123932975f, + (float16_t)0.992479535f, (float16_t)-0.122410675f, + (float16_t)0.992666142f, (float16_t)-0.120888087f, + (float16_t)0.992850414f, (float16_t)-0.119365215f, + (float16_t)0.993032350f, (float16_t)-0.117842062f, + (float16_t)0.993211949f, (float16_t)-0.116318631f, + (float16_t)0.993389211f, (float16_t)-0.114794927f, + (float16_t)0.993564136f, (float16_t)-0.113270952f, + (float16_t)0.993736722f, (float16_t)-0.111746711f, + (float16_t)0.993906970f, (float16_t)-0.110222207f, + (float16_t)0.994074879f, (float16_t)-0.108697444f, + (float16_t)0.994240449f, (float16_t)-0.107172425f, + (float16_t)0.994403680f, (float16_t)-0.105647154f, + (float16_t)0.994564571f, (float16_t)-0.104121634f, + (float16_t)0.994723121f, (float16_t)-0.102595869f, + (float16_t)0.994879331f, (float16_t)-0.101069863f, + (float16_t)0.995033199f, (float16_t)-0.099543619f, + (float16_t)0.995184727f, (float16_t)-0.098017140f, + (float16_t)0.995333912f, (float16_t)-0.096490431f, + (float16_t)0.995480755f, (float16_t)-0.094963495f, + (float16_t)0.995625256f, (float16_t)-0.093436336f, + (float16_t)0.995767414f, (float16_t)-0.091908956f, + (float16_t)0.995907229f, (float16_t)-0.090381361f, + (float16_t)0.996044701f, (float16_t)-0.088853553f, + (float16_t)0.996179829f, (float16_t)-0.087325535f, + (float16_t)0.996312612f, (float16_t)-0.085797312f, + (float16_t)0.996443051f, (float16_t)-0.084268888f, + (float16_t)0.996571146f, (float16_t)-0.082740265f, + (float16_t)0.996696895f, (float16_t)-0.081211447f, + (float16_t)0.996820299f, (float16_t)-0.079682438f, + (float16_t)0.996941358f, (float16_t)-0.078153242f, + (float16_t)0.997060070f, (float16_t)-0.076623861f, + (float16_t)0.997176437f, (float16_t)-0.075094301f, + (float16_t)0.997290457f, (float16_t)-0.073564564f, + (float16_t)0.997402130f, (float16_t)-0.072034653f, + (float16_t)0.997511456f, (float16_t)-0.070504573f, + (float16_t)0.997618435f, (float16_t)-0.068974328f, + (float16_t)0.997723067f, (float16_t)-0.067443920f, + (float16_t)0.997825350f, (float16_t)-0.065913353f, + (float16_t)0.997925286f, (float16_t)-0.064382631f, + (float16_t)0.998022874f, (float16_t)-0.062851758f, + (float16_t)0.998118113f, (float16_t)-0.061320736f, + (float16_t)0.998211003f, (float16_t)-0.059789571f, + (float16_t)0.998301545f, (float16_t)-0.058258265f, + (float16_t)0.998389737f, (float16_t)-0.056726821f, + (float16_t)0.998475581f, (float16_t)-0.055195244f, + (float16_t)0.998559074f, (float16_t)-0.053663538f, + (float16_t)0.998640218f, (float16_t)-0.052131705f, + (float16_t)0.998719012f, (float16_t)-0.050599749f, + (float16_t)0.998795456f, (float16_t)-0.049067674f, + (float16_t)0.998869550f, (float16_t)-0.047535484f, + (float16_t)0.998941293f, (float16_t)-0.046003182f, + (float16_t)0.999010686f, (float16_t)-0.044470772f, + (float16_t)0.999077728f, (float16_t)-0.042938257f, + (float16_t)0.999142419f, (float16_t)-0.041405641f, + (float16_t)0.999204759f, (float16_t)-0.039872928f, + (float16_t)0.999264747f, (float16_t)-0.038340120f, + (float16_t)0.999322385f, (float16_t)-0.036807223f, + (float16_t)0.999377670f, (float16_t)-0.035274239f, + (float16_t)0.999430605f, (float16_t)-0.033741172f, + (float16_t)0.999481187f, (float16_t)-0.032208025f, + (float16_t)0.999529418f, (float16_t)-0.030674803f, + (float16_t)0.999575296f, (float16_t)-0.029141509f, + (float16_t)0.999618822f, (float16_t)-0.027608146f, + (float16_t)0.999659997f, (float16_t)-0.026074718f, + (float16_t)0.999698819f, (float16_t)-0.024541229f, + (float16_t)0.999735288f, (float16_t)-0.023007681f, + (float16_t)0.999769405f, (float16_t)-0.021474080f, + (float16_t)0.999801170f, (float16_t)-0.019940429f, + (float16_t)0.999830582f, (float16_t)-0.018406730f, + (float16_t)0.999857641f, (float16_t)-0.016872988f, + (float16_t)0.999882347f, (float16_t)-0.015339206f, + (float16_t)0.999904701f, (float16_t)-0.013805389f, + (float16_t)0.999924702f, (float16_t)-0.012271538f, + (float16_t)0.999942350f, (float16_t)-0.010737659f, + (float16_t)0.999957645f, (float16_t)-0.009203755f, + (float16_t)0.999970586f, (float16_t)-0.007669829f, + (float16_t)0.999981175f, (float16_t)-0.006135885f, + (float16_t)0.999989411f, (float16_t)-0.004601926f, + (float16_t)0.999995294f, (float16_t)-0.003067957f, + (float16_t)0.999998823f, (float16_t)-0.001533980f +}; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F16_32) +/** + @par + Example code for Floating-point RFFT Twiddle factors Generation: + @par + 
TW = exp(pi/2*i-2*pi*i*[0:L/2-1]/L).'
+ @par + Real and Imag values are in interleaved fashion +*/ +const float16_t twiddleCoefF16_rfft_32[32] = { + (float16_t)0.000000000f, (float16_t)1.000000000f, + (float16_t)0.195090322f, (float16_t)0.980785280f, + (float16_t)0.382683432f, (float16_t)0.923879533f, + (float16_t)0.555570233f, (float16_t)0.831469612f, + (float16_t)0.707106781f, (float16_t)0.707106781f, + (float16_t)0.831469612f, (float16_t)0.555570233f, + (float16_t)0.923879533f, (float16_t)0.382683432f, + (float16_t)0.980785280f, (float16_t)0.195090322f, + (float16_t)1.000000000f, (float16_t)0.000000000f, + (float16_t)0.980785280f, (float16_t)-0.195090322f, + (float16_t)0.923879533f, (float16_t)-0.382683432f, + (float16_t)0.831469612f, (float16_t)-0.555570233f, + (float16_t)0.707106781f, (float16_t)-0.707106781f, + (float16_t)0.555570233f, (float16_t)-0.831469612f, + (float16_t)0.382683432f, (float16_t)-0.923879533f, + (float16_t)0.195090322f, (float16_t)-0.980785280f +}; +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F16_64) +const float16_t twiddleCoefF16_rfft_64[64] = { + (float16_t)0.000000000000000f, (float16_t)1.000000000000000f, + (float16_t)0.098017140329561f, (float16_t)0.995184726672197f, + (float16_t)0.195090322016128f, (float16_t)0.980785280403230f, + (float16_t)0.290284677254462f, (float16_t)0.956940335732209f, + (float16_t)0.382683432365090f, (float16_t)0.923879532511287f, + (float16_t)0.471396736825998f, (float16_t)0.881921264348355f, + (float16_t)0.555570233019602f, (float16_t)0.831469612302545f, + (float16_t)0.634393284163645f, (float16_t)0.773010453362737f, + (float16_t)0.707106781186547f, (float16_t)0.707106781186548f, + (float16_t)0.773010453362737f, (float16_t)0.634393284163645f, + (float16_t)0.831469612302545f, (float16_t)0.555570233019602f, + (float16_t)0.881921264348355f, (float16_t)0.471396736825998f, + (float16_t)0.923879532511287f, (float16_t)0.382683432365090f, + (float16_t)0.956940335732209f, (float16_t)0.290284677254462f, + (float16_t)0.980785280403230f, (float16_t)0.195090322016128f, + (float16_t)0.995184726672197f, (float16_t)0.098017140329561f, + (float16_t)1.000000000000000f, (float16_t)0.000000000000000f, + (float16_t)0.995184726672197f, (float16_t)-0.098017140329561f, + (float16_t)0.980785280403230f, (float16_t)-0.195090322016128f, + (float16_t)0.956940335732209f, (float16_t)-0.290284677254462f, + (float16_t)0.923879532511287f, (float16_t)-0.382683432365090f, + (float16_t)0.881921264348355f, (float16_t)-0.471396736825998f, + (float16_t)0.831469612302545f, (float16_t)-0.555570233019602f, + (float16_t)0.773010453362737f, (float16_t)-0.634393284163645f, + (float16_t)0.707106781186548f, (float16_t)-0.707106781186547f, + (float16_t)0.634393284163645f, (float16_t)-0.773010453362737f, + (float16_t)0.555570233019602f, (float16_t)-0.831469612302545f, + (float16_t)0.471396736825998f, (float16_t)-0.881921264348355f, + (float16_t)0.382683432365090f, (float16_t)-0.923879532511287f, + (float16_t)0.290284677254462f, (float16_t)-0.956940335732209f, + (float16_t)0.195090322016129f, (float16_t)-0.980785280403230f, + (float16_t)0.098017140329561f, (float16_t)-0.995184726672197f +}; +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F16_128) +const float16_t twiddleCoefF16_rfft_128[128] = { + (float16_t)0.000000000f, (float16_t)1.000000000f, + (float16_t)0.049067674f, (float16_t)0.998795456f, + (float16_t)0.098017140f, (float16_t)0.995184727f, + (float16_t)0.146730474f, (float16_t)0.989176510f, + (float16_t)0.195090322f, (float16_t)0.980785280f, + (float16_t)0.242980180f, (float16_t)0.970031253f, + (float16_t)0.290284677f, (float16_t)0.956940336f, + (float16_t)0.336889853f, (float16_t)0.941544065f, + (float16_t)0.382683432f, (float16_t)0.923879533f, + (float16_t)0.427555093f, (float16_t)0.903989293f, + (float16_t)0.471396737f, (float16_t)0.881921264f, + (float16_t)0.514102744f, (float16_t)0.857728610f, + (float16_t)0.555570233f, (float16_t)0.831469612f, + (float16_t)0.595699304f, (float16_t)0.803207531f, + (float16_t)0.634393284f, (float16_t)0.773010453f, + (float16_t)0.671558955f, (float16_t)0.740951125f, + (float16_t)0.707106781f, (float16_t)0.707106781f, + (float16_t)0.740951125f, (float16_t)0.671558955f, + (float16_t)0.773010453f, (float16_t)0.634393284f, + (float16_t)0.803207531f, (float16_t)0.595699304f, + (float16_t)0.831469612f, (float16_t)0.555570233f, + (float16_t)0.857728610f, (float16_t)0.514102744f, + (float16_t)0.881921264f, (float16_t)0.471396737f, + (float16_t)0.903989293f, (float16_t)0.427555093f, + (float16_t)0.923879533f, (float16_t)0.382683432f, + (float16_t)0.941544065f, (float16_t)0.336889853f, + (float16_t)0.956940336f, (float16_t)0.290284677f, + (float16_t)0.970031253f, (float16_t)0.242980180f, + (float16_t)0.980785280f, (float16_t)0.195090322f, + (float16_t)0.989176510f, (float16_t)0.146730474f, + (float16_t)0.995184727f, (float16_t)0.098017140f, + (float16_t)0.998795456f, (float16_t)0.049067674f, + (float16_t)1.000000000f, (float16_t)0.000000000f, + (float16_t)0.998795456f, (float16_t)-0.049067674f, + (float16_t)0.995184727f, (float16_t)-0.098017140f, + (float16_t)0.989176510f, (float16_t)-0.146730474f, + (float16_t)0.980785280f, (float16_t)-0.195090322f, + (float16_t)0.970031253f, (float16_t)-0.242980180f, + (float16_t)0.956940336f, (float16_t)-0.290284677f, + (float16_t)0.941544065f, (float16_t)-0.336889853f, + (float16_t)0.923879533f, (float16_t)-0.382683432f, + (float16_t)0.903989293f, (float16_t)-0.427555093f, + (float16_t)0.881921264f, (float16_t)-0.471396737f, + (float16_t)0.857728610f, (float16_t)-0.514102744f, + (float16_t)0.831469612f, (float16_t)-0.555570233f, + (float16_t)0.803207531f, (float16_t)-0.595699304f, + (float16_t)0.773010453f, (float16_t)-0.634393284f, + (float16_t)0.740951125f, (float16_t)-0.671558955f, + (float16_t)0.707106781f, (float16_t)-0.707106781f, + (float16_t)0.671558955f, (float16_t)-0.740951125f, + (float16_t)0.634393284f, (float16_t)-0.773010453f, + (float16_t)0.595699304f, (float16_t)-0.803207531f, + (float16_t)0.555570233f, (float16_t)-0.831469612f, + (float16_t)0.514102744f, (float16_t)-0.857728610f, + (float16_t)0.471396737f, (float16_t)-0.881921264f, + (float16_t)0.427555093f, (float16_t)-0.903989293f, + (float16_t)0.382683432f, (float16_t)-0.923879533f, + (float16_t)0.336889853f, (float16_t)-0.941544065f, + (float16_t)0.290284677f, (float16_t)-0.956940336f, + (float16_t)0.242980180f, (float16_t)-0.970031253f, + (float16_t)0.195090322f, (float16_t)-0.980785280f, + (float16_t)0.146730474f, (float16_t)-0.989176510f, + (float16_t)0.098017140f, (float16_t)-0.995184727f, + (float16_t)0.049067674f, (float16_t)-0.998795456f +}; +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F16_256) +const float16_t twiddleCoefF16_rfft_256[256] = { + (float16_t)0.000000000f, (float16_t)1.000000000f, + (float16_t)0.024541229f, (float16_t)0.999698819f, + (float16_t)0.049067674f, (float16_t)0.998795456f, + (float16_t)0.073564564f, (float16_t)0.997290457f, + (float16_t)0.098017140f, (float16_t)0.995184727f, + (float16_t)0.122410675f, (float16_t)0.992479535f, + (float16_t)0.146730474f, (float16_t)0.989176510f, + (float16_t)0.170961889f, (float16_t)0.985277642f, + (float16_t)0.195090322f, (float16_t)0.980785280f, + (float16_t)0.219101240f, (float16_t)0.975702130f, + (float16_t)0.242980180f, (float16_t)0.970031253f, + (float16_t)0.266712757f, (float16_t)0.963776066f, + (float16_t)0.290284677f, (float16_t)0.956940336f, + (float16_t)0.313681740f, (float16_t)0.949528181f, + (float16_t)0.336889853f, (float16_t)0.941544065f, + (float16_t)0.359895037f, (float16_t)0.932992799f, + (float16_t)0.382683432f, (float16_t)0.923879533f, + (float16_t)0.405241314f, (float16_t)0.914209756f, + (float16_t)0.427555093f, (float16_t)0.903989293f, + (float16_t)0.449611330f, (float16_t)0.893224301f, + (float16_t)0.471396737f, (float16_t)0.881921264f, + (float16_t)0.492898192f, (float16_t)0.870086991f, + (float16_t)0.514102744f, (float16_t)0.857728610f, + (float16_t)0.534997620f, (float16_t)0.844853565f, + (float16_t)0.555570233f, (float16_t)0.831469612f, + (float16_t)0.575808191f, (float16_t)0.817584813f, + (float16_t)0.595699304f, (float16_t)0.803207531f, + (float16_t)0.615231591f, (float16_t)0.788346428f, + (float16_t)0.634393284f, (float16_t)0.773010453f, + (float16_t)0.653172843f, (float16_t)0.757208847f, + (float16_t)0.671558955f, (float16_t)0.740951125f, + (float16_t)0.689540545f, (float16_t)0.724247083f, + (float16_t)0.707106781f, (float16_t)0.707106781f, + (float16_t)0.724247083f, (float16_t)0.689540545f, + (float16_t)0.740951125f, (float16_t)0.671558955f, + (float16_t)0.757208847f, (float16_t)0.653172843f, + (float16_t)0.773010453f, (float16_t)0.634393284f, + (float16_t)0.788346428f, (float16_t)0.615231591f, + (float16_t)0.803207531f, (float16_t)0.595699304f, + (float16_t)0.817584813f, (float16_t)0.575808191f, + (float16_t)0.831469612f, (float16_t)0.555570233f, + (float16_t)0.844853565f, (float16_t)0.534997620f, + (float16_t)0.857728610f, (float16_t)0.514102744f, + (float16_t)0.870086991f, (float16_t)0.492898192f, + (float16_t)0.881921264f, (float16_t)0.471396737f, + (float16_t)0.893224301f, (float16_t)0.449611330f, + (float16_t)0.903989293f, (float16_t)0.427555093f, + (float16_t)0.914209756f, (float16_t)0.405241314f, + (float16_t)0.923879533f, (float16_t)0.382683432f, + (float16_t)0.932992799f, (float16_t)0.359895037f, + (float16_t)0.941544065f, (float16_t)0.336889853f, + (float16_t)0.949528181f, (float16_t)0.313681740f, + (float16_t)0.956940336f, (float16_t)0.290284677f, + (float16_t)0.963776066f, (float16_t)0.266712757f, + (float16_t)0.970031253f, (float16_t)0.242980180f, + (float16_t)0.975702130f, (float16_t)0.219101240f, + (float16_t)0.980785280f, (float16_t)0.195090322f, + (float16_t)0.985277642f, (float16_t)0.170961889f, + (float16_t)0.989176510f, (float16_t)0.146730474f, + (float16_t)0.992479535f, (float16_t)0.122410675f, + (float16_t)0.995184727f, (float16_t)0.098017140f, + (float16_t)0.997290457f, (float16_t)0.073564564f, + (float16_t)0.998795456f, (float16_t)0.049067674f, + (float16_t)0.999698819f, (float16_t)0.024541229f, + (float16_t)1.000000000f, (float16_t)0.000000000f, + (float16_t)0.999698819f, (float16_t)-0.024541229f, + (float16_t)0.998795456f, (float16_t)-0.049067674f, + (float16_t)0.997290457f, (float16_t)-0.073564564f, + (float16_t)0.995184727f, (float16_t)-0.098017140f, + (float16_t)0.992479535f, (float16_t)-0.122410675f, + (float16_t)0.989176510f, (float16_t)-0.146730474f, + (float16_t)0.985277642f, (float16_t)-0.170961889f, + (float16_t)0.980785280f, (float16_t)-0.195090322f, + (float16_t)0.975702130f, (float16_t)-0.219101240f, + (float16_t)0.970031253f, (float16_t)-0.242980180f, + (float16_t)0.963776066f, (float16_t)-0.266712757f, + (float16_t)0.956940336f, (float16_t)-0.290284677f, + (float16_t)0.949528181f, (float16_t)-0.313681740f, + (float16_t)0.941544065f, (float16_t)-0.336889853f, + (float16_t)0.932992799f, (float16_t)-0.359895037f, + (float16_t)0.923879533f, (float16_t)-0.382683432f, + (float16_t)0.914209756f, (float16_t)-0.405241314f, + (float16_t)0.903989293f, (float16_t)-0.427555093f, + (float16_t)0.893224301f, (float16_t)-0.449611330f, + (float16_t)0.881921264f, (float16_t)-0.471396737f, + (float16_t)0.870086991f, (float16_t)-0.492898192f, + (float16_t)0.857728610f, (float16_t)-0.514102744f, + (float16_t)0.844853565f, (float16_t)-0.534997620f, + (float16_t)0.831469612f, (float16_t)-0.555570233f, + (float16_t)0.817584813f, (float16_t)-0.575808191f, + (float16_t)0.803207531f, (float16_t)-0.595699304f, + (float16_t)0.788346428f, (float16_t)-0.615231591f, + (float16_t)0.773010453f, (float16_t)-0.634393284f, + (float16_t)0.757208847f, (float16_t)-0.653172843f, + (float16_t)0.740951125f, (float16_t)-0.671558955f, + (float16_t)0.724247083f, (float16_t)-0.689540545f, + (float16_t)0.707106781f, (float16_t)-0.707106781f, + (float16_t)0.689540545f, (float16_t)-0.724247083f, + (float16_t)0.671558955f, (float16_t)-0.740951125f, + (float16_t)0.653172843f, (float16_t)-0.757208847f, + (float16_t)0.634393284f, (float16_t)-0.773010453f, + (float16_t)0.615231591f, (float16_t)-0.788346428f, + (float16_t)0.595699304f, (float16_t)-0.803207531f, + (float16_t)0.575808191f, (float16_t)-0.817584813f, + (float16_t)0.555570233f, (float16_t)-0.831469612f, + (float16_t)0.534997620f, (float16_t)-0.844853565f, + (float16_t)0.514102744f, (float16_t)-0.857728610f, + (float16_t)0.492898192f, (float16_t)-0.870086991f, + (float16_t)0.471396737f, (float16_t)-0.881921264f, + (float16_t)0.449611330f, (float16_t)-0.893224301f, + (float16_t)0.427555093f, (float16_t)-0.903989293f, + (float16_t)0.405241314f, (float16_t)-0.914209756f, + (float16_t)0.382683432f, (float16_t)-0.923879533f, + (float16_t)0.359895037f, (float16_t)-0.932992799f, + (float16_t)0.336889853f, (float16_t)-0.941544065f, + (float16_t)0.313681740f, (float16_t)-0.949528181f, + (float16_t)0.290284677f, (float16_t)-0.956940336f, + (float16_t)0.266712757f, (float16_t)-0.963776066f, + (float16_t)0.242980180f, (float16_t)-0.970031253f, + (float16_t)0.219101240f, (float16_t)-0.975702130f, + (float16_t)0.195090322f, (float16_t)-0.980785280f, + (float16_t)0.170961889f, (float16_t)-0.985277642f, + (float16_t)0.146730474f, (float16_t)-0.989176510f, + (float16_t)0.122410675f, (float16_t)-0.992479535f, + (float16_t)0.098017140f, (float16_t)-0.995184727f, + (float16_t)0.073564564f, (float16_t)-0.997290457f, + (float16_t)0.049067674f, (float16_t)-0.998795456f, + (float16_t)0.024541229f, (float16_t)-0.999698819f +}; +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F16_512) +const float16_t twiddleCoefF16_rfft_512[512] = { + (float16_t)0.000000000f, (float16_t)1.000000000f, + (float16_t)0.012271538f, (float16_t)0.999924702f, + (float16_t)0.024541229f, (float16_t)0.999698819f, + (float16_t)0.036807223f, (float16_t)0.999322385f, + (float16_t)0.049067674f, (float16_t)0.998795456f, + (float16_t)0.061320736f, (float16_t)0.998118113f, + (float16_t)0.073564564f, (float16_t)0.997290457f, + (float16_t)0.085797312f, (float16_t)0.996312612f, + (float16_t)0.098017140f, (float16_t)0.995184727f, + (float16_t)0.110222207f, (float16_t)0.993906970f, + (float16_t)0.122410675f, (float16_t)0.992479535f, + (float16_t)0.134580709f, (float16_t)0.990902635f, + (float16_t)0.146730474f, (float16_t)0.989176510f, + (float16_t)0.158858143f, (float16_t)0.987301418f, + (float16_t)0.170961889f, (float16_t)0.985277642f, + (float16_t)0.183039888f, (float16_t)0.983105487f, + (float16_t)0.195090322f, (float16_t)0.980785280f, + (float16_t)0.207111376f, (float16_t)0.978317371f, + (float16_t)0.219101240f, (float16_t)0.975702130f, + (float16_t)0.231058108f, (float16_t)0.972939952f, + (float16_t)0.242980180f, (float16_t)0.970031253f, + (float16_t)0.254865660f, (float16_t)0.966976471f, + (float16_t)0.266712757f, (float16_t)0.963776066f, + (float16_t)0.278519689f, (float16_t)0.960430519f, + (float16_t)0.290284677f, (float16_t)0.956940336f, + (float16_t)0.302005949f, (float16_t)0.953306040f, + (float16_t)0.313681740f, (float16_t)0.949528181f, + (float16_t)0.325310292f, (float16_t)0.945607325f, + (float16_t)0.336889853f, (float16_t)0.941544065f, + (float16_t)0.348418680f, (float16_t)0.937339012f, + (float16_t)0.359895037f, (float16_t)0.932992799f, + (float16_t)0.371317194f, (float16_t)0.928506080f, + (float16_t)0.382683432f, (float16_t)0.923879533f, + (float16_t)0.393992040f, (float16_t)0.919113852f, + (float16_t)0.405241314f, (float16_t)0.914209756f, + (float16_t)0.416429560f, (float16_t)0.909167983f, + (float16_t)0.427555093f, (float16_t)0.903989293f, + (float16_t)0.438616239f, (float16_t)0.898674466f, + (float16_t)0.449611330f, (float16_t)0.893224301f, + (float16_t)0.460538711f, (float16_t)0.887639620f, + (float16_t)0.471396737f, (float16_t)0.881921264f, + (float16_t)0.482183772f, (float16_t)0.876070094f, + (float16_t)0.492898192f, (float16_t)0.870086991f, + (float16_t)0.503538384f, (float16_t)0.863972856f, + (float16_t)0.514102744f, (float16_t)0.857728610f, + (float16_t)0.524589683f, (float16_t)0.851355193f, + (float16_t)0.534997620f, (float16_t)0.844853565f, + (float16_t)0.545324988f, (float16_t)0.838224706f, + (float16_t)0.555570233f, (float16_t)0.831469612f, + (float16_t)0.565731811f, (float16_t)0.824589303f, + (float16_t)0.575808191f, (float16_t)0.817584813f, + (float16_t)0.585797857f, (float16_t)0.810457198f, + (float16_t)0.595699304f, (float16_t)0.803207531f, + (float16_t)0.605511041f, (float16_t)0.795836905f, + (float16_t)0.615231591f, (float16_t)0.788346428f, + (float16_t)0.624859488f, (float16_t)0.780737229f, + (float16_t)0.634393284f, (float16_t)0.773010453f, + (float16_t)0.643831543f, (float16_t)0.765167266f, + (float16_t)0.653172843f, (float16_t)0.757208847f, + (float16_t)0.662415778f, (float16_t)0.749136395f, + (float16_t)0.671558955f, (float16_t)0.740951125f, + (float16_t)0.680600998f, (float16_t)0.732654272f, + (float16_t)0.689540545f, (float16_t)0.724247083f, + (float16_t)0.698376249f, (float16_t)0.715730825f, + (float16_t)0.707106781f, (float16_t)0.707106781f, + (float16_t)0.715730825f, (float16_t)0.698376249f, + (float16_t)0.724247083f, (float16_t)0.689540545f, + (float16_t)0.732654272f, (float16_t)0.680600998f, + (float16_t)0.740951125f, (float16_t)0.671558955f, + (float16_t)0.749136395f, (float16_t)0.662415778f, + (float16_t)0.757208847f, (float16_t)0.653172843f, + (float16_t)0.765167266f, (float16_t)0.643831543f, + (float16_t)0.773010453f, (float16_t)0.634393284f, + (float16_t)0.780737229f, (float16_t)0.624859488f, + (float16_t)0.788346428f, (float16_t)0.615231591f, + (float16_t)0.795836905f, (float16_t)0.605511041f, + (float16_t)0.803207531f, (float16_t)0.595699304f, + (float16_t)0.810457198f, (float16_t)0.585797857f, + (float16_t)0.817584813f, (float16_t)0.575808191f, + (float16_t)0.824589303f, (float16_t)0.565731811f, + (float16_t)0.831469612f, (float16_t)0.555570233f, + (float16_t)0.838224706f, (float16_t)0.545324988f, + (float16_t)0.844853565f, (float16_t)0.534997620f, + (float16_t)0.851355193f, (float16_t)0.524589683f, + (float16_t)0.857728610f, (float16_t)0.514102744f, + (float16_t)0.863972856f, (float16_t)0.503538384f, + (float16_t)0.870086991f, (float16_t)0.492898192f, + (float16_t)0.876070094f, (float16_t)0.482183772f, + (float16_t)0.881921264f, (float16_t)0.471396737f, + (float16_t)0.887639620f, (float16_t)0.460538711f, + (float16_t)0.893224301f, (float16_t)0.449611330f, + (float16_t)0.898674466f, (float16_t)0.438616239f, + (float16_t)0.903989293f, (float16_t)0.427555093f, + (float16_t)0.909167983f, (float16_t)0.416429560f, + (float16_t)0.914209756f, (float16_t)0.405241314f, + (float16_t)0.919113852f, (float16_t)0.393992040f, + (float16_t)0.923879533f, (float16_t)0.382683432f, + (float16_t)0.928506080f, (float16_t)0.371317194f, + (float16_t)0.932992799f, (float16_t)0.359895037f, + (float16_t)0.937339012f, (float16_t)0.348418680f, + (float16_t)0.941544065f, (float16_t)0.336889853f, + (float16_t)0.945607325f, (float16_t)0.325310292f, + (float16_t)0.949528181f, (float16_t)0.313681740f, + (float16_t)0.953306040f, (float16_t)0.302005949f, + (float16_t)0.956940336f, (float16_t)0.290284677f, + (float16_t)0.960430519f, (float16_t)0.278519689f, + (float16_t)0.963776066f, (float16_t)0.266712757f, + (float16_t)0.966976471f, (float16_t)0.254865660f, + (float16_t)0.970031253f, (float16_t)0.242980180f, + (float16_t)0.972939952f, (float16_t)0.231058108f, + (float16_t)0.975702130f, (float16_t)0.219101240f, + (float16_t)0.978317371f, (float16_t)0.207111376f, + (float16_t)0.980785280f, (float16_t)0.195090322f, + (float16_t)0.983105487f, (float16_t)0.183039888f, + (float16_t)0.985277642f, (float16_t)0.170961889f, + (float16_t)0.987301418f, (float16_t)0.158858143f, + (float16_t)0.989176510f, (float16_t)0.146730474f, + (float16_t)0.990902635f, (float16_t)0.134580709f, + (float16_t)0.992479535f, (float16_t)0.122410675f, + (float16_t)0.993906970f, (float16_t)0.110222207f, + (float16_t)0.995184727f, (float16_t)0.098017140f, + (float16_t)0.996312612f, (float16_t)0.085797312f, + (float16_t)0.997290457f, (float16_t)0.073564564f, + (float16_t)0.998118113f, (float16_t)0.061320736f, + (float16_t)0.998795456f, (float16_t)0.049067674f, + (float16_t)0.999322385f, (float16_t)0.036807223f, + (float16_t)0.999698819f, (float16_t)0.024541229f, + (float16_t)0.999924702f, (float16_t)0.012271538f, + (float16_t)1.000000000f, (float16_t)0.000000000f, + (float16_t)0.999924702f, (float16_t)-0.012271538f, + (float16_t)0.999698819f, (float16_t)-0.024541229f, + (float16_t)0.999322385f, (float16_t)-0.036807223f, + (float16_t)0.998795456f, (float16_t)-0.049067674f, + (float16_t)0.998118113f, (float16_t)-0.061320736f, + (float16_t)0.997290457f, (float16_t)-0.073564564f, + (float16_t)0.996312612f, (float16_t)-0.085797312f, + (float16_t)0.995184727f, (float16_t)-0.098017140f, + (float16_t)0.993906970f, (float16_t)-0.110222207f, + (float16_t)0.992479535f, (float16_t)-0.122410675f, + (float16_t)0.990902635f, (float16_t)-0.134580709f, + (float16_t)0.989176510f, (float16_t)-0.146730474f, + (float16_t)0.987301418f, (float16_t)-0.158858143f, + (float16_t)0.985277642f, (float16_t)-0.170961889f, + (float16_t)0.983105487f, (float16_t)-0.183039888f, + (float16_t)0.980785280f, (float16_t)-0.195090322f, + (float16_t)0.978317371f, (float16_t)-0.207111376f, + (float16_t)0.975702130f, (float16_t)-0.219101240f, + (float16_t)0.972939952f, (float16_t)-0.231058108f, + (float16_t)0.970031253f, (float16_t)-0.242980180f, + (float16_t)0.966976471f, (float16_t)-0.254865660f, + (float16_t)0.963776066f, (float16_t)-0.266712757f, + (float16_t)0.960430519f, (float16_t)-0.278519689f, + (float16_t)0.956940336f, (float16_t)-0.290284677f, + (float16_t)0.953306040f, (float16_t)-0.302005949f, + (float16_t)0.949528181f, (float16_t)-0.313681740f, + (float16_t)0.945607325f, (float16_t)-0.325310292f, + (float16_t)0.941544065f, (float16_t)-0.336889853f, + (float16_t)0.937339012f, (float16_t)-0.348418680f, + (float16_t)0.932992799f, (float16_t)-0.359895037f, + (float16_t)0.928506080f, (float16_t)-0.371317194f, + (float16_t)0.923879533f, (float16_t)-0.382683432f, + (float16_t)0.919113852f, (float16_t)-0.393992040f, + (float16_t)0.914209756f, (float16_t)-0.405241314f, + (float16_t)0.909167983f, (float16_t)-0.416429560f, + (float16_t)0.903989293f, (float16_t)-0.427555093f, + (float16_t)0.898674466f, (float16_t)-0.438616239f, + (float16_t)0.893224301f, (float16_t)-0.449611330f, + (float16_t)0.887639620f, (float16_t)-0.460538711f, + (float16_t)0.881921264f, (float16_t)-0.471396737f, + (float16_t)0.876070094f, (float16_t)-0.482183772f, + (float16_t)0.870086991f, (float16_t)-0.492898192f, + (float16_t)0.863972856f, (float16_t)-0.503538384f, + (float16_t)0.857728610f, (float16_t)-0.514102744f, + (float16_t)0.851355193f, (float16_t)-0.524589683f, + (float16_t)0.844853565f, (float16_t)-0.534997620f, + (float16_t)0.838224706f, (float16_t)-0.545324988f, + (float16_t)0.831469612f, (float16_t)-0.555570233f, + (float16_t)0.824589303f, (float16_t)-0.565731811f, + (float16_t)0.817584813f, (float16_t)-0.575808191f, + (float16_t)0.810457198f, (float16_t)-0.585797857f, + (float16_t)0.803207531f, (float16_t)-0.595699304f, + (float16_t)0.795836905f, (float16_t)-0.605511041f, + (float16_t)0.788346428f, (float16_t)-0.615231591f, + (float16_t)0.780737229f, (float16_t)-0.624859488f, + (float16_t)0.773010453f, (float16_t)-0.634393284f, + (float16_t)0.765167266f, (float16_t)-0.643831543f, + (float16_t)0.757208847f, (float16_t)-0.653172843f, + (float16_t)0.749136395f, (float16_t)-0.662415778f, + (float16_t)0.740951125f, (float16_t)-0.671558955f, + (float16_t)0.732654272f, (float16_t)-0.680600998f, + (float16_t)0.724247083f, (float16_t)-0.689540545f, + (float16_t)0.715730825f, (float16_t)-0.698376249f, + (float16_t)0.707106781f, (float16_t)-0.707106781f, + (float16_t)0.698376249f, (float16_t)-0.715730825f, + (float16_t)0.689540545f, (float16_t)-0.724247083f, + (float16_t)0.680600998f, (float16_t)-0.732654272f, + (float16_t)0.671558955f, (float16_t)-0.740951125f, + (float16_t)0.662415778f, (float16_t)-0.749136395f, + (float16_t)0.653172843f, (float16_t)-0.757208847f, + (float16_t)0.643831543f, (float16_t)-0.765167266f, + (float16_t)0.634393284f, (float16_t)-0.773010453f, + (float16_t)0.624859488f, (float16_t)-0.780737229f, + (float16_t)0.615231591f, (float16_t)-0.788346428f, + (float16_t)0.605511041f, (float16_t)-0.795836905f, + (float16_t)0.595699304f, (float16_t)-0.803207531f, + (float16_t)0.585797857f, (float16_t)-0.810457198f, + (float16_t)0.575808191f, (float16_t)-0.817584813f, + (float16_t)0.565731811f, (float16_t)-0.824589303f, + (float16_t)0.555570233f, (float16_t)-0.831469612f, + (float16_t)0.545324988f, (float16_t)-0.838224706f, + (float16_t)0.534997620f, (float16_t)-0.844853565f, + (float16_t)0.524589683f, (float16_t)-0.851355193f, + (float16_t)0.514102744f, (float16_t)-0.857728610f, + (float16_t)0.503538384f, (float16_t)-0.863972856f, + (float16_t)0.492898192f, (float16_t)-0.870086991f, + (float16_t)0.482183772f, (float16_t)-0.876070094f, + (float16_t)0.471396737f, (float16_t)-0.881921264f, + (float16_t)0.460538711f, (float16_t)-0.887639620f, + (float16_t)0.449611330f, (float16_t)-0.893224301f, + (float16_t)0.438616239f, (float16_t)-0.898674466f, + (float16_t)0.427555093f, (float16_t)-0.903989293f, + (float16_t)0.416429560f, (float16_t)-0.909167983f, + (float16_t)0.405241314f, (float16_t)-0.914209756f, + (float16_t)0.393992040f, (float16_t)-0.919113852f, + (float16_t)0.382683432f, (float16_t)-0.923879533f, + (float16_t)0.371317194f, (float16_t)-0.928506080f, + (float16_t)0.359895037f, (float16_t)-0.932992799f, + (float16_t)0.348418680f, (float16_t)-0.937339012f, + (float16_t)0.336889853f, (float16_t)-0.941544065f, + (float16_t)0.325310292f, (float16_t)-0.945607325f, + (float16_t)0.313681740f, (float16_t)-0.949528181f, + (float16_t)0.302005949f, (float16_t)-0.953306040f, + (float16_t)0.290284677f, (float16_t)-0.956940336f, + (float16_t)0.278519689f, (float16_t)-0.960430519f, + (float16_t)0.266712757f, (float16_t)-0.963776066f, + (float16_t)0.254865660f, (float16_t)-0.966976471f, + (float16_t)0.242980180f, (float16_t)-0.970031253f, + (float16_t)0.231058108f, (float16_t)-0.972939952f, + (float16_t)0.219101240f, (float16_t)-0.975702130f, + (float16_t)0.207111376f, (float16_t)-0.978317371f, + (float16_t)0.195090322f, (float16_t)-0.980785280f, + (float16_t)0.183039888f, (float16_t)-0.983105487f, + (float16_t)0.170961889f, (float16_t)-0.985277642f, + (float16_t)0.158858143f, (float16_t)-0.987301418f, + (float16_t)0.146730474f, (float16_t)-0.989176510f, + (float16_t)0.134580709f, (float16_t)-0.990902635f, + (float16_t)0.122410675f, (float16_t)-0.992479535f, + (float16_t)0.110222207f, (float16_t)-0.993906970f, + (float16_t)0.098017140f, (float16_t)-0.995184727f, + (float16_t)0.085797312f, (float16_t)-0.996312612f, + (float16_t)0.073564564f, (float16_t)-0.997290457f, + (float16_t)0.061320736f, (float16_t)-0.998118113f, + (float16_t)0.049067674f, (float16_t)-0.998795456f, + (float16_t)0.036807223f, (float16_t)-0.999322385f, + (float16_t)0.024541229f, (float16_t)-0.999698819f, + (float16_t)0.012271538f, (float16_t)-0.999924702f +}; +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F16_1024) +const float16_t twiddleCoefF16_rfft_1024[1024] = { + (float16_t)0.000000000f, (float16_t)1.000000000f, + (float16_t)0.006135885f, (float16_t)0.999981175f, + (float16_t)0.012271538f, (float16_t)0.999924702f, + (float16_t)0.018406730f, (float16_t)0.999830582f, + (float16_t)0.024541229f, (float16_t)0.999698819f, + (float16_t)0.030674803f, (float16_t)0.999529418f, + (float16_t)0.036807223f, (float16_t)0.999322385f, + (float16_t)0.042938257f, (float16_t)0.999077728f, + (float16_t)0.049067674f, (float16_t)0.998795456f, + (float16_t)0.055195244f, (float16_t)0.998475581f, + (float16_t)0.061320736f, (float16_t)0.998118113f, + (float16_t)0.067443920f, (float16_t)0.997723067f, + (float16_t)0.073564564f, (float16_t)0.997290457f, + (float16_t)0.079682438f, (float16_t)0.996820299f, + (float16_t)0.085797312f, (float16_t)0.996312612f, + (float16_t)0.091908956f, (float16_t)0.995767414f, + (float16_t)0.098017140f, (float16_t)0.995184727f, + (float16_t)0.104121634f, (float16_t)0.994564571f, + (float16_t)0.110222207f, (float16_t)0.993906970f, + (float16_t)0.116318631f, (float16_t)0.993211949f, + (float16_t)0.122410675f, (float16_t)0.992479535f, + (float16_t)0.128498111f, (float16_t)0.991709754f, + (float16_t)0.134580709f, (float16_t)0.990902635f, + (float16_t)0.140658239f, (float16_t)0.990058210f, + (float16_t)0.146730474f, (float16_t)0.989176510f, + (float16_t)0.152797185f, (float16_t)0.988257568f, + (float16_t)0.158858143f, (float16_t)0.987301418f, + (float16_t)0.164913120f, (float16_t)0.986308097f, + (float16_t)0.170961889f, (float16_t)0.985277642f, + (float16_t)0.177004220f, (float16_t)0.984210092f, + (float16_t)0.183039888f, (float16_t)0.983105487f, + (float16_t)0.189068664f, (float16_t)0.981963869f, + (float16_t)0.195090322f, (float16_t)0.980785280f, + (float16_t)0.201104635f, (float16_t)0.979569766f, + (float16_t)0.207111376f, (float16_t)0.978317371f, + (float16_t)0.213110320f, (float16_t)0.977028143f, + (float16_t)0.219101240f, (float16_t)0.975702130f, + (float16_t)0.225083911f, (float16_t)0.974339383f, + (float16_t)0.231058108f, (float16_t)0.972939952f, + (float16_t)0.237023606f, (float16_t)0.971503891f, + (float16_t)0.242980180f, (float16_t)0.970031253f, + (float16_t)0.248927606f, (float16_t)0.968522094f, + (float16_t)0.254865660f, (float16_t)0.966976471f, + (float16_t)0.260794118f, (float16_t)0.965394442f, + (float16_t)0.266712757f, (float16_t)0.963776066f, + (float16_t)0.272621355f, (float16_t)0.962121404f, + (float16_t)0.278519689f, (float16_t)0.960430519f, + (float16_t)0.284407537f, (float16_t)0.958703475f, + (float16_t)0.290284677f, (float16_t)0.956940336f, + (float16_t)0.296150888f, (float16_t)0.955141168f, + (float16_t)0.302005949f, (float16_t)0.953306040f, + (float16_t)0.307849640f, (float16_t)0.951435021f, + (float16_t)0.313681740f, (float16_t)0.949528181f, + (float16_t)0.319502031f, (float16_t)0.947585591f, + (float16_t)0.325310292f, (float16_t)0.945607325f, + (float16_t)0.331106306f, (float16_t)0.943593458f, + (float16_t)0.336889853f, (float16_t)0.941544065f, + (float16_t)0.342660717f, (float16_t)0.939459224f, + (float16_t)0.348418680f, (float16_t)0.937339012f, + (float16_t)0.354163525f, (float16_t)0.935183510f, + (float16_t)0.359895037f, (float16_t)0.932992799f, + (float16_t)0.365612998f, (float16_t)0.930766961f, + (float16_t)0.371317194f, (float16_t)0.928506080f, + (float16_t)0.377007410f, (float16_t)0.926210242f, + (float16_t)0.382683432f, (float16_t)0.923879533f, + (float16_t)0.388345047f, (float16_t)0.921514039f, + (float16_t)0.393992040f, (float16_t)0.919113852f, + (float16_t)0.399624200f, (float16_t)0.916679060f, + (float16_t)0.405241314f, (float16_t)0.914209756f, + (float16_t)0.410843171f, (float16_t)0.911706032f, + (float16_t)0.416429560f, (float16_t)0.909167983f, + (float16_t)0.422000271f, (float16_t)0.906595705f, + (float16_t)0.427555093f, (float16_t)0.903989293f, + (float16_t)0.433093819f, (float16_t)0.901348847f, + (float16_t)0.438616239f, (float16_t)0.898674466f, + (float16_t)0.444122145f, (float16_t)0.895966250f, + (float16_t)0.449611330f, (float16_t)0.893224301f, + (float16_t)0.455083587f, (float16_t)0.890448723f, + (float16_t)0.460538711f, (float16_t)0.887639620f, + (float16_t)0.465976496f, (float16_t)0.884797098f, + (float16_t)0.471396737f, (float16_t)0.881921264f, + (float16_t)0.476799230f, (float16_t)0.879012226f, + (float16_t)0.482183772f, (float16_t)0.876070094f, + (float16_t)0.487550160f, (float16_t)0.873094978f, + (float16_t)0.492898192f, (float16_t)0.870086991f, + (float16_t)0.498227667f, (float16_t)0.867046246f, + (float16_t)0.503538384f, (float16_t)0.863972856f, + (float16_t)0.508830143f, (float16_t)0.860866939f, + (float16_t)0.514102744f, (float16_t)0.857728610f, + (float16_t)0.519355990f, (float16_t)0.854557988f, + (float16_t)0.524589683f, (float16_t)0.851355193f, + (float16_t)0.529803625f, (float16_t)0.848120345f, + (float16_t)0.534997620f, (float16_t)0.844853565f, + (float16_t)0.540171473f, (float16_t)0.841554977f, + (float16_t)0.545324988f, (float16_t)0.838224706f, + (float16_t)0.550457973f, (float16_t)0.834862875f, + (float16_t)0.555570233f, (float16_t)0.831469612f, + (float16_t)0.560661576f, (float16_t)0.828045045f, + (float16_t)0.565731811f, (float16_t)0.824589303f, + (float16_t)0.570780746f, (float16_t)0.821102515f, + (float16_t)0.575808191f, (float16_t)0.817584813f, + (float16_t)0.580813958f, (float16_t)0.814036330f, + (float16_t)0.585797857f, (float16_t)0.810457198f, + (float16_t)0.590759702f, (float16_t)0.806847554f, + (float16_t)0.595699304f, (float16_t)0.803207531f, + (float16_t)0.600616479f, (float16_t)0.799537269f, + (float16_t)0.605511041f, (float16_t)0.795836905f, + (float16_t)0.610382806f, (float16_t)0.792106577f, + (float16_t)0.615231591f, (float16_t)0.788346428f, + (float16_t)0.620057212f, (float16_t)0.784556597f, + (float16_t)0.624859488f, (float16_t)0.780737229f, + (float16_t)0.629638239f, (float16_t)0.776888466f, + (float16_t)0.634393284f, (float16_t)0.773010453f, + (float16_t)0.639124445f, (float16_t)0.769103338f, + (float16_t)0.643831543f, (float16_t)0.765167266f, + (float16_t)0.648514401f, (float16_t)0.761202385f, + (float16_t)0.653172843f, (float16_t)0.757208847f, + (float16_t)0.657806693f, (float16_t)0.753186799f, + (float16_t)0.662415778f, (float16_t)0.749136395f, + (float16_t)0.666999922f, (float16_t)0.745057785f, + (float16_t)0.671558955f, (float16_t)0.740951125f, + (float16_t)0.676092704f, (float16_t)0.736816569f, + (float16_t)0.680600998f, (float16_t)0.732654272f, + (float16_t)0.685083668f, (float16_t)0.728464390f, + (float16_t)0.689540545f, (float16_t)0.724247083f, + (float16_t)0.693971461f, (float16_t)0.720002508f, + (float16_t)0.698376249f, (float16_t)0.715730825f, + (float16_t)0.702754744f, (float16_t)0.711432196f, + (float16_t)0.707106781f, (float16_t)0.707106781f, + (float16_t)0.711432196f, (float16_t)0.702754744f, + (float16_t)0.715730825f, (float16_t)0.698376249f, + (float16_t)0.720002508f, (float16_t)0.693971461f, + (float16_t)0.724247083f, (float16_t)0.689540545f, + (float16_t)0.728464390f, (float16_t)0.685083668f, + (float16_t)0.732654272f, (float16_t)0.680600998f, + (float16_t)0.736816569f, (float16_t)0.676092704f, + (float16_t)0.740951125f, (float16_t)0.671558955f, + (float16_t)0.745057785f, (float16_t)0.666999922f, + (float16_t)0.749136395f, (float16_t)0.662415778f, + (float16_t)0.753186799f, (float16_t)0.657806693f, + (float16_t)0.757208847f, (float16_t)0.653172843f, + (float16_t)0.761202385f, (float16_t)0.648514401f, + (float16_t)0.765167266f, (float16_t)0.643831543f, + (float16_t)0.769103338f, (float16_t)0.639124445f, + (float16_t)0.773010453f, (float16_t)0.634393284f, + (float16_t)0.776888466f, (float16_t)0.629638239f, + (float16_t)0.780737229f, (float16_t)0.624859488f, + (float16_t)0.784556597f, (float16_t)0.620057212f, + (float16_t)0.788346428f, (float16_t)0.615231591f, + (float16_t)0.792106577f, (float16_t)0.610382806f, + (float16_t)0.795836905f, (float16_t)0.605511041f, + (float16_t)0.799537269f, (float16_t)0.600616479f, + (float16_t)0.803207531f, (float16_t)0.595699304f, + (float16_t)0.806847554f, (float16_t)0.590759702f, + (float16_t)0.810457198f, (float16_t)0.585797857f, + (float16_t)0.814036330f, (float16_t)0.580813958f, + (float16_t)0.817584813f, (float16_t)0.575808191f, + (float16_t)0.821102515f, (float16_t)0.570780746f, + (float16_t)0.824589303f, (float16_t)0.565731811f, + (float16_t)0.828045045f, (float16_t)0.560661576f, + (float16_t)0.831469612f, (float16_t)0.555570233f, + (float16_t)0.834862875f, (float16_t)0.550457973f, + (float16_t)0.838224706f, (float16_t)0.545324988f, + (float16_t)0.841554977f, (float16_t)0.540171473f, + (float16_t)0.844853565f, (float16_t)0.534997620f, + (float16_t)0.848120345f, (float16_t)0.529803625f, + (float16_t)0.851355193f, (float16_t)0.524589683f, + (float16_t)0.854557988f, (float16_t)0.519355990f, + (float16_t)0.857728610f, (float16_t)0.514102744f, + (float16_t)0.860866939f, (float16_t)0.508830143f, + (float16_t)0.863972856f, (float16_t)0.503538384f, + (float16_t)0.867046246f, (float16_t)0.498227667f, + (float16_t)0.870086991f, (float16_t)0.492898192f, + (float16_t)0.873094978f, (float16_t)0.487550160f, + (float16_t)0.876070094f, (float16_t)0.482183772f, + (float16_t)0.879012226f, (float16_t)0.476799230f, + (float16_t)0.881921264f, (float16_t)0.471396737f, + (float16_t)0.884797098f, (float16_t)0.465976496f, + (float16_t)0.887639620f, (float16_t)0.460538711f, + (float16_t)0.890448723f, (float16_t)0.455083587f, + (float16_t)0.893224301f, (float16_t)0.449611330f, + (float16_t)0.895966250f, (float16_t)0.444122145f, + (float16_t)0.898674466f, (float16_t)0.438616239f, + (float16_t)0.901348847f, (float16_t)0.433093819f, + (float16_t)0.903989293f, (float16_t)0.427555093f, + (float16_t)0.906595705f, (float16_t)0.422000271f, + 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(float16_t)-0.958703475f, + (float16_t)0.278519689f, (float16_t)-0.960430519f, + (float16_t)0.272621355f, (float16_t)-0.962121404f, + (float16_t)0.266712757f, (float16_t)-0.963776066f, + (float16_t)0.260794118f, (float16_t)-0.965394442f, + (float16_t)0.254865660f, (float16_t)-0.966976471f, + (float16_t)0.248927606f, (float16_t)-0.968522094f, + (float16_t)0.242980180f, (float16_t)-0.970031253f, + (float16_t)0.237023606f, (float16_t)-0.971503891f, + (float16_t)0.231058108f, (float16_t)-0.972939952f, + (float16_t)0.225083911f, (float16_t)-0.974339383f, + (float16_t)0.219101240f, (float16_t)-0.975702130f, + (float16_t)0.213110320f, (float16_t)-0.977028143f, + (float16_t)0.207111376f, (float16_t)-0.978317371f, + (float16_t)0.201104635f, (float16_t)-0.979569766f, + (float16_t)0.195090322f, (float16_t)-0.980785280f, + (float16_t)0.189068664f, (float16_t)-0.981963869f, + (float16_t)0.183039888f, (float16_t)-0.983105487f, + (float16_t)0.177004220f, (float16_t)-0.984210092f, + (float16_t)0.170961889f, (float16_t)-0.985277642f, + (float16_t)0.164913120f, (float16_t)-0.986308097f, + (float16_t)0.158858143f, (float16_t)-0.987301418f, + (float16_t)0.152797185f, (float16_t)-0.988257568f, + (float16_t)0.146730474f, (float16_t)-0.989176510f, + (float16_t)0.140658239f, (float16_t)-0.990058210f, + (float16_t)0.134580709f, (float16_t)-0.990902635f, + (float16_t)0.128498111f, (float16_t)-0.991709754f, + (float16_t)0.122410675f, (float16_t)-0.992479535f, + (float16_t)0.116318631f, (float16_t)-0.993211949f, + (float16_t)0.110222207f, (float16_t)-0.993906970f, + (float16_t)0.104121634f, (float16_t)-0.994564571f, + (float16_t)0.098017140f, (float16_t)-0.995184727f, + (float16_t)0.091908956f, (float16_t)-0.995767414f, + (float16_t)0.085797312f, (float16_t)-0.996312612f, + (float16_t)0.079682438f, (float16_t)-0.996820299f, + (float16_t)0.073564564f, (float16_t)-0.997290457f, + (float16_t)0.067443920f, (float16_t)-0.997723067f, + (float16_t)0.061320736f, (float16_t)-0.998118113f, + (float16_t)0.055195244f, (float16_t)-0.998475581f, + (float16_t)0.049067674f, (float16_t)-0.998795456f, + (float16_t)0.042938257f, (float16_t)-0.999077728f, + (float16_t)0.036807223f, (float16_t)-0.999322385f, + (float16_t)0.030674803f, (float16_t)-0.999529418f, + (float16_t)0.024541229f, (float16_t)-0.999698819f, + (float16_t)0.018406730f, (float16_t)-0.999830582f, + (float16_t)0.012271538f, (float16_t)-0.999924702f, + (float16_t)0.006135885f, (float16_t)-0.999981175f +}; +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F16_2048) +const float16_t twiddleCoefF16_rfft_2048[2048] = { + (float16_t)0.000000000f, (float16_t)1.000000000f, + (float16_t)0.003067957f, (float16_t)0.999995294f, + (float16_t)0.006135885f, (float16_t)0.999981175f, + (float16_t)0.009203755f, (float16_t)0.999957645f, + (float16_t)0.012271538f, (float16_t)0.999924702f, + (float16_t)0.015339206f, (float16_t)0.999882347f, + (float16_t)0.018406730f, (float16_t)0.999830582f, + (float16_t)0.021474080f, (float16_t)0.999769405f, + (float16_t)0.024541229f, (float16_t)0.999698819f, + (float16_t)0.027608146f, (float16_t)0.999618822f, + (float16_t)0.030674803f, (float16_t)0.999529418f, + (float16_t)0.033741172f, (float16_t)0.999430605f, + (float16_t)0.036807223f, (float16_t)0.999322385f, + (float16_t)0.039872928f, (float16_t)0.999204759f, + (float16_t)0.042938257f, (float16_t)0.999077728f, + (float16_t)0.046003182f, (float16_t)0.998941293f, + (float16_t)0.049067674f, (float16_t)0.998795456f, + (float16_t)0.052131705f, (float16_t)0.998640218f, + (float16_t)0.055195244f, (float16_t)0.998475581f, + (float16_t)0.058258265f, (float16_t)0.998301545f, + (float16_t)0.061320736f, (float16_t)0.998118113f, + (float16_t)0.064382631f, (float16_t)0.997925286f, + (float16_t)0.067443920f, (float16_t)0.997723067f, + (float16_t)0.070504573f, (float16_t)0.997511456f, + (float16_t)0.073564564f, (float16_t)0.997290457f, + (float16_t)0.076623861f, (float16_t)0.997060070f, + (float16_t)0.079682438f, (float16_t)0.996820299f, + (float16_t)0.082740265f, (float16_t)0.996571146f, + (float16_t)0.085797312f, (float16_t)0.996312612f, + (float16_t)0.088853553f, (float16_t)0.996044701f, + (float16_t)0.091908956f, (float16_t)0.995767414f, + (float16_t)0.094963495f, (float16_t)0.995480755f, + (float16_t)0.098017140f, (float16_t)0.995184727f, + (float16_t)0.101069863f, (float16_t)0.994879331f, + (float16_t)0.104121634f, (float16_t)0.994564571f, + (float16_t)0.107172425f, (float16_t)0.994240449f, + (float16_t)0.110222207f, (float16_t)0.993906970f, + (float16_t)0.113270952f, (float16_t)0.993564136f, + (float16_t)0.116318631f, (float16_t)0.993211949f, + (float16_t)0.119365215f, (float16_t)0.992850414f, + (float16_t)0.122410675f, (float16_t)0.992479535f, + (float16_t)0.125454983f, (float16_t)0.992099313f, + (float16_t)0.128498111f, (float16_t)0.991709754f, + (float16_t)0.131540029f, (float16_t)0.991310860f, + (float16_t)0.134580709f, (float16_t)0.990902635f, + (float16_t)0.137620122f, (float16_t)0.990485084f, + (float16_t)0.140658239f, (float16_t)0.990058210f, + (float16_t)0.143695033f, (float16_t)0.989622017f, + (float16_t)0.146730474f, (float16_t)0.989176510f, + (float16_t)0.149764535f, (float16_t)0.988721692f, + (float16_t)0.152797185f, (float16_t)0.988257568f, + (float16_t)0.155828398f, (float16_t)0.987784142f, + (float16_t)0.158858143f, (float16_t)0.987301418f, + (float16_t)0.161886394f, (float16_t)0.986809402f, + (float16_t)0.164913120f, (float16_t)0.986308097f, + (float16_t)0.167938295f, (float16_t)0.985797509f, + (float16_t)0.170961889f, (float16_t)0.985277642f, + (float16_t)0.173983873f, (float16_t)0.984748502f, + (float16_t)0.177004220f, (float16_t)0.984210092f, + (float16_t)0.180022901f, (float16_t)0.983662419f, + (float16_t)0.183039888f, (float16_t)0.983105487f, + (float16_t)0.186055152f, (float16_t)0.982539302f, + (float16_t)0.189068664f, (float16_t)0.981963869f, + (float16_t)0.192080397f, (float16_t)0.981379193f, + (float16_t)0.195090322f, (float16_t)0.980785280f, + (float16_t)0.198098411f, (float16_t)0.980182136f, + (float16_t)0.201104635f, (float16_t)0.979569766f, + (float16_t)0.204108966f, (float16_t)0.978948175f, + (float16_t)0.207111376f, (float16_t)0.978317371f, + (float16_t)0.210111837f, (float16_t)0.977677358f, + (float16_t)0.213110320f, (float16_t)0.977028143f, + (float16_t)0.216106797f, (float16_t)0.976369731f, + (float16_t)0.219101240f, (float16_t)0.975702130f, + (float16_t)0.222093621f, (float16_t)0.975025345f, + (float16_t)0.225083911f, (float16_t)0.974339383f, + (float16_t)0.228072083f, (float16_t)0.973644250f, + (float16_t)0.231058108f, (float16_t)0.972939952f, + (float16_t)0.234041959f, (float16_t)0.972226497f, + (float16_t)0.237023606f, (float16_t)0.971503891f, + (float16_t)0.240003022f, (float16_t)0.970772141f, + (float16_t)0.242980180f, (float16_t)0.970031253f, + (float16_t)0.245955050f, (float16_t)0.969281235f, + (float16_t)0.248927606f, (float16_t)0.968522094f, + (float16_t)0.251897818f, (float16_t)0.967753837f, + (float16_t)0.254865660f, (float16_t)0.966976471f, + (float16_t)0.257831102f, (float16_t)0.966190003f, + (float16_t)0.260794118f, (float16_t)0.965394442f, + (float16_t)0.263754679f, (float16_t)0.964589793f, + (float16_t)0.266712757f, (float16_t)0.963776066f, + (float16_t)0.269668326f, (float16_t)0.962953267f, + (float16_t)0.272621355f, (float16_t)0.962121404f, + (float16_t)0.275571819f, (float16_t)0.961280486f, + (float16_t)0.278519689f, (float16_t)0.960430519f, + (float16_t)0.281464938f, (float16_t)0.959571513f, + (float16_t)0.284407537f, (float16_t)0.958703475f, + (float16_t)0.287347460f, (float16_t)0.957826413f, + (float16_t)0.290284677f, (float16_t)0.956940336f, + (float16_t)0.293219163f, (float16_t)0.956045251f, + (float16_t)0.296150888f, (float16_t)0.955141168f, + (float16_t)0.299079826f, (float16_t)0.954228095f, + (float16_t)0.302005949f, (float16_t)0.953306040f, + (float16_t)0.304929230f, (float16_t)0.952375013f, + (float16_t)0.307849640f, (float16_t)0.951435021f, + (float16_t)0.310767153f, (float16_t)0.950486074f, + (float16_t)0.313681740f, (float16_t)0.949528181f, + (float16_t)0.316593376f, (float16_t)0.948561350f, + (float16_t)0.319502031f, (float16_t)0.947585591f, + (float16_t)0.322407679f, (float16_t)0.946600913f, + (float16_t)0.325310292f, (float16_t)0.945607325f, + (float16_t)0.328209844f, (float16_t)0.944604837f, + (float16_t)0.331106306f, (float16_t)0.943593458f, + (float16_t)0.333999651f, (float16_t)0.942573198f, + (float16_t)0.336889853f, (float16_t)0.941544065f, + (float16_t)0.339776884f, (float16_t)0.940506071f, + (float16_t)0.342660717f, (float16_t)0.939459224f, + (float16_t)0.345541325f, (float16_t)0.938403534f, + (float16_t)0.348418680f, (float16_t)0.937339012f, + (float16_t)0.351292756f, (float16_t)0.936265667f, + (float16_t)0.354163525f, (float16_t)0.935183510f, + (float16_t)0.357030961f, (float16_t)0.934092550f, + (float16_t)0.359895037f, (float16_t)0.932992799f, + (float16_t)0.362755724f, (float16_t)0.931884266f, + (float16_t)0.365612998f, (float16_t)0.930766961f, + (float16_t)0.368466830f, (float16_t)0.929640896f, + (float16_t)0.371317194f, (float16_t)0.928506080f, + (float16_t)0.374164063f, (float16_t)0.927362526f, + (float16_t)0.377007410f, (float16_t)0.926210242f, + (float16_t)0.379847209f, (float16_t)0.925049241f, + (float16_t)0.382683432f, (float16_t)0.923879533f, + (float16_t)0.385516054f, (float16_t)0.922701128f, + (float16_t)0.388345047f, (float16_t)0.921514039f, + (float16_t)0.391170384f, (float16_t)0.920318277f, + (float16_t)0.393992040f, (float16_t)0.919113852f, + (float16_t)0.396809987f, (float16_t)0.917900776f, + (float16_t)0.399624200f, (float16_t)0.916679060f, + (float16_t)0.402434651f, (float16_t)0.915448716f, + (float16_t)0.405241314f, (float16_t)0.914209756f, + (float16_t)0.408044163f, (float16_t)0.912962190f, + (float16_t)0.410843171f, (float16_t)0.911706032f, + (float16_t)0.413638312f, (float16_t)0.910441292f, + (float16_t)0.416429560f, (float16_t)0.909167983f, + (float16_t)0.419216888f, (float16_t)0.907886116f, + (float16_t)0.422000271f, (float16_t)0.906595705f, + (float16_t)0.424779681f, (float16_t)0.905296759f, + (float16_t)0.427555093f, (float16_t)0.903989293f, + (float16_t)0.430326481f, (float16_t)0.902673318f, + (float16_t)0.433093819f, (float16_t)0.901348847f, + (float16_t)0.435857080f, (float16_t)0.900015892f, + (float16_t)0.438616239f, (float16_t)0.898674466f, + (float16_t)0.441371269f, (float16_t)0.897324581f, + (float16_t)0.444122145f, (float16_t)0.895966250f, + (float16_t)0.446868840f, (float16_t)0.894599486f, + (float16_t)0.449611330f, (float16_t)0.893224301f, + (float16_t)0.452349587f, (float16_t)0.891840709f, + (float16_t)0.455083587f, (float16_t)0.890448723f, + (float16_t)0.457813304f, (float16_t)0.889048356f, + (float16_t)0.460538711f, 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(float16_t)0.354163525f, (float16_t)-0.935183510f, + (float16_t)0.351292756f, (float16_t)-0.936265667f, + (float16_t)0.348418680f, (float16_t)-0.937339012f, + (float16_t)0.345541325f, (float16_t)-0.938403534f, + (float16_t)0.342660717f, (float16_t)-0.939459224f, + (float16_t)0.339776884f, (float16_t)-0.940506071f, + (float16_t)0.336889853f, (float16_t)-0.941544065f, + (float16_t)0.333999651f, (float16_t)-0.942573198f, + (float16_t)0.331106306f, (float16_t)-0.943593458f, + (float16_t)0.328209844f, (float16_t)-0.944604837f, + (float16_t)0.325310292f, (float16_t)-0.945607325f, + (float16_t)0.322407679f, (float16_t)-0.946600913f, + (float16_t)0.319502031f, (float16_t)-0.947585591f, + (float16_t)0.316593376f, (float16_t)-0.948561350f, + (float16_t)0.313681740f, (float16_t)-0.949528181f, + (float16_t)0.310767153f, (float16_t)-0.950486074f, + (float16_t)0.307849640f, (float16_t)-0.951435021f, + (float16_t)0.304929230f, (float16_t)-0.952375013f, + (float16_t)0.302005949f, (float16_t)-0.953306040f, + (float16_t)0.299079826f, (float16_t)-0.954228095f, + (float16_t)0.296150888f, (float16_t)-0.955141168f, + (float16_t)0.293219163f, (float16_t)-0.956045251f, + (float16_t)0.290284677f, (float16_t)-0.956940336f, + (float16_t)0.287347460f, (float16_t)-0.957826413f, + (float16_t)0.284407537f, (float16_t)-0.958703475f, + (float16_t)0.281464938f, (float16_t)-0.959571513f, + (float16_t)0.278519689f, (float16_t)-0.960430519f, + (float16_t)0.275571819f, (float16_t)-0.961280486f, + (float16_t)0.272621355f, (float16_t)-0.962121404f, + (float16_t)0.269668326f, (float16_t)-0.962953267f, + (float16_t)0.266712757f, (float16_t)-0.963776066f, + (float16_t)0.263754679f, (float16_t)-0.964589793f, + (float16_t)0.260794118f, (float16_t)-0.965394442f, + (float16_t)0.257831102f, (float16_t)-0.966190003f, + (float16_t)0.254865660f, (float16_t)-0.966976471f, + (float16_t)0.251897818f, (float16_t)-0.967753837f, + (float16_t)0.248927606f, (float16_t)-0.968522094f, + (float16_t)0.245955050f, (float16_t)-0.969281235f, + (float16_t)0.242980180f, (float16_t)-0.970031253f, + (float16_t)0.240003022f, (float16_t)-0.970772141f, + (float16_t)0.237023606f, (float16_t)-0.971503891f, + (float16_t)0.234041959f, (float16_t)-0.972226497f, + (float16_t)0.231058108f, (float16_t)-0.972939952f, + (float16_t)0.228072083f, (float16_t)-0.973644250f, + (float16_t)0.225083911f, (float16_t)-0.974339383f, + (float16_t)0.222093621f, (float16_t)-0.975025345f, + (float16_t)0.219101240f, (float16_t)-0.975702130f, + (float16_t)0.216106797f, (float16_t)-0.976369731f, + (float16_t)0.213110320f, (float16_t)-0.977028143f, + (float16_t)0.210111837f, (float16_t)-0.977677358f, + (float16_t)0.207111376f, (float16_t)-0.978317371f, + (float16_t)0.204108966f, (float16_t)-0.978948175f, + (float16_t)0.201104635f, (float16_t)-0.979569766f, + (float16_t)0.198098411f, (float16_t)-0.980182136f, + (float16_t)0.195090322f, (float16_t)-0.980785280f, + (float16_t)0.192080397f, (float16_t)-0.981379193f, + (float16_t)0.189068664f, (float16_t)-0.981963869f, + (float16_t)0.186055152f, (float16_t)-0.982539302f, + (float16_t)0.183039888f, (float16_t)-0.983105487f, + (float16_t)0.180022901f, (float16_t)-0.983662419f, + (float16_t)0.177004220f, (float16_t)-0.984210092f, + (float16_t)0.173983873f, (float16_t)-0.984748502f, + (float16_t)0.170961889f, (float16_t)-0.985277642f, + (float16_t)0.167938295f, (float16_t)-0.985797509f, + (float16_t)0.164913120f, (float16_t)-0.986308097f, + (float16_t)0.161886394f, (float16_t)-0.986809402f, + (float16_t)0.158858143f, (float16_t)-0.987301418f, + (float16_t)0.155828398f, (float16_t)-0.987784142f, + (float16_t)0.152797185f, (float16_t)-0.988257568f, + (float16_t)0.149764535f, (float16_t)-0.988721692f, + (float16_t)0.146730474f, (float16_t)-0.989176510f, + (float16_t)0.143695033f, (float16_t)-0.989622017f, + (float16_t)0.140658239f, (float16_t)-0.990058210f, + (float16_t)0.137620122f, (float16_t)-0.990485084f, + (float16_t)0.134580709f, (float16_t)-0.990902635f, + (float16_t)0.131540029f, (float16_t)-0.991310860f, + (float16_t)0.128498111f, (float16_t)-0.991709754f, + (float16_t)0.125454983f, (float16_t)-0.992099313f, + (float16_t)0.122410675f, (float16_t)-0.992479535f, + (float16_t)0.119365215f, (float16_t)-0.992850414f, + (float16_t)0.116318631f, (float16_t)-0.993211949f, + (float16_t)0.113270952f, (float16_t)-0.993564136f, + (float16_t)0.110222207f, (float16_t)-0.993906970f, + (float16_t)0.107172425f, (float16_t)-0.994240449f, + (float16_t)0.104121634f, (float16_t)-0.994564571f, + (float16_t)0.101069863f, (float16_t)-0.994879331f, + (float16_t)0.098017140f, (float16_t)-0.995184727f, + (float16_t)0.094963495f, (float16_t)-0.995480755f, + (float16_t)0.091908956f, (float16_t)-0.995767414f, + (float16_t)0.088853553f, (float16_t)-0.996044701f, + (float16_t)0.085797312f, (float16_t)-0.996312612f, + (float16_t)0.082740265f, (float16_t)-0.996571146f, + (float16_t)0.079682438f, (float16_t)-0.996820299f, + (float16_t)0.076623861f, (float16_t)-0.997060070f, + (float16_t)0.073564564f, (float16_t)-0.997290457f, + (float16_t)0.070504573f, (float16_t)-0.997511456f, + (float16_t)0.067443920f, (float16_t)-0.997723067f, + (float16_t)0.064382631f, (float16_t)-0.997925286f, + (float16_t)0.061320736f, (float16_t)-0.998118113f, + (float16_t)0.058258265f, (float16_t)-0.998301545f, + (float16_t)0.055195244f, (float16_t)-0.998475581f, + (float16_t)0.052131705f, (float16_t)-0.998640218f, + (float16_t)0.049067674f, (float16_t)-0.998795456f, + (float16_t)0.046003182f, (float16_t)-0.998941293f, + (float16_t)0.042938257f, (float16_t)-0.999077728f, + (float16_t)0.039872928f, (float16_t)-0.999204759f, + (float16_t)0.036807223f, (float16_t)-0.999322385f, + (float16_t)0.033741172f, (float16_t)-0.999430605f, + (float16_t)0.030674803f, (float16_t)-0.999529418f, + (float16_t)0.027608146f, (float16_t)-0.999618822f, + (float16_t)0.024541229f, (float16_t)-0.999698819f, + (float16_t)0.021474080f, (float16_t)-0.999769405f, + (float16_t)0.018406730f, (float16_t)-0.999830582f, + (float16_t)0.015339206f, (float16_t)-0.999882347f, + (float16_t)0.012271538f, (float16_t)-0.999924702f, + (float16_t)0.009203755f, (float16_t)-0.999957645f, + (float16_t)0.006135885f, (float16_t)-0.999981175f, + (float16_t)0.003067957f, (float16_t)-0.999995294f +}; +#endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F16_4096) +const float16_t twiddleCoefF16_rfft_4096[4096] = { + (float16_t)0.000000000f, (float16_t)1.000000000f, + (float16_t)0.001533980f, (float16_t)0.999998823f, + (float16_t)0.003067957f, (float16_t)0.999995294f, + (float16_t)0.004601926f, (float16_t)0.999989411f, + (float16_t)0.006135885f, (float16_t)0.999981175f, + (float16_t)0.007669829f, (float16_t)0.999970586f, + (float16_t)0.009203755f, (float16_t)0.999957645f, + (float16_t)0.010737659f, (float16_t)0.999942350f, + (float16_t)0.012271538f, (float16_t)0.999924702f, + (float16_t)0.013805389f, (float16_t)0.999904701f, + (float16_t)0.015339206f, (float16_t)0.999882347f, + (float16_t)0.016872988f, (float16_t)0.999857641f, + (float16_t)0.018406730f, (float16_t)0.999830582f, + (float16_t)0.019940429f, (float16_t)0.999801170f, + (float16_t)0.021474080f, (float16_t)0.999769405f, + (float16_t)0.023007681f, (float16_t)0.999735288f, + (float16_t)0.024541229f, (float16_t)0.999698819f, + (float16_t)0.026074718f, (float16_t)0.999659997f, + (float16_t)0.027608146f, (float16_t)0.999618822f, + (float16_t)0.029141509f, (float16_t)0.999575296f, + (float16_t)0.030674803f, (float16_t)0.999529418f, + (float16_t)0.032208025f, (float16_t)0.999481187f, + (float16_t)0.033741172f, (float16_t)0.999430605f, + (float16_t)0.035274239f, (float16_t)0.999377670f, + (float16_t)0.036807223f, (float16_t)0.999322385f, + (float16_t)0.038340120f, (float16_t)0.999264747f, + (float16_t)0.039872928f, (float16_t)0.999204759f, + (float16_t)0.041405641f, (float16_t)0.999142419f, + (float16_t)0.042938257f, (float16_t)0.999077728f, + (float16_t)0.044470772f, (float16_t)0.999010686f, + (float16_t)0.046003182f, (float16_t)0.998941293f, + (float16_t)0.047535484f, (float16_t)0.998869550f, + (float16_t)0.049067674f, (float16_t)0.998795456f, + (float16_t)0.050599749f, (float16_t)0.998719012f, + (float16_t)0.052131705f, (float16_t)0.998640218f, + (float16_t)0.053663538f, (float16_t)0.998559074f, + (float16_t)0.055195244f, (float16_t)0.998475581f, + (float16_t)0.056726821f, (float16_t)0.998389737f, + (float16_t)0.058258265f, (float16_t)0.998301545f, + (float16_t)0.059789571f, (float16_t)0.998211003f, + (float16_t)0.061320736f, (float16_t)0.998118113f, + (float16_t)0.062851758f, (float16_t)0.998022874f, + (float16_t)0.064382631f, (float16_t)0.997925286f, + (float16_t)0.065913353f, (float16_t)0.997825350f, + (float16_t)0.067443920f, (float16_t)0.997723067f, + (float16_t)0.068974328f, (float16_t)0.997618435f, + (float16_t)0.070504573f, (float16_t)0.997511456f, + (float16_t)0.072034653f, (float16_t)0.997402130f, + (float16_t)0.073564564f, (float16_t)0.997290457f, + (float16_t)0.075094301f, (float16_t)0.997176437f, + (float16_t)0.076623861f, (float16_t)0.997060070f, + (float16_t)0.078153242f, (float16_t)0.996941358f, + (float16_t)0.079682438f, (float16_t)0.996820299f, + (float16_t)0.081211447f, (float16_t)0.996696895f, + (float16_t)0.082740265f, (float16_t)0.996571146f, + (float16_t)0.084268888f, (float16_t)0.996443051f, + (float16_t)0.085797312f, (float16_t)0.996312612f, + (float16_t)0.087325535f, (float16_t)0.996179829f, + (float16_t)0.088853553f, (float16_t)0.996044701f, + (float16_t)0.090381361f, (float16_t)0.995907229f, + (float16_t)0.091908956f, (float16_t)0.995767414f, + (float16_t)0.093436336f, (float16_t)0.995625256f, + (float16_t)0.094963495f, (float16_t)0.995480755f, + (float16_t)0.096490431f, (float16_t)0.995333912f, + (float16_t)0.098017140f, (float16_t)0.995184727f, + (float16_t)0.099543619f, (float16_t)0.995033199f, + (float16_t)0.101069863f, (float16_t)0.994879331f, + (float16_t)0.102595869f, (float16_t)0.994723121f, + (float16_t)0.104121634f, (float16_t)0.994564571f, + (float16_t)0.105647154f, (float16_t)0.994403680f, + (float16_t)0.107172425f, (float16_t)0.994240449f, + (float16_t)0.108697444f, (float16_t)0.994074879f, + (float16_t)0.110222207f, (float16_t)0.993906970f, + (float16_t)0.111746711f, (float16_t)0.993736722f, + (float16_t)0.113270952f, (float16_t)0.993564136f, + (float16_t)0.114794927f, (float16_t)0.993389211f, + (float16_t)0.116318631f, (float16_t)0.993211949f, + (float16_t)0.117842062f, (float16_t)0.993032350f, + (float16_t)0.119365215f, (float16_t)0.992850414f, + (float16_t)0.120888087f, (float16_t)0.992666142f, + (float16_t)0.122410675f, (float16_t)0.992479535f, + (float16_t)0.123932975f, (float16_t)0.992290591f, + (float16_t)0.125454983f, (float16_t)0.992099313f, + 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(float16_t)0.081211447f, (float16_t)-0.996696895f, + (float16_t)0.079682438f, (float16_t)-0.996820299f, + (float16_t)0.078153242f, (float16_t)-0.996941358f, + (float16_t)0.076623861f, (float16_t)-0.997060070f, + (float16_t)0.075094301f, (float16_t)-0.997176437f, + (float16_t)0.073564564f, (float16_t)-0.997290457f, + (float16_t)0.072034653f, (float16_t)-0.997402130f, + (float16_t)0.070504573f, (float16_t)-0.997511456f, + (float16_t)0.068974328f, (float16_t)-0.997618435f, + (float16_t)0.067443920f, (float16_t)-0.997723067f, + (float16_t)0.065913353f, (float16_t)-0.997825350f, + (float16_t)0.064382631f, (float16_t)-0.997925286f, + (float16_t)0.062851758f, (float16_t)-0.998022874f, + (float16_t)0.061320736f, (float16_t)-0.998118113f, + (float16_t)0.059789571f, (float16_t)-0.998211003f, + (float16_t)0.058258265f, (float16_t)-0.998301545f, + (float16_t)0.056726821f, (float16_t)-0.998389737f, + (float16_t)0.055195244f, (float16_t)-0.998475581f, + (float16_t)0.053663538f, (float16_t)-0.998559074f, + (float16_t)0.052131705f, (float16_t)-0.998640218f, + (float16_t)0.050599749f, (float16_t)-0.998719012f, + (float16_t)0.049067674f, (float16_t)-0.998795456f, + (float16_t)0.047535484f, (float16_t)-0.998869550f, + (float16_t)0.046003182f, (float16_t)-0.998941293f, + (float16_t)0.044470772f, (float16_t)-0.999010686f, + (float16_t)0.042938257f, (float16_t)-0.999077728f, + (float16_t)0.041405641f, (float16_t)-0.999142419f, + (float16_t)0.039872928f, (float16_t)-0.999204759f, + (float16_t)0.038340120f, (float16_t)-0.999264747f, + (float16_t)0.036807223f, (float16_t)-0.999322385f, + (float16_t)0.035274239f, (float16_t)-0.999377670f, + (float16_t)0.033741172f, (float16_t)-0.999430605f, + (float16_t)0.032208025f, (float16_t)-0.999481187f, + (float16_t)0.030674803f, (float16_t)-0.999529418f, + (float16_t)0.029141509f, (float16_t)-0.999575296f, + (float16_t)0.027608146f, (float16_t)-0.999618822f, + (float16_t)0.026074718f, (float16_t)-0.999659997f, + (float16_t)0.024541229f, (float16_t)-0.999698819f, + (float16_t)0.023007681f, (float16_t)-0.999735288f, + (float16_t)0.021474080f, (float16_t)-0.999769405f, + (float16_t)0.019940429f, (float16_t)-0.999801170f, + (float16_t)0.018406730f, (float16_t)-0.999830582f, + (float16_t)0.016872988f, (float16_t)-0.999857641f, + (float16_t)0.015339206f, (float16_t)-0.999882347f, + (float16_t)0.013805389f, (float16_t)-0.999904701f, + (float16_t)0.012271538f, (float16_t)-0.999924702f, + (float16_t)0.010737659f, (float16_t)-0.999942350f, + (float16_t)0.009203755f, (float16_t)-0.999957645f, + (float16_t)0.007669829f, (float16_t)-0.999970586f, + (float16_t)0.006135885f, (float16_t)-0.999981175f, + (float16_t)0.004601926f, (float16_t)-0.999989411f, + (float16_t)0.003067957f, (float16_t)-0.999995294f, + (float16_t)0.001533980f, (float16_t)-0.999998823f +}; + +#endif /* if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_FFT_ALL_TABLES) */ + +#endif /*!defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_FFT_ALLOW_TABLES)*/ + + + +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ + + + +/** + @} end of CFFT_CIFFT group +*/ diff --git a/components/nmsis/dsp/src/CommonTables/riscv_const_structs.c b/components/nmsis/dsp/src/CommonTables/riscv_const_structs.c new file mode 100644 index 00000000..7a3db64e --- /dev/null +++ b/components/nmsis/dsp/src/CommonTables/riscv_const_structs.c @@ -0,0 +1,647 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_const_structs.c + * Description: Constant structs that are initialized for user convenience. + * For example, some can be given as arguments to the riscv_cfft_f32() or riscv_rfft_f32() functions. + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "riscv_math_types.h" +#include "riscv_const_structs.h" + +/* +ALLOW TABLE is true when config table is enabled and the Tramsform folder is included +for compilation. +*/ +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_FFT_ALLOW_TABLES) + +/* Floating-point structs */ +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F64_16) && defined(RISCV_TABLE_BITREVIDX_FLT64_16)) +const riscv_cfft_instance_f64 riscv_cfft_sR_f64_len16 = { + 16, (const float64_t *)twiddleCoefF64_16, riscvBitRevIndexTableF64_16, RISCVBITREVINDEXTABLEF64_16_TABLE_LENGTH +}; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F64_32) && defined(RISCV_TABLE_BITREVIDX_FLT64_32)) +const riscv_cfft_instance_f64 riscv_cfft_sR_f64_len32 = { + 32, (const float64_t *)twiddleCoefF64_32, riscvBitRevIndexTableF64_32, RISCVBITREVINDEXTABLEF64_32_TABLE_LENGTH +}; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F64_64) && defined(RISCV_TABLE_BITREVIDX_FLT64_64)) +const riscv_cfft_instance_f64 riscv_cfft_sR_f64_len64 = { + 64, (const float64_t *)twiddleCoefF64_64, riscvBitRevIndexTableF64_64, RISCVBITREVINDEXTABLEF64_64_TABLE_LENGTH +}; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F64_128) && defined(RISCV_TABLE_BITREVIDX_FLT64_128)) +const riscv_cfft_instance_f64 riscv_cfft_sR_f64_len128 = { + 128, (const float64_t *)twiddleCoefF64_128, riscvBitRevIndexTableF64_128, RISCVBITREVINDEXTABLEF64_128_TABLE_LENGTH +}; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F64_256) && defined(RISCV_TABLE_BITREVIDX_FLT64_256)) +const riscv_cfft_instance_f64 riscv_cfft_sR_f64_len256 = { + 256, (const float64_t *)twiddleCoefF64_256, riscvBitRevIndexTableF64_256, RISCVBITREVINDEXTABLEF64_256_TABLE_LENGTH +}; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F64_512) && defined(RISCV_TABLE_BITREVIDX_FLT64_512)) +const riscv_cfft_instance_f64 riscv_cfft_sR_f64_len512 = { + 512, (const float64_t *)twiddleCoefF64_512, riscvBitRevIndexTableF64_512, RISCVBITREVINDEXTABLEF64_512_TABLE_LENGTH +}; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F64_1024) && defined(RISCV_TABLE_BITREVIDX_FLT64_1024)) +const riscv_cfft_instance_f64 riscv_cfft_sR_f64_len1024 = { + 1024, (const float64_t *)twiddleCoefF64_1024, riscvBitRevIndexTableF64_1024, RISCVBITREVINDEXTABLEF64_1024_TABLE_LENGTH +}; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F64_2048) && defined(RISCV_TABLE_BITREVIDX_FLT64_2048)) +const riscv_cfft_instance_f64 riscv_cfft_sR_f64_len2048 = { + 2048, (const float64_t *)twiddleCoefF64_2048, riscvBitRevIndexTableF64_2048, RISCVBITREVINDEXTABLEF64_2048_TABLE_LENGTH +}; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F64_4096) && defined(RISCV_TABLE_BITREVIDX_FLT64_4096)) +const riscv_cfft_instance_f64 riscv_cfft_sR_f64_len4096 = { + 4096, (const float64_t *)twiddleCoefF64_4096, riscvBitRevIndexTableF64_4096, RISCVBITREVINDEXTABLEF64_4096_TABLE_LENGTH +}; +#endif + +/* Floating-point structs */ + + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F32_16) && defined(RISCV_TABLE_BITREVIDX_FLT_16)) +const riscv_cfft_instance_f32 riscv_cfft_sR_f32_len16 = { + 16, twiddleCoef_16, riscvBitRevIndexTable16, RISCVBITREVINDEXTABLE_16_TABLE_LENGTH +}; +#endif + + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F32_32) && defined(RISCV_TABLE_BITREVIDX_FLT_32)) +const riscv_cfft_instance_f32 riscv_cfft_sR_f32_len32 = { + 32, twiddleCoef_32, riscvBitRevIndexTable32, RISCVBITREVINDEXTABLE_32_TABLE_LENGTH +}; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F32_64) && defined(RISCV_TABLE_BITREVIDX_FLT_64)) +const riscv_cfft_instance_f32 riscv_cfft_sR_f32_len64 = { + 64, twiddleCoef_64, riscvBitRevIndexTable64, RISCVBITREVINDEXTABLE_64_TABLE_LENGTH +}; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F32_128) && defined(RISCV_TABLE_BITREVIDX_FLT_128)) +const riscv_cfft_instance_f32 riscv_cfft_sR_f32_len128 = { + 128, twiddleCoef_128, riscvBitRevIndexTable128, RISCVBITREVINDEXTABLE_128_TABLE_LENGTH +}; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F32_256) && defined(RISCV_TABLE_BITREVIDX_FLT_256)) +const riscv_cfft_instance_f32 riscv_cfft_sR_f32_len256 = { + 256, twiddleCoef_256, riscvBitRevIndexTable256, RISCVBITREVINDEXTABLE_256_TABLE_LENGTH +}; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F32_512) && defined(RISCV_TABLE_BITREVIDX_FLT_512)) +const riscv_cfft_instance_f32 riscv_cfft_sR_f32_len512 = { + 512, twiddleCoef_512, riscvBitRevIndexTable512, RISCVBITREVINDEXTABLE_512_TABLE_LENGTH +}; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F32_1024) && defined(RISCV_TABLE_BITREVIDX_FLT_1024)) +const riscv_cfft_instance_f32 riscv_cfft_sR_f32_len1024 = { + 1024, twiddleCoef_1024, riscvBitRevIndexTable1024, RISCVBITREVINDEXTABLE_1024_TABLE_LENGTH +}; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F32_2048) && defined(RISCV_TABLE_BITREVIDX_FLT_2048)) +const riscv_cfft_instance_f32 riscv_cfft_sR_f32_len2048 = { + 2048, twiddleCoef_2048, riscvBitRevIndexTable2048, RISCVBITREVINDEXTABLE_2048_TABLE_LENGTH +}; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F32_4096) && defined(RISCV_TABLE_BITREVIDX_FLT_4096)) +const riscv_cfft_instance_f32 riscv_cfft_sR_f32_len4096 = { + 4096, twiddleCoef_4096, riscvBitRevIndexTable4096, RISCVBITREVINDEXTABLE_4096_TABLE_LENGTH +}; +#endif + + +/* Fixed-point structs */ + + +/* + +Those structures cannot be used to initialize the MVE version of the FFT Q31 instances. +So they are not compiled when MVE is defined. + +For the MVE version, the new riscv_cfft_init_f32 must be used. + + +*/ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_Q31_16) && defined(RISCV_TABLE_BITREVIDX_FXT_16)) +const riscv_cfft_instance_q31 riscv_cfft_sR_q31_len16 = { + 16, twiddleCoef_16_q31, riscvBitRevIndexTable_fixed_16, RISCVBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH +}; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_Q31_32) && defined(RISCV_TABLE_BITREVIDX_FXT_32)) +const riscv_cfft_instance_q31 riscv_cfft_sR_q31_len32 = { + 32, twiddleCoef_32_q31, riscvBitRevIndexTable_fixed_32, RISCVBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH +}; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_Q31_64) && defined(RISCV_TABLE_BITREVIDX_FXT_64)) +const riscv_cfft_instance_q31 riscv_cfft_sR_q31_len64 = { + 64, twiddleCoef_64_q31, riscvBitRevIndexTable_fixed_64, RISCVBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH +}; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_Q31_128) && defined(RISCV_TABLE_BITREVIDX_FXT_128)) +const riscv_cfft_instance_q31 riscv_cfft_sR_q31_len128 = { + 128, twiddleCoef_128_q31, riscvBitRevIndexTable_fixed_128, RISCVBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH +}; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_Q31_256) && defined(RISCV_TABLE_BITREVIDX_FXT_256)) +const riscv_cfft_instance_q31 riscv_cfft_sR_q31_len256 = { + 256, twiddleCoef_256_q31, riscvBitRevIndexTable_fixed_256, RISCVBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH +}; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_Q31_512) && defined(RISCV_TABLE_BITREVIDX_FXT_512)) +const riscv_cfft_instance_q31 riscv_cfft_sR_q31_len512 = { + 512, twiddleCoef_512_q31, riscvBitRevIndexTable_fixed_512, RISCVBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH +}; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_Q31_1024) && defined(RISCV_TABLE_BITREVIDX_FXT_1024)) +const riscv_cfft_instance_q31 riscv_cfft_sR_q31_len1024 = { + 1024, twiddleCoef_1024_q31, riscvBitRevIndexTable_fixed_1024, RISCVBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH +}; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_Q31_2048) && defined(RISCV_TABLE_BITREVIDX_FXT_2048)) +const riscv_cfft_instance_q31 riscv_cfft_sR_q31_len2048 = { + 2048, twiddleCoef_2048_q31, riscvBitRevIndexTable_fixed_2048, RISCVBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH +}; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_Q31_4096) && defined(RISCV_TABLE_BITREVIDX_FXT_4096)) +const riscv_cfft_instance_q31 riscv_cfft_sR_q31_len4096 = { + 4096, twiddleCoef_4096_q31, riscvBitRevIndexTable_fixed_4096, RISCVBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH +}; +#endif + + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_Q15_16) && defined(RISCV_TABLE_BITREVIDX_FXT_16)) +const riscv_cfft_instance_q15 riscv_cfft_sR_q15_len16 = { + 16, twiddleCoef_16_q15, riscvBitRevIndexTable_fixed_16, RISCVBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH +}; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_Q15_32) && defined(RISCV_TABLE_BITREVIDX_FXT_32)) +const riscv_cfft_instance_q15 riscv_cfft_sR_q15_len32 = { + 32, twiddleCoef_32_q15, riscvBitRevIndexTable_fixed_32, RISCVBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH +}; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_Q15_64) && defined(RISCV_TABLE_BITREVIDX_FXT_64)) +const riscv_cfft_instance_q15 riscv_cfft_sR_q15_len64 = { + 64, twiddleCoef_64_q15, riscvBitRevIndexTable_fixed_64, RISCVBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH +}; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_Q15_128) && defined(RISCV_TABLE_BITREVIDX_FXT_128)) +const riscv_cfft_instance_q15 riscv_cfft_sR_q15_len128 = { + 128, twiddleCoef_128_q15, riscvBitRevIndexTable_fixed_128, RISCVBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH +}; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_Q15_256) && defined(RISCV_TABLE_BITREVIDX_FXT_256)) +const riscv_cfft_instance_q15 riscv_cfft_sR_q15_len256 = { + 256, twiddleCoef_256_q15, riscvBitRevIndexTable_fixed_256, RISCVBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH +}; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_Q15_512) && defined(RISCV_TABLE_BITREVIDX_FXT_512)) +const riscv_cfft_instance_q15 riscv_cfft_sR_q15_len512 = { + 512, twiddleCoef_512_q15, riscvBitRevIndexTable_fixed_512, RISCVBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH +}; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_Q15_1024) && defined(RISCV_TABLE_BITREVIDX_FXT_1024)) +const riscv_cfft_instance_q15 riscv_cfft_sR_q15_len1024 = { + 1024, twiddleCoef_1024_q15, riscvBitRevIndexTable_fixed_1024, RISCVBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH +}; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_Q15_2048) && defined(RISCV_TABLE_BITREVIDX_FXT_2048)) +const riscv_cfft_instance_q15 riscv_cfft_sR_q15_len2048 = { + 2048, twiddleCoef_2048_q15, riscvBitRevIndexTable_fixed_2048, RISCVBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH +}; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_Q15_4096) && defined(RISCV_TABLE_BITREVIDX_FXT_4096)) +const riscv_cfft_instance_q15 riscv_cfft_sR_q15_len4096 = { + 4096, twiddleCoef_4096_q15, riscvBitRevIndexTable_fixed_4096, RISCVBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH +}; +#endif + + +/* Structure for real-value inputs */ +/* Double precision strucs */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F64_32) && defined(RISCV_TABLE_BITREVIDX_FLT64_32) && defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F64_32)) +const riscv_rfft_fast_instance_f64 riscv_rfft_fast_sR_f64_len32 = { + { 16, (const float64_t *)twiddleCoefF64_16, riscvBitRevIndexTableF64_16, RISCVBITREVINDEXTABLEF64_16_TABLE_LENGTH }, + 32U, + (float64_t *)twiddleCoefF64_rfft_32 +}; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F64_64) && defined(RISCV_TABLE_BITREVIDX_FLT64_64) && defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F64_64)) +const riscv_rfft_fast_instance_f64 riscv_rfft_fast_sR_f64_len64 = { + { 32, (const float64_t *)twiddleCoefF64_32, riscvBitRevIndexTableF64_32, RISCVBITREVINDEXTABLEF64_32_TABLE_LENGTH }, + 64U, + (float64_t *)twiddleCoefF64_rfft_64 +}; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F64_128) && defined(RISCV_TABLE_BITREVIDX_FLT64_128) && defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F64_128)) +const riscv_rfft_fast_instance_f64 riscv_rfft_fast_sR_f64_len128 = { + { 64, (const float64_t *)twiddleCoefF64_64, riscvBitRevIndexTableF64_64, RISCVBITREVINDEXTABLEF64_64_TABLE_LENGTH }, + 128U, + (float64_t *)twiddleCoefF64_rfft_128 +}; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F64_256) && defined(RISCV_TABLE_BITREVIDX_FLT64_256) && defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F64_256)) +const riscv_rfft_fast_instance_f64 riscv_rfft_fast_sR_f64_len256 = { + { 128, (const float64_t *)twiddleCoefF64_128, riscvBitRevIndexTableF64_128, RISCVBITREVINDEXTABLEF64_128_TABLE_LENGTH }, + 256U, + (float64_t *)twiddleCoefF64_rfft_256 +}; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F64_512) && defined(RISCV_TABLE_BITREVIDX_FLT64_512) && defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F64_512)) +const riscv_rfft_fast_instance_f64 riscv_rfft_fast_sR_f64_len512 = { + { 256, (const float64_t *)twiddleCoefF64_256, riscvBitRevIndexTableF64_256, RISCVBITREVINDEXTABLEF64_256_TABLE_LENGTH }, + 512U, + (float64_t *)twiddleCoefF64_rfft_512 +}; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F64_1024) && defined(RISCV_TABLE_BITREVIDX_FLT64_1024) && defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F64_1024)) +const riscv_rfft_fast_instance_f64 riscv_rfft_fast_sR_f64_len1024 = { + { 512, (const float64_t *)twiddleCoefF64_512, riscvBitRevIndexTableF64_512, RISCVBITREVINDEXTABLEF64_512_TABLE_LENGTH }, + 1024U, + (float64_t *)twiddleCoefF64_rfft_1024 +}; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F64_2048) && defined(RISCV_TABLE_BITREVIDX_FLT64_2048) && defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F64_2048)) +const riscv_rfft_fast_instance_f64 riscv_rfft_fast_sR_f64_len2048 = { + { 1024, (const float64_t *)twiddleCoefF64_1024, riscvBitRevIndexTableF64_1024, RISCVBITREVINDEXTABLEF64_1024_TABLE_LENGTH }, + 2048U, + (float64_t *)twiddleCoefF64_rfft_2048 +}; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F64_4096) && defined(RISCV_TABLE_BITREVIDX_FLT64_4096) && defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F64_4096)) +const riscv_rfft_fast_instance_f64 riscv_rfft_fast_sR_f64_len4096 = { + { 2048, (const float64_t *)twiddleCoefF64_2048, riscvBitRevIndexTableF64_2048, RISCVBITREVINDEXTABLEF64_2048_TABLE_LENGTH }, + 4096U, + (float64_t *)twiddleCoefF64_rfft_4096 +}; +#endif + +/* Floating-point structs */ + + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F32_16) && defined(RISCV_TABLE_BITREVIDX_FLT_16) && defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F32_32)) +const riscv_rfft_fast_instance_f32 riscv_rfft_fast_sR_f32_len32 = { + { 16, twiddleCoef_16, riscvBitRevIndexTable16, RISCVBITREVINDEXTABLE_16_TABLE_LENGTH }, + 32U, + (float32_t *)twiddleCoef_rfft_32 +}; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F32_32) && defined(RISCV_TABLE_BITREVIDX_FLT_32) && defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F32_64)) +const riscv_rfft_fast_instance_f32 riscv_rfft_fast_sR_f32_len64 = { + { 32, twiddleCoef_32, riscvBitRevIndexTable32, RISCVBITREVINDEXTABLE_32_TABLE_LENGTH }, + 64U, + (float32_t *)twiddleCoef_rfft_64 +}; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F32_64) && defined(RISCV_TABLE_BITREVIDX_FLT_64) && defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F32_128)) +const riscv_rfft_fast_instance_f32 riscv_rfft_fast_sR_f32_len128 = { + { 64, twiddleCoef_64, riscvBitRevIndexTable64, RISCVBITREVINDEXTABLE_64_TABLE_LENGTH }, + 128U, + (float32_t *)twiddleCoef_rfft_128 +}; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F32_128) && defined(RISCV_TABLE_BITREVIDX_FLT_128) && defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F32_256)) +const riscv_rfft_fast_instance_f32 riscv_rfft_fast_sR_f32_len256 = { + { 128, twiddleCoef_128, riscvBitRevIndexTable128, RISCVBITREVINDEXTABLE_128_TABLE_LENGTH }, + 256U, + (float32_t *)twiddleCoef_rfft_256 +}; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F32_256) && defined(RISCV_TABLE_BITREVIDX_FLT_256) && defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F32_512)) +const riscv_rfft_fast_instance_f32 riscv_rfft_fast_sR_f32_len512 = { + { 256, twiddleCoef_256, riscvBitRevIndexTable256, RISCVBITREVINDEXTABLE_256_TABLE_LENGTH }, + 512U, + (float32_t *)twiddleCoef_rfft_512 +}; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F32_512) && defined(RISCV_TABLE_BITREVIDX_FLT_512) && defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F32_1024)) +const riscv_rfft_fast_instance_f32 riscv_rfft_fast_sR_f32_len1024 = { + { 512, twiddleCoef_512, riscvBitRevIndexTable512, RISCVBITREVINDEXTABLE_512_TABLE_LENGTH }, + 1024U, + (float32_t *)twiddleCoef_rfft_1024 +}; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F32_1024) && defined(RISCV_TABLE_BITREVIDX_FLT_1024) && defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F32_2048)) +const riscv_rfft_fast_instance_f32 riscv_rfft_fast_sR_f32_len2048 = { + { 1024, twiddleCoef_1024, riscvBitRevIndexTable1024, RISCVBITREVINDEXTABLE_1024_TABLE_LENGTH }, + 2048U, + (float32_t *)twiddleCoef_rfft_2048 +}; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F32_2048) && defined(RISCV_TABLE_BITREVIDX_FLT_2048) && defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F32_4096)) +const riscv_rfft_fast_instance_f32 riscv_rfft_fast_sR_f32_len4096 = { + { 2048, twiddleCoef_2048, riscvBitRevIndexTable2048, RISCVBITREVINDEXTABLE_2048_TABLE_LENGTH }, + 4096U, + (float32_t *)twiddleCoef_rfft_4096 +}; +#endif + + +/* Fixed-point structs */ +/* q31_t */ + + +/* + +Those structures cannot be used to initialize the MVE version of the FFT Q31 instances. +So they are not compiled when MVE is defined. + +For the MVE version, the new riscv_cfft_init_f32 must be used. + + +*/ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_REALCOEF_Q31) && defined(RISCV_TABLE_TWIDDLECOEF_Q31_16) && defined(RISCV_TABLE_BITREVIDX_FXT_16)) +const riscv_rfft_instance_q31 riscv_rfft_sR_q31_len32 = { + 32U, + 0, + 1, + 256U, + (q31_t*)realCoefAQ31, + (q31_t*)realCoefBQ31, + &riscv_cfft_sR_q31_len16 +}; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_REALCOEF_Q31) && defined(RISCV_TABLE_TWIDDLECOEF_Q31_32) && defined(RISCV_TABLE_BITREVIDX_FXT_32)) +const riscv_rfft_instance_q31 riscv_rfft_sR_q31_len64 = { + 64U, + 0, + 1, + 128U, + (q31_t*)realCoefAQ31, + (q31_t*)realCoefBQ31, + &riscv_cfft_sR_q31_len32 +}; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_REALCOEF_Q31) && defined(RISCV_TABLE_TWIDDLECOEF_Q31_64) && defined(RISCV_TABLE_BITREVIDX_FXT_64)) +const riscv_rfft_instance_q31 riscv_rfft_sR_q31_len128 = { + 128U, + 0, + 1, + 64U, + (q31_t*)realCoefAQ31, + (q31_t*)realCoefBQ31, + &riscv_cfft_sR_q31_len64 +}; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_REALCOEF_Q31) && defined(RISCV_TABLE_TWIDDLECOEF_Q31_128) && defined(RISCV_TABLE_BITREVIDX_FXT_128)) +const riscv_rfft_instance_q31 riscv_rfft_sR_q31_len256 = { + 256U, + 0, + 1, + 32U, + (q31_t*)realCoefAQ31, + (q31_t*)realCoefBQ31, + &riscv_cfft_sR_q31_len128 +}; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_REALCOEF_Q31) && defined(RISCV_TABLE_TWIDDLECOEF_Q31_256) && defined(RISCV_TABLE_BITREVIDX_FXT_256)) +const riscv_rfft_instance_q31 riscv_rfft_sR_q31_len512 = { + 512U, + 0, + 1, + 16U, + (q31_t*)realCoefAQ31, + (q31_t*)realCoefBQ31, + &riscv_cfft_sR_q31_len256 +}; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_REALCOEF_Q31) && defined(RISCV_TABLE_TWIDDLECOEF_Q31_512) && defined(RISCV_TABLE_BITREVIDX_FXT_512)) +const riscv_rfft_instance_q31 riscv_rfft_sR_q31_len1024 = { + 1024U, + 0, + 1, + 8U, + (q31_t*)realCoefAQ31, + (q31_t*)realCoefBQ31, + &riscv_cfft_sR_q31_len512 +}; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_REALCOEF_Q31) && defined(RISCV_TABLE_TWIDDLECOEF_Q31_1024) && defined(RISCV_TABLE_BITREVIDX_FXT_1024)) +const riscv_rfft_instance_q31 riscv_rfft_sR_q31_len2048 = { + 2048U, + 0, + 1, + 4U, + (q31_t*)realCoefAQ31, + (q31_t*)realCoefBQ31, + &riscv_cfft_sR_q31_len1024 +}; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_REALCOEF_Q31) && defined(RISCV_TABLE_TWIDDLECOEF_Q31_2048) && defined(RISCV_TABLE_BITREVIDX_FXT_2048)) +const riscv_rfft_instance_q31 riscv_rfft_sR_q31_len4096 = { + 4096U, + 0, + 1, + 2U, + (q31_t*)realCoefAQ31, + (q31_t*)realCoefBQ31, + &riscv_cfft_sR_q31_len2048 +}; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_REALCOEF_Q31) && defined(RISCV_TABLE_TWIDDLECOEF_Q31_4096) && defined(RISCV_TABLE_BITREVIDX_FXT_4096)) +const riscv_rfft_instance_q31 riscv_rfft_sR_q31_len8192 = { + 8192U, + 0, + 1, + 1U, + (q31_t*)realCoefAQ31, + (q31_t*)realCoefBQ31, + &riscv_cfft_sR_q31_len4096 +}; +#endif + + + +/* q15_t */ +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_REALCOEF_Q15) && defined(RISCV_TABLE_TWIDDLECOEF_Q15_16) && defined(RISCV_TABLE_BITREVIDX_FXT_16)) +const riscv_rfft_instance_q15 riscv_rfft_sR_q15_len32 = { + 32U, + 0, + 1, + 256U, + (q15_t*)realCoefAQ15, + (q15_t*)realCoefBQ15, + &riscv_cfft_sR_q15_len16 +}; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_REALCOEF_Q15) && defined(RISCV_TABLE_TWIDDLECOEF_Q15_32) && defined(RISCV_TABLE_BITREVIDX_FXT_32)) +const riscv_rfft_instance_q15 riscv_rfft_sR_q15_len64 = { + 64U, + 0, + 1, + 128U, + (q15_t*)realCoefAQ15, + (q15_t*)realCoefBQ15, + &riscv_cfft_sR_q15_len32 +}; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_REALCOEF_Q15) && defined(RISCV_TABLE_TWIDDLECOEF_Q15_64) && defined(RISCV_TABLE_BITREVIDX_FXT_64)) +const riscv_rfft_instance_q15 riscv_rfft_sR_q15_len128 = { + 128U, + 0, + 1, + 64U, + (q15_t*)realCoefAQ15, + (q15_t*)realCoefBQ15, + &riscv_cfft_sR_q15_len64 +}; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_REALCOEF_Q15) && defined(RISCV_TABLE_TWIDDLECOEF_Q15_128) && defined(RISCV_TABLE_BITREVIDX_FXT_128)) +const riscv_rfft_instance_q15 riscv_rfft_sR_q15_len256 = { + 256U, + 0, + 1, + 32U, + (q15_t*)realCoefAQ15, + (q15_t*)realCoefBQ15, + &riscv_cfft_sR_q15_len128 +}; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_REALCOEF_Q15) && defined(RISCV_TABLE_TWIDDLECOEF_Q15_256) && defined(RISCV_TABLE_BITREVIDX_FXT_256)) +const riscv_rfft_instance_q15 riscv_rfft_sR_q15_len512 = { + 512U, + 0, + 1, + 16U, + (q15_t*)realCoefAQ15, + (q15_t*)realCoefBQ15, + &riscv_cfft_sR_q15_len256 +}; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_REALCOEF_Q15) && defined(RISCV_TABLE_TWIDDLECOEF_Q15_512) && defined(RISCV_TABLE_BITREVIDX_FXT_512)) +const riscv_rfft_instance_q15 riscv_rfft_sR_q15_len1024 = { + 1024U, + 0, + 1, + 8U, + (q15_t*)realCoefAQ15, + (q15_t*)realCoefBQ15, + &riscv_cfft_sR_q15_len512 +}; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_REALCOEF_Q15) && defined(RISCV_TABLE_TWIDDLECOEF_Q15_1024) && defined(RISCV_TABLE_BITREVIDX_FXT_1024)) +const riscv_rfft_instance_q15 riscv_rfft_sR_q15_len2048 = { + 2048U, + 0, + 1, + 4U, + (q15_t*)realCoefAQ15, + (q15_t*)realCoefBQ15, + &riscv_cfft_sR_q15_len1024 +}; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_REALCOEF_Q15) && defined(RISCV_TABLE_TWIDDLECOEF_Q15_2048) && defined(RISCV_TABLE_BITREVIDX_FXT_2048)) +const riscv_rfft_instance_q15 riscv_rfft_sR_q15_len4096 = { + 4096U, + 0, + 1, + 2U, + (q15_t*)realCoefAQ15, + (q15_t*)realCoefBQ15, + &riscv_cfft_sR_q15_len2048 +}; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_REALCOEF_Q15) && defined(RISCV_TABLE_TWIDDLECOEF_Q15_4096) && defined(RISCV_TABLE_BITREVIDX_FXT_4096)) +const riscv_rfft_instance_q15 riscv_rfft_sR_q15_len8192 = { + 8192U, + 0, + 1, + 1U, + (q15_t*)realCoefAQ15, + (q15_t*)realCoefBQ15, + &riscv_cfft_sR_q15_len4096 +}; +#endif + + + +#endif diff --git a/components/nmsis/dsp/src/CommonTables/riscv_const_structs_f16.c b/components/nmsis/dsp/src/CommonTables/riscv_const_structs_f16.c new file mode 100644 index 00000000..19d6c750 --- /dev/null +++ b/components/nmsis/dsp/src/CommonTables/riscv_const_structs_f16.c @@ -0,0 +1,117 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_const_structs_f16.c + * Description: Constant structs that are initialized for user convenience. + * For example, some can be given as arguments to the riscv_cfft_f32() or riscv_rfft_f32() functions. + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "riscv_math_types_f16.h" + +#if defined(RISCV_FLOAT16_SUPPORTED) + +#include "riscv_const_structs_f16.h" + + +/* +ALLOW TABLE is true when config table is enabled and the Tramsform folder is included +for compilation. +*/ +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_FFT_ALLOW_TABLES) + + +/* Floating-point structs */ + + +/* + +Those structures cannot be used to initialize the MVE version of the FFT F32 instances. +So they are not compiled when MVE is defined. + +For the MVE version, the new riscv_cfft_init_f16 must be used. + + +*/ + + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F16_16) && defined(RISCV_TABLE_BITREVIDX_FLT_16)) +const riscv_cfft_instance_f16 riscv_cfft_sR_f16_len16 = { + 16, twiddleCoefF16_16, riscvBitRevIndexTable_fixed_16, RISCVBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH +}; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F16_32) && defined(RISCV_TABLE_BITREVIDX_FLT_32)) +const riscv_cfft_instance_f16 riscv_cfft_sR_f16_len32 = { + 32, twiddleCoefF16_32, riscvBitRevIndexTable_fixed_32, RISCVBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH +}; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F16_64) && defined(RISCV_TABLE_BITREVIDX_FLT_64)) +const riscv_cfft_instance_f16 riscv_cfft_sR_f16_len64 = { + 64, twiddleCoefF16_64, riscvBitRevIndexTable_fixed_64, RISCVBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH +}; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F16_128) && defined(RISCV_TABLE_BITREVIDX_FLT_128)) +const riscv_cfft_instance_f16 riscv_cfft_sR_f16_len128 = { + 128, twiddleCoefF16_128, riscvBitRevIndexTable_fixed_128, RISCVBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH +}; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F16_256) && defined(RISCV_TABLE_BITREVIDX_FLT_256)) +const riscv_cfft_instance_f16 riscv_cfft_sR_f16_len256 = { + 256, twiddleCoefF16_256, riscvBitRevIndexTable_fixed_256, RISCVBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH +}; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F16_512) && defined(RISCV_TABLE_BITREVIDX_FLT_512)) +const riscv_cfft_instance_f16 riscv_cfft_sR_f16_len512 = { + 512, twiddleCoefF16_512, riscvBitRevIndexTable_fixed_512, RISCVBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH +}; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F16_1024) && defined(RISCV_TABLE_BITREVIDX_FLT_1024)) +const riscv_cfft_instance_f16 riscv_cfft_sR_f16_len1024 = { + 1024, twiddleCoefF16_1024, riscvBitRevIndexTable_fixed_1024, RISCVBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH +}; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F16_2048) && defined(RISCV_TABLE_BITREVIDX_FLT_2048)) +const riscv_cfft_instance_f16 riscv_cfft_sR_f16_len2048 = { + 2048, twiddleCoefF16_2048, riscvBitRevIndexTable_fixed_2048, RISCVBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH +}; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F16_4096) && defined(RISCV_TABLE_BITREVIDX_FLT_4096)) +const riscv_cfft_instance_f16 riscv_cfft_sR_f16_len4096 = { + 4096, twiddleCoefF16_4096, riscvBitRevIndexTable_fixed_4096, RISCVBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH +}; +#endif + + + +#endif + +#endif diff --git a/components/nmsis/dsp/src/CommonTables/riscv_mve_tables.c b/components/nmsis/dsp/src/CommonTables/riscv_mve_tables.c new file mode 100644 index 00000000..32bee808 --- /dev/null +++ b/components/nmsis/dsp/src/CommonTables/riscv_mve_tables.c @@ -0,0 +1,39 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_mve_tables.c + * Description: common tables like fft twiddle factors, Bitreverse, reciprocal etc + * used for MVE implementation only + * + * $Date: 23 April 2021 + * + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#include "riscv_math_types.h" + + + + + + diff --git a/components/nmsis/dsp/src/CommonTables/riscv_mve_tables_f16.c b/components/nmsis/dsp/src/CommonTables/riscv_mve_tables_f16.c new file mode 100644 index 00000000..db8d2676 --- /dev/null +++ b/components/nmsis/dsp/src/CommonTables/riscv_mve_tables_f16.c @@ -0,0 +1,37 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_mve_tables_f16.c + * Description: common tables like fft twiddle factors, Bitreverse, reciprocal etc + * used for MVE implementation only + * + * $Date: 23 April 2021 + * + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "riscv_math_types_f16.h" + +#if defined(RISCV_FLOAT16_SUPPORTED) + + +#endif /* if defined(RISCV_FLOAT16_SUPPORTED) */ diff --git a/components/nmsis/dsp/src/ComplexMathFunctions/ComplexMathFunctions.c b/components/nmsis/dsp/src/ComplexMathFunctions/ComplexMathFunctions.c new file mode 100644 index 00000000..11226f5a --- /dev/null +++ b/components/nmsis/dsp/src/ComplexMathFunctions/ComplexMathFunctions.c @@ -0,0 +1,47 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: CompexMathFunctions.c + * Description: Combination of all comlex math function source files. + * + * $Date: 18. March 2019 + * $Revision: V1.0.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2019 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "riscv_cmplx_conj_f32.c" +#include "riscv_cmplx_conj_q15.c" +#include "riscv_cmplx_conj_q31.c" +#include "riscv_cmplx_dot_prod_f32.c" +#include "riscv_cmplx_dot_prod_q15.c" +#include "riscv_cmplx_dot_prod_q31.c" +#include "riscv_cmplx_mag_f32.c" +#include "riscv_cmplx_mag_q15.c" +#include "riscv_cmplx_mag_q31.c" +#include "riscv_cmplx_mag_squared_f32.c" +#include "riscv_cmplx_mag_squared_q15.c" +#include "riscv_cmplx_mag_squared_q31.c" +#include "riscv_cmplx_mult_cmplx_f32.c" +#include "riscv_cmplx_mult_cmplx_q15.c" +#include "riscv_cmplx_mult_cmplx_q31.c" +#include "riscv_cmplx_mult_real_f32.c" +#include "riscv_cmplx_mult_real_q15.c" +#include "riscv_cmplx_mult_real_q31.c" diff --git a/components/nmsis/dsp/src/ComplexMathFunctions/ComplexMathFunctionsF16.c b/components/nmsis/dsp/src/ComplexMathFunctions/ComplexMathFunctionsF16.c new file mode 100644 index 00000000..193dfa19 --- /dev/null +++ b/components/nmsis/dsp/src/ComplexMathFunctions/ComplexMathFunctionsF16.c @@ -0,0 +1,33 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: CompexMathFunctionsF16.c + * Description: Combination of all complex math function f16 source files. + * + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2020 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "riscv_cmplx_conj_f16.c" +#include "riscv_cmplx_dot_prod_f16.c" +#include "riscv_cmplx_mag_f16.c" +#include "riscv_cmplx_mag_squared_f16.c" +#include "riscv_cmplx_mult_cmplx_f16.c" +#include "riscv_cmplx_mult_real_f16.c" diff --git a/components/nmsis/dsp/src/ComplexMathFunctions/riscv_cmplx_conj_f16.c b/components/nmsis/dsp/src/ComplexMathFunctions/riscv_cmplx_conj_f16.c new file mode 100644 index 00000000..d35e39d7 --- /dev/null +++ b/components/nmsis/dsp/src/ComplexMathFunctions/riscv_cmplx_conj_f16.c @@ -0,0 +1,133 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_cmplx_conj_f16.c + * Description: Floating-point complex conjugate + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/complex_math_functions_f16.h" + +#if defined(RISCV_FLOAT16_SUPPORTED) +/** + @ingroup groupCmplxMath + */ + +/** + @defgroup cmplx_conj Complex Conjugate + + Conjugates the elements of a complex data vector. + + The pSrc points to the source data and + pDst points to the destination data where the result should be written. + numSamples specifies the number of complex samples + and the data in each array is stored in an interleaved fashion + (real, imag, real, imag, ...). + Each array has a total of 2*numSamples values. + + The underlying algorithm is used: + 
+  for (n = 0; n < numSamples; n++) {
+      pDst[(2*n)  ] =  pSrc[(2*n)  ];    // real part
+      pDst[(2*n)+1] = -pSrc[(2*n)+1];    // imag part
+  }
+
+ + There are separate functions for floating-point, Q15, and Q31 data types. + */ + +/** + @addtogroup cmplx_conj + @{ + */ + +/** + @brief Floating-point complex conjugate. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] numSamples number of samples in each vector + @return none + */ + +void riscv_cmplx_conj_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[0] + jC[1] = A[0]+ j(-1)A[1] */ + + /* Calculate Complex Conjugate and store result in destination buffer. */ + *pDst++ = *pSrc++; + *pDst++ = -*pSrc++; + + *pDst++ = *pSrc++; + *pDst++ = -*pSrc++; + + *pDst++ = *pSrc++; + *pDst++ = -*pSrc++; + + *pDst++ = *pSrc++; + *pDst++ = -*pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C[0] + jC[1] = A[0]+ j(-1)A[1] */ + + /* Calculate Complex Conjugate and store result in destination buffer. */ + *pDst++ = *pSrc++; + *pDst++ = -*pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of cmplx_conj group + */ +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ diff --git a/components/nmsis/dsp/src/ComplexMathFunctions/riscv_cmplx_conj_f32.c b/components/nmsis/dsp/src/ComplexMathFunctions/riscv_cmplx_conj_f32.c new file mode 100644 index 00000000..6092a23c --- /dev/null +++ b/components/nmsis/dsp/src/ComplexMathFunctions/riscv_cmplx_conj_f32.c @@ -0,0 +1,154 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_cmplx_conj_f32.c + * Description: Floating-point complex conjugate + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @defgroup cmplx_conj Complex Conjugate + + Conjugates the elements of a complex data vector. + + The pSrc points to the source data and + pDst points to the destination data where the result should be written. + numSamples specifies the number of complex samples + and the data in each array is stored in an interleaved fashion + (real, imag, real, imag, ...). + Each array has a total of 2*numSamples values. + + The underlying algorithm is used: + 
+  for (n = 0; n < numSamples; n++) {
+      pDst[(2*n)  ] =  pSrc[(2*n)  ];    // real part
+      pDst[(2*n)+1] = -pSrc[(2*n)+1];    // imag part
+  }
+
+ + There are separate functions for floating-point, Q15, and Q31 data types. + */ + +/** + @addtogroup cmplx_conj + @{ + */ + +/** + @brief Floating-point complex conjugate. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] numSamples number of samples in each vector + @return none + */ + +void riscv_cmplx_conj_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = numSamples; /* Loop counter */ + size_t l; + l = vsetvl_e32m8(blkCnt); + const float32_t * input = pSrc; + float32_t * output = pDst; + ptrdiff_t bstride = 8; + vfloat32m8_t v_R,v_I; + vfloat32m8_t v0; + v0 = vfsub_vv_f32m8(v0, v0, l); /* vector 0 */ + for (; (l = vsetvl_e32m8(blkCnt)) > 0; blkCnt -= l) + { + v_R = vlse32_v_f32m8(input, bstride, l); + input++; + vsse32_v_f32m8 (output, bstride, v_R, l); + output++; + v_I = vfsub_vv_f32m8(v0, vlse32_v_f32m8(input, bstride, l), l); + input += (l*2-1); + vsse32_v_f32m8 (output, bstride, v_I, l); + output += (l*2-1); + } + +#else + uint32_t blkCnt; /* Loop counter */ + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[0] + jC[1] = A[0]+ j(-1)A[1] */ + + /* Calculate Complex Conjugate and store result in destination buffer. */ + *pDst++ = *pSrc++; + *pDst++ = -*pSrc++; + + *pDst++ = *pSrc++; + *pDst++ = -*pSrc++; + + *pDst++ = *pSrc++; + *pDst++ = -*pSrc++; + + *pDst++ = *pSrc++; + *pDst++ = -*pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C[0] + jC[1] = A[0]+ j(-1)A[1] */ + + /* Calculate Complex Conjugate and store result in destination buffer. */ + *pDst++ = *pSrc++; + *pDst++ = -*pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of cmplx_conj group + */ diff --git a/components/nmsis/dsp/src/ComplexMathFunctions/riscv_cmplx_conj_q15.c b/components/nmsis/dsp/src/ComplexMathFunctions/riscv_cmplx_conj_q15.c new file mode 100644 index 00000000..56a345d8 --- /dev/null +++ b/components/nmsis/dsp/src/ComplexMathFunctions/riscv_cmplx_conj_q15.c @@ -0,0 +1,190 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_cmplx_conj_q15.c + * Description: Q15 complex conjugate + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @addtogroup cmplx_conj + @{ + */ + +/** + @brief Q15 complex conjugate. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] numSamples number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + The Q15 value -1 (0x8000) is saturated to the maximum allowable positive value 0x7FFF. + */ + + +void riscv_cmplx_conj_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = numSamples; /* Loop counter */ + size_t l; + l = vsetvl_e32m8(blkCnt); + const q15_t * input = pSrc; + q15_t * output = pDst; + ptrdiff_t bstride = 4; + vint16m8_t v_R,v_I; + vint16m8_t v0; + v0 = vxor_vv_i16m8(v0, v0, l); /* vector 0 */ + for (; (l = vsetvl_e16m8(blkCnt)) > 0; blkCnt -= l) + { + v_R = vlse16_v_i16m8(input, bstride, l); + input++; + vsse16_v_i16m8 (output, bstride, v_R, l); + output++; + v_I = vsub_vv_i16m8(v0, vlse16_v_i16m8(input, bstride, l), l); + input += (l*2-1); + vsse16_v_i16m8 (output, bstride, v_I, l); + output += (l*2-1); + } + +#else + uint32_t blkCnt; /* Loop counter */ + q31_t in1; /* Temporary input variable */ + +#if defined (RISCV_MATH_LOOPUNROLL) && defined (RISCV_MATH_DSP) +#if __RISCV_XLEN == 64 + q63_t in641, in642, in643, in644; +#else + q31_t in2, in3, in4; /* Temporary input variables */ +#endif /* __RISCV_XLEN == 64 */ +#endif + + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[0] + jC[1] = A[0]+ j(-1)A[1] */ + + /* Calculate Complex Conjugate and store result in destination buffer. */ + +#if defined (RISCV_MATH_DSP) +#if __RISCV_XLEN == 64 + in641 = read_q15x4_ia ((q15_t **) &pSrc); + in641 = __RV_KCRAS16(0, in641); + in641 = ((((uint64_t)in641) >> 48) << 32) | (((((uint64_t)in641) << 16) >> 48) << 48) | (((((uint64_t)in641) << 32) >> 48)) | (((((uint64_t)in641) << 48) >> 32)); + write_q15x4_ia (&pDst, in641); + in641 = read_q15x4_ia ((q15_t **) &pSrc); + in641 = __RV_KCRAS16(0, in641); + in641 = ((((uint64_t)in641) >> 48) << 32) | (((((uint64_t)in641) << 16) >> 48) << 48) | (((((uint64_t)in641) << 32) >> 48)) | (((((uint64_t)in641) << 48) >> 32)); + write_q15x4_ia (&pDst, in641); +#else + in1 = read_q15x2_ia ((q15_t **) &pSrc); + in2 = read_q15x2_ia ((q15_t **) &pSrc); + in3 = read_q15x2_ia ((q15_t **) &pSrc); + in4 = read_q15x2_ia ((q15_t **) &pSrc); + + in1 = __RV_KCRAS16(0, in1); + in2 = __RV_KCRAS16(0, in2); + in3 = __RV_KCRAS16(0, in3); + in4 = __RV_KCRAS16(0, in4); + + in1 = ((uint32_t) in1 >> 16) | ((uint32_t) in1 << 16); + in2 = ((uint32_t) in2 >> 16) | ((uint32_t) in2 << 16); + in3 = ((uint32_t) in3 >> 16) | ((uint32_t) in3 << 16); + in4 = ((uint32_t) in4 >> 16) | ((uint32_t) in4 << 16); + + write_q15x2_ia (&pDst, in1); + write_q15x2_ia (&pDst, in2); + write_q15x2_ia (&pDst, in3); + write_q15x2_ia (&pDst, in4); +#endif /* __RISCV_XLEN == 64 */ +#else + *pDst++ = *pSrc++; + in1 = *pSrc++; + *pDst++ = (in1 == (q15_t) 0x8000) ? (q15_t) 0x7fff : -in1; + + *pDst++ = *pSrc++; + in1 = *pSrc++; + *pDst++ = (in1 == (q15_t) 0x8000) ? (q15_t) 0x7fff : -in1; + + *pDst++ = *pSrc++; + in1 = *pSrc++; + *pDst++ = (in1 == (q15_t) 0x8000) ? (q15_t) 0x7fff : -in1; + + *pDst++ = *pSrc++; + in1 = *pSrc++; + *pDst++ = (in1 == (q15_t) 0x8000) ? (q15_t) 0x7fff : -in1; + +#endif /* #if defined (RISCV_MATH_DSP) */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C[0] + jC[1] = A[0]+ j(-1)A[1] */ + + /* Calculate Complex Conjugate and store result in destination buffer. */ + *pDst++ = *pSrc++; + in1 = *pSrc++; +// #if defined (RISCV_MATH_DSP) +// *pDst++ = __SSAT(-in1, 16); +// #else + *pDst++ = (in1 == (q15_t) 0x8000) ? (q15_t) 0x7fff : -in1; +// #endif + + /* Decrement loop counter */ + blkCnt--; + } +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of cmplx_conj group + */ diff --git a/components/nmsis/dsp/src/ComplexMathFunctions/riscv_cmplx_conj_q31.c b/components/nmsis/dsp/src/ComplexMathFunctions/riscv_cmplx_conj_q31.c new file mode 100644 index 00000000..5e2ef66c --- /dev/null +++ b/components/nmsis/dsp/src/ComplexMathFunctions/riscv_cmplx_conj_q31.c @@ -0,0 +1,173 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_cmplx_conj_q31.c + * Description: Q31 complex conjugate + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @addtogroup cmplx_conj + @{ + */ + +/** + @brief Q31 complex conjugate. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] numSamples number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + The Q31 value -1 (0x80000000) is saturated to the maximum allowable positive value 0x7FFFFFFF. + */ + + +void riscv_cmplx_conj_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = numSamples; /* Loop counter */ + size_t l; + l = vsetvl_e32m8(blkCnt); + const q31_t * input = pSrc; + q31_t * output = pDst; + ptrdiff_t bstride = 8; + vint32m8_t v_R,v_I; + vint32m8_t v0; + v0 = vxor_vv_i32m8(v0, v0, l); /* vector 0 */ + for (; (l = vsetvl_e32m8(blkCnt)) > 0; blkCnt -= l) + { + v_R = vlse32_v_i32m8(input, bstride, l); + input++; + vsse32_v_i32m8 (output, bstride, v_R, l); + output++; + v_I = vsub_vv_i32m8(v0, vlse32_v_i32m8(input, bstride, l), l); + input += (l*2-1); + vsse32_v_i32m8 (output, bstride, v_I, l); + output += (l*2-1); + } + +#else + uint32_t blkCnt; /* Loop counter */ + q31_t in; /* Temporary input variable */ + +#if defined (RISCV_MATH_LOOPUNROLL) +#if __RISCV_XLEN == 64 +q63_t in64; +#endif /* __RISCV_XLEN == 64 */ + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[0] + jC[1] = A[0]+ j(-1)A[1] */ +#if __RISCV_XLEN == 64 + in64 = read_q31x2_ia ((q31_t **) &pSrc); + write_q15x4_ia (&pDst, __RV_STSA32(0,in64)); + in64 = read_q31x2_ia ((q31_t **) &pSrc); + write_q15x4_ia (&pDst, __RV_STSA32(0,in64)); + in64 = read_q31x2_ia ((q31_t **) &pSrc); + write_q15x4_ia (&pDst, __RV_STSA32(0,in64)); + in64 = read_q31x2_ia ((q31_t **) &pSrc); + write_q15x4_ia (&pDst, __RV_STSA32(0,in64)); +#else + /* Calculate Complex Conjugate and store result in destination buffer. */ + *pDst++ = *pSrc++; + in = *pSrc++; +#if defined (RISCV_MATH_DSP) + *pDst++ = __QSUB(0, in); +#else + *pDst++ = (in == INT32_MIN) ? INT32_MAX : -in; +#endif + + *pDst++ = *pSrc++; + in = *pSrc++; +#if defined (RISCV_MATH_DSP) + *pDst++ = __QSUB(0, in); +#else + *pDst++ = (in == INT32_MIN) ? INT32_MAX : -in; +#endif + + *pDst++ = *pSrc++; + in = *pSrc++; +#if defined (RISCV_MATH_DSP) + *pDst++ = __QSUB(0, in); +#else + *pDst++ = (in == INT32_MIN) ? INT32_MAX : -in; +#endif + + *pDst++ = *pSrc++; + in = *pSrc++; +#if defined (RISCV_MATH_DSP) + *pDst++ = __QSUB(0, in); +#else + *pDst++ = (in == INT32_MIN) ? INT32_MAX : -in; +#endif +#endif /* __RISCV_XLEN == 64 */ + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C[0] + jC[1] = A[0]+ j(-1)A[1] */ + + /* Calculate Complex Conjugate and store result in destination buffer. */ + *pDst++ = *pSrc++; + in = *pSrc++; +#if defined (RISCV_MATH_DSP) + *pDst++ = __QSUB(0, in); +#else + *pDst++ = (in == INT32_MIN) ? INT32_MAX : -in; +#endif + + /* Decrement loop counter */ + blkCnt--; + } +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of cmplx_conj group + */ diff --git a/components/nmsis/dsp/src/ComplexMathFunctions/riscv_cmplx_dot_prod_f16.c b/components/nmsis/dsp/src/ComplexMathFunctions/riscv_cmplx_dot_prod_f16.c new file mode 100644 index 00000000..3790b354 --- /dev/null +++ b/components/nmsis/dsp/src/ComplexMathFunctions/riscv_cmplx_dot_prod_f16.c @@ -0,0 +1,178 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_cmplx_dot_prod_f16.c + * Description: Floating-point complex dot product + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/complex_math_functions_f16.h" + +#if defined(RISCV_FLOAT16_SUPPORTED) + + +/** + @ingroup groupCmplxMath + */ + +/** + @defgroup cmplx_dot_prod Complex Dot Product + + Computes the dot product of two complex vectors. + The vectors are multiplied element-by-element and then summed. + + The pSrcA points to the first complex input vector and + pSrcB points to the second complex input vector. + numSamples specifies the number of complex samples + and the data in each array is stored in an interleaved fashion + (real, imag, real, imag, ...). + Each array has a total of 2*numSamples values. + + The underlying algorithm is used: + + 
+  realResult = 0;
+  imagResult = 0;
+  for (n = 0; n < numSamples; n++) {
+      realResult += pSrcA[(2*n)+0] * pSrcB[(2*n)+0] - pSrcA[(2*n)+1] * pSrcB[(2*n)+1];
+      imagResult += pSrcA[(2*n)+0] * pSrcB[(2*n)+1] + pSrcA[(2*n)+1] * pSrcB[(2*n)+0];
+  }
+
+ + There are separate functions for floating-point, Q15, and Q31 data types. + */ + +/** + @addtogroup cmplx_dot_prod + @{ + */ + +/** + @brief Floating-point complex dot product. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[in] numSamples number of samples in each vector + @param[out] realResult real part of the result returned here + @param[out] imagResult imaginary part of the result returned here + @return none + */ + +void riscv_cmplx_dot_prod_f16( + const float16_t * pSrcA, + const float16_t * pSrcB, + uint32_t numSamples, + float16_t * realResult, + float16_t * imagResult) +{ + uint32_t blkCnt; /* Loop counter */ + _Float16 real_sum = 0.0f, imag_sum = 0.0f; /* Temporary result variables */ + _Float16 a0,b0,c0,d0; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += a0 * c0; + imag_sum += a0 * d0; + real_sum -= b0 * d0; + imag_sum += b0 * c0; + + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += a0 * c0; + imag_sum += a0 * d0; + real_sum -= b0 * d0; + imag_sum += b0 * c0; + + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += a0 * c0; + imag_sum += a0 * d0; + real_sum -= b0 * d0; + imag_sum += b0 * c0; + + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += a0 * c0; + imag_sum += a0 * d0; + real_sum -= b0 * d0; + imag_sum += b0 * c0; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += a0 * c0; + imag_sum += a0 * d0; + real_sum -= b0 * d0; + imag_sum += b0 * c0; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store real and imaginary result in destination buffer. */ + *realResult = real_sum; + *imagResult = imag_sum; +} + +/** + @} end of cmplx_dot_prod group + */ + +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ diff --git a/components/nmsis/dsp/src/ComplexMathFunctions/riscv_cmplx_dot_prod_f32.c b/components/nmsis/dsp/src/ComplexMathFunctions/riscv_cmplx_dot_prod_f32.c new file mode 100644 index 00000000..18ebfc85 --- /dev/null +++ b/components/nmsis/dsp/src/ComplexMathFunctions/riscv_cmplx_dot_prod_f32.c @@ -0,0 +1,204 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_cmplx_dot_prod_f32.c + * Description: Floating-point complex dot product + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @defgroup cmplx_dot_prod Complex Dot Product + + Computes the dot product of two complex vectors. + The vectors are multiplied element-by-element and then summed. + + The pSrcA points to the first complex input vector and + pSrcB points to the second complex input vector. + numSamples specifies the number of complex samples + and the data in each array is stored in an interleaved fashion + (real, imag, real, imag, ...). + Each array has a total of 2*numSamples values. + + The underlying algorithm is used: + + 
+  realResult = 0;
+  imagResult = 0;
+  for (n = 0; n < numSamples; n++) {
+      realResult += pSrcA[(2*n)+0] * pSrcB[(2*n)+0] - pSrcA[(2*n)+1] * pSrcB[(2*n)+1];
+      imagResult += pSrcA[(2*n)+0] * pSrcB[(2*n)+1] + pSrcA[(2*n)+1] * pSrcB[(2*n)+0];
+  }
+
+ + There are separate functions for floating-point, Q15, and Q31 data types. + */ + +/** + @addtogroup cmplx_dot_prod + @{ + */ + +/** + @brief Floating-point complex dot product. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[in] numSamples number of samples in each vector + @param[out] realResult real part of the result returned here + @param[out] imagResult imaginary part of the result returned here + @return none + */ + +void riscv_cmplx_dot_prod_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + uint32_t numSamples, + float32_t * realResult, + float32_t * imagResult) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = numSamples; /* Loop counter */ + size_t l; + const float32_t * inputA = pSrcA; + const float32_t * inputB = pSrcB; + ptrdiff_t bstride = 8; + vfloat32m8_t v_R1, v_R2, v_I1, v_I2; + vfloat32m8_t v_RR, v_II, v_RI, v_IR; + vfloat32m1_t v_dst; /* I don't know what the effect is */ + l = vsetvl_e32m1(1); + vfloat32m1_t v_real = vfmv_s_f_f32m1(v_real, 0, l); + vfloat32m1_t v_imag = vfmv_s_f_f32m1(v_imag, 0, l); /* Initialize accumulated value */ + for (; (l = vsetvl_e32m8(blkCnt)) > 0; blkCnt -= l) + { + v_R1 = vlse32_v_f32m8(inputA, bstride, l); + v_R2 = vlse32_v_f32m8(inputB, bstride, l); + inputA++; inputB++; /* Point to the first complex pointer */ + v_I1 = vlse32_v_f32m8(inputA, bstride, l); + v_I2 = vlse32_v_f32m8(inputB, bstride, l); + v_RR = vfmul_vv_f32m8(v_R1, v_R2, l); + v_II = vfmul_vv_f32m8(v_I1, v_I2, l); + v_RI = vfmul_vv_f32m8(v_R1, v_I2, l); + v_IR = vfmul_vv_f32m8(v_I1, v_R2, l); + v_real = vfredsum_vs_f32m8_f32m1(v_real, vfsub_vv_f32m8(v_RR, v_II, l), v_real, l); + v_imag = vfredsum_vs_f32m8_f32m1(v_imag, vfadd_vv_f32m8(v_RI, v_IR, l), v_imag, l); + inputA += (l*2-1); inputB += (l*2-1); + } + *realResult = vfmv_f_s_f32m1_f32(v_real); + *imagResult = vfmv_f_s_f32m1_f32(v_imag); +#else + uint32_t blkCnt; /* Loop counter */ + float32_t real_sum = 0.0f, imag_sum = 0.0f; /* Temporary result variables */ + float32_t a0,b0,c0,d0; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += a0 * c0; + imag_sum += a0 * d0; + real_sum -= b0 * d0; + imag_sum += b0 * c0; + + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += a0 * c0; + imag_sum += a0 * d0; + real_sum -= b0 * d0; + imag_sum += b0 * c0; + + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += a0 * c0; + imag_sum += a0 * d0; + real_sum -= b0 * d0; + imag_sum += b0 * c0; + + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += a0 * c0; + imag_sum += a0 * d0; + real_sum -= b0 * d0; + imag_sum += b0 * c0; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += a0 * c0; + imag_sum += a0 * d0; + real_sum -= b0 * d0; + imag_sum += b0 * c0; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store real and imaginary result in destination buffer. */ + *realResult = real_sum; + *imagResult = imag_sum; +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of cmplx_dot_prod group + */ diff --git a/components/nmsis/dsp/src/ComplexMathFunctions/riscv_cmplx_dot_prod_q15.c b/components/nmsis/dsp/src/ComplexMathFunctions/riscv_cmplx_dot_prod_q15.c new file mode 100644 index 00000000..33b26d62 --- /dev/null +++ b/components/nmsis/dsp/src/ComplexMathFunctions/riscv_cmplx_dot_prod_q15.c @@ -0,0 +1,247 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_cmplx_dot_prod_q15.c + * Description: Processing function for the Q15 Complex Dot product + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @addtogroup cmplx_dot_prod + @{ + */ + +/** + @brief Q15 complex dot product. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[in] numSamples number of samples in each vector + @param[out] realResult real part of the result returned here + @param[out] imagResult imaginary part of the result returned her + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The intermediate 1.15 by 1.15 multiplications are performed with full precision and yield a 2.30 result. + These are accumulated in a 64-bit accumulator with 34.30 precision. + As a final step, the accumulators are converted to 8.24 format. + The return results realResult and imagResult are in 8.24 format. + */ + +void riscv_cmplx_dot_prod_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + uint32_t numSamples, + q31_t * realResult, + q31_t * imagResult) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = numSamples; /* Loop counter */ + size_t l; + const q15_t * inputA = pSrcA; + const q15_t * inputB = pSrcB; + ptrdiff_t bstride = 4; + vint16m4_t v_R1, v_R2, v_I1, v_I2; + vint32m8_t v_RR, v_II, v_RI, v_IR; + // vint32m1_t v_dst; /* I don't know what the effect is */ + l = vsetvl_e64m1(1); + vint64m1_t v_real = vmv_s_x_i64m1(v_real, 0, l); + vint64m1_t v_dst = vmv_s_x_i64m1(v_dst, 0, l); + vint64m1_t v_imag = vmv_s_x_i64m1(v_imag, 0, l); + /* Initialize accumulated value */ + for (; (l = vsetvl_e16m8(blkCnt)) > 0; blkCnt -= l) + { + v_R1 = vlse16_v_i16m4(inputA, bstride, l); + v_R2 = vlse16_v_i16m4(inputB, bstride, l); + inputA++; inputB++; /* Point to the first complex pointer */ + v_I1 = vlse16_v_i16m4(inputA, bstride, l); + v_I2 = vlse16_v_i16m4(inputB, bstride, l); + v_RR = vwmul_vv_i32m8(v_R1, v_R2, l); + v_II = vwmul_vv_i32m8(v_I1, v_I2, l); + v_RI = vwmul_vv_i32m8(v_R1, v_I2, l); + v_IR = vwmul_vv_i32m8(v_I1, v_R2, l); + v_real = vwredsum_vs_i32m8_i64m1(v_dst, vssub_vv_i32m8(v_RR, v_II, l), v_real, l); + v_imag = vwredsum_vs_i32m8_i64m1(v_dst, vsadd_vv_i32m8(v_RI, v_IR, l), v_imag, l); + inputA += (l*2-1); inputB += (l*2-1); + } + vsetvl_e64m1(1); + *realResult = (q31_t)(vmv_x_s_i64m1_i64(v_real)>> 6); + *imagResult = (q31_t)(vmv_x_s_i64m1_i64(v_imag)>> 6); +#else + uint32_t blkCnt; /* Loop counter */ + q63_t real_sum = 0, imag_sum = 0; /* Temporary result variables */ +#if __RISCV_XLEN == 64 + q31_t RESA,RESB; +#endif /* __RISCV_XLEN == 64 */ + q15_t a0,b0,c0,d0; + +#if defined (RISCV_MATH_LOOPUNROLL) + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { +#if __RISCV_XLEN == 64 + RESA = read_q15x2_ia((q15_t **) &pSrcA); + RESB = read_q15x2_ia((q15_t **) &pSrcB); + real_sum += __RV_SMALDRS(0,RESA,RESB); + imag_sum += __RV_SMALXDA(0,RESA,RESB); + + RESA = read_q15x2_ia((q15_t **) &pSrcA); + RESB = read_q15x2_ia((q15_t **) &pSrcB); + real_sum += __RV_SMALDRS(0,RESA,RESB); + imag_sum += __RV_SMALXDA(0,RESA,RESB); + + RESA = read_q15x2_ia((q15_t **) &pSrcA); + RESB = read_q15x2_ia((q15_t **) &pSrcB); + real_sum += __RV_SMALDRS(0,RESA,RESB); + imag_sum += __RV_SMALXDA(0,RESA,RESB); + + RESA = read_q15x2_ia((q15_t **) &pSrcA); + RESB = read_q15x2_ia((q15_t **) &pSrcB); + real_sum += __RV_SMALDRS(0,RESA,RESB); + imag_sum += __RV_SMALXDA(0,RESA,RESB); +#else + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + +#if defined (RISCV_MATH_DSP) + real_sum = __SMALBB(real_sum, a0, c0); + imag_sum = __SMALBB(imag_sum, a0, d0); + real_sum = __SMSLDA(real_sum, b0, d0); + imag_sum = __SMALBB(imag_sum, b0, c0); +#else + real_sum += (q31_t)a0 * c0; + imag_sum += (q31_t)a0 * d0; + real_sum -= (q31_t)b0 * d0; + imag_sum += (q31_t)b0 * c0; +#endif + + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + +#if defined (RISCV_MATH_DSP) + real_sum = __SMALBB(real_sum, a0, c0); + imag_sum = __SMALBB(imag_sum, a0, d0); + real_sum = __SMSLDA(real_sum, b0, d0); + imag_sum = __SMALBB(imag_sum, b0, c0); +#else + real_sum += (q31_t)a0 * c0; + imag_sum += (q31_t)a0 * d0; + real_sum -= (q31_t)b0 * d0; + imag_sum += (q31_t)b0 * c0; +#endif + + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + +#if defined (RISCV_MATH_DSP) + real_sum = __SMALBB(real_sum, a0, c0); + imag_sum = __SMALBB(imag_sum, a0, d0); + real_sum = __SMSLDA(real_sum, b0, d0); + imag_sum = __SMALBB(imag_sum, b0, c0); +#else + real_sum += (q31_t)a0 * c0; + imag_sum += (q31_t)a0 * d0; + real_sum -= (q31_t)b0 * d0; + imag_sum += (q31_t)b0 * c0; +#endif + + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + +#if defined(RISCV_MATH_DSP) + real_sum = __SMALBB(real_sum, a0, c0); + imag_sum = __SMALBB(imag_sum, a0, d0); + real_sum = __SMSLDA(real_sum, b0, d0); + imag_sum = __SMALBB(imag_sum, b0, c0); +#else + real_sum += (q31_t)a0 * c0; + imag_sum += (q31_t)a0 * d0; + real_sum -= (q31_t)b0 * d0; + imag_sum += (q31_t)b0 * c0; +#endif +#endif /* __RISCV_XLEN == 64 */ + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + +// #if defined(RISCV_MATH_DSP) +// real_sum = __SMALBB(real_sum, a0, c0); +// imag_sum = __SMALBB(imag_sum, a0, d0); +// real_sum = __SMSLDA(real_sum, b0, d0); +// imag_sum = __SMALBB(imag_sum, b0, c0); +// #else + real_sum += (q31_t)a0 * c0; + imag_sum += (q31_t)a0 * d0; + real_sum -= (q31_t)b0 * d0; + imag_sum += (q31_t)b0 * c0; +// #endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store real and imaginary result in 8.24 format */ + /* Convert real data in 34.30 to 8.24 by 6 right shifts */ + *realResult = (q31_t) (real_sum >> 6); + /* Convert imaginary data in 34.30 to 8.24 by 6 right shifts */ + *imagResult = (q31_t) (imag_sum >> 6); +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of cmplx_dot_prod group + */ diff --git a/components/nmsis/dsp/src/ComplexMathFunctions/riscv_cmplx_dot_prod_q31.c b/components/nmsis/dsp/src/ComplexMathFunctions/riscv_cmplx_dot_prod_q31.c new file mode 100644 index 00000000..bcbc9da0 --- /dev/null +++ b/components/nmsis/dsp/src/ComplexMathFunctions/riscv_cmplx_dot_prod_q31.c @@ -0,0 +1,222 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_cmplx_dot_prod_q31.c + * Description: Q31 complex dot product + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @addtogroup cmplx_dot_prod + @{ + */ + +/** + @brief Q31 complex dot product. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[in] numSamples number of samples in each vector + @param[out] realResult real part of the result returned here + @param[out] imagResult imaginary part of the result returned here + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The intermediate 1.31 by 1.31 multiplications are performed with 64-bit precision and then shifted to 16.48 format. + The internal real and imaginary accumulators are in 16.48 format and provide 15 guard bits. + Additions are nonsaturating and no overflow will occur as long as numSamples is less than 32768. + The return results realResult and imagResult are in 16.48 format. + Input down scaling is not required. + */ + +void riscv_cmplx_dot_prod_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + uint32_t numSamples, + q63_t * realResult, + q63_t * imagResult) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = numSamples; /* Loop counter */ + size_t l; + const q31_t * inputA = pSrcA; + const q31_t * inputB = pSrcB; + ptrdiff_t bstride = 8; + vint32m4_t v_R1, v_R2, v_I1, v_I2; + vint64m8_t v_RR, v_II, v_RI, v_IR; + vint64m1_t v_dst; /* I don't know what the effect is */ + vint64m1_t v_real ; + vint64m1_t v_imag ; /* Initialize accumulated value */ + l = vsetvl_e64m1(1); + v_real = vmv_s_x_i64m1(v_real, 0, l); + v_imag = vmv_s_x_i64m1(v_imag, 0, l); + v_dst = vmv_s_x_i64m1(v_dst, 0, l); + + for (; (l = vsetvl_e32m4(blkCnt)) > 0; blkCnt -= l) + { + v_R1 = vlse32_v_i32m4(inputA, bstride, l); + v_R2 = vlse32_v_i32m4(inputB, bstride, l); + inputA++; inputB++; /* Point to the first complex pointer */ + v_I1 = vlse32_v_i32m4(inputA, bstride, l); + v_I2 = vlse32_v_i32m4(inputB, bstride, l); + v_RR = vsra_vx_i64m8(vwmul_vv_i64m8(v_R1, v_R2, l), 14, l); + v_II = vsra_vx_i64m8(vwmul_vv_i64m8(v_I1, v_I2, l), 14, l); + v_RI = vsra_vx_i64m8(vwmul_vv_i64m8(v_R1, v_I2, l), 14, l); + v_IR = vsra_vx_i64m8(vwmul_vv_i64m8(v_I1, v_R2, l), 14, l); + v_real = vredsum_vs_i64m8_i64m1(v_dst, vssub_vv_i64m8(v_RR, v_II, l), v_real, l); + v_imag = vredsum_vs_i64m8_i64m1(v_dst, vsadd_vv_i64m8(v_RI, v_IR, l), v_imag, l); + inputA += (l*2-1); inputB += (l*2-1); + } + vsetvl_e32m4(1); + *realResult = vmv_x_s_i64m1_i64(v_real); + *imagResult = vmv_x_s_i64m1_i64(v_imag); +#else + uint32_t blkCnt; /* Loop counter */ + q63_t real_sum = 0, imag_sum = 0; /* Temporary result variables */ +#if __RISCV_XLEN == 64 + q63_t RESA,RESB; +#endif /* __RISCV_XLEN == 64 */ + q31_t a0,b0,c0,d0; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { +#if __RISCV_XLEN == 64 + RESA = read_q31x2_ia((q31_t **) &pSrcA); + RESB = read_q31x2_ia((q31_t **) &pSrcB); + real_sum += (__RV_SMBB32(RESA, RESB) >> 14); + real_sum -= (__RV_SMTT32(RESA, RESB) >> 14); + imag_sum += (__RV_SMBT32(RESA, RESB) >> 14); + imag_sum += (__RV_SMBT32(RESB, RESA) >> 14); + + RESA = read_q31x2_ia((q31_t **) &pSrcA); + RESB = read_q31x2_ia((q31_t **) &pSrcB); + real_sum += (__RV_SMBB32(RESA, RESB) >> 14); + real_sum -= (__RV_SMTT32(RESA, RESB) >> 14); + imag_sum += (__RV_SMBT32(RESA, RESB) >> 14); + imag_sum += (__RV_SMBT32(RESB, RESA) >> 14); + + RESA = read_q31x2_ia((q31_t **) &pSrcA); + RESB = read_q31x2_ia((q31_t **) &pSrcB); + real_sum += (__RV_SMBB32(RESA, RESB) >> 14); + real_sum -= (__RV_SMTT32(RESA, RESB) >> 14); + imag_sum += (__RV_SMBT32(RESA, RESB) >> 14); + imag_sum += (__RV_SMBT32(RESB, RESA) >> 14); + + RESA = read_q31x2_ia((q31_t **) &pSrcA); + RESB = read_q31x2_ia((q31_t **) &pSrcB); + real_sum += (__RV_SMBB32(RESA, RESB) >> 14); + real_sum -= (__RV_SMTT32(RESA, RESB) >> 14); + imag_sum += (__RV_SMBT32(RESA, RESB) >> 14); + imag_sum += (__RV_SMBT32(RESB, RESA) >> 14); +#else + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += ((q63_t)a0 * c0) >> 14; + imag_sum += ((q63_t)a0 * d0) >> 14; + real_sum -= ((q63_t)b0 * d0) >> 14; + imag_sum += ((q63_t)b0 * c0) >> 14; + + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += ((q63_t)a0 * c0) >> 14; + imag_sum += ((q63_t)a0 * d0) >> 14; + real_sum -= ((q63_t)b0 * d0) >> 14; + imag_sum += ((q63_t)b0 * c0) >> 14; + + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += ((q63_t)a0 * c0) >> 14; + imag_sum += ((q63_t)a0 * d0) >> 14; + real_sum -= ((q63_t)b0 * d0) >> 14; + imag_sum += ((q63_t)b0 * c0) >> 14; + + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += ((q63_t)a0 * c0) >> 14; + imag_sum += ((q63_t)a0 * d0) >> 14; + real_sum -= ((q63_t)b0 * d0) >> 14; + imag_sum += ((q63_t)b0 * c0) >> 14; +#endif /* __RISCV_XLEN == 64 */ + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += ((q63_t)a0 * c0) >> 14; + imag_sum += ((q63_t)a0 * d0) >> 14; + real_sum -= ((q63_t)b0 * d0) >> 14; + imag_sum += ((q63_t)b0 * c0) >> 14; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store real and imaginary result in 16.48 format */ + *realResult = real_sum; + *imagResult = imag_sum; +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of cmplx_dot_prod group + */ diff --git a/components/nmsis/dsp/src/ComplexMathFunctions/riscv_cmplx_mag_f16.c b/components/nmsis/dsp/src/ComplexMathFunctions/riscv_cmplx_mag_f16.c new file mode 100644 index 00000000..9e1a1442 --- /dev/null +++ b/components/nmsis/dsp/src/ComplexMathFunctions/riscv_cmplx_mag_f16.c @@ -0,0 +1,143 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_cmplx_mag_f16.c + * Description: Floating-point complex magnitude + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/complex_math_functions_f16.h" + +#if defined(RISCV_FLOAT16_SUPPORTED) +/** + @ingroup groupCmplxMath + */ + +/** + @defgroup cmplx_mag Complex Magnitude + + Computes the magnitude of the elements of a complex data vector. + + The pSrc points to the source data and + pDst points to the where the result should be written. + numSamples specifies the number of complex samples + in the input array and the data is stored in an interleaved fashion + (real, imag, real, imag, ...). + The input array has a total of 2*numSamples values; + the output array has a total of numSamples values. + + The underlying algorithm is used: + + 
+  for (n = 0; n < numSamples; n++) {
+      pDst[n] = sqrt(pSrc[(2*n)+0]^2 + pSrc[(2*n)+1]^2);
+  }
+
+ + There are separate functions for floating-point, Q15, and Q31 data types. + */ + +/** + @addtogroup cmplx_mag + @{ + */ + +/** + @brief Floating-point complex magnitude. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] numSamples number of samples in each vector + @return none + */ + +void riscv_cmplx_mag_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* loop counter */ + _Float16 real, imag; /* Temporary variables to hold input values */ + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */ + + real = *pSrc++; + imag = *pSrc++; + + /* store result in destination buffer. */ + riscv_sqrt_f16((real * real) + (imag * imag), pDst++); + + real = *pSrc++; + imag = *pSrc++; + riscv_sqrt_f16((real * real) + (imag * imag), pDst++); + + real = *pSrc++; + imag = *pSrc++; + riscv_sqrt_f16((real * real) + (imag * imag), pDst++); + + real = *pSrc++; + imag = *pSrc++; + riscv_sqrt_f16((real * real) + (imag * imag), pDst++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */ + + real = *pSrc++; + imag = *pSrc++; + + /* store result in destination buffer. */ + riscv_sqrt_f16((real * real) + (imag * imag), pDst++); + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of cmplx_mag group + */ + +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ diff --git a/components/nmsis/dsp/src/ComplexMathFunctions/riscv_cmplx_mag_f32.c b/components/nmsis/dsp/src/ComplexMathFunctions/riscv_cmplx_mag_f32.c new file mode 100644 index 00000000..4638e48e --- /dev/null +++ b/components/nmsis/dsp/src/ComplexMathFunctions/riscv_cmplx_mag_f32.c @@ -0,0 +1,163 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_cmplx_mag_f32.c + * Description: Floating-point complex magnitude + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @defgroup cmplx_mag Complex Magnitude + + Computes the magnitude of the elements of a complex data vector. + + The pSrc points to the source data and + pDst points to the where the result should be written. + numSamples specifies the number of complex samples + in the input array and the data is stored in an interleaved fashion + (real, imag, real, imag, ...). + The input array has a total of 2*numSamples values; + the output array has a total of numSamples values. + + The underlying algorithm is used: + + 
+  for (n = 0; n < numSamples; n++) {
+      pDst[n] = sqrt(pSrc[(2*n)+0]^2 + pSrc[(2*n)+1]^2);
+  }
+
+ + There are separate functions for floating-point, Q15, and Q31 data types. + */ + +/** + @addtogroup cmplx_mag + @{ + */ + +/** + @brief Floating-point complex magnitude. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] numSamples number of samples in each vector + @return none + */ + + +void riscv_cmplx_mag_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = numSamples; /* Loop counter */ + size_t l; + const float32_t * input = pSrc; + float32_t * output = pDst; + ptrdiff_t bstride = 8; + vfloat32m8_t v_R,v_I; + vfloat32m8_t vR2_m4, vI2_m4; + vfloat32m8_t v_sum; + for (; (l = vsetvl_e32m8(blkCnt)) > 0; blkCnt -= l) + { + v_R = vlse32_v_f32m8(input, bstride, l); + input++; + v_I = vlse32_v_f32m8(input, bstride, l); + input += (l*2-1); + v_sum = vfadd_vv_f32m8(vfmul_vv_f32m8(v_R, v_R, l), vfmul_vv_f32m8(v_I, v_I, l), l); + vse32_v_f32m8(output, vfsqrt_v_f32m8(v_sum, l), l); + output += l; + } + +#else + uint32_t blkCnt; /* loop counter */ + float32_t real, imag; /* Temporary variables to hold input values */ + + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */ + + real = *pSrc++; + imag = *pSrc++; + + /* store result in destination buffer. */ + riscv_sqrt_f32((real * real) + (imag * imag), pDst++); + + real = *pSrc++; + imag = *pSrc++; + riscv_sqrt_f32((real * real) + (imag * imag), pDst++); + + real = *pSrc++; + imag = *pSrc++; + riscv_sqrt_f32((real * real) + (imag * imag), pDst++); + + real = *pSrc++; + imag = *pSrc++; + riscv_sqrt_f32((real * real) + (imag * imag), pDst++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */ + + real = *pSrc++; + imag = *pSrc++; + + /* store result in destination buffer. */ + riscv_sqrt_f32((real * real) + (imag * imag), pDst++); + + /* Decrement loop counter */ + blkCnt--; + } +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of cmplx_mag group + */ diff --git a/components/nmsis/dsp/src/ComplexMathFunctions/riscv_cmplx_mag_q15.c b/components/nmsis/dsp/src/ComplexMathFunctions/riscv_cmplx_mag_q15.c new file mode 100644 index 00000000..8e3c72fb --- /dev/null +++ b/components/nmsis/dsp/src/ComplexMathFunctions/riscv_cmplx_mag_q15.c @@ -0,0 +1,196 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_cmplx_mag_q15.c + * Description: Q15 complex magnitude + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @addtogroup cmplx_mag + @{ + */ + +/** + @brief Q15 complex magnitude. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] numSamples number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function implements 1.15 by 1.15 multiplications and finally output is converted into 2.14 format. + */ +void riscv_cmplx_mag_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (RISCV_MATH_DSP) +#if __RISCV_XLEN == 64 + q63_t in64; + q63_t acc064; + q15_t real, imag; /* Temporary input variables */ + q31_t acc0,acc1; +#else + q31_t in; + q31_t acc0; + q15_t real, imag; /* Temporary input variables */ + q31_t acc1; /* Accumulators */ +#endif /* __RISCV_XLEN == 64 */ +#else + q15_t real, imag; /* Temporary input variables */ + q31_t acc0,acc1; /* Accumulators */ +#endif +// #if defined (RISCV_MATH_DSP) +// // #if __RISCV_XLEN == 64 +// // q63_t in64; +// // q31_t acc064; +// // #else +// q31_t in; +// q31_t acc0; /* Accumulators */ +// // #endif /* __RISCV_XLEN == 64 */ +// #else +// q15_t real, imag; /* Temporary input variables */ +// q31_t acc0, acc1; /* Accumulators */ +// #endif + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */ + +#if defined (RISCV_MATH_DSP) +#if __RISCV_XLEN == 64 + in64 = read_q15x4_ia ((q15_t **) &pSrc); + acc064 = __RV_KMDA(in64, in64); + riscv_sqrt_q15(((q15_t) ((q31_t)acc064 >> 17)), pDst++); + riscv_sqrt_q15(((q15_t) (acc064 >> 49)), pDst++); + + in64 = read_q15x4_ia ((q15_t **) &pSrc); + acc064 = __RV_KMDA(in64, in64); + riscv_sqrt_q15(((q15_t) ((q31_t)acc064 >> 17)), pDst++); + riscv_sqrt_q15(((q15_t) (acc064 >> 49)), pDst++); + +#else + in = read_q15x2_ia ((q15_t **) &pSrc); + acc0 = __RV_KMDA(in, in); + /* store result in 2.14 format in destination buffer. */ + riscv_sqrt_q15((q15_t) (acc0 >> 17), pDst++); + + in = read_q15x2_ia ((q15_t **) &pSrc); + acc0 = __RV_KMDA(in, in); + riscv_sqrt_q15((q15_t) (acc0 >> 17), pDst++); + + in = read_q15x2_ia ((q15_t **) &pSrc); + acc0 = __RV_KMDA(in, in); + riscv_sqrt_q15((q15_t) (acc0 >> 17), pDst++); + + in = read_q15x2_ia ((q15_t **) &pSrc); + acc0 = __RV_KMDA(in, in); + riscv_sqrt_q15((q15_t) (acc0 >> 17), pDst++); +#endif /* __RISCV_XLEN == 64 */ +#else + real = *pSrc++; + imag = *pSrc++; + acc0 = ((q31_t) real * real); + acc1 = ((q31_t) imag * imag); + + /* store result in 2.14 format in destination buffer. */ + riscv_sqrt_q15((q15_t) (((q63_t) acc0 + acc1) >> 17), pDst++); + + real = *pSrc++; + imag = *pSrc++; + acc0 = ((q31_t) real * real); + acc1 = ((q31_t) imag * imag); + riscv_sqrt_q15((q15_t) (((q63_t) acc0 + acc1) >> 17), pDst++); + + real = *pSrc++; + imag = *pSrc++; + acc0 = ((q31_t) real * real); + acc1 = ((q31_t) imag * imag); + riscv_sqrt_q15((q15_t) (((q63_t) acc0 + acc1) >> 17), pDst++); + + real = *pSrc++; + imag = *pSrc++; + acc0 = ((q31_t) real * real); + acc1 = ((q31_t) imag * imag); + riscv_sqrt_q15((q15_t) (((q63_t) acc0 + acc1) >> 17), pDst++); +#endif /* #if defined (RISCV_MATH_DSP) */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */ + +// #if defined (RISCV_MATH_DSP) +// in = read_q15x2_ia ((q15_t **) &pSrc); +// acc0 = __SMUAD(in, in); + +// /* store result in 2.14 format in destination buffer. */ +// riscv_sqrt_q15((q15_t) (acc0 >> 17), pDst++); +// #else + real = *pSrc++; + imag = *pSrc++; + acc0 = ((q31_t) real * real); + acc1 = ((q31_t) imag * imag); + + /* store result in 2.14 format in destination buffer. */ + riscv_sqrt_q15((q15_t) (((q63_t) acc0 + acc1) >> 17), pDst++); +// #endif + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of cmplx_mag group + */ diff --git a/components/nmsis/dsp/src/ComplexMathFunctions/riscv_cmplx_mag_q31.c b/components/nmsis/dsp/src/ComplexMathFunctions/riscv_cmplx_mag_q31.c new file mode 100644 index 00000000..d2b881f7 --- /dev/null +++ b/components/nmsis/dsp/src/ComplexMathFunctions/riscv_cmplx_mag_q31.c @@ -0,0 +1,155 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_cmplx_mag_q31.c + * Description: Q31 complex magnitude + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @addtogroup cmplx_mag + @{ + */ + +/** + @brief Q31 complex magnitude. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] numSamples number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function implements 1.31 by 1.31 multiplications and finally output is converted into 2.30 format. + Input down scaling is not required. + */ + +void riscv_cmplx_mag_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + q31_t real, imag; /* Temporary input variables */ + q31_t acc0, acc1; /* Accumulators */ + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */ + + real = *pSrc++; + imag = *pSrc++; +#if defined(RISCV_MATH_DSP) + acc0 = (q31_t) (__MULSR64(real, real) >> 33); + acc1 = (q31_t) (__MULSR64(imag, imag) >> 33); +#else + acc0 = (q31_t) (((q63_t) real * real) >> 33); + acc1 = (q31_t) (((q63_t) imag * imag) >> 33); +#endif + /* store result in 2.30 format in destination buffer. */ + riscv_sqrt_q31(acc0 + acc1, pDst++); + + real = *pSrc++; + imag = *pSrc++; +#if defined(RISCV_MATH_DSP) + acc0 = (q31_t) (__MULSR64(real, real) >> 33); + acc1 = (q31_t) (__MULSR64(imag, imag) >> 33); +#else + acc0 = (q31_t) (((q63_t) real * real) >> 33); + acc1 = (q31_t) (((q63_t) imag * imag) >> 33); +#endif + riscv_sqrt_q31(acc0 + acc1, pDst++); + + real = *pSrc++; + imag = *pSrc++; +#if defined(RISCV_MATH_DSP) + acc0 = (q31_t) (__MULSR64(real, real) >> 33); + acc1 = (q31_t) (__MULSR64(imag, imag) >> 33); +#else + acc0 = (q31_t) (((q63_t) real * real) >> 33); + acc1 = (q31_t) (((q63_t) imag * imag) >> 33); +#endif + riscv_sqrt_q31(acc0 + acc1, pDst++); + + real = *pSrc++; + imag = *pSrc++; +#if defined(RISCV_MATH_DSP) + acc0 = (q31_t) (__MULSR64(real, real) >> 33); + acc1 = (q31_t) (__MULSR64(imag, imag) >> 33); +#else + acc0 = (q31_t) (((q63_t) real * real) >> 33); + acc1 = (q31_t) (((q63_t) imag * imag) >> 33); +#endif + riscv_sqrt_q31(acc0 + acc1, pDst++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */ + + real = *pSrc++; + imag = *pSrc++; +#if defined(RISCV_MATH_DSP) + acc0 = (q31_t) (__MULSR64(real, real) >> 33); + acc1 = (q31_t) (__MULSR64(imag, imag) >> 33); +#else + acc0 = (q31_t) (((q63_t) real * real) >> 33); + acc1 = (q31_t) (((q63_t) imag * imag) >> 33); +#endif + + /* store result in 2.30 format in destination buffer. */ + riscv_sqrt_q31(acc0 + acc1, pDst++); + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of cmplx_mag group + */ diff --git a/components/nmsis/dsp/src/ComplexMathFunctions/riscv_cmplx_mag_squared_f16.c b/components/nmsis/dsp/src/ComplexMathFunctions/riscv_cmplx_mag_squared_f16.c new file mode 100644 index 00000000..6a8e9b47 --- /dev/null +++ b/components/nmsis/dsp/src/ComplexMathFunctions/riscv_cmplx_mag_squared_f16.c @@ -0,0 +1,142 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_cmplx_mag_squared_f16.c + * Description: Floating-point complex magnitude squared + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/complex_math_functions_f16.h" + +#if defined(RISCV_FLOAT16_SUPPORTED) + +/** + @ingroup groupCmplxMath + */ + +/** + @defgroup cmplx_mag_squared Complex Magnitude Squared + + Computes the magnitude squared of the elements of a complex data vector. + + The pSrc points to the source data and + pDst points to the where the result should be written. + numSamples specifies the number of complex samples + in the input array and the data is stored in an interleaved fashion + (real, imag, real, imag, ...). + The input array has a total of 2*numSamples values; + the output array has a total of numSamples values. + + The underlying algorithm is used: + + 
+  for (n = 0; n < numSamples; n++) {
+      pDst[n] = pSrc[(2*n)+0]^2 + pSrc[(2*n)+1]^2;
+  }
+
+ + There are separate functions for floating-point, Q15, and Q31 data types. + */ + +/** + @addtogroup cmplx_mag_squared + @{ + */ + +/** + @brief Floating-point complex magnitude squared. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] numSamples number of samples in each vector + @return none + */ + +void riscv_cmplx_mag_squared_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + _Float16 real, imag; /* Temporary input variables */ + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[0] = (A[0] * A[0] + A[1] * A[1]) */ + + real = *pSrc++; + imag = *pSrc++; + *pDst++ = (real * real) + (imag * imag); + + real = *pSrc++; + imag = *pSrc++; + *pDst++ = (real * real) + (imag * imag); + + real = *pSrc++; + imag = *pSrc++; + *pDst++ = (real * real) + (imag * imag); + + real = *pSrc++; + imag = *pSrc++; + *pDst++ = (real * real) + (imag * imag); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C[0] = (A[0] * A[0] + A[1] * A[1]) */ + + real = *pSrc++; + imag = *pSrc++; + + /* store result in destination buffer. */ + *pDst++ = (real * real) + (imag * imag); + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of cmplx_mag_squared group + */ + +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ diff --git a/components/nmsis/dsp/src/ComplexMathFunctions/riscv_cmplx_mag_squared_f32.c b/components/nmsis/dsp/src/ComplexMathFunctions/riscv_cmplx_mag_squared_f32.c new file mode 100644 index 00000000..64873f11 --- /dev/null +++ b/components/nmsis/dsp/src/ComplexMathFunctions/riscv_cmplx_mag_squared_f32.c @@ -0,0 +1,158 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_cmplx_mag_squared_f32.c + * Description: Floating-point complex magnitude squared + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @defgroup cmplx_mag_squared Complex Magnitude Squared + + Computes the magnitude squared of the elements of a complex data vector. + + The pSrc points to the source data and + pDst points to the where the result should be written. + numSamples specifies the number of complex samples + in the input array and the data is stored in an interleaved fashion + (real, imag, real, imag, ...). + The input array has a total of 2*numSamples values; + the output array has a total of numSamples values. + + The underlying algorithm is used: + + 
+  for (n = 0; n < numSamples; n++) {
+      pDst[n] = pSrc[(2*n)+0]^2 + pSrc[(2*n)+1]^2;
+  }
+
+ + There are separate functions for floating-point, Q15, and Q31 data types. + */ + +/** + @addtogroup cmplx_mag_squared + @{ + */ + +/** + @brief Floating-point complex magnitude squared. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] numSamples number of samples in each vector + @return none + */ + +void riscv_cmplx_mag_squared_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = numSamples; /* Loop counter */ + size_t l; + const float32_t * input = pSrc; + float32_t * output = pDst; + ptrdiff_t bstride = 8; + vfloat32m8_t v_R,v_I; + vfloat32m8_t vR2_m4, vI2_m4; + vfloat32m8_t v_sum; + for (; (l = vsetvl_e32m8(blkCnt)) > 0; blkCnt -= l) + { + v_R = vlse32_v_f32m8(input, bstride, l); + input++; + v_I = vlse32_v_f32m8(input, bstride, l); + input += (l*2-1); + v_sum = vfadd_vv_f32m8(vfmul_vv_f32m8(v_R, v_R, l), vfmul_vv_f32m8(v_I, v_I, l), l); + vse32_v_f32m8(output, v_sum, l); + output += l; + } + +#else + uint32_t blkCnt; /* Loop counter */ + float32_t real, imag; /* Temporary input variables */ +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[0] = (A[0] * A[0] + A[1] * A[1]) */ + + real = *pSrc++; + imag = *pSrc++; + *pDst++ = (real * real) + (imag * imag); + + real = *pSrc++; + imag = *pSrc++; + *pDst++ = (real * real) + (imag * imag); + + real = *pSrc++; + imag = *pSrc++; + *pDst++ = (real * real) + (imag * imag); + + real = *pSrc++; + imag = *pSrc++; + *pDst++ = (real * real) + (imag * imag); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C[0] = (A[0] * A[0] + A[1] * A[1]) */ + + real = *pSrc++; + imag = *pSrc++; + + /* store result in destination buffer. */ + *pDst++ = (real * real) + (imag * imag); + + /* Decrement loop counter */ + blkCnt--; + } +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of cmplx_mag_squared group + */ diff --git a/components/nmsis/dsp/src/ComplexMathFunctions/riscv_cmplx_mag_squared_q15.c b/components/nmsis/dsp/src/ComplexMathFunctions/riscv_cmplx_mag_squared_q15.c new file mode 100644 index 00000000..aff00f99 --- /dev/null +++ b/components/nmsis/dsp/src/ComplexMathFunctions/riscv_cmplx_mag_squared_q15.c @@ -0,0 +1,211 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_cmplx_mag_squared_q15.c + * Description: Q15 complex magnitude squared + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @addtogroup cmplx_mag_squared + @{ + */ + +/** + @brief Q15 complex magnitude squared. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] numSamples number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function implements 1.15 by 1.15 multiplications and finally output is converted into 3.13 format. + */ + +void riscv_cmplx_mag_squared_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = numSamples; /* Loop counter */ + size_t l; + const q15_t * input = pSrc; + q15_t * output = pDst; + ptrdiff_t bstride = 4; + vint16m2_t v_R,v_I; + vint32m4_t vR2_m4, vI2_m4; + vint64m8_t vsum_m8; + vint16m2_t v_summ2; + for (; (l = vsetvl_e16m2(blkCnt)) > 0; blkCnt -= l) + { + v_R = vlse16_v_i16m2(input, bstride, l); + input++; + v_I = vlse16_v_i16m2(input, bstride, l); + input += (l*2-1); + vR2_m4 = vwmul_vv_i32m4(v_R, v_R, l); + vI2_m4 = vwmul_vv_i32m4(v_I, v_I, l); + vsum_m8 = vwadd_vv_i64m8 (vR2_m4, vI2_m4, l); + //v_summ2 = vnclip_wx_i16m2(vnsra_wx_i32m4(vsum_m8, 17), 0); + v_summ2 = vnclip_wx_i16m2(vnclip_wx_i32m4(vsum_m8, 17, l), 0, l); + vse16_v_i16m2 (output, v_summ2, l); + output += l; + } + +#else + uint32_t blkCnt; /* Loop counter */ + +#if defined (RISCV_MATH_DSP) +#if __RISCV_XLEN == 64 + q63_t in64; + q63_t acc064; + q15_t real, imag; /* Temporary input variables */ + q31_t acc0,acc1; +#else + q31_t in; + q31_t acc0; + q15_t real, imag; /* Temporary input variables */ + q31_t acc1; /* Accumulators */ +#endif /* __RISCV_XLEN == 64 */ +#else + q15_t real, imag; /* Temporary input variables */ + q31_t acc0,acc1; /* Accumulators */ +#endif + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[0] = (A[0] * A[0] + A[1] * A[1]) */ + +#if defined (RISCV_MATH_DSP) +#if __RISCV_XLEN == 64 + in64 = read_q15x4_ia ((q15_t **) &pSrc); + acc064 = __RV_KMDA(in64, in64); + *pDst++ = (q15_t) ((q31_t)acc064 >> 17); + *pDst++ = (q15_t) (acc064 >> 49); + + in64 = read_q15x4_ia ((q15_t **) &pSrc); + acc064 = __RV_KMDA(in64, in64); + *pDst++ = (q15_t) ((q31_t)acc064 >> 17); + *pDst++ = (q15_t) (acc064 >> 49); + +#else + in = read_q15x2_ia ((q15_t **) &pSrc); + acc0 = __RV_KMDA(in, in); + /* store result in 3.13 format in destination buffer. */ + *pDst++ = (q15_t) (acc0 >> 17); + + in = read_q15x2_ia ((q15_t **) &pSrc); + acc0 = __RV_KMDA(in, in); + *pDst++ = (q15_t) (acc0 >> 17); + + in = read_q15x2_ia ((q15_t **) &pSrc); + acc0 = __RV_KMDA(in, in); + *pDst++ = (q15_t) (acc0 >> 17); + + in = read_q15x2_ia ((q15_t **) &pSrc); + acc0 = __RV_KMDA(in, in); + *pDst++ = (q15_t) (acc0 >> 17); +#endif /* __RISCV_XLEN == 64 */ +#else + real = *pSrc++; + imag = *pSrc++; + acc0 = ((q31_t) real * real); + acc1 = ((q31_t) imag * imag); + /* store result in 3.13 format in destination buffer. */ + *pDst++ = (q15_t) (((q63_t) acc0 + acc1) >> 17); + + real = *pSrc++; + imag = *pSrc++; + acc0 = ((q31_t) real * real); + acc1 = ((q31_t) imag * imag); + *pDst++ = (q15_t) (((q63_t) acc0 + acc1) >> 17); + + real = *pSrc++; + imag = *pSrc++; + acc0 = ((q31_t) real * real); + acc1 = ((q31_t) imag * imag); + *pDst++ = (q15_t) (((q63_t) acc0 + acc1) >> 17); + + real = *pSrc++; + imag = *pSrc++; + acc0 = ((q31_t) real * real); + acc1 = ((q31_t) imag * imag); + *pDst++ = (q15_t) (((q63_t) acc0 + acc1) >> 17); +#endif /* #if defined (RISCV_MATH_DSP) */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C[0] = (A[0] * A[0] + A[1] * A[1]) */ + +// #if defined (RISCV_MATH_DSP) +// in = read_q15x2_ia ((q15_t **) &pSrc); +// acc0 = __SMUAD(in, in); + +// /* store result in 3.13 format in destination buffer. */ +// *pDst++ = (q15_t) (acc0 >> 17); +// #else + real = *pSrc++; + imag = *pSrc++; + acc0 = ((q31_t) real * real); + acc1 = ((q31_t) imag * imag); + + /* store result in 3.13 format in destination buffer. */ + *pDst++ = (q15_t) (((q63_t) acc0 + acc1) >> 17); +// #endif + + /* Decrement loop counter */ + blkCnt--; + } +#endif /* defined(RISCV_VECTOR) */ +} + + +/** + @} end of cmplx_mag_squared group + */ diff --git a/components/nmsis/dsp/src/ComplexMathFunctions/riscv_cmplx_mag_squared_q31.c b/components/nmsis/dsp/src/ComplexMathFunctions/riscv_cmplx_mag_squared_q31.c new file mode 100644 index 00000000..056bdaf5 --- /dev/null +++ b/components/nmsis/dsp/src/ComplexMathFunctions/riscv_cmplx_mag_squared_q31.c @@ -0,0 +1,186 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_cmplx_mag_squared_q31.c + * Description: Q31 complex magnitude squared + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @addtogroup cmplx_mag_squared + @{ + */ + +/** + @brief Q31 complex magnitude squared. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] numSamples number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function implements 1.31 by 1.31 multiplications and finally output is converted into 3.29 format. + Input down scaling is not required. + */ + +void riscv_cmplx_mag_squared_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = numSamples; /* Loop counter */ + size_t l; + const q31_t * input = pSrc; + q31_t * output = pDst; + ptrdiff_t bstride = 8; + vint32m4_t v_R,v_I; + vint32m4_t vR2_m4, vI2_m4; + vint32m4_t v_sum; + for (; (l = vsetvl_e32m4(blkCnt)) > 0; blkCnt -= l) + { + v_R = vlse32_v_i32m4(input, bstride, l); + input++; + v_I = vlse32_v_i32m4(input, bstride, l); + input += (l*2-1); + vR2_m4 = vnclip_wx_i32m4(vwmul_vv_i64m8(v_R, v_R, l), 33, l); + vI2_m4 = vnclip_wx_i32m4(vwmul_vv_i64m8(v_I, v_I, l), 33, l); + v_sum = vsadd_vv_i32m4(vR2_m4, vI2_m4, l); + vse32_v_i32m4(output, v_sum, l); + output += l; + } +#else + uint32_t blkCnt; /* Loop counter */ + q31_t real, imag; /* Temporary input variables */ + q31_t acc0, acc1; /* Accumulators */ +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[0] = (A[0] * A[0] + A[1] * A[1]) */ + + real = *pSrc++; + imag = *pSrc++; + +#if defined(RISCV_MATH_DSP) + acc0 = (q31_t) (__RV_MULSR64(real, real) >> 33); + acc1 = (q31_t) (__RV_MULSR64(imag, imag) >> 33); +#else + acc0 = (q31_t) (((q63_t) real * real) >> 33); + acc1 = (q31_t) (((q63_t) imag * imag) >> 33); +#endif + + /* store the result in 3.29 format in the destination buffer. */ + *pDst++ = acc0 + acc1; + + real = *pSrc++; + imag = *pSrc++; + +#if defined(RISCV_MATH_DSP) + acc0 = (q31_t) (__RV_MULSR64(real, real) >> 33); + acc1 = (q31_t) (__RV_MULSR64(imag, imag) >> 33); +#else + acc0 = (q31_t) (((q63_t) real * real) >> 33); + acc1 = (q31_t) (((q63_t) imag * imag) >> 33); +#endif + + *pDst++ = acc0 + acc1; + + real = *pSrc++; + imag = *pSrc++; + +#if defined(RISCV_MATH_DSP) + acc0 = (q31_t) (__RV_MULSR64(real, real) >> 33); + acc1 = (q31_t) (__RV_MULSR64(imag, imag) >> 33); +#else + acc0 = (q31_t) (((q63_t) real * real) >> 33); + acc1 = (q31_t) (((q63_t) imag * imag) >> 33); +#endif + + *pDst++ = acc0 + acc1; + + real = *pSrc++; + imag = *pSrc++; + +#if defined(RISCV_MATH_DSP) + acc0 = (q31_t) (__RV_MULSR64(real, real) >> 33); + acc1 = (q31_t) (__RV_MULSR64(imag, imag) >> 33); +#else + acc0 = (q31_t) (((q63_t) real * real) >> 33); + acc1 = (q31_t) (((q63_t) imag * imag) >> 33); +#endif + + *pDst++ = acc0 + acc1; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C[0] = (A[0] * A[0] + A[1] * A[1]) */ + + real = *pSrc++; + imag = *pSrc++; + +#if defined(RISCV_MATH_DSP) + acc0 = (q31_t) (__RV_MULSR64(real, real) >> 33); + acc1 = (q31_t) (__RV_MULSR64(imag, imag) >> 33); +#else + acc0 = (q31_t) (((q63_t) real * real) >> 33); + acc1 = (q31_t) (((q63_t) imag * imag) >> 33); +#endif + + /* store result in 3.29 format in destination buffer. */ + *pDst++ = acc0 + acc1; + + /* Decrement loop counter */ + blkCnt--; + } +#endif /* defined(RISCV_VECTOR) */ +} + + +/** + @} end of cmplx_mag_squared group + */ diff --git a/components/nmsis/dsp/src/ComplexMathFunctions/riscv_cmplx_mult_cmplx_f16.c b/components/nmsis/dsp/src/ComplexMathFunctions/riscv_cmplx_mult_cmplx_f16.c new file mode 100644 index 00000000..1c9bd3a7 --- /dev/null +++ b/components/nmsis/dsp/src/ComplexMathFunctions/riscv_cmplx_mult_cmplx_f16.c @@ -0,0 +1,160 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_cmplx_mult_cmplx_f16.c + * Description: Floating-point complex-by-complex multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/complex_math_functions_f16.h" + +#if defined(RISCV_FLOAT16_SUPPORTED) + +/** + @ingroup groupCmplxMath + */ + +/** + @defgroup CmplxByCmplxMult Complex-by-Complex Multiplication + + Multiplies a complex vector by another complex vector and generates a complex result. + The data in the complex arrays is stored in an interleaved fashion + (real, imag, real, imag, ...). + The parameter numSamples represents the number of complex + samples processed. The complex arrays have a total of 2*numSamples + real values. + + The underlying algorithm is used: + + 
+  for (n = 0; n < numSamples; n++) {
+      pDst[(2*n)+0] = pSrcA[(2*n)+0] * pSrcB[(2*n)+0] - pSrcA[(2*n)+1] * pSrcB[(2*n)+1];
+      pDst[(2*n)+1] = pSrcA[(2*n)+0] * pSrcB[(2*n)+1] + pSrcA[(2*n)+1] * pSrcB[(2*n)+0];
+  }
+
+ + There are separate functions for floating-point, Q15, and Q31 data types. + */ + +/** + @addtogroup CmplxByCmplxMult + @{ + */ + +/** + @brief Floating-point complex-by-complex multiplication. + @param[in] pSrcA points to first input vector + @param[in] pSrcB points to second input vector + @param[out] pDst points to output vector + @param[in] numSamples number of samples in each vector + @return none + */ + +void riscv_cmplx_mult_cmplx_f16( + const float16_t * pSrcA, + const float16_t * pSrcB, + float16_t * pDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + _Float16 a, b, c, d; /* Temporary variables to store real and imaginary values */ + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i] * B[2 * i ] - A[2 * i + 1] * B[2 * i + 1]. */ + /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i ]. */ + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + /* store result in destination buffer. */ + *pDst++ = (a * c) - (b * d); + *pDst++ = (a * d) + (b * c); + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + *pDst++ = (a * c) - (b * d); + *pDst++ = (a * d) + (b * c); + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + *pDst++ = (a * c) - (b * d); + *pDst++ = (a * d) + (b * c); + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + *pDst++ = (a * c) - (b * d); + *pDst++ = (a * d) + (b * c); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i] * B[2 * i ] - A[2 * i + 1] * B[2 * i + 1]. */ + /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i ]. */ + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + + /* store result in destination buffer. */ + *pDst++ = (a * c) - (b * d); + *pDst++ = (a * d) + (b * c); + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of CmplxByCmplxMult group + */ + +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ diff --git a/components/nmsis/dsp/src/ComplexMathFunctions/riscv_cmplx_mult_cmplx_f32.c b/components/nmsis/dsp/src/ComplexMathFunctions/riscv_cmplx_mult_cmplx_f32.c new file mode 100644 index 00000000..d791c2b4 --- /dev/null +++ b/components/nmsis/dsp/src/ComplexMathFunctions/riscv_cmplx_mult_cmplx_f32.c @@ -0,0 +1,183 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_cmplx_mult_cmplx_f32.c + * Description: Floating-point complex-by-complex multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @defgroup CmplxByCmplxMult Complex-by-Complex Multiplication + + Multiplies a complex vector by another complex vector and generates a complex result. + The data in the complex arrays is stored in an interleaved fashion + (real, imag, real, imag, ...). + The parameter numSamples represents the number of complex + samples processed. The complex arrays have a total of 2*numSamples + real values. + + The underlying algorithm is used: + + 
+  for (n = 0; n < numSamples; n++) {
+      pDst[(2*n)+0] = pSrcA[(2*n)+0] * pSrcB[(2*n)+0] - pSrcA[(2*n)+1] * pSrcB[(2*n)+1];
+      pDst[(2*n)+1] = pSrcA[(2*n)+0] * pSrcB[(2*n)+1] + pSrcA[(2*n)+1] * pSrcB[(2*n)+0];
+  }
+
+ + There are separate functions for floating-point, Q15, and Q31 data types. + */ + +/** + @addtogroup CmplxByCmplxMult + @{ + */ + +/** + @brief Floating-point complex-by-complex multiplication. + @param[in] pSrcA points to first input vector + @param[in] pSrcB points to second input vector + @param[out] pDst points to output vector + @param[in] numSamples number of samples in each vector + @return none + */ + +void riscv_cmplx_mult_cmplx_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = numSamples; /* Loop counter */ + size_t l; + const float32_t * inputA = pSrcA; + const float32_t * inputB = pSrcB; + float32_t *output = pDst; + ptrdiff_t bstride = 8; + vfloat32m8_t v_R1, v_R2, v_I1, v_I2; + vfloat32m8_t v_RR, v_II, v_RI, v_IR; + for (; (l = vsetvl_e32m8(blkCnt)) > 0; blkCnt -= l) + { + v_R1 = vlse32_v_f32m8(inputA, bstride, l); + v_R2 = vlse32_v_f32m8(inputB, bstride, l); + inputA++; inputB++; /* Point to the first complex pointer */ + v_I1 = vlse32_v_f32m8(inputA, bstride, l); + v_I2 = vlse32_v_f32m8(inputB, bstride, l); + inputA += (l*2-1); inputB += (l*2-1); + v_RR = vfmul_vv_f32m8(v_R1, v_R2, l); + v_II = vfmul_vv_f32m8(v_I1, v_I2, l); + v_RI = vfmul_vv_f32m8(v_R1, v_I2, l); + v_IR = vfmul_vv_f32m8(v_I1, v_R2, l); + vsse32_v_f32m8 (output, bstride, vfsub_vv_f32m8(v_RR, v_II, l), l); + output++; + vsse32_v_f32m8 (output, bstride, vfadd_vv_f32m8(v_RI, v_IR, l), l); + output += (l*2-1); + } +#else + uint32_t blkCnt; /* Loop counter */ + float32_t a, b, c, d; /* Temporary variables to store real and imaginary values */ + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i] * B[2 * i ] - A[2 * i + 1] * B[2 * i + 1]. */ + /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i ]. */ + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + /* store result in destination buffer. */ + *pDst++ = (a * c) - (b * d); + *pDst++ = (a * d) + (b * c); + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + *pDst++ = (a * c) - (b * d); + *pDst++ = (a * d) + (b * c); + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + *pDst++ = (a * c) - (b * d); + *pDst++ = (a * d) + (b * c); + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + *pDst++ = (a * c) - (b * d); + *pDst++ = (a * d) + (b * c); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i] * B[2 * i ] - A[2 * i + 1] * B[2 * i + 1]. */ + /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i ]. */ + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + + /* store result in destination buffer. */ + *pDst++ = (a * c) - (b * d); + *pDst++ = (a * d) + (b * c); + + /* Decrement loop counter */ + blkCnt--; + } +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of CmplxByCmplxMult group + */ diff --git a/components/nmsis/dsp/src/ComplexMathFunctions/riscv_cmplx_mult_cmplx_q15.c b/components/nmsis/dsp/src/ComplexMathFunctions/riscv_cmplx_mult_cmplx_q15.c new file mode 100644 index 00000000..7c7a7d60 --- /dev/null +++ b/components/nmsis/dsp/src/ComplexMathFunctions/riscv_cmplx_mult_cmplx_q15.c @@ -0,0 +1,219 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_cmplx_mult_cmplx_q15.c + * Description: Q15 complex-by-complex multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @addtogroup CmplxByCmplxMult + @{ + */ + +/** + @brief Q15 complex-by-complex multiplication. + @param[in] pSrcA points to first input vector + @param[in] pSrcB points to second input vector + @param[out] pDst points to output vector + @param[in] numSamples number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function implements 1.15 by 1.15 multiplications and finally output is converted into 3.13 format. + */ + +void riscv_cmplx_mult_cmplx_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = numSamples; /* Loop counter */ + size_t l; + const q15_t * inputA = pSrcA; + const q15_t * inputB = pSrcB; + q15_t *output = pDst; + ptrdiff_t bstride = 4; + vint16m4_t v_R1, v_R2, v_I1, v_I2; + vint32m8_t v_RR, v_II, v_RI, v_IR; + for (; (l = vsetvl_e16m4(blkCnt)) > 0; blkCnt -= l) + { + v_R1 = vlse16_v_i16m4(inputA, bstride, l); + v_R2 = vlse16_v_i16m4(inputB, bstride, l); + inputA++; inputB++; /* Point to the first complex pointer */ + v_I1 = vlse16_v_i16m4(inputA, bstride, l); + v_I2 = vlse16_v_i16m4(inputB, bstride, l); + inputA += (l*2-1); inputB += (l*2-1); + v_RR = vsra_vx_i32m8(vwmul_vv_i32m8(v_R1, v_R2, l), 17, l); + v_II = vsra_vx_i32m8(vwmul_vv_i32m8(v_I1, v_I2, l), 17, l); + v_RI = vsra_vx_i32m8(vwmul_vv_i32m8(v_R1, v_I2, l), 17, l); + v_IR = vsra_vx_i32m8(vwmul_vv_i32m8(v_I1, v_R2, l), 17, l); + vsse16_v_i16m4 (output, bstride, vnclip_wx_i16m4(vssub_vv_i32m8(v_RR, v_II, l),0, l), l); + output++; + vsse16_v_i16m4 (output, bstride, vnclip_wx_i16m4(vsadd_vv_i32m8(v_RI, v_IR, l),0, l), l); + output += (l*2-1); + } +#else + uint32_t blkCnt; /* Loop counter */ + q15_t a, b, c, d; /* Temporary variables */ +#if __RISCV_XLEN == 64 + q31_t RESA,RESB; +#endif /* __RISCV_XLEN == 64 */ +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i] * B[2 * i ] - A[2 * i + 1] * B[2 * i + 1]. */ + /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i ]. */ +#if defined(RISCV_MATH_DSP) +#if __RISCV_XLEN == 64 + RESA = read_q15x2_ia((q15_t **) &pSrcA); + RESB = read_q15x2_ia((q15_t **) &pSrcB); + *pDst++ = (q15_t) (__RV_SMALDRS(0,RESA,RESB) >> 17); + *pDst++ = (q15_t) (__RV_SMALXDA(0,RESA,RESB) >> 17); + + RESA = read_q15x2_ia((q15_t **) &pSrcA); + RESB = read_q15x2_ia((q15_t **) &pSrcB); + *pDst++ = (q15_t) (__RV_SMALDRS(0,RESA,RESB) >> 17); + *pDst++ = (q15_t) (__RV_SMALXDA(0,RESA,RESB) >> 17); + + RESA = read_q15x2_ia((q15_t **) &pSrcA); + RESB = read_q15x2_ia((q15_t **) &pSrcB); + *pDst++ = (q15_t) (__RV_SMALDRS(0,RESA,RESB) >> 17); + *pDst++ = (q15_t) (__RV_SMALXDA(0,RESA,RESB) >> 17); + + RESA = read_q15x2_ia((q15_t **) &pSrcA); + RESB = read_q15x2_ia((q15_t **) &pSrcB); + *pDst++ = (q15_t) (__RV_SMALDRS(0,RESA,RESB) >> 17); + *pDst++ = (q15_t) (__RV_SMALXDA(0,RESA,RESB) >> 17); + +#else + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + + /* store result in 3.13 format in destination buffer. */ +#if defined(RISCV_MATH_DSP) + *pDst++ = (q15_t) ( (__SMBB16(a, c) >> 17) - (__SMBB16(b, d) >> 17) ); + *pDst++ = (q15_t) ( (__SMBB16(a, d) >> 17) + (__SMBB16(b, c) >> 17) ); +#else + *pDst++ = (q15_t) ( (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17) ); + *pDst++ = (q15_t) ( (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17) ); +#endif + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + +#if defined(RISCV_MATH_DSP) + *pDst++ = (q15_t) ( (__SMBB16(a, c) >> 17) - (__SMBB16(b, d) >> 17) ); + *pDst++ = (q15_t) ( (__SMBB16(a, d) >> 17) + (__SMBB16(b, c) >> 17) ); +#else + *pDst++ = (q15_t) ( (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17) ); + *pDst++ = (q15_t) ( (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17) ); +#endif + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + +#if defined(RISCV_MATH_DSP) + *pDst++ = (q15_t) ( (__SMBB16(a, c) >> 17) - (__SMBB16(b, d) >> 17) ); + *pDst++ = (q15_t) ( (__SMBB16(a, d) >> 17) + (__SMBB16(b, c) >> 17) ); +#else + *pDst++ = (q15_t) ( (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17) ); + *pDst++ = (q15_t) ( (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17) ); +#endif + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + +#if defined(RISCV_MATH_DSP) + *pDst++ = (q15_t) ( (__SMBB16(a, c) >> 17) - (__SMBB16(b, d) >> 17) ); + *pDst++ = (q15_t) ( (__SMBB16(a, d) >> 17) + (__SMBB16(b, c) >> 17) ); +#else + *pDst++ = (q15_t) ( (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17) ); + *pDst++ = (q15_t) ( (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17) ); +#endif +#endif +#endif /* __RISCV_XLEN == 64 */ + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i] * B[2 * i ] - A[2 * i + 1] * B[2 * i + 1]. */ + /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i ]. */ + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + + /* store result in 3.13 format in destination buffer. */ +#if defined(RISCV_MATH_DSP) + *pDst++ = (q15_t) ( (__SMBB16(a, c) >> 17) - (__SMBB16(b, d) >> 17) ); + *pDst++ = (q15_t) ( (__SMBB16(a, d) >> 17) + (__SMBB16(b, c) >> 17) ); +#else + *pDst++ = (q15_t) ( (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17) ); + *pDst++ = (q15_t) ( (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17) ); +#endif + + /* Decrement loop counter */ + blkCnt--; + } +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of CmplxByCmplxMult group + */ diff --git a/components/nmsis/dsp/src/ComplexMathFunctions/riscv_cmplx_mult_cmplx_q31.c b/components/nmsis/dsp/src/ComplexMathFunctions/riscv_cmplx_mult_cmplx_q31.c new file mode 100644 index 00000000..3ce7ae68 --- /dev/null +++ b/components/nmsis/dsp/src/ComplexMathFunctions/riscv_cmplx_mult_cmplx_q31.c @@ -0,0 +1,193 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_cmplx_mult_cmplx_q31.c + * Description: Q31 complex-by-complex multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @addtogroup CmplxByCmplxMult + @{ + */ + +/** + @brief Q31 complex-by-complex multiplication. + @param[in] pSrcA points to first input vector + @param[in] pSrcB points to second input vector + @param[out] pDst points to output vector + @param[in] numSamples number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function implements 1.31 by 1.31 multiplications and finally output is converted into 3.29 format. + Input down scaling is not required. + */ + +void riscv_cmplx_mult_cmplx_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t numSamples) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = numSamples; /* Loop counter */ + size_t l; + const q31_t * inputA = pSrcA; + const q31_t * inputB = pSrcB; + q31_t *output = pDst; + ptrdiff_t bstride = 8; + vint32m4_t v_R1, v_R2, v_I1, v_I2; + vint64m8_t v_RR, v_II, v_RI, v_IR; + for (; (l = vsetvl_e32m4(blkCnt)) > 0; blkCnt -= l) + { + v_R1 = vlse32_v_i32m4(inputA, bstride, l); + v_R2 = vlse32_v_i32m4(inputB, bstride, l); + inputA++; inputB++; /* Point to the first complex pointer */ + v_I1 = vlse32_v_i32m4(inputA, bstride, l); + v_I2 = vlse32_v_i32m4(inputB, bstride, l); + inputA += (l*2-1); inputB += (l*2-1); + v_RR = vsra_vx_i64m8(vwmul_vv_i64m8(v_R1, v_R2, l), 33, l); + v_II = vsra_vx_i64m8(vwmul_vv_i64m8(v_I1, v_I2, l), 33, l); + v_RI = vsra_vx_i64m8(vwmul_vv_i64m8(v_R1, v_I2, l), 33, l); + v_IR = vsra_vx_i64m8(vwmul_vv_i64m8(v_I1, v_R2, l), 33, l); + vsse32_v_i32m4 (output, bstride, vnclip_wx_i32m4(vssub_vv_i64m8(v_RR, v_II, l),0, l), l); + output++; + vsse32_v_i32m4 (output, bstride, vnclip_wx_i32m4(vsadd_vv_i64m8(v_RI, v_IR, l),0, l), l); + output += (l*2-1); + } +#else + uint32_t blkCnt; /* Loop counter */ + q31_t a, b, c, d; /* Temporary variables */ + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i] * B[2 * i ] - A[2 * i + 1] * B[2 * i + 1]. */ + /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i ]. */ + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + + /* store result in 3.29 format in destination buffer. */ +#if defined(RISCV_MATH_DSP) + *pDst++ = (q31_t) ( ((q31_t)__RV_SMMUL(a, c) >> 1) - ((q31_t)__RV_SMMUL(b, d) >> 1) ); + *pDst++ = (q31_t) ( ((q31_t)__RV_SMMUL(a, d) >> 1) + ((q31_t)__RV_SMMUL(b, c) >> 1) ); +#else + *pDst++ = (q31_t) ( (((q63_t) a * c) >> 33) - (((q63_t) b * d) >> 33) ); + *pDst++ = (q31_t) ( (((q63_t) a * d) >> 33) + (((q63_t) b * c) >> 33) ); +#endif + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + +#if defined(RISCV_MATH_DSP) + *pDst++ = (q31_t) ( ((q31_t)__RV_SMMUL(a, c) >> 1) - ((q31_t)__RV_SMMUL(b, d) >> 1) ); + *pDst++ = (q31_t) ( ((q31_t)__RV_SMMUL(a, d) >> 1) + ((q31_t)__RV_SMMUL(b, c) >> 1) ); +#else + *pDst++ = (q31_t) ( (((q63_t) a * c) >> 33) - (((q63_t) b * d) >> 33) ); + *pDst++ = (q31_t) ( (((q63_t) a * d) >> 33) + (((q63_t) b * c) >> 33) ); +#endif + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + +#if defined(RISCV_MATH_DSP) + *pDst++ = (q31_t) ( ((q31_t)__RV_SMMUL(a, c) >> 1) - ((q31_t)__RV_SMMUL(b, d) >> 1) ); + *pDst++ = (q31_t) ( ((q31_t)__RV_SMMUL(a, d) >> 1) + ((q31_t)__RV_SMMUL(b, c) >> 1) ); +#else + *pDst++ = (q31_t) ( (((q63_t) a * c) >> 33) - (((q63_t) b * d) >> 33) ); + *pDst++ = (q31_t) ( (((q63_t) a * d) >> 33) + (((q63_t) b * c) >> 33) ); +#endif + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + +#if defined(RISCV_MATH_DSP) + *pDst++ = (q31_t) ( ((q31_t)__RV_SMMUL(a, c) >> 1) - ((q31_t)__RV_SMMUL(b, d) >> 1) ); + *pDst++ = (q31_t) ( ((q31_t)__RV_SMMUL(a, d) >> 1) + ((q31_t)__RV_SMMUL(b, c) >> 1) ); +#else + *pDst++ = (q31_t) ( (((q63_t) a * c) >> 33) - (((q63_t) b * d) >> 33) ); + *pDst++ = (q31_t) ( (((q63_t) a * d) >> 33) + (((q63_t) b * c) >> 33) ); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i] * B[2 * i ] - A[2 * i + 1] * B[2 * i + 1]. */ + /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i ]. */ + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + + /* store result in 3.29 format in destination buffer. */ +#if defined(RISCV_MATH_DSP) + *pDst++ = (q31_t) ( ((q31_t)__RV_SMMUL(a, c) >> 1) - ((q31_t)__RV_SMMUL(b, d) >> 1) ); + *pDst++ = (q31_t) ( ((q31_t)__RV_SMMUL(a, d) >> 1) + ((q31_t)__RV_SMMUL(b, c) >> 1) ); +#else + *pDst++ = (q31_t) ( (((q63_t) a * c) >> 33) - (((q63_t) b * d) >> 33) ); + *pDst++ = (q31_t) ( (((q63_t) a * d) >> 33) + (((q63_t) b * c) >> 33) ); +#endif + /* Decrement loop counter */ + blkCnt--; + } +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of CmplxByCmplxMult group + */ diff --git a/components/nmsis/dsp/src/ComplexMathFunctions/riscv_cmplx_mult_real_f16.c b/components/nmsis/dsp/src/ComplexMathFunctions/riscv_cmplx_mult_real_f16.c new file mode 100644 index 00000000..e734c8b0 --- /dev/null +++ b/components/nmsis/dsp/src/ComplexMathFunctions/riscv_cmplx_mult_real_f16.c @@ -0,0 +1,145 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_cmplx_mult_real_f16.c + * Description: Floating-point complex by real multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/complex_math_functions_f16.h" + +#if defined(RISCV_FLOAT16_SUPPORTED) + +/** + @ingroup groupCmplxMath + */ + +/** + @defgroup CmplxByRealMult Complex-by-Real Multiplication + + Multiplies a complex vector by a real vector and generates a complex result. + The data in the complex arrays is stored in an interleaved fashion + (real, imag, real, imag, ...). + The parameter numSamples represents the number of complex + samples processed. The complex arrays have a total of 2*numSamples + real values while the real array has a total of numSamples + real values. + + The underlying algorithm is used: + + 
+  for (n = 0; n < numSamples; n++) {
+      pCmplxDst[(2*n)+0] = pSrcCmplx[(2*n)+0] * pSrcReal[n];
+      pCmplxDst[(2*n)+1] = pSrcCmplx[(2*n)+1] * pSrcReal[n];
+  }
+
+ + There are separate functions for floating-point, Q15, and Q31 data types. + */ + +/** + @addtogroup CmplxByRealMult + @{ + */ + +/** + @brief Floating-point complex-by-real multiplication. + @param[in] pSrcCmplx points to complex input vector + @param[in] pSrcReal points to real input vector + @param[out] pCmplxDst points to complex output vector + @param[in] numSamples number of samples in each vector + @return none + */ + +void riscv_cmplx_mult_real_f16( + const float16_t * pSrcCmplx, + const float16_t * pSrcReal, + float16_t * pCmplxDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + float16_t in; /* Temporary variable */ + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i ] * B[i]. */ + /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */ + + in = *pSrcReal++; + /* store result in destination buffer. */ + *pCmplxDst++ = *pSrcCmplx++ * in; + *pCmplxDst++ = *pSrcCmplx++ * in; + + in = *pSrcReal++; + *pCmplxDst++ = *pSrcCmplx++ * in; + *pCmplxDst++ = *pSrcCmplx++ * in; + + in = *pSrcReal++; + *pCmplxDst++ = *pSrcCmplx++ * in; + *pCmplxDst++ = *pSrcCmplx++ * in; + + in = *pSrcReal++; + *pCmplxDst++ = *pSrcCmplx++* in; + *pCmplxDst++ = *pSrcCmplx++ * in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i ] * B[i]. */ + /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */ + + in = *pSrcReal++; + /* store result in destination buffer. */ + *pCmplxDst++ = *pSrcCmplx++ * in; + *pCmplxDst++ = *pSrcCmplx++ * in; + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of CmplxByRealMult group + */ + +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ diff --git a/components/nmsis/dsp/src/ComplexMathFunctions/riscv_cmplx_mult_real_f32.c b/components/nmsis/dsp/src/ComplexMathFunctions/riscv_cmplx_mult_real_f32.c new file mode 100644 index 00000000..f831e775 --- /dev/null +++ b/components/nmsis/dsp/src/ComplexMathFunctions/riscv_cmplx_mult_real_f32.c @@ -0,0 +1,167 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_cmplx_mult_real_f32.c + * Description: Floating-point complex by real multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @defgroup CmplxByRealMult Complex-by-Real Multiplication + + Multiplies a complex vector by a real vector and generates a complex result. + The data in the complex arrays is stored in an interleaved fashion + (real, imag, real, imag, ...). + The parameter numSamples represents the number of complex + samples processed. The complex arrays have a total of 2*numSamples + real values while the real array has a total of numSamples + real values. + + The underlying algorithm is used: + + 
+  for (n = 0; n < numSamples; n++) {
+      pCmplxDst[(2*n)+0] = pSrcCmplx[(2*n)+0] * pSrcReal[n];
+      pCmplxDst[(2*n)+1] = pSrcCmplx[(2*n)+1] * pSrcReal[n];
+  }
+
+ + There are separate functions for floating-point, Q15, and Q31 data types. + */ + +/** + @addtogroup CmplxByRealMult + @{ + */ + +/** + @brief Floating-point complex-by-real multiplication. + @param[in] pSrcCmplx points to complex input vector + @param[in] pSrcReal points to real input vector + @param[out] pCmplxDst points to complex output vector + @param[in] numSamples number of samples in each vector + @return none + */ + +void riscv_cmplx_mult_real_f32( + const float32_t * pSrcCmplx, + const float32_t * pSrcReal, + float32_t * pCmplxDst, + uint32_t numSamples) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = numSamples; /* Loop counter */ + size_t l; + const float32_t * input_c = pSrcCmplx; /* Complex pointer */ + const float32_t * input_r = pSrcReal; /* Real pointer */ + float32_t * output = pCmplxDst; + ptrdiff_t bstride = 8; + vfloat32m8_t v_Rc, v_Ic ,v_Rr; + vfloat32m8_t vR2_m8, vI2_m8; + vfloat32m8_t v_sum; + for (; (l = vsetvl_e32m8(blkCnt)) > 0; blkCnt -= l) + { + v_Rc = vlse32_v_f32m8(input_c, bstride, l); + input_c++; + v_Ic = vlse32_v_f32m8(input_c, bstride, l); + v_Rr = vle32_v_f32m8(input_r, l); + input_r += l; + input_c += (l*2-1); + vR2_m8 = vfmul_vv_f32m8(v_Rc, v_Rr, l); + vI2_m8 = vfmul_vv_f32m8(v_Ic, v_Rr, l); + vsse32_v_f32m8(output, bstride, vR2_m8, l); + output++; + vsse32_v_f32m8(output, bstride, vI2_m8, l); + output += (l*2-1); + } +#else + uint32_t blkCnt; /* Loop counter */ + float32_t in; /* Temporary variable */ + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i ] * B[i]. */ + /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */ + + in = *pSrcReal++; + /* store result in destination buffer. */ + *pCmplxDst++ = *pSrcCmplx++ * in; + *pCmplxDst++ = *pSrcCmplx++ * in; + + in = *pSrcReal++; + *pCmplxDst++ = *pSrcCmplx++ * in; + *pCmplxDst++ = *pSrcCmplx++ * in; + + in = *pSrcReal++; + *pCmplxDst++ = *pSrcCmplx++ * in; + *pCmplxDst++ = *pSrcCmplx++ * in; + + in = *pSrcReal++; + *pCmplxDst++ = *pSrcCmplx++* in; + *pCmplxDst++ = *pSrcCmplx++ * in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i ] * B[i]. */ + /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */ + + in = *pSrcReal++; + /* store result in destination buffer. */ + *pCmplxDst++ = *pSrcCmplx++ * in; + *pCmplxDst++ = *pSrcCmplx++ * in; + + /* Decrement loop counter */ + blkCnt--; + } +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of CmplxByRealMult group + */ diff --git a/components/nmsis/dsp/src/ComplexMathFunctions/riscv_cmplx_mult_real_q15.c b/components/nmsis/dsp/src/ComplexMathFunctions/riscv_cmplx_mult_real_q15.c new file mode 100644 index 00000000..9e2984a4 --- /dev/null +++ b/components/nmsis/dsp/src/ComplexMathFunctions/riscv_cmplx_mult_real_q15.c @@ -0,0 +1,244 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_cmplx_mult_real_q15.c + * Description: Q15 complex by real multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @addtogroup CmplxByRealMult + @{ + */ + +/** + @brief Q15 complex-by-real multiplication. + @param[in] pSrcCmplx points to complex input vector + @param[in] pSrcReal points to real input vector + @param[out] pCmplxDst points to complex output vector + @param[in] numSamples number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q15 range [0x8000 0x7FFF] are saturated. + */ +void riscv_cmplx_mult_real_q15( + const q15_t * pSrcCmplx, + const q15_t * pSrcReal, + q15_t * pCmplxDst, + uint32_t numSamples) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = numSamples; /* Loop counter */ + size_t l; + const q15_t * input_c = pSrcCmplx; /* Complex pointer */ + const q15_t * input_r = pSrcReal; /* Real pointer */ + q15_t * output = pCmplxDst; + ptrdiff_t bstride = 4; + vint16m4_t v_Rc, v_Ic ,v_Rr; + vint16m4_t vR2_m4, vI2_m4; + vint16m4_t v_sum; + for (; (l = vsetvl_e16m4(blkCnt)) > 0; blkCnt -= l) + { + v_Rc = vlse16_v_i16m4(input_c, bstride, l); + input_c++; + v_Ic = vlse16_v_i16m4(input_c, bstride, l); + v_Rr = vle16_v_i16m4(input_r, l); + input_r += l; + input_c += (l*2-1); + vR2_m4 = vnclip_wx_i16m4(vwmul_vv_i32m8(v_Rc, v_Rr, l), 15, l); + vI2_m4 = vnclip_wx_i16m4(vwmul_vv_i32m8(v_Ic, v_Rr, l), 15, l); + vsse16_v_i16m4(output, bstride, vR2_m4, l); + output++; + vsse16_v_i16m4(output, bstride, vI2_m4, l); + output += (l*2-1); + } +#else + uint32_t blkCnt; /* Loop counter */ + q15_t in; /* Temporary variable */ + +#if defined (RISCV_MATH_LOOPUNROLL) + +#if defined (RISCV_MATH_DSP) +#if __RISCV_XLEN == 64 + q63_t inA1, inA2; /* Temporary variables to hold input data */ + q63_t inB1; /* Temporary variables to hold input data */ + q31_t temp; + q15_t out1, out2, out3, out4; /* Temporary variables to hold output data */ + q63_t mul1, mul2, mul3, mul4; /* Temporary variables to hold intermediate data */ +#else + q31_t inA1, inA2; /* Temporary variables to hold input data */ + q31_t inB1; /* Temporary variables to hold input data */ + q15_t out1, out2, out3, out4; /* Temporary variables to hold output data */ + q31_t mul1, mul2, mul3, mul4; /* Temporary variables to hold intermediate data */ +#endif /* __RISCV_XLEN == 64 */ + blkCnt = numSamples >> 2U; +#endif + + /* Loop unrolling: Compute 4 outputs at a time */ + + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i ] * B[i]. */ + /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */ + +#if defined (RISCV_MATH_DSP) +#if __RISCV_XLEN == 64 + /* read 2 complex numbers both real and imaginary from complex input buffer */ + inA1 = read_q15x4_ia ((q15_t **) &pSrcCmplx); + // inA2 = read_q15x4_ia ((q15_t **) &pSrcCmplx); + /* read 2 real values at a time from real input buffer */ + temp = read_q15x2_ia ((q15_t **) &pSrcReal); + inB1 = (q63_t) (((q63_t) (((uint32_t)temp) & 0xffff0000) << 16) | ((q63_t)((uint32_t)temp))); + + mul1 = __RV_SMBB16(inA1, inB1); //1,3 + mul2 = __RV_SMBT16(inB1, inA1); // 2,4 + + write_q15x4_ia (&pCmplxDst, ((uint64_t)((uint16_t) __SSAT(((mul1) & 0xffffffffull) >> 15U, 16)) ) | + ((uint64_t)((uint16_t) __SSAT(((mul2) & 0xffffffffull) >> 15U, 16)) << 16) | + ((uint64_t)((uint16_t) __SSAT(((mul1) & 0xffffffff00000000ull) >> 47U, 16))<< 32) | + ((uint64_t)((uint16_t) __SSAT(((mul2) & 0xffffffff00000000ull) >> 47U, 16)) << 48) + ); + /* read 2 complex numbers both real and imaginary from complex input buffer */ + inA1 = read_q15x4_ia ((q15_t **) &pSrcCmplx); + /* read 2 real values at a time from real input buffer */ + temp = read_q15x2_ia ((q15_t **) &pSrcReal); + inB1 = (q63_t) (((q63_t) (((uint32_t)temp) & 0xffff0000) << 16) | ((q63_t)((uint32_t)temp))); + + mul1 = __RV_SMBB16(inA1, inB1); //1,3 + mul2 = __RV_SMBT16(inB1, inA1); // 2,4 + + write_q15x4_ia (&pCmplxDst, ((uint64_t)((uint16_t) __SSAT(((mul1) & 0xffffffffull) >> 15U, 16)) ) | + ((uint64_t)((uint16_t) __SSAT(((mul2) & 0xffffffffull) >> 15U, 16)) << 16) | + ((uint64_t)((uint16_t) __SSAT(((mul1) & 0xffffffff00000000ull) >> 47U, 16))<< 32) | + ((uint64_t)((uint16_t) __SSAT(((mul2) & 0xffffffff00000000ull) >> 47U, 16)) << 48) + ); +#else + /* read 2 complex numbers both real and imaginary from complex input buffer */ + inA1 = read_q15x2_ia ((q15_t **) &pSrcCmplx); + inA2 = read_q15x2_ia ((q15_t **) &pSrcCmplx); + /* read 2 real values at a time from real input buffer */ + inB1 = read_q15x2_ia ((q15_t **) &pSrcReal); + + /* multiply complex number with real numbers */ +#if defined(RISCV_MATH_DSP) + mul1 = __SMBB16(inA1, inB1); + mul2 = __SMBT16(inB1, inA1); + mul3 = __SMBT16(inA2, inB1); + mul4 = __SMTT16(inA2, inB1); +#else + mul1 = (q31_t) ((q15_t) (inA1) * (q15_t) (inB1)); + mul2 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1)); + mul3 = (q31_t) ((q15_t) (inA2) * (q15_t) (inB1 >> 16)); + mul4 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) (inB1 >> 16)); +#endif + + /* saturate the result */ + out1 = (q15_t) __SSAT(mul1 >> 15U, 16); + out2 = (q15_t) __SSAT(mul2 >> 15U, 16); + out3 = (q15_t) __SSAT(mul3 >> 15U, 16); + out4 = (q15_t) __SSAT(mul4 >> 15U, 16); + + /* pack real and imaginary outputs and store them to destination */ + write_q15x2_ia (&pCmplxDst, __PKHBT(out1, out2, 16)); + write_q15x2_ia (&pCmplxDst, __PKHBT(out3, out4, 16)); + + inA1 = read_q15x2_ia ((q15_t **) &pSrcCmplx); + inA2 = read_q15x2_ia ((q15_t **) &pSrcCmplx); + inB1 = read_q15x2_ia ((q15_t **) &pSrcReal); + + //mul1 = (q31_t) ((q15_t) (inA1) * (q15_t) (inB1)); + //mul2 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1)); + //mul3 = (q31_t) ((q15_t) (inA2) * (q15_t) (inB1 >> 16)); + //mul4 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) (inB1 >> 16)); + mul1 = __SMBB16(inA1, inB1); + mul2 = __SMBT16(inB1, inA1); + mul3 = __SMBT16(inA2, inB1); + mul4 = __SMTT16(inA2, inB1); + + out1 = (q15_t) __SSAT(mul1 >> 15U, 16); + out2 = (q15_t) __SSAT(mul2 >> 15U, 16); + out3 = (q15_t) __SSAT(mul3 >> 15U, 16); + out4 = (q15_t) __SSAT(mul4 >> 15U, 16); + + write_q15x2_ia (&pCmplxDst, __PKHBT(out1, out2, 16)); + write_q15x2_ia (&pCmplxDst, __PKHBT(out3, out4, 16)); +#endif /* __RISCV_XLEN == 64 */ +#else + in = *pSrcReal++; + *pCmplxDst++ = (q15_t) __SSAT((((q31_t) *pSrcCmplx++ * in) >> 15), 16); + *pCmplxDst++ = (q15_t) __SSAT((((q31_t) *pSrcCmplx++ * in) >> 15), 16); + + in = *pSrcReal++; + *pCmplxDst++ = (q15_t) __SSAT((((q31_t) *pSrcCmplx++ * in) >> 15), 16); + *pCmplxDst++ = (q15_t) __SSAT((((q31_t) *pSrcCmplx++ * in) >> 15), 16); + + in = *pSrcReal++; + *pCmplxDst++ = (q15_t) __SSAT((((q31_t) *pSrcCmplx++ * in) >> 15), 16); + *pCmplxDst++ = (q15_t) __SSAT((((q31_t) *pSrcCmplx++ * in) >> 15), 16); + + in = *pSrcReal++; + *pCmplxDst++ = (q15_t) __SSAT((((q31_t) *pSrcCmplx++ * in) >> 15), 16); + *pCmplxDst++ = (q15_t) __SSAT((((q31_t) *pSrcCmplx++ * in) >> 15), 16); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i ] * B[i]. */ + /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */ + + in = *pSrcReal++; + /* store the result in the destination buffer. */ + *pCmplxDst++ = (q15_t) __SSAT((((q31_t) *pSrcCmplx++ * in) >> 15), 16); + *pCmplxDst++ = (q15_t) __SSAT((((q31_t) *pSrcCmplx++ * in) >> 15), 16); + + /* Decrement loop counter */ + blkCnt--; + } +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of CmplxByRealMult group + */ diff --git a/components/nmsis/dsp/src/ComplexMathFunctions/riscv_cmplx_mult_real_q31.c b/components/nmsis/dsp/src/ComplexMathFunctions/riscv_cmplx_mult_real_q31.c new file mode 100644 index 00000000..029d0958 --- /dev/null +++ b/components/nmsis/dsp/src/ComplexMathFunctions/riscv_cmplx_mult_real_q31.c @@ -0,0 +1,185 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_cmplx_mult_real_q31.c + * Description: Q31 complex by real multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @addtogroup CmplxByRealMult + @{ + */ + +/** + @brief Q31 complex-by-real multiplication. + @param[in] pSrcCmplx points to complex input vector + @param[in] pSrcReal points to real input vector + @param[out] pCmplxDst points to complex output vector + @param[in] numSamples number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] are saturated. + */ + +void riscv_cmplx_mult_real_q31( + const q31_t * pSrcCmplx, + const q31_t * pSrcReal, + q31_t * pCmplxDst, + uint32_t numSamples) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = numSamples; /* Loop counter */ + size_t l; + const q31_t * input_c = pSrcCmplx; /* Complex pointer */ + const q31_t * input_r = pSrcReal; /* Real pointer */ + q31_t * output = pCmplxDst; + ptrdiff_t bstride = 8; + vint32m4_t v_Rc, v_Ic ,v_Rr; + vint32m4_t vR2_m4, vI2_m4; + vint32m4_t v_sum; + for (; (l = vsetvl_e32m4(blkCnt)) > 0; blkCnt -= l) + { + v_Rc = vlse32_v_i32m4(input_c, bstride, l); + input_c++; + v_Ic = vlse32_v_i32m4(input_c, bstride, l); + v_Rr = vle32_v_i32m4(input_r, l); + input_r += l; + input_c += (l*2-1); + vR2_m4 = vnclip_wx_i32m4(vwmul_vv_i64m8(v_Rc, v_Rr, l), 31, l); + vI2_m4 = vnclip_wx_i32m4(vwmul_vv_i64m8(v_Ic, v_Rr, l), 31, l); + vsse32_v_i32m4(output, bstride, vR2_m4, l); + output++; + vsse32_v_i32m4(output, bstride, vI2_m4, l); + output += (l*2-1); + } +#else + uint32_t blkCnt; /* Loop counter */ + q31_t in; /* Temporary variable */ + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i ] * B[i]. */ + /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */ + + in = *pSrcReal++; +#if defined (RISCV_MATH_DSP) + /* store saturated result in 1.31 format to destination buffer */ + //*pCmplxDst++ = (__SSAT((q31_t) (((q63_t) *pSrcCmplx++ * in) >> 32), 31) << 1); + //*pCmplxDst++ = (__SSAT((q31_t) (((q63_t) *pSrcCmplx++ * in) >> 32), 31) << 1); + *pCmplxDst++ = (__SSAT((q31_t) (__MULSR64(*pSrcCmplx++, in) >> 32), 31) << 1); + *pCmplxDst++ = (__SSAT((q31_t) (__MULSR64(*pSrcCmplx++, in) >> 32), 31) << 1); +#else + /* store result in destination buffer. */ + *pCmplxDst++ = (q31_t) clip_q63_to_q31(((q63_t) *pSrcCmplx++ * in) >> 31); + *pCmplxDst++ = (q31_t) clip_q63_to_q31(((q63_t) *pSrcCmplx++ * in) >> 31); +#endif + + in = *pSrcReal++; +#if defined (RISCV_MATH_DSP) + //*pCmplxDst++ = (__SSAT((q31_t) (((q63_t) *pSrcCmplx++ * in) >> 32), 31) << 1); + //*pCmplxDst++ = (__SSAT((q31_t) (((q63_t) *pSrcCmplx++ * in) >> 32), 31) << 1); + *pCmplxDst++ = (__SSAT((q31_t) (__MULSR64(*pSrcCmplx++, in) >> 32), 31) << 1); + *pCmplxDst++ = (__SSAT((q31_t) (__MULSR64(*pSrcCmplx++, in) >> 32), 31) << 1); +#else + *pCmplxDst++ = (q31_t) clip_q63_to_q31(((q63_t) *pSrcCmplx++ * in) >> 31); + *pCmplxDst++ = (q31_t) clip_q63_to_q31(((q63_t) *pSrcCmplx++ * in) >> 31); +#endif + + in = *pSrcReal++; +#if defined (RISCV_MATH_DSP) + //*pCmplxDst++ = (__SSAT((q31_t) (((q63_t) *pSrcCmplx++ * in) >> 32), 31) << 1); + //*pCmplxDst++ = (__SSAT((q31_t) (((q63_t) *pSrcCmplx++ * in) >> 32), 31) << 1); + *pCmplxDst++ = (__SSAT((q31_t) (__MULSR64(*pSrcCmplx++, in) >> 32), 31) << 1); + *pCmplxDst++ = (__SSAT((q31_t) (__MULSR64(*pSrcCmplx++, in) >> 32), 31) << 1); +#else + *pCmplxDst++ = (q31_t) clip_q63_to_q31(((q63_t) *pSrcCmplx++ * in) >> 31); + *pCmplxDst++ = (q31_t) clip_q63_to_q31(((q63_t) *pSrcCmplx++ * in) >> 31); +#endif + + in = *pSrcReal++; +#if defined (RISCV_MATH_DSP) + //*pCmplxDst++ = (__SSAT((q31_t) (((q63_t) *pSrcCmplx++ * in) >> 32), 31) << 1); + //*pCmplxDst++ = (__SSAT((q31_t) (((q63_t) *pSrcCmplx++ * in) >> 32), 31) << 1); + *pCmplxDst++ = (__SSAT((q31_t) (__MULSR64(*pSrcCmplx++, in) >> 32), 31) << 1); + *pCmplxDst++ = (__SSAT((q31_t) (__MULSR64(*pSrcCmplx++, in) >> 32), 31) << 1); +#else + *pCmplxDst++ = (q31_t) clip_q63_to_q31(((q63_t) *pSrcCmplx++ * in) >> 31); + *pCmplxDst++ = (q31_t) clip_q63_to_q31(((q63_t) *pSrcCmplx++ * in) >> 31); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i ] * B[i]. */ + /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */ + + in = *pSrcReal++; +#if defined (RISCV_MATH_DSP) + /* store saturated result in 1.31 format to destination buffer */ + //*pCmplxDst++ = (__SSAT((q31_t) (((q63_t) *pSrcCmplx++ * in) >> 32), 31) << 1); + //*pCmplxDst++ = (__SSAT((q31_t) (((q63_t) *pSrcCmplx++ * in) >> 32), 31) << 1); + *pCmplxDst++ = (__SSAT((q31_t) (__MULSR64(*pSrcCmplx++, in) >> 32), 31) << 1); + *pCmplxDst++ = (__SSAT((q31_t) (__MULSR64(*pSrcCmplx++, in) >> 32), 31) << 1); +#else + /* store result in destination buffer. */ + *pCmplxDst++ = (q31_t) clip_q63_to_q31(((q63_t) *pSrcCmplx++ * in) >> 31); + *pCmplxDst++ = (q31_t) clip_q63_to_q31(((q63_t) *pSrcCmplx++ * in) >> 31); +#endif + + /* Decrement loop counter */ + blkCnt--; + } +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of CmplxByRealMult group + */ diff --git a/components/nmsis/dsp/src/ControllerFunctions/ControllerFunctions.c b/components/nmsis/dsp/src/ControllerFunctions/ControllerFunctions.c new file mode 100644 index 00000000..729c749f --- /dev/null +++ b/components/nmsis/dsp/src/ControllerFunctions/ControllerFunctions.c @@ -0,0 +1,47 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: ControllerFunctions.c + * Description: Combination of all controller function source files. + * + * $Date: 18. March 2019 + * $Revision: V1.0.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2019 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "riscv_pid_init_f32.c" +#include "riscv_pid_init_q15.c" +#include "riscv_pid_init_q31.c" +#include "riscv_pid_reset_f32.c" +#include "riscv_pid_reset_q15.c" +#include "riscv_pid_reset_q31.c" + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_FAST_ALLOW_TABLES) + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FAST_TABLES) || defined(RISCV_TABLE_SIN_F32) +#include "riscv_sin_cos_f32.c" +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FAST_TABLES) || defined(RISCV_TABLE_SIN_Q31) +#include "riscv_sin_cos_q31.c" +#endif + +#endif diff --git a/components/nmsis/dsp/src/ControllerFunctions/riscv_pid_init_f32.c b/components/nmsis/dsp/src/ControllerFunctions/riscv_pid_init_f32.c new file mode 100644 index 00000000..9a9924a6 --- /dev/null +++ b/components/nmsis/dsp/src/ControllerFunctions/riscv_pid_init_f32.c @@ -0,0 +1,76 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_pid_init_f32.c + * Description: Floating-point PID Control initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/controller_functions.h" + +/** + @addtogroup PID + @{ + */ + +/** + @brief Initialization function for the floating-point PID Control. + @param[in,out] S points to an instance of the PID structure + @param[in] resetStateFlag + - value = 0: no change in state + - value = 1: reset state + @return none + + @par Details + The resetStateFlag specifies whether to set state to zero or not. \n + The function computes the structure fields: A0, A1 A2 + using the proportional gain( \c Kp), integral gain( \c Ki) and derivative gain( \c Kd) + also sets the state variables to all zeros. + */ + +void riscv_pid_init_f32( + riscv_pid_instance_f32 * S, + int32_t resetStateFlag) +{ + /* Derived coefficient A0 */ + S->A0 = S->Kp + S->Ki + S->Kd; + + /* Derived coefficient A1 */ + S->A1 = (-S->Kp) - ((float32_t) 2.0f * S->Kd); + + /* Derived coefficient A2 */ + S->A2 = S->Kd; + + /* Check whether state needs reset or not */ + if (resetStateFlag) + { + /* Reset state to zero, The size will be always 3 samples */ + memset(S->state, 0, 3U * sizeof(float32_t)); + } + +} + +/** + @} end of PID group + */ diff --git a/components/nmsis/dsp/src/ControllerFunctions/riscv_pid_init_q15.c b/components/nmsis/dsp/src/ControllerFunctions/riscv_pid_init_q15.c new file mode 100644 index 00000000..38b7dfb0 --- /dev/null +++ b/components/nmsis/dsp/src/ControllerFunctions/riscv_pid_init_q15.c @@ -0,0 +1,91 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_pid_init_q15.c + * Description: Q15 PID Control initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/controller_functions.h" + +/** + @addtogroup PID + @{ + */ + +/** + @brief Initialization function for the Q15 PID Control. + @param[in,out] S points to an instance of the Q15 PID structure + @param[in] resetStateFlag + - value = 0: no change in state + - value = 1: reset state + @return none + + @par Details + The resetStateFlag specifies whether to set state to zero or not. \n + The function computes the structure fields: A0, A1 A2 + using the proportional gain( \c Kp), integral gain( \c Ki) and derivative gain( \c Kd) + also sets the state variables to all zeros. + */ + +void riscv_pid_init_q15( + riscv_pid_instance_q15 * S, + int32_t resetStateFlag) +{ + +#if defined (RISCV_MATH_DSP) + + /* Derived coefficient A0 */ + S->A0 = __QADD16(__QADD16(S->Kp, S->Ki), S->Kd); + + /* Derived coefficients and pack into A1 */ + S->A1 = __PKHBT(-__QADD16(__QADD16(S->Kd, S->Kd), S->Kp), S->Kd, 16); + +#else + + q31_t temp; /* to store the sum */ + + /* Derived coefficient A0 */ + temp = S->Kp + S->Ki + S->Kd; + S->A0 = (q15_t) __SSAT(temp, 16); + + /* Derived coefficients and pack into A1 */ + temp = -(S->Kd + S->Kd + S->Kp); + S->A1 = (q15_t) __SSAT(temp, 16); + S->A2 = S->Kd; + +#endif /* #if defined (RISCV_MATH_DSP) */ + + /* Check whether state needs reset or not */ + if (resetStateFlag) + { + /* Reset state to zero, The size will be always 3 samples */ + memset(S->state, 0, 3U * sizeof(q15_t)); + } + +} + +/** + @} end of PID group + */ diff --git a/components/nmsis/dsp/src/ControllerFunctions/riscv_pid_init_q31.c b/components/nmsis/dsp/src/ControllerFunctions/riscv_pid_init_q31.c new file mode 100644 index 00000000..22902254 --- /dev/null +++ b/components/nmsis/dsp/src/ControllerFunctions/riscv_pid_init_q31.c @@ -0,0 +1,93 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_pid_init_q31.c + * Description: Q31 PID Control initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/controller_functions.h" + +/** + @addtogroup PID + @{ + */ + +/** + @brief Initialization function for the Q31 PID Control. + @param[in,out] S points to an instance of the Q31 PID structure + @param[in] resetStateFlag + - value = 0: no change in state + - value = 1: reset state + @return none + + @par Details + The resetStateFlag specifies whether to set state to zero or not. \n + The function computes the structure fields: A0, A1 A2 + using the proportional gain( \c Kp), integral gain( \c Ki) and derivative gain( \c Kd) + also sets the state variables to all zeros. + */ + +void riscv_pid_init_q31( + riscv_pid_instance_q31 * S, + int32_t resetStateFlag) +{ + +#if defined (RISCV_MATH_DSP) + + /* Derived coefficient A0 */ + S->A0 = __QADD(__QADD(S->Kp, S->Ki), S->Kd); + + /* Derived coefficient A1 */ + S->A1 = -__QADD(__QADD(S->Kd, S->Kd), S->Kp); + +#else + + q31_t temp; /* to store the sum */ + + /* Derived coefficient A0 */ + temp = clip_q63_to_q31((q63_t) S->Kp + S->Ki); + S->A0 = clip_q63_to_q31((q63_t) temp + S->Kd); + + /* Derived coefficient A1 */ + temp = clip_q63_to_q31((q63_t) S->Kd + S->Kd); + S->A1 = -clip_q63_to_q31((q63_t) temp + S->Kp); + +#endif /* #if defined (RISCV_MATH_DSP) */ + + /* Derived coefficient A2 */ + S->A2 = S->Kd; + + /* Check whether state needs reset or not */ + if (resetStateFlag) + { + /* Reset state to zero, The size will be always 3 samples */ + memset(S->state, 0, 3U * sizeof(q31_t)); + } + +} + +/** + @} end of PID group + */ diff --git a/components/nmsis/dsp/src/ControllerFunctions/riscv_pid_reset_f32.c b/components/nmsis/dsp/src/ControllerFunctions/riscv_pid_reset_f32.c new file mode 100644 index 00000000..f491a5de --- /dev/null +++ b/components/nmsis/dsp/src/ControllerFunctions/riscv_pid_reset_f32.c @@ -0,0 +1,55 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_pid_reset_f32.c + * Description: Floating-point PID Control reset function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/controller_functions.h" + +/** + @addtogroup PID + @{ + */ + +/** + @brief Reset function for the floating-point PID Control. + @param[in,out] S points to an instance of the floating-point PID structure + @return none + + @par Details + The function resets the state buffer to zeros. + */ + +void riscv_pid_reset_f32( + riscv_pid_instance_f32 * S) +{ + /* Reset state to zero, The size will be always 3 samples */ + memset(S->state, 0, 3U * sizeof(float32_t)); +} + +/** + @} end of PID group + */ diff --git a/components/nmsis/dsp/src/ControllerFunctions/riscv_pid_reset_q15.c b/components/nmsis/dsp/src/ControllerFunctions/riscv_pid_reset_q15.c new file mode 100644 index 00000000..2d8acfd6 --- /dev/null +++ b/components/nmsis/dsp/src/ControllerFunctions/riscv_pid_reset_q15.c @@ -0,0 +1,55 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_pid_reset_q15.c + * Description: Q15 PID Control reset function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/controller_functions.h" + +/** + @addtogroup PID + @{ + */ + +/** + @brief Reset function for the Q15 PID Control. + @param[in,out] S points to an instance of the Q15 PID structure + @return none + + @par Details + The function resets the state buffer to zeros. + */ + +void riscv_pid_reset_q15( + riscv_pid_instance_q15 * S) +{ + /* Reset state to zero, The size will be always 3 samples */ + memset(S->state, 0, 3U * sizeof(q15_t)); +} + +/** + @} end of PID group + */ diff --git a/components/nmsis/dsp/src/ControllerFunctions/riscv_pid_reset_q31.c b/components/nmsis/dsp/src/ControllerFunctions/riscv_pid_reset_q31.c new file mode 100644 index 00000000..0a7d9f24 --- /dev/null +++ b/components/nmsis/dsp/src/ControllerFunctions/riscv_pid_reset_q31.c @@ -0,0 +1,55 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_pid_reset_q31.c + * Description: Q31 PID Control reset function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/controller_functions.h" + +/** + @addtogroup PID + @{ + */ + +/** + @brief Reset function for the Q31 PID Control. + @param[in,out] S points to an instance of the Q31 PID structure + @return none + + @par Details + The function resets the state buffer to zeros. + */ + +void riscv_pid_reset_q31( + riscv_pid_instance_q31 * S) +{ + /* Reset state to zero, The size will be always 3 samples */ + memset(S->state, 0, 3U * sizeof(q31_t)); +} + +/** + @} end of PID group + */ diff --git a/components/nmsis/dsp/src/ControllerFunctions/riscv_sin_cos_f32.c b/components/nmsis/dsp/src/ControllerFunctions/riscv_sin_cos_f32.c new file mode 100644 index 00000000..f9da1e0e --- /dev/null +++ b/components/nmsis/dsp/src/ControllerFunctions/riscv_sin_cos_f32.c @@ -0,0 +1,147 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_sin_cos_f32.c + * Description: Sine and Cosine calculation for floating-point values + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/controller_functions.h" +#include "riscv_common_tables.h" + +/** + @ingroup groupController + */ + +/** + @defgroup SinCos Sine Cosine + + Computes the trigonometric sine and cosine values using a combination of table lookup + and linear interpolation. + There are separate functions for Q31 and floating-point data types. + The input to the floating-point version is in degrees while the + fixed-point Q31 have a scaled input with the range + [-1 0.9999] mapping to [-180 +180] degrees. + + The floating point function also allows values that are out of the usual range. When this happens, the function will + take extra time to adjust the input value to the range of [-180 180]. + + The result is accurate to 5 digits after the decimal point. + + The implementation is based on table lookup using 360 values together with linear interpolation. + The steps used are: + -# Calculation of the nearest integer table index. + -# Compute the fractional portion (fract) of the input. + -# Fetch the value corresponding to \c index from sine table to \c y0 and also value from \c index+1 to \c y1. + -# Sine value is computed as *psinVal = y0 + (fract * (y1 - y0)). + -# Fetch the value corresponding to \c index from cosine table to \c y0 and also value from \c index+1 to \c y1. + -# Cosine value is computed as *pcosVal = y0 + (fract * (y1 - y0)). + */ + +/** + @addtogroup SinCos + @{ + */ + +/** + @brief Floating-point sin_cos function. + @param[in] theta input value in degrees + @param[out] pSinVal points to processed sine output + @param[out] pCosVal points to processed cosine output + @return none + */ + +void riscv_sin_cos_f32( + float32_t theta, + float32_t * pSinVal, + float32_t * pCosVal) +{ + float32_t fract, in; /* Temporary input, output variables */ + uint16_t indexS, indexC; /* Index variable */ + float32_t f1, f2, d1, d2; /* Two nearest output values */ + float32_t Dn, Df; + float32_t temp, findex; + + /* input x is in degrees */ + /* Scale input, divide input by 360, for cosine add 0.25 (pi/2) to read sine table */ + in = theta * 0.00277777777778f; + + if (in < 0.0f) + { + in = -in; + } + + in = in - (int32_t)in; + + /* Calculate the nearest index */ + findex = (float32_t)FAST_MATH_TABLE_SIZE * in; + indexS = ((uint16_t)findex) & 0x1ff; + indexC = (indexS + (FAST_MATH_TABLE_SIZE / 4)) & 0x1ff; + + /* Calculation of fractional value */ + fract = findex - (float32_t) indexS; + + /* Read two nearest values of input value from the cos & sin tables */ + f1 = sinTable_f32[indexC ]; + f2 = sinTable_f32[indexC+1]; + d1 = -sinTable_f32[indexS ]; + d2 = -sinTable_f32[indexS+1]; + + temp = (1.0f - fract) * f1 + fract * f2; + + Dn = 0.0122718463030f; /* delta between the two points (fixed), in this case 2*pi/FAST_MATH_TABLE_SIZE */ + Df = f2 - f1; /* delta between the values of the functions */ + + temp = Dn * (d1 + d2) - 2 * Df; + temp = fract * temp + (3 * Df - (d2 + 2 * d1) * Dn); + temp = fract * temp + d1 * Dn; + + /* Calculation of cosine value */ + *pCosVal = fract * temp + f1; + + /* Read two nearest values of input value from the cos & sin tables */ + f1 = sinTable_f32[indexS ]; + f2 = sinTable_f32[indexS+1]; + d1 = sinTable_f32[indexC ]; + d2 = sinTable_f32[indexC+1]; + + temp = (1.0f - fract) * f1 + fract * f2; + + Df = f2 - f1; // delta between the values of the functions + temp = Dn * (d1 + d2) - 2 * Df; + temp = fract * temp + (3 * Df - (d2 + 2 * d1) * Dn); + temp = fract * temp + d1 * Dn; + + /* Calculation of sine value */ + *pSinVal = fract * temp + f1; + + if (theta < 0.0f) + { + *pSinVal = -*pSinVal; + } +} + +/** + @} end of SinCos group + */ diff --git a/components/nmsis/dsp/src/ControllerFunctions/riscv_sin_cos_q31.c b/components/nmsis/dsp/src/ControllerFunctions/riscv_sin_cos_q31.c new file mode 100644 index 00000000..abd1af37 --- /dev/null +++ b/components/nmsis/dsp/src/ControllerFunctions/riscv_sin_cos_q31.c @@ -0,0 +1,111 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_sin_cos_q31.c + * Description: Cosine & Sine calculation for Q31 values + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/controller_functions.h" +#include "riscv_common_tables.h" + +/** + @ingroup groupController + */ + +/** + @addtogroup SinCos + @{ + */ + +/** + @brief Q31 sin_cos function. + @param[in] theta scaled input value in degrees + @param[out] pSinVal points to processed sine output + @param[out] pCosVal points to processed cosine output + @return none + + The Q31 input value is in the range [-1 0.999999] and is mapped to a degree value in the range [-180 179]. + */ + +void riscv_sin_cos_q31( + q31_t theta, + q31_t * pSinVal, + q31_t * pCosVal) +{ + q31_t fract; /* Temporary input, output variables */ + uint16_t indexS, indexC; /* Index variable */ + q31_t f1, f2, d1, d2; /* Two nearest output values */ + q31_t Dn, Df; + q63_t temp; + + /* Calculate the nearest index */ + indexS = (uint32_t)theta >> CONTROLLER_Q31_SHIFT; + indexC = (indexS + 128) & 0x1ff; + + /* Calculation of fractional value */ + fract = (theta - (indexS << CONTROLLER_Q31_SHIFT)) << 8; + + /* Read two nearest values of input value from the cos & sin tables */ + f1 = sinTable_q31[indexC ]; + f2 = sinTable_q31[indexC+1]; + d1 = -sinTable_q31[indexS ]; + d2 = -sinTable_q31[indexS+1]; + + Dn = 0x1921FB5; /* delta between the two points (fixed), in this case 2*pi/FAST_MATH_TABLE_SIZE */ + Df = f2 - f1; /* delta between the values of the functions */ + + temp = Dn * ((q63_t)d1 + d2); + temp = temp - ((q63_t)Df << 32); + temp = (q63_t)fract * (temp >> 31); + temp = temp + ((3 * (q63_t)Df << 31) - (d2 + ((q63_t)d1 << 1)) * Dn); + temp = (q63_t)fract * (temp >> 31); + temp = temp + (q63_t)d1 * Dn; + temp = (q63_t)fract * (temp >> 31); + + /* Calculation of cosine value */ + *pCosVal = clip_q63_to_q31((temp >> 31) + (q63_t)f1); + + /* Read two nearest values of input value from the cos & sin tables */ + f1 = sinTable_q31[indexS ]; + f2 = sinTable_q31[indexS+1]; + d1 = sinTable_q31[indexC ]; + d2 = sinTable_q31[indexC+1]; + + Df = f2 - f1; // delta between the values of the functions + temp = Dn * ((q63_t)d1 + d2); + temp = temp - ((q63_t)Df << 32); + temp = (q63_t)fract * (temp >> 31); + temp = temp + ((3 * (q63_t)Df << 31) - (d2 + ((q63_t)d1 << 1)) * Dn); + temp = (q63_t)fract * (temp >> 31); + temp = temp + (q63_t)d1 * Dn; + temp = (q63_t)fract * (temp >> 31); + + /* Calculation of sine value */ + *pSinVal = clip_q63_to_q31((temp >> 31) + (q63_t)f1); +} + +/** + @} end of SinCos group + */ diff --git a/components/nmsis/dsp/src/DistanceFunctions/DistanceFunctions.c b/components/nmsis/dsp/src/DistanceFunctions/DistanceFunctions.c new file mode 100644 index 00000000..06a715c2 --- /dev/null +++ b/components/nmsis/dsp/src/DistanceFunctions/DistanceFunctions.c @@ -0,0 +1,48 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: BayesFunctions.c + * Description: Combination of all distance function source files. + * + * $Date: 16. March 2020 + * $Revision: V1.0.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2020 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "riscv_boolean_distance.c" +#include "riscv_braycurtis_distance_f32.c" +#include "riscv_canberra_distance_f32.c" +#include "riscv_chebyshev_distance_f32.c" +#include "riscv_cityblock_distance_f32.c" +#include "riscv_correlation_distance_f32.c" +#include "riscv_cosine_distance_f32.c" +#include "riscv_dice_distance.c" +#include "riscv_euclidean_distance_f32.c" +#include "riscv_hamming_distance.c" +#include "riscv_jaccard_distance.c" +#include "riscv_jensenshannon_distance_f32.c" +#include "riscv_kulsinski_distance.c" +#include "riscv_minkowski_distance_f32.c" +#include "riscv_rogerstanimoto_distance.c" +#include "riscv_russellrao_distance.c" +#include "riscv_sokalmichener_distance.c" +#include "riscv_sokalsneath_distance.c" +#include "riscv_yule_distance.c" diff --git a/components/nmsis/dsp/src/DistanceFunctions/DistanceFunctionsF16.c b/components/nmsis/dsp/src/DistanceFunctions/DistanceFunctionsF16.c new file mode 100644 index 00000000..1a977737 --- /dev/null +++ b/components/nmsis/dsp/src/DistanceFunctions/DistanceFunctionsF16.c @@ -0,0 +1,37 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: DistanceFunctions.c + * Description: Combination of all distance function f16 source files. + * + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2020 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "riscv_braycurtis_distance_f16.c" +#include "riscv_canberra_distance_f16.c" +#include "riscv_chebyshev_distance_f16.c" +#include "riscv_cityblock_distance_f16.c" +#include "riscv_correlation_distance_f16.c" +#include "riscv_cosine_distance_f16.c" +#include "riscv_euclidean_distance_f16.c" +#include "riscv_jensenshannon_distance_f16.c" +#include "riscv_minkowski_distance_f16.c" + diff --git a/components/nmsis/dsp/src/DistanceFunctions/riscv_boolean_distance.c b/components/nmsis/dsp/src/DistanceFunctions/riscv_boolean_distance.c new file mode 100644 index 00000000..4956814a --- /dev/null +++ b/components/nmsis/dsp/src/DistanceFunctions/riscv_boolean_distance.c @@ -0,0 +1,76 @@ + +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_svm_linear_init_f32.c + * Description: SVM Linear Instance Initialization + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions.h" +#include +#include + + + + + + +#define TT +#define TF +#define FT +#define EXT _TT_TF_FT +#include "riscv_boolean_distance_template.h" + +#undef TT +#undef FF +#undef TF +#undef FT +#undef EXT +#define TF +#define FT +#define EXT _TF_FT +#include "riscv_boolean_distance_template.h" + +#undef TT +#undef FF +#undef TF +#undef FT +#undef EXT +#define TT +#define FF +#define TF +#define FT +#define EXT _TT_FF_TF_FT +#include "riscv_boolean_distance_template.h" + +#undef TT +#undef FF +#undef TF +#undef FT +#undef EXT +#define TT +#define EXT _TT +#include "riscv_boolean_distance_template.h" + diff --git a/components/nmsis/dsp/src/DistanceFunctions/riscv_boolean_distance_template.h b/components/nmsis/dsp/src/DistanceFunctions/riscv_boolean_distance_template.h new file mode 100644 index 00000000..4078f22e --- /dev/null +++ b/components/nmsis/dsp/src/DistanceFunctions/riscv_boolean_distance_template.h @@ -0,0 +1,176 @@ + +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_boolean_distance.c + * Description: Templates for boolean distances + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + + + +/** + * @defgroup DISTANCEF Distance Functions + * + * Computes Distances between vectors. + * + * Distance functions are useful in a lot of algorithms. + * + */ + + +/** + * @addtogroup DISTANCEF + * @{ + */ + + + + +#define _FUNC(A,B) A##B + +#define FUNC(EXT) _FUNC(riscv_boolean_distance, EXT) + +/** + * @brief Elements of boolean distances + * + * Different values which are used to compute boolean distances + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return None + * + */ + + +void FUNC(EXT)(const uint32_t *pA + , const uint32_t *pB + , uint32_t numberOfBools +#ifdef TT + , uint32_t *cTT +#endif +#ifdef FF + , uint32_t *cFF +#endif +#ifdef TF + , uint32_t *cTF +#endif +#ifdef FT + , uint32_t *cFT +#endif + ) +{ + +#ifdef TT + uint32_t _ctt=0; +#endif +#ifdef FF + uint32_t _cff=0; +#endif +#ifdef TF + uint32_t _ctf=0; +#endif +#ifdef FT + uint32_t _cft=0; +#endif + uint32_t a,b,ba,bb; + int shift; + + while(numberOfBools >= 32) + { + a = *pA++; + b = *pB++; + shift = 0; + while(shift < 32) + { + ba = a & 1; + bb = b & 1; + a = a >> 1; + b = b >> 1; +#ifdef TT + _ctt += (ba && bb); +#endif +#ifdef FF + _cff += ((1 ^ ba) && (1 ^ bb)); +#endif +#ifdef TF + _ctf += (ba && (1 ^ bb)); +#endif +#ifdef FT + _cft += ((1 ^ ba) && bb); +#endif + shift ++; + } + + numberOfBools -= 32; + } + + a = *pA++; + b = *pB++; + + a = a >> (32 - numberOfBools); + b = b >> (32 - numberOfBools); + + while(numberOfBools > 0) + { + ba = a & 1; + bb = b & 1; + a = a >> 1; + b = b >> 1; + +#ifdef TT + _ctt += (ba && bb); +#endif +#ifdef FF + _cff += ((1 ^ ba) && (1 ^ bb)); +#endif +#ifdef TF + _ctf += (ba && (1 ^ bb)); +#endif +#ifdef FT + _cft += ((1 ^ ba) && bb); +#endif + numberOfBools --; + } + +#ifdef TT + *cTT = _ctt; +#endif +#ifdef FF + *cFF = _cff; +#endif +#ifdef TF + *cTF = _ctf; +#endif +#ifdef FT + *cFT = _cft; +#endif +} + + +/** + * @} end of DISTANCEF group + */ diff --git a/components/nmsis/dsp/src/DistanceFunctions/riscv_braycurtis_distance_f16.c b/components/nmsis/dsp/src/DistanceFunctions/riscv_braycurtis_distance_f16.c new file mode 100644 index 00000000..242d9adc --- /dev/null +++ b/components/nmsis/dsp/src/DistanceFunctions/riscv_braycurtis_distance_f16.c @@ -0,0 +1,102 @@ + +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_braycurtis_distance_f16.c + * Description: Bray-Curtis distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions_f16.h" + +#if defined(RISCV_FLOAT16_SUPPORTED) + +#include +#include + +/** + * @ingroup groupDistance + */ + +/** + * @defgroup FloatDist Float Distances + * + * Distances between two vectors of float values. + */ + +/** + @ingroup FloatDist + */ + +/** + @defgroup braycurtis Bray-Curtis distance + + Bray-Curtis distance between two vectors + */ + +/** + @addtogroup braycurtis + @{ + */ + + +/** + * @brief Bray-Curtis distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + +float16_t riscv_braycurtis_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize) +{ + _Float16 accumDiff=0.0f16, accumSum=0.0f16, tmpA, tmpB; + + while(blockSize > 0) + { + tmpA = *pA++; + tmpB = *pB++; + accumDiff += (_Float16)fabsf(tmpA - tmpB); + accumSum += (_Float16)fabsf(tmpA + tmpB); + blockSize --; + } + /* + + It is assumed that accumSum is not zero. Since it is the sum of several absolute + values it would imply that all of them are zero. It is very unlikely for long vectors. + + */ + return(accumDiff / accumSum); +} + + +/** + * @} end of braycurtis group + */ + + + +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ + diff --git a/components/nmsis/dsp/src/DistanceFunctions/riscv_braycurtis_distance_f32.c b/components/nmsis/dsp/src/DistanceFunctions/riscv_braycurtis_distance_f32.c new file mode 100644 index 00000000..1398f2de --- /dev/null +++ b/components/nmsis/dsp/src/DistanceFunctions/riscv_braycurtis_distance_f32.c @@ -0,0 +1,104 @@ + +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_braycurtis_distance_f32.c + * Description: Bray-Curtis distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions.h" +#include +#include + + + +/** + @addtogroup braycurtis + @{ + */ + + +/** + * @brief Bray-Curtis distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float32_t riscv_braycurtis_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize) +{ + float32_t accumDiff=0.0f, accumSum=0.0f, tmpA, tmpB; + +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + size_t l; + vfloat32m8_t v_x, v_y; + vfloat32m8_t v_a, v_b; + vfloat32m8_t v_at, v_bt; + vfloat32m1_t v_temp; + l = vsetvl_e32m1(1); + v_temp = vfsub_vv_f32m1(v_temp, v_temp, l); + l = vsetvl_e32m8(blkCnt); + v_a = vfsub_vv_f32m8(v_a,v_a, l); + v_b = vfsub_vv_f32m8(v_b,v_b, l); + for (; (l = vsetvl_e32m8(blkCnt)) > 0; blkCnt -= l) { + v_x = vle32_v_f32m8(pA, l); + v_y = vle32_v_f32m8(pB, l); + v_at = vfsub_vv_f32m8(v_x,v_y, l); + v_bt = vfadd_vv_f32m8(v_x,v_y, l); + v_a = vfadd_vv_f32m8 (v_a, vfsgnjx_vv_f32m8(v_at, v_at, l), l); + v_b = vfadd_vv_f32m8 (v_b, vfsgnjx_vv_f32m8(v_bt, v_bt, l), l); + pA += l; + pB += l; + } + l = vsetvl_e32m8(blockSize); + accumDiff = vfmv_f_s_f32m1_f32 (vfredsum_vs_f32m8_f32m1(v_temp,v_a,v_temp, l)); + l = vsetvl_e32m8(blockSize); + accumSum = vfmv_f_s_f32m1_f32 (vfredsum_vs_f32m8_f32m1(v_temp,v_b,v_temp, l)); +#else + while(blockSize > 0) + { + tmpA = *pA++; + tmpB = *pB++; + accumDiff += fabsf(tmpA - tmpB); + accumSum += fabsf(tmpA + tmpB); + blockSize --; + } +#endif + /* + + It is assumed that accumSum is not zero. Since it is the sum of several absolute + values it would imply that all of them are zero. It is very unlikely for long vectors. + + */ + return(accumDiff / accumSum); +} + + +/** + * @} end of braycurtis group + */ + diff --git a/components/nmsis/dsp/src/DistanceFunctions/riscv_canberra_distance_f16.c b/components/nmsis/dsp/src/DistanceFunctions/riscv_canberra_distance_f16.c new file mode 100644 index 00000000..8d5d088d --- /dev/null +++ b/components/nmsis/dsp/src/DistanceFunctions/riscv_canberra_distance_f16.c @@ -0,0 +1,95 @@ + +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_canberra_distance_f16.c + * Description: Canberra distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions_f16.h" + +#if defined(RISCV_FLOAT16_SUPPORTED) + +#include +#include + +/** + @ingroup FloatDist + */ + +/** + @defgroup Canberra Canberra distance + + Canberra distance + */ + + +/** + @addtogroup Canberra + @{ + */ + + +/** + * @brief Canberra distance between two vectors + * + * This function may divide by zero when samples pA[i] and pB[i] are both zero. + * The result of the computation will be correct. So the division per zero may be + * ignored. + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + +float16_t riscv_canberra_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize) +{ + _Float16 accum=0.0f, tmpA, tmpB,diff,sum; + + while(blockSize > 0) + { + tmpA = *pA++; + tmpB = *pB++; + + diff = fabsf(tmpA - tmpB); + sum = fabsf(tmpA) + fabsf(tmpB); + if ((tmpA != 0.0f16) || (tmpB != 0.0f16)) + { + accum += (diff / sum); + } + blockSize --; + } + return(accum); +} + + +/** + * @} end of Canberra group + */ + +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ + diff --git a/components/nmsis/dsp/src/DistanceFunctions/riscv_canberra_distance_f32.c b/components/nmsis/dsp/src/DistanceFunctions/riscv_canberra_distance_f32.c new file mode 100644 index 00000000..3f6f416e --- /dev/null +++ b/components/nmsis/dsp/src/DistanceFunctions/riscv_canberra_distance_f32.c @@ -0,0 +1,79 @@ + +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_canberra_distance_f32.c + * Description: Canberra distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions.h" +#include +#include + + +/** + @addtogroup Canberra + @{ + */ + + +/** + * @brief Canberra distance between two vectors + * + * This function may divide by zero when samples pA[i] and pB[i] are both zero. + * The result of the computation will be correct. So the division per zero may be + * ignored. + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + +float32_t riscv_canberra_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize) +{ + float32_t accum=0.0f, tmpA, tmpB,diff,sum; + + while(blockSize > 0) + { + tmpA = *pA++; + tmpB = *pB++; + + diff = fabsf(tmpA - tmpB); + sum = fabsf(tmpA) + fabsf(tmpB); + if ((tmpA != 0.0f) || (tmpB != 0.0f)) + { + accum += (diff / sum); + } + blockSize --; + } + return(accum); +} + + +/** + * @} end of Canberra group + */ diff --git a/components/nmsis/dsp/src/DistanceFunctions/riscv_chebyshev_distance_f16.c b/components/nmsis/dsp/src/DistanceFunctions/riscv_chebyshev_distance_f16.c new file mode 100644 index 00000000..cd753e63 --- /dev/null +++ b/components/nmsis/dsp/src/DistanceFunctions/riscv_chebyshev_distance_f16.c @@ -0,0 +1,94 @@ + +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_chebyshev_distance_f16.c + * Description: Chebyshev distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions_f16.h" + +#if defined(RISCV_FLOAT16_SUPPORTED) + +#include +#include + +/** + @ingroup FloatDist + */ + +/** + @defgroup Chebyshev Chebyshev distance + + Chebyshev distance + */ + +/** + @addtogroup Chebyshev + @{ + */ + + +/** + * @brief Chebyshev distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + +float16_t riscv_chebyshev_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize) +{ + _Float16 diff=0.0f, maxVal,tmpA, tmpB; + + tmpA = *pA++; + tmpB = *pB++; + diff = fabsf(tmpA - tmpB); + maxVal = diff; + blockSize--; + + while(blockSize > 0) + { + tmpA = *pA++; + tmpB = *pB++; + diff = fabsf(tmpA - tmpB); + if (diff > maxVal) + { + maxVal = diff; + } + blockSize --; + } + + return(maxVal); +} + + +/** + * @} end of Chebyshev group + */ + +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ + diff --git a/components/nmsis/dsp/src/DistanceFunctions/riscv_chebyshev_distance_f32.c b/components/nmsis/dsp/src/DistanceFunctions/riscv_chebyshev_distance_f32.c new file mode 100644 index 00000000..32ef2dc5 --- /dev/null +++ b/components/nmsis/dsp/src/DistanceFunctions/riscv_chebyshev_distance_f32.c @@ -0,0 +1,103 @@ + +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_chebyshev_distance_f32.c + * Description: Chebyshev distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions.h" +#include +#include + + +/** + @addtogroup Chebyshev + @{ + */ + + +/** + * @brief Chebyshev distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + +float32_t riscv_chebyshev_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize) +{ + float32_t diff=0.0f, maxVal,tmpA, tmpB; + + tmpA = *pA++; + tmpB = *pB++; + diff = fabsf(tmpA - tmpB); + maxVal = diff; + blockSize--; + +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + float32_t max_temp; + size_t l; + vfloat32m8_t v_x, v_y; + vfloat32m8_t v_a, v_b; + vfloat32m8_t v_at, v_bt; + vfloat32m1_t v_temp; + l = vsetvl_e32m1(1); + v_temp = vfsub_vv_f32m1(v_temp, v_temp, l); + l = vsetvl_e32m8(blkCnt); + v_a = vfsub_vv_f32m8(v_a,v_a, l); + v_b = vfsub_vv_f32m8(v_b,v_b, l); + for (; (l = vsetvl_e32m8(blkCnt)) > 0; blkCnt -= l) { + v_x = vle32_v_f32m8(pA, l); + v_y = vle32_v_f32m8(pB, l); + v_at = vfsub_vv_f32m8(v_x,v_y, l); + v_at = vfsgnjx_vv_f32m8(v_at, v_at, l); + max_temp = vfmv_f_s_f32m1_f32 (vfredmax_vs_f32m8_f32m1(v_temp,v_at,v_temp, l)); + pA += l; + pB += l; + if(max_temp > maxVal) maxVal = max_temp; + } +#else + while(blockSize > 0) + { + tmpA = *pA++; + tmpB = *pB++; + diff = fabsf(tmpA - tmpB); + if (diff > maxVal) + { + maxVal = diff; + } + blockSize --; + } +#endif + return(maxVal); +} + + +/** + * @} end of Chebyshev group + */ diff --git a/components/nmsis/dsp/src/DistanceFunctions/riscv_cityblock_distance_f16.c b/components/nmsis/dsp/src/DistanceFunctions/riscv_cityblock_distance_f16.c new file mode 100644 index 00000000..7c5cf89f --- /dev/null +++ b/components/nmsis/dsp/src/DistanceFunctions/riscv_cityblock_distance_f16.c @@ -0,0 +1,84 @@ + +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_cityblock_distance_f16.c + * Description: Cityblock (Manhattan) distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions_f16.h" + +#if defined(RISCV_FLOAT16_SUPPORTED) + +#include +#include + +/** + @ingroup FloatDist + */ + +/** + @defgroup Manhattan Cityblock (Manhattan) distance + + Cityblock (Manhattan) distance + */ + +/** + @addtogroup Manhattan + @{ + */ + + +/** + * @brief Cityblock (Manhattan) distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float16_t riscv_cityblock_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize) +{ + _Float16 accum,tmpA, tmpB; + + accum = 0.0f16; + while(blockSize > 0) + { + tmpA = *pA++; + tmpB = *pB++; + accum += (_Float16)fabsf(tmpA - tmpB); + + blockSize --; + } + + return(accum); +} + +/** + * @} end of Manhattan group + */ + +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ + diff --git a/components/nmsis/dsp/src/DistanceFunctions/riscv_cityblock_distance_f32.c b/components/nmsis/dsp/src/DistanceFunctions/riscv_cityblock_distance_f32.c new file mode 100644 index 00000000..753a737d --- /dev/null +++ b/components/nmsis/dsp/src/DistanceFunctions/riscv_cityblock_distance_f32.c @@ -0,0 +1,91 @@ + +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_cityblock_distance_f32.c + * Description: Cityblock (Manhattan) distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions.h" +#include +#include + +/** + @addtogroup Manhattan + @{ + */ + + +/** + * @brief Cityblock (Manhattan) distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float32_t riscv_cityblock_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize) +{ + float32_t accum,tmpA, tmpB; + +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + size_t l; + vfloat32m8_t v_x, v_y; + vfloat32m8_t v_a, v_b; + vfloat32m8_t v_at, v_bt; + vfloat32m1_t v_temp; + l = vsetvl_e32m1(1); + v_temp = vfsub_vv_f32m1(v_temp, v_temp, l); + l = vsetvl_e32m8(blkCnt); + v_a = vfsub_vv_f32m8(v_a,v_a, l); + for (; (l = vsetvl_e32m8(blkCnt)) > 0; blkCnt -= l) { + v_x = vle32_v_f32m8(pA, l); + v_y = vle32_v_f32m8(pB, l); + v_at = vfsub_vv_f32m8(v_x,v_y, l); + v_a = vfadd_vv_f32m8(v_a,vfsgnjx_vv_f32m8(v_at, v_at, l), l); + pA += l; + pB += l; + } + l = vsetvl_e32m8(blockSize); + accum = vfmv_f_s_f32m1_f32 (vfredsum_vs_f32m8_f32m1(v_temp,v_a,v_temp, l)); +#else + accum = 0.0f; + while(blockSize > 0) + { + tmpA = *pA++; + tmpB = *pB++; + accum += fabsf(tmpA - tmpB); + + blockSize --; + } +#endif + + return(accum); +} + +/** + * @} end of Manhattan group + */ diff --git a/components/nmsis/dsp/src/DistanceFunctions/riscv_correlation_distance_f16.c b/components/nmsis/dsp/src/DistanceFunctions/riscv_correlation_distance_f16.c new file mode 100644 index 00000000..049dadf1 --- /dev/null +++ b/components/nmsis/dsp/src/DistanceFunctions/riscv_correlation_distance_f16.c @@ -0,0 +1,100 @@ + +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_correlation_distance_f16.c + * Description: Correlation distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions_f16.h" + +#if defined(RISCV_FLOAT16_SUPPORTED) + +#include +#include + + +/** + @ingroup FloatDist + */ + +/** + @defgroup Correlation Correlation distance + + Correlation distance + */ + +/** + @addtogroup Correlation + @{ + */ + + +/** + * @brief Correlation distance between two vectors + * + * The input vectors are modified in place ! + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + +float16_t riscv_correlation_distance_f16(float16_t *pA,float16_t *pB, uint32_t blockSize) +{ + float16_t ma,mb,pwra,pwrb,dot,tmp; + + riscv_mean_f16(pA, blockSize, &ma); + riscv_mean_f16(pB, blockSize, &mb); + + riscv_offset_f16(pA, -ma, pA, blockSize); + riscv_offset_f16(pB, -mb, pB, blockSize); + + riscv_power_f16(pA, blockSize, &pwra); + riscv_power_f16(pB, blockSize, &pwrb); + + riscv_dot_prod_f16(pA,pB,blockSize,&dot); + + dot = dot / blockSize; + pwra = pwra / blockSize; + pwrb = pwrb / blockSize; + + riscv_sqrt_f16(pwra * pwrb,&tmp); + + return(1.0f - dot / tmp); + + +} + + + +/** + * @} end of Correlation group + */ + +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ + diff --git a/components/nmsis/dsp/src/DistanceFunctions/riscv_correlation_distance_f32.c b/components/nmsis/dsp/src/DistanceFunctions/riscv_correlation_distance_f32.c new file mode 100644 index 00000000..ea14c097 --- /dev/null +++ b/components/nmsis/dsp/src/DistanceFunctions/riscv_correlation_distance_f32.c @@ -0,0 +1,85 @@ + +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_correlation_distance_f32.c + * Description: Correlation distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions.h" +#include +#include + + + +/** + @addtogroup Correlation + @{ + */ + + +/** + * @brief Correlation distance between two vectors + * + * The input vectors are modified in place ! + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + +float32_t riscv_correlation_distance_f32(float32_t *pA,float32_t *pB, uint32_t blockSize) +{ + float32_t ma,mb,pwra,pwrb,dot,tmp; + + riscv_mean_f32(pA, blockSize, &ma); + riscv_mean_f32(pB, blockSize, &mb); + + riscv_offset_f32(pA, -ma, pA, blockSize); + riscv_offset_f32(pB, -mb, pB, blockSize); + + riscv_power_f32(pA, blockSize, &pwra); + riscv_power_f32(pB, blockSize, &pwrb); + + riscv_dot_prod_f32(pA,pB,blockSize,&dot); + + dot = dot / blockSize; + pwra = pwra / blockSize; + pwrb = pwrb / blockSize; + + riscv_sqrt_f32(pwra * pwrb,&tmp); + + return(1.0f - dot / tmp); + + +} + + + +/** + * @} end of Correlation group + */ diff --git a/components/nmsis/dsp/src/DistanceFunctions/riscv_cosine_distance_f16.c b/components/nmsis/dsp/src/DistanceFunctions/riscv_cosine_distance_f16.c new file mode 100644 index 00000000..00f9e590 --- /dev/null +++ b/components/nmsis/dsp/src/DistanceFunctions/riscv_cosine_distance_f16.c @@ -0,0 +1,87 @@ + +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_cosine_distance_f16.c + * Description: Cosine distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions_f16.h" + +#if defined(RISCV_FLOAT16_SUPPORTED) + +#include +#include + +/** + @ingroup FloatDist + */ + +/** + @defgroup CosineDist Cosine distance + + Cosine distance + */ + + +/** + @addtogroup CosineDist + @{ + */ + + + +/** + * @brief Cosine distance between two vectors + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + +float16_t riscv_cosine_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize) +{ + float16_t pwra,pwrb,dot,tmp; + + riscv_power_f16(pA, blockSize, &pwra); + riscv_power_f16(pB, blockSize, &pwrb); + + riscv_dot_prod_f16(pA,pB,blockSize,&dot); + + riscv_sqrt_f16(pwra * pwrb, &tmp); + return(1.0f - dot / tmp); + +} + + + +/** + * @} end of CosineDist group + */ + +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ + diff --git a/components/nmsis/dsp/src/DistanceFunctions/riscv_cosine_distance_f32.c b/components/nmsis/dsp/src/DistanceFunctions/riscv_cosine_distance_f32.c new file mode 100644 index 00000000..2a8044ee --- /dev/null +++ b/components/nmsis/dsp/src/DistanceFunctions/riscv_cosine_distance_f32.c @@ -0,0 +1,71 @@ + +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_cosine_distance_f32.c + * Description: Cosine distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions.h" +#include +#include + + +/** + @addtogroup CosineDist + @{ + */ + + + +/** + * @brief Cosine distance between two vectors + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + +float32_t riscv_cosine_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize) +{ + float32_t pwra,pwrb,dot,tmp; + + riscv_power_f32(pA, blockSize, &pwra); + riscv_power_f32(pB, blockSize, &pwrb); + + riscv_dot_prod_f32(pA,pB,blockSize,&dot); + + riscv_sqrt_f32(pwra * pwrb, &tmp); + return(1.0f - dot / tmp); + +} + + + +/** + * @} end of CosineDist group + */ diff --git a/components/nmsis/dsp/src/DistanceFunctions/riscv_dice_distance.c b/components/nmsis/dsp/src/DistanceFunctions/riscv_dice_distance.c new file mode 100644 index 00000000..55f6452b --- /dev/null +++ b/components/nmsis/dsp/src/DistanceFunctions/riscv_dice_distance.c @@ -0,0 +1,93 @@ + +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_dice_distance.c + * Description: Dice distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions.h" +#include +#include + +extern void riscv_boolean_distance_TT_TF_FT(const uint32_t *pA + , const uint32_t *pB + , uint32_t numberOfBools + , uint32_t *cTT + , uint32_t *cTF + , uint32_t *cFT + ); + + +/** + * @ingroup groupDistance + * @{ + */ + +/** + * @defgroup BoolDist Boolean Distances + * + * Distances between two vectors of boolean values. + * + * Booleans are packed in 32 bit words. + * numberOfBooleans argument is the number of booleans and not the + * number of words. + * + * Bits are packed in big-endian mode (because of behavior of numpy packbits in + * in version < 1.17) + */ + +/** + @addtogroup BoolDist + @{ + */ + +/** + * @brief Dice distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t riscv_dice_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools) +{ + uint32_t ctt=0,ctf=0,cft=0; + + riscv_boolean_distance_TT_TF_FT(pA, pB, numberOfBools, &ctt, &ctf, &cft); + + return(1.0*(ctf + cft) / (2.0*ctt + cft + ctf)); +} + + +/** + * @} end of BoolDist group + */ + +/** + * @} end of groupDistance group + */ diff --git a/components/nmsis/dsp/src/DistanceFunctions/riscv_euclidean_distance_f16.c b/components/nmsis/dsp/src/DistanceFunctions/riscv_euclidean_distance_f16.c new file mode 100644 index 00000000..27bf78e1 --- /dev/null +++ b/components/nmsis/dsp/src/DistanceFunctions/riscv_euclidean_distance_f16.c @@ -0,0 +1,86 @@ + +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_euclidean_distance_f16.c + * Description: Euclidean distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions_f16.h" + +#if defined(RISCV_FLOAT16_SUPPORTED) + +#include +#include + + +/** + @ingroup FloatDist + */ + +/** + @defgroup Euclidean Euclidean distance + + Euclidean distance + */ + + +/** + @addtogroup Euclidean + @{ + */ + + +/** + * @brief Euclidean distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float16_t riscv_euclidean_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize) +{ + _Float16 accum=0.0f,tmp; + float16_t result; + + while(blockSize > 0) + { + tmp = (_Float16)*pA++ - (_Float16)*pB++; + accum += SQ(tmp); + blockSize --; + } + riscv_sqrt_f16(accum,&result); + return(result); +} + + + +/** + * @} end of Euclidean group + */ + +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ + diff --git a/components/nmsis/dsp/src/DistanceFunctions/riscv_euclidean_distance_f32.c b/components/nmsis/dsp/src/DistanceFunctions/riscv_euclidean_distance_f32.c new file mode 100644 index 00000000..9357cfdb --- /dev/null +++ b/components/nmsis/dsp/src/DistanceFunctions/riscv_euclidean_distance_f32.c @@ -0,0 +1,90 @@ + +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_euclidean_distance_f32.c + * Description: Euclidean distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions.h" +#include +#include + + + +/** + @addtogroup Euclidean + @{ + */ + + +/** + * @brief Euclidean distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float32_t riscv_euclidean_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize) +{ + float32_t accum=0.0f,tmp; +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + size_t l; + vfloat32m8_t v_x, v_y; + vfloat32m8_t v_a, v_b; + vfloat32m8_t v_at, v_bt; + vfloat32m1_t v_temp; + l = vsetvl_e32m1(1); + v_temp = vfsub_vv_f32m1(v_temp, v_temp, l); + l = vsetvl_e32m8(blkCnt); + v_a = vfsub_vv_f32m8(v_a,v_a, l); + for (; (l = vsetvl_e32m8(blkCnt)) > 0; blkCnt -= l) { + v_x = vle32_v_f32m8(pA, l); + v_y = vle32_v_f32m8(pB, l); + v_at = vfsub_vv_f32m8(v_x,v_y, l); + v_a = vfmacc_vv_f32m8(v_a,v_at,v_at, l); + pA += l; + pB += l; + } + l = vsetvl_e32m8(blockSize); + accum = vfmv_f_s_f32m1_f32 (vfredsum_vs_f32m8_f32m1(v_temp,v_a,v_temp, l)); +#else + while(blockSize > 0) + { + tmp = *pA++ - *pB++; + accum += SQ(tmp); + blockSize --; + } +#endif + riscv_sqrt_f32(accum,&tmp); + return(tmp); +} + + +/** + * @} end of Euclidean group + */ diff --git a/components/nmsis/dsp/src/DistanceFunctions/riscv_hamming_distance.c b/components/nmsis/dsp/src/DistanceFunctions/riscv_hamming_distance.c new file mode 100644 index 00000000..04963974 --- /dev/null +++ b/components/nmsis/dsp/src/DistanceFunctions/riscv_hamming_distance.c @@ -0,0 +1,71 @@ + +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_hamming_distance.c + * Description: Hamming distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions.h" +#include +#include + + +extern void riscv_boolean_distance_TF_FT(const uint32_t *pA + , const uint32_t *pB + , uint32_t numberOfBools + , uint32_t *cTF + , uint32_t *cFT + ); + +/** + @addtogroup BoolDist + @{ + */ + + +/** + * @brief Hamming distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t riscv_hamming_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools) +{ + uint32_t ctf=0,cft=0; + + riscv_boolean_distance_TF_FT(pA, pB, numberOfBools, &ctf, &cft); + + return(1.0*(ctf + cft) / numberOfBools); +} + + +/** + * @} end of BoolDist group + */ diff --git a/components/nmsis/dsp/src/DistanceFunctions/riscv_jaccard_distance.c b/components/nmsis/dsp/src/DistanceFunctions/riscv_jaccard_distance.c new file mode 100644 index 00000000..a26628d1 --- /dev/null +++ b/components/nmsis/dsp/src/DistanceFunctions/riscv_jaccard_distance.c @@ -0,0 +1,73 @@ + +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_jaccard_distance.c + * Description: Jaccard distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions.h" +#include +#include + + + +extern void riscv_boolean_distance_TT_TF_FT(const uint32_t *pA + , const uint32_t *pB + , uint32_t numberOfBools + , uint32_t *cTT + , uint32_t *cTF + , uint32_t *cFT + ); + + +/** + @addtogroup BoolDist + @{ + */ + +/** + * @brief Jaccard distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t riscv_jaccard_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools) +{ + uint32_t ctt=0,ctf=0,cft=0; + + riscv_boolean_distance_TT_TF_FT(pA, pB, numberOfBools, &ctt, &ctf, &cft); + + return(1.0*(ctf + cft) / (ctt + cft + ctf)); +} + + +/** + * @} end of BoolDist group + */ diff --git a/components/nmsis/dsp/src/DistanceFunctions/riscv_jensenshannon_distance_f16.c b/components/nmsis/dsp/src/DistanceFunctions/riscv_jensenshannon_distance_f16.c new file mode 100644 index 00000000..2f53821e --- /dev/null +++ b/components/nmsis/dsp/src/DistanceFunctions/riscv_jensenshannon_distance_f16.c @@ -0,0 +1,112 @@ + +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_jensenshannon_distance_f16.c + * Description: Jensen-Shannon distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions_f16.h" + +#if defined(RISCV_FLOAT16_SUPPORTED) + +#include +#include + +/** + @ingroup FloatDist + */ + +/** + @defgroup JensenShannon Jensen-Shannon distance + + Jensen-Shannon distance + */ + + +/** + @addtogroup JensenShannon + @{ + */ + +/// @private +__STATIC_INLINE float16_t rel_entr(float16_t x, float16_t y) +{ + return (x * logf(x / y)); +} + + + + +/** + * @brief Jensen-Shannon distance between two vectors + * + * This function is assuming that elements of second vector are > 0 + * and 0 only when the corresponding element of first vector is 0. + * Otherwise the result of the computation does not make sense + * and for speed reasons, the cases returning NaN or Infinity are not + * managed. + * + * When the function is computing x log (x / y) with x == 0 and y == 0, + * it will compute the right result (0) but a division by zero will occur + * and should be ignored in client code. + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + + +float16_t riscv_jensenshannon_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize) +{ + _Float16 left, right,sum, tmp; + float16_t result; + uint32_t i; + + left = 0.0f16; + right = 0.0f16; + for(i=0; i < blockSize; i++) + { + tmp = ((_Float16)pA[i] + (_Float16)pB[i]) / 2.0f16; + left += (_Float16)rel_entr(pA[i], tmp); + right += (_Float16)rel_entr(pB[i], tmp); + } + + + sum = left + right; + riscv_sqrt_f16(sum/2.0f, &result); + return(result); + +} + + +/** + * @} end of JensenShannon group + */ + +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ + diff --git a/components/nmsis/dsp/src/DistanceFunctions/riscv_jensenshannon_distance_f32.c b/components/nmsis/dsp/src/DistanceFunctions/riscv_jensenshannon_distance_f32.c new file mode 100644 index 00000000..68290b73 --- /dev/null +++ b/components/nmsis/dsp/src/DistanceFunctions/riscv_jensenshannon_distance_f32.c @@ -0,0 +1,96 @@ + +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_jensenshannon_distance_f32.c + * Description: Jensen-Shannon distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions.h" +#include +#include + + +/** + @addtogroup JensenShannon + @{ + */ + +/// @private +__STATIC_INLINE float32_t rel_entr(float32_t x, float32_t y) +{ + return (x * logf(x / y)); +} + + + + + +/** + * @brief Jensen-Shannon distance between two vectors + * + * This function is assuming that elements of second vector are > 0 + * and 0 only when the corresponding element of first vector is 0. + * Otherwise the result of the computation does not make sense + * and for speed reasons, the cases returning NaN or Infinity are not + * managed. + * + * When the function is computing x log (x / y) with x == 0 and y == 0, + * it will compute the right result (0) but a division by zero will occur + * and should be ignored in client code. + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + + +float32_t riscv_jensenshannon_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize) +{ + float32_t left, right,sum, result, tmp; + uint32_t i; + + left = 0.0f; + right = 0.0f; + for(i=0; i < blockSize; i++) + { + tmp = (pA[i] + pB[i]) / 2.0f; + left += rel_entr(pA[i], tmp); + right += rel_entr(pB[i], tmp); + } + + + sum = left + right; + riscv_sqrt_f32(sum/2.0f, &result); + return(result); + +} + + +/** + * @} end of JensenShannon group + */ diff --git a/components/nmsis/dsp/src/DistanceFunctions/riscv_kulsinski_distance.c b/components/nmsis/dsp/src/DistanceFunctions/riscv_kulsinski_distance.c new file mode 100644 index 00000000..0c3136f7 --- /dev/null +++ b/components/nmsis/dsp/src/DistanceFunctions/riscv_kulsinski_distance.c @@ -0,0 +1,74 @@ + +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_kulsinski_distance.c + * Description: Kulsinski distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions.h" +#include +#include + + + +extern void riscv_boolean_distance_TT_TF_FT(const uint32_t *pA + , const uint32_t *pB + , uint32_t numberOfBools + , uint32_t *cTT + , uint32_t *cTF + , uint32_t *cFT + ); + + +/** + @addtogroup BoolDist + @{ + */ + + +/** + * @brief Kulsinski distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t riscv_kulsinski_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools) +{ + uint32_t ctt=0,ctf=0,cft=0; + + riscv_boolean_distance_TT_TF_FT(pA, pB, numberOfBools, &ctt, &ctf, &cft); + + return(1.0*(ctf + cft - ctt + numberOfBools) / (cft + ctf + numberOfBools)); +} + + +/** + * @} end of BoolDist group + */ diff --git a/components/nmsis/dsp/src/DistanceFunctions/riscv_minkowski_distance_f16.c b/components/nmsis/dsp/src/DistanceFunctions/riscv_minkowski_distance_f16.c new file mode 100644 index 00000000..8ab1f8a5 --- /dev/null +++ b/components/nmsis/dsp/src/DistanceFunctions/riscv_minkowski_distance_f16.c @@ -0,0 +1,90 @@ + +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_minkowski_distance_f16.c + * Description: Minkowski distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions_f16.h" + +#if defined(RISCV_FLOAT16_SUPPORTED) + +#include +#include + +/** + @ingroup FloatDist + */ + +/** + @defgroup Minkowski Minkowski distance + + Minkowski distance + */ + +/** + @addtogroup Minkowski + @{ + */ + + +/** + * @brief Minkowski distance between two vectors + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] order Distance order + * @param[in] blockSize Number of samples + * @return distance + * + */ + + + +float16_t riscv_minkowski_distance_f16(const float16_t *pA,const float16_t *pB, int32_t order, uint32_t blockSize) +{ + _Float16 sum; + uint32_t i; + + sum = 0.0f; + for(i=0; i < blockSize; i++) + { + sum += (_Float16)powf(fabsf(pA[i] - pB[i]),order); + } + + + return(powf(sum,(1.0f/order))); + +} + + + +/** + * @} end of Minkowski group + */ + +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ + diff --git a/components/nmsis/dsp/src/DistanceFunctions/riscv_minkowski_distance_f32.c b/components/nmsis/dsp/src/DistanceFunctions/riscv_minkowski_distance_f32.c new file mode 100644 index 00000000..623ef36c --- /dev/null +++ b/components/nmsis/dsp/src/DistanceFunctions/riscv_minkowski_distance_f32.c @@ -0,0 +1,75 @@ + +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_minkowski_distance_f32.c + * Description: Minkowski distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions.h" +#include +#include + + +/** + @addtogroup Minkowski + @{ + */ + +/* 6.14 bug */ + +/** + * @brief Minkowski distance between two vectors + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] order Distance order + * @param[in] blockSize Number of samples + * @return distance + * + */ + + + +float32_t riscv_minkowski_distance_f32(const float32_t *pA,const float32_t *pB, int32_t order, uint32_t blockSize) +{ + float32_t sum; + uint32_t i; + + sum = 0.0f; + for(i=0; i < blockSize; i++) + { + sum += powf(fabsf(pA[i] - pB[i]),order); + } + + + return(powf(sum,(1.0f/order))); + +} + + +/** + * @} end of Minkowski group + */ diff --git a/components/nmsis/dsp/src/DistanceFunctions/riscv_rogerstanimoto_distance.c b/components/nmsis/dsp/src/DistanceFunctions/riscv_rogerstanimoto_distance.c new file mode 100644 index 00000000..41d820b9 --- /dev/null +++ b/components/nmsis/dsp/src/DistanceFunctions/riscv_rogerstanimoto_distance.c @@ -0,0 +1,76 @@ + +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_rogerstanimoto_distance.c + * Description: Roger Stanimoto distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions.h" +#include +#include + + + +extern void riscv_boolean_distance_TT_FF_TF_FT(const uint32_t *pA + , const uint32_t *pB + , uint32_t numberOfBools + , uint32_t *cTT + , uint32_t *cFF + , uint32_t *cTF + , uint32_t *cFT + ); + + +/** + @addtogroup BoolDist + @{ + */ + +/** + * @brief Rogers Tanimoto distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t riscv_rogerstanimoto_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools) +{ + uint32_t ctt=0,cff=0,ctf=0,cft=0,r; + + riscv_boolean_distance_TT_FF_TF_FT(pA, pB, numberOfBools, &ctt,&cff, &ctf, &cft); + + r = 2*(ctf + cft); + + return(1.0*r / (r + ctt + cff)); +} + + +/** + * @} end of BoolDist group + */ diff --git a/components/nmsis/dsp/src/DistanceFunctions/riscv_russellrao_distance.c b/components/nmsis/dsp/src/DistanceFunctions/riscv_russellrao_distance.c new file mode 100644 index 00000000..31b7ab95 --- /dev/null +++ b/components/nmsis/dsp/src/DistanceFunctions/riscv_russellrao_distance.c @@ -0,0 +1,73 @@ + +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_russellrao_distance.c + * Description: Russell-Rao distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions.h" +#include +#include + + + +extern void riscv_boolean_distance_TT(const uint32_t *pA + , const uint32_t *pB + , uint32_t numberOfBools + , uint32_t *cTT + ); + + +/** + @addtogroup BoolDist + @{ + */ + +/** + * @brief Russell-Rao distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t riscv_russellrao_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools) +{ + uint32_t ctt=0; + + + riscv_boolean_distance_TT(pA, pB, numberOfBools, &ctt); + + + return(1.0*(numberOfBools - ctt) / ((float32_t)numberOfBools)); +} + + +/** + * @} end of BoolDist group + */ diff --git a/components/nmsis/dsp/src/DistanceFunctions/riscv_sokalmichener_distance.c b/components/nmsis/dsp/src/DistanceFunctions/riscv_sokalmichener_distance.c new file mode 100644 index 00000000..421fe341 --- /dev/null +++ b/components/nmsis/dsp/src/DistanceFunctions/riscv_sokalmichener_distance.c @@ -0,0 +1,77 @@ + +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_sokalmichener_distance.c + * Description: Sokal-Michener distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions.h" +#include +#include + + +extern void riscv_boolean_distance_TT_FF_TF_FT(const uint32_t *pA + , const uint32_t *pB + , uint32_t numberOfBools + , uint32_t *cTT + , uint32_t *cFF + , uint32_t *cTF + , uint32_t *cFT + ); + + +/** + @addtogroup BoolDist + @{ + */ + +/** + * @brief Sokal-Michener distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t riscv_sokalmichener_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools) +{ + uint32_t ctt=0,cff=0,cft=0,ctf=0; + float32_t r,s; + + riscv_boolean_distance_TT_FF_TF_FT(pA, pB, numberOfBools, &ctt, &cff, &ctf, &cft); + + r = 2.0*(ctf + cft); + s = 1.0*(cff + ctt); + + return(r / (s+r)); +} + + +/** + * @} end of BoolDist group + */ diff --git a/components/nmsis/dsp/src/DistanceFunctions/riscv_sokalsneath_distance.c b/components/nmsis/dsp/src/DistanceFunctions/riscv_sokalsneath_distance.c new file mode 100644 index 00000000..0d4171fe --- /dev/null +++ b/components/nmsis/dsp/src/DistanceFunctions/riscv_sokalsneath_distance.c @@ -0,0 +1,75 @@ + +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_sokalsneath_distance.c + * Description: Sokal-Sneath distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions.h" +#include +#include + + +extern void riscv_boolean_distance_TT_TF_FT(const uint32_t *pA + , const uint32_t *pB + , uint32_t numberOfBools + , uint32_t *cTT + , uint32_t *cTF + , uint32_t *cFT + ); + + +/** + @addtogroup BoolDist + @{ + */ + +/** + * @brief Sokal-Sneath distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t riscv_sokalsneath_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools) +{ + uint32_t ctt=0,cft=0,ctf=0; + float32_t r; + + riscv_boolean_distance_TT_TF_FT(pA, pB, numberOfBools, &ctt, &ctf, &cft); + + r = 2.0*(ctf + cft); + + return(r / (r + ctt)); +} + + +/** + * @} end of BoolDist group + */ diff --git a/components/nmsis/dsp/src/DistanceFunctions/riscv_yule_distance.c b/components/nmsis/dsp/src/DistanceFunctions/riscv_yule_distance.c new file mode 100644 index 00000000..d9aafdcd --- /dev/null +++ b/components/nmsis/dsp/src/DistanceFunctions/riscv_yule_distance.c @@ -0,0 +1,75 @@ + +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_yule_distance.c + * Description: Yule distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions.h" +#include +#include + + +extern void riscv_boolean_distance_TT_FF_TF_FT(const uint32_t *pA + , const uint32_t *pB + , uint32_t numberOfBools + , uint32_t *cTT + , uint32_t *cFF + , uint32_t *cTF + , uint32_t *cFT + ); + +/** + @addtogroup BoolDist + @{ + */ + + +/** + * @brief Yule distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t riscv_yule_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools) +{ + uint32_t ctt=0,cff=0,ctf=0,cft=0,r; + + riscv_boolean_distance_TT_FF_TF_FT(pA, pB, numberOfBools, &ctt,&cff, &ctf, &cft); + + r = 2*(ctf * cft); + + return(1.0*r / (r/2.0 + ctt * cff)); +} + + +/** + * @} end of BoolDist group + */ diff --git a/components/nmsis/dsp/src/FastMathFunctions/FastMathFunctions.c b/components/nmsis/dsp/src/FastMathFunctions/FastMathFunctions.c new file mode 100644 index 00000000..24bd5abd --- /dev/null +++ b/components/nmsis/dsp/src/FastMathFunctions/FastMathFunctions.c @@ -0,0 +1,63 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: FastMathFunctions.c + * Description: Combination of all fast math function source files. + * + * $Date: 16. March 2020 + * $Revision: V1.1.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2019-2020 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_FAST_ALLOW_TABLES) + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FAST_TABLES) || defined(RISCV_TABLE_SIN_F32) +#include "riscv_cos_f32.c" +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FAST_TABLES) || defined(RISCV_TABLE_SIN_Q15) +#include "riscv_cos_q15.c" +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FAST_TABLES) || defined(RISCV_TABLE_SIN_Q31) +#include "riscv_cos_q31.c" +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FAST_TABLES) || defined(RISCV_TABLE_SIN_F32) +#include "riscv_sin_f32.c" +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FAST_TABLES) || defined(RISCV_TABLE_SIN_Q15) +#include "riscv_sin_q15.c" +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FAST_TABLES) || defined(RISCV_TABLE_SIN_Q31) +#include "riscv_sin_q31.c" +#endif + +#endif + +#include "riscv_sqrt_q15.c" +#include "riscv_sqrt_q31.c" +#include "riscv_vexp_f32.c" +#include "riscv_vlog_f32.c" +#include "riscv_divide_q15.c" + diff --git a/components/nmsis/dsp/src/FastMathFunctions/FastMathFunctionsF16.c b/components/nmsis/dsp/src/FastMathFunctions/FastMathFunctionsF16.c new file mode 100644 index 00000000..33dd8819 --- /dev/null +++ b/components/nmsis/dsp/src/FastMathFunctions/FastMathFunctionsF16.c @@ -0,0 +1,32 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: FastMathFunctions.c + * Description: Combination of all fast math function source files. + * + * $Date: 16. March 2020 + * $Revision: V1.1.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2019-2020 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "riscv_vexp_f16.c" +#include "riscv_vlog_f16.c" +#include "riscv_vinverse_f16.c" diff --git a/components/nmsis/dsp/src/FastMathFunctions/riscv_cos_f32.c b/components/nmsis/dsp/src/FastMathFunctions/riscv_cos_f32.c new file mode 100644 index 00000000..77e7f030 --- /dev/null +++ b/components/nmsis/dsp/src/FastMathFunctions/riscv_cos_f32.c @@ -0,0 +1,122 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_cos_f32.c + * Description: Fast cosine calculation for floating-point values + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/fast_math_functions.h" +#include "riscv_common_tables.h" + +/** + @ingroup groupFastMath + */ + +/** + @defgroup cos Cosine + + Computes the trigonometric cosine function using a combination of table lookup + and linear interpolation. There are separate functions for + Q15, Q31, and floating-point data types. + The input to the floating-point version is in radians while the + fixed-point Q15 and Q31 have a scaled input with the range + [0 +0.9999] mapping to [0 2*pi). The fixed-point range is chosen so that a + value of 2*pi wraps around to 0. + + The implementation is based on table lookup using 512 values together with linear interpolation. + The steps used are: + -# Calculation of the nearest integer table index + -# Compute the fractional portion (fract) of the table index. + -# The final result equals (1.0f-fract)*a + fract*b; + + where + 
+     a = Table[index];
+     b = Table[index+1];
+
+ */ + +/** + @addtogroup cos + @{ + */ + +/** + @brief Fast approximation to the trigonometric cosine function for floating-point data. + @param[in] x input value in radians + @return cos(x) + */ +float32_t riscv_cos_f32( + float32_t x) +{ + float32_t cosVal, fract, in; /* Temporary input, output variables */ + uint16_t index; /* Index variable */ + float32_t a, b; /* Two nearest output values */ + int32_t n; + float32_t findex; + + /* input x is in radians */ + /* Scale input to [0 1] range from [0 2*PI] , divide input by 2*pi, add 0.25 (pi/2) to read sine table */ + in = x * 0.159154943092f + 0.25f; + + /* Calculation of floor value of input */ + n = (int32_t) in; + + /* Make negative values towards -infinity */ + if (in < 0.0f) + { + n--; + } + + /* Map input value to [0 1] */ + in = in - (float32_t) n; + + /* Calculation of index of the table */ + findex = (float32_t)FAST_MATH_TABLE_SIZE * in; + index = (uint16_t)findex; + + /* when "in" is exactly 1, we need to rotate the index down to 0 */ + if (index >= FAST_MATH_TABLE_SIZE) { + index = 0; + findex -= (float32_t)FAST_MATH_TABLE_SIZE; + } + + /* fractional value calculation */ + fract = findex - (float32_t) index; + + /* Read two nearest values of input value from the cos table */ + a = sinTable_f32[index]; + b = sinTable_f32[index+1]; + + /* Linear interpolation process */ + cosVal = (1.0f - fract) * a + fract * b; + + /* Return output value */ + return (cosVal); +} + +/** + @} end of cos group + */ diff --git a/components/nmsis/dsp/src/FastMathFunctions/riscv_cos_q15.c b/components/nmsis/dsp/src/FastMathFunctions/riscv_cos_q15.c new file mode 100644 index 00000000..31329d87 --- /dev/null +++ b/components/nmsis/dsp/src/FastMathFunctions/riscv_cos_q15.c @@ -0,0 +1,85 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_cos_q15.c + * Description: Fast cosine calculation for Q15 values + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/fast_math_functions.h" +#include "riscv_common_tables.h" + +/** + @ingroup groupFastMath + */ + +/** + @addtogroup cos + @{ + */ + +/** + @brief Fast approximation to the trigonometric cosine function for Q15 data. + @param[in] x Scaled input value in radians + @return cos(x) + + The Q15 input value is in the range [0 +0.9999] and is mapped to a radian value in the range [0 2*PI). + */ + +q15_t riscv_cos_q15( + q15_t x) +{ + q15_t cosVal; /* Temporary input, output variables */ + int32_t index; /* Index variable */ + q15_t a, b; /* Two nearest output values */ + q15_t fract; /* Temporary values for fractional values */ + + /* add 0.25 (pi/2) to read sine table */ + x = (uint16_t)x + 0x2000; + if (x < 0) + { /* convert negative numbers to corresponding positive ones */ + x = (uint16_t)x + 0x8000; + } + + /* Calculate the nearest index */ + index = (uint32_t)x >> FAST_MATH_Q15_SHIFT; + + /* Calculation of fractional value */ + fract = (x - (index << FAST_MATH_Q15_SHIFT)) << 9; + + /* Read two nearest values of input value from the sin table */ + a = sinTable_q15[index]; + b = sinTable_q15[index+1]; + + /* Linear interpolation process */ + cosVal = (q31_t) (0x8000 - fract) * a >> 16; + cosVal = (q15_t) ((((q31_t) cosVal << 16) + ((q31_t) fract * b)) >> 16); + + /* Return output value */ + return (cosVal << 1); +} + +/** + @} end of cos group + */ diff --git a/components/nmsis/dsp/src/FastMathFunctions/riscv_cos_q31.c b/components/nmsis/dsp/src/FastMathFunctions/riscv_cos_q31.c new file mode 100644 index 00000000..70fd38d1 --- /dev/null +++ b/components/nmsis/dsp/src/FastMathFunctions/riscv_cos_q31.c @@ -0,0 +1,85 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_cos_q31.c + * Description: Fast cosine calculation for Q31 values + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/fast_math_functions.h" +#include "riscv_common_tables.h" + +/** + @ingroup groupFastMath + */ + +/** + @addtogroup cos + @{ + */ + +/** + @brief Fast approximation to the trigonometric cosine function for Q31 data. + @param[in] x Scaled input value in radians + @return cos(x) + + The Q31 input value is in the range [0 +0.9999] and is mapped to a radian value in the range [0 2*PI). + */ + +q31_t riscv_cos_q31( + q31_t x) +{ + q31_t cosVal; /* Temporary input, output variables */ + int32_t index; /* Index variable */ + q31_t a, b; /* Two nearest output values */ + q31_t fract; /* Temporary values for fractional values */ + + /* add 0.25 (pi/2) to read sine table */ + x = (uint32_t)x + 0x20000000; + if (x < 0) + { /* convert negative numbers to corresponding positive ones */ + x = (uint32_t)x + 0x80000000; + } + + /* Calculate the nearest index */ + index = (uint32_t)x >> FAST_MATH_Q31_SHIFT; + + /* Calculation of fractional value */ + fract = (x - (index << FAST_MATH_Q31_SHIFT)) << 9; + + /* Read two nearest values of input value from the sin table */ + a = sinTable_q31[index]; + b = sinTable_q31[index+1]; + + /* Linear interpolation process */ + cosVal = (q63_t) (0x80000000 - fract) * a >> 32; + cosVal = (q31_t) ((((q63_t) cosVal << 32) + ((q63_t) fract * b)) >> 32); + + /* Return output value */ + return (cosVal << 1); +} + +/** + @} end of cos group + */ diff --git a/components/nmsis/dsp/src/FastMathFunctions/riscv_divide_q15.c b/components/nmsis/dsp/src/FastMathFunctions/riscv_divide_q15.c new file mode 100644 index 00000000..12bac273 --- /dev/null +++ b/components/nmsis/dsp/src/FastMathFunctions/riscv_divide_q15.c @@ -0,0 +1,111 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_cos_q15.c + * Description: Fast cosine calculation for Q15 values + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/fast_math_functions.h" +#include "riscv_common_tables.h" + +#include + +/** + @ingroup groupFastMath + */ + +/** + @defgroup divide Fixed point division + + */ + +/** + @addtogroup divide + @{ + */ + +/** + @brief Fixed point division + @param[in] numerator Numerator + @param[in] denominator Denominator + @param[out] quotient Quotient value normalized between -1.0 and 1.0 + @param[out] shift Shift left value to get the unnormalized quotient + @return error status + + When dividing by 0, an error RISCV_MATH_NANINF is returned. And the quotient is forced + to the saturated negative or positive value. + */ + +riscv_status riscv_divide_q15(q15_t numerator, + q15_t denominator, + q15_t *quotient, + int16_t *shift) +{ + int16_t sign=0; + q31_t temp; + int16_t shiftForNormalizing; + + *shift = 0; + + sign = (numerator>>15) ^ (denominator>>15); + + if (denominator == 0) + { + if (sign) + { + *quotient = 0x8000; + } + else + { + *quotient = 0x7FFF; + } + return(RISCV_MATH_NANINF); + } + + numerator = abs(numerator); + denominator = abs(denominator); + + temp = ((q31_t)numerator << 15) / ((q31_t)denominator); + + shiftForNormalizing= 17 - __CLZ(temp); + if (shiftForNormalizing > 0) + { + *shift = shiftForNormalizing; + temp = temp >> shiftForNormalizing; + } + + if (sign) + { + temp = -temp; + } + + *quotient=temp; + + return(RISCV_MATH_SUCCESS); +} + +/** + @} end of divide group + */ diff --git a/components/nmsis/dsp/src/FastMathFunctions/riscv_sin_f32.c b/components/nmsis/dsp/src/FastMathFunctions/riscv_sin_f32.c new file mode 100644 index 00000000..333c71bf --- /dev/null +++ b/components/nmsis/dsp/src/FastMathFunctions/riscv_sin_f32.c @@ -0,0 +1,123 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_sin_f32.c + * Description: Fast sine calculation for floating-point values + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/fast_math_functions.h" +#include "riscv_common_tables.h" + +/** + @ingroup groupFastMath + */ + +/** + @defgroup sin Sine + + Computes the trigonometric sine function using a combination of table lookup + and linear interpolation. There are separate functions for + Q15, Q31, and floating-point data types. + The input to the floating-point version is in radians while the + fixed-point Q15 and Q31 have a scaled input with the range + [0 +0.9999] mapping to [0 2*pi). The fixed-point range is chosen so that a + value of 2*pi wraps around to 0. + + The implementation is based on table lookup using 512 values together with linear interpolation. + The steps used are: + -# Calculation of the nearest integer table index + -# Compute the fractional portion (fract) of the table index. + -# The final result equals (1.0f-fract)*a + fract*b; + + where + 
+     b = Table[index];
+     c = Table[index+1];
+
+ */ + +/** + @addtogroup sin + @{ + */ + +/** + @brief Fast approximation to the trigonometric sine function for floating-point data. + @param[in] x input value in radians. + @return sin(x) + */ + +float32_t riscv_sin_f32( + float32_t x) +{ + float32_t sinVal, fract, in; /* Temporary input, output variables */ + uint16_t index; /* Index variable */ + float32_t a, b; /* Two nearest output values */ + int32_t n; + float32_t findex; + + /* input x is in radians */ + /* Scale input to [0 1] range from [0 2*PI] , divide input by 2*pi */ + in = x * 0.159154943092f; + + /* Calculation of floor value of input */ + n = (int32_t) in; + + /* Make negative values towards -infinity */ + if (in < 0.0f) + { + n--; + } + + /* Map input value to [0 1] */ + in = in - (float32_t) n; + + /* Calculation of index of the table */ + findex = (float32_t)FAST_MATH_TABLE_SIZE * in; + index = (uint16_t)findex; + + /* when "in" is exactly 1, we need to rotate the index down to 0 */ + if (index >= FAST_MATH_TABLE_SIZE) { + index = 0; + findex -= (float32_t)FAST_MATH_TABLE_SIZE; + } + + /* fractional value calculation */ + fract = findex - (float32_t) index; + + /* Read two nearest values of input value from the sin table */ + a = sinTable_f32[index]; + b = sinTable_f32[index+1]; + + /* Linear interpolation process */ + sinVal = (1.0f - fract) * a + fract * b; + + /* Return output value */ + return (sinVal); +} + +/** + @} end of sin group + */ diff --git a/components/nmsis/dsp/src/FastMathFunctions/riscv_sin_q15.c b/components/nmsis/dsp/src/FastMathFunctions/riscv_sin_q15.c new file mode 100644 index 00000000..60e7252c --- /dev/null +++ b/components/nmsis/dsp/src/FastMathFunctions/riscv_sin_q15.c @@ -0,0 +1,84 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_sin_q15.c + * Description: Fast sine calculation for Q15 values + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/fast_math_functions.h" +#include "riscv_common_tables.h" + +/** + @ingroup groupFastMath + */ + +/** + @addtogroup sin + @{ + */ + +/** + @brief Fast approximation to the trigonometric sine function for Q15 data. + @param[in] x Scaled input value in radians + @return sin(x) + + The Q15 input value is in the range [0 +0.9999] and is mapped to a radian value in the range [0 2*PI). + */ + +q15_t riscv_sin_q15( + q15_t x) +{ + q15_t sinVal; /* Temporary input, output variables */ + int32_t index; /* Index variable */ + q15_t a, b; /* Two nearest output values */ + q15_t fract; /* Temporary values for fractional values */ + + + if (x < 0) + { /* convert negative numbers to corresponding positive ones */ + x = (uint16_t)x + 0x8000; + } + + /* Calculate the nearest index */ + index = (uint32_t)x >> FAST_MATH_Q15_SHIFT; + + /* Calculation of fractional value */ + fract = (x - (index << FAST_MATH_Q15_SHIFT)) << 9; + + /* Read two nearest values of input value from the sin table */ + a = sinTable_q15[index]; + b = sinTable_q15[index+1]; + + /* Linear interpolation process */ + sinVal = (q31_t) (0x8000 - fract) * a >> 16; + sinVal = (q15_t) ((((q31_t) sinVal << 16) + ((q31_t) fract * b)) >> 16); + + /* Return output value */ + return (sinVal << 1); +} + +/** + @} end of sin group + */ diff --git a/components/nmsis/dsp/src/FastMathFunctions/riscv_sin_q31.c b/components/nmsis/dsp/src/FastMathFunctions/riscv_sin_q31.c new file mode 100644 index 00000000..b6717ee0 --- /dev/null +++ b/components/nmsis/dsp/src/FastMathFunctions/riscv_sin_q31.c @@ -0,0 +1,83 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_sin_q31.c + * Description: Fast sine calculation for Q31 values + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/fast_math_functions.h" +#include "riscv_common_tables.h" + +/** + @ingroup groupFastMath + */ + +/** + @addtogroup sin + @{ + */ + +/** + @brief Fast approximation to the trigonometric sine function for Q31 data. + @param[in] x Scaled input value in radians + @return sin(x) + + The Q31 input value is in the range [0 +0.9999] and is mapped to a radian value in the range [0 2*PI). + */ + +q31_t riscv_sin_q31( + q31_t x) +{ + q31_t sinVal; /* Temporary variables for input, output */ + int32_t index; /* Index variable */ + q31_t a, b; /* Two nearest output values */ + q31_t fract; /* Temporary values for fractional values */ + + if (x < 0) + { /* convert negative numbers to corresponding positive ones */ + x = (uint32_t)x + 0x80000000; + } + + /* Calculate the nearest index */ + index = (uint32_t)x >> FAST_MATH_Q31_SHIFT; + + /* Calculation of fractional value */ + fract = (x - (index << FAST_MATH_Q31_SHIFT)) << 9; + + /* Read two nearest values of input value from the sin table */ + a = sinTable_q31[index]; + b = sinTable_q31[index+1]; + + /* Linear interpolation process */ + sinVal = (q63_t) (0x80000000 - fract) * a >> 32; + sinVal = (q31_t) ((((q63_t) sinVal << 32) + ((q63_t) fract * b)) >> 32); + + /* Return output value */ + return (sinVal << 1); +} + +/** + @} end of sin group + */ diff --git a/components/nmsis/dsp/src/FastMathFunctions/riscv_sqrt_q15.c b/components/nmsis/dsp/src/FastMathFunctions/riscv_sqrt_q15.c new file mode 100644 index 00000000..93158818 --- /dev/null +++ b/components/nmsis/dsp/src/FastMathFunctions/riscv_sqrt_q15.c @@ -0,0 +1,149 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_sqrt_q15.c + * Description: Q15 square root function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/fast_math_functions.h" +#include "riscv_common_tables.h" + +/** + @ingroup groupFastMath + */ + +/** + @addtogroup SQRT + @{ + */ + +/** + @brief Q15 square root function. + @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF + @param[out] pOut points to square root of input value + @return execution status + - \ref RISCV_MATH_SUCCESS : input value is positive + - \ref RISCV_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0 + */ + +riscv_status riscv_sqrt_q15( + q15_t in, + q15_t * pOut) +{ + q31_t bits_val1; + q15_t number, temp1, var1, signBits1, half; + float32_t temp_float1; + union + { + q31_t fracval; + float32_t floatval; + } tempconv; + + number = in; + + /* If the input is a positive number then compute the signBits. */ + if (number > 0) + { +#if __RISCV_XLEN == 64 + signBits1 = __CLZ(number) - 0x2000000011; +#else + signBits1 = __CLZ(number) - 17; +#endif /* __RISCV_XLEN == 64 */ + + /* Shift by the number of signBits1 */ + if ((signBits1 % 2) == 0) + { + number = number << signBits1; + } + else + { + number = number << (signBits1 - 1); + } + + /* Calculate half value of the number */ + half = number >> 1; + /* Store the number for later use */ + temp1 = number; + + /* Convert to float */ + temp_float1 = number * 3.051757812500000e-005f; + /* Store as integer */ + tempconv.floatval = temp_float1; + bits_val1 = tempconv.fracval; + /* Subtract the shifted value from the magic number to give intial guess */ + bits_val1 = 0x5f3759df - (bits_val1 >> 1); /* gives initial guess */ + /* Store as float */ + tempconv.fracval = bits_val1; + temp_float1 = tempconv.floatval; + /* Convert to integer format */ + var1 = (q31_t) (temp_float1 * 16384); + + /* 1st iteration */ + var1 = ((q15_t) ((q31_t) var1 * (0x3000 - + ((q15_t) + ((((q15_t) + (((q31_t) var1 * var1) >> 15)) * + (q31_t) half) >> 15))) >> 15)) << 2; + /* 2nd iteration */ + var1 = ((q15_t) ((q31_t) var1 * (0x3000 - + ((q15_t) + ((((q15_t) + (((q31_t) var1 * var1) >> 15)) * + (q31_t) half) >> 15))) >> 15)) << 2; + /* 3rd iteration */ + var1 = ((q15_t) ((q31_t) var1 * (0x3000 - + ((q15_t) + ((((q15_t) + (((q31_t) var1 * var1) >> 15)) * + (q31_t) half) >> 15))) >> 15)) << 2; + + /* Multiply the inverse square root with the original value */ + var1 = ((q15_t) (((q31_t) temp1 * var1) >> 15)) << 1; + + /* Shift the output down accordingly */ + if ((signBits1 % 2) == 0) + { + var1 = var1 >> (signBits1 / 2); + } + else + { + var1 = var1 >> ((signBits1 - 1) / 2); + } + *pOut = var1; + + return (RISCV_MATH_SUCCESS); + } + /* If the number is a negative number then store zero as its square root value */ + else + { + *pOut = 0; + + return (RISCV_MATH_ARGUMENT_ERROR); + } +} + +/** + @} end of SQRT group + */ diff --git a/components/nmsis/dsp/src/FastMathFunctions/riscv_sqrt_q31.c b/components/nmsis/dsp/src/FastMathFunctions/riscv_sqrt_q31.c new file mode 100644 index 00000000..6297d133 --- /dev/null +++ b/components/nmsis/dsp/src/FastMathFunctions/riscv_sqrt_q31.c @@ -0,0 +1,145 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_sqrt_q31.c + * Description: Q31 square root function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/fast_math_functions.h" +#include "riscv_common_tables.h" + +/** + @ingroup groupFastMath + */ + +/** + @addtogroup SQRT + @{ + */ + +/** + @brief Q31 square root function. + @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF + @param[out] pOut points to square root of input value + @return execution status + - \ref RISCV_MATH_SUCCESS : input value is positive + - \ref RISCV_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0 + */ + +riscv_status riscv_sqrt_q31( + q31_t in, + q31_t * pOut) +{ + q31_t bits_val1; + q31_t number, temp1, var1, signBits1, half; + float32_t temp_float1; + union + { + q31_t fracval; + float32_t floatval; + } tempconv; + + number = in; + + /* If the input is a positive number then compute the signBits. */ + if (number > 0) + { + signBits1 = __CLZ(number) - 1; + + /* Shift by the number of signBits1 */ + if ((signBits1 % 2) == 0) + { + number = number << signBits1; + } + else + { + number = number << (signBits1 - 1); + } + + /* Calculate half value of the number */ + half = number >> 1; + /* Store the number for later use */ + temp1 = number; + + /* Convert to float */ + temp_float1 = number * 4.6566128731e-010f; + /* Store as integer */ + tempconv.floatval = temp_float1; + bits_val1 = tempconv.fracval; + /* Subtract the shifted value from the magic number to give intial guess */ + bits_val1 = 0x5f3759df - (bits_val1 >> 1); /* gives initial guess */ + /* Store as float */ + tempconv.fracval = bits_val1; + temp_float1 = tempconv.floatval; + /* Convert to integer format */ + var1 = (q31_t) (temp_float1 * 1073741824); + + /* 1st iteration */ + var1 = ((q31_t) ((q63_t) var1 * (0x30000000 - + ((q31_t) + ((((q31_t) + (((q63_t) var1 * var1) >> 31)) * + (q63_t) half) >> 31))) >> 31)) << 2; + /* 2nd iteration */ + var1 = ((q31_t) ((q63_t) var1 * (0x30000000 - + ((q31_t) + ((((q31_t) + (((q63_t) var1 * var1) >> 31)) * + (q63_t) half) >> 31))) >> 31)) << 2; + /* 3rd iteration */ + var1 = ((q31_t) ((q63_t) var1 * (0x30000000 - + ((q31_t) + ((((q31_t) + (((q63_t) var1 * var1) >> 31)) * + (q63_t) half) >> 31))) >> 31)) << 2; + + /* Multiply the inverse square root with the original value */ + var1 = ((q31_t) (((q63_t) temp1 * var1) >> 31)) << 1; + + /* Shift the output down accordingly */ + if ((signBits1 % 2) == 0) + { + var1 = var1 >> (signBits1 / 2); + } + else + { + var1 = var1 >> ((signBits1 - 1) / 2); + } + *pOut = var1; + + return (RISCV_MATH_SUCCESS); + } + /* If the number is a negative number then store zero as its square root value */ + else + { + *pOut = 0; + + return (RISCV_MATH_ARGUMENT_ERROR); + } +} + +/** + @} end of SQRT group + */ diff --git a/components/nmsis/dsp/src/FastMathFunctions/riscv_vexp_f16.c b/components/nmsis/dsp/src/FastMathFunctions/riscv_vexp_f16.c new file mode 100644 index 00000000..0d7c007c --- /dev/null +++ b/components/nmsis/dsp/src/FastMathFunctions/riscv_vexp_f16.c @@ -0,0 +1,61 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_vlog_f16.c + * Description: Fast vectorized log + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/fast_math_functions_f16.h" + +#if defined(RISCV_FLOAT16_SUPPORTED) + +#include "riscv_common_tables.h" + +#include "riscv_vec_math_f16.h" + + +void riscv_vexp_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; + + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* C = log(A) */ + + /* Calculate log and store result in destination buffer. */ + *pDst++ = expf(*pSrc++); + + /* Decrement loop counter */ + blkCnt--; + } +} + +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ + diff --git a/components/nmsis/dsp/src/FastMathFunctions/riscv_vexp_f32.c b/components/nmsis/dsp/src/FastMathFunctions/riscv_vexp_f32.c new file mode 100644 index 00000000..8df9b378 --- /dev/null +++ b/components/nmsis/dsp/src/FastMathFunctions/riscv_vexp_f32.c @@ -0,0 +1,53 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_vlog_f32.c + * Description: Fast vectorized log + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/fast_math_functions.h" +#include "riscv_common_tables.h" + + +void riscv_vexp_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; + + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* C = log(A) */ + + /* Calculate log and store result in destination buffer. */ + *pDst++ = expf(*pSrc++); + + /* Decrement loop counter */ + blkCnt--; + } +} diff --git a/components/nmsis/dsp/src/FastMathFunctions/riscv_vinverse_f16.c b/components/nmsis/dsp/src/FastMathFunctions/riscv_vinverse_f16.c new file mode 100644 index 00000000..433facd9 --- /dev/null +++ b/components/nmsis/dsp/src/FastMathFunctions/riscv_vinverse_f16.c @@ -0,0 +1,58 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_vinverse_f16.c + * Description: Fast vectorized inverse + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/fast_math_functions_f16.h" + +#if defined(RISCV_FLOAT16_SUPPORTED) + +#include "riscv_common_tables.h" + +#include "riscv_vec_math_f16.h" + +void riscv_vinverse_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; + + blkCnt = blockSize; + + while (blkCnt > 0U) + { + + *pDst++ = 1.0 / *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } +} + +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ + diff --git a/components/nmsis/dsp/src/FastMathFunctions/riscv_vlog_f16.c b/components/nmsis/dsp/src/FastMathFunctions/riscv_vlog_f16.c new file mode 100644 index 00000000..97bf96bd --- /dev/null +++ b/components/nmsis/dsp/src/FastMathFunctions/riscv_vlog_f16.c @@ -0,0 +1,59 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_vlog_f16.c + * Description: Fast vectorized log + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/fast_math_functions_f16.h" + +#if defined(RISCV_FLOAT16_SUPPORTED) + +#include "riscv_common_tables.h" +#include "riscv_vec_math_f16.h" + +void riscv_vlog_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; + + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* C = log(A) */ + + /* Calculate log and store result in destination buffer. */ + *pDst++ = logf(*pSrc++); + + /* Decrement loop counter */ + blkCnt--; + } +} + +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ + diff --git a/components/nmsis/dsp/src/FastMathFunctions/riscv_vlog_f32.c b/components/nmsis/dsp/src/FastMathFunctions/riscv_vlog_f32.c new file mode 100644 index 00000000..6bd9871a --- /dev/null +++ b/components/nmsis/dsp/src/FastMathFunctions/riscv_vlog_f32.c @@ -0,0 +1,53 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_vlog_f32.c + * Description: Fast vectorized log + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/fast_math_functions.h" +#include "riscv_common_tables.h" + + +void riscv_vlog_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; + + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* C = log(A) */ + + /* Calculate log and store result in destination buffer. */ + *pDst++ = logf(*pSrc++); + + /* Decrement loop counter */ + blkCnt--; + } +} diff --git a/components/nmsis/dsp/src/FilteringFunctions/FilteringFunctions.c b/components/nmsis/dsp/src/FilteringFunctions/FilteringFunctions.c new file mode 100644 index 00000000..eee7d555 --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/FilteringFunctions.c @@ -0,0 +1,137 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: FilteringFunctions.c + * Description: Combination of all filtering function source files. + * + * $Date: 18. March 2019 + * $Revision: V1.0.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2019 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "riscv_biquad_cascade_df1_32x64_init_q31.c" +#include "riscv_biquad_cascade_df1_32x64_q31.c" +#include "riscv_biquad_cascade_df1_f32.c" +#include "riscv_biquad_cascade_df1_fast_q15.c" +#include "riscv_biquad_cascade_df1_fast_q31.c" +#include "riscv_biquad_cascade_df1_init_f32.c" +#include "riscv_biquad_cascade_df1_init_q15.c" +#include "riscv_biquad_cascade_df1_init_q31.c" +#include "riscv_biquad_cascade_df1_q15.c" +#include "riscv_biquad_cascade_df1_q31.c" +#include "riscv_biquad_cascade_df2T_f32.c" +#include "riscv_biquad_cascade_df2T_f64.c" +#include "riscv_biquad_cascade_df2T_init_f32.c" +#include "riscv_biquad_cascade_df2T_init_f64.c" +#include "riscv_biquad_cascade_stereo_df2T_f32.c" +#include "riscv_biquad_cascade_stereo_df2T_init_f32.c" +#include "riscv_conv_f32.c" +#include "riscv_conv_fast_opt_q15.c" +#include "riscv_conv_fast_q15.c" +#include "riscv_conv_fast_q31.c" +#include "riscv_conv_opt_q15.c" +#include "riscv_conv_opt_q7.c" +#include "riscv_conv_partial_f32.c" +#include "riscv_conv_partial_fast_opt_q15.c" +#include "riscv_conv_partial_fast_q15.c" +#include "riscv_conv_partial_fast_q31.c" +#include "riscv_conv_partial_opt_q15.c" +#include "riscv_conv_partial_opt_q7.c" +#include "riscv_conv_partial_q15.c" +#include "riscv_conv_partial_q31.c" +#include "riscv_conv_partial_q7.c" +#include "riscv_conv_q15.c" +#include "riscv_conv_q31.c" +#include "riscv_conv_q7.c" +#include "riscv_correlate_f32.c" +#include "riscv_correlate_fast_opt_q15.c" +#include "riscv_correlate_fast_q15.c" +#include "riscv_correlate_fast_q31.c" +#include "riscv_correlate_opt_q15.c" +#include "riscv_correlate_opt_q7.c" +#include "riscv_correlate_q15.c" +#include "riscv_correlate_q31.c" +#include "riscv_correlate_q7.c" +#include "riscv_fir_decimate_f32.c" +#include "riscv_fir_decimate_fast_q15.c" +#include "riscv_fir_decimate_fast_q31.c" +#include "riscv_fir_decimate_init_f32.c" +#include "riscv_fir_decimate_init_q15.c" +#include "riscv_fir_decimate_init_q31.c" +#include "riscv_fir_decimate_q15.c" +#include "riscv_fir_decimate_q31.c" +#include "riscv_fir_f32.c" +#include "riscv_fir_fast_q15.c" +#include "riscv_fir_fast_q31.c" +#include "riscv_fir_init_f32.c" +#include "riscv_fir_init_q15.c" +#include "riscv_fir_init_q31.c" +#include "riscv_fir_init_q7.c" +#include "riscv_fir_interpolate_f32.c" +#include "riscv_fir_interpolate_init_f32.c" +#include "riscv_fir_interpolate_init_q15.c" +#include "riscv_fir_interpolate_init_q31.c" +#include "riscv_fir_interpolate_q15.c" +#include "riscv_fir_interpolate_q31.c" +#include "riscv_fir_lattice_f32.c" +#include "riscv_fir_lattice_init_f32.c" +#include "riscv_fir_lattice_init_q15.c" +#include "riscv_fir_lattice_init_q31.c" +#include "riscv_fir_lattice_q15.c" +#include "riscv_fir_lattice_q31.c" +#include "riscv_fir_q15.c" +#include "riscv_fir_q31.c" +#include "riscv_fir_q7.c" +#include "riscv_fir_sparse_f32.c" +#include "riscv_fir_sparse_init_f32.c" +#include "riscv_fir_sparse_init_q15.c" +#include "riscv_fir_sparse_init_q31.c" +#include "riscv_fir_sparse_init_q7.c" +#include "riscv_fir_sparse_q15.c" +#include "riscv_fir_sparse_q31.c" +#include "riscv_fir_sparse_q7.c" +#include "riscv_iir_lattice_f32.c" +#include "riscv_iir_lattice_init_f32.c" +#include "riscv_iir_lattice_init_q15.c" +#include "riscv_iir_lattice_init_q31.c" +#include "riscv_iir_lattice_q15.c" +#include "riscv_iir_lattice_q31.c" +#include "riscv_lms_f32.c" +#include "riscv_lms_init_f32.c" +#include "riscv_lms_init_q15.c" +#include "riscv_lms_init_q31.c" +#include "riscv_lms_norm_f32.c" +#include "riscv_lms_norm_init_f32.c" +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_FAST_ALLOW_TABLES) +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FAST_TABLES) || defined(RISCV_TABLE_RECIP_Q15) +#include "riscv_lms_norm_init_q15.c" +#endif +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FAST_TABLES) || defined(RISCV_TABLE_RECIP_Q31) +#include "riscv_lms_norm_init_q31.c" +#endif +#endif +#include "riscv_lms_norm_q15.c" +#include "riscv_lms_norm_q31.c" +#include "riscv_lms_q15.c" +#include "riscv_lms_q31.c" + +#include "riscv_levinson_durbin_f32.c" +#include "riscv_levinson_durbin_q31.c" diff --git a/components/nmsis/dsp/src/FilteringFunctions/FilteringFunctionsF16.c b/components/nmsis/dsp/src/FilteringFunctions/FilteringFunctionsF16.c new file mode 100644 index 00000000..ffe101f2 --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/FilteringFunctionsF16.c @@ -0,0 +1,37 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: FilteringFunctions.c + * Description: Combination of all filtering function f16 source files. + * + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2020 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "riscv_fir_f16.c" +#include "riscv_fir_init_f16.c" +#include "riscv_biquad_cascade_df1_f16.c" +#include "riscv_biquad_cascade_df1_init_f16.c" +#include "riscv_biquad_cascade_df2T_f16.c" +#include "riscv_biquad_cascade_df2T_init_f16.c" +#include "riscv_biquad_cascade_stereo_df2T_f16.c" +#include "riscv_biquad_cascade_stereo_df2T_init_f16.c" +#include "riscv_correlate_f16.c" +#include "riscv_levinson_durbin_f16.c" diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_biquad_cascade_df1_32x64_init_q31.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_biquad_cascade_df1_32x64_init_q31.c new file mode 100644 index 00000000..f0fddde2 --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_biquad_cascade_df1_32x64_init_q31.c @@ -0,0 +1,95 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_biquad_cascade_df1_32x64_init_q31.c + * Description: High precision Q31 Biquad cascade filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup BiquadCascadeDF1_32x64 + @{ + */ + +/** + @brief Initialization function for the Q31 Biquad cascade 32x64 filter. + @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure + @param[in] numStages number of 2nd order stages in the filter + @param[in] pCoeffs points to the filter coefficients + @param[in] pState points to the state buffer + @param[in] postShift Shift to be applied after the accumulator. Varies according to the coefficients format + @return none + + @par Coefficient and State Ordering + The coefficients are stored in the array pCoeffs in the following order: + 
+      {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+
+ where b1x and a1x are the coefficients for the first stage, + b2x and a2x are the coefficients for the second stage, + and so on. The pCoeffs array contains a total of 5*numStages values. + @par + The pState points to state variables array and size of each state variable is 1.63 format. + Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2]. + The state variables are arranged in the state array as: + 
+      {x[n-1], x[n-2], y[n-1], y[n-2]}
+
+ The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on. + The state array has a total length of 4*numStages values. + The state variables are updated after each block of data is processed; the coefficients are untouched. + */ + +void riscv_biquad_cas_df1_32x64_init_q31( + riscv_biquad_cas_df1_32x64_ins_q31 * S, + uint8_t numStages, + const q31_t * pCoeffs, + q63_t * pState, + uint8_t postShift) +{ + /* Assign filter stages */ + S->numStages = numStages; + + /* Assign postShift to be applied to the output */ + S->postShift = postShift; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always 4 * numStages */ + memset(pState, 0, (4U * (uint32_t) numStages) * sizeof(q63_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of BiquadCascadeDF1_32x64 group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_biquad_cascade_df1_32x64_q31.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_biquad_cascade_df1_32x64_q31.c new file mode 100644 index 00000000..b6c4cfb2 --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_biquad_cascade_df1_32x64_q31.c @@ -0,0 +1,459 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_biquad_cascade_df1_32x64_q31.c + * Description: High precision Q31 Biquad cascade filter processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @defgroup BiquadCascadeDF1_32x64 High Precision Q31 Biquad Cascade Filter + + This function implements a high precision Biquad cascade filter which operates on + Q31 data values. The filter coefficients are in 1.31 format and the state variables + are in 1.63 format. The double precision state variables reduce quantization noise + in the filter and provide a cleaner output. + These filters are particularly useful when implementing filters in which the + singularities are close to the unit circle. This is common for low pass or high + pass filters with very low cutoff frequencies. + + The function operates on blocks of input and output data + and each call to the function processes blockSize samples through + the filter. pSrc and pDst points to input and output arrays + containing blockSize Q31 values. + + @par Algorithm + Each Biquad stage implements a second order filter using the difference equation: + 
+      y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+
+ A Direct Form I algorithm is used with 5 coefficients and 4 state variables per stage. + \image html Biquad.png "Single Biquad filter stage" + Coefficients b0, b1 and b2 multiply the input signal x[n] and are referred to as the feedforward coefficients. + Coefficients a1 and a2 multiply the output signal y[n] and are referred to as the feedback coefficients. + Pay careful attention to the sign of the feedback coefficients. + Some design tools use the difference equation + 
+      y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] - a1 * y[n-1] - a2 * y[n-2]
+
+ In this case the feedback coefficients a1 and a2 must be negated when used with the NMSIS DSP Library. + @par + Higher order filters are realized as a cascade of second order sections. + numStages refers to the number of second order stages used. + For example, an 8th order filter would be realized with numStages=4 second order stages. + \image html BiquadCascade.png "8th order filter using a cascade of Biquad stages" + A 9th order filter would be realized with numStages=5 second order stages + with the coefficients for one of the stages configured as a first order filter + (b2=0 and a2=0). + @par + The pState points to state variables array. + Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2] and each state variable in 1.63 format to improve precision. + The state variables are arranged in the array as: + 
+      {x[n-1], x[n-2], y[n-1], y[n-2]}
+
+ @par + The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on. + The state array has a total length of 4*numStages values of data in 1.63 format. + The state variables are updated after each block of data is processed, the coefficients are untouched. + + @par Instance Structure + The coefficients and state variables for a filter are stored together in an instance data structure. + A separate instance structure must be defined for each filter. + Coefficient arrays may be shared among several instances while state variable arrays cannot be shared. + + @par Init Function + There is also an associated initialization function which performs the following operations: + - Sets the values of the internal structure fields. + - Zeros out the values in the state buffer. + To do this manually without calling the init function, assign the follow subfields of the instance structure: + numStages, pCoeffs, postShift, pState. Also set all of the values in pState to zero. + + @par + Use of the initialization function is optional. + However, if the initialization function is used, then the instance structure cannot be placed into a const data section. + To place an instance structure into a const data section, the instance structure must be manually initialized. + Set the values in the state buffer to zeros before static initialization. + For example, to statically initialize the filter instance structure use + 
+      riscv_biquad_cas_df1_32x64_ins_q31 S1 = {numStages, pState, pCoeffs, postShift};
+
+ where numStages is the number of Biquad stages in the filter; + pState is the address of the state buffer; + pCoeffs is the address of the coefficient buffer; + postShift shift to be applied which is described in detail below. + @par Fixed-Point Behavior + Care must be taken while using Biquad Cascade 32x64 filter function. + Following issues must be considered: + - Scaling of coefficients + - Filter gain + - Overflow and saturation + + @par + Filter coefficients are represented as fractional values and + restricted to lie in the range [-1 +1). + The processing function has an additional scaling parameter postShift + which allows the filter coefficients to exceed the range [+1 -1). + At the output of the filter's accumulator is a shift register which shifts the result by postShift bits. + \image html BiquadPostshift.png "Fixed-point Biquad with shift by postShift bits after accumulator" + This essentially scales the filter coefficients by 2^postShift. + For example, to realize the coefficients + 
+     {1.5, -0.8, 1.2, 1.6, -0.9}
+
+ set the Coefficient array to: + 
+     {0.75, -0.4, 0.6, 0.8, -0.45}
+
+ and set postShift=1 + @par + The second thing to keep in mind is the gain through the filter. + The frequency response of a Biquad filter is a function of its coefficients. + It is possible for the gain through the filter to exceed 1.0 meaning that the + filter increases the amplitude of certain frequencies. + This means that an input signal with amplitude < 1.0 may result in an output > 1.0 + and these are saturated or overflowed based on the implementation of the filter. + To avoid this behavior the filter needs to be scaled down such that its peak gain < 1.0 + or the input signal must be scaled down so that the combination of input and filter are never overflowed. + @par + The third item to consider is the overflow and saturation behavior of the fixed-point Q31 version. + This is described in the function specific documentation below. + */ + +/** + @addtogroup BiquadCascadeDF1_32x64 + @{ + */ + +/** + @brief Processing function for the Q31 Biquad cascade 32x64 filter. + @param[in] S points to an instance of the high precision Q31 Biquad cascade filter + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + + @par Details + The function is implemented using an internal 64-bit accumulator. + The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + Thus, if the accumulator result overflows it wraps around rather than clip. + In order to avoid overflows completely the input signal must be scaled down by 2 bits and lie in the range [-0.25 +0.25). + After all 5 multiply-accumulates are performed, the 2.62 accumulator is shifted by postShift bits and the result truncated to + 1.31 format by discarding the low 32 bits. + @par + Two related functions are provided in the NMSIS DSP library. + - \ref riscv_biquad_cascade_df1_q31() implements a Biquad cascade with 32-bit coefficients and state variables with a Q63 accumulator. + - \ref riscv_biquad_cascade_df1_fast_q31() implements a Biquad cascade with 32-bit coefficients and state variables with a Q31 accumulator. + */ + +void riscv_biquad_cas_df1_32x64_q31( + const riscv_biquad_cas_df1_32x64_ins_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + const q31_t *pIn = pSrc; /* input pointer initialization */ + q31_t *pOut = pDst; /* output pointer initialization */ + q63_t *pState = S->pState; /* state pointer initialization */ + const q31_t *pCoeffs = S->pCoeffs; /* coeff pointer initialization */ + q63_t acc; /* accumulator */ + q31_t Xn1, Xn2; /* Input Filter state variables */ + q63_t Yn1, Yn2; /* Output Filter state variables */ + q31_t b0, b1, b2, a1, a2; /* Filter coefficients */ + q31_t Xn; /* temporary input */ + int32_t shift = (int32_t) S->postShift + 1; /* Shift to be applied to the output */ + uint32_t sample, stage = S->numStages; /* loop counters */ + q31_t acc_l, acc_h; /* temporary output */ + uint32_t uShift = ((uint32_t) S->postShift + 1U); + uint32_t lShift = 32U - uShift; /* Shift to be applied to the output */ + + do + { + /* Reading the coefficients */ + b0 = *pCoeffs++; + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + /* Reading the state values */ + Xn1 = (q31_t) (pState[0]); + Xn2 = (q31_t) (pState[1]); + Yn1 = pState[2]; + Yn2 = pState[3]; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Apply loop unrolling and compute 4 output values simultaneously. */ + /* Variable acc hold output value that is being computed and stored in destination buffer + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + */ + + /* Loop unrolling: Compute 4 outputs at a time */ + sample = blockSize >> 2U; + + while (sample > 0U) + { + /* Read the input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + + /* acc = b0 * x[n] */ + acc = (q63_t) Xn * b0; + + /* acc += b1 * x[n-1] */ + acc += (q63_t) Xn1 * b1; + + /* acc += b[2] * x[n-2] */ + acc += (q63_t) Xn2 * b2; + + /* acc += a1 * y[n-1] */ + acc += mult32x64(Yn1, a1); + + /* acc += a2 * y[n-2] */ + acc += mult32x64(Yn2, a2); + + /* The result is converted to 1.63 , Yn2 variable is reused */ + Yn2 = acc << shift; + + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + /* Apply shift for lower part of acc and upper part of acc */ + acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift; + + /* Store the output in the destination buffer in 1.31 format. */ + *pOut = acc_h; + + /* Read the second input into Xn2, to reuse the value */ + Xn2 = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + + /* acc += b1 * x[n-1] */ + acc = (q63_t) Xn * b1; + + /* acc = b0 * x[n] */ + acc += (q63_t) Xn2 * b0; + + /* acc += b[2] * x[n-2] */ + acc += (q63_t) Xn1 * b2; + + /* acc += a1 * y[n-1] */ + acc += mult32x64(Yn2, a1); + + /* acc += a2 * y[n-2] */ + acc += mult32x64(Yn1, a2); + + /* The result is converted to 1.63, Yn1 variable is reused */ + Yn1 = acc << shift; + + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + /* Apply shift for lower part of acc and upper part of acc */ + acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift; + + /* Read the third input into Xn1, to reuse the value */ + Xn1 = *pIn++; + + /* The result is converted to 1.31 */ + /* Store the output in the destination buffer. */ + *(pOut + 1U) = acc_h; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + + /* acc = b0 * x[n] */ + acc = (q63_t) Xn1 * b0; + + /* acc += b1 * x[n-1] */ + acc += (q63_t) Xn2 * b1; + + /* acc += b[2] * x[n-2] */ + acc += (q63_t) Xn * b2; + + /* acc += a1 * y[n-1] */ + acc += mult32x64(Yn1, a1); + + /* acc += a2 * y[n-2] */ + acc += mult32x64(Yn2, a2); + + /* The result is converted to 1.63, Yn2 variable is reused */ + Yn2 = acc << shift; + + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + /* Apply shift for lower part of acc and upper part of acc */ + acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift; + + /* Store the output in the destination buffer in 1.31 format. */ + *(pOut + 2U) = acc_h; + + /* Read the fourth input into Xn, to reuse the value */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + /* acc = b0 * x[n] */ + acc = (q63_t) Xn * b0; + + /* acc += b1 * x[n-1] */ + acc += (q63_t) Xn1 * b1; + + /* acc += b[2] * x[n-2] */ + acc += (q63_t) Xn2 * b2; + + /* acc += a1 * y[n-1] */ + acc += mult32x64(Yn2, a1); + + /* acc += a2 * y[n-2] */ + acc += mult32x64(Yn1, a2); + + /* The result is converted to 1.63, Yn1 variable is reused */ + Yn1 = acc << shift; + + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + /* Apply shift for lower part of acc and upper part of acc */ + acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift; + + /* Store the output in the destination buffer in 1.31 format. */ + *(pOut + 3U) = acc_h; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + Xn2 = Xn1; + Xn1 = Xn; + + /* update output pointer */ + pOut += 4U; + + /* decrement loop counter */ + sample--; + } + + /* Loop unrolling: Compute remaining outputs */ + sample = blockSize & 0x3U; + +#else + + /* Initialize blkCnt with number of samples */ + sample = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (sample > 0U) + { + /* Read the input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + + /* acc = b0 * x[n] */ + acc = (q63_t) Xn * b0; + /* acc += b1 * x[n-1] */ + acc += (q63_t) Xn1 * b1; + /* acc += b[2] * x[n-2] */ + acc += (q63_t) Xn2 * b2; + /* acc += a1 * y[n-1] */ + acc += mult32x64(Yn1, a1); + /* acc += a2 * y[n-2] */ + acc += mult32x64(Yn2, a2); + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + Xn2 = Xn1; + Xn1 = Xn; + Yn2 = Yn1; + + /* The result is converted to 1.63, Yn1 variable is reused */ + Yn1 = acc << shift; + + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + /* Apply shift for lower part of acc and upper part of acc */ + acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift; + + /* Store the output in the destination buffer in 1.31 format. */ + *pOut++ = acc_h; + /* Yn1 = acc << shift; */ + + /* Store the output in the destination buffer in 1.31 format. */ +/* *pOut++ = (q31_t) (acc >> (32 - shift)); */ + + /* decrement loop counter */ + sample--; + } + + /* The first stage output is given as input to the second stage. */ + pIn = pDst; + + /* Reset to destination buffer working pointer */ + pOut = pDst; + + /* Store the updated state variables back into the pState array */ + *pState++ = (q63_t) Xn1; + *pState++ = (q63_t) Xn2; + *pState++ = Yn1; + *pState++ = Yn2; + + } while (--stage); + +} + +/** + @} end of BiquadCascadeDF1_32x64 group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_biquad_cascade_df1_f16.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_biquad_cascade_df1_f16.c new file mode 100644 index 00000000..3c6bd26e --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_biquad_cascade_df1_f16.c @@ -0,0 +1,228 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_biquad_cascade_df1_f16.c + * Description: Processing function for the floating-point Biquad cascade DirectFormI(DF1) filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions_f16.h" + +#if defined(RISCV_FLOAT16_SUPPORTED) +/** + @ingroup groupFilters + */ + + +/** + @addtogroup BiquadCascadeDF1 + @{ + */ + +/** + @brief Processing function for the floating-point Biquad cascade filter. + @param[in] S points to an instance of the floating-point Biquad cascade structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + */ +void riscv_biquad_cascade_df1_f16( + const riscv_biquad_casd_df1_inst_f16 * S, + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize) +{ + const float16_t *pIn = pSrc; /* Source pointer */ + float16_t *pOut = pDst; /* Destination pointer */ + float16_t *pState = S->pState; /* pState pointer */ + const float16_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + _Float16 acc; /* Accumulator */ + _Float16 b0, b1, b2, a1, a2; /* Filter coefficients */ + _Float16 Xn1, Xn2, Yn1, Yn2; /* Filter pState variables */ + _Float16 Xn; /* Temporary input */ + uint32_t sample, stage = S->numStages; /* Loop counters */ + + do + { + /* Reading the coefficients */ + b0 = *pCoeffs++; + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + /* Reading the pState values */ + Xn1 = pState[0]; + Xn2 = pState[1]; + Yn1 = pState[2]; + Yn2 = pState[3]; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Apply loop unrolling and compute 4 output values simultaneously. */ + /* Variable acc hold output values that are being computed: + * + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + */ + + /* Loop unrolling: Compute 4 outputs at a time */ + sample = blockSize >> 2U; + + while (sample > 0U) + { + /* Read the first input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + Yn2 = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn1) + (a2 * Yn2); + + /* Store output in destination buffer. */ + *pOut++ = Yn2; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + + /* Read the second input */ + Xn2 = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + Yn1 = (b0 * Xn2) + (b1 * Xn) + (b2 * Xn1) + (a1 * Yn2) + (a2 * Yn1); + + /* Store output in destination buffer. */ + *pOut++ = Yn1; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + + /* Read the third input */ + Xn1 = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + Yn2 = (b0 * Xn1) + (b1 * Xn2) + (b2 * Xn) + (a1 * Yn1) + (a2 * Yn2); + + /* Store output in destination buffer. */ + *pOut++ = Yn2; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + + /* Read the forth input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + Yn1 = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn2) + (a2 * Yn1); + + /* Store output in destination buffer. */ + *pOut++ = Yn1; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + Xn2 = Xn1; + Xn1 = Xn; + + /* decrement loop counter */ + sample--; + } + + /* Loop unrolling: Compute remaining outputs */ + sample = blockSize & 0x3U; + +#else + + /* Initialize blkCnt with number of samples */ + sample = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (sample > 0U) + { + /* Read the input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + acc = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn1) + (a2 * Yn2); + + /* Store output in destination buffer. */ + *pOut++ = acc; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + Xn2 = Xn1; + Xn1 = Xn; + Yn2 = Yn1; + Yn1 = acc; + + /* decrement loop counter */ + sample--; + } + + /* Store the updated state variables back into the pState array */ + *pState++ = Xn1; + *pState++ = Xn2; + *pState++ = Yn1; + *pState++ = Yn2; + + /* The first stage goes from the input buffer to the output buffer. */ + /* Subsequent numStages occur in-place in the output buffer */ + pIn = pDst; + + /* Reset output pointer */ + pOut = pDst; + + /* decrement loop counter */ + stage--; + + } while (stage > 0U); + +} + +/** + @} end of BiquadCascadeDF1 group + */ + +#endif /*#if defined(RISCV_FLOAT16_SUPPORTED)*/ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_biquad_cascade_df1_f32.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_biquad_cascade_df1_f32.c new file mode 100644 index 00000000..202142c8 --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_biquad_cascade_df1_f32.c @@ -0,0 +1,342 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_biquad_cascade_df1_f32.c + * Description: Processing function for the floating-point Biquad cascade DirectFormI(DF1) filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @defgroup BiquadCascadeDF1 Biquad Cascade IIR Filters Using Direct Form I Structure + + This set of functions implements arbitrary order recursive (IIR) filters. + The filters are implemented as a cascade of second order Biquad sections. + The functions support Q15, Q31 and floating-point data types. + Fast version of Q15 and Q31 also available. + + The functions operate on blocks of input and output data and each call to the function + processes blockSize samples through the filter. + pSrc points to the array of input data and + pDst points to the array of output data. + Both arrays contain blockSize values. + + @par Algorithm + Each Biquad stage implements a second order filter using the difference equation: + 
+      y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+
+ A Direct Form I algorithm is used with 5 coefficients and 4 state variables per stage. + \image html Biquad.png "Single Biquad filter stage" + Coefficients b0, b1 and b2 multiply the input signal x[n] and are referred to as the feedforward coefficients. + Coefficients a1 and a2 multiply the output signal y[n] and are referred to as the feedback coefficients. + Pay careful attention to the sign of the feedback coefficients. + Some design tools use the difference equation + 
+      y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] - a1 * y[n-1] - a2 * y[n-2]
+
+ In this case the feedback coefficients a1 and a2 + must be negated when used with the NMSIS DSP Library. + + @par + Higher order filters are realized as a cascade of second order sections. + numStages refers to the number of second order stages used. + For example, an 8th order filter would be realized with numStages=4 second order stages. + \image html BiquadCascade.png "8th order filter using a cascade of Biquad stages" + A 9th order filter would be realized with numStages=5 second order stages with the coefficients for one of the stages configured as a first order filter (b2=0 and a2=0). + + @par + The pState points to state variables array. + Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2]. + The state variables are arranged in the pState array as: + 
+      {x[n-1], x[n-2], y[n-1], y[n-2]}
+
+ + @par + The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on. + The state array has a total length of 4*numStages values. + The state variables are updated after each block of data is processed, the coefficients are untouched. + + @par Instance Structure + The coefficients and state variables for a filter are stored together in an instance data structure. + A separate instance structure must be defined for each filter. + Coefficient arrays may be shared among several instances while state variable arrays cannot be shared. + There are separate instance structure declarations for each of the 3 supported data types. + + @par Init Function + There is also an associated initialization function for each data type. + The initialization function performs following operations: + - Sets the values of the internal structure fields. + - Zeros out the values in the state buffer. + To do this manually without calling the init function, assign the follow subfields of the instance structure: + numStages, pCoeffs, pState. Also set all of the values in pState to zero. + + @par + Use of the initialization function is optional. + However, if the initialization function is used, then the instance structure cannot be placed into a const data section. + To place an instance structure into a const data section, the instance structure must be manually initialized. + Set the values in the state buffer to zeros before static initialization. + The code below statically initializes each of the 3 different data type filter instance structures + 
+      riscv_biquad_casd_df1_inst_f32 S1 = {numStages, pState, pCoeffs};
+      riscv_biquad_casd_df1_inst_q15 S2 = {numStages, pState, pCoeffs, postShift};
+      riscv_biquad_casd_df1_inst_q31 S3 = {numStages, pState, pCoeffs, postShift};
+
+ where numStages is the number of Biquad stages in the filter; + pState is the address of the state buffer; + pCoeffs is the address of the coefficient buffer; + postShift shift to be applied. + + @par Fixed-Point Behavior + Care must be taken when using the Q15 and Q31 versions of the Biquad Cascade filter functions. + Following issues must be considered: + - Scaling of coefficients + - Filter gain + - Overflow and saturation + + @par Scaling of coefficients + Filter coefficients are represented as fractional values and + coefficients are restricted to lie in the range [-1 +1). + The fixed-point functions have an additional scaling parameter postShift + which allow the filter coefficients to exceed the range [+1 -1). + At the output of the filter's accumulator is a shift register which shifts the result by postShift bits. + \image html BiquadPostshift.png "Fixed-point Biquad with shift by postShift bits after accumulator" + This essentially scales the filter coefficients by 2^postShift. + For example, to realize the coefficients + 
+     {1.5, -0.8, 1.2, 1.6, -0.9}
+
+ set the pCoeffs array to: + 
+     {0.75, -0.4, 0.6, 0.8, -0.45}
+
+ and set postShift=1 + + @par Filter gain + The frequency response of a Biquad filter is a function of its coefficients. + It is possible for the gain through the filter to exceed 1.0 meaning that the filter increases the amplitude of certain frequencies. + This means that an input signal with amplitude < 1.0 may result in an output > 1.0 and these are saturated or overflowed based on the implementation of the filter. + To avoid this behavior the filter needs to be scaled down such that its peak gain < 1.0 or the input signal must be scaled down so that the combination of input and filter are never overflowed. + + @par Overflow and saturation + For Q15 and Q31 versions, it is described separately as part of the function specific documentation below. + */ + +/** + @addtogroup BiquadCascadeDF1 + @{ + */ + +/** + @brief Processing function for the floating-point Biquad cascade filter. + @param[in] S points to an instance of the floating-point Biquad cascade structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + */ + +void riscv_biquad_cascade_df1_f32( + const riscv_biquad_casd_df1_inst_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + const float32_t *pIn = pSrc; /* Source pointer */ + float32_t *pOut = pDst; /* Destination pointer */ + float32_t *pState = S->pState; /* pState pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t acc; /* Accumulator */ + float32_t b0, b1, b2, a1, a2; /* Filter coefficients */ + float32_t Xn1, Xn2, Yn1, Yn2; /* Filter pState variables */ + float32_t Xn; /* Temporary input */ + uint32_t sample, stage = S->numStages; /* Loop counters */ + + do + { + /* Reading the coefficients */ + b0 = *pCoeffs++; + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + /* Reading the pState values */ + Xn1 = pState[0]; + Xn2 = pState[1]; + Yn1 = pState[2]; + Yn2 = pState[3]; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Apply loop unrolling and compute 4 output values simultaneously. */ + /* Variable acc hold output values that are being computed: + * + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + */ + + /* Loop unrolling: Compute 4 outputs at a time */ + sample = blockSize >> 2U; + + while (sample > 0U) + { + /* Read the first input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + Yn2 = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn1) + (a2 * Yn2); + + /* Store output in destination buffer. */ + *pOut++ = Yn2; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + + /* Read the second input */ + Xn2 = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + Yn1 = (b0 * Xn2) + (b1 * Xn) + (b2 * Xn1) + (a1 * Yn2) + (a2 * Yn1); + + /* Store output in destination buffer. */ + *pOut++ = Yn1; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + + /* Read the third input */ + Xn1 = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + Yn2 = (b0 * Xn1) + (b1 * Xn2) + (b2 * Xn) + (a1 * Yn1) + (a2 * Yn2); + + /* Store output in destination buffer. */ + *pOut++ = Yn2; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + + /* Read the forth input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + Yn1 = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn2) + (a2 * Yn1); + + /* Store output in destination buffer. */ + *pOut++ = Yn1; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + Xn2 = Xn1; + Xn1 = Xn; + + /* decrement loop counter */ + sample--; + } + + /* Loop unrolling: Compute remaining outputs */ + sample = blockSize & 0x3U; + +#else + + /* Initialize blkCnt with number of samples */ + sample = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (sample > 0U) + { + /* Read the input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + acc = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn1) + (a2 * Yn2); + + /* Store output in destination buffer. */ + *pOut++ = acc; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + Xn2 = Xn1; + Xn1 = Xn; + Yn2 = Yn1; + Yn1 = acc; + + /* decrement loop counter */ + sample--; + } + + /* Store the updated state variables back into the pState array */ + *pState++ = Xn1; + *pState++ = Xn2; + *pState++ = Yn1; + *pState++ = Yn2; + + /* The first stage goes from the input buffer to the output buffer. */ + /* Subsequent numStages occur in-place in the output buffer */ + pIn = pDst; + + /* Reset output pointer */ + pOut = pDst; + + /* decrement loop counter */ + stage--; + + } while (stage > 0U); + +} + + +/** + @} end of BiquadCascadeDF1 group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_biquad_cascade_df1_fast_q15.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_biquad_cascade_df1_fast_q15.c new file mode 100644 index 00000000..f29cbb51 --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_biquad_cascade_df1_fast_q15.c @@ -0,0 +1,228 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_biquad_cascade_df1_fast_q15.c + * Description: Fast processing function for the Q15 Biquad cascade filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup BiquadCascadeDF1 + @{ + */ + +/** + @brief Processing function for the Q15 Biquad cascade filter (fast variant). + @param[in] S points to an instance of the Q15 Biquad cascade structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process per call + @return none + + @par Scaling and Overflow Behavior + This fast version uses a 32-bit accumulator with 2.30 format. + The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit. + Thus, if the accumulator result overflows it wraps around and distorts the result. + In order to avoid overflows completely the input signal must be scaled down by two bits and lie in the range [-0.25 +0.25). + The 2.30 accumulator is then shifted by postShift bits and the result truncated to 1.15 format by discarding the low 16 bits. + @remark + Refer to \ref riscv_biquad_cascade_df1_q15() for a slower implementation of this function + which uses 64-bit accumulation to avoid wrap around distortion. Both the slow and the fast versions use the same instance structure. + Use the function \ref riscv_biquad_cascade_df1_init_q15() to initialize the filter structure. + */ + +void riscv_biquad_cascade_df1_fast_q15( + const riscv_biquad_casd_df1_inst_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + const q15_t *pIn = pSrc; /* Source pointer */ + q15_t *pOut = pDst; /* Destination pointer */ + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t acc; /* Accumulator */ + q31_t in; /* Temporary variable to hold input value */ + q31_t out; /* Temporary variable to hold output value */ + q31_t b0; /* Temporary variable to hold bo value */ + q31_t b1, a1; /* Filter coefficients */ + q31_t state_in, state_out; /* Filter state variables */ + int32_t shift = (int32_t) (15 - S->postShift); /* Post shift */ + uint32_t sample, stage = S->numStages; /* Loop counters */ + + do + { + /* Read the b0 and 0 coefficients using SIMD */ + b0 = read_q15x2_ia ((q15_t **) &pCoeffs); + + /* Read the b1 and b2 coefficients using SIMD */ + b1 = read_q15x2_ia ((q15_t **) &pCoeffs); + + /* Read the a1 and a2 coefficients using SIMD */ + a1 = read_q15x2_ia ((q15_t **) &pCoeffs); + + /* Read the input state values from the state buffer: x[n-1], x[n-2] */ + state_in = read_q15x2_ia (&pState); + + /* Read the output state values from the state buffer: y[n-1], y[n-2] */ + state_out = read_q15x2_da (&pState); + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Apply loop unrolling and compute 2 output values simultaneously. */ + /* Variable acc hold output values that are being computed: + * + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + */ + + /* Loop unrolling: Compute 2 outputs at a time */ + sample = blockSize >> 1U; + + while (sample > 0U) + { + + /* Read the input */ + in = read_q15x2_ia ((q15_t **) &pIn); + + /* out = b0 * x[n] + 0 * 0 */ + out = __SMUAD(b0, in); + /* acc = b1 * x[n-1] + acc += b2 * x[n-2] + out */ + acc = __SMLAD(b1, state_in, out); + /* acc += a1 * y[n-1] + acc += a2 * y[n-2] */ + acc = __SMLAD(a1, state_out, acc); + + /* The result is converted from 3.29 to 1.31 and then saturation is applied */ + out = __SSAT((acc >> shift), 16); + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */ + /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */ + + state_in = __PKHBT(in, state_in, 16); + state_out = __PKHBT(out, state_out, 16); + + /* out = b0 * x[n] + 0 * 0 */ + out = __SMUADX(b0, in); + /* acc0 = b1 * x[n-1] , acc0 += b2 * x[n-2] + out */ + acc = __SMLAD(b1, state_in, out); + /* acc += a1 * y[n-1] + acc += a2 * y[n-2] */ + acc = __SMLAD(a1, state_out, acc); + + /* The result is converted from 3.29 to 1.31 and then saturation is applied */ + out = __SSAT((acc >> shift), 16); + + /* Store the output in the destination buffer. */ + write_q15x2_ia (&pOut, __PKHBT(state_out, out, 16)); + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */ + /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */ + state_in = __PKHBT(in >> 16, state_in, 16); + state_out = __PKHBT(out, state_out, 16); + + /* Decrement loop counter */ + sample--; + } + + /* Loop unrolling: Compute remaining outputs */ + sample = (blockSize & 0x1U); + +#else + + /* Initialize blkCnt with number of samples */ + sample = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (sample > 0U) + { + /* Read the input */ + in = *pIn++; + + /* out = b0 * x[n] + 0 * 0 */ + out = __SMUAD(b0, in); + + /* acc = b1 * x[n-1], acc += b2 * x[n-2] + out */ + acc = __SMLAD(b1, state_in, out); + /* acc += a1 * y[n-1] + acc += a2 * y[n-2] */ + acc = __SMLAD(a1, state_out, acc); + + /* The result is converted from 3.29 to 1.31 and then saturation is applied */ + out = __SSAT((acc >> shift), 16); + + /* Store the output in the destination buffer. */ + *pOut++ = (q15_t) out; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */ + /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */ + state_in = __PKHBT(in, state_in, 16); + state_out = __PKHBT(out, state_out, 16); + + /* decrement loop counter */ + sample--; + } + + /* The first stage goes from the input buffer to the output buffer. */ + /* Subsequent (numStages - 1) occur in-place in the output buffer */ + pIn = pDst; + + /* Reset the output pointer */ + pOut = pDst; + + /* Store the updated state variables back into the state array */ + write_q15x2_ia(&pState, state_in); + write_q15x2_ia(&pState, state_out); + + /* Decrement loop counter */ + stage--; + + } while (stage > 0U); +} + +/** + @} end of BiquadCascadeDF1 group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_biquad_cascade_df1_fast_q31.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_biquad_cascade_df1_fast_q31.c new file mode 100644 index 00000000..12fe52bd --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_biquad_cascade_df1_fast_q31.c @@ -0,0 +1,297 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_biquad_cascade_df1_fast_q31.c + * Description: Processing function for the Q31 Fast Biquad cascade DirectFormI(DF1) filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup BiquadCascadeDF1 + @{ + */ + +/** + @brief Processing function for the Q31 Biquad cascade filter (fast variant). + @param[in] S points to an instance of the Q31 Biquad cascade structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process per call + @return none + + @par Scaling and Overflow Behavior + This function is optimized for speed at the expense of fixed-point precision and overflow protection. + The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format. + These intermediate results are added to a 2.30 accumulator. + Finally, the accumulator is saturated and converted to a 1.31 result. + The fast version has the same overflow behavior as the standard version and provides less precision since it discards the low 32 bits of each multiplication result. + In order to avoid overflows completely the input signal must be scaled down by two bits and lie in the range [-0.25 +0.25). Use the intialization function + riscv_biquad_cascade_df1_init_q31() to initialize filter structure. + @remark + Refer to \ref riscv_biquad_cascade_df1_q31() for a slower implementation of this function + which uses 64-bit accumulation to provide higher precision. Both the slow and the fast versions use the same instance structure. + Use the function \ref riscv_biquad_cascade_df1_init_q31() to initialize the filter structure. + */ + +void riscv_biquad_cascade_df1_fast_q31( + const riscv_biquad_casd_df1_inst_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + const q31_t *pIn = pSrc; /* Source pointer */ + q31_t *pOut = pDst; /* Destination pointer */ + q31_t *pState = S->pState; /* pState pointer */ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t acc = 0; /* Accumulator */ + q31_t b0, b1, b2, a1, a2; /* Filter coefficients */ + q31_t Xn1, Xn2, Yn1, Yn2; /* Filter pState variables */ + q31_t Xn; /* Temporary input */ + int32_t shift = (int32_t) S->postShift + 1; /* Shift to be applied to the output */ + uint32_t sample, stage = S->numStages; /* Loop counters */ + + do + { + /* Reading the coefficients */ + b0 = *pCoeffs++; + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + /* Reading the pState values */ + Xn1 = pState[0]; + Xn2 = pState[1]; + Yn1 = pState[2]; + Yn2 = pState[3]; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Apply loop unrolling and compute 4 output values simultaneously. */ + /* Variables acc ... acc3 hold output values that are being computed: + * + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + */ + + /* Loop unrolling: Compute 4 outputs at a time */ + sample = blockSize >> 2U; + + while (sample > 0U) + { + /* Read the input */ + Xn = *pIn; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + /* acc = b0 * x[n] */ + /* acc = (q31_t) (((q63_t) b1 * Xn1) >> 32);*/ + mult_32x32_keep32_R(acc, b1, Xn1); + /* acc += b1 * x[n-1] */ + /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b0 * (Xn))) >> 32);*/ + multAcc_32x32_keep32_R(acc, b0, Xn); + /* acc += b[2] * x[n-2] */ + /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn2))) >> 32);*/ + multAcc_32x32_keep32_R(acc, b2, Xn2); + /* acc += a1 * y[n-1] */ + /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn1))) >> 32);*/ + multAcc_32x32_keep32_R(acc, a1, Yn1); + /* acc += a2 * y[n-2] */ + /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn2))) >> 32);*/ + multAcc_32x32_keep32_R(acc, a2, Yn2); + + /* The result is converted to 1.31 , Yn2 variable is reused */ + Yn2 = acc << shift; + + /* Read the second input */ + Xn2 = *(pIn + 1U); + + /* Store the output in the destination buffer. */ + *pOut = Yn2; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + /* acc = b0 * x[n] */ + /* acc = (q31_t) (((q63_t) b0 * (Xn2)) >> 32);*/ + mult_32x32_keep32_R(acc, b0, Xn2); + /* acc += b1 * x[n-1] */ + /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn))) >> 32);*/ + multAcc_32x32_keep32_R(acc, b1, Xn); + /* acc += b[2] * x[n-2] */ + /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn1))) >> 32);*/ + multAcc_32x32_keep32_R(acc, b2, Xn1); + /* acc += a1 * y[n-1] */ + /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn2))) >> 32);*/ + multAcc_32x32_keep32_R(acc, a1, Yn2); + /* acc += a2 * y[n-2] */ + /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn1))) >> 32);*/ + multAcc_32x32_keep32_R(acc, a2, Yn1); + + /* The result is converted to 1.31, Yn1 variable is reused */ + Yn1 = acc << shift; + + /* Read the third input */ + Xn1 = *(pIn + 2U); + + /* Store the output in the destination buffer. */ + *(pOut + 1U) = Yn1; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + /* acc = b0 * x[n] */ + /* acc = (q31_t) (((q63_t) b0 * (Xn1)) >> 32);*/ + mult_32x32_keep32_R(acc, b0, Xn1); + /* acc += b1 * x[n-1] */ + /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn2))) >> 32);*/ + multAcc_32x32_keep32_R(acc, b1, Xn2); + /* acc += b[2] * x[n-2] */ + /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn))) >> 32);*/ + multAcc_32x32_keep32_R(acc, b2, Xn); + /* acc += a1 * y[n-1] */ + /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn1))) >> 32);*/ + multAcc_32x32_keep32_R(acc, a1, Yn1); + /* acc += a2 * y[n-2] */ + /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn2))) >> 32);*/ + multAcc_32x32_keep32_R(acc, a2, Yn2); + + /* The result is converted to 1.31, Yn2 variable is reused */ + Yn2 = acc << shift; + + /* Read the forth input */ + Xn = *(pIn + 3U); + + /* Store the output in the destination buffer. */ + *(pOut + 2U) = Yn2; + pIn += 4U; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + /* acc = b0 * x[n] */ + /* acc = (q31_t) (((q63_t) b0 * (Xn)) >> 32);*/ + mult_32x32_keep32_R(acc, b0, Xn); + /* acc += b1 * x[n-1] */ + /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn1))) >> 32);*/ + multAcc_32x32_keep32_R(acc, b1, Xn1); + /* acc += b[2] * x[n-2] */ + /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn2))) >> 32);*/ + multAcc_32x32_keep32_R(acc, b2, Xn2); + /* acc += a1 * y[n-1] */ + /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn2))) >> 32);*/ + multAcc_32x32_keep32_R(acc, a1, Yn2); + /* acc += a2 * y[n-2] */ + /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn1))) >> 32);*/ + multAcc_32x32_keep32_R(acc, a2, Yn1); + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + Xn2 = Xn1; + + /* The result is converted to 1.31, Yn1 variable is reused */ + Yn1 = acc << shift; + + /* Xn1 = Xn */ + Xn1 = Xn; + + /* Store the output in the destination buffer. */ + *(pOut + 3U) = Yn1; + pOut += 4U; + + /* decrement loop counter */ + sample--; + } + + /* Loop unrolling: Compute remaining outputs */ + sample = (blockSize & 0x3U); + +#else + + /* Initialize blkCnt with number of samples */ + sample = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (sample > 0U) + { + /* Read the input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + /* acc = b0 * x[n] */ + /* acc = (q31_t) (((q63_t) b0 * (Xn)) >> 32);*/ + mult_32x32_keep32_R(acc, b0, Xn); + /* acc += b1 * x[n-1] */ + /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn1))) >> 32);*/ + multAcc_32x32_keep32_R(acc, b1, Xn1); + /* acc += b[2] * x[n-2] */ + /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn2))) >> 32);*/ + multAcc_32x32_keep32_R(acc, b2, Xn2); + /* acc += a1 * y[n-1] */ + /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn1))) >> 32);*/ + multAcc_32x32_keep32_R(acc, a1, Yn1); + /* acc += a2 * y[n-2] */ + /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn2))) >> 32);*/ + multAcc_32x32_keep32_R(acc, a2, Yn2); + + /* The result is converted to 1.31 */ + acc = acc << shift; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + Xn2 = Xn1; + Xn1 = Xn; + Yn2 = Yn1; + Yn1 = acc; + + /* Store the output in the destination buffer. */ + *pOut++ = acc; + + /* decrement loop counter */ + sample--; + } + + /* The first stage goes from the input buffer to the output buffer. */ + /* Subsequent stages occur in-place in the output buffer */ + pIn = pDst; + + /* Reset to destination pointer */ + pOut = pDst; + + /* Store the updated state variables back into the pState array */ + *pState++ = Xn1; + *pState++ = Xn2; + *pState++ = Yn1; + *pState++ = Yn2; + + } while (--stage); +} + +/** + @} end of BiquadCascadeDF1 group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_biquad_cascade_df1_init_f16.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_biquad_cascade_df1_init_f16.c new file mode 100644 index 00000000..8ec52920 --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_biquad_cascade_df1_init_f16.c @@ -0,0 +1,102 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_biquad_cascade_df1_init_f16.c + * Description: Floating-point Biquad cascade DirectFormI(DF1) filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions_f16.h" + +#if defined(RISCV_FLOAT16_SUPPORTED) +/** + @ingroup groupFilters + */ + +/** + @addtogroup BiquadCascadeDF1 + @{ + */ + +/** + @brief Initialization function for the floating-point Biquad cascade filter. + @param[in,out] S points to an instance of the floating-point Biquad cascade structure. + @param[in] numStages number of 2nd order stages in the filter. + @param[in] pCoeffs points to the filter coefficients. + @param[in] pState points to the state buffer. + @return none + + @par Coefficient and State Ordering + The coefficients are stored in the array pCoeffs in the following order: + 
+      {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+
+ + @par + where b1x and a1x are the coefficients for the first stage, + b2x and a2x are the coefficients for the second stage, + and so on. The pCoeffs array contains a total of 5*numStages values. + @par + The pState is a pointer to state array. + Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2]. + The state variables are arranged in the pState array as: + 
+      {x[n-1], x[n-2], y[n-1], y[n-2]}
+
+ The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on. + The state array has a total length of 4*numStages values. + The state variables are updated after each block of data is processed; the coefficients are untouched. + + @par For MVE code, an additional buffer of modified coefficients is required. + Its size is numStages and each element of this buffer has type riscv_biquad_mod_coef_f16. + So, its total size is 96*numStages float16_t elements. + + The initialization function which must be used is riscv_biquad_cascade_df1_mve_init_f16. + */ + + +void riscv_biquad_cascade_df1_init_f16( + riscv_biquad_casd_df1_inst_f16 * S, + uint8_t numStages, + const float16_t * pCoeffs, + float16_t * pState) +{ + /* Assign filter stages */ + S->numStages = numStages; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always 4 * numStages */ + memset(pState, 0, (4U * (uint32_t) numStages) * sizeof(float16_t)); + + /* Assign state pointer */ + S->pState = pState; +} + + +/** + @} end of BiquadCascadeDF1 group + */ +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_biquad_cascade_df1_init_f32.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_biquad_cascade_df1_init_f32.c new file mode 100644 index 00000000..cadd7e56 --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_biquad_cascade_df1_init_f32.c @@ -0,0 +1,101 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_biquad_cascade_df1_init_f32.c + * Description: Floating-point Biquad cascade DirectFormI(DF1) filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup BiquadCascadeDF1 + @{ + */ + +/** + @brief Initialization function for the floating-point Biquad cascade filter. + @param[in,out] S points to an instance of the floating-point Biquad cascade structure. + @param[in] numStages number of 2nd order stages in the filter. + @param[in] pCoeffs points to the filter coefficients. + @param[in] pState points to the state buffer. + @return none + + @par Coefficient and State Ordering + The coefficients are stored in the array pCoeffs in the following order: + 
+      {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+
+ + @par + where b1x and a1x are the coefficients for the first stage, + b2x and a2x are the coefficients for the second stage, + and so on. The pCoeffs array contains a total of 5*numStages values. + @par + The pState is a pointer to state array. + Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2]. + The state variables are arranged in the pState array as: + 
+      {x[n-1], x[n-2], y[n-1], y[n-2]}
+
+ The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on. + The state array has a total length of 4*numStages values. + The state variables are updated after each block of data is processed; the coefficients are untouched. + + @par For MVE code, an additional buffer of modified coefficients is required. + Its size is numStages and each element of this buffer has type riscv_biquad_mod_coef_f32. + So, its total size is 32*numStages float32_t elements. + + The initialization function which must be used is riscv_biquad_cascade_df1_mve_init_f32. + */ + + +void riscv_biquad_cascade_df1_init_f32( + riscv_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + const float32_t * pCoeffs, + float32_t * pState) +{ + /* Assign filter stages */ + S->numStages = numStages; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always 4 * numStages */ + memset(pState, 0, (4U * (uint32_t) numStages) * sizeof(float32_t)); + + /* Assign state pointer */ + S->pState = pState; +} + + + +/** + @} end of BiquadCascadeDF1 group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_biquad_cascade_df1_init_q15.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_biquad_cascade_df1_init_q15.c new file mode 100644 index 00000000..da9e0f5a --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_biquad_cascade_df1_init_q15.c @@ -0,0 +1,97 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_biquad_cascade_df1_init_q15.c + * Description: Q15 Biquad cascade DirectFormI(DF1) filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup BiquadCascadeDF1 + @{ + */ + +/** + @brief Initialization function for the Q15 Biquad cascade filter. + @param[in,out] S points to an instance of the Q15 Biquad cascade structure. + @param[in] numStages number of 2nd order stages in the filter. + @param[in] pCoeffs points to the filter coefficients. + @param[in] pState points to the state buffer. + @param[in] postShift Shift to be applied to the accumulator result. Varies according to the coefficients format + @return none + + @par Coefficient and State Ordering + The coefficients are stored in the array pCoeffs in the following order: + 
+      {b10, 0, b11, b12, a11, a12, b20, 0, b21, b22, a21, a22, ...}
+
+ @par + where b1x and a1x are the coefficients for the first stage, + b2x and a2x are the coefficients for the second stage, + and so on. The pCoeffs array contains a total of 6*numStages values. + The zero coefficient between b1 and b2 facilities use of 16-bit SIMD instructions on the RISC-V Core with DSP. + @par + The state variables are stored in the array pState. + Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2]. + The state variables are arranged in the pState array as: + 
+      {x[n-1], x[n-2], y[n-1], y[n-2]}
+
+ The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on. + The state array has a total length of 4*numStages values. + The state variables are updated after each block of data is processed; the coefficients are untouched. + */ + +void riscv_biquad_cascade_df1_init_q15( + riscv_biquad_casd_df1_inst_q15 * S, + uint8_t numStages, + const q15_t * pCoeffs, + q15_t * pState, + int8_t postShift) +{ + /* Assign filter stages */ + S->numStages = numStages; + + /* Assign postShift to be applied to the output */ + S->postShift = postShift; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always 4 * numStages */ + memset(pState, 0, (4U * (uint32_t) numStages) * sizeof(q15_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of BiquadCascadeDF1 group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_biquad_cascade_df1_init_q31.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_biquad_cascade_df1_init_q31.c new file mode 100644 index 00000000..d3c4f176 --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_biquad_cascade_df1_init_q31.c @@ -0,0 +1,96 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_biquad_cascade_df1_init_q31.c + * Description: Q31 Biquad cascade DirectFormI(DF1) filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup BiquadCascadeDF1 + @{ + */ + +/** + @brief Initialization function for the Q31 Biquad cascade filter. + @param[in,out] S points to an instance of the Q31 Biquad cascade structure. + @param[in] numStages number of 2nd order stages in the filter. + @param[in] pCoeffs points to the filter coefficients. + @param[in] pState points to the state buffer. + @param[in] postShift Shift to be applied after the accumulator. Varies according to the coefficients format + @return none + + @par Coefficient and State Ordering + The coefficients are stored in the array pCoeffs in the following order: + 
+      {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+
+ @par + where b1x and a1x are the coefficients for the first stage, + b2x and a2x are the coefficients for the second stage, + and so on. The pCoeffs array contains a total of 5*numStages values. + @par + The pState points to state variables array. + Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2]. + The state variables are arranged in the pState array as: + 
+      {x[n-1], x[n-2], y[n-1], y[n-2]}
+
+ The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on. + The state array has a total length of 4*numStages values. + The state variables are updated after each block of data is processed; the coefficients are untouched. + */ + +void riscv_biquad_cascade_df1_init_q31( + riscv_biquad_casd_df1_inst_q31 * S, + uint8_t numStages, + const q31_t * pCoeffs, + q31_t * pState, + int8_t postShift) +{ + /* Assign filter stages */ + S->numStages = numStages; + + /* Assign postShift to be applied to the output */ + S->postShift = postShift; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always 4 * numStages */ + memset(pState, 0, (4U * (uint32_t) numStages) * sizeof(q31_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of BiquadCascadeDF1 group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_biquad_cascade_df1_q15.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_biquad_cascade_df1_q15.c new file mode 100644 index 00000000..2b32efb5 --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_biquad_cascade_df1_q15.c @@ -0,0 +1,341 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_biquad_cascade_df1_q15.c + * Description: Processing function for the Q15 Biquad cascade DirectFormI(DF1) filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup BiquadCascadeDF1 + @{ + */ + +/** + @brief Processing function for the Q15 Biquad cascade filter. + @param[in] S points to an instance of the Q15 Biquad cascade structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the location where the output result is written + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + The accumulator is then shifted by postShift bits to truncate the result to 1.15 format by discarding the low 16 bits. + Finally, the result is saturated to 1.15 format. + @remark + Refer to \ref riscv_biquad_cascade_df1_fast_q15() for a faster but less precise implementation of this filter. + */ + +void riscv_biquad_cascade_df1_q15( + const riscv_biquad_casd_df1_inst_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + + +#if defined (RISCV_MATH_DSP) + + const q15_t *pIn = pSrc; /* Source pointer */ + q15_t *pOut = pDst; /* Destination pointer */ + q31_t in; /* Temporary variable to hold input value */ + q31_t out; /* Temporary variable to hold output value */ + q31_t b0; /* Temporary variable to hold bo value */ + q31_t b1, a1; /* Filter coefficients */ + q31_t state_in, state_out; /* Filter state variables */ + q31_t acc_l, acc_h; + q63_t acc; /* Accumulator */ + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + int32_t lShift = (15 - (int32_t) S->postShift); /* Post shift */ + uint32_t sample, stage = (uint32_t) S->numStages; /* Stage loop counter */ + int32_t uShift = (32 - lShift); + + do + { + /* Read the b0 and 0 coefficients using SIMD */ + b0 = read_q15x2_ia ((q15_t **) &pCoeffs); + + /* Read the b1 and b2 coefficients using SIMD */ + b1 = read_q15x2_ia ((q15_t **) &pCoeffs); + + /* Read the a1 and a2 coefficients using SIMD */ + a1 = read_q15x2_ia ((q15_t **) &pCoeffs); + + /* Read the input state values from the state buffer: x[n-1], x[n-2] */ + state_in = read_q15x2_ia (&pState); + + /* Read the output state values from the state buffer: y[n-1], y[n-2] */ + state_out = read_q15x2_da (&pState); + + /* Apply loop unrolling and compute 2 output values simultaneously. */ + /* The variable acc hold output values that are being computed: + * + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + */ + sample = blockSize >> 1U; + + /* First part of the processing with loop unrolling. Compute 2 outputs at a time. + ** a second loop below computes the remaining 1 sample. */ + while (sample > 0U) + { + + /* Read the input */ + in = read_q15x2_ia ((q15_t **) &pIn); + + /* out = b0 * x[n] + 0 * 0 */ + out = __RV_KMDA(b0, in); + + /* acc += b1 * x[n-1] + b2 * x[n-2] + out */ + acc = __RV_SMALDA(out, b1, state_in); + /* acc += a1 * y[n-1] + a2 * y[n-2] */ + acc = __RV_SMALDA(acc, a1, state_out); + + /* The result is converted from 3.29 to 1.31 if postShift = 1, and then saturation is applied */ + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + /* Apply shift for lower part of acc and upper part of acc */ + out = (uint32_t) acc_l >> lShift | acc_h << uShift; + + out = __SSAT(out, 16); + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */ + /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */ + + state_in = __PKHBT(in, state_in, 16); + state_out = __PKHBT(out, state_out, 16); + + /* out = b0 * x[n] + 0 * 0 */ + out = __RV_KMXDA(b0, in); + /* acc += b1 * x[n-1] + b2 * x[n-2] + out */ + acc = __RV_SMALDA(out, b1, state_in); + /* acc += a1 * y[n-1] + a2 * y[n-2] */ + acc = __RV_SMALDA(acc, a1, state_out); + + /* The result is converted from 3.29 to 1.31 if postShift = 1, and then saturation is applied */ + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + /* Apply shift for lower part of acc and upper part of acc */ + out = (uint32_t) acc_l >> lShift | acc_h << uShift; + + out = __SSAT(out, 16); + + /* Store the output in the destination buffer. */ + write_q15x2_ia (&pOut, __PKHBT(state_out, out, 16)); + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */ + /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */ + state_in = __PKHBT(in >> 16, state_in, 16); + state_out = __PKHBT(out, state_out, 16); + + /* Decrement loop counter */ + sample--; + } + + /* If the blockSize is not a multiple of 2, compute any remaining output samples here. + ** No loop unrolling is used. */ + + if ((blockSize & 0x1U) != 0U) + { + /* Read the input */ + in = *pIn++; + + /* out = b0 * x[n] + 0 * 0 */ + out = __RV_KMDA(b0, in); + + /* acc = b1 * x[n-1] + b2 * x[n-2] + out */ + acc = __RV_SMALDA(out, b1, state_in); + /* acc += a1 * y[n-1] + a2 * y[n-2] */ + acc = __RV_SMALDA(acc, a1, state_out); + + /* The result is converted from 3.29 to 1.31 if postShift = 1, and then saturation is applied */ + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + /* Apply shift for lower part of acc and upper part of acc */ + out = (uint32_t) acc_l >> lShift | acc_h << uShift; + + out = __SSAT(out, 16); + + /* Store the output in the destination buffer. */ + *pOut++ = (q15_t) out; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */ + /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */ + state_in = __PKHBT(in, state_in, 16); + state_out = __PKHBT(out, state_out, 16); + } + + /* The first stage goes from the input wire to the output wire. */ + /* Subsequent numStages occur in-place in the output wire */ + pIn = pDst; + + /* Reset the output pointer */ + pOut = pDst; + + /* Store the updated state variables back into the state array */ + write_q15x2_ia (&pState, state_in); + write_q15x2_ia (&pState, state_out); + + /* Decrement loop counter */ + stage--; + + } while (stage > 0U); + +#else + + const q15_t *pIn = pSrc; /* Source pointer */ + q15_t *pOut = pDst; /* Destination pointer */ + q15_t b0, b1, b2, a1, a2; /* Filter coefficients */ + q15_t Xn1, Xn2, Yn1, Yn2; /* Filter state variables */ + q15_t Xn; /* temporary input */ + q63_t acc; /* Accumulator */ + int32_t shift = (15 - (int32_t) S->postShift); /* Post shift */ + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + uint32_t sample, stage = (uint32_t) S->numStages; /* Stage loop counter */ + + do + { + /* Reading the coefficients */ + b0 = *pCoeffs++; + pCoeffs++; // skip the 0 coefficient + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + /* Reading the state values */ + Xn1 = pState[0]; + Xn2 = pState[1]; + Yn1 = pState[2]; + Yn2 = pState[3]; + + /* The variables acc holds the output value that is computed: + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + */ + + sample = blockSize; + + while (sample > 0U) + { + /* Read the input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + /* acc = b0 * x[n] */ + acc = (q31_t) b0 *Xn; + + /* acc += b1 * x[n-1] */ + acc += (q31_t) b1 *Xn1; + /* acc += b[2] * x[n-2] */ + acc += (q31_t) b2 *Xn2; + /* acc += a1 * y[n-1] */ + acc += (q31_t) a1 *Yn1; + /* acc += a2 * y[n-2] */ + acc += (q31_t) a2 *Yn2; + + /* The result is converted to 1.31 */ + acc = __SSAT((acc >> shift), 16); + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + Xn2 = Xn1; + Xn1 = Xn; + Yn2 = Yn1; + Yn1 = (q15_t) acc; + + /* Store the output in the destination buffer. */ + *pOut++ = (q15_t) acc; + + /* decrement the loop counter */ + sample--; + } + + /* The first stage goes from the input buffer to the output buffer. */ + /* Subsequent stages occur in-place in the output buffer */ + pIn = pDst; + + /* Reset to destination pointer */ + pOut = pDst; + + /* Store the updated state variables back into the pState array */ + *pState++ = Xn1; + *pState++ = Xn2; + *pState++ = Yn1; + *pState++ = Yn2; + + } while (--stage); + +#endif /* #if defined (RISCV_MATH_DSP) */ + +} + +/** + @} end of BiquadCascadeDF1 group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_biquad_cascade_df1_q31.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_biquad_cascade_df1_q31.c new file mode 100644 index 00000000..f6a2cee4 --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_biquad_cascade_df1_q31.c @@ -0,0 +1,247 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_biquad_cascade_df1_q31.c + * Description: Processing function for the Q31 Biquad cascade filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup BiquadCascadeDF1 + @{ + */ + +/** + @brief Processing function for the Q31 Biquad cascade filter. + @param[in] S points to an instance of the Q31 Biquad cascade structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + Thus, if the accumulator result overflows it wraps around rather than clip. + In order to avoid overflows completely the input signal must be scaled down by 2 bits and lie in the range [-0.25 +0.25). + After all 5 multiply-accumulates are performed, the 2.62 accumulator is shifted by postShift bits and the result truncated to + 1.31 format by discarding the low 32 bits. + @remark + Refer to \ref riscv_biquad_cascade_df1_fast_q31() for a faster but less precise implementation of this filter. + */ +void riscv_biquad_cascade_df1_q31( + const riscv_biquad_casd_df1_inst_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + const q31_t *pIn = pSrc; /* Source pointer */ + q31_t *pOut = pDst; /* Destination pointer */ + q31_t *pState = S->pState; /* pState pointer */ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q63_t acc; /* Accumulator */ + q31_t b0, b1, b2, a1, a2; /* Filter coefficients */ + q31_t Xn1, Xn2, Yn1, Yn2; /* Filter pState variables */ + q31_t Xn; /* Temporary input */ + uint32_t uShift = ((uint32_t) S->postShift + 1U); + uint32_t lShift = 32U - uShift; /* Shift to be applied to the output */ + uint32_t sample, stage = S->numStages; /* Loop counters */ + +#if defined (RISCV_MATH_LOOPUNROLL) + q31_t acc_l, acc_h; /* temporary output variables */ +#endif + + do + { + /* Reading the coefficients */ + b0 = *pCoeffs++; + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + /* Reading the pState values */ + Xn1 = pState[0]; + Xn2 = pState[1]; + Yn1 = pState[2]; + Yn2 = pState[3]; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Apply loop unrolling and compute 4 output values simultaneously. */ + /* Variable acc hold output values that are being computed: + * + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + */ + + /* Loop unrolling: Compute 4 outputs at a time */ + sample = blockSize >> 2U; + + while (sample > 0U) + { + /* Read the first input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + acc = ((q63_t) b0 * Xn) + ((q63_t) b1 * Xn1) + ((q63_t) b2 * Xn2) + ((q63_t) a1 * Yn1) + ((q63_t) a2 * Yn2); + + /* The result is converted to 1.31 , Yn2 variable is reused */ + acc_l = (acc ) & 0xffffffff; /* Calc lower part of acc */ + acc_h = (acc >> 32) & 0xffffffff; /* Calc upper part of acc */ + + /* Apply shift for lower part of acc and upper part of acc */ + Yn2 = (uint32_t) acc_l >> lShift | acc_h << uShift; + + /* Store output in destination buffer. */ + *pOut++ = Yn2; + + /* Read the second input */ + Xn2 = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + acc = ((q63_t) b0 * Xn2) + ((q63_t) b1 * Xn) + ((q63_t) b2 * Xn1) + ((q63_t) a1 * Yn2) + ((q63_t) a2 * Yn1); + + /* The result is converted to 1.31, Yn1 variable is reused */ + acc_l = (acc ) & 0xffffffff; /* Calc lower part of acc */ + acc_h = (acc >> 32) & 0xffffffff; /* Calc upper part of acc */ + + /* Apply shift for lower part of acc and upper part of acc */ + Yn1 = (uint32_t) acc_l >> lShift | acc_h << uShift; + + /* Store output in destination buffer. */ + *pOut++ = Yn1; + + /* Read the third input */ + Xn1 = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + acc = ((q63_t) b0 * Xn1) + ((q63_t) b1 * Xn2) + ((q63_t) b2 * Xn) + ((q63_t) a1 * Yn1) + ((q63_t) a2 * Yn2); + + /* The result is converted to 1.31, Yn2 variable is reused */ + acc_l = (acc ) & 0xffffffff; /* Calc lower part of acc */ + acc_h = (acc >> 32) & 0xffffffff; /* Calc upper part of acc */ + + /* Apply shift for lower part of acc and upper part of acc */ + Yn2 = (uint32_t) acc_l >> lShift | acc_h << uShift; + + /* Store output in destination buffer. */ + *pOut++ = Yn2; + + /* Read the forth input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + acc = ((q63_t) b0 * Xn) + ((q63_t) b1 * Xn1) + ((q63_t) b2 * Xn2) + ((q63_t) a1 * Yn2) + ((q63_t) a2 * Yn1); + + /* The result is converted to 1.31, Yn1 variable is reused */ + acc_l = (acc ) & 0xffffffff; /* Calc lower part of acc */ + acc_h = (acc >> 32) & 0xffffffff; /* Calc upper part of acc */ + + /* Apply shift for lower part of acc and upper part of acc */ + Yn1 = (uint32_t) acc_l >> lShift | acc_h << uShift; + + /* Store output in destination buffer. */ + *pOut++ = Yn1; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + Xn2 = Xn1; + Xn1 = Xn; + + /* decrement loop counter */ + sample--; + } + + /* Loop unrolling: Compute remaining outputs */ + sample = blockSize & 0x3U; + +#else + + /* Initialize blkCnt with number of samples */ + sample = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (sample > 0U) + { + /* Read the input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + acc = ((q63_t) b0 * Xn) + ((q63_t) b1 * Xn1) + ((q63_t) b2 * Xn2) + ((q63_t) a1 * Yn1) + ((q63_t) a2 * Yn2); + + /* The result is converted to 1.31 */ + acc = acc >> lShift; + + /* Store output in destination buffer. */ + *pOut++ = (q31_t) acc; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + Xn2 = Xn1; + Xn1 = Xn; + Yn2 = Yn1; + Yn1 = (q31_t) acc; + + /* decrement loop counter */ + sample--; + } + + /* Store the updated state variables back into the pState array */ + *pState++ = Xn1; + *pState++ = Xn2; + *pState++ = Yn1; + *pState++ = Yn2; + + /* The first stage goes from the input buffer to the output buffer. */ + /* Subsequent numStages occur in-place in the output buffer */ + pIn = pDst; + + /* Reset output pointer */ + pOut = pDst; + + /* decrement loop counter */ + stage--; + + } while (stage > 0U); + +} + +/** + @} end of BiquadCascadeDF1 group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_biquad_cascade_df2T_f16.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_biquad_cascade_df2T_f16.c new file mode 100644 index 00000000..02fe9b1e --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_biquad_cascade_df2T_f16.c @@ -0,0 +1,356 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_biquad_cascade_df2T_f16.c + * Description: Processing function for floating-point transposed direct form II Biquad cascade filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions_f16.h" + +#if defined(RISCV_FLOAT16_SUPPORTED) +/** + @ingroup groupFilters +*/ + +/** + @addtogroup BiquadCascadeDF2T + @{ + */ + +/** + @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + @param[in] S points to an instance of the filter data structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + */ + +LOW_OPTIMIZATION_ENTER +void riscv_biquad_cascade_df2T_f16( + const riscv_biquad_cascade_df2T_instance_f16 * S, + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize) +{ + const float16_t *pIn = pSrc; /* Source pointer */ + float16_t *pOut = pDst; /* Destination pointer */ + float16_t *pState = S->pState; /* State pointer */ + const float16_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + _Float16 acc1; /* Accumulator */ + _Float16 b0, b1, b2, a1, a2; /* Filter coefficients */ + _Float16 Xn1; /* Temporary input */ + _Float16 d1, d2; /* State variables */ + uint32_t sample, stage = S->numStages; /* Loop counters */ + + do + { + /* Reading the coefficients */ + b0 = pCoeffs[0]; + b1 = pCoeffs[1]; + b2 = pCoeffs[2]; + a1 = pCoeffs[3]; + a2 = pCoeffs[4]; + + /* Reading the state values */ + d1 = pState[0]; + d2 = pState[1]; + + pCoeffs += 5U; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 16 outputs at a time */ + sample = blockSize >> 4U; + + while (sample > 0U) { + + /* y[n] = b0 * x[n] + d1 */ + /* d1 = b1 * x[n] + a1 * y[n] + d2 */ + /* d2 = b2 * x[n] + a2 * y[n] */ + +/* 1 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 2 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 3 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 4 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 5 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 6 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 7 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 8 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 9 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 10 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 11 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 12 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 13 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 14 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 15 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 16 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + + /* decrement loop counter */ + sample--; + } + + /* Loop unrolling: Compute remaining outputs */ + sample = blockSize & 0xFU; + +#else + + /* Initialize blkCnt with number of samples */ + sample = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (sample > 0U) { + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + + /* decrement loop counter */ + sample--; + } + + /* Store the updated state variables back into the state array */ + pState[0] = d1; + pState[1] = d2; + + pState += 2U; + + /* The current stage output is given as the input to the next stage */ + pIn = pDst; + + /* Reset the output working pointer */ + pOut = pDst; + + /* decrement loop counter */ + stage--; + + } while (stage > 0U); + +} +LOW_OPTIMIZATION_EXIT +/** + @} end of BiquadCascadeDF2T group + */ + +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_biquad_cascade_df2T_f32.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_biquad_cascade_df2T_f32.c new file mode 100644 index 00000000..7832478a --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_biquad_cascade_df2T_f32.c @@ -0,0 +1,353 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_biquad_cascade_df2T_f32.c + * Description: Processing function for floating-point transposed direct form II Biquad cascade filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters +*/ + +/** + @addtogroup BiquadCascadeDF2T + @{ + */ + +/** + @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + @param[in] S points to an instance of the filter data structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + */ +LOW_OPTIMIZATION_ENTER +void riscv_biquad_cascade_df2T_f32( + const riscv_biquad_cascade_df2T_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + const float32_t *pIn = pSrc; /* Source pointer */ + float32_t *pOut = pDst; /* Destination pointer */ + float32_t *pState = S->pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t acc1; /* Accumulator */ + float32_t b0, b1, b2, a1, a2; /* Filter coefficients */ + float32_t Xn1; /* Temporary input */ + float32_t d1, d2; /* State variables */ + uint32_t sample, stage = S->numStages; /* Loop counters */ + + do + { + /* Reading the coefficients */ + b0 = pCoeffs[0]; + b1 = pCoeffs[1]; + b2 = pCoeffs[2]; + a1 = pCoeffs[3]; + a2 = pCoeffs[4]; + + /* Reading the state values */ + d1 = pState[0]; + d2 = pState[1]; + + pCoeffs += 5U; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 16 outputs at a time */ + sample = blockSize >> 4U; + + while (sample > 0U) { + + /* y[n] = b0 * x[n] + d1 */ + /* d1 = b1 * x[n] + a1 * y[n] + d2 */ + /* d2 = b2 * x[n] + a2 * y[n] */ + +/* 1 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 2 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 3 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 4 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 5 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 6 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 7 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 8 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 9 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 10 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 11 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 12 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 13 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 14 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 15 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 16 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + + /* decrement loop counter */ + sample--; + } + + /* Loop unrolling: Compute remaining outputs */ + sample = blockSize & 0xFU; + +#else + + /* Initialize blkCnt with number of samples */ + sample = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (sample > 0U) { + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + + /* decrement loop counter */ + sample--; + } + + /* Store the updated state variables back into the state array */ + pState[0] = d1; + pState[1] = d2; + + pState += 2U; + + /* The current stage output is given as the input to the next stage */ + pIn = pDst; + + /* Reset the output working pointer */ + pOut = pDst; + + /* decrement loop counter */ + stage--; + + } while (stage > 0U); + +} +LOW_OPTIMIZATION_EXIT + +/** + @} end of BiquadCascadeDF2T group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_biquad_cascade_df2T_f64.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_biquad_cascade_df2T_f64.c new file mode 100644 index 00000000..433c53f7 --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_biquad_cascade_df2T_f64.c @@ -0,0 +1,444 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_biquad_cascade_df2T_f64.c + * Description: Processing function for floating-point transposed direct form II Biquad cascade filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters +*/ + +/** + @defgroup BiquadCascadeDF2T Biquad Cascade IIR Filters Using a Direct Form II Transposed Structure + + This set of functions implements arbitrary order recursive (IIR) filters using a transposed direct form II structure. + The filters are implemented as a cascade of second order Biquad sections. + These functions provide a slight memory savings as compared to the direct form I Biquad filter functions. + Only floating-point data is supported. + + This function operate on blocks of input and output data and each call to the function + processes blockSize samples through the filter. + pSrc points to the array of input data and + pDst points to the array of output data. + Both arrays contain blockSize values. + + @par Algorithm + Each Biquad stage implements a second order filter using the difference equation: + 
+     y[n] = b0 * x[n] + d1
+     d1 = b1 * x[n] + a1 * y[n] + d2
+     d2 = b2 * x[n] + a2 * y[n]
+
+ where d1 and d2 represent the two state values. + @par + A Biquad filter using a transposed Direct Form II structure is shown below. + \image html BiquadDF2Transposed.png "Single transposed Direct Form II Biquad" + Coefficients b0, b1, and b2 multiply the input signal x[n] and are referred to as the feedforward coefficients. + Coefficients a1 and a2 multiply the output signal y[n] and are referred to as the feedback coefficients. + Pay careful attention to the sign of the feedback coefficients. + Some design tools flip the sign of the feedback coefficients: + 
+     y[n] = b0 * x[n] + d1;
+     d1 = b1 * x[n] - a1 * y[n] + d2;
+     d2 = b2 * x[n] - a2 * y[n];
+
+ In this case the feedback coefficients a1 and a2 must be negated when used with the NMSIS DSP Library. + @par + Higher order filters are realized as a cascade of second order sections. + numStages refers to the number of second order stages used. + For example, an 8th order filter would be realized with numStages=4 second order stages. + A 9th order filter would be realized with numStages=5 second order stages with the + coefficients for one of the stages configured as a first order filter (b2=0 and a2=0). + @par + pState points to the state variable array. + Each Biquad stage has 2 state variables d1 and d2. + The state variables are arranged in the pState array as: + 
+      {d11, d12, d21, d22, ...}
+
+ where d1x refers to the state variables for the first Biquad and + d2x refers to the state variables for the second Biquad. + The state array has a total length of 2*numStages values. + The state variables are updated after each block of data is processed; the coefficients are untouched. + @par + The NMSIS library contains Biquad filters in both Direct Form I and transposed Direct Form II. + The advantage of the Direct Form I structure is that it is numerically more robust for fixed-point data types. + That is why the Direct Form I structure supports Q15 and Q31 data types. + The transposed Direct Form II structure, on the other hand, requires a wide dynamic range for the state variables d1 and d2. + Because of this, the NMSIS library only has a floating-point version of the Direct Form II Biquad. + The advantage of the Direct Form II Biquad is that it requires half the number of state variables, 2 rather than 4, per Biquad stage. + + @par Instance Structure + The coefficients and state variables for a filter are stored together in an instance data structure. + A separate instance structure must be defined for each filter. + Coefficient arrays may be shared among several instances while state variable arrays cannot be shared. + + @par Init Functions + There is also an associated initialization function. + The initialization function performs following operations: + - Sets the values of the internal structure fields. + - Zeros out the values in the state buffer. + To do this manually without calling the init function, assign the follow subfields of the instance structure: + numStages, pCoeffs, pState. Also set all of the values in pState to zero. + @par + Use of the initialization function is optional. + However, if the initialization function is used, then the instance structure cannot be placed into a const data section. + To place an instance structure into a const data section, the instance structure must be manually initialized. + Set the values in the state buffer to zeros before static initialization. + For example, to statically initialize the instance structure use + 
+      riscv_biquad_cascade_df2T_instance_f64 S1 = {numStages, pState, pCoeffs};
+      riscv_biquad_cascade_df2T_instance_f32 S1 = {numStages, pState, pCoeffs};
+
+ where numStages is the number of Biquad stages in the filter; + pState is the address of the state buffer. + pCoeffs is the address of the coefficient buffer; +*/ + +/** + @addtogroup BiquadCascadeDF2T + @{ + */ + +/** + @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + @param[in] S points to an instance of the filter data structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + */ + +LOW_OPTIMIZATION_ENTER +void riscv_biquad_cascade_df2T_f64( + const riscv_biquad_cascade_df2T_instance_f64 * S, + const float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize) +{ + + const float64_t *pIn = pSrc; /* Source pointer */ + float64_t *pOut = pDst; /* Destination pointer */ + float64_t *pState = S->pState; /* State pointer */ + const float64_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float64_t acc1; /* Accumulator */ + float64_t b0, b1, b2, a1, a2; /* Filter coefficients */ + float64_t Xn1; /* Temporary input */ + float64_t d1, d2; /* State variables */ + uint32_t sample, stage = S->numStages; /* Loop counters */ + + + do + { + /* Reading the coefficients */ + b0 = pCoeffs[0]; + b1 = pCoeffs[1]; + b2 = pCoeffs[2]; + a1 = pCoeffs[3]; + a2 = pCoeffs[4]; + + /* Reading the state values */ + d1 = pState[0]; + d2 = pState[1]; + + pCoeffs += 5U; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 16 outputs at a time */ + sample = blockSize >> 4U; + + while (sample > 0U) { + + /* y[n] = b0 * x[n] + d1 */ + /* d1 = b1 * x[n] + a1 * y[n] + d2 */ + /* d2 = b2 * x[n] + a2 * y[n] */ + +/* 1 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + + +/* 2 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 3 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 4 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 5 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 6 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 7 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 8 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 9 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 10 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 11 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 12 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 13 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 14 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 15 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 16 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + + /* decrement loop counter */ + sample--; + } + + /* Loop unrolling: Compute remaining outputs */ + sample = blockSize & 0xFU; + +#else + + /* Initialize blkCnt with number of samples */ + sample = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (sample > 0U) { + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + + /* decrement loop counter */ + sample--; + } + + /* Store the updated state variables back into the state array */ + pState[0] = d1; + pState[1] = d2; + + pState += 2U; + + /* The current stage output is given as the input to the next stage */ + pIn = pDst; + + /* Reset the output working pointer */ + pOut = pDst; + + /* decrement loop counter */ + stage--; + + } while (stage > 0U); + +} +LOW_OPTIMIZATION_EXIT + +/** + @} end of BiquadCascadeDF2T group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_biquad_cascade_df2T_init_f16.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_biquad_cascade_df2T_init_f16.c new file mode 100644 index 00000000..bb8fa7b5 --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_biquad_cascade_df2T_init_f16.c @@ -0,0 +1,115 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_biquad_cascade_df2T_init_f16.c + * Description: Initialization function for floating-point transposed direct form II Biquad cascade filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions_f16.h" + +#if defined(RISCV_FLOAT16_SUPPORTED) +/** + @ingroup groupFilters + */ + +/** + @addtogroup BiquadCascadeDF2T + @{ + */ + +/** + @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + @param[in,out] S points to an instance of the filter data structure. + @param[in] numStages number of 2nd order stages in the filter. + @param[in] pCoeffs points to the filter coefficients. + @param[in] pState points to the state buffer. + @return none + + @par Coefficient and State Ordering + The coefficients are stored in the array pCoeffs in the following order + in the not Neon version. + 
+      {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+
+ + @par + where b1x and a1x are the coefficients for the first stage, + b2x and a2x are the coefficients for the second stage, + and so on. The pCoeffs array contains a total of 5*numStages values. + + For Neon version, this array is bigger. If numstages = 4x + y, then the array has size: + 32*x + 5*y + and it must be initialized using the function + riscv_biquad_cascade_df2T_compute_coefs_f16 which is taking the + standard array coefficient as parameters. + + But, an array of 8*numstages is a good approximation. + + Then, the initialization can be done with: + 
+                   riscv_biquad_cascade_df2T_init_f16(&SNeon, nbCascade, neonCoefs, stateNeon);
+                   riscv_biquad_cascade_df2T_compute_coefs_f16(&SNeon,nbCascade,coefs);
+
+ + @par In this example, neonCoefs is a bigger array of size 8 * numStages. + coefs is the standard array: + + 
+      {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+
+ + + @par + The pState is a pointer to state array. + Each Biquad stage has 2 state variables d1, and d2. + The 2 state variables for stage 1 are first, then the 2 state variables for stage 2, and so on. + The state array has a total length of 2*numStages values. + The state variables are updated after each block of data is processed; the coefficients are untouched. + */ + +void riscv_biquad_cascade_df2T_init_f16( + riscv_biquad_cascade_df2T_instance_f16 * S, + uint8_t numStages, + const float16_t * pCoeffs, + float16_t * pState) +{ + /* Assign filter stages */ + S->numStages = numStages; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always 2 * numStages */ + memset(pState, 0, (2U * (uint32_t) numStages) * sizeof(float16_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of BiquadCascadeDF2T group + */ + +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_biquad_cascade_df2T_init_f32.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_biquad_cascade_df2T_init_f32.c new file mode 100644 index 00000000..864d4960 --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_biquad_cascade_df2T_init_f32.c @@ -0,0 +1,113 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_biquad_cascade_df2T_init_f32.c + * Description: Initialization function for floating-point transposed direct form II Biquad cascade filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup BiquadCascadeDF2T + @{ + */ + +/** + @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + @param[in,out] S points to an instance of the filter data structure. + @param[in] numStages number of 2nd order stages in the filter. + @param[in] pCoeffs points to the filter coefficients. + @param[in] pState points to the state buffer. + @return none + + @par Coefficient and State Ordering + The coefficients are stored in the array pCoeffs in the following order + in the not Neon version. + 
+      {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+
+ + @par + where b1x and a1x are the coefficients for the first stage, + b2x and a2x are the coefficients for the second stage, + and so on. The pCoeffs array contains a total of 5*numStages values. + + For Neon version, this array is bigger. If numstages = 4x + y, then the array has size: + 32*x + 5*y + and it must be initialized using the function + riscv_biquad_cascade_df2T_compute_coefs_f32 which is taking the + standard array coefficient as parameters. + + But, an array of 8*numstages is a good approximation. + + Then, the initialization can be done with: + 
+                   riscv_biquad_cascade_df2T_init_f32(&SNeon, nbCascade, neonCoefs, stateNeon);
+                   riscv_biquad_cascade_df2T_compute_coefs_f32(&SNeon,nbCascade,coefs);
+
+ + @par In this example, neonCoefs is a bigger array of size 8 * numStages. + coefs is the standard array: + + 
+      {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+
+ + + @par + The pState is a pointer to state array. + Each Biquad stage has 2 state variables d1, and d2. + The 2 state variables for stage 1 are first, then the 2 state variables for stage 2, and so on. + The state array has a total length of 2*numStages values. + The state variables are updated after each block of data is processed; the coefficients are untouched. + */ + + +void riscv_biquad_cascade_df2T_init_f32( + riscv_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + const float32_t * pCoeffs, + float32_t * pState) +{ + /* Assign filter stages */ + S->numStages = numStages; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always 2 * numStages */ + memset(pState, 0, (2U * (uint32_t) numStages) * sizeof(float32_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of BiquadCascadeDF2T group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_biquad_cascade_df2T_init_f64.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_biquad_cascade_df2T_init_f64.c new file mode 100644 index 00000000..ccaed725 --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_biquad_cascade_df2T_init_f64.c @@ -0,0 +1,87 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_biquad_cascade_df2T_init_f64.c + * Description: Initialization function for floating-point transposed direct form II Biquad cascade filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup BiquadCascadeDF2T + @{ + */ + +/** + @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + @param[in,out] S points to an instance of the filter data structure + @param[in] numStages number of 2nd order stages in the filter + @param[in] pCoeffs points to the filter coefficients + @param[in] pState points to the state buffer + @return none + + @par Coefficient and State Ordering + The coefficients are stored in the array pCoeffs in the following order: + 
+      {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+
+ @par + where b1x and a1x are the coefficients for the first stage, + b2x and a2x are the coefficients for the second stage, + and so on. The pCoeffs array contains a total of 5*numStages values. + @par + The pState is a pointer to state array. + Each Biquad stage has 2 state variables d1, and d2. + The 2 state variables for stage 1 are first, then the 2 state variables for stage 2, and so on. + The state array has a total length of 2*numStages values. + The state variables are updated after each block of data is processed; the coefficients are untouched. + */ + +void riscv_biquad_cascade_df2T_init_f64( + riscv_biquad_cascade_df2T_instance_f64 * S, + uint8_t numStages, + const float64_t * pCoeffs, + float64_t * pState) +{ + /* Assign filter stages */ + S->numStages = numStages; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always 2 * numStages */ + memset(pState, 0, (2U * (uint32_t) numStages) * sizeof(float64_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of BiquadCascadeDF2T group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_biquad_cascade_stereo_df2T_f16.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_biquad_cascade_stereo_df2T_f16.c new file mode 100644 index 00000000..125556d3 --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_biquad_cascade_stereo_df2T_f16.c @@ -0,0 +1,290 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_biquad_cascade_stereo_df2T_f16.c + * Description: Processing function for floating-point transposed direct form II Biquad cascade filter. 2 channels + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions_f16.h" + +#if defined(RISCV_FLOAT16_SUPPORTED) +/** + @ingroup groupFilters +*/ + +/** + @addtogroup BiquadCascadeDF2T + @{ + */ + +/** + @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + @param[in] S points to an instance of the filter data structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + */ + + +LOW_OPTIMIZATION_ENTER +void riscv_biquad_cascade_stereo_df2T_f16( + const riscv_biquad_cascade_stereo_df2T_instance_f16 * S, + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize) +{ + const float16_t *pIn = pSrc; /* Source pointer */ + float16_t *pOut = pDst; /* Destination pointer */ + float16_t *pState = S->pState; /* State pointer */ + const float16_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + _Float16 acc1a, acc1b; /* Accumulator */ + _Float16 b0, b1, b2, a1, a2; /* Filter coefficients */ + _Float16 Xn1a, Xn1b; /* Temporary input */ + _Float16 d1a, d2a, d1b, d2b; /* State variables */ + uint32_t sample, stage = S->numStages; /* Loop counters */ + + do + { + /* Reading the coefficients */ + b0 = pCoeffs[0]; + b1 = pCoeffs[1]; + b2 = pCoeffs[2]; + a1 = pCoeffs[3]; + a2 = pCoeffs[4]; + + /* Reading the state values */ + d1a = pState[0]; + d2a = pState[1]; + d1b = pState[2]; + d2b = pState[3]; + + pCoeffs += 5U; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 8 outputs at a time */ + sample = blockSize >> 3U; + + while (sample > 0U) { + /* y[n] = b0 * x[n] + d1 */ + /* d1 = b1 * x[n] + a1 * y[n] + d2 */ + /* d2 = b2 * x[n] + a2 * y[n] */ + +/* 1 */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + *pOut++ = acc1a; + *pOut++ = acc1b; + + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + +/* 2 */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + *pOut++ = acc1a; + *pOut++ = acc1b; + + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + +/* 3 */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + *pOut++ = acc1a; + *pOut++ = acc1b; + + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + +/* 4 */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + *pOut++ = acc1a; + *pOut++ = acc1b; + + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + +/* 5 */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + *pOut++ = acc1a; + *pOut++ = acc1b; + + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + +/* 6 */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + *pOut++ = acc1a; + *pOut++ = acc1b; + + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + +/* 7 */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + *pOut++ = acc1a; + *pOut++ = acc1b; + + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + +/* 8 */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + *pOut++ = acc1a; + *pOut++ = acc1b; + + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + + /* decrement loop counter */ + sample--; + } + + /* Loop unrolling: Compute remaining outputs */ + sample = blockSize & 0x7U; + +#else + + /* Initialize blkCnt with number of samples */ + sample = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (sample > 0U) { + /* Read the input */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + /* y[n] = b0 * x[n] + d1 */ + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = acc1a; + *pOut++ = acc1b; + + /* Every time after the output is computed state should be updated. */ + /* d1 = b1 * x[n] + a1 * y[n] + d2 */ + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + /* d2 = b2 * x[n] + a2 * y[n] */ + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + + /* decrement loop counter */ + sample--; + } + + /* Store the updated state variables back into the state array */ + pState[0] = d1a; + pState[1] = d2a; + + pState[2] = d1b; + pState[3] = d2b; + + pState += 4U; + + /* The current stage output is given as the input to the next stage */ + pIn = pDst; + + /* Reset the output working pointer */ + pOut = pDst; + + /* Decrement the loop counter */ + stage--; + + } while (stage > 0U); + +} +LOW_OPTIMIZATION_EXIT +/** + @} end of BiquadCascadeDF2T group + */ + +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_biquad_cascade_stereo_df2T_f32.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_biquad_cascade_stereo_df2T_f32.c new file mode 100644 index 00000000..48495b6c --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_biquad_cascade_stereo_df2T_f32.c @@ -0,0 +1,286 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_biquad_cascade_stereo_df2T_f32.c + * Description: Processing function for floating-point transposed direct form II Biquad cascade filter. 2 channels + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters +*/ + +/** + @addtogroup BiquadCascadeDF2T + @{ + */ + +/** + @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + @param[in] S points to an instance of the filter data structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + */ +LOW_OPTIMIZATION_ENTER +void riscv_biquad_cascade_stereo_df2T_f32( + const riscv_biquad_cascade_stereo_df2T_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + const float32_t *pIn = pSrc; /* Source pointer */ + float32_t *pOut = pDst; /* Destination pointer */ + float32_t *pState = S->pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t acc1a, acc1b; /* Accumulator */ + float32_t b0, b1, b2, a1, a2; /* Filter coefficients */ + float32_t Xn1a, Xn1b; /* Temporary input */ + float32_t d1a, d2a, d1b, d2b; /* State variables */ + uint32_t sample, stage = S->numStages; /* Loop counters */ + + do + { + /* Reading the coefficients */ + b0 = pCoeffs[0]; + b1 = pCoeffs[1]; + b2 = pCoeffs[2]; + a1 = pCoeffs[3]; + a2 = pCoeffs[4]; + + /* Reading the state values */ + d1a = pState[0]; + d2a = pState[1]; + d1b = pState[2]; + d2b = pState[3]; + + pCoeffs += 5U; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 8 outputs at a time */ + sample = blockSize >> 3U; + + while (sample > 0U) { + /* y[n] = b0 * x[n] + d1 */ + /* d1 = b1 * x[n] + a1 * y[n] + d2 */ + /* d2 = b2 * x[n] + a2 * y[n] */ + +/* 1 */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + *pOut++ = acc1a; + *pOut++ = acc1b; + + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + +/* 2 */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + *pOut++ = acc1a; + *pOut++ = acc1b; + + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + +/* 3 */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + *pOut++ = acc1a; + *pOut++ = acc1b; + + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + +/* 4 */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + *pOut++ = acc1a; + *pOut++ = acc1b; + + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + +/* 5 */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + *pOut++ = acc1a; + *pOut++ = acc1b; + + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + +/* 6 */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + *pOut++ = acc1a; + *pOut++ = acc1b; + + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + +/* 7 */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + *pOut++ = acc1a; + *pOut++ = acc1b; + + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + +/* 8 */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + *pOut++ = acc1a; + *pOut++ = acc1b; + + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + + /* decrement loop counter */ + sample--; + } + + /* Loop unrolling: Compute remaining outputs */ + sample = blockSize & 0x7U; + +#else + + /* Initialize blkCnt with number of samples */ + sample = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (sample > 0U) { + /* Read the input */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + /* y[n] = b0 * x[n] + d1 */ + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = acc1a; + *pOut++ = acc1b; + + /* Every time after the output is computed state should be updated. */ + /* d1 = b1 * x[n] + a1 * y[n] + d2 */ + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + /* d2 = b2 * x[n] + a2 * y[n] */ + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + + /* decrement loop counter */ + sample--; + } + + /* Store the updated state variables back into the state array */ + pState[0] = d1a; + pState[1] = d2a; + + pState[2] = d1b; + pState[3] = d2b; + + pState += 4U; + + /* The current stage output is given as the input to the next stage */ + pIn = pDst; + + /* Reset the output working pointer */ + pOut = pDst; + + /* Decrement the loop counter */ + stage--; + + } while (stage > 0U); + +} +LOW_OPTIMIZATION_EXIT + +/** + @} end of BiquadCascadeDF2T group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_biquad_cascade_stereo_df2T_init_f16.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_biquad_cascade_stereo_df2T_init_f16.c new file mode 100644 index 00000000..be18d77b --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_biquad_cascade_stereo_df2T_init_f16.c @@ -0,0 +1,91 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_biquad_cascade_stereo_df2T_init_f16.c + * Description: Initialization function for floating-point transposed direct form II Biquad cascade filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions_f16.h" + +#if defined(RISCV_FLOAT16_SUPPORTED) + +/** + @ingroup groupFilters + */ + +/** + @addtogroup BiquadCascadeDF2T + @{ + */ + +/** + @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + @param[in,out] S points to an instance of the filter data structure. + @param[in] numStages number of 2nd order stages in the filter. + @param[in] pCoeffs points to the filter coefficients. + @param[in] pState points to the state buffer. + @return none + + @par Coefficient and State Ordering + The coefficients are stored in the array pCoeffs in the following order: + 
+      {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+
+ @par + where b1x and a1x are the coefficients for the first stage, + b2x and a2x are the coefficients for the second stage, + and so on. The pCoeffs array contains a total of 5*numStages values. + @par + The pState is a pointer to state array. + Each Biquad stage has 2 state variables d1, and d2 for each channel. + The 2 state variables for stage 1 are first, then the 2 state variables for stage 2, and so on. + The state array has a total length of 2*numStages values. + The state variables are updated after each block of data is processed; the coefficients are untouched. + */ + +void riscv_biquad_cascade_stereo_df2T_init_f16( + riscv_biquad_cascade_stereo_df2T_instance_f16 * S, + uint8_t numStages, + const float16_t * pCoeffs, + float16_t * pState) +{ + /* Assign filter stages */ + S->numStages = numStages; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always 4 * numStages */ + memset(pState, 0, (4U * (uint32_t) numStages) * sizeof(float16_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of BiquadCascadeDF2T group + */ + +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_biquad_cascade_stereo_df2T_init_f32.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_biquad_cascade_stereo_df2T_init_f32.c new file mode 100644 index 00000000..d3c1f4ee --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_biquad_cascade_stereo_df2T_init_f32.c @@ -0,0 +1,87 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_biquad_cascade_stereo_df2T_init_f32.c + * Description: Initialization function for floating-point transposed direct form II Biquad cascade filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup BiquadCascadeDF2T + @{ + */ + +/** + @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + @param[in,out] S points to an instance of the filter data structure. + @param[in] numStages number of 2nd order stages in the filter. + @param[in] pCoeffs points to the filter coefficients. + @param[in] pState points to the state buffer. + @return none + + @par Coefficient and State Ordering + The coefficients are stored in the array pCoeffs in the following order: + 
+      {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+
+ @par + where b1x and a1x are the coefficients for the first stage, + b2x and a2x are the coefficients for the second stage, + and so on. The pCoeffs array contains a total of 5*numStages values. + @par + The pState is a pointer to state array. + Each Biquad stage has 2 state variables d1, and d2 for each channel. + The 2 state variables for stage 1 are first, then the 2 state variables for stage 2, and so on. + The state array has a total length of 2*numStages values. + The state variables are updated after each block of data is processed; the coefficients are untouched. + */ + +void riscv_biquad_cascade_stereo_df2T_init_f32( + riscv_biquad_cascade_stereo_df2T_instance_f32 * S, + uint8_t numStages, + const float32_t * pCoeffs, + float32_t * pState) +{ + /* Assign filter stages */ + S->numStages = numStages; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always 4 * numStages */ + memset(pState, 0, (4U * (uint32_t) numStages) * sizeof(float32_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of BiquadCascadeDF2T group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_conv_f32.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_conv_f32.c new file mode 100644 index 00000000..8b1dacd4 --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_conv_f32.c @@ -0,0 +1,704 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_conv_f32.c + * Description: Convolution of floating-point sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @defgroup Conv Convolution + + Convolution is a mathematical operation that operates on two finite length vectors to generate a finite length output vector. + Convolution is similar to correlation and is frequently used in filtering and data analysis. + The NMSIS DSP library contains functions for convolving Q7, Q15, Q31, and floating-point data types. + The library also provides fast versions of the Q15 and Q31 functions. + + @par Algorithm + Let a[n] and b[n] be sequences of length srcALen and + srcBLen samples respectively. Then the convolution + 
+     c[n] = a[n] * b[n]
+
+ @par + is defined as + \image html ConvolutionEquation.png + @par + Note that c[n] is of length srcALen + srcBLen - 1 and is defined over the interval n=0, 1, 2, ..., srcALen + srcBLen - 2. + pSrcA points to the first input vector of length srcALen and + pSrcB points to the second input vector of length srcBLen. + The output result is written to pDst and the calling function must allocate srcALen+srcBLen-1 words for the result. + @par + Conceptually, when two signals a[n] and b[n] are convolved, + the signal b[n] slides over a[n]. + For each offset \c n, the overlapping portions of a[n] and b[n] are multiplied and summed together. + @par + Note that convolution is a commutative operation: + 
+     a[n] * b[n] = b[n] * a[n].
+
+ @par + This means that switching the A and B arguments to the convolution functions has no effect. + + @par Fixed-Point Behavior + Convolution requires summing up a large number of intermediate products. + As such, the Q7, Q15, and Q31 functions run a risk of overflow and saturation. + Refer to the function specific documentation below for further details of the particular algorithm used. + + @par Fast Versions + Fast versions are supported for Q31 and Q15. Cycles for Fast versions are less compared to Q31 and Q15 of conv and the design requires + the input signals should be scaled down to avoid intermediate overflows. + + @par Opt Versions + Opt versions are supported for Q15 and Q7. Design uses internal scratch buffer for getting good optimisation. + These versions are optimised in cycles and consumes more memory (Scratch memory) compared to Q15 and Q7 versions + */ + +/** + @addtogroup Conv + @{ + */ + +/** + @brief Convolution of floating-point sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + @return none + */ +void riscv_conv_f32( + const float32_t * pSrcA, + uint32_t srcALen, + const float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst) +{ + +#if defined(RISCV_MATH_DSP) || defined (RISCV_VECTOR) + + const float32_t *pIn1; /* InputA pointer */ + const float32_t *pIn2; /* InputB pointer */ + float32_t *pOut = pDst; /* Output pointer */ + const float32_t *px; /* Intermediate inputA pointer */ + const float32_t *py; /* Intermediate inputB pointer */ + const float32_t *pSrc1, *pSrc2; /* Intermediate pointers */ + float32_t sum; /* Accumulators */ + uint32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + uint32_t j, k, count, blkCnt; /* Loop counters */ + + +#if defined (RISCV_MATH_LOOPUNROLL) + float32_t acc0, acc1, acc2, acc3, c0; /* Accumulators */ + float32_t x0, x1, x2, x3; /* Temporary variables to hold state and coefficient values */ +#endif + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */ + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* The algorithm is implemented in three stages. + The loop counters of each stage is initiated here. */ + blockSize1 = srcBLen - 1U; + blockSize2 = srcALen - (srcBLen - 1U); + blockSize3 = blockSize1; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[0] + * sum = x[0] * y[1] + x[1] * y[0] + * .... + * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = 1U; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + py = pIn2; + + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* The first stage starts here */ + while (blockSize1 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.0f; +#if defined (RISCV_VECTOR) + uint32_t vblkCnt = count; /* Loop counter */ + size_t l; + vfloat32m8_t vx, vy; + vfloat32m1_t temp00m1; + ptrdiff_t bstride = -4; + l = vsetvl_e32m1(1); + temp00m1 = vfmv_v_f_f32m1(0, l); + for (; (l = vsetvl_e32m8(vblkCnt)) > 0; vblkCnt -= l) { + vx = vle32_v_f32m8(px, l); + px += l; + vy = vlse32_v_f32m8(py, bstride, l); + py -= l; + sum += vfmv_f_s_f32m1_f32(vfredsum_vs_f32m8_f32m1(temp00m1, vfmul_vv_f32m8(vx, vy, l), temp00m1, l)); + } +#else +#if defined (RISCV_MATH_LOOPUNROLL) + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + + while (k > 0U) + { + /* x[0] * y[srcBLen - 1] */ + sum += *px++ * *py--; + + /* x[1] * y[srcBLen - 2] */ + sum += *px++ * *py--; + + /* x[2] * y[srcBLen - 3] */ + sum += *px++ * *py--; + + /* x[3] * y[srcBLen - 4] */ + sum += *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + + +#else /* defined (RISCV_MATH_LOOPUNROLL) */ + /* Initialize k with number of samples */ + k = count; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += *px++ * *py--; + + /* Decrement loop counter */ + k--; + } +#endif /*defined (RISCV_VECTOR)*/ + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum; + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = pIn2 + count; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0] + * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0] + * .... + * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0] + */ + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* count is index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ +#if defined (RISCV_VECTOR) + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.0f; + + /* srcBLen number of MACS should be performed */ + uint32_t vblkCnt = srcBLen; /* Loop counter */ + size_t l; + vfloat32m8_t vx, vy; + vfloat32m1_t temp00m1; + ptrdiff_t bstride = -4; + l = vsetvl_e32m1(vblkCnt); + temp00m1 = vfmv_v_f_f32m1(0, l); + for (; (l = vsetvl_e32m8(vblkCnt)) > 0; vblkCnt -= l) { + vx = vle32_v_f32m8(px, l); + px += l; + vy = vlse32_v_f32m8(py, bstride, l); + py -= l; + sum += vfmv_f_s_f32m1_f32(vfredsum_vs_f32m8_f32m1(temp00m1, vfmul_vv_f32m8(vx, vy, l), temp00m1, l)); + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum; + + /* Increment the MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement the loop counter */ + blkCnt--; + } +#else + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { + + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize2 >> 2U; + + while (blkCnt > 0U) + { + /* Set all accumulators to zero */ + acc0 = 0.0f; + acc1 = 0.0f; + acc2 = 0.0f; + acc3 = 0.0f; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* read x[0], x[1], x[2] samples */ + x0 = *px++; + x1 = *px++; + x2 = *px++; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + do + { + /* Read y[srcBLen - 1] sample */ + c0 = *py--; + /* Read x[3] sample */ + x3 = *(px); + + /* Perform the multiply-accumulate */ + /* acc0 += x[0] * y[srcBLen - 1] */ + acc0 += x0 * c0; + /* acc1 += x[1] * y[srcBLen - 1] */ + acc1 += x1 * c0; + /* acc2 += x[2] * y[srcBLen - 1] */ + acc2 += x2 * c0; + /* acc3 += x[3] * y[srcBLen - 1] */ + acc3 += x3 * c0; + + /* Read y[srcBLen - 2] sample */ + c0 = *py--; + /* Read x[4] sample */ + x0 = *(px + 1U); + + /* Perform the multiply-accumulate */ + /* acc0 += x[1] * y[srcBLen - 2] */ + acc0 += x1 * c0; + /* acc1 += x[2] * y[srcBLen - 2] */ + acc1 += x2 * c0; + /* acc2 += x[3] * y[srcBLen - 2] */ + acc2 += x3 * c0; + /* acc3 += x[4] * y[srcBLen - 2] */ + acc3 += x0 * c0; + + /* Read y[srcBLen - 3] sample */ + c0 = *py--; + /* Read x[5] sample */ + x1 = *(px + 2U); + + /* Perform the multiply-accumulate */ + /* acc0 += x[2] * y[srcBLen - 3] */ + acc0 += x2 * c0; + /* acc1 += x[3] * y[srcBLen - 2] */ + acc1 += x3 * c0; + /* acc2 += x[4] * y[srcBLen - 2] */ + acc2 += x0 * c0; + /* acc3 += x[5] * y[srcBLen - 2] */ + acc3 += x1 * c0; + + /* Read y[srcBLen - 4] sample */ + c0 = *py--; + /* Read x[6] sample */ + x2 = *(px + 3U); + px += 4U; + + /* Perform the multiply-accumulate */ + /* acc0 += x[3] * y[srcBLen - 4] */ + acc0 += x3 * c0; + /* acc1 += x[4] * y[srcBLen - 4] */ + acc1 += x0 * c0; + /* acc2 += x[5] * y[srcBLen - 4] */ + acc2 += x1 * c0; + /* acc3 += x[6] * y[srcBLen - 4] */ + acc3 += x2 * c0; + + } while (--k); + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Read y[srcBLen - 5] sample */ + c0 = *py--; + /* Read x[7] sample */ + x3 = *px++; + + /* Perform the multiply-accumulate */ + /* acc0 += x[4] * y[srcBLen - 5] */ + acc0 += x0 * c0; + /* acc1 += x[5] * y[srcBLen - 5] */ + acc1 += x1 * c0; + /* acc2 += x[6] * y[srcBLen - 5] */ + acc2 += x2 * c0; + /* acc3 += x[7] * y[srcBLen - 5] */ + acc3 += x3 * c0; + + /* Reuse the present samples for the next MAC */ + x0 = x1; + x1 = x2; + x2 = x3; + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = acc0; + *pOut++ = acc1; + *pOut++ = acc2; + *pOut++ = acc3; + + /* Increment the pointer pIn1 index, count by 4 */ + count += 4U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize2 % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize2; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.0f; + +#if defined (RISCV_MATH_LOOPUNROLL) + /* Loop unrolling: Compute 4 outputs at a time */ + k = srcBLen >> 2U; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += *px++ * *py--; + sum += *px++ * *py--; + sum += *px++ * *py--; + sum += *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = srcBLen % 0x4U; + +#else + /* Initialize blkCnt with number of samples */ + k = srcBLen; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += *px++ * *py--; + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum; + + /* Increment the MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.0f; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += *px++ * *py--; + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum; + + /* Increment the MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement the loop counter */ + blkCnt--; + } + } +#endif /*defined (RISCV_VECTOR)*/ + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1] + * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2] + * .... + * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2] + * sum += x[srcALen-1] * y[srcBLen-1] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The blockSize3 variable holds the number of MAC operations performed */ + + /* Working pointer of inputA */ + pSrc1 = pIn1 + (srcALen - (srcBLen - 1U)); + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* ------------------- + * Stage3 process + * ------------------*/ + while (blockSize3 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.0f; +#if defined (RISCV_VECTOR) + uint32_t vblkCnt = blockSize3; /* Loop counter */ + size_t l; + vfloat32m8_t vx, vy; + vfloat32m1_t temp00m1; + ptrdiff_t bstride = -4; + l = vsetvl_e32m1(1); + temp00m1 = vfmv_v_f_f32m1(0, l); + for (; (l = vsetvl_e32m8(vblkCnt)) > 0; vblkCnt -= l) { + vx = vle32_v_f32m8(px, l); + px += l; + vy = vlse32_v_f32m8(py, bstride, l); + py -= l; + sum += vfmv_f_s_f32m1_f32(vfredsum_vs_f32m8_f32m1(temp00m1, vfmul_vv_f32m8(vx, vy, l), temp00m1, l)); + } +#else +#if defined (RISCV_MATH_LOOPUNROLL) + /* Loop unrolling: Compute 4 outputs at a time */ + k = blockSize3 >> 2U; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */ + sum += *px++ * *py--; + + /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */ + sum += *px++ * *py--; + + /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */ + sum += *px++ * *py--; + + /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */ + sum += *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = blockSize3 % 0x4U; +#else + + /* Initialize blkCnt with number of samples */ + k = blockSize3; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL)*/ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* sum += x[srcALen-1] * y[srcBLen-1] */ + sum += *px++ * *py--; + + /* Decrement loop counter */ + k--; + } +#endif /*defined (RISCV_VECTOR)*/ + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pSrc2; + + /* Decrement the loop counter */ + blockSize3--; + } + +#else +/* alternate version for CM0_FAMILY */ + + const float32_t *pIn1 = pSrcA; /* InputA pointer */ + const float32_t *pIn2 = pSrcB; /* InputB pointer */ + float32_t sum; /* Accumulator */ + uint32_t i, j; /* Loop counters */ + + /* Loop to calculate convolution for output length number of times */ + for (i = 0U; i < (srcALen + srcBLen - 1U); i++) + { + /* Initialize sum with zero to carry out MAC operations */ + sum = 0.0f; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0U; j <= i; j++) + { + /* Check the array limitations */ + if (((i - j) < srcBLen) && (j < srcALen)) + { + /* z[i] += x[i-j] * y[j] */ + sum += ( pIn1[j] * pIn2[i - j]); + } + } + + /* Store the output in the destination buffer */ + pDst[i] = sum; + } + +#endif /* #if !defined(RISCV_MATH_CM0_FAMILY) */ + +} + +/** + @} end of Conv group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_conv_fast_opt_q15.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_conv_fast_opt_q15.c new file mode 100644 index 00000000..529a3cb6 --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_conv_fast_opt_q15.c @@ -0,0 +1,363 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_conv_fast_opt_q15.c + * Description: Fast Q15 Convolution + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Conv + @{ + */ + +/** + @brief Convolution of Q15 sequences (fast version). + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1 + @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2 + @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen + @return none + + @par Scaling and Overflow Behavior + This fast version uses a 32-bit accumulator with 2.30 format. + The accumulator maintains full precision of the intermediate multiplication results + but provides only a single guard bit. There is no saturation on intermediate additions. + Thus, if the accumulator overflows it wraps around and distorts the result. + The input signals should be scaled down to avoid intermediate overflows. + Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows, + as maximum of min(srcALen, srcBLen) number of additions are carried internally. + The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result. + + @remark + Refer to \ref riscv_conv_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion. + */ + +void riscv_conv_fast_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2) +{ +#if defined (RISCV_VECTOR) + riscv_conv_opt_q15(pSrcA,srcALen,pSrcB,srcBLen,pDst,pScratch1,pScratch2); +#else + q31_t acc0; /* Accumulators */ + const q15_t *pIn1; /* InputA pointer */ + const q15_t *pIn2; /* InputB pointer */ + q15_t *pOut = pDst; /* Output pointer */ + q15_t *pScr1 = pScratch1; /* Temporary pointer for scratch1 */ + q15_t *pScr2 = pScratch2; /* Temporary pointer for scratch1 */ + const q15_t *px; /* Intermediate inputA pointer */ + q15_t *py; /* Intermediate inputB pointer */ + uint32_t j, k, blkCnt; /* Loop counter */ + uint32_t tapCnt; /* Loop count */ + +#if defined (RISCV_MATH_LOOPUNROLL) + q31_t acc1, acc2, acc3; /* Accumulators */ + q31_t x1, x2, x3; /* Temporary variables to hold state and coefficient values */ + q31_t y1, y2; /* State variables */ +#endif + + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } +#if __RISCV_XLEN == 64 + /* Pointer to take end of scratch2 buffer */ + pScr2 = pScratch2 + srcBLen - 3; +#else + /* Pointer to take end of scratch2 buffer */ + pScr2 = pScratch2 + srcBLen - 1; +#endif /* __RISCV_XLEN == 64 */ + + /* points to smaller length sequence */ + px = pIn2; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = srcBLen >> 2U; + + /* Copy smaller length input sequence in reverse order into second scratch buffer */ + while (k > 0U) + { +#if __RISCV_XLEN == 64 + write_q15x4_da(&pScr2,read_q15x4_ia((q15_t **)&px)); +#else + /* copy second buffer in reversal manner */ + *pScr2-- = *px++; + *pScr2-- = *px++; + *pScr2-- = *px++; + *pScr2-- = *px++; +#endif /* __RISCV_XLEN == 64 */ + + /* Decrement loop counter */ + k--; + } +#if __RISCV_XLEN == 64 + pScr2 += 3; +#endif /* __RISCV_XLEN == 64 */ + /* Loop unrolling: Compute remaining outputs */ + k = srcBLen % 0x4U; + +#else + + /* Initialize k with number of samples */ + k = srcBLen; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* copy second buffer in reversal manner for remaining samples */ + *pScr2-- = *px++; + + /* Decrement loop counter */ + k--; + } + + /* Initialze temporary scratch pointer */ + pScr1 = pScratch1; + + /* Assuming scratch1 buffer is aligned by 32-bit */ + /* Fill (srcBLen - 1U) zeros in scratch1 buffer */ + riscv_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update temporary scratch pointer */ + pScr1 += (srcBLen - 1U); + + /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */ + + /* Copy (srcALen) samples in scratch buffer */ + riscv_copy_q15(pIn1, pScr1, srcALen); + + /* Update pointers */ + pScr1 += srcALen; + + + /* Fill (srcBLen - 1U) zeros at end of scratch buffer */ + riscv_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update pointer */ + pScr1 += (srcBLen - 1U); + + /* Temporary pointer for scratch2 */ + py = pScratch2; + + + /* Initialization of pIn2 pointer */ + pIn2 = py; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (srcALen + srcBLen - 1U) >> 2; + + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch1; + + /* Clear Accumlators */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Read two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* Read next two samples from scratch1 buffer */ + x2 = read_q15x2_ia (&pScr1); + + tapCnt = (srcBLen) >> 2U; + + while (tapCnt > 0U) + { + + /* Read four samples from smaller buffer */ + y1 = read_q15x2_ia ((q15_t **) &pIn2); + y2 = read_q15x2_ia ((q15_t **) &pIn2); + + /* multiply and accumulate */ + acc0 = __SMLAD(x1, y1, acc0); + acc2 = __SMLAD(x2, y1, acc2); + + /* pack input data */ + x3 = __PKHBT(x2, x1, 0); + + /* multiply and accumulate */ + acc1 = __SMLADX(x3, y1, acc1); + + /* Read next two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* multiply and accumulate */ + acc0 = __SMLAD(x2, y2, acc0); + acc2 = __SMLAD(x1, y2, acc2); + + /* pack input data */ + x3 = __PKHBT(x1, x2, 0); + + acc3 = __SMLADX(x3, y1, acc3); + acc1 = __SMLADX(x3, y2, acc1); + + x2 = read_q15x2_ia (&pScr1); + + x3 = __PKHBT(x2, x1, 0); + + acc3 = __SMLADX(x3, y2, acc3); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Update scratch pointer for remaining samples of smaller length sequence */ + pScr1 -= 4U; + + /* apply same above for remaining samples of smaller length sequence */ + tapCnt = (srcBLen) & 3U; + + while (tapCnt > 0U) + { + /* accumulate the results */ + acc0 += (*pScr1++ * *pIn2); + acc1 += (*pScr1++ * *pIn2); + acc2 += (*pScr1++ * *pIn2); + acc3 += (*pScr1++ * *pIn2++); + + pScr1 -= 3U; + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* Store the results in the accumulators in the destination buffer. */ + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16)); + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16)); + + /* Initialization of inputB pointer */ + pIn2 = py; + + pScratch1 += 4U; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (srcALen + srcBLen - 1U) & 0x3; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = (srcALen + srcBLen - 1U); + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + /* Calculate convolution for remaining samples of Bigger length sequence */ + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch1; + + /* Clear Accumlators */ + acc0 = 0; + + tapCnt = (srcBLen) >> 1U; + + while (tapCnt > 0U) + { + + /* Read next two samples from scratch1 buffer */ + acc0 += (*pScr1++ * *pIn2++); + acc0 += (*pScr1++ * *pIn2++); + + /* Decrement loop counter */ + tapCnt--; + } + + tapCnt = (srcBLen) & 1U; + + /* apply same above for remaining samples of smaller length sequence */ + while (tapCnt > 0U) + { + + /* accumulate the results */ + acc0 += (*pScr1++ * *pIn2++); + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* The result is in 2.30 format. Convert to 1.15 with saturation. + Then store the output in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16)); + + /* Initialization of inputB pointer */ + pIn2 = py; + + pScratch1 += 1U; + } +#endif /*defined (RISCV_VECTOR)*/ +} + +/** + @} end of Conv group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_conv_fast_q15.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_conv_fast_q15.c new file mode 100644 index 00000000..348f995b --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_conv_fast_q15.c @@ -0,0 +1,663 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_conv_fast_q15.c + * Description: Fast Q15 Convolution + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Conv + @{ + */ + +/** + @brief Convolution of Q15 sequences (fast version). + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1 + @return none + + @par Scaling and Overflow Behavior + This fast version uses a 32-bit accumulator with 2.30 format. + The accumulator maintains full precision of the intermediate multiplication results + but provides only a single guard bit. There is no saturation on intermediate additions. + Thus, if the accumulator overflows it wraps around and distorts the result. + The input signals should be scaled down to avoid intermediate overflows. + Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows, + as maximum of min(srcALen, srcBLen) number of additions are carried internally. + The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result. + + @remark + Refer to \ref riscv_conv_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion. + */ + +void riscv_conv_fast_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst) +{ +#if defined (RISCV_VECTOR) + riscv_conv_q15(pSrcA,srcALen,pSrcB,srcBLen,pDst); +#else + const q15_t *pIn1; /* InputA pointer */ + const q15_t *pIn2; /* InputB pointer */ + q15_t *pOut = pDst; /* Output pointer */ + q31_t sum, acc0, acc1, acc2, acc3; /* Accumulators */ + const q15_t *px; /* Intermediate inputA pointer */ + const q15_t *py; /* Intermediate inputB pointer */ + const q15_t *pSrc1, *pSrc2; /* Intermediate pointers */ + q31_t x0, x1, x2, x3, c0; /* Temporary variables to hold state and coefficient values */ + uint32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + uint32_t j, k, count, blkCnt; /* Loop counters */ + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */ + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* The algorithm is implemented in three stages. + The loop counters of each stage is initiated here. */ + blockSize1 = srcBLen - 1U; + blockSize2 = srcALen - (srcBLen - 1U); + blockSize3 = blockSize1; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[0] + * sum = x[0] * y[1] + x[1] * y[0] + * .... + * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = 1U; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + py = pIn2; + + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* For loop unrolling by 4, this stage is divided into two. */ + /* First part of this stage computes the MAC operations less than 4 */ + /* Second part of this stage computes the MAC operations greater than or equal to 4 */ + + /* The first part of the stage starts here */ + while ((count < 4U) && (blockSize1 > 0U)) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Loop over number of MAC operations between + * inputA samples and inputB samples */ + k = count; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum = __SMLAD(*px++, *py--, sum); + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (sum >> 15); + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = pIn2 + count; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* The second part of the stage starts here */ + /* The internal loop, over count, is unrolled by 4 */ + /* To, read the last two inputB samples using SIMD: + * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */ + py = py - 1; + + while (blockSize1 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = count >> 2U; + +#if defined RISCV_MATH_DSP && __RISCV_XLEN == 64 + py -= 2; +#endif /* defined RISCV_MATH_DSP && __RISCV_XLEN == 64 */ + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulates */ +#if defined RISCV_MATH_DSP && __RISCV_XLEN == 64 + sum = __RV_KMAXDA(sum, read_q15x4_ia ((q15_t **) &px), read_q15x4_da ((q15_t **) &py)); +#else + /* x[0], x[1] are multiplied with y[srcBLen - 1], y[srcBLen - 2] respectively */ + sum = __SMLADX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum); + /* x[2], x[3] are multiplied with y[srcBLen - 3], y[srcBLen - 4] respectively */ + sum = __SMLADX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum); +#endif /* defined RISCV_MATH_DSP && __RISCV_XLEN == 64 */ + + /* Decrement loop counter */ + k--; + } +#if defined RISCV_MATH_DSP && __RISCV_XLEN == 64 + py += 2; +#endif /* defined RISCV_MATH_DSP && __RISCV_XLEN == 64 */ + /* For the next MAC operations, the pointer py is used without SIMD + * So, py is incremented by 1 */ + py = py + 1U; + + /* If the count is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = count % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum = __SMLAD(*px++, *py--, sum); + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (sum >> 15); + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = pIn2 + (count - 1U); + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0] + * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0] + * .... + * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0] + */ + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* count is the index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* -------------------- + * Stage2 process + * -------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { + /* Loop unroll over blockSize2, by 4 */ + blkCnt = blockSize2 >> 2U; + + while (blkCnt > 0U) + { + py = py - 1U; + + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* read x[0], x[1] samples */ + x0 = read_q15x2 ((q15_t *) px); + /* read x[1], x[2] samples */ + x1 = read_q15x2 ((q15_t *) px + 1); + px += 2U; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + do + { + /* Read the last two inputB samples using SIMD: + * y[srcBLen - 1] and y[srcBLen - 2] */ + c0 = read_q15x2_da ((q15_t **) &py); + + /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */ + acc0 = __SMLADX(x0, c0, acc0); + + /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */ + acc1 = __SMLADX(x1, c0, acc1); + + /* Read x[2], x[3] */ + x2 = read_q15x2 ((q15_t *) px); + + /* Read x[3], x[4] */ + x3 = read_q15x2 ((q15_t *) px + 1); + + /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */ + acc2 = __SMLADX(x2, c0, acc2); + + /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */ + acc3 = __SMLADX(x3, c0, acc3); + + /* Read y[srcBLen - 3] and y[srcBLen - 4] */ + c0 = read_q15x2_da ((q15_t **) &py); + + /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */ + acc0 = __SMLADX(x2, c0, acc0); + + /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */ + acc1 = __SMLADX(x3, c0, acc1); + + /* Read x[4], x[5] */ + x0 = read_q15x2 ((q15_t *) px + 2); + + /* Read x[5], x[6] */ + x1 = read_q15x2 ((q15_t *) px + 3); + px += 4U; + + /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */ + acc2 = __SMLADX(x0, c0, acc2); + + /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */ + acc3 = __SMLADX(x1, c0, acc3); + + } while (--k); + + /* For the next MAC operations, SIMD is not used + * So, the 16 bit pointer if inputB, py is updated */ + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + if (k == 1U) + { + /* Read y[srcBLen - 5] */ + c0 = *(py+1); + + c0 = c0 & 0x0000FFFF; + + /* Read x[7] */ + x3 = read_q15x2 ((q15_t *) px); + px++; + + /* Perform the multiply-accumulates */ + acc0 = __SMLAD(x0, c0, acc0); + acc1 = __SMLAD(x1, c0, acc1); + acc2 = __SMLADX(x1, c0, acc2); + acc3 = __SMLADX(x3, c0, acc3); + } + + if (k == 2U) + { + /* Read y[srcBLen - 5], y[srcBLen - 6] */ + c0 = read_q15x2 ((q15_t *) py); + + /* Read x[7], x[8] */ + x3 = read_q15x2 ((q15_t *) px); + + /* Read x[9] */ + x2 = read_q15x2 ((q15_t *) px + 1); + px += 2U; + + /* Perform the multiply-accumulates */ + acc0 = __SMLADX(x0, c0, acc0); + acc1 = __SMLADX(x1, c0, acc1); + acc2 = __SMLADX(x3, c0, acc2); + acc3 = __SMLADX(x2, c0, acc3); + } + + if (k == 3U) + { + /* Read y[srcBLen - 5], y[srcBLen - 6] */ + c0 = read_q15x2 ((q15_t *) py); + + /* Read x[7], x[8] */ + x3 = read_q15x2 ((q15_t *) px); + + /* Read x[9] */ + x2 = read_q15x2 ((q15_t *) px + 1); + + /* Perform the multiply-accumulates */ + acc0 = __SMLADX(x0, c0, acc0); + acc1 = __SMLADX(x1, c0, acc1); + acc2 = __SMLADX(x3, c0, acc2); + acc3 = __SMLADX(x2, c0, acc3); + + /* Read y[srcBLen - 7] */ + c0 = *(py-1); + c0 = c0 & 0x0000FFFF; + + /* Read x[10] */ + x3 = read_q15x2 ((q15_t *) px + 2); + px += 3U; + + /* Perform the multiply-accumulates */ + acc0 = __SMLADX(x1, c0, acc0); + acc1 = __SMLAD(x2, c0, acc1); + acc2 = __SMLADX(x2, c0, acc2); + acc3 = __SMLADX(x3, c0, acc3); + } + + /* Store the result in the accumulator in the destination buffer. */ + write_q15x2_ia (&pOut, __PKHBT((acc0 >> 15), (acc1 >> 15), 16)); + write_q15x2_ia (&pOut, __PKHBT((acc2 >> 15), (acc3 >> 15), 16)); + + /* Increment the pointer pIn1 index, count by 4 */ + count += 4U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize2 % 0x4U; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum += ((q31_t) *px++ * *py--); + sum += ((q31_t) *px++ * *py--); + sum += ((q31_t) *px++ * *py--); + sum += ((q31_t) *px++ * *py--); + + /* Decrement loop counter */ + k--; + } + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum += ((q31_t) *px++ * *py--); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (sum >> 15); + + /* Increment the pointer pIn1 index, count by 1 */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += ((q31_t) *px++ * *py--); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (sum >> 15); + + /* Increment MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + } + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1] + * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2] + * .... + * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2] + * sum += x[srcALen-1] * y[srcBLen-1] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The blockSize3 variable holds the number of MAC operations performed */ + + /* Working pointer of inputA */ + pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U); + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + pIn2 = pSrc2 - 1U; + py = pIn2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + /* For loop unrolling by 4, this stage is divided into two. */ + /* First part of this stage computes the MAC operations greater than 4 */ + /* Second part of this stage computes the MAC operations less than or equal to 4 */ + + /* The first part of the stage starts here */ + j = blockSize3 >> 2U; + + while ((j > 0U) && (blockSize3 > 0U)) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = blockSize3 >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* x[srcALen - srcBLen + 1], x[srcALen - srcBLen + 2] are multiplied + * with y[srcBLen - 1], y[srcBLen - 2] respectively */ + sum = __SMLADX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum); + /* x[srcALen - srcBLen + 3], x[srcALen - srcBLen + 4] are multiplied + * with y[srcBLen - 3], y[srcBLen - 4] respectively */ + sum = __SMLADX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum); + + /* Decrement loop counter */ + k--; + } + + /* For the next MAC operations, the pointer py is used without SIMD + * So, py is incremented by 1 */ + py = py + 1U; + + /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = blockSize3 % 0x4U; + + while (k > 0U) + { + /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */ + sum = __SMLAD(*px++, *py--, sum); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (sum >> 15); + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pIn2; + + /* Decrement loop counter */ + blockSize3--; + + j--; + } + + /* The second part of the stage starts here */ + /* SIMD is not used for the next MAC operations, + * so pointer py is updated to read only one sample at a time */ + py = py + 1U; + + while (blockSize3 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = blockSize3; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + /* sum += x[srcALen-1] * y[srcBLen-1] */ + sum = __SMLAD(*px++, *py--, sum); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (sum >> 15); + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pSrc2; + + /* Decrement the loop counter */ + blockSize3--; + } +#endif /*defiend (RISCV_VECTOR)*/ +} + +/** + @} end of Conv group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_conv_fast_q31.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_conv_fast_q31.c new file mode 100644 index 00000000..16fee16b --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_conv_fast_q31.c @@ -0,0 +1,562 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_conv_fast_q31.c + * Description: Fast Q31 Convolution + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Conv + @{ + */ + +/** + @brief Convolution of Q31 sequences (fast version). + @param[in] pSrcA points to the first input sequence. + @param[in] srcALen length of the first input sequence. + @param[in] pSrcB points to the second input sequence. + @param[in] srcBLen length of the second input sequence. + @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + @return none + + @par Scaling and Overflow Behavior + This function is optimized for speed at the expense of fixed-point precision and overflow protection. + The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format. + These intermediate results are accumulated in a 32-bit register in 2.30 format. + Finally, the accumulator is saturated and converted to a 1.31 result. + @par + The fast version has the same overflow behavior as the standard version but provides less precision since it discards the low 32 bits of each multiplication result. + In order to avoid overflows completely the input signals must be scaled down. + Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows, + as maximum of min(srcALen, srcBLen) number of additions are carried internally. + @remark + Refer to \ref riscv_conv_q31() for a slower implementation of this function which uses 64-bit accumulation to provide higher precision. + */ + +void riscv_conv_fast_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst) +{ +#if defined (RISCV_VECTOR) + riscv_conv_q31(pSrcA,srcALen,pSrcB,srcBLen,pDst); +#else + const q31_t *pIn1; /* InputA pointer */ + const q31_t *pIn2; /* InputB pointer */ + q31_t *pOut = pDst; /* Output pointer */ + const q31_t *px; /* Intermediate inputA pointer */ + const q31_t *py; /* Intermediate inputB pointer */ + const q31_t *pSrc1, *pSrc2; /* Intermediate pointers */ + q31_t sum, acc0, acc1, acc2, acc3; /* Accumulators */ + q31_t x0, x1, x2, x3, c0; /* Temporary variables to hold state and coefficient values */ + uint32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + uint32_t j, k, count, blkCnt; /* Loop counters */ + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */ + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* The algorithm is implemented in three stages. + The loop counters of each stage is initiated here. */ + blockSize1 = srcBLen - 1U; + blockSize2 = srcALen - (srcBLen - 1U); + blockSize3 = blockSize1; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[0] + * sum = x[0] * y[1] + x[1] * y[0] + * .... + * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = 1U; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + py = pIn2; + + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* The first stage starts here */ + while (blockSize1 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = count >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* x[0] * y[srcBLen - 1] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* x[1] * y[srcBLen - 2] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* x[2] * y[srcBLen - 3] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* x[3] * y[srcBLen - 4] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* If the count is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = count % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum << 1; + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = pIn2 + count; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0] + * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0] + * .... + * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0] + */ + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* count is index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { + /* Loop unroll over blockSize2, by 4 */ + blkCnt = blockSize2 >> 2U; + + while (blkCnt > 0U) + { + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* read x[0], x[1], x[2] samples */ + x0 = *px++; + x1 = *px++; + x2 = *px++; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + do + { + /* Read y[srcBLen - 1] sample */ + c0 = *py--; + /* Read x[3] sample */ + x3 = *px++; + + /* Perform the multiply-accumulate */ + /* acc0 += x[0] * y[srcBLen - 1] */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32); + /* acc1 += x[1] * y[srcBLen - 1] */ + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32); + /* acc2 += x[2] * y[srcBLen - 1] */ + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32); + /* acc3 += x[3] * y[srcBLen - 1] */ + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32); + + + /* Read y[srcBLen - 2] sample */ + c0 = *py--; + /* Read x[4] sample */ + x0 = *px++; + + /* Perform the multiply-accumulate */ + /* acc0 += x[1] * y[srcBLen - 2] */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x1 * c0)) >> 32); + /* acc1 += x[2] * y[srcBLen - 2] */ + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x2 * c0)) >> 32); + /* acc2 += x[3] * y[srcBLen - 2] */ + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x3 * c0)) >> 32); + /* acc3 += x[4] * y[srcBLen - 2] */ + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x0 * c0)) >> 32); + + + /* Read y[srcBLen - 3] sample */ + c0 = *py--; + /* Read x[5] sample */ + x1 = *px++; + + /* Perform the multiply-accumulates */ + /* acc0 += x[2] * y[srcBLen - 3] */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x2 * c0)) >> 32); + /* acc1 += x[3] * y[srcBLen - 3] */ + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x3 * c0)) >> 32); + /* acc2 += x[4] * y[srcBLen - 3] */ + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x0 * c0)) >> 32); + /* acc3 += x[5] * y[srcBLen - 3] */ + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x1 * c0)) >> 32); + + + /* Read y[srcBLen - 4] sample */ + c0 = *py--; + /* Read x[6] sample */ + x2 = *px++; + + /* Perform the multiply-accumulates */ + /* acc0 += x[3] * y[srcBLen - 4] */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x3 * c0)) >> 32); + /* acc1 += x[4] * y[srcBLen - 4] */ + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x0 * c0)) >> 32); + /* acc2 += x[5] * y[srcBLen - 4] */ + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x1 * c0)) >> 32); + /* acc3 += x[6] * y[srcBLen - 4] */ + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x2 * c0)) >> 32); + + + } while (--k); + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Read y[srcBLen - 5] sample */ + c0 = *py--; + /* Read x[7] sample */ + x3 = *px++; + + /* Perform the multiply-accumulates */ + /* acc0 += x[4] * y[srcBLen - 5] */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32); + /* acc1 += x[5] * y[srcBLen - 5] */ + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32); + /* acc2 += x[6] * y[srcBLen - 5] */ + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32); + /* acc3 += x[7] * y[srcBLen - 5] */ + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32); + + /* Reuse the present samples for the next MAC */ + x0 = x1; + x1 = x2; + x2 = x3; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q31_t) (acc0 << 1); + *pOut++ = (q31_t) (acc1 << 1); + *pOut++ = (q31_t) (acc2 << 1); + *pOut++ = (q31_t) (acc3 << 1); + + /* Increment the pointer pIn1 index, count by 4 */ + count += 4U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize2 % 0x4U; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum << 1; + + /* Increment MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum << 1; + + /* Increment MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + } + + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1] + * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2] + * .... + * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2] + * sum += x[srcALen-1] * y[srcBLen-1] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The blockSize3 variable holds the number of MAC operations performed */ + + /* Working pointer of inputA */ + pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U); + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + while (blockSize3 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = blockSize3 >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = blockSize3 % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum << 1; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pSrc2; + + /* Decrement loop counter */ + blockSize3--; + } +#endif /*defined (RISCV_VECTOR)*/ +} + +/** + @} end of Conv group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_conv_opt_q15.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_conv_opt_q15.c new file mode 100644 index 00000000..5f03a047 --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_conv_opt_q15.c @@ -0,0 +1,380 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_conv_opt_q15.c + * Description: Convolution of Q15 sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Conv + @{ + */ + +/** + @brief Convolution of Q15 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + Both inputs are in 1.15 format and multiplications yield a 2.30 result. + The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + This approach provides 33 guard bits and there is no risk of overflow. + The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format. + @remark + Refer to \ref riscv_conv_fast_q15() for a faster but less precise version of this function. + */ + +void riscv_conv_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2) +{ + q63_t acc0; /* Accumulators */ + const q15_t *pIn1; /* InputA pointer */ + const q15_t *pIn2; /* InputB pointer */ + q15_t *pOut = pDst; /* Output pointer */ + q15_t *pScr1 = pScratch1; /* Temporary pointer for scratch1 */ + q15_t *pScr2 = pScratch2; /* Temporary pointer for scratch1 */ + const q15_t *px; /* Intermediate inputA pointer */ + q15_t *py; /* Intermediate inputB pointer */ + uint32_t j, k, blkCnt; /* Loop counter */ + uint32_t tapCnt; /* Loop count */ + +#if defined (RISCV_MATH_LOOPUNROLL) + q63_t acc1, acc2, acc3; /* Accumulators */ + q31_t x1, x2, x3; /* Temporary variables to hold state and coefficient values */ + q31_t y1, y2; /* State variables */ +#endif + + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* Pointer to take end of scratch2 buffer */ + pScr2 = pScratch2 + srcBLen - 1; + + /* points to smaller length sequence */ + px = pIn2; + +#if defined (RISCV_MATH_LOOPUNROLL) && !defined (RISCV_VECTOR) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = srcBLen >> 2U; +#if __RISCV_XLEN == 64 + pScr2 -= 3; +#endif /* __RISCV_XLEN == 64 */ + /* Copy smaller length input sequence in reverse order into second scratch buffer */ + while (k > 0U) + { +#if __RISCV_XLEN == 64 + write_q15x4_da(&pScr2,read_q15x4_ia(&px)); +#else + /* copy second buffer in reversal manner */ + *pScr2-- = *px++; + *pScr2-- = *px++; + *pScr2-- = *px++; + *pScr2-- = *px++; +#endif /* __RISCV_XLEN == 64 */ + + /* Decrement loop counter */ + k--; + } +#if __RISCV_XLEN == 64 + pScr2 += 3; +#endif /* __RISCV_XLEN == 64 */ + /* Loop unrolling: Compute remaining outputs */ + k = srcBLen % 0x4U; + +#else + + /* Initialize k with number of samples */ + k = srcBLen; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ +#if defined (RISCV_VECTOR) + uint32_t vblkCnt = srcBLen; /* Loop counter */ + size_t l; + vint16m8_t vx; + ptrdiff_t bstride = -2; + for (; (l = vsetvl_e16m8(vblkCnt)) > 0; vblkCnt -= l) { + vx = vle16_v_i16m8(px, l); + px += l; + vsse16_v_i16m8(pScr2, bstride, vx, l); + pScr2 -= l; + } +#else + while (k > 0U) + { + /* copy second buffer in reversal manner for remaining samples */ + *pScr2-- = *px++; + + /* Decrement loop counter */ + k--; + } +#endif /*defined (RISCV_VECTOR)*/ + /* Initialze temporary scratch pointer */ + pScr1 = pScratch1; + + /* Assuming scratch1 buffer is aligned by 32-bit */ + /* Fill (srcBLen - 1U) zeros in scratch1 buffer */ + riscv_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update temporary scratch pointer */ + pScr1 += (srcBLen - 1U); + + /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */ + + /* Copy (srcALen) samples in scratch buffer */ + riscv_copy_q15(pIn1, pScr1, srcALen); + + /* Update pointers */ + pScr1 += srcALen; + + + /* Fill (srcBLen - 1U) zeros at end of scratch buffer */ + riscv_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update pointer */ + pScr1 += (srcBLen - 1U); + + /* Temporary pointer for scratch2 */ + py = pScratch2; + + + /* Initialization of pIn2 pointer */ + pIn2 = py; + +#if defined (RISCV_MATH_LOOPUNROLL) && !defined (RISCV_VECTOR) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (srcALen + srcBLen - 1U) >> 2; + + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch1; + + /* Clear Accumlators */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Read two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* Read next two samples from scratch1 buffer */ + x2 = read_q15x2_ia (&pScr1); + + tapCnt = (srcBLen) >> 2U; + + while (tapCnt > 0U) + { + + /* Read four samples from smaller buffer */ + y1 = read_q15x2_ia ((q15_t **) &pIn2); + y2 = read_q15x2_ia ((q15_t **) &pIn2); + + /* multiply and accumulate */ + acc0 = __SMLALD(x1, y1, acc0); + acc2 = __SMLALD(x2, y1, acc2); + + /* pack input data */ + x3 = __PKHBT(x2, x1, 0); + + /* multiply and accumulate */ + acc1 = __SMLALDX(x3, y1, acc1); + + /* Read next two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* multiply and accumulate */ + acc0 = __SMLALD(x2, y2, acc0); + acc2 = __SMLALD(x1, y2, acc2); + + /* pack input data */ + x3 = __PKHBT(x1, x2, 0); + + acc3 = __SMLALDX(x3, y1, acc3); + acc1 = __SMLALDX(x3, y2, acc1); + + x2 = read_q15x2_ia (&pScr1); + + x3 = __PKHBT(x2, x1, 0); + + acc3 = __SMLALDX(x3, y2, acc3); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Update scratch pointer for remaining samples of smaller length sequence */ + pScr1 -= 4U; + + /* apply same above for remaining samples of smaller length sequence */ + tapCnt = (srcBLen) & 3U; + + while (tapCnt > 0U) + { + /* accumulate the results */ + acc0 += (*pScr1++ * *pIn2); + acc1 += (*pScr1++ * *pIn2); + acc2 += (*pScr1++ * *pIn2); + acc3 += (*pScr1++ * *pIn2++); + + pScr1 -= 3U; + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* Store the results in the accumulators in the destination buffer. */ + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16)); + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16)); + + /* Initialization of inputB pointer */ + pIn2 = py; + + pScratch1 += 4U; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (srcALen + srcBLen - 1U) & 0x3; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = (srcALen + srcBLen - 1U); + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + /* Calculate convolution for remaining samples of Bigger length sequence */ + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch1; + + /* Clear Accumlators */ + acc0 = 0; +#if defined (RISCV_VECTOR) + uint32_t vblkCnt = srcBLen; /* Loop counter */ + size_t l; + vint16m4_t vx, vy; + vint32m1_t temp00m1; + // ptrdiff_t bstride = -2; + l = vsetvl_e32m1(1); + temp00m1 = vmv_v_x_i32m1(0, l); + for (; (l = vsetvl_e16m4(vblkCnt)) > 0; vblkCnt -= l) { + vx = vle16_v_i16m4(pScr1, l); + pScr1 += l; + vy = vle16_v_i16m4(pIn2, l); + pIn2 += l; + acc0 += vmv_x_s_i32m1_i32(vredsum_vs_i32m8_i32m1(temp00m1, vwmul_vv_i32m8(vx, vy, l), temp00m1, l)); + } +#else + tapCnt = (srcBLen) >> 1U; + + while (tapCnt > 0U) + { + + /* Read next two samples from scratch1 buffer */ + acc0 += (*pScr1++ * *pIn2++); + acc0 += (*pScr1++ * *pIn2++); + + /* Decrement loop counter */ + tapCnt--; + } + + tapCnt = (srcBLen) & 1U; + + /* apply same above for remaining samples of smaller length sequence */ + while (tapCnt > 0U) + { + + /* accumulate the results */ + acc0 += (*pScr1++ * *pIn2++); + + /* Decrement loop counter */ + tapCnt--; + } +#endif /*defined (RISCV_VECTOR)*/ + blkCnt--; + + /* The result is in 2.30 format. Convert to 1.15 with saturation. + Then store the output in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16)); + + /* Initialization of inputB pointer */ + pIn2 = py; + + pScratch1 += 1U; + } + +} + +/** + @} end of Conv group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_conv_opt_q7.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_conv_opt_q7.c new file mode 100644 index 00000000..822a0e81 --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_conv_opt_q7.c @@ -0,0 +1,409 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_conv_opt_q7.c + * Description: Convolution of Q7 sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Conv + @{ + */ + +/** + @brief Convolution of Q7 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 32-bit internal accumulator. + Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result. + The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format. + This approach provides 17 guard bits and there is no risk of overflow as long as max(srcALen, srcBLen)<131072. + The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and then saturated to 1.7 format. + */ + +void riscv_conv_opt_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2) +{ + q15_t *pScr1 = pScratch1; /* Temporary pointer for scratch */ + q15_t *pScr2 = pScratch2; /* Temporary pointer for scratch */ + q15_t x4; /* Temporary input variable */ + q15_t *py; /* Temporary input2 pointer */ + q31_t acc0, acc1, acc2, acc3; /* Accumulators */ + const q7_t *pIn1, *pIn2; /* InputA and inputB pointer */ + uint32_t j, k, blkCnt, tapCnt; /* Loop counter */ + q31_t x1, x2, x3, y1; /* Temporary input variables */ + const q7_t *px; /* Temporary input1 pointer */ + q7_t *pOut = pDst; /* Output pointer */ + q7_t out0, out1, out2, out3; /* Temporary variables */ + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } +// #if __RISCV_XLEN == 64 +// /* points to smaller length sequence */ +// px = pIn2 + srcBLen - 8; +// #else + /* points to smaller length sequence */ + px = pIn2 + srcBLen - 1; +// #endif /* __RISCV_XLEN == 64 */ +#if defined (RISCV_VECTOR) + uint32_t vblkCnt = srcBLen; /* Loop counter */ + size_t l; + vint16m8_t vx; + ptrdiff_t bstride = -1; + for (; (l = vsetvl_e8m4(vblkCnt)) > 0; vblkCnt -= l) { + vx = vwadd_vx_i16m8(vlse8_v_i8m4(px, bstride, l),0, l); + px -= l; + vse16_v_i16m8(pScr2, vx, l); + pScr2 += l; + } +#else + /* Apply loop unrolling and do 4 Copies simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling copies 4 data points at a time. + ** a second loop below copies for the remaining 1 to 3 samples. */ + while (k > 0U) + { +// #if __RISCV_XLEN == 64 +// write_q15x4_ia(&pScr2,read_q15x4_da((q15_t **)&px)); +// #else + /* copy second buffer in reversal manner */ + x4 = (q15_t) *px--; + *pScr2++ = x4; + x4 = (q15_t) *px--; + *pScr2++ = x4; + x4 = (q15_t) *px--; + *pScr2++ = x4; + x4 = (q15_t) *px--; + *pScr2++ = x4; +// #endif /* __RISCV_XLEN == 64 */ + + /* Decrement loop counter */ + k--; + } + + /* If the count is not a multiple of 4, copy remaining samples here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* copy second buffer in reversal manner for remaining samples */ + x4 = (q15_t) *px--; + *pScr2++ = x4; + + /* Decrement loop counter */ + k--; + } +#endif /*defined (RISCV_VECTOR)*/ + /* Fill (srcBLen - 1U) zeros in scratch buffer */ + riscv_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update temporary scratch pointer */ + pScr1 += (srcBLen - 1U); +#if defined (RISCV_VECTOR) + vblkCnt = srcALen; /* Loop counter */ + for (; (l = vsetvl_e8m4(vblkCnt)) > 0; vblkCnt -= l) { + vx = vwadd_vx_i16m8(vle8_v_i8m4(pIn1, l),0, l); + pIn1 += l; + vse16_v_i16m8(pScr1, vx, l); + pScr1 += l; + } +#else + /* Copy (srcALen) samples in scratch buffer */ + /* Apply loop unrolling and do 4 Copies simultaneously. */ + k = srcALen >> 2U; + + /* First part of the processing with loop unrolling copies 4 data points at a time. + ** a second loop below copies for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* copy second buffer in reversal manner */ + x4 = (q15_t) *pIn1++; + *pScr1++ = x4; + x4 = (q15_t) *pIn1++; + *pScr1++ = x4; + x4 = (q15_t) *pIn1++; + *pScr1++ = x4; + x4 = (q15_t) *pIn1++; + *pScr1++ = x4; + + /* Decrement loop counter */ + k--; + } + /* If the count is not a multiple of 4, copy remaining samples here. + ** No loop unrolling is used. */ + k = srcALen % 0x4U; + + while (k > 0U) + { + /* copy second buffer in reversal manner for remaining samples */ + x4 = (q15_t) * pIn1++; + *pScr1++ = x4; + + /* Decrement the loop counter */ + k--; + } +#endif /*defined (RISCV_VECTOR)*/ + /* Fill (srcBLen - 1U) zeros at end of scratch buffer */ + riscv_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update pointer */ + pScr1 += (srcBLen - 1U); + + /* Temporary pointer for scratch2 */ + py = pScratch2; + + /* Initialization of pIn2 pointer */ + pIn2 = (q7_t *) py; + + pScr2 = py; +#if defined (RISCV_VECTOR) + blkCnt = (srcALen + srcBLen - 1U); + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch1; + + /* Clear Accumlators */ + acc0 = 0; + + uint32_t vblkCnt = srcBLen; /* Loop counter */ + size_t l; + vint16m4_t vx, vy; + vint32m1_t temp00m1; + l = vsetvl_e32m1(1); + temp00m1 = vmv_v_x_i32m1(0, l); + for (; (l = vsetvl_e16m4(vblkCnt)) > 0; vblkCnt -= l) { + vx = vle16_v_i16m4(pScr1, l); + pScr1 += l; + vy = vle16_v_i16m4(pScr2, l); + pScr2 += l; + acc0 += vmv_x_s_i32m1_i32(vredsum_vs_i32m8_i32m1(temp00m1, vwmul_vv_i32m8(vx, vy, l), temp00m1, l)); + } + + blkCnt--; + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q7_t) (__SSAT(acc0 >> 7U, 8)); + + /* Initialization of inputB pointer */ + pScr2 = py; + + pScratch1 += 1U; + } +#else + /* Actual convolution process starts here */ + blkCnt = (srcALen + srcBLen - 1U) >> 2U; + + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch1; + + /* Clear Accumlators */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Read two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* Read next two samples from scratch1 buffer */ + x2 = read_q15x2_ia (&pScr1); + + tapCnt = (srcBLen) >> 2U; + + while (tapCnt > 0U) + { + /* Read four samples from smaller buffer */ + y1 = read_q15x2_ia (&pScr2); + + /* multiply and accumulate */ + acc0 = __SMLAD(x1, y1, acc0); + acc2 = __SMLAD(x2, y1, acc2); + + /* pack input data */ + x3 = __PKHBT(x2, x1, 0); + + /* multiply and accumulate */ + acc1 = __SMLADX(x3, y1, acc1); + + /* Read next two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* pack input data */ + x3 = __PKHBT(x1, x2, 0); + + acc3 = __SMLADX(x3, y1, acc3); + + /* Read four samples from smaller buffer */ + y1 = read_q15x2_ia (&pScr2); + + acc0 = __SMLAD(x2, y1, acc0); + + acc2 = __SMLAD(x1, y1, acc2); + + acc1 = __SMLADX(x3, y1, acc1); + + x2 = read_q15x2_ia (&pScr1); + + x3 = __PKHBT(x2, x1, 0); + + acc3 = __SMLADX(x3, y1, acc3); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Update scratch pointer for remaining samples of smaller length sequence */ + pScr1 -= 4U; + + /* apply same above for remaining samples of smaller length sequence */ + tapCnt = (srcBLen) & 3U; + + while (tapCnt > 0U) + { + /* accumulate the results */ + acc0 += (*pScr1++ * *pScr2); + acc1 += (*pScr1++ * *pScr2); + acc2 += (*pScr1++ * *pScr2); + acc3 += (*pScr1++ * *pScr2++); + + pScr1 -= 3U; + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* Store the result in the accumulator in the destination buffer. */ + out0 = (q7_t) (__SSAT(acc0 >> 7U, 8)); + out1 = (q7_t) (__SSAT(acc1 >> 7U, 8)); + out2 = (q7_t) (__SSAT(acc2 >> 7U, 8)); + out3 = (q7_t) (__SSAT(acc3 >> 7U, 8)); + + write_q7x4_ia (&pOut, __PACKq7(out0, out1, out2, out3)); + + /* Initialization of inputB pointer */ + pScr2 = py; + + pScratch1 += 4U; + } + + blkCnt = (srcALen + srcBLen - 1U) & 0x3; + + /* Calculate convolution for remaining samples of Bigger length sequence */ + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch1; + + /* Clear Accumlators */ + acc0 = 0; + + tapCnt = (srcBLen) >> 1U; + + while (tapCnt > 0U) + { + acc0 += (*pScr1++ * *pScr2++); + acc0 += (*pScr1++ * *pScr2++); + + /* Decrement loop counter */ + tapCnt--; + } + + tapCnt = (srcBLen) & 1U; + + /* apply same above for remaining samples of smaller length sequence */ + while (tapCnt > 0U) + { + /* accumulate the results */ + acc0 += (*pScr1++ * *pScr2++); + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q7_t) (__SSAT(acc0 >> 7U, 8)); + + /* Initialization of inputB pointer */ + pScr2 = py; + + pScratch1 += 1U; + } +#endif /*defined (RISCV_VECTOR)*/ +} + +/** + @} end of Conv group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_conv_partial_f32.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_conv_partial_f32.c new file mode 100644 index 00000000..38394eab --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_conv_partial_f32.c @@ -0,0 +1,746 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_conv_partial_f32.c + * Description: Partial convolution of floating-point sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @defgroup PartialConv Partial Convolution + + Partial Convolution is equivalent to Convolution except that a subset of the output samples is generated. + Each function has two additional arguments. + firstIndex specifies the starting index of the subset of output samples. + numPoints is the number of output samples to compute. + The function computes the output in the range + [firstIndex, ..., firstIndex+numPoints-1]. + The output array pDst contains numPoints values. + + The allowable range of output indices is [0 srcALen+srcBLen-2]. + If the requested subset does not fall in this range then the functions return RISCV_MATH_ARGUMENT_ERROR. + Otherwise the functions return RISCV_MATH_SUCCESS. + \note Refer to \ref riscv_conv_f32() for details on fixed point behavior. + + @par Fast Versions + Fast versions are supported for Q31 and Q15 of partial convolution. + Cycles for Fast versions are less compared to Q31 and Q15 of partial conv and the design requires + the input signals should be scaled down to avoid intermediate overflows. + + @par Opt Versions + Opt versions are supported for Q15 and Q7. Design uses internal scratch buffer for getting good optimisation. + These versions are optimised in cycles and consumes more memory (Scratch memory) compared to Q15 and Q7 versions of partial convolution + */ + +/** + @addtogroup PartialConv + @{ + */ + +/** + @brief Partial convolution of floating-point sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written + @param[in] firstIndex is the first output sample to start with + @param[in] numPoints is the number of output points to be computed + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_ARGUMENT_ERROR : requested subset is not in the range [0 srcALen+srcBLen-2] + */ + +riscv_status riscv_conv_partial_f32( + const float32_t * pSrcA, + uint32_t srcALen, + const float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst, + uint32_t firstIndex, + uint32_t numPoints) +{ +#if defined (RISCV_MATH_DSP) || defined (RISCV_VECTOR) + const float32_t *pIn1 = pSrcA; /* InputA pointer */ + const float32_t *pIn2 = pSrcB; /* InputB pointer */ + float32_t *pOut = pDst; /* Output pointer */ + const float32_t *px; /* Intermediate inputA pointer */ + const float32_t *py; /* Intermediate inputB pointer */ + const float32_t *pSrc1, *pSrc2; /* Intermediate pointers */ + float32_t sum; /* Accumulator */ + uint32_t j, k, count, blkCnt, check; + int32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + riscv_status status; /* Status of Partial convolution */ + +#if defined (RISCV_MATH_LOOPUNROLL) + float32_t acc0, acc1, acc2, acc3; /* Accumulator */ + float32_t x0, x1, x2, x3, c0; /* Temporary variables */ +#endif + + /* Check for range of output samples to be calculated */ + if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U)))) + { + /* Set status as RISCV_MATH_ARGUMENT_ERROR */ + status = RISCV_MATH_ARGUMENT_ERROR; + } + else + { + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* Conditions to check which loopCounter holds + * the first and last indices of the output samples to be calculated. */ + check = firstIndex + numPoints; + blockSize3 = ((int32_t)check > (int32_t)srcALen) ? (int32_t)check - (int32_t)srcALen : 0; + blockSize3 = ((int32_t)firstIndex > (int32_t)srcALen - 1) ? blockSize3 - (int32_t)firstIndex + (int32_t)srcALen : blockSize3; + blockSize1 = ((int32_t) srcBLen - 1) - (int32_t) firstIndex; + blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1U)) ? blockSize1 : (int32_t)numPoints) : 0; + blockSize2 = ((int32_t) check - blockSize3) - (blockSize1 + (int32_t) firstIndex); + blockSize2 = (blockSize2 > 0) ? blockSize2 : 0; + + /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */ + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* Set the output pointer to point to the firstIndex + * of the output sample to be calculated. */ + pOut = pDst + firstIndex; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[0] + * sum = x[0] * y[1] + x[1] * y[0] + * .... + * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed. + Since the partial convolution starts from firstIndex + Number of Macs to be performed is firstIndex + 1 */ + count = 1U + firstIndex; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc1 = pIn2 + firstIndex; + py = pSrc1; + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* The first stage starts here */ + while (blockSize1 > 0) + { + /* Accumulator is made zero for every iteration */ + sum = 0.0f; + +#if defined (RISCV_MATH_LOOPUNROLL) && !defined (RISCV_VECTOR) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + + while (k > 0U) + { + /* x[0] * y[srcBLen - 1] */ + sum += *px++ * *py--; + + /* x[1] * y[srcBLen - 2] */ + sum += *px++ * *py--; + + /* x[2] * y[srcBLen - 3] */ + sum += *px++ * *py--; + + /* x[3] * y[srcBLen - 4] */ + sum += *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize k with number of samples */ + k = count; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ +#if defined (RISCV_VECTOR) + uint32_t vblkCnt = count; /* Loop counter */ + size_t l; + vfloat32m8_t vx, vy; + vfloat32m1_t temp00m1; + ptrdiff_t bstride = -4; + l = vsetvl_e32m1(1); + temp00m1 = vfmv_v_f_f32m1(0, l); + for (; (l = vsetvl_e32m8(vblkCnt)) > 0; vblkCnt -= l) { + vx = vle32_v_f32m8(px, l); + px += l; + vy = vlse32_v_f32m8(py, bstride, l); + py -= l; + sum += vfmv_f_s_f32m1_f32(vfredsum_vs_f32m8_f32m1(temp00m1, vfmul_vv_f32m8(vx, vy, l), temp00m1, l)); + } +#else + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += *px++ * *py--; + + /* Decrement loop counter */ + k--; + } +#endif /*defined (RISCV_VECTOR)*/ + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum; + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = ++pSrc1; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0] + * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0] + * .... + * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0] + */ + + /* Working pointer of inputA */ + if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0) + { + pSrc1 = pIn1 + firstIndex - srcBLen + 1; + } + else + { + pSrc1 = pIn1; + } + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* count is index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ +#if defined (RISCV_VECTOR) + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.0f; + + /* srcBLen number of MACS should be performed */ + uint32_t vblkCnt = srcBLen; /* Loop counter */ + size_t l; + vfloat32m8_t vx, vy; + vfloat32m1_t temp00m1; + ptrdiff_t bstride = -4; + l = vsetvl_e32m1(1); + temp00m1 = vfmv_v_f_f32m1(0, l); + for (; (l = vsetvl_e32m8(vblkCnt)) > 0; vblkCnt -= l) { + vx = vle32_v_f32m8(px, l); + px += l; + vy = vlse32_v_f32m8(py, bstride, l); + py -= l; + sum += vfmv_f_s_f32m1_f32(vfredsum_vs_f32m8_f32m1(temp00m1, vfmul_vv_f32m8(vx, vy, l), temp00m1, l)); + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum; + + /* Increment the MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement the loop counter */ + blkCnt--; + } +#else + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = ((uint32_t) blockSize2 >> 2U); + + while (blkCnt > 0U) + { + /* Set all accumulators to zero */ + acc0 = 0.0f; + acc1 = 0.0f; + acc2 = 0.0f; + acc3 = 0.0f; + + /* read x[0], x[1], x[2] samples */ + x0 = *px++; + x1 = *px++; + x2 = *px++; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + do + { + /* Read y[srcBLen - 1] sample */ + c0 = *py--; + /* Read x[3] sample */ + x3 = *px++; + + /* Perform the multiply-accumulate */ + /* acc0 += x[0] * y[srcBLen - 1] */ + acc0 += x0 * c0; + /* acc1 += x[1] * y[srcBLen - 1] */ + acc1 += x1 * c0; + /* acc2 += x[2] * y[srcBLen - 1] */ + acc2 += x2 * c0; + /* acc3 += x[3] * y[srcBLen - 1] */ + acc3 += x3 * c0; + + /* Read y[srcBLen - 2] sample */ + c0 = *py--; + /* Read x[4] sample */ + x0 = *px++; + + /* Perform the multiply-accumulate */ + /* acc0 += x[1] * y[srcBLen - 2] */ + acc0 += x1 * c0; + /* acc1 += x[2] * y[srcBLen - 2] */ + acc1 += x2 * c0; + /* acc2 += x[3] * y[srcBLen - 2] */ + acc2 += x3 * c0; + /* acc3 += x[4] * y[srcBLen - 2] */ + acc3 += x0 * c0; + + /* Read y[srcBLen - 3] sample */ + c0 = *py--; + /* Read x[5] sample */ + x1 = *px++; + + /* Perform the multiply-accumulate */ + /* acc0 += x[2] * y[srcBLen - 3] */ + acc0 += x2 * c0; + /* acc1 += x[3] * y[srcBLen - 2] */ + acc1 += x3 * c0; + /* acc2 += x[4] * y[srcBLen - 2] */ + acc2 += x0 * c0; + /* acc3 += x[5] * y[srcBLen - 2] */ + acc3 += x1 * c0; + + /* Read y[srcBLen - 4] sample */ + c0 = *py--; + /* Read x[6] sample */ + x2 = *px++; + + /* Perform the multiply-accumulate */ + /* acc0 += x[3] * y[srcBLen - 4] */ + acc0 += x3 * c0; + /* acc1 += x[4] * y[srcBLen - 4] */ + acc1 += x0 * c0; + /* acc2 += x[5] * y[srcBLen - 4] */ + acc2 += x1 * c0; + /* acc3 += x[6] * y[srcBLen - 4] */ + acc3 += x2 * c0; + + } while (--k); + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Read y[srcBLen - 5] sample */ + c0 = *py--; + /* Read x[7] sample */ + x3 = *px++; + + /* Perform the multiply-accumulates */ + /* acc0 += x[4] * y[srcBLen - 5] */ + acc0 += x0 * c0; + /* acc1 += x[5] * y[srcBLen - 5] */ + acc1 += x1 * c0; + /* acc2 += x[6] * y[srcBLen - 5] */ + acc2 += x2 * c0; + /* acc3 += x[7] * y[srcBLen - 5] */ + acc3 += x3 * c0; + + /* Reuse the present samples for the next MAC */ + x0 = x1; + x1 = x2; + x2 = x3; + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = acc0; + *pOut++ = acc1; + *pOut++ = acc2; + *pOut++ = acc3; + + /* Increment the pointer pIn1 index, count by 4 */ + count += 4U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (uint32_t) blockSize2 % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize2; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.0f; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = srcBLen >> 2U; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum += *px++ * *py--; + sum += *px++ * *py--; + sum += *px++ * *py--; + sum += *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = srcBLen % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = srcBLen; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum; + + /* Increment MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = (uint32_t) blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.0f; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum; + + /* Increment the MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement the loop counter */ + blkCnt--; + } + } +#endif /*defined (RISCV_VECTOR)*/ + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1] + * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2] + * .... + * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2] + * sum += x[srcALen-1] * y[srcBLen-1] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The blockSize3 variable holds the number of MAC operations performed */ + count = srcBLen - 1U; + + /* Working pointer of inputA */ + if (firstIndex > srcALen) + { + pSrc1 = (pIn1 + firstIndex) - (srcBLen - 1U); + } + else + { + pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U); + } + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + while (blockSize3 > 0) + { + /* Accumulator is made zero for every iteration */ + sum = 0.0f; + +#if defined (RISCV_MATH_LOOPUNROLL) && !defined (RISCV_VECTOR) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + + while (k > 0U) + { + /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */ + sum += *px++ * *py--; + + /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */ + sum += *px++ * *py--; + + /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */ + sum += *px++ * *py--; + + /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */ + sum += *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = count; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ +#if defined (RISCV_VECTOR) + uint32_t vblkCnt = blockSize3; /* Loop counter */ + size_t l; + vfloat32m8_t vx, vy; + vfloat32m1_t temp00m1; + ptrdiff_t bstride = -4; + l = vsetvl_e32m1(1); + temp00m1 = vfmv_v_f_f32m1(0, l); + for (; (l = vsetvl_e32m8(vblkCnt)) > 0; vblkCnt -= l) { + vx = vle32_v_f32m8(px, l); + px += l; + vy = vlse32_v_f32m8(py, bstride, l); + py -= l; + sum += vfmv_f_s_f32m1_f32(vfredsum_vs_f32m8_f32m1(temp00m1, vfmul_vv_f32m8(vx, vy, l), temp00m1, l)); + } +#else + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* sum += x[srcALen-1] * y[srcBLen-1] */ + sum += *px++ * *py--; + + /* Decrement loop counter */ + k--; + } +#endif /*defined (RISCV_VECTOR)*/ + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pSrc2; + + /* Decrement MAC count */ + count--; + + /* Decrement the loop counter */ + blockSize3--; + } + + /* Set status as RISCV_MATH_SUCCESS */ + status = RISCV_MATH_SUCCESS; + } + + /* Return to application */ + return (status); + +#else +/* alternate version for CM0_FAMILY */ + + const float32_t *pIn1 = pSrcA; /* InputA pointer */ + const float32_t *pIn2 = pSrcB; /* InputB pointer */ + float32_t sum; /* Accumulator */ + uint32_t i, j; /* Loop counters */ + riscv_status status; /* Status of Partial convolution */ + /* Check for range of output samples to be calculated */ + if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U)))) + { + /* Set status as RISCV_MATH_ARGUMENT_ERROR */ + status = RISCV_MATH_ARGUMENT_ERROR; + } + else + { + /* Loop to calculate convolution for output length number of values */ + for (i = firstIndex; i <= (firstIndex + numPoints - 1); i++) + { + /* Initialize sum with zero to carry on MAC operations */ + sum = 0.0f; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0U; j <= i; j++) + { + /* Check the array limitations */ + if (((i - j) < srcBLen) && (j < srcALen)) + { + /* z[i] += x[i-j] * y[j] */ + sum += ( pIn1[j] * pIn2[i - j]); + } + } + + /* Store the output in the destination buffer */ + pDst[i] = sum; + } + + /* Set status as RISCV_SUCCESS */ + status = RISCV_MATH_SUCCESS; + } + + /* Return to application */ + return (status); + +#endif /* defined(RISCV_MATH_DSP) */ +} + +/** + @} end of PartialConv group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_conv_partial_fast_opt_q15.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_conv_partial_fast_opt_q15.c new file mode 100644 index 00000000..261a484e --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_conv_partial_fast_opt_q15.c @@ -0,0 +1,386 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_conv_partial_fast_opt_q15.c + * Description: Fast Q15 Partial convolution + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup PartialConv + @{ + */ + +/** + @brief Partial convolution of Q15 sequences (fast version). + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written + @param[in] firstIndex is the first output sample to start with + @param[in] numPoints is the number of output points to be computed + @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2 + @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen) + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_ARGUMENT_ERROR : requested subset is not in the range [0 srcALen+srcBLen-2] + + @remark + Refer to \ref riscv_conv_partial_q15() for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion. + */ + +riscv_status riscv_conv_partial_fast_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2) +{ +#if defined (RISCV_VECTOR) + return(riscv_conv_partial_opt_q15(pSrcA, srcALen, pSrcB, srcBLen, pDst, firstIndex, numPoints, pScratch1, pScratch2)); +#else + q15_t *pOut = pDst; /* Output pointer */ + q15_t *pScr1 = pScratch1; /* Temporary pointer for scratch1 */ + q15_t *pScr2 = pScratch2; /* Temporary pointer for scratch1 */ + q31_t acc0; /* Accumulator */ + const q15_t *pIn1; /* InputA pointer */ + const q15_t *pIn2; /* InputB pointer */ + const q15_t *px; /* Intermediate inputA pointer */ + q15_t *py; /* Intermediate inputB pointer */ + uint32_t j, k, blkCnt; /* Loop counter */ + uint32_t tapCnt; /* Loop count */ + riscv_status status; /* Status variable */ + q31_t x1; /* Temporary variables to hold state and coefficient values */ + q31_t y1; /* State variables */ + +#if defined (RISCV_MATH_LOOPUNROLL) + q31_t acc1, acc2, acc3; /* Accumulator */ + q31_t x2, x3; /* Temporary variables to hold state and coefficient values */ + q31_t y2; /* State variables */ +#endif + + /* Check for range of output samples to be calculated */ + if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U)))) + { + /* Set status as RISCV_MATH_ARGUMENT_ERROR */ + status = RISCV_MATH_ARGUMENT_ERROR; + } + else + { + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* Temporary pointer for scratch2 */ + py = pScratch2; + +#if __RISCV_XLEN == 64 + /* Pointer to take end of scratch2 buffer */ + pScr2 = pScratch2 + srcBLen - 4; +#else + /* Pointer to take end of scratch2 buffer */ + pScr2 = pScratch2 + srcBLen - 1; +#endif /* __RISCV_XLEN == 64 */ + + /* points to smaller length sequence */ + px = pIn2; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = srcBLen >> 2U; + + /* Copy smaller length input sequence in reverse order into second scratch buffer */ + while (k > 0U) + { +#if __RISCV_XLEN == 64 + write_q15x4_da(&pScr2,read_q15x4_ia((q15_t **)&px)); +#else + /* copy second buffer in reversal manner */ + *pScr2-- = *px++; + *pScr2-- = *px++; + *pScr2-- = *px++; + *pScr2-- = *px++; +#endif /* __RISCV_XLEN == 64 */ + + /* Decrement loop counter */ + k--; + } +#if __RISCV_XLEN == 64 + pScr2 += 3; +#endif /* __RISCV_XLEN == 64 */ + /* Loop unrolling: Compute remaining outputs */ + k = srcBLen % 0x4U; + +#else + + /* Initialize k with number of samples */ + k = srcBLen; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* copy second buffer in reversal manner for remaining samples */ + *pScr2-- = *px++; + + /* Decrement loop counter */ + k--; + } + + /* Initialze temporary scratch pointer */ + pScr1 = pScratch1; + + /* Assuming scratch1 buffer is aligned by 32-bit */ + /* Fill (srcBLen - 1U) zeros in scratch buffer */ + riscv_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update temporary scratch pointer */ + pScr1 += (srcBLen - 1U); + + /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */ + + /* Copy (srcALen) samples in scratch buffer */ + riscv_copy_q15(pIn1, pScr1, srcALen); + + /* Update pointers */ + pScr1 += srcALen; + + /* Fill (srcBLen - 1U) zeros at end of scratch buffer */ + riscv_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update pointer */ + pScr1 += (srcBLen - 1U); + + /* Initialization of pIn2 pointer */ + pIn2 = py; + + pScratch1 += firstIndex; + + pOut = pDst + firstIndex; + + /* Actual convolution process starts here */ + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (numPoints) >> 2; + + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch1; + + /* Clear Accumlators */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Read two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* Read next two samples from scratch1 buffer */ + x2 = read_q15x2_ia (&pScr1); + + tapCnt = (srcBLen) >> 2U; + + while (tapCnt > 0U) + { + + /* Read four samples from smaller buffer */ + y1 = read_q15x2_ia ((q15_t **) &pIn2); + y2 = read_q15x2_ia ((q15_t **) &pIn2); + + /* multiply and accumulate */ + acc0 = __SMLAD(x1, y1, acc0); + acc2 = __SMLAD(x2, y1, acc2); + + /* pack input data */ + x3 = __PKHBT(x2, x1, 0); + + /* multiply and accumulate */ + acc1 = __SMLADX(x3, y1, acc1); + + /* Read next two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* multiply and accumulate */ + acc0 = __SMLAD(x2, y2, acc0); + acc2 = __SMLAD(x1, y2, acc2); + + /* pack input data */ + x3 = __PKHBT(x1, x2, 0); + + acc3 = __SMLADX(x3, y1, acc3); + acc1 = __SMLADX(x3, y2, acc1); + + x2 = read_q15x2_ia (&pScr1); + + x3 = __PKHBT(x2, x1, 0); + + /* multiply and accumulate */ + acc3 = __SMLADX(x3, y2, acc3); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Update scratch pointer for remaining samples of smaller length sequence */ + pScr1 -= 4U; + + /* apply same above for remaining samples of smaller length sequence */ + tapCnt = (srcBLen) & 3U; + + while (tapCnt > 0U) + { + /* accumulate the results */ + acc0 += (*pScr1++ * *pIn2); + acc1 += (*pScr1++ * *pIn2); + acc2 += (*pScr1++ * *pIn2); + acc3 += (*pScr1++ * *pIn2++); + + pScr1 -= 3U; + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* Store the results in the accumulators in the destination buffer. */ + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16)); + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16)); + + /* Initialization of inputB pointer */ + pIn2 = py; + + pScratch1 += 4U; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numPoints & 0x3; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numPoints; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + /* Calculate convolution for remaining samples of Bigger length sequence */ + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch1; + + /* Clear Accumlators */ + acc0 = 0; + + tapCnt = (srcBLen) >> 1U; + + while (tapCnt > 0U) + { + /* Read next two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* Read two samples from smaller buffer */ + y1 = read_q15x2_ia ((q15_t **) &pIn2); + + /* multiply and accumulate */ + acc0 = __SMLAD(x1, y1, acc0); + + /* Decrement loop counter */ + tapCnt--; + } + + tapCnt = (srcBLen) & 1U; + + /* apply same above for remaining samples of smaller length sequence */ + while (tapCnt > 0U) + { + /* accumulate the results */ + acc0 += (*pScr1++ * *pIn2++); + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* The result is in 2.30 format. Convert to 1.15 with saturation. + ** Then store the output in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16)); + + /* Initialization of inputB pointer */ + pIn2 = py; + + pScratch1 += 1U; + + } + + /* Set status as RISCV_MATH_SUCCESS */ + status = RISCV_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +#endif /*defined (RISCV_VECTOR)*/ +} + +/** + @} end of PartialConv group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_conv_partial_fast_q15.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_conv_partial_fast_q15.c new file mode 100644 index 00000000..77a066b3 --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_conv_partial_fast_q15.c @@ -0,0 +1,705 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_conv_partial_fast_q15.c + * Description: Fast Q15 Partial convolution + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup PartialConv + @{ + */ + +/** + @brief Partial convolution of Q15 sequences (fast version). + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written + @param[in] firstIndex is the first output sample to start with + @param[in] numPoints is the number of output points to be computed + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_ARGUMENT_ERROR : requested subset is not in the range [0 srcALen+srcBLen-2] + @remark + Refer to \ref riscv_conv_partial_q15() for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion. + */ + +riscv_status riscv_conv_partial_fast_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints) +{ +#if defined (RISCV_VECTOR) + return(riscv_conv_partial_q15(pSrcA, srcALen, pSrcB, srcBLen, pDst, firstIndex, numPoints)); +#else + const q15_t *pIn1; /* InputA pointer */ + const q15_t *pIn2; /* InputB pointer */ + q15_t *pOut = pDst; /* Output pointer */ + q31_t sum, acc0, acc1, acc2, acc3; /* Accumulator */ + const q15_t *px; /* Intermediate inputA pointer */ + const q15_t *py; /* Intermediate inputB pointer */ + const q15_t *pSrc1, *pSrc2; /* Intermediate pointers */ + q31_t x0, x1, x2, x3, c0; /* Temporary input variables */ + uint32_t j, k, count, blkCnt, check; + int32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + riscv_status status; /* Status of Partial convolution */ + + /* Check for range of output samples to be calculated */ + if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U)))) + { + /* Set status as RISCV_MATH_ARGUMENT_ERROR */ + status = RISCV_MATH_ARGUMENT_ERROR; + } + else + { + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* Conditions to check which loopCounter holds + * the first and last indices of the output samples to be calculated. */ + check = firstIndex + numPoints; + blockSize3 = ((int32_t)check > (int32_t)srcALen) ? (int32_t)check - (int32_t)srcALen : 0; + blockSize3 = ((int32_t)firstIndex > (int32_t)srcALen - 1) ? blockSize3 - (int32_t)firstIndex + (int32_t)srcALen : blockSize3; + blockSize1 = ((int32_t) srcBLen - 1) - (int32_t) firstIndex; + blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1U)) ? blockSize1 : (int32_t) numPoints) : 0; + blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) + (int32_t) firstIndex); + blockSize2 = (blockSize2 > 0) ? blockSize2 : 0; + + /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */ + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* Set the output pointer to point to the firstIndex + * of the output sample to be calculated. */ + pOut = pDst + firstIndex; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[0] + * sum = x[0] * y[1] + x[1] * y[0] + * .... + * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed. + Since the partial convolution starts from firstIndex + Number of Macs to be performed is firstIndex + 1 */ + count = 1U + firstIndex; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + firstIndex; + py = pSrc2; + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* For loop unrolling by 4, this stage is divided into two. */ + /* First part of this stage computes the MAC operations less than 4 */ + /* Second part of this stage computes the MAC operations greater than or equal to 4 */ + + /* The first part of the stage starts here */ + while ((count < 4U) && (blockSize1 > 0)) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Loop over number of MAC operations between + * inputA samples and inputB samples */ + k = count; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum = __SMLAD(*px++, *py--, sum); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (sum >> 15); + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = ++pSrc2; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* The second part of the stage starts here */ + /* The internal loop, over count, is unrolled by 4 */ + /* To, read the last two inputB samples using SIMD: + * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */ + py = py - 1; + + while (blockSize1 > 0) + { + /* Accumulator is made zero for every iteration */ + sum = 0; +#if defined RISCV_MATH_DSP && __RISCV_XLEN == 64 + py -= 2; +#endif /* RISCV_MATH_DSP && __RISCV_XLEN == 64 */ + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = count >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { +#if defined RISCV_MATH_DSP && __RISCV_XLEN == 64 + sum = __RV_KMAXDA(sum, read_q7x8_ia ((q15_t **) &px), read_q7x8_da ((q15_t **) &py)); +#else + /* Perform the multiply-accumulate */ + /* x[0], x[1] are multiplied with y[srcBLen - 1], y[srcBLen - 2] respectively */ + sum = __SMLADX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum); + /* x[2], x[3] are multiplied with y[srcBLen - 3], y[srcBLen - 4] respectively */ + sum = __SMLADX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum); +#endif /* RISCV_MATH_DSP && __RISCV_XLEN == 64 */ + /* Decrement loop counter */ + k--; + } +#if defined RISCV_MATH_DSP && __RISCV_XLEN == 64 + py += 2; +#endif /* RISCV_MATH_DSP && __RISCV_XLEN == 64 */ + /* For the next MAC operations, the pointer py is used without SIMD + So, py is incremented by 1 */ + py = py + 1U; + + /* If the count is not a multiple of 4, compute any remaining MACs here. + No loop unrolling is used. */ + k = count % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum = __SMLAD(*px++, *py--, sum); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (sum >> 15); + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = ++pSrc2 - 1U; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0] + * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0] + * .... + * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0] + */ + + /* Working pointer of inputA */ + if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0) + { + pSrc1 = pIn1 + firstIndex - srcBLen + 1; + } + else + { + pSrc1 = pIn1; + } + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* count is the index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = ((uint32_t) blockSize2 >> 2U); + + while (blkCnt > 0U) + { + py = py - 1U; + + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + + /* read x[0], x[1] samples */ + x0 = read_q15x2 ((q15_t *) px); + /* read x[1], x[2] samples */ + x1 = read_q15x2 ((q15_t *) px + 1); + px += 2U; + + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + do + { + /* Read the last two inputB samples using SIMD: + * y[srcBLen - 1] and y[srcBLen - 2] */ + c0 = read_q15x2_da ((q15_t **) &py); + + /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */ + acc0 = __SMLADX(x0, c0, acc0); + + /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */ + acc1 = __SMLADX(x1, c0, acc1); + + /* Read x[2], x[3] */ + x2 = read_q15x2 ((q15_t *) px); + + /* Read x[3], x[4] */ + x3 = read_q15x2 ((q15_t *) px + 1); + + /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */ + acc2 = __SMLADX(x2, c0, acc2); + + /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */ + acc3 = __SMLADX(x3, c0, acc3); + + /* Read y[srcBLen - 3] and y[srcBLen - 4] */ + c0 = read_q15x2_da ((q15_t **) &py); + + /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */ + acc0 = __SMLADX(x2, c0, acc0); + + /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */ + acc1 = __SMLADX(x3, c0, acc1); + + /* Read x[4], x[5] */ + x0 = read_q15x2 ((q15_t *) px + 2); + + /* Read x[5], x[6] */ + x1 = read_q15x2 ((q15_t *) px + 3); + px += 4U; + + /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */ + acc2 = __SMLADX(x0, c0, acc2); + + /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */ + acc3 = __SMLADX(x1, c0, acc3); + + } while (--k); + + /* For the next MAC operations, SIMD is not used + So, the 16 bit pointer if inputB, py is updated */ + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + No loop unrolling is used. */ + k = srcBLen % 0x4U; + + if (k == 1U) + { + /* Read y[srcBLen - 5] */ + c0 = *(py + 1); + c0 = c0 & 0x0000FFFF; + + /* Read x[7] */ + x3 = read_q15x2 ((q15_t *) px); + px++; + + /* Perform the multiply-accumulate */ + acc0 = __SMLAD (x0, c0, acc0); + acc1 = __SMLAD (x1, c0, acc1); + acc2 = __SMLADX(x1, c0, acc2); + acc3 = __SMLADX(x3, c0, acc3); + } + + if (k == 2U) + { + /* Read y[srcBLen - 5], y[srcBLen - 6] */ + c0 = read_q15x2 ((q15_t *) py); + + /* Read x[7], x[8] */ + x3 = read_q15x2 ((q15_t *) px); + + /* Read x[9] */ + x2 = read_q15x2 ((q15_t *) px + 1); + px += 2U; + + /* Perform the multiply-accumulate */ + acc0 = __SMLADX(x0, c0, acc0); + acc1 = __SMLADX(x1, c0, acc1); + acc2 = __SMLADX(x3, c0, acc2); + acc3 = __SMLADX(x2, c0, acc3); + } + + if (k == 3U) + { + /* Read y[srcBLen - 5], y[srcBLen - 6] */ + c0 = read_q15x2 ((q15_t *) py); + + /* Read x[7], x[8] */ + x3 = read_q15x2 ((q15_t *) px); + + /* Read x[9] */ + x2 = read_q15x2 ((q15_t *) px + 1); + + /* Perform the multiply-accumulate */ + acc0 = __SMLADX(x0, c0, acc0); + acc1 = __SMLADX(x1, c0, acc1); + acc2 = __SMLADX(x3, c0, acc2); + acc3 = __SMLADX(x2, c0, acc3); + + c0 = *(py-1); + c0 = c0 & 0x0000FFFF; + + /* Read x[10] */ + x3 = read_q15x2 ((q15_t *) px + 2); + px += 3U; + + /* Perform the multiply-accumulates */ + acc0 = __SMLADX(x1, c0, acc0); + acc1 = __SMLAD (x2, c0, acc1); + acc2 = __SMLADX(x2, c0, acc2); + acc3 = __SMLADX(x3, c0, acc3); + } + + /* Store the results in the accumulators in the destination buffer. */ + write_q15x2_ia (&pOut, __PKHBT(acc0 >> 15, acc1 >> 15, 16)); + write_q15x2_ia (&pOut, __PKHBT(acc2 >> 15, acc3 >> 15, 16)); + + /* Increment the pointer pIn1 index, count by 4 */ + count += 4U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here. + No loop unrolling is used. */ + blkCnt = (uint32_t) blockSize2 % 0x4U; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum += ((q31_t) *px++ * *py--); + sum += ((q31_t) *px++ * *py--); + sum += ((q31_t) *px++ * *py--); + sum += ((q31_t) *px++ * *py--); + + /* Decrement loop counter */ + k--; + } + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum += ((q31_t) *px++ * *py--); + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (sum >> 15); + + /* Increment the pointer pIn1 index, count by 1 */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = (uint32_t) blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += ((q31_t) *px++ * *py--); + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (sum >> 15); + + /* Increment the MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1] + * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2] + * .... + * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2] + * sum += x[srcALen-1] * y[srcBLen-1] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = srcBLen - 1U; + + /* Working pointer of inputA */ + if (firstIndex > srcALen) + { + pSrc1 = (pIn1 + firstIndex) - (srcBLen - 1U); + } + else + { + pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U); + } + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + pIn2 = pSrc2 - 1U; + py = pIn2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + /* For loop unrolling by 4, this stage is divided into two. */ + /* First part of this stage computes the MAC operations greater than 4 */ + /* Second part of this stage computes the MAC operations less than or equal to 4 */ + + /* The first part of the stage starts here */ + j = count >> 2U; + + while ((j > 0U) && (blockSize3 > 0)) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = count >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* x[srcALen - srcBLen + 1], x[srcALen - srcBLen + 2] are multiplied + * with y[srcBLen - 1], y[srcBLen - 2] respectively */ + sum = __SMLADX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum); + /* x[srcALen - srcBLen + 3], x[srcALen - srcBLen + 4] are multiplied + * with y[srcBLen - 3], y[srcBLen - 4] respectively */ + sum = __SMLADX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum); + + /* Decrement loop counter */ + k--; + } + + /* For the next MAC operations, the pointer py is used without SIMD + So, py is incremented by 1 */ + py = py + 1U; + + /* If the count is not a multiple of 4, compute any remaining MACs here. + No loop unrolling is used. */ + k = count % 0x4U; + + while (k > 0U) + { + /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */ + sum = __SMLAD(*px++, *py--, sum); + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (sum >> 15); + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pIn2; + + /* Decrement the MAC count */ + count--; + + /* Decrement the loop counter */ + blockSize3--; + + j--; + } + + /* The second part of the stage starts here */ + /* SIMD is not used for the next MAC operations, + * so pointer py is updated to read only one sample at a time */ + py = py + 1U; + + while (blockSize3 > 0) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = count; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + /* sum += x[srcALen-1] * y[srcBLen-1] */ + sum = __SMLAD(*px++, *py--, sum); + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (sum >> 15); + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pSrc2; + + /* Decrement the MAC count */ + count--; + + /* Decrement the loop counter */ + blockSize3--; + } + + /* Set status as RISCV_MATH_SUCCESS */ + status = RISCV_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +#endif /*defined (RISCV_VECTOR)*/ +} + +/** + @} end of PartialConv group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_conv_partial_fast_q31.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_conv_partial_fast_q31.c new file mode 100644 index 00000000..b3bbd86f --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_conv_partial_fast_q31.c @@ -0,0 +1,629 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_conv_partial_fast_q31.c + * Description: Fast Q31 Partial convolution + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup PartialConv + @{ + */ + +/** + @brief Partial convolution of Q31 sequences (fast version). + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written + @param[in] firstIndex is the first output sample to start with + @param[in] numPoints is the number of output points to be computed + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_ARGUMENT_ERROR : requested subset is not in the range [0 srcALen+srcBLen-2] + + @remark + Refer to \ref riscv_conv_partial_q31() for a slower implementation of this function which uses a 64-bit accumulator to provide higher precision. + */ + +riscv_status riscv_conv_partial_fast_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints) +{ +#if defined (RISCV_VECTOR) +return(riscv_conv_partial_q31(pSrcA, srcALen, pSrcB, srcBLen, pDst, firstIndex, numPoints)); +#else + const q31_t *pIn1; /* InputA pointer */ + const q31_t *pIn2; /* InputB pointer */ + q31_t *pOut = pDst; /* Output pointer */ + const q31_t *px; /* Intermediate inputA pointer */ + const q31_t *py; /* Intermediate inputB pointer */ + const q31_t *pSrc1, *pSrc2; /* Intermediate pointers */ + q31_t sum; /* Accumulators */ + uint32_t j, k, count, check, blkCnt; + int32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + riscv_status status; /* Status of Partial convolution */ + +#if defined (RISCV_MATH_LOOPUNROLL) + q31_t acc0, acc1, acc2, acc3; /* Accumulators */ + q31_t x0, x1, x2, x3, c0; +#endif + + /* Check for range of output samples to be calculated */ + if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U)))) + { + /* Set status as RISCV_MATH_ARGUMENT_ERROR */ + status = RISCV_MATH_ARGUMENT_ERROR; + } + else + { + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* Conditions to check which loopCounter holds + * the first and last indices of the output samples to be calculated. */ + check = firstIndex + numPoints; + blockSize3 = ((int32_t)check > (int32_t)srcALen) ? (int32_t)check - (int32_t)srcALen : 0; + blockSize3 = ((int32_t)firstIndex > (int32_t)srcALen - 1) ? blockSize3 - (int32_t)firstIndex + (int32_t)srcALen : blockSize3; + blockSize1 = ((int32_t) srcBLen - 1) - (int32_t) firstIndex; + blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1U)) ? blockSize1 : (int32_t)numPoints) : 0; + blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) + (int32_t) firstIndex); + blockSize2 = (blockSize2 > 0) ? blockSize2 : 0; + + /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */ + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* Set the output pointer to point to the firstIndex + * of the output sample to be calculated. */ + pOut = pDst + firstIndex; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[0] + * sum = x[0] * y[1] + x[1] * y[0] + * .... + * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed. + Since the partial convolution starts from firstIndex + Number of Macs to be performed is firstIndex + 1 */ + count = 1U + firstIndex; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + firstIndex; + py = pSrc2; + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* The first stage starts here */ + while (blockSize1 > 0) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + + while (k > 0U) + { + /* x[0] * y[srcBLen - 1] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* x[1] * y[srcBLen - 2] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* x[2] * y[srcBLen - 3] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* x[3] * y[srcBLen - 4] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize k with number of samples */ + k = count; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum << 1; + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = ++pSrc2; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0] + * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0] + * .... + * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0] + */ + + /* Working pointer of inputA */ + if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0) + { + pSrc1 = pIn1 + firstIndex - srcBLen + 1; + } + else + { + pSrc1 = pIn1; + } + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* count is index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = ((uint32_t) blockSize2 >> 2U); + + while (blkCnt > 0U) + { + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* read x[0], x[1], x[2] samples */ + x0 = *px++; + x1 = *px++; + x2 = *px++; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + do + { + /* Read y[srcBLen - 1] sample */ + c0 = *py--; + /* Read x[3] sample */ + x3 = *px++; + + /* Perform the multiply-accumulate */ + /* acc0 += x[0] * y[srcBLen - 1] */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32); + /* acc1 += x[1] * y[srcBLen - 1] */ + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32); + /* acc2 += x[2] * y[srcBLen - 1] */ + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32); + /* acc3 += x[3] * y[srcBLen - 1] */ + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32); + + /* Read y[srcBLen - 2] sample */ + c0 = *py--; + /* Read x[4] sample */ + x0 = *px++; + + /* Perform the multiply-accumulate */ + /* acc0 += x[1] * y[srcBLen - 2] */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x1 * c0)) >> 32); + /* acc1 += x[2] * y[srcBLen - 2] */ + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x2 * c0)) >> 32); + /* acc2 += x[3] * y[srcBLen - 2] */ + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x3 * c0)) >> 32); + /* acc3 += x[4] * y[srcBLen - 2] */ + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x0 * c0)) >> 32); + + /* Read y[srcBLen - 3] sample */ + c0 = *py--; + /* Read x[5] sample */ + x1 = *px++; + + /* Perform the multiply-accumulates */ + /* acc0 += x[2] * y[srcBLen - 3] */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x2 * c0)) >> 32); + /* acc1 += x[3] * y[srcBLen - 2] */ + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x3 * c0)) >> 32); + /* acc2 += x[4] * y[srcBLen - 2] */ + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x0 * c0)) >> 32); + /* acc3 += x[5] * y[srcBLen - 2] */ + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x1 * c0)) >> 32); + + /* Read y[srcBLen - 4] sample */ + c0 = *py--; + /* Read x[6] sample */ + x2 = *px++; + + /* Perform the multiply-accumulates */ + /* acc0 += x[3] * y[srcBLen - 4] */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x3 * c0)) >> 32); + /* acc1 += x[4] * y[srcBLen - 4] */ + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x0 * c0)) >> 32); + /* acc2 += x[5] * y[srcBLen - 4] */ + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x1 * c0)) >> 32); + /* acc3 += x[6] * y[srcBLen - 4] */ + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x2 * c0)) >> 32); + + } while (--k); + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Read y[srcBLen - 5] sample */ + c0 = *py--; + /* Read x[7] sample */ + x3 = *px++; + + /* Perform the multiply-accumulates */ + /* acc0 += x[4] * y[srcBLen - 5] */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32); + /* acc1 += x[5] * y[srcBLen - 5] */ + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32); + /* acc2 += x[6] * y[srcBLen - 5] */ + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32); + /* acc3 += x[7] * y[srcBLen - 5] */ + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32); + + /* Reuse the present samples for the next MAC */ + x0 = x1; + x1 = x2; + x2 = x3; + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q31_t) (acc0 << 1); + *pOut++ = (q31_t) (acc1 << 1); + *pOut++ = (q31_t) (acc2 << 1); + *pOut++ = (q31_t) (acc3 << 1); + + /* Increment the pointer pIn1 index, count by 4 */ + count += 4U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (uint32_t) blockSize2 % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize2; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = srcBLen >> 2U; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) * px++ * (*py--))) >> 32); + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) * px++ * (*py--))) >> 32); + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) * px++ * (*py--))) >> 32); + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) * px++ * (*py--))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = srcBLen % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = srcBLen; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum << 1; + + /* Increment MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = (uint32_t) blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum << 1; + + /* Increment the MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1] + * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2] + * .... + * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2] + * sum += x[srcALen-1] * y[srcBLen-1] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = srcBLen - 1U; + + /* Working pointer of inputA */ + if (firstIndex > srcALen) + { + pSrc1 = (pIn1 + firstIndex) - (srcBLen - 1U); + } + else + { + pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U); + } + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + while (blockSize3 > 0) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + + while (k > 0U) + { + /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = count; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + /* sum += x[srcALen-1] * y[srcBLen-1] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum << 1; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pSrc2; + + /* Decrement MAC count */ + count--; + + /* Decrement the loop counter */ + blockSize3--; + } + + /* Set status as RISCV_MATH_SUCCESS */ + status = RISCV_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +#endif /*defined (RISCV_VECTOR)*/ +} + +/** + @} end of PartialConv group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_conv_partial_opt_q15.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_conv_partial_opt_q15.c new file mode 100644 index 00000000..74f61cda --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_conv_partial_opt_q15.c @@ -0,0 +1,403 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_conv_partial_opt_q15.c + * Description: Partial convolution of Q15 sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup PartialConv + @{ + */ + +/** + @brief Partial convolution of Q15 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written + @param[in] firstIndex is the first output sample to start with + @param[in] numPoints is the number of output points to be computed + @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_ARGUMENT_ERROR : requested subset is not in the range [0 srcALen+srcBLen-2] + + @remark + Refer to \ref riscv_conv_partial_fast_q15() for a faster but less precise version of this function. + */ + +riscv_status riscv_conv_partial_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2) +{ + + q15_t *pOut = pDst; /* Output pointer */ + q15_t *pScr1 = pScratch1; /* Temporary pointer for scratch1 */ + q15_t *pScr2 = pScratch2; /* Temporary pointer for scratch1 */ + q63_t acc0; /* Accumulator */ + q31_t x1; /* Temporary variables to hold state and coefficient values */ + q31_t y1; /* State variables */ + const q15_t *pIn1; /* InputA pointer */ + const q15_t *pIn2; /* InputB pointer */ + const q15_t *px; /* Intermediate inputA pointer */ + q15_t *py; /* Intermediate inputB pointer */ + uint32_t j, k, blkCnt; /* Loop counter */ + uint32_t tapCnt; /* Loop count */ + riscv_status status; /* Status variable */ + +#if defined (RISCV_MATH_LOOPUNROLL) + q63_t acc1, acc2, acc3; /* Accumulator */ + q31_t x2, x3; /* Temporary variables to hold state and coefficient values */ + q31_t y2; /* State variables */ +#endif + + /* Check for range of output samples to be calculated */ + if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U)))) + { + /* Set status as RISCV_MATH_ARGUMENT_ERROR */ + status = RISCV_MATH_ARGUMENT_ERROR; + } + else + { + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* Temporary pointer for scratch2 */ + py = pScratch2; + + /* pointer to take end of scratch2 buffer */ + pScr2 = pScratch2 + srcBLen - 1; + + /* points to smaller length sequence */ + px = pIn2; + +#if defined (RISCV_MATH_LOOPUNROLL) && !defined (RISCV_VECTOR) +#if __RISCV_XLEN == 64 + pScr2 -= 3; +#endif /* __RISCV_XLEN == 64 */ + /* Loop unrolling: Compute 4 outputs at a time */ + k = srcBLen >> 2U; + + /* Copy smaller length input sequence in reverse order into second scratch buffer */ + while (k > 0U) + { +#if __RISCV_XLEN == 64 + write_q15x4_da(&pScr2,read_q15x4_ia(&px)); +#else + /* copy second buffer in reversal manner */ + *pScr2-- = *px++; + *pScr2-- = *px++; + *pScr2-- = *px++; + *pScr2-- = *px++; +#endif /* __RISCV_XLEN == 64 */ + /* Decrement loop counter */ + k--; + } +#if __RISCV_XLEN == 64 + pScr2 += 3; +#endif /* __RISCV_XLEN == 64 */ + /* Loop unrolling: Compute remaining outputs */ + k = srcBLen % 0x4U; + +#else + + /* Initialize k with number of samples */ + k = srcBLen; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ +#if defined (RISCV_VECTOR) + uint32_t vblkCnt = srcBLen; /* Loop counter */ + size_t l; + vint16m8_t vx; + ptrdiff_t bstride = -2; + for (; (l = vsetvl_e16m8(vblkCnt)) > 0; vblkCnt -= l) { + vx = vle16_v_i16m8(px, l); + px += l; + vsse16_v_i16m8(pScr2, bstride, vx, l); + pScr2 -= l; + } +#else + while (k > 0U) + { + /* copy second buffer in reversal manner for remaining samples */ + *pScr2-- = *px++; + + /* Decrement loop counter */ + k--; + } +#endif /*defined (RISCV_VECTOR)*/ + /* Initialze temporary scratch pointer */ + pScr1 = pScratch1; + + /* Assuming scratch1 buffer is aligned by 32-bit */ + /* Fill (srcBLen - 1U) zeros in scratch buffer */ + riscv_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update temporary scratch pointer */ + pScr1 += (srcBLen - 1U); + + /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */ + + /* Copy (srcALen) samples in scratch buffer */ + riscv_copy_q15(pIn1, pScr1, srcALen); + + /* Update pointers */ + pScr1 += srcALen; + + /* Fill (srcBLen - 1U) zeros at end of scratch buffer */ + riscv_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update pointer */ + pScr1 += (srcBLen - 1U); + + /* Initialization of pIn2 pointer */ + pIn2 = py; + + pScratch1 += firstIndex; + + pOut = pDst + firstIndex; + + /* Actual convolution process starts here */ + +#if defined (RISCV_MATH_LOOPUNROLL) && !defined (RISCV_VECTOR) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (numPoints) >> 2; + + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch1; + + /* Clear Accumlators */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Read two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* Read next two samples from scratch1 buffer */ + x2 = read_q15x2_ia (&pScr1); + + tapCnt = (srcBLen) >> 2U; + + while (tapCnt > 0U) + { + + /* Read four samples from smaller buffer */ + y1 = read_q15x2_ia ((q15_t **) &pIn2); + y2 = read_q15x2_ia ((q15_t **) &pIn2); + + /* multiply and accumulate */ + acc0 = __SMLALD(x1, y1, acc0); + acc2 = __SMLALD(x2, y1, acc2); + + /* pack input data */ + x3 = __PKHBT(x2, x1, 0); + + /* multiply and accumulate */ + acc1 = __SMLALDX(x3, y1, acc1); + + /* Read next two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* multiply and accumulate */ + acc0 = __SMLALD(x2, y2, acc0); + acc2 = __SMLALD(x1, y2, acc2); + + /* pack input data */ + x3 = __PKHBT(x1, x2, 0); + + acc3 = __SMLALDX(x3, y1, acc3); + acc1 = __SMLALDX(x3, y2, acc1); + + x2 = read_q15x2_ia (&pScr1); + + x3 = __PKHBT(x2, x1, 0); + + acc3 = __SMLALDX(x3, y2, acc3); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Update scratch pointer for remaining samples of smaller length sequence */ + pScr1 -= 4U; + + /* apply same above for remaining samples of smaller length sequence */ + tapCnt = (srcBLen) & 3U; + + while (tapCnt > 0U) + { + /* accumulate the results */ + acc0 += (*pScr1++ * *pIn2); + acc1 += (*pScr1++ * *pIn2); + acc2 += (*pScr1++ * *pIn2); + acc3 += (*pScr1++ * *pIn2++); + + pScr1 -= 3U; + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* Store the results in the accumulators in the destination buffer. */ + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16)); + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16)); + + /* Initialization of inputB pointer */ + pIn2 = py; + + pScratch1 += 4U; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numPoints & 0x3; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numPoints; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + /* Calculate convolution for remaining samples of Bigger length sequence */ + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch1; + + /* Clear Accumlators */ + acc0 = 0; +#if defined (RISCV_VECTOR) + uint32_t vblkCnt = srcBLen; /* Loop counter */ + size_t l; + vint16m4_t vx, vy; + vint32m1_t temp00m1; + // ptrdiff_t bstride = -2; + l = vsetvl_e32m1(1); + temp00m1 = vmv_v_x_i32m1(0, l); + for (; (l = vsetvl_e16m4(vblkCnt)) > 0; vblkCnt -= l) { + vx = vle16_v_i16m4(pScr1, l); + pScr1 += l; + vy = vle16_v_i16m4(pIn2, l); + pIn2 += l; + acc0 += vmv_x_s_i32m1_i32(vredsum_vs_i32m8_i32m1(temp00m1, vwmul_vv_i32m8(vx, vy, l), temp00m1, l)); + } +#else + tapCnt = (srcBLen) >> 1U; + + while (tapCnt > 0U) + { + /* Read next two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* Read two samples from smaller buffer */ + y1 = read_q15x2_ia ((q15_t **) &pIn2); + + acc0 = __SMLALD(x1, y1, acc0); + + /* Decrement the loop counter */ + tapCnt--; + } + + tapCnt = (srcBLen) & 1U; + + /* apply same above for remaining samples of smaller length sequence */ + while (tapCnt > 0U) + { + /* accumulate the results */ + acc0 += (*pScr1++ * *pIn2++); + + /* Decrement loop counter */ + tapCnt--; + } +#endif /*defined (RISCV_VECTOR)*/ + blkCnt--; + + /* The result is in 2.30 format. Convert to 1.15 with saturation. + ** Then store the output in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16)); + + /* Initialization of inputB pointer */ + pIn2 = py; + + pScratch1 += 1U; + + } + + /* Set status as RISCV_MATH_SUCCESS */ + status = RISCV_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +/** + @} end of PartialConv group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_conv_partial_opt_q7.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_conv_partial_opt_q7.c new file mode 100644 index 00000000..e080c345 --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_conv_partial_opt_q7.c @@ -0,0 +1,432 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_conv_partial_opt_q7.c + * Description: Partial convolution of Q7 sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup PartialConv + @{ + */ + +/** + @brief Partial convolution of Q7 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written + @param[in] firstIndex is the first output sample to start with + @param[in] numPoints is the number of output points to be computed + @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_ARGUMENT_ERROR : requested subset is not in the range [0 srcALen+srcBLen-2] + */ + +riscv_status riscv_conv_partial_opt_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2) +{ + q15_t *pScr2, *pScr1; /* Intermediate pointers for scratch pointers */ + q15_t x4; /* Temporary input variable */ + const q7_t *pIn1, *pIn2; /* InputA and inputB pointer */ + uint32_t j, k, blkCnt, tapCnt; /* Loop counter */ + const q7_t *px; /* Temporary input1 pointer */ + q15_t *py; /* Temporary input2 pointer */ + q31_t acc0, acc1, acc2, acc3; /* Accumulator */ + q31_t x1, x2, x3, y1; /* Temporary input variables */ + riscv_status status; + q7_t *pOut = pDst; /* Output pointer */ + q7_t out0, out1, out2, out3; /* Temporary variables */ + + /* Check for range of output samples to be calculated */ + if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U)))) + { + /* Set status as RISCV_MATH_ARGUMENT_ERROR */ + status = RISCV_MATH_ARGUMENT_ERROR; + } + else + { + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* pointer to take end of scratch2 buffer */ + pScr2 = pScratch2; + + /* points to smaller length sequence */ + px = pIn2 + srcBLen - 1; +#if defined (RISCV_VECTOR) + uint32_t vblkCnt = srcBLen; /* Loop counter */ + size_t l; + vint16m8_t vx; + ptrdiff_t bstride = -1; + for (; (l = vsetvl_e8m4(vblkCnt)) > 0; vblkCnt -= l) { + vx = vwadd_vx_i16m8(vlse8_v_i8m4(px, bstride, l),0, l); + px -= l; + vse16_v_i16m8(pScr2, vx, l); + pScr2 += l; + } +#else + /* Apply loop unrolling and do 4 Copies simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling copies 4 data points at a time. + ** a second loop below copies for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* copy second buffer in reversal manner */ + x4 = (q15_t) *px--; + *pScr2++ = x4; + x4 = (q15_t) *px--; + *pScr2++ = x4; + x4 = (q15_t) *px--; + *pScr2++ = x4; + x4 = (q15_t) *px--; + *pScr2++ = x4; + + /* Decrement loop counter */ + k--; + } + + /* If the count is not a multiple of 4, copy remaining samples here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* copy second buffer in reversal manner for remaining samples */ + x4 = (q15_t) *px--; + *pScr2++ = x4; + + /* Decrement loop counter */ + k--; + } +#endif /*defined (RISCV_VECTOR)*/ + /* Initialze temporary scratch pointer */ + pScr1 = pScratch1; + + /* Fill (srcBLen - 1U) zeros in scratch buffer */ + riscv_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update temporary scratch pointer */ + pScr1 += (srcBLen - 1U); +#if defined (RISCV_VECTOR) + vblkCnt = srcALen; /* Loop counter */ + for (; (l = vsetvl_e8m4(vblkCnt)) > 0; vblkCnt -= l) { + vx = vwadd_vx_i16m8(vle8_v_i8m4(pIn1, l),0, l); + pIn1 += l; + vse16_v_i16m8(pScr1, vx, l); + pScr1 += l; + } +#else + /* Copy (srcALen) samples in scratch buffer */ + /* Apply loop unrolling and do 4 Copies simultaneously. */ + k = srcALen >> 2U; + + /* First part of the processing with loop unrolling copies 4 data points at a time. + ** a second loop below copies for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* copy second buffer in reversal manner */ + x4 = (q15_t) *pIn1++; + *pScr1++ = x4; + x4 = (q15_t) *pIn1++; + *pScr1++ = x4; + x4 = (q15_t) *pIn1++; + *pScr1++ = x4; + x4 = (q15_t) *pIn1++; + *pScr1++ = x4; + /* Decrement loop counter */ + k--; + } + + /* If the count is not a multiple of 4, copy remaining samples here. + ** No loop unrolling is used. */ + k = srcALen % 0x4U; + + while (k > 0U) + { + /* copy second buffer in reversal manner for remaining samples */ + x4 = (q15_t) *pIn1++; + *pScr1++ = x4; + + /* Decrement the loop counter */ + k--; + } +#endif /*defined (RISCV_VECTOR)*/ + /* Fill (srcBLen - 1U) zeros at end of scratch buffer */ + riscv_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update pointer */ + pScr1 += (srcBLen - 1U); + + + /* Temporary pointer for scratch2 */ + py = pScratch2; + + /* Initialization of pIn2 pointer */ + pIn2 = (q7_t *) py; + + pScr2 = py; + + pOut = pDst + firstIndex; + + pScratch1 += firstIndex; +#if defined (RISCV_VECTOR) + blkCnt = numPoints; + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch1; + + /* Clear Accumlators */ + acc0 = 0; + + uint32_t vblkCnt = srcBLen; /* Loop counter */ + size_t l; + vint16m4_t vx, vy; + vint32m1_t temp00m1; + l = vsetvl_e32m1(vblkCnt); + temp00m1 = vmv_v_x_i32m1(0, l); + for (; (l = vsetvl_e16m4(vblkCnt)) > 0; vblkCnt -= l) { + vx = vle16_v_i16m4(pScr1, l); + pScr1 += l; + vy = vle16_v_i16m4(pScr2, l); + pScr2 += l; + acc0 += vmv_x_s_i32m1_i32(vredsum_vs_i32m8_i32m1(temp00m1, vwmul_vv_i32m8(vx, vy, l), temp00m1, l)); + } + + blkCnt--; + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q7_t) (__SSAT(acc0 >> 7U, 8)); + + /* Initialization of inputB pointer */ + pScr2 = py; + + pScratch1 += 1U; + } +#else + + /* Actual convolution process starts here */ + blkCnt = (numPoints) >> 2; + + while (blkCnt > 0) + { + /* Initialize temporary scratch pointer as scratch1 */ + pScr1 = pScratch1; + + /* Clear Accumulators */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Read two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* Read next two samples from scratch1 buffer */ + x2 = read_q15x2_ia (&pScr1); + + tapCnt = (srcBLen) >> 2U; + + while (tapCnt > 0U) + { + /* Read four samples from smaller buffer */ + y1 = read_q15x2_ia (&pScr2); + + /* multiply and accumulate */ + acc0 = __SMLAD(x1, y1, acc0); + acc2 = __SMLAD(x2, y1, acc2); + + /* pack input data */ + x3 = __PKHBT(x2, x1, 0); + + /* multiply and accumulate */ + acc1 = __SMLADX(x3, y1, acc1); + + /* Read next two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* pack input data */ + x3 = __PKHBT(x1, x2, 0); + + acc3 = __SMLADX(x3, y1, acc3); + + /* Read four samples from smaller buffer */ + y1 = read_q15x2_ia (&pScr2); + + acc0 = __SMLAD(x2, y1, acc0); + + acc2 = __SMLAD(x1, y1, acc2); + + acc1 = __SMLADX(x3, y1, acc1); + + x2 = read_q15x2_ia (&pScr1); + + x3 = __PKHBT(x2, x1, 0); + + acc3 = __SMLADX(x3, y1, acc3); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Update scratch pointer for remaining samples of smaller length sequence */ + pScr1 -= 4U; + + /* apply same above for remaining samples of smaller length sequence */ + tapCnt = (srcBLen) & 3U; + + while (tapCnt > 0U) + { + /* accumulate the results */ + acc0 += (*pScr1++ * *pScr2); + acc1 += (*pScr1++ * *pScr2); + acc2 += (*pScr1++ * *pScr2); + acc3 += (*pScr1++ * *pScr2++); + + pScr1 -= 3U; + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* Store the result in the accumulator in the destination buffer. */ + out0 = (q7_t) (__SSAT(acc0 >> 7U, 8)); + out1 = (q7_t) (__SSAT(acc1 >> 7U, 8)); + out2 = (q7_t) (__SSAT(acc2 >> 7U, 8)); + out3 = (q7_t) (__SSAT(acc3 >> 7U, 8)); + + write_q7x4_ia (&pOut, __PACKq7(out0, out1, out2, out3)); + + /* Initialization of inputB pointer */ + pScr2 = py; + + pScratch1 += 4U; + } + + blkCnt = (numPoints) & 0x3; + + /* Calculate convolution for remaining samples of Bigger length sequence */ + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch1; + + /* Clear Accumlators */ + acc0 = 0; + + tapCnt = (srcBLen) >> 1U; + + while (tapCnt > 0U) + { + + /* Read next two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* Read two samples from smaller buffer */ + y1 = read_q15x2_ia (&pScr2); + + acc0 = __SMLAD(x1, y1, acc0); + + /* Decrement the loop counter */ + tapCnt--; + } + + tapCnt = (srcBLen) & 1U; + + /* apply same above for remaining samples of smaller length sequence */ + while (tapCnt > 0U) + { + + /* accumulate the results */ + acc0 += (*pScr1++ * *pScr2++); + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q7_t) (__SSAT(acc0 >> 7U, 8)); + + /* Initialization of inputB pointer */ + pScr2 = py; + + pScratch1 += 1U; + } +#endif /*defined (RISCV_VECTOR)*/ + /* Set status as RISCV_MATH_SUCCESS */ + status = RISCV_MATH_SUCCESS; + } + + return (status); +} + +/** + @} end of PartialConv group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_conv_partial_q15.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_conv_partial_q15.c new file mode 100644 index 00000000..d7428649 --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_conv_partial_q15.c @@ -0,0 +1,875 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_conv_partial_q15.c + * Description: Partial convolution of Q15 sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup PartialConv + @{ + */ + +/** + @brief Partial convolution of Q15 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written + @param[in] firstIndex is the first output sample to start with + @param[in] numPoints is the number of output points to be computed + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_ARGUMENT_ERROR : requested subset is not in the range [0 srcALen+srcBLen-2] + + @remark + Refer to \ref riscv_conv_partial_fast_q15() for a faster but less precise version of this function. + @remark + Refer to \ref riscv_conv_partial_opt_q15() for a faster implementation of this function using scratch buffers. + */ + +riscv_status riscv_conv_partial_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints) +{ + +#if defined (RISCV_MATH_DSP) || defined (RISCV_VECTOR) + + const q15_t *pIn1; /* InputA pointer */ + const q15_t *pIn2; /* InputB pointer */ + q15_t *pOut = pDst; /* Output pointer */ + q63_t sum, acc0, acc1, acc2, acc3; /* Accumulator */ + const q15_t *px; /* Intermediate inputA pointer */ + const q15_t *py; /* Intermediate inputB pointer */ + const q15_t *pSrc1, *pSrc2; /* Intermediate pointers */ + q31_t x0, x1, x2, x3, c0; /* Temporary input variables to hold state and coefficient values */ + int32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + uint32_t j, k, count, blkCnt, check; + riscv_status status; /* Status of Partial convolution */ + + /* Check for range of output samples to be calculated */ + if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U)))) + { + /* Set status as RISCV_MATH_ARGUMENT_ERROR */ + status = RISCV_MATH_ARGUMENT_ERROR; + } + else + { + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* Conditions to check which loopCounter holds + * the first and last indices of the output samples to be calculated. */ + check = firstIndex + numPoints; + blockSize3 = ((int32_t)check > (int32_t)srcALen) ? (int32_t)check - (int32_t)srcALen : 0; + blockSize3 = ((int32_t)firstIndex > (int32_t)srcALen - 1) ? blockSize3 - (int32_t)firstIndex + (int32_t)srcALen : blockSize3; + blockSize1 = ((int32_t) srcBLen - 1) - (int32_t) firstIndex; + blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1U)) ? blockSize1 : (int32_t)numPoints) : 0; + blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) + (int32_t) firstIndex); + blockSize2 = (blockSize2 > 0) ? blockSize2 : 0; + + /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */ + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* Set the output pointer to point to the firstIndex + * of the output sample to be calculated. */ + pOut = pDst + firstIndex; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[0] + * sum = x[0] * y[1] + x[1] * y[0] + * .... + * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed. + Since the partial convolution starts from firstIndex + Number of Macs to be performed is firstIndex + 1 */ + count = 1U + firstIndex; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + firstIndex; + py = pSrc2; + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* For loop unrolling by 4, this stage is divided into two. */ + /* First part of this stage computes the MAC operations less than 4 */ + /* Second part of this stage computes the MAC operations greater than or equal to 4 */ +#if defined (RISCV_VECTOR) + while (blockSize1 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + uint32_t vblkCnt = count; /* Loop counter */ + size_t l; + vint16m4_t vx, vy; + vint32m1_t temp00m1; + ptrdiff_t bstride = -2; + l = vsetvl_e32m1(vblkCnt); + temp00m1 = vmv_v_x_i32m1(0, l); + for (; (l = vsetvl_e16m4(vblkCnt)) > 0; vblkCnt -= l) { + vx = vle16_v_i16m4(px, l); + px += l; + vy = vlse16_v_i16m4(py, bstride, l); + py -= l; + sum += vmv_x_s_i32m1_i32(vredsum_vs_i32m8_i32m1(temp00m1, vwmul_vv_i32m8(vx, vy, l), temp00m1, l)); + } + + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT((sum >> 15), 16)); + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = pIn2 + (count - 1U); + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } +#else + /* The first part of the stage starts here */ + while ((count < 4U) && (blockSize1 > 0)) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Loop over number of MAC operations between + * inputA samples and inputB samples */ + k = count; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum = __SMLALD(*px++, *py--, sum); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT((sum >> 15), 16)); + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = ++pSrc2; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* The second part of the stage starts here */ + /* The internal loop, over count, is unrolled by 4 */ + /* To, read the last two inputB samples using SIMD: + * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */ + py = py - 1; +#if __RISCV_XLEN == 64 + py = py - 2; +#endif /* __RISCV_XLEN == 64 */ + while (blockSize1 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = count >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { +#if __RISCV_XLEN == 64 + sum = __RV_SMALXDA(sum, read_q15x4_ia ((q15_t **) &px), read_q15x4_da ((q15_t **) &py)); +#else + /* Perform the multiply-accumulate */ + /* x[0], x[1] are multiplied with y[srcBLen - 1], y[srcBLen - 2] respectively */ + sum = __SMLALDX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum); + /* x[2], x[3] are multiplied with y[srcBLen - 3], y[srcBLen - 4] respectively */ + sum = __SMLALDX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum); +#endif /* __RISCV_XLEN == 64 */ + + /* Decrement loop counter */ + k--; + } +#if __RISCV_XLEN == 64 + py = py + 2; +#endif /* __RISCV_XLEN == 64 */ + /* For the next MAC operations, the pointer py is used without SIMD + * So, py is incremented by 1 */ + py = py + 1U; + + /* If the count is not a multiple of 4, compute any remaining MACs here. + No loop unrolling is used. */ + k = count % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum = __SMLALD(*px++, *py--, sum); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT((sum >> 15), 16)); + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = ++pSrc2 - 1U; + px = pIn1; +// #if __RISCV_XLEN == 64 +// py = py - 2; +// #endif /* __RISCV_XLEN == 64 */ + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } +#endif /*defined (RISCV_VECTOR)*/ + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0] + * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0] + * .... + * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0] + */ + + /* Working pointer of inputA */ + if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0) + { + pSrc1 = pIn1 + firstIndex - srcBLen + 1; + } + else + { + pSrc1 = pIn1; + } + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* count is the index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ +#if defined (RISCV_VECTOR) + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + uint32_t vblkCnt = srcBLen; /* Loop counter */ + size_t l; + vint16m4_t vx, vy; + vint32m1_t temp00m1; + ptrdiff_t bstride = -2; + l = vsetvl_e32m1(vblkCnt); + temp00m1 = vmv_v_x_i32m1(0, l); + for (; (l = vsetvl_e16m4(vblkCnt)) > 0; vblkCnt -= l) { + vx = vle16_v_i16m4(px, l); + px += l; + vy = vlse16_v_i16m4(py, bstride, l); + py -= l; + sum += vmv_x_s_i32m1_i32(vredsum_vs_i32m8_i32m1(temp00m1, vwmul_vv_i32m8(vx, vy, l), temp00m1, l)); + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT(sum >> 15, 16)); + + /* Increment the MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement the loop counter */ + blkCnt--; + } +#else + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = ((uint32_t) blockSize2 >> 2U); + + while (blkCnt > 0U) + { + py = py - 1U; + + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + + /* read x[0], x[1] samples */ + x0 = read_q15x2 ((q15_t *) px); + /* read x[1], x[2] samples */ + x1 = read_q15x2 ((q15_t *) px + 1); + px += 2U; + + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + do + { + /* Read the last two inputB samples using SIMD: + * y[srcBLen - 1] and y[srcBLen - 2] */ + c0 = read_q15x2_da ((q15_t **) &py); + + /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */ + acc0 = __SMLALDX(x0, c0, acc0); + + /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */ + acc1 = __SMLALDX(x1, c0, acc1); + + /* Read x[2], x[3] */ + x2 = read_q15x2 ((q15_t *) px); + + /* Read x[3], x[4] */ + x3 = read_q15x2 ((q15_t *) px + 1); + + /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */ + acc2 = __SMLALDX(x2, c0, acc2); + + /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */ + acc3 = __SMLALDX(x3, c0, acc3); + + /* Read y[srcBLen - 3] and y[srcBLen - 4] */ + c0 = read_q15x2_da ((q15_t **) &py); + + /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */ + acc0 = __SMLALDX(x2, c0, acc0); + + /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */ + acc1 = __SMLALDX(x3, c0, acc1); + + /* Read x[4], x[5] */ + x0 = read_q15x2 ((q15_t *) px + 2); + + /* Read x[5], x[6] */ + x1 = read_q15x2 ((q15_t *) px + 3); + px += 4U; + + /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */ + acc2 = __SMLALDX(x0, c0, acc2); + + /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */ + acc3 = __SMLALDX(x1, c0, acc3); + + } while (--k); + + /* For the next MAC operations, SIMD is not used + * So, the 16 bit pointer if inputB, py is updated */ + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + if (k == 1U) + { + /* Read y[srcBLen - 5] */ + c0 = *(py+1); + c0 = c0 & 0x0000FFFF; + + /* Read x[7] */ + x3 = read_q15x2 ((q15_t *) px); + px++; + + /* Perform the multiply-accumulate */ + acc0 = __SMLALD (x0, c0, acc0); + acc1 = __SMLALD (x1, c0, acc1); + acc2 = __SMLALDX(x1, c0, acc2); + acc3 = __SMLALDX(x3, c0, acc3); + } + + if (k == 2U) + { + /* Read y[srcBLen - 5], y[srcBLen - 6] */ + c0 = read_q15x2 ((q15_t *) py); + + /* Read x[7], x[8] */ + x3 = read_q15x2 ((q15_t *) px); + + /* Read x[9] */ + x2 = read_q15x2 ((q15_t *) px + 1); + px += 2U; + + /* Perform the multiply-accumulate */ + acc0 = __SMLALDX(x0, c0, acc0); + acc1 = __SMLALDX(x1, c0, acc1); + acc2 = __SMLALDX(x3, c0, acc2); + acc3 = __SMLALDX(x2, c0, acc3); + } + + if (k == 3U) + { + /* Read y[srcBLen - 5], y[srcBLen - 6] */ + c0 = read_q15x2 ((q15_t *) py); + + /* Read x[7], x[8] */ + x3 = read_q15x2 ((q15_t *) px); + + /* Read x[9] */ + x2 = read_q15x2 ((q15_t *) px + 1); + + /* Perform the multiply-accumulate */ + acc0 = __SMLALDX(x0, c0, acc0); + acc1 = __SMLALDX(x1, c0, acc1); + acc2 = __SMLALDX(x3, c0, acc2); + acc3 = __SMLALDX(x2, c0, acc3); + + c0 = *(py-1); + c0 = c0 & 0x0000FFFF; + + /* Read x[10] */ + x3 = read_q15x2 ((q15_t *) px + 2); + px += 3U; + + /* Perform the multiply-accumulates */ + acc0 = __SMLALDX(x1, c0, acc0); + acc1 = __SMLALD (x2, c0, acc1); + acc2 = __SMLALDX(x2, c0, acc2); + acc3 = __SMLALDX(x3, c0, acc3); + } + + /* Store the results in the accumulators in the destination buffer. */ + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16)); + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16)); + + /* Increment the pointer pIn1 index, count by 4 */ + count += 4U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here. + No loop unrolling is used. */ + blkCnt = (uint32_t) blockSize2 % 0x4U; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; +// #if __RISCV_XLEN == 64 +// py -= 4; +// q63_t acc064, acc164; +// #endif /* __RISCV_XLEN == 64 */ + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { +// #if __RISCV_XLEN == 64 +// acc064 = read_q15x4_ia((q15_t **) &px); +// acc164 = read_q15x4_da((q15_t **) &py); +// sum = __RV_KMADA(sum, acc064, acc164); +// #else + /* Perform the multiply-accumulates */ + sum += (q63_t) ((q31_t) *px++ * *py--); + sum += (q63_t) ((q31_t) *px++ * *py--); + sum += (q63_t) ((q31_t) *px++ * *py--); + sum += (q63_t) ((q31_t) *px++ * *py--); +// #endif /* __RISCV_XLEN == 64 */ + /* Decrement loop counter */ + k--; + } + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += (q63_t) ((q31_t) *px++ * *py--); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT(sum >> 15, 16)); + + /* Increment the pointer pIn1 index, count by 1 */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = (uint32_t) blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += (q63_t) ((q31_t) *px++ * *py--); + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT(sum >> 15, 16)); + + /* Increment the MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement the loop counter */ + blkCnt--; + } + } +#endif /*defined (RISCV_VECTOR)*/ + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1] + * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2] + * .... + * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2] + * sum += x[srcALen-1] * y[srcBLen-1] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = srcBLen - 1U; + + /* Working pointer of inputA */ + if (firstIndex > srcALen) + { + pSrc1 = (pIn1 + firstIndex) - (srcBLen - 1U); + } + else + { + pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U); + } + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + pIn2 = pSrc2 - 1U; + py = pIn2; + + /* ------------------- + * Stage3 process + * ------------------*/ +#if defined (RISCV_VECTOR) + while (blockSize3 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + uint32_t vblkCnt = blockSize3; /* Loop counter */ + size_t l; + vint16m4_t vx, vy; + vint32m1_t temp00m1; + ptrdiff_t bstride = -2; + l = vsetvl_e32m1(1); + temp00m1 = vmv_v_x_i32m1(0, l); + for (; (l = vsetvl_e16m4(vblkCnt)) > 0; vblkCnt -= l) { + vx = vle16_v_i16m4(px, l); + px += l; + vy = vlse16_v_i16m4(py, bstride, l); + py -= l; + sum += vmv_x_s_i32m1_i32(vredsum_vs_i32m8_i32m1(temp00m1, vwmul_vv_i32m8(vx, vy, l), temp00m1, l)); + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT((sum >> 15), 16)); + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pSrc2; + + /* Decrement loop counter */ + blockSize3--; + } + +#else + /* For loop unrolling by 4, this stage is divided into two. */ + /* First part of this stage computes the MAC operations greater than 4 */ + /* Second part of this stage computes the MAC operations less than or equal to 4 */ + + /* The first part of the stage starts here */ + j = count >> 2U; + + while ((j > 0U) && (blockSize3 > 0)) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = count >> 2U; +#if __RISCV_XLEN == 64 + py -= 2; +#endif /* __RISCV_XLEN == 64 */ + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { +#if __RISCV_XLEN == 64 + sum = __SMLALDX(read_q15x4_ia ((q15_t **) &px), read_q15x4_da ((q15_t **) &py), sum); +#else + /* x[srcALen - srcBLen + 1], x[srcALen - srcBLen + 2] are multiplied + * with y[srcBLen - 1], y[srcBLen - 2] respectively */ + sum = __SMLALDX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum); + /* x[srcALen - srcBLen + 3], x[srcALen - srcBLen + 4] are multiplied + * with y[srcBLen - 3], y[srcBLen - 4] respectively */ + sum = __SMLALDX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum); +#endif /* __RISCV_XLEN == 64 */ + + /* Decrement loop counter */ + k--; + } +#if __RISCV_XLEN == 64 + py = py + 2; +#endif /* __RISCV_XLEN == 64 */ + /* For the next MAC operations, the pointer py is used without SIMD + * So, py is incremented by 1 */ + py = py + 1U; + + /* If the count is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = count % 0x4U; + + while (k > 0U) + { + /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */ + sum = __SMLALD(*px++, *py--, sum); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT((sum >> 15), 16)); + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pIn2; + + /* Decrement MAC count */ + count--; + + /* Decrement loop counter */ + blockSize3--; + + j--; + } + + /* The second part of the stage starts here */ + /* SIMD is not used for the next MAC operations, + * so pointer py is updated to read only one sample at a time */ + py = py + 1U; + + while (blockSize3 > 0) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = count; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + /* sum += x[srcALen-1] * y[srcBLen-1] */ + sum = __SMLALD(*px++, *py--, sum); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT((sum >> 15), 16)); + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pSrc2; + + /* Decrement MAC count */ + count--; + + /* Decrement the loop counter */ + blockSize3--; + } +#endif /*defined (RISCV_VECTOR)*/ + + /* Set status as RISCV_MATH_SUCCESS */ + status = RISCV_MATH_SUCCESS; + } + /* Return to application */ + return (status); + +#else /* #if defined (RISCV_MATH_DSP) */ + + const q15_t *pIn1 = pSrcA; /* InputA pointer */ + const q15_t *pIn2 = pSrcB; /* InputB pointer */ + q63_t sum; /* Accumulator */ + uint32_t i, j; /* Loop counters */ + riscv_status status; /* Status of Partial convolution */ + + /* Check for range of output samples to be calculated */ + if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U)))) + { + /* Set status as RISCV_MATH_ARGUMENT_ERROR */ + status = RISCV_MATH_ARGUMENT_ERROR; + } + else + { + /* Loop to calculate convolution for output length number of values */ + for (i = firstIndex; i <= (firstIndex + numPoints - 1); i++) + { + /* Initialize sum with zero to carry on MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0U; j <= i; j++) + { + /* Check the array limitations */ + if (((i - j) < srcBLen) && (j < srcALen)) + { + /* z[i] += x[i-j] * y[j] */ + sum += ((q31_t) pIn1[j] * pIn2[i - j]); + } + } + + /* Store the output in the destination buffer */ + pDst[i] = (q15_t) __SSAT((sum >> 15U), 16U); + } + + /* Set status as RISCV_MATH_SUCCESS */ + status = RISCV_MATH_SUCCESS; + } + + /* Return to application */ + return (status); + +#endif /* #if defined (RISCV_MATH_DSP) */ + +} + +/** + @} end of PartialConv group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_conv_partial_q31.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_conv_partial_q31.c new file mode 100644 index 00000000..a0d366a4 --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_conv_partial_q31.c @@ -0,0 +1,746 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_conv_partial_q31.c + * Description: Partial convolution of Q31 sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup PartialConv + @{ + */ + +/** + @brief Partial convolution of Q31 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written + @param[in] firstIndex is the first output sample to start with + @param[in] numPoints is the number of output points to be computed + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_ARGUMENT_ERROR : requested subset is not in the range [0 srcALen+srcBLen-2] + + @remark + Refer to \ref riscv_conv_partial_fast_q31() for a faster but less precise implementation of this function. + */ + +riscv_status riscv_conv_partial_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints) +{ + +#if defined(RISCV_MATH_DSP) || defined (RISCV_VECTOR) + + const q31_t *pIn1; /* InputA pointer */ + const q31_t *pIn2; /* InputB pointer */ + q31_t *pOut = pDst; /* Output pointer */ + const q31_t *px; /* Intermediate inputA pointer */ + const q31_t *py; /* Intermediate inputB pointer */ + const q31_t *pSrc1, *pSrc2; /* Intermediate pointers */ + q63_t sum; /* Accumulator */ + uint32_t j, k, count, blkCnt, check; + int32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + riscv_status status; /* Status of Partial convolution */ + +#if defined (RISCV_MATH_LOOPUNROLL) + q63_t acc0, acc1, acc2; /* Accumulator */ + q31_t x0, x1, x2, c0; /* Temporary variables */ +#if __RISCV_XLEN == 64 + q63_t acc064, acc164, acc264; +#endif /* __RISCV_XLEN == 64 */ +#endif + + /* Check for range of output samples to be calculated */ + if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U)))) + { + /* Set status as RISCV_MATH_ARGUMENT_ERROR */ + status = RISCV_MATH_ARGUMENT_ERROR; + } + else + { + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* Conditions to check which loopCounter holds + * the first and last indices of the output samples to be calculated. */ + check = firstIndex + numPoints; + blockSize3 = ((int32_t)check > (int32_t)srcALen) ? (int32_t)check - (int32_t)srcALen : 0; + blockSize3 = ((int32_t)firstIndex > (int32_t)srcALen - 1) ? blockSize3 - (int32_t)firstIndex + (int32_t)srcALen : blockSize3; + blockSize1 = ((int32_t) srcBLen - 1) - (int32_t) firstIndex; + blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1U)) ? blockSize1 : (int32_t)numPoints) : 0; + blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) + (int32_t) firstIndex); + blockSize2 = (blockSize2 > 0) ? blockSize2 : 0; + + /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */ + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* Set the output pointer to point to the firstIndex + * of the output sample to be calculated. */ + pOut = pDst + firstIndex; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[0] + * sum = x[0] * y[1] + x[1] * y[0] + * .... + * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed. + Since the partial convolution starts from firstIndex + Number of Macs to be performed is firstIndex + 1 */ + count = 1U + firstIndex; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + firstIndex; + py = pSrc2; + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* The first stage starts here */ + while (blockSize1 > 0) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (RISCV_MATH_LOOPUNROLL) && !defined (RISCV_VECTOR) +#if __RISCV_XLEN == 64 + py--; +#endif /* __RISCV_XLEN == 64 */ + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + + while (k > 0U) + { +#if __RISCV_XLEN == 64 + acc064 = read_q31x2_ia((q31_t **)&px); + acc164 = read_q31x2_da((q31_t **)&py); + sum = __RV_KMAXDA32(sum, acc064, acc164); + acc064 = read_q31x2_ia((q31_t **)&px); + acc164 = read_q31x2_da((q31_t **)&py); + sum = __RV_KMAXDA32(sum, acc064, acc164); +#else + /* x[0] * y[srcBLen - 1] */ + sum += (q63_t) *px++ * (*py--); + + /* x[1] * y[srcBLen - 2] */ + sum += (q63_t) *px++ * (*py--); + + /* x[2] * y[srcBLen - 3] */ + sum += (q63_t) *px++ * (*py--); + + /* x[3] * y[srcBLen - 4] */ + sum += (q63_t) *px++ * (*py--); +#endif /* __RISCV_XLEN == 64 */ + + /* Decrement loop counter */ + k--; + } +#if __RISCV_XLEN == 64 + py++; +#endif /* __RISCV_XLEN == 64 */ + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize k with number of samples */ + k = count; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ +#if defined (RISCV_VECTOR) + uint32_t vblkCnt = count; /* Loop counter */ + size_t l; + vint32m4_t vx, vy; + vint64m1_t temp00m1; + ptrdiff_t bstride = -4; + l = vsetvl_e64m1(1); + temp00m1 = vmv_v_x_i64m1(0, l); + for (; (l = vsetvl_e32m4(vblkCnt)) > 0; vblkCnt -= l) { + vx = vle32_v_i32m4(px, l); + px += l; + vy = vlse32_v_i32m4(py, bstride, l); + py -= l; + sum += vmv_x_s_i64m1_i64(vredsum_vs_i64m8_i64m1(temp00m1, vwmul_vv_i64m8(vx, vy, l), temp00m1, l)); + } +#else + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += (q63_t) *px++ * (*py--); + + /* Decrement loop counter */ + k--; + } +#endif /*defined (RISCV_VECTOR)*/ + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q31_t) (sum >> 31); + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = ++pSrc2; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0] + * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0] + * .... + * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0] + */ + + /* Working pointer of inputA */ + if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0) + { + pSrc1 = pIn1 + firstIndex - srcBLen + 1; + } + else + { + pSrc1 = pIn1; + } + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* count is index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ +#if defined (RISCV_VECTOR) + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + uint32_t vblkCnt = srcBLen; /* Loop counter */ + size_t l; + vint32m4_t vx, vy; + vint64m1_t temp00m1; + ptrdiff_t bstride = -4; + l = vsetvl_e64m1(1); + temp00m1 = vmv_v_x_i64m1(0, l); + for (; (l = vsetvl_e32m4(vblkCnt)) > 0; vblkCnt -= l) { + vx = vle32_v_i32m4(px, l); + px += l; + vy = vlse32_v_i32m4(py, bstride, l); + py -= l; + sum += vmv_x_s_i64m1_i64(vredsum_vs_i64m8_i64m1(temp00m1, vwmul_vv_i64m8(vx, vy, l), temp00m1, l)); + } + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q31_t) (sum >> 31); + + /* Increment MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } +#else + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unroll over blkCnt */ + blkCnt = blockSize2 / 3; + + while (blkCnt > 0U) + { + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + + /* read x[0], x[1] samples */ + x0 = *px++; + x1 = *px++; + + /* Apply loop unrolling and compute 3 MACs simultaneously. */ + k = srcBLen / 3; + + /* First part of the processing with loop unrolling. Compute 3 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 2 samples. */ + do + { + /* Read y[srcBLen - 1] sample */ + c0 = *(py); + + /* Read x[2] sample */ + x2 = *(px); + + /* Perform the multiply-accumulate */ + /* acc0 += x[0] * y[srcBLen - 1] */ + acc0 += (q63_t) x0 * c0; + /* acc1 += x[1] * y[srcBLen - 1] */ + acc1 += (q63_t) x1 * c0; + /* acc2 += x[2] * y[srcBLen - 1] */ + acc2 += (q63_t) x2 * c0; + + /* Read y[srcBLen - 2] sample */ + c0 = *(py - 1U); + + /* Read x[3] sample */ + x0 = *(px + 1U); + + /* Perform the multiply-accumulate */ + /* acc0 += x[1] * y[srcBLen - 2] */ + acc0 += (q63_t) x1 * c0; + /* acc1 += x[2] * y[srcBLen - 2] */ + acc1 += (q63_t) x2 * c0; + /* acc2 += x[3] * y[srcBLen - 2] */ + acc2 += (q63_t) x0 * c0; + + /* Read y[srcBLen - 3] sample */ + c0 = *(py - 2U); + + /* Read x[4] sample */ + x1 = *(px + 2U); + + /* Perform the multiply-accumulate */ + /* acc0 += x[2] * y[srcBLen - 3] */ + acc0 += (q63_t) x2 * c0; + /* acc1 += x[3] * y[srcBLen - 2] */ + acc1 += (q63_t) x0 * c0; + /* acc2 += x[4] * y[srcBLen - 2] */ + acc2 += (q63_t) x1 * c0; + + + px += 3U; + + py -= 3U; + + } while (--k); + + /* If the srcBLen is not a multiple of 3, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen - (3 * (srcBLen / 3)); + + while (k > 0U) + { + /* Read y[srcBLen - 5] sample */ + c0 = *py--; + /* Read x[7] sample */ + x2 = *px++; + + /* Perform the multiply-accumulates */ + /* acc0 += x[4] * y[srcBLen - 5] */ + acc0 += (q63_t) x0 * c0; + /* acc1 += x[5] * y[srcBLen - 5] */ + acc1 += (q63_t) x1 * c0; + /* acc2 += x[6] * y[srcBLen - 5] */ + acc2 += (q63_t) x2 * c0; + + /* Reuse the present samples for the next MAC */ + x0 = x1; + x1 = x2; + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q31_t) (acc0 >> 31); + *pOut++ = (q31_t) (acc1 >> 31); + *pOut++ = (q31_t) (acc2 >> 31); + + /* Increment the pointer pIn1 index, count by 3 */ + count += 3U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize2 - 3 * (blockSize2 / 3); + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize2; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = srcBLen >> 2U; +#if __RISCV_XLEN == 64 + py--; +#endif /* __RISCV_XLEN == 64 */ + while (k > 0U) + { +#if __RISCV_XLEN == 64 + acc064 = read_q31x2_ia((q31_t **)&px); + acc164 = read_q31x2_da((q31_t **)&py); + sum = __RV_KMAXDA32(sum, acc064, acc164); + acc064 = read_q31x2_ia((q31_t **)&px); + acc164 = read_q31x2_da((q31_t **)&py); + sum = __RV_KMAXDA32(sum, acc064, acc164); +#else + /* Perform the multiply-accumulates */ + sum += (q63_t) *px++ * (*py--); + sum += (q63_t) *px++ * (*py--); + sum += (q63_t) *px++ * (*py--); + sum += (q63_t) *px++ * (*py--); +#endif /* __RISCV_XLEN == 64 */ + + /* Decrement loop counter */ + k--; + } +#if __RISCV_XLEN == 64 + py++; +#endif /* __RISCV_XLEN == 64 */ + /* Loop unrolling: Compute remaining outputs */ + k = srcBLen % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = srcBLen; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += (q63_t) *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q31_t) (sum >> 31); + + /* Increment MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = (uint32_t) blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += (q63_t) *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q31_t) (sum >> 31); + + /* Increment the MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement the loop counter */ + blkCnt--; + } + } +#endif /*defined (RISCV_VECTOR)*/ + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1] + * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2] + * .... + * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2] + * sum += x[srcALen-1] * y[srcBLen-1] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The blockSize3 variable holds the number of MAC operations performed */ + count = srcBLen - 1U; + + /* Working pointer of inputA */ + if (firstIndex > srcALen) + { + pSrc1 = (pIn1 + firstIndex) - (srcBLen - 1U); + } + else + { + pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U); + } + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + while (blockSize3 > 0) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (RISCV_MATH_LOOPUNROLL) && !defined (RISCV_VECTOR) +#if __RISCV_XLEN == 64 + py--; +#endif /* __RISCV_XLEN == 64 */ + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + + while (k > 0U) + { +#if __RISCV_XLEN == 64 + acc064 = read_q31x2_ia((q31_t **)&px); + acc164 = read_q31x2_da((q31_t **)&py); + sum = __RV_KMAXDA32(sum, acc064, acc164); + acc064 = read_q31x2_ia((q31_t **)&px); + acc164 = read_q31x2_da((q31_t **)&py); + sum = __RV_KMAXDA32(sum, acc064, acc164); +#else + /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */ + sum += (q63_t) *px++ * *py--; + + /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */ + sum += (q63_t) *px++ * *py--; + + /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */ + sum += (q63_t) *px++ * *py--; + + /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */ + sum += (q63_t) *px++ * *py--; +#endif /* __RISCV_XLEN == 64 */ + /* Decrement loop counter */ + k--; + } +#if __RISCV_XLEN == 64 + py++; +#endif /* __RISCV_XLEN == 64 */ + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = count; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ +#if defined (RISCV_VECTOR) + uint32_t vblkCnt = blockSize3; /* Loop counter */ + size_t l; + vint32m4_t vx, vy; + vint64m1_t temp00m1; + ptrdiff_t bstride = -4; + l = vsetvl_e64m1(1); + temp00m1 = vmv_v_x_i64m1(0, l); + for (; (l = vsetvl_e32m4(vblkCnt)) > 0; vblkCnt -= l) { + vx = vle32_v_i32m4(px, l); + px += l; + vy = vlse32_v_i32m4(py, bstride, l); + py -= l; + sum += vmv_x_s_i64m1_i64(vredsum_vs_i64m8_i64m1(temp00m1, vwmul_vv_i64m8(vx, vy, l), temp00m1, l)); + } +#else + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* sum += x[srcALen-1] * y[srcBLen-1] */ + sum += (q63_t) *px++ * *py--; + + /* Decrement loop counter */ + k--; + } +#endif /*defined (RISCV_VECTOR)*/ + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q31_t) (sum >> 31); + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pSrc2; + + /* Decrement MAC count */ + count--; + + /* Decrement the loop counter */ + blockSize3--; + } + + /* Set status as RISCV_MATH_SUCCESS */ + status = RISCV_MATH_SUCCESS; + } + + /* Return to application */ + return (status); + +#else +/* alternate version for CM0_FAMILY */ + + const q31_t *pIn1 = pSrcA; /* InputA pointer */ + const q31_t *pIn2 = pSrcB; /* InputB pointer */ + q63_t sum; /* Accumulator */ + uint32_t i, j; /* Loop counters */ + riscv_status status; /* Status of Partial convolution */ + + /* Check for range of output samples to be calculated */ + if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U)))) + { + /* Set status as RISCV_MATH_ARGUMENT_ERROR */ + status = RISCV_MATH_ARGUMENT_ERROR; + } + else + { + /* Loop to calculate convolution for output length number of values */ + for (i = firstIndex; i <= (firstIndex + numPoints - 1); i++) + { + /* Initialize sum with zero to carry on MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0U; j <= i; j++) + { + /* Check the array limitations */ + if (((i - j) < srcBLen) && (j < srcALen)) + { + /* z[i] += x[i-j] * y[j] */ + sum += ((q63_t) pIn1[j] * pIn2[i - j]); + } + } + + /* Store the output in the destination buffer */ + pDst[i] = (q31_t) (sum >> 31U); + } + + /* Set status as RISCV_MATH_SUCCESS */ + status = RISCV_MATH_SUCCESS; + } + + /* Return to application */ + return (status); + +#endif /* #if !defined(RISCV_MATH_CM0_FAMILY) */ + +} + +/** + @} end of PartialConv group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_conv_partial_q7.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_conv_partial_q7.c new file mode 100644 index 00000000..d31c9e09 --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_conv_partial_q7.c @@ -0,0 +1,839 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_conv_partial_q7.c + * Description: Partial convolution of Q7 sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup PartialConv + @{ + */ + +/** + @brief Partial convolution of Q7 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written + @param[in] firstIndex is the first output sample to start with + @param[in] numPoints is the number of output points to be computed + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_ARGUMENT_ERROR : requested subset is not in the range [0 srcALen+srcBLen-2] + + @remark + Refer to \ref riscv_conv_partial_opt_q7() for a faster implementation of this function. + */ + +riscv_status riscv_conv_partial_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints) +{ + +#if defined (RISCV_MATH_DSP) || defined (RISCV_VECTOR) + + const q7_t *pIn1; /* InputA pointer */ + const q7_t *pIn2; /* InputB pointer */ + q7_t *pOut = pDst; /* Output pointer */ + const q7_t *px; /* Intermediate inputA pointer */ + const q7_t *py; /* Intermediate inputB pointer */ + const q7_t *pSrc1, *pSrc2; /* Intermediate pointers */ + q31_t sum; /* Accumulator */ + uint32_t j, k, count, blkCnt, check; /* Loop counters */ + int32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + riscv_status status; /* Status of Partial convolution */ + +#if defined (RISCV_MATH_LOOPUNROLL) + q31_t acc0, acc1, acc2, acc3; /* Accumulator */ + q31_t input1, input2; /* Temporary input variables */ + q15_t in1, in2; /* Temporary input variables */ + q7_t x0, x1, x2, x3, c0, c1; /* Temporary variables to hold state and coefficient values */ +// #if __RISCV_XLEN == 64 +// q63_t input164, input264; /* Temporary input variables */ +// q63_t in164, in264; /* Temporary input variables */ +// #endif /* __RISCV_XLEN == 64 */ +#endif + + /* Check for range of output samples to be calculated */ + if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U)))) + { + /* Set status as RISCV_MATH_ARGUMENT_ERROR */ + status = RISCV_MATH_ARGUMENT_ERROR; + } + else + { + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* Conditions to check which loopCounter holds + * the first and last indices of the output samples to be calculated. */ + check = firstIndex + numPoints; + blockSize3 = ((int32_t)check > (int32_t)srcALen) ? (int32_t)check - (int32_t)srcALen : 0; + blockSize3 = ((int32_t)firstIndex > (int32_t)srcALen - 1) ? blockSize3 - (int32_t)firstIndex + (int32_t)srcALen : blockSize3; + blockSize1 = ((int32_t) srcBLen - 1) - (int32_t) firstIndex; + blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1U)) ? blockSize1 : (int32_t)numPoints) : 0; + blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) + (int32_t) firstIndex); + blockSize2 = (blockSize2 > 0) ? blockSize2 : 0; + + /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */ + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* Set the output pointer to point to the firstIndex + * of the output sample to be calculated. */ + pOut = pDst + firstIndex; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[0] + * sum = x[0] * y[1] + x[1] * y[0] + * .... + * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed. + Since the partial convolution starts from firstIndex + Number of Macs to be performed is firstIndex + 1 */ + count = 1U + firstIndex; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + firstIndex; + py = pSrc2; + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* The first stage starts here */ + while (blockSize1 > 0) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (RISCV_MATH_LOOPUNROLL) && !defined(RISCV_VECTOR) +// #if __RISCV_XLEN == 64 +// py -= 7; +// #endif /* __RISCV_XLEN == 64 */ + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + + while (k > 0U) + { +// #if __RISCV_XLEN == 64 +// in164 = read_q7x8_ia ((q7_t **) &px); +// in264 = read_q7x8_da ((q7_t **) &py); +// sum = __RV_SMAQA(sum, in164, in264); +// #else + /* x[0] , x[1] */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* y[srcBLen - 1] , y[srcBLen - 2] */ + in1 = (q15_t) *py--; + in2 = (q15_t) *py--; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* x[0] * y[srcBLen - 1] */ + /* x[1] * y[srcBLen - 2] */ + sum = __SMLAD(input1, input2, sum); + + /* x[2] , x[3] */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* y[srcBLen - 3] , y[srcBLen - 4] */ + in1 = (q15_t) *py--; + in2 = (q15_t) *py--; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* x[2] * y[srcBLen - 3] */ + /* x[3] * y[srcBLen - 4] */ + sum = __SMLAD(input1, input2, sum); +// #endif /* __RISCV_XLEN == 64 */ + /* Decrement loop counter */ + k--; + } +// #if __RISCV_XLEN == 64 +// py += 7; +// #endif /* __RISCV_XLEN == 64 */ + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize k with number of samples */ + k = count; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ +#if defined (RISCV_VECTOR) + uint32_t vblkCnt = count; /* Loop counter */ + size_t l; + vint8m4_t vx, vy; + vint16m1_t temp00m1; + ptrdiff_t bstride = -1; + l = vsetvl_e16m1(vblkCnt); + temp00m1 = vmv_v_x_i16m1(0, l); + for (; (l = vsetvl_e8m4(vblkCnt)) > 0; vblkCnt -= l) { + vx = vle8_v_i8m4(px, l); + px += l; + vy = vlse8_v_i8m4(py, bstride, l); + py -= l; + sum += vmv_x_s_i16m1_i16(vredsum_vs_i16m8_i16m1(temp00m1, vwmul_vv_i16m8(vx, vy, l), temp00m1, l)); + } +#else + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += ((q31_t) * px++ * *py--); + + /* Decrement loop counter */ + k--; + } +#endif /*defined (RISCV_VECTOR)*/ + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q7_t) (__SSAT(sum >> 7, 8)); + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = ++pSrc2; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0] + * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0] + * .... + * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0] + */ + + /* Working pointer of inputA */ + if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0) + { + pSrc1 = pIn1 + firstIndex - srcBLen + 1; + } + else + { + pSrc1 = pIn1; + } + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* count is the index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ +#if defined (RISCV_VECTOR) + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + uint32_t vblkCnt = srcBLen; /* Loop counter */ + size_t l; + vint8m4_t vx, vy; + vint16m1_t temp00m1; + ptrdiff_t bstride = -1; + l = vsetvl_e16m1(1); + temp00m1 = vmv_v_x_i16m1(0, l); + for (; (l = vsetvl_e8m4(vblkCnt)) > 0; vblkCnt -= l) { + vx = vle8_v_i8m4(px, l); + px += l; + vy = vlse8_v_i8m4(py, bstride, l); + py -= l; + sum += vmv_x_s_i16m1_i16(vredsum_vs_i16m8_i16m1(temp00m1, vwmul_vv_i16m8(vx, vy, l), temp00m1, l)); + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q7_t) (__SSAT(sum >> 7U, 8)); + + /* Increment the MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } +#else + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = ((uint32_t) blockSize2 >> 2U); + + while (blkCnt > 0U) + { + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* read x[0], x[1], x[2] samples */ + x0 = *px++; + x1 = *px++; + x2 = *px++; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + do + { + /* Read y[srcBLen - 1] sample */ + c0 = *py--; + /* Read y[srcBLen - 2] sample */ + c1 = *py--; + + /* Read x[3] sample */ + x3 = *px++; + + /* x[0] and x[1] are packed */ + in1 = (q15_t) x0; + in2 = (q15_t) x1; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* y[srcBLen - 1] and y[srcBLen - 2] are packed */ + in1 = (q15_t) c0; + in2 = (q15_t) c1; + + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */ + acc0 = __SMLAD(input1, input2, acc0); + + /* x[1] and x[2] are packed */ + in1 = (q15_t) x1; + in2 = (q15_t) x2; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */ + acc1 = __SMLAD(input1, input2, acc1); + + /* x[2] and x[3] are packed */ + in1 = (q15_t) x2; + in2 = (q15_t) x3; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */ + acc2 = __SMLAD(input1, input2, acc2); + + /* Read x[4] sample */ + x0 = *px++; + + /* x[3] and x[4] are packed */ + in1 = (q15_t) x3; + in2 = (q15_t) x0; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */ + acc3 = __SMLAD(input1, input2, acc3); + + /* Read y[srcBLen - 3] sample */ + c0 = *py--; + /* Read y[srcBLen - 4] sample */ + c1 = *py--; + + /* Read x[5] sample */ + x1 = *px++; + + /* x[2] and x[3] are packed */ + in1 = (q15_t) x2; + in2 = (q15_t) x3; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* y[srcBLen - 3] and y[srcBLen - 4] are packed */ + in1 = (q15_t) c0; + in2 = (q15_t) c1; + + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */ + acc0 = __SMLAD(input1, input2, acc0); + + /* x[3] and x[4] are packed */ + in1 = (q15_t) x3; + in2 = (q15_t) x0; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */ + acc1 = __SMLAD(input1, input2, acc1); + + /* x[4] and x[5] are packed */ + in1 = (q15_t) x0; + in2 = (q15_t) x1; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */ + acc2 = __SMLAD(input1, input2, acc2); + + /* Read x[6] sample */ + x2 = *px++; + + /* x[5] and x[6] are packed */ + in1 = (q15_t) x1; + in2 = (q15_t) x2; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */ + acc3 = __SMLAD(input1, input2, acc3); + + } while (--k); + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Read y[srcBLen - 5] sample */ + c0 = *py--; + /* Read x[7] sample */ + x3 = *px++; + + /* Perform the multiply-accumulates */ + /* acc0 += x[4] * y[srcBLen - 5] */ + acc0 += ((q31_t) x0 * c0); + /* acc1 += x[5] * y[srcBLen - 5] */ + acc1 += ((q31_t) x1 * c0); + /* acc2 += x[6] * y[srcBLen - 5] */ + acc2 += ((q31_t) x2 * c0); + /* acc3 += x[7] * y[srcBLen - 5] */ + acc3 += ((q31_t) x3 * c0); + + /* Reuse the present samples for the next MAC */ + x0 = x1; + x1 = x2; + x2 = x3; + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q7_t) (__SSAT(acc0 >> 7, 8)); + *pOut++ = (q7_t) (__SSAT(acc1 >> 7, 8)); + *pOut++ = (q7_t) (__SSAT(acc2 >> 7, 8)); + *pOut++ = (q7_t) (__SSAT(acc3 >> 7, 8)); + + /* Increment the pointer pIn1 index, count by 4 */ + count += 4U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (uint32_t) blockSize2 % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize2; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = srcBLen >> 2U; + + while (k > 0U) + { + /* Reading two inputs of SrcA buffer and packing */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* Reading two inputs of SrcB buffer and packing */ + in1 = (q15_t) *py--; + in2 = (q15_t) *py--; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* Perform the multiply-accumulate */ + sum = __SMLAD(input1, input2, sum); + + /* Reading two inputs of SrcA buffer and packing */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* Reading two inputs of SrcB buffer and packing */ + in1 = (q15_t) *py--; + in2 = (q15_t) *py--; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* Perform the multiply-accumulate */ + sum = __SMLAD(input1, input2, sum); + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = srcBLen % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = srcBLen; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += ((q31_t) * px++ * *py--); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q7_t) (__SSAT(sum >> 7, 8)); + + /* Increment the pointer pIn1 index, count by 1 */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = (uint32_t) blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += ((q31_t) * px++ * *py--); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q7_t) (__SSAT(sum >> 7, 8)); + + /* Increment the MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement the loop counter */ + blkCnt--; + } + } +#endif /*defined (RISCV_VECTOR)*/ + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1] + * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2] + * .... + * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2] + * sum += x[srcALen-1] * y[srcBLen-1] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = srcBLen - 1U; + + /* Working pointer of inputA */ + if (firstIndex > srcALen) + { + pSrc1 = (pIn1 + firstIndex) - (srcBLen - 1U); + } + else + { + pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U); + } + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + while (blockSize3 > 0) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (RISCV_MATH_LOOPUNROLL) && !defined (RISCV_VECTOR) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + + while (k > 0U) + { + /* Reading two inputs, x[srcALen - srcBLen + 1] and x[srcALen - srcBLen + 2] of SrcA buffer and packing */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* Reading two inputs, y[srcBLen - 1] and y[srcBLen - 2] of SrcB buffer and packing */ + in1 = (q15_t) *py--; + in2 = (q15_t) *py--; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */ + /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */ + sum = __SMLAD(input1, input2, sum); + + /* Reading two inputs, x[srcALen - srcBLen + 3] and x[srcALen - srcBLen + 4] of SrcA buffer and packing */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* Reading two inputs, y[srcBLen - 3] and y[srcBLen - 4] of SrcB buffer and packing */ + in1 = (q15_t) *py--; + in2 = (q15_t) *py--; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */ + /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */ + sum = __SMLAD(input1, input2, sum); + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = count; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ +#if defined (RISCV_VECTOR) + uint32_t vblkCnt = blockSize3; /* Loop counter */ + size_t l; + vint8m4_t vx, vy; + vint16m1_t temp00m1; + ptrdiff_t bstride = -1; + l = vsetvl_e16m1(1); + temp00m1 = vmv_v_x_i16m1(0, l); + for (; (l = vsetvl_e8m4(vblkCnt)) > 0; vblkCnt -= l) { + vx = vle8_v_i8m4(px, l); + px += l; + vy = vlse8_v_i8m4(py, bstride, l); + py -= l; + sum += vmv_x_s_i16m1_i16(vredsum_vs_i16m8_i16m1(temp00m1, vwmul_vv_i16m8(vx, vy, l), temp00m1, l)); + } +#else + while (k > 0U) + { + /* Perform the multiply-accumulates */ + /* sum += x[srcALen-1] * y[srcBLen-1] */ + sum += ((q31_t) * px++ * *py--); + + /* Decrement loop counter */ + k--; + } +#endif /*defined (RISCV_VECTOR)*/ + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q7_t) (__SSAT(sum >> 7, 8)); + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pSrc2; + + /* Decrement MAC count */ + count--; + + /* Decrement the loop counter */ + blockSize3--; + } + + /* Set status as RISCV_MATH_SUCCESS */ + status = RISCV_MATH_SUCCESS; + } + + /* Return to application */ + return (status); + +#else +/* alternate version for CM0_FAMILY */ + + const q7_t *pIn1 = pSrcA; /* InputA pointer */ + const q7_t *pIn2 = pSrcB; /* InputB pointer */ + q31_t sum; /* Accumulator */ + uint32_t i, j; /* Loop counters */ + riscv_status status; /* Status of Partial convolution */ + + /* Check for range of output samples to be calculated */ + if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U)))) + { + /* Set status as RISCV_MATH_ARGUMENT_ERROR */ + status = RISCV_MATH_ARGUMENT_ERROR; + } + else + { + /* Loop to calculate convolution for output length number of values */ + for (i = firstIndex; i <= (firstIndex + numPoints - 1); i++) + { + /* Initialize sum with zero to carry on MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0U; j <= i; j++) + { + /* Check the array limitations */ + if (((i - j) < srcBLen) && (j < srcALen)) + { + /* z[i] += x[i-j] * y[j] */ + sum += ((q15_t) pIn1[j] * (pIn2[i - j])); + } + } + + /* Store the output in the destination buffer */ + pDst[i] = (q7_t) __SSAT((sum >> 7U), 8U); + } + + /* Set status as RISCV_MATH_SUCCESS */ + status = RISCV_MATH_SUCCESS; + } + + /* Return to application */ + return (status); + +#endif /* #if !defined(RISCV_MATH_CM0_FAMILY) */ + +} + +/** + @} end of PartialConv group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_conv_q15.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_conv_q15.c new file mode 100644 index 00000000..a822139b --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_conv_q15.c @@ -0,0 +1,815 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_conv_q15.c + * Description: Convolution of Q15 sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Conv + @{ + */ + +/** + @brief Convolution of Q15 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + Both inputs are in 1.15 format and multiplications yield a 2.30 result. + The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + This approach provides 33 guard bits and there is no risk of overflow. + The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format. + + @remark + Refer to \ref riscv_conv_fast_q15() for a faster but less precise version of this function. + @remark + Refer to \ref riscv_conv_opt_q15() for a faster implementation of this function using scratch buffers. + */ +void riscv_conv_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst) +{ + +#if defined (RISCV_MATH_DSP) || defined (RISCV_VECTOR) + + const q15_t *pIn1; /* InputA pointer */ + const q15_t *pIn2; /* InputB pointer */ + q15_t *pOut = pDst; /* Output pointer */ + q63_t sum, acc0, acc1, acc2, acc3; /* Accumulators */ + const q15_t *px; /* Intermediate inputA pointer */ + const q15_t *py; /* Intermediate inputB pointer */ + const q15_t *pSrc1, *pSrc2; /* Intermediate pointers */ + q31_t x0, x1, x2, x3, c0; /* Temporary input variables to hold state and coefficient values */ + uint32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + uint32_t j, k, count, blkCnt; /* Loop counters */ + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */ + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* The algorithm is implemented in three stages. + The loop counters of each stage is initiated here. */ + blockSize1 = srcBLen - 1U; + blockSize2 = srcALen - (srcBLen - 1U); + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[0] + * sum = x[0] * y[1] + x[1] * y[0] + * .... + * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = 1U; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + py = pIn2; + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* For loop unrolling by 4, this stage is divided into two. */ + /* First part of this stage computes the MAC operations less than 4 */ + /* Second part of this stage computes the MAC operations greater than or equal to 4 */ +#if defined (RISCV_VECTOR) + while (blockSize1 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + uint32_t vblkCnt = count; /* Loop counter */ + size_t l; + vint16m4_t vx, vy; + vint32m1_t temp00m1; + ptrdiff_t bstride = -2; + l = vsetvl_e32m1(vblkCnt); + temp00m1 = vmv_v_x_i32m1(0, l); + for (; (l = vsetvl_e16m4(vblkCnt)) > 0; vblkCnt -= l) { + vx = vle16_v_i16m4(px, l); + px += l; + vy = vlse16_v_i16m4(py, bstride, l); + py -= l; + sum += vmv_x_s_i32m1_i32(vredsum_vs_i32m8_i32m1(temp00m1, vwmul_vv_i32m8(vx, vy, l), temp00m1, l)); + } + + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT((sum >> 15), 16)); + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = pIn2 + (count - 1U); + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } +#else + /* The first part of the stage starts here */ + while ((count < 4U) && (blockSize1 > 0U)) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Loop over number of MAC operations between + * inputA samples and inputB samples */ + k = count; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum = __SMLALD(*px++, *py--, sum); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT((sum >> 15), 16)); + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = pIn2 + count; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* The second part of the stage starts here */ + /* The internal loop, over count, is unrolled by 4 */ + /* To, read the last two inputB samples using SIMD: + * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */ + py = py - 1; +#if __RISCV_XLEN == 64 + py = py - 2; +#endif /* __RISCV_XLEN == 64 */ + + while (blockSize1 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = count >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulate */ + +#if __RISCV_XLEN == 64 + sum = __RV_SMALXDA(sum, read_q15x4_ia ((q15_t **) &px), read_q15x4_da ((q15_t **) &py)); +#else + /* x[0], x[1] are multiplied with y[srcBLen - 1], y[srcBLen - 2] respectively */ + sum = __RV_SMALXDA(sum, read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py)); + /* x[2], x[3] are multiplied with y[srcBLen - 3], y[srcBLen - 4] respectively */ + sum = __RV_SMALXDA(sum, read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py)); +#endif /* __RISCV_XLEN == 64 */ + + /* Decrement loop counter */ + k--; + } + + /* For the next MAC operations, the pointer py is used without SIMD + * So, py is incremented by 1 */ + py = py + 1U; +#if __RISCV_XLEN == 64 + py = py + 2; +#endif /* __RISCV_XLEN == 64 */ + /* If the count is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = count % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum = __SMLALD(*px++, *py--, sum); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT((sum >> 15), 16)); + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = pIn2 + (count - 1U); + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } +#endif /*defined (RISCV_VECTOR)*/ + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0] + * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0] + * .... + * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0] + */ + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* count is the index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ +#if defined (RISCV_VECTOR) + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + uint32_t vblkCnt = srcBLen; /* Loop counter */ + size_t l; + vint16m4_t vx, vy; + vint32m1_t temp00m1; + ptrdiff_t bstride = -2; + l = vsetvl_e32m1(1); + temp00m1 = vmv_v_x_i32m1(0, l); + for (; (l = vsetvl_e16m4(vblkCnt)) > 0; vblkCnt -= l) { + vx = vle16_v_i16m4(px, l); + px += l; + vy = vlse16_v_i16m4(py, bstride, l); + py -= l; + sum += vmv_x_s_i32m1_i32(vredsum_vs_i32m8_i32m1(temp00m1, vwmul_vv_i32m8(vx, vy, l), temp00m1, l)); + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT(sum >> 15, 16)); + + /* Increment the MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement the loop counter */ + blkCnt--; + } +#else + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize2 >> 2U; + + while (blkCnt > 0U) + { + py = py - 1U; + + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* read x[0], x[1] samples */ + x0 = read_q15x2 ((q15_t *) px); + + /* read x[1], x[2] samples */ + x1 = read_q15x2 ((q15_t *) px + 1); + px += 2U; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + do + { + /* Read the last two inputB samples using SIMD: + * y[srcBLen - 1] and y[srcBLen - 2] */ + c0 = read_q15x2_da ((q15_t **) &py); + + /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */ + acc0 = __SMLALDX(x0, c0, acc0); + + /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */ + acc1 = __SMLALDX(x1, c0, acc1); + + /* Read x[2], x[3] */ + x2 = read_q15x2 ((q15_t *) px); + + /* Read x[3], x[4] */ + x3 = read_q15x2 ((q15_t *) px + 1); + + /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */ + acc2 = __SMLALDX(x2, c0, acc2); + + /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */ + acc3 = __SMLALDX(x3, c0, acc3); + + /* Read y[srcBLen - 3] and y[srcBLen - 4] */ + c0 = read_q15x2_da ((q15_t **) &py); + + /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */ + acc0 = __SMLALDX(x2, c0, acc0); + + /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */ + acc1 = __SMLALDX(x3, c0, acc1); + + /* Read x[4], x[5] */ + x0 = read_q15x2 ((q15_t *) px + 2); + + /* Read x[5], x[6] */ + x1 = read_q15x2 ((q15_t *) px + 3); + + px += 4U; + + /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */ + acc2 = __SMLALDX(x0, c0, acc2); + + /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */ + acc3 = __SMLALDX(x1, c0, acc3); + + } while (--k); + + /* For the next MAC operations, SIMD is not used + * So, the 16 bit pointer if inputB, py is updated */ + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + if (k == 1U) + { + /* Read y[srcBLen - 5] */ + c0 = *(py + 1); + c0 = c0 & 0x0000FFFF; + + /* Read x[7] */ + x3 = read_q15x2 ((q15_t *) px); + px++; + + /* Perform the multiply-accumulate */ + acc0 = __RV_SMALDA(acc0, x0, c0); + acc1 = __RV_SMALDA(acc1, x1, c0); + acc2 = __RV_SMALXDA(acc2, x1, c0); + acc3 = __RV_SMALXDA(acc3, x3, c0); + } + + if (k == 2U) + { + /* Read y[srcBLen - 5], y[srcBLen - 6] */ + c0 = read_q15x2 ((q15_t *) py); + + /* Read x[7], x[8] */ + x3 = read_q15x2 ((q15_t *) px); + + /* Read x[9] */ + x2 = read_q15x2 ((q15_t *) px + 1); + px += 2U; + + /* Perform the multiply-accumulate */ + acc0 = __RV_SMALXDA(acc0, x0, c0); + acc1 = __RV_SMALXDA(acc1, x1, c0); + acc2 = __RV_SMALXDA(acc2, x3, c0); + acc3 = __RV_SMALXDA(acc3, x2, c0); + } + + if (k == 3U) + { + /* Read y[srcBLen - 5], y[srcBLen - 6] */ + c0 = read_q15x2 ((q15_t *) py); + + /* Read x[7], x[8] */ + x3 = read_q15x2 ((q15_t *) px); + + /* Read x[9] */ + x2 = read_q15x2 ((q15_t *) px + 1); + + /* Perform the multiply-accumulate */ + acc0 = __RV_SMALXDA(acc0, x0, c0); + acc1 = __RV_SMALXDA(acc1, x1, c0); + acc2 = __RV_SMALXDA(acc2, x3, c0); + acc3 = __RV_SMALXDA(acc3, x2, c0); + + c0 = *(py-1); + c0 = c0 & 0x0000FFFF; + + /* Read x[10] */ + x3 = read_q15x2 ((q15_t *) px + 2); + px += 3U; + + /* Perform the multiply-accumulates */ + acc0 = __RV_SMALXDA(acc0, x1, c0); + acc1 = __RV_SMALDA(acc1, x2, c0); + acc2 = __RV_SMALXDA(acc2, x2, c0); + acc3 = __RV_SMALXDA(acc3, x3, c0); + } + + /* Store the result in the accumulator in the destination buffer. */ + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16)); + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16)); + + /* Increment the pointer pIn1 index, count by 4 */ + count += 4U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize2 % 0x4U; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + +// #if __RISCV_XLEN == 64 +// py -= 4; +// q63_t acc064, acc164; +// #endif /* __RISCV_XLEN == 64 */ + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulates */ +// #if __RISCV_XLEN == 64 +// acc064 = read_q15x4_ia((q15_t **) &px); +// acc164 = read_q15x4_da((q15_t **) &py); +// sum = __RV_KMADA(sum, acc064, acc164); +// #else + sum += (q63_t) ((q31_t) *px++ * *py--); + sum += (q63_t) ((q31_t) *px++ * *py--); + sum += (q63_t) ((q31_t) *px++ * *py--); + sum += (q63_t) ((q31_t) *px++ * *py--); +// #endif /* __RISCV_XLEN == 64 */ + + /* Decrement loop counter */ + k--; + } + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum += (q63_t) ((q31_t) *px++ * *py--); + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT(sum >> 15, 16)); + + /* Increment the pointer pIn1 index, count by 1 */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += (q63_t) ((q31_t) *px++ * *py--); + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT(sum >> 15, 16)); + + /* Increment the MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement the loop counter */ + blkCnt--; + } + } +#endif /*defined (RISCV_VECTOR)*/ + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1] + * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2] + * .... + * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2] + * sum += x[srcALen-1] * y[srcBLen-1] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The blockSize3 variable holds the number of MAC operations performed */ + blockSize3 = srcBLen - 1U; + + /* Working pointer of inputA */ + pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U); + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + pIn2 = pSrc2 - 1U; + py = pIn2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + /* For loop unrolling by 4, this stage is divided into two. */ + /* First part of this stage computes the MAC operations greater than 4 */ + /* Second part of this stage computes the MAC operations less than or equal to 4 */ +#if defined (RISCV_VECTOR) + while (blockSize3 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + uint32_t vblkCnt = blockSize3; /* Loop counter */ + size_t l; + vint16m4_t vx, vy; + vint32m1_t temp00m1; + ptrdiff_t bstride = -2; + l = vsetvl_e32m1(1); + temp00m1 = vmv_v_x_i32m1(0, l); + for (; (l = vsetvl_e16m4(vblkCnt)) > 0; vblkCnt -= l) { + vx = vle16_v_i16m4(px, l); + px += l; + vy = vlse16_v_i16m4(py, bstride, l); + py -= l; + sum += vmv_x_s_i32m1_i32(vredsum_vs_i32m8_i32m1(temp00m1, vwmul_vv_i32m8(vx, vy, l), temp00m1, l)); + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT((sum >> 15), 16)); + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pSrc2; + + /* Decrement loop counter */ + blockSize3--; + } + +#else + /* The first part of the stage starts here */ + j = blockSize3 >> 2U; + + while ((j > 0U) && (blockSize3 > 0U)) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = blockSize3 >> 2U; + +#if __RISCV_XLEN == 64 + py -= 2; +#endif /* __RISCV_XLEN == 64 */ + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulate */ + +#if __RISCV_XLEN == 64 + sum = __SMLALDX(read_q15x4_ia ((q15_t **) &px), read_q15x4_da ((q15_t **) &py), sum); +#else + /* x[srcALen - srcBLen + 1], x[srcALen - srcBLen + 2] are multiplied + * with y[srcBLen - 1], y[srcBLen - 2] respectively */ + sum = __SMLALDX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum); + /* x[srcALen - srcBLen + 3], x[srcALen - srcBLen + 4] are multiplied + * with y[srcBLen - 3], y[srcBLen - 4] respectively */ + sum = __SMLALDX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum); +#endif /* __RISCV_XLEN == 64 */ + + /* Decrement loop counter */ + k--; + } + + /* For the next MAC operations, the pointer py is used without SIMD + * So, py is incremented by 1 */ + py = py + 1U; +#if __RISCV_XLEN == 64 + py += 2; +#endif /* __RISCV_XLEN == 64 */ + /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = blockSize3 % 0x4U; + + while (k > 0U) + { + /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */ + sum = __SMLALD(*px++, *py--, sum); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT((sum >> 15), 16)); + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pIn2; + + /* Decrement loop counter */ + blockSize3--; + + j--; + } + + /* The second part of the stage starts here */ + /* SIMD is not used for the next MAC operations, + * so pointer py is updated to read only one sample at a time */ + py = py + 1U; + + while (blockSize3 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = blockSize3; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + /* sum += x[srcALen-1] * y[srcBLen-1] */ + sum = __SMLALD(*px++, *py--, sum); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT((sum >> 15), 16)); + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pSrc2; + + /* Decrement loop counter */ + blockSize3--; + } +#endif /*defined (RISCV_VECTOR)*/ +#else /* #if defined (RISCV_MATH_DSP) */ + + const q15_t *pIn1 = pSrcA; /* InputA pointer */ + const q15_t *pIn2 = pSrcB; /* InputB pointer */ + q63_t sum; /* Accumulator */ + uint32_t i, j; /* Loop counters */ + + /* Loop to calculate convolution for output length number of values */ + for (i = 0; i < (srcALen + srcBLen - 1); i++) + { + /* Initialize sum with zero to carry on MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0U; j <= i; j++) + { + /* Check the array limitations */ + if (((i - j) < srcBLen) && (j < srcALen)) + { + /* z[i] += x[i-j] * y[j] */ + sum += ((q31_t) pIn1[j] * pIn2[i - j]); + } + } + + /* Store the output in the destination buffer */ + pDst[i] = (q15_t) __SSAT((sum >> 15U), 16U); + } + +#endif /* #if defined (RISCV_MATH_DSP) */ + +} + +/** + @} end of Conv group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_conv_q31.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_conv_q31.c new file mode 100644 index 00000000..1061ee0c --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_conv_q31.c @@ -0,0 +1,656 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_conv_q31.c + * Description: Convolution of Q31 sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Conv + @{ + */ + +/** + @brief Convolution of Q31 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + There is no saturation on intermediate additions. + Thus, if the accumulator overflows it wraps around and distorts the result. + The input signals should be scaled down to avoid intermediate overflows. + Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows, + as maximum of min(srcALen, srcBLen) number of additions are carried internally. + The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result. + + @remark + Refer to \ref riscv_conv_fast_q31() for a faster but less precise implementation of this function. + */ +void riscv_conv_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst) +{ + + + + const q31_t *pIn1; /* InputA pointer */ + const q31_t *pIn2; /* InputB pointer */ + q31_t *pOut = pDst; /* Output pointer */ + const q31_t *px; /* Intermediate inputA pointer */ + const q31_t *py; /* Intermediate inputB pointer */ + const q31_t *pSrc1, *pSrc2; /* Intermediate pointers */ + q63_t sum; /* Accumulators */ + uint32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + uint32_t j, k, count, blkCnt; /* Loop counters */ + +#if defined (RISCV_MATH_LOOPUNROLL) + q63_t acc0, acc1, acc2; /* Accumulators */ + q31_t x0, x1, x2, c0; /* Temporary variables to hold state and coefficient values */ +#if __RISCV_XLEN == 64 + q63_t acc064, acc164, acc264; +#endif /* __RISCV_XLEN == 64 */ +#endif + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */ + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* The algorithm is implemented in three stages. + The loop counters of each stage is initiated here. */ + blockSize1 = srcBLen - 1U; + blockSize2 = srcALen - (srcBLen - 1U); + blockSize3 = blockSize1; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[0] + * sum = x[0] * y[1] + x[1] * y[0] + * .... + * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = 1U; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + py = pIn2; + + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* The first stage starts here */ + while (blockSize1 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (RISCV_MATH_LOOPUNROLL) && !defined (RISCV_VECTOR) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; +#if __RISCV_XLEN == 64 + py--; +#endif /* __RISCV_XLEN == 64 */ + while (k > 0U) + { +#if __RISCV_XLEN == 64 + acc064 = read_q31x2_ia((q31_t **)&px); + acc164 = read_q31x2_da((q31_t **)&py); + sum = __RV_KMAXDA32(sum, acc064, acc164); + acc064 = read_q31x2_ia((q31_t **)&px); + acc164 = read_q31x2_da((q31_t **)&py); + sum = __RV_KMAXDA32(sum, acc064, acc164); +#else + /* x[0] * y[srcBLen - 1] */ + sum += (q63_t) *px++ * (*py--); + + /* x[1] * y[srcBLen - 2] */ + sum += (q63_t) *px++ * (*py--); + + /* x[2] * y[srcBLen - 3] */ + sum += (q63_t) *px++ * (*py--); + + /* x[3] * y[srcBLen - 4] */ + sum += (q63_t) *px++ * (*py--); +#endif /* __RISCV_XLEN == 64 */ + + /* Decrement loop counter */ + k--; + } +#if __RISCV_XLEN == 64 + py++; +#endif /* __RISCV_XLEN == 64 */ + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize k with number of samples */ + k = count; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ +#if defined (RISCV_VECTOR) + uint32_t vblkCnt = count; /* Loop counter */ + size_t l; + vint32m4_t vx, vy; + vint64m1_t temp00m1; + ptrdiff_t bstride = -4; + l = vsetvl_e64m1(1); + temp00m1 = vmv_v_x_i64m1(0, l); + for (; (l = vsetvl_e32m4(vblkCnt)) > 0; vblkCnt -= l) { + vx = vle32_v_i32m4(px, l); + px += l; + vy = vlse32_v_i32m4(py, bstride, l); + py -= l; + sum += vmv_x_s_i64m1_i64(vredsum_vs_i64m8_i64m1(temp00m1, vwmul_vv_i64m8(vx, vy, l), temp00m1, l)); + } +#else + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += (q63_t) *px++ * *py--; + + /* Decrement loop counter */ + k--; + } +#endif /*defined (RISCV_VECTOR)*/ + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q31_t) (sum >> 31); + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = pIn2 + count; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0] + * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0] + * .... + * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0] + */ + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* count is index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ +#if defined (RISCV_VECTOR) + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + uint32_t vblkCnt = srcBLen; /* Loop counter */ + size_t l; + vint32m4_t vx, vy; + vint64m1_t temp00m1; + ptrdiff_t bstride = -4; + l = vsetvl_e64m1(1); + temp00m1 = vmv_v_x_i64m1(0, l); + for (; (l = vsetvl_e32m4(vblkCnt)) > 0; vblkCnt -= l) { + vx = vle32_v_i32m4(px, l); + px += l; + vy = vlse32_v_i32m4(py, bstride, l); + py -= l; + sum += vmv_x_s_i64m1_i64(vredsum_vs_i64m8_i64m1(temp00m1, vwmul_vv_i64m8(vx, vy, l), temp00m1, l)); + } + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q31_t) (sum >> 31); + + /* Increment MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } +#else + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unroll by 3 */ + blkCnt = blockSize2 / 3; + + while (blkCnt > 0U) + { + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + + /* read x[0], x[1], x[2] samples */ + x0 = *px++; + x1 = *px++; + + /* Apply loop unrolling and compute 3 MACs simultaneously. */ + k = srcBLen / 3; + + /* First part of the processing with loop unrolling. Compute 3 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 2 samples. */ + do + { + /* Read y[srcBLen - 1] sample */ + c0 = *(py); + /* Read x[3] sample */ + x2 = *(px); + + /* Perform the multiply-accumulate */ + /* acc0 += x[0] * y[srcBLen - 1] */ + acc0 += ((q63_t) x0 * c0); + /* acc1 += x[1] * y[srcBLen - 1] */ + acc1 += ((q63_t) x1 * c0); + /* acc2 += x[2] * y[srcBLen - 1] */ + acc2 += ((q63_t) x2 * c0); + + /* Read y[srcBLen - 2] sample */ + c0 = *(py - 1U); + /* Read x[4] sample */ + x0 = *(px + 1U); + + /* Perform the multiply-accumulate */ + /* acc0 += x[1] * y[srcBLen - 2] */ + acc0 += ((q63_t) x1 * c0); + /* acc1 += x[2] * y[srcBLen - 2] */ + acc1 += ((q63_t) x2 * c0); + /* acc2 += x[3] * y[srcBLen - 2] */ + acc2 += ((q63_t) x0 * c0); + + /* Read y[srcBLen - 3] sample */ + c0 = *(py - 2U); + /* Read x[5] sample */ + x1 = *(px + 2U); + + /* Perform the multiply-accumulate */ + /* acc0 += x[2] * y[srcBLen - 3] */ + acc0 += ((q63_t) x2 * c0); + /* acc1 += x[3] * y[srcBLen - 2] */ + acc1 += ((q63_t) x0 * c0); + /* acc2 += x[4] * y[srcBLen - 2] */ + acc2 += ((q63_t) x1 * c0); + + /* update scratch pointers */ + px += 3U; + py -= 3U; + + } while (--k); + + /* If the srcBLen is not a multiple of 3, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen - (3 * (srcBLen / 3)); + + while (k > 0U) + { + /* Read y[srcBLen - 5] sample */ + c0 = *py--; + /* Read x[7] sample */ + x2 = *px++; + + /* Perform the multiply-accumulates */ + /* acc0 += x[4] * y[srcBLen - 5] */ + acc0 += ((q63_t) x0 * c0); + /* acc1 += x[5] * y[srcBLen - 5] */ + acc1 += ((q63_t) x1 * c0); + /* acc2 += x[6] * y[srcBLen - 5] */ + acc2 += ((q63_t) x2 * c0); + + /* Reuse the present samples for the next MAC */ + x0 = x1; + x1 = x2; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q31_t) (acc0 >> 31); + *pOut++ = (q31_t) (acc1 >> 31); + *pOut++ = (q31_t) (acc2 >> 31); + + /* Increment the pointer pIn1 index, count by 3 */ + count += 3U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize2 - 3 * (blockSize2 / 3); + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize2; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = srcBLen >> 2U; +#if __RISCV_XLEN == 64 + py--; +#endif /* __RISCV_XLEN == 64 */ + while (k > 0U) + { +#if __RISCV_XLEN == 64 + acc064 = read_q31x2_ia((q31_t **)&px); + acc164 = read_q31x2_da((q31_t **)&py); + sum = __RV_KMAXDA32(sum, acc064, acc164); + acc064 = read_q31x2_ia((q31_t **)&px); + acc164 = read_q31x2_da((q31_t **)&py); + sum = __RV_KMAXDA32(sum, acc064, acc164); +#else + /* Perform the multiply-accumulates */ + sum += (q63_t) *px++ * *py--; + sum += (q63_t) *px++ * *py--; + sum += (q63_t) *px++ * *py--; + sum += (q63_t) *px++ * *py--; +#endif /* __RISCV_XLEN == 64 */ + + /* Decrement loop counter */ + k--; + } +#if __RISCV_XLEN == 64 + py++; +#endif /* __RISCV_XLEN == 64 */ + /* Loop unrolling: Compute remaining outputs */ + k = srcBLen % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = srcBLen; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += (q63_t) *px++ * *py--; + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q31_t) (sum >> 31); + + /* Increment MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += (q63_t) *px++ * *py--; + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q31_t) (sum >> 31); + + /* Increment MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + } +#endif /*defined (RISCV_VECTOR)*/ + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1] + * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2] + * .... + * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2] + * sum += x[srcALen-1] * y[srcBLen-1] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The blockSize3 variable holds the number of MAC operations performed */ + + /* Working pointer of inputA */ + pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U); + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + while (blockSize3 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (RISCV_MATH_LOOPUNROLL) && !defined (RISCV_VECTOR) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = blockSize3 >> 2U; +#if __RISCV_XLEN == 64 + py--; +#endif /* __RISCV_XLEN == 64 */ + while (k > 0U) + { +#if __RISCV_XLEN == 64 + acc064 = read_q31x2_ia((q31_t **)&px); + acc164 = read_q31x2_da((q31_t **)&py); + sum = __RV_KMAXDA32(sum, acc064, acc164); + acc064 = read_q31x2_ia((q31_t **)&px); + acc164 = read_q31x2_da((q31_t **)&py); + sum = __RV_KMAXDA32(sum, acc064, acc164); +#else + /* Perform the multiply-accumulate */ + /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */ + sum += (q63_t) *px++ * *py--; + + /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */ + sum += (q63_t) *px++ * *py--; + + /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */ + sum += (q63_t) *px++ * *py--; + + /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */ + sum += (q63_t) *px++ * *py--; +#endif /* __RISCV_XLEN == 64 */ + + /* Decrement loop counter */ + k--; + } +#if __RISCV_XLEN == 64 + py++; +#endif /* __RISCV_XLEN == 64 */ + /* Loop unrolling: Compute remaining outputs */ + k = blockSize3 % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = blockSize3; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ +#if defined (RISCV_VECTOR) + uint32_t vblkCnt = blockSize3; /* Loop counter */ + size_t l; + vint32m4_t vx, vy; + vint64m1_t temp00m1; + ptrdiff_t bstride = -4; + l = vsetvl_e64m1(1); + temp00m1 = vmv_v_x_i64m1(0, l); + for (; (l = vsetvl_e32m4(vblkCnt)) > 0; vblkCnt -= l) { + vx = vle32_v_i32m4(px, l); + px += l; + vy = vlse32_v_i32m4(py, bstride, l); + py -= l; + sum += vmv_x_s_i64m1_i64(vredsum_vs_i64m8_i64m1(temp00m1, vwmul_vv_i64m8(vx, vy, l), temp00m1, l)); + } +#else + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* sum += x[srcALen-1] * y[srcBLen-1] */ + sum += (q63_t) *px++ * *py--; + + /* Decrement loop counter */ + k--; + } +#endif /*defined (RISCV_VECTOR)*/ + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q31_t) (sum >> 31); + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pSrc2; + + /* Decrement loop counter */ + blockSize3--; + } + + +} + +/** + @} end of Conv group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_conv_q7.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_conv_q7.c new file mode 100644 index 00000000..b8fc1595 --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_conv_q7.c @@ -0,0 +1,761 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_conv_q7.c + * Description: Convolution of Q7 sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Conv + @{ + */ + +/** + @brief Convolution of Q7 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 32-bit internal accumulator. + Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result. + The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format. + This approach provides 17 guard bits and there is no risk of overflow as long as max(srcALen, srcBLen)<131072. + The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and then saturated to 1.7 format. + @remark + Refer to \ref riscv_conv_opt_q7() for a faster implementation of this function. + */ +void riscv_conv_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst) +{ + + + const q7_t *pIn1; /* InputA pointer */ + const q7_t *pIn2; /* InputB pointer */ + q7_t *pOut = pDst; /* Output pointer */ + const q7_t *px; /* Intermediate inputA pointer */ + const q7_t *py; /* Intermediate inputB pointer */ + const q7_t *pSrc1, *pSrc2; /* Intermediate pointers */ + q31_t sum; /* Accumulators */ + uint32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + uint32_t j, k, count, blkCnt; /* Loop counters */ + +#if defined (RISCV_MATH_LOOPUNROLL) + q31_t acc0, acc1, acc2, acc3; /* Accumulators */ + q31_t input1, input2; /* Temporary input variables */ + q15_t in1, in2; /* Temporary input variables */ + q7_t x0, x1, x2, x3, c0, c1; /* Temporary variables to hold state and coefficient values */ + +#if __RISCV_XLEN == 64 + q63_t input164, input264; /* Temporary input variables */ + q63_t in164, in264; /* Temporary input variables */ +#endif /* __RISCV_XLEN == 64 */ +#endif + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */ + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* The algorithm is implemented in three stages. + The loop counters of each stage is initiated here. */ + blockSize1 = srcBLen - 1U; + blockSize2 = srcALen - (srcBLen - 1U); + blockSize3 = blockSize1; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[0] + * sum = x[0] * y[1] + x[1] * y[0] + * .... + * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = 1U; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + py = pIn2; + + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* The first stage starts here */ + while (blockSize1 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (RISCV_MATH_LOOPUNROLL) && !defined (ARN_VECTOR) +#if __RISCV_XLEN == 64 + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 3U; +#else + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; +#endif /* __RISCV_XLEN == 64 */ + +#if __RISCV_XLEN == 64 + py -= 7; +#endif /* __RISCV_XLEN == 64 */ + while (k > 0U) + { + +#if __RISCV_XLEN == 64 + in164 = read_q7x8_ia ((q7_t **) &px); + in264 = read_q7x8_da ((q7_t **) &py); + sum = __RV_SMAQA(sum, in164, in264); +#else + /* x[0] , x[1] */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* y[srcBLen - 1] , y[srcBLen - 2] */ + in1 = (q15_t) *py--; + in2 = (q15_t) *py--; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* x[0] * y[srcBLen - 1] */ + /* x[1] * y[srcBLen - 2] */ + sum = __RV_KMADA(sum, input1, input2); + + /* x[2] , x[3] */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* y[srcBLen - 3] , y[srcBLen - 4] */ + in1 = (q15_t) *py--; + in2 = (q15_t) *py--; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* x[2] * y[srcBLen - 3] */ + /* x[3] * y[srcBLen - 4] */ + sum = __RV_KMADA(sum, input1, input2); + +#endif /* __RISCV_XLEN == 64 */ + /* Decrement loop counter */ + k--; + } + +#if __RISCV_XLEN == 64 + py +=7; +#endif /* __RISCV_XLEN == 64 */ +#if __RISCV_XLEN == 64 + /* Loop unrolling: Compute 4 outputs at a time */ + k = count % 0x8U; +#else + /* Loop unrolling: Compute 4 outputs at a time */ + k = count % 0x4U; +#endif /* __RISCV_XLEN == 64 */ + +#else + + /* Initialize k with number of samples */ + k = count; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ +#if defined (RISCV_VECTOR) + uint32_t vblkCnt = count; /* Loop counter */ + size_t l; + vint8m4_t vx, vy; + vint16m1_t temp00m1; + ptrdiff_t bstride = -1; + l = vsetvl_e16m1(1); + temp00m1 = vmv_v_x_i16m1(0, l); + for (; (l = vsetvl_e8m4(vblkCnt)) > 0; vblkCnt -= l) { + vx = vle8_v_i8m4(px, l); + px += l; + vy = vlse8_v_i8m4(py, bstride, l); + py -= l; + sum += vmv_x_s_i16m1_i16(vredsum_vs_i16m8_i16m1(temp00m1, vwmul_vv_i16m8(vx, vy, l), temp00m1, l)); + } +#else + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += ((q15_t) *px++ * *py--); + + /* Decrement loop counter */ + k--; + } +#endif /*defined (RISCV_VECTOR)*/ + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q7_t) (__SSAT(sum >> 7U, 8)); + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = pIn2 + count; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0] + * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0] + * .... + * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0] + */ + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* count is index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ +#if defined (RISCV_VECTOR) + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + uint32_t vblkCnt = srcBLen; /* Loop counter */ + size_t l; + vint8m4_t vx, vy; + vint16m1_t temp00m1; + ptrdiff_t bstride = -1; + l = vsetvl_e16m1(1); + temp00m1 = vmv_v_x_i16m1(0, l); + for (; (l = vsetvl_e8m4(vblkCnt)) > 0; vblkCnt -= l) { + vx = vle8_v_i8m4(px, l); + px += l; + vy = vlse8_v_i8m4(py, bstride, l); + py -= l; + sum += vmv_x_s_i16m1_i16(vredsum_vs_i16m8_i16m1(temp00m1, vwmul_vv_i16m8(vx, vy, l), temp00m1, l)); + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q7_t) (__SSAT(sum >> 7U, 8)); + + /* Increment the MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } +#else + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize2 >> 2U; + + while (blkCnt > 0U) + { + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* read x[0], x[1], x[2] samples */ + x0 = *px++; + x1 = *px++; + x2 = *px++; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + do + { + /* Read y[srcBLen - 1] sample */ + c0 = *py--; + /* Read y[srcBLen - 2] sample */ + c1 = *py--; + + /* Read x[3] sample */ + x3 = *px++; + + /* x[0] and x[1] are packed */ + in1 = (q15_t) x0; + in2 = (q15_t) x1; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* y[srcBLen - 1] and y[srcBLen - 2] are packed */ + in1 = (q15_t) c0; + in2 = (q15_t) c1; + + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */ + acc0 = __SMLAD(input1, input2, acc0); + + /* x[1] and x[2] are packed */ + in1 = (q15_t) x1; + in2 = (q15_t) x2; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */ + acc1 = __SMLAD(input1, input2, acc1); + + /* x[2] and x[3] are packed */ + in1 = (q15_t) x2; + in2 = (q15_t) x3; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */ + acc2 = __SMLAD(input1, input2, acc2); + + /* Read x[4] sample */ + x0 = *px++; + + /* x[3] and x[4] are packed */ + in1 = (q15_t) x3; + in2 = (q15_t) x0; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */ + acc3 = __SMLAD(input1, input2, acc3); + + /* Read y[srcBLen - 3] sample */ + c0 = *py--; + /* Read y[srcBLen - 4] sample */ + c1 = *py--; + + /* Read x[5] sample */ + x1 = *px++; + + /* x[2] and x[3] are packed */ + in1 = (q15_t) x2; + in2 = (q15_t) x3; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* y[srcBLen - 3] and y[srcBLen - 4] are packed */ + in1 = (q15_t) c0; + in2 = (q15_t) c1; + + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */ + acc0 = __SMLAD(input1, input2, acc0); + + /* x[3] and x[4] are packed */ + in1 = (q15_t) x3; + in2 = (q15_t) x0; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */ + acc1 = __SMLAD(input1, input2, acc1); + + /* x[4] and x[5] are packed */ + in1 = (q15_t) x0; + in2 = (q15_t) x1; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */ + acc2 = __SMLAD(input1, input2, acc2); + + /* Read x[6] sample */ + x2 = *px++; + + /* x[5] and x[6] are packed */ + in1 = (q15_t) x1; + in2 = (q15_t) x2; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */ + acc3 = __SMLAD(input1, input2, acc3); + + } while (--k); + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Read y[srcBLen - 5] sample */ + c0 = *py--; + /* Read x[7] sample */ + x3 = *px++; + + /* Perform the multiply-accumulates */ + /* acc0 += x[4] * y[srcBLen - 5] */ + acc0 += ((q15_t) x0 * c0); + /* acc1 += x[5] * y[srcBLen - 5] */ + acc1 += ((q15_t) x1 * c0); + /* acc2 += x[6] * y[srcBLen - 5] */ + acc2 += ((q15_t) x2 * c0); + /* acc3 += x[7] * y[srcBLen - 5] */ + acc3 += ((q15_t) x3 * c0); + + /* Reuse the present samples for the next MAC */ + x0 = x1; + x1 = x2; + x2 = x3; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q7_t) (__SSAT(acc0 >> 7U, 8)); + *pOut++ = (q7_t) (__SSAT(acc1 >> 7U, 8)); + *pOut++ = (q7_t) (__SSAT(acc2 >> 7U, 8)); + *pOut++ = (q7_t) (__SSAT(acc3 >> 7U, 8)); + + /* Increment the pointer pIn1 index, count by 4 */ + count += 4U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize2 % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize2; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = srcBLen >> 2U; + + while (k > 0U) + { + + /* Reading two inputs of SrcA buffer and packing */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* Reading two inputs of SrcB buffer and packing */ + in1 = (q15_t) *py--; + in2 = (q15_t) *py--; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* Perform the multiply-accumulate */ + sum = __SMLAD(input1, input2, sum); + + /* Reading two inputs of SrcA buffer and packing */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* Reading two inputs of SrcB buffer and packing */ + in1 = (q15_t) *py--; + in2 = (q15_t) *py--; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* Perform the multiply-accumulate */ + sum = __SMLAD(input1, input2, sum); + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = srcBLen % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = srcBLen; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += ((q15_t) *px++ * *py--); + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q7_t) (__SSAT(sum >> 7U, 8)); + + /* Increment the pointer pIn1 index, count by 1 */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += ((q15_t) *px++ * *py--); + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q7_t) (__SSAT(sum >> 7U, 8)); + + /* Increment the MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + } +#endif /*defined (RISCV_VECTOR)*/ + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1] + * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2] + * .... + * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2] + * sum += x[srcALen-1] * y[srcBLen-1] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The blockSize3 variable holds the number of MAC operations performed */ + + /* Working pointer of inputA */ + pSrc1 = pIn1 + (srcALen - (srcBLen - 1U)); + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + while (blockSize3 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (RISCV_MATH_LOOPUNROLL) && !defined (RISCV_VECTOR) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = blockSize3 >> 2U; + + while (k > 0U) + { + /* Reading two inputs, x[srcALen - srcBLen + 1] and x[srcALen - srcBLen + 2] of SrcA buffer and packing */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* Reading two inputs, y[srcBLen - 1] and y[srcBLen - 2] of SrcB buffer and packing */ + in1 = (q15_t) *py--; + in2 = (q15_t) *py--; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */ + /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */ + sum = __SMLAD(input1, input2, sum); + + /* Reading two inputs, x[srcALen - srcBLen + 3] and x[srcALen - srcBLen + 4] of SrcA buffer and packing */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* Reading two inputs, y[srcBLen - 3] and y[srcBLen - 4] of SrcB buffer and packing */ + in1 = (q15_t) *py--; + in2 = (q15_t) *py--; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */ + /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */ + sum = __SMLAD(input1, input2, sum); + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = blockSize3 % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = blockSize3; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ +#if defined (RISCV_VECTOR) + uint32_t vblkCnt = blockSize3; /* Loop counter */ + size_t l; + vint8m4_t vx, vy; + vint16m1_t temp00m1; + ptrdiff_t bstride = -1; + l = vsetvl_e16m1(1); + temp00m1 = vmv_v_x_i16m1(0, l); + for (; (l = vsetvl_e8m4(vblkCnt)) > 0; vblkCnt -= l) { + vx = vle8_v_i8m4(px, l); + px += l; + vy = vlse8_v_i8m4(py, bstride, l); + py -= l; + sum += vmv_x_s_i16m1_i16(vredsum_vs_i16m8_i16m1(temp00m1, vwmul_vv_i16m8(vx, vy, l), temp00m1, l)); + } +#else + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* sum += x[srcALen-1] * y[srcBLen-1] */ + sum += ((q15_t) *px++ * *py--); + + /* Decrement loop counter */ + k--; + } +#endif /*defined (RISCV_VECTOR)*/ + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q7_t) (__SSAT(sum >> 7U, 8)); + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pSrc2; + + /* Decrement loop counter */ + blockSize3--; + } + + +} + +/** + @} end of Conv group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_correlate_f16.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_correlate_f16.c new file mode 100644 index 00000000..09080874 --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_correlate_f16.c @@ -0,0 +1,752 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_correlate_f16.c + * Description: Correlation of floating-point sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions_f16.h" + +#if defined(RISCV_FLOAT16_SUPPORTED) +/** + @ingroup groupFilters + */ + +/** + @defgroup Corr Correlation + + Correlation is a mathematical operation that is similar to convolution. + As with convolution, correlation uses two signals to produce a third signal. + The underlying algorithms in correlation and convolution are identical except that one of the inputs is flipped in convolution. + Correlation is commonly used to measure the similarity between two signals. + It has applications in pattern recognition, cryptanalysis, and searching. + The NMSIS library provides correlation functions for Q7, Q15, Q31 and floating-point data types. + Fast versions of the Q15 and Q31 functions are also provided. + + @par Algorithm + Let a[n] and b[n] be sequences of length srcALen and srcBLen samples respectively. + The convolution of the two signals is denoted by + 
+      c[n] = a[n] * b[n]
+
+ In correlation, one of the signals is flipped in time + 
+       c[n] = a[n] * b[-n]
+
+ @par + and this is mathematically defined as + \image html CorrelateEquation.png + @par + The pSrcA points to the first input vector of length srcALen and pSrcB points to the second input vector of length srcBLen. + The result c[n] is of length 2 * max(srcALen, srcBLen) - 1 and is defined over the interval n=0, 1, 2, ..., (2 * max(srcALen, srcBLen) - 2). + The output result is written to pDst and the calling function must allocate 2 * max(srcALen, srcBLen) - 1 words for the result. + + @note + The pDst should be initialized to all zeros before being used. + + @par Fixed-Point Behavior + Correlation requires summing up a large number of intermediate products. + As such, the Q7, Q15, and Q31 functions run a risk of overflow and saturation. + Refer to the function specific documentation below for further details of the particular algorithm used. + + @par Fast Versions + Fast versions are supported for Q31 and Q15. Cycles for Fast versions are less compared to Q31 and Q15 of correlate and the design requires + the input signals should be scaled down to avoid intermediate overflows. + + @par Opt Versions + Opt versions are supported for Q15 and Q7. Design uses internal scratch buffer for getting good optimisation. + These versions are optimised in cycles and consumes more memory (Scratch memory) compared to Q15 and Q7 versions of correlate + */ + +/** + @addtogroup Corr + @{ + */ + +/** + @brief Correlation of floating-point sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. + @return none + */ + +void riscv_correlate_f16( + const float16_t * pSrcA, + uint32_t srcALen, + const float16_t * pSrcB, + uint32_t srcBLen, + float16_t * pDst) +{ + +#if defined(RISCV_MATH_DSP) + + const float16_t *pIn1; /* InputA pointer */ + const float16_t *pIn2; /* InputB pointer */ + float16_t *pOut = pDst; /* Output pointer */ + const float16_t *px; /* Intermediate inputA pointer */ + const float16_t *py; /* Intermediate inputB pointer */ + const float16_t *pSrc1; + _Float16 sum; + uint32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + uint32_t j, k, count, blkCnt; /* Loop counters */ + uint32_t outBlockSize; /* Loop counter */ + int32_t inc = 1; /* Destination address modifier */ + +#if defined (RISCV_MATH_LOOPUNROLL) + _Float16 acc0, acc1, acc2, acc3,c0; /* Accumulators */ + _Float16 x0, x1, x2, x3; /* temporary variables for holding input and coefficient values */ +#endif + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + /* But CORR(x, y) is reverse of CORR(y, x) */ + /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */ + /* and the destination pointer modifier, inc is set to -1 */ + /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */ + /* But to improve the performance, + * we assume zeroes in the output instead of zero padding either of the the inputs*/ + /* If srcALen > srcBLen, + * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */ + /* If srcALen < srcBLen, + * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + + /* Number of output samples is calculated */ + outBlockSize = (2U * srcALen) - 1U; + + /* When srcALen > srcBLen, zero padding has to be done to srcB + * to make their lengths equal. + * Instead, (outBlockSize - (srcALen + srcBLen - 1)) + * number of output samples are made zero */ + j = outBlockSize - (srcALen + (srcBLen - 1U)); + + /* Updating the pointer position to non zero value */ + pOut += j; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + + /* CORR(x, y) = Reverse order(CORR(y, x)) */ + /* Hence set the destination pointer to point to the last output sample */ + pOut = pDst + ((srcALen + srcBLen) - 2U); + + /* Destination address modifier is set to -1 */ + inc = -1; + } + + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* The algorithm is implemented in three stages. + The loop counters of each stage is initiated here. */ + blockSize1 = srcBLen - 1U; + blockSize2 = srcALen - (srcBLen - 1U); + blockSize3 = blockSize1; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[srcBlen - 1] + * sum = x[0] * y[srcBlen-2] + x[1] * y[srcBlen - 1] + * .... + * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = 1U; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc1 = pIn2 + (srcBLen - 1U); + py = pSrc1; + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* The first stage starts here */ + while (blockSize1 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.0f16; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* x[0] * y[srcBLen - 4] */ + sum += *px++ * *py++; + + /* x[1] * y[srcBLen - 3] */ + sum += *px++ * *py++; + + /* x[2] * y[srcBLen - 2] */ + sum += *px++ * *py++; + + /* x[3] * y[srcBLen - 1] */ + sum += *px++ * *py++; + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize k with number of samples */ + k = count; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* x[0] * y[srcBLen - 1] */ + sum += *px++ * *py++; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = sum; + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = pSrc1 - count; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1] + * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1] + * .... + * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + */ + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + py = pIn2; + + /* count is index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize2 >> 2U; + + while (blkCnt > 0U) + { + /* Set all accumulators to zero */ + acc0 = 0.0f16; + acc1 = 0.0f16; + acc2 = 0.0f16; + acc3 = 0.0f16; + + + /* read x[0], x[1], x[2] samples */ + x0 = *px++; + x1 = *px++; + x2 = *px++; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + do + { + /* Read y[0] sample */ + c0 = *(py++); + /* Read x[3] sample */ + x3 = *(px++); + + /* Perform the multiply-accumulate */ + /* acc0 += x[0] * y[0] */ + acc0 += x0 * c0; + /* acc1 += x[1] * y[0] */ + acc1 += x1 * c0; + /* acc2 += x[2] * y[0] */ + acc2 += x2 * c0; + /* acc3 += x[3] * y[0] */ + acc3 += x3 * c0; + + /* Read y[1] sample */ + c0 = *(py++); + /* Read x[4] sample */ + x0 = *(px++); + + /* Perform the multiply-accumulate */ + /* acc0 += x[1] * y[1] */ + acc0 += x1 * c0; + /* acc1 += x[2] * y[1] */ + acc1 += x2 * c0; + /* acc2 += x[3] * y[1] */ + acc2 += x3 * c0; + /* acc3 += x[4] * y[1] */ + acc3 += x0 * c0; + + /* Read y[2] sample */ + c0 = *(py++); + /* Read x[5] sample */ + x1 = *(px++); + + /* Perform the multiply-accumulate */ + /* acc0 += x[2] * y[2] */ + acc0 += x2 * c0; + /* acc1 += x[3] * y[2] */ + acc1 += x3 * c0; + /* acc2 += x[4] * y[2] */ + acc2 += x0 * c0; + /* acc3 += x[5] * y[2] */ + acc3 += x1 * c0; + + /* Read y[3] sample */ + c0 = *(py++); + /* Read x[6] sample */ + x2 = *(px++); + + /* Perform the multiply-accumulate */ + /* acc0 += x[3] * y[3] */ + acc0 += x3 * c0; + /* acc1 += x[4] * y[3] */ + acc1 += x0 * c0; + /* acc2 += x[5] * y[3] */ + acc2 += x1 * c0; + /* acc3 += x[6] * y[3] */ + acc3 += x2 * c0; + + } while (--k); + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Read y[4] sample */ + c0 = *(py++); + /* Read x[7] sample */ + x3 = *(px++); + + /* Perform the multiply-accumulate */ + /* acc0 += x[4] * y[4] */ + acc0 += x0 * c0; + /* acc1 += x[5] * y[4] */ + acc1 += x1 * c0; + /* acc2 += x[6] * y[4] */ + acc2 += x2 * c0; + /* acc3 += x[7] * y[4] */ + acc3 += x3 * c0; + + /* Reuse the present samples for the next MAC */ + x0 = x1; + x1 = x2; + x2 = x3; + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = acc0; + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + *pOut = acc1; + pOut += inc; + + *pOut = acc2; + pOut += inc; + + *pOut = acc3; + pOut += inc; + + /* Increment the pointer pIn1 index, count by 4 */ + count += 4U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize2 % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize2; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.0f16; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = srcBLen >> 2U; + + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += *px++ * *py++; + sum += *px++ * *py++; + sum += *px++ * *py++; + sum += *px++ * *py++; + + /* Decrement loop counter */ + k--; + } + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; +#else + + /* Initialize blkCnt with number of samples */ + k = srcBLen; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += *px++ * *py++; + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = sum; + + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Increment the pointer pIn1 index, count by 1 */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.0f16; + + /* Loop over srcBLen */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += *px++ * *py++; + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = sum; + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Increment the pointer pIn1 index, count by 1 */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + * .... + * sum += x[srcALen-2] * y[0] + x[srcALen-1] * y[1] + * sum += x[srcALen-1] * y[0] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = srcBLen - 1U; + + /* Working pointer of inputA */ + pSrc1 = pIn1 + (srcALen - (srcBLen - 1U)); + px = pSrc1; + + /* Working pointer of inputB */ + py = pIn2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + while (blockSize3 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.0f16; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* sum += x[srcALen - srcBLen + 4] * y[3] */ + sum += *px++ * *py++; + + /* sum += x[srcALen - srcBLen + 3] * y[2] */ + sum += *px++ * *py++; + + /* sum += x[srcALen - srcBLen + 2] * y[1] */ + sum += *px++ * *py++; + + /* sum += x[srcALen - srcBLen + 1] * y[0] */ + sum += *px++ * *py++; + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = count; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += *px++ * *py++; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = sum; + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pIn2; + + /* Decrement MAC count */ + count--; + + /* Decrement the loop counter */ + blockSize3--; + } + +#else +/* alternate version for CM0_FAMILY */ + + const float16_t *pIn1 = pSrcA; /* inputA pointer */ + const float16_t *pIn2 = pSrcB + (srcBLen - 1U); /* inputB pointer */ + _Float16 sum; /* Accumulator */ + uint32_t i = 0U, j; /* Loop counters */ + uint32_t inv = 0U; /* Reverse order flag */ + uint32_t tot = 0U; /* Length */ + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + /* But CORR(x, y) is reverse of CORR(y, x) */ + /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */ + /* and a varaible, inv is set to 1 */ + /* If lengths are not equal then zero pad has to be done to make the two + * inputs of same length. But to improve the performance, we assume zeroes + * in the output instead of zero padding either of the the inputs*/ + /* If srcALen > srcBLen, (srcALen - srcBLen) zeroes has to included in the + * starting of the output buffer */ + /* If srcALen < srcBLen, (srcALen - srcBLen) zeroes has to included in the + * ending of the output buffer */ + /* Once the zero padding is done the remaining of the output is calcualted + * using convolution but with the shorter signal time shifted. */ + + /* Calculate the length of the remaining sequence */ + tot = ((srcALen + srcBLen) - 2U); + + if (srcALen > srcBLen) + { + /* Calculating the number of zeros to be padded to the output */ + j = srcALen - srcBLen; + + /* Initialise the pointer after zero padding */ + pDst += j; + } + + else if (srcALen < srcBLen) + { + /* Initialization to inputB pointer */ + pIn1 = pSrcB; + + /* Initialization to the end of inputA pointer */ + pIn2 = pSrcA + (srcALen - 1U); + + /* Initialisation of the pointer after zero padding */ + pDst = pDst + tot; + + /* Swapping the lengths */ + j = srcALen; + srcALen = srcBLen; + srcBLen = j; + + /* Setting the reverse flag */ + inv = 1; + + } + + /* Loop to calculate convolution for output length number of times */ + for (i = 0U; i <= tot; i++) + { + /* Initialize sum with zero to carry out MAC operations */ + sum = 0.0f16; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0U; j <= i; j++) + { + /* Check the array limitations */ + if ((((i - j) < srcBLen) && (j < srcALen))) + { + /* z[i] += x[i-j] * y[j] */ + sum += pIn1[j] * pIn2[-((int32_t) i - (int32_t) j)]; + } + } + + /* Store the output in the destination buffer */ + if (inv == 1) + *pDst-- = sum; + else + *pDst++ = sum; + } + +#endif /* #if !defined(RISCV_MATH_CM0_FAMILY) */ + +} + +/** + @} end of Corr group + */ + +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_correlate_f32.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_correlate_f32.c new file mode 100644 index 00000000..6473d433 --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_correlate_f32.c @@ -0,0 +1,813 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_correlate_f32.c + * Description: Correlation of floating-point sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @defgroup Corr Correlation + + Correlation is a mathematical operation that is similar to convolution. + As with convolution, correlation uses two signals to produce a third signal. + The underlying algorithms in correlation and convolution are identical except that one of the inputs is flipped in convolution. + Correlation is commonly used to measure the similarity between two signals. + It has applications in pattern recognition, cryptanalysis, and searching. + The NMSIS library provides correlation functions for Q7, Q15, Q31 and floating-point data types. + Fast versions of the Q15 and Q31 functions are also provided. + + @par Algorithm + Let a[n] and b[n] be sequences of length srcALen and srcBLen samples respectively. + The convolution of the two signals is denoted by + 
+      c[n] = a[n] * b[n]
+
+ In correlation, one of the signals is flipped in time + 
+       c[n] = a[n] * b[-n]
+
+ @par + and this is mathematically defined as + \image html CorrelateEquation.png + @par + The pSrcA points to the first input vector of length srcALen and pSrcB points to the second input vector of length srcBLen. + The result c[n] is of length 2 * max(srcALen, srcBLen) - 1 and is defined over the interval n=0, 1, 2, ..., (2 * max(srcALen, srcBLen) - 2). + The output result is written to pDst and the calling function must allocate 2 * max(srcALen, srcBLen) - 1 words for the result. + + @note + The pDst should be initialized to all zeros before being used. + + @par Fixed-Point Behavior + Correlation requires summing up a large number of intermediate products. + As such, the Q7, Q15, and Q31 functions run a risk of overflow and saturation. + Refer to the function specific documentation below for further details of the particular algorithm used. + + @par Fast Versions + Fast versions are supported for Q31 and Q15. Cycles for Fast versions are less compared to Q31 and Q15 of correlate and the design requires + the input signals should be scaled down to avoid intermediate overflows. + + @par Opt Versions + Opt versions are supported for Q15 and Q7. Design uses internal scratch buffer for getting good optimisation. + These versions are optimised in cycles and consumes more memory (Scratch memory) compared to Q15 and Q7 versions of correlate + */ + +/** + @addtogroup Corr + @{ + */ + +/** + @brief Correlation of floating-point sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. + @return none + */ + +void riscv_correlate_f32( + const float32_t * pSrcA, + uint32_t srcALen, + const float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst) +{ + +#if defined(RISCV_MATH_DSP) || defined (RISCV_VECTOR) + + const float32_t *pIn1; /* InputA pointer */ + const float32_t *pIn2; /* InputB pointer */ + float32_t *pOut = pDst; /* Output pointer */ + const float32_t *px; /* Intermediate inputA pointer */ + const float32_t *py; /* Intermediate inputB pointer */ + const float32_t *pSrc1; + float32_t sum; + uint32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + uint32_t j, k, count, blkCnt; /* Loop counters */ + uint32_t outBlockSize; /* Loop counter */ + int32_t inc = 1; /* Destination address modifier */ + +#if defined (RISCV_MATH_LOOPUNROLL) + float32_t acc0, acc1, acc2, acc3,c0; /* Accumulators */ + float32_t x0, x1, x2, x3; /* temporary variables for holding input and coefficient values */ +#endif + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + /* But CORR(x, y) is reverse of CORR(y, x) */ + /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */ + /* and the destination pointer modifier, inc is set to -1 */ + /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */ + /* But to improve the performance, + * we assume zeroes in the output instead of zero padding either of the the inputs*/ + /* If srcALen > srcBLen, + * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */ + /* If srcALen < srcBLen, + * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + + /* Number of output samples is calculated */ + outBlockSize = (2U * srcALen) - 1U; + + /* When srcALen > srcBLen, zero padding has to be done to srcB + * to make their lengths equal. + * Instead, (outBlockSize - (srcALen + srcBLen - 1)) + * number of output samples are made zero */ + j = outBlockSize - (srcALen + (srcBLen - 1U)); + + /* Updating the pointer position to non zero value */ + pOut += j; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + + /* CORR(x, y) = Reverse order(CORR(y, x)) */ + /* Hence set the destination pointer to point to the last output sample */ + pOut = pDst + ((srcALen + srcBLen) - 2U); + + /* Destination address modifier is set to -1 */ + inc = -1; + } + + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* The algorithm is implemented in three stages. + The loop counters of each stage is initiated here. */ + blockSize1 = srcBLen - 1U; + blockSize2 = srcALen - (srcBLen - 1U); + blockSize3 = blockSize1; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[srcBlen - 1] + * sum = x[0] * y[srcBlen-2] + x[1] * y[srcBlen - 1] + * .... + * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = 1U; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc1 = pIn2 + (srcBLen - 1U); + py = pSrc1; + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* The first stage starts here */ + while (blockSize1 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.0f; +#if defined (RISCV_VECTOR) + uint32_t vblkCnt = count; /* Loop counter */ + size_t l; + vfloat32m8_t vx, vy; + vfloat32m1_t temp00m1; + l = vsetvl_e32m1(1); + temp00m1 = vfmv_v_f_f32m1(0, l); + for (; (l = vsetvl_e32m8(vblkCnt)) > 0; vblkCnt -= l) { + vx = vle32_v_f32m8(px, l); + px += l; + vy = vle32_v_f32m8(py, l); + py += l; + sum += vfmv_f_s_f32m1_f32(vfredsum_vs_f32m8_f32m1(temp00m1, vfmul_vv_f32m8(vx, vy, l), temp00m1, l)); + } +#else +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* x[0] * y[srcBLen - 4] */ + sum += *px++ * *py++; + + /* x[1] * y[srcBLen - 3] */ + sum += *px++ * *py++; + + /* x[2] * y[srcBLen - 2] */ + sum += *px++ * *py++; + + /* x[3] * y[srcBLen - 1] */ + sum += *px++ * *py++; + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize k with number of samples */ + k = count; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* x[0] * y[srcBLen - 1] */ + sum += *px++ * *py++; + + /* Decrement loop counter */ + k--; + } +#endif /*defined (RISCV_VECTOR)*/ + /* Store the result in the accumulator in the destination buffer. */ + *pOut = sum; + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = pSrc1 - count; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1] + * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1] + * .... + * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + */ + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + py = pIn2; + + /* count is index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ +#if defined (RISCV_VECTOR) + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.0f; + + uint32_t vblkCnt = srcBLen; /* Loop counter */ + size_t l; + vfloat32m8_t vx, vy; + vfloat32m1_t temp00m1; + l = vsetvl_e32m1(vblkCnt); + temp00m1 = vfmv_v_f_f32m1(0, l); + for (; (l = vsetvl_e32m8(vblkCnt)) > 0; vblkCnt -= l) { + vx = vle32_v_f32m8(px, l); + px += l; + vy = vle32_v_f32m8(py, l); + py += l; + sum += vfmv_f_s_f32m1_f32(vfredsum_vs_f32m8_f32m1(temp00m1, vfmul_vv_f32m8(vx, vy, l), temp00m1, l)); + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = sum; + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Increment the pointer pIn1 index, count by 1 */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement the loop counter */ + blkCnt--; + } + +#else + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize2 >> 2U; + + + while (blkCnt > 0U) + { + /* Set all accumulators to zero */ + acc0 = 0.0f; + acc1 = 0.0f; + acc2 = 0.0f; + acc3 = 0.0f; + + /* read x[0], x[1], x[2] samples */ + x0 = *px++; + x1 = *px++; + x2 = *px++; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + do + { + /* Read y[0] sample */ + c0 = *(py++); + /* Read x[3] sample */ + x3 = *(px++); + + /* Perform the multiply-accumulate */ + /* acc0 += x[0] * y[0] */ + acc0 += x0 * c0; + /* acc1 += x[1] * y[0] */ + acc1 += x1 * c0; + /* acc2 += x[2] * y[0] */ + acc2 += x2 * c0; + /* acc3 += x[3] * y[0] */ + acc3 += x3 * c0; + + /* Read y[1] sample */ + c0 = *(py++); + /* Read x[4] sample */ + x0 = *(px++); + + /* Perform the multiply-accumulate */ + /* acc0 += x[1] * y[1] */ + acc0 += x1 * c0; + /* acc1 += x[2] * y[1] */ + acc1 += x2 * c0; + /* acc2 += x[3] * y[1] */ + acc2 += x3 * c0; + /* acc3 += x[4] * y[1] */ + acc3 += x0 * c0; + + /* Read y[2] sample */ + c0 = *(py++); + /* Read x[5] sample */ + x1 = *(px++); + + /* Perform the multiply-accumulate */ + /* acc0 += x[2] * y[2] */ + acc0 += x2 * c0; + /* acc1 += x[3] * y[2] */ + acc1 += x3 * c0; + /* acc2 += x[4] * y[2] */ + acc2 += x0 * c0; + /* acc3 += x[5] * y[2] */ + acc3 += x1 * c0; + + /* Read y[3] sample */ + c0 = *(py++); + /* Read x[6] sample */ + x2 = *(px++); + + /* Perform the multiply-accumulate */ + /* acc0 += x[3] * y[3] */ + acc0 += x3 * c0; + /* acc1 += x[4] * y[3] */ + acc1 += x0 * c0; + /* acc2 += x[5] * y[3] */ + acc2 += x1 * c0; + /* acc3 += x[6] * y[3] */ + acc3 += x2 * c0; + + } while (--k); + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Read y[4] sample */ + c0 = *(py++); + /* Read x[7] sample */ + x3 = *(px++); + + /* Perform the multiply-accumulate */ + /* acc0 += x[4] * y[4] */ + acc0 += x0 * c0; + /* acc1 += x[5] * y[4] */ + acc1 += x1 * c0; + /* acc2 += x[6] * y[4] */ + acc2 += x2 * c0; + /* acc3 += x[7] * y[4] */ + acc3 += x3 * c0; + + /* Reuse the present samples for the next MAC */ + x0 = x1; + x1 = x2; + x2 = x3; + + /* Decrement the loop counter */ + k--; + } + + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = acc0; + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + *pOut = acc1; + pOut += inc; + + *pOut = acc2; + pOut += inc; + + *pOut = acc3; + pOut += inc; + + /* Increment the pointer pIn1 index, count by 4 */ + count += 4U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize2 % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize2; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.0f; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += *px++ * *py++; + sum += *px++ * *py++; + sum += *px++ * *py++; + sum += *px++ * *py++; + + /* Decrement loop counter */ + k--; + } + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; +#else + + /* Initialize blkCnt with number of samples */ + k = srcBLen; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += *px++ * *py++; + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = sum; + + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Increment the pointer pIn1 index, count by 1 */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.0f; + + /* Loop over srcBLen */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += *px++ * *py++; + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = sum; + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Increment the pointer pIn1 index, count by 1 */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement the loop counter */ + blkCnt--; + } + } +#endif /*defined (RISCV_VECTOR)*/ + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + * .... + * sum += x[srcALen-2] * y[0] + x[srcALen-1] * y[1] + * sum += x[srcALen-1] * y[0] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = srcBLen - 1U; + + /* Working pointer of inputA */ + pSrc1 = pIn1 + (srcALen - (srcBLen - 1U)); + px = pSrc1; + + /* Working pointer of inputB */ + py = pIn2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + while (blockSize3 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.0f; + +#if defined (RISCV_MATH_LOOPUNROLL) && !defined (RISCV_VECTOR) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* sum += x[srcALen - srcBLen + 4] * y[3] */ + sum += *px++ * *py++; + + /* sum += x[srcALen - srcBLen + 3] * y[2] */ + sum += *px++ * *py++; + + /* sum += x[srcALen - srcBLen + 2] * y[1] */ + sum += *px++ * *py++; + + /* sum += x[srcALen - srcBLen + 1] * y[0] */ + sum += *px++ * *py++; + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = count; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ +#if defined (RISCV_VECTOR) + uint32_t vblkCnt = count; /* Loop counter */ + size_t l; + vfloat32m8_t vx, vy; + vfloat32m1_t temp00m1; + l = vsetvl_e32m1(1); + temp00m1 = vfmv_v_f_f32m1(0, l); + for (; (l = vsetvl_e32m8(vblkCnt)) > 0; vblkCnt -= l) { + vx = vle32_v_f32m8(px, l); + px += l; + vy = vle32_v_f32m8(py, l); + py += l; + sum += vfmv_f_s_f32m1_f32(vfredsum_vs_f32m8_f32m1(temp00m1, vfmul_vv_f32m8(vx, vy, l), temp00m1, l)); + } +#else + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += *px++ * *py++; + + /* Decrement loop counter */ + k--; + } +#endif /*defined (RISCV_VECTOR)*/ + /* Store the result in the accumulator in the destination buffer. */ + *pOut = sum; + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pIn2; + + /* Decrement MAC count */ + count--; + + /* Decrement the loop counter */ + blockSize3--; + } + +#else +/* alternate version for CM0_FAMILY */ + + const float32_t *pIn1 = pSrcA; /* inputA pointer */ + const float32_t *pIn2 = pSrcB + (srcBLen - 1U); /* inputB pointer */ + float32_t sum; /* Accumulator */ + int32_t i = 0U, j; /* Loop counters */ + uint32_t inv = 0U; /* Reverse order flag */ + uint32_t tot = 0U; /* Length */ + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + /* But CORR(x, y) is reverse of CORR(y, x) */ + /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */ + /* and a varaible, inv is set to 1 */ + /* If lengths are not equal then zero pad has to be done to make the two + * inputs of same length. But to improve the performance, we assume zeroes + * in the output instead of zero padding either of the the inputs*/ + /* If srcALen > srcBLen, (srcALen - srcBLen) zeroes has to included in the + * starting of the output buffer */ + /* If srcALen < srcBLen, (srcALen - srcBLen) zeroes has to included in the + * ending of the output buffer */ + /* Once the zero padding is done the remaining of the output is calcualted + * using convolution but with the shorter signal time shifted. */ + + /* Calculate the length of the remaining sequence */ + tot = ((srcALen + srcBLen) - 2U); + + if (srcALen > srcBLen) + { + /* Calculating the number of zeros to be padded to the output */ + j = srcALen - srcBLen; + + /* Initialise the pointer after zero padding */ + pDst += j; + } + + else if (srcALen < srcBLen) + { + /* Initialization to inputB pointer */ + pIn1 = pSrcB; + + /* Initialization to the end of inputA pointer */ + pIn2 = pSrcA + (srcALen - 1U); + + /* Initialisation of the pointer after zero padding */ + pDst = pDst + tot; + + /* Swapping the lengths */ + j = srcALen; + srcALen = srcBLen; + srcBLen = j; + + /* Setting the reverse flag */ + inv = 1; + + } + + /* Loop to calculate convolution for output length number of times */ + for (i = 0U; i <= tot; i++) + { + /* Initialize sum with zero to carry out MAC operations */ + sum = 0.0f; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0U; j <= i; j++) + { + /* Check the array limitations */ + if ((((i - j) < srcBLen) && (j < srcALen))) + { + /* z[i] += x[i-j] * y[j] */ + sum += pIn1[j] * pIn2[-((int32_t) i - (int32_t) j)]; + } + } + + /* Store the output in the destination buffer */ + if (inv == 1) + *pDst-- = sum; + else + *pDst++ = sum; + } + +#endif /* #if !defined(RISCV_MATH_CM0_FAMILY) */ + +} + +/** + @} end of Corr group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_correlate_fast_opt_q15.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_correlate_fast_opt_q15.c new file mode 100644 index 00000000..7fef61fb --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_correlate_fast_opt_q15.c @@ -0,0 +1,337 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_correlate_fast_opt_q15.c + * Description: Fast Q15 Correlation + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Corr + @{ + */ + +/** + @brief Correlation of Q15 sequences (fast version). + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence. + @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. + @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + @return none + + @par Scaling and Overflow Behavior + This fast version uses a 32-bit accumulator with 2.30 format. + The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit. + There is no saturation on intermediate additions. + Thus, if the accumulator overflows it wraps around and distorts the result. + The input signals should be scaled down to avoid intermediate overflows. + Scale down one of the inputs by 1/min(srcALen, srcBLen) to avoid overflow since a + maximum of min(srcALen, srcBLen) number of additions is carried internally. + The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result. + + @remark + Refer to \ref riscv_correlate_q15() for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion. + */ + +void riscv_correlate_fast_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch) +{ +#if defined (RISCV_VECTOR) + riscv_correlate_opt_q15(pSrcA, srcALen, pSrcB, srcBLen, pDst, pScratch); +#else + const q15_t *pIn1; /* InputA pointer */ + const q15_t *pIn2; /* InputB pointer */ + q31_t acc0; /* Accumulators */ + q15_t *pOut = pDst; /* Output pointer */ + q15_t *pScr1 = pScratch; /* Temporary pointer for scratch */ + const q15_t *py; /* Intermediate inputB pointer */ + uint32_t j, blkCnt, outBlockSize; /* Loop counter */ + int32_t inc = 1; /* Destination address modifier */ + uint32_t tapCnt; /* Loop count */ + +#if defined (RISCV_MATH_LOOPUNROLL) + q31_t acc1, acc2, acc3; /* Accumulators */ + q31_t x1, x2, x3; /* Temporary variables for holding input and coefficient values */ + q31_t y1, y2; /* State variables */ +#endif + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + /* But CORR(x, y) is reverse of CORR(y, x) */ + /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */ + /* and the destination pointer modifier, inc is set to -1 */ + /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */ + /* But to improve the performance, + * we include zeroes in the output instead of zero padding either of the the inputs*/ + /* If srcALen > srcBLen, + * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */ + /* If srcALen < srcBLen, + * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + + /* Number of output samples is calculated */ + outBlockSize = (2U * srcALen) - 1U; + + /* When srcALen > srcBLen, zero padding is done to srcB + * to make their lengths equal. + * Instead, (outBlockSize - (srcALen + srcBLen - 1)) + * number of output samples are made zero */ + j = outBlockSize - (srcALen + (srcBLen - 1U)); + + /* Updating the pointer position to non zero value */ + pOut += j; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + + /* CORR(x, y) = Reverse order(CORR(y, x)) */ + /* Hence set the destination pointer to point to the last output sample */ + pOut = pDst + ((srcALen + srcBLen) - 2U); + + /* Destination address modifier is set to -1 */ + inc = -1; + } + + pScr1 = pScratch; + + /* Fill (srcBLen - 1U) zeros in scratch buffer */ + riscv_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update temporary scratch pointer */ + pScr1 += (srcBLen - 1U); + + + /* Copy (srcALen) samples in scratch buffer */ + riscv_copy_q15(pIn1, pScr1, srcALen); + + /* Update pointers */ + pScr1 += srcALen; + + + /* Fill (srcBLen - 1U) zeros at end of scratch buffer */ + riscv_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update pointer */ + pScr1 += (srcBLen - 1U); + + /* Temporary pointer for scratch2 */ + py = pIn2; + + + /* Actual correlation process starts here */ + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (srcALen + srcBLen - 1U) >> 2; + + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch; + + /* Clear Accumlators */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Read two samples from scratch buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* Read next two samples from scratch buffer */ + x2 = read_q15x2_ia (&pScr1); + + tapCnt = (srcBLen) >> 2U; + + while (tapCnt > 0U) + { + /* Read four samples from smaller buffer */ + y1 = read_q15x2_ia ((q15_t **) &pIn2); + y2 = read_q15x2_ia ((q15_t **) &pIn2); + + /* multiply and accumulate */ + acc0 = __SMLAD(x1, y1, acc0); + acc2 = __SMLAD(x2, y1, acc2); + + /* pack input data */ + x3 = __PKHBT(x2, x1, 0); + + /* multiply and accumulate */ + acc1 = __SMLADX(x3, y1, acc1); + + /* Read next two samples from scratch buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* multiply and accumulate */ + acc0 = __SMLAD(x2, y2, acc0); + acc2 = __SMLAD(x1, y2, acc2); + + /* pack input data */ + x3 = __PKHBT(x1, x2, 0); + + acc3 = __SMLADX(x3, y1, acc3); + acc1 = __SMLADX(x3, y2, acc1); + + x2 = read_q15x2_ia (&pScr1); + + x3 = __PKHBT(x2, x1, 0); + + acc3 = __SMLADX(x3, y2, acc3); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Update scratch pointer for remaining samples of smaller length sequence */ + pScr1 -= 4U; + + /* apply same above for remaining samples of smaller length sequence */ + tapCnt = (srcBLen) & 3U; + + while (tapCnt > 0U) + { + /* accumulate the results */ + acc0 += (*pScr1++ * *pIn2); + acc1 += (*pScr1++ * *pIn2); + acc2 += (*pScr1++ * *pIn2); + acc3 += (*pScr1++ * *pIn2++); + + pScr1 -= 3U; + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* Store the results in the accumulators in the destination buffer. */ + *pOut = (__SSAT(acc0 >> 15U, 16)); + pOut += inc; + *pOut = (__SSAT(acc1 >> 15U, 16)); + pOut += inc; + *pOut = (__SSAT(acc2 >> 15U, 16)); + pOut += inc; + *pOut = (__SSAT(acc3 >> 15U, 16)); + pOut += inc; + + /* Initialization of inputB pointer */ + pIn2 = py; + + pScratch += 4U; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (srcALen + srcBLen - 1U) & 0x3; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = (srcALen + srcBLen - 1U); + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + /* Calculate correlation for remaining samples of Bigger length sequence */ + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch; + + /* Clear Accumlators */ + acc0 = 0; + + tapCnt = (srcBLen) >> 1U; + + while (tapCnt > 0U) + { + + /* Read next two samples from scratch buffer */ + acc0 += (*pScr1++ * *pIn2++); + acc0 += (*pScr1++ * *pIn2++); + + /* Decrement loop counter */ + tapCnt--; + } + + tapCnt = (srcBLen) & 1U; + + /* apply same above for remaining samples of smaller length sequence */ + while (tapCnt > 0U) + { + + /* accumulate the results */ + acc0 += (*pScr1++ * *pIn2++); + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* The result is in 2.30 format. Convert to 1.15 with saturation. + ** Then store the output in the destination buffer. */ + *pOut = (q15_t) (__SSAT((acc0 >> 15), 16)); + pOut += inc; + + /* Initialization of inputB pointer */ + pIn2 = py; + + pScratch += 1U; + } +#endif /*defined (RISCV_VECTOR)*/ +} + +/** + @} end of Corr group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_correlate_fast_q15.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_correlate_fast_q15.c new file mode 100644 index 00000000..dd9a5163 --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_correlate_fast_q15.c @@ -0,0 +1,610 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_correlate_fast_q15.c + * Description: Fast Q15 Correlation + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Corr + @{ + */ + +/** + @brief Correlation of Q15 sequences (fast version). + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. + @return none + + @par Scaling and Overflow Behavior + This fast version uses a 32-bit accumulator with 2.30 format. + The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit. + There is no saturation on intermediate additions. + Thus, if the accumulator overflows it wraps around and distorts the result. + The input signals should be scaled down to avoid intermediate overflows. + Scale down one of the inputs by 1/min(srcALen, srcBLen) to avoid overflow since a + maximum of min(srcALen, srcBLen) number of additions is carried internally. + The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result. + + @remark + Refer to \ref riscv_correlate_q15() for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion. + */ + +void riscv_correlate_fast_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst) +{ +#if defined (RISCV_VECTOR) + riscv_correlate_q15(pSrcA, srcALen, pSrcB, srcBLen, pDst); +#else + const q15_t *pIn1; /* InputA pointer */ + const q15_t *pIn2; /* InputB pointer */ + q15_t *pOut = pDst; /* Output pointer */ + q31_t sum, acc0, acc1, acc2, acc3; /* Accumulators */ + const q15_t *px; /* Intermediate inputA pointer */ + const q15_t *py; /* Intermediate inputB pointer */ + const q15_t *pSrc1; /* Intermediate pointers */ + q31_t x0, x1, x2, x3, c0; /* Temporary variables for holding input and coefficient values */ + uint32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + uint32_t j, k, count, blkCnt; /* Loop counters */ + uint32_t outBlockSize; + int32_t inc = 1; /* Destination address modifier */ + + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + /* But CORR(x, y) is reverse of CORR(y, x) */ + /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */ + /* and the destination pointer modifier, inc is set to -1 */ + /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */ + /* But to improve the performance, + * we include zeroes in the output instead of zero padding either of the the inputs*/ + /* If srcALen > srcBLen, + * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */ + /* If srcALen < srcBLen, + * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + + /* Number of output samples is calculated */ + outBlockSize = (2U * srcALen) - 1U; + + /* When srcALen > srcBLen, zero padding is done to srcB + * to make their lengths equal. + * Instead, (outBlockSize - (srcALen + srcBLen - 1)) + * number of output samples are made zero */ + j = outBlockSize - (srcALen + (srcBLen - 1U)); + + /* Updating the pointer position to non zero value */ + pOut += j; + + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + + /* CORR(x, y) = Reverse order(CORR(y, x)) */ + /* Hence set the destination pointer to point to the last output sample */ + pOut = pDst + ((srcALen + srcBLen) - 2U); + + /* Destination address modifier is set to -1 */ + inc = -1; + + } + + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* The algorithm is implemented in three stages. + The loop counters of each stage is initiated here. */ + blockSize1 = srcBLen - 1U; + blockSize2 = srcALen - (srcBLen - 1U); + blockSize3 = blockSize1; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[srcBlen - 1] + * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1] + * .... + * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = 1U; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc1 = pIn2 + (srcBLen - 1U); + py = pSrc1; + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* The first loop starts here */ + while (blockSize1 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = count >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* x[0] * y[srcBLen - 4] , x[1] * y[srcBLen - 3] */ + sum = __SMLAD(read_q15x2_ia ((q15_t **) &px), read_q15x2_ia ((q15_t **) &py), sum); + /* x[3] * y[srcBLen - 1] , x[2] * y[srcBLen - 2] */ + sum = __SMLAD(read_q15x2_ia ((q15_t **) &px), read_q15x2_ia ((q15_t **) &py), sum); + + /* Decrement loop counter */ + k--; + } + + /* If the count is not a multiple of 4, compute any remaining MACs here. + No loop unrolling is used. */ + k = count % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + /* x[0] * y[srcBLen - 1] */ + sum = __SMLAD(*px++, *py++, sum); + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q15_t) (sum >> 15); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = pSrc1 - count; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1] + * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1] + * .... + * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + */ + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + py = pIn2; + + /* count is the index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* -------------------- + * Stage2 process + * -------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { + /* Loop unroll over blockSize2, by 4 */ + blkCnt = blockSize2 >> 2U; + + while (blkCnt > 0U) + { + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* read x[0], x[1] samples */ + x0 = read_q15x2 ((q15_t *) px); + /* read x[1], x[2] samples */ + x1 = read_q15x2 ((q15_t *) px + 1); + px += 2U; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + do + { + /* Read the first two inputB samples using SIMD: + * y[0] and y[1] */ + c0 = read_q15x2_ia ((q15_t **) &py); + + /* acc0 += x[0] * y[0] + x[1] * y[1] */ + acc0 = __SMLAD(x0, c0, acc0); + + /* acc1 += x[1] * y[0] + x[2] * y[1] */ + acc1 = __SMLAD(x1, c0, acc1); + + /* Read x[2], x[3] */ + x2 = read_q15x2 ((q15_t *) px); + + /* Read x[3], x[4] */ + x3 = read_q15x2 ((q15_t *) px + 1); + + /* acc2 += x[2] * y[0] + x[3] * y[1] */ + acc2 = __SMLAD(x2, c0, acc2); + + /* acc3 += x[3] * y[0] + x[4] * y[1] */ + acc3 = __SMLAD(x3, c0, acc3); + + /* Read y[2] and y[3] */ + c0 = read_q15x2_ia ((q15_t **) &py); + + /* acc0 += x[2] * y[2] + x[3] * y[3] */ + acc0 = __SMLAD(x2, c0, acc0); + + /* acc1 += x[3] * y[2] + x[4] * y[3] */ + acc1 = __SMLAD(x3, c0, acc1); + + /* Read x[4], x[5] */ + x0 = read_q15x2 ((q15_t *) px + 2); + + /* Read x[5], x[6] */ + x1 = read_q15x2 ((q15_t *) px + 3); + px += 4U; + + /* acc2 += x[4] * y[2] + x[5] * y[3] */ + acc2 = __SMLAD(x0, c0, acc2); + + /* acc3 += x[5] * y[2] + x[6] * y[3] */ + acc3 = __SMLAD(x1, c0, acc3); + + } while (--k); + + /* For the next MAC operations, SIMD is not used + * So, the 16 bit pointer if inputB, py is updated */ + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + if (k == 1U) + { + /* Read y[4] */ + c0 = *py; + + c0 = c0 & 0x0000FFFF; + + /* Read x[7] */ + x3 = read_q15x2 ((q15_t *) px); + px++; + + /* Perform the multiply-accumulates */ + acc0 = __SMLAD (x0, c0, acc0); + acc1 = __SMLAD (x1, c0, acc1); + acc2 = __SMLADX(x1, c0, acc2); + acc3 = __SMLADX(x3, c0, acc3); + } + + if (k == 2U) + { + /* Read y[4], y[5] */ + c0 = read_q15x2 ((q15_t *) py); + + /* Read x[7], x[8] */ + x3 = read_q15x2 ((q15_t *) px); + + /* Read x[9] */ + x2 = read_q15x2 ((q15_t *) px + 1); + px += 2U; + + /* Perform the multiply-accumulates */ + acc0 = __SMLAD(x0, c0, acc0); + acc1 = __SMLAD(x1, c0, acc1); + acc2 = __SMLAD(x3, c0, acc2); + acc3 = __SMLAD(x2, c0, acc3); + } + + if (k == 3U) + { + /* Read y[4], y[5] */ + c0 = read_q15x2_ia ((q15_t **) &py); + + /* Read x[7], x[8] */ + x3 = read_q15x2 ((q15_t *) px); + + /* Read x[9] */ + x2 = read_q15x2 ((q15_t *) px + 1); + + /* Perform the multiply-accumulates */ + acc0 = __SMLAD(x0, c0, acc0); + acc1 = __SMLAD(x1, c0, acc1); + acc2 = __SMLAD(x3, c0, acc2); + acc3 = __SMLAD(x2, c0, acc3); + + c0 = (*py); + /* Read y[6] */ + c0 = c0 & 0x0000FFFF; + + /* Read x[10] */ + x3 = read_q15x2 ((q15_t *) px + 2); + px += 3U; + + /* Perform the multiply-accumulates */ + acc0 = __SMLADX(x1, c0, acc0); + acc1 = __SMLAD (x2, c0, acc1); + acc2 = __SMLADX(x2, c0, acc2); + acc3 = __SMLADX(x3, c0, acc3); + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q15_t) (acc0 >> 15); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + *pOut = (q15_t) (acc1 >> 15); + pOut += inc; + + *pOut = (q15_t) (acc2 >> 15); + pOut += inc; + + *pOut = (q15_t) (acc3 >> 15); + pOut += inc; + + /* Increment the pointer pIn1 index, count by 4 */ + count += 4U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize2 % 0x4U; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum += ((q31_t) *px++ * *py++); + sum += ((q31_t) *px++ * *py++); + sum += ((q31_t) *px++ * *py++); + sum += ((q31_t) *px++ * *py++); + + /* Decrement loop counter */ + k--; + } + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum += ((q31_t) * px++ * *py++); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q15_t) (sum >> 15); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Increment the pointer pIn1 index, count by 1 */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += ((q31_t) *px++ * *py++); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q15_t) (sum >> 15); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Increment MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement loop counter */ + blkCnt--; + } + } + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + * .... + * sum += x[srcALen-2] * y[0] + x[srcALen-1] * y[1] + * sum += x[srcALen-1] * y[0] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = srcBLen - 1U; + + /* Working pointer of inputA */ + pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U); + px = pSrc1; + + /* Working pointer of inputB */ + py = pIn2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + while (blockSize3 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = count >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulates */ + /* sum += x[srcALen - srcBLen + 4] * y[3] , sum += x[srcALen - srcBLen + 3] * y[2] */ + sum = __SMLAD(read_q15x2_ia ((q15_t **) &px), read_q15x2_ia ((q15_t **) &py), sum); + /* sum += x[srcALen - srcBLen + 2] * y[1] , sum += x[srcALen - srcBLen + 1] * y[0] */ + sum = __SMLAD(read_q15x2_ia ((q15_t **) &px), read_q15x2_ia ((q15_t **) &py), sum); + + /* Decrement loop counter */ + k--; + } + + /* If the count is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = count % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum = __SMLAD(*px++, *py++, sum); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q15_t) (sum >> 15); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pIn2; + + /* Decrement the MAC count */ + count--; + + /* Decrement the loop counter */ + blockSize3--; + } +#endif /*defined (RISCV_VECTOR)*/ +} + +/** + @} end of Corr group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_correlate_fast_q31.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_correlate_fast_q31.c new file mode 100644 index 00000000..3b542d82 --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_correlate_fast_q31.c @@ -0,0 +1,605 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_correlate_fast_q31.c + * Description: Fast Q31 Correlation + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Corr + @{ + */ + +/** + @brief Correlation of Q31 sequences (fast version). + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. + @return none + + @par Scaling and Overflow Behavior + This function is optimized for speed at the expense of fixed-point precision and overflow protection. + The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format. + These intermediate results are accumulated in a 32-bit register in 2.30 format. + Finally, the accumulator is saturated and converted to a 1.31 result. + @par + The fast version has the same overflow behavior as the standard version but provides less precision since it discards the low 32 bits of each multiplication result. + In order to avoid overflows completely the input signals must be scaled down. + The input signals should be scaled down to avoid intermediate overflows. + Scale down one of the inputs by 1/min(srcALen, srcBLen)to avoid overflows since a + maximum of min(srcALen, srcBLen) number of additions is carried internally. + + @remark + Refer to \ref riscv_correlate_q31() for a slower implementation of this function which uses 64-bit accumulation to provide higher precision. + */ + +void riscv_correlate_fast_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst) +{ +#if defined (RISCV_VECTOR) + riscv_correlate_q31(pSrcA, srcALen, pSrcB, srcBLen, pDst); +#else + const q31_t *pIn1; /* InputA pointer */ + const q31_t *pIn2; /* InputB pointer */ + q31_t *pOut = pDst; /* Output pointer */ + const q31_t *px; /* Intermediate inputA pointer */ + const q31_t *py; /* Intermediate inputB pointer */ + const q31_t *pSrc1; /* Intermediate pointers */ + q31_t sum, acc0, acc1, acc2, acc3; /* Accumulators */ + q31_t x0, x1, x2, x3, c0; /* Temporary variables for holding input and coefficient values */ + uint32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + uint32_t j, k, count, blkCnt; /* Loop counters */ + uint32_t outBlockSize; + int32_t inc = 1; /* Destination address modifier */ + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + + /* Number of output samples is calculated */ + outBlockSize = (2U * srcALen) - 1U; + + /* When srcALen > srcBLen, zero padding is done to srcB + * to make their lengths equal. + * Instead, (outBlockSize - (srcALen + srcBLen - 1)) + * number of output samples are made zero */ + j = outBlockSize - (srcALen + (srcBLen - 1U)); + + /* Updating the pointer position to non zero value */ + pOut += j; + + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + + /* CORR(x, y) = Reverse order(CORR(y, x)) */ + /* Hence set the destination pointer to point to the last output sample */ + pOut = pDst + ((srcALen + srcBLen) - 2U); + + /* Destination address modifier is set to -1 */ + inc = -1; + + } + + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* The algorithm is implemented in three stages. + The loop counters of each stage is initiated here. */ + blockSize1 = srcBLen - 1U; + blockSize2 = srcALen - (srcBLen - 1U); + blockSize3 = blockSize1; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[srcBlen - 1] + * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1] + * .... + * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = 1U; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc1 = pIn2 + (srcBLen - 1U); + py = pSrc1; + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* The first stage starts here */ + while (blockSize1 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = count >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* x[0] * y[srcBLen - 4] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py++))) >> 32); + + /* x[1] * y[srcBLen - 3] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py++))) >> 32); + + /* x[2] * y[srcBLen - 2] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py++))) >> 32); + + /* x[3] * y[srcBLen - 1] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py++))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* If the count is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = count % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* x[0] * y[srcBLen - 1] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py++))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = sum << 1; + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = pSrc1 - count; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1] + * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1] + * .... + * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + */ + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + py = pIn2; + + /* count is index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { + /* Loop unroll over blockSize2, by 4 */ + blkCnt = blockSize2 >> 2U; + + while (blkCnt > 0U) + { + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* read x[0], x[1], x[2] samples */ + x0 = *px++; + x1 = *px++; + x2 = *px++; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + do + { + /* Read y[0] sample */ + c0 = *py++; + /* Read x[3] sample */ + x3 = *px++; + + /* Perform the multiply-accumulate */ + /* acc0 += x[0] * y[0] */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32); + /* acc1 += x[1] * y[0] */ + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32); + /* acc2 += x[2] * y[0] */ + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32); + /* acc3 += x[3] * y[0] */ + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32); + + + /* Read y[1] sample */ + c0 = *py++; + /* Read x[4] sample */ + x0 = *px++; + + /* Perform the multiply-accumulate */ + /* acc0 += x[1] * y[1] */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x1 * c0)) >> 32); + /* acc1 += x[2] * y[1] */ + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x2 * c0)) >> 32); + /* acc2 += x[3] * y[1] */ + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x3 * c0)) >> 32); + /* acc3 += x[4] * y[1] */ + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x0 * c0)) >> 32); + + + /* Read y[2] sample */ + c0 = *py++; + /* Read x[5] sample */ + x1 = *px++; + + /* Perform the multiply-accumulates */ + /* acc0 += x[2] * y[2] */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x2 * c0)) >> 32); + /* acc1 += x[3] * y[2] */ + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x3 * c0)) >> 32); + /* acc2 += x[4] * y[2] */ + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x0 * c0)) >> 32); + /* acc3 += x[5] * y[2] */ + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x1 * c0)) >> 32); + + + /* Read y[3] sample */ + c0 = *py++; + /* Read x[6] sample */ + x2 = *px++; + + /* Perform the multiply-accumulates */ + /* acc0 += x[3] * y[3] */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x3 * c0)) >> 32); + /* acc1 += x[4] * y[3] */ + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x0 * c0)) >> 32); + /* acc2 += x[5] * y[3] */ + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x1 * c0)) >> 32); + /* acc3 += x[6] * y[3] */ + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x2 * c0)) >> 32); + + + } while (--k); + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Read y[4] sample */ + c0 = *py++; + /* Read x[7] sample */ + x3 = *px++; + + /* Perform the multiply-accumulates */ + /* acc0 += x[4] * y[4] */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32); + /* acc1 += x[5] * y[4] */ + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32); + /* acc2 += x[6] * y[4] */ + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32); + /* acc3 += x[7] * y[4] */ + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32); + + /* Reuse the present samples for the next MAC */ + x0 = x1; + x1 = x2; + x2 = x3; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q31_t) (acc0 << 1); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + *pOut = (q31_t) (acc1 << 1); + pOut += inc; + + *pOut = (q31_t) (acc2 << 1); + pOut += inc; + + *pOut = (q31_t) (acc3 << 1); + pOut += inc; + + /* Increment the pointer pIn1 index, count by 4 */ + count += 4U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize2 % 0x4U; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py++))) >> 32); + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py++))) >> 32); + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py++))) >> 32); + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py++))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py++))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = sum << 1; + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Increment MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py++))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = sum << 1; + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Increment MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement loop counter */ + blkCnt--; + } + } + + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + * .... + * sum += x[srcALen-2] * y[0] + x[srcALen-1] * y[1] + * sum += x[srcALen-1] * y[0] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = srcBLen - 1U; + + /* Working pointer of inputA */ + pSrc1 = ((pIn1 + srcALen) - srcBLen) + 1U; + px = pSrc1; + + /* Working pointer of inputB */ + py = pIn2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + while (blockSize3 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = count >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* sum += x[srcALen - srcBLen + 4] * y[3] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py++))) >> 32); + + /* sum += x[srcALen - srcBLen + 3] * y[2] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py++))) >> 32); + + /* sum += x[srcALen - srcBLen + 2] * y[1] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py++))) >> 32); + + /* sum += x[srcALen - srcBLen + 1] * y[0] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py++))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* If the count is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = count % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py++))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = sum << 1; + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pIn2; + + /* Decrement MAC count */ + count--; + + /* Decrement loop counter */ + blockSize3--; + } +#endif /*defined (RISCV_VECTOR)*/ +} + +/** + @} end of Corr group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_correlate_opt_q15.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_correlate_opt_q15.c new file mode 100644 index 00000000..4d9a48be --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_correlate_opt_q15.c @@ -0,0 +1,344 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_correlate_opt_q15.c + * Description: Correlation of Q15 sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Corr + @{ + */ + +/** + @brief Correlation of Q15 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. + @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + Both inputs are in 1.15 format and multiplications yield a 2.30 result. + The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + This approach provides 33 guard bits and there is no risk of overflow. + The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format. + + @remark + Refer to \ref riscv_correlate_fast_q15() for a faster but less precise version of this function. + */ + +void riscv_correlate_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch) +{ + q63_t acc0; /* Accumulators */ + q15_t *pOut = pDst; /* Output pointer */ + q15_t *pScr1; /* Temporary pointer for scratch1 */ + const q15_t *pIn1; /* InputA pointer */ + const q15_t *pIn2; /* InputB pointer */ + const q15_t *py; /* Intermediate inputB pointer */ + uint32_t j, blkCnt, outBlockSize; /* Loop counter */ + int32_t inc = 1; /* Output pointer increment */ + uint32_t tapCnt; + +#if defined (RISCV_MATH_LOOPUNROLL) + q63_t acc1, acc2, acc3; /* Accumulators */ + q31_t x1, x2, x3; /* Temporary variables for holding input1 and input2 values */ + q31_t y1, y2; /* State variables */ +#endif + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + /* But CORR(x, y) is reverse of CORR(y, x) */ + /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */ + /* and the destination pointer modifier, inc is set to -1 */ + /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */ + /* But to improve the performance, + * we include zeroes in the output instead of zero padding either of the the inputs*/ + /* If srcALen > srcBLen, + * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */ + /* If srcALen < srcBLen, + * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + + /* Number of output samples is calculated */ + outBlockSize = (srcALen * 2U) - 1U; + + /* When srcALen > srcBLen, zero padding is done to srcB + * to make their lengths equal. + * Instead, (outBlockSize - (srcALen + srcBLen - 1)) + * number of output samples are made zero */ + j = outBlockSize - (srcALen + (srcBLen - 1U)); + + /* Updating the pointer position to non zero value */ + pOut += j; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + + /* CORR(x, y) = Reverse order(CORR(y, x)) */ + /* Hence set the destination pointer to point to the last output sample */ + pOut = pDst + ((srcALen + srcBLen) - 2U); + + /* Destination address modifier is set to -1 */ + inc = -1; + } + + pScr1 = pScratch; + + /* Fill (srcBLen - 1U) zeros in scratch buffer */ + riscv_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update temporary scratch pointer */ + pScr1 += (srcBLen - 1U); + + /* Copy (srcALen) samples in scratch buffer */ + riscv_copy_q15(pIn1, pScr1, srcALen); + + /* Update pointers */ + pScr1 += srcALen; + + + /* Fill (srcBLen - 1U) zeros at end of scratch buffer */ + riscv_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update pointer */ + pScr1 += (srcBLen - 1U); + + /* Temporary pointer for scratch2 */ + py = pIn2; + + + /* Actual correlation process starts here */ +#if defined (RISCV_MATH_LOOPUNROLL) && !defined (RISCV_VECTOR) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (srcALen + srcBLen - 1U) >> 2; + + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch; + + /* Clear Accumlators */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Read two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* Read next two samples from scratch1 buffer */ + x2 = read_q15x2_ia (&pScr1); + + tapCnt = (srcBLen) >> 2U; + + while (tapCnt > 0U) + { + /* Read four samples from smaller buffer */ + y1 = read_q15x2_ia ((q15_t **) &pIn2); + y2 = read_q15x2_ia ((q15_t **) &pIn2); + + /* multiply and accumulate */ + acc0 = __SMLALD(x1, y1, acc0); + acc2 = __SMLALD(x2, y1, acc2); + + /* pack input data */ + x3 = __PKHBT(x2, x1, 0); + + /* multiply and accumulate */ + acc1 = __SMLALDX(x3, y1, acc1); + + /* Read next two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* multiply and accumulate */ + acc0 = __SMLALD(x2, y2, acc0); + acc2 = __SMLALD(x1, y2, acc2); + + /* pack input data */ + x3 = __PKHBT(x1, x2, 0); + + acc3 = __SMLALDX(x3, y1, acc3); + acc1 = __SMLALDX(x3, y2, acc1); + + x2 = read_q15x2_ia (&pScr1); + + x3 = __PKHBT(x2, x1, 0); + + acc3 = __SMLALDX(x3, y2, acc3); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Update scratch pointer for remaining samples of smaller length sequence */ + pScr1 -= 4U; + + /* apply same above for remaining samples of smaller length sequence */ + tapCnt = (srcBLen) & 3U; + + while (tapCnt > 0U) + { + /* accumulate the results */ + acc0 += (*pScr1++ * *pIn2); + acc1 += (*pScr1++ * *pIn2); + acc2 += (*pScr1++ * *pIn2); + acc3 += (*pScr1++ * *pIn2++); + + pScr1 -= 3U; + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + + /* Store the results in the accumulators in the destination buffer. */ + *pOut = (__SSAT(acc0 >> 15U, 16)); + pOut += inc; + *pOut = (__SSAT(acc1 >> 15U, 16)); + pOut += inc; + *pOut = (__SSAT(acc2 >> 15U, 16)); + pOut += inc; + *pOut = (__SSAT(acc3 >> 15U, 16)); + pOut += inc; + + /* Initialization of inputB pointer */ + pIn2 = py; + + pScratch += 4U; + } + + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (srcALen + srcBLen - 1U) & 0x3; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = (srcALen + srcBLen - 1U); + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + /* Calculate correlation for remaining samples of Bigger length sequence */ + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch; + + /* Clear Accumlators */ + acc0 = 0; +#if defined (RISCV_VECTOR) + uint32_t vblkCnt = srcBLen; /* Loop counter */ + size_t l; + vint16m4_t vx, vy; + vint32m1_t temp00m1; + l = vsetvl_e32m1(1); + temp00m1 = vmv_v_x_i32m1(0, l); + for (; (l = vsetvl_e16m4(vblkCnt)) > 0; vblkCnt -= l) { + vx = vle16_v_i16m4(pScr1, l); + pScr1 += l; + vy = vle16_v_i16m4(pIn2, l); + pIn2 += l; + acc0 += vmv_x_s_i32m1_i32(vredsum_vs_i32m8_i32m1(temp00m1, vwmul_vv_i32m8(vx, vy, l), temp00m1, l)); + } +#else + tapCnt = (srcBLen) >> 1U; + + while (tapCnt > 0U) + { + + /* Read next two samples from scratch1 buffer */ + acc0 += (*pScr1++ * *pIn2++); + acc0 += (*pScr1++ * *pIn2++); + + /* Decrement loop counter */ + tapCnt--; + } + + tapCnt = (srcBLen) & 1U; + + /* apply same above for remaining samples of smaller length sequence */ + while (tapCnt > 0U) + { + /* accumulate the results */ + acc0 += (*pScr1++ * *pIn2++); + + /* Decrement loop counter */ + tapCnt--; + } +#endif /*defined (RISCV_VECTOR)*/ + blkCnt--; + + /* The result is in 2.30 format. Convert to 1.15 with saturation. + Then store the output in the destination buffer. */ + *pOut = (q15_t) (__SSAT((acc0 >> 15), 16)); + pOut += inc; + + /* Initialization of inputB pointer */ + pIn2 = py; + + pScratch += 1U; + } + +} + +/** + @} end of Corr group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_correlate_opt_q7.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_correlate_opt_q7.c new file mode 100644 index 00000000..d7791fa8 --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_correlate_opt_q7.c @@ -0,0 +1,433 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_correlate_opt_q7.c + * Description: Correlation of Q7 sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Corr + @{ + */ + +/** + @brief Correlation of Q7 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. + @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 32-bit internal accumulator. + Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result. + The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format. + This approach provides 17 guard bits and there is no risk of overflow as long as max(srcALen, srcBLen)<131072. + The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and then saturated to 1.7 format. + */ + +void riscv_correlate_opt_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2) +{ + q15_t *pScr1 = pScratch1; /* Temporary pointer for scratch */ + q15_t *pScr2 = pScratch2; /* Temporary pointer for scratch */ + q15_t x4; /* Temporary input variable */ + q15_t *py; /* Temporary input2 pointer */ + q31_t acc0, acc1, acc2, acc3; /* Accumulators */ + const q7_t *pIn1, *pIn2; /* InputA and inputB pointer */ + uint32_t j, k, blkCnt, tapCnt; /* Loop counter */ + int32_t inc = 1; /* Output pointer increment */ + uint32_t outBlockSize; /* Loop counter */ + q31_t x1, x2, x3, y1; /* Temporary input variables */ + q7_t *pOut = pDst; /* Output pointer */ + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + /* But CORR(x, y) is reverse of CORR(y, x) */ + /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */ + /* and the destination pointer modifier, inc is set to -1 */ + /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */ + /* But to improve the performance, + * we include zeroes in the output instead of zero padding either of the the inputs*/ + /* If srcALen > srcBLen, + * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */ + /* If srcALen < srcBLen, + * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + + /* Number of output samples is calculated */ + outBlockSize = (srcALen * 2U) - 1U; + + /* When srcALen > srcBLen, zero padding is done to srcB + * to make their lengths equal. + * Instead, (outBlockSize - (srcALen + srcBLen - 1)) + * number of output samples are made zero */ + j = outBlockSize - (srcALen + (srcBLen - 1U)); + + /* Updating the pointer position to non zero value */ + pOut += j; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + + /* CORR(x, y) = Reverse order(CORR(y, x)) */ + /* Hence set the destination pointer to point to the last output sample */ + pOut = pDst + ((srcALen + srcBLen) - 2U); + + /* Destination address modifier is set to -1 */ + inc = -1; + } + +#if defined (RISCV_VECTOR) + uint32_t vblkCnt = srcBLen; /* Loop counter */ + size_t l; + vint16m8_t vx; + for (; (l = vsetvl_e8m4(vblkCnt)) > 0; vblkCnt -= l) { + vx = vwadd_vx_i16m8(vle8_v_i8m4(pIn2, l),0, l); + pIn2 += l; + vse16_v_i16m8(pScr2, vx, l); + pScr2 += l; + } +#else + /* Copy (srcBLen) samples in scratch buffer */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling copies 4 data points at a time. + a second loop below copies for the remaining 1 to 3 samples. */ + while (k > 0U) + { +// #if __RISCV_XLEN == 64 && defined RISCV_MATH_DSP +// write_q15x4_ia(&pScr2,read_q15x4_ia((q15_t **)&pIn2)); +// #else + /* copy second buffer in reversal manner */ + x4 = (q15_t) *pIn2++; + *pScr2++ = x4; + x4 = (q15_t) *pIn2++; + *pScr2++ = x4; + x4 = (q15_t) *pIn2++; + *pScr2++ = x4; + x4 = (q15_t) *pIn2++; + *pScr2++ = x4; +// #endif /*__RISCV_XLEN == 64 && defined RISCV_MATH_DSP*/ + /* Decrement loop counter */ + k--; + } + + /* If the count is not a multiple of 4, copy remaining samples here. + No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* copy second buffer in reversal manner for remaining samples */ + x4 = (q15_t) *pIn2++; + *pScr2++ = x4; + + /* Decrement loop counter */ + k--; + } +#endif /*defined (RISCV_VECTOR)*/ + /* Fill (srcBLen - 1U) zeros in scratch buffer */ + riscv_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update temporary scratch pointer */ + pScr1 += (srcBLen - 1U); +#if defined (RISCV_VECTOR) + vblkCnt = srcBLen; /* Loop counter */ + for (; (l = vsetvl_e8m4(vblkCnt)) > 0; vblkCnt -= l) { + vx = vwadd_vx_i16m8(vle8_v_i8m4(pIn1, l),0, l); + pIn1 += l; + vse16_v_i16m8(pScr1, vx, l); + pScr1 += l; + } +#else + /* Copy (srcALen) samples in scratch buffer */ + /* Apply loop unrolling and do 4 Copies simultaneously. */ + k = srcALen >> 2U; + + /* First part of the processing with loop unrolling copies 4 data points at a time. + a second loop below copies for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* copy second buffer in reversal manner */ + x4 = (q15_t) *pIn1++; + *pScr1++ = x4; + x4 = (q15_t) *pIn1++; + *pScr1++ = x4; + x4 = (q15_t) *pIn1++; + *pScr1++ = x4; + x4 = (q15_t) *pIn1++; + *pScr1++ = x4; + + /* Decrement loop counter */ + k--; + } + + /* If the count is not a multiple of 4, copy remaining samples here. + No loop unrolling is used. */ + k = srcALen % 0x4U; + + while (k > 0U) + { + /* copy second buffer in reversal manner for remaining samples */ + x4 = (q15_t) * pIn1++; + *pScr1++ = x4; + + /* Decrement the loop counter */ + k--; + } +#endif /*defined (RISCV_VECTOR)*/ + /* Fill (srcBLen - 1U) zeros at end of scratch buffer */ + riscv_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update pointer */ + pScr1 += (srcBLen - 1U); + + /* Temporary pointer for scratch2 */ + py = pScratch2; + + /* Initialization of pScr2 pointer */ + pScr2 = pScratch2; +#if defined (RISCV_VECTOR) + blkCnt = (srcALen + srcBLen - 1U); + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch1; + + /* Clear Accumlators */ + acc0 = 0; + + uint32_t vblkCnt = srcBLen; /* Loop counter */ + size_t l; + vint16m4_t vx, vy; + vint32m1_t temp00m1; + l = vsetvl_e32m1(1); + temp00m1 = vmv_v_x_i32m1(0, l); + for (; (l = vsetvl_e16m4(vblkCnt)) > 0; vblkCnt -= l) { + vx = vle16_v_i16m4(pScr1, l); + pScr1 += l; + vy = vle16_v_i16m4(pScr2, l); + pScr2 += l; + acc0 += vmv_x_s_i32m1_i32(vredsum_vs_i32m8_i32m1(temp00m1, vwmul_vv_i32m8(vx, vy, l), temp00m1, l)); + } + + blkCnt--; + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q7_t) (__SSAT(acc0 >> 7U, 8)); + pOut += inc; + + /* Initialization of inputB pointer */ + pScr2 = py; + + pScratch1 += 1U; + } +#else + /* Actual correlation process starts here */ + blkCnt = (srcALen + srcBLen - 1U) >> 2; + + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch1; + + /* Clear Accumlators */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Read two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* Read next two samples from scratch1 buffer */ + x2 = read_q15x2_ia (&pScr1); + + tapCnt = (srcBLen) >> 2U; + + while (tapCnt > 0U) + { + /* Read four samples from smaller buffer */ + y1 = read_q15x2_ia (&pScr2); + + /* multiply and accumulate */ + acc0 = __SMLAD(x1, y1, acc0); + acc2 = __SMLAD(x2, y1, acc2); + + /* pack input data */ + x3 = __PKHBT(x2, x1, 0); + + /* multiply and accumulate */ + acc1 = __SMLADX(x3, y1, acc1); + + /* Read next two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* pack input data */ + x3 = __PKHBT(x1, x2, 0); + + acc3 = __SMLADX(x3, y1, acc3); + + /* Read four samples from smaller buffer */ + y1 = read_q15x2_ia (&pScr2); + + acc0 = __SMLAD(x2, y1, acc0); + + acc2 = __SMLAD(x1, y1, acc2); + + acc1 = __SMLADX(x3, y1, acc1); + + x2 = read_q15x2_ia (&pScr1); + + x3 = __PKHBT(x2, x1, 0); + + acc3 = __SMLADX(x3, y1, acc3); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Update scratch pointer for remaining samples of smaller length sequence */ + pScr1 -= 4U; + + /* apply same above for remaining samples of smaller length sequence */ + tapCnt = (srcBLen) & 3U; + + while (tapCnt > 0U) + { + /* accumulate the results */ + acc0 += (*pScr1++ * *pScr2); + acc1 += (*pScr1++ * *pScr2); + acc2 += (*pScr1++ * *pScr2); + acc3 += (*pScr1++ * *pScr2++); + + pScr1 -= 3U; + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q7_t) (__SSAT(acc0 >> 7U, 8)); + pOut += inc; + *pOut = (q7_t) (__SSAT(acc1 >> 7U, 8)); + pOut += inc; + *pOut = (q7_t) (__SSAT(acc2 >> 7U, 8)); + pOut += inc; + *pOut = (q7_t) (__SSAT(acc3 >> 7U, 8)); + pOut += inc; + + /* Initialization of inputB pointer */ + pScr2 = py; + + pScratch1 += 4U; + } + + blkCnt = (srcALen + srcBLen - 1U) & 0x3; + + /* Calculate correlation for remaining samples of Bigger length sequence */ + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch1; + + /* Clear Accumlators */ + acc0 = 0; + + tapCnt = (srcBLen) >> 1U; + + while (tapCnt > 0U) + { + acc0 += (*pScr1++ * *pScr2++); + acc0 += (*pScr1++ * *pScr2++); + + /* Decrement loop counter */ + tapCnt--; + } + + tapCnt = (srcBLen) & 1U; + + /* apply same above for remaining samples of smaller length sequence */ + while (tapCnt > 0U) + { + /* accumulate the results */ + acc0 += (*pScr1++ * *pScr2++); + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q7_t) (__SSAT(acc0 >> 7U, 8)); + pOut += inc; + + /* Initialization of inputB pointer */ + pScr2 = py; + + pScratch1 += 1U; + } +#endif /*defined (RISCV_VECTOR)*/ +} + +/** + @} end of Corr group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_correlate_q15.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_correlate_q15.c new file mode 100644 index 00000000..84e3a8ca --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_correlate_q15.c @@ -0,0 +1,770 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_correlate_q15.c + * Description: Correlation of Q15 sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Corr + @{ + */ + +/** + @brief Correlation of Q15 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + Both inputs are in 1.15 format and multiplications yield a 2.30 result. + The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + This approach provides 33 guard bits and there is no risk of overflow. + The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format. + + @remark + Refer to \ref riscv_correlate_fast_q15() for a faster but less precise version of this function. + @remark + Refer to \ref riscv_correlate_opt_q15() for a faster implementation of this function using scratch buffers. + */ +void riscv_correlate_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst) +{ + +#if defined (RISCV_MATH_DSP) || defined (RISCV_VECTOR) + + const q15_t *pIn1; /* InputA pointer */ + const q15_t *pIn2; /* InputB pointer */ + q15_t *pOut = pDst; /* Output pointer */ + q63_t sum, acc0, acc1, acc2, acc3; /* Accumulators */ + const q15_t *px; /* Intermediate inputA pointer */ + const q15_t *py; /* Intermediate inputB pointer */ + const q15_t *pSrc1; /* Intermediate pointers */ + q31_t x0, x1, x2, x3, c0; /* Temporary input variables for holding input and coefficient values */ + uint32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + uint32_t j, k, count, blkCnt; /* Loop counters */ + uint32_t outBlockSize; + int32_t inc = 1; /* Destination address modifier */ + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + /* But CORR(x, y) is reverse of CORR(y, x) */ + /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */ + /* and the destination pointer modifier, inc is set to -1 */ + /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */ + /* But to improve the performance, + * we include zeroes in the output instead of zero padding either of the the inputs*/ + /* If srcALen > srcBLen, + * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */ + /* If srcALen < srcBLen, + * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + + /* Number of output samples is calculated */ + outBlockSize = (srcALen * 2U) - 1U; + + /* When srcALen > srcBLen, zero padding is done to srcB + * to make their lengths equal. + * Instead, (outBlockSize - (srcALen + srcBLen - 1)) + * number of output samples are made zero */ + j = outBlockSize - (srcALen + (srcBLen - 1U)); + + /* Updating the pointer position to non zero value */ + pOut += j; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + + /* CORR(x, y) = Reverse order(CORR(y, x)) */ + /* Hence set the destination pointer to point to the last output sample */ + pOut = pDst + ((srcALen + srcBLen) - 2U); + + /* Destination address modifier is set to -1 */ + inc = -1; + } + + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* The algorithm is implemented in three stages. + The loop counters of each stage is initiated here. */ + blockSize1 = srcBLen - 1U; + blockSize2 = srcALen - (srcBLen - 1U); + blockSize3 = blockSize1; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[srcBlen - 1] + * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1] + * .... + * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = 1U; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc1 = pIn2 + (srcBLen - 1U); + py = pSrc1; + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* The first loop starts here */ + while (blockSize1 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; +#if defined (RISCV_VECTOR) + uint32_t vblkCnt = count; /* Loop counter */ + size_t l; + vint16m4_t vx, vy; + vint32m1_t temp00m1; + l = vsetvl_e32m1(1); + temp00m1 = vmv_v_x_i32m1(0, l); + for (; (l = vsetvl_e16m4(vblkCnt)) > 0; vblkCnt -= l) { + vx = vle16_v_i16m4(px, l); + px += l; + vy = vle16_v_i16m4(py, l); + py += l; + sum += vmv_x_s_i32m1_i32(vredsum_vs_i32m8_i32m1(temp00m1, vwmul_vv_i32m8(vx, vy, l), temp00m1, l)); + } +#else + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = count >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { +#if __RISCV_XLEN == 64 + sum = __RV_SMALDA(sum, read_q15x4_ia ((q15_t **) &px), read_q15x4_ia ((q15_t **) &py)); +#else + /* Perform the multiply-accumulate */ + /* x[0] * y[srcBLen - 4] , x[1] * y[srcBLen - 3] */ + sum = __SMLALD(read_q15x2_ia ((q15_t **) &px), read_q15x2_ia ((q15_t **) &py), sum); + /* x[3] * y[srcBLen - 1] , x[2] * y[srcBLen - 2] */ + sum = __SMLALD(read_q15x2_ia ((q15_t **) &px), read_q15x2_ia ((q15_t **) &py), sum); +#endif /* __RISCV_XLEN == 64 */ + + /* Decrement loop counter */ + k--; + } + + /* If the count is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = count % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* x[0] * y[srcBLen - 1] */ + sum = __SMLALD(*px++, *py++, sum); + + /* Decrement loop counter */ + k--; + } +#endif /*defined (RISCV_VECTOR)*/ + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q15_t) (__SSAT((sum >> 15), 16)); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = pSrc1 - count; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1] + * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1] + * .... + * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + */ + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + py = pIn2; + + /* count is the index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ +#if defined (RISCV_VECTOR) + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + uint32_t vblkCnt = srcBLen; /* Loop counter */ + size_t l; + vint16m4_t vx, vy; + vint32m1_t temp00m1; + ptrdiff_t bstride = -2; + l = vsetvl_e32m1(1); + temp00m1 = vmv_v_x_i32m1(0, l); + for (; (l = vsetvl_e16m4(vblkCnt)) > 0; vblkCnt -= l) { + vx = vle16_v_i16m4(px, l); + px += l; + vy = vlse16_v_i16m4(py, bstride, l); + py -= l; + sum += vmv_x_s_i32m1_i32(vredsum_vs_i32m8_i32m1(temp00m1, vwmul_vv_i32m8(vx, vy, l), temp00m1, l)); + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q15_t) (__SSAT(sum >> 15, 16)); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Increment the MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement the loop counter */ + blkCnt--; + } +#else + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize2 >> 2U; + + while (blkCnt > 0U) + { + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* read x[0], x[1] samples */ + x0 = read_q15x2 ((q15_t *) px); + + /* read x[1], x[2] samples */ + x1 = read_q15x2 ((q15_t *) px + 1); + px += 2U; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + do + { + /* Read the first two inputB samples using SIMD: + * y[0] and y[1] */ + c0 = read_q15x2_ia ((q15_t **) &py); + + /* acc0 += x[0] * y[0] + x[1] * y[1] */ + acc0 = __SMLALD(x0, c0, acc0); + + /* acc1 += x[1] * y[0] + x[2] * y[1] */ + acc1 = __SMLALD(x1, c0, acc1); + + /* Read x[2], x[3] */ + x2 = read_q15x2 ((q15_t *) px); + + /* Read x[3], x[4] */ + x3 = read_q15x2 ((q15_t *) px + 1); + + /* acc2 += x[2] * y[0] + x[3] * y[1] */ + acc2 = __SMLALD(x2, c0, acc2); + + /* acc3 += x[3] * y[0] + x[4] * y[1] */ + acc3 = __SMLALD(x3, c0, acc3); + + /* Read y[2] and y[3] */ + c0 = read_q15x2_ia ((q15_t **) &py); + + /* acc0 += x[2] * y[2] + x[3] * y[3] */ + acc0 = __SMLALD(x2, c0, acc0); + + /* acc1 += x[3] * y[2] + x[4] * y[3] */ + acc1 = __SMLALD(x3, c0, acc1); + + /* Read x[4], x[5] */ + x0 = read_q15x2 ((q15_t *) px + 2); + + /* Read x[5], x[6] */ + x1 = read_q15x2 ((q15_t *) px + 3); + px += 4U; + + /* acc2 += x[4] * y[2] + x[5] * y[3] */ + acc2 = __SMLALD(x0, c0, acc2); + + /* acc3 += x[5] * y[2] + x[6] * y[3] */ + acc3 = __SMLALD(x1, c0, acc3); + + } while (--k); + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + if (k == 1U) + { + /* Read y[4] */ + c0 = *py; + c0 = c0 & 0x0000FFFF; + + /* Read x[7] */ + x3 = read_q15x2 ((q15_t *) px); + px++; + + /* Perform the multiply-accumulate */ + acc0 = __SMLALD (x0, c0, acc0); + acc1 = __SMLALD (x1, c0, acc1); + acc2 = __SMLALDX(x1, c0, acc2); + acc3 = __SMLALDX(x3, c0, acc3); + } + + if (k == 2U) + { + /* Read y[4], y[5] */ + c0 = read_q15x2 ((q15_t *) py); + + /* Read x[7], x[8] */ + x3 = read_q15x2 ((q15_t *) px); + + /* Read x[9] */ + x2 = read_q15x2 ((q15_t *) px + 1); + px += 2U; + + /* Perform the multiply-accumulate */ + acc0 = __SMLALD(x0, c0, acc0); + acc1 = __SMLALD(x1, c0, acc1); + acc2 = __SMLALD(x3, c0, acc2); + acc3 = __SMLALD(x2, c0, acc3); + } + + if (k == 3U) + { + /* Read y[4], y[5] */ + c0 = read_q15x2_ia ((q15_t **) &py); + + /* Read x[7], x[8] */ + x3 = read_q15x2 ((q15_t *) px); + + /* Read x[9] */ + x2 = read_q15x2 ((q15_t *) px + 1); + + /* Perform the multiply-accumulate */ + acc0 = __SMLALD(x0, c0, acc0); + acc1 = __SMLALD(x1, c0, acc1); + acc2 = __SMLALD(x3, c0, acc2); + acc3 = __SMLALD(x2, c0, acc3); + + c0 = (*py); + + /* Read y[6] */ + c0 = c0 & 0x0000FFFF; + + /* Read x[10] */ + x3 = read_q15x2 ((q15_t *) px + 2); + px += 3U; + + /* Perform the multiply-accumulates */ + acc0 = __SMLALDX(x1, c0, acc0); + acc1 = __SMLALD (x2, c0, acc1); + acc2 = __SMLALDX(x2, c0, acc2); + acc3 = __SMLALDX(x3, c0, acc3); + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q15_t) (__SSAT(acc0 >> 15, 16)); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + *pOut = (q15_t) (__SSAT(acc1 >> 15, 16)); + pOut += inc; + + *pOut = (q15_t) (__SSAT(acc2 >> 15, 16)); + pOut += inc; + + *pOut = (q15_t) (__SSAT(acc3 >> 15, 16)); + pOut += inc; + + /* Increment the count by 4 as 4 output values are computed */ + count += 4U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize2 % 0x4U; +// #if __RISCV_XLEN == 64 +// q63_t acc064, acc164; +// #endif /* __RISCV_XLEN == 64 */ + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { +#if __RISCV_XLEN == 64 +// acc064 = read_q15x4_ia((q15_t **) &px); +// acc164 = read_q15x4_ia((q15_t **) &py); + sum = __RV_SMALDA(sum, read_q15x4_ia((q15_t **) &px), read_q15x4_ia((q15_t **) &py)); +#else + /* Perform the multiply-accumulates */ + sum += ((q63_t) *px++ * *py++); + sum += ((q63_t) *px++ * *py++); + sum += ((q63_t) *px++ * *py++); + sum += ((q63_t) *px++ * *py++); +#endif /* __RISCV_XLEN == 64 */ + /* Decrement loop counter */ + k--; + } + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum += ((q63_t) *px++ * *py++); + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q15_t) (__SSAT(sum >> 15, 16)); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Increment count by 1, as one output value is computed */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += ((q63_t) *px++ * *py++); + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q15_t) (__SSAT(sum >> 15, 16)); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Increment the MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement the loop counter */ + blkCnt--; + } + } +#endif /*defined (RISCV_VECTOR)*/ + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + * .... + * sum += x[srcALen-2] * y[0] + x[srcALen-1] * y[1] + * sum += x[srcALen-1] * y[0] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = srcBLen - 1U; + + /* Working pointer of inputA */ + pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U); + px = pSrc1; + + /* Working pointer of inputB */ + py = pIn2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + while (blockSize3 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; +#if defined (RISCV_VECTOR) + uint32_t vblkCnt = count; /* Loop counter */ + size_t l; + vint16m4_t vx, vy; + vint32m1_t temp00m1; + l = vsetvl_e32m1(1); + temp00m1 = vmv_v_x_i32m1(0, l); + for (; (l = vsetvl_e16m4(vblkCnt)) > 0; vblkCnt -= l) { + vx = vle16_v_i16m4(px, l); + px += l; + vy = vle16_v_i16m4(py, l); + py += l; + sum += vmv_x_s_i32m1_i32(vredsum_vs_i32m8_i32m1(temp00m1, vwmul_vv_i32m8(vx, vy, l), temp00m1, l)); + } + +#else + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = count >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { +#if __RISCV_XLEN == 64 + sum = __SMLALD(read_q15x4_ia ((q15_t **) &px), read_q15x4_ia ((q15_t **) &py), sum); +#else + /* Perform the multiply-accumulate */ + /* sum += x[srcALen - srcBLen + 4] * y[3] , sum += x[srcALen - srcBLen + 3] * y[2] */ + sum = __SMLALD(read_q15x2_ia ((q15_t **) &px), read_q15x2_ia ((q15_t **) &py), sum); + /* sum += x[srcALen - srcBLen + 2] * y[1] , sum += x[srcALen - srcBLen + 1] * y[0] */ + sum = __SMLALD(read_q15x2_ia ((q15_t **) &px), read_q15x2_ia ((q15_t **) &py), sum); +#endif /* __RISCV_XLEN == 64 */ + + /* Decrement loop counter */ + k--; + } + + /* If the count is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = count % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum = __SMLALD(*px++, *py++, sum); + + /* Decrement loop counter */ + k--; + } +#endif /*defined (RISCV_VECTOR)*/ + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q15_t) (__SSAT((sum >> 15), 16)); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pIn2; + + /* Decrement MAC count */ + count--; + + /* Decrement loop counter */ + blockSize3--; + } + +#else /* #if defined (RISCV_MATH_DSP) */ + + const q15_t *pIn1 = pSrcA; /* InputA pointer */ + const q15_t *pIn2 = pSrcB + (srcBLen - 1U); /* InputB pointer */ + q63_t sum; /* Accumulators */ + int32_t i = 0U, j; /* Loop counters */ + uint32_t inv = 0U; /* Reverse order flag */ + uint32_t tot = 0U; /* Length */ + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + /* But CORR(x, y) is reverse of CORR(y, x) */ + /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */ + /* and a varaible, inv is set to 1 */ + /* If lengths are not equal then zero pad has to be done to make the two + * inputs of same length. But to improve the performance, we include zeroes + * in the output instead of zero padding either of the the inputs*/ + /* If srcALen > srcBLen, (srcALen - srcBLen) zeroes has to included in the + * starting of the output buffer */ + /* If srcALen < srcBLen, (srcALen - srcBLen) zeroes has to included in the + * ending of the output buffer */ + /* Once the zero padding is done the remaining of the output is calcualted + * using convolution but with the shorter signal time shifted. */ + + /* Calculate the length of the remaining sequence */ + tot = ((srcALen + srcBLen) - 2U); + + if (srcALen > srcBLen) + { + /* Calculating the number of zeros to be padded to the output */ + j = srcALen - srcBLen; + + /* Initialise the pointer after zero padding */ + pDst += j; + } + + else if (srcALen < srcBLen) + { + /* Initialization to inputB pointer */ + pIn1 = pSrcB; + + /* Initialization to the end of inputA pointer */ + pIn2 = pSrcA + (srcALen - 1U); + + /* Initialisation of the pointer after zero padding */ + pDst = pDst + tot; + + /* Swapping the lengths */ + j = srcALen; + srcALen = srcBLen; + srcBLen = j; + + /* Setting the reverse flag */ + inv = 1; + } + + /* Loop to calculate convolution for output length number of values */ + for (i = 0U; i <= tot; i++) + { + /* Initialize sum with zero to carry on MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0U; j <= i; j++) + { + /* Check the array limitations */ + if (((i - j) < srcBLen) && (j < srcALen)) + { + /* z[i] += x[i-j] * y[j] */ + sum += ((q31_t) pIn1[j] * pIn2[-((int32_t) i - (int32_t) j)]); + } + } + + /* Store the output in the destination buffer */ + if (inv == 1) + *pDst-- = (q15_t) __SSAT((sum >> 15U), 16U); + else + *pDst++ = (q15_t) __SSAT((sum >> 15U), 16U); + } + +#endif /* #if defined (RISCV_MATH_DSP) */ + +} + +/** + @} end of Corr group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_correlate_q31.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_correlate_q31.c new file mode 100644 index 00000000..ae0dcef2 --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_correlate_q31.c @@ -0,0 +1,673 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_correlate_q31.c + * Description: Correlation of Q31 sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Corr + @{ + */ + +/** + @brief Correlation of Q31 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + There is no saturation on intermediate additions. + Thus, if the accumulator overflows it wraps around and distorts the result. + The input signals should be scaled down to avoid intermediate overflows. + Scale down one of the inputs by 1/min(srcALen, srcBLen)to avoid overflows since a + maximum of min(srcALen, srcBLen) number of additions is carried internally. + The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result. + + @remark + Refer to \ref riscv_correlate_fast_q31() for a faster but less precise implementation of this function. + */ +void riscv_correlate_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst) +{ + + + + const q31_t *pIn1; /* InputA pointer */ + const q31_t *pIn2; /* InputB pointer */ + q31_t *pOut = pDst; /* Output pointer */ + const q31_t *px; /* Intermediate inputA pointer */ + const q31_t *py; /* Intermediate inputB pointer */ + const q31_t *pSrc1; /* Intermediate pointers */ + q63_t sum; /* Accumulators */ + uint32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + uint32_t j, k, count, blkCnt; /* Loop counters */ + uint32_t outBlockSize; + int32_t inc = 1; /* Destination address modifier */ + +#if defined (RISCV_MATH_LOOPUNROLL) + q63_t acc0, acc1, acc2; /* Accumulators */ + q31_t x0, x1, x2, c0; /* Temporary variables for holding input and coefficient values */ +#if __RISCV_XLEN == 64 + q63_t acc064, acc164, acc264; +#endif /* __RISCV_XLEN == 64 */ +#endif + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + /* But CORR(x, y) is reverse of CORR(y, x) */ + /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */ + /* and the destination pointer modifier, inc is set to -1 */ + /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */ + /* But to improve the performance, + * we include zeroes in the output instead of zero padding either of the the inputs*/ + /* If srcALen > srcBLen, + * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */ + /* If srcALen < srcBLen, + * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + + /* Number of output samples is calculated */ + outBlockSize = (2U * srcALen) - 1U; + + /* When srcALen > srcBLen, zero padding is done to srcB + * to make their lengths equal. + * Instead, (outBlockSize - (srcALen + srcBLen - 1)) + * number of output samples are made zero */ + j = outBlockSize - (srcALen + (srcBLen - 1U)); + + /* Updating the pointer position to non zero value */ + pOut += j; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + + /* CORR(x, y) = Reverse order(CORR(y, x)) */ + /* Hence set the destination pointer to point to the last output sample */ + pOut = pDst + ((srcALen + srcBLen) - 2U); + + /* Destination address modifier is set to -1 */ + inc = -1; + } + + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* The algorithm is implemented in three stages. + The loop counters of each stage is initiated here. */ + blockSize1 = srcBLen - 1U; + blockSize2 = srcALen - (srcBLen - 1U); + blockSize3 = blockSize1; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[srcBlen - 1] + * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1] + * .... + * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = 1U; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc1 = pIn2 + (srcBLen - 1U); + py = pSrc1; + + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* The first stage starts here */ + while (blockSize1 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (RISCV_MATH_LOOPUNROLL) && !defined (RISCV_VECTOR) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + + while (k > 0U) + { +#if __RISCV_XLEN == 64 + acc064 = read_q31x2_ia(&px); + acc164 = read_q31x2_ia(&py); + sum = __RV_KMADA32(sum, acc064, acc164); + acc064 = read_q31x2_ia(&px); + acc164 = read_q31x2_ia(&py); + sum = __RV_KMADA32(sum, acc064, acc164); +#else + /* x[0] * y[srcBLen - 4] */ + sum += (q63_t) *px++ * (*py++); + + /* x[1] * y[srcBLen - 3] */ + sum += (q63_t) *px++ * (*py++); + + /* x[2] * y[srcBLen - 2] */ + sum += (q63_t) *px++ * (*py++); + + /* x[3] * y[srcBLen - 1] */ + sum += (q63_t) *px++ * (*py++); +#endif /* __RISCV_XLEN == 64 */ + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize k with number of samples */ + k = count; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ +#if defined (RISCV_VECTOR) + uint32_t vblkCnt = count; /* Loop counter */ + size_t l; + vint32m4_t vx, vy; + vint64m1_t temp00m1; + l = vsetvl_e64m1(1); + temp00m1 = vmv_v_x_i64m1(0, l); + for (; (l = vsetvl_e32m4(vblkCnt)) > 0; vblkCnt -= l) { + vx = vle32_v_i32m4(px, l); + px += l; + vy = vle32_v_i32m4(py, l); + py += l; + sum += vmv_x_s_i64m1_i64(vredsum_vs_i64m8_i64m1(temp00m1, vwmul_vv_i64m8(vx, vy, l), temp00m1, l)); + } +#else + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* x[0] * y[srcBLen - 1] */ + sum += (q63_t) *px++ * (*py++); + + /* Decrement loop counter */ + k--; + } +#endif /*defined (RISCV_VECTOR)*/ + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q31_t) (sum >> 31); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = pSrc1 - count; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1] + * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1] + * .... + * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + */ + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + py = pIn2; + + /* count is index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ +#if defined (RISCV_VECTOR) + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + uint32_t vblkCnt = srcBLen; /* Loop counter */ + size_t l; + vint32m4_t vx, vy; + vint64m1_t temp00m1; + l = vsetvl_e64m1(1); + temp00m1 = vmv_v_x_i64m1(0, l); + for (; (l = vsetvl_e32m4(vblkCnt)) > 0; vblkCnt -= l) { + vx = vle32_v_i32m4(px, l); + px += l; + vy = vle32_v_i32m4(py, l); + py += l; + sum += vmv_x_s_i64m1_i64(vredsum_vs_i64m8_i64m1(temp00m1, vwmul_vv_i64m8(vx, vy, l), temp00m1, l)); + } + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q31_t) (sum >> 31); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Increment MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement loop counter */ + blkCnt--; + } +#else + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unroll by 3 */ + blkCnt = blockSize2 / 3; + + while (blkCnt > 0U) + { + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + + /* read x[0], x[1] samples */ + x0 = *px++; + x1 = *px++; + + /* Apply loop unrolling and compute 3 MACs simultaneously. */ + k = srcBLen / 3; + + /* First part of the processing with loop unrolling. Compute 3 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 2 samples. */ + do + { + /* Read y[0] sample */ + c0 = *(py); + /* Read x[2] sample */ + x2 = *(px); + + /* Perform the multiply-accumulate */ + /* acc0 += x[0] * y[0] */ + acc0 += ((q63_t) x0 * c0); + /* acc1 += x[1] * y[0] */ + acc1 += ((q63_t) x1 * c0); + /* acc2 += x[2] * y[0] */ + acc2 += ((q63_t) x2 * c0); + + /* Read y[1] sample */ + c0 = *(py + 1U); + /* Read x[3] sample */ + x0 = *(px + 1U); + + /* Perform the multiply-accumulate */ + /* acc0 += x[1] * y[1] */ + acc0 += ((q63_t) x1 * c0); + /* acc1 += x[2] * y[1] */ + acc1 += ((q63_t) x2 * c0); + /* acc2 += x[3] * y[1] */ + acc2 += ((q63_t) x0 * c0); + + /* Read y[2] sample */ + c0 = *(py + 2U); + /* Read x[4] sample */ + x1 = *(px + 2U); + + /* Perform the multiply-accumulate */ + /* acc0 += x[2] * y[2] */ + acc0 += ((q63_t) x2 * c0); + /* acc1 += x[3] * y[2] */ + acc1 += ((q63_t) x0 * c0); + /* acc2 += x[4] * y[2] */ + acc2 += ((q63_t) x1 * c0); + + /* update scratch pointers */ + px += 3U; + py += 3U; + + } while (--k); + + /* If the srcBLen is not a multiple of 3, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen - (3 * (srcBLen / 3)); + + while (k > 0U) + { + /* Read y[4] sample */ + c0 = *(py++); + + /* Read x[7] sample */ + x2 = *(px++); + + /* Perform the multiply-accumulates */ + /* acc0 += x[4] * y[4] */ + acc0 += ((q63_t) x0 * c0); + /* acc1 += x[5] * y[4] */ + acc1 += ((q63_t) x1 * c0); + /* acc2 += x[6] * y[4] */ + acc2 += ((q63_t) x2 * c0); + + /* Reuse the present samples for the next MAC */ + x0 = x1; + x1 = x2; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q31_t) (acc0 >> 31); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + *pOut = (q31_t) (acc1 >> 31); + pOut += inc; + + *pOut = (q31_t) (acc2 >> 31); + pOut += inc; + + /* Increment the pointer pIn1 index, count by 3 */ + count += 3U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize2 - 3 * (blockSize2 / 3); + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize2; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = srcBLen >> 2U; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum += (q63_t) *px++ * *py++; + sum += (q63_t) *px++ * *py++; + sum += (q63_t) *px++ * *py++; + sum += (q63_t) *px++ * *py++; + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = srcBLen % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = srcBLen; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += (q63_t) *px++ * *py++; + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q31_t) (sum >> 31); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Increment MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += (q63_t) *px++ * *py++; + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q31_t) (sum >> 31); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Increment MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement loop counter */ + blkCnt--; + } + } +#endif /*defined (RISCV_VECTOR)*/ + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + * .... + * sum += x[srcALen-2] * y[0] + x[srcALen-1] * y[1] + * sum += x[srcALen-1] * y[0] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = srcBLen - 1U; + + /* Working pointer of inputA */ + pSrc1 = pIn1 + (srcALen - (srcBLen - 1U)); + px = pSrc1; + + /* Working pointer of inputB */ + py = pIn2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + while (blockSize3 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (RISCV_MATH_LOOPUNROLL) && !defined (RISCV_VECTOR) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* sum += x[srcALen - srcBLen + 4] * y[3] */ + sum += (q63_t) *px++ * *py++; + + /* sum += x[srcALen - srcBLen + 3] * y[2] */ + sum += (q63_t) *px++ * *py++; + + /* sum += x[srcALen - srcBLen + 2] * y[1] */ + sum += (q63_t) *px++ * *py++; + + /* sum += x[srcALen - srcBLen + 1] * y[0] */ + sum += (q63_t) *px++ * *py++; + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = count; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ +#if defined (RISCV_VECTOR) + uint32_t vblkCnt = count; /* Loop counter */ + size_t l; + vint32m4_t vx, vy; + vint64m1_t temp00m1; + l = vsetvl_e64m1(1); + temp00m1 = vmv_v_x_i64m1(0, l); + for (; (l = vsetvl_e32m4(vblkCnt)) > 0; vblkCnt -= l) { + vx = vle32_v_i32m4(px, l); + px += l; + vy = vle32_v_i32m4(py, l); + py += l; + sum += vmv_x_s_i64m1_i64(vredsum_vs_i64m8_i64m1(temp00m1, vwmul_vv_i64m8(vx, vy, l), temp00m1, l)); + } +#else + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += (q63_t) *px++ * *py++; + + /* Decrement loop counter */ + k--; + } +#endif /*defined (RISCV_VECTOR)*/ + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q31_t) (sum >> 31); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pIn2; + + /* Decrement MAC count */ + count--; + + /* Decrement loop counter */ + blockSize3--; + } + + +} + +/** + @} end of Corr group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_correlate_q7.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_correlate_q7.c new file mode 100644 index 00000000..f11c4200 --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_correlate_q7.c @@ -0,0 +1,802 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_correlate_q7.c + * Description: Correlation of Q7 sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Corr + @{ + */ + +/** + @brief Correlation of Q7 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 32-bit internal accumulator. + Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result. + The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format. + This approach provides 17 guard bits and there is no risk of overflow as long as max(srcALen, srcBLen)<131072. + The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and saturated to 1.7 format. + + @remark + Refer to \ref riscv_correlate_opt_q7() for a faster implementation of this function. + */ +void riscv_correlate_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst) +{ + + + + const q7_t *pIn1; /* InputA pointer */ + const q7_t *pIn2; /* InputB pointer */ + q7_t *pOut = pDst; /* Output pointer */ + const q7_t *px; /* Intermediate inputA pointer */ + const q7_t *py; /* Intermediate inputB pointer */ + const q7_t *pSrc1; /* Intermediate pointers */ + q31_t sum; /* Accumulators */ + uint32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + uint32_t j, k, count, blkCnt; /* Loop counters */ + uint32_t outBlockSize; + int32_t inc = 1; + +#if defined (RISCV_MATH_LOOPUNROLL) + q31_t acc0, acc1, acc2, acc3; /* Accumulators */ + q31_t input1, input2; /* Temporary input variables */ + q15_t in1, in2; /* Temporary input variables */ + q7_t x0, x1, x2, x3, c0, c1; /* Temporary variables for holding input and coefficient values */ +// #if __RISCV_XLEN == 64 +// q63_t input164, input264; /* Temporary input variables */ +// q63_t in164, in264; /* Temporary input variables */ +// #endif /* __RISCV_XLEN == 64 */ +#endif + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + /* But CORR(x, y) is reverse of CORR(y, x) */ + /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */ + /* and the destination pointer modifier, inc is set to -1 */ + /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */ + /* But to improve the performance, + * we include zeroes in the output instead of zero padding either of the the inputs*/ + /* If srcALen > srcBLen, + * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */ + /* If srcALen < srcBLen, + * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + + /* Number of output samples is calculated */ + outBlockSize = (2U * srcALen) - 1U; + + /* When srcALen > srcBLen, zero padding is done to srcB + * to make their lengths equal. + * Instead, (outBlockSize - (srcALen + srcBLen - 1)) + * number of output samples are made zero */ + j = outBlockSize - (srcALen + (srcBLen - 1U)); + + /* Updating the pointer position to non zero value */ + pOut += j; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + + /* CORR(x, y) = Reverse order(CORR(y, x)) */ + /* Hence set the destination pointer to point to the last output sample */ + pOut = pDst + ((srcALen + srcBLen) - 2U); + + /* Destination address modifier is set to -1 */ + inc = -1; + } + + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* The algorithm is implemented in three stages. + The loop counters of each stage is initiated here. */ + blockSize1 = srcBLen - 1U; + blockSize2 = srcALen - (srcBLen - 1U); + blockSize3 = blockSize1; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[srcBlen - 1] + * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1] + * .... + * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = 1U; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc1 = pIn2 + (srcBLen - 1U); + py = pSrc1; + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* The first stage starts here */ + while (blockSize1 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (RISCV_MATH_LOOPUNROLL) && !defined (RISCV_VECTOR) +// #if __RISCV_XLEN == 64 +// /* Loop unrolling: Compute 8 outputs at a time */ +// k = count >> 3U; +// #else + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; +// #endif +// #if __RISCV_XLEN == 64 +// py -= 7; +// #endif /* __RISCV_XLEN == 64 */ + while (k > 0U) + { +// #if __RISCV_XLEN == 64 +// in164 = read_q7x8_ia ((q7_t **) &px); +// in264 = read_q7x8_da ((q7_t **) &py); +// sum = __RV_SMAQA(sum, input1, input2); +// #else + /* x[0] , x[1] */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* y[srcBLen - 4] , y[srcBLen - 3] */ + in1 = (q15_t) *py++; + in2 = (q15_t) *py++; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* x[0] * y[srcBLen - 4] */ + /* x[1] * y[srcBLen - 3] */ + sum = __SMLAD(input1, input2, sum); + + /* x[2] , x[3] */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* y[srcBLen - 2] , y[srcBLen - 1] */ + in1 = (q15_t) *py++; + in2 = (q15_t) *py++; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* x[2] * y[srcBLen - 2] */ + /* x[3] * y[srcBLen - 1] */ + sum = __SMLAD(input1, input2, sum); +// #endif /* __RISCV_XLEN == 64 */ + /* Decrement loop counter */ + k--; + } +// #if __RISCV_XLEN == 64 +// py += 7; +// #endif /* __RISCV_XLEN == 64 */ +// #if __RISCV_XLEN == 64 +// /* Loop unrolling: Compute remaining outputs */ +// k = count % 0x8U; +// #else + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; +// #endif +#else + + /* Initialize k with number of samples */ + k = count; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ +#if defined (RISCV_VECTOR) + uint32_t vblkCnt = count; /* Loop counter */ + size_t l; + vint8m4_t vx, vy; + vint16m1_t temp00m1; + l = vsetvl_e16m1(1); + temp00m1 = vmv_v_x_i16m1(0, l); + for (; (l = vsetvl_e8m4(vblkCnt)) > 0; vblkCnt -= l) { + vx = vle8_v_i8m4(px, l); + px += l; + vy = vle8_v_i8m4(py, l); + py += l; + sum += vmv_x_s_i16m1_i16(vredsum_vs_i16m8_i16m1(temp00m1, vwmul_vv_i16m8(vx, vy, l), temp00m1, l)); + } +#else + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* x[0] * y[srcBLen - 1] */ + sum += (q31_t) ((q15_t) *px++ * *py++); + + /* Decrement loop counter */ + k--; + } +#endif /*defined (RISCV_VECTOR)*/ + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q7_t) (__SSAT(sum >> 7U, 8)); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = pSrc1 - count; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1] + * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1] + * .... + * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + */ + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + py = pIn2; + + /* count is index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ +#if defined (RISCV_VECTOR) + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + uint32_t vblkCnt = srcBLen; /* Loop counter */ + size_t l; + vint8m4_t vx, vy; + vint16m1_t temp00m1; + l = vsetvl_e16m1(1); + temp00m1 = vmv_v_x_i16m1(0, l); + for (; (l = vsetvl_e8m4(vblkCnt)) > 0; vblkCnt -= l) { + vx = vle8_v_i8m4(px, l); + px += l; + vy = vle8_v_i8m4(py, l); + py += l; + sum += vmv_x_s_i16m1_i16(vredsum_vs_i16m8_i16m1(temp00m1, vwmul_vv_i16m8(vx, vy, l), temp00m1, l)); + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q7_t) (__SSAT(sum >> 7U, 8)); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Increment the MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement loop counter */ + blkCnt--; + } +#else + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize2 >> 2U; + + while (blkCnt > 0U) + { + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* read x[0], x[1], x[2] samples */ + x0 = *px++; + x1 = *px++; + x2 = *px++; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + do + { + /* Read y[0] sample */ + c0 = *py++; + /* Read y[1] sample */ + c1 = *py++; + + /* Read x[3] sample */ + x3 = *px++; + + /* x[0] and x[1] are packed */ + in1 = (q15_t) x0; + in2 = (q15_t) x1; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* y[0] and y[1] are packed */ + in1 = (q15_t) c0; + in2 = (q15_t) c1; + + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* acc0 += x[0] * y[0] + x[1] * y[1] */ + acc0 = __SMLAD(input1, input2, acc0); + + /* x[1] and x[2] are packed */ + in1 = (q15_t) x1; + in2 = (q15_t) x2; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* acc1 += x[1] * y[0] + x[2] * y[1] */ + acc1 = __SMLAD(input1, input2, acc1); + + /* x[2] and x[3] are packed */ + in1 = (q15_t) x2; + in2 = (q15_t) x3; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* acc2 += x[2] * y[0] + x[3] * y[1] */ + acc2 = __SMLAD(input1, input2, acc2); + + /* Read x[4] sample */ + x0 = *px++; + + /* x[3] and x[4] are packed */ + in1 = (q15_t) x3; + in2 = (q15_t) x0; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* acc3 += x[3] * y[0] + x[4] * y[1] */ + acc3 = __SMLAD(input1, input2, acc3); + + /* Read y[2] sample */ + c0 = *py++; + /* Read y[3] sample */ + c1 = *py++; + + /* Read x[5] sample */ + x1 = *px++; + + /* x[2] and x[3] are packed */ + in1 = (q15_t) x2; + in2 = (q15_t) x3; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* y[2] and y[3] are packed */ + in1 = (q15_t) c0; + in2 = (q15_t) c1; + + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* acc0 += x[2] * y[2] + x[3] * y[3] */ + acc0 = __SMLAD(input1, input2, acc0); + + /* x[3] and x[4] are packed */ + in1 = (q15_t) x3; + in2 = (q15_t) x0; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* acc1 += x[3] * y[2] + x[4] * y[3] */ + acc1 = __SMLAD(input1, input2, acc1); + + /* x[4] and x[5] are packed */ + in1 = (q15_t) x0; + in2 = (q15_t) x1; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* acc2 += x[4] * y[2] + x[5] * y[3] */ + acc2 = __SMLAD(input1, input2, acc2); + + /* Read x[6] sample */ + x2 = *px++; + + /* x[5] and x[6] are packed */ + in1 = (q15_t) x1; + in2 = (q15_t) x2; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* acc3 += x[5] * y[2] + x[6] * y[3] */ + acc3 = __SMLAD(input1, input2, acc3); + + } while (--k); + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Read y[4] sample */ + c0 = *py++; + /* Read x[7] sample */ + x3 = *px++; + + /* Perform the multiply-accumulates */ + /* acc0 += x[4] * y[4] */ + acc0 += ((q15_t) x0 * c0); + /* acc1 += x[5] * y[4] */ + acc1 += ((q15_t) x1 * c0); + /* acc2 += x[6] * y[4] */ + acc2 += ((q15_t) x2 * c0); + /* acc3 += x[7] * y[4] */ + acc3 += ((q15_t) x3 * c0); + + /* Reuse the present samples for the next MAC */ + x0 = x1; + x1 = x2; + x2 = x3; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q7_t) (__SSAT(acc0 >> 7, 8)); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + *pOut = (q7_t) (__SSAT(acc1 >> 7, 8)); + pOut += inc; + + *pOut = (q7_t) (__SSAT(acc2 >> 7, 8)); + pOut += inc; + + *pOut = (q7_t) (__SSAT(acc3 >> 7, 8)); + pOut += inc; + + count += 4U; + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize2 % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize2; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = srcBLen >> 2U; + + while (k > 0U) + { + + /* Reading two inputs of SrcA buffer and packing */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* Reading two inputs of SrcB buffer and packing */ + in1 = (q15_t) *py++; + in2 = (q15_t) *py++; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* Perform the multiply-accumulate */ + sum = __SMLAD(input1, input2, sum); + + /* Reading two inputs of SrcA buffer and packing */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* Reading two inputs of SrcB buffer and packing */ + in1 = (q15_t) *py++; + in2 = (q15_t) *py++; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* Perform the multiply-accumulate */ + sum = __SMLAD(input1, input2, sum); + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = srcBLen % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = srcBLen; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += ((q15_t) *px++ * *py++); + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q7_t) (__SSAT(sum >> 7U, 8)); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Increment the pointer pIn1 index, count by 1 */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += ((q15_t) *px++ * *py++); + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q7_t) (__SSAT(sum >> 7U, 8)); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Increment the MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement loop counter */ + blkCnt--; + } + } +#endif /*defined (RISCV_VECTOR)*/ + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + * .... + * sum += x[srcALen-2] * y[0] + x[srcALen-1] * y[1] + * sum += x[srcALen-1] * y[0] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = srcBLen - 1U; + + /* Working pointer of inputA */ + pSrc1 = pIn1 + (srcALen - (srcBLen - 1U)); + px = pSrc1; + + /* Working pointer of inputB */ + py = pIn2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + while (blockSize3 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (RISCV_MATH_LOOPUNROLL) && !defined (RISCV_VECTOR) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + + while (k > 0U) + { + /* x[srcALen - srcBLen + 1] , x[srcALen - srcBLen + 2] */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* y[0] , y[1] */ + in1 = (q15_t) *py++; + in2 = (q15_t) *py++; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* sum += x[srcALen - srcBLen + 1] * y[0] */ + /* sum += x[srcALen - srcBLen + 2] * y[1] */ + sum = __SMLAD(input1, input2, sum); + + /* x[srcALen - srcBLen + 3] , x[srcALen - srcBLen + 4] */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* y[2] , y[3] */ + in1 = (q15_t) *py++; + in2 = (q15_t) *py++; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* sum += x[srcALen - srcBLen + 3] * y[2] */ + /* sum += x[srcALen - srcBLen + 4] * y[3] */ + sum = __SMLAD(input1, input2, sum); + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = count; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ +#if defined (RISCV_VECTOR) + uint32_t vblkCnt = blockSize3; /* Loop counter */ + size_t l; + vint8m4_t vx, vy; + vint16m1_t temp00m1; + l = vsetvl_e16m1(1); + temp00m1 = vmv_v_x_i16m1(0, l); + for (; (l = vsetvl_e8m4(vblkCnt)) > 0; vblkCnt -= l) { + vx = vle8_v_i8m4(px, l); + px += l; + vy = vle8_v_i8m4(py, l); + py += l; + sum += vmv_x_s_i16m1_i16(vredsum_vs_i16m8_i16m1(temp00m1, vwmul_vv_i16m8(vx, vy, l), temp00m1, l)); + } +#else + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += ((q15_t) *px++ * *py++); + + /* Decrement loop counter */ + k--; + } +#endif /*defined (RISCV_VECTOR)*/ + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q7_t) (__SSAT(sum >> 7U, 8)); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pIn2; + + /* Decrement MAC count */ + count--; + + /* Decrement loop counter */ + blockSize3--; + } + + +} + +/** + @} end of Corr group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_decimate_f32.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_decimate_f32.c new file mode 100644 index 00000000..81a75b05 --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_decimate_f32.c @@ -0,0 +1,506 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_fir_decimate_f32.c + * Description: FIR decimation for floating-point sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @defgroup FIR_decimate Finite Impulse Response (FIR) Decimator + + These functions combine an FIR filter together with a decimator. + They are used in multirate systems for reducing the sample rate of a signal without introducing aliasing distortion. + Conceptually, the functions are equivalent to the block diagram below: + \image html FIRDecimator.png "Components included in the FIR Decimator functions" + When decimating by a factor of M, the signal should be prefiltered by a lowpass filter with a normalized + cutoff frequency of 1/M in order to prevent aliasing distortion. + The user of the function is responsible for providing the filter coefficients. + + The FIR decimator functions provided in the NMSIS DSP Library combine the FIR filter and the decimator in an efficient manner. + Instead of calculating all of the FIR filter outputs and discarding M-1 out of every M, only the + samples output by the decimator are computed. + The functions operate on blocks of input and output data. + pSrc points to an array of blockSize input values and + pDst points to an array of blockSize/M output values. + In order to have an integer number of output samples blockSize + must always be a multiple of the decimation factor M. + + The library provides separate functions for Q15, Q31 and floating-point data types. + + @par Algorithm: + The FIR portion of the algorithm uses the standard form filter: + 
+      y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]
+
+ where, b[n] are the filter coefficients. + @par + The pCoeffs points to a coefficient array of size numTaps. + Coefficients are stored in time reversed order. + @par + 
+      {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ @par + pState points to a state array of size numTaps + blockSize - 1. + Samples in the state buffer are stored in the order: + @par + 
+      {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}
+
+ The state variables are updated after each block of data is processed, the coefficients are untouched. + + @par Instance Structure + The coefficients and state variables for a filter are stored together in an instance data structure. + A separate instance structure must be defined for each filter. + Coefficient arrays may be shared among several instances while state variable array should be allocated separately. + There are separate instance structure declarations for each of the 3 supported data types. + + @par Initialization Functions + There is also an associated initialization function for each data type. + The initialization function performs the following operations: + - Sets the values of the internal structure fields. + - Zeros out the values in the state buffer. + - Checks to make sure that the size of the input is a multiple of the decimation factor. + To do this manually without calling the init function, assign the follow subfields of the instance structure: + numTaps, pCoeffs, M (decimation factor), pState. Also set all of the values in pState to zero. + @par + Use of the initialization function is optional. + However, if the initialization function is used, then the instance structure cannot be placed into a const data section. + To place an instance structure into a const data section, the instance structure must be manually initialized. + The code below statically initializes each of the 3 different data type filter instance structures + 
+      riscv_fir_decimate_instance_f32 S = {M, numTaps, pCoeffs, pState};
+      riscv_fir_decimate_instance_q31 S = {M, numTaps, pCoeffs, pState};
+      riscv_fir_decimate_instance_q15 S = {M, numTaps, pCoeffs, pState};
+
+ where M is the decimation factor; numTaps is the number of filter coefficients in the filter; + pCoeffs is the address of the coefficient buffer; + pState is the address of the state buffer. + Be sure to set the values in the state buffer to zeros when doing static initialization. + + @par Fixed-Point Behavior + Care must be taken when using the fixed-point versions of the FIR decimate filter functions. + In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + Refer to the function specific documentation below for usage guidelines. + */ + +/** + @addtogroup FIR_decimate + @{ + */ + +/** + @brief Processing function for floating-point FIR decimator. + @param[in] S points to an instance of the floating-point FIR decimator structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + */ +void riscv_fir_decimate_f32( + const riscv_fir_decimate_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *pStateCur; /* Points to the current sample of the state */ + float32_t *px0; /* Temporary pointer for state buffer */ + const float32_t *pb; /* Temporary pointer for coefficient buffer */ + float32_t x0, c0; /* Temporary variables to hold state and coefficient values */ + float32_t acc0; /* Accumulator */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i, tapCnt, blkCnt, outBlockSize = blockSize / S->M; /* Loop counters */ + +#if defined (RISCV_MATH_LOOPUNROLL) + float32_t *px1, *px2, *px3; + float32_t x1, x2, x3; + float32_t acc1, acc2, acc3; +#endif + + /* S->pState buffer contains previous frame (numTaps - 1) samples */ + /* pStateCur points to the location where the new input data should be written */ + pStateCur = S->pState + (numTaps - 1U); + +#if defined (RISCV_MATH_LOOPUNROLL) && !defined (RISCV_VECTOR) + + /* Loop unrolling: Compute 4 samples at a time */ + blkCnt = outBlockSize >> 2U; + + /* Samples loop unrolled by 4 */ + while (blkCnt > 0U) + { + /* Copy 4 * decimation factor number of new input samples into the state buffer */ + i = S->M * 4; + + do + { + *pStateCur++ = *pSrc++; + + } while (--i); + + /* Set accumulators to zero */ + acc0 = 0.0f; + acc1 = 0.0f; + acc2 = 0.0f; + acc3 = 0.0f; + + /* Initialize state pointer for all the samples */ + px0 = pState; + px1 = pState + S->M; + px2 = pState + 2 * S->M; + px3 = pState + 3 * S->M; + + /* Initialize coeff pointer */ + pb = pCoeffs; + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Read the b[numTaps-1] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-1] sample for acc0 */ + x0 = *(px0++); + /* Read x[n-numTaps-1] sample for acc1 */ + x1 = *(px1++); + /* Read x[n-numTaps-1] sample for acc2 */ + x2 = *(px2++); + /* Read x[n-numTaps-1] sample for acc3 */ + x3 = *(px3++); + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + acc2 += x2 * c0; + acc3 += x3 * c0; + + /* Read the b[numTaps-2] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-2] sample for acc0, acc1, acc2, acc3 */ + x0 = *(px0++); + x1 = *(px1++); + x2 = *(px2++); + x3 = *(px3++); + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + acc2 += x2 * c0; + acc3 += x3 * c0; + + /* Read the b[numTaps-3] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-3] sample acc0, acc1, acc2, acc3 */ + x0 = *(px0++); + x1 = *(px1++); + x2 = *(px2++); + x3 = *(px3++); + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + acc2 += x2 * c0; + acc3 += x3 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-4] sample acc0, acc1, acc2, acc3 */ + x0 = *(px0++); + x1 = *(px1++); + x2 = *(px2++); + x3 = *(px3++); + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + acc2 += x2 * c0; + acc3 += x3 * c0; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *(pb++); + + /* Fetch state variables for acc0, acc1, acc2, acc3 */ + x0 = *(px0++); + x1 = *(px1++); + x2 = *(px2++); + x3 = *(px3++); + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + acc2 += x2 * c0; + acc3 += x3 * c0; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + S->M * 4; + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst++ = acc0; + *pDst++ = acc1; + *pDst++ = acc2; + *pDst++ = acc3; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining samples */ + blkCnt = outBlockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = outBlockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Copy decimation factor number of new input samples into the state buffer */ +#if defined (RISCV_VECTOR) + uint32_t blkCnti = S->M; /* Loop counter */ + size_t l; + + for (; (l = vsetvl_e32m8(blkCnti)) > 0; blkCnti -= l) { + vse32_v_f32m8 (pStateCur, vle32_v_f32m8(pSrc, l), l); + pSrc += l; + pStateCur += l; + } +#else + i = S->M; + + do + { + *pStateCur++ = *pSrc++; + + } while (--i); +#endif /*defined (RISCV_VECTOR)*/ + /* Set accumulator to zero */ + acc0 = 0.0f; + + /* Initialize state pointer */ + px0 = pState; + + /* Initialize coeff pointer */ + pb = pCoeffs; + +#if defined (RISCV_MATH_LOOPUNROLL) && !defined (RISCV_VECTOR) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Read the b[numTaps-1] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-1] sample */ + x0 = *px0++; + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + + /* Read the b[numTaps-2] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-2] sample */ + x0 = *px0++; + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + + /* Read the b[numTaps-3] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-3] sample */ + x0 = *px0++; + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-4] sample */ + x0 = *px0++; + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = numTaps; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ +#if defined (RISCV_VECTOR) + uint32_t blkCntb; + vfloat32m4_t va1m4,va2m4; + vfloat32m4_t vch00m4; + vfloat32m1_t vch00m1; + vfloat32m1_t vtemp00m1; + vfloat32m4_t vach00m4; + blkCntb = numTaps; /* Loop counter */ + // q7_t temp[] = {0}; + l = vsetvl_e32m4(blkCntb); + //initial array to zero + vach00m4 = vfmv_v_f_f32m4(0, l); + l = vsetvl_e32m4(1); + vtemp00m1 = vfmv_v_f_f32m1(0, l); + for (; (l = vsetvl_e32m4(blkCntb)) > 0; blkCntb -= l) { + va1m4 = vle32_v_f32m4(pb, l); + va2m4 = vle32_v_f32m4(px0, l); + pb += l; + px0 += l; + vch00m4 = vfmul_vv_f32m4(va1m4, va2m4, l); + vach00m4 = vfadd_vv_f32m4(vach00m4, vch00m4, l); + } + //Here we calculate sum of four vector + //set vl to max vl + l = vsetvl_e32m4(numTaps); + //calculate sum + vch00m1 = vfredsum_vs_f32m4_f32m1(vtemp00m1, vach00m4, vtemp00m1, l); + //set vl to 1 + l = vsetvl_e32m1(1); + //wrfte result scalar back + acc0 += (float32_t)vfmv_f_s_f32m1_f32(vch00m1); +#else + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *pb++; + + /* Fetch 1 state variable */ + x0 = *px0++; + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + + /* Decrement loop counter */ + tapCnt--; + } +#endif /*defined (RISCV_VECTOR)*/ + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + S->M; + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst++ = acc0; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the satrt of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCur = S->pState; + +#if defined (RISCV_MATH_LOOPUNROLL) && !defined (RISCV_VECTOR) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = (numTaps - 1U) >> 2U; + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = (numTaps - 1U) % 0x04U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = (numTaps - 1U); + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ +#if defined (RISCV_VECTOR) + uint32_t blkCnti = tapCnt; /* Loop counter */ + size_t l; + + for (; (l = vsetvl_e32m8(blkCnti)) > 0; blkCnti -= l) { + vse32_v_f32m8 (pStateCur, vle32_v_f32m8(pState, l), l); + pState += l; + pStateCur += l; + } +#else + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } +#endif /*defined (RISCV_VECTOR)*/ +} + +/** + @} end of FIR_decimate group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_decimate_fast_q15.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_decimate_fast_q15.c new file mode 100644 index 00000000..21224132 --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_decimate_fast_q15.c @@ -0,0 +1,651 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_fir_decimate_fast_q15.c + * Description: Fast Q15 FIR Decimator + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_decimate + @{ + */ + +/** + @brief Processing function for the Q15 FIR decimator (fast variant). + @param[in] S points to an instance of the Q15 FIR decimator structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of input samples to process per call + @return none + + @par Scaling and Overflow Behavior + This fast version uses a 32-bit accumulator with 2.30 format. + The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit. + Thus, if the accumulator result overflows it wraps around and distorts the result. + In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits (log2 is read as log to the base 2). + The 2.30 accumulator is then truncated to 2.15 format and saturated to yield the 1.15 result. + @remark + Refer to \ref riscv_fir_decimate_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion. + Both the slow and the fast versions use the same instance structure. + Use function \ref riscv_fir_decimate_init_q15() to initialize the filter structure. + */ + +#if defined (RISCV_MATH_DSP) + +void riscv_fir_decimate_fast_q15( + const riscv_fir_decimate_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCur; /* Points to the current sample of the state */ + q15_t *px; /* Temporary pointer for state buffer */ + const q15_t *pb; /* Temporary pointer for coefficient buffer */ + q31_t x0, x1, c0; /* Temporary variables to hold state and coefficient values */ + q31_t sum0; /* Accumulators */ + q31_t acc0, acc1; + q15_t *px0, *px1; + uint32_t blkCntN3; + uint32_t numTaps = S->numTaps; /* Number of taps */ + uint32_t i, blkCnt, tapCnt, outBlockSize = blockSize / S->M; /* Loop counters */ + +#if defined (RISCV_MATH_LOOPUNROLL) + q31_t c1; /* Temporary variables to hold state and coefficient values */ +#if __RISCV_XLEN == 64 + q63_t x064, x164, c064, sum064 = 0; +#endif /* __RISCV_XLEN == 64 */ +#endif + + /* S->pState buffer contains previous frame (numTaps - 1) samples */ + /* pStateCur points to the location where the new input data should be written */ + pStateCur = S->pState + (numTaps - 1U); + + /* Total number of output samples to be computed */ + blkCnt = outBlockSize / 2; + blkCntN3 = outBlockSize - (2 * blkCnt); + + while (blkCnt > 0U) + { + /* Copy 2 * decimation factor number of new input samples into the state buffer */ + i = S->M * 2; + + do + { + *pStateCur++ = *pSrc++; + + } while (--i); + + /* Set accumulator to zero */ + acc0 = 0; + acc1 = 0; + + /* Initialize state pointer for all the samples */ + px0 = pState; + px1 = pState + S->M; + + /* Initialize coeff pointer */ + pb = pCoeffs; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { +#if __RISCV_XLEN == 64 + /* Read the b[numTaps-1] and b[numTaps-2] coefficients */ + c064 = read_q15x4_ia ((q15_t **) &pb); + + /* Read x[n-numTaps-1] and x[n-numTaps-2]sample */ + x064 = read_q15x4_ia ((q15_t **) &px0); + x164 = read_q15x4_ia ((q15_t **) &px1); + + acc0 = __RV_SMALDA(acc0, x064, c064); + acc1 = __RV_SMALDA(acc1, x164, c064); + +#else + /* Read the b[numTaps-1] and b[numTaps-2] coefficients */ + c0 = read_q15x2_ia ((q15_t **) &pb); + + /* Read x[n-numTaps-1] and x[n-numTaps-2]sample */ + x0 = read_q15x2_ia (&px0); + x1 = read_q15x2_ia (&px1); + + /* Perform the multiply-accumulate */ + acc0 = __SMLAD(x0, c0, acc0); + acc1 = __SMLAD(x1, c0, acc1); + + /* Read the b[numTaps-3] and b[numTaps-4] coefficient */ + c0 = read_q15x2_ia ((q15_t **) &pb); + + /* Read x[n-numTaps-2] and x[n-numTaps-3] sample */ + x0 = read_q15x2_ia (&px0); + x1 = read_q15x2_ia (&px1); + + /* Perform the multiply-accumulate */ + acc0 = __SMLAD(x0, c0, acc0); + acc1 = __SMLAD(x1, c0, acc1); +#endif /* __RISCV_XLEN == 64 */ + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = numTaps; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *pb++; + + /* Fetch state variables for acc0, acc1 */ + x0 = *px0++; + x1 = *px1++; + + /* Perform the multiply-accumulate */ + acc0 = __SMLAD(x0, c0, acc0); + acc1 = __SMLAD(x1, c0, acc1); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + S->M * 2; + + /* Store filter output, smlad returns the values in 2.14 format */ + /* so downsacle by 15 to get output in 1.15 */ + *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16)); + *pDst++ = (q15_t) (__SSAT((acc1 >> 15), 16)); + + /* Decrement loop counter */ + blkCnt--; + } + + while (blkCntN3 > 0U) + { + /* Copy decimation factor number of new input samples into the state buffer */ + i = S->M; + + do + { + *pStateCur++ = *pSrc++; + + } while (--i); + + /* Set accumulator to zero */ + sum0 = 0; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coeff pointer */ + pb = pCoeffs; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { +#if __RISCV_XLEN == 64 + /* Read the b[numTaps-1] and b[numTaps-2] coefficients */ + c064 = read_q15x4_ia ((q15_t **) &pb); + + /* Read x[n-numTaps-1] and x[n-numTaps-2] sample */ + x064 = read_q15x4_ia ((q15_t **) &px); + + sum064 = __SMLAD(x064, c064, sum064); +#else + /* Read the b[numTaps-1] and b[numTaps-2] coefficients */ + c0 = read_q15x2_ia ((q15_t **) &pb); + + /* Read x[n-numTaps-1] and x[n-numTaps-2] sample */ + x0 = read_q15x2_ia (&px); + + /* Read the b[numTaps-3] and b[numTaps-4] coefficients */ + c1 = read_q15x2_ia ((q15_t **) &pb); + + /* Perform the multiply-accumulate */ + sum0 = __SMLAD(x0, c0, sum0); + + /* Read x[n-numTaps-2] and x[n-numTaps-3] sample */ + x0 = read_q15x2_ia (&px); + + /* Perform the multiply-accumulate */ + sum0 = __SMLAD(x0, c1, sum0); +#endif + /* Decrement loop counter */ + tapCnt--; + } +#if __RISCV_XLEN == 64 + sum0 =(q31_t)((sum064 + (sum064<<32u))>>32u); +#endif + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = numTaps; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *pb++; + + /* Fetch 1 state variable */ + x0 = *px++; + + /* Perform the multiply-accumulate */ + sum0 = __SMLAD(x0, c0, sum0); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + S->M; + + /* Store filter output, smlad returns the values in 2.14 format */ + /* so downsacle by 15 to get output in 1.15 */ + *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16)); + + /* Decrement loop counter */ + blkCntN3--; + } + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the satrt of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCur = S->pState; + + i = (numTaps - 1U) >> 2U; + + /* copy data */ + while (i > 0U) + { + write_q15x2_ia (&pStateCur, read_q15x2_ia (&pState)); + write_q15x2_ia (&pStateCur, read_q15x2_ia (&pState)); + + /* Decrement loop counter */ + i--; + } + + i = (numTaps - 1U) % 0x04U; + + /* Copy data */ + while (i > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + i--; + } + +} + +#else /* #if defined (RISCV_MATH_DSP) */ + +void riscv_fir_decimate_fast_q15( + const riscv_fir_decimate_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCur; /* Points to the current sample of the state */ + q15_t *px; /* Temporary pointer for state buffer */ + const q15_t *pb; /* Temporary pointer for coefficient buffer */ + q15_t x0, x1, c0; /* Temporary variables to hold state and coefficient values */ + q31_t sum0; /* Accumulators */ + q31_t acc0, acc1; + q15_t *px0, *px1; + uint32_t blkCntN3; + uint32_t numTaps = S->numTaps; /* Number of taps */ + uint32_t i, blkCnt, tapCnt, outBlockSize = blockSize / S->M; /* Loop counters */ + + + /* S->pState buffer contains previous frame (numTaps - 1) samples */ + /* pStateCur points to the location where the new input data should be written */ + pStateCur = S->pState + (numTaps - 1U); + + /* Total number of output samples to be computed */ + blkCnt = outBlockSize / 2; + blkCntN3 = outBlockSize - (2 * blkCnt); + + while (blkCnt > 0U) + { + /* Copy 2 * decimation factor number of new input samples into the state buffer */ + i = S->M * 2; +#if defined (RISCV_VECTOR) + uint32_t blkCnti = i; /* Loop counter */ + size_t l; + + for (; (l = vsetvl_e16m8(blkCnti)) > 0; blkCnti -= l) { + vse16_v_i16m8 (pStateCur, vle16_v_i16m8(pSrc, l), l); + pSrc += l; + pStateCur += l; + } +#else + do + { + *pStateCur++ = *pSrc++; + + } while (--i); +#endif + + /* Set accumulator to zero */ + acc0 = 0; + acc1 = 0; + + /* Initialize state pointer */ + px0 = pState; + px1 = pState + S->M; + + /* Initialize coeff pointer */ + pb = pCoeffs; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Read the Read b[numTaps-1] coefficients */ + c0 = *pb++; + + /* Read x[n-numTaps-1] for sample 0 and for sample 1 */ + x0 = *px0++; + x1 = *px1++; + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + + /* Read the b[numTaps-2] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-2] for sample 0 and sample 1 */ + x0 = *px0++; + x1 = *px1++; + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + + /* Read the b[numTaps-3] coefficients */ + c0 = *pb++; + + /* Read x[n-numTaps-3] for sample 0 and sample 1 */ + x0 = *px0++; + x1 = *px1++; + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-4] for sample 0 and sample 1 */ + x0 = *px0++; + x1 = *px1++; + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = numTaps; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *pb++; + + /* Fetch 1 state variable */ + x0 = *px0++; + x1 = *px1++; + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + S->M * 2; + + /* Store filter output, smlad returns the values in 2.14 format */ + /* so downsacle by 15 to get output in 1.15 */ + + *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16)); + *pDst++ = (q15_t) (__SSAT((acc1 >> 15), 16)); + + /* Decrement loop counter */ + blkCnt--; + } + + while (blkCntN3 > 0U) + { + /* Copy decimation factor number of new input samples into the state buffer */ + i = S->M; +#if defined (RISCV_VECTOR) + uint32_t blkCnti = i; /* Loop counter */ + size_t l; + + for (; (l = vsetvl_e16m8(blkCnti)) > 0; blkCnti -= l) { + vse16_v_i16m8 (pStateCur, vle16_v_i16m8(pSrc, l), l); + pSrc += l; + pStateCur += l; + } +#else + do + { + *pStateCur++ = *pSrc++; + + } while (--i); +#endif + /* Set accumulator to zero */ + sum0 = 0; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coeff pointer */ + pb = pCoeffs; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Read the b[numTaps-1] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-1] sample */ + x0 = *px++; + + /* Perform the multiply-accumulate */ + sum0 += x0 * c0; + + /* Read the b[numTaps-2] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-2] sample */ + x0 = *px++; + + /* Perform the multiply-accumulate */ + sum0 += x0 * c0; + + /* Read the b[numTaps-3] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-3] sample */ + x0 = *px++; + + /* Perform the multiply-accumulate */ + sum0 += x0 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-4] sample */ + x0 = *px++; + + /* Perform the multiply-accumulate */ + sum0 += x0 * c0; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = numTaps; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *pb++; + + /* Fetch 1 state variable */ + x0 = *px++; + + /* Perform the multiply-accumulate */ + sum0 += x0 * c0; + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + S->M; + + /* Store filter output, smlad returns the values in 2.14 format */ + /* so downsacle by 15 to get output in 1.15 */ + *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16)); + + /* Decrement loop counter */ + blkCntN3--; + } + + /* Processing is complete. + ** Now copy the last numTaps - 1 samples to the satrt of the state buffer. + ** This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCur = S->pState; +#if defined (RISCV_VECTOR) + uint32_t blkCnti = (numTaps - 1U); /* Loop counter */ + size_t l; + + for (; (l = vsetvl_e16m8(blkCnti)) > 0; blkCnti -= l) { + vse16_v_i16m8 (pStateCur, vle16_v_i16m8(pSrc, l), l); + pSrc += l; + pStateCur += l; + } +#else + i = (numTaps - 1U) >> 2U; + + /* copy data */ + while (i > 0U) + { + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + i--; + } + + i = (numTaps - 1U) % 0x04U; + + /* copy data */ + while (i > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + i--; + } +#endif +} + +#endif /* #if defined (RISCV_MATH_DSP) */ + +/** + @} end of FIR_decimate group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_decimate_fast_q31.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_decimate_fast_q31.c new file mode 100644 index 00000000..1c6f0bd1 --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_decimate_fast_q31.c @@ -0,0 +1,414 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_fir_decimate_fast_q31.c + * Description: Fast Q31 FIR Decimator + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_decimate + @{ + */ + +/** + @brief Processing function for the Q31 FIR decimator (fast variant). + @param[in] S points to an instance of the Q31 FIR decimator structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + This function is optimized for speed at the expense of fixed-point precision and overflow protection. + The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format. + These intermediate results are added to a 2.30 accumulator. + Finally, the accumulator is saturated and converted to a 1.31 result. + The fast version has the same overflow behavior as the standard version and provides less precision since it discards the low 32 bits of each multiplication result. + In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits (where log2 is read as log to the base 2). + + @remark + Refer to \ref riscv_fir_decimate_q31() for a slower implementation of this function which uses a 64-bit accumulator to provide higher precision. + Both the slow and the fast versions use the same instance structure. + Use function \ref riscv_fir_decimate_init_q31() to initialize the filter structure. + */ + +void riscv_fir_decimate_fast_q31( + const riscv_fir_decimate_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + q31_t *pState = S->pState; /* State pointer */ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *pStateCur; /* Points to the current sample of the state */ + q31_t *px0; /* Temporary pointer for state buffer */ + const q31_t *pb; /* Temporary pointer for coefficient buffer */ + q31_t x0, c0; /* Temporary variables to hold state and coefficient values */ + q63_t acc0; /* Accumulator */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i, tapCnt, blkCnt, outBlockSize = blockSize / S->M; /* Loop counters */ + +#if defined (RISCV_MATH_LOOPUNROLL) + q31_t *px1, *px2, *px3; + q31_t x1, x2, x3; + q63_t acc1, acc2, acc3; +#endif + + /* S->pState buffer contains previous frame (numTaps - 1) samples */ + /* pStateCur points to the location where the new input data should be written */ + pStateCur = S->pState + (numTaps - 1U); + +#if defined (RISCV_MATH_LOOPUNROLL) && !defined (RISCV_VECTOR) + + /* Loop unrolling: Compute 4 samples at a time */ + blkCnt = outBlockSize >> 2U; + + /* Samples loop unrolled by 4 */ + while (blkCnt > 0U) + { + /* Copy 4 * decimation factor number of new input samples into the state buffer */ + i = S->M * 4; + + do + { + *pStateCur++ = *pSrc++; + + } while (--i); + + /* Set accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Initialize state pointer for all the samples */ + px0 = pState; + px1 = pState + S->M; + px2 = pState + 2 * S->M; + px3 = pState + 3 * S->M; + + /* Initialize coeff pointer */ + pb = pCoeffs; + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Read the b[numTaps-1] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-1] sample for acc0 */ + x0 = *(px0++); + /* Read x[n-numTaps-1] sample for acc1 */ + x1 = *(px1++); + /* Read x[n-numTaps-1] sample for acc2 */ + x2 = *(px2++); + /* Read x[n-numTaps-1] sample for acc3 */ + x3 = *(px3++); + + /* Perform the multiply-accumulate */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32); + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32); + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32); + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32); + + /* Read the b[numTaps-2] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-2] sample for acc0, acc1, acc2, acc3 */ + x0 = *(px0++); + x1 = *(px1++); + x2 = *(px2++); + x3 = *(px3++); + + /* Perform the multiply-accumulate */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32); + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32); + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32); + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32); + + /* Read the b[numTaps-3] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-3] sample acc0, acc1, acc2, acc3 */ + x0 = *(px0++); + x1 = *(px1++); + x2 = *(px2++); + x3 = *(px3++); + + /* Perform the multiply-accumulate */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32); + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32); + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32); + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32); + + /* Read the b[numTaps-4] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-4] sample acc0, acc1, acc2, acc3 */ + x0 = *(px0++); + x1 = *(px1++); + x2 = *(px2++); + x3 = *(px3++); + + /* Perform the multiply-accumulate */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32); + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32); + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32); + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *(pb++); + + /* Fetch state variables for acc0, acc1, acc2, acc3 */ + x0 = *(px0++); + x1 = *(px1++); + x2 = *(px2++); + x3 = *(px3++); + + /* Perform the multiply-accumulate */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32); + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32); + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32); + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + S->M * 4; +// #if __RISCV_XLEN == 64 +// write_q31x2_ia ((q31_t **) &pDst,__RV_PKBB32((q31_t) (acc0<<1),(q31_t) (acc1<<1))); +// write_q31x2_ia ((q31_t **) &pDst,__RV_PKBB32((q31_t) (acc2<<1),(q31_t) (acc3<<1))); +// #else + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst++ = (q31_t) (acc0 << 1); + *pDst++ = (q31_t) (acc1 << 1); + *pDst++ = (q31_t) (acc2 << 1); + *pDst++ = (q31_t) (acc3 << 1); +// #endif /* __RISCV_XLEN == 64 */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining samples */ + blkCnt = outBlockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = outBlockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Copy decimation factor number of new input samples into the state buffer */ + i = S->M; +#if defined (RISCV_VECTOR) + uint32_t blkCnti = S->M; /* Loop counter */ + size_t l; + + for (; (l = vsetvl_e32m8(blkCnti)) > 0; blkCnti -= l) { + vse32_v_i32m8 (pStateCur, vle32_v_i32m8(pSrc, l), l); + pSrc += l; + pStateCur += l; + } +#else + do + { + *pStateCur++ = *pSrc++; + + } while (--i); +#endif /*defined (RISCV_VECTOR)*/ + /* Set accumulator to zero */ + acc0 = 0; + + /* Initialize state pointer */ + px0 = pState; + + /* Initialize coeff pointer */ + pb = pCoeffs; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Read the b[numTaps-1] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-1] sample */ + x0 = *px0++; + + /* Perform the multiply-accumulate */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32); + + /* Read the b[numTaps-2] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-2] sample */ + x0 = *px0++; + + /* Perform the multiply-accumulate */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32); + + /* Read the b[numTaps-3] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-3] sample */ + x0 = *px0++; + + /* Perform the multiply-accumulate */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32); + + /* Read the b[numTaps-4] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-4] sample */ + x0 = *px0++; + + /* Perform the multiply-accumulate */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = numTaps; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *pb++; + + /* Fetch 1 state variable */ + x0 = *px0++; + + /* Perform the multiply-accumulate */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + S->M; + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst++ = (q31_t) (acc0 << 1); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the satrt of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCur = S->pState; + +#if defined (RISCV_MATH_LOOPUNROLL) && !defined (RISCV_VECTOR) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = (numTaps - 1U) >> 2U; + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = (numTaps - 1U) % 0x04U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = (numTaps - 1U); + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ +#if defined (RISCV_VECTOR) + uint32_t blkCnti =tapCnt; /* Loop counter */ + size_t l; + + for (; (l = vsetvl_e32m8(blkCnti)) > 0; blkCnti -= l) { + vse32_v_i32m8 (pStateCur, vle32_v_i32m8(pState, l), l); + pState += l; + pStateCur += l; + } +#else + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } +#endif /*defined (RISCV_VECTOR)*/ +} + +/** + @} end of FIR_decimate group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_decimate_init_f32.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_decimate_init_f32.c new file mode 100644 index 00000000..3cc29087 --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_decimate_init_f32.c @@ -0,0 +1,106 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_fir_decimate_init_f32.c + * Description: Floating-point FIR Decimator initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_decimate + @{ + */ + +/** + @brief Initialization function for the floating-point FIR decimator. + @param[in,out] S points to an instance of the floating-point FIR decimator structure + @param[in] numTaps number of coefficients in the filter + @param[in] M decimation factor + @param[in] pCoeffs points to the filter coefficients + @param[in] pState points to the state buffer + @param[in] blockSize number of input samples to process per call + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_LENGTH_ERROR : blockSize is not a multiple of M + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: + 
+      {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ @par + pState points to the array of state variables. + pState is of length numTaps+blockSize-1 words where blockSize is the number of input samples passed to riscv_fir_decimate_f32(). + M is the decimation factor. + */ + +riscv_status riscv_fir_decimate_init_f32( + riscv_fir_decimate_instance_f32 * S, + uint16_t numTaps, + uint8_t M, + const float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize) +{ + riscv_status status; + + /* The size of the input block must be a multiple of the decimation factor */ + if ((blockSize % M) != 0U) + { + /* Set status as RISCV_MATH_LENGTH_ERROR */ + status = RISCV_MATH_LENGTH_ERROR; + } + else + { + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear the state buffer. The size is always (blockSize + numTaps - 1) */ + memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(float32_t)); + + /* Assign state pointer */ + S->pState = pState; + + /* Assign Decimation Factor */ + S->M = M; + + status = RISCV_MATH_SUCCESS; + } + + return (status); + +} + +/** + @} end of FIR_decimate group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_decimate_init_q15.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_decimate_init_q15.c new file mode 100644 index 00000000..cf7f9b44 --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_decimate_init_q15.c @@ -0,0 +1,107 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_fir_decimate_init_q15.c + * Description: Initialization function for the Q15 FIR Decimator + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_decimate + @{ + */ + +/** + @brief Initialization function for the Q15 FIR decimator. + @param[in,out] S points to an instance of the Q15 FIR decimator structure + @param[in] numTaps number of coefficients in the filter + @param[in] M decimation factor + @param[in] pCoeffs points to the filter coefficients + @param[in] pState points to the state buffer + @param[in] blockSize number of input samples to process + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_LENGTH_ERROR : blockSize is not a multiple of M + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: + 
+      {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ @par + pState points to the array of state variables. + pState is of length numTaps+blockSize-1 words where blockSize is the number of input samples + to the call riscv_fir_decimate_q15(). + M is the decimation factor. + */ + +riscv_status riscv_fir_decimate_init_q15( + riscv_fir_decimate_instance_q15 * S, + uint16_t numTaps, + uint8_t M, + const q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize) +{ + riscv_status status; + + /* The size of the input block must be a multiple of the decimation factor */ + if ((blockSize % M) != 0U) + { + /* Set status as RISCV_MATH_LENGTH_ERROR */ + status = RISCV_MATH_LENGTH_ERROR; + } + else + { + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear the state buffer. The size is always (blockSize + numTaps - 1) */ + memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(q15_t)); + + /* Assign state pointer */ + S->pState = pState; + + /* Assign Decimation Factor */ + S->M = M; + + status = RISCV_MATH_SUCCESS; + } + + return (status); + +} + +/** + @} end of FIR_decimate group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_decimate_init_q31.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_decimate_init_q31.c new file mode 100644 index 00000000..d3700f9b --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_decimate_init_q31.c @@ -0,0 +1,106 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_fir_decimate_init_q31.c + * Description: Initialization function for Q31 FIR Decimation filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_decimate + @{ + */ + +/** + @brief Initialization function for the Q31 FIR decimator. + @param[in,out] S points to an instance of the Q31 FIR decimator structure + @param[in] numTaps number of coefficients in the filter + @param[in] M decimation factor + @param[in] pCoeffs points to the filter coefficients + @param[in] pState points to the state buffer + @param[in] blockSize number of input samples to process + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_LENGTH_ERROR : blockSize is not a multiple of M + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: + 
+      {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ @par + pState points to the array of state variables. + pState is of length numTaps+blockSize-1 words where blockSize is the number of input samples passed to riscv_fir_decimate_q31(). + M is the decimation factor. + */ + +riscv_status riscv_fir_decimate_init_q31( + riscv_fir_decimate_instance_q31 * S, + uint16_t numTaps, + uint8_t M, + const q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize) +{ + riscv_status status; + + /* The size of the input block must be a multiple of the decimation factor */ + if ((blockSize % M) != 0U) + { + /* Set status as RISCV_MATH_LENGTH_ERROR */ + status = RISCV_MATH_LENGTH_ERROR; + } + else + { + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear the state buffer. The size is always (blockSize + numTaps - 1) */ + memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(q31_t)); + + /* Assign state pointer */ + S->pState = pState; + + /* Assign Decimation Factor */ + S->M = M; + + status = RISCV_MATH_SUCCESS; + } + + return (status); + +} + +/** + @} end of FIR_decimate group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_decimate_q15.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_decimate_q15.c new file mode 100644 index 00000000..426be065 --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_decimate_q15.c @@ -0,0 +1,669 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_fir_decimate_q15.c + * Description: Q15 FIR Decimator + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_decimate + @{ + */ + +/** + @brief Processing function for the Q15 FIR decimator. + @param[in] S points to an instance of the Q15 FIR decimator structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of input samples to process per call + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + Lastly, the accumulator is saturated to yield a result in 1.15 format. + + @remark + Refer to \ref riscv_fir_decimate_fast_q15() for a faster but less precise implementation of this function. + */ + +#if defined (RISCV_MATH_DSP) && !defined (RISCV_VECTOR) + +void riscv_fir_decimate_q15( + const riscv_fir_decimate_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCur; /* Points to the current sample of the state */ + q15_t *px; /* Temporary pointer for state buffer */ + const q15_t *pb; /* Temporary pointer for coefficient buffer */ + q31_t x0, x1, c0; /* Temporary variables to hold state and coefficient values */ + q63_t sum0; /* Accumulators */ + q63_t acc0, acc1; + q15_t *px0, *px1; + uint32_t blkCntN3; + uint32_t numTaps = S->numTaps; /* Number of taps */ + uint32_t i, blkCnt, tapCnt, outBlockSize = blockSize / S->M; /* Loop counters */ + +#if defined (RISCV_MATH_LOOPUNROLL) + q31_t c1; /* Temporary variables to hold state and coefficient values */ +#if __RISCV_XLEN == 64 + q63_t x064, x164, c064; +#endif /* __RISCV_XLEN == 64 */ +#endif + + /* S->pState buffer contains previous frame (numTaps - 1) samples */ + /* pStateCur points to the location where the new input data should be written */ + pStateCur = S->pState + (numTaps - 1U); + + /* Total number of output samples to be computed */ + blkCnt = outBlockSize / 2; + blkCntN3 = outBlockSize - (2 * blkCnt); + + while (blkCnt > 0U) + { + /* Copy 2 * decimation factor number of new input samples into the state buffer */ + i = S->M * 2; + + do + { + *pStateCur++ = *pSrc++; + + } while (--i); + + /* Set accumulator to zero */ + acc0 = 0; + acc1 = 0; + + /* Initialize state pointer for all the samples */ + px0 = pState; + px1 = pState + S->M; + + /* Initialize coeff pointer */ + pb = pCoeffs; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { +#if __RISCV_XLEN == 64 + /* Read the b[numTaps-1] and b[numTaps-2] coefficients */ + c064 = read_q15x4_ia ((q15_t **) &pb); + + /* Read x[n-numTaps-1] and x[n-numTaps-2]sample */ + x064 = read_q15x4_ia ((q15_t **) &px0); + x164 = read_q15x4_ia ((q15_t **) &px1); + + acc0 = __RV_SMALDA(acc0, x064, c064); + acc1 = __RV_SMALDA(acc1, x164, c064); + +#else + /* Read the b[numTaps-1] and b[numTaps-2] coefficients */ + c0 = read_q15x2_ia ((q15_t **) &pb); + + /* Read x[n-numTaps-1] and x[n-numTaps-2]sample */ + x0 = read_q15x2_ia (&px0); + x1 = read_q15x2_ia (&px1); + + /* Perform the multiply-accumulate */ + acc0 = __RV_SMALDA(acc0, x0, c0); + acc1 = __RV_SMALDA(acc1, x1, c0); + + /* Read the b[numTaps-3] and b[numTaps-4] coefficient */ + c0 = read_q15x2_ia ((q15_t **) &pb); + + /* Read x[n-numTaps-2] and x[n-numTaps-3] sample */ + x0 = read_q15x2_ia (&px0); + x1 = read_q15x2_ia (&px1); + + /* Perform the multiply-accumulate */ + acc0 = __RV_SMALDA(acc0, x0, c0); + acc1 = __RV_SMALDA(acc1, x1, c0); +#endif /* __RISCV_XLEN == 64 */ + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = numTaps; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *pb++; + + /* Fetch state variables for acc0, acc1 */ + x0 = *px0++; + x1 = *px1++; + + /* Perform the multiply-accumulate */ + acc0 = __SMLALD(x0, c0, acc0); + acc1 = __SMLALD(x1, c0, acc1); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + S->M * 2; + + /* Store filter output, smlad returns the values in 2.14 format */ + /* so downsacle by 15 to get output in 1.15 */ + *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16)); + *pDst++ = (q15_t) (__SSAT((acc1 >> 15), 16)); + + /* Decrement loop counter */ + blkCnt--; + } + + while (blkCntN3 > 0U) + { + /* Copy decimation factor number of new input samples into the state buffer */ + i = S->M; + + do + { + *pStateCur++ = *pSrc++; + + } while (--i); + + /* Set accumulator to zero */ + sum0 = 0; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coeff pointer */ + pb = pCoeffs; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Read the b[numTaps-1] and b[numTaps-2] coefficients */ + c0 = read_q15x2_ia ((q15_t **) &pb); + + /* Read x[n-numTaps-1] and x[n-numTaps-2] sample */ + x0 = read_q15x2_ia (&px); + + /* Read the b[numTaps-3] and b[numTaps-4] coefficients */ + c1 = read_q15x2_ia ((q15_t **) &pb); + + /* Perform the multiply-accumulate */ + sum0 = __SMLALD(x0, c0, sum0); + + /* Read x[n-numTaps-2] and x[n-numTaps-3] sample */ + x0 = read_q15x2_ia (&px); + + /* Perform the multiply-accumulate */ + sum0 = __SMLALD(x0, c1, sum0); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = numTaps; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *pb++; + + /* Fetch 1 state variable */ + x0 = *px++; + + /* Perform the multiply-accumulate */ + sum0 = __SMLALD(x0, c0, sum0); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + S->M; + + /* Store filter output, smlad returns the values in 2.14 format */ + /* so downsacle by 15 to get output in 1.15 */ + *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16)); + + /* Decrement loop counter */ + blkCntN3--; + } + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the satrt of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCur = S->pState; + i = (numTaps - 1U) >> 2U; + + /* copy data */ + while (i > 0U) + { + write_q15x2_ia (&pStateCur, read_q15x2_ia (&pState)); + write_q15x2_ia (&pStateCur, read_q15x2_ia (&pState)); + + /* Decrement loop counter */ + i--; + } + + i = (numTaps - 1U) % 0x04U; + + /* Copy data */ + while (i > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + i--; + } + +} + +#else /* #if defined (RISCV_MATH_DSP) */ + +void riscv_fir_decimate_q15( + const riscv_fir_decimate_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCur; /* Points to the current sample of the state */ + q15_t *px; /* Temporary pointer for state buffer */ + const q15_t *pb; /* Temporary pointer for coefficient buffer */ + q15_t x0, x1, c0; /* Temporary variables to hold state and coefficient values */ + q63_t sum0; /* Accumulators */ + q63_t acc0, acc1; + q15_t *px0, *px1; + uint32_t blkCntN3; + uint32_t numTaps = S->numTaps; /* Number of taps */ + uint32_t i, blkCnt, tapCnt, outBlockSize = blockSize / S->M; /* Loop counters */ + + + /* S->pState buffer contains previous frame (numTaps - 1) samples */ + /* pStateCur points to the location where the new input data should be written */ + pStateCur = S->pState + (numTaps - 1U); + + /* Total number of output samples to be computed */ + blkCnt = outBlockSize / 2; + blkCntN3 = outBlockSize - (2 * blkCnt); + + while (blkCnt > 0U) + { +#if defined (RISCV_VECTOR) + uint32_t blkCnti = S->M * 2; /* Loop counter */ + size_t l; + + for (; (l = vsetvl_e32m8(blkCnti)) > 0; blkCnti -= l) { + vse32_v_i32m8 (pStateCur, vle32_v_i32m8(pSrc, l), l); + pSrc += l; + pStateCur += l; + } +#else + /* Copy 2 * decimation factor number of new input samples into the state buffer */ + i = S->M * 2; + + do + { + *pStateCur++ = *pSrc++; + + } while (--i); +#endif /*defined (RISCV_VECTOR)*/ + /* Set accumulator to zero */ + acc0 = 0; + acc1 = 0; + + /* Initialize state pointer */ + px0 = pState; + px1 = pState + S->M; + + /* Initialize coeff pointer */ + pb = pCoeffs; + +#if defined (RISCV_MATH_LOOPUNROLL) && !defined (RISCV_VECTOR) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Read the Read b[numTaps-1] coefficients */ + c0 = *pb++; + + /* Read x[n-numTaps-1] for sample 0 and for sample 1 */ + x0 = *px0++; + x1 = *px1++; + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + + /* Read the b[numTaps-2] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-2] for sample 0 and sample 1 */ + x0 = *px0++; + x1 = *px1++; + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + + /* Read the b[numTaps-3] coefficients */ + c0 = *pb++; + + /* Read x[n-numTaps-3] for sample 0 and sample 1 */ + x0 = *px0++; + x1 = *px1++; + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-4] for sample 0 and sample 1 */ + x0 = *px0++; + x1 = *px1++; + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = numTaps; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ +#if defined (RISCV_VECTOR) + uint32_t blkCntb; + // size_t l; + vint16m2_t va1m2,vb1m2,vb2m2; + vint32m4_t vch00m4,vch01m4; + vint64m1_t vch00m1,vch01m1; + vint64m1_t vtemp00m1,vtemp01m1; + vint64m8_t vach00m8,vach01m8; + blkCntb = numTaps; /* Loop counter */ + // q7_t temp[] = {0}; + l = vsetvl_e16m2(blkCntb); + //initial array to zero + vach00m8 = vmv_v_x_i64m8(0, l); + vach01m8 = vmv_v_x_i64m8(0, l); + l = vsetvl_e64m1(1); + vtemp00m1 = vmv_v_x_i64m1(0, l); + vtemp01m1 = vmv_v_x_i64m1(0, l); + for (; (l = vsetvl_e16m2(blkCntb)) > 0; blkCntb -= l) { + va1m2 = vle16_v_i16m2(pb , l); + vb1m2 = vle16_v_i16m2(px0, l); + vb2m2 = vle16_v_i16m2(px1, l); + pb += l; + px0 += l; + px1 += l; + vch00m4 = vwmul_vv_i32m4(va1m2, vb1m2, l); + vch01m4 = vwmul_vv_i32m4(va1m2, vb2m2, l); + vach00m8 = vwadd_wv_i64m8(vach00m8, vch00m4, l); + vach01m8 = vwadd_wv_i64m8(vach01m8, vch01m4, l); + } + //Here we calculate sum of four vector + //set vl to max vl + l = vsetvl_e16m2(numTaps); + //calculate sum + vch00m1 = vredsum_vs_i64m8_i64m1(vtemp00m1, vach00m8, vtemp00m1, l); + vch01m1 = vredsum_vs_i64m8_i64m1(vtemp01m1, vach01m8, vtemp01m1, l); + //set vl to 1 + l = vsetvl_e64m1(1); + //wrfte result scalar back + acc0 += (q63_t)vmv_x_s_i64m1_i64(vch00m1); + acc1 += (q63_t)vmv_x_s_i64m1_i64(vch01m1); +#else + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *pb++; + + /* Fetch 1 state variable */ + x0 = *px0++; + x1 = *px1++; + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + + /* Decrement the loop counter */ + tapCnt--; + } +#endif /*defined (RISCV_VECTOR)*/ + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + S->M * 2; + + /* Store filter output, smlad returns the values in 2.14 format */ + /* so downsacle by 15 to get output in 1.15 */ + + *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16)); + *pDst++ = (q15_t) (__SSAT((acc1 >> 15), 16)); + + /* Decrement loop counter */ + blkCnt--; + } + + while (blkCntN3 > 0U) + { + /* Copy decimation factor number of new input samples into the state buffer */ +#if defined (RISCV_VECTOR) + uint32_t blkCnti = S->M * 2; /* Loop counter */ + size_t l; + + for (; (l = vsetvl_e32m8(blkCnti)) > 0; blkCnti -= l) { + vse32_v_i32m8 (pStateCur, vle32_v_i32m8(pSrc, l), l); + pSrc += l; + pStateCur += l; + } +#else + i = S->M; + do + { + *pStateCur++ = *pSrc++; + + } while (--i); +#endif /*defined (RISCV_VECTOR)*/ + /* Set accumulator to zero */ + sum0 = 0; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coeff pointer */ + pb = pCoeffs; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Read the b[numTaps-1] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-1] sample */ + x0 = *px++; + + /* Perform the multiply-accumulate */ + sum0 += x0 * c0; + + /* Read the b[numTaps-2] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-2] sample */ + x0 = *px++; + + /* Perform the multiply-accumulate */ + sum0 += x0 * c0; + + /* Read the b[numTaps-3] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-3] sample */ + x0 = *px++; + + /* Perform the multiply-accumulate */ + sum0 += x0 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-4] sample */ + x0 = *px++; + + /* Perform the multiply-accumulate */ + sum0 += x0 * c0; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = numTaps; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *pb++; + + /* Fetch 1 state variable */ + x0 = *px++; + + /* Perform the multiply-accumulate */ + sum0 += x0 * c0; + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + S->M; + + /* Store filter output, smlad returns the values in 2.14 format */ + /* so downsacle by 15 to get output in 1.15 */ + *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16)); + + /* Decrement loop counter */ + blkCntN3--; + } + + /* Processing is complete. + ** Now copy the last numTaps - 1 samples to the satrt of the state buffer. + ** This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCur = S->pState; + + i = (numTaps - 1U) >> 2U; + + /* copy data */ + while (i > 0U) + { + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + i--; + } + + i = (numTaps - 1U) % 0x04U; + + /* copy data */ + while (i > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + i--; + } +} + +#endif /* #if defined (RISCV_MATH_DSP) */ +/** + @} end of FIR_decimate group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_decimate_q31.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_decimate_q31.c new file mode 100644 index 00000000..ebac33b5 --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_decimate_q31.c @@ -0,0 +1,472 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_fir_decimate_q31.c + * Description: Q31 FIR Decimator + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_decimate + @{ + */ + +/** + @brief Processing function for the Q31 FIR decimator. + @param[in] S points to an instance of the Q31 FIR decimator structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + Thus, if the accumulator result overflows it wraps around rather than clip. + In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits (where log2 is read as log to the base 2). + After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + + @remark + Refer to \ref riscv_fir_decimate_fast_q31() for a faster but less precise implementation of this function. + */ + +void riscv_fir_decimate_q31( + const riscv_fir_decimate_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + q31_t *pState = S->pState; /* State pointer */ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *pStateCur; /* Points to the current sample of the state */ + q31_t *px0; /* Temporary pointer for state buffer */ + const q31_t *pb; /* Temporary pointer for coefficient buffer */ + q31_t x0, c0; /* Temporary variables to hold state and coefficient values */ + q63_t acc0; /* Accumulator */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i, tapCnt, blkCnt, outBlockSize = blockSize / S->M; /* Loop counters */ + +#if defined (RISCV_MATH_LOOPUNROLL) + q31_t *px1, *px2, *px3; + q31_t x1, x2, x3; + q63_t acc1, acc2, acc3; +#if __RISCV_XLEN == 64 + q63_t x064, c064, x164, x264, x364; +#endif /* __RISCV_XLEN == 64 */ +#endif + + /* S->pState buffer contains previous frame (numTaps - 1) samples */ + /* pStateCur points to the location where the new input data should be written */ + pStateCur = S->pState + (numTaps - 1U); + +#if defined (RISCV_MATH_LOOPUNROLL) && !defined (RISCV_VECTOR) + + /* Loop unrolling: Compute 4 samples at a time */ + blkCnt = outBlockSize >> 2U; + + /* Samples loop unrolled by 4 */ + while (blkCnt > 0U) + { + /* Copy 4 * decimation factor number of new input samples into the state buffer */ + i = S->M * 4; + + do + { + *pStateCur++ = *pSrc++; + + } while (--i); + + /* Set accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Initialize state pointer for all the samples */ + px0 = pState; + px1 = pState + S->M; + px2 = pState + 2 * S->M; + px3 = pState + 3 * S->M; + + /* Initialize coeff pointer */ + pb = pCoeffs; + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { +#if __RISCV_XLEN == 64 + c064 = read_q31x2_ia((q31_t **)&pb); + x064 = read_q31x2_ia((q31_t **)&px0); + x164 = read_q31x2_ia((q31_t **)&px1); + x264 = read_q31x2_ia((q31_t **)&px2); + x364 = read_q31x2_ia((q31_t **)&px3); + + acc0 = __RV_KMADA32(acc0, x064, c064); + acc1 = __RV_KMADA32(acc1, x164, c064); + acc2 = __RV_KMADA32(acc2, x264, c064); + acc3 = __RV_KMADA32(acc3, x364, c064); + + c064 = read_q31x2_ia((q31_t **)&pb); + x064 = read_q31x2_ia((q31_t **)&px0); + x164 = read_q31x2_ia((q31_t **)&px1); + x264 = read_q31x2_ia((q31_t **)&px2); + x364 = read_q31x2_ia((q31_t **)&px3); + + acc0 = __RV_KMADA32(acc0, x064, c064); + acc1 = __RV_KMADA32(acc1, x164, c064); + acc2 = __RV_KMADA32(acc2, x264, c064); + acc3 = __RV_KMADA32(acc3, x364, c064); + +#else + /* Read the b[numTaps-1] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-1] sample for acc0 */ + x0 = *(px0++); + /* Read x[n-numTaps-1] sample for acc1 */ + x1 = *(px1++); + /* Read x[n-numTaps-1] sample for acc2 */ + x2 = *(px2++); + /* Read x[n-numTaps-1] sample for acc3 */ + x3 = *(px3++); + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x0 * c0; + acc1 += (q63_t) x1 * c0; + acc2 += (q63_t) x2 * c0; + acc3 += (q63_t) x3 * c0; + + /* Read the b[numTaps-2] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-2] sample for acc0, acc1, acc2, acc3 */ + x0 = *(px0++); + x1 = *(px1++); + x2 = *(px2++); + x3 = *(px3++); + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x0 * c0; + acc1 += (q63_t) x1 * c0; + acc2 += (q63_t) x2 * c0; + acc3 += (q63_t) x3 * c0; + + /* Read the b[numTaps-3] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-3] sample acc0, acc1, acc2, acc3 */ + x0 = *(px0++); + x1 = *(px1++); + x2 = *(px2++); + x3 = *(px3++); + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x0 * c0; + acc1 += (q63_t) x1 * c0; + acc2 += (q63_t) x2 * c0; + acc3 += (q63_t) x3 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-4] sample acc0, acc1, acc2, acc3 */ + x0 = *(px0++); + x1 = *(px1++); + x2 = *(px2++); + x3 = *(px3++); + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x0 * c0; + acc1 += (q63_t) x1 * c0; + acc2 += (q63_t) x2 * c0; + acc3 += (q63_t) x3 * c0; +#endif /* __RISCV_XLEN == 64 */ + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *(pb++); + + /* Fetch state variables for acc0, acc1, acc2, acc3 */ + x0 = *(px0++); + x1 = *(px1++); + x2 = *(px2++); + x3 = *(px3++); + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x0 * c0; + acc1 += (q63_t) x1 * c0; + acc2 += (q63_t) x2 * c0; + acc3 += (q63_t) x3 * c0; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + S->M * 4; + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst++ = (q31_t) (acc0 >> 31); + *pDst++ = (q31_t) (acc1 >> 31); + *pDst++ = (q31_t) (acc2 >> 31); + *pDst++ = (q31_t) (acc3 >> 31); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining samples */ + blkCnt = outBlockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = outBlockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { +//It turns out if add these part, it will take more cycles +#if defined (RISCV_VECTOR) + uint32_t blkCnti = S->M; /* Loop counter */ + size_t l; + + for (; (l = vsetvl_e32m8(blkCnti)) > 0; blkCnti -= l) { + vse32_v_i32m8 (pStateCur, vle32_v_i32m8(pSrc, l), l); + pSrc += l; + pStateCur += l; + } +#else + /* Copy decimation factor number of new input samples into the state buffer */ + i = S->M; + + do + { + *pStateCur++ = *pSrc++; + + } while (--i); +#endif /*defined (RISCV_VECTOR)*/ + /* Set accumulator to zero */ + acc0 = 0; + + /* Initialize state pointer */ + px0 = pState; + + /* Initialize coeff pointer */ + pb = pCoeffs; + +#if defined (RISCV_MATH_LOOPUNROLL) && !defined (RISCV_VECTOR) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Read the b[numTaps-1] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-1] sample */ + x0 = *px0++; + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x0 * c0; + + /* Read the b[numTaps-2] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-2] sample */ + x0 = *px0++; + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x0 * c0; + + /* Read the b[numTaps-3] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-3] sample */ + x0 = *px0++; + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x0 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-4] sample */ + x0 = *px0++; + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x0 * c0; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = numTaps; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ +#if defined (RISCV_VECTOR) + uint32_t blkCntb; + // size_t l; + vint32m4_t va1m4,va2m4; + vint64m8_t vch00m8; + vint64m1_t vch00m1; + vint64m1_t vtemp00m1; + vint64m8_t vach00m8; + blkCntb = numTaps; /* Loop counter */ + // q7_t temp[] = {0}; + l = vsetvl_e32m4(blkCntb); + //initial array to zero + vach00m8 = vmv_v_x_i64m8(0, l); + l = vsetvl_e64m4(1); + vtemp00m1 = vmv_v_x_i64m1(0, l); + for (; (l = vsetvl_e32m4(blkCntb)) > 0; blkCntb -= l) { + va1m4 = vle32_v_i32m4(pb, l); + va2m4 = vle32_v_i32m4(px0, l); + pb += l; + px0 += l; + vch00m8 = vwmul_vv_i64m8(va1m4, va2m4, l); + vach00m8 = vadd_vv_i64m8(vach00m8, vch00m8, l); + } + //Here we calculate sum of four vector + //set vl to max vl + l = vsetvl_e32m4(numTaps); + //calculate sum + vch00m1 = vredsum_vs_i64m8_i64m1(vtemp00m1, vach00m8, vtemp00m1, l); + //set vl to 1 + l = vsetvl_e64m1(1); + //wrfte result scalar back + acc0 += (q63_t)vmv_x_s_i64m1_i64(vch00m1); +#else + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *pb++; + + /* Fetch 1 state variable */ + x0 = *px0++; + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x0 * c0; + + /* Decrement loop counter */ + tapCnt--; + } +#endif /*defined (RISCV_VECTOR)*/ + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + S->M; + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst++ = (q31_t) (acc0 >> 31); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the satrt of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCur = S->pState; + +#if defined (RISCV_MATH_LOOPUNROLL) && !defined (RISCV_VECTOR) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = (numTaps - 1U) >> 2U; + + /* Copy data */ + while (tapCnt > 0U) + { +#if __RISCV_XLEN == 64 + write_q31x2_ia((q31_t **)&pStateCur,read_q31x2_ia((q31_t **)&pState)); + write_q31x2_ia((q31_t **)&pStateCur,read_q31x2_ia((q31_t **)&pState)); +#else + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; +#endif /* __RISCV_XLEN == 64 */ + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = (numTaps - 1U) % 0x04U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = (numTaps - 1U); + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ +#if defined (RISCV_VECTOR) + uint32_t blkCnti = tapCnt; /* Loop counter */ + size_t l; + + for (; (l = vsetvl_e32m8(blkCnti)) > 0; blkCnti -= l) { + vse32_v_i32m8 (pStateCur, vle32_v_i32m8(pState, l), l); + pState += l; + pStateCur += l; + } +#else + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } +#endif /*defined (RISCV_VECTOR)*/ +} +/** + @} end of FIR_decimate group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_f16.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_f16.c new file mode 100644 index 00000000..f7b21ea3 --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_f16.c @@ -0,0 +1,428 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_fir_f16.c + * Description: Floating-point FIR filter processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions_f16.h" + +#if defined(RISCV_FLOAT16_SUPPORTED) +/** + @ingroup groupFilters + */ + + +/** + @addtogroup FIR + @{ + */ + +/** + @brief Processing function for floating-point FIR filter. + @param[in] S points to an instance of the floating-point FIR filter structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + */ + + +void riscv_fir_f16( + const riscv_fir_instance_f16 * S, + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize) +{ + float16_t *pState = S->pState; /* State pointer */ + const float16_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float16_t *pStateCurnt; /* Points to the current sample of the state */ + float16_t *px; /* Temporary pointer for state buffer */ + const float16_t *pb; /* Temporary pointer for coefficient buffer */ + _Float16 acc0; /* Accumulator */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i, tapCnt, blkCnt; /* Loop counters */ + +#if defined (RISCV_MATH_LOOPUNROLL) + _Float16 acc1, acc2, acc3, acc4, acc5, acc6, acc7; /* Accumulators */ + _Float16 x0, x1, x2, x3, x4, x5, x6, x7; /* Temporary variables to hold state values */ + _Float16 c0; /* Temporary variable to hold coefficient value */ +#endif + + /* S->pState points to state array which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 8 output values simultaneously. + * The variables acc0 ... acc7 hold output values that are being computed: + * + * acc0 = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] + * acc1 = b[numTaps-1] * x[n-numTaps] + b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1] + * acc2 = b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] + b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2] + * acc3 = b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps] +...+ b[0] * x[3] + */ + + blkCnt = blockSize >> 3U; + + while (blkCnt > 0U) + { + /* Copy 4 new input samples into the state buffer. */ + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + + /* Set all accumulators to zero */ + acc0 = 0.0f; + acc1 = 0.0f; + acc2 = 0.0f; + acc3 = 0.0f; + acc4 = 0.0f; + acc5 = 0.0f; + acc6 = 0.0f; + acc7 = 0.0f; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + + /* This is separated from the others to avoid + * a call to __aeabi_memmove which would be slower + */ + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + + /* Read the first 7 samples from the state buffer: x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2] */ + x0 = *px++; + x1 = *px++; + x2 = *px++; + x3 = *px++; + x4 = *px++; + x5 = *px++; + x6 = *px++; + + /* Loop unrolling: process 8 taps at a time. */ + tapCnt = numTaps >> 3U; + + while (tapCnt > 0U) + { + /* Read the b[numTaps-1] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-3] sample */ + x7 = *(px++); + + /* acc0 += b[numTaps-1] * x[n-numTaps] */ + acc0 += x0 * c0; + + /* acc1 += b[numTaps-1] * x[n-numTaps-1] */ + acc1 += x1 * c0; + + /* acc2 += b[numTaps-1] * x[n-numTaps-2] */ + acc2 += x2 * c0; + + /* acc3 += b[numTaps-1] * x[n-numTaps-3] */ + acc3 += x3 * c0; + + /* acc4 += b[numTaps-1] * x[n-numTaps-4] */ + acc4 += x4 * c0; + + /* acc1 += b[numTaps-1] * x[n-numTaps-5] */ + acc5 += x5 * c0; + + /* acc2 += b[numTaps-1] * x[n-numTaps-6] */ + acc6 += x6 * c0; + + /* acc3 += b[numTaps-1] * x[n-numTaps-7] */ + acc7 += x7 * c0; + + /* Read the b[numTaps-2] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-4] sample */ + x0 = *(px++); + + /* Perform the multiply-accumulate */ + acc0 += x1 * c0; + acc1 += x2 * c0; + acc2 += x3 * c0; + acc3 += x4 * c0; + acc4 += x5 * c0; + acc5 += x6 * c0; + acc6 += x7 * c0; + acc7 += x0 * c0; + + /* Read the b[numTaps-3] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-5] sample */ + x1 = *(px++); + + /* Perform the multiply-accumulates */ + acc0 += x2 * c0; + acc1 += x3 * c0; + acc2 += x4 * c0; + acc3 += x5 * c0; + acc4 += x6 * c0; + acc5 += x7 * c0; + acc6 += x0 * c0; + acc7 += x1 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-6] sample */ + x2 = *(px++); + + /* Perform the multiply-accumulates */ + acc0 += x3 * c0; + acc1 += x4 * c0; + acc2 += x5 * c0; + acc3 += x6 * c0; + acc4 += x7 * c0; + acc5 += x0 * c0; + acc6 += x1 * c0; + acc7 += x2 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-6] sample */ + x3 = *(px++); + /* Perform the multiply-accumulates */ + acc0 += x4 * c0; + acc1 += x5 * c0; + acc2 += x6 * c0; + acc3 += x7 * c0; + acc4 += x0 * c0; + acc5 += x1 * c0; + acc6 += x2 * c0; + acc7 += x3 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-6] sample */ + x4 = *(px++); + + /* Perform the multiply-accumulates */ + acc0 += x5 * c0; + acc1 += x6 * c0; + acc2 += x7 * c0; + acc3 += x0 * c0; + acc4 += x1 * c0; + acc5 += x2 * c0; + acc6 += x3 * c0; + acc7 += x4 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-6] sample */ + x5 = *(px++); + + /* Perform the multiply-accumulates */ + acc0 += x6 * c0; + acc1 += x7 * c0; + acc2 += x0 * c0; + acc3 += x1 * c0; + acc4 += x2 * c0; + acc5 += x3 * c0; + acc6 += x4 * c0; + acc7 += x5 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-6] sample */ + x6 = *(px++); + + /* Perform the multiply-accumulates */ + acc0 += x7 * c0; + acc1 += x0 * c0; + acc2 += x1 * c0; + acc3 += x2 * c0; + acc4 += x3 * c0; + acc5 += x4 * c0; + acc6 += x5 * c0; + acc7 += x6 * c0; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + tapCnt = numTaps % 0x8U; + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *(pb++); + + /* Fetch 1 state variable */ + x7 = *(px++); + + /* Perform the multiply-accumulates */ + acc0 += x0 * c0; + acc1 += x1 * c0; + acc2 += x2 * c0; + acc3 += x3 * c0; + acc4 += x4 * c0; + acc5 += x5 * c0; + acc6 += x6 * c0; + acc7 += x7 * c0; + + /* Reuse the present sample states for next sample */ + x0 = x1; + x1 = x2; + x2 = x3; + x3 = x4; + x4 = x5; + x5 = x6; + x6 = x7; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Advance the state pointer by 8 to process the next group of 8 samples */ + pState = pState + 8; + + /* The results in the 8 accumulators, store in the destination buffer. */ + *pDst++ = acc0; + *pDst++ = acc1; + *pDst++ = acc2; + *pDst++ = acc3; + *pDst++ = acc4; + *pDst++ = acc5; + *pDst++ = acc6; + *pDst++ = acc7; + + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining output samples */ + blkCnt = blockSize % 0x8U; + +#else + + /* Initialize blkCnt with number of taps */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Copy one sample at a time into state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Set the accumulator to zero */ + acc0 = 0.0f; + + /* Initialize state pointer */ + px = pState; + + /* Initialize Coefficient pointer */ + pb = pCoeffs; + + i = numTaps; + + /* Perform the multiply-accumulates */ + while (i > 0U) + { + /* acc = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] */ + acc0 += *px++ * *pb++; + + i--; + } + + /* Store result in destination buffer. */ + *pDst++ = acc0; + + /* Advance state pointer by 1 for the next sample */ + pState = pState + 1U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the start of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = (numTaps - 1U) >> 2U; + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Calculate remaining number of copies */ + tapCnt = (numTaps - 1U) % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = (numTaps - 1U); + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + /* Copy remaining data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +} + +/** +* @} end of FIR group +*/ + +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_f32.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_f32.c new file mode 100644 index 00000000..1e13471b --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_f32.c @@ -0,0 +1,553 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_fir_f32.c + * Description: Floating-point FIR filter processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @defgroup FIR Finite Impulse Response (FIR) Filters + + This set of functions implements Finite Impulse Response (FIR) filters + for Q7, Q15, Q31, and floating-point data types. Fast versions of Q15 and Q31 are also provided. + The functions operate on blocks of input and output data and each call to the function processes + blockSize samples through the filter. pSrc and + pDst points to input and output arrays containing blockSize values. + + @par Algorithm + The FIR filter algorithm is based upon a sequence of multiply-accumulate (MAC) operations. + Each filter coefficient b[n] is multiplied by a state variable which equals a previous input sample x[n]. + 
+      y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]
+
+ @par + \image html FIR.png "Finite Impulse Response filter" + @par + pCoeffs points to a coefficient array of size numTaps. + Coefficients are stored in time reversed order. + @par + 
+      {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ @par + pState points to a state array of size numTaps + blockSize - 1. + Samples in the state buffer are stored in the following order. + @par + 
+      {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[n](==pSrc[0]), x[n+1](==pSrc[1]), ..., x[n+blockSize-1](==pSrc[blockSize-1])}
+
+ @par + Note that the length of the state buffer exceeds the length of the coefficient array by blockSize-1. + The increased state buffer length allows circular addressing, which is traditionally used in the FIR filters, + to be avoided and yields a significant speed improvement. + The state variables are updated after each block of data is processed; the coefficients are untouched. + + @par Instance Structure + The coefficients and state variables for a filter are stored together in an instance data structure. + A separate instance structure must be defined for each filter. + Coefficient arrays may be shared among several instances while state variable arrays cannot be shared. + There are separate instance structure declarations for each of the 4 supported data types. + + @par Initialization Functions + There is also an associated initialization function for each data type. + The initialization function performs the following operations: + - Sets the values of the internal structure fields. + - Zeros out the values in the state buffer. + To do this manually without calling the init function, assign the follow subfields of the instance structure: + numTaps, pCoeffs, pState. Also set all of the values in pState to zero. + @par + Use of the initialization function is optional. + However, if the initialization function is used, then the instance structure cannot be placed into a const data section. + To place an instance structure into a const data section, the instance structure must be manually initialized. + Set the values in the state buffer to zeros before static initialization. + The code below statically initializes each of the 4 different data type filter instance structures + 
+      riscv_fir_instance_f32 S = {numTaps, pState, pCoeffs};
+      riscv_fir_instance_q31 S = {numTaps, pState, pCoeffs};
+      riscv_fir_instance_q15 S = {numTaps, pState, pCoeffs};
+      riscv_fir_instance_q7 S =  {numTaps, pState, pCoeffs};
+
+ where numTaps is the number of filter coefficients in the filter; pState is the address of the state buffer; + pCoeffs is the address of the coefficient buffer. + @par Initialization of Helium version + For Helium version the array of coefficients must be padded with zero to contain + a full number of lanes. + + The array length L must be a multiple of x. L = x * a : + - x is 4 for f32 + - x is 4 for q31 + - x is 4 for f16 (so managed like the f32 version and not like the q15 one) + - x is 8 for q15 + - x is 16 for q7 + + The additional coefficients + (x * a - numTaps) must be set to 0. + numTaps is still set to its right value in the init function. It means that + the implementation may require to read more coefficients due to the vectorization and + to avoid having to manage too many different cases in the code. + + + @par Helium state buffer + The state buffer must contain some additional temporary data + used during the computation but which is not the state of the FIR. + The first A samples are temporary data. + The remaining samples are the state of the FIR filter. + @par + So the state buffer has size numTaps + A + blockSize - 1 : + - A is blockSize for f32 + - A is 8*ceil(blockSize/8) for f16 + - A is 8*ceil(blockSize/4) for q31 + - A is 0 for other datatypes (q15 and q7) + + + @par Fixed-Point Behavior + Care must be taken when using the fixed-point versions of the FIR filter functions. + In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + Refer to the function specific documentation below for usage guidelines. + + */ + +/** + @addtogroup FIR + @{ + */ + +/** + @brief Processing function for floating-point FIR filter. + @param[in] S points to an instance of the floating-point FIR filter structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + */ + +void riscv_fir_f32( + const riscv_fir_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *pStateCurnt; /* Points to the current sample of the state */ + float32_t *px; /* Temporary pointer for state buffer */ + const float32_t *pb; /* Temporary pointer for coefficient buffer */ + float32_t acc0; /* Accumulator */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i, tapCnt, blkCnt; /* Loop counters */ + +#if defined (RISCV_MATH_LOOPUNROLL) + float32_t acc1, acc2, acc3, acc4, acc5, acc6, acc7; /* Accumulators */ + float32_t x0, x1, x2, x3, x4, x5, x6, x7; /* Temporary variables to hold state values */ + float32_t c0; /* Temporary variable to hold coefficient value */ +#endif + + /* S->pState points to state array which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + +#if defined (RISCV_MATH_LOOPUNROLL) && !defined (RISCV_VECTOR) + + /* Loop unrolling: Compute 8 output values simultaneously. + * The variables acc0 ... acc7 hold output values that are being computed: + * + * acc0 = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] + * acc1 = b[numTaps-1] * x[n-numTaps] + b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1] + * acc2 = b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] + b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2] + * acc3 = b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps] +...+ b[0] * x[3] + */ + + blkCnt = blockSize >> 3U; + + while (blkCnt > 0U) + { + /* Copy 4 new input samples into the state buffer. */ + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + + /* Set all accumulators to zero */ + acc0 = 0.0f; + acc1 = 0.0f; + acc2 = 0.0f; + acc3 = 0.0f; + acc4 = 0.0f; + acc5 = 0.0f; + acc6 = 0.0f; + acc7 = 0.0f; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + + /* This is separated from the others to avoid + * a call to __aeabi_memmove which would be slower + */ + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + + /* Read the first 7 samples from the state buffer: x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2] */ + x0 = *px++; + x1 = *px++; + x2 = *px++; + x3 = *px++; + x4 = *px++; + x5 = *px++; + x6 = *px++; + + /* Loop unrolling: process 8 taps at a time. */ + tapCnt = numTaps >> 3U; + + while (tapCnt > 0U) + { + /* Read the b[numTaps-1] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-3] sample */ + x7 = *(px++); + + /* acc0 += b[numTaps-1] * x[n-numTaps] */ + acc0 += x0 * c0; + + /* acc1 += b[numTaps-1] * x[n-numTaps-1] */ + acc1 += x1 * c0; + + /* acc2 += b[numTaps-1] * x[n-numTaps-2] */ + acc2 += x2 * c0; + + /* acc3 += b[numTaps-1] * x[n-numTaps-3] */ + acc3 += x3 * c0; + + /* acc4 += b[numTaps-1] * x[n-numTaps-4] */ + acc4 += x4 * c0; + + /* acc1 += b[numTaps-1] * x[n-numTaps-5] */ + acc5 += x5 * c0; + + /* acc2 += b[numTaps-1] * x[n-numTaps-6] */ + acc6 += x6 * c0; + + /* acc3 += b[numTaps-1] * x[n-numTaps-7] */ + acc7 += x7 * c0; + + /* Read the b[numTaps-2] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-4] sample */ + x0 = *(px++); + + /* Perform the multiply-accumulate */ + acc0 += x1 * c0; + acc1 += x2 * c0; + acc2 += x3 * c0; + acc3 += x4 * c0; + acc4 += x5 * c0; + acc5 += x6 * c0; + acc6 += x7 * c0; + acc7 += x0 * c0; + + /* Read the b[numTaps-3] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-5] sample */ + x1 = *(px++); + + /* Perform the multiply-accumulates */ + acc0 += x2 * c0; + acc1 += x3 * c0; + acc2 += x4 * c0; + acc3 += x5 * c0; + acc4 += x6 * c0; + acc5 += x7 * c0; + acc6 += x0 * c0; + acc7 += x1 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-6] sample */ + x2 = *(px++); + + /* Perform the multiply-accumulates */ + acc0 += x3 * c0; + acc1 += x4 * c0; + acc2 += x5 * c0; + acc3 += x6 * c0; + acc4 += x7 * c0; + acc5 += x0 * c0; + acc6 += x1 * c0; + acc7 += x2 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-6] sample */ + x3 = *(px++); + /* Perform the multiply-accumulates */ + acc0 += x4 * c0; + acc1 += x5 * c0; + acc2 += x6 * c0; + acc3 += x7 * c0; + acc4 += x0 * c0; + acc5 += x1 * c0; + acc6 += x2 * c0; + acc7 += x3 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-6] sample */ + x4 = *(px++); + + /* Perform the multiply-accumulates */ + acc0 += x5 * c0; + acc1 += x6 * c0; + acc2 += x7 * c0; + acc3 += x0 * c0; + acc4 += x1 * c0; + acc5 += x2 * c0; + acc6 += x3 * c0; + acc7 += x4 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-6] sample */ + x5 = *(px++); + + /* Perform the multiply-accumulates */ + acc0 += x6 * c0; + acc1 += x7 * c0; + acc2 += x0 * c0; + acc3 += x1 * c0; + acc4 += x2 * c0; + acc5 += x3 * c0; + acc6 += x4 * c0; + acc7 += x5 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-6] sample */ + x6 = *(px++); + + /* Perform the multiply-accumulates */ + acc0 += x7 * c0; + acc1 += x0 * c0; + acc2 += x1 * c0; + acc3 += x2 * c0; + acc4 += x3 * c0; + acc5 += x4 * c0; + acc6 += x5 * c0; + acc7 += x6 * c0; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + tapCnt = numTaps % 0x8U; + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *(pb++); + + /* Fetch 1 state variable */ + x7 = *(px++); + + /* Perform the multiply-accumulates */ + acc0 += x0 * c0; + acc1 += x1 * c0; + acc2 += x2 * c0; + acc3 += x3 * c0; + acc4 += x4 * c0; + acc5 += x5 * c0; + acc6 += x6 * c0; + acc7 += x7 * c0; + + /* Reuse the present sample states for next sample */ + x0 = x1; + x1 = x2; + x2 = x3; + x3 = x4; + x4 = x5; + x5 = x6; + x6 = x7; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Advance the state pointer by 8 to process the next group of 8 samples */ + pState = pState + 8; + + /* The results in the 8 accumulators, store in the destination buffer. */ + *pDst++ = acc0; + *pDst++ = acc1; + *pDst++ = acc2; + *pDst++ = acc3; + *pDst++ = acc4; + *pDst++ = acc5; + *pDst++ = acc6; + *pDst++ = acc7; + + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining output samples */ + blkCnt = blockSize % 0x8U; + +#else + + /* Initialize blkCnt with number of taps */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Copy one sample at a time into state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Set the accumulator to zero */ + acc0 = 0.0f; + + /* Initialize state pointer */ + px = pState; + + /* Initialize Coefficient pointer */ + pb = pCoeffs; + + i = numTaps; +#if defined (RISCV_VECTOR) + uint32_t vblkCnt = numTaps; /* Loop counter */ + size_t l; + vfloat32m8_t vx, vy; + vfloat32m1_t temp00m1,temp01m1,accm1; + l = vsetvl_e32m1(1); + temp00m1 = vfmv_v_f_f32m1(0, l); + temp01m1 = vfmv_v_f_f32m1(0, l); + for (; (l = vsetvl_e32m8(vblkCnt)) > 0; vblkCnt -= l) { + vx = vle32_v_f32m8(px, l); + px += l; + vy = vle32_v_f32m8(pb, l); + accm1 = vfredsum_vs_f32m8_f32m1 ( temp00m1,vfmul_vv_f32m8(vy, vx, l), temp01m1, l); + pb += l; + acc0 += vfmv_f_s_f32m1_f32(accm1); + } +#else + /* Perform the multiply-accumulates */ + while (i > 0U) + { + /* acc = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] */ + acc0 += *px++ * *pb++; + + i--; + } +#endif /* defined (RISCV_VECTOR) */ + /* Store result in destination buffer. */ + *pDst++ = acc0; + + /* Advance state pointer by 1 for the next sample */ + pState = pState + 1U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the start of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + +#if defined (RISCV_MATH_LOOPUNROLL) && !defined (RISCV_VECTOR) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = (numTaps - 1U) >> 2U; + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Calculate remaining number of copies */ + tapCnt = (numTaps - 1U) % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = (numTaps - 1U); + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ +#if defined (RISCV_VECTOR) + uint32_t vblkCnt = (numTaps - 1U); /* Loop counter */ + size_t l; + vfloat32m8_t vx; + for (; (l = vsetvl_e32m8(vblkCnt)) > 0; vblkCnt -= l) { + vx = vle32_v_f32m8(pState, l); + pState += l; + vse32_v_f32m8 (pStateCurnt, vx, l); + pStateCurnt += l; + } +#else + /* Copy remaining data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } +#endif /* defined (RISCV_VECTOR) */ + +} + + +/** +* @} end of FIR group +*/ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_fast_q15.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_fast_q15.c new file mode 100644 index 00000000..3dad8fdb --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_fast_q15.c @@ -0,0 +1,334 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_fir_fast_q15.c + * Description: Q15 Fast FIR filter processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR + @{ + */ + +/** + @brief Processing function for the Q15 FIR filter (fast version). + @param[in] S points to an instance of the Q15 FIR filter structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + This fast version uses a 32-bit accumulator with 2.30 format. + The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit. + Thus, if the accumulator result overflows it wraps around and distorts the result. + In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits. + The 2.30 accumulator is then truncated to 2.15 format and saturated to yield the 1.15 result. + + @remark + Refer to \ref riscv_fir_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion. Both the slow and the fast versions use the same instance structure. + Use function \ref riscv_fir_init_q15() to initialize the filter structure. + */ + +void riscv_fir_fast_q15( + const riscv_fir_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCurnt; /* Points to the current sample of the state */ + q15_t *px; /* Temporary pointer for state buffer */ + const q15_t *pb; /* Temporary pointer for coefficient buffer */ + q31_t acc0; /* Accumulators */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t tapCnt, blkCnt; /* Loop counters */ + +#if defined (RISCV_VECTOR) + uint32_t blkCnt_v; /* Loop counter */ + size_t l; + vint16m4_t v_x, v_y; + vint32m8_t v_a; + vint32m1_t v_temp; + l = vsetvl_e32m1(1); + v_temp = vsub_vv_i32m1(v_temp, v_temp, l); +#endif + +#if defined (RISCV_MATH_LOOPUNROLL) + q31_t acc1, acc2, acc3; /* Accumulators */ + q31_t x0, x1, x2, c0; /* Temporary variables to hold state and coefficient values */ +#endif + + /* S->pState points to state array which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 output values simultaneously. + * The variables acc0 ... acc3 hold output values that are being computed: + * + * acc0 = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] + * acc1 = b[numTaps-1] * x[n-numTaps] + b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1] + * acc2 = b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] + b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2] + * acc3 = b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps] +...+ b[0] * x[3] + */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Copy 4 new input samples into the state buffer. */ + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Typecast q15_t pointer to q31_t pointer for state reading in q31_t */ + px = pState; + + /* Typecast q15_t pointer to q31_t pointer for coefficient reading in q31_t */ + pb = pCoeffs; + + /* Read the first two samples from the state buffer: x[n-N], x[n-N-1] */ + x0 = read_q15x2_ia (&px); + + /* Read the third and forth samples from the state buffer: x[n-N-2], x[n-N-3] */ + x2 = read_q15x2_ia (&px); + + /* Loop over the number of taps. Unroll by a factor of 4. + Repeat until we've computed numTaps-(numTaps%4) coefficients. */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Read the first two coefficients using SIMD: b[N] and b[N-1] coefficients */ + c0 = read_q15x2_ia ((q15_t **) &pb); + + /* acc0 += b[N] * x[n-N] + b[N-1] * x[n-N-1] */ + acc0 = __SMLAD(x0, c0, acc0); + + /* acc2 += b[N] * x[n-N-2] + b[N-1] * x[n-N-3] */ + acc2 = __SMLAD(x2, c0, acc2); + + /* pack x[n-N-1] and x[n-N-2] */ + x1 = __PKHBT(x2, x0, 0); + + /* Read state x[n-N-4], x[n-N-5] */ + x0 = read_q15x2_ia (&px); + + /* acc1 += b[N] * x[n-N-1] + b[N-1] * x[n-N-2] */ + acc1 = __SMLADX(x1, c0, acc1); + + /* pack x[n-N-3] and x[n-N-4] */ + x1 = __PKHBT(x0, x2, 0); + + /* acc3 += b[N] * x[n-N-3] + b[N-1] * x[n-N-4] */ + acc3 = __SMLADX(x1, c0, acc3); + + /* Read coefficients b[N-2], b[N-3] */ + c0 = read_q15x2_ia ((q15_t **) &pb); + + /* acc0 += b[N-2] * x[n-N-2] + b[N-3] * x[n-N-3] */ + acc0 = __SMLAD(x2, c0, acc0); + + /* Read state x[n-N-6], x[n-N-7] with offset */ + x2 = read_q15x2_ia (&px); + + /* acc2 += b[N-2] * x[n-N-4] + b[N-3] * x[n-N-5] */ + acc2 = __SMLAD(x0, c0, acc2); + + /* acc1 += b[N-2] * x[n-N-3] + b[N-3] * x[n-N-4] */ + acc1 = __SMLADX(x1, c0, acc1); + + /* pack x[n-N-5] and x[n-N-6] */ + x1 = __PKHBT(x2, x0, 0); + + /* acc3 += b[N-2] * x[n-N-5] + b[N-3] * x[n-N-6] */ + acc3 = __SMLADX(x1, c0, acc3); + + /* Decrement tap count */ + tapCnt--; + } + + /* If the filter length is not a multiple of 4, compute the remaining filter taps. + This is always be 2 taps since the filter length is even. */ + if ((numTaps & 0x3U) != 0U) + { + /* Read last two coefficients */ + c0 = read_q15x2_ia ((q15_t **) &pb); + + /* Perform the multiply-accumulates */ + acc0 = __SMLAD(x0, c0, acc0); + acc2 = __SMLAD(x2, c0, acc2); + + /* pack state variables */ + x1 = __PKHBT(x2, x0, 0); + + /* Read last state variables */ + x0 = read_q15x2 (px); + + /* Perform the multiply-accumulates */ + acc1 = __SMLADX(x1, c0, acc1); + + /* pack state variables */ + x1 = __PKHBT(x0, x2, 0); + + /* Perform the multiply-accumulates */ + acc3 = __SMLADX(x1, c0, acc3); + } + + /* The results in the 4 accumulators are in 2.30 format. Convert to 1.15 with saturation. + Then store the 4 outputs in the destination buffer. */ +#if __RISCV_XLEN == 64 + write_q15x4_ia (&pDst, __RV_PKBB32(__PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16),__PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16))); +#else + write_q15x2_ia (&pDst, __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16)); + write_q15x2_ia (&pDst, __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16)); +#endif /* __RISCV_XLEN == 64 */ + /* Advance the state pointer by 4 to process the next group of 4 samples */ + pState = pState + 4U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining output samples */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of taps */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Copy two samples into state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Set the accumulator to zero */ + acc0 = 0; + + /* Use SIMD to hold states and coefficients */ + px = pState; + pb = pCoeffs; + +#if defined (RISCV_VECTOR) + blkCnt_v = numTaps; + l = vsetvl_e16m4(blkCnt_v); + v_a = vsub_vv_i32m8(v_a,v_a, l); + for (; (l = vsetvl_e16m4(blkCnt_v)) > 0; blkCnt_v -= l) { + v_x = vle16_v_i16m4(px, l); + v_y = vle16_v_i16m4(pb, l); + v_a = vwmacc_vv_i32m8(v_a,v_x,v_y, l); + px += l; + pb += l; + } + l = vsetvl_e16m4(numTaps); + acc0 = vmv_x_s_i32m1_i32 (vredsum_vs_i32m8_i32m1(v_temp,v_a,v_temp, l)); +#else + tapCnt = numTaps >> 1U; + do + { + acc0 += (q31_t) *px++ * *pb++; + acc0 += (q31_t) *px++ * *pb++; + + tapCnt--; + } + while (tapCnt > 0U); +#endif + /* The result is in 2.30 format. Convert to 1.15 with saturation. + Then store the output in the destination buffer. */ + *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16)); + + /* Advance state pointer by 1 for the next sample */ + pState = pState + 1U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the start of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = (numTaps - 1U) >> 2U; + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Calculate remaining number of copies */ + tapCnt = (numTaps - 1U) % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = (numTaps - 1U); + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + /* Copy remaining data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +} + +/** + @} end of FIR group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_fast_q31.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_fast_q31.c new file mode 100644 index 00000000..887666d4 --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_fast_q31.c @@ -0,0 +1,325 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_fir_fast_q31.c + * Description: Processing function for the Q31 Fast FIR filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR + @{ + */ + +/** + @brief Processing function for the Q31 FIR filter (fast version). + @param[in] S points to an instance of the Q31 structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + This function is optimized for speed at the expense of fixed-point precision and overflow protection. + The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format. + These intermediate results are added to a 2.30 accumulator. + Finally, the accumulator is saturated and converted to a 1.31 result. + The fast version has the same overflow behavior as the standard version and provides less precision since it discards the low 32 bits of each multiplication result. + In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits. + + @remark + Refer to \ref riscv_fir_q31() for a slower implementation of this function which uses a 64-bit accumulator to provide higher precision. Both the slow and the fast versions use the same instance structure. + Use function \ref riscv_fir_init_q31() to initialize the filter structure. + */ + +IAR_ONLY_LOW_OPTIMIZATION_ENTER +void riscv_fir_fast_q31( + const riscv_fir_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + q31_t *pState = S->pState; /* State pointer */ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *pStateCurnt; /* Points to the current sample of the state */ + q31_t *px; /* Temporary pointer for state buffer */ + const q31_t *pb; /* Temporary pointer for coefficient buffer */ + q31_t acc0; /* Accumulators */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i, tapCnt, blkCnt; /* Loop counters */ + +#if defined (RISCV_MATH_LOOPUNROLL) + q31_t acc1, acc2, acc3; /* Accumulators */ + q31_t x0, x1, x2, x3, c0; /* Temporary variables to hold state and coefficient values */ +#endif + + /* S->pState points to state array which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 output values simultaneously. + * The variables acc0 ... acc3 hold output values that are being computed: + * + * acc0 = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] + * acc1 = b[numTaps-1] * x[n-numTaps] + b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1] + * acc2 = b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] + b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2] + * acc3 = b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps] +...+ b[0] * x[3] + */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Copy 4 new input samples into the state buffer. */ + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + + /* Read the first 3 samples from the state buffer: + * x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2] */ + x0 = *px++; + x1 = *px++; + x2 = *px++; + + /* Loop unrolling. Process 4 taps at a time. */ + tapCnt = numTaps >> 2U; + + /* Loop over the number of taps. Unroll by a factor of 4. + Repeat until we've computed numTaps-4 coefficients. */ + while (tapCnt > 0U) + { + /* Read the b[numTaps] coefficient */ + c0 = *pb; + + /* Read x[n-numTaps-3] sample */ + x3 = *px; + + /* acc0 += b[numTaps] * x[n-numTaps] */ + multAcc_32x32_keep32_R(acc0, x0, c0); + + /* acc1 += b[numTaps] * x[n-numTaps-1] */ + multAcc_32x32_keep32_R(acc1, x1, c0); + + /* acc2 += b[numTaps] * x[n-numTaps-2] */ + multAcc_32x32_keep32_R(acc2, x2, c0); + + /* acc3 += b[numTaps] * x[n-numTaps-3] */ + multAcc_32x32_keep32_R(acc3, x3, c0); + + /* Read the b[numTaps-1] coefficient */ + c0 = *(pb + 1U); + + /* Read x[n-numTaps-4] sample */ + x0 = *(px + 1U); + + /* Perform the multiply-accumulates */ + multAcc_32x32_keep32_R(acc0, x1, c0); + multAcc_32x32_keep32_R(acc1, x2, c0); + multAcc_32x32_keep32_R(acc2, x3, c0); + multAcc_32x32_keep32_R(acc3, x0, c0); + + /* Read the b[numTaps-2] coefficient */ + c0 = *(pb + 2U); + + /* Read x[n-numTaps-5] sample */ + x1 = *(px + 2U); + + /* Perform the multiply-accumulates */ + multAcc_32x32_keep32_R(acc0, x2, c0); + multAcc_32x32_keep32_R(acc1, x3, c0); + multAcc_32x32_keep32_R(acc2, x0, c0); + multAcc_32x32_keep32_R(acc3, x1, c0); + + /* Read the b[numTaps-3] coefficients */ + c0 = *(pb + 3U); + + /* Read x[n-numTaps-6] sample */ + x2 = *(px + 3U); + + /* Perform the multiply-accumulates */ + multAcc_32x32_keep32_R(acc0, x3, c0); + multAcc_32x32_keep32_R(acc1, x0, c0); + multAcc_32x32_keep32_R(acc2, x1, c0); + multAcc_32x32_keep32_R(acc3, x2, c0); + + /* update coefficient pointer */ + pb += 4U; + px += 4U; + + /* Decrement loop counter */ + tapCnt--; + } + + /* If the filter length is not a multiple of 4, compute the remaining filter taps */ + tapCnt = numTaps % 0x4U; + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *(pb++); + + /* Fetch 1 state variable */ + x3 = *(px++); + + /* Perform the multiply-accumulates */ + multAcc_32x32_keep32_R(acc0, x0, c0); + multAcc_32x32_keep32_R(acc1, x1, c0); + multAcc_32x32_keep32_R(acc2, x2, c0); + multAcc_32x32_keep32_R(acc3, x3, c0); + + /* Reuse the present sample states for next sample */ + x0 = x1; + x1 = x2; + x2 = x3; + + /* Decrement loop counter */ + tapCnt--; + } + + /* The results in the 4 accumulators are in 2.30 format. Convert to 1.31 + Then store the 4 outputs in the destination buffer. */ + *pDst++ = (q31_t) (acc0 << 1); + *pDst++ = (q31_t) (acc1 << 1); + *pDst++ = (q31_t) (acc2 << 1); + *pDst++ = (q31_t) (acc3 << 1); + + /* Advance the state pointer by 4 to process the next group of 4 samples */ + pState = pState + 4U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining output samples */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of taps */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Copy one sample at a time into state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Set the accumulator to zero */ + acc0 = 0; + + /* Initialize state pointer */ + px = pState; + + /* Initialize Coefficient pointer */ + pb = pCoeffs; + + i = numTaps; + + /* Perform the multiply-accumulates */ + do + { + multAcc_32x32_keep32_R(acc0, (*px++), (*pb++)); + i--; + } while (i > 0U); + + /* The result is in 2.30 format. Convert to 1.31 + Then store the output in the destination buffer. */ + *pDst++ = (q31_t) (acc0 << 1); + + /* Advance state pointer by 1 for the next sample */ + pState = pState + 1U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the start of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = (numTaps - 1U) >> 2U; + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Calculate remaining number of copies */ + tapCnt = (numTaps - 1U) % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = (numTaps - 1U); + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + /* Copy remaining data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement the loop counter */ + tapCnt--; + } + +} +IAR_ONLY_LOW_OPTIMIZATION_EXIT +/** + @} end of FIR group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_init_f16.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_init_f16.c new file mode 100644 index 00000000..a6a2429e --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_init_f16.c @@ -0,0 +1,102 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_fir_init_f16.c + * Description: Floating-point FIR filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions_f16.h" + +#if defined(RISCV_FLOAT16_SUPPORTED) + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR + @{ + */ + +/** + @brief Initialization function for the floating-point FIR filter. + @param[in,out] S points to an instance of the floating-point FIR filter structure + @param[in] numTaps number of filter coefficients in the filter + @param[in] pCoeffs points to the filter coefficients buffer + @param[in] pState points to the state buffer + @param[in] blockSize number of samples processed per call + @return none + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: + 
+      {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ @par + pState points to the array of state variables. + pState is of length numTaps+blockSize-1 samples (except for Helium - see below), where blockSize is the number of input samples processed by each call to riscv_fir_f16(). + @par Initialization of Helium version + For Helium version the array of coefficients must be a multiple of 4 (4a) even if less + then 4a coefficients are defined in the FIR. The additional coefficients + (4a - numTaps) must be set to 0. + numTaps is still set to its right value in the init function. It means that + the implementation may require to read more coefficients due to the vectorization and + to avoid having to manage too many different cases in the code. + + + @par Helium state buffer + The state buffer must contain some additional temporary data + used during the computation but which is not the state of the FIR. + The first 8*ceil(blockSize/8) samples are temporary data. + The remaining samples are the state of the FIR filter. + So the state buffer has size numTaps + 8*ceil(blockSize/8) + blockSize - 1 + + */ + +void riscv_fir_init_f16( + riscv_fir_instance_f16 * S, + uint16_t numTaps, + const float16_t * pCoeffs, + float16_t * pState, + uint32_t blockSize) +{ + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer. The size is always (blockSize + numTaps - 1) */ + memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(float16_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of FIR group + */ + +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_init_f32.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_init_f32.c new file mode 100644 index 00000000..e8d6ff54 --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_init_f32.c @@ -0,0 +1,96 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_fir_init_f32.c + * Description: Floating-point FIR filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR + @{ + */ + +/** + @brief Initialization function for the floating-point FIR filter. + @param[in,out] S points to an instance of the floating-point FIR filter structure + @param[in] numTaps number of filter coefficients in the filter + @param[in] pCoeffs points to the filter coefficients buffer + @param[in] pState points to the state buffer + @param[in] blockSize number of samples processed per call + @return none + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: + 
+      {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ @par + pState points to the array of state variables and some working memory for the Helium version. + pState is of length numTaps+blockSize-1 samples (except for Helium - see below), where blockSize is the number of input samples processed by each call to riscv_fir_f32(). + @par Initialization of Helium version + For Helium version the array of coefficients must be a multiple of 4 (4a) even if less + then 4a coefficients are defined in the FIR. The additional coefficients + (4a - numTaps) must be set to 0. + numTaps is still set to its right value in the init function. It means that + the implementation may require to read more coefficients due to the vectorization and + to avoid having to manage too many different cases in the code. + + @par Helium state buffer + The state buffer must contain some additional temporary data + used during the computation but which is not the state of the FIR. + The first blockSize samples are temporary data. + The remaining samples are the state of the FIR filter. + So the state buffer has size numTaps + 2 * blockSize - 1 + + */ + +void riscv_fir_init_f32( + riscv_fir_instance_f32 * S, + uint16_t numTaps, + const float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize) +{ + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer. The size is always (blockSize + numTaps - 1) */ + memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(float32_t)); + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of FIR group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_init_q15.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_init_q15.c new file mode 100644 index 00000000..fafe2b55 --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_init_q15.c @@ -0,0 +1,146 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_fir_init_q15.c + * Description: Q15 FIR filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR + @{ + */ + +/** + @brief Initialization function for the Q15 FIR filter. + @param[in,out] S points to an instance of the Q15 FIR filter structure. + @param[in] numTaps number of filter coefficients in the filter. Must be even and greater than or equal to 4. + @param[in] pCoeffs points to the filter coefficients buffer. + @param[in] pState points to the state buffer. + @param[in] blockSize number of samples processed per call. + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_ARGUMENT_ERROR : numTaps is not greater than or equal to 4 and even + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: + 
+      {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ Note that numTaps must be even and greater than or equal to 4. + To implement an odd length filter simply increase numTaps by 1 and set the last coefficient to zero. + For example, to implement a filter with numTaps=3 and coefficients + 
+      {0.3, -0.8, 0.3}
+
+ set numTaps=4 and use the coefficients: + 
+      {0.3, -0.8, 0.3, 0}.
+
+ Similarly, to implement a two point filter + 
+      {0.3, -0.3}
+
+ set numTaps=4 and use the coefficients: + 
+      {0.3, -0.3, 0, 0}.
+
+ pState points to the array of state variables. + pState is of length numTaps+blockSize, when running on RISC-V Core with DSP enabled and is of length numTaps+blockSize-1, when running on RISC-V Core without DSP where blockSize is the number of input samples processed by each call to riscv_fir_q15(). + + @par Initialization of Helium version + For Helium version the array of coefficients must be a multiple of 8 (8a) even if less + then 8a coefficients are defined in the FIR. The additional coefficients + (8a - numTaps) must be set to 0. + numTaps is still set to its right value in the init function. It means that + the implementation may require to read more coefficients due to the vectorization and + to avoid having to manage too many different cases in the code. + */ + +riscv_status riscv_fir_init_q15( + riscv_fir_instance_q15 * S, + uint16_t numTaps, + const q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize) +{ + riscv_status status; + +#if defined (RISCV_MATH_DSP) + + /* The Number of filter coefficients in the filter must be even and at least 4 */ + if (numTaps & 0x1U) + { + status = RISCV_MATH_ARGUMENT_ERROR; + } + else + { + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear the state buffer. The size is always (blockSize + numTaps ) */ + memset(pState, 0, (numTaps + (blockSize)) * sizeof(q15_t)); + + /* Assign state pointer */ + S->pState = pState; + + status = RISCV_MATH_SUCCESS; + } + + return (status); + +#else + + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer. The size is always (blockSize + numTaps - 1) */ + memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(q15_t)); + + /* Assign state pointer */ + S->pState = pState; + + status = RISCV_MATH_SUCCESS; + + return (status); + +#endif /* #if defined (RISCV_MATH_DSP) */ + +} + +/** + @} end of FIR group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_init_q31.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_init_q31.c new file mode 100644 index 00000000..1d83ad6c --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_init_q31.c @@ -0,0 +1,97 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_fir_init_q31.c + * Description: Q31 FIR filter initialization function. + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR + @{ + */ + +/** + @brief Initialization function for the Q31 FIR filter. + @param[in,out] S points to an instance of the Q31 FIR filter structure + @param[in] numTaps number of filter coefficients in the filter + @param[in] pCoeffs points to the filter coefficients buffer + @param[in] pState points to the state buffer + @param[in] blockSize number of samples processed + @return none + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: + 
+      {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ pState points to the array of state variables. + pState is of length numTaps+blockSize-1 samples (except for Helium - see below), where blockSize is the number of input samples processed by each call to riscv_fir_q31(). + + @par Initialization of Helium version + For Helium version the array of coefficients must be a multiple of 4 (4a) even if less + then 4a coefficients are defined in the FIR. The additional coefficients + (4a - numTaps) must be set to 0. + numTaps is still set to its right value in the init function. It means that + the implementation may require to read more coefficients due to the vectorization and + to avoid having to manage too many different cases in the code. + + @par Helium state buffer + The state buffer must contain some additional temporary data + used during the computation but which is not the state of the FIR. + The first 2*4*ceil(blockSize/4) samples are temporary data. + The remaining samples are the state of the FIR filter. + So the state buffer has size numTaps + 8*ceil(blockSize/4) + blockSize - 1 + + */ + +void riscv_fir_init_q31( + riscv_fir_instance_q31 * S, + uint16_t numTaps, + const q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize) +{ + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer. The size is always (blockSize + numTaps - 1) */ + memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(q31_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of FIR group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_init_q7.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_init_q7.c new file mode 100644 index 00000000..e6ba6a0a --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_init_q7.c @@ -0,0 +1,91 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_fir_init_q7.c + * Description: Q7 FIR filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR + @{ + */ + +/** + @brief Initialization function for the Q7 FIR filter. + @param[in,out] S points to an instance of the Q7 FIR filter structure + @param[in] numTaps number of filter coefficients in the filter + @param[in] pCoeffs points to the filter coefficients buffer + @param[in] pState points to the state buffer + @param[in] blockSize number of samples processed + @return none + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: + 
+      {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ @par + pState points to the array of state variables. + pState is of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to riscv_fir_q7(). + + @par Initialization of Helium version + For Helium version the array of coefficients must be a multiple of 16 (16a) even if less + then 16a coefficients are defined in the FIR. The additional coefficients + (16a - numTaps) must be set to 0. + numTaps is still set to its right value in the init function. It means that + the implementation may require to read more coefficients due to the vectorization and + to avoid having to manage too many different cases in the code. + + */ + +void riscv_fir_init_q7( + riscv_fir_instance_q7 * S, + uint16_t numTaps, + const q7_t * pCoeffs, + q7_t * pState, + uint32_t blockSize) +{ + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer. The size is always (blockSize + numTaps - 1) */ + memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(q7_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of FIR group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_interpolate_f32.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_interpolate_f32.c new file mode 100644 index 00000000..28cc682e --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_interpolate_f32.c @@ -0,0 +1,494 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_fir_interpolate_f32.c + * Description: Floating-point FIR interpolation sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @defgroup FIR_Interpolate Finite Impulse Response (FIR) Interpolator + + These functions combine an upsampler (zero stuffer) and an FIR filter. + They are used in multirate systems for increasing the sample rate of a signal without introducing high frequency images. + Conceptually, the functions are equivalent to the block diagram below: + \image html FIRInterpolator.png "Components included in the FIR Interpolator functions" + After upsampling by a factor of L, the signal should be filtered by a lowpass filter with a normalized + cutoff frequency of 1/L in order to eliminate high frequency copies of the spectrum. + The user of the function is responsible for providing the filter coefficients. + + The FIR interpolator functions provided in the NMSIS DSP Library combine the upsampler and FIR filter in an efficient manner. + The upsampler inserts L-1 zeros between each sample. + Instead of multiplying by these zero values, the FIR filter is designed to skip them. + This leads to an efficient implementation without any wasted effort. + The functions operate on blocks of input and output data. + pSrc points to an array of blockSize input values and + pDst points to an array of blockSize*L output values. + + The library provides separate functions for Q15, Q31, and floating-point data types. + + @par Algorithm + The functions use a polyphase filter structure: + 
+      y[n] = b[0] * x[n] + b[L]   * x[n-1] + ... + b[L*(phaseLength-1)] * x[n-phaseLength+1]
+      y[n+1] = b[1] * x[n] + b[L+1] * x[n-1] + ... + b[L*(phaseLength-1)+1] * x[n-phaseLength+1]
+      ...
+      y[n+(L-1)] = b[L-1] * x[n] + b[2*L-1] * x[n-1] + ....+ b[L*(phaseLength-1)+(L-1)] * x[n-phaseLength+1]
+
+ This approach is more efficient than straightforward upsample-then-filter algorithms. + With this method the computation is reduced by a factor of 1/L when compared to using a standard FIR filter. + @par + pCoeffs points to a coefficient array of size numTaps. + numTaps must be a multiple of the interpolation factor L and this is checked by the + initialization functions. + Internally, the function divides the FIR filter's impulse response into shorter filters of length + phaseLength=numTaps/L. + Coefficients are stored in time reversed order. + 
+      {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ @par + pState points to a state array of size blockSize + phaseLength - 1. + Samples in the state buffer are stored in the order: + 
+     {x[n-phaseLength+1], x[n-phaseLength], x[n-phaseLength-1], x[n-phaseLength-2]....x[0], x[1], ..., x[blockSize-1]}
+
+ @par + The state variables are updated after each block of data is processed, the coefficients are untouched. + + @par Instance Structure + The coefficients and state variables for a filter are stored together in an instance data structure. + A separate instance structure must be defined for each filter. + Coefficient arrays may be shared among several instances while state variable array should be allocated separately. + There are separate instance structure declarations for each of the 3 supported data types. + + @par Initialization Functions + There is also an associated initialization function for each data type. + The initialization function performs the following operations: + - Sets the values of the internal structure fields. + - Zeros out the values in the state buffer. + - Checks to make sure that the length of the filter is a multiple of the interpolation factor. + To do this manually without calling the init function, assign the follow subfields of the instance structure: + L (interpolation factor), pCoeffs, phaseLength (numTaps / L), pState. Also set all of the values in pState to zero. + @par + Use of the initialization function is optional. + However, if the initialization function is used, then the instance structure cannot be placed into a const data section. + To place an instance structure into a const data section, the instance structure must be manually initialized. + The code below statically initializes each of the 3 different data type filter instance structures + 
+      riscv_fir_interpolate_instance_f32 S = {L, phaseLength, pCoeffs, pState};
+      riscv_fir_interpolate_instance_q31 S = {L, phaseLength, pCoeffs, pState};
+      riscv_fir_interpolate_instance_q15 S = {L, phaseLength, pCoeffs, pState};
+
+ @par + where L is the interpolation factor; phaseLength=numTaps/L is the + length of each of the shorter FIR filters used internally, + pCoeffs is the address of the coefficient buffer; + pState is the address of the state buffer. + Be sure to set the values in the state buffer to zeros when doing static initialization. + + @par Fixed-Point Behavior + Care must be taken when using the fixed-point versions of the FIR interpolate filter functions. + In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + Refer to the function specific documentation below for usage guidelines. + */ + +/** + @addtogroup FIR_Interpolate + @{ + */ + +/** + @brief Processing function for floating-point FIR interpolator. + @param[in] S points to an instance of the floating-point FIR interpolator structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + */ + + +void riscv_fir_interpolate_f32( + const riscv_fir_interpolate_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + + + float32_t *pState = S->pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *pStateCur; /* Points to the current sample of the state */ + float32_t *ptr1; /* Temporary pointer for state buffer */ + const float32_t *ptr2; /* Temporary pointer for coefficient buffer */ + float32_t sum0; /* Accumulators */ + uint32_t i, blkCnt, tapCnt; /* Loop counters */ + uint32_t phaseLen = S->phaseLength; /* Length of each polyphase filter component */ + uint32_t j; +#if defined(RISCV_VECTOR) + uint32_t blkCnt_v; /* Loop counter */ + size_t l; + vfloat32m8_t v_x, v_y; + vfloat32m8_t v_a; + vfloat32m1_t v_temp; + ptrdiff_t bstride = S->L*4; + l = vsetvl_e32m1(1); + v_temp = vfsub_vv_f32m1(v_temp, v_temp, l); +#endif +#if defined (RISCV_MATH_LOOPUNROLL) + float32_t acc0, acc1, acc2, acc3; + float32_t x0, x1, x2, x3; + float32_t c0, c1, c2, c3; +#endif + + /* S->pState buffer contains previous frame (phaseLen - 1) samples */ + /* pStateCur points to the location where the new input data should be written */ + pStateCur = S->pState + (phaseLen - 1U); + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Copy new input sample into the state buffer */ + *pStateCur++ = *pSrc++; + *pStateCur++ = *pSrc++; + *pStateCur++ = *pSrc++; + *pStateCur++ = *pSrc++; + + /* Address modifier index of coefficient buffer */ + j = 1U; + + /* Loop over the Interpolation factor. */ + i = (S->L); + + while (i > 0U) + { + /* Set accumulator to zero */ + acc0 = 0.0f; + acc1 = 0.0f; + acc2 = 0.0f; + acc3 = 0.0f; + + /* Initialize state pointer */ + ptr1 = pState; + + /* Initialize coefficient pointer */ + ptr2 = pCoeffs + (S->L - j); + + /* Loop over the polyPhase length. Unroll by a factor of 4. + Repeat until we've computed numTaps-(4*S->L) coefficients. */ + tapCnt = phaseLen >> 2U; + + x0 = *(ptr1++); + x1 = *(ptr1++); + x2 = *(ptr1++); + + while (tapCnt > 0U) + { + /* Read the input sample */ + x3 = *(ptr1++); + + /* Read the coefficient */ + c0 = *(ptr2); + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + acc2 += x2 * c0; + acc3 += x3 * c0; + + /* Read the coefficient */ + c1 = *(ptr2 + S->L); + + /* Read the input sample */ + x0 = *(ptr1++); + + /* Perform the multiply-accumulate */ + acc0 += x1 * c1; + acc1 += x2 * c1; + acc2 += x3 * c1; + acc3 += x0 * c1; + + /* Read the coefficient */ + c2 = *(ptr2 + S->L * 2); + + /* Read the input sample */ + x1 = *(ptr1++); + + /* Perform the multiply-accumulate */ + acc0 += x2 * c2; + acc1 += x3 * c2; + acc2 += x0 * c2; + acc3 += x1 * c2; + + /* Read the coefficient */ + c3 = *(ptr2 + S->L * 3); + + /* Read the input sample */ + x2 = *(ptr1++); + + /* Perform the multiply-accumulate */ + acc0 += x3 * c3; + acc1 += x0 * c3; + acc2 += x1 * c3; + acc3 += x2 * c3; + + + /* Upsampling is done by stuffing L-1 zeros between each sample. + * So instead of multiplying zeros with coefficients, + * Increment the coefficient pointer by interpolation factor times. */ + ptr2 += 4 * S->L; + + /* Decrement loop counter */ + tapCnt--; + } + + /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */ + tapCnt = phaseLen % 0x4U; + + while (tapCnt > 0U) + { + /* Read the input sample */ + x3 = *(ptr1++); + + /* Read the coefficient */ + c0 = *(ptr2); + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + acc2 += x2 * c0; + acc3 += x3 * c0; + + /* Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + /* update states for next sample processing */ + x0 = x1; + x1 = x2; + x2 = x3; + + /* Decrement loop counter */ + tapCnt--; + } + + /* The result is in the accumulator, store in the destination buffer. */ + *(pDst ) = acc0; + *(pDst + S->L) = acc1; + *(pDst + 2 * S->L) = acc2; + *(pDst + 3 * S->L) = acc3; + + pDst++; + + /* Increment the address modifier index of coefficient buffer */ + j++; + + /* Decrement loop counter */ + i--; + } + + /* Advance the state pointer by 1 + * to process the next group of interpolation factor number samples */ + pState = pState + 4; + + pDst += S->L * 3; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Copy new input sample into the state buffer */ + *pStateCur++ = *pSrc++; + + /* Address modifier index of coefficient buffer */ + j = 1U; + + /* Loop over the Interpolation factor. */ + i = S->L; + + while (i > 0U) + { + /* Set accumulator to zero */ + sum0 = 0.0f; + + /* Initialize state pointer */ + ptr1 = pState; + + /* Initialize coefficient pointer */ + ptr2 = pCoeffs + (S->L - j); + + /* Loop over the polyPhase length. + Repeat until we've computed numTaps-(4*S->L) coefficients. */ + + +#if defined(RISCV_VECTOR) + tapCnt = phaseLen; + blkCnt_v = tapCnt; + l = vsetvl_e32m8(blkCnt_v); + v_a = vfsub_vv_f32m8(v_a,v_a, l); + for (; (l = vsetvl_e32m8(blkCnt_v)) > 0; blkCnt_v -= l) { + v_x = vle32_v_f32m8(ptr1, l); + v_y = vlse32_v_f32m8(ptr2,bstride, l); + v_a = vfmacc_vv_f32m8(v_a,v_x,v_y, l); + ptr1 += l; + ptr2 += l; + } + l = vsetvl_e32m8(blockSize); + sum0 = vfmv_f_s_f32m1_f32 (vfredsum_vs_f32m8_f32m1(v_temp,v_a,v_temp, l)); +#else +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + tapCnt = phaseLen >> 2U; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + sum0 += *ptr1++ * *ptr2; + + /* Upsampling is done by stuffing L-1 zeros between each sample. + * So instead of multiplying zeros with coefficients, + * Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + sum0 += *ptr1++ * *ptr2; + ptr2 += S->L; + + sum0 += *ptr1++ * *ptr2; + ptr2 += S->L; + + sum0 += *ptr1++ * *ptr2; + ptr2 += S->L; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + tapCnt = phaseLen % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = phaseLen; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + sum0 += *ptr1++ * *ptr2; + + /* Upsampling is done by stuffing L-1 zeros between each sample. + * So instead of multiplying zeros with coefficients, + * Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + /* Decrement loop counter */ + tapCnt--; + } +#endif + /* The result is in the accumulator, store in the destination buffer. */ + *pDst++ = sum0; + + /* Increment the address modifier index of coefficient buffer */ + j++; + + /* Decrement the loop counter */ + i--; + } + + /* Advance the state pointer by 1 + * to process the next group of interpolation factor number samples */ + pState = pState + 1; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last phaseLen - 1 samples to the satrt of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCur = S->pState; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + tapCnt = (phaseLen - 1U) >> 2U; + + /* copy data */ + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + tapCnt = (phaseLen - 1U) % 0x04U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = (phaseLen - 1U); + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + +} + +/** + @} end of FIR_Interpolate group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_interpolate_init_f32.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_interpolate_init_f32.c new file mode 100644 index 00000000..660b7373 --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_interpolate_init_f32.c @@ -0,0 +1,107 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_fir_interpolate_init_f32.c + * Description: Floating-point FIR interpolator initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Interpolate + @{ + */ + +/** + @brief Initialization function for the floating-point FIR interpolator. + @param[in,out] S points to an instance of the floating-point FIR interpolator structure + @param[in] L upsample factor + @param[in] numTaps number of filter coefficients in the filter + @param[in] pCoeffs points to the filter coefficient buffer + @param[in] pState points to the state buffer + @param[in] blockSize number of input samples to process per call + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_ARGUMENT_ERROR : filter length numTaps is not a multiple of the interpolation factor L + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: + 
+      {b[numTaps-1], b[numTaps-2], b[numTaps-2], ..., b[1], b[0]}
+
+ @par + The length of the filter numTaps must be a multiple of the interpolation factor L. + @par + pState points to the array of state variables. + pState is of length (numTaps/L)+blockSize-1 words + where blockSize is the number of input samples processed by each call to riscv_fir_interpolate_f32(). + */ + +riscv_status riscv_fir_interpolate_init_f32( + riscv_fir_interpolate_instance_f32 * S, + uint8_t L, + uint16_t numTaps, + const float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize) +{ + riscv_status status; + + /* The filter length must be a multiple of the interpolation factor */ + if ((numTaps % L) != 0U) + { + /* Set status as RISCV_MATH_LENGTH_ERROR */ + status = RISCV_MATH_LENGTH_ERROR; + } + else + { + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Assign Interpolation factor */ + S->L = L; + + /* Assign polyPhaseLength */ + S->phaseLength = numTaps / L; + + /* Clear state buffer and size of buffer is always phaseLength + blockSize - 1 */ + memset(pState, 0, (blockSize + ((uint32_t) S->phaseLength - 1U)) * sizeof(float32_t)); + + /* Assign state pointer */ + S->pState = pState; + + status = RISCV_MATH_SUCCESS; + } + + return (status); +} + +/** + @} end of FIR_Interpolate group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_interpolate_init_q15.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_interpolate_init_q15.c new file mode 100644 index 00000000..62746f37 --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_interpolate_init_q15.c @@ -0,0 +1,107 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_fir_interpolate_init_q15.c + * Description: Q15 FIR interpolator initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Interpolate + @{ + */ + +/** + @brief Initialization function for the Q15 FIR interpolator. + @param[in,out] S points to an instance of the Q15 FIR interpolator structure + @param[in] L upsample factor + @param[in] numTaps number of filter coefficients in the filter + @param[in] pCoeffs points to the filter coefficient buffer + @param[in] pState points to the state buffer + @param[in] blockSize number of input samples to process per call + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_ARGUMENT_ERROR : filter length numTaps is not a multiple of the interpolation factor L + + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: + 
+      {b[numTaps-1], b[numTaps-2], b[numTaps-2], ..., b[1], b[0]}
+
+ The length of the filter numTaps must be a multiple of the interpolation factor L. + @par + pState points to the array of state variables. + pState is of length (numTaps/L)+blockSize-1 words + where blockSize is the number of input samples processed by each call to riscv_fir_interpolate_q15(). + */ + +riscv_status riscv_fir_interpolate_init_q15( + riscv_fir_interpolate_instance_q15 * S, + uint8_t L, + uint16_t numTaps, + const q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize) +{ + riscv_status status; + + /* The filter length must be a multiple of the interpolation factor */ + if ((numTaps % L) != 0U) + { + /* Set status as RISCV_MATH_LENGTH_ERROR */ + status = RISCV_MATH_LENGTH_ERROR; + } + else + { + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Assign Interpolation factor */ + S->L = L; + + /* Assign polyPhaseLength */ + S->phaseLength = numTaps / L; + + /* Clear state buffer and size of buffer is always phaseLength + blockSize - 1 */ + memset(pState, 0, (blockSize + ((uint32_t) S->phaseLength - 1U)) * sizeof(q15_t)); + + /* Assign state pointer */ + S->pState = pState; + + status = RISCV_MATH_SUCCESS; + } + + return (status); +} + +/** + @} end of FIR_Interpolate group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_interpolate_init_q31.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_interpolate_init_q31.c new file mode 100644 index 00000000..33dbb9e1 --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_interpolate_init_q31.c @@ -0,0 +1,106 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_fir_interpolate_init_q31.c + * Description: Q31 FIR interpolator initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Interpolate + @{ + */ + +/** + @brief Initialization function for the Q31 FIR interpolator. + @param[in,out] S points to an instance of the Q31 FIR interpolator structure + @param[in] L upsample factor + @param[in] numTaps number of filter coefficients in the filter + @param[in] pCoeffs points to the filter coefficient buffer + @param[in] pState points to the state buffer + @param[in] blockSize number of input samples to process per call + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_ARGUMENT_ERROR : filter length numTaps is not a multiple of the interpolation factor L + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: + 
+      {b[numTaps-1], b[numTaps-2], b[numTaps-2], ..., b[1], b[0]}
+
+ The length of the filter numTaps must be a multiple of the interpolation factor L. + @par + pState points to the array of state variables. + pState is of length (numTaps/L)+blockSize-1 words + where blockSize is the number of input samples processed by each call to riscv_fir_interpolate_q31(). + */ + +riscv_status riscv_fir_interpolate_init_q31( + riscv_fir_interpolate_instance_q31 * S, + uint8_t L, + uint16_t numTaps, + const q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize) +{ + riscv_status status; + + /* The filter length must be a multiple of the interpolation factor */ + if ((numTaps % L) != 0U) + { + /* Set status as RISCV_MATH_LENGTH_ERROR */ + status = RISCV_MATH_LENGTH_ERROR; + } + else + { + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Assign Interpolation factor */ + S->L = L; + + /* Assign polyPhaseLength */ + S->phaseLength = numTaps / L; + + /* Clear state buffer and size of buffer is always phaseLength + blockSize - 1 */ + memset(pState, 0, (blockSize + ((uint32_t) S->phaseLength - 1U)) * sizeof(q31_t)); + + /* Assign state pointer */ + S->pState = pState; + + status = RISCV_MATH_SUCCESS; + } + + return (status); +} + +/** + @} end of FIR_Interpolate group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_interpolate_q15.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_interpolate_q15.c new file mode 100644 index 00000000..ce446d21 --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_interpolate_q15.c @@ -0,0 +1,390 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_fir_interpolate_q15.c + * Description: Q15 FIR interpolation + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Interpolate + @{ + */ + +/** + @brief Processing function for the Q15 FIR interpolator. + @param[in] S points to an instance of the Q15 FIR interpolator structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ + +void riscv_fir_interpolate_q15( + const riscv_fir_interpolate_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + + + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCur; /* Points to the current sample of the state */ + q15_t *ptr1; /* Temporary pointer for state buffer */ + const q15_t *ptr2; /* Temporary pointer for coefficient buffer */ + q63_t sum0; /* Accumulators */ + uint32_t i, blkCnt, tapCnt; /* Loop counters */ + uint32_t phaseLen = S->phaseLength; /* Length of each polyphase filter component */ + uint32_t j; + +#if defined (RISCV_MATH_LOOPUNROLL) + q63_t acc0, acc1, acc2, acc3; + q15_t x0, x1, x2, x3; + q15_t c0, c1, c2, c3; +#endif + + /* S->pState buffer contains previous frame (phaseLen - 1) samples */ + /* pStateCur points to the location where the new input data should be written */ + pStateCur = S->pState + (phaseLen - 1U); + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Copy new input sample into the state buffer */ + *pStateCur++ = *pSrc++; + *pStateCur++ = *pSrc++; + *pStateCur++ = *pSrc++; + *pStateCur++ = *pSrc++; + + /* Address modifier index of coefficient buffer */ + j = 1U; + + /* Loop over the Interpolation factor. */ + i = (S->L); + + while (i > 0U) + { + /* Set accumulator to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Initialize state pointer */ + ptr1 = pState; + + /* Initialize coefficient pointer */ + ptr2 = pCoeffs + (S->L - j); + + /* Loop over the polyPhase length. Unroll by a factor of 4. + Repeat until we've computed numTaps-(4*S->L) coefficients. */ + tapCnt = phaseLen >> 2U; + + x0 = *(ptr1++); + x1 = *(ptr1++); + x2 = *(ptr1++); + + while (tapCnt > 0U) + { + /* Read the input sample */ + x3 = *(ptr1++); + + /* Read the coefficient */ + c0 = *(ptr2); + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x0 * c0; + acc1 += (q63_t) x1 * c0; + acc2 += (q63_t) x2 * c0; + acc3 += (q63_t) x3 * c0; + + /* Read the coefficient */ + c1 = *(ptr2 + S->L); + + /* Read the input sample */ + x0 = *(ptr1++); + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x1 * c1; + acc1 += (q63_t) x2 * c1; + acc2 += (q63_t) x3 * c1; + acc3 += (q63_t) x0 * c1; + + /* Read the coefficient */ + c2 = *(ptr2 + S->L * 2); + + /* Read the input sample */ + x1 = *(ptr1++); + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x2 * c2; + acc1 += (q63_t) x3 * c2; + acc2 += (q63_t) x0 * c2; + acc3 += (q63_t) x1 * c2; + + /* Read the coefficient */ + c3 = *(ptr2 + S->L * 3); + + /* Read the input sample */ + x2 = *(ptr1++); + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x3 * c3; + acc1 += (q63_t) x0 * c3; + acc2 += (q63_t) x1 * c3; + acc3 += (q63_t) x2 * c3; + + + /* Upsampling is done by stuffing L-1 zeros between each sample. + * So instead of multiplying zeros with coefficients, + * Increment the coefficient pointer by interpolation factor times. */ + ptr2 += 4 * S->L; + + /* Decrement loop counter */ + tapCnt--; + } + + /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */ + tapCnt = phaseLen % 0x4U; + + while (tapCnt > 0U) + { + /* Read the input sample */ + x3 = *(ptr1++); + + /* Read the coefficient */ + c0 = *(ptr2); + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x0 * c0; + acc1 += (q63_t) x1 * c0; + acc2 += (q63_t) x2 * c0; + acc3 += (q63_t) x3 * c0; + + /* Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + /* update states for next sample processing */ + x0 = x1; + x1 = x2; + x2 = x3; + + /* Decrement loop counter */ + tapCnt--; + } + + /* The result is in the accumulator, store in the destination buffer. */ + *(pDst ) = (q15_t) (__SSAT((acc0 >> 15), 16)); + *(pDst + S->L) = (q15_t) (__SSAT((acc1 >> 15), 16)); + *(pDst + 2 * S->L) = (q15_t) (__SSAT((acc2 >> 15), 16)); + *(pDst + 3 * S->L) = (q15_t) (__SSAT((acc3 >> 15), 16)); + + pDst++; + + /* Increment the address modifier index of coefficient buffer */ + j++; + + /* Decrement loop counter */ + i--; + } + + /* Advance the state pointer by 1 + * to process the next group of interpolation factor number samples */ + pState = pState + 4; + + pDst += S->L * 3; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Copy new input sample into the state buffer */ + *pStateCur++ = *pSrc++; + + /* Address modifier index of coefficient buffer */ + j = 1U; + + /* Loop over the Interpolation factor. */ + i = S->L; + while (i > 0U) + { + /* Set accumulator to zero */ + sum0 = 0; + + /* Initialize state pointer */ + ptr1 = pState; + + /* Initialize coefficient pointer */ + ptr2 = pCoeffs + (S->L - j); + + /* Loop over the polyPhase length. + Repeat until we've computed numTaps-(4*S->L) coefficients. */ + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + tapCnt = phaseLen >> 2U; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + sum0 += (q63_t) *ptr1++ * *ptr2; + + /* Upsampling is done by stuffing L-1 zeros between each sample. + * So instead of multiplying zeros with coefficients, + * Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + sum0 += (q63_t) *ptr1++ * *ptr2; + ptr2 += S->L; + + sum0 += (q63_t) *ptr1++ * *ptr2; + ptr2 += S->L; + + sum0 += (q63_t) *ptr1++ * *ptr2; + ptr2 += S->L; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + tapCnt = phaseLen % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = phaseLen; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + sum0 += (q63_t) *ptr1++ * *ptr2; + + /* Upsampling is done by stuffing L-1 zeros between each sample. + * So instead of multiplying zeros with coefficients, + * Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + /* Decrement loop counter */ + tapCnt--; + } + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16)); + + /* Increment the address modifier index of coefficient buffer */ + j++; + + /* Decrement the loop counter */ + i--; + } + + /* Advance the state pointer by 1 + * to process the next group of interpolation factor number samples */ + pState = pState + 1; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last phaseLen - 1 samples to the satrt of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCur = S->pState; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + tapCnt = (phaseLen - 1U) >> 2U; + + /* copy data */ + while (tapCnt > 0U) + { + write_q15x2_ia (&pStateCur, read_q15x2_ia (&pState)); + write_q15x2_ia (&pStateCur, read_q15x2_ia (&pState)); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + tapCnt = (phaseLen - 1U) % 0x04U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = (phaseLen - 1U); + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + +} +/** + @} end of FIR_Interpolate group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_interpolate_q31.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_interpolate_q31.c new file mode 100644 index 00000000..56a53fd3 --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_interpolate_q31.c @@ -0,0 +1,416 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_fir_interpolate_q31.c + * Description: Q31 FIR interpolation + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Interpolate + @{ + */ + +/** + @brief Processing function for the Q31 FIR interpolator. + @param[in] S points to an instance of the Q31 FIR interpolator structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + Thus, if the accumulator result overflows it wraps around rather than clip. + In order to avoid overflows completely the input signal must be scaled down by 1/(numTaps/L). + since numTaps/L additions occur per output sample. + After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + */ + +void riscv_fir_interpolate_q31( + const riscv_fir_interpolate_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + + + q31_t *pState = S->pState; /* State pointer */ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *pStateCur; /* Points to the current sample of the state */ + q31_t *ptr1; /* Temporary pointer for state buffer */ + const q31_t *ptr2; /* Temporary pointer for coefficient buffer */ + q63_t sum0; /* Accumulators */ + uint32_t i, blkCnt, tapCnt; /* Loop counters */ + uint32_t phaseLen = S->phaseLength; /* Length of each polyphase filter component */ + uint32_t j; +#if defined (RISCV_VECTOR) + uint32_t blkCnt_v; /* Loop counter */ + size_t l; + vint32m4_t v_x, v_y; + vint64m8_t v_a; + vint64m1_t v_temp; + ptrdiff_t bstride = S->L*4; + l = vsetvl_e64m1(1); + v_temp = vsub_vv_i64m1(v_temp, v_temp, l); +#endif + +#if defined (RISCV_MATH_LOOPUNROLL) + q63_t acc0, acc1, acc2, acc3; + q31_t x0, x1, x2, x3; + q31_t c0, c1, c2, c3; +#endif + + /* S->pState buffer contains previous frame (phaseLen - 1) samples */ + /* pStateCur points to the location where the new input data should be written */ + pStateCur = S->pState + (phaseLen - 1U); + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Copy new input sample into the state buffer */ + *pStateCur++ = *pSrc++; + *pStateCur++ = *pSrc++; + *pStateCur++ = *pSrc++; + *pStateCur++ = *pSrc++; + + /* Address modifier index of coefficient buffer */ + j = 1U; + + /* Loop over the Interpolation factor. */ + i = (S->L); + + while (i > 0U) + { + /* Set accumulator to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Initialize state pointer */ + ptr1 = pState; + + /* Initialize coefficient pointer */ + ptr2 = pCoeffs + (S->L - j); + + /* Loop over the polyPhase length. Unroll by a factor of 4. + Repeat until we've computed numTaps-(4*S->L) coefficients. */ + tapCnt = phaseLen >> 2U; + + x0 = *(ptr1++); + x1 = *(ptr1++); + x2 = *(ptr1++); + + while (tapCnt > 0U) + { + /* Read the input sample */ + x3 = *(ptr1++); + + /* Read the coefficient */ + c0 = *(ptr2); + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x0 * c0; + acc1 += (q63_t) x1 * c0; + acc2 += (q63_t) x2 * c0; + acc3 += (q63_t) x3 * c0; + + /* Read the coefficient */ + c1 = *(ptr2 + S->L); + + /* Read the input sample */ + x0 = *(ptr1++); + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x1 * c1; + acc1 += (q63_t) x2 * c1; + acc2 += (q63_t) x3 * c1; + acc3 += (q63_t) x0 * c1; + + /* Read the coefficient */ + c2 = *(ptr2 + S->L * 2); + + /* Read the input sample */ + x1 = *(ptr1++); + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x2 * c2; + acc1 += (q63_t) x3 * c2; + acc2 += (q63_t) x0 * c2; + acc3 += (q63_t) x1 * c2; + + /* Read the coefficient */ + c3 = *(ptr2 + S->L * 3); + + /* Read the input sample */ + x2 = *(ptr1++); + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x3 * c3; + acc1 += (q63_t) x0 * c3; + acc2 += (q63_t) x1 * c3; + acc3 += (q63_t) x2 * c3; + + + /* Upsampling is done by stuffing L-1 zeros between each sample. + * So instead of multiplying zeros with coefficients, + * Increment the coefficient pointer by interpolation factor times. */ + ptr2 += 4 * S->L; + + /* Decrement loop counter */ + tapCnt--; + } + + /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */ + tapCnt = phaseLen % 0x4U; + + while (tapCnt > 0U) + { + /* Read the input sample */ + x3 = *(ptr1++); + + /* Read the coefficient */ + c0 = *(ptr2); + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x0 * c0; + acc1 += (q63_t) x1 * c0; + acc2 += (q63_t) x2 * c0; + acc3 += (q63_t) x3 * c0; + + /* Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + /* update states for next sample processing */ + x0 = x1; + x1 = x2; + x2 = x3; + + /* Decrement loop counter */ + tapCnt--; + } + + /* The result is in the accumulator, store in the destination buffer. */ + *(pDst ) = (q31_t) (acc0 >> 31); + *(pDst + S->L) = (q31_t) (acc1 >> 31); + *(pDst + 2 * S->L) = (q31_t) (acc2 >> 31); + *(pDst + 3 * S->L) = (q31_t) (acc3 >> 31); + + pDst++; + + /* Increment the address modifier index of coefficient buffer */ + j++; + + /* Decrement loop counter */ + i--; + } + + /* Advance the state pointer by 1 + * to process the next group of interpolation factor number samples */ + pState = pState + 4; + + pDst += S->L * 3; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Copy new input sample into the state buffer */ + *pStateCur++ = *pSrc++; + + /* Address modifier index of coefficient buffer */ + j = 1U; + + /* Loop over the Interpolation factor. */ + i = S->L; + while (i > 0U) + { + /* Set accumulator to zero */ + sum0 = 0; + + /* Initialize state pointer */ + ptr1 = pState; + + /* Initialize coefficient pointer */ + ptr2 = pCoeffs + (S->L - j); + + /* Loop over the polyPhase length. + Repeat until we've computed numTaps-(4*S->L) coefficients. */ +#if defined (RISCV_VECTOR) + tapCnt = phaseLen; + blkCnt_v = tapCnt; + l = vsetvl_e32m4(blkCnt_v); + v_a = vsub_vv_i64m8(v_a,v_a, l); + for (; (l = vsetvl_e32m4(blkCnt_v)) > 0; blkCnt_v -= l) { + v_x = vle32_v_i32m4(ptr1, l); + v_y = vlse32_v_i32m4(ptr2,bstride, l); + v_a = vwmacc_vv_i64m8(v_a,v_x,v_y, l); + ptr1 += l; + ptr2 += l*S->L; + } + l = vsetvl_e32m4(tapCnt); + sum0 = vmv_x_s_i64m1_i64 (vredsum_vs_i64m8_i64m1(v_temp,v_a,v_temp, l)); +#else +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + tapCnt = phaseLen >> 2U; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + sum0 += (q63_t) *ptr1++ * *ptr2; + + /* Upsampling is done by stuffing L-1 zeros between each sample. + * So instead of multiplying zeros with coefficients, + * Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + sum0 += (q63_t) *ptr1++ * *ptr2; + ptr2 += S->L; + + sum0 += (q63_t) *ptr1++ * *ptr2; + ptr2 += S->L; + + sum0 += (q63_t) *ptr1++ * *ptr2; + ptr2 += S->L; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + tapCnt = phaseLen % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = phaseLen; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + sum0 += (q63_t) *ptr1++ * *ptr2; + + /* Upsampling is done by stuffing L-1 zeros between each sample. + * So instead of multiplying zeros with coefficients, + * Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + /* Decrement loop counter */ + tapCnt--; + } +#endif + /* The result is in the accumulator, store in the destination buffer. */ + *pDst++ = (q31_t) (sum0 >> 31); + + /* Increment the address modifier index of coefficient buffer */ + j++; + + /* Decrement the loop counter */ + i--; + } + + /* Advance the state pointer by 1 + * to process the next group of interpolation factor number samples */ + pState = pState + 1; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last phaseLen - 1 samples to the satrt of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCur = S->pState; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + tapCnt = (phaseLen - 1U) >> 2U; + + /* copy data */ + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + tapCnt = (phaseLen - 1U) % 0x04U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = (phaseLen - 1U); + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + +} +/** + @} end of FIR_Interpolate group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_lattice_f32.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_lattice_f32.c new file mode 100644 index 00000000..b7f822cb --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_lattice_f32.c @@ -0,0 +1,454 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_fir_lattice_f32.c + * Description: Processing function for floating-point FIR Lattice filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @defgroup FIR_Lattice Finite Impulse Response (FIR) Lattice Filters + + This set of functions implements Finite Impulse Response (FIR) lattice filters + for Q15, Q31 and floating-point data types. Lattice filters are used in a + variety of adaptive filter applications. The filter structure is feedforward and + the net impulse response is finite length. + The functions operate on blocks + of input and output data and each call to the function processes + blockSize samples through the filter. pSrc and + pDst point to input and output arrays containing blockSize values. + + @par Algorithm + \image html FIRLattice.png "Finite Impulse Response Lattice filter" + The following difference equation is implemented: + @par + 
+      f0[n] = g0[n] = x[n]
+      fm[n] = fm-1[n] + km * gm-1[n-1] for m = 1, 2, ...M
+      gm[n] = km * fm-1[n] + gm-1[n-1] for m = 1, 2, ...M
+      y[n] = fM[n]
+
+ @par + pCoeffs points to tha array of reflection coefficients of size numStages. + Reflection Coefficients are stored in the following order. + @par + 
+      {k1, k2, ..., kM}
+
+ where M is number of stages + @par + pState points to a state array of size numStages. + The state variables (g values) hold previous inputs and are stored in the following order. + 
+    {g0[n], g1[n], g2[n] ...gM-1[n]}
+
+ The state variables are updated after each block of data is processed; the coefficients are untouched. + + @par Instance Structure + The coefficients and state variables for a filter are stored together in an instance data structure. + A separate instance structure must be defined for each filter. + Coefficient arrays may be shared among several instances while state variable arrays cannot be shared. + There are separate instance structure declarations for each of the 3 supported data types. + + @par Initialization Functions + There is also an associated initialization function for each data type. + The initialization function performs the following operations: + - Sets the values of the internal structure fields. + - Zeros out the values in the state buffer. + To do this manually without calling the init function, assign the follow subfields of the instance structure: + numStages, pCoeffs, pState. Also set all of the values in pState to zero. + @par + Use of the initialization function is optional. + However, if the initialization function is used, then the instance structure cannot be placed into a const data section. + To place an instance structure into a const data section, the instance structure must be manually initialized. + Set the values in the state buffer to zeros and then manually initialize the instance structure as follows: + 
+      riscv_fir_lattice_instance_f32 S = {numStages, pState, pCoeffs};
+      riscv_fir_lattice_instance_q31 S = {numStages, pState, pCoeffs};
+      riscv_fir_lattice_instance_q15 S = {numStages, pState, pCoeffs};
+
+ @par + where numStages is the number of stages in the filter; + pState is the address of the state buffer; + pCoeffs is the address of the coefficient buffer. + + @par Fixed-Point Behavior + Care must be taken when using the fixed-point versions of the FIR Lattice filter functions. + In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + Refer to the function specific documentation below for usage guidelines. + */ + +/** + @addtogroup FIR_Lattice + @{ + */ + +/** + @brief Processing function for the floating-point FIR lattice filter. + @param[in] S points to an instance of the floating-point FIR lattice structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + */ + +void riscv_fir_lattice_f32( + const riscv_fir_lattice_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *px; /* Temporary state pointer */ + const float32_t *pk; /* Temporary coefficient pointer */ + uint32_t numStages = S->numStages; /* Number of stages in the filter */ + uint32_t blkCnt, stageCnt; /* Loop counters */ + float32_t fcurr0, fnext0, gnext0, gcurr0; /* Temporary variables */ + +#if defined (RISCV_MATH_LOOPUNROLL) + float32_t fcurr1, fnext1, gnext1; /* Temporary variables for second sample in loop unrolling */ + float32_t fcurr2, fnext2, gnext2; /* Temporary variables for third sample in loop unrolling */ + float32_t fcurr3, fnext3, gnext3; /* Temporary variables for fourth sample in loop unrolling */ +#endif + + gcurr0 = 0.0f; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Read two samples from input buffer */ + /* f0(n) = x(n) */ + fcurr0 = *pSrc++; + fcurr1 = *pSrc++; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coeff pointer */ + pk = pCoeffs; + + /* Read g0(n-1) from state buffer */ + gcurr0 = *px; + + /* Process first sample for first tap */ + /* f1(n) = f0(n) + K1 * g0(n-1) */ + fnext0 = (gcurr0 * (*pk)) + fcurr0; + + /* g1(n) = f0(n) * K1 + g0(n-1) */ + gnext0 = (fcurr0 * (*pk)) + gcurr0; + + /* Process second sample for first tap */ + fnext1 = (fcurr0 * (*pk)) + fcurr1; + gnext1 = (fcurr1 * (*pk)) + fcurr0; + + /* Read next two samples from input buffer */ + /* f0(n+2) = x(n+2) */ + fcurr2 = *pSrc++; + fcurr3 = *pSrc++; + + /* Process third sample for first tap */ + fnext2 = (fcurr1 * (*pk)) + fcurr2; + gnext2 = (fcurr2 * (*pk)) + fcurr1; + + /* Process fourth sample for first tap */ + fnext3 = (fcurr2 * (*pk )) + fcurr3; + gnext3 = (fcurr3 * (*pk++)) + fcurr2; + + /* Copy only last input sample into the state buffer + which will be used for next samples processing */ + *px++ = fcurr3; + + /* Update of f values for next coefficient set processing */ + fcurr0 = fnext0; + fcurr1 = fnext1; + fcurr2 = fnext2; + fcurr3 = fnext3; + + /* Loop unrolling. Process 4 taps at a time . */ + stageCnt = (numStages - 1U) >> 2U; + + /* Loop over the number of taps. Unroll by a factor of 4. + Repeat until we've computed numStages-3 coefficients. */ + + /* Process 2nd, 3rd, 4th and 5th taps ... here */ + while (stageCnt > 0U) + { + /* Read g1(n-1), g3(n-1) .... from state */ + gcurr0 = *px; + + /* save g1(n) in state buffer */ + *px++ = gnext3; + + /* Process first sample for 2nd, 6th .. tap */ + /* Sample processing for K2, K6.... */ + /* f2(n) = f1(n) + K2 * g1(n-1) */ + fnext0 = (gcurr0 * (*pk)) + fcurr0; + + /* Process second sample for 2nd, 6th .. tap */ + /* for sample 2 processing */ + fnext1 = (gnext0 * (*pk)) + fcurr1; + + /* Process third sample for 2nd, 6th .. tap */ + fnext2 = (gnext1 * (*pk)) + fcurr2; + + /* Process fourth sample for 2nd, 6th .. tap */ + fnext3 = (gnext2 * (*pk)) + fcurr3; + + /* g2(n) = f1(n) * K2 + g1(n-1) */ + /* Calculation of state values for next stage */ + gnext3 = (fcurr3 * (*pk)) + gnext2; + + gnext2 = (fcurr2 * (*pk)) + gnext1; + + gnext1 = (fcurr1 * (*pk)) + gnext0; + + gnext0 = (fcurr0 * (*pk++)) + gcurr0; + + + /* Read g2(n-1), g4(n-1) .... from state */ + gcurr0 = *px; + + /* save g2(n) in state buffer */ + *px++ = gnext3; + + /* Sample processing for K3, K7.... */ + /* Process first sample for 3rd, 7th .. tap */ + /* f3(n) = f2(n) + K3 * g2(n-1) */ + fcurr0 = (gcurr0 * (*pk)) + fnext0; + + /* Process second sample for 3rd, 7th .. tap */ + fcurr1 = (gnext0 * (*pk)) + fnext1; + + /* Process third sample for 3rd, 7th .. tap */ + fcurr2 = (gnext1 * (*pk)) + fnext2; + + /* Process fourth sample for 3rd, 7th .. tap */ + fcurr3 = (gnext2 * (*pk)) + fnext3; + + /* Calculation of state values for next stage */ + /* g3(n) = f2(n) * K3 + g2(n-1) */ + gnext3 = (fnext3 * (*pk)) + gnext2; + + gnext2 = (fnext2 * (*pk)) + gnext1; + + gnext1 = (fnext1 * (*pk)) + gnext0; + + gnext0 = (fnext0 * (*pk++)) + gcurr0; + + + /* Read g1(n-1), g3(n-1) .... from state */ + gcurr0 = *px; + + /* save g3(n) in state buffer */ + *px++ = gnext3; + + /* Sample processing for K4, K8.... */ + /* Process first sample for 4th, 8th .. tap */ + /* f4(n) = f3(n) + K4 * g3(n-1) */ + fnext0 = (gcurr0 * (*pk)) + fcurr0; + + /* Process second sample for 4th, 8th .. tap */ + /* for sample 2 processing */ + fnext1 = (gnext0 * (*pk)) + fcurr1; + + /* Process third sample for 4th, 8th .. tap */ + fnext2 = (gnext1 * (*pk)) + fcurr2; + + /* Process fourth sample for 4th, 8th .. tap */ + fnext3 = (gnext2 * (*pk)) + fcurr3; + + /* g4(n) = f3(n) * K4 + g3(n-1) */ + /* Calculation of state values for next stage */ + gnext3 = (fcurr3 * (*pk)) + gnext2; + + gnext2 = (fcurr2 * (*pk)) + gnext1; + + gnext1 = (fcurr1 * (*pk)) + gnext0; + + gnext0 = (fcurr0 * (*pk++)) + gcurr0; + + + /* Read g2(n-1), g4(n-1) .... from state */ + gcurr0 = *px; + + /* save g4(n) in state buffer */ + *px++ = gnext3; + + /* Sample processing for K5, K9.... */ + /* Process first sample for 5th, 9th .. tap */ + /* f5(n) = f4(n) + K5 * g4(n-1) */ + fcurr0 = (gcurr0 * (*pk)) + fnext0; + + /* Process second sample for 5th, 9th .. tap */ + fcurr1 = (gnext0 * (*pk)) + fnext1; + + /* Process third sample for 5th, 9th .. tap */ + fcurr2 = (gnext1 * (*pk)) + fnext2; + + /* Process fourth sample for 5th, 9th .. tap */ + fcurr3 = (gnext2 * (*pk)) + fnext3; + + /* Calculation of state values for next stage */ + /* g5(n) = f4(n) * K5 + g4(n-1) */ + gnext3 = (fnext3 * (*pk)) + gnext2; + + gnext2 = (fnext2 * (*pk)) + gnext1; + + gnext1 = (fnext1 * (*pk)) + gnext0; + + gnext0 = (fnext0 * (*pk++)) + gcurr0; + + stageCnt--; + } + + /* If the (filter length -1) is not a multiple of 4, compute the remaining filter taps */ + stageCnt = (numStages - 1U) % 0x4U; + + while (stageCnt > 0U) + { + gcurr0 = *px; + + /* save g value in state buffer */ + *px++ = gnext3; + + /* Process four samples for last three taps here */ + fnext0 = (gcurr0 * (*pk)) + fcurr0; + + fnext1 = (gnext0 * (*pk)) + fcurr1; + + fnext2 = (gnext1 * (*pk)) + fcurr2; + + fnext3 = (gnext2 * (*pk)) + fcurr3; + + /* g1(n) = f0(n) * K1 + g0(n-1) */ + gnext3 = (fcurr3 * (*pk)) + gnext2; + + gnext2 = (fcurr2 * (*pk)) + gnext1; + + gnext1 = (fcurr1 * (*pk)) + gnext0; + + gnext0 = (fcurr0 * (*pk++)) + gcurr0; + + /* Update of f values for next coefficient set processing */ + fcurr0 = fnext0; + fcurr1 = fnext1; + fcurr2 = fnext2; + fcurr3 = fnext3; + + stageCnt--; + } + + /* The results in the 4 accumulators, store in the destination buffer. */ + /* y(n) = fN(n) */ + *pDst++ = fcurr0; + *pDst++ = fcurr1; + *pDst++ = fcurr2; + *pDst++ = fcurr3; + + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* f0(n) = x(n) */ + fcurr0 = *pSrc++; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coeff pointer */ + pk = pCoeffs; + + /* read g2(n) from state buffer */ + gcurr0 = *px; + + /* for sample 1 processing */ + /* f1(n) = f0(n) + K1 * g0(n-1) */ + fnext0 = (gcurr0 * (*pk)) + fcurr0; + + /* g1(n) = f0(n) * K1 + g0(n-1) */ + gnext0 = (fcurr0 * (*pk++)) + gcurr0; + + /* save g1(n) in state buffer */ + *px++ = fcurr0; + + /* f1(n) is saved in fcurr0 for next stage processing */ + fcurr0 = fnext0; + + stageCnt = (numStages - 1U); + + /* stage loop */ + while (stageCnt > 0U) + { + /* read g2(n) from state buffer */ + gcurr0 = *px; + + /* save g1(n) in state buffer */ + *px++ = gnext0; + + /* Sample processing for K2, K3.... */ + /* f2(n) = f1(n) + K2 * g1(n-1) */ + fnext0 = (gcurr0 * (*pk)) + fcurr0; + + /* g2(n) = f1(n) * K2 + g1(n-1) */ + gnext0 = (fcurr0 * (*pk++)) + gcurr0; + + /* f1(n) is saved in fcurr0 for next stage processing */ + fcurr0 = fnext0; + + stageCnt--; + } + + /* y(n) = fN(n) */ + *pDst++ = fcurr0; + + blkCnt--; + } + +} + +/** + @} end of FIR_Lattice group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_lattice_init_f32.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_lattice_init_f32.c new file mode 100644 index 00000000..0382418b --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_lattice_init_f32.c @@ -0,0 +1,71 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_fir_lattice_init_f32.c + * Description: Floating-point FIR Lattice filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Lattice + @{ + */ + +/** + @brief Initialization function for the floating-point FIR lattice filter. + @param[in] S points to an instance of the floating-point FIR lattice structure + @param[in] numStages number of filter stages + @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages + @param[in] pState points to the state buffer. The array is of length numStages + @return none + */ + +void riscv_fir_lattice_init_f32( + riscv_fir_lattice_instance_f32 * S, + uint16_t numStages, + const float32_t * pCoeffs, + float32_t * pState) +{ + /* Assign filter taps */ + S->numStages = numStages; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always numStages */ + memset(pState, 0, (numStages) * sizeof(float32_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of FIR_Lattice group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_lattice_init_q15.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_lattice_init_q15.c new file mode 100644 index 00000000..51c18e7c --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_lattice_init_q15.c @@ -0,0 +1,71 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_fir_lattice_init_q15.c + * Description: Q15 FIR Lattice filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Lattice + @{ + */ + +/** + @brief Initialization function for the Q15 FIR lattice filter. + @param[in] S points to an instance of the Q15 FIR lattice structure + @param[in] numStages number of filter stages + @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages + @param[in] pState points to the state buffer. The array is of length numStages + @return none + */ + +void riscv_fir_lattice_init_q15( + riscv_fir_lattice_instance_q15 * S, + uint16_t numStages, + const q15_t * pCoeffs, + q15_t * pState) +{ + /* Assign filter taps */ + S->numStages = numStages; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always numStages */ + memset(pState, 0, (numStages) * sizeof(q15_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of FIR_Lattice group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_lattice_init_q31.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_lattice_init_q31.c new file mode 100644 index 00000000..071fdd93 --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_lattice_init_q31.c @@ -0,0 +1,71 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_fir_lattice_init_q31.c + * Description: Q31 FIR lattice filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Lattice + @{ + */ + +/** + @brief Initialization function for the Q31 FIR lattice filter. + @param[in] S points to an instance of the Q31 FIR lattice structure + @param[in] numStages number of filter stages + @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages + @param[in] pState points to the state buffer. The array is of length numStages + @return none + */ + +void riscv_fir_lattice_init_q31( + riscv_fir_lattice_instance_q31 * S, + uint16_t numStages, + const q31_t * pCoeffs, + q31_t * pState) +{ + /* Assign filter taps */ + S->numStages = numStages; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always numStages */ + memset(pState, 0, (numStages) * sizeof(q31_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of FIR_Lattice group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_lattice_q15.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_lattice_q15.c new file mode 100644 index 00000000..18062934 --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_lattice_q15.c @@ -0,0 +1,434 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_fir_lattice_q15.c + * Description: Q15 FIR lattice filter processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Lattice + @{ + */ + +/** + @brief Processing function for Q15 FIR lattice filter. + @param[in] S points to an instance of the Q15 FIR lattice structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + */ + +void riscv_fir_lattice_q15( + const riscv_fir_lattice_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *px; /* Temporary state pointer */ + const q15_t *pk; /* Temporary coefficient pointer */ + uint32_t numStages = S->numStages; /* Number of stages in the filter */ + uint32_t blkCnt, stageCnt; /* Loop counters */ + q31_t fcurr0, fnext0, gnext0, gcurr0; /* Temporary variables */ + + + +#if defined (RISCV_MATH_LOOPUNROLL) + q31_t fcurr1, fnext1, gnext1; /* Temporary variables for second sample in loop unrolling */ + q31_t fcurr2, fnext2, gnext2; /* Temporary variables for third sample in loop unrolling */ + q31_t fcurr3, fnext3, gnext3; /* Temporary variables for fourth sample in loop unrolling */ +#endif + + gcurr0 = 0; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Read two samples from input buffer */ + /* f0(n) = x(n) */ + fcurr0 = *pSrc++; + fcurr1 = *pSrc++; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coeff pointer */ + pk = pCoeffs; + + /* Read g0(n-1) from state buffer */ + gcurr0 = *px; + + /* Process first sample for first tap */ + /* f1(n) = f0(n) + K1 * g0(n-1) */ + fnext0 = (q31_t) ((gcurr0 * (*pk)) >> 15U) + fcurr0; + fnext0 = __SSAT(fnext0, 16); + + /* g1(n) = f0(n) * K1 + g0(n-1) */ + gnext0 = (q31_t) ((fcurr0 * (*pk)) >> 15U) + gcurr0; + gnext0 = __SSAT(gnext0, 16); + + /* Process second sample for first tap */ + fnext1 = (q31_t) ((fcurr0 * (*pk)) >> 15U) + fcurr1; + fnext1 = __SSAT(fnext1, 16); + gnext1 = (q31_t) ((fcurr1 * (*pk)) >> 15U) + fcurr0; + gnext1 = __SSAT(gnext1, 16); + + /* Read next two samples from input buffer */ + /* f0(n+2) = x(n+2) */ + fcurr2 = *pSrc++; + fcurr3 = *pSrc++; + + /* Process third sample for first tap */ + fnext2 = (q31_t) ((fcurr1 * (*pk)) >> 15U) + fcurr2; + fnext2 = __SSAT(fnext2, 16); + gnext2 = (q31_t) ((fcurr2 * (*pk)) >> 15U) + fcurr1; + gnext2 = __SSAT(gnext2, 16); + + /* Process fourth sample for first tap */ + fnext3 = (q31_t) ((fcurr2 * (*pk )) >> 15U) + fcurr3; + fnext3 = __SSAT(fnext3, 16); + gnext3 = (q31_t) ((fcurr3 * (*pk++)) >> 15U) + fcurr2; + gnext3 = __SSAT(gnext3, 16); + + /* Copy only last input sample into the state buffer + which will be used for next samples processing */ + *px++ = (q15_t) fcurr3; + + /* Update of f values for next coefficient set processing */ + fcurr0 = fnext0; + fcurr1 = fnext1; + fcurr2 = fnext2; + fcurr3 = fnext3; + + /* Loop unrolling. Process 4 taps at a time . */ + stageCnt = (numStages - 1U) >> 2U; + + /* Loop over the number of taps. Unroll by a factor of 4. + Repeat until we've computed numStages-3 coefficients. */ + + /* Process 2nd, 3rd, 4th and 5th taps ... here */ + while (stageCnt > 0U) + { + /* Read g1(n-1), g3(n-1) .... from state */ + gcurr0 = *px; + + /* save g1(n) in state buffer */ + *px++ = (q15_t) gnext3; + + /* Process first sample for 2nd, 6th .. tap */ + /* Sample processing for K2, K6.... */ + /* f1(n) = f0(n) + K1 * g0(n-1) */ + fnext0 = (q31_t) ((gcurr0 * (*pk)) >> 15U) + fcurr0; + fnext0 = __SSAT(fnext0, 16); + + /* Process second sample for 2nd, 6th .. tap */ + /* for sample 2 processing */ + fnext1 = (q31_t) ((gnext0 * (*pk)) >> 15U) + fcurr1; + fnext1 = __SSAT(fnext1, 16); + + /* Process third sample for 2nd, 6th .. tap */ + fnext2 = (q31_t) ((gnext1 * (*pk)) >> 15U) + fcurr2; + fnext2 = __SSAT(fnext2, 16); + + /* Process fourth sample for 2nd, 6th .. tap */ + fnext3 = (q31_t) ((gnext2 * (*pk)) >> 15U) + fcurr3; + fnext3 = __SSAT(fnext3, 16); + + /* g1(n) = f0(n) * K1 + g0(n-1) */ + /* Calculation of state values for next stage */ + gnext3 = (q31_t) ((fcurr3 * (*pk)) >> 15U) + gnext2; + gnext3 = __SSAT(gnext3, 16); + + gnext2 = (q31_t) ((fcurr2 * (*pk)) >> 15U) + gnext1; + gnext2 = __SSAT(gnext2, 16); + + gnext1 = (q31_t) ((fcurr1 * (*pk)) >> 15U) + gnext0; + gnext1 = __SSAT(gnext1, 16); + + gnext0 = (q31_t) ((fcurr0 * (*pk++)) >> 15U) + gcurr0; + gnext0 = __SSAT(gnext0, 16); + + + /* Read g2(n-1), g4(n-1) .... from state */ + gcurr0 = *px; + + /* save g1(n) in state buffer */ + *px++ = (q15_t) gnext3; + + /* Sample processing for K3, K7.... */ + /* Process first sample for 3rd, 7th .. tap */ + /* f3(n) = f2(n) + K3 * g2(n-1) */ + fcurr0 = (q31_t) ((gcurr0 * (*pk)) >> 15U) + fnext0; + fcurr0 = __SSAT(fcurr0, 16); + + /* Process second sample for 3rd, 7th .. tap */ + fcurr1 = (q31_t) ((gnext0 * (*pk)) >> 15U) + fnext1; + fcurr1 = __SSAT(fcurr1, 16); + + /* Process third sample for 3rd, 7th .. tap */ + fcurr2 = (q31_t) ((gnext1 * (*pk)) >> 15U) + fnext2; + fcurr2 = __SSAT(fcurr2, 16); + + /* Process fourth sample for 3rd, 7th .. tap */ + fcurr3 = (q31_t) ((gnext2 * (*pk)) >> 15U) + fnext3; + fcurr3 = __SSAT(fcurr3, 16); + + /* Calculation of state values for next stage */ + /* g3(n) = f2(n) * K3 + g2(n-1) */ + gnext3 = (q31_t) ((fnext3 * (*pk)) >> 15U) + gnext2; + gnext3 = __SSAT(gnext3, 16); + + gnext2 = (q31_t) ((fnext2 * (*pk)) >> 15U) + gnext1; + gnext2 = __SSAT(gnext2, 16); + + gnext1 = (q31_t) ((fnext1 * (*pk)) >> 15U) + gnext0; + gnext1 = __SSAT(gnext1, 16); + + gnext0 = (q31_t) ((fnext0 * (*pk++)) >> 15U) + gcurr0; + gnext0 = __SSAT(gnext0, 16); + + /* Read g1(n-1), g3(n-1) .... from state */ + gcurr0 = *px; + + /* save g1(n) in state buffer */ + *px++ = (q15_t) gnext3; + + /* Sample processing for K4, K8.... */ + /* Process first sample for 4th, 8th .. tap */ + /* f4(n) = f3(n) + K4 * g3(n-1) */ + fnext0 = (q31_t) ((gcurr0 * (*pk)) >> 15U) + fcurr0; + fnext0 = __SSAT(fnext0, 16); + + /* Process second sample for 4th, 8th .. tap */ + /* for sample 2 processing */ + fnext1 = (q31_t) ((gnext0 * (*pk)) >> 15U) + fcurr1; + fnext1 = __SSAT(fnext1, 16); + + /* Process third sample for 4th, 8th .. tap */ + fnext2 = (q31_t) ((gnext1 * (*pk)) >> 15U) + fcurr2; + fnext2 = __SSAT(fnext2, 16); + + /* Process fourth sample for 4th, 8th .. tap */ + fnext3 = (q31_t) ((gnext2 * (*pk)) >> 15U) + fcurr3; + fnext3 = __SSAT(fnext3, 16); + + /* g4(n) = f3(n) * K4 + g3(n-1) */ + /* Calculation of state values for next stage */ + gnext3 = (q31_t) ((fcurr3 * (*pk)) >> 15U) + gnext2; + gnext3 = __SSAT(gnext3, 16); + + gnext2 = (q31_t) ((fcurr2 * (*pk)) >> 15U) + gnext1; + gnext2 = __SSAT(gnext2, 16); + + gnext1 = (q31_t) ((fcurr1 * (*pk)) >> 15U) + gnext0; + gnext1 = __SSAT(gnext1, 16); + + gnext0 = (q31_t) ((fcurr0 * (*pk++)) >> 15U) + gcurr0; + gnext0 = __SSAT(gnext0, 16); + + /* Read g2(n-1), g4(n-1) .... from state */ + gcurr0 = *px; + + /* save g4(n) in state buffer */ + *px++ = (q15_t) gnext3; + + /* Sample processing for K5, K9.... */ + /* Process first sample for 5th, 9th .. tap */ + /* f5(n) = f4(n) + K5 * g4(n-1) */ + fcurr0 = (q31_t) ((gcurr0 * (*pk)) >> 15U) + fnext0; + fcurr0 = __SSAT(fcurr0, 16); + + /* Process second sample for 5th, 9th .. tap */ + fcurr1 = (q31_t) ((gnext0 * (*pk)) >> 15U) + fnext1; + fcurr1 = __SSAT(fcurr1, 16); + + /* Process third sample for 5th, 9th .. tap */ + fcurr2 = (q31_t) ((gnext1 * (*pk)) >> 15U) + fnext2; + fcurr2 = __SSAT(fcurr2, 16); + + /* Process fourth sample for 5th, 9th .. tap */ + fcurr3 = (q31_t) ((gnext2 * (*pk)) >> 15U) + fnext3; + fcurr3 = __SSAT(fcurr3, 16); + + /* Calculation of state values for next stage */ + /* g5(n) = f4(n) * K5 + g4(n-1) */ + gnext3 = (q31_t) ((fnext3 * (*pk)) >> 15U) + gnext2; + gnext3 = __SSAT(gnext3, 16); + + gnext2 = (q31_t) ((fnext2 * (*pk)) >> 15U) + gnext1; + gnext2 = __SSAT(gnext2, 16); + + gnext1 = (q31_t) ((fnext1 * (*pk)) >> 15U) + gnext0; + gnext1 = __SSAT(gnext1, 16); + + gnext0 = (q31_t) ((fnext0 * (*pk++)) >> 15U) + gcurr0; + gnext0 = __SSAT(gnext0, 16); + + stageCnt--; + } + + /* If the (filter length -1) is not a multiple of 4, compute the remaining filter taps */ + stageCnt = (numStages - 1U) % 0x4U; + + while (stageCnt > 0U) + { + gcurr0 = *px; + + /* save g value in state buffer */ + *px++ = (q15_t) gnext3; + + /* Process four samples for last three taps here */ + fnext0 = (q31_t) ((gcurr0 * (*pk)) >> 15U) + fcurr0; + fnext0 = __SSAT(fnext0, 16); + + fnext1 = (q31_t) ((gnext0 * (*pk)) >> 15U) + fcurr1; + fnext1 = __SSAT(fnext1, 16); + + fnext2 = (q31_t) ((gnext1 * (*pk)) >> 15U) + fcurr2; + fnext2 = __SSAT(fnext2, 16); + + fnext3 = (q31_t) ((gnext2 * (*pk)) >> 15U) + fcurr3; + fnext3 = __SSAT(fnext3, 16); + + /* g1(n) = f0(n) * K1 + g0(n-1) */ + gnext3 = (q31_t) ((fcurr3 * (*pk)) >> 15U) + gnext2; + gnext3 = __SSAT(gnext3, 16); + + gnext2 = (q31_t) ((fcurr2 * (*pk)) >> 15U) + gnext1; + gnext2 = __SSAT(gnext2, 16); + + gnext1 = (q31_t) ((fcurr1 * (*pk)) >> 15U) + gnext0; + gnext1 = __SSAT(gnext1, 16); + + gnext0 = (q31_t) ((fcurr0 * (*pk++)) >> 15U) + gcurr0; + gnext0 = __SSAT(gnext0, 16); + + /* Update of f values for next coefficient set processing */ + fcurr0 = fnext0; + fcurr1 = fnext1; + fcurr2 = fnext2; + fcurr3 = fnext3; + + stageCnt--; + } + + /* The results in the 4 accumulators, store in the destination buffer. */ + /* y(n) = fN(n) */ + + write_q15x2_ia (&pDst, __PKHBT(fcurr0, fcurr1, 16)); + write_q15x2_ia (&pDst, __PKHBT(fcurr2, fcurr3, 16)); + + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* f0(n) = x(n) */ + fcurr0 = *pSrc++; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coeff pointer */ + pk = pCoeffs; + + /* read g2(n) from state buffer */ + gcurr0 = *px; + + /* for sample 1 processing */ + /* f1(n) = f0(n) + K1 * g0(n-1) */ + fnext0 = (((q31_t) gcurr0 * (*pk)) >> 15U) + fcurr0; + fnext0 = __SSAT(fnext0, 16); + + /* g1(n) = f0(n) * K1 + g0(n-1) */ + gnext0 = (((q31_t) fcurr0 * (*pk++)) >> 15U) + gcurr0; + gnext0 = __SSAT(gnext0, 16); + + /* save g1(n) in state buffer */ + *px++ = (q15_t) fcurr0; + + /* f1(n) is saved in fcurr0 for next stage processing */ + fcurr0 = fnext0; + + stageCnt = (numStages - 1U); + + /* stage loop */ + while (stageCnt > 0U) + { + /* read g2(n) from state buffer */ + gcurr0 = *px; + + /* save g1(n) in state buffer */ + *px++ = (q15_t) gnext0; + + /* Sample processing for K2, K3.... */ + /* f2(n) = f1(n) + K2 * g1(n-1) */ + fnext0 = (((q31_t) gcurr0 * (*pk)) >> 15U) + fcurr0; + fnext0 = __SSAT(fnext0, 16); + + /* g2(n) = f1(n) * K2 + g1(n-1) */ + gnext0 = (((q31_t) fcurr0 * (*pk++)) >> 15U) + gcurr0; + gnext0 = __SSAT(gnext0, 16); + + /* f1(n) is saved in fcurr0 for next stage processing */ + fcurr0 = fnext0; + + stageCnt--; + } + + /* y(n) = fN(n) */ + *pDst++ = __SSAT(fcurr0, 16); + + blkCnt--; + } + + +} + +/** + @} end of FIR_Lattice group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_lattice_q31.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_lattice_q31.c new file mode 100644 index 00000000..6247a999 --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_lattice_q31.c @@ -0,0 +1,438 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_fir_lattice_q31.c + * Description: Q31 FIR lattice filter processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Lattice + @{ + */ + +/** + @brief Processing function for the Q31 FIR lattice filter. + @param[in] S points to an instance of the Q31 FIR lattice structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + In order to avoid overflows the input signal must be scaled down by 2*log2(numStages) bits. + */ + +void riscv_fir_lattice_q31( + const riscv_fir_lattice_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + q31_t *pState = S->pState; /* State pointer */ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *px; /* Temporary state pointer */ + const q31_t *pk; /* Temporary coefficient pointer */ + uint32_t numStages = S->numStages; /* Number of stages in the filter */ + uint32_t blkCnt, stageCnt; /* Loop counters */ + q31_t fcurr0, fnext0, gnext0, gcurr0; /* Temporary variables */ + + + +#if defined (RISCV_MATH_LOOPUNROLL) + q31_t fcurr1, fnext1, gnext1; /* Temporary variables for second sample in loop unrolling */ + q31_t fcurr2, fnext2, gnext2; /* Temporary variables for third sample in loop unrolling */ + q31_t fcurr3, fnext3, gnext3; /* Temporary variables for fourth sample in loop unrolling */ +#endif + + gcurr0 = 0; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Read two samples from input buffer */ + /* f0(n) = x(n) */ + fcurr0 = *pSrc++; + fcurr1 = *pSrc++; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coeff pointer */ + pk = pCoeffs; + + /* Read g0(n-1) from state buffer */ + gcurr0 = *px; + + /* Process first sample for first tap */ + /* f1(n) = f0(n) + K1 * g0(n-1) */ + fnext0 = (q31_t) (((q63_t) gcurr0 * (*pk)) >> 32U); + fnext0 = (fnext0 << 1U) + fcurr0; + + /* g1(n) = f0(n) * K1 + g0(n-1) */ + gnext0 = (q31_t) (((q63_t) fcurr0 * (*pk)) >> 32U); + gnext0 = (gnext0 << 1U) + gcurr0; + + /* Process second sample for first tap */ + fnext1 = (q31_t) (((q63_t) fcurr0 * (*pk)) >> 32U); + fnext1 = (fnext1 << 1U) + fcurr1; + gnext1 = (q31_t) (((q63_t) fcurr1 * (*pk)) >> 32U); + gnext1 = (gnext1 << 1U) + fcurr0; + + /* Read next two samples from input buffer */ + /* f0(n+2) = x(n+2) */ + fcurr2 = *pSrc++; + fcurr3 = *pSrc++; + + /* Process third sample for first tap */ + fnext2 = (q31_t) (((q63_t) fcurr1 * (*pk)) >> 32U); + fnext2 = (fnext2 << 1U) + fcurr2; + gnext2 = (q31_t) (((q63_t) fcurr2 * (*pk)) >> 32U); + gnext2 = (gnext2 << 1U) + fcurr1; + + /* Process fourth sample for first tap */ + fnext3 = (q31_t) (((q63_t) fcurr2 * (*pk )) >> 32U); + fnext3 = (fnext3 << 1U) + fcurr3; + gnext3 = (q31_t) (((q63_t) fcurr3 * (*pk++)) >> 32U); + gnext3 = (gnext3 << 1U) + fcurr2; + + /* Copy only last input sample into the state buffer + which will be used for next samples processing */ + *px++ = fcurr3; + + /* Update of f values for next coefficient set processing */ + fcurr0 = fnext0; + fcurr1 = fnext1; + fcurr2 = fnext2; + fcurr3 = fnext3; + + /* Loop unrolling. Process 4 taps at a time . */ + stageCnt = (numStages - 1U) >> 2U; + + /* Loop over the number of taps. Unroll by a factor of 4. + Repeat until we've computed numStages-3 coefficients. */ + + /* Process 2nd, 3rd, 4th and 5th taps ... here */ + while (stageCnt > 0U) + { + /* Read g1(n-1), g3(n-1) .... from state */ + gcurr0 = *px; + + /* save g1(n) in state buffer */ + *px++ = gnext3; + + /* Process first sample for 2nd, 6th .. tap */ + /* Sample processing for K2, K6.... */ + /* f1(n) = f0(n) + K1 * g0(n-1) */ + fnext0 = (q31_t) (((q63_t) gcurr0 * (*pk)) >> 32U); + fnext0 = (fnext0 << 1U) + fcurr0; + + /* Process second sample for 2nd, 6th .. tap */ + /* for sample 2 processing */ + fnext1 = (q31_t) (((q63_t) gnext0 * (*pk)) >> 32U); + fnext1 = (fnext1 << 1U) + fcurr1; + + /* Process third sample for 2nd, 6th .. tap */ + fnext2 = (q31_t) (((q63_t) gnext1 * (*pk)) >> 32U); + fnext2 = (fnext2 << 1U) + fcurr2; + + /* Process fourth sample for 2nd, 6th .. tap */ + fnext3 = (q31_t) (((q63_t) gnext2 * (*pk)) >> 32U); + fnext3 = (fnext3 << 1U) + fcurr3; + + /* g1(n) = f0(n) * K1 + g0(n-1) */ + /* Calculation of state values for next stage */ + gnext3 = (q31_t) (((q63_t) fcurr3 * (*pk)) >> 32U); + gnext3 = (gnext3 << 1U) + gnext2; + + gnext2 = (q31_t) (((q63_t) fcurr2 * (*pk)) >> 32U); + gnext2 = (gnext2 << 1U) + gnext1; + + gnext1 = (q31_t) (((q63_t) fcurr1 * (*pk)) >> 32U); + gnext1 = (gnext1 << 1U) + gnext0; + + gnext0 = (q31_t) (((q63_t) fcurr0 * (*pk++)) >> 32U); + gnext0 = (gnext0 << 1U) + gcurr0; + + + /* Read g2(n-1), g4(n-1) .... from state */ + gcurr0 = *px; + + /* save g1(n) in state buffer */ + *px++ = gnext3; + + /* Sample processing for K3, K7.... */ + /* Process first sample for 3rd, 7th .. tap */ + /* f3(n) = f2(n) + K3 * g2(n-1) */ + fcurr0 = (q31_t) (((q63_t) gcurr0 * (*pk)) >> 32U); + fcurr0 = (fcurr0 << 1U) + fnext0; + + /* Process second sample for 3rd, 7th .. tap */ + fcurr1 = (q31_t) (((q63_t) gnext0 * (*pk)) >> 32U); + fcurr1 = (fcurr1 << 1U) + fnext1; + + /* Process third sample for 3rd, 7th .. tap */ + fcurr2 = (q31_t) (((q63_t) gnext1 * (*pk)) >> 32U); + fcurr2 = (fcurr2 << 1U) + fnext2; + + /* Process fourth sample for 3rd, 7th .. tap */ + fcurr3 = (q31_t) (((q63_t) gnext2 * (*pk)) >> 32U); + fcurr3 = (fcurr3 << 1U) + fnext3; + + /* Calculation of state values for next stage */ + /* g3(n) = f2(n) * K3 + g2(n-1) */ + gnext3 = (q31_t) (((q63_t) fnext3 * (*pk)) >> 32U); + gnext3 = (gnext3 << 1U) + gnext2; + + gnext2 = (q31_t) (((q63_t) fnext2 * (*pk)) >> 32U); + gnext2 = (gnext2 << 1U) + gnext1; + + gnext1 = (q31_t) (((q63_t) fnext1 * (*pk)) >> 32U); + gnext1 = (gnext1 << 1U) + gnext0; + + gnext0 = (q31_t) (((q63_t) fnext0 * (*pk++)) >> 32U); + gnext0 = (gnext0 << 1U) + gcurr0; + + /* Read g1(n-1), g3(n-1) .... from state */ + gcurr0 = *px; + + /* save g1(n) in state buffer */ + *px++ = gnext3; + + /* Sample processing for K4, K8.... */ + /* Process first sample for 4th, 8th .. tap */ + /* f4(n) = f3(n) + K4 * g3(n-1) */ + fnext0 = (q31_t) (((q63_t) gcurr0 * (*pk)) >> 32U); + fnext0 = (fnext0 << 1U) + fcurr0; + + /* Process second sample for 4th, 8th .. tap */ + /* for sample 2 processing */ + fnext1 = (q31_t) (((q63_t) gnext0 * (*pk)) >> 32U); + fnext1 = (fnext1 << 1U) + fcurr1; + + /* Process third sample for 4th, 8th .. tap */ + fnext2 = (q31_t) (((q63_t) gnext1 * (*pk)) >> 32U); + fnext2 = (fnext2 << 1U) + fcurr2; + + /* Process fourth sample for 4th, 8th .. tap */ + fnext3 = (q31_t) (((q63_t) gnext2 * (*pk)) >> 32U); + fnext3 = (fnext3 << 1U) + fcurr3; + + /* g4(n) = f3(n) * K4 + g3(n-1) */ + /* Calculation of state values for next stage */ + gnext3 = (q31_t) (((q63_t) fcurr3 * (*pk)) >> 32U); + gnext3 = (gnext3 << 1U) + gnext2; + + gnext2 = (q31_t) (((q63_t) fcurr2 * (*pk)) >> 32U); + gnext2 = (gnext2 << 1U) + gnext1; + + gnext1 = (q31_t) (((q63_t) fcurr1 * (*pk)) >> 32U); + gnext1 = (gnext1 << 1U) + gnext0; + + gnext0 = (q31_t) (((q63_t) fcurr0 * (*pk++)) >> 32U); + gnext0 = (gnext0 << 1U) + gcurr0; + + /* Read g2(n-1), g4(n-1) .... from state */ + gcurr0 = *px; + + /* save g4(n) in state buffer */ + *px++ = gnext3; + + /* Sample processing for K5, K9.... */ + /* Process first sample for 5th, 9th .. tap */ + /* f5(n) = f4(n) + K5 * g4(n-1) */ + fcurr0 = (q31_t) (((q63_t) gcurr0 * (*pk)) >> 32U); + fcurr0 = (fcurr0 << 1U) + fnext0; + + /* Process second sample for 5th, 9th .. tap */ + fcurr1 = (q31_t) (((q63_t) gnext0 * (*pk)) >> 32U); + fcurr1 = (fcurr1 << 1U) + fnext1; + + /* Process third sample for 5th, 9th .. tap */ + fcurr2 = (q31_t) (((q63_t) gnext1 * (*pk)) >> 32U); + fcurr2 = (fcurr2 << 1U) + fnext2; + + /* Process fourth sample for 5th, 9th .. tap */ + fcurr3 = (q31_t) (((q63_t) gnext2 * (*pk)) >> 32U); + fcurr3 = (fcurr3 << 1U) + fnext3; + + /* Calculation of state values for next stage */ + /* g5(n) = f4(n) * K5 + g4(n-1) */ + gnext3 = (q31_t) (((q63_t) fnext3 * (*pk)) >> 32U); + gnext3 = (gnext3 << 1U) + gnext2; + + gnext2 = (q31_t) (((q63_t) fnext2 * (*pk)) >> 32U); + gnext2 = (gnext2 << 1U) + gnext1; + + gnext1 = (q31_t) (((q63_t) fnext1 * (*pk)) >> 32U); + gnext1 = (gnext1 << 1U) + gnext0; + + gnext0 = (q31_t) (((q63_t) fnext0 * (*pk++)) >> 32U); + gnext0 = (gnext0 << 1U) + gcurr0; + + stageCnt--; + } + + /* If the (filter length -1) is not a multiple of 4, compute the remaining filter taps */ + stageCnt = (numStages - 1U) % 0x4U; + + while (stageCnt > 0U) + { + gcurr0 = *px; + + /* save g value in state buffer */ + *px++ = gnext3; + + /* Process four samples for last three taps here */ + fnext0 = (q31_t) (((q63_t) gcurr0 * (*pk)) >> 32U); + fnext0 = (fnext0 << 1U) + fcurr0; + + fnext1 = (q31_t) (((q63_t) gnext0 * (*pk)) >> 32U); + fnext1 = (fnext1 << 1U) + fcurr1; + + fnext2 = (q31_t) (((q63_t) gnext1 * (*pk)) >> 32U); + fnext2 = (fnext2 << 1U) + fcurr2; + + fnext3 = (q31_t) (((q63_t) gnext2 * (*pk)) >> 32U); + fnext3 = (fnext3 << 1U) + fcurr3; + + /* g1(n) = f0(n) * K1 + g0(n-1) */ + gnext3 = (q31_t) (((q63_t) fcurr3 * (*pk)) >> 32U); + gnext3 = (gnext3 << 1U) + gnext2; + + gnext2 = (q31_t) (((q63_t) fcurr2 * (*pk)) >> 32U); + gnext2 = (gnext2 << 1U) + gnext1; + + gnext1 = (q31_t) (((q63_t) fcurr1 * (*pk)) >> 32U); + gnext1 = (gnext1 << 1U) + gnext0; + + gnext0 = (q31_t) (((q63_t) fcurr0 * (*pk++)) >> 32U); + gnext0 = (gnext0 << 1U) + gcurr0; + + /* Update of f values for next coefficient set processing */ + fcurr0 = fnext0; + fcurr1 = fnext1; + fcurr2 = fnext2; + fcurr3 = fnext3; + + stageCnt--; + } + + /* The results in the 4 accumulators, store in the destination buffer. */ + /* y(n) = fN(n) */ + *pDst++ = fcurr0; + *pDst++ = fcurr1; + *pDst++ = fcurr2; + *pDst++ = fcurr3; + + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* f0(n) = x(n) */ + fcurr0 = *pSrc++; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coeff pointer */ + pk = pCoeffs; + + /* read g2(n) from state buffer */ + gcurr0 = *px; + + /* for sample 1 processing */ + /* f1(n) = f0(n) + K1 * g0(n-1) */ + fnext0 = (q31_t) (((q63_t) gcurr0 * (*pk)) >> 32U); + fnext0 = (fnext0 << 1U) + fcurr0; + + /* g1(n) = f0(n) * K1 + g0(n-1) */ + gnext0 = (q31_t) (((q63_t) fcurr0 * (*pk++)) >> 32U); + gnext0 = (gnext0 << 1U) + gcurr0; + + /* save g1(n) in state buffer */ + *px++ = fcurr0; + + /* f1(n) is saved in fcurr0 for next stage processing */ + fcurr0 = fnext0; + + stageCnt = (numStages - 1U); + + /* stage loop */ + while (stageCnt > 0U) + { + /* read g2(n) from state buffer */ + gcurr0 = *px; + + /* save g1(n) in state buffer */ + *px++ = gnext0; + + /* Sample processing for K2, K3.... */ + /* f2(n) = f1(n) + K2 * g1(n-1) */ + fnext0 = (q31_t) (((q63_t) gcurr0 * (*pk)) >> 32U); + fnext0 = (fnext0 << 1U) + fcurr0; + + /* g2(n) = f1(n) * K2 + g1(n-1) */ + gnext0 = (q31_t) (((q63_t) fcurr0 * (*pk++)) >> 32U); + gnext0 = (gnext0 << 1U) + gcurr0; + + /* f1(n) is saved in fcurr0 for next stage processing */ + fcurr0 = fnext0; + + stageCnt--; + } + + /* y(n) = fN(n) */ + *pDst++ = fcurr0; + + blkCnt--; + } + + +} + +/** + @} end of FIR_Lattice group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_q15.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_q15.c new file mode 100644 index 00000000..14722c2c --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_q15.c @@ -0,0 +1,328 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_fir_q15.c + * Description: Q15 FIR filter processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR + @{ + */ + +/** + @brief Processing function for the Q15 FIR filter. + @param[in] S points to an instance of the Q15 FIR filter structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + Lastly, the accumulator is saturated to yield a result in 1.15 format. + + @remark + Refer to \ref riscv_fir_fast_q15() for a faster but less precise implementation of this function. + */ +void riscv_fir_q15( + const riscv_fir_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCurnt; /* Points to the current sample of the state */ + q15_t *px; /* Temporary pointer for state buffer */ + const q15_t *pb; /* Temporary pointer for coefficient buffer */ + q63_t acc0; /* Accumulators */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t tapCnt, blkCnt; /* Loop counters */ + +#if defined (RISCV_MATH_LOOPUNROLL) + q63_t acc1, acc2, acc3; /* Accumulators */ + q31_t x0, x1, x2, c0; /* Temporary variables to hold state and coefficient values */ +#endif + + /* S->pState points to state array which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + +#if defined (RISCV_MATH_LOOPUNROLL) && !defined (RISCV_VECTOR) + + /* Loop unrolling: Compute 4 output values simultaneously. + * The variables acc0 ... acc3 hold output values that are being computed: + * + * acc0 = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] + * acc1 = b[numTaps-1] * x[n-numTaps] + b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1] + * acc2 = b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] + b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2] + * acc3 = b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps] +...+ b[0] * x[3] + */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Copy 4 new input samples into the state buffer. */ + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Typecast q15_t pointer to q31_t pointer for state reading in q31_t */ + px = pState; + + /* Typecast q15_t pointer to q31_t pointer for coefficient reading in q31_t */ + pb = pCoeffs; + + /* Read the first two samples from the state buffer: x[n-N], x[n-N-1] */ + x0 = read_q15x2_ia (&px); + + /* Read the third and forth samples from the state buffer: x[n-N-2], x[n-N-3] */ + x2 = read_q15x2_ia (&px); + + /* Loop over the number of taps. Unroll by a factor of 4. + Repeat until we've computed numTaps-(numTaps%4) coefficients. */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Read the first two coefficients using SIMD: b[N] and b[N-1] coefficients */ + c0 = read_q15x2_ia ((q15_t **) &pb); + + /* acc0 += b[N] * x[n-N] + b[N-1] * x[n-N-1] */ + acc0 = __SMLALD(x0, c0, acc0); + + /* acc2 += b[N] * x[n-N-2] + b[N-1] * x[n-N-3] */ + acc2 = __SMLALD(x2, c0, acc2); + + /* pack x[n-N-1] and x[n-N-2] */ + x1 = __PKHBT(x2, x0, 0); + + /* Read state x[n-N-4], x[n-N-5] */ + x0 = read_q15x2_ia (&px); + + /* acc1 += b[N] * x[n-N-1] + b[N-1] * x[n-N-2] */ + acc1 = __SMLALDX(x1, c0, acc1); + + /* pack x[n-N-3] and x[n-N-4] */ + x1 = __PKHBT(x0, x2, 0); + + /* acc3 += b[N] * x[n-N-3] + b[N-1] * x[n-N-4] */ + acc3 = __SMLALDX(x1, c0, acc3); + + /* Read coefficients b[N-2], b[N-3] */ + c0 = read_q15x2_ia ((q15_t **) &pb); + + /* acc0 += b[N-2] * x[n-N-2] + b[N-3] * x[n-N-3] */ + acc0 = __SMLALD(x2, c0, acc0); + + /* Read state x[n-N-6], x[n-N-7] with offset */ + x2 = read_q15x2_ia (&px); + + /* acc2 += b[N-2] * x[n-N-4] + b[N-3] * x[n-N-5] */ + acc2 = __SMLALD(x0, c0, acc2); + + /* acc1 += b[N-2] * x[n-N-3] + b[N-3] * x[n-N-4] */ + acc1 = __SMLALDX(x1, c0, acc1); + + /* pack x[n-N-5] and x[n-N-6] */ + x1 = __PKHBT(x2, x0, 0); + + /* acc3 += b[N-2] * x[n-N-5] + b[N-3] * x[n-N-6] */ + acc3 = __SMLALDX(x1, c0, acc3); + + /* Decrement tap count */ + tapCnt--; + } + + /* If the filter length is not a multiple of 4, compute the remaining filter taps. + This is always be 2 taps since the filter length is even. */ + if ((numTaps & 0x3U) != 0U) + { + /* Read last two coefficients */ + c0 = read_q15x2_ia ((q15_t **) &pb); + + /* Perform the multiply-accumulates */ + acc0 = __SMLALD(x0, c0, acc0); + acc2 = __SMLALD(x2, c0, acc2); + + /* pack state variables */ + x1 = __PKHBT(x2, x0, 0); + + /* Read last state variables */ + x0 = read_q15x2 (px); + + /* Perform the multiply-accumulates */ + acc1 = __SMLALDX(x1, c0, acc1); + + /* pack state variables */ + x1 = __PKHBT(x0, x2, 0); + + /* Perform the multiply-accumulates */ + acc3 = __SMLALDX(x1, c0, acc3); + } + + /* The results in the 4 accumulators are in 2.30 format. Convert to 1.15 with saturation. + Then store the 4 outputs in the destination buffer. */ +#if __RISCV_XLEN == 64 + write_q15x4_ia (&pDst, __RV_PKBB32(__PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16),__PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16))); +#else + write_q15x2_ia (&pDst, __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16)); + write_q15x2_ia (&pDst, __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16)); +#endif /* __RISCV_XLEN == 64 */ + + /* Advance the state pointer by 4 to process the next group of 4 samples */ + pState = pState + 4U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining output samples */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of taps */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Copy two samples into state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Set the accumulator to zero */ + acc0 = 0; + + /* Use SIMD to hold states and coefficients */ + px = pState; + pb = pCoeffs; +#if defined (RISCV_VECTOR) + uint32_t vblkCnt = numTaps; /* Loop counter */ + size_t l; + vint16m4_t vx,vy; + vint64m1_t temp00m1,temp01m1,accm1; + l = vsetvl_e64m1(1); + temp00m1 = vmv_v_x_i64m1(0, l); + temp01m1 = vmv_v_x_i64m1(0, l); + + for (; (l = vsetvl_e16m4(vblkCnt)) > 0; vblkCnt -= l) { + vx = vle16_v_i16m4(px, l); + px += l; + vy = vle16_v_i16m4(pb, l); + pb += l; + accm1 = vwredsum_vs_i32m8_i64m1 ( temp00m1,vwmul_vv_i32m8(vx, vy, l), temp01m1, l); + acc0 +=vmv_x_s_i64m1_i64(accm1); + } +#else + tapCnt = numTaps >> 1U; + + while (tapCnt > 0U) + { + acc0 += (q31_t) *px++ * *pb++; + acc0 += (q31_t) *px++ * *pb++; + + tapCnt--; + } +#endif /* defined (RISCV_VECTOR) */ + + /* The result is in 2.30 format. Convert to 1.15 with saturation. + Then store the output in the destination buffer. */ + *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16)); + + /* Advance state pointer by 1 for the next sample */ + pState = pState + 1U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the start of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = (numTaps - 1U) >> 2U; + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Calculate remaining number of copies */ + tapCnt = (numTaps - 1U) % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = (numTaps - 1U); + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + /* Copy remaining data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +} + +/** + @} end of FIR group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_q31.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_q31.c new file mode 100644 index 00000000..3ee152a7 --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_q31.c @@ -0,0 +1,321 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_fir_q31.c + * Description: Q31 FIR filter processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR + @{ + */ + +/** + @brief Processing function for Q31 FIR filter. + @param[in] S points to an instance of the Q31 FIR filter structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + Thus, if the accumulator result overflows it wraps around rather than clip. + In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits. + After all multiply-accumulates are performed, the 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result. + + @remark + Refer to \ref riscv_fir_fast_q31() for a faster but less precise implementation of this filter. + */ +void riscv_fir_q31( + const riscv_fir_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + q31_t *pState = S->pState; /* State pointer */ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *pStateCurnt; /* Points to the current sample of the state */ + q31_t *px; /* Temporary pointer for state buffer */ + const q31_t *pb; /* Temporary pointer for coefficient buffer */ + q63_t acc0; /* Accumulator */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i, tapCnt, blkCnt; /* Loop counters */ + +#if defined (RISCV_MATH_LOOPUNROLL) + q63_t acc1, acc2; /* Accumulators */ + q31_t x0, x1, x2; /* Temporary variables to hold state values */ + q31_t c0; /* Temporary variable to hold coefficient value */ +#if __RISCV_XLEN == 64 + q63_t c064, x064, x164, x264; +#endif /* __RISCV_XLEN == 64 */ +#endif + + /* S->pState points to state array which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + +#if defined (RISCV_MATH_LOOPUNROLL) && !defined (RISCV_VECTOR) + + /* Loop unrolling: Compute 4 output values simultaneously. + * The variables acc0 ... acc3 hold output values that are being computed: + * + * acc0 = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] + * acc1 = b[numTaps-1] * x[n-numTaps] + b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1] + * acc2 = b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] + b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2] + * acc3 = b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps] +...+ b[0] * x[3] + */ + + blkCnt = blockSize / 3; + + while (blkCnt > 0U) + { + /* Copy 3 new input samples into the state buffer. */ + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + + /* Read the first 2 samples from the state buffer: x[n-numTaps], x[n-numTaps-1] */ + x0 = *px++; + x1 = *px++; + + /* Loop unrolling: process 3 taps at a time. */ + tapCnt = numTaps / 3; + + while (tapCnt > 0U) + { +#if __RISCV_XLEN == 64 + c064 = read_q31x2_ia ((q31_t **) &pb); + x2 = *(px++); + acc0 = __RV_KMADA32(acc0, __RV_PKBB32(x1, x0), c064); + acc1 = __RV_KMADA32(acc1, __RV_PKBB32(x2, x1), c064); + x0 = *(px++); + acc2 = __RV_KMADA32(acc2, __RV_PKBB32(x0, x2), c064); + c0 = *(pb++); + x1 = *(px++); +#else + /* Read the b[numTaps] coefficient */ + c0 = *pb; + + /* Read x[n-numTaps-2] sample */ + x2 = *(px++); + + /* Perform the multiply-accumulates */ + acc0 += ((q63_t) x0 * c0); + acc1 += ((q63_t) x1 * c0); + acc2 += ((q63_t) x2 * c0); + + /* Read the coefficient and state */ + c0 = *(pb + 1U); + x0 = *(px++); + + /* Perform the multiply-accumulates */ + acc0 += ((q63_t) x1 * c0); + acc1 += ((q63_t) x2 * c0); + acc2 += ((q63_t) x0 * c0); + + /* Read the coefficient and state */ + c0 = *(pb + 2U); + x1 = *(px++); + + /* update coefficient pointer */ + pb += 3U; +#endif /* __RISCV_XLEN == 64 */ + + /* Perform the multiply-accumulates */ + acc0 += ((q63_t) x2 * c0); + acc1 += ((q63_t) x0 * c0); + acc2 += ((q63_t) x1 * c0); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + tapCnt = numTaps % 0x3U; + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *(pb++); + + /* Fetch 1 state variable */ + x2 = *(px++); + + /* Perform the multiply-accumulates */ + acc0 += ((q63_t) x0 * c0); + acc1 += ((q63_t) x1 * c0); + acc2 += ((q63_t) x2 * c0); + + /* Reuse the present sample states for next sample */ + x0 = x1; + x1 = x2; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Advance the state pointer by 3 to process the next group of 3 samples */ + pState = pState + 3; + + /* The result is in 2.30 format. Convert to 1.31 and store in destination buffer. */ + *pDst++ = (q31_t) (acc0 >> 31U); + *pDst++ = (q31_t) (acc1 >> 31U); + *pDst++ = (q31_t) (acc2 >> 31U); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining output samples */ + blkCnt = blockSize % 0x3U; + +#else + + /* Initialize blkCnt with number of taps */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Copy one sample at a time into state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Set the accumulator to zero */ + acc0 = 0; + + /* Initialize state pointer */ + px = pState; + + /* Initialize Coefficient pointer */ + pb = pCoeffs; + + i = numTaps; +#if defined (RISCV_VECTOR) + uint32_t vblkCnt = numTaps; /* Loop counter */ + size_t l; + vint32m4_t vx,vy; + vint64m1_t temp00m1,temp01m1,accm1; + l = vsetvl_e64m1(1); + temp00m1 = vmv_v_x_i64m1(0, l); + temp01m1 = vmv_v_x_i64m1(0, l); + + for (; (l = vsetvl_e32m4(vblkCnt)) > 0; vblkCnt -= l) { + vx = vle32_v_i32m4(px, l); + px += l; + vy = vle32_v_i32m4(pb, l); + pb += l; + accm1 = vredsum_vs_i64m8_i64m1 ( temp00m1,vwmul_vv_i64m8(vx, vy, l), temp01m1, l); + acc0 +=vmv_x_s_i64m1_i64(accm1); + } +#else + /* Perform the multiply-accumulates */ + do + { + /* acc = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] */ + acc0 += (q63_t) *px++ * *pb++; + + i--; + } while (i > 0U); +#endif /* defined (RISCV_VECTOR) */ + + /* Result is in 2.62 format. Convert to 1.31 and store in destination buffer. */ + *pDst++ = (q31_t) (acc0 >> 31U); + + /* Advance state pointer by 1 for the next sample */ + pState = pState + 1U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the start of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = (numTaps - 1U) >> 2U; + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Calculate remaining number of copies */ + tapCnt = (numTaps - 1U) % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = (numTaps - 1U); + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + /* Copy remaining data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +} + +/** + @} end of FIR group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_q7.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_q7.c new file mode 100644 index 00000000..37849114 --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_q7.c @@ -0,0 +1,342 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_fir_q7.c + * Description: Q7 FIR filter processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR + @{ + */ + +/** + @brief Processing function for Q7 FIR filter. + @param[in] S points to an instance of the Q7 FIR filter structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 32-bit internal accumulator. + Both coefficients and state variables are represented in 1.7 format and multiplications yield a 2.14 result. + The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format. + There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + The accumulator is converted to 18.7 format by discarding the low 7 bits. + Finally, the result is truncated to 1.7 format. + */ + +void riscv_fir_q7( + const riscv_fir_instance_q7 * S, + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize) +{ + q7_t *pState = S->pState; /* State pointer */ + const q7_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q7_t *pStateCurnt; /* Points to the current sample of the state */ + q7_t *px; /* Temporary pointer for state buffer */ + const q7_t *pb; /* Temporary pointer for coefficient buffer */ + q31_t acc0; /* Accumulators */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i, tapCnt, blkCnt; /* Loop counters */ + +#if defined (RISCV_MATH_LOOPUNROLL) + q31_t acc1, acc2, acc3; /* Accumulators */ + q7_t x0, x1, x2, x3, c0; /* Temporary variables to hold state */ +#endif + + /* S->pState points to state array which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + +#if defined (RISCV_MATH_LOOPUNROLL) && !defined (RISCV_VECTOR) + + /* Loop unrolling: Compute 4 output values simultaneously. + * The variables acc0 ... acc3 hold output values that are being computed: + * + * acc0 = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] + * acc1 = b[numTaps-1] * x[n-numTaps] + b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1] + * acc2 = b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] + b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2] + * acc3 = b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps] +...+ b[0] * x[3] + */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Copy 4 new input samples into the state buffer. */ + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + + /* Read the first 3 samples from the state buffer: + * x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2] */ + x0 = *px++; + x1 = *px++; + x2 = *px++; + + /* Loop unrolling. Process 4 taps at a time. */ + tapCnt = numTaps >> 2U; + + /* Loop over the number of taps. Unroll by a factor of 4. + Repeat until we've computed numTaps-4 coefficients. */ + while (tapCnt > 0U) + { + /* Read the b[numTaps] coefficient */ + c0 = *pb; + + /* Read x[n-numTaps-3] sample */ + x3 = *px; + + /* acc0 += b[numTaps] * x[n-numTaps] */ + acc0 += ((q15_t) x0 * c0); + + /* acc1 += b[numTaps] * x[n-numTaps-1] */ + acc1 += ((q15_t) x1 * c0); + + /* acc2 += b[numTaps] * x[n-numTaps-2] */ + acc2 += ((q15_t) x2 * c0); + + /* acc3 += b[numTaps] * x[n-numTaps-3] */ + acc3 += ((q15_t) x3 * c0); + + /* Read the b[numTaps-1] coefficient */ + c0 = *(pb + 1U); + + /* Read x[n-numTaps-4] sample */ + x0 = *(px + 1U); + + /* Perform the multiply-accumulates */ + acc0 += ((q15_t) x1 * c0); + acc1 += ((q15_t) x2 * c0); + acc2 += ((q15_t) x3 * c0); + acc3 += ((q15_t) x0 * c0); + + /* Read the b[numTaps-2] coefficient */ + c0 = *(pb + 2U); + + /* Read x[n-numTaps-5] sample */ + x1 = *(px + 2U); + + /* Perform the multiply-accumulates */ + acc0 += ((q15_t) x2 * c0); + acc1 += ((q15_t) x3 * c0); + acc2 += ((q15_t) x0 * c0); + acc3 += ((q15_t) x1 * c0); + + /* Read the b[numTaps-3] coefficients */ + c0 = *(pb + 3U); + + /* Read x[n-numTaps-6] sample */ + x2 = *(px + 3U); + + /* Perform the multiply-accumulates */ + acc0 += ((q15_t) x3 * c0); + acc1 += ((q15_t) x0 * c0); + acc2 += ((q15_t) x1 * c0); + acc3 += ((q15_t) x2 * c0); + + /* update coefficient pointer */ + pb += 4U; + px += 4U; + + /* Decrement loop counter */ + tapCnt--; + } + + /* If the filter length is not a multiple of 4, compute the remaining filter taps */ + tapCnt = numTaps % 0x4U; + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *(pb++); + + /* Fetch 1 state variable */ + x3 = *(px++); + + /* Perform the multiply-accumulates */ + acc0 += ((q15_t) x0 * c0); + acc1 += ((q15_t) x1 * c0); + acc2 += ((q15_t) x2 * c0); + acc3 += ((q15_t) x3 * c0); + + /* Reuse the present sample states for next sample */ + x0 = x1; + x1 = x2; + x2 = x3; + + /* Decrement loop counter */ + tapCnt--; + } + + /* The results in the 4 accumulators are in 2.62 format. Convert to 1.31 + Then store the 4 outputs in the destination buffer. */ + acc0 = __SSAT((acc0 >> 7U), 8); + *pDst++ = acc0; + acc1 = __SSAT((acc1 >> 7U), 8); + *pDst++ = acc1; + acc2 = __SSAT((acc2 >> 7U), 8); + *pDst++ = acc2; + acc3 = __SSAT((acc3 >> 7U), 8); + *pDst++ = acc3; + + /* Advance the state pointer by 4 to process the next group of 4 samples */ + pState = pState + 4U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining output samples */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of taps */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Copy one sample at a time into state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Set the accumulator to zero */ + acc0 = 0; + + /* Initialize state pointer */ + px = pState; + + /* Initialize Coefficient pointer */ + pb = pCoeffs; + + i = numTaps; +#if defined (RISCV_VECTOR) + uint32_t vblkCnt = numTaps; /* Loop counter */ + size_t l; + vint16m8_t vx,vy; + vint32m1_t temp00m1,temp01m1,accm1; + l = vsetvl_e32m1(1); + temp00m1 = vmv_v_x_i32m1(0, l); + temp01m1 = vmv_v_x_i32m1(0, l); + + for (; (l = vsetvl_e8m4(vblkCnt)) > 0; vblkCnt -= l) { + vx = vwadd_vx_i16m8(vle8_v_i8m4(px, l),0, l); + px += l; + vy = vwadd_vx_i16m8(vle8_v_i8m4(pb, l),0, l); + pb += l; + accm1 = vwredsum_vs_i16m8_i32m1 ( temp00m1,vmul_vv_i16m8(vx, vy, l), temp01m1, l); + acc0 +=vmv_x_s_i32m1_i32(accm1); + } +#else + /* Perform the multiply-accumulates */ + while (i > 0U) + { + acc0 += (q15_t) * (px++) * (*(pb++)); + i--; + } +#endif /* defined (RISCV_VECTOR) */ + + /* The result is in 2.14 format. Convert to 1.7 + Then store the output in the destination buffer. */ + *pDst++ = __SSAT((acc0 >> 7U), 8); + + /* Advance state pointer by 1 for the next sample */ + pState = pState + 1U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the start of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = (numTaps - 1U) >> 2U; + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Calculate remaining number of copies */ + tapCnt = (numTaps - 1U) % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = (numTaps - 1U); + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + /* Copy remaining data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement the loop counter */ + tapCnt--; + } + +} + +/** + @} end of FIR group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_sparse_f32.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_sparse_f32.c new file mode 100644 index 00000000..6840e230 --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_sparse_f32.c @@ -0,0 +1,363 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_fir_sparse_f32.c + * Description: Floating-point sparse FIR filter processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @defgroup FIR_Sparse Finite Impulse Response (FIR) Sparse Filters + + This group of functions implements sparse FIR filters. + Sparse FIR filters are equivalent to standard FIR filters except that most of the coefficients are equal to zero. + Sparse filters are used for simulating reflections in communications and audio applications. + + There are separate functions for Q7, Q15, Q31, and floating-point data types. + The functions operate on blocks of input and output data and each call to the function processes + blockSize samples through the filter. pSrc and + pDst points to input and output arrays respectively containing blockSize values. + + @par Algorithm + The sparse filter instant structure contains an array of tap indices pTapDelay which specifies the locations of the non-zero coefficients. + This is in addition to the coefficient array b. + The implementation essentially skips the multiplications by zero and leads to an efficient realization. + 
+      y[n] = b[0] * x[n-pTapDelay[0]] + b[1] * x[n-pTapDelay[1]] + b[2] * x[n-pTapDelay[2]] + ...+ b[numTaps-1] * x[n-pTapDelay[numTaps-1]]
+
+ @par + \image html FIRSparse.png "Sparse FIR filter. b[n] represents the filter coefficients" + @par + pCoeffs points to a coefficient array of size numTaps; + pTapDelay points to an array of nonzero indices and is also of size numTaps; + pState points to a state array of size maxDelay + blockSize, where + maxDelay is the largest offset value that is ever used in the pTapDelay array. + Some of the processing functions also require temporary working buffers. + + @par Instance Structure + The coefficients and state variables for a filter are stored together in an instance data structure. + A separate instance structure must be defined for each filter. + Coefficient and offset arrays may be shared among several instances while state variable arrays cannot be shared. + There are separate instance structure declarations for each of the 4 supported data types. + + @par Initialization Functions + There is also an associated initialization function for each data type. + The initialization function performs the following operations: + - Sets the values of the internal structure fields. + - Zeros out the values in the state buffer. + To do this manually without calling the init function, assign the follow subfields of the instance structure: + numTaps, pCoeffs, pTapDelay, maxDelay, stateIndex, pState. Also set all of the values in pState to zero. + @par + Use of the initialization function is optional. + However, if the initialization function is used, then the instance structure cannot be placed into a const data section. + To place an instance structure into a const data section, the instance structure must be manually initialized. + Set the values in the state buffer to zeros before static initialization. + The code below statically initializes each of the 4 different data type filter instance structures + 
+      riscv_fir_sparse_instance_f32 S = {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};
+      riscv_fir_sparse_instance_q31 S = {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};
+      riscv_fir_sparse_instance_q15 S = {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};
+      riscv_fir_sparse_instance_q7 S =  {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};
+
+ + @par Fixed-Point Behavior + Care must be taken when using the fixed-point versions of the sparse FIR filter functions. + In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + Refer to the function specific documentation below for usage guidelines. + */ + +/** + @addtogroup FIR_Sparse + @{ + */ + +/** + @brief Processing function for the floating-point sparse FIR filter. + @param[in] S points to an instance of the floating-point sparse FIR structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] pScratchIn points to a temporary buffer of size blockSize + @param[in] blockSize number of input samples to process + @return none + */ + +void riscv_fir_sparse_f32( + riscv_fir_sparse_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + float32_t * pScratchIn, + uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *px; /* Scratch buffer pointer */ + float32_t *py = pState; /* Temporary pointers for state buffer */ + float32_t *pb = pScratchIn; /* Temporary pointers for scratch buffer */ + float32_t *pOut; /* Destination pointer */ + int32_t *pTapDelay = S->pTapDelay; /* Pointer to the array containing offset of the non-zero tap values. */ + uint32_t delaySize = S->maxDelay + blockSize; /* state length */ + uint16_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + int32_t readIndex; /* Read index of the state buffer */ + uint32_t tapCnt, blkCnt; /* loop counters */ + float32_t coeff = *pCoeffs++; /* Read the first coefficient value */ + + + /* BlockSize of Input samples are copied into the state buffer */ + /* StateIndex points to the starting position to write in the state buffer */ + riscv_circularWrite_f32((int32_t *) py, delaySize, &S->stateIndex, 1, (int32_t *) pSrc, 1, blockSize); + + /* Read Index, from where the state buffer should be read, is calculated. */ + readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) + { + readIndex += (int32_t) delaySize; + } + + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + riscv_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1, + (int32_t *) pb, (int32_t *) pb, blockSize, 1, blockSize); + + /* Working pointer for the scratch buffer of state values */ + px = pb; + + /* Working pointer for scratch buffer of output values */ + pOut = pDst; + + +#if defined (RISCV_MATH_LOOPUNROLL) && !defined (RISCV_VECTOR) + + /* Loop unrolling: Compute 4 outputs at a time. */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Perform Multiplications and store in destination buffer */ + *pOut++ = *px++ * coeff; + + *pOut++ = *px++ * coeff; + + *pOut++ = *px++ * coeff; + + *pOut++ = *px++ * coeff; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ +#if defined (RISCV_VECTOR) + uint32_t vblkCnt = blockSize; /* Loop counter */ + size_t l; + vfloat32m8_t vx, vy; + for (; (l = vsetvl_e32m8(vblkCnt)) > 0; vblkCnt -= l) { + vx = vle32_v_f32m8(px, l); + px += l; + vse32_v_f32m8 (pOut, vfmul_vf_f32m8(vx, coeff, l), l); + pOut += l; + } +#else + while (blkCnt > 0U) + { + /* Perform Multiplication and store in destination buffer */ + *pOut++ = *px++ * coeff; + + /* Decrement loop counter */ + blkCnt--; + } +#endif /* defined (RISCV_VECTOR) */ + + /* Load the coefficient value and + * increment the coefficient buffer for the next set of state values */ + coeff = *pCoeffs++; + + /* Read Index, from where the state buffer should be read, is calculated. */ + readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) + { + readIndex += (int32_t) delaySize; + } + + /* Loop over the number of taps. */ + tapCnt = (uint32_t) numTaps - 2U; + + while (tapCnt > 0U) + { + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + riscv_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1, + (int32_t *) pb, (int32_t *) pb, blockSize, 1, blockSize); + + /* Working pointer for the scratch buffer of state values */ + px = pb; + + /* Working pointer for scratch buffer of output values */ + pOut = pDst; + + +#if defined (RISCV_MATH_LOOPUNROLL) && !defined (RISCV_VECTOR) + + /* Loop unrolling: Compute 4 outputs at a time. */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + *pOut++ += *px++ * coeff; + + *pOut++ += *px++ * coeff; + + *pOut++ += *px++ * coeff; + + *pOut++ += *px++ * coeff; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ +#if defined (RISCV_VECTOR) + uint32_t vblkCnt = blockSize; /* Loop counter */ + size_t l; + vfloat32m8_t vx, vy; + for (; (l = vsetvl_e32m8(vblkCnt)) > 0; vblkCnt -= l) { + vx = vle32_v_f32m8(px, l); + px += l; + vse32_v_f32m8 (pOut,vfadd_vv_f32m8(vfmul_vf_f32m8(vx, coeff, l), vle32_v_f32m8(pOut, l), l) , l); + pOut += l; + } +#else + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + *pOut++ += *px++ * coeff; + + /* Decrement loop counter */ + blkCnt--; + } +#endif /* defined (RISCV_VECTOR) */ + /* Load the coefficient value and + * increment the coefficient buffer for the next set of state values */ + coeff = *pCoeffs++; + + /* Read Index, from where the state buffer should be read, is calculated. */ + readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) + { + readIndex += (int32_t) delaySize; + } + + /* Decrement tap loop counter */ + tapCnt--; + } + + /* Compute last tap without the final read of pTapDelay */ + + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + riscv_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1, + (int32_t *) pb, (int32_t *) pb, blockSize, 1, blockSize); + + /* Working pointer for the scratch buffer of state values */ + px = pb; + + /* Working pointer for scratch buffer of output values */ + pOut = pDst; + + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time. */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + *pOut++ += *px++ * coeff; + *pOut++ += *px++ * coeff; + *pOut++ += *px++ * coeff; + *pOut++ += *px++ * coeff; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + *pOut++ += *px++ * coeff; + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of FIR_Sparse group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_sparse_init_f32.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_sparse_init_f32.c new file mode 100644 index 00000000..23323416 --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_sparse_init_f32.c @@ -0,0 +1,94 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_fir_sparse_init_f32.c + * Description: Floating-point sparse FIR filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Sparse + @{ + */ + +/** + @brief Initialization function for the floating-point sparse FIR filter. + @param[in,out] S points to an instance of the floating-point sparse FIR structure + @param[in] numTaps number of nonzero coefficients in the filter + @param[in] pCoeffs points to the array of filter coefficients + @param[in] pState points to the state buffer + @param[in] pTapDelay points to the array of offset times + @param[in] maxDelay maximum offset time supported + @param[in] blockSize number of samples that will be processed per block + @return none + + @par Details + pCoeffs holds the filter coefficients and has length numTaps. + pState holds the filter's state variables and must be of length + maxDelay + blockSize, where maxDelay + is the maximum number of delay line values. + blockSize is the + number of samples processed by the riscv_fir_sparse_f32() function. + */ + +void riscv_fir_sparse_init_f32( + riscv_fir_sparse_instance_f32 * S, + uint16_t numTaps, + const float32_t * pCoeffs, + float32_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize) +{ + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Assign TapDelay pointer */ + S->pTapDelay = pTapDelay; + + /* Assign MaxDelay */ + S->maxDelay = maxDelay; + + /* reset the stateIndex to 0 */ + S->stateIndex = 0U; + + /* Clear state buffer and size is always maxDelay + blockSize */ + memset(pState, 0, (maxDelay + blockSize) * sizeof(float32_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of FIR_Sparse group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_sparse_init_q15.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_sparse_init_q15.c new file mode 100644 index 00000000..ff8b4d5b --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_sparse_init_q15.c @@ -0,0 +1,94 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_fir_sparse_init_q15.c + * Description: Q15 sparse FIR filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Sparse + @{ + */ + +/** + @brief Initialization function for the Q15 sparse FIR filter. + @param[in,out] S points to an instance of the Q15 sparse FIR structure + @param[in] numTaps number of nonzero coefficients in the filter + @param[in] pCoeffs points to the array of filter coefficients + @param[in] pState points to the state buffer + @param[in] pTapDelay points to the array of offset times + @param[in] maxDelay maximum offset time supported + @param[in] blockSize number of samples that will be processed per block + @return none + + @par Details + pCoeffs holds the filter coefficients and has length numTaps. + pState holds the filter's state variables and must be of length + maxDelay + blockSize, where maxDelay + is the maximum number of delay line values. + blockSize is the + number of words processed by riscv_fir_sparse_q15() function. + */ + +void riscv_fir_sparse_init_q15( + riscv_fir_sparse_instance_q15 * S, + uint16_t numTaps, + const q15_t * pCoeffs, + q15_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize) +{ + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Assign TapDelay pointer */ + S->pTapDelay = pTapDelay; + + /* Assign MaxDelay */ + S->maxDelay = maxDelay; + + /* reset the stateIndex to 0 */ + S->stateIndex = 0U; + + /* Clear state buffer and size is always maxDelay + blockSize */ + memset(pState, 0, (maxDelay + blockSize) * sizeof(q15_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of FIR_Sparse group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_sparse_init_q31.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_sparse_init_q31.c new file mode 100644 index 00000000..12b11922 --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_sparse_init_q31.c @@ -0,0 +1,93 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_fir_sparse_init_q31.c + * Description: Q31 sparse FIR filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Sparse + @{ + */ + +/** + @brief Initialization function for the Q31 sparse FIR filter. + @param[in,out] S points to an instance of the Q31 sparse FIR structure + @param[in] numTaps number of nonzero coefficients in the filter + @param[in] pCoeffs points to the array of filter coefficients + @param[in] pState points to the state buffer + @param[in] pTapDelay points to the array of offset times + @param[in] maxDelay maximum offset time supported + @param[in] blockSize number of samples that will be processed per block + @return none + + @par Details + pCoeffs holds the filter coefficients and has length numTaps. + pState holds the filter's state variables and must be of length + maxDelay + blockSize, where maxDelay + is the maximum number of delay line values. + blockSize is the number of words processed by riscv_fir_sparse_q31() function. + */ + +void riscv_fir_sparse_init_q31( + riscv_fir_sparse_instance_q31 * S, + uint16_t numTaps, + const q31_t * pCoeffs, + q31_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize) +{ + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Assign TapDelay pointer */ + S->pTapDelay = pTapDelay; + + /* Assign MaxDelay */ + S->maxDelay = maxDelay; + + /* reset the stateIndex to 0 */ + S->stateIndex = 0U; + + /* Clear state buffer and size is always maxDelay + blockSize */ + memset(pState, 0, (maxDelay + blockSize) * sizeof(q31_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of FIR_Sparse group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_sparse_init_q7.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_sparse_init_q7.c new file mode 100644 index 00000000..3723cee4 --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_sparse_init_q7.c @@ -0,0 +1,94 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_fir_sparse_init_q7.c + * Description: Q7 sparse FIR filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Sparse + @{ + */ + +/** + @brief Initialization function for the Q7 sparse FIR filter. + @param[in,out] S points to an instance of the Q7 sparse FIR structure + @param[in] numTaps number of nonzero coefficients in the filter + @param[in] pCoeffs points to the array of filter coefficients + @param[in] pState points to the state buffer + @param[in] pTapDelay points to the array of offset times + @param[in] maxDelay maximum offset time supported + @param[in] blockSize number of samples that will be processed per block + @return none + + @par Details + pCoeffs holds the filter coefficients and has length numTaps. + pState holds the filter's state variables and must be of length + maxDelay + blockSize, where maxDelay + is the maximum number of delay line values. + blockSize is the + number of samples processed by the riscv_fir_sparse_q7() function. + */ + +void riscv_fir_sparse_init_q7( + riscv_fir_sparse_instance_q7 * S, + uint16_t numTaps, + const q7_t * pCoeffs, + q7_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize) +{ + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Assign TapDelay pointer */ + S->pTapDelay = pTapDelay; + + /* Assign MaxDelay */ + S->maxDelay = maxDelay; + + /* reset the stateIndex to 0 */ + S->stateIndex = 0U; + + /* Clear state buffer and size is always maxDelay + blockSize */ + memset(pState, 0, (maxDelay + blockSize) * sizeof(q7_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of FIR_Sparse group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_sparse_q15.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_sparse_q15.c new file mode 100644 index 00000000..422f4f24 --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_sparse_q15.c @@ -0,0 +1,372 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_fir_sparse_q15.c + * Description: Q15 sparse FIR filter processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Sparse + @{ + */ + +/** + @brief Processing function for the Q15 sparse FIR filter. + @param[in] S points to an instance of the Q15 sparse FIR structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] pScratchIn points to a temporary buffer of size blockSize + @param[in] pScratchOut points to a temporary buffer of size blockSize + @param[in] blockSize number of input samples to process per call + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 32-bit accumulator. + The 1.15 x 1.15 multiplications yield a 2.30 result and these are added to a 2.30 accumulator. + Thus the full precision of the multiplications is maintained but there is only a single guard bit in the accumulator. + If the accumulator result overflows it will wrap around rather than saturate. + After all multiply-accumulates are performed, the 2.30 accumulator is truncated to 2.15 format and then saturated to 1.15 format. + In order to avoid overflows the input signal or coefficients must be scaled down by log2(numTaps) bits. + */ + +void riscv_fir_sparse_q15( + riscv_fir_sparse_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + q15_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *px; /* Temporary pointers for scratch buffer */ + q15_t *py = pState; /* Temporary pointers for state buffer */ + q15_t *pb = pScratchIn; /* Temporary pointers for scratch buffer */ + q15_t *pOut = pDst; /* Working pointer for output */ + int32_t *pTapDelay = S->pTapDelay; /* Pointer to the array containing offset of the non-zero tap values. */ + uint32_t delaySize = S->maxDelay + blockSize; /* state length */ + uint16_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + int32_t readIndex; /* Read index of the state buffer */ + uint32_t tapCnt, blkCnt; /* loop counters */ + q31_t *pScr2 = pScratchOut; /* Working pointer for scratch buffer of output values */ + q15_t coeff = *pCoeffs++; /* Read the first coefficient value */ + +#if defined (RISCV_MATH_LOOPUNROLL) + q31_t in1, in2; /* Temporary variables */ +#if __RISCV_XLEN == 64 + q63_t temp; +#endif /* __RISCV_XLEN == 64 */ +#endif + + /* BlockSize of Input samples are copied into the state buffer */ + /* StateIndex points to the starting position to write in the state buffer */ + riscv_circularWrite_q15(py, (int32_t) delaySize, &S->stateIndex, 1,pSrc, 1, blockSize); + + /* Loop over the number of taps. */ + tapCnt = numTaps; + + /* Read Index, from where the state buffer should be read, is calculated. */ + readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) + { + readIndex += (int32_t) delaySize; + } + + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + riscv_circularRead_q15(py, (int32_t) delaySize, &readIndex, 1, + pb, pb, (int32_t) blockSize, 1, blockSize); + + /* Working pointer for the scratch buffer of state values */ + px = pb; + + /* Working pointer for scratch buffer of output values */ + pScratchOut = pScr2; + + +#if defined (RISCV_MATH_LOOPUNROLL) && !defined (RISCV_VECTOR) + + /* Loop unrolling: Compute 4 outputs at a time. */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { +#if __RISCV_XLEN == 64 + temp = (((q63_t)coeff) << 16) | ((uint64_t)((uint16_t)coeff)); +// // temp = __RV_PKBB16(coeff, coeff); + write_q31x2_ia (&pScratchOut, __RV_SMUL16(read_q15x2_ia(&px), (q31_t)temp)); + write_q31x2_ia (&pScratchOut, __RV_SMUL16(read_q15x2_ia(&px), (q31_t)temp)); +#else + /* Perform multiplication and store in the scratch buffer */ + *pScratchOut++ = ((q31_t) *px++ * coeff); + *pScratchOut++ = ((q31_t) *px++ * coeff); + *pScratchOut++ = ((q31_t) *px++ * coeff); + *pScratchOut++ = ((q31_t) *px++ * coeff); +#endif /* __RISCV_XLEN == 64 */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ +#if defined (RISCV_VECTOR) + uint32_t vblkCnt = blockSize; + size_t l; + vint16m4_t vx; + for (; (l = vsetvl_e16m4(vblkCnt)) > 0; vblkCnt -= l) { + vx = vle16_v_i16m4(px, l); + px += l; + vse32_v_i32m8 (pScratchOut,vwmul_vx_i32m8(vx, coeff, l), l); + pScratchOut += l; + } +#else + while (blkCnt > 0U) + { + /* Perform Multiplication and store in the scratch buffer */ + *pScratchOut++ = ((q31_t) *px++ * coeff); + + /* Decrement loop counter */ + blkCnt--; + } +#endif /* defined (RISCV_VECTOR) */ + /* Load the coefficient value and + * increment the coefficient buffer for the next set of state values */ + coeff = *pCoeffs++; + + /* Read Index, from where the state buffer should be read, is calculated. */ + readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) + { + readIndex += (int32_t) delaySize; + } + + /* Loop over the number of taps. */ + tapCnt = (uint32_t) numTaps - 2U; + + while (tapCnt > 0U) + { + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + riscv_circularRead_q15(py, (int32_t) delaySize, &readIndex, 1, + pb, pb, (int32_t) blockSize, 1, blockSize); + + /* Working pointer for the scratch buffer of state values */ + px = pb; + + /* Working pointer for scratch buffer of output values */ + pScratchOut = pScr2; + + +#if defined (RISCV_MATH_LOOPUNROLL) && !defined (RISCV_VECTOR) + + /* Loop unrolling: Compute 4 outputs at a time. */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + *pScratchOut++ += (q31_t) *px++ * coeff; + *pScratchOut++ += (q31_t) *px++ * coeff; + *pScratchOut++ += (q31_t) *px++ * coeff; + *pScratchOut++ += (q31_t) *px++ * coeff; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ +#if defined (RISCV_VECTOR) + vblkCnt = blockSize; + for (; (l = vsetvl_e16m4(vblkCnt)) > 0; vblkCnt -= l) { + vx = vle16_v_i16m4(px, l); + px += l; + vse32_v_i32m8 (pScratchOut,vadd_vv_i32m8(vle32_v_i32m8(pScratchOut, l), vwmul_vx_i32m8(vx, coeff, l), l), l); + pScratchOut += l; + } +#else + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + *pScratchOut++ += (q31_t) *px++ * coeff; + + /* Decrement loop counter */ + blkCnt--; + } +#endif /* defined (RISCV_VECTOR) */ + + /* Load the coefficient value and + * increment the coefficient buffer for the next set of state values */ + coeff = *pCoeffs++; + + /* Read Index, from where the state buffer should be read, is calculated. */ + readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) + { + readIndex += (int32_t) delaySize; + } + + /* Decrement loop counter */ + tapCnt--; + } + + /* Compute last tap without the final read of pTapDelay */ + + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + riscv_circularRead_q15(py, (int32_t) delaySize, &readIndex, 1, + pb, pb, (int32_t) blockSize, 1, blockSize); + + /* Working pointer for the scratch buffer of state values */ + px = pb; + + /* Working pointer for scratch buffer of output values */ + pScratchOut = pScr2; + + +#if defined (RISCV_MATH_LOOPUNROLL) && !defined (RISCV_VECTOR) + + /* Loop unrolling: Compute 4 outputs at a time. */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + *pScratchOut++ += (q31_t) *px++ * coeff; + *pScratchOut++ += (q31_t) *px++ * coeff; + *pScratchOut++ += (q31_t) *px++ * coeff; + *pScratchOut++ += (q31_t) *px++ * coeff; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ +#if defined (RISCV_VECTOR) + vblkCnt = blockSize; + for (; (l = vsetvl_e16m4(vblkCnt)) > 0; vblkCnt -= l) { + vx = vle16_v_i16m4(px, l); + px += l; + vse32_v_i32m8 (pScratchOut,vadd_vv_i32m8(vle32_v_i32m8(pScratchOut, l), vwmul_vx_i32m8(vx, coeff, l), l), l); + pScratchOut += l; + } +#else + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + *pScratchOut++ += (q31_t) *px++ * coeff; + + /* Decrement loop counter */ + blkCnt--; + } +#endif /* defined (RISCV_VECTOR) */ + + /* All the output values are in pScratchOut buffer. + Convert them into 1.15 format, saturate and store in the destination buffer. */ +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time. */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + in1 = *pScr2++; + in2 = *pScr2++; + + write_q15x2_ia (&pOut, __PKHBT((q15_t) __SSAT(in1 >> 15, 16), (q15_t) __SSAT(in2 >> 15, 16), 16)); + + in1 = *pScr2++; + in2 = *pScr2++; + + write_q15x2_ia (&pOut, __PKHBT((q15_t) __SSAT(in1 >> 15, 16), (q15_t) __SSAT(in2 >> 15, 16), 16)); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + *pOut++ = (q15_t) __SSAT(*pScr2++ >> 15, 16); + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of FIR_Sparse group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_sparse_q31.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_sparse_q31.c new file mode 100644 index 00000000..819ac74b --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_sparse_q31.c @@ -0,0 +1,394 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_fir_sparse_q31.c + * Description: Q31 sparse FIR filter processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Sparse + @{ + */ + +/** + @brief Processing function for the Q31 sparse FIR filter. + @param[in] S points to an instance of the Q31 sparse FIR structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] pScratchIn points to a temporary buffer of size blockSize + @param[in] blockSize number of input samples to process + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 32-bit accumulator. + The 1.31 x 1.31 multiplications are truncated to 2.30 format. + This leads to loss of precision on the intermediate multiplications and provides only a single guard bit. + If the accumulator result overflows, it wraps around rather than saturate. + In order to avoid overflows the input signal or coefficients must be scaled down by log2(numTaps) bits. + */ + +void riscv_fir_sparse_q31( + riscv_fir_sparse_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + q31_t * pScratchIn, + uint32_t blockSize) +{ + q31_t *pState = S->pState; /* State pointer */ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *px; /* Scratch buffer pointer */ + q31_t *py = pState; /* Temporary pointers for state buffer */ + q31_t *pb = pScratchIn; /* Temporary pointers for scratch buffer */ + q31_t *pOut; /* Destination pointer */ + int32_t *pTapDelay = S->pTapDelay; /* Pointer to the array containing offset of the non-zero tap values. */ + uint32_t delaySize = S->maxDelay + blockSize; /* state length */ + uint16_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + int32_t readIndex; /* Read index of the state buffer */ + uint32_t tapCnt, blkCnt; /* loop counters */ + q31_t coeff = *pCoeffs++; /* Read the first coefficient value */ + q31_t in; + q63_t out; /* Temporary output variable */ + +#if __RISCV_XLEN == 64 + q63_t temp; +#endif /* __RISCV_XLEN == 64 */ + /* BlockSize of Input samples are copied into the state buffer */ + /* StateIndex points to the starting position to write in the state buffer */ + riscv_circularWrite_f32((int32_t *) py, delaySize, &S->stateIndex, 1, + (int32_t *) pSrc, 1, blockSize); + + /* Read Index, from where the state buffer should be read, is calculated. */ + readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) + { + readIndex += (int32_t) delaySize; + } + + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + riscv_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1, + (int32_t *) pb, (int32_t *) pb, blockSize, 1, blockSize); + + /* Working pointer for the scratch buffer of state values */ + px = pb; + + /* Working pointer for scratch buffer of output values */ + pOut = pDst; + + +#if defined (RISCV_MATH_LOOPUNROLL) && !defined (RISCV_VECTOR) + + /* Loop unrolling: Compute 4 outputs at a time. */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { +#if __RISCV_XLEN == 64 + temp = read_q31x2_ia((q63_t) &px); + write_q31x2_ia (&pOut, __RV_PKBB32((__RV_SMBT32(coeff, temp) >> 32), (__RV_SMBB32(temp, coeff) >> 32))); + temp = read_q31x2_ia((q63_t) &px); + write_q31x2_ia (&pOut, __RV_PKBB32((__RV_SMBT32(coeff, temp) >> 32), (__RV_SMBB32(temp, coeff) >> 32))); +#else + /* Perform Multiplications and store in destination buffer */ + *pOut++ = (q31_t) (((q63_t) *px++ * coeff) >> 32); + + *pOut++ = (q31_t) (((q63_t) *px++ * coeff) >> 32); + + *pOut++ = (q31_t) (((q63_t) *px++ * coeff) >> 32); + + *pOut++ = (q31_t) (((q63_t) *px++ * coeff) >> 32); +#endif /* __RISCV_XLEN == 64 */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ +#if defined (RISCV_VECTOR) + uint32_t vblkCnt = blockSize; + size_t l; + vint32m4_t vx; + for (; (l = vsetvl_e32m4(vblkCnt)) > 0; vblkCnt -= l) { + vx = vle32_v_i32m4(px, l); + px += l; + vse32_v_i32m4 (pOut,vnclip_wx_i32m4(vwmul_vx_i64m8(vx, coeff, l),32, l), l); + pOut += l; + } +#else + while (blkCnt > 0U) + { + /* Perform Multiplication and store in destination buffer */ + *pOut++ = (q31_t) (((q63_t) *px++ * coeff) >> 32); + + /* Decrement loop counter */ + blkCnt--; + } +#endif /* defined (RISCV_VECTOR) */ + /* Load the coefficient value and + * increment the coefficient buffer for the next set of state values */ + coeff = *pCoeffs++; + + /* Read Index, from where the state buffer should be read, is calculated. */ + readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) + { + readIndex += (int32_t) delaySize; + } + + /* Loop over the number of taps. */ + tapCnt = (uint32_t) numTaps - 2U; + + while (tapCnt > 0U) + { + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + riscv_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1, + (int32_t *) pb, (int32_t *) pb, blockSize, 1, blockSize); + + /* Working pointer for the scratch buffer of state values */ + px = pb; + + /* Working pointer for scratch buffer of output values */ + pOut = pDst; + + +#if defined (RISCV_MATH_LOOPUNROLL) && !defined (RISCV_VECTOR) + + /* Loop unrolling: Compute 4 outputs at a time. */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + out = *pOut; + out += ((q63_t) *px++ * coeff) >> 32; + *pOut++ = (q31_t) (out); + + out = *pOut; + out += ((q63_t) *px++ * coeff) >> 32; + *pOut++ = (q31_t) (out); + + out = *pOut; + out += ((q63_t) *px++ * coeff) >> 32; + *pOut++ = (q31_t) (out); + + out = *pOut; + out += ((q63_t) *px++ * coeff) >> 32; + *pOut++ = (q31_t) (out); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ +#if defined (RISCV_VECTOR) + vblkCnt = blockSize; + for (; (l = vsetvl_e32m4(vblkCnt)) > 0; vblkCnt -= l) { + vx = vle32_v_i32m4(px, l); + px += l; + vse32_v_i32m4 (pOut,vadd_vv_i32m4(vle32_v_i32m4(pOut, l), vnclip_wx_i32m4(vwmul_vx_i64m8(vx, coeff, l),32, l), l), l); + pOut += l; + } +#else + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + out = *pOut; + out += ((q63_t) *px++ * coeff) >> 32; + *pOut++ = (q31_t) (out); + + /* Decrement loop counter */ + blkCnt--; + } +#endif /* defined (RISCV_VECTOR) */ + + /* Load the coefficient value and + * increment the coefficient buffer for the next set of state values */ + coeff = *pCoeffs++; + + /* Read Index, from where the state buffer should be read, is calculated. */ + readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) + { + readIndex += (int32_t) delaySize; + } + + /* Decrement tap loop counter */ + tapCnt--; + } + + /* Compute last tap without the final read of pTapDelay */ + + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + riscv_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1, + (int32_t *) pb, (int32_t *) pb, blockSize, 1, blockSize); + + /* Working pointer for the scratch buffer of state values */ + px = pb; + + /* Working pointer for scratch buffer of output values */ + pOut = pDst; + + +#if defined (RISCV_MATH_LOOPUNROLL) && !defined (RISCV_VECTOR) + + /* Loop unrolling: Compute 4 outputs at a time. */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + out = *pOut; + out += ((q63_t) * px++ * coeff) >> 32; + *pOut++ = (q31_t) (out); + + out = *pOut; + out += ((q63_t) * px++ * coeff) >> 32; + *pOut++ = (q31_t) (out); + + out = *pOut; + out += ((q63_t) * px++ * coeff) >> 32; + *pOut++ = (q31_t) (out); + + out = *pOut; + out += ((q63_t) * px++ * coeff) >> 32; + *pOut++ = (q31_t) (out); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ +#if defined (RISCV_VECTOR) + vblkCnt = blockSize; + for (; (l = vsetvl_e32m4(vblkCnt)) > 0; vblkCnt -= l) { + vx = vle32_v_i32m4(px, l); + px += l; + vse32_v_i32m4 (pOut,vadd_vv_i32m4(vle32_v_i32m4(pOut, l), vnclip_wx_i32m4(vwmul_vx_i64m8(vx, coeff, l),32, l), l), l); + pOut += l; + } +#else + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + out = *pOut; + out += ((q63_t) *px++ * coeff) >> 32; + *pOut++ = (q31_t) (out); + + /* Decrement loop counter */ + blkCnt--; + } +#endif /* defined (RISCV_VECTOR) */ + /* Working output pointer is updated */ + pOut = pDst; + + /* Output is converted into 1.31 format. */ +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time. */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + in = *pOut << 1; + *pOut++ = in; + in = *pOut << 1; + *pOut++ = in; + in = *pOut << 1; + *pOut++ = in; + in = *pOut << 1; + *pOut++ = in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + in = *pOut << 1; + *pOut++ = in; + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of FIR_Sparse group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_sparse_q7.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_sparse_q7.c new file mode 100644 index 00000000..b0e83754 --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_fir_sparse_q7.c @@ -0,0 +1,368 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_fir_sparse_q7.c + * Description: Q7 sparse FIR filter processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Sparse + @{ + */ + +/** + @brief Processing function for the Q7 sparse FIR filter. + @param[in] S points to an instance of the Q7 sparse FIR structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] pScratchIn points to a temporary buffer of size blockSize + @param[in] pScratchOut points to a temporary buffer of size blockSize + @param[in] blockSize number of input samples to process + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 32-bit internal accumulator. + Both coefficients and state variables are represented in 1.7 format and multiplications yield a 2.14 result. + The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format. + There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + The accumulator is then converted to 18.7 format by discarding the low 7 bits. + Finally, the result is truncated to 1.7 format. + */ + +void riscv_fir_sparse_q7( + riscv_fir_sparse_instance_q7 * S, + const q7_t * pSrc, + q7_t * pDst, + q7_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize) +{ + q7_t *pState = S->pState; /* State pointer */ + const q7_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q7_t *px; /* Scratch buffer pointer */ + q7_t *py = pState; /* Temporary pointers for state buffer */ + q7_t *pb = pScratchIn; /* Temporary pointers for scratch buffer */ + q7_t *pOut = pDst; /* Destination pointer */ + int32_t *pTapDelay = S->pTapDelay; /* Pointer to the array containing offset of the non-zero tap values. */ + uint32_t delaySize = S->maxDelay + blockSize; /* state length */ + uint16_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + int32_t readIndex; /* Read index of the state buffer */ + uint32_t tapCnt, blkCnt; /* loop counters */ + q31_t *pScr2 = pScratchOut; /* Working pointer for scratch buffer of output values */ + q31_t in; + q7_t coeff = *pCoeffs++; /* Read the coefficient value */ + +#if defined (RISCV_MATH_LOOPUNROLL) + q7_t in1, in2, in3, in4; +#endif + + /* BlockSize of Input samples are copied into the state buffer */ + /* StateIndex points to the starting position to write in the state buffer */ + riscv_circularWrite_q7(py, (int32_t) delaySize, &S->stateIndex, 1, pSrc, 1, blockSize); + + /* Loop over the number of taps. */ + tapCnt = numTaps; + + /* Read Index, from where the state buffer should be read, is calculated. */ + readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) + { + readIndex += (int32_t) delaySize; + } + + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + riscv_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, + pb, pb, (int32_t) blockSize, 1, blockSize); + + /* Working pointer for the scratch buffer of state values */ + px = pb; + + /* Working pointer for scratch buffer of output values */ + pScratchOut = pScr2; + + +#if defined (RISCV_MATH_LOOPUNROLL) && !defined (RISCV_VECTOR) + + /* Loop unrolling: Compute 4 outputs at a time. */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Perform multiplication and store in the scratch buffer */ + *pScratchOut++ = ((q31_t) *px++ * coeff); + *pScratchOut++ = ((q31_t) *px++ * coeff); + *pScratchOut++ = ((q31_t) *px++ * coeff); + *pScratchOut++ = ((q31_t) *px++ * coeff); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ +#if defined (RISCV_VECTOR) + uint32_t vblkCnt = blockSize; /* Loop counter */ + size_t l; + vint8m2_t vx; + for (; (l = vsetvl_e8m2(vblkCnt)) > 0; vblkCnt -= l) { + vx = vle8_v_i8m2(px, l); + px += l; + vse32_v_i32m8 (pScratchOut,vwadd_vx_i32m8(vwmul_vx_i16m4(vx, coeff, l),0, l), l); + pScratchOut += l; + } +#else + while (blkCnt > 0U) + { + /* Perform Multiplication and store in the scratch buffer */ + *pScratchOut++ = ((q31_t) *px++ * coeff); + + /* Decrement loop counter */ + blkCnt--; + } +#endif /* defined (RISCV_VECTOR) */ + /* Load the coefficient value and + * increment the coefficient buffer for the next set of state values */ + coeff = *pCoeffs++; + + /* Read Index, from where the state buffer should be read, is calculated. */ + readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) + { + readIndex += (int32_t) delaySize; + } + + /* Loop over the number of taps. */ + tapCnt = (uint32_t) numTaps - 2U; + + while (tapCnt > 0U) + { + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + riscv_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, + pb, pb, (int32_t) blockSize, 1, blockSize); + + /* Working pointer for the scratch buffer of state values */ + px = pb; + + /* Working pointer for scratch buffer of output values */ + pScratchOut = pScr2; + + +#if defined (RISCV_MATH_LOOPUNROLL) && !defined (RISCV_VECTOR) + + /* Loop unrolling: Compute 4 outputs at a time. */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + in = *pScratchOut + ((q31_t) * px++ * coeff); + *pScratchOut++ = in; + in = *pScratchOut + ((q31_t) * px++ * coeff); + *pScratchOut++ = in; + in = *pScratchOut + ((q31_t) * px++ * coeff); + *pScratchOut++ = in; + in = *pScratchOut + ((q31_t) * px++ * coeff); + *pScratchOut++ = in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ +#if defined (RISCV_VECTOR) + vblkCnt = blockSize; /* Loop counter */ + for (; (l = vsetvl_e8m2(vblkCnt)) > 0; vblkCnt -= l) { + vx = vle8_v_i8m2(px, l); + px += l; + vse32_v_i32m8 (pScratchOut,vadd_vv_i32m8(vle32_v_i32m8(pScratchOut, l), vwadd_vx_i32m8(vwmul_vx_i16m4(vx, coeff, l),0, l), l), l); + pScratchOut += l; + } +#else + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + in = *pScratchOut + ((q31_t) *px++ * coeff); + *pScratchOut++ = in; + + /* Decrement loop counter */ + blkCnt--; + } +#endif /* defined (RISCV_VECTOR) */ + /* Load the coefficient value and + * increment the coefficient buffer for the next set of state values */ + coeff = *pCoeffs++; + + /* Read Index, from where the state buffer should be read, is calculated. */ + readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) + { + readIndex += (int32_t) delaySize; + } + + /* Decrement loop counter */ + tapCnt--; + } + + /* Compute last tap without the final read of pTapDelay */ + + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + riscv_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, + pb, pb, (int32_t) blockSize, 1, blockSize); + + /* Working pointer for the scratch buffer of state values */ + px = pb; + + /* Working pointer for scratch buffer of output values */ + pScratchOut = pScr2; + + +#if defined (RISCV_MATH_LOOPUNROLL) && !defined (RISCV_VECTOR) + + /* Loop unrolling: Compute 4 outputs at a time. */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + in = *pScratchOut + ((q31_t) *px++ * coeff); + *pScratchOut++ = in; + in = *pScratchOut + ((q31_t) *px++ * coeff); + *pScratchOut++ = in; + in = *pScratchOut + ((q31_t) *px++ * coeff); + *pScratchOut++ = in; + in = *pScratchOut + ((q31_t) *px++ * coeff); + *pScratchOut++ = in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ +#if defined (RISCV_VECTOR) + vblkCnt = blockSize; /* Loop counter */ + for (; (l = vsetvl_e8m2(vblkCnt)) > 0; vblkCnt -= l) { + vx = vle8_v_i8m2(px, l); + px += l; + vse32_v_i32m8 (pScratchOut,vadd_vv_i32m8(vle32_v_i32m8(pScratchOut, l), vwadd_vx_i32m8(vwmul_vx_i16m4(vx, coeff, l),0, l), l), l); + pScratchOut += l; + } +#else + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + in = *pScratchOut + ((q31_t) *px++ * coeff); + *pScratchOut++ = in; + + /* Decrement loop counter */ + blkCnt--; + } +#endif /* defined (RISCV_VECTOR) */ + /* All the output values are in pScratchOut buffer. + Convert them into 1.15 format, saturate and store in the destination buffer. */ +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time. */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + in1 = (q7_t) __SSAT(*pScr2++ >> 7, 8); + in2 = (q7_t) __SSAT(*pScr2++ >> 7, 8); + in3 = (q7_t) __SSAT(*pScr2++ >> 7, 8); + in4 = (q7_t) __SSAT(*pScr2++ >> 7, 8); + + write_q7x4_ia (&pOut, __PACKq7(in1, in2, in3, in4)); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + *pOut++ = (q7_t) __SSAT(*pScr2++ >> 7, 8); + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of FIR_Sparse group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_iir_lattice_f32.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_iir_lattice_f32.c new file mode 100644 index 00000000..71597307 --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_iir_lattice_f32.c @@ -0,0 +1,355 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_iir_lattice_f32.c + * Description: Floating-point IIR Lattice filter processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @defgroup IIR_Lattice Infinite Impulse Response (IIR) Lattice Filters + + This set of functions implements lattice filters + for Q15, Q31 and floating-point data types. Lattice filters are used in a + variety of adaptive filter applications. The filter structure has feedforward and + feedback components and the net impulse response is infinite length. + The functions operate on blocks + of input and output data and each call to the function processes + blockSize samples through the filter. pSrc and + pDst point to input and output arrays containing blockSize values. + + @par Algorithm + \image html IIRLattice.png "Infinite Impulse Response Lattice filter" + @par + 
+      fN(n)   = x(n)
+      fm-1(n) = fm(n) - km * gm-1(n-1)   for m = N, N-1, ..., 1
+      gm(n)   = km * fm-1(n) + gm-1(n-1) for m = N, N-1, ..., 1
+      y(n)    = vN * gN(n) + vN-1 * gN-1(n) + ...+ v0 * g0(n)
+
+ @par + pkCoeffs points to array of reflection coefficients of size numStages. + Reflection Coefficients are stored in time-reversed order. + @par + 
+     {kN, kN-1, ..., k1}
+
+ @par + pvCoeffs points to the array of ladder coefficients of size (numStages+1). + Ladder coefficients are stored in time-reversed order. + 
+      {vN, vN-1, ..., v0}
+
+ @par + pState points to a state array of size numStages + blockSize. + The state variables shown in the figure above (the g values) are stored in the pState array. + The state variables are updated after each block of data is processed; the coefficients are untouched. + + @par Instance Structure + The coefficients and state variables for a filter are stored together in an instance data structure. + A separate instance structure must be defined for each filter. + Coefficient arrays may be shared among several instances while state variable arrays cannot be shared. + There are separate instance structure declarations for each of the 3 supported data types. + + @par Initialization Functions + There is also an associated initialization function for each data type. + The initialization function performs the following operations: + - Sets the values of the internal structure fields. + - Zeros out the values in the state buffer. + To do this manually without calling the init function, assign the follow subfields of the instance structure: + numStages, pkCoeffs, pvCoeffs, pState. Also set all of the values in pState to zero. + @par + Use of the initialization function is optional. + However, if the initialization function is used, then the instance structure cannot be placed into a const data section. + To place an instance structure into a const data section, the instance structure must be manually initialized. + Set the values in the state buffer to zeros and then manually initialize the instance structure as follows: + 
+      riscv_iir_lattice_instance_f32 S = {numStages, pState, pkCoeffs, pvCoeffs};
+      riscv_iir_lattice_instance_q31 S = {numStages, pState, pkCoeffs, pvCoeffs};
+      riscv_iir_lattice_instance_q15 S = {numStages, pState, pkCoeffs, pvCoeffs};
+
+ @par + where numStages is the number of stages in the filter; pState points to the state buffer array; + pkCoeffs points to array of the reflection coefficients; pvCoeffs points to the array of ladder coefficients. + + @par Fixed-Point Behavior + Care must be taken when using the fixed-point versions of the IIR lattice filter functions. + In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + Refer to the function specific documentation below for usage guidelines. + */ + +/** + @addtogroup IIR_Lattice + @{ + */ + +/** + @brief Processing function for the floating-point IIR lattice filter. + @param[in] S points to an instance of the floating-point IIR lattice structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + */ + +void riscv_iir_lattice_f32( + const riscv_iir_lattice_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + float32_t *pStateCur; /* State current pointer */ + float32_t acc; /* Accumlator */ + float32_t fnext1, fnext2, gcurr1, gnext; /* Temporary variables for lattice stages */ + float32_t *px1, *px2, *pk, *pv; /* Temporary pointers for state and coef */ + uint32_t numStages = S->numStages; /* Number of stages */ + uint32_t blkCnt, tapCnt; /* Temporary variables for counts */ + +#if defined (RISCV_MATH_LOOPUNROLL) + float32_t gcurr2; /* Temporary variables for lattice stages */ + float32_t k1, k2; + float32_t v1, v2, v3, v4; +#endif + + /* initialise loop count */ + blkCnt = blockSize; + + /* Sample processing */ + while (blkCnt > 0U) + { + /* Read Sample from input buffer */ + /* fN(n) = x(n) */ + fnext2 = *pSrc++; + + /* Initialize Ladder coeff pointer */ + pv = &S->pvCoeffs[0]; + + /* Initialize Reflection coeff pointer */ + pk = &S->pkCoeffs[0]; + + /* Initialize state read pointer */ + px1 = pState; + + /* Initialize state write pointer */ + px2 = pState; + + /* Set accumulator to zero */ + acc = 0.0; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = (numStages) >> 2U; + + while (tapCnt > 0U) + { + /* Read gN-1(n-1) from state buffer */ + gcurr1 = *px1; + + /* read reflection coefficient kN */ + k1 = *pk; + + /* fN-1(n) = fN(n) - kN * gN-1(n-1) */ + fnext1 = fnext2 - (k1 * gcurr1); + + /* read ladder coefficient vN */ + v1 = *pv; + + /* read next reflection coefficient kN-1 */ + k2 = *(pk + 1U); + + /* Read gN-2(n-1) from state buffer */ + gcurr2 = *(px1 + 1U); + + /* read next ladder coefficient vN-1 */ + v2 = *(pv + 1U); + + /* fN-2(n) = fN-1(n) - kN-1 * gN-2(n-1) */ + fnext2 = fnext1 - (k2 * gcurr2); + + /* gN(n) = kN * fN-1(n) + gN-1(n-1) */ + gnext = gcurr1 + (k1 * fnext1); + + /* read reflection coefficient kN-2 */ + k1 = *(pk + 2U); + + /* write gN(n) into state for next sample processing */ + *px2++ = gnext; + + /* Read gN-3(n-1) from state buffer */ + gcurr1 = *(px1 + 2U); + + /* y(n) += gN(n) * vN */ + acc += (gnext * v1); + + /* fN-3(n) = fN-2(n) - kN-2 * gN-3(n-1) */ + fnext1 = fnext2 - (k1 * gcurr1); + + /* gN-1(n) = kN-1 * fN-2(n) + gN-2(n-1) */ + gnext = gcurr2 + (k2 * fnext2); + + /* Read gN-4(n-1) from state buffer */ + gcurr2 = *(px1 + 3U); + + /* y(n) += gN-1(n) * vN-1 */ + acc += (gnext * v2); + + /* read reflection coefficient kN-3 */ + k2 = *(pk + 3U); + + /* write gN-1(n) into state for next sample processing */ + *px2++ = gnext; + + /* fN-4(n) = fN-3(n) - kN-3 * gN-4(n-1) */ + fnext2 = fnext1 - (k2 * gcurr2); + + /* gN-2(n) = kN-2 * fN-3(n) + gN-3(n-1) */ + gnext = gcurr1 + (k1 * fnext1); + + /* read ladder coefficient vN-2 */ + v3 = *(pv + 2U); + + /* y(n) += gN-2(n) * vN-2 */ + acc += (gnext * v3); + + /* write gN-2(n) into state for next sample processing */ + *px2++ = gnext; + + /* update pointer */ + pk += 4U; + + /* gN-3(n) = kN-3 * fN-4(n) + gN-4(n-1) */ + gnext = (fnext2 * k2) + gcurr2; + + /* read next ladder coefficient vN-3 */ + v4 = *(pv + 3U); + + /* y(n) += gN-4(n) * vN-4 */ + acc += (gnext * v4); + + /* write gN-3(n) into state for next sample processing */ + *px2++ = gnext; + + /* update pointers */ + px1 += 4U; + pv += 4U; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numStages % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = numStages; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + gcurr1 = *px1++; + /* Process sample for last taps */ + fnext1 = fnext2 - ((*pk) * gcurr1); + gnext = (fnext1 * (*pk++)) + gcurr1; + /* Output samples for last taps */ + acc += (gnext * (*pv++)); + *px2++ = gnext; + fnext2 = fnext1; + + /* Decrement loop counter */ + tapCnt--; + } + + /* y(n) += g0(n) * v0 */ + acc += (fnext2 * (*pv)); + + *px2++ = fnext2; + + /* write out into pDst */ + *pDst++ = acc; + + /* Advance the state pointer by 4 to process the next group of 4 samples */ + pState = pState + 1U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. Now copy last S->numStages samples to start of the buffer + for the preperation of next frame process */ + + /* Points to the start of the state buffer */ + pStateCur = &S->pState[0]; + pState = &S->pState[blockSize]; + + /* Copy data */ +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = numStages >> 2U; + + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numStages % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + tapCnt = numStages; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +} + +/** + @} end of IIR_Lattice group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_iir_lattice_init_f32.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_iir_lattice_init_f32.c new file mode 100644 index 00000000..e883a084 --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_iir_lattice_init_f32.c @@ -0,0 +1,78 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_iir_lattice_init_f32.c + * Description: Floating-point IIR lattice filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup IIR_Lattice + @{ + */ + +/** + @brief Initialization function for the floating-point IIR lattice filter. + @param[in] S points to an instance of the floating-point IIR lattice structure + @param[in] numStages number of stages in the filter + @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages + @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1 + @param[in] pState points to state buffer. The array is of length numStages+blockSize + @param[in] blockSize number of samples to process + @return none + */ + +void riscv_iir_lattice_init_f32( + riscv_iir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pkCoeffs, + float32_t * pvCoeffs, + float32_t * pState, + uint32_t blockSize) +{ + /* Assign filter taps */ + S->numStages = numStages; + + /* Assign reflection coefficient pointer */ + S->pkCoeffs = pkCoeffs; + + /* Assign ladder coefficient pointer */ + S->pvCoeffs = pvCoeffs; + + /* Clear state buffer and size is always blockSize + numStages */ + memset(pState, 0, (numStages + blockSize) * sizeof(float32_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of IIR_Lattice group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_iir_lattice_init_q15.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_iir_lattice_init_q15.c new file mode 100644 index 00000000..b14c2e5f --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_iir_lattice_init_q15.c @@ -0,0 +1,78 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_iir_lattice_init_q15.c + * Description: Q15 IIR lattice filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup IIR_Lattice + @{ + */ + +/** + @brief Initialization function for the Q15 IIR lattice filter. + @param[in] S points to an instance of the Q15 IIR lattice structure + @param[in] numStages number of stages in the filter + @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages + @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1 + @param[in] pState points to state buffer. The array is of length numStages+blockSize + @param[in] blockSize number of samples to process + @return none + */ + +void riscv_iir_lattice_init_q15( + riscv_iir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pkCoeffs, + q15_t * pvCoeffs, + q15_t * pState, + uint32_t blockSize) +{ + /* Assign filter taps */ + S->numStages = numStages; + + /* Assign reflection coefficient pointer */ + S->pkCoeffs = pkCoeffs; + + /* Assign ladder coefficient pointer */ + S->pvCoeffs = pvCoeffs; + + /* Clear state buffer and size is always blockSize + numStages */ + memset(pState, 0, (numStages + blockSize) * sizeof(q15_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of IIR_Lattice group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_iir_lattice_init_q31.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_iir_lattice_init_q31.c new file mode 100644 index 00000000..8b3c6ef6 --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_iir_lattice_init_q31.c @@ -0,0 +1,78 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_iir_lattice_init_q31.c + * Description: Initialization function for the Q31 IIR lattice filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup IIR_Lattice + @{ + */ + +/** + @brief Initialization function for the Q31 IIR lattice filter. + @param[in] S points to an instance of the Q31 IIR lattice structure + @param[in] numStages number of stages in the filter + @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages + @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1 + @param[in] pState points to state buffer. The array is of length numStages+blockSize + @param[in] blockSize number of samples to process + @return none + */ + +void riscv_iir_lattice_init_q31( + riscv_iir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pkCoeffs, + q31_t * pvCoeffs, + q31_t * pState, + uint32_t blockSize) +{ + /* Assign filter taps */ + S->numStages = numStages; + + /* Assign reflection coefficient pointer */ + S->pkCoeffs = pkCoeffs; + + /* Assign ladder coefficient pointer */ + S->pvCoeffs = pvCoeffs; + + /* Clear state buffer and size is always blockSize + numStages */ + memset(pState, 0, (numStages + blockSize) * sizeof(q31_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of IIR_Lattice group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_iir_lattice_q15.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_iir_lattice_q15.c new file mode 100644 index 00000000..e8a21c67 --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_iir_lattice_q15.c @@ -0,0 +1,389 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_iir_lattice_q15.c + * Description: Q15 IIR Lattice filter processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup IIR_Lattice + @{ + */ + +/** + @brief Processing function for the Q15 IIR lattice filter. + @param[in] S points to an instance of the Q15 IIR lattice structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ + +void riscv_iir_lattice_q15( + const riscv_iir_lattice_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + q15_t *pStateCur; /* State current pointer */ + q31_t fcurr, fnext = 0, gcurr = 0, gnext; /* Temporary variables for lattice stages */ + q63_t acc; /* Accumlator */ + q15_t *px1, *px2, *pk, *pv; /* Temporary pointers for state and coef */ + uint32_t numStages = S->numStages; /* Number of stages */ + uint32_t blkCnt, tapCnt; /* Temporary variables for counts */ + q15_t out; /* Temporary variable for output */ + +#if defined (RISCV_MATH_DSP) && defined (RISCV_MATH_LOOPUNROLL) + q15_t gnext1, gnext2; /* Temporary variables for lattice stages */ + q31_t v; /* Temporary variable for ladder coefficient */ +#endif + + /* initialise loop count */ + blkCnt = blockSize; + +#if defined (RISCV_MATH_DSP) + + /* Sample processing */ + while (blkCnt > 0U) + { + /* Read Sample from input buffer */ + /* fN(n) = x(n) */ + fcurr = *pSrc++; + + /* Initialize Ladder coeff pointer */ + pv = &S->pvCoeffs[0]; + + /* Initialize Reflection coeff pointer */ + pk = &S->pkCoeffs[0]; + + /* Initialize state read pointer */ + px1 = pState; + + /* Initialize state write pointer */ + px2 = pState; + + /* Set accumulator to zero */ + acc = 0; + + /* Process sample for first tap */ + gcurr = *px1++; + /* fN-1(n) = fN(n) - kN * gN-1(n-1) */ + fnext = fcurr - (((q31_t) gcurr * (*pk)) >> 15); + fnext = __SSAT(fnext, 16); + + /* gN(n) = kN * fN-1(n) + gN-1(n-1) */ + gnext = (((q31_t) fnext * (*pk++)) >> 15) + gcurr; + gnext = __SSAT(gnext, 16); + + /* write gN(n) into state for next sample processing */ + *px2++ = (q15_t) gnext; + + /* y(n) += gN(n) * vN */ + acc += (q31_t) ((gnext * (*pv++))); + + /* Update f values for next coefficient processing */ + fcurr = fnext; + + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = (numStages - 1U) >> 2U; + + while (tapCnt > 0U) + { + /* Process sample for 2nd, 6th ...taps */ + /* Read gN-2(n-1) from state buffer */ + gcurr = *px1++; + /* fN-2(n) = fN-1(n) - kN-1 * gN-2(n-1) */ + fnext = fcurr - (((q31_t) gcurr * (*pk)) >> 15); + fnext = __SSAT(fnext, 16); + /* gN-1(n) = kN-1 * fN-2(n) + gN-2(n-1) */ + gnext = (((q31_t) fnext * (*pk++)) >> 15) + gcurr; + gnext1 = (q15_t) __SSAT(gnext, 16); + /* write gN-1(n) into state for next sample processing */ + *px2++ = (q15_t) gnext1; + + /* Process sample for 3nd, 7th ...taps */ + /* Read gN-3(n-1) from state buffer */ + gcurr = *px1++; + /* Process sample for 3rd, 7th .. taps */ + /* fN-3(n) = fN-2(n) - kN-2 * gN-3(n-1) */ + fcurr = fnext - (((q31_t) gcurr * (*pk)) >> 15); + fcurr = __SSAT(fcurr, 16); + /* gN-2(n) = kN-2 * fN-3(n) + gN-3(n-1) */ + gnext = (((q31_t) fcurr * (*pk++)) >> 15) + gcurr; + gnext2 = (q15_t) __SSAT(gnext, 16); + /* write gN-2(n) into state */ + *px2++ = (q15_t) gnext2; + + /* Read vN-1 and vN-2 at a time */ + v = read_q15x2_ia (&pv); + + /* Pack gN-1(n) and gN-2(n) */ + + gnext = __PKHBT(gnext1, gnext2, 16); + + /* y(n) += gN-1(n) * vN-1 */ + /* process for gN-5(n) * vN-5, gN-9(n) * vN-9 ... */ + /* y(n) += gN-2(n) * vN-2 */ + /* process for gN-6(n) * vN-6, gN-10(n) * vN-10 ... */ + acc = __SMLALD(gnext, v, acc); + + /* Process sample for 4th, 8th ...taps */ + /* Read gN-4(n-1) from state buffer */ + gcurr = *px1++; + /* Process sample for 4th, 8th .. taps */ + /* fN-4(n) = fN-3(n) - kN-3 * gN-4(n-1) */ + fnext = fcurr - (((q31_t) gcurr * (*pk)) >> 15); + fnext = __SSAT(fnext, 16); + /* gN-3(n) = kN-3 * fN-1(n) + gN-1(n-1) */ + gnext = (((q31_t) fnext * (*pk++)) >> 15) + gcurr; + gnext1 = (q15_t) __SSAT(gnext, 16); + /* write gN-3(n) for the next sample process */ + *px2++ = (q15_t) gnext1; + + /* Process sample for 5th, 9th ...taps */ + /* Read gN-5(n-1) from state buffer */ + gcurr = *px1++; + /* Process sample for 5th, 9th .. taps */ + /* fN-5(n) = fN-4(n) - kN-4 * gN-5(n-1) */ + fcurr = fnext - (((q31_t) gcurr * (*pk)) >> 15); + fcurr = __SSAT(fcurr, 16); + /* gN-4(n) = kN-4 * fN-5(n) + gN-5(n-1) */ + gnext = (((q31_t) fcurr * (*pk++)) >> 15) + gcurr; + gnext2 = (q15_t) __SSAT(gnext, 16); + /* write gN-4(n) for the next sample process */ + *px2++ = (q15_t) gnext2; + + /* Read vN-3 and vN-4 at a time */ + v = read_q15x2_ia (&pv); + + /* Pack gN-3(n) and gN-4(n) */ + gnext = __PKHBT(gnext1, gnext2, 16); + + /* y(n) += gN-4(n) * vN-4 */ + /* process for gN-8(n) * vN-8, gN-12(n) * vN-12 ... */ + /* y(n) += gN-3(n) * vN-3 */ + /* process for gN-7(n) * vN-7, gN-11(n) * vN-11 ... */ + acc = __SMLALD(gnext, v, acc); + + /* Decrement loop counter */ + tapCnt--; + } + + fnext = fcurr; + + /* Loop unrolling: Compute remaining taps */ + tapCnt = (numStages - 1U) % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + tapCnt = (numStages - 1U); + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + gcurr = *px1++; + /* Process sample for last taps */ + fnext = fcurr - (((q31_t) gcurr * (*pk)) >> 15); + fnext = __SSAT(fnext, 16); + gnext = (((q31_t) fnext * (*pk++)) >> 15) + gcurr; + gnext = __SSAT(gnext, 16); + + /* Output samples for last taps */ + acc += (q31_t) (((q31_t) gnext * (*pv++))); + *px2++ = (q15_t) gnext; + fcurr = fnext; + + /* Decrement loop counter */ + tapCnt--; + } + + /* y(n) += g0(n) * v0 */ + acc += (q31_t) (((q31_t) fnext * (*pv++))); + + out = (q15_t) __SSAT(acc >> 15, 16); + *px2++ = (q15_t) fnext; + + /* write out into pDst */ + *pDst++ = out; + + /* Advance the state pointer by 4 to process the next group of 4 samples */ + pState = pState + 1U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. Now copy last S->numStages samples to start of the buffer + for the preperation of next frame process */ + + /* Points to the start of the state buffer */ + pStateCur = &S->pState[0]; + pState = &S->pState[blockSize]; + + /* copy data */ +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = numStages >> 2U; + + while (tapCnt > 0U) + { + write_q15x2_ia (&pStateCur, read_q15x2_ia (&pState)); + write_q15x2_ia (&pStateCur, read_q15x2_ia (&pState)); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numStages % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + tapCnt = (numStages - 1U); + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +#else /* #if defined (RISCV_MATH_DSP) */ + + /* Sample processing */ + while (blkCnt > 0U) + { + /* Read Sample from input buffer */ + /* fN(n) = x(n) */ + fcurr = *pSrc++; + + /* Initialize Ladder coeff pointer */ + pv = &S->pvCoeffs[0]; + + /* Initialize Reflection coeff pointer */ + pk = &S->pkCoeffs[0]; + + /* Initialize state read pointer */ + px1 = pState; + + /* Initialize state write pointer */ + px2 = pState; + + /* Set accumulator to zero */ + acc = 0; + + tapCnt = numStages; + + while (tapCnt > 0U) + { + gcurr = *px1++; + /* Process sample */ + /* fN-1(n) = fN(n) - kN * gN-1(n-1) */ + fnext = fcurr - ((gcurr * (*pk)) >> 15); + fnext = __SSAT(fnext, 16); + + /* gN(n) = kN * fN-1(n) + gN-1(n-1) */ + gnext = ((fnext * (*pk++)) >> 15) + gcurr; + gnext = __SSAT(gnext, 16); + + /* Output samples */ + /* y(n) += gN(n) * vN */ + acc += (q31_t) ((gnext * (*pv++))); + + /* write gN(n) into state for next sample processing */ + *px2++ = (q15_t) gnext; + + /* Update f values for next coefficient processing */ + fcurr = fnext; + + tapCnt--; + } + + /* y(n) += g0(n) * v0 */ + acc += (q31_t) ((fnext * (*pv++))); + + out = (q15_t) __SSAT(acc >> 15, 16); + *px2++ = (q15_t) fnext; + + /* write out into pDst */ + *pDst++ = out; + + /* Advance the state pointer by 1 to process the next group of samples */ + pState = pState + 1U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. Now copy last S->numStages samples to start of the buffer + for the preperation of next frame process */ + + /* Points to the start of the state buffer */ + pStateCur = &S->pState[0]; + pState = &S->pState[blockSize]; + + tapCnt = numStages; + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +#endif /* #if defined (RISCV_MATH_DSP) */ + +} + +/** + @} end of IIR_Lattice group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_iir_lattice_q31.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_iir_lattice_q31.c new file mode 100644 index 00000000..262fd2ef --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_iir_lattice_q31.c @@ -0,0 +1,357 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_iir_lattice_q31.c + * Description: Q31 IIR Lattice filter processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup IIR_Lattice + @{ + */ + +/** + @brief Processing function for the Q31 IIR lattice filter. + @param[in] S points to an instance of the Q31 IIR lattice structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + Thus, if the accumulator result overflows it wraps around rather than clip. + In order to avoid overflows completely the input signal must be scaled down by 2*log2(numStages) bits. + After all multiply-accumulates are performed, the 2.62 accumulator is saturated to 1.32 format and then truncated to 1.31 format. + */ + +void riscv_iir_lattice_q31( + const riscv_iir_lattice_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + q31_t *pState = S->pState; /* State pointer */ + q31_t *pStateCur; /* State current pointer */ + q31_t fcurr, fnext = 0, gcurr = 0, gnext; /* Temporary variables for lattice stages */ + q63_t acc; /* Accumlator */ + q31_t *px1, *px2, *pk, *pv; /* Temporary pointers for state and coef */ + uint32_t numStages = S->numStages; /* Number of stages */ + uint32_t blkCnt, tapCnt; /* Temporary variables for counts */ + + + /* initialise loop count */ + blkCnt = blockSize; + +#if defined (RISCV_MATH_DSP) + + /* Sample processing */ + while (blkCnt > 0U) + { + /* Read Sample from input buffer */ + /* fN(n) = x(n) */ + fcurr = *pSrc++; + + /* Initialize Ladder coeff pointer */ + pv = &S->pvCoeffs[0]; + + /* Initialize Reflection coeff pointer */ + pk = &S->pkCoeffs[0]; + + /* Initialize state read pointer */ + px1 = pState; + + /* Initialize state write pointer */ + px2 = pState; + + /* Set accumulator to zero */ + acc = 0; + + /* Process sample for first tap */ + gcurr = *px1++; + /* fN-1(n) = fN(n) - kN * gN-1(n-1) */ + fnext = __QSUB(fcurr, (q31_t) (((q63_t) gcurr * (*pk )) >> 31)); + + /* gN(n) = kN * fN-1(n) + gN-1(n-1) */ + gnext = __QADD(gcurr, (q31_t) (((q63_t) fnext * (*pk++)) >> 31)); + + /* write gN-1(n-1) into state for next sample processing */ + *px2++ = gnext; + + /* y(n) += gN(n) * vN */ + acc += ((q63_t) gnext * *pv++); + + /* Update f values for next coefficient processing */ + fcurr = fnext; + + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = (numStages - 1U) >> 2U; + + while (tapCnt > 0U) + { + /* Process sample for 2nd, 6th ...taps */ + /* Read gN-2(n-1) from state buffer */ + gcurr = *px1++; + /* fN-2(n) = fN-1(n) - kN-1 * gN-2(n-1) */ + fnext = __QSUB(fcurr, (q31_t) (((q63_t) gcurr * (*pk )) >> 31)); + /* gN-1(n) = kN-1 * fN-2(n) + gN-2(n-1) */ + gnext = __QADD(gcurr, (q31_t) (((q63_t) fnext * (*pk++)) >> 31)); + /* y(n) += gN-1(n) * vN-1 */ + /* process for gN-5(n) * vN-5, gN-9(n) * vN-9 ... */ + acc += ((q63_t) gnext * *pv++); + /* write gN-1(n) into state for next sample processing */ + *px2++ = gnext; + + /* Process sample for 3nd, 7th ...taps */ + /* Read gN-3(n-1) from state buffer */ + gcurr = *px1++; + /* Process sample for 3rd, 7th .. taps */ + /* fN-3(n) = fN-2(n) - kN-2 * gN-3(n-1) */ + fcurr = __QSUB(fnext, (q31_t) (((q63_t) gcurr * (*pk )) >> 31)); + /* gN-2(n) = kN-2 * fN-3(n) + gN-3(n-1) */ + gnext = __QADD(gcurr, (q31_t) (((q63_t) fcurr * (*pk++)) >> 31)); + /* y(n) += gN-2(n) * vN-2 */ + /* process for gN-6(n) * vN-6, gN-10(n) * vN-10 ... */ + acc += ((q63_t) gnext * *pv++); + /* write gN-2(n) into state for next sample processing */ + *px2++ = gnext; + + /* Process sample for 4th, 8th ...taps */ + /* Read gN-4(n-1) from state buffer */ + gcurr = *px1++; + /* Process sample for 4th, 8th .. taps */ + /* fN-4(n) = fN-3(n) - kN-3 * gN-4(n-1) */ + fnext = __QSUB(fcurr, (q31_t) (((q63_t) gcurr * (*pk )) >> 31)); + /* gN-3(n) = kN-3 * fN-4(n) + gN-4(n-1) */ + gnext = __QADD(gcurr, (q31_t) (((q63_t) fnext * (*pk++)) >> 31)); + /* y(n) += gN-3(n) * vN-3 */ + /* process for gN-7(n) * vN-7, gN-11(n) * vN-11 ... */ + acc += ((q63_t) gnext * *pv++); + /* write gN-3(n) into state for next sample processing */ + *px2++ = gnext; + + /* Process sample for 5th, 9th ...taps */ + /* Read gN-5(n-1) from state buffer */ + gcurr = *px1++; + /* Process sample for 5th, 9th .. taps */ + /* fN-5(n) = fN-4(n) - kN-4 * gN-1(n-1) */ + fcurr = __QSUB(fnext, (q31_t) (((q63_t) gcurr * (*pk )) >> 31)); + /* gN-4(n) = kN-4 * fN-5(n) + gN-5(n-1) */ + gnext = __QADD(gcurr, (q31_t) (((q63_t) fcurr * (*pk++)) >> 31)); + /* y(n) += gN-4(n) * vN-4 */ + /* process for gN-8(n) * vN-8, gN-12(n) * vN-12 ... */ + acc += ((q63_t) gnext * *pv++); + + /* write gN-4(n) into state for next sample processing */ + *px2++ = gnext; + + /* Decrement loop counter */ + tapCnt--; + } + + fnext = fcurr; + + /* Loop unrolling: Compute remaining taps */ + tapCnt = (numStages - 1U) % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + tapCnt = (numStages - 1U); + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + gcurr = *px1++; + /* Process sample for last taps */ + fnext = __QSUB(fcurr, (q31_t) (((q63_t) gcurr * (*pk )) >> 31)); + gnext = __QADD(gcurr, (q31_t) (((q63_t) fnext * (*pk++)) >> 31)); + + /* Output samples for last taps */ + acc += ((q63_t) gnext * *pv++); + *px2++ = gnext; + fcurr = fnext; + + /* Decrement loop counter */ + tapCnt--; + } + + /* y(n) += g0(n) * v0 */ + acc += ((q63_t) fnext * *pv++); + + *px2++ = fnext; + + /* write out into pDst */ + *pDst++ = (q31_t) (acc >> 31U); + + /* Advance the state pointer by 4 to process the next group of 4 samples */ + pState = pState + 1U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. Now copy last S->numStages samples to start of the buffer + for the preperation of next frame process */ + + /* Points to the start of the state buffer */ + pStateCur = &S->pState[0]; + pState = &S->pState[blockSize]; + + /* Copy data */ +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = numStages >> 2U; + + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numStages % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + tapCnt = (numStages - 1U); + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +#else /* #if defined (RISCV_MATH_DSP) */ + + /* Sample processing */ + while (blkCnt > 0U) + { + /* Read Sample from input buffer */ + /* fN(n) = x(n) */ + fcurr = *pSrc++; + + /* Initialize Ladder coeff pointer */ + pv = &S->pvCoeffs[0]; + + /* Initialize Reflection coeff pointer */ + pk = &S->pkCoeffs[0]; + + /* Initialize state read pointer */ + px1 = pState; + + /* Initialize state write pointer */ + px2 = pState; + + /* Set accumulator to zero */ + acc = 0; + + tapCnt = numStages; + + while (tapCnt > 0U) + { + gcurr = *px1++; + /* Process sample */ + /* fN-1(n) = fN(n) - kN * gN-1(n-1) */ + fnext = clip_q63_to_q31(((q63_t) fcurr - ((q31_t) (((q63_t) gcurr * (*pk )) >> 31)))); + + /* gN(n) = kN * fN-1(n) + gN-1(n-1) */ + gnext = clip_q63_to_q31(((q63_t) gcurr + ((q31_t) (((q63_t) fnext * (*pk++)) >> 31)))); + + /* Output samples */ + /* y(n) += gN(n) * vN */ + acc += ((q63_t) gnext * *pv++); + + /* write gN-1(n-1) into state for next sample processing */ + *px2++ = gnext; + + /* Update f values for next coefficient processing */ + fcurr = fnext; + + tapCnt--; + } + + /* y(n) += g0(n) * v0 */ + acc += ((q63_t) fnext * *pv++); + + *px2++ = fnext; + + /* write out into pDst */ + *pDst++ = (q31_t) (acc >> 31U); + + /* Advance the state pointer by 1 to process the next group of samples */ + pState = pState + 1U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. Now copy last S->numStages samples to start of the buffer + for the preperation of next frame process */ + + /* Points to the start of the state buffer */ + pStateCur = &S->pState[0]; + pState = &S->pState[blockSize]; + + tapCnt = numStages; + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +#endif /* #if defined (RISCV_MATH_DSP) */ + +} + +/** + @} end of IIR_Lattice group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_levinson_durbin_f16.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_levinson_durbin_f16.c new file mode 100644 index 00000000..51c387f3 --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_levinson_durbin_f16.c @@ -0,0 +1,116 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_levinson_durbin_f16.c + * Description: f16 version of Levinson Durbin algorithm + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions_f16.h" + +/** + @ingroup groupFilters + */ + +/** + @defgroup LD Levinson Durbin Algorithm + + */ + +/** + @addtogroup LD + @{ + */ + +/** + @brief Levinson Durbin + @param[in] phi autocovariance vector starting with lag 0 (length is nbCoefs + 1) + @param[out] a autoregressive coefficients + @param[out] err prediction error (variance) + @param[in] nbCoefs number of autoregressive coefficients + @return none + */ + + + +#if defined(RISCV_FLOAT16_SUPPORTED) + +void riscv_levinson_durbin_f16(const float16_t *phi, + float16_t *a, + float16_t *err, + int nbCoefs) +{ + _Float16 e; + + a[0] = (_Float16)phi[1] / (_Float16)phi[0]; + + e = (_Float16)phi[0] - (_Float16)phi[1] * (_Float16)a[0]; + for(int p=1; p < nbCoefs; p++) + { + _Float16 suma=0.0f16; + _Float16 sumb=0.0f16; + _Float16 k; + int nb,j; + + for(int i=0; i < p; i++) + { + suma += (_Float16)a[i] * (_Float16)phi[p - i]; + sumb += (_Float16)a[i] * (_Float16)phi[i + 1]; + } + + k = ((_Float16)phi[p+1]-suma)/((_Float16)phi[0] - sumb); + + + nb = p >> 1; + j=0; + for(int i =0;i < nb ; i++) + { + _Float16 x,y; + + x=(_Float16)a[j] - (_Float16)k * (_Float16)a[p-1-j]; + y=(_Float16)a[p-1-j] - (_Float16)k * (_Float16)a[j]; + + a[j] = x; + a[p-1-j] = y; + + j++; + } + + nb = p & 1; + if (nb) + { + a[j]=(_Float16)a[j]- (_Float16)k * (_Float16)a[p-1-j]; + } + + a[p] = k; + e = e * (1.0f16 - k*k); + + + } + *err = e; +} +#endif /* defined(RISCV_FLOAT16_SUPPORTED */ +/** + @} end of LD group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_levinson_durbin_f32.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_levinson_durbin_f32.c new file mode 100644 index 00000000..acb6b4ee --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_levinson_durbin_f32.c @@ -0,0 +1,113 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_levinson_durbin_f32.c + * Description: f32 version of Levinson Durbin algorithm + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @defgroup LD Levinson Durbin Algorithm + + */ + +/** + @addtogroup LD + @{ + */ + +/** + @brief Levinson Durbin + @param[in] phi autocovariance vector starting with lag 0 (length is nbCoefs + 1) + @param[out] a autoregressive coefficients + @param[out] err prediction error (variance) + @param[in] nbCoefs number of autoregressive coefficients + @return none + */ + + +void riscv_levinson_durbin_f32(const float32_t *phi, + float32_t *a, + float32_t *err, + int nbCoefs) +{ + float32_t e; + + a[0] = phi[1] / phi[0]; + + e = phi[0] - phi[1] * a[0]; + for(int p=1; p < nbCoefs; p++) + { + float32_t suma=0.0f; + float32_t sumb=0.0f; + float32_t k; + int nb,j; + + for(int i=0; i < p; i++) + { + suma += a[i] * phi[p - i]; + sumb += a[i] * phi[i + 1]; + } + + k = (phi[p+1]-suma)/(phi[0] - sumb); + + + nb = p >> 1; + j=0; + for(int i =0; i < nb ; i++) + { + float32_t x,y; + + x=a[j] - k * a[p-1-j]; + y=a[p-1-j] - k * a[j]; + + a[j] = x; + a[p-1-j] = y; + + j++; + } + + nb = p & 1; + if (nb) + { + a[j]=a[j]- k * a[p-1-j]; + } + + a[p] = k; + e = e * (1.0f - k*k); + + + } + *err = e; +} + +/** + @} end of LD group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_levinson_durbin_q31.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_levinson_durbin_q31.c new file mode 100644 index 00000000..b622418b --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_levinson_durbin_q31.c @@ -0,0 +1,191 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_levinson_durbin_q31.c + * Description: q31 version of Levinson Durbin algorithm + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +#define ONE_Q31 0x7FFFFFFFL +#define TWO_Q30 0x7FFFFFFFL + +#define HALF_Q31 0x00008000L +#define ONE_Q15 0x7FFF +#define HALF_Q15 0x3FFF +#define LOWPART_MASK 0x07FFF + +__STATIC_FORCEINLINE q31_t mul32x16(q31_t a, q15_t b) +{ + q31_t r = ((q63_t)a * (q63_t)b) >> 15; + + return(r); + +} + +__STATIC_FORCEINLINE q31_t mul32x32(q31_t a, q31_t b) +{ + //q31_t r = __SSAT(((q63_t)a * b) >> 31,31); + q31_t r = ((q63_t)a * b) >> 31; + + return(r); + +} + +__STATIC_FORCEINLINE q31_t divide(q31_t n, q31_t d) +{ + riscv_status status; + int16_t shift; + q15_t inverse; + q31_t r; + // We are computing: + // n / d = n / (h + l) where h and l are the high end and low end part. + // 1 / (h + l) = 1 / h (1 - l / h) + // Our division algorithm has a shift. So it is returning a scaled value sh. + // So we need a << shift to convert 1/ sh to 1/h. + // In below code, we are organizing the computation differently. Instead of computing: + // 1 / h (1 - l / h) + // we are computing + // 1 / h (2 - (l + h) / h) + // 1 / h (2 - d / h) + // Also, we are not computing 1/h in Q15 but in Q14. + // 2 is expressed in Q30. + // So at the end of all computation we need a << 2 + + // Result is in Q14 because of use of HALF_Q15 instead of ONE_Q15. + status=riscv_divide_q15(HALF_Q15,d>>16,&inverse,&shift); + (void)status; + + // d is used instead of l + // So we will need to substract to 2 instead of 1. + r = mul32x16(d,inverse); + r = TWO_Q30 - (r << shift); + r = mul32x16(r, inverse); + r = mul32x32(r,n) ; + r = r << (shift + 2); + + return(r); + +} + +/** + @ingroup groupFilters + */ + +/** + @defgroup LD Levinson Durbin Algorithm + + */ + +/** + @addtogroup LD + @{ + */ + +/** + @brief Levinson Durbin + @param[in] phi autocovariance vector starting with lag 0 (length is nbCoefs + 1) + @param[out] a autoregressive coefficients + @param[out] err prediction error (variance) + @param[in] nbCoefs number of autoregressive coefficients + @return none + */ + + + +void riscv_levinson_durbin_q31(const q31_t *phi, + q31_t *a, + q31_t *err, + int nbCoefs) +{ + q31_t e; + + //a[0] = phi[1] / phi[0]; + a[0] = divide(phi[1], phi[0]); + + + //e = phi[0] - phi[1] * a[0]; + e = phi[0] - mul32x32(phi[1],a[0]); + + for(int p=1; p < nbCoefs; p++) + { + q63_t suma=0; + q63_t sumb=0; + q31_t k; + int nb,j; + + for(int i=0; i < p; i++) + { + suma += ((q63_t)a[i] * phi[p - i]); + sumb += ((q63_t)a[i] * phi[i + 1]); + } + + suma = suma >> 31; + sumb = sumb >> 31; + + + + //k = (phi[p+1]-suma)/(phi[0] - sumb); + k = divide(phi[p+1]-(q31_t)suma,phi[0] - (q31_t)sumb); + + + nb = p >> 1; + j=0; + for(int i =0;i < nb ; i++) + { + q31_t x,y; + + //x = a[j] - k * a[p-1-j]; + x = a[j] - mul32x32(k,a[p-1-j]); + + //y = a[p-1-j] - k * a[j]; + y = a[p-1-j] - mul32x32(k , a[j]); + + a[j] = x; + a[p-1-j] = y; + + j++; + } + + nb = p & 1; + if (nb) + { + //a[j] = a[j]- k * a[p-1-j]; + a[j] = a[j] - mul32x32(k,a[p-1-j]); + } + + a[p] = k; + + // e = e * (1 - k*k); + e = mul32x32(e,ONE_Q31 - mul32x32(k,k)); + + + } + *err = e; +} + +/** + @} end of LD group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_lms_f32.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_lms_f32.c new file mode 100644 index 00000000..46ce5426 --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_lms_f32.c @@ -0,0 +1,390 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_lms_f32.c + * Description: Processing function for the floating-point LMS filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @defgroup LMS Least Mean Square (LMS) Filters + + LMS filters are a class of adaptive filters that are able to "learn" an unknown transfer functions. + LMS filters use a gradient descent method in which the filter coefficients are updated based on the instantaneous error signal. + Adaptive filters are often used in communication systems, equalizers, and noise removal. + The NMSIS DSP Library contains LMS filter functions that operate on Q15, Q31, and floating-point data types. + The library also contains normalized LMS filters in which the filter coefficient adaptation is indepedent of the level of the input signal. + + An LMS filter consists of two components as shown below. + The first component is a standard transversal or FIR filter. + The second component is a coefficient update mechanism. + The LMS filter has two input signals. + The "input" feeds the FIR filter while the "reference input" corresponds to the desired output of the FIR filter. + That is, the FIR filter coefficients are updated so that the output of the FIR filter matches the reference input. + The filter coefficient update mechanism is based on the difference between the FIR filter output and the reference input. + This "error signal" tends towards zero as the filter adapts. + The LMS processing functions accept the input and reference input signals and generate the filter output and error signal. + \image html LMS.png "Internal structure of the Least Mean Square filter" + + The functions operate on blocks of data and each call to the function processes + blockSize samples through the filter. + pSrc points to input signal, pRef points to reference signal, + pOut points to output signal and pErr points to error signal. + All arrays contain blockSize values. + + The functions operate on a block-by-block basis. + Internally, the filter coefficients b[n] are updated on a sample-by-sample basis. + The convergence of the LMS filter is slower compared to the normalized LMS algorithm. + + @par Algorithm + The output signal y[n] is computed by a standard FIR filter: + 
+      y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]
+
+ + @par + The error signal equals the difference between the reference signal d[n] and the filter output: + 
+      e[n] = d[n] - y[n].
+
+ + @par + After each sample of the error signal is computed, the filter coefficients b[k] are updated on a sample-by-sample basis: + 
+      b[k] = b[k] + e[n] * mu * x[n-k],  for k=0, 1, ..., numTaps-1
+
+ where mu is the step size and controls the rate of coefficient convergence. + @par + In the APIs, pCoeffs points to a coefficient array of size numTaps. + Coefficients are stored in time reversed order. + @par + 
+     {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ @par + pState points to a state array of size numTaps + blockSize - 1. + Samples in the state buffer are stored in the order: + @par + 
+     {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}
+
+ @par + Note that the length of the state buffer exceeds the length of the coefficient array by blockSize-1 samples. + The increased state buffer length allows circular addressing, which is traditionally used in FIR filters, + to be avoided and yields a significant speed improvement. + The state variables are updated after each block of data is processed. + @par Instance Structure + The coefficients and state variables for a filter are stored together in an instance data structure. + A separate instance structure must be defined for each filter and + coefficient and state arrays cannot be shared among instances. + There are separate instance structure declarations for each of the 3 supported data types. + + @par Initialization Functions + There is also an associated initialization function for each data type. + The initialization function performs the following operations: + - Sets the values of the internal structure fields. + - Zeros out the values in the state buffer. + To do this manually without calling the init function, assign the follow subfields of the instance structure: + numTaps, pCoeffs, mu, postShift (not for f32), pState. Also set all of the values in pState to zero. + + @par + Use of the initialization function is optional. + However, if the initialization function is used, then the instance structure cannot be placed into a const data section. + To place an instance structure into a const data section, the instance structure must be manually initialized. + Set the values in the state buffer to zeros before static initialization. + The code below statically initializes each of the 3 different data type filter instance structures + 
+     riscv_lms_instance_f32 S = {numTaps, pState, pCoeffs, mu};
+     riscv_lms_instance_q31 S = {numTaps, pState, pCoeffs, mu, postShift};
+     riscv_lms_instance_q15 S = {numTaps, pState, pCoeffs, mu, postShift};
+
+ where numTaps is the number of filter coefficients in the filter; pState is the address of the state buffer; + pCoeffs is the address of the coefficient buffer; mu is the step size parameter; and postShift is the shift applied to coefficients. + + @par Fixed-Point Behavior + Care must be taken when using the Q15 and Q31 versions of the LMS filter. + The following issues must be considered: + - Scaling of coefficients + - Overflow and saturation + + @par Scaling of Coefficients + Filter coefficients are represented as fractional values and + coefficients are restricted to lie in the range [-1 +1). + The fixed-point functions have an additional scaling parameter postShift. + At the output of the filter's accumulator is a shift register which shifts the result by postShift bits. + This essentially scales the filter coefficients by 2^postShift and + allows the filter coefficients to exceed the range [+1 -1). + The value of postShift is set by the user based on the expected gain through the system being modeled. + + @par Overflow and Saturation + Overflow and saturation behavior of the fixed-point Q15 and Q31 versions are + described separately as part of the function specific documentation below. + */ + +/** + @addtogroup LMS + @{ + */ + +/** + @brief Processing function for floating-point LMS filter. + @param[in] S points to an instance of the floating-point LMS filter structure + @param[in] pSrc points to the block of input data + @param[in] pRef points to the block of reference data + @param[out] pOut points to the block of output data + @param[out] pErr points to the block of error data + @param[in] blockSize number of samples to process + @return none + */ +void riscv_lms_f32( + const riscv_lms_instance_f32 * S, + const float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *pStateCurnt; /* Points to the current sample of the state */ + float32_t *px, *pb; /* Temporary pointers for state and coefficient buffers */ + float32_t mu = S->mu; /* Adaptive factor */ + float32_t acc, e; /* Accumulator, error */ + float32_t w; /* Weight factor */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t tapCnt, blkCnt; /* Loop counters */ + + /* Initializations of error, difference, Coefficient update */ + e = 0.0f; + w = 0.0f; + + /* S->pState points to state array which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + + /* initialise loop count */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* Copy the new input sample into the state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Initialize pState pointer */ + px = pState; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + + /* Set the accumulator to zero */ + acc = 0.0f; + +#if defined (RISCV_MATH_LOOPUNROLL) && !defined (RISCV_VECTOR) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + acc += (*px++) * (*pb++); + + acc += (*px++) * (*pb++); + + acc += (*px++) * (*pb++); + + acc += (*px++) * (*pb++); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = numTaps; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ +#if defined (RISCV_VECTOR) + uint32_t vblkCnt = numTaps; /* Loop counter */ + size_t l; + vfloat32m8_t vx, vy; + vfloat32m1_t temp00m1; + l = vsetvl_e32m1(1); + temp00m1 = vfmv_v_f_f32m1(0, l); + for (; (l = vsetvl_e32m8(vblkCnt)) > 0; vblkCnt -= l) { + vx = vle32_v_f32m8(px, l); + px += l; + vy = vle32_v_f32m8(pb, l); + pb += l; + acc += vfmv_f_s_f32m1_f32(vfredsum_vs_f32m8_f32m1(temp00m1, vfmul_vv_f32m8(vx, vy, l), temp00m1, l)); + } +#else + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + acc += (*px++) * (*pb++); + + /* Decrement the loop counter */ + tapCnt--; + } +#endif /* defined (RISCV_VECTOR) */ + /* Store the result from accumulator into the destination buffer. */ + *pOut++ = acc; + + /* Compute and store error */ + e = (float32_t) *pRef++ - acc; + *pErr++ = e; + + /* Calculation of Weighting factor for updating filter coefficients */ + w = e * mu; + + /* Initialize pState pointer */ + /* Advance state pointer by 1 for the next sample */ + px = pState++; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + +#if defined (RISCV_MATH_LOOPUNROLL) && !defined (RISCV_VECTOR) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = numTaps >> 2U; + + /* Update filter coefficients */ + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + *pb += w * (*px++); + pb++; + + *pb += w * (*px++); + pb++; + + *pb += w * (*px++); + pb++; + + *pb += w * (*px++); + pb++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = numTaps; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ +#if defined (RISCV_VECTOR) + vblkCnt = numTaps; + for (; (l = vsetvl_e32m8(vblkCnt)) > 0; vblkCnt -= l) { + vx = vle32_v_f32m8(px, l); + px += l; + vse32_v_f32m8 (pb,vfadd_vv_f32m8(vfmul_vf_f32m8(vx, w, l), vle32_v_f32m8(pb, l), l) , l); + pb += l; + } +#else + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + *pb += w * (*px++); + pb++; + + /* Decrement loop counter */ + tapCnt--; + } +#endif /* defined (RISCV_VECTOR) */ + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the start of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the pState buffer */ + pStateCurnt = S->pState; + + /* copy data */ +#if defined (RISCV_MATH_LOOPUNROLL) && !defined (RISCV_VECTOR) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = (numTaps - 1U) >> 2U; + + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = (numTaps - 1U) % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = (numTaps - 1U); + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ +#if defined (RISCV_VECTOR) + uint32_t vblkCnt = (numTaps - 1U); /* Loop counter */ + size_t l; + for (; (l = vsetvl_e32m8(vblkCnt)) > 0; vblkCnt -= l) { + vse32_v_f32m8 (pStateCurnt,vle32_v_f32m8(pState, l) , l); + pState += l; + pStateCurnt += l; + } +#else + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } +#endif /* defined (RISCV_VECTOR) */ +} + +/** + @} end of LMS group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_lms_init_f32.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_lms_init_f32.c new file mode 100644 index 00000000..e22b9965 --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_lms_init_f32.c @@ -0,0 +1,82 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_lms_init_f32.c + * Description: Floating-point LMS filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @addtogroup LMS + @{ + */ + +/** + @brief Initialization function for floating-point LMS filter. + @param[in] S points to an instance of the floating-point LMS filter structure + @param[in] numTaps number of filter coefficients + @param[in] pCoeffs points to coefficient buffer + @param[in] pState points to state buffer + @param[in] mu step size that controls filter coefficient updates + @param[in] blockSize number of samples to process + @return none + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: + 
+     {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ The initial filter coefficients serve as a starting point for the adaptive filter. + pState points to an array of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to riscv_lms_f32(). + */ + +void riscv_lms_init_f32( + riscv_lms_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize) +{ + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always blockSize + numTaps */ + memset(pState, 0, (numTaps + (blockSize - 1)) * sizeof(float32_t)); + + /* Assign state pointer */ + S->pState = pState; + + /* Assign Step size value */ + S->mu = mu; +} + +/** + @} end of LMS group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_lms_init_q15.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_lms_init_q15.c new file mode 100644 index 00000000..aa0c52f4 --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_lms_init_q15.c @@ -0,0 +1,93 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_lms_init_q15.c + * Description: Q15 LMS filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup LMS + @{ + */ + +/** + @brief Initialization function for the Q15 LMS filter. + @param[in] S points to an instance of the Q15 LMS filter structure. + @param[in] numTaps number of filter coefficients. + @param[in] pCoeffs points to coefficient buffer. + @param[in] pState points to state buffer. + @param[in] mu step size that controls filter coefficient updates. + @param[in] blockSize number of samples to process. + @param[in] postShift bit shift applied to coefficients. + @return none + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: + 
+     {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ The initial filter coefficients serve as a starting point for the adaptive filter. + pState points to the array of state variables and size of array is + numTaps+blockSize-1 samples, where blockSize is the number of + input samples processed by each call to riscv_lms_q15(). + */ + +void riscv_lms_init_q15( + riscv_lms_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint32_t postShift) +{ + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always blockSize + numTaps - 1 */ + memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(q15_t)); + + /* Assign state pointer */ + S->pState = pState; + + /* Assign Step size value */ + S->mu = mu; + + /* Assign postShift value to be applied */ + S->postShift = postShift; +} + +/** + @} end of LMS group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_lms_init_q31.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_lms_init_q31.c new file mode 100644 index 00000000..bcedb3b9 --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_lms_init_q31.c @@ -0,0 +1,93 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_lms_init_q31.c + * Description: Q31 LMS filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup LMS + @{ + */ + +/** + @brief Initialization function for Q31 LMS filter. + @param[in] S points to an instance of the Q31 LMS filter structure + @param[in] numTaps number of filter coefficients + @param[in] pCoeffs points to coefficient buffer + @param[in] pState points to state buffer + @param[in] mu step size that controls filter coefficient updates + @param[in] blockSize number of samples to process + @param[in] postShift bit shift applied to coefficients + @return none + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: + 
+     {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ The initial filter coefficients serve as a starting point for the adaptive filter. + pState points to an array of length numTaps+blockSize-1 samples, + where blockSize is the number of input samples processed by each call to + riscv_lms_q31(). + */ + +void riscv_lms_init_q31( + riscv_lms_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint32_t postShift) +{ + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always blockSize + numTaps - 1 */ + memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(q31_t)); + + /* Assign state pointer */ + S->pState = pState; + + /* Assign Step size value */ + S->mu = mu; + + /* Assign postShift value to be applied */ + S->postShift = postShift; +} + +/** + @} end of LMS group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_lms_norm_f32.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_lms_norm_f32.c new file mode 100644 index 00000000..4307e911 --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_lms_norm_f32.c @@ -0,0 +1,407 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_lms_norm_f32.c + * Description: Processing function for the floating-point NLMS filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @defgroup LMS_NORM Normalized LMS Filters + + This set of functions implements a commonly used adaptive filter. + It is related to the Least Mean Square (LMS) adaptive filter and includes an additional normalization + factor which increases the adaptation rate of the filter. + The NMSIS DSP Library contains normalized LMS filter functions that operate on Q15, Q31, and floating-point data types. + + A normalized least mean square (NLMS) filter consists of two components as shown below. + The first component is a standard transversal or FIR filter. + The second component is a coefficient update mechanism. + The NLMS filter has two input signals. + The "input" feeds the FIR filter while the "reference input" corresponds to the desired output of the FIR filter. + That is, the FIR filter coefficients are updated so that the output of the FIR filter matches the reference input. + The filter coefficient update mechanism is based on the difference between the FIR filter output and the reference input. + This "error signal" tends towards zero as the filter adapts. + The NLMS processing functions accept the input and reference input signals and generate the filter output and error signal. + \image html LMS.png "Internal structure of the NLMS adaptive filter" + + The functions operate on blocks of data and each call to the function processes + blockSize samples through the filter. + pSrc points to input signal, pRef points to reference signal, + pOut points to output signal and pErr points to error signal. + All arrays contain blockSize values. + + The functions operate on a block-by-block basis. + Internally, the filter coefficients b[n] are updated on a sample-by-sample basis. + The convergence of the LMS filter is slower compared to the normalized LMS algorithm. + + @par Algorithm + The output signal y[n] is computed by a standard FIR filter: + 
+      y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]
+
+ + @par + The error signal equals the difference between the reference signal d[n] and the filter output: + 
+      e[n] = d[n] - y[n].
+
+ + @par + After each sample of the error signal is computed the instanteous energy of the filter state variables is calculated: + 
+     E = x[n]^2 + x[n-1]^2 + ... + x[n-numTaps+1]^2.
+
+ The filter coefficients b[k] are then updated on a sample-by-sample basis: + 
+      b[k] = b[k] + e[n] * (mu/E) * x[n-k],  for k=0, 1, ..., numTaps-1
+
+ where mu is the step size and controls the rate of coefficient convergence. + @par + In the APIs, pCoeffs points to a coefficient array of size numTaps. + Coefficients are stored in time reversed order. + @par + 
+     {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ @par + pState points to a state array of size numTaps + blockSize - 1. + Samples in the state buffer are stored in the order: + @par + 
+     {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}
+
+ @par + Note that the length of the state buffer exceeds the length of the coefficient array by blockSize-1 samples. + The increased state buffer length allows circular addressing, which is traditionally used in FIR filters, + to be avoided and yields a significant speed improvement. + The state variables are updated after each block of data is processed. + + @par Instance Structure + The coefficients and state variables for a filter are stored together in an instance data structure. + A separate instance structure must be defined for each filter and + coefficient and state arrays cannot be shared among instances. + There are separate instance structure declarations for each of the 3 supported data types. + + @par Initialization Functions + There is also an associated initialization function for each data type. + The initialization function performs the following operations: + - Sets the values of the internal structure fields. + - Zeros out the values in the state buffer. + To do this manually without calling the init function, assign the follow subfields of the instance structure: + numTaps, pCoeffs, mu, energy, x0, pState. Also set all of the values in pState to zero. + For Q7, Q15, and Q31 the following fields must also be initialized; + recipTable, postShift + @par + Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. + @par Fixed-Point Behavior + Care must be taken when using the Q15 and Q31 versions of the normalised LMS filter. + The following issues must be considered: + - Scaling of coefficients + - Overflow and saturation + + @par Scaling of Coefficients (fixed point versions) + Filter coefficients are represented as fractional values and + coefficients are restricted to lie in the range [-1 +1). + The fixed-point functions have an additional scaling parameter postShift. + At the output of the filter's accumulator is a shift register which shifts the result by postShift bits. + This essentially scales the filter coefficients by 2^postShift and + allows the filter coefficients to exceed the range [+1 -1). + The value of postShift is set by the user based on the expected gain through the system being modeled. + + @par Overflow and Saturation (fixed point versions) + Overflow and saturation behavior of the fixed-point Q15 and Q31 versions are + described separately as part of the function specific documentation below. + */ + +/** + @addtogroup LMS_NORM + @{ + */ + +/** + @brief Processing function for floating-point normalized LMS filter. + @param[in] S points to an instance of the floating-point normalized LMS filter structure + @param[in] pSrc points to the block of input data + @param[in] pRef points to the block of reference data + @param[out] pOut points to the block of output data + @param[out] pErr points to the block of error data + @param[in] blockSize number of samples to process + @return none + */ + +void riscv_lms_norm_f32( + riscv_lms_norm_instance_f32 * S, + const float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *pStateCurnt; /* Points to the current sample of the state */ + float32_t *px, *pb; /* Temporary pointers for state and coefficient buffers */ + float32_t mu = S->mu; /* Adaptive factor */ + float32_t acc, e; /* Accumulator, error */ + float32_t w; /* Weight factor */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t tapCnt, blkCnt; /* Loop counters */ + float32_t energy; /* Energy of the input */ + float32_t x0, in; /* Temporary variable to hold input sample and state */ + + /* Initializations of error, difference, Coefficient update */ + e = 0.0f; + w = 0.0f; + + energy = S->energy; + x0 = S->x0; + + /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + + /* initialise loop count */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* Copy the new input sample into the state buffer */ + *pStateCurnt++ = *pSrc; + + /* Initialize pState pointer */ + px = pState; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + + /* Read the sample from input buffer */ + in = *pSrc++; + + /* Update the energy calculation */ + energy -= x0 * x0; + energy += in * in; + + /* Set the accumulator to zero */ + acc = 0.0f; + +#if defined (RISCV_MATH_LOOPUNROLL) && !defined (RISCV_VECTOR) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + acc += (*px++) * (*pb++); + + acc += (*px++) * (*pb++); + + acc += (*px++) * (*pb++); + + acc += (*px++) * (*pb++); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = numTaps; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ +#if defined (RISCV_VECTOR) + uint32_t vblkCnt = numTaps; /* Loop counter */ + size_t l; + vfloat32m8_t vx, vy; + vfloat32m1_t temp00m1,temp01m1,vz; + l = vsetvl_e32m8(vblkCnt); + temp00m1 = vfmv_v_f_f32m1(0, l); + temp01m1 = vfmv_v_f_f32m1(0, l); + for (; (l = vsetvl_e32m8(vblkCnt)) > 0; vblkCnt -= l) { + vx = vle32_v_f32m8(px, l); + px += l; + vy = vle32_v_f32m8(pb, l); + pb += l; + vx = vfmul_vv_f32m8(vx, vy, l); + vz = vfredsum_vs_f32m8_f32m1(temp00m1, vx, temp01m1, l); + acc += vfmv_f_s_f32m1_f32(vz); + } +#else + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + acc += (*px++) * (*pb++); + + /* Decrement the loop counter */ + tapCnt--; + } +#endif /* defined (RISCV_VECTOR) */ + /* Store the result from accumulator into the destination buffer. */ + *pOut++ = acc; + + /* Compute and store error */ + e = (float32_t) *pRef++ - acc; + *pErr++ = e; + + /* Calculation of Weighting factor for updating filter coefficients */ + /* epsilon value 0.000000119209289f */ + w = (e * mu) / (energy + 0.000000119209289f); + + /* Initialize pState pointer */ + px = pState; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + +#if defined (RISCV_MATH_LOOPUNROLL) && !defined (RISCV_VECTOR) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = numTaps >> 2U; + + /* Update filter coefficients */ + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + *pb += w * (*px++); + pb++; + + *pb += w * (*px++); + pb++; + + *pb += w * (*px++); + pb++; + + *pb += w * (*px++); + pb++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = numTaps; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ +#if defined (RISCV_VECTOR) + vblkCnt = numTaps; + for (; (l = vsetvl_e32m8(vblkCnt)) > 0; vblkCnt -= l) { + vx = vle32_v_f32m8(px, l); + px += l; + vse32_v_f32m8 (pb,vfadd_vv_f32m8(vfmul_vf_f32m8(vx, w, l), vle32_v_f32m8(pb, l), l) , l); + pb += l; + } +#else + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + *pb += w * (*px++); + pb++; + + /* Decrement loop counter */ + tapCnt--; + } +#endif /* defined (RISCV_VECTOR) */ + x0 = *pState; + + /* Advance state pointer by 1 for the next sample */ + pState = pState + 1; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Save energy and x0 values for the next frame */ + S->energy = energy; + S->x0 = x0; + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the start of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the pState buffer */ + pStateCurnt = S->pState; + + /* copy data */ +#if defined (RISCV_MATH_LOOPUNROLL) && !defined (RISCV_VECTOR) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = (numTaps - 1U) >> 2U; + + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = (numTaps - 1U) % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = (numTaps - 1U); + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ +#if defined (RISCV_VECTOR) + uint32_t vblkCnt = (numTaps - 1U); /* Loop counter */ + size_t l; + for (; (l = vsetvl_e32m8(vblkCnt)) > 0; vblkCnt -= l) { + vse32_v_f32m8 (pStateCurnt,vle32_v_f32m8(pState, l) , l); + pState += l; + pStateCurnt += l; + } +#else + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } +#endif /* defined (RISCV_VECTOR) */ +} +/** + @} end of LMS_NORM group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_lms_norm_init_f32.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_lms_norm_init_f32.c new file mode 100644 index 00000000..06f96b38 --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_lms_norm_init_f32.c @@ -0,0 +1,93 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_lms_norm_init_f32.c + * Description: Floating-point NLMS filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup LMS_NORM + @{ + */ + +/** + @brief Initialization function for floating-point normalized LMS filter. + @param[in] S points to an instance of the floating-point LMS filter structure + @param[in] numTaps number of filter coefficients + @param[in] pCoeffs points to coefficient buffer + @param[in] pState points to state buffer + @param[in] mu step size that controls filter coefficient updates + @param[in] blockSize number of samples to process + @return none + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: + 
+     {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ The initial filter coefficients serve as a starting point for the adaptive filter. + pState points to an array of length numTaps+blockSize-1 samples, + where blockSize is the number of input samples processed by each call to riscv_lms_norm_f32(). + */ + +void riscv_lms_norm_init_f32( + riscv_lms_norm_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize) +{ + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always blockSize + numTaps - 1 */ + memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(float32_t)); + + /* Assign state pointer */ + S->pState = pState; + + /* Assign Step size value */ + S->mu = mu; + + /* Initialise Energy to zero */ + S->energy = 0.0f; + + /* Initialise x0 to zero */ + S->x0 = 0.0f; +} + +/** + @} end of LMS_NORM group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_lms_norm_init_q15.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_lms_norm_init_q15.c new file mode 100644 index 00000000..ede184df --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_lms_norm_init_q15.c @@ -0,0 +1,99 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_lms_norm_init_q15.c + * Description: Q15 NLMS filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" +#include "riscv_common_tables.h" + +/** + @addtogroup LMS_NORM + @{ + */ + +/** + @brief Initialization function for Q15 normalized LMS filter. + @param[in] S points to an instance of the Q15 normalized LMS filter structure. + @param[in] numTaps number of filter coefficients. + @param[in] pCoeffs points to coefficient buffer. + @param[in] pState points to state buffer. + @param[in] mu step size that controls filter coefficient updates. + @param[in] blockSize number of samples to process. + @param[in] postShift bit shift applied to coefficients. + @return none + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: + 
+     {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ The initial filter coefficients serve as a starting point for the adaptive filter. + pState points to the array of state variables and size of array is + numTaps+blockSize-1 samples, where blockSize is the number of input samples processed + by each call to riscv_lms_norm_q15(). + */ + +void riscv_lms_norm_init_q15( + riscv_lms_norm_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint8_t postShift) +{ + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always blockSize + numTaps - 1 */ + memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(q15_t)); + + /* Assign post Shift value applied to coefficients */ + S->postShift = postShift; + + /* Assign state pointer */ + S->pState = pState; + + /* Assign Step size value */ + S->mu = mu; + + /* Initialize reciprocal pointer table */ + S->recipTable = (q15_t *) riscvRecipTableQ15; + + /* Initialise Energy to zero */ + S->energy = 0; + + /* Initialise x0 to zero */ + S->x0 = 0; +} + +/** + @} end of LMS_NORM group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_lms_norm_init_q31.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_lms_norm_init_q31.c new file mode 100644 index 00000000..9bf1e9ca --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_lms_norm_init_q31.c @@ -0,0 +1,98 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_lms_norm_init_q31.c + * Description: Q31 NLMS filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" +#include "riscv_common_tables.h" + +/** + @addtogroup LMS_NORM + @{ + */ + +/** + @brief Initialization function for Q31 normalized LMS filter. + @param[in] S points to an instance of the Q31 normalized LMS filter structure. + @param[in] numTaps number of filter coefficients. + @param[in] pCoeffs points to coefficient buffer. + @param[in] pState points to state buffer. + @param[in] mu step size that controls filter coefficient updates. + @param[in] blockSize number of samples to process. + @param[in] postShift bit shift applied to coefficients. + @return none + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: + 
+     {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ The initial filter coefficients serve as a starting point for the adaptive filter. + pState points to an array of length numTaps+blockSize-1 samples, + where blockSize is the number of input samples processed by each call to riscv_lms_norm_q31(). + */ + +void riscv_lms_norm_init_q31( + riscv_lms_norm_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint8_t postShift) +{ + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always blockSize + numTaps - 1 */ + memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(q31_t)); + + /* Assign post Shift value applied to coefficients */ + S->postShift = postShift; + + /* Assign state pointer */ + S->pState = pState; + + /* Assign Step size value */ + S->mu = mu; + + /* Initialize reciprocal pointer table */ + S->recipTable = (q31_t *) riscvRecipTableQ31; + + /* Initialise Energy to zero */ + S->energy = 0; + + /* Initialise x0 to zero */ + S->x0 = 0; +} + +/** + @} end of LMS_NORM group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_lms_norm_q15.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_lms_norm_q15.c new file mode 100644 index 00000000..8745bb72 --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_lms_norm_q15.c @@ -0,0 +1,333 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_lms_norm_q15.c + * Description: Processing function for Q15 normalized LMS filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup LMS_NORM + @{ + */ + +/** + @brief Processing function for Q15 normalized LMS filter. + @param[in] S points to an instance of the Q15 normalized LMS filter structure + @param[in] pSrc points to the block of input data + @param[in] pRef points to the block of reference data + @param[out] pOut points to the block of output data + @param[out] pErr points to the block of error data + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + Both coefficients and state variables are represented in 1.15 format and + multiplications yield a 2.30 result. The 2.30 intermediate results are + accumulated in a 64-bit accumulator in 34.30 format. + There is no risk of internal overflow with this approach and the full + precision of intermediate multiplications is preserved. After all additions + have been performed, the accumulator is truncated to 34.15 format by + discarding low 15 bits. Lastly, the accumulator is saturated to yield a + result in 1.15 format. + @par + In this filter, filter coefficients are updated for each sample and the + updation of filter cofficients are saturted. + */ + +void riscv_lms_norm_q15( + riscv_lms_norm_instance_q15 * S, + const q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCurnt; /* Points to the current sample of the state */ + q15_t *px, *pb; /* Temporary pointers for state and coefficient buffers */ + q15_t mu = S->mu; /* Adaptive factor */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t tapCnt, blkCnt; /* Loop counters */ + q63_t acc; /* Accumulator */ + q31_t energy; /* Energy of the input */ + q15_t e = 0, d = 0; /* Error, reference data sample */ + q15_t w = 0, in; /* Weight factor and state */ + q15_t x0; /* Temporary variable to hold input sample */ + q15_t errorXmu, oneByEnergy; /* Temporary variables to store error and mu product and reciprocal of energy */ + q15_t postShift; /* Post shift to be applied to weight after reciprocal calculation */ + q31_t coef; /* Temporary variable for coefficient */ + q31_t acc_l, acc_h; /* Temporary input */ + int32_t lShift = (15 - (int32_t) S->postShift); /* Post shift */ + int32_t uShift = (32 - lShift); + + energy = S->energy; + x0 = S->x0; + + /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + + /* initialise loop count */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* Copy the new input sample into the state buffer */ + *pStateCurnt++ = *pSrc; + + /* Initialize pState pointer */ + px = pState; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + + /* Read the sample from input buffer */ + in = *pSrc++; + + /* Update the energy calculation */ + energy -= (((q31_t) x0 * (x0)) >> 15); + energy += (((q31_t) in * (in)) >> 15); + + /* Set the accumulator to zero */ + acc = 0; + +#if defined (RISCV_MATH_LOOPUNROLL) && !defined (RISCV_VECTOR) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { +#if __RISCV_XLEN == 64 + acc = __RV_SMALDA(acc, read_q15x4_ia (&px), read_q15x4_ia (&pb)); +#else + /* Perform the multiply-accumulate */ + /* acc += b[N] * x[n-N] + b[N-1] * x[n-N-1] */ + acc = __RV_SMALDA(acc, read_q15x2_ia (&px), read_q15x2_ia (&pb)); + acc = __RV_SMALDA(acc, read_q15x2_ia (&px), read_q15x2_ia (&pb)); +#endif /* __RISCV_XLEN == 64 */ + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = numTaps; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ +#if defined (RISCV_VECTOR) + uint32_t vblkCnt = numTaps; + size_t l; + vint16m4_t vx, vy; + vint64m1_t temp00m1,temp01m1,accm1; + l = vsetvl_e64m1(1); + temp00m1 = vmv_v_x_i64m1(0, l); + temp01m1 = vmv_v_x_i64m1(0, l); + for (; (l = vsetvl_e16m4(vblkCnt)) > 0; vblkCnt -= l) { + vx = vle16_v_i16m4(px, l); + px += l; + vy = vle16_v_i16m4(pb, l); + pb += l; + acc += vmv_x_s_i64m1_i64(vwredsum_vs_i32m8_i64m1 ( temp00m1,vwmul_vv_i32m8(vx, vy, l), temp01m1, l)); + } +#else + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + acc += (q63_t) (((q31_t) (*px++) * (*pb++))); + + /* Decrement the loop counter */ + tapCnt--; + } +#endif /* defined (RISCV_VECTOR) */ + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + /* Apply shift for lower part of acc and upper part of acc */ + acc = (uint32_t) acc_l >> lShift | acc_h << uShift; + + /* Converting the result to 1.15 format and saturate the output */ + acc = __SSAT(acc, 16U); + + /* Store the result from accumulator into the destination buffer. */ + *pOut++ = (q15_t) acc; + + /* Compute and store error */ + d = *pRef++; + e = d - (q15_t) acc; + *pErr++ = e; + + /* Calculation of 1/energy */ + postShift = riscv_recip_q15((q15_t) energy + DELTA_Q15, &oneByEnergy, S->recipTable); + + /* Calculation of e * mu value */ + errorXmu = (q15_t) (((q31_t) e * mu) >> 15); + + /* Calculation of (e * mu) * (1/energy) value */ + acc = (((q31_t) errorXmu * oneByEnergy) >> (15 - postShift)); + + /* Weighting factor for the normalized version */ + w = (q15_t) __SSAT((q31_t) acc, 16); + + /* Initialize pState pointer */ + px = pState; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + +#if defined (RISCV_MATH_LOOPUNROLL) && !defined (RISCV_VECTOR) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = numTaps >> 2U; + + /* Update filter coefficients */ + while (tapCnt > 0U) + { + coef = (q31_t) *pb + (((q31_t) w * (*px++)) >> 15); + *pb++ = (q15_t) __SSAT(coef, 16); + + coef = (q31_t) *pb + (((q31_t) w * (*px++)) >> 15); + *pb++ = (q15_t) __SSAT(coef, 16); + + coef = (q31_t) *pb + (((q31_t) w * (*px++)) >> 15); + *pb++ = (q15_t) __SSAT(coef, 16); + + coef = (q31_t) *pb + (((q31_t) w * (*px++)) >> 15); + *pb++ = (q15_t) __SSAT(coef, 16); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = numTaps; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ +#if defined (RISCV_VECTOR) + vblkCnt = numTaps; + for (; (l = vsetvl_e16m4(vblkCnt)) > 0; vblkCnt -= l) { + vx = vle16_v_i16m4(px, l); + px += l; + vy = vle16_v_i16m4(pb, l); + vse16_v_i16m4(pb,vnclip_wx_i16m4(vwadd_wv_i32m8(vsra_vx_i32m8(vwmul_vx_i32m8(vx, w, l),15, l),vy, l),0, l), l); + pb += l; + } +#else + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + coef = (q31_t) *pb + (((q31_t) w * (*px++)) >> 15); + *pb++ = (q15_t) __SSAT(coef, 16); + + /* Decrement loop counter */ + tapCnt--; + } +#endif /* defined (RISCV_VECTOR) */ + x0 = *pState; + + /* Advance state pointer by 1 for the next sample */ + pState = pState + 1; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Save energy and x0 values for the next frame */ + S->energy = (q15_t) energy; + S->x0 = x0; + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the start of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the pState buffer */ + pStateCurnt = S->pState; + + /* copy data */ +#if defined (RISCV_MATH_LOOPUNROLL) && !defined (RISCV_VECTOR) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = (numTaps - 1U) >> 2U; + + while (tapCnt > 0U) + { + write_q15x2_ia (&pStateCurnt, read_q15x2_ia (&pState)); + write_q15x2_ia (&pStateCurnt, read_q15x2_ia (&pState)); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = (numTaps - 1U) % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = (numTaps - 1U); + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ +#if defined (RISCV_VECTOR) + uint32_t vblkCnt = (numTaps - 1U); + size_t l; + for (; (l = vsetvl_e16m4(vblkCnt)) > 0; vblkCnt -= l) { + vse16_v_i16m4(pStateCurnt,vle16_v_i16m4(pState, l), l); + pState += l; + pStateCurnt += l; + } +#else + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } +#endif /* defined (RISCV_VECTOR) */ +} + +/** + @} end of LMS_NORM group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_lms_norm_q31.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_lms_norm_q31.c new file mode 100644 index 00000000..e8d0d91b --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_lms_norm_q31.c @@ -0,0 +1,354 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_lms_norm_q31.c + * Description: Processing function for the Q31 NLMS filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup LMS_NORM + @{ + */ + +/** + @brief Processing function for Q31 normalized LMS filter. + @param[in] S points to an instance of the Q31 normalized LMS filter structure + @param[in] pSrc points to the block of input data + @param[in] pRef points to the block of reference data + @param[out] pOut points to the block of output data + @param[out] pErr points to the block of error data + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The accumulator has a 2.62 format and maintains full precision of the intermediate + multiplication results but provides only a single guard bit. + Thus, if the accumulator result overflows it wraps around rather than clip. + In order to avoid overflows completely the input signal must be scaled down by + log2(numTaps) bits. The reference signal should not be scaled down. + After all multiply-accumulates are performed, the 2.62 accumulator is shifted + and saturated to 1.31 format to yield the final result. + The output signal and error signal are in 1.31 format. + @par + In this filter, filter coefficients are updated for each sample and the + updation of filter cofficients are saturted. + */ + +void riscv_lms_norm_q31( + riscv_lms_norm_instance_q31 * S, + const q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize) +{ + q31_t *pState = S->pState; /* State pointer */ + q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *pStateCurnt; /* Points to the current sample of the state */ + q31_t *px, *pb; /* Temporary pointers for state and coefficient buffers */ + q31_t mu = S->mu; /* Adaptive factor */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t tapCnt, blkCnt; /* Loop counters */ + q63_t acc; /* Accumulator */ + q63_t energy; /* Energy of the input */ + q31_t e = 0; /* Error data sample */ + q31_t w = 0, in; /* Weight factor and state */ + q31_t x0; /* Temporary variable to hold input sample */ + q31_t errorXmu, oneByEnergy; /* Temporary variables to store error and mu product and reciprocal of energy */ + q31_t postShift; /* Post shift to be applied to weight after reciprocal calculation */ + q31_t coef; /* Temporary variable for coef */ + q31_t acc_l, acc_h; /* Temporary input */ + uint32_t uShift = ((uint32_t) S->postShift + 1U); + uint32_t lShift = 32U - uShift; /* Shift to be applied to the output */ +#if __RISCV_XLEN == 64 + q63_t acc064, acc164, acc264; +#endif /* __RISCV_XLEN == 64 */ + energy = S->energy; + x0 = S->x0; + + /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + + /* initialise loop count */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* Copy the new input sample into the state buffer */ + *pStateCurnt++ = *pSrc; + + /* Initialize pState pointer */ + px = pState; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + + /* Read the sample from input buffer */ + in = *pSrc++; + + /* Update the energy calculation */ + energy = (q31_t) ((((q63_t) energy << 32) - (((q63_t) x0 * x0) << 1)) >> 32); + energy = (q31_t) (((((q63_t) in * in) << 1) + (energy << 32)) >> 32); + + /* Set the accumulator to zero */ + acc = 0; + +#if defined (RISCV_MATH_LOOPUNROLL) && !defined (RISCV_VECTOR) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { +#if __RISCV_XLEN == 64 + acc064 = read_q31x2_ia(&px); + acc164 = read_q31x2_ia(&pb); + acc = __RV_KMADA32(acc, acc064, acc164); + acc064 = read_q31x2_ia(&px); + acc164 = read_q31x2_ia(&pb); + acc = __RV_KMADA32(acc, acc064, acc164); +#else + /* Perform the multiply-accumulate */ + /* acc += b[N] * x[n-N] */ + acc += ((q63_t) (*px++)) * (*pb++); + + /* acc += b[N-1] * x[n-N-1] */ + acc += ((q63_t) (*px++)) * (*pb++); + + /* acc += b[N-2] * x[n-N-2] */ + acc += ((q63_t) (*px++)) * (*pb++); + + /* acc += b[N-3] * x[n-N-3] */ + acc += ((q63_t) (*px++)) * (*pb++); +#endif /* __RISCV_XLEN == 64 */ + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = numTaps; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ +#if defined (RISCV_VECTOR) + uint32_t vblkCnt = numTaps; + size_t l; + vint32m4_t vx, vy; + vint64m1_t temp00m1,temp01m1,accm1; + l = vsetvl_e64m1(1); + temp00m1 = vmv_v_x_i64m1(0, l); + temp01m1 = vmv_v_x_i64m1(0, l); + for (; (l = vsetvl_e32m4(vblkCnt)) > 0; vblkCnt -= l) { + vx = vle32_v_i32m4(px, l); + px += l; + vy = vle32_v_i32m4(pb, l); + pb += l; + accm1 = vredsum_vs_i64m8_i64m1 ( temp00m1,vwmul_vv_i64m8(vx, vy, l), temp01m1, l); + acc += vmv_x_s_i64m1_i64(accm1); + } +#else + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + acc += ((q63_t) (*px++)) * (*pb++); + + /* Decrement the loop counter */ + tapCnt--; + } +#endif /* defined (RISCV_VECTOR) */ + /* Converting the result to 1.31 format */ + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + acc = (uint32_t) acc_l >> lShift | acc_h << uShift; + + /* Store the result from accumulator into the destination buffer. */ + *pOut++ = (q31_t) acc; + + /* Compute and store error */ + e = *pRef++ - (q31_t) acc; + *pErr++ = e; + + /* Calculates the reciprocal of energy */ + postShift = riscv_recip_q31(energy + DELTA_Q31, &oneByEnergy, &S->recipTable[0]); + + /* Calculation of product of (e * mu) */ + errorXmu = (q31_t) (((q63_t) e * mu) >> 31); + + /* Weighting factor for the normalized version */ + w = clip_q63_to_q31(((q63_t) errorXmu * oneByEnergy) >> (31 - postShift)); + + /* Initialize pState pointer */ + px = pState; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + +#if defined (RISCV_MATH_LOOPUNROLL) && !defined (RISCV_VECTOR) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = numTaps >> 2U; + + /* Update filter coefficients */ + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + + /* coef is in 2.30 format */ + coef = (q31_t) (((q63_t) w * (*px++)) >> (32)); + /* get coef in 1.31 format by left shifting */ + *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1U)); + /* update coefficient buffer to next coefficient */ + pb++; + + coef = (q31_t) (((q63_t) w * (*px++)) >> (32)); + *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1U)); + pb++; + + coef = (q31_t) (((q63_t) w * (*px++)) >> (32)); + *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1U)); + pb++; + + coef = (q31_t) (((q63_t) w * (*px++)) >> (32)); + *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1U)); + pb++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = numTaps; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ +#if defined (RISCV_VECTOR) + vblkCnt = blockSize; + for (; (l = vsetvl_e32m4(vblkCnt)) > 0; vblkCnt -= l) { + vx = vle32_v_i32m4(px, l); + px += l; + vse32_v_i32m4 (pb,vnclip_wx_i32m4(vwadd_vv_i64m8(vsll_vx_i32m4(vnclip_wx_i32m4(vwmul_vx_i64m8(vx, w, l),32, l),1, l), vle32_v_i32m4(pb, l), l),0, l), l); + pb += l; + } +#else + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + coef = (q31_t) (((q63_t) w * (*px++)) >> (32)); + *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1U)); + pb++; + + /* Decrement loop counter */ + tapCnt--; + } +#endif /* defined (RISCV_VECTOR) */ + /* Read the sample from state buffer */ + x0 = *pState; + + /* Advance state pointer by 1 for the next sample */ + pState = pState + 1; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Save energy and x0 values for the next frame */ + S->energy = (q31_t) energy; + S->x0 = x0; + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the start of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the pState buffer */ + pStateCurnt = S->pState; + + /* copy data */ +#if defined (RISCV_MATH_LOOPUNROLL) && !defined (RISCV_VECTOR) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = (numTaps - 1U) >> 2U; + + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = (numTaps - 1U) % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = (numTaps - 1U); + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ +#if defined (RISCV_VECTOR) + uint32_t vblkCnt = (numTaps - 1U); + size_t l; + for (; (l = vsetvl_e32m4(vblkCnt)) > 0; vblkCnt -= l) { + vse32_v_i32m4(pStateCurnt,vle32_v_i32m4(pState, l), l); + pState += l; + pStateCurnt += l; + } +#else + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } +#endif /* defined (RISCV_VECTOR) */ +} + +/** + @} end of LMS_NORM group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_lms_q15.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_lms_q15.c new file mode 100644 index 00000000..10f59849 --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_lms_q15.c @@ -0,0 +1,298 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_lms_q15.c + * Description: Processing function for Q15 LMS filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup LMS + @{ + */ + +/** + @brief Processing function for Q15 LMS filter. + @param[in] S points to an instance of the Q15 LMS filter structure + @param[in] pSrc points to the block of input data + @param[in] pRef points to the block of reference data + @param[out] pOut points to the block of output data + @param[out] pErr points to the block of error data + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + Lastly, the accumulator is saturated to yield a result in 1.15 format. + @par + In this filter, filter coefficients are updated for each sample and + the updation of filter cofficients are saturted. + */ + +void riscv_lms_q15( + const riscv_lms_instance_q15 * S, + const q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCurnt; /* Points to the current sample of the state */ + q15_t *px, *pb; /* Temporary pointers for state and coefficient buffers */ + q15_t mu = S->mu; /* Adaptive factor */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t tapCnt, blkCnt; /* Loop counters */ + q63_t acc; /* Accumulator */ + q15_t e = 0; /* Error of data sample */ + q15_t alpha; /* Intermediate constant for taps update */ + q31_t coef; /* Temporary variable for coefficient */ + q31_t acc_l, acc_h; /* Temporary input */ + int32_t lShift = (15 - (int32_t) S->postShift); /* Post shift */ + int32_t uShift = (32 - lShift); + + /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + + /* initialise loop count */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* Copy the new input sample into the state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Initialize pState pointer */ + px = pState; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + + /* Set the accumulator to zero */ + acc = 0; + +#if defined (RISCV_MATH_LOOPUNROLL) && !defined (RISCV_VECTOR) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { +#if __RISCV_XLEN == 64 + acc = __RV_SMALDA(acc, read_q15x4_ia (&px), read_q15x4_ia (&pb)); +#else + /* Perform the multiply-accumulate */ + /* acc += b[N] * x[n-N] + b[N-1] * x[n-N-1] */ + acc = __RV_SMALDA(acc, read_q15x2_ia (&px), read_q15x2_ia (&pb)); + acc = __RV_SMALDA(acc, read_q15x2_ia (&px), read_q15x2_ia (&pb)); +#endif /* __RISCV_XLEN == 64 */ + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = numTaps; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ +#if defined (RISCV_VECTOR) + uint32_t vblkCnt = numTaps; + size_t l; + vint16m4_t vx, vy; + vint64m1_t temp00m1,temp01m1,accm1; + l = vsetvl_e64m1(1); + temp00m1 = vmv_v_x_i64m1(0, l); + temp01m1 = vmv_v_x_i64m1(0, l); + for (; (l = vsetvl_e16m4(vblkCnt)) > 0; vblkCnt -= l) { + vx = vle16_v_i16m4(px, l); + px += l; + vy = vle16_v_i16m4(pb, l); + pb += l; + acc += vmv_x_s_i64m1_i64(vwredsum_vs_i32m8_i64m1 ( temp00m1,vwmul_vv_i32m8(vx, vy, l), temp01m1, l)); + } +#else + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + acc += (q63_t) (((q31_t) (*px++) * (*pb++))); + + /* Decrement the loop counter */ + tapCnt--; + } +#endif /* defined (RISCV_VECTOR) */ + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + /* Apply shift for lower part of acc and upper part of acc */ + acc = (uint32_t) acc_l >> lShift | acc_h << uShift; + + /* Converting the result to 1.15 format and saturate the output */ + acc = __SSAT(acc, 16U); + + /* Store the result from accumulator into the destination buffer. */ + *pOut++ = (q15_t) acc; + + /* Compute and store error */ + e = *pRef++ - (q15_t) acc; + *pErr++ = (q15_t) e; + + /* Compute alpha i.e. intermediate constant for taps update */ + alpha = (q15_t) (((q31_t) e * (mu)) >> 15); + + /* Initialize pState pointer */ + /* Advance state pointer by 1 for the next sample */ + px = pState++; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + +#if defined (RISCV_MATH_LOOPUNROLL) && !defined (RISCV_VECTOR) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = numTaps >> 2U; + + /* Update filter coefficients */ + while (tapCnt > 0U) + { + coef = (q31_t) *pb + (((q31_t) alpha * (*px++)) >> 15); + *pb++ = (q15_t) __SSAT((coef), 16); + + coef = (q31_t) *pb + (((q31_t) alpha * (*px++)) >> 15); + *pb++ = (q15_t) __SSAT((coef), 16); + + coef = (q31_t) *pb + (((q31_t) alpha * (*px++)) >> 15); + *pb++ = (q15_t) __SSAT((coef), 16); + + coef = (q31_t) *pb + (((q31_t) alpha * (*px++)) >> 15); + *pb++ = (q15_t) __SSAT((coef), 16); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = numTaps; +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ +#if defined (RISCV_VECTOR) + vblkCnt = numTaps; + for (; (l = vsetvl_e16m4(vblkCnt)) > 0; vblkCnt -= l) { + vx = vle16_v_i16m4(px, l); + px += l; + vy = vle16_v_i16m4(pb, l); + vse16_v_i16m4(pb,vnclip_wx_i16m4(vwadd_wv_i32m8(vsra_vx_i32m8(vwmul_vx_i32m8(vx, alpha, l),15, l),vy, l),0, l), l); + pb += l; + } +#else + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + coef = (q31_t) *pb + (((q31_t) alpha * (*px++)) >> 15); + *pb++ = (q15_t) __SSAT((coef), 16); + + /* Decrement loop counter */ + tapCnt--; + } +#endif /* defined (RISCV_VECTOR) */ + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the start of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the pState buffer */ + pStateCurnt = S->pState; + + /* copy data */ +#if defined (RISCV_MATH_LOOPUNROLL) && !defined (RISCV_VECTOR) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = (numTaps - 1U) >> 2U; + + while (tapCnt > 0U) + { + write_q15x2_ia (&pStateCurnt, read_q15x2_ia (&pState)); + write_q15x2_ia (&pStateCurnt, read_q15x2_ia (&pState)); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = (numTaps - 1U) % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = (numTaps - 1U); + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ +#if defined (RISCV_VECTOR) + uint32_t vblkCnt = (numTaps - 1U); + size_t l; + for (; (l = vsetvl_e16m4(vblkCnt)) > 0; vblkCnt -= l) { + vse16_v_i16m4(pStateCurnt,vle16_v_i16m4(pState, l), l); + pState += l; + pStateCurnt += l; + } +#else + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } +#endif /* defined (RISCV_VECTOR) */ +} + +/** + @} end of LMS group + */ diff --git a/components/nmsis/dsp/src/FilteringFunctions/riscv_lms_q31.c b/components/nmsis/dsp/src/FilteringFunctions/riscv_lms_q31.c new file mode 100644 index 00000000..8ebdf4ac --- /dev/null +++ b/components/nmsis/dsp/src/FilteringFunctions/riscv_lms_q31.c @@ -0,0 +1,326 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_lms_q31.c + * Description: Processing function for the Q31 LMS filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup LMS + @{ + */ + +/** + @brief Processing function for Q31 LMS filter. + @param[in] S points to an instance of the Q31 LMS filter structure. + @param[in] pSrc points to the block of input data. + @param[in] pRef points to the block of reference data. + @param[out] pOut points to the block of output data. + @param[out] pErr points to the block of error data. + @param[in] blockSize number of samples to process. + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The accumulator has a 2.62 format and maintains full precision of the intermediate + multiplication results but provides only a single guard bit. + Thus, if the accumulator result overflows it wraps around rather than clips. + In order to avoid overflows completely the input signal must be scaled down by + log2(numTaps) bits. + The reference signal should not be scaled down. + After all multiply-accumulates are performed, the 2.62 accumulator is shifted + and saturated to 1.31 format to yield the final result. + The output signal and error signal are in 1.31 format. + @par + In this filter, filter coefficients are updated for each sample and + the updation of filter cofficients are saturted. + */ + +void riscv_lms_q31( + const riscv_lms_instance_q31 * S, + const q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize) +{ + q31_t *pState = S->pState; /* State pointer */ + q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *pStateCurnt; /* Points to the current sample of the state */ + q31_t *px, *pb; /* Temporary pointers for state and coefficient buffers */ + q31_t mu = S->mu; /* Adaptive factor */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t tapCnt, blkCnt; /* Loop counters */ + q63_t acc; /* Accumulator */ + q31_t e = 0; /* Error of data sample */ + q31_t alpha; /* Intermediate constant for taps update */ + q31_t coef; /* Temporary variable for coef */ + q31_t acc_l, acc_h; /* Temporary input */ + uint32_t uShift = ((uint32_t) S->postShift + 1U); + uint32_t lShift = 32U - uShift; /* Shift to be applied to the output */ +#if __RISCV_XLEN == 64 + q63_t acc064, acc164, acc264; +#endif /* __RISCV_XLEN == 64 */ + /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + + /* initialise loop count */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* Copy the new input sample into the state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Initialize pState pointer */ + px = pState; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + + /* Set the accumulator to zero */ + acc = 0; + +#if defined (RISCV_MATH_LOOPUNROLL) && !defined (RISCV_VECTOR) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { +#if __RISCV_XLEN == 64 + acc064 = read_q31x2_ia(&px); + acc164 = read_q31x2_ia(&pb); + acc = __RV_KMADA32(acc, acc064, acc164); + acc064 = read_q31x2_ia(&px); + acc164 = read_q31x2_ia(&pb); + acc = __RV_KMADA32(acc, acc064, acc164); +#else + /* Perform the multiply-accumulate */ + /* acc += b[N] * x[n-N] */ + acc += ((q63_t) (*px++)) * (*pb++); + + /* acc += b[N-1] * x[n-N-1] */ + acc += ((q63_t) (*px++)) * (*pb++); + + /* acc += b[N-2] * x[n-N-2] */ + acc += ((q63_t) (*px++)) * (*pb++); + + /* acc += b[N-3] * x[n-N-3] */ + acc += ((q63_t) (*px++)) * (*pb++); +#endif /* __RISCV_XLEN == 64 */ + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = numTaps; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ +#if defined (RISCV_VECTOR) + uint32_t vblkCnt = numTaps; + size_t l; + vint32m4_t vx, vy; + vint64m1_t temp00m1,temp01m1,accm1; + l = vsetvl_e64m1(1); + temp00m1 = vmv_v_x_i64m1(0, l); + temp01m1 = vmv_v_x_i64m1(0, l); + for (; (l = vsetvl_e32m4(vblkCnt)) > 0; vblkCnt -= l) { + vx = vle32_v_i32m4(px, l); + px += l; + vy = vle32_v_i32m4(pb, l); + pb += l; + accm1 = vredsum_vs_i64m8_i64m1 ( temp00m1,vwmul_vv_i64m8(vx, vy, l), temp01m1, l); + acc += vmv_x_s_i64m1_i64(accm1); + } +#else + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + acc += ((q63_t) (*px++)) * (*pb++); + + /* Decrement the loop counter */ + tapCnt--; + } +#endif /* defined (RISCV_VECTOR) */ + /* Converting the result to 1.31 format */ + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + acc = (uint32_t) acc_l >> lShift | acc_h << uShift; + + /* Store the result from accumulator into the destination buffer. */ + *pOut++ = (q31_t) acc; + + /* Compute and store error */ + e = *pRef++ - (q31_t) acc; + *pErr++ = e; + + /* Compute alpha i.e. intermediate constant for taps update */ + alpha = (q31_t) (((q63_t) e * mu) >> 31); + + /* Initialize pState pointer */ + /* Advance state pointer by 1 for the next sample */ + px = pState++; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + +#if defined (RISCV_MATH_LOOPUNROLL) && !defined (RISCV_VECTOR) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = numTaps >> 2U; + + /* Update filter coefficients */ + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + + /* coef is in 2.30 format */ + coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32)); + /* get coef in 1.31 format by left shifting */ + *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1U)); + /* update coefficient buffer to next coefficient */ + pb++; + + coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32)); + *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1U)); + pb++; + + coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32)); + *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1U)); + pb++; + + coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32)); + *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1U)); + pb++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = numTaps; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ +#if defined (RISCV_VECTOR) + vblkCnt = blockSize; + for (; (l = vsetvl_e32m4(vblkCnt)) > 0; vblkCnt -= l) { + vx = vle32_v_i32m4(px, l); + px += l; + vse32_v_i32m4 (pb,vnclip_wx_i32m4(vwadd_vv_i64m8(vsll_vx_i32m4(vnclip_wx_i32m4(vwmul_vx_i64m8(vx, alpha, l),32, l),1, l), vle32_v_i32m4(pb, l), l),0, l), l); + pb += l; + } +#else + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32)); + *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1U)); + pb++; + + /* Decrement loop counter */ + tapCnt--; + } +#endif /* defined (RISCV_VECTOR) */ + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the start of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the pState buffer */ + pStateCurnt = S->pState; + + /* copy data */ +#if defined (RISCV_MATH_LOOPUNROLL) && !defined (RISCV_VECTOR) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = (numTaps - 1U) >> 2U; + + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = (numTaps - 1U) % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = (numTaps - 1U); + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ +#if defined (RISCV_VECTOR) + uint32_t vblkCnt = (numTaps - 1U); + size_t l; + for (; (l = vsetvl_e32m4(vblkCnt)) > 0; vblkCnt -= l) { + vse32_v_i32m4(pStateCurnt,vle32_v_i32m4(pState, l), l); + pState += l; + pStateCurnt += l; + } +#else + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } +#endif /* defined (RISCV_VECTOR) */ +} + +/** + @} end of LMS group + */ diff --git a/components/nmsis/dsp/src/InterpolationFunctions/InterpolationFunctions.c b/components/nmsis/dsp/src/InterpolationFunctions/InterpolationFunctions.c new file mode 100644 index 00000000..ed1b6bb6 --- /dev/null +++ b/components/nmsis/dsp/src/InterpolationFunctions/InterpolationFunctions.c @@ -0,0 +1,42 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: InterpolationFunctions.c + * Description: Combination of all interpolation function source files. + * + * $Date: 22. July 2020 + * $Revision: V1.0.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2020 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "riscv_bilinear_interp_f32.c" +#include "riscv_bilinear_interp_q15.c" +#include "riscv_bilinear_interp_q31.c" +#include "riscv_bilinear_interp_q7.c" +#include "riscv_linear_interp_f32.c" +#include "riscv_linear_interp_q15.c" +#include "riscv_linear_interp_q31.c" +#include "riscv_linear_interp_q7.c" +#include "riscv_spline_interp_f32.c" +#include "riscv_spline_interp_init_f32.c" + + + diff --git a/components/nmsis/dsp/src/InterpolationFunctions/InterpolationFunctionsF16.c b/components/nmsis/dsp/src/InterpolationFunctions/InterpolationFunctionsF16.c new file mode 100644 index 00000000..ff1463ed --- /dev/null +++ b/components/nmsis/dsp/src/InterpolationFunctions/InterpolationFunctionsF16.c @@ -0,0 +1,34 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: InterpolationFunctions.c + * Description: Combination of all interpolation function source files. + * + * $Date: 22. July 2020 + * $Revision: V1.0.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2020 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "riscv_bilinear_interp_f16.c" +#include "riscv_linear_interp_f16.c" + + + diff --git a/components/nmsis/dsp/src/InterpolationFunctions/riscv_bilinear_interp_f16.c b/components/nmsis/dsp/src/InterpolationFunctions/riscv_bilinear_interp_f16.c new file mode 100644 index 00000000..844bdb07 --- /dev/null +++ b/components/nmsis/dsp/src/InterpolationFunctions/riscv_bilinear_interp_f16.c @@ -0,0 +1,168 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_bilinear_interp_f16.c + * Description: Floating-point bilinear interpolation + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/interpolation_functions_f16.h" + +#if defined(RISCV_FLOAT16_SUPPORTED) + + +/** + @ingroup groupInterpolation + */ + +/** + * @defgroup BilinearInterpolate Bilinear Interpolation + * + * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. + * The underlying function f(x, y) is sampled on a regular grid and the interpolation process + * determines values between the grid points. + * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. + * Bilinear interpolation is often used in image processing to rescale images. + * The NMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. + * + * Algorithm + * \par + * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. + * For floating-point, the instance structure is defined as: + * 
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float16_t *pData;
+   * } riscv_bilinear_interp_instance_f16;
+   *
+ * + * \par + * where numRows specifies the number of rows in the table; + * numCols specifies the number of columns in the table; + * and pData points to an array of size numRows*numCols values. + * The data table pTable is organized in row order and the supplied data values fall on integer indexes. + * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. + * + * \par + * Let (x, y) specify the desired interpolation point. Then define: + * 
+   *     XF = floor(x)
+   *     YF = floor(y)
+   *
+ * \par + * The interpolated output point is computed as: + * 
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   *
+ * Note that the coordinates (x, y) contain integer and fractional components. + * The integer components specify which portion of the table to use while the + * fractional components control the interpolation processor. + * + * \par + * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. + */ + + + /** + * @addtogroup BilinearInterpolate + * @{ + */ + + + /** + * @brief Floating-point bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate. + * @param[in] Y interpolation coordinate. + * @return out interpolated value. + */ + float16_t riscv_bilinear_interp_f16( + const riscv_bilinear_interp_instance_f16 * S, + float16_t X, + float16_t Y) + { + float16_t out; + float16_t f00, f01, f10, f11; + float16_t *pData = S->pData; + int32_t xIndex, yIndex, index; + float16_t xdiff, ydiff; + float16_t b1, b2, b3, b4; + + xIndex = (int32_t) X; + yIndex = (int32_t) Y; + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (xIndex < 0 || xIndex > (S->numCols - 2) || yIndex < 0 || yIndex > (S->numRows - 2)) + { + return (0); + } + + /* Calculation of index for two nearest points in X-direction */ + index = (xIndex ) + (yIndex ) * S->numCols; + + + /* Read two nearest points in X-direction */ + f00 = pData[index]; + f01 = pData[index + 1]; + + /* Calculation of index for two nearest points in Y-direction */ + index = (xIndex ) + (yIndex+1) * S->numCols; + + + /* Read two nearest points in Y-direction */ + f10 = pData[index]; + f11 = pData[index + 1]; + + /* Calculation of intermediate values */ + b1 = f00; + b2 = f01 - f00; + b3 = f10 - f00; + b4 = f00 - f01 - f10 + f11; + + /* Calculation of fractional part in X */ + xdiff = X - xIndex; + + /* Calculation of fractional part in Y */ + ydiff = Y - yIndex; + + /* Calculation of bi-linear interpolated output */ + out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; + + /* return to application */ + return (out); + } + + /** + * @} end of BilinearInterpolate group + */ + + +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ + diff --git a/components/nmsis/dsp/src/InterpolationFunctions/riscv_bilinear_interp_f32.c b/components/nmsis/dsp/src/InterpolationFunctions/riscv_bilinear_interp_f32.c new file mode 100644 index 00000000..e93145fb --- /dev/null +++ b/components/nmsis/dsp/src/InterpolationFunctions/riscv_bilinear_interp_f32.c @@ -0,0 +1,162 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_bilinear_interp_f32.c + * Description: Floating-point bilinear interpolation + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/interpolation_functions.h" + +/** + @ingroup groupInterpolation + */ + +/** + * @defgroup BilinearInterpolate Bilinear Interpolation + * + * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. + * The underlying function f(x, y) is sampled on a regular grid and the interpolation process + * determines values between the grid points. + * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. + * Bilinear interpolation is often used in image processing to rescale images. + * The NMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. + * + * Algorithm + * \par + * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. + * For floating-point, the instance structure is defined as: + * 
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } riscv_bilinear_interp_instance_f32;
+   *
+ * + * \par + * where numRows specifies the number of rows in the table; + * numCols specifies the number of columns in the table; + * and pData points to an array of size numRows*numCols values. + * The data table pTable is organized in row order and the supplied data values fall on integer indexes. + * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. + * + * \par + * Let (x, y) specify the desired interpolation point. Then define: + * 
+   *     XF = floor(x)
+   *     YF = floor(y)
+   *
+ * \par + * The interpolated output point is computed as: + * 
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   *
+ * Note that the coordinates (x, y) contain integer and fractional components. + * The integer components specify which portion of the table to use while the + * fractional components control the interpolation processor. + * + * \par + * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. + */ + + + /** + * @addtogroup BilinearInterpolate + * @{ + */ + + + /** + * @brief Floating-point bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate. + * @param[in] Y interpolation coordinate. + * @return out interpolated value. + */ + float32_t riscv_bilinear_interp_f32( + const riscv_bilinear_interp_instance_f32 * S, + float32_t X, + float32_t Y) + { + float32_t out; + float32_t f00, f01, f10, f11; + float32_t *pData = S->pData; + int32_t xIndex, yIndex, index; + float32_t xdiff, ydiff; + float32_t b1, b2, b3, b4; + + xIndex = (int32_t) X; + yIndex = (int32_t) Y; + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (xIndex < 0 || xIndex > (S->numCols - 2) || yIndex < 0 || yIndex > (S->numRows - 2)) + { + return (0); + } + + /* Calculation of index for two nearest points in X-direction */ + index = (xIndex ) + (yIndex ) * S->numCols; + + + /* Read two nearest points in X-direction */ + f00 = pData[index]; + f01 = pData[index + 1]; + + /* Calculation of index for two nearest points in Y-direction */ + index = (xIndex ) + (yIndex+1) * S->numCols; + + + /* Read two nearest points in Y-direction */ + f10 = pData[index]; + f11 = pData[index + 1]; + + /* Calculation of intermediate values */ + b1 = f00; + b2 = f01 - f00; + b3 = f10 - f00; + b4 = f00 - f01 - f10 + f11; + + /* Calculation of fractional part in X */ + xdiff = X - xIndex; + + /* Calculation of fractional part in Y */ + ydiff = Y - yIndex; + + /* Calculation of bi-linear interpolated output */ + out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; + + /* return to application */ + return (out); + } + + /** + * @} end of BilinearInterpolate group + */ + diff --git a/components/nmsis/dsp/src/InterpolationFunctions/riscv_bilinear_interp_q15.c b/components/nmsis/dsp/src/InterpolationFunctions/riscv_bilinear_interp_q15.c new file mode 100644 index 00000000..8e6e0629 --- /dev/null +++ b/components/nmsis/dsp/src/InterpolationFunctions/riscv_bilinear_interp_q15.c @@ -0,0 +1,122 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_linear_interp_q15.c + * Description: Q15 linear interpolation + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/interpolation_functions.h" + +/** + @ingroup groupInterpolation + */ + +/** + * @addtogroup BilinearInterpolate + * @{ + */ + + /** + * @brief Q15 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + q15_t riscv_bilinear_interp_q15( + riscv_bilinear_interp_instance_q15 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q15_t x1, x2, y1, y2; /* Nearest output values */ + q31_t xfract, yfract; /* X, Y fractional parts */ + int32_t rI, cI; /* Row and column indices */ + q15_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numCols - 2) || cI < 0 || cI > (S->numRows - 2)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ + + /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ + /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ + out = (q31_t) (((q63_t) x1 * (0x0FFFFF - xfract)) >> 4U); + acc = ((q63_t) out * (0x0FFFFF - yfract)); + + /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) x2 * (0x0FFFFF - yfract)) >> 4U); + acc += ((q63_t) out * (xfract)); + + /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y1 * (0x0FFFFF - xfract)) >> 4U); + acc += ((q63_t) out * (yfract)); + + /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y2 * (xfract)) >> 4U); + acc += ((q63_t) out * (yfract)); + + /* acc is in 13.51 format and down shift acc by 36 times */ + /* Convert out to 1.15 format */ + return ((q15_t)(acc >> 36)); + } + + + /** + * @} end of BilinearInterpolate group + */ + diff --git a/components/nmsis/dsp/src/InterpolationFunctions/riscv_bilinear_interp_q31.c b/components/nmsis/dsp/src/InterpolationFunctions/riscv_bilinear_interp_q31.c new file mode 100644 index 00000000..0f73c235 --- /dev/null +++ b/components/nmsis/dsp/src/InterpolationFunctions/riscv_bilinear_interp_q31.c @@ -0,0 +1,120 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_linear_interp_q31.c + * Description: Q31 linear interpolation + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/interpolation_functions.h" + +/** + @ingroup groupInterpolation + */ + + +/** + * @addtogroup BilinearInterpolate + * @{ + */ + + /** + * @brief Q31 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + q31_t riscv_bilinear_interp_q31( + riscv_bilinear_interp_instance_q31 * S, + q31_t X, + q31_t Y) + { + q31_t out; /* Temporary output */ + q31_t acc = 0; /* output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q31_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q31_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numCols - 2) || cI < 0 || cI > (S->numRows - 2)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* shift left xfract by 11 to keep 1.31 format */ + xfract = (X & 0x000FFFFF) << 11U; + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + (int32_t)nCols * (cI) ]; + x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1]; + + /* 20 bits for the fractional part */ + /* shift left yfract by 11 to keep 1.31 format */ + yfract = (Y & 0x000FFFFF) << 11U; + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ]; + y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ + out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); + acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); + + /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); + + /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* Convert acc to 1.31(q31) format */ + return ((q31_t)(acc << 2)); + } + + + + /** + * @} end of BilinearInterpolate group + */ + diff --git a/components/nmsis/dsp/src/InterpolationFunctions/riscv_bilinear_interp_q7.c b/components/nmsis/dsp/src/InterpolationFunctions/riscv_bilinear_interp_q7.c new file mode 100644 index 00000000..f62be726 --- /dev/null +++ b/components/nmsis/dsp/src/InterpolationFunctions/riscv_bilinear_interp_q7.c @@ -0,0 +1,118 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_linear_interp_q7.c + * Description: Q7 linear interpolation + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/interpolation_functions.h" + +/** + @ingroup groupInterpolation + */ + + +/** + * @addtogroup BilinearInterpolate + * @{ + */ + +/** + * @brief Q7 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + q7_t riscv_bilinear_interp_q7( + riscv_bilinear_interp_instance_q7 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q7_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q7_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numCols - 2) || cI < 0 || cI > (S->numRows - 2)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ + out = ((x1 * (0xFFFFF - xfract))); + acc = (((q63_t) out * (0xFFFFF - yfract))); + + /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ + out = ((x2 * (0xFFFFF - yfract))); + acc += (((q63_t) out * (xfract))); + + /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y1 * (0xFFFFF - xfract))); + acc += (((q63_t) out * (yfract))); + + /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y2 * (yfract))); + acc += (((q63_t) out * (xfract))); + + /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ + return ((q7_t)(acc >> 40)); + } + + /** + * @} end of BilinearInterpolate group + */ + diff --git a/components/nmsis/dsp/src/InterpolationFunctions/riscv_linear_interp_f16.c b/components/nmsis/dsp/src/InterpolationFunctions/riscv_linear_interp_f16.c new file mode 100644 index 00000000..1c8fdf15 --- /dev/null +++ b/components/nmsis/dsp/src/InterpolationFunctions/riscv_linear_interp_f16.c @@ -0,0 +1,132 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_linear_interp_f16.c + * Description: Floating-point linear interpolation + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/interpolation_functions_f16.h" + +#if defined(RISCV_FLOAT16_SUPPORTED) + + +/** + @ingroup groupInterpolation + */ + +/** + * @defgroup LinearInterpolate Linear Interpolation + * + * Linear interpolation is a method of curve fitting using linear polynomials. + * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line + * + * \par + * \image html LinearInterp.png "Linear interpolation" + * + * \par + * A Linear Interpolate function calculates an output value(y), for the input(x) + * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) + * + * \par Algorithm: + * 
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   *
+ * + * \par + * This set of functions implements Linear interpolation process + * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single + * sample of data and each call to the function returns a single processed value. + * S points to an instance of the Linear Interpolate function data structure. + * x is the input sample value. The functions returns the output value. + * + * \par + * if x is outside of the table boundary, Linear interpolation returns first value of the table + * if x is below input range and returns last value of table if x is above range. + */ + +/** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ + float16_t riscv_linear_interp_f16( + riscv_linear_interp_instance_f16 * S, + float16_t x) + { + float16_t y; + float16_t x0, x1; /* Nearest input values */ + float16_t y0, y1; /* Nearest output values */ + float16_t xSpacing = S->xSpacing; /* spacing between input values */ + int32_t i; /* Index variable */ + float16_t *pYData = S->pYData; /* pointer to output table */ + + /* Calculation of index */ + i = (int32_t) ((x - S->x1) / xSpacing); + + if (i < 0) + { + /* Iniatilize output for below specified range as least output value of table */ + y = pYData[0]; + } + else if ((uint32_t)i >= (S->nValues - 1)) + { + /* Iniatilize output for above specified range as last output value of table */ + y = pYData[S->nValues - 1]; + } + else + { + /* Calculation of nearest input values */ + x0 = S->x1 + i * xSpacing; + x1 = S->x1 + (i + 1) * xSpacing; + + /* Read of nearest output values */ + y0 = pYData[i]; + y1 = pYData[i + 1]; + + /* Calculation of output */ + y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); + + } + + /* returns output value */ + return (y); + } + + /** + * @} end of LinearInterpolate group + */ + + +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ + diff --git a/components/nmsis/dsp/src/InterpolationFunctions/riscv_linear_interp_f32.c b/components/nmsis/dsp/src/InterpolationFunctions/riscv_linear_interp_f32.c new file mode 100644 index 00000000..4b77fb8b --- /dev/null +++ b/components/nmsis/dsp/src/InterpolationFunctions/riscv_linear_interp_f32.c @@ -0,0 +1,126 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_linear_interp_f32.c + * Description: Floating-point linear interpolation + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/interpolation_functions.h" + +/** + @ingroup groupInterpolation + */ + +/** + * @defgroup LinearInterpolate Linear Interpolation + * + * Linear interpolation is a method of curve fitting using linear polynomials. + * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line + * + * \par + * \image html LinearInterp.png "Linear interpolation" + * + * \par + * A Linear Interpolate function calculates an output value(y), for the input(x) + * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) + * + * \par Algorithm: + * 
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   *
+ * + * \par + * This set of functions implements Linear interpolation process + * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single + * sample of data and each call to the function returns a single processed value. + * S points to an instance of the Linear Interpolate function data structure. + * x is the input sample value. The functions returns the output value. + * + * \par + * if x is outside of the table boundary, Linear interpolation returns first value of the table + * if x is below input range and returns last value of table if x is above range. + */ + +/** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ + float32_t riscv_linear_interp_f32( + riscv_linear_interp_instance_f32 * S, + float32_t x) + { + float32_t y; + float32_t x0, x1; /* Nearest input values */ + float32_t y0, y1; /* Nearest output values */ + float32_t xSpacing = S->xSpacing; /* spacing between input values */ + int32_t i; /* Index variable */ + float32_t *pYData = S->pYData; /* pointer to output table */ + + /* Calculation of index */ + i = (int32_t) ((x - S->x1) / xSpacing); + + if (i < 0) + { + /* Iniatilize output for below specified range as least output value of table */ + y = pYData[0]; + } + else if ((uint32_t)i >= (S->nValues - 1)) + { + /* Iniatilize output for above specified range as last output value of table */ + y = pYData[S->nValues - 1]; + } + else + { + /* Calculation of nearest input values */ + x0 = S->x1 + i * xSpacing; + x1 = S->x1 + (i + 1) * xSpacing; + + /* Read of nearest output values */ + y0 = pYData[i]; + y1 = pYData[i + 1]; + + /* Calculation of output */ + y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); + + } + + /* returns output value */ + return (y); + } + + /** + * @} end of LinearInterpolate group + */ + diff --git a/components/nmsis/dsp/src/InterpolationFunctions/riscv_linear_interp_q15.c b/components/nmsis/dsp/src/InterpolationFunctions/riscv_linear_interp_q15.c new file mode 100644 index 00000000..f70e89c0 --- /dev/null +++ b/components/nmsis/dsp/src/InterpolationFunctions/riscv_linear_interp_q15.c @@ -0,0 +1,102 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_linear_interp_q15.c + * Description: Q15 linear interpolation + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/interpolation_functions.h" + +/** + @ingroup groupInterpolation + */ + +/** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * + * @brief Process function for the Q15 Linear Interpolation Function. + * @param[in] pYData pointer to Q15 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + q15_t riscv_linear_interp_q15( + q15_t * pYData, + q31_t x, + uint32_t nValues) + { + q63_t y; /* output */ + q15_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (int32_t)0xFFF00000) >> 20); + + if (index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if (index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 13.35 format */ + y = ((q63_t) y0 * (0xFFFFF - fract)); + + /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ + y += ((q63_t) y1 * (fract)); + + /* convert y to 1.15 format */ + return (q15_t) (y >> 20); + } + } + + + /** + * @} end of LinearInterpolate group + */ + diff --git a/components/nmsis/dsp/src/InterpolationFunctions/riscv_linear_interp_q31.c b/components/nmsis/dsp/src/InterpolationFunctions/riscv_linear_interp_q31.c new file mode 100644 index 00000000..8a659125 --- /dev/null +++ b/components/nmsis/dsp/src/InterpolationFunctions/riscv_linear_interp_q31.c @@ -0,0 +1,104 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_linear_interp_q31.c + * Description: Q31 linear interpolation + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/interpolation_functions.h" + +/** + @ingroup groupInterpolation + */ + + +/** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * + * @brief Process function for the Q31 Linear Interpolation Function. + * @param[in] pYData pointer to Q31 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + q31_t riscv_linear_interp_q31( + q31_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q31_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (q31_t)0xFFF00000) >> 20); + + if (index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if (index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* shift left by 11 to keep fract in 1.31 format */ + fract = (x & 0x000FFFFF) << 11; + + /* Read two nearest output values from the index in 1.31(q31) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 2.30 format */ + y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); + + /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ + y += ((q31_t) (((q63_t) y1 * fract) >> 32)); + + /* Convert y to 1.31 format */ + return (y << 1U); + } + } + + + + /** + * @} end of LinearInterpolate group + */ + diff --git a/components/nmsis/dsp/src/InterpolationFunctions/riscv_linear_interp_q7.c b/components/nmsis/dsp/src/InterpolationFunctions/riscv_linear_interp_q7.c new file mode 100644 index 00000000..2c810ff2 --- /dev/null +++ b/components/nmsis/dsp/src/InterpolationFunctions/riscv_linear_interp_q7.c @@ -0,0 +1,100 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_linear_interp_q7.c + * Description: Q7 linear interpolation + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/interpolation_functions.h" + +/** + @ingroup groupInterpolation + */ + + +/** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * + * @brief Process function for the Q7 Linear Interpolation Function. + * @param[in] pYData pointer to Q7 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + */ + q7_t riscv_linear_interp_q7( + q7_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q7_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + uint32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + if (x < 0) + { + return (pYData[0]); + } + index = (x >> 20) & 0xfff; + + if (index >= (nValues - 1)) + { + return (pYData[nValues - 1]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index and are in 1.7(q7) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ + y = ((y0 * (0xFFFFF - fract))); + + /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ + y += (y1 * fract); + + /* convert y to 1.7(q7) format */ + return (q7_t) (y >> 20); + } + } + /** + * @} end of LinearInterpolate group + */ + diff --git a/components/nmsis/dsp/src/InterpolationFunctions/riscv_spline_interp_f32.c b/components/nmsis/dsp/src/InterpolationFunctions/riscv_spline_interp_f32.c new file mode 100644 index 00000000..8e6cc120 --- /dev/null +++ b/components/nmsis/dsp/src/InterpolationFunctions/riscv_spline_interp_f32.c @@ -0,0 +1,227 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_spline_interp_f32.c + * Description: Floating-point cubic spline interpolation + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/interpolation_functions.h" + +/** + @ingroup groupInterpolation + */ + +/** + @defgroup SplineInterpolate Cubic Spline Interpolation + + Spline interpolation is a method of interpolation where the interpolant + is a piecewise-defined polynomial called "spline". + + @par Introduction + + Given a function f defined on the interval [a,b], a set of n nodes x(i) + where a=x(1) + S1(x) x(1) < x < x(2) + S(x) = ... + Sn-1(x) x(n-1) < x < x(n) + + + where + + 
 
+  Si(x) = a_i+b_i(x-xi)+c_i(x-xi)^2+d_i(x-xi)^3    i=1, ..., n-1
+
+ + @par Algorithm + + Having defined h(i) = x(i+1) - x(i) + + 
+  h(i-1)c(i-1)+2[h(i-1)+h(i)]c(i)+h(i)c(i+1) = 3/h(i)*[a(i+1)-a(i)]-3/h(i-1)*[a(i)-a(i-1)]    i=2, ..., n-1
+
+ + It is possible to write the previous conditions in matrix form (Ax=B). + In order to solve the system two boundary conidtions are needed. + - Natural spline: S1''(x1)=2*c(1)=0 ; Sn''(xn)=2*c(n)=0 + In matrix form: + + 
+  |  1        0         0  ...    0         0           0     ||  c(1)  | |                        0                        |
+  | h(0) 2[h(0)+h(1)] h(1) ...    0         0           0     ||  c(2)  | |      3/h(2)*[a(3)-a(2)]-3/h(1)*[a(2)-a(1)]      |
+  | ...      ...       ... ...   ...       ...         ...    ||  ...   |=|                       ...                       |
+  |  0        0         0  ... h(n-2) 2[h(n-2)+h(n-1)] h(n-1) || c(n-1) | | 3/h(n-1)*[a(n)-a(n-1)]-3/h(n-2)*[a(n-1)-a(n-2)] |
+  |  0        0         0  ...    0         0           1     ||  c(n)  | |                        0                        |
+
+ + - Parabolic runout spline: S1''(x1)=2*c(1)=S2''(x2)=2*c(2) ; Sn-1''(xn-1)=2*c(n-1)=Sn''(xn)=2*c(n) + In matrix form: + + 
+  |  1       -1         0  ...    0         0           0     ||  c(1)  | |                        0                        |
+  | h(0) 2[h(0)+h(1)] h(1) ...    0         0           0     ||  c(2)  | |      3/h(2)*[a(3)-a(2)]-3/h(1)*[a(2)-a(1)]      |
+  | ...      ...       ... ...   ...       ...         ...    ||  ...   |=|                       ...                       |
+  |  0        0         0  ... h(n-2) 2[h(n-2)+h(n-1)] h(n-1) || c(n-1) | | 3/h(n-1)*[a(n)-a(n-1)]-3/h(n-2)*[a(n-1)-a(n-2)] |
+  |  0        0         0  ...    0        -1           1     ||  c(n)  | |                        0                        |
+
+ + A is a tridiagonal matrix (a band matrix of bandwidth 3) of size N=n+1. The factorization + algorithms (A=LU) can be simplified considerably because a large number of zeros appear + in regular patterns. The Crout method has been used: + 1) Solve LZ=B + + 
+  u(1,2) = A(1,2)/A(1,1)
+  z(1)   = B(1)/l(11)
+ 
+  FOR i=2, ..., N-1
+    l(i,i)   = A(i,i)-A(i,i-1)u(i-1,i)
+    u(i,i+1) = a(i,i+1)/l(i,i)
+    z(i)     = [B(i)-A(i,i-1)z(i-1)]/l(i,i)
+  
+  l(N,N) = A(N,N)-A(N,N-1)u(N-1,N)
+  z(N)   = [B(N)-A(N,N-1)z(N-1)]/l(N,N)
+
+ + 2) Solve UX=Z + + 
+  c(N)=z(N)
+  
+  FOR i=N-1, ..., 1
+    c(i)=z(i)-u(i,i+1)c(i+1) 
+
+ + c(i) for i=1, ..., n-1 are needed to compute the n-1 polynomials. + b(i) and d(i) are computed as: + - b(i) = [y(i+1)-y(i)]/h(i)-h(i)*[c(i+1)+2*c(i)]/3 + - d(i) = [c(i+1)-c(i)]/[3*h(i)] + Moreover, a(i)=y(i). + + @par Behaviour outside the given intervals + + It is possible to compute the interpolated vector for x values outside the + input range (xqx(n)). The coefficients used to compute the y values for + xqx(n) the + coefficients used for the last interval. + + */ + +/** + @addtogroup SplineInterpolate + @{ + */ + +/** + * @brief Processing function for the floating-point cubic spline interpolation. + * @param[in] S points to an instance of the floating-point spline structure. + * @param[in] xq points to the x values of the interpolated data points. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples of output data. + */ + +void riscv_spline_f32( + riscv_spline_instance_f32 * S, + const float32_t * xq, + float32_t * pDst, + uint32_t blockSize) +{ + const float32_t * x = S->x; + const float32_t * y = S->y; + int32_t n = S->n_x; + + /* Coefficients (a==y for i<=n-1) */ + float32_t * b = (S->coeffs); + float32_t * c = (S->coeffs)+(n-1); + float32_t * d = (S->coeffs)+(2*(n-1)); + + const float32_t * pXq = xq; + int32_t blkCnt = (int32_t)blockSize; + int32_t blkCnt2; + int32_t i; + float32_t x_sc; + +#if defined(RISCV_VECTOR) + uint32_t blkCnt_v; /* Loop counter */ + size_t l; + float32_t temp_max; + vfloat32m8_t v_x, v_y; + vfloat32m8_t v_a, v_b; + vfloat32m1_t v_temp; + l = vsetvl_e32m1(1); + v_temp = vfsub_vv_f32m1(v_temp, v_temp, l); +#endif + + + /* Create output for x(i) 0 ) + { + x_sc = *pXq++; + + *pDst = y[i]+b[i]*(x_sc-x[i])+c[i]*(x_sc-x[i])*(x_sc-x[i])+d[i]*(x_sc-x[i])*(x_sc-x[i])*(x_sc-x[i]); + + pDst++; + blkCnt--; + } + } + + /* Create output for remaining samples (x>=x(n)) */ + blkCnt2 = blkCnt; +#if defined(RISCV_VECTOR) + blkCnt_v = blkCnt; + l = vsetvl_e32m8(blkCnt_v); + v_a = vfsub_vv_f32m8(v_a,v_a, l); + for (; (l = vsetvl_e32m8(blkCnt_v)) > 0; blkCnt_v -= l) { + v_x = vle32_v_f32m8(pXq, l); + v_x = vfsub_vf_f32m8(v_x,x[i-1], l); + v_y = vfmul_vv_f32m8(v_x,v_x, l); + v_b = vfmul_vv_f32m8(v_y,v_x, l); + v_x = vfadd_vf_f32m8(vfmul_vf_f32m8(v_x,b[i-1], l),y[i-1], l); + v_y = vfadd_vv_f32m8(vfmul_vf_f32m8(v_y,c[i-1], l),vfmul_vf_f32m8(v_b,d[i-1], l), l); + v_x = vfadd_vv_f32m8(v_x,v_y, l); + vse32_v_f32m8(pDst,v_x, l); + pXq += l; + pDst += l; + } +#else + while(blkCnt2 > 0) + { + x_sc = *pXq++; + + *pDst = y[i-1]+b[i-1]*(x_sc-x[i-1])+c[i-1]*(x_sc-x[i-1])*(x_sc-x[i-1])+d[i-1]*(x_sc-x[i-1])*(x_sc-x[i-1])*(x_sc-x[i-1]); + + pDst++; + blkCnt2--; + } +#endif +} +/** + @} end of SplineInterpolate group + */ diff --git a/components/nmsis/dsp/src/InterpolationFunctions/riscv_spline_interp_init_f32.c b/components/nmsis/dsp/src/InterpolationFunctions/riscv_spline_interp_init_f32.c new file mode 100644 index 00000000..f042f3ee --- /dev/null +++ b/components/nmsis/dsp/src/InterpolationFunctions/riscv_spline_interp_init_f32.c @@ -0,0 +1,176 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_spline_interp_init_f32.c + * Description: Floating-point cubic spline initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/interpolation_functions.h" + +/** + @ingroup groupInterpolation + */ + +/** + @addtogroup SplineInterpolate + @{ + + @par Initialization function + + The initialization function takes as input two arrays that the user has to allocate: + coeffs will contain the b, c, and d coefficients for the (n-1) intervals + (n is the number of known points), hence its size must be 3*(n-1); tempBuffer + is temporally used for internal computations and its size is n+n-1. + + @par + + The x input array must be strictly sorted in ascending order and it must + not contain twice the same value (x(i)x = x; + S->y = y; + S->n_x = n; + + /* == Solve LZ=B to obtain z(i) and u(i) == */ + + /* -- Row 1 -- */ + /* B(0) = 0, not computed */ + /* u(1,2) = a(1,2)/a(1,1) = a(1,2) */ + if(type == RISCV_SPLINE_NATURAL) + u[0] = 0; /* a(1,2) = 0 */ + else if(type == RISCV_SPLINE_PARABOLIC_RUNOUT) + u[0] = -1; /* a(1,2) = -1 */ + + z[0] = 0; /* z(1) = B(1)/a(1,1) = 0 always */ + + /* -- Rows 2 to N-1 (N=n+1) -- */ + hm1 = x[1] - x[0]; /* Initialize h(i-1) = h(1) = x(2)-x(1) */ + + for (i=1; i<(int32_t)n-1; i++) + { + /* Compute B(i) */ + hi = x[i+1]-x[i]; + Bi = 3*(y[i+1]-y[i])/hi - 3*(y[i]-y[i-1])/hm1; + + /* l(i) = a(i)-a(i,i-1)*u(i-1) = 2[h(i-1)+h(i)]-h(i-1)*u(i-1) */ + li = 2*(hi+hm1) - hm1*u[i-1]; + + /* u(i) = a(i,i+1)/l(i) = h(i)/l(i) */ + u[i] = hi/li; + + /* z(i) = [B(i)-h(i-1)*z(i-1)]/l(i) */ + z[i] = (Bi-hm1*z[i-1])/li; + + /* Update h(i-1) for next iteration */ + hm1 = hi; + } + + /* -- Row N -- */ + /* l(N) = a(N,N)-a(N,N-1)u(N-1) */ + /* z(N) = [-a(N,N-1)z(N-1)]/l(N) */ + if(type == RISCV_SPLINE_NATURAL) + { + /* li = 1; a(N,N) = 1; a(N,N-1) = 0 */ + z[n-1] = 0; /* a(N,N-1) = 0 */ + } + else if(type == RISCV_SPLINE_PARABOLIC_RUNOUT) + { + li = 1+u[n-2]; /* a(N,N) = 1; a(N,N-1) = -1 */ + z[n-1] = z[n-2]/li; /* a(N,N-1) = -1 */ + } + + /* == Solve UX = Z to obtain c(i) and */ + /* compute b(i) and d(i) from c(i) == */ + + cp1 = z[n-1]; /* Initialize c(i+1) = c(N) = z(N) */ + + for (i=n-2; i>=0; i--) + { + /* c(i) = z(i)-u(i+1)c(i+1) */ + c[i] = z[i]-u[i]*cp1; + + hi = x[i+1]-x[i]; + /* b(i) = [y(i+1)-y(i)]/h(i)-h(i)*[c(i+1)+2*c(i)]/3 */ + b[i] = (y[i+1]-y[i])/hi-hi*(cp1+2*c[i])/3; + + /* d(i) = [c(i+1)-c(i)]/[3*h(i)] */ + d[i] = (cp1-c[i])/(3*hi); + + /* Update c(i+1) for next iteration */ + cp1 = c[i]; + } + + /* == Finally, store the coefficients in the instance == */ + + S->coeffs = coeffs; +} + +/** + @} end of SplineInterpolate group + */ + diff --git a/components/nmsis/dsp/src/MatrixFunctions/MatrixFunctions.c b/components/nmsis/dsp/src/MatrixFunctions/MatrixFunctions.c new file mode 100644 index 00000000..0a31859a --- /dev/null +++ b/components/nmsis/dsp/src/MatrixFunctions/MatrixFunctions.c @@ -0,0 +1,75 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: MatrixFunctions.c + * Description: Combination of all matrix function source files. + * + * $Date: 18. March 2019 + * $Revision: V1.0.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2019 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "riscv_mat_add_f32.c" +#include "riscv_mat_add_q15.c" +#include "riscv_mat_add_q31.c" +#include "riscv_mat_cmplx_mult_f32.c" +#include "riscv_mat_cmplx_mult_q15.c" +#include "riscv_mat_cmplx_mult_q31.c" +#include "riscv_mat_init_f32.c" +#include "riscv_mat_init_q15.c" +#include "riscv_mat_init_q31.c" +#include "riscv_mat_inverse_f32.c" +#include "riscv_mat_inverse_f64.c" +#include "riscv_mat_mult_f64.c" +#include "riscv_mat_mult_f32.c" +#include "riscv_mat_mult_fast_q15.c" +#include "riscv_mat_mult_fast_q31.c" +#include "riscv_mat_mult_q7.c" +#include "riscv_mat_mult_q15.c" +#include "riscv_mat_mult_q31.c" +#include "riscv_mat_scale_f32.c" +#include "riscv_mat_scale_q15.c" +#include "riscv_mat_scale_q31.c" +#include "riscv_mat_sub_f64.c" +#include "riscv_mat_sub_f32.c" +#include "riscv_mat_sub_q15.c" +#include "riscv_mat_sub_q31.c" +#include "riscv_mat_trans_f32.c" +#include "riscv_mat_trans_f64.c" +#include "riscv_mat_trans_q7.c" +#include "riscv_mat_trans_q15.c" +#include "riscv_mat_trans_q31.c" +#include "riscv_mat_vec_mult_f32.c" +#include "riscv_mat_vec_mult_q31.c" +#include "riscv_mat_vec_mult_q15.c" +#include "riscv_mat_vec_mult_q7.c" +#include "riscv_mat_cmplx_trans_f32.c" +#include "riscv_mat_cmplx_trans_q31.c" +#include "riscv_mat_cmplx_trans_q15.c" +#include "riscv_mat_cholesky_f64.c" +#include "riscv_mat_cholesky_f32.c" +#include "riscv_mat_solve_upper_triangular_f32.c" +#include "riscv_mat_solve_lower_triangular_f32.c" +#include "riscv_mat_solve_upper_triangular_f64.c" +#include "riscv_mat_solve_lower_triangular_f64.c" +#include "riscv_mat_ldlt_f32.c" +#include "riscv_mat_ldlt_f64.c" +#include "riscv_mat_init_f64.c" diff --git a/components/nmsis/dsp/src/MatrixFunctions/MatrixFunctionsF16.c b/components/nmsis/dsp/src/MatrixFunctions/MatrixFunctionsF16.c new file mode 100644 index 00000000..1b435a34 --- /dev/null +++ b/components/nmsis/dsp/src/MatrixFunctions/MatrixFunctionsF16.c @@ -0,0 +1,42 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: MatrixFunctions.c + * Description: Combination of all matrix function f16 source files. + * + * $Date: 18. March 2020 + * $Revision: V1.0.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2020 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "riscv_mat_add_f16.c" +#include "riscv_mat_sub_f16.c" +#include "riscv_mat_trans_f16.c" +#include "riscv_mat_scale_f16.c" +#include "riscv_mat_mult_f16.c" +#include "riscv_mat_vec_mult_f16.c" +#include "riscv_mat_cmplx_trans_f16.c" +#include "riscv_mat_cmplx_mult_f16.c" +#include "riscv_mat_inverse_f16.c" +#include "riscv_mat_init_f16.c" +#include "riscv_mat_cholesky_f16.c" +#include "riscv_mat_solve_upper_triangular_f16.c" +#include "riscv_mat_solve_lower_triangular_f16.c" diff --git a/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_add_f16.c b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_add_f16.c new file mode 100644 index 00000000..fd1dc977 --- /dev/null +++ b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_add_f16.c @@ -0,0 +1,145 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_mat_add_f16.c + * Description: Floating-point matrix addition + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions_f16.h" + +#if defined(RISCV_FLOAT16_SUPPORTED) + + +/** + @ingroup groupMatrix + */ + + +/** + @addtogroup MatrixAdd + @{ + */ + + +/** + @brief Floating-point matrix addition. + @param[in] pSrcA points to first input matrix structure + @param[in] pSrcB points to second input matrix structure + @param[out] pDst points to output matrix structure + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_SIZE_MISMATCH : Matrix size check failed + */ + + +riscv_status riscv_mat_add_f16( + const riscv_matrix_instance_f16 * pSrcA, + const riscv_matrix_instance_f16 * pSrcB, + riscv_matrix_instance_f16 * pDst) +{ + float16_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + float16_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + float16_t *pOut = pDst->pData; /* output data matrix pointer */ + + uint32_t numSamples; /* total number of elements in the matrix */ + uint32_t blkCnt; /* loop counters */ + riscv_status status; /* status of matrix addition */ + +#ifdef RISCV_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || + (pSrcA->numCols != pSrcB->numCols) || + (pSrcA->numRows != pDst->numRows) || + (pSrcA->numCols != pDst->numCols) ) + { + /* Set status as RISCV_MATH_SIZE_MISMATCH */ + status = RISCV_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef RISCV_MATH_MATRIX_CHECK */ + + { + /* Total number of samples in input matrix */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) + B(m,n) */ + + /* Add and store result in destination buffer. */ + *pOut++ = *pInA++ + *pInB++; + + *pOut++ = *pInA++ + *pInB++; + + *pOut++ = *pInA++ + *pInB++; + + *pOut++ = *pInA++ + *pInB++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) + B(m,n) */ + + /* Add and store result in destination buffer. */ + *pOut++ = *pInA++ + *pInB++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Set status as RISCV_MATH_SUCCESS */ + status = RISCV_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +/** + @} end of MatrixAdd group + */ + +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ + diff --git a/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_add_f32.c b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_add_f32.c new file mode 100644 index 00000000..8d8f2bc1 --- /dev/null +++ b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_add_f32.c @@ -0,0 +1,165 @@ +/* -------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_mat_add_f32.c + * Description: Floating-point matrix addition + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @defgroup MatrixAdd Matrix Addition + + Adds two matrices. + \image html MatrixAddition.png "Addition of two 3 x 3 matrices" + + The functions check to make sure that + pSrcA, pSrcB, and pDst have the same + number of rows and columns. + */ + +/** + @addtogroup MatrixAdd + @{ + */ + + +/** + @brief Floating-point matrix addition. + @param[in] pSrcA points to first input matrix structure + @param[in] pSrcB points to second input matrix structure + @param[out] pDst points to output matrix structure + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_SIZE_MISMATCH : Matrix size check failed + */ + +riscv_status riscv_mat_add_f32( + const riscv_matrix_instance_f32 * pSrcA, + const riscv_matrix_instance_f32 * pSrcB, + riscv_matrix_instance_f32 * pDst) +{ + float32_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + float32_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + float32_t *pOut = pDst->pData; /* output data matrix pointer */ + + uint32_t numSamples; /* total number of elements in the matrix */ + uint32_t blkCnt; /* loop counters */ + riscv_status status; /* status of matrix addition */ + +#ifdef RISCV_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || + (pSrcA->numCols != pSrcB->numCols) || + (pSrcA->numRows != pDst->numRows) || + (pSrcA->numCols != pDst->numCols) ) + { + /* Set status as RISCV_MATH_SIZE_MISMATCH */ + status = RISCV_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef RISCV_MATH_MATRIX_CHECK */ +#if defined(RISCV_VECTOR) + /* Total number of samples in input matrix */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + blkCnt = numSamples; + size_t l; + vfloat32m8_t vx, vy; + for (; (l = vsetvl_e32m8(blkCnt)) > 0; blkCnt -= l) { + vx = vle32_v_f32m8(pInA, l); + pInA += l; + vy = vle32_v_f32m8(pInB, l); + vse32_v_f32m8 (pOut, vfadd_vv_f32m8(vy, vx, l), l); + pInB += l; + pOut += l; + } + /* Set status as RISCV_MATH_SUCCESS */ + status = RISCV_MATH_SUCCESS; +#else + { + /* Total number of samples in input matrix */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) + B(m,n) */ + + /* Add and store result in destination buffer. */ + *pOut++ = *pInA++ + *pInB++; + + *pOut++ = *pInA++ + *pInB++; + + *pOut++ = *pInA++ + *pInB++; + + *pOut++ = *pInA++ + *pInB++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) + B(m,n) */ + + /* Add and store result in destination buffer. */ + *pOut++ = *pInA++ + *pInB++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Set status as RISCV_MATH_SUCCESS */ + status = RISCV_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +#endif /*defined(RISCV_VECTOR)*/ +} + +/** + @} end of MatrixAdd group + */ diff --git a/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_add_q15.c b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_add_q15.c new file mode 100644 index 00000000..27ad8d54 --- /dev/null +++ b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_add_q15.c @@ -0,0 +1,171 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_mat_add_q15.c + * Description: Q15 matrix addition + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixAdd + @{ + */ + +/** + @brief Q15 matrix addition. + @param[in] pSrcA points to first input matrix structure + @param[in] pSrcB points to second input matrix structure + @param[out] pDst points to output matrix structure + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_SIZE_MISMATCH : Matrix size check failed + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q15 range [0x8000 0x7FFF] are saturated. + */ +riscv_status riscv_mat_add_q15( + const riscv_matrix_instance_q15 * pSrcA, + const riscv_matrix_instance_q15 * pSrcB, + riscv_matrix_instance_q15 * pDst) +{ + q15_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + q15_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + q15_t *pOut = pDst->pData; /* output data matrix pointer */ + + uint32_t numSamples; /* total number of elements in the matrix */ + uint32_t blkCnt; /* loop counters */ + riscv_status status; /* status of matrix addition */ + +#ifdef RISCV_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || + (pSrcA->numCols != pSrcB->numCols) || + (pSrcA->numRows != pDst->numRows) || + (pSrcA->numCols != pDst->numCols) ) + { + /* Set status as RISCV_MATH_SIZE_MISMATCH */ + status = RISCV_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef RISCV_MATH_MATRIX_CHECK */ + /* Set status as RISCV_MATH_SUCCESS */ +#if defined(RISCV_VECTOR) + /* Total number of samples in input matrix */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + blkCnt = numSamples; + size_t l; + vint16m8_t vx, vy; + + for (; (l = vsetvl_e16m8(blkCnt)) > 0; blkCnt -= l) { + vx = vle16_v_i16m8(pInA, l); + pInA += l; + vy = vle16_v_i16m8(pInB, l); + vse16_v_i16m8 (pOut, vsadd_vv_i16m8(vx, vy, l), l); + pInB += l; + pOut += l; + } +#else + status = RISCV_MATH_SUCCESS; + { + /* Total number of samples in input matrix */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) + B(m,n) */ + + /* Add, saturate and store result in destination buffer. */ +#if defined (RISCV_MATH_DSP) +#if __RISCV_XLEN == 64 + write_q15x4_ia(&pOut, __RV_KADD16(read_q15x4_ia(&pInA), read_q15x4_ia(&pInB))); +#else + write_q15x2_ia (&pOut, __QADD16(read_q15x2_ia (&pInA), read_q15x2_ia (&pInB))); + + write_q15x2_ia (&pOut, __QADD16(read_q15x2_ia (&pInA), read_q15x2_ia (&pInB))); +#endif /* __RISCV_XLEN == 64 */ +#else + *pOut++ = (q15_t) __SSAT(((q31_t) *pInA++ + *pInB++), 16); + + *pOut++ = (q15_t) __SSAT(((q31_t) *pInA++ + *pInB++), 16); + + *pOut++ = (q15_t) __SSAT(((q31_t) *pInA++ + *pInB++), 16); + + *pOut++ = (q15_t) __SSAT(((q31_t) *pInA++ + *pInB++), 16); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) + B(m,n) */ + + /* Add, saturate and store result in destination buffer. */ +#if defined (RISCV_MATH_DSP) + *pOut++ = (q15_t) __QADD16(*pInA++, *pInB++); +#else + *pOut++ = (q15_t) __SSAT(((q31_t) *pInA++ + *pInB++), 16); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Set status as RISCV_MATH_SUCCESS */ + status = RISCV_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +#endif /*defined(RISCV_VECTOR)*/ +} + +/** + @} end of MatrixAdd group + */ diff --git a/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_add_q31.c b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_add_q31.c new file mode 100644 index 00000000..cf944496 --- /dev/null +++ b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_add_q31.c @@ -0,0 +1,164 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_mat_add_q31.c + * Description: Q31 matrix addition + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixAdd + @{ + */ + +/** + @brief Q31 matrix addition. + @param[in] pSrcA points to first input matrix structure + @param[in] pSrcB points to second input matrix structure + @param[out] pDst points to output matrix structure + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_SIZE_MISMATCH : Matrix size check failed + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] are saturated. + */ +riscv_status riscv_mat_add_q31( + const riscv_matrix_instance_q31 * pSrcA, + const riscv_matrix_instance_q31 * pSrcB, + riscv_matrix_instance_q31 * pDst) +{ + q31_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + q31_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + q31_t *pOut = pDst->pData; /* output data matrix pointer */ + + uint32_t numSamples; /* total number of elements in the matrix */ + uint32_t blkCnt; /* loop counters */ + riscv_status status; /* status of matrix addition */ + +#ifdef RISCV_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || + (pSrcA->numCols != pSrcB->numCols) || + (pSrcA->numRows != pDst->numRows) || + (pSrcA->numCols != pDst->numCols) ) + { + /* Set status as RISCV_MATH_SIZE_MISMATCH */ + status = RISCV_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef RISCV_MATH_MATRIX_CHECK */ +#if defined(RISCV_VECTOR) + /* Total number of samples in input matrix */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + blkCnt = numSamples; + size_t l; + vint32m4_t vx, vy, vout_fin; + vint64m8_t vout, vout_mm; + for (; (l = vsetvl_e32m4(blkCnt)) > 0; blkCnt -= l) { + vx = vle32_v_i32m4(pInA, l); + pInA += l; + vy = vle32_v_i32m4(pInB, l); + pInB += l; + vout = vwadd_vv_i64m8(vx, vy, l); + vout_mm = vmin_vx_i64m8(vmax_vx_i64m8(vout, 0xffffffff80000000, l),0x7fffffff, l); + vout_fin = vnclip_wx_i32m4(vout_mm, 0U, l); + vse32_v_i32m4 (pOut, vout_fin, l); + pOut += l; + } +#else + /* Set status as RISCV_MATH_SUCCESS */ + status = RISCV_MATH_SUCCESS; + { + /* Total number of samples in input matrix */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) + B(m,n) */ +#if __RISCV_XLEN == 64 + write_q31x2_ia (&pOut, __RV_KADD32(read_q31x2_ia ((q31_t **) &pInA),read_q31x2_ia ((q31_t **) &pInB))); + write_q31x2_ia (&pOut, __RV_KADD32(read_q31x2_ia ((q31_t **) &pInA),read_q31x2_ia ((q31_t **) &pInB))); +#else + /* Add, saturate and store result in destination buffer. */ + *pOut++ = __QADD(*pInA++, *pInB++); + + *pOut++ = __QADD(*pInA++, *pInB++); + + *pOut++ = __QADD(*pInA++, *pInB++); + + *pOut++ = __QADD(*pInA++, *pInB++); +#endif /* __RISCV_XLEN == 64 */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) + B(m,n) */ + + /* Add, saturate and store result in destination buffer. */ + *pOut++ = __QADD(*pInA++, *pInB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Set status as RISCV_MATH_SUCCESS */ + status = RISCV_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +#endif /*defined(RISCV_VECTOR)*/ +} + +/** + @} end of MatrixAdd group + */ diff --git a/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_cholesky_f16.c b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_cholesky_f16.c new file mode 100644 index 00000000..01be0195 --- /dev/null +++ b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_cholesky_f16.c @@ -0,0 +1,126 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_mat_cholesky_f16.c + * Description: Floating-point Cholesky decomposition + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions_f16.h" + +#if defined(RISCV_FLOAT16_SUPPORTED) + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixChol + @{ + */ + +/** + * @brief Floating-point Cholesky decomposition of positive-definite matrix. + * @param[in] pSrc points to the instance of the input floating-point matrix structure. + * @param[out] pDst points to the instance of the output floating-point matrix structure. + * @return The function returns RISCV_MATH_SIZE_MISMATCH, if the dimensions do not match. + * @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_SIZE_MISMATCH : Matrix size check failed + - \ref RISCV_MATH_DECOMPOSITION_FAILURE : Input matrix cannot be decomposed + * @par + * If the matrix is ill conditioned or only semi-definite, then it is better using the LDL^t decomposition. + * The decomposition of A is returning a lower triangular matrix U such that A = U U^t + */ + +riscv_status riscv_mat_cholesky_f16( + const riscv_matrix_instance_f16 * pSrc, + riscv_matrix_instance_f16 * pDst) +{ + + riscv_status status; /* status of matrix inverse */ + + +#ifdef RISCV_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pSrc->numCols) || + (pDst->numRows != pDst->numCols) || + (pSrc->numRows != pDst->numRows) ) + { + /* Set status as RISCV_MATH_SIZE_MISMATCH */ + status = RISCV_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef RISCV_MATH_MATRIX_CHECK */ + + { + int i,j,k; + int n = pSrc->numRows; + float16_t invSqrtVj; + float16_t *pA,*pG; + + pA = pSrc->pData; + pG = pDst->pData; + + + for(i=0 ; i < n ; i++) + { + for(j=i ; j < n ; j++) + { + pG[j * n + i] = pA[j * n + i]; + + for(k=0; k < i ; k++) + { + pG[j * n + i] = pG[j * n + i] - pG[i * n + k] * pG[j * n + k]; + } + } + + if (pG[i * n + i] <= 0.0f) + { + return(RISCV_MATH_DECOMPOSITION_FAILURE); + } + + invSqrtVj = 1.0f/sqrtf(pG[i * n + i]); + for(j=i ; j < n ; j++) + { + pG[j * n + i] = pG[j * n + i] * invSqrtVj ; + } + } + + status = RISCV_MATH_SUCCESS; + + } + + + /* Return to application */ + return (status); +} + + +/** + @} end of MatrixChol group + */ +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ diff --git a/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_cholesky_f32.c b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_cholesky_f32.c new file mode 100644 index 00000000..adb582e5 --- /dev/null +++ b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_cholesky_f32.c @@ -0,0 +1,167 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_mat_cholesky_f32.c + * Description: Floating-point Cholesky decomposition + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @defgroup MatrixChol Cholesky and LDLT decompositions + + Computes the Cholesky or LDL^t decomposition of a matrix. + + + If the input matrix does not have a decomposition, then the + algorithm terminates and returns error status RISCV_MATH_DECOMPOSITION_FAILURE. + */ + +/** + @addtogroup MatrixChol + @{ + */ + +/** + * @brief Floating-point Cholesky decomposition of positive-definite matrix. + * @param[in] pSrc points to the instance of the input floating-point matrix structure. + * @param[out] pDst points to the instance of the output floating-point matrix structure. + * @return The function returns RISCV_MATH_SIZE_MISMATCH, if the dimensions do not match. + * @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_SIZE_MISMATCH : Matrix size check failed + - \ref RISCV_MATH_DECOMPOSITION_FAILURE : Input matrix cannot be decomposed + * @par + * If the matrix is ill conditioned or only semi-definite, then it is better using the LDL^t decomposition. + * The decomposition of A is returning a lower triangular matrix U such that A = U U^t + */ + +riscv_status riscv_mat_cholesky_f32( + const riscv_matrix_instance_f32 * pSrc, + riscv_matrix_instance_f32 * pDst) +{ + + riscv_status status; /* status of matrix inverse */ + + +#ifdef RISCV_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pSrc->numCols) || + (pDst->numRows != pDst->numCols) || + (pSrc->numRows != pDst->numRows) ) + { + /* Set status as RISCV_MATH_SIZE_MISMATCH */ + status = RISCV_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef RISCV_MATH_MATRIX_CHECK */ + + { + int i,j,k; + int n = pSrc->numRows; + float32_t invSqrtVj; + float32_t *pA,*pG; + +#if defined(RISCV_VECTOR) + uint32_t blkCnt; /* Loop counter */ + size_t l; + vfloat32m8_t v_x, v_y; + vfloat32m8_t v_a; + vfloat32m1_t v_temp; + float32_t *pGX; + float32_t *pGY; + ptrdiff_t bstride = 8; + l = vsetvl_e32m1(1); + v_temp = vfsub_vv_f32m1(v_temp, v_temp, l); +#endif + + pA = pSrc->pData; + pG = pDst->pData; + + + for(i=0 ; i < n ; i++) + { + for(j=i ; j < n ; j++) + { +#if defined(RISCV_VECTOR) + if(i==0){ + pG[j * n + i] = pA[j * n + i]; + } + else{ + blkCnt = i; + pGX = pG + i * n; + pGY = pG + j * n; + l = vsetvl_e32m8(blkCnt); + v_a = vfsub_vv_f32m8(v_a,v_a, l); + for (; (l = vsetvl_e32m8(blkCnt)) > 0; blkCnt -= l) { + v_x = vle32_v_f32m8(pGX, l); + v_y = vle32_v_f32m8(pGY, l); + v_a = vfmacc_vv_f32m8(v_a,v_x,v_y, l); + pGX += l; + pGY += l; + } + l = vsetvl_e32m8(i); + pG[j * n + i] = pA[j * n + i] - vfmv_f_s_f32m1_f32(vfredsum_vs_f32m8_f32m1(v_temp,v_a,v_temp, l)); + } +#else + pG[j * n + i] = pA[j * n + i]; + + for(k=0; k < i ; k++) + { + pG[j * n + i] = pG[j * n + i] - pG[i * n + k] * pG[j * n + k]; + } +#endif + } + + if (pG[i * n + i] <= 0.0f) + { + return(RISCV_MATH_DECOMPOSITION_FAILURE); + } + + invSqrtVj = 1.0f/sqrtf(pG[i * n + i]); + for(j=i ; j < n ; j++) + { + pG[j * n + i] = pG[j * n + i] * invSqrtVj ; + } + } + + status = RISCV_MATH_SUCCESS; + + } + + + /* Return to application */ + return (status); +} + +/** + @} end of MatrixChol group + */ diff --git a/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_cholesky_f64.c b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_cholesky_f64.c new file mode 100644 index 00000000..a8339968 --- /dev/null +++ b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_cholesky_f64.c @@ -0,0 +1,154 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_mat_cholesky_f64.c + * Description: Floating-point Cholesky decomposition + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixChol + @{ + */ + +/** + * @brief Floating-point Cholesky decomposition of positive-definite matrix. + * @param[in] pSrc points to the instance of the input floating-point matrix structure. + * @param[out] pDst points to the instance of the output floating-point matrix structure. + * @return The function returns RISCV_MATH_SIZE_MISMATCH, if the dimensions do not match. + * @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_SIZE_MISMATCH : Matrix size check failed + - \ref RISCV_MATH_DECOMPOSITION_FAILURE : Input matrix cannot be decomposed + * @par + * If the matrix is ill conditioned or only semi-definite, then it is better using the LDL^t decomposition. + * The decomposition of A is returning a lower triangular matrix U such that A = U U^t + */ + + +riscv_status riscv_mat_cholesky_f64( + const riscv_matrix_instance_f64 * pSrc, + riscv_matrix_instance_f64 * pDst) +{ + + riscv_status status; /* status of matrix inverse */ + +#if defined(RISCV_VECTOR) && (defined(__riscv_flen) && (__riscv_flen == 64)) + uint32_t blkCnt; /* Loop counter */ + size_t l; + vfloat64m8_t v_x, v_y; + vfloat64m8_t v_a; + vfloat64m1_t v_temp; + float64_t *pGX; + float64_t *pGY; + ptrdiff_t bstride = 8; + l = vsetvl_e64m1(1); + v_temp = vfsub_vv_f64m1(v_temp, v_temp, l); +#endif + +#ifdef RISCV_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pSrc->numCols) || + (pDst->numRows != pDst->numCols) || + (pSrc->numRows != pDst->numRows) ) + { + /* Set status as RISCV_MATH_SIZE_MISMATCH */ + status = RISCV_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef RISCV_MATH_MATRIX_CHECK */ + + { + int i,j,k; + int n = pSrc->numRows; + float64_t invSqrtVj; + float64_t *pA,*pG; + + pA = pSrc->pData; + pG = pDst->pData; + + + for(i=0 ; i < n ; i++) + { + for(j=i ; j < n ; j++) + { +#if defined(RISCV_VECTOR) && (defined(__riscv_flen) && (__riscv_flen == 64)) + if(i==0){ + pG[j * n + i] = pA[j * n + i]; + } + else{ + blkCnt = i; + pGX = pG + i * n; + pGY = pG + j * n; + l = vsetvl_e64m8(blkCnt); + v_a = vfsub_vv_f64m8(v_a,v_a, l); + for (; (l = vsetvl_e64m8(blkCnt)) > 0; blkCnt -= l) { + v_x = vle64_v_f64m8(pGX, l); + v_y = vle64_v_f64m8(pGY, l); + v_a = vfmacc_vv_f64m8(v_a,v_x,v_y, l); + pGX += l; + pGY += l; + } + l = vsetvl_e64m8(i); + pG[j * n + i] = pA[j * n + i] - vfmv_f_s_f64m1_f64(vfredsum_vs_f64m8_f64m1(v_temp,v_a,v_temp, l)); + } +#else + pG[j * n + i] = pA[j * n + i]; + + for(k=0; k < i ; k++) + { + pG[j * n + i] = pG[j * n + i] - pG[i * n + k] * pG[j * n + k]; + } +#endif + } + + if (pG[i * n + i] <= 0.0f) + { + return(RISCV_MATH_DECOMPOSITION_FAILURE); + } + + invSqrtVj = 1.0/sqrt(pG[i * n + i]); + for(j=i ; j < n ; j++) + { + pG[j * n + i] = pG[j * n + i] * invSqrtVj ; + } + } + + status = RISCV_MATH_SUCCESS; + } + /* Return to application */ + return (status); +} + +/** + @} end of MatrixChol group + */ diff --git a/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_cmplx_mult_f16.c b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_cmplx_mult_f16.c new file mode 100644 index 00000000..1acb6aaa --- /dev/null +++ b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_cmplx_mult_f16.c @@ -0,0 +1,284 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_mat_cmplx_mult_f16.c + * Description: Floating-point matrix multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions_f16.h" + +#if defined(RISCV_FLOAT16_SUPPORTED) + + +/** + @ingroup groupMatrix + */ + + +/** + @addtogroup CmplxMatrixMult + @{ + */ + +/** + @brief Floating-point Complex matrix multiplication. + @param[in] pSrcA points to first input complex matrix structure + @param[in] pSrcB points to second input complex matrix structure + @param[out] pDst points to output complex matrix structure + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_SIZE_MISMATCH : Matrix size check failed + */ + + + +riscv_status riscv_mat_cmplx_mult_f16( + const riscv_matrix_instance_f16 * pSrcA, + const riscv_matrix_instance_f16 * pSrcB, + riscv_matrix_instance_f16 * pDst) +{ + float16_t *pIn1 = pSrcA->pData; /* Input data matrix pointer A */ + float16_t *pIn2 = pSrcB->pData; /* Input data matrix pointer B */ + float16_t *pInA = pSrcA->pData; /* Input data matrix pointer A */ + float16_t *pOut = pDst->pData; /* Output data matrix pointer */ + float16_t *px; /* Temporary output data matrix pointer */ + uint16_t numRowsA = pSrcA->numRows; /* Number of rows of input matrix A */ + uint16_t numColsB = pSrcB->numCols; /* Number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* Number of columns of input matrix A */ + _Float16 sumReal, sumImag; /* Accumulator */ + _Float16 a1, b1, c1, d1; + uint32_t col, i = 0U, j, row = numRowsA, colCnt; /* loop counters */ + riscv_status status; /* status of matrix multiplication */ + +#if defined (RISCV_MATH_LOOPUNROLL) + _Float16 a0, b0, c0, d0; +#endif + +#ifdef RISCV_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as RISCV_MATH_SIZE_MISMATCH */ + status = RISCV_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef RISCV_MATH_MATRIX_CHECK */ + + { + /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */ + /* row loop */ + do + { + /* Output pointer is set to starting address of the row being processed */ + px = pOut + 2 * i; + + /* For every row wise process, the column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, the pIn2 pointer is set + ** to the starting address of the pSrcB data */ + pIn2 = pSrcB->pData; + + j = 0U; + + /* column loop */ + do + { + /* Set the variable sum, that acts as accumulator, to zero */ + sumReal = 0.0f16; + sumImag = 0.0f16; + + /* Initiate pointer pIn1 to point to starting address of column being processed */ + pIn1 = pInA; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + colCnt = numColsA >> 2U; + + /* matrix multiplication */ + while (colCnt > 0U) + { + + /* Reading real part of complex matrix A */ + a0 = *pIn1; + + /* Reading real part of complex matrix B */ + c0 = *pIn2; + + /* Reading imaginary part of complex matrix A */ + b0 = *(pIn1 + 1U); + + /* Reading imaginary part of complex matrix B */ + d0 = *(pIn2 + 1U); + + /* Multiply and Accumlates */ + sumReal += a0 * c0; + sumImag += b0 * c0; + + /* update pointers */ + pIn1 += 2U; + pIn2 += 2 * numColsB; + + /* Multiply and Accumlates */ + sumReal -= b0 * d0; + sumImag += a0 * d0; + + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + + /* read real and imag values from pSrcA and pSrcB buffer */ + a1 = *(pIn1 ); + c1 = *(pIn2 ); + b1 = *(pIn1 + 1U); + d1 = *(pIn2 + 1U); + + /* Multiply and Accumlates */ + sumReal += a1 * c1; + sumImag += b1 * c1; + + /* update pointers */ + pIn1 += 2U; + pIn2 += 2 * numColsB; + + /* Multiply and Accumlates */ + sumReal -= b1 * d1; + sumImag += a1 * d1; + + a0 = *(pIn1 ); + c0 = *(pIn2 ); + b0 = *(pIn1 + 1U); + d0 = *(pIn2 + 1U); + + /* Multiply and Accumlates */ + sumReal += a0 * c0; + sumImag += b0 * c0; + + /* update pointers */ + pIn1 += 2U; + pIn2 += 2 * numColsB; + + /* Multiply and Accumlates */ + sumReal -= b0 * d0; + sumImag += a0 * d0; + + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + + a1 = *(pIn1 ); + c1 = *(pIn2 ); + b1 = *(pIn1 + 1U); + d1 = *(pIn2 + 1U); + + /* Multiply and Accumlates */ + sumReal += a1 * c1; + sumImag += b1 * c1; + + /* update pointers */ + pIn1 += 2U; + pIn2 += 2 * numColsB; + + /* Multiply and Accumlates */ + sumReal -= b1 * d1; + sumImag += a1 * d1; + + /* Decrement loop count */ + colCnt--; + } + + /* If the columns of pSrcA is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + colCnt = numColsA % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + colCnt = numColsA; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + a1 = *(pIn1 ); + c1 = *(pIn2 ); + b1 = *(pIn1 + 1U); + d1 = *(pIn2 + 1U); + + /* Multiply and Accumlates */ + sumReal += a1 * c1; + sumImag += b1 * c1; + + /* update pointers */ + pIn1 += 2U; + pIn2 += 2 * numColsB; + + /* Multiply and Accumlates */ + sumReal -= b1 * d1; + sumImag += a1 * d1; + + /* Decrement loop counter */ + colCnt--; + } + + /* Store result in destination buffer */ + *px++ = sumReal; + *px++ = sumImag; + + /* Update pointer pIn2 to point to starting address of next column */ + j++; + pIn2 = pSrcB->pData + 2U * j; + + /* Decrement column loop counter */ + col--; + + } while (col > 0U); + + /* Update pointer pInA to point to starting address of next row */ + i = i + numColsB; + pInA = pInA + 2 * numColsA; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); + + /* Set status as RISCV_MATH_SUCCESS */ + status = RISCV_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + + +/** + @} end of MatrixMult group + */ + +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ + diff --git a/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_cmplx_mult_f32.c b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_cmplx_mult_f32.c new file mode 100644 index 00000000..6e180cea --- /dev/null +++ b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_cmplx_mult_f32.c @@ -0,0 +1,356 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_mat_cmplx_mult_f32.c + * Description: Floating-point matrix multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @defgroup CmplxMatrixMult Complex Matrix Multiplication + + Complex Matrix multiplication is only defined if the number of columns of the + first matrix equals the number of rows of the second matrix. + Multiplying an M x N matrix with an N x P matrix results + in an M x P matrix. + @par + When matrix size checking is enabled, the functions check: + - that the inner dimensions of pSrcA and pSrcB are equal; + - that the size of the output matrix equals the outer dimensions of pSrcA and pSrcB. + */ + + +/** + @addtogroup CmplxMatrixMult + @{ + */ + +/** + @brief Floating-point Complex matrix multiplication. + @param[in] pSrcA points to first input complex matrix structure + @param[in] pSrcB points to second input complex matrix structure + @param[out] pDst points to output complex matrix structure + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_SIZE_MISMATCH : Matrix size check failed + */ +riscv_status riscv_mat_cmplx_mult_f32( + const riscv_matrix_instance_f32 * pSrcA, + const riscv_matrix_instance_f32 * pSrcB, + riscv_matrix_instance_f32 * pDst) +{ + float32_t *pIn1 = pSrcA->pData; /* Input data matrix pointer A */ + float32_t *pIn2 = pSrcB->pData; /* Input data matrix pointer B */ + float32_t *pInA = pSrcA->pData; /* Input data matrix pointer A */ + float32_t *pOut = pDst->pData; /* Output data matrix pointer */ + float32_t *px; /* Temporary output data matrix pointer */ + uint16_t numRowsA = pSrcA->numRows; /* Number of rows of input matrix A */ + uint16_t numColsB = pSrcB->numCols; /* Number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* Number of columns of input matrix A */ + float32_t sumReal, sumImag; /* Accumulator */ + float32_t a1, b1, c1, d1; + uint32_t col, i = 0U, j, row = numRowsA, colCnt; /* loop counters */ + riscv_status status; /* status of matrix multiplication */ + +#if defined (RISCV_MATH_LOOPUNROLL) + float32_t a0, b0, c0, d0; +#endif + +#ifdef RISCV_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as RISCV_MATH_SIZE_MISMATCH */ + status = RISCV_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef RISCV_MATH_MATRIX_CHECK */ + +#if defined(RISCV_VECTOR) + float32_t *pInB = pSrcB->pData; /* Input data matrix pointer A */ + uint16_t blkCnt = numColsA; //number of matrix columns numColsA = numrowB + size_t l,max_l; // max_l is the maximum column elements at a time + ptrdiff_t bstride = 4; // 32bit/8bit = 4 + ptrdiff_t reim_diff = bstride * 2; + ptrdiff_t col_diff = reim_diff * numColsB; //Control the column width of the span + uint16_t colnum,rownum; // How many rowumns and rownum are controlled + vfloat32m8_t v_inAR, v_inBR, v_inAI, v_inBI; + vfloat32m8_t v_RR, v_II, v_RI, v_IR; + vfloat32m8_t vReal, vImag; + l = vsetvl_e32m1(1); + vfloat32m1_t vsumReal = vfmv_s_f_f32m1(vsumReal, 0, l); + vfloat32m1_t vsumImag = vfmv_s_f_f32m1(vsumImag, 0, l); + // max_l = vsetvl_e32m4(32); + px = pOut; +for(rownum = 0;rownum < numRowsA; rownum++) + { + pIn1 = pInA; //backup pointer position + for(colnum = 0;colnum < numColsB; colnum++) + { + blkCnt = numColsA; + pIn2 = pInB; //backup pointer position + sumReal = 0; + sumImag = 0; + l = vsetvl_e32m1(1); + vsumReal = vfmv_s_f_f32m1(vsumReal, 0, l); + vsumImag = vfmv_s_f_f32m1(vsumImag, 0, l); + for (; (l = vsetvl_e32m8(blkCnt)) > 0; blkCnt -= l) //Multiply a row by a column + { + v_inAR = vlse32_v_f32m8(pInA, reim_diff, l); + v_inBR = vlse32_v_f32m8(pInB, col_diff, l); + pInA++; pInB++; + v_inAI = vlse32_v_f32m8(pInA, reim_diff, l); + v_inBI = vlse32_v_f32m8(pInB, col_diff, l); + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + /* Perform multiply-accumulates */ + v_RR = vfmul_vv_f32m8(v_inAR , v_inBR, l); + v_II = vfmul_vv_f32m8(v_inAI , v_inBI, l); + v_RI = vfmul_vv_f32m8(v_inAR , v_inBI, l); + v_IR = vfmul_vv_f32m8(v_inAI , v_inBR, l); + vReal = vfsub_vv_f32m8(v_RR, v_II, l); + vImag = vfadd_vv_f32m8(v_RI, v_IR, l); + vsumReal = vfredsum_vs_f32m8_f32m1(vsumReal, vReal, vsumReal, l); + vsumImag = vfredsum_vs_f32m8_f32m1(vsumImag, vImag, vsumImag, l); + // if(l == max_l) + // { + pInA = pInA+l*2-1; //Pointer to the first element of the next line + pInB = pInB+l*numColsB*4-1; + // } + } + sumReal = vfmv_f_s_f32m1_f32 (vsumReal); + sumImag = vfmv_f_s_f32m1_f32 (vsumImag); + *px = sumReal; + px++; + *px = sumImag; + px++; + pInA = pIn1; + pInB = pIn2;pInB = pInB+2; //Pointer to the first element of the next column for matrix BS + } + pInB = pSrcB->pData; + pInA = pIn1;pInA = pInA+numColsA*2; //Pointer to the first element of the next row for matrix A + } + /* Set status as RISCV_MATH_SUCCESS */ + status = RISCV_MATH_SUCCESS; +#else + + { + /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */ + /* row loop */ + do + { + /* Output pointer is set to starting address of the row being processed */ + px = pOut + 2 * i; + + /* For every row wise process, the column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, the pIn2 pointer is set + ** to the starting address of the pSrcB data */ + pIn2 = pSrcB->pData; + + j = 0U; + + /* column loop */ + do + { + /* Set the variable sum, that acts as accumulator, to zero */ + sumReal = 0.0f; + sumImag = 0.0f; + + /* Initiate pointer pIn1 to point to starting address of column being processed */ + pIn1 = pInA; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + colCnt = numColsA >> 2U; + + /* matrix multiplication */ + while (colCnt > 0U) + { + + /* Reading real part of complex matrix A */ + a0 = *pIn1; + + /* Reading real part of complex matrix B */ + c0 = *pIn2; + + /* Reading imaginary part of complex matrix A */ + b0 = *(pIn1 + 1U); + + /* Reading imaginary part of complex matrix B */ + d0 = *(pIn2 + 1U); + + /* Multiply and Accumlates */ + sumReal += a0 * c0; + sumImag += b0 * c0; + + /* update pointers */ + pIn1 += 2U; + pIn2 += 2 * numColsB; + + /* Multiply and Accumlates */ + sumReal -= b0 * d0; + sumImag += a0 * d0; + + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + + /* read real and imag values from pSrcA and pSrcB buffer */ + a1 = *(pIn1 ); + c1 = *(pIn2 ); + b1 = *(pIn1 + 1U); + d1 = *(pIn2 + 1U); + + /* Multiply and Accumlates */ + sumReal += a1 * c1; + sumImag += b1 * c1; + + /* update pointers */ + pIn1 += 2U; + pIn2 += 2 * numColsB; + + /* Multiply and Accumlates */ + sumReal -= b1 * d1; + sumImag += a1 * d1; + + a0 = *(pIn1 ); + c0 = *(pIn2 ); + b0 = *(pIn1 + 1U); + d0 = *(pIn2 + 1U); + + /* Multiply and Accumlates */ + sumReal += a0 * c0; + sumImag += b0 * c0; + + /* update pointers */ + pIn1 += 2U; + pIn2 += 2 * numColsB; + + /* Multiply and Accumlates */ + sumReal -= b0 * d0; + sumImag += a0 * d0; + + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + + a1 = *(pIn1 ); + c1 = *(pIn2 ); + b1 = *(pIn1 + 1U); + d1 = *(pIn2 + 1U); + + /* Multiply and Accumlates */ + sumReal += a1 * c1; + sumImag += b1 * c1; + + /* update pointers */ + pIn1 += 2U; + pIn2 += 2 * numColsB; + + /* Multiply and Accumlates */ + sumReal -= b1 * d1; + sumImag += a1 * d1; + + /* Decrement loop count */ + colCnt--; + } + + /* If the columns of pSrcA is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + colCnt = numColsA % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + colCnt = numColsA; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + a1 = *(pIn1 ); + c1 = *(pIn2 ); + b1 = *(pIn1 + 1U); + d1 = *(pIn2 + 1U); + + /* Multiply and Accumlates */ + sumReal += a1 * c1; + sumImag += b1 * c1; + + /* update pointers */ + pIn1 += 2U; + pIn2 += 2 * numColsB; + + /* Multiply and Accumlates */ + sumReal -= b1 * d1; + sumImag += a1 * d1; + + /* Decrement loop counter */ + colCnt--; + } + + /* Store result in destination buffer */ + *px++ = sumReal; + *px++ = sumImag; + + /* Update pointer pIn2 to point to starting address of next column */ + j++; + pIn2 = pSrcB->pData + 2U * j; + + /* Decrement column loop counter */ + col--; + + } while (col > 0U); + + /* Update pointer pInA to point to starting address of next row */ + i = i + numColsB; + pInA = pInA + 2 * numColsA; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); + + /* Set status as RISCV_MATH_SUCCESS */ + status = RISCV_MATH_SUCCESS; + } + +#endif /*defined(RISCV_VECTOR)*/ + /* Return to application */ + return (status); +} + + +/** + @} end of MatrixMult group + */ diff --git a/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_cmplx_mult_q15.c b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_cmplx_mult_q15.c new file mode 100644 index 00000000..3f4b9279 --- /dev/null +++ b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_cmplx_mult_q15.c @@ -0,0 +1,414 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_cmplx_mat_mult_q15.c + * Description: Q15 complex matrix multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup CmplxMatrixMult + @{ + */ + +/** + @brief Q15 Complex matrix multiplication. + @param[in] pSrcA points to first input complex matrix structure + @param[in] pSrcB points to second input complex matrix structure + @param[out] pDst points to output complex matrix structure + @param[in] pScratch points to an array for storing intermediate results + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_SIZE_MISMATCH : Matrix size check failed + + @par Conditions for optimum performance + Input, output and state buffers should be aligned by 32-bit + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. The inputs to the + multiplications are in 1.15 format and multiplications yield a 2.30 result. + The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + This approach provides 33 guard bits and there is no risk of overflow. The 34.30 result is then + truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format. + */ +riscv_status riscv_mat_cmplx_mult_q15( + const riscv_matrix_instance_q15 * pSrcA, + const riscv_matrix_instance_q15 * pSrcB, + riscv_matrix_instance_q15 * pDst, + q15_t * pScratch) +{ + q15_t *pSrcBT = pScratch; /* input data matrix pointer for transpose */ + q15_t *pInA = pSrcA->pData; /* input data matrix pointer A of Q15 type */ + q15_t *pInB = pSrcB->pData; /* input data matrix pointer B of Q15 type */ + q15_t *px; /* Temporary output data matrix pointer */ + uint16_t numRowsA = pSrcA->numRows; /* number of rows of input matrix A */ + uint16_t numColsB = pSrcB->numCols; /* number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* number of columns of input matrix A */ + uint16_t numRowsB = pSrcB->numRows; /* number of rows of input matrix A */ + q63_t sumReal, sumImag; /* accumulator */ + uint32_t col, i = 0U, row = numRowsB, colCnt; /* Loop counters */ + riscv_status status; /* Status of matrix multiplication */ + +#if defined (RISCV_MATH_DSP) && !defined (RISCV_VECTOR) +#if __RISCV_XLEN == 64 + q63_t prod164, prod264, pSourceA64, pSourceB64; + q15_t a, b, c, d; +#endif /* __RISCV_XLEN == 64 */ + q31_t prod1, prod2; + q31_t pSourceA, pSourceB; +#else + q15_t a, b, c, d; +#endif /* #if defined (RISCV_MATH_DSP) */ + +#ifdef RISCV_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as RISCV_MATH_SIZE_MISMATCH */ + status = RISCV_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef RISCV_MATH_MATRIX_CHECK */ + +#if defined(RISCV_VECTOR) + q15_t *pIn1 = pSrcA->pData; /* Input data matrix pointer A */ + q15_t *pIn2 = pSrcB->pData; /* Input data matrix pointer B */ + uint16_t blkCnt = numColsA; //number of matrix columns numColsA = numrowB + size_t l,max_l; // max_l is the maximum column elements at a time + ptrdiff_t bstride = 2; // 16bit/8bit = 2 + ptrdiff_t reim_diff = bstride * 2; + ptrdiff_t col_diff = reim_diff * numColsB; //Control the column width of the span + uint16_t colnum,rownum; // How many rowumns and rownum are controlled + vint16m4_t v_inAR, v_inBR, v_inAI, v_inBI; + vint32m8_t v_RR, v_II, v_RI, v_IR; + vint32m8_t vReal, vImag; + l = vsetvl_e16m1(1); + vint64m1_t vsumReal = vmv_s_x_i64m1(vsumReal, 0, l); + vint64m1_t vsumImag = vmv_s_x_i64m1(vsumImag, 0, l); + // max_l = vsetvl_e16m4(32); + q15_t *pOut = pDst->pData; /* Output data matrix pointer */ + px = pOut; +for(rownum = 0;rownum < numRowsA; rownum++) + { + pIn1 = pInA; //backup pointer position + for(colnum = 0;colnum < numColsB; colnum++) + { + blkCnt = numColsA; + pIn2 = pInB; //backup pointer position + sumReal = 0; + sumImag = 0; + l = vsetvl_e16m1(1); + vsumReal = vmv_s_x_i64m1(vsumReal, 0, l); + vsumImag = vmv_s_x_i64m1(vsumImag, 0, l); + for (; (l = vsetvl_e16m4(blkCnt)) > 0; blkCnt -= l) //Multiply a row by a column + { + v_inAR = vlse16_v_i16m4(pInA, reim_diff, l); + v_inBR = vlse16_v_i16m4(pInB, col_diff, l); + pInA++; pInB++; + v_inAI = vlse16_v_i16m4(pInA, reim_diff, l); + v_inBI = vlse16_v_i16m4(pInB, col_diff, l); + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + /* Perform multiply-accumulates */ + v_RR = vwmul_vv_i32m8(v_inAR , v_inBR, l); + v_II = vwmul_vv_i32m8(v_inAI , v_inBI, l); + v_RI = vwmul_vv_i32m8(v_inAR , v_inBI, l); + v_IR = vwmul_vv_i32m8(v_inAI , v_inBR, l); + vReal = vssub_vv_i32m8(v_RR, v_II, l); + vImag = vsadd_vv_i32m8(v_RI, v_IR, l); + vsumReal = vwredsum_vs_i32m8_i64m1(vsumReal, vReal, vsumReal, l); + vsumImag = vwredsum_vs_i32m8_i64m1(vsumImag, vImag, vsumImag, l); + // if(l == max_l) + // { + pInA = pInA+l*2-1; //Pointer to the first element of the next line + pInB = pInB+l*numColsB*4-1; + // } + } + sumReal = vmv_x_s_i64m1_i64 (vsumReal); + sumImag = vmv_x_s_i64m1_i64 (vsumImag); + *px = (q15_t) __SSAT((sumReal >> 15), 16); + px++; + *px = (q15_t) __SSAT((sumImag >> 15), 16); + px++; + pInA = pIn1; + pInB = pIn2;pInB = pInB+2; //Pointer to the first element of the next column for matrix BS + //printf("px=%d\n",px); + } + pInB = pSrcB->pData; + pInA = pIn1;pInA = pInA+numColsA*2; //Pointer to the first element of the next row for matrix A + } + /* Set status as RISCV_MATH_SUCCESS */ + status = RISCV_MATH_SUCCESS; +#else + + { + /* Matrix transpose */ + do + { + /* The pointer px is set to starting address of column being processed */ + px = pSrcBT + i; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Apply loop unrolling and exchange the columns with row elements */ + col = numColsB >> 2; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + a second loop below computes the remaining 1 to 3 samples. */ + while (col > 0U) + { + /* Read two elements from row */ + write_q15x2 (px, read_q15x2_ia (&pInB)); + + /* Update pointer px to point to next row of transposed matrix */ + px += numRowsB * 2; + + /* Read two elements from row */ + write_q15x2 (px, read_q15x2_ia (&pInB)); + + /* Update pointer px to point to next row of transposed matrix */ + px += numRowsB * 2; + + /* Read two elements from row */ + write_q15x2 (px, read_q15x2_ia (&pInB)); + + /* Update pointer px to point to next row of transposed matrix */ + px += numRowsB * 2; + + /* Read two elements from row */ + write_q15x2 (px, read_q15x2_ia (&pInB)); + + /* Update pointer px to point to next row of transposed matrix */ + px += numRowsB * 2; + + /* Decrement column loop counter */ + col--; + } + + /* If the columns of pSrcB is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + col = numColsB % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + col = numColsB; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (col > 0U) + { + /* Read two elements from row */ + write_q15x2 (px, read_q15x2_ia (&pInB)); + + /* Update pointer px to point to next row of transposed matrix */ + px += numRowsB * 2; + + /* Decrement column loop counter */ + col--; + } + + i = i + 2U; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); + + /* Reset variables for usage in following multiplication process */ + row = numRowsA; + i = 0U; + px = pDst->pData; + + /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */ + /* row loop */ + do + { + /* For every row wise process, column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, pIn2 pointer is set to starting address of transposed pSrcB data */ + pInB = pSrcBT; + + /* column loop */ + do + { + /* Set variable sum, that acts as accumulator, to zero */ + sumReal = 0; + sumImag = 0; + + /* Initiate pointer pInA to point to starting address of column being processed */ + pInA = pSrcA->pData + i * 2; + + /* Apply loop unrolling and compute 2 MACs simultaneously. */ + colCnt = numColsA >> 1U; + + /* matrix multiplication */ + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + +#if defined (RISCV_MATH_DSP) +#if __RISCV_XLEN == 64 + pSourceA64 = read_q15x4_ia ((q15_t **) &pInA); + pSourceB64 = read_q15x4_ia ((q15_t **) &pInB); + + prod164 = __RV_SMDRS(pSourceA64, pSourceB64); + prod264 = __RV_KMXDA(pSourceA64, pSourceB64); + + sumReal += (q63_t) ((q31_t) prod164); + sumReal += (q63_t) ((q31_t) (prod164 >> 32)); + sumImag += (q63_t) ((q31_t) prod264); + sumImag += (q63_t) ((q31_t) (prod264 >> 32)); +#else + /* read real and imag values from pSrcA and pSrcB buffer */ + pSourceA = read_q15x2_ia ((q15_t **) &pInA); + pSourceB = read_q15x2_ia ((q15_t **) &pInB); + + /* Multiply and Accumlates */ + prod1 = __RV_SMDRS(pSourceA, pSourceB); + prod2 = __RV_KMXDA(pSourceA, pSourceB); + sumReal += (q63_t) prod1; + sumImag += (q63_t) prod2; + + /* read real and imag values from pSrcA and pSrcB buffer */ + pSourceA = read_q15x2_ia ((q15_t **) &pInA); + pSourceB = read_q15x2_ia ((q15_t **) &pInB); + + /* Multiply and Accumlates */ + prod1 = __RV_SMDRS(pSourceA, pSourceB); + prod2 = __RV_KMXDA(pSourceA, pSourceB); + sumReal += (q63_t) prod1; + sumImag += (q63_t) prod2; +#endif /* __RISCV_XLEN == 64 */ +#else /* #if defined (RISCV_MATH_DSP) */ + + /* read real and imag values from pSrcA buffer */ + a = *pInA; + b = *(pInA + 1U); + /* read real and imag values from pSrcB buffer */ + c = *pInB; + d = *(pInB + 1U); + + /* Multiply and Accumlates */ + sumReal += (q31_t) a *c; + sumImag += (q31_t) a *d; + sumReal -= (q31_t) b *d; + sumImag += (q31_t) b *c; + + /* read next real and imag values from pSrcA buffer */ + a = *(pInA + 2U); + b = *(pInA + 3U); + /* read next real and imag values from pSrcB buffer */ + c = *(pInB + 2U); + d = *(pInB + 3U); + + /* update pointer */ + pInA += 4U; + + /* Multiply and Accumlates */ + sumReal += (q31_t) a * c; + sumImag += (q31_t) a * d; + sumReal -= (q31_t) b * d; + sumImag += (q31_t) b * c; + /* update pointer */ + pInB += 4U; + +#endif /* #if defined (RISCV_MATH_DSP) */ + + /* Decrement loop counter */ + colCnt--; + } + + /* process odd column samples */ + if ((numColsA & 0x1U) > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + +#if defined (RISCV_MATH_DSP) && (__RISCV_XLEN != 64) + /* read real and imag values from pSrcA and pSrcB buffer */ + pSourceA = read_q15x2_ia ((q15_t **) &pInA); + pSourceB = read_q15x2_ia ((q15_t **) &pInB); + + /* Multiply and Accumlates */ + prod1 = __RV_SMDRS(pSourceA, pSourceB); + prod2 = __RV_KMXDA(pSourceA, pSourceB); + sumReal += (q63_t) prod1; + sumImag += (q63_t) prod2; + +#else /* #if defined (RISCV_MATH_DSP) */ + + /* read real and imag values from pSrcA and pSrcB buffer */ + a = *pInA++; + b = *pInA++; + c = *pInB++; + d = *pInB++; + + /* Multiply and Accumlates */ + sumReal += (q31_t) a * c; + sumImag += (q31_t) a * d; + sumReal -= (q31_t) b * d; + sumImag += (q31_t) b * c; + +#endif /* #if defined (RISCV_MATH_DSP) */ + + } + + /* Saturate and store result in destination buffer */ + *px++ = (q15_t) (__SSAT(sumReal >> 15, 16)); + *px++ = (q15_t) (__SSAT(sumImag >> 15, 16)); + + /* Decrement column loop counter */ + col--; + + } while (col > 0U); + + i = i + numColsA; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); + + /* Set status as RISCV_MATH_SUCCESS */ + status = RISCV_MATH_SUCCESS; + } + +#endif /*defined(RISCV_VECTOR)*/ + /* Return to application */ + return (status); +} + +/** + @} end of MatrixMult group + */ diff --git a/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_cmplx_mult_q31.c b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_cmplx_mult_q31.c new file mode 100644 index 00000000..246a35c1 --- /dev/null +++ b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_cmplx_mult_q31.c @@ -0,0 +1,391 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_mat_cmplx_mult_q31.c + * Description: Floating-point matrix multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup CmplxMatrixMult + @{ + */ + +/** + @brief Q31 Complex matrix multiplication. + @param[in] pSrcA points to first input complex matrix structure + @param[in] pSrcB points to second input complex matrix structure + @param[out] pDst points to output complex matrix structure + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_SIZE_MISMATCH : Matrix size check failed + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The accumulator has a 2.62 format and maintains full precision of the intermediate + multiplication results but provides only a single guard bit. There is no saturation + on intermediate additions. Thus, if the accumulator overflows it wraps around and + distorts the result. The input signals should be scaled down to avoid intermediate + overflows. The input is thus scaled down by log2(numColsA) bits + to avoid overflows, as a total of numColsA additions are performed internally. + The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result. + */ +riscv_status riscv_mat_cmplx_mult_q31( + const riscv_matrix_instance_q31 * pSrcA, + const riscv_matrix_instance_q31 * pSrcB, + riscv_matrix_instance_q31 * pDst) +{ + q31_t *pIn1 = pSrcA->pData; /* Input data matrix pointer A */ + q31_t *pIn2 = pSrcB->pData; /* Input data matrix pointer B */ + q31_t *pInA = pSrcA->pData; /* Input data matrix pointer A */ + q31_t *pOut = pDst->pData; /* Output data matrix pointer */ + q31_t *px; /* Temporary output data matrix pointer */ + uint16_t numRowsA = pSrcA->numRows; /* Number of rows of input matrix A */ + uint16_t numColsB = pSrcB->numCols; /* Number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* Number of columns of input matrix A */ + q63_t sumReal, sumImag; /* Accumulator */ + q31_t a1, b1, c1, d1; + uint32_t col, i = 0U, j, row = numRowsA, colCnt; /* loop counters */ + riscv_status status; /* status of matrix multiplication */ +#if defined RISCV_MATH_DSP && (__RISCV_XLEN == 64) + q63_t in164, in264; +#endif /* defined RISCV_MATH_DSP && (__RISCV_XLEN == 64) */ +#if defined (RISCV_MATH_LOOPUNROLL) + q31_t a0, b0, c0, d0; +#endif + +#ifdef RISCV_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as RISCV_MATH_SIZE_MISMATCH */ + status = RISCV_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef RISCV_MATH_MATRIX_CHECK */ + +#if defined(RISCV_VECTOR) + q31_t *pInB = pSrcB->pData; /* Input data matrix pointer A */ + uint16_t blkCnt = numColsA; //number of matrix columns numColsA = numrowB + size_t l,max_l; // max_l is the maximum column elements at a time + ptrdiff_t bstride = 4; // 32bit/8bit = 4 + ptrdiff_t reim_diff = bstride * 2; + ptrdiff_t col_diff = reim_diff * numColsB; //Control the column width of the span + uint16_t colnum,rownum; // How many rowumns and rownum are controlled + vint32m4_t v_inAR, v_inBR, v_inAI, v_inBI; + vint64m8_t v_RR, v_II, v_RI, v_IR; + vint64m8_t vReal, vImag; + l = vsetvl_e32m1(1); + vint64m1_t vsumReal = vmv_s_x_i64m1(vsumReal, 0, l); + vint64m1_t vsumImag = vmv_s_x_i64m1(vsumImag, 0, l); + // max_l = vsetvl_e32m4(32); + px = pOut; +for(rownum = 0;rownum < numRowsA; rownum++) + { + pIn1 = pInA; //backup pointer position + for(colnum = 0;colnum < numColsB; colnum++) + { + blkCnt = numColsA; + pIn2 = pInB; //backup pointer position + sumReal = 0; + sumImag = 0; + l = vsetvl_e32m1(1); + vsumReal = vmv_s_x_i64m1(vsumReal, 0, l); + vsumImag = vmv_s_x_i64m1(vsumImag, 0, l); + for (; (l = vsetvl_e32m4(blkCnt)) > 0; blkCnt -= l) //Multiply a row by a column + { + v_inAR = vlse32_v_i32m4(pInA, reim_diff, l); + v_inBR = vlse32_v_i32m4(pInB, col_diff, l); + pInA++; pInB++; + v_inAI = vlse32_v_i32m4(pInA, reim_diff, l); + v_inBI = vlse32_v_i32m4(pInB, col_diff, l); + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + /* Perform multiply-accumulates */ + v_RR = vwmul_vv_i64m8(v_inAR , v_inBR, l); + v_II = vwmul_vv_i64m8(v_inAI , v_inBI, l); + v_RI = vwmul_vv_i64m8(v_inAR , v_inBI, l); + v_IR = vwmul_vv_i64m8(v_inAI , v_inBR, l); + vReal = vssub_vv_i64m8(v_RR, v_II, l); + vImag = vsadd_vv_i64m8(v_RI, v_IR, l); + vsumReal = vredsum_vs_i64m8_i64m1(vsumReal, vReal, vsumReal, l); + vsumImag = vredsum_vs_i64m8_i64m1(vsumImag, vImag, vsumImag, l); + // if(l == max_l) + // { + pInA = pInA+l*2-1; //Pointer to the first element of the next line + pInB = pInB+l*numColsB*4-1; + // } + } + sumReal = vmv_x_s_i64m1_i64 (vsumReal); + sumImag = vmv_x_s_i64m1_i64 (vsumImag); + *px = (q31_t) clip_q63_to_q31(sumReal >> 31); + px++; + *px = (q31_t) clip_q63_to_q31(sumImag >> 31); + px++; + pInA = pIn1; + pInB = pIn2;pInB = pInB+2; //Pointer to the first element of the next column for matrix BS + //printf("px=%d\n",px); + } + pInB = pSrcB->pData; + pInA = pIn1;pInA = pInA+numColsA*2; //Pointer to the first element of the next row for matrix A + } + /* Set status as RISCV_MATH_SUCCESS */ + status = RISCV_MATH_SUCCESS; +#else + + { + /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */ + /* row loop */ + do + { + /* Output pointer is set to starting address of the row being processed */ + px = pOut + 2 * i; + + /* For every row wise process, the column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, the pIn2 pointer is set + ** to the starting address of the pSrcB data */ + pIn2 = pSrcB->pData; + + j = 0U; + + /* column loop */ + do + { + /* Set the variable sum, that acts as accumulator, to zero */ + sumReal = 0.0; + sumImag = 0.0; + + /* Initiate pointer pIn1 to point to starting address of column being processed */ + pIn1 = pInA; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + colCnt = numColsA >> 2U; + + /* matrix multiplication */ + while (colCnt > 0U) + { +#if __RISCV_XLEN == 64 + in164 = read_q31x2_ia ((q31_t **) &pIn1); + in264 = read_q31x2_ia ((q31_t **) &pIn2); + pIn2 -= 2; + pIn2 += 2 * numColsB; + sumReal = __RV_KMABB32(sumReal, in164, in264); + sumImag = __RV_KMABT32(sumImag, in264, in164); + sumReal -= __RV_SMTT32(in164, in264); + sumImag = __RV_KMABT32(sumImag, in164, in264); + + in164 = read_q31x2_ia ((q31_t **) &pIn1); + in264 = read_q31x2_ia ((q31_t **) &pIn2); + pIn2 -= 2; + pIn2 += 2 * numColsB; + sumReal = __RV_KMABB32(sumReal, in164, in264); + sumImag = __RV_KMABT32(sumImag, in264, in164); + sumReal -= __RV_SMTT32(in164, in264); + sumImag = __RV_KMABT32(sumImag, in164, in264); + + in164 = read_q31x2_ia ((q31_t **) &pIn1); + in264 = read_q31x2_ia ((q31_t **) &pIn2); + pIn2 -= 2; + pIn2 += 2 * numColsB; + sumReal = __RV_KMABB32(sumReal, in164, in264); + sumImag = __RV_KMABT32(sumImag, in264, in164); + sumReal -= __RV_SMTT32(in164, in264); + sumImag = __RV_KMABT32(sumImag, in164, in264); + + in164 = read_q31x2_ia ((q31_t **) &pIn1); + in264 = read_q31x2_ia ((q31_t **) &pIn2); + pIn2 -= 2; + pIn2 += 2 * numColsB; + sumReal = __RV_KMABB32(sumReal, in164, in264); + sumImag = __RV_KMABT32(sumImag, in264, in164); + sumReal -= __RV_SMTT32(in164, in264); + sumImag = __RV_KMABT32(sumImag, in164, in264); +#else + + /* Reading real part of complex matrix A */ + a0 = *pIn1; + + /* Reading real part of complex matrix B */ + c0 = *pIn2; + + /* Reading imaginary part of complex matrix A */ + b0 = *(pIn1 + 1U); + + /* Reading imaginary part of complex matrix B */ + d0 = *(pIn2 + 1U); + + /* Multiply and Accumlates */ + sumReal += (q63_t) a0 * c0; + sumImag += (q63_t) b0 * c0; + + /* update pointers */ + pIn1 += 2U; + pIn2 += 2 * numColsB; + + /* Multiply and Accumlates */ + sumReal -= (q63_t) b0 * d0; + sumImag += (q63_t) a0 * d0; + + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + + /* read real and imag values from pSrcA and pSrcB buffer */ + a1 = *(pIn1 ); + c1 = *(pIn2 ); + b1 = *(pIn1 + 1U); + d1 = *(pIn2 + 1U); + + /* Multiply and Accumlates */ + sumReal += (q63_t) a1 * c1; + sumImag += (q63_t) b1 * c1; + + /* update pointers */ + pIn1 += 2U; + pIn2 += 2 * numColsB; + + /* Multiply and Accumlates */ + sumReal -= (q63_t) b1 * d1; + sumImag += (q63_t) a1 * d1; + + a0 = *(pIn1 ); + c0 = *(pIn2 ); + b0 = *(pIn1 + 1U); + d0 = *(pIn2 + 1U); + + /* Multiply and Accumlates */ + sumReal += (q63_t) a0 * c0; + sumImag += (q63_t) b0 * c0; + + /* update pointers */ + pIn1 += 2U; + pIn2 += 2 * numColsB; + + /* Multiply and Accumlates */ + sumReal -= (q63_t) b0 * d0; + sumImag += (q63_t) a0 * d0; + + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + + a1 = *(pIn1 ); + c1 = *(pIn2 ); + b1 = *(pIn1 + 1U); + d1 = *(pIn2 + 1U); + + /* Multiply and Accumlates */ + sumReal += (q63_t) a1 * c1; + sumImag += (q63_t) b1 * c1; + + /* update pointers */ + pIn1 += 2U; + pIn2 += 2 * numColsB; + + /* Multiply and Accumlates */ + sumReal -= (q63_t) b1 * d1; + sumImag += (q63_t) a1 * d1; +#endif /* __RISCV_XLEN == 64 */ + /* Decrement loop count */ + colCnt--; + } + + /* If the columns of pSrcA is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + colCnt = numColsA % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + colCnt = numColsA; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + a1 = *(pIn1 ); + c1 = *(pIn2 ); + b1 = *(pIn1 + 1U); + d1 = *(pIn2 + 1U); + + /* Multiply and Accumlates */ + sumReal += (q63_t) a1 * c1; + sumImag += (q63_t) b1 * c1; + + /* update pointers */ + pIn1 += 2U; + pIn2 += 2 * numColsB; + + /* Multiply and Accumlates */ + sumReal -= (q63_t) b1 * d1; + sumImag += (q63_t) a1 * d1; + + /* Decrement loop counter */ + colCnt--; + } + + /* Store result in destination buffer */ + *px++ = (q31_t) clip_q63_to_q31(sumReal >> 31); + *px++ = (q31_t) clip_q63_to_q31(sumImag >> 31); + + /* Update pointer pIn2 to point to starting address of next column */ + j++; + pIn2 = pSrcB->pData + 2U * j; + + /* Decrement column loop counter */ + col--; + + } while (col > 0U); + + /* Update pointer pInA to point to starting address of next row */ + i = i + numColsB; + pInA = pInA + 2 * numColsA; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); + + /* Set status as RISCV_MATH_SUCCESS */ + status = RISCV_MATH_SUCCESS; + } + +#endif /* defined(RISCV_VECTOR) */ + /* Return to application */ + return (status); +} + +/** + @} end of MatrixMult group + */ diff --git a/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_cmplx_trans_f16.c b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_cmplx_trans_f16.c new file mode 100644 index 00000000..41a95493 --- /dev/null +++ b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_cmplx_trans_f16.c @@ -0,0 +1,120 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_mat_cmplx_trans_f16.c + * Description: Floating-point complex matrix transpose + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions_f16.h" + +#if defined(RISCV_FLOAT16_SUPPORTED) + + +/** + @ingroup groupMatrix + */ + + +/** + @addtogroup MatrixComplexTrans + @{ + */ + +/** + @brief Floating-point matrix transpose. + @param[in] pSrc points to input matrix + @param[out] pDst points to output matrix + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_SIZE_MISMATCH : Matrix size check failed + */ +riscv_status riscv_mat_cmplx_trans_f16( + const riscv_matrix_instance_f16 * pSrc, + riscv_matrix_instance_f16 * pDst) +{ + float16_t *pIn = pSrc->pData; /* input data matrix pointer */ + float16_t *pOut = pDst->pData; /* output data matrix pointer */ + float16_t *px; /* Temporary output data matrix pointer */ + uint16_t nRows = pSrc->numRows; /* number of rows */ + uint16_t nColumns = pSrc->numCols; /* number of columns */ + uint16_t col, i = 0U, row = nRows; /* loop counters */ + riscv_status status; /* status of matrix transpose */ + + +#ifdef RISCV_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows)) + { + /* Set status as RISCV_MATH_SIZE_MISMATCH */ + status = RISCV_MATH_SIZE_MISMATCH; + } + else +#endif /* #ifdef RISCV_MATH_MATRIX_CHECK */ + + { + /* Matrix transpose by exchanging the rows with columns */ + /* row loop */ + do + { + /* The pointer px is set to starting address of the column being processed */ + px = pOut + CMPLX_DIM * i; + + /* Initialize column loop counter */ + col = nColumns; + + while (col > 0U) + { + /* Read and store the input element in the destination */ + px[0] = *pIn++; // real + px[1] = *pIn++; // imag + + /* Update the pointer px to point to the next row of the transposed matrix */ + px += CMPLX_DIM * nRows; + + /* Decrement the column loop counter */ + col--; + } + i++; + + /* Decrement the row loop counter */ + row--; + + } while (row > 0U); /* row loop end */ + + /* Set status as RISCV_MATH_SUCCESS */ + status = RISCV_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +/** + * @} end of MatrixTrans group + */ + +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ + diff --git a/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_cmplx_trans_f32.c b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_cmplx_trans_f32.c new file mode 100644 index 00000000..b0634ead --- /dev/null +++ b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_cmplx_trans_f32.c @@ -0,0 +1,122 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_mat_cmplx_trans_f32.c + * Description: Floating-point complex matrix transpose + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @defgroup MatrixComplexTrans Complex Matrix Transpose + + Tranposes a complex matrix. + + Transposing an M x N matrix flips it around the center diagonal and results in an N x M matrix. + \image html MatrixTranspose.png "Transpose of a 3 x 3 matrix" + */ + +/** + @addtogroup MatrixComplexTrans + @{ + */ + +/** + @brief Floating-point matrix transpose. + @param[in] pSrc points to input matrix + @param[out] pDst points to output matrix + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_SIZE_MISMATCH : Matrix size check failed + */ +riscv_status riscv_mat_cmplx_trans_f32( + const riscv_matrix_instance_f32 * pSrc, + riscv_matrix_instance_f32 * pDst) +{ + float32_t *pIn = pSrc->pData; /* input data matrix pointer */ + float32_t *pOut = pDst->pData; /* output data matrix pointer */ + float32_t *px; /* Temporary output data matrix pointer */ + uint16_t nRows = pSrc->numRows; /* number of rows */ + uint16_t nColumns = pSrc->numCols; /* number of columns */ + uint16_t col, i = 0U, row = nRows; /* loop counters */ + riscv_status status; /* status of matrix transpose */ + + +#ifdef RISCV_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows)) + { + /* Set status as RISCV_MATH_SIZE_MISMATCH */ + status = RISCV_MATH_SIZE_MISMATCH; + } + else +#endif /* #ifdef RISCV_MATH_MATRIX_CHECK */ + + { + /* Matrix transpose by exchanging the rows with columns */ + /* row loop */ + do + { + /* The pointer px is set to starting address of the column being processed */ + px = pOut + CMPLX_DIM * i; + + /* Initialize column loop counter */ + col = nColumns; + + while (col > 0U) + { + /* Read and store the input element in the destination */ + px[0] = *pIn++; // real + px[1] = *pIn++; // imag + + /* Update the pointer px to point to the next row of the transposed matrix */ + px += CMPLX_DIM * nRows; + + /* Decrement the column loop counter */ + col--; + } + i++; + + /* Decrement the row loop counter */ + row--; + + } while (row > 0U); /* row loop end */ + + /* Set status as RISCV_MATH_SUCCESS */ + status = RISCV_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +/** + * @} end of MatrixTrans group + */ diff --git a/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_cmplx_trans_q15.c b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_cmplx_trans_q15.c new file mode 100644 index 00000000..ebc10f36 --- /dev/null +++ b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_cmplx_trans_q15.c @@ -0,0 +1,112 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_mat_cmplx_trans_q31.c + * Description: Q15 complex matrix transpose + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixComplexTrans + @{ + */ + +/** + @brief Q15 complex matrix transpose. + @param[in] pSrc points to input matrix + @param[out] pDst points to output matrix + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_SIZE_MISMATCH : Matrix size check failed + */ +riscv_status riscv_mat_cmplx_trans_q15( + const riscv_matrix_instance_q15 * pSrc, + riscv_matrix_instance_q15 * pDst) +{ + q15_t *pSrcA = pSrc->pData; /* input data matrix pointer */ + q15_t *pOut = pDst->pData; /* output data matrix pointer */ + uint16_t nRows = pSrc->numRows; /* number of nRows */ + uint16_t nColumns = pSrc->numCols; /* number of nColumns */ + uint16_t col, row = nRows, i = 0U; /* row and column loop counters */ + riscv_status status; /* status of matrix transpose */ + + +#ifdef RISCV_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows)) + { + /* Set status as RISCV_MATH_SIZE_MISMATCH */ + status = RISCV_MATH_SIZE_MISMATCH; + } + else +#endif /* #ifdef RISCV_MATH_MATRIX_CHECK */ + + { + /* Matrix transpose by exchanging the rows with columns */ + /* row loop */ + do + { + /* The pointer pOut is set to starting address of the column being processed */ + pOut = pDst->pData + CMPLX_DIM * i; + + /* Initialize column loop counter */ + col = nColumns; + + while (col > 0U) + { + /* Read and store the input element in the destination */ + pOut[0] = *pSrcA++; //real + pOut[1] = *pSrcA++; //imag + + /* Update the pointer pOut to point to the next row of the transposed matrix */ + pOut += CMPLX_DIM *nRows; + + /* Decrement the column loop counter */ + col--; + } + + i++; + + /* Decrement the row loop counter */ + row--; + + } while (row > 0U); + + /* set status as RISCV_MATH_SUCCESS */ + status = RISCV_MATH_SUCCESS; + } + /* Return to application */ + return (status); +} + +/** + * @} end of MatrixTrans group + */ diff --git a/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_cmplx_trans_q31.c b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_cmplx_trans_q31.c new file mode 100644 index 00000000..c9d361c0 --- /dev/null +++ b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_cmplx_trans_q31.c @@ -0,0 +1,116 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_mat_cmplx_trans_q31.c + * Description: Q31 complex matrix transpose + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + + + +/** + @addtogroup MatrixComplexTrans + @{ + */ + +/** + @brief Q31 complex matrix transpose. + @param[in] pSrc points to input matrix + @param[out] pDst points to output matrix + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_SIZE_MISMATCH : Matrix size check failed + */ +riscv_status riscv_mat_cmplx_trans_q31( + const riscv_matrix_instance_q31 * pSrc, + riscv_matrix_instance_q31 * pDst) +{ + q31_t *pIn = pSrc->pData; /* input data matrix pointer */ + q31_t *pOut = pDst->pData; /* output data matrix pointer */ + q31_t *px; /* Temporary output data matrix pointer */ + uint16_t nRows = pSrc->numRows; /* number of nRows */ + uint16_t nColumns = pSrc->numCols; /* number of nColumns */ + uint16_t col, i = 0U, row = nRows; /* loop counters */ + riscv_status status; /* status of matrix transpose */ + + +#ifdef RISCV_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows)) + { + /* Set status as RISCV_MATH_SIZE_MISMATCH */ + status = RISCV_MATH_SIZE_MISMATCH; + } + else +#endif /* #ifdef RISCV_MATH_MATRIX_CHECK */ + + { + /* Matrix transpose by exchanging the rows with columns */ + /* row loop */ + do + { + /* The pointer px is set to starting address of the column being processed */ + px = pOut + CMPLX_DIM * i; + + /* Initialize column loop counter */ + col = nColumns; + + while (col > 0U) + { + /* Read and store the input element in the destination */ + px[0] = *pIn++; // real + px[1] = *pIn++; // imag + + /* Update the pointer px to point to the next row of the transposed matrix */ + px += CMPLX_DIM * nRows; + + /* Decrement the column loop counter */ + col--; + } + + i++; + + /* Decrement the row loop counter */ + row--; + + } + while (row > 0U); /* row loop end */ + + /* set status as RISCV_MATH_SUCCESS */ + status = RISCV_MATH_SUCCESS; + } + /* Return to application */ + return (status); +} + +/** + * @} end of MatrixTrans group + */ diff --git a/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_init_f16.c b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_init_f16.c new file mode 100644 index 00000000..0d07d616 --- /dev/null +++ b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_init_f16.c @@ -0,0 +1,75 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_mat_init_f16.c + * Description: Floating-point matrix initialization + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions_f16.h" + +#if defined(RISCV_FLOAT16_SUPPORTED) + + +/** + @ingroup groupMatrix + */ + + +/** + @addtogroup MatrixInit + @{ + */ + +/** + @brief Floating-point matrix initialization. + @param[in,out] S points to an instance of the floating-point matrix structure + @param[in] nRows number of rows in the matrix + @param[in] nColumns number of columns in the matrix + @param[in] pData points to the matrix data array + @return none + */ + +void riscv_mat_init_f16( + riscv_matrix_instance_f16 * S, + uint16_t nRows, + uint16_t nColumns, + float16_t * pData) +{ + /* Assign Number of Rows */ + S->numRows = nRows; + + /* Assign Number of Columns */ + S->numCols = nColumns; + + /* Assign Data pointer */ + S->pData = pData; +} + +/** + @} end of MatrixInit group + */ + +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ + diff --git a/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_init_f32.c b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_init_f32.c new file mode 100644 index 00000000..15542bb8 --- /dev/null +++ b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_init_f32.c @@ -0,0 +1,77 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_mat_init_f32.c + * Description: Floating-point matrix initialization + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @defgroup MatrixInit Matrix Initialization + + Initializes the underlying matrix data structure. + The functions set the numRows, + numCols, and pData fields + of the matrix data structure. + */ + +/** + @addtogroup MatrixInit + @{ + */ + +/** + @brief Floating-point matrix initialization. + @param[in,out] S points to an instance of the floating-point matrix structure + @param[in] nRows number of rows in the matrix + @param[in] nColumns number of columns in the matrix + @param[in] pData points to the matrix data array + @return none + */ + +void riscv_mat_init_f32( + riscv_matrix_instance_f32 * S, + uint16_t nRows, + uint16_t nColumns, + float32_t * pData) +{ + /* Assign Number of Rows */ + S->numRows = nRows; + + /* Assign Number of Columns */ + S->numCols = nColumns; + + /* Assign Data pointer */ + S->pData = pData; +} + +/** + @} end of MatrixInit group + */ diff --git a/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_init_f64.c b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_init_f64.c new file mode 100644 index 00000000..72aeeab7 --- /dev/null +++ b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_init_f64.c @@ -0,0 +1,77 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_mat_init_f64.c + * Description: Floating-point matrix initialization + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @defgroup MatrixInit Matrix Initialization + + Initializes the underlying matrix data structure. + The functions set the numRows, + numCols, and pData fields + of the matrix data structure. + */ + +/** + @addtogroup MatrixInit + @{ + */ + +/** + @brief Floating-point matrix initialization. + @param[in,out] S points to an instance of the floating-point matrix structure + @param[in] nRows number of rows in the matrix + @param[in] nColumns number of columns in the matrix + @param[in] pData points to the matrix data array + @return none + */ + +void riscv_mat_init_f64( + riscv_matrix_instance_f64 * S, + uint16_t nRows, + uint16_t nColumns, + float32_t * pData) +{ + /* Assign Number of Rows */ + S->numRows = nRows; + + /* Assign Number of Columns */ + S->numCols = nColumns; + + /* Assign Data pointer */ + S->pData = pData; +} + +/** + @} end of MatrixInit group + */ diff --git a/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_init_q15.c b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_init_q15.c new file mode 100644 index 00000000..0e3b38fe --- /dev/null +++ b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_init_q15.c @@ -0,0 +1,68 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_mat_init_q15.c + * Description: Q15 matrix initialization + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixInit + @{ + */ + +/** + @brief Q15 matrix initialization. + @param[in,out] S points to an instance of the floating-point matrix structure + @param[in] nRows number of rows in the matrix + @param[in] nColumns number of columns in the matrix + @param[in] pData points to the matrix data array + @return none + */ + +void riscv_mat_init_q15( + riscv_matrix_instance_q15 * S, + uint16_t nRows, + uint16_t nColumns, + q15_t * pData) +{ + /* Assign Number of Rows */ + S->numRows = nRows; + + /* Assign Number of Columns */ + S->numCols = nColumns; + + /* Assign Data pointer */ + S->pData = pData; +} + +/** + @} end of MatrixInit group + */ diff --git a/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_init_q31.c b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_init_q31.c new file mode 100644 index 00000000..734b9e85 --- /dev/null +++ b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_init_q31.c @@ -0,0 +1,73 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_mat_init_q31.c + * Description: Q31 matrix initialization + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @defgroup MatrixInit Matrix Initialization + + */ + +/** + @addtogroup MatrixInit + @{ + */ + +/** + @brief Q31 matrix initialization. + @param[in,out] S points to an instance of the Q31 matrix structure + @param[in] nRows number of rows in the matrix + @param[in] nColumns number of columns in the matrix + @param[in] pData points to the matrix data array + @return none + */ + +void riscv_mat_init_q31( + riscv_matrix_instance_q31 * S, + uint16_t nRows, + uint16_t nColumns, + q31_t * pData) +{ + /* Assign Number of Rows */ + S->numRows = nRows; + + /* Assign Number of Columns */ + S->numCols = nColumns; + + /* Assign Data pointer */ + S->pData = pData; +} + +/** + @} end of MatrixInit group + */ diff --git a/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_inverse_f16.c b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_inverse_f16.c new file mode 100644 index 00000000..46004dff --- /dev/null +++ b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_inverse_f16.c @@ -0,0 +1,392 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_mat_inverse_f16.c + * Description: Floating-point matrix inverse + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions_f16.h" + +#if defined(RISCV_FLOAT16_SUPPORTED) + + +/** + @ingroup groupMatrix + */ + + +/** + @addtogroup MatrixInv + @{ + */ + +/** + @brief Floating-point matrix inverse. + @param[in] pSrc points to input matrix structure. The source matrix is modified by the function. + @param[out] pDst points to output matrix structure + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_SIZE_MISMATCH : Matrix size check failed + - \ref RISCV_MATH_SINGULAR : Input matrix is found to be singular (non-invertible) + */ + +riscv_status riscv_mat_inverse_f16( + const riscv_matrix_instance_f16 * pSrc, + riscv_matrix_instance_f16 * pDst) +{ + float16_t *pIn = pSrc->pData; /* input data matrix pointer */ + float16_t *pOut = pDst->pData; /* output data matrix pointer */ + float16_t *pInT1, *pInT2; /* Temporary input data matrix pointer */ + float16_t *pOutT1, *pOutT2; /* Temporary output data matrix pointer */ + float16_t *pPivotRowIn, *pPRT_in, *pPivotRowDst, *pPRT_pDst; /* Temporary input and output data matrix pointer */ + uint32_t numRows = pSrc->numRows; /* Number of rows in the matrix */ + uint32_t numCols = pSrc->numCols; /* Number of Cols in the matrix */ + + _Float16 Xchg, in = 0.0f16, in1; /* Temporary input values */ + uint32_t i, rowCnt, flag = 0U, j, loopCnt, k,l; /* loop counters */ + riscv_status status; /* status of matrix inverse */ + +#ifdef RISCV_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pSrc->numCols) || + (pDst->numRows != pDst->numCols) || + (pSrc->numRows != pDst->numRows) ) + { + /* Set status as RISCV_MATH_SIZE_MISMATCH */ + status = RISCV_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef RISCV_MATH_MATRIX_CHECK */ + + { + + /*-------------------------------------------------------------------------------------------------------------- + * Matrix Inverse can be solved using elementary row operations. + * + * Gauss-Jordan Method: + * + * 1. First combine the identity matrix and the input matrix separated by a bar to form an + * augmented matrix as follows: + * _ _ _ _ + * | a11 a12 | 1 0 | | X11 X12 | + * | | | = | | + * |_ a21 a22 | 0 1 _| |_ X21 X21 _| + * + * 2. In our implementation, pDst Matrix is used as identity matrix. + * + * 3. Begin with the first row. Let i = 1. + * + * 4. Check to see if the pivot for row i is zero. + * The pivot is the element of the main diagonal that is on the current row. + * For instance, if working with row i, then the pivot element is aii. + * If the pivot is zero, exchange that row with a row below it that does not + * contain a zero in column i. If this is not possible, then an inverse + * to that matrix does not exist. + * + * 5. Divide every element of row i by the pivot. + * + * 6. For every row below and row i, replace that row with the sum of that row and + * a multiple of row i so that each new element in column i below row i is zero. + * + * 7. Move to the next row and column and repeat steps 2 through 5 until you have zeros + * for every element below and above the main diagonal. + * + * 8. Now an identical matrix is formed to the left of the bar(input matrix, pSrc). + * Therefore, the matrix to the right of the bar is our solution(pDst matrix, pDst). + *----------------------------------------------------------------------------------------------------------------*/ + + /* Working pointer for destination matrix */ + pOutT1 = pOut; + + /* Loop over the number of rows */ + rowCnt = numRows; + + /* Making the destination matrix as identity matrix */ + while (rowCnt > 0U) + { + /* Writing all zeroes in lower triangle of the destination matrix */ + j = numRows - rowCnt; + while (j > 0U) + { + *pOutT1++ = 0.0f16; + j--; + } + + /* Writing all ones in the diagonal of the destination matrix */ + *pOutT1++ = 1.0f16; + + /* Writing all zeroes in upper triangle of the destination matrix */ + j = rowCnt - 1U; + while (j > 0U) + { + *pOutT1++ = 0.0f16; + j--; + } + + /* Decrement loop counter */ + rowCnt--; + } + + /* Loop over the number of columns of the input matrix. + All the elements in each column are processed by the row operations */ + loopCnt = numCols; + + /* Index modifier to navigate through the columns */ + l = 0U; + + while (loopCnt > 0U) + { + /* Check if the pivot element is zero.. + * If it is zero then interchange the row with non zero row below. + * If there is no non zero element to replace in the rows below, + * then the matrix is Singular. */ + + /* Working pointer for the input matrix that points + * to the pivot element of the particular row */ + pInT1 = pIn + (l * numCols); + + /* Working pointer for the destination matrix that points + * to the pivot element of the particular row */ + pOutT1 = pOut + (l * numCols); + + /* Temporary variable to hold the pivot value */ + in = *pInT1; + + + /* Check if the pivot element is zero */ + if (*pInT1 == 0.0f16) + { + /* Loop over the number rows present below */ + + for (i = 1U; i < numRows-l; i++) + { + /* Update the input and destination pointers */ + pInT2 = pInT1 + (numCols * i); + pOutT2 = pOutT1 + (numCols * i); + + /* Check if there is a non zero pivot element to + * replace in the rows below */ + if (*pInT2 != 0.0f16) + { + /* Loop over number of columns + * to the right of the pilot element */ + j = numCols - l; + + while (j > 0U) + { + /* Exchange the row elements of the input matrix */ + Xchg = *pInT2; + *pInT2++ = *pInT1; + *pInT1++ = Xchg; + + /* Decrement the loop counter */ + j--; + } + + /* Loop over number of columns of the destination matrix */ + j = numCols; + + while (j > 0U) + { + /* Exchange the row elements of the destination matrix */ + Xchg = *pOutT2; + *pOutT2++ = *pOutT1; + *pOutT1++ = Xchg; + + /* Decrement loop counter */ + j--; + } + + /* Flag to indicate whether exchange is done or not */ + flag = 1U; + + /* Break after exchange is done */ + break; + } + + } + } + + /* Update the status if the matrix is singular */ + if ((flag != 1U) && (in == 0.0f16)) + { + return RISCV_MATH_SINGULAR; + } + + /* Points to the pivot row of input and destination matrices */ + pPivotRowIn = pIn + (l * numCols); + pPivotRowDst = pOut + (l * numCols); + + /* Temporary pointers to the pivot row pointers */ + pInT1 = pPivotRowIn; + pInT2 = pPivotRowDst; + + /* Pivot element of the row */ + in = *pPivotRowIn; + + /* Loop over number of columns + * to the right of the pilot element */ + j = (numCols - l); + + while (j > 0U) + { + /* Divide each element of the row of the input matrix + * by the pivot element */ + in1 = *pInT1; + *pInT1++ = in1 / in; + + /* Decrement the loop counter */ + j--; + } + + /* Loop over number of columns of the destination matrix */ + j = numCols; + + while (j > 0U) + { + /* Divide each element of the row of the destination matrix + * by the pivot element */ + in1 = *pInT2; + *pInT2++ = in1 / in; + + /* Decrement the loop counter */ + j--; + } + + /* Replace the rows with the sum of that row and a multiple of row i + * so that each new element in column i above row i is zero.*/ + + /* Temporary pointers for input and destination matrices */ + pInT1 = pIn; + pInT2 = pOut; + + /* index used to check for pivot element */ + i = 0U; + + /* Loop over number of rows */ + /* to be replaced by the sum of that row and a multiple of row i */ + k = numRows; + + while (k > 0U) + { + /* Check for the pivot element */ + if (i == l) + { + /* If the processing element is the pivot element, + only the columns to the right are to be processed */ + pInT1 += numCols - l; + + pInT2 += numCols; + } + else + { + /* Element of the reference row */ + in = *pInT1; + + /* Working pointers for input and destination pivot rows */ + pPRT_in = pPivotRowIn; + pPRT_pDst = pPivotRowDst; + + /* Loop over the number of columns to the right of the pivot element, + to replace the elements in the input matrix */ + j = (numCols - l); + + while (j > 0U) + { + /* Replace the element by the sum of that row + and a multiple of the reference row */ + in1 = *pInT1; + *pInT1++ = in1 - (in * *pPRT_in++); + + /* Decrement the loop counter */ + j--; + } + + /* Loop over the number of columns to + replace the elements in the destination matrix */ + j = numCols; + + while (j > 0U) + { + /* Replace the element by the sum of that row + and a multiple of the reference row */ + in1 = *pInT2; + *pInT2++ = in1 - (in * *pPRT_pDst++); + + /* Decrement loop counter */ + j--; + } + + } + + /* Increment temporary input pointer */ + pInT1 = pInT1 + l; + + /* Decrement loop counter */ + k--; + + /* Increment pivot index */ + i++; + } + + /* Increment the input pointer */ + pIn++; + + /* Decrement the loop counter */ + loopCnt--; + + /* Increment the index modifier */ + l++; + } + + /* Set status as RISCV_MATH_SUCCESS */ + status = RISCV_MATH_SUCCESS; + + if ((flag != 1U) && (in == 0.0f16)) + { + pIn = pSrc->pData; + for (i = 0; i < numRows * numCols; i++) + { + if (pIn[i] != 0.0f16) + break; + } + + if (i == numRows * numCols) + status = RISCV_MATH_SINGULAR; + } + } + + /* Return to application */ + return (status); +} + +/** + @} end of MatrixInv group + */ + +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ + diff --git a/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_inverse_f32.c b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_inverse_f32.c new file mode 100644 index 00000000..7e24f31e --- /dev/null +++ b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_inverse_f32.c @@ -0,0 +1,715 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_mat_inverse_f32.c + * Description: Floating-point matrix inverse + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + + +/** + @ingroup groupMatrix + */ + +/** + @defgroup MatrixInv Matrix Inverse + + Computes the inverse of a matrix. + + The inverse is defined only if the input matrix is square and non-singular (the determinant is non-zero). + The function checks that the input and output matrices are square and of the same size. + + Matrix inversion is numerically sensitive and the NMSIS DSP library only supports matrix + inversion of floating-point matrices. + + @par Algorithm + The Gauss-Jordan method is used to find the inverse. + The algorithm performs a sequence of elementary row-operations until it + reduces the input matrix to an identity matrix. Applying the same sequence + of elementary row-operations to an identity matrix yields the inverse matrix. + If the input matrix is singular, then the algorithm terminates and returns error status + RISCV_MATH_SINGULAR. + \image html MatrixInverse.png "Matrix Inverse of a 3 x 3 matrix using Gauss-Jordan Method" + */ + +/** + @addtogroup MatrixInv + @{ + */ + +/** + @brief Floating-point matrix inverse. + @param[in] pSrc points to input matrix structure. The source matrix is modified by the function. + @param[out] pDst points to output matrix structure + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_SIZE_MISMATCH : Matrix size check failed + - \ref RISCV_MATH_SINGULAR : Input matrix is found to be singular (non-invertible) + */ +riscv_status riscv_mat_inverse_f32( + const riscv_matrix_instance_f32 * pSrc, + riscv_matrix_instance_f32 * pDst) +{ + float32_t *pIn = pSrc->pData; /* input data matrix pointer */ + float32_t *pOut = pDst->pData; /* output data matrix pointer */ + float32_t *pInT1, *pInT2; /* Temporary input data matrix pointer */ + float32_t *pOutT1, *pOutT2; /* Temporary output data matrix pointer */ + float32_t *pPivotRowIn, *pPRT_in, *pPivotRowDst, *pPRT_pDst; /* Temporary input and output data matrix pointer */ + uint32_t numRows = pSrc->numRows; /* Number of rows in the matrix */ + uint32_t numCols = pSrc->numCols; /* Number of Cols in the matrix */ +#if defined (RISCV_VECTOR) + uint32_t blkCnt; /* loop counters */ + size_t vl; + vfloat32m8_t vx, vy; +#endif + +#if defined (RISCV_MATH_DSP) && !defined (RISCV_VECTOR) + + float32_t Xchg, in = 0.0f, in1; /* Temporary input values */ + uint32_t i, rowCnt, flag = 0U, j, loopCnt, k,l; /* loop counters */ + riscv_status status; /* status of matrix inverse */ + +#ifdef RISCV_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pSrc->numCols) || + (pDst->numRows != pDst->numCols) || + (pSrc->numRows != pDst->numRows) ) + { + /* Set status as RISCV_MATH_SIZE_MISMATCH */ + status = RISCV_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef RISCV_MATH_MATRIX_CHECK */ + + { + + /*-------------------------------------------------------------------------------------------------------------- + * Matrix Inverse can be solved using elementary row operations. + * + * Gauss-Jordan Method: + * + * 1. First combine the identity matrix and the input matrix separated by a bar to form an + * augmented matrix as follows: + * _ _ _ _ + * | a11 a12 | 1 0 | | X11 X12 | + * | | | = | | + * |_ a21 a22 | 0 1 _| |_ X21 X21 _| + * + * 2. In our implementation, pDst Matrix is used as identity matrix. + * + * 3. Begin with the first row. Let i = 1. + * + * 4. Check to see if the pivot for row i is zero. + * The pivot is the element of the main diagonal that is on the current row. + * For instance, if working with row i, then the pivot element is aii. + * If the pivot is zero, exchange that row with a row below it that does not + * contain a zero in column i. If this is not possible, then an inverse + * to that matrix does not exist. + * + * 5. Divide every element of row i by the pivot. + * + * 6. For every row below and row i, replace that row with the sum of that row and + * a multiple of row i so that each new element in column i below row i is zero. + * + * 7. Move to the next row and column and repeat steps 2 through 5 until you have zeros + * for every element below and above the main diagonal. + * + * 8. Now an identical matrix is formed to the left of the bar(input matrix, pSrc). + * Therefore, the matrix to the right of the bar is our solution(pDst matrix, pDst). + *----------------------------------------------------------------------------------------------------------------*/ + + /* Working pointer for destination matrix */ + pOutT1 = pOut; + + /* Loop over the number of rows */ + rowCnt = numRows; + + /* Making the destination matrix as identity matrix */ + while (rowCnt > 0U) + { + /* Writing all zeroes in lower triangle of the destination matrix */ + j = numRows - rowCnt; + while (j > 0U) + { + *pOutT1++ = 0.0f; + j--; + } + + /* Writing all ones in the diagonal of the destination matrix */ + *pOutT1++ = 1.0f; + + /* Writing all zeroes in upper triangle of the destination matrix */ + j = rowCnt - 1U; + while (j > 0U) + { + *pOutT1++ = 0.0f; + j--; + } + + /* Decrement loop counter */ + rowCnt--; + } + + /* Loop over the number of columns of the input matrix. + All the elements in each column are processed by the row operations */ + loopCnt = numCols; + + /* Index modifier to navigate through the columns */ + l = 0U; + + while (loopCnt > 0U) + { + /* Check if the pivot element is zero.. + * If it is zero then interchange the row with non zero row below. + * If there is no non zero element to replace in the rows below, + * then the matrix is Singular. */ + + /* Working pointer for the input matrix that points + * to the pivot element of the particular row */ + pInT1 = pIn + (l * numCols); + + /* Working pointer for the destination matrix that points + * to the pivot element of the particular row */ + pOutT1 = pOut + (l * numCols); + + /* Temporary variable to hold the pivot value */ + in = *pInT1; + + /* Check if the pivot element is zero */ + if (*pInT1 == 0.0f) + { + /* Loop over the number rows present below */ + + for (i = 1U; i < numRows - l; i++) + { + /* Update the input and destination pointers */ + pInT2 = pInT1 + (numCols * i); + pOutT2 = pOutT1 + (numCols * i); + + /* Check if there is a non zero pivot element to + * replace in the rows below */ + if (*pInT2 != 0.0f) + { + /* Loop over number of columns + * to the right of the pilot element */ + j = numCols - l; + + while (j > 0U) + { + /* Exchange the row elements of the input matrix */ + Xchg = *pInT2; + *pInT2++ = *pInT1; + *pInT1++ = Xchg; + + /* Decrement the loop counter */ + j--; + } + + /* Loop over number of columns of the destination matrix */ + j = numCols; + + while (j > 0U) + { + /* Exchange the row elements of the destination matrix */ + Xchg = *pOutT2; + *pOutT2++ = *pOutT1; + *pOutT1++ = Xchg; + + /* Decrement loop counter */ + j--; + } + + /* Flag to indicate whether exchange is done or not */ + flag = 1U; + + /* Break after exchange is done */ + break; + } + /* Decrement loop counter */ + } + } + + /* Update the status if the matrix is singular */ + if ((flag != 1U) && (in == 0.0f)) + { + return RISCV_MATH_SINGULAR; + } + + /* Points to the pivot row of input and destination matrices */ + pPivotRowIn = pIn + (l * numCols); + pPivotRowDst = pOut + (l * numCols); + + /* Temporary pointers to the pivot row pointers */ + pInT1 = pPivotRowIn; + pInT2 = pPivotRowDst; + + /* Pivot element of the row */ + in = *pPivotRowIn; + + /* Loop over number of columns + * to the right of the pilot element */ + j = (numCols - l); + + while (j > 0U) + { + /* Divide each element of the row of the input matrix + * by the pivot element */ + in1 = *pInT1; + *pInT1++ = in1 / in; + + /* Decrement the loop counter */ + j--; + } + + /* Loop over number of columns of the destination matrix */ + j = numCols; + + while (j > 0U) + { + /* Divide each element of the row of the destination matrix + * by the pivot element */ + in1 = *pInT2; + *pInT2++ = in1 / in; + + /* Decrement the loop counter */ + j--; + } + + /* Replace the rows with the sum of that row and a multiple of row i + * so that each new element in column i above row i is zero.*/ + + /* Temporary pointers for input and destination matrices */ + pInT1 = pIn; + pInT2 = pOut; + + /* index used to check for pivot element */ + i = 0U; + + /* Loop over number of rows */ + /* to be replaced by the sum of that row and a multiple of row i */ + k = numRows; + + while (k > 0U) + { + /* Check for the pivot element */ + if (i == l) + { + /* If the processing element is the pivot element, + only the columns to the right are to be processed */ + pInT1 += numCols - l; + + pInT2 += numCols; + } + else + { + /* Element of the reference row */ + in = *pInT1; + + /* Working pointers for input and destination pivot rows */ + pPRT_in = pPivotRowIn; + pPRT_pDst = pPivotRowDst; + + /* Loop over the number of columns to the right of the pivot element, + to replace the elements in the input matrix */ + j = (numCols - l); + + while (j > 0U) + { + /* Replace the element by the sum of that row + and a multiple of the reference row */ + in1 = *pInT1; + *pInT1++ = in1 - (in * *pPRT_in++); + + /* Decrement the loop counter */ + j--; + } + + /* Loop over the number of columns to + replace the elements in the destination matrix */ + j = numCols; + + while (j > 0U) + { + /* Replace the element by the sum of that row + and a multiple of the reference row */ + in1 = *pInT2; + *pInT2++ = in1 - (in * *pPRT_pDst++); + + /* Decrement loop counter */ + j--; + } + + } + + /* Increment temporary input pointer */ + pInT1 = pInT1 + l; + + /* Decrement loop counter */ + k--; + + /* Increment pivot index */ + i++; + } + + /* Increment the input pointer */ + pIn++; + + /* Decrement the loop counter */ + loopCnt--; + + /* Increment the index modifier */ + l++; + } + + +#else + + float32_t Xchg, in = 0.0f; /* Temporary input values */ + uint32_t i, rowCnt, flag = 0U, j, loopCnt, l; /* loop counters */ + riscv_status status; /* status of matrix inverse */ + +#ifdef RISCV_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pSrc->numCols) || + (pDst->numRows != pDst->numCols) || + (pSrc->numRows != pDst->numRows) ) + { + /* Set status as RISCV_MATH_SIZE_MISMATCH */ + status = RISCV_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef RISCV_MATH_MATRIX_CHECK */ + + { + + /*-------------------------------------------------------------------------------------------------------------- + * Matrix Inverse can be solved using elementary row operations. + * + * Gauss-Jordan Method: + * + * 1. First combine the identity matrix and the input matrix separated by a bar to form an + * augmented matrix as follows: + * _ _ _ _ _ _ _ _ + * | | a11 a12 | | | 1 0 | | | X11 X12 | + * | | | | | | | = | | + * |_ |_ a21 a22 _| | |_0 1 _| _| |_ X21 X21 _| + * + * 2. In our implementation, pDst Matrix is used as identity matrix. + * + * 3. Begin with the first row. Let i = 1. + * + * 4. Check to see if the pivot for row i is zero. + * The pivot is the element of the main diagonal that is on the current row. + * For instance, if working with row i, then the pivot element is aii. + * If the pivot is zero, exchange that row with a row below it that does not + * contain a zero in column i. If this is not possible, then an inverse + * to that matrix does not exist. + * + * 5. Divide every element of row i by the pivot. + * + * 6. For every row below and row i, replace that row with the sum of that row and + * a multiple of row i so that each new element in column i below row i is zero. + * + * 7. Move to the next row and column and repeat steps 2 through 5 until you have zeros + * for every element below and above the main diagonal. + * + * 8. Now an identical matrix is formed to the left of the bar(input matrix, src). + * Therefore, the matrix to the right of the bar is our solution(dst matrix, dst). + *----------------------------------------------------------------------------------------------------------------*/ + + /* Working pointer for destination matrix */ + pOutT1 = pOut; + + /* Loop over the number of rows */ + rowCnt = numRows; + + /* Making the destination matrix as identity matrix */ +#if defined (RISCV_VECTOR) + while (rowCnt > 0U) + { + blkCnt = numRows - rowCnt; + vl = vsetvl_e32m8(blkCnt); + vx = vfmv_v_f_f32m8(0, vl); + for (; (vl = vsetvl_e32m8(blkCnt)) > 0; blkCnt -= vl) { + vse32_v_f32m8 (pOutT1, vx, vl); + pOutT1 += vl; + } + /* Writing all ones in the diagonal of the destination matrix */ + *pOutT1++ = 1.0f; + + blkCnt = rowCnt - 1U; + vl = vsetvl_e32m8(blkCnt); + vx = vfmv_v_f_f32m8(0, vl); + for (; (vl = vsetvl_e32m8(blkCnt)) > 0; blkCnt -= vl) { + vse32_v_f32m8 (pOutT1, vx, vl); + pOutT1 += vl; + } + rowCnt--; + } +#else + while (rowCnt > 0U) + { + /* Writing all zeroes in lower triangle of the destination matrix */ + j = numRows - rowCnt; + while (j > 0U) + { + *pOutT1++ = 0.0f; + j--; + } + + /* Writing all ones in the diagonal of the destination matrix */ + *pOutT1++ = 1.0f; + + /* Writing all zeroes in upper triangle of the destination matrix */ + j = rowCnt - 1U; + while (j > 0U) + { + *pOutT1++ = 0.0f; + j--; + } + + /* Decrement loop counter */ + rowCnt--; + } +#endif + + /* Loop over the number of columns of the input matrix. + All the elements in each column are processed by the row operations */ + loopCnt = numCols; + + /* Index modifier to navigate through the columns */ + l = 0U; + + while (loopCnt > 0U) + { + /* Check if the pivot element is zero.. + * If it is zero then interchange the row with non zero row below. + * If there is no non zero element to replace in the rows below, + * then the matrix is Singular. */ + + /* Working pointer for the input matrix that points + * to the pivot element of the particular row */ + pInT1 = pIn + (l * numCols); + + /* Working pointer for the destination matrix that points + * to the pivot element of the particular row */ + pOutT1 = pOut + (l * numCols); + + /* Temporary variable to hold the pivot value */ + in = *pInT1; + + /* Check if the pivot element is zero */ + if (*pInT1 == 0.0f) + { + /* Loop over the number rows present below */ + for (i = 1U; i < numRows-l; i++) + { + /* Update the input and destination pointers */ + pInT2 = pInT1 + (numCols * i); + pOutT2 = pOutT1 + (numCols * i); + + /* Check if there is a non zero pivot element to + * replace in the rows below */ + if (*pInT2 != 0.0f) + { + /* Loop over number of columns + * to the right of the pilot element */ + for (j = 0U; j < (numCols - l); j++) + { + /* Exchange the row elements of the input matrix */ + Xchg = *pInT2; + *pInT2++ = *pInT1; + *pInT1++ = Xchg; + } + + for (j = 0U; j < numCols; j++) + { + Xchg = *pOutT2; + *pOutT2++ = *pOutT1; + *pOutT1++ = Xchg; + } + + /* Flag to indicate whether exchange is done or not */ + flag = 1U; + + /* Break after exchange is done */ + break; + } + } + } + + + /* Update the status if the matrix is singular */ + if ((flag != 1U) && (in == 0.0f)) + { + return RISCV_MATH_SINGULAR; + } + + /* Points to the pivot row of input and destination matrices */ + pPivotRowIn = pIn + (l * numCols); + pPivotRowDst = pOut + (l * numCols); + + /* Temporary pointers to the pivot row pointers */ + pInT1 = pPivotRowIn; + pOutT1 = pPivotRowDst; + + /* Pivot element of the row */ + in = *(pIn + (l * numCols)); + + /* Loop over number of columns + * to the right of the pilot element */ + for (j = 0U; j < (numCols - l); j++) + { + /* Divide each element of the row of the input matrix + * by the pivot element */ + *pInT1 = *pInT1 / in; + pInT1++; + } + for (j = 0U; j < numCols; j++) + { + /* Divide each element of the row of the destination matrix + * by the pivot element */ + *pOutT1 = *pOutT1 / in; + pOutT1++; + } + + /* Replace the rows with the sum of that row and a multiple of row i + * so that each new element in column i above row i is zero.*/ + + /* Temporary pointers for input and destination matrices */ + pInT1 = pIn; + pOutT1 = pOut; + + for (i = 0U; i < numRows; i++) + { + /* Check for the pivot element */ + if (i == l) + { + /* If the processing element is the pivot element, + only the columns to the right are to be processed */ + pInT1 += numCols - l; + pOutT1 += numCols; + } + else + { + /* Element of the reference row */ + in = *pInT1; + + /* Working pointers for input and destination pivot rows */ + pPRT_in = pPivotRowIn; + pPRT_pDst = pPivotRowDst; + + /* Loop over the number of columns to the right of the pivot element, + to replace the elements in the input matrix */ +#if defined (RISCV_VECTOR) + /* Replace the element by the sum of that row + and a multiple of the reference row */ + blkCnt = numCols - l; + for (; (vl = vsetvl_e32m8(blkCnt)) > 0; blkCnt -= vl) + { + vx = vle32_v_f32m8(pInT1, vl); + vy = vle32_v_f32m8(pPRT_in, vl); + vse32_v_f32m8 (pInT1, vfsub_vv_f32m8(vx, vfmul_vf_f32m8(vy,in, vl), vl), vl); + pInT1 += vl; + pPRT_in += vl; + } + /* Loop over the number of columns to + replace the elements in the destination matrix */ + blkCnt = numCols; + for (; (vl = vsetvl_e32m8(blkCnt)) > 0; blkCnt -= vl) + { + vx = vle32_v_f32m8(pOutT1, vl); + vy = vle32_v_f32m8(pPRT_pDst, vl); + vse32_v_f32m8 (pOutT1, vfsub_vv_f32m8(vx, vfmul_vf_f32m8(vy,in, vl), vl), vl); + pOutT1 += vl; + pPRT_pDst += vl; + } +#else + for (j = 0U; j < (numCols - l); j++) + { + /* Replace the element by the sum of that row + and a multiple of the reference row */ + *pInT1 = *pInT1 - (in * *pPRT_in++); + pInT1++; + } + + /* Loop over the number of columns to + replace the elements in the destination matrix */ + for (j = 0U; j < numCols; j++) + { + /* Replace the element by the sum of that row + and a multiple of the reference row */ + *pOutT1 = *pOutT1 - (in * *pPRT_pDst++); + pOutT1++; + } +#endif + + } + + /* Increment temporary input pointer */ + pInT1 = pInT1 + l; + } + + /* Increment the input pointer */ + pIn++; + + /* Decrement the loop counter */ + loopCnt--; + + /* Increment the index modifier */ + l++; + } + +#endif /* #if defined (RISCV_MATH_DSP) */ + + /* Set status as RISCV_MATH_SUCCESS */ + status = RISCV_MATH_SUCCESS; + + if ((flag != 1U) && (in == 0.0f)) + { + pIn = pSrc->pData; + for (i = 0; i < numRows * numCols; i++) + { + if (pIn[i] != 0.0f) + break; + } + + if (i == numRows * numCols) + status = RISCV_MATH_SINGULAR; + } + } + + /* Return to application */ + return (status); +} + +/** + @} end of MatrixInv group + */ diff --git a/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_inverse_f64.c b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_inverse_f64.c new file mode 100644 index 00000000..a21c724c --- /dev/null +++ b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_inverse_f64.c @@ -0,0 +1,645 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_mat_inverse_f64.c + * Description: Floating-point matrix inverse + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + + +/** + @addtogroup MatrixInv + @{ + */ + +/** + @brief Floating-point (64 bit) matrix inverse. + @param[in] pSrc points to input matrix structure. The source matrix is modified by the function. + @param[out] pDst points to output matrix structure + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_SIZE_MISMATCH : Matrix size check failed + - \ref RISCV_MATH_SINGULAR : Input matrix is found to be singular (non-invertible) + */ + +riscv_status riscv_mat_inverse_f64( + const riscv_matrix_instance_f64 * pSrc, + riscv_matrix_instance_f64 * pDst) +{ + float64_t *pIn = pSrc->pData; /* input data matrix pointer */ + float64_t *pOut = pDst->pData; /* output data matrix pointer */ + float64_t *pInT1, *pInT2; /* Temporary input data matrix pointer */ + float64_t *pOutT1, *pOutT2; /* Temporary output data matrix pointer */ + float64_t *pPivotRowIn, *pPRT_in, *pPivotRowDst, *pPRT_pDst; /* Temporary input and output data matrix pointer */ + uint32_t numRows = pSrc->numRows; /* Number of rows in the matrix */ + uint32_t numCols = pSrc->numCols; /* Number of Cols in the matrix */ + +#if defined (RISCV_MATH_DSP) + + float64_t Xchg, in = 0.0, in1; /* Temporary input values */ + uint32_t i, rowCnt, flag = 0U, j, loopCnt, k,l; /* loop counters */ + riscv_status status; /* status of matrix inverse */ + +#ifdef RISCV_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pSrc->numCols) || + (pDst->numRows != pDst->numCols) || + (pSrc->numRows != pDst->numRows) ) + { + /* Set status as RISCV_MATH_SIZE_MISMATCH */ + status = RISCV_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef RISCV_MATH_MATRIX_CHECK */ + + { + + /*-------------------------------------------------------------------------------------------------------------- + * Matrix Inverse can be solved using elementary row operations. + * + * Gauss-Jordan Method: + * + * 1. First combine the identity matrix and the input matrix separated by a bar to form an + * augmented matrix as follows: + * _ _ _ _ + * | a11 a12 | 1 0 | | X11 X12 | + * | | | = | | + * |_ a21 a22 | 0 1 _| |_ X21 X21 _| + * + * 2. In our implementation, pDst Matrix is used as identity matrix. + * + * 3. Begin with the first row. Let i = 1. + * + * 4. Check to see if the pivot for row i is zero. + * The pivot is the element of the main diagonal that is on the current row. + * For instance, if working with row i, then the pivot element is aii. + * If the pivot is zero, exchange that row with a row below it that does not + * contain a zero in column i. If this is not possible, then an inverse + * to that matrix does not exist. + * + * 5. Divide every element of row i by the pivot. + * + * 6. For every row below and row i, replace that row with the sum of that row and + * a multiple of row i so that each new element in column i below row i is zero. + * + * 7. Move to the next row and column and repeat steps 2 through 5 until you have zeros + * for every element below and above the main diagonal. + * + * 8. Now an identical matrix is formed to the left of the bar(input matrix, pSrc). + * Therefore, the matrix to the right of the bar is our solution(pDst matrix, pDst). + *----------------------------------------------------------------------------------------------------------------*/ + + /* Working pointer for destination matrix */ + pOutT1 = pOut; + + /* Loop over the number of rows */ + rowCnt = numRows; + + /* Making the destination matrix as identity matrix */ + while (rowCnt > 0U) + { + /* Writing all zeroes in lower triangle of the destination matrix */ + j = numRows - rowCnt; + while (j > 0U) + { + *pOutT1++ = 0.0; + j--; + } + + /* Writing all ones in the diagonal of the destination matrix */ + *pOutT1++ = 1.0; + + /* Writing all zeroes in upper triangle of the destination matrix */ + j = rowCnt - 1U; + while (j > 0U) + { + *pOutT1++ = 0.0; + j--; + } + + /* Decrement loop counter */ + rowCnt--; + } + + /* Loop over the number of columns of the input matrix. + All the elements in each column are processed by the row operations */ + loopCnt = numCols; + + /* Index modifier to navigate through the columns */ + l = 0U; + + while (loopCnt > 0U) + { + /* Check if the pivot element is zero.. + * If it is zero then interchange the row with non zero row below. + * If there is no non zero element to replace in the rows below, + * then the matrix is Singular. */ + + /* Working pointer for the input matrix that points + * to the pivot element of the particular row */ + pInT1 = pIn + (l * numCols); + + /* Working pointer for the destination matrix that points + * to the pivot element of the particular row */ + pOutT1 = pOut + (l * numCols); + + /* Temporary variable to hold the pivot value */ + in = *pInT1; + + + + /* Check if the pivot element is zero */ + if (*pInT1 == 0.0) + { + /* Loop over the number rows present below */ + + for (i = 1U; i < numRows - l; i++) + { + /* Update the input and destination pointers */ + pInT2 = pInT1 + (numCols * i); + pOutT2 = pOutT1 + (numCols * i); + + /* Check if there is a non zero pivot element to + * replace in the rows below */ + if (*pInT2 != 0.0) + { + /* Loop over number of columns + * to the right of the pilot element */ + j = numCols - l; + + while (j > 0U) + { + /* Exchange the row elements of the input matrix */ + Xchg = *pInT2; + *pInT2++ = *pInT1; + *pInT1++ = Xchg; + + /* Decrement the loop counter */ + j--; + } + + /* Loop over number of columns of the destination matrix */ + j = numCols; + + while (j > 0U) + { + /* Exchange the row elements of the destination matrix */ + Xchg = *pOutT2; + *pOutT2++ = *pOutT1; + *pOutT1++ = Xchg; + + /* Decrement loop counter */ + j--; + } + + /* Flag to indicate whether exchange is done or not */ + flag = 1U; + + /* Break after exchange is done */ + break; + } + + + /* Decrement loop counter */ + } + } + + /* Update the status if the matrix is singular */ + if ((flag != 1U) && (in == 0.0)) + { + return RISCV_MATH_SINGULAR; + } + + /* Points to the pivot row of input and destination matrices */ + pPivotRowIn = pIn + (l * numCols); + pPivotRowDst = pOut + (l * numCols); + + /* Temporary pointers to the pivot row pointers */ + pInT1 = pPivotRowIn; + pInT2 = pPivotRowDst; + + /* Pivot element of the row */ + in = *pPivotRowIn; + + /* Loop over number of columns + * to the right of the pilot element */ + j = (numCols - l); + + while (j > 0U) + { + /* Divide each element of the row of the input matrix + * by the pivot element */ + in1 = *pInT1; + *pInT1++ = in1 / in; + + /* Decrement the loop counter */ + j--; + } + + /* Loop over number of columns of the destination matrix */ + j = numCols; + + while (j > 0U) + { + /* Divide each element of the row of the destination matrix + * by the pivot element */ + in1 = *pInT2; + *pInT2++ = in1 / in; + + /* Decrement the loop counter */ + j--; + } + + /* Replace the rows with the sum of that row and a multiple of row i + * so that each new element in column i above row i is zero.*/ + + /* Temporary pointers for input and destination matrices */ + pInT1 = pIn; + pInT2 = pOut; + + /* index used to check for pivot element */ + i = 0U; + + /* Loop over number of rows */ + /* to be replaced by the sum of that row and a multiple of row i */ + k = numRows; + + while (k > 0U) + { + /* Check for the pivot element */ + if (i == l) + { + /* If the processing element is the pivot element, + only the columns to the right are to be processed */ + pInT1 += numCols - l; + + pInT2 += numCols; + } + else + { + /* Element of the reference row */ + in = *pInT1; + + /* Working pointers for input and destination pivot rows */ + pPRT_in = pPivotRowIn; + pPRT_pDst = pPivotRowDst; + + /* Loop over the number of columns to the right of the pivot element, + to replace the elements in the input matrix */ + j = (numCols - l); + + while (j > 0U) + { + /* Replace the element by the sum of that row + and a multiple of the reference row */ + in1 = *pInT1; + *pInT1++ = in1 - (in * *pPRT_in++); + + /* Decrement the loop counter */ + j--; + } + + /* Loop over the number of columns to + replace the elements in the destination matrix */ + j = numCols; + + while (j > 0U) + { + /* Replace the element by the sum of that row + and a multiple of the reference row */ + in1 = *pInT2; + *pInT2++ = in1 - (in * *pPRT_pDst++); + + /* Decrement loop counter */ + j--; + } + + } + + /* Increment temporary input pointer */ + pInT1 = pInT1 + l; + + /* Decrement loop counter */ + k--; + + /* Increment pivot index */ + i++; + } + + /* Increment the input pointer */ + pIn++; + + /* Decrement the loop counter */ + loopCnt--; + + /* Increment the index modifier */ + l++; + } + + +#else + + float64_t Xchg, in = 0.0; /* Temporary input values */ + uint32_t i, rowCnt, flag = 0U, j, loopCnt, l; /* loop counters */ + riscv_status status; /* status of matrix inverse */ + +#ifdef RISCV_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pSrc->numCols) || + (pDst->numRows != pDst->numCols) || + (pSrc->numRows != pDst->numRows) ) + { + /* Set status as RISCV_MATH_SIZE_MISMATCH */ + status = RISCV_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef RISCV_MATH_MATRIX_CHECK */ + + { + + /*-------------------------------------------------------------------------------------------------------------- + * Matrix Inverse can be solved using elementary row operations. + * + * Gauss-Jordan Method: + * + * 1. First combine the identity matrix and the input matrix separated by a bar to form an + * augmented matrix as follows: + * _ _ _ _ _ _ _ _ + * | | a11 a12 | | | 1 0 | | | X11 X12 | + * | | | | | | | = | | + * |_ |_ a21 a22 _| | |_0 1 _| _| |_ X21 X21 _| + * + * 2. In our implementation, pDst Matrix is used as identity matrix. + * + * 3. Begin with the first row. Let i = 1. + * + * 4. Check to see if the pivot for row i is zero. + * The pivot is the element of the main diagonal that is on the current row. + * For instance, if working with row i, then the pivot element is aii. + * If the pivot is zero, exchange that row with a row below it that does not + * contain a zero in column i. If this is not possible, then an inverse + * to that matrix does not exist. + * + * 5. Divide every element of row i by the pivot. + * + * 6. For every row below and row i, replace that row with the sum of that row and + * a multiple of row i so that each new element in column i below row i is zero. + * + * 7. Move to the next row and column and repeat steps 2 through 5 until you have zeros + * for every element below and above the main diagonal. + * + * 8. Now an identical matrix is formed to the left of the bar(input matrix, src). + * Therefore, the matrix to the right of the bar is our solution(dst matrix, dst). + *----------------------------------------------------------------------------------------------------------------*/ + + /* Working pointer for destination matrix */ + pOutT1 = pOut; + + /* Loop over the number of rows */ + rowCnt = numRows; + + /* Making the destination matrix as identity matrix */ + while (rowCnt > 0U) + { + /* Writing all zeroes in lower triangle of the destination matrix */ + j = numRows - rowCnt; + while (j > 0U) + { + *pOutT1++ = 0.0; + j--; + } + + /* Writing all ones in the diagonal of the destination matrix */ + *pOutT1++ = 1.0; + + /* Writing all zeroes in upper triangle of the destination matrix */ + j = rowCnt - 1U; + while (j > 0U) + { + *pOutT1++ = 0.0; + j--; + } + + /* Decrement loop counter */ + rowCnt--; + } + + /* Loop over the number of columns of the input matrix. + All the elements in each column are processed by the row operations */ + loopCnt = numCols; + + /* Index modifier to navigate through the columns */ + l = 0U; + + while (loopCnt > 0U) + { + /* Check if the pivot element is zero.. + * If it is zero then interchange the row with non zero row below. + * If there is no non zero element to replace in the rows below, + * then the matrix is Singular. */ + + /* Working pointer for the input matrix that points + * to the pivot element of the particular row */ + pInT1 = pIn + (l * numCols); + + /* Working pointer for the destination matrix that points + * to the pivot element of the particular row */ + pOutT1 = pOut + (l * numCols); + + /* Temporary variable to hold the pivot value */ + in = *pInT1; + + /* Check if the pivot element is zero */ + if (*pInT1 == 0.0) + { + /* Loop over the number rows present below */ + for (i = 1U; i < numRows-l; i++) + { + /* Update the input and destination pointers */ + pInT2 = pInT1 + (numCols * i); + pOutT2 = pOutT1 + (numCols * i); + + /* Check if there is a non zero pivot element to + * replace in the rows below */ + if (*pInT2 != 0.0) + { + /* Loop over number of columns + * to the right of the pilot element */ + for (j = 0U; j < (numCols - l); j++) + { + /* Exchange the row elements of the input matrix */ + Xchg = *pInT2; + *pInT2++ = *pInT1; + *pInT1++ = Xchg; + } + + for (j = 0U; j < numCols; j++) + { + Xchg = *pOutT2; + *pOutT2++ = *pOutT1; + *pOutT1++ = Xchg; + } + + /* Flag to indicate whether exchange is done or not */ + flag = 1U; + + /* Break after exchange is done */ + break; + } + } + } + + + /* Update the status if the matrix is singular */ + if ((flag != 1U) && (in == 0.0)) + { + return RISCV_MATH_SINGULAR; + } + + /* Points to the pivot row of input and destination matrices */ + pPivotRowIn = pIn + (l * numCols); + pPivotRowDst = pOut + (l * numCols); + + /* Temporary pointers to the pivot row pointers */ + pInT1 = pPivotRowIn; + pOutT1 = pPivotRowDst; + + /* Pivot element of the row */ + in = *(pIn + (l * numCols)); + + /* Loop over number of columns + * to the right of the pilot element */ + for (j = 0U; j < (numCols - l); j++) + { + /* Divide each element of the row of the input matrix + * by the pivot element */ + *pInT1 = *pInT1 / in; + pInT1++; + } + for (j = 0U; j < numCols; j++) + { + /* Divide each element of the row of the destination matrix + * by the pivot element */ + *pOutT1 = *pOutT1 / in; + pOutT1++; + } + + /* Replace the rows with the sum of that row and a multiple of row i + * so that each new element in column i above row i is zero.*/ + + /* Temporary pointers for input and destination matrices */ + pInT1 = pIn; + pOutT1 = pOut; + + for (i = 0U; i < numRows; i++) + { + /* Check for the pivot element */ + if (i == l) + { + /* If the processing element is the pivot element, + only the columns to the right are to be processed */ + pInT1 += numCols - l; + pOutT1 += numCols; + } + else + { + /* Element of the reference row */ + in = *pInT1; + + /* Working pointers for input and destination pivot rows */ + pPRT_in = pPivotRowIn; + pPRT_pDst = pPivotRowDst; + + /* Loop over the number of columns to the right of the pivot element, + to replace the elements in the input matrix */ + for (j = 0U; j < (numCols - l); j++) + { + /* Replace the element by the sum of that row + and a multiple of the reference row */ + *pInT1 = *pInT1 - (in * *pPRT_in++); + pInT1++; + } + + /* Loop over the number of columns to + replace the elements in the destination matrix */ + for (j = 0U; j < numCols; j++) + { + /* Replace the element by the sum of that row + and a multiple of the reference row */ + *pOutT1 = *pOutT1 - (in * *pPRT_pDst++); + pOutT1++; + } + + } + + /* Increment temporary input pointer */ + pInT1 = pInT1 + l; + } + + /* Increment the input pointer */ + pIn++; + + /* Decrement the loop counter */ + loopCnt--; + + /* Increment the index modifier */ + l++; + } + +#endif /* #if defined (RISCV_MATH_DSP) */ + + /* Set status as RISCV_MATH_SUCCESS */ + status = RISCV_MATH_SUCCESS; + + if ((flag != 1U) && (in == 0.0)) + { + pIn = pSrc->pData; + for (i = 0; i < numRows * numCols; i++) + { + if (pIn[i] != 0.0) + break; + } + + if (i == numRows * numCols) + status = RISCV_MATH_SINGULAR; + } + } + + /* Return to application */ + return (status); +} + +/** + @} end of MatrixInv group + */ diff --git a/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_ldlt_f32.c b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_ldlt_f32.c new file mode 100644 index 00000000..8786f930 --- /dev/null +++ b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_ldlt_f32.c @@ -0,0 +1,211 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_mat_ldl_f32.c + * Description: Floating-point LDL decomposition + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + + + + + + +/// @private +#define SWAP_ROWS_F32(A,i,j) \ + for(int w=0;w < n; w++) \ + { \ + float32_t tmp; \ + tmp = A[i*n + w]; \ + A[i*n + w] = A[j*n + w];\ + A[j*n + w] = tmp; \ + } + +/// @private +#define SWAP_COLS_F32(A,i,j) \ + for(int w=0;w < n; w++) \ + { \ + float32_t tmp; \ + tmp = A[w*n + i]; \ + A[w*n + i] = A[w*n + j];\ + A[w*n + j] = tmp; \ + } + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixChol + @{ + */ + +/** + * @brief Floating-point LDL^t decomposition of positive semi-definite matrix. + * @param[in] pSrc points to the instance of the input floating-point matrix structure. + * @param[out] pl points to the instance of the output floating-point triangular matrix structure. + * @param[out] pd points to the instance of the output floating-point diagonal matrix structure. + * @param[out] pp points to the instance of the output floating-point permutation vector. + * @return The function returns RISCV_MATH_SIZE_MISMATCH, if the dimensions do not match. + * @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_SIZE_MISMATCH : Matrix size check failed + - \ref RISCV_MATH_DECOMPOSITION_FAILURE : Input matrix cannot be decomposed + * @par + * Computes the LDL^t decomposition of a matrix A such that P A P^t = L D L^t. + */ +riscv_status riscv_mat_ldlt_f32( + const riscv_matrix_instance_f32 * pSrc, + riscv_matrix_instance_f32 * pl, + riscv_matrix_instance_f32 * pd, + uint16_t * pp) +{ + + riscv_status status; /* status of matrix inverse */ + + +#ifdef RISCV_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pSrc->numCols) || + (pl->numRows != pl->numCols) || + (pd->numRows != pd->numCols) || + (pl->numRows != pd->numRows) ) + { + /* Set status as RISCV_MATH_SIZE_MISMATCH */ + status = RISCV_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef RISCV_MATH_MATRIX_CHECK */ + + { + + const int n=pSrc->numRows; + int fullRank = 1, diag,k; + float32_t *pA; + + memcpy(pl->pData,pSrc->pData,n*n*sizeof(float32_t)); + pA = pl->pData; + + for(int k=0;k < n; k++) + { + pp[k] = k; + } + + + for(k=0;k < n; k++) + { + /* Find pivot */ + float32_t m=F32_MIN,a; + int j=k; + + + for(int r=k;r m) + { + m = pA[r*n+r]; + j = r; + } + } + + if(j != k) + { + SWAP_ROWS_F32(pA,k,j); + SWAP_COLS_F32(pA,k,j); + } + + + pp[k] = j; + + a = pA[k*n+k]; + + if (fabs(a) < 1.0e-8) + { + + fullRank = 0; + break; + } + + for(int w=k+1;wpData[row*n+col]=0.0; + } + } + } + + for(int row=0; row < n;row++) + { + for(int col=row+1; col < n;col++) + { + pl->pData[row*n+col] = 0.0; + } + } + + for(int d=0; d < diag;d++) + { + pd->pData[d*n+d] = pl->pData[d*n+d]; + pl->pData[d*n+d] = 1.0; + } + + status = RISCV_MATH_SUCCESS; + + } + + + /* Return to application */ + return (status); +} + +/** + @} end of MatrixChol group + */ diff --git a/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_ldlt_f64.c b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_ldlt_f64.c new file mode 100644 index 00000000..814f9779 --- /dev/null +++ b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_ldlt_f64.c @@ -0,0 +1,209 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_mat_ldl_f64.c + * Description: Floating-point LDL decomposition + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" +#include + + + +/// @private +#define SWAP_ROWS_F64(A,i,j) \ + for(int w=0;w < n; w++) \ + { \ + float64_t tmp; \ + tmp = A[i*n + w]; \ + A[i*n + w] = A[j*n + w];\ + A[j*n + w] = tmp; \ + } +/// @private +#define SWAP_COLS_F64(A,i,j) \ + for(int w=0;w < n; w++) \ + { \ + float64_t tmp; \ + tmp = A[w*n + i]; \ + A[w*n + i] = A[w*n + j];\ + A[w*n + j] = tmp; \ + } + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixChol + @{ + */ + +/** + * @brief Floating-point LDL^t decomposition of positive semi-definite matrix. + * @param[in] pSrc points to the instance of the input floating-point matrix structure. + * @param[out] pl points to the instance of the output floating-point triangular matrix structure. + * @param[out] pd points to the instance of the output floating-point diagonal matrix structure. + * @param[out] pp points to the instance of the output floating-point permutation vector. + * @return The function returns RISCV_MATH_SIZE_MISMATCH, if the dimensions do not match. + * @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_SIZE_MISMATCH : Matrix size check failed + - \ref RISCV_MATH_DECOMPOSITION_FAILURE : Input matrix cannot be decomposed + * @par + * Computes the LDL^t decomposition of a matrix A such that P A P^t = L D L^t. + */ + +riscv_status riscv_mat_ldlt_f64( + const riscv_matrix_instance_f64 * pSrc, + riscv_matrix_instance_f64 * pl, + riscv_matrix_instance_f64 * pd, + uint16_t * pp) +{ + + riscv_status status; /* status of matrix inverse */ + + +#ifdef RISCV_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pSrc->numCols) || + (pl->numRows != pl->numCols) || + (pd->numRows != pd->numCols) || + (pl->numRows != pd->numRows) ) + { + /* Set status as RISCV_MATH_SIZE_MISMATCH */ + status = RISCV_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef RISCV_MATH_MATRIX_CHECK */ + + { + + const int n=pSrc->numRows; + int fullRank = 1, diag,k; + float64_t *pA; + + memcpy(pl->pData,pSrc->pData,n*n*sizeof(float64_t)); + pA = pl->pData; + + for(int k=0;k < n; k++) + { + pp[k] = k; + } + + + for(k=0;k < n; k++) + { + /* Find pivot */ + float64_t m=F64_MIN,a; + int j=k; + + + for(int r=k;r m) + { + m = pA[r*n+r]; + j = r; + } + } + + if(j != k) + { + SWAP_ROWS_F64(pA,k,j); + SWAP_COLS_F64(pA,k,j); + } + + + pp[k] = j; + + a = pA[k*n+k]; + + if (fabs(a) < 1.0e-18) + { + + fullRank = 0; + break; + } + + for(int w=k+1;wpData[row*n+col]=0.0; + } + } + } + + for(int row=0; row < n;row++) + { + for(int col=row+1; col < n;col++) + { + pl->pData[row*n+col] = 0.0; + } + } + + for(int d=0; d < diag;d++) + { + pd->pData[d*n+d] = pl->pData[d*n+d]; + pl->pData[d*n+d] = 1.0; + } + + status = RISCV_MATH_SUCCESS; + + } + + + /* Return to application */ + return (status); +} + +/** + @} end of MatrixChol group + */ diff --git a/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_mult_f16.c b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_mult_f16.c new file mode 100644 index 00000000..6845994b --- /dev/null +++ b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_mult_f16.c @@ -0,0 +1,194 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_mat_mult_f16.c + * Description: Floating-point matrix multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions_f16.h" + +#if defined(RISCV_FLOAT16_SUPPORTED) + + +/** + * @ingroup groupMatrix + */ + + +/** + * @addtogroup MatrixMult + * @{ + */ + +/** + * @brief Floating-point matrix multiplication. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * RISCV_MATH_SIZE_MISMATCH or RISCV_MATH_SUCCESS based on the outcome of size checking. + */ + + + +riscv_status riscv_mat_mult_f16( + const riscv_matrix_instance_f16 * pSrcA, + const riscv_matrix_instance_f16 * pSrcB, + riscv_matrix_instance_f16 * pDst) +{ + float16_t *pIn1 = pSrcA->pData; /* Input data matrix pointer A */ + float16_t *pIn2 = pSrcB->pData; /* Input data matrix pointer B */ + float16_t *pInA = pSrcA->pData; /* Input data matrix pointer A */ + float16_t *pInB = pSrcB->pData; /* Input data matrix pointer B */ + float16_t *pOut = pDst->pData; /* Output data matrix pointer */ + float16_t *px; /* Temporary output data matrix pointer */ + _Float16 sum; /* Accumulator */ + uint16_t numRowsA = pSrcA->numRows; /* Number of rows of input matrix A */ + uint16_t numColsB = pSrcB->numCols; /* Number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* Number of columns of input matrix A */ + uint32_t col, i = 0U, row = numRowsA, colCnt; /* Loop counters */ + riscv_status status; /* Status of matrix multiplication */ + +#ifdef RISCV_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as RISCV_MATH_SIZE_MISMATCH */ + status = RISCV_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef RISCV_MATH_MATRIX_CHECK */ + + { + /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */ + /* row loop */ + do + { + /* Output pointer is set to starting address of row being processed */ + px = pOut + i; + + /* For every row wise process, column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, pIn2 pointer is set to starting address of pSrcB data */ + pIn2 = pSrcB->pData; + + /* column loop */ + do + { + /* Set the variable sum, that acts as accumulator, to zero */ + sum = 0.0f16; + + /* Initialize pointer pIn1 to point to starting address of column being processed */ + pIn1 = pInA; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 MACs at a time. */ + colCnt = numColsA >> 2U; + + /* matrix multiplication */ + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + + /* Perform the multiply-accumulates */ + sum += *pIn1++ * *pIn2; + pIn2 += numColsB; + + sum += *pIn1++ * *pIn2; + pIn2 += numColsB; + + sum += *pIn1++ * *pIn2; + pIn2 += numColsB; + + sum += *pIn1++ * *pIn2; + pIn2 += numColsB; + + /* Decrement loop counter */ + colCnt--; + } + + /* Loop unrolling: Compute remaining MACs */ + colCnt = numColsA % 0x4U; + +#else + + /* Initialize cntCnt with number of columns */ + colCnt = numColsA; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + + /* Perform the multiply-accumulates */ + sum += *pIn1++ * *pIn2; + pIn2 += numColsB; + + /* Decrement loop counter */ + colCnt--; + } + + /* Store result in destination buffer */ + *px++ = sum; + + /* Decrement column loop counter */ + col--; + + /* Update pointer pIn2 to point to starting address of next column */ + pIn2 = pInB + (numColsB - col); + + } while (col > 0U); + + /* Update pointer pInA to point to starting address of next row */ + i = i + numColsB; + pInA = pInA + numColsA; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); + + /* Set status as RISCV_MATH_SUCCESS */ + status = RISCV_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + + +/** + * @} end of MatrixMult group + */ + +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ + diff --git a/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_mult_f32.c b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_mult_f32.c new file mode 100644 index 00000000..0cfc99a0 --- /dev/null +++ b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_mult_f32.c @@ -0,0 +1,252 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_mat_mult_f32.c + * Description: Floating-point matrix multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + * @ingroup groupMatrix + */ + +/** + * @defgroup MatrixMult Matrix Multiplication + * + * Multiplies two matrices. + * + * \image html MatrixMultiplication.png "Multiplication of two 3 x 3 matrices" + + * Matrix multiplication is only defined if the number of columns of the + * first matrix equals the number of rows of the second matrix. + * Multiplying an M x N matrix with an N x P matrix results + * in an M x P matrix. + * When matrix size checking is enabled, the functions check: (1) that the inner dimensions of + * pSrcA and pSrcB are equal; and (2) that the size of the output + * matrix equals the outer dimensions of pSrcA and pSrcB. + */ + + +/** + * @addtogroup MatrixMult + * @{ + */ + +/** + * @brief Floating-point matrix multiplication. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * RISCV_MATH_SIZE_MISMATCH or RISCV_MATH_SUCCESS based on the outcome of size checking. + */ + + +riscv_status riscv_mat_mult_f32( + const riscv_matrix_instance_f32 * pSrcA, + const riscv_matrix_instance_f32 * pSrcB, + riscv_matrix_instance_f32 * pDst) +{ + float32_t *pIn1 = pSrcA->pData; /* Input data matrix pointer A */ + float32_t *pIn2 = pSrcB->pData; /* Input data matrix pointer B */ + float32_t *pInA = pSrcA->pData; /* Input data matrix pointer A */ + float32_t *pInB = pSrcB->pData; /* Input data matrix pointer B */ + float32_t *pOut = pDst->pData; /* Output data matrix pointer */ + float32_t *px; /* Temporary output data matrix pointer */ + float32_t sum; /* Accumulator */ + uint16_t numRowsA = pSrcA->numRows; /* Number of rows of input matrix A */ + uint16_t numColsB = pSrcB->numCols; /* Number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* Number of columns of input matrix A */ + uint32_t col, i = 0U, row = numRowsA, colCnt; /* Loop counters */ + riscv_status status; /* Status of matrix multiplication */ + +#ifdef RISCV_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as RISCV_MATH_SIZE_MISMATCH */ + status = RISCV_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef RISCV_MATH_MATRIX_CHECK */ +#if defined(RISCV_VECTOR) + uint16_t blkCnt = numColsA; //number of matrix columns numColsA = numrowB + size_t l,max_l; // max_l is the maximum column elements at a time + ptrdiff_t bstride = 4; // 32bit/8bit = 4 + ptrdiff_t col_diff = bstride * numColsB; //Control the column width of the span + uint16_t colnum,rownum; // How many rowumns and rownum are controlled + vfloat32m8_t v_inA, v_inB; + vfloat32m8_t vmul; + l = vsetvl_e32m1(1); + vfloat32m1_t vsum = vfmv_s_f_f32m1(vsum, 0.0f, l); + // max_l = vsetvl_e32m8(32); + px = pOut; +for(rownum = 0;rownum < numRowsA; rownum++) + { + pIn1 = pInA; //backup pointer position + for(colnum = 0;colnum < numColsB; colnum++) + { + blkCnt = numColsA; + pIn2 = pInB; //backup pointer position + sum = 0.0f; + l = vsetvl_e32m1(1); + vsum = vfmv_s_f_f32m1(vsum, 0.0f, l); + for (; (l = vsetvl_e32m8(blkCnt)) > 0; blkCnt -= l) //Multiply a row by a column + { + v_inA = vle32_v_f32m8(pInA, l); + v_inB = vlse32_v_f32m8(pInB, col_diff, l); + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + /* Perform multiply-accumulates */ + vmul = vfmul_vv_f32m8(v_inA, v_inB, l); + vsum = vfredsum_vs_f32m8_f32m1(vsum, vmul, vsum, l); + sum = vfmv_f_s_f32m1_f32 (vsum); + // if(l == max_l) + // { + pInA = pInA+l; //Pointer to the first element of the next line + pInB = pInB+l*numColsB; + // } + } + *px = sum; + px++; + pInA = pIn1; + pInB = pIn2;pInB = pInB+1; //Pointer to the first element of the next column for matrix BS + //printf("px=%d\n",px); + } + pInB = pSrcB->pData; + pInA = pIn1;pInA = pInA+numColsA; //Pointer to the first element of the next row for matrix A + } + /* Set status as RISCV_MATH_SUCCESS */ + status = RISCV_MATH_SUCCESS; +#else + { + /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */ + /* row loop */ + do + { + /* Output pointer is set to starting address of row being processed */ + px = pOut + i; + + /* For every row wise process, column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, pIn2 pointer is set to starting address of pSrcB data */ + pIn2 = pSrcB->pData; + + /* column loop */ + do + { + /* Set the variable sum, that acts as accumulator, to zero */ + sum = 0.0f; + + /* Initialize pointer pIn1 to point to starting address of column being processed */ + pIn1 = pInA; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 MACs at a time. */ + colCnt = numColsA >> 2U; + + /* matrix multiplication */ + while (colCnt > 0U) + { + /* c(m,p) = a(m,1) * b(1,p) + a(m,2) * b(2,p) + .... + a(m,n) * b(n,p) */ + + /* Perform the multiply-accumulates */ + sum += *pIn1++ * *pIn2; + pIn2 += numColsB; + + sum += *pIn1++ * *pIn2; + pIn2 += numColsB; + + sum += *pIn1++ * *pIn2; + pIn2 += numColsB; + + sum += *pIn1++ * *pIn2; + pIn2 += numColsB; + + /* Decrement loop counter */ + colCnt--; + } + + /* Loop unrolling: Compute remaining MACs */ + colCnt = numColsA % 0x4U; + +#else + + /* Initialize cntCnt with number of columns */ + colCnt = numColsA; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (colCnt > 0U) + { + /* c(m,p) = a(m,1) * b(1,p) + a(m,2) * b(2,p) + .... + a(m,n) * b(n,p) */ + + /* Perform the multiply-accumulates */ + sum += *pIn1++ * *pIn2; + pIn2 += numColsB; + + /* Decrement loop counter */ + colCnt--; + } + + /* Store result in destination buffer */ + *px++ = sum; + + /* Decrement column loop counter */ + col--; + + /* Update pointer pIn2 to point to starting address of next column */ + pIn2 = pInB + (numColsB - col); + + } while (col > 0U); + + /* Update pointer pInA to point to starting address of next row */ + i = i + numColsB; + pInA = pInA + numColsA; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); + + /* Set status as RISCV_MATH_SUCCESS */ + status = RISCV_MATH_SUCCESS; + } + +#endif /*defined(RISCV_VECTOR)*/ + /* Return to application */ + return (status); +} + + +/** + * @} end of MatrixMult group + */ diff --git a/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_mult_f64.c b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_mult_f64.c new file mode 100644 index 00000000..9afdbe48 --- /dev/null +++ b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_mult_f64.c @@ -0,0 +1,203 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_mat_mult_f64.c + * Description: Floating-point matrix multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + * @ingroup groupMatrix + */ + +/** + * @defgroup MatrixMult Matrix Multiplication + * + * Multiplies two matrices. + * + * \image html MatrixMultiplication.png "Multiplication of two 3 x 3 matrices" + + * Matrix multiplication is only defined if the number of columns of the + * first matrix equals the number of rows of the second matrix. + * Multiplying an M x N matrix with an N x P matrix results + * in an M x P matrix. + * When matrix size checking is enabled, the functions check: (1) that the inner dimensions of + * pSrcA and pSrcB are equal; and (2) that the size of the output + * matrix equals the outer dimensions of pSrcA and pSrcB. + */ + + +/** + * @addtogroup MatrixMult + * @{ + */ + +/** + * @brief Floating-point matrix multiplication. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * RISCV_MATH_SIZE_MISMATCH or RISCV_MATH_SUCCESS based on the outcome of size checking. + */ + + +riscv_status riscv_mat_mult_f64( + const riscv_matrix_instance_f64 * pSrcA, + const riscv_matrix_instance_f64 * pSrcB, + riscv_matrix_instance_f64 * pDst) +{ + float64_t *pIn1 = pSrcA->pData; /* Input data matrix pointer A */ + float64_t *pIn2 = pSrcB->pData; /* Input data matrix pointer B */ + float64_t *pInA = pSrcA->pData; /* Input data matrix pointer A */ + float64_t *pInB = pSrcB->pData; /* Input data matrix pointer B */ + float64_t *pOut = pDst->pData; /* Output data matrix pointer */ + float64_t *px; /* Temporary output data matrix pointer */ + float64_t sum; /* Accumulator */ + uint16_t numRowsA = pSrcA->numRows; /* Number of rows of input matrix A */ + uint16_t numColsB = pSrcB->numCols; /* Number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* Number of columns of input matrix A */ + uint64_t col, i = 0U, row = numRowsA, colCnt; /* Loop counters */ + riscv_status status; /* Status of matrix multiplication */ + +#ifdef RISCV_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as RISCV_MATH_SIZE_MISMATCH */ + status = RISCV_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef RISCV_MATH_MATRIX_CHECK */ + + { + /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */ + /* row loop */ + do + { + /* Output pointer is set to starting address of row being processed */ + px = pOut + i; + + /* For every row wise process, column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, pIn2 pointer is set to starting address of pSrcB data */ + pIn2 = pSrcB->pData; + + /* column loop */ + do + { + /* Set the variable sum, that acts as accumulator, to zero */ + sum = 0.0f; + + /* Initialize pointer pIn1 to point to starting address of column being processed */ + pIn1 = pInA; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 MACs at a time. */ + colCnt = numColsA >> 2U; + + /* matrix multiplication */ + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + + /* Perform the multiply-accumulates */ + sum += *pIn1++ * *pIn2; + pIn2 += numColsB; + + sum += *pIn1++ * *pIn2; + pIn2 += numColsB; + + sum += *pIn1++ * *pIn2; + pIn2 += numColsB; + + sum += *pIn1++ * *pIn2; + pIn2 += numColsB; + + /* Decrement loop counter */ + colCnt--; + } + + /* Loop unrolling: Compute remaining MACs */ + colCnt = numColsA % 0x4U; + +#else + + /* Initialize cntCnt with number of columns */ + colCnt = numColsA; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + + /* Perform the multiply-accumulates */ + sum += *pIn1++ * *pIn2; + pIn2 += numColsB; + + /* Decrement loop counter */ + colCnt--; + } + + /* Store result in destination buffer */ + *px++ = sum; + + /* Decrement column loop counter */ + col--; + + /* Update pointer pIn2 to point to starting address of next column */ + pIn2 = pInB + (numColsB - col); + + } while (col > 0U); + + /* Update pointer pInA to point to starting address of next row */ + i = i + numColsB; + pInA = pInA + numColsA; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); + + /* Set status as RISCV_MATH_SUCCESS */ + status = RISCV_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + + +/** + * @} end of MatrixMult group + */ diff --git a/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_mult_fast_q15.c b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_mult_fast_q15.c new file mode 100644 index 00000000..fe35d8c3 --- /dev/null +++ b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_mult_fast_q15.c @@ -0,0 +1,644 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_mat_mult_fast_q15.c + * Description: Q15 matrix multiplication (fast variant) + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixMult + @{ + */ + +/** + @brief Q15 matrix multiplication (fast variant). + @param[in] pSrcA points to the first input matrix structure + @param[in] pSrcB points to the second input matrix structure + @param[out] pDst points to output matrix structure + @param[in] pState points to the array for storing intermediate results + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_SIZE_MISMATCH : Matrix size check failed + + @par Scaling and Overflow Behavior + The difference between the function \ref riscv_mat_mult_q15() and this fast variant is that + the fast variant use a 32-bit rather than a 64-bit accumulator. + The result of each 1.15 x 1.15 multiplication is truncated to + 2.30 format. These intermediate results are accumulated in a 32-bit register in 2.30 + format. Finally, the accumulator is saturated and converted to a 1.15 result. + @par + The fast version has the same overflow behavior as the standard version but provides + less precision since it discards the low 16 bits of each multiplication result. + In order to avoid overflows completely the input signals must be scaled down. + Scale down one of the input matrices by log2(numColsA) bits to avoid overflows, + as a total of numColsA additions are computed internally for each output element. + @remark + Refer to \ref riscv_mat_mult_q15() for a slower implementation of this function + which uses 64-bit accumulation to provide higher precision. + */ + +riscv_status riscv_mat_mult_fast_q15( + const riscv_matrix_instance_q15 * pSrcA, + const riscv_matrix_instance_q15 * pSrcB, + riscv_matrix_instance_q15 * pDst, + q15_t * pState) +{ + q31_t sum; /* Accumulator */ + q15_t *pSrcBT = pState; /* Input data matrix pointer for transpose */ + q15_t *pInA = pSrcA->pData; /* Input data matrix pointer A of Q15 type */ + q15_t *pInB = pSrcB->pData; /* Input data matrix pointer B of Q15 type */ + q15_t *px; /* Temporary output data matrix pointer */ + uint16_t numRowsA = pSrcA->numRows; /* Number of rows of input matrix A */ + uint16_t numColsB = pSrcB->numCols; /* Number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* Number of columns of input matrix A */ + uint16_t numRowsB = pSrcB->numRows; /* Number of rows of input matrix B */ + uint32_t col, i = 0U, row = numRowsB, colCnt; /* Loop counters */ + riscv_status status; /* Status of matrix multiplication */ + +#if defined(RISCV_VECTOR) + q15_t in; /* Temporary variable to hold the input value */ + q15_t inA1, inB1, inA2, inB2; + uint16_t blkCnt; //number of matrix columns numColsA = numrowB + size_t l; // max_l is the maximum column elements at a time + ptrdiff_t bstride = 4; // 32bit/8bit = 4 + uint16_t colnum,rownum; // How many rowumns and rownum are controlled + vint16m4_t v_inA, v_inB; + vint32m8_t v_sum; + vint16m8_t vReal, vImag; + l = vsetvl_e32m1(1); + vint32m1_t vtemp = vsub_vv_i32m1(vtemp, vtemp, l); + +#ifdef RISCV_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as RISCV_MATH_SIZE_MISMATCH */ + status = RISCV_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef RISCV_MATH_MATRIX_CHECK */ + + { + /* Matrix transpose */ + do + { + /* The pointer px is set to starting address of column being processed */ + px = pSrcBT + i; + + col = numColsB ; + blkCnt = col; + bstride = numRowsB*2; + for (; (l = vsetvl_e16m8(blkCnt)) > 0; blkCnt -= l) //Multiply a row by a column + { + vsse16_v_i16m8(px,bstride,vle16_v_i16m8(pInB, l), l); + px += l*numRowsB; + pInB += l; + } + + i++; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); + + /* Reset variables for usage in following multiplication process */ + row = numRowsA; + i = 0U; + px = pDst->pData; + + /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */ + /* row loop */ + while (row > 0U) + { + /* For every row wise process, column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, pIn2 pointer is set to starting address of transposed pSrcB data */ + pInB = pSrcBT; + + /* column loop */ + while (col > 0U) + { + /* Set variable sum, that acts as accumulator, to zero */ + sum = 0; + + /* Initiate pointer pInA to point to starting address of column being processed */ + pInA = pSrcA->pData + i; + + /* process odd column samples */ + colCnt = numColsA; + + blkCnt = colCnt; + l = vsetvl_e16m4(blkCnt); + v_sum = vsub_vv_i32m8(v_sum,v_sum, l); + for (; (l = vsetvl_e16m4(blkCnt)) > 0; blkCnt -= l) //Multiply a row by a column + { + v_inA = vle16_v_i16m4(pInA, l); + v_inB = vle16_v_i16m4(pInB, l); + pInA += l; + pInB += l; + v_sum = vwmacc_vv_i32m8(v_sum,v_inA,v_inB, l); + } + l = vsetvl_e16m4(colCnt); + sum = vmv_x_s_i32m1_i32 (vredsum_vs_i32m8_i32m1(vtemp, v_sum, vtemp, l)); + + /* Saturate and store result in destination buffer */ + *px++ = (q15_t) (sum >> 15); + + /* Decrement column loop counter */ + col--; + + } + + i = i + numColsA; + + /* Decrement row loop counter */ + row--; + + } + /* Set status as RISCV_MATH_SUCCESS */ + status = RISCV_MATH_SUCCESS; + } + + +#else +#if defined (RISCV_MATH_DSP) && (__RISCV_XLEN == 64) + q63_t in64; /* Temporary variable to hold the input value */ + q63_t sum64=0, sum264=0, sum364=0, sum464=0; + q63_t inA164, inA264, inB164, inB264 ; +#endif /* defined RISCV_MATH_DSP || (__RISCV_XLEN == 64) */ +#if defined (RISCV_MATH_DSP) + q31_t in; /* Temporary variable to hold the input value */ + q31_t inA1, inB1, inA2, inB2; + q31_t sum2, sum3, sum4; + q15_t *pInA2, *pInB2, *px2; + uint32_t j = 0; +#else + q15_t in; /* Temporary variable to hold the input value */ + q15_t inA1, inB1, inA2, inB2; +#endif /* #if defined (RISCV_MATH_DSP) */ + +#ifdef RISCV_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as RISCV_MATH_SIZE_MISMATCH */ + status = RISCV_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef RISCV_MATH_MATRIX_CHECK */ + + { + /* Matrix transpose */ + do + { + /* The pointer px is set to starting address of column being processed */ + px = pSrcBT + i; + + /* Apply loop unrolling and exchange columns with row elements */ + col = numColsB >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (col > 0U) + { + +#if defined (RISCV_MATH_DSP) +// #if __RISCV_XLEN == 64 +// /* Read two elements from row */ +// in64 = read_q15x4_ia ((q15_t **) &pInB); +// *px = (q15_t) ((in64) >> 16); +// px += numRowsB; +// *px = (q15_t) in64; +// px += numRowsB; +// *px = (q15_t) ((in64) >> 48); +// px += numRowsB; +// *px = (q15_t) (in64 >> 32); +// px += numRowsB; +// #else + /* Read two elements from row */ + in = read_q15x2_ia ((q15_t **) &pInB); + + /* Unpack and store one element in destination */ + *px = (q15_t) in; + + /* Update pointer px to point to next row of transposed matrix */ + px += numRowsB; + + /* Unpack and store second element in destination */ + *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16); + + /* Update pointer px to point to next row of transposed matrix */ + px += numRowsB; + + in = read_q15x2_ia ((q15_t **) &pInB); + *px = (q15_t) in; + px += numRowsB; + + *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16); + px += numRowsB; +// #endif /* __RISCV_XLEN == 64 */ +#else /* #if defined (RISCV_MATH_DSP) */ + + /* Read one element from row */ + in = *pInB++; + + /* Store one element in destination */ + *px = in; + + /* Update pointer px to point to next row of transposed matrix */ + px += numRowsB; + + in = *pInB++; + *px = in; + px += numRowsB; + + in = *pInB++; + *px = in; + px += numRowsB; + + in = *pInB++; + *px = in; + px += numRowsB; + +#endif /* #if defined (RISCV_MATH_DSP) */ + + /* Decrement column loop counter */ + col--; + } + + /* If the columns of pSrcB is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + col = numColsB % 0x4U; + + while (col > 0U) + { + /* Read and store input element in destination */ + *px = *pInB++; + + /* Update pointer px to point to next row of transposed matrix */ + px += numRowsB; + + /* Decrement column loop counter */ + col--; + } + + i++; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); + + /* Reset variables for usage in following multiplication process */ + row = numRowsA; + i = 0U; + px = pDst->pData; + +#if defined (RISCV_MATH_DSP) + /* Process two rows from matrix A at a time and output two rows at a time */ + row = row >> 1U; + px2 = px + numColsB; +#endif + + /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */ + /* row loop */ + while (row > 0U) + { + /* For every row wise process, column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, pIn2 pointer is set to starting address of transposed pSrcB data */ + pInB = pSrcBT; + +#if defined (RISCV_MATH_DSP) + /* Process two (transposed) columns from matrix B at a time */ + col = col >> 1U; + j = 0; +#endif + + /* column loop */ + while (col > 0U) + { + /* Set variable sum, that acts as accumulator, to zero */ + sum = 0; + + /* Initiate pointer pInA to point to starting address of column being processed */ + pInA = pSrcA->pData + i; + +#if defined (RISCV_MATH_DSP) + sum2 = 0; + sum3 = 0; + sum4 = 0; + pInB = pSrcBT + j; + pInA2 = pInA + numColsA; + pInB2 = pInB + numRowsB; + + /* Read in two elements at once - allows dual MAC instruction */ + colCnt = numColsA >> 1U; +#else + colCnt = numColsA >> 2U; +#endif + + /* matrix multiplication */ + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + +#if defined (RISCV_MATH_DSP) +// #if __RISCV_XLEN == 64 +// /* read real and imag values from pSrcA and pSrcB buffer */ +// inA1 = read_q15x2_ia ((q15_t **) &pInA); +// inB1 = read_q15x2_ia ((q15_t **) &pInB); + +// inA2 = read_q15x2_ia ((q15_t **) &pInA2); +// inB2 = read_q15x2_ia ((q15_t **) &pInB2); + +// /* Multiply and Accumlates */ +// sum = ((uint32_t)(((((q31_t)inA1 << 16) >> 16) * (((q31_t)inB1 << 16) >> 16)) + +// ((((q31_t)inA1 ) >> 16) * (((q31_t)inB1 ) >> 16)) + +// ( ((q31_t)sum ) ) )); +// // ((inA1 & (uint32_t)0x0ffff) * (inB1 & (uint32_t)0x0ffff)) + (((inA1 >> 16) & (uint32_t)0x0ffff) * ((inB1 >> 16) & (uint32_t)0x0ffff)); +// sum2 = ((uint32_t)(((((q31_t)inA1 << 16) >> 16) * (((q31_t)inB2 << 16) >> 16)) + +// ((((q31_t)inA1 ) >> 16) * (((q31_t)inB2 ) >> 16)) + +// ( ((q31_t)sum ) ) )); +// // ((inA1 & (uint32_t)0x0ffff) * (inB2 & (uint32_t)0x0ffff)) + (((inA1 >> 16) & (uint32_t)0x0ffff) * ((inB2 >> 16) & (uint32_t)0x0ffff)); +// sum3 = ((uint32_t)(((((q31_t)inA2 << 16) >> 16) * (((q31_t)inB1 << 16) >> 16)) + +// ((((q31_t)inA2 ) >> 16) * (((q31_t)inB1 ) >> 16)) + +// ( ((q31_t)sum ) ) )); +// // ((inA2 & (uint32_t)0x0ffff) * (inB1 & (uint32_t)0x0ffff)) + (((inA2 >> 16) & (uint32_t)0x0ffff) * ((inB1 >> 16) & (uint32_t)0x0ffff)); +// sum4 = ((uint32_t)(((((q31_t)inA2 << 16) >> 16) * (((q31_t)inB2 << 16) >> 16)) + +// ((((q31_t)inA2 ) >> 16) * (((q31_t)inB2 ) >> 16)) + +// ( ((q31_t)sum ) ) )); +// // ((inA2 & (uint32_t)0x0ffff) * (inB2 & (uint32_t)0x0ffff)) + (((inA2 >> 16) & (uint32_t)0x0ffff) * ((inB2 >> 16) & (uint32_t)0x0ffff)); +// #else + /* read real and imag values from pSrcA and pSrcB buffer */ + inA1 = read_q15x2_ia ((q15_t **) &pInA); + inB1 = read_q15x2_ia ((q15_t **) &pInB); + + inA2 = read_q15x2_ia ((q15_t **) &pInA2); + inB2 = read_q15x2_ia ((q15_t **) &pInB2); + + /* Multiply and Accumlates */ + sum = __RV_KMADA(sum, inA1, inB1); + sum2 = __RV_KMADA(sum2, inA1, inB2); + sum3 = __RV_KMADA(sum3, inA2, inB1); + sum4 = __RV_KMADA(sum4, inA2, inB2); +// #endif /* __RISCV_XLEN == 64 */ +#else + /* read real and imag values from pSrcA and pSrcB buffer */ + inA1 = *pInA++; + inB1 = *pInB++; + /* Multiply and Accumulates */ + sum += inA1 * inB1; + + inA2 = *pInA++; + inB2 = *pInB++; + sum += inA2 * inB2; + + inA1 = *pInA++; + inB1 = *pInB++; + sum += inA1 * inB1; + + inA2 = *pInA++; + inB2 = *pInB++; + sum += inA2 * inB2; +#endif /* #if defined (RISCV_MATH_DSP) */ + + /* Decrement loop counter */ + colCnt--; + } + + /* process odd column samples */ +#if defined (RISCV_MATH_DSP) + if (numColsA & 1U) { + inA1 = *pInA++; + inB1 = *pInB++; + inA2 = *pInA2++; + inB2 = *pInB2++; + sum += inA1 * inB1; + sum2 += inA1 * inB2; + sum3 += inA2 * inB1; + sum4 += inA2 * inB2; + } +#else + colCnt = numColsA % 0x4U; + + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + sum += (q31_t) *pInA++ * *pInB++; + + /* Decrement loop counter */ + colCnt--; + } +#endif /* #if defined (RISCV_MATH_DSP) */ + + /* Saturate and store result in destination buffer */ + *px++ = (q15_t) (sum >> 15); + +#if defined (RISCV_MATH_DSP) + *px++ = (q15_t) (sum2 >> 15); + *px2++ = (q15_t) (sum3 >> 15); + *px2++ = (q15_t) (sum4 >> 15); + j += numRowsB * 2; +#endif + + /* Decrement column loop counter */ + col--; + + } + + i = i + numColsA; + +#if defined (RISCV_MATH_DSP) + i = i + numColsA; + px = px2 + (numColsB & 1U); + px2 = px + numColsB; +#endif + + /* Decrement row loop counter */ + row--; + + } + + /* Compute any remaining odd row/column below */ + +#if defined (RISCV_MATH_DSP) + + /* Compute remaining output column */ + if (numColsB & 1U) { + + /* Avoid redundant computation of last element */ + row = numRowsA & (~0x1); + + /* Point to remaining unfilled column in output matrix */ + px = pDst->pData + numColsB-1; + pInA = pSrcA->pData; + + /* row loop */ + while (row > 0) + { + + /* point to last column in matrix B */ + pInB = pSrcBT + numRowsB * (numColsB-1); +#if __RISCV_XLEN == 64 + sum64 = 0; +#endif + /* Set variable sum, that acts as accumulator, to zero */ + sum = 0; + + /* Compute 4 columns at once */ + colCnt = numColsA >> 2U; + + /* matrix multiplication */ + while (colCnt > 0U) + { +#if __RISCV_XLEN == 64 + inA164 = read_q15x4_ia ((q15_t **) &pInA); + inB164 = read_q15x4_ia ((q15_t **) &pInB); + + sum64 = __RV_KMADA(sum64, inA164, inB164); +#else + inA1 = read_q15x2_ia ((q15_t **) &pInA); + inA2 = read_q15x2_ia ((q15_t **) &pInA); + inB1 = read_q15x2_ia ((q15_t **) &pInB); + inB2 = read_q15x2_ia ((q15_t **) &pInB); + + sum = __RV_KMADA(sum, inA1, inB1); + sum = __RV_KMADA(sum, inA2, inB2); +#endif /* __RISCV_XLEN == 64 */ + + /* Decrement loop counter */ + colCnt--; + } +#if __RISCV_XLEN == 64 + sum = (q31_t) ((q31_t) (sum64 & 0xffffffff)) + ((q31_t) ((sum64 & 0xffffffff00000000)>> 32)); +#endif /* __RISCV_XLEN == 64 */ + colCnt = numColsA & 3U; + while (colCnt > 0U) { + sum += (q31_t) (*pInA++) * (*pInB++); + colCnt--; + } + + /* Store result in destination buffer */ + *px = (q15_t) (sum >> 15); + px += numColsB; + + /* Decrement row loop counter */ + row--; + } + } + + /* Compute remaining output row */ + if (numRowsA & 1U) { + + /* point to last row in output matrix */ + px = pDst->pData + (numColsB) * (numRowsA-1); + + pInB = pSrcBT; + col = numColsB; + i = 0U; + + /* col loop */ + while (col > 0) + { + /* point to last row in matrix A */ + pInA = pSrcA->pData + (numRowsA-1) * numColsA; +#if __RISCV_XLEN == 64 + sum64 = 0; +#endif + /* Set variable sum, that acts as accumulator, to zero */ + sum = 0; + + /* Compute 4 columns at once */ + colCnt = numColsA >> 2U; + + /* matrix multiplication */ + while (colCnt > 0U) + { +#if __RISCV_XLEN == 64 + inA164 = read_q15x4_ia ((q15_t **) &pInA); + inB164 = read_q15x4_ia ((q15_t **) &pInB); + + sum64 = __RV_KMADA(sum64, inA164, inB164); +#else + inA1 = read_q15x2_ia ((q15_t **) &pInA); + inA2 = read_q15x2_ia ((q15_t **) &pInA); + inB1 = read_q15x2_ia ((q15_t **) &pInB); + inB2 = read_q15x2_ia ((q15_t **) &pInB); + + sum = __RV_KMADA(sum, inA1, inB1); + sum = __RV_KMADA(sum, inA2, inB2); +#endif /* __RISCV_XLEN == 64 */ + /* Decrement loop counter */ + colCnt--; + } +#if __RISCV_XLEN == 64 + sum = (q31_t) ((q31_t) (sum64 & 0xffffffff)) + ((q31_t) ((sum64 & 0xffffffff00000000)>> 32)); +#endif /* __RISCV_XLEN == 64 */ + colCnt = numColsA % 4U; + while (colCnt > 0U) { + sum += (q31_t) (*pInA++) * (*pInB++); + + colCnt--; + } + + /* Store result in destination buffer */ + *px++ = (q15_t) (sum >> 15); + + /* Decrement column loop counter */ + col--; + } + } + +#endif /* #if defined (RISCV_MATH_DSP) */ + /* Set status as RISCV_MATH_SUCCESS */ + status = RISCV_MATH_SUCCESS; + } +#endif + + /* Return to application */ + return (status); +} + +/** + @} end of MatrixMult group + */ diff --git a/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_mult_fast_q31.c b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_mult_fast_q31.c new file mode 100644 index 00000000..e799d0f5 --- /dev/null +++ b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_mult_fast_q31.c @@ -0,0 +1,585 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_mat_mult_fast_q31.c + * Description: Q31 matrix multiplication (fast variant) + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixMult + @{ + */ + +/** + @brief Q31 matrix multiplication (fast variant). + @param[in] pSrcA points to the first input matrix structure + @param[in] pSrcB points to the second input matrix structure + @param[out] pDst points to output matrix structure + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_SIZE_MISMATCH : Matrix size check failed + + @par Scaling and Overflow Behavior + The difference between the function \ref riscv_mat_mult_q31() and this fast variant is that + the fast variant use a 32-bit rather than a 64-bit accumulator. + The result of each 1.31 x 1.31 multiplication is truncated to + 2.30 format. These intermediate results are accumulated in a 32-bit register in 2.30 + format. Finally, the accumulator is saturated and converted to a 1.31 result. + @par + The fast version has the same overflow behavior as the standard version but provides + less precision since it discards the low 32 bits of each multiplication result. + In order to avoid overflows completely the input signals must be scaled down. + Scale down one of the input matrices by log2(numColsA) bits to avoid overflows, + as a total of numColsA additions are computed internally for each output element. + @remark + Refer to \ref riscv_mat_mult_q31() for a slower implementation of this function + which uses 64-bit accumulation to provide higher precision. + */ + +riscv_status riscv_mat_mult_fast_q31( + const riscv_matrix_instance_q31 * pSrcA, + const riscv_matrix_instance_q31 * pSrcB, + riscv_matrix_instance_q31 * pDst) +{ + q31_t *pInA = pSrcA->pData; /* Input data matrix pointer A */ + q31_t *pInB = pSrcB->pData; /* Input data matrix pointer B */ + q31_t *pInA2; + q31_t *px; /* Temporary output data matrix pointer */ + q31_t *px2; + q31_t sum1, sum2, sum3, sum4; /* Accumulator */ + q31_t inA1, inA2, inB1, inB2; + uint16_t numRowsA = pSrcA->numRows; /* Number of rows of input matrix A */ + uint16_t numColsB = pSrcB->numCols; /* Number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* Number of columns of input matrix A */ + uint32_t col, i = 0U, j, row = numRowsA, colCnt; /* Loop counters */ + riscv_status status; /* Status of matrix multiplication */ + +#if defined(RISCV_VECTOR) + uint16_t blkCnt; //number of matrix columns numColsA = numrowB + size_t l; // max_l is the maximum column elements at a time + ptrdiff_t bstride = 4; // 32bit/8bit = 4 + uint16_t colnum,rownum; // How many rowumns and rownum are controlled + vint32m4_t v_inA1, v_inA2, v_inB1, v_inB2; + vint32m4_t v_sum1, v_sum2, v_sum3, v_sum4; + vint16m8_t vReal, vImag; + l = vsetvl_e32m1(1); + vint32m1_t vtemp = vsub_vv_i32m1(vtemp, vtemp, l); + +#ifdef RISCV_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as RISCV_MATH_SIZE_MISMATCH */ + status = RISCV_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef RISCV_MATH_MATRIX_CHECK */ + + { + px = pDst->pData; + + row = row >> 1U; + px2 = px + numColsB; + + /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */ + /* row loop */ + while (row > 0U) + { + /* For every row wise process, column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, pIn2 pointer is set to starting address of pSrcB data */ + pInB = pSrcB->pData; + + j = 0U; + + col = col >> 1U; + + /* column loop */ + while (col > 0U) + { + /* Set the variable sum, that acts as accumulator, to zero */ + // sum1 = 0; + // sum2 = 0; + // sum3 = 0; + // sum4 = 0; + + /* Initiate data pointers */ + pInA = pSrcA->pData + i; + pInB = pSrcB->pData + j; + pInA2 = pInA + numColsA; + + colCnt = numColsA; + + /* matrix multiplication */ + blkCnt = numColsA; + bstride = numColsB*4; + l = vsetvl_e32m4(blkCnt); + v_sum1 = vsub_vv_i32m4(v_sum1,v_sum1, l); + v_sum2 = vsub_vv_i32m4(v_sum2,v_sum2, l); + v_sum3 = vsub_vv_i32m4(v_sum3,v_sum3, l); + v_sum4 = vsub_vv_i32m4(v_sum4,v_sum4, l); + for (; (l = vsetvl_e32m4(blkCnt)) > 0; blkCnt -= l) //Multiply a row by a column + { + v_inA1 = vle32_v_i32m4(pInA, l); + v_inA2 = vle32_v_i32m4(pInA2, l); + pInA += l; + pInA2 += l; + v_inB1 = vlse32_v_i32m4(pInB,bstride, l); + v_inB2 = vlse32_v_i32m4(pInB+1,bstride, l); + pInB += l*numColsB; + + v_sum1 = vadd_vv_i32m4(v_sum1, vsmul_vv_i32m4(v_inA1, v_inB1, l), l); + v_sum2 = vadd_vv_i32m4(v_sum2, vsmul_vv_i32m4(v_inA1, v_inB2, l), l); + v_sum3 = vadd_vv_i32m4(v_sum3, vsmul_vv_i32m4(v_inA2, v_inB1, l), l); + v_sum4 = vadd_vv_i32m4(v_sum4, vsmul_vv_i32m4(v_inA2, v_inB2, l), l); + } + l = vsetvl_e32m4(numColsA); + sum1 = vmv_x_s_i32m1_i32 (vredsum_vs_i32m4_i32m1(vtemp, v_sum1, vtemp, l)); + l = vsetvl_e32m4(numColsA); + sum2 = vmv_x_s_i32m1_i32 (vredsum_vs_i32m4_i32m1(vtemp, v_sum2, vtemp, l)); + l = vsetvl_e32m4(numColsA); + sum3 = vmv_x_s_i32m1_i32 (vredsum_vs_i32m4_i32m1(vtemp, v_sum3, vtemp, l)); + l = vsetvl_e32m4(numColsA); + sum4 = vmv_x_s_i32m1_i32 (vredsum_vs_i32m4_i32m1(vtemp, v_sum4, vtemp, l)); + + /* Convert the result from 2.30 to 1.31 format and store in destination buffer */ + *px++ = sum1 << 1; + *px++ = sum2 << 1; + *px2++ = sum3 << 1; + *px2++ = sum4 << 1; + + j += 2; + + /* Decrement column loop counter */ + col--; + } + + i = i + (numColsA << 1U); + px = px2 + (numColsB & 1U); + px2 = px + numColsB; + + /* Decrement row loop counter */ + row--; + } + + /* Compute any remaining odd row/column below */ + + /* Compute remaining output column */ + if (numColsB & 1U) { + + /* Avoid redundant computation of last element */ + row = numRowsA & (~1U); + + /* Point to remaining unfilled column in output matrix */ + px = pDst->pData + numColsB-1; + pInA = pSrcA->pData; + + /* row loop */ + while (row > 0) + { + + /* point to last column in matrix B */ + pInB = pSrcB->pData + numColsB-1; + + /* Set variable sum1, that acts as accumulator, to zero */ + sum1 = 0; + + /* Initialize colCnt with number of columns */ + colCnt = numColsA; + + blkCnt = numColsA; + bstride = numColsB*4; + l = vsetvl_e32m4(blkCnt); + v_sum1 = vsub_vv_i32m4(v_sum1,v_sum1, l); + for (; (l = vsetvl_e32m4(blkCnt)) > 0; blkCnt -= l) //Multiply a row by a column + { + v_inA1 = vle32_v_i32m4(pInA, l); + pInA += l; + v_inB1 = vlse32_v_i32m4(pInB,bstride, l); + pInB += l*numColsB; + + v_sum1 = vadd_vv_i32m4(v_sum1, vsmul_vv_i32m4(v_inA1, v_inB1, l), l); + } + l = vsetvl_e32m4(numColsA); + sum1 = vmv_x_s_i32m1_i32 (vredsum_vs_i32m4_i32m1(vtemp, v_sum1, vtemp, l)); + + /* Convert the result from 2.30 to 1.31 format and store in destination buffer */ + *px = sum1 << 1; + px += numColsB; + + /* Decrement row loop counter */ + row--; + } + } + + /* Compute remaining output row */ + if (numRowsA & 1U) { + + /* point to last row in output matrix */ + px = pDst->pData + (numColsB) * (numRowsA-1); + + col = numColsB; + i = 0U; + + /* col loop */ + while (col > 0) + { + + /* point to last row in matrix A */ + pInA = pSrcA->pData + (numRowsA-1) * numColsA; + pInB = pSrcB->pData + i; + + /* Set variable sum1, that acts as accumulator, to zero */ + sum1 = 0; + + /* Initialize colCnt with number of columns */ + colCnt = numColsA; + + blkCnt = numColsA; + bstride = numColsB*4; + l = vsetvl_e32m4(blkCnt); + v_sum1 = vsub_vv_i32m4(v_sum1,v_sum1, l); + for (; (l = vsetvl_e32m4(blkCnt)) > 0; blkCnt -= l) //Multiply a row by a column + { + v_inA1 = vle32_v_i32m4(pInA, l); + pInA += l; + v_inB1 = vlse32_v_i32m4(pInB,bstride, l); + pInB += l*numColsB; + + v_sum1 = vadd_vv_i32m4(v_sum1, vsmul_vv_i32m4(v_inA1, v_inB1, l), l); + } + l = vsetvl_e32m4(numColsA); + sum1 = vmv_x_s_i32m1_i32 (vredsum_vs_i32m4_i32m1(vtemp, v_sum1, vtemp, l)); + + /* Saturate and store the result in the destination buffer */ + *px++ = sum1 << 1; + i++; + + /* Decrement col loop counter */ + col--; + } + } + +#else +#ifdef RISCV_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as RISCV_MATH_SIZE_MISMATCH */ + status = RISCV_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef RISCV_MATH_MATRIX_CHECK */ + + { + px = pDst->pData; + + row = row >> 1U; + px2 = px + numColsB; + + /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */ + /* row loop */ + while (row > 0U) + { + /* For every row wise process, column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, pIn2 pointer is set to starting address of pSrcB data */ + pInB = pSrcB->pData; + + j = 0U; + + col = col >> 1U; + + /* column loop */ + while (col > 0U) + { + /* Set the variable sum, that acts as accumulator, to zero */ + sum1 = 0; + sum2 = 0; + sum3 = 0; + sum4 = 0; + + /* Initiate data pointers */ + pInA = pSrcA->pData + i; + pInB = pSrcB->pData + j; + pInA2 = pInA + numColsA; + + colCnt = numColsA; + + /* matrix multiplication */ + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + + inA1 = *pInA++; + inB1 = pInB[0]; + inA2 = *pInA2++; + inB2 = pInB[1]; + pInB += numColsB; + +#if defined (RISCV_MATH_DSP) + sum1 = __SMMLA(inA1, inB1, sum1); + sum2 = __SMMLA(inA1, inB2, sum2); + sum3 = __SMMLA(inA2, inB1, sum3); + sum4 = __SMMLA(inA2, inB2, sum4); +#else + sum1 = (q31_t) ((((q63_t) sum1 << 32) + ((q63_t) inA1 * inB1)) >> 32); + sum2 = (q31_t) ((((q63_t) sum2 << 32) + ((q63_t) inA1 * inB2)) >> 32); + sum3 = (q31_t) ((((q63_t) sum3 << 32) + ((q63_t) inA2 * inB1)) >> 32); + sum4 = (q31_t) ((((q63_t) sum4 << 32) + ((q63_t) inA2 * inB2)) >> 32); +#endif + + /* Decrement loop counter */ + colCnt--; + } + + /* Convert the result from 2.30 to 1.31 format and store in destination buffer */ + *px++ = sum1 << 1; + *px++ = sum2 << 1; + *px2++ = sum3 << 1; + *px2++ = sum4 << 1; + + j += 2; + + /* Decrement column loop counter */ + col--; + } + + i = i + (numColsA << 1U); + px = px2 + (numColsB & 1U); + px2 = px + numColsB; + + /* Decrement row loop counter */ + row--; + } + + /* Compute any remaining odd row/column below */ + + /* Compute remaining output column */ + if (numColsB & 1U) { + + /* Avoid redundant computation of last element */ + row = numRowsA & (~1U); + + /* Point to remaining unfilled column in output matrix */ + px = pDst->pData + numColsB-1; + pInA = pSrcA->pData; + + /* row loop */ + while (row > 0) + { + + /* point to last column in matrix B */ + pInB = pSrcB->pData + numColsB-1; + + /* Set variable sum1, that acts as accumulator, to zero */ + sum1 = 0; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 columns at a time. */ + colCnt = numColsA >> 2U; + + /* matrix multiplication */ + while (colCnt > 0U) + { +#if defined (RISCV_MATH_DSP) + sum1 = __SMMLA(*pInA++, *pInB, sum1); +#else + sum1 = (q31_t) ((((q63_t) sum1 << 32) + ((q63_t) *pInA++ * *pInB)) >> 32); +#endif + pInB += numColsB; + +#if defined (RISCV_MATH_DSP) + sum1 = __SMMLA(*pInA++, *pInB, sum1); +#else + sum1 = (q31_t) ((((q63_t) sum1 << 32) + ((q63_t) *pInA++ * *pInB)) >> 32); +#endif + pInB += numColsB; + +#if defined (RISCV_MATH_DSP) + sum1 = __SMMLA(*pInA++, *pInB, sum1); +#else + sum1 = (q31_t) ((((q63_t) sum1 << 32) + ((q63_t) *pInA++ * *pInB)) >> 32); +#endif + pInB += numColsB; + +#if defined (RISCV_MATH_DSP) + sum1 = __SMMLA(*pInA++, *pInB, sum1); +#else + sum1 = (q31_t) ((((q63_t) sum1 << 32) + ((q63_t) *pInA++ * *pInB)) >> 32); +#endif + pInB += numColsB; + + /* Decrement loop counter */ + colCnt--; + } + + /* Loop unrolling: Compute remaining column */ + colCnt = numColsA % 4U; + +#else + + /* Initialize colCnt with number of columns */ + colCnt = numColsA; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (colCnt > 0U) { +#if defined (RISCV_MATH_DSP) + sum1 = __SMMLA(*pInA++, *pInB, sum1); +#else + sum1 = (q31_t) ((((q63_t) sum1 << 32) + ((q63_t) *pInA++ * *pInB)) >> 32); +#endif + pInB += numColsB; + + colCnt--; + } + + /* Convert the result from 2.30 to 1.31 format and store in destination buffer */ + *px = sum1 << 1; + px += numColsB; + + /* Decrement row loop counter */ + row--; + } + } + + /* Compute remaining output row */ + if (numRowsA & 1U) { + + /* point to last row in output matrix */ + px = pDst->pData + (numColsB) * (numRowsA-1); + + col = numColsB; + i = 0U; + + /* col loop */ + while (col > 0) + { + + /* point to last row in matrix A */ + pInA = pSrcA->pData + (numRowsA-1) * numColsA; + pInB = pSrcB->pData + i; + + /* Set variable sum1, that acts as accumulator, to zero */ + sum1 = 0; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 columns at a time. */ + colCnt = numColsA >> 2U; + + /* matrix multiplication */ + while (colCnt > 0U) + { + inA1 = *pInA++; + inA2 = *pInA++; + inB1 = *pInB; + pInB += numColsB; + inB2 = *pInB; + pInB += numColsB; +#if defined (RISCV_MATH_DSP) + sum1 = __SMMLA(inA1, inB1, sum1); + sum1 = __SMMLA(inA2, inB2, sum1); +#else + sum1 = (q31_t) ((((q63_t) sum1 << 32) + ((q63_t) inA1 * inB1)) >> 32); + sum1 = (q31_t) ((((q63_t) sum1 << 32) + ((q63_t) inA2 * inB2)) >> 32); +#endif + + inA1 = *pInA++; + inA2 = *pInA++; + inB1 = *pInB; + pInB += numColsB; + inB2 = *pInB; + pInB += numColsB; +#if defined (RISCV_MATH_DSP) + sum1 = __SMMLA(inA1, inB1, sum1); + sum1 = __SMMLA(inA2, inB2, sum1); +#else + sum1 = (q31_t) ((((q63_t) sum1 << 32) + ((q63_t) inA1 * inB1)) >> 32); + sum1 = (q31_t) ((((q63_t) sum1 << 32) + ((q63_t) inA2 * inB2)) >> 32); +#endif + + /* Decrement loop counter */ + colCnt--; + } + + /* Loop unrolling: Compute remaining column */ + colCnt = numColsA % 4U; + +#else + + /* Initialize colCnt with number of columns */ + colCnt = numColsA; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (colCnt > 0U) { +#if defined (RISCV_MATH_DSP) + sum1 = __SMMLA(*pInA++, *pInB, sum1); +#else + sum1 = (q31_t) ((((q63_t) sum1 << 32) + ((q63_t) *pInA++ * *pInB)) >> 32); +#endif + pInB += numColsB; + + colCnt--; + } + + /* Saturate and store the result in the destination buffer */ + *px++ = sum1 << 1; + i++; + + /* Decrement col loop counter */ + col--; + } + } +#endif + /* Set status as RISCV_MATH_SUCCESS */ + status = RISCV_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +/** + @} end of MatrixMult group + */ diff --git a/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_mult_q15.c b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_mult_q15.c new file mode 100644 index 00000000..37bc71ad --- /dev/null +++ b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_mult_q15.c @@ -0,0 +1,405 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_mat_mult_q15.c + * Description: Q15 matrix multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixMult + @{ + */ + +/** + @brief Q15 matrix multiplication. + @param[in] pSrcA points to the first input matrix structure + @param[in] pSrcB points to the second input matrix structure + @param[out] pDst points to output matrix structure + @param[in] pState points to the array for storing intermediate results (Unused) + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_SIZE_MISMATCH : Matrix size check failed + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. The inputs to the + multiplications are in 1.15 format and multiplications yield a 2.30 result. + The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + This approach provides 33 guard bits and there is no risk of overflow. + The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits + and then saturated to 1.15 format. + @par + Refer to \ref riscv_mat_mult_fast_q15() for a faster but less precise version of this function. + */ +riscv_status riscv_mat_mult_q15( + const riscv_matrix_instance_q15 * pSrcA, + const riscv_matrix_instance_q15 * pSrcB, + riscv_matrix_instance_q15 * pDst, + q15_t * pState) +{ + q63_t sum; /* Accumulator */ + +#if defined (RISCV_MATH_DSP) && !defined (RISCV_VECTOR) + + q15_t *pSrcBT = pState; /* Input data matrix pointer for transpose */ + q15_t *pInA = pSrcA->pData; /* Input data matrix pointer A of Q15 type */ + q15_t *pInB = pSrcB->pData; /* Input data matrix pointer B of Q15 type */ + q15_t *px; /* Temporary output data matrix pointer */ + uint16_t numRowsA = pSrcA->numRows; /* Number of rows of input matrix A */ + uint16_t numColsB = pSrcB->numCols; /* Number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* Number of columns of input matrix A */ + uint16_t numRowsB = pSrcB->numRows; /* Number of rows of input matrix B */ + uint32_t col, i = 0U, row = numRowsB, colCnt; /* Loop counters */ + riscv_status status; /* Status of matrix multiplication */ + q31_t in; /* Temporary variable to hold the input value */ + q31_t inA1, inB1, inA2, inB2; +#if __RISCV_XLEN == 64 + q63_t inA164, inB164, sum64; +#else +#endif /* __RISCV_XLEN == 64 */ + +#ifdef RISCV_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as RISCV_MATH_SIZE_MISMATCH */ + status = RISCV_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef RISCV_MATH_MATRIX_CHECK */ + + { + /* Matrix transpose */ + do + { + /* The pointer px is set to starting address of column being processed */ + px = pSrcBT + i; + + /* Apply loop unrolling and exchange columns with row elements */ + col = numColsB >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (col > 0U) + { + /* Read two elements from row */ + in = read_q15x2_ia ((q15_t **) &pInB); + + /* Unpack and store one element in destination */ + *px = (q15_t) in; + + /* Update pointer px to point to next row of transposed matrix */ + px += numRowsB; + + /* Unpack and store second element in destination */ + *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16); + + /* Update pointer px to point to next row of transposed matrix */ + px += numRowsB; + + /* Read two elements from row */ + in = read_q15x2_ia ((q15_t **) &pInB); + + /* Unpack and store one element in destination */ + *px = (q15_t) in; + px += numRowsB; + + *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16); + px += numRowsB; + + /* Decrement column loop counter */ + col--; + } + + /* If the columns of pSrcB is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + col = numColsB % 0x4U; + + while (col > 0U) + { + /* Read and store input element in destination */ + *px = *pInB++; + + /* Update pointer px to point to next row of transposed matrix */ + px += numRowsB; + + /* Decrement column loop counter */ + col--; + } + + i++; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); + + /* Reset variables for usage in following multiplication process */ + row = numRowsA; + i = 0U; + px = pDst->pData; + + /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */ + /* row loop */ + do + { + /* For every row wise process, column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, pIn2 pointer is set to starting address of transposed pSrcB data */ + pInB = pSrcBT; + + /* column loop */ + do + { + /* Set variable sum, that acts as accumulator, to zero */ + sum = 0; + + /* Initiate pointer pInA to point to starting address of column being processed */ + pInA = pSrcA->pData + i; + + /* Apply loop unrolling and compute 2 MACs simultaneously. */ + colCnt = numColsA >> 2U; + + /* matrix multiplication */ + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ +#if __RISCV_XLEN == 64 + inA164 = read_q15x4_ia ((q15_t **) &pInA); + inB164 = read_q15x4_ia ((q15_t **) &pInB); + /* Multiply and Accumlates */ + sum = __RV_SMALDA(sum, inA164, inB164); + // sum = (q31_t)(sum64 + (sum64 >> 32)); + +#else + /* read real and imag values from pSrcA and pSrcB buffer */ + inA1 = read_q15x2_ia ((q15_t **) &pInA); + inB1 = read_q15x2_ia ((q15_t **) &pInB); + + inA2 = read_q15x2_ia ((q15_t **) &pInA); + inB2 = read_q15x2_ia ((q15_t **) &pInB); + + /* Multiply and Accumlates */ + sum = __RV_SMALDA(sum, inA1, inB1); + sum = __RV_SMALDA(sum, inA2, inB2); +#endif /* __RISCV_XLEN == 64 */ + + /* Decrement loop counter */ + colCnt--; + } + + /* process remaining column samples */ + colCnt = numColsA % 0x4U; + + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + sum += *pInA++ * *pInB++; + + /* Decrement loop counter */ + colCnt--; + } + + /* Saturate and store result in destination buffer */ + *px = (q15_t) (__SSAT((sum >> 15), 16)); + px++; + + /* Decrement column loop counter */ + col--; + + } while (col > 0U); + + i = i + numColsA; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); + /* Set status as RISCV_MATH_SUCCESS */ + status = RISCV_MATH_SUCCESS; + } +#else /* #if defined (RISCV_MATH_DSP) */ + + q15_t *pIn1 = pSrcA->pData; /* Input data matrix pointer A */ + q15_t *pIn2 = pSrcB->pData; /* Input data matrix pointer B */ + q15_t *pInA = pSrcA->pData; /* Input data matrix pointer A of Q15 type */ + q15_t *pInB = pSrcB->pData; /* Input data matrix pointer B of Q15 type */ + q15_t *pOut = pDst->pData; /* Output data matrix pointer */ + q15_t *px; /* Temporary output data matrix pointer */ + uint16_t numColsB = pSrcB->numCols; /* Number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* Number of columns of input matrix A */ + uint16_t numRowsA = pSrcA->numRows; /* Number of rows of input matrix A */ + uint32_t col, i = 0U, row = numRowsA, colCnt; /* Loop counters */ + riscv_status status; /* Status of matrix multiplication */ + (void)pState; + +#ifdef RISCV_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as RISCV_MATH_SIZE_MISMATCH */ + status = RISCV_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef RISCV_MATH_MATRIX_CHECK */ +#if defined(RISCV_VECTOR) + uint16_t blkCnt = numColsA; //number of matrix columns numColsA = numrowB + size_t l,max_l; // max_l is the maximum column elements at a time + ptrdiff_t bstride = 2; // 16bit/8bit = 2 + ptrdiff_t col_diff = bstride * numColsB; //Control the column width of the span + uint16_t colnum,rownum; // How many rowumns and rownum are controlled + vint16m4_t v_inA,v_inB; + vint32m8_t vmul; + l = vsetvl_e32m1(1); + vint64m1_t vsum = vmv_s_x_i64m1(vsum, 0, l); + // max_l = vsetvl_e16m4(32); + px = pOut; +for(rownum = 0;rownum < numRowsA; rownum++) + { + pIn1 = pInA; //backup pointer position + for(colnum = 0;colnum < numColsB; colnum++) + { + blkCnt = numColsA; + pIn2 = pInB; //backup pointer position + sum = 0; + l = vsetvl_e16m1(1); + vsum = vmv_s_x_i64m1(vsum, 0, l); + for (; (l = vsetvl_e16m4(blkCnt)) > 0; blkCnt -= l) //Multiply a row by a column + { + v_inA = vle16_v_i16m4(pInA, l); + v_inB = vlse16_v_i16m4(pInB, col_diff, l); + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + /* Perform multiply-accumulates */ + vmul = vwmul_vv_i32m8(v_inA, v_inB, l); + vsum = vwredsum_vs_i32m8_i64m1(vsum, vmul, vsum, l); + //sum = vmv_x_s_i64m1_i64 (vsum); + //*px = (q15_t) __SSAT((sum >> 15), 16); + //printf("l=%d\t",l); + // if(l == max_l) + // { + pInA = pInA+l; //Pointer to the first element of the next line + pInB = pInB+l*numColsB; + // } + } + sum = vmv_x_s_i64m1_i64 (vsum); + *px = (q15_t) __SSAT((sum >> 15), 16); + px++; + pInA = pIn1; + pInB = pIn2;pInB = pInB+1; //Pointer to the first element of the next column for matrix BS + //printf("px=%d\n",px); + } + pInB = pSrcB->pData; + pInA = pIn1;pInA = pInA+numColsA; //Pointer to the first element of the next row for matrix A + } + /* Set status as RISCV_MATH_SUCCESS */ + status = RISCV_MATH_SUCCESS; +#else + { + /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */ + /* row loop */ + do + { + /* Output pointer is set to starting address of the row being processed */ + px = pOut + i; + + /* For every row wise process, column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, pIn2 pointer is set to starting address of pSrcB data */ + pIn2 = pSrcB->pData; + + /* column loop */ + do + { + /* Set the variable sum, that acts as accumulator, to zero */ + sum = 0; + + /* Initiate pointer pIn1 to point to starting address of pSrcA */ + pIn1 = pInA; + + /* Matrix A columns number of MAC operations are to be performed */ + colCnt = numColsA; + + /* matrix multiplication */ + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + + /* Perform multiply-accumulates */ + sum += (q31_t) * pIn1++ * *pIn2; + pIn2 += numColsB; + + /* Decrement loop counter */ + colCnt--; + } + + /* Convert result from 34.30 to 1.15 format and store saturated value in destination buffer */ + + /* Saturate and store result in destination buffer */ + *px++ = (q15_t) __SSAT((sum >> 15), 16); + + /* Decrement column loop counter */ + col--; + + /* Update pointer pIn2 to point to starting address of next column */ + pIn2 = pInB + (numColsB - col); + + } while (col > 0U); + + /* Update pointer pSrcA to point to starting address of next row */ + i = i + numColsB; + pInA = pInA + numColsA; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); + + /* Set status as RISCV_MATH_SUCCESS */ + status = RISCV_MATH_SUCCESS; + } +#endif /* #if defined (RISCV_MATH_DSP) */ +#endif /*defined(RISCV_VECTOR)*/ + /* Return to application */ + return (status); +} + +/** + @} end of MatrixMult group + */ diff --git a/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_mult_q31.c b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_mult_q31.c new file mode 100644 index 00000000..d7a3ad82 --- /dev/null +++ b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_mult_q31.c @@ -0,0 +1,254 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_mat_mult_q31.c + * Description: Q31 matrix multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixMult + @{ + */ + +/** + @brief Q31 matrix multiplication. + @param[in] pSrcA points to the first input matrix structure + @param[in] pSrcB points to the second input matrix structure + @param[out] pDst points to output matrix structure + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_SIZE_MISMATCH : Matrix size check failed + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The accumulator has a 2.62 format and maintains full precision of the intermediate + multiplication results but provides only a single guard bit. There is no saturation + on intermediate additions. Thus, if the accumulator overflows it wraps around and + distorts the result. The input signals should be scaled down to avoid intermediate + overflows. The input is thus scaled down by log2(numColsA) bits + to avoid overflows, as a total of numColsA additions are performed internally. + The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result. + @remark + Refer to \ref riscv_mat_mult_fast_q31() for a faster but less precise implementation of this function. + */ +riscv_status riscv_mat_mult_q31( + const riscv_matrix_instance_q31 * pSrcA, + const riscv_matrix_instance_q31 * pSrcB, + riscv_matrix_instance_q31 * pDst) +{ + q31_t *pIn1 = pSrcA->pData; /* Input data matrix pointer A */ + q31_t *pIn2 = pSrcB->pData; /* Input data matrix pointer B */ + q31_t *pInA = pSrcA->pData; /* Input data matrix pointer A */ + q31_t *pInB = pSrcB->pData; /* Input data matrix pointer B */ + q31_t *pOut = pDst->pData; /* Output data matrix pointer */ + q31_t *px; /* Temporary output data matrix pointer */ + q63_t sum; /* Accumulator */ + uint16_t numRowsA = pSrcA->numRows; /* Number of rows of input matrix A */ + uint16_t numColsB = pSrcB->numCols; /* Number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* Number of columns of input matrix A */ + uint32_t col, i = 0U, row = numRowsA, colCnt; /* Loop counters */ + riscv_status status; /* Status of matrix multiplication */ +#if __RISCV_XLEN == 64 + q63_t temp164, temp264; /* Accumulator */ +#endif /* __RISCV_XLEN == 64 */ +#ifdef RISCV_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as RISCV_MATH_SIZE_MISMATCH */ + status = RISCV_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef RISCV_MATH_MATRIX_CHECK */ + +#if defined(RISCV_VECTOR) + uint16_t blkCnt = numColsA; //number of matrix columns numColsA = numrowB + size_t l,max_l; // max_l is the maximum column elements at a time + ptrdiff_t bstride = 4; // 32bit/8bit = 4 + ptrdiff_t col_diff = bstride * numColsB; //Control the column width of the span + uint16_t colnum,rownum; // How many rowumns and rownum are controlled + vint32m4_t v_inA,v_inB; + vint64m8_t vmul; + l = vsetvl_e32m1(1); + vint64m1_t vsum = vmv_s_x_i64m1(vsum, 0, l); + // max_l = vsetvl_e32m4(32); + px = pOut; +for(rownum = 0;rownum < numRowsA; rownum++) + { + pIn1 = pInA; //backup pointer position + for(colnum = 0;colnum < numColsB; colnum++) + { + blkCnt = numColsA; + pIn2 = pInB; //backup pointer position + sum = 0; + l = vsetvl_e32m1(1); + vsum = vmv_s_x_i64m1(vsum, 0, l); + for (; (l = vsetvl_e32m4(blkCnt)) > 0; blkCnt -= l) //Multiply a row by a column + { + v_inA = vle32_v_i32m4(pInA, l); + v_inB = vlse32_v_i32m4(pInB, col_diff, l); + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + /* Perform multiply-accumulates */ + vmul = vwmul_vv_i64m8(v_inA, v_inB, l); + vsum = vredsum_vs_i64m8_i64m1(vsum, vmul, vsum, l); + //vsum = vmin_vx_i64m1(vmax_vx_i64m1(vredsum_vs_i64m8_i64m1(vsum, vmul, vsum) , 0xffffffff80000000),0x7fffffff); + //sum = vmv_x_s_i64m1_i64 (vsum); + // if(l == max_l) + // { + pInA = pInA+l; //Pointer to the first element of the next line + pInB = pInB+l*numColsB; + // } + } + sum = vmv_x_s_i64m1_i64 (vsum); + *px = (q31_t) (sum >> 31); + px++; + pInA = pIn1; + pInB = pIn2;pInB = pInB+1; //Pointer to the first element of the next column for matrix BS + //printf("px=%d\n",px); + } + pInB = pSrcB->pData; + pInA = pIn1;pInA = pInA+numColsA; //Pointer to the first element of the next row for matrix A + } + /* Set status as RISCV_MATH_SUCCESS */ + status = RISCV_MATH_SUCCESS; +#else + { + /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */ + /* row loop */ + do + { + /* Output pointer is set to starting address of row being processed */ + px = pOut + i; + + /* For every row wise process, column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, pIn2 pointer is set to starting address of pSrcB data */ + pIn2 = pSrcB->pData; + + /* column loop */ + do + { + /* Set the variable sum, that acts as accumulator, to zero */ + sum = 0; + + /* Initialize pointer pIn1 to point to starting address of column being processed */ + pIn1 = pInA; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 MACs at a time. */ + colCnt = numColsA >> 2U; + + /* matrix multiplication */ + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ +#if __RISCV_XLEN == 64 + temp164 = read_q31x2_ia ((q31_t **) &pIn1); + temp264 = ((q63_t) *pIn2) | ((q63_t) *pIn2 << 32); + sum = __RV_KMADA32(sum, temp164, temp264); +#else + /* Perform the multiply-accumulates */ + sum += (q63_t) *pIn1++ * *pIn2; + pIn2 += numColsB; + + sum += (q63_t) *pIn1++ * *pIn2; + pIn2 += numColsB; + + sum += (q63_t) *pIn1++ * *pIn2; + pIn2 += numColsB; + + sum += (q63_t) *pIn1++ * *pIn2; + pIn2 += numColsB; +#endif /* __RISCV_XLEN == 64 */ + + /* Decrement loop counter */ + colCnt--; + } + + /* Loop unrolling: Compute remaining MACs */ + colCnt = numColsA % 0x4U; + +#else + + /* Initialize cntCnt with number of columns */ + colCnt = numColsA; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + + /* Perform the multiply-accumulates */ + sum += (q63_t) *pIn1++ * *pIn2; + pIn2 += numColsB; + + /* Decrement loop counter */ + colCnt--; + } + + /* Convert result from 2.62 to 1.31 format and store in destination buffer */ + *px++ = (q31_t) (sum >> 31); + + /* Decrement column loop counter */ + col--; + + /* Update pointer pIn2 to point to starting address of next column */ + pIn2 = pInB + (numColsB - col); + + } while (col > 0U); + + /* Update pointer pInA to point to starting address of next row */ + i = i + numColsB; + pInA = pInA + numColsA; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); + + /* Set status as RISCV_MATH_SUCCESS */ + status = RISCV_MATH_SUCCESS; + } +#endif /*defined(RISCV_VECTOR)*/ + /* Return to application */ + return (status); +} + +/** + @} end of MatrixMult group + */ diff --git a/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_mult_q7.c b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_mult_q7.c new file mode 100644 index 00000000..b8d1057d --- /dev/null +++ b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_mult_q7.c @@ -0,0 +1,157 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_mat_mult_q7.c + * Description: Q15 matrix multiplication + * + * $Date: 23 April 2021 + * + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixMult + @{ + */ + +/** + * @brief Q7 matrix multiplication + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @param[in] *pState points to the array for storing intermediate results (Unused in some versions) + * @return The function returns either + * RISCV_MATH_SIZE_MISMATCH or RISCV_MATH_SUCCESS based on the outcome of size checking. + * + * @details + * Scaling and Overflow Behavior: + * + * \par + * The function is implemented using a 32-bit internal accumulator saturated to 1.7 format. + * + * + */ +riscv_status riscv_mat_mult_q7(const riscv_matrix_instance_q7 *pSrcA, const riscv_matrix_instance_q7 *pSrcB, riscv_matrix_instance_q7 *pDst, q7_t *pState) +{ + q31_t sum; /* accumulator */ + q7_t *pIn1 = pSrcA->pData; /* input data matrix pointer A */ + q7_t *pIn2 = pSrcB->pData; /* input data matrix pointer B */ + q7_t *pInA = pSrcA->pData; /* input data matrix pointer A of Q7 type */ + q7_t *pInB = pSrcB->pData; /* input data matrix pointer B of Q7 type */ + q7_t *pOut = pDst->pData; /* output data matrix pointer */ + q7_t *px; /* Temporary output data matrix pointer */ + uint16_t numColsB = pSrcB->numCols; /* number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* number of columns of input matrix A */ + uint16_t numRowsA = pSrcA->numRows; /* number of rows of input matrix A */ + uint16_t col, i = 0U, row = numRowsA, colCnt; /* loop counters */ + riscv_status status; /* status of matrix multiplication */ + + (void)pState; + +#ifdef RISCV_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as RISCV_MATH_SIZE_MISMATCH */ + status = RISCV_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef RISCV_MATH_MATRIX_CHECK */ + + { + /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */ + /* row loop */ + do { + /* Output pointer is set to starting address of the row being processed */ + px = pOut + i; + + /* For every row wise process, the column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, the pIn2 pointer is set + ** to the starting address of the pSrcB data */ + pIn2 = pSrcB->pData; + + /* column loop */ + do { + /* Set the variable sum, that acts as accumulator, to zero */ + sum = 0; + + /* Initiate the pointer pIn1 to point to the starting address of pSrcA */ + pIn1 = pInA; + + /* Matrix A columns number of MAC operations are to be performed */ + colCnt = numColsA; + + /* matrix multiplication */ + while (colCnt > 0U) { + /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */ + /* Perform the multiply-accumulates */ + sum += (q31_t)*pIn1++ * *pIn2; + pIn2 += numColsB; + + /* Decrement the loop counter */ + colCnt--; + } + + /* Convert the result from 34.30 to 1.15 format and store the saturated value in destination buffer */ + /* Saturate and store the result in the destination buffer */ + *px++ = (q7_t)__SSAT((sum >> 7), 8); + + /* Decrement the column loop counter */ + col--; + + /* Update the pointer pIn2 to point to the starting address of the next column */ + pIn2 = pInB + (numColsB - col); + + } while (col > 0U); + + /* Update the pointer pSrcA to point to the starting address of the next row */ + i = i + numColsB; + pInA = pInA + numColsA; + + /* Decrement the row loop counter */ + row--; + + } while (row > 0U); + + /* set status as RISCV_MATH_SUCCESS */ + status = RISCV_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +/** + @} end of MatrixMult group + */ diff --git a/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_scale_f16.c b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_scale_f16.c new file mode 100644 index 00000000..86b9a8ae --- /dev/null +++ b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_scale_f16.c @@ -0,0 +1,136 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_mat_scale_f16.c + * Description: Multiplies a floating-point matrix by a scalar + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions_f16.h" + +#if defined(RISCV_FLOAT16_SUPPORTED) + + +/** + @ingroup groupMatrix + */ + + +/** + @addtogroup MatrixScale + @{ + */ + +/** + @brief Floating-point matrix scaling. + @param[in] pSrc points to input matrix + @param[in] scale scale factor to be applied + @param[out] pDst points to output matrix structure + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_SIZE_MISMATCH : Matrix size check failed + */ + +riscv_status riscv_mat_scale_f16( + const riscv_matrix_instance_f16 * pSrc, + float16_t scale, + riscv_matrix_instance_f16 * pDst) +{ + float16_t *pIn = pSrc->pData; /* Input data matrix pointer */ + float16_t *pOut = pDst->pData; /* Output data matrix pointer */ + uint32_t numSamples; /* Total number of elements in the matrix */ + uint32_t blkCnt; /* Loop counters */ + riscv_status status; /* Status of matrix scaling */ + +#ifdef RISCV_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numRows) || + (pSrc->numCols != pDst->numCols) ) + { + /* Set status as RISCV_MATH_SIZE_MISMATCH */ + status = RISCV_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef RISCV_MATH_MATRIX_CHECK */ + + { + /* Total number of samples in input matrix */ + numSamples = (uint32_t) pSrc->numRows * pSrc->numCols; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) * scale */ + + /* Scale and store result in destination buffer. */ + *pOut++ = (*pIn++) * scale; + *pOut++ = (*pIn++) * scale; + *pOut++ = (*pIn++) * scale; + *pOut++ = (*pIn++) * scale; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) * scale */ + + /* Scale and store result in destination buffer. */ + *pOut++ = (*pIn++) * scale; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Set status as RISCV_MATH_SUCCESS */ + status = RISCV_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +/** + @} end of MatrixScale group + */ + +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ + diff --git a/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_scale_f32.c b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_scale_f32.c new file mode 100644 index 00000000..4d2075cc --- /dev/null +++ b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_scale_f32.c @@ -0,0 +1,162 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_mat_scale_f32.c + * Description: Multiplies a floating-point matrix by a scalar + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @defgroup MatrixScale Matrix Scale + + Multiplies a matrix by a scalar. This is accomplished by multiplying each element in the + matrix by the scalar. For example: + \image html MatrixScale.png "Matrix Scaling of a 3 x 3 matrix" + + The function checks to make sure that the input and output matrices are of the same size. + + In the fixed-point Q15 and Q31 functions, scale is represented by + a fractional multiplication scaleFract and an arithmetic shift shift. + The shift allows the gain of the scaling operation to exceed 1.0. + The overall scale factor applied to the fixed-point data is + 
+      scale = scaleFract * 2^shift.
+
+ */ + +/** + @addtogroup MatrixScale + @{ + */ + +/** + @brief Floating-point matrix scaling. + @param[in] pSrc points to input matrix + @param[in] scale scale factor to be applied + @param[out] pDst points to output matrix structure + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_SIZE_MISMATCH : Matrix size check failed + */ +riscv_status riscv_mat_scale_f32( + const riscv_matrix_instance_f32 * pSrc, + float32_t scale, + riscv_matrix_instance_f32 * pDst) +{ + float32_t *pIn = pSrc->pData; /* Input data matrix pointer */ + float32_t *pOut = pDst->pData; /* Output data matrix pointer */ + uint32_t numSamples; /* Total number of elements in the matrix */ + uint32_t blkCnt; /* Loop counters */ + riscv_status status; /* Status of matrix scaling */ + +#ifdef RISCV_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numRows) || + (pSrc->numCols != pDst->numCols) ) + { + /* Set status as RISCV_MATH_SIZE_MISMATCH */ + status = RISCV_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef RISCV_MATH_MATRIX_CHECK */ +#if defined(RISCV_VECTOR) + /* Total number of samples in input matrix */ + numSamples = (uint32_t) pSrc->numRows * pSrc->numCols; + blkCnt = numSamples; + size_t l; + vfloat32m8_t vx; + for (; (l = vsetvl_e32m8(blkCnt)) > 0; blkCnt -= l) { + vx = vle32_v_f32m8(pIn, l); + pIn += l; + vse32_v_f32m8 (pOut, vfmul_vf_f32m8(vx, scale, l), l); + pOut += l; + } + /* Set status as RISCV_MATH_SUCCESS */ + status = RISCV_MATH_SUCCESS; +#else + + { + /* Total number of samples in input matrix */ + numSamples = (uint32_t) pSrc->numRows * pSrc->numCols; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) * scale */ + + /* Scale and store result in destination buffer. */ + *pOut++ = (*pIn++) * scale; + *pOut++ = (*pIn++) * scale; + *pOut++ = (*pIn++) * scale; + *pOut++ = (*pIn++) * scale; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) * scale */ + + /* Scale and store result in destination buffer. */ + *pOut++ = (*pIn++) * scale; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Set status as RISCV_MATH_SUCCESS */ + status = RISCV_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +#endif /*defined(RISCV_VECTOR)*/ +} + +/** + @} end of MatrixScale group + */ diff --git a/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_scale_q15.c b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_scale_q15.c new file mode 100644 index 00000000..076d8c8a --- /dev/null +++ b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_scale_q15.c @@ -0,0 +1,201 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_mat_scale_q15.c + * Description: Multiplies a Q15 matrix by a scalar + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixScale + @{ + */ + +/** + @brief Q15 matrix scaling. + @param[in] pSrc points to input matrix + @param[in] scaleFract fractional portion of the scale factor + @param[in] shift number of bits to shift the result by + @param[out] pDst points to output matrix structure + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_SIZE_MISMATCH : Matrix size check failed + + @par Scaling and Overflow Behavior + The input data *pSrc and scaleFract are in 1.15 format. + These are multiplied to yield a 2.30 intermediate result and this is shifted with saturation to 1.15 format. + */ +riscv_status riscv_mat_scale_q15( + const riscv_matrix_instance_q15 * pSrc, + q15_t scaleFract, + int32_t shift, + riscv_matrix_instance_q15 * pDst) +{ + q15_t *pIn = pSrc->pData; /* Input data matrix pointer */ + q15_t *pOut = pDst->pData; /* Output data matrix pointer */ + uint32_t numSamples; /* Total number of elements in the matrix */ + uint32_t blkCnt; /* Loop counter */ + riscv_status status; /* Status of matrix scaling */ + int32_t kShift = 15 - shift; /* Total shift to apply after scaling */ + +#if defined (RISCV_MATH_DSP) && (__RISCV_XLEN == 64) + q63_t inA164; +#endif /* __RISCV_XLEN == 64 */ +#if defined (RISCV_MATH_LOOPUNROLL) && defined (RISCV_MATH_DSP) + q31_t inA1, inA2; + q31_t out1, out2, out3, out4; /* Temporary output variables */ + q15_t in1, in2, in3, in4; /* Temporary input variables */ +#endif + +#ifdef RISCV_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numRows) || + (pSrc->numCols != pDst->numCols) ) + { + /* Set status as RISCV_MATH_SIZE_MISMATCH */ + status = RISCV_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef RISCV_MATH_MATRIX_CHECK */ +#if defined(RISCV_VECTOR) + /* Total number of samples in input matrix */ + numSamples = (uint32_t) pSrc->numRows * pSrc->numCols; + blkCnt = numSamples; + size_t l; + vint16m4_t vx; + for (; (l = vsetvl_e32m4(blkCnt)) > 0; blkCnt -= l) { + vx = vle16_v_i16m4(pIn, l); + pIn += l; + //vse16_v_i16m4 (pOut, vnsra_wx_i16m4(vmin_vx_i32m8(vmax_vx_i32m8(vwmul_vx_i32m8(vx, scaleFract), 0xffff8000), 0x7fff), kShift)); + vse16_v_i16m4 (pOut, vnclip_wx_i16m4(vwmul_vx_i32m8(vx, scaleFract, l), kShift, l), l); + pOut += l; + } + /* Set status as RISCV_MATH_SUCCESS */ + status = RISCV_MATH_SUCCESS; +#else + + { + /* Total number of samples in input matrix */ + numSamples = (uint32_t) pSrc->numRows * pSrc->numCols; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) * k */ + +#if defined (RISCV_MATH_DSP) +#if __RISCV_XLEN == 64 + inA164 = read_q15x4_ia ((q15_t **) &pIn); + + /* Scale inputs and store result in temporary variables + * in single cycle by packing the outputs */ + out1 = (q31_t) ((q15_t) (inA164 >> 16) * scaleFract); + out2 = (q31_t) ((q15_t) (inA164 ) * scaleFract); + out3 = (q31_t) ((q15_t) (inA164 >> 48) * scaleFract); + out4 = (q31_t) ((q15_t) (inA164 >> 32) * scaleFract); +#else + /* read 2 times 2 samples at a time from source */ + inA1 = read_q15x2_ia ((q15_t **) &pIn); + inA2 = read_q15x2_ia ((q15_t **) &pIn); + + /* Scale inputs and store result in temporary variables + * in single cycle by packing the outputs */ + out1 = (q31_t) ((q15_t) (inA1 >> 16) * scaleFract); + out2 = (q31_t) ((q15_t) (inA1 ) * scaleFract); + out3 = (q31_t) ((q15_t) (inA2 >> 16) * scaleFract); + out4 = (q31_t) ((q15_t) (inA2 ) * scaleFract); +#endif /* __RISCV_XLEN == 64 */ + + /* apply shifting */ + out1 = out1 >> kShift; + out2 = out2 >> kShift; + out3 = out3 >> kShift; + out4 = out4 >> kShift; + + /* saturate the output */ + in1 = (q15_t) (__SSAT(out1, 16)); + in2 = (q15_t) (__SSAT(out2, 16)); + in3 = (q15_t) (__SSAT(out3, 16)); + in4 = (q15_t) (__SSAT(out4, 16)); + + /* store result to destination */ + write_q15x2_ia (&pOut, __PKHBT(in2, in1, 16)); + write_q15x2_ia (&pOut, __PKHBT(in4, in3, 16)); + +#else + *pOut++ = (q15_t) (__SSAT(((q31_t) (*pIn++) * scaleFract) >> kShift, 16)); + *pOut++ = (q15_t) (__SSAT(((q31_t) (*pIn++) * scaleFract) >> kShift, 16)); + *pOut++ = (q15_t) (__SSAT(((q31_t) (*pIn++) * scaleFract) >> kShift, 16)); + *pOut++ = (q15_t) (__SSAT(((q31_t) (*pIn++) * scaleFract) >> kShift, 16)); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) * k */ + + /* Scale, saturate and store result in destination buffer. */ + *pOut++ = (q15_t) (__SSAT(((q31_t) (*pIn++) * scaleFract) >> kShift, 16)); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Set status as RISCV_MATH_SUCCESS */ + status = RISCV_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +#endif /*defined(RISCV_VECTOR)*/ +} + +/** + @} end of MatrixScale group + */ diff --git a/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_scale_q31.c b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_scale_q31.c new file mode 100644 index 00000000..ee9e4b8b --- /dev/null +++ b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_scale_q31.c @@ -0,0 +1,182 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_mat_scale_q31.c + * Description: Multiplies a Q31 matrix by a scalar + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixScale + @{ + */ + +/** + @brief Q31 matrix scaling. + @param[in] pSrc points to input matrix + @param[in] scaleFract fractional portion of the scale factor + @param[in] shift number of bits to shift the result by + @param[out] pDst points to output matrix structure + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_SIZE_MISMATCH : Matrix size check failed + + @par Scaling and Overflow Behavior + The input data *pSrc and scaleFract are in 1.31 format. + These are multiplied to yield a 2.62 intermediate result which is shifted with saturation to 1.31 format. + */ +riscv_status riscv_mat_scale_q31( + const riscv_matrix_instance_q31 * pSrc, + q31_t scaleFract, + int32_t shift, + riscv_matrix_instance_q31 * pDst) +{ + q31_t *pIn = pSrc->pData; /* Input data matrix pointer */ + q31_t *pOut = pDst->pData; /* Output data matrix pointer */ + uint32_t numSamples; /* Total number of elements in the matrix */ + uint32_t blkCnt; /* Loop counter */ + riscv_status status; /* Status of matrix scaling */ + int32_t kShift = shift + 1; /* Shift to apply after scaling */ + q31_t in, out; /* Temporary variabels */ + +#ifdef RISCV_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numRows) || + (pSrc->numCols != pDst->numCols) ) + { + /* Set status as RISCV_MATH_SIZE_MISMATCH */ + status = RISCV_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef RISCV_MATH_MATRIX_CHECK */ +#if defined(RISCV_VECTOR) + /* Total number of samples in input matrix */ + numSamples = (uint32_t) pSrc->numRows * pSrc->numCols; + blkCnt = numSamples; + size_t l; + vint32m4_t v_in, v_out; + for (; (l = vsetvl_e32m4(blkCnt)) > 0; blkCnt -= l) { + v_in = vle32_v_i32m4(pIn, l); + pIn += l; + v_in = vnsra_wx_i32m4(vwmul_vx_i64m8(v_in, scaleFract, l),32U, l); + v_out = vsll_vx_i32m4(v_in, (uint8_t)kShift, l); + vse32_v_i32m4 (pOut, v_out, l); + pOut += l; + } + /* Set status as RISCV_MATH_SUCCESS */ + status = RISCV_MATH_SUCCESS; +#else + + { + /* Total number of samples in input matrix */ + numSamples = (uint32_t) pSrc->numRows * pSrc->numCols; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) * k */ + + /* Scale, saturate and store result in destination buffer. */ + in = *pIn++; /* read four inputs from source */ + in = ((q63_t) in * scaleFract) >> 32; /* multiply input with scaler value */ + out = in << kShift; /* apply shifting */ + if (in != (out >> kShift)) /* saturate the results. */ + out = 0x7FFFFFFF ^ (in >> 31); + *pOut++ = out; /* Store result destination */ + + in = *pIn++; + in = ((q63_t) in * scaleFract) >> 32; + out = in << kShift; + if (in != (out >> kShift)) + out = 0x7FFFFFFF ^ (in >> 31); + *pOut++ = out; + + in = *pIn++; + in = ((q63_t) in * scaleFract) >> 32; + out = in << kShift; + if (in != (out >> kShift)) + out = 0x7FFFFFFF ^ (in >> 31); + *pOut++ = out; + + in = *pIn++; + in = ((q63_t) in * scaleFract) >> 32; + out = in << kShift; + if (in != (out >> kShift)) + out = 0x7FFFFFFF ^ (in >> 31); + *pOut++ = out; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) * k */ + + /* Scale, saturate and store result in destination buffer. */ + in = *pIn++; + in = ((q63_t) in * scaleFract) >> 32; + out = in << kShift; + if (in != (out >> kShift)) + out = 0x7FFFFFFF ^ (in >> 31); + *pOut++ = out; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Set status as RISCV_MATH_SUCCESS */ + status = RISCV_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +#endif /*defined(RISCV_VECTOR)*/ +} + +/** + @} end of MatrixScale group + */ diff --git a/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_solve_lower_triangular_f16.c b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_solve_lower_triangular_f16.c new file mode 100644 index 00000000..58ce11cf --- /dev/null +++ b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_solve_lower_triangular_f16.c @@ -0,0 +1,129 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_mat_solve_lower_triangular_f16.c + * Description: Solve linear system LT X = A with LT lower triangular matrix + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions_f16.h" + +#if defined(RISCV_FLOAT16_SUPPORTED) +/** + @ingroup groupMatrix + */ + + +/** + @addtogroup MatrixInv + @{ + */ + + + /** + * @brief Solve LT . X = A where LT is a lower triangular matrix + * @param[in] lt The lower triangular matrix + * @param[in] a The matrix a + * @param[out] dst The solution X of LT . X = A + * @return The function returns RISCV_MATH_SINGULAR, if the system can't be solved. + */ + + riscv_status riscv_mat_solve_lower_triangular_f16( + const riscv_matrix_instance_f16 * lt, + const riscv_matrix_instance_f16 * a, + riscv_matrix_instance_f16 * dst) + { + riscv_status status; /* status of matrix inverse */ + + +#ifdef RISCV_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((lt->numRows != lt->numCols) || + (a->numRows != a->numCols) || + (lt->numRows != a->numRows) ) + { + /* Set status as RISCV_MATH_SIZE_MISMATCH */ + status = RISCV_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef RISCV_MATH_MATRIX_CHECK */ + + { + /* a1 b1 c1 x1 = a1 + b2 c2 x2 a2 + c3 x3 a3 + + x3 = a3 / c3 + x2 = (a2 - c2 x3) / b2 + + */ + int i,j,k,n; + + n = dst->numRows; + + float16_t *pX = dst->pData; + float16_t *pLT = lt->pData; + float16_t *pA = a->pData; + + float16_t *lt_row; + float16_t *a_col; + + for(j=0; j < n; j ++) + { + a_col = &pA[j]; + + for(i=0; i < n ; i++) + { + lt_row = &pLT[n*i]; + + float16_t tmp=a_col[i * n]; + + for(k=0; k < i; k++) + { + tmp -= lt_row[k] * pX[n*k+j]; + } + + if (lt_row[i]==0.0f) + { + return(RISCV_MATH_SINGULAR); + } + tmp = tmp / lt_row[i]; + pX[i*n+j] = tmp; + } + + } + status = RISCV_MATH_SUCCESS; + + } + + /* Return to application */ + return (status); +} + +/** + @} end of MatrixInv group + */ +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ diff --git a/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_solve_lower_triangular_f32.c b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_solve_lower_triangular_f32.c new file mode 100644 index 00000000..1c2f6b32 --- /dev/null +++ b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_solve_lower_triangular_f32.c @@ -0,0 +1,155 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_mat_solve_lower_triangular_f32.c + * Description: Solve linear system LT X = A with LT lower triangular matrix + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + + +/** + @addtogroup MatrixInv + @{ + */ + + + /** + * @brief Solve LT . X = A where LT is a lower triangular matrix + * @param[in] lt The lower triangular matrix + * @param[in] a The matrix a + * @param[out] dst The solution X of LT . X = A + * @return The function returns RISCV_MATH_SINGULAR, if the system can't be solved. + */ + + riscv_status riscv_mat_solve_lower_triangular_f32( + const riscv_matrix_instance_f32 * lt, + const riscv_matrix_instance_f32 * a, + riscv_matrix_instance_f32 * dst) + { + riscv_status status; /* status of matrix inverse */ + +#if defined(RISCV_VECTOR) + uint32_t blkCnt; /* Loop counter */ + size_t l; + vfloat32m8_t v_x, v_y; + vfloat32m8_t v_a; + vfloat32m1_t v_temp; + float32_t *pVlt_row; + float32_t *pX_row; + ptrdiff_t bstride; + l = vsetvl_e32m1(1); + v_temp = vfsub_vv_f32m1(v_temp, v_temp, l); +#endif + +#ifdef RISCV_MATH_MATRIX_CHECK + /* Check for matrix mismatch condition */ + if ((lt->numRows != lt->numCols) || + (a->numRows != a->numCols) || + (lt->numRows != a->numRows) ) + { + /* Set status as RISCV_MATH_SIZE_MISMATCH */ + status = RISCV_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef RISCV_MATH_MATRIX_CHECK */ + + { + /* a1 b1 c1 x1 = a1 + b2 c2 x2 a2 + c3 x3 a3 + + x3 = a3 / c3 + x2 = (a2 - c2 x3) / b2 + + */ + int i,j,k,n; + + n = dst->numRows; + + float32_t *pX = dst->pData; + float32_t *pLT = lt->pData; + float32_t *pA = a->pData; + + float32_t *lt_row; + float32_t *a_col; + + for(j=0; j < n; j ++) + { + a_col = &pA[j]; + + for(i=0; i < n ; i++) + { + lt_row = &pLT[n*i]; + + float32_t tmp=a_col[i * n]; +#if defined(RISCV_VECTOR) + blkCnt = i; + pVlt_row = lt_row; + pX_row = pX + j; + l = vsetvl_e32m8(blkCnt); + v_a = vfsub_vv_f32m8(v_a,v_a, l); + bstride = 4*n; + for (; (l = vsetvl_e32m8(blkCnt)) > 0; blkCnt -= l) { + v_x = vle32_v_f32m8(pVlt_row, l); + v_y = vlse32_v_f32m8(pX_row,bstride, l); + v_a = vfmacc_vv_f32m8(v_a,v_x,v_y, l); + pVlt_row += l; + pX_row += l*n; + } + l = vsetvl_e32m8(i); + tmp -= vfmv_f_s_f32m1_f32(vfredsum_vs_f32m8_f32m1(v_temp,v_a,v_temp, l)); +#else + for(k=0; k < i; k++) + { + tmp -= lt_row[k] * pX[n*k+j]; + } +#endif + if (lt_row[i]==0.0f) + { + return(RISCV_MATH_SINGULAR); + } + tmp = tmp / lt_row[i]; + pX[i*n+j] = tmp; + } + + } + status = RISCV_MATH_SUCCESS; + + } + + /* Return to application */ + return (status); +} + + +/** + @} end of MatrixInv group + */ diff --git a/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_solve_lower_triangular_f64.c b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_solve_lower_triangular_f64.c new file mode 100644 index 00000000..8a787ed2 --- /dev/null +++ b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_solve_lower_triangular_f64.c @@ -0,0 +1,153 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_mat_solve_lower_triangular_f64.c + * Description: Solve linear system LT X = A with LT lower triangular matrix + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + + +/** + @addtogroup MatrixInv + @{ + */ + + + /** + * @brief Solve LT . X = A where LT is a lower triangular matrix + * @param[in] lt The lower triangular matrix + * @param[in] a The matrix a + * @param[out] dst The solution X of LT . X = A + * @return The function returns RISCV_MATH_SINGULAR, if the system can't be solved. + */ + riscv_status riscv_mat_solve_lower_triangular_f64( + const riscv_matrix_instance_f64 * lt, + const riscv_matrix_instance_f64 * a, + riscv_matrix_instance_f64 * dst) + { + riscv_status status; /* status of matrix inverse */ + +#if defined(RISCV_VECTOR) && (defined(__riscv_flen) && (__riscv_flen == 64)) + uint32_t blkCnt; /* Loop counter */ + size_t l; + vfloat64m8_t v_x, v_y; + vfloat64m8_t v_a; + vfloat64m1_t v_temp; + float64_t *pVlt_row; + float64_t *pX_row; + ptrdiff_t bstride; + l = vsetvl_e64m1(1); + v_temp = vfsub_vv_f64m1(v_temp, v_temp, l); +#endif + +#ifdef RISCV_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((lt->numRows != lt->numCols) || + (a->numRows != a->numCols) || + (lt->numRows != a->numRows) ) + { + /* Set status as RISCV_MATH_SIZE_MISMATCH */ + status = RISCV_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef RISCV_MATH_MATRIX_CHECK */ + + { + /* a1 b1 c1 x1 = a1 + b2 c2 x2 a2 + c3 x3 a3 + + x3 = a3 / c3 + x2 = (a2 - c2 x3) / b2 + + */ + int i,j,k,n; + + n = dst->numRows; + + float64_t *pX = dst->pData; + float64_t *pLT = lt->pData; + float64_t *pA = a->pData; + + float64_t *lt_row; + float64_t *a_col; + + for(j=0; j < n; j ++) + { + a_col = &pA[j]; + + for(i=0; i < n ; i++) + { + lt_row = &pLT[n*i]; + + float64_t tmp=a_col[i * n]; +#if defined(RISCV_VECTOR) && (defined(__riscv_flen) && (__riscv_flen == 64)) + blkCnt = i; + pVlt_row = lt_row; + pX_row = pX + j; + l = vsetvl_e64m8(blkCnt); + v_a = vfsub_vv_f64m8(v_a,v_a, l); + bstride = 4*n; + for (; (l = vsetvl_e64m8(blkCnt)) > 0; blkCnt -= l) { + v_x = vle64_v_f64m8(pVlt_row, l); + v_y = vlse64_v_f64m8(pX_row,bstride, l); + v_a = vfmacc_vv_f64m8(v_a,v_x,v_y, l); + pVlt_row += l; + pX_row += l*n; + } + l = vsetvl_e64m8(i); + tmp -= vfmv_f_s_f64m1_f64(vfredsum_vs_f64m8_f64m1(v_temp,v_a,v_temp, l)); +#else + for(k=0; k < i; k++) + { + tmp -= lt_row[k] * pX[n*k+j]; + } +#endif + if (lt_row[i]==0.0f) + { + return(RISCV_MATH_SINGULAR); + } + tmp = tmp / lt_row[i]; + pX[i*n+j] = tmp; + } + + } + status = RISCV_MATH_SUCCESS; + + } + + /* Return to application */ + return (status); +} +/** + @} end of MatrixInv group + */ diff --git a/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_solve_upper_triangular_f16.c b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_solve_upper_triangular_f16.c new file mode 100644 index 00000000..deb2b09e --- /dev/null +++ b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_solve_upper_triangular_f16.c @@ -0,0 +1,126 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_mat_solve_upper_triangular_f16.c + * Description: Solve linear system UT X = A with UT upper triangular matrix + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#include "dsp/matrix_functions_f16.h" + +#if defined(RISCV_FLOAT16_SUPPORTED) + + +/** + @ingroup groupMatrix + */ + + +/** + @addtogroup MatrixInv + @{ + */ + +/** + * @brief Solve UT . X = A where UT is an upper triangular matrix + * @param[in] ut The upper triangular matrix + * @param[in] a The matrix a + * @param[out] dst The solution X of UT . X = A + * @return The function returns RISCV_MATH_SINGULAR, if the system can't be solved. + */ + + riscv_status riscv_mat_solve_upper_triangular_f16( + const riscv_matrix_instance_f16 * ut, + const riscv_matrix_instance_f16 * a, + riscv_matrix_instance_f16 * dst) + { +riscv_status status; /* status of matrix inverse */ + + +#ifdef RISCV_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((ut->numRows != ut->numCols) || + (a->numRows != a->numCols) || + (ut->numRows != a->numRows) ) + { + /* Set status as RISCV_MATH_SIZE_MISMATCH */ + status = RISCV_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef RISCV_MATH_MATRIX_CHECK */ + + { + + int i,j,k,n; + + n = dst->numRows; + + float16_t *pX = dst->pData; + float16_t *pUT = ut->pData; + float16_t *pA = a->pData; + + float16_t *ut_row; + float16_t *a_col; + + for(j=0; j < n; j ++) + { + a_col = &pA[j]; + + for(i=n-1; i >= 0 ; i--) + { + ut_row = &pUT[n*i]; + + float16_t tmp=a_col[i * n]; + + for(k=n-1; k > i; k--) + { + tmp -= ut_row[k] * pX[n*k+j]; + } + + if (ut_row[i]==0.0f) + { + return(RISCV_MATH_SINGULAR); + } + tmp = tmp / ut_row[i]; + pX[i*n+j] = tmp; + } + + } + status = RISCV_MATH_SUCCESS; + + } + + + /* Return to application */ + return (status); +} + + +/** + @} end of MatrixInv group + */ +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ diff --git a/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_solve_upper_triangular_f32.c b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_solve_upper_triangular_f32.c new file mode 100644 index 00000000..bc5bf6a1 --- /dev/null +++ b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_solve_upper_triangular_f32.c @@ -0,0 +1,149 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_mat_solve_upper_triangular_f32.c + * Description: Solve linear system UT X = A with UT upper triangular matrix + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + + +/** + @ingroup groupMatrix + */ + + +/** + @addtogroup MatrixInv + @{ + */ + +/** + * @brief Solve UT . X = A where UT is an upper triangular matrix + * @param[in] ut The upper triangular matrix + * @param[in] a The matrix a + * @param[out] dst The solution X of UT . X = A + * @return The function returns RISCV_MATH_SINGULAR, if the system can't be solved. + */ + + riscv_status riscv_mat_solve_upper_triangular_f32( + const riscv_matrix_instance_f32 * ut, + const riscv_matrix_instance_f32 * a, + riscv_matrix_instance_f32 * dst) + { +riscv_status status; /* status of matrix inverse */ + + +#ifdef RISCV_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((ut->numRows != ut->numCols) || + (a->numRows != a->numCols) || + (ut->numRows != a->numRows) ) + { + /* Set status as RISCV_MATH_SIZE_MISMATCH */ + status = RISCV_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef RISCV_MATH_MATRIX_CHECK */ + + { +#if defined(RISCV_VECTOR) + uint32_t blkCnt; /* Loop counter */ + size_t l; + vfloat32m8_t v_x, v_y; + vfloat32m8_t v_a; + vfloat32m1_t v_temp; + float32_t *pVut_row; + float32_t *pX_row; + ptrdiff_t bstride; + l = vsetvl_e32m1(1); + v_temp = vfsub_vv_f32m1(v_temp, v_temp, l); +#endif + int i,j,k,n; + + n = dst->numRows; + + float32_t *pX = dst->pData; + float32_t *pUT = ut->pData; + float32_t *pA = a->pData; + + float32_t *ut_row; + float32_t *a_col; + + for(j=0; j < n; j ++) + { + a_col = &pA[j]; + + for(i=n-1; i >= 0 ; i--) + { + ut_row = &pUT[n*i]; + + float32_t tmp=a_col[i * n]; +#if defined(RISCV_VECTOR) + blkCnt = n-i-1; + pVut_row = ut_row + i+1; + pX_row = pX + n*(i+1)+j; + l = vsetvl_e32m8(blkCnt); + v_a = vfsub_vv_f32m8(v_a,v_a, l); + bstride = 4*n; + for (; (l = vsetvl_e32m8(blkCnt)) > 0; blkCnt -= l) { + v_x = vle32_v_f32m8(pVut_row, l); + v_y = vlse32_v_f32m8(pX_row,bstride, l); + v_a = vfmacc_vv_f32m8(v_a,v_x,v_y, l); + pVut_row += l; + pX_row += l*n; + } + l = vsetvl_e32m8(n-i-1); + tmp -= vfmv_f_s_f32m1_f32(vfredsum_vs_f32m8_f32m1(v_temp,v_a,v_temp, l)); +#else + for(k=i+1; k < n; k++) + { + tmp -= ut_row[k] * pX[n*k+j]; + } +#endif + if (ut_row[i]==0.0f) + { + return(RISCV_MATH_SINGULAR); + } + tmp = tmp / ut_row[i]; + pX[i*n+j] = tmp; + } + + } + status = RISCV_MATH_SUCCESS; + + } + + + /* Return to application */ + return (status); +} + + +/** + @} end of MatrixInv group + */ diff --git a/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_solve_upper_triangular_f64.c b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_solve_upper_triangular_f64.c new file mode 100644 index 00000000..5403ca5e --- /dev/null +++ b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_solve_upper_triangular_f64.c @@ -0,0 +1,148 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_mat_solve_upper_triangular_f64.c + * Description: Solve linear system UT X = A with UT upper triangular matrix + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + + +/** + @ingroup groupMatrix + */ + + +/** + @addtogroup MatrixInv + @{ + */ + +/** + * @brief Solve UT . X = A where UT is an upper triangular matrix + * @param[in] ut The upper triangular matrix + * @param[in] a The matrix a + * @param[out] dst The solution X of UT . X = A + * @return The function returns RISCV_MATH_SINGULAR, if the system can't be solved. + */ + riscv_status riscv_mat_solve_upper_triangular_f64( + const riscv_matrix_instance_f64 * ut, + const riscv_matrix_instance_f64 * a, + riscv_matrix_instance_f64 * dst) + { +riscv_status status; /* status of matrix inverse */ +#if defined(RISCV_VECTOR) && (defined(__riscv_flen) && (__riscv_flen == 64)) + uint32_t blkCnt; /* Loop counter */ + size_t l; + vfloat64m8_t v_x, v_y; + vfloat64m8_t v_a; + vfloat64m1_t v_temp; + float64_t *pVut_row; + float64_t *pX_row; + ptrdiff_t bstride; + l = vsetvl_e64m1(1); + v_temp = vfsub_vv_f64m1(v_temp, v_temp, l); +#endif +#ifdef RISCV_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((ut->numRows != ut->numCols) || + (a->numRows != a->numCols) || + (ut->numRows != a->numRows) ) + { + /* Set status as RISCV_MATH_SIZE_MISMATCH */ + status = RISCV_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef RISCV_MATH_MATRIX_CHECK */ + + { + + int i,j,k,n; + + n = dst->numRows; + + float64_t *pX = dst->pData; + float64_t *pUT = ut->pData; + float64_t *pA = a->pData; + + float64_t *ut_row; + float64_t *a_col; + + for(j=0; j < n; j ++) + { + a_col = &pA[j]; + + for(i=n-1; i >= 0 ; i--) + { + ut_row = &pUT[n*i]; + + float64_t tmp=a_col[i * n]; +#if defined(RISCV_VECTOR) && (defined(__riscv_flen) && (__riscv_flen == 64)) + blkCnt = n-i-1; + pVut_row = ut_row + i+1; + pX_row = pX + n*(i+1)+j; + l = vsetvl_e64m8(blkCnt); + v_a = vfsub_vv_f64m8(v_a,v_a, l); + bstride = 8*n; + for (; (l = vsetvl_e64m8(blkCnt)) > 0; blkCnt -= l) { + v_x = vle64_v_f64m8(pVut_row, l); + v_y = vlse64_v_f64m8(pX_row,bstride, l); + v_a = vfmacc_vv_f64m8(v_a,v_x,v_y, l); + pVut_row += l; + pX_row += l*n; + } + l = vsetvl_e64m8(n-i-1); + tmp -= vfmv_f_s_f64m1_f64(vfredsum_vs_f64m8_f64m1(v_temp,v_a,v_temp, l)); +#else + for(k=n-1; k > i; k--) + { + tmp -= ut_row[k] * pX[n*k+j]; + } +#endif + + if (ut_row[i]==0.0f) + { + return(RISCV_MATH_SINGULAR); + } + tmp = tmp / ut_row[i]; + pX[i*n+j] = tmp; + } + + } + status = RISCV_MATH_SUCCESS; + + } + + + /* Return to application */ + return (status); +} + + +/** + @} end of MatrixInv group + */ diff --git a/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_sub_f16.c b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_sub_f16.c new file mode 100644 index 00000000..aa95346d --- /dev/null +++ b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_sub_f16.c @@ -0,0 +1,140 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_mat_sub_f16.c + * Description: Floating-point matrix subtraction + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions_f16.h" + +#if defined(RISCV_FLOAT16_SUPPORTED) + + +/** + @ingroup groupMatrix + */ + + +/** + @addtogroup MatrixSub + @{ + */ + +/** + @brief Floating-point matrix subtraction. + @param[in] pSrcA points to the first input matrix structure + @param[in] pSrcB points to the second input matrix structure + @param[out] pDst points to output matrix structure + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_SIZE_MISMATCH : Matrix size check failed + */ + +riscv_status riscv_mat_sub_f16( + const riscv_matrix_instance_f16 * pSrcA, + const riscv_matrix_instance_f16 * pSrcB, + riscv_matrix_instance_f16 * pDst) +{ + float16_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + float16_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + float16_t *pOut = pDst->pData; /* output data matrix pointer */ + + uint32_t numSamples; /* total number of elements in the matrix */ + uint32_t blkCnt; /* loop counters */ + riscv_status status; /* status of matrix subtraction */ + +#ifdef RISCV_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || + (pSrcA->numCols != pSrcB->numCols) || + (pSrcA->numRows != pDst->numRows) || + (pSrcA->numCols != pDst->numCols) ) + { + /* Set status as RISCV_MATH_SIZE_MISMATCH */ + status = RISCV_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef RISCV_MATH_MATRIX_CHECK */ + + { + /* Total number of samples in input matrix */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) - B(m,n) */ + + /* Subtract and store result in destination buffer. */ + *pOut++ = (*pInA++) - (*pInB++); + *pOut++ = (*pInA++) - (*pInB++); + *pOut++ = (*pInA++) - (*pInB++); + *pOut++ = (*pInA++) - (*pInB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) - B(m,n) */ + + /* Subtract and store result in destination buffer. */ + *pOut++ = (*pInA++) - (*pInB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Set status as RISCV_MATH_SUCCESS */ + status = RISCV_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +/** + @} end of MatrixSub group + */ + +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ + diff --git a/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_sub_f32.c b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_sub_f32.c new file mode 100644 index 00000000..f3442296 --- /dev/null +++ b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_sub_f32.c @@ -0,0 +1,160 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_mat_sub_f32.c + * Description: Floating-point matrix subtraction + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @defgroup MatrixSub Matrix Subtraction + + Subtract two matrices. + \image html MatrixSubtraction.png "Subraction of two 3 x 3 matrices" + + The functions check to make sure that + pSrcA, pSrcB, and pDst have the same + number of rows and columns. + */ + +/** + @addtogroup MatrixSub + @{ + */ + +/** + @brief Floating-point matrix subtraction. + @param[in] pSrcA points to the first input matrix structure + @param[in] pSrcB points to the second input matrix structure + @param[out] pDst points to output matrix structure + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_SIZE_MISMATCH : Matrix size check failed + */ +riscv_status riscv_mat_sub_f32( + const riscv_matrix_instance_f32 * pSrcA, + const riscv_matrix_instance_f32 * pSrcB, + riscv_matrix_instance_f32 * pDst) +{ + float32_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + float32_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + float32_t *pOut = pDst->pData; /* output data matrix pointer */ + + uint32_t numSamples; /* total number of elements in the matrix */ + uint32_t blkCnt; /* loop counters */ + riscv_status status; /* status of matrix subtraction */ + +#ifdef RISCV_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || + (pSrcA->numCols != pSrcB->numCols) || + (pSrcA->numRows != pDst->numRows) || + (pSrcA->numCols != pDst->numCols) ) + { + /* Set status as RISCV_MATH_SIZE_MISMATCH */ + status = RISCV_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef RISCV_MATH_MATRIX_CHECK */ +#if defined(RISCV_VECTOR) + /* Total number of samples in input matrix */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + blkCnt = numSamples; + size_t l; + vfloat32m8_t vx, vy; + for (; (l = vsetvl_e32m8(blkCnt)) > 0; blkCnt -= l) { + vx = vle32_v_f32m8(pInA, l); + pInA += l; + vy = vle32_v_f32m8(pInB, l); + vse32_v_f32m8 (pOut, vfsub_vv_f32m8(vx, vy, l), l); + pInB += l; + pOut += l; + } + /* Set status as RISCV_MATH_SUCCESS */ + status = RISCV_MATH_SUCCESS; +#else + { + /* Total number of samples in input matrix */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) - B(m,n) */ + + /* Subtract and store result in destination buffer. */ + *pOut++ = (*pInA++) - (*pInB++); + *pOut++ = (*pInA++) - (*pInB++); + *pOut++ = (*pInA++) - (*pInB++); + *pOut++ = (*pInA++) - (*pInB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) - B(m,n) */ + + /* Subtract and store result in destination buffer. */ + *pOut++ = (*pInA++) - (*pInB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Set status as RISCV_MATH_SUCCESS */ + status = RISCV_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +#endif /*defined(RISCV_VECTOR)*/ +} + +/** + @} end of MatrixSub group + */ diff --git a/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_sub_f64.c b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_sub_f64.c new file mode 100644 index 00000000..e9613969 --- /dev/null +++ b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_sub_f64.c @@ -0,0 +1,144 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_mat_sub_f64.c + * Description: Floating-point matrix subtraction + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @defgroup MatrixSub Matrix Subtraction + + Subtract two matrices. + \image html MatrixSubtraction.png "Subraction of two 3 x 3 matrices" + + The functions check to make sure that + pSrcA, pSrcB, and pDst have the same + number of rows and columns. + */ + +/** + @addtogroup MatrixSub + @{ + */ + +/** + @brief Floating-point matrix subtraction. + @param[in] pSrcA points to the first input matrix structure + @param[in] pSrcB points to the second input matrix structure + @param[out] pDst points to output matrix structure + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_SIZE_MISMATCH : Matrix size check failed + */ + +riscv_status riscv_mat_sub_f64( + const riscv_matrix_instance_f64 * pSrcA, + const riscv_matrix_instance_f64 * pSrcB, + riscv_matrix_instance_f64 * pDst) +{ + float64_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + float64_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + float64_t *pOut = pDst->pData; /* output data matrix pointer */ + + uint64_t numSamples; /* total number of elements in the matrix */ + uint64_t blkCnt; /* loop counters */ + riscv_status status; /* status of matrix subtraction */ + +#ifdef RISCV_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || + (pSrcA->numCols != pSrcB->numCols) || + (pSrcA->numRows != pDst->numRows) || + (pSrcA->numCols != pDst->numCols) ) + { + /* Set status as RISCV_MATH_SIZE_MISMATCH */ + status = RISCV_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef RISCV_MATH_MATRIX_CHECK */ + + { + /* Total number of samples in input matrix */ + numSamples = (uint64_t) pSrcA->numRows * pSrcA->numCols; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) - B(m,n) */ + + /* Subtract and store result in destination buffer. */ + *pOut++ = (*pInA++) - (*pInB++); + *pOut++ = (*pInA++) - (*pInB++); + *pOut++ = (*pInA++) - (*pInB++); + *pOut++ = (*pInA++) - (*pInB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) - B(m,n) */ + + /* Subtract and store result in destination buffer. */ + *pOut++ = (*pInA++) - (*pInB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Set status as RISCV_MATH_SUCCESS */ + status = RISCV_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +/** + @} end of MatrixSub group + */ diff --git a/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_sub_q15.c b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_sub_q15.c new file mode 100644 index 00000000..28084afb --- /dev/null +++ b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_sub_q15.c @@ -0,0 +1,167 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_mat_sub_q15.c + * Description: Q15 Matrix subtraction + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixSub + @{ + */ + +/** + @brief Q15 matrix subtraction. + @param[in] pSrcA points to the first input matrix structure + @param[in] pSrcB points to the second input matrix structure + @param[out] pDst points to output matrix structure + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_SIZE_MISMATCH : Matrix size check failed + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q15 range [0x8000 0x7FFF] are saturated. + */ +riscv_status riscv_mat_sub_q15( + const riscv_matrix_instance_q15 * pSrcA, + const riscv_matrix_instance_q15 * pSrcB, + riscv_matrix_instance_q15 * pDst) +{ + q15_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + q15_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + q15_t *pOut = pDst->pData; /* output data matrix pointer */ + + uint32_t numSamples; /* total number of elements in the matrix */ + uint32_t blkCnt; /* loop counters */ + riscv_status status; /* status of matrix subtraction */ + +#ifdef RISCV_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || + (pSrcA->numCols != pSrcB->numCols) || + (pSrcA->numRows != pDst->numRows) || + (pSrcA->numCols != pDst->numCols) ) + { + /* Set status as RISCV_MATH_SIZE_MISMATCH */ + status = RISCV_MATH_SIZE_MISMATCH; + } + else +#endif /* #ifdef RISCV_MATH_MATRIX_CHECK */ +#if defined(RISCV_VECTOR) + /* Total number of samples in input matrix */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + blkCnt = numSamples; + size_t l; + vint16m8_t vx, vy; + + for (; (l = vsetvl_e16m8(blkCnt)) > 0; blkCnt -= l) { + vx = vle16_v_i16m8(pInA, l); + pInA += l; + vy = vle16_v_i16m8(pInB, l); + vse16_v_i16m8 (pOut, vssub_vv_i16m8(vx, vy, l), l); + pInB += l; + pOut += l; + } +#else + /* Set status as RISCV_MATH_SUCCESS */ + status = RISCV_MATH_SUCCESS; + + { + /* Total number of samples in input matrix */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) - B(m,n) */ + + /* Subtract, Saturate and store result in destination buffer. */ +#if defined (RISCV_MATH_DSP) +#if __RISCV_XLEN == 64 + write_q15x4_ia (&pOut, __RV_KSUB16(read_q15x4_ia((q15_t**)&pInA), read_q15x4_ia((q15_t **)&pInB))); +#else + write_q15x2_ia (&pOut, __QSUB16(read_q15x2_ia ((q15_t **) &pInA), read_q15x2_ia ((q15_t **) &pInB))); + write_q15x2_ia (&pOut, __QSUB16(read_q15x2_ia ((q15_t **) &pInA), read_q15x2_ia ((q15_t **) &pInB))); +#endif /* __RISCV_XLEN == 64 */ +#else + *pOut++ = (q15_t) __SSAT(((q31_t) * pInA++ - *pInB++), 16); + *pOut++ = (q15_t) __SSAT(((q31_t) * pInA++ - *pInB++), 16); + *pOut++ = (q15_t) __SSAT(((q31_t) * pInA++ - *pInB++), 16); + *pOut++ = (q15_t) __SSAT(((q31_t) * pInA++ - *pInB++), 16); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) - B(m,n) */ + + /* Subtract and store result in destination buffer. */ +#if defined (RISCV_MATH_DSP) + *pOut++ = (q15_t) __QSUB16(*pInA++, *pInB++); +#else + *pOut++ = (q15_t) __SSAT(((q31_t) * pInA++ - *pInB++), 16); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Set status as RISCV_MATH_SUCCESS */ + status = RISCV_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +#endif /*defined(RISCV_VECTOR)*/ +} + +/** + @} end of MatrixSub group + */ diff --git a/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_sub_q31.c b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_sub_q31.c new file mode 100644 index 00000000..8767d68b --- /dev/null +++ b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_sub_q31.c @@ -0,0 +1,164 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_mat_sub_q31.c + * Description: Q31 matrix subtraction + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixSub + @{ + */ + +/** + @brief Q31 matrix subtraction. + @param[in] pSrcA points to the first input matrix structure + @param[in] pSrcB points to the second input matrix structure + @param[out] pDst points to output matrix structure + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_SIZE_MISMATCH : Matrix size check failed + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] are saturated. + */ +riscv_status riscv_mat_sub_q31( + const riscv_matrix_instance_q31 * pSrcA, + const riscv_matrix_instance_q31 * pSrcB, + riscv_matrix_instance_q31 * pDst) +{ + q31_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + q31_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + q31_t *pOut = pDst->pData; /* output data matrix pointer */ + + uint32_t numSamples; /* total number of elements in the matrix */ + uint32_t blkCnt; /* loop counters */ + riscv_status status; /* status of matrix subtraction */ + +#ifdef RISCV_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || + (pSrcA->numCols != pSrcB->numCols) || + (pSrcA->numRows != pDst->numRows) || + (pSrcA->numCols != pDst->numCols) ) + { + /* Set status as RISCV_MATH_SIZE_MISMATCH */ + status = RISCV_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef RISCV_MATH_MATRIX_CHECK */ +#if defined(RISCV_VECTOR) + /* Total number of samples in input matrix */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + blkCnt = numSamples; + size_t l; + vint32m4_t vx, vy, vout_fin; + vint64m8_t vout, vout_mm; + for (; (l = vsetvl_e32m4(blkCnt)) > 0; blkCnt -= l) { + vx = vle32_v_i32m4(pInA, l); + pInA += l; + vy = vle32_v_i32m4(pInB, l); + pInB += l; + vout = vwsub_vv_i64m8(vx, vy, l); + vout_mm = vmin_vx_i64m8(vmax_vx_i64m8(vout, 0xffffffff80000000, l),0x7fffffff, l); + vout_fin = vnclip_wx_i32m4(vout_mm, 0U, l); + vse32_v_i32m4 (pOut, vout_fin, l); + pOut += l; + } +#else + /* Set status as RISCV_MATH_SUCCESS */ + status = RISCV_MATH_SUCCESS; + { + /* Total number of samples in input matrix */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) - B(m,n) */ +#if __RISCV_XLEN == 64 + /* Subtract and store result in destination buffer (8 samples at a time). */ + write_q31x2_ia (&pOut, __RV_KSUB32(read_q31x2_ia ((q31_t **) &pInA), read_q31x2_ia ((q31_t **) &pInB))); + write_q31x2_ia (&pOut, __RV_KSUB32(read_q31x2_ia ((q31_t **) &pInA), read_q31x2_ia ((q31_t **) &pInB))); +#else + /* Subtract, saturate and then store the results in the destination buffer. */ + *pOut++ = __QSUB(*pInA++, *pInB++); + + *pOut++ = __QSUB(*pInA++, *pInB++); + + *pOut++ = __QSUB(*pInA++, *pInB++); + + *pOut++ = __QSUB(*pInA++, *pInB++); +#endif /* __RISCV_XLEN == 64 */ + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) - B(m,n) */ + + /* Subtract, saturate and store result in destination buffer. */ + *pOut++ = __QSUB(*pInA++, *pInB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Set status as RISCV_MATH_SUCCESS */ + status = RISCV_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +#endif /*defined(RISCV_VECTOR)*/ +} + +/** + @} end of MatrixSub group + */ diff --git a/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_trans_f16.c b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_trans_f16.c new file mode 100644 index 00000000..7dfe8ed7 --- /dev/null +++ b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_trans_f16.c @@ -0,0 +1,153 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_mat_trans_f16.c + * Description: Floating-point matrix transpose + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions_f16.h" + +#if defined(RISCV_FLOAT16_SUPPORTED) + + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixTrans + @{ + */ + +/** + @brief Floating-point matrix transpose. + @param[in] pSrc points to input matrix + @param[out] pDst points to output matrix + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_SIZE_MISMATCH : Matrix size check failed + */ + +riscv_status riscv_mat_trans_f16( + const riscv_matrix_instance_f16 * pSrc, + riscv_matrix_instance_f16 * pDst) +{ + float16_t *pIn = pSrc->pData; /* input data matrix pointer */ + float16_t *pOut = pDst->pData; /* output data matrix pointer */ + float16_t *px; /* Temporary output data matrix pointer */ + uint16_t nRows = pSrc->numRows; /* number of rows */ + uint16_t nCols = pSrc->numCols; /* number of columns */ + uint32_t col, row = nRows, i = 0U; /* Loop counters */ + riscv_status status; /* status of matrix transpose */ + +#ifdef RISCV_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numCols) || + (pSrc->numCols != pDst->numRows) ) + { + /* Set status as RISCV_MATH_SIZE_MISMATCH */ + status = RISCV_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef RISCV_MATH_MATRIX_CHECK */ + + { + /* Matrix transpose by exchanging the rows with columns */ + /* row loop */ + do + { + /* Pointer px is set to starting address of column being processed */ + px = pOut + i; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + col = nCols >> 2U; + + while (col > 0U) /* column loop */ + { + /* Read and store input element in destination */ + *px = *pIn++; + /* Update pointer px to point to next row of transposed matrix */ + px += nRows; + + *px = *pIn++; + px += nRows; + + *px = *pIn++; + px += nRows; + + *px = *pIn++; + px += nRows; + + /* Decrement column loop counter */ + col--; + } + + /* Loop unrolling: Compute remaining outputs */ + col = nCols % 0x4U; + +#else + + /* Initialize col with number of samples */ + col = nCols; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (col > 0U) + { + /* Read and store input element in destination */ + *px = *pIn++; + + /* Update pointer px to point to next row of transposed matrix */ + px += nRows; + + /* Decrement column loop counter */ + col--; + } + + i++; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); /* row loop end */ + + /* Set status as RISCV_MATH_SUCCESS */ + status = RISCV_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +/** + * @} end of MatrixTrans group + */ + +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ + diff --git a/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_trans_f32.c b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_trans_f32.c new file mode 100644 index 00000000..917a7ed8 --- /dev/null +++ b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_trans_f32.c @@ -0,0 +1,187 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_mat_trans_f32.c + * Description: Floating-point matrix transpose + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @defgroup MatrixTrans Matrix Transpose + + Tranposes a matrix. + + Transposing an M x N matrix flips it around the center diagonal and results in an N x M matrix. + \image html MatrixTranspose.png "Transpose of a 3 x 3 matrix" + */ + +/** + @addtogroup MatrixTrans + @{ + */ + +/** + @brief Floating-point matrix transpose. + @param[in] pSrc points to input matrix + @param[out] pDst points to output matrix + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_SIZE_MISMATCH : Matrix size check failed + */ +riscv_status riscv_mat_trans_f32( + const riscv_matrix_instance_f32 * pSrc, + riscv_matrix_instance_f32 * pDst) +{ + float32_t *pIn = pSrc->pData; /* input data matrix pointer */ + float32_t *pOut = pDst->pData; /* output data matrix pointer */ + float32_t *px; /* Temporary output data matrix pointer */ + uint16_t nRows = pSrc->numRows; /* number of rows */ + uint16_t nCols = pSrc->numCols; /* number of columns */ + uint32_t col, row = nRows, i = 0U; /* Loop counters */ + riscv_status status; /* status of matrix transpose */ + +#ifdef RISCV_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numCols) || + (pSrc->numCols != pDst->numRows) ) + { + /* Set status as RISCV_MATH_SIZE_MISMATCH */ + status = RISCV_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef RISCV_MATH_MATRIX_CHECK */ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = nRows; + size_t l,max_l; + ptrdiff_t bstride = 4; // 32bit/8bit = 4 + ptrdiff_t col_diff = bstride * nCols; //Control the column width of the span + uint16_t colnum; // How many rowumns are controlled + vfloat32m8_t v_in; + float32_t *pIn1; + // max_l = vsetvl_e32m8(32); + + for(colnum = 0;colnum < nCols; colnum++) + { + blkCnt = nRows; + pIn1 = pIn; + for (; (l = vsetvl_e32m8(blkCnt)) > 0; blkCnt -= l) + { + v_in = vlse32_v_f32m8(pIn, col_diff, l); + vse32_v_f32m8 (pOut, v_in, l); + // if(l == max_l) + // { + pIn = pIn+l*nCols; + // } + pOut = pOut+l; + } + pIn = pIn1; + pIn = pIn+1; + } + /* Set status as RISCV_MATH_SUCCESS */ + status = RISCV_MATH_SUCCESS; +#else + { + /* Matrix transpose by exchanging the rows with columns */ + /* row loop */ + do + { + /* Pointer px is set to starting address of column being processed */ + px = pOut + i; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + col = nCols >> 2U; + + while (col > 0U) /* column loop */ + { + /* Read and store input element in destination */ + *px = *pIn++; + /* Update pointer px to point to next row of transposed matrix */ + px += nRows; + + *px = *pIn++; + px += nRows; + + *px = *pIn++; + px += nRows; + + *px = *pIn++; + px += nRows; + + /* Decrement column loop counter */ + col--; + } + + /* Loop unrolling: Compute remaining outputs */ + col = nCols % 0x4U; + +#else + + /* Initialize col with number of samples */ + col = nCols; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (col > 0U) + { + /* Read and store input element in destination */ + *px = *pIn++; + + /* Update pointer px to point to next row of transposed matrix */ + px += nRows; + + /* Decrement column loop counter */ + col--; + } + + i++; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); /* row loop end */ + + /* Set status as RISCV_MATH_SUCCESS */ + status = RISCV_MATH_SUCCESS; + } + +#endif /*defined(RISCV_VECTOR)*/ + + /* Return to application */ + return (status); + +} + +/** + * @} end of MatrixTrans group + */ diff --git a/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_trans_f64.c b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_trans_f64.c new file mode 100644 index 00000000..142fd6e6 --- /dev/null +++ b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_trans_f64.c @@ -0,0 +1,156 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_mat_trans_f64.c + * Description: Floating-point matrix transpose + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @defgroup MatrixTrans Matrix Transpose + + Tranposes a matrix. + + Transposing an M x N matrix flips it around the center diagonal and results in an N x M matrix. + \image html MatrixTranspose.png "Transpose of a 3 x 3 matrix" + */ + +/** + @addtogroup MatrixTrans + @{ + */ + +/** + @brief Floating-point matrix transpose. + @param[in] pSrc points to input matrix + @param[out] pDst points to output matrix + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_SIZE_MISMATCH : Matrix size check failed + */ + +riscv_status riscv_mat_trans_f64( + const riscv_matrix_instance_f64 * pSrc, + riscv_matrix_instance_f64 * pDst) +{ + float64_t *pIn = pSrc->pData; /* input data matrix pointer */ + float64_t *pOut = pDst->pData; /* output data matrix pointer */ + float64_t *px; /* Temporary output data matrix pointer */ + uint16_t nRows = pSrc->numRows; /* number of rows */ + uint16_t nCols = pSrc->numCols; /* number of columns */ + uint64_t col, row = nRows, i = 0U; /* Loop counters */ + riscv_status status; /* status of matrix transpose */ + +#ifdef RISCV_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numCols) || + (pSrc->numCols != pDst->numRows) ) + { + /* Set status as RISCV_MATH_SIZE_MISMATCH */ + status = RISCV_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef RISCV_MATH_MATRIX_CHECK */ + + { + /* Matrix transpose by exchanging the rows with columns */ + /* row loop */ + do + { + /* Pointer px is set to starting address of column being processed */ + px = pOut + i; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + col = nCols >> 2U; + + while (col > 0U) /* column loop */ + { + /* Read and store input element in destination */ + *px = *pIn++; + /* Update pointer px to point to next row of transposed matrix */ + px += nRows; + + *px = *pIn++; + px += nRows; + + *px = *pIn++; + px += nRows; + + *px = *pIn++; + px += nRows; + + /* Decrement column loop counter */ + col--; + } + + /* Loop unrolling: Compute remaining outputs */ + col = nCols % 0x4U; + +#else + + /* Initialize col with number of samples */ + col = nCols; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (col > 0U) + { + /* Read and store input element in destination */ + *px = *pIn++; + + /* Update pointer px to point to next row of transposed matrix */ + px += nRows; + + /* Decrement column loop counter */ + col--; + } + + i++; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); /* row loop end */ + + /* Set status as RISCV_MATH_SUCCESS */ + status = RISCV_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +/** + * @} end of MatrixTrans group + */ diff --git a/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_trans_q15.c b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_trans_q15.c new file mode 100644 index 00000000..dd0b39ae --- /dev/null +++ b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_trans_q15.c @@ -0,0 +1,216 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_mat_trans_q15.c + * Description: Q15 matrix transpose + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixTrans + @{ + */ + +/** + @brief Q15 matrix transpose. + @param[in] pSrc points to input matrix + @param[out] pDst points to output matrix + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_SIZE_MISMATCH : Matrix size check failed + */ + +riscv_status riscv_mat_trans_q15( + const riscv_matrix_instance_q15 * pSrc, + riscv_matrix_instance_q15 * pDst) +{ + q15_t *pIn = pSrc->pData; /* input data matrix pointer */ + q15_t *pOut = pDst->pData; /* output data matrix pointer */ + uint16_t nRows = pSrc->numRows; /* number of rows */ + uint16_t nCols = pSrc->numCols; /* number of columns */ + uint32_t col, row = nRows, i = 0U; /* Loop counters */ + riscv_status status; /* status of matrix transpose */ + +#if defined (RISCV_MATH_LOOPUNROLL) +#if __RISCV_XLEN == 64 + q63_t in64; /* variable to hold temporary output */ +#else + q31_t in; /* variable to hold temporary output */ +#endif /* __RISCV_XLEN == 64 */ +#endif + +#ifdef RISCV_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numCols) || + (pSrc->numCols != pDst->numRows) ) + { + /* Set status as RISCV_MATH_SIZE_MISMATCH */ + status = RISCV_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef RISCV_MATH_MATRIX_CHECK */ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = nRows; + size_t l,max_l; + ptrdiff_t bstride = 2; // 16bit/8bit = 2 + ptrdiff_t col_diff = bstride * nCols; //Control the column width of the span + uint16_t colnum; // How many rowumns are controlled + vint16m8_t v_in; + q15_t *pIn1; + // max_l = vsetvl_e16m8(32); + for(colnum = 0;colnum < nCols; colnum++) + { + blkCnt = nRows; + pIn1 = pIn; + for (; (l = vsetvl_e16m8(blkCnt)) > 0; blkCnt -= l) + { + v_in = vlse16_v_i16m8(pIn, col_diff, l); + vse16_v_i16m8 (pOut, v_in, l); + // if(l == max_l) + // { + pIn = pIn+l*nCols; + // } + pOut = pOut+l; + } + pIn = pIn1; + pIn = pIn+1; + } + /* Set status as RISCV_MATH_SUCCESS */ + status = RISCV_MATH_SUCCESS; +#else + + { + /* Matrix transpose by exchanging the rows with columns */ + /* row loop */ + do + { + /* Pointer pOut is set to starting address of column being processed */ + pOut = pDst->pData + i; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + col = nCols >> 2U; + + while (col > 0U) /* column loop */ + { +#if __RISCV_XLEN == 64 + in64 = read_q15x4_ia ((q15_t **) &pIn); + + *pOut = (q15_t) in64; + /* Update pointer pOut to point to next row of transposed matrix */ + pOut += nRows; + *pOut = (q15_t) ((in64 & (q31_t) 0xffff0000) >> 16); + pOut += nRows; + *pOut = (q15_t) (in64 >> 32); + pOut += nRows; + *pOut = (q15_t) (((in64 >> 32) & (q31_t) 0xffff0000) >> 16); + pOut += nRows; + +#else + /* Read two elements from row */ + in = read_q15x2_ia ((q15_t **) &pIn); + + /* Unpack and store one element in destination */ + *pOut = (q15_t) in; + + /* Update pointer pOut to point to next row of transposed matrix */ + pOut += nRows; + + /* Unpack and store second element in destination */ + *pOut = (q15_t) ((in & (q31_t) 0xffff0000) >> 16); + + /* Update pointer pOut to point to next row of transposed matrix */ + pOut += nRows; + + /* Read two elements from row */ + in = read_q15x2_ia ((q15_t **) &pIn); + + /* Unpack and store one element in destination */ + *pOut = (q15_t) in; + + /* Update pointer pOut to point to next row of transposed matrix */ + pOut += nRows; + + /* Unpack and store second element in destination */ + *pOut = (q15_t) ((in & (q31_t) 0xffff0000) >> 16); + + /* Update pointer pOut to point to next row of transposed matrix */ + pOut += nRows; +#endif /* __RISCV_XLEN == 64 */ + /* Decrement column loop counter */ + col--; + } + + /* Loop unrolling: Compute remaining outputs */ + col = nCols % 0x4U; + +#else + + /* Initialize col with number of samples */ + col = nCols; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (col > 0U) + { + /* Read and store input element in destination */ + *pOut = *pIn++; + + /* Update pointer pOut to point to next row of transposed matrix */ + pOut += nRows; + + /* Decrement column loop counter */ + col--; + } + + i++; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); /* row loop end */ + + /* Set status as RISCV_MATH_SUCCESS */ + status = RISCV_MATH_SUCCESS; + } + +#endif /*defined(RISCV_VECTOR)*/ + + /* Return to application */ + return (status); + +} + +/** + @} end of MatrixTrans group + */ diff --git a/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_trans_q31.c b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_trans_q31.c new file mode 100644 index 00000000..e5220b6b --- /dev/null +++ b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_trans_q31.c @@ -0,0 +1,177 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_mat_trans_q31.c + * Description: Q31 matrix transpose + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixTrans + @{ + */ + +/** + @brief Q31 matrix transpose. + @param[in] pSrc points to input matrix + @param[out] pDst points to output matrix + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_SIZE_MISMATCH : Matrix size check failed + */ +riscv_status riscv_mat_trans_q31( + const riscv_matrix_instance_q31 * pSrc, + riscv_matrix_instance_q31 * pDst) +{ + q31_t *pIn = pSrc->pData; /* input data matrix pointer */ + q31_t *pOut = pDst->pData; /* output data matrix pointer */ + q31_t *px; /* Temporary output data matrix pointer */ + uint16_t nRows = pSrc->numRows; /* number of rows */ + uint16_t nCols = pSrc->numCols; /* number of columns */ + uint32_t col, row = nRows, i = 0U; /* Loop counters */ + riscv_status status; /* status of matrix transpose */ + +#ifdef RISCV_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numCols) || + (pSrc->numCols != pDst->numRows) ) + { + /* Set status as RISCV_MATH_SIZE_MISMATCH */ + status = RISCV_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef RISCV_MATH_MATRIX_CHECK */ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = nRows; + size_t l,max_l; + ptrdiff_t bstride = 4; // 32bit/8bit = 4 + ptrdiff_t col_diff = bstride * nCols; //Control the column width of the span + uint16_t colnum; // How many rowumns are controlled + vint32m8_t v_in; + q31_t *pIn1; + // max_l = vsetvl_e32m8(32); + + for(colnum = 0;colnum < nCols; colnum++) + { + blkCnt = nRows; + pIn1 = pIn; + for (; (l = vsetvl_e32m8(blkCnt)) > 0; blkCnt -= l) + { + v_in = vlse32_v_i32m8(pIn, col_diff, l); + vse32_v_i32m8 (pOut, v_in, l); + // if(l == max_l) + // { + pIn = pIn+l*nCols; + // } + pOut = pOut+l; + } + pIn = pIn1; + pIn = pIn+1; + } + /* Set status as RISCV_MATH_SUCCESS */ + status = RISCV_MATH_SUCCESS; +#else + { + /* Matrix transpose by exchanging the rows with columns */ + /* row loop */ + do + { + /* Pointer px is set to starting address of column being processed */ + px = pOut + i; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + col = nCols >> 2U; + + while (col > 0U) /* column loop */ + { + /* Read and store input element in destination */ + *px = *pIn++; + /* Update pointer px to point to next row of transposed matrix */ + px += nRows; + + *px = *pIn++; + px += nRows; + + *px = *pIn++; + px += nRows; + + *px = *pIn++; + px += nRows; + + /* Decrement column loop counter */ + col--; + } + + /* Loop unrolling: Compute remaining outputs */ + col = nCols % 0x4U; + +#else + + /* Initialize col with number of samples */ + col = nCols; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (col > 0U) + { + /* Read and store input element in destination */ + *px = *pIn++; + + /* Update pointer px to point to next row of transposed matrix */ + px += nRows; + + /* Decrement column loop counter */ + col--; + } + + i++; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); /* row loop end */ + + /* Set status as RISCV_MATH_SUCCESS */ + status = RISCV_MATH_SUCCESS; + } + +#endif /*defined(RISCV_VECTOR)*/ + + /* Return to application */ + return (status); +} + +/** + @} end of MatrixTrans group + */ diff --git a/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_trans_q7.c b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_trans_q7.c new file mode 100644 index 00000000..c44da2be --- /dev/null +++ b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_trans_q7.c @@ -0,0 +1,106 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_mat_trans_q7.c + * Description: Q7 matrix transpose + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixTrans + @{ + */ + +/** + @brief Q7 matrix transpose. + @param[in] pSrc points to input matrix + @param[out] pDst points to output matrix + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_SIZE_MISMATCH : Matrix size check failed + */ +riscv_status riscv_mat_trans_q7(const riscv_matrix_instance_q7 *pSrc, riscv_matrix_instance_q7 *pDst) +{ + q7_t *pSrcA = pSrc->pData; /* input data matrix pointer */ + q7_t *pOut = pDst->pData; /* output data matrix pointer */ + uint16_t nRows = pSrc->numRows; /* number of nRows */ + uint16_t nColumns = pSrc->numCols; /* number of nColumns */ + uint16_t col, row = nRows, i = 0U; /* row and column loop counters */ + riscv_status status; /* status of matrix transpose */ + + +#ifdef RISCV_MATH_MATRIX_CHECK + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows)) { + /* Set status as RISCV_MATH_SIZE_MISMATCH */ + status = RISCV_MATH_SIZE_MISMATCH; + } else +#endif /* #ifdef RISCV_MATH_MATRIX_CHECK */ + + { + /* Matrix transpose by exchanging the rows with columns */ + /* row loop */ + do { + /* The pointer pOut is set to starting address of the column being processed */ + pOut = pDst->pData + i; + + /* Initialize column loop counter */ + col = nColumns; + + + while (col > 0U) { + /* Read and store the input element in the destination */ + *pOut = *pSrcA++; + + /* Update the pointer pOut to point to the next row of the transposed matrix */ + pOut += nRows; + + /* Decrement the column loop counter */ + col--; + } + + i++; + + /* Decrement the row loop counter */ + row--; + + } while (row > 0U); + + /* set status as RISCV_MATH_SUCCESS */ + status = RISCV_MATH_SUCCESS; + } + /* Return to application */ + return (status); +} + + +/** + @} end of MatrixTrans group + */ diff --git a/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_vec_mult_f16.c b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_vec_mult_f16.c new file mode 100644 index 00000000..be670bf4 --- /dev/null +++ b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_vec_mult_f16.c @@ -0,0 +1,162 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_mat_vec_mult_f16.c + * Description: Floating-point matrix and vector multiplication + * + * $Date: 23 April 2021 + * + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions_f16.h" + +#if defined(RISCV_FLOAT16_SUPPORTED) + + +/** + * @ingroup groupMatrix + */ + + +/** + * @addtogroup MatrixVectMult + * @{ + */ + +/** + * @brief Floating-point matrix and vector multiplication. + * @param[in] *pSrcMat points to the input matrix structure + * @param[in] *pVec points to input vector + * @param[out] *pDst points to output vector + */ +void riscv_mat_vec_mult_f16(const riscv_matrix_instance_f16 *pSrcMat, const float16_t *pVec, float16_t *pDst) +{ + uint32_t numRows = pSrcMat->numRows; + uint32_t numCols = pSrcMat->numCols; + const float16_t *pSrcA = pSrcMat->pData; + const float16_t *pInA1; /* input data matrix pointer A of Q31 type */ + const float16_t *pInA2; /* input data matrix pointer A of Q31 type */ + const float16_t *pInA3; /* input data matrix pointer A of Q31 type */ + const float16_t *pInA4; /* input data matrix pointer A of Q31 type */ + const float16_t *pInVec; /* input data matrix pointer B of Q31 type */ + float16_t *px; /* Temporary output data matrix pointer */ + uint16_t i, row, colCnt; /* loop counters */ + float16_t matData, matData2, vecData, vecData2; + + + /* Process 4 rows at a time */ + row = numRows >> 2; + i = 0u; + px = pDst; + + /* The following loop performs the dot-product of each row in pSrcA with the vector */ + /* row loop */ + while (row > 0) { + /* For every row wise process, the pInVec pointer is set + ** to the starting address of the vector */ + pInVec = pVec; + + /* Initialize accumulators */ + float16_t sum1 = 0.0f; + float16_t sum2 = 0.0f; + float16_t sum3 = 0.0f; + float16_t sum4 = 0.0f; + + /* Loop unrolling: process 2 columns per iteration */ + colCnt = numCols; + + /* Initialize pointers to the starting address of the column being processed */ + pInA1 = pSrcA + i; + pInA2 = pInA1 + numCols; + pInA3 = pInA2 + numCols; + pInA4 = pInA3 + numCols; + + + // Main loop: matrix-vector multiplication + while (colCnt > 0u) { + // Read 2 values from vector + vecData = *(pInVec)++; + // Read 8 values from the matrix - 2 values from each of 4 rows, and do multiply accumulate + matData = *(pInA1)++; + sum1 += matData * vecData; + matData = *(pInA2)++; + sum2 += matData * vecData; + matData = *(pInA3)++; + sum3 += matData * vecData; + matData = *(pInA4)++; + sum4 += matData * vecData; + + // Decrement the loop counter + colCnt--; + } + + /* Saturate and store the result in the destination buffer */ + *px++ = sum1; + *px++ = sum2; + *px++ = sum3; + *px++ = sum4; + + i = i + numCols * 4; + + /* Decrement the row loop counter */ + row--; + } + + /* process any remaining rows */ + row = numRows & 3u; + while (row > 0) { + + float16_t sum = 0.0f; + pInVec = pVec; + pInA1 = pSrcA + i; + + colCnt = numCols >> 1; + + while (colCnt > 0) { + vecData = *(pInVec)++; + vecData2 = *(pInVec)++; + matData = *(pInA1)++; + matData2 = *(pInA1)++; + sum += matData * vecData; + sum += matData2 * vecData2; + colCnt--; + } + // process remainder of row + colCnt = numCols & 1u; + while (colCnt > 0) { + sum += *pInA1++ * *pInVec++; + colCnt--; + } + + *px++ = sum; + i = i + numCols; + row--; + } +} + +/** + * @} end of MatrixMult group + */ + +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ + diff --git a/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_vec_mult_f32.c b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_vec_mult_f32.c new file mode 100644 index 00000000..36630bca --- /dev/null +++ b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_vec_mult_f32.c @@ -0,0 +1,165 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_mat_vec_mult_f32.c + * Description: Floating-point matrix and vector multiplication + * + * $Date: 23 April 2021 + * + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + + +/** + * @ingroup groupMatrix + */ + +/** + * @defgroup MatrixVectMult Matrix Vector Multiplication + * + * Multiplies a matrix and a vector. + * + */ + +/** + * @addtogroup MatrixVectMult + * @{ + */ + +/** + * @brief Floating-point matrix and vector multiplication. + * @param[in] *pSrcMat points to the input matrix structure + * @param[in] *pVec points to input vector + * @param[out] *pDst points to output vector + */ + +void riscv_mat_vec_mult_f32(const riscv_matrix_instance_f32 *pSrcMat, const float32_t *pVec, float32_t *pDst) +{ + uint32_t numRows = pSrcMat->numRows; + uint32_t numCols = pSrcMat->numCols; + const float32_t *pSrcA = pSrcMat->pData; + const float32_t *pInA1; /* input data matrix pointer A of Q31 type */ + const float32_t *pInA2; /* input data matrix pointer A of Q31 type */ + const float32_t *pInA3; /* input data matrix pointer A of Q31 type */ + const float32_t *pInA4; /* input data matrix pointer A of Q31 type */ + const float32_t *pInVec; /* input data matrix pointer B of Q31 type */ + float32_t *px; /* Temporary output data matrix pointer */ + uint16_t i, row, colCnt; /* loop counters */ + float32_t matData, matData2, vecData, vecData2; + + + /* Process 4 rows at a time */ + row = numRows >> 2; + i = 0u; + px = pDst; + + /* The following loop performs the dot-product of each row in pSrcA with the vector */ + /* row loop */ + while (row > 0) { + /* For every row wise process, the pInVec pointer is set + ** to the starting address of the vector */ + pInVec = pVec; + + /* Initialize accumulators */ + float32_t sum1 = 0.0f; + float32_t sum2 = 0.0f; + float32_t sum3 = 0.0f; + float32_t sum4 = 0.0f; + + /* Loop unrolling: process 2 columns per iteration */ + colCnt = numCols; + + /* Initialize pointers to the starting address of the column being processed */ + pInA1 = pSrcA + i; + pInA2 = pInA1 + numCols; + pInA3 = pInA2 + numCols; + pInA4 = pInA3 + numCols; + + + // Main loop: matrix-vector multiplication + while (colCnt > 0u) { + // Read 2 values from vector + vecData = *(pInVec)++; + // Read 8 values from the matrix - 2 values from each of 4 rows, and do multiply accumulate + matData = *(pInA1)++; + sum1 += matData * vecData; + matData = *(pInA2)++; + sum2 += matData * vecData; + matData = *(pInA3)++; + sum3 += matData * vecData; + matData = *(pInA4)++; + sum4 += matData * vecData; + + // Decrement the loop counter + colCnt--; + } + + /* Saturate and store the result in the destination buffer */ + *px++ = sum1; + *px++ = sum2; + *px++ = sum3; + *px++ = sum4; + + i = i + numCols * 4; + + /* Decrement the row loop counter */ + row--; + } + + /* process any remaining rows */ + row = numRows & 3u; + while (row > 0) { + + float32_t sum = 0.0f; + pInVec = pVec; + pInA1 = pSrcA + i; + + colCnt = numCols >> 1; + while (colCnt > 0) { + vecData = *(pInVec)++; + vecData2 = *(pInVec)++; + matData = *(pInA1)++; + matData2 = *(pInA1)++; + sum += matData * vecData; + sum += matData2 * vecData2; + colCnt--; + } + // process remainder of row + colCnt = numCols & 1u; + + + while (colCnt > 0) { + sum += *pInA1++ * *pInVec++; + colCnt--; + } + + *px++ = sum; + i = i + numCols; + row--; + } +} + +/** + * @} end of MatrixMult group + */ diff --git a/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_vec_mult_q15.c b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_vec_mult_q15.c new file mode 100644 index 00000000..3e2cf776 --- /dev/null +++ b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_vec_mult_q15.c @@ -0,0 +1,168 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_mat_vec_mult_q15.c + * Description: Q15 matrix and vector multiplication + * + * $Date: 23 April 2021 + * + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + * @ingroup groupMatrix + */ + + + +/** + * @addtogroup MatrixVectMult + * @{ + */ + +/** + * @brief Q15 matrix and vector multiplication. + * @param[in] *pSrcMat points to the input matrix structure + * @param[in] *pVec points to input vector + * @param[out] *pDst points to output vector + */ +void riscv_mat_vec_mult_q15(const riscv_matrix_instance_q15 *pSrcMat, const q15_t *pVec, q15_t *pDst) +{ + uint32_t numRows = pSrcMat->numRows; + uint32_t numCols = pSrcMat->numCols; + const q15_t *pSrcA = pSrcMat->pData; + const q15_t *pInA1; /* input data matrix pointer A of Q15 type */ + const q15_t *pInA2; /* input data matrix pointer A of Q15 type */ + const q15_t *pInA3; /* input data matrix pointer A of Q15 type */ + const q15_t *pInA4; /* input data matrix pointer A of Q15 type */ + const q15_t *pInVec; /* input data matrix pointer B of Q15 type */ + q15_t *px; /* Temporary output data matrix pointer */ + uint16_t i, row, colCnt; /* loop counters */ + q31_t matData, matData2, vecData, vecData2; + + + /* Process 4 rows at a time */ + row = numRows >> 2; + i = 0u; + px = pDst; + + /* The following loop performs the dot-product of each row in pSrcA with the vector */ + /* row loop */ + while (row > 0) { + /* For every row wise process, the pInVec pointer is set + ** to the starting address of the vector */ + pInVec = pVec; + + /* Initialize accumulators */ + q63_t sum1 = 0; + q63_t sum2 = 0; + q63_t sum3 = 0; + q63_t sum4 = 0; + + /* Loop unrolling: process 2 columns per iteration */ + colCnt = numCols >> 1; + + /* Initialize pointers to the starting address of the column being processed */ + pInA1 = pSrcA + i; + pInA2 = pInA1 + numCols; + pInA3 = pInA2 + numCols; + pInA4 = pInA3 + numCols; + + // Main loop: matrix-vector multiplication + while (colCnt > 0u) { + // Read 2 values from vector + vecData = read_q15x2_ia ((q15_t **) &pInVec); + + // Read 8 values from the matrix - 2 values from each of 4 rows, and do multiply accumulate + matData = read_q15x2_ia ((q15_t **) &pInA1); + sum1 = __SMLALD(matData, vecData, sum1); + matData = read_q15x2_ia ((q15_t **) &pInA2); + sum2 = __SMLALD(matData, vecData, sum2); + matData = read_q15x2_ia ((q15_t **) &pInA3); + sum3 = __SMLALD(matData, vecData, sum3); + matData = read_q15x2_ia ((q15_t **) &pInA4); + sum4 = __SMLALD(matData, vecData, sum4); + + // Decrement the loop counter + colCnt--; + } + + /* process any remaining columns */ + colCnt = numCols & 1u; + if (numCols & 1u) { + vecData = *pInVec++; + sum1 += (q63_t)*pInA1++ * vecData; + sum2 += (q63_t)*pInA2++ * vecData; + sum3 += (q63_t)*pInA3++ * vecData; + sum4 += (q63_t)*pInA4++ * vecData; + } + + /* Saturate and store the result in the destination buffer */ + *px++ = (q15_t)(__SSAT((sum1 >> 15), 16)); + *px++ = (q15_t)(__SSAT((sum2 >> 15), 16)); + *px++ = (q15_t)(__SSAT((sum3 >> 15), 16)); + *px++ = (q15_t)(__SSAT((sum4 >> 15), 16)); + + i = i + numCols * 4; + + /* Decrement the row loop counter */ + row--; + } + + /* process any remaining rows */ + row = numRows & 3u; + while (row > 0) { + + q63_t sum = 0; + pInVec = pVec; + pInA1 = pSrcA + i; + + // loop unrolling - process 4 elements at a time + colCnt = numCols >> 2; + + while (colCnt > 0) { + vecData = read_q15x2_ia ((q15_t **) &pInVec); + vecData2 = read_q15x2_ia ((q15_t **) &pInVec); + matData = read_q15x2_ia ((q15_t **) &pInA1); + matData2 = read_q15x2_ia ((q15_t **) &pInA1); + sum = __SMLALD(matData, vecData, sum); + sum = __SMLALD(matData2, vecData2, sum); + colCnt--; + } + + // process remainder of row + colCnt = numCols & 3u; + while (colCnt > 0) { + sum += (q63_t)*pInA1++ * *pInVec++; + colCnt--; + } + *px++ = (q15_t)(__SSAT((sum >> 15), 16)); + i = i + numCols; + row--; + } +} + +/** + * @} end of MatrixMult group + */ diff --git a/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_vec_mult_q31.c b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_vec_mult_q31.c new file mode 100644 index 00000000..bbde80fe --- /dev/null +++ b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_vec_mult_q31.c @@ -0,0 +1,159 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_mat_vec_mult_q31.c + * Description: Q31 matrix and vector multiplication + * + * $Date: 23 April 2021 + * + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + * @ingroup groupMatrix + */ + + + +/** + * @addtogroup MatrixVectMult + * @{ + */ + +/** + * @brief Q31 matrix and vector multiplication. + * @param[in] *pSrcMat points to the input matrix structure + * @param[in] *pVec points to the input vector + * @param[out] *pDst points to the output vector + */ +void riscv_mat_vec_mult_q31(const riscv_matrix_instance_q31 *pSrcMat, const q31_t *pVec, q31_t *pDst) +{ + uint32_t numRows = pSrcMat->numRows; + uint32_t numCols = pSrcMat->numCols; + const q31_t *pSrcA = pSrcMat->pData; + const q31_t *pInA1; /* input data matrix pointer A of Q31 type */ + const q31_t *pInA2; /* input data matrix pointer A of Q31 type */ + const q31_t *pInA3; /* input data matrix pointer A of Q31 type */ + const q31_t *pInA4; /* input data matrix pointer A of Q31 type */ + const q31_t *pInVec; /* input data matrix pointer B of Q31 type */ + q31_t *px; /* Temporary output data matrix pointer */ + uint16_t i, row, colCnt; /* loop counters */ + q31_t matData, matData2, vecData, vecData2; + + + /* Process 4 rows at a time */ + row = numRows >> 2; + i = 0u; + px = pDst; + + /* The following loop performs the dot-product of each row in pSrcA with the vector */ + /* row loop */ + while (row > 0) { + /* For every row wise process, the pInVec pointer is set + ** to the starting address of the vector */ + pInVec = pVec; + + /* Initialize accumulators */ + q63_t sum1 = 0; + q63_t sum2 = 0; + q63_t sum3 = 0; + q63_t sum4 = 0; + + /* Loop unrolling: process 2 columns per iteration */ + colCnt = numCols; + + /* Initialize pointers to the starting address of the column being processed */ + pInA1 = pSrcA + i; + pInA2 = pInA1 + numCols; + pInA3 = pInA2 + numCols; + pInA4 = pInA3 + numCols; + + + // Main loop: matrix-vector multiplication + while (colCnt > 0u) { + // Read 2 values from vector + vecData = *(pInVec)++; + + // Read 8 values from the matrix - 2 values from each of 4 rows, and do multiply accumulate + matData = *(pInA1)++; + sum1 += (q63_t)matData * vecData; + matData = *(pInA2)++; + sum2 += (q63_t)matData * vecData; + matData = *(pInA3)++; + sum3 += (q63_t)matData * vecData; + matData = *(pInA4)++; + sum4 += (q63_t)matData * vecData; + + // Decrement the loop counter + colCnt--; + } + + /* Saturate and store the result in the destination buffer */ + *px++ = (q31_t)(sum1 >> 31); + *px++ = (q31_t)(sum2 >> 31); + *px++ = (q31_t)(sum3 >> 31); + *px++ = (q31_t)(sum4 >> 31); + + i = i + numCols * 4; + + /* Decrement the row loop counter */ + row--; + } + + /* process any remaining rows */ + row = numRows & 3u; + while (row > 0) { + + q63_t sum = 0; + pInVec = pVec; + pInA1 = pSrcA + i; + + colCnt = numCols >> 1; + + while (colCnt > 0) { + vecData = *(pInVec)++; + vecData2 = *(pInVec)++; + matData = *(pInA1)++; + matData2 = *(pInA1)++; + sum += (q63_t)matData * vecData; + sum += (q63_t)matData2 * vecData2; + colCnt--; + } + + // process remainder of row + colCnt = numCols & 1u; + while (colCnt > 0) { + sum += (q63_t)*pInA1++ * *pInVec++; + colCnt--; + } + + *px++ = (q31_t)(sum >> 31); + i = i + numCols; + row--; + } +} + +/** + * @} end of MatrixMult group + */ diff --git a/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_vec_mult_q7.c b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_vec_mult_q7.c new file mode 100644 index 00000000..6161b338 --- /dev/null +++ b/components/nmsis/dsp/src/MatrixFunctions/riscv_mat_vec_mult_q7.c @@ -0,0 +1,190 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_mat_vec_mult_q7.c + * Description: Q7 matrix and vector multiplication + * + * $Date: 23 April 2021 + * + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + * @ingroup groupMatrix + */ + + + +/** + * @addtogroup MatrixVectMult + * @{ + */ + +/** + * @brief Q7 matrix and vector multiplication. + * @param[in] *pSrcMat points to the input matrix structure + * @param[in] *pVec points to the input vector + * @param[out] *pDst points to the output vector + */ +void riscv_mat_vec_mult_q7(const riscv_matrix_instance_q7 *pSrcMat, const q7_t *pVec, q7_t *pDst) +{ + uint32_t numRows = pSrcMat->numRows; + uint32_t numCols = pSrcMat->numCols; + const q7_t *pSrcA = pSrcMat->pData; + const q7_t *pInA1; /* input data matrix pointer of Q7 type */ + const q7_t *pInA2; /* input data matrix pointer of Q7 type */ + const q7_t *pInA3; /* input data matrix pointer of Q7 type */ + const q7_t *pInA4; /* input data matrix pointer of Q7 type */ + const q7_t *pInVec; /* input data vector pointer of Q7 type */ + q7_t *px; /* output data pointer */ + uint32_t i, row, colCnt; /* loop counters */ + + q31_t matData, matData2, vecData, vecData2; + + + /* Process 4 rows at a time */ + row = numRows >> 2; + i = 0u; + px = pDst; + + + + /* The following loop performs the dot-product of each row in pSrcA with the vector */ + while (row > 0) { + /* For every row wise process, the pInVec pointer is set + ** to the starting address of the vector */ + pInVec = pVec; + + /* Initialize accumulators */ + q31_t sum1 = 0; + q31_t sum2 = 0; + q31_t sum3 = 0; + q31_t sum4 = 0; + + /* Loop unrolling: process 4 columns per iteration */ + colCnt = numCols >> 2; + + /* Initialize row pointers so we can track 4 rows at once */ + pInA1 = pSrcA + i; + pInA2 = pInA1 + numCols; + pInA3 = pInA2 + numCols; + pInA4 = pInA3 + numCols; + + + // Inner loop: matrix-vector multiplication + + while (colCnt > 0u) { + // Read 4 values from vector + vecData = read_q7x4_ia ((q7_t **) &pInVec); + vecData2 = __SXTB16(__ROR(vecData, 8)); + vecData = __SXTB16(vecData); + // Read 16 values from the matrix - 4 values from each of 4 rows, and do multiply accumulate + matData = read_q7x4_ia ((q7_t **) &pInA1); + matData2 = __SXTB16(__ROR(matData, 8)); + matData = __SXTB16(matData); + sum1 = __SMLAD(matData, vecData, sum1); + sum1 = __SMLAD(matData2, vecData2, sum1); + matData = read_q7x4_ia ((q7_t **) &pInA2); + matData2 = __SXTB16(__ROR(matData, 8)); + matData = __SXTB16(matData); + sum2 = __SMLAD(matData, vecData, sum2); + sum2 = __SMLAD(matData2, vecData2, sum2); + matData = read_q7x4_ia ((q7_t **) &pInA3); + matData2 = __SXTB16(__ROR(matData, 8)); + matData = __SXTB16(matData); + sum3 = __SMLAD(matData, vecData, sum3); + sum3 = __SMLAD(matData2, vecData2, sum3); + matData = read_q7x4_ia ((q7_t **) &pInA4); + matData2 = __SXTB16(__ROR(matData, 8)); + matData = __SXTB16(matData); + sum4 = __SMLAD(matData, vecData, sum4); + sum4 = __SMLAD(matData2, vecData2, sum4); + + // Decrement the loop counter + colCnt--; + } + + /* process any remaining columns */ + + colCnt = numCols & 3u; + + while (colCnt > 0) { + vecData = *pInVec++; + sum1 += *pInA1++ * vecData; + sum2 += *pInA2++ * vecData; + sum3 += *pInA3++ * vecData; + sum4 += *pInA4++ * vecData; + colCnt--; + } + + /* Saturate and store the result in the destination buffer */ + *px++ = (q7_t)(__SSAT((sum1 >> 7), 8)); + *px++ = (q7_t)(__SSAT((sum2 >> 7), 8)); + *px++ = (q7_t)(__SSAT((sum3 >> 7), 8)); + *px++ = (q7_t)(__SSAT((sum4 >> 7), 8)); + + i = i + numCols * 4; + + /* Decrement the row loop counter */ + row--; + } + + /* process any remaining rows */ + row = numRows & 3u; + while (row > 0) { + + q31_t sum = 0; + pInVec = pVec; + pInA1 = pSrcA + i; + + // loop unrolling - process 4 elements at a time + colCnt = numCols >> 2; + + while (colCnt > 0) { + vecData = read_q7x4_ia ((q7_t **) &pInVec); + vecData2 = __SXTB16(__ROR(vecData, 8)); + vecData = __SXTB16(vecData); + matData = read_q7x4_ia ((q7_t **) &pInA1); + matData2 = __SXTB16(__ROR(matData, 8)); + matData = __SXTB16(matData); + sum = __SMLAD(matData, vecData, sum); + sum = __SMLAD(matData2, vecData2, sum); + colCnt--; + } + + // process remainder of row + colCnt = numCols & 3u; + while (colCnt > 0) { + sum += *pInA1++ * *pInVec++; + colCnt--; + } + *px++ = (q7_t)(__SSAT((sum >> 7), 8)); + i = i + numCols; + row--; + } +} + +/** + * @} end of MatrixMult group + */ diff --git a/components/nmsis/dsp/src/QuaternionMathFunctions/QuaternionMathFunctions.c b/components/nmsis/dsp/src/QuaternionMathFunctions/QuaternionMathFunctions.c new file mode 100644 index 00000000..ff3a574d --- /dev/null +++ b/components/nmsis/dsp/src/QuaternionMathFunctions/QuaternionMathFunctions.c @@ -0,0 +1,35 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: QuaternionMathFunctions.c + * Description: Combination of all quaternion math function source files. + * + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2019-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "riscv_quaternion_norm_f32.c" +#include "riscv_quaternion_inverse_f32.c" +#include "riscv_quaternion_conjugate_f32.c" +#include "riscv_quaternion_normalize_f32.c" +#include "riscv_quaternion_product_single_f32.c" +#include "riscv_quaternion_product_f32.c" +#include "riscv_quaternion2rotation_f32.c" +#include "riscv_rotation2quaternion_f32.c" diff --git a/components/nmsis/dsp/src/QuaternionMathFunctions/riscv_quaternion2rotation_f32.c b/components/nmsis/dsp/src/QuaternionMathFunctions/riscv_quaternion2rotation_f32.c new file mode 100644 index 00000000..378e5be6 --- /dev/null +++ b/components/nmsis/dsp/src/QuaternionMathFunctions/riscv_quaternion2rotation_f32.c @@ -0,0 +1,167 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_quaternion2rotation_f32.c + * Description: Floating-point quaternion 2 rotation conversion + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/quaternion_math_functions.h" +#include + +/** + @ingroup groupQuaternionMath + */ + +/** + @defgroup QuatConv Quaternion conversions + + Conversions between quaternion and rotation representations. + */ + +/** + @ingroup QuatConv + */ + +/** + @defgroup QuatRot Quaternion to Rotation + + Conversions from quaternion to rotation. + */ + +/** + @addtogroup QuatRot + @{ + */ + +/** + @brief Conversion of quaternion to equivalent rotation matrix. + @param[in] pInputQuaternions points to an array of normalized quaternions + @param[out] pOutputRotations points to an array of 3x3 rotations (in row order) + @param[in] nbQuaternions number of quaternions in the array + @return none. + + @par + Format of rotation matrix + + + The quaternion a + ib + jc + kd is converted into rotation matrix: + 
+     a^2 + b^2 - c^2 - d^2                 2bc - 2ad                 2bd + 2ac
+                 2bc + 2ad     a^2 - b^2 + c^2 - d^2                 2cd - 2ab
+                 2bd - 2ac                 2cd + 2ab     a^2 - b^2 - c^2 + d^2
+
+ Rotation matrix is saved in row order : R00 R01 R02 R10 R11 R12 R20 R21 R22 + */ + +void riscv_quaternion2rotation_f32(const float32_t *pInputQuaternions, + float32_t *pOutputRotations, + uint32_t nbQuaternions) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = nbQuaternions; /* Loop counter */ + size_t l; + vfloat32m8_t v_QA0, v_QA1, v_QA2, v_QA3; + vfloat32m8_t v_q00, v_q11, v_q22, v_q33, v_q01, v_q02, v_q03, v_q12, v_q13, v_q23; + vfloat32m8_t v_xx, v_yy, v_zz, v_xy, v_xz, v_yx, v_yz, v_zx, v_zy; + vfloat32m8_t v_temp; + float32_t *pQA = pInputQuaternions; + float32_t *pOUT = pOutputRotations; + ptrdiff_t bstride = 16; + ptrdiff_t bstride_out = 36; + for (; (l = vsetvl_e32m8(blkCnt)) > 0; blkCnt -= l) { + v_QA0 = vlse32_v_f32m8(pQA,bstride, l); + v_QA1 = vlse32_v_f32m8(pQA+1,bstride, l); + v_QA2 = vlse32_v_f32m8(pQA+2,bstride, l); + v_QA3 = vlse32_v_f32m8(pQA+3,bstride, l); + + v_q00 = vfmul_vv_f32m8(v_QA0,v_QA0, l); + v_q11 = vfmul_vv_f32m8(v_QA1,v_QA1, l); + v_q22 = vfmul_vv_f32m8(v_QA2,v_QA2, l); + v_q33 = vfmul_vv_f32m8(v_QA3,v_QA3, l); + v_q01 = vfmul_vv_f32m8(v_QA0,v_QA1, l); + v_q02 = vfmul_vv_f32m8(v_QA0,v_QA2, l); + v_q03 = vfmul_vv_f32m8(v_QA0,v_QA3, l); + v_q12 = vfmul_vv_f32m8(v_QA1,v_QA2, l); + v_q13 = vfmul_vv_f32m8(v_QA1,v_QA3, l); + v_q23 = vfmul_vv_f32m8(v_QA2,v_QA3, l); + + v_xx = vfsub_vv_f32m8(vfadd_vv_f32m8(v_q00,v_q11, l),vfadd_vv_f32m8(v_q22,v_q33, l), l); + v_yy = vfadd_vv_f32m8(vfsub_vv_f32m8(v_q00,v_q11, l),vfsub_vv_f32m8(v_q22,v_q33, l), l); + v_zz = vfsub_vv_f32m8(vfsub_vv_f32m8(v_q00,v_q11, l),vfsub_vv_f32m8(v_q22,v_q33, l), l); + v_xy = vfmul_vf_f32m8(vfsub_vv_f32m8(v_q12,v_q03, l),2, l); + v_xz = vfmul_vf_f32m8(vfadd_vv_f32m8(v_q13,v_q02, l),2, l); + v_yx = vfmul_vf_f32m8(vfadd_vv_f32m8(v_q12,v_q03, l),2, l); + v_yz = vfmul_vf_f32m8(vfsub_vv_f32m8(v_q23,v_q01, l),2, l); + v_zx = vfmul_vf_f32m8(vfsub_vv_f32m8(v_q13,v_q02, l),2, l); + v_zy = vfmul_vf_f32m8(vfadd_vv_f32m8(v_q23,v_q01, l),2, l); + + vsse32_v_f32m8(pOUT,bstride_out,v_xx, l); + vsse32_v_f32m8(pOUT+1,bstride_out,v_xy, l); + vsse32_v_f32m8(pOUT+2,bstride_out,v_xz, l); + vsse32_v_f32m8(pOUT+3,bstride_out,v_yx, l); + vsse32_v_f32m8(pOUT+4,bstride_out,v_yy, l); + vsse32_v_f32m8(pOUT+5,bstride_out,v_yz, l); + vsse32_v_f32m8(pOUT+6,bstride_out,v_zx, l); + vsse32_v_f32m8(pOUT+7,bstride_out,v_zy, l); + vsse32_v_f32m8(pOUT+8,bstride_out,v_zz, l); + + pQA += l*4; + pOUT += l*9; + } +#else + for(uint32_t nb=0; nb < nbQuaternions; nb++) + { + float32_t q00 = SQ(pInputQuaternions[0 + nb * 4]); + float32_t q11 = SQ(pInputQuaternions[1 + nb * 4]); + float32_t q22 = SQ(pInputQuaternions[2 + nb * 4]); + float32_t q33 = SQ(pInputQuaternions[3 + nb * 4]); + float32_t q01 = pInputQuaternions[0 + nb * 4]*pInputQuaternions[1 + nb * 4]; + float32_t q02 = pInputQuaternions[0 + nb * 4]*pInputQuaternions[2 + nb * 4]; + float32_t q03 = pInputQuaternions[0 + nb * 4]*pInputQuaternions[3 + nb * 4]; + float32_t q12 = pInputQuaternions[1 + nb * 4]*pInputQuaternions[2 + nb * 4]; + float32_t q13 = pInputQuaternions[1 + nb * 4]*pInputQuaternions[3 + nb * 4]; + float32_t q23 = pInputQuaternions[2 + nb * 4]*pInputQuaternions[3 + nb * 4]; + + float32_t xx = q00 + q11 - q22 - q33; + float32_t yy = q00 - q11 + q22 - q33; + float32_t zz = q00 - q11 - q22 + q33; + float32_t xy = 2*(q12 - q03); + float32_t xz = 2*(q13 + q02); + float32_t yx = 2*(q12 + q03); + float32_t yz = 2*(q23 - q01); + float32_t zx = 2*(q13 - q02); + float32_t zy = 2*(q23 + q01); + + pOutputRotations[0 + nb * 9] = xx; pOutputRotations[1 + nb * 9] = xy; pOutputRotations[2 + nb * 9] = xz; + pOutputRotations[3 + nb * 9] = yx; pOutputRotations[4 + nb * 9] = yy; pOutputRotations[5 + nb * 9] = yz; + pOutputRotations[6 + nb * 9] = zx; pOutputRotations[7 + nb * 9] = zy; pOutputRotations[8 + nb * 9] = zz; + } +#endif +} + + +/** + @} end of QuatRot group + */ diff --git a/components/nmsis/dsp/src/QuaternionMathFunctions/riscv_quaternion_conjugate_f32.c b/components/nmsis/dsp/src/QuaternionMathFunctions/riscv_quaternion_conjugate_f32.c new file mode 100644 index 00000000..f57dd8f4 --- /dev/null +++ b/components/nmsis/dsp/src/QuaternionMathFunctions/riscv_quaternion_conjugate_f32.c @@ -0,0 +1,96 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_quaternion_conjugate_f32.c + * Description: Floating-point quaternion conjugate + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/quaternion_math_functions.h" +#include + +/** + @ingroup groupQuaternionMath + */ + +/** + @defgroup QuatConjugate Quaternion Conjugate + + Compute the conjugate of a quaternion. + */ + +/** + @addtogroup QuatConjugate + @{ + */ + +/** + @brief Floating-point quaternion conjugates. + @param[in] pInputQuaternions points to the input vector of quaternions + @param[out] pConjugateQuaternions points to the output vector of conjugate quaternions + @param[in] nbQuaternions number of quaternions in each vector + @return none + */ + +void riscv_quaternion_conjugate_f32(const float32_t *pInputQuaternions, + float32_t *pConjugateQuaternions, + uint32_t nbQuaternions) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = nbQuaternions; /* Loop counter */ + size_t l; + vfloat32m8_t v_x, v_y; + float32_t *pIN = pInputQuaternions; + float32_t *pOUT = pConjugateQuaternions; + ptrdiff_t bstride = 16; + for (; (l = vsetvl_e32m8(blkCnt)) > 0; blkCnt -= l) { + v_x = vlse32_v_f32m8(pIN,bstride, l); + vsse32_v_f32m8(pOUT,bstride,v_x, l); + v_x = vlse32_v_f32m8(pIN+1,bstride, l); + v_x = vfsgnjn_vv_f32m8(v_x,v_x, l); + vsse32_v_f32m8(pOUT+1,bstride,v_x, l); + v_x = vlse32_v_f32m8(pIN+2,bstride, l); + v_x = vfsgnjn_vv_f32m8(v_x,v_x, l); + vsse32_v_f32m8(pOUT+2,bstride,v_x, l); + v_x = vlse32_v_f32m8(pIN+3,bstride, l); + v_x = vfsgnjn_vv_f32m8(v_x,v_x, l); + vsse32_v_f32m8(pOUT+3,bstride,v_x, l); + pIN += l*4; + pOUT += l*4; + } +#else + for(uint32_t i=0; i < nbQuaternions; i++) + { + + pConjugateQuaternions[4 * i + 0] = pInputQuaternions[4 * i + 0]; + pConjugateQuaternions[4 * i + 1] = -pInputQuaternions[4 * i + 1]; + pConjugateQuaternions[4 * i + 2] = -pInputQuaternions[4 * i + 2]; + pConjugateQuaternions[4 * i + 3] = -pInputQuaternions[4 * i + 3]; + } +#endif +} + +/** + @} end of QuatConjugate group + */ diff --git a/components/nmsis/dsp/src/QuaternionMathFunctions/riscv_quaternion_inverse_f32.c b/components/nmsis/dsp/src/QuaternionMathFunctions/riscv_quaternion_inverse_f32.c new file mode 100644 index 00000000..b4c9621d --- /dev/null +++ b/components/nmsis/dsp/src/QuaternionMathFunctions/riscv_quaternion_inverse_f32.c @@ -0,0 +1,114 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_quaternion_inverse_f32.c + * Description: Floating-point quaternion inverse + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/quaternion_math_functions.h" +#include + +/** + @ingroup groupQuaternionMath + */ + +/** + @defgroup QuatInverse Quaternion Inverse + + Compute the inverse of a quaternion. + */ + +/** + @addtogroup QuatInverse + @{ + */ + +/** + @brief Floating-point quaternion inverse. + @param[in] pInputQuaternions points to the input vector of quaternions + @param[out] pInverseQuaternions points to the output vector of inverse quaternions + @param[in] nbQuaternions number of quaternions in each vector + @return none + */ + + +void riscv_quaternion_inverse_f32(const float32_t *pInputQuaternions, + float32_t *pInverseQuaternions, + uint32_t nbQuaternions) +{ + float32_t temp; +#if defined(RISCV_VECTOR) + uint32_t blkCnt = nbQuaternions; /* Loop counter */ + size_t l; + vfloat32m8_t v_x0, v_x1, v_x2, v_x3; + vfloat32m8_t v_temp; + float32_t *pIN = pInputQuaternions; + float32_t *pOUT = pInverseQuaternions; + ptrdiff_t bstride = 16; + for (; (l = vsetvl_e32m8(blkCnt)) > 0; blkCnt -= l) { + v_x0 = vlse32_v_f32m8(pIN,bstride, l); + v_x1 = vlse32_v_f32m8(pIN+1,bstride, l); + v_x2 = vlse32_v_f32m8(pIN+2,bstride, l); + v_x3 = vlse32_v_f32m8(pIN+3,bstride, l); + + v_temp = vfmul_vv_f32m8(v_x0,v_x0, l); + v_temp = vfmacc_vv_f32m8(v_temp,v_x1,v_x1, l); + v_temp = vfmacc_vv_f32m8(v_temp,v_x2,v_x2, l); + v_temp = vfmacc_vv_f32m8(v_temp,v_x3,v_x3, l); + + vsse32_v_f32m8(pOUT,bstride,vfdiv_vv_f32m8(v_x0,v_temp, l), l); + v_x1 = vfsgnjn_vv_f32m8(v_x1,v_x1, l); + v_x1 = vfdiv_vv_f32m8(v_x1,v_temp, l); + vsse32_v_f32m8(pOUT+1,bstride,v_x1, l); + v_x2 = vfsgnjn_vv_f32m8(v_x2,v_x2, l); + v_x2 = vfdiv_vv_f32m8(v_x2,v_temp, l); + vsse32_v_f32m8(pOUT+2,bstride,v_x2, l); + v_x3 = vfsgnjn_vv_f32m8(v_x3,v_x3, l); + v_x3 = vfdiv_vv_f32m8(v_x3,v_temp, l); + vsse32_v_f32m8(pOUT+3,bstride,v_x3, l); + + pIN += l*4; + pOUT += l*4; + } +#else + for(uint32_t i=0; i < nbQuaternions; i++) + { + + temp = SQ(pInputQuaternions[4 * i + 0]) + + SQ(pInputQuaternions[4 * i + 1]) + + SQ(pInputQuaternions[4 * i + 2]) + + SQ(pInputQuaternions[4 * i + 3]); + + pInverseQuaternions[4 * i + 0] = pInputQuaternions[4 * i + 0] / temp; + pInverseQuaternions[4 * i + 1] = -pInputQuaternions[4 * i + 1] / temp; + pInverseQuaternions[4 * i + 2] = -pInputQuaternions[4 * i + 2] / temp; + pInverseQuaternions[4 * i + 3] = -pInputQuaternions[4 * i + 3] / temp; + } +#endif +} + +/** + @} end of QuatInverse group + */ diff --git a/components/nmsis/dsp/src/QuaternionMathFunctions/riscv_quaternion_norm_f32.c b/components/nmsis/dsp/src/QuaternionMathFunctions/riscv_quaternion_norm_f32.c new file mode 100644 index 00000000..aab359ef --- /dev/null +++ b/components/nmsis/dsp/src/QuaternionMathFunctions/riscv_quaternion_norm_f32.c @@ -0,0 +1,100 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_quaternion_norm_f32.c + * Description: Floating-point quaternion Norm + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/quaternion_math_functions.h" +#include + +/** + @ingroup groupQuaternionMath + */ + +/** + @defgroup QuatNorm Quaternion Norm + + Compute the norm of a quaternion. + */ + +/** + @addtogroup QuatNorm + @{ + */ + +/** + @brief Floating-point quaternion Norm. + @param[in] pInputQuaternions points to the input vector of quaternions + @param[out] pNorms points to the output vector of norms + @param[in] nbQuaternions number of quaternions in the input vector + @return none + */ + + +void riscv_quaternion_norm_f32(const float32_t *pInputQuaternions, + float32_t *pNorms, + uint32_t nbQuaternions) +{ + float32_t temp; +#if defined(RISCV_VECTOR) + uint32_t blkCnt = nbQuaternions; /* Loop counter */ + size_t l; + vfloat32m8_t v_x0, v_x1, v_x2, v_x3; + vfloat32m8_t v_temp; + float32_t *pIN = pInputQuaternions; + float32_t *pOUT = pNorms; + ptrdiff_t bstride = 16; + for (; (l = vsetvl_e32m8(blkCnt)) > 0; blkCnt -= l) { + v_x0 = vlse32_v_f32m8(pIN,bstride, l); + v_x1 = vlse32_v_f32m8(pIN+1,bstride, l); + v_x2 = vlse32_v_f32m8(pIN+2,bstride, l); + v_x3 = vlse32_v_f32m8(pIN+3,bstride, l); + + v_temp = vfmul_vv_f32m8(v_x0,v_x0, l); + v_temp = vfmacc_vv_f32m8(v_temp,v_x1,v_x1, l); + v_temp = vfmacc_vv_f32m8(v_temp,v_x2,v_x2, l); + v_temp = vfmacc_vv_f32m8(v_temp,v_x3,v_x3, l); + + vse32_v_f32m8(pOUT,vfsqrt_v_f32m8(v_temp, l), l); + + pIN += l*4; + pOUT += l; + } +#else + for(uint32_t i=0; i < nbQuaternions; i++) + { + temp = SQ(pInputQuaternions[4 * i + 0]) + + SQ(pInputQuaternions[4 * i + 1]) + + SQ(pInputQuaternions[4 * i + 2]) + + SQ(pInputQuaternions[4 * i + 3]); + pNorms[i] = sqrtf(temp); + } +#endif +} + +/** + @} end of QuatNorm group + */ diff --git a/components/nmsis/dsp/src/QuaternionMathFunctions/riscv_quaternion_normalize_f32.c b/components/nmsis/dsp/src/QuaternionMathFunctions/riscv_quaternion_normalize_f32.c new file mode 100644 index 00000000..2b3f63f8 --- /dev/null +++ b/components/nmsis/dsp/src/QuaternionMathFunctions/riscv_quaternion_normalize_f32.c @@ -0,0 +1,112 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_quaternion_normalize_f32.c + * Description: Floating-point quaternion normalization + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/quaternion_math_functions.h" +#include + +/** + @ingroup groupQuaternionMath + */ + +/** + @defgroup QuatNormalized Quaternion normalization + + Compute a normalized quaternion. + */ + +/** + @addtogroup QuatNormalized + @{ + */ + +/** + @brief Floating-point normalization of quaternions. + @param[in] pInputQuaternions points to the input vector of quaternions + @param[out] pNormalizedQuaternions points to the output vector of normalized quaternions + @param[in] nbQuaternions number of quaternions in each vector + @return none + */ + +void riscv_quaternion_normalize_f32(const float32_t *pInputQuaternions, + float32_t *pNormalizedQuaternions, + uint32_t nbQuaternions) +{ + float32_t temp; +#if defined(RISCV_VECTOR) + uint32_t blkCnt = nbQuaternions; /* Loop counter */ + size_t l; + vfloat32m8_t v_x0, v_x1, v_x2, v_x3; + vfloat32m8_t v_temp; + float32_t *pIN = pInputQuaternions; + float32_t *pOUT = pNormalizedQuaternions; + ptrdiff_t bstride = 16; + for (; (l = vsetvl_e32m8(blkCnt)) > 0; blkCnt -= l) { + v_x0 = vlse32_v_f32m8(pIN,bstride, l); + v_x1 = vlse32_v_f32m8(pIN+1,bstride, l); + v_x2 = vlse32_v_f32m8(pIN+2,bstride, l); + v_x3 = vlse32_v_f32m8(pIN+3,bstride, l); + + v_temp = vfmul_vv_f32m8(v_x0,v_x0, l); + v_temp = vfmacc_vv_f32m8(v_temp,v_x1,v_x1, l); + v_temp = vfmacc_vv_f32m8(v_temp,v_x2,v_x2, l); + v_temp = vfmacc_vv_f32m8(v_temp,v_x3,v_x3, l); + + v_temp = vfsqrt_v_f32m8(v_temp, l); + + vsse32_v_f32m8(pOUT,bstride,vfdiv_vv_f32m8(v_x0,v_temp, l), l); + v_x1 = vfdiv_vv_f32m8(v_x1,v_temp, l); + vsse32_v_f32m8(pOUT+1,bstride,v_x1, l); + v_x2 = vfdiv_vv_f32m8(v_x2,v_temp, l); + vsse32_v_f32m8(pOUT+2,bstride,v_x2, l); + v_x3 = vfdiv_vv_f32m8(v_x3,v_temp, l); + vsse32_v_f32m8(pOUT+3,bstride,v_x3, l); + + pIN += l*4; + pOUT += l*4; + } +#else + for(uint32_t i=0; i < nbQuaternions; i++) + { + temp = SQ(pInputQuaternions[4 * i + 0]) + + SQ(pInputQuaternions[4 * i + 1]) + + SQ(pInputQuaternions[4 * i + 2]) + + SQ(pInputQuaternions[4 * i + 3]); + temp = sqrtf(temp); + + pNormalizedQuaternions[4 * i + 0] = pInputQuaternions[4 * i + 0] / temp; + pNormalizedQuaternions[4 * i + 1] = pInputQuaternions[4 * i + 1] / temp; + pNormalizedQuaternions[4 * i + 2] = pInputQuaternions[4 * i + 2] / temp; + pNormalizedQuaternions[4 * i + 3] = pInputQuaternions[4 * i + 3] / temp; + } +#endif +} + +/** + @} end of QuatNormalized group + */ diff --git a/components/nmsis/dsp/src/QuaternionMathFunctions/riscv_quaternion_product_f32.c b/components/nmsis/dsp/src/QuaternionMathFunctions/riscv_quaternion_product_f32.c new file mode 100644 index 00000000..09d87ffc --- /dev/null +++ b/components/nmsis/dsp/src/QuaternionMathFunctions/riscv_quaternion_product_f32.c @@ -0,0 +1,137 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_quaternion_product_f32.c + * Description: Floating-point quaternion product + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/quaternion_math_functions.h" +#include + +/** + @ingroup groupQuaternionMath + */ + +/** + @defgroup QuatProd Quaternion Product + + Compute the product of quaternions. + */ + +/** + @ingroup QuatProd + */ + +/** + @defgroup QuatProdVect Elementwise Quaternion Product + + Compute the elementwise product of quaternions. + */ + +/** + @addtogroup QuatProdVect + @{ + */ + +/** + @brief Floating-point elementwise product two quaternions. + @param[in] qa first array of quaternions + @param[in] qb second array of quaternions + @param[out] qr elementwise product of quaternions + @param[in] nbQuaternions number of quaternions in the array + @return none + */ + + +void riscv_quaternion_product_f32(const float32_t *qa, + const float32_t *qb, + float32_t *qr, + uint32_t nbQuaternions) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = nbQuaternions; /* Loop counter */ + size_t l; + vfloat32m8_t v_QA0, v_QA1, v_QA2, v_QA3; + vfloat32m8_t v_QB0, v_QB1, v_QB2, v_QB3; + vfloat32m8_t v_QR0, v_QR1, v_QR2, v_QR3; + vfloat32m8_t v_temp; + float32_t *pQA = qa; + float32_t *pQB = qb; + float32_t *pQR = qr; + ptrdiff_t bstride = 16; + for (; (l = vsetvl_e32m8(blkCnt)) > 0; blkCnt -= l) { + v_QA0 = vlse32_v_f32m8(pQA,bstride, l); + v_QA1 = vlse32_v_f32m8(pQA+1,bstride, l); + v_QA2 = vlse32_v_f32m8(pQA+2,bstride, l); + v_QA3 = vlse32_v_f32m8(pQA+3,bstride, l); + + v_QB0 = vlse32_v_f32m8(pQB,bstride, l); + v_QB1 = vlse32_v_f32m8(pQB+1,bstride, l); + v_QB2 = vlse32_v_f32m8(pQB+2,bstride, l); + v_QB3 = vlse32_v_f32m8(pQB+3,bstride, l); + + v_QR0 = vfmul_vv_f32m8(v_QA0,v_QB0, l); + v_QR0 = vfnmsac_vv_f32m8(v_QR0,v_QA1,v_QB1, l); + v_QR0 = vfnmsac_vv_f32m8(v_QR0,v_QA2,v_QB2, l); + v_QR0 = vfnmsac_vv_f32m8(v_QR0,v_QA3,v_QB3, l); + vsse32_v_f32m8(pQR,bstride,v_QR0, l); + + v_QR1 = vfmul_vv_f32m8(v_QA0,v_QB1, l); + v_QR1 = vfmacc_vv_f32m8(v_QR1,v_QA1,v_QB0, l); + v_QR1 = vfmacc_vv_f32m8(v_QR1,v_QA2,v_QB3, l); + v_QR1 = vfnmsac_vv_f32m8(v_QR1,v_QA3,v_QB2, l); + vsse32_v_f32m8(pQR+1,bstride,v_QR1, l); + + v_QR2 = vfmul_vv_f32m8(v_QA0,v_QB2, l); + v_QR2 = vfmacc_vv_f32m8(v_QR2,v_QA2,v_QB0, l); + v_QR2 = vfmacc_vv_f32m8(v_QR2,v_QA3,v_QB1, l); + v_QR2 = vfnmsac_vv_f32m8(v_QR2,v_QA1,v_QB3, l); + vsse32_v_f32m8(pQR+2,bstride,v_QR2, l); + + v_QR3 = vfmul_vv_f32m8(v_QA0,v_QB3, l); + v_QR3 = vfmacc_vv_f32m8(v_QR3,v_QA3,v_QB0, l); + v_QR3 = vfmacc_vv_f32m8(v_QR3,v_QA1,v_QB2, l); + v_QR3 = vfnmsac_vv_f32m8(v_QR3,v_QA2,v_QB1, l); + vsse32_v_f32m8(pQR+3,bstride,v_QR3, l); + + pQA += l*4; + pQB += l*4; + pQR += l*4; + } +#else + for(uint32_t i=0; i < nbQuaternions; i++) + { + riscv_quaternion_product_single_f32(qa, qb, qr); + + qa += 4; + qb += 4; + qr += 4; + } +#endif +} + +/** + @} end of QuatProdVect group + */ diff --git a/components/nmsis/dsp/src/QuaternionMathFunctions/riscv_quaternion_product_single_f32.c b/components/nmsis/dsp/src/QuaternionMathFunctions/riscv_quaternion_product_single_f32.c new file mode 100644 index 00000000..04d2e1d2 --- /dev/null +++ b/components/nmsis/dsp/src/QuaternionMathFunctions/riscv_quaternion_product_single_f32.c @@ -0,0 +1,69 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_quaternion_product_single_f32.c + * Description: Floating-point quaternion product + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/quaternion_math_functions.h" +#include + + +/** + @ingroup QuatProd + */ + +/** + @defgroup QuatProdSingle Quaternion Product + + Compute the product of two quaternions. + */ + +/** + @addtogroup QuatProdSingle + @{ + */ + +/** + @brief Floating-point product of two quaternions. + @param[in] qa first quaternion + @param[in] qb second quaternion + @param[out] qr product of two quaternions + @return none + */ + +void riscv_quaternion_product_single_f32(const float32_t *qa, + const float32_t *qb, + float32_t *qr) +{ + qr[0] = qa[0] * qb[0] - qa[1] * qb[1] - qa[2] * qb[2] - qa[3] * qb[3]; + qr[1] = qa[0] * qb[1] + qa[1] * qb[0] + qa[2] * qb[3] - qa[3] * qb[2]; + qr[2] = qa[0] * qb[2] + qa[2] * qb[0] + qa[3] * qb[1] - qa[1] * qb[3]; + qr[3] = qa[0] * qb[3] + qa[3] * qb[0] + qa[1] * qb[2] - qa[2] * qb[1]; +} + +/** + @} end of QuatProdSingle group + */ diff --git a/components/nmsis/dsp/src/QuaternionMathFunctions/riscv_rotation2quaternion_f32.c b/components/nmsis/dsp/src/QuaternionMathFunctions/riscv_rotation2quaternion_f32.c new file mode 100644 index 00000000..119fdd52 --- /dev/null +++ b/components/nmsis/dsp/src/QuaternionMathFunctions/riscv_rotation2quaternion_f32.c @@ -0,0 +1,121 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_rotation2quaternion_f32.c + * Description: Floating-point rotation to quaternion conversion + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/quaternion_math_functions.h" +#include + +#define RI(x,y) r[(3*(x) + (y))] + + +/** + @ingroup QuatConv + */ + +/** + @defgroup RotQuat Rotation to Quaternion + + Conversions from rotation to quaternion. + */ + +/** + @addtogroup RotQuat + @{ + */ + +/** + * @brief Conversion of a rotation matrix to an equivalent quaternion. + * @param[in] pInputRotations points to an array 3x3 rotation matrix (in row order) + * @param[out] pOutputQuaternions points to an array quaternions + * @param[in] nbQuaternions number of quaternions in the array + * @return none. + * + * q and -q are representing the same rotation. This ambiguity must be taken into + * account when using the output of this function. + * + */ + +void riscv_rotation2quaternion_f32(const float32_t *pInputRotations, + float32_t *pOutputQuaternions, + uint32_t nbQuaternions) +{ + for(uint32_t nb=0; nb < nbQuaternions; nb++) + { + const float32_t *r=&pInputRotations[nb*9]; + float32_t *q=&pOutputQuaternions[nb*4]; + + float32_t trace = RI(0,0) + RI(1,1) + RI(2,2); + + float32_t doubler; + float32_t s; + + + + if (trace > 0) + { + doubler = sqrtf(trace + 1.0) * 2; // invs=4*qw + s = 1.0 / doubler; + q[0] = 0.25 * doubler; + q[1] = (RI(2,1) - RI(1,2)) * s; + q[2] = (RI(0,2) - RI(2,0)) * s; + q[3] = (RI(1,0) - RI(0,1)) * s; + } + else if ((RI(0,0) > RI(1,1)) && (RI(0,0) > RI(2,2)) ) + { + doubler = sqrtf(1.0 + RI(0,0) - RI(1,1) - RI(2,2)) * 2; // invs=4*qx + s = 1.0 / doubler; + q[0] = (RI(2,1) - RI(1,2)) * s; + q[1] = 0.25 * doubler; + q[2] = (RI(0,1) + RI(1,0)) * s; + q[3] = (RI(0,2) + RI(2,0)) * s; + } + else if (RI(1,1) > RI(2,2)) + { + doubler = sqrtf(1.0 + RI(1,1) - RI(0,0) - RI(2,2)) * 2; // invs=4*qy + s = 1.0 / doubler; + q[0] = (RI(0,2) - RI(2,0)) * s; + q[1] = (RI(0,1) + RI(1,0)) * s; + q[2] = 0.25 * doubler; + q[3] = (RI(1,2) + RI(2,1)) * s; + } + else + { + doubler = sqrtf(1.0 + RI(2,2) - RI(0,0) - RI(1,1)) * 2; // invs=4*qz + s = 1.0 / doubler; + q[0] = (RI(1,0) - RI(0,1)) * s; + q[1] = (RI(0,2) + RI(2,0)) * s; + q[2] = (RI(1,2) + RI(2,1)) * s; + q[3] = 0.25 * doubler; + } + + } +} + +/** + @} end of RotQuat group + */ diff --git a/components/nmsis/dsp/src/SVMFunctions/SVMFunctions.c b/components/nmsis/dsp/src/SVMFunctions/SVMFunctions.c new file mode 100644 index 00000000..edd16a3b --- /dev/null +++ b/components/nmsis/dsp/src/SVMFunctions/SVMFunctions.c @@ -0,0 +1,37 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: BayesFunctions.c + * Description: Combination of all SVM function source files. + * + * $Date: 16. March 2020 + * $Revision: V1.0.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2020 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "riscv_svm_linear_init_f32.c" +#include "riscv_svm_linear_predict_f32.c" +#include "riscv_svm_polynomial_init_f32.c" +#include "riscv_svm_polynomial_predict_f32.c" +#include "riscv_svm_rbf_init_f32.c" +#include "riscv_svm_rbf_predict_f32.c" +#include "riscv_svm_sigmoid_init_f32.c" +#include "riscv_svm_sigmoid_predict_f32.c" diff --git a/components/nmsis/dsp/src/SVMFunctions/SVMFunctionsF16.c b/components/nmsis/dsp/src/SVMFunctions/SVMFunctionsF16.c new file mode 100644 index 00000000..ad72b838 --- /dev/null +++ b/components/nmsis/dsp/src/SVMFunctions/SVMFunctionsF16.c @@ -0,0 +1,37 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: BayesFunctions.c + * Description: Combination of all SVM function source files. + * + * $Date: 16. March 2020 + * $Revision: V1.0.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2020 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "riscv_svm_linear_init_f16.c" +#include "riscv_svm_linear_predict_f16.c" +#include "riscv_svm_polynomial_init_f16.c" +#include "riscv_svm_polynomial_predict_f16.c" +#include "riscv_svm_rbf_init_f16.c" +#include "riscv_svm_rbf_predict_f16.c" +#include "riscv_svm_sigmoid_init_f16.c" +#include "riscv_svm_sigmoid_predict_f16.c" diff --git a/components/nmsis/dsp/src/SVMFunctions/riscv_svm_linear_init_f16.c b/components/nmsis/dsp/src/SVMFunctions/riscv_svm_linear_init_f16.c new file mode 100644 index 00000000..4209e9c1 --- /dev/null +++ b/components/nmsis/dsp/src/SVMFunctions/riscv_svm_linear_init_f16.c @@ -0,0 +1,99 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_svm_linear_init_f16.c + * Description: SVM Linear Instance Initialization + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/svm_functions_f16.h" + +#if defined(RISCV_FLOAT16_SUPPORTED) + +#include +#include + +/** + * @defgroup groupSVM SVM Functions + * + */ + +/** + @ingroup groupSVM + */ + +/** + @defgroup linearsvm Linear SVM + + Linear SVM classifier + */ + +/** + * @addtogroup linearsvm + * @{ + */ + + +/** + * @brief SVM linear instance init function + * + * Classes are integer used as output of the function (instead of having -1,1 + * as class values). + * + * @param[in] S Parameters for the SVM function + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @return none. + * + */ + + +void riscv_svm_linear_init_f16(riscv_svm_linear_instance_f16 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float16_t intercept, + const float16_t *dualCoefficients, + const float16_t *supportVectors, + const int32_t *classes) +{ + S->nbOfSupportVectors = nbOfSupportVectors; + S->vectorDimension = vectorDimension; + S->intercept = intercept; + S->dualCoefficients = dualCoefficients; + S->supportVectors = supportVectors; + S->classes = classes; +} + + + +/** + * @} end of linearsvm group + */ + +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ + diff --git a/components/nmsis/dsp/src/SVMFunctions/riscv_svm_linear_init_f32.c b/components/nmsis/dsp/src/SVMFunctions/riscv_svm_linear_init_f32.c new file mode 100644 index 00000000..f45568ad --- /dev/null +++ b/components/nmsis/dsp/src/SVMFunctions/riscv_svm_linear_init_f32.c @@ -0,0 +1,93 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_svm_linear_init_f32.c + * Description: SVM Linear Instance Initialization + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/svm_functions.h" +#include +#include + +/** + * @defgroup groupSVM SVM Functions + * + */ + +/** + @ingroup groupSVM + */ + +/** + @defgroup linearsvm Linear SVM + + Linear SVM classifier + */ + +/** + * @addtogroup linearsvm + * @{ + */ + + +/** + * @brief SVM linear instance init function + * + * Classes are integer used as output of the function (instead of having -1,1 + * as class values). + * + * @param[in] S Parameters for the SVM function + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @return none. + * + */ + + +void riscv_svm_linear_init_f32(riscv_svm_linear_instance_f32 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float32_t intercept, + const float32_t *dualCoefficients, + const float32_t *supportVectors, + const int32_t *classes) +{ + S->nbOfSupportVectors = nbOfSupportVectors; + S->vectorDimension = vectorDimension; + S->intercept = intercept; + S->dualCoefficients = dualCoefficients; + S->supportVectors = supportVectors; + S->classes = classes; +} + + + +/** + * @} end of linearsvm group + */ diff --git a/components/nmsis/dsp/src/SVMFunctions/riscv_svm_linear_predict_f16.c b/components/nmsis/dsp/src/SVMFunctions/riscv_svm_linear_predict_f16.c new file mode 100644 index 00000000..65d41f63 --- /dev/null +++ b/components/nmsis/dsp/src/SVMFunctions/riscv_svm_linear_predict_f16.c @@ -0,0 +1,79 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_svm_linear_predict_f16.c + * Description: SVM Linear Classifier + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/svm_functions_f16.h" + +#if defined(RISCV_FLOAT16_SUPPORTED) + +#include +#include + + +/** + * @addtogroup linearsvm + * @{ + */ + + +/** + * @brief SVM linear prediction + * @param[in] S Pointer to an instance of the linear SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult Decision value + * @return none. + * + */ +void riscv_svm_linear_predict_f16( + const riscv_svm_linear_instance_f16 *S, + const float16_t * in, + int32_t * pResult) +{ + _Float16 sum=S->intercept; + _Float16 dot=0; + uint32_t i,j; + const float16_t *pSupport = S->supportVectors; + + for(i=0; i < S->nbOfSupportVectors; i++) + { + dot=0; + for(j=0; j < S->vectorDimension; j++) + { + dot = dot + in[j]* *pSupport++; + } + sum += S->dualCoefficients[i] * dot; + } + *pResult=S->classes[STEP(sum)]; +} + +/** + * @} end of linearsvm group + */ + +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ + diff --git a/components/nmsis/dsp/src/SVMFunctions/riscv_svm_linear_predict_f32.c b/components/nmsis/dsp/src/SVMFunctions/riscv_svm_linear_predict_f32.c new file mode 100644 index 00000000..11c32563 --- /dev/null +++ b/components/nmsis/dsp/src/SVMFunctions/riscv_svm_linear_predict_f32.c @@ -0,0 +1,109 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_svm_linear_predict_f32.c + * Description: SVM Linear Classifier + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/svm_functions.h" +#include +#include + + +/** + * @addtogroup linearsvm + * @{ + */ + + +/** + * @brief SVM linear prediction + * @param[in] S Pointer to an instance of the linear SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult Decision value + * @return none. + * + */ +void riscv_svm_linear_predict_f32( + const riscv_svm_linear_instance_f32 *S, + const float32_t * in, + int32_t * pResult) +{ +#if defined(RISCV_VECTOR) + + float32_t dot = 0; + float32_t sum = S->intercept; + const float32_t *pSupport = S->supportVectors; + uint32_t blkCnt = S->vectorDimension; + uint32_t vectorBlkCnt = S->nbOfSupportVectors; + const float32_t *pDualCoefs = S->dualCoefficients; + size_t l; + size_t l2; + vfloat32m8_t v_in, v_support, v_dualcoefs; + vfloat32m1_t v_dot; /* init v_dot data */ + uint32_t i; + const float32_t * pIn = in; + for(i=0; i < S->nbOfSupportVectors; i++) + { + l = vsetvl_e32m1(1); + blkCnt = S->vectorDimension; + v_dot = vfmv_s_f_f32m1(v_dot, 0, l); + in = pIn; + for (; (l = vsetvl_e32m8(blkCnt)) > 0; blkCnt -= l) + { + v_in = vle32_v_f32m8(in, l); + v_support = vle32_v_f32m8(pSupport, l); + v_dot = vfredsum_vs_f32m8_f32m1(v_dot, vfmul_vv_f32m8(v_in, v_support, l), v_dot, l); + in += l; + pSupport += l; + } + l = vsetvl_e32m1(1); + dot = vfmv_f_s_f32m1_f32(v_dot); + sum += S->dualCoefficients[i] * dot; + } + *pResult=S->classes[STEP(sum)]; + +#else + float32_t sum=S->intercept; + float32_t dot=0; + uint32_t i,j; + const float32_t *pSupport = S->supportVectors; + + for(i=0; i < S->nbOfSupportVectors; i++) + { + dot=0; + for(j=0; j < S->vectorDimension; j++) + { + dot = dot + in[j]* *pSupport++; + } + sum += S->dualCoefficients[i] * dot; + } + *pResult=S->classes[STEP(sum)]; +#endif /* defined(RISCV_VECTOR) */ +} + +/** + * @} end of linearsvm group + */ diff --git a/components/nmsis/dsp/src/SVMFunctions/riscv_svm_polynomial_init_f16.c b/components/nmsis/dsp/src/SVMFunctions/riscv_svm_polynomial_init_f16.c new file mode 100644 index 00000000..c20597c4 --- /dev/null +++ b/components/nmsis/dsp/src/SVMFunctions/riscv_svm_polynomial_init_f16.c @@ -0,0 +1,104 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_svm_polynomial_init_f16.c + * Description: SVM Polynomial Instance Initialization + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/svm_functions_f16.h" + +#if defined(RISCV_FLOAT16_SUPPORTED) + +#include +#include + +/** + @ingroup groupSVM + */ + +/** + @defgroup polysvm Polynomial SVM + + Polynomial SVM classifier + */ + +/** + * @addtogroup polysvm + * @{ + */ + + +/** + * @brief SVM polynomial instance init function + * + * Classes are integer used as output of the function (instead of having -1,1 + * as class values). + * + * @param[in] S points to an instance of the polynomial SVM structure. + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @param[in] degree Polynomial degree + * @param[in] coef0 coeff0 (scikit-learn terminology) + * @param[in] gamma gamma (scikit-learn terminology) + * @return none. + * + */ + + +void riscv_svm_polynomial_init_f16(riscv_svm_polynomial_instance_f16 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float16_t intercept, + const float16_t *dualCoefficients, + const float16_t *supportVectors, + const int32_t *classes, + int32_t degree, + float16_t coef0, + float16_t gamma + ) +{ + S->nbOfSupportVectors = nbOfSupportVectors; + S->vectorDimension = vectorDimension; + S->intercept = intercept; + S->dualCoefficients = dualCoefficients; + S->supportVectors = supportVectors; + S->classes = classes; + S->degree = degree; + S->coef0 = coef0; + S->gamma = gamma; +} + + + +/** + * @} end of polysvm group + */ + +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ + diff --git a/components/nmsis/dsp/src/SVMFunctions/riscv_svm_polynomial_init_f32.c b/components/nmsis/dsp/src/SVMFunctions/riscv_svm_polynomial_init_f32.c new file mode 100644 index 00000000..2b150ff8 --- /dev/null +++ b/components/nmsis/dsp/src/SVMFunctions/riscv_svm_polynomial_init_f32.c @@ -0,0 +1,98 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_svm_polynomial_init_f32.c + * Description: SVM Polynomial Instance Initialization + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/svm_functions.h" +#include +#include + +/** + @ingroup groupSVM + */ + +/** + @defgroup polysvm Polynomial SVM + + Polynomial SVM classifier + */ + +/** + * @addtogroup polysvm + * @{ + */ + + +/** + * @brief SVM polynomial instance init function + * + * Classes are integer used as output of the function (instead of having -1,1 + * as class values). + * + * @param[in] S points to an instance of the polynomial SVM structure. + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @param[in] degree Polynomial degree + * @param[in] coef0 coeff0 (scikit-learn terminology) + * @param[in] gamma gamma (scikit-learn terminology) + * @return none. + * + */ + + +void riscv_svm_polynomial_init_f32(riscv_svm_polynomial_instance_f32 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float32_t intercept, + const float32_t *dualCoefficients, + const float32_t *supportVectors, + const int32_t *classes, + int32_t degree, + float32_t coef0, + float32_t gamma + ) +{ + S->nbOfSupportVectors = nbOfSupportVectors; + S->vectorDimension = vectorDimension; + S->intercept = intercept; + S->dualCoefficients = dualCoefficients; + S->supportVectors = supportVectors; + S->classes = classes; + S->degree = degree; + S->coef0 = coef0; + S->gamma = gamma; +} + + + +/** + * @} end of polysvm group + */ diff --git a/components/nmsis/dsp/src/SVMFunctions/riscv_svm_polynomial_predict_f16.c b/components/nmsis/dsp/src/SVMFunctions/riscv_svm_polynomial_predict_f16.c new file mode 100644 index 00000000..1d499a45 --- /dev/null +++ b/components/nmsis/dsp/src/SVMFunctions/riscv_svm_polynomial_predict_f16.c @@ -0,0 +1,82 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_svm_polynomial_predict_f16.c + * Description: SVM Polynomial Classifier + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/svm_functions_f16.h" + +#if defined(RISCV_FLOAT16_SUPPORTED) + +#include +#include + + +/** + * @addtogroup polysvm + * @{ + */ + + +/** + * @brief SVM polynomial prediction + * @param[in] S Pointer to an instance of the polynomial SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult Decision value + * @return none. + * + */ + +void riscv_svm_polynomial_predict_f16( + const riscv_svm_polynomial_instance_f16 *S, + const float16_t * in, + int32_t * pResult) +{ + _Float16 sum=S->intercept; + _Float16 dot=0; + uint32_t i,j; + const float16_t *pSupport = S->supportVectors; + + for(i=0; i < S->nbOfSupportVectors; i++) + { + dot=0; + for(j=0; j < S->vectorDimension; j++) + { + dot = dot + (_Float16)in[j]* (_Float16)*pSupport++; + } + sum += S->dualCoefficients[i] * (_Float16)riscv_exponent_f16(S->gamma * dot + S->coef0, S->degree); + } + + *pResult=S->classes[STEP(sum)]; +} + + +/** + * @} end of polysvm group + */ + +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ + diff --git a/components/nmsis/dsp/src/SVMFunctions/riscv_svm_polynomial_predict_f32.c b/components/nmsis/dsp/src/SVMFunctions/riscv_svm_polynomial_predict_f32.c new file mode 100644 index 00000000..ba45d8fa --- /dev/null +++ b/components/nmsis/dsp/src/SVMFunctions/riscv_svm_polynomial_predict_f32.c @@ -0,0 +1,109 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_svm_polynomial_predict_f32.c + * Description: SVM Polynomial Classifier + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/svm_functions.h" +#include +#include + + +/** + * @addtogroup polysvm + * @{ + */ + + +/** + * @brief SVM polynomial prediction + * @param[in] S Pointer to an instance of the polynomial SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult Decision value + * @return none. + * + */ + +void riscv_svm_polynomial_predict_f32( + const riscv_svm_polynomial_instance_f32 *S, + const float32_t * in, + int32_t * pResult) +{ +#if defined(RISCV_VECTOR) + + float32_t dot = 0; + float32_t sum = S->intercept; + const float32_t *pSupport = S->supportVectors; + uint32_t blkCnt = S->vectorDimension; + uint32_t blkCnt_back = S->vectorDimension; + size_t l; + size_t l2; + vfloat32m8_t v_in, v_support; + vfloat32m1_t v_dot; + uint32_t i; + const float32_t * pIn = in; + for(i=0; i < S->nbOfSupportVectors; i++) + { + l = vsetvl_e32m1(1); + v_dot = vfmv_s_f_f32m1(v_dot, 0, l); + in = pIn; + for (blkCnt = blkCnt_back; (l = vsetvl_e32m8(blkCnt)) > 0; blkCnt -= l) + { + v_in = vle32_v_f32m8(in, l); + v_support = vle32_v_f32m8(pSupport, l); + v_dot = vfredsum_vs_f32m8_f32m1(v_dot, vfmul_vv_f32m8(v_in, v_support, l), v_dot, l); + in += l; + pSupport += l; + } + vsetvl_e32m1(1); + dot = vfmv_f_s_f32m1_f32(v_dot); + sum += S->dualCoefficients[i] * riscv_exponent_f32(S->gamma * dot + S->coef0, S->degree); + } + *pResult=S->classes[STEP(sum)]; +#else + float32_t sum=S->intercept; + float32_t dot=0; + uint32_t i,j; + const float32_t *pSupport = S->supportVectors; + + for(i=0; i < S->nbOfSupportVectors; i++) + { + dot=0; + for(j=0; j < S->vectorDimension; j++) + { + dot = dot + in[j]* *pSupport++; + } + sum += S->dualCoefficients[i] * riscv_exponent_f32(S->gamma * dot + S->coef0, S->degree); + } + + *pResult=S->classes[STEP(sum)]; +#endif /* defined(RISCV_VECTOR) */ +} + + +/** + * @} end of polysvm group + */ diff --git a/components/nmsis/dsp/src/SVMFunctions/riscv_svm_rbf_init_f16.c b/components/nmsis/dsp/src/SVMFunctions/riscv_svm_rbf_init_f16.c new file mode 100644 index 00000000..c1c4c1d4 --- /dev/null +++ b/components/nmsis/dsp/src/SVMFunctions/riscv_svm_rbf_init_f16.c @@ -0,0 +1,98 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_svm_rbf_init_f16.c + * Description: SVM Radial Basis Function Instance Initialization + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/svm_functions_f16.h" + +#if defined(RISCV_FLOAT16_SUPPORTED) + +#include +#include + +/** + @ingroup groupSVM + */ + +/** + @defgroup rbfsvm RBF SVM + + RBF SVM classifier + */ + + +/** + * @addtogroup rbfsvm + * @{ + */ + + +/** + * @brief SVM radial basis function instance init function + * + * Classes are integer used as output of the function (instead of having -1,1 + * as class values). + * + * @param[in] S points to an instance of the polynomial SVM structure. + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @param[in] gamma gamma (scikit-learn terminology) + * @return none. + * + */ + +void riscv_svm_rbf_init_f16(riscv_svm_rbf_instance_f16 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float16_t intercept, + const float16_t *dualCoefficients, + const float16_t *supportVectors, + const int32_t *classes, + float16_t gamma + ) +{ + S->nbOfSupportVectors = nbOfSupportVectors; + S->vectorDimension = vectorDimension; + S->intercept = intercept; + S->dualCoefficients = dualCoefficients; + S->supportVectors = supportVectors; + S->classes = classes; + S->gamma = gamma; +} + + + +/** + * @} end of rbfsvm group + */ + +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ + diff --git a/components/nmsis/dsp/src/SVMFunctions/riscv_svm_rbf_init_f32.c b/components/nmsis/dsp/src/SVMFunctions/riscv_svm_rbf_init_f32.c new file mode 100644 index 00000000..53489b24 --- /dev/null +++ b/components/nmsis/dsp/src/SVMFunctions/riscv_svm_rbf_init_f32.c @@ -0,0 +1,92 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_svm_rbf_init_f32.c + * Description: SVM Radial Basis Function Instance Initialization + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/svm_functions.h" +#include +#include + +/** + @ingroup groupSVM + */ + +/** + @defgroup rbfsvm RBF SVM + + RBF SVM classifier + */ + + +/** + * @addtogroup rbfsvm + * @{ + */ + + +/** + * @brief SVM radial basis function instance init function + * + * Classes are integer used as output of the function (instead of having -1,1 + * as class values). + * + * @param[in] S points to an instance of the polynomial SVM structure. + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @param[in] gamma gamma (scikit-learn terminology) + * @return none. + * + */ + +void riscv_svm_rbf_init_f32(riscv_svm_rbf_instance_f32 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float32_t intercept, + const float32_t *dualCoefficients, + const float32_t *supportVectors, + const int32_t *classes, + float32_t gamma + ) +{ + S->nbOfSupportVectors = nbOfSupportVectors; + S->vectorDimension = vectorDimension; + S->intercept = intercept; + S->dualCoefficients = dualCoefficients; + S->supportVectors = supportVectors; + S->classes = classes; + S->gamma = gamma; +} + + + +/** + * @} end of rbfsvm group + */ diff --git a/components/nmsis/dsp/src/SVMFunctions/riscv_svm_rbf_predict_f16.c b/components/nmsis/dsp/src/SVMFunctions/riscv_svm_rbf_predict_f16.c new file mode 100644 index 00000000..f3931b9d --- /dev/null +++ b/components/nmsis/dsp/src/SVMFunctions/riscv_svm_rbf_predict_f16.c @@ -0,0 +1,82 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_svm_rbf_predict_f16.c + * Description: SVM Radial Basis Function Classifier + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/svm_functions_f16.h" + +#if defined(RISCV_FLOAT16_SUPPORTED) + +#include +#include + + +/** + * @addtogroup rbfsvm + * @{ + */ + + +/** + * @brief SVM rbf prediction + * @param[in] S Pointer to an instance of the rbf SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult decision value + * @return none. + * + */ + +void riscv_svm_rbf_predict_f16( + const riscv_svm_rbf_instance_f16 *S, + const float16_t * in, + int32_t * pResult) +{ + _Float16 sum=S->intercept; + _Float16 dot=00.f16; + uint32_t i,j; + const float16_t *pSupport = S->supportVectors; + + for(i=0; i < S->nbOfSupportVectors; i++) + { + dot=0.0f16; + for(j=0; j < S->vectorDimension; j++) + { + dot = dot + SQ((_Float16)in[j] - (_Float16) *pSupport); + pSupport++; + } + sum += (_Float16)S->dualCoefficients[i] * (_Float16)expf(-(_Float16)S->gamma * dot); + } + *pResult=S->classes[STEP(sum)]; +} + + +/** + * @} end of rbfsvm group + */ + +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ + diff --git a/components/nmsis/dsp/src/SVMFunctions/riscv_svm_rbf_predict_f32.c b/components/nmsis/dsp/src/SVMFunctions/riscv_svm_rbf_predict_f32.c new file mode 100644 index 00000000..f1593c02 --- /dev/null +++ b/components/nmsis/dsp/src/SVMFunctions/riscv_svm_rbf_predict_f32.c @@ -0,0 +1,109 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_svm_rbf_predict_f32.c + * Description: SVM Radial Basis Function Classifier + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/svm_functions.h" +#include +#include + + +/** + * @addtogroup rbfsvm + * @{ + */ + + +/** + * @brief SVM rbf prediction + * @param[in] S Pointer to an instance of the rbf SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult decision value + * @return none. + * + */ + +void riscv_svm_rbf_predict_f32( + const riscv_svm_rbf_instance_f32 *S, + const float32_t * in, + int32_t * pResult) +{ +#if defined(RISCV_VECTOR) + + float32_t dot = 0; + float32_t sum = S->intercept; + const float32_t *pSupport = S->supportVectors; + uint32_t blkCnt = S->vectorDimension; + uint32_t blkCnt_back = S->vectorDimension; + size_t l; + vfloat32m8_t v_in, v_support, v_sq; + vfloat32m1_t v_dot; + uint32_t i; + const float32_t * pIn = in; + for(i=0; i < S->nbOfSupportVectors; i++) + { + l = vsetvl_e32m1(1); + v_dot = vfmv_s_f_f32m1(v_dot, 0, l); + in = pIn; + for (blkCnt = blkCnt_back; (l = vsetvl_e32m8(blkCnt)) > 0; blkCnt -= l) + { + v_in = vle32_v_f32m8(in, l); + v_support = vle32_v_f32m8(pSupport, l); + v_sq = vfsub_vv_f32m8(v_in, v_support, l); + v_dot = vfredsum_vs_f32m8_f32m1(v_dot, vfmul_vv_f32m8(v_sq, v_sq, l), v_dot, l); + in += l; + pSupport += l; + } + vsetvl_e32m1(1); + dot = vfmv_f_s_f32m1_f32(v_dot); + sum += S->dualCoefficients[i] * expf(-S->gamma * dot); + } + *pResult=S->classes[STEP(sum)]; +#else + float32_t sum=S->intercept; + float32_t dot=0; + uint32_t i,j; + const float32_t *pSupport = S->supportVectors; + + for(i=0; i < S->nbOfSupportVectors; i++) + { + dot=0; + for(j=0; j < S->vectorDimension; j++) + { + dot = dot + SQ(in[j] - *pSupport); + pSupport++; + } + sum += S->dualCoefficients[i] * expf(-S->gamma * dot); + } + *pResult=S->classes[STEP(sum)]; +#endif /* defined(RISCV_VECTOR) */ +} + + +/** + * @} end of rbfsvm group + */ diff --git a/components/nmsis/dsp/src/SVMFunctions/riscv_svm_sigmoid_init_f16.c b/components/nmsis/dsp/src/SVMFunctions/riscv_svm_sigmoid_init_f16.c new file mode 100644 index 00000000..e9e41719 --- /dev/null +++ b/components/nmsis/dsp/src/SVMFunctions/riscv_svm_sigmoid_init_f16.c @@ -0,0 +1,99 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_svm_sigmoid_predict_f16.c + * Description: SVM Sigmoid Instance Initialization + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/svm_functions_f16.h" + +#if defined(RISCV_FLOAT16_SUPPORTED) + +#include +#include + +/** + @ingroup groupSVM + */ + +/** + @defgroup sigmoidsvm Sigmoid SVM + + Sigmoid SVM classifier + */ + +/** + * @addtogroup sigmoidsvm + * @{ + */ + + +/** + * @brief SVM sigmoid instance init function + * + * Classes are integer used as output of the function (instead of having -1,1 + * as class values). + * + * @param[in] S points to an instance of the rbf SVM structure. + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @param[in] coef0 coeff0 (scikit-learn terminology) + * @param[in] gamma gamma (scikit-learn terminology) + * @return none. + * + */ + +void riscv_svm_sigmoid_init_f16(riscv_svm_sigmoid_instance_f16 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float16_t intercept, + const float16_t *dualCoefficients, + const float16_t *supportVectors, + const int32_t *classes, + float16_t coef0, + float16_t gamma + ) +{ + S->nbOfSupportVectors = nbOfSupportVectors; + S->vectorDimension = vectorDimension; + S->intercept = intercept; + S->dualCoefficients = dualCoefficients; + S->supportVectors = supportVectors; + S->classes = classes; + S->coef0 = coef0; + S->gamma = gamma; +} + + +/** + * @} end of sigmoidsvm group + */ + +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ + diff --git a/components/nmsis/dsp/src/SVMFunctions/riscv_svm_sigmoid_init_f32.c b/components/nmsis/dsp/src/SVMFunctions/riscv_svm_sigmoid_init_f32.c new file mode 100644 index 00000000..cad9378d --- /dev/null +++ b/components/nmsis/dsp/src/SVMFunctions/riscv_svm_sigmoid_init_f32.c @@ -0,0 +1,93 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_svm_sigmoid_predict_f32.c + * Description: SVM Sigmoid Instance Initialization + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/svm_functions.h" +#include +#include + +/** + @ingroup groupSVM + */ + +/** + @defgroup sigmoidsvm Sigmoid SVM + + Sigmoid SVM classifier + */ + +/** + * @addtogroup sigmoidsvm + * @{ + */ + + +/** + * @brief SVM sigmoid instance init function + * + * Classes are integer used as output of the function (instead of having -1,1 + * as class values). + * + * @param[in] S points to an instance of the rbf SVM structure. + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @param[in] coef0 coeff0 (scikit-learn terminology) + * @param[in] gamma gamma (scikit-learn terminology) + * @return none. + * + */ + +void riscv_svm_sigmoid_init_f32(riscv_svm_sigmoid_instance_f32 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float32_t intercept, + const float32_t *dualCoefficients, + const float32_t *supportVectors, + const int32_t *classes, + float32_t coef0, + float32_t gamma + ) +{ + S->nbOfSupportVectors = nbOfSupportVectors; + S->vectorDimension = vectorDimension; + S->intercept = intercept; + S->dualCoefficients = dualCoefficients; + S->supportVectors = supportVectors; + S->classes = classes; + S->coef0 = coef0; + S->gamma = gamma; +} + + +/** + * @} end of sigmoidsvm group + */ diff --git a/components/nmsis/dsp/src/SVMFunctions/riscv_svm_sigmoid_predict_f16.c b/components/nmsis/dsp/src/SVMFunctions/riscv_svm_sigmoid_predict_f16.c new file mode 100644 index 00000000..71a50d47 --- /dev/null +++ b/components/nmsis/dsp/src/SVMFunctions/riscv_svm_sigmoid_predict_f16.c @@ -0,0 +1,81 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_svm_sigmoid_predict_f16.c + * Description: SVM Sigmoid Classifier + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/svm_functions_f16.h" + +#if defined(RISCV_FLOAT16_SUPPORTED) + +#include +#include + +/** + * @addtogroup sigmoidsvm + * @{ + */ + + + +/** + * @brief SVM sigmoid prediction + * @param[in] S Pointer to an instance of the rbf SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult Decision value + * @return none. + * + */ + +void riscv_svm_sigmoid_predict_f16( + const riscv_svm_sigmoid_instance_f16 *S, + const float16_t * in, + int32_t * pResult) +{ + _Float16 sum=S->intercept; + _Float16 dot=0.0f16; + uint32_t i,j; + const float16_t *pSupport = S->supportVectors; + + for(i=0; i < S->nbOfSupportVectors; i++) + { + dot=0.0f16; + for(j=0; j < S->vectorDimension; j++) + { + dot = dot + (_Float16)in[j] * (_Float16)*pSupport++; + } + sum += (_Float16)S->dualCoefficients[i] * (_Float16)tanhf((_Float16)S->gamma * dot + (_Float16)S->coef0); + } + *pResult=S->classes[STEP(sum)]; +} + + +/** + * @} end of sigmoidsvm group + */ + +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ + diff --git a/components/nmsis/dsp/src/SVMFunctions/riscv_svm_sigmoid_predict_f32.c b/components/nmsis/dsp/src/SVMFunctions/riscv_svm_sigmoid_predict_f32.c new file mode 100644 index 00000000..171876cc --- /dev/null +++ b/components/nmsis/dsp/src/SVMFunctions/riscv_svm_sigmoid_predict_f32.c @@ -0,0 +1,107 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_svm_sigmoid_predict_f32.c + * Description: SVM Sigmoid Classifier + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/svm_functions.h" +#include +#include + +/** + * @addtogroup sigmoidsvm + * @{ + */ + + + +/** + * @brief SVM sigmoid prediction + * @param[in] S Pointer to an instance of the rbf SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult Decision value + * @return none. + * + */ + +void riscv_svm_sigmoid_predict_f32( + const riscv_svm_sigmoid_instance_f32 *S, + const float32_t * in, + int32_t * pResult) +{ +#if defined(RISCV_VECTOR) + + float32_t dot = 0; + float32_t sum = S->intercept; + const float32_t *pSupport = S->supportVectors; + uint32_t blkCnt = S->vectorDimension; + uint32_t blkCnt_back = S->vectorDimension; + size_t l; + vfloat32m8_t v_in, v_support; + vfloat32m1_t v_dot; + uint32_t i; + const float32_t * pIn = in; + for(i=0; i < S->nbOfSupportVectors; i++) + { + l = vsetvl_e32m1(1); + v_dot = vfmv_s_f_f32m1(v_dot, 0, l); + in = pIn; + for (blkCnt = blkCnt_back; (l = vsetvl_e32m8(blkCnt)) > 0; blkCnt -= l) + { + v_in = vle32_v_f32m8(in, l); + v_support = vle32_v_f32m8(pSupport, l); + v_dot = vfredsum_vs_f32m8_f32m1(v_dot, vfmul_vv_f32m8(v_in, v_support, l), v_dot, l); + in += l; + pSupport += l; + } + vsetvl_e32m1(1); + dot = vfmv_f_s_f32m1_f32(v_dot); + sum += S->dualCoefficients[i] * tanhf(S->gamma * dot + S->coef0); + } + *pResult=S->classes[STEP(sum)]; +#else + float32_t sum=S->intercept; + float32_t dot=0; + uint32_t i,j; + const float32_t *pSupport = S->supportVectors; + + for(i=0; i < S->nbOfSupportVectors; i++) + { + dot=0; + for(j=0; j < S->vectorDimension; j++) + { + dot = dot + in[j]* *pSupport++; + } + sum += S->dualCoefficients[i] * tanhf(S->gamma * dot + S->coef0); + } + *pResult=S->classes[STEP(sum)]; +#endif /* defined(RISCV_VECTOR) */ +} + + +/** + * @} end of sigmoidsvm group + */ diff --git a/components/nmsis/dsp/src/StatisticsFunctions/StatisticsFunctions.c b/components/nmsis/dsp/src/StatisticsFunctions/StatisticsFunctions.c new file mode 100644 index 00000000..d9e47ed3 --- /dev/null +++ b/components/nmsis/dsp/src/StatisticsFunctions/StatisticsFunctions.c @@ -0,0 +1,69 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: StatisticsFunctions.c + * Description: Combination of all statistics function source files. + * + * $Date: 16. March 2020 + * $Revision: V1.1.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2019-2020 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "riscv_entropy_f32.c" +#include "riscv_entropy_f64.c" +#include "riscv_kullback_leibler_f32.c" +#include "riscv_kullback_leibler_f64.c" +#include "riscv_logsumexp_dot_prod_f32.c" +#include "riscv_logsumexp_f32.c" +#include "riscv_max_f32.c" +#include "riscv_max_q15.c" +#include "riscv_max_q31.c" +#include "riscv_max_q7.c" +#include "riscv_max_no_idx_f32.c" +#include "riscv_mean_f32.c" +#include "riscv_mean_q15.c" +#include "riscv_mean_q31.c" +#include "riscv_mean_q7.c" +#include "riscv_min_f32.c" +#include "riscv_min_q15.c" +#include "riscv_min_q31.c" +#include "riscv_min_q7.c" +#include "riscv_power_f32.c" +#include "riscv_power_q15.c" +#include "riscv_power_q31.c" +#include "riscv_power_q7.c" +#include "riscv_rms_f32.c" +#include "riscv_rms_q15.c" +#include "riscv_rms_q31.c" +#include "riscv_std_f32.c" +#include "riscv_std_q15.c" +#include "riscv_std_q31.c" +#include "riscv_var_f32.c" +#include "riscv_var_q15.c" +#include "riscv_var_q31.c" +#include "riscv_absmax_f32.c" +#include "riscv_absmax_q15.c" +#include "riscv_absmax_q31.c" +#include "riscv_absmax_q7.c" +#include "riscv_absmin_f32.c" +#include "riscv_absmin_q15.c" +#include "riscv_absmin_q31.c" +#include "riscv_absmin_q7.c" \ No newline at end of file diff --git a/components/nmsis/dsp/src/StatisticsFunctions/StatisticsFunctionsF16.c b/components/nmsis/dsp/src/StatisticsFunctions/StatisticsFunctionsF16.c new file mode 100644 index 00000000..b1a81346 --- /dev/null +++ b/components/nmsis/dsp/src/StatisticsFunctions/StatisticsFunctionsF16.c @@ -0,0 +1,43 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: StatisticsFunctions.c + * Description: Combination of all statistics function source files. + * + * $Date: 16. March 2020 + * $Revision: V1.1.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2019-2020 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "riscv_max_f16.c" +#include "riscv_min_f16.c" +#include "riscv_mean_f16.c" +#include "riscv_power_f16.c" +#include "riscv_rms_f16.c" +#include "riscv_std_f16.c" +#include "riscv_var_f16.c" +#include "riscv_entropy_f16.c" +#include "riscv_kullback_leibler_f16.c" +#include "riscv_logsumexp_dot_prod_f16.c" +#include "riscv_logsumexp_f16.c" +#include "riscv_max_no_idx_f16.c" +#include "riscv_absmax_f16.c" +#include "riscv_absmin_f16.c" \ No newline at end of file diff --git a/components/nmsis/dsp/src/StatisticsFunctions/riscv_absmax_f16.c b/components/nmsis/dsp/src/StatisticsFunctions/riscv_absmax_f16.c new file mode 100644 index 00000000..56359c86 --- /dev/null +++ b/components/nmsis/dsp/src/StatisticsFunctions/riscv_absmax_f16.c @@ -0,0 +1,187 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_absmax_f16.c + * Description: Maximum value of a absolute values of a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions_f16.h" + +#if defined(RISCV_FLOAT16_SUPPORTED) + + +/** + @ingroup groupStats + */ + + +/** + @addtogroup AbsMax + @{ + */ + +/** + @brief Maximum value of absolute values of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @param[out] pIndex index of maximum value returned here + @return none + */ + +#if defined(RISCV_MATH_LOOPUNROLL) +void riscv_absmax_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult, + uint32_t * pIndex) +{ + float16_t cur_absmax, out; /* Temporary variables to store the output value. */\ + uint32_t blkCnt, outIndex; /* Loop counter */ \ + uint32_t index; /* index of maximum value */ \ + \ + /* Initialize index value to zero. */ \ + outIndex = 0U; \ + /* Load first input value that act as reference value for comparision */ \ + out = *pSrc++; \ + out = (out > 0.0f16) ? out : -out; \ + /* Initialize index of extrema value. */ \ + index = 0U; \ + \ + /* Loop unrolling: Compute 4 outputs at a time */ \ + blkCnt = (blockSize - 1U) >> 2U; \ + \ + while (blkCnt > 0U) \ + { \ + /* Initialize cur_absmax to next consecutive values one by one */ \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0.0f16) ? cur_absmax : -cur_absmax; \ + /* compare for the extrema value */ \ + if (cur_absmax > out) \ + { \ + /* Update the extrema value and it's index */ \ + out = cur_absmax; \ + outIndex = index + 1U; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0.0f16) ? cur_absmax : -cur_absmax; \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + outIndex = index + 2U; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0.0f16) ? cur_absmax : -cur_absmax; \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + outIndex = index + 3U; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0.0f16) ? cur_absmax : -cur_absmax; \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + outIndex = index + 4U; \ + } \ + \ + index += 4U; \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Loop unrolling: Compute remaining outputs */ \ + blkCnt = (blockSize - 1U) % 4U; \ + \ + \ + while (blkCnt > 0U) \ + { \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0.0f16) ? cur_absmax : -cur_absmax; \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + outIndex = blockSize - blkCnt; \ + } \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Store the extrema value and it's index into destination pointers */ \ + *pResult = out; \ + *pIndex = outIndex; +} +#else +void riscv_absmax_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult, + uint32_t * pIndex) +{ + float16_t maxVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + + /* Initialise index value to zero. */ + outIndex = 0U; + + /* Load first input value that act as reference value for comparision */ + out = fabsf(*pSrc++); + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal = fabsf(*pSrc++); + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the maximum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} +#endif /* defined(RISCV_MATH_LOOPUNROLL) */ +/** + @} end of AbsMax group + */ + +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ + diff --git a/components/nmsis/dsp/src/StatisticsFunctions/riscv_absmax_f32.c b/components/nmsis/dsp/src/StatisticsFunctions/riscv_absmax_f32.c new file mode 100644 index 00000000..9ac44f43 --- /dev/null +++ b/components/nmsis/dsp/src/StatisticsFunctions/riscv_absmax_f32.c @@ -0,0 +1,223 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_absmax_f32.c + * Description: Maximum value of absolute values of a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @defgroup AbsMax Absolute Maximum + + Computes the maximum value of absolute values of an array of data. + The function returns both the maximum value and its position within the array. + There are separate functions for floating-point, Q31, Q15, and Q7 data types. + */ + +/** + @addtogroup AbsMax + @{ + */ + +/** + @brief Maximum value of absolute values of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @param[out] pIndex index of maximum value returned here + @return none + */ +#if defined(RISCV_MATH_LOOPUNROLL) +void riscv_absmax_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex) +{ + float32_t cur_absmax, out; /* Temporary variables to store the output value. */\ + uint32_t blkCnt, outIndex; /* Loop counter */ \ + uint32_t index; /* index of maximum value */ \ + \ + /* Initialize index value to zero. */ \ + outIndex = 0U; \ + /* Load first input value that act as reference value for comparision */ \ + out = *pSrc++; \ + out = (out > 0.0f) ? out : -out; \ + /* Initialize index of extrema value. */ \ + index = 0U; \ + \ + /* Loop unrolling: Compute 4 outputs at a time */ \ + blkCnt = (blockSize - 1U) >> 2U; \ + \ + while (blkCnt > 0U) \ + { \ + /* Initialize cur_absmax to next consecutive values one by one */ \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0.0f) ? cur_absmax : -cur_absmax; \ + /* compare for the extrema value */ \ + if (cur_absmax > out) \ + { \ + /* Update the extrema value and it's index */ \ + out = cur_absmax; \ + outIndex = index + 1U; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0.0f) ? cur_absmax : -cur_absmax; \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + outIndex = index + 2U; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0.0f) ? cur_absmax : -cur_absmax; \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + outIndex = index + 3U; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0.0f) ? cur_absmax : -cur_absmax; \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + outIndex = index + 4U; \ + } \ + \ + index += 4U; \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Loop unrolling: Compute remaining outputs */ \ + blkCnt = (blockSize - 1U) % 4U; \ + \ + \ + while (blkCnt > 0U) \ + { \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0.0f) ? cur_absmax : -cur_absmax; \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + outIndex = blockSize - blkCnt; \ + } \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Store the extrema value and it's index into destination pointers */ \ + *pResult = out; \ + *pIndex = outIndex; +} +#else +void riscv_absmax_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex) +{ + float32_t maxVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + + +#if defined(RISCV_VECTOR) + blkCnt = blockSize; + uint32_t temp_index = 0; + float32_t temp_max; + size_t l; + vfloat32m8_t v_x; + vfloat32m1_t v_temp; + float32_t *pIN = pSrc; + out = 0; + outIndex = 0; + l = vsetvl_e32m1(1); + v_temp = vfsub_vv_f32m1(v_temp, v_temp, l); + for (; (l = vsetvl_e32m8(blkCnt)) > 0; blkCnt -= l) { + v_x = vle32_v_f32m8(pIN, l); + pIN += l; + v_x = vfsgnjx_vv_f32m8(v_x,v_x, l); + temp_max = vfmv_f_s_f32m1_f32(vfredmax_vs_f32m8_f32m1(v_temp,v_x,v_temp, l)); + if(temp_max > out){ + out = temp_max; + outIndex = temp_index; + } + temp_index += l; + } + pIN = pSrc + outIndex; + while(1){ + if(out == *pIN){ + break; + } + else{ + pIN++; + outIndex++; + } + } +#else + /* Initialise index value to zero. */ + outIndex = 0U; + + /* Load first input value that act as reference value for comparision */ + out = fabsf(*pSrc++); + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal = fabsf(*pSrc++); + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } +#endif + /* Store the maximum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} +#endif /* defined(RISCV_MATH_LOOPUNROLL) */ +/** + @} end of AbsMax group + */ diff --git a/components/nmsis/dsp/src/StatisticsFunctions/riscv_absmax_q15.c b/components/nmsis/dsp/src/StatisticsFunctions/riscv_absmax_q15.c new file mode 100644 index 00000000..948b153e --- /dev/null +++ b/components/nmsis/dsp/src/StatisticsFunctions/riscv_absmax_q15.c @@ -0,0 +1,180 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_absmax_q15.c + * Description: Maximum value of absolute values of a Q15 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup AbsMax + @{ + */ + +/** + @brief Maximum value of absolute values of a Q15 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @param[out] pIndex index of maximum value returned here + @return none + */ +#if defined(RISCV_MATH_DSP) +void riscv_absmax_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex) +{ + q15_t cur_absmax, out; /* Temporary variables to store the output value. */\ + uint32_t blkCnt, outIndex; /* Loop counter */ \ + uint32_t index; /* index of maximum value */ \ + \ + /* Initialize index value to zero. */ \ + outIndex = 0U; \ + /* Load first input value that act as reference value for comparision */ \ + out = *pSrc++; \ + out = (out > 0) ? out : (q15_t)__QSUB16(0, out); \ + /* Initialize index of extrema value. */ \ + index = 0U; \ + \ + /* Loop unrolling: Compute 4 outputs at a time */ \ + blkCnt = (blockSize - 1U) >> 2U; \ + \ + while (blkCnt > 0U) \ + { \ + /* Initialize cur_absmax to next consecutive values one by one */ \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q15_t)__QSUB16(0, cur_absmax); \ + /* compare for the extrema value */ \ + if (cur_absmax > out) \ + { \ + /* Update the extrema value and it's index */ \ + out = cur_absmax; \ + outIndex = index + 1U; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q15_t)__QSUB16(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + outIndex = index + 2U; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q15_t)__QSUB16(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + outIndex = index + 3U; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q15_t)__QSUB16(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + outIndex = index + 4U; \ + } \ + \ + index += 4U; \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Loop unrolling: Compute remaining outputs */ \ + blkCnt = (blockSize - 1U) % 4U; \ + \ + \ + while (blkCnt > 0U) \ + { \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q15_t)__QSUB16(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + outIndex = blockSize - blkCnt; \ + } \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Store the extrema value and it's index into destination pointers */ \ + *pResult = out; \ + *pIndex = outIndex; +} +#else +void riscv_absmax_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex) +{ + q15_t maxVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + + /* Initialise index value to zero. */ + outIndex = 0U; + /* Load first input value that act as reference value for comparision */ + out = (*pSrc > 0) ? *pSrc : ((*pSrc == (q15_t) 0x8000) ? 0x7fff : -*pSrc); + pSrc++; + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal = (*pSrc > 0) ? *pSrc : ((*pSrc == (q15_t) 0x8000) ? 0x7fff : -*pSrc); + pSrc++; + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the maximum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} +#endif /* defined(RISCV_MATH_DSP) */ +/** + @} end of AbsMax group + */ diff --git a/components/nmsis/dsp/src/StatisticsFunctions/riscv_absmax_q31.c b/components/nmsis/dsp/src/StatisticsFunctions/riscv_absmax_q31.c new file mode 100644 index 00000000..d6823e7c --- /dev/null +++ b/components/nmsis/dsp/src/StatisticsFunctions/riscv_absmax_q31.c @@ -0,0 +1,182 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_absmax_q31.c + * Description: Maximum value of absolute values of a Q31 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup AbsMax + @{ + */ + +/** + @brief Maximum value of absolute values of a Q31 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @param[out] pIndex index of maximum value returned here + @return none + */ + +#if defined(RISCV_MATH_DSP) +void riscv_absmax_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex) +{ + q31_t cur_absmax, out; /* Temporary variables to store the output value. */\ + uint32_t blkCnt, outIndex; /* Loop counter */ \ + uint32_t index; /* index of maximum value */ \ + \ + /* Initialize index value to zero. */ \ + outIndex = 0U; \ + /* Load first input value that act as reference value for comparision */ \ + out = *pSrc++; \ + out = (out > 0) ? out : (q31_t)__QSUB(0, out); \ + /* Initialize index of extrema value. */ \ + index = 0U; \ + \ + /* Loop unrolling: Compute 4 outputs at a time */ \ + blkCnt = (blockSize - 1U) >> 2U; \ + \ + while (blkCnt > 0U) \ + { \ + /* Initialize cur_absmax to next consecutive values one by one */ \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q31_t)__QSUB(0, cur_absmax); \ + /* compare for the extrema value */ \ + if (cur_absmax > out) \ + { \ + /* Update the extrema value and it's index */ \ + out = cur_absmax; \ + outIndex = index + 1U; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q31_t)__QSUB(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + outIndex = index + 2U; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q31_t)__QSUB(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + outIndex = index + 3U; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q31_t)__QSUB(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + outIndex = index + 4U; \ + } \ + \ + index += 4U; \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Loop unrolling: Compute remaining outputs */ \ + blkCnt = (blockSize - 1U) % 4U; \ + \ + \ + while (blkCnt > 0U) \ + { \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q31_t)__QSUB(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + outIndex = blockSize - blkCnt; \ + } \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Store the extrema value and it's index into destination pointers */ \ + *pResult = out; \ + *pIndex = outIndex; +} +#else +void riscv_absmax_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex) +{ + q31_t maxVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + + + /* Initialise index value to zero. */ + outIndex = 0U; + /* Load first input value that act as reference value for comparision */ + out = (*pSrc > 0) ? *pSrc : ((*pSrc == INT32_MIN) ? INT32_MAX : -*pSrc); + pSrc++; + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal = (*pSrc > 0) ? *pSrc : ((*pSrc == INT32_MIN) ? INT32_MAX : -*pSrc); + pSrc++; + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the maximum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} +#endif /* defined(RISCV_MATH_DSP) */ +/** + @} end of AbsMax group + */ diff --git a/components/nmsis/dsp/src/StatisticsFunctions/riscv_absmax_q7.c b/components/nmsis/dsp/src/StatisticsFunctions/riscv_absmax_q7.c new file mode 100644 index 00000000..164fc9df --- /dev/null +++ b/components/nmsis/dsp/src/StatisticsFunctions/riscv_absmax_q7.c @@ -0,0 +1,182 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_absmax_q7.c + * Description: Maximum value of absolute values of a Q7 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup AbsMax + @{ + */ + +/** + @brief Maximum value of absolute values of a Q7 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @param[out] pIndex index of maximum value returned here + @return none + */ + +#if defined(RISCV_MATH_DSP) +void riscv_absmax_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex) +{ + q7_t cur_absmax, out; /* Temporary variables to store the output value. */\ + uint32_t blkCnt, outIndex; /* Loop counter */ \ + uint32_t index; /* index of maximum value */ \ + \ + /* Initialize index value to zero. */ \ + outIndex = 0U; \ + /* Load first input value that act as reference value for comparision */ \ + out = *pSrc++; \ + out = (out > 0) ? out : (q7_t)__QSUB8(0, out); \ + /* Initialize index of extrema value. */ \ + index = 0U; \ + \ + /* Loop unrolling: Compute 4 outputs at a time */ \ + blkCnt = (blockSize - 1U) >> 2U; \ + \ + while (blkCnt > 0U) \ + { \ + /* Initialize cur_absmax to next consecutive values one by one */ \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q7_t)__QSUB8(0, cur_absmax); \ + /* compare for the extrema value */ \ + if (cur_absmax > out) \ + { \ + /* Update the extrema value and it's index */ \ + out = cur_absmax; \ + outIndex = index + 1U; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q7_t)__QSUB8(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + outIndex = index + 2U; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q7_t)__QSUB8(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + outIndex = index + 3U; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q7_t)__QSUB8(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + outIndex = index + 4U; \ + } \ + \ + index += 4U; \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Loop unrolling: Compute remaining outputs */ \ + blkCnt = (blockSize - 1U) % 4U; \ + \ + \ + while (blkCnt > 0U) \ + { \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q7_t)__QSUB8(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + outIndex = blockSize - blkCnt; \ + } \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Store the extrema value and it's index into destination pointers */ \ + *pResult = out; \ + *pIndex = outIndex; +} +#else +void riscv_absmax_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex) +{ + q7_t maxVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + + + /* Initialise index value to zero. */ + outIndex = 0U; + /* Load first input value that act as reference value for comparision */ + out = (*pSrc > 0) ? *pSrc : ((*pSrc == (q7_t) 0x80) ? (q7_t) 0x7f : -*pSrc); + pSrc++; + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal = (*pSrc > 0) ? *pSrc : ((*pSrc == (q7_t) 0x80) ? (q7_t) 0x7f : -*pSrc); + pSrc++; + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the maximum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} +#endif /* defined(RISCV_MATH_DSP) */ +/** + @} end of AbsMax group + */ diff --git a/components/nmsis/dsp/src/StatisticsFunctions/riscv_absmin_f16.c b/components/nmsis/dsp/src/StatisticsFunctions/riscv_absmin_f16.c new file mode 100644 index 00000000..4e98cd5c --- /dev/null +++ b/components/nmsis/dsp/src/StatisticsFunctions/riscv_absmin_f16.c @@ -0,0 +1,188 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_absmin_f16.c + * Description: Minimum value of absolute values of a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions_f16.h" + +#if defined(RISCV_FLOAT16_SUPPORTED) + + + + +/** + @ingroup groupStats + */ + +/** + @addtogroup AbsMin + @{ + */ + +/** + @brief Minimum value of absolute values of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @param[out] pIndex index of minimum value returned here + @return none + */ + +#if defined(RISCV_MATH_LOOPUNROLL) +void riscv_absmin_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult, + uint32_t * pIndex) +{ + float16_t cur_absmin, out; /* Temporary variables to store the output value. */\ + uint32_t blkCnt, outIndex; /* Loop counter */ \ + uint32_t index; /* index of maximum value */ \ + \ + /* Initialize index value to zero. */ \ + outIndex = 0U; \ + /* Load first input value that act as reference value for comparision */ \ + out = *pSrc++; \ + out = (out > 0.0f16) ? out : -out; \ + /* Initialize index of extrema value. */ \ + index = 0U; \ + \ + /* Loop unrolling: Compute 4 outputs at a time */ \ + blkCnt = (blockSize - 1U) >> 2U; \ + \ + while (blkCnt > 0U) \ + { \ + /* Initialize cur_absmin to next consecutive values one by one */ \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0.0f16) ? cur_absmin : -cur_absmin; \ + /* compare for the extrema value */ \ + if (cur_absmin < out) \ + { \ + /* Update the extrema value and it's index */ \ + out = cur_absmin; \ + outIndex = index + 1U; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0.0f16) ? cur_absmin : -cur_absmin; \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + outIndex = index + 2U; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0.0f16) ? cur_absmin : -cur_absmin; \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + outIndex = index + 3U; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0.0f16) ? cur_absmin : -cur_absmin; \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + outIndex = index + 4U; \ + } \ + \ + index += 4U; \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Loop unrolling: Compute remaining outputs */ \ + blkCnt = (blockSize - 1U) % 4U; \ + \ + \ + while (blkCnt > 0U) \ + { \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0.0f16) ? cur_absmin : -cur_absmin; \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + outIndex = blockSize - blkCnt; \ + } \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Store the extrema value and it's index into destination pointers */ \ + *pResult = out; \ + *pIndex = outIndex; +} +#else +void riscv_absmin_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult, + uint32_t * pIndex) +{ + float16_t minVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + + /* Initialise index value to zero. */ + outIndex = 0U; + + /* Load first input value that act as reference value for comparision */ + out = fabsf(*pSrc++); + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal = fabsf(*pSrc++); + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the minimum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} +#endif /* defined(RISCV_MATH_LOOPUNROLL) */ +/** + @} end of AbsMin group + */ + +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ + diff --git a/components/nmsis/dsp/src/StatisticsFunctions/riscv_absmin_f32.c b/components/nmsis/dsp/src/StatisticsFunctions/riscv_absmin_f32.c new file mode 100644 index 00000000..82ab935a --- /dev/null +++ b/components/nmsis/dsp/src/StatisticsFunctions/riscv_absmin_f32.c @@ -0,0 +1,227 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_absmin_f32.c + * Description: Minimum value of absolute values of a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + + + +/** + @ingroup groupStats + */ + +/** + @defgroup AbsMin Absolute Minimum + + Computes the minimum value of absolute values of an array of data. + The function returns both the minimum value and its position within the array. + There are separate functions for floating-point, Q31, Q15, and Q7 data types. + */ + +/** + @addtogroup AbsMin + @{ + */ + +/** + @brief Minimum value of absolute values of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @param[out] pIndex index of minimum value returned here + @return none + */ + +#if defined(RISCV_MATH_LOOPUNROLL) +void riscv_absmin_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex) +{ + float32_t cur_absmin, out; /* Temporary variables to store the output value. */\ + uint32_t blkCnt, outIndex; /* Loop counter */ \ + uint32_t index; /* index of maximum value */ \ + \ + /* Initialize index value to zero. */ \ + outIndex = 0U; \ + /* Load first input value that act as reference value for comparision */ \ + out = *pSrc++; \ + out = (out > 0.0f) ? out : -out; \ + /* Initialize index of extrema value. */ \ + index = 0U; \ + \ + /* Loop unrolling: Compute 4 outputs at a time */ \ + blkCnt = (blockSize - 1U) >> 2U; \ + \ + while (blkCnt > 0U) \ + { \ + /* Initialize cur_absmin to next consecutive values one by one */ \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0.0f) ? cur_absmin : -cur_absmin; \ + /* compare for the extrema value */ \ + if (cur_absmin < out) \ + { \ + /* Update the extrema value and it's index */ \ + out = cur_absmin; \ + outIndex = index + 1U; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0.0f) ? cur_absmin : -cur_absmin; \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + outIndex = index + 2U; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0.0f) ? cur_absmin : -cur_absmin; \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + outIndex = index + 3U; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0.0f) ? cur_absmin : -cur_absmin; \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + outIndex = index + 4U; \ + } \ + \ + index += 4U; \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Loop unrolling: Compute remaining outputs */ \ + blkCnt = (blockSize - 1U) % 4U; \ + \ + \ + while (blkCnt > 0U) \ + { \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0.0f) ? cur_absmin : -cur_absmin; \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + outIndex = blockSize - blkCnt; \ + } \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Store the extrema value and it's index into destination pointers */ \ + *pResult = out; \ + *pIndex = outIndex; +} +#else +void riscv_absmin_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex) +{ + float32_t minVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + +#if defined(RISCV_VECTOR) + blkCnt = blockSize; + uint32_t temp_index = 0; + float32_t temp_min; + size_t l; + vfloat32m8_t v_x; + vfloat32m1_t v_temp; + float32_t *pIN = pSrc; + out = fabsf(*pIN); + outIndex = 0; + l = vsetvl_e32m1(1); + v_temp = vfmv_v_f_f32m1(out, l); + for (; (l = vsetvl_e32m8(blkCnt)) > 0; blkCnt -= l) { + v_x = vle32_v_f32m8(pIN, l); + pIN += l; + v_x = vfsgnjx_vv_f32m8(v_x,v_x, l); + temp_min = vfmv_f_s_f32m1_f32(vfredmin_vs_f32m8_f32m1(v_temp,v_x,v_temp, l)); + if(temp_min < out){ + out = temp_min; + outIndex = temp_index; + temp_index = 0; + } + temp_index += l; + } + pIN = pSrc + outIndex; + while(1){ + if(out == *pIN){ + break; + } + else{ + pIN++; + outIndex++; + } + } +#else + /* Initialise index value to zero. */ + outIndex = 0U; + + /* Load first input value that act as reference value for comparision */ + out = fabsf(*pSrc++); + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal = fabsf(*pSrc++); + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } +#endif + /* Store the minimum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} + + +#endif /* defined(RISCV_MATH_LOOPUNROLL) */ +/** + @} end of AbsMin group + */ diff --git a/components/nmsis/dsp/src/StatisticsFunctions/riscv_absmin_q15.c b/components/nmsis/dsp/src/StatisticsFunctions/riscv_absmin_q15.c new file mode 100644 index 00000000..5cc391a6 --- /dev/null +++ b/components/nmsis/dsp/src/StatisticsFunctions/riscv_absmin_q15.c @@ -0,0 +1,182 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_absmin_q15.c + * Description: Minimum value of absolute values of a Q15 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + + +/** + @addtogroup AbsMin + @{ + */ + +/** + @brief Minimum value of absolute values of a Q15 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @param[out] pIndex index of minimum value returned here + @return none + */ +#if defined(RISCV_MATH_DSP) +void riscv_absmin_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex) +{ + q15_t cur_absmin, out; /* Temporary variables to store the output value. */\ + uint32_t blkCnt, outIndex; /* Loop counter */ \ + uint32_t index; /* index of maximum value */ \ + \ + /* Initialize index value to zero. */ \ + outIndex = 0U; \ + /* Load first input value that act as reference value for comparision */ \ + out = *pSrc++; \ + out = (out > 0) ? out : (q15_t)__QSUB16(0, out); \ + /* Initialize index of extrema value. */ \ + index = 0U; \ + \ + /* Loop unrolling: Compute 4 outputs at a time */ \ + blkCnt = (blockSize - 1U) >> 2U; \ + \ + while (blkCnt > 0U) \ + { \ + /* Initialize cur_absmin to next consecutive values one by one */ \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q15_t)__QSUB16(0, cur_absmin); \ + /* compare for the extrema value */ \ + if (cur_absmin < out) \ + { \ + /* Update the extrema value and it's index */ \ + out = cur_absmin; \ + outIndex = index + 1U; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q15_t)__QSUB16(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + outIndex = index + 2U; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q15_t)__QSUB16(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + outIndex = index + 3U; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q15_t)__QSUB16(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + outIndex = index + 4U; \ + } \ + \ + index += 4U; \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Loop unrolling: Compute remaining outputs */ \ + blkCnt = (blockSize - 1U) % 4U; \ + \ + \ + while (blkCnt > 0U) \ + { \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q15_t)__QSUB16(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + outIndex = blockSize - blkCnt; \ + } \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Store the extrema value and it's index into destination pointers */ \ + *pResult = out; \ + *pIndex = outIndex; +} +#else +void riscv_absmin_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex) +{ + q15_t minVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + + + /* Initialise index value to zero. */ + outIndex = 0U; + /* Load first input value that act as reference value for comparision */ + out = (*pSrc > 0) ? *pSrc : ((*pSrc == (q15_t) 0x8000) ? 0x7fff : -*pSrc); + pSrc++; + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal = (*pSrc > 0) ? *pSrc : ((*pSrc == (q15_t) 0x8000) ? 0x7fff : -*pSrc); + pSrc++; + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the minimum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} +#endif /* defined(RISCV_MATH_DSP) */ +/** + @} end of AbsMin group + */ diff --git a/components/nmsis/dsp/src/StatisticsFunctions/riscv_absmin_q31.c b/components/nmsis/dsp/src/StatisticsFunctions/riscv_absmin_q31.c new file mode 100644 index 00000000..ad8c8c0b --- /dev/null +++ b/components/nmsis/dsp/src/StatisticsFunctions/riscv_absmin_q31.c @@ -0,0 +1,182 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_absmin_q31.c + * Description: Minimum value of absolute values of a Q31 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + + +/** + @addtogroup AbsMin + @{ + */ + +/** + @brief Minimum value of absolute values of a Q31 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @param[out] pIndex index of minimum value returned here + @return none + */ + +#if defined(RISCV_MATH_DSP) +void riscv_absmin_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex) +{ + q31_t cur_absmin, out; /* Temporary variables to store the output value. */\ + uint32_t blkCnt, outIndex; /* Loop counter */ \ + uint32_t index; /* index of maximum value */ \ + \ + /* Initialize index value to zero. */ \ + outIndex = 0U; \ + /* Load first input value that act as reference value for comparision */ \ + out = *pSrc++; \ + out = (out > 0) ? out : (q31_t)__QSUB(0, out); \ + /* Initialize index of extrema value. */ \ + index = 0U; \ + \ + /* Loop unrolling: Compute 4 outputs at a time */ \ + blkCnt = (blockSize - 1U) >> 2U; \ + \ + while (blkCnt > 0U) \ + { \ + /* Initialize cur_absmin to next consecutive values one by one */ \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q31_t)__QSUB(0, cur_absmin); \ + /* compare for the extrema value */ \ + if (cur_absmin < out) \ + { \ + /* Update the extrema value and it's index */ \ + out = cur_absmin; \ + outIndex = index + 1U; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q31_t)__QSUB(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + outIndex = index + 2U; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q31_t)__QSUB(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + outIndex = index + 3U; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q31_t)__QSUB(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + outIndex = index + 4U; \ + } \ + \ + index += 4U; \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Loop unrolling: Compute remaining outputs */ \ + blkCnt = (blockSize - 1U) % 4U; \ + \ + \ + while (blkCnt > 0U) \ + { \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q31_t)__QSUB(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + outIndex = blockSize - blkCnt; \ + } \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Store the extrema value and it's index into destination pointers */ \ + *pResult = out; \ + *pIndex = outIndex; +} +#else +void riscv_absmin_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex) +{ + q31_t minVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + + /* Initialise index value to zero. */ + outIndex = 0U; + /* Load first input value that act as reference value for comparision */ + out = (*pSrc > 0) ? *pSrc : ((*pSrc == INT32_MIN) ? INT32_MAX : -*pSrc); + pSrc++; + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal = (*pSrc > 0) ? *pSrc : ((*pSrc == INT32_MIN) ? INT32_MAX : -*pSrc); + pSrc++; + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the minimum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} +#endif /* defined(RISCV_MATH_DSP) */ +/** + @} end of AbsMin group + */ diff --git a/components/nmsis/dsp/src/StatisticsFunctions/riscv_absmin_q7.c b/components/nmsis/dsp/src/StatisticsFunctions/riscv_absmin_q7.c new file mode 100644 index 00000000..a4ef0dec --- /dev/null +++ b/components/nmsis/dsp/src/StatisticsFunctions/riscv_absmin_q7.c @@ -0,0 +1,181 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_absmin_q7.c + * Description: Minimum value of absolute values of a Q7 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + + +/** + @addtogroup AbsMin + @{ + */ + +/** + @brief Minimum value of absolute values of a Q7 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @param[out] pIndex index of minimum value returned here + @return none + */ +#if defined(RISCV_MATH_DSP) +void riscv_absmin_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex) +{ + q7_t cur_absmin, out; /* Temporary variables to store the output value. */\ + uint32_t blkCnt, outIndex; /* Loop counter */ \ + uint32_t index; /* index of maximum value */ \ + \ + /* Initialize index value to zero. */ \ + outIndex = 0U; \ + /* Load first input value that act as reference value for comparision */ \ + out = *pSrc++; \ + out = (out > 0) ? out : (q7_t)__QSUB8(0, out); \ + /* Initialize index of extrema value. */ \ + index = 0U; \ + \ + /* Loop unrolling: Compute 4 outputs at a time */ \ + blkCnt = (blockSize - 1U) >> 2U; \ + \ + while (blkCnt > 0U) \ + { \ + /* Initialize cur_absmin to next consecutive values one by one */ \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q7_t)__QSUB8(0, cur_absmin); \ + /* compare for the extrema value */ \ + if (cur_absmin < out) \ + { \ + /* Update the extrema value and it's index */ \ + out = cur_absmin; \ + outIndex = index + 1U; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q7_t)__QSUB8(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + outIndex = index + 2U; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q7_t)__QSUB8(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + outIndex = index + 3U; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q7_t)__QSUB8(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + outIndex = index + 4U; \ + } \ + \ + index += 4U; \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Loop unrolling: Compute remaining outputs */ \ + blkCnt = (blockSize - 1U) % 4U; \ + \ + \ + while (blkCnt > 0U) \ + { \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q7_t)__QSUB8(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + outIndex = blockSize - blkCnt; \ + } \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Store the extrema value and it's index into destination pointers */ \ + *pResult = out; \ + *pIndex = outIndex; +} +#else +void riscv_absmin_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex) +{ + q7_t minVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + + /* Initialise index value to zero. */ + outIndex = 0U; + /* Load first input value that act as reference value for comparision */ + out = (*pSrc > 0) ? *pSrc : ((*pSrc == (q7_t) 0x80) ? (q7_t) 0x7f : -*pSrc); + pSrc++; + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal = (*pSrc > 0) ? *pSrc : ((*pSrc == (q7_t) 0x80) ? (q7_t) 0x7f : -*pSrc); + pSrc++; + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the minimum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} +#endif /* defined(RISCV_MATH_DSP) */ +/** + @} end of AbsMin group + */ diff --git a/components/nmsis/dsp/src/StatisticsFunctions/riscv_entropy_f16.c b/components/nmsis/dsp/src/StatisticsFunctions/riscv_entropy_f16.c new file mode 100644 index 00000000..b368338b --- /dev/null +++ b/components/nmsis/dsp/src/StatisticsFunctions/riscv_entropy_f16.c @@ -0,0 +1,92 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_logsumexp_f16.c + * Description: LogSumExp + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions_f16.h" + +#if defined(RISCV_FLOAT16_SUPPORTED) + +#include +#include + +/** + @ingroup groupStats + */ + +/** + @defgroup Entropy Entropy + + Computes the entropy of a distribution + + */ + +/** + * @addtogroup Entropy + * @{ + */ + + +/** + * @brief Entropy + * + * @param[in] pSrcA Array of input values. + * @param[in] blockSize Number of samples in the input array. + * @return Entropy -Sum(p ln p) + * + */ + + +float16_t riscv_entropy_f16(const float16_t * pSrcA,uint32_t blockSize) +{ + const float16_t *pIn; + uint32_t blkCnt; + _Float16 accum, p; + + pIn = pSrcA; + blkCnt = blockSize; + + accum = 0.0f; + + while(blkCnt > 0) + { + p = *pIn++; + accum += p * logf(p); + + blkCnt--; + + } + + return(-accum); +} + +/** + * @} end of Entropy group + */ + +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ + diff --git a/components/nmsis/dsp/src/StatisticsFunctions/riscv_entropy_f32.c b/components/nmsis/dsp/src/StatisticsFunctions/riscv_entropy_f32.c new file mode 100644 index 00000000..8bf3f080 --- /dev/null +++ b/components/nmsis/dsp/src/StatisticsFunctions/riscv_entropy_f32.c @@ -0,0 +1,75 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_logsumexp_f32.c + * Description: LogSumExp + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" +#include +#include + + +/** + * @addtogroup Entropy + * @{ + */ + + +/** + * @brief Entropy + * + * @param[in] pSrcA Array of input values. + * @param[in] blockSize Number of samples in the input array. + * @return Entropy -Sum(p ln p) + * + */ + +float32_t riscv_entropy_f32(const float32_t * pSrcA,uint32_t blockSize) +{ + const float32_t *pIn; + uint32_t blkCnt; + float32_t accum, p; + + pIn = pSrcA; + blkCnt = blockSize; + + accum = 0.0f; + + while(blkCnt > 0) + { + p = *pIn++; + accum += p * logf(p); + + blkCnt--; + + } + + return(-accum); +} + +/** + * @} end of Entropy group + */ diff --git a/components/nmsis/dsp/src/StatisticsFunctions/riscv_entropy_f64.c b/components/nmsis/dsp/src/StatisticsFunctions/riscv_entropy_f64.c new file mode 100644 index 00000000..9ad603b0 --- /dev/null +++ b/components/nmsis/dsp/src/StatisticsFunctions/riscv_entropy_f64.c @@ -0,0 +1,74 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_logsumexp_f64.c + * Description: LogSumExp + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" +#include +#include + +/** + * @addtogroup Entropy + * @{ + */ + +/** + * @brief Entropy + * + * @param[in] pSrcA Array of input values. + * @param[in] blockSize Number of samples in the input array. + * @return Entropy -Sum(p ln p) + * + */ + +float64_t riscv_entropy_f64(const float64_t * pSrcA, uint32_t blockSize) +{ + const float64_t *pIn; + uint32_t blkCnt; + float64_t accum, p; + + pIn = pSrcA; + blkCnt = blockSize; + + accum = 0.0f; + + while(blkCnt > 0) + { + p = *pIn++; + + accum += p * log(p); + + blkCnt--; + + } + + return(-accum); +} + +/** + * @} end of Entropy group + */ diff --git a/components/nmsis/dsp/src/StatisticsFunctions/riscv_kullback_leibler_f16.c b/components/nmsis/dsp/src/StatisticsFunctions/riscv_kullback_leibler_f16.c new file mode 100644 index 00000000..7b5a8959 --- /dev/null +++ b/components/nmsis/dsp/src/StatisticsFunctions/riscv_kullback_leibler_f16.c @@ -0,0 +1,100 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_logsumexp_f16.c + * Description: LogSumExp + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions_f16.h" + +#if defined(RISCV_FLOAT16_SUPPORTED) + +#include +#include + +/** + @ingroup groupStats + */ + +/** + @defgroup Kullback-Leibler Kullback-Leibler divergence + + Computes the Kullback-Leibler divergence between two distributions + + */ + + +/** + * @addtogroup Kullback-Leibler + * @{ + */ + + +/** + * @brief Kullback-Leibler + * + * Distribution A may contain 0 with Neon version. + * Result will be right but some exception flags will be set. + * + * Distribution B must not contain 0 probability. + * + * @param[in] *pSrcA points to an array of input values for probaility distribution A. + * @param[in] *pSrcB points to an array of input values for probaility distribution B. + * @param[in] blockSize number of samples in the input array. + * @return Kullback-Leibler divergence D(A || B) + * + */ + +float16_t riscv_kullback_leibler_f16(const float16_t * pSrcA,const float16_t * pSrcB,uint32_t blockSize) +{ + const float16_t *pInA, *pInB; + uint32_t blkCnt; + _Float16 accum, pA,pB; + + pInA = pSrcA; + pInB = pSrcB; + blkCnt = blockSize; + + accum = 0.0f; + + while(blkCnt > 0) + { + pA = *pInA++; + pB = *pInB++; + accum += pA * logf(pB / pA); + + blkCnt--; + + } + + return(-accum); +} + +/** + * @} end of Kullback-Leibler group + */ + +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ + diff --git a/components/nmsis/dsp/src/StatisticsFunctions/riscv_kullback_leibler_f32.c b/components/nmsis/dsp/src/StatisticsFunctions/riscv_kullback_leibler_f32.c new file mode 100644 index 00000000..ba88e966 --- /dev/null +++ b/components/nmsis/dsp/src/StatisticsFunctions/riscv_kullback_leibler_f32.c @@ -0,0 +1,83 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_logsumexp_f32.c + * Description: LogSumExp + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" +#include +#include + + +/** + * @addtogroup Kullback-Leibler + * @{ + */ + + +/** + * @brief Kullback-Leibler + * + * Distribution A may contain 0 with Neon version. + * Result will be right but some exception flags will be set. + * + * Distribution B must not contain 0 probability. + * + * @param[in] *pSrcA points to an array of input values for probaility distribution A. + * @param[in] *pSrcB points to an array of input values for probaility distribution B. + * @param[in] blockSize number of samples in the input array. + * @return Kullback-Leibler divergence D(A || B) + * + */ + +float32_t riscv_kullback_leibler_f32(const float32_t * pSrcA,const float32_t * pSrcB,uint32_t blockSize) +{ + const float32_t *pInA, *pInB; + uint32_t blkCnt; + float32_t accum, pA,pB; + + pInA = pSrcA; + pInB = pSrcB; + blkCnt = blockSize; + + accum = 0.0f; + + while(blkCnt > 0) + { + pA = *pInA++; + pB = *pInB++; + accum += pA * logf(pB / pA); + + blkCnt--; + + } + + return(-accum); +} + +/** + * @} end of Kullback-Leibler group + */ diff --git a/components/nmsis/dsp/src/StatisticsFunctions/riscv_kullback_leibler_f64.c b/components/nmsis/dsp/src/StatisticsFunctions/riscv_kullback_leibler_f64.c new file mode 100644 index 00000000..3bc95881 --- /dev/null +++ b/components/nmsis/dsp/src/StatisticsFunctions/riscv_kullback_leibler_f64.c @@ -0,0 +1,76 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_logsumexp_f64.c + * Description: LogSumExp + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" +#include +#include + +/** + * @addtogroup Kullback-Leibler + * @{ + */ + +/** + * @brief Kullback-Leibler + * + * @param[in] *pSrcA points to an array of input values for probaility distribution A. + * @param[in] *pSrcB points to an array of input values for probaility distribution B. + * @param[in] blockSize number of samples in the input array. + * @return Kullback-Leibler divergence D(A || B) + * + */ + +float64_t riscv_kullback_leibler_f64(const float64_t * pSrcA, const float64_t * pSrcB, uint32_t blockSize) +{ + const float64_t *pInA, *pInB; + uint32_t blkCnt; + float64_t accum, pA,pB; + + pInA = pSrcA; + pInB = pSrcB; + blkCnt = blockSize; + + accum = 0.0f; + + while(blkCnt > 0) + { + pA = *pInA++; + pB = *pInB++; + + accum += pA * log(pB / pA); + + blkCnt--; + } + + return(-accum); +} + +/** + * @} end of Kullback-Leibler group + */ diff --git a/components/nmsis/dsp/src/StatisticsFunctions/riscv_logsumexp_dot_prod_f16.c b/components/nmsis/dsp/src/StatisticsFunctions/riscv_logsumexp_dot_prod_f16.c new file mode 100644 index 00000000..5b381387 --- /dev/null +++ b/components/nmsis/dsp/src/StatisticsFunctions/riscv_logsumexp_dot_prod_f16.c @@ -0,0 +1,85 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_logsumexp_f16.c + * Description: LogSumExp + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions_f16.h" + +#if defined(RISCV_FLOAT16_SUPPORTED) + +#include +#include + +/** + @ingroup groupStats + */ + +/** + @defgroup LogSumExp LogSumExp + + LogSumExp optimizations to compute sum of probabilities with Gaussian distributions + + */ + +/** + * @addtogroup LogSumExp + * @{ + */ + + +/** + * @brief Dot product with log arithmetic + * + * Vectors are containing the log of the samples + * + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[in] *pTmpBuffer temporary buffer of length blockSize + * @return The log of the dot product. + * + */ + + +float16_t riscv_logsumexp_dot_prod_f16(const float16_t * pSrcA, + const float16_t * pSrcB, + uint32_t blockSize, + float16_t *pTmpBuffer) +{ + float16_t result; + riscv_add_f16((float16_t*)pSrcA, (float16_t*)pSrcB, pTmpBuffer, blockSize); + + result = riscv_logsumexp_f16(pTmpBuffer, blockSize); + return(result); +} + +/** + * @} end of LogSumExp group + */ + +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ + diff --git a/components/nmsis/dsp/src/StatisticsFunctions/riscv_logsumexp_dot_prod_f32.c b/components/nmsis/dsp/src/StatisticsFunctions/riscv_logsumexp_dot_prod_f32.c new file mode 100644 index 00000000..d553b9aa --- /dev/null +++ b/components/nmsis/dsp/src/StatisticsFunctions/riscv_logsumexp_dot_prod_f32.c @@ -0,0 +1,69 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_logsumexp_f32.c + * Description: LogSumExp + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" +#include +#include + + +/** + * @addtogroup LogSumExp + * @{ + */ + + +/** + * @brief Dot product with log arithmetic + * + * Vectors are containing the log of the samples + * + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[in] *pTmpBuffer temporary buffer of length blockSize + * @return The log of the dot product. + * + */ + + +float32_t riscv_logsumexp_dot_prod_f32(const float32_t * pSrcA, + const float32_t * pSrcB, + uint32_t blockSize, + float32_t *pTmpBuffer) +{ + float32_t result; + riscv_add_f32((float32_t*)pSrcA, (float32_t*)pSrcB, pTmpBuffer, blockSize); + + result = riscv_logsumexp_f32(pTmpBuffer, blockSize); + return(result); +} + +/** + * @} end of LogSumExp group + */ diff --git a/components/nmsis/dsp/src/StatisticsFunctions/riscv_logsumexp_f16.c b/components/nmsis/dsp/src/StatisticsFunctions/riscv_logsumexp_f16.c new file mode 100644 index 00000000..7ccf7b85 --- /dev/null +++ b/components/nmsis/dsp/src/StatisticsFunctions/riscv_logsumexp_f16.c @@ -0,0 +1,114 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_logsumexp_f16.c + * Description: LogSumExp + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions_f16.h" + +#if defined(RISCV_FLOAT16_SUPPORTED) + +#include +#include + + +/** + * @addtogroup LogSumExp + * @{ + */ + + +/** + * @brief Computation of the LogSumExp + * + * In probabilistic computations, the dynamic of the probability values can be very + * wide because they come from gaussian functions. + * To avoid underflow and overflow issues, the values are represented by their log. + * In this representation, multiplying the original exp values is easy : their logs are added. + * But adding the original exp values is requiring some special handling and it is the + * goal of the LogSumExp function. + * + * If the values are x1...xn, the function is computing: + * + * ln(exp(x1) + ... + exp(xn)) and the computation is done in such a way that + * rounding issues are minimised. + * + * The max xm of the values is extracted and the function is computing: + * xm + ln(exp(x1 - xm) + ... + exp(xn - xm)) + * + * @param[in] *in Pointer to an array of input values. + * @param[in] blockSize Number of samples in the input array. + * @return LogSumExp + * + */ + +float16_t riscv_logsumexp_f16(const float16_t *in, uint32_t blockSize) +{ + _Float16 maxVal; + _Float16 tmp; + const float16_t *pIn; + uint32_t blkCnt; + _Float16 accum; + + pIn = in; + blkCnt = blockSize; + + maxVal = *pIn++; + blkCnt--; + + while(blkCnt > 0) + { + tmp = *pIn++; + + if (tmp > maxVal) + { + maxVal = tmp; + } + blkCnt--; + + } + + blkCnt = blockSize; + pIn = in; + accum = 0; + while(blkCnt > 0) + { + tmp = *pIn++; + accum += expf(tmp - maxVal); + blkCnt--; + + } + accum = maxVal + logf(accum); + + return(accum); +} + +/** + * @} end of LogSumExp group + */ + +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ + diff --git a/components/nmsis/dsp/src/StatisticsFunctions/riscv_logsumexp_f32.c b/components/nmsis/dsp/src/StatisticsFunctions/riscv_logsumexp_f32.c new file mode 100644 index 00000000..47a2dec2 --- /dev/null +++ b/components/nmsis/dsp/src/StatisticsFunctions/riscv_logsumexp_f32.c @@ -0,0 +1,127 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_logsumexp_f32.c + * Description: LogSumExp + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" +#include +#include + + +/** + * @addtogroup LogSumExp + * @{ + */ + + +/** + * @brief Computation of the LogSumExp + * + * In probabilistic computations, the dynamic of the probability values can be very + * wide because they come from gaussian functions. + * To avoid underflow and overflow issues, the values are represented by their log. + * In this representation, multiplying the original exp values is easy : their logs are added. + * But adding the original exp values is requiring some special handling and it is the + * goal of the LogSumExp function. + * + * If the values are x1...xn, the function is computing: + * + * ln(exp(x1) + ... + exp(xn)) and the computation is done in such a way that + * rounding issues are minimised. + * + * The max xm of the values is extracted and the function is computing: + * xm + ln(exp(x1 - xm) + ... + exp(xn - xm)) + * + * @param[in] *in Pointer to an array of input values. + * @param[in] blockSize Number of samples in the input array. + * @return LogSumExp + * + */ + +float32_t riscv_logsumexp_f32(const float32_t *in, uint32_t blockSize) +{ + float32_t maxVal; + float32_t tmp; + const float32_t *pIn; + uint32_t blkCnt; + float32_t accum; + + pIn = in; + blkCnt = blockSize; + + maxVal = *pIn++; + blkCnt--; +#if defined(RISCV_VECTOR) + uint32_t blkCnt_v; /* Loop counter */ + size_t l; + float32_t temp_max; + vfloat32m8_t v_x, v_y; + vfloat32m8_t v_a; + vfloat32m1_t v_temp; + l = vsetvl_e32m1(1); + v_temp = vfsub_vv_f32m1(v_temp, v_temp, l); + blkCnt_v = blkCnt; + l = vsetvl_e32m8(blkCnt_v); + v_a = vfsub_vv_f32m8(v_a,v_a, l); + for (; (l = vsetvl_e32m8(blkCnt_v)) > 0; blkCnt_v -= l) { + v_x = vle32_v_f32m8(pIn, l); + temp_max = vfmv_f_s_f32m1_f32 (vfredmax_vs_f32m8_f32m1(v_temp,v_x,v_temp, l)); + if (temp_max > maxVal) + maxVal = temp_max; + pIn += l; + } +#else + while(blkCnt > 0) + { + tmp = *pIn++; + + if (tmp > maxVal) + { + maxVal = tmp; + } + blkCnt--; + } +#endif + + blkCnt = blockSize; + pIn = in; + accum = 0; + while(blkCnt > 0) + { + tmp = *pIn++; + accum += expf(tmp - maxVal); + blkCnt--; + + } + accum = maxVal + logf(accum); + + return(accum); +} + +/** + * @} end of LogSumExp group + */ diff --git a/components/nmsis/dsp/src/StatisticsFunctions/riscv_max_f16.c b/components/nmsis/dsp/src/StatisticsFunctions/riscv_max_f16.c new file mode 100644 index 00000000..a89297d8 --- /dev/null +++ b/components/nmsis/dsp/src/StatisticsFunctions/riscv_max_f16.c @@ -0,0 +1,157 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_max_f16.c + * Description: Maximum value of a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions_f16.h" + +#if defined(RISCV_FLOAT16_SUPPORTED) + + +/** + @ingroup groupStats + */ + + +/** + @addtogroup Max + @{ + */ + +/** + @brief Maximum value of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @param[out] pIndex index of maximum value returned here + @return none + */ + +void riscv_max_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult, + uint32_t * pIndex) +{ + float16_t maxVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + +#if defined (RISCV_MATH_LOOPUNROLL) + uint32_t index; /* index of maximum value */ +#endif + + /* Initialise index value to zero. */ + outIndex = 0U; + + /* Load first input value that act as reference value for comparision */ + out = *pSrc++; + +#if defined (RISCV_MATH_LOOPUNROLL) + /* Initialise index of maximum value. */ + index = 0U; + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (blockSize - 1U) >> 2U; + + while (blkCnt > 0U) + { + /* Initialize maxVal to next consecutive values one by one */ + maxVal = *pSrc++; + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + outIndex = index + 1U; + } + + maxVal = *pSrc++; + if (out < maxVal) + { + out = maxVal; + outIndex = index + 2U; + } + + maxVal = *pSrc++; + if (out < maxVal) + { + out = maxVal; + outIndex = index + 3U; + } + + maxVal = *pSrc++; + if (out < maxVal) + { + out = maxVal; + outIndex = index + 4U; + } + + index += 4U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (blockSize - 1U) % 4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal = *pSrc++; + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the maximum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} + +/** + @} end of Max group + */ + +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ + diff --git a/components/nmsis/dsp/src/StatisticsFunctions/riscv_max_f32.c b/components/nmsis/dsp/src/StatisticsFunctions/riscv_max_f32.c new file mode 100644 index 00000000..fee3141e --- /dev/null +++ b/components/nmsis/dsp/src/StatisticsFunctions/riscv_max_f32.c @@ -0,0 +1,196 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_max_f32.c + * Description: Maximum value of a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @defgroup Max Maximum + + Computes the maximum value of an array of data. + The function returns both the maximum value and its position within the array. + There are separate functions for floating-point, Q31, Q15, and Q7 data types. + */ + +/** + @addtogroup Max + @{ + */ + +/** + @brief Maximum value of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @param[out] pIndex index of maximum value returned here + @return none + */ + +void riscv_max_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex) +{ +#if defined(RISCV_VECTOR) + float32_t max = pSrc[0],max_temp; + uint32_t index = 0,index_temp = 0; + + uint32_t blkCnt; + size_t l; + float32_t * inputx; + vfloat32m8_t v_x; + vfloat32m1_t v_tempa; + + inputx = pSrc; + blkCnt = blockSize; + l = vsetvl_e32m1(1); + v_tempa = vfmv_s_f_f32m1(v_tempa, pSrc[0], l); + for (; (l = vsetvl_e32m8(blkCnt)) > 0; blkCnt -= l) + { + v_x = vle32_v_f32m8(inputx, l); + inputx += l; + max_temp = vfmv_f_s_f32m1_f32 (vfredmax_vs_f32m8_f32m1(v_tempa,v_x,v_tempa, l)); + if (max_temp > max){ + max = max_temp; + index = index_temp; + } + index_temp += l; + } + * pResult = max; + while(1) + { + if (pSrc[index] == max){ + break; + } + else + index++; + } + * pIndex = index; + +#else + float32_t maxVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + +#if defined (RISCV_MATH_LOOPUNROLL) + uint32_t index; /* index of maximum value */ +#endif + + /* Initialise index value to zero. */ + outIndex = 0U; + + /* Load first input value that act as reference value for comparision */ + out = *pSrc++; + +#if defined (RISCV_MATH_LOOPUNROLL) + /* Initialise index of maximum value. */ + index = 0U; + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (blockSize - 1U) >> 2U; + + while (blkCnt > 0U) + { + /* Initialize maxVal to next consecutive values one by one */ + maxVal = *pSrc++; + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + outIndex = index + 1U; + } + + maxVal = *pSrc++; + if (out < maxVal) + { + out = maxVal; + outIndex = index + 2U; + } + + maxVal = *pSrc++; + if (out < maxVal) + { + out = maxVal; + outIndex = index + 3U; + } + + maxVal = *pSrc++; + if (out < maxVal) + { + out = maxVal; + outIndex = index + 4U; + } + + index += 4U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (blockSize - 1U) % 4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal = *pSrc++; + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the maximum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of Max group + */ diff --git a/components/nmsis/dsp/src/StatisticsFunctions/riscv_max_no_idx_f16.c b/components/nmsis/dsp/src/StatisticsFunctions/riscv_max_no_idx_f16.c new file mode 100644 index 00000000..59528ccb --- /dev/null +++ b/components/nmsis/dsp/src/StatisticsFunctions/riscv_max_no_idx_f16.c @@ -0,0 +1,85 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_max_no_idx_f16.c + * Description: Maximum value of a floating-point vector without returning the index + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions_f16.h" + +#if defined(RISCV_FLOAT16_SUPPORTED) + + +/** + @ingroup groupStats + */ + + +/** + @addtogroup Max + @{ + */ + +/** + @brief Maximum value of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @return none + */ + + +void riscv_max_no_idx_f16( + const float16_t *pSrc, + uint32_t blockSize, + float16_t *pResult) +{ + float16_t maxValue = F16_MIN; + float16_t newVal; + + while (blockSize > 0U) + { + newVal = *pSrc++; + + /* compare for the maximum value */ + if (maxValue < newVal) + { + /* Update the maximum value and it's index */ + maxValue = newVal; + } + + blockSize --; + } + + *pResult = maxValue; +} + + +/** + @} end of Max group + */ + +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ + diff --git a/components/nmsis/dsp/src/StatisticsFunctions/riscv_max_no_idx_f32.c b/components/nmsis/dsp/src/StatisticsFunctions/riscv_max_no_idx_f32.c new file mode 100644 index 00000000..68ec7302 --- /dev/null +++ b/components/nmsis/dsp/src/StatisticsFunctions/riscv_max_no_idx_f32.c @@ -0,0 +1,94 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_max_no_idx_f32.c + * Description: Maximum value of a floating-point vector without returning the index + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + + +/** + @addtogroup Max + @{ + */ + +/** + @brief Maximum value of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @return none + */ + + +void riscv_max_no_idx_f32( + const float32_t *pSrc, + uint32_t blockSize, + float32_t *pResult) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + size_t l; + vfloat32m8_t v_in; + l = vsetvl_e32m1(1); + vfloat32m1_t v_max = vfmv_s_f_f32m1(v_max, 0, l); /* vector0 */ + for (; (l = vsetvl_e32m8(blkCnt)) > 0; blkCnt -= l) { + v_in = vle32_v_f32m8(pSrc, l); + pSrc += l; + v_max = vfredmax_vs_f32m8_f32m1(v_max, v_in, v_max, l); + } + l = vsetvl_e32m1(1); + vse32_v_f32m1 (pResult, v_max, l); +#else + float32_t maxValue = F32_MIN; + float32_t newVal; + + while (blockSize > 0U) + { + newVal = *pSrc++; + + /* compare for the maximum value */ + if (maxValue < newVal) + { + /* Update the maximum value and it's index */ + maxValue = newVal; + } + + blockSize --; + } + + *pResult = maxValue; +#endif /* defined(RISCV_VECTOR) */ +} + + +/** + @} end of Max group + */ diff --git a/components/nmsis/dsp/src/StatisticsFunctions/riscv_max_q15.c b/components/nmsis/dsp/src/StatisticsFunctions/riscv_max_q15.c new file mode 100644 index 00000000..0d684074 --- /dev/null +++ b/components/nmsis/dsp/src/StatisticsFunctions/riscv_max_q15.c @@ -0,0 +1,186 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_max_q15.c + * Description: Maximum value of a Q15 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup Max + @{ + */ + +/** + @brief Maximum value of a Q15 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @param[out] pIndex index of maximum value returned here + @return none + */ +void riscv_max_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex) +{ +#if defined(RISCV_VECTOR) + int16_t max = pSrc[0],max_temp; + uint32_t index = 0,index_temp = 0; + + uint32_t blkCnt; + size_t l; + int16_t * inputx; + vint16m8_t v_x; + vint16m1_t v_tempa; + + inputx = pSrc; + blkCnt = blockSize; + l = vsetvl_e16m1(1); + v_tempa = vmv_s_x_i16m1(v_tempa, pSrc[0], l); + for (; (l = vsetvl_e16m8(blkCnt)) > 0; blkCnt -= l) + { + v_x = vle16_v_i16m8(inputx, l); + inputx += l; + max_temp = vmv_x_s_i16m1_i16 (vredmax_vs_i16m8_i16m1(v_tempa,v_x,v_tempa, l)); + if (max_temp > max){ + max = max_temp; + index = index_temp; + } + index_temp += l; + + } + * pResult = max; + while(1) + { + if (pSrc[index] == max){ + break; + } + else + index++; + } + * pIndex = index; + +#else + q15_t maxVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + +#if defined (RISCV_MATH_LOOPUNROLL) + uint32_t index; /* index of maximum value */ +#endif + + /* Initialise index value to zero. */ + outIndex = 0U; + /* Load first input value that act as reference value for comparision */ + out = *pSrc++; + +#if defined (RISCV_MATH_LOOPUNROLL) + /* Initialise index of maximum value. */ + index = 0U; + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (blockSize - 1U) >> 2U; + + while (blkCnt > 0U) + { + /* Initialize maxVal to next consecutive values one by one */ + maxVal = *pSrc++; + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + outIndex = index + 1U; + } + + maxVal = *pSrc++; + if (out < maxVal) + { + out = maxVal; + outIndex = index + 2U; + } + + maxVal = *pSrc++; + if (out < maxVal) + { + out = maxVal; + outIndex = index + 3U; + } + + maxVal = *pSrc++; + if (out < maxVal) + { + out = maxVal; + outIndex = index + 4U; + } + + index += 4U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (blockSize - 1U) % 4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal = *pSrc++; + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the maximum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +#endif /* defined(RISCV_VECTOR) */ +} +/** + @} end of Max group + */ diff --git a/components/nmsis/dsp/src/StatisticsFunctions/riscv_max_q31.c b/components/nmsis/dsp/src/StatisticsFunctions/riscv_max_q31.c new file mode 100644 index 00000000..5eeb8a8e --- /dev/null +++ b/components/nmsis/dsp/src/StatisticsFunctions/riscv_max_q31.c @@ -0,0 +1,187 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_max_q31.c + * Description: Maximum value of a Q31 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup Max + @{ + */ + +/** + @brief Maximum value of a Q31 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @param[out] pIndex index of maximum value returned here + @return none + */ +void riscv_max_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex) +{ +#if defined(RISCV_VECTOR) + int32_t max = pSrc[0],max_temp; + uint32_t index = 0,index_temp = 0; + + uint32_t blkCnt; + size_t l; + int32_t * inputx; + vint32m8_t v_x; + vint32m1_t v_tempa; + + inputx = pSrc; + blkCnt = blockSize; + l = vsetvl_e32m1(1); + v_tempa = vmv_s_x_i32m1(v_tempa, pSrc[0], l); + for (; (l = vsetvl_e32m8(blkCnt)) > 0; blkCnt -= l) + { + v_x = vle32_v_i32m8(inputx, l); + inputx += l; + max_temp = vmv_x_s_i32m1_i32 (vredmax_vs_i32m8_i32m1(v_tempa,v_x,v_tempa, l)); + if (max_temp > max){ + max = max_temp; + index = index_temp; + } + index_temp += l; + + } + * pResult = max; + while(1) + { + if (pSrc[index] == max){ + break; + } + else + index++; + } + * pIndex = index; + +#else + q31_t maxVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + +#if defined (RISCV_MATH_LOOPUNROLL) + uint32_t index; /* index of maximum value */ +#endif + + /* Initialise index value to zero. */ + outIndex = 0U; + /* Load first input value that act as reference value for comparision */ + out = *pSrc++; + +#if defined (RISCV_MATH_LOOPUNROLL) + /* Initialise index of maximum value. */ + index = 0U; + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (blockSize - 1U) >> 2U; + + while (blkCnt > 0U) + { + /* Initialize maxVal to next consecutive values one by one */ + maxVal = *pSrc++; + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + outIndex = index + 1U; + } + + maxVal = *pSrc++; + if (out < maxVal) + { + out = maxVal; + outIndex = index + 2U; + } + + maxVal = *pSrc++; + if (out < maxVal) + { + out = maxVal; + outIndex = index + 3U; + } + + maxVal = *pSrc++; + if (out < maxVal) + { + out = maxVal; + outIndex = index + 4U; + } + + index += 4U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (blockSize - 1U) % 4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal = *pSrc++; + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the maximum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of Max group + */ diff --git a/components/nmsis/dsp/src/StatisticsFunctions/riscv_max_q7.c b/components/nmsis/dsp/src/StatisticsFunctions/riscv_max_q7.c new file mode 100644 index 00000000..2b050da7 --- /dev/null +++ b/components/nmsis/dsp/src/StatisticsFunctions/riscv_max_q7.c @@ -0,0 +1,187 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_max_q7.c + * Description: Maximum value of a Q7 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup Max + @{ + */ + +/** + @brief Maximum value of a Q7 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @param[out] pIndex index of maximum value returned here + @return none + */ +void riscv_max_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex) +{ +#if defined(RISCV_VECTOR) + int8_t max = pSrc[0],max_temp; + uint32_t index = 0,index_temp = 0; + + uint32_t blkCnt; + size_t l; + int8_t * inputx; + vint8m8_t v_x; + vint8m1_t v_tempa; + + inputx = pSrc; + blkCnt = blockSize; + l = vsetvl_e8m1(1); + v_tempa = vmv_s_x_i8m1(v_tempa, pSrc[0], l); + for (; (l = vsetvl_e8m8(blkCnt)) > 0; blkCnt -= l) + { + v_x = vle8_v_i8m8(inputx, l); + inputx += l; + max_temp = vmv_x_s_i8m1_i8 (vredmax_vs_i8m8_i8m1(v_tempa,v_x,v_tempa, l)); + if (max_temp > max){ + max = max_temp; + index = index_temp; + } + index_temp += l; + + } + * pResult = max; + while(1) + { + if (pSrc[index] == max){ + break; + } + else + index++; + } + * pIndex = index; + +#else + q7_t maxVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + +#if defined (RISCV_MATH_LOOPUNROLL) + uint32_t index; /* index of maximum value */ +#endif + + /* Initialise index value to zero. */ + outIndex = 0U; + /* Load first input value that act as reference value for comparision */ + out = *pSrc++; + +#if defined (RISCV_MATH_LOOPUNROLL) + /* Initialise index of maximum value. */ + index = 0U; + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (blockSize - 1U) >> 2U; + + while (blkCnt > 0U) + { + /* Initialize maxVal to next consecutive values one by one */ + maxVal = *pSrc++; + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + outIndex = index + 1U; + } + + maxVal = *pSrc++; + if (out < maxVal) + { + out = maxVal; + outIndex = index + 2U; + } + + maxVal = *pSrc++; + if (out < maxVal) + { + out = maxVal; + outIndex = index + 3U; + } + + maxVal = *pSrc++; + if (out < maxVal) + { + out = maxVal; + outIndex = index + 4U; + } + + index += 4U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (blockSize - 1U) % 4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal = *pSrc++; + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the maximum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of Max group + */ diff --git a/components/nmsis/dsp/src/StatisticsFunctions/riscv_mean_f16.c b/components/nmsis/dsp/src/StatisticsFunctions/riscv_mean_f16.c new file mode 100644 index 00000000..8b344436 --- /dev/null +++ b/components/nmsis/dsp/src/StatisticsFunctions/riscv_mean_f16.c @@ -0,0 +1,122 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_mean_f16.c + * Description: Mean value of a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions_f16.h" + +#if defined(RISCV_FLOAT16_SUPPORTED) + + +/** + @ingroup groupStats + */ + +/** + @defgroup mean Mean + + Calculates the mean of the input vector. Mean is defined as the average of the elements in the vector. + The underlying algorithm is used: + + 
+      Result = (pSrc[0] + pSrc[1] + pSrc[2] + ... + pSrc[blockSize-1]) / blockSize;
+
+ + There are separate functions for floating-point, Q31, Q15, and Q7 data types. + */ + +/** + @addtogroup mean + @{ + */ + +/** + @brief Mean value of a floating-point vector. + @param[in] pSrc points to the input vector. + @param[in] blockSize number of samples in input vector. + @param[out] pResult mean value returned here. + @return none + */ + +void riscv_mean_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + float16_t sum = 0.0f; /* Temporary result storage */ + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + sum += *pSrc++; + + sum += *pSrc++; + + sum += *pSrc++; + + sum += *pSrc++; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + sum += *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize */ + /* Store result to destination */ + *pResult = (sum / (float16_t)blockSize); +} + +/** + @} end of mean group + */ + +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ + diff --git a/components/nmsis/dsp/src/StatisticsFunctions/riscv_mean_f32.c b/components/nmsis/dsp/src/StatisticsFunctions/riscv_mean_f32.c new file mode 100644 index 00000000..d3c62cb0 --- /dev/null +++ b/components/nmsis/dsp/src/StatisticsFunctions/riscv_mean_f32.c @@ -0,0 +1,122 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_mean_f32.c + * Description: Mean value of a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + + +/** + @addtogroup mean + @{ + */ + +/** + @brief Mean value of a floating-point vector. + @param[in] pSrc points to the input vector. + @param[in] blockSize number of samples in input vector. + @param[out] pResult mean value returned here. + @return none + */ +void riscv_mean_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + size_t l; + const float32_t * input = pSrc; + float32_t * result = pResult; + float32_t sum; + vfloat32m8_t v_in; + l = vsetvl_e64m1(1); + vfloat32m1_t v_sum = vfmv_s_f_f32m1(v_sum, 0, l); /* init v_sum data */ + for (; (l = vsetvl_e32m8(blkCnt)) > 0; blkCnt -= l) { + v_in = vle32_v_f32m8(input, l); + input += l; + v_sum = vfredsum_vs_f32m8_f32m1(v_sum, v_in ,v_sum, l); + } + l = vsetvl_e32m1(1); + sum = vfmv_f_s_f32m1_f32(v_sum); + * result = (sum / blockSize); +#else + uint32_t blkCnt; /* Loop counter */ + float32_t sum = 0.0f; /* Temporary result storage */ + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + sum += *pSrc++; + + sum += *pSrc++; + + sum += *pSrc++; + + sum += *pSrc++; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + sum += *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize */ + /* Store result to destination */ + *pResult = (sum / blockSize); +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of mean group + */ diff --git a/components/nmsis/dsp/src/StatisticsFunctions/riscv_mean_q15.c b/components/nmsis/dsp/src/StatisticsFunctions/riscv_mean_q15.c new file mode 100644 index 00000000..ec5b5b74 --- /dev/null +++ b/components/nmsis/dsp/src/StatisticsFunctions/riscv_mean_q15.c @@ -0,0 +1,155 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_mean_q15.c + * Description: Mean value of a Q15 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup mean + @{ + */ + +/** + @brief Mean value of a Q15 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult mean value returned here + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 32-bit internal accumulator. + The input is represented in 1.15 format and is accumulated in a 32-bit + accumulator in 17.15 format. + There is no risk of internal overflow with this approach, and the + full precision of intermediate result is preserved. + Finally, the accumulator is truncated to yield a result of 1.15 format. + */ + +void riscv_mean_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + size_t l; + const q15_t * input = pSrc; + q15_t * result = pResult; + q31_t sum; + vint16m8_t v_in; + l = vsetvl_e64m1(1); + vint32m1_t v_sum = vmv_s_x_i32m1(v_sum, 0, l); /* init v_sum data */ + for (; (l = vsetvl_e16m8(blkCnt)) > 0; blkCnt -= l) { + v_in = vle16_v_i16m8(input, l); + input += l; + v_sum = vwredsum_vs_i16m8_i32m1(v_sum, v_in ,v_sum, l); + } + l = vsetvl_e32m1(1); + sum = vmv_x_s_i32m1_i32(v_sum); + * result = (q15_t) (sum / (int32_t) blockSize); +#else + uint32_t blkCnt; /* Loop counter */ + q31_t sum = 0; /* Temporary result storage */ + +#if defined (RISCV_MATH_LOOPUNROLL) + q31_t in; +#if __RISCV_XLEN == 64 + q63_t in64A,in64B,sum64; +#endif /* __RISCV_XLEN == 64 */ +#endif + +#if defined (RISCV_MATH_LOOPUNROLL) +#if __RISCV_XLEN == 64 + /* Loop unrolling: Compute 8 outputs at a time */ + blkCnt = blockSize >> 3U; +#else + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; +#endif /* __RISCV_XLEN == 64 */ + + while (blkCnt > 0U) + { +#if __RISCV_XLEN == 64 + in64A = read_q15x4_ia ((q15_t **) &pSrc); + in64B = read_q15x4_ia ((q15_t **) &pSrc); + sum64 = __RV_KADD16(in64A, in64B); + sum += ((q31_t)((sum64 << 48U) >> 48U)); + sum += ((q31_t)((sum64 << 32U) >> 48U)); + sum += ((q31_t)((sum64 << 16U) >> 48U)); + sum += ((q31_t)((sum64 ) >> 48U)); +#else + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + in = read_q15x2_ia ((q15_t **) &pSrc); + sum += ((in << 16U) >> 16U); + sum += (in >> 16U); + + in = read_q15x2_ia ((q15_t **) &pSrc); + sum += ((in << 16U) >> 16U); + sum += (in >> 16U); +#endif /* __RISCV_XLEN == 64 */ + + /* Decrement the loop counter */ + blkCnt--; + } +#if __RISCV_XLEN == 64 + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x8U; +#else + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; +#endif /* __RISCV_XLEN == 64 */ + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + sum += *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize */ + /* Store result to destination */ + *pResult = (q15_t) (sum / (int32_t) blockSize); +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of mean group + */ diff --git a/components/nmsis/dsp/src/StatisticsFunctions/riscv_mean_q31.c b/components/nmsis/dsp/src/StatisticsFunctions/riscv_mean_q31.c new file mode 100644 index 00000000..dc4e59aa --- /dev/null +++ b/components/nmsis/dsp/src/StatisticsFunctions/riscv_mean_q31.c @@ -0,0 +1,138 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_mean_q31.c + * Description: Mean value of a Q31 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup mean + @{ + */ + +/** + @brief Mean value of a Q31 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult mean value returned here + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + The input is represented in 1.31 format and is accumulated in a 64-bit + accumulator in 33.31 format. + There is no risk of internal overflow with this approach, and the + full precision of intermediate result is preserved. + Finally, the accumulator is truncated to yield a result of 1.31 format. + */ +void riscv_mean_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + size_t l; + const q31_t * input = pSrc; + q31_t * result = pResult; + q63_t sum; + vint32m8_t v_in; + l = vsetvl_e64m1(1); + vint64m1_t v_sum = vmv_s_x_i64m1(v_sum, 0, l); /* init v_sum data */ + for (; (l = vsetvl_e32m8(blkCnt)) > 0; blkCnt -= l) { + v_in = vle32_v_i32m8(input, l); + input += l; + v_sum = vwredsum_vs_i32m8_i64m1(v_sum, v_in ,v_sum, l); + } + l = vsetvl_e64m1(1); + sum = vmv_x_s_i64m1_i64(v_sum); + * result = (q31_t) (sum / blockSize); +#else + uint32_t blkCnt; /* Loop counter */ + q63_t sum = 0; /* Temporary result storage */ +#if __RISCV_XLEN == 64 + q63_t valueA,valueB; /* Temporary result storage */ +#endif /* __RISCV_XLEN == 64 */ +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { +#if __RISCV_XLEN == 64 + valueA = read_q31x2_ia ((q31_t **) &pSrc); + valueB = read_q31x2_ia ((q31_t **) &pSrc); + valueA = __RV_ADD32(valueA,valueB); + sum += (((int64_t)__RV_CRAS32(valueA,valueA)) >> 32); +#else + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + sum += *pSrc++; + + sum += *pSrc++; + + sum += *pSrc++; + + sum += *pSrc++; +#endif /* __RISCV_XLEN == 64 */ + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + sum += *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize */ + /* Store result to destination */ + *pResult = (q31_t) (sum / blockSize); +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of mean group + */ diff --git a/components/nmsis/dsp/src/StatisticsFunctions/riscv_mean_q7.c b/components/nmsis/dsp/src/StatisticsFunctions/riscv_mean_q7.c new file mode 100644 index 00000000..ca045c2b --- /dev/null +++ b/components/nmsis/dsp/src/StatisticsFunctions/riscv_mean_q7.c @@ -0,0 +1,156 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_mean_q7.c + * Description: Mean value of a Q7 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup mean + @{ + */ + +/** + @brief Mean value of a Q7 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult mean value returned here + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 32-bit internal accumulator. + The input is represented in 1.7 format and is accumulated in a 32-bit + accumulator in 25.7 format. + There is no risk of internal overflow with this approach, and the + full precision of intermediate result is preserved. + Finally, the accumulator is truncated to yield a result of 1.7 format. + */ + +void riscv_mean_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + size_t l; + const q7_t * input = pSrc; + q7_t * result = pResult; + q15_t sum; + vint8m8_t v_in; + l = vsetvl_e16m1(1); + vint16m1_t v_sum = vmv_s_x_i16m1(v_sum, 0, l); /* init v_sum data */ + for (; (l = vsetvl_e8m8(blkCnt)) > 0; blkCnt -= l) { + v_in = vle8_v_i8m8(input, l); + input += l; + v_sum = vwredsum_vs_i8m8_i16m1(v_sum, v_in ,v_sum, l); + } + l = vsetvl_e16m1(1); + sum = vmv_x_s_i16m1_i16(v_sum); + * result = (q7_t) (sum / (int32_t) blockSize); +#else + uint32_t blkCnt; /* Loop counter */ + q31_t sum = 0; /* Temporary result storage */ + +#if defined (RISCV_MATH_LOOPUNROLL) +#if __RISCV_XLEN == 64 + q63_t in64; +#endif /* __RISCV_XLEN == 64 */ + q31_t in; +#endif + +#if defined (RISCV_MATH_LOOPUNROLL) +#if __RISCV_XLEN == 64 + /* Loop unrolling: Compute 8 outputs at a time */ + blkCnt = blockSize >> 3U; +#else + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; +#endif /* __RISCV_XLEN == 64 */ + + while (blkCnt > 0U) + { +#if __RISCV_XLEN == 64 + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + in64 = read_q7x8_ia ((q7_t **) &pSrc); + sum += (q31_t)((in64 << 56U) >> 56U); + sum += (q31_t)((in64 << 48U) >> 56U); + sum += (q31_t)((in64 << 40U) >> 56U); + sum += (q31_t)((in64 << 32U) >> 56U); + sum += (q31_t)((in64 << 24U) >> 56U); + sum += (q31_t)((in64 << 16U) >> 56U); + sum += (q31_t)((in64 << 8U) >> 56U); + sum += (q31_t)((in64 ) >> 56U); +#else + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + in = read_q7x4_ia ((q7_t **) &pSrc); + sum += ((in << 24U) >> 24U); + sum += ((in << 16U) >> 24U); + sum += ((in << 8U) >> 24U); + sum += (in >> 24U); +#endif /* __RISCV_XLEN == 64 */ + + /* Decrement the loop counter */ + blkCnt--; + } +#if __RISCV_XLEN == 64 + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x8U; +#else + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; +#endif /* __RISCV_XLEN == 64 */ + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + sum += *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize */ + /* Store result to destination */ + *pResult = (q7_t) (sum / (int32_t) blockSize); +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of mean group + */ diff --git a/components/nmsis/dsp/src/StatisticsFunctions/riscv_min_f16.c b/components/nmsis/dsp/src/StatisticsFunctions/riscv_min_f16.c new file mode 100644 index 00000000..ab9893cc --- /dev/null +++ b/components/nmsis/dsp/src/StatisticsFunctions/riscv_min_f16.c @@ -0,0 +1,159 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_min_f16.c + * Description: Minimum value of a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions_f16.h" + +#if defined(RISCV_FLOAT16_SUPPORTED) + + + + +/** + @ingroup groupStats + */ + +/** + @addtogroup Min + @{ + */ + +/** + @brief Minimum value of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @param[out] pIndex index of minimum value returned here + @return none + */ + + +void riscv_min_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult, + uint32_t * pIndex) +{ + float16_t minVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + +#if defined (RISCV_MATH_LOOPUNROLL) + uint32_t index; /* index of maximum value */ +#endif + + /* Initialise index value to zero. */ + outIndex = 0U; + + /* Load first input value that act as reference value for comparision */ + out = *pSrc++; + +#if defined (RISCV_MATH_LOOPUNROLL) + /* Initialise index of maximum value. */ + index = 0U; + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (blockSize - 1U) >> 2U; + + while (blkCnt > 0U) + { + /* Initialize minVal to next consecutive values one by one */ + minVal = *pSrc++; + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + outIndex = index + 1U; + } + + minVal = *pSrc++; + if (out > minVal) + { + out = minVal; + outIndex = index + 2U; + } + + minVal = *pSrc++; + if (out > minVal) + { + out = minVal; + outIndex = index + 3U; + } + + minVal = *pSrc++; + if (out > minVal) + { + out = minVal; + outIndex = index + 4U; + } + + index += 4U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (blockSize - 1U) % 4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal = *pSrc++; + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the minimum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} + +/** + @} end of Min group + */ + +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ + diff --git a/components/nmsis/dsp/src/StatisticsFunctions/riscv_min_f32.c b/components/nmsis/dsp/src/StatisticsFunctions/riscv_min_f32.c new file mode 100644 index 00000000..f9ee1f85 --- /dev/null +++ b/components/nmsis/dsp/src/StatisticsFunctions/riscv_min_f32.c @@ -0,0 +1,198 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_min_f32.c + * Description: Minimum value of a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + + + +/** + @ingroup groupStats + */ + +/** + @defgroup Min Minimum + + Computes the minimum value of an array of data. + The function returns both the minimum value and its position within the array. + There are separate functions for floating-point, Q31, Q15, and Q7 data types. + */ + +/** + @addtogroup Min + @{ + */ + +/** + @brief Minimum value of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @param[out] pIndex index of minimum value returned here + @return none + */ + +void riscv_min_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex) +{ +#if defined(RISCV_VECTOR) + float32_t min = pSrc[0],min_temp; + uint32_t index = 0,index_temp = 0; + + uint32_t blkCnt; + size_t l; + float32_t * inputx; + vfloat32m8_t v_x; + vfloat32m1_t v_tempa; + + inputx = pSrc; + blkCnt = blockSize; + l = vsetvl_e32m1(1); + v_tempa = vfmv_s_f_f32m1(v_tempa, pSrc[0], l); + for (; (l = vsetvl_e32m8(blkCnt)) > 0; blkCnt -= l) + { + v_x = vle32_v_f32m8(inputx, l); + inputx += l; + min_temp = vfmv_f_s_f32m1_f32 (vfredmin_vs_f32m8_f32m1(v_tempa,v_x,v_tempa, l)); + if (min_temp < min){ + min = min_temp; + index = index_temp; + } + index_temp += l; + } + * pResult = min; + while(1) + { + if (pSrc[index] == min){ + break; + } + else + index++; + } + * pIndex = index; + +#else + float32_t minVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + +#if defined (RISCV_MATH_LOOPUNROLL) + uint32_t index; /* index of minimum value */ +#endif + + /* Initialise index value to zero. */ + outIndex = 0U; + + /* Load first input value that act as reference value for comparision */ + out = *pSrc++; + +#if defined (RISCV_MATH_LOOPUNROLL) + /* Initialise index of minimum value. */ + index = 0U; + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (blockSize - 1U) >> 2U; + + while (blkCnt > 0U) + { + /* Initialize minVal to next consecutive values one by one */ + minVal = *pSrc++; + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + outIndex = index + 1U; + } + + minVal = *pSrc++; + if (out > minVal) + { + out = minVal; + outIndex = index + 2U; + } + + minVal = *pSrc++; + if (out > minVal) + { + out = minVal; + outIndex = index + 3U; + } + + minVal = *pSrc++; + if (out > minVal) + { + out = minVal; + outIndex = index + 4U; + } + + index += 4U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (blockSize - 1U) % 4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal = *pSrc++; + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the minimum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of Min group + */ diff --git a/components/nmsis/dsp/src/StatisticsFunctions/riscv_min_q15.c b/components/nmsis/dsp/src/StatisticsFunctions/riscv_min_q15.c new file mode 100644 index 00000000..6d37b075 --- /dev/null +++ b/components/nmsis/dsp/src/StatisticsFunctions/riscv_min_q15.c @@ -0,0 +1,188 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_min_q15.c + * Description: Minimum value of a Q15 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + + +/** + @addtogroup Min + @{ + */ + +/** + @brief Minimum value of a Q15 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @param[out] pIndex index of minimum value returned here + @return none + */ +void riscv_min_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex) +{ +#if defined(RISCV_VECTOR) + int16_t min = pSrc[0],min_temp; + uint32_t index = 0,index_temp = 0; + + uint32_t blkCnt; + size_t l; + int16_t * inputx; + vint16m8_t v_x; + vint16m1_t v_tempa; + + inputx = pSrc; + blkCnt = blockSize; + l = vsetvl_e16m1(1); + v_tempa = vmv_s_x_i16m1(v_tempa, pSrc[0], l); + for (; (l = vsetvl_e16m8(blkCnt)) > 0; blkCnt -= l) + { + v_x = vle16_v_i16m8(inputx, l); + inputx += l; + min_temp = vmv_x_s_i16m1_i16 (vredmin_vs_i16m8_i16m1(v_tempa,v_x,v_tempa, l)); + if (min_temp < min){ + min = min_temp; + index = index_temp; + } + index_temp += l; + + } + * pResult = min; + while(1) + { + if (pSrc[index] == min){ + break; + } + else + index++; + } + * pIndex = index; + +#else + q15_t minVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + +#if defined (RISCV_MATH_LOOPUNROLL) + uint32_t index; /* index of minimum value */ +#endif + + /* Initialise index value to zero. */ + outIndex = 0U; + /* Load first input value that act as reference value for comparision */ + out = *pSrc++; + +#if defined (RISCV_MATH_LOOPUNROLL) + /* Initialise index of minimum value. */ + index = 0U; + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (blockSize - 1U) >> 2U; + + while (blkCnt > 0U) + { + /* Initialize minVal to next consecutive values one by one */ + minVal = *pSrc++; + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + outIndex = index + 1U; + } + + minVal = *pSrc++; + if (out > minVal) + { + out = minVal; + outIndex = index + 2U; + } + + minVal = *pSrc++; + if (out > minVal) + { + out = minVal; + outIndex = index + 3U; + } + + minVal = *pSrc++; + if (out > minVal) + { + out = minVal; + outIndex = index + 4U; + } + + index += 4U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (blockSize - 1U) % 4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal = *pSrc++; + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the minimum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of Min group + */ diff --git a/components/nmsis/dsp/src/StatisticsFunctions/riscv_min_q31.c b/components/nmsis/dsp/src/StatisticsFunctions/riscv_min_q31.c new file mode 100644 index 00000000..23679fca --- /dev/null +++ b/components/nmsis/dsp/src/StatisticsFunctions/riscv_min_q31.c @@ -0,0 +1,188 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_min_q31.c + * Description: Minimum value of a Q31 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + + +/** + @addtogroup Min + @{ + */ + +/** + @brief Minimum value of a Q31 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @param[out] pIndex index of minimum value returned here + @return none + */ +void riscv_min_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex) +{ +#if defined(RISCV_VECTOR) + int32_t min = pSrc[0],min_temp; + uint32_t index = 0,index_temp = 0; + + uint32_t blkCnt; + size_t l; + int32_t * inputx; + vint32m8_t v_x; + vint32m1_t v_tempa; + + inputx = pSrc; + blkCnt = blockSize; + l = vsetvl_e32m1(1); + v_tempa = vmv_s_x_i32m1(v_tempa, pSrc[0], l); + for (; (l = vsetvl_e32m8(blkCnt)) > 0; blkCnt -= l) + { + v_x = vle32_v_i32m8(inputx, l); + inputx += l; + min_temp = vmv_x_s_i32m1_i32 (vredmin_vs_i32m8_i32m1(v_tempa,v_x,v_tempa, l)); + if (min_temp < min){ + min = min_temp; + index = index_temp; + } + index_temp += l; + + } + * pResult = min; + while(1) + { + if (pSrc[index] == min){ + break; + } + else + index++; + } + * pIndex = index; + +#else + q31_t minVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + +#if defined (RISCV_MATH_LOOPUNROLL) + uint32_t index; /* index of minimum value */ +#endif + + /* Initialise index value to zero. */ + outIndex = 0U; + /* Load first input value that act as reference value for comparision */ + out = *pSrc++; + +#if defined (RISCV_MATH_LOOPUNROLL) + /* Initialise index of minimum value. */ + index = 0U; + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (blockSize - 1U) >> 2U; + + while (blkCnt > 0U) + { + /* Initialize minVal to next consecutive values one by one */ + minVal = *pSrc++; + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + outIndex = index + 1U; + } + + minVal = *pSrc++; + if (out > minVal) + { + out = minVal; + outIndex = index + 2U; + } + + minVal = *pSrc++; + if (out > minVal) + { + out = minVal; + outIndex = index + 3U; + } + + minVal = *pSrc++; + if (out > minVal) + { + out = minVal; + outIndex = index + 4U; + } + + index += 4U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (blockSize - 1U) % 4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal = *pSrc++; + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the minimum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of Min group + */ diff --git a/components/nmsis/dsp/src/StatisticsFunctions/riscv_min_q7.c b/components/nmsis/dsp/src/StatisticsFunctions/riscv_min_q7.c new file mode 100644 index 00000000..c63efefa --- /dev/null +++ b/components/nmsis/dsp/src/StatisticsFunctions/riscv_min_q7.c @@ -0,0 +1,188 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_min_q7.c + * Description: Minimum value of a Q7 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + + +/** + @addtogroup Min + @{ + */ + +/** + @brief Minimum value of a Q7 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @param[out] pIndex index of minimum value returned here + @return none + */ +void riscv_min_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex) +{ +#if defined(RISCV_VECTOR) + int8_t min = pSrc[0],min_temp; + uint32_t index = 0,index_temp = 0; + + uint32_t blkCnt; + size_t l; + int8_t * inputx; + vint8m8_t v_x; + vint8m1_t v_tempa; + + inputx = pSrc; + blkCnt = blockSize; + l = vsetvl_e8m1(1); + v_tempa = vmv_s_x_i8m1(v_tempa, pSrc[0], l); + for (; (l = vsetvl_e8m8(blkCnt)) > 0; blkCnt -= l) + { + v_x = vle8_v_i8m8(inputx, l); + inputx += l; + min_temp = vmv_x_s_i8m1_i8 (vredmin_vs_i8m8_i8m1(v_tempa,v_x,v_tempa, l)); + if (min_temp < min){ + min = min_temp; + index = index_temp; + } + index_temp += l; + + } + * pResult = min; + while(1) + { + if (pSrc[index] == min){ + break; + } + else + index++; + } + * pIndex = index; + +#else + q7_t minVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + +#if defined (RISCV_MATH_LOOPUNROLL) + uint32_t index; /* index of minimum value */ +#endif + + /* Initialise index value to zero. */ + outIndex = 0U; + /* Load first input value that act as reference value for comparision */ + out = *pSrc++; + +#if defined (RISCV_MATH_LOOPUNROLL) + /* Initialise index of minimum value. */ + index = 0U; + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (blockSize - 1U) >> 2U; + + while (blkCnt > 0U) + { + /* Initialize minVal to next consecutive values one by one */ + minVal = *pSrc++; + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + outIndex = index + 1U; + } + + minVal = *pSrc++; + if (out > minVal) + { + out = minVal; + outIndex = index + 2U; + } + + minVal = *pSrc++; + if (out > minVal) + { + out = minVal; + outIndex = index + 3U; + } + + minVal = *pSrc++; + if (out > minVal) + { + out = minVal; + outIndex = index + 4U; + } + + index += 4U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (blockSize - 1U) % 4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal = *pSrc++; + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the minimum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of Min group + */ diff --git a/components/nmsis/dsp/src/StatisticsFunctions/riscv_power_f16.c b/components/nmsis/dsp/src/StatisticsFunctions/riscv_power_f16.c new file mode 100644 index 00000000..814ca7e5 --- /dev/null +++ b/components/nmsis/dsp/src/StatisticsFunctions/riscv_power_f16.c @@ -0,0 +1,120 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_power_f16.c + * Description: Sum of the squares of the elements of a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions_f16.h" + +#if defined(RISCV_FLOAT16_SUPPORTED) + + +/** + @ingroup groupStats + */ + + + +/** + @addtogroup power + @{ + */ + +/** + @brief Sum of the squares of the elements of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult sum of the squares value returned here + @return none + */ + +void riscv_power_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + _Float16 sum = 0.0f16; /* Temporary result storage */ + _Float16 in; /* Temporary variable to store input value */ + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + /* Compute Power and store result in a temporary variable, sum. */ + in = *pSrc++; + sum += in * in; + + in = *pSrc++; + sum += in * in; + + in = *pSrc++; + sum += in * in; + + in = *pSrc++; + sum += in * in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + /* Compute Power and store result in a temporary variable, sum. */ + in = *pSrc++; + sum += in * in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store result to destination */ + *pResult = sum; +} + +/** + @} end of power group + */ + +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ + diff --git a/components/nmsis/dsp/src/StatisticsFunctions/riscv_power_f32.c b/components/nmsis/dsp/src/StatisticsFunctions/riscv_power_f32.c new file mode 100644 index 00000000..478bed52 --- /dev/null +++ b/components/nmsis/dsp/src/StatisticsFunctions/riscv_power_f32.c @@ -0,0 +1,148 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_power_f32.c + * Description: Sum of the squares of the elements of a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @defgroup power Power + + Calculates the sum of the squares of the elements in the input vector. + The underlying algorithm is used: + + 
+      Result = pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + pSrc[2] * pSrc[2] + ... + pSrc[blockSize-1] * pSrc[blockSize-1];
+
+ + There are separate functions for floating point, Q31, Q15, and Q7 data types. + + Since the result is not divided by the length, those functions are in fact computing + something which is more an energy than a power. + + */ + +/** + @addtogroup power + @{ + */ + +/** + @brief Sum of the squares of the elements of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult sum of the squares value returned here + @return none + */ +void riscv_power_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + size_t l; + const float32_t * input = pSrc; + float32_t * output = pResult; + vfloat32m8_t v_in; + vfloat32m8_t v_in2; + l = vsetvl_e32m1(1); + vfloat32m1_t v_sum = vfmv_s_f_f32m1(v_sum, 0.0f, l); + for (; (l = vsetvl_e32m8(blkCnt)) > 0; blkCnt -= l) + { + v_in = vle32_v_f32m8(input, l); + input += l; + v_in2 = vfmul_vv_f32m8(v_in, v_in, l); + v_sum = vfredsum_vs_f32m8_f32m1(v_sum, v_in2, v_sum, l); + } + l = vsetvl_e32m1(1); + vse32_v_f32m1(output, v_sum, l); +#else + uint32_t blkCnt; /* Loop counter */ + float32_t sum = 0.0f; /* Temporary result storage */ + float32_t in; /* Temporary variable to store input value */ + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + /* Compute Power and store result in a temporary variable, sum. */ + in = *pSrc++; + sum += in * in; + + in = *pSrc++; + sum += in * in; + + in = *pSrc++; + sum += in * in; + + in = *pSrc++; + sum += in * in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + /* Compute Power and store result in a temporary variable, sum. */ + in = *pSrc++; + sum += in * in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store result to destination */ + *pResult = sum; +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of power group + */ diff --git a/components/nmsis/dsp/src/StatisticsFunctions/riscv_power_q15.c b/components/nmsis/dsp/src/StatisticsFunctions/riscv_power_q15.c new file mode 100644 index 00000000..dd9ba822 --- /dev/null +++ b/components/nmsis/dsp/src/StatisticsFunctions/riscv_power_q15.c @@ -0,0 +1,160 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_power_q15.c + * Description: Sum of the squares of the elements of a Q15 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup power + @{ + */ + +/** + @brief Sum of the squares of the elements of a Q15 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult sum of the squares value returned here + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + The input is represented in 1.15 format. + Intermediate multiplication yields a 2.30 format, and this + result is added without saturation to a 64-bit accumulator in 34.30 format. + With 33 guard bits in the accumulator, there is no risk of overflow, and the + full precision of the intermediate multiplication is preserved. + Finally, the return result is in 34.30 format. + */ +void riscv_power_q15( + const q15_t * pSrc, + uint32_t blockSize, + q63_t * pResult) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + size_t l; + const q15_t * input = pSrc; + q63_t * output = pResult; + vint16m4_t v_in; + vint32m8_t v_in2; + l = vsetvl_e64m1(1); + vint64m1_t v_sum = vmv_s_x_i64m1(v_sum, 0, l); + for (; (l = vsetvl_e16m4(blkCnt)) > 0; blkCnt -= l) + { + v_in = vle16_v_i16m4(input, l); + input += l; + v_in2 = vwmul_vv_i32m8(v_in, v_in, l); + v_sum = vwredsum_vs_i32m8_i64m1(v_sum, v_in2, v_sum, l); + } + l = vsetvl_e64m1(1); + vse64_v_i64m1(output, v_sum, l); +#else + uint32_t blkCnt; /* Loop counter */ + q63_t sum = 0; /* Temporary result storage */ + q15_t in; /* Temporary variable to store input value */ + +#if defined (RISCV_MATH_LOOPUNROLL) && defined (RISCV_MATH_DSP) +#if __RISCV_XLEN == 64 + q63_t in64; /* Temporary variable to store packed input value */ +#endif /* __RISCV_XLEN == 64 */ + q31_t in32; /* Temporary variable to store packed input value */ +#endif + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + /* Compute Power and store result in a temporary variable, sum. */ +#if defined (RISCV_MATH_DSP) +#if __RISCV_XLEN == 64 + in64 = read_q15x4_ia ((q15_t **) &pSrc); + sum = __RV_SMALDA(sum, in64, in64); +#else + in32 = read_q15x2_ia ((q15_t **) &pSrc); + sum = __RV_SMALDA(sum, in32, in32); + + in32 = read_q15x2_ia ((q15_t **) &pSrc); + sum = __RV_SMALDA(sum, in32, in32); +#endif /* __RISCV_XLEN == 64 */ +#else + in = *pSrc++; + sum += ((q31_t) in * in); + + in = *pSrc++; + sum += ((q31_t) in * in); + + in = *pSrc++; + sum += ((q31_t) in * in); + + in = *pSrc++; + sum += ((q31_t) in * in); +#endif /* #if defined (RISCV_MATH_DSP) */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + /* Compute Power and store result in a temporary variable, sum. */ + in = *pSrc++; + sum += ((q31_t) in * in); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store result in 34.30 format */ + *pResult = sum; +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of power group + */ diff --git a/components/nmsis/dsp/src/StatisticsFunctions/riscv_power_q31.c b/components/nmsis/dsp/src/StatisticsFunctions/riscv_power_q31.c new file mode 100644 index 00000000..9c578817 --- /dev/null +++ b/components/nmsis/dsp/src/StatisticsFunctions/riscv_power_q31.c @@ -0,0 +1,151 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_power_q31.c + * Description: Sum of the squares of the elements of a Q31 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup power + @{ + */ + +/** + @brief Sum of the squares of the elements of a Q31 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult sum of the squares value returned here + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + The input is represented in 1.31 format. + Intermediate multiplication yields a 2.62 format, and this + result is truncated to 2.48 format by discarding the lower 14 bits. + The 2.48 result is then added without saturation to a 64-bit accumulator in 16.48 format. + With 15 guard bits in the accumulator, there is no risk of overflow, and the + full precision of the intermediate multiplication is preserved. + Finally, the return result is in 16.48 format. + */ +void riscv_power_q31( + const q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + size_t l; + const q31_t * input = pSrc; + q63_t * output = pResult; + vint32m4_t v_in; + vint64m8_t v_in2; + l = vsetvl_e64m1(1); + vint64m1_t v_sum = vmv_s_x_i64m1(v_sum, 0, l); + for (; (l = vsetvl_e32m4(blkCnt)) > 0; blkCnt -= l) + { + v_in = vle32_v_i32m4(input, l); + input += l; + v_in2 = vsra_vx_i64m8(vwmul_vv_i64m8(v_in, v_in, l), 14, l); + v_sum = vredsum_vs_i64m8_i64m1(v_sum, v_in2, v_sum, l); + } + l = vsetvl_e64m1(1); + vse64_v_i64m1(output, v_sum, l); +#else + uint32_t blkCnt; /* Loop counter */ + q63_t sum = 0; /* Temporary result storage */ + q31_t in; /* Temporary variable to store input value */ +#if __RISCV_XLEN == 64 + q63_t in64; /* Temporary variable to store input value */ +#endif /* __RISCV_XLEN == 64 */ +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ +#if __RISCV_XLEN == 64 + in64 = read_q31x2_ia ((q31_t **) &pSrc); + sum += __RV_SMBB32(in64, in64); + sum += __RV_SMTT32(in64, in64); + in64 = read_q31x2_ia ((q31_t **) &pSrc); + sum += __RV_SMBB32(in64, in64); + sum += __RV_SMTT32(in64, in64); +#else + /* Compute Power then shift intermediate results by 14 bits to maintain 16.48 format and store result in a temporary variable sum, providing 15 guard bits. */ + in = *pSrc++; + sum += ((q63_t) in * in) >> 14U; + + in = *pSrc++; + sum += ((q63_t) in * in) >> 14U; + + in = *pSrc++; + sum += ((q63_t) in * in) >> 14U; + + in = *pSrc++; + sum += ((q63_t) in * in) >> 14U; +#endif /* __RISCV_XLEN == 64 */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + /* Compute Power and store result in a temporary variable, sum. */ + in = *pSrc++; + sum += ((q63_t) in * in) >> 14U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store results in 16.48 format */ + *pResult = sum; +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of power group + */ diff --git a/components/nmsis/dsp/src/StatisticsFunctions/riscv_power_q7.c b/components/nmsis/dsp/src/StatisticsFunctions/riscv_power_q7.c new file mode 100644 index 00000000..ff2ef5e3 --- /dev/null +++ b/components/nmsis/dsp/src/StatisticsFunctions/riscv_power_q7.c @@ -0,0 +1,167 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_power_q7.c + * Description: Sum of the squares of the elements of a Q7 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup power + @{ + */ + +/** + @brief Sum of the squares of the elements of a Q7 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult sum of the squares value returned here + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 32-bit internal accumulator. + The input is represented in 1.7 format. + Intermediate multiplication yields a 2.14 format, and this + result is added without saturation to an accumulator in 18.14 format. + With 17 guard bits in the accumulator, there is no risk of overflow, and the + full precision of the intermediate multiplication is preserved. + Finally, the return result is in 18.14 format. + */ +void riscv_power_q7( + const q7_t * pSrc, + uint32_t blockSize, + q31_t * pResult) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + size_t l; + const q7_t * input = pSrc; + q31_t * output = pResult; + vint8m4_t v_in; + vint16m8_t v_in2; + l = vsetvl_e32m1(1); + vint32m1_t v_sum = vmv_s_x_i32m1(v_sum, 0, l); + for (; (l = vsetvl_e8m4(blkCnt)) > 0; blkCnt -= l) + { + v_in = vle8_v_i8m4(input, l); + input += l; + v_in2 = vwmul_vv_i16m8(v_in, v_in, l); + v_sum = vwredsum_vs_i16m8_i32m1(v_sum, v_in2, v_sum, l); + } + l = vsetvl_e32m1(1); + vse32_v_i32m1(output, v_sum, l); +#else + uint32_t blkCnt; /* Loop counter */ + q31_t sum = 0; /* Temporary result storage */ + q7_t in; /* Temporary variable to store input value */ + +#if defined (RISCV_MATH_LOOPUNROLL) && defined (RISCV_MATH_DSP) +#if __RISCV_XLEN == 64 + q63_t in64,sum64 = 0; /* Temporary variable to store packed input value */ +#else + q31_t in32; /* Temporary variable to store packed input value */ +#endif /* __RISCV_XLEN == 64 */ +#endif + +#if defined (RISCV_MATH_LOOPUNROLL) +#if __RISCV_XLEN == 64 + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 3U; +#else + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; +#endif /* __RISCV_XLEN == 64 */ + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + /* Compute Power and store result in a temporary variable, sum. */ +#if defined (RISCV_MATH_DSP) +#if __RISCV_XLEN == 64 + in64 = read_q7x8_ia ((q7_t **) &pSrc); + sum64 = __RV_SMAQA(sum64, in64, in64); +#else + in32 = read_q7x4_ia ((q7_t **) &pSrc); + sum = __RV_SMAQA(sum, in32, in32); +#endif /* __RISCV_XLEN == 64 */ +#else + in = *pSrc++; + sum += ((q15_t) in * in); + + in = *pSrc++; + sum += ((q15_t) in * in); + + in = *pSrc++; + sum += ((q15_t) in * in); + + in = *pSrc++; + sum += ((q15_t) in * in); +#endif /* #if defined (RISCV_MATH_DSP) */ + + /* Decrement loop counter */ + blkCnt--; + } +#if __RISCV_XLEN == 64 + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x8U; + sum = (q31_t) ((sum64 >> 32U) + ((sum64 << 32U) >> 32U)); +#else + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; +#endif /* __RISCV_XLEN == 64 */ + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + /* Compute Power and store result in a temporary variable, sum. */ + in = *pSrc++; + sum += ((q15_t) in * in); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store result in 18.14 format */ + *pResult = sum; +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of power group + */ diff --git a/components/nmsis/dsp/src/StatisticsFunctions/riscv_rms_f16.c b/components/nmsis/dsp/src/StatisticsFunctions/riscv_rms_f16.c new file mode 100644 index 00000000..7710f740 --- /dev/null +++ b/components/nmsis/dsp/src/StatisticsFunctions/riscv_rms_f16.c @@ -0,0 +1,132 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_rms_f16.c + * Description: Root mean square value of the elements of a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions_f16.h" + +#if defined(RISCV_FLOAT16_SUPPORTED) + + +/** + @ingroup groupStats + */ + +/** + @defgroup RMS Root mean square (RMS) + + Calculates the Root Mean Square of the elements in the input vector. + The underlying algorithm is used: + + 
+      Result = sqrt(((pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + ... + pSrc[blockSize-1] * pSrc[blockSize-1]) / blockSize));
+
+ + There are separate functions for floating point, Q31, and Q15 data types. + */ + +/** + @addtogroup RMS + @{ + */ + +/** + @brief Root Mean Square of the elements of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult root mean square value returned here + @return none + */ + + +void riscv_rms_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + _Float16 sum = 0.0f16; /* Temporary result storage */ + _Float16 in; /* Temporary variable to store input value */ + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + in = *pSrc++; + /* Compute sum of squares and store result in a temporary variable, sum. */ + sum += in * in; + + in = *pSrc++; + sum += in * in; + + in = *pSrc++; + sum += in * in; + + in = *pSrc++; + sum += in * in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + in = *pSrc++; + /* Compute sum of squares and store result in a temporary variable. */ + sum += ( in * in); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Compute Rms and store result in destination */ + riscv_sqrt_f16(sum / (float16_t) blockSize, pResult); +} + +/** + @} end of RMS group + */ + +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ + diff --git a/components/nmsis/dsp/src/StatisticsFunctions/riscv_rms_f32.c b/components/nmsis/dsp/src/StatisticsFunctions/riscv_rms_f32.c new file mode 100644 index 00000000..1f3afa68 --- /dev/null +++ b/components/nmsis/dsp/src/StatisticsFunctions/riscv_rms_f32.c @@ -0,0 +1,147 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_rms_f32.c + * Description: Root mean square value of the elements of a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @defgroup RMS Root mean square (RMS) + + Calculates the Root Mean Square of the elements in the input vector. + The underlying algorithm is used: + + 
+      Result = sqrt(((pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + ... + pSrc[blockSize-1] * pSrc[blockSize-1]) / blockSize));
+
+ + There are separate functions for floating point, Q31, and Q15 data types. + */ + +/** + @addtogroup RMS + @{ + */ + +/** + @brief Root Mean Square of the elements of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult root mean square value returned here + @return none + */ + +void riscv_rms_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + size_t l; + float32_t sum = 0.0f; /* Temporary result storage */ + const float32_t * input = pSrc; + float32_t * output = pResult; + vfloat32m8_t v_in; + vfloat32m8_t v_in2; + l = vsetvl_e32m1(1); + vfloat32m1_t v_sum = vfmv_s_f_f32m1(v_sum, 0.0f, l); + for (; (l = vsetvl_e32m8(blkCnt)) > 0; blkCnt -= l) + { + v_in = vle32_v_f32m8(input, l); + input +=l; + v_in2 = vfmul_vv_f32m8(v_in, v_in, l); + v_sum = vfredsum_vs_f32m8_f32m1(v_sum, v_in2, v_sum, l); + } + l = vsetvl_e32m1(1); + sum = vfmv_f_s_f32m1_f32(v_sum); + riscv_sqrt_f32(sum / (float32_t) blockSize, output); +#else + uint32_t blkCnt; /* Loop counter */ + float32_t sum = 0.0f; /* Temporary result storage */ + float32_t in; /* Temporary variable to store input value */ + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + in = *pSrc++; + /* Compute sum of squares and store result in a temporary variable, sum. */ + sum += in * in; + + in = *pSrc++; + sum += in * in; + + in = *pSrc++; + sum += in * in; + + in = *pSrc++; + sum += in * in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + in = *pSrc++; + /* Compute sum of squares and store result in a temporary variable. */ + sum += ( in * in); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Compute Rms and store result in destination */ + riscv_sqrt_f32(sum / (float32_t) blockSize, pResult); +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of RMS group + */ diff --git a/components/nmsis/dsp/src/StatisticsFunctions/riscv_rms_q15.c b/components/nmsis/dsp/src/StatisticsFunctions/riscv_rms_q15.c new file mode 100644 index 00000000..05a0400d --- /dev/null +++ b/components/nmsis/dsp/src/StatisticsFunctions/riscv_rms_q15.c @@ -0,0 +1,161 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_rms_q15.c + * Description: Root Mean Square of the elements of a Q15 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup RMS + @{ + */ + +/** + @brief Root Mean Square of the elements of a Q15 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult root mean square value returned here + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + The input is represented in 1.15 format. + Intermediate multiplication yields a 2.30 format, and this + result is added without saturation to a 64-bit accumulator in 34.30 format. + With 33 guard bits in the accumulator, there is no risk of overflow, and the + full precision of the intermediate multiplication is preserved. + Finally, the 34.30 result is truncated to 34.15 format by discarding the lower + 15 bits, and then saturated to yield a result in 1.15 format. + */ +void riscv_rms_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + size_t l; + const q15_t * input = pSrc; + q15_t * result = pResult; + q63_t sum; + vint16m4_t v_in; + l = vsetvl_e64m1(1); + vint64m1_t v_sum = vmv_s_x_i64m1(v_sum, 0, l); /* init v_sum data= vmv_s_x_i64m1(v_sum, 0) */ + for (; (l = vsetvl_e16m4(blkCnt)) > 0; blkCnt -= l) { + v_in = vle16_v_i16m4(input, l); + input += l; + v_sum = vwredsum_vs_i32m8_i64m1(v_sum, vwmul_vv_i32m8(v_in, v_in, l) ,v_sum, l); + } + l = vsetvl_e64m1(1); + sum = vmv_x_s_i64m1_i64(v_sum); + riscv_sqrt_q15(__SSAT((sum / (q63_t)blockSize) >> 15, 16), result); +#else + uint32_t blkCnt; /* Loop counter */ + q63_t sum = 0; /* Temporary result storage */ + q15_t in; /* Temporary variable to store input value */ + +#if defined (RISCV_MATH_LOOPUNROLL) && defined (RISCV_MATH_DSP) +#if __RISCV_XLEN == 64 + q63_t in64; /* Temporary variable to store packed input value */ +#endif /* __RISCV_XLEN == 64 */ + q31_t in32; /* Temporary variable to store input value */ +#endif + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + /* Compute sum of squares and store result in a temporary variable. */ +#if defined (RISCV_MATH_DSP) +#if __RISCV_XLEN == 64 + in64 = read_q15x4_ia ((q15_t **) &pSrc); + sum = __RV_SMALDA(sum, in64, in64); +#else + in32 = read_q15x2_ia ((q15_t **) &pSrc); + sum = __SMLALD(in32, in32, sum); + + in32 = read_q15x2_ia ((q15_t **) &pSrc); + sum = __SMLALD(in32, in32, sum); +#endif +#else + in = *pSrc++; + sum += ((q31_t) in * in); + + in = *pSrc++; + sum += ((q31_t) in * in); + + in = *pSrc++; + sum += ((q31_t) in * in); + + in = *pSrc++; + sum += ((q31_t) in * in); +#endif /* #if defined (RISCV_MATH_DSP) */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + in = *pSrc++; + /* Compute sum of squares and store result in a temporary variable. */ + sum += ((q31_t) in * in); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Truncating and saturating the accumulator to 1.15 format */ + /* Store result in destination */ + riscv_sqrt_q15(__SSAT((sum / (q63_t)blockSize) >> 15, 16), pResult); +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of RMS group + */ diff --git a/components/nmsis/dsp/src/StatisticsFunctions/riscv_rms_q31.c b/components/nmsis/dsp/src/StatisticsFunctions/riscv_rms_q31.c new file mode 100644 index 00000000..4153dd19 --- /dev/null +++ b/components/nmsis/dsp/src/StatisticsFunctions/riscv_rms_q31.c @@ -0,0 +1,154 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_rms_q31.c + * Description: Root Mean Square of the elements of a Q31 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup RMS + @{ + */ + +/** + @brief Root Mean Square of the elements of a Q31 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult root mean square value returned here + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The input is represented in 1.31 format, and intermediate multiplication + yields a 2.62 format. + The accumulator maintains full precision of the intermediate multiplication results, + but provides only a single guard bit. + There is no saturation on intermediate additions. + If the accumulator overflows, it wraps around and distorts the result. + In order to avoid overflows completely, the input signal must be scaled down by + log2(blockSize) bits, as a total of blockSize additions are performed internally. + Finally, the 2.62 accumulator is right shifted by 31 bits to yield a 1.31 format value. + */ +void riscv_rms_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + size_t l; + const q31_t * input = pSrc; + q31_t * result = pResult; + q63_t sum; + vint32m4_t v_in; + l = vsetvl_e64m1(1); + vint64m1_t v_sum = vmv_s_x_i64m1(v_sum, 0, l); /* init v_sum data */ + for (; (l = vsetvl_e32m4(blkCnt)) > 0; blkCnt -= l) { + v_in = vle32_v_i32m4(input, l); + input += l; + v_sum = vredsum_vs_i64m8_i64m1(v_sum, vwmul_vv_i64m8(v_in, v_in, l) ,v_sum, l); + } + l = vsetvl_e64m1(1); + sum = vmv_x_s_i64m1_i64(v_sum); + riscv_sqrt_q31(clip_q63_to_q31((sum / (q63_t) blockSize) >> 31), result); +#else + uint32_t blkCnt; /* Loop counter */ + uint64_t sum = 0; /* Temporary result storage (can get never negative. changed type from q63 to uint64 */ + q31_t in; /* Temporary variable to store input value */ +#if __RISCV_XLEN == 64 + q63_t in64; /* Temporary variable to store input value */ +#endif /* __RISCV_XLEN == 64 */ +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ +#if __RISCV_XLEN == 64 + in64 = read_q31x2_ia ((q31_t **) &pSrc); + sum += ((q63_t)__RV_SMBB32(in64, in64) >> 32); + sum += __RV_SMTT32(in64, in64); + in64 = read_q31x2_ia ((q31_t **) &pSrc); + sum += ((q63_t)__RV_SMBB32(in64, in64) >> 32); + sum += __RV_SMTT32(in64, in64); +#else + in = *pSrc++; + /* Compute sum of squares and store result in a temporary variable, sum. */ + sum += ((q63_t) in * in); + + in = *pSrc++; + sum += ((q63_t) in * in); + + in = *pSrc++; + sum += ((q63_t) in * in); + + in = *pSrc++; + sum += ((q63_t) in * in); + +#endif /* __RISCV_XLEN == 64 */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + in = *pSrc++; + /* Compute sum of squares and store result in a temporary variable. */ + sum += ((q63_t) in * in); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Convert data in 2.62 to 1.31 by 31 right shifts and saturate */ + /* Compute Rms and store result in destination vector */ + riscv_sqrt_q31(clip_q63_to_q31((sum / (q63_t) blockSize) >> 31), pResult); +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of RMS group + */ diff --git a/components/nmsis/dsp/src/StatisticsFunctions/riscv_std_f16.c b/components/nmsis/dsp/src/StatisticsFunctions/riscv_std_f16.c new file mode 100644 index 00000000..b3ec07f1 --- /dev/null +++ b/components/nmsis/dsp/src/StatisticsFunctions/riscv_std_f16.c @@ -0,0 +1,68 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_std_f16.c + * Description: Standard deviation of the elements of a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions_f16.h" + +#if defined(RISCV_FLOAT16_SUPPORTED) + + +/** + @ingroup groupStats + */ + + + +/** + @addtogroup STD + @{ + */ + +/** + @brief Standard deviation of the elements of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult standard deviation value returned here + @return none + */ +void riscv_std_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult) +{ + float16_t var; + riscv_var_f16(pSrc,blockSize,&var); + riscv_sqrt_f16(var, pResult); +} + +/** + @} end of STD group + */ + +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ + diff --git a/components/nmsis/dsp/src/StatisticsFunctions/riscv_std_f32.c b/components/nmsis/dsp/src/StatisticsFunctions/riscv_std_f32.c new file mode 100644 index 00000000..c58e1a96 --- /dev/null +++ b/components/nmsis/dsp/src/StatisticsFunctions/riscv_std_f32.c @@ -0,0 +1,84 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_std_f32.c + * Description: Standard deviation of the elements of a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @defgroup STD Standard deviation + + Calculates the standard deviation of the elements in the input vector. + + The float implementation is relying on riscv_var_f32 which is using a two-pass algorithm + to avoid problem of numerical instabilities and cancellation errors. + + Fixed point versions are using the standard textbook algorithm since the fixed point + numerical behavior is different from the float one. + + Algorithm for fixed point versions is summarized below: + + + 
+      Result = sqrt((sumOfSquares - sum2 / blockSize) / (blockSize - 1))
+
+      sumOfSquares = pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + ... + pSrc[blockSize-1] * pSrc[blockSize-1]
+      sum = pSrc[0] + pSrc[1] + pSrc[2] + ... + pSrc[blockSize-1]
+
+ + There are separate functions for floating point, Q31, and Q15 data types. + */ + +/** + @addtogroup STD + @{ + */ + +/** + @brief Standard deviation of the elements of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult standard deviation value returned here + @return none + */ +void riscv_std_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ + float32_t var; + riscv_var_f32(pSrc,blockSize,&var); + riscv_sqrt_f32(var, pResult); +} + +/** + @} end of STD group + */ diff --git a/components/nmsis/dsp/src/StatisticsFunctions/riscv_std_q15.c b/components/nmsis/dsp/src/StatisticsFunctions/riscv_std_q15.c new file mode 100644 index 00000000..6ca28dfc --- /dev/null +++ b/components/nmsis/dsp/src/StatisticsFunctions/riscv_std_q15.c @@ -0,0 +1,208 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_std_q15.c + * Description: Standard deviation of an array of Q15 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup STD + @{ + */ + +/** + @brief Standard deviation of the elements of a Q15 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult standard deviation value returned here + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + The input is represented in 1.15 format. + Intermediate multiplication yields a 2.30 format, and this + result is added without saturation to a 64-bit accumulator in 34.30 format. + With 33 guard bits in the accumulator, there is no risk of overflow, and the + full precision of the intermediate multiplication is preserved. + Finally, the 34.30 result is truncated to 34.15 format by discarding the lower + 15 bits, and then saturated to yield a result in 1.15 format. + */ +void riscv_std_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + q31_t sum = 0; /* Accumulator */ + q31_t meanOfSquares, squareOfMean; /* Square of mean and mean of square */ + q63_t sumOfSquares = 0; /* Sum of squares */ + size_t l; + const q15_t * input = pSrc; + q15_t * output = pResult; + vint16m4_t v_in; /* Temporary variable to store input value */ + vint32m8_t v_in2; + l = vsetvl_e64m1(1); + vint64m1_t v_sumOfSquares = vmv_s_x_i64m1(v_sumOfSquares, 0, l); + vint32m1_t v_sum = vmv_s_x_i32m1(v_sum, 0, l); + for (; (l = vsetvl_e16m4(blkCnt)) > 0; blkCnt -= l) + { + v_in = vle16_v_i16m4(input, l); + input += l; + v_in2 = vwmul_vv_i32m8(v_in, v_in, l); + v_sum = vwredsum_vs_i16m4_i32m1(v_sum, v_in, v_sum, l); + v_sumOfSquares = vwredsum_vs_i32m8_i64m1(v_sumOfSquares, v_in2, v_sumOfSquares, l); + } + l = vsetvl_e64m1(1); + sum = vmv_x_s_i32m1_i32(v_sum); + sumOfSquares = vmv_x_s_i64m1_i64(v_sumOfSquares); + /* Compute Mean of squares and store result in a temporary variable, meanOfSquares. */ + meanOfSquares = (q31_t) (sumOfSquares / (q63_t)(blockSize - 1U)); + + /* Compute square of mean */ + squareOfMean = (q31_t) ((q63_t) sum * sum / (q63_t)(blockSize * (blockSize - 1U))); + + /* mean of squares minus the square of mean. */ + /* Compute standard deviation and store result in destination */ + riscv_sqrt_q15(__SSAT((meanOfSquares - squareOfMean) >> 15U, 16U), pResult); +#else + uint32_t blkCnt; /* Loop counter */ + q31_t sum = 0; /* Accumulator */ + q31_t meanOfSquares, squareOfMean; /* Square of mean and mean of square */ + q63_t sumOfSquares = 0; /* Sum of squares */ + q15_t in; /* Temporary variable to store input value */ + +#if defined (RISCV_MATH_LOOPUNROLL) && defined (RISCV_MATH_DSP) +#if __RISCV_XLEN == 64 + q63_t in64,sum64; +#endif /* __RISCV_XLEN == 64 */ + q31_t in32; /* Temporary variable to store input value */ +#endif + + if (blockSize <= 1U) + { + *pResult = 0; + return; + } + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + /* C = A[0] + A[1] + ... + A[blockSize-1] */ + + /* Compute sum of squares and store result in a temporary variable, sumOfSquares. */ + /* Compute sum and store result in a temporary variable, sum. */ +#if defined (RISCV_MATH_DSP) +#if __RISCV_XLEN == 64 + in64 = read_q15x4_ia ((q15_t **) &pSrc); + sumOfSquares = __RV_SMALDA(sumOfSquares, in64, in64); + sum += ((q31_t)((in64 << 48U) >> 48U)); + sum += ((q31_t)((in64 << 32U) >> 48U)); + sum += ((q31_t)((in64 << 16U) >> 48U)); + sum += ((q31_t)((in64 ) >> 48U)); +#else + in32 = read_q15x2_ia ((q15_t **) &pSrc); + sumOfSquares = __SMLALD(in32, in32, sumOfSquares); + sum += ((in32 << 16U) >> 16U); + sum += (in32 >> 16U); + + in32 = read_q15x2_ia ((q15_t **) &pSrc); + sumOfSquares = __SMLALD(in32, in32, sumOfSquares); + sum += ((in32 << 16U) >> 16U); + sum += (in32 >> 16U); +#endif /* __RISCV_XLEN == 64 */ +#else + in = *pSrc++; + sumOfSquares += (in * in); + sum += in; + + in = *pSrc++; + sumOfSquares += (in * in); + sum += in; + + in = *pSrc++; + sumOfSquares += (in * in); + sum += in; + + in = *pSrc++; + sumOfSquares += (in * in); + sum += in; +#endif /* #if defined (RISCV_MATH_DSP) */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + /* C = A[0] + A[1] + ... + A[blockSize-1] */ + + in = *pSrc++; + /* Compute sum of squares and store result in a temporary variable, sumOfSquares. */ + sumOfSquares += (in * in); + /* Compute sum and store result in a temporary variable, sum. */ + sum += in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Compute Mean of squares and store result in a temporary variable, meanOfSquares. */ + meanOfSquares = (q31_t) (sumOfSquares / (q63_t)(blockSize - 1U)); + + /* Compute square of mean */ + squareOfMean = (q31_t) ((q63_t) sum * sum / (q63_t)(blockSize * (blockSize - 1U))); + + /* mean of squares minus the square of mean. */ + /* Compute standard deviation and store result in destination */ + riscv_sqrt_q15(__SSAT((meanOfSquares - squareOfMean) >> 15U, 16U), pResult); +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of STD group + */ diff --git a/components/nmsis/dsp/src/StatisticsFunctions/riscv_std_q31.c b/components/nmsis/dsp/src/StatisticsFunctions/riscv_std_q31.c new file mode 100644 index 00000000..f1894736 --- /dev/null +++ b/components/nmsis/dsp/src/StatisticsFunctions/riscv_std_q31.c @@ -0,0 +1,197 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_std_q31.c + * Description: Standard deviation of the elements of a Q31 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup STD + @{ + */ + +/** + @brief Standard deviation of the elements of a Q31 vector. + @param[in] pSrc points to the input vector. + @param[in] blockSize number of samples in input vector. + @param[out] pResult standard deviation value returned here. + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The input is represented in 1.31 format, which is then downshifted by 8 bits + which yields 1.23, and intermediate multiplication yields a 2.46 format. + The accumulator maintains full precision of the intermediate multiplication results, + but provides only a 16 guard bits. + There is no saturation on intermediate additions. + If the accumulator overflows it wraps around and distorts the result. + In order to avoid overflows completely the input signal must be scaled down by + log2(blockSize)-8 bits, as a total of blockSize additions are performed internally. + After division, internal variables should be Q18.46 + Finally, the 18.46 accumulator is right shifted by 15 bits to yield a 1.31 format value. + */ +void riscv_std_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + q63_t sum = 0; /* Temporary result storage */ + q63_t meanOfSquares, squareOfMean; /* Square of mean and mean of square */ + q63_t sumOfSquares = 0; /* Sum of squares */ + size_t l; + const q31_t * input = pSrc; + q31_t * output = pResult; + vint32m4_t v_in; /* Temporary variable to store input value */ + vint64m8_t v_in2; + l = vsetvl_e64m1(1); + vint64m1_t v_sumOfSquares = vmv_s_x_i64m1(v_sumOfSquares, 0, l); + vint64m1_t v_sum = vmv_s_x_i64m1(v_sum, 0, l); + for (; (l = vsetvl_e32m4(blkCnt)) > 0; blkCnt -= l) + { + v_in = vsra_vx_i32m4(vle32_v_i32m4(input, l), 8U, l); + input += l; + v_in2 = vwmul_vv_i64m8(v_in, v_in, l); + v_sum = vwredsum_vs_i32m4_i64m1(v_sum, v_in, v_sum, l); + v_sumOfSquares = vredsum_vs_i64m8_i64m1(v_sumOfSquares, v_in2, v_sumOfSquares, l); + } + l = vsetvl_e64m1(1); + sum = vmv_x_s_i64m1_i64(v_sum); + sumOfSquares = vmv_x_s_i64m1_i64(v_sumOfSquares); + /* Compute Mean of squares and store result in a temporary variable, meanOfSquares. */ + meanOfSquares = (sumOfSquares / (q63_t)(blockSize - 1U)); + + /* Compute square of mean */ + squareOfMean = ( sum * sum / (q63_t)(blockSize * (blockSize - 1U))); + + /* Compute standard deviation and store result in destination */ + riscv_sqrt_q31((meanOfSquares - squareOfMean) >> 15U, pResult); +#else + uint32_t blkCnt; /* Loop counter */ + q63_t sum = 0; /* Accumulator */ + q63_t meanOfSquares, squareOfMean; /* Square of mean and mean of square */ + q63_t sumOfSquares = 0; /* Sum of squares */ + q31_t in; /* Temporary variable to store input value */ +#if __RISCV_XLEN == 64 + q63_t in64A,in64B; /* Temporary variable to store input value */ +#endif /* __RISCV_XLEN == 64 */ + if (blockSize <= 1U) + { + *pResult = 0; + return; + } + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + /* C = A[0] + A[1] + ... + A[blockSize-1] */ +#if __RISCV_XLEN == 64 + in64A = read_q31x2_ia ((q31_t **) &pSrc); + in64A = (((int64_t)(in64A << 32)) >> 40) | ((((int64_t) in64A) >> 40) << 32); + sumOfSquares += ((q63_t)__RV_SMBB32(in64A, in64A) >> 32); + sumOfSquares += __RV_SMTT32(in64A, in64A); + in64B = read_q31x2_ia ((q31_t **) &pSrc); + in64B = (((int64_t)(in64B << 32)) >> 40) | ((((int64_t) in64B) >> 40) << 32); + sumOfSquares += ((q63_t)__RV_SMBB32(in64B, in64B) >> 32); + sumOfSquares += __RV_SMTT32(in64B, in64B); + + in64A = __RV_ADD32(in64A,in64B); + sum += (((int64_t)__RV_CRAS32(in64A,in64A)) >> 32); + +#else + in = *pSrc++ >> 8U; + /* Compute sum of squares and store result in a temporary variable, sumOfSquares. */ + sumOfSquares += ((q63_t) (in) * (in)); + /* Compute sum and store result in a temporary variable, sum. */ + sum += in; + + in = *pSrc++ >> 8U; + sumOfSquares += ((q63_t) (in) * (in)); + sum += in; + + in = *pSrc++ >> 8U; + sumOfSquares += ((q63_t) (in) * (in)); + sum += in; + + in = *pSrc++ >> 8U; + sumOfSquares += ((q63_t) (in) * (in)); + sum += in; +#endif /* __RISCV_XLEN == 64 */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + /* C = A[0] + A[1] + ... + A[blockSize-1] */ + + in = *pSrc++ >> 8U; + /* Compute sum of squares and store result in a temporary variable, sumOfSquares. */ + sumOfSquares += ((q63_t) (in) * (in)); + /* Compute sum and store result in a temporary variable, sum. */ + sum += in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Compute Mean of squares and store result in a temporary variable, meanOfSquares. */ + meanOfSquares = (sumOfSquares / (q63_t)(blockSize - 1U)); + + /* Compute square of mean */ + squareOfMean = ( sum * sum / (q63_t)(blockSize * (blockSize - 1U))); + + /* Compute standard deviation and store result in destination */ + riscv_sqrt_q31((meanOfSquares - squareOfMean) >> 15U, pResult); +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of STD group + */ diff --git a/components/nmsis/dsp/src/StatisticsFunctions/riscv_var_f16.c b/components/nmsis/dsp/src/StatisticsFunctions/riscv_var_f16.c new file mode 100644 index 00000000..4d1649e2 --- /dev/null +++ b/components/nmsis/dsp/src/StatisticsFunctions/riscv_var_f16.c @@ -0,0 +1,166 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_var_f16.c + * Description: Variance of the elements of a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions_f16.h" + + +#if defined(RISCV_FLOAT16_SUPPORTED) + + +/** + @ingroup groupStats + */ + + +/** + @addtogroup variance + @{ + */ + +/** + @brief Variance of the elements of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult variance value returned here + @return none + */ + +void riscv_var_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + _Float16 sum = 0.0f; /* Temporary result storage */ + _Float16 fSum = 0.0f; + _Float16 fMean, fValue; + const float16_t * pInput = pSrc; + + if (blockSize <= 1U) + { + *pResult = 0; + return; + } + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + + sum += *pInput++; + sum += *pInput++; + sum += *pInput++; + sum += *pInput++; + + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + + sum += *pInput++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize */ + fMean = sum / (float16_t) blockSize; + + pInput = pSrc; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + fValue = *pInput++ - fMean; + fSum += fValue * fValue; + + fValue = *pInput++ - fMean; + fSum += fValue * fValue; + + fValue = *pInput++ - fMean; + fSum += fValue * fValue; + + fValue = *pInput++ - fMean; + fSum += fValue * fValue; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + fValue = *pInput++ - fMean; + fSum += fValue * fValue; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Variance */ + *pResult = fSum / (float16_t)(blockSize - 1.0f); +} + +/** + @} end of variance group + */ + +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ + diff --git a/components/nmsis/dsp/src/StatisticsFunctions/riscv_var_f32.c b/components/nmsis/dsp/src/StatisticsFunctions/riscv_var_f32.c new file mode 100644 index 00000000..eb9eb26c --- /dev/null +++ b/components/nmsis/dsp/src/StatisticsFunctions/riscv_var_f32.c @@ -0,0 +1,209 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_var_f32.c + * Description: Variance of the elements of a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @defgroup variance Variance + + Calculates the variance of the elements in the input vector. + The underlying algorithm used is the direct method sometimes referred to as the two-pass method: + + 
+      Result = sum(element - meanOfElements)^2) / numElement - 1
+
+      meanOfElements = ( pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + ... + pSrc[blockSize-1] ) / blockSize
+
+ + There are separate functions for floating point, Q31, and Q15 data types. + */ + +/** + @addtogroup variance + @{ + */ + +/** + @brief Variance of the elements of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult variance value returned here + @return none + */ +void riscv_var_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + float32_t sum = 0.0f; /* Temporary result storage */ + float32_t fSum = 0.0f; + float32_t fMean, fValue; + size_t l; + const float32_t * input = pSrc; + float32_t * output = pResult; + vfloat32m8_t v_in; /* Temporary variable to store input value */ + vfloat32m8_t v_fValue; + l = vsetvl_e32m1(1); + vfloat32m1_t v_fSum = vfmv_s_f_f32m1(v_fSum, 0.0f, l); + vfloat32m1_t v_sum = vfmv_s_f_f32m1(v_sum, 0.0f, l); + for (; (l = vsetvl_e32m8(blkCnt)) > 0; blkCnt -= l) + { + v_in = vle32_v_f32m8(input, l); + input += l; + v_sum = vfredsum_vs_f32m8_f32m1(v_sum, v_in, v_sum, l); + } + l = vsetvl_e32m1(1); + sum = vfmv_f_s_f32m1_f32(v_sum); + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize */ + fMean = sum / (float32_t) blockSize; + input = pSrc; + for (blkCnt = blockSize; (l = vsetvl_e32m8(blkCnt)) > 0; blkCnt -= l) + { + v_in = vle32_v_f32m8(input, l); + input += l; + v_fValue = vfsub_vf_f32m8(v_in, fMean, l); + v_fSum = vfredsum_vs_f32m8_f32m1(v_fSum, vfmul_vv_f32m8(v_fValue, v_fValue, l), v_fSum, l); + } + l = vsetvl_e32m1(1); + fSum = vfmv_f_s_f32m1_f32(v_fSum); + /* Variance */ + *output = fSum / (float32_t)(blockSize - 1.0f); +#else + uint32_t blkCnt; /* Loop counter */ + float32_t sum = 0.0f; /* Temporary result storage */ + float32_t fSum = 0.0f; + float32_t fMean, fValue; + const float32_t * pInput = pSrc; + + if (blockSize <= 1U) + { + *pResult = 0; + return; + } + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + + sum += *pInput++; + sum += *pInput++; + sum += *pInput++; + sum += *pInput++; + + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + + sum += *pInput++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize */ + fMean = sum / (float32_t) blockSize; + + pInput = pSrc; + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + fValue = *pInput++ - fMean; + fSum += fValue * fValue; + + fValue = *pInput++ - fMean; + fSum += fValue * fValue; + + fValue = *pInput++ - fMean; + fSum += fValue * fValue; + + fValue = *pInput++ - fMean; + fSum += fValue * fValue; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + fValue = *pInput++ - fMean; + fSum += fValue * fValue; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Variance */ + *pResult = fSum / (float32_t)(blockSize - 1.0f); +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of variance group + */ diff --git a/components/nmsis/dsp/src/StatisticsFunctions/riscv_var_q15.c b/components/nmsis/dsp/src/StatisticsFunctions/riscv_var_q15.c new file mode 100644 index 00000000..242c10f7 --- /dev/null +++ b/components/nmsis/dsp/src/StatisticsFunctions/riscv_var_q15.c @@ -0,0 +1,210 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_var_q15.c + * Description: Variance of an array of Q15 type + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup variance + @{ + */ + +/** + @brief Variance of the elements of a Q15 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult variance value returned here + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + The input is represented in 1.15 format. + Intermediate multiplication yields a 2.30 format, and this + result is added without saturation to a 64-bit accumulator in 34.30 format. + With 33 guard bits in the accumulator, there is no risk of overflow, and the + full precision of the intermediate multiplication is preserved. + Finally, the 34.30 result is truncated to 34.15 format by discarding the lower + 15 bits, and then saturated to yield a result in 1.15 format. + */ +void riscv_var_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + q31_t sum = 0; /* Accumulator */ + q31_t meanOfSquares, squareOfMean; /* Square of mean and mean of square */ + q63_t sumOfSquares = 0; /* Sum of squares */ + size_t l; + const q15_t * input = pSrc; + q15_t * output = pResult; + vint16m4_t v_in; /* Temporary variable to store input value */ + vint32m8_t v_in2; + l = vsetvl_e64m1(1); + vint64m1_t v_sumOfSquares = vmv_s_x_i64m1(v_sumOfSquares, 0, l); + vint32m1_t v_sum = vmv_s_x_i32m1(v_sum, 0, l); + for (; (l = vsetvl_e16m4(blkCnt)) > 0; blkCnt -= l) + { + v_in = vle16_v_i16m4(input, l); + input += l; + v_in2 = vwmul_vv_i32m8(v_in, v_in, l); + v_sum = vwredsum_vs_i16m4_i32m1(v_sum, v_in, v_sum, l); + v_sumOfSquares = vwredsum_vs_i32m8_i64m1(v_sumOfSquares, v_in2, v_sumOfSquares, l); + } + l = vsetvl_e64m1(1); + sum = vmv_x_s_i32m1_i32(v_sum); + sumOfSquares = vmv_x_s_i64m1_i64(v_sumOfSquares); + /* Compute Mean of squares and store result in a temporary variable, meanOfSquares. */ + meanOfSquares = (q31_t) (sumOfSquares / (q63_t)(blockSize - 1U)); + + /* Compute square of mean */ + squareOfMean = (q31_t) ((q63_t) sum * sum / (q63_t)(blockSize * (blockSize - 1U))); + + /* mean of squares minus the square of mean. */ + *pResult = (meanOfSquares - squareOfMean) >> 15U; +#else + uint32_t blkCnt; /* Loop counter */ + q31_t sum = 0; /* Accumulator */ + q31_t meanOfSquares, squareOfMean; /* Square of mean and mean of square */ + q63_t sumOfSquares = 0; /* Sum of squares */ + q15_t in; /* Temporary variable to store input value */ + +#if defined (RISCV_MATH_LOOPUNROLL) && defined (RISCV_MATH_DSP) +#if __RISCV_XLEN == 64 + q63_t in64,sum64; +#endif /* __RISCV_XLEN == 64 */ + q31_t in32; /* Temporary variable to store input value */ +#endif + + if (blockSize <= 1U) + { + *pResult = 0; + return; + } + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + /* C = A[0] + A[1] + ... + A[blockSize-1] */ + + /* Compute sum of squares and store result in a temporary variable, sumOfSquares. */ + /* Compute sum and store result in a temporary variable, sum. */ +#if defined (RISCV_MATH_DSP) +#if __RISCV_XLEN == 64 + in64 = read_q15x4_ia ((q15_t **) &pSrc); + sumOfSquares = __RV_SMALDA(sumOfSquares, in64, in64); + sum += ((q31_t)((in64 << 48U) >> 48U)); + sum += ((q31_t)((in64 << 32U) >> 48U)); + sum += ((q31_t)((in64 << 16U) >> 48U)); + sum += ((q31_t)((in64 ) >> 48U)); +#else + in32 = read_q15x2_ia ((q15_t **) &pSrc); + sumOfSquares = __SMLALD(in32, in32, sumOfSquares); + sum += ((in32 << 16U) >> 16U); + sum += (in32 >> 16U); + + in32 = read_q15x2_ia ((q15_t **) &pSrc); + sumOfSquares = __SMLALD(in32, in32, sumOfSquares); + sum += ((in32 << 16U) >> 16U); + sum += (in32 >> 16U); +#endif /* __RISCV_XLEN == 64 */ +#else + in = *pSrc++; + sumOfSquares += (in * in); + sum += in; + + in = *pSrc++; + sumOfSquares += (in * in); + sum += in; + + in = *pSrc++; + sumOfSquares += (in * in); + sum += in; + + in = *pSrc++; + sumOfSquares += (in * in); + sum += in; +#endif /* #if defined (RISCV_MATH_DSP) */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + /* C = A[0] + A[1] + ... + A[blockSize-1] */ + + in = *pSrc++; + /* Compute sum of squares and store result in a temporary variable, sumOfSquares. */ +#if defined (RISCV_MATH_DSP) + sumOfSquares = __SMLALD(in, in, sumOfSquares); +#else + sumOfSquares += (in * in); +#endif /* #if defined (RISCV_MATH_DSP) */ + /* Compute sum and store result in a temporary variable, sum. */ + sum += in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Compute Mean of squares and store result in a temporary variable, meanOfSquares. */ + meanOfSquares = (q31_t) (sumOfSquares / (q63_t)(blockSize - 1U)); + + /* Compute square of mean */ + squareOfMean = (q31_t) ((q63_t) sum * sum / (q63_t)(blockSize * (blockSize - 1U))); + + /* mean of squares minus the square of mean. */ + *pResult = (meanOfSquares - squareOfMean) >> 15U; +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of variance group + */ diff --git a/components/nmsis/dsp/src/StatisticsFunctions/riscv_var_q31.c b/components/nmsis/dsp/src/StatisticsFunctions/riscv_var_q31.c new file mode 100644 index 00000000..38112b97 --- /dev/null +++ b/components/nmsis/dsp/src/StatisticsFunctions/riscv_var_q31.c @@ -0,0 +1,195 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_var_q31.c + * Description: Variance of an array of Q31 type + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup variance + @{ + */ + +/** + @brief Variance of the elements of a Q31 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult variance value returned here + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The input is represented in 1.31 format, which is then downshifted by 8 bits + which yields 1.23, and intermediate multiplication yields a 2.46 format. + The accumulator maintains full precision of the intermediate multiplication results, + and as a consequence has only 16 guard bits. + There is no saturation on intermediate additions. + If the accumulator overflows it wraps around and distorts the result. + In order to avoid overflows completely the input signal must be scaled down by + log2(blockSize)-8 bits, as a total of blockSize additions are performed internally. + After division, internal variables should be Q18.46 + Finally, the 18.46 accumulator is right shifted by 15 bits to yield a 1.31 format value. + */ +void riscv_var_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + q63_t sum = 0; /* Temporary result storage */ + q63_t meanOfSquares, squareOfMean; /* Square of mean and mean of square */ + q63_t sumOfSquares = 0; /* Sum of squares */ + size_t l; + const q31_t * input = pSrc; + q31_t * output = pResult; + vint32m4_t v_in; /* Temporary variable to store input value */ + vint64m8_t v_in2; + l = vsetvl_e64m1(1); + vint64m1_t v_sumOfSquares = vmv_s_x_i64m1(v_sumOfSquares, 0, l); + vint64m1_t v_sum = vmv_s_x_i64m1(v_sum, 0, l); + for (; (l = vsetvl_e32m4(blkCnt)) > 0; blkCnt -= l) + { + v_in = vsra_vx_i32m4(vle32_v_i32m4(input, l), 8U, l); + input += l; + v_in2 = vwmul_vv_i64m8(v_in, v_in, l); + v_sum = vwredsum_vs_i32m4_i64m1(v_sum, v_in, v_sum, l); + v_sumOfSquares = vredsum_vs_i64m8_i64m1(v_sumOfSquares, v_in2, v_sumOfSquares, l); + } + l = vsetvl_e64m1(1); + sum = vmv_x_s_i64m1_i64(v_sum); + sumOfSquares = vmv_x_s_i64m1_i64(v_sumOfSquares); + /* Compute Mean of squares and store result in a temporary variable, meanOfSquares. */ + meanOfSquares = (sumOfSquares / (q63_t)(blockSize - 1U)); + + /* Compute square of mean */ + squareOfMean = ( sum * sum / (q63_t)(blockSize * (blockSize - 1U))); + + /* Compute variance and store result in destination */ + *output = (meanOfSquares - squareOfMean) >> 15U; +#else + uint32_t blkCnt; /* Loop counter */ + q63_t sum = 0; /* Temporary result storage */ + q63_t meanOfSquares, squareOfMean; /* Square of mean and mean of square */ + q63_t sumOfSquares = 0; /* Sum of squares */ + q31_t in; /* Temporary variable to store input value */ +#if __RISCV_XLEN == 64 + q63_t in64A,in64B; /* Temporary variable to store input value */ +#endif /* __RISCV_XLEN == 64 */ + if (blockSize <= 1U) + { + *pResult = 0; + return; + } + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + /* C = A[0] + A[1] + ... + A[blockSize-1] */ +#if __RISCV_XLEN == 64 + in64A = read_q31x2_ia ((q31_t **) &pSrc); + in64A = (((int64_t)(in64A << 32)) >> 40) | ((((int64_t) in64A) >> 40) << 32); + sumOfSquares += ((q63_t)__RV_SMBB32(in64A, in64A) >> 32); + sumOfSquares += __RV_SMTT32(in64A, in64A); + in64B = read_q31x2_ia ((q31_t **) &pSrc); + in64B = (((int64_t)(in64B << 32)) >> 40) | ((((int64_t) in64B) >> 40) << 32); + sumOfSquares += ((q63_t)__RV_SMBB32(in64B, in64B) >> 32); + sumOfSquares += __RV_SMTT32(in64B, in64B); + + in64A = __RV_ADD32(in64A,in64B); + sum += (((int64_t)__RV_CRAS32(in64A,in64A)) >> 32); + +#else + in = *pSrc++ >> 8U; + /* Compute sum of squares and store result in a temporary variable, sumOfSquares. */ + sumOfSquares += ((q63_t) (in) * (in)); + /* Compute sum and store result in a temporary variable, sum. */ + sum += in; + + in = *pSrc++ >> 8U; + sumOfSquares += ((q63_t) (in) * (in)); + sum += in; + + in = *pSrc++ >> 8U; + sumOfSquares += ((q63_t) (in) * (in)); + sum += in; + + in = *pSrc++ >> 8U; + sumOfSquares += ((q63_t) (in) * (in)); + sum += in; +#endif /* __RISCV_XLEN == 64 */ + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + /* C = A[0] + A[1] + ... + A[blockSize-1] */ + + in = *pSrc++ >> 8U; + /* Compute sum of squares and store result in a temporary variable, sumOfSquares. */ + sumOfSquares += ((q63_t) (in) * (in)); + /* Compute sum and store result in a temporary variable, sum. */ + sum += in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Compute Mean of squares and store result in a temporary variable, meanOfSquares. */ + meanOfSquares = (sumOfSquares / (q63_t)(blockSize - 1U)); + + /* Compute square of mean */ + squareOfMean = ( sum * sum / (q63_t)(blockSize * (blockSize - 1U))); + + /* Compute variance and store result in destination */ + *pResult = (meanOfSquares - squareOfMean) >> 15U; +#endif /* defined(RISCV_VECTOR) */ +} +/** + @} end of variance group + */ diff --git a/components/nmsis/dsp/src/SupportFunctions/SupportFunctions.c b/components/nmsis/dsp/src/SupportFunctions/SupportFunctions.c new file mode 100644 index 00000000..0d2905ac --- /dev/null +++ b/components/nmsis/dsp/src/SupportFunctions/SupportFunctions.c @@ -0,0 +1,62 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: SupportFunctions.c + * Description: Combination of all support function source files. + * + * $Date: 16. March 2020 + * $Revision: V1.1.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2019-2020 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "riscv_barycenter_f32.c" +#include "riscv_bitonic_sort_f32.c" +#include "riscv_bubble_sort_f32.c" +#include "riscv_copy_f32.c" +#include "riscv_copy_q15.c" +#include "riscv_copy_q31.c" +#include "riscv_copy_q7.c" +#include "riscv_fill_f32.c" +#include "riscv_fill_q15.c" +#include "riscv_fill_q31.c" +#include "riscv_fill_q7.c" +#include "riscv_heap_sort_f32.c" +#include "riscv_insertion_sort_f32.c" +#include "riscv_merge_sort_f32.c" +#include "riscv_merge_sort_init_f32.c" +#include "riscv_quick_sort_f32.c" +#include "riscv_selection_sort_f32.c" +#include "riscv_sort_f32.c" +#include "riscv_sort_init_f32.c" +#include "riscv_weighted_sum_f32.c" + +#include "riscv_float_to_q15.c" +#include "riscv_float_to_q31.c" +#include "riscv_float_to_q7.c" +#include "riscv_q15_to_float.c" +#include "riscv_q15_to_q31.c" +#include "riscv_q15_to_q7.c" +#include "riscv_q31_to_float.c" +#include "riscv_q31_to_q15.c" +#include "riscv_q31_to_q7.c" +#include "riscv_q7_to_float.c" +#include "riscv_q7_to_q15.c" +#include "riscv_q7_to_q31.c" diff --git a/components/nmsis/dsp/src/SupportFunctions/SupportFunctionsF16.c b/components/nmsis/dsp/src/SupportFunctions/SupportFunctionsF16.c new file mode 100644 index 00000000..57ecbb20 --- /dev/null +++ b/components/nmsis/dsp/src/SupportFunctions/SupportFunctionsF16.c @@ -0,0 +1,37 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: SupportFunctions.c + * Description: Combination of all support function source files. + * + * $Date: 16. March 2020 + * $Revision: V1.1.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2019-2020 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "riscv_copy_f16.c" +#include "riscv_fill_f16.c" +#include "riscv_f16_to_q15.c" +#include "riscv_f16_to_float.c" +#include "riscv_q15_to_f16.c" +#include "riscv_float_to_f16.c" +#include "riscv_weighted_sum_f16.c" +#include "riscv_barycenter_f16.c" diff --git a/components/nmsis/dsp/src/SupportFunctions/riscv_barycenter_f16.c b/components/nmsis/dsp/src/SupportFunctions/riscv_barycenter_f16.c new file mode 100644 index 00000000..d719d8a0 --- /dev/null +++ b/components/nmsis/dsp/src/SupportFunctions/riscv_barycenter_f16.c @@ -0,0 +1,129 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_barycenter_f16.c + * Description: Barycenter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions_f16.h" + +#if defined(RISCV_FLOAT16_SUPPORTED) + +#include +#include + +/** + @ingroup groupSupport + */ + +/** + @defgroup barycenter Barycenter + + Barycenter of weighted vectors + */ + +/** + @addtogroup barycenter + @{ + */ + + +/** + * @brief Barycenter + * + * + * @param[in] *in List of vectors + * @param[in] *weights Weights of the vectors + * @param[out] *out Barycenter + * @param[in] nbVectors Number of vectors + * @param[in] vecDim Dimension of space (vector dimension) + * @return None + * + */ + +void riscv_barycenter_f16(const float16_t *in, const float16_t *weights, float16_t *out, uint32_t nbVectors,uint32_t vecDim) +{ + + const float16_t *pIn,*pW; + float16_t *pOut; + uint32_t blkCntVector,blkCntSample; + float16_t accum, w; + + blkCntVector = nbVectors; + blkCntSample = vecDim; + + accum = 0.0f; + + pW = weights; + pIn = in; + + /* Set counters to 0 */ + blkCntSample = vecDim; + pOut = out; + + while(blkCntSample > 0) + { + *pOut = 0.0f; + pOut++; + blkCntSample--; + } + + /* Sum */ + while(blkCntVector > 0) + { + pOut = out; + w = *pW++; + accum += w; + + blkCntSample = vecDim; + while(blkCntSample > 0) + { + *pOut = *pOut + *pIn++ * w; + pOut++; + blkCntSample--; + } + + blkCntVector--; + } + + /* Normalize */ + blkCntSample = vecDim; + pOut = out; + + while(blkCntSample > 0) + { + *pOut = *pOut / accum; + pOut++; + blkCntSample--; + } + +} + +/** + * @} end of barycenter group + */ + +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ + diff --git a/components/nmsis/dsp/src/SupportFunctions/riscv_barycenter_f32.c b/components/nmsis/dsp/src/SupportFunctions/riscv_barycenter_f32.c new file mode 100644 index 00000000..64a44c5f --- /dev/null +++ b/components/nmsis/dsp/src/SupportFunctions/riscv_barycenter_f32.c @@ -0,0 +1,136 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_barycenter_f32.c + * Description: Barycenter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions.h" +#include +#include + + +/** + @ingroup barycenter + */ + + +/** + * @brief Barycenter + * + * + * @param[in] *in List of vectors + * @param[in] *weights Weights of the vectors + * @param[out] *out Barycenter + * @param[in] nbVectors Number of vectors + * @param[in] vecDim Dimension of space (vector dimension) + * @return None + * + */ + +void riscv_barycenter_f32(const float32_t *in, const float32_t *weights, float32_t *out, uint32_t nbVectors,uint32_t vecDim) +{ + + const float32_t *pIn,*pW; + float32_t *pOut; + uint32_t blkCntVector,blkCntSample; + float32_t accum, w; + + blkCntVector = nbVectors; + blkCntSample = vecDim; + +#if defined(RISCV_VECTOR) + uint32_t blkCnt_v; /* Loop counter */ + size_t l; + float32_t temp_max; + vfloat32m8_t v_x, v_y; + vfloat32m8_t v_a, v_b; + vfloat32m1_t v_temp; + l = vsetvl_e32m1(1); + v_temp = vfsub_vv_f32m1(v_temp, v_temp, l); +#endif + + accum = 0.0f; + + pW = weights; + pIn = in; + + /* Set counters to 0 */ + blkCntSample = vecDim; + pOut = out; + + while(blkCntSample > 0) + { + *pOut = 0.0f; + pOut++; + blkCntSample--; + } + + /* Sum */ + while(blkCntVector > 0) + { + pOut = out; + w = *pW++; + accum += w; +#if defined(RISCV_VECTOR) + blkCnt_v = vecDim; + l = vsetvl_e32m8(blkCnt_v); + v_a = vfsub_vv_f32m8(v_a,v_a, l); + for (; (l = vsetvl_e32m8(blkCnt_v)) > 0; blkCnt_v -= l) { + v_x = vle32_v_f32m8(pIn, l); + v_y = vle32_v_f32m8(pOut, l); + v_x = vfmacc_vf_f32m8(v_y,w,v_x, l); + vse32_v_f32m8(pOut,v_x, l); + pIn += l; + pOut += l; + } +#else + blkCntSample = vecDim; + while(blkCntSample > 0) + { + *pOut = *pOut + *pIn++ * w; + pOut++; + blkCntSample--; + } +#endif + blkCntVector--; + } + + /* Normalize */ + blkCntSample = vecDim; + pOut = out; + + while(blkCntSample > 0) + { + *pOut = *pOut / accum; + pOut++; + blkCntSample--; + } + +} + +/** + * @} end of barycenter group + */ diff --git a/components/nmsis/dsp/src/SupportFunctions/riscv_bitonic_sort_f32.c b/components/nmsis/dsp/src/SupportFunctions/riscv_bitonic_sort_f32.c new file mode 100644 index 00000000..f273e4ff --- /dev/null +++ b/components/nmsis/dsp/src/SupportFunctions/riscv_bitonic_sort_f32.c @@ -0,0 +1,143 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_bitonic_sort_f32.c + * Description: Floating point bitonic sort + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions.h" +#include "riscv_sorting.h" + + + +static void riscv_bitonic_sort_core_f32(float32_t *pSrc, uint32_t n, uint8_t dir) +{ + uint32_t step; + uint32_t k, j; + float32_t *leftPtr, *rightPtr; + float32_t temp; + + step = n>>1; + leftPtr = pSrc; + rightPtr = pSrc+n-1; + + for(k=0; k *rightPtr)) + { + // Swap + temp=*leftPtr; + *leftPtr=*rightPtr; + *rightPtr=temp; + } + + leftPtr++; // Move right + rightPtr--; // Move left + } + + // Merge + for(step=(n>>2); step>0; step/=2) + { + for(j=0; j *rightPtr) + { + // Swap + temp=*leftPtr; + *leftPtr=*rightPtr; + *rightPtr=temp; + } + + leftPtr++; + rightPtr++; + } + } + } +} + + +/** + @ingroup groupSupport + */ + +/** + @defgroup Sorting Vector sorting algorithms + + Sort the elements of a vector + + There are separate functions for floating-point, Q31, Q15, and Q7 data types. + */ + +/** + @addtogroup Sorting + @{ + */ + +/** + * @private + * @param[in] S points to an instance of the sorting structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ +void riscv_bitonic_sort_f32( +const riscv_sort_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + uint16_t s, i; + uint8_t dir = S->dir; + + + float32_t * pA; + + if(pSrc != pDst) // out-of-place + { + memcpy(pDst, pSrc, blockSize*sizeof(float32_t) ); + pA = pDst; + } + else + pA = pSrc; + + + if( (blockSize & (blockSize-1)) == 0 ) // Powers of 2 only + { + for(s=2; s<=blockSize; s=s*2) + { + for(i=0; idir; + uint32_t i; + uint8_t swapped =1; + float32_t * pA; + float32_t temp; + + if(pSrc != pDst) // out-of-place + { + memcpy(pDst, pSrc, blockSize*sizeof(float32_t) ); + pA = pDst; + } + else + pA = pSrc; + + while(swapped==1) // If nothing has been swapped after one loop stop + { + swapped=0; + + for(i=0; ipA[i+1])) + { + // Swap + temp = pA[i]; + pA[i] = pA[i+1]; + pA[i+1] = temp; + + // Update flag + swapped = 1; + } + } + + blockSize--; + } +} + +/** + @} end of Sorting group + */ diff --git a/components/nmsis/dsp/src/SupportFunctions/riscv_copy_f16.c b/components/nmsis/dsp/src/SupportFunctions/riscv_copy_f16.c new file mode 100644 index 00000000..d9f1f868 --- /dev/null +++ b/components/nmsis/dsp/src/SupportFunctions/riscv_copy_f16.c @@ -0,0 +1,106 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_copy_f16.c + * Description: Copies the elements of a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions_f16.h" + +#if defined(RISCV_FLOAT16_SUPPORTED) + + +/** + @ingroup groupSupport + */ + + +/** + @addtogroup copy + @{ + */ + +/** + @brief Copies the elements of a f16 vector. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +void riscv_copy_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A */ + + /* Copy and store result in destination buffer */ + *pDst++ = *pSrc++; + *pDst++ = *pSrc++; + *pDst++ = *pSrc++; + *pDst++ = *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A */ + + /* Copy and store result in destination buffer */ + *pDst++ = *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } +} + +/** + @} end of BasicCopy group + */ + +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ + diff --git a/components/nmsis/dsp/src/SupportFunctions/riscv_copy_f32.c b/components/nmsis/dsp/src/SupportFunctions/riscv_copy_f32.c new file mode 100644 index 00000000..0fa8e7a4 --- /dev/null +++ b/components/nmsis/dsp/src/SupportFunctions/riscv_copy_f32.c @@ -0,0 +1,123 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_copy_f32.c + * Description: Copies the elements of a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + @defgroup copy Vector Copy + + Copies sample by sample from source vector to destination vector. + + 
+      pDst[n] = pSrc[n];   0 <= n < blockSize.
+
+ + There are separate functions for floating point, Q31, Q15, and Q7 data types. + */ + +/** + @addtogroup copy + @{ + */ + +/** + @brief Copies the elements of a floating-point vector. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ +void riscv_copy_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + size_t l; + vfloat32m8_t v_copy; + + for (; (l = vsetvl_e32m8(blkCnt)) > 0; blkCnt -= l) { + v_copy = vle32_v_f32m8(pSrc, l); + pSrc += l; + vse32_v_f32m8 (pDst, v_copy, l); + pDst += l; + } +#else + uint32_t blkCnt; /* Loop counter */ + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A */ + + /* Copy and store result in destination buffer */ + *pDst++ = *pSrc++; + *pDst++ = *pSrc++; + *pDst++ = *pSrc++; + *pDst++ = *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A */ + + /* Copy and store result in destination buffer */ + *pDst++ = *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of BasicCopy group + */ diff --git a/components/nmsis/dsp/src/SupportFunctions/riscv_copy_q15.c b/components/nmsis/dsp/src/SupportFunctions/riscv_copy_q15.c new file mode 100644 index 00000000..0b0758d1 --- /dev/null +++ b/components/nmsis/dsp/src/SupportFunctions/riscv_copy_q15.c @@ -0,0 +1,113 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_copy_q15.c + * Description: Copies the elements of a Q15 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup copy + @{ + */ + +/** + @brief Copies the elements of a Q15 vector. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ +void riscv_copy_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + size_t l; + vint16m8_t v_copy; + + for (; (l = vsetvl_e16m8(blkCnt)) > 0; blkCnt -= l) { + v_copy = vle16_v_i16m8(pSrc, l); + pSrc += l; + vse16_v_i16m8 (pDst, v_copy, l); + pDst += l; + } +#else + uint32_t blkCnt; /* Loop counter */ + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A */ +#if __RISCV_XLEN == 64 + /* read 4 samples at a time */ + write_q15x4_ia (&pDst, read_q15x4_ia ((q15_t **) &pSrc)); +#else + /* read 2 times 2 samples at a time */ + write_q15x2_ia (&pDst, read_q15x2_ia ((q15_t **) &pSrc)); + write_q15x2_ia (&pDst, read_q15x2_ia ((q15_t **) &pSrc)); +#endif /* __RISCV_XLEN == 64 */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A */ + + /* Copy and store result in destination buffer */ + *pDst++ = *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of BasicCopy group + */ diff --git a/components/nmsis/dsp/src/SupportFunctions/riscv_copy_q31.c b/components/nmsis/dsp/src/SupportFunctions/riscv_copy_q31.c new file mode 100644 index 00000000..5ef9a929 --- /dev/null +++ b/components/nmsis/dsp/src/SupportFunctions/riscv_copy_q31.c @@ -0,0 +1,115 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_copy_q31.c + * Description: Copies the elements of a Q31 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup copy + @{ + */ + +/** + @brief Copies the elements of a Q31 vector. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ +void riscv_copy_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + size_t l; + vint32m8_t v_copy; + + for (; (l = vsetvl_e32m8(blkCnt)) > 0; blkCnt -= l) { + v_copy = vle32_v_i32m8(pSrc, l); + pSrc += l; + vse32_v_i32m8 (pDst, v_copy, l); + pDst += l; + } +#else + uint32_t blkCnt; /* Loop counter */ + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A */ +#if __RISCV_XLEN == 64 + write_q31x2_ia (&pDst, read_q31x2_ia ((q31_t **) &pSrc)); + write_q31x2_ia (&pDst, read_q31x2_ia ((q31_t **) &pSrc)); +#else + /* Copy and store result in destination buffer */ + *pDst++ = *pSrc++; + *pDst++ = *pSrc++; + *pDst++ = *pSrc++; + *pDst++ = *pSrc++; +#endif /* __RISCV_XLEN == 64 */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A */ + + /* Copy and store result in destination buffer */ + *pDst++ = *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of BasicCopy group + */ diff --git a/components/nmsis/dsp/src/SupportFunctions/riscv_copy_q7.c b/components/nmsis/dsp/src/SupportFunctions/riscv_copy_q7.c new file mode 100644 index 00000000..6494df1e --- /dev/null +++ b/components/nmsis/dsp/src/SupportFunctions/riscv_copy_q7.c @@ -0,0 +1,120 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_copy_q7.c + * Description: Copies the elements of a Q7 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup copy + @{ + */ + +/** + @brief Copies the elements of a Q7 vector. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ +void riscv_copy_q7( + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + size_t l; + vint8m8_t v_copy; + + for (; (l = vsetvl_e8m8(blkCnt)) > 0; blkCnt -= l) { + v_copy = vle8_v_i8m8(pSrc, l); + pSrc += l; + vse8_v_i8m8 (pDst, v_copy, l); + pDst += l; + } +#else + uint32_t blkCnt; /* Loop counter */ + +#if defined (RISCV_MATH_LOOPUNROLL) +#if __RISCV_XLEN == 64 + /* Loop unrolling: Compute 8 outputs at a time */ + blkCnt = blockSize >> 3U; +#else + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; +#endif /* __RISCV_XLEN == 64 */ + + while (blkCnt > 0U) + { + /* C = A */ +#if __RISCV_XLEN == 64 + /* read 8 samples at a time */ + write_q7x8_ia (&pDst, read_q7x8_ia ((q7_t **) &pSrc)); +#else + /* read 4 samples at a time */ + write_q7x4_ia (&pDst, read_q7x4_ia ((q7_t **) &pSrc)); +#endif /* __RISCV_XLEN == 64 */ + + /* Decrement loop counter */ + blkCnt--; + } +#if __RISCV_XLEN == 64 + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x8U; +#else + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; +#endif /* __RISCV_XLEN == 64 */ + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A */ + + /* Copy and store result in destination buffer */ + *pDst++ = *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of BasicCopy group + */ diff --git a/components/nmsis/dsp/src/SupportFunctions/riscv_f16_to_float.c b/components/nmsis/dsp/src/SupportFunctions/riscv_f16_to_float.c new file mode 100644 index 00000000..9568dccf --- /dev/null +++ b/components/nmsis/dsp/src/SupportFunctions/riscv_f16_to_float.c @@ -0,0 +1,87 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_float_to_q15.c + * Description: Converts the elements of the floating-point vector to Q15 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions_f16.h" + +#if defined(RISCV_FLOAT16_SUPPORTED) + + +/** + @ingroup groupSupport + */ + +/** + * @defgroup f16_to_x Convert 16-bit floating point value + */ + +/** + @addtogroup f16_to_x + @{ + */ + +/** + @brief Converts the elements of the f16 vector to f32 vector. + @param[in] pSrc points to the f16 input vector + @param[out] pDst points to the f32 output vector + @param[in] blockSize number of samples in each vector + @return none + + */ + + +void riscv_f16_to_float( + const float16_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + const float16_t *pIn = pSrc; /* Src pointer */ + uint32_t blkCnt; /* loop counter */ + + /* + * Loop over blockSize number of values + */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + + *pDst++ = (float32_t) * pIn++; + /* + * Decrement the loop counter + */ + blkCnt--; + } +} + +/** + @} end of f16_to_x group + */ + +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ + diff --git a/components/nmsis/dsp/src/SupportFunctions/riscv_f16_to_q15.c b/components/nmsis/dsp/src/SupportFunctions/riscv_f16_to_q15.c new file mode 100644 index 00000000..9eceb4a0 --- /dev/null +++ b/components/nmsis/dsp/src/SupportFunctions/riscv_f16_to_q15.c @@ -0,0 +1,124 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_float_to_q15.c + * Description: Converts the elements of the floating-point vector to Q15 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions_f16.h" + +#if defined(RISCV_FLOAT16_SUPPORTED) + + +/** + @ingroup groupSupport + */ + +/** + @addtogroup f16_to_x + @{ + */ + +/** + @brief Converts the elements of the f16 vector to Q15 vector. + @param[in] pSrc points to the f16 input vector + @param[out] pDst points to the Q15 output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Details + The equation used for the conversion process is: + 
+      pDst[n] = (q15_t)(pSrc[n] * 32768);   0 <= n < blockSize.
+
+ + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q15 range [0x8000 0x7FFF] are saturated. + + @note + In order to apply rounding in scalar version, the library should be rebuilt with the ROUNDING macro + defined in the preprocessor section of project options. + */ + + +void riscv_f16_to_q15( + const float16_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + const float16_t *pIn = pSrc; /* Src pointer */ + uint32_t blkCnt; /* loop counter */ +#ifdef RISCV_MATH_ROUNDING + float16_t in; +#endif /* #ifdef RISCV_MATH_ROUNDING */ + + /* + * Loop over blockSize number of values + */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + +#ifdef RISCV_MATH_ROUNDING + + /* + * C = A * 65536 + */ + /* + * convert from float to Q31 and then store the results in the destination buffer + */ + in = *pIn++; + in = (in * 32768.0); + in += in > 0.0 ? 0.5 : -0.5; + *pDst++ = clip_q31_to_q15((q31_t) (in)); + +#else + + /* + * C = A * 32768 + */ + /* + * convert from float to Q31 and then store the results in the destination buffer + */ + *pDst++ = clip_q31_to_q15((q31_t) (*pIn++ * 32768.0)); + +#endif /* #ifdef RISCV_MATH_ROUNDING */ + + /* + * Decrement the loop counter + */ + blkCnt--; + } + +} + +/** + @} end of f16_to_x group + */ + +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ + diff --git a/components/nmsis/dsp/src/SupportFunctions/riscv_fill_f16.c b/components/nmsis/dsp/src/SupportFunctions/riscv_fill_f16.c new file mode 100644 index 00000000..e919d615 --- /dev/null +++ b/components/nmsis/dsp/src/SupportFunctions/riscv_fill_f16.c @@ -0,0 +1,105 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_fill_f16.c + * Description: Fills a constant value into a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions_f16.h" + +#if defined(RISCV_FLOAT16_SUPPORTED) + + +/** + @ingroup groupSupport + */ + + +/** + @addtogroup Fill + @{ + */ + +/** + @brief Fills a constant value into a f16 vector. + @param[in] value input value to be filled + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ +void riscv_fill_f16( + float16_t value, + float16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = value */ + + /* Fill value in destination buffer */ + *pDst++ = value; + *pDst++ = value; + *pDst++ = value; + *pDst++ = value; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = value */ + + /* Fill value in destination buffer */ + *pDst++ = value; + + /* Decrement loop counter */ + blkCnt--; + } +} + +/** + @} end of Fill group + */ + +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ + diff --git a/components/nmsis/dsp/src/SupportFunctions/riscv_fill_f32.c b/components/nmsis/dsp/src/SupportFunctions/riscv_fill_f32.c new file mode 100644 index 00000000..0d181034 --- /dev/null +++ b/components/nmsis/dsp/src/SupportFunctions/riscv_fill_f32.c @@ -0,0 +1,121 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_fill_f32.c + * Description: Fills a constant value into a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + @defgroup Fill Vector Fill + + Fills the destination vector with a constant value. + + 
+      pDst[n] = value;   0 <= n < blockSize.
+
+ + There are separate functions for floating point, Q31, Q15, and Q7 data types. + */ + +/** + @addtogroup Fill + @{ + */ + +/** + @brief Fills a constant value into a floating-point vector. + @param[in] value input value to be filled + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ +void riscv_fill_f32( + float32_t value, + float32_t * pDst, + uint32_t blockSize) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + size_t l; + vfloat32m8_t v_fill; + for (; (l = vsetvl_e32m8(blkCnt)) > 0; blkCnt -= l) { + v_fill = vfmv_v_f_f32m8(value, l); + vse32_v_f32m8 (pDst, v_fill, l); + pDst += l; + } +#else + uint32_t blkCnt; /* Loop counter */ + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = value */ + + /* Fill value in destination buffer */ + *pDst++ = value; + *pDst++ = value; + *pDst++ = value; + *pDst++ = value; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = value */ + + /* Fill value in destination buffer */ + *pDst++ = value; + + /* Decrement loop counter */ + blkCnt--; + } +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of Fill group + */ diff --git a/components/nmsis/dsp/src/SupportFunctions/riscv_fill_q15.c b/components/nmsis/dsp/src/SupportFunctions/riscv_fill_q15.c new file mode 100644 index 00000000..e00b9227 --- /dev/null +++ b/components/nmsis/dsp/src/SupportFunctions/riscv_fill_q15.c @@ -0,0 +1,118 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_fill_q15.c + * Description: Fills a constant value into a Q15 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup Fill + @{ + */ + +/** + @brief Fills a constant value into a Q15 vector. + @param[in] value input value to be filled + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ +void riscv_fill_q15( + q15_t value, + q15_t * pDst, + uint32_t blockSize) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + size_t l; + vint16m8_t v_fill; + for (; (l = vsetvl_e16m8(blkCnt)) > 0; blkCnt -= l) { + v_fill = vmv_v_x_i16m8(value, l); + vse16_v_i16m8 (pDst, v_fill, l); + pDst += l; + } +#else + uint32_t blkCnt; /* Loop counter */ + +#if defined (RISCV_MATH_LOOPUNROLL) + q31_t packedValue; /* value packed to 32 bits */ + + /* Packing two 16 bit values to 32 bit value in order to use SIMD */ + //packedValue = __PKHBT(value, value, 16U); + packedValue = __PKBB16(value, value); +#if __RISCV_XLEN == 64 + q63_t packedValue64; /* value packed to 32 bits */ + packedValue64 = __RV_PKBB32(packedValue,packedValue); +#endif /* __RISCV_XLEN == 64 */ + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = value */ +#if __RISCV_XLEN == 64 + write_q15x4_ia (&pDst, packedValue64); +#else + /* fill 2 times 2 samples at a time */ + write_q15x2_ia (&pDst, packedValue); + write_q15x2_ia (&pDst, packedValue); +#endif /* __RISCV_XLEN == 64 */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = value */ + + /* Fill value in destination buffer */ + *pDst++ = value; + + /* Decrement loop counter */ + blkCnt--; + } +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of Fill group + */ diff --git a/components/nmsis/dsp/src/SupportFunctions/riscv_fill_q31.c b/components/nmsis/dsp/src/SupportFunctions/riscv_fill_q31.c new file mode 100644 index 00000000..44fb2879 --- /dev/null +++ b/components/nmsis/dsp/src/SupportFunctions/riscv_fill_q31.c @@ -0,0 +1,113 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_fill_q31.c + * Description: Fills a constant value into a Q31 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup Fill + @{ + */ + +/** + @brief Fills a constant value into a Q31 vector. + @param[in] value input value to be filled + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ +void riscv_fill_q31( + q31_t value, + q31_t * pDst, + uint32_t blockSize) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + size_t l; + vint32m8_t v_fill; + for (; (l = vsetvl_e32m8(blkCnt)) > 0; blkCnt -= l) { + v_fill = vmv_v_x_i32m8(value, l); + vse32_v_i32m8 (pDst, v_fill, l); + pDst += l; + } +#else + uint32_t blkCnt; /* Loop counter */ + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = value */ +#if __RISCV_XLEN == 64 + write_q31x2_ia (&pDst, ((((uint64_t)((uint32_t)value)) << 32) | (((uint64_t)((uint32_t)value))))); + write_q31x2_ia (&pDst, ((((uint64_t)((uint32_t)value)) << 32) | (((uint64_t)((uint32_t)value))))); +#else + /* Fill value in destination buffer */ + *pDst++ = value; + *pDst++ = value; + *pDst++ = value; + *pDst++ = value; +#endif /* __RISCV_XLEN == 64 */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = value */ + + /* Fill value in destination buffer */ + *pDst++ = value; + + /* Decrement loop counter */ + blkCnt--; + } +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of Fill group + */ diff --git a/components/nmsis/dsp/src/SupportFunctions/riscv_fill_q7.c b/components/nmsis/dsp/src/SupportFunctions/riscv_fill_q7.c new file mode 100644 index 00000000..d910431b --- /dev/null +++ b/components/nmsis/dsp/src/SupportFunctions/riscv_fill_q7.c @@ -0,0 +1,132 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_fill_q7.c + * Description: Fills a constant value into a Q7 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup Fill + @{ + */ + +/** + @brief Fills a constant value into a Q7 vector. + @param[in] value input value to be filled + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ +void riscv_fill_q7( + q7_t value, + q7_t * pDst, + uint32_t blockSize) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + size_t l; + vint8m8_t v_fill; + for (; (l = vsetvl_e8m8(blkCnt)) > 0; blkCnt -= l) { + v_fill = vmv_v_x_i8m8(value, l); + vse8_v_i8m8 (pDst, v_fill, l); + pDst += l; + } +#else + uint32_t blkCnt; /* Loop counter */ + +#if defined (RISCV_MATH_LOOPUNROLL) + q31_t packedValue; /* value packed to 32 bits */ +#if __RISCV_XLEN == 64 + q63_t packedValue64; /* value packed to 32 bits */ + + packedValue = __PACKq7(value, value, value, value); + packedValue64 = __RV_PKBB32(packedValue,packedValue); +#else + #ifdef RISCV_DSP64 + packedValue = __PACKq7(value, value, value, value); + // packedValue = __RV_EXPD80(value); + #else + packedValue = __PACKq7(value, value, value, value); + #endif +#endif /* __RISCV_XLEN == 64 */ +#if __RISCV_XLEN == 64 + /* Loop unrolling: Compute 8 outputs at a time */ + blkCnt = blockSize >> 3U; +#else + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; +#endif /* __RISCV_XLEN == 64 */ + + while (blkCnt > 0U) + { + /* C = value */ +#if __RISCV_XLEN == 64 + /* fill 4 samples at a time */ + write_q7x8_ia (&pDst, packedValue64); +#else + /* fill 4 samples at a time */ + write_q7x4_ia (&pDst, packedValue); +#endif /* __RISCV_XLEN == 64 */ + + /* Decrement loop counter */ + blkCnt--; + } +#if __RISCV_XLEN == 64 + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x8U; +#else + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; +#endif /* __RISCV_XLEN == 64 */ + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = value */ + + /* Fill value in destination buffer */ + *pDst++ = value; + + /* Decrement loop counter */ + blkCnt--; + } +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of Fill group + */ diff --git a/components/nmsis/dsp/src/SupportFunctions/riscv_float_to_f16.c b/components/nmsis/dsp/src/SupportFunctions/riscv_float_to_f16.c new file mode 100644 index 00000000..c58180d0 --- /dev/null +++ b/components/nmsis/dsp/src/SupportFunctions/riscv_float_to_f16.c @@ -0,0 +1,84 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_float_to_q15.c + * Description: Converts the elements of the floating-point vector to Q15 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions_f16.h" + +#if defined(RISCV_FLOAT16_SUPPORTED) + + +/** + @ingroup groupSupport + */ + +/** + @addtogroup float_to_x + @{ + */ + +/** + @brief Converts the elements of the floating-point vector to f16 vector. + @param[in] pSrc points to the f32 input vector + @param[out] pDst points to the f16 output vector + @param[in] blockSize number of samples in each vector + @return none + + */ + + + +void riscv_float_to_f16( + const float32_t * pSrc, + float16_t * pDst, + uint32_t blockSize) +{ + const float32_t *pIn = pSrc; /* Src pointer */ + uint32_t blkCnt; /* loop counter */ + + /* + * Loop over blockSize number of values + */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + + *pDst++ = (float16_t) * pIn++; + /* + * Decrement the loop counter + */ + blkCnt--; + } +} + +/** + @} end of float_to_x group + */ + +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ + diff --git a/components/nmsis/dsp/src/SupportFunctions/riscv_float_to_q15.c b/components/nmsis/dsp/src/SupportFunctions/riscv_float_to_q15.c new file mode 100644 index 00000000..dec30ba6 --- /dev/null +++ b/components/nmsis/dsp/src/SupportFunctions/riscv_float_to_q15.c @@ -0,0 +1,172 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_float_to_q15.c + * Description: Converts the elements of the floating-point vector to Q15 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup float_to_x + @{ + */ + +/** + @brief Converts the elements of the floating-point vector to Q15 vector. + @param[in] pSrc points to the floating-point input vector + @param[out] pDst points to the Q15 output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Details + The equation used for the conversion process is: + 
+      pDst[n] = (q15_t)(pSrc[n] * 32768);   0 <= n < blockSize.
+
+ + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q15 range [0x8000 0x7FFF] are saturated. + + @note + In order to apply rounding, the library should be rebuilt with the ROUNDING macro + defined in the preprocessor section of project options. + */ + +void riscv_float_to_q15( + const float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + const float32_t *pIn = pSrc; /* Source pointer */ + size_t l; + vfloat32m8_t v_in; + vint16m4_t v_out; + for (; (l = vsetvl_e32m8(blkCnt)) > 0; blkCnt -= l) + { + v_in = vle32_v_f32m8(pIn, l); + pIn += l; +#ifdef RISCV_MATH_ROUNDING + v_out = vnclip_wx_i16m4(vfcvt_x_f_v_i32m8(vfmul_vf_f32m8(v_in, 32768.0f, l), l),0, l); +#else + v_out = vnclip_wx_i16m4(vfcvt_rtz_x_f_v_i32m8(vfmul_vf_f32m8(v_in, 32768.0f, l), l),0, l); +#endif + vse16_v_i16m4 (pDst, v_out, l); + pDst +=l; + } +#else + uint32_t blkCnt; /* Loop counter */ + const float32_t *pIn = pSrc; /* Source pointer */ + +#ifdef RISCV_MATH_ROUNDING + float32_t in; +#endif /* #ifdef RISCV_MATH_ROUNDING */ + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A * 32768 */ + + /* convert from float to Q15 and store result in destination buffer */ +#ifdef RISCV_MATH_ROUNDING + + in = (*pIn++ * 32768.0f); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16)); + + in = (*pIn++ * 32768.0f); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16)); + + in = (*pIn++ * 32768.0f); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16)); + + in = (*pIn++ * 32768.0f); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16)); + +#else + + *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16); + *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16); + *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16); + *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16); + +#endif /* #ifdef RISCV_MATH_ROUNDING */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A * 32768 */ + + /* convert from float to Q15 and store result in destination buffer */ +#ifdef RISCV_MATH_ROUNDING + + in = (*pIn++ * 32768.0f); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16)); + +#else + + /* C = A * 32768 */ + /* Convert from float to q15 and then store the results in the destination buffer */ + *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16); + +#endif /* #ifdef RISCV_MATH_ROUNDING */ + + /* Decrement loop counter */ + blkCnt--; + } +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of float_to_x group + */ diff --git a/components/nmsis/dsp/src/SupportFunctions/riscv_float_to_q31.c b/components/nmsis/dsp/src/SupportFunctions/riscv_float_to_q31.c new file mode 100644 index 00000000..8399884e --- /dev/null +++ b/components/nmsis/dsp/src/SupportFunctions/riscv_float_to_q31.c @@ -0,0 +1,178 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_float_to_q31.c + * Description: Converts the elements of the floating-point vector to Q31 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + * @defgroup float_to_x Convert 32-bit floating point value + */ + +/** + @addtogroup float_to_x + @{ + */ + +/** + @brief Converts the elements of the floating-point vector to Q31 vector. + @param[in] pSrc points to the floating-point input vector + @param[out] pDst points to the Q31 output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Details + The equation used for the conversion process is: + 
+      pDst[n] = (q31_t)(pSrc[n] * 2147483648);   0 <= n < blockSize.
+
+ + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] are saturated. + + @note + In order to apply rounding, the library should be rebuilt with the ROUNDING macro + defined in the preprocessor section of project options. + */ + +void riscv_float_to_q31( + const float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + const float32_t *pIn = pSrc; /* Source pointer */ + size_t l; + vfloat32m4_t v_in; + vint32m4_t v_out; + for (; (l = vsetvl_e32m4(blkCnt)) > 0; blkCnt -= l) + { + v_in = vle32_v_f32m4(pIn, l); + pIn += l; +#ifdef RISCV_MATH_ROUNDING + v_out = vnclip_wx_i32m4(vfcvt_x_f_v_i64m8(vfwmul_vf_f64m8(v_in, 2147483648.0f, l), l), 0U, l); +#else + v_out = vnclip_wx_i32m4(vfcvt_rtz_x_f_v_i64m8(vfwmul_vf_f64m8(v_in, 2147483648.0f, l), l), 0U, l); +#endif + vse32_v_i32m4 (pDst, v_out, l); + pDst += l; + } +#else + uint32_t blkCnt; /* Loop counter */ + const float32_t *pIn = pSrc; /* Source pointer */ + +#ifdef RISCV_MATH_ROUNDING + float32_t in; +#endif /* #ifdef RISCV_MATH_ROUNDING */ + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A * 2147483648 */ + + /* convert from float to Q31 and store result in destination buffer */ +#ifdef RISCV_MATH_ROUNDING + + in = (*pIn++ * 2147483648.0f); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = clip_q63_to_q31((q63_t) (in)); + + in = (*pIn++ * 2147483648.0f); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = clip_q63_to_q31((q63_t) (in)); + + in = (*pIn++ * 2147483648.0f); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = clip_q63_to_q31((q63_t) (in)); + + in = (*pIn++ * 2147483648.0f); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = clip_q63_to_q31((q63_t) (in)); + +#else + + /* C = A * 2147483648 */ + /* Convert from float to Q31 and then store the results in the destination buffer */ + *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f)); + *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f)); + *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f)); + *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f)); + +#endif /* #ifdef RISCV_MATH_ROUNDING */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A * 2147483648 */ + + /* convert from float to Q31 and store result in destination buffer */ +#ifdef RISCV_MATH_ROUNDING + + in = (*pIn++ * 2147483648.0f); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = clip_q63_to_q31((q63_t) (in)); + +#else + + /* C = A * 2147483648 */ + /* Convert from float to Q31 and then store the results in the destination buffer */ + *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f)); + +#endif /* #ifdef RISCV_MATH_ROUNDING */ + + /* Decrement loop counter */ + blkCnt--; + } +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of float_to_x group + */ diff --git a/components/nmsis/dsp/src/SupportFunctions/riscv_float_to_q7.c b/components/nmsis/dsp/src/SupportFunctions/riscv_float_to_q7.c new file mode 100644 index 00000000..6c01b7d7 --- /dev/null +++ b/components/nmsis/dsp/src/SupportFunctions/riscv_float_to_q7.c @@ -0,0 +1,169 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_float_to_q7.c + * Description: Converts the elements of the floating-point vector to Q7 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup float_to_x + @{ + */ + +/** + * @brief Converts the elements of the floating-point vector to Q7 vector. + * @param[in] *pSrc points to the floating-point input vector + * @param[out] *pDst points to the Q7 output vector + * @param[in] blockSize length of the input vector + * @return none. + * + *\par Description: + * \par + * The equation used for the conversion process is: + * 
+ * 	pDst[n] = (q7_t)(pSrc[n] * 128);   0 <= n < blockSize.
+ *
+ * \par Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q7 range [0x80 0x7F] will be saturated. + * \note + * In order to apply rounding, the library should be rebuilt with the ROUNDING macro + * defined in the preprocessor section of project options. + */ +void riscv_float_to_q7( + const float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + const float32_t *pIn = pSrc; /* Source pointer */ + size_t l; + vfloat32m8_t v_in; + vint8m2_t v_out; + for (; (l = vsetvl_e32m8(blkCnt)) > 0; blkCnt -= l) + { + v_in = vle32_v_f32m8(pIn, l); + pIn += l; +#ifdef RISCV_MATH_ROUNDING + v_out = vnclip_wx_i8m2(vnclip_wx_i16m4(vfcvt_x_f_v_i32m8(vfmul_vf_f32m8(v_in, 128.0f, l), l), 0U, l), 0U, l); +#else + v_out = vnclip_wx_i8m2(vnclip_wx_i16m4(vfcvt_rtz_x_f_v_i32m8(vfmul_vf_f32m8(v_in, 128.0f, l), l), 0U, l), 0U, l); +#endif + vse8_v_i8m2 (pDst, v_out, l); + pDst +=l; + } +#else + uint32_t blkCnt; /* Loop counter */ + const float32_t *pIn = pSrc; /* Source pointer */ + +#ifdef RISCV_MATH_ROUNDING + float32_t in; +#endif /* #ifdef RISCV_MATH_ROUNDING */ + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A * 128 */ + + /* Convert from float to q7 and store result in destination buffer */ +#ifdef RISCV_MATH_ROUNDING + + in = (*pIn++ * 128); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8)); + + in = (*pIn++ * 128); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8)); + + in = (*pIn++ * 128); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8)); + + in = (*pIn++ * 128); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8)); + +#else + + *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8); + *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8); + *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8); + *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8); + +#endif /* #ifdef RISCV_MATH_ROUNDING */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A * 128 */ + + /* Convert from float to q7 and store result in destination buffer */ +#ifdef RISCV_MATH_ROUNDING + + in = (*pIn++ * 128); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8)); + +#else + + *pDst++ = (q7_t) __SSAT((q31_t) (*pIn++ * 128.0f), 8); + +#endif /* #ifdef RISCV_MATH_ROUNDING */ + + /* Decrement loop counter */ + blkCnt--; + } +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of float_to_x group + */ diff --git a/components/nmsis/dsp/src/SupportFunctions/riscv_heap_sort_f32.c b/components/nmsis/dsp/src/SupportFunctions/riscv_heap_sort_f32.c new file mode 100644 index 00000000..931537e5 --- /dev/null +++ b/components/nmsis/dsp/src/SupportFunctions/riscv_heap_sort_f32.c @@ -0,0 +1,120 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_heap_sort_f32.c + * Description: Floating point heap sort + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions.h" +#include "riscv_sorting.h" + + + +static void riscv_heapify(float32_t * pSrc, uint32_t n, uint32_t i, uint8_t dir) +{ + /* Put all the elements of pSrc in heap order */ + uint32_t k = i; // Initialize largest/smallest as root + uint32_t l = 2*i + 1; // left = 2*i + 1 + uint32_t r = 2*i + 2; // right = 2*i + 2 + float32_t temp; + + if (l < n && dir==(pSrc[l] > pSrc[k]) ) + k = l; + + if (r < n && dir==(pSrc[r] > pSrc[k]) ) + k = r; + + if (k != i) + { + temp = pSrc[i]; + pSrc[i]=pSrc[k]; + pSrc[k]=temp; + + riscv_heapify(pSrc, n, k, dir); + } +} + +/** + @ingroup groupSupport + */ + +/** + @addtogroup Sorting + @{ + */ + +/** + * @private + * @param[in] S points to an instance of the sorting structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * + * @par Algorithm + * The heap sort algorithm is a comparison algorithm that + * divides the input array into a sorted and an unsorted region, + * and shrinks the unsorted region by extracting the largest + * element and moving it to the sorted region. A heap data + * structure is used to find the maximum. + * + * @par It's an in-place algorithm. In order to obtain an out-of-place + * function, a memcpy of the source vector is performed. + */ +void riscv_heap_sort_f32( + const riscv_sort_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + float32_t * pA; + int32_t i; + float32_t temp; + + if(pSrc != pDst) // out-of-place + { + memcpy(pDst, pSrc, blockSize*sizeof(float32_t) ); + pA = pDst; + } + else + pA = pSrc; + + // Build the heap array so that the largest value is the root + for (i = blockSize/2 - 1; i >= 0; i--) + riscv_heapify(pA, blockSize, i, S->dir); + + for (i = blockSize - 1; i >= 0; i--) + { + // Swap + temp = pA[i]; + pA[i] = pA[0]; + pA[0] = temp; + + // Restore heap order + riscv_heapify(pA, i, 0, S->dir); + } +} +/** + @} end of Sorting group + */ diff --git a/components/nmsis/dsp/src/SupportFunctions/riscv_insertion_sort_f32.c b/components/nmsis/dsp/src/SupportFunctions/riscv_insertion_sort_f32.c new file mode 100644 index 00000000..a422b2c5 --- /dev/null +++ b/components/nmsis/dsp/src/SupportFunctions/riscv_insertion_sort_f32.c @@ -0,0 +1,94 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_insertion_sort_f32.c + * Description: Floating point insertion sort + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions.h" +#include "riscv_sorting.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup Sorting + @{ + */ + +/** + * @private + * @param[in] S points to an instance of the sorting structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * + * @par Algorithm + * The insertion sort is a simple sorting algorithm that + * reads all the element of the input array and removes one element + * at a time, finds the location it belongs in the final sorted list, + * and inserts it there. + * + * @par It's an in-place algorithm. In order to obtain an out-of-place + * function, a memcpy of the source vector is performed. + */ + +void riscv_insertion_sort_f32( + const riscv_sort_instance_f32 * S, + float32_t *pSrc, + float32_t* pDst, + uint32_t blockSize) +{ + float32_t * pA; + uint8_t dir = S->dir; + uint32_t i, j; + float32_t temp; + + if(pSrc != pDst) // out-of-place + { + memcpy(pDst, pSrc, blockSize*sizeof(float32_t) ); + pA = pDst; + } + else + pA = pSrc; + + // Real all the element of the input array + for(i=0; i0 && dir==(pA[j]= end || dir==(pA[i] <= pA[j])) ) + { + pB[k] = pA[i]; + i++; + } + else + { + pB[k] = pA[j]; + j++; + } + } +} + +static void riscv_merge_sort_core_f32(float32_t * pB, uint32_t begin, uint32_t end, float32_t * pA, uint8_t dir) +{ + if((int32_t)end - (int32_t)begin >= 2 ) // If run size != 1 divide + { + int32_t middle = (end + begin) / 2; // Take the middle point + + riscv_merge_sort_core_f32(pA, begin, middle, pB, dir); // Sort the left part + riscv_merge_sort_core_f32(pA, middle, end, pB, dir); // Sort the right part + + topDownMerge(pB, begin, middle, end, pA, dir); + } +} + + +/** + @ingroup groupSupport + */ + +/** + @addtogroup Sorting + @{ + */ + +/** + * @param[in] S points to an instance of the sorting structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * + * @par Algorithm + * The merge sort algorithm is a comparison algorithm that + * divide the input array in sublists and merge them to produce + * longer sorted sublists until there is only one list remaining. + * + * @par A work array is always needed. It must be allocated by the user + * linked to the instance at initialization time. + * + * @par It's an in-place algorithm. In order to obtain an out-of-place + * function, a memcpy of the source vector is performed + */ + + +void riscv_merge_sort_f32( + const riscv_merge_sort_instance_f32 * S, + float32_t *pSrc, + float32_t *pDst, + uint32_t blockSize) +{ + float32_t * pA; + + /* Out-of-place */ + if(pSrc != pDst) + { + memcpy(pDst, pSrc, blockSize*sizeof(float32_t)); + pA = pDst; + } + else + pA = pSrc; + + /* A working buffer is needed */ + memcpy(S->buffer, pSrc, blockSize*sizeof(float32_t)); + + riscv_merge_sort_core_f32(S->buffer, 0, blockSize, pA, S->dir); +} +/** + @} end of Sorting group + */ diff --git a/components/nmsis/dsp/src/SupportFunctions/riscv_merge_sort_init_f32.c b/components/nmsis/dsp/src/SupportFunctions/riscv_merge_sort_init_f32.c new file mode 100644 index 00000000..3c330672 --- /dev/null +++ b/components/nmsis/dsp/src/SupportFunctions/riscv_merge_sort_init_f32.c @@ -0,0 +1,54 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_merge_sort_init_f32.c + * Description: Floating point merge sort initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup Sorting + @{ + */ + + + /** + * @param[in,out] S points to an instance of the sorting structure. + * @param[in] dir Sorting order. + * @param[in] buffer Working buffer. + */ +void riscv_merge_sort_init_f32(riscv_merge_sort_instance_f32 * S, riscv_sort_dir dir, float32_t * buffer) +{ + S->dir = dir; + S->buffer = buffer; +} +/** + @} end of Sorting group + */ diff --git a/components/nmsis/dsp/src/SupportFunctions/riscv_q15_to_f16.c b/components/nmsis/dsp/src/SupportFunctions/riscv_q15_to_f16.c new file mode 100644 index 00000000..82aa4383 --- /dev/null +++ b/components/nmsis/dsp/src/SupportFunctions/riscv_q15_to_f16.c @@ -0,0 +1,118 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_q15_to_float.c + * Description: Converts the elements of the Q15 vector to floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions_f16.h" + +#if defined(RISCV_FLOAT16_SUPPORTED) + + +/** + @ingroup groupSupport + */ + +/** + * @defgroup q15_to_x Convert 16-bit Integer value + */ + +/** + @addtogroup q15_to_x + @{ + */ + +/** + @brief Converts the elements of the Q15 vector to f16 vector. + @param[in] pSrc points to the Q15 input vector + @param[out] pDst points to the f16 output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Details + The equation used for the conversion process is: + 
+      pDst[n] = (float16_t) pSrc[n] / 32768;   0 <= n < blockSize.
+
+ */ + + +void riscv_q15_to_f16( + const q15_t * pSrc, + float16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + const q15_t *pIn = pSrc; /* Source pointer */ + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (float16_t) A / 32768 */ + + /* Convert from q15 to float and store result in destination buffer */ + *pDst++ = ((float16_t) * pIn++ / 32768.0f); + *pDst++ = ((float16_t) * pIn++ / 32768.0f); + *pDst++ = ((float16_t) * pIn++ / 32768.0f); + *pDst++ = ((float16_t) * pIn++ / 32768.0f); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (float16_t) A / 32768 */ + + /* Convert from q15 to float and store result in destination buffer */ + *pDst++ = ((float16_t) *pIn++ / 32768.0f); + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of q15_to_x group + */ + +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ + diff --git a/components/nmsis/dsp/src/SupportFunctions/riscv_q15_to_float.c b/components/nmsis/dsp/src/SupportFunctions/riscv_q15_to_float.c new file mode 100644 index 00000000..24ce7137 --- /dev/null +++ b/components/nmsis/dsp/src/SupportFunctions/riscv_q15_to_float.c @@ -0,0 +1,126 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_q15_to_float.c + * Description: Converts the elements of the Q15 vector to floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + * @defgroup q15_to_x Convert 16-bit Integer value + */ + +/** + @addtogroup q15_to_x + @{ + */ + +/** + @brief Converts the elements of the Q15 vector to floating-point vector. + @param[in] pSrc points to the Q15 input vector + @param[out] pDst points to the floating-point output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Details + The equation used for the conversion process is: + 
+      pDst[n] = (float32_t) pSrc[n] / 32768;   0 <= n < blockSize.
+
+ */ + +void riscv_q15_to_float( + const q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ +#if defined(RISCV_VECTOR) + const q15_t *pIn = pSrc; /* Src pointer */ + uint32_t blkCnt = blockSize; /* loop counter */ + size_t l; + vint16m4_t v_in; + vfloat32m8_t v_out; + for (; (l = vsetvl_e16m4(blkCnt)) > 0; blkCnt -= l) + { + v_in = vle16_v_i16m4(pIn, l); + pIn += l; + v_out = vfdiv_vf_f32m8(vfwcvt_f_x_v_f32m8(v_in, l), 32768.0f, l); + vse32_v_f32m8 (pDst, v_out, l); + pDst += l; + } +#else + uint32_t blkCnt; /* Loop counter */ + const q15_t *pIn = pSrc; /* Source pointer */ + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (float32_t) A / 32768 */ + + /* Convert from q15 to float and store result in destination buffer */ + *pDst++ = ((float32_t) * pIn++ / 32768.0f); + *pDst++ = ((float32_t) * pIn++ / 32768.0f); + *pDst++ = ((float32_t) * pIn++ / 32768.0f); + *pDst++ = ((float32_t) * pIn++ / 32768.0f); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (float32_t) A / 32768 */ + + /* Convert from q15 to float and store result in destination buffer */ + *pDst++ = ((float32_t) *pIn++ / 32768.0f); + + /* Decrement loop counter */ + blkCnt--; + } +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of q15_to_x group + */ diff --git a/components/nmsis/dsp/src/SupportFunctions/riscv_q15_to_q31.c b/components/nmsis/dsp/src/SupportFunctions/riscv_q15_to_q31.c new file mode 100644 index 00000000..f7b27926 --- /dev/null +++ b/components/nmsis/dsp/src/SupportFunctions/riscv_q15_to_q31.c @@ -0,0 +1,140 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_q15_to_q31.c + * Description: Converts the elements of the Q15 vector to Q31 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup q15_to_x + @{ + */ + +/** + @brief Converts the elements of the Q15 vector to Q31 vector. + @param[in] pSrc points to the Q15 input vector + @param[out] pDst points to the Q31 output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Details + The equation used for the conversion process is: + 
+      pDst[n] = (q31_t) pSrc[n] << 16;   0 <= n < blockSize.
+
+ */ +void riscv_q15_to_q31( + const q15_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + const q15_t *pIn = pSrc; /* Source pointer */ + size_t l; + vint16m4_t v_in; + vint32m8_t v_out; + for (; (l = vsetvl_e16m4(blkCnt)) > 0; blkCnt -= l) + { + v_in = vle16_v_i16m4(pIn, l); + pIn += l; + v_out = vsll_vx_i32m8(vsext_vf2_i32m8(v_in, l), 16U, l); + vse32_v_i32m8 (pDst, v_out, l); + pDst += l; + } +#else + uint32_t blkCnt; /* Loop counter */ + const q15_t *pIn = pSrc; /* Source pointer */ + +#if defined (RISCV_MATH_LOOPUNROLL) + q31_t in1, in2; + q31_t out1, out2, out3, out4; +#endif + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (q31_t)A << 16 */ + + /* Convert from q15 to q31 and store result in destination buffer */ + in1 = read_q15x2_ia ((q15_t **) &pIn); + in2 = read_q15x2_ia ((q15_t **) &pIn); + + + /* extract lower 16 bits to 32 bit result */ + out1 = in1 << 16U; + /* extract upper 16 bits to 32 bit result */ + out2 = in1 & 0xFFFF0000; + /* extract lower 16 bits to 32 bit result */ + out3 = in2 << 16U; + /* extract upper 16 bits to 32 bit result */ + out4 = in2 & 0xFFFF0000; + + + *pDst++ = out1; + *pDst++ = out2; + *pDst++ = out3; + *pDst++ = out4; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (q31_t) A << 16 */ + + /* Convert from q15 to q31 and store result in destination buffer */ + *pDst++ = (q31_t) *pIn++ << 16; + + /* Decrement loop counter */ + blkCnt--; + } +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of q15_to_x group + */ diff --git a/components/nmsis/dsp/src/SupportFunctions/riscv_q15_to_q7.c b/components/nmsis/dsp/src/SupportFunctions/riscv_q15_to_q7.c new file mode 100644 index 00000000..fdb7edfb --- /dev/null +++ b/components/nmsis/dsp/src/SupportFunctions/riscv_q15_to_q7.c @@ -0,0 +1,154 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_q15_to_q7.c + * Description: Converts the elements of the Q15 vector to Q7 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup q15_to_x + @{ + */ + +/** + @brief Converts the elements of the Q15 vector to Q7 vector. + @param[in] pSrc points to the Q15 input vector + @param[out] pDst points to the Q7 output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Details + The equation used for the conversion process is: + 
+      pDst[n] = (q7_t) pSrc[n] >> 8;   0 <= n < blockSize.
+
+ */ +void riscv_q15_to_q7( + const q15_t * pSrc, + q7_t * pDst, + uint32_t blockSize) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + const q15_t *pIn = pSrc; /* Source pointer */ + size_t l; + vint16m8_t v_in; + vint8m4_t v_out; + for (; (l = vsetvl_e16m8(blkCnt)) > 0; blkCnt -= l) + { + v_in = vle16_v_i16m8(pIn, l); + pIn += l; + v_out = vnclip_wx_i8m4(v_in, 8U, l); + vse8_v_i8m4 (pDst, v_out, l); + pDst += l; + } +#else + uint32_t blkCnt; /* Loop counter */ + const q15_t *pIn = pSrc; /* Source pointer */ + +#if defined (RISCV_MATH_LOOPUNROLL) && defined (RISCV_MATH_DSP) + q31_t in1, in2; + q31_t out1, out2; +#endif + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (q7_t) A >> 8 */ + + /* Convert from q15 to q7 and store result in destination buffer */ +#if defined (RISCV_MATH_DSP) + + in1 = read_q15x2_ia ((q15_t **) &pIn); + in2 = read_q15x2_ia ((q15_t **) &pIn); + + + out1 = __PKHTB(in2, in1, 16); + out2 = __PKHBT(in2, in1, 16); + + + /* rotate packed value by 24 */ + out2 = ((uint32_t) out2 << 8) | ((uint32_t) out2 >> 24); + + /* anding with 0xff00ff00 to get two 8 bit values */ + out1 = out1 & 0xFF00FF00; + /* anding with 0x00ff00ff to get two 8 bit values */ + out2 = out2 & 0x00FF00FF; + + /* oring two values(contains two 8 bit values) to get four packed 8 bit values */ + out1 = out1 | out2; + + /* store 4 samples at a time to destiantion buffer */ + write_q7x4_ia (&pDst, out1); + +#else + + *pDst++ = (q7_t) (*pIn++ >> 8); + *pDst++ = (q7_t) (*pIn++ >> 8); + *pDst++ = (q7_t) (*pIn++ >> 8); + *pDst++ = (q7_t) (*pIn++ >> 8); + +#endif /* #if defined (RISCV_MATH_DSP) */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (q7_t) A >> 8 */ + + /* Convert from q15 to q7 and store result in destination buffer */ + *pDst++ = (q7_t) (*pIn++ >> 8); + + /* Decrement loop counter */ + blkCnt--; + } +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of q15_to_x group + */ diff --git a/components/nmsis/dsp/src/SupportFunctions/riscv_q31_to_float.c b/components/nmsis/dsp/src/SupportFunctions/riscv_q31_to_float.c new file mode 100644 index 00000000..02f4a7f5 --- /dev/null +++ b/components/nmsis/dsp/src/SupportFunctions/riscv_q31_to_float.c @@ -0,0 +1,125 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_q31_to_float.c + * Description: Converts the elements of the Q31 vector to floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + * @defgroup q31_to_x Convert 32-bit Integer value + */ + +/** + @addtogroup q31_to_x + @{ + */ + +/** + @brief Converts the elements of the Q31 vector to floating-point vector. + @param[in] pSrc points to the Q31 input vector + @param[out] pDst points to the floating-point output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Details + The equation used for the conversion process is: + 
+      pDst[n] = (float32_t) pSrc[n] / 2147483648;   0 <= n < blockSize.
+
+ */ +void riscv_q31_to_float( + const q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ +#if defined(RISCV_VECTOR) + const q31_t *pIn = pSrc; /* Src pointer */ + uint32_t blkCnt = blockSize; /* loop counter */ + size_t l; + vint32m8_t v_in; + vfloat32m8_t v_out; + for (; (l = vsetvl_e32m8(blkCnt)) > 0; blkCnt -= l) + { + v_in = vle32_v_i32m8(pIn, l); + pIn += l; + v_out = vfdiv_vf_f32m8(vfcvt_f_x_v_f32m8(v_in, l), 2147483648.0f, l); + vse32_v_f32m8 (pDst, v_out, l); + pDst += l; + } +#else + const q31_t *pIn = pSrc; /* Src pointer */ + uint32_t blkCnt; /* loop counter */ + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (float32_t) A / 2147483648 */ + + /* Convert from q31 to float and store result in destination buffer */ + *pDst++ = ((float32_t) *pIn++ / 2147483648.0f); + *pDst++ = ((float32_t) *pIn++ / 2147483648.0f); + *pDst++ = ((float32_t) *pIn++ / 2147483648.0f); + *pDst++ = ((float32_t) *pIn++ / 2147483648.0f); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (float32_t) A / 2147483648 */ + + /* Convert from q31 to float and store result in destination buffer */ + *pDst++ = ((float32_t) *pIn++ / 2147483648.0f); + + /* Decrement loop counter */ + blkCnt--; + } +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of q31_to_x group + */ diff --git a/components/nmsis/dsp/src/SupportFunctions/riscv_q31_to_q15.c b/components/nmsis/dsp/src/SupportFunctions/riscv_q31_to_q15.c new file mode 100644 index 00000000..0e7cf673 --- /dev/null +++ b/components/nmsis/dsp/src/SupportFunctions/riscv_q31_to_q15.c @@ -0,0 +1,144 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_q31_to_q15.c + * Description: Converts the elements of the Q31 vector to Q15 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup q31_to_x + @{ + */ + +/** + @brief Converts the elements of the Q31 vector to Q15 vector. + @param[in] pSrc points to the Q31 input vector + @param[out] pDst points to the Q15 output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Details + The equation used for the conversion process is: + 
+      pDst[n] = (q15_t) pSrc[n] >> 16;   0 <= n < blockSize.
+
+ */ +void riscv_q31_to_q15( + const q31_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + const q31_t *pIn = pSrc; /* Source pointer */ + size_t l; + vint32m8_t v_in; + vint16m4_t v_out; + for (; (l = vsetvl_e32m8(blkCnt)) > 0; blkCnt -= l) + { + v_in = vle32_v_i32m8(pIn, l); + pIn += l; + v_out = vnclip_wx_i16m4(v_in, 16U, l); + vse16_v_i16m4 (pDst, v_out, l); + pDst += l; + } +#else + uint32_t blkCnt; /* Loop counter */ + const q31_t *pIn = pSrc; /* Source pointer */ + +#if defined (RISCV_MATH_LOOPUNROLL) && defined (RISCV_MATH_DSP) + q31_t in1, in2, in3, in4; + q31_t out1, out2; +#endif + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (q15_t) (A >> 16) */ + + /* Convert from q31 to q15 and store result in destination buffer */ +#if defined (RISCV_MATH_DSP) + + in1 = *pIn++; + in2 = *pIn++; + in3 = *pIn++; + in4 = *pIn++; + + /* pack two higher 16-bit values from two 32-bit values */ + out1 = __PKHTB(in2, in1, 16); + out2 = __PKHTB(in4, in3, 16); + + write_q15x2_ia (&pDst, out1); + write_q15x2_ia (&pDst, out2); + +#else + + *pDst++ = (q15_t) (*pIn++ >> 16); + *pDst++ = (q15_t) (*pIn++ >> 16); + *pDst++ = (q15_t) (*pIn++ >> 16); + *pDst++ = (q15_t) (*pIn++ >> 16); + +#endif /* #if defined (RISCV_MATH_DSP) */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (q15_t) (A >> 16) */ + + /* Convert from q31 to q15 and store result in destination buffer */ + *pDst++ = (q15_t) (*pIn++ >> 16); + + /* Decrement loop counter */ + blkCnt--; + } +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of q31_to_x group + */ diff --git a/components/nmsis/dsp/src/SupportFunctions/riscv_q31_to_q7.c b/components/nmsis/dsp/src/SupportFunctions/riscv_q31_to_q7.c new file mode 100644 index 00000000..a0b17b40 --- /dev/null +++ b/components/nmsis/dsp/src/SupportFunctions/riscv_q31_to_q7.c @@ -0,0 +1,125 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_q31_to_q7.c + * Description: Converts the elements of the Q31 vector to Q7 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup q31_to_x + @{ + */ + +/** + @brief Converts the elements of the Q31 vector to Q7 vector. + @param[in] pSrc points to the Q31 input vector + @param[out] pDst points to the Q7 output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Details + The equation used for the conversion process is: + 
+      pDst[n] = (q7_t) pSrc[n] >> 24;   0 <= n < blockSize.
+
+ */ +void riscv_q31_to_q7( + const q31_t * pSrc, + q7_t * pDst, + uint32_t blockSize) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + const q31_t *pIn = pSrc; /* Source pointer */ + size_t l; + vint32m8_t v_in; + vint8m2_t v_out; + for (; (l = vsetvl_e32m8(blkCnt)) > 0; blkCnt -= l) + { + v_in = vle32_v_i32m8(pIn, l); + pIn += l; + v_out = vnclip_wx_i8m2(vnclip_wx_i16m4(v_in, 24U, l), 0U, l); + vse8_v_i8m2 (pDst, v_out, l); + pDst += l; + } +#else + uint32_t blkCnt; /* Loop counter */ + const q31_t *pIn = pSrc; /* Source pointer */ + +#if defined (RISCV_MATH_LOOPUNROLL) + + q7_t out1, out2, out3, out4; + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (q7_t) (A >> 24) */ + + /* Convert from q31 to q7 and store result in destination buffer */ + + out1 = (q7_t) (*pIn++ >> 24); + out2 = (q7_t) (*pIn++ >> 24); + out3 = (q7_t) (*pIn++ >> 24); + out4 = (q7_t) (*pIn++ >> 24); + write_q7x4_ia (&pDst, __PACKq7(out1, out2, out3, out4)); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (q7_t) (A >> 24) */ + + /* Convert from q31 to q7 and store result in destination buffer */ + *pDst++ = (q7_t) (*pIn++ >> 24); + + /* Decrement loop counter */ + blkCnt--; + } +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of q31_to_x group + */ diff --git a/components/nmsis/dsp/src/SupportFunctions/riscv_q7_to_float.c b/components/nmsis/dsp/src/SupportFunctions/riscv_q7_to_float.c new file mode 100644 index 00000000..1e1d9d92 --- /dev/null +++ b/components/nmsis/dsp/src/SupportFunctions/riscv_q7_to_float.c @@ -0,0 +1,125 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_q7_to_float.c + * Description: Converts the elements of the Q7 vector to floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + * @defgroup q7_to_x Convert 8-bit Integer value + */ + +/** + @addtogroup q7_to_x + @{ + */ + +/** + @brief Converts the elements of the Q7 vector to floating-point vector. + @param[in] pSrc points to the Q7 input vector + @param[out] pDst points to the floating-point output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Details + The equation used for the conversion process is: + 
+      pDst[n] = (float32_t) pSrc[n] / 128;   0 <= n < blockSize.
+
+ */ +void riscv_q7_to_float( + const q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ +#if defined(RISCV_VECTOR) + const q7_t *pIn = pSrc; /* Src pointer */ + uint32_t blkCnt = blockSize; /* loop counter */ + size_t l; + vint8m2_t v_in; + vfloat32m8_t v_out; + for (; (l = vsetvl_e8m2(blkCnt)) > 0; blkCnt -= l) + { + v_in = vle8_v_i8m2(pIn, l); + pIn += l; + v_out = vfdiv_vf_f32m8(vfwcvt_f_x_v_f32m8(vwadd_vx_i16m4(v_in, 0, l), l), 128.0f, l); + vse32_v_f32m8 (pDst, v_out, l); + pDst += l; + } +#else + uint32_t blkCnt; /* Loop counter */ + const q7_t *pIn = pSrc; /* Source pointer */ + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (float32_t) A / 128 */ + + /* Convert from q7 to float and store result in destination buffer */ + *pDst++ = ((float32_t) * pIn++ / 128.0f); + *pDst++ = ((float32_t) * pIn++ / 128.0f); + *pDst++ = ((float32_t) * pIn++ / 128.0f); + *pDst++ = ((float32_t) * pIn++ / 128.0f); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (float32_t) A / 128 */ + + /* Convert from q7 to float and store result in destination buffer */ + *pDst++ = ((float32_t) * pIn++ / 128.0f); + + /* Decrement loop counter */ + blkCnt--; + } +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of q7_to_x group + */ diff --git a/components/nmsis/dsp/src/SupportFunctions/riscv_q7_to_q15.c b/components/nmsis/dsp/src/SupportFunctions/riscv_q7_to_q15.c new file mode 100644 index 00000000..de245e36 --- /dev/null +++ b/components/nmsis/dsp/src/SupportFunctions/riscv_q7_to_q15.c @@ -0,0 +1,154 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_q7_to_q15.c + * Description: Converts the elements of the Q7 vector to Q15 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup q7_to_x + @{ + */ + +/** + @brief Converts the elements of the Q7 vector to Q15 vector. + @param[in] pSrc points to the Q7 input vector + @param[out] pDst points to the Q15 output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Details + The equation used for the conversion process is: + 
+      pDst[n] = (q15_t) pSrc[n] << 8;   0 <= n < blockSize.
+
+ */ + +void riscv_q7_to_q15( + const q7_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + const q7_t *pIn = pSrc; /* Source pointer */ + size_t l; + vint8m4_t v_in; + vint16m8_t v_out; + for (; (l = vsetvl_e8m4(blkCnt)) > 0; blkCnt -= l) + { + v_in = vle8_v_i8m4(pIn, l); + pIn += l; + v_out = vsll_vx_i16m8(vsext_vf2_i16m8(v_in, l), 8U, l); + vse16_v_i16m8 (pDst, v_out, l); + pDst += l; + } +#else + uint32_t blkCnt; /* Loop counter */ + const q7_t *pIn = pSrc; /* Source pointer */ + +#if defined (RISCV_MATH_LOOPUNROLL) && defined (RISCV_MATH_DSP) + q31_t in; + q31_t in1, in2; + q31_t out1, out2; +#endif + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (q15_t) A << 8 */ + + /* Convert from q7 to q15 and store result in destination buffer */ +#if defined (RISCV_MATH_DSP) + + in = read_q7x4_ia ((q7_t **) &pIn); + + /* rotatate in by 8 and extend two q7_t values to q15_t values */ + in1 = __SXTB16(__ROR(in, 8)); + + /* extend remainig two q7_t values to q15_t values */ + in2 = __SXTB16(in); + + in1 = in1 << 8U; + in2 = in2 << 8U; + + in1 = in1 & 0xFF00FF00; + in2 = in2 & 0xFF00FF00; + + out2 = __PKHTB(in1, in2, 16); + out1 = __PKHBT(in2, in1, 16); + + write_q15x2_ia (&pDst, out1); + write_q15x2_ia (&pDst, out2); + +#else + + *pDst++ = (q15_t) *pIn++ << 8; + *pDst++ = (q15_t) *pIn++ << 8; + *pDst++ = (q15_t) *pIn++ << 8; + *pDst++ = (q15_t) *pIn++ << 8; + +#endif /* #if defined (RISCV_MATH_DSP) */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (q15_t) A << 8 */ + + /* Convert from q7 to q15 and store result in destination buffer */ + *pDst++ = (q15_t) * pIn++ << 8; + + /* Decrement loop counter */ + blkCnt--; + } +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of q7_to_x group + */ diff --git a/components/nmsis/dsp/src/SupportFunctions/riscv_q7_to_q31.c b/components/nmsis/dsp/src/SupportFunctions/riscv_q7_to_q31.c new file mode 100644 index 00000000..2f9a60bf --- /dev/null +++ b/components/nmsis/dsp/src/SupportFunctions/riscv_q7_to_q31.c @@ -0,0 +1,127 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_q7_to_q31.c + * Description: Converts the elements of the Q7 vector to Q31 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup q7_to_x + @{ + */ + +/** + @brief Converts the elements of the Q7 vector to Q31 vector. + @param[in] pSrc points to the Q7 input vector + @param[out] pDst points to the Q31 output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Details + The equation used for the conversion process is: + 
+      pDst[n] = (q31_t) pSrc[n] << 24;   0 <= n < blockSize.
+
+ */ +void riscv_q7_to_q31( + const q7_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + const q7_t *pIn = pSrc; /* Source pointer */ + size_t l; + vint8m2_t v_in; + vint32m8_t v_out; + for (; (l = vsetvl_e8m2(blkCnt)) > 0; blkCnt -= l) + { + v_in = vle8_v_i8m2(pIn, l); + pIn += l; + v_out = vsll_vx_i32m8(vsext_vf4_i32m8(v_in, l), 24U, l); + vse32_v_i32m8 (pDst, v_out, l); + pDst += l; + } +#else + uint32_t blkCnt; /* Loop counter */ + const q7_t *pIn = pSrc; /* Source pointer */ + +#if defined (RISCV_MATH_LOOPUNROLL) + + q31_t in; + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (q31_t) A << 24 */ + + /* Convert from q7 to q31 and store result in destination buffer */ + in = read_q7x4_ia ((q7_t **) &pIn); + + + *pDst++ = (__ROR(in, 8)) & 0xFF000000; + *pDst++ = (__ROR(in, 16)) & 0xFF000000; + *pDst++ = (__ROR(in, 24)) & 0xFF000000; + *pDst++ = (in & 0xFF000000); + + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (q31_t) A << 24 */ + + /* Convert from q7 to q31 and store result in destination buffer */ + *pDst++ = (q31_t) * pIn++ << 24; + + /* Decrement loop counter */ + blkCnt--; + } +#endif /* defined(RISCV_VECTOR) */ +} + +/** + @} end of q7_to_x group + */ diff --git a/components/nmsis/dsp/src/SupportFunctions/riscv_quick_sort_f32.c b/components/nmsis/dsp/src/SupportFunctions/riscv_quick_sort_f32.c new file mode 100644 index 00000000..efb99e9f --- /dev/null +++ b/components/nmsis/dsp/src/SupportFunctions/riscv_quick_sort_f32.c @@ -0,0 +1,182 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_quick_sort_f32.c + * Description: Floating point quick sort + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "riscv_sorting.h" + +static uint32_t riscv_quick_sort_partition_f32(float32_t *pSrc, int32_t first, int32_t last, uint8_t dir) +{ + /* This function will be called */ + int32_t i, j, pivot_index; + float32_t pivot; + float32_t temp; + + /* The first element is the pivot */ + pivot_index = first; + pivot = pSrc[pivot_index]; + + /* Initialize indices for do-while loops */ + i = first - 1; + j = last + 1; + + while(i < j) + { + /* The loop will stop as soon as the indices i and j cross each other. + * + * This event will happen surely since the values of the indices are incremented and + * decrement in the do-while loops that are executed at least once. + * It is impossible to loop forever inside the do-while loops since the pivot is + * always an element of the array and the conditions cannot be always true (at least + * the i-th or the j-th element will be equal to the pivot-th element). + * For example, in the extreme case of an ordered array the do-while loop related to i will stop + * at the first iteration (because pSrc[i]=pSrc[pivot] already), and the loop related to j + * will stop after (last-first) iterations (when j=pivot=i=first). j is returned and + * j+1 is going to be used as pivot by other calls of the function, until j=pivot=last. */ + + /* Move indices to the right and to the left */ + if(dir) + { + /* Compare left elements with pivot */ + do + { + i++; + } while (pSrc[i] < pivot && i pivot); + } + else + { + /* Compare left elements with pivot */ + do + { + i++; + } while (pSrc[i] > pivot && i Swap */ + temp=pSrc[i]; + pSrc[i]=pSrc[j]; + pSrc[j]=temp; + } + } + + return j; +} + +static void riscv_quick_sort_core_f32(float32_t *pSrc, int32_t first, int32_t last, uint8_t dir) +{ + /* If the array [first ... last] has more than one element */ + if(firstdir); + /* The previous function could be called recursively a maximum + * of (blockSize-1) times, generating a stack consumption of 4*(blockSize-1) bytes. */ +} + +/** + @} end of Sorting group + */ diff --git a/components/nmsis/dsp/src/SupportFunctions/riscv_selection_sort_f32.c b/components/nmsis/dsp/src/SupportFunctions/riscv_selection_sort_f32.c new file mode 100644 index 00000000..0fbc2d46 --- /dev/null +++ b/components/nmsis/dsp/src/SupportFunctions/riscv_selection_sort_f32.c @@ -0,0 +1,108 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_selection_sort_f32.c + * Description: Floating point selection sort + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "riscv_sorting.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup Sorting + @{ + */ + +/** + * @private + * @param[in] S points to an instance of the sorting structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * + * @par Algorithm + * The Selection sort algorithm is a comparison algorithm that + * divides the input array into a sorted and an unsorted sublist + * (initially the sorted sublist is empty and the unsorted sublist + * is the input array), looks for the smallest (or biggest) + * element in the unsorted sublist, swapping it with the leftmost + * one, and moving the sublists boundary one element to the right. + * + * @par It's an in-place algorithm. In order to obtain an out-of-place + * function, a memcpy of the source vector is performed. + */ + +void riscv_selection_sort_f32( + const riscv_sort_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t i, j, k; + uint8_t dir = S->dir; + float32_t temp; + + float32_t * pA; + + if(pSrc != pDst) // out-of-place + { + memcpy(pDst, pSrc, blockSize*sizeof(float32_t) ); + pA = pDst; + } + else + pA = pSrc; + + /* Move the boundary one element to the right */ + for (i=0; ialg) + { + case RISCV_SORT_BITONIC: + riscv_bitonic_sort_f32(S, pSrc, pDst, blockSize); + break; + + case RISCV_SORT_BUBBLE: + riscv_bubble_sort_f32(S, pSrc, pDst, blockSize); + break; + + case RISCV_SORT_HEAP: + riscv_heap_sort_f32(S, pSrc, pDst, blockSize); + break; + + case RISCV_SORT_INSERTION: + riscv_insertion_sort_f32(S, pSrc, pDst, blockSize); + break; + + case RISCV_SORT_QUICK: + riscv_quick_sort_f32(S, pSrc, pDst, blockSize); + break; + + case RISCV_SORT_SELECTION: + riscv_selection_sort_f32(S, pSrc, pDst, blockSize); + break; + } +} + +/** + @} end of Sorting group + */ diff --git a/components/nmsis/dsp/src/SupportFunctions/riscv_sort_init_f32.c b/components/nmsis/dsp/src/SupportFunctions/riscv_sort_init_f32.c new file mode 100644 index 00000000..9fb5b70a --- /dev/null +++ b/components/nmsis/dsp/src/SupportFunctions/riscv_sort_init_f32.c @@ -0,0 +1,55 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_sort_init_f32.c + * Description: Floating point sort initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "riscv_sorting.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup Sorting + @{ + */ + + + /** + * @param[in,out] S points to an instance of the sorting structure. + * @param[in] alg Selected algorithm. + * @param[in] dir Sorting order. + */ +void riscv_sort_init_f32(riscv_sort_instance_f32 * S, riscv_sort_alg alg, riscv_sort_dir dir) +{ + S->alg = alg; + S->dir = dir; +} + +/** + @} end of Sorting group + */ diff --git a/components/nmsis/dsp/src/SupportFunctions/riscv_weighted_sum_f16.c b/components/nmsis/dsp/src/SupportFunctions/riscv_weighted_sum_f16.c new file mode 100644 index 00000000..521da6c4 --- /dev/null +++ b/components/nmsis/dsp/src/SupportFunctions/riscv_weighted_sum_f16.c @@ -0,0 +1,96 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_weighted_sum_f16.c + * Description: Weighted Sum + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include + +#include "dsp/support_functions_f16.h" + +#if defined(RISCV_FLOAT16_SUPPORTED) + +/** + @ingroup groupSupport + */ + +/** + @defgroup weightedsum Weighted Sum + + Weighted sum of values + */ + + +/** + * @addtogroup weightedsum + * @{ + */ + + +/** + * @brief Weighted sum + * + * + * @param[in] *in Array of input values. + * @param[in] *weigths Weights + * @param[in] blockSize Number of samples in the input array. + * @return Weighted sum + * + */ + + +float16_t riscv_weighted_sum_f16(const float16_t *in, const float16_t *weigths, uint32_t blockSize) +{ + + _Float16 accum1, accum2; + const float16_t *pIn, *pW; + uint32_t blkCnt; + + + pIn = in; + pW = weigths; + + accum1=0.0f16; + accum2=0.0f16; + + blkCnt = blockSize; + while(blkCnt > 0) + { + accum1 += (_Float16)*pIn++ * (_Float16)*pW; + accum2 += (_Float16)*pW++; + blkCnt--; + } + + return(accum1 / accum2); +} + +/** + * @} end of weightedsum group + */ + +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ + diff --git a/components/nmsis/dsp/src/SupportFunctions/riscv_weighted_sum_f32.c b/components/nmsis/dsp/src/SupportFunctions/riscv_weighted_sum_f32.c new file mode 100644 index 00000000..ab6be3ac --- /dev/null +++ b/components/nmsis/dsp/src/SupportFunctions/riscv_weighted_sum_f32.c @@ -0,0 +1,107 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_weighted_sum_f32.c + * Description: Weighted Sum + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include + +#include "dsp/support_functions.h" + +/** + * @addtogroup weightedsum + * @{ + */ + + +/** + * @brief Weighted sum + * + * + * @param[in] *in Array of input values. + * @param[in] *weigths Weights + * @param[in] blockSize Number of samples in the input array. + * @return Weighted sum + * + */ + +float32_t riscv_weighted_sum_f32(const float32_t *in, const float32_t *weigths, uint32_t blockSize) +{ + + float32_t accum1, accum2; + const float32_t *pIn, *pW; + uint32_t blkCnt; + +#if defined(RISCV_VECTOR) + uint32_t blkCnt_v; + size_t l; + float32_t temp_max; + vfloat32m8_t v_x, v_y; + vfloat32m8_t v_a, v_b; + vfloat32m1_t v_temp; + l = vsetvl_e32m1(1); + v_temp = vfsub_vv_f32m1(v_temp, v_temp, l); +#endif + + pIn = in; + pW = weigths; + + accum1=0.0f; + accum2=0.0f; + +#if defined(RISCV_VECTOR) + blkCnt_v = blockSize; + l = vsetvl_e32m8(blkCnt_v); + v_a = vfsub_vv_f32m8(v_a,v_a, l); + v_b = vfsub_vv_f32m8(v_b,v_b, l); + for (; (l = vsetvl_e32m8(blkCnt_v)) > 0; blkCnt_v -= l) { + v_x = vle32_v_f32m8(pIn, l); + v_y = vle32_v_f32m8(pW, l); + v_a = vfmacc_vv_f32m8(v_a,v_x,v_y, l); + v_b = vfadd_vv_f32m8(v_b,v_y, l); + pIn += l; + pW += l; + } + l = vsetvl_e32m8(blockSize); + accum1 = vfmv_f_s_f32m1_f32 (vfredsum_vs_f32m8_f32m1(v_temp,v_a,v_temp, l)); + l = vsetvl_e32m8(blockSize); + accum2 = vfmv_f_s_f32m1_f32 (vfredsum_vs_f32m8_f32m1(v_temp,v_b,v_temp, l)); +#else + blkCnt = blockSize; + while(blkCnt > 0) + { + accum1 += *pIn++ * *pW; + accum2 += *pW++; + blkCnt--; + } +#endif + return(accum1 / accum2); +} + +/** + * @} end of weightedsum group + */ diff --git a/components/nmsis/dsp/src/TransformFunctions/TransformFunctions.c b/components/nmsis/dsp/src/TransformFunctions/TransformFunctions.c new file mode 100644 index 00000000..1860276c --- /dev/null +++ b/components/nmsis/dsp/src/TransformFunctions/TransformFunctions.c @@ -0,0 +1,75 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: TransformFunctions.c + * Description: Combination of all transform function source files. + * + * $Date: 18. March 2019 + * $Revision: V1.0.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2019 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "riscv_bitreversal.c" +#include "riscv_bitreversal2.c" +#include "riscv_cfft_f32.c" +#include "riscv_cfft_f64.c" +#include "riscv_cfft_q15.c" +#include "riscv_cfft_q31.c" +#include "riscv_cfft_init_f32.c" +#include "riscv_cfft_init_f64.c" +#include "riscv_cfft_init_q15.c" +#include "riscv_cfft_init_q31.c" +#include "riscv_cfft_radix2_f32.c" +#include "riscv_cfft_radix2_q15.c" +#include "riscv_cfft_radix2_q31.c" +#include "riscv_cfft_radix4_f32.c" +#include "riscv_cfft_radix4_q15.c" +#include "riscv_cfft_radix4_q31.c" +#include "riscv_cfft_radix8_f32.c" +#include "riscv_rfft_fast_f32.c" +#include "riscv_rfft_fast_f64.c" +#include "riscv_rfft_fast_init_f32.c" +#include "riscv_rfft_fast_init_f64.c" + +/* Deprecated */ + +#include "riscv_dct4_f32.c" +#include "riscv_dct4_init_f32.c" +#include "riscv_dct4_init_q15.c" +#include "riscv_dct4_init_q31.c" +#include "riscv_dct4_q15.c" +#include "riscv_dct4_q31.c" + +#include "riscv_rfft_f32.c" +#include "riscv_rfft_q15.c" +#include "riscv_rfft_q31.c" + +#include "riscv_rfft_init_f32.c" +#include "riscv_rfft_init_q15.c" +#include "riscv_rfft_init_q31.c" + +#include "riscv_cfft_radix4_init_f32.c" +#include "riscv_cfft_radix4_init_q15.c" +#include "riscv_cfft_radix4_init_q31.c" + +#include "riscv_cfft_radix2_init_f32.c" +#include "riscv_cfft_radix2_init_q15.c" +#include "riscv_cfft_radix2_init_q31.c" diff --git a/components/nmsis/dsp/src/TransformFunctions/TransformFunctionsF16.c b/components/nmsis/dsp/src/TransformFunctions/TransformFunctionsF16.c new file mode 100644 index 00000000..4ebc50cf --- /dev/null +++ b/components/nmsis/dsp/src/TransformFunctions/TransformFunctionsF16.c @@ -0,0 +1,42 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: TransformFunctionsF16.c + * Description: Combination of all transform function f16 source files. + * + * $Date: 20. April 2020 + * $Revision: V1.0.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2019 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "riscv_cfft_f16.c" +#include "riscv_cfft_init_f16.c" +#include "riscv_cfft_radix2_f16.c" +#include "riscv_cfft_radix4_f16.c" +#include "riscv_rfft_fast_init_f16.c" +#include "riscv_rfft_fast_f16.c" +#include "riscv_cfft_radix8_f16.c" + +#include "riscv_bitreversal_f16.c" + +/* Deprecated */ +#include "riscv_cfft_radix2_init_f16.c" +#include "riscv_cfft_radix4_init_f16.c" diff --git a/components/nmsis/dsp/src/TransformFunctions/riscv_bitreversal.c b/components/nmsis/dsp/src/TransformFunctions/riscv_bitreversal.c new file mode 100644 index 00000000..d7597413 --- /dev/null +++ b/components/nmsis/dsp/src/TransformFunctions/riscv_bitreversal.c @@ -0,0 +1,231 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_bitreversal.c + * Description: Bitreversal functions + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" +#include "riscv_common_tables.h" + + +/** + @brief In-place floating-point bit reversal function. + @param[in,out] pSrc points to in-place floating-point data buffer + @param[in] fftSize length of FFT + @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table + @param[in] pBitRevTab points to bit reversal table + @return none + */ + +void riscv_bitreversal_f32( + float32_t * pSrc, + uint16_t fftSize, + uint16_t bitRevFactor, + const uint16_t * pBitRevTab) +{ + uint16_t fftLenBy2, fftLenBy2p1; + uint16_t i, j; + float32_t in; + + /* Initializations */ + j = 0U; + fftLenBy2 = fftSize >> 1U; + fftLenBy2p1 = (fftSize >> 1U) + 1U; + + /* Bit Reversal Implementation */ + for (i = 0U; i <= (fftLenBy2 - 2U); i += 2U) + { + if (i < j) + { + /* pSrc[i] <-> pSrc[j]; */ + in = pSrc[2U * i]; + pSrc[2U * i] = pSrc[2U * j]; + pSrc[2U * j] = in; + + /* pSrc[i+1U] <-> pSrc[j+1U] */ + in = pSrc[(2U * i) + 1U]; + pSrc[(2U * i) + 1U] = pSrc[(2U * j) + 1U]; + pSrc[(2U * j) + 1U] = in; + + /* pSrc[i+fftLenBy2p1] <-> pSrc[j+fftLenBy2p1] */ + in = pSrc[2U * (i + fftLenBy2p1)]; + pSrc[2U * (i + fftLenBy2p1)] = pSrc[2U * (j + fftLenBy2p1)]; + pSrc[2U * (j + fftLenBy2p1)] = in; + + /* pSrc[i+fftLenBy2p1+1U] <-> pSrc[j+fftLenBy2p1+1U] */ + in = pSrc[(2U * (i + fftLenBy2p1)) + 1U]; + pSrc[(2U * (i + fftLenBy2p1)) + 1U] = + pSrc[(2U * (j + fftLenBy2p1)) + 1U]; + pSrc[(2U * (j + fftLenBy2p1)) + 1U] = in; + + } + + /* pSrc[i+1U] <-> pSrc[j+1U] */ + in = pSrc[2U * (i + 1U)]; + pSrc[2U * (i + 1U)] = pSrc[2U * (j + fftLenBy2)]; + pSrc[2U * (j + fftLenBy2)] = in; + + /* pSrc[i+2U] <-> pSrc[j+2U] */ + in = pSrc[(2U * (i + 1U)) + 1U]; + pSrc[(2U * (i + 1U)) + 1U] = pSrc[(2U * (j + fftLenBy2)) + 1U]; + pSrc[(2U * (j + fftLenBy2)) + 1U] = in; + + /* Reading the index for the bit reversal */ + j = *pBitRevTab; + + /* Updating the bit reversal index depending on the fft length */ + pBitRevTab += bitRevFactor; + } +} + + +/** + @brief In-place Q31 bit reversal function. + @param[in,out] pSrc points to in-place Q31 data buffer. + @param[in] fftLen length of FFT. + @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table + @param[in] pBitRevTab points to bit reversal table + @return none +*/ + +void riscv_bitreversal_q31( + q31_t * pSrc, + uint32_t fftLen, + uint16_t bitRevFactor, + const uint16_t * pBitRevTab) +{ + uint32_t fftLenBy2, fftLenBy2p1, i, j; + q31_t in; + + /* Initializations */ + j = 0U; + fftLenBy2 = fftLen / 2U; + fftLenBy2p1 = (fftLen / 2U) + 1U; + + /* Bit Reversal Implementation */ + for (i = 0U; i <= (fftLenBy2 - 2U); i += 2U) + { + if (i < j) + { + /* pSrc[i] <-> pSrc[j]; */ + in = pSrc[2U * i]; + pSrc[2U * i] = pSrc[2U * j]; + pSrc[2U * j] = in; + + /* pSrc[i+1U] <-> pSrc[j+1U] */ + in = pSrc[(2U * i) + 1U]; + pSrc[(2U * i) + 1U] = pSrc[(2U * j) + 1U]; + pSrc[(2U * j) + 1U] = in; + + /* pSrc[i+fftLenBy2p1] <-> pSrc[j+fftLenBy2p1] */ + in = pSrc[2U * (i + fftLenBy2p1)]; + pSrc[2U * (i + fftLenBy2p1)] = pSrc[2U * (j + fftLenBy2p1)]; + pSrc[2U * (j + fftLenBy2p1)] = in; + + /* pSrc[i+fftLenBy2p1+1U] <-> pSrc[j+fftLenBy2p1+1U] */ + in = pSrc[(2U * (i + fftLenBy2p1)) + 1U]; + pSrc[(2U * (i + fftLenBy2p1)) + 1U] = + pSrc[(2U * (j + fftLenBy2p1)) + 1U]; + pSrc[(2U * (j + fftLenBy2p1)) + 1U] = in; + + } + + /* pSrc[i+1U] <-> pSrc[j+1U] */ + in = pSrc[2U * (i + 1U)]; + pSrc[2U * (i + 1U)] = pSrc[2U * (j + fftLenBy2)]; + pSrc[2U * (j + fftLenBy2)] = in; + + /* pSrc[i+2U] <-> pSrc[j+2U] */ + in = pSrc[(2U * (i + 1U)) + 1U]; + pSrc[(2U * (i + 1U)) + 1U] = pSrc[(2U * (j + fftLenBy2)) + 1U]; + pSrc[(2U * (j + fftLenBy2)) + 1U] = in; + + /* Reading the index for the bit reversal */ + j = *pBitRevTab; + + /* Updating the bit reversal index depending on the fft length */ + pBitRevTab += bitRevFactor; + } +} + + + +/** + @brief In-place Q15 bit reversal function. + @param[in,out] pSrc16 points to in-place Q15 data buffer + @param[in] fftLen length of FFT + @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table + @param[in] pBitRevTab points to bit reversal table + @return none +*/ + +void riscv_bitreversal_q15( + q15_t * pSrc16, + uint32_t fftLen, + uint16_t bitRevFactor, + const uint16_t * pBitRevTab) +{ + q31_t *pSrc = (q31_t *) pSrc16; + q31_t in; + uint32_t fftLenBy2, fftLenBy2p1; + uint32_t i, j; + + /* Initializations */ + j = 0U; + fftLenBy2 = fftLen / 2U; + fftLenBy2p1 = (fftLen / 2U) + 1U; + + /* Bit Reversal Implementation */ + for (i = 0U; i <= (fftLenBy2 - 2U); i += 2U) + { + if (i < j) + { + /* pSrc[i] <-> pSrc[j]; */ + /* pSrc[i+1U] <-> pSrc[j+1U] */ + in = pSrc[i]; + pSrc[i] = pSrc[j]; + pSrc[j] = in; + + /* pSrc[i + fftLenBy2p1] <-> pSrc[j + fftLenBy2p1]; */ + /* pSrc[i + fftLenBy2p1+1U] <-> pSrc[j + fftLenBy2p1+1U] */ + in = pSrc[i + fftLenBy2p1]; + pSrc[i + fftLenBy2p1] = pSrc[j + fftLenBy2p1]; + pSrc[j + fftLenBy2p1] = in; + } + + /* pSrc[i+1U] <-> pSrc[j+fftLenBy2]; */ + /* pSrc[i+2] <-> pSrc[j+fftLenBy2+1U] */ + in = pSrc[i + 1U]; + pSrc[i + 1U] = pSrc[j + fftLenBy2]; + pSrc[j + fftLenBy2] = in; + + /* Reading the index for the bit reversal */ + j = *pBitRevTab; + + /* Updating the bit reversal index depending on the fft length */ + pBitRevTab += bitRevFactor; + } +} diff --git a/components/nmsis/dsp/src/TransformFunctions/riscv_bitreversal2.c b/components/nmsis/dsp/src/TransformFunctions/riscv_bitreversal2.c new file mode 100644 index 00000000..3a5cbe70 --- /dev/null +++ b/components/nmsis/dsp/src/TransformFunctions/riscv_bitreversal2.c @@ -0,0 +1,135 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_bitreversal2.c + * Description: Bitreversal functions + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2019 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" +#include "riscv_common_tables.h" + + +/** + @brief In-place 64 bit reversal function. + @param[in,out] pSrc points to in-place buffer of unknown 64-bit data type + @param[in] bitRevLen bit reversal table length + @param[in] pBitRevTab points to bit reversal table + @return none +*/ + +void riscv_bitreversal_64( + uint64_t *pSrc, + const uint16_t bitRevLen, + const uint16_t *pBitRevTab) +{ + uint64_t a, b, i, tmp; + + for (i = 0; i < bitRevLen; ) + { + a = pBitRevTab[i ] >> 2; + b = pBitRevTab[i + 1] >> 2; + + //real + tmp = pSrc[a]; + pSrc[a] = pSrc[b]; + pSrc[b] = tmp; + + //complex + tmp = pSrc[a+1]; + pSrc[a+1] = pSrc[b+1]; + pSrc[b+1] = tmp; + + i += 2; + } +} + +/** + @brief In-place 32 bit reversal function. + @param[in,out] pSrc points to in-place buffer of unknown 32-bit data type + @param[in] bitRevLen bit reversal table length + @param[in] pBitRevTab points to bit reversal table + @return none +*/ + +void riscv_bitreversal_32( + uint32_t *pSrc, + const uint16_t bitRevLen, + const uint16_t *pBitRevTab) +{ + uint32_t a, b, i, tmp; + + for (i = 0; i < bitRevLen; ) + { + a = pBitRevTab[i ] >> 2; + b = pBitRevTab[i + 1] >> 2; + + //real + tmp = pSrc[a]; + pSrc[a] = pSrc[b]; + pSrc[b] = tmp; + + //complex + tmp = pSrc[a+1]; + pSrc[a+1] = pSrc[b+1]; + pSrc[b+1] = tmp; + + i += 2; + } +} + + +/** + @brief In-place 16 bit reversal function. + @param[in,out] pSrc points to in-place buffer of unknown 16-bit data type + @param[in] bitRevLen bit reversal table length + @param[in] pBitRevTab points to bit reversal table + @return none +*/ + +void riscv_bitreversal_16( + uint16_t *pSrc, + const uint16_t bitRevLen, + const uint16_t *pBitRevTab) +{ + uint16_t a, b, i, tmp; + + for (i = 0; i < bitRevLen; ) + { + a = pBitRevTab[i ] >> 2; + b = pBitRevTab[i + 1] >> 2; + + //real + tmp = pSrc[a]; + pSrc[a] = pSrc[b]; + pSrc[b] = tmp; + + //complex + tmp = pSrc[a+1]; + pSrc[a+1] = pSrc[b+1]; + pSrc[b+1] = tmp; + + i += 2; + } +} diff --git a/components/nmsis/dsp/src/TransformFunctions/riscv_bitreversal_f16.c b/components/nmsis/dsp/src/TransformFunctions/riscv_bitreversal_f16.c new file mode 100644 index 00000000..da84510b --- /dev/null +++ b/components/nmsis/dsp/src/TransformFunctions/riscv_bitreversal_f16.c @@ -0,0 +1,103 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_bitreversal_f16.c + * Description: Bitreversal functions + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions_f16.h" + +/* +* @brief In-place bit reversal function. +* @param[in, out] *pSrc points to the in-place buffer of floating-point data type. +* @param[in] fftSize length of the FFT. +* @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table. +* @param[in] *pBitRevTab points to the bit reversal table. +* @return none. +*/ + +#if defined(RISCV_FLOAT16_SUPPORTED) + +void riscv_bitreversal_f16( +float16_t * pSrc, +uint16_t fftSize, +uint16_t bitRevFactor, +const uint16_t * pBitRevTab) +{ + uint16_t fftLenBy2, fftLenBy2p1; + uint16_t i, j; + float16_t in; + + /* Initializations */ + j = 0U; + fftLenBy2 = fftSize >> 1U; + fftLenBy2p1 = (fftSize >> 1U) + 1U; + + /* Bit Reversal Implementation */ + for (i = 0U; i <= (fftLenBy2 - 2U); i += 2U) + { + if (i < j) + { + /* pSrc[i] <-> pSrc[j]; */ + in = pSrc[2U * i]; + pSrc[2U * i] = pSrc[2U * j]; + pSrc[2U * j] = in; + + /* pSrc[i+1U] <-> pSrc[j+1U] */ + in = pSrc[(2U * i) + 1U]; + pSrc[(2U * i) + 1U] = pSrc[(2U * j) + 1U]; + pSrc[(2U * j) + 1U] = in; + + /* pSrc[i+fftLenBy2p1] <-> pSrc[j+fftLenBy2p1] */ + in = pSrc[2U * (i + fftLenBy2p1)]; + pSrc[2U * (i + fftLenBy2p1)] = pSrc[2U * (j + fftLenBy2p1)]; + pSrc[2U * (j + fftLenBy2p1)] = in; + + /* pSrc[i+fftLenBy2p1+1U] <-> pSrc[j+fftLenBy2p1+1U] */ + in = pSrc[(2U * (i + fftLenBy2p1)) + 1U]; + pSrc[(2U * (i + fftLenBy2p1)) + 1U] = + pSrc[(2U * (j + fftLenBy2p1)) + 1U]; + pSrc[(2U * (j + fftLenBy2p1)) + 1U] = in; + + } + + /* pSrc[i+1U] <-> pSrc[j+1U] */ + in = pSrc[2U * (i + 1U)]; + pSrc[2U * (i + 1U)] = pSrc[2U * (j + fftLenBy2)]; + pSrc[2U * (j + fftLenBy2)] = in; + + /* pSrc[i+2U] <-> pSrc[j+2U] */ + in = pSrc[(2U * (i + 1U)) + 1U]; + pSrc[(2U * (i + 1U)) + 1U] = pSrc[(2U * (j + fftLenBy2)) + 1U]; + pSrc[(2U * (j + fftLenBy2)) + 1U] = in; + + /* Reading the index for the bit reversal */ + j = *pBitRevTab; + + /* Updating the bit reversal index depending on the fft length */ + pBitRevTab += bitRevFactor; + } +} +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ diff --git a/components/nmsis/dsp/src/TransformFunctions/riscv_cfft_f16.c b/components/nmsis/dsp/src/TransformFunctions/riscv_cfft_f16.c new file mode 100644 index 00000000..398ec56b --- /dev/null +++ b/components/nmsis/dsp/src/TransformFunctions/riscv_cfft_f16.c @@ -0,0 +1,292 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_cfft_f32.c + * Description: Combined Radix Decimation in Frequency CFFT Floating point processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions_f16.h" +#include "riscv_common_tables_f16.h" + + + +#if defined(RISCV_FLOAT16_SUPPORTED) + +extern void riscv_bitreversal_16( + uint16_t * pSrc, + const uint16_t bitRevLen, + const uint16_t * pBitRevTable); + + +extern void riscv_cfft_radix4by2_f16( + float16_t * pSrc, + uint32_t fftLen, + const float16_t * pCoef); + +extern void riscv_radix4_butterfly_f16( + float16_t * pSrc, + uint16_t fftLen, + const float16_t * pCoef, + uint16_t twidCoefModifier); + +/** + @ingroup groupTransforms + */ + +/** + @defgroup ComplexFFT Complex FFT Functions + + @par + The Fast Fourier Transform (FFT) is an efficient algorithm for computing the + Discrete Fourier Transform (DFT). The FFT can be orders of magnitude faster + than the DFT, especially for long lengths. + The algorithms described in this section + operate on complex data. A separate set of functions is devoted to handling + of real sequences. + @par + There are separate algorithms for handling floating-point, Q15, and Q31 data + types. The algorithms available for each data type are described next. + @par + The FFT functions operate in-place. That is, the array holding the input data + will also be used to hold the corresponding result. The input data is complex + and contains 2*fftLen interleaved values as shown below. + 
{real[0], imag[0], real[1], imag[1], ...}
+ The FFT result will be contained in the same array and the frequency domain + values will have the same interleaving. + + @par Floating-point + The floating-point complex FFT uses a mixed-radix algorithm. Multiple radix-8 + stages are performed along with a single radix-2 or radix-4 stage, as needed. + The algorithm supports lengths of [16, 32, 64, ..., 4096] and each length uses + a different twiddle factor table. + @par + The function uses the standard FFT definition and output values may grow by a + factor of fftLen when computing the forward transform. The + inverse transform includes a scale of 1/fftLen as part of the + calculation and this matches the textbook definition of the inverse FFT. + @par + For the MVE version, the new riscv_cfft_init_f32 initialization function is + mandatory. Compilation flags are available to include only the required tables for the + needed FFTs. Other FFT versions can continue to be initialized as + explained below. + @par + For not MVE versions, pre-initialized data structures containing twiddle factors + and bit reversal tables are provided and defined in riscv_const_structs.h. Include + this header in your function and then pass one of the constant structures as + an argument to riscv_cfft_f32. For example: + @par + riscv_cfft_f32(riscv_cfft_sR_f32_len64, pSrc, 1, 1) + @par + computes a 64-point inverse complex FFT including bit reversal. + The data structures are treated as constant data and not modified during the + calculation. The same data structure can be reused for multiple transforms + including mixing forward and inverse transforms. + @par + Earlier releases of the library provided separate radix-2 and radix-4 + algorithms that operated on floating-point data. These functions are still + provided but are deprecated. The older functions are slower and less general + than the new functions. + @par + An example of initialization of the constants for the riscv_cfft_f32 function follows: + @code + const static riscv_cfft_instance_f32 *S; + ... + switch (length) { + case 16: + S = &riscv_cfft_sR_f32_len16; + break; + case 32: + S = &riscv_cfft_sR_f32_len32; + break; + case 64: + S = &riscv_cfft_sR_f32_len64; + break; + case 128: + S = &riscv_cfft_sR_f32_len128; + break; + case 256: + S = &riscv_cfft_sR_f32_len256; + break; + case 512: + S = &riscv_cfft_sR_f32_len512; + break; + case 1024: + S = &riscv_cfft_sR_f32_len1024; + break; + case 2048: + S = &riscv_cfft_sR_f32_len2048; + break; + case 4096: + S = &riscv_cfft_sR_f32_len4096; + break; + } + @endcode + @par + The new riscv_cfft_init_f32 can also be used. + @par Q15 and Q31 + The floating-point complex FFT uses a mixed-radix algorithm. Multiple radix-4 + stages are performed along with a single radix-2 stage, as needed. + The algorithm supports lengths of [16, 32, 64, ..., 4096] and each length uses + a different twiddle factor table. + @par + The function uses the standard FFT definition and output values may grow by a + factor of fftLen when computing the forward transform. The + inverse transform includes a scale of 1/fftLen as part of the + calculation and this matches the textbook definition of the inverse FFT. + @par + Pre-initialized data structures containing twiddle factors and bit reversal + tables are provided and defined in riscv_const_structs.h. Include + this header in your function and then pass one of the constant structures as + an argument to riscv_cfft_q31. For example: + @par + riscv_cfft_q31(riscv_cfft_sR_q31_len64, pSrc, 1, 1) + @par + computes a 64-point inverse complex FFT including bit reversal. + The data structures are treated as constant data and not modified during the + calculation. The same data structure can be reused for multiple transforms + including mixing forward and inverse transforms. + @par + Earlier releases of the library provided separate radix-2 and radix-4 + algorithms that operated on floating-point data. These functions are still + provided but are deprecated. The older functions are slower and less general + than the new functions. + @par + An example of initialization of the constants for the riscv_cfft_q31 function follows: + @code + const static riscv_cfft_instance_q31 *S; + ... + switch (length) { + case 16: + S = &riscv_cfft_sR_q31_len16; + break; + case 32: + S = &riscv_cfft_sR_q31_len32; + break; + case 64: + S = &riscv_cfft_sR_q31_len64; + break; + case 128: + S = &riscv_cfft_sR_q31_len128; + break; + case 256: + S = &riscv_cfft_sR_q31_len256; + break; + case 512: + S = &riscv_cfft_sR_q31_len512; + break; + case 1024: + S = &riscv_cfft_sR_q31_len1024; + break; + case 2048: + S = &riscv_cfft_sR_q31_len2048; + break; + case 4096: + S = &riscv_cfft_sR_q31_len4096; + break; + } + @endcode + + */ + + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Processing function for the floating-point complex FFT. + @param[in] S points to an instance of the floating-point CFFT structure + @param[in,out] p1 points to the complex data buffer of size 2*fftLen. Processing occurs in-place + @param[in] ifftFlag flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return none + */ + +void riscv_cfft_f16( + const riscv_cfft_instance_f16 * S, + float16_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + uint32_t L = S->fftLen, l; + float16_t invL, * pSrc; + + if (ifftFlag == 1U) + { + /* Conjugate input data */ + pSrc = p1 + 1; + for(l=0; lpTwiddle, 1U); + break; + + case 32: + case 128: + case 512: + case 2048: + riscv_cfft_radix4by2_f16 ( p1, L, (float16_t*)S->pTwiddle); + break; + + } + + if ( bitReverseFlag ) + riscv_bitreversal_16((uint16_t*)p1, S->bitRevLength,(uint16_t*)S->pBitRevTable); + + if (ifftFlag == 1U) + { + invL = 1.0f/(float16_t)L; + /* Conjugate and scale output data */ + pSrc = p1; + for(l=0; l2*fftLen interleaved values as shown below. + 
{real[0], imag[0], real[1], imag[1], ...}
+ The FFT result will be contained in the same array and the frequency domain + values will have the same interleaving. + + @par Floating-point + The floating-point complex FFT uses a mixed-radix algorithm. Multiple radix-8 + stages are performed along with a single radix-2 or radix-4 stage, as needed. + The algorithm supports lengths of [16, 32, 64, ..., 4096] and each length uses + a different twiddle factor table. + @par + The function uses the standard FFT definition and output values may grow by a + factor of fftLen when computing the forward transform. The + inverse transform includes a scale of 1/fftLen as part of the + calculation and this matches the textbook definition of the inverse FFT. + @par + For the MVE version, the new riscv_cfft_init_f32 initialization function is + mandatory. Compilation flags are available to include only the required tables for the + needed FFTs. Other FFT versions can continue to be initialized as + explained below. + @par + For not MVE versions, pre-initialized data structures containing twiddle factors + and bit reversal tables are provided and defined in riscv_const_structs.h. Include + this header in your function and then pass one of the constant structures as + an argument to riscv_cfft_f32. For example: + @par + riscv_cfft_f32(riscv_cfft_sR_f32_len64, pSrc, 1, 1) + @par + computes a 64-point inverse complex FFT including bit reversal. + The data structures are treated as constant data and not modified during the + calculation. The same data structure can be reused for multiple transforms + including mixing forward and inverse transforms. + @par + Earlier releases of the library provided separate radix-2 and radix-4 + algorithms that operated on floating-point data. These functions are still + provided but are deprecated. The older functions are slower and less general + than the new functions. + @par + An example of initialization of the constants for the riscv_cfft_f32 function follows: + @code + const static riscv_cfft_instance_f32 *S; + ... + switch (length) { + case 16: + S = &riscv_cfft_sR_f32_len16; + break; + case 32: + S = &riscv_cfft_sR_f32_len32; + break; + case 64: + S = &riscv_cfft_sR_f32_len64; + break; + case 128: + S = &riscv_cfft_sR_f32_len128; + break; + case 256: + S = &riscv_cfft_sR_f32_len256; + break; + case 512: + S = &riscv_cfft_sR_f32_len512; + break; + case 1024: + S = &riscv_cfft_sR_f32_len1024; + break; + case 2048: + S = &riscv_cfft_sR_f32_len2048; + break; + case 4096: + S = &riscv_cfft_sR_f32_len4096; + break; + } + @endcode + @par + The new riscv_cfft_init_f32 can also be used. + @par Q15 and Q31 + The floating-point complex FFT uses a mixed-radix algorithm. Multiple radix-4 + stages are performed along with a single radix-2 stage, as needed. + The algorithm supports lengths of [16, 32, 64, ..., 4096] and each length uses + a different twiddle factor table. + @par + The function uses the standard FFT definition and output values may grow by a + factor of fftLen when computing the forward transform. The + inverse transform includes a scale of 1/fftLen as part of the + calculation and this matches the textbook definition of the inverse FFT. + @par + Pre-initialized data structures containing twiddle factors and bit reversal + tables are provided and defined in riscv_const_structs.h. Include + this header in your function and then pass one of the constant structures as + an argument to riscv_cfft_q31. For example: + @par + riscv_cfft_q31(riscv_cfft_sR_q31_len64, pSrc, 1, 1) + @par + computes a 64-point inverse complex FFT including bit reversal. + The data structures are treated as constant data and not modified during the + calculation. The same data structure can be reused for multiple transforms + including mixing forward and inverse transforms. + @par + Earlier releases of the library provided separate radix-2 and radix-4 + algorithms that operated on floating-point data. These functions are still + provided but are deprecated. The older functions are slower and less general + than the new functions. + @par + An example of initialization of the constants for the riscv_cfft_q31 function follows: + @code + const static riscv_cfft_instance_q31 *S; + ... + switch (length) { + case 16: + S = &riscv_cfft_sR_q31_len16; + break; + case 32: + S = &riscv_cfft_sR_q31_len32; + break; + case 64: + S = &riscv_cfft_sR_q31_len64; + break; + case 128: + S = &riscv_cfft_sR_q31_len128; + break; + case 256: + S = &riscv_cfft_sR_q31_len256; + break; + case 512: + S = &riscv_cfft_sR_q31_len512; + break; + case 1024: + S = &riscv_cfft_sR_q31_len1024; + break; + case 2048: + S = &riscv_cfft_sR_q31_len2048; + break; + case 4096: + S = &riscv_cfft_sR_q31_len4096; + break; + } + @endcode + + */ + +void riscv_cfft_radix8by2_f32 (riscv_cfft_instance_f32 * S, float32_t * p1) +{ + uint32_t L = S->fftLen; + float32_t * pCol1, * pCol2, * pMid1, * pMid2; + float32_t * p2 = p1 + L; + const float32_t * tw = (float32_t *) S->pTwiddle; + float32_t t1[4], t2[4], t3[4], t4[4], twR, twI; + float32_t m0, m1, m2, m3; + uint32_t l; + + pCol1 = p1; + pCol2 = p2; + + /* Define new length */ + L >>= 1; + + /* Initialize mid pointers */ + pMid1 = p1 + L; + pMid2 = p2 + L; + + /* do two dot Fourier transform */ + for (l = L >> 2; l > 0; l-- ) + { +// #if defined(RISCV_VECTOR) + t1[0] = p1[0]; + t1[1] = p1[1]; + t1[2] = p1[2]; + t1[3] = p1[3]; + + t2[0] = p2[0]; + t2[1] = p2[1]; + t2[2] = p2[2]; + t2[3] = p2[3]; + + t3[0] = pMid1[0]; + t3[1] = pMid1[1]; + t3[2] = pMid1[2]; + t3[3] = pMid1[3]; + + t4[0] = pMid2[0]; + t4[1] = pMid2[1]; + t4[2] = pMid2[2]; + t4[3] = pMid2[3]; + + *p1++ = t1[0] + t2[0]; + *p1++ = t1[1] + t2[1]; + *p1++ = t1[2] + t2[2]; + *p1++ = t1[3] + t2[3]; /* col 1 */ + + t2[0] = t1[0] - t2[0]; + t2[1] = t1[1] - t2[1]; + t2[2] = t1[2] - t2[2]; + t2[3] = t1[3] - t2[3]; /* for col 2 */ + + *pMid1++ = t3[0] + t4[0]; + *pMid1++ = t3[1] + t4[1]; + *pMid1++ = t3[2] + t4[2]; + *pMid1++ = t3[3] + t4[3]; /* col 1 */ + + t4[0] = t4[0] - t3[0]; + t4[1] = t4[1] - t3[1]; + t4[2] = t4[2] - t3[2]; + t4[3] = t4[3] - t3[3]; /* for col 2 */ + + twR = *tw++; + twI = *tw++; + + /* multiply by twiddle factors */ + m0 = t2[0] * twR; + m1 = t2[1] * twI; + m2 = t2[1] * twR; + m3 = t2[0] * twI; + + /* R = R * Tr - I * Ti */ + *p2++ = m0 + m1; + /* I = I * Tr + R * Ti */ + *p2++ = m2 - m3; + + /* use vertical symmetry */ + /* 0.9988 - 0.0491i <==> -0.0491 - 0.9988i */ + m0 = t4[0] * twI; + m1 = t4[1] * twR; + m2 = t4[1] * twI; + m3 = t4[0] * twR; + + *pMid2++ = m0 - m1; + *pMid2++ = m2 + m3; + + twR = *tw++; + twI = *tw++; + + m0 = t2[2] * twR; + m1 = t2[3] * twI; + m2 = t2[3] * twR; + m3 = t2[2] * twI; + + *p2++ = m0 + m1; + *p2++ = m2 - m3; + + m0 = t4[2] * twI; + m1 = t4[3] * twR; + m2 = t4[3] * twI; + m3 = t4[2] * twR; + + *pMid2++ = m0 - m1; + *pMid2++ = m2 + m3; + } + + /* first col */ + riscv_radix8_butterfly_f32 (pCol1, L, (float32_t *) S->pTwiddle, 2U); + + /* second col */ + riscv_radix8_butterfly_f32 (pCol2, L, (float32_t *) S->pTwiddle, 2U); +} + +void riscv_cfft_radix8by4_f32 (riscv_cfft_instance_f32 * S, float32_t * p1) +{ + uint32_t L = S->fftLen >> 1; + float32_t * pCol1, *pCol2, *pCol3, *pCol4, *pEnd1, *pEnd2, *pEnd3, *pEnd4; + const float32_t *tw2, *tw3, *tw4; + float32_t * p2 = p1 + L; + float32_t * p3 = p2 + L; + float32_t * p4 = p3 + L; + float32_t t2[4], t3[4], t4[4], twR, twI; + float32_t p1ap3_0, p1sp3_0, p1ap3_1, p1sp3_1; + float32_t m0, m1, m2, m3; + uint32_t l, twMod2, twMod3, twMod4; + + pCol1 = p1; /* points to real values by default */ + pCol2 = p2; + pCol3 = p3; + pCol4 = p4; + pEnd1 = p2 - 1; /* points to imaginary values by default */ + pEnd2 = p3 - 1; + pEnd3 = p4 - 1; + pEnd4 = pEnd3 + L; + + tw2 = tw3 = tw4 = (float32_t *) S->pTwiddle; + + L >>= 1; + + /* do four dot Fourier transform */ + + twMod2 = 2; + twMod3 = 4; + twMod4 = 6; + + /* TOP */ + p1ap3_0 = p1[0] + p3[0]; + p1sp3_0 = p1[0] - p3[0]; + p1ap3_1 = p1[1] + p3[1]; + p1sp3_1 = p1[1] - p3[1]; + + /* col 2 */ + t2[0] = p1sp3_0 + p2[1] - p4[1]; + t2[1] = p1sp3_1 - p2[0] + p4[0]; + /* col 3 */ + t3[0] = p1ap3_0 - p2[0] - p4[0]; + t3[1] = p1ap3_1 - p2[1] - p4[1]; + /* col 4 */ + t4[0] = p1sp3_0 - p2[1] + p4[1]; + t4[1] = p1sp3_1 + p2[0] - p4[0]; + /* col 1 */ + *p1++ = p1ap3_0 + p2[0] + p4[0]; + *p1++ = p1ap3_1 + p2[1] + p4[1]; + + /* Twiddle factors are ones */ + *p2++ = t2[0]; + *p2++ = t2[1]; + *p3++ = t3[0]; + *p3++ = t3[1]; + *p4++ = t4[0]; + *p4++ = t4[1]; + + tw2 += twMod2; + tw3 += twMod3; + tw4 += twMod4; + + for (l = (L - 2) >> 1; l > 0; l-- ) + { + /* TOP */ + p1ap3_0 = p1[0] + p3[0]; + p1sp3_0 = p1[0] - p3[0]; + p1ap3_1 = p1[1] + p3[1]; + p1sp3_1 = p1[1] - p3[1]; + /* col 2 */ + t2[0] = p1sp3_0 + p2[1] - p4[1]; + t2[1] = p1sp3_1 - p2[0] + p4[0]; + /* col 3 */ + t3[0] = p1ap3_0 - p2[0] - p4[0]; + t3[1] = p1ap3_1 - p2[1] - p4[1]; + /* col 4 */ + t4[0] = p1sp3_0 - p2[1] + p4[1]; + t4[1] = p1sp3_1 + p2[0] - p4[0]; + /* col 1 - top */ + *p1++ = p1ap3_0 + p2[0] + p4[0]; + *p1++ = p1ap3_1 + p2[1] + p4[1]; + + /* BOTTOM */ + p1ap3_1 = pEnd1[-1] + pEnd3[-1]; + p1sp3_1 = pEnd1[-1] - pEnd3[-1]; + p1ap3_0 = pEnd1[ 0] + pEnd3[0]; + p1sp3_0 = pEnd1[ 0] - pEnd3[0]; + /* col 2 */ + t2[2] = pEnd2[0] - pEnd4[0] + p1sp3_1; + t2[3] = pEnd1[0] - pEnd3[0] - pEnd2[-1] + pEnd4[-1]; + /* col 3 */ + t3[2] = p1ap3_1 - pEnd2[-1] - pEnd4[-1]; + t3[3] = p1ap3_0 - pEnd2[ 0] - pEnd4[ 0]; + /* col 4 */ + t4[2] = pEnd2[ 0] - pEnd4[ 0] - p1sp3_1; + t4[3] = pEnd4[-1] - pEnd2[-1] - p1sp3_0; + /* col 1 - Bottom */ + *pEnd1-- = p1ap3_0 + pEnd2[ 0] + pEnd4[ 0]; + *pEnd1-- = p1ap3_1 + pEnd2[-1] + pEnd4[-1]; + + /* COL 2 */ + /* read twiddle factors */ + twR = *tw2++; + twI = *tw2++; + /* multiply by twiddle factors */ + /* let Z1 = a + i(b), Z2 = c + i(d) */ + /* => Z1 * Z2 = (a*c - b*d) + i(b*c + a*d) */ + + /* Top */ + m0 = t2[0] * twR; + m1 = t2[1] * twI; + m2 = t2[1] * twR; + m3 = t2[0] * twI; + + *p2++ = m0 + m1; + *p2++ = m2 - m3; + /* use vertical symmetry col 2 */ + /* 0.9997 - 0.0245i <==> 0.0245 - 0.9997i */ + /* Bottom */ + m0 = t2[3] * twI; + m1 = t2[2] * twR; + m2 = t2[2] * twI; + m3 = t2[3] * twR; + + *pEnd2-- = m0 - m1; + *pEnd2-- = m2 + m3; + + /* COL 3 */ + twR = tw3[0]; + twI = tw3[1]; + tw3 += twMod3; + /* Top */ + m0 = t3[0] * twR; + m1 = t3[1] * twI; + m2 = t3[1] * twR; + m3 = t3[0] * twI; + + *p3++ = m0 + m1; + *p3++ = m2 - m3; + /* use vertical symmetry col 3 */ + /* 0.9988 - 0.0491i <==> -0.9988 - 0.0491i */ + /* Bottom */ + m0 = -t3[3] * twR; + m1 = t3[2] * twI; + m2 = t3[2] * twR; + m3 = t3[3] * twI; + + *pEnd3-- = m0 - m1; + *pEnd3-- = m3 - m2; + + /* COL 4 */ + twR = tw4[0]; + twI = tw4[1]; + tw4 += twMod4; + /* Top */ + m0 = t4[0] * twR; + m1 = t4[1] * twI; + m2 = t4[1] * twR; + m3 = t4[0] * twI; + + *p4++ = m0 + m1; + *p4++ = m2 - m3; + /* use vertical symmetry col 4 */ + /* 0.9973 - 0.0736i <==> -0.0736 + 0.9973i */ + /* Bottom */ + m0 = t4[3] * twI; + m1 = t4[2] * twR; + m2 = t4[2] * twI; + m3 = t4[3] * twR; + + *pEnd4-- = m0 - m1; + *pEnd4-- = m2 + m3; + } + + /* MIDDLE */ + /* Twiddle factors are */ + /* 1.0000 0.7071-0.7071i -1.0000i -0.7071-0.7071i */ + p1ap3_0 = p1[0] + p3[0]; + p1sp3_0 = p1[0] - p3[0]; + p1ap3_1 = p1[1] + p3[1]; + p1sp3_1 = p1[1] - p3[1]; + + /* col 2 */ + t2[0] = p1sp3_0 + p2[1] - p4[1]; + t2[1] = p1sp3_1 - p2[0] + p4[0]; + /* col 3 */ + t3[0] = p1ap3_0 - p2[0] - p4[0]; + t3[1] = p1ap3_1 - p2[1] - p4[1]; + /* col 4 */ + t4[0] = p1sp3_0 - p2[1] + p4[1]; + t4[1] = p1sp3_1 + p2[0] - p4[0]; + /* col 1 - Top */ + *p1++ = p1ap3_0 + p2[0] + p4[0]; + *p1++ = p1ap3_1 + p2[1] + p4[1]; + + /* COL 2 */ + twR = tw2[0]; + twI = tw2[1]; + + m0 = t2[0] * twR; + m1 = t2[1] * twI; + m2 = t2[1] * twR; + m3 = t2[0] * twI; + + *p2++ = m0 + m1; + *p2++ = m2 - m3; + /* COL 3 */ + twR = tw3[0]; + twI = tw3[1]; + + m0 = t3[0] * twR; + m1 = t3[1] * twI; + m2 = t3[1] * twR; + m3 = t3[0] * twI; + + *p3++ = m0 + m1; + *p3++ = m2 - m3; + /* COL 4 */ + twR = tw4[0]; + twI = tw4[1]; + + m0 = t4[0] * twR; + m1 = t4[1] * twI; + m2 = t4[1] * twR; + m3 = t4[0] * twI; + + *p4++ = m0 + m1; + *p4++ = m2 - m3; + + /* first col */ + riscv_radix8_butterfly_f32 (pCol1, L, (float32_t *) S->pTwiddle, 4U); + + /* second col */ + riscv_radix8_butterfly_f32 (pCol2, L, (float32_t *) S->pTwiddle, 4U); + + /* third col */ + riscv_radix8_butterfly_f32 (pCol3, L, (float32_t *) S->pTwiddle, 4U); + + /* fourth col */ + riscv_radix8_butterfly_f32 (pCol4, L, (float32_t *) S->pTwiddle, 4U); +} + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Processing function for the floating-point complex FFT. + @param[in] S points to an instance of the floating-point CFFT structure + @param[in,out] p1 points to the complex data buffer of size 2*fftLen. Processing occurs in-place + @param[in] ifftFlag flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return none + */ + +void riscv_cfft_f32( + const riscv_cfft_instance_f32 * S, + float32_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + uint32_t L = S->fftLen, l; + float32_t invL, * pSrc; + + if (ifftFlag == 1U) + { + /* Conjugate input data */ + pSrc = p1 + 1; + for (l = 0; l < L; l++) + { + *pSrc = -*pSrc; + pSrc += 2; + } + } + + switch (L) + { + case 16: + case 128: + case 1024: + riscv_cfft_radix8by2_f32 ( (riscv_cfft_instance_f32 *) S, p1); + break; + case 32: + case 256: + case 2048: + riscv_cfft_radix8by4_f32 ( (riscv_cfft_instance_f32 *) S, p1); + break; + case 64: + case 512: + case 4096: + riscv_radix8_butterfly_f32 ( p1, L, (float32_t *) S->pTwiddle, 1); + break; + } + + if ( bitReverseFlag ) + riscv_bitreversal_32 ((uint32_t*) p1, S->bitRevLength, S->pBitRevTable); + + if (ifftFlag == 1U) + { + invL = 1.0f / (float32_t)L; + + /* Conjugate and scale output data */ + pSrc = p1; + for (l= 0; l < L; l++) + { + *pSrc++ *= invL ; + *pSrc = -(*pSrc) * invL; + pSrc++; + } + } +} + +/** + @} end of ComplexFFT group + */ diff --git a/components/nmsis/dsp/src/TransformFunctions/riscv_cfft_f64.c b/components/nmsis/dsp/src/TransformFunctions/riscv_cfft_f64.c new file mode 100644 index 00000000..cbdbea58 --- /dev/null +++ b/components/nmsis/dsp/src/TransformFunctions/riscv_cfft_f64.c @@ -0,0 +1,319 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_cfft_f64.c + * Description: Combined Radix Decimation in Frequency CFFT Double Precision Floating point processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" +#include "riscv_common_tables.h" + + +extern void riscv_radix4_butterfly_f64( + float64_t * pSrc, + uint16_t fftLen, + const float64_t * pCoef, + uint16_t twidCoefModifier); + +extern void riscv_bitreversal_64( + uint64_t * pSrc, + const uint16_t bitRevLen, + const uint16_t * pBitRevTable); + +/** +* @} end of ComplexFFT group +*/ + +/* ---------------------------------------------------------------------- + * Internal helper function used by the FFTs + * ---------------------------------------------------------------------- */ + +/* +* @brief Core function for the Double Precision floating-point CFFT butterfly process. +* @param[in, out] *pSrc points to the in-place buffer of F64 data type. +* @param[in] fftLen length of the FFT. +* @param[in] *pCoef points to the twiddle coefficient buffer. +* @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. +* @return none. +*/ + +void riscv_radix4_butterfly_f64( + float64_t * pSrc, + uint16_t fftLen, + const float64_t * pCoef, + uint16_t twidCoefModifier) +{ + + float64_t co1, co2, co3, si1, si2, si3; + uint32_t ia1, ia2, ia3; + uint32_t i0, i1, i2, i3; + uint32_t n1, n2, j, k; + + float64_t t1, t2, r1, r2, s1, s2; + + + /* Initializations for the fft calculation */ + n2 = fftLen; + n1 = n2; + for (k = fftLen; k > 1U; k >>= 2U) + { + /* Initializations for the fft calculation */ + n1 = n2; + n2 >>= 2U; + ia1 = 0U; + + /* FFT Calculation */ + j = 0; + do + { + /* index calculation for the coefficients */ + ia2 = ia1 + ia1; + ia3 = ia2 + ia1; + co1 = pCoef[ia1 * 2U]; + si1 = pCoef[(ia1 * 2U) + 1U]; + co2 = pCoef[ia2 * 2U]; + si2 = pCoef[(ia2 * 2U) + 1U]; + co3 = pCoef[ia3 * 2U]; + si3 = pCoef[(ia3 * 2U) + 1U]; + + /* Twiddle coefficients index modifier */ + ia1 = ia1 + twidCoefModifier; + + i0 = j; + do + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* xa + xc */ + r1 = pSrc[(2U * i0)] + pSrc[(2U * i2)]; + + /* xa - xc */ + r2 = pSrc[(2U * i0)] - pSrc[(2U * i2)]; + + /* ya + yc */ + s1 = pSrc[(2U * i0) + 1U] + pSrc[(2U * i2) + 1U]; + + /* ya - yc */ + s2 = pSrc[(2U * i0) + 1U] - pSrc[(2U * i2) + 1U]; + + /* xb + xd */ + t1 = pSrc[2U * i1] + pSrc[2U * i3]; + + /* xa' = xa + xb + xc + xd */ + pSrc[2U * i0] = r1 + t1; + + /* xa + xc -(xb + xd) */ + r1 = r1 - t1; + + /* yb + yd */ + t2 = pSrc[(2U * i1) + 1U] + pSrc[(2U * i3) + 1U]; + + /* ya' = ya + yb + yc + yd */ + pSrc[(2U * i0) + 1U] = s1 + t2; + + /* (ya + yc) - (yb + yd) */ + s1 = s1 - t2; + + /* (yb - yd) */ + t1 = pSrc[(2U * i1) + 1U] - pSrc[(2U * i3) + 1U]; + + /* (xb - xd) */ + t2 = pSrc[2U * i1] - pSrc[2U * i3]; + + /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = (r1 * co2) + (s1 * si2); + + /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = (s1 * co2) - (r1 * si2); + + /* (xa - xc) + (yb - yd) */ + r1 = r2 + t1; + + /* (xa - xc) - (yb - yd) */ + r2 = r2 - t1; + + /* (ya - yc) - (xb - xd) */ + s1 = s2 - t2; + + /* (ya - yc) + (xb - xd) */ + s2 = s2 + t2; + + /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = (r1 * co1) + (s1 * si1); + + /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = (s1 * co1) - (r1 * si1); + + /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = (r2 * co3) + (s2 * si3); + + /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = (s2 * co3) - (r2 * si3); + + i0 += n1; + } while ( i0 < fftLen); + j++; + } while (j <= (n2 - 1U)); + twidCoefModifier <<= 2U; + } +} + +/* +* @brief Core function for the Double Precision floating-point CFFT butterfly process. +* @param[in, out] *pSrc points to the in-place buffer of F64 data type. +* @param[in] fftLen length of the FFT. +* @param[in] *pCoef points to the twiddle coefficient buffer. +* @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. +* @return none. +*/ + +void riscv_cfft_radix4by2_f64( + float64_t * pSrc, + uint32_t fftLen, + const float64_t * pCoef) +{ + uint32_t i, l; + uint32_t n2, ia; + float64_t xt, yt, cosVal, sinVal; + float64_t p0, p1,p2,p3,a0,a1; + + n2 = fftLen >> 1; + ia = 0; + for (i = 0; i < n2; i++) + { + cosVal = pCoef[2*ia]; + sinVal = pCoef[2*ia + 1]; + ia++; + + l = i + n2; + + /* Butterfly implementation */ + a0 = pSrc[2 * i] + pSrc[2 * l]; + xt = pSrc[2 * i] - pSrc[2 * l]; + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1]; + + p0 = xt * cosVal; + p1 = yt * sinVal; + p2 = yt * cosVal; + p3 = xt * sinVal; + + pSrc[2 * i] = a0; + pSrc[2 * i + 1] = a1; + + pSrc[2 * l] = p0 + p1; + pSrc[2 * l + 1] = p2 - p3; + + } + + // first col + riscv_radix4_butterfly_f64( pSrc, n2, (float64_t*)pCoef, 2U); + // second col + riscv_radix4_butterfly_f64( pSrc + fftLen, n2, (float64_t*)pCoef, 2U); + +} + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Processing function for the Double Precision floating-point complex FFT. + @param[in] S points to an instance of the Double Precision floating-point CFFT structure + @param[in,out] p1 points to the complex data buffer of size 2*fftLen. Processing occurs in-place + @param[in] ifftFlag flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return none + */ + +void riscv_cfft_f64( + const riscv_cfft_instance_f64 * S, + float64_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + uint32_t L = S->fftLen, l; + float64_t invL, * pSrc; + + if (ifftFlag == 1U) + { + /* Conjugate input data */ + pSrc = p1 + 1; + for(l=0; lpTwiddle, 1U); + break; + + case 32: + case 128: + case 512: + case 2048: + riscv_cfft_radix4by2_f64 ( p1, L, (float64_t*)S->pTwiddle); + break; + + } + + if ( bitReverseFlag ) + riscv_bitreversal_64((uint64_t*)p1, S->bitRevLength,S->pBitRevTable); + + if (ifftFlag == 1U) + { + invL = 1.0 / (float64_t)L; + /* Conjugate and scale output data */ + pSrc = p1; + for(l=0; lbitRevLength = riscv_cfft_sR_##EXT##_len##SIZE.bitRevLength; \ + S->pBitRevTable = riscv_cfft_sR_##EXT##_len##SIZE.pBitRevTable; \ + S->pTwiddle = riscv_cfft_sR_##EXT##_len##SIZE.pTwiddle; + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Initialization function for the cfft f16 function + @param[in,out] S points to an instance of the floating-point CFFT structure + @param[in] fftLen fft length (number of complex samples) + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_ARGUMENT_ERROR : an error is detected + + @par Use of this function is mandatory only for the MVE version of the FFT. + Other versions can still initialize directly the data structure using + variables declared in riscv_const_structs.h + */ + +#include "dsp/transform_functions_f16.h" +#include "riscv_common_tables_f16.h" +#include "riscv_const_structs_f16.h" + + + +#if defined(RISCV_FLOAT16_SUPPORTED) + +riscv_status riscv_cfft_init_f16( + riscv_cfft_instance_f16 * S, + uint16_t fftLen) +{ + /* Initialise the default riscv status */ + riscv_status status = RISCV_MATH_SUCCESS; + + /* Initialise the FFT length */ + S->fftLen = fftLen; + + /* Initialise the Twiddle coefficient pointer */ + S->pTwiddle = NULL; + + + /* Initializations of Instance structure depending on the FFT length */ + switch (S->fftLen) { +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F16_4096) && defined(RISCV_TABLE_BITREVIDX_FLT_4096)) + /* Initializations of structure parameters for 4096 point FFT */ + case 4096U: + /* Initialise the bit reversal table modifier */ + FFTINIT(f16,4096); + break; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F16_2048) && defined(RISCV_TABLE_BITREVIDX_FLT_2048)) + /* Initializations of structure parameters for 2048 point FFT */ + case 2048U: + /* Initialise the bit reversal table modifier */ + FFTINIT(f16,2048); + + break; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F16_1024) && defined(RISCV_TABLE_BITREVIDX_FLT_1024)) + /* Initializations of structure parameters for 1024 point FFT */ + case 1024U: + /* Initialise the bit reversal table modifier */ + FFTINIT(f16,1024); + + break; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F16_512) && defined(RISCV_TABLE_BITREVIDX_FLT_512)) + /* Initializations of structure parameters for 512 point FFT */ + case 512U: + /* Initialise the bit reversal table modifier */ + FFTINIT(f16,512); + break; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F16_256) && defined(RISCV_TABLE_BITREVIDX_FLT_256)) + case 256U: + FFTINIT(f16,256); + break; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F16_128) && defined(RISCV_TABLE_BITREVIDX_FLT_128)) + case 128U: + FFTINIT(f16,128); + break; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F16_64) && defined(RISCV_TABLE_BITREVIDX_FLT_64)) + case 64U: + FFTINIT(f16,64); + break; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F16_32) && defined(RISCV_TABLE_BITREVIDX_FLT_32)) + case 32U: + FFTINIT(f16,32); + break; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F16_16) && defined(RISCV_TABLE_BITREVIDX_FLT_16)) + case 16U: + /* Initializations of structure parameters for 16 point FFT */ + FFTINIT(f16,16); + break; +#endif + + default: + /* Reporting argument error if fftSize is not valid value */ + status = RISCV_MATH_ARGUMENT_ERROR; + break; + } + + + return (status); +} +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ + +/** + @} end of ComplexFFT group + */ diff --git a/components/nmsis/dsp/src/TransformFunctions/riscv_cfft_init_f32.c b/components/nmsis/dsp/src/TransformFunctions/riscv_cfft_init_f32.c new file mode 100644 index 00000000..e7c2d433 --- /dev/null +++ b/components/nmsis/dsp/src/TransformFunctions/riscv_cfft_init_f32.c @@ -0,0 +1,150 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_cfft_init_f32.c + * Description: Initialization function for cfft f32 instance + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#define FFTINIT(EXT,SIZE) \ + S->bitRevLength = riscv_cfft_sR_##EXT##_len##SIZE.bitRevLength; \ + S->pBitRevTable = riscv_cfft_sR_##EXT##_len##SIZE.pBitRevTable; \ + S->pTwiddle = riscv_cfft_sR_##EXT##_len##SIZE.pTwiddle; + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Initialization function for the cfft f32 function + @param[in,out] S points to an instance of the floating-point CFFT structure + @param[in] fftLen fft length (number of complex samples) + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_ARGUMENT_ERROR : an error is detected + + @par Use of this function is mandatory only for the MVE version of the FFT. + Other versions can still initialize directly the data structure using + variables declared in riscv_const_structs.h + */ + +#include "dsp/transform_functions.h" +#include "riscv_common_tables.h" +#include "riscv_const_structs.h" + +riscv_status riscv_cfft_init_f32( + riscv_cfft_instance_f32 * S, + uint16_t fftLen) +{ + /* Initialise the default riscv status */ + riscv_status status = RISCV_MATH_SUCCESS; + + /* Initialise the FFT length */ + S->fftLen = fftLen; + + /* Initialise the Twiddle coefficient pointer */ + S->pTwiddle = NULL; + + + /* Initializations of Instance structure depending on the FFT length */ + switch (S->fftLen) { +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F32_4096) && defined(RISCV_TABLE_BITREVIDX_FLT_4096)) + /* Initializations of structure parameters for 4096 point FFT */ + case 4096U: + /* Initialise the bit reversal table modifier */ + FFTINIT(f32,4096); + break; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F32_2048) && defined(RISCV_TABLE_BITREVIDX_FLT_2048)) + /* Initializations of structure parameters for 2048 point FFT */ + case 2048U: + /* Initialise the bit reversal table modifier */ + FFTINIT(f32,2048); + + break; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F32_1024) && defined(RISCV_TABLE_BITREVIDX_FLT_1024)) + /* Initializations of structure parameters for 1024 point FFT */ + case 1024U: + /* Initialise the bit reversal table modifier */ + FFTINIT(f32,1024); + + break; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F32_512) && defined(RISCV_TABLE_BITREVIDX_FLT_512)) + /* Initializations of structure parameters for 512 point FFT */ + case 512U: + /* Initialise the bit reversal table modifier */ + FFTINIT(f32,512); + break; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F32_256) && defined(RISCV_TABLE_BITREVIDX_FLT_256)) + case 256U: + FFTINIT(f32,256); + break; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F32_128) && defined(RISCV_TABLE_BITREVIDX_FLT_128)) + case 128U: + FFTINIT(f32,128); + break; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F32_64) && defined(RISCV_TABLE_BITREVIDX_FLT_64)) + case 64U: + FFTINIT(f32,64); + break; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F32_32) && defined(RISCV_TABLE_BITREVIDX_FLT_32)) + case 32U: + FFTINIT(f32,32); + break; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F32_16) && defined(RISCV_TABLE_BITREVIDX_FLT_16)) + case 16U: + /* Initializations of structure parameters for 16 point FFT */ + FFTINIT(f32,16); + break; +#endif + + default: + /* Reporting argument error if fftSize is not valid value */ + status = RISCV_MATH_ARGUMENT_ERROR; + break; + } + + + return (status); +} + +/** + @} end of ComplexFFT group + */ diff --git a/components/nmsis/dsp/src/TransformFunctions/riscv_cfft_init_f64.c b/components/nmsis/dsp/src/TransformFunctions/riscv_cfft_init_f64.c new file mode 100644 index 00000000..edf7a11d --- /dev/null +++ b/components/nmsis/dsp/src/TransformFunctions/riscv_cfft_init_f64.c @@ -0,0 +1,151 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_cfft_init_f64.c + * Description: Initialization function for cfft f64 instance + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#define FFTINIT(EXT,SIZE) \ + S->bitRevLength = riscv_cfft_sR_##EXT##_len##SIZE.bitRevLength; \ + S->pBitRevTable = riscv_cfft_sR_##EXT##_len##SIZE.pBitRevTable; \ + S->pTwiddle = riscv_cfft_sR_##EXT##_len##SIZE.pTwiddle; + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Initialization function for the cfft f64 function + @param[in,out] S points to an instance of the floating-point CFFT structure + @param[in] fftLen fft length (number of complex samples) + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_ARGUMENT_ERROR : an error is detected + + @par Use of this function is mandatory only for the MVE version of the FFT. + Other versions can still initialize directly the data structure using + variables declared in riscv_const_structs.h + */ + +#include "dsp/transform_functions.h" +#include "riscv_common_tables.h" +#include "riscv_const_structs.h" + + +riscv_status riscv_cfft_init_f64( + riscv_cfft_instance_f64 * S, + uint16_t fftLen) +{ + /* Initialise the default riscv status */ + riscv_status status = RISCV_MATH_SUCCESS; + + /* Initialise the FFT length */ + S->fftLen = fftLen; + + /* Initialise the Twiddle coefficient pointer */ + S->pTwiddle = NULL; + + + /* Initializations of Instance structure depending on the FFT length */ + switch (S->fftLen) { +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_f64_4096) && defined(RISCV_TABLE_BITREVIDX_FLT_4096)) + /* Initializations of structure parameters for 4096 point FFT */ + case 4096U: + /* Initialise the bit reversal table modifier */ + FFTINIT(f64,4096); + break; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_f64_2048) && defined(RISCV_TABLE_BITREVIDX_FLT_2048)) + /* Initializations of structure parameters for 2048 point FFT */ + case 2048U: + /* Initialise the bit reversal table modifier */ + FFTINIT(f64,2048); + + break; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_f64_1024) && defined(RISCV_TABLE_BITREVIDX_FLT_1024)) + /* Initializations of structure parameters for 1024 point FFT */ + case 1024U: + /* Initialise the bit reversal table modifier */ + FFTINIT(f64,1024); + + break; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_f64_512) && defined(RISCV_TABLE_BITREVIDX_FLT_512)) + /* Initializations of structure parameters for 512 point FFT */ + case 512U: + /* Initialise the bit reversal table modifier */ + FFTINIT(f64,512); + break; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_f64_256) && defined(RISCV_TABLE_BITREVIDX_FLT_256)) + case 256U: + FFTINIT(f64,256); + break; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_f64_128) && defined(RISCV_TABLE_BITREVIDX_FLT_128)) + case 128U: + FFTINIT(f64,128); + break; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_f64_64) && defined(RISCV_TABLE_BITREVIDX_FLT_64)) + case 64U: + FFTINIT(f64,64); + break; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_f64_32) && defined(RISCV_TABLE_BITREVIDX_FLT_32)) + case 32U: + FFTINIT(f64,32); + break; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_f64_16) && defined(RISCV_TABLE_BITREVIDX_FLT_16)) + case 16U: + /* Initializations of structure parameters for 16 point FFT */ + FFTINIT(f64,16); + break; +#endif + + default: + /* Reporting argument error if fftSize is not valid value */ + status = RISCV_MATH_ARGUMENT_ERROR; + break; + } + + + return (status); +} + +/** + @} end of ComplexFFT group + */ diff --git a/components/nmsis/dsp/src/TransformFunctions/riscv_cfft_init_q15.c b/components/nmsis/dsp/src/TransformFunctions/riscv_cfft_init_q15.c new file mode 100644 index 00000000..740c4ba2 --- /dev/null +++ b/components/nmsis/dsp/src/TransformFunctions/riscv_cfft_init_q15.c @@ -0,0 +1,150 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_cfft_init_q15.c + * Description: Initialization function for cfft q15 instance + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#define FFTINIT(EXT,SIZE) \ + S->bitRevLength = riscv_cfft_sR_##EXT##_len##SIZE.bitRevLength; \ + S->pBitRevTable = riscv_cfft_sR_##EXT##_len##SIZE.pBitRevTable; \ + S->pTwiddle = riscv_cfft_sR_##EXT##_len##SIZE.pTwiddle; + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Initialization function for the cfft q15 function + @param[in,out] S points to an instance of the floating-point CFFT structure + @param[in] fftLen fft length (number of complex samples) + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_ARGUMENT_ERROR : an error is detected + + @par Use of this function is mandatory only for the MVE version of the FFT. + Other versions can still initialize directly the data structure using + variables declared in riscv_const_structs.h + */ + +#include "dsp/transform_functions.h" +#include "riscv_common_tables.h" +#include "riscv_const_structs.h" + +riscv_status riscv_cfft_init_q15( + riscv_cfft_instance_q15 * S, + uint16_t fftLen) +{ + /* Initialise the default riscv status */ + riscv_status status = RISCV_MATH_SUCCESS; + + /* Initialise the FFT length */ + S->fftLen = fftLen; + + /* Initialise the Twiddle coefficient pointer */ + S->pTwiddle = NULL; + + + /* Initializations of Instance structure depending on the FFT length */ + switch (S->fftLen) { +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_Q15_4096) && defined(RISCV_TABLE_BITREVIDX_FXT_4096)) + /* Initializations of structure parameters for 4096 point FFT */ + case 4096U: + /* Initialise the bit reversal table modifier */ + FFTINIT(q15,4096); + break; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_Q15_2048) && defined(RISCV_TABLE_BITREVIDX_FXT_2048)) + /* Initializations of structure parameters for 2048 point FFT */ + case 2048U: + /* Initialise the bit reversal table modifier */ + FFTINIT(q15,2048); + + break; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_Q15_1024) && defined(RISCV_TABLE_BITREVIDX_FXT_1024)) + /* Initializations of structure parameters for 1024 point FFT */ + case 1024U: + /* Initialise the bit reversal table modifier */ + FFTINIT(q15,1024); + + break; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_Q15_512) && defined(RISCV_TABLE_BITREVIDX_FXT_512)) + /* Initializations of structure parameters for 512 point FFT */ + case 512U: + /* Initialise the bit reversal table modifier */ + FFTINIT(q15,512); + break; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_Q15_256) && defined(RISCV_TABLE_BITREVIDX_FXT_256)) + case 256U: + FFTINIT(q15,256); + break; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_Q15_128) && defined(RISCV_TABLE_BITREVIDX_FXT_128)) + case 128U: + FFTINIT(q15,128); + break; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_Q15_64) && defined(RISCV_TABLE_BITREVIDX_FXT_64)) + case 64U: + FFTINIT(q15,64); + break; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_Q15_32) && defined(RISCV_TABLE_BITREVIDX_FXT_32)) + case 32U: + FFTINIT(q15,32); + break; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_Q15_16) && defined(RISCV_TABLE_BITREVIDX_FXT_16)) + case 16U: + /* Initializations of structure parameters for 16 point FFT */ + FFTINIT(q15,16); + break; +#endif + + default: + /* Reporting argument error if fftSize is not valid value */ + status = RISCV_MATH_ARGUMENT_ERROR; + break; + } + + + return (status); +} + +/** + @} end of ComplexFFT group + */ diff --git a/components/nmsis/dsp/src/TransformFunctions/riscv_cfft_init_q31.c b/components/nmsis/dsp/src/TransformFunctions/riscv_cfft_init_q31.c new file mode 100644 index 00000000..c6bb3905 --- /dev/null +++ b/components/nmsis/dsp/src/TransformFunctions/riscv_cfft_init_q31.c @@ -0,0 +1,150 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_cfft_init_q31.c + * Description: Initialization function for cfft q31 instance + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#define FFTINIT(EXT,SIZE) \ + S->bitRevLength = riscv_cfft_sR_##EXT##_len##SIZE.bitRevLength; \ + S->pBitRevTable = riscv_cfft_sR_##EXT##_len##SIZE.pBitRevTable; \ + S->pTwiddle = riscv_cfft_sR_##EXT##_len##SIZE.pTwiddle; + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Initialization function for the cfft q31 function + @param[in,out] S points to an instance of the floating-point CFFT structure + @param[in] fftLen fft length (number of complex samples) + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_ARGUMENT_ERROR : an error is detected + + @par Use of this function is mandatory only for the MVE version of the FFT. + Other versions can still initialize directly the data structure using + variables declared in riscv_const_structs.h + */ + +#include "dsp/transform_functions.h" +#include "riscv_common_tables.h" +#include "riscv_const_structs.h" + +riscv_status riscv_cfft_init_q31( + riscv_cfft_instance_q31 * S, + uint16_t fftLen) +{ + /* Initialise the default riscv status */ + riscv_status status = RISCV_MATH_SUCCESS; + + /* Initialise the FFT length */ + S->fftLen = fftLen; + + /* Initialise the Twiddle coefficient pointer */ + S->pTwiddle = NULL; + + + /* Initializations of Instance structure depending on the FFT length */ + switch (S->fftLen) { +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_Q31_4096) && defined(RISCV_TABLE_BITREVIDX_FXT_4096)) + /* Initializations of structure parameters for 4096 point FFT */ + case 4096U: + /* Initialise the bit reversal table modifier */ + FFTINIT(q31,4096); + break; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_Q31_2048) && defined(RISCV_TABLE_BITREVIDX_FXT_2048)) + /* Initializations of structure parameters for 2048 point FFT */ + case 2048U: + /* Initialise the bit reversal table modifier */ + FFTINIT(q31,2048); + + break; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_Q31_1024) && defined(RISCV_TABLE_BITREVIDX_FXT_1024)) + /* Initializations of structure parameters for 1024 point FFT */ + case 1024U: + /* Initialise the bit reversal table modifier */ + FFTINIT(q31,1024); + + break; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_Q31_512) && defined(RISCV_TABLE_BITREVIDX_FXT_512)) + /* Initializations of structure parameters for 512 point FFT */ + case 512U: + /* Initialise the bit reversal table modifier */ + FFTINIT(q31,512); + break; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_Q31_256) && defined(RISCV_TABLE_BITREVIDX_FXT_256)) + case 256U: + FFTINIT(q31,256); + break; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_Q31_128) && defined(RISCV_TABLE_BITREVIDX_FXT_128)) + case 128U: + FFTINIT(q31,128); + break; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_Q31_64) && defined(RISCV_TABLE_BITREVIDX_FXT_64)) + case 64U: + FFTINIT(q31,64); + break; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_Q31_32) && defined(RISCV_TABLE_BITREVIDX_FXT_32)) + case 32U: + FFTINIT(q31,32); + break; +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_Q31_16) && defined(RISCV_TABLE_BITREVIDX_FXT_16)) + case 16U: + /* Initializations of structure parameters for 16 point FFT */ + FFTINIT(q31,16); + break; +#endif + + default: + /* Reporting argument error if fftSize is not valid value */ + status = RISCV_MATH_ARGUMENT_ERROR; + break; + } + + + return (status); +} + +/** + @} end of ComplexFFT group + */ diff --git a/components/nmsis/dsp/src/TransformFunctions/riscv_cfft_q15.c b/components/nmsis/dsp/src/TransformFunctions/riscv_cfft_q15.c new file mode 100644 index 00000000..c474f23b --- /dev/null +++ b/components/nmsis/dsp/src/TransformFunctions/riscv_cfft_q15.c @@ -0,0 +1,405 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_cfft_q15.c + * Description: Combined Radix Decimation in Q15 Frequency CFFT processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" + + +extern void riscv_radix4_butterfly_q15( + q15_t * pSrc, + uint32_t fftLen, + const q15_t * pCoef, + uint32_t twidCoefModifier); + +extern void riscv_radix4_butterfly_inverse_q15( + q15_t * pSrc, + uint32_t fftLen, + const q15_t * pCoef, + uint32_t twidCoefModifier); + +extern void riscv_bitreversal_16( + uint16_t * pSrc, + const uint16_t bitRevLen, + const uint16_t * pBitRevTable); + +void riscv_cfft_radix4by2_q15( + q15_t * pSrc, + uint32_t fftLen, + const q15_t * pCoef); + +void riscv_cfft_radix4by2_inverse_q15( + q15_t * pSrc, + uint32_t fftLen, + const q15_t * pCoef); + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Processing function for Q15 complex FFT. + @param[in] S points to an instance of Q15 CFFT structure + @param[in,out] p1 points to the complex data buffer of size 2*fftLen. Processing occurs in-place + @param[in] ifftFlag flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return none + */ + +void riscv_cfft_q15( + const riscv_cfft_instance_q15 * S, + q15_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + uint32_t L = S->fftLen; + + if (ifftFlag == 1U) + { + switch (L) + { + case 16: + case 64: + case 256: + case 1024: + case 4096: + riscv_radix4_butterfly_inverse_q15 ( p1, L, (q15_t*)S->pTwiddle, 1 ); + break; + + case 32: + case 128: + case 512: + case 2048: + riscv_cfft_radix4by2_inverse_q15 ( p1, L, S->pTwiddle ); + break; + } + } + else + { + switch (L) + { + case 16: + case 64: + case 256: + case 1024: + case 4096: + riscv_radix4_butterfly_q15 ( p1, L, (q15_t*)S->pTwiddle, 1 ); + break; + + case 32: + case 128: + case 512: + case 2048: + riscv_cfft_radix4by2_q15 ( p1, L, S->pTwiddle ); + break; + } + } + + if ( bitReverseFlag ) + riscv_bitreversal_16 ((uint16_t*) p1, S->bitRevLength, S->pBitRevTable); +} + +/** + @} end of ComplexFFT group + */ + +void riscv_cfft_radix4by2_q15( + q15_t * pSrc, + uint32_t fftLen, + const q15_t * pCoef) +{ + uint32_t i; + uint32_t n2; + q15_t p0, p1, p2, p3; +#if defined (RISCV_MATH_DSP) + q31_t T, S, R; + q31_t coeff, out1, out2; + const q15_t *pC = pCoef; + q15_t *pSi = pSrc; + q15_t *pSl = pSrc + fftLen; +#if __RISCV_XLEN == 64 + q15_t xt, yt, cosVal, sinVal; + uint32_t n264; + q63_t T64, S64, R64; + q63_t coeff64, out164, out264; + uint32_t l; +#endif /* __RISCV_XLEN == 64 */ +#else + uint32_t l; + q15_t xt, yt, cosVal, sinVal; +#endif + + n2 = fftLen >> 1U; + +#if defined (RISCV_MATH_DSP) +#if __RISCV_XLEN == 64 + n264 = n2 >> 1U; + for (i = n264; i > 0; i--) + { + coeff64 = read_q15x4_ia ((q15_t **) &pC); + + T64 = read_q15x4 (pSi); + T64 = __RV_RADD16(T64, 0); /* this is just a SIMD arithmetic shift right by 1 */ + + S64 = read_q15x4 (pSl); + S64 = __RV_RADD16(S64, 0); /* this is just a SIMD arithmetic shift right by 1 */ + + R64 = __RV_KSUB16(T64, S64); + + write_q15x4_ia (&pSi, __RV_RADD16(T64, S64)); + + out164 = __RV_KMDA(coeff64, R64) >> 16U; + out264 = __RV_SMXDS(R64, coeff64); + + write_q15x4_ia (&pSl, (q63_t) (((out264) & 0xFFFF0000FFFF0000) | (out164 & 0x0000FFFF0000FFFF))); + } + +#else + for (i = n2; i > 0; i--) + { + coeff = read_q15x2_ia ((q15_t **) &pC); + + T = read_q15x2 (pSi); + T = __RV_RADD16(T, 0); /* this is just a SIMD arithmetic shift right by 1 */ + + S = read_q15x2 (pSl); + S = __RV_RADD16(S, 0); /* this is just a SIMD arithmetic shift right by 1 */ + + R = __RV_KSUB16(T, S); + + write_q15x2_ia (&pSi, __RV_RADD16(T, S)); + + out1 = __RV_KMDA(coeff, R) >> 16U; + out2 = __RV_SMXDS(R, coeff); + + write_q15x2_ia (&pSl, (q31_t)__PKHBT( out1, out2, 0 ) ); + } +#endif /* __RISCV_XLEN == 64 */ + +#else /* #if defined (RISCV_MATH_DSP) */ + + for (i = 0; i < n2; i++) + { + cosVal = pCoef[2 * i]; + sinVal = pCoef[2 * i + 1]; + + l = i + n2; + + xt = (pSrc[2 * i] >> 1U) - (pSrc[2 * l] >> 1U); + pSrc[2 * i] = ((pSrc[2 * i] >> 1U) + (pSrc[2 * l] >> 1U)) >> 1U; + + yt = (pSrc[2 * i + 1] >> 1U) - (pSrc[2 * l + 1] >> 1U); + pSrc[2 * i + 1] = ((pSrc[2 * l + 1] >> 1U) + (pSrc[2 * i + 1] >> 1U)) >> 1U; + + pSrc[2 * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16U)) + + ((int16_t) (((q31_t) yt * sinVal) >> 16U)) ); + + pSrc[2 * l + 1] = (((int16_t) (((q31_t) yt * cosVal) >> 16U)) - + ((int16_t) (((q31_t) xt * sinVal) >> 16U)) ); + } + +#endif /* #if defined (RISCV_MATH_DSP) */ + + /* first col */ + riscv_radix4_butterfly_q15( pSrc, n2, (q15_t*)pCoef, 2U); + + /* second col */ + riscv_radix4_butterfly_q15( pSrc + fftLen, n2, (q15_t*)pCoef, 2U); + + n2 = fftLen >> 1U; + for (i = 0; i < n2; i++) + { + p0 = pSrc[4 * i + 0]; + p1 = pSrc[4 * i + 1]; + p2 = pSrc[4 * i + 2]; + p3 = pSrc[4 * i + 3]; + + p0 <<= 1U; + p1 <<= 1U; + p2 <<= 1U; + p3 <<= 1U; + + pSrc[4 * i + 0] = p0; + pSrc[4 * i + 1] = p1; + pSrc[4 * i + 2] = p2; + pSrc[4 * i + 3] = p3; + } + +} + +void riscv_cfft_radix4by2_inverse_q15( + q15_t * pSrc, + uint32_t fftLen, + const q15_t * pCoef) +{ + uint32_t i; + uint32_t n2; + q15_t p0, p1, p2, p3; +#if defined (RISCV_MATH_DSP) + q31_t T, S, R; + q31_t coeff, out1, out2; + const q15_t *pC = pCoef; + q15_t *pSi = pSrc; + q15_t *pSl = pSrc + fftLen; +#if __RISCV_XLEN == 64 + q15_t xt, yt, cosVal, sinVal; + uint32_t n264; + q63_t T64, S64, R64; + q63_t coeff64, out164, out264; + uint32_t l; +#endif /* __RISCV_XLEN == 64 */ +#else + uint32_t l; + q15_t xt, yt, cosVal, sinVal; +#endif + + n2 = fftLen >> 1U; + +#if defined (RISCV_MATH_DSP) +#if __RISCV_XLEN == 64 + n264 = n2 >> 1U; + for (i = n264; i > 0; i--) + { + coeff64 = read_q15x4_ia ((q15_t **) &pC); + + T64 = read_q15x4 (pSi); + T64 = __RV_RADD16(T64, 0); /* this is just a SIMD arithmetic shift right by 1 */ + + S64 = read_q15x4 (pSl); + S64 = __RV_RADD16(S64, 0); /* this is just a SIMD arithmetic shift right by 1 */ + + R64 = __RV_KSUB16(T64, S64); + + write_q15x4_ia (&pSi, __RV_RADD16(T64, S64)); + + out1 = __SMUAD(coeff, R) >> 16U; + out2 = __SMUSDX(coeff, R); + + write_q15x4_ia (&pSl, (q63_t) ((out264) & 0xFFFF0000FFFF0000) | (out164 & 0x0000FFFF0000FFFF)); + } + n264 = n2 % 2; + if (1 == n264) + { + coeff = read_q15x2_ia ((q15_t **) &pC); + + T = read_q15x2 (pSi); + T = __RV_RADD16(T, 0); /* this is just a SIMD arithmetic shift right by 1 */ + + S = read_q15x2 (pSl); + S = __RV_RADD16(S, 0); /* this is just a SIMD arithmetic shift right by 1 */ + + R = __RV_KSUB16(T, S); + + write_q15x2_ia (&pSi, __RV_RADD16(T, S)); + + out1 = __SMUAD(coeff, R) >> 16U; + out2 = __SMUSDX(coeff, R); + + write_q15x2_ia (&pSl, (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF)); + } + +#else + + for (i = n2; i > 0; i--) + { + coeff = read_q15x2_ia ((q15_t **) &pC); + + T = read_q15x2 (pSi); + T = __RV_RADD16(T, 0); /* this is just a SIMD arithmetic shift right by 1 */ + + S = read_q15x2 (pSl); + S = __RV_RADD16(S, 0); /* this is just a SIMD arithmetic shift right by 1 */ + + R = __RV_KSUB16(T, S); + + write_q15x2_ia (&pSi, __RV_RADD16(T, S)); + + out1 = __SMUSD(coeff, R) >> 16U; + out2 = __SMUADX(coeff, R); + + write_q15x2_ia (&pSl, (q31_t)__PKHBT( out1, out2, 0 )); + } +#endif +#else /* #if defined (RISCV_MATH_DSP) */ + + for (i = 0; i < n2; i++) + { + cosVal = pCoef[2 * i]; + sinVal = pCoef[2 * i + 1]; + + l = i + n2; + + xt = (pSrc[2 * i] >> 1U) - (pSrc[2 * l] >> 1U); + pSrc[2 * i] = ((pSrc[2 * i] >> 1U) + (pSrc[2 * l] >> 1U)) >> 1U; + + yt = (pSrc[2 * i + 1] >> 1U) - (pSrc[2 * l + 1] >> 1U); + pSrc[2 * i + 1] = ((pSrc[2 * l + 1] >> 1U) + (pSrc[2 * i + 1] >> 1U)) >> 1U; + + pSrc[2 * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16U)) - + ((int16_t) (((q31_t) yt * sinVal) >> 16U)) ); + + pSrc[2 * l + 1] = (((int16_t) (((q31_t) yt * cosVal) >> 16U)) + + ((int16_t) (((q31_t) xt * sinVal) >> 16U)) ); + } + +#endif /* #if defined (RISCV_MATH_DSP) */ + + /* first col */ + riscv_radix4_butterfly_inverse_q15( pSrc, n2, (q15_t*)pCoef, 2U); + + /* second col */ + riscv_radix4_butterfly_inverse_q15( pSrc + fftLen, n2, (q15_t*)pCoef, 2U); + + n2 = fftLen >> 1U; + for (i = 0; i < n2; i++) + { + p0 = pSrc[4 * i + 0]; + p1 = pSrc[4 * i + 1]; + p2 = pSrc[4 * i + 2]; + p3 = pSrc[4 * i + 3]; + + p0 <<= 1U; + p1 <<= 1U; + p2 <<= 1U; + p3 <<= 1U; + + pSrc[4 * i + 0] = p0; + pSrc[4 * i + 1] = p1; + pSrc[4 * i + 2] = p2; + pSrc[4 * i + 3] = p3; + } +} + diff --git a/components/nmsis/dsp/src/TransformFunctions/riscv_cfft_q31.c b/components/nmsis/dsp/src/TransformFunctions/riscv_cfft_q31.c new file mode 100644 index 00000000..9213774e --- /dev/null +++ b/components/nmsis/dsp/src/TransformFunctions/riscv_cfft_q31.c @@ -0,0 +1,267 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_cfft_q31.c + * Description: Combined Radix Decimation in Frequency CFFT fixed point processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" + + + + +extern void riscv_radix4_butterfly_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pCoef, + uint32_t twidCoefModifier); + +extern void riscv_radix4_butterfly_inverse_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pCoef, + uint32_t twidCoefModifier); + +extern void riscv_bitreversal_32( + uint32_t * pSrc, + const uint16_t bitRevLen, + const uint16_t * pBitRevTable); + +void riscv_cfft_radix4by2_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pCoef); + +void riscv_cfft_radix4by2_inverse_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pCoef); + + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Processing function for the Q31 complex FFT. + @param[in] S points to an instance of the fixed-point CFFT structure + @param[in,out] p1 points to the complex data buffer of size 2*fftLen. Processing occurs in-place + @param[in] ifftFlag flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return none + */ +void riscv_cfft_q31( + const riscv_cfft_instance_q31 * S, + q31_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + uint32_t L = S->fftLen; + + if (ifftFlag == 1U) + { + switch (L) + { + case 16: + case 64: + case 256: + case 1024: + case 4096: + riscv_radix4_butterfly_inverse_q31 ( p1, L, (q31_t*)S->pTwiddle, 1 ); + break; + + case 32: + case 128: + case 512: + case 2048: + riscv_cfft_radix4by2_inverse_q31 ( p1, L, S->pTwiddle ); + break; + } + } + else + { + switch (L) + { + case 16: + case 64: + case 256: + case 1024: + case 4096: + riscv_radix4_butterfly_q31 ( p1, L, (q31_t*)S->pTwiddle, 1 ); + break; + + case 32: + case 128: + case 512: + case 2048: + riscv_cfft_radix4by2_q31 ( p1, L, S->pTwiddle ); + break; + } + } + + if ( bitReverseFlag ) + riscv_bitreversal_32 ((uint32_t*) p1, S->bitRevLength, S->pBitRevTable); +} + +/** + @} end of ComplexFFT group + */ + +void riscv_cfft_radix4by2_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pCoef) +{ + uint32_t i, l; + uint32_t n2; + q31_t xt, yt, cosVal, sinVal; + q31_t p0, p1; + + n2 = fftLen >> 1U; + for (i = 0; i < n2; i++) + { + cosVal = pCoef[2 * i]; + sinVal = pCoef[2 * i + 1]; + + l = i + n2; + + xt = (pSrc[2 * i] >> 2U) - (pSrc[2 * l] >> 2U); + yt = (pSrc[2 * i + 1] >> 2U) - (pSrc[2 * l + 1] >> 2U); +#if defined RISCV_MATH_DSP && (__RISCV_XLEN == 64) + + write_q31x2 ((pSrc+2*i), (q63_t) ((q63_t)((pSrc[2 * i] >> 2U) + (pSrc[2 * l] >> 2U)) | (((q63_t)((pSrc[2 * l + 1] >> 2U) + (pSrc[2 * i + 1] >> 2U))) << 32))); +#else + pSrc[2 * i] = (pSrc[2 * i] >> 2U) + (pSrc[2 * l] >> 2U); + pSrc[2 * i + 1] = (pSrc[2 * l + 1] >> 2U) + (pSrc[2 * i + 1] >> 2U); +#endif /* __RISCV_XLEN == 64 */ + + mult_32x32_keep32_R(p0, xt, cosVal); + mult_32x32_keep32_R(p1, yt, cosVal); + multAcc_32x32_keep32_R(p0, yt, sinVal); + multSub_32x32_keep32_R(p1, xt, sinVal); + + pSrc[2 * l] = p0 << 1; + pSrc[2 * l + 1] = p1 << 1; + } + + + /* first col */ + riscv_radix4_butterfly_q31 (pSrc, n2, (q31_t*)pCoef, 2U); + + /* second col */ + riscv_radix4_butterfly_q31 (pSrc + fftLen, n2, (q31_t*)pCoef, 2U); + + n2 = fftLen >> 1U; + for (i = 0; i < n2; i++) + { + p0 = pSrc[4 * i + 0]; + p1 = pSrc[4 * i + 1]; + xt = pSrc[4 * i + 2]; + yt = pSrc[4 * i + 3]; + + p0 <<= 1U; + p1 <<= 1U; + xt <<= 1U; + yt <<= 1U; + + pSrc[4 * i + 0] = p0; + pSrc[4 * i + 1] = p1; + pSrc[4 * i + 2] = xt; + pSrc[4 * i + 3] = yt; + } + +} + +void riscv_cfft_radix4by2_inverse_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pCoef) +{ + uint32_t i, l; + uint32_t n2; + q31_t xt, yt, cosVal, sinVal; + q31_t p0, p1; + + n2 = fftLen >> 1U; + for (i = 0; i < n2; i++) + { + cosVal = pCoef[2 * i]; + sinVal = pCoef[2 * i + 1]; + + l = i + n2; + + xt = (pSrc[2 * i] >> 2U) - (pSrc[2 * l] >> 2U); + yt = (pSrc[2 * i + 1] >> 2U) - (pSrc[2 * l + 1] >> 2U); +#if defined RISCV_MATH_DSP && (__RISCV_XLEN == 64) + + write_q31x2 ((pSrc+2*i), (q63_t) ((q63_t)((pSrc[2 * i] >> 2U) + (pSrc[2 * l] >> 2U)) | (((q63_t)((pSrc[2 * l + 1] >> 2U) + (pSrc[2 * i + 1] >> 2U))) << 32))); +#else + pSrc[2 * i] = (pSrc[2 * i] >> 2U) + (pSrc[2 * l] >> 2U); + pSrc[2 * i + 1] = (pSrc[2 * l + 1] >> 2U) + (pSrc[2 * i + 1] >> 2U); +#endif /* __RISCV_XLEN == 64 */ + + mult_32x32_keep32_R(p0, xt, cosVal); + mult_32x32_keep32_R(p1, yt, cosVal); + multSub_32x32_keep32_R(p0, yt, sinVal); + multAcc_32x32_keep32_R(p1, xt, sinVal); + + pSrc[2 * l] = p0 << 1U; + pSrc[2 * l + 1] = p1 << 1U; + } + + /* first col */ + riscv_radix4_butterfly_inverse_q31( pSrc, n2, (q31_t*)pCoef, 2U); + + /* second col */ + riscv_radix4_butterfly_inverse_q31( pSrc + fftLen, n2, (q31_t*)pCoef, 2U); + + n2 = fftLen >> 1U; + for (i = 0; i < n2; i++) + { + p0 = pSrc[4 * i + 0]; + p1 = pSrc[4 * i + 1]; + xt = pSrc[4 * i + 2]; + yt = pSrc[4 * i + 3]; + + p0 <<= 1U; + p1 <<= 1U; + xt <<= 1U; + yt <<= 1U; + + pSrc[4 * i + 0] = p0; + pSrc[4 * i + 1] = p1; + pSrc[4 * i + 2] = xt; + pSrc[4 * i + 3] = yt; + } +} diff --git a/components/nmsis/dsp/src/TransformFunctions/riscv_cfft_radix2_f16.c b/components/nmsis/dsp/src/TransformFunctions/riscv_cfft_radix2_f16.c new file mode 100644 index 00000000..7b2978fc --- /dev/null +++ b/components/nmsis/dsp/src/TransformFunctions/riscv_cfft_radix2_f16.c @@ -0,0 +1,476 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_cfft_radix2_f16.c + * Description: Radix-2 Decimation in Frequency CFFT & CIFFT Floating point processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions_f16.h" + +#if defined(RISCV_FLOAT16_SUPPORTED) + +void riscv_radix2_butterfly_f16( + float16_t * pSrc, + uint32_t fftLen, + const float16_t * pCoef, + uint16_t twidCoefModifier); + +void riscv_radix2_butterfly_inverse_f16( + float16_t * pSrc, + uint32_t fftLen, + const float16_t * pCoef, + uint16_t twidCoefModifier, + float16_t onebyfftLen); + +extern void riscv_bitreversal_f16( + float16_t * pSrc, + uint16_t fftSize, + uint16_t bitRevFactor, + const uint16_t * pBitRevTab); + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Radix-2 CFFT/CIFFT. + @deprecated Do not use this function. It has been superseded by \ref riscv_cfft_f16 and will be removed in the future + @param[in] S points to an instance of the floating-point Radix-2 CFFT/CIFFT structure + @param[in,out] pSrc points to the complex data buffer of size 2*fftLen. Processing occurs in-place + @return none + */ + +void riscv_cfft_radix2_f16( +const riscv_cfft_radix2_instance_f16 * S, + float16_t * pSrc) +{ + + if (S->ifftFlag == 1U) + { + /* Complex IFFT radix-2 */ + riscv_radix2_butterfly_inverse_f16(pSrc, S->fftLen, S->pTwiddle, + S->twidCoefModifier, S->onebyfftLen); + } + else + { + /* Complex FFT radix-2 */ + riscv_radix2_butterfly_f16(pSrc, S->fftLen, S->pTwiddle, + S->twidCoefModifier); + } + + if (S->bitReverseFlag == 1U) + { + /* Bit Reversal */ + riscv_bitreversal_f16(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable); + } + +} + + +/** + @} end of ComplexFFT group + */ + + + +/* ---------------------------------------------------------------------- +** Internal helper function used by the FFTs +** ------------------------------------------------------------------- */ + +/* +* @brief Core function for the floating-point CFFT butterfly process. +* @param[in, out] *pSrc points to the in-place buffer of floating-point data type. +* @param[in] fftLen length of the FFT. +* @param[in] *pCoef points to the twiddle coefficient buffer. +* @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. +* @return none. +*/ + +void riscv_radix2_butterfly_f16( +float16_t * pSrc, +uint32_t fftLen, +const float16_t * pCoef, +uint16_t twidCoefModifier) +{ + + uint32_t i, j, k, l; + uint32_t n1, n2, ia; + float16_t xt, yt, cosVal, sinVal; + float16_t p0, p1, p2, p3; + float16_t a0, a1; + +#if defined (RISCV_MATH_DSP) + + /* Initializations for the first stage */ + n2 = fftLen >> 1; + ia = 0; + i = 0; + + // loop for groups + for (k = n2; k > 0; k--) + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + + /* Twiddle coefficients index modifier */ + ia += twidCoefModifier; + + /* index calculation for the input as, */ + /* pSrc[i + 0], pSrc[i + fftLen/1] */ + l = i + n2; + + /* Butterfly implementation */ + a0 = pSrc[2 * i] + pSrc[2 * l]; + xt = pSrc[2 * i] - pSrc[2 * l]; + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1]; + + p0 = xt * cosVal; + p1 = yt * sinVal; + p2 = yt * cosVal; + p3 = xt * sinVal; + + pSrc[2 * i] = a0; + pSrc[2 * i + 1] = a1; + + pSrc[2 * l] = p0 + p1; + pSrc[2 * l + 1] = p2 - p3; + + i++; + } // groups loop end + + twidCoefModifier <<= 1U; + + // loop for stage + for (k = n2; k > 2; k = k >> 1) + { + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + // loop for groups + j = 0; + do + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + ia += twidCoefModifier; + + // loop for butterfly + i = j; + do + { + l = i + n2; + a0 = pSrc[2 * i] + pSrc[2 * l]; + xt = pSrc[2 * i] - pSrc[2 * l]; + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1]; + + p0 = xt * cosVal; + p1 = yt * sinVal; + p2 = yt * cosVal; + p3 = xt * sinVal; + + pSrc[2 * i] = a0; + pSrc[2 * i + 1] = a1; + + pSrc[2 * l] = p0 + p1; + pSrc[2 * l + 1] = p2 - p3; + + i += n1; + } while ( i < fftLen ); // butterfly loop end + j++; + } while ( j < n2); // groups loop end + twidCoefModifier <<= 1U; + } // stages loop end + + // loop for butterfly + for (i = 0; i < fftLen; i += 2) + { + a0 = pSrc[2 * i] + pSrc[2 * i + 2]; + xt = pSrc[2 * i] - pSrc[2 * i + 2]; + + yt = pSrc[2 * i + 1] - pSrc[2 * i + 3]; + a1 = pSrc[2 * i + 3] + pSrc[2 * i + 1]; + + pSrc[2 * i] = a0; + pSrc[2 * i + 1] = a1; + pSrc[2 * i + 2] = xt; + pSrc[2 * i + 3] = yt; + } // groups loop end + +#else + + n2 = fftLen; + + // loop for stage + for (k = fftLen; k > 1; k = k >> 1) + { + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + // loop for groups + j = 0; + do + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + ia += twidCoefModifier; + + // loop for butterfly + i = j; + do + { + l = i + n2; + a0 = pSrc[2 * i] + pSrc[2 * l]; + xt = pSrc[2 * i] - pSrc[2 * l]; + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1]; + + p0 = xt * cosVal; + p1 = yt * sinVal; + p2 = yt * cosVal; + p3 = xt * sinVal; + + pSrc[2 * i] = a0; + pSrc[2 * i + 1] = a1; + + pSrc[2 * l] = p0 + p1; + pSrc[2 * l + 1] = p2 - p3; + + i += n1; + } while (i < fftLen); + j++; + } while (j < n2); + twidCoefModifier <<= 1U; + } + +#endif // #if defined (RISCV_MATH_DSP) + +} + + +void riscv_radix2_butterfly_inverse_f16( +float16_t * pSrc, +uint32_t fftLen, +const float16_t * pCoef, +uint16_t twidCoefModifier, +float16_t onebyfftLen) +{ + + uint32_t i, j, k, l; + uint32_t n1, n2, ia; + float16_t xt, yt, cosVal, sinVal; + float16_t p0, p1, p2, p3; + float16_t a0, a1; + +#if defined (RISCV_MATH_DSP) + + n2 = fftLen >> 1; + ia = 0; + + // loop for groups + for (i = 0; i < n2; i++) + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + ia += twidCoefModifier; + + l = i + n2; + a0 = pSrc[2 * i] + pSrc[2 * l]; + xt = pSrc[2 * i] - pSrc[2 * l]; + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1]; + + p0 = xt * cosVal; + p1 = yt * sinVal; + p2 = yt * cosVal; + p3 = xt * sinVal; + + pSrc[2 * i] = a0; + pSrc[2 * i + 1] = a1; + + pSrc[2 * l] = p0 - p1; + pSrc[2 * l + 1] = p2 + p3; + } // groups loop end + + twidCoefModifier <<= 1U; + + // loop for stage + for (k = fftLen / 2; k > 2; k = k >> 1) + { + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + // loop for groups + j = 0; + do + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + ia += twidCoefModifier; + + // loop for butterfly + i = j; + do + { + l = i + n2; + a0 = pSrc[2 * i] + pSrc[2 * l]; + xt = pSrc[2 * i] - pSrc[2 * l]; + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1]; + + p0 = xt * cosVal; + p1 = yt * sinVal; + p2 = yt * cosVal; + p3 = xt * sinVal; + + pSrc[2 * i] = a0; + pSrc[2 * i + 1] = a1; + + pSrc[2 * l] = p0 - p1; + pSrc[2 * l + 1] = p2 + p3; + + i += n1; + } while ( i < fftLen ); // butterfly loop end + j++; + } while (j < n2); // groups loop end + + twidCoefModifier <<= 1U; + } // stages loop end + + // loop for butterfly + for (i = 0; i < fftLen; i += 2) + { + a0 = pSrc[2 * i] + pSrc[2 * i + 2]; + xt = pSrc[2 * i] - pSrc[2 * i + 2]; + + a1 = pSrc[2 * i + 3] + pSrc[2 * i + 1]; + yt = pSrc[2 * i + 1] - pSrc[2 * i + 3]; + + p0 = a0 * onebyfftLen; + p2 = xt * onebyfftLen; + p1 = a1 * onebyfftLen; + p3 = yt * onebyfftLen; + + pSrc[2 * i] = p0; + pSrc[2 * i + 1] = p1; + pSrc[2 * i + 2] = p2; + pSrc[2 * i + 3] = p3; + } // butterfly loop end + +#else + + n2 = fftLen; + + // loop for stage + for (k = fftLen; k > 2; k = k >> 1) + { + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + // loop for groups + j = 0; + do + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + ia = ia + twidCoefModifier; + + // loop for butterfly + i = j; + do + { + l = i + n2; + a0 = pSrc[2 * i] + pSrc[2 * l]; + xt = pSrc[2 * i] - pSrc[2 * l]; + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1]; + + p0 = xt * cosVal; + p1 = yt * sinVal; + p2 = yt * cosVal; + p3 = xt * sinVal; + + pSrc[2 * i] = a0; + pSrc[2 * i + 1] = a1; + + pSrc[2 * l] = p0 - p1; + pSrc[2 * l + 1] = p2 + p3; + + i += n1; + } while ( i < fftLen ); // butterfly loop end + j++; + } while ( j < n2 ); // groups loop end + + twidCoefModifier = twidCoefModifier << 1U; + } // stages loop end + + n1 = n2; + n2 = n2 >> 1; + + // loop for butterfly + for (i = 0; i < fftLen; i += n1) + { + l = i + n2; + + a0 = pSrc[2 * i] + pSrc[2 * l]; + xt = pSrc[2 * i] - pSrc[2 * l]; + + a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1]; + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + + p0 = a0 * onebyfftLen; + p2 = xt * onebyfftLen; + p1 = a1 * onebyfftLen; + p3 = yt * onebyfftLen; + + pSrc[2 * i] = p0; + pSrc[2U * l] = p2; + + pSrc[2 * i + 1] = p1; + pSrc[2U * l + 1U] = p3; + } // butterfly loop end + +#endif // #if defined (RISCV_MATH_DSP) + +} + + +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ diff --git a/components/nmsis/dsp/src/TransformFunctions/riscv_cfft_radix2_f32.c b/components/nmsis/dsp/src/TransformFunctions/riscv_cfft_radix2_f32.c new file mode 100644 index 00000000..0b58ae3f --- /dev/null +++ b/components/nmsis/dsp/src/TransformFunctions/riscv_cfft_radix2_f32.c @@ -0,0 +1,471 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_cfft_radix2_f32.c + * Description: Radix-2 Decimation in Frequency CFFT & CIFFT Floating point processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" + +void riscv_radix2_butterfly_f32( + float32_t * pSrc, + uint32_t fftLen, + const float32_t * pCoef, + uint16_t twidCoefModifier); + +void riscv_radix2_butterfly_inverse_f32( + float32_t * pSrc, + uint32_t fftLen, + const float32_t * pCoef, + uint16_t twidCoefModifier, + float32_t onebyfftLen); + +extern void riscv_bitreversal_f32( + float32_t * pSrc, + uint16_t fftSize, + uint16_t bitRevFactor, + const uint16_t * pBitRevTab); + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Radix-2 CFFT/CIFFT. + @deprecated Do not use this function. It has been superseded by \ref riscv_cfft_f32 and will be removed in the future + @param[in] S points to an instance of the floating-point Radix-2 CFFT/CIFFT structure + @param[in,out] pSrc points to the complex data buffer of size 2*fftLen. Processing occurs in-place + @return none + */ + +void riscv_cfft_radix2_f32( +const riscv_cfft_radix2_instance_f32 * S, + float32_t * pSrc) +{ + + if (S->ifftFlag == 1U) + { + /* Complex IFFT radix-2 */ + riscv_radix2_butterfly_inverse_f32(pSrc, S->fftLen, S->pTwiddle, + S->twidCoefModifier, S->onebyfftLen); + } + else + { + /* Complex FFT radix-2 */ + riscv_radix2_butterfly_f32(pSrc, S->fftLen, S->pTwiddle, + S->twidCoefModifier); + } + + if (S->bitReverseFlag == 1U) + { + /* Bit Reversal */ + riscv_bitreversal_f32(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable); + } + +} + + +/** + @} end of ComplexFFT group + */ + + + +/* ---------------------------------------------------------------------- + ** Internal helper function used by the FFTs + ** ------------------------------------------------------------------- */ + +/** + brief Core function for the floating-point CFFT butterfly process. + param[in,out] pSrc points to in-place buffer of floating-point data type + param[in] fftLen length of the FFT + param[in] pCoef points to twiddle coefficient buffer + param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table + return none + */ + +void riscv_radix2_butterfly_f32( + float32_t * pSrc, + uint32_t fftLen, + const float32_t * pCoef, + uint16_t twidCoefModifier) +{ + + uint32_t i, j, k, l; + uint32_t n1, n2, ia; + float32_t xt, yt, cosVal, sinVal; + float32_t p0, p1, p2, p3; + float32_t a0, a1; + +#if defined (RISCV_MATH_DSP) + + /* Initializations for the first stage */ + n2 = fftLen >> 1; + ia = 0; + i = 0; + + // loop for groups + for (k = n2; k > 0; k--) + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + + /* Twiddle coefficients index modifier */ + ia += twidCoefModifier; + + /* index calculation for the input as, */ + /* pSrc[i + 0], pSrc[i + fftLen/1] */ + l = i + n2; + + /* Butterfly implementation */ + a0 = pSrc[2 * i] + pSrc[2 * l]; + xt = pSrc[2 * i] - pSrc[2 * l]; + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1]; + + p0 = xt * cosVal; + p1 = yt * sinVal; + p2 = yt * cosVal; + p3 = xt * sinVal; + + pSrc[2 * i] = a0; + pSrc[2 * i + 1] = a1; + + pSrc[2 * l] = p0 + p1; + pSrc[2 * l + 1] = p2 - p3; + + i++; + } // groups loop end + + twidCoefModifier <<= 1U; + + // loop for stage + for (k = n2; k > 2; k = k >> 1) + { + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + // loop for groups + j = 0; + do + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + ia += twidCoefModifier; + + // loop for butterfly + i = j; + do + { + l = i + n2; + a0 = pSrc[2 * i] + pSrc[2 * l]; + xt = pSrc[2 * i] - pSrc[2 * l]; + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1]; + + p0 = xt * cosVal; + p1 = yt * sinVal; + p2 = yt * cosVal; + p3 = xt * sinVal; + + pSrc[2 * i] = a0; + pSrc[2 * i + 1] = a1; + + pSrc[2 * l] = p0 + p1; + pSrc[2 * l + 1] = p2 - p3; + + i += n1; + } while ( i < fftLen ); // butterfly loop end + j++; + } while ( j < n2); // groups loop end + twidCoefModifier <<= 1U; + } // stages loop end + + // loop for butterfly + for (i = 0; i < fftLen; i += 2) + { + a0 = pSrc[2 * i] + pSrc[2 * i + 2]; + xt = pSrc[2 * i] - pSrc[2 * i + 2]; + + yt = pSrc[2 * i + 1] - pSrc[2 * i + 3]; + a1 = pSrc[2 * i + 3] + pSrc[2 * i + 1]; + + pSrc[2 * i] = a0; + pSrc[2 * i + 1] = a1; + pSrc[2 * i + 2] = xt; + pSrc[2 * i + 3] = yt; + } // groups loop end + +#else /* #if defined (RISCV_MATH_DSP) */ + + n2 = fftLen; + + // loop for stage + for (k = fftLen; k > 1; k = k >> 1) + { + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + // loop for groups + j = 0; + do + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + ia += twidCoefModifier; + + // loop for butterfly + i = j; + do + { + l = i + n2; + a0 = pSrc[2 * i] + pSrc[2 * l]; + xt = pSrc[2 * i] - pSrc[2 * l]; + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1]; + + p0 = xt * cosVal; + p1 = yt * sinVal; + p2 = yt * cosVal; + p3 = xt * sinVal; + + pSrc[2 * i] = a0; + pSrc[2 * i + 1] = a1; + + pSrc[2 * l] = p0 + p1; + pSrc[2 * l + 1] = p2 - p3; + + i += n1; + } while (i < fftLen); + j++; + } while (j < n2); + twidCoefModifier <<= 1U; + } + +#endif /* #if defined (RISCV_MATH_DSP) */ + +} + + +void riscv_radix2_butterfly_inverse_f32( + float32_t * pSrc, + uint32_t fftLen, + const float32_t * pCoef, + uint16_t twidCoefModifier, + float32_t onebyfftLen) +{ + + uint32_t i, j, k, l; + uint32_t n1, n2, ia; + float32_t xt, yt, cosVal, sinVal; + float32_t p0, p1, p2, p3; + float32_t a0, a1; + +#if defined (RISCV_MATH_DSP) + + n2 = fftLen >> 1; + ia = 0; + + // loop for groups + for (i = 0; i < n2; i++) + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + ia += twidCoefModifier; + + l = i + n2; + a0 = pSrc[2 * i] + pSrc[2 * l]; + xt = pSrc[2 * i] - pSrc[2 * l]; + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1]; + + p0 = xt * cosVal; + p1 = yt * sinVal; + p2 = yt * cosVal; + p3 = xt * sinVal; + + pSrc[2 * i] = a0; + pSrc[2 * i + 1] = a1; + + pSrc[2 * l] = p0 - p1; + pSrc[2 * l + 1] = p2 + p3; + } // groups loop end + + twidCoefModifier <<= 1U; + + // loop for stage + for (k = fftLen / 2; k > 2; k = k >> 1) + { + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + // loop for groups + j = 0; + do + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + ia += twidCoefModifier; + + // loop for butterfly + i = j; + do + { + l = i + n2; + a0 = pSrc[2 * i] + pSrc[2 * l]; + xt = pSrc[2 * i] - pSrc[2 * l]; + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1]; + + p0 = xt * cosVal; + p1 = yt * sinVal; + p2 = yt * cosVal; + p3 = xt * sinVal; + + pSrc[2 * i] = a0; + pSrc[2 * i + 1] = a1; + + pSrc[2 * l] = p0 - p1; + pSrc[2 * l + 1] = p2 + p3; + + i += n1; + } while ( i < fftLen ); // butterfly loop end + j++; + } while (j < n2); // groups loop end + + twidCoefModifier <<= 1U; + } // stages loop end + + // loop for butterfly + for (i = 0; i < fftLen; i += 2) + { + a0 = pSrc[2 * i] + pSrc[2 * i + 2]; + xt = pSrc[2 * i] - pSrc[2 * i + 2]; + + a1 = pSrc[2 * i + 3] + pSrc[2 * i + 1]; + yt = pSrc[2 * i + 1] - pSrc[2 * i + 3]; + + p0 = a0 * onebyfftLen; + p2 = xt * onebyfftLen; + p1 = a1 * onebyfftLen; + p3 = yt * onebyfftLen; + + pSrc[2 * i] = p0; + pSrc[2 * i + 1] = p1; + pSrc[2 * i + 2] = p2; + pSrc[2 * i + 3] = p3; + } // butterfly loop end + +#else /* #if defined (RISCV_MATH_DSP) */ + + n2 = fftLen; + + // loop for stage + for (k = fftLen; k > 2; k = k >> 1) + { + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + // loop for groups + j = 0; + do + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + ia = ia + twidCoefModifier; + + // loop for butterfly + i = j; + do + { + l = i + n2; + a0 = pSrc[2 * i] + pSrc[2 * l]; + xt = pSrc[2 * i] - pSrc[2 * l]; + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1]; + + p0 = xt * cosVal; + p1 = yt * sinVal; + p2 = yt * cosVal; + p3 = xt * sinVal; + + pSrc[2 * i] = a0; + pSrc[2 * i + 1] = a1; + + pSrc[2 * l] = p0 - p1; + pSrc[2 * l + 1] = p2 + p3; + + i += n1; + } while ( i < fftLen ); // butterfly loop end + j++; + } while ( j < n2 ); // groups loop end + + twidCoefModifier = twidCoefModifier << 1U; + } // stages loop end + + n1 = n2; + n2 = n2 >> 1; + + // loop for butterfly + for (i = 0; i < fftLen; i += n1) + { + l = i + n2; + + a0 = pSrc[2 * i] + pSrc[2 * l]; + xt = pSrc[2 * i] - pSrc[2 * l]; + + a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1]; + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + + p0 = a0 * onebyfftLen; + p2 = xt * onebyfftLen; + p1 = a1 * onebyfftLen; + p3 = yt * onebyfftLen; + + pSrc[2 * i] = p0; + pSrc[2 * l] = p2; + + pSrc[2 * i + 1] = p1; + pSrc[2 * l + 1] = p3; + } // butterfly loop end + +#endif /* #if defined (RISCV_MATH_DSP) */ + +} diff --git a/components/nmsis/dsp/src/TransformFunctions/riscv_cfft_radix2_init_f16.c b/components/nmsis/dsp/src/TransformFunctions/riscv_cfft_radix2_init_f16.c new file mode 100644 index 00000000..eba712a9 --- /dev/null +++ b/components/nmsis/dsp/src/TransformFunctions/riscv_cfft_radix2_init_f16.c @@ -0,0 +1,215 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_cfft_radix2_init_f16.c + * Description: Radix-2 Decimation in Frequency Floating-point CFFT & CIFFT Initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions_f16.h" +#include "riscv_common_tables.h" +#include "riscv_common_tables_f16.h" + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Initialization function for the floating-point CFFT/CIFFT. + @deprecated Do not use this function. It has been superseded by \ref riscv_cfft_f16 and will be removed in the future. + @param[in,out] S points to an instance of the floating-point CFFT/CIFFT structure + @param[in] fftLen length of the FFT + @param[in] ifftFlag flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_ARGUMENT_ERROR : fftLen is not a supported length + + @par Details + The parameter ifftFlag controls whether a forward or inverse transform is computed. + Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated + @par + The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. + Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. + @par + The parameter fftLen Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024. + @par + This Function also initializes Twiddle factor table pointer and Bit reversal table pointer. +*/ + +#if defined(RISCV_FLOAT16_SUPPORTED) + +riscv_status riscv_cfft_radix2_init_f16( + riscv_cfft_radix2_instance_f16 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + /* Initialise the default riscv status */ + riscv_status status = RISCV_MATH_ARGUMENT_ERROR; + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_FFT_ALLOW_TABLES) + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_F16_4096) + + + /* Initialise the default riscv status */ + status = RISCV_MATH_SUCCESS; + + /* Initialise the FFT length */ + S->fftLen = fftLen; + + /* Initialise the Twiddle coefficient pointer */ + S->pTwiddle = (float16_t *) twiddleCoefF16_4096; + + /* Initialise the Flag for selection of CFFT or CIFFT */ + S->ifftFlag = ifftFlag; + + /* Initialise the Flag for calculation Bit reversal or not */ + S->bitReverseFlag = bitReverseFlag; + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREV_1024) + + /* Initializations of structure parameters depending on the FFT length */ + switch (S->fftLen) + { + + case 4096U: + /* Initializations of structure parameters for 4096 point FFT */ + + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 1U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 1U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) riscvBitRevTable; + /* Initialise the 1/fftLen Value */ + S->onebyfftLen = 0.000244140625; + break; + + case 2048U: + /* Initializations of structure parameters for 2048 point FFT */ + + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 2U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 2U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) & riscvBitRevTable[1]; + /* Initialise the 1/fftLen Value */ + S->onebyfftLen = 0.00048828125; + break; + + case 1024U: + /* Initializations of structure parameters for 1024 point FFT */ + + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 4U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 4U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) & riscvBitRevTable[3]; + /* Initialise the 1/fftLen Value */ + S->onebyfftLen = 0.0009765625f; + break; + + case 512U: + /* Initializations of structure parameters for 512 point FFT */ + + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 8U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 8U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) & riscvBitRevTable[7]; + /* Initialise the 1/fftLen Value */ + S->onebyfftLen = 0.001953125; + break; + + case 256U: + /* Initializations of structure parameters for 256 point FFT */ + S->twidCoefModifier = 16U; + S->bitRevFactor = 16U; + S->pBitRevTable = (uint16_t *) & riscvBitRevTable[15]; + S->onebyfftLen = 0.00390625f; + break; + + case 128U: + /* Initializations of structure parameters for 128 point FFT */ + S->twidCoefModifier = 32U; + S->bitRevFactor = 32U; + S->pBitRevTable = (uint16_t *) & riscvBitRevTable[31]; + S->onebyfftLen = 0.0078125; + break; + + case 64U: + /* Initializations of structure parameters for 64 point FFT */ + S->twidCoefModifier = 64U; + S->bitRevFactor = 64U; + S->pBitRevTable = (uint16_t *) & riscvBitRevTable[63]; + S->onebyfftLen = 0.015625f; + break; + + case 32U: + /* Initializations of structure parameters for 64 point FFT */ + S->twidCoefModifier = 128U; + S->bitRevFactor = 128U; + S->pBitRevTable = (uint16_t *) & riscvBitRevTable[127]; + S->onebyfftLen = 0.03125; + break; + + case 16U: + /* Initializations of structure parameters for 16 point FFT */ + S->twidCoefModifier = 256U; + S->bitRevFactor = 256U; + S->pBitRevTable = (uint16_t *) & riscvBitRevTable[255]; + S->onebyfftLen = 0.0625f; + break; + + + default: + /* Reporting argument error if fftSize is not valid value */ + status = RISCV_MATH_ARGUMENT_ERROR; + break; + } + +#endif +#endif +#endif + return (status); +} + +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ +/** + @} end of ComplexFFT group + */ diff --git a/components/nmsis/dsp/src/TransformFunctions/riscv_cfft_radix2_init_f32.c b/components/nmsis/dsp/src/TransformFunctions/riscv_cfft_radix2_init_f32.c new file mode 100644 index 00000000..1f0e46f7 --- /dev/null +++ b/components/nmsis/dsp/src/TransformFunctions/riscv_cfft_radix2_init_f32.c @@ -0,0 +1,210 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_cfft_radix2_init_f32.c + * Description: Radix-2 Decimation in Frequency Floating-point CFFT & CIFFT Initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" +#include "riscv_common_tables.h" + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Initialization function for the floating-point CFFT/CIFFT. + @deprecated Do not use this function. It has been superseded by \ref riscv_cfft_f32 and will be removed in the future. + @param[in,out] S points to an instance of the floating-point CFFT/CIFFT structure + @param[in] fftLen length of the FFT + @param[in] ifftFlag flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_ARGUMENT_ERROR : fftLen is not a supported length + + @par Details + The parameter ifftFlag controls whether a forward or inverse transform is computed. + Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated + @par + The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. + Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. + @par + The parameter fftLen Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024. + @par + This Function also initializes Twiddle factor table pointer and Bit reversal table pointer. +*/ + +riscv_status riscv_cfft_radix2_init_f32( + riscv_cfft_radix2_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + /* Initialise the default riscv status */ + riscv_status status = RISCV_MATH_ARGUMENT_ERROR; + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_FFT_ALLOW_TABLES) + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_F32_4096) + + /* Initialise the default riscv status */ + status = RISCV_MATH_SUCCESS; + + /* Initialise the FFT length */ + S->fftLen = fftLen; + + /* Initialise the Twiddle coefficient pointer */ + S->pTwiddle = (float32_t *) twiddleCoef; + + /* Initialise the Flag for selection of CFFT or CIFFT */ + S->ifftFlag = ifftFlag; + + /* Initialise the Flag for calculation Bit reversal or not */ + S->bitReverseFlag = bitReverseFlag; + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_F32_4096) + + /* Initializations of structure parameters depending on the FFT length */ + switch (S->fftLen) + { + + case 4096U: + /* Initializations of structure parameters for 4096 point FFT */ + + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 1U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 1U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) riscvBitRevTable; + /* Initialise the 1/fftLen Value */ + S->onebyfftLen = 0.000244140625; + break; + + case 2048U: + /* Initializations of structure parameters for 2048 point FFT */ + + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 2U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 2U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) & riscvBitRevTable[1]; + /* Initialise the 1/fftLen Value */ + S->onebyfftLen = 0.00048828125; + break; + + case 1024U: + /* Initializations of structure parameters for 1024 point FFT */ + + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 4U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 4U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) & riscvBitRevTable[3]; + /* Initialise the 1/fftLen Value */ + S->onebyfftLen = 0.0009765625f; + break; + + case 512U: + /* Initializations of structure parameters for 512 point FFT */ + + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 8U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 8U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) & riscvBitRevTable[7]; + /* Initialise the 1/fftLen Value */ + S->onebyfftLen = 0.001953125; + break; + + case 256U: + /* Initializations of structure parameters for 256 point FFT */ + S->twidCoefModifier = 16U; + S->bitRevFactor = 16U; + S->pBitRevTable = (uint16_t *) & riscvBitRevTable[15]; + S->onebyfftLen = 0.00390625f; + break; + + case 128U: + /* Initializations of structure parameters for 128 point FFT */ + S->twidCoefModifier = 32U; + S->bitRevFactor = 32U; + S->pBitRevTable = (uint16_t *) & riscvBitRevTable[31]; + S->onebyfftLen = 0.0078125; + break; + + case 64U: + /* Initializations of structure parameters for 64 point FFT */ + S->twidCoefModifier = 64U; + S->bitRevFactor = 64U; + S->pBitRevTable = (uint16_t *) & riscvBitRevTable[63]; + S->onebyfftLen = 0.015625f; + break; + + case 32U: + /* Initializations of structure parameters for 64 point FFT */ + S->twidCoefModifier = 128U; + S->bitRevFactor = 128U; + S->pBitRevTable = (uint16_t *) & riscvBitRevTable[127]; + S->onebyfftLen = 0.03125; + break; + + case 16U: + /* Initializations of structure parameters for 16 point FFT */ + S->twidCoefModifier = 256U; + S->bitRevFactor = 256U; + S->pBitRevTable = (uint16_t *) & riscvBitRevTable[255]; + S->onebyfftLen = 0.0625f; + break; + + + default: + /* Reporting argument error if fftSize is not valid value */ + status = RISCV_MATH_ARGUMENT_ERROR; + break; + } + +#endif +#endif +#endif + return (status); +} + +/** + @} end of ComplexFFT group + */ diff --git a/components/nmsis/dsp/src/TransformFunctions/riscv_cfft_radix2_init_q15.c b/components/nmsis/dsp/src/TransformFunctions/riscv_cfft_radix2_init_q15.c new file mode 100644 index 00000000..1b7c8381 --- /dev/null +++ b/components/nmsis/dsp/src/TransformFunctions/riscv_cfft_radix2_init_q15.c @@ -0,0 +1,195 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_cfft_radix2_init_q15.c + * Description: Radix-2 Decimation in Frequency Q15 FFT & IFFT initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" +#include "riscv_common_tables.h" + +/** + @ingroup groupTransforms + */ + + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Initialization function for the Q15 CFFT/CIFFT. + @deprecated Do not use this function. It has been superseded by \ref riscv_cfft_q15 and will be removed + @param[in,out] S points to an instance of the Q15 CFFT/CIFFT structure. + @param[in] fftLen length of the FFT. + @param[in] ifftFlag flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_ARGUMENT_ERROR : fftLen is not a supported length + + @par Details + The parameter ifftFlag controls whether a forward or inverse transform is computed. + Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated + @par + The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. + Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. + @par + The parameter fftLen Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024. + @par + This Function also initializes Twiddle factor table pointer and Bit reversal table pointer. +*/ + +riscv_status riscv_cfft_radix2_init_q15( + riscv_cfft_radix2_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + /* Initialise the default riscv status */ + riscv_status status = RISCV_MATH_ARGUMENT_ERROR; + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_FFT_ALLOW_TABLES) + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_Q15_4096) + + /* Initialise the default riscv status */ + status = RISCV_MATH_SUCCESS; + + /* Initialise the FFT length */ + S->fftLen = fftLen; + + /* Initialise the Twiddle coefficient pointer */ + S->pTwiddle = (q15_t *) twiddleCoef_4096_q15; + /* Initialise the Flag for selection of CFFT or CIFFT */ + S->ifftFlag = ifftFlag; + /* Initialise the Flag for calculation Bit reversal or not */ + S->bitReverseFlag = bitReverseFlag; + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREV_1024) + + /* Initializations of structure parameters depending on the FFT length */ + switch (S->fftLen) + { + case 4096U: + /* Initializations of structure parameters for 4096 point FFT */ + + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 1U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 1U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) riscvBitRevTable; + + break; + + case 2048U: + /* Initializations of structure parameters for 2048 point FFT */ + + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 2U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 2U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) & riscvBitRevTable[1]; + + break; + + case 1024U: + /* Initializations of structure parameters for 1024 point FFT */ + S->twidCoefModifier = 4U; + S->bitRevFactor = 4U; + S->pBitRevTable = (uint16_t *) & riscvBitRevTable[3]; + + break; + + case 512U: + /* Initializations of structure parameters for 512 point FFT */ + S->twidCoefModifier = 8U; + S->bitRevFactor = 8U; + S->pBitRevTable = (uint16_t *) & riscvBitRevTable[7]; + + break; + + case 256U: + /* Initializations of structure parameters for 256 point FFT */ + S->twidCoefModifier = 16U; + S->bitRevFactor = 16U; + S->pBitRevTable = (uint16_t *) & riscvBitRevTable[15]; + + break; + + case 128U: + /* Initializations of structure parameters for 128 point FFT */ + S->twidCoefModifier = 32U; + S->bitRevFactor = 32U; + S->pBitRevTable = (uint16_t *) & riscvBitRevTable[31]; + + break; + + case 64U: + /* Initializations of structure parameters for 64 point FFT */ + S->twidCoefModifier = 64U; + S->bitRevFactor = 64U; + S->pBitRevTable = (uint16_t *) & riscvBitRevTable[63]; + + break; + + case 32U: + /* Initializations of structure parameters for 32 point FFT */ + S->twidCoefModifier = 128U; + S->bitRevFactor = 128U; + S->pBitRevTable = (uint16_t *) & riscvBitRevTable[127]; + + break; + + case 16U: + /* Initializations of structure parameters for 16 point FFT */ + S->twidCoefModifier = 256U; + S->bitRevFactor = 256U; + S->pBitRevTable = (uint16_t *) & riscvBitRevTable[255]; + + break; + + default: + /* Reporting argument error if fftSize is not valid value */ + status = RISCV_MATH_ARGUMENT_ERROR; + break; + } + +#endif +#endif +#endif + return (status); +} + +/** + @} end of ComplexFFT group + */ diff --git a/components/nmsis/dsp/src/TransformFunctions/riscv_cfft_radix2_init_q31.c b/components/nmsis/dsp/src/TransformFunctions/riscv_cfft_radix2_init_q31.c new file mode 100644 index 00000000..fb117bd8 --- /dev/null +++ b/components/nmsis/dsp/src/TransformFunctions/riscv_cfft_radix2_init_q31.c @@ -0,0 +1,192 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_cfft_radix2_init_q31.c + * Description: Radix-2 Decimation in Frequency Fixed-point CFFT & CIFFT Initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" +#include "riscv_common_tables.h" + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Initialization function for the Q31 CFFT/CIFFT. + @deprecated Do not use this function. It has been superseded by \ref riscv_cfft_q31 and will be removed in the future. + @param[in,out] S points to an instance of the Q31 CFFT/CIFFT structure + @param[in] fftLen length of the FFT + @param[in] ifftFlag flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_ARGUMENT_ERROR : fftLen is not a supported length + + @par Details + The parameter ifftFlag controls whether a forward or inverse transform is computed. + Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated + @par + The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. + Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. + @par + The parameter fftLen Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024. + @par + This Function also initializes Twiddle factor table pointer and Bit reversal table pointer. +*/ + +riscv_status riscv_cfft_radix2_init_q31( + riscv_cfft_radix2_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + /* Initialise the default riscv status */ + riscv_status status = RISCV_MATH_ARGUMENT_ERROR; + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_FFT_ALLOW_TABLES) + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_Q31_4096) + + /* Initialise the default riscv status */ + status = RISCV_MATH_SUCCESS; + + /* Initialise the FFT length */ + S->fftLen = fftLen; + + /* Initialise the Twiddle coefficient pointer */ + S->pTwiddle = (q31_t *) twiddleCoef_4096_q31; + + /* Initialise the Flag for selection of CFFT or CIFFT */ + S->ifftFlag = ifftFlag; + + /* Initialise the Flag for calculation Bit reversal or not */ + S->bitReverseFlag = bitReverseFlag; + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREV_1024) + + /* Initializations of Instance structure depending on the FFT length */ + switch (S->fftLen) + { + /* Initializations of structure parameters for 4096 point FFT */ + case 4096U: + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 1U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 1U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) riscvBitRevTable; + break; + + /* Initializations of structure parameters for 2048 point FFT */ + case 2048U: + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 2U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 2U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) & riscvBitRevTable[1]; + break; + + /* Initializations of structure parameters for 1024 point FFT */ + case 1024U: + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 4U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 4U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) & riscvBitRevTable[3]; + break; + + /* Initializations of structure parameters for 512 point FFT */ + case 512U: + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 8U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 8U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) & riscvBitRevTable[7]; + break; + + case 256U: + /* Initializations of structure parameters for 256 point FFT */ + S->twidCoefModifier = 16U; + S->bitRevFactor = 16U; + S->pBitRevTable = (uint16_t *) & riscvBitRevTable[15]; + break; + + case 128U: + /* Initializations of structure parameters for 128 point FFT */ + S->twidCoefModifier = 32U; + S->bitRevFactor = 32U; + S->pBitRevTable = (uint16_t *) & riscvBitRevTable[31]; + break; + + case 64U: + /* Initializations of structure parameters for 64 point FFT */ + S->twidCoefModifier = 64U; + S->bitRevFactor = 64U; + S->pBitRevTable = (uint16_t *) & riscvBitRevTable[63]; + break; + + case 32U: + /* Initializations of structure parameters for 32 point FFT */ + S->twidCoefModifier = 128U; + S->bitRevFactor = 128U; + S->pBitRevTable = (uint16_t *) & riscvBitRevTable[127]; + break; + + case 16U: + /* Initializations of structure parameters for 16 point FFT */ + S->twidCoefModifier = 256U; + S->bitRevFactor = 256U; + S->pBitRevTable = (uint16_t *) & riscvBitRevTable[255]; + break; + + + default: + /* Reporting argument error if fftSize is not valid value */ + status = RISCV_MATH_ARGUMENT_ERROR; + break; + } + +#endif +#endif +#endif + return (status); +} + +/** + @} end of ComplexFFT group + */ diff --git a/components/nmsis/dsp/src/TransformFunctions/riscv_cfft_radix2_q15.c b/components/nmsis/dsp/src/TransformFunctions/riscv_cfft_radix2_q15.c new file mode 100644 index 00000000..8f88fd5b --- /dev/null +++ b/components/nmsis/dsp/src/TransformFunctions/riscv_cfft_radix2_q15.c @@ -0,0 +1,704 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_cfft_radix2_q15.c + * Description: Radix-2 Decimation in Frequency CFFT & CIFFT Fixed point processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" + +void riscv_radix2_butterfly_q15( + q15_t * pSrc, + uint32_t fftLen, + const q15_t * pCoef, + uint16_t twidCoefModifier); + +void riscv_radix2_butterfly_inverse_q15( + q15_t * pSrc, + uint32_t fftLen, + const q15_t * pCoef, + uint16_t twidCoefModifier); + +void riscv_bitreversal_q15( + q15_t * pSrc, + uint32_t fftLen, + uint16_t bitRevFactor, + const uint16_t * pBitRevTab); + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Processing function for the fixed-point CFFT/CIFFT. + @deprecated Do not use this function. It has been superseded by \ref riscv_cfft_q15 and will be removed in the future. + @param[in] S points to an instance of the fixed-point CFFT/CIFFT structure + @param[in,out] pSrc points to the complex data buffer of size 2*fftLen. Processing occurs in-place + @return none + */ + +void riscv_cfft_radix2_q15( + const riscv_cfft_radix2_instance_q15 * S, + q15_t * pSrc) +{ + + if (S->ifftFlag == 1U) + { + riscv_radix2_butterfly_inverse_q15 (pSrc, S->fftLen, S->pTwiddle, S->twidCoefModifier); + } + else + { + riscv_radix2_butterfly_q15 (pSrc, S->fftLen, S->pTwiddle, S->twidCoefModifier); + } + + riscv_bitreversal_q15(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable); +} + +/** + @} end of ComplexFFT group + */ + +void riscv_radix2_butterfly_q15( + q15_t * pSrc, + uint32_t fftLen, + const q15_t * pCoef, + uint16_t twidCoefModifier) +{ +#if defined (RISCV_MATH_DSP) + + uint32_t i, j, k, l; + uint32_t n1, n2, ia; + q15_t in; + q31_t T, S, R; + q31_t coeff, out1, out2; +#if __RISCV_XLEN == 64 + q63_t T64, S64, R64; + q63_t coeff64, out164, out264; +#endif /* __RISCV_XLEN == 64 */ + //N = fftLen; + n2 = fftLen; + + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + // loop for groups + for (i = 0; i < n2; i++) + { +#if __RISCV_XLEN == 64 + coeff64 = (q63_t)(((uint64_t)(read_q15x2 ((q15_t *)pCoef + (ia * 2U)))) | (((uint64_t)(read_q15x2 ((q15_t *)pCoef + ((ia + twidCoefModifier) * 2U)))) << 32)); + + ia = ia + twidCoefModifier; + ia = ia + twidCoefModifier; + + l = i + n2; + + T64 = read_q15x4 (pSrc + (2 * i)); + T64 = __RV_RADD16(T64, 0); + + S64 = read_q15x4 (pSrc + (2 * l)); + S64 = __RV_RADD16(S64, 0); + + R64 = __RV_KSUB16(T64, S64); + + write_q15x4 (pSrc + (2 * i), __RV_RADD16(T64, S64)); + + out164 = __RV_KMDA(coeff64, R64) >> 16; + out264 = __RV_SMXDS(R64, coeff64); + + write_q15x4 (pSrc + (2U * l), (q63_t) ((out264) & 0xFFFF0000FFFF0000) | (out164 & 0x0000FFFF0000FFFF)); + i++; +#else + coeff = read_q15x2 ((q15_t *)pCoef + (ia * 2U)); + + ia = ia + twidCoefModifier; + + l = i + n2; + + T = read_q15x2 (pSrc + (2 * i)); + in = ((int16_t) (T & 0xFFFF)) >> 1; + T = ((T >> 1) & 0xFFFF0000) | (in & 0xFFFF); + + S = read_q15x2 (pSrc + (2 * l)); + in = ((int16_t) (S & 0xFFFF)) >> 1; + S = ((S >> 1) & 0xFFFF0000) | (in & 0xFFFF); + + R = __QSUB16(T, S); + + write_q15x2 (pSrc + (2 * i), __SHADD16(T, S)); + + out1 = __RV_KMDA(coeff, R) >> 16; + out2 = __RV_SMXDS(R, coeff); + + write_q15x2 (pSrc + (2U * l), (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF)); + + coeff = read_q15x2 ((q15_t *)pCoef + (ia * 2U)); + + ia = ia + twidCoefModifier; + + /* loop for butterfly */ + i++; + l++; + + T = read_q15x2 (pSrc + (2 * i)); + in = ((int16_t) (T & 0xFFFF)) >> 1; + T = ((T >> 1) & 0xFFFF0000) | (in & 0xFFFF); + + S = read_q15x2 (pSrc + (2 * l)); + in = ((int16_t) (S & 0xFFFF)) >> 1; + S = ((S >> 1) & 0xFFFF0000) | (in & 0xFFFF); + + R = __QSUB16(T, S); + + write_q15x2 (pSrc + (2 * i), __SHADD16(T, S)); + + out1 = __RV_KMDA(coeff, R) >> 16; + out2 = __RV_SMXDS(R, coeff); + + write_q15x2 (pSrc + (2U * l), (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF)); + +#endif /* __RISCV_XLEN == 64 */ + } /* groups loop end */ + + twidCoefModifier = twidCoefModifier << 1U; + + /* loop for stage */ + for (k = fftLen / 2; k > 2; k = k >> 1) + { + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + /* loop for groups */ + for (j = 0; j < n2; j++) + { + coeff = read_q15x2 ((q15_t *)pCoef + (ia * 2U)); + + ia = ia + twidCoefModifier; + + /* loop for butterfly */ + for (i = j; i < fftLen; i += n1) + { + l = i + n2; + + T = read_q15x2 (pSrc + (2 * i)); + + S = read_q15x2 (pSrc + (2 * l)); + + R = __QSUB16(T, S); + + write_q15x2 (pSrc + (2 * i), __SHADD16(T, S)); + + out1 = __RV_KMDA(coeff, R) >> 16; + out2 = __RV_SMXDS(R, coeff); + + write_q15x2 (pSrc + (2U * l), (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF)); + + i += n1; + + l = i + n2; + + T = read_q15x2 (pSrc + (2 * i)); + + S = read_q15x2 (pSrc + (2 * l)); + + R = __QSUB16(T, S); + + write_q15x2 (pSrc + (2 * i), __SHADD16(T, S)); + + out1 = __RV_KMDA(coeff, R) >> 16; + out2 = __RV_SMXDS(R, coeff); + + write_q15x2 (pSrc + (2U * l), (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF)); + + } /* butterfly loop end */ + + } /* groups loop end */ + + twidCoefModifier = twidCoefModifier << 1U; + } /* stages loop end */ + + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + coeff = read_q15x2 ((q15_t *)pCoef + (ia * 2U)); + + ia = ia + twidCoefModifier; + + /* loop for butterfly */ + for (i = 0; i < fftLen; i += n1) + { + l = i + n2; + + T = read_q15x2 (pSrc + (2 * i)); + + S = read_q15x2 (pSrc + (2 * l)); + + R = __RV_KSUB16(T, S); + + write_q15x2 (pSrc + (2 * i), __RV_KADD16(T, S)); + + write_q15x2 (pSrc + (2 * l), R); + + i += n1; + l = i + n2; + + T = read_q15x2 (pSrc + (2 * i)); + + S = read_q15x2 (pSrc + (2 * l)); + + R = __RV_KSUB16(T, S); + + write_q15x2 (pSrc + (2 * i), __RV_KADD16(T, S)); + + write_q15x2 (pSrc + (2 * l), R); + + } /* groups loop end */ + + +#else /* #if defined (RISCV_MATH_DSP) */ + + uint32_t i, j, k, l; + uint32_t n1, n2, ia; + q15_t xt, yt, cosVal, sinVal; + + + // N = fftLen; + n2 = fftLen; + + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + /* loop for groups */ + for (j = 0; j < n2; j++) + { + cosVal = pCoef[(ia * 2)]; + sinVal = pCoef[(ia * 2) + 1]; + ia = ia + twidCoefModifier; + + /* loop for butterfly */ + for (i = j; i < fftLen; i += n1) + { + l = i + n2; + xt = (pSrc[2 * i] >> 1U) - (pSrc[2 * l] >> 1U); + pSrc[2 * i] = ((pSrc[2 * i] >> 1U) + (pSrc[2 * l] >> 1U)) >> 1U; + + yt = (pSrc[2 * i + 1] >> 1U) - (pSrc[2 * l + 1] >> 1U); + pSrc[2 * i + 1] = ((pSrc[2 * l + 1] >> 1U) + + (pSrc[2 * i + 1] >> 1U) ) >> 1U; + + pSrc[2 * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16)) + + ((int16_t) (((q31_t) yt * sinVal) >> 16))); + + pSrc[2U * l + 1] = (((int16_t) (((q31_t) yt * cosVal) >> 16)) - + ((int16_t) (((q31_t) xt * sinVal) >> 16))); + + } /* butterfly loop end */ + + } /* groups loop end */ + + twidCoefModifier = twidCoefModifier << 1U; + + /* loop for stage */ + for (k = fftLen / 2; k > 2; k = k >> 1) + { + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + /* loop for groups */ + for (j = 0; j < n2; j++) + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + ia = ia + twidCoefModifier; + + /* loop for butterfly */ + for (i = j; i < fftLen; i += n1) + { + l = i + n2; + xt = pSrc[2 * i] - pSrc[2 * l]; + pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]) >> 1U; + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]) >> 1U; + + pSrc[2 * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16)) + + ((int16_t) (((q31_t) yt * sinVal) >> 16))); + + pSrc[2U * l + 1] = (((int16_t) (((q31_t) yt * cosVal) >> 16)) - + ((int16_t) (((q31_t) xt * sinVal) >> 16))); + + } /* butterfly loop end */ + + } /* groups loop end */ + + twidCoefModifier = twidCoefModifier << 1U; + } /* stages loop end */ + + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + /* loop for groups */ + for (j = 0; j < n2; j++) + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + + ia = ia + twidCoefModifier; + + /* loop for butterfly */ + for (i = j; i < fftLen; i += n1) + { + l = i + n2; + xt = pSrc[2 * i] - pSrc[2 * l]; + pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]); + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]); + + pSrc[2 * l] = xt; + + pSrc[2 * l + 1] = yt; + + } /* butterfly loop end */ + + } /* groups loop end */ + + twidCoefModifier = twidCoefModifier << 1U; + +#endif /* #if defined (RISCV_MATH_DSP) */ + +} + + +void riscv_radix2_butterfly_inverse_q15( + q15_t * pSrc, + uint32_t fftLen, + const q15_t * pCoef, + uint16_t twidCoefModifier) +{ +#if defined (RISCV_MATH_DSP) + + uint32_t i, j, k, l; + uint32_t n1, n2, ia; + q15_t in; + q31_t T, S, R; + q31_t coeff, out1, out2; +#if __RISCV_XLEN == 64 + q63_t T64, S64, R64; + q63_t coeff64, out164, out264; +#endif /* __RISCV_XLEN == 64 */ + // N = fftLen; + n2 = fftLen; + + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + /* loop for groups */ + for (i = 0; i < n2; i++) + { +#if __RISCV_XLEN == 64 + coeff64 = (q63_t)(((uint64_t)(read_q15x2 ((q15_t *)pCoef + (ia * 2U)))) | (((uint64_t)(read_q15x2 ((q15_t *)pCoef + ((ia + twidCoefModifier) * 2U)))) << 32)); + + ia = ia + twidCoefModifier; + ia = ia + twidCoefModifier; + + l = i + n2; + + T64 = read_q15x4 (pSrc + (2 * i)); + T64 = __RV_RADD16(T64, 0); + + S64 = read_q15x4 (pSrc + (2 * l)); + S64 = __RV_RADD16(S64, 0); + + R64 = __RV_KSUB16(T64, S64); + + write_q15x4 (pSrc + (2 * i), __RV_RADD16(T64, S64)); + + out164 = __RV_KMDA(coeff64, R64) >> 16; + out264 = __RV_SMXDS(R64, coeff64); + + write_q15x4 (pSrc + (2U * l), (q63_t) ((out264) & 0xFFFF0000FFFF0000) | (out164 & 0x0000FFFF0000FFFF)); + i++; +#else + coeff = read_q15x2 ((q15_t *)pCoef + (ia * 2U)); + + ia = ia + twidCoefModifier; + + l = i + n2; + + T = read_q15x2 (pSrc + (2 * i)); + in = ((int16_t) (T & 0xFFFF)) >> 1; + T = ((T >> 1) & 0xFFFF0000) | (in & 0xFFFF); + + S = read_q15x2 (pSrc + (2 * l)); + in = ((int16_t) (S & 0xFFFF)) >> 1; + S = ((S >> 1) & 0xFFFF0000) | (in & 0xFFFF); + + R = __RV_KSUB16(T, S); + + write_q15x2 (pSrc + (2 * i), __RV_RADD16(T, S)); + + out1 = __RV_SMDRS(coeff, R) >> 16; + out2 = __RV_KMXDA(coeff, R); + + write_q15x2 (pSrc + (2 * l), (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF)); + + coeff = read_q15x2 ((q15_t *)pCoef + (ia * 2U)); + + ia = ia + twidCoefModifier; + + /* loop for butterfly */ + i++; + l++; + + T = read_q15x2 (pSrc + (2 * i)); + in = ((int16_t) (T & 0xFFFF)) >> 1; + T = ((T >> 1) & 0xFFFF0000) | (in & 0xFFFF); + + S = read_q15x2 (pSrc + (2 * l)); + in = ((int16_t) (S & 0xFFFF)) >> 1; + S = ((S >> 1) & 0xFFFF0000) | (in & 0xFFFF); + + R = __RV_KSUB16(T, S); + + write_q15x2 (pSrc + (2 * i), __RV_RADD16(T, S)); + + out1 = __RV_SMDRS(coeff, R) >> 16; + out2 = __RV_KMXDA(coeff, R); + + write_q15x2 (pSrc + (2 * l), (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF)); +#endif /* __RISCV_XLEN == 64 */ + } /* groups loop end */ + + twidCoefModifier = twidCoefModifier << 1U; + + /* loop for stage */ + for (k = fftLen / 2; k > 2; k = k >> 1) + { + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + /* loop for groups */ + for (j = 0; j < n2; j++) + { + coeff = read_q15x2 ((q15_t *)pCoef + (ia * 2U)); + + ia = ia + twidCoefModifier; + + /* loop for butterfly */ + for (i = j; i < fftLen; i += n1) + { + l = i + n2; + + T = read_q15x2 (pSrc + (2 * i)); + + S = read_q15x2 (pSrc + (2 * l)); + + R = __RV_KSUB16(T, S); + + write_q15x2 (pSrc + (2 * i), __RV_RADD16(T, S)); + + out1 = __RV_SMDRS(coeff, R) >> 16; + out2 = __RV_KMXDA(coeff, R); + + write_q15x2 (pSrc + (2 * l), (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF)); + + i += n1; + + l = i + n2; + + T = read_q15x2 (pSrc + (2 * i)); + + S = read_q15x2 (pSrc + (2 * l)); + + R = __RV_KSUB16(T, S); + + write_q15x2 (pSrc + (2 * i), __RV_RADD16(T, S)); + + out1 = __RV_SMDRS(coeff, R) >> 16; + out2 = __RV_KMXDA(coeff, R); + + write_q15x2 (pSrc + (2 * l), (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF)); + + } /* butterfly loop end */ + + } /* groups loop end */ + + twidCoefModifier = twidCoefModifier << 1U; + } /* stages loop end */ + + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + /* loop for groups */ + for (j = 0; j < n2; j++) + { + coeff = read_q15x2 ((q15_t *)pCoef + (ia * 2U)); + + ia = ia + twidCoefModifier; + + /* loop for butterfly */ + for (i = j; i < fftLen; i += n1) + { + l = i + n2; + + T = read_q15x2 (pSrc + (2 * i)); + + S = read_q15x2 (pSrc + (2 * l)); + + R = __RV_KSUB16(T, S); + + write_q15x2 (pSrc + (2 * i), __RV_KADD16(T, S)); + + write_q15x2 (pSrc + (2 * l), R); + + } /* butterfly loop end */ + + } /* groups loop end */ + + twidCoefModifier = twidCoefModifier << 1U; + +#else /* #if defined (RISCV_MATH_DSP) */ + + uint32_t i, j, k, l; + uint32_t n1, n2, ia; + q15_t xt, yt, cosVal, sinVal; + + // N = fftLen; + n2 = fftLen; + + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + /* loop for groups */ + for (j = 0; j < n2; j++) + { + cosVal = pCoef[(ia * 2)]; + sinVal = pCoef[(ia * 2) + 1]; + ia = ia + twidCoefModifier; + + /* loop for butterfly */ + for (i = j; i < fftLen; i += n1) + { + l = i + n2; + xt = (pSrc[2 * i] >> 1U) - (pSrc[2 * l] >> 1U); + pSrc[2 * i] = ((pSrc[2 * i] >> 1U) + (pSrc[2 * l] >> 1U)) >> 1U; + + yt = (pSrc[2 * i + 1] >> 1U) - (pSrc[2 * l + 1] >> 1U); + pSrc[2 * i + 1] = ((pSrc[2 * l + 1] >> 1U) + + (pSrc[2 * i + 1] >> 1U) ) >> 1U; + + pSrc[2 * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16)) - + ((int16_t) (((q31_t) yt * sinVal) >> 16))); + + pSrc[2 * l + 1] = (((int16_t) (((q31_t) yt * cosVal) >> 16)) + + ((int16_t) (((q31_t) xt * sinVal) >> 16))); + + } /* butterfly loop end */ + + } /* groups loop end */ + + twidCoefModifier = twidCoefModifier << 1U; + + /* loop for stage */ + for (k = fftLen / 2; k > 2; k = k >> 1) + { + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + /* loop for groups */ + for (j = 0; j < n2; j++) + { + cosVal = pCoef[(ia * 2)]; + sinVal = pCoef[(ia * 2) + 1]; + ia = ia + twidCoefModifier; + + /* loop for butterfly */ + for (i = j; i < fftLen; i += n1) + { + l = i + n2; + xt = pSrc[2 * i] - pSrc[2 * l]; + pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]) >> 1U; + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]) >> 1U; + + pSrc[2 * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16)) - + ((int16_t) (((q31_t) yt * sinVal) >> 16)) ); + + pSrc[2 * l + 1] = (((int16_t) (((q31_t) yt * cosVal) >> 16)) + + ((int16_t) (((q31_t) xt * sinVal) >> 16)) ); + + } /* butterfly loop end */ + + } /* groups loop end */ + + twidCoefModifier = twidCoefModifier << 1U; + } /* stages loop end */ + + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + cosVal = pCoef[(ia * 2)]; + sinVal = pCoef[(ia * 2) + 1]; + + ia = ia + twidCoefModifier; + + /* loop for butterfly */ + for (i = 0; i < fftLen; i += n1) + { + l = i + n2; + xt = pSrc[2 * i] - pSrc[2 * l]; + pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]); + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]); + + pSrc[2 * l] = xt; + + pSrc[2 * l + 1] = yt; + + } /* groups loop end */ + + +#endif /* #if defined (RISCV_MATH_DSP) */ + +} diff --git a/components/nmsis/dsp/src/TransformFunctions/riscv_cfft_radix2_q31.c b/components/nmsis/dsp/src/TransformFunctions/riscv_cfft_radix2_q31.c new file mode 100644 index 00000000..cbf67fa3 --- /dev/null +++ b/components/nmsis/dsp/src/TransformFunctions/riscv_cfft_radix2_q31.c @@ -0,0 +1,359 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_cfft_radix2_q31.c + * Description: Radix-2 Decimation in Frequency CFFT & CIFFT Fixed point processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" + +void riscv_radix2_butterfly_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pCoef, + uint16_t twidCoefModifier); + +void riscv_radix2_butterfly_inverse_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pCoef, + uint16_t twidCoefModifier); + +void riscv_bitreversal_q31( + q31_t * pSrc, + uint32_t fftLen, + uint16_t bitRevFactor, + const uint16_t * pBitRevTab); + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Processing function for the fixed-point CFFT/CIFFT. + @deprecated Do not use this function. It has been superseded by \ref riscv_cfft_q31 and will be removed in the future. + @param[in] S points to an instance of the fixed-point CFFT/CIFFT structure + @param[in,out] pSrc points to the complex data buffer of size 2*fftLen. Processing occurs in-place + @return none + */ + +void riscv_cfft_radix2_q31( + const riscv_cfft_radix2_instance_q31 * S, + q31_t * pSrc) +{ + + if (S->ifftFlag == 1U) + { + riscv_radix2_butterfly_inverse_q31(pSrc, S->fftLen, + S->pTwiddle, S->twidCoefModifier); + } + else + { + riscv_radix2_butterfly_q31(pSrc, S->fftLen, + S->pTwiddle, S->twidCoefModifier); + } + + riscv_bitreversal_q31(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable); +} + +/** + @} end of ComplexFFT group + */ + +void riscv_radix2_butterfly_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pCoef, + uint16_t twidCoefModifier) +{ + + unsigned i, j, k, l, m; + unsigned n1, n2, ia; + q31_t xt, yt, cosVal, sinVal; + q31_t p0, p1; + + //N = fftLen; + n2 = fftLen; + + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + // loop for groups + for (i = 0; i < n2; i++) + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + ia = ia + twidCoefModifier; + + l = i + n2; + xt = (pSrc[2 * i] >> 1U) - (pSrc[2 * l] >> 1U); + yt = (pSrc[2 * i + 1] >> 1U) - (pSrc[2 * l + 1] >> 1U); +#if __RISCV_XLEN == 64 + write_q31x2 ((pSrc+2*i), (q63_t) ((q63_t)((pSrc[2 * i] >> 2U) + (pSrc[2 * l] >> 2U)) | (((q63_t)((pSrc[2 * l + 1] >> 2U) + (pSrc[2 * i + 1] >> 2U))) << 32))); +#else + pSrc[2 * i] = (pSrc[2 * i] >> 2U) + (pSrc[2 * l] >> 2U); + pSrc[2 * i + 1] = (pSrc[2 * l + 1] >> 2U) + (pSrc[2 * i + 1] >> 2U); +#endif /* __RISCV_XLEN == 64 */ + + // pSrc[2 * i] = ((pSrc[2 * i] >> 1U) + (pSrc[2 * l] >> 1U)) >> 1U; + + // pSrc[2 * i + 1] = + // ((pSrc[2 * l + 1] >> 1U) + (pSrc[2 * i + 1] >> 1U)) >> 1U; + + mult_32x32_keep32_R(p0, xt, cosVal); + mult_32x32_keep32_R(p1, yt, cosVal); + multAcc_32x32_keep32_R(p0, yt, sinVal); + multSub_32x32_keep32_R(p1, xt, sinVal); + + pSrc[2U * l] = p0; + pSrc[2U * l + 1U] = p1; + + } // groups loop end + + twidCoefModifier <<= 1U; + + // loop for stage + for (k = fftLen / 2; k > 2; k = k >> 1) + { + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + // loop for groups + for (j = 0; j < n2; j++) + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + ia = ia + twidCoefModifier; + + // loop for butterfly + i = j; + m = fftLen / n1; + do + { + l = i + n2; + xt = pSrc[2 * i] - pSrc[2 * l]; + pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]) >> 1U; + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]) >> 1U; + + mult_32x32_keep32_R(p0, xt, cosVal); + mult_32x32_keep32_R(p1, yt, cosVal); + multAcc_32x32_keep32_R(p0, yt, sinVal); + multSub_32x32_keep32_R(p1, xt, sinVal); + + pSrc[2U * l] = p0; + pSrc[2U * l + 1U] = p1; + i += n1; + m--; + } while ( m > 0); // butterfly loop end + + } // groups loop end + + twidCoefModifier <<= 1U; + } // stages loop end + + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + ia = ia + twidCoefModifier; + + // loop for butterfly + for (i = 0; i < fftLen; i += n1) + { + l = i + n2; + xt = pSrc[2 * i] - pSrc[2 * l]; + pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]); + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]); + + pSrc[2U * l] = xt; + + pSrc[2U * l + 1U] = yt; + + i += n1; + l = i + n2; + + xt = pSrc[2 * i] - pSrc[2 * l]; + pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]); + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]); + + pSrc[2U * l] = xt; + + pSrc[2U * l + 1U] = yt; + + } // butterfly loop end + +} + + +void riscv_radix2_butterfly_inverse_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pCoef, + uint16_t twidCoefModifier) +{ + + unsigned i, j, k, l; + unsigned n1, n2, ia; + q31_t xt, yt, cosVal, sinVal; + q31_t p0, p1; + + //N = fftLen; + n2 = fftLen; + + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + // loop for groups + for (i = 0; i < n2; i++) + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + ia = ia + twidCoefModifier; + + l = i + n2; + xt = (pSrc[2 * i] >> 1U) - (pSrc[2 * l] >> 1U); + yt = (pSrc[2 * i + 1] >> 1U) - (pSrc[2 * l + 1] >> 1U); +#if __RISCV_XLEN == 64 + write_q31x2 ((pSrc+2*i), (q63_t) ((q63_t)((pSrc[2 * i] >> 2U) + (pSrc[2 * l] >> 2U)) | (((q63_t)((pSrc[2 * l + 1] >> 2U) + (pSrc[2 * i + 1] >> 2U))) << 32))); +#else + pSrc[2 * i] = (pSrc[2 * i] >> 2U) + (pSrc[2 * l] >> 2U); + pSrc[2 * i + 1] = (pSrc[2 * l + 1] >> 2U) + (pSrc[2 * i + 1] >> 2U); +#endif /* __RISCV_XLEN == 64 */ + + // pSrc[2 * i] = ((pSrc[2 * i] >> 1U) + (pSrc[2 * l] >> 1U)) >> 1U; + + // pSrc[2 * i + 1] = + // ((pSrc[2 * l + 1] >> 1U) + (pSrc[2 * i + 1] >> 1U)) >> 1U; + + mult_32x32_keep32_R(p0, xt, cosVal); + mult_32x32_keep32_R(p1, yt, cosVal); + multSub_32x32_keep32_R(p0, yt, sinVal); + multAcc_32x32_keep32_R(p1, xt, sinVal); + + pSrc[2U * l] = p0; + pSrc[2U * l + 1U] = p1; + } // groups loop end + + twidCoefModifier = twidCoefModifier << 1U; + + // loop for stage + for (k = fftLen / 2; k > 2; k = k >> 1) + { + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + // loop for groups + for (j = 0; j < n2; j++) + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + ia = ia + twidCoefModifier; + + // loop for butterfly + for (i = j; i < fftLen; i += n1) + { + l = i + n2; + xt = pSrc[2 * i] - pSrc[2 * l]; + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; +#if __RISCV_XLEN == 64 + write_q31x2 ((pSrc+2*i), (q63_t) ((q63_t)((pSrc[2 * i] >> 1U) + (pSrc[2 * l] >> 1U)) | (((q63_t)((pSrc[2 * l + 1] >> 1U) + (pSrc[2 * i + 1] >> 1U))) << 32))); +#else + // pSrc[2 * i] = (pSrc[2 * i] >> 2U) + (pSrc[2 * l] >> 2U); + // pSrc[2 * i + 1] = (pSrc[2 * l + 1] >> 2U) + (pSrc[2 * i + 1] >> 2U); + + pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]) >> 1U; + + pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]) >> 1U; +#endif /* __RISCV_XLEN == 64 */ + + mult_32x32_keep32_R(p0, xt, cosVal); + mult_32x32_keep32_R(p1, yt, cosVal); + multSub_32x32_keep32_R(p0, yt, sinVal); + multAcc_32x32_keep32_R(p1, xt, sinVal); + + pSrc[2U * l] = p0; + pSrc[2U * l + 1U] = p1; + } // butterfly loop end + + } // groups loop end + + twidCoefModifier = twidCoefModifier << 1U; + } // stages loop end + + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + ia = ia + twidCoefModifier; + + // loop for butterfly + for (i = 0; i < fftLen; i += n1) + { + l = i + n2; + xt = pSrc[2 * i] - pSrc[2 * l]; + pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]); + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]); + + pSrc[2U * l] = xt; + + pSrc[2U * l + 1U] = yt; + + i += n1; + l = i + n2; + + xt = pSrc[2 * i] - pSrc[2 * l]; + pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]); + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]); + + pSrc[2U * l] = xt; + + pSrc[2U * l + 1U] = yt; + + } // butterfly loop end + +} diff --git a/components/nmsis/dsp/src/TransformFunctions/riscv_cfft_radix4_f16.c b/components/nmsis/dsp/src/TransformFunctions/riscv_cfft_radix4_f16.c new file mode 100644 index 00000000..b3a83c2a --- /dev/null +++ b/components/nmsis/dsp/src/TransformFunctions/riscv_cfft_radix4_f16.c @@ -0,0 +1,1273 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_cfft_radix4_f16.c + * Description: Radix-4 Decimation in Frequency CFFT & CIFFT Floating point processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions_f16.h" + +#if defined(RISCV_FLOAT16_SUPPORTED) + +extern void riscv_bitreversal_f16( + float16_t * pSrc, + uint16_t fftSize, + uint16_t bitRevFactor, + const uint16_t * pBitRevTab); + +void riscv_radix4_butterfly_f16( + float16_t * pSrc, + uint16_t fftLen, + const float16_t * pCoef, + uint16_t twidCoefModifier); + +void riscv_radix4_butterfly_inverse_f16( + float16_t * pSrc, + uint16_t fftLen, + const float16_t * pCoef, + uint16_t twidCoefModifier, + float16_t onebyfftLen); + + +void riscv_cfft_radix4by2_f16( + float16_t * pSrc, + uint32_t fftLen, + const float16_t * pCoef); + + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + +/* +* @brief Core function for the floating-point CFFT butterfly process. +* @param[in, out] *pSrc points to the in-place buffer of floating-point data type. +* @param[in] fftLen length of the FFT. +* @param[in] *pCoef points to the twiddle coefficient buffer. +* @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. +* @return none. +*/ + +void riscv_cfft_radix4by2_f16( + float16_t * pSrc, + uint32_t fftLen, + const float16_t * pCoef) +{ + uint32_t i, l; + uint32_t n2, ia; + float16_t xt, yt, cosVal, sinVal; + float16_t p0, p1,p2,p3,a0,a1; + + n2 = fftLen >> 1; + ia = 0; + for (i = 0; i < n2; i++) + { + cosVal = pCoef[2*ia]; + sinVal = pCoef[2*ia + 1]; + ia++; + + l = i + n2; + + /* Butterfly implementation */ + a0 = pSrc[2 * i] + pSrc[2 * l]; + xt = pSrc[2 * i] - pSrc[2 * l]; + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1]; + + p0 = xt * cosVal; + p1 = yt * sinVal; + p2 = yt * cosVal; + p3 = xt * sinVal; + + pSrc[2 * i] = a0; + pSrc[2 * i + 1] = a1; + + pSrc[2 * l] = p0 + p1; + pSrc[2 * l + 1] = p2 - p3; + + } + + // first col + riscv_radix4_butterfly_f16( pSrc, n2, (float16_t*)pCoef, 2U); + // second col + riscv_radix4_butterfly_f16( pSrc + fftLen, n2, (float16_t*)pCoef, 2U); + +} + + +/** + @brief Processing function for the floating-point Radix-4 CFFT/CIFFT. + @deprecated Do not use this function. It has been superseded by \ref riscv_cfft_f16 and will be removed in the future. + @param[in] S points to an instance of the floating-point Radix-4 CFFT/CIFFT structure + @param[in,out] pSrc points to the complex data buffer of size 2*fftLen. Processing occurs in-place + @return none + */ + +void riscv_cfft_radix4_f16( + const riscv_cfft_radix4_instance_f16 * S, + float16_t * pSrc) +{ + if (S->ifftFlag == 1U) + { + /* Complex IFFT radix-4 */ + riscv_radix4_butterfly_inverse_f16(pSrc, S->fftLen, S->pTwiddle, S->twidCoefModifier, S->onebyfftLen); + } + else + { + /* Complex FFT radix-4 */ + riscv_radix4_butterfly_f16(pSrc, S->fftLen, S->pTwiddle, S->twidCoefModifier); + } + + if (S->bitReverseFlag == 1U) + { + /* Bit Reversal */ + riscv_bitreversal_f16(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable); + } + +} + +/** + @} end of ComplexFFT group + */ + +/* ---------------------------------------------------------------------- + * Internal helper function used by the FFTs + * ---------------------------------------------------------------------- */ + +/* +* @brief Core function for the floating-point CFFT butterfly process. +* @param[in, out] *pSrc points to the in-place buffer of floating-point data type. +* @param[in] fftLen length of the FFT. +* @param[in] *pCoef points to the twiddle coefficient buffer. +* @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. +* @return none. +*/ + +void riscv_radix4_butterfly_f16( +float16_t * pSrc, +uint16_t fftLen, +const float16_t * pCoef, +uint16_t twidCoefModifier) +{ + + float16_t co1, co2, co3, si1, si2, si3; + uint32_t ia1, ia2, ia3; + uint32_t i0, i1, i2, i3; + uint32_t n1, n2, j, k; + +#if defined (RISCV_MATH_DSP) + + /* Run the below code for RISC-V Core with DSP enabled */ + + float16_t xaIn, yaIn, xbIn, ybIn, xcIn, ycIn, xdIn, ydIn; + float16_t Xaplusc, Xbplusd, Yaplusc, Ybplusd, Xaminusc, Xbminusd, Yaminusc, + Ybminusd; + float16_t Xb12C_out, Yb12C_out, Xc12C_out, Yc12C_out, Xd12C_out, Yd12C_out; + float16_t Xb12_out, Yb12_out, Xc12_out, Yc12_out, Xd12_out, Yd12_out; + float16_t *ptr1; + float16_t p0,p1,p2,p3,p4,p5; + float16_t a0,a1,a2,a3,a4,a5,a6,a7; + + /* Initializations for the first stage */ + n2 = fftLen; + n1 = n2; + + /* n2 = fftLen/4 */ + n2 >>= 2U; + i0 = 0U; + ia1 = 0U; + + j = n2; + + /* Calculation of first stage */ + do + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + xaIn = pSrc[(2U * i0)]; + yaIn = pSrc[(2U * i0) + 1U]; + + xbIn = pSrc[(2U * i1)]; + ybIn = pSrc[(2U * i1) + 1U]; + + xcIn = pSrc[(2U * i2)]; + ycIn = pSrc[(2U * i2) + 1U]; + + xdIn = pSrc[(2U * i3)]; + ydIn = pSrc[(2U * i3) + 1U]; + + /* xa + xc */ + Xaplusc = xaIn + xcIn; + /* xb + xd */ + Xbplusd = xbIn + xdIn; + /* ya + yc */ + Yaplusc = yaIn + ycIn; + /* yb + yd */ + Ybplusd = ybIn + ydIn; + + /* index calculation for the coefficients */ + ia2 = ia1 + ia1; + co2 = pCoef[ia2 * 2U]; + si2 = pCoef[(ia2 * 2U) + 1U]; + + /* xa - xc */ + Xaminusc = xaIn - xcIn; + /* xb - xd */ + Xbminusd = xbIn - xdIn; + /* ya - yc */ + Yaminusc = yaIn - ycIn; + /* yb - yd */ + Ybminusd = ybIn - ydIn; + + /* xa' = xa + xb + xc + xd */ + pSrc[(2U * i0)] = Xaplusc + Xbplusd; + /* ya' = ya + yb + yc + yd */ + pSrc[(2U * i0) + 1U] = Yaplusc + Ybplusd; + + /* (xa - xc) + (yb - yd) */ + Xb12C_out = (Xaminusc + Ybminusd); + /* (ya - yc) + (xb - xd) */ + Yb12C_out = (Yaminusc - Xbminusd); + /* (xa + xc) - (xb + xd) */ + Xc12C_out = (Xaplusc - Xbplusd); + /* (ya + yc) - (yb + yd) */ + Yc12C_out = (Yaplusc - Ybplusd); + /* (xa - xc) - (yb - yd) */ + Xd12C_out = (Xaminusc - Ybminusd); + /* (ya - yc) + (xb - xd) */ + Yd12C_out = (Xbminusd + Yaminusc); + + co1 = pCoef[ia1 * 2U]; + si1 = pCoef[(ia1 * 2U) + 1U]; + + /* index calculation for the coefficients */ + ia3 = ia2 + ia1; + co3 = pCoef[ia3 * 2U]; + si3 = pCoef[(ia3 * 2U) + 1U]; + + Xb12_out = Xb12C_out * co1; + Yb12_out = Yb12C_out * co1; + Xc12_out = Xc12C_out * co2; + Yc12_out = Yc12C_out * co2; + Xd12_out = Xd12C_out * co3; + Yd12_out = Yd12C_out * co3; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + //Xb12_out -= Yb12C_out * si1; + p0 = Yb12C_out * si1; + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + //Yb12_out += Xb12C_out * si1; + p1 = Xb12C_out * si1; + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + //Xc12_out -= Yc12C_out * si2; + p2 = Yc12C_out * si2; + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + //Yc12_out += Xc12C_out * si2; + p3 = Xc12C_out * si2; + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + //Xd12_out -= Yd12C_out * si3; + p4 = Yd12C_out * si3; + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + //Yd12_out += Xd12C_out * si3; + p5 = Xd12C_out * si3; + + Xb12_out += p0; + Yb12_out -= p1; + Xc12_out += p2; + Yc12_out -= p3; + Xd12_out += p4; + Yd12_out -= p5; + + /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = Xc12_out; + + /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = Yc12_out; + + /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = Xb12_out; + + /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = Yb12_out; + + /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = Xd12_out; + + /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = Yd12_out; + + /* Twiddle coefficients index modifier */ + ia1 += twidCoefModifier; + + /* Updating input index */ + i0++; + + } + while (--j); + + twidCoefModifier <<= 2U; + + /* Calculation of second stage to excluding last stage */ + for (k = fftLen >> 2U; k > 4U; k >>= 2U) + { + /* Initializations for the first stage */ + n1 = n2; + n2 >>= 2U; + ia1 = 0U; + + /* Calculation of first stage */ + j = 0; + do + { + /* index calculation for the coefficients */ + ia2 = ia1 + ia1; + ia3 = ia2 + ia1; + co1 = pCoef[ia1 * 2U]; + si1 = pCoef[(ia1 * 2U) + 1U]; + co2 = pCoef[ia2 * 2U]; + si2 = pCoef[(ia2 * 2U) + 1U]; + co3 = pCoef[ia3 * 2U]; + si3 = pCoef[(ia3 * 2U) + 1U]; + + /* Twiddle coefficients index modifier */ + ia1 += twidCoefModifier; + + i0 = j; + do + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + xaIn = pSrc[(2U * i0)]; + yaIn = pSrc[(2U * i0) + 1U]; + + xbIn = pSrc[(2U * i1)]; + ybIn = pSrc[(2U * i1) + 1U]; + + xcIn = pSrc[(2U * i2)]; + ycIn = pSrc[(2U * i2) + 1U]; + + xdIn = pSrc[(2U * i3)]; + ydIn = pSrc[(2U * i3) + 1U]; + + /* xa - xc */ + Xaminusc = xaIn - xcIn; + /* (xb - xd) */ + Xbminusd = xbIn - xdIn; + /* ya - yc */ + Yaminusc = yaIn - ycIn; + /* (yb - yd) */ + Ybminusd = ybIn - ydIn; + + /* xa + xc */ + Xaplusc = xaIn + xcIn; + /* xb + xd */ + Xbplusd = xbIn + xdIn; + /* ya + yc */ + Yaplusc = yaIn + ycIn; + /* yb + yd */ + Ybplusd = ybIn + ydIn; + + /* (xa - xc) + (yb - yd) */ + Xb12C_out = (Xaminusc + Ybminusd); + /* (ya - yc) - (xb - xd) */ + Yb12C_out = (Yaminusc - Xbminusd); + /* xa + xc -(xb + xd) */ + Xc12C_out = (Xaplusc - Xbplusd); + /* (ya + yc) - (yb + yd) */ + Yc12C_out = (Yaplusc - Ybplusd); + /* (xa - xc) - (yb - yd) */ + Xd12C_out = (Xaminusc - Ybminusd); + /* (ya - yc) + (xb - xd) */ + Yd12C_out = (Xbminusd + Yaminusc); + + pSrc[(2U * i0)] = Xaplusc + Xbplusd; + pSrc[(2U * i0) + 1U] = Yaplusc + Ybplusd; + + Xb12_out = Xb12C_out * co1; + Yb12_out = Yb12C_out * co1; + Xc12_out = Xc12C_out * co2; + Yc12_out = Yc12C_out * co2; + Xd12_out = Xd12C_out * co3; + Yd12_out = Yd12C_out * co3; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + //Xb12_out -= Yb12C_out * si1; + p0 = Yb12C_out * si1; + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + //Yb12_out += Xb12C_out * si1; + p1 = Xb12C_out * si1; + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + //Xc12_out -= Yc12C_out * si2; + p2 = Yc12C_out * si2; + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + //Yc12_out += Xc12C_out * si2; + p3 = Xc12C_out * si2; + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + //Xd12_out -= Yd12C_out * si3; + p4 = Yd12C_out * si3; + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + //Yd12_out += Xd12C_out * si3; + p5 = Xd12C_out * si3; + + Xb12_out += p0; + Yb12_out -= p1; + Xc12_out += p2; + Yc12_out -= p3; + Xd12_out += p4; + Yd12_out -= p5; + + /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = Xc12_out; + + /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = Yc12_out; + + /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = Xb12_out; + + /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = Yb12_out; + + /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = Xd12_out; + + /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = Yd12_out; + + i0 += n1; + } while (i0 < fftLen); + j++; + } while (j <= (n2 - 1U)); + twidCoefModifier <<= 2U; + } + + j = fftLen >> 2; + ptr1 = &pSrc[0]; + + /* Calculations of last stage */ + do + { + xaIn = ptr1[0]; + yaIn = ptr1[1]; + xbIn = ptr1[2]; + ybIn = ptr1[3]; + xcIn = ptr1[4]; + ycIn = ptr1[5]; + xdIn = ptr1[6]; + ydIn = ptr1[7]; + + /* xa + xc */ + Xaplusc = xaIn + xcIn; + + /* xa - xc */ + Xaminusc = xaIn - xcIn; + + /* ya + yc */ + Yaplusc = yaIn + ycIn; + + /* ya - yc */ + Yaminusc = yaIn - ycIn; + + /* xb + xd */ + Xbplusd = xbIn + xdIn; + + /* yb + yd */ + Ybplusd = ybIn + ydIn; + + /* (xb-xd) */ + Xbminusd = xbIn - xdIn; + + /* (yb-yd) */ + Ybminusd = ybIn - ydIn; + + /* xa' = xa + xb + xc + xd */ + a0 = (Xaplusc + Xbplusd); + /* ya' = ya + yb + yc + yd */ + a1 = (Yaplusc + Ybplusd); + /* xc' = (xa-xb+xc-xd) */ + a2 = (Xaplusc - Xbplusd); + /* yc' = (ya-yb+yc-yd) */ + a3 = (Yaplusc - Ybplusd); + /* xb' = (xa+yb-xc-yd) */ + a4 = (Xaminusc + Ybminusd); + /* yb' = (ya-xb-yc+xd) */ + a5 = (Yaminusc - Xbminusd); + /* xd' = (xa-yb-xc+yd)) */ + a6 = (Xaminusc - Ybminusd); + /* yd' = (ya+xb-yc-xd) */ + a7 = (Xbminusd + Yaminusc); + + ptr1[0] = a0; + ptr1[1] = a1; + ptr1[2] = a2; + ptr1[3] = a3; + ptr1[4] = a4; + ptr1[5] = a5; + ptr1[6] = a6; + ptr1[7] = a7; + + /* increment pointer by 8 */ + ptr1 += 8U; + } while (--j); + +#else + + float16_t t1, t2, r1, r2, s1, s2; + + /* Run the below code for RISC-V Core without DSP */ + + /* Initializations for the fft calculation */ + n2 = fftLen; + n1 = n2; + for (k = fftLen; k > 1U; k >>= 2U) + { + /* Initializations for the fft calculation */ + n1 = n2; + n2 >>= 2U; + ia1 = 0U; + + /* FFT Calculation */ + j = 0; + do + { + /* index calculation for the coefficients */ + ia2 = ia1 + ia1; + ia3 = ia2 + ia1; + co1 = pCoef[ia1 * 2U]; + si1 = pCoef[(ia1 * 2U) + 1U]; + co2 = pCoef[ia2 * 2U]; + si2 = pCoef[(ia2 * 2U) + 1U]; + co3 = pCoef[ia3 * 2U]; + si3 = pCoef[(ia3 * 2U) + 1U]; + + /* Twiddle coefficients index modifier */ + ia1 = ia1 + twidCoefModifier; + + i0 = j; + do + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* xa + xc */ + r1 = pSrc[(2U * i0)] + pSrc[(2U * i2)]; + + /* xa - xc */ + r2 = pSrc[(2U * i0)] - pSrc[(2U * i2)]; + + /* ya + yc */ + s1 = pSrc[(2U * i0) + 1U] + pSrc[(2U * i2) + 1U]; + + /* ya - yc */ + s2 = pSrc[(2U * i0) + 1U] - pSrc[(2U * i2) + 1U]; + + /* xb + xd */ + t1 = pSrc[2U * i1] + pSrc[2U * i3]; + + /* xa' = xa + xb + xc + xd */ + pSrc[2U * i0] = r1 + t1; + + /* xa + xc -(xb + xd) */ + r1 = r1 - t1; + + /* yb + yd */ + t2 = pSrc[(2U * i1) + 1U] + pSrc[(2U * i3) + 1U]; + + /* ya' = ya + yb + yc + yd */ + pSrc[(2U * i0) + 1U] = s1 + t2; + + /* (ya + yc) - (yb + yd) */ + s1 = s1 - t2; + + /* (yb - yd) */ + t1 = pSrc[(2U * i1) + 1U] - pSrc[(2U * i3) + 1U]; + + /* (xb - xd) */ + t2 = pSrc[2U * i1] - pSrc[2U * i3]; + + /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = (r1 * co2) + (s1 * si2); + + /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = (s1 * co2) - (r1 * si2); + + /* (xa - xc) + (yb - yd) */ + r1 = r2 + t1; + + /* (xa - xc) - (yb - yd) */ + r2 = r2 - t1; + + /* (ya - yc) - (xb - xd) */ + s1 = s2 - t2; + + /* (ya - yc) + (xb - xd) */ + s2 = s2 + t2; + + /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = (r1 * co1) + (s1 * si1); + + /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = (s1 * co1) - (r1 * si1); + + /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = (r2 * co3) + (s2 * si3); + + /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = (s2 * co3) - (r2 * si3); + + i0 += n1; + } while ( i0 < fftLen); + j++; + } while (j <= (n2 - 1U)); + twidCoefModifier <<= 2U; + } + +#endif /* #if defined (RISCV_MATH_DSP) */ + +} + +/* +* @brief Core function for the floating-point CIFFT butterfly process. +* @param[in, out] *pSrc points to the in-place buffer of floating-point data type. +* @param[in] fftLen length of the FFT. +* @param[in] *pCoef points to twiddle coefficient buffer. +* @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. +* @param[in] onebyfftLen value of 1/fftLen. +* @return none. +*/ + +void riscv_radix4_butterfly_inverse_f16( +float16_t * pSrc, +uint16_t fftLen, +const float16_t * pCoef, +uint16_t twidCoefModifier, +float16_t onebyfftLen) +{ + float16_t co1, co2, co3, si1, si2, si3; + uint32_t ia1, ia2, ia3; + uint32_t i0, i1, i2, i3; + uint32_t n1, n2, j, k; + +#if defined (RISCV_MATH_DSP) + + float16_t xaIn, yaIn, xbIn, ybIn, xcIn, ycIn, xdIn, ydIn; + float16_t Xaplusc, Xbplusd, Yaplusc, Ybplusd, Xaminusc, Xbminusd, Yaminusc, + Ybminusd; + float16_t Xb12C_out, Yb12C_out, Xc12C_out, Yc12C_out, Xd12C_out, Yd12C_out; + float16_t Xb12_out, Yb12_out, Xc12_out, Yc12_out, Xd12_out, Yd12_out; + float16_t *ptr1; + float16_t p0,p1,p2,p3,p4,p5,p6,p7; + float16_t a0,a1,a2,a3,a4,a5,a6,a7; + + + /* Initializations for the first stage */ + n2 = fftLen; + n1 = n2; + + /* n2 = fftLen/4 */ + n2 >>= 2U; + i0 = 0U; + ia1 = 0U; + + j = n2; + + /* Calculation of first stage */ + do + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* Butterfly implementation */ + xaIn = pSrc[(2U * i0)]; + yaIn = pSrc[(2U * i0) + 1U]; + + xcIn = pSrc[(2U * i2)]; + ycIn = pSrc[(2U * i2) + 1U]; + + xbIn = pSrc[(2U * i1)]; + ybIn = pSrc[(2U * i1) + 1U]; + + xdIn = pSrc[(2U * i3)]; + ydIn = pSrc[(2U * i3) + 1U]; + + /* xa + xc */ + Xaplusc = xaIn + xcIn; + /* xb + xd */ + Xbplusd = xbIn + xdIn; + /* ya + yc */ + Yaplusc = yaIn + ycIn; + /* yb + yd */ + Ybplusd = ybIn + ydIn; + + /* index calculation for the coefficients */ + ia2 = ia1 + ia1; + co2 = pCoef[ia2 * 2U]; + si2 = pCoef[(ia2 * 2U) + 1U]; + + /* xa - xc */ + Xaminusc = xaIn - xcIn; + /* xb - xd */ + Xbminusd = xbIn - xdIn; + /* ya - yc */ + Yaminusc = yaIn - ycIn; + /* yb - yd */ + Ybminusd = ybIn - ydIn; + + /* xa' = xa + xb + xc + xd */ + pSrc[(2U * i0)] = Xaplusc + Xbplusd; + + /* ya' = ya + yb + yc + yd */ + pSrc[(2U * i0) + 1U] = Yaplusc + Ybplusd; + + /* (xa - xc) - (yb - yd) */ + Xb12C_out = (Xaminusc - Ybminusd); + /* (ya - yc) + (xb - xd) */ + Yb12C_out = (Yaminusc + Xbminusd); + /* (xa + xc) - (xb + xd) */ + Xc12C_out = (Xaplusc - Xbplusd); + /* (ya + yc) - (yb + yd) */ + Yc12C_out = (Yaplusc - Ybplusd); + /* (xa - xc) + (yb - yd) */ + Xd12C_out = (Xaminusc + Ybminusd); + /* (ya - yc) - (xb - xd) */ + Yd12C_out = (Yaminusc - Xbminusd); + + co1 = pCoef[ia1 * 2U]; + si1 = pCoef[(ia1 * 2U) + 1U]; + + /* index calculation for the coefficients */ + ia3 = ia2 + ia1; + co3 = pCoef[ia3 * 2U]; + si3 = pCoef[(ia3 * 2U) + 1U]; + + Xb12_out = Xb12C_out * co1; + Yb12_out = Yb12C_out * co1; + Xc12_out = Xc12C_out * co2; + Yc12_out = Yc12C_out * co2; + Xd12_out = Xd12C_out * co3; + Yd12_out = Yd12C_out * co3; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + //Xb12_out -= Yb12C_out * si1; + p0 = Yb12C_out * si1; + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + //Yb12_out += Xb12C_out * si1; + p1 = Xb12C_out * si1; + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + //Xc12_out -= Yc12C_out * si2; + p2 = Yc12C_out * si2; + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + //Yc12_out += Xc12C_out * si2; + p3 = Xc12C_out * si2; + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + //Xd12_out -= Yd12C_out * si3; + p4 = Yd12C_out * si3; + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + //Yd12_out += Xd12C_out * si3; + p5 = Xd12C_out * si3; + + Xb12_out -= p0; + Yb12_out += p1; + Xc12_out -= p2; + Yc12_out += p3; + Xd12_out -= p4; + Yd12_out += p5; + + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = Xc12_out; + + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = Yc12_out; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = Xb12_out; + + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = Yb12_out; + + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = Xd12_out; + + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = Yd12_out; + + /* Twiddle coefficients index modifier */ + ia1 = ia1 + twidCoefModifier; + + /* Updating input index */ + i0 = i0 + 1U; + + } while (--j); + + twidCoefModifier <<= 2U; + + /* Calculation of second stage to excluding last stage */ + for (k = fftLen >> 2U; k > 4U; k >>= 2U) + { + /* Initializations for the first stage */ + n1 = n2; + n2 >>= 2U; + ia1 = 0U; + + /* Calculation of first stage */ + j = 0; + do + { + /* index calculation for the coefficients */ + ia2 = ia1 + ia1; + ia3 = ia2 + ia1; + co1 = pCoef[ia1 * 2U]; + si1 = pCoef[(ia1 * 2U) + 1U]; + co2 = pCoef[ia2 * 2U]; + si2 = pCoef[(ia2 * 2U) + 1U]; + co3 = pCoef[ia3 * 2U]; + si3 = pCoef[(ia3 * 2U) + 1U]; + + /* Twiddle coefficients index modifier */ + ia1 = ia1 + twidCoefModifier; + + i0 = j; + do + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + xaIn = pSrc[(2U * i0)]; + yaIn = pSrc[(2U * i0) + 1U]; + + xbIn = pSrc[(2U * i1)]; + ybIn = pSrc[(2U * i1) + 1U]; + + xcIn = pSrc[(2U * i2)]; + ycIn = pSrc[(2U * i2) + 1U]; + + xdIn = pSrc[(2U * i3)]; + ydIn = pSrc[(2U * i3) + 1U]; + + /* xa - xc */ + Xaminusc = xaIn - xcIn; + /* (xb - xd) */ + Xbminusd = xbIn - xdIn; + /* ya - yc */ + Yaminusc = yaIn - ycIn; + /* (yb - yd) */ + Ybminusd = ybIn - ydIn; + + /* xa + xc */ + Xaplusc = xaIn + xcIn; + /* xb + xd */ + Xbplusd = xbIn + xdIn; + /* ya + yc */ + Yaplusc = yaIn + ycIn; + /* yb + yd */ + Ybplusd = ybIn + ydIn; + + /* (xa - xc) - (yb - yd) */ + Xb12C_out = (Xaminusc - Ybminusd); + /* (ya - yc) + (xb - xd) */ + Yb12C_out = (Yaminusc + Xbminusd); + /* xa + xc -(xb + xd) */ + Xc12C_out = (Xaplusc - Xbplusd); + /* (ya + yc) - (yb + yd) */ + Yc12C_out = (Yaplusc - Ybplusd); + /* (xa - xc) + (yb - yd) */ + Xd12C_out = (Xaminusc + Ybminusd); + /* (ya - yc) - (xb - xd) */ + Yd12C_out = (Yaminusc - Xbminusd); + + pSrc[(2U * i0)] = Xaplusc + Xbplusd; + pSrc[(2U * i0) + 1U] = Yaplusc + Ybplusd; + + Xb12_out = Xb12C_out * co1; + Yb12_out = Yb12C_out * co1; + Xc12_out = Xc12C_out * co2; + Yc12_out = Yc12C_out * co2; + Xd12_out = Xd12C_out * co3; + Yd12_out = Yd12C_out * co3; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + //Xb12_out -= Yb12C_out * si1; + p0 = Yb12C_out * si1; + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + //Yb12_out += Xb12C_out * si1; + p1 = Xb12C_out * si1; + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + //Xc12_out -= Yc12C_out * si2; + p2 = Yc12C_out * si2; + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + //Yc12_out += Xc12C_out * si2; + p3 = Xc12C_out * si2; + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + //Xd12_out -= Yd12C_out * si3; + p4 = Yd12C_out * si3; + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + //Yd12_out += Xd12C_out * si3; + p5 = Xd12C_out * si3; + + Xb12_out -= p0; + Yb12_out += p1; + Xc12_out -= p2; + Yc12_out += p3; + Xd12_out -= p4; + Yd12_out += p5; + + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = Xc12_out; + + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = Yc12_out; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = Xb12_out; + + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = Yb12_out; + + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = Xd12_out; + + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = Yd12_out; + + i0 += n1; + } while (i0 < fftLen); + j++; + } while (j <= (n2 - 1U)); + twidCoefModifier <<= 2U; + } + /* Initializations of last stage */ + + j = fftLen >> 2; + ptr1 = &pSrc[0]; + + /* Calculations of last stage */ + do + { + xaIn = ptr1[0]; + yaIn = ptr1[1]; + xbIn = ptr1[2]; + ybIn = ptr1[3]; + xcIn = ptr1[4]; + ycIn = ptr1[5]; + xdIn = ptr1[6]; + ydIn = ptr1[7]; + + /* Butterfly implementation */ + /* xa + xc */ + Xaplusc = xaIn + xcIn; + + /* xa - xc */ + Xaminusc = xaIn - xcIn; + + /* ya + yc */ + Yaplusc = yaIn + ycIn; + + /* ya - yc */ + Yaminusc = yaIn - ycIn; + + /* xb + xd */ + Xbplusd = xbIn + xdIn; + + /* yb + yd */ + Ybplusd = ybIn + ydIn; + + /* (xb-xd) */ + Xbminusd = xbIn - xdIn; + + /* (yb-yd) */ + Ybminusd = ybIn - ydIn; + + /* xa' = (xa+xb+xc+xd) * onebyfftLen */ + a0 = (Xaplusc + Xbplusd); + /* ya' = (ya+yb+yc+yd) * onebyfftLen */ + a1 = (Yaplusc + Ybplusd); + /* xc' = (xa-xb+xc-xd) * onebyfftLen */ + a2 = (Xaplusc - Xbplusd); + /* yc' = (ya-yb+yc-yd) * onebyfftLen */ + a3 = (Yaplusc - Ybplusd); + /* xb' = (xa-yb-xc+yd) * onebyfftLen */ + a4 = (Xaminusc - Ybminusd); + /* yb' = (ya+xb-yc-xd) * onebyfftLen */ + a5 = (Yaminusc + Xbminusd); + /* xd' = (xa-yb-xc+yd) * onebyfftLen */ + a6 = (Xaminusc + Ybminusd); + /* yd' = (ya-xb-yc+xd) * onebyfftLen */ + a7 = (Yaminusc - Xbminusd); + + p0 = a0 * onebyfftLen; + p1 = a1 * onebyfftLen; + p2 = a2 * onebyfftLen; + p3 = a3 * onebyfftLen; + p4 = a4 * onebyfftLen; + p5 = a5 * onebyfftLen; + p6 = a6 * onebyfftLen; + p7 = a7 * onebyfftLen; + + /* xa' = (xa+xb+xc+xd) * onebyfftLen */ + ptr1[0] = p0; + /* ya' = (ya+yb+yc+yd) * onebyfftLen */ + ptr1[1] = p1; + /* xc' = (xa-xb+xc-xd) * onebyfftLen */ + ptr1[2] = p2; + /* yc' = (ya-yb+yc-yd) * onebyfftLen */ + ptr1[3] = p3; + /* xb' = (xa-yb-xc+yd) * onebyfftLen */ + ptr1[4] = p4; + /* yb' = (ya+xb-yc-xd) * onebyfftLen */ + ptr1[5] = p5; + /* xd' = (xa-yb-xc+yd) * onebyfftLen */ + ptr1[6] = p6; + /* yd' = (ya-xb-yc+xd) * onebyfftLen */ + ptr1[7] = p7; + + /* increment source pointer by 8 for next calculations */ + ptr1 = ptr1 + 8U; + + } while (--j); + +#else + + float16_t t1, t2, r1, r2, s1, s2; + + /* Run the below code for RISC-V Core without DSP */ + + /* Initializations for the first stage */ + n2 = fftLen; + n1 = n2; + + /* Calculation of first stage */ + for (k = fftLen; k > 4U; k >>= 2U) + { + /* Initializations for the first stage */ + n1 = n2; + n2 >>= 2U; + ia1 = 0U; + + /* Calculation of first stage */ + j = 0; + do + { + /* index calculation for the coefficients */ + ia2 = ia1 + ia1; + ia3 = ia2 + ia1; + co1 = pCoef[ia1 * 2U]; + si1 = pCoef[(ia1 * 2U) + 1U]; + co2 = pCoef[ia2 * 2U]; + si2 = pCoef[(ia2 * 2U) + 1U]; + co3 = pCoef[ia3 * 2U]; + si3 = pCoef[(ia3 * 2U) + 1U]; + + /* Twiddle coefficients index modifier */ + ia1 = ia1 + twidCoefModifier; + + i0 = j; + do + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* xa + xc */ + r1 = pSrc[(2U * i0)] + pSrc[(2U * i2)]; + + /* xa - xc */ + r2 = pSrc[(2U * i0)] - pSrc[(2U * i2)]; + + /* ya + yc */ + s1 = pSrc[(2U * i0) + 1U] + pSrc[(2U * i2) + 1U]; + + /* ya - yc */ + s2 = pSrc[(2U * i0) + 1U] - pSrc[(2U * i2) + 1U]; + + /* xb + xd */ + t1 = pSrc[2U * i1] + pSrc[2U * i3]; + + /* xa' = xa + xb + xc + xd */ + pSrc[2U * i0] = r1 + t1; + + /* xa + xc -(xb + xd) */ + r1 = r1 - t1; + + /* yb + yd */ + t2 = pSrc[(2U * i1) + 1U] + pSrc[(2U * i3) + 1U]; + + /* ya' = ya + yb + yc + yd */ + pSrc[(2U * i0) + 1U] = s1 + t2; + + /* (ya + yc) - (yb + yd) */ + s1 = s1 - t2; + + /* (yb - yd) */ + t1 = pSrc[(2U * i1) + 1U] - pSrc[(2U * i3) + 1U]; + + /* (xb - xd) */ + t2 = pSrc[2U * i1] - pSrc[2U * i3]; + + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = (r1 * co2) - (s1 * si2); + + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = (s1 * co2) + (r1 * si2); + + /* (xa - xc) - (yb - yd) */ + r1 = r2 - t1; + + /* (xa - xc) + (yb - yd) */ + r2 = r2 + t1; + + /* (ya - yc) + (xb - xd) */ + s1 = s2 + t2; + + /* (ya - yc) - (xb - xd) */ + s2 = s2 - t2; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = (r1 * co1) - (s1 * si1); + + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = (s1 * co1) + (r1 * si1); + + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = (r2 * co3) - (s2 * si3); + + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = (s2 * co3) + (r2 * si3); + + i0 += n1; + } while ( i0 < fftLen); + j++; + } while (j <= (n2 - 1U)); + twidCoefModifier <<= 2U; + } + /* Initializations of last stage */ + n1 = n2; + n2 >>= 2U; + + /* Calculations of last stage */ + for (i0 = 0U; i0 <= (fftLen - n1); i0 += n1) + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* Butterfly implementation */ + /* xa + xc */ + r1 = pSrc[2U * i0] + pSrc[2U * i2]; + + /* xa - xc */ + r2 = pSrc[2U * i0] - pSrc[2U * i2]; + + /* ya + yc */ + s1 = pSrc[(2U * i0) + 1U] + pSrc[(2U * i2) + 1U]; + + /* ya - yc */ + s2 = pSrc[(2U * i0) + 1U] - pSrc[(2U * i2) + 1U]; + + /* xc + xd */ + t1 = pSrc[2U * i1] + pSrc[2U * i3]; + + /* xa' = xa + xb + xc + xd */ + pSrc[2U * i0] = (r1 + t1) * onebyfftLen; + + /* (xa + xb) - (xc + xd) */ + r1 = r1 - t1; + + /* yb + yd */ + t2 = pSrc[(2U * i1) + 1U] + pSrc[(2U * i3) + 1U]; + + /* ya' = ya + yb + yc + yd */ + pSrc[(2U * i0) + 1U] = (s1 + t2) * onebyfftLen; + + /* (ya + yc) - (yb + yd) */ + s1 = s1 - t2; + + /* (yb-yd) */ + t1 = pSrc[(2U * i1) + 1U] - pSrc[(2U * i3) + 1U]; + + /* (xb-xd) */ + t2 = pSrc[2U * i1] - pSrc[2U * i3]; + + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = r1 * onebyfftLen; + + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = s1 * onebyfftLen; + + /* (xa - xc) - (yb-yd) */ + r1 = r2 - t1; + + /* (xa - xc) + (yb-yd) */ + r2 = r2 + t1; + + /* (ya - yc) + (xb-xd) */ + s1 = s2 + t2; + + /* (ya - yc) - (xb-xd) */ + s2 = s2 - t2; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = r1 * onebyfftLen; + + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = s1 * onebyfftLen; + + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = r2 * onebyfftLen; + + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = s2 * onebyfftLen; + } + +#endif /* #if defined (RISCV_MATH_DSP) */ +} + +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ diff --git a/components/nmsis/dsp/src/TransformFunctions/riscv_cfft_radix4_f32.c b/components/nmsis/dsp/src/TransformFunctions/riscv_cfft_radix4_f32.c new file mode 100644 index 00000000..dd4ed629 --- /dev/null +++ b/components/nmsis/dsp/src/TransformFunctions/riscv_cfft_radix4_f32.c @@ -0,0 +1,1204 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_cfft_radix4_f32.c + * Description: Radix-4 Decimation in Frequency CFFT & CIFFT Floating point processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" + +extern void riscv_bitreversal_f32( + float32_t * pSrc, + uint16_t fftSize, + uint16_t bitRevFactor, + const uint16_t * pBitRevTab); + +void riscv_radix4_butterfly_f32( + float32_t * pSrc, + uint16_t fftLen, + const float32_t * pCoef, + uint16_t twidCoefModifier); + +void riscv_radix4_butterfly_inverse_f32( + float32_t * pSrc, + uint16_t fftLen, + const float32_t * pCoef, + uint16_t twidCoefModifier, + float32_t onebyfftLen); + + + + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + + +/** + @brief Processing function for the floating-point Radix-4 CFFT/CIFFT. + @deprecated Do not use this function. It has been superseded by \ref riscv_cfft_f32 and will be removed in the future. + @param[in] S points to an instance of the floating-point Radix-4 CFFT/CIFFT structure + @param[in,out] pSrc points to the complex data buffer of size 2*fftLen. Processing occurs in-place + @return none + */ + +void riscv_cfft_radix4_f32( + const riscv_cfft_radix4_instance_f32 * S, + float32_t * pSrc) +{ + if (S->ifftFlag == 1U) + { + /* Complex IFFT radix-4 */ + riscv_radix4_butterfly_inverse_f32(pSrc, S->fftLen, S->pTwiddle, S->twidCoefModifier, S->onebyfftLen); + } + else + { + /* Complex FFT radix-4 */ + riscv_radix4_butterfly_f32(pSrc, S->fftLen, S->pTwiddle, S->twidCoefModifier); + } + + if (S->bitReverseFlag == 1U) + { + /* Bit Reversal */ + riscv_bitreversal_f32(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable); + } + +} + +/** + @} end of ComplexFFT group + */ + +/* ---------------------------------------------------------------------- + * Internal helper function used by the FFTs + * ---------------------------------------------------------------------- */ + +/** + brief Core function for the floating-point CFFT butterfly process. + param[in,out] pSrc points to the in-place buffer of floating-point data type + param[in] fftLen length of the FFT + param[in] pCoef points to the twiddle coefficient buffer + param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table + return none + */ + +void riscv_radix4_butterfly_f32( + float32_t * pSrc, + uint16_t fftLen, + const float32_t * pCoef, + uint16_t twidCoefModifier) +{ + float32_t co1, co2, co3, si1, si2, si3; + uint32_t ia1, ia2, ia3; + uint32_t i0, i1, i2, i3; + uint32_t n1, n2, j, k; + +#if defined (RISCV_MATH_LOOPUNROLL) + + float32_t xaIn, yaIn, xbIn, ybIn, xcIn, ycIn, xdIn, ydIn; + float32_t Xaplusc, Xbplusd, Yaplusc, Ybplusd, Xaminusc, Xbminusd, Yaminusc, + Ybminusd; + float32_t Xb12C_out, Yb12C_out, Xc12C_out, Yc12C_out, Xd12C_out, Yd12C_out; + float32_t Xb12_out, Yb12_out, Xc12_out, Yc12_out, Xd12_out, Yd12_out; + float32_t *ptr1; + float32_t p0,p1,p2,p3,p4,p5; + float32_t a0,a1,a2,a3,a4,a5,a6,a7; + + /* Initializations for the first stage */ + n2 = fftLen; + n1 = n2; + + /* n2 = fftLen/4 */ + n2 >>= 2U; + i0 = 0U; + ia1 = 0U; + + j = n2; + + /* Calculation of first stage */ + do + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + xaIn = pSrc[(2U * i0)]; + yaIn = pSrc[(2U * i0) + 1U]; + + xbIn = pSrc[(2U * i1)]; + ybIn = pSrc[(2U * i1) + 1U]; + + xcIn = pSrc[(2U * i2)]; + ycIn = pSrc[(2U * i2) + 1U]; + + xdIn = pSrc[(2U * i3)]; + ydIn = pSrc[(2U * i3) + 1U]; + + /* xa + xc */ + Xaplusc = xaIn + xcIn; + /* xb + xd */ + Xbplusd = xbIn + xdIn; + /* ya + yc */ + Yaplusc = yaIn + ycIn; + /* yb + yd */ + Ybplusd = ybIn + ydIn; + + /* index calculation for the coefficients */ + ia2 = ia1 + ia1; + co2 = pCoef[ia2 * 2U]; + si2 = pCoef[(ia2 * 2U) + 1U]; + + /* xa - xc */ + Xaminusc = xaIn - xcIn; + /* xb - xd */ + Xbminusd = xbIn - xdIn; + /* ya - yc */ + Yaminusc = yaIn - ycIn; + /* yb - yd */ + Ybminusd = ybIn - ydIn; + + /* xa' = xa + xb + xc + xd */ + pSrc[(2U * i0)] = Xaplusc + Xbplusd; + /* ya' = ya + yb + yc + yd */ + pSrc[(2U * i0) + 1U] = Yaplusc + Ybplusd; + + /* (xa - xc) + (yb - yd) */ + Xb12C_out = (Xaminusc + Ybminusd); + /* (ya - yc) + (xb - xd) */ + Yb12C_out = (Yaminusc - Xbminusd); + /* (xa + xc) - (xb + xd) */ + Xc12C_out = (Xaplusc - Xbplusd); + /* (ya + yc) - (yb + yd) */ + Yc12C_out = (Yaplusc - Ybplusd); + /* (xa - xc) - (yb - yd) */ + Xd12C_out = (Xaminusc - Ybminusd); + /* (ya - yc) + (xb - xd) */ + Yd12C_out = (Xbminusd + Yaminusc); + + co1 = pCoef[ia1 * 2U]; + si1 = pCoef[(ia1 * 2U) + 1U]; + + /* index calculation for the coefficients */ + ia3 = ia2 + ia1; + co3 = pCoef[ia3 * 2U]; + si3 = pCoef[(ia3 * 2U) + 1U]; + + Xb12_out = Xb12C_out * co1; + Yb12_out = Yb12C_out * co1; + Xc12_out = Xc12C_out * co2; + Yc12_out = Yc12C_out * co2; + Xd12_out = Xd12C_out * co3; + Yd12_out = Yd12C_out * co3; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + //Xb12_out -= Yb12C_out * si1; + p0 = Yb12C_out * si1; + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + //Yb12_out += Xb12C_out * si1; + p1 = Xb12C_out * si1; + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + //Xc12_out -= Yc12C_out * si2; + p2 = Yc12C_out * si2; + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + //Yc12_out += Xc12C_out * si2; + p3 = Xc12C_out * si2; + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + //Xd12_out -= Yd12C_out * si3; + p4 = Yd12C_out * si3; + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + //Yd12_out += Xd12C_out * si3; + p5 = Xd12C_out * si3; + + Xb12_out += p0; + Yb12_out -= p1; + Xc12_out += p2; + Yc12_out -= p3; + Xd12_out += p4; + Yd12_out -= p5; + + /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = Xc12_out; + + /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = Yc12_out; + + /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = Xb12_out; + + /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = Yb12_out; + + /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = Xd12_out; + + /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = Yd12_out; + + /* Twiddle coefficients index modifier */ + ia1 += twidCoefModifier; + + /* Updating input index */ + i0++; + + } + while (--j); + + twidCoefModifier <<= 2U; + + /* Calculation of second stage to excluding last stage */ + for (k = fftLen >> 2U; k > 4U; k >>= 2U) + { + /* Initializations for the first stage */ + n1 = n2; + n2 >>= 2U; + ia1 = 0U; + + /* Calculation of first stage */ + j = 0; + do + { + /* index calculation for the coefficients */ + ia2 = ia1 + ia1; + ia3 = ia2 + ia1; + co1 = pCoef[(ia1 * 2U)]; + si1 = pCoef[(ia1 * 2U) + 1U]; + co2 = pCoef[(ia2 * 2U)]; + si2 = pCoef[(ia2 * 2U) + 1U]; + co3 = pCoef[(ia3 * 2U)]; + si3 = pCoef[(ia3 * 2U) + 1U]; + + /* Twiddle coefficients index modifier */ + ia1 += twidCoefModifier; + + i0 = j; + do + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + xaIn = pSrc[(2U * i0)]; + yaIn = pSrc[(2U * i0) + 1U]; + + xbIn = pSrc[(2U * i1)]; + ybIn = pSrc[(2U * i1) + 1U]; + + xcIn = pSrc[(2U * i2)]; + ycIn = pSrc[(2U * i2) + 1U]; + + xdIn = pSrc[(2U * i3)]; + ydIn = pSrc[(2U * i3) + 1U]; + + /* xa - xc */ + Xaminusc = xaIn - xcIn; + /* (xb - xd) */ + Xbminusd = xbIn - xdIn; + /* ya - yc */ + Yaminusc = yaIn - ycIn; + /* (yb - yd) */ + Ybminusd = ybIn - ydIn; + + /* xa + xc */ + Xaplusc = xaIn + xcIn; + /* xb + xd */ + Xbplusd = xbIn + xdIn; + /* ya + yc */ + Yaplusc = yaIn + ycIn; + /* yb + yd */ + Ybplusd = ybIn + ydIn; + + /* (xa - xc) + (yb - yd) */ + Xb12C_out = (Xaminusc + Ybminusd); + /* (ya - yc) - (xb - xd) */ + Yb12C_out = (Yaminusc - Xbminusd); + /* xa + xc -(xb + xd) */ + Xc12C_out = (Xaplusc - Xbplusd); + /* (ya + yc) - (yb + yd) */ + Yc12C_out = (Yaplusc - Ybplusd); + /* (xa - xc) - (yb - yd) */ + Xd12C_out = (Xaminusc - Ybminusd); + /* (ya - yc) + (xb - xd) */ + Yd12C_out = (Xbminusd + Yaminusc); + + pSrc[(2U * i0)] = Xaplusc + Xbplusd; + pSrc[(2U * i0) + 1U] = Yaplusc + Ybplusd; + + Xb12_out = Xb12C_out * co1; + Yb12_out = Yb12C_out * co1; + Xc12_out = Xc12C_out * co2; + Yc12_out = Yc12C_out * co2; + Xd12_out = Xd12C_out * co3; + Yd12_out = Yd12C_out * co3; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + //Xb12_out -= Yb12C_out * si1; + p0 = Yb12C_out * si1; + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + //Yb12_out += Xb12C_out * si1; + p1 = Xb12C_out * si1; + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + //Xc12_out -= Yc12C_out * si2; + p2 = Yc12C_out * si2; + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + //Yc12_out += Xc12C_out * si2; + p3 = Xc12C_out * si2; + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + //Xd12_out -= Yd12C_out * si3; + p4 = Yd12C_out * si3; + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + //Yd12_out += Xd12C_out * si3; + p5 = Xd12C_out * si3; + + Xb12_out += p0; + Yb12_out -= p1; + Xc12_out += p2; + Yc12_out -= p3; + Xd12_out += p4; + Yd12_out -= p5; + + /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = Xc12_out; + + /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = Yc12_out; + + /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = Xb12_out; + + /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = Yb12_out; + + /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = Xd12_out; + + /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = Yd12_out; + + i0 += n1; + } while (i0 < fftLen); + j++; + } while (j <= (n2 - 1U)); + twidCoefModifier <<= 2U; + } + + j = fftLen >> 2; + ptr1 = &pSrc[0]; + + /* Calculations of last stage */ + do + { + xaIn = ptr1[0]; + yaIn = ptr1[1]; + xbIn = ptr1[2]; + ybIn = ptr1[3]; + xcIn = ptr1[4]; + ycIn = ptr1[5]; + xdIn = ptr1[6]; + ydIn = ptr1[7]; + + /* xa + xc */ + Xaplusc = xaIn + xcIn; + + /* xa - xc */ + Xaminusc = xaIn - xcIn; + + /* ya + yc */ + Yaplusc = yaIn + ycIn; + + /* ya - yc */ + Yaminusc = yaIn - ycIn; + + /* xb + xd */ + Xbplusd = xbIn + xdIn; + + /* yb + yd */ + Ybplusd = ybIn + ydIn; + + /* (xb-xd) */ + Xbminusd = xbIn - xdIn; + + /* (yb-yd) */ + Ybminusd = ybIn - ydIn; + + /* xa' = xa + xb + xc + xd */ + a0 = (Xaplusc + Xbplusd); + /* ya' = ya + yb + yc + yd */ + a1 = (Yaplusc + Ybplusd); + /* xc' = (xa-xb+xc-xd) */ + a2 = (Xaplusc - Xbplusd); + /* yc' = (ya-yb+yc-yd) */ + a3 = (Yaplusc - Ybplusd); + /* xb' = (xa+yb-xc-yd) */ + a4 = (Xaminusc + Ybminusd); + /* yb' = (ya-xb-yc+xd) */ + a5 = (Yaminusc - Xbminusd); + /* xd' = (xa-yb-xc+yd)) */ + a6 = (Xaminusc - Ybminusd); + /* yd' = (ya+xb-yc-xd) */ + a7 = (Xbminusd + Yaminusc); + + ptr1[0] = a0; + ptr1[1] = a1; + ptr1[2] = a2; + ptr1[3] = a3; + ptr1[4] = a4; + ptr1[5] = a5; + ptr1[6] = a6; + ptr1[7] = a7; + + /* increment pointer by 8 */ + ptr1 += 8U; + } while (--j); + +#else + + float32_t t1, t2, r1, r2, s1, s2; + + /* Initializations for the fft calculation */ + n2 = fftLen; + n1 = n2; + for (k = fftLen; k > 1U; k >>= 2U) + { + /* Initializations for the fft calculation */ + n1 = n2; + n2 >>= 2U; + ia1 = 0U; + + /* FFT Calculation */ + j = 0; + do + { + /* index calculation for the coefficients */ + ia2 = ia1 + ia1; + ia3 = ia2 + ia1; + co1 = pCoef[ia1 * 2U]; + si1 = pCoef[(ia1 * 2U) + 1U]; + co2 = pCoef[ia2 * 2U]; + si2 = pCoef[(ia2 * 2U) + 1U]; + co3 = pCoef[ia3 * 2U]; + si3 = pCoef[(ia3 * 2U) + 1U]; + + /* Twiddle coefficients index modifier */ + ia1 = ia1 + twidCoefModifier; + + i0 = j; + do + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* xa + xc */ + r1 = pSrc[(2U * i0)] + pSrc[(2U * i2)]; + + /* xa - xc */ + r2 = pSrc[(2U * i0)] - pSrc[(2U * i2)]; + + /* ya + yc */ + s1 = pSrc[(2U * i0) + 1U] + pSrc[(2U * i2) + 1U]; + + /* ya - yc */ + s2 = pSrc[(2U * i0) + 1U] - pSrc[(2U * i2) + 1U]; + + /* xb + xd */ + t1 = pSrc[2U * i1] + pSrc[2U * i3]; + + /* xa' = xa + xb + xc + xd */ + pSrc[2U * i0] = r1 + t1; + + /* xa + xc -(xb + xd) */ + r1 = r1 - t1; + + /* yb + yd */ + t2 = pSrc[(2U * i1) + 1U] + pSrc[(2U * i3) + 1U]; + + /* ya' = ya + yb + yc + yd */ + pSrc[(2U * i0) + 1U] = s1 + t2; + + /* (ya + yc) - (yb + yd) */ + s1 = s1 - t2; + + /* (yb - yd) */ + t1 = pSrc[(2U * i1) + 1U] - pSrc[(2U * i3) + 1U]; + + /* (xb - xd) */ + t2 = pSrc[2U * i1] - pSrc[2U * i3]; + + /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = (r1 * co2) + (s1 * si2); + + /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = (s1 * co2) - (r1 * si2); + + /* (xa - xc) + (yb - yd) */ + r1 = r2 + t1; + + /* (xa - xc) - (yb - yd) */ + r2 = r2 - t1; + + /* (ya - yc) - (xb - xd) */ + s1 = s2 - t2; + + /* (ya - yc) + (xb - xd) */ + s2 = s2 + t2; + + /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = (r1 * co1) + (s1 * si1); + + /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = (s1 * co1) - (r1 * si1); + + /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = (r2 * co3) + (s2 * si3); + + /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = (s2 * co3) - (r2 * si3); + + i0 += n1; + } while ( i0 < fftLen); + j++; + } while (j <= (n2 - 1U)); + twidCoefModifier <<= 2U; + } + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + +} + +/** + brief Core function for the floating-point CIFFT butterfly process. + param[in,out] pSrc points to the in-place buffer of floating-point data type + param[in] fftLen length of the FFT + param[in] pCoef points to twiddle coefficient buffer + param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + param[in] onebyfftLen value of 1/fftLen + return none + */ + +void riscv_radix4_butterfly_inverse_f32( + float32_t * pSrc, + uint16_t fftLen, + const float32_t * pCoef, + uint16_t twidCoefModifier, + float32_t onebyfftLen) +{ + float32_t co1, co2, co3, si1, si2, si3; + uint32_t ia1, ia2, ia3; + uint32_t i0, i1, i2, i3; + uint32_t n1, n2, j, k; + +#if defined (RISCV_MATH_LOOPUNROLL) + + float32_t xaIn, yaIn, xbIn, ybIn, xcIn, ycIn, xdIn, ydIn; + float32_t Xaplusc, Xbplusd, Yaplusc, Ybplusd, Xaminusc, Xbminusd, Yaminusc, + Ybminusd; + float32_t Xb12C_out, Yb12C_out, Xc12C_out, Yc12C_out, Xd12C_out, Yd12C_out; + float32_t Xb12_out, Yb12_out, Xc12_out, Yc12_out, Xd12_out, Yd12_out; + float32_t *ptr1; + float32_t p0,p1,p2,p3,p4,p5,p6,p7; + float32_t a0,a1,a2,a3,a4,a5,a6,a7; + + + /* Initializations for the first stage */ + n2 = fftLen; + n1 = n2; + + /* n2 = fftLen/4 */ + n2 >>= 2U; + i0 = 0U; + ia1 = 0U; + + j = n2; + + /* Calculation of first stage */ + do + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* Butterfly implementation */ + xaIn = pSrc[(2U * i0)]; + yaIn = pSrc[(2U * i0) + 1U]; + + xcIn = pSrc[(2U * i2)]; + ycIn = pSrc[(2U * i2) + 1U]; + + xbIn = pSrc[(2U * i1)]; + ybIn = pSrc[(2U * i1) + 1U]; + + xdIn = pSrc[(2U * i3)]; + ydIn = pSrc[(2U * i3) + 1U]; + + /* xa + xc */ + Xaplusc = xaIn + xcIn; + /* xb + xd */ + Xbplusd = xbIn + xdIn; + /* ya + yc */ + Yaplusc = yaIn + ycIn; + /* yb + yd */ + Ybplusd = ybIn + ydIn; + + /* index calculation for the coefficients */ + ia2 = ia1 + ia1; + co2 = pCoef[ia2 * 2U]; + si2 = pCoef[(ia2 * 2U) + 1U]; + + /* xa - xc */ + Xaminusc = xaIn - xcIn; + /* xb - xd */ + Xbminusd = xbIn - xdIn; + /* ya - yc */ + Yaminusc = yaIn - ycIn; + /* yb - yd */ + Ybminusd = ybIn - ydIn; + + /* xa' = xa + xb + xc + xd */ + pSrc[(2U * i0)] = Xaplusc + Xbplusd; + + /* ya' = ya + yb + yc + yd */ + pSrc[(2U * i0) + 1U] = Yaplusc + Ybplusd; + + /* (xa - xc) - (yb - yd) */ + Xb12C_out = (Xaminusc - Ybminusd); + /* (ya - yc) + (xb - xd) */ + Yb12C_out = (Yaminusc + Xbminusd); + /* (xa + xc) - (xb + xd) */ + Xc12C_out = (Xaplusc - Xbplusd); + /* (ya + yc) - (yb + yd) */ + Yc12C_out = (Yaplusc - Ybplusd); + /* (xa - xc) + (yb - yd) */ + Xd12C_out = (Xaminusc + Ybminusd); + /* (ya - yc) - (xb - xd) */ + Yd12C_out = (Yaminusc - Xbminusd); + + co1 = pCoef[ia1 * 2U]; + si1 = pCoef[(ia1 * 2U) + 1U]; + + /* index calculation for the coefficients */ + ia3 = ia2 + ia1; + co3 = pCoef[ia3 * 2U]; + si3 = pCoef[(ia3 * 2U) + 1U]; + + Xb12_out = Xb12C_out * co1; + Yb12_out = Yb12C_out * co1; + Xc12_out = Xc12C_out * co2; + Yc12_out = Yc12C_out * co2; + Xd12_out = Xd12C_out * co3; + Yd12_out = Yd12C_out * co3; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + //Xb12_out -= Yb12C_out * si1; + p0 = Yb12C_out * si1; + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + //Yb12_out += Xb12C_out * si1; + p1 = Xb12C_out * si1; + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + //Xc12_out -= Yc12C_out * si2; + p2 = Yc12C_out * si2; + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + //Yc12_out += Xc12C_out * si2; + p3 = Xc12C_out * si2; + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + //Xd12_out -= Yd12C_out * si3; + p4 = Yd12C_out * si3; + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + //Yd12_out += Xd12C_out * si3; + p5 = Xd12C_out * si3; + + Xb12_out -= p0; + Yb12_out += p1; + Xc12_out -= p2; + Yc12_out += p3; + Xd12_out -= p4; + Yd12_out += p5; + + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = Xc12_out; + + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = Yc12_out; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = Xb12_out; + + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = Yb12_out; + + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = Xd12_out; + + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = Yd12_out; + + /* Twiddle coefficients index modifier */ + ia1 = ia1 + twidCoefModifier; + + /* Updating input index */ + i0 = i0 + 1U; + + } while (--j); + + twidCoefModifier <<= 2U; + + /* Calculation of second stage to excluding last stage */ + for (k = fftLen >> 2U; k > 4U; k >>= 2U) + { + /* Initializations for the first stage */ + n1 = n2; + n2 >>= 2U; + ia1 = 0U; + + /* Calculation of first stage */ + j = 0; + do + { + /* index calculation for the coefficients */ + ia2 = ia1 + ia1; + ia3 = ia2 + ia1; + co1 = pCoef[ia1 * 2U]; + si1 = pCoef[(ia1 * 2U) + 1U]; + co2 = pCoef[ia2 * 2U]; + si2 = pCoef[(ia2 * 2U) + 1U]; + co3 = pCoef[ia3 * 2U]; + si3 = pCoef[(ia3 * 2U) + 1U]; + + /* Twiddle coefficients index modifier */ + ia1 = ia1 + twidCoefModifier; + + i0 = j; + do + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + xaIn = pSrc[(2U * i0)]; + yaIn = pSrc[(2U * i0) + 1U]; + + xbIn = pSrc[(2U * i1)]; + ybIn = pSrc[(2U * i1) + 1U]; + + xcIn = pSrc[(2U * i2)]; + ycIn = pSrc[(2U * i2) + 1U]; + + xdIn = pSrc[(2U * i3)]; + ydIn = pSrc[(2U * i3) + 1U]; + + /* xa - xc */ + Xaminusc = xaIn - xcIn; + /* (xb - xd) */ + Xbminusd = xbIn - xdIn; + /* ya - yc */ + Yaminusc = yaIn - ycIn; + /* (yb - yd) */ + Ybminusd = ybIn - ydIn; + + /* xa + xc */ + Xaplusc = xaIn + xcIn; + /* xb + xd */ + Xbplusd = xbIn + xdIn; + /* ya + yc */ + Yaplusc = yaIn + ycIn; + /* yb + yd */ + Ybplusd = ybIn + ydIn; + + /* (xa - xc) - (yb - yd) */ + Xb12C_out = (Xaminusc - Ybminusd); + /* (ya - yc) + (xb - xd) */ + Yb12C_out = (Yaminusc + Xbminusd); + /* xa + xc -(xb + xd) */ + Xc12C_out = (Xaplusc - Xbplusd); + /* (ya + yc) - (yb + yd) */ + Yc12C_out = (Yaplusc - Ybplusd); + /* (xa - xc) + (yb - yd) */ + Xd12C_out = (Xaminusc + Ybminusd); + /* (ya - yc) - (xb - xd) */ + Yd12C_out = (Yaminusc - Xbminusd); + + pSrc[(2U * i0)] = Xaplusc + Xbplusd; + pSrc[(2U * i0) + 1U] = Yaplusc + Ybplusd; + + Xb12_out = Xb12C_out * co1; + Yb12_out = Yb12C_out * co1; + Xc12_out = Xc12C_out * co2; + Yc12_out = Yc12C_out * co2; + Xd12_out = Xd12C_out * co3; + Yd12_out = Yd12C_out * co3; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + //Xb12_out -= Yb12C_out * si1; + p0 = Yb12C_out * si1; + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + //Yb12_out += Xb12C_out * si1; + p1 = Xb12C_out * si1; + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + //Xc12_out -= Yc12C_out * si2; + p2 = Yc12C_out * si2; + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + //Yc12_out += Xc12C_out * si2; + p3 = Xc12C_out * si2; + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + //Xd12_out -= Yd12C_out * si3; + p4 = Yd12C_out * si3; + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + //Yd12_out += Xd12C_out * si3; + p5 = Xd12C_out * si3; + + Xb12_out -= p0; + Yb12_out += p1; + Xc12_out -= p2; + Yc12_out += p3; + Xd12_out -= p4; + Yd12_out += p5; + + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = Xc12_out; + + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = Yc12_out; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = Xb12_out; + + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = Yb12_out; + + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = Xd12_out; + + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = Yd12_out; + + i0 += n1; + } while (i0 < fftLen); + j++; + } while (j <= (n2 - 1U)); + twidCoefModifier <<= 2U; + } + /* Initializations of last stage */ + + j = fftLen >> 2; + ptr1 = &pSrc[0]; + + /* Calculations of last stage */ + do + { + xaIn = ptr1[0]; + yaIn = ptr1[1]; + xbIn = ptr1[2]; + ybIn = ptr1[3]; + xcIn = ptr1[4]; + ycIn = ptr1[5]; + xdIn = ptr1[6]; + ydIn = ptr1[7]; + + /* Butterfly implementation */ + /* xa + xc */ + Xaplusc = xaIn + xcIn; + + /* xa - xc */ + Xaminusc = xaIn - xcIn; + + /* ya + yc */ + Yaplusc = yaIn + ycIn; + + /* ya - yc */ + Yaminusc = yaIn - ycIn; + + /* xb + xd */ + Xbplusd = xbIn + xdIn; + + /* yb + yd */ + Ybplusd = ybIn + ydIn; + + /* (xb-xd) */ + Xbminusd = xbIn - xdIn; + + /* (yb-yd) */ + Ybminusd = ybIn - ydIn; + + /* xa' = (xa+xb+xc+xd) * onebyfftLen */ + a0 = (Xaplusc + Xbplusd); + /* ya' = (ya+yb+yc+yd) * onebyfftLen */ + a1 = (Yaplusc + Ybplusd); + /* xc' = (xa-xb+xc-xd) * onebyfftLen */ + a2 = (Xaplusc - Xbplusd); + /* yc' = (ya-yb+yc-yd) * onebyfftLen */ + a3 = (Yaplusc - Ybplusd); + /* xb' = (xa-yb-xc+yd) * onebyfftLen */ + a4 = (Xaminusc - Ybminusd); + /* yb' = (ya+xb-yc-xd) * onebyfftLen */ + a5 = (Yaminusc + Xbminusd); + /* xd' = (xa-yb-xc+yd) * onebyfftLen */ + a6 = (Xaminusc + Ybminusd); + /* yd' = (ya-xb-yc+xd) * onebyfftLen */ + a7 = (Yaminusc - Xbminusd); + + p0 = a0 * onebyfftLen; + p1 = a1 * onebyfftLen; + p2 = a2 * onebyfftLen; + p3 = a3 * onebyfftLen; + p4 = a4 * onebyfftLen; + p5 = a5 * onebyfftLen; + p6 = a6 * onebyfftLen; + p7 = a7 * onebyfftLen; + + /* xa' = (xa+xb+xc+xd) * onebyfftLen */ + ptr1[0] = p0; + /* ya' = (ya+yb+yc+yd) * onebyfftLen */ + ptr1[1] = p1; + /* xc' = (xa-xb+xc-xd) * onebyfftLen */ + ptr1[2] = p2; + /* yc' = (ya-yb+yc-yd) * onebyfftLen */ + ptr1[3] = p3; + /* xb' = (xa-yb-xc+yd) * onebyfftLen */ + ptr1[4] = p4; + /* yb' = (ya+xb-yc-xd) * onebyfftLen */ + ptr1[5] = p5; + /* xd' = (xa-yb-xc+yd) * onebyfftLen */ + ptr1[6] = p6; + /* yd' = (ya-xb-yc+xd) * onebyfftLen */ + ptr1[7] = p7; + + /* increment source pointer by 8 for next calculations */ + ptr1 = ptr1 + 8U; + + } while (--j); + +#else + + float32_t t1, t2, r1, r2, s1, s2; + + /* Initializations for the first stage */ + n2 = fftLen; + n1 = n2; + + /* Calculation of first stage */ + for (k = fftLen; k > 4U; k >>= 2U) + { + /* Initializations for the first stage */ + n1 = n2; + n2 >>= 2U; + ia1 = 0U; + + /* Calculation of first stage */ + j = 0; + do + { + /* index calculation for the coefficients */ + ia2 = ia1 + ia1; + ia3 = ia2 + ia1; + co1 = pCoef[ia1 * 2U]; + si1 = pCoef[(ia1 * 2U) + 1U]; + co2 = pCoef[ia2 * 2U]; + si2 = pCoef[(ia2 * 2U) + 1U]; + co3 = pCoef[ia3 * 2U]; + si3 = pCoef[(ia3 * 2U) + 1U]; + + /* Twiddle coefficients index modifier */ + ia1 = ia1 + twidCoefModifier; + + i0 = j; + do + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* xa + xc */ + r1 = pSrc[(2U * i0)] + pSrc[(2U * i2)]; + + /* xa - xc */ + r2 = pSrc[(2U * i0)] - pSrc[(2U * i2)]; + + /* ya + yc */ + s1 = pSrc[(2U * i0) + 1U] + pSrc[(2U * i2) + 1U]; + + /* ya - yc */ + s2 = pSrc[(2U * i0) + 1U] - pSrc[(2U * i2) + 1U]; + + /* xb + xd */ + t1 = pSrc[2U * i1] + pSrc[2U * i3]; + + /* xa' = xa + xb + xc + xd */ + pSrc[2U * i0] = r1 + t1; + + /* xa + xc -(xb + xd) */ + r1 = r1 - t1; + + /* yb + yd */ + t2 = pSrc[(2U * i1) + 1U] + pSrc[(2U * i3) + 1U]; + + /* ya' = ya + yb + yc + yd */ + pSrc[(2U * i0) + 1U] = s1 + t2; + + /* (ya + yc) - (yb + yd) */ + s1 = s1 - t2; + + /* (yb - yd) */ + t1 = pSrc[(2U * i1) + 1U] - pSrc[(2U * i3) + 1U]; + + /* (xb - xd) */ + t2 = pSrc[2U * i1] - pSrc[2U * i3]; + + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = (r1 * co2) - (s1 * si2); + + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = (s1 * co2) + (r1 * si2); + + /* (xa - xc) - (yb - yd) */ + r1 = r2 - t1; + + /* (xa - xc) + (yb - yd) */ + r2 = r2 + t1; + + /* (ya - yc) + (xb - xd) */ + s1 = s2 + t2; + + /* (ya - yc) - (xb - xd) */ + s2 = s2 - t2; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = (r1 * co1) - (s1 * si1); + + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = (s1 * co1) + (r1 * si1); + + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = (r2 * co3) - (s2 * si3); + + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = (s2 * co3) + (r2 * si3); + + i0 += n1; + } while ( i0 < fftLen); + j++; + } while (j <= (n2 - 1U)); + twidCoefModifier <<= 2U; + } + /* Initializations of last stage */ + n1 = n2; + n2 >>= 2U; + + /* Calculations of last stage */ + for (i0 = 0U; i0 <= (fftLen - n1); i0 += n1) + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* Butterfly implementation */ + /* xa + xc */ + r1 = pSrc[2U * i0] + pSrc[2U * i2]; + + /* xa - xc */ + r2 = pSrc[2U * i0] - pSrc[2U * i2]; + + /* ya + yc */ + s1 = pSrc[(2U * i0) + 1U] + pSrc[(2U * i2) + 1U]; + + /* ya - yc */ + s2 = pSrc[(2U * i0) + 1U] - pSrc[(2U * i2) + 1U]; + + /* xc + xd */ + t1 = pSrc[2U * i1] + pSrc[2U * i3]; + + /* xa' = xa + xb + xc + xd */ + pSrc[2U * i0] = (r1 + t1) * onebyfftLen; + + /* (xa + xb) - (xc + xd) */ + r1 = r1 - t1; + + /* yb + yd */ + t2 = pSrc[(2U * i1) + 1U] + pSrc[(2U * i3) + 1U]; + + /* ya' = ya + yb + yc + yd */ + pSrc[(2U * i0) + 1U] = (s1 + t2) * onebyfftLen; + + /* (ya + yc) - (yb + yd) */ + s1 = s1 - t2; + + /* (yb-yd) */ + t1 = pSrc[(2U * i1) + 1U] - pSrc[(2U * i3) + 1U]; + + /* (xb-xd) */ + t2 = pSrc[2U * i1] - pSrc[2U * i3]; + + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = r1 * onebyfftLen; + + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = s1 * onebyfftLen; + + /* (xa - xc) - (yb-yd) */ + r1 = r2 - t1; + + /* (xa - xc) + (yb-yd) */ + r2 = r2 + t1; + + /* (ya - yc) + (xb-xd) */ + s1 = s2 + t2; + + /* (ya - yc) - (xb-xd) */ + s2 = s2 - t2; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = r1 * onebyfftLen; + + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = s1 * onebyfftLen; + + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = r2 * onebyfftLen; + + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = s2 * onebyfftLen; + } + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ +} + + diff --git a/components/nmsis/dsp/src/TransformFunctions/riscv_cfft_radix4_init_f16.c b/components/nmsis/dsp/src/TransformFunctions/riscv_cfft_radix4_init_f16.c new file mode 100644 index 00000000..90c6737b --- /dev/null +++ b/components/nmsis/dsp/src/TransformFunctions/riscv_cfft_radix4_init_f16.c @@ -0,0 +1,172 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_cfft_radix4_init_f16.c + * Description: Radix-4 Decimation in Frequency Floating-point CFFT & CIFFT Initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions_f16.h" +#include "riscv_common_tables.h" +#include "riscv_common_tables_f16.h" + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Initialization function for the floating-point CFFT/CIFFT. + @deprecated Do not use this function. It has been superceded by \ref riscv_cfft_f16 and will be removed in the future. + @param[in,out] S points to an instance of the floating-point CFFT/CIFFT structure + @param[in] fftLen length of the FFT + @param[in] ifftFlag flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_ARGUMENT_ERROR : fftLen is not a supported length + + @par Details + The parameter ifftFlag controls whether a forward or inverse transform is computed. + Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated + @par + The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. + Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. + @par + The parameter fftLen Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024. + @par + This Function also initializes Twiddle factor table pointer and Bit reversal table pointer. + */ + +#if defined(RISCV_FLOAT16_SUPPORTED) + +riscv_status riscv_cfft_radix4_init_f16( + riscv_cfft_radix4_instance_f16 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + /* Initialise the default riscv status */ + riscv_status status = RISCV_MATH_ARGUMENT_ERROR; + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_FFT_ALLOW_TABLES) + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_F16_4096) + + /* Initialise the default riscv status */ + status = RISCV_MATH_SUCCESS; + + /* Initialise the FFT length */ + S->fftLen = fftLen; + + /* Initialise the Twiddle coefficient pointer */ + S->pTwiddle = (float16_t *) twiddleCoefF16; + + /* Initialise the Flag for selection of CFFT or CIFFT */ + S->ifftFlag = ifftFlag; + + /* Initialise the Flag for calculation Bit reversal or not */ + S->bitReverseFlag = bitReverseFlag; + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREV_1024) + + /* Initializations of structure parameters depending on the FFT length */ + switch (S->fftLen) + { + + case 4096U: + /* Initializations of structure parameters for 4096 point FFT */ + + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 1U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 1U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) riscvBitRevTable; + /* Initialise the 1/fftLen Value */ + S->onebyfftLen = 0.000244140625; + break; + + case 1024U: + /* Initializations of structure parameters for 1024 point FFT */ + + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 4U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 4U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) & riscvBitRevTable[3]; + /* Initialise the 1/fftLen Value */ + S->onebyfftLen = 0.0009765625f; + break; + + + case 256U: + /* Initializations of structure parameters for 256 point FFT */ + S->twidCoefModifier = 16U; + S->bitRevFactor = 16U; + S->pBitRevTable = (uint16_t *) & riscvBitRevTable[15]; + S->onebyfftLen = 0.00390625f; + break; + + case 64U: + /* Initializations of structure parameters for 64 point FFT */ + S->twidCoefModifier = 64U; + S->bitRevFactor = 64U; + S->pBitRevTable = (uint16_t *) & riscvBitRevTable[63]; + S->onebyfftLen = 0.015625f; + break; + + case 16U: + /* Initializations of structure parameters for 16 point FFT */ + S->twidCoefModifier = 256U; + S->bitRevFactor = 256U; + S->pBitRevTable = (uint16_t *) & riscvBitRevTable[255]; + S->onebyfftLen = 0.0625f; + break; + + + default: + /* Reporting argument error if fftSize is not valid value */ + status = RISCV_MATH_ARGUMENT_ERROR; + break; + } + +#endif +#endif +#endif + return (status); +} +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ +/** + @} end of ComplexFFT group + */ diff --git a/components/nmsis/dsp/src/TransformFunctions/riscv_cfft_radix4_init_f32.c b/components/nmsis/dsp/src/TransformFunctions/riscv_cfft_radix4_init_f32.c new file mode 100644 index 00000000..57e90f8b --- /dev/null +++ b/components/nmsis/dsp/src/TransformFunctions/riscv_cfft_radix4_init_f32.c @@ -0,0 +1,169 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_cfft_radix4_init_f32.c + * Description: Radix-4 Decimation in Frequency Floating-point CFFT & CIFFT Initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" +#include "riscv_common_tables.h" + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Initialization function for the floating-point CFFT/CIFFT. + @deprecated Do not use this function. It has been superceded by \ref riscv_cfft_f32 and will be removed in the future. + @param[in,out] S points to an instance of the floating-point CFFT/CIFFT structure + @param[in] fftLen length of the FFT + @param[in] ifftFlag flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_ARGUMENT_ERROR : fftLen is not a supported length + + @par Details + The parameter ifftFlag controls whether a forward or inverse transform is computed. + Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated + @par + The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. + Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. + @par + The parameter fftLen Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024. + @par + This Function also initializes Twiddle factor table pointer and Bit reversal table pointer. + */ + +riscv_status riscv_cfft_radix4_init_f32( + riscv_cfft_radix4_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + /* Initialise the default riscv status */ + riscv_status status = RISCV_MATH_ARGUMENT_ERROR; + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_FFT_ALLOW_TABLES) + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_F32_4096) + + /* Initialise the default riscv status */ + status = RISCV_MATH_SUCCESS; + + /* Initialise the FFT length */ + S->fftLen = fftLen; + + /* Initialise the Twiddle coefficient pointer */ + S->pTwiddle = (float32_t *) twiddleCoef; + + /* Initialise the Flag for selection of CFFT or CIFFT */ + S->ifftFlag = ifftFlag; + + /* Initialise the Flag for calculation Bit reversal or not */ + S->bitReverseFlag = bitReverseFlag; + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_F32_4096) + + /* Initializations of structure parameters depending on the FFT length */ + switch (S->fftLen) + { + + case 4096U: + /* Initializations of structure parameters for 4096 point FFT */ + + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 1U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 1U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) riscvBitRevTable; + /* Initialise the 1/fftLen Value */ + S->onebyfftLen = 0.000244140625; + break; + + case 1024U: + /* Initializations of structure parameters for 1024 point FFT */ + + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 4U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 4U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) & riscvBitRevTable[3]; + /* Initialise the 1/fftLen Value */ + S->onebyfftLen = 0.0009765625f; + break; + + + case 256U: + /* Initializations of structure parameters for 256 point FFT */ + S->twidCoefModifier = 16U; + S->bitRevFactor = 16U; + S->pBitRevTable = (uint16_t *) & riscvBitRevTable[15]; + S->onebyfftLen = 0.00390625f; + break; + + case 64U: + /* Initializations of structure parameters for 64 point FFT */ + S->twidCoefModifier = 64U; + S->bitRevFactor = 64U; + S->pBitRevTable = (uint16_t *) & riscvBitRevTable[63]; + S->onebyfftLen = 0.015625f; + break; + + case 16U: + /* Initializations of structure parameters for 16 point FFT */ + S->twidCoefModifier = 256U; + S->bitRevFactor = 256U; + S->pBitRevTable = (uint16_t *) & riscvBitRevTable[255]; + S->onebyfftLen = 0.0625f; + break; + + + default: + /* Reporting argument error if fftSize is not valid value */ + status = RISCV_MATH_ARGUMENT_ERROR; + break; + } +#endif +#endif +#endif + + return (status); +} + +/** + @} end of ComplexFFT group + */ diff --git a/components/nmsis/dsp/src/TransformFunctions/riscv_cfft_radix4_init_q15.c b/components/nmsis/dsp/src/TransformFunctions/riscv_cfft_radix4_init_q15.c new file mode 100644 index 00000000..688930ba --- /dev/null +++ b/components/nmsis/dsp/src/TransformFunctions/riscv_cfft_radix4_init_q15.c @@ -0,0 +1,158 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_cfft_radix4_init_q15.c + * Description: Radix-4 Decimation in Frequency Q15 FFT & IFFT initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" +#include "riscv_common_tables.h" + +/** + @ingroup groupTransforms + */ + + +/** + @addtogroup ComplexFFT + @{ + */ + + +/** + @brief Initialization function for the Q15 CFFT/CIFFT. + @deprecated Do not use this function. It has been superseded by \ref riscv_cfft_q15 and will be removed in the future. + @param[in,out] S points to an instance of the Q15 CFFT/CIFFT structure + @param[in] fftLen length of the FFT + @param[in] ifftFlag flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_ARGUMENT_ERROR : fftLen is not a supported length + + @par Details + The parameter ifftFlag controls whether a forward or inverse transform is computed. + Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated + @par + The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. + Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. + @par + The parameter fftLen Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024. + @par + This Function also initializes Twiddle factor table pointer and Bit reversal table pointer. + */ + +riscv_status riscv_cfft_radix4_init_q15( + riscv_cfft_radix4_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + /* Initialise the default riscv status */ + riscv_status status = RISCV_MATH_ARGUMENT_ERROR; + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_FFT_ALLOW_TABLES) + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_Q15_4096) + + /* Initialise the default riscv status */ + status = RISCV_MATH_SUCCESS; + /* Initialise the FFT length */ + S->fftLen = fftLen; + /* Initialise the Twiddle coefficient pointer */ + S->pTwiddle = (q15_t *) twiddleCoef_4096_q15; + /* Initialise the Flag for selection of CFFT or CIFFT */ + S->ifftFlag = ifftFlag; + /* Initialise the Flag for calculation Bit reversal or not */ + S->bitReverseFlag = bitReverseFlag; + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREV_1024) + + /* Initializations of structure parameters depending on the FFT length */ + switch (S->fftLen) + { + case 4096U: + /* Initializations of structure parameters for 4096 point FFT */ + + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 1U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 1U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) riscvBitRevTable; + + break; + + case 1024U: + /* Initializations of structure parameters for 1024 point FFT */ + S->twidCoefModifier = 4U; + S->bitRevFactor = 4U; + S->pBitRevTable = (uint16_t *) & riscvBitRevTable[3]; + + break; + + case 256U: + /* Initializations of structure parameters for 256 point FFT */ + S->twidCoefModifier = 16U; + S->bitRevFactor = 16U; + S->pBitRevTable = (uint16_t *) & riscvBitRevTable[15]; + + break; + + case 64U: + /* Initializations of structure parameters for 64 point FFT */ + S->twidCoefModifier = 64U; + S->bitRevFactor = 64U; + S->pBitRevTable = (uint16_t *) & riscvBitRevTable[63]; + + break; + + case 16U: + /* Initializations of structure parameters for 16 point FFT */ + S->twidCoefModifier = 256U; + S->bitRevFactor = 256U; + S->pBitRevTable = (uint16_t *) & riscvBitRevTable[255]; + + break; + + default: + /* Reporting argument error if fftSize is not valid value */ + status = RISCV_MATH_ARGUMENT_ERROR; + break; + } + +#endif +#endif +#endif + return (status); +} + +/** + @} end of ComplexFFT group + */ diff --git a/components/nmsis/dsp/src/TransformFunctions/riscv_cfft_radix4_init_q31.c b/components/nmsis/dsp/src/TransformFunctions/riscv_cfft_radix4_init_q31.c new file mode 100644 index 00000000..2dd8f63a --- /dev/null +++ b/components/nmsis/dsp/src/TransformFunctions/riscv_cfft_radix4_init_q31.c @@ -0,0 +1,155 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_cfft_radix4_init_q31.c + * Description: Radix-4 Decimation in Frequency Q31 FFT & IFFT initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" +#include "riscv_common_tables.h" + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + + @brief Initialization function for the Q31 CFFT/CIFFT. + @deprecated Do not use this function. It has been superseded by \ref riscv_cfft_q31 and will be removed in the future. + @param[in,out] S points to an instance of the Q31 CFFT/CIFFT structure. + @param[in] fftLen length of the FFT. + @param[in] ifftFlag flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_ARGUMENT_ERROR : fftLen is not a supported length + + @par Details + The parameter ifftFlag controls whether a forward or inverse transform is computed. + Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated + @par + The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. + Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. + @par + The parameter fftLen Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024. + @par + This Function also initializes Twiddle factor table pointer and Bit reversal table pointer. +*/ + +riscv_status riscv_cfft_radix4_init_q31( + riscv_cfft_radix4_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + + /* Initialise the default riscv status */ + riscv_status status = RISCV_MATH_ARGUMENT_ERROR; + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_FFT_ALLOW_TABLES) + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_Q31_4096) + + /* Initialise the default riscv status */ + status = RISCV_MATH_SUCCESS; + /* Initialise the FFT length */ + S->fftLen = fftLen; + /* Initialise the Twiddle coefficient pointer */ + S->pTwiddle = (q31_t *) twiddleCoef_4096_q31; + /* Initialise the Flag for selection of CFFT or CIFFT */ + S->ifftFlag = ifftFlag; + /* Initialise the Flag for calculation Bit reversal or not */ + S->bitReverseFlag = bitReverseFlag; + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREV_1024) + + /* Initializations of Instance structure depending on the FFT length */ + switch (S->fftLen) + { + /* Initializations of structure parameters for 4096 point FFT */ + case 4096U: + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 1U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 1U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) riscvBitRevTable; + break; + + /* Initializations of structure parameters for 1024 point FFT */ + case 1024U: + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 4U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 4U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) & riscvBitRevTable[3]; + break; + + case 256U: + /* Initializations of structure parameters for 256 point FFT */ + S->twidCoefModifier = 16U; + S->bitRevFactor = 16U; + S->pBitRevTable = (uint16_t *) & riscvBitRevTable[15]; + break; + + case 64U: + /* Initializations of structure parameters for 64 point FFT */ + S->twidCoefModifier = 64U; + S->bitRevFactor = 64U; + S->pBitRevTable = (uint16_t *) & riscvBitRevTable[63]; + break; + + case 16U: + /* Initializations of structure parameters for 16 point FFT */ + S->twidCoefModifier = 256U; + S->bitRevFactor = 256U; + S->pBitRevTable = (uint16_t *) & riscvBitRevTable[255]; + break; + + default: + /* Reporting argument error if fftSize is not valid value */ + status = RISCV_MATH_ARGUMENT_ERROR; + break; + } + +#endif +#endif +#endif + return (status); +} + +/** + @} end of ComplexFFT group + */ diff --git a/components/nmsis/dsp/src/TransformFunctions/riscv_cfft_radix4_q15.c b/components/nmsis/dsp/src/TransformFunctions/riscv_cfft_radix4_q15.c new file mode 100644 index 00000000..2b4f8985 --- /dev/null +++ b/components/nmsis/dsp/src/TransformFunctions/riscv_cfft_radix4_q15.c @@ -0,0 +1,1709 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_cfft_radix4_q15.c + * Description: This file has function definition of Radix-4 FFT & IFFT function and + * In-place bit reversal using bit reversal table + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" + + +void riscv_radix4_butterfly_q15( + q15_t * pSrc16, + uint32_t fftLen, + const q15_t * pCoef16, + uint32_t twidCoefModifier); + +void riscv_radix4_butterfly_inverse_q15( + q15_t * pSrc16, + uint32_t fftLen, + const q15_t * pCoef16, + uint32_t twidCoefModifier); + +void riscv_bitreversal_q15( + q15_t * pSrc, + uint32_t fftLen, + uint16_t bitRevFactor, + const uint16_t * pBitRevTab); + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + + +/** + @brief Processing function for the Q15 CFFT/CIFFT. + @deprecated Do not use this function. It has been superseded by \ref riscv_cfft_q15 and will be removed in the future. + @param[in] S points to an instance of the Q15 CFFT/CIFFT structure. + @param[in,out] pSrc points to the complex data buffer. Processing occurs in-place. + @return none + + @par Input and output formats: + Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process. + Hence the output format is different for different FFT sizes. + The input and output formats for different FFT sizes and number of bits to upscale are mentioned in the tables below for CFFT and CIFFT: + @par + \image html CFFTQ15.png "Input and Output Formats for Q15 CFFT" + \image html CIFFTQ15.png "Input and Output Formats for Q15 CIFFT" + */ + +void riscv_cfft_radix4_q15( + const riscv_cfft_radix4_instance_q15 * S, + q15_t * pSrc) +{ + if (S->ifftFlag == 1U) + { + /* Complex IFFT radix-4 */ + riscv_radix4_butterfly_inverse_q15(pSrc, S->fftLen, S->pTwiddle, S->twidCoefModifier); + } + else + { + /* Complex FFT radix-4 */ + riscv_radix4_butterfly_q15(pSrc, S->fftLen, S->pTwiddle, S->twidCoefModifier); + } + + if (S->bitReverseFlag == 1U) + { + /* Bit Reversal */ + riscv_bitreversal_q15(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable); + } + +} + +/** + @} end of ComplexFFT group + */ + +/* + * Radix-4 FFT algorithm used is : + * + * Input real and imaginary data: + * x(n) = xa + j * ya + * x(n+N/4 ) = xb + j * yb + * x(n+N/2 ) = xc + j * yc + * x(n+3N 4) = xd + j * yd + * + * + * Output real and imaginary data: + * x(4r) = xa'+ j * ya' + * x(4r+1) = xb'+ j * yb' + * x(4r+2) = xc'+ j * yc' + * x(4r+3) = xd'+ j * yd' + * + * + * Twiddle factors for radix-4 FFT: + * Wn = co1 + j * (- si1) + * W2n = co2 + j * (- si2) + * W3n = co3 + j * (- si3) + + * The real and imaginary output values for the radix-4 butterfly are + * xa' = xa + xb + xc + xd + * ya' = ya + yb + yc + yd + * xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) + * yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) + * xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) + * yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) + * xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) + * yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) + * + */ + +/** + @brief Core function for the Q15 CFFT butterfly process. + @param[in,out] pSrc16 points to the in-place buffer of Q15 data type + @param[in] fftLen length of the FFT + @param[in] pCoef16 points to twiddle coefficient buffer + @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table + @return none + */ + +void riscv_radix4_butterfly_q15( + q15_t * pSrc16, + uint32_t fftLen, + const q15_t * pCoef16, + uint32_t twidCoefModifier) +{ +#if defined (RISCV_MATH_DSP) + + q31_t R, S, T, U; + q31_t C1, C2, C3, out1, out2; + uint32_t n1, n2, ic, i0, j, k; + + q15_t *ptr1; + q15_t *pSi0; + q15_t *pSi1; + q15_t *pSi2; + q15_t *pSi3; + + q31_t xaya, xbyb, xcyc, xdyd; + + /* Total process is divided into three stages */ + + /* process first stage, middle stages, & last stage */ + + /* Initializations for the first stage */ + n2 = fftLen; + n1 = n2; + + /* n2 = fftLen/4 */ + n2 >>= 2U; + + /* Index for twiddle coefficient */ + ic = 0U; + + /* Index for input read and output write */ + j = n2; + + pSi0 = pSrc16; + pSi1 = pSi0 + 2 * n2; + pSi2 = pSi1 + 2 * n2; + pSi3 = pSi2 + 2 * n2; + + /* Input is in 1.15(q15) format */ + + /* start of first stage process */ + do + { + /* Butterfly implementation */ + + /* Reading i0, i0+fftLen/2 inputs */ + /* Read ya (real), xa(imag) input */ + T = read_q15x2 (pSi0); + T = __SHADD16(T, 0); /* this is just a SIMD arithmetic shift right by 1 */ + T = __SHADD16(T, 0); /* it turns out doing this twice is 2 cycles, the alternative takes 3 cycles */ +/* + in = ((int16_t) (T & 0xFFFF)) >> 2; // alternative code that takes 3 cycles + T = ((T >> 2) & 0xFFFF0000) | (in & 0xFFFF); +*/ + + /* Read yc (real), xc(imag) input */ + S = read_q15x2 (pSi2); + S = __SHADD16(S, 0); + S = __SHADD16(S, 0); + + /* R = packed((ya + yc), (xa + xc) ) */ + R = __QADD16(T, S); + + /* S = packed((ya - yc), (xa - xc) ) */ + S = __QSUB16(T, S); + + /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */ + /* Read yb (real), xb(imag) input */ + T = read_q15x2 (pSi1); + T = __SHADD16(T, 0); + T = __SHADD16(T, 0); + + /* Read yd (real), xd(imag) input */ + U = read_q15x2 (pSi3); + U = __SHADD16(U, 0); + U = __SHADD16(U, 0); + + /* T = packed((yb + yd), (xb + xd) ) */ + T = __QADD16(T, U); + + /* writing the butterfly processed i0 sample */ + /* xa' = xa + xb + xc + xd */ + /* ya' = ya + yb + yc + yd */ + write_q15x2_ia (&pSi0, __SHADD16(R, T)); + + /* R = packed((ya + yc) - (yb + yd), (xa + xc)- (xb + xd)) */ + R = __QSUB16(R, T); + + /* co2 & si2 are read from SIMD Coefficient pointer */ + C2 = read_q15x2 ((q15_t *) pCoef16 + (4U * ic)); + + /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */ + out1 = __SMUAD(C2, R) >> 16U; + /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */ + out2 = __SMUSDX(C2, R); + + /* Reading i0+fftLen/4 */ + /* T = packed(yb, xb) */ + T = read_q15x2 (pSi1); + T = __SHADD16(T, 0); + T = __SHADD16(T, 0); + + /* writing the butterfly processed i0 + fftLen/4 sample */ + /* writing output(xc', yc') in little endian format */ + write_q15x2_ia (&pSi1, (q31_t) __PKHBT( out1, out2, 0 )); + + /* Butterfly calculations */ + /* U = packed(yd, xd) */ + U = read_q15x2 (pSi3); + U = __SHADD16(U, 0); + U = __SHADD16(U, 0); + + /* T = packed(yb-yd, xb-xd) */ + T = __QSUB16(T, U); + + /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */ + R = __QASX(S, T); + /* S = packed((ya-yc) - (xb- xd), (xa-xc) + (yb-yd)) */ + S = __QSAX(S, T); + + /* co1 & si1 are read from SIMD Coefficient pointer */ + C1 = read_q15x2 ((q15_t *) pCoef16 + (2U * ic)); + /* Butterfly process for the i0+fftLen/2 sample */ + + /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */ + out1 = __SMUAD(C1, S) >> 16U; + /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */ + out2 = __SMUSDX(C1, S); + + /* writing output(xb', yb') in little endian format */ + write_q15x2_ia (&pSi2, __PKHBT( out1, out2, 0 )); + + /* co3 & si3 are read from SIMD Coefficient pointer */ + C3 = read_q15x2 ((q15_t *) pCoef16 + (6U * ic)); + /* Butterfly process for the i0+3fftLen/4 sample */ + + /* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */ + out1 = __SMUAD(C3, R) >> 16U; + /* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */ + out2 = __SMUSDX(C3, R); + + /* writing output(xd', yd') in little endian format */ + write_q15x2_ia (&pSi3, __PKHBT( out1, out2, 0 )); + + /* Twiddle coefficients index modifier */ + ic = ic + twidCoefModifier; + + } while (--j); + /* data is in 4.11(q11) format */ + + /* end of first stage process */ + + + /* start of middle stage process */ + + /* Twiddle coefficients index modifier */ + twidCoefModifier <<= 2U; + + /* Calculation of Middle stage */ + for (k = fftLen / 4U; k > 4U; k >>= 2U) + { + /* Initializations for the middle stage */ + n1 = n2; + n2 >>= 2U; + ic = 0U; + + for (j = 0U; j <= (n2 - 1U); j++) + { + /* index calculation for the coefficients */ + C1 = read_q15x2 ((q15_t *) pCoef16 + (2U * ic)); + C2 = read_q15x2 ((q15_t *) pCoef16 + (4U * ic)); + C3 = read_q15x2 ((q15_t *) pCoef16 + (6U * ic)); + + /* Twiddle coefficients index modifier */ + ic = ic + twidCoefModifier; + + pSi0 = pSrc16 + 2 * j; + pSi1 = pSi0 + 2 * n2; + pSi2 = pSi1 + 2 * n2; + pSi3 = pSi2 + 2 * n2; + + /* Butterfly implementation */ + for (i0 = j; i0 < fftLen; i0 += n1) + { + /* Reading i0, i0+fftLen/2 inputs */ + /* Read ya (real), xa(imag) input */ + T = read_q15x2 (pSi0); + + /* Read yc (real), xc(imag) input */ + S = read_q15x2 (pSi2); + + /* R = packed( (ya + yc), (xa + xc)) */ + R = __QADD16(T, S); + + /* S = packed((ya - yc), (xa - xc)) */ + S = __QSUB16(T, S); + + /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */ + /* Read yb (real), xb(imag) input */ + T = read_q15x2 (pSi1); + + /* Read yd (real), xd(imag) input */ + U = read_q15x2 (pSi3); + + /* T = packed( (yb + yd), (xb + xd)) */ + T = __QADD16(T, U); + + /* writing the butterfly processed i0 sample */ + + /* xa' = xa + xb + xc + xd */ + /* ya' = ya + yb + yc + yd */ + out1 = __SHADD16(R, T); + out1 = __SHADD16(out1, 0); + write_q15x2 (pSi0, out1); + pSi0 += 2 * n1; + + /* R = packed( (ya + yc) - (yb + yd), (xa + xc) - (xb + xd)) */ + R = __SHSUB16(R, T); + + /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */ + out1 = __SMUAD(C2, R) >> 16U; + + /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */ + out2 = __SMUSDX(C2, R); + + /* Reading i0+3fftLen/4 */ + /* Read yb (real), xb(imag) input */ + T = read_q15x2 (pSi1); + + /* writing the butterfly processed i0 + fftLen/4 sample */ + /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */ + /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */ + write_q15x2 (pSi1, __PKHBT( out1, out2, 0 )); + pSi1 += 2 * n1; + + /* Butterfly calculations */ + + /* Read yd (real), xd(imag) input */ + U = read_q15x2 (pSi3); + + /* T = packed(yb-yd, xb-xd) */ + T = __QSUB16(T, U); + + /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */ + R = __SHASX(S, T); + + /* S = packed((ya-yc) - (xb- xd), (xa-xc) + (yb-yd)) */ + S = __SHSAX(S, T); + + + /* Butterfly process for the i0+fftLen/2 sample */ + out1 = __SMUAD(C1, S) >> 16U; + out2 = __SMUSDX(C1, S); + + /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */ + /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */ + write_q15x2 (pSi2, __PKHBT( out1, out2, 0 )); + pSi2 += 2 * n1; + + /* Butterfly process for the i0+3fftLen/4 sample */ + + out1 = __SMUAD(C3, R) >> 16U; + out2 = __SMUSDX(C3, R); + + /* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */ + /* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */ + write_q15x2 (pSi3, __PKHBT( out1, out2, 0 )); + pSi3 += 2 * n1; + } + } + /* Twiddle coefficients index modifier */ + twidCoefModifier <<= 2U; + } + /* end of middle stage process */ + + + /* data is in 10.6(q6) format for the 1024 point */ + /* data is in 8.8(q8) format for the 256 point */ + /* data is in 6.10(q10) format for the 64 point */ + /* data is in 4.12(q12) format for the 16 point */ + + /* Initializations for the last stage */ + j = fftLen >> 2; + + ptr1 = &pSrc16[0]; + + /* start of last stage process */ + + /* Butterfly implementation */ + do + { + /* Read xa (real), ya(imag) input */ + xaya = read_q15x2_ia ((q15_t **) &ptr1); + + /* Read xb (real), yb(imag) input */ + xbyb = read_q15x2_ia ((q15_t **) &ptr1); + + /* Read xc (real), yc(imag) input */ + xcyc = read_q15x2_ia ((q15_t **) &ptr1); + + /* Read xd (real), yd(imag) input */ + xdyd = read_q15x2_ia ((q15_t **) &ptr1); + + /* R = packed((ya + yc), (xa + xc)) */ + R = __QADD16(xaya, xcyc); + + /* T = packed((yb + yd), (xb + xd)) */ + T = __QADD16(xbyb, xdyd); + + /* pointer updation for writing */ + ptr1 = ptr1 - 8U; + + + /* xa' = xa + xb + xc + xd */ + /* ya' = ya + yb + yc + yd */ + write_q15x2_ia (&ptr1, __SHADD16(R, T)); + + /* T = packed((yb + yd), (xb + xd)) */ + T = __QADD16(xbyb, xdyd); + + /* xc' = (xa-xb+xc-xd) */ + /* yc' = (ya-yb+yc-yd) */ + write_q15x2_ia (&ptr1, __SHSUB16(R, T)); + + /* S = packed((ya - yc), (xa - xc)) */ + S = __QSUB16(xaya, xcyc); + + /* Read yd (real), xd(imag) input */ + /* T = packed( (yb - yd), (xb - xd)) */ + U = __QSUB16(xbyb, xdyd); + + /* xb' = (xa+yb-xc-yd) */ + /* yb' = (ya-xb-yc+xd) */ + write_q15x2_ia (&ptr1, __SHSAX(S, U)); + + /* xd' = (xa-yb-xc+yd) */ + /* yd' = (ya+xb-yc-xd) */ + write_q15x2_ia (&ptr1, __SHASX(S, U)); + + } while (--j); + + /* end of last stage process */ + + /* output is in 11.5(q5) format for the 1024 point */ + /* output is in 9.7(q7) format for the 256 point */ + /* output is in 7.9(q9) format for the 64 point */ + /* output is in 5.11(q11) format for the 16 point */ + + +#else /* #if defined (RISCV_MATH_DSP) */ + + q15_t R0, R1, S0, S1, T0, T1, U0, U1; + q15_t Co1, Si1, Co2, Si2, Co3, Si3, out1, out2; + uint32_t n1, n2, ic, i0, i1, i2, i3, j, k; + + /* Total process is divided into three stages */ + + /* process first stage, middle stages, & last stage */ + + /* Initializations for the first stage */ + n2 = fftLen; + n1 = n2; + + /* n2 = fftLen/4 */ + n2 >>= 2U; + + /* Index for twiddle coefficient */ + ic = 0U; + + /* Index for input read and output write */ + i0 = 0U; + j = n2; + + /* Input is in 1.15(q15) format */ + + /* start of first stage process */ + do + { + /* Butterfly implementation */ + + /* index calculation for the input as, */ + /* pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* Reading i0, i0+fftLen/2 inputs */ + + /* input is down scale by 4 to avoid overflow */ + /* Read ya (real), xa(imag) input */ + T0 = pSrc16[i0 * 2U] >> 2U; + T1 = pSrc16[(i0 * 2U) + 1U] >> 2U; + + /* input is down scale by 4 to avoid overflow */ + /* Read yc (real), xc(imag) input */ + S0 = pSrc16[i2 * 2U] >> 2U; + S1 = pSrc16[(i2 * 2U) + 1U] >> 2U; + + /* R0 = (ya + yc) */ + R0 = __SSAT(T0 + S0, 16U); + /* R1 = (xa + xc) */ + R1 = __SSAT(T1 + S1, 16U); + + /* S0 = (ya - yc) */ + S0 = __SSAT(T0 - S0, 16); + /* S1 = (xa - xc) */ + S1 = __SSAT(T1 - S1, 16); + + /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */ + /* input is down scale by 4 to avoid overflow */ + /* Read yb (real), xb(imag) input */ + T0 = pSrc16[i1 * 2U] >> 2U; + T1 = pSrc16[(i1 * 2U) + 1U] >> 2U; + + /* input is down scale by 4 to avoid overflow */ + /* Read yd (real), xd(imag) input */ + U0 = pSrc16[i3 * 2U] >> 2U; + U1 = pSrc16[(i3 * 2U) + 1] >> 2U; + + /* T0 = (yb + yd) */ + T0 = __SSAT(T0 + U0, 16U); + /* T1 = (xb + xd) */ + T1 = __SSAT(T1 + U1, 16U); + + /* writing the butterfly processed i0 sample */ + /* ya' = ya + yb + yc + yd */ + /* xa' = xa + xb + xc + xd */ + pSrc16[i0 * 2U] = (R0 >> 1U) + (T0 >> 1U); + pSrc16[(i0 * 2U) + 1U] = (R1 >> 1U) + (T1 >> 1U); + + /* R0 = (ya + yc) - (yb + yd) */ + /* R1 = (xa + xc) - (xb + xd) */ + R0 = __SSAT(R0 - T0, 16U); + R1 = __SSAT(R1 - T1, 16U); + + /* co2 & si2 are read from Coefficient pointer */ + Co2 = pCoef16[2U * ic * 2U]; + Si2 = pCoef16[(2U * ic * 2U) + 1]; + + /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */ + out1 = (q15_t) ((Co2 * R0 + Si2 * R1) >> 16U); + /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */ + out2 = (q15_t) ((-Si2 * R0 + Co2 * R1) >> 16U); + + /* Reading i0+fftLen/4 */ + /* input is down scale by 4 to avoid overflow */ + /* T0 = yb, T1 = xb */ + T0 = pSrc16[i1 * 2U] >> 2; + T1 = pSrc16[(i1 * 2U) + 1] >> 2; + + /* writing the butterfly processed i0 + fftLen/4 sample */ + /* writing output(xc', yc') in little endian format */ + pSrc16[i1 * 2U] = out1; + pSrc16[(i1 * 2U) + 1] = out2; + + /* Butterfly calculations */ + /* input is down scale by 4 to avoid overflow */ + /* U0 = yd, U1 = xd */ + U0 = pSrc16[i3 * 2U] >> 2; + U1 = pSrc16[(i3 * 2U) + 1] >> 2; + /* T0 = yb-yd */ + T0 = __SSAT(T0 - U0, 16); + /* T1 = xb-xd */ + T1 = __SSAT(T1 - U1, 16); + + /* R1 = (ya-yc) + (xb- xd), R0 = (xa-xc) - (yb-yd)) */ + R0 = (q15_t) __SSAT((q31_t) (S0 - T1), 16); + R1 = (q15_t) __SSAT((q31_t) (S1 + T0), 16); + + /* S1 = (ya-yc) - (xb- xd), S0 = (xa-xc) + (yb-yd)) */ + S0 = (q15_t) __SSAT(((q31_t) S0 + T1), 16U); + S1 = (q15_t) __SSAT(((q31_t) S1 - T0), 16U); + + /* co1 & si1 are read from Coefficient pointer */ + Co1 = pCoef16[ic * 2U]; + Si1 = pCoef16[(ic * 2U) + 1]; + /* Butterfly process for the i0+fftLen/2 sample */ + /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */ + out1 = (q15_t) ((Si1 * S1 + Co1 * S0) >> 16); + /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */ + out2 = (q15_t) ((-Si1 * S0 + Co1 * S1) >> 16); + + /* writing output(xb', yb') in little endian format */ + pSrc16[i2 * 2U] = out1; + pSrc16[(i2 * 2U) + 1] = out2; + + /* Co3 & si3 are read from Coefficient pointer */ + Co3 = pCoef16[3U * (ic * 2U)]; + Si3 = pCoef16[(3U * (ic * 2U)) + 1]; + /* Butterfly process for the i0+3fftLen/4 sample */ + /* xd' = (xa-yb-xc+yd)* Co3 + (ya+xb-yc-xd)* (si3) */ + out1 = (q15_t) ((Si3 * R1 + Co3 * R0) >> 16U); + /* yd' = (ya+xb-yc-xd)* Co3 - (xa-yb-xc+yd)* (si3) */ + out2 = (q15_t) ((-Si3 * R0 + Co3 * R1) >> 16U); + /* writing output(xd', yd') in little endian format */ + pSrc16[i3 * 2U] = out1; + pSrc16[(i3 * 2U) + 1] = out2; + + /* Twiddle coefficients index modifier */ + ic = ic + twidCoefModifier; + + /* Updating input index */ + i0 = i0 + 1U; + + } while (--j); + /* data is in 4.11(q11) format */ + + /* end of first stage process */ + + + /* start of middle stage process */ + + /* Twiddle coefficients index modifier */ + twidCoefModifier <<= 2U; + + /* Calculation of Middle stage */ + for (k = fftLen / 4U; k > 4U; k >>= 2U) + { + /* Initializations for the middle stage */ + n1 = n2; + n2 >>= 2U; + ic = 0U; + + for (j = 0U; j <= (n2 - 1U); j++) + { + /* index calculation for the coefficients */ + Co1 = pCoef16[ic * 2U]; + Si1 = pCoef16[(ic * 2U) + 1U]; + Co2 = pCoef16[2U * (ic * 2U)]; + Si2 = pCoef16[(2U * (ic * 2U)) + 1U]; + Co3 = pCoef16[3U * (ic * 2U)]; + Si3 = pCoef16[(3U * (ic * 2U)) + 1U]; + + /* Twiddle coefficients index modifier */ + ic = ic + twidCoefModifier; + + /* Butterfly implementation */ + for (i0 = j; i0 < fftLen; i0 += n1) + { + /* index calculation for the input as, */ + /* pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* Reading i0, i0+fftLen/2 inputs */ + /* Read ya (real), xa(imag) input */ + T0 = pSrc16[i0 * 2U]; + T1 = pSrc16[(i0 * 2U) + 1U]; + + /* Read yc (real), xc(imag) input */ + S0 = pSrc16[i2 * 2U]; + S1 = pSrc16[(i2 * 2U) + 1U]; + + /* R0 = (ya + yc), R1 = (xa + xc) */ + R0 = __SSAT(T0 + S0, 16); + R1 = __SSAT(T1 + S1, 16); + + /* S0 = (ya - yc), S1 =(xa - xc) */ + S0 = __SSAT(T0 - S0, 16); + S1 = __SSAT(T1 - S1, 16); + + /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */ + /* Read yb (real), xb(imag) input */ + T0 = pSrc16[i1 * 2U]; + T1 = pSrc16[(i1 * 2U) + 1U]; + + /* Read yd (real), xd(imag) input */ + U0 = pSrc16[i3 * 2U]; + U1 = pSrc16[(i3 * 2U) + 1U]; + + + /* T0 = (yb + yd), T1 = (xb + xd) */ + T0 = __SSAT(T0 + U0, 16); + T1 = __SSAT(T1 + U1, 16); + + /* writing the butterfly processed i0 sample */ + + /* xa' = xa + xb + xc + xd */ + /* ya' = ya + yb + yc + yd */ + out1 = ((R0 >> 1U) + (T0 >> 1U)) >> 1U; + out2 = ((R1 >> 1U) + (T1 >> 1U)) >> 1U; + + pSrc16[i0 * 2U] = out1; + pSrc16[(2U * i0) + 1U] = out2; + + /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc) - (xb + xd) */ + R0 = (R0 >> 1U) - (T0 >> 1U); + R1 = (R1 >> 1U) - (T1 >> 1U); + + /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */ + out1 = (q15_t) ((Co2 * R0 + Si2 * R1) >> 16U); + + /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */ + out2 = (q15_t) ((-Si2 * R0 + Co2 * R1) >> 16U); + + /* Reading i0+3fftLen/4 */ + /* Read yb (real), xb(imag) input */ + T0 = pSrc16[i1 * 2U]; + T1 = pSrc16[(i1 * 2U) + 1U]; + + /* writing the butterfly processed i0 + fftLen/4 sample */ + /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */ + /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */ + pSrc16[i1 * 2U] = out1; + pSrc16[(i1 * 2U) + 1U] = out2; + + /* Butterfly calculations */ + + /* Read yd (real), xd(imag) input */ + U0 = pSrc16[i3 * 2U]; + U1 = pSrc16[(i3 * 2U) + 1U]; + + /* T0 = yb-yd, T1 = xb-xd */ + T0 = __SSAT(T0 - U0, 16); + T1 = __SSAT(T1 - U1, 16); + + /* R0 = (ya-yc) + (xb- xd), R1 = (xa-xc) - (yb-yd)) */ + R0 = (S0 >> 1U) - (T1 >> 1U); + R1 = (S1 >> 1U) + (T0 >> 1U); + + /* S0 = (ya-yc) - (xb- xd), S1 = (xa-xc) + (yb-yd)) */ + S0 = (S0 >> 1U) + (T1 >> 1U); + S1 = (S1 >> 1U) - (T0 >> 1U); + + /* Butterfly process for the i0+fftLen/2 sample */ + out1 = (q15_t) ((Co1 * S0 + Si1 * S1) >> 16U); + + out2 = (q15_t) ((-Si1 * S0 + Co1 * S1) >> 16U); + + /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */ + /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */ + pSrc16[i2 * 2U] = out1; + pSrc16[(i2 * 2U) + 1U] = out2; + + /* Butterfly process for the i0+3fftLen/4 sample */ + out1 = (q15_t) ((Si3 * R1 + Co3 * R0) >> 16U); + + out2 = (q15_t) ((-Si3 * R0 + Co3 * R1) >> 16U); + /* xd' = (xa-yb-xc+yd)* Co3 + (ya+xb-yc-xd)* (si3) */ + /* yd' = (ya+xb-yc-xd)* Co3 - (xa-yb-xc+yd)* (si3) */ + pSrc16[i3 * 2U] = out1; + pSrc16[(i3 * 2U) + 1U] = out2; + } + } + /* Twiddle coefficients index modifier */ + twidCoefModifier <<= 2U; + } + /* end of middle stage process */ + + + /* data is in 10.6(q6) format for the 1024 point */ + /* data is in 8.8(q8) format for the 256 point */ + /* data is in 6.10(q10) format for the 64 point */ + /* data is in 4.12(q12) format for the 16 point */ + + /* Initializations for the last stage */ + n1 = n2; + n2 >>= 2U; + + /* start of last stage process */ + + /* Butterfly implementation */ + for (i0 = 0U; i0 <= (fftLen - n1); i0 += n1) + { + /* index calculation for the input as, */ + /* pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* Reading i0, i0+fftLen/2 inputs */ + /* Read ya (real), xa(imag) input */ + T0 = pSrc16[i0 * 2U]; + T1 = pSrc16[(i0 * 2U) + 1U]; + + /* Read yc (real), xc(imag) input */ + S0 = pSrc16[i2 * 2U]; + S1 = pSrc16[(i2 * 2U) + 1U]; + + /* R0 = (ya + yc), R1 = (xa + xc) */ + R0 = __SSAT(T0 + S0, 16U); + R1 = __SSAT(T1 + S1, 16U); + + /* S0 = (ya - yc), S1 = (xa - xc) */ + S0 = __SSAT(T0 - S0, 16U); + S1 = __SSAT(T1 - S1, 16U); + + /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */ + /* Read yb (real), xb(imag) input */ + T0 = pSrc16[i1 * 2U]; + T1 = pSrc16[(i1 * 2U) + 1U]; + /* Read yd (real), xd(imag) input */ + U0 = pSrc16[i3 * 2U]; + U1 = pSrc16[(i3 * 2U) + 1U]; + + /* T0 = (yb + yd), T1 = (xb + xd)) */ + T0 = __SSAT(T0 + U0, 16U); + T1 = __SSAT(T1 + U1, 16U); + + /* writing the butterfly processed i0 sample */ + /* xa' = xa + xb + xc + xd */ + /* ya' = ya + yb + yc + yd */ + pSrc16[i0 * 2U] = (R0 >> 1U) + (T0 >> 1U); + pSrc16[(i0 * 2U) + 1U] = (R1 >> 1U) + (T1 >> 1U); + + /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc) - (xb + xd) */ + R0 = (R0 >> 1U) - (T0 >> 1U); + R1 = (R1 >> 1U) - (T1 >> 1U); + /* Read yb (real), xb(imag) input */ + T0 = pSrc16[i1 * 2U]; + T1 = pSrc16[(i1 * 2U) + 1U]; + + /* writing the butterfly processed i0 + fftLen/4 sample */ + /* xc' = (xa-xb+xc-xd) */ + /* yc' = (ya-yb+yc-yd) */ + pSrc16[i1 * 2U] = R0; + pSrc16[(i1 * 2U) + 1U] = R1; + + /* Read yd (real), xd(imag) input */ + U0 = pSrc16[i3 * 2U]; + U1 = pSrc16[(i3 * 2U) + 1U]; + /* T0 = (yb - yd), T1 = (xb - xd) */ + T0 = __SSAT(T0 - U0, 16U); + T1 = __SSAT(T1 - U1, 16U); + + /* writing the butterfly processed i0 + fftLen/2 sample */ + /* xb' = (xa+yb-xc-yd) */ + /* yb' = (ya-xb-yc+xd) */ + pSrc16[i2 * 2U] = (S0 >> 1U) + (T1 >> 1U); + pSrc16[(i2 * 2U) + 1U] = (S1 >> 1U) - (T0 >> 1U); + + /* writing the butterfly processed i0 + 3fftLen/4 sample */ + /* xd' = (xa-yb-xc+yd) */ + /* yd' = (ya+xb-yc-xd) */ + pSrc16[i3 * 2U] = (S0 >> 1U) - (T1 >> 1U); + pSrc16[(i3 * 2U) + 1U] = (S1 >> 1U) + (T0 >> 1U); + + } + + /* end of last stage process */ + + /* output is in 11.5(q5) format for the 1024 point */ + /* output is in 9.7(q7) format for the 256 point */ + /* output is in 7.9(q9) format for the 64 point */ + /* output is in 5.11(q11) format for the 16 point */ + +#endif /* #if defined (RISCV_MATH_DSP) */ + + +} + + +/** + @brief Core function for the Q15 CIFFT butterfly process. + @param[in,out] pSrc16 points to the in-place buffer of Q15 data type + @param[in] fftLen length of the FFT + @param[in] pCoef16 points to twiddle coefficient buffer + @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + @return none + */ + +/* + * Radix-4 IFFT algorithm used is : + * + * CIFFT uses same twiddle coefficients as CFFT function + * x[k] = x[n] + (j)k * x[n + fftLen/4] + (-1)k * x[n+fftLen/2] + (-j)k * x[n+3*fftLen/4] + * + * + * IFFT is implemented with following changes in equations from FFT + * + * Input real and imaginary data: + * x(n) = xa + j * ya + * x(n+N/4 ) = xb + j * yb + * x(n+N/2 ) = xc + j * yc + * x(n+3N 4) = xd + j * yd + * + * + * Output real and imaginary data: + * x(4r) = xa'+ j * ya' + * x(4r+1) = xb'+ j * yb' + * x(4r+2) = xc'+ j * yc' + * x(4r+3) = xd'+ j * yd' + * + * + * Twiddle factors for radix-4 IFFT: + * Wn = co1 + j * (si1) + * W2n = co2 + j * (si2) + * W3n = co3 + j * (si3) + + * The real and imaginary output values for the radix-4 butterfly are + * xa' = xa + xb + xc + xd + * ya' = ya + yb + yc + yd + * xb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1) + * yb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1) + * xc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2) + * yc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2) + * xd' = (xa+yb-xc-yd)* co3 - (ya-xb-yc+xd)* (si3) + * yd' = (ya-xb-yc+xd)* co3 + (xa+yb-xc-yd)* (si3) + * + */ + +void riscv_radix4_butterfly_inverse_q15( + q15_t * pSrc16, + uint32_t fftLen, + const q15_t * pCoef16, + uint32_t twidCoefModifier) +{ + +#if defined (RISCV_MATH_DSP) + + q31_t R, S, T, U; + q31_t C1, C2, C3, out1, out2; + uint32_t n1, n2, ic, i0, j, k; + + q15_t *ptr1; + q15_t *pSi0; + q15_t *pSi1; + q15_t *pSi2; + q15_t *pSi3; + + q31_t xaya, xbyb, xcyc, xdyd; + + /* Total process is divided into three stages */ + + /* process first stage, middle stages, & last stage */ + + /* Initializations for the first stage */ + n2 = fftLen; + n1 = n2; + + /* n2 = fftLen/4 */ + n2 >>= 2U; + + /* Index for twiddle coefficient */ + ic = 0U; + + /* Index for input read and output write */ + j = n2; + + pSi0 = pSrc16; + pSi1 = pSi0 + 2 * n2; + pSi2 = pSi1 + 2 * n2; + pSi3 = pSi2 + 2 * n2; + + /* Input is in 1.15(q15) format */ + + /* start of first stage process */ + do + { + /* Butterfly implementation */ + + /* Reading i0, i0+fftLen/2 inputs */ + /* Read ya (real), xa(imag) input */ + T = read_q15x2 (pSi0); +#if __RISCV_XLEN == 64 + T = __RV_SRA16(T, 2); /* this is just a SIMD arithmetic shift right by 1 */ +#else + T = __RV_RADD16(T, 0); /* this is just a SIMD arithmetic shift right by 1 */ + T = __RV_RADD16(T, 0); /* it turns out doing this twice is 2 cycles, the alternative takes 3 cycles */ +#endif /* __RISCV_XLEN == 64 */ +/* + in = ((int16_t) (T & 0xFFFF)) >> 2; // alternative code that takes 3 cycles + T = ((T >> 2) & 0xFFFF0000) | (in & 0xFFFF); +*/ + + /* Read yc (real), xc(imag) input */ + S = read_q15x2 (pSi2); +#if __RISCV_XLEN == 64 + S = __RV_SRA16(S, 2); /* this is just a SIMD arithmetic shift right by 1 */ +#else + S = __RV_RADD16(S, 0); + S = __RV_RADD16(S, 0); +#endif /* __RISCV_XLEN == 64 */ + + /* R = packed((ya + yc), (xa + xc) ) */ + R = __RV_KADD16(T, S); + + /* S = packed((ya - yc), (xa - xc) ) */ + S = __RV_KSUB16(T, S); + + /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */ + /* Read yb (real), xb(imag) input */ + T = read_q15x2 (pSi1); +#if __RISCV_XLEN == 64 + T = __RV_SRA16(T, 2); /* this is just a SIMD arithmetic shift right by 1 */ +#else + T = __RV_RADD16(T, 0); + T = __RV_RADD16(T, 0); +#endif /* __RISCV_XLEN == 64 */ + /* Read yd (real), xd(imag) input */ + U = read_q15x2 (pSi3); +#if __RISCV_XLEN == 64 + U = __RV_SRA16(U, 2); /* this is just a SIMD arithmetic shift right by 1 */ +#else + U = __RV_RADD16(U, 0); + U = __RV_RADD16(U, 0); +#endif /* __RISCV_XLEN == 64 */ + /* T = packed((yb + yd), (xb + xd) ) */ + T = __RV_KADD16(T, U); + + + /* writing the butterfly processed i0 sample */ + /* xa' = xa + xb + xc + xd */ + /* ya' = ya + yb + yc + yd */ + write_q15x2_ia (&pSi0, __RV_RADD16(R, T)); + + /* R = packed((ya + yc) - (yb + yd), (xa + xc)- (xb + xd)) */ + R = __RV_KSUB16(R, T); + + /* co2 & si2 are read from SIMD Coefficient pointer */ + C2 = read_q15x2 ((q15_t *) pCoef16 + (4U * ic)); + + /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */ + out1 = __RV_KMDA(C2, R) >> 16U; + /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */ + out2 = __RV_KMXDA(C2, R); + + /* Reading i0+fftLen/4 */ + /* T = packed(yb, xb) */ + T = read_q15x2 (pSi1); +#if __RISCV_XLEN == 64 + T = __RV_SRA16(T, 2); /* this is just a SIMD arithmetic shift right by 1 */ +#else + T = __RV_RADD16(T, 0); + T = __RV_RADD16(T, 0); +#endif /* __RISCV_XLEN == 64 */ + /* writing the butterfly processed i0 + fftLen/4 sample */ + /* writing output(xc', yc') in little endian format */ + write_q15x2_ia (&pSi1, (q31_t) __PKHBT( out1, out2, 0 )); + + /* Butterfly calculations */ + /* U = packed(yd, xd) */ + U = read_q15x2 (pSi3); +#if __RISCV_XLEN == 64 + U = __RV_SRA16(U, 2); /* this is just a SIMD arithmetic shift right by 1 */ +#else + U = __RV_RADD16(U, 0); + U = __RV_RADD16(U, 0); +#endif /* __RISCV_XLEN == 64 */ + /* T = packed(yb-yd, xb-xd) */ + T = __RV_KSUB16(T, U); + + /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */ + R = __RV_KCRAS16(S, T); + /* S = packed((ya-yc) - (xb- xd), (xa-xc) + (yb-yd)) */ + S = __RV_KCRSA16(S, T); + + /* co1 & si1 are read from SIMD Coefficient pointer */ + C1 = read_q15x2 ((q15_t *) pCoef16 + (2U * ic)); + /* Butterfly process for the i0+fftLen/2 sample */ + + /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */ + out1 = __RV_KMDA(C1, S) >> 16U; + /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */ + out2 = __RV_KMXDA(C1, S); + + /* writing output(xb', yb') in little endian format */ + write_q15x2_ia (&pSi2, __PKHBT( out1, out2, 0 )); + + /* co3 & si3 are read from SIMD Coefficient pointer */ + C3 = read_q15x2 ((q15_t *) pCoef16 + (6U * ic)); + /* Butterfly process for the i0+3fftLen/4 sample */ + + /* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */ + out1 = __RV_KMDA(C3, R) >> 16U; + /* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */ + out2 = __RV_KMXDA(C3, R); + + /* writing output(xd', yd') in little endian format */ + write_q15x2_ia (&pSi3, __PKHBT( out1, out2, 0 )); + + /* Twiddle coefficients index modifier */ + ic = ic + twidCoefModifier; + + } while (--j); + /* data is in 4.11(q11) format */ + + /* end of first stage process */ + + + /* start of middle stage process */ + + /* Twiddle coefficients index modifier */ + twidCoefModifier <<= 2U; + + /* Calculation of Middle stage */ + for (k = fftLen / 4U; k > 4U; k >>= 2U) + { + /* Initializations for the middle stage */ + n1 = n2; + n2 >>= 2U; + ic = 0U; + + for (j = 0U; j <= (n2 - 1U); j++) + { + /* index calculation for the coefficients */ + C1 = read_q15x2 ((q15_t *) pCoef16 + (2U * ic)); + C2 = read_q15x2 ((q15_t *) pCoef16 + (4U * ic)); + C3 = read_q15x2 ((q15_t *) pCoef16 + (6U * ic)); + + /* Twiddle coefficients index modifier */ + ic = ic + twidCoefModifier; + + pSi0 = pSrc16 + 2 * j; + pSi1 = pSi0 + 2 * n2; + pSi2 = pSi1 + 2 * n2; + pSi3 = pSi2 + 2 * n2; + + /* Butterfly implementation */ + for (i0 = j; i0 < fftLen; i0 += n1) + { + /* Reading i0, i0+fftLen/2 inputs */ + /* Read ya (real), xa(imag) input */ + T = read_q15x2 (pSi0); + + /* Read yc (real), xc(imag) input */ + S = read_q15x2 (pSi2); + + /* R = packed( (ya + yc), (xa + xc)) */ + R = __RV_KADD16(T, S); + + /* S = packed((ya - yc), (xa - xc)) */ + S = __RV_KSUB16(T, S); + + /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */ + /* Read yb (real), xb(imag) input */ + T = read_q15x2 (pSi1); + + /* Read yd (real), xd(imag) input */ + U = read_q15x2 (pSi3); + + /* T = packed( (yb + yd), (xb + xd)) */ + T = __RV_KADD16(T, U); + + /* writing the butterfly processed i0 sample */ + + /* xa' = xa + xb + xc + xd */ + /* ya' = ya + yb + yc + yd */ + out1 = __RV_RADD16(R, T); + out1 = __RV_RADD16(out1, 0); + write_q15x2 (pSi0, out1); + pSi0 += 2 * n1; + + /* R = packed( (ya + yc) - (yb + yd), (xa + xc) - (xb + xd)) */ + R = __SHSUB16(R, T); + + /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */ + out1 = __RV_KMDA(C2, R) >> 16U; + + /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */ + out2 = __RV_KMXDA(C2, R); + + /* Reading i0+3fftLen/4 */ + /* Read yb (real), xb(imag) input */ + T = read_q15x2 (pSi1); + + /* writing the butterfly processed i0 + fftLen/4 sample */ + /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */ + /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */ + write_q15x2 (pSi1, __PKHBT( out1, out2, 0 )); + pSi1 += 2 * n1; + + /* Butterfly calculations */ + + /* Read yd (real), xd(imag) input */ + U = read_q15x2 (pSi3); + + /* T = packed(yb-yd, xb-xd) */ + T = __RV_KSUB16(T, U); + + /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */ + R = __RV_RCRAS16(S, T); + + /* S = packed((ya-yc) - (xb- xd), (xa-xc) + (yb-yd)) */ + S = __RV_RCRSA16(S, T); + + + /* Butterfly process for the i0+fftLen/2 sample */ + out1 = __RV_KMDA(C1, S) >> 16U; + out2 = __RV_KMXDA(C1, S); + + /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */ + /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */ + write_q15x2 (pSi2, __PKHBT( out1, out2, 0 )); + pSi2 += 2 * n1; + + /* Butterfly process for the i0+3fftLen/4 sample */ + + out1 = __RV_KMDA(C3, R) >> 16U; + out2 = __RV_KMXDA(C3, R); + + /* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */ + /* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */ + write_q15x2 (pSi3, __PKHBT( out1, out2, 0 )); + pSi3 += 2 * n1; + } + } + /* Twiddle coefficients index modifier */ + twidCoefModifier <<= 2U; + } + /* end of middle stage process */ + + /* data is in 10.6(q6) format for the 1024 point */ + /* data is in 8.8(q8) format for the 256 point */ + /* data is in 6.10(q10) format for the 64 point */ + /* data is in 4.12(q12) format for the 16 point */ + + /* Initializations for the last stage */ + j = fftLen >> 2; + + ptr1 = &pSrc16[0]; + + /* start of last stage process */ + + /* Butterfly implementation */ + do + { + /* Read xa (real), ya(imag) input */ + xaya = read_q15x2_ia ((q15_t **) &ptr1); + + /* Read xb (real), yb(imag) input */ + xbyb = read_q15x2_ia ((q15_t **) &ptr1); + + /* Read xc (real), yc(imag) input */ + xcyc = read_q15x2_ia ((q15_t **) &ptr1); + + /* Read xd (real), yd(imag) input */ + xdyd = read_q15x2_ia ((q15_t **) &ptr1); + + /* R = packed((ya + yc), (xa + xc)) */ + R = __RV_KADD16(xaya, xcyc); + + /* T = packed((yb + yd), (xb + xd)) */ + T = __RV_KADD16(xbyb, xdyd); + + /* pointer updation for writing */ + ptr1 = ptr1 - 8U; + + + /* xa' = xa + xb + xc + xd */ + /* ya' = ya + yb + yc + yd */ + write_q15x2_ia (&ptr1, __RV_RADD16(R, T)); + + /* T = packed((yb + yd), (xb + xd)) */ + T = __RV_KADD16(xbyb, xdyd); + + /* xc' = (xa-xb+xc-xd) */ + /* yc' = (ya-yb+yc-yd) */ + write_q15x2_ia (&ptr1, __RV_RSUB16(R, T)); + + /* S = packed((ya - yc), (xa - xc)) */ + S = __RV_KSUB16(xaya, xcyc); + + /* Read yd (real), xd(imag) input */ + /* T = packed( (yb - yd), (xb - xd)) */ + U = __RV_KSUB16(xbyb, xdyd); + + /* xb' = (xa+yb-xc-yd) */ + /* yb' = (ya-xb-yc+xd) */ + write_q15x2_ia (&ptr1, __RV_RCRSA16(S, U)); + + /* xd' = (xa-yb-xc+yd) */ + /* yd' = (ya+xb-yc-xd) */ + write_q15x2_ia (&ptr1, __RV_RCRAS16(S, U)); + + } while (--j); + + /* end of last stage process */ + + /* output is in 11.5(q5) format for the 1024 point */ + /* output is in 9.7(q7) format for the 256 point */ + /* output is in 7.9(q9) format for the 64 point */ + /* output is in 5.11(q11) format for the 16 point */ + + +#else /* riscv_radix4_butterfly_inverse_q15 */ + + q15_t R0, R1, S0, S1, T0, T1, U0, U1; + q15_t Co1, Si1, Co2, Si2, Co3, Si3, out1, out2; + uint32_t n1, n2, ic, i0, i1, i2, i3, j, k; + + /* Total process is divided into three stages */ + + /* process first stage, middle stages, & last stage */ + + /* Initializations for the first stage */ + n2 = fftLen; + n1 = n2; + + /* n2 = fftLen/4 */ + n2 >>= 2U; + + /* Index for twiddle coefficient */ + ic = 0U; + + /* Index for input read and output write */ + i0 = 0U; + + j = n2; + + /* Input is in 1.15(q15) format */ + + /* Start of first stage process */ + do + { + /* Butterfly implementation */ + + /* index calculation for the input as, */ + /* pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* Reading i0, i0+fftLen/2 inputs */ + /* input is down scale by 4 to avoid overflow */ + /* Read ya (real), xa(imag) input */ + T0 = pSrc16[i0 * 2U] >> 2U; + T1 = pSrc16[(i0 * 2U) + 1U] >> 2U; + /* input is down scale by 4 to avoid overflow */ + /* Read yc (real), xc(imag) input */ + S0 = pSrc16[i2 * 2U] >> 2U; + S1 = pSrc16[(i2 * 2U) + 1U] >> 2U; + + /* R0 = (ya + yc), R1 = (xa + xc) */ + R0 = __SSAT(T0 + S0, 16U); + R1 = __SSAT(T1 + S1, 16U); + /* S0 = (ya - yc), S1 = (xa - xc) */ + S0 = __SSAT(T0 - S0, 16U); + S1 = __SSAT(T1 - S1, 16U); + + /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */ + /* input is down scale by 4 to avoid overflow */ + /* Read yb (real), xb(imag) input */ + T0 = pSrc16[i1 * 2U] >> 2U; + T1 = pSrc16[(i1 * 2U) + 1U] >> 2U; + /* Read yd (real), xd(imag) input */ + /* input is down scale by 4 to avoid overflow */ + U0 = pSrc16[i3 * 2U] >> 2U; + U1 = pSrc16[(i3 * 2U) + 1U] >> 2U; + + /* T0 = (yb + yd), T1 = (xb + xd) */ + T0 = __SSAT(T0 + U0, 16U); + T1 = __SSAT(T1 + U1, 16U); + + /* writing the butterfly processed i0 sample */ + /* xa' = xa + xb + xc + xd */ + /* ya' = ya + yb + yc + yd */ + pSrc16[i0 * 2U] = (R0 >> 1U) + (T0 >> 1U); + pSrc16[(i0 * 2U) + 1U] = (R1 >> 1U) + (T1 >> 1U); + + /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc)- (xb + xd) */ + R0 = __SSAT(R0 - T0, 16U); + R1 = __SSAT(R1 - T1, 16U); + /* co2 & si2 are read from Coefficient pointer */ + Co2 = pCoef16[2U * ic * 2U]; + Si2 = pCoef16[(2U * ic * 2U) + 1U]; + /* xc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2) */ + out1 = (q15_t) ((Co2 * R0 - Si2 * R1) >> 16U); + /* yc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2) */ + out2 = (q15_t) ((Si2 * R0 + Co2 * R1) >> 16U); + + /* Reading i0+fftLen/4 */ + /* input is down scale by 4 to avoid overflow */ + /* T0 = yb, T1 = xb */ + T0 = pSrc16[i1 * 2U] >> 2U; + T1 = pSrc16[(i1 * 2U) + 1U] >> 2U; + + /* writing the butterfly processed i0 + fftLen/4 sample */ + /* writing output(xc', yc') in little endian format */ + pSrc16[i1 * 2U] = out1; + pSrc16[(i1 * 2U) + 1U] = out2; + + /* Butterfly calculations */ + /* input is down scale by 4 to avoid overflow */ + /* U0 = yd, U1 = xd) */ + U0 = pSrc16[i3 * 2U] >> 2U; + U1 = pSrc16[(i3 * 2U) + 1U] >> 2U; + + /* T0 = yb-yd, T1 = xb-xd) */ + T0 = __SSAT(T0 - U0, 16U); + T1 = __SSAT(T1 - U1, 16U); + /* R0 = (ya-yc) - (xb- xd) , R1 = (xa-xc) + (yb-yd) */ + R0 = (q15_t) __SSAT((q31_t) (S0 + T1), 16); + R1 = (q15_t) __SSAT((q31_t) (S1 - T0), 16); + /* S = (ya-yc) + (xb- xd), S1 = (xa-xc) - (yb-yd) */ + S0 = (q15_t) __SSAT((q31_t) (S0 - T1), 16); + S1 = (q15_t) __SSAT((q31_t) (S1 + T0), 16); + + /* co1 & si1 are read from Coefficient pointer */ + Co1 = pCoef16[ic * 2U]; + Si1 = pCoef16[(ic * 2U) + 1U]; + /* Butterfly process for the i0+fftLen/2 sample */ + /* xb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1) */ + out1 = (q15_t) ((Co1 * S0 - Si1 * S1) >> 16U); + /* yb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1) */ + out2 = (q15_t) ((Si1 * S0 + Co1 * S1) >> 16U); + /* writing output(xb', yb') in little endian format */ + pSrc16[i2 * 2U] = out1; + pSrc16[(i2 * 2U) + 1U] = out2; + + /* Co3 & si3 are read from Coefficient pointer */ + Co3 = pCoef16[3U * ic * 2U]; + Si3 = pCoef16[(3U * ic * 2U) + 1U]; + /* Butterfly process for the i0+3fftLen/4 sample */ + /* xd' = (xa+yb-xc-yd)* Co3 - (ya-xb-yc+xd)* (si3) */ + out1 = (q15_t) ((Co3 * R0 - Si3 * R1) >> 16U); + /* yd' = (ya-xb-yc+xd)* Co3 + (xa+yb-xc-yd)* (si3) */ + out2 = (q15_t) ((Si3 * R0 + Co3 * R1) >> 16U); + /* writing output(xd', yd') in little endian format */ + pSrc16[i3 * 2U] = out1; + pSrc16[(i3 * 2U) + 1U] = out2; + + /* Twiddle coefficients index modifier */ + ic = ic + twidCoefModifier; + + /* Updating input index */ + i0 = i0 + 1U; + + } while (--j); + + /* End of first stage process */ + + /* data is in 4.11(q11) format */ + + + /* Start of Middle stage process */ + + /* Twiddle coefficients index modifier */ + twidCoefModifier <<= 2U; + + /* Calculation of Middle stage */ + for (k = fftLen / 4U; k > 4U; k >>= 2U) + { + /* Initializations for the middle stage */ + n1 = n2; + n2 >>= 2U; + ic = 0U; + + for (j = 0U; j <= (n2 - 1U); j++) + { + /* index calculation for the coefficients */ + Co1 = pCoef16[ic * 2U]; + Si1 = pCoef16[(ic * 2U) + 1U]; + Co2 = pCoef16[2U * ic * 2U]; + Si2 = pCoef16[2U * ic * 2U + 1U]; + Co3 = pCoef16[3U * ic * 2U]; + Si3 = pCoef16[(3U * ic * 2U) + 1U]; + + /* Twiddle coefficients index modifier */ + ic = ic + twidCoefModifier; + + /* Butterfly implementation */ + for (i0 = j; i0 < fftLen; i0 += n1) + { + /* index calculation for the input as, */ + /* pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* Reading i0, i0+fftLen/2 inputs */ + /* Read ya (real), xa(imag) input */ + T0 = pSrc16[i0 * 2U]; + T1 = pSrc16[(i0 * 2U) + 1U]; + + /* Read yc (real), xc(imag) input */ + S0 = pSrc16[i2 * 2U]; + S1 = pSrc16[(i2 * 2U) + 1U]; + + + /* R0 = (ya + yc), R1 = (xa + xc) */ + R0 = __SSAT(T0 + S0, 16U); + R1 = __SSAT(T1 + S1, 16U); + /* S0 = (ya - yc), S1 = (xa - xc) */ + S0 = __SSAT(T0 - S0, 16U); + S1 = __SSAT(T1 - S1, 16U); + + /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */ + /* Read yb (real), xb(imag) input */ + T0 = pSrc16[i1 * 2U]; + T1 = pSrc16[(i1 * 2U) + 1U]; + + /* Read yd (real), xd(imag) input */ + U0 = pSrc16[i3 * 2U]; + U1 = pSrc16[(i3 * 2U) + 1U]; + + /* T0 = (yb + yd), T1 = (xb + xd) */ + T0 = __SSAT(T0 + U0, 16U); + T1 = __SSAT(T1 + U1, 16U); + + /* writing the butterfly processed i0 sample */ + /* xa' = xa + xb + xc + xd */ + /* ya' = ya + yb + yc + yd */ + pSrc16[i0 * 2U] = ((R0 >> 1U) + (T0 >> 1U)) >> 1U; + pSrc16[(i0 * 2U) + 1U] = ((R1 >> 1U) + (T1 >> 1U)) >> 1U; + + /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc) - (xb + xd) */ + R0 = (R0 >> 1U) - (T0 >> 1U); + R1 = (R1 >> 1U) - (T1 >> 1U); + + /* (ya-yb+yc-yd)* (si2) - (xa-xb+xc-xd)* co2 */ + out1 = (q15_t) ((Co2 * R0 - Si2 * R1) >> 16); + /* (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2) */ + out2 = (q15_t) ((Si2 * R0 + Co2 * R1) >> 16); + + /* Reading i0+3fftLen/4 */ + /* Read yb (real), xb(imag) input */ + T0 = pSrc16[i1 * 2U]; + T1 = pSrc16[(i1 * 2U) + 1U]; + + /* writing the butterfly processed i0 + fftLen/4 sample */ + /* xc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2) */ + /* yc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2) */ + pSrc16[i1 * 2U] = out1; + pSrc16[(i1 * 2U) + 1U] = out2; + + /* Butterfly calculations */ + /* Read yd (real), xd(imag) input */ + U0 = pSrc16[i3 * 2U]; + U1 = pSrc16[(i3 * 2U) + 1U]; + + /* T0 = yb-yd, T1 = xb-xd) */ + T0 = __SSAT(T0 - U0, 16U); + T1 = __SSAT(T1 - U1, 16U); + + /* R0 = (ya-yc) - (xb- xd) , R1 = (xa-xc) + (yb-yd) */ + R0 = (S0 >> 1U) + (T1 >> 1U); + R1 = (S1 >> 1U) - (T0 >> 1U); + + /* S1 = (ya-yc) + (xb- xd), S1 = (xa-xc) - (yb-yd) */ + S0 = (S0 >> 1U) - (T1 >> 1U); + S1 = (S1 >> 1U) + (T0 >> 1U); + + /* Butterfly process for the i0+fftLen/2 sample */ + out1 = (q15_t) ((Co1 * S0 - Si1 * S1) >> 16U); + out2 = (q15_t) ((Si1 * S0 + Co1 * S1) >> 16U); + /* xb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1) */ + /* yb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1) */ + pSrc16[i2 * 2U] = out1; + pSrc16[(i2 * 2U) + 1U] = out2; + + /* Butterfly process for the i0+3fftLen/4 sample */ + out1 = (q15_t) ((Co3 * R0 - Si3 * R1) >> 16U); + + out2 = (q15_t) ((Si3 * R0 + Co3 * R1) >> 16U); + /* xd' = (xa+yb-xc-yd)* Co3 - (ya-xb-yc+xd)* (si3) */ + /* yd' = (ya-xb-yc+xd)* Co3 + (xa+yb-xc-yd)* (si3) */ + pSrc16[i3 * 2U] = out1; + pSrc16[(i3 * 2U) + 1U] = out2; + + + } + } + /* Twiddle coefficients index modifier */ + twidCoefModifier <<= 2U; + } + /* End of Middle stages process */ + + + /* data is in 10.6(q6) format for the 1024 point */ + /* data is in 8.8(q8) format for the 256 point */ + /* data is in 6.10(q10) format for the 64 point */ + /* data is in 4.12(q12) format for the 16 point */ + + /* start of last stage process */ + + + /* Initializations for the last stage */ + n1 = n2; + n2 >>= 2U; + + /* Butterfly implementation */ + for (i0 = 0U; i0 <= (fftLen - n1); i0 += n1) + { + /* index calculation for the input as, */ + /* pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* Reading i0, i0+fftLen/2 inputs */ + /* Read ya (real), xa(imag) input */ + T0 = pSrc16[i0 * 2U]; + T1 = pSrc16[(i0 * 2U) + 1U]; + /* Read yc (real), xc(imag) input */ + S0 = pSrc16[i2 * 2U]; + S1 = pSrc16[(i2 * 2U) + 1U]; + + /* R0 = (ya + yc), R1 = (xa + xc) */ + R0 = __SSAT(T0 + S0, 16U); + R1 = __SSAT(T1 + S1, 16U); + /* S0 = (ya - yc), S1 = (xa - xc) */ + S0 = __SSAT(T0 - S0, 16U); + S1 = __SSAT(T1 - S1, 16U); + + /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */ + /* Read yb (real), xb(imag) input */ + T0 = pSrc16[i1 * 2U]; + T1 = pSrc16[(i1 * 2U) + 1U]; + /* Read yd (real), xd(imag) input */ + U0 = pSrc16[i3 * 2U]; + U1 = pSrc16[(i3 * 2U) + 1U]; + + /* T0 = (yb + yd), T1 = (xb + xd) */ + T0 = __SSAT(T0 + U0, 16U); + T1 = __SSAT(T1 + U1, 16U); + + /* writing the butterfly processed i0 sample */ + /* xa' = xa + xb + xc + xd */ + /* ya' = ya + yb + yc + yd */ + pSrc16[i0 * 2U] = (R0 >> 1U) + (T0 >> 1U); + pSrc16[(i0 * 2U) + 1U] = (R1 >> 1U) + (T1 >> 1U); + + /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc) - (xb + xd) */ + R0 = (R0 >> 1U) - (T0 >> 1U); + R1 = (R1 >> 1U) - (T1 >> 1U); + + /* Read yb (real), xb(imag) input */ + T0 = pSrc16[i1 * 2U]; + T1 = pSrc16[(i1 * 2U) + 1U]; + + /* writing the butterfly processed i0 + fftLen/4 sample */ + /* xc' = (xa-xb+xc-xd) */ + /* yc' = (ya-yb+yc-yd) */ + pSrc16[i1 * 2U] = R0; + pSrc16[(i1 * 2U) + 1U] = R1; + + /* Read yd (real), xd(imag) input */ + U0 = pSrc16[i3 * 2U]; + U1 = pSrc16[(i3 * 2U) + 1U]; + /* T0 = (yb - yd), T1 = (xb - xd) */ + T0 = __SSAT(T0 - U0, 16U); + T1 = __SSAT(T1 - U1, 16U); + + /* writing the butterfly processed i0 + fftLen/2 sample */ + /* xb' = (xa-yb-xc+yd) */ + /* yb' = (ya+xb-yc-xd) */ + pSrc16[i2 * 2U] = (S0 >> 1U) - (T1 >> 1U); + pSrc16[(i2 * 2U) + 1U] = (S1 >> 1U) + (T0 >> 1U); + + + /* writing the butterfly processed i0 + 3fftLen/4 sample */ + /* xd' = (xa+yb-xc-yd) */ + /* yd' = (ya-xb-yc+xd) */ + pSrc16[i3 * 2U] = (S0 >> 1U) + (T1 >> 1U); + pSrc16[(i3 * 2U) + 1U] = (S1 >> 1U) - (T0 >> 1U); + } + /* end of last stage process */ + + /* output is in 11.5(q5) format for the 1024 point */ + /* output is in 9.7(q7) format for the 256 point */ + /* output is in 7.9(q9) format for the 64 point */ + /* output is in 5.11(q11) format for the 16 point */ + +#endif /* #if defined (RISCV_MATH_DSP) */ + +} diff --git a/components/nmsis/dsp/src/TransformFunctions/riscv_cfft_radix4_q31.c b/components/nmsis/dsp/src/TransformFunctions/riscv_cfft_radix4_q31.c new file mode 100644 index 00000000..51203ca2 --- /dev/null +++ b/components/nmsis/dsp/src/TransformFunctions/riscv_cfft_radix4_q31.c @@ -0,0 +1,878 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_cfft_radix4_q31.c + * Description: This file has function definition of Radix-4 FFT & IFFT function and + * In-place bit reversal using bit reversal table + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" + +void riscv_radix4_butterfly_inverse_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pCoef, + uint32_t twidCoefModifier); + +void riscv_radix4_butterfly_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pCoef, + uint32_t twidCoefModifier); + +void riscv_bitreversal_q31( + q31_t * pSrc, + uint32_t fftLen, + uint16_t bitRevFactor, + const uint16_t * pBitRevTab); + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Processing function for the Q31 CFFT/CIFFT. + @deprecated Do not use this function. It has been superseded by \ref riscv_cfft_q31 and will be removed in the future. + @param[in] S points to an instance of the Q31 CFFT/CIFFT structure + @param[in,out] pSrc points to the complex data buffer of size 2*fftLen. Processing occurs in-place + @return none + + @par Input and output formats: + Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process. + Hence the output format is different for different FFT sizes. + The input and output formats for different FFT sizes and number of bits to upscale are mentioned in the tables below for CFFT and CIFFT: + @par + \image html CFFTQ31.png "Input and Output Formats for Q31 CFFT" + \image html CIFFTQ31.png "Input and Output Formats for Q31 CIFFT" + */ + +void riscv_cfft_radix4_q31( + const riscv_cfft_radix4_instance_q31 * S, + q31_t * pSrc) +{ + if (S->ifftFlag == 1U) + { + /* Complex IFFT radix-4 */ + riscv_radix4_butterfly_inverse_q31(pSrc, S->fftLen, S->pTwiddle, S->twidCoefModifier); + } + else + { + /* Complex FFT radix-4 */ + riscv_radix4_butterfly_q31(pSrc, S->fftLen, S->pTwiddle, S->twidCoefModifier); + } + + if (S->bitReverseFlag == 1U) + { + /* Bit Reversal */ + riscv_bitreversal_q31(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable); + } + +} + +/** + @} end of ComplexFFT group + */ + +/* + * Radix-4 FFT algorithm used is : + * + * Input real and imaginary data: + * x(n) = xa + j * ya + * x(n+N/4 ) = xb + j * yb + * x(n+N/2 ) = xc + j * yc + * x(n+3N 4) = xd + j * yd + * + * + * Output real and imaginary data: + * x(4r) = xa'+ j * ya' + * x(4r+1) = xb'+ j * yb' + * x(4r+2) = xc'+ j * yc' + * x(4r+3) = xd'+ j * yd' + * + * + * Twiddle factors for radix-4 FFT: + * Wn = co1 + j * (- si1) + * W2n = co2 + j * (- si2) + * W3n = co3 + j * (- si3) + * + * Butterfly implementation: + * xa' = xa + xb + xc + xd + * ya' = ya + yb + yc + yd + * xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) + * yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) + * xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) + * yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) + * xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) + * yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) + * + */ + +/** + @brief Core function for the Q31 CFFT butterfly process. + @param[in,out] pSrc points to the in-place buffer of Q31 data type. + @param[in] fftLen length of the FFT. + @param[in] pCoef points to twiddle coefficient buffer. + @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + @return none + */ + +void riscv_radix4_butterfly_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pCoef, + uint32_t twidCoefModifier) +{ + uint32_t n1, n2, ia1, ia2, ia3, i0, i1, i2, i3, j, k; + q31_t t1, t2, r1, r2, s1, s2, co1, co2, co3, si1, si2, si3; + + q31_t xa, xb, xc, xd; + q31_t ya, yb, yc, yd; + q31_t xa_out, xb_out, xc_out, xd_out; + q31_t ya_out, yb_out, yc_out, yd_out; + + q31_t *ptr1; +#if __RISCV_XLEN == 64 + q63_t xa64, xb64, xc64, xd64; + q63_t xa_out64; +#endif /* __RISCV_XLEN == 64 */ + /* Total process is divided into three stages */ + + /* process first stage, middle stages, & last stage */ + + + /* start of first stage process */ + + /* Initializations for the first stage */ + n2 = fftLen; + n1 = n2; + /* n2 = fftLen/4 */ + n2 >>= 2U; + i0 = 0U; + ia1 = 0U; + + j = n2; + + /* Calculation of first stage */ + do + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2U], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* input is in 1.31(q31) format and provide 4 guard bits for the input */ + + /* Butterfly implementation */ + /* xa + xc */ + r1 = (pSrc[(2U * i0)] >> 4U) + (pSrc[(2U * i2)] >> 4U); + /* xa - xc */ + r2 = (pSrc[(2U * i0)] >> 4U) - (pSrc[(2U * i2)] >> 4U); + + /* xb + xd */ + t1 = (pSrc[(2U * i1)] >> 4U) + (pSrc[(2U * i3)] >> 4U); + + /* ya + yc */ + s1 = (pSrc[(2U * i0) + 1U] >> 4U) + (pSrc[(2U * i2) + 1U] >> 4U); + /* ya - yc */ + s2 = (pSrc[(2U * i0) + 1U] >> 4U) - (pSrc[(2U * i2) + 1U] >> 4U); + + /* xa' = xa + xb + xc + xd */ + pSrc[2U * i0] = (r1 + t1); + /* (xa + xc) - (xb + xd) */ + r1 = r1 - t1; + /* yb + yd */ + t2 = (pSrc[(2U * i1) + 1U] >> 4U) + (pSrc[(2U * i3) + 1U] >> 4U); + + /* ya' = ya + yb + yc + yd */ + pSrc[(2U * i0) + 1U] = (s1 + t2); + + /* (ya + yc) - (yb + yd) */ + s1 = s1 - t2; + + /* yb - yd */ + t1 = (pSrc[(2U * i1) + 1U] >> 4U) - (pSrc[(2U * i3) + 1U] >> 4U); + /* xb - xd */ + t2 = (pSrc[(2U * i1)] >> 4U) - (pSrc[(2U * i3)] >> 4U); + + /* index calculation for the coefficients */ + ia2 = 2U * ia1; + co2 = pCoef[(ia2 * 2U)]; + si2 = pCoef[(ia2 * 2U) + 1U]; + + /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = (((int32_t) (((q63_t) r1 * co2) >> 32)) + + ((int32_t) (((q63_t) s1 * si2) >> 32))) << 1U; + + /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = (((int32_t) (((q63_t) s1 * co2) >> 32)) - + ((int32_t) (((q63_t) r1 * si2) >> 32))) << 1U; + + /* (xa - xc) + (yb - yd) */ + r1 = r2 + t1; + /* (xa - xc) - (yb - yd) */ + r2 = r2 - t1; + + /* (ya - yc) - (xb - xd) */ + s1 = s2 - t2; + /* (ya - yc) + (xb - xd) */ + s2 = s2 + t2; + + co1 = pCoef[(ia1 * 2U)]; + si1 = pCoef[(ia1 * 2U) + 1U]; + + /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = (((int32_t) (((q63_t) r1 * co1) >> 32)) + + ((int32_t) (((q63_t) s1 * si1) >> 32))) << 1U; + + /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = (((int32_t) (((q63_t) s1 * co1) >> 32)) - + ((int32_t) (((q63_t) r1 * si1) >> 32))) << 1U; + + /* index calculation for the coefficients */ + ia3 = 3U * ia1; + co3 = pCoef[(ia3 * 2U)]; + si3 = pCoef[(ia3 * 2U) + 1U]; + + /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = (((int32_t) (((q63_t) r2 * co3) >> 32)) + + ((int32_t) (((q63_t) s2 * si3) >> 32))) << 1U; + + /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = (((int32_t) (((q63_t) s2 * co3) >> 32)) - + ((int32_t) (((q63_t) r2 * si3) >> 32))) << 1U; + + /* Twiddle coefficients index modifier */ + ia1 = ia1 + twidCoefModifier; + + /* Updating input index */ + i0 = i0 + 1U; + + } while (--j); + + /* end of first stage process */ + + /* data is in 5.27(q27) format */ + + + /* start of Middle stages process */ + + + /* each stage in middle stages provides two down scaling of the input */ + + twidCoefModifier <<= 2U; + + + for (k = fftLen / 4U; k > 4U; k >>= 2U) + { + /* Initializations for the first stage */ + n1 = n2; + n2 >>= 2U; + ia1 = 0U; + + /* Calculation of first stage */ + for (j = 0U; j <= (n2 - 1U); j++) + { + /* index calculation for the coefficients */ + ia2 = ia1 + ia1; + ia3 = ia2 + ia1; + co1 = pCoef[(ia1 * 2U)]; + si1 = pCoef[(ia1 * 2U) + 1U]; + co2 = pCoef[(ia2 * 2U)]; + si2 = pCoef[(ia2 * 2U) + 1U]; + co3 = pCoef[(ia3 * 2U)]; + si3 = pCoef[(ia3 * 2U) + 1U]; + /* Twiddle coefficients index modifier */ + ia1 = ia1 + twidCoefModifier; + + for (i0 = j; i0 < fftLen; i0 += n1) + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2U], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* Butterfly implementation */ + /* xa + xc */ + r1 = pSrc[2U * i0] + pSrc[2U * i2]; + /* xa - xc */ + r2 = pSrc[2U * i0] - pSrc[2U * i2]; + + /* ya + yc */ + s1 = pSrc[(2U * i0) + 1U] + pSrc[(2U * i2) + 1U]; + /* ya - yc */ + s2 = pSrc[(2U * i0) + 1U] - pSrc[(2U * i2) + 1U]; + + /* xb + xd */ + t1 = pSrc[2U * i1] + pSrc[2U * i3]; + + /* xa' = xa + xb + xc + xd */ + pSrc[2U * i0] = (r1 + t1) >> 2U; + /* xa + xc -(xb + xd) */ + r1 = r1 - t1; + + /* yb + yd */ + t2 = pSrc[(2U * i1) + 1U] + pSrc[(2U * i3) + 1U]; + /* ya' = ya + yb + yc + yd */ + pSrc[(2U * i0) + 1U] = (s1 + t2) >> 2U; + + /* (ya + yc) - (yb + yd) */ + s1 = s1 - t2; + + /* (yb - yd) */ + t1 = pSrc[(2U * i1) + 1U] - pSrc[(2U * i3) + 1U]; + /* (xb - xd) */ + t2 = pSrc[2U * i1] - pSrc[2U * i3]; + + /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = (((int32_t) (((q63_t) r1 * co2) >> 32)) + + ((int32_t) (((q63_t) s1 * si2) >> 32))) >> 1U; + + /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = (((int32_t) (((q63_t) s1 * co2) >> 32)) - + ((int32_t) (((q63_t) r1 * si2) >> 32))) >> 1U; + + /* (xa - xc) + (yb - yd) */ + r1 = r2 + t1; + /* (xa - xc) - (yb - yd) */ + r2 = r2 - t1; + + /* (ya - yc) - (xb - xd) */ + s1 = s2 - t2; + /* (ya - yc) + (xb - xd) */ + s2 = s2 + t2; + + /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = (((int32_t) (((q63_t) r1 * co1) >> 32)) + + ((int32_t) (((q63_t) s1 * si1) >> 32))) >> 1U; + + /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = (((int32_t) (((q63_t) s1 * co1) >> 32)) - + ((int32_t) (((q63_t) r1 * si1) >> 32))) >> 1U; + + /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = (((int32_t) (((q63_t) r2 * co3) >> 32)) + + ((int32_t) (((q63_t) s2 * si3) >> 32))) >> 1U; + + /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = (((int32_t) (((q63_t) s2 * co3) >> 32)) - + ((int32_t) (((q63_t) r2 * si3) >> 32))) >> 1U; + } + } + twidCoefModifier <<= 2U; + } + + /* End of Middle stages process */ + + /* data is in 11.21(q21) format for the 1024 point as there are 3 middle stages */ + /* data is in 9.23(q23) format for the 256 point as there are 2 middle stages */ + /* data is in 7.25(q25) format for the 64 point as there are 1 middle stage */ + /* data is in 5.27(q27) format for the 16 point as there are no middle stages */ + + + /* start of Last stage process */ + /* Initializations for the last stage */ + j = fftLen >> 2; + ptr1 = &pSrc[0]; + + /* Calculations of last stage */ + do + { +#if defined RISCV_MATH_DSP && (__RISCV_XLEN == 64) + xa64 = read_q31x2_ia((q31_t **)&ptr1); + xb64 = read_q31x2_ia((q31_t **)&ptr1); + xc64 = read_q31x2_ia((q31_t **)&ptr1); + xd64 = read_q31x2_ia((q31_t **)&ptr1); + /* xa' = xa + xb + xc + xd */ /* ya' = ya + yb + yc + yd */ + xa_out64 = __RV_KADD32( __RV_KADD32( __RV_KADD32(xa64, xb64), xc64), xd64); + /* pointer updation for writing */ + ptr1 = ptr1 - 8U; + write_q31x2_ia((q31_t **)&ptr1, xa_out64); + /* xc_out = (xa - xb + xc - xd);yc_out = (ya - yb + yc - yd);*/ + xa_out64 = __RV_KSUB32( __RV_KADD32( __RV_KSUB32(xa64, xb64), xc64), xd64); + write_q31x2_ia((q31_t **)&ptr1, xa_out64); + /* xb_out = (xa + yb - xc - yd);yb_out = (ya - xb - yc + xd);*/ + xa_out64 = __RV_KCRAS32( __RV_KSUB32( __RV_KCRSA32(xa64, xb64), xc64), xd64); + write_q31x2_ia((q31_t **)&ptr1, xa_out64); + /* xd_out = (xa - yb - xc + yd); yd_out = (ya + xb - yc - xd);*/ + xa_out64 = __RV_KCRSA32( __RV_KSUB32( __RV_KCRAS32(xa64, xb64), xc64), xd64); + write_q31x2_ia((q31_t **)&ptr1, xa_out64); + +#else + /* Read xa (real), ya(imag) input */ + xa = *ptr1++; + ya = *ptr1++; + + /* Read xb (real), yb(imag) input */ + xb = *ptr1++; + yb = *ptr1++; + + /* Read xc (real), yc(imag) input */ + xc = *ptr1++; + yc = *ptr1++; + + /* Read xd (real), yd(imag) input */ + xd = *ptr1++; + yd = *ptr1++; + + /* xa' = xa + xb + xc + xd */ + xa_out = xa + xb + xc + xd; + + /* ya' = ya + yb + yc + yd */ + ya_out = ya + yb + yc + yd; + + /* pointer updation for writing */ + ptr1 = ptr1 - 8U; + + /* writing xa' and ya' */ + *ptr1++ = xa_out; + *ptr1++ = ya_out; + + xc_out = (xa - xb + xc - xd); + yc_out = (ya - yb + yc - yd); + + /* writing xc' and yc' */ + *ptr1++ = xc_out; + *ptr1++ = yc_out; + + xb_out = (xa + yb - xc - yd); + yb_out = (ya - xb - yc + xd); + + /* writing xb' and yb' */ + *ptr1++ = xb_out; + *ptr1++ = yb_out; + + xd_out = (xa - yb - xc + yd); + yd_out = (ya + xb - yc - xd); + + /* writing xd' and yd' */ + *ptr1++ = xd_out; + *ptr1++ = yd_out; + +#endif /* __RISCV_XLEN == 64 */ + + } while (--j); + + /* output is in 11.21(q21) format for the 1024 point */ + /* output is in 9.23(q23) format for the 256 point */ + /* output is in 7.25(q25) format for the 64 point */ + /* output is in 5.27(q27) format for the 16 point */ + + /* End of last stage process */ + +} + + +/** + @brief Core function for the Q31 CIFFT butterfly process. + @param[in,out] pSrc points to the in-place buffer of Q31 data type. + @param[in] fftLen length of the FFT. + @param[in] pCoef points to twiddle coefficient buffer. + @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + @return none + */ + +/* + * Radix-4 IFFT algorithm used is : + * + * CIFFT uses same twiddle coefficients as CFFT Function + * x[k] = x[n] + (j)k * x[n + fftLen/4] + (-1)k * x[n+fftLen/2] + (-j)k * x[n+3*fftLen/4] + * + * + * IFFT is implemented with following changes in equations from FFT + * + * Input real and imaginary data: + * x(n) = xa + j * ya + * x(n+N/4 ) = xb + j * yb + * x(n+N/2 ) = xc + j * yc + * x(n+3N 4) = xd + j * yd + * + * + * Output real and imaginary data: + * x(4r) = xa'+ j * ya' + * x(4r+1) = xb'+ j * yb' + * x(4r+2) = xc'+ j * yc' + * x(4r+3) = xd'+ j * yd' + * + * + * Twiddle factors for radix-4 IFFT: + * Wn = co1 + j * (si1) + * W2n = co2 + j * (si2) + * W3n = co3 + j * (si3) + + * The real and imaginary output values for the radix-4 butterfly are + * xa' = xa + xb + xc + xd + * ya' = ya + yb + yc + yd + * xb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1) + * yb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1) + * xc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2) + * yc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2) + * xd' = (xa+yb-xc-yd)* co3 - (ya-xb-yc+xd)* (si3) + * yd' = (ya-xb-yc+xd)* co3 + (xa+yb-xc-yd)* (si3) + * + */ + +void riscv_radix4_butterfly_inverse_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pCoef, + uint32_t twidCoefModifier) +{ + uint32_t n1, n2, ia1, ia2, ia3, i0, i1, i2, i3, j, k; + q31_t t1, t2, r1, r2, s1, s2, co1, co2, co3, si1, si2, si3; + q31_t xa, xb, xc, xd; + q31_t ya, yb, yc, yd; + q31_t xa_out, xb_out, xc_out, xd_out; + q31_t ya_out, yb_out, yc_out, yd_out; + + q31_t *ptr1; +#if __RISCV_XLEN == 64 + q63_t xa64, xb64, xc64, xd64; + q63_t xa_out64; +#endif /* __RISCV_XLEN == 64 */ + /* input is be 1.31(q31) format for all FFT sizes */ + /* Total process is divided into three stages */ + /* process first stage, middle stages, & last stage */ + + /* Start of first stage process */ + + /* Initializations for the first stage */ + n2 = fftLen; + n1 = n2; + /* n2 = fftLen/4 */ + n2 >>= 2U; + i0 = 0U; + ia1 = 0U; + + j = n2; + + do + { + /* input is in 1.31(q31) format and provide 4 guard bits for the input */ + + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2U], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* Butterfly implementation */ + /* xa + xc */ + r1 = (pSrc[2U * i0] >> 4U) + (pSrc[2U * i2] >> 4U); + /* xa - xc */ + r2 = (pSrc[2U * i0] >> 4U) - (pSrc[2U * i2] >> 4U); + + /* xb + xd */ + t1 = (pSrc[2U * i1] >> 4U) + (pSrc[2U * i3] >> 4U); + + /* ya + yc */ + s1 = (pSrc[(2U * i0) + 1U] >> 4U) + (pSrc[(2U * i2) + 1U] >> 4U); + /* ya - yc */ + s2 = (pSrc[(2U * i0) + 1U] >> 4U) - (pSrc[(2U * i2) + 1U] >> 4U); + + /* xa' = xa + xb + xc + xd */ + pSrc[2U * i0] = (r1 + t1); + /* (xa + xc) - (xb + xd) */ + r1 = r1 - t1; + /* yb + yd */ + t2 = (pSrc[(2U * i1) + 1U] >> 4U) + (pSrc[(2U * i3) + 1U] >> 4U); + /* ya' = ya + yb + yc + yd */ + pSrc[(2U * i0) + 1U] = (s1 + t2); + + /* (ya + yc) - (yb + yd) */ + s1 = s1 - t2; + + /* yb - yd */ + t1 = (pSrc[(2U * i1) + 1U] >> 4U) - (pSrc[(2U * i3) + 1U] >> 4U); + /* xb - xd */ + t2 = (pSrc[2U * i1] >> 4U) - (pSrc[2U * i3] >> 4U); + + /* index calculation for the coefficients */ + ia2 = 2U * ia1; + co2 = pCoef[ia2 * 2U]; + si2 = pCoef[(ia2 * 2U) + 1U]; + + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = (((int32_t) (((q63_t) r1 * co2) >> 32)) - + ((int32_t) (((q63_t) s1 * si2) >> 32))) << 1U; + + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + pSrc[2U * i1 + 1U] = (((int32_t) (((q63_t) s1 * co2) >> 32)) + + ((int32_t) (((q63_t) r1 * si2) >> 32))) << 1U; + + /* (xa - xc) - (yb - yd) */ + r1 = r2 - t1; + /* (xa - xc) + (yb - yd) */ + r2 = r2 + t1; + + /* (ya - yc) + (xb - xd) */ + s1 = s2 + t2; + /* (ya - yc) - (xb - xd) */ + s2 = s2 - t2; + + co1 = pCoef[ia1 * 2U]; + si1 = pCoef[(ia1 * 2U) + 1U]; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = (((int32_t) (((q63_t) r1 * co1) >> 32)) - + ((int32_t) (((q63_t) s1 * si1) >> 32))) << 1U; + + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = (((int32_t) (((q63_t) s1 * co1) >> 32)) + + ((int32_t) (((q63_t) r1 * si1) >> 32))) << 1U; + + /* index calculation for the coefficients */ + ia3 = 3U * ia1; + co3 = pCoef[ia3 * 2U]; + si3 = pCoef[(ia3 * 2U) + 1U]; + + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = (((int32_t) (((q63_t) r2 * co3) >> 32)) - + ((int32_t) (((q63_t) s2 * si3) >> 32))) << 1U; + + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = (((int32_t) (((q63_t) s2 * co3) >> 32)) + + ((int32_t) (((q63_t) r2 * si3) >> 32))) << 1U; + + /* Twiddle coefficients index modifier */ + ia1 = ia1 + twidCoefModifier; + + /* Updating input index */ + i0 = i0 + 1U; + + } while (--j); + + /* data is in 5.27(q27) format */ + /* each stage provides two down scaling of the input */ + + + /* Start of Middle stages process */ + + twidCoefModifier <<= 2U; + + /* Calculation of second stage to excluding last stage */ + for (k = fftLen / 4U; k > 4U; k >>= 2U) + { + /* Initializations for the first stage */ + n1 = n2; + n2 >>= 2U; + ia1 = 0U; + + for (j = 0; j <= (n2 - 1U); j++) + { + /* index calculation for the coefficients */ + ia2 = ia1 + ia1; + ia3 = ia2 + ia1; + co1 = pCoef[(ia1 * 2U)]; + si1 = pCoef[(ia1 * 2U) + 1U]; + co2 = pCoef[(ia2 * 2U)]; + si2 = pCoef[(ia2 * 2U) + 1U]; + co3 = pCoef[(ia3 * 2U)]; + si3 = pCoef[(ia3 * 2U) + 1U]; + /* Twiddle coefficients index modifier */ + ia1 = ia1 + twidCoefModifier; + + for (i0 = j; i0 < fftLen; i0 += n1) + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2U], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* Butterfly implementation */ + /* xa + xc */ + r1 = pSrc[2U * i0] + pSrc[2U * i2]; + /* xa - xc */ + r2 = pSrc[2U * i0] - pSrc[2U * i2]; + + /* ya + yc */ + s1 = pSrc[(2U * i0) + 1U] + pSrc[(2U * i2) + 1U]; + /* ya - yc */ + s2 = pSrc[(2U * i0) + 1U] - pSrc[(2U * i2) + 1U]; + + /* xb + xd */ + t1 = pSrc[2U * i1] + pSrc[2U * i3]; + + /* xa' = xa + xb + xc + xd */ + pSrc[2U * i0] = (r1 + t1) >> 2U; + /* xa + xc -(xb + xd) */ + r1 = r1 - t1; + /* yb + yd */ + t2 = pSrc[(2U * i1) + 1U] + pSrc[(2U * i3) + 1U]; + /* ya' = ya + yb + yc + yd */ + pSrc[(2U * i0) + 1U] = (s1 + t2) >> 2U; + + /* (ya + yc) - (yb + yd) */ + s1 = s1 - t2; + + /* (yb - yd) */ + t1 = pSrc[(2U * i1) + 1U] - pSrc[(2U * i3) + 1U]; + /* (xb - xd) */ + t2 = pSrc[2U * i1] - pSrc[2U * i3]; + + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = (((int32_t) (((q63_t) r1 * co2) >> 32U)) - + ((int32_t) (((q63_t) s1 * si2) >> 32U))) >> 1U; + + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = (((int32_t) (((q63_t) s1 * co2) >> 32U)) + + ((int32_t) (((q63_t) r1 * si2) >> 32U))) >> 1U; + + /* (xa - xc) - (yb - yd) */ + r1 = r2 - t1; + /* (xa - xc) + (yb - yd) */ + r2 = r2 + t1; + + /* (ya - yc) + (xb - xd) */ + s1 = s2 + t2; + /* (ya - yc) - (xb - xd) */ + s2 = s2 - t2; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = (((int32_t) (((q63_t) r1 * co1) >> 32)) - + ((int32_t) (((q63_t) s1 * si1) >> 32))) >> 1U; + + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = (((int32_t) (((q63_t) s1 * co1) >> 32)) + + ((int32_t) (((q63_t) r1 * si1) >> 32))) >> 1U; + + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + pSrc[(2U * i3)] = (((int32_t) (((q63_t) r2 * co3) >> 32)) - + ((int32_t) (((q63_t) s2 * si3) >> 32))) >> 1U; + + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = (((int32_t) (((q63_t) s2 * co3) >> 32)) + + ((int32_t) (((q63_t) r2 * si3) >> 32))) >> 1U; + } + } + twidCoefModifier <<= 2U; + } + + /* End of Middle stages process */ + + /* data is in 11.21(q21) format for the 1024 point as there are 3 middle stages */ + /* data is in 9.23(q23) format for the 256 point as there are 2 middle stages */ + /* data is in 7.25(q25) format for the 64 point as there are 1 middle stage */ + /* data is in 5.27(q27) format for the 16 point as there are no middle stages */ + + + /* Start of last stage process */ + + + /* Initializations for the last stage */ + j = fftLen >> 2; + ptr1 = &pSrc[0]; + + /* Calculations of last stage */ + do + { +#if defined RISCV_MATH_DSP && (__RISCV_XLEN == 64) + xa64 = read_q31x2_ia((q31_t **)&ptr1); + xb64 = read_q31x2_ia((q31_t **)&ptr1); + xc64 = read_q31x2_ia((q31_t **)&ptr1); + xd64 = read_q31x2_ia((q31_t **)&ptr1); + /* xa' = xa + xb + xc + xd */ /* ya' = ya + yb + yc + yd */ + xa_out64 = __RV_KADD32( __RV_KADD32( __RV_KADD32(xa64, xb64), xc64), xd64); + /* pointer updation for writing */ + ptr1 = ptr1 - 8U; + write_q31x2_ia((q31_t **)&ptr1, xa_out64); + /* xc_out = (xa - xb + xc - xd);yc_out = (ya - yb + yc - yd);*/ + xa_out64 = __RV_KSUB32( __RV_KADD32( __RV_KSUB32(xa64, xb64), xc64), xd64); + write_q31x2_ia((q31_t **)&ptr1, xa_out64); + /* xb_out = (xa + yb - xc - yd);yb_out = (ya - xb - yc + xd);*/ + xa_out64 = __RV_KCRAS32( __RV_KSUB32( __RV_KCRSA32(xa64, xb64), xc64), xd64); + write_q31x2_ia((q31_t **)&ptr1, xa_out64); + /* xd_out = (xa - yb - xc + yd); yd_out = (ya + xb - yc - xd);*/ + xa_out64 = __RV_KCRSA32( __RV_KSUB32( __RV_KCRAS32(xa64, xb64), xc64), xd64); + write_q31x2_ia((q31_t **)&ptr1, xa_out64); + +#else + /* Read xa (real), ya(imag) input */ + xa = *ptr1++; + ya = *ptr1++; + + /* Read xb (real), yb(imag) input */ + xb = *ptr1++; + yb = *ptr1++; + + /* Read xc (real), yc(imag) input */ + xc = *ptr1++; + yc = *ptr1++; + + /* Read xc (real), yc(imag) input */ + xd = *ptr1++; + yd = *ptr1++; + + /* xa' = xa + xb + xc + xd */ + xa_out = xa + xb + xc + xd; + + /* ya' = ya + yb + yc + yd */ + ya_out = ya + yb + yc + yd; + + /* pointer updation for writing */ + ptr1 = ptr1 - 8U; + + /* writing xa' and ya' */ + *ptr1++ = xa_out; + *ptr1++ = ya_out; + + xc_out = (xa - xb + xc - xd); + yc_out = (ya - yb + yc - yd); + + /* writing xc' and yc' */ + *ptr1++ = xc_out; + *ptr1++ = yc_out; + + xb_out = (xa - yb - xc + yd); + yb_out = (ya + xb - yc - xd); + + /* writing xb' and yb' */ + *ptr1++ = xb_out; + *ptr1++ = yb_out; + + xd_out = (xa + yb - xc - yd); + yd_out = (ya - xb - yc + xd); + + /* writing xd' and yd' */ + *ptr1++ = xd_out; + *ptr1++ = yd_out; +#endif /* __RISCV_XLEN == 64 */ + + } while (--j); + + /* output is in 11.21(q21) format for the 1024 point */ + /* output is in 9.23(q23) format for the 256 point */ + /* output is in 7.25(q25) format for the 64 point */ + /* output is in 5.27(q27) format for the 16 point */ + + /* End of last stage process */ +} diff --git a/components/nmsis/dsp/src/TransformFunctions/riscv_cfft_radix8_f16.c b/components/nmsis/dsp/src/TransformFunctions/riscv_cfft_radix8_f16.c new file mode 100644 index 00000000..3ff67b38 --- /dev/null +++ b/components/nmsis/dsp/src/TransformFunctions/riscv_cfft_radix8_f16.c @@ -0,0 +1,290 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_cfft_radix8_f16.c + * Description: Radix-8 Decimation in Frequency CFFT & CIFFT Floating point processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions_f16.h" + +#if defined(RISCV_FLOAT16_SUPPORTED) + + +/* ---------------------------------------------------------------------- + * Internal helper function used by the FFTs + * -------------------------------------------------------------------- */ + +/** + brief Core function for the floating-point CFFT butterfly process. + param[in,out] pSrc points to the in-place buffer of floating-point data type. + param[in] fftLen length of the FFT. + param[in] pCoef points to the twiddle coefficient buffer. + param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + return none +*/ + +void riscv_radix8_butterfly_f16( + float16_t * pSrc, + uint16_t fftLen, + const float16_t * pCoef, + uint16_t twidCoefModifier) +{ + uint32_t ia1, ia2, ia3, ia4, ia5, ia6, ia7; + uint32_t i1, i2, i3, i4, i5, i6, i7, i8; + uint32_t id; + uint32_t n1, n2, j; + + float16_t r1, r2, r3, r4, r5, r6, r7, r8; + float16_t t1, t2; + float16_t s1, s2, s3, s4, s5, s6, s7, s8; + float16_t p1, p2, p3, p4; + float16_t co2, co3, co4, co5, co6, co7, co8; + float16_t si2, si3, si4, si5, si6, si7, si8; + const float16_t C81 = 0.70710678118f; + + n2 = fftLen; + + do + { + n1 = n2; + n2 = n2 >> 3; + i1 = 0; + + do + { + i2 = i1 + n2; + i3 = i2 + n2; + i4 = i3 + n2; + i5 = i4 + n2; + i6 = i5 + n2; + i7 = i6 + n2; + i8 = i7 + n2; + r1 = pSrc[2 * i1] + pSrc[2 * i5]; + r5 = pSrc[2 * i1] - pSrc[2 * i5]; + r2 = pSrc[2 * i2] + pSrc[2 * i6]; + r6 = pSrc[2 * i2] - pSrc[2 * i6]; + r3 = pSrc[2 * i3] + pSrc[2 * i7]; + r7 = pSrc[2 * i3] - pSrc[2 * i7]; + r4 = pSrc[2 * i4] + pSrc[2 * i8]; + r8 = pSrc[2 * i4] - pSrc[2 * i8]; + t1 = r1 - r3; + r1 = r1 + r3; + r3 = r2 - r4; + r2 = r2 + r4; + pSrc[2 * i1] = r1 + r2; + pSrc[2 * i5] = r1 - r2; + r1 = pSrc[2 * i1 + 1] + pSrc[2 * i5 + 1]; + s5 = pSrc[2 * i1 + 1] - pSrc[2 * i5 + 1]; + r2 = pSrc[2 * i2 + 1] + pSrc[2 * i6 + 1]; + s6 = pSrc[2 * i2 + 1] - pSrc[2 * i6 + 1]; + s3 = pSrc[2 * i3 + 1] + pSrc[2 * i7 + 1]; + s7 = pSrc[2 * i3 + 1] - pSrc[2 * i7 + 1]; + r4 = pSrc[2 * i4 + 1] + pSrc[2 * i8 + 1]; + s8 = pSrc[2 * i4 + 1] - pSrc[2 * i8 + 1]; + t2 = r1 - s3; + r1 = r1 + s3; + s3 = r2 - r4; + r2 = r2 + r4; + pSrc[2 * i1 + 1] = r1 + r2; + pSrc[2 * i5 + 1] = r1 - r2; + pSrc[2 * i3] = t1 + s3; + pSrc[2 * i7] = t1 - s3; + pSrc[2 * i3 + 1] = t2 - r3; + pSrc[2 * i7 + 1] = t2 + r3; + r1 = (r6 - r8) * C81; + r6 = (r6 + r8) * C81; + r2 = (s6 - s8) * C81; + s6 = (s6 + s8) * C81; + t1 = r5 - r1; + r5 = r5 + r1; + r8 = r7 - r6; + r7 = r7 + r6; + t2 = s5 - r2; + s5 = s5 + r2; + s8 = s7 - s6; + s7 = s7 + s6; + pSrc[2 * i2] = r5 + s7; + pSrc[2 * i8] = r5 - s7; + pSrc[2 * i6] = t1 + s8; + pSrc[2 * i4] = t1 - s8; + pSrc[2 * i2 + 1] = s5 - r7; + pSrc[2 * i8 + 1] = s5 + r7; + pSrc[2 * i6 + 1] = t2 - r8; + pSrc[2 * i4 + 1] = t2 + r8; + + i1 += n1; + } while (i1 < fftLen); + + if (n2 < 8) + break; + + ia1 = 0; + j = 1; + + do + { + /* index calculation for the coefficients */ + id = ia1 + twidCoefModifier; + ia1 = id; + ia2 = ia1 + id; + ia3 = ia2 + id; + ia4 = ia3 + id; + ia5 = ia4 + id; + ia6 = ia5 + id; + ia7 = ia6 + id; + + co2 = pCoef[2 * ia1]; + co3 = pCoef[2 * ia2]; + co4 = pCoef[2 * ia3]; + co5 = pCoef[2 * ia4]; + co6 = pCoef[2 * ia5]; + co7 = pCoef[2 * ia6]; + co8 = pCoef[2 * ia7]; + si2 = pCoef[2 * ia1 + 1]; + si3 = pCoef[2 * ia2 + 1]; + si4 = pCoef[2 * ia3 + 1]; + si5 = pCoef[2 * ia4 + 1]; + si6 = pCoef[2 * ia5 + 1]; + si7 = pCoef[2 * ia6 + 1]; + si8 = pCoef[2 * ia7 + 1]; + + i1 = j; + + do + { + /* index calculation for the input */ + i2 = i1 + n2; + i3 = i2 + n2; + i4 = i3 + n2; + i5 = i4 + n2; + i6 = i5 + n2; + i7 = i6 + n2; + i8 = i7 + n2; + r1 = pSrc[2 * i1] + pSrc[2 * i5]; + r5 = pSrc[2 * i1] - pSrc[2 * i5]; + r2 = pSrc[2 * i2] + pSrc[2 * i6]; + r6 = pSrc[2 * i2] - pSrc[2 * i6]; + r3 = pSrc[2 * i3] + pSrc[2 * i7]; + r7 = pSrc[2 * i3] - pSrc[2 * i7]; + r4 = pSrc[2 * i4] + pSrc[2 * i8]; + r8 = pSrc[2 * i4] - pSrc[2 * i8]; + t1 = r1 - r3; + r1 = r1 + r3; + r3 = r2 - r4; + r2 = r2 + r4; + pSrc[2 * i1] = r1 + r2; + r2 = r1 - r2; + s1 = pSrc[2 * i1 + 1] + pSrc[2 * i5 + 1]; + s5 = pSrc[2 * i1 + 1] - pSrc[2 * i5 + 1]; + s2 = pSrc[2 * i2 + 1] + pSrc[2 * i6 + 1]; + s6 = pSrc[2 * i2 + 1] - pSrc[2 * i6 + 1]; + s3 = pSrc[2 * i3 + 1] + pSrc[2 * i7 + 1]; + s7 = pSrc[2 * i3 + 1] - pSrc[2 * i7 + 1]; + s4 = pSrc[2 * i4 + 1] + pSrc[2 * i8 + 1]; + s8 = pSrc[2 * i4 + 1] - pSrc[2 * i8 + 1]; + t2 = s1 - s3; + s1 = s1 + s3; + s3 = s2 - s4; + s2 = s2 + s4; + r1 = t1 + s3; + t1 = t1 - s3; + pSrc[2 * i1 + 1] = s1 + s2; + s2 = s1 - s2; + s1 = t2 - r3; + t2 = t2 + r3; + p1 = co5 * r2; + p2 = si5 * s2; + p3 = co5 * s2; + p4 = si5 * r2; + pSrc[2 * i5] = p1 + p2; + pSrc[2 * i5 + 1] = p3 - p4; + p1 = co3 * r1; + p2 = si3 * s1; + p3 = co3 * s1; + p4 = si3 * r1; + pSrc[2 * i3] = p1 + p2; + pSrc[2 * i3 + 1] = p3 - p4; + p1 = co7 * t1; + p2 = si7 * t2; + p3 = co7 * t2; + p4 = si7 * t1; + pSrc[2 * i7] = p1 + p2; + pSrc[2 * i7 + 1] = p3 - p4; + r1 = (r6 - r8) * C81; + r6 = (r6 + r8) * C81; + s1 = (s6 - s8) * C81; + s6 = (s6 + s8) * C81; + t1 = r5 - r1; + r5 = r5 + r1; + r8 = r7 - r6; + r7 = r7 + r6; + t2 = s5 - s1; + s5 = s5 + s1; + s8 = s7 - s6; + s7 = s7 + s6; + r1 = r5 + s7; + r5 = r5 - s7; + r6 = t1 + s8; + t1 = t1 - s8; + s1 = s5 - r7; + s5 = s5 + r7; + s6 = t2 - r8; + t2 = t2 + r8; + p1 = co2 * r1; + p2 = si2 * s1; + p3 = co2 * s1; + p4 = si2 * r1; + pSrc[2 * i2] = p1 + p2; + pSrc[2 * i2 + 1] = p3 - p4; + p1 = co8 * r5; + p2 = si8 * s5; + p3 = co8 * s5; + p4 = si8 * r5; + pSrc[2 * i8] = p1 + p2; + pSrc[2 * i8 + 1] = p3 - p4; + p1 = co6 * r6; + p2 = si6 * s6; + p3 = co6 * s6; + p4 = si6 * r6; + pSrc[2 * i6] = p1 + p2; + pSrc[2 * i6 + 1] = p3 - p4; + p1 = co4 * t1; + p2 = si4 * t2; + p3 = co4 * t2; + p4 = si4 * t1; + pSrc[2 * i4] = p1 + p2; + pSrc[2 * i4 + 1] = p3 - p4; + + i1 += n1; + } while (i1 < fftLen); + + j++; + } while (j < n2); + + twidCoefModifier <<= 3; + } while (n2 > 7); +} + +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ diff --git a/components/nmsis/dsp/src/TransformFunctions/riscv_cfft_radix8_f32.c b/components/nmsis/dsp/src/TransformFunctions/riscv_cfft_radix8_f32.c new file mode 100644 index 00000000..3bc6d916 --- /dev/null +++ b/components/nmsis/dsp/src/TransformFunctions/riscv_cfft_radix8_f32.c @@ -0,0 +1,286 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_cfft_radix8_f32.c + * Description: Radix-8 Decimation in Frequency CFFT & CIFFT Floating point processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" + + +/* ---------------------------------------------------------------------- + * Internal helper function used by the FFTs + * -------------------------------------------------------------------- */ + +/** + brief Core function for the floating-point CFFT butterfly process. + param[in,out] pSrc points to the in-place buffer of floating-point data type. + param[in] fftLen length of the FFT. + param[in] pCoef points to the twiddle coefficient buffer. + param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + return none +*/ + +void riscv_radix8_butterfly_f32( + float32_t * pSrc, + uint16_t fftLen, + const float32_t * pCoef, + uint16_t twidCoefModifier) +{ + uint32_t ia1, ia2, ia3, ia4, ia5, ia6, ia7; + uint32_t i1, i2, i3, i4, i5, i6, i7, i8; + uint32_t id; + uint32_t n1, n2, j; + + float32_t r1, r2, r3, r4, r5, r6, r7, r8; + float32_t t1, t2; + float32_t s1, s2, s3, s4, s5, s6, s7, s8; + float32_t p1, p2, p3, p4; + float32_t co2, co3, co4, co5, co6, co7, co8; + float32_t si2, si3, si4, si5, si6, si7, si8; + const float32_t C81 = 0.70710678118f; + + n2 = fftLen; + + do + { + n1 = n2; + n2 = n2 >> 3; + i1 = 0; + + do + { + i2 = i1 + n2; + i3 = i2 + n2; + i4 = i3 + n2; + i5 = i4 + n2; + i6 = i5 + n2; + i7 = i6 + n2; + i8 = i7 + n2; + r1 = pSrc[2 * i1] + pSrc[2 * i5]; + r5 = pSrc[2 * i1] - pSrc[2 * i5]; + r2 = pSrc[2 * i2] + pSrc[2 * i6]; + r6 = pSrc[2 * i2] - pSrc[2 * i6]; + r3 = pSrc[2 * i3] + pSrc[2 * i7]; + r7 = pSrc[2 * i3] - pSrc[2 * i7]; + r4 = pSrc[2 * i4] + pSrc[2 * i8]; + r8 = pSrc[2 * i4] - pSrc[2 * i8]; + t1 = r1 - r3; + r1 = r1 + r3; + r3 = r2 - r4; + r2 = r2 + r4; + pSrc[2 * i1] = r1 + r2; + pSrc[2 * i5] = r1 - r2; + r1 = pSrc[2 * i1 + 1] + pSrc[2 * i5 + 1]; + s5 = pSrc[2 * i1 + 1] - pSrc[2 * i5 + 1]; + r2 = pSrc[2 * i2 + 1] + pSrc[2 * i6 + 1]; + s6 = pSrc[2 * i2 + 1] - pSrc[2 * i6 + 1]; + s3 = pSrc[2 * i3 + 1] + pSrc[2 * i7 + 1]; + s7 = pSrc[2 * i3 + 1] - pSrc[2 * i7 + 1]; + r4 = pSrc[2 * i4 + 1] + pSrc[2 * i8 + 1]; + s8 = pSrc[2 * i4 + 1] - pSrc[2 * i8 + 1]; + t2 = r1 - s3; + r1 = r1 + s3; + s3 = r2 - r4; + r2 = r2 + r4; + pSrc[2 * i1 + 1] = r1 + r2; + pSrc[2 * i5 + 1] = r1 - r2; + pSrc[2 * i3] = t1 + s3; + pSrc[2 * i7] = t1 - s3; + pSrc[2 * i3 + 1] = t2 - r3; + pSrc[2 * i7 + 1] = t2 + r3; + r1 = (r6 - r8) * C81; + r6 = (r6 + r8) * C81; + r2 = (s6 - s8) * C81; + s6 = (s6 + s8) * C81; + t1 = r5 - r1; + r5 = r5 + r1; + r8 = r7 - r6; + r7 = r7 + r6; + t2 = s5 - r2; + s5 = s5 + r2; + s8 = s7 - s6; + s7 = s7 + s6; + pSrc[2 * i2] = r5 + s7; + pSrc[2 * i8] = r5 - s7; + pSrc[2 * i6] = t1 + s8; + pSrc[2 * i4] = t1 - s8; + pSrc[2 * i2 + 1] = s5 - r7; + pSrc[2 * i8 + 1] = s5 + r7; + pSrc[2 * i6 + 1] = t2 - r8; + pSrc[2 * i4 + 1] = t2 + r8; + + i1 += n1; + } while (i1 < fftLen); + + if (n2 < 8) + break; + + ia1 = 0; + j = 1; + + do + { + /* index calculation for the coefficients */ + id = ia1 + twidCoefModifier; + ia1 = id; + ia2 = ia1 + id; + ia3 = ia2 + id; + ia4 = ia3 + id; + ia5 = ia4 + id; + ia6 = ia5 + id; + ia7 = ia6 + id; + + co2 = pCoef[2 * ia1]; + co3 = pCoef[2 * ia2]; + co4 = pCoef[2 * ia3]; + co5 = pCoef[2 * ia4]; + co6 = pCoef[2 * ia5]; + co7 = pCoef[2 * ia6]; + co8 = pCoef[2 * ia7]; + si2 = pCoef[2 * ia1 + 1]; + si3 = pCoef[2 * ia2 + 1]; + si4 = pCoef[2 * ia3 + 1]; + si5 = pCoef[2 * ia4 + 1]; + si6 = pCoef[2 * ia5 + 1]; + si7 = pCoef[2 * ia6 + 1]; + si8 = pCoef[2 * ia7 + 1]; + + i1 = j; + + do + { + /* index calculation for the input */ + i2 = i1 + n2; + i3 = i2 + n2; + i4 = i3 + n2; + i5 = i4 + n2; + i6 = i5 + n2; + i7 = i6 + n2; + i8 = i7 + n2; + r1 = pSrc[2 * i1] + pSrc[2 * i5]; + r5 = pSrc[2 * i1] - pSrc[2 * i5]; + r2 = pSrc[2 * i2] + pSrc[2 * i6]; + r6 = pSrc[2 * i2] - pSrc[2 * i6]; + r3 = pSrc[2 * i3] + pSrc[2 * i7]; + r7 = pSrc[2 * i3] - pSrc[2 * i7]; + r4 = pSrc[2 * i4] + pSrc[2 * i8]; + r8 = pSrc[2 * i4] - pSrc[2 * i8]; + t1 = r1 - r3; + r1 = r1 + r3; + r3 = r2 - r4; + r2 = r2 + r4; + pSrc[2 * i1] = r1 + r2; + r2 = r1 - r2; + s1 = pSrc[2 * i1 + 1] + pSrc[2 * i5 + 1]; + s5 = pSrc[2 * i1 + 1] - pSrc[2 * i5 + 1]; + s2 = pSrc[2 * i2 + 1] + pSrc[2 * i6 + 1]; + s6 = pSrc[2 * i2 + 1] - pSrc[2 * i6 + 1]; + s3 = pSrc[2 * i3 + 1] + pSrc[2 * i7 + 1]; + s7 = pSrc[2 * i3 + 1] - pSrc[2 * i7 + 1]; + s4 = pSrc[2 * i4 + 1] + pSrc[2 * i8 + 1]; + s8 = pSrc[2 * i4 + 1] - pSrc[2 * i8 + 1]; + t2 = s1 - s3; + s1 = s1 + s3; + s3 = s2 - s4; + s2 = s2 + s4; + r1 = t1 + s3; + t1 = t1 - s3; + pSrc[2 * i1 + 1] = s1 + s2; + s2 = s1 - s2; + s1 = t2 - r3; + t2 = t2 + r3; + p1 = co5 * r2; + p2 = si5 * s2; + p3 = co5 * s2; + p4 = si5 * r2; + pSrc[2 * i5] = p1 + p2; + pSrc[2 * i5 + 1] = p3 - p4; + p1 = co3 * r1; + p2 = si3 * s1; + p3 = co3 * s1; + p4 = si3 * r1; + pSrc[2 * i3] = p1 + p2; + pSrc[2 * i3 + 1] = p3 - p4; + p1 = co7 * t1; + p2 = si7 * t2; + p3 = co7 * t2; + p4 = si7 * t1; + pSrc[2 * i7] = p1 + p2; + pSrc[2 * i7 + 1] = p3 - p4; + r1 = (r6 - r8) * C81; + r6 = (r6 + r8) * C81; + s1 = (s6 - s8) * C81; + s6 = (s6 + s8) * C81; + t1 = r5 - r1; + r5 = r5 + r1; + r8 = r7 - r6; + r7 = r7 + r6; + t2 = s5 - s1; + s5 = s5 + s1; + s8 = s7 - s6; + s7 = s7 + s6; + r1 = r5 + s7; + r5 = r5 - s7; + r6 = t1 + s8; + t1 = t1 - s8; + s1 = s5 - r7; + s5 = s5 + r7; + s6 = t2 - r8; + t2 = t2 + r8; + p1 = co2 * r1; + p2 = si2 * s1; + p3 = co2 * s1; + p4 = si2 * r1; + pSrc[2 * i2] = p1 + p2; + pSrc[2 * i2 + 1] = p3 - p4; + p1 = co8 * r5; + p2 = si8 * s5; + p3 = co8 * s5; + p4 = si8 * r5; + pSrc[2 * i8] = p1 + p2; + pSrc[2 * i8 + 1] = p3 - p4; + p1 = co6 * r6; + p2 = si6 * s6; + p3 = co6 * s6; + p4 = si6 * r6; + pSrc[2 * i6] = p1 + p2; + pSrc[2 * i6 + 1] = p3 - p4; + p1 = co4 * t1; + p2 = si4 * t2; + p3 = co4 * t2; + p4 = si4 * t1; + pSrc[2 * i4] = p1 + p2; + pSrc[2 * i4 + 1] = p3 - p4; + + i1 += n1; + } while (i1 < fftLen); + + j++; + } while (j < n2); + + twidCoefModifier <<= 3; + } while (n2 > 7); +} diff --git a/components/nmsis/dsp/src/TransformFunctions/riscv_dct4_f32.c b/components/nmsis/dsp/src/TransformFunctions/riscv_dct4_f32.c new file mode 100644 index 00000000..aa2e23b8 --- /dev/null +++ b/components/nmsis/dsp/src/TransformFunctions/riscv_dct4_f32.c @@ -0,0 +1,449 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_dct4_f32.c + * Description: Processing function of DCT4 & IDCT4 F32 + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" + +/** + @ingroup groupTransforms + */ + +/** + @defgroup DCT4_IDCT4 DCT Type IV Functions + + Representation of signals by minimum number of values is important for storage and transmission. + The possibility of large discontinuity between the beginning and end of a period of a signal + in DFT can be avoided by extending the signal so that it is even-symmetric. + Discrete Cosine Transform (DCT) is constructed such that its energy is heavily concentrated in the lower part of the + spectrum and is very widely used in signal and image coding applications. + The family of DCTs (DCT type- 1,2,3,4) is the outcome of different combinations of homogeneous boundary conditions. + DCT has an excellent energy-packing capability, hence has many applications and in data compression in particular. + + DCT is essentially the Discrete Fourier Transform(DFT) of an even-extended real signal. + Reordering of the input data makes the computation of DCT just a problem of + computing the DFT of a real signal with a few additional operations. + This approach provides regular, simple, and very efficient DCT algorithms for practical hardware and software implementations. + + DCT type-II can be implemented using Fast fourier transform (FFT) internally, as the transform is applied on real values, Real FFT can be used. + DCT4 is implemented using DCT2 as their implementations are similar except with some added pre-processing and post-processing. + DCT2 implementation can be described in the following steps: + - Re-ordering input + - Calculating Real FFT + - Multiplication of weights and Real FFT output and getting real part from the product. + + This process is explained by the block diagram below: + \image html DCT4.png "Discrete Cosine Transform - type-IV" + + @par Algorithm + The N-point type-IV DCT is defined as a real, linear transformation by the formula: + \image html DCT4Equation.png + where k = 0, 1, 2, ..., N-1 + @par + Its inverse is defined as follows: + \image html IDCT4Equation.png + where n = 0, 1, 2, ..., N-1 + @par + The DCT4 matrices become involutory (i.e. they are self-inverse) by multiplying with an overall scale factor of sqrt(2/N). + The symmetry of the transform matrix indicates that the fast algorithms for the forward + and inverse transform computation are identical. + Note that the implementation of Inverse DCT4 and DCT4 is same, hence same process function can be used for both. + + @par Lengths supported by the transform: + As DCT4 internally uses Real FFT, it supports all the lengths 128, 512, 2048 and 8192. + The library provides separate functions for Q15, Q31, and floating-point data types. + + @par Instance Structure + The instances for Real FFT and FFT, cosine values table and twiddle factor table are stored in an instance data structure. + A separate instance structure must be defined for each transform. + There are separate instance structure declarations for each of the 3 supported data types. + + @par Initialization Functions + There is also an associated initialization function for each data type. + The initialization function performs the following operations: + - Sets the values of the internal structure fields. + - Initializes Real FFT as its process function is used internally in DCT4, by calling \ref riscv_rfft_init_f32(). + @par + Use of the initialization function is optional. + However, if the initialization function is used, then the instance structure cannot be placed into a const data section. + To place an instance structure into a const data section, the instance structure must be manually initialized. + Manually initialize the instance structure as follows: + 
+      riscv_dct4_instance_f32 S = {N, Nby2, normalize, pTwiddle, pCosFactor, pRfft, pCfft};
+      riscv_dct4_instance_q31 S = {N, Nby2, normalize, pTwiddle, pCosFactor, pRfft, pCfft};
+      riscv_dct4_instance_q15 S = {N, Nby2, normalize, pTwiddle, pCosFactor, pRfft, pCfft};
+
+ where \c N is the length of the DCT4; \c Nby2 is half of the length of the DCT4; + \c normalize is normalizing factor used and is equal to sqrt(2/N); + \c pTwiddle points to the twiddle factor table; + \c pCosFactor points to the cosFactor table; + \c pRfft points to the real FFT instance; + \c pCfft points to the complex FFT instance; + The CFFT and RFFT structures also needs to be initialized, refer to riscv_cfft_radix4_f32() + and riscv_rfft_f32() respectively for details regarding static initialization. + + @par Fixed-Point Behavior + Care must be taken when using the fixed-point versions of the DCT4 transform functions. + In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + Refer to the function specific documentation below for usage guidelines. + */ + + /** + @addtogroup DCT4_IDCT4 + @{ + */ + +/** + @brief Processing function for the floating-point DCT4/IDCT4. + @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure + @param[in] pState points to state buffer + @param[in,out] pInlineBuffer points to the in-place input and output buffer + @return none + */ + +void riscv_dct4_f32( + const riscv_dct4_instance_f32 * S, + float32_t * pState, + float32_t * pInlineBuffer) +{ + const float32_t *weights = S->pTwiddle; /* Pointer to the Weights table */ + const float32_t *cosFact = S->pCosFactor; /* Pointer to the cos factors table */ + float32_t *pS1, *pS2, *pbuff; /* Temporary pointers for input buffer and pState buffer */ + float32_t in; /* Temporary variable */ + uint32_t i; /* Loop counter */ + + + /* DCT4 computation involves DCT2 (which is calculated using RFFT) + * along with some pre-processing and post-processing. + * Computational procedure is explained as follows: + * (a) Pre-processing involves multiplying input with cos factor, + * r(n) = 2 * u(n) * cos(pi*(2*n+1)/(4*n)) + * where, + * r(n) -- output of preprocessing + * u(n) -- input to preprocessing(actual Source buffer) + * (b) Calculation of DCT2 using FFT is divided into three steps: + * Step1: Re-ordering of even and odd elements of input. + * Step2: Calculating FFT of the re-ordered input. + * Step3: Taking the real part of the product of FFT output and weights. + * (c) Post-processing - DCT4 can be obtained from DCT2 output using the following equation: + * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0) + * where, + * Y4 -- DCT4 output, Y2 -- DCT2 output + * (d) Multiplying the output with the normalizing factor sqrt(2/N). + */ + + /*-------- Pre-processing ------------*/ + /* Multiplying input with cos factor i.e. r(n) = 2 * x(n) * cos(pi*(2*n+1)/(4*n)) */ + riscv_scale_f32(pInlineBuffer, 2.0f, pInlineBuffer, S->N); + riscv_mult_f32(pInlineBuffer, cosFact, pInlineBuffer, S->N); + + /* ---------------------------------------------------------------- + * Step1: Re-ordering of even and odd elements as + * pState[i] = pInlineBuffer[2*i] and + * pState[N-i-1] = pInlineBuffer[2*i+1] where i = 0 to N/2 + ---------------------------------------------------------------------*/ + + /* pS1 initialized to pState */ + pS1 = pState; + + /* pS2 initialized to pState+N-1, so that it points to the end of the state buffer */ + pS2 = pState + (S->N - 1U); + + /* pbuff initialized to input buffer */ + pbuff = pInlineBuffer; + + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Initializing the loop counter to N/2 >> 2 for loop unrolling by 4 */ + i = S->Nby2 >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + do + { + /* Re-ordering of even and odd elements */ + /* pState[i] = pInlineBuffer[2*i] */ + *pS1++ = *pbuff++; + /* pState[N-i-1] = pInlineBuffer[2*i+1] */ + *pS2-- = *pbuff++; + + *pS1++ = *pbuff++; + *pS2-- = *pbuff++; + + *pS1++ = *pbuff++; + *pS2-- = *pbuff++; + + *pS1++ = *pbuff++; + *pS2-- = *pbuff++; + + /* Decrement loop counter */ + i--; + } while (i > 0U); + + /* pbuff initialized to input buffer */ + pbuff = pInlineBuffer; + + /* pS1 initialized to pState */ + pS1 = pState; + + /* Initializing the loop counter to N/4 instead of N for loop unrolling */ + i = S->N >> 2U; + + /* Processing with loop unrolling 4 times as N is always multiple of 4. + * Compute 4 outputs at a time */ + do + { + /* Writing the re-ordered output back to inplace input buffer */ + *pbuff++ = *pS1++; + *pbuff++ = *pS1++; + *pbuff++ = *pS1++; + *pbuff++ = *pS1++; + + /* Decrement the loop counter */ + i--; + } while (i > 0U); + + + /* --------------------------------------------------------- + * Step2: Calculate RFFT for N-point input + * ---------------------------------------------------------- */ + /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */ + riscv_rfft_f32 (S->pRfft, pInlineBuffer, pState); + + /*---------------------------------------------------------------------- + * Step3: Multiply the FFT output with the weights. + *----------------------------------------------------------------------*/ + riscv_cmplx_mult_cmplx_f32 (pState, weights, pState, S->N); + + /* ----------- Post-processing ---------- */ + /* DCT-IV can be obtained from DCT-II by the equation, + * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0) + * Hence, Y4(0) = Y2(0)/2 */ + /* Getting only real part from the output and Converting to DCT-IV */ + + /* Initializing the loop counter to N >> 2 for loop unrolling by 4 */ + i = (S->N - 1U) >> 2U; + + /* pbuff initialized to input buffer. */ + pbuff = pInlineBuffer; + + /* pS1 initialized to pState */ + pS1 = pState; + + /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */ + in = *pS1++ * (float32_t) 0.5; + /* input buffer acts as inplace, so output values are stored in the input itself. */ + *pbuff++ = in; + + /* pState pointer is incremented twice as the real values are located alternatively in the array */ + pS1++; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + do + { + /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */ + /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */ + in = *pS1++ - in; + *pbuff++ = in; + /* points to the next real value */ + pS1++; + + in = *pS1++ - in; + *pbuff++ = in; + pS1++; + + in = *pS1++ - in; + *pbuff++ = in; + pS1++; + + in = *pS1++ - in; + *pbuff++ = in; + pS1++; + + /* Decrement the loop counter */ + i--; + } while (i > 0U); + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + i = (S->N - 1U) % 0x4U; + + while (i > 0U) + { + /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */ + /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */ + in = *pS1++ - in; + *pbuff++ = in; + + /* points to the next real value */ + pS1++; + + /* Decrement the loop counter */ + i--; + } + + + /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/ + + /* Initializing the loop counter to N/4 instead of N for loop unrolling */ + i = S->N >> 2U; + + /* pbuff initialized to the pInlineBuffer(now contains the output values) */ + pbuff = pInlineBuffer; + + /* Processing with loop unrolling 4 times as N is always multiple of 4. Compute 4 outputs at a time */ + do + { + /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */ + in = *pbuff; + *pbuff++ = in * S->normalize; + + in = *pbuff; + *pbuff++ = in * S->normalize; + + in = *pbuff; + *pbuff++ = in * S->normalize; + + in = *pbuff; + *pbuff++ = in * S->normalize; + + /* Decrement the loop counter */ + i--; + } while (i > 0U); + + +#else + + /* Initializing the loop counter to N/2 */ + i = S->Nby2; + + do + { + /* Re-ordering of even and odd elements */ + /* pState[i] = pInlineBuffer[2*i] */ + *pS1++ = *pbuff++; + /* pState[N-i-1] = pInlineBuffer[2*i+1] */ + *pS2-- = *pbuff++; + + /* Decrement the loop counter */ + i--; + } while (i > 0U); + + /* pbuff initialized to input buffer */ + pbuff = pInlineBuffer; + + /* pS1 initialized to pState */ + pS1 = pState; + + /* Initializing the loop counter */ + i = S->N; + + do + { + /* Writing the re-ordered output back to inplace input buffer */ + *pbuff++ = *pS1++; + + /* Decrement the loop counter */ + i--; + } while (i > 0U); + + + /* --------------------------------------------------------- + * Step2: Calculate RFFT for N-point input + * ---------------------------------------------------------- */ + /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */ + riscv_rfft_f32 (S->pRfft, pInlineBuffer, pState); + + /*---------------------------------------------------------------------- + * Step3: Multiply the FFT output with the weights. + *----------------------------------------------------------------------*/ + riscv_cmplx_mult_cmplx_f32 (pState, weights, pState, S->N); + + /* ----------- Post-processing ---------- */ + /* DCT-IV can be obtained from DCT-II by the equation, + * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0) + * Hence, Y4(0) = Y2(0)/2 */ + /* Getting only real part from the output and Converting to DCT-IV */ + + /* pbuff initialized to input buffer. */ + pbuff = pInlineBuffer; + + /* pS1 initialized to pState */ + pS1 = pState; + + /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */ + in = *pS1++ * (float32_t) 0.5; + /* input buffer acts as inplace, so output values are stored in the input itself. */ + *pbuff++ = in; + + /* pState pointer is incremented twice as the real values are located alternatively in the array */ + pS1++; + + /* Initializing the loop counter */ + i = (S->N - 1U); + + do + { + /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */ + /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */ + in = *pS1++ - in; + *pbuff++ = in; + + /* points to the next real value */ + pS1++; + + /* Decrement loop counter */ + i--; + } while (i > 0U); + + /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/ + + /* Initializing loop counter */ + i = S->N; + + /* pbuff initialized to the pInlineBuffer (now contains the output values) */ + pbuff = pInlineBuffer; + + do + { + /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */ + in = *pbuff; + *pbuff++ = in * S->normalize; + + /* Decrement loop counter */ + i--; + } while (i > 0U); + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + +} + +/** + @} end of DCT4_IDCT4 group + */ diff --git a/components/nmsis/dsp/src/TransformFunctions/riscv_dct4_init_f32.c b/components/nmsis/dsp/src/TransformFunctions/riscv_dct4_init_f32.c new file mode 100644 index 00000000..f263b243 --- /dev/null +++ b/components/nmsis/dsp/src/TransformFunctions/riscv_dct4_init_f32.c @@ -0,0 +1,131 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_dct4_init_f32.c + * Description: Initialization function of DCT-4 & IDCT4 F32 + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" +#include "riscv_common_tables.h" + +/** + @ingroup groupTransforms + */ + + /** + @addtogroup DCT4_IDCT4 + @{ + */ + +/** + @brief Initialization function for the floating-point DCT4/IDCT4. + @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure + @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure + @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure + @param[in] N length of the DCT4 + @param[in] Nby2 half of the length of the DCT4 + @param[in] normalize normalizing factor. + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_ARGUMENT_ERROR : N is not a supported transform length + + @par Normalizing factor + The normalizing factor is sqrt(2/N), which depends on the size of transform N. + Floating-point normalizing factors are mentioned in the table below for different DCT sizes: + + \image html dct4NormalizingF32Table.png + */ + +riscv_status riscv_dct4_init_f32( + riscv_dct4_instance_f32 * S, + riscv_rfft_instance_f32 * S_RFFT, + riscv_cfft_radix4_instance_f32 * S_CFFT, + uint16_t N, + uint16_t Nby2, + float32_t normalize) +{ + /* Initialize the default riscv status */ + riscv_status status = RISCV_MATH_SUCCESS; + + + /* Initialize the DCT4 length */ + S->N = N; + + /* Initialize the half of DCT4 length */ + S->Nby2 = Nby2; + + /* Initialize the DCT4 Normalizing factor */ + S->normalize = normalize; + + /* Initialize Real FFT Instance */ + S->pRfft = S_RFFT; + + /* Initialize Complex FFT Instance */ + S->pCfft = S_CFFT; + + switch (N) + { + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_DCT4_F32_8192) + /* Initialize the table modifier values */ + case 8192U: + S->pTwiddle = Weights_8192; + S->pCosFactor = cos_factors_8192; + break; + #endif + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_DCT4_F32_2048) + case 2048U: + S->pTwiddle = Weights_2048; + S->pCosFactor = cos_factors_2048; + break; + #endif + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_DCT4_F32_512) + case 512U: + S->pTwiddle = Weights_512; + S->pCosFactor = cos_factors_512; + break; + #endif + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_DCT4_F32_128) + case 128U: + S->pTwiddle = Weights_128; + S->pCosFactor = cos_factors_128; + break; + #endif + default: + status = RISCV_MATH_ARGUMENT_ERROR; + } + + /* Initialize the RFFT/RIFFT Function */ + riscv_rfft_init_f32(S->pRfft, S->pCfft, S->N, 0U, 1U); + + /* return the status of DCT4 Init function */ + return (status); +} + +/** + @} end of DCT4_IDCT4 group + */ diff --git a/components/nmsis/dsp/src/TransformFunctions/riscv_dct4_init_q15.c b/components/nmsis/dsp/src/TransformFunctions/riscv_dct4_init_q15.c new file mode 100644 index 00000000..b30afe44 --- /dev/null +++ b/components/nmsis/dsp/src/TransformFunctions/riscv_dct4_init_q15.c @@ -0,0 +1,131 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_dct4_init_q15.c + * Description: Initialization function of DCT-4 & IDCT4 Q15 + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" +#include "riscv_common_tables.h" + +/** + @ingroup groupTransforms + */ + + /** + @addtogroup DCT4_IDCT4 + @{ + */ + +/** + @brief Initialization function for the Q15 DCT4/IDCT4. + @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure + @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure + @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure + @param[in] N length of the DCT4 + @param[in] Nby2 half of the length of the DCT4 + @param[in] normalize normalizing factor + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_ARGUMENT_ERROR : N is not a supported transform length + + @par Normalizing factor + The normalizing factor is sqrt(2/N), which depends on the size of transform N. + Normalizing factors in 1.15 format are mentioned in the table below for different DCT sizes: + + \image html dct4NormalizingQ15Table.png + */ + +riscv_status riscv_dct4_init_q15( + riscv_dct4_instance_q15 * S, + riscv_rfft_instance_q15 * S_RFFT, + riscv_cfft_radix4_instance_q15 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize) +{ + /* Initialise the default riscv status */ + riscv_status status = RISCV_MATH_SUCCESS; + + /* Initialize the DCT4 length */ + S->N = N; + + /* Initialize the half of DCT4 length */ + S->Nby2 = Nby2; + + /* Initialize the DCT4 Normalizing factor */ + S->normalize = normalize; + + /* Initialize Real FFT Instance */ + S->pRfft = S_RFFT; + + /* Initialize Complex FFT Instance */ + S->pCfft = S_CFFT; + + switch (N) + { + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_DCT4_Q15_8192) + /* Initialize the table modifier values */ + case 8192U: + S->pTwiddle = WeightsQ15_8192; + S->pCosFactor = cos_factorsQ15_8192; + break; + #endif + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_DCT4_Q15_2048) + case 2048U: + S->pTwiddle = WeightsQ15_2048; + S->pCosFactor = cos_factorsQ15_2048; + break; + #endif + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_DCT4_Q15_512) + case 512U: + S->pTwiddle = WeightsQ15_512; + S->pCosFactor = cos_factorsQ15_512; + break; + #endif + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_DCT4_Q15_128) + case 128U: + S->pTwiddle = WeightsQ15_128; + S->pCosFactor = cos_factorsQ15_128; + break; + #endif + + default: + status = RISCV_MATH_ARGUMENT_ERROR; + } + + /* Initialize the RFFT/RIFFT */ + riscv_rfft_init_q15(S->pRfft, S->N, 0U, 1U); + + /* return the status of DCT4 Init function */ + return (status); +} + +/** + @} end of DCT4_IDCT4 group + */ diff --git a/components/nmsis/dsp/src/TransformFunctions/riscv_dct4_init_q31.c b/components/nmsis/dsp/src/TransformFunctions/riscv_dct4_init_q31.c new file mode 100644 index 00000000..7da8fb0c --- /dev/null +++ b/components/nmsis/dsp/src/TransformFunctions/riscv_dct4_init_q31.c @@ -0,0 +1,130 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_dct4_init_q31.c + * Description: Initialization function of DCT-4 & IDCT4 Q31 + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" +#include "riscv_common_tables.h" + +/** + @ingroup groupTransforms + */ + + /** + @addtogroup DCT4_IDCT4 + @{ + */ + +/** + @brief Initialization function for the Q31 DCT4/IDCT4. + @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure. + @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure + @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure + @param[in] N length of the DCT4. + @param[in] Nby2 half of the length of the DCT4. + @param[in] normalize normalizing factor. + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_ARGUMENT_ERROR : N is not a supported transform length + + @par Normalizing factor: + The normalizing factor is sqrt(2/N), which depends on the size of transform N. + Normalizing factors in 1.31 format are mentioned in the table below for different DCT sizes: + + \image html dct4NormalizingQ31Table.png + */ + +riscv_status riscv_dct4_init_q31( + riscv_dct4_instance_q31 * S, + riscv_rfft_instance_q31 * S_RFFT, + riscv_cfft_radix4_instance_q31 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize) +{ + /* Initialize the default riscv status */ + riscv_status status = RISCV_MATH_SUCCESS; + + /* Initialize the DCT4 length */ + S->N = N; + + /* Initialize the half of DCT4 length */ + S->Nby2 = Nby2; + + /* Initialize the DCT4 Normalizing factor */ + S->normalize = normalize; + + /* Initialize Real FFT Instance */ + S->pRfft = S_RFFT; + + /* Initialize Complex FFT Instance */ + S->pCfft = S_CFFT; + + switch (N) + { + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_DCT4_Q31_8192) + /* Initialize the table modifier values */ + case 8192U: + S->pTwiddle = WeightsQ31_8192; + S->pCosFactor = cos_factorsQ31_8192; + break; + #endif + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_DCT4_Q31_2048) + case 2048U: + S->pTwiddle = WeightsQ31_2048; + S->pCosFactor = cos_factorsQ31_2048; + break; + #endif + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_DCT4_Q31_512) + case 512U: + S->pTwiddle = WeightsQ31_512; + S->pCosFactor = cos_factorsQ31_512; + break; + #endif + + #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_DCT4_Q31_128) + case 128U: + S->pTwiddle = WeightsQ31_128; + S->pCosFactor = cos_factorsQ31_128; + break; + #endif + default: + status = RISCV_MATH_ARGUMENT_ERROR; + } + + /* Initialize the RFFT/RIFFT Function */ + riscv_rfft_init_q31(S->pRfft, S->N, 0U, 1U); + + /* return the status of DCT4 Init function */ + return (status); +} + +/** + @} end of DCT4_IDCT4 group + */ diff --git a/components/nmsis/dsp/src/TransformFunctions/riscv_dct4_q15.c b/components/nmsis/dsp/src/TransformFunctions/riscv_dct4_q15.c new file mode 100644 index 00000000..43715283 --- /dev/null +++ b/components/nmsis/dsp/src/TransformFunctions/riscv_dct4_q15.c @@ -0,0 +1,382 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_dct4_q15.c + * Description: Processing function of DCT4 & IDCT4 Q15 + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" + +/** + @addtogroup DCT4_IDCT4 + @{ + */ + +/** + @brief Processing function for the Q15 DCT4/IDCT4. + @param[in] S points to an instance of the Q15 DCT4 structure. + @param[in] pState points to state buffer. + @param[in,out] pInlineBuffer points to the in-place input and output buffer. + @return none + + @par Input an output formats + Internally inputs are downscaled in the RFFT process function to avoid overflows. + Number of bits downscaled, depends on the size of the transform. The input and output + formats for different DCT sizes and number of bits to upscale are mentioned in the table below: + + \image html dct4FormatsQ15Table.png + */ + +void riscv_dct4_q15( + const riscv_dct4_instance_q15 * S, + q15_t * pState, + q15_t * pInlineBuffer) +{ + const q15_t *weights = S->pTwiddle; /* Pointer to the Weights table */ + const q15_t *cosFact = S->pCosFactor; /* Pointer to the cos factors table */ + q15_t *pS1, *pS2, *pbuff; /* Temporary pointers for input buffer and pState buffer */ + q15_t in; /* Temporary variable */ + uint32_t i; /* Loop counter */ + + + /* DCT4 computation involves DCT2 (which is calculated using RFFT) + * along with some pre-processing and post-processing. + * Computational procedure is explained as follows: + * (a) Pre-processing involves multiplying input with cos factor, + * r(n) = 2 * u(n) * cos(pi*(2*n+1)/(4*n)) + * where, + * r(n) -- output of preprocessing + * u(n) -- input to preprocessing(actual Source buffer) + * (b) Calculation of DCT2 using FFT is divided into three steps: + * Step1: Re-ordering of even and odd elements of input. + * Step2: Calculating FFT of the re-ordered input. + * Step3: Taking the real part of the product of FFT output and weights. + * (c) Post-processing - DCT4 can be obtained from DCT2 output using the following equation: + * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0) + * where, + * Y4 -- DCT4 output, Y2 -- DCT2 output + * (d) Multiplying the output with the normalizing factor sqrt(2/N). + */ + + /*-------- Pre-processing ------------*/ + /* Multiplying input with cos factor i.e. r(n) = 2 * x(n) * cos(pi*(2*n+1)/(4*n)) */ + riscv_mult_q15 (pInlineBuffer, cosFact, pInlineBuffer, S->N); + riscv_shift_q15 (pInlineBuffer, 1, pInlineBuffer, S->N); + + /* ---------------------------------------------------------------- + * Step1: Re-ordering of even and odd elements as + * pState[i] = pInlineBuffer[2*i] and + * pState[N-i-1] = pInlineBuffer[2*i+1] where i = 0 to N/2 + ---------------------------------------------------------------------*/ + + /* pS1 initialized to pState */ + pS1 = pState; + + /* pS2 initialized to pState+N-1, so that it points to the end of the state buffer */ + pS2 = pState + (S->N - 1U); + + /* pbuff initialized to input buffer */ + pbuff = pInlineBuffer; + + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Initializing the loop counter to N/2 >> 2 for loop unrolling by 4 */ + i = S->Nby2 >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + do + { + /* Re-ordering of even and odd elements */ + /* pState[i] = pInlineBuffer[2*i] */ + *pS1++ = *pbuff++; + /* pState[N-i-1] = pInlineBuffer[2*i+1] */ + *pS2-- = *pbuff++; + + *pS1++ = *pbuff++; + *pS2-- = *pbuff++; + + *pS1++ = *pbuff++; + *pS2-- = *pbuff++; + + *pS1++ = *pbuff++; + *pS2-- = *pbuff++; + + /* Decrement loop counter */ + i--; + } while (i > 0U); + + /* pbuff initialized to input buffer */ + pbuff = pInlineBuffer; + + /* pS1 initialized to pState */ + pS1 = pState; + + /* Initializing the loop counter to N/4 instead of N for loop unrolling */ + i = S->N >> 2U; + + /* Processing with loop unrolling 4 times as N is always multiple of 4. + * Compute 4 outputs at a time */ + do + { + /* Writing the re-ordered output back to inplace input buffer */ + *pbuff++ = *pS1++; + *pbuff++ = *pS1++; + *pbuff++ = *pS1++; + *pbuff++ = *pS1++; + + /* Decrement the loop counter */ + i--; + } while (i > 0U); + + + /* --------------------------------------------------------- + * Step2: Calculate RFFT for N-point input + * ---------------------------------------------------------- */ + /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */ + riscv_rfft_q15 (S->pRfft, pInlineBuffer, pState); + + /*---------------------------------------------------------------------- + * Step3: Multiply the FFT output with the weights. + *----------------------------------------------------------------------*/ + riscv_cmplx_mult_cmplx_q15 (pState, weights, pState, S->N); + + /* The output of complex multiplication is in 3.13 format. + * Hence changing the format of N (i.e. 2*N elements) complex numbers to 1.15 format by shifting left by 2 bits. */ + riscv_shift_q15 (pState, 2, pState, S->N * 2); + + /* ----------- Post-processing ---------- */ + /* DCT-IV can be obtained from DCT-II by the equation, + * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0) + * Hence, Y4(0) = Y2(0)/2 */ + /* Getting only real part from the output and Converting to DCT-IV */ + + /* Initializing the loop counter to N >> 2 for loop unrolling by 4 */ + i = (S->N - 1U) >> 2U; + + /* pbuff initialized to input buffer. */ + pbuff = pInlineBuffer; + + /* pS1 initialized to pState */ + pS1 = pState; + + /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */ + in = *pS1++ >> 1U; + /* input buffer acts as inplace, so output values are stored in the input itself. */ + *pbuff++ = in; + + /* pState pointer is incremented twice as the real values are located alternatively in the array */ + pS1++; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + do + { + /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */ + /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */ + in = *pS1++ - in; + *pbuff++ = in; + /* points to the next real value */ + pS1++; + + in = *pS1++ - in; + *pbuff++ = in; + pS1++; + + in = *pS1++ - in; + *pbuff++ = in; + pS1++; + + in = *pS1++ - in; + *pbuff++ = in; + pS1++; + + /* Decrement the loop counter */ + i--; + } while (i > 0U); + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + i = (S->N - 1U) % 0x4U; + + while (i > 0U) + { + /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */ + /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */ + in = *pS1++ - in; + *pbuff++ = in; + + /* points to the next real value */ + pS1++; + + /* Decrement loop counter */ + i--; + } + + + /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/ + + /* Initializing the loop counter to N/4 instead of N for loop unrolling */ + i = S->N >> 2U; + + /* pbuff initialized to the pInlineBuffer(now contains the output values) */ + pbuff = pInlineBuffer; + + /* Processing with loop unrolling 4 times as N is always multiple of 4. Compute 4 outputs at a time */ + do + { + /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */ + in = *pbuff; + *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15)); + + in = *pbuff; + *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15)); + + in = *pbuff; + *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15)); + + in = *pbuff; + *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15)); + + /* Decrement loop counter */ + i--; + } while (i > 0U); + + +#else + + /* Initializing the loop counter to N/2 */ + i = S->Nby2; + + do + { + /* Re-ordering of even and odd elements */ + /* pState[i] = pInlineBuffer[2*i] */ + *pS1++ = *pbuff++; + /* pState[N-i-1] = pInlineBuffer[2*i+1] */ + *pS2-- = *pbuff++; + + /* Decrement the loop counter */ + i--; + } while (i > 0U); + + /* pbuff initialized to input buffer */ + pbuff = pInlineBuffer; + + /* pS1 initialized to pState */ + pS1 = pState; + + /* Initializing the loop counter */ + i = S->N; + + do + { + /* Writing the re-ordered output back to inplace input buffer */ + *pbuff++ = *pS1++; + + /* Decrement the loop counter */ + i--; + } while (i > 0U); + + + /* --------------------------------------------------------- + * Step2: Calculate RFFT for N-point input + * ---------------------------------------------------------- */ + /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */ + riscv_rfft_q15 (S->pRfft, pInlineBuffer, pState); + + /*---------------------------------------------------------------------- + * Step3: Multiply the FFT output with the weights. + *----------------------------------------------------------------------*/ + riscv_cmplx_mult_cmplx_q15 (pState, weights, pState, S->N); + + /* The output of complex multiplication is in 3.13 format. + * Hence changing the format of N (i.e. 2*N elements) complex numbers to 1.15 format by shifting left by 2 bits. */ + riscv_shift_q15 (pState, 2, pState, S->N * 2); + + /* ----------- Post-processing ---------- */ + /* DCT-IV can be obtained from DCT-II by the equation, + * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0) + * Hence, Y4(0) = Y2(0)/2 */ + /* Getting only real part from the output and Converting to DCT-IV */ + + /* pbuff initialized to input buffer. */ + pbuff = pInlineBuffer; + + /* pS1 initialized to pState */ + pS1 = pState; + + /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */ + in = *pS1++ >> 1U; + /* input buffer acts as inplace, so output values are stored in the input itself. */ + *pbuff++ = in; + + /* pState pointer is incremented twice as the real values are located alternatively in the array */ + pS1++; + + /* Initializing the loop counter */ + i = (S->N - 1U); + + do + { + /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */ + /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */ + in = *pS1++ - in; + *pbuff++ = in; + + /* points to the next real value */ + pS1++; + + /* Decrement loop counter */ + i--; + } while (i > 0U); + + /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/ + + /* Initializing loop counter */ + i = S->N; + + /* pbuff initialized to the pInlineBuffer (now contains the output values) */ + pbuff = pInlineBuffer; + + do + { + /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */ + in = *pbuff; + *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15)); + + /* Decrement loop counter */ + i--; + + } while (i > 0U); + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + +} + +/** + @} end of DCT4_IDCT4 group + */ diff --git a/components/nmsis/dsp/src/TransformFunctions/riscv_dct4_q31.c b/components/nmsis/dsp/src/TransformFunctions/riscv_dct4_q31.c new file mode 100644 index 00000000..34e4e68f --- /dev/null +++ b/components/nmsis/dsp/src/TransformFunctions/riscv_dct4_q31.c @@ -0,0 +1,384 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_dct4_q31.c + * Description: Processing function of DCT4 & IDCT4 Q31 + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" + +/** + @addtogroup DCT4_IDCT4 + @{ + */ + +/** + @brief Processing function for the Q31 DCT4/IDCT4. + @param[in] S points to an instance of the Q31 DCT4 structure. + @param[in] pState points to state buffer. + @param[in,out] pInlineBuffer points to the in-place input and output buffer. + @return none + + @par Input an output formats + Input samples need to be downscaled by 1 bit to avoid saturations in the Q31 DCT process, + as the conversion from DCT2 to DCT4 involves one subtraction. + Internally inputs are downscaled in the RFFT process function to avoid overflows. + Number of bits downscaled, depends on the size of the transform. + The input and output formats for different DCT sizes and number of bits to upscale are + mentioned in the table below: + + \image html dct4FormatsQ31Table.png + */ + +void riscv_dct4_q31( + const riscv_dct4_instance_q31 * S, + q31_t * pState, + q31_t * pInlineBuffer) +{ + const q31_t *weights = S->pTwiddle; /* Pointer to the Weights table */ + const q31_t *cosFact = S->pCosFactor; /* Pointer to the cos factors table */ + q31_t *pS1, *pS2, *pbuff; /* Temporary pointers for input buffer and pState buffer */ + q31_t in; /* Temporary variable */ + uint32_t i; /* Loop counter */ + + + /* DCT4 computation involves DCT2 (which is calculated using RFFT) + * along with some pre-processing and post-processing. + * Computational procedure is explained as follows: + * (a) Pre-processing involves multiplying input with cos factor, + * r(n) = 2 * u(n) * cos(pi*(2*n+1)/(4*n)) + * where, + * r(n) -- output of preprocessing + * u(n) -- input to preprocessing(actual Source buffer) + * (b) Calculation of DCT2 using FFT is divided into three steps: + * Step1: Re-ordering of even and odd elements of input. + * Step2: Calculating FFT of the re-ordered input. + * Step3: Taking the real part of the product of FFT output and weights. + * (c) Post-processing - DCT4 can be obtained from DCT2 output using the following equation: + * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0) + * where, + * Y4 -- DCT4 output, Y2 -- DCT2 output + * (d) Multiplying the output with the normalizing factor sqrt(2/N). + */ + + /*-------- Pre-processing ------------*/ + /* Multiplying input with cos factor i.e. r(n) = 2 * x(n) * cos(pi*(2*n+1)/(4*n)) */ + riscv_mult_q31 (pInlineBuffer, cosFact, pInlineBuffer, S->N); + riscv_shift_q31 (pInlineBuffer, 1, pInlineBuffer, S->N); + + /* ---------------------------------------------------------------- + * Step1: Re-ordering of even and odd elements as + * pState[i] = pInlineBuffer[2*i] and + * pState[N-i-1] = pInlineBuffer[2*i+1] where i = 0 to N/2 + ---------------------------------------------------------------------*/ + + /* pS1 initialized to pState */ + pS1 = pState; + + /* pS2 initialized to pState+N-1, so that it points to the end of the state buffer */ + pS2 = pState + (S->N - 1U); + + /* pbuff initialized to input buffer */ + pbuff = pInlineBuffer; + + +#if defined (RISCV_MATH_LOOPUNROLL) + + /* Initializing the loop counter to N/2 >> 2 for loop unrolling by 4 */ + i = S->Nby2 >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + do + { + /* Re-ordering of even and odd elements */ + /* pState[i] = pInlineBuffer[2*i] */ + *pS1++ = *pbuff++; + /* pState[N-i-1] = pInlineBuffer[2*i+1] */ + *pS2-- = *pbuff++; + + *pS1++ = *pbuff++; + *pS2-- = *pbuff++; + + *pS1++ = *pbuff++; + *pS2-- = *pbuff++; + + *pS1++ = *pbuff++; + *pS2-- = *pbuff++; + + /* Decrement loop counter */ + i--; + } while (i > 0U); + + /* pbuff initialized to input buffer */ + pbuff = pInlineBuffer; + + /* pS1 initialized to pState */ + pS1 = pState; + + /* Initializing the loop counter to N/4 instead of N for loop unrolling */ + i = S->N >> 2U; + + /* Processing with loop unrolling 4 times as N is always multiple of 4. + * Compute 4 outputs at a time */ + do + { + /* Writing the re-ordered output back to inplace input buffer */ + *pbuff++ = *pS1++; + *pbuff++ = *pS1++; + *pbuff++ = *pS1++; + *pbuff++ = *pS1++; + + /* Decrement the loop counter */ + i--; + } while (i > 0U); + + + /* --------------------------------------------------------- + * Step2: Calculate RFFT for N-point input + * ---------------------------------------------------------- */ + /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */ + riscv_rfft_q31 (S->pRfft, pInlineBuffer, pState); + + /*---------------------------------------------------------------------- + * Step3: Multiply the FFT output with the weights. + *----------------------------------------------------------------------*/ + riscv_cmplx_mult_cmplx_q31 (pState, weights, pState, S->N); + + /* The output of complex multiplication is in 3.29 format. + * Hence changing the format of N (i.e. 2*N elements) complex numbers to 1.31 format by shifting left by 2 bits. */ + riscv_shift_q31 (pState, 2, pState, S->N * 2); + + /* ----------- Post-processing ---------- */ + /* DCT-IV can be obtained from DCT-II by the equation, + * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0) + * Hence, Y4(0) = Y2(0)/2 */ + /* Getting only real part from the output and Converting to DCT-IV */ + + /* Initializing the loop counter to N >> 2 for loop unrolling by 4 */ + i = (S->N - 1U) >> 2U; + + /* pbuff initialized to input buffer. */ + pbuff = pInlineBuffer; + + /* pS1 initialized to pState */ + pS1 = pState; + + /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */ + in = *pS1++ >> 1U; + /* input buffer acts as inplace, so output values are stored in the input itself. */ + *pbuff++ = in; + + /* pState pointer is incremented twice as the real values are located alternatively in the array */ + pS1++; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + do + { + /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */ + /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */ + in = *pS1++ - in; + *pbuff++ = in; + /* points to the next real value */ + pS1++; + + in = *pS1++ - in; + *pbuff++ = in; + pS1++; + + in = *pS1++ - in; + *pbuff++ = in; + pS1++; + + in = *pS1++ - in; + *pbuff++ = in; + pS1++; + + /* Decrement the loop counter */ + i--; + } while (i > 0U); + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + i = (S->N - 1U) % 0x4U; + + while (i > 0U) + { + /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */ + /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */ + in = *pS1++ - in; + *pbuff++ = in; + + /* points to the next real value */ + pS1++; + + /* Decrement loop counter */ + i--; + } + + + /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/ + + /* Initializing the loop counter to N/4 instead of N for loop unrolling */ + i = S->N >> 2U; + + /* pbuff initialized to the pInlineBuffer(now contains the output values) */ + pbuff = pInlineBuffer; + + /* Processing with loop unrolling 4 times as N is always multiple of 4. Compute 4 outputs at a time */ + do + { + /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */ + in = *pbuff; + *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31)); + + in = *pbuff; + *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31)); + + in = *pbuff; + *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31)); + + in = *pbuff; + *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31)); + + /* Decrement loop counter */ + i--; + } while (i > 0U); + + +#else + + /* Initializing the loop counter to N/2 */ + i = S->Nby2; + + do + { + /* Re-ordering of even and odd elements */ + /* pState[i] = pInlineBuffer[2*i] */ + *pS1++ = *pbuff++; + /* pState[N-i-1] = pInlineBuffer[2*i+1] */ + *pS2-- = *pbuff++; + + /* Decrement the loop counter */ + i--; + } while (i > 0U); + + /* pbuff initialized to input buffer */ + pbuff = pInlineBuffer; + + /* pS1 initialized to pState */ + pS1 = pState; + + /* Initializing the loop counter */ + i = S->N; + + do + { + /* Writing the re-ordered output back to inplace input buffer */ + *pbuff++ = *pS1++; + + /* Decrement the loop counter */ + i--; + } while (i > 0U); + + + /* --------------------------------------------------------- + * Step2: Calculate RFFT for N-point input + * ---------------------------------------------------------- */ + /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */ + riscv_rfft_q31 (S->pRfft, pInlineBuffer, pState); + + /*---------------------------------------------------------------------- + * Step3: Multiply the FFT output with the weights. + *----------------------------------------------------------------------*/ + riscv_cmplx_mult_cmplx_q31 (pState, weights, pState, S->N); + + /* The output of complex multiplication is in 3.29 format. + * Hence changing the format of N (i.e. 2*N elements) complex numbers to 1.31 format by shifting left by 2 bits. */ + riscv_shift_q31(pState, 2, pState, S->N * 2); + + /* ----------- Post-processing ---------- */ + /* DCT-IV can be obtained from DCT-II by the equation, + * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0) + * Hence, Y4(0) = Y2(0)/2 */ + /* Getting only real part from the output and Converting to DCT-IV */ + + /* pbuff initialized to input buffer. */ + pbuff = pInlineBuffer; + + /* pS1 initialized to pState */ + pS1 = pState; + + /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */ + in = *pS1++ >> 1U; + /* input buffer acts as inplace, so output values are stored in the input itself. */ + *pbuff++ = in; + + /* pState pointer is incremented twice as the real values are located alternatively in the array */ + pS1++; + + /* Initializing the loop counter */ + i = (S->N - 1U); + + while (i > 0U) + { + /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */ + /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */ + in = *pS1++ - in; + *pbuff++ = in; + + /* points to the next real value */ + pS1++; + + /* Decrement loop counter */ + i--; + } + + /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/ + + /* Initializing loop counter */ + i = S->N; + + /* pbuff initialized to the pInlineBuffer (now contains the output values) */ + pbuff = pInlineBuffer; + + do + { + /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */ + in = *pbuff; + *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31)); + + /* Decrement loop counter */ + i--; + } while (i > 0U); + +#endif /* #if defined (RISCV_MATH_LOOPUNROLL) */ + +} + +/** + @} end of DCT4_IDCT4 group + */ diff --git a/components/nmsis/dsp/src/TransformFunctions/riscv_rfft_f32.c b/components/nmsis/dsp/src/TransformFunctions/riscv_rfft_f32.c new file mode 100644 index 00000000..115e91e3 --- /dev/null +++ b/components/nmsis/dsp/src/TransformFunctions/riscv_rfft_f32.c @@ -0,0 +1,319 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_rfft_f32.c + * Description: RFFT & RIFFT Floating point process function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" + +/* ---------------------------------------------------------------------- + * Internal functions prototypes + * -------------------------------------------------------------------- */ + +extern void riscv_radix4_butterfly_f32( + float32_t * pSrc, + uint16_t fftLen, + const float32_t * pCoef, + uint16_t twidCoefModifier); + +extern void riscv_radix4_butterfly_inverse_f32( + float32_t * pSrc, + uint16_t fftLen, + const float32_t * pCoef, + uint16_t twidCoefModifier, + float32_t onebyfftLen); + +extern void riscv_bitreversal_f32( + float32_t * pSrc, + uint16_t fftSize, + uint16_t bitRevFactor, + const uint16_t * pBitRevTab); + +void riscv_split_rfft_f32( + float32_t * pSrc, + uint32_t fftLen, + const float32_t * pATable, + const float32_t * pBTable, + float32_t * pDst, + uint32_t modifier); + +void riscv_split_rifft_f32( + float32_t * pSrc, + uint32_t fftLen, + const float32_t * pATable, + const float32_t * pBTable, + float32_t * pDst, + uint32_t modifier); + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup RealFFT + @{ + */ + +/** + @brief Processing function for the floating-point RFFT/RIFFT. + Source buffer is modified by this function. + + @deprecated Do not use this function. It has been superceded by \ref riscv_rfft_fast_f32 and will be removed in the future. + @param[in] S points to an instance of the floating-point RFFT/RIFFT structure + @param[in] pSrc points to the input buffer + @param[out] pDst points to the output buffer + @return none + + @par + For the RIFFT, the source buffer must at least have length + fftLenReal + 2. + The last two elements must be equal to what would be generated + by the RFFT: + (pSrc[0] - pSrc[1]) and 0.0f + */ + +void riscv_rfft_f32( + const riscv_rfft_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst) +{ + const riscv_cfft_radix4_instance_f32 *S_CFFT = S->pCfft; + + /* Calculation of Real IFFT of input */ + if (S->ifftFlagR == 1U) + { + /* Real IFFT core process */ + riscv_split_rifft_f32 (pSrc, S->fftLenBy2, S->pTwiddleAReal, S->pTwiddleBReal, pDst, S->twidCoefRModifier); + + + /* Complex radix-4 IFFT process */ + riscv_radix4_butterfly_inverse_f32 (pDst, S_CFFT->fftLen, S_CFFT->pTwiddle, S_CFFT->twidCoefModifier, S_CFFT->onebyfftLen); + + /* Bit reversal process */ + if (S->bitReverseFlagR == 1U) + { + riscv_bitreversal_f32 (pDst, S_CFFT->fftLen, S_CFFT->bitRevFactor, S_CFFT->pBitRevTable); + } + } + else + { + /* Calculation of RFFT of input */ + + /* Complex radix-4 FFT process */ + riscv_radix4_butterfly_f32 (pSrc, S_CFFT->fftLen, S_CFFT->pTwiddle, S_CFFT->twidCoefModifier); + + /* Bit reversal process */ + if (S->bitReverseFlagR == 1U) + { + riscv_bitreversal_f32 (pSrc, S_CFFT->fftLen, S_CFFT->bitRevFactor, S_CFFT->pBitRevTable); + } + + /* Real FFT core process */ + riscv_split_rfft_f32 (pSrc, S->fftLenBy2, S->pTwiddleAReal, S->pTwiddleBReal, pDst, S->twidCoefRModifier); + } + +} + +/** + @} end of RealFFT group + */ + +/** + @brief Core Real FFT process + @param[in] pSrc points to input buffer + @param[in] fftLen length of FFT + @param[in] pATable points to twiddle Coef A buffer + @param[in] pBTable points to twiddle Coef B buffer + @param[out] pDst points to output buffer + @param[in] modifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table + @return none + */ + +void riscv_split_rfft_f32( + float32_t * pSrc, + uint32_t fftLen, + const float32_t * pATable, + const float32_t * pBTable, + float32_t * pDst, + uint32_t modifier) +{ + uint32_t i; /* Loop Counter */ + float32_t outR, outI; /* Temporary variables for output */ + const float32_t *pCoefA, *pCoefB; /* Temporary pointers for twiddle factors */ + float32_t CoefA1, CoefA2, CoefB1; /* Temporary variables for twiddle coefficients */ + float32_t *pDst1 = &pDst[2], *pDst2 = &pDst[(4U * fftLen) - 1U]; /* temp pointers for output buffer */ + float32_t *pSrc1 = &pSrc[2], *pSrc2 = &pSrc[(2U * fftLen) - 1U]; /* temp pointers for input buffer */ + + /* Init coefficient pointers */ + pCoefA = &pATable[modifier * 2]; + pCoefB = &pBTable[modifier * 2]; + + i = fftLen - 1U; + + while (i > 0U) + { + /* + outR = ( pSrc[2 * i] * pATable[2 * i] + - pSrc[2 * i + 1] * pATable[2 * i + 1] + + pSrc[2 * n - 2 * i] * pBTable[2 * i] + + pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]); + + outI = ( pIn[2 * i + 1] * pATable[2 * i] + + pIn[2 * i] * pATable[2 * i + 1] + + pIn[2 * n - 2 * i] * pBTable[2 * i + 1] + - pIn[2 * n - 2 * i + 1] * pBTable[2 * i]); + */ + + /* read pATable[2 * i] */ + CoefA1 = *pCoefA++; + /* pATable[2 * i + 1] */ + CoefA2 = *pCoefA; + + /* pSrc[2 * i] * pATable[2 * i] */ + outR = *pSrc1 * CoefA1; + /* pSrc[2 * i] * CoefA2 */ + outI = *pSrc1++ * CoefA2; + + /* (pSrc[2 * i + 1] + pSrc[2 * fftLen - 2 * i + 1]) * CoefA2 */ + outR -= (*pSrc1 + *pSrc2) * CoefA2; + /* pSrc[2 * i + 1] * CoefA1 */ + outI += *pSrc1++ * CoefA1; + + CoefB1 = *pCoefB; + + /* pSrc[2 * fftLen - 2 * i + 1] * CoefB1 */ + outI -= *pSrc2-- * CoefB1; + /* pSrc[2 * fftLen - 2 * i] * CoefA2 */ + outI -= *pSrc2 * CoefA2; + + /* pSrc[2 * fftLen - 2 * i] * CoefB1 */ + outR += *pSrc2-- * CoefB1; + + /* write output */ + *pDst1++ = outR; + *pDst1++ = outI; + + /* write complex conjugate output */ + *pDst2-- = -outI; + *pDst2-- = outR; + + /* update coefficient pointer */ + pCoefB = pCoefB + (modifier * 2U); + pCoefA = pCoefA + ((modifier * 2U) - 1U); + + i--; + + } + + pDst[2U * fftLen] = pSrc[0] - pSrc[1]; + pDst[(2U * fftLen) + 1U] = 0.0f; + + pDst[0] = pSrc[0] + pSrc[1]; + pDst[1] = 0.0f; + +} + + +/** + @brief Core Real IFFT process + @param[in] pSrc points to input buffer + @param[in] fftLen length of FFT + @param[in] pATable points to twiddle Coef A buffer + @param[in] pBTable points to twiddle Coef B buffer + @param[out] pDst points to output buffer + @param[in] modifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table + @return none + */ + +void riscv_split_rifft_f32( + float32_t * pSrc, + uint32_t fftLen, + const float32_t * pATable, + const float32_t * pBTable, + float32_t * pDst, + uint32_t modifier) +{ + float32_t outR, outI; /* Temporary variables for output */ + const float32_t *pCoefA, *pCoefB; /* Temporary pointers for twiddle factors */ + float32_t CoefA1, CoefA2, CoefB1; /* Temporary variables for twiddle coefficients */ + float32_t *pSrc1 = &pSrc[0], *pSrc2 = &pSrc[(2U * fftLen) + 1U]; + + pCoefA = &pATable[0]; + pCoefB = &pBTable[0]; + + while (fftLen > 0U) + { + /* + outR = ( pIn[2 * i] * pATable[2 * i] + + pIn[2 * i + 1] * pATable[2 * i + 1] + + pIn[2 * n - 2 * i] * pBTable[2 * i] + - pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]); + + outI = ( pIn[2 * i + 1] * pATable[2 * i] + - pIn[2 * i] * pATable[2 * i + 1] + - pIn[2 * n - 2 * i] * pBTable[2 * i + 1] + - pIn[2 * n - 2 * i + 1] * pBTable[2 * i]); + */ + + CoefA1 = *pCoefA++; + CoefA2 = *pCoefA; + + /* outR = (pSrc[2 * i] * CoefA1 */ + outR = *pSrc1 * CoefA1; + + /* - pSrc[2 * i] * CoefA2 */ + outI = -(*pSrc1++) * CoefA2; + + /* (pSrc[2 * i + 1] + pSrc[2 * fftLen - 2 * i + 1]) * CoefA2 */ + outR += (*pSrc1 + *pSrc2) * CoefA2; + + /* pSrc[2 * i + 1] * CoefA1 */ + outI += (*pSrc1++) * CoefA1; + + CoefB1 = *pCoefB; + + /* - pSrc[2 * fftLen - 2 * i + 1] * CoefB1 */ + outI -= *pSrc2-- * CoefB1; + + /* pSrc[2 * fftLen - 2 * i] * CoefB1 */ + outR += *pSrc2 * CoefB1; + + /* pSrc[2 * fftLen - 2 * i] * CoefA2 */ + outI += *pSrc2-- * CoefA2; + + /* write output */ + *pDst++ = outR; + *pDst++ = outI; + + /* update coefficient pointer */ + pCoefB = pCoefB + (modifier * 2); + pCoefA = pCoefA + (modifier * 2 - 1); + + /* Decrement loop count */ + fftLen--; + } + +} diff --git a/components/nmsis/dsp/src/TransformFunctions/riscv_rfft_fast_f16.c b/components/nmsis/dsp/src/TransformFunctions/riscv_rfft_fast_f16.c new file mode 100644 index 00000000..18f90b63 --- /dev/null +++ b/components/nmsis/dsp/src/TransformFunctions/riscv_rfft_fast_f16.c @@ -0,0 +1,331 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_rfft_fast_f16.c + * Description: RFFT & RIFFT Floating point process function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions_f16.h" +#include "riscv_common_tables_f16.h" + +#if defined(RISCV_FLOAT16_SUPPORTED) + + +void stage_rfft_f16( + const riscv_rfft_fast_instance_f16 * S, + float16_t * p, + float16_t * pOut) +{ + int32_t k; /* Loop Counter */ + float16_t twR, twI; /* RFFT Twiddle coefficients */ + const float16_t * pCoeff = S->pTwiddleRFFT; /* Points to RFFT Twiddle factors */ + float16_t *pA = p; /* increasing pointer */ + float16_t *pB = p; /* decreasing pointer */ + float16_t xAR, xAI, xBR, xBI; /* temporary variables */ + float16_t t1a, t1b; /* temporary variables */ + float16_t p0, p1, p2, p3; /* temporary variables */ + + + k = (S->Sint).fftLen - 1; + + /* Pack first and last sample of the frequency domain together */ + + xBR = pB[0]; + xBI = pB[1]; + xAR = pA[0]; + xAI = pA[1]; + + twR = *pCoeff++ ; + twI = *pCoeff++ ; + + + // U1 = XA(1) + XB(1); % It is real + t1a = xBR + xAR ; + + // U2 = XB(1) - XA(1); % It is imaginary + t1b = xBI + xAI ; + + // real(tw * (xB - xA)) = twR * (xBR - xAR) - twI * (xBI - xAI); + // imag(tw * (xB - xA)) = twI * (xBR - xAR) + twR * (xBI - xAI); + *pOut++ = 0.5f * ( t1a + t1b ); + *pOut++ = 0.5f * ( t1a - t1b ); + + // XA(1) = 1/2*( U1 - imag(U2) + i*( U1 +imag(U2) )); + pB = p + 2*k; + pA += 2; + + do + { + /* + function X = my_split_rfft(X, ifftFlag) + % X is a series of real numbers + L = length(X); + XC = X(1:2:end) +i*X(2:2:end); + XA = fft(XC); + XB = conj(XA([1 end:-1:2])); + TW = i*exp(-2*pi*i*[0:L/2-1]/L).'; + for l = 2:L/2 + XA(l) = 1/2 * (XA(l) + XB(l) + TW(l) * (XB(l) - XA(l))); + end + XA(1) = 1/2* (XA(1) + XB(1) + TW(1) * (XB(1) - XA(1))) + i*( 1/2*( XA(1) + XB(1) + i*( XA(1) - XB(1)))); + X = XA; + */ + + xBI = pB[1]; + xBR = pB[0]; + xAR = pA[0]; + xAI = pA[1]; + + twR = *pCoeff++; + twI = *pCoeff++; + + t1a = xBR - xAR ; + t1b = xBI + xAI ; + + // real(tw * (xB - xA)) = twR * (xBR - xAR) - twI * (xBI - xAI); + // imag(tw * (xB - xA)) = twI * (xBR - xAR) + twR * (xBI - xAI); + p0 = twR * t1a; + p1 = twI * t1a; + p2 = twR * t1b; + p3 = twI * t1b; + + *pOut++ = 0.5f * (xAR + xBR + p0 + p3 ); //xAR + *pOut++ = 0.5f * (xAI - xBI + p1 - p2 ); //xAI + + + pA += 2; + pB -= 2; + k--; + } while (k > 0); +} + +/* Prepares data for inverse cfft */ +void merge_rfft_f16( + const riscv_rfft_fast_instance_f16 * S, + float16_t * p, + float16_t * pOut) +{ + int32_t k; /* Loop Counter */ + float16_t twR, twI; /* RFFT Twiddle coefficients */ + const float16_t *pCoeff = S->pTwiddleRFFT; /* Points to RFFT Twiddle factors */ + float16_t *pA = p; /* increasing pointer */ + float16_t *pB = p; /* decreasing pointer */ + float16_t xAR, xAI, xBR, xBI; /* temporary variables */ + float16_t t1a, t1b, r, s, t, u; /* temporary variables */ + + k = (S->Sint).fftLen - 1; + + xAR = pA[0]; + xAI = pA[1]; + + pCoeff += 2 ; + + *pOut++ = 0.5f * ( xAR + xAI ); + *pOut++ = 0.5f * ( xAR - xAI ); + + pB = p + 2*k ; + pA += 2 ; + + while (k > 0) + { + /* G is half of the frequency complex spectrum */ + //for k = 2:N + // Xk(k) = 1/2 * (G(k) + conj(G(N-k+2)) + Tw(k)*( G(k) - conj(G(N-k+2)))); + xBI = pB[1] ; + xBR = pB[0] ; + xAR = pA[0]; + xAI = pA[1]; + + twR = *pCoeff++; + twI = *pCoeff++; + + t1a = xAR - xBR ; + t1b = xAI + xBI ; + + r = twR * t1a; + s = twI * t1b; + t = twI * t1a; + u = twR * t1b; + + // real(tw * (xA - xB)) = twR * (xAR - xBR) - twI * (xAI - xBI); + // imag(tw * (xA - xB)) = twI * (xAR - xBR) + twR * (xAI - xBI); + *pOut++ = 0.5f * (xAR + xBR - r - s ); //xAR + *pOut++ = 0.5f * (xAI - xBI + t - u ); //xAI + + pA += 2; + pB -= 2; + k--; + } + +} + + +/** + @ingroup groupTransforms +*/ + +/** + @defgroup RealFFT Real FFT Functions + + @par + The NMSIS DSP library includes specialized algorithms for computing the + FFT of real data sequences. The FFT is defined over complex data but + in many applications the input is real. Real FFT algorithms take advantage + of the symmetry properties of the FFT and have a speed advantage over complex + algorithms of the same length. + @par + The Fast RFFT algorithm relays on the mixed radix CFFT that save processor usage. + @par + The real length N forward FFT of a sequence is computed using the steps shown below. + @par + \image html RFFT.png "Real Fast Fourier Transform" + @par + The real sequence is initially treated as if it were complex to perform a CFFT. + Later, a processing stage reshapes the data to obtain half of the frequency spectrum + in complex format. Except the first complex number that contains the two real numbers + X[0] and X[N/2] all the data is complex. In other words, the first complex sample + contains two real values packed. + @par + The input for the inverse RFFT should keep the same format as the output of the + forward RFFT. A first processing stage pre-process the data to later perform an + inverse CFFT. + @par + \image html RIFFT.png "Real Inverse Fast Fourier Transform" + @par + The algorithms for floating-point, Q15, and Q31 data are slightly different + and we describe each algorithm in turn. + @par Floating-point + The main functions are \ref riscv_rfft_fast_f16() and \ref riscv_rfft_fast_init_f16(). + + @par + The FFT of a real N-point sequence has even symmetry in the frequency domain. + The second half of the data equals the conjugate of the first half flipped in frequency. + Looking at the data, we see that we can uniquely represent the FFT using only N/2 complex numbers. + These are packed into the output array in alternating real and imaginary components: + @par + X = { real[0], imag[0], real[1], imag[1], real[2], imag[2] ... + real[(N/2)-1], imag[(N/2)-1 } + @par + It happens that the first complex number (real[0], imag[0]) is actually + all real. real[0] represents the DC offset, and imag[0] should be 0. + (real[1], imag[1]) is the fundamental frequency, (real[2], imag[2]) is + the first harmonic and so on. + @par + The real FFT functions pack the frequency domain data in this fashion. + The forward transform outputs the data in this form and the inverse + transform expects input data in this form. The function always performs + the needed bitreversal so that the input and output data is always in + normal order. The functions support lengths of [32, 64, 128, ..., 4096] + samples. + @par Q15 and Q31 + The real algorithms are defined in a similar manner and utilize N/2 complex + transforms behind the scenes. + @par + The complex transforms used internally include scaling to prevent fixed-point + overflows. The overall scaling equals 1/(fftLen/2). + Due to the use of complex transform internally, the source buffer is + modified by the rfft. + @par + A separate instance structure must be defined for each transform used but + twiddle factor and bit reversal tables can be reused. + @par + There is also an associated initialization function for each data type. + The initialization function performs the following operations: + - Sets the values of the internal structure fields. + - Initializes twiddle factor table and bit reversal table pointers. + - Initializes the internal complex FFT data structure. + @par + Use of the initialization function is optional **except for MVE versions where it is mandatory**. + If you don't use the initialization functions, then the structures should be initialized with code + similar to the one below: + 
+      riscv_rfft_instance_q31 S = {fftLenReal, fftLenBy2, ifftFlagR, bitReverseFlagR, twidCoefRModifier, pTwiddleAReal, pTwiddleBReal, pCfft};
+      riscv_rfft_instance_q15 S = {fftLenReal, fftLenBy2, ifftFlagR, bitReverseFlagR, twidCoefRModifier, pTwiddleAReal, pTwiddleBReal, pCfft};
+
+ where fftLenReal is the length of the real transform; + fftLenBy2 length of the internal complex transform (fftLenReal/2). + ifftFlagR Selects forward (=0) or inverse (=1) transform. + bitReverseFlagR Selects bit reversed output (=0) or normal order + output (=1). + twidCoefRModifier stride modifier for the twiddle factor table. + The value is based on the FFT length; + pTwiddleARealpoints to the A array of twiddle coefficients; + pTwiddleBRealpoints to the B array of twiddle coefficients; + pCfft points to the CFFT Instance structure. The CFFT structure + must also be initialized. +@par + Note that with MVE versions you can't initialize instance structures directly and **must + use the initialization function**. + */ + +/** + @addtogroup RealFFT + @{ +*/ + +/** + @brief Processing function for the floating-point real FFT. + @param[in] S points to an riscv_rfft_fast_instance_f16 structure + @param[in] p points to input buffer (Source buffer is modified by this function.) + @param[in] pOut points to output buffer + @param[in] ifftFlag + - value = 0: RFFT + - value = 1: RIFFT + @return none +*/ + +void riscv_rfft_fast_f16( + const riscv_rfft_fast_instance_f16 * S, + float16_t * p, + float16_t * pOut, + uint8_t ifftFlag) +{ + const riscv_cfft_instance_f16 * Sint = &(S->Sint); + + + /* Calculation of Real FFT */ + if (ifftFlag) + { + /* Real FFT compression */ + merge_rfft_f16(S, p, pOut); + /* Complex radix-4 IFFT process */ + riscv_cfft_f16( Sint, pOut, ifftFlag, 1); + } + else + { + + /* Calculation of RFFT of input */ + riscv_cfft_f16( Sint, p, ifftFlag, 1); + + /* Real FFT extraction */ + stage_rfft_f16(S, p, pOut); + } +} + +/** +* @} end of RealFFT group +*/ + +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ diff --git a/components/nmsis/dsp/src/TransformFunctions/riscv_rfft_fast_f32.c b/components/nmsis/dsp/src/TransformFunctions/riscv_rfft_fast_f32.c new file mode 100644 index 00000000..647cfc4e --- /dev/null +++ b/components/nmsis/dsp/src/TransformFunctions/riscv_rfft_fast_f32.c @@ -0,0 +1,324 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_rfft_fast_f32.c + * Description: RFFT & RIFFT Floating point process function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" + +void stage_rfft_f32( + const riscv_rfft_fast_instance_f32 * S, + float32_t * p, + float32_t * pOut) +{ + int32_t k; /* Loop Counter */ + float32_t twR, twI; /* RFFT Twiddle coefficients */ + const float32_t * pCoeff = S->pTwiddleRFFT; /* Points to RFFT Twiddle factors */ + float32_t *pA = p; /* increasing pointer */ + float32_t *pB = p; /* decreasing pointer */ + float32_t xAR, xAI, xBR, xBI; /* temporary variables */ + float32_t t1a, t1b; /* temporary variables */ + float32_t p0, p1, p2, p3; /* temporary variables */ + + + k = (S->Sint).fftLen - 1; + + /* Pack first and last sample of the frequency domain together */ + + xBR = pB[0]; + xBI = pB[1]; + xAR = pA[0]; + xAI = pA[1]; + + twR = *pCoeff++ ; + twI = *pCoeff++ ; + + + // U1 = XA(1) + XB(1); % It is real + t1a = xBR + xAR ; + + // U2 = XB(1) - XA(1); % It is imaginary + t1b = xBI + xAI ; + + // real(tw * (xB - xA)) = twR * (xBR - xAR) - twI * (xBI - xAI); + // imag(tw * (xB - xA)) = twI * (xBR - xAR) + twR * (xBI - xAI); + *pOut++ = 0.5f * ( t1a + t1b ); + *pOut++ = 0.5f * ( t1a - t1b ); + + // XA(1) = 1/2*( U1 - imag(U2) + i*( U1 +imag(U2) )); + pB = p + 2*k; + pA += 2; + + do + { + /* + function X = my_split_rfft(X, ifftFlag) + % X is a series of real numbers + L = length(X); + XC = X(1:2:end) +i*X(2:2:end); + XA = fft(XC); + XB = conj(XA([1 end:-1:2])); + TW = i*exp(-2*pi*i*[0:L/2-1]/L).'; + for l = 2:L/2 + XA(l) = 1/2 * (XA(l) + XB(l) + TW(l) * (XB(l) - XA(l))); + end + XA(1) = 1/2* (XA(1) + XB(1) + TW(1) * (XB(1) - XA(1))) + i*( 1/2*( XA(1) + XB(1) + i*( XA(1) - XB(1)))); + X = XA; + */ + + xBI = pB[1]; + xBR = pB[0]; + xAR = pA[0]; + xAI = pA[1]; + + twR = *pCoeff++; + twI = *pCoeff++; + + t1a = xBR - xAR ; + t1b = xBI + xAI ; + + // real(tw * (xB - xA)) = twR * (xBR - xAR) - twI * (xBI - xAI); + // imag(tw * (xB - xA)) = twI * (xBR - xAR) + twR * (xBI - xAI); + p0 = twR * t1a; + p1 = twI * t1a; + p2 = twR * t1b; + p3 = twI * t1b; + + *pOut++ = 0.5f * (xAR + xBR + p0 + p3 ); //xAR + *pOut++ = 0.5f * (xAI - xBI + p1 - p2 ); //xAI + + + pA += 2; + pB -= 2; + k--; + } while (k > 0); +} + +/* Prepares data for inverse cfft */ +void merge_rfft_f32( + const riscv_rfft_fast_instance_f32 * S, + float32_t * p, + float32_t * pOut) +{ + int32_t k; /* Loop Counter */ + float32_t twR, twI; /* RFFT Twiddle coefficients */ + const float32_t *pCoeff = S->pTwiddleRFFT; /* Points to RFFT Twiddle factors */ + float32_t *pA = p; /* increasing pointer */ + float32_t *pB = p; /* decreasing pointer */ + float32_t xAR, xAI, xBR, xBI; /* temporary variables */ + float32_t t1a, t1b, r, s, t, u; /* temporary variables */ + + k = (S->Sint).fftLen - 1; + + xAR = pA[0]; + xAI = pA[1]; + + pCoeff += 2 ; + + *pOut++ = 0.5f * ( xAR + xAI ); + *pOut++ = 0.5f * ( xAR - xAI ); + + pB = p + 2*k ; + pA += 2 ; + + while (k > 0) + { + /* G is half of the frequency complex spectrum */ + //for k = 2:N + // Xk(k) = 1/2 * (G(k) + conj(G(N-k+2)) + Tw(k)*( G(k) - conj(G(N-k+2)))); + xBI = pB[1] ; + xBR = pB[0] ; + xAR = pA[0]; + xAI = pA[1]; + + twR = *pCoeff++; + twI = *pCoeff++; + + t1a = xAR - xBR ; + t1b = xAI + xBI ; + + r = twR * t1a; + s = twI * t1b; + t = twI * t1a; + u = twR * t1b; + + // real(tw * (xA - xB)) = twR * (xAR - xBR) - twI * (xAI - xBI); + // imag(tw * (xA - xB)) = twI * (xAR - xBR) + twR * (xAI - xBI); + *pOut++ = 0.5f * (xAR + xBR - r - s ); //xAR + *pOut++ = 0.5f * (xAI - xBI + t - u ); //xAI + + pA += 2; + pB -= 2; + k--; + } + +} + + +/** + @ingroup groupTransforms +*/ + +/** + @defgroup RealFFT Real FFT Functions + + @par + The NMSIS DSP library includes specialized algorithms for computing the + FFT of real data sequences. The FFT is defined over complex data but + in many applications the input is real. Real FFT algorithms take advantage + of the symmetry properties of the FFT and have a speed advantage over complex + algorithms of the same length. + @par + The Fast RFFT algorithm relays on the mixed radix CFFT that save processor usage. + @par + The real length N forward FFT of a sequence is computed using the steps shown below. + @par + \image html RFFT.png "Real Fast Fourier Transform" + @par + The real sequence is initially treated as if it were complex to perform a CFFT. + Later, a processing stage reshapes the data to obtain half of the frequency spectrum + in complex format. Except the first complex number that contains the two real numbers + X[0] and X[N/2] all the data is complex. In other words, the first complex sample + contains two real values packed. + @par + The input for the inverse RFFT should keep the same format as the output of the + forward RFFT. A first processing stage pre-process the data to later perform an + inverse CFFT. + @par + \image html RIFFT.png "Real Inverse Fast Fourier Transform" + @par + The algorithms for floating-point, Q15, and Q31 data are slightly different + and we describe each algorithm in turn. + @par Floating-point + The main functions are \ref riscv_rfft_fast_f32() and \ref riscv_rfft_fast_init_f32(). + The older functions \ref riscv_rfft_f32() and \ref riscv_rfft_init_f32() have been deprecated + but are still documented. + @par + The FFT of a real N-point sequence has even symmetry in the frequency domain. + The second half of the data equals the conjugate of the first half flipped in frequency. + Looking at the data, we see that we can uniquely represent the FFT using only N/2 complex numbers. + These are packed into the output array in alternating real and imaginary components: + @par + X = { real[0], imag[0], real[1], imag[1], real[2], imag[2] ... + real[(N/2)-1], imag[(N/2)-1 } + @par + It happens that the first complex number (real[0], imag[0]) is actually + all real. real[0] represents the DC offset, and imag[0] should be 0. + (real[1], imag[1]) is the fundamental frequency, (real[2], imag[2]) is + the first harmonic and so on. + @par + The real FFT functions pack the frequency domain data in this fashion. + The forward transform outputs the data in this form and the inverse + transform expects input data in this form. The function always performs + the needed bitreversal so that the input and output data is always in + normal order. The functions support lengths of [32, 64, 128, ..., 4096] + samples. + @par Q15 and Q31 + The real algorithms are defined in a similar manner and utilize N/2 complex + transforms behind the scenes. + @par + The complex transforms used internally include scaling to prevent fixed-point + overflows. The overall scaling equals 1/(fftLen/2). + Due to the use of complex transform internally, the source buffer is + modified by the rfft. + @par + A separate instance structure must be defined for each transform used but + twiddle factor and bit reversal tables can be reused. + @par + There is also an associated initialization function for each data type. + The initialization function performs the following operations: + - Sets the values of the internal structure fields. + - Initializes twiddle factor table and bit reversal table pointers. + - Initializes the internal complex FFT data structure. + @par + Use of the initialization function is optional **except for MVE versions where it is mandatory**. + If you don't use the initialization functions, then the structures should be initialized with code + similar to the one below: + 
+      riscv_rfft_instance_q31 S = {fftLenReal, fftLenBy2, ifftFlagR, bitReverseFlagR, twidCoefRModifier, pTwiddleAReal, pTwiddleBReal, pCfft};
+      riscv_rfft_instance_q15 S = {fftLenReal, fftLenBy2, ifftFlagR, bitReverseFlagR, twidCoefRModifier, pTwiddleAReal, pTwiddleBReal, pCfft};
+
+ where fftLenReal is the length of the real transform; + fftLenBy2 length of the internal complex transform (fftLenReal/2). + ifftFlagR Selects forward (=0) or inverse (=1) transform. + bitReverseFlagR Selects bit reversed output (=0) or normal order + output (=1). + twidCoefRModifier stride modifier for the twiddle factor table. + The value is based on the FFT length; + pTwiddleARealpoints to the A array of twiddle coefficients; + pTwiddleBRealpoints to the B array of twiddle coefficients; + pCfft points to the CFFT Instance structure. The CFFT structure + must also be initialized. +@par + Note that with MVE versions you can't initialize instance structures directly and **must + use the initialization function**. + */ + +/** + @addtogroup RealFFT + @{ +*/ + +/** + @brief Processing function for the floating-point real FFT. + @param[in] S points to an riscv_rfft_fast_instance_f32 structure + @param[in] p points to input buffer (Source buffer is modified by this function.) + @param[in] pOut points to output buffer + @param[in] ifftFlag + - value = 0: RFFT + - value = 1: RIFFT + @return none +*/ + +void riscv_rfft_fast_f32( + const riscv_rfft_fast_instance_f32 * S, + float32_t * p, + float32_t * pOut, + uint8_t ifftFlag) +{ + const riscv_cfft_instance_f32 * Sint = &(S->Sint); + + /* Calculation of Real FFT */ + if (ifftFlag) + { + /* Real FFT compression */ + merge_rfft_f32(S, p, pOut); + /* Complex radix-4 IFFT process */ + riscv_cfft_f32( Sint, pOut, ifftFlag, 1); + } + else + { + /* Calculation of RFFT of input */ + riscv_cfft_f32( Sint, p, ifftFlag, 1); + + /* Real FFT extraction */ + stage_rfft_f32(S, p, pOut); + } +} + +/** +* @} end of RealFFT group +*/ diff --git a/components/nmsis/dsp/src/TransformFunctions/riscv_rfft_fast_f64.c b/components/nmsis/dsp/src/TransformFunctions/riscv_rfft_fast_f64.c new file mode 100644 index 00000000..9590d433 --- /dev/null +++ b/components/nmsis/dsp/src/TransformFunctions/riscv_rfft_fast_f64.c @@ -0,0 +1,229 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_rfft_fast_f64.c + * Description: RFFT & RIFFT Double precision Floating point process function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" + +void stage_rfft_f64( + const riscv_rfft_fast_instance_f64 * S, + float64_t * p, + float64_t * pOut) +{ + uint32_t k; /* Loop Counter */ + float64_t twR, twI; /* RFFT Twiddle coefficients */ + const float64_t * pCoeff = S->pTwiddleRFFT; /* Points to RFFT Twiddle factors */ + float64_t *pA = p; /* increasing pointer */ + float64_t *pB = p; /* decreasing pointer */ + float64_t xAR, xAI, xBR, xBI; /* temporary variables */ + float64_t t1a, t1b; /* temporary variables */ + float64_t p0, p1, p2, p3; /* temporary variables */ + + + k = (S->Sint).fftLen - 1; + + /* Pack first and last sample of the frequency domain together */ + + xBR = pB[0]; + xBI = pB[1]; + xAR = pA[0]; + xAI = pA[1]; + + twR = *pCoeff++ ; + twI = *pCoeff++ ; + + // U1 = XA(1) + XB(1); % It is real + t1a = xBR + xAR ; + + // U2 = XB(1) - XA(1); % It is imaginary + t1b = xBI + xAI ; + + // real(tw * (xB - xA)) = twR * (xBR - xAR) - twI * (xBI - xAI); + // imag(tw * (xB - xA)) = twI * (xBR - xAR) + twR * (xBI - xAI); + *pOut++ = 0.5 * ( t1a + t1b ); + *pOut++ = 0.5 * ( t1a - t1b ); + + // XA(1) = 1/2*( U1 - imag(U2) + i*( U1 +imag(U2) )); + pB = p + 2*k; + pA += 2; + + do + { + /* + function X = my_split_rfft(X, ifftFlag) + % X is a series of real numbers + L = length(X); + XC = X(1:2:end) +i*X(2:2:end); + XA = fft(XC); + XB = conj(XA([1 end:-1:2])); + TW = i*exp(-2*pi*i*[0:L/2-1]/L).'; + for l = 2:L/2 + XA(l) = 1/2 * (XA(l) + XB(l) + TW(l) * (XB(l) - XA(l))); + end + XA(1) = 1/2* (XA(1) + XB(1) + TW(1) * (XB(1) - XA(1))) + i*( 1/2*( XA(1) + XB(1) + i*( XA(1) - XB(1)))); + X = XA; + */ + + xBI = pB[1]; + xBR = pB[0]; + xAR = pA[0]; + xAI = pA[1]; + + twR = *pCoeff++; + twI = *pCoeff++; + + t1a = xBR - xAR ; + t1b = xBI + xAI ; + + // real(tw * (xB - xA)) = twR * (xBR - xAR) - twI * (xBI - xAI); + // imag(tw * (xB - xA)) = twI * (xBR - xAR) + twR * (xBI - xAI); + p0 = twR * t1a; + p1 = twI * t1a; + p2 = twR * t1b; + p3 = twI * t1b; + + *pOut++ = 0.5 * (xAR + xBR + p0 + p3 ); //xAR + *pOut++ = 0.5 * (xAI - xBI + p1 - p2 ); //xAI + + pA += 2; + pB -= 2; + k--; + } while (k > 0U); +} + +/* Prepares data for inverse cfft */ +void merge_rfft_f64( + const riscv_rfft_fast_instance_f64 * S, + float64_t * p, + float64_t * pOut) +{ + uint32_t k; /* Loop Counter */ + float64_t twR, twI; /* RFFT Twiddle coefficients */ + const float64_t *pCoeff = S->pTwiddleRFFT; /* Points to RFFT Twiddle factors */ + float64_t *pA = p; /* increasing pointer */ + float64_t *pB = p; /* decreasing pointer */ + float64_t xAR, xAI, xBR, xBI; /* temporary variables */ + float64_t t1a, t1b, r, s, t, u; /* temporary variables */ + + k = (S->Sint).fftLen - 1; + + xAR = pA[0]; + xAI = pA[1]; + + pCoeff += 2 ; + + *pOut++ = 0.5 * ( xAR + xAI ); + *pOut++ = 0.5 * ( xAR - xAI ); + + pB = p + 2*k ; + pA += 2 ; + + while (k > 0U) + { + /* G is half of the frequency complex spectrum */ + //for k = 2:N + // Xk(k) = 1/2 * (G(k) + conj(G(N-k+2)) + Tw(k)*( G(k) - conj(G(N-k+2)))); + xBI = pB[1] ; + xBR = pB[0] ; + xAR = pA[0]; + xAI = pA[1]; + + twR = *pCoeff++; + twI = *pCoeff++; + + t1a = xAR - xBR ; + t1b = xAI + xBI ; + + r = twR * t1a; + s = twI * t1b; + t = twI * t1a; + u = twR * t1b; + + // real(tw * (xA - xB)) = twR * (xAR - xBR) - twI * (xAI - xBI); + // imag(tw * (xA - xB)) = twI * (xAR - xBR) + twR * (xAI - xBI); + *pOut++ = 0.5 * (xAR + xBR - r - s ); //xAR + *pOut++ = 0.5 * (xAI - xBI + t - u ); //xAI + + pA += 2; + pB -= 2; + k--; + } + +} + +/** + @ingroup groupTransforms +*/ + + +/** + @addtogroup RealFFT + @{ +*/ + +/** + @brief Processing function for the Double Precision floating-point real FFT. + @param[in] S points to an riscv_rfft_fast_instance_f64 structure + @param[in] p points to input buffer (Source buffer is modified by this function.) + @param[in] pOut points to output buffer + @param[in] ifftFlag + - value = 0: RFFT + - value = 1: RIFFT + @return none +*/ + +void riscv_rfft_fast_f64( + riscv_rfft_fast_instance_f64 * S, + float64_t * p, + float64_t * pOut, + uint8_t ifftFlag) +{ + riscv_cfft_instance_f64 * Sint = &(S->Sint); + Sint->fftLen = S->fftLenRFFT / 2; + + /* Calculation of Real FFT */ + if (ifftFlag) + { + /* Real FFT compression */ + merge_rfft_f64(S, p, pOut); + + /* Complex radix-4 IFFT process */ + riscv_cfft_f64( Sint, pOut, ifftFlag, 1); + } + else + { + /* Calculation of RFFT of input */ + riscv_cfft_f64( Sint, p, ifftFlag, 1); + + /* Real FFT extraction */ + stage_rfft_f64(S, p, pOut); + } +} + +/** +* @} end of RealFFT group +*/ diff --git a/components/nmsis/dsp/src/TransformFunctions/riscv_rfft_fast_init_f16.c b/components/nmsis/dsp/src/TransformFunctions/riscv_rfft_fast_init_f16.c new file mode 100644 index 00000000..3d828dc6 --- /dev/null +++ b/components/nmsis/dsp/src/TransformFunctions/riscv_rfft_fast_init_f16.c @@ -0,0 +1,358 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_rfft_fast_init_f16.c + * Description: Split Radix Decimation in Frequency CFFT Floating point processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions_f16.h" +#include "riscv_common_tables_f16.h" +#include "riscv_const_structs_f16.h" + +#if defined(RISCV_FLOAT16_SUPPORTED) + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup RealFFT + @{ + */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F16_16) && defined(RISCV_TABLE_BITREVIDX_FLT_16) && defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F16_32)) + +/** + @private + @brief Initialization function for the 32pt floating-point real FFT. + @param[in,out] S points to an riscv_rfft_fast_instance_f16 structure + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_ARGUMENT_ERROR : an error is detected + */ + +static riscv_status riscv_rfft_32_fast_init_f16( riscv_rfft_fast_instance_f16 * S ) { + + riscv_status status; + + if( !S ) return RISCV_MATH_ARGUMENT_ERROR; + + status=riscv_cfft_init_f16(&(S->Sint),16); + if (status != RISCV_MATH_SUCCESS) + { + return(status); + } + + S->fftLenRFFT = 32U; + S->pTwiddleRFFT = (float16_t *) twiddleCoefF16_rfft_32; + + return RISCV_MATH_SUCCESS; +} +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F16_32) && defined(RISCV_TABLE_BITREVIDX_FLT_32) && defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F16_64)) + +/** + @private + @brief Initialization function for the 64pt floating-point real FFT. + @param[in,out] S points to an riscv_rfft_fast_instance_f16 structure + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_ARGUMENT_ERROR : an error is detected + */ + +static riscv_status riscv_rfft_64_fast_init_f16( riscv_rfft_fast_instance_f16 * S ) { + + riscv_status status; + + if( !S ) return RISCV_MATH_ARGUMENT_ERROR; + + status=riscv_cfft_init_f16(&(S->Sint),32); + if (status != RISCV_MATH_SUCCESS) + { + return(status); + } + S->fftLenRFFT = 64U; + + S->pTwiddleRFFT = (float16_t *) twiddleCoefF16_rfft_64; + + return RISCV_MATH_SUCCESS; +} +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F16_64) && defined(RISCV_TABLE_BITREVIDX_FLT_64) && defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F16_128)) + +/** + @private + @brief Initialization function for the 128pt floating-point real FFT. + @param[in,out] S points to an riscv_rfft_fast_instance_f16 structure + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_ARGUMENT_ERROR : an error is detected + */ + +static riscv_status riscv_rfft_128_fast_init_f16( riscv_rfft_fast_instance_f16 * S ) { + + riscv_status status; + + if( !S ) return RISCV_MATH_ARGUMENT_ERROR; + + status=riscv_cfft_init_f16(&(S->Sint),64); + if (status != RISCV_MATH_SUCCESS) + { + return(status); + } + S->fftLenRFFT = 128; + + S->pTwiddleRFFT = (float16_t *) twiddleCoefF16_rfft_128; + + return RISCV_MATH_SUCCESS; +} +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F16_128) && defined(RISCV_TABLE_BITREVIDX_FLT_128) && defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F16_256)) + +/** + @private + @brief Initialization function for the 256pt floating-point real FFT. + @param[in,out] S points to an riscv_rfft_fast_instance_f16 structure + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_ARGUMENT_ERROR : an error is detected +*/ + +static riscv_status riscv_rfft_256_fast_init_f16( riscv_rfft_fast_instance_f16 * S ) { + + riscv_status status; + + if( !S ) return RISCV_MATH_ARGUMENT_ERROR; + + status=riscv_cfft_init_f16(&(S->Sint),128); + if (status != RISCV_MATH_SUCCESS) + { + return(status); + } + S->fftLenRFFT = 256U; + + S->pTwiddleRFFT = (float16_t *) twiddleCoefF16_rfft_256; + + return RISCV_MATH_SUCCESS; +} +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F16_256) && defined(RISCV_TABLE_BITREVIDX_FLT_256) && defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F16_512)) + +/** + @private + @brief Initialization function for the 512pt floating-point real FFT. + @param[in,out] S points to an riscv_rfft_fast_instance_f16 structure + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_ARGUMENT_ERROR : an error is detected + */ + +static riscv_status riscv_rfft_512_fast_init_f16( riscv_rfft_fast_instance_f16 * S ) { + + riscv_status status; + + if( !S ) return RISCV_MATH_ARGUMENT_ERROR; + + status=riscv_cfft_init_f16(&(S->Sint),256); + if (status != RISCV_MATH_SUCCESS) + { + return(status); + } + S->fftLenRFFT = 512U; + + S->pTwiddleRFFT = (float16_t *) twiddleCoefF16_rfft_512; + + return RISCV_MATH_SUCCESS; +} +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F16_512) && defined(RISCV_TABLE_BITREVIDX_FLT_512) && defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F16_1024)) +/** + @private + @brief Initialization function for the 1024pt floating-point real FFT. + @param[in,out] S points to an riscv_rfft_fast_instance_f16 structure + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_ARGUMENT_ERROR : an error is detected + */ + +static riscv_status riscv_rfft_1024_fast_init_f16( riscv_rfft_fast_instance_f16 * S ) { + + riscv_status status; + + if( !S ) return RISCV_MATH_ARGUMENT_ERROR; + + status=riscv_cfft_init_f16(&(S->Sint),512); + if (status != RISCV_MATH_SUCCESS) + { + return(status); + } + S->fftLenRFFT = 1024U; + + S->pTwiddleRFFT = (float16_t *) twiddleCoefF16_rfft_1024; + + return RISCV_MATH_SUCCESS; +} +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F16_1024) && defined(RISCV_TABLE_BITREVIDX_FLT_1024) && defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F16_2048)) +/** + @private + @brief Initialization function for the 2048pt floating-point real FFT. + @param[in,out] S points to an riscv_rfft_fast_instance_f16 structure + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_ARGUMENT_ERROR : an error is detected + */ +static riscv_status riscv_rfft_2048_fast_init_f16( riscv_rfft_fast_instance_f16 * S ) { + + riscv_status status; + + if( !S ) return RISCV_MATH_ARGUMENT_ERROR; + + status=riscv_cfft_init_f16(&(S->Sint),1024); + if (status != RISCV_MATH_SUCCESS) + { + return(status); + } + S->fftLenRFFT = 2048U; + + S->pTwiddleRFFT = (float16_t *) twiddleCoefF16_rfft_2048; + + return RISCV_MATH_SUCCESS; +} +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F16_2048) && defined(RISCV_TABLE_BITREVIDX_FLT_2048) && defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F16_4096)) +/** + @private +* @brief Initialization function for the 4096pt floating-point real FFT. +* @param[in,out] S points to an riscv_rfft_fast_instance_f16 structure + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_ARGUMENT_ERROR : an error is detected + */ + +static riscv_status riscv_rfft_4096_fast_init_f16( riscv_rfft_fast_instance_f16 * S ) { + + riscv_status status; + + if( !S ) return RISCV_MATH_ARGUMENT_ERROR; + + status=riscv_cfft_init_f16(&(S->Sint),2048); + if (status != RISCV_MATH_SUCCESS) + { + return(status); + } + S->fftLenRFFT = 4096U; + + S->pTwiddleRFFT = (float16_t *) twiddleCoefF16_rfft_4096; + + return RISCV_MATH_SUCCESS; +} +#endif + +/** + @brief Initialization function for the floating-point real FFT. + @param[in,out] S points to an riscv_rfft_fast_instance_f16 structure + @param[in] fftLen length of the Real Sequence + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_ARGUMENT_ERROR : fftLen is not a supported length + + @par Description + The parameter fftLen specifies the length of RFFT/CIFFT process. + Supported FFT Lengths are 32, 64, 128, 256, 512, 1024, 2048, 4096. + @par + This Function also initializes Twiddle factor table pointer and Bit reversal table pointer. + */ + +riscv_status riscv_rfft_fast_init_f16( + riscv_rfft_fast_instance_f16 * S, + uint16_t fftLen) +{ + typedef riscv_status(*fft_init_ptr)( riscv_rfft_fast_instance_f16 *); + fft_init_ptr fptr = 0x0; + + switch (fftLen) + { +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F16_2048) && defined(RISCV_TABLE_BITREVIDX_FLT_2048) && defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F16_4096)) + case 4096U: + fptr = riscv_rfft_4096_fast_init_f16; + break; +#endif +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F16_1024) && defined(RISCV_TABLE_BITREVIDX_FLT_1024) && defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F16_2048)) + case 2048U: + fptr = riscv_rfft_2048_fast_init_f16; + break; +#endif +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F16_512) && defined(RISCV_TABLE_BITREVIDX_FLT_512) && defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F16_1024)) + case 1024U: + fptr = riscv_rfft_1024_fast_init_f16; + break; +#endif +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F16_256) && defined(RISCV_TABLE_BITREVIDX_FLT_256) && defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F16_512)) + case 512U: + fptr = riscv_rfft_512_fast_init_f16; + break; +#endif +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F16_128) && defined(RISCV_TABLE_BITREVIDX_FLT_128) && defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F16_256)) + case 256U: + fptr = riscv_rfft_256_fast_init_f16; + break; +#endif +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F16_64) && defined(RISCV_TABLE_BITREVIDX_FLT_64) && defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F16_128)) + case 128U: + fptr = riscv_rfft_128_fast_init_f16; + break; +#endif +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F16_32) && defined(RISCV_TABLE_BITREVIDX_FLT_32) && defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F16_64)) + case 64U: + fptr = riscv_rfft_64_fast_init_f16; + break; +#endif +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F16_16) && defined(RISCV_TABLE_BITREVIDX_FLT_16) && defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F16_32)) + case 32U: + fptr = riscv_rfft_32_fast_init_f16; + break; +#endif + default: + return RISCV_MATH_ARGUMENT_ERROR; + } + + if( ! fptr ) return RISCV_MATH_ARGUMENT_ERROR; + return fptr( S ); + +} + +/** + @} end of RealFFT group + */ + +#endif /* #if defined(RISCV_FLOAT16_SUPPORTED) */ diff --git a/components/nmsis/dsp/src/TransformFunctions/riscv_rfft_fast_init_f32.c b/components/nmsis/dsp/src/TransformFunctions/riscv_rfft_fast_init_f32.c new file mode 100644 index 00000000..af0febd5 --- /dev/null +++ b/components/nmsis/dsp/src/TransformFunctions/riscv_rfft_fast_init_f32.c @@ -0,0 +1,353 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_rfft_fast_init_f32.c + * Description: Split Radix Decimation in Frequency CFFT Floating point processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" +#include "riscv_common_tables.h" + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup RealFFT + @{ + */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F32_16) && defined(RISCV_TABLE_BITREVIDX_FLT_16) && defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F32_32)) + +/** + @private + @brief Initialization function for the 32pt floating-point real FFT. + @param[in,out] S points to an riscv_rfft_fast_instance_f32 structure + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_ARGUMENT_ERROR : an error is detected + */ + +static riscv_status riscv_rfft_32_fast_init_f32( riscv_rfft_fast_instance_f32 * S ) { + + riscv_status status; + + if( !S ) return RISCV_MATH_ARGUMENT_ERROR; + + status=riscv_cfft_init_f32(&(S->Sint),16); + if (status != RISCV_MATH_SUCCESS) + { + return(status); + } + + S->fftLenRFFT = 32U; + S->pTwiddleRFFT = (float32_t *) twiddleCoef_rfft_32; + + return RISCV_MATH_SUCCESS; +} +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F32_32) && defined(RISCV_TABLE_BITREVIDX_FLT_32) && defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F32_64)) + +/** + @private + @brief Initialization function for the 64pt floating-point real FFT. + @param[in,out] S points to an riscv_rfft_fast_instance_f32 structure + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_ARGUMENT_ERROR : an error is detected + */ + +static riscv_status riscv_rfft_64_fast_init_f32( riscv_rfft_fast_instance_f32 * S ) { + + riscv_status status; + + if( !S ) return RISCV_MATH_ARGUMENT_ERROR; + + status=riscv_cfft_init_f32(&(S->Sint),32); + if (status != RISCV_MATH_SUCCESS) + { + return(status); + } + S->fftLenRFFT = 64U; + + S->pTwiddleRFFT = (float32_t *) twiddleCoef_rfft_64; + + return RISCV_MATH_SUCCESS; +} +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F32_64) && defined(RISCV_TABLE_BITREVIDX_FLT_64) && defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F32_128)) + +/** + @private + @brief Initialization function for the 128pt floating-point real FFT. + @param[in,out] S points to an riscv_rfft_fast_instance_f32 structure + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_ARGUMENT_ERROR : an error is detected + */ + +static riscv_status riscv_rfft_128_fast_init_f32( riscv_rfft_fast_instance_f32 * S ) { + + riscv_status status; + + if( !S ) return RISCV_MATH_ARGUMENT_ERROR; + + status=riscv_cfft_init_f32(&(S->Sint),64); + if (status != RISCV_MATH_SUCCESS) + { + return(status); + } + S->fftLenRFFT = 128; + + S->pTwiddleRFFT = (float32_t *) twiddleCoef_rfft_128; + + return RISCV_MATH_SUCCESS; +} +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F32_128) && defined(RISCV_TABLE_BITREVIDX_FLT_128) && defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F32_256)) + +/** + @private + @brief Initialization function for the 256pt floating-point real FFT. + @param[in,out] S points to an riscv_rfft_fast_instance_f32 structure + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_ARGUMENT_ERROR : an error is detected +*/ + +static riscv_status riscv_rfft_256_fast_init_f32( riscv_rfft_fast_instance_f32 * S ) { + + riscv_status status; + + if( !S ) return RISCV_MATH_ARGUMENT_ERROR; + + status=riscv_cfft_init_f32(&(S->Sint),128); + if (status != RISCV_MATH_SUCCESS) + { + return(status); + } + S->fftLenRFFT = 256U; + + S->pTwiddleRFFT = (float32_t *) twiddleCoef_rfft_256; + + return RISCV_MATH_SUCCESS; +} +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F32_256) && defined(RISCV_TABLE_BITREVIDX_FLT_256) && defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F32_512)) + +/** + @private + @brief Initialization function for the 512pt floating-point real FFT. + @param[in,out] S points to an riscv_rfft_fast_instance_f32 structure + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_ARGUMENT_ERROR : an error is detected + */ + +static riscv_status riscv_rfft_512_fast_init_f32( riscv_rfft_fast_instance_f32 * S ) { + + riscv_status status; + + if( !S ) return RISCV_MATH_ARGUMENT_ERROR; + + status=riscv_cfft_init_f32(&(S->Sint),256); + if (status != RISCV_MATH_SUCCESS) + { + return(status); + } + S->fftLenRFFT = 512U; + + S->pTwiddleRFFT = (float32_t *) twiddleCoef_rfft_512; + + return RISCV_MATH_SUCCESS; +} +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F32_512) && defined(RISCV_TABLE_BITREVIDX_FLT_512) && defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F32_1024)) +/** + @private + @brief Initialization function for the 1024pt floating-point real FFT. + @param[in,out] S points to an riscv_rfft_fast_instance_f32 structure + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_ARGUMENT_ERROR : an error is detected + */ + +static riscv_status riscv_rfft_1024_fast_init_f32( riscv_rfft_fast_instance_f32 * S ) { + + riscv_status status; + + if( !S ) return RISCV_MATH_ARGUMENT_ERROR; + + status=riscv_cfft_init_f32(&(S->Sint),512); + if (status != RISCV_MATH_SUCCESS) + { + return(status); + } + S->fftLenRFFT = 1024U; + + S->pTwiddleRFFT = (float32_t *) twiddleCoef_rfft_1024; + + return RISCV_MATH_SUCCESS; +} +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F32_1024) && defined(RISCV_TABLE_BITREVIDX_FLT_1024) && defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F32_2048)) +/** + @private + @brief Initialization function for the 2048pt floating-point real FFT. + @param[in,out] S points to an riscv_rfft_fast_instance_f32 structure + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_ARGUMENT_ERROR : an error is detected + */ +static riscv_status riscv_rfft_2048_fast_init_f32( riscv_rfft_fast_instance_f32 * S ) { + + riscv_status status; + + if( !S ) return RISCV_MATH_ARGUMENT_ERROR; + + status=riscv_cfft_init_f32(&(S->Sint),1024); + if (status != RISCV_MATH_SUCCESS) + { + return(status); + } + S->fftLenRFFT = 2048U; + + S->pTwiddleRFFT = (float32_t *) twiddleCoef_rfft_2048; + + return RISCV_MATH_SUCCESS; +} +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F32_2048) && defined(RISCV_TABLE_BITREVIDX_FLT_2048) && defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F32_4096)) +/** + @private +* @brief Initialization function for the 4096pt floating-point real FFT. +* @param[in,out] S points to an riscv_rfft_fast_instance_f32 structure + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_ARGUMENT_ERROR : an error is detected + */ + +static riscv_status riscv_rfft_4096_fast_init_f32( riscv_rfft_fast_instance_f32 * S ) { + + riscv_status status; + + if( !S ) return RISCV_MATH_ARGUMENT_ERROR; + + status=riscv_cfft_init_f32(&(S->Sint),2048); + if (status != RISCV_MATH_SUCCESS) + { + return(status); + } + S->fftLenRFFT = 4096U; + + S->pTwiddleRFFT = (float32_t *) twiddleCoef_rfft_4096; + + return RISCV_MATH_SUCCESS; +} +#endif + +/** + @brief Initialization function for the floating-point real FFT. + @param[in,out] S points to an riscv_rfft_fast_instance_f32 structure + @param[in] fftLen length of the Real Sequence + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_ARGUMENT_ERROR : fftLen is not a supported length + + @par Description + The parameter fftLen specifies the length of RFFT/CIFFT process. + Supported FFT Lengths are 32, 64, 128, 256, 512, 1024, 2048, 4096. + @par + This Function also initializes Twiddle factor table pointer and Bit reversal table pointer. + */ + +riscv_status riscv_rfft_fast_init_f32( + riscv_rfft_fast_instance_f32 * S, + uint16_t fftLen) +{ + typedef riscv_status(*fft_init_ptr)( riscv_rfft_fast_instance_f32 *); + fft_init_ptr fptr = 0x0; + + switch (fftLen) + { +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F32_2048) && defined(RISCV_TABLE_BITREVIDX_FLT_2048) && defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F32_4096)) + case 4096U: + fptr = riscv_rfft_4096_fast_init_f32; + break; +#endif +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F32_1024) && defined(RISCV_TABLE_BITREVIDX_FLT_1024) && defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F32_2048)) + case 2048U: + fptr = riscv_rfft_2048_fast_init_f32; + break; +#endif +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F32_512) && defined(RISCV_TABLE_BITREVIDX_FLT_512) && defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F32_1024)) + case 1024U: + fptr = riscv_rfft_1024_fast_init_f32; + break; +#endif +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F32_256) && defined(RISCV_TABLE_BITREVIDX_FLT_256) && defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F32_512)) + case 512U: + fptr = riscv_rfft_512_fast_init_f32; + break; +#endif +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F32_128) && defined(RISCV_TABLE_BITREVIDX_FLT_128) && defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F32_256)) + case 256U: + fptr = riscv_rfft_256_fast_init_f32; + break; +#endif +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F32_64) && defined(RISCV_TABLE_BITREVIDX_FLT_64) && defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F32_128)) + case 128U: + fptr = riscv_rfft_128_fast_init_f32; + break; +#endif +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F32_32) && defined(RISCV_TABLE_BITREVIDX_FLT_32) && defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F32_64)) + case 64U: + fptr = riscv_rfft_64_fast_init_f32; + break; +#endif +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F32_16) && defined(RISCV_TABLE_BITREVIDX_FLT_16) && defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F32_32)) + case 32U: + fptr = riscv_rfft_32_fast_init_f32; + break; +#endif + default: + return RISCV_MATH_ARGUMENT_ERROR; + } + + if( ! fptr ) return RISCV_MATH_ARGUMENT_ERROR; + return fptr( S ); + +} + +/** + @} end of RealFFT group + */ diff --git a/components/nmsis/dsp/src/TransformFunctions/riscv_rfft_fast_init_f64.c b/components/nmsis/dsp/src/TransformFunctions/riscv_rfft_fast_init_f64.c new file mode 100644 index 00000000..474ae17a --- /dev/null +++ b/components/nmsis/dsp/src/TransformFunctions/riscv_rfft_fast_init_f64.c @@ -0,0 +1,345 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_rfft_fast_init_f64.c + * Description: Split Radix Decimation in Frequency CFFT Double Precision Floating point processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" +#include "riscv_common_tables.h" + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup RealFFT + @{ + */ + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F64_16) && defined(RISCV_TABLE_BITREVIDX_FLT64_16) && defined(RISCV_TABLE_TWIDDLECOEF_F64_16) && defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F64_32)) + +/** + @brief Initialization function for the 32pt double precision floating-point real FFT. + @param[in,out] S points to an riscv_rfft_fast_instance_f64 structure + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_ARGUMENT_ERROR : an error is detected + */ + +static riscv_status riscv_rfft_32_fast_init_f64( riscv_rfft_fast_instance_f64 * S ) { + + riscv_cfft_instance_f64 * Sint; + + if( !S ) return RISCV_MATH_ARGUMENT_ERROR; + + Sint = &(S->Sint); + Sint->fftLen = 16U; + S->fftLenRFFT = 32U; + + Sint->bitRevLength = RISCVBITREVINDEXTABLEF64_16_TABLE_LENGTH; + Sint->pBitRevTable = (uint16_t *)riscvBitRevIndexTableF64_16; + Sint->pTwiddle = (float64_t *) twiddleCoefF64_16; + S->pTwiddleRFFT = (float64_t *) twiddleCoefF64_rfft_32; + + return RISCV_MATH_SUCCESS; +} +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F64_32) && defined(RISCV_TABLE_BITREVIDX_FLT64_32) && defined(RISCV_TABLE_TWIDDLECOEF_F64_32) && defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F64_64)) + +/** + @brief Initialization function for the 64pt Double Precision floating-point real FFT. + @param[in,out] S points to an riscv_rfft_fast_instance_f64 structure + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_ARGUMENT_ERROR : an error is detected + */ + +static riscv_status riscv_rfft_64_fast_init_f64( riscv_rfft_fast_instance_f64 * S ) { + + riscv_cfft_instance_f64 * Sint; + + if( !S ) return RISCV_MATH_ARGUMENT_ERROR; + + Sint = &(S->Sint); + Sint->fftLen = 32U; + S->fftLenRFFT = 64U; + + Sint->bitRevLength = RISCVBITREVINDEXTABLEF64_32_TABLE_LENGTH; + Sint->pBitRevTable = (uint16_t *)riscvBitRevIndexTableF64_32; + Sint->pTwiddle = (float64_t *) twiddleCoefF64_32; + S->pTwiddleRFFT = (float64_t *) twiddleCoefF64_rfft_64; + + return RISCV_MATH_SUCCESS; +} +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F64_64) && defined(RISCV_TABLE_BITREVIDX_FLT64_64) && defined(RISCV_TABLE_TWIDDLECOEF_F64_64) && defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F64_128)) + +/** + @brief Initialization function for the 128pt Double Precision floating-point real FFT. + @param[in,out] S points to an riscv_rfft_fast_instance_f64 structure + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_ARGUMENT_ERROR : an error is detected + */ + +static riscv_status riscv_rfft_128_fast_init_f64( riscv_rfft_fast_instance_f64 * S ) { + + riscv_cfft_instance_f64 * Sint; + + if( !S ) return RISCV_MATH_ARGUMENT_ERROR; + + Sint = &(S->Sint); + Sint->fftLen = 64U; + S->fftLenRFFT = 128U; + + Sint->bitRevLength = RISCVBITREVINDEXTABLEF64_64_TABLE_LENGTH; + Sint->pBitRevTable = (uint16_t *)riscvBitRevIndexTableF64_64; + Sint->pTwiddle = (float64_t *) twiddleCoefF64_64; + S->pTwiddleRFFT = (float64_t *) twiddleCoefF64_rfft_128; + + return RISCV_MATH_SUCCESS; +} +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F64_128) && defined(RISCV_TABLE_BITREVIDX_FLT64_128) && defined(RISCV_TABLE_TWIDDLECOEF_F64_128) && defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F64_256)) + +/** + @brief Initialization function for the 256pt Double Precision floating-point real FFT. + @param[in,out] S points to an riscv_rfft_fast_instance_f64 structure + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_ARGUMENT_ERROR : an error is detected +*/ + +static riscv_status riscv_rfft_256_fast_init_f64( riscv_rfft_fast_instance_f64 * S ) { + + riscv_cfft_instance_f64 * Sint; + + if( !S ) return RISCV_MATH_ARGUMENT_ERROR; + + Sint = &(S->Sint); + Sint->fftLen = 128U; + S->fftLenRFFT = 256U; + + Sint->bitRevLength = RISCVBITREVINDEXTABLEF64_128_TABLE_LENGTH; + Sint->pBitRevTable = (uint16_t *)riscvBitRevIndexTableF64_128; + Sint->pTwiddle = (float64_t *) twiddleCoefF64_128; + S->pTwiddleRFFT = (float64_t *) twiddleCoefF64_rfft_256; + + return RISCV_MATH_SUCCESS; +} +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F64_256) && defined(RISCV_TABLE_BITREVIDX_FLT64_256) && defined(RISCV_TABLE_TWIDDLECOEF_F64_256) && defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F64_512)) + +/** + @brief Initialization function for the 512pt Double Precision floating-point real FFT. + @param[in,out] S points to an riscv_rfft_fast_instance_f64 structure + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_ARGUMENT_ERROR : an error is detected + */ + +static riscv_status riscv_rfft_512_fast_init_f64( riscv_rfft_fast_instance_f64 * S ) { + + riscv_cfft_instance_f64 * Sint; + + if( !S ) return RISCV_MATH_ARGUMENT_ERROR; + + Sint = &(S->Sint); + Sint->fftLen = 256U; + S->fftLenRFFT = 512U; + + Sint->bitRevLength = RISCVBITREVINDEXTABLEF64_256_TABLE_LENGTH; + Sint->pBitRevTable = (uint16_t *)riscvBitRevIndexTableF64_256; + Sint->pTwiddle = (float64_t *) twiddleCoefF64_256; + S->pTwiddleRFFT = (float64_t *) twiddleCoefF64_rfft_512; + + return RISCV_MATH_SUCCESS; +} +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F64_512) && defined(RISCV_TABLE_BITREVIDX_FLT64_512) && defined(RISCV_TABLE_TWIDDLECOEF_F64_512) && defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F64_1024)) +/** + @brief Initialization function for the 1024pt Double Precision floating-point real FFT. + @param[in,out] S points to an riscv_rfft_fast_instance_f64 structure + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_ARGUMENT_ERROR : an error is detected + */ + +static riscv_status riscv_rfft_1024_fast_init_f64( riscv_rfft_fast_instance_f64 * S ) { + + riscv_cfft_instance_f64 * Sint; + + if( !S ) return RISCV_MATH_ARGUMENT_ERROR; + + Sint = &(S->Sint); + Sint->fftLen = 512U; + S->fftLenRFFT = 1024U; + + Sint->bitRevLength = RISCVBITREVINDEXTABLEF64_512_TABLE_LENGTH; + Sint->pBitRevTable = (uint16_t *)riscvBitRevIndexTableF64_512; + Sint->pTwiddle = (float64_t *) twiddleCoefF64_512; + S->pTwiddleRFFT = (float64_t *) twiddleCoefF64_rfft_1024; + + return RISCV_MATH_SUCCESS; +} +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F64_1024) && defined(RISCV_TABLE_BITREVIDX_FLT64_1024) && defined(RISCV_TABLE_TWIDDLECOEF_F64_1024) && defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F64_2048)) +/** + @brief Initialization function for the 2048pt Double Precision floating-point real FFT. + @param[in,out] S points to an riscv_rfft_fast_instance_f64 structure + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_ARGUMENT_ERROR : an error is detected + */ +static riscv_status riscv_rfft_2048_fast_init_f64( riscv_rfft_fast_instance_f64 * S ) { + + riscv_cfft_instance_f64 * Sint; + + if( !S ) return RISCV_MATH_ARGUMENT_ERROR; + + Sint = &(S->Sint); + Sint->fftLen = 1024U; + S->fftLenRFFT = 2048U; + + Sint->bitRevLength = RISCVBITREVINDEXTABLEF64_1024_TABLE_LENGTH; + Sint->pBitRevTable = (uint16_t *)riscvBitRevIndexTableF64_1024; + Sint->pTwiddle = (float64_t *) twiddleCoefF64_1024; + S->pTwiddleRFFT = (float64_t *) twiddleCoefF64_rfft_2048; + + return RISCV_MATH_SUCCESS; +} +#endif + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F64_2048) && defined(RISCV_TABLE_BITREVIDX_FLT64_2048) && defined(RISCV_TABLE_TWIDDLECOEF_F64_2048) && defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F64_4096)) +/** +* @brief Initialization function for the 4096pt Double Precision floating-point real FFT. +* @param[in,out] S points to an riscv_rfft_fast_instance_f64 structure + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_ARGUMENT_ERROR : an error is detected + */ + +static riscv_status riscv_rfft_4096_fast_init_f64( riscv_rfft_fast_instance_f64 * S ) { + + riscv_cfft_instance_f64 * Sint; + + if( !S ) return RISCV_MATH_ARGUMENT_ERROR; + + Sint = &(S->Sint); + Sint->fftLen = 2048U; + S->fftLenRFFT = 4096U; + + Sint->bitRevLength = RISCVBITREVINDEXTABLEF64_2048_TABLE_LENGTH; + Sint->pBitRevTable = (uint16_t *)riscvBitRevIndexTableF64_2048; + Sint->pTwiddle = (float64_t *) twiddleCoefF64_2048; + S->pTwiddleRFFT = (float64_t *) twiddleCoefF64_rfft_4096; + + return RISCV_MATH_SUCCESS; +} +#endif + +/** + @brief Initialization function for the Double Precision floating-point real FFT. + @param[in,out] S points to an riscv_rfft_fast_instance_f64 structure + @param[in] fftLen length of the Real Sequence + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_ARGUMENT_ERROR : fftLen is not a supported length + + @par Description + The parameter fftLen specifies the length of RFFT/CIFFT process. + Supported FFT Lengths are 32, 64, 128, 256, 512, 1024, 2048, 4096. + @par + This Function also initializes Twiddle factor table pointer and Bit reversal table pointer. + */ + +riscv_status riscv_rfft_fast_init_f64( + riscv_rfft_fast_instance_f64 * S, + uint16_t fftLen) +{ + typedef riscv_status(*fft_init_ptr)( riscv_rfft_fast_instance_f64 *); + fft_init_ptr fptr = 0x0; + + switch (fftLen) + { +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F64_2048) && defined(RISCV_TABLE_BITREVIDX_FLT64_2048) && defined(RISCV_TABLE_TWIDDLECOEF_F64_2048) && defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F64_4096)) + case 4096U: + fptr = riscv_rfft_4096_fast_init_f64; + break; +#endif +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F64_1024) && defined(RISCV_TABLE_BITREVIDX_FLT64_1024) && defined(RISCV_TABLE_TWIDDLECOEF_F64_1024) && defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F64_2048)) + case 2048U: + fptr = riscv_rfft_2048_fast_init_f64; + break; +#endif +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F64_512) && defined(RISCV_TABLE_BITREVIDX_FLT64_512) && defined(RISCV_TABLE_TWIDDLECOEF_F64_512) && defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F64_1024)) + case 1024U: + fptr = riscv_rfft_1024_fast_init_f64; + break; +#endif +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F64_256) && defined(RISCV_TABLE_BITREVIDX_FLT64_256) && defined(RISCV_TABLE_TWIDDLECOEF_F64_256) && defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F64_512)) + case 512U: + fptr = riscv_rfft_512_fast_init_f64; + break; +#endif +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F64_128) && defined(RISCV_TABLE_BITREVIDX_FLT64_128) && defined(RISCV_TABLE_TWIDDLECOEF_F64_128) && defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F64_256)) + case 256U: + fptr = riscv_rfft_256_fast_init_f64; + break; +#endif +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F64_64) && defined(RISCV_TABLE_BITREVIDX_FLT64_64) && defined(RISCV_TABLE_TWIDDLECOEF_F64_64) && defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F64_128)) + case 128U: + fptr = riscv_rfft_128_fast_init_f64; + break; +#endif +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F64_32) && defined(RISCV_TABLE_BITREVIDX_FLT64_32) && defined(RISCV_TABLE_TWIDDLECOEF_F64_32) && defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F64_64)) + case 64U: + fptr = riscv_rfft_64_fast_init_f64; + break; +#endif +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_F64_16) && defined(RISCV_TABLE_BITREVIDX_FLT64_16) && defined(RISCV_TABLE_TWIDDLECOEF_F64_16) && defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F64_32)) + case 32U: + fptr = riscv_rfft_32_fast_init_f64; + break; +#endif + default: + return RISCV_MATH_ARGUMENT_ERROR; + } + + if( ! fptr ) return RISCV_MATH_ARGUMENT_ERROR; + return fptr( S ); + +} + +/** + @} end of RealFFT group + */ diff --git a/components/nmsis/dsp/src/TransformFunctions/riscv_rfft_init_f32.c b/components/nmsis/dsp/src/TransformFunctions/riscv_rfft_init_f32.c new file mode 100644 index 00000000..c4105c95 --- /dev/null +++ b/components/nmsis/dsp/src/TransformFunctions/riscv_rfft_init_f32.c @@ -0,0 +1,148 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_rfft_init_f32.c + * Description: RFFT & RIFFT Floating point initialisation function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" +#include "riscv_common_tables.h" + + +/** + @addtogroup RealFFT + @{ + */ + +/** + @brief Initialization function for the floating-point RFFT/RIFFT. + @deprecated Do not use this function. It has been superceded by \ref riscv_rfft_fast_init_f32 and will be removed in the future. + @param[in,out] S points to an instance of the floating-point RFFT/RIFFT structure + @param[in,out] S_CFFT points to an instance of the floating-point CFFT/CIFFT structure + @param[in] fftLenReal length of the FFT. + @param[in] ifftFlagR flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_ARGUMENT_ERROR : fftLenReal is not a supported length + + @par Description + The parameter fftLenRealspecifies length of RFFT/RIFFT Process. + Supported FFT Lengths are 128, 512, 2048. + @par + The parameter ifftFlagR controls whether a forward or inverse transform is computed. + Set(=1) ifftFlagR to calculate RIFFT, otherwise RFFT is calculated. + @par + The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. + Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. + @par + This function also initializes Twiddle factor table. + */ + +riscv_status riscv_rfft_init_f32( + riscv_rfft_instance_f32 * S, + riscv_cfft_radix4_instance_f32 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag) +{ + /* Initialise the default riscv status */ + riscv_status status = RISCV_MATH_ARGUMENT_ERROR; + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_FFT_ALLOW_TABLES) + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_REALCOEF_F32) + + /* Initialise the default riscv status */ + status = RISCV_MATH_SUCCESS; + + /* Initialize the Real FFT length */ + S->fftLenReal = (uint16_t) fftLenReal; + + /* Initialize the Complex FFT length */ + S->fftLenBy2 = (uint16_t) fftLenReal / 2U; + + /* Initialize the Twiddle coefficientA pointer */ + S->pTwiddleAReal = (float32_t *) realCoefA; + + /* Initialize the Twiddle coefficientB pointer */ + S->pTwiddleBReal = (float32_t *) realCoefB; + + /* Initialize the Flag for selection of RFFT or RIFFT */ + S->ifftFlagR = (uint8_t) ifftFlagR; + + /* Initialize the Flag for calculation Bit reversal or not */ + S->bitReverseFlagR = (uint8_t) bitReverseFlag; + + /* Initializations of structure parameters depending on the FFT length */ + switch (S->fftLenReal) + { + /* Init table modifier value */ + case 8192U: + S->twidCoefRModifier = 1U; + break; + case 2048U: + S->twidCoefRModifier = 4U; + break; + case 512U: + S->twidCoefRModifier = 16U; + break; + case 128U: + S->twidCoefRModifier = 64U; + break; + default: + /* Reporting argument error if rfftSize is not valid value */ + status = RISCV_MATH_ARGUMENT_ERROR; + break; + } + + /* Init Complex FFT Instance */ + S->pCfft = S_CFFT; + + if (S->ifftFlagR) + { + /* Initializes the CIFFT Module for fftLenreal/2 length */ + riscv_cfft_radix4_init_f32(S->pCfft, S->fftLenBy2, 1U, 0U); + } + else + { + /* Initializes the CFFT Module for fftLenreal/2 length */ + riscv_cfft_radix4_init_f32(S->pCfft, S->fftLenBy2, 0U, 0U); + } + +#endif +#endif + /* return the status of RFFT Init function */ + return (status); + +} + +/** + @} end of RealFFT group + */ diff --git a/components/nmsis/dsp/src/TransformFunctions/riscv_rfft_init_q15.c b/components/nmsis/dsp/src/TransformFunctions/riscv_rfft_init_q15.c new file mode 100644 index 00000000..3752b879 --- /dev/null +++ b/components/nmsis/dsp/src/TransformFunctions/riscv_rfft_init_q15.c @@ -0,0 +1,177 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_rfft_init_q15.c + * Description: RFFT & RIFFT Q15 initialisation function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" +#include "riscv_common_tables.h" +#include "riscv_const_structs.h" + +/** + @addtogroup RealFFT + @{ + */ + +/** + @brief Initialization function for the Q15 RFFT/RIFFT. + @param[in,out] S points to an instance of the Q15 RFFT/RIFFT structure + @param[in] fftLenReal length of the FFT + @param[in] ifftFlagR flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_ARGUMENT_ERROR : fftLenReal is not a supported length + + @par Details + The parameter fftLenReal specifies length of RFFT/RIFFT Process. + Supported FFT Lengths are 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192. + @par + The parameter ifftFlagR controls whether a forward or inverse transform is computed. + Set(=1) ifftFlagR to calculate RIFFT, otherwise RFFT is calculated. + @par + The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. + Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. + @par + This function also initializes Twiddle factor table. + */ + +riscv_status riscv_rfft_init_q15( + riscv_rfft_instance_q15 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag) +{ + /* Initialise the default riscv status */ + riscv_status status = RISCV_MATH_ARGUMENT_ERROR; + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_FFT_ALLOW_TABLES) + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_REALCOEF_Q15) + + /* Initialise the default riscv status */ + status = RISCV_MATH_SUCCESS; + + /* Initialize the Real FFT length */ + S->fftLenReal = (uint16_t) fftLenReal; + + /* Initialize the Twiddle coefficientA pointer */ + S->pTwiddleAReal = (q15_t *) realCoefAQ15; + + /* Initialize the Twiddle coefficientB pointer */ + S->pTwiddleBReal = (q15_t *) realCoefBQ15; + + /* Initialize the Flag for selection of RFFT or RIFFT */ + S->ifftFlagR = (uint8_t) ifftFlagR; + + /* Initialize the Flag for calculation Bit reversal or not */ + S->bitReverseFlagR = (uint8_t) bitReverseFlag; + + /* Initialization of coef modifier depending on the FFT length */ + switch (S->fftLenReal) + { +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_Q15_4096) && defined(RISCV_TABLE_BITREVIDX_FXT_4096)) + case 8192U: + S->twidCoefRModifier = 1U; + + S->pCfft = &riscv_cfft_sR_q15_len4096; + break; +#endif +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_Q15_2048) && defined(RISCV_TABLE_BITREVIDX_FXT_2048)) + case 4096U: + S->twidCoefRModifier = 2U; + + S->pCfft = &riscv_cfft_sR_q15_len2048; + break; +#endif +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_Q15_1024) && defined(RISCV_TABLE_BITREVIDX_FXT_1024)) + case 2048U: + S->twidCoefRModifier = 4U; + + S->pCfft = &riscv_cfft_sR_q15_len1024; + break; +#endif +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_Q15_512) && defined(RISCV_TABLE_BITREVIDX_FXT_512)) + case 1024U: + S->twidCoefRModifier = 8U; + + S->pCfft = &riscv_cfft_sR_q15_len512; + break; +#endif +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_Q15_256) && defined(RISCV_TABLE_BITREVIDX_FXT_256)) + case 512U: + S->twidCoefRModifier = 16U; + + S->pCfft = &riscv_cfft_sR_q15_len256; + break; +#endif +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_Q15_128) && defined(RISCV_TABLE_BITREVIDX_FXT_128)) + case 256U: + S->twidCoefRModifier = 32U; + + S->pCfft = &riscv_cfft_sR_q15_len128; + break; +#endif +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_Q15_64) && defined(RISCV_TABLE_BITREVIDX_FXT_64)) + case 128U: + S->twidCoefRModifier = 64U; + + S->pCfft = &riscv_cfft_sR_q15_len64; + break; +#endif +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_Q15_32) && defined(RISCV_TABLE_BITREVIDX_FXT_32)) + case 64U: + S->twidCoefRModifier = 128U; + + S->pCfft = &riscv_cfft_sR_q15_len32; + break; +#endif +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_Q15_16) && defined(RISCV_TABLE_BITREVIDX_FXT_16)) + case 32U: + S->twidCoefRModifier = 256U; + + S->pCfft = &riscv_cfft_sR_q15_len16; + break; +#endif + default: + /* Reporting argument error if rfftSize is not valid value */ + status = RISCV_MATH_ARGUMENT_ERROR; + break; + } + +#endif +#endif + /* return the status of RFFT Init function */ + return (status); +} + +/** + @} end of RealFFT group + */ diff --git a/components/nmsis/dsp/src/TransformFunctions/riscv_rfft_init_q31.c b/components/nmsis/dsp/src/TransformFunctions/riscv_rfft_init_q31.c new file mode 100644 index 00000000..b0b10481 --- /dev/null +++ b/components/nmsis/dsp/src/TransformFunctions/riscv_rfft_init_q31.c @@ -0,0 +1,175 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_rfft_init_q31.c + * Description: RFFT & RIFFT Q31 initialisation function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" +#include "riscv_common_tables.h" +#include "riscv_const_structs.h" + + + +/** + @addtogroup RealFFT + @{ + */ + +/** + @brief Initialization function for the Q31 RFFT/RIFFT. + @param[in,out] S points to an instance of the Q31 RFFT/RIFFT structure + @param[in] fftLenReal length of the FFT + @param[in] ifftFlagR flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return execution status + - \ref RISCV_MATH_SUCCESS : Operation successful + - \ref RISCV_MATH_ARGUMENT_ERROR : fftLenReal is not a supported length + + @par Details + The parameter fftLenReal specifies length of RFFT/RIFFT Process. + Supported FFT Lengths are 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192. + @par + The parameter ifftFlagR controls whether a forward or inverse transform is computed. + Set(=1) ifftFlagR to calculate RIFFT, otherwise RFFT is calculated. + @par + The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. + Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. + @par + This function also initializes Twiddle factor table. +*/ + +riscv_status riscv_rfft_init_q31( + riscv_rfft_instance_q31 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag) +{ + /* Initialise the default riscv status */ + riscv_status status = RISCV_MATH_ARGUMENT_ERROR; + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_FFT_ALLOW_TABLES) + +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_REALCOEF_Q31) + + /* Initialise the default riscv status */ + status = RISCV_MATH_SUCCESS; + + /* Initialize the Real FFT length */ + S->fftLenReal = (uint16_t) fftLenReal; + + /* Initialize the Twiddle coefficientA pointer */ + S->pTwiddleAReal = (q31_t *) realCoefAQ31; + + /* Initialize the Twiddle coefficientB pointer */ + S->pTwiddleBReal = (q31_t *) realCoefBQ31; + + /* Initialize the Flag for selection of RFFT or RIFFT */ + S->ifftFlagR = (uint8_t) ifftFlagR; + + /* Initialize the Flag for calculation Bit reversal or not */ + S->bitReverseFlagR = (uint8_t) bitReverseFlag; + + /* Initialization of coef modifier depending on the FFT length */ + switch (S->fftLenReal) + { +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_Q31_4096) && defined(RISCV_TABLE_BITREVIDX_FXT_4096)) + case 8192U: + + + S->twidCoefRModifier = 1U; + + S->pCfft = &riscv_cfft_sR_q31_len4096; + break; +#endif +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_Q31_2048) && defined(RISCV_TABLE_BITREVIDX_FXT_2048)) + case 4096U: + S->twidCoefRModifier = 2U; + + S->pCfft = &riscv_cfft_sR_q31_len2048; + break; +#endif +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_Q31_1024) && defined(RISCV_TABLE_BITREVIDX_FXT_1024)) + case 2048U: + S->twidCoefRModifier = 4U; + + S->pCfft = &riscv_cfft_sR_q31_len1024; + break; +#endif +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_Q31_512) && defined(RISCV_TABLE_BITREVIDX_FXT_512)) + case 1024U: + S->twidCoefRModifier = 8U; + S->pCfft = &riscv_cfft_sR_q31_len512; + break; +#endif +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_Q31_256) && defined(RISCV_TABLE_BITREVIDX_FXT_256)) + case 512U: + S->twidCoefRModifier = 16U; + S->pCfft = &riscv_cfft_sR_q31_len256; + break; +#endif +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_Q31_128) && defined(RISCV_TABLE_BITREVIDX_FXT_128)) + case 256U: + S->twidCoefRModifier = 32U; + S->pCfft = &riscv_cfft_sR_q31_len128; + break; +#endif +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_Q31_64) && defined(RISCV_TABLE_BITREVIDX_FXT_64)) + case 128U: + S->twidCoefRModifier = 64U; + S->pCfft = &riscv_cfft_sR_q31_len64; + break; +#endif +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_Q31_32) && defined(RISCV_TABLE_BITREVIDX_FXT_32)) + case 64U: + S->twidCoefRModifier = 128U; + S->pCfft = &riscv_cfft_sR_q31_len32; + break; +#endif +#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || (defined(RISCV_TABLE_TWIDDLECOEF_Q31_16) && defined(RISCV_TABLE_BITREVIDX_FXT_16)) + case 32U: + S->twidCoefRModifier = 256U; + S->pCfft = &riscv_cfft_sR_q31_len16; + break; +#endif + default: + /* Reporting argument error if rfftSize is not valid value */ + status = RISCV_MATH_ARGUMENT_ERROR; + break; + } + +#endif +#endif + /* return the status of RFFT Init function */ + return (status); +} + +/** + @} end of RealFFT group + */ diff --git a/components/nmsis/dsp/src/TransformFunctions/riscv_rfft_q15.c b/components/nmsis/dsp/src/TransformFunctions/riscv_rfft_q15.c new file mode 100644 index 00000000..e7e76d5a --- /dev/null +++ b/components/nmsis/dsp/src/TransformFunctions/riscv_rfft_q15.c @@ -0,0 +1,364 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_rfft_q15.c + * Description: RFFT & RIFFT Q15 process function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" + +/* ---------------------------------------------------------------------- + * Internal functions prototypes + * -------------------------------------------------------------------- */ + +void riscv_split_rfft_q15( + q15_t * pSrc, + uint32_t fftLen, + const q15_t * pATable, + const q15_t * pBTable, + q15_t * pDst, + uint32_t modifier); + +void riscv_split_rifft_q15( + q15_t * pSrc, + uint32_t fftLen, + const q15_t * pATable, + const q15_t * pBTable, + q15_t * pDst, + uint32_t modifier); + +/** + @addtogroup RealFFT + @{ + */ + +/** + @brief Processing function for the Q15 RFFT/RIFFT. + @param[in] S points to an instance of the Q15 RFFT/RIFFT structure + @param[in] pSrc points to input buffer (Source buffer is modified by this function.) + @param[out] pDst points to output buffer + @return none + + @par Input an output formats + Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process. + Hence the output format is different for different RFFT sizes. + The input and output formats for different RFFT sizes and number of bits to upscale are mentioned in the tables below for RFFT and RIFFT: + @par + \image html RFFTQ15.png "Input and Output Formats for Q15 RFFT" + @par + \image html RIFFTQ15.png "Input and Output Formats for Q15 RIFFT" + @par + If the input buffer is of length N, the output buffer must have length 2*N. + The input buffer is modified by this function. + @par + For the RIFFT, the source buffer must at least have length + fftLenReal + 2. + The last two elements must be equal to what would be generated + by the RFFT: + (pSrc[0] - pSrc[1]) >> 1 and 0 + */ + +void riscv_rfft_q15( + const riscv_rfft_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst) +{ + const riscv_cfft_instance_q15 *S_CFFT = S->pCfft; + uint32_t L2 = S->fftLenReal >> 1U; + + /* Calculation of RIFFT of input */ + if (S->ifftFlagR == 1U) + { + /* Real IFFT core process */ + riscv_split_rifft_q15 (pSrc, L2, S->pTwiddleAReal, S->pTwiddleBReal, pDst, S->twidCoefRModifier); + + /* Complex IFFT process */ + riscv_cfft_q15 (S_CFFT, pDst, S->ifftFlagR, S->bitReverseFlagR); + + riscv_shift_q15(pDst, 1, pDst, S->fftLenReal); + } + else + { + /* Calculation of RFFT of input */ + + /* Complex FFT process */ + riscv_cfft_q15 (S_CFFT, pSrc, S->ifftFlagR, S->bitReverseFlagR); + + /* Real FFT core process */ + riscv_split_rfft_q15 (pSrc, L2, S->pTwiddleAReal, S->pTwiddleBReal, pDst, S->twidCoefRModifier); + } + +} + +/** + @} end of RealFFT group + */ + +/** + @brief Core Real FFT process + @param[in] pSrc points to input buffer + @param[in] fftLen length of FFT + @param[in] pATable points to twiddle Coef A buffer + @param[in] pBTable points to twiddle Coef B buffer + @param[out] pDst points to output buffer + @param[in] modifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table + @return none + + @par + The function implements a Real FFT + */ + +void riscv_split_rfft_q15( + q15_t * pSrc, + uint32_t fftLen, + const q15_t * pATable, + const q15_t * pBTable, + q15_t * pDst, + uint32_t modifier) +{ + uint32_t i; /* Loop Counter */ + q31_t outR, outI; /* Temporary variables for output */ + const q15_t *pCoefA, *pCoefB; /* Temporary pointers for twiddle factors */ + q15_t *pSrc1, *pSrc2; +#if defined (RISCV_MATH_DSP) + q15_t *pD1, *pD2; +#endif + + /* Init coefficient pointers */ + pCoefA = &pATable[modifier * 2]; + pCoefB = &pBTable[modifier * 2]; + + pSrc1 = &pSrc[2]; + pSrc2 = &pSrc[(2U * fftLen) - 2U]; + +#if defined (RISCV_MATH_DSP) + + i = 1U; + pD1 = pDst + 2; + pD2 = pDst + (4U * fftLen) - 2; + + for (i = fftLen - 1; i > 0; i--) + { + /* + outR = ( pSrc[2 * i] * pATable[2 * i] + - pSrc[2 * i + 1] * pATable[2 * i + 1] + + pSrc[2 * n - 2 * i] * pBTable[2 * i] + + pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]); + + outI = ( pIn[2 * i + 1] * pATable[2 * i] + + pIn[2 * i] * pATable[2 * i + 1] + + pIn[2 * n - 2 * i] * pBTable[2 * i + 1] + - pIn[2 * n - 2 * i + 1] * pBTable[2 * i]) + */ + + + /* pSrc[2 * i] * pATable[2 * i] - pSrc[2 * i + 1] * pATable[2 * i + 1] */ + outR = __RV_SMDRS(read_q15x2 (pSrc1), read_q15x2((q15_t *) pCoefA)); + + /* pSrc[2 * n - 2 * i] * pBTable[2 * i] + pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]) */ + outR = __RV_KMADA(outR, read_q15x2 (pSrc2), read_q15x2((q15_t *) pCoefB)) >> 16U; + + /* pIn[2 * n - 2 * i] * pBTable[2 * i + 1] - pIn[2 * n - 2 * i + 1] * pBTable[2 * i] */ + outI = __RV_SMXDS(read_q15x2((q15_t *) pCoefB), read_q15x2_da (&pSrc2)); + + /* (pIn[2 * i + 1] * pATable[2 * i] + pIn[2 * i] * pATable[2 * i + 1] */ + outI = __RV_KMAXDA(outI, read_q15x2_ia (&pSrc1), read_q15x2 ((q15_t *) pCoefA)); + + /* write output */ + *pD1++ = (q15_t) outR; + *pD1++ = outI >> 16U; + + /* write complex conjugate output */ + pD2[0] = (q15_t) outR; + pD2[1] = -(outI >> 16U); + pD2 -= 2; + + /* update coefficient pointer */ + pCoefB = pCoefB + (2U * modifier); + pCoefA = pCoefA + (2U * modifier); + } + + pDst[2U * fftLen] = (pSrc[0] - pSrc[1]) >> 1U; + pDst[2U * fftLen + 1U] = 0; + + pDst[0] = (pSrc[0] + pSrc[1]) >> 1U; + pDst[1] = 0; + +#else + + i = 1U; + + while (i < fftLen) + { + /* + outR = ( pSrc[2 * i] * pATable[2 * i] + - pSrc[2 * i + 1] * pATable[2 * i + 1] + + pSrc[2 * n - 2 * i] * pBTable[2 * i] + + pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]); + */ + + outR = *pSrc1 * *pCoefA; + outR = outR - (*(pSrc1 + 1) * *(pCoefA + 1)); + outR = outR + (*pSrc2 * *pCoefB); + outR = (outR + (*(pSrc2 + 1) * *(pCoefB + 1))) >> 16; + + /* + outI = ( pIn[2 * i + 1] * pATable[2 * i] + + pIn[2 * i] * pATable[2 * i + 1] + + pIn[2 * n - 2 * i] * pBTable[2 * i + 1] + - pIn[2 * n - 2 * i + 1] * pBTable[2 * i]); + */ + + outI = *pSrc2 * *(pCoefB + 1); + outI = outI - (*(pSrc2 + 1) * *pCoefB); + outI = outI + (*(pSrc1 + 1) * *pCoefA); + outI = outI + (*pSrc1 * *(pCoefA + 1)); + + /* update input pointers */ + pSrc1 += 2U; + pSrc2 -= 2U; + + /* write output */ + pDst[2U * i] = (q15_t) outR; + pDst[2U * i + 1U] = outI >> 16U; + + /* write complex conjugate output */ + pDst[(4U * fftLen) - (2U * i)] = (q15_t) outR; + pDst[((4U * fftLen) - (2U * i)) + 1U] = -(outI >> 16U); + + /* update coefficient pointer */ + pCoefB = pCoefB + (2U * modifier); + pCoefA = pCoefA + (2U * modifier); + + i++; + } + + pDst[2U * fftLen] = (pSrc[0] - pSrc[1]) >> 1; + pDst[2U * fftLen + 1U] = 0; + + pDst[0] = (pSrc[0] + pSrc[1]) >> 1; + pDst[1] = 0; + +#endif /* #if defined (RISCV_MATH_DSP) */ + +} + +/** + @brief Core Real IFFT process + @param[in] pSrc points to input buffer + @param[in] fftLen length of FFT + @param[in] pATable points to twiddle Coef A buffer + @param[in] pBTable points to twiddle Coef B buffer + @param[out] pDst points to output buffer + @param[in] modifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table + @return none + + @par + The function implements a Real IFFT + */ + +void riscv_split_rifft_q15( + q15_t * pSrc, + uint32_t fftLen, + const q15_t * pATable, + const q15_t * pBTable, + q15_t * pDst, + uint32_t modifier) +{ + uint32_t i; /* Loop Counter */ + q31_t outR, outI; /* Temporary variables for output */ + const q15_t *pCoefA, *pCoefB; /* Temporary pointers for twiddle factors */ + q15_t *pSrc1, *pSrc2; + q15_t *pDst1 = &pDst[0]; + + pCoefA = &pATable[0]; + pCoefB = &pBTable[0]; + + pSrc1 = &pSrc[0]; + pSrc2 = &pSrc[2 * fftLen]; + + i = fftLen; + while (i > 0U) + { + /* + outR = ( pIn[2 * i] * pATable[2 * i] + + pIn[2 * i + 1] * pATable[2 * i + 1] + + pIn[2 * n - 2 * i] * pBTable[2 * i] + - pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]); + + outI = ( pIn[2 * i + 1] * pATable[2 * i] + - pIn[2 * i] * pATable[2 * i + 1] + - pIn[2 * n - 2 * i] * pBTable[2 * i + 1] + - pIn[2 * n - 2 * i + 1] * pBTable[2 * i]); + */ + +#if defined (RISCV_MATH_DSP) + + /* pIn[2 * n - 2 * i] * pBTable[2 * i] - pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]) */ + outR = __RV_SMDRS(read_q15x2(pSrc2), read_q15x2((q15_t *) pCoefB)); + + /* pIn[2 * i] * pATable[2 * i] + pIn[2 * i + 1] * pATable[2 * i + 1] + pIn[2 * n - 2 * i] * pBTable[2 * i] */ + outR = __RV_KMADA(outR, read_q15x2(pSrc1), read_q15x2 ((q15_t *) pCoefA)) >> 16U; + + /* -pIn[2 * n - 2 * i] * pBTable[2 * i + 1] + pIn[2 * n - 2 * i + 1] * pBTable[2 * i] */ + outI = __RV_KMXDA(read_q15x2_da (&pSrc2), read_q15x2((q15_t *) pCoefB)); + + /* pIn[2 * i + 1] * pATable[2 * i] - pIn[2 * i] * pATable[2 * i + 1] */ + outI = __SMLSDX(read_q15x2 ((q15_t *) pCoefA), read_q15x2_ia (&pSrc1), -outI); + + /* write output */ + write_q15x2_ia (&pDst1, __PKHBT(outR, (outI >> 16U), 16)); + + +#else /* #if defined (RISCV_MATH_DSP) */ + + outR = *pSrc2 * *pCoefB; + outR = outR - (*(pSrc2 + 1) * *(pCoefB + 1)); + outR = outR + (*pSrc1 * *pCoefA); + outR = (outR + (*(pSrc1 + 1) * *(pCoefA + 1))) >> 16; + + outI = *(pSrc1 + 1) * *pCoefA; + outI = outI - (*pSrc1 * *(pCoefA + 1)); + outI = outI - (*pSrc2 * *(pCoefB + 1)); + outI = outI - (*(pSrc2 + 1) * *(pCoefB)); + + /* update input pointers */ + pSrc1 += 2U; + pSrc2 -= 2U; + + /* write output */ + *pDst1++ = (q15_t) outR; + *pDst1++ = (q15_t) (outI >> 16); + +#endif /* #if defined (RISCV_MATH_DSP) */ + + /* update coefficient pointer */ + pCoefB = pCoefB + (2 * modifier); + pCoefA = pCoefA + (2 * modifier); + + i--; + } + +} diff --git a/components/nmsis/dsp/src/TransformFunctions/riscv_rfft_q31.c b/components/nmsis/dsp/src/TransformFunctions/riscv_rfft_q31.c new file mode 100644 index 00000000..be9dda5e --- /dev/null +++ b/components/nmsis/dsp/src/TransformFunctions/riscv_rfft_q31.c @@ -0,0 +1,299 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS DSP Library + * Title: riscv_rfft_q31.c + * Description: FFT & RIFFT Q31 process function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" + +/* ---------------------------------------------------------------------- + * Internal functions prototypes + * -------------------------------------------------------------------- */ + +void riscv_split_rfft_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pATable, + const q31_t * pBTable, + q31_t * pDst, + uint32_t modifier); + +void riscv_split_rifft_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pATable, + const q31_t * pBTable, + q31_t * pDst, + uint32_t modifier); + +/** + @addtogroup RealFFT + @{ + */ + +/** + @brief Processing function for the Q31 RFFT/RIFFT. + @param[in] S points to an instance of the Q31 RFFT/RIFFT structure + @param[in] pSrc points to input buffer (Source buffer is modified by this function) + @param[out] pDst points to output buffer + @return none + + @par Input an output formats + Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process. + Hence the output format is different for different RFFT sizes. + The input and output formats for different RFFT sizes and number of bits to upscale are mentioned in the tables below for RFFT and RIFFT: + @par + \image html RFFTQ31.png "Input and Output Formats for Q31 RFFT" + @par + \image html RIFFTQ31.png "Input and Output Formats for Q31 RIFFT" + @par + If the input buffer is of length N, the output buffer must have length 2*N. + The input buffer is modified by this function. + @par + For the RIFFT, the source buffer must at least have length + fftLenReal + 2. + The last two elements must be equal to what would be generated + by the RFFT: + (pSrc[0] - pSrc[1]) >> 1 and 0 + + */ + +void riscv_rfft_q31( + const riscv_rfft_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst) +{ + const riscv_cfft_instance_q31 *S_CFFT = S->pCfft; + uint32_t L2 = S->fftLenReal >> 1U; + + /* Calculation of RIFFT of input */ + if (S->ifftFlagR == 1U) + { + /* Real IFFT core process */ + riscv_split_rifft_q31 (pSrc, L2, S->pTwiddleAReal, S->pTwiddleBReal, pDst, S->twidCoefRModifier); + + /* Complex IFFT process */ + riscv_cfft_q31 (S_CFFT, pDst, S->ifftFlagR, S->bitReverseFlagR); + + riscv_shift_q31(pDst, 1, pDst, S->fftLenReal); + } + else + { + /* Calculation of RFFT of input */ + + /* Complex FFT process */ + riscv_cfft_q31 (S_CFFT, pSrc, S->ifftFlagR, S->bitReverseFlagR); + + /* Real FFT core process */ + riscv_split_rfft_q31 (pSrc, L2, S->pTwiddleAReal, S->pTwiddleBReal, pDst, S->twidCoefRModifier); + } + +} + +/** + @} end of RealFFT group + */ + +/** + @brief Core Real FFT process + @param[in] pSrc points to input buffer + @param[in] fftLen length of FFT + @param[in] pATable points to twiddle Coef A buffer + @param[in] pBTable points to twiddle Coef B buffer + @param[out] pDst points to output buffer + @param[in] modifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table + @return none + */ + +void riscv_split_rfft_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pATable, + const q31_t * pBTable, + q31_t * pDst, + uint32_t modifier) +{ + uint32_t i; /* Loop Counter */ + q31_t outR, outI; /* Temporary variables for output */ + const q31_t *pCoefA, *pCoefB; /* Temporary pointers for twiddle factors */ + q31_t CoefA1, CoefA2, CoefB1; /* Temporary variables for twiddle coefficients */ + q31_t *pOut1 = &pDst[2], *pOut2 = &pDst[4 * fftLen - 1]; + q31_t *pIn1 = &pSrc[2], *pIn2 = &pSrc[2 * fftLen - 1]; + + /* Init coefficient pointers */ + pCoefA = &pATable[modifier * 2]; + pCoefB = &pBTable[modifier * 2]; + + i = fftLen - 1U; + + while (i > 0U) + { + /* + outR = ( pSrc[2 * i] * pATable[2 * i] + - pSrc[2 * i + 1] * pATable[2 * i + 1] + + pSrc[2 * n - 2 * i] * pBTable[2 * i] + + pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]); + + outI = ( pIn[2 * i + 1] * pATable[2 * i] + + pIn[2 * i] * pATable[2 * i + 1] + + pIn[2 * n - 2 * i] * pBTable[2 * i + 1] + - pIn[2 * n - 2 * i + 1] * pBTable[2 * i]); + */ + + CoefA1 = *pCoefA++; + CoefA2 = *pCoefA; + + /* outR = (pSrc[2 * i] * pATable[2 * i] */ + mult_32x32_keep32_R (outR, *pIn1, CoefA1); + + /* outI = pIn[2 * i] * pATable[2 * i + 1] */ + mult_32x32_keep32_R (outI, *pIn1++, CoefA2); + + /* - pSrc[2 * i + 1] * pATable[2 * i + 1] */ + multSub_32x32_keep32_R (outR, *pIn1, CoefA2); + + /* (pIn[2 * i + 1] * pATable[2 * i] */ + multAcc_32x32_keep32_R (outI, *pIn1++, CoefA1); + + /* pSrc[2 * n - 2 * i] * pBTable[2 * i] */ + multSub_32x32_keep32_R (outR, *pIn2, CoefA2); + CoefB1 = *pCoefB; + + /* pIn[2 * n - 2 * i] * pBTable[2 * i + 1] */ + multSub_32x32_keep32_R (outI, *pIn2--, CoefB1); + + /* pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1] */ + multAcc_32x32_keep32_R (outR, *pIn2, CoefB1); + + /* pIn[2 * n - 2 * i + 1] * pBTable[2 * i] */ + multSub_32x32_keep32_R (outI, *pIn2--, CoefA2); + + /* write output */ + *pOut1++ = outR; + *pOut1++ = outI; + + /* write complex conjugate output */ + *pOut2-- = -outI; + *pOut2-- = outR; + + /* update coefficient pointer */ + pCoefB = pCoefB + (2 * modifier); + pCoefA = pCoefA + (2 * modifier - 1); + + /* Decrement loop count */ + i--; + } + + pDst[2 * fftLen] = (pSrc[0] - pSrc[1]) >> 1U; + pDst[2 * fftLen + 1] = 0; + + pDst[0] = (pSrc[0] + pSrc[1]) >> 1U; + pDst[1] = 0; +} + +/** + @brief Core Real IFFT process + @param[in] pSrc points to input buffer + @param[in] fftLen length of FFT + @param[in] pATable points to twiddle Coef A buffer + @param[in] pBTable points to twiddle Coef B buffer + @param[out] pDst points to output buffer + @param[in] modifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table + @return none + */ + +void riscv_split_rifft_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pATable, + const q31_t * pBTable, + q31_t * pDst, + uint32_t modifier) +{ + q31_t outR, outI; /* Temporary variables for output */ + const q31_t *pCoefA, *pCoefB; /* Temporary pointers for twiddle factors */ + q31_t CoefA1, CoefA2, CoefB1; /* Temporary variables for twiddle coefficients */ + q31_t *pIn1 = &pSrc[0], *pIn2 = &pSrc[2 * fftLen + 1]; + + pCoefA = &pATable[0]; + pCoefB = &pBTable[0]; + + while (fftLen > 0U) + { + /* + outR = ( pIn[2 * i] * pATable[2 * i] + + pIn[2 * i + 1] * pATable[2 * i + 1] + + pIn[2 * n - 2 * i] * pBTable[2 * i] + - pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]); + + outI = ( pIn[2 * i + 1] * pATable[2 * i] + - pIn[2 * i] * pATable[2 * i + 1] + - pIn[2 * n - 2 * i] * pBTable[2 * i + 1] + - pIn[2 * n - 2 * i + 1] * pBTable[2 * i]); + */ + + CoefA1 = *pCoefA++; + CoefA2 = *pCoefA; + + /* outR = (pIn[2 * i] * pATable[2 * i] */ + mult_32x32_keep32_R (outR, *pIn1, CoefA1); + + /* - pIn[2 * i] * pATable[2 * i + 1] */ + mult_32x32_keep32_R (outI, *pIn1++, -CoefA2); + + /* pIn[2 * i + 1] * pATable[2 * i + 1] */ + multAcc_32x32_keep32_R (outR, *pIn1, CoefA2); + + /* pIn[2 * i + 1] * pATable[2 * i] */ + multAcc_32x32_keep32_R (outI, *pIn1++, CoefA1); + + /* pIn[2 * n - 2 * i] * pBTable[2 * i] */ + multAcc_32x32_keep32_R (outR, *pIn2, CoefA2); + CoefB1 = *pCoefB; + + /* pIn[2 * n - 2 * i] * pBTable[2 * i + 1] */ + multSub_32x32_keep32_R (outI, *pIn2--, CoefB1); + + /* pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1] */ + multAcc_32x32_keep32_R (outR, *pIn2, CoefB1); + + /* pIn[2 * n - 2 * i + 1] * pBTable[2 * i] */ + multAcc_32x32_keep32_R (outI, *pIn2--, CoefA2); + + /* write output */ + *pDst++ = outR; + *pDst++ = outI; + + /* update coefficient pointer */ + pCoefB = pCoefB + (modifier * 2); + pCoefA = pCoefA + (modifier * 2 - 1); + + /* Decrement loop count */ + fftLen--; + } + +} + diff --git a/components/nmsis/nn/inc/riscv_nn_tables.h b/components/nmsis/nn/inc/riscv_nn_tables.h new file mode 100644 index 00000000..dc2074f3 --- /dev/null +++ b/components/nmsis/nn/inc/riscv_nn_tables.h @@ -0,0 +1,57 @@ +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_nn_tables.h + * Description: Extern declaration for NN tables + * + * $Date: 09. October 2020 + * $Revision: V.1.0.1 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _RISCV_NN_TABLES_H +#define _RISCV_NN_TABLES_H + +#include "riscv_math_types.h" + +/** +* @brief tables for various activation functions +* +*/ + +extern const q15_t sigmoidTable_q15[256]; +extern const q7_t sigmoidTable_q7[256]; + +extern const q7_t tanhTable_q7[256]; +extern const q15_t tanhTable_q15[256]; + +/** + * @brief 2-way tables for various activation functions + * + * 2-way table, H table for value larger than 1/4 + * L table for value smaller than 1/4, H table for remaining + * We have this only for the q15_t version. It does not make + * sense to have it for q7_t type + */ +extern const q15_t sigmoidHTable_q15[192]; +extern const q15_t sigmoidLTable_q15[128]; + +#endif /* RISCV_NN_TABLES_H */ diff --git a/components/nmsis/nn/inc/riscv_nn_types.h b/components/nmsis/nn/inc/riscv_nn_types.h new file mode 100644 index 00000000..29008793 --- /dev/null +++ b/components/nmsis/nn/inc/riscv_nn_types.h @@ -0,0 +1,131 @@ +/* + * Copyright (C) 2020-2021 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_nn_types.h + * Description: Public header file to contain the NMSIS-NN structs for the + * TensorFlowLite micro compliant functions + * + * $Date: 19. March 2021 + * $Revision: V.2.0.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ + +#ifndef _RISCV_NN_TYPES_H +#define _RISCV_NN_TYPES_H + +#include + +/** NMSIS-NN object to contain the width and height of a tile */ +typedef struct +{ + int32_t w; /**< Width */ + int32_t h; /**< Height */ +} nmsis_nn_tile; + +/** NMSIS-NN object used for the function context. */ +typedef struct +{ + void *buf; /**< Pointer to a buffer needed for the optimization */ + int32_t size; /**< Buffer size */ +} nmsis_nn_context; + +/** NMSIS-NN object to contain the dimensions of the tensors */ +typedef struct +{ + int32_t n; /**< Generic dimension to contain either the batch size or output channels. + Please refer to the function documentation for more information */ + int32_t h; /**< Height */ + int32_t w; /**< Width */ + int32_t c; /**< Input channels */ +} nmsis_nn_dims; + +/** NMSIS-NN object for the per-channel quantization parameters */ +typedef struct +{ + int32_t *multiplier; /**< Multiplier values */ + int32_t *shift; /**< Shift values */ +} nmsis_nn_per_channel_quant_params; + +/** NMSIS-NN object for the per-tensor quantization parameters */ +typedef struct +{ + int32_t multiplier; /**< Multiplier value */ + int32_t shift; /**< Shift value */ +} nmsis_nn_per_tensor_quant_params; + +/** NMSIS-NN object for the quantized Relu activation */ +typedef struct +{ + int32_t min; /**< Min value used to clamp the result */ + int32_t max; /**< Max value used to clamp the result */ +} nmsis_nn_activation; + +/** NMSIS-NN object for the convolution layer parameters */ +typedef struct +{ + int32_t input_offset; /**< Zero value for the input tensor */ + int32_t output_offset; /**< Zero value for the output tensor */ + nmsis_nn_tile stride; + nmsis_nn_tile padding; + nmsis_nn_tile dilation; + nmsis_nn_activation activation; +} nmsis_nn_conv_params; + +/** NMSIS-NN object for Depthwise convolution layer parameters */ +typedef struct +{ + int32_t input_offset; /**< Zero value for the input tensor */ + int32_t output_offset; /**< Zero value for the output tensor */ + int32_t ch_mult; /**< Channel Multiplier. ch_mult * in_ch = out_ch */ + nmsis_nn_tile stride; + nmsis_nn_tile padding; + nmsis_nn_tile dilation; + nmsis_nn_activation activation; +} nmsis_nn_dw_conv_params; +/** NMSIS-NN object for pooling layer parameters */ +typedef struct +{ + nmsis_nn_tile stride; + nmsis_nn_tile padding; + nmsis_nn_activation activation; +} nmsis_nn_pool_params; + +/** NMSIS-NN object for Fully Connected layer parameters */ +typedef struct +{ + int32_t input_offset; /**< Zero value for the input tensor */ + int32_t filter_offset; /**< Zero value for the filter tensor. Not used */ + int32_t output_offset; /**< Zero value for the output tensor */ + nmsis_nn_activation activation; +} nmsis_nn_fc_params; + +/** NMSIS-NN object for SVDF layer parameters */ +typedef struct +{ + int32_t rank; + int32_t input_offset; /**< Zero value for the input tensor */ + int32_t output_offset; /**< Zero value for the output tensor */ + nmsis_nn_activation input_activation; + nmsis_nn_activation output_activation; +} nmsis_nn_svdf_params; + +#endif // _RISCV_NN_TYPES_H diff --git a/components/nmsis/nn/inc/riscv_nnfunctions.h b/components/nmsis/nn/inc/riscv_nnfunctions.h new file mode 100644 index 00000000..9532b429 --- /dev/null +++ b/components/nmsis/nn/inc/riscv_nnfunctions.h @@ -0,0 +1,2159 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_nnfunctions.h + * Description: Public header file for NMSIS NN Library + * + * $Date: 19 March 2021 + * $Revision: V.7.0.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ + +/** + \mainpage NMSIS NN Software Library + * + * Introduction + * ------------ + * + * This user manual describes the NMSIS NN software library, + * a collection of efficient neural network kernels developed to maximize the + * performance and minimize the memory footprint of neural networks on Nuclei N processor cores. + * + * The library is divided into a number of functions each covering a specific category: + * - Convolution Functions + * - Activation Functions + * - Fully-connected Layer Functions + * - SVDF Layer Functions + * - Pooling Functions + * - Softmax Functions + * - Basic math Functions + * + * The library has separate functions for operating on different weight and activation data + * types including 8-bit integers (q7_t) and 16-bit integers (q15_t). The descrition of the + * kernels are included in the function description. The implementation details are also + * described in this paper [1]. + * + * \note Please refer to [NMSIS-NN](../../../nn/index.html) + * + * Block Diagram + * -------- + * \image html NMSIS-NN-OVERVIEW.PNG + * + * Examples + * -------- + * + * The library ships with a number of examples which demonstrate how to use the library functions. + * + * Pre-processor Macros + * ------------ + * + * Each library project have different pre-processor macros. + * + * - RISCV_MATH_DSP: + * + * Define macro RISCV_MATH_DSP, If the silicon supports DSP instructions. + * + * - RISCV_NN_TRUNCATE: + * + * Define macro RISCV_NN_TRUNCATE to use floor instead of round-to-the-nearest-int for the computation. + * + * + * [1] CMSIS-NN: Efficient Neural Network Kernels for Arm Cortex-M CPUs https://arxiv.org/abs/1801.06601 + * + * [2] Converting a Neural Network for Arm Cortex-M with NMSIS-NN + * + https://developer.arm.com/solutions/machine-learning-on-arm/developer-material/how-to-guides/converting-a-neural-network-for-arm-RISC-V-with-nmsis-nn/single-page + * [3] https://www.tensorflow.org/lite/microcontrollers/library + * + * [4] https://github.com/ARM-software/NMSIS_5/tree/develop/NMSIS/NN#legacy-vs-tfl-micro-compliant-apis + */ + +/** + * @defgroup groupNN Neural Network Functions + * A collection of functions to perform basic operations for neural network layers. Functions with a _s8 suffix support + * TensorFlow Lite framework. + */ + +#ifndef _RISCV_NNFUNCTIONS_H +#define _RISCV_NNFUNCTIONS_H + +#include "riscv_math_types.h" +#include "riscv_nn_types.h" + +#define USE_INTRINSIC + +//#define RISCV_NN_TRUNCATE /* This config the rounding model to floor or round to the nearest int */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Struct for specifying activation function types + * + */ +typedef enum +{ + RISCV_SIGMOID = 0, + /**< Sigmoid activation function */ + RISCV_TANH = 1, + /**< Tanh activation function */ +} riscv_nn_activation_type; + +/** + * @defgroup NNConv Convolution Functions + * + * Collection of convolution, depthwise convolution functions and their variants. + * + * The convolution is implemented in 2 steps: im2col and GEMM + * + * im2col is a process of converting each patch of image data into + * a column. After im2col, the convolution is computed as matrix-matrix + * multiplication. + * + * To reduce the memory footprint, the im2col is performed partially. + * Each iteration, only a few column (i.e., patches) are generated and + * computed with GEMM kernels similar to NMSIS-DSP riscv_mat_mult functions. + * + */ + +/** + * @brief s8 convolution layer wrapper function with the main purpose to call the optimal kernel available in + nmsis-nn + * to perform the convolution. + * + * @param[in, out] ctx Function context that contains the additional buffer if required by the function. + riscv_convolve_wrapper_s8_get_buffer_size will return the buffer_size if required + * @param[in] conv_params Convolution parameters (e.g. strides, dilations, pads,...). + * Range of conv_params->input_offset : [-127, 128] + * Range of conv_params->output_offset : [-128, 127] + * @param[in] quant_params Per-channel quantization info. + * It contains the multiplier and shift values to be applied to each output channel + * @param[in] input_dims Input (activation) tensor dimensions. Format: [N, H, W, C_IN] + * @param[in] input_data Input (activation) data pointer. Data type: int8 + * @param[in] filter_dims Filter tensor dimensions. Format: [C_OUT, HK, WK, C_IN] where HK and WK are the + * spatial filter dimensions + * @param[in] filter_data Filter data pointer. Data type: int8 + * @param[in] bias_dims Bias tensor dimensions. Format: [C_OUT] + * @param[in] bias_data Bias data pointer. Data type: int32 + * @param[in] output_dims Output tensor dimensions. Format: [N, H, W, C_OUT] + * @param[out] output_data Output data pointer. Data type: int8 + * + * @return The function returns either + * RISCV_MATH_SIZE_MISMATCH if argument constraints fail. or, + * RISCV_MATH_SUCCESS on successful completion. + * + */ +riscv_status riscv_convolve_wrapper_s8(const nmsis_nn_context *ctx, + const nmsis_nn_conv_params *conv_params, + const nmsis_nn_per_channel_quant_params *quant_params, + const nmsis_nn_dims *input_dims, + const q7_t *input_data, + const nmsis_nn_dims *filter_dims, + const q7_t *filter_data, + const nmsis_nn_dims *bias_dims, + const int32_t *bias_data, + const nmsis_nn_dims *output_dims, + q7_t *output_data); + +/** + * @brief Get the required buffer size for riscv_convolve_wrapper_s8 + * + * @param[in] conv_params Convolution parameters (e.g. strides, dilations, pads,...). + * Range of conv_params->input_offset : [-127, 128] + * Range of conv_params->output_offset : [-128, 127] + * @param[in] input_dims Input (activation) dimensions. Format: [N, H, W, C_IN] + * @param[in] filter_dims Filter dimensions. Format: [C_OUT, HK, WK, C_IN] where HK and WK are the spatial + * filter dimensions + * @param[in] output_dims Output tensor dimensions. Format: [N, H, W, C_OUT] + * + * @return The function returns required buffer size(bytes) + * + */ +int32_t riscv_convolve_wrapper_s8_get_buffer_size(const nmsis_nn_conv_params *conv_params, + const nmsis_nn_dims *input_dims, + const nmsis_nn_dims *filter_dims, + const nmsis_nn_dims *output_dims); + +/** + * @brief Basic s8 convolution function + * @param[in, out] ctx Function context that contains the additional buffer if required by the function. + riscv_convolve_s8_get_buffer_size will return the buffer_size if required + * @param[in] conv_params Convolution parameters (e.g. strides, dilations, pads,...). + * Range of conv_params->input_offset : [-127, 128] + * Range of conv_params->output_offset : [-128, 127] + * @param[in] quant_params Per-channel quantization info. + * It contains the multiplier and shift values to be applied to each output channel + * @param[in] input_dims Input (activation) tensor dimensions. Format: [N, H, W, C_IN] + * @param[in] input_data Input (activation) data pointer. Data type: int8 + * @param[in] filter_dims Filter tensor dimensions. Format: [C_OUT, HK, WK, C_IN] where HK and WK are the + * spatial filter dimensions + * @param[in] filter_data Filter data pointer. Data type: int8 + * @param[in] bias_dims Bias tensor dimensions. Format: [C_OUT] + * @param[in] bias_data Optional bias data pointer. Data type: int32 + * @param[in] output_dims Output tensor dimensions. Format: [N, H, W, C_OUT] + * @param[out] output_data Output data pointer. Data type: int8 + + * @return The function returns RISCV_MATH_SUCCESS + * + * @details + * 1. Supported framework: TensorFlow Lite micro + * 2. q7 is used as data type eventhough it is s8 data. It is done so to be consistent with existing APIs. + * 3. Additional memory is required for optimization. Refer to argument 'ctx' for details. + * + */ +riscv_status riscv_convolve_s8(const nmsis_nn_context *ctx, + const nmsis_nn_conv_params *conv_params, + const nmsis_nn_per_channel_quant_params *quant_params, + const nmsis_nn_dims *input_dims, + const q7_t *input_data, + const nmsis_nn_dims *filter_dims, + const q7_t *filter_data, + const nmsis_nn_dims *bias_dims, + const int32_t *bias_data, + const nmsis_nn_dims *output_dims, + q7_t *output_data); + +/** + * @brief Get the required buffer size for s8 convolution function + * + * @param[in] input_dims Input (activation) tensor dimensions. Format: [N, H, W, C_IN] + * @param[in] filter_dims Filter tensor dimensions. Format: [C_OUT, HK, WK, C_IN] where HK and WK + * are the spatial filter dimensions + * @return The function returns required buffer size(bytes) + * + */ +int32_t riscv_convolve_s8_get_buffer_size(const nmsis_nn_dims *input_dims, const nmsis_nn_dims *filter_dims); + +/** + * @brief Basic Q7 convolution function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimension + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns RISCV_MATH_SUCCESS + * + */ +riscv_status riscv_convolve_HWC_q7_basic(const q7_t *Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q7_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q7_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t *Im_out, + const uint16_t dim_im_out, + q15_t *bufferA, + q7_t *bufferB); + +/** + * @brief Basic Q7 convolution function (non-square shape) + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in_x input tensor dimension x + * @param[in] dim_im_in_y input tensor dimension y + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel_x filter kernel size x + * @param[in] dim_kernel_y filter kernel size y + * @param[in] padding_x padding size x + * @param[in] padding_y padding size y + * @param[in] stride_x convolution stride x + * @param[in] stride_y convolution stride y + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out_x output tensor dimension x + * @param[in] dim_im_out_y output tensor dimension y + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns RISCV_MATH_SUCCESS + */ +riscv_status riscv_convolve_HWC_q7_basic_nonsquare(const q7_t *Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q7_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q7_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t *Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t *bufferA, + q7_t *bufferB); + +/** + * @brief Basic Q15 convolution function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimension + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns RISCV_MATH_SUCCESS + * + */ +riscv_status riscv_convolve_HWC_q15_basic(const q15_t *Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q15_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q15_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q15_t *Im_out, + const uint16_t dim_im_out, + q15_t *bufferA, + q7_t *bufferB); + +/** + * @brief Fast Q7 convolution function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimension + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * RISCV_MATH_SIZE_MISMATCH or RISCV_MATH_SUCCESS based on the outcome of size checking. + * + * This function is the version with full list of optimization tricks, but with + * some contraints: + * ch_im_in is multiple of 4 + * ch_im_out is multiple of 2 + */ +riscv_status riscv_convolve_HWC_q7_fast(const q7_t *Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q7_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q7_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t *Im_out, + const uint16_t dim_im_out, + q15_t *bufferA, + q7_t *bufferB); + +/** + * @brief Fast Q7 convolution function (non-sqaure shape) + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in_x input tensor dimension x + * @param[in] dim_im_in_y input tensor dimension y + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel_x filter kernel size x + * @param[in] dim_kernel_y filter kernel size y + * @param[in] padding_x padding size x + * @param[in] padding_y padding size y + * @param[in] stride_x convolution stride x + * @param[in] stride_y convolution stride y + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out_x output tensor dimension x + * @param[in] dim_im_out_y output tensor dimension y + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * RISCV_MATH_SIZE_MISMATCH or RISCV_MATH_SUCCESS based on the outcome of size checking. + * + * This function is the version with full list of optimization tricks, but with + * some contraints: + * ch_im_in is multiple of 4 + * ch_im_out is multiple of 2 + */ + +riscv_status riscv_convolve_HWC_q7_fast_nonsquare(const q7_t *Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q7_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q7_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t *Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t *bufferA, + q7_t *bufferB); + +/** + * @brief Fast Q7 version of 1x1 convolution (non-sqaure shape) + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in_x input tensor dimension x + * @param[in] dim_im_in_y input tensor dimension y + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel_x filter kernel size x + * @param[in] dim_kernel_y filter kernel size y + * @param[in] padding_x padding size x + * @param[in] padding_y padding size y + * @param[in] stride_x convolution stride x + * @param[in] stride_y convolution stride y + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out_x output tensor dimension x + * @param[in] dim_im_out_y output tensor dimension y + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * RISCV_MATH_SIZE_MISMATCH if argument constraints fail. or, + * RISCV_MATH_SUCCESS on successful completion. + * + * This function implement convolution with 1x1 kernel size (i.e., dim_kernel_x=1 + * and dim_kernel_y=1). It can be used for + * second half of MobileNets after depthwise separable convolution. + * + * This function is the version with full list of optimization tricks, but with + * some contraints: + * ch_im_in is multiple of 4 + * ch_im_out is multiple of 2 + */ +riscv_status riscv_convolve_1x1_HWC_q7_fast_nonsquare(const q7_t *Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q7_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q7_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t *Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t *bufferA, + q7_t *bufferB); + +/** + * @brief Fast s8 version for 1x1 convolution (non-square shape) + * + * @param[in, out] ctx Function context that contains the additional buffer if required by the function. + riscv_convolve_1x1_s8_fast_get_buffer_size will return the buffer_size if required + * @param[in] conv_params Convolution parameters (e.g. strides, dilations, pads,...). + * Range of conv_params->input_offset : [-127, 128] + * Range of conv_params->output_offset : [-128, 127] + * @param[in] quant_params Per-channel quantization info. + * It contains the multiplier and shift values to be applied to each output channel + * @param[in] input_dims Input (activation) tensor dimensions. Format: [N, H, W, C_IN] + * @param[in] input_data Input (activation) data pointer. Data type: int8 + * @param[in] filter_dims Filter tensor dimensions. Format: [C_OUT, 1, 1, C_IN] + * @param[in] filter_data Filter data pointer. Data type: int8 + * @param[in] bias_dims Bias tensor dimensions. Format: [C_OUT] + * @param[in] bias_data Optional bias data pointer. Data type: int32 + * @param[in] output_dims Output tensor dimensions. Format: [N, H, W, C_OUT] + * @param[out] output_data Output data pointer. Data type: int8 + * + * @return The function returns either + * RISCV_MATH_SIZE_MISMATCH if argument constraints fail. or, + * RISCV_MATH_SUCCESS on successful completion. + * + * @details + * - Supported framework : TensorFlow Lite Micro + * - The following constrains on the arguments apply + * -# input_dims->c is a multiple of 4 + * -# conv_params->padding.w = conv_params->padding.h = 0 + * -# conv_params->stride.w = conv_params->stride.h = 1 + * + */ +riscv_status riscv_convolve_1x1_s8_fast(const nmsis_nn_context *ctx, + const nmsis_nn_conv_params *conv_params, + const nmsis_nn_per_channel_quant_params *quant_params, + const nmsis_nn_dims *input_dims, + const q7_t *input_data, + const nmsis_nn_dims *filter_dims, + const q7_t *filter_data, + const nmsis_nn_dims *bias_dims, + const int32_t *bias_data, + const nmsis_nn_dims *output_dims, + q7_t *output_data); + +/** + * @brief Get the required buffer size for riscv_convolve_1x1_s8_fast + * + * @param[in] input_dims Input (activation) dimensions + * @return The function returns the required buffer size in bytes + * + */ +int32_t riscv_convolve_1x1_s8_fast_get_buffer_size(const nmsis_nn_dims *input_dims); + +/** + * @brief 1xn convolution + * + * @param[in, out] ctx Function context that contains the additional buffer if required by the function. + riscv_convolve_1_x_n_s8_get_buffer_size will return the buffer_size if required + * @param[in] conv_params Convolution parameters (e.g. strides, dilations, pads,...). + * Range of conv_params->input_offset : [-127, 128] + * Range of conv_params->output_offset : [-128, 127] + * @param[in] quant_params Per-channel quantization info. + * It contains the multiplier and shift values to be applied to each output channel + * @param[in] input_dims Input (activation) tensor dimensions. Format: [N, H, W, C_IN] + * @param[in] input_data Input (activation) data pointer. Data type: int8 + * @param[in] filter_dims Filter tensor dimensions. Format: [C_OUT, 1, WK, C_IN] where WK is the horizontal + * spatial filter dimension + * @param[in] filter_data Filter data pointer. Data type: int8 + * @param[in] bias_dims Bias tensor dimensions. Format: [C_OUT] + * @param[in] bias_data Optional bias data pointer. Data type: int32 + * @param[in] output_dims Output tensor dimensions. Format: [N, H, W, C_OUT] + * @param[out] output_data Output data pointer. Data type: int8 + * + * @return The function returns either + * RISCV_MATH_SIZE_MISMATCH if argument constraints fail. or, + * RISCV_MATH_SUCCESS on successful completion. + * + * @details + * - Supported framework : TensorFlow Lite Micro + * - The following constrains on the arguments apply + * -# input_dims->n equals 1 + * -# ouput_dims->w is a multiple of 4 + * -# Explicit constraints(since it is for 1xN convolution) + * -## input_dims->h equals 1 + * -## output_dims->h equals 1 + * -## filter_dims->h equals 1 + *@todo Remove constraint on output_dims->w to make the function generic. + * + */ +riscv_status riscv_convolve_1_x_n_s8(const nmsis_nn_context *ctx, + const nmsis_nn_conv_params *conv_params, + const nmsis_nn_per_channel_quant_params *quant_params, + const nmsis_nn_dims *input_dims, + const q7_t *input_data, + const nmsis_nn_dims *filter_dims, + const q7_t *filter_data, + const nmsis_nn_dims *bias_dims, + const int32_t *bias_data, + const nmsis_nn_dims *output_dims, + q7_t *output_data); + +/** + * @brief Get the required additional buffer size for 1xn convolution + * + * @param[in] input_dims Input (activation) tensor dimensions. Format: [N, H, W, C_IN] + * @param[in] filter_dims Filter tensor dimensions. Format: [C_OUT, 1, WK, C_IN] where WK is the + * horizontal spatial filter dimension + * @return The function returns required buffer size(bytes) + * + */ +int32_t riscv_convolve_1_x_n_s8_get_buffer_size(const nmsis_nn_dims *input_dims, const nmsis_nn_dims *filter_dims); + +/** + * @brief Q7 version of convolution for RGB image + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimension + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * RISCV_MATH_SIZE_MISMATCH or RISCV_MATH_SUCCESS based on the outcome of size checking. + * + * This kernel is written exclusively for convolution with ch_im_in + * equals 3. This applies on the first layer of CNNs which has input + * image with RGB format. + */ + +riscv_status riscv_convolve_HWC_q7_RGB(const q7_t *Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q7_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q7_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t *Im_out, + const uint16_t dim_im_out, + q15_t *bufferA, + q7_t *bufferB); + +/** + * @brief Fast Q15 convolution function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimension + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * RISCV_MATH_SIZE_MISMATCH or RISCV_MATH_SUCCESS based on the outcome of size checking. + * + * This function is the version with full list of optimization tricks, but with + * some contraints: + * ch_im_in is multiple of 2 + * ch_im_out is multiple of 2 + */ + +riscv_status riscv_convolve_HWC_q15_fast(const q15_t *Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q15_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q15_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q15_t *Im_out, + const uint16_t dim_im_out, + q15_t *bufferA, + q7_t *bufferB); + +/** + * @brief Fast Q15 convolution function (non-sqaure shape) + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in_x input tensor dimension x + * @param[in] dim_im_in_y input tensor dimension y + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel_x filter kernel size x + * @param[in] dim_kernel_y filter kernel size y + * @param[in] padding_x padding size x + * @param[in] padding_y padding size y + * @param[in] stride_x convolution stride x + * @param[in] stride_y convolution stride y + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out_x output tensor dimension x + * @param[in] dim_im_out_y output tensor dimension y + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * RISCV_MATH_SIZE_MISMATCH or RISCV_MATH_SUCCESS based on the outcome of size checking. + * + * @details + * + * Buffer size: + * + * bufferA size: 2*ch_im_in*dim_kernel*dim_kernel + * + * bufferB size: 0 + * + * Input dimension constraints: + * + * ch_im_in is multiple of 2 + * + * ch_im_out is multipe of 2 + * + */ + +riscv_status riscv_convolve_HWC_q15_fast_nonsquare(const q15_t *Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q15_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q15_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q15_t *Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t *bufferA, + q7_t *bufferB); + +/** + * @brief Q7 depthwise separable convolution function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimension + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * RISCV_MATH_SIZE_MISMATCH or RISCV_MATH_SUCCESS based on the outcome of size checking. + * + * This function is the version with full list of optimization tricks, but with + * some contraints: + * ch_im_in is multiple of 2 + * ch_im_out is multiple of 2 + */ + +riscv_status riscv_depthwise_separable_conv_HWC_q7(const q7_t *Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q7_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q7_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t *Im_out, + const uint16_t dim_im_out, + q15_t *bufferA, + q7_t *bufferB); + +/** + * @brief Q7 depthwise separable convolution function (non-square shape) + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in_x input tensor dimension x + * @param[in] dim_im_in_y input tensor dimension y + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel_x filter kernel size x + * @param[in] dim_kernel_y filter kernel size y + * @param[in] padding_x padding sizes x + * @param[in] padding_y padding sizes y + * @param[in] stride_x convolution stride x + * @param[in] stride_y convolution stride y + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out_x output tensor dimension x + * @param[in] dim_im_out_y output tensor dimension y + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * RISCV_MATH_SIZE_MISMATCH or RISCV_MATH_SUCCESS based on the outcome of size checking. + * + * This function is the version with full list of optimization tricks, but with + * some contraints: + * ch_im_in is multiple of 2 + * ch_im_out is multiple of 2 + */ +riscv_status riscv_depthwise_separable_conv_HWC_q7_nonsquare(const q7_t *Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q7_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q7_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t *Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t *bufferA, + q7_t *bufferB); + +/** + * @brief Wrapper function to pick the right optimized s8 depthwise convolution function + * + * @param[in, out] ctx Function context (e.g. temporary buffer). Check the function + * definition file to see if an additional buffer is required. + * Optional function {API}_get_buffer_size() provides the buffer + * size if required. + * @param[in] dw_conv_params Depthwise convolution parameters (e.g. strides, dilations, pads,...) + * dw_conv_params->dilation is not used. + * Range of dw_conv_params->input_offset : [-127, 128] + * Range of dw_conv_params->output_offset : [-128, 127] + * @param[in] quant_params Per-channel quantization info. + * It contains the multiplier and shift values to be applied to each + * output channel + * @param[in] input_dims Input (activation) tensor dimensions. Format: [H, W, C_IN] + * Batch argument N is not used and assumed to be 1. + * @param[in] input_data Input (activation) data pointer. Data type: int8 + * @param[in] filter_dims Filter tensor dimensions. Format: [1, H, W, C_OUT] + * @param[in] filter_data Filter data pointer. Data type: int8 + * @param[in] bias_dims Bias tensor dimensions. Format: [C_OUT] + * @param[in] bias_data Bias data pointer. Data type: int32 + * @param[in] output_dims Output tensor dimensions. Format: [1, H, W, C_OUT] + * @param[in, out] output_data Output data pointer. Data type: int8 + * @return The function returns + * RISCV_MATH_SUCCESS - Successful completion. + * + * @details + * - Supported framework: TensorFlow Lite + * - Picks one of the the following functions + * -# riscv_depthwise_conv_s8() + * -# riscv_depthwise_conv_3x3_s8() - RISC-V CPUs with DSP extension only + * -# riscv_depthwise_conv_s8_opt() + * - q7 is used as data type eventhough it is s8 data. It is done so to be consistent with existing APIs. + * - Check details of riscv_depthwise_conv_s8_opt() for potential data that can be accessed outside of the + * boundary. + */ +riscv_status riscv_depthwise_conv_wrapper_s8(const nmsis_nn_context *ctx, + const nmsis_nn_dw_conv_params *dw_conv_params, + const nmsis_nn_per_channel_quant_params *quant_params, + const nmsis_nn_dims *input_dims, + const q7_t *input_data, + const nmsis_nn_dims *filter_dims, + const q7_t *filter_data, + const nmsis_nn_dims *bias_dims, + const int32_t *bias_data, + const nmsis_nn_dims *output_dims, + q7_t *output_data); + +/** + * @brief Get size of additional buffer required by riscv_depthwise_conv_wrapper_s8() + * + * @param[in] dw_conv_params Depthwise convolution parameters (e.g. strides, dilations, pads,...) + * dw_conv_params->dilation is not used. + * Range of dw_conv_params->input_offset : [-127, 128] + * Range of dw_conv_params->input_offset : [-128, 127] + * @param[in] input_dims Input (activation) tensor dimensions. Format: [H, W, C_IN] + * Batch argument N is not used and assumed to be 1. + * @param[in] filter_dims Filter tensor dimensions. Format: [1, H, W, C_OUT] + * @param[in] output_dims Output tensor dimensions. Format: [1, H, W, C_OUT] + * @return Size of additional memory required for optimizations in bytes. + * + */ +int32_t riscv_depthwise_conv_wrapper_s8_get_buffer_size(const nmsis_nn_dw_conv_params *dw_conv_params, + const nmsis_nn_dims *input_dims, + const nmsis_nn_dims *filter_dims, + const nmsis_nn_dims *output_dims); + +/** + * @brief Basic s8 depthwise convolution function that doesn't have any constraints on the input dimensions. + * + * @param[in, out] ctx Function context (e.g. temporary buffer). Check the function + * definition file to see if an additional buffer is required. + * Optional function {API}_get_buffer_size() provides the buffer + * size if an additional buffer is required. + * exists if additional memory is. + * @param[in] dw_conv_params Depthwise convolution parameters (e.g. strides, dilations, pads,...) + * dw_conv_params->dilation is not used. + * Range of dw_conv_params->input_offset : [-127, 128] + * Range of dw_conv_params->input_offset : [-128, 127] + * @param[in] quant_params Per-channel quantization info. + * It contains the multiplier and shift values to be applied to each + * output channel + * @param[in] input_dims Input (activation) tensor dimensions. Format: [1, H, W, C_IN] + * Batch argument N is not used. + * @param[in] input_data Input (activation) data pointer. Data type: int8 + * @param[in] filter_dims Filter tensor dimensions. Format: [1, H, W, C_OUT] + * @param[in] filter_data Filter data pointer. Data type: int8 + * @param[in] bias_dims Bias tensor dimensions. Format: [C_OUT] + * @param[in] bias_data Bias data pointer. Data type: int32 + * @param[in] output_dims Output tensor dimensions. Format: [1, H, W, C_OUT] + * @param[in, out] output_data Output data pointer. Data type: int8 + * @return The function returns RISCV_MATH_SUCCESS + * + * @details + * - Supported framework: TensorFlow Lite + * - q7 is used as data type eventhough it is s8 data. It is done so to be consistent with existing APIs. + */ +riscv_status riscv_depthwise_conv_s8(const nmsis_nn_context *ctx, + const nmsis_nn_dw_conv_params *dw_conv_params, + const nmsis_nn_per_channel_quant_params *quant_params, + const nmsis_nn_dims *input_dims, + const q7_t *input_data, + const nmsis_nn_dims *filter_dims, + const q7_t *filter_data, + const nmsis_nn_dims *bias_dims, + const int32_t *bias_data, + const nmsis_nn_dims *output_dims, + q7_t *output_data); + +/** + * @brief Optimized s8 depthwise convolution function for 3x3 kernel size with some constraints on + * the input arguments(documented below). Refer riscv_depthwise_conv_s8() for function + * argument details. + * + * @return The function returns one of the following + * RISCV_MATH_SIZE_MISMATCH - Unsupported dimension of tensors + * RISCV_MATH_ARGUMENT_ERROR - Unsupported pad size along the x axis + * RISCV_MATH_SUCCESS - Successful operation + * + * @details + * - Supported framework : TensorFlow Lite Micro + * - The following constrains on the arguments apply + * -# Number of input channel equals number of output channels + * -# Filter height and width equals 3 + * -# Padding along x is either 0 or 1. + * + */ +riscv_status riscv_depthwise_conv_3x3_s8(const nmsis_nn_context *ctx, + const nmsis_nn_dw_conv_params *dw_conv_params, + const nmsis_nn_per_channel_quant_params *quant_params, + const nmsis_nn_dims *input_dims, + const q7_t *input_data, + const nmsis_nn_dims *filter_dims, + const q7_t *filter_data, + const nmsis_nn_dims *bias_dims, + const int32_t *bias_data, + const nmsis_nn_dims *output_dims, + q7_t *output_data); + +/** + * @brief Optimized s8 depthwise convolution function with constraint that in_channel equals out_channel. + * Refer riscv_depthwise_conv_s8() for function argument details. + * + * @return The function returns one of the following + * RISCV_MATH_SIZE_MISMATCH - input channel != output channel or + * ch_mult != 1 + * RISCV_MATH_SUCCESS - Successful operation + * + * @note If number of channels is not a multiple of 4, upto 3 elements outside the boundary will be read out + * for the following if MVE optimizations(Arm Helium Technology) are used. + * - Output shift + * - Output multiplier + * - Output bias + * - kernel + * @details + * - Supported framework: TensorFlow Lite + * - The following constrains on the arguments apply + * -# Number of input channel equals number of output channels or ch_mult equals 1 + * - q7 is used as data type eventhough it is s8 data. It is done so to be consistent with existing APIs. + * - Reccomended when number of channels is 4 or greater. + * + */ +riscv_status riscv_depthwise_conv_s8_opt(const nmsis_nn_context *ctx, + const nmsis_nn_dw_conv_params *dw_conv_params, + const nmsis_nn_per_channel_quant_params *quant_params, + const nmsis_nn_dims *input_dims, + const q7_t *input_data, + const nmsis_nn_dims *filter_dims, + const q7_t *filter_data, + const nmsis_nn_dims *bias_dims, + const int32_t *bias_data, + const nmsis_nn_dims *output_dims, + q7_t *output_data); + +/** + * @brief Get the required buffer size for optimized s8 depthwise convolution + * function with constraint that in_channel equals out_channel. + * @param[in] input_dims Input (activation) tensor dimensions. Format: [1, H, W, C_IN] + * Batch argument N is not used. + * @param[in] filter_dims Filter tensor dimensions. Format: [1, H, W, C_OUT] + * @return The function returns required buffer size in bytes + * + */ +int32_t riscv_depthwise_conv_s8_opt_get_buffer_size(const nmsis_nn_dims *input_dims, const nmsis_nn_dims *filter_dims); + +/** + * @defgroup FC Fully-connected Layer Functions + * + * Collection of fully-connected and matrix multiplication functions. + * + * Fully-connected layer is basically a matrix-vector multiplication + * with bias. The matrix is the weights and the input/output vectors + * are the activation values. Supported {weight, activation} precisions + * include {8-bit, 8-bit}, {16-bit, 16-bit}, and {8-bit, 16-bit}. + * + * Here we have two types of kernel functions. The basic function + * implements the function using regular GEMV approach. The opt functions + * operates with weights in interleaved formats. + * + */ + +/** + *@brief Q7 basic fully-connected layer function + *@param[in] pV pointer to input vector + *@param[in] pM pointer to matrix weights + *@param[in] dim_vec length of the vector + *@param[in] num_of_rows number of rows in weight matrix + *@param[in] bias_shift amount of left-shift for bias + *@param[in] out_shift amount of right-shift for output + *@param[in] bias pointer to bias + *@param[in,out] pOut pointer to output vector + *@param[in,out] vec_buffer pointer to buffer space for input + *@return The function returns RISCV_MATH_SUCCESS + * + */ + +riscv_status riscv_fully_connected_q7(const q7_t *pV, + const q7_t *pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t *bias, + q7_t *pOut, + q15_t *vec_buffer); + +/** + * @brief Basic s8 Fully Connected function. + * + * @param[in, out] ctx Function context (e.g. temporary buffer). Check the function + * definition file to see if an additional buffer is required. + * Optional function {API}_get_buffer_size() provides the buffer + * size if an additional buffer is required. + * @param[in] fc_params Fully Connected layer parameters (e.g. strides, dilations, pads,...) + * Range of fc_params->input_offset : [-127, 128] + * fc_params->filter_offset : 0 + * Range of fc_params->output_offset : [-128, 127] + * @param[in] quant_params Per-tensor quantization info. + * It contains the multiplier and shift values to be applied to the output tensor. + * @param[in] input_dims Input (activation) tensor dimensions. Format: [N, H, W, C_IN] + * Input dimension is taken as Nx(H * W * C_IN) + * @param[in] input_data Input (activation) data pointer. Data type: int8 + * @param[in] filter_dims Two dimensional filter dimensions. Format: [N, C] + * N : accumulation depth and equals (H * W * C_IN) from input_dims + * C : output depth and equals C_OUT in output_dims + * H & W : Not used + * @param[in] filter_data Filter data pointer. Data type: int8 + * @param[in] bias_dims Bias tensor dimensions. Format: [C_OUT] + * N, H, W : Not used + * @param[in] bias_data Bias data pointer. Data type: int32 + * @param[in] output_dims Output tensor dimensions. Format: [N, C_OUT] + * N : Batches + * C_OUT : Output depth + * H & W : Not used. + * @param[in, out] output_data Output data pointer. Data type: int8 + * @return The function returns RISCV_MATH_SUCCESS + * + * @details + * - Supported framework: TensorFlow Lite + * - q7 is used as data type eventhough it is s8 data. It is done so to be consistent with existing APIs. + */ +riscv_status riscv_fully_connected_s8(const nmsis_nn_context *ctx, + const nmsis_nn_fc_params *fc_params, + const nmsis_nn_per_tensor_quant_params *quant_params, + const nmsis_nn_dims *input_dims, + const q7_t *input_data, + const nmsis_nn_dims *filter_dims, + const q7_t *filter_data, + const nmsis_nn_dims *bias_dims, + const int32_t *bias_data, + const nmsis_nn_dims *output_dims, + q7_t *output_data); + +/** + * @brief Get the required buffer size for S8 basic fully-connected and + * matrix multiplication layer function for TF Lite + * @param[in] filter_dims dimension of filter + * @return The function returns required buffer size in bytes + * + */ +int32_t riscv_fully_connected_s8_get_buffer_size(const nmsis_nn_dims *filter_dims); + +/** + * @brief Q7 opt fully-connected layer function + * @param[in] pV pointer to input vector + * @param[in] pM pointer to matrix weights + * @param[in] dim_vec length of the vector + * @param[in] num_of_rows number of rows in weight matrix + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias pointer to bias + * @param[in,out] pOut pointer to output vector + * @param[in,out] vec_buffer pointer to buffer space for input + * @return The function returns RISCV_MATH_SUCCESS + * + */ + +riscv_status riscv_fully_connected_q7_opt(const q7_t *pV, + const q7_t *pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t *bias, + q7_t *pOut, + q15_t *vec_buffer); + +/** + * @brief Q15 basic fully-connected layer function + * @param[in] pV pointer to input vector + * @param[in] pM pointer to matrix weights + * @param[in] dim_vec length of the vector + * @param[in] num_of_rows number of rows in weight matrix + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias pointer to bias + * @param[in,out] pOut pointer to output vector + * @param[in,out] vec_buffer pointer to buffer space for input + * @return The function returns RISCV_MATH_SUCCESS + * + */ + +riscv_status riscv_fully_connected_q15(const q15_t *pV, + const q15_t *pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, + const q15_t *bias, + q15_t *pOut, + q15_t *vec_buffer); + +/** + * @brief Q15 opt fully-connected layer function + * @param[in] pV pointer to input vector + * @param[in] pM pointer to matrix weights + * @param[in] dim_vec length of the vector + * @param[in] num_of_rows number of rows in weight matrix + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias pointer to bias + * @param[in,out] pOut pointer to output vector + * @param[in,out] vec_buffer pointer to buffer space for input + * @return The function returns RISCV_MATH_SUCCESS + * + */ + +riscv_status riscv_fully_connected_q15_opt(const q15_t *pV, + const q15_t *pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, + const q15_t *bias, + q15_t *pOut, + q15_t *vec_buffer); + +/** + * @brief Mixed Q15-Q7 fully-connected layer function + * @param[in] pV pointer to input vector + * @param[in] pM pointer to matrix weights + * @param[in] dim_vec length of the vector + * @param[in] num_of_rows number of rows in weight matrix + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias pointer to bias + * @param[in,out] pOut pointer to output vector + * @param[in,out] vec_buffer pointer to buffer space for input + * @return The function returns RISCV_MATH_SUCCESS + * + */ + +riscv_status riscv_fully_connected_mat_q7_vec_q15(const q15_t *pV, + const q7_t *pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t *bias, + q15_t *pOut, + q15_t *vec_buffer); + +/** + * @brief Mixed Q15-Q7 opt fully-connected layer function + * @param[in] pV pointer to input vector + * @param[in] pM pointer to matrix weights + * @param[in] dim_vec length of the vector + * @param[in] num_of_rows number of rows in weight matrix + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias pointer to bias + * @param[in,out] pOut pointer to output vector + * @param[in,out] vec_buffer pointer to buffer space for input + * @return The function returns RISCV_MATH_SUCCESS + * + */ + +riscv_status riscv_fully_connected_mat_q7_vec_q15_opt(const q15_t *pV, + const q7_t *pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t *bias, + q15_t *pOut, + q15_t *vec_buffer); + +/** + * @brief Matrix-Multiplication Kernels for Convolution + * + * These functions are used within convolution layer functions for + * matrix multiplication. + * + * The implementation is similar to NMSIS-DSP riscv_mat_mult functions + * with one Q7 and one Q15 operands. The Q15 operand is the im2col + * output which is always with 2 columns. + * + */ + +/** + * @brief Matrix-multiplication function for convolution + * @param[in] pA pointer to operand A + * @param[in] pInBuffer pointer to operand B, always conssists of 2 vectors + * @param[in] ch_im_out numRow of A + * @param[in] numCol_A numCol of A + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias the bias + * @param[in,out] pOut pointer to output + * @return The function returns the incremented output pointer + */ + + q7_t *riscv_nn_mat_mult_kernel_q7_q15(const q7_t * pA, + const q15_t * pInBuffer, + const uint16_t ch_im_out, + const uint16_t numCol_A, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t * bias, + q7_t * pOut); + + /** + * @brief Matrix-multiplication function for convolution + * @param[in] pA pointer to operand A, q7 type + * @param[in] pInBuffer pointer to operand B, q7 type + * @param[in] ch_im_out numRow of A + * @param[in] numCol_A numCol of A + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias the bias + * @param[in,out] pOut pointer to output + * @return The function returns the incremented output pointer + */ + q7_t *riscv_nn_mat_mult_kernel_q7(const q7_t * pA, + const q7_t * pInBuffer, + const uint16_t ch_im_out, + const uint16_t numCol_A, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t * bias, + q7_t * pOut); + + /** + * @brief Matrix-multiplication function for convolution with per-channel requantization. + * @param[in] input_a pointer to operand A + * @param[in] input_b pointer to operand B, always consists of 2 vectors. + * @param[in] output_ch number of rows of A + * @param[in] out_shift pointer to per output channel requantization shift parameter. + * @param[in] out_mult pointer to per output channel requantization multiplier parameter. + * @param[in] out_offset output tensor offset. + * @param[in] activation_min minimum value to clamp the output to. Range : int8 + * @param[in] activation_max maximum value to clamp the output to. Range : int8 + * @param[in] num_col_a number of columns of A + * @param[in] output_bias per output channel bias. Range : int32 + * @param[in,out] out_0 pointer to output + * @return The function returns one of the two + * 1. The incremented output pointer for a successful operation or + * 2. NULL if implementation is not available. + * + * @details This function does the matrix multiplication of weight matrix for all output channels + * with 2 columns from im2col and produces two elements/output_channel. The outputs are + * clamped in the range provided by activation min and max. + * Supported framework: TensorFlow Lite micro. + */ + q7_t *riscv_nn_mat_mult_kernel_s8_s16(const q7_t *input_a, + const q15_t *input_b, + const uint16_t output_ch, + const int32_t *out_shift, + const int32_t *out_mult, + const int32_t out_offset, + const int16_t activation_min, + const int16_t activation_max, + const uint16_t num_col_a, + const int32_t *const output_bias, + q7_t *out_0); + + /** + * @brief Matrix-multiplication function for convolution with per-channel requantization. + * @param[in] input_a pointer to operand A + * @param[in] input_b pointer to operand B, always consists of 2 vectors. + * @param[in] output_ch number of rows of A + * @param[in] out_shift pointer to per output channel requantization shift parameter. + * @param[in] out_mult pointer to per output channel requantization multiplier parameter. + * @param[in] out_offset output tensor offset. + * @param[in] activation_min minimum value to clamp the output to. Range : int8 + * @param[in] activation_max maximum value to clamp the output to. Range : int8 + * @param[in] num_col_a number of columns of A + * @param[in] output_bias per output channel bias. Range : int32 + * @param[in,out] out_0 pointer to output + * @return The function returns one of the two + * 1. The incremented output pointer for a successful operation or + * 2. NULL if implementation is not available. + * + * @details This function does the matrix multiplication of weight matrix for all output channels + * with 2 columns from im2col and produces two elements/output_channel. The outputs are + * clamped in the range provided by activation min and max. + * Supported framework: TensorFlow Lite micro. + */ + q7_t *riscv_nn_mat_mult_kernel_s8(const q7_t *input_a, + const q7_t *input_b, + const uint16_t output_ch, + const int32_t *out_shift, + const int32_t *out_mult, + const int32_t out_offset, + const int16_t activation_min, + const int16_t activation_max, + const uint16_t num_col_a, + const int32_t *const output_bias, + q7_t *out_0); + + /** + * @brief Matrix-multiplication of re-ordered input B with A. + * + * @details For arguments, refer riscv_nn_mat_mult_kernel_s8_s16. The re-ordering is a consequence + * of sign extension done by the SXTB16 command on input_b. The outputs are clamped in the range + * provided by activation min and max. + * * @details + * - Supported framework : TensorFlow Lite Micro + * - The following constrains on the arguments apply + * -# num_col_a is a multiple of 4 + * -# output_ch is a multiple of 2 + * + */ + q7_t *riscv_nn_mat_mult_kernel_s8_s16_reordered(const q7_t *input_a, + const q15_t *input_b, + const uint16_t output_ch, + const int32_t *out_shift, + const int32_t *out_mult, + const int32_t out_offset, + const int16_t activation_min, + const int16_t activation_max, + const uint16_t num_col_a, + const int32_t *const output_bias, + q7_t *out_0); + + /** + * @brief Matrix-multiplication of re-ordered input B with A. + * + * @details For arguments, refer riscv_nn_mat_mult_kernel_s8_s16. The re-ordering is a consequence + * of sign extension done by the SXTB16 command on input_b. The outputs are clamped in the range + * provided by activation min and max. + * * @details + * - Supported framework : TensorFlow Lite Micro + * - The following constrains on the arguments apply + * -# num_col_a is a multiple of 4 + * -# output_ch is a multiple of 2 + * + */ + q7_t *riscv_nn_mat_mult_kernel_s8_reordered(const q7_t *input_a, + const q7_t *input_b, + const uint16_t output_ch, + const int32_t *out_shift, + const int32_t *out_mult, + const int32_t out_offset, + const int16_t activation_min, + const int16_t activation_max, + const uint16_t num_col_a, + const int32_t *const output_bias, + q7_t *out_0); + + /** + * @brief Matrix-multiplication function for convolution with reordered columns + * @param[in] pA pointer to operand A + * @param[in] pInBuffer pointer to operand B, always conssists of 2 vectors + * @param[in] ch_im_out numRow of A + * @param[in] numCol_A numCol of A + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias the bias + * @param[in,out] pOut pointer to output + * @return The function returns the incremented output pointer + * + * @details This function assumes that data in pInBuffer are reordered + */ + q7_t *riscv_nn_mat_mult_kernel_q7_q15_reordered(const q7_t * pA, + const q15_t * pInBuffer, + const uint16_t ch_im_out, + const uint16_t numCol_A, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t * bias, + q7_t * pOut); + + q7_t *riscv_nn_mat_mult_kernel_q7_reordered(const q7_t * pA, + const q7_t * pInBuffer, + const uint16_t ch_im_out, + const uint16_t numCol_A, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t * bias, + q7_t * pOut); + +#ifdef __cplusplus +} +#endif + +/* + * Other functions + * These layers are typically not timing critical + * Basic implementation is supported here + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup BasicMath Basic math functions + * + * Element wise add and multiplication functions. + * + */ + +/** + * @brief s8 element wise add of two vectors + * @param[in] input_1_vect pointer to input vector 1 + * @param[in] input_2_vect pointer to input vector 2 + * @param[in] input_1_offset offset for input 1. Range: Range: -127 to 128 + * @param[in] input_1_mult multiplier for input 1 + * @param[in] input_1_shift shift for input 1 + * @param[in] input_2_offset offset for input 2. Range: Range: -127 to 128 + * @param[in] input_2_mult multiplier for input 2 + * @param[in] input_2_shift shift for input 2 + * @param[in] left_shift input left shift + * @param[in,out] output pointer to output vector + * @param[in] out_offset output offset + * @param[in] out_mult output multiplier + * @param[in] out_shift output shift + * @param[in] out_activation_min minimum value to clamp output to + * @param[in] out_activation_max maximum value to clamp output to + * @param[in] block_size number of samples + * @return The function returns RISCV_MATH_SUCCESS + */ +riscv_status riscv_elementwise_add_s8(const int8_t *input_1_vect, + const int8_t *input_2_vect, + const int32_t input_1_offset, + const int32_t input_1_mult, + const int32_t input_1_shift, + const int32_t input_2_offset, + const int32_t input_2_mult, + const int32_t input_2_shift, + const int32_t left_shift, + int8_t *output, + const int32_t out_offset, + const int32_t out_mult, + const int32_t out_shift, + const int32_t out_activation_min, + const int32_t out_activation_max, + const uint32_t block_size); + +/** + * @brief s8 element wise multiplication + * @param[in] input_1_vect pointer to input vector 1 + * @param[in] input_2_vect pointer to input vector 2 + * @param[in] input_1_offset offset for input 1. Range: Range: -127 to 128 + * @param[in] input_2_offset offset for input 2. Range: Range: -127 to 128 + * @param[in,out] output pointer to output vector + * @param[in] out_offset output offset + * @param[in] out_mult output multiplier + * @param[in] out_shift output shift + * @param[in] out_activation_min minimum value to clamp output to + * @param[in] out_activation_max maximum value to clamp output to + * @param[in] block_size number of samples + * @return The function returns RISCV_MATH_SUCCESS + * + * @details Supported framework: TensorFlow Lite micro + */ +riscv_status riscv_elementwise_mul_s8(const int8_t *input_1_vect, + const int8_t *input_2_vect, + const int32_t input_1_offset, + const int32_t input_2_offset, + int8_t *output, + const int32_t out_offset, + const int32_t out_mult, + const int32_t out_shift, + const int32_t out_activation_min, + const int32_t out_activation_max, + const uint32_t block_size); +/** + * @defgroup Acti Activation Functions + * + * Perform activation layers, including ReLU (Rectified Linear Unit), + * sigmoid and tanh + * + */ + +/** + * @brief Q7 RELU function + * @param[in,out] data pointer to input + * @param[in] size number of elements + * @return none. + */ + +void riscv_relu_q7(q7_t *data, uint16_t size); + +/** + * @brief s8 ReLU6 function + * @param[in,out] data pointer to input + * @param[in] size number of elements + */ + +void riscv_relu6_s8(q7_t *data, uint16_t size); + +/** + * @brief Q15 RELU function + * @param[in,out] data pointer to input + * @param[in] size number of elements + * @return none. + */ + +void riscv_relu_q15(q15_t *data, uint16_t size); + +/** + * @brief Q7 neural network activation function using direct table look-up + * @param[in,out] data pointer to input + * @param[in] size number of elements + * @param[in] int_width bit-width of the integer part, assume to be smaller than 3 + * @param[in] type type of activation functions + * @return none. + */ + +void riscv_nn_activations_direct_q7(q7_t *data, uint16_t size, uint16_t int_width, riscv_nn_activation_type type); + +/** + * @brief Q15 neural network activation function using direct table look-up + * @param[in,out] data pointer to input + * @param[in] size number of elements + * @param[in] int_width bit-width of the integer part, assume to be smaller than 3 + * @param[in] type type of activation functions + * @return none. + * + * @details + * + * This is the direct table look-up approach. + * + * Assume here the integer part of the fixed-point is <= 3. + * More than 3 just not making much sense, makes no difference with + * saturation followed by any of these activation functions. + */ + +void riscv_nn_activations_direct_q15(q15_t *data, uint16_t size, uint16_t int_width, riscv_nn_activation_type type); + +/** + * @defgroup Pooling Pooling Functions + * + * Perform pooling functions, including max pooling and average pooling + * + */ + +/** + * @brief Q7 max pooling function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimension + * @param[in] ch_im_in number of input tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] Im_out pointer to output tensor + * @return none. + * + */ + +void riscv_maxpool_q7_HWC(q7_t *Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const uint16_t dim_im_out, + q7_t *bufferA, + q7_t *Im_out); + +/** + * @brief Q7 average pooling function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimension + * @param[in] ch_im_in number of input tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] Im_out pointer to output tensor + * @return none. + * + */ + +void riscv_avepool_q7_HWC(q7_t *Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const uint16_t dim_im_out, + q7_t *bufferA, + q7_t *Im_out); + +/** + * @brief s8 average pooling function. + * + * @param[in, out] ctx Function context (e.g. temporary buffer). Check the function + * definition file to see if an additional buffer is required. + * Optional function {API}_get_buffer_size() provides the buffer + * size if an additional buffer is required. + * @param[in] pool_params Pooling parameters + * @param[in] input_dims Input (activation) tensor dimensions. Format: [H, W, C_IN] + * Argument 'N' is not used. + * @param[in] input_data Input (activation) data pointer. Data type: int8 + * @param[in] filter_dims Filter tensor dimensions. Format: [H, W] + * Argument N and C are not used. + * @param[in] output_dims Output tensor dimensions. Format: [H, W, C_OUT] + * Argument N is not used. + * C_OUT equals C_IN. + * @param[in, out] output_data Output data pointer. Data type: int8 + * @return The function returns + * RISCV_MATH_SUCCESS - Successful operation + * + * @details + * - Supported Framework: TensorFlow Lite + * + */ +riscv_status riscv_avgpool_s8(const nmsis_nn_context *ctx, + const nmsis_nn_pool_params *pool_params, + const nmsis_nn_dims *input_dims, + const q7_t *input_data, + const nmsis_nn_dims *filter_dims, + const nmsis_nn_dims *output_dims, + q7_t *output_data); + +/** + * @brief Get the required buffer size for S8 average pooling function + * @param[in] dim_dst_width output tensor dimension + * @param[in] ch_src number of input tensor channels + * @return The function returns required buffer size in bytes + * + */ +int32_t riscv_avgpool_s8_get_buffer_size(const int dim_dst_width, const int ch_src); + +/** + * @brief s8 max pooling function. + * + * @param[in, out] ctx Function context (e.g. temporary buffer). Check the function + * definition file to see if an additional buffer is required. + * Optional function {API}_get_buffer_size() provides the buffer + * size if an additional buffer is required. + * @param[in] pool_params Pooling parameters + * @param[in] input_dims Input (activation) tensor dimensions. Format: [H, W, C_IN] + * Argument 'N' is not used. + * @param[in] input_data Input (activation) data pointer. Data type: int8 + * @param[in] filter_dims Filter tensor dimensions. Format: [H, W] + * Argument N and C are not used. + * @param[in] output_dims Output tensor dimensions. Format: [H, W, C_OUT] + * Argument N is not used. + * C_OUT equals C_IN. + * @param[in, out] output_data Output data pointer. Data type: int8 + * @return The function returns + * RISCV_MATH_SUCCESS - Successful operation + * + * @details + * - Supported Framework: TensorFlow Lite + * + */ +riscv_status riscv_max_pool_s8(const nmsis_nn_context *ctx, + const nmsis_nn_pool_params *pool_params, + const nmsis_nn_dims *input_dims, + const q7_t *input_data, + const nmsis_nn_dims *filter_dims, + const nmsis_nn_dims *output_dims, + q7_t *output_data); +/** + * @defgroup Softmax Softmax Functions + * + * EXP(2) based softmax functions. + * + */ + +/** + * @brief Q7 softmax function + * @param[in] vec_in pointer to input vector + * @param[in] dim_vec input vector dimension + * @param[out] p_out pointer to output vector + * + * @note This function is an optimized version which is not bit-accurate with + * TensorFlow Lite's kernel + * + */ + +void riscv_softmax_q7(const q7_t *vec_in, const uint16_t dim_vec, q7_t *p_out); + +/** + * @brief Q7 softmax function with batch parameter + * @param[in] vec_in pointer to input vector + * @param[in] nb_batches number of batches + * @param[in] dim_vec input vector dimension + * @param[out] p_out pointer to output vector + * @return none. + * + * @note This function is an optimized version which is not bit-accurate with + * TensorFlow Lite's kernel + * + */ + +void riscv_softmax_with_batch_q7(const q7_t *vec_in, const uint16_t nb_batches, const uint16_t dim_vec, q7_t *p_out); +/** + * @brief Q15 softmax function + * @param[in] vec_in pointer to input vector + * @param[in] dim_vec input vector dimension + * @param[out] p_out pointer to output vector + * @return none. + * + * @note This function is an optimized version which is not bit-accurate with + * TensorFlow Lite's kernel + * + */ + +void riscv_softmax_q15(const q15_t *vec_in, const uint16_t dim_vec, q15_t *p_out); + +/** + * @brief S8 softmax function + * @param[in] input Pointer to the input tensor + * @param[in] num_rows Number of rows in the input tensor + * @param[in] row_size Number of elements in each input row + * @param[in] mult Input quantization multiplier + * @param[in] shift Input quantization shift within the range [0, 31] + * @param[in] diff_min Minimum difference with max in row. Used to check if + * the quantized exponential operation can be performed + * @param[out] output Pointer to the output tensor + * + * @note Supported framework: TensorFlow Lite micro (bit-accurate) + * + */ + +void riscv_softmax_s8(const int8_t *input, + const int32_t num_rows, + const int32_t row_size, + const int32_t mult, + const int32_t shift, + const int32_t diff_min, + int8_t *output); + +/** + * @brief U8 softmax function + * @param[in] input Pointer to the input tensor + * @param[in] num_rows Number of rows in the input tensor + * @param[in] row_size Number of elements in each input row + * @param[in] mult Input quantization multiplier + * @param[in] shift Input quantization shift within the range [0, 31] + * @param[in] diff_min Minimum difference with max in row. Used to check if + * the quantized exponential operation can be performed + * @param[out] output Pointer to the output tensor + * + * @note Supported framework: TensorFlow Lite micro (bit-accurate) + * + */ + +void riscv_softmax_u8(const uint8_t *input, + const int32_t num_rows, + const int32_t row_size, + const int32_t mult, + const int32_t shift, + const int32_t diff_min, + uint8_t *output); + +/** + * @brief uint8 depthwise convolution function with asymmetric quantization + * Unless specified otherwise, arguments are mandatory. + * + * @param[in] input Pointer to input tensor + * @param[in] input_x Width of input tensor + * @param[in] input_y Height of input tensor + * @param[in] input_ch Channels in input tensor + * @param[in] kernel Pointer to kernel weights + * @param[in] kernel_x Width of kernel + * @param[in] kernel_y Height of kernel + * @param[in] ch_mult Number of channel multiplier + * @param[in] pad_x Padding sizes x + * @param[in] pad_y Padding sizes y + * @param[in] stride_x stride along the width + * @param[in] stride_y stride along the height + * @param[in] dilation_x Dilation along width. Not used and intended for future enhancement. + * @param[in] dilation_y Dilation along height. Not used and intended for future enhancement. + * @param[in] bias Pointer to optional bias values. If no bias is + * availble, NULL is expected + * @param[in] input_offset Input tensor zero offset + * @param[in] filter_offset Kernel tensor zero offset + * @param[in] output_offset Output tensor zero offset + * @param[in,out] output Pointer to output tensor + * @param[in] output_x Width of output tensor + * @param[in] output_y Height of output tensor + * @param[in] output_activation_min Minimum value to clamp the output to. Range : {0, 255} + * @param[in] output_activation_max Minimum value to clamp the output to. Range : {0, 255} + * @param[in] out_shift Amount of right-shift for output + * @param[in] out_mult Output multiplier for requantization + * @return The function returns the following + * RISCV_MATH_SUCCESS - Successful operation + * + */ +riscv_status riscv_depthwise_conv_u8_basic_ver1(const uint8_t *input, + const uint16_t input_x, + const uint16_t input_y, + const uint16_t input_ch, + const uint8_t *kernel, + const uint16_t kernel_x, + const uint16_t kernel_y, + const int16_t ch_mult, + const int16_t pad_x, + const int16_t pad_y, + const int16_t stride_x, + const int16_t stride_y, + const int16_t dilation_x, + const int16_t dilation_y, + const int32_t *bias, + const int32_t input_offset, + const int32_t filter_offset, + const int32_t output_offset, + uint8_t *output, + const uint16_t output_x, + const uint16_t output_y, + const int32_t output_activation_min, + const int32_t output_activation_max, + const int32_t out_shift, + const int32_t out_mult); + +/** + * @defgroup Reshape Reshape Functions + * + */ + +/** + * @brief Reshape a s8 vector into another with different shape + * @param[in] input points to the s8 input vector + * @param[out] output points to the s8 output vector + * @param[in] total_size total size of the input and output vectors in bytes + * + * @note The output is expected to be in a memory area that does not overlap with the input's + * + */ +void riscv_reshape_s8(const int8_t *input, int8_t *output, const uint32_t total_size); + +/** + * @defgroup Concatenation Concatenation Functions + * + */ + +/** + * @brief int8/uint8 concatenation function to be used for concatenating N-tensors along the X axis + * This function should be called for each input tensor to concatenate. The argument offset_x + * will be used to store the input tensor in the correct position in the output tensor + * + * i.e. offset_x = 0 + * for(i = 0 i < num_input_tensors; ++i) + * { + * riscv_concatenation_s8_x(&input[i], ..., &output, ..., ..., offset_x) + * offset_x += input_x[i] + * } + * + * This function assumes that the output tensor has: + * -# The same height of the input tensor + * -# The same number of channels of the input tensor + * -# The same batch size of the input tensor + * + * Unless specified otherwise, arguments are mandatory. + * + * @note This function, data layout independent, can be used to concatenate either int8 or uint8 tensors because it + * does not involve any arithmetic operation + * + * @param[in] input Pointer to input tensor + * @param[in] input_x Width of input tensor + * @param[in] input_y Height of input tensor + * @param[in] input_z Channels in input tensor + * @param[in] input_w Batch size in input tensor + * @param[out] output Pointer to output tensor + * @param[in] output_x Width of output tensor + * @param[in] offset_x The offset (in number of elements) on the X axis to start concatenating the input tensor + * It is user responsibility to provide the correct value + * + * Input constraints + * offset_x is less than output_x + * + */ +void riscv_concatenation_s8_x(const int8_t *input, + const uint16_t input_x, + const uint16_t input_y, + const uint16_t input_z, + const uint16_t input_w, + int8_t *output, + const uint16_t output_x, + const uint32_t offset_x); + +/** + * @brief int8/uint8 concatenation function to be used for concatenating N-tensors along the Y axis + * This function should be called for each input tensor to concatenate. The argument offset_y + * will be used to store the input tensor in the correct position in the output tensor + * + * i.e. offset_y = 0 + * for(i = 0 i < num_input_tensors; ++i) + * { + * riscv_concatenation_s8_y(&input[i], ..., &output, ..., ..., offset_y) + * offset_y += input_y[i] + * } + * + * This function assumes that the output tensor has: + * -# The same width of the input tensor + * -# The same number of channels of the input tensor + * -# The same batch size of the input tensor + * + * Unless specified otherwise, arguments are mandatory. + * + * @note This function, data layout independent, can be used to concatenate either int8 or uint8 tensors because it + * does not involve any arithmetic operation + * + * @param[in] input Pointer to input tensor + * @param[in] input_x Width of input tensor + * @param[in] input_y Height of input tensor + * @param[in] input_z Channels in input tensor + * @param[in] input_w Batch size in input tensor + * @param[out] output Pointer to output tensor + * @param[in] output_y Height of output tensor + * @param[in] offset_y The offset on the Y axis to start concatenating the input tensor + * It is user responsibility to provide the correct value + * + * Input constraints + * offset_y is less than output_y + * + */ +void riscv_concatenation_s8_y(const int8_t *input, + const uint16_t input_x, + const uint16_t input_y, + const uint16_t input_z, + const uint16_t input_w, + int8_t *output, + const uint16_t output_y, + const uint32_t offset_y); + +/** + * @brief int8/uint8 concatenation function to be used for concatenating N-tensors along the Z axis + * This function should be called for each input tensor to concatenate. The argument offset_z + * will be used to store the input tensor in the correct position in the output tensor + * + * i.e. offset_z = 0 + * for(i = 0 i < num_input_tensors; ++i) + * { + * riscv_concatenation_s8_z(&input[i], ..., &output, ..., ..., offset_z) + * offset_z += input_z[i] + * } + * + * This function assumes that the output tensor has: + * -# The same width of the input tensor + * -# The same height of the input tensor + * -# The same batch size of the input tensor + * + * Unless specified otherwise, arguments are mandatory. + * + * @note This function, data layout independent, can be used to concatenate either int8 or uint8 tensors because it + * does not involve any arithmetic operation + * + * @param[in] input Pointer to input tensor + * @param[in] input_x Width of input tensor + * @param[in] input_y Height of input tensor + * @param[in] input_z Channels in input tensor + * @param[in] input_w Batch size in input tensor + * @param[out] output Pointer to output tensor + * @param[in] output_z Channels in output tensor + * @param[in] offset_z The offset on the Z axis to start concatenating the input tensor + * It is user responsibility to provide the correct value + * + * Input constraints + * offset_z is less than output_z + * + */ +void riscv_concatenation_s8_z(const int8_t *input, + const uint16_t input_x, + const uint16_t input_y, + const uint16_t input_z, + const uint16_t input_w, + int8_t *output, + const uint16_t output_z, + const uint32_t offset_z); + +/** + * @brief int8/uint8 concatenation function to be used for concatenating N-tensors along the W axis (Batch size) + * This function should be called for each input tensor to concatenate. The argument offset_w + * will be used to store the input tensor in the correct position in the output tensor + * + * i.e. offset_w = 0 + * for(i = 0 i < num_input_tensors; ++i) + * { + * riscv_concatenation_s8_w(&input[i], ..., &output, ..., ..., offset_w) + * offset_w += input_w[i] + * } + * + * This function assumes that the output tensor has: + * -# The same width of the input tensor + * -# The same height of the input tensor + * -# The same number o channels of the input tensor + * + * Unless specified otherwise, arguments are mandatory. + * + * @note This function, data layout independent, can be used to concatenate either int8 or uint8 tensors because it + * does not involve any arithmetic operation + * + * @param[in] input Pointer to input tensor + * @param[in] input_x Width of input tensor + * @param[in] input_y Height of input tensor + * @param[in] input_z Channels in input tensor + * @param[in] input_w Batch size in input tensor + * @param[out] output Pointer to output tensor + * @param[in] offset_w The offset on the W axis to start concatenating the input tensor + * It is user responsibility to provide the correct value + * + */ +void riscv_concatenation_s8_w(const int8_t *input, + const uint16_t input_x, + const uint16_t input_y, + const uint16_t input_z, + const uint16_t input_w, + int8_t *output, + const uint32_t offset_w); +/** + * @defgroup SVDF SVDF Layer Functions + * + */ + +/** + * @brief s8 SVDF function + * + * @param[in] input_ctx Temporary scratch buffer + * @param[in] output_ctx Temporary output scratch buffer + * @param[in] svdf_params SVDF Parameters + * Range of svdf_params->input_offset : [-128, 127] + * Range of svdf_params->output_offset : [-128, 127] + * @param[in] input_quant_params Input quantization parameters + * @param[in] output_quant_params Output quantization parameters + * @param[in] input_dims Input tensor dimensions + * @param[in] input_data Pointer to input tensor + * @param[in] state_dims State tensor dimensions + * @param[in] state_data Pointer to state tensor + * @param[in] weights_feature_dims Weights (feature) tensor dimensions + * @param[in] weights_feature_data Pointer to the weights (feature) tensor + * @param[in] weights_time_dims Weights (time) tensor dimensions + * @param[in] weights_time_data Pointer to the weights (time) tensor + * @param[in] bias_dims Bias tensor dimensions + * @param[in] bias_data Pointer to bias tensor + * @param[in] output_dims Output tensor dimensions + * @param[out] output_data Pointer to the output tensor + * + * @return The function returns RISCV_MATH_SUCCESS + * + * @details + * 1. Supported framework: TensorFlow Lite micro + * 2. q7 is used as data type eventhough it is s8 data. It is done so to be consistent with existing APIs. + * + */ +riscv_status riscv_svdf_s8(const nmsis_nn_context *input_ctx, + const nmsis_nn_context *output_ctx, + const nmsis_nn_svdf_params *svdf_params, + const nmsis_nn_per_tensor_quant_params *input_quant_params, + const nmsis_nn_per_tensor_quant_params *output_quant_params, + const nmsis_nn_dims *input_dims, + const q7_t *input_data, + const nmsis_nn_dims *state_dims, + q15_t *state_data, + const nmsis_nn_dims *weights_feature_dims, + const q7_t *weights_feature_data, + const nmsis_nn_dims *weights_time_dims, + const q15_t *weights_time_data, + const nmsis_nn_dims *bias_dims, + const q31_t *bias_data, + const nmsis_nn_dims *output_dims, + q7_t *output_data); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/components/nmsis/nn/inc/riscv_nnsupportfunctions.h b/components/nmsis/nn/inc/riscv_nnsupportfunctions.h new file mode 100644 index 00000000..27e8c67b --- /dev/null +++ b/components/nmsis/nn/inc/riscv_nnsupportfunctions.h @@ -0,0 +1,902 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_nnsupportfunctions.h + * Description: Public header file of support functions for NMSIS NN Library + * + * $Date: 15. April 2021 + * $Revision: V.5.5.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ + +#ifndef _RISCV_NNSUPPORTFUNCTIONS_H_ +#define _RISCV_NNSUPPORTFUNCTIONS_H_ + +#include "riscv_common_tables.h" +#include "riscv_math_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define LEFT_SHIFT(_shift) (_shift > 0 ? _shift : 0) +#define RIGHT_SHIFT(_shift) (_shift > 0 ? 0 : -_shift) +#define MASK_IF_ZERO(x) (x) == 0 ? ~0 : 0 +#define MASK_IF_NON_ZERO(x) (x) != 0 ? ~0 : 0 +#define SELECT_USING_MASK(mask, a, b) ((mask) & (a)) ^ (~(mask) & (b)) + +#define MAX(A, B) ((A) > (B) ? (A) : (B)) +#define MIN(A, B) ((A) < (B) ? (A) : (B)) +#define CLAMP(x, h, l) MAX(MIN((x), (h)), (l)) + +/** + * @brief Union for SIMD access of q31/q15/q7 types + */ +union riscv_nnword +{ + q31_t word; + /**< q31 type */ + q15_t half_words[2]; + /**< q15 type */ + q7_t bytes[4]; + /**< q7 type */ +}; + +/** + * @brief Union for data type long long + */ +struct riscv_nn_double +{ + uint32_t low; + int32_t high; +}; + +union riscv_nn_long_long +{ + int64_t long_long; + struct riscv_nn_double word; +}; + +/** + * @defgroup nndata_convert Neural Network Data Conversion Functions + * + * Perform data type conversion in-between neural network operations + * + */ + +/** + * @brief Converts the elements of the q7 vector to q15 vector without left-shift + * @param[in] *pSrc points to the q7 input vector + * @param[out] *pDst points to the q15 output vector + * @param[in] blockSize length of the input vector + * + */ +void riscv_q7_to_q15_no_shift(const q7_t *pSrc, q15_t *pDst, uint32_t blockSize); + +void riscv_q7_to_q7_no_shift(const q7_t * pSrc, q7_t * pDst, uint32_t blockSize); + +/** + * @brief Non-saturating addition of elements of a q7 vector + * @param[in] *input Pointer to the q7 input vector + * @param[out] *output Pointer to the q31 output variable. + * @param[in] block_size length of the input vector + * \par Description: + * + * 2^24 samples can be added without saturating the result. + * + * The equation used for the conversion process is: + * + * 
+ *  sum = input[0] + input[1] + .. + input[block_size -1]
+ *
+ * + * */ +void riscv_nn_add_q7(const q7_t *input, q31_t *output, uint32_t block_size); + +/** + * @brief Converts the elements of the q7 vector to reordered q15 vector without left-shift + * @param[in] *pSrc points to the q7 input vector + * @param[out] *pDst points to the q15 output vector + * @param[in] blockSize length of the input vector + * @return none. + * + */ +void riscv_q7_to_q15_reordered_no_shift(const q7_t *pSrc, q15_t *pDst, uint32_t blockSize); + +void riscv_q7_to_q7_reordered_no_shift(const q7_t * pSrc, q7_t * pDst, uint32_t blockSize); + +/** + * @brief Converts the elements from a q7 vector to a q15 vector with an added offset + * @param[in] src pointer to the q7 input vector + * @param[out] dst pointer to the q15 output vector + * @param[in] block_size length of the input vector + * @param[in] offset q7 offset to be added to each input vector element. + * + * \par Description: + * + * The equation used for the conversion process is: + * + * 
+ *  dst[n] = (q15_t) src[n] + offset;   0 <= n < block_size.
+ *
+ * + */ +void riscv_q7_to_q15_with_offset(const q7_t *src, q15_t *dst, uint32_t block_size, q15_t offset); + +/** + * @brief Converts the elements of the q7 vector to reordered q15 vector with an added offset + * @param[in] src pointer to the q7 input vector + * @param[out] dst pointer to the q15 output vector + * @param[in] block_size length of the input vector + * @param[in] offset offset to be added to each input vector element. + * @return none. + * + * @details This function does the q7 to q15 expansion with re-ordering of bytes. Re-ordering is a consequence of + * the sign extension intrinsic(DSP extension). The tail (i.e., last (N % 4) elements) retains its + * original order. + * + */ +void riscv_q7_to_q15_reordered_with_offset(const q7_t *src, q15_t *dst, uint32_t block_size, q15_t offset); + +/** + * @brief Converts the elements from a q7 vector and accumulate to a q15 vector + * @param[in] *src points to the q7 input vector + * @param[out] *dst points to the q15 output vector + * @param[in] block_size length of the input vector + * + * \par Description: + * + * The equation used for the conversion process is: + * + * 
+ *  dst[n] += (q15_t) src[n] ;   0 <= n < block_size.
+ *
+ * + */ +void riscv_nn_accumulate_q7_to_q15(q15_t *dst, const q7_t *src, uint32_t block_size); + +/** + * @brief Converts the elements from a q7 vector and accumulate to a q7 vector + * @param[in] *src points to the q7 input vector + * @param[out] *dst points to the q7 output vector + * @param[in] block_size length of the input vector + * + * \par Description: + * + * The equation used for the conversion process is: + * + * 
+ *  dst[n] += (q7_t) src[n] ;   0 <= n < block_size.
+ *
+ * + */ +void riscv_nn_accumulate_q7_to_q7(q7_t *dst, const q7_t *src, uint32_t block_size); + +/** + * @brief Depthwise conv on an im2col buffer where the input channel equals output channel. + * @param[in] row pointer to row + * @param[in] col pointer to im2col buffer, always consists of 2 columns. + * @param[in] num_ch number of channels + * @param[in] out_shift pointer to per output channel requantization shift parameter. + * @param[in] out_mult pointer to per output channel requantization multiplier parameter. + * @param[in] out_offset output tensor offset. + * @param[in] activation_min minimum value to clamp the output to. Range : int8 + * @param[in] activation_max maximum value to clamp the output to. Range : int8 + * @param[in] kernel_size number of elements in one column. + * @param[in] output_bias per output channel bias. Range : int32 + * @param[out] out pointer to output + * @return The function returns one of the two + * 1. The incremented output pointer for a successful operation or + * 2. NULL if implementation is not available. + * + * @details Supported framework: TensorFlow Lite micro. + */ +q7_t *riscv_nn_depthwise_conv_s8_core(const q7_t *row, + const q15_t *col, + const uint16_t num_ch, + const int32_t *out_shift, + const int32_t *out_mult, + const int32_t out_offset, + const int32_t activation_min, + const int32_t activation_max, + const uint16_t kernel_size, + const int32_t *const output_bias, + q7_t *out); + +/** + * @brief General Matrix-multiplication function with per-channel requantization. + * @param[in] input_row pointer to row operand + * @param[in] input_col pointer to col operand + * @param[in] output_ch number of rows of input_row + * @param[in] col_batches number of column batches. Range: 1 to 4 + * @param[in] output_shift pointer to per output channel requantization shift parameter. + * @param[in] output_mult pointer to per output channel requantization multiplier parameter. + * @param[in] out_offset output tensor offset. + * @param[in] col_offset input tensor(col) offset. + * @param[in] row_offset kernel offset(row). Not used. + * @param[in] out_activation_min minimum value to clamp the output to. Range : int8 + * @param[in] out_activation_max maximum value to clamp the output to. Range : int8 + * @param[in] row_len number of elements in each row + * @param[in] bias per output channel bias. Range : int32 + * @param[in,out] out pointer to output + * @return The function returns one of the two + * 1. The incremented output pointer for a successful operation or + * 2. NULL if implementation is not available. + * + * @details Supported framework: TensorFlow Lite + */ +q7_t *riscv_nn_mat_mult_s8(const q7_t *input_row, + const q7_t *input_col, + const uint16_t output_ch, + const uint16_t col_batches, + const int32_t *output_shift, + const int32_t *output_mult, + const int32_t out_offset, + const int32_t col_offset, + const int32_t row_offset, + const int16_t out_activation_min, + const int16_t out_activation_max, + const uint16_t row_len, + const int32_t *const bias, + q7_t *out); + +/** + * @brief General Matrix-multiplication without requantization for one row & one column + * @param[in] row_elements number of row elements + * @param[in] row_base pointer to row operand + * @param[in] col_base pointer to col operand + * @param[out] sum_col pointer to store sum of column elements + * @param[out] output pointer to store result of multiply-accumulate + * @return The function returns the multiply-accumulated result of the row by column. + * + * @details Pseudo-code + * *output = 0 + * sum_col = 0 + * for (i = 0; i < row_elements; i++) + * *output += row_base[i] * col_base[i] + * sum_col += col_base[i] + * + */ +riscv_status riscv_nn_mat_mul_core_1x_s8(int32_t row_elements, + const int8_t *row_base, + const int8_t *col_base, + int32_t *const sum_col, + int32_t *const output); + +/** + * @brief General Matrix-multiplication without requantization for four rows and one column + * @param[in] row_elements number of row elements + * @param[in] offset offset between rows. Can be the same as row_elements. + * For e.g, in a 1x1 conv scenario with stride as 1. + * @param[in] row_base pointer to row operand + * @param[in] col_base pointer to col operand + * @param[out] sum_col pointer to store sum of column elements + * @param[out] output pointer to store result(4 int32's) of multiply-accumulate + * @return The function returns the multiply-accumulated result of the row by column + * + * @details Pseudo-code + * output[0] = 0 + * .. + * output[3] = 0 + * sum_col = 0 + * for (i = 0; i < row_elements; i++) + * output[0] += row_base[i] * col_base[i] + * .. + * output[3] += row_base[i + (row_elements * 3)] * col_base[i] + * sum_col += col_base[i] + */ +riscv_status riscv_nn_mat_mul_core_4x_s8(const int32_t row_elements, + const int32_t offset, + const int8_t *row_base, + const int8_t *col_base, + int32_t *const sum_col, + int32_t *const output); + +/** + * @brief General Matrix-multiplication function with per-channel requantization. + * This function assumes: + * - LHS input matrix NOT transposed (nt) + * - RHS input matrix transposed (t) + * + * @note This operation also performs the broadcast bias addition before the requantization + * + * @param[in] lhs Pointer to the LHS input matrix + * @param[in] rhs Pointer to the RHS input matrix + * @param[in] bias Pointer to the bias vector. The length of this vector is equal to the number of + * output columns (or RHS input rows) + * @param[out] dst Pointer to the output matrix with "m" rows and "n" columns + * @param[in] dst_multipliers Pointer to the multipliers vector needed for the per-channel requantization. + * The length of this vector is equal to the number of output columns (or RHS input + * rows) + * @param[in] dst_shifts Pointer to the shifts vector needed for the per-channel requantization. The length + * of this vector is equal to the number of output columns (or RHS input rows) + * @param[in] lhs_rows Number of LHS input rows + * @param[in] rhs_rows Number of RHS input rows + * @param[in] rhs_cols Number of LHS/RHS input columns + * @param[in] lhs_offset Offset to be applied to the LHS input value + * @param[in] dst_offset Offset to be applied the output result + * @param[in] activation_min Minimum value to clamp down the output. Range : int8 + * @param[in] activation_max Maximum value to clamp up the output. Range : int8 + * + * @return The function returns RISCV_MATH_SUCCESS + * + */ +riscv_status riscv_nn_mat_mult_nt_t_s8(const q7_t *lhs, + const q7_t *rhs, + const q31_t *bias, + q7_t *dst, + const int32_t *dst_multipliers, + const int32_t *dst_shifts, + const int32_t lhs_rows, + const int32_t rhs_rows, + const int32_t rhs_cols, + const int32_t lhs_offset, + const int32_t dst_offset, + const int32_t activation_min, + const int32_t activation_max); + +/** + * @brief s8 Vector by Matrix (transposed) multiplication + * + * @param[in] lhs Input left-hand side vector + * @param[in] rhs Input right-hand side matrix (transposed) + * @param[in] bias Input bias + * @param[out] dst Output vector + * @param[in] lhs_offset Offset to be added to the input values of the left-hand side vector. + * Range: -127 to 128 + * @param[in] rhs_offset Not used + * @param[in] dst_offset Offset to be added to the output values. Range: -127 to 128 + * @param[in] dst_multiplier Output multiplier + * @param[in] dst_shift Output shift + * @param[in] rhs_cols Number of columns in the right-hand side input matrix + * @param[in] rhs_rows Number of rows in the right-hand side input matrix + * @param[in] activation_min Minimum value to clamp the output to. Range: int8 + * @param[in] activation_max Maximum value to clamp the output to. Range: int8 + * + * @return The function returns RISCV_MATH_SUCCESS + * + */ +riscv_status riscv_nn_vec_mat_mult_t_s8(const q7_t *lhs, + const q7_t *rhs, + const q31_t *bias, + q7_t *dst, + const int32_t lhs_offset, + const int32_t rhs_offset, + const int32_t dst_offset, + const int32_t dst_multiplier, + const int32_t dst_shift, + const int32_t rhs_cols, + const int32_t rhs_rows, + const int32_t activation_min, + const int32_t activation_max); + +/** + * @brief s8 Vector by Matrix (transposed) multiplication with s16 output + * + * @param[in] lhs Input left-hand side vector + * @param[in] rhs Input right-hand side matrix (transposed) + * @param[out] dst Output vector + * @param[in] lhs_offset Offset to be added to the input values of the left-hand side + * vector. Range: -127 to 128 + * @param[in] rhs_offset Not used + * @param[in] scatter_offset Address offset for dst. First output is stored at 'dst', the + * second at 'dst + scatter_offset' and so on. + * @param[in] dst_multiplier Output multiplier + * @param[in] dst_shift Output shift + * @param[in] rhs_cols Number of columns in the right-hand side input matrix + * @param[in] rhs_rows Number of rows in the right-hand side input matrix + * @param[in] activation_min Minimum value to clamp the output to. Range: int16 + * @param[in] activation_max Maximum value to clamp the output to. Range: int16 + * + * @return The function returns RISCV_MATH_SUCCESS + * + */ +riscv_status riscv_nn_vec_mat_mult_t_svdf_s8(const q7_t *lhs, + const q7_t *rhs, + q15_t *dst, + const int32_t lhs_offset, + const int32_t rhs_offset, + const int32_t scatter_offset, + const int32_t dst_multiplier, + const int32_t dst_shift, + const int32_t rhs_cols, + const int32_t rhs_rows, + const int32_t activation_min, + const int32_t activation_max); + +/** + * @brief Depthwise convolution of transposed rhs matrix with 4 lhs matrices. To be used in padded cases where + * the padding is -lhs_offset(Range: int8). Dimensions are the same for lhs and rhs. + * + * @param[in] lhs Input left-hand side matrix + * @param[in] rhs Input right-hand side matrix (transposed) + * @param[in] lhs_offset LHS matrix offset(input offset). Range: -127 to 128 + * @param[in] num_ch Number of channels in LHS/RHS + * @param[in] out_shift Per channel output shift. Length of vector is equal to number of channels + * @param[in] out_mult Per channel output multiplier. Length of vector is equal to number of channels + * @param[in] out_offset Offset to be added to the output values. Range: -127 to 128 + * @param[in] activation_min Minimum value to clamp the output to. Range: int8 + * @param[in] activation_max Maximum value to clamp the output to. Range: int8 + * @param[in] row_x_col (row_dimension * col_dimension) of LHS/RHS matrix + * @param[in] output_bias Per channel output bias. Length of vector is equal to number of channels + * @param[in] out Output pointer + * + * @return The function returns one of the two + * - Updated output pointer if an implementation is available + * - NULL if no implementation is available. + * + * @note If number of channels is not a multiple of 4, upto 3 elements outside the boundary will be read + * out for the following. + * - Output shift + * - Output multiplier + * - Output bias + * - rhs + */ +q7_t *riscv_nn_depthwise_conv_nt_t_padded_s8(const q7_t *lhs, + const q7_t *rhs, + const int32_t lhs_offset, + const uint16_t num_ch, + const int32_t *out_shift, + const int32_t *out_mult, + const int32_t out_offset, + const int32_t activation_min, + const int32_t activation_max, + const uint16_t row_x_col, + const int32_t *const output_bias, + q7_t *out); + +/** + * @brief Depthwise convolution of transposed rhs matrix with 4 lhs matrices. To be used in non-padded cases. + * Dimensions are the same for lhs and rhs. + * + * @param[in] lhs Input left-hand side matrix + * @param[in] rhs Input right-hand side matrix (transposed) + * @param[in] lhs_offset LHS matrix offset(input offset). Range: -127 to 128 + * @param[in] num_ch Number of channels in LHS/RHS + * @param[in] out_shift Per channel output shift. Length of vector is equal to number of channels. + * @param[in] out_mult Per channel output multiplier. Length of vector is equal to number of channels. + * @param[in] out_offset Offset to be added to the output values. Range: -127 to 128 + * @param[in] activation_min Minimum value to clamp the output to. Range: int8 + * @param[in] activation_max Maximum value to clamp the output to. Range: int8 + * @param[in] row_x_col (row_dimension * col_dimension) of LHS/RHS matrix + * @param[in] output_bias Per channel output bias. Length of vector is equal to number of channels. + * @param[in] out Output pointer + * + * @return The function returns one of the two + * - Updated output pointer if an implementation is available + * - NULL if no implementation is available. + * + * @note If number of channels is not a multiple of 4, upto 3 elements outside the boundary will be read + * out for the following. + * - Output shift + * - Output multiplier + * - Output bias + * - rhs + */ +q7_t *riscv_nn_depthwise_conv_nt_t_s8(const q7_t *lhs, + const q7_t *rhs, + const int32_t lhs_offset, + const uint16_t num_ch, + const int32_t *out_shift, + const int32_t *out_mult, + const int32_t out_offset, + const int32_t activation_min, + const int32_t activation_max, + const uint16_t row_x_col, + const int32_t *const output_bias, + q7_t *out); + +/** + @brief Read 2 q15 elements and post increment pointer. + @param[in] in_q15 Pointer to pointer that holds address of input. + @return q31 value + */ +__STATIC_FORCEINLINE q31_t riscv_nn_read_q15x2_ia(const q15_t **in_q15) +{ + q31_t val; + +#ifdef __RISCV_FEATURE_UNALIGNED + memcpy (&val, *in_q15, 4); +#else + __ASM volatile ("lw %0, 0(%1)" : "=r" (val) : "r" (*in_q15)); +#endif + *in_q15 += 2; + + return (val); +} + +/** + @brief Read 4 q7 from q7 pointer and post increment pointer. + @param[in] in_q7 Pointer to pointer that holds address of input. + @return q31 value + */ +__STATIC_FORCEINLINE q31_t riscv_nn_read_q7x4_ia(const q7_t **in_q7) +{ + q31_t val; +#ifdef __RISCV_FEATURE_UNALIGNED + memcpy (&val, *in_q7, 4); +#else + __ASM volatile ("lw %0, 0(%1)" : "=r" (val) : "r" (*in_q7)); +#endif + *in_q7 += 4; + + return (val); +} + +/** + @brief Read 2 q15 from q15 pointer. + @param[in] in_q15 pointer to address of input. + @return q31 value + */ +__STATIC_FORCEINLINE q31_t riscv_nn_read_q15x2(const q15_t *in_q15) +{ + q31_t val; +#ifdef __RISCV_FEATURE_UNALIGNED + memcpy (&val, in_q15, 4); +#else + __ASM volatile ("lw %0, 0(%1)" : "=r" (val) : "r" (in_q15)); +#endif + + + return (val); +} + +/** + @brief Read 4 q7 values. + @param[in] in_q7 pointer to address of input. + @return q31 value + */ +__STATIC_FORCEINLINE q31_t riscv_nn_read_q7x4(const q7_t *in_q7) +{ + q31_t val; +#ifdef __RISCV_FEATURE_UNALIGNED + memcpy (&val, in_q7, 4); +#else + __ASM volatile ("lw %0, 0(%1)" : "=r" (val) : "r" (in_q7)); +#endif + + return (val); +} + +/** + * @brief memset + * @param[in, out] dst Destination pointer + * @param[in] val Value to set + * @param[in] block_size Number of bytes to copy. + * + */ +__STATIC_FORCEINLINE void riscv_memset_q7(q7_t *dst, const q7_t val, uint32_t block_size) +{ + memset(dst, val, block_size); +} + +#if defined(RISCV_MATH_DSP) + +/** + * @brief read and expand one q7 word into two q15 words + */ + +__STATIC_FORCEINLINE const q7_t *read_and_pad(const q7_t *source, q31_t *out1, q31_t *out2) +{ + q31_t inA = riscv_nn_read_q7x4_ia(&source); + q31_t inAbuf1 = __SXTB16(__ROR((uint32_t)inA, 8)); + q31_t inAbuf2 = __SXTB16(inA); + + *out2 = (int32_t)(__PKHTB(inAbuf1, inAbuf2, 16)); + *out1 = (int32_t)(__PKHBT(inAbuf2, inAbuf1, 16)); + + return source; +} + +/** + * @brief read and expand one q7 word into two q15 words with reordering + */ + +__STATIC_FORCEINLINE const q7_t *read_and_pad_reordered(const q7_t *source, q31_t *out1, q31_t *out2) +{ + q31_t inA = riscv_nn_read_q7x4_ia(&source); + *out2 = __SXTB16(__ROR((uint32_t)inA, 8)); + *out1 = __SXTB16(inA); + + return source; +} + +/** + * @brief read and expand one q7 word into two q15 words with reordering and add an offset + */ +__STATIC_FORCEINLINE const q7_t * +read_and_pad_reordered_with_offset(const q7_t *source, q31_t *out1, q31_t *out2, q31_t offset) +{ + q31_t inA = riscv_nn_read_q7x4_ia(&source); + + *out2 = __SXTB16(__ROR((uint32_t)inA, 8)); + *out1 = __SXTB16(inA); + *out1 = __QADD16(*out1, offset); + *out2 = __QADD16(*out2, offset); + + return source; +} + +#endif + +/** + * @defgroup NNBasicMath Basic Math Functions for Neural Network Computation + * + * Basic Math Functions for Neural Network Computation + * + */ + +/** + * @brief q7 vector multiplication with variable output shifts + * @param[in] *pSrcA pointer to the first input vector + * @param[in] *pSrcB pointer to the second input vector + * @param[out] *pDst pointer to the output vector + * @param[in] out_shift amount of right-shift for output + * @param[in] blockSize number of samples in each vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable q15 range [0x8000 0x7FFF] will be saturated. + */ + +void riscv_nn_mult_q15(q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, const uint16_t out_shift, uint32_t blockSize); + +/** + * @brief q7 vector multiplication with variable output shifts + * @param[in] *pSrcA pointer to the first input vector + * @param[in] *pSrcB pointer to the second input vector + * @param[out] *pDst pointer to the output vector + * @param[in] out_shift amount of right-shift for output + * @param[in] blockSize number of samples in each vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable q7 range [0x80 0x7F] will be saturated. + */ + +void riscv_nn_mult_q7(q7_t *pSrcA, q7_t *pSrcB, q7_t *pDst, const uint16_t out_shift, uint32_t blockSize); + +/** + * @brief macro for adding rounding offset + */ +#ifndef RISCV_NN_TRUNCATE +#define NN_ROUND(out_shift) ((0x1u << out_shift) >> 1) +#else +#define NN_ROUND(out_shift) 0 +#endif + +// Macros for shortening quantization functions' names and avoid long lines +#define MUL_SAT(a, b) riscv_nn_doubling_high_mult((a), (b)) +#define MUL_SAT_MVE(a, b) riscv_doubling_high_mult_mve_32x4((a), (b)) +#define MUL_POW2(a, b) riscv_nn_mult_by_power_of_two((a), (b)) + +#define DIV_POW2(a, b) riscv_nn_divide_by_power_of_two((a), (b)) +#define DIV_POW2_MVE(a, b) riscv_divide_by_power_of_two_mve((a), (b)) + +#define EXP_ON_NEG(x) riscv_nn_exp_on_negative_values((x)) +#define ONE_OVER1(x) riscv_nn_one_over_one_plus_x_for_x_in_0_1((x)) + +/** + * @brief Saturating doubling high multiply. Result matches + * NEON instruction VQRDMULH. + * @param[in] m1 Multiplicand. Range: {Q31_MIN, Q31_MAX} + * @param[in] m2 Multiplier. Range: {Q31_MIN, Q31_MAX} + * @return Result of multiplication. + * + */ +__STATIC_FORCEINLINE q31_t riscv_nn_doubling_high_mult(const q31_t m1, const q31_t m2) +{ + q31_t result = 0; + // Rounding offset to add for a right shift of 31 + q63_t mult = 1 << 30; + + if ((m1 < 0) ^ (m2 < 0)) + { + mult = 1 - mult; + } + // Gets resolved as a SMLAL instruction + mult = mult + (q63_t)m1 * m2; + + // Utilize all of the upper 32 bits. This is the doubling step + // as well. + result = (int32_t)(mult / (1ll << 31)); + + if ((m1 == m2) && (m1 == (int32_t)Q31_MIN)) + { + result = Q31_MAX; + } + return result; +} + +/** + * @brief Doubling high multiply without saturation. This is intended + * for requantization where the scale is a positive integer + * + * @param[in] m1 Multiplicand. Range: {Q31_MIN, Q31_MAX} + * @param[in] m2 Multiplier Range: {Q31_MIN, Q31_MAX} + * @return Result of multiplication. + * @note The result of this matches that of neon instruction + * VQRDMULH for m1 in range {Q31_MIN, Q31_MAX} and m2 in + * range {Q31_MIN + 1, Q31_MAX}. Saturation occurs when + * m1 equals m2 equals Q31_MIN and that is not handled by + * this function. + * + */ +__STATIC_FORCEINLINE q31_t riscv_nn_doubling_high_mult_no_sat(const q31_t m1, const q31_t m2) +{ + q31_t result = 0; + union riscv_nn_long_long mult; + + // Rounding offset to add for a right shift of 31 + mult.word.low = 1 << 30; + mult.word.high = 0; + + // Gets resolved as a SMLAL instruction + mult.long_long = mult.long_long + (q63_t)m1 * m2; + + // Utilize all of the upper 32 bits. This is the doubling step + // as well. + result = (int32_t)(mult.long_long >> 31); + + return result; +} + +/** + * @brief Rounding divide by power of two. + * @param[in] dividend - Dividend + * @param[in] exponent - Divisor = power(2, exponent) + * Range: [0, 31] + * @return Rounded result of division. Midpoint is rounded away from zero. + * + */ +__STATIC_FORCEINLINE q31_t riscv_nn_divide_by_power_of_two(const q31_t dividend, const q31_t exponent) +{ + q31_t result = 0; + const q31_t remainder_mask = (1 << exponent) - 1; + int32_t remainder = remainder_mask & dividend; + + // Basic division + result = dividend >> exponent; + + // Adjust 'result' for rounding (mid point away from zero) + q31_t threshold = remainder_mask >> 1; + if (result < 0) + { + threshold++; + } + if (remainder > threshold) + { + result++; + } + + return result; +} + +/** + * @brief Requantize a given value. + * @param[in] val Value to be requantized + * @param[in] multiplier multiplier. Range {Q31_MIN + 1, Q32_MAX} + * @param[in] shift left or right shift for 'val * multiplier' + * + * @return Returns (val * multiplier)/(2 ^ shift) + * + */ +__STATIC_FORCEINLINE q31_t riscv_nn_requantize(const q31_t val, const q31_t multiplier, const q31_t shift) +{ + return riscv_nn_divide_by_power_of_two(riscv_nn_doubling_high_mult_no_sat(val * (1 << LEFT_SHIFT(shift)), multiplier), + RIGHT_SHIFT(shift)); +} + +/** + * @brief memcpy + * @param[in, out] dst Destination pointer + * @param[in] src Source pointer. + * @param[in] block_size Number of bytes to copy. + * + */ +__STATIC_FORCEINLINE void riscv_memcpy_q7(q7_t *__RESTRICT dst, const q7_t *__RESTRICT src, uint32_t block_size) +{ + memcpy(dst, src, block_size); +} + + +// @note The following functions are used only for softmax layer, scaled bits = 5 assumed + +__STATIC_FORCEINLINE int32_t riscv_nn_exp_on_negative_values(int32_t val) +{ + int32_t mask = 0; + int32_t shift = 24; + + const int32_t val_mod_minus_quarter = (val & ((1 << shift) - 1)) - (1 << shift); + const int32_t remainder = val_mod_minus_quarter - val; + const int32_t x = (val_mod_minus_quarter << 5) + (1 << 28); + const int32_t x2 = MUL_SAT(x, x); + + int32_t result = 1895147668 + + MUL_SAT(1895147668, x + DIV_POW2(MUL_SAT(DIV_POW2(MUL_SAT(x2, x2), 2) + MUL_SAT(x2, x), 715827883) + x2, 1)); + +#define SELECT_IF_NON_ZERO(x) \ + { \ + mask = MASK_IF_NON_ZERO(remainder & (1 << shift++)); \ + result = SELECT_USING_MASK(mask, MUL_SAT(result, x), result); \ + } + + SELECT_IF_NON_ZERO(1672461947) + SELECT_IF_NON_ZERO(1302514674) + SELECT_IF_NON_ZERO(790015084) + SELECT_IF_NON_ZERO(290630308) + SELECT_IF_NON_ZERO(39332535) + SELECT_IF_NON_ZERO(720401) + SELECT_IF_NON_ZERO(242) + +#undef SELECT_IF_NON_ZERO + + mask = MASK_IF_ZERO(val); + return SELECT_USING_MASK(mask, Q31_MAX, result); +} + +__STATIC_FORCEINLINE q31_t riscv_nn_mult_by_power_of_two(const int32_t val, const int32_t exp) +{ + const int32_t thresh = ((1 << (31 - exp)) - 1); + int32_t result = val << exp; + result = SELECT_USING_MASK(MASK_IF_NON_ZERO(val > thresh), Q31_MAX, result); + result = SELECT_USING_MASK(MASK_IF_NON_ZERO(val < -thresh), Q31_MIN, result); + return result; +} + +__STATIC_FORCEINLINE int32_t riscv_nn_one_over_one_plus_x_for_x_in_0_1(int32_t val) +{ + const int64_t sum = (int64_t)val + (int64_t)Q31_MAX; + const int32_t half_denominator = (int32_t)((sum + (sum >= 0 ? 1 : -1)) / 2L); + int32_t x = 1515870810 + MUL_SAT(half_denominator, -1010580540); + + const int32_t shift = (1 << 29); + x += MUL_POW2(MUL_SAT(x, shift - MUL_SAT(half_denominator, x)), 2); + x += MUL_POW2(MUL_SAT(x, shift - MUL_SAT(half_denominator, x)), 2); + x += MUL_POW2(MUL_SAT(x, shift - MUL_SAT(half_denominator, x)), 2); + + return MUL_POW2(x, 1); +} + +/** + @brief Write 2 q15 elements and post increment pointer. + @param[in] dest_q15 Pointer to pointer that holds address of destination. + @param[in] src_q31 Input value to be written. + @return none + */ +__STATIC_FORCEINLINE void riscv_nn_write_q15x2_ia(q15_t **dest_q15, q31_t src_q31) +{ + q31_t val = src_q31; + + memcpy(*dest_q15, &val, 4); + *dest_q15 += 2; +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/components/nmsis/nn/src/ActivationFunctions/riscv_nn_activations_q15.c b/components/nmsis/nn/src/ActivationFunctions/riscv_nn_activations_q15.c new file mode 100644 index 00000000..8dffed90 --- /dev/null +++ b/components/nmsis/nn/src/ActivationFunctions/riscv_nn_activations_q15.c @@ -0,0 +1,97 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_nn_activations_q15.c + * Description: Q15 neural network activation function using direct table look-up + * + * $Date: 09. October 2020 + * $Revision: V.1.0.1 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "riscv_nn_tables.h" +#include "riscv_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Acti + * @{ + */ + +/** + * @brief neural network activation function using direct table look-up + * + * @note Refer header file for details. + * + */ + +void riscv_nn_activations_direct_q15(q15_t *data, uint16_t size, uint16_t int_width, riscv_nn_activation_type type) +{ + uint16_t i = size; + q15_t *pIn = data; + q15_t *pOut = data; + uint16_t shift_size = 8 + 3 - int_width; + uint32_t bit_mask = 0x7FF >> int_width; + uint32_t full_frac = bit_mask + 1; + const q15_t *lookup_table; + + switch (type) + { + case RISCV_SIGMOID: + lookup_table = sigmoidTable_q15; + break; + case RISCV_TANH: + default: + lookup_table = tanhTable_q15; + break; + } + + while (i) + { + q15_t out; + q15_t in = *pIn++; + q15_t frac = (uint32_t)in & bit_mask; + q15_t value = lookup_table[(uint8_t)(in >> shift_size)]; + if ((in >> shift_size) != 0x7f) + { + q15_t value2 = lookup_table[(uint8_t)(1 + ((uint8_t)(in >> shift_size)))]; + /* doing the interpolation here for better accuracy */ + out = ((q31_t)(full_frac - frac) * value + (q31_t)value2 * frac) >> shift_size; + } + else + { + /* the largest positive value does not have a right side for linear interpolation */ + out = value; + } + + *pOut++ = out; + i--; + } +} + +/** + * @} end of Acti group + */ diff --git a/components/nmsis/nn/src/ActivationFunctions/riscv_nn_activations_q7.c b/components/nmsis/nn/src/ActivationFunctions/riscv_nn_activations_q7.c new file mode 100644 index 00000000..f6e0a614 --- /dev/null +++ b/components/nmsis/nn/src/ActivationFunctions/riscv_nn_activations_q7.c @@ -0,0 +1,90 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_nn_activations_q7.c + * Description: Q7 neural network activation function using direct table look-up + * + * $Date: 09. October 2020 + * $Revision: V.1.0.1 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "riscv_nn_tables.h" +#include "riscv_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Acti + * @{ + */ + +/** + * @brief Q7 neural network activation function using direct table look-up + * @param[in,out] data pointer to input + * @param[in] size number of elements + * @param[in] int_width bit-width of the integer part, assume to be smaller than 3 + * @param[in] type type of activation functions + * + * @details + * + * This is the direct table look-up approach. + * + * Assume here the integer part of the fixed-point is <= 3. + * More than 3 just not making much sense, makes no difference with + * saturation followed by any of these activation functions. + */ + +void riscv_nn_activations_direct_q7(q7_t *data, uint16_t size, uint16_t int_width, riscv_nn_activation_type type) +{ + uint16_t i = size; + q7_t *pIn = data; + q7_t *pOut = data; + q7_t in; + q7_t out; + uint16_t shift_size = 3 - int_width; + const q7_t *lookup_table; + switch (type) + { + case RISCV_SIGMOID: + lookup_table = sigmoidTable_q7; + break; + case RISCV_TANH: + default: + lookup_table = tanhTable_q7; + break; + } + while (i) + { + in = *pIn++; + out = lookup_table[(uint8_t)(in >> shift_size)]; + *pOut++ = out; + i--; + } +} + +/** + * @} end of Acti group + */ diff --git a/components/nmsis/nn/src/ActivationFunctions/riscv_relu6_s8.c b/components/nmsis/nn/src/ActivationFunctions/riscv_relu6_s8.c new file mode 100644 index 00000000..1385da7b --- /dev/null +++ b/components/nmsis/nn/src/ActivationFunctions/riscv_relu6_s8.c @@ -0,0 +1,81 @@ +/* + * Copyright (C) 2010-2019 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_relu6_s8.c + * Description: Basic s8 version of ReLU6 + * + * $Date: 09. October 2020 + * $Revision: V.1.0.1 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "riscv_nnfunctions.h" +#include "riscv_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Acti + * @{ + */ + +/* + * Basic ReLU6 function + * + * Refer to header file for details. + * + */ + +void riscv_relu6_s8(q7_t *data, uint16_t size) +{ +#if defined(RISCV_VECTOR) + uint16_t blkCnt = size; /* Loop counter */ + size_t l; + vint8m8_t vx; + //inital to zero + int8_t vy1=0,vy2=6; + for (; (l = vsetvl_e8m8(blkCnt)) > 0; blkCnt -= l) { + vx = vle8_v_i8m8(data, l); + // if data >= zero, return data, else return zero + vse8_v_i8m8 (data, vmax_vx_i8m8(vx, vy1, l), l); + vse8_v_i8m8 (data, vmin_vx_i8m8(vx, vy2, l), l); + data += l; + } +#else + int32_t i; + + for (i = 0; i < size; i++) + { + int32_t ip = data[i]; + + ip = MAX(ip, 0); + data[i] = MIN(ip, 6); + } +#endif /* defined(RISCV_VECTOR) */ +} + +/** + * @} end of Acti group + */ diff --git a/components/nmsis/nn/src/ActivationFunctions/riscv_relu_q15.c b/components/nmsis/nn/src/ActivationFunctions/riscv_relu_q15.c new file mode 100644 index 00000000..58c6e9ca --- /dev/null +++ b/components/nmsis/nn/src/ActivationFunctions/riscv_relu_q15.c @@ -0,0 +1,146 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_relu_q15.c + * Description: Q15 version of ReLU + * + * $Date: 09. October 2020 + * $Revision: V.1.0.2 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "riscv_nnfunctions.h" +#include "riscv_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Acti + * @{ + */ + +/** + * @brief Q15 RELU function + * @param[in,out] data pointer to input + * @param[in] size number of elements + * + * @details + * + * Optimized relu with QSUB instructions. + * + */ + +void riscv_relu_q15(q15_t *data, uint16_t size) +{ +#if defined(RISCV_VECTOR) + uint16_t blkCnt = size; /* Loop counter */ + size_t l; + vint16m8_t vx; + int16_t vy = 0; + for (; (l = vsetvl_e16m8(blkCnt)) > 0; blkCnt -= l) { + vx = vle16_v_i16m8(data, l); + // if data >= zero, return data, else return zero + vse16_v_i16m8 (data, vmax_vx_i16m8(vx, vy, l), l); + data += l; + } +#else +#if defined(RISCV_MATH_DSP) + /* Run the following code for M cores with DSP extension */ + + q15_t *input = data; + q15_t *output = data; + q31_t in; + q31_t buf; + q31_t mask; + q31_t zero; +#if __RISCV_XLEN == 64 + uint16_t i = size >> 2; + q63_t in64; + while (i) + { + in64 = *__SIMD64(input)++; + + *__SIMD64(output)++ = __RV_SMAX16 (in64,zero); + + i--; + } + i = size & 0x3; + while (i) + { + if (*input < 0) + { + *input = 0; + } + input++; + i--; + } +#else + uint16_t i = size >> 1; + while (i) + { + + + // in = *__SIMD32(input)++; + + //*__SIMD32(output)++ = __SMAX8 (in,zero); + + in = *__SIMD32(input)++; + + /* extract the first bit */ + //buf = __ROR(in & 0x80008000, 15); + + /* if MSB=1, mask will be 0xFF, 0x0 otherwise */ + // mask = __QSUB16(0x00000000, buf); + *__SIMD32(output)++ = __RV_SMAX16 (in,zero); + // *__SIMD32(output)++ = in & (~mask); + i--; + } + + if (size & 0x1) + { + if (*input < 0) + { + *input = 0; + } + input++; + } +#endif /* __RISCV_XLEN == 64 */ +#else + /* Run the following code as reference implementation for M cores without DSP extension */ + uint16_t i; + + for (i = 0; i < size; i++) + { + if (data[i] < 0) + data[i] = 0; + } + +#endif /* RISCV_MATH_DSP */ +#endif /* RISCV_VECTOR */ +} + +/** + * @} end of Acti group + */ diff --git a/components/nmsis/nn/src/ActivationFunctions/riscv_relu_q7.c b/components/nmsis/nn/src/ActivationFunctions/riscv_relu_q7.c new file mode 100644 index 00000000..af045138 --- /dev/null +++ b/components/nmsis/nn/src/ActivationFunctions/riscv_relu_q7.c @@ -0,0 +1,134 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_relu_q7.c + * Description: Q7 version of ReLU + * + * $Date: 09. October 2020 + * $Revision: V.1.0.3 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "riscv_nnfunctions.h" +#include "riscv_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Acti + * @{ + */ + +/** + * @brief Q7 RELU function + * @param[in,out] data pointer to input + * @param[in] size number of elements + * + * @details + * + * Optimized relu with QSUB instructions. + * + */ + +void riscv_relu_q7(q7_t *data, uint16_t size) +{ +#if defined(RISCV_VECTOR) + uint16_t blkCnt = size; /* Loop counter */ + size_t l; + vint8m8_t vx; + //inital to zero + int8_t vy=0; + for (; (l = vsetvl_e8m8(blkCnt)) > 0; blkCnt -= l) { + vx = vle8_v_i8m8(data, l); + // if data >= zero, return data, else return zero + vse8_v_i8m8 (data, vmax_vx_i8m8(vx, vy, l), l); + data += l; + } +#else +#if defined(RISCV_MATH_DSP) + /* Run the following code for M cores with DSP extension */ + + q7_t *input = data; + q7_t *output = data; + q31_t in; + q31_t buf; + q31_t mask; + q31_t zero = 0; +#if __RISCV_XLEN == 64 +uint16_t i = size >> 3; + q63_t in64; + while (i) + { + + in64 = *__SIMD64(input)++; + + *__SIMD64(output)++ = __RV_SMAX8 (in64,zero); + + i--; + } + + i = size & 0x7; +#else + uint16_t i = size >> 2; + + while (i) + { + + in = *__SIMD32(input)++; + + *__SIMD32(output)++ = __RV_SMAX8 (in,zero); + + i--; + } + + i = size & 0x3; +#endif /* __RISCV_XLEN == 64 */ + while (i) + { + if (*input < 0) + { + *input = 0; + } + input++; + i--; + } + +#else + /* Run the following code as reference implementation for cores without DSP extension */ + + uint16_t i; + + for (i = 0; i < size; i++) + { + if (data[i] < 0) + data[i] = 0; + } +#endif +#endif /* defined(RISCV_VECTOR) */ +} + +/** + * @} end of Acti group + */ diff --git a/components/nmsis/nn/src/BasicMathFunctions/riscv_elementwise_add_s8.c b/components/nmsis/nn/src/BasicMathFunctions/riscv_elementwise_add_s8.c new file mode 100644 index 00000000..24ab153d --- /dev/null +++ b/components/nmsis/nn/src/BasicMathFunctions/riscv_elementwise_add_s8.c @@ -0,0 +1,234 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_elementwise_add_s8 + * Description: Element wise add + * + * $Date: 01. March 2021 + * $Revision: V.2.5.3 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "riscv_nnfunctions.h" +#include "riscv_nnsupportfunctions.h" + + +/** + * @note The *_no_sat API does not mean that the input not saturated, Since + * __MULT is a positive integer, it is saturated. The API definition + * has more info about it. + */ +#define SAT_INPUT(__INPUT, __MULT, __SHIFT) \ + __INPUT = riscv_nn_doubling_high_mult_no_sat(__INPUT, __MULT); \ + __INPUT = riscv_nn_divide_by_power_of_two(__INPUT, -__SHIFT); + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup BasicMath + * @{ + */ + +/* + * s8 element wise add + * + * Refer header file for details. + * + */ + +/* Note: __SHIFT is expected to be <=0 */ + +riscv_status riscv_elementwise_add_s8(const int8_t *input_1_vect, + const int8_t *input_2_vect, + const int32_t input_1_offset, + const int32_t input_1_mult, + const int32_t input_1_shift, + const int32_t input_2_offset, + const int32_t input_2_mult, + const int32_t input_2_shift, + const int32_t left_shift, + int8_t *output, + const int32_t out_offset, + const int32_t out_mult, + const int32_t out_shift, + const int32_t out_activation_min, + const int32_t out_activation_max, + const uint32_t block_size) +{ +#if defined(RISCV_VECTOR) && (__XLEN != 32) && (__FLEN != 32) + uint32_t blkCnt = block_size; /* Loop counter */ + size_t l; + vint32m4_t input_1; + vint32m4_t input_2; + vint32m4_t sum; + + for (; (l = vsetvl_e8m1(blkCnt)) > 0; blkCnt -= l) { + input_1 = vsll_vx_i32m4(vwadd_vx_i32m4(vwadd_vx_i16m2(vle8_v_i8m1(input_1_vect, l), 0, l), input_1_offset, l), left_shift, l); + input_1_vect += l; + input_2 = vsll_vx_i32m4(vwadd_vx_i32m4(vwadd_vx_i16m2(vle8_v_i8m1(input_2_vect, l), 0, l), input_2_offset, l), left_shift, l); + input_2_vect += l; + + input_1 = vsra_vx_i32m4(vsmul_vx_i32m4(input_1, input_1_mult, l), -input_1_shift, l); + input_2 = vsra_vx_i32m4(vsmul_vx_i32m4(input_2, input_2_mult, l), -input_2_shift, l); + + sum = vadd_vv_i32m4(input_1, input_2, l); + sum = vadd_vx_i32m4(vsra_vx_i32m4(vnclip_wx_i32m4(vsra_vx_i64m8(vadd_vx_i64m8(vwmul_vx_i64m8(sum, out_mult, l),0x8000,l),31,l),0,l), -out_shift, l), out_offset, l); + + sum = vmax_vx_i32m4(sum, out_activation_min, l); + sum = vmin_vx_i32m4(sum, out_activation_max, l); + vse8_v_i8m1(output, vnsra_wx_i8m1(vnsra_wx_i16m2(sum, 0, l), 0, l), l); + output += l; + } +#else + uint32_t loop_count; + int32_t input_1; + int32_t input_2; + int32_t sum; + +#if defined(RISCV_MATH_DSP) + int32_t a_1, b_1, a_2, b_2; + + int32_t offset_1_packed, offset_2_packed; + + int8_t r1, r2, r3, r4; + + offset_1_packed = (input_1_offset << 16U) | (input_1_offset & 0x0FFFFL); + offset_2_packed = (input_2_offset << 16U) | (input_2_offset & 0x0FFFFL); + + loop_count = block_size >> 2; + + while (loop_count > 0U) + { + /* 4 outputs are calculated in one loop. The order of calculation is follows the order of output sign extension + intrinsic */ + input_1_vect = read_and_pad_reordered(input_1_vect, &b_1, &a_1); + input_2_vect = read_and_pad_reordered(input_2_vect, &b_2, &a_2); + + a_1 = __SADD16(a_1, offset_1_packed); + b_1 = __SADD16(b_1, offset_1_packed); + + a_2 = __SADD16(a_2, offset_2_packed); + b_2 = __SADD16(b_2, offset_2_packed); + + /* Sum 1 */ + input_1 = (b_1 & 0x0FFFF) << left_shift; + + SAT_INPUT(input_1, input_1_mult, input_1_shift); + + input_2 = (b_2 & 0x0FFFF) << left_shift; + SAT_INPUT(input_2, input_2_mult, input_2_shift); + + sum = input_1 + input_2; + SAT_INPUT(sum, out_mult, out_shift); + sum += out_offset; + sum = MAX(sum, out_activation_min); + sum = MIN(sum, out_activation_max); + r1 = (q7_t)sum; + + /* Sum 3 */ + input_1 = ((b_1 >> 16) & 0x0FFFF) << left_shift; + SAT_INPUT(input_1, input_1_mult, input_1_shift); + + input_2 = ((b_2 >> 16) & 0x0FFFF) << left_shift; + SAT_INPUT(input_2, input_2_mult, input_2_shift); + + sum = input_1 + input_2; + SAT_INPUT(sum, out_mult, out_shift); + sum += out_offset; + sum = MAX(sum, out_activation_min); + sum = MIN(sum, out_activation_max); + r3 = (q7_t)sum; + + /* Sum 2 */ + input_1 = (a_1 & 0x0FFFF) << left_shift; + SAT_INPUT(input_1, input_1_mult, input_1_shift); + + input_2 = (a_2 & 0x0FFFF) << left_shift; + SAT_INPUT(input_2, input_2_mult, input_2_shift); + + sum = input_1 + input_2; + SAT_INPUT(sum, out_mult, out_shift); + sum += out_offset; + sum = MAX(sum, out_activation_min); + sum = MIN(sum, out_activation_max); + r2 = (q7_t)sum; + + /* Sum 4 */ + input_1 = ((a_1 >> 16) & 0x0FFFF) << left_shift; + SAT_INPUT(input_1, input_1_mult, input_1_shift); + + input_2 = ((a_2 >> 16) & 0x0FFFF) << left_shift; + SAT_INPUT(input_2, input_2_mult, input_2_shift); + + sum = input_1 + input_2; + SAT_INPUT(sum, out_mult, out_shift); + sum += out_offset; + sum = MAX(sum, out_activation_min); + sum = MIN(sum, out_activation_max); + r4 = (q7_t)sum; + + write_q7x4_ia(&output, __PACKq7(r1, r2, r3, r4)); + + loop_count--; + } + + loop_count = block_size & 0x3; +#else + loop_count = block_size; +#endif + + while (loop_count > 0U) + { + /* C = A + B */ + + input_1 = (*input_1_vect++ + input_1_offset) << left_shift; + input_2 = (*input_2_vect++ + input_2_offset) << left_shift; + + input_1 = riscv_nn_doubling_high_mult(input_1, input_1_mult); + input_1 = riscv_nn_divide_by_power_of_two(input_1, -input_1_shift); + + input_2 = riscv_nn_doubling_high_mult(input_2, input_2_mult); + input_2 = riscv_nn_divide_by_power_of_two(input_2, -input_2_shift); + + sum = input_1 + input_2; + SAT_INPUT(sum, out_mult, out_shift); + sum += out_offset; + + sum = MAX(sum, out_activation_min); + sum = MIN(sum, out_activation_max); + + *output++ = (q7_t)sum; + + /* Decrement loop counter */ + loop_count--; + } + +#endif /* defined(RISCV_VECTOR) */ + return (RISCV_MATH_SUCCESS); +} + +/** + * @} end of BasicMath group + */ diff --git a/components/nmsis/nn/src/BasicMathFunctions/riscv_elementwise_mul_s8.c b/components/nmsis/nn/src/BasicMathFunctions/riscv_elementwise_mul_s8.c new file mode 100644 index 00000000..da3d4539 --- /dev/null +++ b/components/nmsis/nn/src/BasicMathFunctions/riscv_elementwise_mul_s8.c @@ -0,0 +1,205 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_elementwise_mul_s8 + * Description: Element wise multiplication + * + * $Date: January 26, 2021 + * $Revision: V.1.0.5 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "riscv_nnfunctions.h" +#include "riscv_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup BasicMath + * @{ + */ + +/** + * @brief s8 element wise multiplication of two vectors + * + * @note Refer header file for details. + * + */ + +riscv_status riscv_elementwise_mul_s8(const int8_t *input_1_vect, + const int8_t *input_2_vect, + const int32_t input_1_offset, + const int32_t input_2_offset, + int8_t *output, + const int32_t out_offset, + const int32_t out_mult, + const int32_t out_shift, + const int32_t out_activation_min, + const int32_t out_activation_max, + const uint32_t block_size) +{ + + int32_t loop_count; +#if defined(RISCV_VECTOR) && (__XLEN != 32) && (__FLEN != 32) + uint32_t blkCnt = block_size; + size_t l; + vint32m4_t input_1; + vint32m4_t input_2; + // vint64m8_t mul_res64; + vint32m4_t mul_res32; + int32_t mul_res; + + for (; (l = vsetvl_e8m1(blkCnt)) > 0; blkCnt -= l) { + input_1 = vadd_vx_i32m4(vwadd_vx_i32m4(vwadd_vx_i16m2(vle8_v_i8m1(input_1_vect, l), 0, l), 0, l), input_1_offset, l); + input_1_vect += l; + input_2 = vadd_vx_i32m4(vwadd_vx_i32m4(vwadd_vx_i16m2(vle8_v_i8m1(input_2_vect, l), 0, l), 0, l), input_2_offset, l); + input_2_vect += l; + + mul_res32 = vmul_vv_i32m4(input_1, input_2, l); + for(size_t i =0;i> 2; + + while (loop_count > 0) + { + /* 4 outputs are calculated in one loop. The order of calculation is follows the order of output sign extension + intrinsic */ + input_1_vect = read_and_pad_reordered(input_1_vect, &b_1, &a_1); + input_2_vect = read_and_pad_reordered(input_2_vect, &b_2, &a_2); + + a_1 = __SADD16(a_1, offset_1_packed); + b_1 = __SADD16(b_1, offset_1_packed); + + a_2 = __SADD16(a_2, offset_2_packed); + b_2 = __SADD16(b_2, offset_2_packed); + + /* Mul 1 */ + input_1 = (int16_t)(b_1 & 0x0FFFFL); + input_2 = (int16_t)(b_2 & 0x0FFFFL); + + mul_res = input_1 * input_2; + mul_res = riscv_nn_requantize(mul_res, out_mult, out_shift) + out_offset; + + mul_res = MAX(mul_res, out_activation_min); + mul_res = MIN(mul_res, out_activation_max); + r1 = (q7_t)mul_res; + + /* Mul 3 */ + input_1 = (int16_t)((b_1 >> 16U) & 0x0FFFFL); + input_2 = (int16_t)((b_2 >> 16U) & 0x0FFFFL); + + mul_res = input_1 * input_2; + mul_res = riscv_nn_requantize(mul_res, out_mult, out_shift) + out_offset; + mul_res = MAX(mul_res, out_activation_min); + mul_res = MIN(mul_res, out_activation_max); + r3 = (q7_t)mul_res; + + /* Mul 2 */ + input_1 = (int16_t)(a_1 & 0x0FFFFL); + input_2 = (int16_t)(a_2 & 0x0FFFFL); + + mul_res = input_1 * input_2; + mul_res = riscv_nn_requantize(mul_res, out_mult, out_shift) + out_offset; + mul_res = MAX(mul_res, out_activation_min); + mul_res = MIN(mul_res, out_activation_max); + r2 = (q7_t)mul_res; + + /* Mul 4 */ + input_1 = (int16_t)((a_1 >> 16U) & 0x0FFFFL); + input_2 = (int16_t)((a_2 >> 16U) & 0x0FFFFL); + + mul_res = input_1 * input_2; + mul_res = riscv_nn_requantize(mul_res, out_mult, out_shift) + out_offset; + mul_res = MAX(mul_res, out_activation_min); + mul_res = MIN(mul_res, out_activation_max); + r4 = (q7_t)mul_res; + + write_q7x4_ia(&output, __PACKq7(r1, r2, r3, r4)); + + loop_count--; + } + + loop_count = block_size & 0x3; +#else + loop_count = block_size; +#endif + + while (loop_count > 0) + { + /* C = A * B */ + + input_1 = *input_1_vect++ + input_1_offset; + input_2 = *input_2_vect++ + input_2_offset; + + mul_res = input_1 * input_2; + mul_res = riscv_nn_requantize(mul_res, out_mult, out_shift) + out_offset; + + mul_res = MAX(mul_res, out_activation_min); + mul_res = MIN(mul_res, out_activation_max); + + *output++ = (q7_t)mul_res; + + /* Decrement loop counter */ + loop_count--; + } +#endif + return RISCV_MATH_SUCCESS; +} + +/** + * @} end of BasicMath group + */ diff --git a/components/nmsis/nn/src/ConcatenationFunctions/riscv_concatenation_s8_w.c b/components/nmsis/nn/src/ConcatenationFunctions/riscv_concatenation_s8_w.c new file mode 100644 index 00000000..95db345b --- /dev/null +++ b/components/nmsis/nn/src/ConcatenationFunctions/riscv_concatenation_s8_w.c @@ -0,0 +1,66 @@ +/* + * Copyright (C) 2010-2019 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_concatenation_s8_w.c + * Description: s8 version of concatenation along the W axis + * + * $Date: October 2019 + * $Revision: V.1.0.0 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "riscv_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Concatenation + * @{ + */ + +/* + * s8 version of concatenation along the W axis + * + * Refer to header file for details. + * + */ +void riscv_concatenation_s8_w(const int8_t *input, + const uint16_t input_x, + const uint16_t input_y, + const uint16_t input_z, + const uint16_t input_w, + int8_t *output, + const uint32_t offset_w) +{ + const uint32_t input_copy_size = input_x * input_y * input_z * input_w; + + output += offset_w * (input_x * input_y * input_z); + + memcpy(output, input, input_copy_size); +} + +/** + * @} end of Concatenation group + */ diff --git a/components/nmsis/nn/src/ConcatenationFunctions/riscv_concatenation_s8_x.c b/components/nmsis/nn/src/ConcatenationFunctions/riscv_concatenation_s8_x.c new file mode 100644 index 00000000..2342f894 --- /dev/null +++ b/components/nmsis/nn/src/ConcatenationFunctions/riscv_concatenation_s8_x.c @@ -0,0 +1,75 @@ +/* + * Copyright (C) 2010-2019 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_concatenation_s8_x.c + * Description: s8 version of concatenation along the X axis + * + * $Date: October 2019 + * $Revision: V.1.0.0 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "riscv_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Concatenation + * @{ + */ + +/* + * s8 version of concatenation along the X axis + * + * Refer to header file for details. + * + */ +void riscv_concatenation_s8_x(const int8_t *input, + const uint16_t input_x, + const uint16_t input_y, + const uint16_t input_z, + const uint16_t input_w, + int8_t *output, + const uint16_t output_x, + const uint32_t offset_x) +{ + const uint32_t num_iterations = input_y * input_z * input_w; + + output += offset_x; + + uint32_t i; + + // Copy per row + for (i = 0; i < num_iterations; ++i) + { + memcpy(output, input, input_x); + input += input_x; + output += output_x; + } +} + +/** + * @} end of Concatenation group + */ diff --git a/components/nmsis/nn/src/ConcatenationFunctions/riscv_concatenation_s8_y.c b/components/nmsis/nn/src/ConcatenationFunctions/riscv_concatenation_s8_y.c new file mode 100644 index 00000000..b29357bc --- /dev/null +++ b/components/nmsis/nn/src/ConcatenationFunctions/riscv_concatenation_s8_y.c @@ -0,0 +1,76 @@ +/* + * Copyright (C) 2010-2019 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_concatenation_s8_y.c + * Description: s8 version of concatenation along the Y axis + * + * $Date: October 2019 + * $Revision: V.1.0.0 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "riscv_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Concatenation + * @{ + */ + +/* + * s8 version of concatenation along the Y axis + * + * Refer to header file for details. + * + */ +void riscv_concatenation_s8_y(const int8_t *input, + const uint16_t input_x, + const uint16_t input_y, + const uint16_t input_z, + const uint16_t input_w, + int8_t *output, + const uint16_t output_y, + const uint32_t offset_y) +{ + const uint32_t num_iterations = input_z * input_w; + const uint32_t input_copy_size = input_x * input_y; + const uint32_t output_stride = input_x * output_y; + + output += offset_y * input_x; + uint32_t i; + + // Copy per tile + for (i = 0; i < num_iterations; ++i) + { + memcpy(output, input, input_copy_size); + input += input_copy_size; + output += output_stride; + } +} + +/** + * @} end of Concatenation group + */ diff --git a/components/nmsis/nn/src/ConcatenationFunctions/riscv_concatenation_s8_z.c b/components/nmsis/nn/src/ConcatenationFunctions/riscv_concatenation_s8_z.c new file mode 100644 index 00000000..2ef235d9 --- /dev/null +++ b/components/nmsis/nn/src/ConcatenationFunctions/riscv_concatenation_s8_z.c @@ -0,0 +1,75 @@ +/* + * Copyright (C) 2010-2019 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_concatenation_s8_z.c + * Description: s8 version of concatenation along the Z axis + * + * $Date: October 2019 + * $Revision: V.1.0.0 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "riscv_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Concatenation + * @{ + */ + +/* + * s8 version of concatenation along the Z axis + * + * Refer to header file for details. + * + */ +void riscv_concatenation_s8_z(const int8_t *input, + const uint16_t input_x, + const uint16_t input_y, + const uint16_t input_z, + const uint16_t input_w, + int8_t *output, + const uint16_t output_z, + const uint32_t offset_z) +{ + const uint32_t input_copy_size = input_x * input_y * input_z; + const uint32_t output_stride = input_x * input_y * output_z; + + output += offset_z * (input_x * input_y); + + uint32_t i; + + for (i = 0; i < input_w; ++i) + { + memcpy(output, input, input_copy_size); + input += input_copy_size; + output += output_stride; + } +} + +/** + * @} end of Concatenation group + */ diff --git a/components/nmsis/nn/src/ConvolutionFunctions/riscv_convolve_1_x_n_s8.c b/components/nmsis/nn/src/ConvolutionFunctions/riscv_convolve_1_x_n_s8.c new file mode 100644 index 00000000..eed50897 --- /dev/null +++ b/components/nmsis/nn/src/ConvolutionFunctions/riscv_convolve_1_x_n_s8.c @@ -0,0 +1,101 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_convolve_1_x_n_s8.c + * Description: s8 version of 1xN convolution using symmetric quantization. + * + * $Date: January 26, 2021 + * $Revision: V.2.0.3 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "riscv_nnfunctions.h" +#include "riscv_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/* + * 1xN s8 convolution function. + * + * Refer header file for details. + * + */ + +riscv_status riscv_convolve_1_x_n_s8(const nmsis_nn_context *ctx, + const nmsis_nn_conv_params *conv_params, + const nmsis_nn_per_channel_quant_params *quant_params, + const nmsis_nn_dims *input_dims, + const q7_t *input_data, + const nmsis_nn_dims *filter_dims, + const q7_t *filter_data, + const nmsis_nn_dims *bias_dims, + const int32_t *bias_data, + const nmsis_nn_dims *output_dims, + q7_t *output_data) +{ + (void)bias_dims; + riscv_status status = RISCV_MATH_SUCCESS; + if (output_dims->w % 4 != 0) + { + status = RISCV_MATH_SIZE_MISMATCH; + goto out; + } + + status = riscv_convolve_s8(ctx, + conv_params, + quant_params, + input_dims, + input_data, + filter_dims, + filter_data, + bias_dims, + bias_data, + output_dims, + output_data); + +out: + /* Return to application */ + return status; +} + +int32_t riscv_convolve_1_x_n_s8_get_buffer_size(const nmsis_nn_dims *input_dims, const nmsis_nn_dims *filter_dims) +{ +#if defined(RISCV_MATH_DSP) + return (2 * input_dims->c * filter_dims->w * filter_dims->h) * sizeof(int16_t); +#else + (void)input_dims; + (void)filter_dims; + return 0; +#endif +} + +/** + * @} end of NNConv group + */ diff --git a/components/nmsis/nn/src/ConvolutionFunctions/riscv_convolve_1x1_HWC_q7_fast_nonsquare.c b/components/nmsis/nn/src/ConvolutionFunctions/riscv_convolve_1x1_HWC_q7_fast_nonsquare.c new file mode 100644 index 00000000..3957df4a --- /dev/null +++ b/components/nmsis/nn/src/ConvolutionFunctions/riscv_convolve_1x1_HWC_q7_fast_nonsquare.c @@ -0,0 +1,267 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_convolve_1x1_HWC_q7_fast_nonsquare.c + * Description: Fast Q7 version of 1x1 convolution (non-square shape) + * + * $Date: January 26, 2021 + * $Revision: V.1.0.2 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "riscv_nnfunctions.h" +#include "riscv_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/** + * @brief Fast Q7 version of 1x1 convolution (non-sqaure shape) + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in_x input tensor dimention x + * @param[in] dim_im_in_y input tensor dimention y + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel_x filter kernel size x + * @param[in] dim_kernel_y filter kernel size y + * @param[in] padding_x padding size x + * @param[in] padding_y padding size y + * @param[in] stride_x convolution stride x + * @param[in] stride_y convolution stride y + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out_x output tensor dimension x + * @param[in] dim_im_out_y output tensor dimension y + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * RISCV_MATH_SIZE_MISMATCH or RISCV_MATH_SUCCESS based on the outcome of size checking. + * + * This function is optimized for convolution with 1x1 kernel size (i.e., dim_kernel_x=1 + * and dim_kernel_y=1). It can be used for the second half of MobileNets [1] after depthwise + * separable convolution. + * + * This function is the version with full list of optimization tricks, but with + * some constraints: + * ch_im_in is multiple of 4 + * ch_im_out is multiple of 2 + * + * [1] MobileNets: Efficient Convolutional Neural Networks for Mobile Vision Applications + * https://arxiv.org/abs/1704.04861 + */ + +riscv_status riscv_convolve_1x1_HWC_q7_fast_nonsquare(const q7_t *Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q7_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q7_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t *Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t *bufferA, + q7_t *bufferB) +{ + (void)bufferB; +#if defined (RISCV_MATH_DSP) || defined (RISCV_VECTOR) + /* Run the following code for RISC-V Core with DSP enabled */ + (void)dim_im_in_y; + int16_t i_out_y, i_out_x; + int16_t i_ch_out; +#if defined(RISCV_VECTOR) + uint32_t blkCnt_v; + size_t l; + vint8m2_t v_a, v_b; + int32_t i_a; + vint32m1_t v_temp; + l = vsetvl_e32m1(1); + v_temp = vsub_vv_i32m1(v_temp, v_temp, l); +#endif + /* ----------------------- + * Here we use bufferA as q15_t internally as computation are done with q15_t level + * im2col are done to output in q15_t format from q7_t input + */ + + q7_t *pBuffer = (q7_t *)bufferA; + q7_t *pOut = Im_out; + + if (ch_im_in % 4 != 0 || ch_im_out % 2 != 0 || dim_kernel_x != 1 || dim_kernel_y != 1 || padding_x != 0 || + padding_y != 0 || stride_x != 1 || stride_y != 1) + { + /* check if the input dimension meets the constraints */ + return RISCV_MATH_SIZE_MISMATCH; + } + + for (i_out_y = 0; i_out_y < dim_im_out_y; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out_x; i_out_x++) + { + /* This part implements the im2col function */ + riscv_q7_to_q7_reordered_no_shift((q7_t *) Im_in + (i_out_y * dim_im_in_x + i_out_x) * ch_im_in, pBuffer, + ch_im_in); + pBuffer += ch_im_in; + + if (pBuffer == (q7_t *)bufferA + 2 * ch_im_in * dim_kernel_x * dim_kernel_y) + { + pOut = + riscv_nn_mat_mult_kernel_q7_reordered(wt, (q7_t *)bufferA, ch_im_out, ch_im_in, bias_shift, out_shift, bias, pOut); + /* counter reset */ + pBuffer = (q7_t *)bufferA; + } + } + } + + /* check if there is left-over for compute */ + if (pBuffer != (q7_t *)bufferA) + { + const q7_t *pA = wt; + for (i_ch_out = 0; i_ch_out < ch_im_out; i_ch_out++) + { + q31_t sum = ((q31_t)(bias[i_ch_out]) << bias_shift) + NN_ROUND(out_shift); + q7_t *pB = (q7_t *)bufferA; + /* basically each time it process 4 entries */ +#if defined(RISCV_VECTOR) + blkCnt_v = ch_im_in * dim_kernel_y * dim_kernel_x; + for (; (l = vsetvl_e8m2(blkCnt_v)) > 0; blkCnt_v -= l) { + v_a = vle8_v_i8m2(pA, l); + v_b = vle8_v_i8m2(pB, l); + pA += l; + pB += l; + sum += vmv_x_s_i32m1_i32 (vwredsum_vs_i16m4_i32m1(v_temp,vwmul_vv_i16m4(v_a,v_b, l),v_temp, l)); + } +#else +#if defined (RISCV_MATH_DSP) +#if __RISCV_XLEN == 64 + uint16_t colCnt = ch_im_in * dim_kernel_x * dim_kernel_y >> 3; + q63_t sum64 = 0; + while (colCnt) + { + q63_t inB1 = *__SIMD64(pB)++; + q63_t inA1 = *__SIMD64(pA)++; + sum64 = __RV_SMAQA(sum64, inA1, inB1); + + colCnt--; + } + sum = sum + (q31_t)(sum64 & 0xFFFFFFFF) + (q31_t)((sum64 & 0xFFFFFFFF00000000)>>32); + colCnt = ch_im_in * dim_kernel_y * dim_kernel_x & 0x7; + +#else + uint16_t colCnt = ch_im_in * dim_kernel_x * dim_kernel_y >> 2; + + while (colCnt) + { + q31_t inB1 = *__SIMD32(pB)++; + q31_t inA1 = *__SIMD32(pA)++; + sum = __RV_SMAQA(sum, inA1, inB1); + + colCnt--; + } + colCnt = ch_im_in * dim_kernel_y * dim_kernel_x & 0x3; +#endif /* __RISCV_XLEN == 64 */ +#else + uint16_t colCnt = ch_im_in * dim_kernel_y * dim_kernel_x; +#endif /* defined (RISCV_MATH_DSP) */ + while (colCnt) + { + q7_t inA1 = *pA++; + q15_t inB1 = *pB++; + sum += inA1 * inB1; + colCnt--; + } +#endif + *pOut = (q7_t) __SSAT((sum >> out_shift), 8); + pOut++; + } + } + +#else + (void)bufferA; + /* Run the following code as reference implementation for RISC-V Core without DSP */ + int i, j, k, l, m, n; + int conv_out; + int in_row, in_col; + + if (ch_im_in % 4 != 0 || ch_im_out % 2 != 0 || dim_kernel_x != 1 || dim_kernel_y != 1 || padding_x != 0 || + padding_y != 0 || stride_x != 1 || stride_y != 1) + { + /* check if the input dimension meets the constraints */ + return RISCV_MATH_SIZE_MISMATCH; + } + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out_y; j++) + { + for (k = 0; k < dim_im_out_x; k++) + { + conv_out = ((q31_t)(bias[i]) << bias_shift) + NN_ROUND(out_shift); + for (m = 0; m < dim_kernel_y; m++) + { + for (n = 0; n < dim_kernel_x; n++) + { + // if-for implementation + in_row = stride_y * j + m - padding_y; + in_col = stride_x * k + n - padding_x; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in_y && in_col < dim_im_in_x) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += Im_in[(in_row * dim_im_in_x + in_col) * ch_im_in + l] * + wt[i * ch_im_in * dim_kernel_y * dim_kernel_x + (m * dim_kernel_y + n) * ch_im_in + + l]; + } + } + } + } + Im_out[i + (j * dim_im_out_x + k) * ch_im_out] = (q7_t)__SSAT((conv_out >> out_shift), 8); + } + } + } + +#endif /* RISCV_MATH_DSP */ + + /* Return to application */ + return RISCV_MATH_SUCCESS; +} + +/** + * @} end of NNConv group + */ diff --git a/components/nmsis/nn/src/ConvolutionFunctions/riscv_convolve_1x1_s8_fast.c b/components/nmsis/nn/src/ConvolutionFunctions/riscv_convolve_1x1_s8_fast.c new file mode 100644 index 00000000..1b0a5785 --- /dev/null +++ b/components/nmsis/nn/src/ConvolutionFunctions/riscv_convolve_1x1_s8_fast.c @@ -0,0 +1,109 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_convolve_1x1_s8_fast.c + * Description: Fast q7 version of 1x1 convolution (non-square shape) + * + * $Date: 09. October 2020 + * $Revision: V.2.0.3 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "riscv_nnfunctions.h" +#include "riscv_nnsupportfunctions.h" + +#define DIM_KER_X (1U) +#define DIM_KER_Y (1U) + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/* + * Fast s8 version for 1x1 convolution (non-square shape) + * + * Refer header file for details. + * + */ + +riscv_status riscv_convolve_1x1_s8_fast(const nmsis_nn_context *ctx, + const nmsis_nn_conv_params *conv_params, + const nmsis_nn_per_channel_quant_params *quant_params, + const nmsis_nn_dims *input_dims, + const q7_t *input_data, + const nmsis_nn_dims *filter_dims, + const q7_t *filter_data, + const nmsis_nn_dims *bias_dims, + const int32_t *bias_data, + const nmsis_nn_dims *output_dims, + q7_t *output_data) +{ + if (input_dims->c % 4 != 0 || conv_params->padding.w != 0 || conv_params->padding.h != 0 || + conv_params->stride.w != 1 || conv_params->stride.h != 1) + { + return RISCV_MATH_SIZE_MISMATCH; + } + + (void)ctx; + (void)filter_dims; + (void)bias_dims; + + /* Run the following code as reference implementation for RISC-V processors with or without DSP extension */ + + const int32_t lhs_rows = input_dims->w * input_dims->h * input_dims->n; + const int32_t rhs_rows = output_dims->c; + const int32_t rhs_cols = input_dims->c; + + riscv_nn_mat_mult_nt_t_s8(input_data, + filter_data, + bias_data, + output_data, + quant_params->multiplier, + quant_params->shift, + lhs_rows, + rhs_rows, + rhs_cols, + conv_params->input_offset, + conv_params->output_offset, + conv_params->activation.min, + conv_params->activation.max); + + + /* Return to application */ + return RISCV_MATH_SUCCESS; +} + +int32_t riscv_convolve_1x1_s8_fast_get_buffer_size(const nmsis_nn_dims *input_dims) +{ + (void)input_dims; + return 0; +} + +/** + * @} end of NNConv group + */ diff --git a/components/nmsis/nn/src/ConvolutionFunctions/riscv_convolve_HWC_q15_basic.c b/components/nmsis/nn/src/ConvolutionFunctions/riscv_convolve_HWC_q15_basic.c new file mode 100644 index 00000000..38301695 --- /dev/null +++ b/components/nmsis/nn/src/ConvolutionFunctions/riscv_convolve_HWC_q15_basic.c @@ -0,0 +1,219 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_convolve_HWC_q15_basic.c + * Description: Q15 version of convolution + * + * $Date: January 26, 2021 + * $Revision: V.1.0.2 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "riscv_nnfunctions.h" +#include "riscv_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/** + * @brief Basic Q15 convolution function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimention + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns RISCV_MATH_SUCCESS + * + * @details + * + * Buffer size: + * + * bufferA size: ch_im_in*dim_kernel*dim_kernel + * + * bufferB size: 0 + * + * This basic version is designed to work for any input tensor and weight + * dimension. + */ + +riscv_status riscv_convolve_HWC_q15_basic(const q15_t *Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q15_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q15_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q15_t *Im_out, + const uint16_t dim_im_out, + q15_t *bufferA, + q7_t *bufferB) +{ + (void)bufferB; +#if defined(RISCV_MATH_DSP) + /* Run the following code for RISC-V Core with DSP enabled */ + + int16_t i_out_y, i_out_x, i_ker_y, i_ker_x; + + uint16_t im2col_out_pixel_index = 0; + q15_t *pBuffer = bufferA; + q15_t *pOut = Im_out; + q15_t *im_buffer = bufferA; + const q15_t *pA; + int i; + + /* This part implements the im2col function */ + for (i_out_y = 0; i_out_y < dim_im_out; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out; i_out_x++) + { + for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++) + { + for (i_ker_x = i_out_x * stride - padding; i_ker_x < i_out_x * stride - padding + dim_kernel; i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in || i_ker_x < 0 || i_ker_x >= dim_im_in) + { + /* Filling 0 for out-of-bound paddings */ + riscv_fill_q15(0, pBuffer, ch_im_in); + /* memset(pBuffer, 0, sizeof(q15_t)*ch_im_in); */ + } else + { + riscv_copy_q15((q15_t *) Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, pBuffer, ch_im_in); + /* memcpy(pBuffer, (q15_t *) Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, sizeof(q15_t)*ch_im_in); */ + } + pBuffer += ch_im_in; + } + } + + pA = wt; + for (i = 0; i < ch_im_out; i++) + { + q31_t sum = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + const q15_t *pB = im_buffer; + uint16_t colCnt = ch_im_in * dim_kernel * dim_kernel >> 2; +#if __RISCV_XLEN == 64 + while (colCnt) + { + q63_t inA1 = *__SIMD64(pA)++; + q63_t inB1 = *__SIMD64(pB)++; + + sum = __RV_SMALDA(sum, inA1, inB1); + + colCnt--; + } + colCnt = ch_im_in * dim_kernel * dim_kernel & 0x3; +#else + while (colCnt) + { + q31_t inA1 = riscv_nn_read_q15x2_ia(&pA); + q31_t inB1 = riscv_nn_read_q15x2_ia(&pB); + q31_t inA2 = riscv_nn_read_q15x2_ia(&pA); + q31_t inB2 = riscv_nn_read_q15x2_ia(&pB); + + sum = __RV_SMALDA(sum, inA1, inB1); + sum = __RV_SMALDA(sum, inA2, inB2); + + colCnt--; + } + colCnt = ch_im_in * dim_kernel * dim_kernel & 0x3; +#endif /* __RISCV_XLEN == 64 */ + while (colCnt) + { + q15_t inA1 = *pA++; + q15_t inB1 = *pB++; + sum += inA1 * inB1; + colCnt--; + } + *pOut = (q15_t)__SSAT((sum >> out_shift), 16); + pOut++; + } + + /* counter reset */ + pBuffer = im_buffer; + im2col_out_pixel_index++; + } + } + +#else + (void)bufferA; + /* Run the following code as reference implementation for RISC-V Core without DSP */ + int i, j, k, l, m, n; + int conv_out; + int in_row, in_col; + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out; j++) + { + for (k = 0; k < dim_im_out; k++) + { + conv_out = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + for (m = 0; m < dim_kernel; m++) + { + for (n = 0; n < dim_kernel; n++) + { + in_row = stride * j + m - padding; + in_col = stride * k + n - padding; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in && in_col < dim_im_in) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += Im_in[(in_row * dim_im_in + in_col) * ch_im_in + l] * + wt[i * ch_im_in * dim_kernel * dim_kernel + (m * dim_kernel + n) * ch_im_in + l]; + } + } + } + } + Im_out[i + (j * dim_im_out + k) * ch_im_out] = (q15_t)__SSAT((conv_out >> out_shift), 16); + } + } + } + +#endif /* RISCV_MATH_DSP */ + + /* Return to application */ + return RISCV_MATH_SUCCESS; +} + +/** + * @} end of NNConv group + */ diff --git a/components/nmsis/nn/src/ConvolutionFunctions/riscv_convolve_HWC_q15_fast.c b/components/nmsis/nn/src/ConvolutionFunctions/riscv_convolve_HWC_q15_fast.c new file mode 100644 index 00000000..06c19f65 --- /dev/null +++ b/components/nmsis/nn/src/ConvolutionFunctions/riscv_convolve_HWC_q15_fast.c @@ -0,0 +1,274 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_convolve_HWC_q15_fast.c + * Description: Fast Q15 version of convolution + * + * $Date: January 26, 2021 + * $Revision: V.1.0.2 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "riscv_nnfunctions.h" +#include "riscv_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/** + * @brief Fast Q15 convolution function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimention + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * RISCV_MATH_SIZE_MISMATCH or RISCV_MATH_SUCCESS based on the outcome of size checking. + * + * @details + * + * Buffer size: + * + * bufferA size: 2*ch_im_in*dim_kernel*dim_kernel + * + * bufferB size: 0 + * + * Input dimension constraints: + * + * ch_im_in is multiple of 2 + * + * ch_im_out is multiple of 2 + * + */ + +riscv_status riscv_convolve_HWC_q15_fast(const q15_t *Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q15_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q15_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q15_t *Im_out, + const uint16_t dim_im_out, + q15_t *bufferA, + q7_t *bufferB) +{ + (void)bufferB; +#if defined(RISCV_MATH_DSP) + int16_t i_out_y, i_out_x, i_ker_y, i_ker_x; + + q15_t *pBuffer = bufferA; + q15_t *im_buffer = bufferA; + q15_t *pOut = Im_out; + + if (ch_im_in % 2 != 0 || ch_im_out % 2 != 0) + { + /* check if the input dimension meets the constraints */ + return RISCV_MATH_SIZE_MISMATCH; + } + + /* Run the following code for RISC-V Core with DSP enabled */ + + /* This part implements the im2col function */ + for (i_out_y = 0; i_out_y < dim_im_out; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out; i_out_x++) + { + for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++) + { + for (i_ker_x = i_out_x * stride - padding; i_ker_x < i_out_x * stride - padding + dim_kernel; i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in || i_ker_x < 0 || i_ker_x >= dim_im_in) + { + riscv_fill_q15(0, pBuffer, ch_im_in); + /* memset(pBuffer, 0, sizeof(q15_t)*ch_im_in); */ + } else + { + riscv_copy_q15((q15_t *) Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, pBuffer, ch_im_in); + /* memcpy(pBuffer, (q15_t *) Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, sizeof(q15_t)*ch_im_in); */ + } + pBuffer += ch_im_in; + } + } + + if (i_out_x & 0x1) + { + int i; + /* initialize the matrix pointers for A */ + const q15_t *pA = wt; + + /* set up the second output pointers */ + q15_t *pOut2 = pOut + ch_im_out; + + /* this loop over rows in A */ + for (i = 0; i < ch_im_out; i += 2) + { + /* setup pointers for B */ + const q15_t *pB = im_buffer; + const q15_t *pB2 = pB + ch_im_in * dim_kernel * dim_kernel; + + /* aling the second pointer for A */ + const q15_t *pA2 = pA + ch_im_in * dim_kernel * dim_kernel; + + /* init the sum with bias */ + q31_t sum = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)bias[i + 1] << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)bias[i + 1] << bias_shift) + NN_ROUND(out_shift); +#if __RISCV_XLEN == 64 + uint16_t colCnt = ch_im_in * dim_kernel * dim_kernel >> 2; + /* accumulate over the vector */ + while (colCnt) + { + q63_t inA1 = *__SIMD64(pA)++; + q63_t inB1 = *__SIMD64(pB)++; + q63_t inA2 = *__SIMD64(pA2)++; + q63_t inB2 = *__SIMD64(pB2)++; + + sum = __RV_SMALDA(sum , inA1, inB1); + sum2 = __RV_SMALDA(sum2, inA1, inB2); + sum3 = __RV_SMALDA(sum3, inA2, inB1); + sum4 = __RV_SMALDA(sum4, inA2, inB2); + + colCnt--; + } /* while over colCnt */ + colCnt = ch_im_in * dim_kernel * dim_kernel & 0x3; + +#else + uint16_t colCnt = ch_im_in * dim_kernel * dim_kernel >> 1; + /* accumulate over the vector */ + while (colCnt) + { + q31_t inA1 = riscv_nn_read_q15x2_ia(&pA); + q31_t inB1 = riscv_nn_read_q15x2_ia(&pB); + q31_t inA2 = riscv_nn_read_q15x2_ia(&pA2); + q31_t inB2 = riscv_nn_read_q15x2_ia(&pB2); + + sum = __RV_SMALDA(sum , inA1, inB1); + sum2 = __RV_SMALDA(sum2, inA1, inB2); + sum3 = __RV_SMALDA(sum3, inA2, inB1); + sum4 = __RV_SMALDA(sum4, inA2, inB2); + + colCnt--; + } /* while over colCnt */ + colCnt = ch_im_in * dim_kernel * dim_kernel & 0x1; +#endif /* __RISCV_XLEN == 64 */ + while (colCnt) + { + q15_t inA1 = *pA++; + q15_t inB1 = *pB++; + q15_t inA2 = *pA2++; + q15_t inB2 = *pB2++; + + sum += inA1 * inB1; + sum2 += inA1 * inB2; + sum3 += inA2 * inB1; + sum4 += inA2 * inB2; + colCnt--; + } /* while over colCnt */ + *pOut++ = (q15_t)__SSAT(sum >> out_shift, 16); + *pOut++ = (q15_t)__SSAT(sum3 >> out_shift, 16); + *pOut2++ = (q15_t)__SSAT(sum2 >> out_shift, 16); + *pOut2++ = (q15_t)__SSAT(sum4 >> out_shift, 16); + + /* skip the row computed with A2 */ + pA += ch_im_in * dim_kernel * dim_kernel; + } /* for over ch_im_out */ + + pOut += ch_im_out; + /* counter reset */ + pBuffer = im_buffer; + } + } + } + +#else + (void)bufferA; + /* Run the following code as reference implementation for RISC-V Core without DSP */ + int i, j, k, l, m, n; + int conv_out; + int in_row, in_col; + + if (ch_im_in % 2 != 0 || ch_im_out % 2 != 0) + { + /* check if the input dimension meets the constraints */ + return RISCV_MATH_SIZE_MISMATCH; + } + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out; j++) + { + for (k = 0; k < dim_im_out; k++) + { + conv_out = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + for (m = 0; m < dim_kernel; m++) + { + for (n = 0; n < dim_kernel; n++) + { + in_row = stride * j + m - padding; + in_col = stride * k + n - padding; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in && in_col < dim_im_in) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += Im_in[(in_row * dim_im_in + in_col) * ch_im_in + l] * + wt[i * ch_im_in * dim_kernel * dim_kernel + (m * dim_kernel + n) * ch_im_in + l]; + } + } + } + } + Im_out[i + (j * dim_im_out + k) * ch_im_out] = (q15_t)__SSAT((conv_out >> out_shift), 16); + } + } + } + +#endif /* RISCV_MATH_DSP */ + + /* Return to application */ + return RISCV_MATH_SUCCESS; +} + +/** + * @} end of NNConv group + */ diff --git a/components/nmsis/nn/src/ConvolutionFunctions/riscv_convolve_HWC_q15_fast_nonsquare.c b/components/nmsis/nn/src/ConvolutionFunctions/riscv_convolve_HWC_q15_fast_nonsquare.c new file mode 100644 index 00000000..fe62dffc --- /dev/null +++ b/components/nmsis/nn/src/ConvolutionFunctions/riscv_convolve_HWC_q15_fast_nonsquare.c @@ -0,0 +1,330 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_convolve_HWC_q15_fast.c + * Description: Fast Q15 version of convolution + * + * $Date: January 26, 2021 + * $Revision: V.1.0.2 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "riscv_nnfunctions.h" +#include "riscv_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/** + * @brief Fast Q15 convolution function (non-sqaure shape) + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in_x input tensor dimention x + * @param[in] dim_im_in_y input tensor dimention y + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel_x filter kernel size x + * @param[in] dim_kernel_y filter kernel size y + * @param[in] padding_x padding size x + * @param[in] padding_y padding size y + * @param[in] stride_x convolution stride x + * @param[in] stride_y convolution stride y + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out_x output tensor dimension x + * @param[in] dim_im_out_y output tensor dimension y + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * RISCV_MATH_SIZE_MISMATCH or RISCV_MATH_SUCCESS based on the outcome of size checking. + * + * @details + * + * Buffer size: + * + * bufferA size: 2*ch_im_in*dim_kernel*dim_kernel + * + * bufferB size: 0 + * + * Input dimension constraints: + * + * ch_im_in is multiple of 2 + * + * ch_im_out is multiple of 2 + * + */ + +riscv_status riscv_convolve_HWC_q15_fast_nonsquare(const q15_t *Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q15_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q15_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q15_t *Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t *bufferA, + q7_t *bufferB) +{ + (void)bufferB; +#if defined (RISCV_MATH_DSP) || defined (RISCV_VECTOR) + int16_t i_out_y, i_out_x, i_ker_y, i_ker_x; + + q15_t *pBuffer = bufferA; + q15_t *im_buffer = bufferA; + q15_t *pOut = Im_out; + +#if defined(RISCV_VECTOR) + size_t l; + uint32_t blkCnt; + ptrdiff_t bstride; + vint16m4_t va1m4,vb1m4,va2m4,vb2m4; + vint64m1_t vtemp; + l = vsetvl_e64m1(1); + vtemp = vsub_vv_i64m1(vtemp,vtemp, l); +#endif + + if (ch_im_in % 2 != 0 || ch_im_out % 2 != 0) + { + /* check if the input dimension meets the constraints */ + return RISCV_MATH_SIZE_MISMATCH; + } + + /* Run the following code for RISC-V Core with DSP enabled */ + + /* This part implements the im2col function */ + for (i_out_y = 0; i_out_y < dim_im_out_y; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out_x; i_out_x++) + { + for (i_ker_y = i_out_y * stride_y - padding_y; i_ker_y < i_out_y * stride_y - padding_y + dim_kernel_y; + i_ker_y++) + { + for (i_ker_x = i_out_x * stride_x - padding_x; i_ker_x < i_out_x * stride_x - padding_x + dim_kernel_x; + i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in_y || i_ker_x < 0 || i_ker_x >= dim_im_in_x) + { + riscv_fill_q15(0, pBuffer, ch_im_in); + /* memset(pBuffer, 0, sizeof(q15_t)*ch_im_in); */ + } else + { + riscv_copy_q15((q15_t *) Im_in + (i_ker_y * dim_im_in_x + i_ker_x) * ch_im_in, pBuffer, ch_im_in); + /* memcpy(pBuffer, (q15_t *) Im_in + (i_ker_y * dim_im_in_x + i_ker_x) * ch_im_in, sizeof(q15_t)*ch_im_in); */ + } + pBuffer += ch_im_in; + } + } + + if (i_out_x & 0x1) + { + int i; + /* initialize the matrix pointers for A */ + const q15_t *pA = wt; + + /* set up the second output pointers */ + q15_t *pOut2 = pOut + ch_im_out; + + /* this loop over rows in A */ + for (i = 0; i < ch_im_out; i += 2) + { + /* setup pointers for B */ + const q15_t *pB = im_buffer; + const q15_t *pB2 = pB + ch_im_in * dim_kernel_y * dim_kernel_x; + + /* aling the second pointer for A */ + const q15_t *pA2 = pA + ch_im_in * dim_kernel_y * dim_kernel_x; + + /* init the sum with bias */ + q31_t sum = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)bias[i + 1] << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)bias[i + 1] << bias_shift) + NN_ROUND(out_shift); +#if defined(RISCV_VECTOR) + uint16_t colCnt = ch_im_in * dim_kernel_y * dim_kernel_x; + blkCnt = colCnt; + for (; (l = vsetvl_e16m4(blkCnt)) > 0; blkCnt -= l) { + va1m4 = vle16_v_i16m4(pA, l); + vb1m4 = vle16_v_i16m4(pB, l); + va2m4 = vle16_v_i16m4(pA2, l); + vb2m4 = vle16_v_i16m4(pB2, l); + pA += l; + pB += l; + pA2 += l; + pB2 += l; + l = vsetvl_e16m4(blkCnt); + sum += (q31_t)vmv_x_s_i64m1_i64(vwredsum_vs_i32m8_i64m1(vtemp, vwmul_vv_i32m8(va1m4, vb1m4, l), vtemp, l)); + l = vsetvl_e16m4(blkCnt); + sum2 += (q31_t)vmv_x_s_i64m1_i64(vwredsum_vs_i32m8_i64m1(vtemp, vwmul_vv_i32m8(va1m4, vb2m4, l), vtemp, l)); + l = vsetvl_e16m4(blkCnt); + sum3 += (q31_t)vmv_x_s_i64m1_i64(vwredsum_vs_i32m8_i64m1(vtemp, vwmul_vv_i32m8(va2m4, vb1m4, l), vtemp, l)); + l = vsetvl_e16m4(blkCnt); + sum4 += (q31_t)vmv_x_s_i64m1_i64(vwredsum_vs_i32m8_i64m1(vtemp, vwmul_vv_i32m8(va2m4, vb2m4, l), vtemp, l)); + } + *pOut++ = (q15_t) __SSAT(sum >> out_shift, 16); + *pOut++ = (q15_t) __SSAT(sum3 >> out_shift, 16); + *pOut2++ = (q15_t) __SSAT(sum2 >> out_shift, 16); + *pOut2++ = (q15_t) __SSAT(sum4 >> out_shift, 16); + /* skip the row computed with A2 */ + pA += ch_im_in * dim_kernel_y * dim_kernel_x; + } +#else +#if defined (RISCV_MATH_DSP) +#if __RISCV_XLEN == 64 + uint16_t colCnt = ch_im_in * dim_kernel_y * dim_kernel_x >> 2; + /* accumulate over the vector */ + while (colCnt) + { + q63_t inA1 = *__SIMD64(pA)++; + q63_t inB1 = *__SIMD64(pB)++; + q63_t inA2 = *__SIMD64(pA2)++; + q63_t inB2 = *__SIMD64(pB2)++; + + sum = __RV_SMALDA(sum , inA1, inB1); + sum2 = __RV_SMALDA(sum2, inA1, inB2); + sum3 = __RV_SMALDA(sum3, inA2, inB1); + sum4 = __RV_SMALDA(sum4, inA2, inB2); + + colCnt--; + } /* while over colCnt */ + colCnt = ch_im_in * dim_kernel_y * dim_kernel_x & 0x3; + +#else + uint16_t colCnt = ch_im_in * dim_kernel_y * dim_kernel_x >> 1; + /* accumulate over the vector */ + while (colCnt) + { + q31_t inA1 = riscv_nn_read_q15x2_ia(&pA); + q31_t inB1 = riscv_nn_read_q15x2_ia(&pB); + q31_t inA2 = riscv_nn_read_q15x2_ia(&pA2); + q31_t inB2 = riscv_nn_read_q15x2_ia(&pB2); + + sum = __RV_SMALDA(sum , inA1, inB1); + sum2 = __RV_SMALDA(sum2, inA1, inB2); + sum3 = __RV_SMALDA(sum3, inA2, inB1); + sum4 = __RV_SMALDA(sum4, inA2, inB2); + + colCnt--; + } /* while over colCnt */ + colCnt = ch_im_in * dim_kernel_y * dim_kernel_x & 0x1; +#endif /* __RISCV_XLEN == 64 */ +#else + uint16_t colCnt = ch_im_in * dim_kernel_y * dim_kernel_x; +#endif + while (colCnt) + { + q15_t inA1 = *pA++; + q15_t inB1 = *pB++; + q15_t inA2 = *pA2++; + q15_t inB2 = *pB2++; + + sum += inA1 * inB1; + sum2 += inA1 * inB2; + sum3 += inA2 * inB1; + sum4 += inA2 * inB2; + colCnt--; + } /* while over colCnt */ + + *pOut++ = (q15_t) __SSAT(sum >> out_shift, 16); + *pOut++ = (q15_t) __SSAT(sum3 >> out_shift, 16); + *pOut2++ = (q15_t) __SSAT(sum2 >> out_shift, 16); + *pOut2++ = (q15_t) __SSAT(sum4 >> out_shift, 16); + + /* skip the row computed with A2 */ + pA += ch_im_in * dim_kernel_y * dim_kernel_x; + } /* for over ch_im_out */ +#endif + pOut += ch_im_out; + /* counter reset */ + pBuffer = im_buffer; + } + } + } + +#else + (void)bufferA; + /* Run the following code as reference implementation for RISC-V Core without DSP */ + int i, j, k, l, m, n; + int conv_out; + int in_row, in_col; + + if (ch_im_in % 2 != 0 || ch_im_out % 2 != 0) + { + /* check if the input dimension meets the constraints */ + return RISCV_MATH_SIZE_MISMATCH; + } + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out_y; j++) + { + for (k = 0; k < dim_im_out_x; k++) + { + conv_out = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + for (m = 0; m < dim_kernel_y; m++) + { + for (n = 0; n < dim_kernel_x; n++) + { + in_row = stride_y * j + m - padding_y; + in_col = stride_x * k + n - padding_x; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in_y && in_col < dim_im_in_x) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += Im_in[(in_row * dim_im_in_x + in_col) * ch_im_in + l] * + wt[i * ch_im_in * dim_kernel_x * dim_kernel_y + (m * dim_kernel_x + n) * ch_im_in + + l]; + } + } + } + } + Im_out[i + (j * dim_im_out_x + k) * ch_im_out] = (q15_t)__SSAT((conv_out >> out_shift), 16); + } + } + } + +#endif /* RISCV_MATH_DSP */ + + /* Return to application */ + return RISCV_MATH_SUCCESS; +} +/** + * @} end of NNConv group + */ diff --git a/components/nmsis/nn/src/ConvolutionFunctions/riscv_convolve_HWC_q7_RGB.c b/components/nmsis/nn/src/ConvolutionFunctions/riscv_convolve_HWC_q7_RGB.c new file mode 100644 index 00000000..a4a38836 --- /dev/null +++ b/components/nmsis/nn/src/ConvolutionFunctions/riscv_convolve_HWC_q7_RGB.c @@ -0,0 +1,265 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_convolve_HWC_q7_RGB.c + * Description: Q7 version of convolution for RGB image + * + * $Date: January 26, 2021 + * $Revision: V.1.0.2 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "riscv_nnfunctions.h" +#include "riscv_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/** + * @brief Q7 convolution function for RGB image + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimention + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * RISCV_MATH_SIZE_MISMATCH or RISCV_MATH_SUCCESS based on the outcome of size checking. + * + * @details + * + * Buffer size: + * + * bufferA size: 2*ch_im_in*dim_kernel*dim_kernel + * + * bufferB size: 0 + * + * Input dimension constraints: + * + * ch_im_in equals 3 + * + * This kernel is written exclusively for convolution with ch_im_in + * equals 3. This applies on the first layer of CNNs which has input + * image with RGB format. + */ + +riscv_status riscv_convolve_HWC_q7_RGB(const q7_t *Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q7_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q7_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t *Im_out, + const uint16_t dim_im_out, + q15_t *bufferA, + q7_t *bufferB) +{ + (void)bufferB; +#if defined (RISCV_MATH_DSP) || defined (RISCV_VECTOR) + /* Run the following code for RISC-V Core with DSP enabled */ + int16_t i_out_y, i_out_x, i_ker_y, i_ker_x; + + /* + * Here we use bufferA as q15_t internally as computation are done with q15_t level + * im2col are done to output in q15_t format from q7_t input + */ + q7_t *pBuffer = (q7_t *)bufferA; + q7_t *pOut = Im_out; + + // check if number of input channels is 3 + if (ch_im_in != 3) + { + return RISCV_MATH_SIZE_MISMATCH; + } + // This part implements the im2col function + /* This part implements the im2col function */ + for (i_out_y = 0; i_out_y < dim_im_out; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out; i_out_x++) + { + for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++) + { + for (i_ker_x = i_out_x * stride - padding; i_ker_x < i_out_x * stride - padding + dim_kernel; i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in || i_ker_x < 0 || i_ker_x >= dim_im_in) + { + /* Filling 0 for out-of-bound paddings */ + + riscv_fill_q7(0, pBuffer, ch_im_in); + /* memset(pBuffer, 0, sizeof(q15_t)*ch_im_in); */ + } else + { + /* Copying the pixel data to column */ + + riscv_q7_to_q7_no_shift((q7_t *) + Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, pBuffer, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + /* Computation is filed for every 2 columns */ + if (pBuffer == (q7_t *)bufferA + 2 * ch_im_in * dim_kernel * dim_kernel) + { + pOut = + riscv_nn_mat_mult_kernel_q7(wt, (q7_t *)bufferA, + ch_im_out, + ch_im_in * + dim_kernel * dim_kernel, bias_shift, out_shift, bias, pOut); + + /* counter reset */ + + pBuffer = (q7_t *)bufferA; + } + } + } + + /* left-over because odd number of output pixels */ + if (pBuffer != (q7_t *)bufferA) + { + const q7_t *pA = wt; + int i; + + for (i = 0; i < ch_im_out; i++) + { + /* Load the accumulator with bias first */ + q31_t sum = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + + /* Point to the beging of the im2col buffer */ + q7_t *pB = (q7_t *)bufferA; +#if defined (RISCV_MATH_DSP) +#if __RISCV_XLEN == 64 + /* basically each time it process 4 entries */ + uint16_t colCnt = ch_im_in * dim_kernel * dim_kernel >> 3; + q63_t sum64 = 0; + while (colCnt) + { + //pA = (const q7_t *)read_and_pad_reordered((void *)pA, &inA1, &inA2); + q63_t inB1 = *__SIMD64(pB)++; + q63_t inA1 = *__SIMD64(pA)++; + sum64 = __RV_SMAQA(sum64, inA1, inB1); + colCnt--; + } + sum = sum + (q31_t)(sum64 & 0xFFFFFFFF) + (q31_t)((sum64 & 0xFFFFFFFF00000000)>>32); + colCnt = (ch_im_in * dim_kernel * dim_kernel) & 0x7; + +#else + /* Each time it process 4 entries */ + uint16_t colCnt = ch_im_in * dim_kernel * dim_kernel >> 2; + + while (colCnt) + { + + q31_t inB1 = *__SIMD32(pB)++; + q31_t inA1 = *__SIMD32(pA)++; + sum = __RV_SMAQA(sum, inA1, inB1); + + + colCnt--; + } + colCnt = ch_im_in * dim_kernel * dim_kernel & 0x3; +#endif /* __RISCV_XLEN == 64 */ +#else + uint16_t colCnt = ch_im_in * dim_kernel * dim_kernel; +#endif + while (colCnt) + { + q7_t inA1 = *pA++; + q15_t inB1 = *pB++; + sum += inA1 * inB1; + colCnt--; + } + *pOut++ = (q7_t)__SSAT((sum >> out_shift), 8); + } + } +#else + (void)bufferA; + /* Run the following code as reference implementation for RISC-V Core without DSP */ + int i, j, k, l, m, n; + int conv_out; + int in_row, in_col; + + // check if number of input channels is 3 + if (ch_im_in != 3) + { + return RISCV_MATH_SIZE_MISMATCH; + } + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out; j++) + { + for (k = 0; k < dim_im_out; k++) + { + conv_out = (bias[i] << bias_shift) + NN_ROUND(out_shift); + for (m = 0; m < dim_kernel; m++) + { + for (n = 0; n < dim_kernel; n++) + { + /* if-for implementation */ + in_row = stride * j + m - padding; + in_col = stride * k + n - padding; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in && in_col < dim_im_in) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += Im_in[(in_row * dim_im_in + in_col) * ch_im_in + l] * + wt[i * ch_im_in * dim_kernel * dim_kernel + (m * dim_kernel + n) * ch_im_in + l]; + } + } + } + } + Im_out[i + (j * dim_im_out + k) * ch_im_out] = (q7_t)__SSAT((conv_out >> out_shift), 8); + } + } + } + +#endif /* RISCV_MATH_DSP */ + + /* Return to application */ + return (RISCV_MATH_SUCCESS); +} + +/** + * @} end of NNConv group + */ diff --git a/components/nmsis/nn/src/ConvolutionFunctions/riscv_convolve_HWC_q7_basic.c b/components/nmsis/nn/src/ConvolutionFunctions/riscv_convolve_HWC_q7_basic.c new file mode 100644 index 00000000..bf24f1c3 --- /dev/null +++ b/components/nmsis/nn/src/ConvolutionFunctions/riscv_convolve_HWC_q7_basic.c @@ -0,0 +1,250 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_convolve_HWC_q7_basic.c + * Description: Q7 version of convolution + * + * $Date: 09. October 2020 + * $Revision: V.1.0.1 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "riscv_nnfunctions.h" +#include "riscv_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/** + * @brief Basic Q7 convolution function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimention + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns RISCV_MATH_SUCCESS + * + * @details + * + * Buffer size: + * + * bufferA size: 2*ch_im_in*dim_kernel*dim_kernel + * + * bufferB size: 0 + * + * This basic version is designed to work for any input tensor and weight + * dimension. + */ + +riscv_status riscv_convolve_HWC_q7_basic(const q7_t *Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q7_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q7_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t *Im_out, + const uint16_t dim_im_out, + q15_t *bufferA, + q7_t *bufferB) +{ + (void)bufferB; +#if defined (RISCV_MATH_DSP) || defined (RISCV_VECTOR) + /* Run the following code for RISC-V Core with DSP enabled */ + + int16_t i_out_y, i_out_x, i_ker_y, i_ker_x; + + /* + * Here we use bufferA as q15_t internally as computation are done with q15_t level + * im2col are done to output in q15_t format from q7_t input + */ + + q7_t *pOut = Im_out; + q7_t *pBuffer = (q7_t *)bufferA; + + /* This part implements the im2col function */ + for (i_out_y = 0; i_out_y < dim_im_out; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out; i_out_x++) + { + for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++) + { + for (i_ker_x = i_out_x * stride - padding; i_ker_x < i_out_x * stride - padding + dim_kernel; i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in || i_ker_x < 0 || i_ker_x >= dim_im_in) + { + /* Filling 0 for out-of-bound paddings */ + + riscv_fill_q7(0, pBuffer, ch_im_in); + /* memset(pBuffer, 0, sizeof(q15_t)*ch_im_in); */ + } else + { + /* Copying the pixel data to column */ + + riscv_q7_to_q7_no_shift((q7_t *) + Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, pBuffer, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + /* Computation is filed for every 2 columns */ + if (pBuffer == (q7_t *)bufferA + 2 * ch_im_in * dim_kernel * dim_kernel) + { + pOut = + riscv_nn_mat_mult_kernel_q7(wt, (q7_t *)bufferA, + ch_im_out, + ch_im_in * + dim_kernel * dim_kernel, bias_shift, out_shift, bias, pOut); + + /* counter reset */ + + pBuffer = (q7_t *)bufferA; + } + } + } + + /* left-over because odd number of output pixels */ + if (pBuffer != (q7_t *)bufferA) + { + const q7_t *pA = wt; + int i; + + for (i = 0; i < ch_im_out; i++) + { + /* Load the accumulator with bias first */ + q31_t sum = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + + /* Point to the beging of the im2col buffer */ + q7_t *pB = (q7_t *)bufferA; +#if defined (RISCV_VECTOR) + uint16_t colCnt = ch_im_in * dim_kernel * dim_kernel; +#else +#if __RISCV_XLEN == 64 + /* Each time it process 4 entries */ + uint16_t colCnt = ch_im_in * dim_kernel * dim_kernel >> 3; + q63_t sum64 = 0; + while (colCnt) + { + + q63_t inB1 = *__SIMD64(pB)++; + q63_t inA1 = *__SIMD64(pA)++; + sum64 = __RV_SMAQA(sum64, inA1, inB1); + + colCnt--; + } + sum = sum + (q31_t)(sum64 & 0xFFFFFFFF) + (q31_t)((sum64 & 0xFFFFFFFF00000000)>>32); + colCnt = ch_im_in * dim_kernel * dim_kernel & 0x7; + +#else + /* Each time it process 4 entries */ + uint16_t colCnt = ch_im_in * dim_kernel * dim_kernel >> 2; + + while (colCnt) + { + + q31_t inB1 = *__SIMD32(pB)++; + q31_t inA1 = *__SIMD32(pA)++; + sum = __RV_SMAQA(sum, inA1, inB1); + + + colCnt--; + } + colCnt = ch_im_in * dim_kernel * dim_kernel & 0x3; +#endif /* __RISCV_XLEN == 64 */ +#endif + while (colCnt) + { + q7_t inA1 = *pA++; + q15_t inB1 = *pB++; + sum += inA1 * inB1; + colCnt--; + } + *pOut++ = (q7_t)__SSAT((sum >> out_shift), 8); + } + } +#else + /* Run the following code as reference implementation for RISC-V Core without DSP */ + + int i, j, k, l, m, n; + int conv_out; + int in_row, in_col; + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out; j++) + { + for (k = 0; k < dim_im_out; k++) + { + conv_out = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + for (m = 0; m < dim_kernel; m++) + { + for (n = 0; n < dim_kernel; n++) + { + // if-for implementation + in_row = stride * j + m - padding; + in_col = stride * k + n - padding; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in && in_col < dim_im_in) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += Im_in[(in_row * dim_im_in + in_col) * ch_im_in + l] * + wt[i * ch_im_in * dim_kernel * dim_kernel + (m * dim_kernel + n) * ch_im_in + l]; + } + } + } + } + Im_out[i + (j * dim_im_out + k) * ch_im_out] = (q7_t)__SSAT((conv_out >> out_shift), 8); + } + } + } + +#endif /* RISCV_MATH_DSP */ + + /* Return to application */ + return RISCV_MATH_SUCCESS; +} + +/** + * @} end of NNConv group + */ diff --git a/components/nmsis/nn/src/ConvolutionFunctions/riscv_convolve_HWC_q7_basic_nonsquare.c b/components/nmsis/nn/src/ConvolutionFunctions/riscv_convolve_HWC_q7_basic_nonsquare.c new file mode 100644 index 00000000..df90e6f2 --- /dev/null +++ b/components/nmsis/nn/src/ConvolutionFunctions/riscv_convolve_HWC_q7_basic_nonsquare.c @@ -0,0 +1,258 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_convolve_HWC_q7_basic.c + * Description: Q7 version of convolution + * + * $Date: January 26, 2021 + * $Revision: V.1.0.2 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "riscv_nnfunctions.h" +#include "riscv_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/** + * @brief Basic Q7 convolution function (non-sqaure shape) + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in_x input tensor dimention x + * @param[in] dim_im_in_y input tensor dimention y + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel_x filter kernel size x + * @param[in] dim_kernel_y filter kernel size y + * @param[in] padding_x padding size x + * @param[in] padding_y padding size y + * @param[in] stride_x convolution stride x + * @param[in] stride_y convolution stride y + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out_x output tensor dimension x + * @param[in] dim_im_out_y output tensor dimension y + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns RISCV_MATH_SUCCESS + */ + +riscv_status riscv_convolve_HWC_q7_basic_nonsquare(const q7_t *Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q7_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q7_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t *Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t *bufferA, + q7_t *bufferB) +{ + (void)bufferB; +#if defined (RISCV_MATH_DSP) || defined (RISCV_VECTOR) + /* Run the following code for RISC-V Core with DSP enabled */ + + int16_t i_out_y, i_out_x, i_ker_y, i_ker_x; + + /* + * Here we use bufferA as q15_t internally as computation are done with q15_t level + * im2col are done to output in q15_t format from q7_t input + */ + q7_t *pBuffer = (q7_t *)bufferA; + q7_t *pOut = Im_out; + + /* This part implements the im2col function */ + for (i_out_y = 0; i_out_y < dim_im_out_y; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out_x; i_out_x++) + { + for (i_ker_y = i_out_y * stride_y - padding_y; i_ker_y < i_out_y * stride_y - padding_y + dim_kernel_y; + i_ker_y++) + { + for (i_ker_x = i_out_x * stride_x - padding_x; i_ker_x < i_out_x * stride_x - padding_x + dim_kernel_x; + i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in_y || i_ker_x < 0 || i_ker_x >= dim_im_in_x) + { + /* Filling 0 for out-of-bound paddings */ + riscv_fill_q7(0, pBuffer, ch_im_in); + /* memset(pBuffer, 0, sizeof(q15_t)*ch_im_in); */ + } else + { + /* Copying the pixel data to column */ + riscv_q7_to_q7_no_shift((q7_t *) + Im_in + (i_ker_y * dim_im_in_x + i_ker_x) * ch_im_in, pBuffer, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + /* Computation is filed for every 2 columns */ + if (pBuffer == (q7_t *)bufferA + 2 * ch_im_in * dim_kernel_y * dim_kernel_x) + { + pOut = + riscv_nn_mat_mult_kernel_q7(wt, (q7_t*)bufferA, + ch_im_out, + ch_im_in * + dim_kernel_y * dim_kernel_x, bias_shift, out_shift, bias, pOut); + + /* counter reset */ + pBuffer = (q7_t *)bufferA; + } + } + } + + /* left-over because odd number of output pixels */ + if (pBuffer != (q7_t *)bufferA) + { + const q7_t *pA = wt; + int i; + + for (i = 0; i < ch_im_out; i++) + { + /* Load the accumulator with bias first */ + q31_t sum = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + + /* Point to the beging of the im2col buffer */ + q7_t *pB = (q7_t *)bufferA; +#if defined (RISCV_MATH_DSP) +#if __RISCV_XLEN == 64 + /* Each time it process 4 entries */ + uint16_t colCnt = ch_im_in * dim_kernel_y * dim_kernel_x >> 3; + q63_t sum64 = 0; + while (colCnt) + { + q63_t inB1 = *__SIMD64(pB)++; + q63_t inA1 = *__SIMD64(pA)++; + sum64 = __RV_KMADA(sum64, inA1, inB1); + colCnt--; + } + sum = sum + (q31_t)(sum64 & 0xFFFFFFFF) + (q31_t)((sum64 & 0xFFFFFFFF00000000)>>32); + colCnt = ch_im_in * dim_kernel_y * dim_kernel_x & 0x7; +#else + /* Each time it process 4 entries */ + uint16_t colCnt = ch_im_in * dim_kernel_y * dim_kernel_x >> 2; + + while (colCnt) + { + + + q31_t inB1 = *__SIMD32(pB)++; + q31_t inA1 = *__SIMD32(pA)++; + sum = __RV_KMADA(sum, inA1, inB1); + colCnt--; + + + /* q31_t inA1, inA2; + q31_t inB1, inB2; + + pA = read_and_pad(pA, &inA1, &inA2); + + inB1 = riscv_nn_read_q15x2_ia(&pB); + sum = __SMLAD(inA1, inB1, sum); + inB2 = riscv_nn_read_q15x2_ia(&pB); + + sum = __SMLAD(inA2, inB2, sum); + + colCnt--;*/ + } + colCnt = ch_im_in * dim_kernel_y * dim_kernel_x & 0x3; +#endif /* __RISCV_XLEN == 64 */ +#else + uint16_t colCnt = ch_im_in * dim_kernel_y * dim_kernel_x; +#endif /*ndef RISCV_VECTOR*/ + while (colCnt) + { + q7_t inA1 = *pA++; + q15_t inB1 = *pB++; + sum += inA1 * inB1; + colCnt--; + } + *pOut++ = (q7_t)__SSAT((sum >> out_shift), 8); + } + } +#else + /* Run the following code as reference implementation for RISC-V Core without DSP */ + (void)bufferA; + int i, j, k, l, m, n; + int conv_out; + int in_row, in_col; + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out_y; j++) + { + for (k = 0; k < dim_im_out_x; k++) + { + conv_out = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + for (m = 0; m < dim_kernel_y; m++) + { + for (n = 0; n < dim_kernel_x; n++) + { + // if-for implementation + in_row = stride_y * j + m - padding_y; + in_col = stride_x * k + n - padding_x; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in_y && in_col < dim_im_in_x) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += Im_in[(in_row * dim_im_in_x + in_col) * ch_im_in + l] * + wt[i * ch_im_in * dim_kernel_y * dim_kernel_x + (m * dim_kernel_x + n) * ch_im_in + + l]; + } + } + } + } + Im_out[i + (j * dim_im_out_x + k) * ch_im_out] = (q7_t)__SSAT((conv_out >> out_shift), 8); + } + } + } + +#endif /* RISCV_MATH_DSP */ + + /* Return to application */ + return RISCV_MATH_SUCCESS; +} + +/** + * @} end of NNConv group + */ diff --git a/components/nmsis/nn/src/ConvolutionFunctions/riscv_convolve_HWC_q7_fast.c b/components/nmsis/nn/src/ConvolutionFunctions/riscv_convolve_HWC_q7_fast.c new file mode 100644 index 00000000..b59f5944 --- /dev/null +++ b/components/nmsis/nn/src/ConvolutionFunctions/riscv_convolve_HWC_q7_fast.c @@ -0,0 +1,418 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_convolve_HWC_q7_fast.c + * Description: Fast Q7 version of convolution + * + * $Date: January 26, 2021 + * $Revision: V.1.0.2 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "riscv_nnfunctions.h" +#include "riscv_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/** + * @brief Fast Q7 convolution function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimention + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * RISCV_MATH_SIZE_MISMATCH or RISCV_MATH_SUCCESS based on the outcome of size checking. + * + * @details + * + * Buffer size: + * + * bufferA size: 2*ch_im_in*dim_kernel*dim_kernel + * + * bufferB size: 0 + * + * Input dimension constraints: + * + * ch_im_in is multiple of 4 ( because of the SIMD32 read and swap ) + * + * ch_im_out is multiple of 2 ( bacause 2x2 mat_mult kernel ) + * + * The im2col converts the Q7 tensor input into Q15 column, which is stored in + * bufferA. There is reordering happenning during this im2col process with + * riscv_q7_to_q15_reordered_no_shift. For every four elements, the second and + * third elements are swapped. + * + * The computation kernel riscv_nn_mat_mult_kernel_q7_q15_reordered does the + * GEMM computation with the reordered columns. + * + * To speed-up the determination of the padding condition, we split the + * computation into 3x3 parts, i.e., {top, mid, bottom} X {left, mid, right}. + * This reduces the total number of boundary condition checks and improves + * the data copying performance. + */ + +riscv_status riscv_convolve_HWC_q7_fast(const q7_t *Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q7_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q7_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t *Im_out, + const uint16_t dim_im_out, + q15_t *bufferA, + q7_t *bufferB) +{ + (void)bufferB; +#if defined (RISCV_MATH_DSP) || defined (RISCV_VECTOR) + /* Run the following code for RISC-V Core with DSP enabled */ + + int16_t i_out_y, i_out_x, i_ker_y, i_ker_x; + + /* + * Here we use bufferA as q15_t internally as computation are done with q15_t level + * im2col are done to output in q15_t format from q7_t input + */ + + q7_t *pBuffer = (q7_t *)bufferA; + q7_t *pOut = Im_out; + + if (ch_im_in % 4 != 0 || ch_im_out % 2 != 0) + { + /* check if the input dimension meets the constraints */ + return RISCV_MATH_SIZE_MISMATCH; + } + + /* + * Here we split the entire matrix into three regions depending on the padding situation + * Top: i_out_y from 0 to padding - 1 + * Middle: i_out_y from padding to dim_im_out-padding-1 + * Bottom: i_out_y from dim_im_out-padding to dim_im_out-1 + */ + + /* top part */ + for (i_out_y = 0; i_out_y < padding; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out; i_out_x++) + { + /* This part implements the im2col function */ + for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++) + { + for (i_ker_x = i_out_x * stride - padding; i_ker_x < i_out_x * stride - padding + dim_kernel; i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in || i_ker_x < 0 || i_ker_x >= dim_im_in) + { + riscv_fill_q7(0, pBuffer, ch_im_in); + /* memset(pBuffer, 0, sizeof(q15_t)*ch_im_in); */ + } else + { + riscv_q7_to_q7_reordered_no_shift + ((q7_t *) Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, pBuffer, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + if (pBuffer == (q7_t *)bufferA + 2 * ch_im_in * dim_kernel * dim_kernel) + { + pOut = + riscv_nn_mat_mult_kernel_q7_reordered(wt, + (q7_t *)bufferA, + ch_im_out, + ch_im_in + * + dim_kernel * dim_kernel, bias_shift, out_shift, bias, pOut); + /* counter reset */ + pBuffer = (q7_t *)bufferA; + } + } + } + + /* middle part, here we also divide the x into left, mid and right */ + for (; i_out_y < dim_im_out - padding; i_out_y++) + { + + /* left part */ + for (i_out_x = 0; i_out_x < padding; i_out_x++) + { + /* This part implements the im2col function */ + for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++) + { + for (i_ker_x = i_out_x * stride - padding; i_ker_x < i_out_x * stride - padding + dim_kernel; i_ker_x++) + { + if (i_ker_x < 0 || i_ker_x >= dim_im_in) + { + riscv_fill_q7(0, pBuffer, ch_im_in); + /* memset(pBuffer, 0, sizeof(q15_t)*ch_im_in); */ + } else + { + riscv_q7_to_q7_reordered_no_shift + ((q7_t *) Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, pBuffer, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + if (pBuffer == (q7_t *)bufferA + 2 * ch_im_in * dim_kernel * dim_kernel) + { + pOut = + riscv_nn_mat_mult_kernel_q7_reordered(wt, + (q7_t *)bufferA, + ch_im_out, + ch_im_in + * + dim_kernel * dim_kernel, bias_shift, out_shift, bias, pOut); + /* counter reset */ + pBuffer = (q7_t *)bufferA; + } + } + + /* mid part */ + for (; i_out_x < dim_im_out - padding; i_out_x++) + { + /* This part implements the im2col function */ + for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++) + { + riscv_q7_to_q7_reordered_no_shift((q7_t *) Im_in + + + (i_ker_y * + dim_im_in + + i_out_x * + stride - padding) * ch_im_in, pBuffer, ch_im_in * dim_kernel); + pBuffer += ch_im_in * dim_kernel; + } + + if (pBuffer == (q7_t *)bufferA + 2 * ch_im_in * dim_kernel * dim_kernel) + { + pOut = + riscv_nn_mat_mult_kernel_q7_reordered(wt, + (q7_t *)bufferA, + ch_im_out, + ch_im_in + * + dim_kernel * dim_kernel, bias_shift, out_shift, bias, pOut); + /* counter reset */ + pBuffer = (q7_t *)bufferA; + } + } + + /* right part */ + for (; i_out_x < dim_im_out; i_out_x++) + { + /* This part implements the im2col function */ + for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++) + { + for (i_ker_x = i_out_x * stride - padding; i_ker_x < i_out_x * stride - padding + dim_kernel; i_ker_x++) + { + if (i_ker_x < 0 || i_ker_x >= dim_im_in) + { + riscv_fill_q7(0, pBuffer, ch_im_in); + /* memset(pBuffer, 0, sizeof(q15_t)*ch_im_in); */ + } else + { + riscv_q7_to_q7_reordered_no_shift + ((q7_t *) Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, pBuffer, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + if (pBuffer == (q7_t *)bufferA + 2 * ch_im_in * dim_kernel * dim_kernel) + { + pOut = + riscv_nn_mat_mult_kernel_q7_reordered(wt, + (q7_t *)bufferA, + ch_im_out, + ch_im_in + * + dim_kernel * dim_kernel, bias_shift, out_shift, bias, pOut); + /* counter reset */ + pBuffer = (q7_t *)bufferA; + } + } + } + + for (; i_out_y < dim_im_out; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out; i_out_x++) + { + /* This part implements the im2col function */ + for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++) + { + for (i_ker_x = i_out_x * stride - padding; i_ker_x < i_out_x * stride - padding + dim_kernel; i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in || i_ker_x < 0 || i_ker_x >= dim_im_in) + { + riscv_fill_q7(0, pBuffer, ch_im_in); + /* memset(pBuffer, 0, sizeof(q15_t)*ch_im_in); */ + } else + { + riscv_q7_to_q7_reordered_no_shift + ((q7_t *) Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, pBuffer, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + if (pBuffer == (q7_t *)bufferA + 2 * ch_im_in * dim_kernel * dim_kernel) + { + pOut = + riscv_nn_mat_mult_kernel_q7_reordered(wt, + (q7_t *)bufferA, + ch_im_out, + ch_im_in + * + dim_kernel * dim_kernel, bias_shift, out_shift, bias, pOut); + /* counter reset */ + pBuffer = (q7_t *)bufferA; + } + } + } + + /* check if there is left-over for compute */ + if (pBuffer != (q7_t *)bufferA) + { + const q7_t *pA = wt; + int i; + + for (i = 0; i < ch_im_out; i++) + { + q31_t sum = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + q7_t *pB = (q7_t *)bufferA; +#if defined (RISCV_MATH_DSP) +#if __RISCV_XLEN == 64 + /* basically each time it process 4 entries */ + uint16_t colCnt = ch_im_in * dim_kernel * dim_kernel >> 3; + q63_t sum64 = 0; + while (colCnt) + { + //pA = (const q7_t *)read_and_pad_reordered((void *)pA, &inA1, &inA2); + q63_t inB1 = *__SIMD64(pB)++; + q63_t inA1 = *__SIMD64(pA)++; + sum64 = __RV_SMAQA(sum64, inA1, inB1); + colCnt--; + } + sum = sum + (q31_t)(sum64 & 0xFFFFFFFF) + (q31_t)((sum64 & 0xFFFFFFFF00000000)>>32); + colCnt = (ch_im_in * dim_kernel * dim_kernel) & 0x7; + +#else + /* each time it process 4 entries */ + uint16_t colCnt = ch_im_in * dim_kernel * dim_kernel >> 2; + + while (colCnt) + { + q31_t inB1 = *__SIMD32(pB)++; + q31_t inA1 = *__SIMD32(pA)++; + sum = __RV_SMAQA(sum, inA1, inB1); + + colCnt--; + } + colCnt = ch_im_in * dim_kernel * dim_kernel & 0x3; +#endif /* __RISCV_XLEN == 64 */ +#else + uint16_t colCnt = ch_im_in * dim_kernel * dim_kernel; +#endif + while (colCnt) + { + q7_t inA1 = *pA++; + q15_t inB1 = *pB++; + sum += inA1 * inB1; + colCnt--; + } + *pOut = (q7_t)__SSAT((sum >> out_shift), 8); + pOut++; + } + } +#else + (void)bufferA; + /* Run the following code as reference implementation for RISC-V Core without DSP */ + int i, j, k, l, m, n; + int conv_out; + int in_row, in_col; + + if (ch_im_in % 4 != 0 || ch_im_out % 2 != 0) + { + /* check if the input dimension meets the constraints */ + return RISCV_MATH_SIZE_MISMATCH; + } + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out; j++) + { + for (k = 0; k < dim_im_out; k++) + { + conv_out = (bias[i] << bias_shift) + NN_ROUND(out_shift); + for (m = 0; m < dim_kernel; m++) + { + for (n = 0; n < dim_kernel; n++) + { + // if-for implementation + in_row = stride * j + m - padding; + in_col = stride * k + n - padding; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in && in_col < dim_im_in) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += Im_in[(in_row * dim_im_in + in_col) * ch_im_in + l] * + wt[i * ch_im_in * dim_kernel * dim_kernel + (m * dim_kernel + n) * ch_im_in + l]; + } + } + } + } + Im_out[i + (j * dim_im_out + k) * ch_im_out] = (q7_t)__SSAT((conv_out >> out_shift), 8); + } + } + } + +#endif /* RISCV_MATH_DSP */ + + /* Return to application */ + return RISCV_MATH_SUCCESS; +} + +/** + * @} end of NNConv group + */ diff --git a/components/nmsis/nn/src/ConvolutionFunctions/riscv_convolve_HWC_q7_fast_nonsquare.c b/components/nmsis/nn/src/ConvolutionFunctions/riscv_convolve_HWC_q7_fast_nonsquare.c new file mode 100644 index 00000000..cc4fc069 --- /dev/null +++ b/components/nmsis/nn/src/ConvolutionFunctions/riscv_convolve_HWC_q7_fast_nonsquare.c @@ -0,0 +1,400 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_convolve_HWC_q7_fast_nonsquare.c + * Description: Fast Q7 version of convolution (non-sqaure shape) + * + * $Date: January 26, 2021 + * $Revision: V.1.0.2 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "riscv_nnfunctions.h" +#include "riscv_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/** + * @brief Fast Q7 convolution function (non-sqaure shape) + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in_x input tensor dimention x + * @param[in] dim_im_in_y input tensor dimention y + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel_x filter kernel size x + * @param[in] dim_kernel_y filter kernel size y + * @param[in] padding_x padding size x + * @param[in] padding_y padding size y + * @param[in] stride_x convolution stride x + * @param[in] stride_y convolution stride y + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out_x output tensor dimension x + * @param[in] dim_im_out_y output tensor dimension y + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * RISCV_MATH_SIZE_MISMATCH or RISCV_MATH_SUCCESS based on the outcome of size checking. + * + * This function is the version with full list of optimization tricks, but with + * some constraints: + * ch_im_in is multiple of 4 + * ch_im_out is multiple of 2 + */ + +riscv_status riscv_convolve_HWC_q7_fast_nonsquare(const q7_t *Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q7_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q7_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t *Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t *bufferA, + q7_t *bufferB) +{ + (void)bufferB; +#if defined (RISCV_MATH_DSP) || defined (RISCV_VECTOR) + /* Run the following code for RISC-V Core with DSP enabled */ + + int16_t i_out_y, i_out_x, i_ker_y, i_ker_x; + + /* ----------------------- + * Here we use bufferA as q15_t internally as computation are done with q15_t level + * im2col are done to output in q15_t format from q7_t input + */ + + q7_t *pBuffer = (q7_t *)bufferA; + q7_t *pOut = Im_out; + + if (ch_im_in % 4 != 0 || ch_im_out % 2 != 0) + { + /* check if the input dimension meets the constraints */ + return RISCV_MATH_SIZE_MISMATCH; + } + + /* + * Here we split the entire matrix into three regions depending on the padding situation + * Top: i_out_y from 0 to padding - 1 + * Middle: i_out_y from padding to dim_im_out-padding-1 + * Bottom: i_out_y from dim_im_out-padding to dim_im_out-1 + */ + + /* top part */ + for (i_out_y = 0; i_out_y < padding_y; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out_x; i_out_x++) + { + /* This part implements the im2col function */ + for (i_ker_y = i_out_y * stride_y - padding_y; i_ker_y < i_out_y * stride_y - padding_y + dim_kernel_y; + i_ker_y++) + { + for (i_ker_x = i_out_x * stride_x - padding_x; i_ker_x < i_out_x * stride_x - padding_x + dim_kernel_x; + i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in_y || i_ker_x < 0 || i_ker_x >= dim_im_in_x) + { + riscv_fill_q7(0, pBuffer, ch_im_in); + /* memset(pBuffer, 0, sizeof(q15_t)*ch_im_in); */ + } else + { + riscv_q7_to_q7_reordered_no_shift((q7_t *) Im_in + (i_ker_y * dim_im_in_x + i_ker_x) * ch_im_in, + pBuffer, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + if (pBuffer == (q7_t *)bufferA + 2 * ch_im_in * dim_kernel_x * dim_kernel_y) + { + pOut = + riscv_nn_mat_mult_kernel_q7_reordered(wt, (q7_t *)bufferA, ch_im_out, ch_im_in * dim_kernel_x * dim_kernel_y, + bias_shift, out_shift, bias, pOut); + /* counter reset */ + pBuffer = (q7_t *)bufferA; + } + } + } + + /* middle part, here we also divide the x into left, mid and right */ + for (; i_out_y < dim_im_out_y - padding_y; i_out_y++) + { + + /* left part */ + for (i_out_x = 0; i_out_x < padding_x; i_out_x++) + { + /* This part implements the im2col function */ + for (i_ker_y = i_out_y * stride_y - padding_y; i_ker_y < i_out_y * stride_y - padding_y + dim_kernel_y; + i_ker_y++) + { + for (i_ker_x = i_out_x * stride_x - padding_x; i_ker_x < i_out_x * stride_x - padding_x + dim_kernel_x; + i_ker_x++) + { + if (i_ker_x < 0 || i_ker_x >= dim_im_in_x) + { + riscv_fill_q7(0, pBuffer, ch_im_in); + /* memset(pBuffer, 0, sizeof(q15_t)*ch_im_in); */ + } else + { + riscv_q7_to_q7_reordered_no_shift((q7_t *) Im_in + (i_ker_y * dim_im_in_x + i_ker_x) * ch_im_in, + pBuffer, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + if (pBuffer == (q7_t *)bufferA + 2 * ch_im_in * dim_kernel_x * dim_kernel_y) + { + pOut = + riscv_nn_mat_mult_kernel_q7_reordered(wt, (q7_t *)bufferA, ch_im_out, ch_im_in * dim_kernel_x * dim_kernel_y, + bias_shift, out_shift, bias, pOut); + /* counter reset */ + pBuffer = (q7_t *)bufferA; + } + } + + /* mid part */ + for (; i_out_x < dim_im_out_x - padding_x; i_out_x++) + { + /* This part implements the im2col function */ + for (i_ker_y = i_out_y * stride_y - padding_y; i_ker_y < i_out_y * stride_y - padding_y + dim_kernel_y; + i_ker_y++) + { + riscv_q7_to_q7_reordered_no_shift((q7_t *) Im_in + + (i_ker_y * dim_im_in_x + i_out_x * stride_x - padding_x) * ch_im_in, + pBuffer, ch_im_in * dim_kernel_x); + pBuffer += ch_im_in * dim_kernel_x; + } + + if (pBuffer == (q7_t *)bufferA + 2 * ch_im_in * dim_kernel_x * dim_kernel_y) + { + pOut = + riscv_nn_mat_mult_kernel_q7_reordered(wt, (q7_t *)bufferA, ch_im_out, ch_im_in * dim_kernel_x * dim_kernel_y, + bias_shift, out_shift, bias, pOut); + /* counter reset */ + pBuffer = (q7_t *)bufferA; + } + } + + /* right part */ + for (; i_out_x < dim_im_out_x; i_out_x++) + { + /* This part implements the im2col function */ + for (i_ker_y = i_out_y * stride_y - padding_y; i_ker_y < i_out_y * stride_y - padding_y + dim_kernel_y; + i_ker_y++) + { + for (i_ker_x = i_out_x * stride_x - padding_x; i_ker_x < i_out_x * stride_x - padding_x + dim_kernel_x; + i_ker_x++) + { + if (i_ker_x < 0 || i_ker_x >= dim_im_in_x) + { + riscv_fill_q7(0, pBuffer, ch_im_in); + /* memset(pBuffer, 0, sizeof(q15_t)*ch_im_in); */ + } else + { + riscv_q7_to_q7_reordered_no_shift((q7_t *) Im_in + (i_ker_y * dim_im_in_x + i_ker_x) * ch_im_in, + pBuffer, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + if (pBuffer == (q7_t *)bufferA + 2 * ch_im_in * dim_kernel_x * dim_kernel_y) + { + pOut = + riscv_nn_mat_mult_kernel_q7_reordered(wt, (q7_t *)bufferA, ch_im_out, ch_im_in * dim_kernel_x * dim_kernel_y, + bias_shift, out_shift, bias, pOut); + /* counter reset */ + pBuffer = (q7_t *)bufferA; + } + } + } + + for (; i_out_y < dim_im_out_y; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out_x; i_out_x++) + { + /* This part implements the im2col function */ + for (i_ker_y = i_out_y * stride_y - padding_y; i_ker_y < i_out_y * stride_y - padding_y + dim_kernel_y; + i_ker_y++) + { + for (i_ker_x = i_out_x * stride_x - padding_x; i_ker_x < i_out_x * stride_x - padding_x + dim_kernel_x; + i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in_y || i_ker_x < 0 || i_ker_x >= dim_im_in_x) + { + riscv_fill_q7(0, pBuffer, ch_im_in); + /* memset(pBuffer, 0, sizeof(q15_t)*ch_im_in); */ + } else + { + riscv_q7_to_q7_reordered_no_shift((q7_t *) Im_in + (i_ker_y * dim_im_in_x + i_ker_x) * ch_im_in, + pBuffer, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + if (pBuffer == (q7_t *)bufferA + 2 * ch_im_in * dim_kernel_x * dim_kernel_y) + { + pOut = + riscv_nn_mat_mult_kernel_q7_reordered(wt, (q7_t *)bufferA, ch_im_out, ch_im_in * dim_kernel_x * dim_kernel_y, + bias_shift, out_shift, bias, pOut); + /* counter reset */ + pBuffer = (q7_t *)bufferA; + } + } + } + + /* check if there is left-over for compute */ + if (pBuffer != (q7_t *)bufferA) + { + const q7_t *pA = wt; + int i; + for (i = 0; i < ch_im_out; i++) + { + q31_t sum = ((q31_t)(bias[i]) << bias_shift) + NN_ROUND(out_shift); + q7_t *pB = (q7_t *)bufferA; +#if defined (RISCV_MATH_DSP) +#if __RISCV_XLEN == 64 + /* basically each time it process 4 entries */ + uint16_t colCnt = ch_im_in * dim_kernel_x * dim_kernel_y >> 3; + q63_t sum64 = 0; + while (colCnt) + { + //pA = (const q7_t *)read_and_pad_reordered((void *)pA, &inA1, &inA2); + q63_t inB1 = *__SIMD64(pB)++; + q63_t inA1 = *__SIMD64(pA)++; + sum64 = __RV_SMAQA(sum64, inA1, inB1); + colCnt--; + } + sum = sum + (q31_t)(sum64 & 0xFFFFFFFF) + (q31_t)((sum64 & 0xFFFFFFFF00000000)>>32); + colCnt = (ch_im_in * dim_kernel_y * dim_kernel_x) & 0x7; +#else + /* basically each time it process 4 entries */ + uint16_t colCnt = ch_im_in * dim_kernel_x * dim_kernel_y >> 2; + + while (colCnt) + { + + //pA = (const q7_t *)read_and_pad_reordered((void *)pA, &inA1, &inA2); + q31_t inB1 = *__SIMD32(pB)++; + q31_t inA1 = *__SIMD32(pA)++; + sum = __RV_SMAQA(sum, inA1, inB1); + + /*colCnt--; + inB1 = *__SIMD32(pB)++; + sum = __SMLAD(inA1, inB1, sum); + inB2 = riscv_nn_read_q15x2_ia(&pB); + sum = __SMLAD(inA2, inB2, sum); + */ + colCnt--; + } + colCnt = (ch_im_in * dim_kernel_y * dim_kernel_x) & 0x3; +#endif /* __RISCV_XLEN == 64 */ +#else + uint16_t colCnt = ch_im_in * dim_kernel_x * dim_kernel_y; +#endif /*ndef RISCV_VECTOR*/ + while (colCnt) + { + q7_t inA1 = *pA++; + q15_t inB1 = *pB++; + sum += inA1 * inB1; + colCnt--; + } + *pOut = (q7_t)__SSAT((sum >> out_shift), 8); + pOut++; + } + } + +#else + (void)bufferA; + /* Run the following code as reference implementation for RISC-V Core without DSP */ + int i, j, k, l, m, n; + int conv_out; + int in_row, in_col; + + if (ch_im_in % 4 != 0 || ch_im_out % 2 != 0) + { + /* check if the input dimension meets the constraints */ + return RISCV_MATH_SIZE_MISMATCH; + } + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out_y; j++) + { + for (k = 0; k < dim_im_out_x; k++) + { + conv_out = ((q31_t)(bias[i]) << bias_shift) + NN_ROUND(out_shift); + for (m = 0; m < dim_kernel_y; m++) + { + for (n = 0; n < dim_kernel_x; n++) + { + /* if-for implementation */ + in_row = stride_y * j + m - padding_y; + in_col = stride_x * k + n - padding_x; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in_y && in_col < dim_im_in_x) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += Im_in[(in_row * dim_im_in_x + in_col) * ch_im_in + l] * + wt[i * ch_im_in * dim_kernel_y * dim_kernel_x + (m * dim_kernel_x + n) * ch_im_in + + l]; + } + } + } + } + Im_out[i + (j * dim_im_out_x + k) * ch_im_out] = (q7_t)__SSAT((conv_out >> out_shift), 8); + } + } + } + +#endif /* RISCV_MATH_DSP */ + + /* Return to application */ + return RISCV_MATH_SUCCESS; +} + +/** + * @} end of NNConv group + */ diff --git a/components/nmsis/nn/src/ConvolutionFunctions/riscv_convolve_s8.c b/components/nmsis/nn/src/ConvolutionFunctions/riscv_convolve_s8.c new file mode 100644 index 00000000..e138842f --- /dev/null +++ b/components/nmsis/nn/src/ConvolutionFunctions/riscv_convolve_s8.c @@ -0,0 +1,637 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_convolve_s8.c + * Description: s8 version of convolution using symmetric quantization. + * + * $Date: January 26, 2021 + * $Revision: V.2.0.4 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "riscv_nnfunctions.h" +#include "riscv_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/* + * Basic s8 convolution function. + * + * Refer header file for details. Optimal use case for the DSP implementation is when input and output channels + * are multiples of 4 or atleast greater than 4. + * + */ + +// riscv_status riscv_convolve_s8(const nmsis_nn_context *ctx, +// const nmsis_nn_conv_params *conv_params, +// const nmsis_nn_per_channel_quant_params *quant_params, +// const nmsis_nn_dims *input_dims, +// const q7_t *input_data, +// const nmsis_nn_dims *filter_dims, +// const q7_t *filter_data, +// const nmsis_nn_dims *bias_dims, +// const int32_t *bias_data, +// const nmsis_nn_dims *output_dims, +// q7_t *output_data) +// { +// q7_t *buffer_a = (q7_t *)ctx->buf; + +// const uint16_t input_batches = input_dims->n; +// const uint16_t input_x = input_dims->w; +// const uint16_t input_y = input_dims->h; +// const uint16_t input_ch = input_dims->c; +// const uint16_t kernel_x = filter_dims->w; +// const uint16_t kernel_y = filter_dims->h; +// const uint16_t output_x = output_dims->w; +// const uint16_t output_y = output_dims->h; +// const uint16_t output_ch = output_dims->c; + +// const uint16_t pad_x = conv_params->padding.w; +// const uint16_t pad_y = conv_params->padding.h; +// const uint16_t stride_x = conv_params->stride.w; +// const uint16_t stride_y = conv_params->stride.h; + +// const int32_t input_offset = conv_params->input_offset; +// const int32_t out_offset = conv_params->output_offset; +// const int32_t out_activation_min = conv_params->activation.min; +// const int32_t out_activation_max = conv_params->activation.max; +// int32_t *output_mult = quant_params->multiplier; +// int32_t *output_shift = quant_params->shift; + +// int i_batch; +// for (i_batch = 0; i_batch < input_batches; i_batch++) +// { +// #if defined(RISCV_MATH_MVEI) +// /* Generate upto four columns from the input tensor a GEMM computation */ +// q7_t *im2col_buf = (q7_t *)buffer_a; +// q7_t *out = output_data; +// int32_t buffer_fill_cnt = 0; +// int32_t padded = 0; +// const int32_t num_elem = kernel_x * kernel_y * input_ch; + +// /* This part implements the im2col function */ +// for (int i_out_y = 0; i_out_y < output_y; i_out_y++) +// { +// for (int i_out_x = 0; i_out_x < output_x; i_out_x++) +// { +// for (int i_ker_y = i_out_y * stride_y - pad_y; i_ker_y < i_out_y * stride_y - pad_y + kernel_y; +// i_ker_y++) +// { +// for (int i_ker_x = i_out_x * stride_x - pad_x; i_ker_x < i_out_x * stride_x - pad_x + kernel_x; +// i_ker_x++) +// { +// if (i_ker_y < 0 || i_ker_y >= input_y || i_ker_x < 0 || i_ker_x >= input_x) +// { +// memset(im2col_buf, (int8_t)-input_offset, sizeof(q7_t) * input_ch); +// padded = 1; +// } +// else +// { +// riscv_memcpy_q7(im2col_buf, input_data + (i_ker_y * input_x + i_ker_x) * input_ch, input_ch); +// } +// im2col_buf += input_ch; +// } +// } + +// buffer_fill_cnt++; + +// /* Computation is filed for every 4 columns */ +// if (buffer_fill_cnt == 4 && (padded == 0)) +// { +// buffer_fill_cnt = 0; +// for (int i_out_ch = 0; i_out_ch < output_ch; i_out_ch++) +// { +// int32_t sum_row; +// int32_t acc[4]; + +// (void)riscv_nn_mat_mul_core_4x_s8( +// num_elem, num_elem, (q7_t *)buffer_a, filter_data + num_elem * i_out_ch, &sum_row, acc); +// int32x4_t s_offset = vdupq_n_s32(sum_row); + +// int32x4_t res = vldrwq_s32(acc); +// s_offset = vmulq_n_s32(s_offset, input_offset); +// if (bias_data) +// { +// res = vaddq_n_s32(res, bias_data[i_out_ch]); +// } +// res = vaddq_s32(res, s_offset); +// res = riscv_requantize_mve(res, output_mult[i_out_ch], output_shift[i_out_ch]); +// res = vaddq_n_s32(res, out_offset); + +// res = vmaxq_s32(res, vdupq_n_s32(out_activation_min)); +// res = vminq_s32(res, vdupq_n_s32(out_activation_max)); + +// const uint32x4_t scatter_offset = {0, output_ch, output_ch * 2, output_ch * 3}; +// vstrbq_scatter_offset_s32(out, scatter_offset, res); +// out++; +// } +// out += (3 * output_ch); +// im2col_buf = (q7_t *)buffer_a; +// } +// else if (buffer_fill_cnt == 4 && (padded != 0)) +// { +// buffer_fill_cnt = 0; +// out = riscv_nn_mat_mult_s8(filter_data, +// (q7_t *)buffer_a, +// output_ch, +// 4, +// output_shift, +// output_mult, +// out_offset, +// input_offset, +// 0, +// out_activation_min, +// out_activation_max, +// num_elem, +// bias_data, +// out); + +// im2col_buf = (q7_t *)buffer_a; +// padded = 0; +// } +// } +// } +// /* Handle left over columns */ +// if (buffer_fill_cnt != 0) +// { +// out = riscv_nn_mat_mult_s8(filter_data, +// (q7_t *)buffer_a, +// output_ch, +// buffer_fill_cnt, +// output_shift, +// output_mult, +// out_offset, +// input_offset, +// 0, +// out_activation_min, +// out_activation_max, +// num_elem, +// bias_data, +// out); +// } + +// #elif defined(RISCV_MATH_DSP) || defined(RISCV_VECTOR) +// (void)bias_dims; +// int32_t i_out_y, i_out_x, i_ker_y, i_ker_x; + +// /* Generate two columns from the input tensor a GEMM computation */ +// q7_t *two_column_buf = (q7_t *)buffer_a; +// q7_t *out = output_data; + +// /* This part implements the im2col function */ +// for (i_out_y = 0; i_out_y < output_y; i_out_y++) +// { +// for (i_out_x = 0; i_out_x < output_x; i_out_x++) +// { +// for (i_ker_y = i_out_y * stride_y - pad_y; i_ker_y < i_out_y * stride_y - pad_y + kernel_y; i_ker_y++) +// { +// for (i_ker_x = i_out_x * stride_x - pad_x; i_ker_x < i_out_x * stride_x - pad_x + kernel_x; +// i_ker_x++) +// { +// if (i_ker_y < 0 || i_ker_y >= input_y || i_ker_x < 0 || i_ker_x >= input_x) +// { +// /* Filling 0 for out-of-bound paddings */ +// riscv_fill_q7(0, two_column_buf, input_ch); +// // memset(two_column_buf, 0, sizeof(q15_t) * input_ch); +// } +// else +// { +// /* Copying the pixel data to column */ +// riscv_offset_q7(input_data + (i_ker_y * input_x + i_ker_x) * input_ch, input_offset, two_column_buf, input_ch); +// } +// two_column_buf += input_ch; +// } +// } + +// /* Computation is filed for every 2 columns */ +// if (two_column_buf == (q7_t *)buffer_a + 2 * input_ch * kernel_y * kernel_x) +// { +// out = +// riscv_nn_mat_mult_kernel_s8(filter_data, +// (q7_t *)buffer_a, +// output_ch, +// output_shift, +// output_mult, +// out_offset, +// out_activation_min, +// out_activation_max, +// input_ch * kernel_y * kernel_x, +// bias_data, +// out); + +// /* counter reset */ +// two_column_buf = (q7_t *)buffer_a; +// } +// } +// } + +// /* left-over because odd number of output pixels */ +// if (two_column_buf != (q7_t *)buffer_a) +// { +// const q7_t *ker_a = filter_data; +// int i; + +// for (i = 0; i < output_ch; i++) +// { +// /* Load the accumulator with bias first */ +// q31_t sum = 0; +// if (bias_data) +// { +// sum = bias_data[i]; +// } + +// /* Point to the beginning of the im2col buffer where the input is available as a rearranged column */ +// const q7_t *ip_as_col = (q7_t *)buffer_a; + +// #if defined(RISCV_MATH_DSP) +// /* 4 multiply and accumulates are done in one loop. */ +// uint16_t col_count = (input_ch * kernel_y * kernel_x) >> 2; + +// while (col_count) +// { +// q31_t ker_a1 = *__SIMD32(ker_a)++; +// q31_t ip_b1 = *__SIMD32(ip_as_col)++; + +// sum = __RV_SMAQA(sum, ker_a1, ip_b1); + +// col_count--; +// } +// /* Handle left over mac */ +// col_count = input_ch * kernel_y * kernel_x & 0x3; +// while (col_count) +// { +// q7_t ker_a1 = *ker_a++; +// q15_t ip_b1 = *ip_as_col++; +// sum += ker_a1 * ip_b1; +// col_count--; +// } +// #else +// #if defined (RISCV_VECTOR) && ( (__XLEN != 32) || (__FLEN != 32) ) +// q31_t ch_0_out_0,ch_0_out_1; +// uint32_t blkCnt = (input_ch * kernel_y * kernel_x); /* Loop counter */ +// size_t l; +// vint8m4_t ker_a1; +// vint8m4_t ip_b1; +// vint16m8_t vch00i16m8; +// vint32m1_t vch00i32m1; +// vint32m1_t vtemp00m1,vtemp01m1; +// l = vsetvl_e8m4(1); +// vtemp00m1 = vmv_v_x_i32m1(0, l); +// vtemp01m1 = vmv_v_x_i32m1(0, l); +// vch00i32m1 = vmv_v_x_i32m1(0, l); +// for (; (l = vsetvl_e8m4(blkCnt)) > 0; blkCnt -= l) { +// ker_a1 = vle8_v_i8m4(ker_a, l); +// ip_b1 = vle8_v_i8m4(ip_as_col, l); +// ker_a += l; +// ip_as_col += l; +// vch00i16m8 = vwmul_vv_i16m8(ip_b1, ker_a1, l); +// vch00i32m1 = vadd_vv_i32m1(vwredsum_vs_i16m8_i32m1(vtemp00m1, vch00i16m8, vtemp01m1, l), vch00i32m1, l); +// } +// vsetvl_e32m1(1); +// sum += (q31_t)vmv_x_s_i32m1_i32(vch00i32m1); +// #else +// uint16_t col_count = (input_ch * kernel_y * kernel_x); +// while (col_count) +// { +// q7_t ker_a1 = *ker_a++; +// q15_t ip_b1 = *ip_as_col++; +// sum += ker_a1 * ip_b1; +// col_count--; +// } +// #endif /*defined (RISCV_VECTOR)*/ +// #endif + +// sum = riscv_nn_requantize(sum, output_mult[i], output_shift[i]); +// sum += out_offset; +// sum = MAX(sum, out_activation_min); +// sum = MIN(sum, out_activation_max); +// *out++ = (q7_t)sum; +// } +// } +// #else +// /* Run the following code as reference implementation for RISC-V Core without DSP */ +// (void)buffer_a; +// int32_t i_out_ch, i_out_y, i_out_x, i_input_ch, i_ker_y, i_ker_x; +// int32_t conv_out; + +// for (i_out_ch = 0; i_out_ch < output_ch; i_out_ch++) +// { +// for (i_out_y = 0; i_out_y < output_y; i_out_y++) +// { +// for (i_out_x = 0; i_out_x < output_x; i_out_x++) +// { +// conv_out = 0; + +// const int32_t base_idx_y = stride_y * i_out_y - pad_y; +// const int32_t base_idx_x = stride_x * i_out_x - pad_x; + +// const int32_t ker_y_start = MAX(0, -base_idx_y); +// const int32_t ker_x_start = MAX(0, -base_idx_x); + +// const int32_t ker_y_end = MIN(kernel_y, input_y - base_idx_y); +// const int32_t ker_x_end = MIN(kernel_x, input_x - base_idx_x); + +// for (i_ker_y = ker_y_start; i_ker_y < ker_y_end; i_ker_y++) +// { +// for (i_ker_x = ker_x_start; i_ker_x < ker_x_end; i_ker_x++) +// { +// const int32_t in_row = base_idx_y + i_ker_y; +// const int32_t in_col = base_idx_x + i_ker_x; +// for (i_input_ch = 0; i_input_ch < input_ch; i_input_ch++) +// { +// conv_out += +// (input_data[(in_row * input_x + in_col) * input_ch + i_input_ch] + input_offset) * +// filter_data[i_out_ch * input_ch * kernel_y * kernel_x + +// (i_ker_y * kernel_x + i_ker_x) * input_ch + i_input_ch]; +// } +// } +// } +// if (bias_data) +// { +// conv_out += bias_data[i_out_ch]; +// } +// conv_out = riscv_nn_requantize(conv_out, output_mult[i_out_ch], output_shift[i_out_ch]); +// conv_out += out_offset; +// conv_out = MAX(conv_out, out_activation_min); +// conv_out = MIN(conv_out, out_activation_max); +// output_data[i_out_ch + (i_out_y * output_x + i_out_x) * output_ch] = (int8_t)conv_out; +// } +// } +// } +// #endif +// /* Advance to the next batch */ +// input_data += (input_x * input_y * input_ch); +// output_data += (output_x * output_y * output_ch); +// } + +// /* Return to application */ +// return RISCV_MATH_SUCCESS; +// } + +// int32_t riscv_convolve_s8_get_buffer_size(const nmsis_nn_dims *input_dims, const nmsis_nn_dims *filter_dims) +// { +// #if defined(RISCV_MATH_DSP) +// return (2 * input_dims->c * filter_dims->w * filter_dims->h) * (int32_t)sizeof(int16_t); +// #else +// (void)input_dims; +// (void)filter_dims; +// return 0; +// #endif +// } + + +riscv_status riscv_convolve_s8(const nmsis_nn_context *ctx, + const nmsis_nn_conv_params *conv_params, + const nmsis_nn_per_channel_quant_params *quant_params, + const nmsis_nn_dims *input_dims, + const q7_t *input_data, + const nmsis_nn_dims *filter_dims, + const q7_t *filter_data, + const nmsis_nn_dims *bias_dims, + const int32_t *bias_data, + const nmsis_nn_dims *output_dims, + q7_t *output_data) +{ + (void)bias_dims; + q15_t *buffer_a = (q15_t *)ctx->buf; + + const uint16_t input_batches = input_dims->n; + const uint16_t input_x = input_dims->w; + const uint16_t input_y = input_dims->h; + const uint16_t input_ch = input_dims->c; + const uint16_t kernel_x = filter_dims->w; + const uint16_t kernel_y = filter_dims->h; + const uint16_t output_x = output_dims->w; + const uint16_t output_y = output_dims->h; + const uint16_t output_ch = output_dims->c; + + const uint16_t pad_x = conv_params->padding.w; + const uint16_t pad_y = conv_params->padding.h; + const uint16_t stride_x = conv_params->stride.w; + const uint16_t stride_y = conv_params->stride.h; + + const int32_t input_offset = conv_params->input_offset; + const int32_t out_offset = conv_params->output_offset; + const int32_t out_activation_min = conv_params->activation.min; + const int32_t out_activation_max = conv_params->activation.max; + int32_t *output_mult = quant_params->multiplier; + int32_t *output_shift = quant_params->shift; + + int i_batch; + for (i_batch = 0; i_batch < input_batches; i_batch++) + { +#if defined(RISCV_MATH_DSP) + int32_t i_out_y, i_out_x, i_ker_y, i_ker_x; + + /* Generate two columns from the input tensor a GEMM computation */ + q15_t *two_column_buf = buffer_a; + q7_t *out = output_data; + + /* This part implements the im2col function */ + for (i_out_y = 0; i_out_y < output_y; i_out_y++) + { + for (i_out_x = 0; i_out_x < output_x; i_out_x++) + { + for (i_ker_y = i_out_y * stride_y - pad_y; i_ker_y < i_out_y * stride_y - pad_y + kernel_y; i_ker_y++) + { + for (i_ker_x = i_out_x * stride_x - pad_x; i_ker_x < i_out_x * stride_x - pad_x + kernel_x; + i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= input_y || i_ker_x < 0 || i_ker_x >= input_x) + { + /* Filling 0 for out-of-bound paddings */ + memset(two_column_buf, 0, sizeof(q15_t) * input_ch); + } + else + { + /* Copying the pixel data to column */ + riscv_q7_to_q15_with_offset(input_data + (i_ker_y * input_x + i_ker_x) * input_ch, + two_column_buf, + input_ch, + input_offset); + } + two_column_buf += input_ch; + } + } + + /* Computation is filed for every 2 columns */ + if (two_column_buf == buffer_a + 2 * input_ch * kernel_y * kernel_x) + { + out = riscv_nn_mat_mult_kernel_s8_s16(filter_data, + buffer_a, + output_ch, + output_shift, + output_mult, + out_offset, + out_activation_min, + out_activation_max, + input_ch * kernel_y * kernel_x, + bias_data, + out); + + /* counter reset */ + two_column_buf = buffer_a; + } + } + } + + /* left-over because odd number of output pixels */ + if (two_column_buf != buffer_a) + { + const q7_t *ker_a = filter_data; + int i; + + for (i = 0; i < output_ch; i++) + { + /* Load the accumulator with bias first */ + q31_t sum = 0; + if (bias_data) + { + sum = bias_data[i]; + } + + /* Point to the beginning of the im2col buffer where the input is available as a rearranged column */ + const q15_t *ip_as_col = buffer_a; + + /* 4 multiply and accumulates are done in one loop. */ + uint16_t col_count = (input_ch * kernel_y * kernel_x) >> 2; + + while (col_count) + { + q31_t ker_a1, ker_a2; + q31_t ip_b1, ip_b2; + + // ker_a = read_and_pad(ker_a, &ker_a1, &ker_a2); + q31_t inA = riscv_nn_read_q7x4_ia(&ker_a); + ker_a1 = __RV_SUNPKD810(inA); + ker_a2 = __RV_SUNPKD832(inA); + + ip_b1 = riscv_nn_read_q15x2_ia(&ip_as_col); + sum = __RV_KMADA(sum, ker_a1, ip_b1); + ip_b2 = riscv_nn_read_q15x2_ia(&ip_as_col); + sum = __RV_KMADA(sum, ker_a2, ip_b2); + + col_count--; + } + /* Handle left over mac */ + col_count = input_ch * kernel_y * kernel_x & 0x3; + while (col_count) + { + q7_t ker_a1 = *ker_a++; + q15_t ip_b1 = *ip_as_col++; + sum += ker_a1 * ip_b1; + col_count--; + } + + sum = riscv_nn_requantize(sum, output_mult[i], output_shift[i]); + sum += out_offset; + sum = MAX(sum, out_activation_min); + sum = MIN(sum, out_activation_max); + *out++ = (q7_t)sum; + } + } +#else + /* Run the following code as reference implementation for RISC-V Core without DSP */ + (void)buffer_a; + int32_t i_out_ch, i_out_y, i_out_x, i_input_ch, i_ker_y, i_ker_x; + int32_t conv_out; + + for (i_out_ch = 0; i_out_ch < output_ch; i_out_ch++) + { + for (i_out_y = 0; i_out_y < output_y; i_out_y++) + { + for (i_out_x = 0; i_out_x < output_x; i_out_x++) + { + conv_out = 0; + + const int32_t base_idx_y = stride_y * i_out_y - pad_y; + const int32_t base_idx_x = stride_x * i_out_x - pad_x; + + const int32_t ker_y_start = MAX(0, -base_idx_y); + const int32_t ker_x_start = MAX(0, -base_idx_x); + + const int32_t ker_y_end = MIN(kernel_y, input_y - base_idx_y); + const int32_t ker_x_end = MIN(kernel_x, input_x - base_idx_x); + + for (i_ker_y = ker_y_start; i_ker_y < ker_y_end; i_ker_y++) + { + for (i_ker_x = ker_x_start; i_ker_x < ker_x_end; i_ker_x++) + { + const int32_t in_row = base_idx_y + i_ker_y; + const int32_t in_col = base_idx_x + i_ker_x; + for (i_input_ch = 0; i_input_ch < input_ch; i_input_ch++) + { + conv_out += + (input_data[(in_row * input_x + in_col) * input_ch + i_input_ch] + input_offset) * + filter_data[i_out_ch * input_ch * kernel_y * kernel_x + + (i_ker_y * kernel_x + i_ker_x) * input_ch + i_input_ch]; + } + } + } + if (bias_data) + { + conv_out += bias_data[i_out_ch]; + } + conv_out = riscv_nn_requantize(conv_out, output_mult[i_out_ch], output_shift[i_out_ch]); + conv_out += out_offset; + conv_out = MAX(conv_out, out_activation_min); + conv_out = MIN(conv_out, out_activation_max); + output_data[i_out_ch + (i_out_y * output_x + i_out_x) * output_ch] = (int8_t)conv_out; + } + } + } +#endif + /* Advance to the next batch */ + input_data += (input_x * input_y * input_ch); + output_data += (output_x * output_y * output_ch); + } + + /* Return to application */ + return RISCV_MATH_SUCCESS; +} + +int32_t riscv_convolve_s8_get_buffer_size(const nmsis_nn_dims *input_dims, const nmsis_nn_dims *filter_dims) +{ +#if defined(RISCV_MATH_DSP) + return (2 * input_dims->c * filter_dims->w * filter_dims->h) * (int32_t)sizeof(int16_t); +#else + (void)input_dims; + (void)filter_dims; + return 0; +#endif +} + + + + + +/** + * @} end of NNConv group + */ diff --git a/components/nmsis/nn/src/ConvolutionFunctions/riscv_convolve_wrapper_s8.c b/components/nmsis/nn/src/ConvolutionFunctions/riscv_convolve_wrapper_s8.c new file mode 100644 index 00000000..a6fe9db1 --- /dev/null +++ b/components/nmsis/nn/src/ConvolutionFunctions/riscv_convolve_wrapper_s8.c @@ -0,0 +1,132 @@ +/* + * Copyright (C) 2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_convolve_wrapper_s8.c + * Description: s8 convolution layer wrapper function with the main purpose to call the optimal kernel available in + * nmsis-nn to perform the convolution. + * + * $Date: 09. October 2020 + * $Revision: V.1.0.1 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "riscv_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/* + * Convolution layer + * + * Refer header file for details. + * + */ + +riscv_status riscv_convolve_wrapper_s8(const nmsis_nn_context *ctx, + const nmsis_nn_conv_params *conv_params, + const nmsis_nn_per_channel_quant_params *quant_params, + const nmsis_nn_dims *input_dims, + const q7_t *input_data, + const nmsis_nn_dims *filter_dims, + const q7_t *filter_data, + const nmsis_nn_dims *bias_dims, + const int32_t *bias_data, + const nmsis_nn_dims *output_dims, + q7_t *output_data) +{ + if ((conv_params->padding.w == 0) && (conv_params->padding.h == 0) && (input_dims->c % 4 == 0) && + (conv_params->stride.w == 1) && (conv_params->stride.h == 1) && (filter_dims->w == 1) && (filter_dims->h == 1)) + { + return riscv_convolve_1x1_s8_fast(ctx, + conv_params, + quant_params, + input_dims, + input_data, + filter_dims, + filter_data, + bias_dims, + bias_data, + output_dims, + output_data); + } + else if ((output_dims->h == 1) && (input_dims->h == 1) && (filter_dims->h == 1) && (output_dims->w % 4 == 0) && + (input_dims->n == 1)) + { + return riscv_convolve_1_x_n_s8(ctx, + conv_params, + quant_params, + input_dims, + input_data, + filter_dims, + filter_data, + bias_dims, + bias_data, + output_dims, + output_data); + } + else + { + return riscv_convolve_s8(ctx, + conv_params, + quant_params, + input_dims, + input_data, + filter_dims, + filter_data, + bias_dims, + bias_data, + output_dims, + output_data); + } +} + +int32_t riscv_convolve_wrapper_s8_get_buffer_size(const nmsis_nn_conv_params *conv_params, + const nmsis_nn_dims *input_dims, + const nmsis_nn_dims *filter_dims, + const nmsis_nn_dims *output_dims) +{ + if ((conv_params->padding.w == 0) && (conv_params->padding.h == 0) && (input_dims->c % 4 == 0) && + (conv_params->stride.w == 1) && (conv_params->stride.h == 1) && (filter_dims->w == 1) && (filter_dims->h == 1)) + { + return riscv_convolve_1x1_s8_fast_get_buffer_size(input_dims); + } + else if ((output_dims->h == 1) && (input_dims->h == 1) && (filter_dims->h == 1) && (output_dims->w % 4 == 0) && + (input_dims->n == 1)) + { + return riscv_convolve_1_x_n_s8_get_buffer_size(input_dims, filter_dims); + } + else + { + return riscv_convolve_s8_get_buffer_size(input_dims, filter_dims); + } +} + +/** + * @} end of NNConv group + */ diff --git a/components/nmsis/nn/src/ConvolutionFunctions/riscv_depthwise_conv_3x3_s8.c b/components/nmsis/nn/src/ConvolutionFunctions/riscv_depthwise_conv_3x3_s8.c new file mode 100644 index 00000000..c8e01c82 --- /dev/null +++ b/components/nmsis/nn/src/ConvolutionFunctions/riscv_depthwise_conv_3x3_s8.c @@ -0,0 +1,264 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_depthwise_conv_3x3_s8.c + * Description: Optimized s8 depthwise convolution function for channel + * multiplier of 1 and 3x3 kernel size. + * + * $Date: 09. October 2020 + * $Revision: V.2.0.1 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "riscv_nnfunctions.h" +#include "riscv_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/* + * Optimized s8 depthwise convolution function with constraint that + * in_channel == out_channel and kernel_x == kernel_y == 3 with pads at most 1 + * + * Refer prototype header file for details. + * + */ + +riscv_status riscv_depthwise_conv_3x3_s8(const nmsis_nn_context *ctx, + const nmsis_nn_dw_conv_params *dw_conv_params, + const nmsis_nn_per_channel_quant_params *quant_params, + const nmsis_nn_dims *input_dims, + const q7_t *input, + const nmsis_nn_dims *filter_dims, + const q7_t *kernel, + const nmsis_nn_dims *bias_dims, + const int32_t *bias, + const nmsis_nn_dims *output_dims, + q7_t *output) +{ + (void)ctx; + (void)bias_dims; + + const int32_t input_x = input_dims->w; + const int32_t input_y = input_dims->h; + const int32_t input_ch = input_dims->c; + const int32_t output_ch = output_dims->c; + const int32_t pad_x = dw_conv_params->padding.w; + const int32_t pad_y = dw_conv_params->padding.h; + const int32_t stride_x = dw_conv_params->stride.w; + const int32_t stride_y = dw_conv_params->stride.h; + const int32_t *output_shift = quant_params->shift; + const int32_t *output_mult = quant_params->multiplier; + const int32_t output_x = output_dims->w; + const int32_t output_y = output_dims->h; + const int32_t output_offset = dw_conv_params->output_offset; + const int32_t input_offset = dw_conv_params->input_offset; + const int32_t output_activation_min = dw_conv_params->activation.min; + const int32_t output_activation_max = dw_conv_params->activation.max; + +#if defined(RISCV_VECTOR) + uint32_t blkCnt_v; + size_t l; + vint8m1_t v_in, v_ker; + vint32m4_t v_buff; + vint8m1_t v_a, v_b; + vfloat32m1_t v_temp; + l = vsetvl_e32m1(1); + v_temp = vfsub_vv_f32m1(v_temp, v_temp, l); +#endif + + /* Check input constraints input_ch == output_ch */ + if (input_ch != output_ch) + { + return RISCV_MATH_SIZE_MISMATCH; + } + /* Check input constraints pad_x <= 1 */ + if (pad_x > 1 || filter_dims->w != 3 || filter_dims->h != 3) + { + return RISCV_MATH_ARGUMENT_ERROR; + } + + for (int32_t in_h = -pad_y, out_h = 0, out_idx = 0; out_h < output_y; in_h += stride_y, ++out_h) + { + for (int32_t in_w = -pad_x, out_w = 0, ker_h_start = MAX(0, -in_h); out_w < output_x; in_w += stride_x, ++out_w) + { + int32_t in_ch = 0; + int32_t ker_w_start = MAX(0, -in_w); + + for (; in_ch <= (input_ch - 4); in_ch += 4) + { +#if defined(RISCV_VECTOR) + int32_t out_buff0, out_buff1, out_buff2, out_buff3; + blkCnt_v = 4; + l = vsetvl_e32m4(blkCnt_v); + v_buff = vle32_v_i32m4(bias+in_ch, l); +#else + int32_t out_buff0 = bias[in_ch + 0]; + int32_t out_buff1 = bias[in_ch + 1]; + int32_t out_buff2 = bias[in_ch + 2]; + int32_t out_buff3 = bias[in_ch + 3]; +#endif + + const int8_t *input_ptr = input + (in_h + ker_h_start) * (input_ch * input_x) + in_w * input_ch + in_ch; + const int8_t *kernel_ptr = kernel + ker_h_start * (input_ch * 3) + in_ch; + + for (int32_t ker_h = ker_h_start; ker_h < MIN(3, input_y - in_h); ++ker_h) + { + int32_t in_val = 0; + int32_t ker_val = 0; + if (ker_w_start == 0) + { +#if defined(RISCV_VECTOR) + l = vsetvl_e8m1(blkCnt_v); + v_a = vsub_vv_i8m1(v_a,v_a, l); + v_in = vle8_v_i8m1(input_ptr, l); + v_ker = vle8_v_i8m1(kernel_ptr, l); + v_a = vadd_vx_i8m1(v_in,input_offset, l); + v_buff = vwadd_wv_i32m4(v_buff,vwmul_vv_i16m2(v_a,v_ker, l), l); +#else + in_val = riscv_nn_read_q7x4(input_ptr); + ker_val = riscv_nn_read_q7x4(kernel_ptr); + + out_buff0 += ((int8_t)in_val + input_offset) * (int8_t)ker_val; + out_buff1 += ((int8_t)(in_val >> 8) + input_offset) * (int8_t)(ker_val >> 8); + out_buff2 += ((int8_t)(in_val >> 16) + input_offset) * (int8_t)(ker_val >> 16); + out_buff3 += ((int8_t)(in_val >> 24) + input_offset) * (int8_t)(ker_val >> 24); +#endif + } +#if defined(RISCV_VECTOR) + l = vsetvl_e8m1(blkCnt_v); + v_a = vsub_vv_i8m1(v_a,v_a, l); + v_in = vle8_v_i8m1(input_ptr + input_ch, l); + v_ker = vle8_v_i8m1(kernel_ptr + input_ch, l); + v_a = vadd_vx_i8m1(v_in,input_offset, l); + v_buff = vwadd_wv_i32m4(v_buff,vwmul_vv_i16m2(v_a,v_ker, l), l); +#else + in_val = riscv_nn_read_q7x4(input_ptr + input_ch); + ker_val = riscv_nn_read_q7x4(kernel_ptr + input_ch); + + out_buff0 += ((int8_t)in_val + input_offset) * (int8_t)ker_val; + out_buff1 += ((int8_t)(in_val >> 8) + input_offset) * (int8_t)(ker_val >> 8); + out_buff2 += ((int8_t)(in_val >> 16) + input_offset) * (int8_t)(ker_val >> 16); + out_buff3 += ((int8_t)(in_val >> 24) + input_offset) * (int8_t)(ker_val >> 24); +#endif + if ((input_x - in_w) >= 3) + { +#if defined(RISCV_VECTOR) + l = vsetvl_e8m1(blkCnt_v); + v_a = vsub_vv_i8m1(v_a,v_a, l); + v_in = vle8_v_i8m1(input_ptr + (input_ch << 1), l); + v_ker = vle8_v_i8m1(kernel_ptr + (input_ch << 1), l); + v_a = vadd_vx_i8m1(v_in,input_offset, l); + v_buff = vwadd_wv_i32m4(v_buff,vwmul_vv_i16m2(v_a,v_ker, l), l); +#else + in_val = riscv_nn_read_q7x4(input_ptr + (input_ch << 1)); + ker_val = riscv_nn_read_q7x4(kernel_ptr + (input_ch << 1)); + + out_buff0 += ((int8_t)in_val + input_offset) * (int8_t)ker_val; + out_buff1 += ((int8_t)(in_val >> 8) + input_offset) * (int8_t)(ker_val >> 8); + out_buff2 += ((int8_t)(in_val >> 16) + input_offset) * (int8_t)(ker_val >> 16); + out_buff3 += ((int8_t)(in_val >> 24) + input_offset) * (int8_t)(ker_val >> 24); +#endif + } + + input_ptr += (input_ch * input_x); + kernel_ptr += (input_ch * 3); + } +#if defined(RISCV_VECTOR) + l = vsetvl_e8m1(blkCnt_v); + out_buff0 = vmv_x_s_i32m4_i32(v_buff); + vslide1down_vx_i32m4(v_buff,0, l); + out_buff1 = vmv_x_s_i32m4_i32(v_buff); + vslide1down_vx_i32m4(v_buff,0, l); + out_buff2 = vmv_x_s_i32m4_i32(v_buff); + vslide1down_vx_i32m4(v_buff,0, l); + out_buff3 = vmv_x_s_i32m4_i32(v_buff); +#endif + out_buff0 = riscv_nn_requantize(out_buff0, output_mult[in_ch + 0], output_shift[in_ch + 0]); + out_buff1 = riscv_nn_requantize(out_buff1, output_mult[in_ch + 1], output_shift[in_ch + 1]); + out_buff2 = riscv_nn_requantize(out_buff2, output_mult[in_ch + 2], output_shift[in_ch + 2]); + out_buff3 = riscv_nn_requantize(out_buff3, output_mult[in_ch + 3], output_shift[in_ch + 3]); + + out_buff0 += output_offset; + out_buff1 += output_offset; + out_buff2 += output_offset; + out_buff3 += output_offset; + + out_buff0 = MIN(MAX(out_buff0, output_activation_min), output_activation_max); + out_buff1 = MIN(MAX(out_buff1, output_activation_min), output_activation_max); + out_buff2 = MIN(MAX(out_buff2, output_activation_min), output_activation_max); + out_buff3 = MIN(MAX(out_buff3, output_activation_min), output_activation_max); + + output[out_idx++] = (int8_t)out_buff0; + output[out_idx++] = (int8_t)out_buff1; + output[out_idx++] = (int8_t)out_buff2; + output[out_idx++] = (int8_t)out_buff3; + } + + // Leftover + for (; in_ch < input_ch; ++in_ch) + { + int32_t out_buff = bias[in_ch]; + + const int8_t *input_ptr = input + (in_h + ker_h_start) * (input_ch * input_x) + in_w * input_ch + in_ch; + const int8_t *kernel_ptr = kernel + ker_h_start * (input_ch * 3) + in_ch; + + for (int32_t ker_h = ker_h_start; ker_h < MIN(3, input_y - in_h); ++ker_h) + { + if (ker_w_start == 0) + { + out_buff += (*(input_ptr) + input_offset) * *(kernel_ptr); + } + + out_buff += (*(input_ptr + input_ch) + input_offset) * *(kernel_ptr + input_ch); + + if ((input_x - in_w) >= 3) + { + out_buff += (*(input_ptr + (input_ch << 1)) + input_offset) * *(kernel_ptr + (input_ch << 1)); + } + + input_ptr += (input_ch * input_x); + kernel_ptr += (input_ch * 3); + } + + out_buff = riscv_nn_requantize(out_buff, output_mult[in_ch], output_shift[in_ch]); + out_buff += output_offset; + out_buff = MIN(MAX(out_buff, output_activation_min), output_activation_max); + output[out_idx++] = (int8_t)out_buff; + } + } + } + + /* Return to application */ + return RISCV_MATH_SUCCESS; +} + +/** + * @} end of NNConv group + */ diff --git a/components/nmsis/nn/src/ConvolutionFunctions/riscv_depthwise_conv_s8.c b/components/nmsis/nn/src/ConvolutionFunctions/riscv_depthwise_conv_s8.c new file mode 100644 index 00000000..ca4852ca --- /dev/null +++ b/components/nmsis/nn/src/ConvolutionFunctions/riscv_depthwise_conv_s8.c @@ -0,0 +1,373 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_depthwise_conv_s8.c + * Description: s8 version of depthwise convolution. + * + * $Date: 11. May 2021 + * $Revision: V.2.5.0 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "riscv_nnfunctions.h" +#include "riscv_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +static void depthwise_conv_s8_mult_4(const int8_t *input, + const int32_t input_x, + const int32_t input_y, + const int32_t input_ch, + const int8_t *kernel, + const int32_t output_ch, + const int32_t ch_mult, + const int32_t kernel_x, + const int32_t kernel_y, + const int32_t pad_x, + const int32_t pad_y, + const int32_t stride_x, + const int32_t stride_y, + const int32_t *bias, + int8_t *output, + const int32_t *output_shift, + const int32_t *output_mult, + const int32_t output_x, + const int32_t output_y, + const int32_t output_offset, + const int32_t input_offset, + const int32_t output_activation_min, + const int32_t output_activation_max) +{ +#if defined(RISCV_VECTOR) + size_t l; + uint32_t blkCnt; + vint8m1_t vkernel; + vint32m4_t vout_buff; +#endif + for (int32_t in_h = -pad_y, out_h = 0, out_idx = 0; out_h < output_y; in_h += stride_y, ++out_h) + { + for (int32_t in_w = -pad_x, out_w = 0, ker_h_start = MAX(0, -in_h); out_w < output_x; in_w += stride_x, ++out_w) + { + for (int32_t in_ch = 0, out_ch = 0, ker_w_start = MAX(0, -in_w); out_ch < output_ch; + ++in_ch, out_ch += ch_mult) + { + for (int mult_tile = 0; mult_tile < ch_mult; mult_tile += 4) + { + int32_t out_buff[4]; +#if defined(RISCV_VECTOR) + l = vsetvl_e32m1(4); + vout_buff = vle32_v_i32m4(bias + out_ch + mult_tile, l); +#else + out_buff[0] = bias[out_ch + 0 + mult_tile]; + out_buff[1] = bias[out_ch + 1 + mult_tile]; + out_buff[2] = bias[out_ch + 2 + mult_tile]; + out_buff[3] = bias[out_ch + 3 + mult_tile]; +#endif + + for (int32_t ker_h = ker_h_start; ker_h < MIN(kernel_y, input_y - in_h); ++ker_h) + { + int32_t ker_idx = ker_h * (output_ch * kernel_x) + ker_w_start * output_ch + out_ch; + int32_t in_idx = (in_h + ker_h) * (input_ch * input_x) + in_w * input_ch + in_ch; + + for (int32_t ker_w = ker_w_start; ker_w < MIN(kernel_x, input_x - in_w); + ++ker_w, ker_idx += output_ch) + { + int32_t in_val = input[in_idx + ker_w * input_ch] + input_offset; +#if defined(RISCV_VECTOR) + l = vsetvl_e8m1(4); + vkernel = vle8_v_i8m1(kernel + ker_idx + mult_tile, l); + vout_buff = vadd_vv_i32m4(vout_buff, vmul_vx_i32m4(vsext_vf4_i32m4 (vkernel, l),in_val, l), l); + vse32_v_i32m4(out_buff,vout_buff, l); +#else + out_buff[0] += in_val * kernel[ker_idx + 0 + mult_tile]; + out_buff[1] += in_val * kernel[ker_idx + 1 + mult_tile]; + out_buff[2] += in_val * kernel[ker_idx + 2 + mult_tile]; + out_buff[3] += in_val * kernel[ker_idx + 3 + mult_tile]; +#endif + } + } + out_buff[0] = riscv_nn_requantize(out_buff[0], output_mult[out_ch + 0 + mult_tile], output_shift[out_ch + 0 + mult_tile]); + out_buff[1] = riscv_nn_requantize(out_buff[1], output_mult[out_ch + 1 + mult_tile], output_shift[out_ch + 1 + mult_tile]); + out_buff[2] = riscv_nn_requantize(out_buff[2], output_mult[out_ch + 2 + mult_tile], output_shift[out_ch + 2 + mult_tile]); + out_buff[3] = riscv_nn_requantize(out_buff[3], output_mult[out_ch + 3 + mult_tile], output_shift[out_ch + 3 + mult_tile]); +#if defined(RISCV_VECTOR) + l = vsetvl_e32m4(4); + vout_buff = vle32_v_i32m4(out_buff, l); + vout_buff = vadd_vx_i32m4(vout_buff, output_offset, l); + vout_buff = vmin_vx_i32m4(vmax_vx_i32m4(vout_buff,output_activation_min, l),output_activation_max, l); + vse8_v_i8m1(output+out_idx,vnclip_wx_i8m1(vnclip_wx_i16m2(vout_buff,0, l),0, l), l); + out_idx += 4; + // vse32_v_i32m4(out_buff,vout_buff); +#else + out_buff[0] += output_offset; + out_buff[1] += output_offset; + out_buff[2] += output_offset; + out_buff[3] += output_offset; + + out_buff[0] = MIN(MAX(out_buff[0], output_activation_min), output_activation_max); + out_buff[1] = MIN(MAX(out_buff[1], output_activation_min), output_activation_max); + out_buff[2] = MIN(MAX(out_buff[2], output_activation_min), output_activation_max); + out_buff[3] = MIN(MAX(out_buff[3], output_activation_min), output_activation_max); + + output[out_idx++] = (int8_t)out_buff[0]; + output[out_idx++] = (int8_t)out_buff[1]; + output[out_idx++] = (int8_t)out_buff[2]; + output[out_idx++] = (int8_t)out_buff[3]; +#endif + } + } + } + } +} + +static void depthwise_conv_s8_generic(const q7_t *input, + const uint16_t input_batches, + const uint16_t input_x, + const uint16_t input_y, + const uint16_t input_ch, + const q7_t *kernel, + const uint16_t output_ch, + const uint16_t ch_mult, + const uint16_t kernel_x, + const uint16_t kernel_y, + const uint16_t pad_x, + const uint16_t pad_y, + const uint16_t stride_x, + const uint16_t stride_y, + const int32_t *bias, + q7_t *output, + const int32_t *output_shift, + const int32_t *output_mult, + const uint16_t output_x, + const uint16_t output_y, + const int32_t output_offset, + const int32_t input_offset, + const int32_t output_activation_min, + const int32_t output_activation_max) +{ + (void)output_ch; +#if defined(RISCV_VECTOR) + size_t l; + uint32_t blkCnt_v; + vint8m2_t vkernel; + vint32m8_t vout_acc; +#endif + int i_out = 0; + int i_batch; + + for (i_batch = 0; i_batch < input_batches; i_batch++) + { + for (int i_out_y = 0; i_out_y < output_y; i_out_y++) + { + const int16_t base_idx_y = (i_out_y * stride_y) - pad_y; + for (int i_out_x = 0; i_out_x < output_x; i_out_x++) + { + const int16_t base_idx_x = (i_out_x * stride_x) - pad_x; + for (int i_input_ch = 0; i_input_ch < input_ch; i_input_ch++) + { +#if defined(RISCV_VECTOR) + blkCnt_v = ch_mult; + int idx_out_ch = i_input_ch * ch_mult; + /* Condition for kernel start dimension: (base_idx_ + ker__start) >= 0 */ + const int ker_y_start = MAX(0, -base_idx_y); + const int ker_x_start = MAX(0, -base_idx_x); + /* Condition for kernel end dimension: (base_idx_ + ker__end) < input_ */ + const int ker_y_end = MIN(kernel_y, input_y - base_idx_y); + const int ker_x_end = MIN(kernel_x, input_x - base_idx_x); + for (; (l = vsetvl_e32m8(blkCnt_v)) > 0; blkCnt_v -= l) { + vout_acc = vle32_v_i32m8(bias + idx_out_ch, l); + + for (int i_ker_y = ker_y_start; i_ker_y < ker_y_end; i_ker_y++) + { + const int32_t idx_y = base_idx_y + i_ker_y; + for (int i_ker_x = ker_x_start; i_ker_x < ker_x_end; i_ker_x++) + { + const int32_t idx_x = base_idx_x + i_ker_x; + int32_t idx_0 = (idx_y * input_x + idx_x) * input_ch + i_input_ch; + // bstridea = input_ch; + int32_t ker_idx_0 = (i_ker_y * kernel_x + i_ker_x) * (input_ch * ch_mult) + idx_out_ch; + // bstrideb = input_ch * ch_mult; + int8_t input_data = input[idx_0]; + + // vinput = vlse8_v_i8m2(input + idx_0,bstridea, l); + vkernel = vle8_v_i8m2(kernel + ker_idx_0, l); + + vout_acc = vadd_vv_i32m8(vout_acc,vmul_vx_i32m8(vsext_vf4_i32m8(vkernel, l), ((int32_t)input_data + input_offset), l), l); + } + } + + int32_t acc_0; + for(size_t i=l;i>0;i--){ + acc_0 = vmv_x_s_i32m8_i32 (vout_acc); + + /* Requantize and clamp output to provided range */ + acc_0 = riscv_nn_requantize(acc_0, output_mult[idx_out_ch], output_shift[idx_out_ch]); + acc_0 += output_offset; + acc_0 = MAX(acc_0, output_activation_min); + acc_0 = MIN(acc_0, output_activation_max); + + output[i_out++] = acc_0; + l = vsetvl_e32m8(l); + vout_acc = vslide1down_vx_i32m8(vout_acc,0, l); + idx_out_ch++; + } + } + } +#else + // for (int i_ch_mult = 0; i_ch_mult < ch_mult; i_ch_mult++) + // const int16_t base_idx_x = (i_out_x * stride_x) - pad_x; + // for (int i_input_ch = 0; i_input_ch < input_ch; i_input_ch++) + // { + for (int i_ch_mult = 0; i_ch_mult < ch_mult; i_ch_mult++) + { + const int idx_out_ch = i_ch_mult + i_input_ch * ch_mult; + int32_t acc_0; + /* Condition for kernel start dimension: (base_idx_ + ker__start) >= 0 */ + const int ker_y_start = MAX(0, -base_idx_y); + const int ker_x_start = MAX(0, -base_idx_x); + /* Condition for kernel end dimension: (base_idx_ + ker__end) < input_ */ + const int ker_y_end = MIN(kernel_y, input_y - base_idx_y); + const int ker_x_end = MIN(kernel_x, input_x - base_idx_x); + acc_0 = bias[idx_out_ch]; + + for (int i_ker_y = ker_y_start; i_ker_y < ker_y_end; i_ker_y++) + { + const int32_t idx_y = base_idx_y + i_ker_y; + for (int i_ker_x = ker_x_start; i_ker_x < ker_x_end; i_ker_x++) + { + const int32_t idx_x = base_idx_x + i_ker_x; + int32_t idx_0 = (idx_y * input_x + idx_x) * input_ch + i_input_ch; + int32_t ker_idx_0 = (i_ker_y * kernel_x + i_ker_x) * (input_ch * ch_mult) + idx_out_ch; + + acc_0 += (input[idx_0] + input_offset) * kernel[ker_idx_0]; + } + } + + /* Requantize and clamp output to provided range */ + acc_0 = riscv_nn_requantize(acc_0, output_mult[idx_out_ch], output_shift[idx_out_ch]); + acc_0 += output_offset; + acc_0 = MAX(acc_0, output_activation_min); + acc_0 = MIN(acc_0, output_activation_max); + + output[i_out++] = acc_0; + } + } +#endif + } + } + /* Advance to the next batch */ + input += (input_x * input_y * input_ch); + } +} + +/* + * Basic s8 depthwise convolution function. + * + * Refer header file for details. + * Optimization using DSP extension is not available for the generic case where channel multiplier is > 1. + * + */ +riscv_status riscv_depthwise_conv_s8(const nmsis_nn_context *ctx, + const nmsis_nn_dw_conv_params *dw_conv_params, + const nmsis_nn_per_channel_quant_params *quant_params, + const nmsis_nn_dims *input_dims, + const q7_t *input, + const nmsis_nn_dims *filter_dims, + const q7_t *kernel, + const nmsis_nn_dims *bias_dims, + const int32_t *bias, + const nmsis_nn_dims *output_dims, + q7_t *output) +{ + (void)dw_conv_params->dilation; + (void)bias_dims; + (void)ctx; + + if (dw_conv_params->ch_mult % 4 == 0 && input_dims->n == 1) + { + depthwise_conv_s8_mult_4(input, + input_dims->w, + input_dims->h, + input_dims->c, + kernel, + output_dims->c, + dw_conv_params->ch_mult, + filter_dims->w, + filter_dims->h, + dw_conv_params->padding.w, + dw_conv_params->padding.h, + dw_conv_params->stride.w, + dw_conv_params->stride.h, + bias, + output, + quant_params->shift, + quant_params->multiplier, + output_dims->w, + output_dims->h, + dw_conv_params->output_offset, + dw_conv_params->input_offset, + dw_conv_params->activation.min, + dw_conv_params->activation.max); + } + else + { + depthwise_conv_s8_generic(input, + input_dims->n, + input_dims->w, + input_dims->h, + input_dims->c, + kernel, + output_dims->c, + dw_conv_params->ch_mult, + filter_dims->w, + filter_dims->h, + dw_conv_params->padding.w, + dw_conv_params->padding.h, + dw_conv_params->stride.w, + dw_conv_params->stride.h, + bias, + output, + quant_params->shift, + quant_params->multiplier, + output_dims->w, + output_dims->h, + dw_conv_params->output_offset, + dw_conv_params->input_offset, + dw_conv_params->activation.min, + dw_conv_params->activation.max); + } + + /* Return to application */ + return RISCV_MATH_SUCCESS; +} + +/** + * @} end of NNConv group + */ diff --git a/components/nmsis/nn/src/ConvolutionFunctions/riscv_depthwise_conv_s8_opt.c b/components/nmsis/nn/src/ConvolutionFunctions/riscv_depthwise_conv_s8_opt.c new file mode 100644 index 00000000..27b89711 --- /dev/null +++ b/components/nmsis/nn/src/ConvolutionFunctions/riscv_depthwise_conv_s8_opt.c @@ -0,0 +1,767 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_depthwise_conv_s8_opt.c + * Description: Optimized s8 depthwise separable convolution function for + * channel multiplier of 1. + * + * $Date: January 26, 2021 + * $Revision: V.2.0.3 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "riscv_nnfunctions.h" +#include "riscv_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/* + * Optimized s8 depthwise convolution function with constraint that in_channel equals out_channel + * + * Refer prototype header file for details. + * + */ + +riscv_status riscv_depthwise_conv_s8_opt(const nmsis_nn_context *ctx, + const nmsis_nn_dw_conv_params *dw_conv_params, + const nmsis_nn_per_channel_quant_params *quant_params, + const nmsis_nn_dims *input_dims, + const q7_t *input, + const nmsis_nn_dims *filter_dims, + const q7_t *kernel, + const nmsis_nn_dims *bias_dims, + const int32_t *bias, + const nmsis_nn_dims *output_dims, + q7_t *output) +{ + + const int32_t input_ch = input_dims->c; + const int32_t output_ch = output_dims->c; + + /* Check input constraints input_ch == output_ch */ + if (input_ch != output_ch) + { + return RISCV_MATH_SIZE_MISMATCH; + } +#ifdef RISCV_MATH_DSP + const int32_t input_x = input_dims->w; + const int32_t input_y = input_dims->h; + const int32_t kernel_x = filter_dims->w; + const int32_t kernel_y = filter_dims->h; + const int32_t pad_x = dw_conv_params->padding.w; + const int32_t pad_y = dw_conv_params->padding.h; + const int32_t stride_x = dw_conv_params->stride.w; + const int32_t stride_y = dw_conv_params->stride.h; + const int32_t *output_shift = quant_params->shift; + const int32_t *output_mult = quant_params->multiplier; + const int32_t output_x = output_dims->w; + const int32_t output_y = output_dims->h; + const int32_t output_offset = dw_conv_params->output_offset; + const int32_t input_offset = dw_conv_params->input_offset; + const int32_t output_activation_min = dw_conv_params->activation.min; + const int32_t output_activation_max = dw_conv_params->activation.max; + q15_t *buffer_a = (q15_t *)ctx->buf; + + (void)bias_dims; + /* Run the following code in cores using DSP extension */ + q15_t *const col_buffer_start = buffer_a; + q15_t *col_buffer = col_buffer_start; + const int32_t *const bias_start_pos = bias; + const q31_t *const out_mult_start_pos = output_mult; + const q31_t *const out_shift_start_pos = output_shift; + uint16_t row_count; + uint16_t row_shift; + + for (int i_out_y = 0; i_out_y < output_y; i_out_y++) + { + const int16_t base_idx_y = (i_out_y * stride_y) - pad_y; + for (int i_out_x = 0; i_out_x < output_x; i_out_x++) + { + const int16_t base_idx_x = (i_out_x * stride_x) - pad_x; + + /* Out of bounds is only considered for the y axis as it provides a contiguous zero'ing opportunity than + along the x axis */ + const int ker_y_start = MAX(0, -base_idx_y); + /* Condition for kernel end dimension: (base_idx_y + ker_y_end) < input_y */ + const int ker_y_end = MIN(kernel_y, input_y - base_idx_y); + + int32_t index = 0; + if (ker_y_start != 0) + { + memset(&col_buffer[index], 0, (kernel_x * input_ch) * ker_y_start * sizeof(q15_t)); + index += (kernel_x * input_ch) * ker_y_start; + } + + for (int i_ker_y = ker_y_start; i_ker_y < ker_y_end; i_ker_y++) + { + const int32_t idx_y = base_idx_y + i_ker_y; + + for (int i_ker_x = 0; i_ker_x < kernel_x; i_ker_x++) + { + const int32_t idx_x = base_idx_x + i_ker_x; + if (idx_x < 0 || idx_x >= input_x) + { + memset(&col_buffer[index], 0, input_ch * sizeof(q15_t)); + } + else + { + riscv_q7_to_q15_with_offset((q7_t *)input + (idx_y * input_x + idx_x) * input_ch, + &col_buffer[index], + input_ch, + input_offset); + } + index += input_ch; + } + } + + const int diff = kernel_y - ker_y_end; + if (diff != 0) + { + memset(&col_buffer[index], 0, (kernel_x * input_ch) * diff * sizeof(q15_t)); + } + + row_count = output_ch / 4; + row_shift = 0; + bias = bias_start_pos; + output_mult = out_mult_start_pos; + output_shift = out_shift_start_pos; + + while (row_count) + { + q31_t sum = *bias++; + q31_t sum_2 = *bias++; + q31_t sum_3 = *bias++; + q31_t sum_4 = *bias++; + + uint16_t col_count = (kernel_x * kernel_y) / 2; + q15_t *col_pos = col_buffer_start + row_shift; + const q7_t *row_pos = kernel + row_shift; + row_shift += 4; + + while (col_count) + { + /* General idea is to read 4 + 4 (input, kernel) pair and re-arrange them in the right order to + use in a SMLAD instruction . One run of this loop produces 4 partial outputs with 8 MACs. */ + /* Note: variable names can be improved here to align with rows and columns. */ + q31_t ip_a1, ip_b1, op_a, op_b; + q31_t ip_a01, ip_a23, ip_b01, ip_b23; + /* Read 4 weights */ + ip_a1 = riscv_nn_read_q7x4(row_pos); + ip_b1 = riscv_nn_read_q7x4(row_pos + input_ch); + op_a = riscv_nn_read_q15x2(col_pos); + op_b = riscv_nn_read_q15x2(col_pos + input_ch); + + ip_a01 = __RV_SUNPKD810(ip_a1); + ip_a23 = __RV_SUNPKD832(ip_a1); + + ip_b01 = __RV_SUNPKD810(ip_b1); + ip_b23 = __RV_SUNPKD832(ip_b1); + + sum = __RV_KMABB(sum,ip_a01,op_a); + sum = __RV_KMABB(sum,ip_b01,op_b); + sum_2 = __RV_KMATT(sum_2,ip_a01,op_a); + sum_2 = __RV_KMATT(sum_2,ip_b01,op_b); + // sum_3 = __RV_KMABB(sum_3,ip_a23,op_a); + // sum_3 = __RV_KMABB(sum_3,ip_b23,op_b); + // sum_4 = __RV_KMATT(sum_4,ip_a23,op_a); + // sum_4 = __RV_KMATT(sum_4,ip_b23,op_b); + + op_a = riscv_nn_read_q15x2(col_pos + 2); + op_b = riscv_nn_read_q15x2(col_pos + input_ch + 2); + + // sum = __RV_KMABB(sum,ip_a01,op_a); + // sum = __RV_KMABB(sum,ip_b01,op_b); + // sum_2 = __RV_KMATT(sum_2,ip_a01,op_a); + // sum_2 = __RV_KMATT(sum_2,ip_b01,op_b); + sum_3 = __RV_KMABB(sum_3,ip_a23,op_a); + sum_3 = __RV_KMABB(sum_3,ip_b23,op_b); + sum_4 = __RV_KMATT(sum_4,ip_a23,op_a); + sum_4 = __RV_KMATT(sum_4,ip_b23,op_b); + // ip_a2 = __SXTB16(ip_b1); + // ip_b1 = __SXTB16(__ROR(ip_b1, 8)); + + // ip_b2 = __SXTB16(ip_a1); + // ip_a1 = __SXTB16(__ROR(ip_a1, 8)); + + // op_c = __PKHBT(op_b, op_a, 16); + // op_a = __PKHTB(op_b, op_a, 16); + // op_b = __PKHBT(ip_b2, ip_a2, 16); + // sum = __SMLAD(op_c, op_b, sum); + + // op_b = __PKHBT(ip_b1, ip_a1, 16); + // sum_2 = __SMLAD(op_a, op_b, sum_2); + + // op_a = riscv_nn_read_q15x2(col_pos + 2); + // op_b = riscv_nn_read_q15x2(col_pos + input_ch + 2); + + // op_c = __PKHBT(op_b, op_a, 16); + // op_a = __PKHTB(op_b, op_a, 16); + // op_b = __PKHTB(ip_a2, ip_b2, 16); + // sum_3 = __SMLAD(op_c, op_b, sum_3); + + // op_b = __PKHTB(ip_a1, ip_b1, 16); + // sum_4 = __SMLAD(op_a, op_b, sum_4); + + row_pos += input_ch << 1; + col_pos += input_ch << 1; + col_count--; + } + + col_count = (kernel_x * kernel_y) & 0x1; + while (col_count) + { + sum += row_pos[0] * col_pos[0]; + sum_2 += row_pos[1] * col_pos[1]; + sum_3 += row_pos[2] * col_pos[2]; + sum_4 += row_pos[3] * col_pos[3]; + + row_pos += input_ch; + col_pos += input_ch; + + col_count--; + } + sum = riscv_nn_requantize(sum, *output_mult++, *output_shift++); + sum += output_offset; + sum = MAX(sum, output_activation_min); + sum = MIN(sum, output_activation_max); + *output++ = (q7_t)sum; + + sum_2 = riscv_nn_requantize(sum_2, *output_mult++, *output_shift++); + sum_2 += output_offset; + sum_2 = MAX(sum_2, output_activation_min); + sum_2 = MIN(sum_2, output_activation_max); + *output++ = (q7_t)sum_2; + sum_3 = riscv_nn_requantize(sum_3, *output_mult++, *output_shift++); + sum_3 += output_offset; + sum_3 = MAX(sum_3, output_activation_min); + sum_3 = MIN(sum_3, output_activation_max); + *output++ = (q7_t)sum_3; + + sum_4 = riscv_nn_requantize(sum_4, *output_mult++, *output_shift++); + sum_4 += output_offset; + sum_4 = MAX(sum_4, output_activation_min); + sum_4 = MIN(sum_4, output_activation_max); + *output++ = (q7_t)sum_4; + + row_count--; + } + + row_count = output_ch & 0x3; + while (row_count) + { + q15_t *col_pos = col_buffer_start + row_shift; + const q7_t *row_pos = kernel + row_shift; + q31_t sum = *bias++; + const uint16_t col_count = (kernel_x * kernel_y); + row_shift += 1; + + for (int i = 0; i < col_count; i++) + { + sum += row_pos[i * input_ch] * col_pos[i * input_ch]; + } + sum = riscv_nn_requantize(sum, *output_mult++, *output_shift++); + sum += output_offset; + sum = MAX(sum, output_activation_min); + sum = MIN(sum, output_activation_max); + *output++ = (q7_t)sum; + + row_count--; + } + + // clear counter and pointers + col_buffer = col_buffer_start; + } + } +#else + /* Run the following code as reference implementation for RISC-V Core without DSP */ + return riscv_depthwise_conv_s8(ctx, + dw_conv_params, + quant_params, + input_dims, + input, + filter_dims, + kernel, + bias_dims, + bias, + output_dims, + output); +#endif /* RISCV_MATH_DSP */ + + /* Return to application */ + return RISCV_MATH_SUCCESS; +} + + + + + + + + + + + +// riscv_status riscv_depthwise_conv_s8_opt(const nmsis_nn_context *ctx, +// const nmsis_nn_dw_conv_params *dw_conv_params, +// const nmsis_nn_per_channel_quant_params *quant_params, +// const nmsis_nn_dims *input_dims, +// const q7_t *input, +// const nmsis_nn_dims *filter_dims, +// const q7_t *kernel, +// const nmsis_nn_dims *bias_dims, +// const int32_t *bias, +// const nmsis_nn_dims *output_dims, +// q7_t *output) +// { + +// const int32_t input_ch = input_dims->c; +// const int32_t output_ch = output_dims->c; + +// /* Check input constraints input_ch == output_ch */ +// if (input_ch != output_ch) +// { +// return RISCV_MATH_SIZE_MISMATCH; +// } +// #ifdef RISCV_MATH_DSP +// const int32_t input_x = input_dims->w; +// const int32_t input_y = input_dims->h; +// const int32_t kernel_x = filter_dims->w; +// const int32_t kernel_y = filter_dims->h; +// const int32_t pad_x = dw_conv_params->padding.w; +// const int32_t pad_y = dw_conv_params->padding.h; +// const int32_t stride_x = dw_conv_params->stride.w; +// const int32_t stride_y = dw_conv_params->stride.h; +// const int32_t *output_shift = quant_params->shift; +// const int32_t *output_mult = quant_params->multiplier; +// const int32_t output_x = output_dims->w; +// const int32_t output_y = output_dims->h; +// const int32_t output_offset = dw_conv_params->output_offset; +// const int32_t input_offset = dw_conv_params->input_offset; +// const int32_t output_activation_min = dw_conv_params->activation.min; +// const int32_t output_activation_max = dw_conv_params->activation.max; +// q15_t *buffer_a = (q15_t *)ctx->buf; + +// #ifdef RISCV_MATH_MVEI +// (void)bias_dims; +// /* Generate two columns from the input tensor */ +// q7_t *lhs_buffer = (q7_t *)buffer_a; +// q7_t *out = output; +// int padded = 0; +// int buffer_count = 0; +// const int32_t kernel_size = kernel_x * kernel_y; + +// /* This part implements the im2col function */ +// for (int i_out_y = 0, base_idx_y = -pad_y; i_out_y < output_y; base_idx_y += stride_y, i_out_y++) +// { +// for (int i_out_x = 0, base_idx_x = -pad_x; i_out_x < output_x; base_idx_x += stride_x, i_out_x++) +// { +// for (int i_ker_y = base_idx_y; i_ker_y < base_idx_y + kernel_y; i_ker_y++) +// { +// for (int i_ker_x = base_idx_x; i_ker_x < base_idx_x + kernel_x; i_ker_x++) +// { +// if (i_ker_y < 0 || i_ker_y >= input_y || i_ker_x < 0 || i_ker_x >= input_x) +// { +// riscv_memset_q7(lhs_buffer, (int8_t)-input_offset, (uint32_t)input_ch); +// padded = 1; +// } +// else +// { +// riscv_memcpy_q7(lhs_buffer, input + (i_ker_y * input_x + i_ker_x) * input_ch, (uint32_t)input_ch); +// } +// lhs_buffer += input_ch; +// } +// } +// buffer_count++; + +// if (buffer_count == 4) +// { +// lhs_buffer = (q7_t *)buffer_a; +// if (padded == 0) +// { +// out = riscv_nn_depthwise_conv_nt_t_s8(lhs_buffer, +// kernel, +// input_offset, +// input_ch, +// output_shift, +// output_mult, +// output_offset, +// output_activation_min, +// output_activation_max, +// kernel_size, +// bias, +// out); +// } +// else +// { +// out = riscv_nn_depthwise_conv_nt_t_padded_s8(lhs_buffer, +// kernel, +// input_offset, +// input_ch, +// output_shift, +// output_mult, +// output_offset, +// output_activation_min, +// output_activation_max, +// kernel_size, +// bias, +// out); +// padded = 0; +// } +// buffer_count = 0; +// } +// } +// } + +// /* Handle left over buffers */ +// lhs_buffer = (q7_t *)buffer_a; + +// for (int i_buf = 0; i_buf < buffer_count; i_buf++) +// { +// int32_t loop_count = (input_ch + 3) / 4; + +// int32_t num_ch_to_process = input_ch; +// for (int i_loop_cnt = 0, offset = 0; i_loop_cnt < loop_count; num_ch_to_process -= 4, offset += 4, i_loop_cnt++) +// { +// const int8_t *col_0 = lhs_buffer + (kernel_size * input_ch * i_buf) + offset; +// const int8_t *row_0 = kernel + offset; +// int32x4_t out_0 = vldrwq_s32(&bias[offset]); + +// for (int i_ker = 0; i_ker < kernel_size; i_ker++) +// { +// const int32x4_t ker_0 = vldrbq_s32(row_0); + +// int32x4_t ip_0 = vldrbq_s32(col_0); +// ip_0 = vaddq_n_s32(ip_0, input_offset); +// out_0 += vmulq_s32(ip_0, ker_0); + +// col_0 += input_ch; +// row_0 += input_ch; +// } + +// const int32x4_t mult = vldrwq_s32(&output_mult[offset]); +// const int32x4_t shift = vldrwq_s32(&output_shift[offset]); + +// out_0 = riscv_requantize_mve_32x4(out_0, mult, shift); +// out_0 = vaddq_n_s32(out_0, output_offset); +// out_0 = vmaxq_s32(out_0, vdupq_n_s32(output_activation_min)); +// out_0 = vminq_s32(out_0, vdupq_n_s32(output_activation_max)); +// mve_pred16_t p = vctp32q((uint32_t)num_ch_to_process); +// vstrbq_p_s32(out, out_0, p); + +// out += 4; +// } + +// const int tail_ch = input_ch & 0x3; +// if (tail_ch != 0) +// { +// out -= (4 - tail_ch); +// } +// } + +// #elif defined(RISCV_MATH_DSP) || defined(RISCV_VECTOR) +// (void)bias_dims; +// /* Run the following code in cores using DSP extension */ +// q7_t *const col_buffer_start = buffer_a; +// q7_t *col_buffer = col_buffer_start; +// const int32_t *const bias_start_pos = bias; +// const q31_t *const out_mult_start_pos = output_mult; +// const q31_t *const out_shift_start_pos = output_shift; +// uint16_t row_count; +// uint16_t row_shift; + +// for (int i_out_y = 0; i_out_y < output_y; i_out_y++) +// { +// const int16_t base_idx_y = (i_out_y * stride_y) - pad_y; +// for (int i_out_x = 0; i_out_x < output_x; i_out_x++) +// { +// const int16_t base_idx_x = (i_out_x * stride_x) - pad_x; + +// /* Out of bounds is only considered for the y axis as it provides a contiguous zero'ing opportunity than +// along the x axis */ +// const int ker_y_start = MAX(0, -base_idx_y); +// /* Condition for kernel end dimension: (base_idx_y + ker_y_end) < input_y */ +// const int ker_y_end = MIN(kernel_y, input_y - base_idx_y); + +// int32_t index = 0; +// if (ker_y_start != 0) +// { +// riscv_fill_q7(0, &col_buffer[index], (kernel_x * input_ch) * ker_y_start); +// // memset(&col_buffer[index], 0, (kernel_x * input_ch) * ker_y_start * sizeof(q15_t)); +// index += (kernel_x * input_ch) * ker_y_start; +// } + +// for (int i_ker_y = ker_y_start; i_ker_y < ker_y_end; i_ker_y++) +// { +// const int32_t idx_y = base_idx_y + i_ker_y; + +// for (int i_ker_x = 0; i_ker_x < kernel_x; i_ker_x++) +// { +// const int32_t idx_x = base_idx_x + i_ker_x; +// if (idx_x < 0 || idx_x >= input_x) +// { +// riscv_fill_q7(0, &col_buffer[index], input_ch); +// // memset(&col_buffer[index], 0, input_ch * sizeof(q15_t)); +// } +// else +// { +// riscv_offset_q7((q7_t *)input + (idx_y * input_x + idx_x) * input_ch, input_offset, &col_buffer[index], input_ch); +// } +// index += input_ch; +// } +// } + +// const int diff = kernel_y - ker_y_end; +// if (diff != 0) +// { +// riscv_fill_q7(0, &col_buffer[index], (kernel_x * input_ch) * diff); +// // memset(&col_buffer[index], 0, (kernel_x * input_ch) * diff * sizeof(q15_t)); +// } + + +// row_shift = 0; +// bias = bias_start_pos; +// output_mult = out_mult_start_pos; +// output_shift = out_shift_start_pos; + +// #if defined(RISCV_VECTOR) && !defined (RISCV_MATH_DSP) +// // This is tipical read with fixed step, can not be optimized this round +// row_count = output_ch; +// size_t l; +// ptrdiff_t bstridea = input_ch*2; +// ptrdiff_t bstrideb = input_ch; +// vint16m4_t v_R,v_C; +// vint64m1_t v0; +// l = vsetvl_e32m8(1); +// v0 = vsub_vv_i64m1(v0, v0, l); /* vector 0 */ +// while (row_count) +// { +// q15_t *col_pos = col_buffer_start + row_shift; +// const q7_t *row_pos = kernel + row_shift; +// q31_t sum = *bias++; +// const uint16_t col_count = (kernel_x * kernel_y); +// row_shift += 1; + +// uint32_t blkCnt = col_count; +// int i = 0; +// for (; (l = vsetvl_e16m4(blkCnt)) > 0; blkCnt -= l) +// { +// v_R = vlse16_v_i16m4(row_pos + i*input_ch, bstridea, l); +// v_C = vwadd_vx_i16m4(vlse8_v_i8m2(col_pos + i*input_ch, bstrideb, l),0, l); +// i += l; +// sum += (q31_t)vmv_x_s_i64m1_i64(vwredsum_vs_i32m8_i64m1(v0, vwmul_vv_i32m8(v_R, v_C, l), v0, l)); +// } +// // for (int i = 0; i < col_count; i++) +// // { +// // sum += row_pos[i * input_ch] * col_pos[i * input_ch]; +// // } +// sum = riscv_nn_requantize(sum, *output_mult++, *output_shift++); +// sum += output_offset; +// sum = MAX(sum, output_activation_min); +// sum = MIN(sum, output_activation_max); +// *output++ = (q7_t)sum; + +// row_count--; +// } + +// #else +// row_count = output_ch / 4; +// while (row_count) +// { +// q31_t sum = *bias++; +// q31_t sum_2 = *bias++; +// q31_t sum_3 = *bias++; +// q31_t sum_4 = *bias++; + +// uint16_t col_count = (kernel_x * kernel_y) / 2; +// q7_t *col_pos = col_buffer_start + row_shift; +// const q7_t *row_pos = kernel + row_shift; +// row_shift += 4; + +// q63_t temp_1, temp_2, temp_sum_0_1 = 0, temp_sum_2_3 = 0; +// while (col_count) +// { +// /* General idea is to read 4 + 4 (input, kernel) pair and re-arrange them in the right order to +// use in a SMLAD instruction . One run of this loop produces 4 partial outputs with 8 MACs. */ +// /* Note: variable names can be improved here to align with rows and columns. */ +// q31_t ip_a1, ip_a2, ip_b1, ip_b2, op_a, op_b, op_c; +// /* Read 4 weights */ +// ip_a1 = riscv_nn_read_q7x4(row_pos); +// ip_b1 = riscv_nn_read_q7x4(row_pos + input_ch); +// op_a = riscv_nn_read_q7x4(col_pos); +// op_b = riscv_nn_read_q7x4(col_pos + input_ch); + +// temp_1 = __RV_SMUL8(ip_a1, op_a); +// temp_2 = __RV_SMUL8(ip_b1, op_b); + +// /* +// Can not add temps directly, because q15 addition is not equal to q63 addition +// */ +// temp_sum_0_1 += __RV_KADD16((temp_1 & 0xffffffff), (temp_2 & 0xffffffff)); +// temp_sum_2_3 += __RV_KADD16(((temp_1 >> 32) & 0xffffffff), ((temp_2 >> 32) & 0xffffffff)); + +// /* Read 4 weights */ +// // ip_b1 = riscv_nn_read_q7x4(row_pos); +// // ip_a1 = riscv_nn_read_q7x4(row_pos + input_ch); +// // op_a = riscv_nn_read_q15x2(col_pos); +// // op_b = riscv_nn_read_q15x2(col_pos + input_ch); + +// // ip_a2 = __SXTB16(ip_b1); +// // ip_b1 = __SXTB16(__ROR(ip_b1, 8)); + +// // ip_b2 = __SXTB16(ip_a1); +// // ip_a1 = __SXTB16(__ROR(ip_a1, 8)); + +// // op_c = __PKHBT(op_b, op_a, 16); +// // op_a = __PKHTB(op_b, op_a, 16); +// // op_b = __PKHBT(ip_b2, ip_a2, 16); +// // sum = __SMLAD(op_c, op_b, sum); + +// // op_b = __PKHBT(ip_b1, ip_a1, 16); +// // sum_2 = __SMLAD(op_a, op_b, sum_2); + +// // op_a = riscv_nn_read_q15x2(col_pos + 2); +// // op_b = riscv_nn_read_q15x2(col_pos + input_ch + 2); + +// // op_c = __PKHBT(op_b, op_a, 16); +// // op_a = __PKHTB(op_b, op_a, 16); +// // op_b = __PKHTB(ip_a2, ip_b2, 16); +// // sum_3 = __SMLAD(op_c, op_b, sum_3); + +// // op_b = __PKHTB(ip_a1, ip_b1, 16); +// // sum_4 = __SMLAD(op_a, op_b, sum_4); + +// row_pos += input_ch << 1; +// col_pos += input_ch << 1; +// col_count--; +// } +// sum += (temp_sum_0_1 & 0x0000ffff); +// sum_2 += (temp_sum_0_1 & 0xffff0000); +// sum_3 += (temp_sum_2_3 & 0x0000ffff); +// sum_4 += (temp_sum_2_3 & 0xffff0000); + +// col_count = (kernel_x * kernel_y) & 0x1; +// while (col_count) +// { +// sum += row_pos[0] * col_pos[0]; +// sum_2 += row_pos[1] * col_pos[1]; +// sum_3 += row_pos[2] * col_pos[2]; +// sum_4 += row_pos[3] * col_pos[3]; + +// row_pos += input_ch; +// col_pos += input_ch; + +// col_count--; +// } +// sum = riscv_nn_requantize(sum, *output_mult++, *output_shift++); +// sum += output_offset; +// sum = MAX(sum, output_activation_min); +// sum = MIN(sum, output_activation_max); +// *output++ = (q7_t)sum; + +// sum_2 = riscv_nn_requantize(sum_2, *output_mult++, *output_shift++); +// sum_2 += output_offset; +// sum_2 = MAX(sum_2, output_activation_min); +// sum_2 = MIN(sum_2, output_activation_max); +// *output++ = (q7_t)sum_2; +// sum_3 = riscv_nn_requantize(sum_3, *output_mult++, *output_shift++); +// sum_3 += output_offset; +// sum_3 = MAX(sum_3, output_activation_min); +// sum_3 = MIN(sum_3, output_activation_max); +// *output++ = (q7_t)sum_3; + +// sum_4 = riscv_nn_requantize(sum_4, *output_mult++, *output_shift++); +// sum_4 += output_offset; +// sum_4 = MAX(sum_4, output_activation_min); +// sum_4 = MIN(sum_4, output_activation_max); +// *output++ = (q7_t)sum_4; + +// row_count--; +// } + +// row_count = output_ch & 0x3; +// while (row_count) +// { +// q15_t *col_pos = col_buffer_start + row_shift; +// const q7_t *row_pos = kernel + row_shift; +// q31_t sum = *bias++; +// const uint16_t col_count = (kernel_x * kernel_y); +// row_shift += 1; + +// for (int i = 0; i < col_count; i++) +// { +// sum += row_pos[i * input_ch] * col_pos[i * input_ch]; +// } +// sum = riscv_nn_requantize(sum, *output_mult++, *output_shift++); +// sum += output_offset; +// sum = MAX(sum, output_activation_min); +// sum = MIN(sum, output_activation_max); +// *output++ = (q7_t)sum; + +// row_count--; +// } +// #endif /*defined(RISCV_VECTOR)*/ +// // clear counter and pointers +// col_buffer = col_buffer_start; +// } +// } +// #endif +// #else +// /* Run the following code as reference implementation for RISC-V Core without DSP */ +// return riscv_depthwise_conv_s8(ctx, +// dw_conv_params, +// quant_params, +// input_dims, +// input, +// filter_dims, +// kernel, +// bias_dims, +// bias, +// output_dims, +// output); +// #endif /* RISCV_MATH_DSP */ + +// /* Return to application */ +// return RISCV_MATH_SUCCESS; +// } + +int32_t riscv_depthwise_conv_s8_opt_get_buffer_size(const nmsis_nn_dims *input_dims, const nmsis_nn_dims *filter_dims) +{ +#if defined(RISCV_MATH_DSP) + return (input_dims->c * filter_dims->w * filter_dims->h) * sizeof(int16_t); +#else + (void)input_dims; + (void)filter_dims; + return 0; +#endif +} + +/** + * @} end of NNConv group + */ diff --git a/components/nmsis/nn/src/ConvolutionFunctions/riscv_depthwise_conv_u8_basic_ver1.c b/components/nmsis/nn/src/ConvolutionFunctions/riscv_depthwise_conv_u8_basic_ver1.c new file mode 100644 index 00000000..c5139101 --- /dev/null +++ b/components/nmsis/nn/src/ConvolutionFunctions/riscv_depthwise_conv_u8_basic_ver1.c @@ -0,0 +1,337 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_depthwise_conv_u8_basic_ver1.c + * Description: u8 depthwise convolution function + * + * $Date: 09. October 2020 + * $Revision: V.1.1.1 + * + * Target : RISC-V CPUs + * + * -------------------------------------------------------------------- */ + +#include "riscv_nnfunctions.h" +#include "riscv_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +static void depthwise_conv_u8_mult_4(const uint8_t *input, + const int32_t input_x, + const int32_t input_y, + const int32_t input_ch, + const uint8_t *kernel, + const int32_t output_ch, + const int32_t ch_mult, + const int32_t kernel_x, + const int32_t kernel_y, + const int32_t pad_x, + const int32_t pad_y, + const int32_t stride_x, + const int32_t stride_y, + const int32_t *bias, + uint8_t *output, + const int32_t output_shift, + const int32_t output_mult, + const int32_t output_x, + const int32_t output_y, + const int32_t output_offset, + const int32_t input_offset, + const int32_t filter_offset, + const int32_t output_activation_min, + const int32_t output_activation_max) +{ + for (int32_t in_h = -pad_y, out_h = 0, out_idx = 0; out_h < output_y; in_h += stride_y, ++out_h) + { + for (int32_t in_w = -pad_x, out_w = 0, ker_h_start = MAX(0, -in_h); out_w < output_x; in_w += stride_x, ++out_w) + { + for (int32_t in_ch = 0, out_ch = 0, ker_w_start = MAX(0, -in_w); out_ch < output_ch; + ++in_ch, out_ch += ch_mult) + { + for (int mult_tile = 0; mult_tile < ch_mult; mult_tile += 4) + { + int32_t out_buff[4]; + + out_buff[0] = 0; + out_buff[1] = 0; + out_buff[2] = 0; + out_buff[3] = 0; + + for (int32_t ker_h = ker_h_start; ker_h < MIN(kernel_y, input_y - in_h); ++ker_h) + { + int32_t ker_idx = ker_h * (output_ch * kernel_x) + ker_w_start * output_ch + out_ch; + int32_t in_idx = (in_h + ker_h) * (input_ch * input_x) + in_w * input_ch + in_ch; + + for (int32_t ker_w = ker_w_start; ker_w < MIN(kernel_x, input_x - in_w); + ++ker_w, ker_idx += output_ch) + { + int32_t in_val = input[in_idx + ker_w * input_ch] + input_offset; + out_buff[0] += in_val * (kernel[ker_idx + 0 + mult_tile] + filter_offset); + out_buff[1] += in_val * (kernel[ker_idx + 1 + mult_tile] + filter_offset); + out_buff[2] += in_val * (kernel[ker_idx + 2 + mult_tile] + filter_offset); + out_buff[3] += in_val * (kernel[ker_idx + 3 + mult_tile] + filter_offset); + } + } + + if (bias != NULL) + { + out_buff[0] += bias[out_ch + 0 + mult_tile]; + out_buff[1] += bias[out_ch + 1 + mult_tile]; + out_buff[2] += bias[out_ch + 2 + mult_tile]; + out_buff[3] += bias[out_ch + 3 + mult_tile]; + } + out_buff[0] = riscv_nn_requantize(out_buff[0], output_mult, output_shift); + out_buff[1] = riscv_nn_requantize(out_buff[1], output_mult, output_shift); + out_buff[2] = riscv_nn_requantize(out_buff[2], output_mult, output_shift); + out_buff[3] = riscv_nn_requantize(out_buff[3], output_mult, output_shift); + + out_buff[0] += output_offset; + out_buff[1] += output_offset; + out_buff[2] += output_offset; + out_buff[3] += output_offset; + + out_buff[0] = MIN(MAX(out_buff[0], output_activation_min), output_activation_max); + out_buff[1] = MIN(MAX(out_buff[1], output_activation_min), output_activation_max); + out_buff[2] = MIN(MAX(out_buff[2], output_activation_min), output_activation_max); + out_buff[3] = MIN(MAX(out_buff[3], output_activation_min), output_activation_max); + + output[out_idx++] = (uint8_t)out_buff[0]; + output[out_idx++] = (uint8_t)out_buff[1]; + output[out_idx++] = (uint8_t)out_buff[2]; + output[out_idx++] = (uint8_t)out_buff[3]; + } + } + } + } +} + +static void depthwise_conv_u8_generic(const uint8_t *input, + const int32_t input_x, + const int32_t input_y, + const int32_t input_ch, + const uint8_t *kernel, + const int32_t output_ch, + const int32_t ch_mult, + const int32_t kernel_x, + const int32_t kernel_y, + const int32_t pad_x, + const int32_t pad_y, + const int32_t stride_x, + const int32_t stride_y, + const int32_t *bias, + uint8_t *output, + const int32_t output_shift, + const int32_t output_mult, + const int32_t output_x, + const int32_t output_y, + const int32_t output_offset, + const int32_t input_offset, + const int32_t filter_offset, + const int32_t output_activation_min, + const int32_t output_activation_max) +{ + (void)output_ch; + int i_out = 0; + for (int i_out_y = 0; i_out_y < output_y; i_out_y++) + { + const int16_t base_idx_y = (i_out_y * stride_y) - pad_y; + for (int i_out_x = 0; i_out_x < output_x; i_out_x++) + { + const int16_t base_idx_x = (i_out_x * stride_x) - pad_x; + for (int i_input_ch = 0; i_input_ch < input_ch; i_input_ch++) + { + for (int i_ch_mult = 0; i_ch_mult < ch_mult; i_ch_mult++) + { + const int idx_out_ch = i_ch_mult + i_input_ch * ch_mult; + int32_t acc_0; + /* Condition for kernel start dimension: (base_idx_ + ker__start) >= 0 */ + const int ker_y_start = MAX(0, -base_idx_y); + const int ker_x_start = MAX(0, -base_idx_x); + /* Condition for kernel end dimension: (base_idx_ + ker__end) < input_ */ + const int ker_y_end = MIN(kernel_y, input_y - base_idx_y); + const int ker_x_end = MIN(kernel_x, input_x - base_idx_x); + acc_0 = 0; + + for (int i_ker_y = ker_y_start; i_ker_y < ker_y_end; i_ker_y++) + { + const int32_t idx_y = base_idx_y + i_ker_y; + for (int i_ker_x = ker_x_start; i_ker_x < ker_x_end; i_ker_x++) + { + const int32_t idx_x = base_idx_x + i_ker_x; + int32_t idx_0 = (idx_y * input_x + idx_x) * input_ch + i_input_ch; + int32_t ker_idx_0 = (i_ker_y * kernel_x + i_ker_x) * (input_ch * ch_mult) + idx_out_ch; + + acc_0 += (input[idx_0] + input_offset) * (kernel[ker_idx_0] + filter_offset); + } + } + if (bias != NULL) + { + acc_0 += bias[idx_out_ch]; + } + + /* Requantize and clamp output to provided range */ + acc_0 = riscv_nn_requantize(acc_0, output_mult, output_shift); + acc_0 += output_offset; + acc_0 = MAX(acc_0, output_activation_min); + acc_0 = MIN(acc_0, output_activation_max); + + output[i_out++] = acc_0; + } + } + } + } +} + +/** + * @brief uint8 depthwise convolution function with asymmetric quantization + * + * @param[in] input Pointer to input tensor + * @param[in] input_x Width of input tensor + * @param[in] input_y Height of input tensor + * @param[in] input_ch Channels in input tensor + * @param[in] kernel Pointer to kernel weights + * @param[in] kernel_x Width of kernel + * @param[in] kernel_y Height of kernel + * @param[in] ch_mult Number of channel multiplier + * @param[in] pad_x Padding sizes x + * @param[in] pad_y Padding sizes y + * @param[in] stride_x Convolution stride along the width + * @param[in] stride_y Convolution stride along the height + * @param[in] dilation_x Dilation along width. Not used and intended for future enhancement. + * @param[in] dilation_y Dilation along height. Not used and intended for future enhancement. + * @param[in] bias Pointer to optional bias values. If no bias is + * available, NULL is expected + * @param[in] input_offset Input tensor zero offset + * @param[in] filter_offset Kernel tensor zero offset + * @param[in] output_offset Output tensor zero offset + * @param[in,out] output Pointer to output tensor + * @param[in] output_x Width of output tensor + * @param[in] output_y Height of output tensor + * @param[in] output_activation_min Minimum value to clamp the output to. Range : {0, 255} + * @param[in] output_activation_max Minimum value to clamp the output to. Range : {0, 255} + * @param[in] output_shift Amount of right-shift for output + * @param[in] output_mult Output multiplier for requantization + * @return The function returns one of the following + * RISCV_MATH_SIZE_MISMATCH - Not supported dimension of tensors + * RISCV_MATH_SUCCESS - Successful operation + * RISCV_MATH_ARGUMENT_ERROR - Implementation not available + * + * + */ + +riscv_status riscv_depthwise_conv_u8_basic_ver1(const uint8_t *input, + const uint16_t input_x, + const uint16_t input_y, + const uint16_t input_ch, + const uint8_t *kernel, + const uint16_t kernel_x, + const uint16_t kernel_y, + const int16_t ch_mult, + const int16_t pad_x, + const int16_t pad_y, + const int16_t stride_x, + const int16_t stride_y, + const int16_t dilation_x, + const int16_t dilation_y, + const int32_t *bias, + const int32_t input_offset, + const int32_t filter_offset, + const int32_t output_offset, + uint8_t *output, + const uint16_t output_x, + const uint16_t output_y, + const int32_t output_activation_min, + const int32_t output_activation_max, + const int32_t output_shift, + const int32_t output_mult) +{ + (void)dilation_x; + (void)dilation_y; + + if (ch_mult % 4 == 0) + { + depthwise_conv_u8_mult_4(input, + input_x, + input_y, + input_ch, + kernel, + ch_mult * input_ch, + ch_mult, + kernel_x, + kernel_y, + pad_x, + pad_y, + stride_x, + stride_y, + bias, + output, + output_shift, + output_mult, + output_x, + output_y, + output_offset, + input_offset, + filter_offset, + output_activation_min, + output_activation_max); + } + else + { + depthwise_conv_u8_generic(input, + input_x, + input_y, + input_ch, + kernel, + ch_mult * input_ch, + ch_mult, + kernel_x, + kernel_y, + pad_x, + pad_y, + stride_x, + stride_y, + bias, + output, + output_shift, + output_mult, + output_x, + output_y, + output_offset, + input_offset, + filter_offset, + output_activation_min, + output_activation_max); + } + + /* Return to application */ + return RISCV_MATH_SUCCESS; +} + +/** + * @} end of NNConv group + */ diff --git a/components/nmsis/nn/src/ConvolutionFunctions/riscv_depthwise_conv_wrapper_s8.c b/components/nmsis/nn/src/ConvolutionFunctions/riscv_depthwise_conv_wrapper_s8.c new file mode 100644 index 00000000..f5c8f135 --- /dev/null +++ b/components/nmsis/nn/src/ConvolutionFunctions/riscv_depthwise_conv_wrapper_s8.c @@ -0,0 +1,131 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_depthwise_conv_wrapper_s8.c + * Description: Wrapper API to select appropriate depthwise conv API based + * on dimensions. + * + * $Date: 11. May 2021 + * $Revision: V.1.0.3 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "riscv_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/* + * s8 Depthwise conv wrapper function + * + * Refer header file for details. + * + */ +riscv_status riscv_depthwise_conv_wrapper_s8(const nmsis_nn_context *ctx, + const nmsis_nn_dw_conv_params *dw_conv_params, + const nmsis_nn_per_channel_quant_params *quant_params, + const nmsis_nn_dims *input_dims, + const q7_t *input, + const nmsis_nn_dims *filter_dims, + const q7_t *filter, + const nmsis_nn_dims *bias_dims, + const int32_t *bias, + const nmsis_nn_dims *output_dims, + q7_t *output) +{ + riscv_status status = RISCV_MATH_SUCCESS; + if (1 == dw_conv_params->ch_mult && input_dims->n == 1) + { + if ((filter_dims->w == 3) && (filter_dims->h == 3) && (dw_conv_params->padding.h <= 1)) + { + status = riscv_depthwise_conv_3x3_s8(ctx, + dw_conv_params, + quant_params, + input_dims, + input, + filter_dims, + filter, + bias_dims, + bias, + output_dims, + output); + } + else + { + status = riscv_depthwise_conv_s8_opt(ctx, + dw_conv_params, + quant_params, + input_dims, + input, + filter_dims, + filter, + bias_dims, + bias, + output_dims, + output); + } + } + else + { + status = riscv_depthwise_conv_s8(ctx, + dw_conv_params, + quant_params, + input_dims, + input, + filter_dims, + filter, + bias_dims, + bias, + output_dims, + output); + } + + /* Return to application */ + return status; +} + +int32_t riscv_depthwise_conv_wrapper_s8_get_buffer_size(const nmsis_nn_dw_conv_params *dw_conv_params, + const nmsis_nn_dims *input_dims, + const nmsis_nn_dims *filter_dims, + const nmsis_nn_dims *output_dims) +{ + (void)dw_conv_params; + int32_t size = 0; + + if (input_dims->c == output_dims->c && input_dims->n == 1) + { + size = riscv_depthwise_conv_s8_opt_get_buffer_size(input_dims, filter_dims); + } + + return size; +} + +/** + * @} end of NNConv group + */ diff --git a/components/nmsis/nn/src/ConvolutionFunctions/riscv_depthwise_separable_conv_HWC_q7.c b/components/nmsis/nn/src/ConvolutionFunctions/riscv_depthwise_separable_conv_HWC_q7.c new file mode 100644 index 00000000..2622ab23 --- /dev/null +++ b/components/nmsis/nn/src/ConvolutionFunctions/riscv_depthwise_separable_conv_HWC_q7.c @@ -0,0 +1,328 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_depthwise_separable_conv_HWC_q7.c + * Description: Q7 depthwise separable convolution function + * + * $Date: January 26, 2021 + * $Revision: V.1.0.2 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "riscv_nnfunctions.h" +#include "riscv_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/** + * @brief Q7 depthwise separable convolution function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimension + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * RISCV_MATH_SIZE_MISMATCH or RISCV_MATH_SUCCESS based on the outcome of size checking. + * + * @details + * + * Buffer size: + * + * bufferA size: 2*ch_im_in*dim_kernel*dim_kernel + * + * bufferB size: 0 + * + * Input dimension constraints: + * + * ch_im_in equals ch_im_out + * + * Implementation: + * There are 3 nested loop here: + * Inner loop: calculate each output value with MAC instruction over an accumulator + * Mid loop: loop over different output channel + * Outer loop: loop over different output (x, y) + */ + +riscv_status riscv_depthwise_separable_conv_HWC_q7(const q7_t *Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q7_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q7_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t *Im_out, + const uint16_t dim_im_out, + q15_t *bufferA, + q7_t *bufferB) +{ + (void)bufferB; +#if defined(RISCV_MATH_DSP) + /* Run the following code for RISC-V Core with DSP enabled */ + + int16_t i_out_y, i_out_x; + int16_t i_ker_y, i_ker_x; + q7_t *colBuffer = (q7_t *)bufferA; + q7_t *pBuffer = colBuffer; + const q7_t *pBias = bias; + q7_t *pOut = Im_out; + uint16_t rowCnt; + uint16_t row_shift; + + /* do some checking here, basically ch_im_in == ch_im_out */ + if (ch_im_in != ch_im_out) + { + return RISCV_MATH_SIZE_MISMATCH; + } + + for (i_out_y = 0; i_out_y < dim_im_out; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out; i_out_x++) + { + /* we first do im2col here */ + for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++) + { + for (i_ker_x = i_out_x * stride - padding; i_ker_x < i_out_x * stride - padding + dim_kernel; i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in || i_ker_x < 0 || i_ker_x >= dim_im_in) + { + riscv_fill_q7(0, pBuffer, ch_im_in); + /* memset(pBuffer, 0, ch_im_in); */ + } else + { + riscv_copy_q7((q7_t *) Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, pBuffer, ch_im_in); + /* memcpy(pBuffer, (q7_t *) Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, ch_im_in); */ + } + pBuffer += ch_im_in; + } + } + + /* we will do the computation here for each channel */ + rowCnt = ch_im_out >> 2; + row_shift = 0; + pBias = bias; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = (dim_kernel * dim_kernel) >> 2; + q7_t *pB = colBuffer + row_shift; + const q7_t *pA = wt + row_shift; + row_shift += 4; + + while (colCnt) + { + q31_t A1, A2, A3 , A4 , B1, B2, B3, B4 ; + q31_t opA1, opA2, opA3 , opA4 , opB1, opB2, opB3, opB4 ; + + opB1 = *__SIMD32(pB); + pB += ch_im_in; + opB2 = *__SIMD32(pB); + pB += ch_im_in; + opB3 = *__SIMD32(pB); + pB += ch_im_in; + opB4 = *__SIMD32(pB); + pB += ch_im_in; + + B1 = (opB1 & 0x000000ff) | + ((opB2 & 0x000000ff)<<8) | + ((opB3 & 0x000000ff)<<16) | + ((opB4 & 0x000000ff)<<24); + + B2 = ((opB1 & 0x0000ff00)>>8) | + ((opB2 & 0x0000ff00)) | + ((opB3 & 0x0000ff00)<<8) | + ((opB4 & 0x0000ff00)<<16); + + B3 = ((opB1 & 0x00ff0000)>>16) | + ((opB2 & 0x00ff0000)>>8) | + ((opB3 & 0x00ff0000)) | + ((opB4 & 0x00ff0000)<<8); + + B4 = ((opB1 & 0xff000000)>>24) | + ((opB2 & 0xff000000)>>16) | + ((opB3 & 0xff000000)>>8) | + ((opB4 & 0xff000000)); + + opA1 = *__SIMD32(pA); + pA += ch_im_in; + opA2 = *__SIMD32(pA); + pA += ch_im_in; + opA3 = *__SIMD32(pA); + pA += ch_im_in; + opA4 = *__SIMD32(pA); + pA += ch_im_in; + + A1 = (opA1 & 0x000000ff) | + ((opA2 & 0x000000ff)<<8) | + ((opA3 & 0x000000ff)<<16) | + ((opA4 & 0x000000ff)<<24); + + A2 = ((opA1 & 0x0000ff00)>>8) | + ((opA2 & 0x0000ff00)) | + ((opA3 & 0x0000ff00)<<8) | + ((opA4 & 0x0000ff00)<<16); + + A3 = ((opA1 & 0x00ff0000)>>16) | + ((opA2 & 0x00ff0000)>>8) | + ((opA3 & 0x00ff0000)) | + ((opA4 & 0x00ff0000)<<8); + + A4 = ((opA1 & 0xff000000)>>24) | + ((opA2 & 0xff000000)>>16) | + ((opA3 & 0xff000000)>>8) | + ((opA4 & 0xff000000)); + + sum = __RV_SMAQA(sum, A1, B1); + sum2 = __RV_SMAQA(sum2, A2, B2); + sum3 = __RV_SMAQA(sum3, A3, B3); + sum4 = __RV_SMAQA(sum4, A4, B4); + + colCnt--; + } + + + colCnt = (dim_kernel * dim_kernel) & 0x3; + while (colCnt) + { + union riscv_nnword inA, inB; + inA.word = riscv_nn_read_q7x4(pA); + pA += ch_im_in; + inB.word = riscv_nn_read_q7x4(pB); + pB += ch_im_in; + sum += inA.bytes[0] * inB.bytes[0]; + sum2 += inA.bytes[1] * inB.bytes[1]; + sum3 += inA.bytes[2] * inB.bytes[2]; + sum4 += inA.bytes[3] * inB.bytes[3]; + colCnt--; + } + + *pOut++ = (q7_t)__SSAT((sum >> out_shift), 8); + *pOut++ = (q7_t)__SSAT((sum2 >> out_shift), 8); + *pOut++ = (q7_t)__SSAT((sum3 >> out_shift), 8); + *pOut++ = (q7_t)__SSAT((sum4 >> out_shift), 8); + + rowCnt--; + } + + rowCnt = ch_im_out & 0x3; + while (rowCnt) + { + q7_t *pB = colBuffer + row_shift; + const q7_t *pA = wt + row_shift; + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + uint16_t colCnt = (dim_kernel * dim_kernel); + + row_shift += 1; + + while (colCnt) + { + q7_t A1 = *pA; + q7_t B1 = *pB; + pA += ch_im_in; + pB += ch_im_in; + sum += A1 * B1; + + colCnt--; + } + *pOut++ = (q7_t)__SSAT((sum >> out_shift), 8); + rowCnt--; + } + + /* clear counter and pointers */ + pBuffer = colBuffer; + } + } + +#else + (void)bufferA; + /* Run the following code as reference implementation for RISC-V Core without DSP */ + int i_out_y, i_out_x, i_ch_out, i_ker_x, i_ker_y; + int conv_out; + + /* do some checking here, basically ch_im_in == ch_im_out */ + if (ch_im_in != ch_im_out) + { + return RISCV_MATH_SIZE_MISMATCH; + } + + for (i_out_y = 0; i_out_y < dim_im_out; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out; i_out_x++) + { + for (i_ch_out = 0; i_ch_out < ch_im_out; i_ch_out++) + { + // for each output + conv_out = ((q31_t)(bias[i_ch_out]) << bias_shift) + NN_ROUND(out_shift); + for (i_ker_y = 0; i_ker_y < dim_kernel; i_ker_y++) + { + for (i_ker_x = 0; i_ker_x < dim_kernel; i_ker_x++) + { + int in_row = stride * i_out_y + i_ker_y - padding; + int in_col = stride * i_out_x + i_ker_x - padding; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in && in_col < dim_im_in) + { + conv_out += Im_in[(in_row * dim_im_in + in_col) * ch_im_in + i_ch_out] * + wt[(i_ker_y * dim_kernel + i_ker_x) * ch_im_out + i_ch_out]; + } + } + } + Im_out[(i_out_y * dim_im_out + i_out_x) * ch_im_out + i_ch_out] = + (q7_t)__SSAT((conv_out >> out_shift), 8); + } + } + } + +#endif /* RISCV_MATH_DSP */ + + /* Return to application */ + return RISCV_MATH_SUCCESS; +} + +/** + * @} end of NNConv group + */ diff --git a/components/nmsis/nn/src/ConvolutionFunctions/riscv_depthwise_separable_conv_HWC_q7_nonsquare.c b/components/nmsis/nn/src/ConvolutionFunctions/riscv_depthwise_separable_conv_HWC_q7_nonsquare.c new file mode 100644 index 00000000..4459d40b --- /dev/null +++ b/components/nmsis/nn/src/ConvolutionFunctions/riscv_depthwise_separable_conv_HWC_q7_nonsquare.c @@ -0,0 +1,379 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_depthwise_separable_conv_HWC_q7_nonsquare.c + * Description: Q7 depthwise separable convolution function (non-square shape) + * + * $Date: January 26, 2021 + * $Revision: V.1.0.2 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "riscv_nnfunctions.h" +#include "riscv_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/** + * @brief Q7 depthwise separable convolution function (non-square shape) + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in_x input tensor dimension x + * @param[in] dim_im_in_y input tensor dimension y + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel_x filter kernel size x + * @param[in] dim_kernel_y filter kernel size y + * @param[in] padding_x padding sizes x + * @param[in] padding_y padding sizes y + * @param[in] stride_x convolution stride x + * @param[in] stride_y convolution stride y + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out_x output tensor dimension x + * @param[in] dim_im_out_y output tensor dimension y + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * RISCV_MATH_SIZE_MISMATCH or RISCV_MATH_SUCCESS based on the outcome of size checking. + * + * This function is the version with full list of optimization tricks, but with + * some constraints: + * ch_im_in is equal to ch_im_out + * + */ + +riscv_status riscv_depthwise_separable_conv_HWC_q7_nonsquare(const q7_t *Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q7_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q7_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t *Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t *bufferA, + q7_t *bufferB) +{ + + (void)bufferB; + +#if defined (RISCV_MATH_DSP) || defined (RISCV_VECTOR) + /* Run the following code for RISC-V Core with DSP enabled */ + + /* + * Implementation: + * There are 3 nested loop here: + * Inner loop: calculate each output value with MAC instruction over an accumulator + * Mid loop: loop over different output channel + * Outer loop: loop over different output (x, y) + * + */ + + int16_t i_out_y, i_out_x; + int16_t i_ker_y, i_ker_x; + q7_t *colBuffer = (q7_t *)bufferA; + q7_t *pBuffer = colBuffer; + const q7_t *pBias = bias; + q7_t *pOut = Im_out; + uint16_t rowCnt; + uint16_t row_shift; + +#if defined(RISCV_VECTOR) + size_t l; + uint32_t blkCnt; + ptrdiff_t bstride; + vint8m2_t vam2,vbm2; + vint32m1_t vtemp; + l = vsetvl_e32m1(1); + vtemp = vsub_vv_i32m1(vtemp,vtemp, l); +#endif + + /* do some checking here, basically ch_im_in == ch_im_out */ + if (ch_im_in != ch_im_out) + { + return RISCV_MATH_SIZE_MISMATCH; + } + + for (i_out_y = 0; i_out_y < dim_im_out_y; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out_x; i_out_x++) + { + /* we first do im2col here */ + for (i_ker_y = i_out_y * stride_y - padding_y; i_ker_y < i_out_y * stride_y - padding_y + dim_kernel_y; + i_ker_y++) + { + for (i_ker_x = i_out_x * stride_x - padding_x; i_ker_x < i_out_x * stride_x - padding_x + dim_kernel_x; + i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in_y || i_ker_x < 0 || i_ker_x >= dim_im_in_x) + { + riscv_fill_q7(0, pBuffer, ch_im_in); + /* memset(pBuffer, 0, ch_im_in); */ + } else + { + riscv_copy_q7((q7_t *) Im_in + (i_ker_y * dim_im_in_x + i_ker_x) * ch_im_in, pBuffer, ch_im_in); + /* memcpy(pBuffer, (q7_t *) Im_in + (i_ker_y * dim_im_in_x + i_ker_x) * ch_im_in, ch_im_in); */ + } + pBuffer += ch_im_in; + } + } + + /* we will do the computation here for each channel */ + rowCnt = ch_im_out >> 2; + row_shift = 0; + pBias = bias; +#if defined(RISCV_VECTOR) + rowCnt = ch_im_out; + bstride = ch_im_in; + while (rowCnt) + { + q7_t *pB = colBuffer + row_shift; + const q7_t *pA = wt + row_shift; + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + uint16_t colCnt = (dim_kernel_x * dim_kernel_y); + + row_shift += 1; + + blkCnt = colCnt; + for (; (l = vsetvl_e8m2(blkCnt)) > 0; blkCnt -= l) { + vam2 = vlse8_v_i8m2(pA,bstride, l); + vbm2 = vlse8_v_i8m2(pB,bstride, l); + pA += l*ch_im_in; + pB += l*ch_im_in; + l = vsetvl_e8m2(blkCnt); + sum += vmv_x_s_i32m1_i32(vwredsum_vs_i16m4_i32m1(vtemp, vwmul_vv_i16m4(vam2, vbm2, l), vtemp, l)); + } + *pOut++ = (q7_t) __SSAT((sum >> out_shift), 8); + rowCnt--; + } +#else + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); +#if defined (RISCV_MATH_DSP) + uint16_t colCnt = (dim_kernel_x * dim_kernel_y) >> 2; + q7_t *pB = colBuffer + row_shift; + const q7_t *pA = wt + row_shift; + row_shift += 4; + + while (colCnt) + { + + q31_t A1, A2, A3 , A4 , B1, B2, B3, B4 ; + q31_t opA1, opA2, opA3 , opA4 , opB1, opB2, opB3, opB4 ; + + opB1 = *__SIMD32(pB); + pB += ch_im_in; + opB2 = *__SIMD32(pB); + pB += ch_im_in; + opB3 = *__SIMD32(pB); + pB += ch_im_in; + opB4 = *__SIMD32(pB); + pB += ch_im_in; + + B1 = (opB1 & 0x000000ff) | + ((opB2 & 0x000000ff)<<8) | + ((opB3 & 0x000000ff)<<16) | + ((opB4 & 0x000000ff)<<24); + + B2 = ((opB1 & 0x0000ff00)>>8) | + ((opB2 & 0x0000ff00)) | + ((opB3 & 0x0000ff00)<<8) | + ((opB4 & 0x0000ff00)<<16); + + B3 = ((opB1 & 0x00ff0000)>>16) | + ((opB2 & 0x00ff0000)>>8) | + ((opB3 & 0x00ff0000)) | + ((opB4 & 0x00ff0000)<<8); + + B4 = ((opB1 & 0xff000000)>>24) | + ((opB2 & 0xff000000)>>16) | + ((opB3 & 0xff000000)>>8) | + ((opB4 & 0xff000000)); + + opA1 = *__SIMD32(pA); + pA += ch_im_in; + opA2 = *__SIMD32(pA); + pA += ch_im_in; + opA3 = *__SIMD32(pA); + pA += ch_im_in; + opA4 = *__SIMD32(pA); + pA += ch_im_in; + + A1 = (opA1 & 0x000000ff) | + ((opA2 & 0x000000ff)<<8) | + ((opA3 & 0x000000ff)<<16) | + ((opA4 & 0x000000ff)<<24); + + A2 = ((opA1 & 0x0000ff00)>>8) | + ((opA2 & 0x0000ff00)) | + ((opA3 & 0x0000ff00)<<8) | + ((opA4 & 0x0000ff00)<<16); + + A3 = ((opA1 & 0x00ff0000)>>16) | + ((opA2 & 0x00ff0000)>>8) | + ((opA3 & 0x00ff0000)) | + ((opA4 & 0x00ff0000)<<8); + + A4 = ((opA1 & 0xff000000)>>24) | + ((opA2 & 0xff000000)>>16) | + ((opA3 & 0xff000000)>>8) | + ((opA4 & 0xff000000)); + + sum = __RV_SMAQA(sum , A1, B1); + sum2 = __RV_SMAQA(sum2, A2, B2); + sum3 = __RV_SMAQA(sum3, A3, B3); + sum4 = __RV_SMAQA(sum4, A4, B4); + colCnt--; + } + + + colCnt = (dim_kernel_x * dim_kernel_y) & 0x3; +#else + uint16_t colCnt = (dim_kernel_x * dim_kernel_y); + q7_t *pB = colBuffer + row_shift; + const q7_t *pA = wt + row_shift; + row_shift += 4; +#endif /*ndef RISCV_VECTOR*/ + while (colCnt) + { + union riscv_nnword inA, inB; + inA.word = riscv_nn_read_q7x4(pA); + pA += ch_im_in; + inB.word = riscv_nn_read_q7x4(pB); + pB += ch_im_in; + sum += inA.bytes[0] * inB.bytes[0]; + sum2 += inA.bytes[1] * inB.bytes[1]; + sum3 += inA.bytes[2] * inB.bytes[2]; + sum4 += inA.bytes[3] * inB.bytes[3]; + colCnt--; + } + + *pOut++ = (q7_t)__SSAT((sum >> out_shift), 8); + *pOut++ = (q7_t)__SSAT((sum2 >> out_shift), 8); + *pOut++ = (q7_t)__SSAT((sum3 >> out_shift), 8); + *pOut++ = (q7_t)__SSAT((sum4 >> out_shift), 8); + + rowCnt--; + } + + rowCnt = ch_im_out & 0x3; + while (rowCnt) + { + q7_t *pB = colBuffer + row_shift; + const q7_t *pA = wt + row_shift; + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + uint16_t colCnt = (dim_kernel_x * dim_kernel_y); + + row_shift += 1; + + while (colCnt) + { + q7_t A1 = *pA; + q7_t B1 = *pB; + pA += ch_im_in; + pB += ch_im_in; + sum += A1 * B1; + + colCnt--; + } + *pOut++ = (q7_t)__SSAT((sum >> out_shift), 8); + rowCnt--; + } +#endif + // clear counter and pointers + pBuffer = colBuffer; + } + } + +#else + (void)bufferA; + + /* Run the following code as reference implementation for RISC-V Core without DSP */ + int i_out_y, i_out_x, i_ch_out; + int i_ker_y, i_ker_x; + + /* do some checking here, basically ch_im_in == ch_im_out */ + if (ch_im_in != ch_im_out) + { + return RISCV_MATH_SIZE_MISMATCH; + } + + for (i_out_y = 0; i_out_y < dim_im_out_y; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out_x; i_out_x++) + { + for (i_ch_out = 0; i_ch_out < ch_im_out; i_ch_out++) + { + // for each output + int conv_out = ((q31_t)(bias[i_ch_out]) << bias_shift) + NN_ROUND(out_shift); + for (i_ker_y = 0; i_ker_y < dim_kernel_y; i_ker_y++) + { + for (i_ker_x = 0; i_ker_x < dim_kernel_x; i_ker_x++) + { + int in_row = stride_y * i_out_y + i_ker_y - padding_y; + int in_col = stride_x * i_out_x + i_ker_x - padding_x; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in_y && in_col < dim_im_in_x) + { + conv_out += Im_in[(in_row * dim_im_in_x + in_col) * ch_im_in + i_ch_out] * + wt[(i_ker_y * dim_kernel_x + i_ker_x) * ch_im_out + i_ch_out]; + } + } + } + Im_out[(i_out_y * dim_im_out_x + i_out_x) * ch_im_out + i_ch_out] = + (q7_t)__SSAT((conv_out >> out_shift), 8); + } + } + } + +#endif /* RISCV_MATH_DSP */ + + /* Return to application */ + return RISCV_MATH_SUCCESS; +} + +/** + * @} end of NNConv group + */ diff --git a/components/nmsis/nn/src/ConvolutionFunctions/riscv_nn_depthwise_conv_s8_core.c b/components/nmsis/nn/src/ConvolutionFunctions/riscv_nn_depthwise_conv_s8_core.c new file mode 100644 index 00000000..47fbe623 --- /dev/null +++ b/components/nmsis/nn/src/ConvolutionFunctions/riscv_nn_depthwise_conv_s8_core.c @@ -0,0 +1,65 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_nn_depthwise_conv_s8_core.c + * Description: Depthwise convolution on im2col buffers. + * + * $Date: 09. October 2020 + * $Revision: V.1.0.4 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ + +#include "riscv_nnsupportfunctions.h" + +/* + * Depthwise conv on an im2col buffer where the input channel equals + * output channel. + * + * Refer header file for details. + * + */ + +q7_t *riscv_nn_depthwise_conv_s8_core(const q7_t *row, + const q15_t *col, + const uint16_t num_ch, + const int32_t *out_shift, + const int32_t *out_mult, + const int32_t out_offset, + const int32_t activation_min, + const int32_t activation_max, + const uint16_t kernel_size, + const int32_t *const output_bias, + q7_t *out) +{ + (void)row; + (void)col; + (void)num_ch; + (void)out_shift; + (void)out_mult; + (void)out_offset; + (void)activation_min; + (void)activation_max; + (void)kernel_size; + (void)output_bias; + (void)out; + return NULL; +} diff --git a/components/nmsis/nn/src/ConvolutionFunctions/riscv_nn_mat_mult_kernel_q7.c b/components/nmsis/nn/src/ConvolutionFunctions/riscv_nn_mat_mult_kernel_q7.c new file mode 100644 index 00000000..db14130c --- /dev/null +++ b/components/nmsis/nn/src/ConvolutionFunctions/riscv_nn_mat_mult_kernel_q7.c @@ -0,0 +1,334 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_nn_mat_mult_kernel_q7_q15.c + * Description: Matrix-multiplication function for convolution + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ + +#include "riscv_nnsupportfunctions.h" +#include "riscv_nnfunctions.h" + + /** + * @brief Matrix-multiplication function for convolution + * @param[in] pA pointer to operand A + * @param[in] pInBuffer pointer to operand B, always conssists of 2 vectors + * @param[in] ch_im_out numRow of A + * @param[in] numCol_A numCol of A + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias the bias + * @param[in,out] pOut pointer to output + * @return The function returns the incremented output pointer + * + * @details + * + * This function does the matrix multiplication with weight matrix + * and 2 columns from im2col. + */ + +q7_t *riscv_nn_mat_mult_kernel_q7(const q7_t * pA, + const q7_t * pInBuffer, + const uint16_t ch_im_out, + const uint16_t numCol_A, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t * bias, + q7_t * pOut) +{ +#if defined (RISCV_MATH_DSP) || defined (RISCV_VECTOR) + /* set up the second output pointers */ + q7_t *pOut2 = pOut + ch_im_out; + const q7_t *pBias = bias; +#if defined (RISCV_VECTOR) && !defined (RISCV_MATH_DSP) + uint16_t rowCnt = ch_im_out >> 1; + /* this loop over rows in A */ + while (rowCnt) + { + /* setup pointers for B */ + const q7_t *pB = pInBuffer; + const q7_t *pB2 = pB + numCol_A; + + /* align the second pointer for A */ + const q7_t *pA2 = pA + numCol_A; + /* accumulate over the vector */ + size_t l; + uint32_t blkCnt = numCol_A; + q31_t sum,sum2,sum3,sum4; + // q7_t temp[] = {0}; + l = vsetvl_e8m1(blkCnt); + vint8m1_t va1m1,va2m1,vb1m1,vb2m1; + vint16m2_t vch00m2,vch01m2,vch10m2,vch11m2; + vint64m1_t vch00m1,vch01m1,vch10m1,vch11m1; + vint64m1_t vtemp00m1,vtemp01m1,vtemp10m1,vtemp11m1; + vint32m4_t vch00m4,vch01m4,vch10m4,vch11m4; + //initial array and temp sum to zero + vch00m4 = vmv_v_x_i32m4(0, l); + vch01m4 = vmv_v_x_i32m4(0, l); + vch10m4 = vmv_v_x_i32m4(0, l); + vch11m4 = vmv_v_x_i32m4(0, l); + vch00m1 = vmv_v_x_i64m1(0, l); + vch01m1 = vmv_v_x_i64m1(0, l); + vch10m1 = vmv_v_x_i64m1(0, l); + vch11m1 = vmv_v_x_i64m1(0, l); + vtemp00m1 = vmv_v_x_i64m1(0, l); + vtemp01m1 = vmv_v_x_i64m1(0, l); + vtemp10m1 = vmv_v_x_i64m1(0, l); + vtemp11m1 = vmv_v_x_i64m1(0, l); + for (; (l = vsetvl_e8m1(blkCnt)) > 0; blkCnt -= l) { + va1m1 = vle8_v_i8m1(pA , l); + va2m1 = vle8_v_i8m1(pA2, l); + vb1m1 = vle8_v_i8m1(pB , l); + vb2m1 = vle8_v_i8m1(pB2, l); + pA += l; + pA2 += l; + pB += l; + pB2 += l; + vch00m2= vwmul_vv_i16m2(va1m1, vb1m1, l); + vch01m2= vwmul_vv_i16m2(va1m1, vb2m1, l); + vch10m2= vwmul_vv_i16m2(va2m1, vb1m1, l); + vch11m2= vwmul_vv_i16m2(va2m1, vb2m1, l); + vch00m4 = vwadd_wv_i32m4(vch00m4, vch00m2, l); + vch01m4 = vwadd_wv_i32m4(vch01m4, vch01m2, l); + vch10m4 = vwadd_wv_i32m4(vch10m4, vch10m2, l); + vch11m4 = vwadd_wv_i32m4(vch11m4, vch11m2, l); + } + //set vl to max vl + l = vsetvl_e8m1(numCol_A); + //calculate sum + vch00m1 = vwredsum_vs_i32m4_i64m1(vtemp00m1, vch00m4, vtemp00m1, l); + vch01m1 = vwredsum_vs_i32m4_i64m1(vtemp01m1, vch01m4, vtemp01m1, l); + vch10m1 = vwredsum_vs_i32m4_i64m1(vtemp10m1, vch10m4, vtemp10m1, l); + vch11m1 = vwredsum_vs_i32m4_i64m1(vtemp11m1, vch11m4, vtemp11m1, l); + //Here we calculate sum of four vector + //write result scalar back + sum = (q31_t)vmv_x_s_i64m1_i64(vch00m1); + sum2 = (q31_t)vmv_x_s_i64m1_i64(vch01m1); + sum3 = (q31_t)vmv_x_s_i64m1_i64(vch10m1); + sum4 = (q31_t)vmv_x_s_i64m1_i64(vch11m1); + /* init the sum with bias */ + sum += ((q31_t)(*pBias) << bias_shift) + NN_ROUND(out_shift); + sum2 += ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + sum3 += ((q31_t)(*pBias) << bias_shift) + NN_ROUND(out_shift); + sum4 += ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + *pOut++ = (q7_t) __SSAT((sum >> out_shift), 8); + *pOut++ = (q7_t) __SSAT((sum3 >> out_shift), 8); + *pOut2++ = (q7_t) __SSAT((sum2 >> out_shift), 8); + *pOut2++ = (q7_t) __SSAT((sum4 >> out_shift), 8); + + /* skip the row computed with A2 */ + pA += numCol_A; + rowCnt--; + } /* for over ch_im_out */ + if (ch_im_out & 0x1) + { + /* setup pointers for B */ + const q7_t *pB = pInBuffer; + const q7_t *pB2 = pB + numCol_A; + /* accumulate over the vector */ + size_t l; + uint32_t blkCnt = numCol_A; + q31_t sum,sum2; + // q7_t temp[] = {0}; + l = vsetvl_e8m1(blkCnt); + vint8m1_t va1m1,va2m1,vb1m1,vb2m1; + vint16m2_t vch00m2,vch01m2; + vint64m1_t vch00m1,vch01m1; + vint64m1_t vtemp00m1,vtemp01m1; + vint32m4_t vch00m4,vch01m4; + //initial array and temp sum to zero + vch00m4 = vmv_v_x_i32m4(0, l); + vch01m4 = vmv_v_x_i32m4(0, l); + vch00m1 = vmv_v_x_i64m1(0, l); + vch01m1 = vmv_v_x_i64m1(0, l); + vtemp00m1 = vmv_v_x_i64m1(0, l); + vtemp01m1 = vmv_v_x_i64m1(0, l); + for (; (l = vsetvl_e8m1(blkCnt)) > 0; blkCnt -= l) { + va1m1 = vle8_v_i8m1(pA , l); + vb1m1 = vle8_v_i8m1(pB , l); + vb2m1 = vle8_v_i8m1(pB2, l); + pA += l; + pB += l; + pB2 += l; + vch00m2= vwmul_vv_i16m2(va1m1, vb1m1, l); + vch01m2= vwmul_vv_i16m2(va1m1, vb2m1, l); + vch00m4 = vwadd_wv_i32m4(vch00m4, vch00m2, l); + vch01m4 = vwadd_wv_i32m4(vch01m4, vch01m2, l); + } + //set vl to max vl + l = vsetvl_e8m1(numCol_A); + //calculate sum + vch00m1 = vwredsum_vs_i32m4_i64m1(vtemp00m1, vch00m4, vtemp00m1, l); + vch01m1 = vwredsum_vs_i32m4_i64m1(vtemp01m1, vch01m4, vtemp01m1, l); + //Here we calculate sum of four vector + //write result scalar back + sum = (q31_t)vmv_x_s_i64m1_i64(vch00m1); + sum2 = (q31_t)vmv_x_s_i64m1_i64(vch01m1); + /* init the sum with bias */ + sum += ((q31_t)(*pBias) << bias_shift) + NN_ROUND(out_shift); + sum2 += ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + *pOut++ = (q7_t) __SSAT((sum >> out_shift), 8); + *pOut2++ = (q7_t) __SSAT((sum2 >> out_shift), 8); + rowCnt--; + } +#else + uint16_t rowCnt = ch_im_out >> 1; + /* this loop over rows in A */ + while (rowCnt) + { + /* setup pointers for B */ + const q7_t *pB = pInBuffer; + const q7_t *pB2 = pB + numCol_A; + + /* align the second pointer for A */ + const q7_t *pA2 = pA + numCol_A; + + /* init the sum with bias */ + q31_t sum = ((q31_t)(*pBias) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)(*pBias) << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); +#if __RISCV_XLEN == 64 + uint16_t colCnt = numCol_A >> 3; + q63_t sum64 = 0, sum642 = 0, sum643 = 0, sum644 = 0; + /* accumulate over the vector */ + while (colCnt) + { + + q63_t inB1 = *__SIMD64(pB)++; + q63_t inB2 = *__SIMD64(pB2)++; + q63_t inA1 = *__SIMD64(pA)++; + q63_t inA2 = *__SIMD64(pA2)++; + + sum64 = __RV_SMAQA(sum64 , inA1, inB1); + sum642 = __RV_SMAQA(sum642, inA1, inB2); + sum643 = __RV_SMAQA(sum643, inA2, inB1); + sum644 = __RV_SMAQA(sum644, inA2, inB2); + + colCnt--; + } /* while over colCnt */ + sum = sum + (q31_t)(sum64 & 0xFFFFFFFF) + (q31_t)((sum64 & 0xFFFFFFFF00000000)>>32); + sum2 = sum2 + (q31_t)(sum642 & 0xFFFFFFFF) + (q31_t)((sum642 & 0xFFFFFFFF00000000)>>32); + sum3 = sum3 + (q31_t)(sum643 & 0xFFFFFFFF) + (q31_t)((sum643 & 0xFFFFFFFF00000000)>>32); + sum4 = sum4 + (q31_t)(sum644 & 0xFFFFFFFF) + (q31_t)((sum644 & 0xFFFFFFFF00000000)>>32); + colCnt = numCol_A & 0x7; +#else + uint16_t colCnt = numCol_A >> 2; + /* accumulate over the vector */ + while (colCnt) + { + //q31_t inA11, inA12, inA21, inA22; + q31_t inB1 = *__SIMD32(pB)++; + q31_t inB2 = *__SIMD32(pB2)++; + + q31_t inA1 = *__SIMD32(pA)++; + q31_t inA2 = *__SIMD32(pA2)++; + + sum = __RV_SMAQA(sum , inA1, inB1); + sum2 = __RV_SMAQA(sum2, inA1, inB2); + sum3 = __RV_SMAQA(sum3, inA2, inB1); + sum4 = __RV_SMAQA(sum4, inA2, inB2); + + colCnt--; + } /* while over colCnt */ + + colCnt = numCol_A & 0x3; +#endif /* __RISCV_XLEN == 64 */ + while (colCnt) + { + q7_t inA1 = *pA++; + q7_t inB1 = *pB++; + q7_t inA2 = *pA2++; + q7_t inB2 = *pB2++; + + sum += inA1 * inB1; + sum2 += inA1 * inB2; + sum3 += inA2 * inB1; + sum4 += inA2 * inB2; + colCnt--; + } /* while over colCnt */ + + *pOut++ = (q7_t) __SSAT((sum >> out_shift), 8); + *pOut++ = (q7_t) __SSAT((sum3 >> out_shift), 8); + *pOut2++ = (q7_t) __SSAT((sum2 >> out_shift), 8); + *pOut2++ = (q7_t) __SSAT((sum4 >> out_shift), 8); + + /* skip the row computed with A2 */ + pA += numCol_A; + rowCnt--; + } /* for over ch_im_out */ + + /* compute left-over row if any */ + if (ch_im_out & 0x1) + { + /* setup pointers for B */ + const q7_t *pB = pInBuffer; + const q7_t *pB2 = pB + numCol_A; + + /* load the bias */ + q31_t sum = ((q31_t)(*pBias) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = numCol_A >> 2; + while (colCnt) + { + q31_t inB1 = *__SIMD32(pB)++; + q31_t inB2 = *__SIMD32(pB2)++; + + q31_t inA1 = *__SIMD32(pA)++; + + sum = __RV_SMAQA(sum , inA1, inB1); + sum2 = __RV_SMAQA(sum2, inA1, inB2); + + colCnt--; + } + colCnt = numCol_A & 0x3; + while (colCnt) + { + q7_t inA1 = *pA++; + q15_t inB1 = *pB++; + q15_t inB2 = *pB2++; + + sum += inA1 * inB1; + sum2 += inA1 * inB2; + colCnt--; + } + + *pOut++ = (q7_t) __SSAT((sum >> out_shift), 8); + *pOut2++ = (q7_t) __SSAT((sum2 >> out_shift), 8); + } +#endif /* defined (RISCV_VECTOR) */ + pOut += ch_im_out; + + /* return the new output pointer with offset */ + return pOut; +#else + /* To be completed */ + return NULL; +#endif /* RISCV_MATH_DSP */ + +} \ No newline at end of file diff --git a/components/nmsis/nn/src/ConvolutionFunctions/riscv_nn_mat_mult_kernel_q7_q15.c b/components/nmsis/nn/src/ConvolutionFunctions/riscv_nn_mat_mult_kernel_q7_q15.c new file mode 100644 index 00000000..aa05593c --- /dev/null +++ b/components/nmsis/nn/src/ConvolutionFunctions/riscv_nn_mat_mult_kernel_q7_q15.c @@ -0,0 +1,188 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_nn_mat_mult_kernel_q7_q15.c + * Description: Matrix-multiplication function for convolution + * + * $Date: January 26, 2021 + * $Revision: V.1.0.2 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ + +#include "riscv_nnfunctions.h" +#include "riscv_nnsupportfunctions.h" + +/** + * @brief Matrix-multiplication function for convolution. + * + * @details Refer to header file for details. + * + */ + +q7_t *riscv_nn_mat_mult_kernel_q7_q15(const q7_t *pA, + const q15_t *pInBuffer, + const uint16_t ch_im_out, + const uint16_t numCol_A, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t *bias, + q7_t *pOut) +{ +#if defined(RISCV_MATH_DSP) + /* set up the second output pointers */ + q7_t *pOut2 = pOut + ch_im_out; + const q7_t *pBias = bias; + + uint16_t rowCnt = ch_im_out >> 1; + /* this loop over rows in A */ + while (rowCnt) + { + /* setup pointers for B */ + const q15_t *pB = pInBuffer; + const q15_t *pB2 = pB + numCol_A; + + /* align the second pointer for A */ + const q7_t *pA2 = pA + numCol_A; + + /* init the sum with bias */ + q31_t sum = ((q31_t)(*pBias) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)(*pBias) << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = numCol_A >> 2; + /* accumulate over the vector */ + while (colCnt) + { + q31_t inA11, inA12, inA21, inA22; + + q31_t inB1 = riscv_nn_read_q15x2_ia(&pB); + q31_t inB2 = riscv_nn_read_q15x2_ia(&pB2); + + pA = read_and_pad(pA, &inA11, &inA12); + pA2 = read_and_pad(pA2, &inA21, &inA22); + + sum = __SMLAD(inA11, inB1, sum); + sum2 = __SMLAD(inA11, inB2, sum2); + sum3 = __SMLAD(inA21, inB1, sum3); + sum4 = __SMLAD(inA21, inB2, sum4); + + inB1 = riscv_nn_read_q15x2_ia(&pB); + inB2 = riscv_nn_read_q15x2_ia(&pB2); + + sum = __SMLAD(inA12, inB1, sum); + sum2 = __SMLAD(inA12, inB2, sum2); + sum3 = __SMLAD(inA22, inB1, sum3); + sum4 = __SMLAD(inA22, inB2, sum4); + + // printf("sum = %x\n", sum); + colCnt--; + } /* while over colCnt */ + colCnt = numCol_A & 0x3; + while (colCnt) + { + q7_t inA1 = *pA++; + q15_t inB1 = *pB++; + q7_t inA2 = *pA2++; + q15_t inB2 = *pB2++; + + sum += inA1 * inB1; + sum2 += inA1 * inB2; + sum3 += inA2 * inB1; + sum4 += inA2 * inB2; + colCnt--; + } /* while over colCnt */ + *pOut++ = (q7_t)__SSAT((sum >> out_shift), 8); + *pOut++ = (q7_t)__SSAT((sum3 >> out_shift), 8); + *pOut2++ = (q7_t)__SSAT((sum2 >> out_shift), 8); + *pOut2++ = (q7_t)__SSAT((sum4 >> out_shift), 8); + + /* skip the row computed with A2 */ + pA += numCol_A; + rowCnt--; + } /* for over ch_im_out */ + + /* compute left-over row if any */ + if (ch_im_out & 0x1) + { + /* setup pointers for B */ + const q15_t *pB = pInBuffer; + const q15_t *pB2 = pB + numCol_A; + + /* load the bias */ + q31_t sum = ((q31_t)(*pBias) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = numCol_A >> 2; + while (colCnt) + { + q31_t inA11, inA12; + + q31_t inB1 = riscv_nn_read_q15x2_ia(&pB); + q31_t inB2 = riscv_nn_read_q15x2_ia(&pB2); + + pA = read_and_pad(pA, &inA11, &inA12); + + sum = __SMLAD(inA11, inB1, sum); + sum2 = __SMLAD(inA11, inB2, sum2); + + inB1 = riscv_nn_read_q15x2_ia(&pB); + inB2 = riscv_nn_read_q15x2_ia(&pB2); + + sum = __SMLAD(inA12, inB1, sum); + sum2 = __SMLAD(inA12, inB2, sum2); + + colCnt--; + } + colCnt = numCol_A & 0x3; + while (colCnt) + { + q7_t inA1 = *pA++; + q15_t inB1 = *pB++; + q15_t inB2 = *pB2++; + + sum += inA1 * inB1; + sum2 += inA1 * inB2; + colCnt--; + } + + *pOut++ = (q7_t)__SSAT((sum >> out_shift), 8); + *pOut2++ = (q7_t)__SSAT((sum2 >> out_shift), 8); + } + + pOut += ch_im_out; + + /* return the new output pointer with offset */ + return pOut; +#else + (void)pA; + (void)pInBuffer; + (void)ch_im_out; + (void)numCol_A; + (void)bias_shift; + (void)out_shift; + (void)bias; + (void)pOut; + /* To be completed */ + return NULL; +#endif /* RISCV_MATH_DSP */ +} diff --git a/components/nmsis/nn/src/ConvolutionFunctions/riscv_nn_mat_mult_kernel_q7_q15_reordered.c b/components/nmsis/nn/src/ConvolutionFunctions/riscv_nn_mat_mult_kernel_q7_q15_reordered.c new file mode 100644 index 00000000..9009003e --- /dev/null +++ b/components/nmsis/nn/src/ConvolutionFunctions/riscv_nn_mat_mult_kernel_q7_q15_reordered.c @@ -0,0 +1,138 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_nn_mat_mult_kernel_q7_q15_reordered.c + * Description: Matrix-multiplication function for convolution with reordered columns + * + * $Date: January 26, 2021 + * $Revision: V.1.0.2 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ + +#include "riscv_nnfunctions.h" +#include "riscv_nnsupportfunctions.h" + +/** + * @brief Matrix-multiplication function for convolution with re-ordered input. + * + * @details Refer to header file for details. + * + */ + +q7_t *riscv_nn_mat_mult_kernel_q7_q15_reordered(const q7_t *pA, + const q15_t *pInBuffer, + const uint16_t ch_im_out, + const uint16_t numCol_A, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t *bias, + q7_t *pOut) +{ + +#if defined(RISCV_MATH_DSP) + /* set up the second output pointers */ + q7_t *pOut2 = pOut + ch_im_out; + int i; + + /* this loop over rows in A */ + for (i = 0; i < ch_im_out; i += 2) + { + /* setup pointers for B */ + const q15_t *pB = pInBuffer; + const q15_t *pB2 = pB + numCol_A; + + /* align the second pointer for A */ + const q7_t *pA2 = pA + numCol_A; + + /* init the sum with bias */ + q31_t sum = ((q31_t)(bias[i]) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(bias[i]) << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)(bias[i + 1]) << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)(bias[i + 1]) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = numCol_A >> 2; + /* accumulate over the vector */ + while (colCnt) + { + q31_t inA11, inA12, inA21, inA22; + + q31_t inB1 = riscv_nn_read_q15x2_ia(&pB); + q31_t inB2 = riscv_nn_read_q15x2_ia(&pB2); + + pA = read_and_pad_reordered(pA, &inA11, &inA12); + pA2 = read_and_pad_reordered(pA2, &inA21, &inA22); + + sum = __SMLAD(inA11, inB1, sum); + sum2 = __SMLAD(inA11, inB2, sum2); + sum3 = __SMLAD(inA21, inB1, sum3); + sum4 = __SMLAD(inA21, inB2, sum4); + + inB1 = riscv_nn_read_q15x2_ia(&pB); + inB2 = riscv_nn_read_q15x2_ia(&pB2); + + sum = __SMLAD(inA12, inB1, sum); + sum2 = __SMLAD(inA12, inB2, sum2); + sum3 = __SMLAD(inA22, inB1, sum3); + sum4 = __SMLAD(inA22, inB2, sum4); + + colCnt--; + } /* while over colCnt */ + colCnt = numCol_A & 0x3; + while (colCnt) + { + q7_t inA1 = *pA++; + q15_t inB1 = *pB++; + q7_t inA2 = *pA2++; + q15_t inB2 = *pB2++; + + sum += inA1 * inB1; + sum2 += inA1 * inB2; + sum3 += inA2 * inB1; + sum4 += inA2 * inB2; + colCnt--; + } /* while over colCnt */ + *pOut++ = (q7_t)__SSAT((sum >> out_shift), 8); + *pOut++ = (q7_t)__SSAT((sum3 >> out_shift), 8); + *pOut2++ = (q7_t)__SSAT((sum2 >> out_shift), 8); + *pOut2++ = (q7_t)__SSAT((sum4 >> out_shift), 8); + + /* skip the row computed with A2 */ + pA += numCol_A; + } /* for over ch_im_out */ + + pOut += ch_im_out; + + /* return the new output pointer with offset */ + return pOut; +#else + (void)pA; + (void)pInBuffer; + (void)ch_im_out; + (void)numCol_A; + (void)bias_shift; + (void)out_shift; + (void)bias; + (void)pOut; + /* To be completed */ + return NULL; +#endif /* RISCV_MATH_DSP */ +} diff --git a/components/nmsis/nn/src/ConvolutionFunctions/riscv_nn_mat_mult_kernel_q7_reordered.c b/components/nmsis/nn/src/ConvolutionFunctions/riscv_nn_mat_mult_kernel_q7_reordered.c new file mode 100644 index 00000000..65613dca --- /dev/null +++ b/components/nmsis/nn/src/ConvolutionFunctions/riscv_nn_mat_mult_kernel_q7_reordered.c @@ -0,0 +1,233 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_nn_mat_mult_kernel_q7_q15_reordered.c + * Description: Matrix-multiplication function for convolution with reordered columns + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ + +#include "riscv_nnfunctions.h" +#include "riscv_nnsupportfunctions.h" + + /** + * @brief Matrix-multiplication function for convolution with reordered columns + * @param[in] pA pointer to operand A + * @param[in] pInBuffer pointer to operand B, always conssists of 2 vectors + * @param[in] ch_im_out numRow of A + * @param[in] numCol_A numCol of A + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias the bias + * @param[in,out] pOut pointer to output + * @return The function returns the incremented output pointer + * + * @details + * + * This function assumes that data in pInBuffer are reordered + */ + +q7_t *riscv_nn_mat_mult_kernel_q7_reordered(const q7_t * pA, + const q7_t * pInBuffer, + const uint16_t ch_im_out, + const uint16_t numCol_A, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t * bias, + q7_t * pOut) +{ + + +#if defined (RISCV_MATH_DSP) || defined(RISCV_VECTOR) + /* set up the second output pointers */ + q7_t *pOut2 = pOut + ch_im_out; + int i; + + /* this loop over rows in A */ + for (i = 0; i < ch_im_out; i += 2) + { + /* setup pointers for B */ + const q7_t *pB = pInBuffer; + const q7_t *pB2 = pB + numCol_A; + + /* align the second pointer for A */ + const q7_t *pA2 = pA + numCol_A; + +#if defined(RISCV_VECTOR) && !defined (RISCV_MATH_DSP) + /* accumulate over the vector */ + size_t l; + uint32_t blkCnt = numCol_A; + q31_t sum,sum2,sum3,sum4; + // q7_t temp[] = {0}; + l = vsetvl_e8m1(blkCnt); + vint8m1_t va1m1,va2m1,vb1m1,vb2m1; + vint16m2_t vch00m2,vch01m2,vch10m2,vch11m2; + vint64m1_t vch00m1,vch01m1,vch10m1,vch11m1; + vint64m1_t vtemp00m1,vtemp01m1,vtemp10m1,vtemp11m1; + vint32m4_t vch00m4,vch01m4,vch10m4,vch11m4; + //initial array and temp sum to zero + vch00m4 = vmv_v_x_i32m4(0, l); + vch01m4 = vmv_v_x_i32m4(0, l); + vch10m4 = vmv_v_x_i32m4(0, l); + vch11m4 = vmv_v_x_i32m4(0, l); + vtemp00m1 = vmv_v_x_i64m1(0, l); + for (; (l = vsetvl_e8m1(blkCnt)) > 0; blkCnt -= l) { + va1m1 = vle8_v_i8m1(pA , l); + va2m1 = vle8_v_i8m1(pA2, l); + vb1m1 = vle8_v_i8m1(pB , l); + vb2m1 = vle8_v_i8m1(pB2, l); + pA += l; + pA2 += l; + pB += l; + pB2 += l; + vch00m2= vwmul_vv_i16m2(va1m1, vb1m1, l); + vch01m2= vwmul_vv_i16m2(va1m1, vb2m1, l); + vch10m2= vwmul_vv_i16m2(va2m1, vb1m1, l); + vch11m2= vwmul_vv_i16m2(va2m1, vb2m1, l); + vch00m4 = vwadd_wv_i32m4(vch00m4, vch00m2, l); + vch01m4 = vwadd_wv_i32m4(vch01m4, vch01m2, l); + vch10m4 = vwadd_wv_i32m4(vch10m4, vch10m2, l); + vch11m4 = vwadd_wv_i32m4(vch11m4, vch11m2, l); + } + //set vl to max vl + l = vsetvl_e8m1(numCol_A); + vch00m1 = vwredsum_vs_i32m4_i64m1(vtemp00m1, vch00m4, vtemp00m1, l); + vch01m1 = vwredsum_vs_i32m4_i64m1(vtemp00m1, vch01m4, vtemp00m1, l); + vch10m1 = vwredsum_vs_i32m4_i64m1(vtemp00m1, vch10m4, vtemp00m1, l); + vch11m1 = vwredsum_vs_i32m4_i64m1(vtemp00m1, vch11m4, vtemp00m1, l); + //Here we calculate sum of four vector + //write result scalar back + sum = (q31_t)vmv_x_s_i64m1_i64(vch00m1); + sum2 = (q31_t)vmv_x_s_i64m1_i64(vch01m1); + sum3 = (q31_t)vmv_x_s_i64m1_i64(vch10m1); + sum4 = (q31_t)vmv_x_s_i64m1_i64(vch11m1); + /* init the sum with bias */ + sum += ((q31_t)(bias[i]) << bias_shift) + NN_ROUND(out_shift); + sum2 += ((q31_t)(bias[i]) << bias_shift) + NN_ROUND(out_shift); + sum3 += ((q31_t)(bias[i + 1]) << bias_shift) + NN_ROUND(out_shift); + sum4 += ((q31_t)(bias[i + 1]) << bias_shift) + NN_ROUND(out_shift); +#else + /* init the sum with bias */ + q31_t sum = ((q31_t)(bias[i]) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(bias[i]) << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)(bias[i + 1]) << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)(bias[i + 1]) << bias_shift) + NN_ROUND(out_shift); +#if __RISCV_XLEN == 64 + uint16_t colCnt = numCol_A >> 3; + q63_t sum64 = 0, sum642 = 0, sum643 = 0, sum644 = 0; + /* accumulate over the vector */ + while (colCnt) + { + + q63_t inB1 = *__SIMD64(pB)++; + q63_t inB2 = *__SIMD64(pB2)++; + q63_t inA1 = *__SIMD64(pA)++; + q63_t inA2 = *__SIMD64(pA2)++; + + sum64 = __RV_SMAQA(sum64 , inA1, inB1); + sum642 = __RV_SMAQA(sum642, inA1, inB2); + sum643 = __RV_SMAQA(sum643, inA2, inB1); + sum644 = __RV_SMAQA(sum644, inA2, inB2); + + colCnt--; + } /* while over colCnt */ + sum = sum + (q31_t)(sum64 & 0xFFFFFFFF) + (q31_t)((sum64 & 0xFFFFFFFF00000000)>>32); + sum2 = sum2 + (q31_t)(sum642 & 0xFFFFFFFF) + (q31_t)((sum642 & 0xFFFFFFFF00000000)>>32); + sum3 = sum3 + (q31_t)(sum643 & 0xFFFFFFFF) + (q31_t)((sum643 & 0xFFFFFFFF00000000)>>32); + sum4 = sum4 + (q31_t)(sum644 & 0xFFFFFFFF) + (q31_t)((sum644 & 0xFFFFFFFF00000000)>>32); + + colCnt = numCol_A & 0x7; +#else + uint16_t colCnt = numCol_A >> 2; + /* accumulate over the vector */ + while (colCnt) + { + /* + q31_t inA11, inA12, inA21, inA22; + q31_t inB1 = *__SIMD32(pB)++; + q31_t inB2 = *__SIMD32(pB2)++; + + pA = (q7_t *) read_and_pad_reordered((void *)pA, &inA11, &inA12); + pA2 = (q7_t *) read_and_pad_reordered((void *)pA2, &inA21, &inA22); + + sum = __SMLAD(inA11, inB1, sum); + sum2 = __SMLAD(inA11, inB2, sum2); + sum3 = __SMLAD(inA21, inB1, sum3); + sum4 = __SMLAD(inA21, inB2, sum4); + + inB1 = *__SIMD32(pB)++; + inB2 = *__SIMD32(pB2)++; + + sum = __SMLAD(inA12, inB1, sum); + sum2 = __SMLAD(inA12, inB2, sum2); + sum3 = __SMLAD(inA22, inB1, sum3); + sum4 = __SMLAD(inA22, inB2, sum4); + */ + + q31_t inB1 = *__SIMD32(pB)++; + q31_t inB2 = *__SIMD32(pB2)++; + + q31_t inA1 = *__SIMD32(pA)++; + q31_t inA2 = *__SIMD32(pA2)++; + + sum = __RV_SMAQA(sum , inA1, inB1); + sum2 = __RV_SMAQA(sum2, inA1, inB2); + sum3 = __RV_SMAQA(sum3, inA2, inB1); + sum4 = __RV_SMAQA(sum4, inA2, inB2); + + colCnt--; + } /* while over colCnt */ + colCnt = numCol_A & 0x3; +#endif /* __RISCV_XLEN == 64 */ + while (colCnt) + { + q7_t inA1 = *pA++; + q7_t inB1 = *pB++; + q7_t inA2 = *pA2++; + q7_t inB2 = *pB2++; + + sum += inA1 * inB1; + sum2 += inA1 * inB2; + sum3 += inA2 * inB1; + sum4 += inA2 * inB2; + colCnt--; + } /* while over colCnt */ +#endif /* defined(RISCV_VECTOR) */ + *pOut++ = (q7_t) __SSAT((sum >> out_shift), 8); + *pOut++ = (q7_t) __SSAT((sum3 >> out_shift), 8); + *pOut2++ = (q7_t) __SSAT((sum2 >> out_shift), 8); + *pOut2++ = (q7_t) __SSAT((sum4 >> out_shift), 8); + /* skip the row computed with A2 */ + pA += numCol_A; + } /* for over ch_im_out */ + + pOut += ch_im_out; + + /* return the new output pointer with offset */ + return pOut; +#else + /* To be completed */ + return NULL; +#endif /* RISCV_MATH_DSP */ +} diff --git a/components/nmsis/nn/src/ConvolutionFunctions/riscv_nn_mat_mult_kernel_s8.c b/components/nmsis/nn/src/ConvolutionFunctions/riscv_nn_mat_mult_kernel_s8.c new file mode 100644 index 00000000..6907a732 --- /dev/null +++ b/components/nmsis/nn/src/ConvolutionFunctions/riscv_nn_mat_mult_kernel_s8.c @@ -0,0 +1,379 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_nn_mat_mult_kernel_s8.c + * Description: Matrix-multiplication function for convolution + * + * $Date: May 29, 2020 + * $Revision: V.1.0.2 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ + +#include "riscv_nnsupportfunctions.h" +#include "riscv_nnfunctions.h" + +/* + * Matrix-multiplication function for convolution with per-channel requantization. + * + * Refer header file for details. + * + */ + +q7_t *riscv_nn_mat_mult_kernel_s8(const q7_t *input_a, + const q7_t *input_b, + const uint16_t output_ch, + const int32_t *out_shift, + const int32_t *out_mult, + const int32_t out_offset, + const int16_t activation_min, + const int16_t activation_max, + const uint16_t num_col_a, + const int32_t *const output_bias, + q7_t *out_0) +{ +#if defined(RISCV_VECTOR) + /* set up the second output pointers */ + q7_t *out_1 = out_0 + output_ch; + const int32_t *bias = output_bias; + + size_t l; + uint32_t blkCnt; + vint8m2_t va1m2,va2m2,vb1m2,vb2m2; + vint32m1_t vch00m1,vch01m1,vch10m1,vch11m1; + vint32m1_t vtemp; + vint32m8_t vch00m8,vch01m8,vch10m8,vch11m8; + // q31_t ch_0_out_0,ch_0_out_1; + l = vsetvl_e32m1(1); + vtemp = vsub_vv_i32m1(vtemp,vtemp, l); + + uint16_t row_count = output_ch/2; + const q7_t *ip_a0 = input_a; + /* compute the last odd numbered row if any */ + while (row_count) + { + /* setup pointers for B */ + const q7_t *ip_b0 = input_b; + const q7_t *ip_b1 = ip_b0 + num_col_a; + const q7_t *ip_a1 = ip_a0 + num_col_a; + + /* load the bias */ + q31_t ch_0_out_0 = *bias; + q31_t ch_0_out_1 = *bias++; + q31_t ch_1_out_0 = *bias; + q31_t ch_1_out_1 = *bias++; + + uint16_t col_count = num_col_a; + blkCnt = col_count; + vch00m8 = vand_vx_i32m8(vch00m8, 0, l); + vch01m8 = vand_vx_i32m8(vch01m8, 0, l); + vch10m8 = vand_vx_i32m8(vch10m8, 0, l); + vch11m8 = vand_vx_i32m8(vch11m8, 0, l); + for (; (l = vsetvl_e8m2(blkCnt)) > 0; blkCnt -= l) { + va1m2 = vle8_v_i8m2(ip_a0, l); + va2m2 = vle8_v_i8m2(ip_a1, l); + vb1m2 = vle8_v_i8m2(ip_b0, l); + vb2m2 = vle8_v_i8m2(ip_b1, l); + ip_a0 += l; + ip_a1 += l; + ip_b0 += l; + ip_b1 += l; + l = vsetvl_e8m2(blkCnt); + ch_0_out_0 += vmv_x_s_i32m1_i32(vwredsum_vs_i16m4_i32m1(vtemp, vwmul_vv_i16m4(va1m2, vb1m2, l), vtemp, l)); + l = vsetvl_e8m2(blkCnt); + ch_0_out_1 += vmv_x_s_i32m1_i32(vwredsum_vs_i16m4_i32m1(vtemp, vwmul_vv_i16m4(va1m2, vb2m2, l), vtemp, l)); + l = vsetvl_e8m2(blkCnt); + ch_1_out_0 += vmv_x_s_i32m1_i32(vwredsum_vs_i16m4_i32m1(vtemp, vwmul_vv_i16m4(va2m2, vb1m2, l), vtemp, l)); + l = vsetvl_e8m2(blkCnt); + ch_1_out_1 += vmv_x_s_i32m1_i32(vwredsum_vs_i16m4_i32m1(vtemp, vwmul_vv_i16m4(va2m2, vb2m2, l), vtemp, l)); + } + + ch_0_out_0 = riscv_nn_requantize(ch_0_out_0, *out_mult, *out_shift); + ch_0_out_0 += out_offset; + ch_0_out_0 = MAX(ch_0_out_0, activation_min); + ch_0_out_0 = MIN(ch_0_out_0, activation_max); + *out_0++ = (q7_t)ch_0_out_0; + + ch_0_out_1 = riscv_nn_requantize(ch_0_out_1, *out_mult, *out_shift); + ch_0_out_1 += out_offset; + ch_0_out_1 = MAX(ch_0_out_1, activation_min); + ch_0_out_1 = MIN(ch_0_out_1, activation_max); + *out_1++ = (q7_t)ch_0_out_1; + out_mult++; + out_shift++; + + ch_1_out_0 = riscv_nn_requantize(ch_1_out_0, *out_mult, *out_shift); + ch_1_out_0 += out_offset; + ch_1_out_0 = MAX(ch_1_out_0, activation_min); + ch_1_out_0 = MIN(ch_1_out_0, activation_max); + *out_0++ = (q7_t)ch_1_out_0; + + ch_1_out_1 = riscv_nn_requantize(ch_1_out_1, *out_mult, *out_shift); + ch_1_out_1 += out_offset; + ch_1_out_1 = MAX(ch_1_out_1, activation_min); + ch_1_out_1 = MIN(ch_1_out_1, activation_max); + *out_1++ = (q7_t)ch_1_out_1; + out_mult++; + out_shift++; + + row_count--; + ip_a0 += num_col_a; + } + if (output_ch & 0x1) + { + const q7_t *ip_b0 = input_b; + const q7_t *ip_b1 = ip_b0 + num_col_a; + + /* load the bias */ + q31_t ch_0_out_0 = *bias; + q31_t ch_0_out_1 = *bias++; + + uint16_t col_count = num_col_a; + // while (col_count) + blkCnt = col_count; + l = vsetvl_e8m2(blkCnt); + vch00m8 = vand_vx_i32m8(vch00m8, 0, l); + vch01m8 = vand_vx_i32m8(vch01m8, 0, l); + for (; (l = vsetvl_e8m2(blkCnt)) > 0; blkCnt -= l) { + va1m2 = vle8_v_i8m2(ip_a0, l); + vb1m2 = vle8_v_i8m2(ip_b0, l); + vb2m2 = vle8_v_i8m2(ip_b1, l); + ip_a0 += l; + ip_b0 += l; + ip_b1 += l; + vch00m8 = vwadd_wv_i32m8(vch00m8, vwmul_vv_i16m4(va1m2, vb1m2, l), l); + vch01m8 = vwadd_wv_i32m8(vch01m8, vwmul_vv_i16m4(va1m2, vb2m2, l), l); + } + l = vsetvl_e32m8(col_count); + vch00m1 = vredsum_vs_i32m8_i32m1(vtemp, vch00m8, vtemp, l); + vch01m1 = vredsum_vs_i32m8_i32m1(vtemp, vch01m8, vtemp, l); + + l = vsetvl_e32m1(1); + ch_0_out_0 += vmv_x_s_i32m1_i32(vch00m1); + ch_0_out_1 += vmv_x_s_i32m1_i32(vch01m1); + // printf("ch_0_out_0 is %d\n",ch_0_out_0); + + ch_0_out_0 = riscv_nn_requantize(ch_0_out_0, *out_mult, *out_shift); + ch_0_out_0 += out_offset; + ch_0_out_0 = MAX(ch_0_out_0, activation_min); + ch_0_out_0 = MIN(ch_0_out_0, activation_max); + *out_0++ = (q7_t)ch_0_out_0; + + ch_0_out_1 = riscv_nn_requantize(ch_0_out_1, *out_mult, *out_shift); + ch_0_out_1 += out_offset; + ch_0_out_1 = MAX(ch_0_out_1, activation_min); + ch_0_out_1 = MIN(ch_0_out_1, activation_max); + *out_1++ = (q7_t)ch_0_out_1; + out_mult++; + out_shift++; + } + + out_0 += output_ch; + + /* return the new output pointer with offset */ + return out_0; + + +#else +#if defined(RISCV_MATH_DSP) + /* set up the second output pointers */ + q7_t *out_1 = out_0 + output_ch; + const int32_t *bias = output_bias; + + uint16_t row_count = output_ch / 2; + const q7_t *ip_a0 = input_a; + /* this loop over rows in A */ + while (row_count) + { + /* setup pointers for B */ + const q7_t *ip_b0 = input_b; + const q7_t *ip_b1 = ip_b0 + num_col_a; + + /* align the second pointer for A */ + const q7_t *ip_a1 = ip_a0 + num_col_a; + + /* Init accumulator with bias for channel N and N + 1 */ + q31_t ch_0_out_0 = *bias; + q31_t ch_0_out_1 = *bias++; + q31_t ch_1_out_0 = *bias; + q31_t ch_1_out_1 = *bias++; + + uint16_t col_count = num_col_a / 4; + /* accumulate over the vector */ + while (col_count) + { + q31_t inB1 = *__SIMD32(ip_b0)++; + q31_t inB2 = *__SIMD32(ip_b1)++; + + q31_t inA1 = *__SIMD32(ip_a0)++; + q31_t inA2 = *__SIMD32(ip_a1)++; + + ch_0_out_0 = __RV_SMAQA(ch_0_out_0, inA1, inB1); + ch_0_out_1 = __RV_SMAQA(ch_0_out_1, inA1, inB2); + ch_1_out_0 = __RV_SMAQA(ch_1_out_0, inA2, inB1); + ch_1_out_1 = __RV_SMAQA(ch_1_out_1, inA2, inB2); + + // q31_t a01, a02, a11, a12; + // q31_t b0 = riscv_nn_read_q15x2_ia(&ip_b0); + // q31_t b1 = riscv_nn_read_q15x2_ia(&ip_b1); + + // ip_a0 = read_and_pad(ip_a0, &a01, &a02); + // ip_a1 = read_and_pad(ip_a1, &a11, &a12); + + // ch_0_out_0 = __SMLAD(a01, b0, ch_0_out_0); + // ch_0_out_1 = __SMLAD(a01, b1, ch_0_out_1); + // ch_1_out_0 = __SMLAD(a11, b0, ch_1_out_0); + // ch_1_out_1 = __SMLAD(a11, b1, ch_1_out_1); + + // b0 = riscv_nn_read_q15x2_ia(&ip_b0); + // b1 = riscv_nn_read_q15x2_ia(&ip_b1); + + // ch_0_out_0 = __SMLAD(a02, b0, ch_0_out_0); + // ch_0_out_1 = __SMLAD(a02, b1, ch_0_out_1); + // ch_1_out_0 = __SMLAD(a12, b0, ch_1_out_0); + // ch_1_out_1 = __SMLAD(a12, b1, ch_1_out_1); + + col_count--; + } /* while over col_count */ + col_count = num_col_a & 0x3; + while (col_count) + { + q7_t a0 = *ip_a0++; + q7_t b0 = *ip_b0++; + q7_t a1 = *ip_a1++; + q7_t b1 = *ip_b1++; + + ch_0_out_0 += a0 * b0; + ch_0_out_1 += a0 * b1; + ch_1_out_0 += a1 * b0; + ch_1_out_1 += a1 * b1; + col_count--; + } /* while over col_count */ + + ch_0_out_0 = riscv_nn_requantize(ch_0_out_0, *out_mult, *out_shift); + ch_0_out_0 += out_offset; + ch_0_out_0 = MAX(ch_0_out_0, activation_min); + ch_0_out_0 = MIN(ch_0_out_0, activation_max); + *out_0++ = (q7_t)ch_0_out_0; + + ch_0_out_1 = riscv_nn_requantize(ch_0_out_1, *out_mult, *out_shift); + ch_0_out_1 += out_offset; + ch_0_out_1 = MAX(ch_0_out_1, activation_min); + ch_0_out_1 = MIN(ch_0_out_1, activation_max); + *out_1++ = (q7_t)ch_0_out_1; + out_mult++; + out_shift++; + ch_1_out_0 = riscv_nn_requantize(ch_1_out_0, *out_mult, *out_shift); + ch_1_out_0 += out_offset; + ch_1_out_0 = MAX(ch_1_out_0, activation_min); + ch_1_out_0 = MIN(ch_1_out_0, activation_max); + *out_0++ = (q7_t)ch_1_out_0; + + ch_1_out_1 = riscv_nn_requantize(ch_1_out_1, *out_mult, *out_shift); + ch_1_out_1 += out_offset; + ch_1_out_1 = MAX(ch_1_out_1, activation_min); + ch_1_out_1 = MIN(ch_1_out_1, activation_max); + *out_1++ = (q7_t)ch_1_out_1; + out_mult++; + out_shift++; + + /* skip row */ + ip_a0 += num_col_a; + row_count--; + } + + /* compute the last odd numbered row if any */ + if (output_ch & 0x1) + { + /* setup pointers for B */ + const q7_t *ip_b0 = input_b; + const q7_t *ip_b1 = ip_b0 + num_col_a; + + /* load the bias */ + q31_t ch_0_out_0 = *bias; + q31_t ch_0_out_1 = *bias++; + + uint16_t col_count = num_col_a >> 2; + while (col_count) + { + q31_t a01, a02; + q31_t b0 = riscv_nn_read_q7x4_ia(&ip_b0); + q31_t b1 = riscv_nn_read_q7x4_ia(&ip_b1); + a01 = riscv_nn_read_q7x4_ia(&ip_a0); + // ip_a0 = read_and_pad(ip_a0, &a01, &a02); + + ch_0_out_0 = __RV_SMAQA(ch_0_out_0, a01, b0); + ch_0_out_1 = __RV_SMAQA(ch_0_out_1, a01, b1); + + // b0 = riscv_nn_read_q15x2_ia(&ip_b0); + // b1 = riscv_nn_read_q15x2_ia(&ip_b1); + // ch_0_out_0 = __SMLAD(a02, b0, ch_0_out_0); + // ch_0_out_1 = __SMLAD(a02, b1, ch_0_out_1); + + col_count--; + } + col_count = num_col_a & 0x3; + while (col_count) + { + q7_t a0 = *ip_a0++; + q7_t b0 = *ip_b0++; + q7_t b1 = *ip_b1++; + + ch_0_out_0 += a0 * b0; + ch_0_out_1 += a0 * b1; + col_count--; + } + ch_0_out_0 = riscv_nn_requantize(ch_0_out_0, *out_mult, *out_shift); + ch_0_out_0 += out_offset; + ch_0_out_0 = MAX(ch_0_out_0, activation_min); + ch_0_out_0 = MIN(ch_0_out_0, activation_max); + *out_0++ = (q7_t)ch_0_out_0; + + ch_0_out_1 = riscv_nn_requantize(ch_0_out_1, *out_mult, *out_shift); + ch_0_out_1 += out_offset; + ch_0_out_1 = MAX(ch_0_out_1, activation_min); + ch_0_out_1 = MIN(ch_0_out_1, activation_max); + *out_1++ = (q7_t)ch_0_out_1; + out_mult++; + out_shift++; + } + + out_0 += output_ch; + + /* return the new output pointer with offset */ + return out_0; +#else + (void)input_a; + (void)input_b; + (void)output_ch; + (void)out_shift; + (void)out_mult; + (void)out_offset; + (void)activation_min; + (void)activation_max; + (void)num_col_a; + (void)output_bias; + (void)out_0; + /* To be completed */ + return NULL; +#endif +#endif /* defined(RISCV_VECTOR) */ +} diff --git a/components/nmsis/nn/src/ConvolutionFunctions/riscv_nn_mat_mult_kernel_s8_reordered.c b/components/nmsis/nn/src/ConvolutionFunctions/riscv_nn_mat_mult_kernel_s8_reordered.c new file mode 100644 index 00000000..bc6380ed --- /dev/null +++ b/components/nmsis/nn/src/ConvolutionFunctions/riscv_nn_mat_mult_kernel_s8_reordered.c @@ -0,0 +1,213 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_nn_mat_mult_kernel_s8_reordered.c + * Description: Matrix-multiplication function for convolution with reordered columns + * + * $Date: February 27, 2020 + * $Revision: V.1.0.2 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ + +#include "riscv_nnfunctions.h" +#include "riscv_nnsupportfunctions.h" + +/* + * Matrix-multiplication with re-ordered input and bias inputs for convolution with per-channel + * requantization. The re-ordering is a consequence of sign extension is done by the SXTB16 command. + * + * Refer header file for details. This function differs from riscv_nn_mat_mult_kernel_s8(), in that it uses + * read_and_pad_reordered() instead of riscv_nn_mat_mult_kernel_s8(). Investigating the cycles impact and + * unifying these two functions is a potential future improvement. + * + */ + +q7_t *riscv_nn_mat_mult_kernel_s8_reordered(const q7_t *input_a, + const q7_t *input_b, + const uint16_t output_ch, + const int32_t *out_shift, + const int32_t *out_mult, + const int32_t out_offset, + const int16_t activation_min, + const int16_t activation_max, + const uint16_t num_col_a, + const int32_t *const output_bias, + q7_t *out_0) +{ +#if defined(RISCV_MATH_DSP) + /* set up the second output pointers */ + q7_t *out_1 = out_0 + output_ch; + const int32_t *bias = output_bias; + + uint16_t row_count = output_ch / 2; + const q7_t *ip_a0 = input_a; + /* this loop over rows in A */ + while (row_count) + { + /* setup pointers for B */ + const q15_t *ip_b0 = input_b; + const q15_t *ip_b1 = ip_b0 + num_col_a; + + /* align the second pointer for A */ + const q7_t *ip_a1 = ip_a0 + num_col_a; + + /* Init accumulator with bias for channel N and N + 1 */ + q31_t ch_0_out_0 = *bias; + q31_t ch_0_out_1 = *bias++; + q31_t ch_1_out_0 = *bias; + q31_t ch_1_out_1 = *bias++; + + uint16_t col_count = num_col_a / 4; + /* accumulate over the vector */ + while (col_count) + { + // q31_t a01, a02, a11, a12; + // q31_t b0 = riscv_nn_read_q15x2_ia(&ip_b0); + // q31_t b1 = riscv_nn_read_q15x2_ia(&ip_b1); + + // ip_a0 = read_and_pad_reordered(ip_a0, &a01, &a02); + // ip_a1 = read_and_pad_reordered(ip_a1, &a11, &a12); + + // ch_0_out_0 = __SMLAD(a01, b0, ch_0_out_0); + // ch_0_out_1 = __SMLAD(a01, b1, ch_0_out_1); + // ch_1_out_0 = __SMLAD(a11, b0, ch_1_out_0); + // ch_1_out_1 = __SMLAD(a11, b1, ch_1_out_1); + + // b0 = riscv_nn_read_q15x2_ia(&ip_b0); + // b1 = riscv_nn_read_q15x2_ia(&ip_b1); + + // ch_0_out_0 = __SMLAD(a02, b0, ch_0_out_0); + // ch_0_out_1 = __SMLAD(a02, b1, ch_0_out_1); + // ch_1_out_0 = __SMLAD(a12, b0, ch_1_out_0); + // ch_1_out_1 = __SMLAD(a12, b1, ch_1_out_1); + + q31_t inB1 = *__SIMD32(ip_b0)++; + q31_t inB2 = *__SIMD32(ip_b1)++; + + q31_t inA1 = *__SIMD32(ip_a0)++; + q31_t inA2 = *__SIMD32(ip_a1)++; + + ch_0_out_0 = __RV_SMAQA(ch_0_out_0, inA1, inB1); + ch_0_out_1 = __RV_SMAQA(ch_0_out_1, inA1, inB2); + ch_1_out_0 = __RV_SMAQA(ch_1_out_0, inA2, inB1); + ch_1_out_1 = __RV_SMAQA(ch_1_out_1, inA2, inB2); + + col_count--; + } /* while over col_count */ + + ch_0_out_0 = riscv_nn_requantize(ch_0_out_0, *out_mult, *out_shift); + ch_0_out_0 += out_offset; + ch_0_out_0 = MAX(ch_0_out_0, activation_min); + ch_0_out_0 = MIN(ch_0_out_0, activation_max); + *out_0++ = (q7_t)ch_0_out_0; + + ch_0_out_1 = riscv_nn_requantize(ch_0_out_1, *out_mult, *out_shift); + ch_0_out_1 += out_offset; + ch_0_out_1 = MAX(ch_0_out_1, activation_min); + ch_0_out_1 = MIN(ch_0_out_1, activation_max); + *out_1++ = (q7_t)ch_0_out_1; + out_mult++; + out_shift++; + + ch_1_out_0 = riscv_nn_requantize(ch_1_out_0, *out_mult, *out_shift); + ch_1_out_0 += out_offset; + ch_1_out_0 = MAX(ch_1_out_0, activation_min); + ch_1_out_0 = MIN(ch_1_out_0, activation_max); + *out_0++ = (q7_t)ch_1_out_0; + + ch_1_out_1 = riscv_nn_requantize(ch_1_out_1, *out_mult, *out_shift); + ch_1_out_1 += out_offset; + ch_1_out_1 = MAX(ch_1_out_1, activation_min); + ch_1_out_1 = MIN(ch_1_out_1, activation_max); + *out_1++ = (q7_t)ch_1_out_1; + out_mult++; + out_shift++; + + /* skip row */ + ip_a0 += num_col_a; + row_count--; + } + + if (output_ch & 1) + { + /* setup pointers for B */ + const q15_t *ip_b0 = input_b; + const q15_t *ip_b1 = ip_b0 + num_col_a; + + /* Init accumulator with bias for channel N + 1 */ + q31_t ch_0_out_0 = *bias; + q31_t ch_0_out_1 = ch_0_out_0; + + int32_t col_count = num_col_a / 4; + while (col_count) + { + q31_t a01, a02; + q31_t b0 = riscv_nn_read_q15x2_ia(&ip_b0); + q31_t b1 = riscv_nn_read_q15x2_ia(&ip_b1); + + ip_a0 = read_and_pad_reordered(ip_a0, &a01, &a02); + + ch_0_out_0 = __SMLAD(a01, b0, ch_0_out_0); + ch_0_out_1 = __SMLAD(a01, b1, ch_0_out_1); + + b0 = riscv_nn_read_q15x2_ia(&ip_b0); + b1 = riscv_nn_read_q15x2_ia(&ip_b1); + + ch_0_out_0 = __SMLAD(a02, b0, ch_0_out_0); + ch_0_out_1 = __SMLAD(a02, b1, ch_0_out_1); + + col_count--; + } /* while over col_count */ + + ch_0_out_0 = riscv_nn_requantize(ch_0_out_0, *out_mult, *out_shift); + ch_0_out_0 += out_offset; + ch_0_out_0 = MAX(ch_0_out_0, activation_min); + ch_0_out_0 = MIN(ch_0_out_0, activation_max); + *out_0++ = (q7_t)ch_0_out_0; + + ch_0_out_1 = riscv_nn_requantize(ch_0_out_1, *out_mult, *out_shift); + ch_0_out_1 += out_offset; + ch_0_out_1 = MAX(ch_0_out_1, activation_min); + ch_0_out_1 = MIN(ch_0_out_1, activation_max); + *out_1++ = (q7_t)ch_0_out_1; + } + + out_0 += output_ch; + + /* return the new output pointer with offset */ + return out_0; +#else + (void)input_a; + (void)input_b; + (void)output_ch; + (void)out_shift; + (void)out_mult; + (void)out_offset; + (void)activation_min; + (void)activation_max; + (void)num_col_a; + (void)output_bias; + (void)out_0; + /* To be completed */ + return NULL; +#endif +} diff --git a/components/nmsis/nn/src/ConvolutionFunctions/riscv_nn_mat_mult_kernel_s8_s16.c b/components/nmsis/nn/src/ConvolutionFunctions/riscv_nn_mat_mult_kernel_s8_s16.c new file mode 100644 index 00000000..0d335a4f --- /dev/null +++ b/components/nmsis/nn/src/ConvolutionFunctions/riscv_nn_mat_mult_kernel_s8_s16.c @@ -0,0 +1,234 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_nn_mat_mult_kernel_s8_s16.c + * Description: Matrix-multiplication function for convolution + * + * $Date: 09. October 2020 + * $Revision: V.1.0.3 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ + +#include "riscv_nnfunctions.h" +#include "riscv_nnsupportfunctions.h" + +/* + * Matrix-multiplication function for convolution with per-channel requantization. + * + * Refer header file for details. + * + */ + +q7_t *riscv_nn_mat_mult_kernel_s8_s16(const q7_t *input_a, + const q15_t *input_b, + const uint16_t output_ch, + const int32_t *out_shift, + const int32_t *out_mult, + const int32_t out_offset, + const int16_t activation_min, + const int16_t activation_max, + const uint16_t num_col_a, + const int32_t *const output_bias, + q7_t *out_0) +{ +#if defined(RISCV_MATH_DSP) + /* set up the second output pointers */ + q7_t *out_1 = out_0 + output_ch; + const int32_t *bias = output_bias; + + uint16_t row_count = output_ch / 2; + const q7_t *ip_a0 = input_a; + /* this loop over rows in A */ + while (row_count) + { + /* setup pointers for B */ + const q15_t *ip_b0 = input_b; + const q15_t *ip_b1 = ip_b0 + num_col_a; + + /* align the second pointer for A */ + const q7_t *ip_a1 = ip_a0 + num_col_a; + + /* Init accumulator with bias for channel N and N + 1 */ + q31_t ch_0_out_0 = *bias; + q31_t ch_0_out_1 = *bias++; + q31_t ch_1_out_0 = *bias; + q31_t ch_1_out_1 = *bias++; + + uint16_t col_count = num_col_a / 4; + /* accumulate over the vector */ + while (col_count) + { + q31_t a01, a02, a11, a12; + q31_t b0 = riscv_nn_read_q15x2_ia(&ip_b0); + q31_t b1 = riscv_nn_read_q15x2_ia(&ip_b1); + + // ip_a0 = read_and_pad(ip_a0, &a01, &a02); + // ip_a1 = read_and_pad(ip_a1, &a11, &a12); + q31_t inA = riscv_nn_read_q7x4_ia(&ip_a0); + a01 = __RV_SUNPKD810(inA); + a02 = __RV_SUNPKD832(inA); + inA = riscv_nn_read_q7x4_ia(&ip_a1); + a11 = __RV_SUNPKD810(inA); + a12 = __RV_SUNPKD832(inA); + + ch_0_out_0 = __SMLAD(a01, b0, ch_0_out_0); + ch_0_out_1 = __SMLAD(a01, b1, ch_0_out_1); + ch_1_out_0 = __SMLAD(a11, b0, ch_1_out_0); + ch_1_out_1 = __SMLAD(a11, b1, ch_1_out_1); + + b0 = riscv_nn_read_q15x2_ia(&ip_b0); + b1 = riscv_nn_read_q15x2_ia(&ip_b1); + + ch_0_out_0 = __SMLAD(a02, b0, ch_0_out_0); + ch_0_out_1 = __SMLAD(a02, b1, ch_0_out_1); + ch_1_out_0 = __SMLAD(a12, b0, ch_1_out_0); + ch_1_out_1 = __SMLAD(a12, b1, ch_1_out_1); + + col_count--; + } /* while over col_count */ + col_count = num_col_a & 0x3; + while (col_count) + { + q7_t a0 = *ip_a0++; + q15_t b0 = *ip_b0++; + q7_t a1 = *ip_a1++; + q15_t b1 = *ip_b1++; + + ch_0_out_0 += a0 * b0; + ch_0_out_1 += a0 * b1; + ch_1_out_0 += a1 * b0; + ch_1_out_1 += a1 * b1; + col_count--; + } /* while over col_count */ + + ch_0_out_0 = riscv_nn_requantize(ch_0_out_0, *out_mult, *out_shift); + ch_0_out_0 += out_offset; + ch_0_out_0 = MAX(ch_0_out_0, activation_min); + ch_0_out_0 = MIN(ch_0_out_0, activation_max); + *out_0++ = (q7_t)ch_0_out_0; + + ch_0_out_1 = riscv_nn_requantize(ch_0_out_1, *out_mult, *out_shift); + ch_0_out_1 += out_offset; + ch_0_out_1 = MAX(ch_0_out_1, activation_min); + ch_0_out_1 = MIN(ch_0_out_1, activation_max); + *out_1++ = (q7_t)ch_0_out_1; + out_mult++; + out_shift++; + + ch_1_out_0 = riscv_nn_requantize(ch_1_out_0, *out_mult, *out_shift); + ch_1_out_0 += out_offset; + ch_1_out_0 = MAX(ch_1_out_0, activation_min); + ch_1_out_0 = MIN(ch_1_out_0, activation_max); + *out_0++ = (q7_t)ch_1_out_0; + + ch_1_out_1 = riscv_nn_requantize(ch_1_out_1, *out_mult, *out_shift); + ch_1_out_1 += out_offset; + ch_1_out_1 = MAX(ch_1_out_1, activation_min); + ch_1_out_1 = MIN(ch_1_out_1, activation_max); + *out_1++ = (q7_t)ch_1_out_1; + out_mult++; + out_shift++; + + /* skip row */ + ip_a0 += num_col_a; + row_count--; + } + + /* compute the last odd numbered row if any */ + if (output_ch & 0x1) + { + /* setup pointers for B */ + const q15_t *ip_b0 = input_b; + const q15_t *ip_b1 = ip_b0 + num_col_a; + + /* load the bias */ + q31_t ch_0_out_0 = *bias; + q31_t ch_0_out_1 = *bias++; + + uint16_t col_count = num_col_a >> 2; + while (col_count) + { + q31_t a01, a02; + q31_t b0 = riscv_nn_read_q15x2_ia(&ip_b0); + q31_t b1 = riscv_nn_read_q15x2_ia(&ip_b1); + + // ip_a0 = read_and_pad(ip_a0, &a01, &a02); + q31_t inA = riscv_nn_read_q7x4_ia(&ip_a0); + a01 = __RV_SUNPKD810(inA); + a02 = __RV_SUNPKD832(inA); + + ch_0_out_0 = __SMLAD(a01, b0, ch_0_out_0); + ch_0_out_1 = __SMLAD(a01, b1, ch_0_out_1); + + b0 = riscv_nn_read_q15x2_ia(&ip_b0); + b1 = riscv_nn_read_q15x2_ia(&ip_b1); + ch_0_out_0 = __SMLAD(a02, b0, ch_0_out_0); + ch_0_out_1 = __SMLAD(a02, b1, ch_0_out_1); + + col_count--; + } + col_count = num_col_a & 0x3; + while (col_count) + { + q7_t a0 = *ip_a0++; + q15_t b0 = *ip_b0++; + q15_t b1 = *ip_b1++; + + ch_0_out_0 += a0 * b0; + ch_0_out_1 += a0 * b1; + col_count--; + } + ch_0_out_0 = riscv_nn_requantize(ch_0_out_0, *out_mult, *out_shift); + ch_0_out_0 += out_offset; + ch_0_out_0 = MAX(ch_0_out_0, activation_min); + ch_0_out_0 = MIN(ch_0_out_0, activation_max); + *out_0++ = (q7_t)ch_0_out_0; + + ch_0_out_1 = riscv_nn_requantize(ch_0_out_1, *out_mult, *out_shift); + ch_0_out_1 += out_offset; + ch_0_out_1 = MAX(ch_0_out_1, activation_min); + ch_0_out_1 = MIN(ch_0_out_1, activation_max); + *out_1++ = (q7_t)ch_0_out_1; + out_mult++; + out_shift++; + } + + out_0 += output_ch; + + /* return the new output pointer with offset */ + return out_0; +#else + (void)input_a; + (void)input_b; + (void)output_ch; + (void)out_shift; + (void)out_mult; + (void)out_offset; + (void)activation_min; + (void)activation_max; + (void)num_col_a; + (void)output_bias; + (void)out_0; + /* To be completed */ + return NULL; +#endif +} diff --git a/components/nmsis/nn/src/ConvolutionFunctions/riscv_nn_mat_mult_kernel_s8_s16_reordered.c b/components/nmsis/nn/src/ConvolutionFunctions/riscv_nn_mat_mult_kernel_s8_s16_reordered.c new file mode 100644 index 00000000..ceae5364 --- /dev/null +++ b/components/nmsis/nn/src/ConvolutionFunctions/riscv_nn_mat_mult_kernel_s8_s16_reordered.c @@ -0,0 +1,202 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_nn_mat_mult_kernel_s8_s16_reordered.c + * Description: Matrix-multiplication function for convolution with reordered columns + * + * $Date: 09. October 2020 + * $Revision: V.1.0.3 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ + +#include "riscv_nnfunctions.h" +#include "riscv_nnsupportfunctions.h" + +/* + * Matrix-multiplication with re-ordered input and bias inputs for convolution with per-channel + * requantization. The re-ordering is a consequence of sign extension is done by the SXTB16 command. + * + * Refer header file for details. This function differs from riscv_nn_mat_mult_kernel_s8_s16(), in that it uses + * read_and_pad_reordered() instead of riscv_nn_mat_mult_kernel_s8_s16(). Investigating the cycles impact and + * unifying these two functions is a potential future improvement. + * + */ + +q7_t *riscv_nn_mat_mult_kernel_s8_s16_reordered(const q7_t *input_a, + const q15_t *input_b, + const uint16_t output_ch, + const int32_t *out_shift, + const int32_t *out_mult, + const int32_t out_offset, + const int16_t activation_min, + const int16_t activation_max, + const uint16_t num_col_a, + const int32_t *const output_bias, + q7_t *out_0) +{ +#if defined(RISCV_MATH_DSP) + /* set up the second output pointers */ + q7_t *out_1 = out_0 + output_ch; + const int32_t *bias = output_bias; + + uint16_t row_count = output_ch / 2; + const q7_t *ip_a0 = input_a; + /* this loop over rows in A */ + while (row_count) + { + /* setup pointers for B */ + const q15_t *ip_b0 = input_b; + const q15_t *ip_b1 = ip_b0 + num_col_a; + + /* align the second pointer for A */ + const q7_t *ip_a1 = ip_a0 + num_col_a; + + /* Init accumulator with bias for channel N and N + 1 */ + q31_t ch_0_out_0 = *bias; + q31_t ch_0_out_1 = *bias++; + q31_t ch_1_out_0 = *bias; + q31_t ch_1_out_1 = *bias++; + + uint16_t col_count = num_col_a / 4; + /* accumulate over the vector */ + while (col_count) + { + q31_t a01, a02, a11, a12; + q31_t b0 = riscv_nn_read_q15x2_ia(&ip_b0); + q31_t b1 = riscv_nn_read_q15x2_ia(&ip_b1); + + ip_a0 = read_and_pad_reordered(ip_a0, &a01, &a02); + ip_a1 = read_and_pad_reordered(ip_a1, &a11, &a12); + + ch_0_out_0 = __SMLAD(a01, b0, ch_0_out_0); + ch_0_out_1 = __SMLAD(a01, b1, ch_0_out_1); + ch_1_out_0 = __SMLAD(a11, b0, ch_1_out_0); + ch_1_out_1 = __SMLAD(a11, b1, ch_1_out_1); + + b0 = riscv_nn_read_q15x2_ia(&ip_b0); + b1 = riscv_nn_read_q15x2_ia(&ip_b1); + + ch_0_out_0 = __SMLAD(a02, b0, ch_0_out_0); + ch_0_out_1 = __SMLAD(a02, b1, ch_0_out_1); + ch_1_out_0 = __SMLAD(a12, b0, ch_1_out_0); + ch_1_out_1 = __SMLAD(a12, b1, ch_1_out_1); + + col_count--; + } /* while over col_count */ + + ch_0_out_0 = riscv_nn_requantize(ch_0_out_0, *out_mult, *out_shift); + ch_0_out_0 += out_offset; + ch_0_out_0 = MAX(ch_0_out_0, activation_min); + ch_0_out_0 = MIN(ch_0_out_0, activation_max); + *out_0++ = (q7_t)ch_0_out_0; + + ch_0_out_1 = riscv_nn_requantize(ch_0_out_1, *out_mult, *out_shift); + ch_0_out_1 += out_offset; + ch_0_out_1 = MAX(ch_0_out_1, activation_min); + ch_0_out_1 = MIN(ch_0_out_1, activation_max); + *out_1++ = (q7_t)ch_0_out_1; + out_mult++; + out_shift++; + + ch_1_out_0 = riscv_nn_requantize(ch_1_out_0, *out_mult, *out_shift); + ch_1_out_0 += out_offset; + ch_1_out_0 = MAX(ch_1_out_0, activation_min); + ch_1_out_0 = MIN(ch_1_out_0, activation_max); + *out_0++ = (q7_t)ch_1_out_0; + + ch_1_out_1 = riscv_nn_requantize(ch_1_out_1, *out_mult, *out_shift); + ch_1_out_1 += out_offset; + ch_1_out_1 = MAX(ch_1_out_1, activation_min); + ch_1_out_1 = MIN(ch_1_out_1, activation_max); + *out_1++ = (q7_t)ch_1_out_1; + out_mult++; + out_shift++; + + /* skip row */ + ip_a0 += num_col_a; + row_count--; + } + + if (output_ch & 1) + { + /* setup pointers for B */ + const q15_t *ip_b0 = input_b; + const q15_t *ip_b1 = ip_b0 + num_col_a; + + /* Init accumulator with bias for channel N + 1 */ + q31_t ch_0_out_0 = *bias; + q31_t ch_0_out_1 = ch_0_out_0; + + int32_t col_count = num_col_a / 4; + while (col_count) + { + q31_t a01, a02; + q31_t b0 = riscv_nn_read_q15x2_ia(&ip_b0); + q31_t b1 = riscv_nn_read_q15x2_ia(&ip_b1); + + ip_a0 = read_and_pad_reordered(ip_a0, &a01, &a02); + + ch_0_out_0 = __SMLAD(a01, b0, ch_0_out_0); + ch_0_out_1 = __SMLAD(a01, b1, ch_0_out_1); + + b0 = riscv_nn_read_q15x2_ia(&ip_b0); + b1 = riscv_nn_read_q15x2_ia(&ip_b1); + + ch_0_out_0 = __SMLAD(a02, b0, ch_0_out_0); + ch_0_out_1 = __SMLAD(a02, b1, ch_0_out_1); + + col_count--; + } /* while over col_count */ + + ch_0_out_0 = riscv_nn_requantize(ch_0_out_0, *out_mult, *out_shift); + ch_0_out_0 += out_offset; + ch_0_out_0 = MAX(ch_0_out_0, activation_min); + ch_0_out_0 = MIN(ch_0_out_0, activation_max); + *out_0++ = (q7_t)ch_0_out_0; + + ch_0_out_1 = riscv_nn_requantize(ch_0_out_1, *out_mult, *out_shift); + ch_0_out_1 += out_offset; + ch_0_out_1 = MAX(ch_0_out_1, activation_min); + ch_0_out_1 = MIN(ch_0_out_1, activation_max); + *out_1++ = (q7_t)ch_0_out_1; + } + + out_0 += output_ch; + + /* return the new output pointer with offset */ + return out_0; +#else + (void)input_a; + (void)input_b; + (void)output_ch; + (void)out_shift; + (void)out_mult; + (void)out_offset; + (void)activation_min; + (void)activation_max; + (void)num_col_a; + (void)output_bias; + (void)out_0; + /* To be completed */ + return NULL; +#endif +} diff --git a/components/nmsis/nn/src/ConvolutionFunctions/riscv_nn_mat_mult_s8.c b/components/nmsis/nn/src/ConvolutionFunctions/riscv_nn_mat_mult_s8.c new file mode 100644 index 00000000..09715adb --- /dev/null +++ b/components/nmsis/nn/src/ConvolutionFunctions/riscv_nn_mat_mult_s8.c @@ -0,0 +1,70 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_nn_mat_mult_s8.c + * Description: General Matrix-multiplication function + * + * $Date: 09. October 2020 + * $Revision: V.2.0.5 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ + +#include "riscv_nnsupportfunctions.h" + +/* + * s8 General matrix multiplication function with per-channel requantization for upto 4 column batches. + * + * Refer header file for details. + * + */ + +q7_t *riscv_nn_mat_mult_s8(const q7_t *input_row, + const q7_t *input_col, + const uint16_t output_ch, + const uint16_t col_batches, + const int32_t *output_shift, + const int32_t *output_mult, + const int32_t out_offset, + const int32_t col_offset, + const int32_t row_offset, + const int16_t activation_min, + const int16_t activation_max, + const uint16_t row_len, + const int32_t *const bias, + q7_t *out) +{ + (void)input_row; + (void)input_col; + (void)output_ch; + (void)col_batches; + (void)output_shift; + (void)output_mult; + (void)out_offset; + (void)col_offset; + (void)row_offset; + (void)activation_min; + (void)activation_max; + (void)row_len; + (void)bias; + (void)out; + return NULL; +} diff --git a/components/nmsis/nn/src/FullyConnectedFunctions/riscv_fully_connected_mat_q7_vec_q15.c b/components/nmsis/nn/src/FullyConnectedFunctions/riscv_fully_connected_mat_q7_vec_q15.c new file mode 100644 index 00000000..f1b3de55 --- /dev/null +++ b/components/nmsis/nn/src/FullyConnectedFunctions/riscv_fully_connected_mat_q7_vec_q15.c @@ -0,0 +1,251 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_fully_connected_mat_q7_vec_q15.c + * Description: Mixed Q15-Q7 fully-connected layer function + * + * $Date: 09. October 2020 + * $Revision: V.1.0.1 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "riscv_nnfunctions.h" +#include "riscv_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup FC + * @{ + */ + +/** + * @brief Mixed Q15-Q7 fully-connected layer function + * @param[in] pV pointer to input vector + * @param[in] pM pointer to matrix weights + * @param[in] dim_vec length of the vector + * @param[in] num_of_rows number of rows in weight matrix + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias pointer to bias + * @param[in,out] pOut pointer to output vector + * @param[in,out] vec_buffer pointer to buffer space for input + * @return The function returns RISCV_MATH_SUCCESS + * + * @details + * + * Buffer size: + * + * vec_buffer size: 0 + * + * Q7_Q15 version of the fully connected layer + * + * Weights are in q7_t and Activations are in q15_t + * + */ + +riscv_status riscv_fully_connected_mat_q7_vec_q15(const q15_t *pV, + const q7_t *pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t *bias, + q15_t *pOut, + q15_t *vec_buffer) +{ + (void)vec_buffer; +#if defined(RISCV_VECTOR) + int i, j; + uint32_t blkCnt_v; + size_t l; + vint16m4_t v_x, v_y; + vint32m8_t v_a; + vint64m1_t v_temp; + l = vsetvl_e64m1(1); + v_temp = vsub_vv_i64m1(v_temp, v_temp, l); + /* Run the following code as reference implementation for RISC-V Core without DSP */ + for (i = 0; i < num_of_rows; i++) + { + int ip_out = ((q31_t)(bias[i]) << bias_shift) + NN_ROUND(out_shift); + + blkCnt_v = dim_vec; + j = 0; + l = vsetvl_e32m8(blkCnt_v); + v_a = vsub_vv_i32m8(v_a,v_a, l); + for (; (l = vsetvl_e16m4(blkCnt_v)) > 0; blkCnt_v -= l) { + v_x = vle16_v_i16m4(pV+j, l); + v_y = vwadd_vx_i16m4(vle8_v_i8m2(pM+i * dim_vec + j, l),0, l); + v_a = vwmacc_vv_i32m8(v_a,v_x,v_y, l); + j += l; + } + l = vsetvl_e32m8(dim_vec); + ip_out += (q31_t)vmv_x_s_i64m1_i64 (vwredsum_vs_i32m8_i64m1(v_temp,v_a,v_temp, l)); + pOut[i] = (q15_t) __SSAT((ip_out >> out_shift), 16); + } +#else +#if defined (RISCV_MATH_DSP) + /* Run the following code for RISC-V Core with DSP enabled */ + + const q7_t *pB = pM; + const q7_t *pB2; + q15_t *pO = pOut; + const q7_t *pBias = bias; + const q15_t *pA = pV; + + uint16_t rowCnt = num_of_rows >> 1; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + uint16_t colCnt = dim_vec >> 2; + + pA = pV; + pB2 = pB + dim_vec; + + while (colCnt) + { + q31_t inV, inM11, inM12, inM21, inM22; + pB = read_and_pad(pB, &inM11, &inM12); + pB2 = read_and_pad(pB2, &inM21, &inM22); + + inV = riscv_nn_read_q15x2_ia(&pA); + + sum = __RV_KMADA(sum , inV, inM11); + sum2 = __RV_KMADA(sum2, inV, inM21); + + inV = riscv_nn_read_q15x2_ia(&pA); + + sum = __RV_KMADA(sum , inV, inM12); + sum2 = __RV_KMADA(sum2, inV, inM22); + + colCnt--; + } + colCnt = dim_vec & 0x3; + while (colCnt) + { + q15_t inV = *pA++; + q7_t inM = *pB++; + q7_t inM2 = *pB2++; + + sum += inV * inM; + sum2 += inV * inM2; + colCnt--; + } /* while over colCnt */ + *pO++ = (q15_t)(__SSAT((sum >> out_shift), 16)); + *pO++ = (q15_t)(__SSAT((sum2 >> out_shift), 16)); + + /*adjust the pointers and counters */ + pB += dim_vec; + rowCnt--; + } + + /* left-over part of the rows */ + rowCnt = num_of_rows & 0x1; + + while (rowCnt) + { + + pA = pV; + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + uint16_t colCnt = dim_vec >> 2; +#if __RISCV_XLEN == 64 + q63_t sum64 = 0; + while (colCnt) + { + q63_t inV1, inV2; + q31_t inM11, inM12; + pB = (q7_t *) read_and_pad((void *)pB, &inM11, &inM12); + inV2 = __RV_PKBB32(inM12,inM11); + inV1 = *__SIMD64(pA)++; + sum64 = __RV_KMADA(sum64, inV1, inV2); + + // inV2 = *__SIMD32(pA)++; + // sum = __RV_KMADA(sum, inV2, inM12); + colCnt--; + + } + sum = sum + (q31_t)(sum64 & 0xFFFFFFFF) + (q31_t)((sum64 & 0xFFFFFFFF00000000)>>32); + +#else + + while (colCnt) + { + q31_t inV1, inV2, inM11, inM12; + + pB = read_and_pad(pB, &inM11, &inM12); + + inV1 = *__SIMD32(pA)++; + sum = __RV_KMADA(sum, inV1, inM11); + + inV2 = *__SIMD32(pA)++; + sum = __RV_KMADA(sum, inV2, inM12); + /* + q31_t inB1 = *__SIMD32(pB)++; + q31_t inA1 = *__SIMD32(pA)++; + sum = __RV_SMALDA(sum, inA1, inB1); */ + + colCnt--; + } + +#endif /* __RISCV_XLEN == 64 */ + /* left-over of the vector */ + colCnt = dim_vec & 0x3; + while (colCnt) + { + q15_t inV = *pA++; + q7_t inM = *pB++; + sum += inV * inM; + colCnt--; + } + + *pO++ = (q15_t) (__SSAT(((uint64_t)sum >> out_shift), 16)); + + rowCnt--; + } + +#else + int i, j; + /* Run the following code as reference implementation for RISC-V Core without DSP */ + for (i = 0; i < num_of_rows; i++) + { + int ip_out = ((q31_t)(bias[i]) << bias_shift) + NN_ROUND(out_shift); + for (j = 0; j < dim_vec; j++) + { + ip_out += pV[j] * pM[i * dim_vec + j]; + } + pOut[i] = (q15_t)__SSAT((ip_out >> out_shift), 16); + } + +#endif /* RISCV_MATH_DSP */ +#endif + /* Return to RISCV_MATH_SUCCESS */ + return (RISCV_MATH_SUCCESS); +} + +/** + * @} end of FC group + */ diff --git a/components/nmsis/nn/src/FullyConnectedFunctions/riscv_fully_connected_mat_q7_vec_q15_opt.c b/components/nmsis/nn/src/FullyConnectedFunctions/riscv_fully_connected_mat_q7_vec_q15_opt.c new file mode 100644 index 00000000..81388a9d --- /dev/null +++ b/components/nmsis/nn/src/FullyConnectedFunctions/riscv_fully_connected_mat_q7_vec_q15_opt.c @@ -0,0 +1,452 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_fully_connected_mat_q7_vec_q15_opt.c + * Description: Mixed Q15-Q7 opt fully-connected layer function + * + * $Date: 09. October 2020 + * $Revision: V.1.0.1 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "riscv_nnfunctions.h" +#include "riscv_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup FC + * @{ + */ + + /** + * @brief Mixed Q15-Q7 opt fully-connected layer function + * @param[in] pV pointer to input vector + * @param[in] pM pointer to matrix weights + * @param[in] dim_vec length of the vector + * @param[in] num_of_rows number of rows in weight matrix + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias pointer to bias + * @param[in,out] pOut pointer to output vector + * @param[in,out] vec_buffer pointer to buffer space for input + * @return The function returns RISCV_MATH_SUCCESS + * + * @details + * + * Buffer size: + * + * vec_buffer size: 0 + * + * Q7_Q15 version of the fully connected layer + * + * Weights are in q7_t and Activations are in q15_t + * + * Limitation: x4 version requires weight reordering to work + * + * Here we use only one pointer to read 4 rows in the weight + * matrix. So if the original q7_t matrix looks like this: + * + * | a11 | a12 | a13 | a14 | a15 | a16 | a17 | + * + * | a21 | a22 | a23 | a24 | a25 | a26 | a27 | + * + * | a31 | a32 | a33 | a34 | a35 | a36 | a37 | + * + * | a41 | a42 | a43 | a44 | a45 | a46 | a47 | + * + * | a51 | a52 | a53 | a54 | a55 | a56 | a57 | + * + * | a61 | a62 | a63 | a64 | a65 | a66 | a67 | + * + * We operates on multiple-of-4 rows, so the first four rows becomes + * + * | a11 | a21 | a12 | a22 | a31 | a41 | a32 | a42 | + * + * | a13 | a23 | a14 | a24 | a33 | a43 | a34 | a44 | + * + * | a15 | a25 | a16 | a26 | a35 | a45 | a36 | a46 | + * + * The column left over will be in-order. + * which is: + * | a17 | a27 | a37 | a47 | + * + * For the left-over rows, we do 1x1 computation, so the data remains + * as its original order. + * + * So the stored weight matrix looks like this: + * + * | a11 | a21 | a12 | a22 | a31 | a41 | + * + * | a32 | a42 | a13 | a23 | a14 | a24 | + * + * | a33 | a43 | a34 | a44 | a15 | a25 | + * + * | a16 | a26 | a35 | a45 | a36 | a46 | + * + * | a17 | a27 | a37 | a47 | a51 | a52 | + * + * | a53 | a54 | a55 | a56 | a57 | a61 | + * + * | a62 | a63 | a64 | a65 | a66 | a67 | + * + */ +#define USE_INTRINSIC + +riscv_status +riscv_fully_connected_mat_q7_vec_q15_opt(const q15_t * pV, + const q7_t * pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, const q7_t * bias, q15_t * pOut, q15_t * vec_buffer) +{ + + (void)vec_buffer; +#if defined(RISCV_VECTOR) + /* Run the following code as reference implementation for RISC-V Core without DSP */ + uint16_t rowCnt = num_of_rows >> 2; + const q7_t *pB = pM; + const q15_t *pA; + q15_t *pO = pOut; + const q7_t *pBias = bias; + + int i, j; + uint32_t blkCnt_v; + size_t l; + ptrdiff_t bstridea = 4; + ptrdiff_t bstrideb = 8; + vint16m4_t v_a1, v_a2; + vint16m4_t v_b1, v_b2, v_b3, v_b4; + vint64m1_t v_temp; + l = vsetvl_e64m1(1); + v_temp = vsub_vv_i64m1(v_temp, v_temp, l); + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = dim_vec >> 1; + blkCnt_v = colCnt; + pA = pV; + for (; (l = vsetvl_e16m4(blkCnt_v)) > 0; blkCnt_v -= l) { + v_a1 = vlse16_v_i16m4(pA, bstridea, l); + v_a2 = vlse16_v_i16m4(pA+1, bstridea, l); + pA += l*2; + + v_b1 = vwadd_vx_i16m4(vlse8_v_i8m2(pB , bstrideb, l),0, l); + v_b3 = vwadd_vx_i16m4(vlse8_v_i8m2(pB+1, bstrideb, l),0, l); + v_b2 = vwadd_vx_i16m4(vlse8_v_i8m2(pB+2, bstrideb, l),0, l); + v_b4 = vwadd_vx_i16m4(vlse8_v_i8m2(pB+3, bstrideb, l),0, l); + + sum += (q31_t)vmv_x_s_i64m1_i64 (vwredsum_vs_i32m8_i64m1(v_temp,vadd_vv_i32m8(vwmul_vv_i32m8(v_a1,v_b1, l),vwmul_vv_i32m8(v_a2,v_b2, l), l),v_temp, l)); + l = vsetvl_e16m4(blkCnt_v); + sum2 += (q31_t)vmv_x_s_i64m1_i64 (vwredsum_vs_i32m8_i64m1(v_temp,vadd_vv_i32m8(vwmul_vv_i32m8(v_a1,v_b3, l),vwmul_vv_i32m8(v_a2,v_b4, l), l),v_temp, l)); + l = vsetvl_e16m4(blkCnt_v); + + v_b1 = vwadd_vx_i16m4(vlse8_v_i8m2(pB+4, bstrideb, l),0, l); + v_b3 = vwadd_vx_i16m4(vlse8_v_i8m2(pB+5, bstrideb, l),0, l); + v_b2 = vwadd_vx_i16m4(vlse8_v_i8m2(pB+6, bstrideb, l),0, l); + v_b4 = vwadd_vx_i16m4(vlse8_v_i8m2(pB+7, bstrideb, l),0, l); + + sum3 += (q31_t)vmv_x_s_i64m1_i64 (vwredsum_vs_i32m8_i64m1(v_temp,vadd_vv_i32m8(vwmul_vv_i32m8(v_a1,v_b1, l),vwmul_vv_i32m8(v_a2,v_b2, l), l),v_temp, l)); + l = vsetvl_e16m4(blkCnt_v); + sum4 += (q31_t)vmv_x_s_i64m1_i64 (vwredsum_vs_i32m8_i64m1(v_temp,vadd_vv_i32m8(vwmul_vv_i32m8(v_a1,v_b3, l),vwmul_vv_i32m8(v_a2,v_b4, l), l),v_temp, l)); + + pB += l*8; + } + colCnt = dim_vec & 0x1; + while (colCnt) + { + q15_t inA = *pA++; + q15_t inB = *pB++; + sum += inA * inB; + inB = *pB++; + sum2 += inA * inB; + inB = *pB++; + sum3 += inA * inB; + inB = *pB++; + sum4 += inA * inB; + colCnt--; + } + *pO++ = (q15_t) __SSAT((sum >> out_shift), 16); + *pO++ = (q15_t) __SSAT((sum2 >> out_shift), 16); + *pO++ = (q15_t) __SSAT((sum3 >> out_shift), 16); + *pO++ = (q15_t) __SSAT((sum4 >> out_shift), 16); + + rowCnt--; + } + rowCnt = num_of_rows & 0x3; + + while (rowCnt) + { + int ip_out = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + int j; + + pA = pV; + for (j = 0; j < dim_vec; j++) + { + q15_t inA = *pA++; + q15_t inB = *pB++; + ip_out += inA * inB; + } + *pO++ = (q15_t) __SSAT((ip_out >> out_shift), 16); + + rowCnt--; + } + + + +#else +#if defined (RISCV_MATH_DSP) + /* Run the following code for RISC-V Core with DSP enabled */ + + const q7_t *pB = pM; + q15_t *pO = pOut; + const q7_t *pBias = bias; + const q15_t *pA = pV; + + uint16_t rowCnt = num_of_rows >> 2; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = dim_vec >> 1; + + pA = pV; + + + + while (colCnt) + { + q31_t inM11, inM12, inM13, inM14; + q31_t inV; + + inV = *__SIMD32(pA)++; + inM11 = *__SIMD32(pB)++; + inM12 = __RV_SUNPKD820(__ROR(inM11, 8)); + inM11 = __RV_SUNPKD820(inM11); + sum = __RV_KMADA(sum, inM11, inV); + sum2 = __RV_KMADA(sum2, inM12, inV); + inM13 = *__SIMD32(pB)++; + inM14 = __RV_SUNPKD820(__ROR(inM13, 8)); + inM13 = __RV_SUNPKD820(inM13); + sum3 = __RV_KMADA(sum3, inM13, inV); + sum4 = __RV_KMADA(sum4, inM14, inV); + + + colCnt--; + } + + + + colCnt = dim_vec & 0x1; + while (colCnt) + { + q15_t inV = *pA++; + q7_t inM = *pB++; + q7_t inM2 = *pB++; + q7_t inM3 = *pB++; + q7_t inM4 = *pB++; + + sum += inV * inM; + sum2 += inV * inM2; + sum3 += inV * inM3; + sum4 += inV * inM4; + colCnt--; + } /* while over colCnt */ + *pO++ = (q15_t)(__SSAT((sum >> out_shift), 16)); + *pO++ = (q15_t)(__SSAT((sum2 >> out_shift), 16)); + *pO++ = (q15_t)(__SSAT((sum3 >> out_shift), 16)); + *pO++ = (q15_t)(__SSAT((sum4 >> out_shift), 16)); + + /* adjust the pointers and counters */ + rowCnt--; + } + + /* left-over part of the rows */ + rowCnt = num_of_rows & 0x3; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + pA = pV; + uint16_t colCnt = dim_vec >> 2; +#if __RISCV_XLEN == 64 + q63_t sum64 = 0; + while (colCnt) + { + q63_t inV1, inV2; + q31_t inM11, inM12; + pB = (q7_t *) read_and_pad(pB, &inM11, &inM12); + inV2 = __RV_PKBB32(inM12,inM11); + inV1 = *__SIMD64(pA)++; + sum64 = __RV_KMADA(sum64, inV1, inV2); + colCnt--; + + // inV2 = *__SIMD32(pA)++; + // sum = __RV_KMADA(sum, inV2, inM12); + + } + sum = sum + (q31_t)(sum64 & 0xFFFFFFFF) + (q31_t)((sum64 & 0xFFFFFFFF00000000)>>32); + /* left-over of the vector */ +#else + + + while (colCnt) + { + q31_t inV1, inV2, inM11, inM12; + + pB = read_and_pad(pB, &inM11, &inM12); + + inV1 = *__SIMD32(pA)++; + sum = __RV_KMADA(sum, inV1, inM11); + + inV2 = *__SIMD32(pA)++; + sum = __RV_KMADA(sum, inV2, inM12); + /* + q31_t inB1 = *__SIMD32(pB)++; + q31_t inA1 = *__SIMD32(pA)++; + sum = __RV_KMAR64(sum, inA1, inB1);*/ + colCnt--; + + } +#endif /* __RISCV_XLEN == 64 */ + + /* left-over of the vector */ + colCnt = dim_vec & 0x3; + while (colCnt) + { + q15_t inV = *pA++; + q7_t inM = *pB++; + sum += inV * inM; + colCnt--; + } + + *pO++ = (q15_t) (__SSAT(((q31_t)((uint64_t)sum) >> out_shift), 16)); + + rowCnt--; + } + +#else + /* Run the following code as reference implementation for RISC-V Core without DSP */ + uint16_t rowCnt = num_of_rows >> 2; + const q7_t *pB = pM; + const q15_t *pA; + q15_t *pO = pOut; + const q7_t *pBias = bias; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + uint16_t colCnt = dim_vec >> 1; + + pA = pV; + + while (colCnt) + { + q15_t inA1 = *pA++; + q15_t inA2 = *pA++; + + q7_t inB1 = *pB++; + q7_t inB3 = *pB++; + q7_t inB2 = *pB++; + q7_t inB4 = *pB++; + + sum += inA1 * inB1 + inA2 * inB2; + sum2 += inA1 * inB3 + inA2 * inB4; + + inB1 = *pB++; + inB3 = *pB++; + inB2 = *pB++; + inB4 = *pB++; + + sum3 += inA1 * inB1 + inA2 * inB2; + sum4 += inA1 * inB3 + inA2 * inB4; + + colCnt--; + } + + colCnt = dim_vec & 0x1; + while (colCnt) + { + q15_t inA = *pA++; + q7_t inB = *pB++; + sum += inA * inB; + inB = *pB++; + sum2 += inA * inB; + inB = *pB++; + sum3 += inA * inB; + inB = *pB++; + sum4 += inA * inB; + + colCnt--; + } + *pO++ = (q15_t)__SSAT((sum >> out_shift), 16); + *pO++ = (q15_t)__SSAT((sum2 >> out_shift), 16); + *pO++ = (q15_t)__SSAT((sum3 >> out_shift), 16); + *pO++ = (q15_t)__SSAT((sum4 >> out_shift), 16); + + rowCnt--; + } + + rowCnt = num_of_rows & 0x3; + + while (rowCnt) + { + int ip_out = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + int j; + + pA = pV; + for (j = 0; j < dim_vec; j++) + { + q15_t inA = *pA++; + q7_t inB = *pB++; + ip_out += inA * inB; + } + *pO++ = (q15_t)__SSAT((ip_out >> out_shift), 16); + + rowCnt--; + } + +#endif /* RISCV_MATH_DSP */ +#endif + /* Return to RISCV_MATH_SUCCESS */ + return (RISCV_MATH_SUCCESS); +} + +/** + * @} end of FC group + */ diff --git a/components/nmsis/nn/src/FullyConnectedFunctions/riscv_fully_connected_q15.c b/components/nmsis/nn/src/FullyConnectedFunctions/riscv_fully_connected_q15.c new file mode 100644 index 00000000..b49c5fca --- /dev/null +++ b/components/nmsis/nn/src/FullyConnectedFunctions/riscv_fully_connected_q15.c @@ -0,0 +1,251 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_fully_connected_q15.c + * Description: Q15 basic fully-connected layer function + * + * $Date: 09. October 2020 + * $Revision: V.1.0.1 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "riscv_nnfunctions.h" +#include "riscv_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup FC + * @{ + */ + +/** + * @brief Q15 opt fully-connected layer function + * @param[in] pV pointer to input vector + * @param[in] pM pointer to matrix weights + * @param[in] dim_vec length of the vector + * @param[in] num_of_rows number of rows in weight matrix + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias pointer to bias + * @param[in,out] pOut pointer to output vector + * @param[in,out] vec_buffer pointer to buffer space for input + * @return The function returns RISCV_MATH_SUCCESS + * + * + * @details + * + * Buffer size: + * + * vec_buffer size: 0 + * + */ + +riscv_status riscv_fully_connected_q15(const q15_t *pV, + const q15_t *pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, + const q15_t *bias, + q15_t *pOut, + q15_t *vec_buffer) +{ + (void)vec_buffer; +#if defined(RISCV_VECTOR) + int i, j; + uint32_t blkCnt_v; + size_t l; + vint16m4_t v_v, v_m; + vint32m8_t v_a; + vint32m1_t v_temp; + l = vsetvl_e32m1(1); + v_temp = vsub_vv_i32m1(v_temp, v_temp, l); + /* Run the following code as reference implementation for RISC-V Core without DSP */ + for (i = 0; i < num_of_rows; i++) + { + int ip_out = ((q31_t)(bias[i]) << bias_shift) + NN_ROUND(out_shift); + + blkCnt_v = dim_vec; + j = 0; + l = vsetvl_e32m8(blkCnt_v); + v_a = vsub_vv_i32m8(v_a,v_a, l); + for (; (l = vsetvl_e16m4(blkCnt_v)) > 0; blkCnt_v -= l) { + v_v = vle16_v_i16m4(pV + j, l); + v_m = vle16_v_i16m4(pM + i * dim_vec + j, l); + v_a = vwmacc_vv_i32m8(v_a,v_v,v_m, l); + j += l; + } + l = vsetvl_e32m8(dim_vec); + ip_out += vmv_x_s_i32m1_i32 (vredsum_vs_i32m8_i32m1(v_temp,v_a,v_temp, l)); + // for (j = 0; j < dim_vec; j++) + // { + // ip_out += pV[j] * pM[i * dim_vec + j]; + // } + pOut[i] = (q15_t) __SSAT((ip_out >> out_shift), 16); + } +#else +#if defined (RISCV_MATH_DSP) + /* Run the following code for RISC-V Core with DSP enabled */ + + const q15_t *pB = pM; + const q15_t *pB2 = pB + dim_vec; + q15_t *pO = pOut; + const q15_t *pA; + const q15_t *pBias = bias; + uint16_t rowCnt = num_of_rows >> 1; + + /* this loop loops over different output */ + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = dim_vec >> 2; + + pA = pV; + pB2 = pB + dim_vec; + + while (colCnt) + { + q31_t inV1, inM1, inM2; + inV1 = riscv_nn_read_q15x2_ia(&pA); + inM1 = riscv_nn_read_q15x2_ia(&pB); + sum = __SMLAD(inV1, inM1, sum); + inM2 = riscv_nn_read_q15x2_ia(&pB2); + sum2 = __SMLAD(inV1, inM2, sum2); + + inV1 = riscv_nn_read_q15x2_ia(&pA); + inM1 = riscv_nn_read_q15x2_ia(&pB); + sum = __SMLAD(inV1, inM1, sum); + inM2 = riscv_nn_read_q15x2_ia(&pB2); + sum2 = __SMLAD(inV1, inM2, sum2); + +/* q31_t inA1 = *__SIMD32(pA)++; + q31_t inB1 = *__SIMD32(pB)++; + + q31_t inB2 = *__SIMD32(pB2)++; + sum = __SMLAD(inA1, inB1, sum); + sum2 = __SMLAD(inA1, inB2, sum);*/ + colCnt--; + } + colCnt = dim_vec & 0x3; + while (colCnt) + { + q15_t inV = *pA++; + q15_t inM = *pB++; + q15_t inM2 = *pB2++; + + sum += inV * inM; + sum2 += inV * inM2; + colCnt--; + } /* while over colCnt */ + *pO++ = (q15_t)(__SSAT((sum >> out_shift), 16)); + *pO++ = (q15_t)(__SSAT((sum2 >> out_shift), 16)); + + /* adjust the pointers and counters */ + pB = pB + dim_vec; + rowCnt--; + } + + rowCnt = num_of_rows & 0x1; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + + pA = pV; + +#if __RISCV_XLEN == 64 + uint16_t colCnt = dim_vec >> 2; + q63_t sum64 = 0; + while (colCnt) { + + q63_t inB1 = *__SIMD64(pB)++; + q63_t inA1 = *__SIMD64(pA)++; + sum64 = __RV_KMADA(sum64, inA1, inB1); + colCnt--; + } + sum = sum + (q31_t)(sum64 & 0xFFFFFFFF) + (q31_t)((sum64 & 0xFFFFFFFF00000000)>>32); + /* left-over of the vector */ + colCnt = dim_vec & 0x3; +#else + uint16_t colCnt = dim_vec >> 2; + while (colCnt) { + q31_t inV1, inM1; + inV1 = *__SIMD32(pA)++; + inM1 = *__SIMD32(pB)++; + sum = __SMLAD(inV1, inM1, sum); + + inV1 = riscv_nn_read_q15x2_ia(&pA); + inM1 = riscv_nn_read_q15x2_ia(&pB); + sum = __SMLAD(inV1, inM1, sum); + + // q31_t inB1 = *__SIMD32(pB)++; + // q31_t inA1 = *__SIMD32(pA)++; + // sum = __RV_KMADA(sum, inA1, inB1); + colCnt--; + } + + /* left-over of the vector */ + colCnt = dim_vec & 0x3; +#endif /* __RISCV_XLEN == 64 */ + while(colCnt) { + q15_t inV = *pA++; + q15_t inM = *pB++; + + sum += inV * inM; + + colCnt--; + } + + *pO++ = (q15_t)(__SSAT((sum >> out_shift), 16)); + + rowCnt--; + } + +#else + int i, j; + /* Run the following code as reference implementation for RISC-V Core without DSP */ + for (i = 0; i < num_of_rows; i++) + { + int ip_out = ((q31_t)(bias[i]) << bias_shift) + NN_ROUND(out_shift); + for (j = 0; j < dim_vec; j++) + { + ip_out += pV[j] * pM[i * dim_vec + j]; + } + pOut[i] = (q15_t)__SSAT((ip_out >> out_shift), 16); + } + +#endif /* RISCV_MATH_DSP */ +#endif + /* Return to application */ + return (RISCV_MATH_SUCCESS); +} + +/** + * @} end of FC group + */ diff --git a/components/nmsis/nn/src/FullyConnectedFunctions/riscv_fully_connected_q15_opt.c b/components/nmsis/nn/src/FullyConnectedFunctions/riscv_fully_connected_q15_opt.c new file mode 100644 index 00000000..d4487654 --- /dev/null +++ b/components/nmsis/nn/src/FullyConnectedFunctions/riscv_fully_connected_q15_opt.c @@ -0,0 +1,423 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_fully_connected_q15_opt.c + * Description: Q15 opt fully-connected layer function + * + * $Date: 09. October 2020 + * $Revision: V.1.0.1 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "riscv_nnfunctions.h" +#include "riscv_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup FC + * @{ + */ + +/** + * @brief Q15 opt fully-connected layer function + * @param[in] pV pointer to input vector + * @param[in] pM pointer to matrix weights + * @param[in] dim_vec length of the vector + * @param[in] num_of_rows number of rows in weight matrix + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias pointer to bias + * @param[in,out] pOut pointer to output vector + * @param[in,out] vec_buffer pointer to buffer space for input + * @return The function returns RISCV_MATH_SUCCESS + * + * + * @details + * + * Buffer size: + * + * vec_buffer size: 0 + * + * Here we use only one pointer to read 4 rows in the weight + * matrix. So if the original matrix looks like this: + * + * | a11 | a12 | a13 | + * + * | a21 | a22 | a23 | + * + * | a31 | a32 | a33 | + * + * | a41 | a42 | a43 | + * + * | a51 | a52 | a53 | + * + * | a61 | a62 | a63 | + * + * We operates on multiple-of-4 rows, so the first four rows becomes + * + * | a11 | a12 | a21 | a22 | a31 | a32 | a41 | a42 | + * + * | a13 | a23 | a33 | a43 | + * + * Remaining rows are kept the same original order. + * + * So the stored weight matrix looks like this: + * + * + * | a11 | a12 | a21 | a22 | a31 | a32 | a41 | a42 | + * + * | a13 | a23 | a33 | a43 | a51 | a52 | a53 | a61 | + * + * | a62 | a63 | + */ + +riscv_status riscv_fully_connected_q15_opt(const q15_t *pV, + const q15_t *pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, + const q15_t *bias, + q15_t *pOut, + q15_t *vec_buffer) +{ + (void)vec_buffer; +#if defined(RISCV_VECTOR) + /* Run the following code as reference implementation for RISC-V Core without DSP */ + uint16_t rowCnt = num_of_rows >> 2; + const q15_t *pB = pM; + const q15_t *pA; + q15_t *pO = pOut; + const q15_t *pBias = bias; + + int i, j; + uint32_t blkCnt_v; + size_t l; + ptrdiff_t bstridea = 4; + ptrdiff_t bstrideb = 16; + vint16m4_t v_a1, v_a2; + vint16m4_t v_b1, v_b2; + vint64m1_t v_temp; + l = vsetvl_e64m1(1); + v_temp = vsub_vv_i64m1(v_temp, v_temp, l); + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = dim_vec >> 1; + blkCnt_v = colCnt; + pA = pV; + for (; (l = vsetvl_e16m4(blkCnt_v)) > 0; blkCnt_v -= l) { + v_a1 = vlse16_v_i16m4(pA, bstridea, l); + v_a2 = vlse16_v_i16m4(pA+1, bstridea, l); + pA += l*2; + v_b1 = vlse16_v_i16m4(pB, bstrideb, l); + v_b2 = vlse16_v_i16m4(pB+1, bstrideb, l); + sum += (q31_t)vmv_x_s_i64m1_i64 (vwredsum_vs_i32m8_i64m1(v_temp,vadd_vv_i32m8(vwmul_vv_i32m8(v_a1,v_b1, l),vwmul_vv_i32m8(v_a2,v_b2, l), l),v_temp, l)); + l = vsetvl_e16m4(blkCnt_v); + v_b1 = vlse16_v_i16m4(pB+2, bstrideb, l); + v_b2 = vlse16_v_i16m4(pB+3, bstrideb, l); + sum2 += (q31_t)vmv_x_s_i64m1_i64 (vwredsum_vs_i32m8_i64m1(v_temp,vadd_vv_i32m8(vwmul_vv_i32m8(v_a1,v_b1, l),vwmul_vv_i32m8(v_a2,v_b2, l), l),v_temp, l)); + l = vsetvl_e16m4(blkCnt_v); + v_b1 = vlse16_v_i16m4(pB+4, bstrideb, l); + v_b2 = vlse16_v_i16m4(pB+5, bstrideb, l); + sum3 += (q31_t)vmv_x_s_i64m1_i64 (vwredsum_vs_i32m8_i64m1(v_temp,vadd_vv_i32m8(vwmul_vv_i32m8(v_a1,v_b1, l),vwmul_vv_i32m8(v_a2,v_b2, l), l),v_temp, l)); + l = vsetvl_e16m4(blkCnt_v); + v_b1 = vlse16_v_i16m4(pB+6, bstrideb, l); + v_b2 = vlse16_v_i16m4(pB+7, bstrideb, l); + sum4 += (q31_t)vmv_x_s_i64m1_i64 (vwredsum_vs_i32m8_i64m1(v_temp,vadd_vv_i32m8(vwmul_vv_i32m8(v_a1,v_b1, l),vwmul_vv_i32m8(v_a2,v_b2, l), l),v_temp, l)); + + pB += l*8; + } + colCnt = dim_vec & 0x1; + while (colCnt) + { + q15_t inA = *pA++; + q15_t inB = *pB++; + sum += inA * inB; + inB = *pB++; + sum2 += inA * inB; + inB = *pB++; + sum3 += inA * inB; + inB = *pB++; + sum4 += inA * inB; + colCnt--; + } + *pO++ = (q15_t) __SSAT((sum >> out_shift), 16); + *pO++ = (q15_t) __SSAT((sum2 >> out_shift), 16); + *pO++ = (q15_t) __SSAT((sum3 >> out_shift), 16); + *pO++ = (q15_t) __SSAT((sum4 >> out_shift), 16); + + rowCnt--; + } + rowCnt = num_of_rows & 0x3; + + while (rowCnt) + { + int ip_out = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + int j; + + pA = pV; + for (j = 0; j < dim_vec; j++) + { + q15_t inA = *pA++; + q15_t inB = *pB++; + ip_out += inA * inB; + } + *pO++ = (q15_t) __SSAT((ip_out >> out_shift), 16); + + rowCnt--; + } +#else +#if defined (RISCV_MATH_DSP) + /* Run the following code for RISC-V Core with DSP enabled */ + + const q15_t *pB = pM; + q15_t *pO = pOut; + const q15_t *pBias = bias; + const q15_t *pA = pV; + + uint16_t rowCnt = num_of_rows >> 2; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = dim_vec >> 1; + + pA = pV; + + + while (colCnt) + { + q31_t inM11, inM12, inM13, inM14; + q31_t inV; + + inV = *__SIMD32(pA)++; + inM11 = *__SIMD32(pB)++; + sum = __RV_KMADA(sum , inV, inM11); + inM12 = *__SIMD32(pB)++; + sum2 = __RV_KMADA(sum2, inV, inM12); + inM13 = *__SIMD32(pB)++; + sum3 = __RV_KMADA(sum3, inV, inM13); + inM14 = *__SIMD32(pB)++; + sum4 = __RV_KMADA(sum4, inV, inM14); + colCnt--; + } + + + colCnt = dim_vec & 0x1; + while (colCnt) + { + + q15_t inV = *pA++; + q15_t inM = *pB++; + q15_t inM2 = *pB++; + q15_t inM3 = *pB++; + q15_t inM4 = *pB++; + + sum += inV * inM; + sum2 += inV * inM2; + sum3 += inV * inM3; + sum4 += inV * inM4; + colCnt--; + } /* while over colCnt */ + *pO++ = (q15_t)(__SSAT((sum >> out_shift), 16)); + *pO++ = (q15_t)(__SSAT((sum2 >> out_shift), 16)); + *pO++ = (q15_t)(__SSAT((sum3 >> out_shift), 16)); + *pO++ = (q15_t)(__SSAT((sum4 >> out_shift), 16)); + + /* adjust the pointers and counters */ + rowCnt--; + } + + /* left-over part of the rows */ + rowCnt = num_of_rows & 0x3; + + while (rowCnt) + { + + pA = pV; + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + uint16_t colCnt = dim_vec >> 2; +#if __RISCV_XLEN == 64 + // q63_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + // uint16_t colCnt = dim_vec >> 3; + q63_t sum64 = 0; + while (colCnt) + { + q63_t inV1, inV2, inM1, inM2; + + inM1 = *__SIMD64(pB)++; + inV1 = *__SIMD64(pA)++; + sum64 = __RV_KMADA(sum64, inV1, inM1); + + // inM2 = *__SIMD64(pB)++; + // inV2 = *__SIMD64(pA)++; + // sum = __RV_SMALDA(sum, inV2, inM2); + + // q31_t inB1 = *__SIMD32(pB)++; + // q31_t inA1 = *__SIMD32(pA)++; + //sum = __RV_KMAR64(sum, inB1, inA1); + colCnt--; + } + sum = sum + (q31_t)(sum64 & 0xFFFFFFFF) + (q31_t)((sum64 & 0xFFFFFFFF00000000)>>32); + + /* left-over of the vector */ + // colCnt = dim_vec & 0x7; +#else +//original should be q63_t? + + while (colCnt) + { + q31_t inV1, inV2, inM1, inM2; + + inM1 = *__SIMD32(pB)++; + inV1 = *__SIMD32(pA)++; + sum = __RV_KMADA(sum, inV1, inM1); + + inM2 = *__SIMD32(pB)++; + inV2 = *__SIMD32(pA)++; + sum = __RV_KMADA(sum, inV2, inM2); + + // q31_t inB1 = *__SIMD32(pB)++; + // q31_t inA1 = *__SIMD32(pA)++; + //sum = __RV_KMAR64(sum, inB1, inA1); + colCnt--; + } + +#endif /* __RISCV_XLEN == 64 */ + /* left-over of the vector */ + colCnt = dim_vec & 0x3; + while (colCnt) + { + q15_t inV = *pA++; + q15_t inM = *pB++; + sum += inV * inM; + colCnt--; + } + + *pO++ = (q15_t)(__SSAT((sum >> out_shift), 16)); + + rowCnt--; + } + +#else + /* Run the following code as reference implementation for RISC-V Core without DSP */ + uint16_t rowCnt = num_of_rows >> 2; + const q15_t *pB = pM; + const q15_t *pA; + q15_t *pO = pOut; + const q15_t *pBias = bias; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = dim_vec >> 1; + + pA = pV; + while (colCnt) + { + q15_t inA1 = *pA++; + q15_t inA2 = *pA++; + + q15_t inB1 = *pB++; + q15_t inB2 = *pB++; + sum += inA1 * inB1 + inA2 * inB2; + + inB1 = *pB++; + inB2 = *pB++; + sum2 += inA1 * inB1 + inA2 * inB2; + + inB1 = *pB++; + inB2 = *pB++; + sum3 += inA1 * inB1 + inA2 * inB2; + + inB1 = *pB++; + inB2 = *pB++; + sum4 += inA1 * inB1 + inA2 * inB2; + + colCnt--; + } + colCnt = dim_vec & 0x1; + while (colCnt) + { + q15_t inA = *pA++; + q15_t inB = *pB++; + sum += inA * inB; + inB = *pB++; + sum2 += inA * inB; + inB = *pB++; + sum3 += inA * inB; + inB = *pB++; + sum4 += inA * inB; + colCnt--; + } + *pO++ = (q15_t)__SSAT((sum >> out_shift), 16); + *pO++ = (q15_t)__SSAT((sum2 >> out_shift), 16); + *pO++ = (q15_t)__SSAT((sum3 >> out_shift), 16); + *pO++ = (q15_t)__SSAT((sum4 >> out_shift), 16); + + rowCnt--; + } + rowCnt = num_of_rows & 0x3; + + while (rowCnt) + { + int ip_out = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + int j; + + pA = pV; + for (j = 0; j < dim_vec; j++) + { + q15_t inA = *pA++; + q15_t inB = *pB++; + ip_out += inA * inB; + } + *pO++ = (q15_t)__SSAT((ip_out >> out_shift), 16); + + rowCnt--; + } + +#endif /* RISCV_MATH_DSP */ +#endif + /* Return to RISCV_MATH_SUCCESS */ + return (RISCV_MATH_SUCCESS); +} +/** + * @} end of FC group + */ diff --git a/components/nmsis/nn/src/FullyConnectedFunctions/riscv_fully_connected_q7.c b/components/nmsis/nn/src/FullyConnectedFunctions/riscv_fully_connected_q7.c new file mode 100644 index 00000000..3b47dedf --- /dev/null +++ b/components/nmsis/nn/src/FullyConnectedFunctions/riscv_fully_connected_q7.c @@ -0,0 +1,321 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_fully_connected_q7.c + * Description: Q7 basic fully-connected layer function + * + * $Date: January 26, 2021 + * $Revision: V.1.0.2 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "riscv_nnfunctions.h" +#include "riscv_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup FC + * @{ + */ + +/** + * @brief Q7 basic fully-connected layer function + * @param[in] pV pointer to input vector + * @param[in] pM pointer to matrix weights + * @param[in] dim_vec length of the vector + * @param[in] num_of_rows number of rows in weight matrix + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias pointer to bias + * @param[in,out] pOut pointer to output vector + * @param[in,out] vec_buffer pointer to buffer space for input + * @return The function returns RISCV_MATH_SUCCESS + * + * @details + * + * Buffer size: + * + * vec_buffer size: dim_vec + * + * This basic function is designed to work with regular weight + * matrix without interleaving. + * + */ + +riscv_status riscv_fully_connected_q7(const q7_t *pV, + const q7_t *pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t *bias, + q7_t *pOut, + q15_t *vec_buffer) +{ + +#if defined (RISCV_MATH_DSP) || defined (RISCV_VECTOR) + /* Run the following code for RISC-V Core with DSP enabled */ + + const q7_t *pB = pM; + const q7_t *pB2; + q7_t *pO = pOut; + const q7_t *pBias = bias; + q7_t *pA; + uint16_t rowCnt = num_of_rows >> 1; + + /* expand the vector into the buffer */ + riscv_q7_to_q7_reordered_no_shift(pV, (q7_t *)vec_buffer, dim_vec); + + while (rowCnt) + { + pA = (q7_t *)vec_buffer; + pB2 = pB + dim_vec; +#if defined (RISCV_VECTOR) + /* accumulate over the vector */ + size_t l; + uint32_t blkCnt = dim_vec; + q31_t sum,sum2; + // q7_t temp[] = {0}; + l = vsetvl_e8m1(blkCnt); + vint8m1_t va1m1,vb1m1,vb2m1; + vint16m2_t vch00m2,vch01m2; + vint64m1_t vch00m1,vch01m1; + vint64m1_t vtemp00m1,vtemp01m1; + vint32m4_t vch00m4,vch01m4; + //initial array and temp sum to zero + vch00m4 = vmv_v_x_i32m4(0, l); + vch01m4 = vmv_v_x_i32m4(0, l); + vch00m1 = vmv_v_x_i64m1(0, l); + vch01m1 = vmv_v_x_i64m1(0, l); + vtemp00m1 = vmv_v_x_i64m1(0, l); + vtemp01m1 = vmv_v_x_i64m1(0, l); + for (; (l = vsetvl_e8m1(blkCnt)) > 0; blkCnt -= l) { + va1m1 = vle8_v_i8m1(pA , l); + vb1m1 = vle8_v_i8m1(pB , l); + vb2m1 = vle8_v_i8m1(pB2, l); + pA += l; + pB += l; + pB2 += l; + vch00m2= vwmul_vv_i16m2(va1m1, vb1m1, l); + vch01m2= vwmul_vv_i16m2(va1m1, vb2m1, l); + vch00m4 = vwadd_wv_i32m4(vch00m4, vch00m2, l); + vch01m4 = vwadd_wv_i32m4(vch01m4, vch01m2, l); + } + //set vl to max vl + l = vsetvl_e8m1(dim_vec); + //calculate sum + vch00m1 = vwredsum_vs_i32m4_i64m1(vtemp00m1, vch00m4, vtemp00m1, l); + vch01m1 = vwredsum_vs_i32m4_i64m1(vtemp01m1, vch01m4, vtemp01m1, l); + //set vl to 1 + l = vsetvl_e32m1(1); + vch00m1 = vmin_vx_i64m1(vmax_vx_i64m1(vch00m1, 0xffffffff80000000ULL, l), 0x000000007fffffffULL, l); + vch01m1 = vmin_vx_i64m1(vmax_vx_i64m1(vch01m1, 0xffffffff80000000ULL, l), 0x000000007fffffffULL, l); + //Here we calculate sum of four vector + //write result scalar back + sum = (q31_t)vmv_x_s_i64m1_i64(vch00m1); + sum2 = (q31_t)vmv_x_s_i64m1_i64(vch01m1); + /* init the sum with bias */ + sum += ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + sum2 += ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); +#else + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); +#if __RISCV_XLEN == 64 + uint16_t colCnt = dim_vec >> 3; + q63_t sum64 = 0; + q63_t sum642 = 0; + while (colCnt) + { + q63_t inB1 = *__SIMD64(pB)++; + q63_t inB2 = *__SIMD64(pB2)++; + q63_t inA1 = *__SIMD64(pA)++; + + sum64 = __RV_SMAQA(sum64 , inA1, inB1); + sum642 = __RV_SMAQA(sum642, inA1, inB2); + + colCnt--; + } + sum = sum + (q31_t)(sum64 & 0xFFFFFFFF) + (q31_t)((sum64 & 0xFFFFFFFF00000000)>>32); + sum2 = sum2 + (q31_t)(sum642 & 0xFFFFFFFF) + (q31_t)((sum642 & 0xFFFFFFFF00000000)>>32); + colCnt = dim_vec & 0x7; +#else + uint16_t colCnt = dim_vec >> 2; + while (colCnt) + { + /* + q31_t inV, inM11, inM12, inM21, inM22; + pB = read_and_pad_reordered(pB, &inM11, &inM12); + pB2 = read_and_pad_reordered(pB2, &inM21, &inM22); + + inV = riscv_nn_read_q15x2_ia(&pA); + + sum = __SMLAD(inV, inM11, sum); + sum2 = __SMLAD(inV, inM21, sum2); + + inV = riscv_nn_read_q15x2_ia(&pA); + + sum = __SMLAD(inV, inM12, sum); + sum2 = __SMLAD(inV, inM22, sum2); + */ + q31_t inB1 = *__SIMD32(pB)++; + q31_t inB2 = *__SIMD32(pB2)++; + + q31_t inA1 = *__SIMD32(pA)++; + + sum = __RV_SMAQA(sum , inA1, inB1); + sum2 = __RV_SMAQA(sum2, inA1, inB2); + + colCnt--; + } + colCnt = dim_vec & 0x3; +#endif /* __RISCV_XLEN == 64 */ + while (colCnt) + { + q7_t inV = *pA++; + q15_t inM = *pB++; + q15_t inM2 = *pB2++; + + sum += inV * inM; + sum2 += inV * inM2; + colCnt--; + } /* while over colCnt */ +#endif /* defined (RISCV_VECTOR) */ + *pO++ = (q7_t) (__SSAT((sum >> out_shift), 8)); + *pO++ = (q7_t) (__SSAT((sum2 >> out_shift), 8)); + + /* adjust the pointers and counters */ + pB += dim_vec; + rowCnt--; + } + + /* left-over part of the rows */ + rowCnt = num_of_rows & 0x1; + + while (rowCnt) + { + uint16_t colCnt = dim_vec >> 2; + + pA = (q7_t *)vec_buffer; +#if defined (RISCV_VECTOR) + /* accumulate over the vector */ + size_t l; + uint32_t blkCnt = dim_vec; + q31_t sum; + // q7_t temp[] = {0}; + l = vsetvl_e8m1(blkCnt); + vint8m1_t va1m1,vb1m1; + vint16m2_t vch00m2; + vint64m1_t vch00m1; + vint64m1_t vtemp00m1; + vint32m4_t vch00m4; + //initial array and temp sum to zero + vch00m4 = vmv_v_x_i32m4(0, l); + vch00m1 = vmv_v_x_i64m1(0, l); + vtemp00m1 = vmv_v_x_i64m1(0, l); + for (; (l = vsetvl_e8m1(blkCnt)) > 0; blkCnt -= l) { + va1m1 = vle8_v_i8m1(pA , l); + vb1m1 = vle8_v_i8m1(pB , l); + pA += l; + pB += l; + pB2 += l; + vch00m2= vwmul_vv_i16m2(va1m1, vb1m1, l); + vch00m4 = vwadd_wv_i32m4(vch00m4, vch00m2, l); + } + //set vl to max vl + l = vsetvl_e8m1(dim_vec); + //calculate sum + vch00m1 = vwredsum_vs_i32m4_i64m1(vtemp00m1, vch00m4, vtemp00m1, l); + //set vl to 1 + l = vsetvl_e32m1(1); + vch00m1 = vmin_vx_i64m1(vmax_vx_i64m1(vch00m1, 0xffffffff80000000ULL, l), 0x000000007fffffffULL, l); + //Here we calculate sum of four vector + //write result scalar back + sum = (q31_t)vmv_x_s_i64m1_i64(vch00m1); + /* init the sum with bias */ + sum += ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); +#else + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + while (colCnt) + { + /* + q31_t inV1, inV2, inM11, inM12; + + pB = read_and_pad_reordered(pB, &inM11, &inM12); + + inV1 = riscv_nn_read_q15x2_ia(&pA); + sum = __SMLAD(inV1, inM11, sum); + + inV2 = riscv_nn_read_q15x2_ia(&pA); + sum = __SMLAD(inV2, inM12, sum); + */ + + q31_t inB1 = *__SIMD32(pB)++; + q31_t inA1 = *__SIMD32(pA)++; + sum = __RV_SMAQA(sum, inA1, inB1); + + colCnt--; + } + + /* left-over of the vector */ + colCnt = dim_vec & 0x3; + while (colCnt) + { + q7_t inV = *pA++; + q15_t inM = *pB++; + sum += inV * inM; + colCnt--; + } +#endif /* defined (RISCV_VECTOR) */ + *pO++ = (q7_t) (__SSAT((sum >> out_shift), 8)); + + rowCnt--; + } + +#else + (void)vec_buffer; + int i, j; + + /* Run the following code as reference implementation for RISC-V Core without DSP */ + for (i = 0; i < num_of_rows; i++) + { + int ip_out = ((q31_t)(bias[i]) << bias_shift) + NN_ROUND(out_shift); + for (j = 0; j < dim_vec; j++) + { + ip_out += pV[j] * pM[i * dim_vec + j]; + } + pOut[i] = (q7_t)__SSAT((ip_out >> out_shift), 8); + } + +#endif /* RISCV_MATH_DSP */ + + /* Return to RISCV_MATH_SUCCESS */ + return (RISCV_MATH_SUCCESS); +} + +/** + * @} end of FC group + */ diff --git a/components/nmsis/nn/src/FullyConnectedFunctions/riscv_fully_connected_q7_opt.c b/components/nmsis/nn/src/FullyConnectedFunctions/riscv_fully_connected_q7_opt.c new file mode 100644 index 00000000..f5f059bc --- /dev/null +++ b/components/nmsis/nn/src/FullyConnectedFunctions/riscv_fully_connected_q7_opt.c @@ -0,0 +1,444 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_fully_connected_q7_opt.c + * Description: Q7 basic fully-connected layer function + * + * $Date: 09. October 2020 + * $Revision: V.1.0.1 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "riscv_nnfunctions.h" +#include "riscv_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup FC + * @{ + */ + +/** + * @brief Q7 opt fully-connected layer function + * @param[in] pV pointer to input vector + * @param[in] pM pointer to matrix weights + * @param[in] dim_vec length of the vector + * @param[in] num_of_rows number of rows in weight matrix + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias pointer to bias + * @param[in,out] pOut pointer to output vector + * @param[in,out] vec_buffer pointer to buffer space for input + * @return The function returns RISCV_MATH_SUCCESS + * + * @details + * + * Buffer size: + * + * vec_buffer size: dim_vec + * + * This opt function is designed to work with interleaved weight + * matrix. The vector input is assumed in q7_t format, we call + * riscv_q7_to_q15_no_shift_shuffle function to expand into + * q15_t format with certain weight re-ordering, refer to the function + * comments for more details. + * Here we use only one pointer to read 4 rows in the weight + * matrix. So if the original q7_t matrix looks like this: + * + * | a11 | a12 | a13 | a14 | a15 | a16 | a17 | + * + * | a21 | a22 | a23 | a24 | a25 | a26 | a27 | + * + * | a31 | a32 | a33 | a34 | a35 | a36 | a37 | + * + * | a41 | a42 | a43 | a44 | a45 | a46 | a47 | + * + * | a51 | a52 | a53 | a54 | a55 | a56 | a57 | + * + * | a61 | a62 | a63 | a64 | a65 | a66 | a67 | + * + * + * We operates on multiple-of-4 rows, so the first four rows becomes + * + * | a11 | a21 | a13 | a23 | a31 | a41 | a33 | a43 | + * + * | a12 | a22 | a14 | a24 | a32 | a42 | a34 | a44 | + * + * | a15 | a25 | a35 | a45 | a16 | a26 | a36 | a46 | + * + * So within the kernel, we first read the re-ordered vector in as: + * + * | b1 | b3 | and | b2 | b4 | + * + * the four q31_t weights will look like + * + * | a11 | a13 |, | a21 | a23 |, | a31 | a33 |, | a41 | a43 | + * + * | a12 | a14 |, | a22 | a24 |, | a32 | a34 |, | a42 | a44 | + * + * The column left over will be in-order. + * which is: + * + * | a17 | a27 | a37 | a47 | + * + * For the left-over rows, we do 1x1 computation, so the data remains + * as its original order. + * + * So the stored weight matrix looks like this: + * + * | a11 | a21 | a13 | a23 | a31 | a41 | + * + * | a33 | a43 | a12 | a22 | a14 | a24 | + * + * | a32 | a42 | a34 | a44 | a15 | a25 | + * + * | a35 | a45 | a16 | a26 | a36 | a46 | + * + * | a17 | a27 | a37 | a47 | a51 | a52 | + * + * | a53 | a54 | a55 | a56 | a57 | a61 | + * + * | a62 | a63 | a64 | a65 | a66 | a67 | + * + * + */ + +riscv_status riscv_fully_connected_q7_opt(const q7_t *pV, + const q7_t *pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t *bias, + q7_t *pOut, + q15_t *vec_buffer) +{ + +#if defined(RISCV_MATH_DSP) + /* Run the following code for RISC-V Core with DSP enabled */ + + const q7_t *pB = pM; + q7_t *pO = pOut; + const q7_t *pBias = bias; + q7_t *pA; + uint16_t rowCnt = num_of_rows >> 2; + //q7_t *vec_buffer_q7 = (q7_t *)vec_buffer; + + riscv_q7_to_q7_reordered_no_shift(pV, (q7_t *)vec_buffer, dim_vec); + + while (rowCnt) + { + + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = dim_vec >> 2; + + pA = (q7_t *)vec_buffer; + while (colCnt) + { + + q31_t inA1 = *__SIMD32(pA)++; + q31_t inB1 = *__SIMD32(pB)++; + q31_t inB2 = *__SIMD32(pB)++; + q31_t inB3 = *__SIMD32(pB)++; + q31_t inB4 = *__SIMD32(pB)++; + + q31_t sumb1 = inB1 & 0x000000ff | (inB3 & 0x000000ff) << 8 | + inB1 & 0x00ff0000 | (inB3 & 0x00ff0000) << 8 ; + + q31_t sumb2 = (inB1 & 0x0000ff00) >> 8 | (inB3 & 0x0000ff00) | + ((inB1 & 0xff000000) >> 8) & 0x00ff0000 | (inB3 & 0xff000000) ; + + q31_t sumb3 = inB2 & 0x000000ff | (inB4 & 0x000000ff) << 8 | + inB2 & 0x00ff0000 | (inB4 & 0x00ff0000) << 8 ; + + q31_t sumb4 = (inB2 & 0x0000ff00) >> 8 | (inB4 & 0x0000ff00) | + ((inB2 & 0xff000000) >> 8) & 0x00ff0000 | (inB4 & 0xff000000) ; + + sum = __RV_SMAQA(sum , inA1, sumb1); + sum2 = __RV_SMAQA(sum2, inA1, sumb2); + sum3 = __RV_SMAQA(sum3, inA1, sumb3); + sum4 = __RV_SMAQA(sum4, inA1, sumb4); + + colCnt--; + } + + colCnt = dim_vec & 0x3; + + while (colCnt) + { + q7_t inV = *pA++; + q7_t inM = *pB++; + q7_t inM2 = *pB++; + q7_t inM3 = *pB++; + q7_t inM4 = *pB++; + + sum += inV * inM; + sum2 += inV * inM2; + sum3 += inV * inM3; + sum4 += inV * inM4; + colCnt--; + } /* while over colCnt */ + *pO++ = (q7_t)(__SSAT((sum >> out_shift), 8)); + *pO++ = (q7_t)(__SSAT((sum2 >> out_shift), 8)); + *pO++ = (q7_t)(__SSAT((sum3 >> out_shift), 8)); + *pO++ = (q7_t)(__SSAT((sum4 >> out_shift), 8)); + + /* adjust the pointers and counters */ + rowCnt--; + } + + /* left-over part of the rows */ + rowCnt = num_of_rows & 0x3; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + pA = (q7_t *)vec_buffer; +#if __RISCV_XLEN == 64 + uint16_t colCnt = dim_vec >> 3; + q63_t sum64 = 0; + while (colCnt) + { + + q63_t inA1 = *__SIMD64(pA)++; + q63_t inB1 = *__SIMD64(pB)++; + + sum64 = __RV_SMAQA(sum64, inA1, inB1); + + colCnt--; + } + sum = sum + (q31_t)(sum64 & 0xFFFFFFFF) + (q31_t)((sum64 & 0xFFFFFFFF00000000)>>32); + /* left-over of the vector */ + colCnt = dim_vec & 0x7; + +#else + uint16_t colCnt = dim_vec >> 2; + while (colCnt) + { + + q31_t inA1 = *__SIMD32(pA)++; + q31_t inB1 = *__SIMD32(pB)++; + + sum = __RV_SMAQA(sum, inA1, inB1); + + colCnt--; + } + + /* left-over of the vector */ + colCnt = dim_vec & 0x3; +#endif /* __RISCV_XLEN == 64 */ + + while (colCnt) + { + q15_t inV = *pA++; + q7_t inM = *pB++; + sum += inV * inM; + colCnt--; + } + + *pO++ = (q7_t)(__SSAT((sum >> out_shift), 8)); + + rowCnt--; + } + +#else + /* Run the following code as reference implementation for RISC-V Core without DSP */ + uint16_t rowCnt = num_of_rows >> 2; + const q7_t *pB = pM; + const q7_t *pA; + q7_t *pO = pOut; + const q7_t *pBias = bias; + +#if defined(RISCV_VECTOR) + size_t l; + uint32_t blkCnt; + ptrdiff_t bstridea; + ptrdiff_t bstrideb; + vint8m2_t v_a1,v_a2,v_a3,v_a4; + vint8m2_t v_b1,v_b2,v_b3,v_b4; + vint32m1_t vtemp; + l = vsetvl_e32m1(1); + vtemp = vsub_vv_i32m1(vtemp,vtemp, l); +#endif + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = dim_vec >> 2; + + pA = pV; +#if defined(RISCV_VECTOR) + bstridea = 4; + bstrideb = 16; + blkCnt = colCnt; + for (; (l = vsetvl_e8m2(blkCnt)) > 0; blkCnt -= l) { + v_a1 = vlse8_v_i8m2(pA++,bstridea, l); + v_a3 = vlse8_v_i8m2(pA++,bstridea, l); + v_a2 = vlse8_v_i8m2(pA++,bstridea, l); + v_a4 = vlse8_v_i8m2(pA++,bstridea, l); + v_b1 = vlse8_v_i8m2(pB++,bstrideb, l); + v_b3 = vlse8_v_i8m2(pB++,bstrideb, l); + v_b2 = vlse8_v_i8m2(pB++,bstrideb, l); + v_b4 = vlse8_v_i8m2(pB++,bstrideb, l); + + l = vsetvl_e8m2(blkCnt); + sum += vmv_x_s_i32m1_i32(vredsum_vs_i32m8_i32m1(vtemp, vwadd_vv_i32m8(vwmul_vv_i16m4(v_a1, v_b1, l),vwmul_vv_i16m4(v_a2, v_b2, l), l), vtemp, l)); + l = vsetvl_e8m2(blkCnt); + sum2 += vmv_x_s_i32m1_i32(vredsum_vs_i32m8_i32m1(vtemp, vwadd_vv_i32m8(vwmul_vv_i16m4(v_a1, v_b3, l),vwmul_vv_i16m4(v_a2, v_b4, l), l), vtemp, l)); + l = vsetvl_e8m2(blkCnt); + v_b1 = vlse8_v_i8m2(pB++,bstrideb, l); + v_b3 = vlse8_v_i8m2(pB++,bstrideb, l); + v_b2 = vlse8_v_i8m2(pB++,bstrideb, l); + v_b4 = vlse8_v_i8m2(pB++,bstrideb, l); + l = vsetvl_e8m2(blkCnt); + sum3 += vmv_x_s_i32m1_i32(vredsum_vs_i32m8_i32m1(vtemp, vwadd_vv_i32m8(vwmul_vv_i16m4(v_a1, v_b1, l),vwmul_vv_i16m4(v_a2, v_b2, l), l), vtemp, l)); + l = vsetvl_e8m2(blkCnt); + sum4 += vmv_x_s_i32m1_i32(vredsum_vs_i32m8_i32m1(vtemp, vwadd_vv_i32m8(vwmul_vv_i16m4(v_a1, v_b3, l),vwmul_vv_i16m4(v_a2, v_b4, l), l), vtemp, l)); + l = vsetvl_e8m2(blkCnt); + v_b1 = vlse8_v_i8m2(pB++,bstrideb, l); + v_b3 = vlse8_v_i8m2(pB++,bstrideb, l); + v_b2 = vlse8_v_i8m2(pB++,bstrideb, l); + v_b4 = vlse8_v_i8m2(pB++,bstrideb, l); + l = vsetvl_e8m2(blkCnt); + sum += vmv_x_s_i32m1_i32(vredsum_vs_i32m8_i32m1(vtemp, vwadd_vv_i32m8(vwmul_vv_i16m4(v_a3, v_b1, l),vwmul_vv_i16m4(v_a4, v_b2, l), l), vtemp, l)); + l = vsetvl_e8m2(blkCnt); + sum2 += vmv_x_s_i32m1_i32(vredsum_vs_i32m8_i32m1(vtemp, vwadd_vv_i32m8(vwmul_vv_i16m4(v_a3, v_b3, l),vwmul_vv_i16m4(v_a4, v_b4, l), l), vtemp, l)); + l = vsetvl_e8m2(blkCnt); + v_b1 = vlse8_v_i8m2(pB++,bstrideb, l); + v_b3 = vlse8_v_i8m2(pB++,bstrideb, l); + v_b2 = vlse8_v_i8m2(pB++,bstrideb, l); + v_b4 = vlse8_v_i8m2(pB++,bstrideb, l); + l = vsetvl_e8m2(blkCnt); + sum3 += vmv_x_s_i32m1_i32(vredsum_vs_i32m8_i32m1(vtemp, vwadd_vv_i32m8(vwmul_vv_i16m4(v_a3, v_b1, l),vwmul_vv_i16m4(v_a4, v_b2, l), l), vtemp, l)); + l = vsetvl_e8m2(blkCnt); + sum4 += vmv_x_s_i32m1_i32(vredsum_vs_i32m8_i32m1(vtemp, vwadd_vv_i32m8(vwmul_vv_i16m4(v_a3, v_b3, l),vwmul_vv_i16m4(v_a4, v_b4, l), l), vtemp, l)); + pA += (l-1)*bstridea; + pB += (l-1)*bstrideb; + } +#else + while (colCnt) + { + q7_t inA1 = *pA++; + q7_t inA3 = *pA++; + q7_t inA2 = *pA++; + q7_t inA4 = *pA++; + + q7_t inB1 = *pB++; + q7_t inB3 = *pB++; + q7_t inB2 = *pB++; + q7_t inB4 = *pB++; + + sum += inA1 * inB1 + inA2 * inB2; + sum2 += inA1 * inB3 + inA2 * inB4; + + inB1 = *pB++; + inB3 = *pB++; + inB2 = *pB++; + inB4 = *pB++; + + sum3 += inA1 * inB1 + inA2 * inB2; + sum4 += inA1 * inB3 + inA2 * inB4; + + inB1 = *pB++; + inB3 = *pB++; + inB2 = *pB++; + inB4 = *pB++; + + sum += inA3 * inB1 + inA4 * inB2; + sum2 += inA3 * inB3 + inA4 * inB4; + + inB1 = *pB++; + inB3 = *pB++; + inB2 = *pB++; + inB4 = *pB++; + + sum3 += inA3 * inB1 + inA4 * inB2; + sum4 += inA3 * inB3 + inA4 * inB4; + + colCnt--; + } +#endif + colCnt = dim_vec & 0x3; + while (colCnt) + { + q7_t inA = *pA++; + q7_t inB = *pB++; + sum += inA * inB; + inB = *pB++; + sum2 += inA * inB; + inB = *pB++; + sum3 += inA * inB; + inB = *pB++; + sum4 += inA * inB; + + colCnt--; + } + *pO++ = (q7_t)__SSAT((sum >> out_shift), 8); + *pO++ = (q7_t)__SSAT((sum2 >> out_shift), 8); + *pO++ = (q7_t)__SSAT((sum3 >> out_shift), 8); + *pO++ = (q7_t)__SSAT((sum4 >> out_shift), 8); + + rowCnt--; + } + + rowCnt = num_of_rows & 0x3; + + while (rowCnt) + { + int ip_out = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + int j; + + pA = pV; + for (j = 0; j < dim_vec; j++) + { + q7_t inA = *pA++; + q7_t inB = *pB++; + ip_out += inA * inB; + } + *pO++ = (q7_t)__SSAT((ip_out >> out_shift), 8); + + rowCnt--; + } + +#endif /* RISCV_MATH_DSP */ + + /* Return to RISCV_MATH_SUCCESS */ + return (RISCV_MATH_SUCCESS); +} + +/** + * @} end of FC group + */ diff --git a/components/nmsis/nn/src/FullyConnectedFunctions/riscv_fully_connected_s8.c b/components/nmsis/nn/src/FullyConnectedFunctions/riscv_fully_connected_s8.c new file mode 100644 index 00000000..1751216f --- /dev/null +++ b/components/nmsis/nn/src/FullyConnectedFunctions/riscv_fully_connected_s8.c @@ -0,0 +1,99 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_fully_connected_s8 + * Description: Fully connected function compatible with TF Lite. + * + * $Date: 19. March 2021 + * $Revision: V.3.0.0 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "riscv_nnfunctions.h" +#include "riscv_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup FC + * @{ + */ + +/* + * S8 basic fully-connected and matrix multiplication layer function for TensorFlow Lite + * + * Refer header file for details. + * + */ + +riscv_status riscv_fully_connected_s8(const nmsis_nn_context *ctx, + const nmsis_nn_fc_params *fc_params, + const nmsis_nn_per_tensor_quant_params *quant_params, + const nmsis_nn_dims *input_dims, + const q7_t *input, + const nmsis_nn_dims *filter_dims, + const q7_t *kernel, + const nmsis_nn_dims *bias_dims, + const int32_t *bias, + const nmsis_nn_dims *output_dims, + q7_t *output) +{ + (void)bias_dims; + (void)ctx; + (void)fc_params->filter_offset; + + int32_t batch_cnt = input_dims->n; + + while (batch_cnt) + { + riscv_nn_vec_mat_mult_t_s8(input, + kernel, + bias, + output, + fc_params->input_offset, + 0, + fc_params->output_offset, + quant_params->multiplier, + quant_params->shift, + filter_dims->n, /* col_dim or accum_depth */ + output_dims->c, /* row_dim or output_depth */ + fc_params->activation.min, + fc_params->activation.max); + input += filter_dims->n; + output += output_dims->c; + batch_cnt--; + } + return (RISCV_MATH_SUCCESS); +} + +int32_t riscv_fully_connected_s8_get_buffer_size(const nmsis_nn_dims *filter_dims) +{ + (void)filter_dims; + return 0; +} + +/** + * @} end of FC group + */ diff --git a/components/nmsis/nn/src/NNSupportFunctions/riscv_nn_accumulate_q7_to_q15.c b/components/nmsis/nn/src/NNSupportFunctions/riscv_nn_accumulate_q7_to_q15.c new file mode 100644 index 00000000..69377ea8 --- /dev/null +++ b/components/nmsis/nn/src/NNSupportFunctions/riscv_nn_accumulate_q7_to_q15.c @@ -0,0 +1,93 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_nn_accumulate_q7_to_q15.c + * Description: Accumulate q7 vector into q15 one. + * + * $Date: 09. October 2020 + * $Revision: V.1.0.2 + * + * pSrc Processor: RISC-V CPUs + * + * -------------------------------------------------------------------- */ + +#include "riscv_nnfunctions.h" +#include "riscv_nnsupportfunctions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup NNBasicMath + * @{ + */ + +void riscv_nn_accumulate_q7_to_q15(q15_t *pDst, const q7_t *pSrc, uint32_t length) +{ + q15_t *pCnt = pDst; + const q7_t *pV = pSrc; +#if defined (RISCV_VECTOR) + uint32_t blkCnt = length; /* Loop counter */ + size_t l; + vint8m4_t pA_v8m4; + vint16m8_t pCnt_v16m8; + + for (; (l = vsetvl_e8m4(blkCnt)) > 0; blkCnt -= l) { + pA_v8m4 = vle8_v_i8m4(pV, l); + pCnt_v16m8 = vle16_v_i16m8(pCnt, l); + pV += l; + vse16_v_i16m8 (pCnt, vsadd_vv_i16m8(pCnt_v16m8,vwadd_vx_i16m8(pA_v8m4,0, l), l), l); + pCnt += l; + } +#else + q31_t v1, v2, vo1, vo2; + int32_t cnt = length >> 2; + q31_t in; + + while (cnt > 0l) + { + q31_t value = riscv_nn_read_q7x4_ia(&pV); + v1 = __SXTB16(__ROR((uint32_t)value, 8)); + v2 = __SXTB16(value); + vo2 = (q31_t)__PKHTB(v1, v2, 16); + vo1 = (q31_t)__PKHBT(v2, v1, 16); + + in = riscv_nn_read_q15x2(pCnt); + riscv_nn_write_q15x2_ia(&pCnt, __QADD16(vo1, in)); + + in = riscv_nn_read_q15x2(pCnt); + riscv_nn_write_q15x2_ia(&pCnt, __QADD16(vo2, in)); + + cnt--; + } + cnt = length & 0x3; + while (cnt > 0l) + { + *pCnt++ += *pV++; + cnt--; + } +#endif /*defined (RISCV_VECTOR)*/ +} + +/** + * @} end of NNBasicMath group + */ diff --git a/components/nmsis/nn/src/NNSupportFunctions/riscv_nn_accumulate_q7_to_q7.c b/components/nmsis/nn/src/NNSupportFunctions/riscv_nn_accumulate_q7_to_q7.c new file mode 100644 index 00000000..847ddc77 --- /dev/null +++ b/components/nmsis/nn/src/NNSupportFunctions/riscv_nn_accumulate_q7_to_q7.c @@ -0,0 +1,81 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_nn_accumulate_q7_to_q7.c + * Description: Accumulate q7 vector into q7 one. + * + * $Date: May 29, 2020 + * $Revision: V.1.0.1 + * + * pSrc Processor: RISC-V CPUs + * + * -------------------------------------------------------------------- */ +#include "riscv_nnsupportfunctions.h" +#include "riscv_nnfunctions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup NNBasicMath + * @{ + */ + +void riscv_nn_accumulate_q7_to_q7(q7_t *pDst, const q7_t *pSrc, uint32_t length) +{ + q7_t *pCnt = pDst; + const q7_t *pV = pSrc; +#if defined(RISCV_VECTOR) + uint32_t blkCnt = length; /* Loop counter */ + size_t l; + vint8m8_t valuea,valueb; + + for (; (l = vsetvl_e8m8(blkCnt)) > 0; blkCnt -= l) { + valuea = vle8_v_i8m8(pV, l); + valueb = vle8_v_i8m8(pCnt, l); + vse8_v_i8m8 (pCnt, vsadd_vv_i8m8(valuea, valueb, l), l); + pV += l; + pCnt += l; + } +#else + int32_t cnt = length >> 2; + + while (cnt > 0l) + { + q31_t valuea = riscv_nn_read_q7x4_ia(&pV); + q31_t valueb = riscv_nn_read_q7x4(pCnt); + + write_q7x4_ia(&pCnt, __RV_KADD8(valuea, valueb)); + cnt--; + } + cnt = length & 0x3; + while (cnt > 0l) + { + *pCnt++ += *pV++; + cnt--; + } +#endif /* defined(RISCV_VECTOR) */ +} + +/** + * @} end of NNBasicMath group + */ \ No newline at end of file diff --git a/components/nmsis/nn/src/NNSupportFunctions/riscv_nn_add_q7.c b/components/nmsis/nn/src/NNSupportFunctions/riscv_nn_add_q7.c new file mode 100644 index 00000000..f08aa6fa --- /dev/null +++ b/components/nmsis/nn/src/NNSupportFunctions/riscv_nn_add_q7.c @@ -0,0 +1,101 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_nn_add_q7.c + * Description: Non saturating addition of elements of a q7 vector. + * + * $Date: 09. October 2020 + * $Revision: V.1.0.1 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "riscv_nn_tables.h" +#include "riscv_nnsupportfunctions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup NNBasicMath + * @{ + */ + +void riscv_nn_add_q7(const q7_t *input, q31_t *output, uint32_t block_size) +{ + uint32_t block_count; + q31_t result = 0; +#if defined (RISCV_VECTOR) + uint32_t blkCnt = block_size; /* Loop counter */ + size_t l; + const q7_t *pCnt = input; + vint8m2_t pA_v8m2; + vint32m1_t temp; + l = vsetvl_e32m1(1); + temp = vsub_vv_i32m1(temp, temp, l); + + for (; (l = vsetvl_e8m2(blkCnt)) > 0; blkCnt -= l) { + pA_v8m2 = vle8_v_i8m2(pCnt, l); + pCnt += l; + result += (q31_t)vmv_x_s_i32m1_i32(vwredsum_vs_i16m4_i32m1(temp,vwadd_vx_i16m4(pA_v8m2,0, l),temp, l)); + // vsetvl_e32m1(1); + //lack of mf2 function 2020.11.17 + } + // result += (q31_t)vmv_x_s_i32m1_i32(addRes_i32m1); +#else +#if defined(RISCV_MATH_DSP) + /* Loop unrolling: Compute 4 outputs at a time */ + block_count = block_size >> 2U; + + while (block_count > 0U) + { + const int32_t mult_q15x2 = (1UL << 16) | 1UL; + q31_t in_q7x4 = riscv_nn_read_q7x4_ia(&input); + q31_t temp_q15x2 = __SXTAB16(__SXTB16(in_q7x4), __ROR((uint32_t)in_q7x4, 8)); + + result = __SMLAD(temp_q15x2, mult_q15x2, result); + + /* Decrement loop counter */ + block_count--; + } + + /* Loop unrolling: Compute remaining outputs */ + block_count = block_size & 0x3; +#else + block_count = block_size; +#endif + while (block_count > 0U) + { + /* Add and store result in destination buffer. */ + result += *input++; + + /* Decrement loop counter */ + block_count--; + } +#endif /*defined (RISCV_VECTOR)*/ + *output = result; +} + +/** + * @} end of NNBasicMath group + */ \ No newline at end of file diff --git a/components/nmsis/nn/src/NNSupportFunctions/riscv_nn_depthwise_conv_nt_t_padded_s8.c b/components/nmsis/nn/src/NNSupportFunctions/riscv_nn_depthwise_conv_nt_t_padded_s8.c new file mode 100644 index 00000000..921bc079 --- /dev/null +++ b/components/nmsis/nn/src/NNSupportFunctions/riscv_nn_depthwise_conv_nt_t_padded_s8.c @@ -0,0 +1,80 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_nn_depthwise_conv_nt_t_padded_s8.c + * Description: Depthwise convolution with padded matrices. + * + * $Date: 09. October 2020 + * $Revision: V.1.0.2 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ + +#include "riscv_nnsupportfunctions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup NNBasicMath + * @{ + */ + +/* + * Depthwise convolution of transposed rhs matrix with 4 lhs matrices. One or more of the rhs matrices are padded. + * Dimensions are the same for lhs and rhs. + * + * Refer header file for details. + * + */ + +q7_t *riscv_nn_depthwise_conv_nt_t_padded_s8(const q7_t *lhs, + const q7_t *rhs, + const int32_t input_offset, + const uint16_t num_ch, + const int32_t *out_shift, + const int32_t *out_mult, + const int32_t out_offset, + const int32_t activation_min, + const int32_t activation_max, + const uint16_t row_x_col, + const int32_t *const output_bias, + q7_t *out) +{ + (void)lhs; + (void)rhs; + (void)input_offset; + (void)num_ch; + (void)out_shift; + (void)out_mult; + (void)out_offset; + (void)activation_min; + (void)activation_max; + (void)row_x_col; + (void)output_bias; + (void)out; + return NULL; +} + +/** + * @} end of NNBasicMath group + */ diff --git a/components/nmsis/nn/src/NNSupportFunctions/riscv_nn_depthwise_conv_nt_t_s8.c b/components/nmsis/nn/src/NNSupportFunctions/riscv_nn_depthwise_conv_nt_t_s8.c new file mode 100644 index 00000000..b1196993 --- /dev/null +++ b/components/nmsis/nn/src/NNSupportFunctions/riscv_nn_depthwise_conv_nt_t_s8.c @@ -0,0 +1,79 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_nn_depthwise_conv_nt_t_s8.c + * Description: Depthwise convolution on matrices with no padding. + * + * $Date: 09. October 2020 + * $Revision: V.1.0.2 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ + +#include "riscv_nnsupportfunctions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup NNBasicMath + * @{ + */ + +/* + * Depthwise convolution of rhs matrix with 4 lhs matrices with no padding. Dimensions are the same for lhs and rhs. + * + * Refer header file for details. + * + */ + +q7_t *riscv_nn_depthwise_conv_nt_t_s8(const q7_t *lhs, + const q7_t *rhs, + const int32_t input_offset, + const uint16_t num_ch, + const int32_t *out_shift, + const int32_t *out_mult, + const int32_t out_offset, + const int32_t activation_min, + const int32_t activation_max, + const uint16_t row_x_col, + const int32_t *const output_bias, + q7_t *out) +{ + (void)lhs; + (void)rhs; + (void)input_offset; + (void)num_ch; + (void)out_shift; + (void)out_mult; + (void)out_offset; + (void)activation_min; + (void)activation_max; + (void)row_x_col; + (void)output_bias; + (void)out; + return NULL; +} + +/** + * @} end of NNBasicMath group + */ diff --git a/components/nmsis/nn/src/NNSupportFunctions/riscv_nn_mat_mul_core_1x_s8.c b/components/nmsis/nn/src/NNSupportFunctions/riscv_nn_mat_mul_core_1x_s8.c new file mode 100644 index 00000000..40999616 --- /dev/null +++ b/components/nmsis/nn/src/NNSupportFunctions/riscv_nn_mat_mul_core_1x_s8.c @@ -0,0 +1,91 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_nn_mat_mul_core_1x_s8.c + * Description: General Matrix-multiplication function + * + * $Date: 09. October 2020 + * $Revision: V.1.0.2 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ + +#include "riscv_nnsupportfunctions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup NNBasicMath + * @{ + */ + +/* + * s8 matrix multiplication to process 1 row + * + * Refer header file for details. + * + */ + +riscv_status riscv_nn_mat_mul_core_1x_s8(int32_t row_elements, + const int8_t *row_base, + const int8_t *col_base, + int32_t *const sum_col, + int32_t *const output) +{ + int32_t acc_n0 = 0; + int32_t sum_tmp = 0; + +#if defined (RISCV_VECTOR) + uint32_t blkCnt = row_elements; /* Loop counter */ + size_t l; + const q7_t *pCol = col_base; + const q7_t *pRow = row_base; + vint8m2_t v_col,v_row; + vint32m1_t temp; + l = vsetvl_e8m2(1); + temp = vsub_vv_i32m1(temp,temp, l); + for (; (l = vsetvl_e8m2(blkCnt)) > 0; blkCnt -= l) { + v_col = vle8_v_i8m2(pCol, l); + v_row = vle8_v_i8m2(pRow, l); + pCol += l; + pRow += l; + sum_tmp += vmv_x_s_i32m1_i32(vwredsum_vs_i16m4_i32m1(temp,vwadd_vx_i16m4(v_col,0, l),temp, l)); + l = vsetvl_e8m2(blkCnt); + acc_n0 += vmv_x_s_i32m1_i32(vwredsum_vs_i16m4_i32m1(temp,vwadd_vv_i16m4(v_col,v_row, l),temp, l)); + } +#else + for (int i = 0; i < row_elements; i++) + { + sum_tmp += col_base[i]; + acc_n0 += row_base[i] * col_base[i]; + } +#endif + + *sum_col = sum_tmp; + *output = acc_n0; + return RISCV_MATH_SUCCESS; +} + +/** + * @} end of NNBasicMath group + */ diff --git a/components/nmsis/nn/src/NNSupportFunctions/riscv_nn_mat_mul_core_4x_s8.c b/components/nmsis/nn/src/NNSupportFunctions/riscv_nn_mat_mul_core_4x_s8.c new file mode 100644 index 00000000..34afae3f --- /dev/null +++ b/components/nmsis/nn/src/NNSupportFunctions/riscv_nn_mat_mul_core_4x_s8.c @@ -0,0 +1,87 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_nn_mat_mul_core_4x_s8.c + * Description: General matrix multiplication function for MVE extension + * + * $Date: 09. October 2020 + * $Revision: V.2.0.1 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ + +#include "riscv_nnsupportfunctions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup NNBasicMath + * @{ + */ + +/* + * s8 matrix multiplication to process 4 rows and one column + * + * Refer header file for details. + * + */ +riscv_status riscv_nn_mat_mul_core_4x_s8(const int32_t row_elements, + const int32_t offset, + const int8_t *row_base, + const int8_t *col_base, + int32_t *const sum_col, + int32_t *const output) +{ + int32_t acc_n0 = 0; + int32_t acc_n1 = 0; + int32_t acc_n2 = 0; + int32_t acc_n3 = 0; + + const int8_t *ip_row_0 = row_base; + const int8_t *ip_row_1 = row_base + offset; + const int8_t *ip_row_2 = row_base + (2 * offset); + const int8_t *ip_row_3 = row_base + (3 * offset); + int32_t sum_tmp = 0; + + for (int i = 0; i < row_elements; i++) + { + int32_t col = col_base[i]; + sum_tmp += col; + acc_n0 += ip_row_0[i] * col; + acc_n1 += ip_row_1[i] * col; + acc_n2 += ip_row_2[i] * col; + acc_n3 += ip_row_3[i] * col; + } + output[0] = acc_n0; + output[1] = acc_n1; + output[2] = acc_n2; + output[3] = acc_n3; + + *sum_col = sum_tmp; + + return RISCV_MATH_SUCCESS; +} + +/** + * @} end of NNBasicMath group + */ diff --git a/components/nmsis/nn/src/NNSupportFunctions/riscv_nn_mat_mult_nt_t_s8.c b/components/nmsis/nn/src/NNSupportFunctions/riscv_nn_mat_mult_nt_t_s8.c new file mode 100644 index 00000000..a2d723c1 --- /dev/null +++ b/components/nmsis/nn/src/NNSupportFunctions/riscv_nn_mat_mult_nt_t_s8.c @@ -0,0 +1,783 @@ +/* + * Copyright (C) 2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_nn_mat_mult_s8_nt_t_s8 + * Description: Matrix multiplication support function with the right-hand-side (rhs) matrix transposed + * + * $Date: 09. October 2020 + * $Revision: V.1.0.3 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "riscv_nnsupportfunctions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup NNBasicMath + * @{ + */ + +/* + * s8 matrix multiplication with the right-hand-side matrix transposed + * + * Refer header file for details. + * + */ +riscv_status riscv_nn_mat_mult_nt_t_s8(const q7_t *lhs, + const q7_t *rhs, + const q31_t *bias, + q7_t *dst, + const int32_t *dst_multipliers, + const int32_t *dst_shifts, + const int32_t lhs_rows, + const int32_t rhs_rows, + const int32_t rhs_cols, + const int32_t lhs_offset, + const int32_t dst_offset, + const int32_t activation_min, + const int32_t activation_max) +{ +#if defined(RISCV_MATH_DSP) && !defined (RISCV_VECTOR) + const int32_t off0 = rhs_cols - 4; + + for (int32_t rhs_rows_idx = 0; rhs_rows_idx <= (rhs_rows - 2); rhs_rows_idx += 2) + { + const q7_t *lhs_ptr = &lhs[0]; + q7_t *dst_ptr = &dst[0]; + + q31_t lhs_offset_contribution0 = 0; + q31_t lhs_offset_contribution1 = 0; + + for (int32_t x = 0; x < rhs_cols; ++x) + { + lhs_offset_contribution0 += rhs[x]; + lhs_offset_contribution1 += rhs[x + rhs_cols]; + } + + lhs_offset_contribution0 *= lhs_offset; + lhs_offset_contribution1 *= lhs_offset; + if (bias) + { + lhs_offset_contribution0 += bias[rhs_rows_idx]; + lhs_offset_contribution1 += bias[rhs_rows_idx + 1]; + } + + int32_t lhs_rows_idx = lhs_rows >> 1; + + while (lhs_rows_idx) + { + const q7_t *rhs_ptr = &rhs[0]; + + q31_t res00 = lhs_offset_contribution0; + q31_t res01 = lhs_offset_contribution1; + q31_t res10 = lhs_offset_contribution0; + q31_t res11 = lhs_offset_contribution1; + + int32_t rhs_cols_idx = 0; + + q31_t val0, val1, val2, val3, val4, val5; + + for (; rhs_cols_idx <= (rhs_cols - 16); rhs_cols_idx += 16) + { + val1 = riscv_nn_read_q7x4_ia((const q7_t **)&rhs_ptr); + val2 = __SXTB16(val1); + val0 = riscv_nn_read_q7x4_ia((const q7_t **)&lhs_ptr); + val3 = __SXTB16(val0); + val4 = riscv_nn_read_q7x4((const q7_t *)&rhs_ptr[off0]); + val1 = __SXTB16_RORn(val1, 8); + val0 = __SXTB16_RORn(val0, 8); + + // 4 x MAC res00, res01 + res00 = __SMLAD(val3, val2, res00); + val5 = __SXTB16(val4); + res00 = __SMLAD(val0, val1, res00); + val4 = __SXTB16_RORn(val4, 8); + res01 = __SMLAD(val3, val5, res01); + res01 = __SMLAD(val0, val4, res01); + + // 4 x MAC res10, res11 + val0 = riscv_nn_read_q7x4((const q7_t *)&lhs_ptr[off0]); + val3 = __SXTB16(val0); + val0 = __SXTB16_RORn(val0, 8); + res10 = __SMLAD(val3, val2, res10); + res11 = __SMLAD(val3, val5, res11); + res10 = __SMLAD(val0, val1, res10); + val1 = riscv_nn_read_q7x4_ia((const q7_t **)&rhs_ptr); + res11 = __SMLAD(val0, val4, res11); + + val4 = riscv_nn_read_q7x4((const q7_t *)&rhs_ptr[off0]); + val2 = __SXTB16(val1); + val0 = riscv_nn_read_q7x4_ia((const q7_t **)&lhs_ptr); + val3 = __SXTB16(val0); + val1 = __SXTB16_RORn(val1, 8); + val0 = __SXTB16_RORn(val0, 8); + + // 4 x MAC res00, res01 + res00 = __SMLAD(val3, val2, res00); + val5 = __SXTB16(val4); + res00 = __SMLAD(val0, val1, res00); + val4 = __SXTB16_RORn(val4, 8); + res01 = __SMLAD(val3, val5, res01); + res01 = __SMLAD(val0, val4, res01); + + // 4 x MAC res10, res11 + val0 = riscv_nn_read_q7x4((const q7_t *)&lhs_ptr[off0]); + val3 = __SXTB16(val0); + val0 = __SXTB16_RORn(val0, 8); + res10 = __SMLAD(val3, val2, res10); + res11 = __SMLAD(val3, val5, res11); + res10 = __SMLAD(val0, val1, res10); + val1 = riscv_nn_read_q7x4_ia((const q7_t **)&rhs_ptr); + res11 = __SMLAD(val0, val4, res11); + + val4 = riscv_nn_read_q7x4((const q7_t *)&rhs_ptr[off0]); + val2 = __SXTB16(val1); + val0 = riscv_nn_read_q7x4_ia((const q7_t **)&lhs_ptr); + val3 = __SXTB16(val0); + val1 = __SXTB16_RORn(val1, 8); + val0 = __SXTB16_RORn(val0, 8); + + // 4 x MAC res00, res01 + res00 = __SMLAD(val3, val2, res00); + val5 = __SXTB16(val4); + res00 = __SMLAD(val0, val1, res00); + val4 = __SXTB16_RORn(val4, 8); + res01 = __SMLAD(val3, val5, res01); + res01 = __SMLAD(val0, val4, res01); + + // 4 x MAC res10, res11 + val0 = riscv_nn_read_q7x4((const q7_t *)&lhs_ptr[off0]); + val3 = __SXTB16(val0); + val0 = __SXTB16_RORn(val0, 8); + res10 = __SMLAD(val3, val2, res10); + res11 = __SMLAD(val3, val5, res11); + res10 = __SMLAD(val0, val1, res10); + val1 = riscv_nn_read_q7x4_ia((const q7_t **)&rhs_ptr); + res11 = __SMLAD(val0, val4, res11); + + val4 = riscv_nn_read_q7x4((const q7_t *)&rhs_ptr[off0]); + val2 = __SXTB16(val1); + val0 = riscv_nn_read_q7x4_ia((const q7_t **)&lhs_ptr); + val3 = __SXTB16(val0); + val1 = __SXTB16_RORn(val1, 8); + val0 = __SXTB16_RORn(val0, 8); + + // 4 x MAC res00, res01 + res00 = __SMLAD(val3, val2, res00); + val5 = __SXTB16(val4); + res00 = __SMLAD(val0, val1, res00); + val4 = __SXTB16_RORn(val4, 8); + res01 = __SMLAD(val3, val5, res01); + res01 = __SMLAD(val0, val4, res01); + + // 4 x MAC res10, res11 + val0 = riscv_nn_read_q7x4((const q7_t *)&lhs_ptr[off0]); + val3 = __SXTB16(val0); + val0 = __SXTB16_RORn(val0, 8); + res10 = __SMLAD(val3, val2, res10); + res11 = __SMLAD(val3, val5, res11); + res10 = __SMLAD(val0, val1, res10); + res11 = __SMLAD(val0, val4, res11); + } + + for (; rhs_cols_idx < rhs_cols; ++rhs_cols_idx) + { + q7_t rhs_value0 = rhs_ptr[0]; + q7_t rhs_value1 = rhs_ptr[rhs_cols]; + q7_t lhs_value = lhs_ptr[0]; + + res00 += lhs_value * rhs_value0; + res01 += lhs_value * rhs_value1; + + lhs_value = lhs_ptr[rhs_cols]; + res10 += lhs_value * rhs_value0; + res11 += lhs_value * rhs_value1; + + ++rhs_ptr; + ++lhs_ptr; + } + + // Quantize down + res00 = riscv_nn_requantize(res00, dst_multipliers[rhs_rows_idx], dst_shifts[rhs_rows_idx]); + res01 = riscv_nn_requantize(res01, dst_multipliers[rhs_rows_idx + 1], dst_shifts[rhs_rows_idx + 1]); + res10 = riscv_nn_requantize(res10, dst_multipliers[rhs_rows_idx], dst_shifts[rhs_rows_idx]); + res11 = riscv_nn_requantize(res11, dst_multipliers[rhs_rows_idx + 1], dst_shifts[rhs_rows_idx + 1]); + + // Add offset + res00 += dst_offset; + res01 += dst_offset; + res10 += dst_offset; + res11 += dst_offset; + + // Clamp the result + res00 = MAX(res00, activation_min); + res00 = MIN(res00, activation_max); + res01 = MAX(res01, activation_min); + res01 = MIN(res01, activation_max); + res10 = MAX(res10, activation_min); + res10 = MIN(res10, activation_max); + res11 = MAX(res11, activation_min); + res11 = MIN(res11, activation_max); + + dst_ptr[0] = (q7_t)res00; + dst_ptr[1] = (q7_t)res01; + dst_ptr += rhs_rows; + dst_ptr[0] = (q7_t)res10; + dst_ptr[1] = (q7_t)res11; + dst_ptr += rhs_rows; + + lhs_ptr += rhs_cols; + + lhs_rows_idx--; + } + + // Left-over rows + if (lhs_rows % 2) + { + const q7_t *rhs_ptr = &rhs[0]; + + q31_t res00 = lhs_offset_contribution0; + q31_t res01 = lhs_offset_contribution1; + + int32_t rhs_cols_idx = 0; + + q31_t val0, val1, val2, val3, val4, val5; + for (; rhs_cols_idx <= (rhs_cols - 16); rhs_cols_idx += 16) + { + val0 = riscv_nn_read_q7x4_ia((const q7_t **)&rhs_ptr); + val1 = riscv_nn_read_q7x4((const q7_t *)&rhs_ptr[off0]); + val2 = riscv_nn_read_q7x4_ia((const q7_t **)&lhs_ptr); + val3 = __SXTB16(val0); + val5 = __SXTB16(val2); + val4 = __SXTB16(val1); + val0 = __SXTB16_RORn(val0, 8); + val2 = __SXTB16_RORn(val2, 8); + val1 = __SXTB16_RORn(val1, 8); + + // 4 x MAC res00, res01 + res00 = __SMLAD(val5, val3, res00); + res00 = __SMLAD(val2, val0, res00); + res01 = __SMLAD(val5, val4, res01); + res01 = __SMLAD(val2, val1, res01); + + val0 = riscv_nn_read_q7x4_ia((const q7_t **)&rhs_ptr); + val1 = riscv_nn_read_q7x4((const q7_t *)&rhs_ptr[off0]); + val2 = riscv_nn_read_q7x4_ia((const q7_t **)&lhs_ptr); + val3 = __SXTB16(val0); + val5 = __SXTB16(val2); + val4 = __SXTB16(val1); + val0 = __SXTB16_RORn(val0, 8); + val2 = __SXTB16_RORn(val2, 8); + val1 = __SXTB16_RORn(val1, 8); + + // 4 x MAC res00, res01 + res00 = __SMLAD(val5, val3, res00); + res00 = __SMLAD(val2, val0, res00); + res01 = __SMLAD(val5, val4, res01); + res01 = __SMLAD(val2, val1, res01); + + val0 = riscv_nn_read_q7x4_ia((const q7_t **)&rhs_ptr); + val1 = riscv_nn_read_q7x4((const q7_t *)&rhs_ptr[off0]); + val2 = riscv_nn_read_q7x4_ia((const q7_t **)&lhs_ptr); + val3 = __SXTB16(val0); + val5 = __SXTB16(val2); + val4 = __SXTB16(val1); + val0 = __SXTB16_RORn(val0, 8); + val2 = __SXTB16_RORn(val2, 8); + val1 = __SXTB16_RORn(val1, 8); + + // 4 x MAC res00, res01 + res00 = __SMLAD(val5, val3, res00); + res00 = __SMLAD(val2, val0, res00); + res01 = __SMLAD(val5, val4, res01); + res01 = __SMLAD(val2, val1, res01); + + val0 = riscv_nn_read_q7x4_ia((const q7_t **)&rhs_ptr); + val1 = riscv_nn_read_q7x4((const q7_t *)&rhs_ptr[off0]); + val2 = riscv_nn_read_q7x4_ia((const q7_t **)&lhs_ptr); + val3 = __SXTB16(val0); + val5 = __SXTB16(val2); + val4 = __SXTB16(val1); + val0 = __SXTB16_RORn(val0, 8); + val2 = __SXTB16_RORn(val2, 8); + val1 = __SXTB16_RORn(val1, 8); + + // 4 x MAC res00, res01 + res00 = __SMLAD(val5, val3, res00); + res00 = __SMLAD(val2, val0, res00); + res01 = __SMLAD(val5, val4, res01); + res01 = __SMLAD(val2, val1, res01); + } + + // Left-over accumulations + for (; rhs_cols_idx < rhs_cols; ++rhs_cols_idx) + { + q7_t rhs_value0 = rhs_ptr[0]; + q7_t rhs_value1 = rhs_ptr[rhs_cols]; + q7_t lhs_value = lhs_ptr[0]; + + res00 += lhs_value * rhs_value0; + res01 += lhs_value * rhs_value1; + + ++rhs_ptr; + ++lhs_ptr; + } + + // Quantize down + res00 = riscv_nn_requantize(res00, dst_multipliers[rhs_rows_idx], dst_shifts[rhs_rows_idx]); + res01 = riscv_nn_requantize(res01, dst_multipliers[rhs_rows_idx + 1], dst_shifts[rhs_rows_idx + 1]); + + // Add offset + res00 += dst_offset; + res01 += dst_offset; + + // Clamp the result + res00 = MAX(res00, activation_min); + res00 = MIN(res00, activation_max); + res01 = MAX(res01, activation_min); + res01 = MIN(res01, activation_max); + + dst_ptr[0] = (q7_t)res00; + dst_ptr[1] = (q7_t)res01; + } + + rhs += 2 * rhs_cols; + dst += 2; + } + + if (rhs_rows % 2) + { + const q7_t *lhs_ptr = &lhs[0]; + q7_t *dst_ptr = &dst[0]; + + for (int32_t lhs_rows_idx = 0; lhs_rows_idx < lhs_rows; ++lhs_rows_idx) + { + const q7_t *rhs_ptr = &rhs[0]; + q31_t res00 = 0; + if (bias) + { + res00 = bias[rhs_rows - 1]; + } + + for (int32_t rhs_cols_idx = 0; rhs_cols_idx < rhs_cols; ++rhs_cols_idx) + { + q31_t rhs_value = rhs_ptr[0]; + q31_t lhs_value = lhs_ptr[0] + lhs_offset; + + res00 += lhs_value * rhs_value; + + ++rhs_ptr; + ++lhs_ptr; + } + + // Quantize down + res00 = riscv_nn_requantize(res00, dst_multipliers[rhs_rows - 1], dst_shifts[rhs_rows - 1]); + + // Add offset + res00 += dst_offset; + + // Clamp the result + res00 = MAX(res00, activation_min); + res00 = MIN(res00, activation_max); + + dst_ptr[0] = (q7_t)res00; + dst_ptr += rhs_rows; + } + } +#elif defined (RISCV_VECTOR) + for (int32_t rhs_rows_idx = 0; rhs_rows_idx <= (rhs_rows - 2); rhs_rows_idx += 2) + { + const q7_t *lhs_ptr = &lhs[0]; + q7_t *dst_ptr = &dst[0]; + + q31_t lhs_offset_contribution0 = 0; + q31_t lhs_offset_contribution1 = 0; + + for (int32_t x = 0; x < rhs_cols; ++x) + { + lhs_offset_contribution0 += rhs[x]; + lhs_offset_contribution1 += rhs[x + rhs_cols]; + } + + lhs_offset_contribution0 *= lhs_offset; + lhs_offset_contribution1 *= lhs_offset; + if (bias) + { + lhs_offset_contribution0 += bias[rhs_rows_idx]; + lhs_offset_contribution1 += bias[rhs_rows_idx + 1]; + } + + int32_t lhs_rows_idx = lhs_rows >> 1; + + // Left-over rows + while (lhs_rows_idx) + { + const q7_t *rhs_ptr = &rhs[0]; + + q31_t res00 = lhs_offset_contribution0; + q31_t res01 = lhs_offset_contribution1; + q31_t res10 = lhs_offset_contribution0; + q31_t res11 = lhs_offset_contribution1; + size_t l; + uint32_t blkCnt = rhs_cols; + l = vsetvl_e8m1(blkCnt); + vint8m1_t rhs_value0,rhs_value1,lhs_value; + vint32m4_t vch00m4,vch01m4,vch10m4,vch11m4; + vint32m1_t vch00m1,vch01m1,vch10m1,vch11m1; + vint32m1_t vtemp00m1; + vch00m4 = vsub_vv_i32m4(vch00m4, vch00m4, l); + vch01m4 = vsub_vv_i32m4(vch01m4, vch01m4, l); + vch10m4 = vsub_vv_i32m4(vch10m4, vch10m4, l); + vch11m4 = vsub_vv_i32m4(vch11m4, vch11m4, l); + vtemp00m1 = vmv_v_x_i32m1(0, l); + for (; (l = vsetvl_e8m1(blkCnt)) > 0; blkCnt -= l) { + rhs_value0 = vle8_v_i8m1(rhs_ptr, l); + rhs_value1 = vle8_v_i8m1(rhs_ptr + rhs_cols, l); + lhs_value = vle8_v_i8m1(lhs_ptr, l); + vch00m4= vwadd_wv_i32m4(vch00m4, vwmul_vv_i16m2(lhs_value, rhs_value0, l), l); + vch01m4= vwadd_wv_i32m4(vch01m4, vwmul_vv_i16m2(lhs_value, rhs_value1, l), l); + lhs_value = vle8_v_i8m1(lhs_ptr + rhs_cols, l); + vch10m4= vwadd_wv_i32m4(vch10m4, vwmul_vv_i16m2(lhs_value, rhs_value0, l), l); + vch11m4= vwadd_wv_i32m4(vch11m4, vwmul_vv_i16m2(lhs_value, rhs_value1, l), l); + rhs_ptr += l; + lhs_ptr += l; + } + l = vsetvl_e8m1(rhs_cols); + vch00m1 = vredsum_vs_i32m4_i32m1(vtemp00m1, vch00m4, vtemp00m1, l); + vch01m1 = vredsum_vs_i32m4_i32m1(vtemp00m1, vch01m4, vtemp00m1, l); + vch10m1 = vredsum_vs_i32m4_i32m1(vtemp00m1, vch10m4, vtemp00m1, l); + vch11m1 = vredsum_vs_i32m4_i32m1(vtemp00m1, vch11m4, vtemp00m1, l); + res00 += (q31_t)vmv_x_s_i32m1_i32(vch00m1); + res01 += (q31_t)vmv_x_s_i32m1_i32(vch01m1); + res10 += (q31_t)vmv_x_s_i32m1_i32(vch10m1); + res11 += (q31_t)vmv_x_s_i32m1_i32(vch11m1); + + // Quantize down + res00 = riscv_nn_requantize(res00, dst_multipliers[rhs_rows_idx], dst_shifts[rhs_rows_idx]); + res01 = riscv_nn_requantize(res01, dst_multipliers[rhs_rows_idx + 1], dst_shifts[rhs_rows_idx + 1]); + res10 = riscv_nn_requantize(res10, dst_multipliers[rhs_rows_idx], dst_shifts[rhs_rows_idx]); + res11 = riscv_nn_requantize(res11, dst_multipliers[rhs_rows_idx + 1], dst_shifts[rhs_rows_idx + 1]); + + // Add offset + res00 += dst_offset; + res01 += dst_offset; + res10 += dst_offset; + res11 += dst_offset; + + // Clamp the result + res00 = MAX(res00, activation_min); + res00 = MIN(res00, activation_max); + res01 = MAX(res01, activation_min); + res01 = MIN(res01, activation_max); + res10 = MAX(res10, activation_min); + res10 = MIN(res10, activation_max); + res11 = MAX(res11, activation_min); + res11 = MIN(res11, activation_max); + + dst_ptr[0] = (q7_t)res00; + dst_ptr[1] = (q7_t)res01; + dst_ptr += rhs_rows; + dst_ptr[0] = (q7_t)res10; + dst_ptr[1] = (q7_t)res11; + dst_ptr += rhs_rows; + + lhs_ptr += rhs_cols; + + lhs_rows_idx--; + } + + // Left-over rows + if (lhs_rows % 2) + { + const q7_t *rhs_ptr = &rhs[0]; + + q31_t res00 = lhs_offset_contribution0; + q31_t res01 = lhs_offset_contribution1; + + size_t l; + uint32_t blkCnt = rhs_cols; + l = vsetvl_e8m1(blkCnt); + vint8m1_t rhs_value0,rhs_value1,lhs_value; + vint32m4_t vch00m4,vch01m4; + vint32m1_t vch00m1,vch01m1; + vint32m1_t vtemp00m1; + vch00m4 = vsub_vv_i32m4(vch00m4, vch00m4, l); + vch01m4 = vsub_vv_i32m4(vch01m4, vch01m4, l); + vtemp00m1 = vmv_v_x_i32m1(0, l); + for (; (l = vsetvl_e8m1(blkCnt)) > 0; blkCnt -= l) { + rhs_value0 = vle8_v_i8m1(rhs_ptr, l); + rhs_value1 = vle8_v_i8m1(rhs_ptr + rhs_cols, l); + lhs_value = vle8_v_i8m1(lhs_ptr, l); + vch00m4= vwadd_wv_i32m4(vch00m4, vwmul_vv_i16m2(lhs_value, rhs_value0, l), l); + vch01m4= vwadd_wv_i32m4(vch01m4, vwmul_vv_i16m2(lhs_value, rhs_value1, l), l); + rhs_ptr += l; + lhs_ptr += l; + } + l = vsetvl_e8m1(rhs_cols); + vch00m1 = vredsum_vs_i32m4_i32m1(vtemp00m1, vch00m4, vtemp00m1, l); + vch01m1 = vredsum_vs_i32m4_i32m1(vtemp00m1, vch01m4, vtemp00m1, l); + + res00 += (q31_t)vmv_x_s_i32m1_i32(vch00m1); + res01 += (q31_t)vmv_x_s_i32m1_i32(vch01m1); + + + // Quantize down + res00 = riscv_nn_requantize(res00, dst_multipliers[rhs_rows_idx], dst_shifts[rhs_rows_idx]); + res01 = riscv_nn_requantize(res01, dst_multipliers[rhs_rows_idx + 1], dst_shifts[rhs_rows_idx + 1]); + + // Add offset + res00 += dst_offset; + res01 += dst_offset; + + // Clamp the result + res00 = MAX(res00, activation_min); + res00 = MIN(res00, activation_max); + res01 = MAX(res01, activation_min); + res01 = MIN(res01, activation_max); + + dst_ptr[0] = (q7_t)res00; + dst_ptr[1] = (q7_t)res01; + } + + + rhs += 2 * rhs_cols; + dst += 2; + } + + if (rhs_rows % 2) + { + const q7_t *lhs_ptr = &lhs[0]; + q7_t *dst_ptr = &dst[0]; + + for (int32_t lhs_rows_idx = 0; lhs_rows_idx < lhs_rows; ++lhs_rows_idx) + { + const q7_t *rhs_ptr = &rhs[0]; + q31_t res00 = 0; + if (bias) + { + res00 = bias[rhs_rows - 1]; + } + + for (int32_t rhs_cols_idx = 0; rhs_cols_idx < rhs_cols; ++rhs_cols_idx) + { + q31_t rhs_value = rhs_ptr[0]; + q31_t lhs_value = lhs_ptr[0] + lhs_offset; + + res00 += lhs_value * rhs_value; + + ++rhs_ptr; + ++lhs_ptr; + } + + // Quantize down + res00 = riscv_nn_requantize(res00, dst_multipliers[rhs_rows - 1], dst_shifts[rhs_rows - 1]); + + // Add offset + res00 += dst_offset; + + // Clamp the result + res00 = MAX(res00, activation_min); + res00 = MIN(res00, activation_max); + + dst_ptr[0] = (q7_t)res00; + dst_ptr += rhs_rows; + } + } + +#else + for (int32_t rhs_rows_idx = 0; rhs_rows_idx <= (rhs_rows - 2); rhs_rows_idx += 2) + { + const q7_t *lhs_ptr = &lhs[0]; + q7_t *dst_ptr = &dst[0]; + + q31_t lhs_offset_contribution0 = 0; + q31_t lhs_offset_contribution1 = 0; + + for (int32_t x = 0; x < rhs_cols; ++x) + { + lhs_offset_contribution0 += rhs[x]; + lhs_offset_contribution1 += rhs[x + rhs_cols]; + } + + lhs_offset_contribution0 *= lhs_offset; + lhs_offset_contribution1 *= lhs_offset; + if (bias) + { + lhs_offset_contribution0 += bias[rhs_rows_idx]; + lhs_offset_contribution1 += bias[rhs_rows_idx + 1]; + } + + int32_t lhs_rows_idx = lhs_rows >> 1; + + while (lhs_rows_idx) + { + const q7_t *rhs_ptr = &rhs[0]; + + q31_t res00 = lhs_offset_contribution0; + q31_t res01 = lhs_offset_contribution1; + q31_t res10 = lhs_offset_contribution0; + q31_t res11 = lhs_offset_contribution1; + + for (int32_t rhs_cols_idx = rhs_cols; rhs_cols_idx != 0; rhs_cols_idx--) + { + q7_t rhs_value0 = rhs_ptr[0]; + q7_t rhs_value1 = rhs_ptr[rhs_cols]; + q7_t lhs_value = lhs_ptr[0]; + + res00 += lhs_value * rhs_value0; + res01 += lhs_value * rhs_value1; + + lhs_value = lhs_ptr[rhs_cols]; + res10 += lhs_value * rhs_value0; + res11 += lhs_value * rhs_value1; + + ++rhs_ptr; + ++lhs_ptr; + } + + // Quantize down + res00 = riscv_nn_requantize(res00, dst_multipliers[rhs_rows_idx], dst_shifts[rhs_rows_idx]); + res01 = riscv_nn_requantize(res01, dst_multipliers[rhs_rows_idx + 1], dst_shifts[rhs_rows_idx + 1]); + res10 = riscv_nn_requantize(res10, dst_multipliers[rhs_rows_idx], dst_shifts[rhs_rows_idx]); + res11 = riscv_nn_requantize(res11, dst_multipliers[rhs_rows_idx + 1], dst_shifts[rhs_rows_idx + 1]); + + // Add offset + res00 += dst_offset; + res01 += dst_offset; + res10 += dst_offset; + res11 += dst_offset; + + // Clamp the result + res00 = MAX(res00, activation_min); + res00 = MIN(res00, activation_max); + res01 = MAX(res01, activation_min); + res01 = MIN(res01, activation_max); + res10 = MAX(res10, activation_min); + res10 = MIN(res10, activation_max); + res11 = MAX(res11, activation_min); + res11 = MIN(res11, activation_max); + + dst_ptr[0] = (q7_t)res00; + dst_ptr[1] = (q7_t)res01; + dst_ptr += rhs_rows; + dst_ptr[0] = (q7_t)res10; + dst_ptr[1] = (q7_t)res11; + dst_ptr += rhs_rows; + + lhs_ptr += rhs_cols; + + lhs_rows_idx--; + } + + // Left-over rows + if (lhs_rows % 2) + { + const q7_t *rhs_ptr = &rhs[0]; + + q31_t res00 = lhs_offset_contribution0; + q31_t res01 = lhs_offset_contribution1; + + for (int32_t rhs_cols_idx = rhs_cols; rhs_cols_idx != 0; rhs_cols_idx--) + { + q7_t rhs_value0 = rhs_ptr[0]; + q7_t rhs_value1 = rhs_ptr[rhs_cols]; + q7_t lhs_value = lhs_ptr[0]; + + res00 += lhs_value * rhs_value0; + res01 += lhs_value * rhs_value1; + + ++rhs_ptr; + ++lhs_ptr; + } + + // Quantize down + res00 = riscv_nn_requantize(res00, dst_multipliers[rhs_rows_idx], dst_shifts[rhs_rows_idx]); + res01 = riscv_nn_requantize(res01, dst_multipliers[rhs_rows_idx + 1], dst_shifts[rhs_rows_idx + 1]); + + // Add offset + res00 += dst_offset; + res01 += dst_offset; + + // Clamp the result + res00 = MAX(res00, activation_min); + res00 = MIN(res00, activation_max); + res01 = MAX(res01, activation_min); + res01 = MIN(res01, activation_max); + + dst_ptr[0] = (q7_t)res00; + dst_ptr[1] = (q7_t)res01; + } + + rhs += 2 * rhs_cols; + dst += 2; + } + + if (rhs_rows % 2) + { + const q7_t *lhs_ptr = &lhs[0]; + q7_t *dst_ptr = &dst[0]; + + for (int32_t lhs_rows_idx = 0; lhs_rows_idx < lhs_rows; ++lhs_rows_idx) + { + const q7_t *rhs_ptr = &rhs[0]; + q31_t res00 = 0; + if (bias) + { + res00 = bias[rhs_rows - 1]; + } + + for (int32_t rhs_cols_idx = rhs_cols; rhs_cols_idx != 0; rhs_cols_idx--) + { + q31_t rhs_value = rhs_ptr[0]; + q31_t lhs_value = lhs_ptr[0] + lhs_offset; + + res00 += lhs_value * rhs_value; + + ++rhs_ptr; + ++lhs_ptr; + } + + // Quantize down + res00 = riscv_nn_requantize(res00, dst_multipliers[rhs_rows - 1], dst_shifts[rhs_rows - 1]); + + // Add offset + res00 += dst_offset; + + // Clamp the result + res00 = MAX(res00, activation_min); + res00 = MIN(res00, activation_max); + + dst_ptr[0] = (q7_t)res00; + dst_ptr += rhs_rows; + } + } +#endif + return RISCV_MATH_SUCCESS; +} + +/** + * @} end of NNBasicMath group + */ diff --git a/components/nmsis/nn/src/NNSupportFunctions/riscv_nn_mult_q15.c b/components/nmsis/nn/src/NNSupportFunctions/riscv_nn_mult_q15.c new file mode 100644 index 00000000..b901c602 --- /dev/null +++ b/components/nmsis/nn/src/NNSupportFunctions/riscv_nn_mult_q15.c @@ -0,0 +1,160 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_nn_mult_q15.c + * Description: Q15 vector multiplication with variable output shifts + * + * $Date: 09. October 2020 + * $Revision: V.1.0.2 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "riscv_nnsupportfunctions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup NNBasicMath + * @{ + */ + +/** + * @brief Q7 vector multiplication with variable output shifts + * @param[in] *pSrcA pointer to the first input vector + * @param[in] *pSrcB pointer to the second input vector + * @param[out] *pDst pointer to the output vector + * @param[in] out_shift amount of right-shift for output + * @param[in] blockSize number of samples in each vector + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated. + */ + +void riscv_nn_mult_q15(q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, const uint16_t out_shift, uint32_t blockSize) +{ +#if defined (RISCV_VECTOR) && ((__XLEN != 32) || (__FLEN != 32)) + uint32_t blkCnt = blockSize; /* Loop counter */ + size_t l; + q15_t *pCnt = pDst; + q15_t *pA = pSrcA; + q15_t *pB = pSrcB; + vint16m2_t pA_v16m2,pB_v16m2; + vint32m4_t mulRes_i32m4; + vint64m8_t addRes_i64m8; + + for (; (l = vsetvl_e16m2(blkCnt)) > 0; blkCnt -= l) { + pA_v16m2 = vle16_v_i16m2(pA, l); + pB_v16m2 = vle16_v_i16m2(pB, l); + pA += l; + pB += l; + mulRes_i32m4 = vwmul_vv_i32m4(pA_v16m2,pB_v16m2, l); + addRes_i64m8 = vwadd_vx_i64m8(mulRes_i32m4,NN_ROUND(out_shift), l); + vse16_v_i16m2 (pCnt, vnclip_wx_i16m2(vnsra_wx_i32m4(addRes_i64m8,out_shift, l),0, l), l); + pCnt += l; + } +#else + uint32_t blkCnt; /* loop counters */ + +#if defined (RISCV_MATH_DSP) + +/* Run the below code for RISC-V Core with DSP enabled */ + q31_t inA1, inA2, inB1, inB2; /* temporary input variables */ + q15_t out1, out2, out3, out4; /* temporary output variables */ + // q31_t mul1, mul2, mul3, mul4; /* temporary variables */ + q63_t mul1, mul2; + + /* loop Unrolling */ + blkCnt = blockSize >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* read two samples at a time from sourceA */ + inA1 = riscv_nn_read_q15x2_ia((const q15_t **)&pSrcA); + /* read two samples at a time from sourceB */ + inB1 = riscv_nn_read_q15x2_ia((const q15_t **)&pSrcB); + /* read two samples at a time from sourceA */ + inA2 = riscv_nn_read_q15x2_ia((const q15_t **)&pSrcA); + /* read two samples at a time from sourceB */ + inB2 = riscv_nn_read_q15x2_ia((const q15_t **)&pSrcB); + + // /* multiply mul = sourceA * sourceB */ + // mul1 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1 >> 16)); + // mul2 = (q31_t) ((q15_t) inA1 * (q15_t) inB1); + // mul3 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) (inB2 >> 16)); + // mul4 = (q31_t) ((q15_t) inA2 * (q15_t) inB2); + mul1 = __RV_SMUL16(inA1,inB1); + mul2 = __RV_SMUL16(inA2,inB2); + + // /* saturate result to 16 bit */ + // out1 = (q15_t) __SSAT((q31_t) (mul1 + NN_ROUND(out_shift)) >> out_shift, 16); + // out2 = (q15_t) __SSAT((q31_t) (mul2 + NN_ROUND(out_shift)) >> out_shift, 16); + // out3 = (q15_t) __SSAT((q31_t) (mul3 + NN_ROUND(out_shift)) >> out_shift, 16); + // out4 = (q15_t) __SSAT((q31_t) (mul4 + NN_ROUND(out_shift)) >> out_shift, 16); + out1 = (q15_t) __SSAT((q31_t) ((mul1 & 0xffffffff) + NN_ROUND(out_shift)) >> out_shift, 16); + out2 = (q15_t) __SSAT((q31_t) (((mul1 & 0xffffffff00000000UL) >> 32) + NN_ROUND(out_shift)) >> out_shift, 16); + out3 = (q15_t) __SSAT((q31_t) ((mul2 & 0xffffffff) + NN_ROUND(out_shift)) >> out_shift, 16); + out4 = (q15_t) __SSAT((q31_t) (((mul2 & 0xffffffff00000000UL) >> 32) + NN_ROUND(out_shift)) >> out_shift, 16); + /* store the result */ + + *__SIMD32(pDst)++ = __RV_PKBB16(out2, out1); + *__SIMD32(pDst)++ = __RV_PKBB16(out4, out3); + + + /* Decrement the blockSize loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4U; + +#else + + /* Run the below code for RISC-V Core without DSP */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_DSP) */ + + while (blkCnt > 0U) + { + /* C = A * B */ + /* Multiply the inputs and store the result in the destination buffer */ + *pDst++ = (q15_t)__SSAT(((q31_t)((q31_t)(*pSrcA++) * (*pSrcB++) + NN_ROUND(out_shift)) >> out_shift), 16); + + /* Decrement the blockSize loop counter */ + blkCnt--; + } +#endif /*defined (RISCV_VECTOR)*/ +} + +/** + * @} end of NNBasicMath group + */ diff --git a/components/nmsis/nn/src/NNSupportFunctions/riscv_nn_mult_q7.c b/components/nmsis/nn/src/NNSupportFunctions/riscv_nn_mult_q7.c new file mode 100644 index 00000000..e8778927 --- /dev/null +++ b/components/nmsis/nn/src/NNSupportFunctions/riscv_nn_mult_q7.c @@ -0,0 +1,146 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_nn_mult_q7.c + * Description: Q7 vector multiplication with variable output shifts + * + * $Date: 09. October 2020 + * $Revision: V.1.0.2 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "riscv_nnsupportfunctions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup NNBasicMath + * @{ + */ + +/** + * @brief Q7 vector multiplication with variable output shifts + * @param[in] *pSrcA pointer to the first input vector + * @param[in] *pSrcB pointer to the second input vector + * @param[out] *pDst pointer to the output vector + * @param[in] out_shift amount of right-shift for output + * @param[in] blockSize number of samples in each vector + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q7 range [0x80 0x7F] will be saturated. + */ + +void riscv_nn_mult_q7(q7_t *pSrcA, q7_t *pSrcB, q7_t *pDst, const uint16_t out_shift, uint32_t blockSize) +{ +#if defined (RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + size_t l; + q7_t *pCnt = pDst; + q7_t *pA = pSrcA; + q7_t *pB = pSrcB; + vint8m2_t pA_v8m2,pB_v8m2; + vint16m4_t mulRes_i16m4; + vint32m8_t addRes_i32m8; + + for (; (l = vsetvl_e8m2(blkCnt)) > 0; blkCnt -= l) { + pA_v8m2 = vle8_v_i8m2(pA, l); + pB_v8m2 = vle8_v_i8m2(pB, l); + pA += l; + pB += l; + mulRes_i16m4 = vwmul_vv_i16m4(pA_v8m2,pB_v8m2, l); + addRes_i32m8 = vwadd_vx_i32m8(mulRes_i16m4,NN_ROUND(out_shift), l); + vse8_v_i8m2 (pCnt, vnclip_wx_i8m2(vnsra_wx_i16m4(addRes_i32m8,out_shift, l),0, l), l); + pCnt += l; + } +#else + uint32_t blkCnt; /* loop counters */ + +#if defined(RISCV_MATH_DSP) + +/* Run the below code for RISC-V Core with DSP enabled */ + q7_t out1, out2, out3, out4; /* Temporary variables to store the product */ + q63_t mul1; + q31_t inA1, inB1; + /* loop Unrolling */ + blkCnt = blockSize >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C = A * B */ + /* Multiply the inputs and store the results in temporary variables */ + // out1 = (q7_t) __SSAT(((q15_t) ((q15_t) (*pSrcA++) * (*pSrcB++) + NN_ROUND(out_shift)) >> out_shift), 8); + // out2 = (q7_t) __SSAT(((q15_t) ((q15_t) (*pSrcA++) * (*pSrcB++) + NN_ROUND(out_shift)) >> out_shift), 8); + // out3 = (q7_t) __SSAT(((q15_t) ((q15_t) (*pSrcA++) * (*pSrcB++) + NN_ROUND(out_shift)) >> out_shift), 8); + // out4 = (q7_t) __SSAT(((q15_t) ((q15_t) (*pSrcA++) * (*pSrcB++) + NN_ROUND(out_shift)) >> out_shift), 8); + + inA1 = riscv_nn_read_q7x4_ia((const q7_t **)&pSrcA); + inB1 = riscv_nn_read_q7x4_ia((const q7_t **)&pSrcB); + + mul1 = __RV_SMUL8(inA1,inB1); + + out1 = (q7_t) __SSAT((q15_t) ((mul1 & 0xffff) + NN_ROUND(out_shift)) >> out_shift, 8); + out2 = (q7_t) __SSAT((q15_t) (((mul1 & 0x00000000ffff0000UL) >> 16) + NN_ROUND(out_shift)) >> out_shift, 8); + out3 = (q7_t) __SSAT((q15_t) (((mul1 & 0x0000ffff00000000UL) >> 32) + NN_ROUND(out_shift)) >> out_shift, 8); + out4 = (q7_t) __SSAT((q15_t) (((mul1 & 0xffff000000000000UL) >> 48) + NN_ROUND(out_shift)) >> out_shift, 8); + + /* Store the results of 4 inputs in the destination buffer in single cycle by packing */ + *__SIMD32(pDst)++ = __PACKq7(out1, out2, out3, out4); + + /* Decrement the blockSize loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4U; + +#else + + /* Run the below code for RISC-V Core without DSP */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (RISCV_MATH_DSP) */ + + while (blkCnt > 0U) + { + /* C = A * B */ + /* Multiply the inputs and store the result in the destination buffer */ + *pDst++ = (q7_t)__SSAT(((q15_t)((q15_t)(*pSrcA++) * (*pSrcB++) + NN_ROUND(out_shift)) >> out_shift), 8); + + /* Decrement the blockSize loop counter */ + blkCnt--; + } +#endif /*defined (RISCV_VECTOR)*/ +} + +/** + * @} end of NNBasicMath group + */ diff --git a/components/nmsis/nn/src/NNSupportFunctions/riscv_nn_vec_mat_mult_t_s8.c b/components/nmsis/nn/src/NNSupportFunctions/riscv_nn_vec_mat_mult_t_s8.c new file mode 100644 index 00000000..b61c73e7 --- /dev/null +++ b/components/nmsis/nn/src/NNSupportFunctions/riscv_nn_vec_mat_mult_t_s8.c @@ -0,0 +1,412 @@ +/* + * Copyright (C) 2020-2021 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_nn_vec_mat_mult_t_s8 + * Description: s8 vector by matrix (transposed) multiplication + * + * $Date: 02. May 2021 + * $Revision: V.2.5.0 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "riscv_nnsupportfunctions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup NNBasicMath + * @{ + */ + +/* + * s8 vector(lhs) by matrix (transposed) multiplication + * + * Refer header file for details. + * + */ +riscv_status riscv_nn_vec_mat_mult_t_s8(const q7_t *lhs, + const q7_t *rhs, + const q31_t *bias, + q7_t *dst, + const int32_t lhs_offset, + const int32_t rhs_offset, + const int32_t dst_offset, + const int32_t dst_multiplier, + const int32_t dst_shift, + const int32_t rhs_cols, + const int32_t rhs_rows, + const int32_t activation_min, + const int32_t activation_max) +{ + (void)rhs_offset; +#if defined(RISCV_MATH_DSP) + int32_t row_loop_cnt = rhs_rows / 2; + + const int16_t lhs_offset_s16 = (int16_t)lhs_offset; + + const uint32_t lhs_offset_s16x2 = __PKHBT(lhs_offset_s16, lhs_offset_s16, 16); + + for (int32_t i = 0; i < row_loop_cnt; i++) + { + int32_t acc_0 = 0; + int32_t acc_1 = 0; + if (bias) + { + acc_0 = *bias++; + acc_1 = *bias++; + } + + const int32_t col_loop_cnt = rhs_cols / 4; + + const int8_t *lhs_vec = lhs; + const int8_t *rhs_0 = rhs; + const int8_t *rhs_1 = rhs + rhs_cols; + rhs += 2 * rhs_cols; + + for (int j = col_loop_cnt; j != 0; j--) + { + int32_t vec_0 = riscv_nn_read_q7x4_ia(&lhs_vec); + int32_t vec_1 = __SXTAB16_RORn(lhs_offset_s16x2, (uint32_t)vec_0, 8); + + vec_0 = __SXTAB16(lhs_offset_s16x2, vec_0); + + int32_t ker_0 = riscv_nn_read_q7x4_ia(&rhs_0); + int32_t ker_1 = __SXTB16_RORn((uint32_t)ker_0, 8); + ker_0 = __SXTB16(ker_0); + + acc_0 = __SMLAD(ker_1, vec_1, acc_0); + acc_0 = __SMLAD(ker_0, vec_0, acc_0); + + ker_0 = riscv_nn_read_q7x4_ia(&rhs_1); + ker_1 = __SXTB16_RORn((uint32_t)ker_0, 8); + ker_0 = __SXTB16(ker_0); + + acc_1 = __SMLAD(ker_1, vec_1, acc_1); + acc_1 = __SMLAD(ker_0, vec_0, acc_1); + } + + for (int k = col_loop_cnt * 4; k < rhs_cols; k++) + { + const int32_t lhs_temp = (*lhs_vec + lhs_offset); + lhs_vec++; + acc_0 += lhs_temp * (*rhs_0); + rhs_0++; + acc_1 += lhs_temp * (*rhs_1); + rhs_1++; + } + + acc_0 = riscv_nn_requantize(acc_0, dst_multiplier, dst_shift); + acc_1 = riscv_nn_requantize(acc_1, dst_multiplier, dst_shift); + + // Add offset + acc_0 += dst_offset; + acc_1 += dst_offset; + // Clamp the result + acc_0 = MAX(acc_0, activation_min); + acc_0 = MIN(acc_0, activation_max); + acc_1 = MAX(acc_1, activation_min); + acc_1 = MIN(acc_1, activation_max); + + *dst++ = (q7_t)acc_0; + *dst++ = (q7_t)acc_1; + } + + if (rhs_rows & 0x1) + { + int32_t acc_0 = 0; + if (bias) + { + acc_0 = *bias++; + } + const int32_t col_loop_cnt = rhs_cols / 4; + + const int8_t *lhs_vec = lhs; + const int8_t *rhs_0 = rhs; + + for (int i = col_loop_cnt; i != 0; i--) + { + int32_t vec_0 = riscv_nn_read_q7x4_ia(&lhs_vec); + int32_t vec_1 = __SXTAB16_RORn(lhs_offset_s16x2, (uint32_t)vec_0, 8); + vec_0 = __SXTAB16(lhs_offset_s16x2, vec_0); + + int32_t ker_0 = riscv_nn_read_q7x4_ia(&rhs_0); + int32_t ker_1 = __SXTB16_RORn((uint32_t)ker_0, 8); + ker_0 = __SXTB16(ker_0); + + acc_0 = __SMLAD(ker_1, vec_1, acc_0); + acc_0 = __SMLAD(ker_0, vec_0, acc_0); + } + + for (int j = col_loop_cnt * 4; j < rhs_cols; j++) + { + const int32_t lhs_temp = (*lhs_vec + lhs_offset); + lhs_vec++; + acc_0 += lhs_temp * (*rhs_0); + rhs_0++; + } + + acc_0 = riscv_nn_requantize(acc_0, dst_multiplier, dst_shift); + + // Add offset + acc_0 += dst_offset; + // Clamp the result + acc_0 = MAX(acc_0, activation_min); + acc_0 = MIN(acc_0, activation_max); + + *dst++ = (q7_t)acc_0; + } + +#else +#if defined (RISCV_VECTOR) + for (int32_t rhs_rows_idx = 0; rhs_rows_idx <= (rhs_rows - 2); rhs_rows_idx += 2) + { + const q7_t *lhs_ptr = &lhs[0]; + const q7_t *rhs_ptr = &rhs[0]; + + /* accumulate over the vector */ + size_t l; + uint32_t blkCnt = rhs_cols; + q31_t res00,res01; + // q7_t temp[] = {0}; + l = vsetvl_e8m1(blkCnt); + vint8m1_t va1m1,vb1m1,vb2m1; + vint16m2_t vch00m2,vch01m2; + vint64m1_t vch00m1,vch01m1; + vint64m1_t vtemp00m1,vtemp01m1; + vint32m4_t vch00m4,vch01m4; + //initial array and temp sum to zero + vch00m4 = vmv_v_x_i32m4(0, l); + vch01m4 = vmv_v_x_i32m4(0, l); + vch00m1 = vmv_v_x_i64m1(0, l); + vch01m1 = vmv_v_x_i64m1(0, l); + vtemp00m1 = vmv_v_x_i64m1(0, l); + vtemp01m1 = vmv_v_x_i64m1(0, l); + for (; (l = vsetvl_e8m1(blkCnt)) > 0; blkCnt -= l) { + va1m1 = vle8_v_i8m1(lhs_ptr + lhs_offset, l); + vb1m1 = vle8_v_i8m1(rhs_ptr + rhs_offset, l); + vb2m1 = vle8_v_i8m1(rhs_ptr + rhs_offset + rhs_cols, l); + lhs_ptr += l; + rhs_ptr += l; + vch00m2= vwmul_vv_i16m2(va1m1, vb1m1, l); + vch01m2= vwmul_vv_i16m2(va1m1, vb2m1, l); + vch00m4 = vwadd_wv_i32m4(vch00m4, vch00m2, l); + vch01m4 = vwadd_wv_i32m4(vch01m4, vch01m2, l); + } + //set vl to max vl + l = vsetvl_e8m1(rhs_rows - 2); + //calculate sum + vch00m1 = vwredsum_vs_i32m4_i64m1(vtemp00m1, vch00m4, vtemp00m1, l); + vch01m1 = vwredsum_vs_i32m4_i64m1(vtemp01m1, vch01m4, vtemp01m1, l); + //set vl to 1 + l = vsetvl_e32m1(1); + vch00m1 = vmin_vx_i64m1(vmax_vx_i64m1(vch00m1, 0xffffffff80000000ULL, l), 0x000000007fffffffULL, l); + vch01m1 = vmin_vx_i64m1(vmax_vx_i64m1(vch01m1, 0xffffffff80000000ULL, l), 0x000000007fffffffULL, l); + //Here we calculate sum of four vector + //write result scalar back + res00 = (q31_t)vmv_x_s_i64m1_i64(vch00m1); + res01 = (q31_t)vmv_x_s_i64m1_i64(vch01m1); + /* init the sum with bias */ + res00 += *bias++; + res01 += *bias++; + + // Quantize down + res00 = riscv_nn_requantize(res00, dst_multiplier, dst_shift); + res01 = riscv_nn_requantize(res01, dst_multiplier, dst_shift); + + // Add offset + res00 += dst_offset; + res01 += dst_offset; + + // Clamp the result + res00 = MAX(res00, activation_min); + res00 = MIN(res00, activation_max); + res01 = MAX(res01, activation_min); + res01 = MIN(res01, activation_max); + + *dst++ = (q7_t)res00; + *dst++ = (q7_t)res01; + + rhs += rhs_cols; + } + + if (rhs_rows % 2) + { + const q7_t *lhs_ptr = &lhs[0]; + const q7_t *rhs_ptr = &rhs[0]; + + /* accumulate over the vector */ + size_t l; + uint32_t blkCnt = rhs_cols; + q31_t res00; + // q7_t temp[] = {0}; + l = vsetvl_e8m1(blkCnt); + vint8m1_t va1m1,vb1m1; + vint16m2_t vch00m2; + vint64m1_t vch00m1; + vint64m1_t vtemp00m1; + vint32m4_t vch00m4; + //initial array and temp sum to zero + vch00m4 = vmv_v_x_i32m4(0, l); + vch00m1 = vmv_v_x_i64m1(0, l); + vtemp00m1 = vmv_v_x_i64m1(0, l); + for (; (l = vsetvl_e8m1(blkCnt)) > 0; blkCnt -= l) { + va1m1 = vle8_v_i8m1(lhs_ptr + lhs_offset, l); + vb1m1 = vle8_v_i8m1(rhs_ptr + rhs_offset, l); + lhs_ptr += l; + rhs_ptr += l; + vch00m2= vwmul_vv_i16m2(va1m1, vb1m1, l); + vch00m4 = vwadd_wv_i32m4(vch00m4, vch00m2, l); + } + //set vl to max vl + l = vsetvl_e8m1(rhs_cols); + //calculate sum + vch00m1 = vwredsum_vs_i32m4_i64m1(vtemp00m1, vch00m4, vtemp00m1, l); + //set vl to 1 + vsetvl_e32m1(1); + vch00m1 = vmin_vx_i64m1(vmax_vx_i64m1(vch00m1, 0xffffffff80000000ULL, l), 0x000000007fffffffULL, l); + //Here we calculate sum of four vector + //write result scalar back + res00 = (q31_t)vmv_x_s_i64m1_i64(vch00m1); + /* init the sum with bias */ + res00 += *bias++; + + // Quantize down + res00 = riscv_nn_requantize(res00, dst_multiplier, dst_shift); + + // Add offset + res00 += dst_offset; + + // Clamp the result + res00 = MAX(res00, activation_min); + res00 = MIN(res00, activation_max); + + *dst = (q7_t)res00; + } + +#else + int32_t row_loop_cnt = rhs_rows / 3; + + for (int i_row_loop_cnt = 0; i_row_loop_cnt < row_loop_cnt; i_row_loop_cnt++) + { + const q7_t *lhs_ptr = lhs; + const q7_t *rhs_ptr_0 = &rhs[0]; + const q7_t *rhs_ptr_1 = &rhs[rhs_cols]; + const q7_t *rhs_ptr_2 = &rhs[rhs_cols * 2]; + + q31_t res00 = 0; + q31_t res01 = 0; + q31_t res02 = 0; + if (bias) + { + res00 = *bias++; + res01 = *bias++; + res02 = *bias++; + } + for (int32_t rhs_cols_idx = 0; rhs_cols_idx < rhs_cols; ++rhs_cols_idx) + { + const q31_t rhs_value0 = (int8_t)*rhs_ptr_0; + const q31_t rhs_value1 = (int8_t)*rhs_ptr_1; + const q31_t rhs_value2 = (int8_t)*rhs_ptr_2; + const q31_t lhs_value = (int8_t)*lhs_ptr + lhs_offset; + + res00 += lhs_value * rhs_value0; + res01 += lhs_value * rhs_value1; + res02 += lhs_value * rhs_value2; + + ++rhs_ptr_0; + ++rhs_ptr_1; + ++rhs_ptr_2; + ++lhs_ptr; + } + // Quantize down + res00 = riscv_nn_requantize(res00, dst_multiplier, dst_shift); + res01 = riscv_nn_requantize(res01, dst_multiplier, dst_shift); + res02 = riscv_nn_requantize(res02, dst_multiplier, dst_shift); + + // Add offset + res00 += dst_offset; + res01 += dst_offset; + res02 += dst_offset; + + // Clamp the result + res00 = MAX(res00, activation_min); + res00 = MIN(res00, activation_max); + res01 = MAX(res01, activation_min); + res01 = MIN(res01, activation_max); + res02 = MAX(res02, activation_min); + res02 = MIN(res02, activation_max); + + *dst++ = (q7_t)res00; + *dst++ = (q7_t)res01; + *dst++ = (q7_t)res02; + + rhs += 3 * rhs_cols; + } + + const int loop_cnt = rhs_rows % 3; + + for (int i_loop_cnt = 0; i_loop_cnt < loop_cnt; i_loop_cnt++) + { + const q7_t *lhs_ptr = &lhs[0]; + const q7_t *rhs_ptr = &rhs[0]; + + q31_t res00 = 0; + if (bias) + { + res00 = *bias++; + } + + for (int32_t rhs_cols_idx = 0; rhs_cols_idx < rhs_cols; ++rhs_cols_idx) + { + q31_t rhs_value0 = (int8_t)rhs_ptr[0] + rhs_offset; + q31_t lhs_value = (int8_t)lhs_ptr[0] + lhs_offset; + + res00 += lhs_value * rhs_value0; + + ++rhs_ptr; + ++lhs_ptr; + } + + // Quantize down + res00 = riscv_nn_requantize(res00, dst_multiplier, dst_shift); + + // Add offset + res00 += dst_offset; + + // Clamp the result + res00 = MAX(res00, activation_min); + res00 = MIN(res00, activation_max); + + *dst++ = (q7_t)res00; + rhs += rhs_cols; + } +#endif /*defined (RISCV_VECTOR)*/ +#endif + return RISCV_MATH_SUCCESS; +} + +/** + * @} end of NNBasicMath group + */ diff --git a/components/nmsis/nn/src/NNSupportFunctions/riscv_nn_vec_mat_mult_t_svdf_s8.c b/components/nmsis/nn/src/NNSupportFunctions/riscv_nn_vec_mat_mult_t_svdf_s8.c new file mode 100644 index 00000000..0022c82a --- /dev/null +++ b/components/nmsis/nn/src/NNSupportFunctions/riscv_nn_vec_mat_mult_t_svdf_s8.c @@ -0,0 +1,312 @@ +/* + * Copyright (C) 2021 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_nn_vec_mat_mult_t_svdf_s8 + * Description: s8 vector by matrix (transposed) multiplication with + * s16 output. Targetted at SVDF operator. + * + * $Date: 15. April 2021 + * $Revision: V.1.0.0 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "riscv_nnsupportfunctions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup NNBasicMath + * @{ + */ + +/* + * s8 vector(lhs) by matrix (transposed) multiplication + * + * Refer header file for details. + * + */ +riscv_status riscv_nn_vec_mat_mult_t_svdf_s8(const q7_t *lhs, + const q7_t *rhs, + q15_t *dst, + const int32_t lhs_offset, + const int32_t rhs_offset, + const int32_t dst_offset, + const int32_t dst_multiplier, + const int32_t dst_shift, + const int32_t rhs_cols, + const int32_t rhs_rows, + const int32_t activation_min, + const int32_t activation_max) +{ + (void)rhs_offset; + if (rhs_cols < 0 || (Q31_MAX - rhs_cols) < 16 || dst_offset < 0) + { + return RISCV_MATH_ARGUMENT_ERROR; + } + + (void)rhs_offset; +#if defined(RISCV_MATH_DSP) && !defined(RISCV_VECTOR) + int32_t row_loop_cnt = rhs_rows / 2; + + const int16_t lhs_offset_s16 = lhs_offset; + const int16_t rhs_offset_s16 = rhs_offset; + + const uint32_t lhs_offset_s16x2 = __PKHBT(lhs_offset_s16, lhs_offset_s16, 16); + const uint32_t rhs_offset_s16x2 = __PKHBT(rhs_offset_s16, rhs_offset_s16, 16); + for (int32_t i = 0; i < row_loop_cnt; i++) + { + int32_t acc_0 = 0; + int32_t acc_1 = 0; + + const int32_t col_loop_cnt = rhs_cols / 4; + const int8_t *lhs_vec = lhs; + const int8_t *rhs_0 = rhs; + const int8_t *rhs_1 = rhs + rhs_cols; + rhs += 2 * rhs_cols; + for (int j = col_loop_cnt; j != 0; j--) + { + int32_t vec_0 = riscv_nn_read_q7x4_ia(&lhs_vec); + int32_t vec_1 = __SXTAB16_RORn(lhs_offset_s16x2, (uint32_t)vec_0, 8); + vec_0 = __SXTAB16(lhs_offset_s16x2, vec_0); + int32_t ker_0 = riscv_nn_read_q7x4_ia(&rhs_0); + int32_t ker_1 = __SXTAB16_RORn(rhs_offset_s16x2, (uint32_t)ker_0, 8); + ker_0 = __SXTAB16(rhs_offset_s16x2, ker_0); + acc_0 = __SMLAD(ker_1, vec_1, acc_0); + acc_0 = __SMLAD(ker_0, vec_0, acc_0); + ker_0 = riscv_nn_read_q7x4_ia(&rhs_1); + ker_1 = __SXTAB16_RORn(rhs_offset_s16x2, (uint32_t)ker_0, 8); + ker_0 = __SXTAB16(rhs_offset_s16x2, ker_0); + acc_1 = __SMLAD(ker_1, vec_1, acc_1); + acc_1 = __SMLAD(ker_0, vec_0, acc_1); + } + for (int k = col_loop_cnt * 4; k < rhs_cols; k++) + { + const int32_t lhs_temp = (*lhs_vec + lhs_offset); + lhs_vec++; + acc_0 += lhs_temp * (*rhs_0 + rhs_offset); + rhs_0++; + acc_1 += lhs_temp * (*rhs_1 + rhs_offset); + rhs_1++; + } + acc_0 = riscv_nn_requantize(acc_0, dst_multiplier, dst_shift); + acc_1 = riscv_nn_requantize(acc_1, dst_multiplier, dst_shift); + + // Clamp the result + acc_0 = MAX(acc_0, activation_min); + acc_0 = MIN(acc_0, activation_max); + acc_1 = MAX(acc_1, activation_min); + acc_1 = MIN(acc_1, activation_max); + *dst = (q15_t)acc_0; + *(dst + dst_offset) = (q15_t)acc_1; + dst += 2 * dst_offset; + } + if (rhs_rows & 0x1) + { + int32_t acc_0 = 0; + const int32_t col_loop_cnt = rhs_cols / 4; + const int8_t *lhs_vec = lhs; + const int8_t *rhs_0 = rhs; + for (int i = col_loop_cnt; i != 0; i--) + { + int32_t vec_0 = riscv_nn_read_q7x4_ia(&lhs_vec); + int32_t vec_1 = __SXTAB16(lhs_offset_s16x2, __ROR((uint32_t)vec_0, 8)); + vec_0 = __SXTAB16(lhs_offset_s16x2, vec_0); + int32_t ker_0 = riscv_nn_read_q7x4_ia(&rhs_0); + int32_t ker_1 = __SXTAB16(rhs_offset_s16x2, __ROR((uint32_t)ker_0, 8)); + ker_0 = __SXTAB16(rhs_offset_s16x2, ker_0); + acc_0 = __SMLAD(ker_1, vec_1, acc_0); + acc_0 = __SMLAD(ker_0, vec_0, acc_0); + } + for (int j = col_loop_cnt * 4; j < rhs_cols; j++) + { + const int32_t lhs_temp = (*lhs_vec + lhs_offset); + lhs_vec++; + acc_0 += lhs_temp * (*rhs_0 + rhs_offset); + rhs_0++; + } + acc_0 = riscv_nn_requantize(acc_0, dst_multiplier, dst_shift); + + // Clamp the result + acc_0 = MAX(acc_0, activation_min); + acc_0 = MIN(acc_0, activation_max); + *dst = (q15_t)acc_0; + dst += dst_offset; + } + +#else + +#if defined(RISCV_VECTOR) + uint32_t blkCnt; /* Loop counter */ + size_t l; + vint8m2_t v_rhs0, v_rhs1, v_rhs2; + vint8m2_t v_lhs; + vint16m4_t v_a, v_b, v_c; + vint32m1_t v_temp; + const q7_t *pRHS0; + const q7_t *pRHS1; + const q7_t *pRHS2; + const q7_t *pLHS; + ptrdiff_t bstride; + l = vsetvl_e32m1(1); + v_temp = vsub_vv_i32m1(v_temp, v_temp, l); +#endif + int32_t row_loop_cnt = rhs_rows / 3; + + for (int i_row_loop_cnt = 0; i_row_loop_cnt < row_loop_cnt; i_row_loop_cnt++) + { + const q7_t *lhs_ptr = lhs; + const q7_t *rhs_ptr_0 = &rhs[0]; + const q7_t *rhs_ptr_1 = &rhs[rhs_cols]; + const q7_t *rhs_ptr_2 = &rhs[rhs_cols * 2]; +#if defined(RISCV_VECTOR) + blkCnt = rhs_cols; + pRHS0 = rhs_ptr_0; + pRHS1 = rhs_ptr_1; + pRHS2 = rhs_ptr_2; + pLHS = lhs_ptr; + l = vsetvl_e32m8(blkCnt); + v_a = vsub_vv_i16m4(v_a,v_a, l); + v_b = vsub_vv_i16m4(v_b,v_b, l); + v_c = vsub_vv_i16m4(v_c,v_c, l); + for (; (l = vsetvl_e8m2(blkCnt)) > 0; blkCnt -= l) { + v_rhs0 = vle8_v_i8m2(pRHS0, l); + v_rhs1 = vle8_v_i8m2(pRHS1, l); + v_rhs2 = vle8_v_i8m2(pRHS2, l); + v_lhs = vle8_v_i8m2(pLHS, l); + v_lhs = vadd_vx_i8m2(v_lhs,lhs_offset, l); + v_a = vwmacc_vv_i16m4(v_a,v_lhs,v_rhs0, l); + v_b = vwmacc_vv_i16m4(v_b,v_lhs,v_rhs1, l); + v_c = vwmacc_vv_i16m4(v_c,v_lhs,v_rhs2, l); + + pRHS0 += l; + pRHS1 += l; + pRHS2 += l; + pLHS += l; + } + l = vsetvl_e8m2(rhs_cols); + q31_t res00 = vmv_x_s_i32m1_i32(vwredsum_vs_i16m4_i32m1(v_temp,v_a,v_temp, l)); + l = vsetvl_e8m2(rhs_cols); + q31_t res01 = vmv_x_s_i32m1_i32(vwredsum_vs_i16m4_i32m1(v_temp,v_b,v_temp, l)); + l = vsetvl_e8m2(rhs_cols); + q31_t res02 = vmv_x_s_i32m1_i32(vwredsum_vs_i16m4_i32m1(v_temp,v_c,v_temp, l)); +#else + q31_t res00 = 0; + q31_t res01 = 0; + q31_t res02 = 0; + for (int32_t rhs_cols_idx = 0; rhs_cols_idx < rhs_cols; ++rhs_cols_idx) + { + const q31_t rhs_value0 = (int8_t)*rhs_ptr_0; + const q31_t rhs_value1 = (int8_t)*rhs_ptr_1; + const q31_t rhs_value2 = (int8_t)*rhs_ptr_2; + const q31_t lhs_value = (int8_t)*lhs_ptr + lhs_offset; + + res00 += lhs_value * rhs_value0; + res01 += lhs_value * rhs_value1; + res02 += lhs_value * rhs_value2; + + ++rhs_ptr_0; + ++rhs_ptr_1; + ++rhs_ptr_2; + ++lhs_ptr; + } +#endif + // Quantize down + res00 = riscv_nn_requantize(res00, dst_multiplier, dst_shift); + res01 = riscv_nn_requantize(res01, dst_multiplier, dst_shift); + res02 = riscv_nn_requantize(res02, dst_multiplier, dst_shift); + + // Clamp the result + res00 = MAX(res00, activation_min); + res00 = MIN(res00, activation_max); + res01 = MAX(res01, activation_min); + res01 = MIN(res01, activation_max); + res02 = MAX(res02, activation_min); + res02 = MIN(res02, activation_max); + + *dst = (q15_t)res00; + *(dst + dst_offset) = (q15_t)res01; + *(dst + 2 * dst_offset) = (q15_t)res02; + dst += 3 * dst_offset; + rhs += 3 * rhs_cols; + } + + const int loop_cnt = rhs_rows % 3; + + for (int i_loop_cnt = 0; i_loop_cnt < loop_cnt; i_loop_cnt++) + { + const q7_t *lhs_ptr = &lhs[0]; + const q7_t *rhs_ptr = &rhs[0]; + + q31_t res00 = 0; + +#if defined(RISCV_VECTOR) + blkCnt = rhs_cols; + pRHS0 = rhs_ptr; + pLHS = lhs_ptr; + l = vsetvl_e32m8(blkCnt); + v_a = vsub_vv_i16m4(v_a,v_a, l); + for (; (l = vsetvl_e8m2(blkCnt)) > 0; blkCnt -= l) { + v_rhs0 = vle8_v_i8m2(pRHS0, l); + v_lhs = vle8_v_i8m2(pLHS, l); + v_lhs = vadd_vx_i8m2(v_lhs,lhs_offset, l); + v_a = vwmacc_vv_i16m4(v_a,v_lhs,v_rhs0, l); + + pRHS0 += l; + pLHS += l; + } + l = vsetvl_e8m2(rhs_cols); + res00 = vmv_x_s_i32m1_i32(vwredsum_vs_i16m4_i32m1(v_temp,v_a,v_temp, l)); +#else + for (int32_t rhs_cols_idx = 0; rhs_cols_idx < rhs_cols; ++rhs_cols_idx) + { + q31_t rhs_value0 = (int8_t)rhs_ptr[0] + rhs_offset; + q31_t lhs_value = (int8_t)lhs_ptr[0] + lhs_offset; + + res00 += lhs_value * rhs_value0; + + ++rhs_ptr; + ++lhs_ptr; + } +#endif + + // Quantize down + res00 = riscv_nn_requantize(res00, dst_multiplier, dst_shift); + + // Clamp the result + res00 = MAX(res00, activation_min); + res00 = MIN(res00, activation_max); + + *dst = (q15_t)res00; + dst += dst_offset; + rhs += rhs_cols; + } +#endif + + return RISCV_MATH_SUCCESS; +} + +/** + * @} end of NNBasicMath group + */ diff --git a/components/nmsis/nn/src/NNSupportFunctions/riscv_nntables.c b/components/nmsis/nn/src/NNSupportFunctions/riscv_nntables.c new file mode 100644 index 00000000..491a5196 --- /dev/null +++ b/components/nmsis/nn/src/NNSupportFunctions/riscv_nntables.c @@ -0,0 +1,204 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_nntables.c + * Description: Converts the elements of the Q7 vector to Q15 vector without left-shift + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "riscv_nnsupportfunctions.h" + +/** + * @brief tables for various activation functions + * + * This file include the declaration of common tables. + * Most of them are used for activation functions + * + * Assumption: + * Unified table: input is 3.x format, i.e, range of [-8, 8) + * sigmoid(8) = 0.9996646498695336 + * tanh(8) = 0.9999997749296758 + * The accuracy here should be good enough + * + * 2-stage HL table: + * + * The entire input range is divided into two parts: + * + * Low range table: 0x000x xxxx or 0x111x xxxx + * table entry will be the binary number excluding the first + * two digits, i.e., 0x0x xxxx or 0x1x xxxx + * + * + * + * High range table 0x0010 0000 -- 0x0111 1111 + * 0x1000 0000 -- 0x1101 1111 + * + * For positive numbers, table entry will be + * 0x0010 0000 -- 0x0111 1111 minus 0x0010 0000 + * i.e., 0x0000 0000 - 0x0101 11111 + * + * same thing for the negative numbers, table entry will be + * 0x1000 0000 -- 0x1101 1111 minux 0x0010 0000 + * i.e., 0x0110 0000 - 0x1011 1111 + */ + +const q7_t sigmoidTable_q7[256] = { + 0x40, 0x42, 0x44, 0x46, 0x48, 0x4a, 0x4c, 0x4e, 0x50, 0x52, 0x53, 0x55, 0x57, 0x59, 0x5a, 0x5c, 0x5e, 0x5f, 0x61, + 0x62, 0x63, 0x65, 0x66, 0x67, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x70, 0x71, 0x72, 0x72, 0x73, 0x74, 0x74, + 0x75, 0x76, 0x76, 0x77, 0x77, 0x78, 0x78, 0x79, 0x79, 0x7a, 0x7a, 0x7a, 0x7b, 0x7b, 0x7b, 0x7c, 0x7c, 0x7c, 0x7c, + 0x7c, 0x7d, 0x7d, 0x7d, 0x7d, 0x7d, 0x7e, 0x7e, 0x7e, 0x7e, 0x7e, 0x7e, 0x7e, 0x7e, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, + 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x02, 0x02, 0x02, 0x02, + 0x02, 0x02, 0x02, 0x02, 0x03, 0x03, 0x03, 0x03, 0x03, 0x04, 0x04, 0x04, 0x04, 0x04, 0x05, 0x05, 0x05, 0x06, 0x06, + 0x06, 0x07, 0x07, 0x08, 0x08, 0x09, 0x09, 0x0a, 0x0a, 0x0b, 0x0c, 0x0c, 0x0d, 0x0e, 0x0e, 0x0f, 0x10, 0x11, 0x12, + 0x13, 0x14, 0x15, 0x16, 0x17, 0x19, 0x1a, 0x1b, 0x1d, 0x1e, 0x1f, 0x21, 0x22, 0x24, 0x26, 0x27, 0x29, 0x2b, 0x2d, + 0x2e, 0x30, 0x32, 0x34, 0x36, 0x38, 0x3a, 0x3c, 0x3e, +}; + +const q15_t sigmoidTable_q15[256] = { + 0x4000, 0x4200, 0x43ff, 0x45fc, 0x47f5, 0x49eb, 0x4bdc, 0x4dc8, 0x4fad, 0x518a, 0x5360, 0x552c, 0x56ef, 0x58a8, + 0x5a57, 0x5bfb, 0x5d93, 0x5f20, 0x60a1, 0x6216, 0x637f, 0x64db, 0x662b, 0x676f, 0x68a6, 0x69d2, 0x6af1, 0x6c05, + 0x6d0d, 0x6e09, 0x6efb, 0x6fe2, 0x70be, 0x7190, 0x7258, 0x7316, 0x73cc, 0x7478, 0x751b, 0x75b7, 0x764a, 0x76d6, + 0x775b, 0x77d8, 0x784f, 0x78c0, 0x792a, 0x798f, 0x79ee, 0x7a48, 0x7a9d, 0x7aed, 0x7b39, 0x7b80, 0x7bc4, 0x7c03, + 0x7c3f, 0x7c78, 0x7cad, 0x7ce0, 0x7d0f, 0x7d3c, 0x7d66, 0x7d8d, 0x7db3, 0x7dd6, 0x7df7, 0x7e16, 0x7e33, 0x7e4f, + 0x7e69, 0x7e81, 0x7e98, 0x7eae, 0x7ec2, 0x7ed5, 0x7ee7, 0x7ef8, 0x7f08, 0x7f17, 0x7f25, 0x7f32, 0x7f3e, 0x7f4a, + 0x7f55, 0x7f5f, 0x7f69, 0x7f72, 0x7f7b, 0x7f83, 0x7f8a, 0x7f91, 0x7f98, 0x7f9e, 0x7fa4, 0x7faa, 0x7faf, 0x7fb4, + 0x7fb8, 0x7fbd, 0x7fc1, 0x7fc5, 0x7fc8, 0x7fcc, 0x7fcf, 0x7fd2, 0x7fd5, 0x7fd7, 0x7fda, 0x7fdc, 0x7fde, 0x7fe0, + 0x7fe2, 0x7fe4, 0x7fe6, 0x7fe7, 0x7fe9, 0x7fea, 0x7feb, 0x7fed, 0x7fee, 0x7fef, 0x7ff0, 0x7ff1, 0x7ff2, 0x7ff3, + 0x7ff4, 0x7ff4, 0x000b, 0x000c, 0x000c, 0x000d, 0x000e, 0x000f, 0x0010, 0x0011, 0x0012, 0x0013, 0x0015, 0x0016, + 0x0017, 0x0019, 0x001a, 0x001c, 0x001e, 0x0020, 0x0022, 0x0024, 0x0026, 0x0029, 0x002b, 0x002e, 0x0031, 0x0034, + 0x0038, 0x003b, 0x003f, 0x0043, 0x0048, 0x004c, 0x0051, 0x0056, 0x005c, 0x0062, 0x0068, 0x006f, 0x0076, 0x007d, + 0x0085, 0x008e, 0x0097, 0x00a1, 0x00ab, 0x00b6, 0x00c2, 0x00ce, 0x00db, 0x00e9, 0x00f8, 0x0108, 0x0119, 0x012b, + 0x013e, 0x0152, 0x0168, 0x017f, 0x0197, 0x01b1, 0x01cd, 0x01ea, 0x0209, 0x022a, 0x024d, 0x0273, 0x029a, 0x02c4, + 0x02f1, 0x0320, 0x0353, 0x0388, 0x03c1, 0x03fd, 0x043c, 0x0480, 0x04c7, 0x0513, 0x0563, 0x05b8, 0x0612, 0x0671, + 0x06d6, 0x0740, 0x07b1, 0x0828, 0x08a5, 0x092a, 0x09b6, 0x0a49, 0x0ae5, 0x0b88, 0x0c34, 0x0cea, 0x0da8, 0x0e70, + 0x0f42, 0x101e, 0x1105, 0x11f7, 0x12f3, 0x13fb, 0x150f, 0x162e, 0x175a, 0x1891, 0x19d5, 0x1b25, 0x1c81, 0x1dea, + 0x1f5f, 0x20e0, 0x226d, 0x2405, 0x25a9, 0x2758, 0x2911, 0x2ad4, 0x2ca0, 0x2e76, 0x3053, 0x3238, 0x3424, 0x3615, + 0x380b, 0x3a04, 0x3c01, 0x3e00, +}; + +const q15_t sigmoidLTable_q15[128] = { + 0x4000, 0x4100, 0x4200, 0x42ff, 0x43ff, 0x44fd, 0x45fc, 0x46f9, 0x47f5, 0x48f1, 0x49eb, 0x4ae5, 0x4bdc, + 0x4cd3, 0x4dc8, 0x4ebb, 0x4fad, 0x509c, 0x518a, 0x5276, 0x5360, 0x5447, 0x552c, 0x560f, 0x56ef, 0x57cd, + 0x58a8, 0x5981, 0x5a57, 0x5b2a, 0x5bfb, 0x5cc9, 0x5d93, 0x5e5b, 0x5f20, 0x5fe2, 0x60a1, 0x615d, 0x6216, + 0x62cc, 0x637f, 0x642e, 0x64db, 0x6584, 0x662b, 0x66ce, 0x676f, 0x680c, 0x68a6, 0x693d, 0x69d2, 0x6a63, + 0x6af1, 0x6b7c, 0x6c05, 0x6c8a, 0x6d0d, 0x6d8d, 0x6e09, 0x6e84, 0x6efb, 0x6f70, 0x6fe2, 0x7051, 0x0f42, + 0x0faf, 0x101e, 0x1090, 0x1105, 0x117c, 0x11f7, 0x1273, 0x12f3, 0x1376, 0x13fb, 0x1484, 0x150f, 0x159d, + 0x162e, 0x16c3, 0x175a, 0x17f4, 0x1891, 0x1932, 0x19d5, 0x1a7c, 0x1b25, 0x1bd2, 0x1c81, 0x1d34, 0x1dea, + 0x1ea3, 0x1f5f, 0x201e, 0x20e0, 0x21a5, 0x226d, 0x2337, 0x2405, 0x24d6, 0x25a9, 0x267f, 0x2758, 0x2833, + 0x2911, 0x29f1, 0x2ad4, 0x2bb9, 0x2ca0, 0x2d8a, 0x2e76, 0x2f64, 0x3053, 0x3145, 0x3238, 0x332d, 0x3424, + 0x351b, 0x3615, 0x370f, 0x380b, 0x3907, 0x3a04, 0x3b03, 0x3c01, 0x3d01, 0x3e00, 0x3f00, +}; + +const q15_t sigmoidHTable_q15[192] = { + 0x70be, 0x7190, 0x7258, 0x7316, 0x73cc, 0x7478, 0x751b, 0x75b7, 0x764a, 0x76d6, 0x775b, 0x77d8, 0x784f, 0x78c0, + 0x792a, 0x798f, 0x79ee, 0x7a48, 0x7a9d, 0x7aed, 0x7b39, 0x7b80, 0x7bc4, 0x7c03, 0x7c3f, 0x7c78, 0x7cad, 0x7ce0, + 0x7d0f, 0x7d3c, 0x7d66, 0x7d8d, 0x7db3, 0x7dd6, 0x7df7, 0x7e16, 0x7e33, 0x7e4f, 0x7e69, 0x7e81, 0x7e98, 0x7eae, + 0x7ec2, 0x7ed5, 0x7ee7, 0x7ef8, 0x7f08, 0x7f17, 0x7f25, 0x7f32, 0x7f3e, 0x7f4a, 0x7f55, 0x7f5f, 0x7f69, 0x7f72, + 0x7f7b, 0x7f83, 0x7f8a, 0x7f91, 0x7f98, 0x7f9e, 0x7fa4, 0x7faa, 0x7faf, 0x7fb4, 0x7fb8, 0x7fbd, 0x7fc1, 0x7fc5, + 0x7fc8, 0x7fcc, 0x7fcf, 0x7fd2, 0x7fd5, 0x7fd7, 0x7fda, 0x7fdc, 0x7fde, 0x7fe0, 0x7fe2, 0x7fe4, 0x7fe6, 0x7fe7, + 0x7fe9, 0x7fea, 0x7feb, 0x7fed, 0x7fee, 0x7fef, 0x7ff0, 0x7ff1, 0x7ff2, 0x7ff3, 0x7ff4, 0x7ff4, 0x000b, 0x000c, + 0x000c, 0x000d, 0x000e, 0x000f, 0x0010, 0x0011, 0x0012, 0x0013, 0x0015, 0x0016, 0x0017, 0x0019, 0x001a, 0x001c, + 0x001e, 0x0020, 0x0022, 0x0024, 0x0026, 0x0029, 0x002b, 0x002e, 0x0031, 0x0034, 0x0038, 0x003b, 0x003f, 0x0043, + 0x0048, 0x004c, 0x0051, 0x0056, 0x005c, 0x0062, 0x0068, 0x006f, 0x0076, 0x007d, 0x0085, 0x008e, 0x0097, 0x00a1, + 0x00ab, 0x00b6, 0x00c2, 0x00ce, 0x00db, 0x00e9, 0x00f8, 0x0108, 0x0119, 0x012b, 0x013e, 0x0152, 0x0168, 0x017f, + 0x0197, 0x01b1, 0x01cd, 0x01ea, 0x0209, 0x022a, 0x024d, 0x0273, 0x029a, 0x02c4, 0x02f1, 0x0320, 0x0353, 0x0388, + 0x03c1, 0x03fd, 0x043c, 0x0480, 0x04c7, 0x0513, 0x0563, 0x05b8, 0x0612, 0x0671, 0x06d6, 0x0740, 0x07b1, 0x0828, + 0x08a5, 0x092a, 0x09b6, 0x0a49, 0x0ae5, 0x0b88, 0x0c34, 0x0cea, 0x0da8, 0x0e70, +}; + +const q7_t tanhTable_q7[256] = { + 0x00, 0x08, 0x10, 0x18, 0x1f, 0x27, 0x2e, 0x35, 0x3b, 0x41, 0x47, 0x4c, 0x51, 0x56, 0x5a, 0x5e, 0x61, 0x65, 0x68, + 0x6a, 0x6d, 0x6f, 0x71, 0x72, 0x74, 0x75, 0x76, 0x78, 0x78, 0x79, 0x7a, 0x7b, 0x7b, 0x7c, 0x7c, 0x7d, 0x7d, 0x7e, + 0x7e, 0x7e, 0x7e, 0x7e, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x81, 0x81, + 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x82, 0x82, 0x82, 0x82, 0x82, 0x83, 0x83, 0x84, 0x84, 0x85, 0x85, 0x86, 0x87, + 0x88, 0x88, 0x8a, 0x8b, 0x8c, 0x8e, 0x8f, 0x91, 0x93, 0x96, 0x98, 0x9b, 0x9f, 0xa2, 0xa6, 0xaa, 0xaf, 0xb4, 0xb9, + 0xbf, 0xc5, 0xcb, 0xd2, 0xd9, 0xe1, 0xe8, 0xf0, 0xf8, +}; + +const q15_t tanhTable_q15[256] = { + 0x0000, 0x07fd, 0x0feb, 0x17b9, 0x1f59, 0x26bf, 0x2ddf, 0x34ae, 0x3b27, 0x4142, 0x46fd, 0x4c56, 0x514d, 0x55e2, + 0x5a1a, 0x5df6, 0x617c, 0x64b0, 0x6797, 0x6a37, 0x6c95, 0x6eb5, 0x709e, 0x7254, 0x73dc, 0x753a, 0x7672, 0x7788, + 0x787f, 0x795b, 0x7a1e, 0x7acb, 0x7b65, 0x7bee, 0x7c66, 0x7cd1, 0x7d30, 0x7d84, 0x7dce, 0x7e0f, 0x7e49, 0x7e7d, + 0x7eaa, 0x7ed2, 0x7ef5, 0x7f14, 0x7f30, 0x7f48, 0x7f5e, 0x7f71, 0x7f82, 0x7f91, 0x7f9e, 0x7fa9, 0x7fb3, 0x7fbc, + 0x7fc4, 0x7fcb, 0x7fd1, 0x7fd7, 0x7fdc, 0x7fe0, 0x7fe4, 0x7fe7, 0x7fea, 0x7fed, 0x7fef, 0x7ff1, 0x7ff3, 0x7ff4, + 0x7ff6, 0x7ff7, 0x7ff8, 0x7ff9, 0x7ffa, 0x7ffa, 0x7ffb, 0x7ffc, 0x7ffc, 0x7ffd, 0x7ffd, 0x7ffd, 0x7ffe, 0x7ffe, + 0x7ffe, 0x7ffe, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x7fff, 0x7fff, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, + 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, + 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8001, 0x8001, 0x8001, 0x8001, 0x8001, 0x8001, + 0x8001, 0x8001, 0x8001, 0x8002, 0x8002, 0x8002, 0x8002, 0x8003, 0x8003, 0x8003, 0x8004, 0x8004, 0x8005, 0x8006, + 0x8006, 0x8007, 0x8008, 0x8009, 0x800a, 0x800c, 0x800d, 0x800f, 0x8011, 0x8013, 0x8016, 0x8019, 0x801c, 0x8020, + 0x8024, 0x8029, 0x802f, 0x8035, 0x803c, 0x8044, 0x804d, 0x8057, 0x8062, 0x806f, 0x807e, 0x808f, 0x80a2, 0x80b8, + 0x80d0, 0x80ec, 0x810b, 0x812e, 0x8156, 0x8183, 0x81b7, 0x81f1, 0x8232, 0x827c, 0x82d0, 0x832f, 0x839a, 0x8412, + 0x849b, 0x8535, 0x85e2, 0x86a5, 0x8781, 0x8878, 0x898e, 0x8ac6, 0x8c24, 0x8dac, 0x8f62, 0x914b, 0x936b, 0x95c9, + 0x9869, 0x9b50, 0x9e84, 0xa20a, 0xa5e6, 0xaa1e, 0xaeb3, 0xb3aa, 0xb903, 0xbebe, 0xc4d9, 0xcb52, 0xd221, 0xd941, + 0xe0a7, 0xe847, 0xf015, 0xf803, +}; + +const q15_t tanhLTable_q15[128] = { + 0x0000, 0x0400, 0x07fd, 0x0bf7, 0x0feb, 0x13d7, 0x17b9, 0x1b90, 0x1f59, 0x2314, 0x26bf, 0x2a58, 0x2ddf, + 0x3151, 0x34ae, 0x37f6, 0x3b27, 0x3e40, 0x4142, 0x442c, 0x46fd, 0x49b6, 0x4c56, 0x4edd, 0x514d, 0x53a3, + 0x55e2, 0x580a, 0x5a1a, 0x5c13, 0x5df6, 0x5fc4, 0x617c, 0x6320, 0x64b0, 0x662d, 0x6797, 0x68f0, 0x6a37, + 0x6b6e, 0x6c95, 0x6dac, 0x6eb5, 0x6fb0, 0x709e, 0x717f, 0x7254, 0x731e, 0x73dc, 0x7490, 0x753a, 0x75da, + 0x7672, 0x7701, 0x7788, 0x7807, 0x787f, 0x78f0, 0x795b, 0x79bf, 0x7a1e, 0x7a77, 0x7acb, 0x7b1b, 0x849b, + 0x84e5, 0x8535, 0x8589, 0x85e2, 0x8641, 0x86a5, 0x8710, 0x8781, 0x87f9, 0x8878, 0x88ff, 0x898e, 0x8a26, + 0x8ac6, 0x8b70, 0x8c24, 0x8ce2, 0x8dac, 0x8e81, 0x8f62, 0x9050, 0x914b, 0x9254, 0x936b, 0x9492, 0x95c9, + 0x9710, 0x9869, 0x99d3, 0x9b50, 0x9ce0, 0x9e84, 0xa03c, 0xa20a, 0xa3ed, 0xa5e6, 0xa7f6, 0xaa1e, 0xac5d, + 0xaeb3, 0xb123, 0xb3aa, 0xb64a, 0xb903, 0xbbd4, 0xbebe, 0xc1c0, 0xc4d9, 0xc80a, 0xcb52, 0xceaf, 0xd221, + 0xd5a8, 0xd941, 0xdcec, 0xe0a7, 0xe470, 0xe847, 0xec29, 0xf015, 0xf409, 0xf803, 0xfc00, +}; + +const q15_t tanhHTable_q15[192] = { + 0x7b65, 0x7bee, 0x7c66, 0x7cd1, 0x7d30, 0x7d84, 0x7dce, 0x7e0f, 0x7e49, 0x7e7d, 0x7eaa, 0x7ed2, 0x7ef5, 0x7f14, + 0x7f30, 0x7f48, 0x7f5e, 0x7f71, 0x7f82, 0x7f91, 0x7f9e, 0x7fa9, 0x7fb3, 0x7fbc, 0x7fc4, 0x7fcb, 0x7fd1, 0x7fd7, + 0x7fdc, 0x7fe0, 0x7fe4, 0x7fe7, 0x7fea, 0x7fed, 0x7fef, 0x7ff1, 0x7ff3, 0x7ff4, 0x7ff6, 0x7ff7, 0x7ff8, 0x7ff9, + 0x7ffa, 0x7ffa, 0x7ffb, 0x7ffc, 0x7ffc, 0x7ffd, 0x7ffd, 0x7ffd, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7fff, 0x7fff, + 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x8000, 0x8000, + 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, + 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, + 0x8000, 0x8000, 0x8000, 0x8000, 0x8001, 0x8001, 0x8001, 0x8001, 0x8001, 0x8001, 0x8001, 0x8001, 0x8001, 0x8002, + 0x8002, 0x8002, 0x8002, 0x8003, 0x8003, 0x8003, 0x8004, 0x8004, 0x8005, 0x8006, 0x8006, 0x8007, 0x8008, 0x8009, + 0x800a, 0x800c, 0x800d, 0x800f, 0x8011, 0x8013, 0x8016, 0x8019, 0x801c, 0x8020, 0x8024, 0x8029, 0x802f, 0x8035, + 0x803c, 0x8044, 0x804d, 0x8057, 0x8062, 0x806f, 0x807e, 0x808f, 0x80a2, 0x80b8, 0x80d0, 0x80ec, 0x810b, 0x812e, + 0x8156, 0x8183, 0x81b7, 0x81f1, 0x8232, 0x827c, 0x82d0, 0x832f, 0x839a, 0x8412, +}; diff --git a/components/nmsis/nn/src/NNSupportFunctions/riscv_q7_to_q15_no_shift.c b/components/nmsis/nn/src/NNSupportFunctions/riscv_q7_to_q15_no_shift.c new file mode 100644 index 00000000..ab2aaef5 --- /dev/null +++ b/components/nmsis/nn/src/NNSupportFunctions/riscv_q7_to_q15_no_shift.c @@ -0,0 +1,130 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_q7_to_q15_no_shift.c + * Description: Converts the elements of the Q7 vector to Q15 vector without left-shift + * + * $Date: May 29, 2020 + * $Revision: V.1.0.2 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "riscv_nnsupportfunctions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup nndata_convert + * @{ + */ + +/** + * @brief Converts the elements of the Q7 vector to Q15 vector without left-shift + * @param[in] *pSrc points to the Q7 input vector + * @param[out] *pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + * + * \par Description: + * + * The equation used for the conversion process is: + * + * 
+ * 	pDst[n] = (q15_t) pSrc[n];   0 <= n < blockSize.
+ *
+ * + */ + +void riscv_q7_to_q15_no_shift(const q7_t *pSrc, q15_t *pDst, uint32_t blockSize) +{ + const q7_t *pIn = pSrc; + +#if defined (RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + size_t l; + q15_t *pCnt = pDst; + const q7_t *pV = pSrc; + + for (; (l = vsetvl_e8m4(blkCnt)) > 0; blkCnt -= l) { + vse16_v_i16m8 (pCnt, vwadd_vx_i16m8(vle8_v_i8m4(pV, l),0, l), l); + pV += l; + pCnt += l; + } +#else + uint32_t blkCnt; +#if defined(RISCV_MATH_DSP) + q31_t in; + q31_t in1, in2; + q31_t out1, out2; + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. */ + while (blkCnt > 0u) + { + in = riscv_nn_read_q7x4_ia(&pIn); + + /* rotatate in by 8 and extend two q7_t values to q15_t values */ + in1 = __SXTB16(__ROR((uint32_t)in, 8)); + + /* extend remaining two q7_t values to q15_t values */ + in2 = __SXTB16(in); + + out2 = (int32_t)__PKHTB(in1, in2, 16); + out1 = (int32_t)__PKHBT(in2, in1, 16); + riscv_nn_write_q15x2_ia(&pDst, out1); + riscv_nn_write_q15x2_ia(&pDst, out2); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + +#else + + /* Run the below code for RISC-V Core without DSP */ + + /* Loop over blockSize number of values */ + blkCnt = blockSize; + +#endif + + while (blkCnt > 0u) + { + /* convert from q7 to q15 and then store the results in the destination buffer */ + *pDst++ = (q15_t)*pIn++; + + /* Decrement the loop counter */ + blkCnt--; + } +#endif /*defined (RISCV_VECTOR)*/ +} + +/** + * @} end of nndata_convert group + */ diff --git a/components/nmsis/nn/src/NNSupportFunctions/riscv_q7_to_q15_reordered_no_shift.c b/components/nmsis/nn/src/NNSupportFunctions/riscv_q7_to_q15_reordered_no_shift.c new file mode 100644 index 00000000..02d2599d --- /dev/null +++ b/components/nmsis/nn/src/NNSupportFunctions/riscv_q7_to_q15_reordered_no_shift.c @@ -0,0 +1,130 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_q7_to_q15_reordered_no_shift.c + * Description: Converts the elements of the Q7 vector to reordered Q15 vector without left-shift + * + * $Date: May 29, 2020 + * $Revision: V.1.0.1 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "riscv_nnsupportfunctions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup nndata_convert + * @{ + */ + +/** + * @brief Converts the elements of the Q7 vector to reordered Q15 vector without left-shift + * @param[in] *pSrc points to the Q7 input vector + * @param[out] *pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + * + * @details + * + * This function does the q7 to q15 expansion with re-ordering + * + * 
+ *                          |   A1   |   A2   |   A3   |   A4   |
+ *
+ *                           0      7 8     15 16    23 24    31
+ *
+ * + * is converted into: + * + * 
+ *  |       A1       |       A3       |   and  |       A2       |       A4       |
+ *
+ *   0             15 16            31          0             15 16            31
+ *
+ * + * + * This looks strange but is natural considering how sign-extension is done at + * assembly level. + * + * The expansion of other other oprand will follow the same rule so that the end + * results are the same. + * + * The tail (i.e., last (N % 4) elements) will still be in original order. + * + */ + +void riscv_q7_to_q15_reordered_no_shift(const q7_t *pSrc, q15_t *pDst, uint32_t blockSize) +{ + const q7_t *pIn = pSrc; /* Src pointer */ + uint32_t blkCnt; /* loop counter */ + + q31_t in; + q31_t in1, in2; + + /* Run the below code for RISC-V Core with DSP enabled */ + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0u) + { + /* C = (q15_t) A << 8 */ + /* convert from q7 to q15 and then store the results in the destination buffer */ + in = riscv_nn_read_q7x4_ia(&pIn); + + /* rotatate in by 8 and extend two q7_t values to q15_t values */ + in1 = __SXTB16(__ROR((uint32_t)in, 8)); + + /* extend remainig two q7_t values to q15_t values */ + in2 = __SXTB16(in); + + *__SIMD32(pDst)++ = in2; + *__SIMD32(pDst)++ = in1; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + + + while (blkCnt > 0u) + { + /* C = (q15_t) A << 8 */ + /* convert from q7 to q15 and then store the results in the destination buffer */ + *pDst++ = (q15_t)*pIn++; + + /* Decrement the loop counter */ + blkCnt--; + } +} + +/** + * @} end of q7_to_x group + */ diff --git a/components/nmsis/nn/src/NNSupportFunctions/riscv_q7_to_q15_reordered_with_offset.c b/components/nmsis/nn/src/NNSupportFunctions/riscv_q7_to_q15_reordered_with_offset.c new file mode 100644 index 00000000..76fd2565 --- /dev/null +++ b/components/nmsis/nn/src/NNSupportFunctions/riscv_q7_to_q15_reordered_with_offset.c @@ -0,0 +1,101 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_q7_to_q15_reordered_with_offset.c + * Description: Converts the elements of the Q7 vector to a reordered Q15 vector with an added offset. The re-ordering + * is a signature of sign extension intrinsic(DSP extension). + * + * $Date: May 29, 2020 + * $Revision: V.2.0.3 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "riscv_nnsupportfunctions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup nndata_convert + * @{ + */ + +/** + * @brief Converts the elements of the Q7 vector to a reordered Q15 vector with an added offset. + * + * @note Refer header file for details. + * + */ + +void riscv_q7_to_q15_reordered_with_offset(const q7_t *src, q15_t *dst, uint32_t block_size, q15_t offset) +{ + +#if defined(RISCV_MATH_DSP) + uint32_t block_cnt; + /* Run the below code for cores that support SIMD instructions */ + q31_t in_q7x4; + q31_t out_q15x2_1; + q31_t out_q15x2_2; + + /*loop unrolling */ + block_cnt = block_size >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. */ + const q31_t offset_q15x2 = (q31_t)__PKHBT(offset, offset, 16); + while (block_cnt > 0u) + { + /* convert from q7 to q15 and then store the results in the destination buffer */ + in_q7x4 = riscv_nn_read_q7x4_ia(&src); + + /* Extract and sign extend each of the four q7 values to q15 */ + out_q15x2_1 = __SXTAB16(offset_q15x2, __ROR((uint32_t)in_q7x4, 8)); + out_q15x2_2 = __SXTAB16(offset_q15x2, in_q7x4); + + riscv_nn_write_q15x2_ia(&dst, out_q15x2_2); + riscv_nn_write_q15x2_ia(&dst, out_q15x2_1); + + block_cnt--; + } + /* Handle left over samples */ + block_cnt = block_size % 0x4u; + + while (block_cnt > 0u) + { + *dst++ = (q15_t)*src++ + offset; + + /* Decrement the loop counter */ + block_cnt--; + } +#else + (void)src; + (void)dst; + (void)block_size; + (void)offset; + /* Not available */ +#endif +} + +/** + * @} end of nndata_convert group + */ diff --git a/components/nmsis/nn/src/NNSupportFunctions/riscv_q7_to_q15_with_offset.c b/components/nmsis/nn/src/NNSupportFunctions/riscv_q7_to_q15_with_offset.c new file mode 100644 index 00000000..532cdb62 --- /dev/null +++ b/components/nmsis/nn/src/NNSupportFunctions/riscv_q7_to_q15_with_offset.c @@ -0,0 +1,101 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in_q7x4 compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in_q7x4 writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_q7_to_q15_with_offset.c + * Description: Converts the elements of the Q7 vector to Q15 vector with an added offset + * + * $Date: March 3, 2020 + * $Revision: V.2.0.2 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "riscv_nnsupportfunctions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup nndata_convert + * @{ + */ + +void riscv_q7_to_q15_with_offset(const q7_t *src, q15_t *dst, uint32_t block_size, q15_t offset) +{ + int block_cnt; +#if defined (RISCV_VECTOR) + uint32_t blkCnt = block_size; /* Loop counter */ + size_t l; + q15_t *pCnt = dst; + const q7_t *pV = src; + + for (; (l = vsetvl_e8m4(blkCnt)) > 0; blkCnt -= l) { + vse16_v_i16m8 (pCnt, vadd_vx_i16m8(vwadd_vx_i16m8(vle8_v_i8m4(pV, l), 0, l), offset, l), l); + pV += l; + pCnt += l; + } +#else +#if defined(RISCV_MATH_DSP) + /* Run the below code for cores that support SIMD instructions */ + q31_t in_q7x4; + q31_t in_q15x2_1; + q31_t in_q15x2_2; + + /*loop unrolling */ + block_cnt = block_size >> 2; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. */ + const q31_t offset_q15x2 = __RV_PKBB16(offset, offset); + while (block_cnt > 0) + { + in_q7x4 = riscv_nn_read_q7x4_ia(&src); + + in_q15x2_1 = __RV_ADD16(offset_q15x2, __RV_SUNPKD810(in_q7x4)); + in_q15x2_2 = __RV_ADD16(offset_q15x2, __RV_SUNPKD832(in_q7x4)); + + riscv_nn_write_q15x2_ia(&dst, in_q15x2_1); + riscv_nn_write_q15x2_ia(&dst, in_q15x2_2); + + block_cnt--; + } + /* Handle left over samples */ + block_cnt = block_size % 0x4; + +#else + /* Run the below code for RISC-V Core without DSP */ + /* Loop over block_size number of values */ + block_cnt = block_size; +#endif + + while (block_cnt > 0) + { + *dst++ = (q15_t)*src++ + offset; + + /* Decrement the loop counter */ + block_cnt--; + } +#endif /*defined (RISCV_VECTOR)*/ +} +/** + * @} end of nndata_convert group + */ diff --git a/components/nmsis/nn/src/NNSupportFunctions/riscv_q7_to_q7_no_shift.c b/components/nmsis/nn/src/NNSupportFunctions/riscv_q7_to_q7_no_shift.c new file mode 100644 index 00000000..c1d08bfb --- /dev/null +++ b/components/nmsis/nn/src/NNSupportFunctions/riscv_q7_to_q7_no_shift.c @@ -0,0 +1,120 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_q7_to_q7_no_shift.c + * Description: Converts the elements of the Q7 vector to Q7 vector without left-shift + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "riscv_nnsupportfunctions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup nndata_convert + * @{ + */ + +/** + * @brief Converts the elements of the Q7 vector to Q7 vector without left-shift + * @param[in] *pSrc points to the Q7 input vector + * @param[out] *pDst points to the Q7 output vector + * @param[in] blockSize length of the input vector + * @return none. + * + * \par Description: + * + * The equation used for the conversion process is: + * + * 
+ * 	pDst[n] = (q15_t) pSrc[n];   0 <= n < blockSize.
+ *
+ * + */ + +void riscv_q7_to_q7_no_shift(const q7_t * pSrc, q7_t * pDst, uint32_t blockSize) +{ + const q7_t *pIn = pSrc; +#if defined (RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + size_t l; + vint8m8_t vx, vy; + + for (; (l = vsetvl_e8m8(blkCnt)) > 0; blkCnt -= l) { + vse8_v_i8m8 (pDst, vle8_v_i8m8(pIn, l), l); + pIn += l; + pDst += l; + } +#else + uint32_t blkCnt; +#if defined(RISCV_MATH_LOOPUNROLL) && defined(RISCV_MATH_DSP) + q31_t in; + q31_t in1, in2; + q31_t out1, out2; + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. */ + while (blkCnt > 0u) + { + //in = riscv_nn_read_q7x4_ia(&pIn); + in = read_q7x4_ia((q7_t **)&pIn); + write_q7x4_ia(&pDst, in); + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + +#else + + /* Run the below code for RISC-V Core without DSP */ + + /* Loop over blockSize number of values */ + blkCnt = blockSize; + +#endif + + while (blkCnt > 0u) + { + /* convert from q7 to q7 and then store the results in the destination buffer */ + + *pDst++ = *pIn++; + + /* Decrement the loop counter */ + blkCnt--; + } +#endif /*defined (RISCV_VECTOR)*/ +} + +/** + * @} end of nndata_convert group + */ diff --git a/components/nmsis/nn/src/NNSupportFunctions/riscv_q7_to_q7_reordered_no_shift.c b/components/nmsis/nn/src/NNSupportFunctions/riscv_q7_to_q7_reordered_no_shift.c new file mode 100644 index 00000000..9b3fd75a --- /dev/null +++ b/components/nmsis/nn/src/NNSupportFunctions/riscv_q7_to_q7_reordered_no_shift.c @@ -0,0 +1,137 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_q7_to_q15_reordered_no_shift.c + * Description: Converts the elements of the Q7 vector to reordered Q15 vector without left-shift + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "riscv_nnsupportfunctions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup nndata_convert + * @{ + */ + +/** + * @brief Converts the elements of the Q7 vector to reordered Q7 vector without left-shift + * @param[in] *pSrc points to the Q7 input vector + * @param[out] *pDst points to the Q7 output vector + * @param[in] blockSize length of the input vector + * @return none. + * + * @details + * + * This function does the q7 to q7 expansion with re-ordering + * + * 
+ *                          |   A1   |   A2   |   A3   |   A4   |
+ *
+ *                           0      7 8     15 16    23 24    31
+ *
+ * + * is converted into: + * + * 
+ *  |       A1       |       A3       |   and  |       A2       |       A4       |
+ *
+ *   0             15 16            31          0             15 16            31
+ *
+ * + * + * This looks strange but is natural considering how sign-extension is done at + * assembly level. + * + * The expansion of other other oprand will follow the same rule so that the end + * results are the same. + * + * The tail (i.e., last (N % 4) elements) will still be in original order. + * + */ + +void riscv_q7_to_q7_reordered_no_shift(const q7_t * pSrc, q7_t * pDst, uint32_t blockSize) +{ + const q7_t *pIn = pSrc; /* Src pointer */ + +#if defined(RISCV_VECTOR) + uint32_t blkCnt = blockSize; /* Loop counter */ + size_t l; + vint8m8_t vx, vy; + + for (; (l = vsetvl_e8m8(blkCnt)) > 0; blkCnt -= l) { + vse8_v_i8m8 (pDst, vle8_v_i8m8(pIn, l), l); + pIn += l; + pDst += l; + } + +#else + uint32_t blkCnt; /* loop counter */ + q31_t in; + //q31_t in1, in2; + q31_t out; + /* Run the below code for RISC-V Core with DSP enabled */ + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0u) + { + /* C = (q15_t) A << 8 */ + /* convert from q7 to q7 and then store the results in the destination buffer */ + in = *__SIMD32(pIn)++; + + *__SIMD32(pDst)++ = in; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + + + while (blkCnt > 0u) + { + /* C = (q15_t) A << 8 */ + /* convert from q7 to q7 and then store the results in the destination buffer */ + *pDst++ = (q7_t) * pIn++; + + /* Decrement the loop counter */ + blkCnt--; + } +#endif /* defined(RISCV_VECTOR) */ +} + +/** + * @} end of q7_to_x group + */ diff --git a/components/nmsis/nn/src/PoolingFunctions/riscv_avgpool_s8.c b/components/nmsis/nn/src/PoolingFunctions/riscv_avgpool_s8.c new file mode 100644 index 00000000..3fa0c7be --- /dev/null +++ b/components/nmsis/nn/src/PoolingFunctions/riscv_avgpool_s8.c @@ -0,0 +1,211 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_avgpool_s8.c + * Description: Pooling function implementations + * + * $Date: 01. March 2021 + * $Revision: V.2.0.4 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "riscv_nnfunctions.h" +#include "riscv_nnsupportfunctions.h" + +#if defined(RISCV_MATH_DSP) + +static void scale_q31_to_q7_and_clamp(const q31_t *buffer, + q7_t *target, + int32_t length, + const int32_t count, + const int act_min, + const int act_max) +{ + const int half_count = count / 2; + for (int i = 0; i < length; i++) + { + int32_t sum = buffer[i] > 0 ? (buffer[i] + half_count) : (buffer[i] - half_count); + sum = sum / count; + sum = MAX(sum, act_min); + sum = MIN(sum, act_max); + + target[i] = (q7_t)sum; + } +} +#endif + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Pooling + * @{ + */ + +/* + * s8 average pooling function + * + * Refer to header file for details. + * + */ + +riscv_status riscv_avgpool_s8(const nmsis_nn_context *ctx, + const nmsis_nn_pool_params *pool_params, + const nmsis_nn_dims *input_dims, + const q7_t *src, + const nmsis_nn_dims *filter_dims, + const nmsis_nn_dims *output_dims, + q7_t *dst) +{ + const int32_t input_y = input_dims->h; + const int32_t input_x = input_dims->w; + const int32_t output_y = output_dims->h; + const int32_t output_x = output_dims->w; + const int32_t stride_y = pool_params->stride.h; + const int32_t stride_x = pool_params->stride.w; + const int32_t kernel_y = filter_dims->h; + const int32_t kernel_x = filter_dims->w; + const int32_t pad_y = pool_params->padding.h; + const int32_t pad_x = pool_params->padding.w; + const int32_t act_min = pool_params->activation.min; + const int32_t act_max = pool_params->activation.max; + const int32_t ch_src = input_dims->c; + q31_t *buffer = (q31_t *)ctx->buf; + +#if defined(RISCV_MATH_DSP) + + /* Run the following code for CPU's with DSP extension + */ + for (int i_y = 0, idx_y = -pad_y; i_y < output_y; idx_y += stride_y, i_y++) + { + for (int i_x = 0, idx_x = -pad_x; i_x < output_x; idx_x += stride_x, i_x++) + { + /* Condition for kernel start dimension: + (base_idx_ + kernel__start) >= 0 */ + const int32_t kernel_y_start = MAX(0, -idx_y); + const int32_t kernel_x_start = MAX(0, -idx_x); + + /* Condition for kernel end dimension: + (base_idx_ + kernel__end) < dim_src_ */ + const int32_t kernel_y_end = MIN(kernel_y, input_y - idx_y); + const int32_t kernel_x_end = MIN(kernel_x, input_x - idx_x); + + int count = 0; + + for (int k_y = kernel_y_start; k_y < kernel_y_end; k_y++) + { + for (int k_x = kernel_x_start; k_x < kernel_x_end; k_x++) + { + const q7_t *start = src + ch_src * (k_x + idx_x + (k_y + idx_y) * input_x); + + if (count == 0) + { + for (int i = 0; i < ch_src; i++) + { + buffer[i] = start[i]; + } + } + else + { + for (int i = 0; i < ch_src; i++) + { + buffer[i] = __QADD(start[i], buffer[i]); + } + } + count++; + } + } + + // Prevent static code issue DIVIDE_BY_ZERO. + if (count == 0) + { + return RISCV_MATH_ARGUMENT_ERROR; + } + + scale_q31_to_q7_and_clamp(buffer, dst, ch_src, count, act_min, act_max); + dst += ch_src; + } + } +#else + + /* Reference C code adapted from NMSIS-NN riscv_avepool_q7_HWC. + */ + (void)buffer; + int16_t i_ch_in, i_x, i_y; + int16_t k_x, k_y; + + for (i_y = 0; i_y < output_y; i_y++) + { + for (i_x = 0; i_x < output_x; i_x++) + { + for (i_ch_in = 0; i_ch_in < ch_src; i_ch_in++) + { + int sum = 0; + int count = 0; + for (k_y = i_y * stride_y - pad_y; k_y < i_y * stride_y - pad_y + kernel_y; k_y++) + { + for (k_x = i_x * stride_x - pad_x; k_x < i_x * stride_x - pad_x + kernel_x; k_x++) + { + if (k_y >= 0 && k_x >= 0 && k_y < input_y && k_x < input_x) + { + sum += src[i_ch_in + ch_src * (k_x + k_y * input_x)]; + count++; + } + } + } + + // Prevent static code issue DIVIDE_BY_ZERO. + if (count == 0) + { + return RISCV_MATH_ARGUMENT_ERROR; + } + + sum = sum > 0 ? (sum + count / 2) / count : (sum - count / 2) / count; + sum = MAX(sum, act_min); + sum = MIN(sum, act_max); + + dst[i_ch_in + ch_src * (i_x + i_y * output_x)] = sum; + } + } + } + +#endif + return RISCV_MATH_SUCCESS; +} + + +int32_t riscv_avgpool_s8_get_buffer_size(const int output_x, const int ch_src) +{ + (void)output_x; + +#if defined(RISCV_MATH_DSP) + return (ch_src * sizeof(int32_t)); +#else + (void)ch_src; + return 0; +#endif +} +/** + * @} end of Pooling group + */ diff --git a/components/nmsis/nn/src/PoolingFunctions/riscv_max_pool_s8.c b/components/nmsis/nn/src/PoolingFunctions/riscv_max_pool_s8.c new file mode 100644 index 00000000..150738ba --- /dev/null +++ b/components/nmsis/nn/src/PoolingFunctions/riscv_max_pool_s8.c @@ -0,0 +1,224 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_max_pool_s8.c + * Description: Pooling function implementations + * + * $Date: 19. Februari 2021 + * $Revision: V.2.0.2 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "riscv_nnfunctions.h" +#include "riscv_nnsupportfunctions.h" + +static void compare_and_replace_if_larger_q7(q7_t *base, const q7_t *target, int32_t length) +{ +#if defined (RISCV_VECTOR) + q7_t *dst = base; + const q7_t *src = target; + uint32_t blkCnt = length; /* Loop counter */ + size_t l; + vint8m8_t vx, vy; + + for (; (l = vsetvl_e8m8(blkCnt)) > 0; blkCnt -= l) { + vse8_v_i8m8(dst, vmax_vv_i8m8(vle8_v_i8m8(src, l), vle8_v_i8m8(dst, l), l), l); + src += l; + dst += l; + } +#else + q7_t *dst = base; + const q7_t *src = target; + union riscv_nnword ref_max; + union riscv_nnword comp_max; + int32_t cnt = length >> 2; + + while (cnt > 0l) + { + ref_max.word = riscv_nn_read_q7x4(dst); + comp_max.word = riscv_nn_read_q7x4_ia(&src); + + if (comp_max.bytes[0] > ref_max.bytes[0]) + { + ref_max.bytes[0] = comp_max.bytes[0]; + } + if (comp_max.bytes[1] > ref_max.bytes[1]) + { + ref_max.bytes[1] = comp_max.bytes[1]; + } + if (comp_max.bytes[2] > ref_max.bytes[2]) + { + ref_max.bytes[2] = comp_max.bytes[2]; + } + if (comp_max.bytes[3] > ref_max.bytes[3]) + { + ref_max.bytes[3] = comp_max.bytes[3]; + } + + write_q7x4_ia(&dst, ref_max.word); + + cnt--; + } + + cnt = length & 0x3; + while (cnt > 0l) + { + if (*src > *dst) + { + *dst = *src; + } + dst++; + src++; + cnt--; + } +#endif /*defined (RISCV_VECTOR)*/ +} + +static void clamp_output(q7_t *source, int32_t length, const int32_t act_min, const int32_t act_max) +{ +#if defined (RISCV_VECTOR) + uint32_t blkCnt = length; /* Loop counter */ + size_t l; + vint8m8_t vx, vy; + + for (; (l = vsetvl_e8m8(blkCnt)) > 0; blkCnt -= l) { + vse8_v_i8m8(source, vmax_vx_i8m8(vmin_vx_i8m8(vle8_v_i8m8(source, l), act_max, l),act_min, l), l); + source += l; + } +#else + union riscv_nnword in; + int32_t cnt = length >> 2; + + while (cnt > 0l) + { + in.word = riscv_nn_read_q7x4(source); + + in.bytes[0] = MAX(in.bytes[0], act_min); + in.bytes[0] = MIN(in.bytes[0], act_max); + in.bytes[1] = MAX(in.bytes[1], act_min); + in.bytes[1] = MIN(in.bytes[1], act_max); + in.bytes[2] = MAX(in.bytes[2], act_min); + in.bytes[2] = MIN(in.bytes[2], act_max); + in.bytes[3] = MAX(in.bytes[3], act_min); + in.bytes[3] = MIN(in.bytes[3], act_max); + + write_q7x4_ia(&source, in.word); + cnt--; + } + + cnt = length & 0x3; + while (cnt > 0l) + { + int32_t comp = *source; + comp = MAX(comp, act_min); + comp = MIN(comp, act_max); + *source++ = (int8_t)comp; + cnt--; + } +#endif /*defined (RISCV_VECTOR)*/ +} + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Pooling + * @{ + */ + +/* + * Optimized s8 max pooling function + * + * Refer to header file for details. + * + */ + +riscv_status riscv_max_pool_s8(const nmsis_nn_context *ctx, + const nmsis_nn_pool_params *pool_params, + const nmsis_nn_dims *input_dims, + const q7_t *src, + const nmsis_nn_dims *filter_dims, + const nmsis_nn_dims *output_dims, + q7_t *dst) +{ + const int32_t input_y = input_dims->h; + const int32_t input_x = input_dims->w; + const int32_t output_y = output_dims->h; + const int32_t output_x = output_dims->w; + const int32_t stride_y = pool_params->stride.h; + const int32_t stride_x = pool_params->stride.w; + const int32_t kernel_y = filter_dims->h; + const int32_t kernel_x = filter_dims->w; + const int32_t pad_y = pool_params->padding.h; + const int32_t pad_x = pool_params->padding.w; + const int32_t act_min = pool_params->activation.min; + const int32_t act_max = pool_params->activation.max; + const int32_t channel_in = input_dims->c; + (void)ctx; + q7_t *dst_base = dst; + + for (int i_y = 0, base_idx_y = -pad_y; i_y < output_y; base_idx_y += stride_y, i_y++) + { + for (int i_x = 0, base_idx_x = -pad_x; i_x < output_x; base_idx_x += stride_x, i_x++) + { + /* Condition for kernel start dimension: (base_idx_ + kernel__start) >= 0 */ + const int32_t ker_y_start = MAX(0, -base_idx_y); + const int32_t ker_x_start = MAX(0, -base_idx_x); + + /* Condition for kernel end dimension: (base_idx_ + kernel__end) < dim_src_ */ + const int32_t kernel_y_end = MIN(kernel_y, input_y - base_idx_y); + const int32_t kernel_x_end = MIN(kernel_x, input_x - base_idx_x); + + int count = 0; + + for (int k_y = ker_y_start; k_y < kernel_y_end; k_y++) + { + for (int k_x = ker_x_start; k_x < kernel_x_end; k_x++) + { + const q7_t *start = src + channel_in * (k_x + base_idx_x + (k_y + base_idx_y) * input_x); + + if (count == 0) + { + memcpy(dst, start, channel_in); + count++; + } + else + { + compare_and_replace_if_larger_q7(dst, start, channel_in); + } + } + } + /* 'count' is expected to be non-zero here. */ + dst += channel_in; + } + } + + clamp_output(dst_base, output_x * output_y * channel_in, act_min, act_max); + + return RISCV_MATH_SUCCESS; +} + +/** + * @} end of Pooling group + */ diff --git a/components/nmsis/nn/src/PoolingFunctions/riscv_pool_q7_HWC.c b/components/nmsis/nn/src/PoolingFunctions/riscv_pool_q7_HWC.c new file mode 100644 index 00000000..744acbfc --- /dev/null +++ b/components/nmsis/nn/src/PoolingFunctions/riscv_pool_q7_HWC.c @@ -0,0 +1,516 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_pool_q7_HWC.c + * Description: Pooling function implementations + * + * $Date: 09. October 2020 + * $Revision: V.1.0.1 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ +#include "riscv_nnfunctions.h" +#include "riscv_nnsupportfunctions.h" +#if defined (RISCV_VECTOR) +static void compare_and_replace_if_larger_q7(q7_t * base, // base data + const q7_t * target, // compare target + const uint16_t length // data length + ) +{ + q7_t *pIn = base; + const q7_t *pCom = target; + uint32_t blkCnt = length; /* Loop counter */ + size_t l; + vint8m8_t valuea,valueb; + + for (; (l = vsetvl_e8m8(blkCnt)) > 0; blkCnt -= l) { + valuea = vle8_v_i8m8(pIn, l); + valueb = vle8_v_i8m8(pCom, l); + vse8_v_i8m8 (pIn, vmax_vv_i8m8(valuea, valueb, l), l); + pIn += l; + pCom += l; + } +} + +static void buffer_scale_back_q7_to_q7(q7_t * buffer, q7_t * target, uint16_t length, uint16_t scale) +{ + int i; + + for (i = 0; i < length; i++) + { + target[i] = (q7_t) (buffer[i] / scale); + } +} + +#else +#if defined (RISCV_MATH_DSP) + +/** + * @brief A few utility functions used by pooling functions + * + * + */ + +static void buffer_scale_back_q15_to_q7(q15_t *buffer, q7_t *target, uint16_t length, uint16_t scale) +{ + int i; + + for (i = 0; i < length; i++) + { + target[i] = (q7_t)(buffer[i] / scale); + } +} + +static void buffer_scale_back_q7_to_q7(q7_t * buffer, q7_t * target, uint16_t length, uint16_t scale) +{ + int i; + + for (i = 0; i < length; i++) + { + target[i] = (q7_t) (buffer[i] / scale); + } +} + +static void compare_and_replace_if_larger_q7(q7_t * base, // base data + const q7_t * target, // compare target + const uint16_t length // data length + ) +{ + q7_t *pIn = base; + const q7_t *pCom = target; +#if defined (RISCV_VECTOR) + uint32_t blkCnt = length; /* Loop counter */ + size_t l; + vint8m8_t valuea,valueb; + + for (; (l = vsetvl_e8m8(blkCnt)) > 0; blkCnt -= l) { + valuea = vle8_v_i8m8(pIn, l); + valueb = vle8_v_i8m8(pCom, l); + vse8_v_i8m8 (pIn, vmax_vv_i8m8(valuea, valueb, l), l); + pIn += l; + pCom += l; + } +#else + union riscv_nnword in; + union riscv_nnword com; + uint16_t cnt = length >> 2; + + while (cnt > 0u) + { + in.word = *__SIMD32(pIn); + com.word = *__SIMD32(pCom)++; + //__SMAX8(in.word,com.word); + // if version + /* if (com.bytes[0] > in.bytes[0]) + in.bytes[0] = com.bytes[0]; + if (com.bytes[1] > in.bytes[1]) + in.bytes[1] = com.bytes[1]; + if (com.bytes[2] > in.bytes[2]) + in.bytes[2] = com.bytes[2]; + if (com.bytes[3] > in.bytes[3]) + in.bytes[3] = com.bytes[3];*/ + *__SIMD32(pIn)++ = __RV_SMAX8(in.word,com.word); + ///*__SIMD32(pIn)++ = in.word; + + cnt--; + } + + cnt = length & 0x3; + while (cnt > 0u) + { + if (*pCom > *pIn) + { + *pIn = *pCom; + } + pIn++; + pCom++; + cnt--; + } +#endif /*defined (RISCV_VECTOR)*/ +} + +static void accumulate_q7_to_q15(q15_t *base, q7_t *target, const uint16_t length) +{ + q15_t *pCnt = base; + q7_t *pV = target; + q31_t v1, v2, vo1, vo2; + uint16_t cnt = length >> 2; + q31_t in; + + while (cnt > 0u) + { + + q31_t value = *__SIMD32(pV)++; + v1 = __SXTB16(__ROR(value, 8)); + v2 = __SXTB16(value); + + vo2 = __RV_PKTT16(v1,v2); + vo1 = __RV_PKBB16(v1,v2); + + + + in = *__SIMD32(pCnt); + *__SIMD32(pCnt)++ = __RV_KADD16(vo1, in); + + in = *__SIMD32(pCnt); + *__SIMD32(pCnt)++ = __RV_KADD16(vo2, in); + + cnt--; + } + cnt = length & 0x3; + while (cnt > 0u) + { + *pCnt++ += *pV++; + cnt--; + } +} + +#endif // RISCV_MATH_DSP +#endif /*defined (RISCV_VECTOR)*/ +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Pooling + * @{ + */ + +/** + * @brief Q7 max pooling function + * @param[in, out] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimention + * @param[in] ch_im_in number of input tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA Not used + * @param[in,out] Im_out pointer to output tensor + * + * @details + * + * The pooling function is implemented as split x-pooling then + * y-pooling. + * + * This pooling function is input-destructive. Input data is undefined + * after calling this function. + * + */ + +void riscv_maxpool_q7_HWC(q7_t *Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const uint16_t dim_im_out, + q7_t *bufferA, + q7_t *Im_out) +{ + (void)bufferA; +#if defined (RISCV_MATH_DSP) || defined (RISCV_VECTOR) + /* Run the following code for RISC-V Core with DSP enabled */ + + int16_t i_x, i_y; + + /* first does the pooling along x axis */ + for (i_y = 0; i_y < dim_im_in; i_y++) + { + + for (i_x = 0; i_x < dim_im_out; i_x++) + { + /* for each output pixel */ + q7_t *target = Im_in + (i_y * dim_im_in + i_x) * ch_im_in; + q7_t *win_start; + q7_t *win_stop; + if (i_x * stride - padding < 0) + { + win_start = target; + } + else + { + win_start = Im_in + (i_y * dim_im_in + i_x * stride - padding) * ch_im_in; + } + + if (i_x * stride - padding + dim_kernel >= dim_im_in) + { + win_stop = Im_in + (i_y * dim_im_in + dim_im_in) * ch_im_in; + } + else + { + win_stop = Im_in + (i_y * dim_im_in + i_x * stride - padding + dim_kernel) * ch_im_in; + } + + /* first step is to copy over initial data */ + riscv_copy_q7(win_start, target, ch_im_in); + /* memmove(target, win_start, ch_im_in); */ + + /* start the max operation from the second part */ + win_start += ch_im_in; + for (; win_start < win_stop; win_start += ch_im_in) + { + compare_and_replace_if_larger_q7(target, win_start, ch_im_in); + } + } + } + + /* then does the pooling along y axis */ + for (i_y = 0; i_y < dim_im_out; i_y++) + { + + /* for each output row */ + q7_t *target = Im_out + i_y * dim_im_out * ch_im_in; + q7_t *row_start; + q7_t *row_end; + /* setting the starting row */ + if (i_y * stride - padding < 0) + { + row_start = Im_in; + } + else + { + row_start = Im_in + (i_y * stride - padding) * dim_im_in * ch_im_in; + } + /* setting the stopping row */ + if (i_y * stride - padding + dim_kernel >= dim_im_in) + { + row_end = Im_in + dim_im_in * dim_im_in * ch_im_in; + } + else + { + row_end = Im_in + (i_y * stride - padding + dim_kernel) * dim_im_in * ch_im_in; + } + + /* copy over the first row */ + riscv_copy_q7(row_start, target, dim_im_out * ch_im_in); + /* memmove(target, row_start, dim_im_out * ch_im_in); */ + + /* move over to next row */ + row_start += ch_im_in * dim_im_in; + + for (; row_start < row_end; row_start += dim_im_in * ch_im_in) + { + compare_and_replace_if_larger_q7(target, row_start, dim_im_out * ch_im_in); + } + } + +#else + /* Run the following code as reference implementation for RISC-V Core without DSP */ + int16_t i_ch_in, i_x, i_y; + int16_t k_x, k_y; + + for (i_ch_in = 0; i_ch_in < ch_im_in; i_ch_in++) + { + for (i_y = 0; i_y < dim_im_out; i_y++) + { + for (i_x = 0; i_x < dim_im_out; i_x++) + { + int max = -129; + for (k_y = i_y * stride - padding; k_y < i_y * stride - padding + dim_kernel; k_y++) + { + for (k_x = i_x * stride - padding; k_x < i_x * stride - padding + dim_kernel; k_x++) + { + if (k_y >= 0 && k_x >= 0 && k_y < dim_im_in && k_x < dim_im_in) + { + if (Im_in[i_ch_in + ch_im_in * (k_x + k_y * dim_im_in)] > max) + { + max = Im_in[i_ch_in + ch_im_in * (k_x + k_y * dim_im_in)]; + } + } + } + } + Im_out[i_ch_in + ch_im_in * (i_x + i_y * dim_im_out)] = max; + } + } + } + +#endif /* RISCV_MATH_DSP */ +} + +/** + * @brief Q7 average pooling function + * @param[in,out] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimention + * @param[in] ch_im_in number of input tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] Im_out pointer to output tensor + * + * @details + * + * Buffer size: + * + * bufferA size: 2*dim_im_out*ch_im_in + * + * The pooling function is implemented as split x-pooling then + * y-pooling. + * + * This pooling function is input-destructive. Input data is undefined + * after calling this function. + * + */ + +void riscv_avepool_q7_HWC(q7_t *Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const uint16_t dim_im_out, + q7_t *bufferA, + q7_t *Im_out) +{ + +#if defined (RISCV_MATH_DSP) || defined (RISCV_VECTOR) + /* Run the following code for RISC-V Core with DSP enabled */ + + q15_t *buffer = (q15_t *)bufferA; + int16_t i_x, i_y; + int16_t count = 0; + + /* first does the pooling along x axis */ + for (i_y = 0; i_y < dim_im_in; i_y++) + { + + for (i_x = 0; i_x < dim_im_out; i_x++) + { + /* for each output pixel */ + q7_t *target = Im_in + (i_y * dim_im_in + i_x) * ch_im_in; + q7_t *win_start; + q7_t *win_stop; + if (i_x * stride - padding < 0) + { + win_start = target; + } + else + { + win_start = Im_in + (i_y * dim_im_in + i_x * stride - padding) * ch_im_in; + } + + if (i_x * stride - padding + dim_kernel >= dim_im_in) + { + win_stop = Im_in + (i_y * dim_im_in + dim_im_in) * ch_im_in; + } + else + { + win_stop = Im_in + (i_y * dim_im_in + i_x * stride - padding + dim_kernel) * ch_im_in; + } + + /* first step is to copy over initial data */ + riscv_q7_to_q7_no_shift(win_start, (q7_t *)buffer, ch_im_in); + count = 1; + + /* start the max operation from the second part */ + win_start += ch_im_in; + for (; win_start < win_stop; win_start += ch_im_in) + { + riscv_nn_accumulate_q7_to_q7((q7_t *)buffer, win_start, ch_im_in); + count++; + } + buffer_scale_back_q7_to_q7(buffer, target, ch_im_in, count); + // riscv_scale_q7((q7_t *)buffer,(1/ch_im_in),0,target,count); + } + } + + /* then does the pooling along y axis */ + for (i_y = 0; i_y < dim_im_out; i_y++) + { + /* for each output row */ + q7_t *target = Im_out + i_y * dim_im_out * ch_im_in; + q7_t *row_start; + q7_t *row_end; + /* setting the starting row */ + if (i_y * stride - padding < 0) + { + row_start = Im_in; + } + else + { + row_start = Im_in + (i_y * stride - padding) * dim_im_in * ch_im_in; + } + /* setting the stopping row */ + if (i_y * stride - padding + dim_kernel >= dim_im_in) + { + row_end = Im_in + dim_im_in * dim_im_in * ch_im_in; + } + else + { + row_end = Im_in + (i_y * stride - padding + dim_kernel) * dim_im_in * ch_im_in; + } + + /* copy over the first row */ + riscv_q7_to_q7_no_shift(row_start, (q7_t *)buffer, dim_im_out * ch_im_in); + count = 1; + + /* move over to next row */ + row_start += ch_im_in * dim_im_in; + + for (; row_start < row_end; row_start += dim_im_in * ch_im_in) + { + riscv_nn_accumulate_q7_to_q7((q7_t *)buffer, row_start, dim_im_out * ch_im_in); + count++; + } + buffer_scale_back_q7_to_q7(buffer, target, dim_im_out * ch_im_in, count); + // riscv_scale_q7((q7_t *)buffer,ch_im_in,0,target,count); + } + +#else + /* Run the following code as reference implementation for RISC-V Core without DSP */ + + (void)bufferA; + int16_t i_ch_in, i_x, i_y; + int16_t k_x, k_y; + + for (i_ch_in = 0; i_ch_in < ch_im_in; i_ch_in++) + { + for (i_y = 0; i_y < dim_im_out; i_y++) + { + for (i_x = 0; i_x < dim_im_out; i_x++) + { + int sum = 0; + int count = 0; + for (k_y = i_y * stride - padding; k_y < i_y * stride - padding + dim_kernel; k_y++) + { + for (k_x = i_x * stride - padding; k_x < i_x * stride - padding + dim_kernel; k_x++) + { + if (k_y >= 0 && k_x >= 0 && k_y < dim_im_in && k_x < dim_im_in) + { + sum += Im_in[i_ch_in + ch_im_in * (k_x + k_y * dim_im_in)]; + count++; + } + } + } + Im_out[i_ch_in + ch_im_in * (i_x + i_y * dim_im_out)] = sum / count; + } + } + } + +#endif /* RISCV_MATH_DSP */ +} + +/** + * @} end of Pooling group + */ diff --git a/components/nmsis/nn/src/ReshapeFunctions/riscv_reshape_s8.c b/components/nmsis/nn/src/ReshapeFunctions/riscv_reshape_s8.c new file mode 100644 index 00000000..e4a2c52e --- /dev/null +++ b/components/nmsis/nn/src/ReshapeFunctions/riscv_reshape_s8.c @@ -0,0 +1,57 @@ +/* + * Copyright (C) 2010-2019 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_reshape_s8.c + * Description: Reshape a s8 vector + * + * $Date: September 2019 + * $Revision: V.1.0.0 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "riscv_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Reshape + * @{ + */ + +/** + * Basic s8 reshape function. + * + * Refer header file for details. + * + */ + +void riscv_reshape_s8(const int8_t *input, int8_t *output, const uint32_t total_size) +{ + memcpy(output, input, total_size); +} + +/** + * @} end of Reshape group + */ \ No newline at end of file diff --git a/components/nmsis/nn/src/SVDFunctions/riscv_svdf_s8.c b/components/nmsis/nn/src/SVDFunctions/riscv_svdf_s8.c new file mode 100644 index 00000000..e15ca094 --- /dev/null +++ b/components/nmsis/nn/src/SVDFunctions/riscv_svdf_s8.c @@ -0,0 +1,299 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_svdf_s8.c + * Description: S8 basic SVDF layer function + * + * $Date: 15. April 2021 + * $Revision: V.1.5.0 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "riscv_nnfunctions.h" +#include "riscv_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup SVDF + * @{ + */ + +/* + * S8 SVDF layer function for TensorFlow Lite + * + * Refer to header file for details. + * + */ + +riscv_status riscv_svdf_s8(const nmsis_nn_context *input_ctx, + const nmsis_nn_context *output_ctx, + const nmsis_nn_svdf_params *svdf_params, + const nmsis_nn_per_tensor_quant_params *input_quant_params, + const nmsis_nn_per_tensor_quant_params *output_quant_params, + const nmsis_nn_dims *input_dims, + const q7_t *input_data, + const nmsis_nn_dims *state_dims, + q15_t *state_data, + const nmsis_nn_dims *weights_feature_dims, + const q7_t *weights_feature_data, + const nmsis_nn_dims *weights_time_dims, + const q15_t *weights_time_data, + const nmsis_nn_dims *bias_dims, + const q31_t *bias_data, + const nmsis_nn_dims *output_dims, + q7_t *output_data) +{ + (void)bias_dims; + (void)state_dims; + (void)output_dims; + + const q31_t multiplier_in = input_quant_params->multiplier; + const q31_t shift_in = input_quant_params->shift; + const q31_t multiplier_out = output_quant_params->multiplier; + const q31_t shift_2 = output_quant_params->shift; + const int32_t zp_in = svdf_params->input_offset; + const int32_t zp_out = svdf_params->output_offset; + const int32_t in_activation_min = svdf_params->input_activation.min; + const int32_t in_activation_max = svdf_params->input_activation.max; + const int32_t out_activation_min = svdf_params->output_activation.min; + const int32_t out_activation_max = svdf_params->output_activation.max; + const int16_t rank = svdf_params->rank; + + const int32_t input_batches = input_dims->n; + const int32_t input_height = input_dims->h; + const int32_t feature_batches = weights_feature_dims->n; + const int32_t time_batches = weights_time_dims->h; + const int32_t unit_count = feature_batches / rank; + + q31_t *buffer_a = (q31_t *)input_ctx->buf; + q31_t *buffer_b = (q31_t *)output_ctx->buf; + +#if defined(RISCV_VECTOR) + uint32_t blkCnt; /* Loop counter */ + size_t l; + vint16m4_t v_pv1, v_pv2; + vint32m8_t v_a, v_b; + vint32m1_t v_temp; + const q31_t *pA; + const q31_t *pB; + q31_t *pOUT; + l = vsetvl_e32m1(1); + v_temp = vsub_vv_i32m1(v_temp, v_temp, l); +#endif + + memmove((q15_t *)state_data, + (q15_t *)state_data + 1, + (size_t)(input_batches * feature_batches * time_batches * (int32_t)sizeof(int16_t))); + + for (int i_batch = 0; i_batch < input_batches; i_batch++) + { + q15_t *res_ptr = state_data + (time_batches * i_batch * feature_batches) + (time_batches - 1); + const q7_t *weight = weights_feature_data; + const q7_t *input = input_data + i_batch * input_height; + + riscv_status res = riscv_nn_vec_mat_mult_t_svdf_s8(input, + weight, + res_ptr, + -zp_in, + 0, + time_batches, + multiplier_in, + shift_in, + input_height, + feature_batches, + in_activation_min, + in_activation_max); + + if (res != RISCV_MATH_SUCCESS) + { + return res; + } + } + + { + q31_t *ptr_a = buffer_a; + const q15_t *v2 = state_data; + for (int i_batch = 0; i_batch < input_batches; i_batch++) + { + const q15_t *v1 = weights_time_data; + + for (int i_feature_batch = 0; i_feature_batch < feature_batches; i_feature_batch++) + { + *ptr_a = 0; + int32_t sum = 0; +#if defined(RISCV_VECTOR) + blkCnt = time_batches; + for (; (l = vsetvl_e16m4(blkCnt)) > 0; blkCnt -= l) { + v_pv1 = vle16_v_i16m4(v1, l); + v_pv2 = vle16_v_i16m4(v2, l); + v_a = vwmul_vv_i32m8(v_pv1,v_pv2, l); + + sum += vmv_x_s_i32m1_i32(vredsum_vs_i32m8_i32m1(v_temp,v_a,v_temp, l)); + v1 += l; + v2 += l; + } +#else +#if defined(RISCV_MATH_DSP) + int j = 0; + int32_t block_count = time_batches >> 1; + for (int i = 0; i < block_count; i++) + { + j += 2; + q31_t r1 = riscv_nn_read_q15x2_ia(&v1); + q31_t r2 = riscv_nn_read_q15x2_ia(&v2); + + sum = __SMLAD(r1, r2, sum); + } + + // Process the remaining data + for (; j < time_batches; j++) + { + sum += *v1 * *v2; + v1++; + v2++; + } +#else + for (int j = 0; j < time_batches; j++) + { + sum += *v1 * *v2; + v1++; + v2++; + } +#endif +#endif + + *ptr_a = sum; + ptr_a++; + } + } + } + + if (bias_data) + { + if (unit_count == feature_batches) + { + for (int i = 0; i < input_batches; i++) + { + q31_t *output_temp = buffer_b + i * feature_batches; + const q31_t *ptr_a = buffer_a + i * feature_batches; + + const int32_t *bi = bias_data; +#if defined(RISCV_VECTOR) + blkCnt = feature_batches; + pA = ptr_a; + pB = bi; + pOUT = output_temp; + for (; (l = vsetvl_e32m8(blkCnt)) > 0; blkCnt -= l) { + v_a = vle32_v_i32m8(pA, l); + v_b = vle32_v_i32m8(pB, l); + vse32_v_i32m8(pOUT,vadd_vv_i32m8(v_a,v_b, l), l); + + pA += l; + pB += l; + pOUT += l; + } +#else + for (int j = 0; j < feature_batches; j++) + { + output_temp[j] = ptr_a[j] + bi[j]; + } +#endif + } + } + else + { + for (int i_batch = 0; i_batch < input_batches; i_batch++) + { + q31_t *output_data_temp = buffer_b + i_batch * unit_count; + q31_t *ptr_a = buffer_a + i_batch * feature_batches; + + for (int i = 0; i < unit_count; i++) + { + int32_t sum = bias_data[i]; +// May not optimise when rank is low +#if defined(RISCV_VECTOR) + blkCnt = rank; + l = vsetvl_e32m8(blkCnt); + for (; (l = vsetvl_e32m8(blkCnt)) > 0; blkCnt -= l) { + v_b = vle32_v_i32m8(ptr_a, l); + sum += vmv_x_s_i32m1_i32(vredsum_vs_i32m8_i32m1(v_temp,v_b,v_temp, l)); + ptr_a += l; + } +#else + for (int j = 0; j < rank; j++) + { + sum += *ptr_a; + ptr_a++; + } +#endif + output_data_temp[i] = sum; + } + } + } + } + else + { + for (int i_batch = 0; i_batch < input_batches; i_batch++) + { + q31_t *output_data_temp = buffer_b + i_batch * unit_count; + q31_t *ptr_a = buffer_a + i_batch * feature_batches; + + for (int i = 0; i < unit_count; i++) + { + int32_t sum = 0; +// May not optimise when rank is low +#if defined(RISCV_VECTOR) + blkCnt = rank; + l = vsetvl_e32m8(blkCnt); + for (; (l = vsetvl_e32m8(blkCnt)) > 0; blkCnt -= l) { + v_b = vle32_v_i32m8(ptr_a, l); + sum += vmv_x_s_i32m1_i32(vredsum_vs_i32m8_i32m1(v_temp,v_b,v_temp, l)); + ptr_a += l; + } +#else + for (int j = 0; j < rank; j++) + { + sum += *ptr_a; + ptr_a++; + } +#endif + output_data_temp[i] = sum; + } + } + } + + for (int i = 0; i < input_batches * unit_count; i++) + { + output_data[i] = (q7_t)CLAMP( + riscv_nn_requantize(buffer_b[i], multiplier_out, shift_2) + zp_out, out_activation_max, out_activation_min); + } + + return (RISCV_MATH_SUCCESS); +} + +/** + * @} end of SVDF group + */ diff --git a/components/nmsis/nn/src/SoftmaxFunctions/riscv_softmax_q15.c b/components/nmsis/nn/src/SoftmaxFunctions/riscv_softmax_q15.c new file mode 100644 index 00000000..3b16a25f --- /dev/null +++ b/components/nmsis/nn/src/SoftmaxFunctions/riscv_softmax_q15.c @@ -0,0 +1,119 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_softmax_q15.c + * Description: Q15 softmax function + * + * $Date: 09. October 2020 + * $Revision: V.1.0.1 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "riscv_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Softmax + * @{ + */ + +/** + * @brief Q15 softmax function + * @param[in] vec_in pointer to input vector + * @param[in] dim_vec input vector dimention + * @param[out] p_out pointer to output vector + * + * @details + * + * Here, instead of typical e based softmax, we use + * 2-based softmax, i.e.,: + * + * y_i = 2^(x_i) / sum(2^x_j) + * + * The relative output will be different here. + * But mathematically, the gradient will be the same + * with a log(2) scaling factor. + * + */ + +void riscv_softmax_q15(const q15_t *vec_in, const uint16_t dim_vec, q15_t *p_out) +{ + q31_t sum; + int16_t i; + uint8_t shift; + q31_t base; + base = -1 * 0x100000; + for (i = 0; i < dim_vec; i++) + { + if (vec_in[i] > base) + { + base = vec_in[i]; + } + } + + /* we ignore really small values + * anyway, they will be 0 after shrinking + * to q15_t + */ + base = base - 16; + + sum = 0; + + for (i = 0; i < dim_vec; i++) + { + if (vec_in[i] > base) + { + shift = (uint8_t)__USAT(vec_in[i] - base, 5); + sum += 0x1 << shift; + } + } + + /* This is effectively (0x1 << 32) / sum */ + int64_t div_base = 0x100000000LL; + int output_base = (int32_t)(div_base / sum); + + /* Final confidence will be output_base >> ( 17 - (vec_in[i] - base) ) + * so 32768 (0x1<<15) -> 100% confidence when sum = 0x1 << 16, output_base = 0x1 << 16 + * and vec_in[i]-base = 16 + */ + for (i = 0; i < dim_vec; i++) + { + if (vec_in[i] > base) + { + /* Here minimum value of 17+base-vec[i] will be 1 */ + shift = (uint8_t)__USAT(17 + base - vec_in[i], 5); + p_out[i] = (q15_t)__SSAT((output_base >> shift), 16); + } + else + { + p_out[i] = 0; + } + } +} + +/** + * @} end of Softmax group + */ diff --git a/components/nmsis/nn/src/SoftmaxFunctions/riscv_softmax_q7.c b/components/nmsis/nn/src/SoftmaxFunctions/riscv_softmax_q7.c new file mode 100644 index 00000000..5772eed4 --- /dev/null +++ b/components/nmsis/nn/src/SoftmaxFunctions/riscv_softmax_q7.c @@ -0,0 +1,128 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_softmax_q7.c + * Description: Q7 softmax function + * + * $Date: 09. October 2020 + * $Revision: V.1.0.2 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "riscv_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Softmax + * @{ + */ + +/** + * @brief Q7 softmax function + * @param[in] vec_in pointer to input vector + * @param[in] dim_vec input vector dimention + * @param[out] p_out pointer to output vector + * + * @details + * + * Here, instead of typical natural logarithm e based softmax, we use + * 2-based softmax here, i.e.,: + * + * y_i = 2^(x_i) / sum(2^x_j) + * + * The relative output will be different here. + * But mathematically, the gradient will be the same + * with a log(2) scaling factor. + * + */ + +void riscv_softmax_q7(const q7_t *vec_in, const uint16_t dim_vec, q7_t *p_out) +{ + q31_t sum; + int16_t i; + uint8_t shift; + q15_t base; + base = -128; +#if defined(RISCV_VECTOR) + size_t l; + q15_t temp_max; + uint32_t blkCnt; + ptrdiff_t bstride; + vint8m8_t v_x; + vint8m1_t vtemp; + l = vsetvl_e8m1(1); + vtemp = vmv_v_x_i8m1(base, l); + blkCnt = dim_vec; + // base = vec_in[0]; + i = 0; + for (; (l = vsetvl_e8m8(blkCnt)) > 0; blkCnt -= l) { + v_x = vle8_v_i8m8(vec_in+i, l); + i += l; + temp_max = vmv_x_s_i8m1_i8(vredmax_vs_i8m8_i8m1(vtemp, v_x, vtemp, l)); + if(temp_max > base) + base = temp_max; + } +#else + /* We first search for the maximum */ + for (i = 0; i < dim_vec; i++) + { + if (vec_in[i] > base) + { + base = vec_in[i]; + } + } +#endif + + /* + * So the base is set to max-8, meaning + * that we ignore really small values. + * anyway, they will be 0 after shrinking to q7_t. + */ + base = base - (1 << 3); + + sum = 0; + + for (i = 0; i < dim_vec; i++) + { + shift = (uint8_t)__USAT(vec_in[i] - base, 3); + sum += 0x1 << shift; + } + + /* This is effectively (0x1 << 20) / sum */ + int output_base = (1 << 20) / sum; + + for (i = 0; i < dim_vec; i++) + { + + /* Here minimum value of 13+base-vec_in[i] will be 5 */ + shift = (uint8_t)__USAT(13 + base - vec_in[i], 5); + p_out[i] = (q7_t)__SSAT((output_base >> shift), 8); + } +} + +/** + * @} end of Softmax group + */ \ No newline at end of file diff --git a/components/nmsis/nn/src/SoftmaxFunctions/riscv_softmax_s8.c b/components/nmsis/nn/src/SoftmaxFunctions/riscv_softmax_s8.c new file mode 100644 index 00000000..518b7437 --- /dev/null +++ b/components/nmsis/nn/src/SoftmaxFunctions/riscv_softmax_s8.c @@ -0,0 +1,129 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_softmax_s8.c + * Description: S8 softmax function + * + * $Date: 01. March 2021 + * $Revision: V.2.0.2 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "riscv_nnfunctions.h" +#include "riscv_nnsupportfunctions.h" + +#define ACCUM_BITS 12 + + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Softmax + * @{ + */ + +void riscv_softmax_s8(const int8_t *input, + const int32_t num_rows, + const int32_t row_size, + const int32_t mult, + const int32_t shift, + const int32_t diff_min, + int8_t *output) +{ + const int32_t mask = (1 << shift); + + int32_t col = 0; + int32_t row_idx; + +#if defined(RISCV_VECTOR) + uint32_t blkCnt_v; + size_t l; + vint8m8_t v_x, v_y; + int32_t i_a; + vint8m1_t v_temp; + l = vsetvl_e8m1(1); + v_temp = vsub_vv_i8m1(v_temp, v_temp, l); +#endif + + for (row_idx = 0; row_idx < num_rows; ++row_idx) + { + // Find the maximum value in order to ensure numerical stability + int8_t max = *input; + +#if defined(RISCV_VECTOR) + blkCnt_v = row_size - 1; + col = 1; + for (; (l = vsetvl_e8m8(blkCnt_v)) > 0; blkCnt_v -= l) { + v_x = vle8_v_i8m8(input + col, l); + i_a = vmv_x_s_i8m1_i8 (vredmax_vs_i8m8_i8m1(v_temp,v_x,v_temp, l)); + if(i_a > max) + max = i_a; + col += l; + } +#else + for (col = 1; col < row_size; ++col) + { + max = MAX(max, input[col]); + } +#endif + + int32_t diff = 0; + int32_t sum = 0; + + for (col = 0; col < row_size; ++col) + { + diff = input[col] - max; + if (diff >= diff_min) + { + sum += DIV_POW2(EXP_ON_NEG(MUL_SAT(diff * mask, mult)), ACCUM_BITS); + } + } + + const int32_t headroom = __CLZ(sum); + const int32_t bits_over_unit = ACCUM_BITS - headroom + 23; + const int32_t shifted_scale = ONE_OVER1((sum > 0 ? sum << headroom : 0) - (1 << 31)); + + for (col = 0; col < row_size; ++col) + { + diff = input[col] - max; + if (diff >= diff_min) + { + const int32_t res = + DIV_POW2(MUL_SAT(shifted_scale, EXP_ON_NEG(MUL_SAT(diff * mask, mult))), bits_over_unit) - 128; + output[col] = (int8_t)CLAMP(res, (int32_t)127, (int32_t)-128); + } + else + { + output[col] = -128; + } + } + input += row_size; + output += row_size; + } + +} +/** + * @} end of Softmax group + */ diff --git a/components/nmsis/nn/src/SoftmaxFunctions/riscv_softmax_u8.c b/components/nmsis/nn/src/SoftmaxFunctions/riscv_softmax_u8.c new file mode 100644 index 00000000..a09ed75a --- /dev/null +++ b/components/nmsis/nn/src/SoftmaxFunctions/riscv_softmax_u8.c @@ -0,0 +1,127 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_softmax_u8.c + * Description: U8 softmax function + * + * $Date: 09. October 2020 + * $Revision: V.1.0.2 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "riscv_nnfunctions.h" +#include "riscv_nnsupportfunctions.h" + +#define ACCUM_BITS 12 + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Softmax + * @{ + */ +void riscv_softmax_u8(const uint8_t *input, + const int32_t num_rows, + const int32_t row_size, + const int32_t mult, + const int32_t shift, + const int32_t diff_min, + uint8_t *output) +{ + const int32_t mask = (1 << shift); + + int32_t col = 0; + int32_t row_idx; + +#if defined(RISCV_VECTOR) + uint32_t blkCnt_v; + size_t l; + vuint8m8_t v_x, v_y; + int32_t i_a; + vuint8m1_t v_temp; + l = vsetvl_e8m1(1); + v_temp = vsub_vv_u8m1(v_temp, v_temp, l); +#endif + + for(row_idx = 0; row_idx < num_rows; ++row_idx) + { + // Find the maximum value in order to ensure numerical stability + uint8_t max = *input; + +#if defined(RISCV_VECTOR) + blkCnt_v = row_size - 1; + col = 1; + for (; (l = vsetvl_e8m8(blkCnt_v)) > 0; blkCnt_v -= l) { + v_x = vle8_v_u8m8(input + col, l); + i_a = vmv_x_s_u8m1_u8 (vredmaxu_vs_u8m8_u8m1(v_temp,v_x,v_temp, l)); + if(i_a > max) + max = i_a; + col += l; + } +#else + for (col = 1; col < row_size; ++col) + { + max = MAX(max, input[col]); + } +#endif + + int32_t diff = 0; + int32_t sum = 0; + + for (col = 0; col < row_size; ++col) + { + diff = input[col] - max; + if (diff >= diff_min) + { + sum += DIV_POW2(EXP_ON_NEG(MUL_SAT(diff * mask, mult)), ACCUM_BITS); + } + } + + const int32_t headroom = __CLZ((uint32_t)sum); + const int32_t bits_over_unit = ACCUM_BITS - headroom + 23; + const int32_t shifted_scale = ONE_OVER1((sum << headroom) - (1 << 31)); + + for (col = 0; col < row_size; ++col) + { + diff = input[col] - max; + if (diff >= diff_min) + { + const int32_t res = + DIV_POW2(MUL_SAT(shifted_scale, EXP_ON_NEG(MUL_SAT(diff * mask, mult))), bits_over_unit); + output[col] = (uint8_t)CLAMP(res, (int32_t)255, (int32_t)0); + } + else + { + output[col] = 0; + } + } + input += row_size; + output += row_size; + } +} + +/** + * @} end of Softmax group + */ \ No newline at end of file diff --git a/components/nmsis/nn/src/SoftmaxFunctions/riscv_softmax_with_batch_q7.c b/components/nmsis/nn/src/SoftmaxFunctions/riscv_softmax_with_batch_q7.c new file mode 100644 index 00000000..6dde8dc5 --- /dev/null +++ b/components/nmsis/nn/src/SoftmaxFunctions/riscv_softmax_with_batch_q7.c @@ -0,0 +1,75 @@ +/* + * Copyright (C) 2010-2019 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_softmax_with_batch_q7.c + * Description: Q7 softmax function + * + * $Date: 09. October 2020 + * $Revision: V.1.0.1 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "riscv_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Softmax + * @{ + */ + +/** + * @brief Q7 softmax function with batch parameter + * @param[in] vec_in pointer to input vector + * @param[in] nb_batches number of batches + * @param[in] dim_vec input vector dimention + * @param[out] p_out pointer to output vector + * + * @details + * + * Here, instead of typical natural logarithm e based softmax, we use + * 2-based softmax here, i.e.,: + * + * y_i = 2^(x_i) / sum(2^x_j) + * + * The relative output will be different here. + * But mathematically, the gradient will be the same + * with a log(2) scaling factor. + * + */ + +void riscv_softmax_with_batch_q7(const q7_t *vec_in, const uint16_t nb_batches, const uint16_t dim_vec, q7_t *p_out) +{ + for (int i = 0; i < nb_batches; i++) + { + riscv_softmax_q7(vec_in, dim_vec, p_out); + vec_in += dim_vec; + p_out += dim_vec; + } +} + +/** + * @} end of Softmax group + */ diff --git a/examples/dsp/BasicMathFunctions_part1/CMakeLists.txt b/examples/dsp/BasicMathFunctions_part1/CMakeLists.txt new file mode 100644 index 00000000..c48827d3 --- /dev/null +++ b/examples/dsp/BasicMathFunctions_part1/CMakeLists.txt @@ -0,0 +1,5 @@ +set(TARGET_REQUIRED_PRIVATE_INCLUDE ${CMAKE_CURRENT_SOURCE_DIR} ${CMAKE_CURRENT_SOURCE_DIR}/..) +set(TARGET_REQUIRED_SRCS abs.c add.c mult.c dot_prod.c) +set(TARGET_REQUIRED_LIBS nmsis) +set(mains main.c) +generate_bin() diff --git a/examples/dsp/BasicMathFunctions_part1/abs.c b/examples/dsp/BasicMathFunctions_part1/abs.c new file mode 100644 index 00000000..257acae7 --- /dev/null +++ b/examples/dsp/BasicMathFunctions_part1/abs.c @@ -0,0 +1,40 @@ +#include "ref.h" + +void ref_abs_f32(float32_t *pSrc, float32_t *pDst, uint32_t blockSize) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) { + pDst[i] = pSrc[i] < 0 ? -pSrc[i] : pSrc[i]; + } +} + +void ref_abs_q31(q31_t *pSrc, q31_t *pDst, uint32_t blockSize) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) { + pDst[i] = pSrc[i] < 0 ? -pSrc[i] : pSrc[i]; + } +} + +void ref_abs_q15(q15_t *pSrc, q15_t *pDst, uint32_t blockSize) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) { + pDst[i] = pSrc[i] < 0 ? -pSrc[i] : pSrc[i]; + } +} + +void ref_abs_q7(q7_t *pSrc, q7_t *pDst, uint32_t blockSize) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) { + if (pSrc[i] == -128) + pDst[i] = 127; + else + pDst[i] = pSrc[i] < 0 ? -pSrc[i] : pSrc[i]; + } +} diff --git a/examples/dsp/BasicMathFunctions_part1/add.c b/examples/dsp/BasicMathFunctions_part1/add.c new file mode 100644 index 00000000..675d0b43 --- /dev/null +++ b/examples/dsp/BasicMathFunctions_part1/add.c @@ -0,0 +1,38 @@ +#include "ref.h" + +void ref_add_f32(float32_t *pSrcA, float32_t *pSrcB, float32_t *pDst, + uint32_t blockSize) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) { + pDst[i] = pSrcA[i] + pSrcB[i]; + } +} + +void ref_add_q31(q31_t *pSrcA, q31_t *pSrcB, q31_t *pDst, uint32_t blockSize) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) { + pDst[i] = ref_sat_q31((q63_t)pSrcA[i] + pSrcB[i]); + } +} + +void ref_add_q15(q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, uint32_t blockSize) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) { + pDst[i] = ref_sat_q15((q31_t)pSrcA[i] + pSrcB[i]); + } +} + +void ref_add_q7(q7_t *pSrcA, q7_t *pSrcB, q7_t *pDst, uint32_t blockSize) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) { + pDst[i] = ref_sat_q7((q15_t)pSrcA[i] + pSrcB[i]); + } +} diff --git a/examples/dsp/BasicMathFunctions_part1/array.h b/examples/dsp/BasicMathFunctions_part1/array.h new file mode 100644 index 00000000..4dd6b055 --- /dev/null +++ b/examples/dsp/BasicMathFunctions_part1/array.h @@ -0,0 +1,30 @@ +// Array for BasicMathFunctions part1 +#define ARRAY_SIZE 257 + float32_t f32_a_array[ARRAY_SIZE] = { + 52331.288433, -48577.168507, 37541.128682, 26659.310242, 7633.298190, 47316.037824, 84089.195625, 79745.946380, 40155.952076, 46563.196204, 44099.519321, 33011.037777, -35269.990235, 2872.005647, -12838.517627, -87521.031716, 50016.765012, -84521.559465, -67765.771700, 62680.699895, 68373.039960, -53632.691314, -74083.289779, -82973.898048, -59370.680537, -36973.033347, -94929.902292, 53786.361838, -45899.602558, -41248.686598, -43806.038501, 11002.909520, -2941.800784, 49730.775090, 91426.796942, -76039.873184, 58843.103285, -92438.838688, 96004.542320, 1554.960120, -66542.023915, -90053.450851, -46349.869299, -89358.804340, 58501.331357, -61726.872720, -19021.692386, -80410.920374, 59607.584952, -29940.851717, 81505.290356, -60937.795758, 10682.928851, -67737.313853, -57466.652143, 31505.823080, 92388.510223, 49761.443920, 96610.767675, 22256.440811, 16796.757241, 58298.853138, -24489.292791, 57233.903592, -40847.910484, 10359.367685, 83753.857690, 26415.461313, -77446.419844, -65849.698894, -65928.653292, 59254.601853, -46206.507304, -85111.036098, 66801.566764, -74938.948694, 65732.005771, 17326.005148, -309.993151, -79531.517004, -79029.333327, -2932.637044, 73984.743122, -81206.337558, 38289.233209, -73844.742306, 40960.150496, -7609.540504, 2401.131977, 76308.648178, -92505.468389, 71305.413217, -23037.348088, -73577.170036, 33086.154336, -45194.365110, -16542.993069, -14940.368757, 61054.722234, 42437.475020, -74651.166819, 53080.506990, 4980.415587, 48517.051470, -29991.366258, 99295.134177, 4451.464113, 56004.455071, -94324.235920, -51485.557159, 42940.493537, -12791.198267, -1770.403019, -62774.757604, -51482.431501, -86123.160142, 84076.715024, -43882.331214, 98448.478438, 81023.660745, 32947.073964, 21730.758103, 14718.088681, -52272.842985, -37985.478491, -12193.390249, -6122.464346, 7585.463115, 75203.959320, -8276.419329, 30419.691385, 99387.100328, -83704.984719, -17945.209460, 15860.785857, 55692.522582, -37014.516805, -35058.273893, -63270.591407, -71875.422740, -64843.383162, -52460.197925, -49788.105733, 41847.550664, 7039.609820, 60323.495478, -13105.425088, -28456.829635, -57621.930531, 77851.971584, -91071.463412, -35432.683524, -70638.512344, 20384.886551, 84816.865093, -18649.781348, 94104.828428, -16611.121410, 91323.723008, -9217.603410, -84232.250832, 44072.940747, -60470.771933, 47376.486542, 19785.643449, -74141.729284, -81806.848759, 34403.267913, -13973.165371, -48798.422802, -20894.039920, -38104.428921, -32488.142945, 4047.880293, -54026.109997, 99146.351590, -87810.892192, -29245.189835, -43464.327430, -12983.310076, -29775.234191, 65259.560103, 379.330207, -31178.333111, 78500.227741, -1872.495036, 93883.187587, 42445.673660, 76333.886537, 17394.628843, -16854.430580, 26596.133783, -15327.745771, -40010.595847, 53477.753118, 66216.627695, 63808.332473, -45209.605747, 61373.025107, -11226.800183, -15311.893268, 47484.245222, 94259.572273, 42402.273343, -2616.576467, 72938.046369, -57708.866182, 42473.217724, -31233.510291, -69096.584839, 40075.109015, 84795.600947, 55688.998872, 80012.203974, -28875.812190, -92635.007732, 71342.750304, -31988.280404, 47687.152546, -8496.759875, -70315.230444, 55389.932447, -36858.190582, -78150.660918, 96964.622124, -35788.274089, 97181.022610, -62662.599472, -40025.536726, 94309.502917, 78583.295615, 32561.432512, 30759.542053, -29127.825718, 39218.237061, 4236.728252, -49585.145204, -29642.945237, -63983.871887, 37449.022023, -62372.998789, 73842.986013, -28996.921064, 45289.518788, 68829.285430, 72548.129432, 91111.351457, 75128.996215, -19285.933410, -54055.665627, -5611.050417, -9911.675718, -4180.616322, -64614.763347, -23932.549428, -26566.954749, 0 + }; + float32_t f32_b_array[ARRAY_SIZE] = { + -14748.363506, -52882.384680, 25759.674589, -8430.675902, 74296.471371, -43863.727703, -523.083136, -77357.923759, 32783.353464, 14412.111012, -71393.350919, -84183.651778, 824.589092, 5762.424446, 50730.438763, 48260.466707, -64545.815296, -39900.156962, -42110.612503, 56969.361004, -51774.608591, 9524.295477, -56397.699274, 32974.695621, 54630.484822, 90917.121406, 58344.534264, -29546.804178, 29363.527509, -87659.765721, -80490.876894, 37360.782533, 83452.673319, -19566.741800, -64002.115525, -86502.336497, -86006.512493, 80838.557374, -14739.922414, -16896.379687, 8249.474651, 62724.054497, -1554.008023, -20395.188880, -31156.347950, 79891.105230, -45867.738768, 41333.044629, -7676.999956, 21771.713145, 82557.192605, 30500.710863, 31020.717681, 90597.001881, 99010.508568, 30322.571728, 40948.345159, -56276.504473, -61883.945216, -43079.002095, 29078.509077, 22794.228547, 74372.378733, -44055.068256, -53388.492633, -47784.325626, 14655.815561, 87444.174577, 87769.374380, -68921.250204, -68386.761085, -52032.613959, 59823.419305, 1754.801055, 95175.314736, -81105.314495, -34347.237022, 99133.704956, -1084.496731, -7528.947275, -8550.169841, 96866.053124, -32186.038563, 36079.172067, -25788.868160, 57515.787963, -89526.285196, -77820.605829, 49394.787719, -35410.274156, -2256.085487, -83347.534826, -19993.092476, -65402.603615, -35246.742498, -22573.751524, 54198.764622, -12551.651641, 38204.923509, 98339.464040, -78764.691121, -2536.506110, 62301.390849, -85946.411564, 25842.028436, 76980.636907, 66949.171540, -29600.343091, -67253.179681, 7999.959469, 51332.669028, -44266.161876, 63008.256158, 49447.784664, -8380.123077, 46.292316, -67452.730308, 93632.612589, -81494.922442, 83208.281900, -77996.866742, 53254.044501, -2066.082186, 89818.784744, -15978.453803, -58657.785681, 30989.308148, 63421.056711, 68160.313136, -44862.375309, -91802.269653, -10308.420264, 94507.850245, 43351.597128, -1687.669472, 8944.333835, -42358.233628, -66830.639128, 31335.273026, 1305.552391, 90904.188061, 26056.581575, 76717.070907, 69598.252599, -29449.914625, 51436.373685, -15138.962974, 78186.487897, -54861.987172, 15103.224330, -72401.041527, -79902.737504, -11792.134683, 35998.732785, -17947.048577, -35121.453671, 95234.578361, 33760.262870, -49548.979357, 33613.590186, -59180.165768, -12312.964538, 68976.756638, -98421.925464, 18748.996727, 87649.415189, -42603.968561, 66093.151677, -72649.431024, 58901.864996, -67727.390125, -93153.696522, -49001.478199, 51765.998867, 83230.060919, -40058.643283, -95872.550493, 37144.776727, 95117.125646, -49387.279353, -24978.646538, 51620.351258, -22826.467093, -27834.035075, 58073.389064, 51847.867995, -86010.948205, -41612.180492, 69343.113867, -95211.627972, 50191.674724, 29427.473654, 25573.797740, -58615.487098, 54218.880235, -32891.418497, 98733.460752, -63682.034121, 12563.683345, -75141.721838, 15118.782568, 37524.587438, -73081.462512, 4141.596016, 19532.955276, -71059.521486, 83329.657219, 24808.360451, 49712.670973, 55451.749620, -9809.453314, -87943.676689, -34302.161571, -94239.070472, 12611.124712, -38415.464213, -10883.611425, 2520.958779, 77365.058601, -77828.961437, 40915.821395, -65590.466499, -44446.352196, 43511.623038, -67237.562075, 38946.545673, -56447.758311, 8714.617727, 99568.415968, -45626.895014, 95102.601971, 43532.618006, 52518.777936, -31728.780028, -20026.763246, 71735.294631, -79396.329375, -16707.811932, 57955.715055, 4169.562060, -69506.060979, -67552.113568, -36282.586949, -31273.361532, -18139.073474, -22958.638140, 3438.475837, 86574.556610, -93725.007343, 8368.616620, 1270.601154, -21430.484085, -98146.567789, 96054.887155, 79600.800101, 45881.525507, 0 + }; + q7_t q7_a_array[ARRAY_SIZE] = { + -22, -117, 90, 77, 4, -73, 115, -93, 36, -25, -122, 12, -54, 113, 66, -122, -88, 20, 22, 70, -67, 6, 13, -42, 98, -80, 23, -94, 58, -62, 25, -116, -101, -80, 12, 10, -2, -90, -46, -118, -111, -120, 16, 8, 22, -65, 64, 70, 11, 86, -75, -19, -98, 49, 99, -89, -15, 125, 15, 5, 71, 98, -101, 34, -43, -73, -100, -127, 4, -39, -62, 83, -59, 68, -105, 52, 91, -22, 124, 17, -27, 47, -78, -82, 79, 49, -108, 41, 2, -85, -115, -27, -110, 21, -107, 49, -101, -108, 114, -4, -121, 32, -65, -30, -52, -92, -95, -111, 77, -12, 25, -43, -73, 15, 96, -11, 84, 28, 52, -97, -52, 46, 64, 11, 56, -10, -117, -116, 41, 93, -3, -19, 74, -28, -7, -86, 14, -116, 46, 113, 41, -99, -89, -53, 109, 78, 19, 16, 13, 112, 40, -46, -119, 120, -10, 23, 56, -126, 84, 32, 127, -114, -46, 124, 71, 56, 60, -101, 96, 94, -113, 70, -103, 69, 71, -120, -25, -78, 24, 39, 0, -63, -69, -65, -19, -52, -108, -78, -83, -108, 35, -70, 114, -91, -26, -24, 24, -20, 103, -126, 44, 112, 34, 18, 2, -30, 94, 29, 51, 116, -70, 58, -78, -15, -42, 43, 123, 43, -93, -11, -123, -35, -43, 109, -47, 34, 58, -75, -30, -98, -95, 47, 54, -25, -127, -40, 18, 8, -70, 122, -67, -9, 34, 126, 86, -1, -78, -118, 19, -69, -18, -108, 98, -8, 10, -99, 0 + }; + q7_t q7_b_array[ARRAY_SIZE] = { + 80, -7, 32, 18, 9, 28, -88, 74, -91, 30, -46, 49, 28, -37, -89, -63, -9, -69, -114, 6, 107, -12, -8, -29, 124, -113, 73, -31, 27, 12, 9, -49, 99, -79, -77, 59, -88, 71, -120, -20, -89, 1, -84, -26, 111, -54, -92, 105, 108, -83, -119, -30, 66, 2, -1, 40, -88, 53, 16, 85, 75, -122, -14, -53, -118, 78, 45, -8, -72, -52, 9, -63, -64, 64, -62, -125, -11, -71, 91, 36, -93, 74, 17, -97, 20, -56, 109, -33, -121, 104, -86, -21, -39, 2, -121, -72, 47, 47, 2, -123, 53, -104, -72, 8, 30, -18, 10, 104, -110, -83, 70, 34, -92, 32, -105, 70, 74, -57, 19, 109, -41, 17, 62, 80, 103, 98, 75, 118, 118, -54, 97, -93, 73, -112, -18, -50, -68, -10, -59, -112, 84, 100, -106, 70, 77, 114, -85, 104, 100, 53, -13, -18, -116, -74, -7, -116, 50, 77, -8, -27, 24, 28, -92, 68, 74, -119, 64, -30, -21, -35, -47, -13, -126, -27, 3, 83, -65, -126, -57, -116, -110, -105, 30, 45, -50, 108, -126, -83, 77, 90, 80, 84, 123, -49, -70, -3, 52, -20, -92, 8, 106, -101, -70, 105, -122, 50, -85, 21, 93, 85, -32, 31, -53, -5, 4, -88, -4, 87, 41, -27, -94, -26, -74, -47, 85, 10, -88, -94, 65, 34, 50, 121, -23, -68, -87, -93, -96, 26, 119, -83, -114, 50, -99, -61, -125, -107, -30, 98, 110, -81, 0, -94, -42, 21, -74, -35, 0 + }; + q15_t q15_a_array[ARRAY_SIZE] = { + 1982,1152,1883,65,2732,2402,2238,2440,1150,1852,1727,1591,826,746,1355,684,2414,2959,90,1607,262,2407,2968,201,2819,55,2052,2352,1603,2657,2698,1878,414,654,547,126,321,1850,2819,1064,1232,2954,2837,2030,2965,2301,1011,1988,733,887,2041,1584,1235,1808,2252,1751,1656,1751,1536,248,2159,2989,1064,2914,1040,2660,1365,1241,654,377,927,2179,2349,2082,30,2530,2767,2313,128,1135,2114,2189,673,808,2020,1433,1872,710,532,2489,2301,2804,324,547,298,1470,580,2688,298,133,1672,2318,936,537,1017,631,1531,2720,1887,305,1173,164,1504,1296,2993,2435,1457,2684,413,1171,2783,2753,2141,1856,1030,2809,375,2192,1940,2500,1195,2250,2506,968,1657,2938,1648,992,1859,1082,2270,1242,1478,2085,2919,984,2514,2218,2863,96,1071,1988,845,692,2134,1874,1772,1982,143,1047,1355,723,2146,2569,845,2194,414,2511,416,1765,1099,2421,1512,1469,2632,1060,1349,2891,127,2919,568,2002,1760,2026,1084,1861,2434,58,252,2925,1955,694,1211,367,806,774,995,457,1045,365,2653,283,2791,1198,143,1028,2208,2385,1635,2059,2681,165,911,139,587,2161,2166,2634,1748,213,2769,2402,858,1631,2955,2148,2517,1300,1412,1683,808,2248,1512,1941,924,417,1427,1088,2365,2341,2006,401,65,1680,903,2819,2943,860,2403,2689,1793,2653,2832,1648,2186,1731,78 + }; + q15_t q15_b_array[ARRAY_SIZE] = { + 1340,1939,1564,1117,2812,2489,2548,1118,1780,2618,2801,2006,621,1962,217,1221,2001,2802,2433,1454,2271,1252,2916,2964,2593,1167,1365,741,2354,2649,2742,1675,1797,447,2700,1352,618,2699,2288,2648,855,2020,1993,369,1222,826,2151,851,2689,2480,1171,1494,2085,2504,1829,1725,979,1370,2142,2654,2163,56,2025,1316,1314,352,2445,975,739,1029,1128,1640,1686,1188,1195,1547,1973,2853,2168,1201,2496,404,182,253,492,973,906,36,1620,287,440,1894,2578,2923,1713,2991,1661,1547,993,1291,1476,214,2664,194,1309,2480,1184,1841,2456,2659,2794,573,776,2694,1781,1512,1839,2459,1596,607,1362,1284,2899,1861,2087,2161,1041,1551,1671,470,1687,2085,1280,2509,2195,1081,1363,1160,2327,2203,1291,2082,2836,2353,2117,329,1170,1773,1379,152,687,2503,47,2592,235,2008,1501,654,1715,367,2014,1799,168,170,458,59,1306,2497,1853,1561,2592,294,2725,325,1551,430,1679,14,2301,2547,2751,2961,1516,815,303,1524,1757,2289,249,1985,1551,514,2816,1772,1322,2826,1968,1356,2520,1598,1662,2041,1102,718,1737,2601,1221,338,1332,901,1205,2501,1211,1171,1082,421,781,261,1289,772,893,1275,358,1486,2120,731,2356,223,1182,11,663,4,568,428,805,525,416,1797,2704,2819,664,1449,1129,1572,795,206,1309,522,79,2865,1292,2885,2288,23,2041,2118,1936 + }; + q31_t q31_a_array[ARRAY_SIZE] = { + 122675060, -19679606, 12005090, 128022795, -95284239, 1562872905, 214945602, 1304329431, -1508008274, 240787476, -905121314, 1622448750, 1128343957, 1088297819, 1929718262, 301748725, -1705937804, 412523122, 1868902555, 1990922011, 667241326, 1515133104, 122494706, -1539561650, 1117106510, 859507136, -940688492, -216177261, 1480104259, -634335848, 1983809950, -1406467930, -475661641, 1322061117, -825315378, -1807561254, 1449578423, 657148057, 1926668369, -1215598619, 412458663, -1807869491, 1422979790, 1023406889, -597431780, -1448317484, 1541343116, -2012852409, -43191490, -1215649277, -1017506653, -1915995397, -2080480350, 1094251372, 528600991, 143231710, 1391256474, -1041052209, 1278401986, 850686725, -2102619359, 1935527594, -431606953, -1976242055, -350139619, -589613336, 723038213, 166006808, 1760518450, 1386001502, -1457863745, -843865763, -1469590333, -605307148, -1892711295, 1107317389, 2133350043, 857819879, -798439008, -683125572, 1414380309, -1296729433, -972942965, -486754604, 428102856, -954668329, -2135465095, 1294752174, -2115260357, -1285371550, 142879568, -1259143073, 1988627270, 25731949, -1919745773, 1911174931, -835919509, -46679513, 275933135, 1724700061, 869122148, 473727312, -2018146537, 237804352, 145422132, 1233850002, -1329633347, 12780582, 1110157442, -1915661877, -928226928, -227663812, 828379127, -1674105026, 1927003415, -1639017283, -465311741, -658984229, -903260597, 490177562, 1126362032, -1034719085, -422641969, 1772346616, -1907663619, 1817734130, -1923639110, 1120016563, 141086779, -2102345903, 1724327426, -1866919811, -830684706, 1745078516, -1976128296, 799279002, -993799341, -1390877590, 904934458, -472067105, -455592220, 212192933, -34506575, 333518014, -85924850, -1599754424, 1355485624, -2014365016, -1127697814, -1076997804, 1705661182, -3234669, -632233921, 1798567554, -33103420, 4247767, -49163650, 779091592, -1163771871, 387580837, 127441404, 209878412, 61087762, 518500510, 836574845, 1629528554, -406038126, 459087674, -1103579310, 21540829, 1530951457, -1901138893, 809545038, -1083073633, -1608669130, -1714887885, 305376892, 905733099, 268734751, -1761301144, -1110601471, 581811091, 1926809483, 875843018, -409535295, -1494401242, -1492148258, 668320270, -1996003820, -470239924, 793927528, 1945752597, -336927405, -1078519032, 1673260004, -1226877022, 521095932, -572753832, 1860213970, 1198498531, 88542373, 1360949371, 656122057, 1792409478, 1656830983, -350299887, 1580672481, -1680928093, -2092549882, 876454682, -1735152678, 1646616771, 1189864260, 790291045, -337847342, 1947695906, -53101665, 1238647266, -89940713, -371577084, -1610381759, -402627031, 506455569, 430996275, 1774144323, 1310368600, -724205623, 370714565, 725347367, -1828596909, 365721697, -53655909, -1185780624, 1770739705, -2034892356, -418862235, 1739930005, -1498889924, -716521073, -263983575, -2042749120, -1263297029, 2060971911, -1666777591, 188198003, 251790886, 280390084, 1738016223, -580281801, 1831928083, -355653596, 1102400369, 2095795866, -294097927, 419052797, -1582812810, 0 + }; + q31_t q31_b_array[ARRAY_SIZE] = { + 204712319, 180144284, -209543243, 53916792, 197369355, 170830946, 1203514600, -312712536, 920743651, -1824625112, 420984875, 566536029, -506845364, -6857324, -434156189, -2142111505, 1045850978, -553910124, 824249774, -1488182567, -1675551882, -1925964935, 130855719, -1519925487, -589106798, 1494457749, -1565562513, -1262423706, -1230994795, -1088443954, 292519408, 1485212926, 242646787, -1088539142, -1274467679, 377739522, 159674802, -1547588366, -1949250075, -70691370, 781689702, -1835633981, 1942796846, -946887651, 848483564, -1548962935, 1870014462, 965663041, 1064259438, -383719640, -978783057, -944796566, 1430103113, -1260222873, -491040724, 1890727220, 2083502691, -556734811, -2113938357, -1585633018, 500105338, -886584662, 1336908666, -1311222963, 829306607, 910265989, 772979607, 626531703, 1646600062, -1937223716, -2024512853, -2067002399, -339307241, 1222434257, 1935277322, -231577250, -1724802316, 1907944900, 1658715575, -167516745, -58080523, 704490019, 1769573496, 32104716, 1064048689, -1318211013, 1016863918, 156537401, -1570152318, 131164953, 473324936, -196058652, -804227817, -9864755, 261520124, 1688883032, -1390111444, -522034107, 1274716973, 28982511, -1257583053, 1239694813, 1559794457, -1954406219, -416627738, -1691661573, 2039656472, -775687970, 729664130, 71135859, 2096190599, -1103089806, 1123796817, 694770500, -1976481918, -2134177767, -1583968644, -335906080, 2071961996, 1579203899, 262093988, 650393055, -338265896, -1505741655, 1175860682, 946357443, -1207168411, -225330030, -1176181106, 2011575645, -1754066324, -809543616, -1373368213, 358483112, 340851017, -997540864, -1584216501, 739788159, -1149806217, -1975988237, -1970552427, 1972302799, -448351628, 270309495, -2139626674, -2098878453, -1182495205, 2083627675, -610056538, -1743625393, 673599227, 1366000634, -1502388581, 1682967668, 42387805, 1022528321, -96259255, -151651019, 1907675374, -1465653629, 913779582, 199093513, -1083451962, 1172360491, -173772550, -1036446741, 2087691584, 954130802, -828357762, 916251036, 607400636, 1421070580, 1517590451, 979323974, -447508836, -1857041315, -1438039268, 2094707628, -1113865682, 1858121943, -1697925378, 1947565393, -2033040794, 826742982, -1017221207, -1265775408, 1775001649, -901031292, -1006552336, 28220675, 348700548, -2022106631, -1882248812, 2128053164, 447961767, 1419683607, -584893763, 1106977433, 486359498, 1533950699, 1837531408, 69590196, 1154641977, 1250545798, 505825431, 827243169, -632897439, -1841468473, 576227897, 1408476080, -251749351, -1814864257, -1767927418, -1694086470, -158656041, 1426194109, -1158397383, 896561495, 562232852, 973254663, -1206226163, -680189470, 522302066, -262726378, -74845893, -1057028022, 1845899344, 1161389957, -778331576, -11579864, 1225550271, -1500506478, 381609770, -1012049574, -1757206767, 96165946, 815148018, 265234274, 98201427, -826365919, -100542806, 1481517858, 1701987141, -1255526945, 611861026, -1118297781, 529286200, 1718060564, -6828272, -313800781, 1878684705, -2109937359, 732996262, 588183518, -872143020, -950440153, 0 + }; + float32_t f32_out_array[ARRAY_SIZE], f32_out_ref_array[ARRAY_SIZE]; + q7_t q7_out_array[ARRAY_SIZE], q7_out_ref_array[ARRAY_SIZE]; + q15_t q15_out_array[ARRAY_SIZE], q15_out_ref_array[ARRAY_SIZE]; + q31_t q31_out_array[ARRAY_SIZE], q31_out_ref_array[ARRAY_SIZE]; \ No newline at end of file diff --git a/examples/dsp/BasicMathFunctions_part1/dot_prod.c b/examples/dsp/BasicMathFunctions_part1/dot_prod.c new file mode 100644 index 00000000..07e6e68d --- /dev/null +++ b/examples/dsp/BasicMathFunctions_part1/dot_prod.c @@ -0,0 +1,49 @@ +#include "ref.h" + +void ref_dot_prod_f32(float32_t *pSrcA, float32_t *pSrcB, uint32_t blockSize, + float32_t *result) +{ + uint32_t i; + float32_t sum = 0.0f; + + for (i = 0; i < blockSize; i++) { + sum += pSrcA[i] * pSrcB[i]; + } + *result = sum; +} + +void ref_dot_prod_q31(q31_t *pSrcA, q31_t *pSrcB, uint32_t blockSize, + q63_t *result) +{ + uint32_t i; + q63_t sum = 0.0f; + + for (i = 0; i < blockSize; i++) { + sum += ((q63_t)pSrcA[i] * pSrcB[i]) >> 14; // 16.48 + } + *result = sum; +} + +void ref_dot_prod_q15(q15_t *pSrcA, q15_t *pSrcB, uint32_t blockSize, + q63_t *result) +{ + uint32_t i; + q63_t sum = 0.0f; + + for (i = 0; i < blockSize; i++) { + sum += (q31_t)pSrcA[i] * pSrcB[i]; // 34.30 + } + *result = sum; +} + +void ref_dot_prod_q7(q7_t *pSrcA, q7_t *pSrcB, uint32_t blockSize, + q31_t *result) +{ + uint32_t i; + q31_t sum = 0.0f; + + for (i = 0; i < blockSize; i++) { + sum += (q31_t)pSrcA[i] * pSrcB[i]; // 18.14 + } + *result = sum; +} diff --git a/examples/dsp/BasicMathFunctions_part1/main.c b/examples/dsp/BasicMathFunctions_part1/main.c new file mode 100644 index 00000000..e82b8dad --- /dev/null +++ b/examples/dsp/BasicMathFunctions_part1/main.c @@ -0,0 +1,269 @@ +// +// Created by lujun on 19-6-21. +// +#include "riscv_math.h" +#include +#include +#include "array.h" +#include "../common.h" + +#include "../HelperFunctions/math_helper.c" +#include "../HelperFunctions/ref_helper.c" + +#include +#define DELTAF32 (0.05f) +#define DELTAQ31 (63) +#define DELTAQ15 (1) +#define DELTAQ7 (1) + +#define ENABLE_ALL +#define ABS +#define ADD +#define DOT_PROD +#define MULT + +int test_flag_error = 0; + +int main() +{ + int i; + float32_t f32_out, f32_out_ref; + q7_t q7_out, q7_out_ref; + q15_t q15_out, q15_out_ref; + q31_t q31_out, q31_out_ref; + q63_t q63_out, q63_out_ref; + BENCH_INIT; +#if defined ABS || defined ENABLE_ALL + // *********************************** abs + // ********************************** riscv_abs_f32.c + BENCH_START(riscv_abs_f32); + riscv_abs_f32(f32_a_array, f32_out_array, ARRAY_SIZE); + BENCH_END(riscv_abs_f32); + ref_abs_f32(f32_a_array, f32_out_ref_array, ARRAY_SIZE); + for (int i = 0; i < ARRAY_SIZE; i++) + if (fabs(f32_out_array[i] - f32_out_ref_array[i]) > DELTAF32) { + BENCH_ERROR(riscv_abs_f32); + printf("index: %d,expect: %f, actual: %f\n", i, + f32_out_ref_array[i], f32_out_array[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_abs_f32); + + // riscv_abs_q7.c + BENCH_START(riscv_abs_q7); + riscv_abs_q7(q7_a_array, q7_out_array, ARRAY_SIZE); + BENCH_END(riscv_abs_q7); + ref_abs_q7(q7_a_array, q7_out_ref_array, ARRAY_SIZE); + for (int i = 0; i < ARRAY_SIZE; i++) + if (abs(q7_out_array[i] - q7_out_ref_array[i]) > DELTAQ7) { + BENCH_ERROR(riscv_abs_q7); + printf("index: %d, expect: %x, actual: %x\n", i, + q7_out_ref_array[i], q7_out_array[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_abs_q7); + + // riscv_abs_q15.c + BENCH_START(riscv_abs_q15); + riscv_abs_q15(q15_a_array, q15_out_array, ARRAY_SIZE); + BENCH_END(riscv_abs_q15); + ref_abs_q15(q15_a_array, q15_out_ref_array, ARRAY_SIZE); + for (int i = 0; i < ARRAY_SIZE; i++) + if (abs(q15_out_array[i] - q15_out_ref_array[i]) > DELTAQ15) { + BENCH_ERROR(riscv_abs_q15); + printf("index: %d, expect: %x, actual: %x\n", i, + q15_out_ref_array[i], q15_out_array[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_abs_q15); + + // riscv_abs_q31.c + BENCH_START(riscv_abs_q31); + riscv_abs_q31(q31_a_array, q31_out_array, ARRAY_SIZE); + BENCH_END(riscv_abs_q31); + ref_abs_q31(q31_a_array, q31_out_ref_array, ARRAY_SIZE); + for (int i = 0; i < ARRAY_SIZE; i++) + if (labs(q31_out_array[i] - q31_out_ref_array[i]) > DELTAQ31) { + BENCH_ERROR(riscv_abs_q31); + printf("index: %d, expect: %x, actual: %x\n", i, + q31_out_ref_array[i], q31_out_array[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_abs_q31); +#endif +#if defined ADD || defined ENABLE_ALL + // ************************************* add + // **************************************** riscv_add_f32.c + BENCH_START(riscv_add_f32); + riscv_add_f32(f32_a_array, f32_b_array, f32_out_array, ARRAY_SIZE); + BENCH_END(riscv_add_f32); + ref_add_f32(f32_a_array, f32_b_array, f32_out_ref_array, ARRAY_SIZE); + for (int i = 0; i < ARRAY_SIZE; i++) + if (fabs(f32_out_array[i] - f32_out_ref_array[i]) > DELTAF32) { + BENCH_ERROR(riscv_add_f32); + printf("index: %d, expect: %f, actual: %f\n", i, + f32_out_ref_array[i], f32_out_array[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_add_f32); + + // riscv_add_q7.c + BENCH_START(riscv_add_q7); + riscv_add_q7(q7_a_array, q7_b_array, q7_out_array, ARRAY_SIZE); + BENCH_END(riscv_add_q7); + ref_add_q7(q7_a_array, q7_b_array, q7_out_ref_array, ARRAY_SIZE); + for (int i = 0; i < ARRAY_SIZE; i++) + if (abs(q7_out_array[i] - q7_out_ref_array[i]) > DELTAQ7) { + BENCH_ERROR(riscv_add_q7); + printf("index: %d, expect: %x, actual: %x\n", i, + q7_out_ref_array[i], q7_out_array[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_add_q7); + + // riscv_add_q15.c + BENCH_START(riscv_add_q15); + riscv_add_q15(q15_a_array, q15_b_array, q15_out_array, ARRAY_SIZE); + BENCH_END(riscv_add_q15); + ref_add_q15(q15_a_array, q15_b_array, q15_out_ref_array, ARRAY_SIZE); + for (int i = 0; i < ARRAY_SIZE; i++) + if (abs(q15_out_array[i] - q15_out_ref_array[i]) > DELTAQ15) { + BENCH_ERROR(riscv_add_q15); + printf("index: %d, expect: %x, actual: %x\n", i, + q15_out_ref_array[i], q15_out_array[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_add_q15); + + // riscv_add_q31.c + BENCH_START(riscv_add_q31); + riscv_add_q31(q31_a_array, q31_b_array, q31_out_array, ARRAY_SIZE); + BENCH_END(riscv_add_q31); + ref_add_q31(q31_a_array, q31_b_array, q31_out_ref_array, ARRAY_SIZE); + for (int i = 0; i < ARRAY_SIZE; i++) + if (labs(q31_out_array[i] - q31_out_ref_array[i]) > DELTAQ31) { + BENCH_ERROR(riscv_add_q31); + printf("index: %d expect: %x, actual: %x\n", i, + q31_out_ref_array[i], q31_out_array[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_add_q31); +#endif +#if defined DOT_PROD || defined ENABLE_ALL + //************************************* dot prod + //******************************************** + // f32_dot + BENCH_START(riscv_dot_prod_f32); + riscv_dot_prod_f32(f32_a_array, f32_b_array, ARRAY_SIZE, &f32_out); + BENCH_END(riscv_dot_prod_f32); + ref_dot_prod_f32(f32_a_array, f32_b_array, ARRAY_SIZE, &f32_out_ref); + if (fabs(f32_out - f32_out_ref) > 0.5) { + BENCH_ERROR(riscv_dot_prod_f32); + printf("index:%d, expect: %f, actual: %f\n", i, f32_out_ref, f32_out); + test_flag_error = 1; + } + BENCH_STATUS(riscv_dot_prod_f32); + + // q7_dot + BENCH_START(riscv_dot_prod_q7); + riscv_dot_prod_q7(q7_a_array, q7_b_array, ARRAY_SIZE, &q31_out); + BENCH_END(riscv_dot_prod_q7); + ref_dot_prod_q7(q7_a_array, q7_b_array, ARRAY_SIZE, &q31_out_ref); + if (abs(q31_out - q31_out_ref) > DELTAQ7) { + BENCH_ERROR(riscv_dot_prod_q7); + printf("index: %d, expect: %x, actual: %x\n", i, q31_out_ref, q31_out); + test_flag_error = 1; + } + BENCH_STATUS(riscv_dot_prod_q7); + + // q15_dot + BENCH_START(riscv_dot_prod_q15); + riscv_dot_prod_q15(q15_a_array, q15_b_array, ARRAY_SIZE, &q63_out); + BENCH_END(riscv_dot_prod_q15); + ref_dot_prod_q15(q15_a_array, q15_b_array, ARRAY_SIZE, &q63_out_ref); + if (abs(q63_out - q63_out_ref) > DELTAQ31) { + BENCH_ERROR(riscv_dot_prod_q15); + printf("index: %d, expect: %x, actual: %x\n", i, q63_out_ref, q63_out); + test_flag_error = 1; + } + BENCH_STATUS(riscv_dot_prod_q15); + + // q31_dot + BENCH_START(riscv_dot_prod_q31); + riscv_dot_prod_q31(q31_a_array, q31_b_array, ARRAY_SIZE, &q63_out); + BENCH_END(riscv_dot_prod_q31); + ref_dot_prod_q31(q31_a_array, q31_b_array, ARRAY_SIZE, &q63_out_ref); + if (abs(q63_out - q63_out_ref) > DELTAQ31) { + BENCH_ERROR(riscv_dot_prod_q31); + printf("index: %d, expect: %x, actual: %x\n", i, q63_out_ref, q63_out); + test_flag_error = 1; + } + BENCH_STATUS(riscv_dot_prod_q31); +#endif +#if defined MULT || defined ENABLE_ALL + // ******************************** mult ******************************** + // f32_mult + BENCH_START(riscv_mult_f32); + riscv_mult_f32(f32_a_array, f32_b_array, f32_out_array, ARRAY_SIZE); + BENCH_END(riscv_mult_f32); + ref_mult_f32(f32_a_array, f32_b_array, f32_out_ref_array, ARRAY_SIZE); + for (int i = 0; i < ARRAY_SIZE; i++) + if (fabs(f32_out_array[i] - f32_out_ref_array[i]) > 0.5) { + BENCH_ERROR(riscv_mult_f32); + printf("index:%d, expect: %f, actual: %f\n", i, + f32_out_ref_array[i], f32_out_array[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_mult_f32); + + // riscv_mult_q7.c + BENCH_START(riscv_mult_q7); + riscv_mult_q7(q7_a_array, q7_b_array, q7_out_array, ARRAY_SIZE); + BENCH_END(riscv_mult_q7); + ref_mult_q7(q7_a_array, q7_b_array, q7_out_ref_array, ARRAY_SIZE); + for (int i = 0; i < ARRAY_SIZE; i++) + if (abs(q7_out_array[i] - q7_out_ref_array[i]) > DELTAQ7) { + BENCH_ERROR(riscv_mult_q7); + printf("index: %d, expect: %x, actual: %x\n", i, + q7_out_ref_array[i], q7_out_array[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_mult_q7); + + // riscv_mult_q15.c + BENCH_START(riscv_mult_q15); + riscv_mult_q15(q15_a_array, q15_b_array, q15_out_array, ARRAY_SIZE); + BENCH_END(riscv_mult_q15); + ref_mult_q15(q15_a_array, q15_b_array, q15_out_ref_array, ARRAY_SIZE); + for (int i = 0; i < ARRAY_SIZE; i++) + if (abs(q15_out_array[i] - q15_out_ref_array[i]) > DELTAQ15) { + BENCH_ERROR(riscv_mult_q15); + printf("expect: %x, actual: %x\n", q15_out_ref_array[i], + q15_out_array[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_mult_q15); + + // riscv_mult_q31.c + BENCH_START(riscv_mult_q31); + riscv_mult_q31(q31_a_array, q31_b_array, q31_out_array, ARRAY_SIZE); + BENCH_END(riscv_mult_q31); + ref_mult_q31(q31_a_array, q31_b_array, q31_out_ref_array, ARRAY_SIZE); + for (int i = 0; i < ARRAY_SIZE; i++) + if (labs(q31_out_array[i] - q31_out_ref_array[i]) > DELTAQ31) { + BENCH_ERROR(riscv_mult_q31); + printf("index: %d, expect: %x, actual: %x\n", i, + q31_out_ref_array[i], q31_out_array[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_mult_q31); +#endif + BENCH_FINISH; + if (test_flag_error) { + printf("test error apprears, please recheck.\n"); + return 1; + } else { + printf("all test are passed. Well done!\n"); + } + return 0; +} diff --git a/examples/dsp/BasicMathFunctions_part1/mult.c b/examples/dsp/BasicMathFunctions_part1/mult.c new file mode 100644 index 00000000..b63afcc1 --- /dev/null +++ b/examples/dsp/BasicMathFunctions_part1/mult.c @@ -0,0 +1,48 @@ +#include "ref.h" + +void ref_mult_f32(float32_t *pSrcA, float32_t *pSrcB, float32_t *pDst, + uint32_t blockSize) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) { + pDst[i] = pSrcA[i] * pSrcB[i]; + } +} + +void ref_mult_q31(q31_t *pSrcA, q31_t *pSrcB, q31_t *pDst, uint32_t blockSize) +{ + uint32_t i; + q63_t temp; + + for (i = 0; i < blockSize; i++) { + temp = ((q63_t)pSrcA[i] * pSrcB[i]) >> 32; + temp = temp << 1; + pDst[i] = ref_sat_q31(temp); + } +} + +void ref_mult_q15(q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, uint32_t blockSize) +{ + uint32_t i; + q31_t temp; + + for (i = 0; i < blockSize; i++) { + temp = ((q31_t)pSrcA[i] * pSrcB[i]) >> + 15; // this comment is for JD, this is specifically 15 and not 16 + // like the q31 case might imply. This is because NMSIS DSP + // lib does it this way. No other reason. + pDst[i] = ref_sat_q15(temp); + } +} + +void ref_mult_q7(q7_t *pSrcA, q7_t *pSrcB, q7_t *pDst, uint32_t blockSize) +{ + uint32_t i; + q15_t temp; + + for (i = 0; i < blockSize; i++) { + temp = ((q15_t)pSrcA[i] * pSrcB[i]) >> 7; + pDst[i] = ref_sat_q7(temp); + } +} diff --git a/examples/dsp/BasicMathFunctions_part2/CMakeLists.txt b/examples/dsp/BasicMathFunctions_part2/CMakeLists.txt new file mode 100644 index 00000000..77ef91c1 --- /dev/null +++ b/examples/dsp/BasicMathFunctions_part2/CMakeLists.txt @@ -0,0 +1,5 @@ +set(TARGET_REQUIRED_PRIVATE_INCLUDE ${CMAKE_CURRENT_SOURCE_DIR} ${CMAKE_CURRENT_SOURCE_DIR}/..) +set(TARGET_REQUIRED_SRCS clip.c negate.c offset.c scale.c shift.c sub.c) +set(TARGET_REQUIRED_LIBS nmsis) +set(mains main.c) +generate_bin() diff --git a/examples/dsp/BasicMathFunctions_part2/array.h b/examples/dsp/BasicMathFunctions_part2/array.h new file mode 100644 index 00000000..23e6a9b3 --- /dev/null +++ b/examples/dsp/BasicMathFunctions_part2/array.h @@ -0,0 +1,31 @@ +// Array for BasicMathFunctions part2 +#define ARRAY_SIZE 257 + float32_t f32_a_array[ARRAY_SIZE] = { + 52331.288433, -48577.168507, 37541.128682, 26659.310242, 7633.298190, 47316.037824, 84089.195625, 79745.946380, 40155.952076, 46563.196204, 44099.519321, 33011.037777, -35269.990235, 2872.005647, -12838.517627, -87521.031716, 50016.765012, -84521.559465, -67765.771700, 62680.699895, 68373.039960, -53632.691314, -74083.289779, -82973.898048, -59370.680537, -36973.033347, -94929.902292, 53786.361838, -45899.602558, -41248.686598, -43806.038501, 11002.909520, -2941.800784, 49730.775090, 91426.796942, -76039.873184, 58843.103285, -92438.838688, 96004.542320, 1554.960120, -66542.023915, -90053.450851, -46349.869299, -89358.804340, 58501.331357, -61726.872720, -19021.692386, -80410.920374, 59607.584952, -29940.851717, 81505.290356, -60937.795758, 10682.928851, -67737.313853, -57466.652143, 31505.823080, 92388.510223, 49761.443920, 96610.767675, 22256.440811, 16796.757241, 58298.853138, -24489.292791, 57233.903592, -40847.910484, 10359.367685, 83753.857690, 26415.461313, -77446.419844, -65849.698894, -65928.653292, 59254.601853, -46206.507304, -85111.036098, 66801.566764, -74938.948694, 65732.005771, 17326.005148, -309.993151, -79531.517004, -79029.333327, -2932.637044, 73984.743122, -81206.337558, 38289.233209, -73844.742306, 40960.150496, -7609.540504, 2401.131977, 76308.648178, -92505.468389, 71305.413217, -23037.348088, -73577.170036, 33086.154336, -45194.365110, -16542.993069, -14940.368757, 61054.722234, 42437.475020, -74651.166819, 53080.506990, 4980.415587, 48517.051470, -29991.366258, 99295.134177, 4451.464113, 56004.455071, -94324.235920, -51485.557159, 42940.493537, -12791.198267, -1770.403019, -62774.757604, -51482.431501, -86123.160142, 84076.715024, -43882.331214, 98448.478438, 81023.660745, 32947.073964, 21730.758103, 14718.088681, -52272.842985, -37985.478491, -12193.390249, -6122.464346, 7585.463115, 75203.959320, -8276.419329, 30419.691385, 99387.100328, -83704.984719, -17945.209460, 15860.785857, 55692.522582, -37014.516805, -35058.273893, -63270.591407, -71875.422740, -64843.383162, -52460.197925, -49788.105733, 41847.550664, 7039.609820, 60323.495478, -13105.425088, -28456.829635, -57621.930531, 77851.971584, -91071.463412, -35432.683524, -70638.512344, 20384.886551, 84816.865093, -18649.781348, 94104.828428, -16611.121410, 91323.723008, -9217.603410, -84232.250832, 44072.940747, -60470.771933, 47376.486542, 19785.643449, -74141.729284, -81806.848759, 34403.267913, -13973.165371, -48798.422802, -20894.039920, -38104.428921, -32488.142945, 4047.880293, -54026.109997, 99146.351590, -87810.892192, -29245.189835, -43464.327430, -12983.310076, -29775.234191, 65259.560103, 379.330207, -31178.333111, 78500.227741, -1872.495036, 93883.187587, 42445.673660, 76333.886537, 17394.628843, -16854.430580, 26596.133783, -15327.745771, -40010.595847, 53477.753118, 66216.627695, 63808.332473, -45209.605747, 61373.025107, -11226.800183, -15311.893268, 47484.245222, 94259.572273, 42402.273343, -2616.576467, 72938.046369, -57708.866182, 42473.217724, -31233.510291, -69096.584839, 40075.109015, 84795.600947, 55688.998872, 80012.203974, -28875.812190, -92635.007732, 71342.750304, -31988.280404, 47687.152546, -8496.759875, -70315.230444, 55389.932447, -36858.190582, -78150.660918, 96964.622124, -35788.274089, 97181.022610, -62662.599472, -40025.536726, 94309.502917, 78583.295615, 32561.432512, 30759.542053, -29127.825718, 39218.237061, 4236.728252, -49585.145204, -29642.945237, -63983.871887, 37449.022023, -62372.998789, 73842.986013, -28996.921064, 45289.518788, 68829.285430, 72548.129432, 91111.351457, 75128.996215, -19285.933410, -54055.665627, -5611.050417, -9911.675718, -4180.616322, -64614.763347, -23932.549428, -26566.954749, 0 + }; + float32_t f32_b_array[ARRAY_SIZE] = { + -14748.363506, -52882.384680, 25759.674589, -8430.675902, 74296.471371, -43863.727703, -523.083136, -77357.923759, 32783.353464, 14412.111012, -71393.350919, -84183.651778, 824.589092, 5762.424446, 50730.438763, 48260.466707, -64545.815296, -39900.156962, -42110.612503, 56969.361004, -51774.608591, 9524.295477, -56397.699274, 32974.695621, 54630.484822, 90917.121406, 58344.534264, -29546.804178, 29363.527509, -87659.765721, -80490.876894, 37360.782533, 83452.673319, -19566.741800, -64002.115525, -86502.336497, -86006.512493, 80838.557374, -14739.922414, -16896.379687, 8249.474651, 62724.054497, -1554.008023, -20395.188880, -31156.347950, 79891.105230, -45867.738768, 41333.044629, -7676.999956, 21771.713145, 82557.192605, 30500.710863, 31020.717681, 90597.001881, 99010.508568, 30322.571728, 40948.345159, -56276.504473, -61883.945216, -43079.002095, 29078.509077, 22794.228547, 74372.378733, -44055.068256, -53388.492633, -47784.325626, 14655.815561, 87444.174577, 87769.374380, -68921.250204, -68386.761085, -52032.613959, 59823.419305, 1754.801055, 95175.314736, -81105.314495, -34347.237022, 99133.704956, -1084.496731, -7528.947275, -8550.169841, 96866.053124, -32186.038563, 36079.172067, -25788.868160, 57515.787963, -89526.285196, -77820.605829, 49394.787719, -35410.274156, -2256.085487, -83347.534826, -19993.092476, -65402.603615, -35246.742498, -22573.751524, 54198.764622, -12551.651641, 38204.923509, 98339.464040, -78764.691121, -2536.506110, 62301.390849, -85946.411564, 25842.028436, 76980.636907, 66949.171540, -29600.343091, -67253.179681, 7999.959469, 51332.669028, -44266.161876, 63008.256158, 49447.784664, -8380.123077, 46.292316, -67452.730308, 93632.612589, -81494.922442, 83208.281900, -77996.866742, 53254.044501, -2066.082186, 89818.784744, -15978.453803, -58657.785681, 30989.308148, 63421.056711, 68160.313136, -44862.375309, -91802.269653, -10308.420264, 94507.850245, 43351.597128, -1687.669472, 8944.333835, -42358.233628, -66830.639128, 31335.273026, 1305.552391, 90904.188061, 26056.581575, 76717.070907, 69598.252599, -29449.914625, 51436.373685, -15138.962974, 78186.487897, -54861.987172, 15103.224330, -72401.041527, -79902.737504, -11792.134683, 35998.732785, -17947.048577, -35121.453671, 95234.578361, 33760.262870, -49548.979357, 33613.590186, -59180.165768, -12312.964538, 68976.756638, -98421.925464, 18748.996727, 87649.415189, -42603.968561, 66093.151677, -72649.431024, 58901.864996, -67727.390125, -93153.696522, -49001.478199, 51765.998867, 83230.060919, -40058.643283, -95872.550493, 37144.776727, 95117.125646, -49387.279353, -24978.646538, 51620.351258, -22826.467093, -27834.035075, 58073.389064, 51847.867995, -86010.948205, -41612.180492, 69343.113867, -95211.627972, 50191.674724, 29427.473654, 25573.797740, -58615.487098, 54218.880235, -32891.418497, 98733.460752, -63682.034121, 12563.683345, -75141.721838, 15118.782568, 37524.587438, -73081.462512, 4141.596016, 19532.955276, -71059.521486, 83329.657219, 24808.360451, 49712.670973, 55451.749620, -9809.453314, -87943.676689, -34302.161571, -94239.070472, 12611.124712, -38415.464213, -10883.611425, 2520.958779, 77365.058601, -77828.961437, 40915.821395, -65590.466499, -44446.352196, 43511.623038, -67237.562075, 38946.545673, -56447.758311, 8714.617727, 99568.415968, -45626.895014, 95102.601971, 43532.618006, 52518.777936, -31728.780028, -20026.763246, 71735.294631, -79396.329375, -16707.811932, 57955.715055, 4169.562060, -69506.060979, -67552.113568, -36282.586949, -31273.361532, -18139.073474, -22958.638140, 3438.475837, 86574.556610, -93725.007343, 8368.616620, 1270.601154, -21430.484085, -98146.567789, 96054.887155, 79600.800101, 45881.525507, 0 + }; + q7_t q7_a_array[ARRAY_SIZE] = { + -22, -117, 90, 77, 4, -73, 115, -93, 36, -25, -122, 12, -54, 113, 66, -122, -88, 20, 22, 70, -67, 6, 13, -42, 98, -80, 23, -94, 58, -62, 25, -116, -101, -80, 12, 10, -2, -90, -46, -118, -111, -120, 16, 8, 22, -65, 64, 70, 11, 86, -75, -19, -98, 49, 99, -89, -15, 125, 15, 5, 71, 98, -101, 34, -43, -73, -100, -127, 4, -39, -62, 83, -59, 68, -105, 52, 91, -22, 124, 17, -27, 47, -78, -82, 79, 49, -108, 41, 2, -85, -115, -27, -110, 21, -107, 49, -101, -108, 114, -4, -121, 32, -65, -30, -52, -92, -95, -111, 77, -12, 25, -43, -73, 15, 96, -11, 84, 28, 52, -97, -52, 46, 64, 11, 56, -10, -117, -116, 41, 93, -3, -19, 74, -28, -7, -86, 14, -116, 46, 113, 41, -99, -89, -53, 109, 78, 19, 16, 13, 112, 40, -46, -119, 120, -10, 23, 56, -126, 84, 32, 127, -114, -46, 124, 71, 56, 60, -101, 96, 94, -113, 70, -103, 69, 71, -120, -25, -78, 24, 39, 0, -63, -69, -65, -19, -52, -108, -78, -83, -108, 35, -70, 114, -91, -26, -24, 24, -20, 103, -126, 44, 112, 34, 18, 2, -30, 94, 29, 51, 116, -70, 58, -78, -15, -42, 43, 123, 43, -93, -11, -123, -35, -43, 109, -47, 34, 58, -75, -30, -98, -95, 47, 54, -25, -127, -40, 18, 8, -70, 122, -67, -9, 34, 126, 86, -1, -78, -118, 19, -69, -18, -108, 98, -8, 10, -99, 0 + }; + q7_t q7_b_array[ARRAY_SIZE] = { + 80, -7, 32, 18, 9, 28, -88, 74, -91, 30, -46, 49, 28, -37, -89, -63, -9, -69, -114, 6, 107, -12, -8, -29, 124, -113, 73, -31, 27, 12, 9, -49, 99, -79, -77, 59, -88, 71, -120, -20, -89, 1, -84, -26, 111, -54, -92, 105, 108, -83, -119, -30, 66, 2, -1, 40, -88, 53, 16, 85, 75, -122, -14, -53, -118, 78, 45, -8, -72, -52, 9, -63, -64, 64, -62, -125, -11, -71, 91, 36, -93, 74, 17, -97, 20, -56, 109, -33, -121, 104, -86, -21, -39, 2, -121, -72, 47, 47, 2, -123, 53, -104, -72, 8, 30, -18, 10, 104, -110, -83, 70, 34, -92, 32, -105, 70, 74, -57, 19, 109, -41, 17, 62, 80, 103, 98, 75, 118, 118, -54, 97, -93, 73, -112, -18, -50, -68, -10, -59, -112, 84, 100, -106, 70, 77, 114, -85, 104, 100, 53, -13, -18, -116, -74, -7, -116, 50, 77, -8, -27, 24, 28, -92, 68, 74, -119, 64, -30, -21, -35, -47, -13, -126, -27, 3, 83, -65, -126, -57, -116, -110, -105, 30, 45, -50, 108, -126, -83, 77, 90, 80, 84, 123, -49, -70, -3, 52, -20, -92, 8, 106, -101, -70, 105, -122, 50, -85, 21, 93, 85, -32, 31, -53, -5, 4, -88, -4, 87, 41, -27, -94, -26, -74, -47, 85, 10, -88, -94, 65, 34, 50, 121, -23, -68, -87, -93, -96, 26, 119, -83, -114, 50, -99, -61, -125, -107, -30, 98, 110, -81, 0, -94, -42, 21, -74, -35, 0 + }; + q15_t q15_a_array[ARRAY_SIZE] = { + 1982,1152,1883,65,2732,2402,2238,2440,1150,1852,1727,1591,826,746,1355,684,2414,2959,90,1607,262,2407,2968,201,2819,55,2052,2352,1603,2657,2698,1878,414,654,547,126,321,1850,2819,1064,1232,2954,2837,2030,2965,2301,1011,1988,733,887,2041,1584,1235,1808,2252,1751,1656,1751,1536,248,2159,2989,1064,2914,1040,2660,1365,1241,654,377,927,2179,2349,2082,30,2530,2767,2313,128,1135,2114,2189,673,808,2020,1433,1872,710,532,2489,2301,2804,324,547,298,1470,580,2688,298,133,1672,2318,936,537,1017,631,1531,2720,1887,305,1173,164,1504,1296,2993,2435,1457,2684,413,1171,2783,2753,2141,1856,1030,2809,375,2192,1940,2500,1195,2250,2506,968,1657,2938,1648,992,1859,1082,2270,1242,1478,2085,2919,984,2514,2218,2863,96,1071,1988,845,692,2134,1874,1772,1982,143,1047,1355,723,2146,2569,845,2194,414,2511,416,1765,1099,2421,1512,1469,2632,1060,1349,2891,127,2919,568,2002,1760,2026,1084,1861,2434,58,252,2925,1955,694,1211,367,806,774,995,457,1045,365,2653,283,2791,1198,143,1028,2208,2385,1635,2059,2681,165,911,139,587,2161,2166,2634,1748,213,2769,2402,858,1631,2955,2148,2517,1300,1412,1683,808,2248,1512,1941,924,417,1427,1088,2365,2341,2006,401,65,1680,903,2819,2943,860,2403,2689,1793,2653,2832,1648,2186,1731,78 + }; + q15_t q15_b_array[ARRAY_SIZE] = { + 1340,1939,1564,1117,2812,2489,2548,1118,1780,2618,2801,2006,621,1962,217,1221,2001,2802,2433,1454,2271,1252,2916,2964,2593,1167,1365,741,2354,2649,2742,1675,1797,447,2700,1352,618,2699,2288,2648,855,2020,1993,369,1222,826,2151,851,2689,2480,1171,1494,2085,2504,1829,1725,979,1370,2142,2654,2163,56,2025,1316,1314,352,2445,975,739,1029,1128,1640,1686,1188,1195,1547,1973,2853,2168,1201,2496,404,182,253,492,973,906,36,1620,287,440,1894,2578,2923,1713,2991,1661,1547,993,1291,1476,214,2664,194,1309,2480,1184,1841,2456,2659,2794,573,776,2694,1781,1512,1839,2459,1596,607,1362,1284,2899,1861,2087,2161,1041,1551,1671,470,1687,2085,1280,2509,2195,1081,1363,1160,2327,2203,1291,2082,2836,2353,2117,329,1170,1773,1379,152,687,2503,47,2592,235,2008,1501,654,1715,367,2014,1799,168,170,458,59,1306,2497,1853,1561,2592,294,2725,325,1551,430,1679,14,2301,2547,2751,2961,1516,815,303,1524,1757,2289,249,1985,1551,514,2816,1772,1322,2826,1968,1356,2520,1598,1662,2041,1102,718,1737,2601,1221,338,1332,901,1205,2501,1211,1171,1082,421,781,261,1289,772,893,1275,358,1486,2120,731,2356,223,1182,11,663,4,568,428,805,525,416,1797,2704,2819,664,1449,1129,1572,795,206,1309,522,79,2865,1292,2885,2288,23,2041,2118,1936 + }; + q31_t q31_a_array[ARRAY_SIZE] = { + 122675060, -19679606, 12005090, 128022795, -95284239, 1562872905, 214945602, 1304329431, -1508008274, 240787476, -905121314, 1622448750, 1128343957, 1088297819, 1929718262, 301748725, -1705937804, 412523122, 1868902555, 1990922011, 667241326, 1515133104, 122494706, -1539561650, 1117106510, 859507136, -940688492, -216177261, 1480104259, -634335848, 1983809950, -1406467930, -475661641, 1322061117, -825315378, -1807561254, 1449578423, 657148057, 1926668369, -1215598619, 412458663, -1807869491, 1422979790, 1023406889, -597431780, -1448317484, 1541343116, -2012852409, -43191490, -1215649277, -1017506653, -1915995397, -2080480350, 1094251372, 528600991, 143231710, 1391256474, -1041052209, 1278401986, 850686725, -2102619359, 1935527594, -431606953, -1976242055, -350139619, -589613336, 723038213, 166006808, 1760518450, 1386001502, -1457863745, -843865763, -1469590333, -605307148, -1892711295, 1107317389, 2133350043, 857819879, -798439008, -683125572, 1414380309, -1296729433, -972942965, -486754604, 428102856, -954668329, -2135465095, 1294752174, -2115260357, -1285371550, 142879568, -1259143073, 1988627270, 25731949, -1919745773, 1911174931, -835919509, -46679513, 275933135, 1724700061, 869122148, 473727312, -2018146537, 237804352, 145422132, 1233850002, -1329633347, 12780582, 1110157442, -1915661877, -928226928, -227663812, 828379127, -1674105026, 1927003415, -1639017283, -465311741, -658984229, -903260597, 490177562, 1126362032, -1034719085, -422641969, 1772346616, -1907663619, 1817734130, -1923639110, 1120016563, 141086779, -2102345903, 1724327426, -1866919811, -830684706, 1745078516, -1976128296, 799279002, -993799341, -1390877590, 904934458, -472067105, -455592220, 212192933, -34506575, 333518014, -85924850, -1599754424, 1355485624, -2014365016, -1127697814, -1076997804, 1705661182, -3234669, -632233921, 1798567554, -33103420, 4247767, -49163650, 779091592, -1163771871, 387580837, 127441404, 209878412, 61087762, 518500510, 836574845, 1629528554, -406038126, 459087674, -1103579310, 21540829, 1530951457, -1901138893, 809545038, -1083073633, -1608669130, -1714887885, 305376892, 905733099, 268734751, -1761301144, -1110601471, 581811091, 1926809483, 875843018, -409535295, -1494401242, -1492148258, 668320270, -1996003820, -470239924, 793927528, 1945752597, -336927405, -1078519032, 1673260004, -1226877022, 521095932, -572753832, 1860213970, 1198498531, 88542373, 1360949371, 656122057, 1792409478, 1656830983, -350299887, 1580672481, -1680928093, -2092549882, 876454682, -1735152678, 1646616771, 1189864260, 790291045, -337847342, 1947695906, -53101665, 1238647266, -89940713, -371577084, -1610381759, -402627031, 506455569, 430996275, 1774144323, 1310368600, -724205623, 370714565, 725347367, -1828596909, 365721697, -53655909, -1185780624, 1770739705, -2034892356, -418862235, 1739930005, -1498889924, -716521073, -263983575, -2042749120, -1263297029, 2060971911, -1666777591, 188198003, 251790886, 280390084, 1738016223, -580281801, 1831928083, -355653596, 1102400369, 2095795866, -294097927, 419052797, -1582812810, 0 + }; + q31_t q31_b_array[ARRAY_SIZE] = { + 204712319, 180144284, -209543243, 53916792, 197369355, 170830946, 1203514600, -312712536, 920743651, -1824625112, 420984875, 566536029, -506845364, -6857324, -434156189, -2142111505, 1045850978, -553910124, 824249774, -1488182567, -1675551882, -1925964935, 130855719, -1519925487, -589106798, 1494457749, -1565562513, -1262423706, -1230994795, -1088443954, 292519408, 1485212926, 242646787, -1088539142, -1274467679, 377739522, 159674802, -1547588366, -1949250075, -70691370, 781689702, -1835633981, 1942796846, -946887651, 848483564, -1548962935, 1870014462, 965663041, 1064259438, -383719640, -978783057, -944796566, 1430103113, -1260222873, -491040724, 1890727220, 2083502691, -556734811, -2113938357, -1585633018, 500105338, -886584662, 1336908666, -1311222963, 829306607, 910265989, 772979607, 626531703, 1646600062, -1937223716, -2024512853, -2067002399, -339307241, 1222434257, 1935277322, -231577250, -1724802316, 1907944900, 1658715575, -167516745, -58080523, 704490019, 1769573496, 32104716, 1064048689, -1318211013, 1016863918, 156537401, -1570152318, 131164953, 473324936, -196058652, -804227817, -9864755, 261520124, 1688883032, -1390111444, -522034107, 1274716973, 28982511, -1257583053, 1239694813, 1559794457, -1954406219, -416627738, -1691661573, 2039656472, -775687970, 729664130, 71135859, 2096190599, -1103089806, 1123796817, 694770500, -1976481918, -2134177767, -1583968644, -335906080, 2071961996, 1579203899, 262093988, 650393055, -338265896, -1505741655, 1175860682, 946357443, -1207168411, -225330030, -1176181106, 2011575645, -1754066324, -809543616, -1373368213, 358483112, 340851017, -997540864, -1584216501, 739788159, -1149806217, -1975988237, -1970552427, 1972302799, -448351628, 270309495, -2139626674, -2098878453, -1182495205, 2083627675, -610056538, -1743625393, 673599227, 1366000634, -1502388581, 1682967668, 42387805, 1022528321, -96259255, -151651019, 1907675374, -1465653629, 913779582, 199093513, -1083451962, 1172360491, -173772550, -1036446741, 2087691584, 954130802, -828357762, 916251036, 607400636, 1421070580, 1517590451, 979323974, -447508836, -1857041315, -1438039268, 2094707628, -1113865682, 1858121943, -1697925378, 1947565393, -2033040794, 826742982, -1017221207, -1265775408, 1775001649, -901031292, -1006552336, 28220675, 348700548, -2022106631, -1882248812, 2128053164, 447961767, 1419683607, -584893763, 1106977433, 486359498, 1533950699, 1837531408, 69590196, 1154641977, 1250545798, 505825431, 827243169, -632897439, -1841468473, 576227897, 1408476080, -251749351, -1814864257, -1767927418, -1694086470, -158656041, 1426194109, -1158397383, 896561495, 562232852, 973254663, -1206226163, -680189470, 522302066, -262726378, -74845893, -1057028022, 1845899344, 1161389957, -778331576, -11579864, 1225550271, -1500506478, 381609770, -1012049574, -1757206767, 96165946, 815148018, 265234274, 98201427, -826365919, -100542806, 1481517858, 1701987141, -1255526945, 611861026, -1118297781, 529286200, 1718060564, -6828272, -313800781, 1878684705, -2109937359, 732996262, 588183518, -872143020, -950440153, 0 + }; + /* clang-format on */ + float32_t f32_out_array[ARRAY_SIZE], f32_out_ref_array[ARRAY_SIZE]; + q7_t q7_out_array[ARRAY_SIZE], q7_out_ref_array[ARRAY_SIZE]; + q15_t q15_out_array[ARRAY_SIZE], q15_out_ref_array[ARRAY_SIZE]; + q31_t q31_out_array[ARRAY_SIZE], q31_out_ref_array[ARRAY_SIZE]; \ No newline at end of file diff --git a/examples/dsp/BasicMathFunctions_part2/clip.c b/examples/dsp/BasicMathFunctions_part2/clip.c new file mode 100644 index 00000000..28d08dd1 --- /dev/null +++ b/examples/dsp/BasicMathFunctions_part2/clip.c @@ -0,0 +1,71 @@ +#include "ref.h" + +void ref_clip_f32(const float32_t * pSrc, + float32_t * pDst, + float32_t low, + float32_t high, + uint32_t numSamples) +{ + for (uint32_t i = 0; i < numSamples; i++) + { + if (pSrc[i] > high) + pDst[i] = high; + else if (pSrc[i] < low) + pDst[i] = low; + else + pDst[i] = pSrc[i]; + } +} + +void ref_clip_q7(const q7_t * pSrc, + q7_t * pDst, + q7_t low, + q7_t high, + uint32_t numSamples) +{ + for (uint32_t i = 0; i < numSamples; i++) + { + if (pSrc[i] > high) + pDst[i] = high; + else if (pSrc[i] < low) + pDst[i] = low; + else + pDst[i] = pSrc[i]; + } +} + +void ref_clip_q15(const q15_t * pSrc, + q15_t * pDst, + q15_t low, + q15_t high, + uint32_t numSamples) +{ + for (uint32_t i = 0; i < numSamples; i++) + { + if (pSrc[i] > high) + pDst[i] = high; + else if (pSrc[i] < low) + pDst[i] = low; + else + pDst[i] = pSrc[i]; + } +} + +void ref_clip_q31(const q31_t * pSrc, + q31_t * pDst, + q31_t low, + q31_t high, + uint32_t numSamples) +{ + for (uint32_t i = 0; i < numSamples; i++) + { + if (pSrc[i] > high) + pDst[i] = high; + else if (pSrc[i] < low) + pDst[i] = low; + else + pDst[i] = pSrc[i]; + } +} + + diff --git a/examples/dsp/BasicMathFunctions_part2/main.c b/examples/dsp/BasicMathFunctions_part2/main.c new file mode 100644 index 00000000..c3781fb4 --- /dev/null +++ b/examples/dsp/BasicMathFunctions_part2/main.c @@ -0,0 +1,377 @@ +// +// Created by lujun on 19-6-21. +// +#include "riscv_math.h" +#include +#include +#include "array.h" +#include "../common.h" + +#include "../HelperFunctions/math_helper.c" +#include "../HelperFunctions/ref_helper.c" + +#include +#define DELTAF32 (0.05f) +#define DELTAQ31 (63) +#define DELTAQ15 (1) +#define DELTAQ7 (1) + +#define ENABLE_ALL +#define NEGATE +#define OFFSET +#define SCALE +#define SHIFT +#define SUB +#define CLIP + +int test_flag_error = 0; + +int main() +{ + int i; + + float32_t f32_out, f32_out_ref; + q7_t q7_out, q7_out_ref; + q15_t q15_out, q15_out_ref; + q31_t q31_out, q31_out_ref; + q63_t q63_out, q63_out_ref; + BENCH_INIT; +#if defined NEGATE || defined ENABLE_ALL + // **************************************** negate + // ******************************* f32_negate + BENCH_START(riscv_negate_f32); + riscv_negate_f32(f32_a_array, f32_out_array, ARRAY_SIZE); + BENCH_END(riscv_negate_f32); + ref_negate_f32(f32_a_array, f32_out_ref_array, ARRAY_SIZE); + for (int i = 0; i < ARRAY_SIZE; i++) + if (fabs(f32_out_array[i] - f32_out_ref_array[i]) > DELTAF32) { + BENCH_ERROR(riscv_negate_f32); + printf("index: %d, expect: %f, actual: %f\n", i, + f32_out_ref_array[i], f32_out_array[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_negate_f32); + + // riscv_negate_q7.c + BENCH_START(riscv_negate_q7); + riscv_negate_q7(q7_a_array, q7_out_array, ARRAY_SIZE); + BENCH_END(riscv_negate_q7); + ref_negate_q7(q7_a_array, q7_out_ref_array, ARRAY_SIZE); + for (int i = 0; i < ARRAY_SIZE; i++) + if (abs(q7_out_array[i] - q7_out_ref_array[i]) > DELTAQ7) { + BENCH_ERROR(riscv_negate_q7); + printf("index: %d, expect: %x, actual: %x\n", i, + q7_out_ref_array[i], q7_out_array[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_negate_q7); + + // riscv_negate_q15.c + BENCH_START(riscv_negate_q15); + riscv_negate_q15(q15_a_array, q15_out_array, ARRAY_SIZE); + BENCH_END(riscv_negate_q15); + ref_negate_q15(q15_a_array, q15_out_ref_array, ARRAY_SIZE); + for (int i = 0; i < ARRAY_SIZE; i++) + if (abs(q15_out_array[i] - q15_out_ref_array[i]) > DELTAQ15) { + BENCH_ERROR(riscv_negate_q15); + printf("index: %d, expect: %x, actual: %x\n", i, + q15_out_ref_array[i], q15_out_array[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_negate_q15); + + // riscv_negate_q31.c + BENCH_START(riscv_negate_q31); + riscv_negate_q31(q31_a_array, q31_out_array, ARRAY_SIZE); + BENCH_END(riscv_negate_q31); + ref_negate_q31(q31_a_array, q31_out_ref_array, ARRAY_SIZE); + for (int i = 0; i < ARRAY_SIZE; i++) + if (labs(q31_out_array[i] - q31_out_ref_array[i]) > DELTAQ31) { + BENCH_ERROR(riscv_negate_q31); + printf("index: %d, expect: %x, actual: %x\n", i, + q31_out_ref_array[i], q31_out_array[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_negate_q31); +#endif +#if defined OFFSET || defined ENABLE_ALL + // ************************************* offset + // ********************************** f32_offset + BENCH_START(riscv_offset_f32); + riscv_offset_f32(f32_a_array, 100, f32_out_array, ARRAY_SIZE); + BENCH_END(riscv_offset_f32); + ref_offset_f32(f32_a_array, 100, f32_out_ref_array, ARRAY_SIZE); + for (int i = 0; i < ARRAY_SIZE; i++) + if (fabs(f32_out_array[i] - f32_out_ref_array[i]) > DELTAF32) { + BENCH_ERROR(riscv_offset_f32); + printf("index: %d, expect: %f, actual: %f\n", i, + f32_out_ref_array[i], f32_out_array[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_offset_f32); + + // riscv_offset_q7.c + BENCH_START(riscv_offset_q7); + riscv_offset_q7(q7_a_array, 100, q7_out_array, ARRAY_SIZE); + BENCH_END(riscv_offset_q7); + ref_offset_q7(q7_a_array, 100, q7_out_ref_array, ARRAY_SIZE); + for (int i = 0; i < ARRAY_SIZE; i++) + if (abs(q7_out_array[i] - q7_out_ref_array[i]) > DELTAQ7) { + BENCH_ERROR(riscv_offset_q7); + printf("index: %d, expect: %x, actual: %x\n", i, + q7_out_ref_array[i], q7_out_array[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_offset_q7); + + // riscv_offset_q15.c + BENCH_START(riscv_offset_q15); + riscv_offset_q15(q15_a_array, 100, q15_out_array, ARRAY_SIZE); + BENCH_END(riscv_offset_q15); + ref_offset_q15(q15_a_array, 100, q15_out_ref_array, ARRAY_SIZE); + for (int i = 0; i < ARRAY_SIZE; i++) + if (abs(q15_out_array[i] - q15_out_ref_array[i]) > DELTAQ15) { + BENCH_ERROR(riscv_offset_q15); + printf("index:%d, expect: %x, actual: %x\n", i, + q15_out_ref_array[i], q15_out_array[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_offset_q15); + + // riscv_offset_q31.c + BENCH_START(riscv_offset_q31); + riscv_offset_q31(q31_a_array, 100, q31_out_array, ARRAY_SIZE); + BENCH_END(riscv_offset_q31); + ref_offset_q31(q31_a_array, 100, q31_out_ref_array, ARRAY_SIZE); + for (int i = 0; i < ARRAY_SIZE; i++) + if (labs(q31_out_array[i] - q31_out_ref_array[i]) > DELTAQ31) { + BENCH_ERROR(riscv_offset_q31); + printf("index: %d, expect: %x, actual: %x\n", i, + q31_out_ref_array[i], q31_out_array[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_offset_q31); +#endif +#if defined SCALE || defined ENABLE_ALL + // ************************************* scale *************************** + // f32_scale + BENCH_START(riscv_scale_f32); + riscv_scale_f32(f32_a_array, 3.5, f32_out_array, ARRAY_SIZE); + BENCH_END(riscv_scale_f32); + ref_scale_f32(f32_a_array, 3.5, f32_out_ref_array, ARRAY_SIZE); + for (int i = 0; i < ARRAY_SIZE; i++) + if (fabs(f32_out_array[i] - f32_out_ref_array[i]) > DELTAF32) { + BENCH_ERROR(riscv_scale_f32); + printf("index: %d, expect: %f, actual: %f\n", i, + f32_out_ref_array[i], f32_out_array[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_scale_f32); + + // riscv_scale_q7.c + BENCH_START(riscv_scale_q7); + riscv_scale_q7(q7_a_array, 6, 7, q7_out_array, ARRAY_SIZE); + BENCH_END(riscv_scale_q7); + ref_scale_q7(q7_a_array, 6, 7, q7_out_ref_array, ARRAY_SIZE); + for (int i = 0; i < ARRAY_SIZE; i++) + if (abs(q7_out_array[i] - q7_out_ref_array[i]) > DELTAQ7) { + BENCH_ERROR(riscv_scale_q7); + printf("index: %d, expect: %x, actual: %x\n", i, + q7_out_ref_array[i], q7_out_array[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_scale_q7); + + // riscv_scale_q15.c + BENCH_START(riscv_scale_q15); + riscv_scale_q15(q15_a_array, 15, 15, q15_out_array, ARRAY_SIZE); + BENCH_END(riscv_scale_q15); + ref_scale_q15(q15_a_array, 15, 15, q15_out_ref_array, ARRAY_SIZE); + for (int i = 0; i < ARRAY_SIZE; i++) + if (abs(q15_out_array[i] - q15_out_ref_array[i]) > DELTAQ15) { + BENCH_ERROR(riscv_scale_q15); + printf("index: %d, expect: %x, actual: %x\n", i, + q15_out_ref_array[i], q15_out_array[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_scale_q15); + + // riscv_scale_q31.c + BENCH_START(riscv_scale_q31); + riscv_scale_q31(q31_a_array, 987746463, -1, q31_out_array, ARRAY_SIZE); + BENCH_END(riscv_scale_q31); + ref_scale_q31(q31_a_array, 987746463, -1, q31_out_ref_array, ARRAY_SIZE); + for (int i = 0; i < ARRAY_SIZE; i++) + if (labs(q31_out_array[i] - q31_out_ref_array[i]) > DELTAQ31) { + BENCH_ERROR(riscv_scale_q31); + printf("index: %d, expect: %x, actual: %x\n", i, + q31_out_ref_array[i], q31_out_array[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_scale_q31); +#endif +#if defined SHIFT || defined ENABLE_ALL + // ************************************** shift + // ************************************** riscv_shift_q7.c + BENCH_START(riscv_shift_q7); + riscv_shift_q7(q7_a_array, -3, q7_out_array, ARRAY_SIZE); + BENCH_END(riscv_shift_q7); + ref_shift_q7(q7_a_array, -3, q7_out_ref_array, ARRAY_SIZE); + for (int i = 0; i < ARRAY_SIZE; i++) + if (abs(q7_out_array[i] - q7_out_ref_array[i]) > DELTAQ7) { + BENCH_ERROR(riscv_shift_q7); + printf("index: %d, expect: %x, actual: %x\n", i, + q7_out_ref_array[i], q7_out_array[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_shift_q7); + + // riscv_shift_q15.c + BENCH_START(riscv_shift_q15); + riscv_shift_q15(q15_a_array, -3, q15_out_array, ARRAY_SIZE); + BENCH_END(riscv_shift_q15); + ref_shift_q15(q15_a_array, -3, q15_out_ref_array, ARRAY_SIZE); + for (int i = 0; i < ARRAY_SIZE; i++) + if (abs(q15_out_array[i] - q15_out_ref_array[i]) > DELTAQ15) { + BENCH_ERROR(riscv_shift_q15); + printf("index:%d expect: %x, actual: %x\n", i, q15_out_ref_array[i], + q15_out_array[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_shift_q15); + + // riscv_shift_q31.c + BENCH_START(riscv_shift_q31); + riscv_shift_q31(q31_a_array, -3, q31_out_array, ARRAY_SIZE); + BENCH_END(riscv_shift_q31); + ref_shift_q31(q31_a_array, -3, q31_out_ref_array, ARRAY_SIZE); + for (int i = 0; i < ARRAY_SIZE; i++) + if (labs(q31_out_array[i] - q31_out_ref_array[i]) > DELTAQ31) { + BENCH_ERROR(riscv_shift_q31); + printf("index:%d, expect: %d, actual: %d\n", i, + q31_out_ref_array[i], q31_out_array[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_shift_q31); +#endif +#if defined SUB || defined ENABLE_ALL + // ************************************* sub + // **************************************** riscv_sub_f32.c + BENCH_START(riscv_sub_f32); + riscv_sub_f32(f32_a_array, f32_b_array, f32_out_array, ARRAY_SIZE); + BENCH_END(riscv_sub_f32); + ref_sub_f32(f32_a_array, f32_b_array, f32_out_ref_array, ARRAY_SIZE); + for (int i = 0; i < ARRAY_SIZE; i++) + if (fabs(f32_out_array[i] - f32_out_ref_array[i]) > DELTAF32) { + BENCH_ERROR(riscv_sub_f32); + printf("i: %d, expect: %f, actual: %f\n", i, f32_out_ref_array[i], + f32_out_array[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_sub_f32); + + // riscv_sub_q7.c + BENCH_START(riscv_sub_q7); + riscv_sub_q7(q7_a_array, q7_b_array, q7_out_array, ARRAY_SIZE); + BENCH_END(riscv_sub_q7); + ref_sub_q7(q7_a_array, q7_b_array, q7_out_ref_array, ARRAY_SIZE); + for (int i = 0; i < ARRAY_SIZE; i++) + if (abs(q7_out_array[i] - q7_out_ref_array[i]) > DELTAQ7) { + BENCH_ERROR(riscv_sub_q7); + printf("index: %d, expect: %x, actual: %x\n", i, + q7_out_ref_array[i], q7_out_array[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_sub_q7); + + // riscv_sub_q15.c + BENCH_START(riscv_sub_q15); + riscv_sub_q15(q15_a_array, q15_b_array, q15_out_array, ARRAY_SIZE); + BENCH_END(riscv_sub_q15); + ref_sub_q15(q15_a_array, q15_b_array, q15_out_ref_array, ARRAY_SIZE); + for (int i = 0; i < ARRAY_SIZE; i++) + if (abs(q15_out_array[i] - q15_out_ref_array[i]) > DELTAQ15) { + BENCH_ERROR(riscv_sub_q15); + printf("index: %d, expect: %x, actual: %x\n", i, + q15_out_ref_array[i], q15_out_array[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_sub_q15); + + // riscv_sub_q31.c + BENCH_START(riscv_sub_q31); + riscv_sub_q31(q31_a_array, q31_b_array, q31_out_array, ARRAY_SIZE); + BENCH_END(riscv_sub_q31); + ref_sub_q31(q31_a_array, q31_b_array, q31_out_ref_array, ARRAY_SIZE); + for (int i = 0; i < ARRAY_SIZE; i++) + if (labs(q31_out_array[i] - q31_out_ref_array[i]) > DELTAQ31) { + BENCH_ERROR(riscv_sub_q31); + printf("index: %d, expect: %x, actual: %x\n", i, + q31_out_ref_array[i], q31_out_array[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_sub_q31); +#endif +#if defined CLIP || defined ENABLE_ALL + BENCH_START(riscv_clip_f32); + riscv_clip_f32(f32_a_array, f32_out_array, -4230.37, 4230.45, ARRAY_SIZE); + BENCH_END(riscv_clip_f32); + ref_clip_f32(f32_a_array, f32_out_ref_array, -4230.37, 4230.45, ARRAY_SIZE); + for (int i = 0; i < ARRAY_SIZE; i++) + if (fabs(f32_out_array[i] - f32_out_ref_array[i]) > DELTAF32) { + BENCH_ERROR(riscv_clip_f32); + printf("i: %d, expect: %f, actual: %f\n", i, f32_out_ref_array[i], + f32_out_array[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_clip_f32); + + BENCH_START(riscv_clip_q7); + riscv_clip_q7(q7_a_array, q7_out_array, -100, 100, ARRAY_SIZE); + BENCH_END(riscv_clip_q7); + ref_clip_q7(q7_a_array, q7_out_ref_array, -100, 100, ARRAY_SIZE); + for (int i = 0; i < ARRAY_SIZE; i++) + if (abs(q7_out_array[i] - q7_out_ref_array[i]) > DELTAQ7) { + BENCH_ERROR(riscv_clip_q7); + printf("index: %d, expect: %x, actual: %x\n", i, + q7_out_ref_array[i], q7_out_array[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_clip_q7); + + BENCH_START(riscv_clip_q15); + riscv_clip_q15(q15_a_array, q15_out_array, -2638, 1000, ARRAY_SIZE); + BENCH_END(riscv_clip_q15); + ref_clip_q15(q15_a_array, q15_out_ref_array, -2638, 1000, ARRAY_SIZE); + for (int i = 0; i < ARRAY_SIZE; i++) + if (abs(q15_out_array[i] - q15_out_ref_array[i]) > DELTAQ15) { + BENCH_ERROR(riscv_clip_q15); + printf("index: %d, expect: %x, actual: %x\n", i, + q15_out_ref_array[i], q15_out_array[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_clip_q15); + + BENCH_START(riscv_clip_q31); + riscv_clip_q31(q31_a_array, q31_out_array, -214712319, 214712319, ARRAY_SIZE); + BENCH_END(riscv_clip_q31); + ref_clip_q31(q31_a_array, q31_out_ref_array, -214712319, 214712319, ARRAY_SIZE); + for (int i = 0; i < ARRAY_SIZE; i++) + if (abs(q31_out_array[i] - q31_out_ref_array[i]) > DELTAQ31) { + BENCH_ERROR(riscv_clip_q31); + printf("index: %d, expect: %x, actual: %x\n", i, + q31_out_ref_array[i], q31_out_array[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_clip_q31); +#endif /*defined CLIP || defined ENABLE_ALL*/ + + BENCH_FINISH; + if (test_flag_error) { + printf("test error apprears, please recheck.\n"); + return 1; + } else { + printf("all test are passed. Well done!\n"); + } + return 0; +}; diff --git a/examples/dsp/BasicMathFunctions_part2/negate.c b/examples/dsp/BasicMathFunctions_part2/negate.c new file mode 100644 index 00000000..ff135e29 --- /dev/null +++ b/examples/dsp/BasicMathFunctions_part2/negate.c @@ -0,0 +1,37 @@ +#include "ref.h" + +void ref_negate_f32(float32_t *pSrc, float32_t *pDst, uint32_t blockSize) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) { + pDst[i] = -pSrc[i]; + } +} + +void ref_negate_q31(q31_t *pSrc, q31_t *pDst, uint32_t blockSize) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) { + pDst[i] = -pSrc[i]; + } +} + +void ref_negate_q15(q15_t *pSrc, q15_t *pDst, uint32_t blockSize) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) { + pDst[i] = -pSrc[i]; + } +} + +void ref_negate_q7(q7_t *pSrc, q7_t *pDst, uint32_t blockSize) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) { + pDst[i] = -pSrc[i]; + } +} diff --git a/examples/dsp/BasicMathFunctions_part2/offset.c b/examples/dsp/BasicMathFunctions_part2/offset.c new file mode 100644 index 00000000..91ade19d --- /dev/null +++ b/examples/dsp/BasicMathFunctions_part2/offset.c @@ -0,0 +1,38 @@ +#include "ref.h" + +void ref_offset_f32(float32_t *pSrc, float32_t offset, float32_t *pDst, + uint32_t blockSize) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) { + pDst[i] = pSrc[i] + offset; + } +} + +void ref_offset_q31(q31_t *pSrc, q31_t offset, q31_t *pDst, uint32_t blockSize) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) { + pDst[i] = ref_sat_q31((q63_t)pSrc[i] + offset); + } +} + +void ref_offset_q15(q15_t *pSrc, q15_t offset, q15_t *pDst, uint32_t blockSize) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) { + pDst[i] = ref_sat_q15((q31_t)pSrc[i] + offset); + } +} + +void ref_offset_q7(q7_t *pSrc, q7_t offset, q7_t *pDst, uint32_t blockSize) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) { + pDst[i] = ref_sat_q7((q15_t)pSrc[i] + offset); + } +} diff --git a/examples/dsp/BasicMathFunctions_part2/scale.c b/examples/dsp/BasicMathFunctions_part2/scale.c new file mode 100644 index 00000000..3e53ce7c --- /dev/null +++ b/examples/dsp/BasicMathFunctions_part2/scale.c @@ -0,0 +1,50 @@ +#include "ref.h" + +void ref_scale_f32(float32_t *pSrc, float32_t scale, float32_t *pDst, + uint32_t blockSize) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) { + pDst[i] = pSrc[i] * scale; + } +} + +void ref_scale_q31(q31_t *pSrc, q31_t scaleFract, int8_t shift, q31_t *pDst, + uint32_t blockSize) +{ + uint32_t i; + int8_t kShift = shift + 1; /* Shift to apply after scaling */ + int8_t sign = (kShift & 0x80); + q63_t temp; + + for (i = 0; i < blockSize; i++) { + temp = ((q63_t)pSrc[i] * scaleFract) >> 32; + if (sign) + pDst[i] = temp >> -kShift; + else + pDst[i] = ref_sat_q31((q63_t)temp << kShift); + } +} + +void ref_scale_q15(q15_t *pSrc, q15_t scaleFract, int8_t shift, q15_t *pDst, + uint32_t blockSize) +{ + uint32_t i; + int8_t kShift = 15 - shift; /* Shift to apply after scaling */ + + for (i = 0; i < blockSize; i++) { + pDst[i] = ref_sat_q15(((q31_t)pSrc[i] * scaleFract) >> kShift); + } +} + +void ref_scale_q7(q7_t *pSrc, q7_t scaleFract, int8_t shift, q7_t *pDst, + uint32_t blockSize) +{ + uint32_t i; + int8_t kShift = 7 - shift; /* Shift to apply after scaling */ + + for (i = 0; i < blockSize; i++) { + pDst[i] = ref_sat_q7(((q15_t)pSrc[i] * scaleFract) >> kShift); + } +} diff --git a/examples/dsp/BasicMathFunctions_part2/shift.c b/examples/dsp/BasicMathFunctions_part2/shift.c new file mode 100644 index 00000000..28279860 --- /dev/null +++ b/examples/dsp/BasicMathFunctions_part2/shift.c @@ -0,0 +1,48 @@ +#include "ref.h" + +void ref_shift_q31(q31_t *pSrc, int8_t shiftBits, q31_t *pDst, + uint32_t blockSize) +{ + uint32_t i; + + if (shiftBits >= 0) { + for (i = 0; i < blockSize; i++) { + pDst[i] = pSrc[i] << shiftBits; + } + } else { + for (i = 0; i < blockSize; i++) { + pDst[i] = pSrc[i] >> -shiftBits; + } + } +} + +void ref_shift_q15(q15_t *pSrc, int8_t shiftBits, q15_t *pDst, + uint32_t blockSize) +{ + uint32_t i; + + if (shiftBits >= 0) { + for (i = 0; i < blockSize; i++) { + pDst[i] = pSrc[i] << shiftBits; + } + } else { + for (i = 0; i < blockSize; i++) { + pDst[i] = pSrc[i] >> -shiftBits; + } + } +} + +void ref_shift_q7(q7_t *pSrc, int8_t shiftBits, q7_t *pDst, uint32_t blockSize) +{ + uint32_t i; + + if (shiftBits >= 0) { + for (i = 0; i < blockSize; i++) { + pDst[i] = pSrc[i] << shiftBits; + } + } else { + for (i = 0; i < blockSize; i++) { + pDst[i] = pSrc[i] >> -shiftBits; + } + } +} diff --git a/examples/dsp/BasicMathFunctions_part2/sub.c b/examples/dsp/BasicMathFunctions_part2/sub.c new file mode 100644 index 00000000..0d19f1cf --- /dev/null +++ b/examples/dsp/BasicMathFunctions_part2/sub.c @@ -0,0 +1,38 @@ +#include "ref.h" + +void ref_sub_f32(float32_t *pSrcA, float32_t *pSrcB, float32_t *pDst, + uint32_t blockSize) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) { + pDst[i] = pSrcA[i] - pSrcB[i]; + } +} + +void ref_sub_q31(q31_t *pSrcA, q31_t *pSrcB, q31_t *pDst, uint32_t blockSize) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) { + pDst[i] = ref_sat_q31((q63_t)pSrcA[i] - pSrcB[i]); + } +} + +void ref_sub_q15(q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, uint32_t blockSize) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) { + pDst[i] = ref_sat_q15((q31_t)pSrcA[i] - pSrcB[i]); + } +} + +void ref_sub_q7(q7_t *pSrcA, q7_t *pSrcB, q7_t *pDst, uint32_t blockSize) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) { + pDst[i] = ref_sat_q7((q15_t)pSrcA[i] - pSrcB[i]); + } +} diff --git a/examples/dsp/BasicMathFunctions_part3/CMakeLists.txt b/examples/dsp/BasicMathFunctions_part3/CMakeLists.txt new file mode 100644 index 00000000..807896b4 --- /dev/null +++ b/examples/dsp/BasicMathFunctions_part3/CMakeLists.txt @@ -0,0 +1,5 @@ +set(TARGET_REQUIRED_PRIVATE_INCLUDE ${CMAKE_CURRENT_SOURCE_DIR} ${CMAKE_CURRENT_SOURCE_DIR}/..) +set(TARGET_REQUIRED_SRCS and.c not.c or.c xor.c) +set(TARGET_REQUIRED_LIBS nmsis) +set(mains main.c) +generate_bin() \ No newline at end of file diff --git a/examples/dsp/BasicMathFunctions_part3/and.c b/examples/dsp/BasicMathFunctions_part3/and.c new file mode 100644 index 00000000..60521922 --- /dev/null +++ b/examples/dsp/BasicMathFunctions_part3/and.c @@ -0,0 +1,51 @@ +#include "ref.h" + +void ref_and_u16( + const uint16_t * pSrcA, + const uint16_t * pSrcB, + uint16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + blkCnt = blockSize; + while (blkCnt > 0U) + { + *pDst++ = (*pSrcA++)&(*pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } +} + +void ref_and_u32( + const uint32_t * pSrcA, + const uint32_t * pSrcB, + uint32_t * pDst, + uint32_t blockSize) +{ + /* Initialize blkCnt with number of samples */ + uint32_t blkCnt = blockSize; + while (blkCnt > 0U) + { + *pDst++ = (*pSrcA++)&(*pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } +} + +void ref_and_u8( + const uint8_t * pSrcA, + const uint8_t * pSrcB, + uint8_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt = blockSize; + while (blkCnt > 0U) + { + *pDst++ = (*pSrcA++)&(*pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } +} diff --git a/examples/dsp/BasicMathFunctions_part3/array.h b/examples/dsp/BasicMathFunctions_part3/array.h new file mode 100644 index 00000000..0a0d6591 --- /dev/null +++ b/examples/dsp/BasicMathFunctions_part3/array.h @@ -0,0 +1,14 @@ +// Array for BasicMathFunctions part3 +#define ARRAY_SIZE 128 +uint16_t u16_a_array[ARRAY_SIZE] = {65123,14331,6933,7189,4167,26514,29384,23974,50037,41149,50592,61135,63749,12584,9101,45630,6148,34432,34756,56435,31775,25785,44002,48579,34082,22787,9830,38410,17179,2913,49475,15911,28993,45075,23542,48256,25867,44788,46140,28986,1283,21683,27807,17712,12914,53852,28175,58180,25636,50404,26004,52986,49484,24732,14157,51800,62213,21467,43991,28747,54624,50387,10961,56490,64872,33713,57952,38536,10141,13098,26670,49067,54105,51771,20874,35000,5895,7320,8932,44476,32451,12432,32440,9673,3602,55752,36736,60922,45656,38193,53437,57607,64809,34,56717,40145,64877,34582,31426,52517,14931,32643,59038,37660,55389,48407,38403,16169,43674,5471,41022,43315,47825,58376,64376,50399,38105,60837,38016,1112,7920,56538,31738,55368,13723,36194,41280,2096}; +uint16_t u16_b_array[ARRAY_SIZE] = {22536,38277,7062,59395,57648,53592,17087,38951,1475,27869,20494,10583,11715,27714,6175,39224,30862,45609,45867,41846,2202,4509,20945,34790,42889,26713,53738,47078,63481,34821,21308,6922,40039,51039,27751,5952,17463,10070,18415,28841,34546,29977,57368,33951,61841,41792,62763,15774,44310,18944,44027,45556,4455,16697,14682,43767,55338,22574,51152,44258,440,39463,25347,60030,75,30307,27810,30206,50473,21133,51428,30890,2343,11526,47301,31030,10008,22355,39805,12566,48393,15915,60124,17633,50167,12364,18841,5971,37762,44784,35821,27900,42234,42442,44500,41666,61942,13692,46483,15481,7824,39800,29500,30063,43381,50481,22951,43385,27273,55176,54586,16806,40203,38158,35437,57012,17352,20845,7812,61592,42306,31422,41898,35698,42422,35644,47254,34242}; +uint16_t u16_out_array[ARRAY_SIZE]; +uint16_t u16_out_array_ref[ARRAY_SIZE]; +uint32_t u32_a_array[ARRAY_SIZE] = {1492233325,2837327656,1648703087,2694432711,92985245,3910868321,3438373247,3203390553,3492292942,1646288102,2651194115,2471731601,2276554737,1181415605,1067853250,1939773748,978019140,3455084652,4235285469,128814445,2300660180,373993811,3444956505,4248345038,287531990,4034685242,78071912,2937064481,3366122550,2294103385,3802589886,3861196639,2688381633,592142813,935450722,782289964,179614948,459310926,2647604608,4035813307,1522375772,1763638512,4227748553,4061231692,2906166764,4244725895,3293515729,1446112329,2844908427,1048681921,1269193978,2921343859,2267084873,1767780679,2588311437,3223459095,2506255899,2369930805,2506416722,2198249817,354733061,3090530196,4278457919,1522713245,4171524847,1487986099,3807676892,1952899574,1775656685,935152112,539682343,1326778076,3118594787,3362409950,2979795116,42100352,3621573710,3961385766,3311223164,183222686,1624297090,3025115652,3133234672,963262683,1155581273,2890646842,2050813373,2678841594,1015523252,760740732,3563291208,3293903482,4013553621,463379318,782661176,425610997,2103519512,829982374,3847825010,425586804,189689686,2393564468,3317841049,1339772345,768723895,1455803552,902568638,2191088388,3892805126,2701207748,436084731,1678708380,234576576,2152993718,1854228314,4284489076,3485806542,2085858039,3841623858,590758126,1675058352,3982964658,3940606004,3064777043,2655738840,1474410261,4020206756,535900424}; +uint32_t u32_b_array[ARRAY_SIZE] = {3137840234,2776599429,3578360531,1710609144,3220461867,3587244777,1384956860,2371945583,4205327602,2359262184,1419158597,2660610070,1548922278,3249183748,1777690179,2114606121,2983899465,4177860224,1407696836,3598337271,3174291045,4098148084,137106649,1532740624,2846076546,1209039990,989487739,3054273870,2682520252,2536644849,2836559466,204245765,1498019345,1938493031,1034679084,3071094947,3677274943,1209066344,3139839405,591687117,3593696983,595289836,2526340073,1572631483,3465005860,2163721999,2102791673,3766895583,1516732537,1930345376,4138331070,181667658,4178824225,812637203,2865259871,2518738966,2899585749,1550577894,2664075558,3483866523,82710235,360233975,4186741280,2797524939,993158858,1732981263,524074135,1152935958,1107440868,1424491353,653840106,1494681517,522519082,3797408467,404922602,3994494073,1713777717,203587729,1470482999,3160950583,3413133876,2340353012,2947307331,3838123203,235328945,1304215694,198391223,839566306,3093088569,3099906705,3770118303,2501530534,303586908,3963157751,3437571961,1228132396,2335015805,4229581731,3073813892,3603346982,1860839940,2021317762,2408245762,1155739379,3217009822,2164181507,2778026363,1321757210,595817775,2042570197,1556750757,3384921400,3351345031,2871238097,573394711,92581830,2404497522,1292007844,4034733998,4212949037,1231025196,3439496942,3848768947,2566357105,3796822969,4053296105,2358616025,3128397590}; +uint32_t u32_out_array[ARRAY_SIZE]; +uint32_t u32_out_array_ref[ARRAY_SIZE]; +uint8_t u8_a_array[ARRAY_SIZE] = {252,9,226,233,203,25,67,85,174,34,184,27,167,126,199,183,231,228,85,178,50,7,190,128,122,231,156,158,220,206,147,46,61,226,7,125,42,250,182,128,120,15,174,10,18,133,24,209,209,184,38,168,132,249,166,204,116,110,211,21,34,44,100,212,205,15,102,134,106,168,160,74,110,3,251,42,27,95,50,125,86,243,235,13,188,68,108,140,241,106,251,77,179,170,138,178,170,45,32,255,43,8,143,225,171,48,94,117,251,40,219,165,96,48,109,123,30,150,57,98,149,64,74,157,67,211,251,186}; +uint8_t u8_b_array[ARRAY_SIZE] = {233,46,67,37,34,222,148,140,37,218,159,89,131,102,19,61,31,47,61,106,12,231,241,125,125,86,230,94,28,199,99,61,103,24,33,241,244,147,15,60,90,210,3,11,43,166,187,165,115,140,75,190,48,175,46,94,160,199,20,237,198,124,111,114,78,130,130,209,203,164,96,207,136,89,240,224,140,159,150,53,77,120,59,216,49,57,43,58,111,79,236,110,47,231,250,112,28,66,104,152,67,154,182,56,30,75,81,108,130,21,67,205,7,237,186,125,148,60,117,246,139,133,59,125,159,173,101,94}; +uint8_t u8_out_array[ARRAY_SIZE]; +uint8_t u8_out_array_ref[ARRAY_SIZE]; \ No newline at end of file diff --git a/examples/dsp/BasicMathFunctions_part3/main.c b/examples/dsp/BasicMathFunctions_part3/main.c new file mode 100644 index 00000000..0047849f --- /dev/null +++ b/examples/dsp/BasicMathFunctions_part3/main.c @@ -0,0 +1,204 @@ +// +// Created by lujun on 19-6-21. +// +#include "riscv_math.h" +#include +#include +#include "array.h" +#include "../common.h" + +#include "../HelperFunctions/math_helper.c" +#include "../HelperFunctions/ref_helper.c" + +#include +#define DELTAF32 (0.05f) +#define DELTAQ31 (63) +#define DELTAQ15 (1) +#define DELTAQ7 (1) + +#define ENABLE_ALL +#define AND +#define OR +#define NOT +#define XOR + +int test_flag_error = 0; + +int main() +{ + int i; + + BENCH_INIT; +#if defined AND || defined ENABLE_ALL + BENCH_START(riscv_and_u16); + riscv_and_u16(u16_a_array, u16_b_array, u16_out_array, ARRAY_SIZE); + BENCH_END(riscv_and_u16); + ref_and_u16(u16_a_array, u16_b_array, u16_out_array_ref, ARRAY_SIZE); + for (int i = 0; i < ARRAY_SIZE; i++) + if (abs(u16_out_array[i] - u16_out_array_ref[i]) > DELTAF32) { + BENCH_ERROR(riscv_and_u16); + printf("index: %d, expect: %d, actual: %d\n", i, + u16_out_array_ref[i], u16_out_array[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_and_u16); + + BENCH_START(riscv_and_u32); + riscv_and_u32(u32_a_array, u32_b_array, u32_out_array, ARRAY_SIZE); + BENCH_END(riscv_and_u32); + ref_and_u32(u32_a_array, u32_b_array, u32_out_array_ref, ARRAY_SIZE); + for (int i = 0; i < ARRAY_SIZE; i++) + if (abs(u32_out_array[i] - u32_out_array_ref[i]) > DELTAF32) { + BENCH_ERROR(riscv_and_u32); + printf("index: %d, expect: %d, actual: %d\n", i, + u32_out_array_ref[i], u32_out_array[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_and_u32); + + BENCH_START(riscv_and_u8); + riscv_and_u8(u8_a_array, u8_b_array, u8_out_array, ARRAY_SIZE); + BENCH_END(riscv_and_u8); + ref_and_u8(u8_a_array, u8_b_array, u8_out_array_ref, ARRAY_SIZE); + for (int i = 0; i < ARRAY_SIZE; i++) + if (abs(u8_out_array[i] - u8_out_array_ref[i]) > DELTAF32) { + BENCH_ERROR(riscv_and_u8); + printf("index: %d, expect: %d, actual: %d\n", i, + u8_out_array_ref[i], u8_out_array[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_and_u8); +#endif /*defined AND || defined ENABLE_ALL*/ + +#if defined OR || defined ENABLE_ALL + BENCH_START(riscv_or_u16); + riscv_or_u16(u16_a_array, u16_b_array, u16_out_array, ARRAY_SIZE); + BENCH_END(riscv_or_u16); + ref_or_u16(u16_a_array, u16_b_array, u16_out_array_ref, ARRAY_SIZE); + for (int i = 0; i < ARRAY_SIZE; i++) + if (abs(u16_out_array[i] - u16_out_array_ref[i]) > DELTAF32) { + BENCH_ERROR(riscv_or_u16); + printf("index: %d, expect: %d, actual: %d\n", i, + u16_out_array_ref[i], u16_out_array[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_or_u16); + + BENCH_START(riscv_or_u32); + riscv_or_u32(u32_a_array, u32_b_array, u32_out_array, ARRAY_SIZE); + BENCH_END(riscv_or_u32); + ref_or_u32(u32_a_array, u32_b_array, u32_out_array_ref, ARRAY_SIZE); + for (int i = 0; i < ARRAY_SIZE; i++) + if (abs(u32_out_array[i] - u32_out_array_ref[i]) > DELTAF32) { + BENCH_ERROR(riscv_or_u32); + printf("index: %d, expect: %d, actual: %d\n", i, + u32_out_array_ref[i], u32_out_array[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_or_u32); + + BENCH_START(riscv_or_u8); + riscv_or_u8(u8_a_array, u8_b_array, u8_out_array, ARRAY_SIZE); + BENCH_END(riscv_or_u8); + ref_or_u8(u8_a_array, u8_b_array, u8_out_array_ref, ARRAY_SIZE); + for (int i = 0; i < ARRAY_SIZE; i++) + if (abs(u8_out_array[i] - u8_out_array_ref[i]) > DELTAF32) { + BENCH_ERROR(riscv_or_u8); + printf("index: %d, expect: %d, actual: %d\n", i, + u8_out_array_ref[i], u8_out_array[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_or_u8); +#endif /*defined OR || defined ENABLE_ALL*/ + +#if defined NOT || defined ENABLE_ALL + BENCH_START(riscv_not_u16); + riscv_not_u16(u16_a_array, u16_out_array, ARRAY_SIZE); + BENCH_END(riscv_not_u16); + ref_not_u16(u16_a_array, u16_out_array_ref, ARRAY_SIZE); + for (int i = 0; i < ARRAY_SIZE; i++) + if (abs(u16_out_array[i] - u16_out_array_ref[i]) > DELTAF32) { + BENCH_ERROR(riscv_not_u16); + printf("index: %d, expect: %d, actual: %d\n", i, + u16_out_array_ref[i], u16_out_array[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_not_u16); + + BENCH_START(riscv_not_u32); + riscv_not_u32(u32_a_array, u32_out_array, ARRAY_SIZE); + BENCH_END(riscv_not_u32); + ref_not_u32(u32_a_array, u32_out_array_ref, ARRAY_SIZE); + for (int i = 0; i < ARRAY_SIZE; i++) + if (abs(u32_out_array[i] - u32_out_array_ref[i]) > DELTAF32) { + BENCH_ERROR(riscv_not_u32); + printf("index: %d, expect: %d, actual: %d\n", i, + u32_out_array_ref[i], u32_out_array[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_not_u32); + + BENCH_START(riscv_not_u8); + riscv_not_u8(u8_a_array, u8_out_array, ARRAY_SIZE); + BENCH_END(riscv_not_u8); + ref_not_u8(u8_a_array, u8_out_array_ref, ARRAY_SIZE); + for (int i = 0; i < ARRAY_SIZE; i++) + if (abs(u8_out_array[i] - u8_out_array_ref[i]) > DELTAF32) { + BENCH_ERROR(riscv_not_u8); + printf("index: %d, expect: %d, actual: %d\n", i, + u8_out_array_ref[i], u8_out_array[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_not_u8); +#endif /*defined NOT || defined ENABLE_ALL*/ + +#if defined XOR || defined ENABLE_ALL + BENCH_START(riscv_xor_u16); + riscv_xor_u16(u16_a_array, u16_b_array, u16_out_array, ARRAY_SIZE); + BENCH_END(riscv_xor_u16); + ref_xor_u16(u16_a_array, u16_b_array, u16_out_array_ref, ARRAY_SIZE); + for (int i = 0; i < ARRAY_SIZE; i++) + if (abs(u16_out_array[i] - u16_out_array_ref[i]) > DELTAF32) { + BENCH_ERROR(riscv_xor_u16); + printf("index: %d, expect: %d, actual: %d\n", i, + u16_out_array_ref[i], u16_out_array[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_xor_u16); + + BENCH_START(riscv_xor_u32); + riscv_xor_u32(u32_a_array, u32_b_array, u32_out_array, ARRAY_SIZE); + BENCH_END(riscv_xor_u32); + ref_xor_u32(u32_a_array, u32_b_array, u32_out_array_ref, ARRAY_SIZE); + for (int i = 0; i < ARRAY_SIZE; i++) + if (abs(u32_out_array[i] - u32_out_array_ref[i]) > DELTAF32) { + BENCH_ERROR(riscv_xor_u32); + printf("index: %d, expect: %d, actual: %d\n", i, + u32_out_array_ref[i], u32_out_array[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_xor_u32); + + BENCH_START(riscv_xor_u8); + riscv_xor_u8(u8_a_array, u8_b_array, u8_out_array, ARRAY_SIZE); + BENCH_END(riscv_xor_u8); + ref_xor_u8(u8_a_array, u8_b_array, u8_out_array_ref, ARRAY_SIZE); + for (int i = 0; i < ARRAY_SIZE; i++) + if (abs(u8_out_array[i] - u8_out_array_ref[i]) > DELTAF32) { + BENCH_ERROR(riscv_xor_u8); + printf("index: %d, expect: %d, actual: %d\n", i, + u8_out_array_ref[i], u8_out_array[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_xor_u8); +#endif /*defined XOR || defined ENABLE_ALL*/ + BENCH_FINISH; + + if (test_flag_error) { + printf("test error apprears, please recheck.\n"); + return 1; + } else { + printf("all test are passed. Well done!\n"); + } + return 0; +}; diff --git a/examples/dsp/BasicMathFunctions_part3/not.c b/examples/dsp/BasicMathFunctions_part3/not.c new file mode 100644 index 00000000..fcd98910 --- /dev/null +++ b/examples/dsp/BasicMathFunctions_part3/not.c @@ -0,0 +1,54 @@ +#include "ref.h" + +void ref_not_u16( + const uint16_t * pSrc, + uint16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt = blockSize; /* Loop counter */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + *pDst++ = ~(*pSrc++); + + /* Decrement the loop counter */ + blkCnt--; + } +} + +void ref_not_u32( + const uint32_t * pSrc, + uint32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + *pDst++ = ~(*pSrc++); + + /* Decrement the loop counter */ + blkCnt--; + } +} + +void ref_not_u8( + const uint8_t * pSrc, + uint8_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + *pDst++ = ~(*pSrc++); + + /* Decrement the loop counter */ + blkCnt--; + } +} + + diff --git a/examples/dsp/BasicMathFunctions_part3/or.c b/examples/dsp/BasicMathFunctions_part3/or.c new file mode 100644 index 00000000..afce8d2f --- /dev/null +++ b/examples/dsp/BasicMathFunctions_part3/or.c @@ -0,0 +1,54 @@ +#include "ref.h" + +void ref_or_u16( + const uint16_t * pSrcA, + const uint16_t * pSrcB, + uint16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + *pDst++ = (*pSrcA++)|(*pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } +} + +void ref_or_u32( + const uint32_t * pSrcA, + const uint32_t * pSrcB, + uint32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + blkCnt = blockSize; + while (blkCnt > 0U) + { + *pDst++ = (*pSrcA++)|(*pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } +} + +void ref_or_u8( + const uint8_t * pSrcA, + const uint8_t * pSrcB, + uint8_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + blkCnt = blockSize; + while (blkCnt > 0U) + { + *pDst++ = (*pSrcA++)|(*pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } +} + diff --git a/examples/dsp/BasicMathFunctions_part3/xor.c b/examples/dsp/BasicMathFunctions_part3/xor.c new file mode 100644 index 00000000..c04e9d6a --- /dev/null +++ b/examples/dsp/BasicMathFunctions_part3/xor.c @@ -0,0 +1,51 @@ +#include "ref.h" + +void ref_xor_u16( + const uint16_t * pSrcA, + const uint16_t * pSrcB, + uint16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt = blockSize; + while (blkCnt > 0U) + { + *pDst++ = (*pSrcA++)^(*pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } +} + +void ref_xor_u32( + const uint32_t * pSrcA, + const uint32_t * pSrcB, + uint32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt = blockSize; + + while (blkCnt > 0U) + { + *pDst++ = (*pSrcA++)^(*pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } +} + +void ref_xor_u8( + const uint8_t * pSrcA, + const uint8_t * pSrcB, + uint8_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt = blockSize; + + while (blkCnt > 0U) + { + *pDst++ = (*pSrcA++)^(*pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } +} diff --git a/examples/dsp/BayesianFunctions_part1/CMakeLists.txt b/examples/dsp/BayesianFunctions_part1/CMakeLists.txt new file mode 100644 index 00000000..6a0b0998 --- /dev/null +++ b/examples/dsp/BayesianFunctions_part1/CMakeLists.txt @@ -0,0 +1,4 @@ +set(TARGET_REQUIRED_PRIVATE_INCLUDE ${CMAKE_CURRENT_SOURCE_DIR} ${CMAKE_CURRENT_SOURCE_DIR}/..) +set(TARGET_REQUIRED_LIBS nmsis) +set(mains main.c) +generate_bin() \ No newline at end of file diff --git a/examples/dsp/BayesianFunctions_part1/main.c b/examples/dsp/BayesianFunctions_part1/main.c new file mode 100644 index 00000000..17d27595 --- /dev/null +++ b/examples/dsp/BayesianFunctions_part1/main.c @@ -0,0 +1,103 @@ +#include "riscv_math.h" +#include +#include +#include "../common.h" + +#include "../HelperFunctions/math_helper.c" +#include "../HelperFunctions/ref_helper.c" + +#include +#define DELTAF32 (0.05f) +#define DELTAQ31 (63) +#define DELTAQ15 (1) +#define DELTAQ7 (1) + +int test_flag_error = 0; + +/* +Those parameters can be generated with the python library scikit-learn. +*/ +riscv_gaussian_naive_bayes_instance_f32 S; + +#define NB_OF_CLASSES 3 +#define VECTOR_DIMENSION 2 + +const float32_t theta[NB_OF_CLASSES*VECTOR_DIMENSION] = {1.525400412246743, 1.1286029390034396, -1.5547934054920127, 0.9976789084710983, -0.14944114212609047, -3.0461975645866857}; /**< Mean values for the Gaussians */ + +const float32_t sigma[NB_OF_CLASSES*VECTOR_DIMENSION] = {0.8790413342380022, 1.0687689375338891, 0.9512598687040021, 0.9514543522981638, 1.0755900156857314, 0.9088718773623725}; /**< Variances for the Gaussians */ + +const float32_t classPriors[NB_OF_CLASSES] = {0.3333333333333333f, 0.3333333333333333f, 0.3333333333333333f}; /**< Class prior probabilities */ + +int32_t main(void) +{ + BENCH_INIT; + /* Array of input data */ + float32_t in[2]; + + /* Result of the classifier */ + float32_t result[NB_OF_CLASSES]; + float32_t pBufferB[NB_OF_CLASSES]; + float32_t maxProba; + uint32_t index; + + S.vectorDimension = VECTOR_DIMENSION; + S.numberOfClasses = NB_OF_CLASSES; + S.theta = theta; + S.sigma = sigma; + S.classPriors = classPriors; + S.epsilon=4.731813637210494e-09f; + + in[0] = 1.5f; + in[1] = 1.0f; + BENCH_START(riscv_gaussian_naive_bayes_predict_f32); + riscv_gaussian_naive_bayes_predict_f32(&S, in, result, pBufferB); + BENCH_END(riscv_gaussian_naive_bayes_predict_f32); + riscv_max_f32(result, NB_OF_CLASSES, &maxProba, &index); + /* Index should be 0 : First class */ + for(int i=0;i> 14) - + (((q63_t)pSrcA[i + 1] * pSrcB[i + 1]) >> 14); + sumi += (((q63_t)pSrcA[i] * pSrcB[i + 1]) >> 14) + + (((q63_t)pSrcA[i + 1] * pSrcB[i]) >> 14); + } + + *realResult = sumr; + *imagResult = sumi; +} + +void ref_cmplx_dot_prod_q15(q15_t *pSrcA, q15_t *pSrcB, uint32_t numSamples, + q31_t *realResult, q31_t *imagResult) +{ + q63_t sumr, sumi; + uint32_t i; + + sumr = 0; + sumi = 0; + + for (i = 0; i < numSamples * 2; i += 2) { + sumr += (q31_t)pSrcA[i] * pSrcB[i] - (q31_t)pSrcA[i + 1] * pSrcB[i + 1]; + sumi += (q31_t)pSrcA[i] * pSrcB[i + 1] + (q31_t)pSrcA[i + 1] * pSrcB[i]; + } + + // shifting down 6 at the end here because there are already 32 guard bits + // available, this method is more accurate + *realResult = (q31_t)(sumr >> 6); + *imagResult = (q31_t)(sumi >> 6); +} diff --git a/examples/dsp/ComplexMathFunctions/cmplx_mag.c b/examples/dsp/ComplexMathFunctions/cmplx_mag.c new file mode 100644 index 00000000..3f7069fc --- /dev/null +++ b/examples/dsp/ComplexMathFunctions/cmplx_mag.c @@ -0,0 +1,37 @@ +#include "ref.h" + +void ref_cmplx_mag_f32(float32_t *pSrc, float32_t *pDst, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples * 2; i += 2) { + *pDst++ = sqrtf(pSrc[i] * pSrc[i] + pSrc[i + 1] * pSrc[i + 1]); + } +} + +void ref_cmplx_mag_q31(q31_t *pSrc, q31_t *pDst, uint32_t numSamples) +{ + uint32_t i; + q31_t acc0, acc1, out; + + for (i = 0; i < numSamples * 2; i += 2) { + acc0 = (q31_t)(((q63_t)pSrc[i] * pSrc[i]) >> 33); + acc1 = (q31_t)(((q63_t)pSrc[i + 1] * pSrc[i + 1]) >> 33); + out = acc0 + acc1; + *pDst++ = (q31_t)(sqrtf((float)out / 2147483648.0f) * 2147483648.0f); + } +} + +void ref_cmplx_mag_q15(q15_t *pSrc, q15_t *pDst, uint32_t numSamples) +{ + uint32_t i; + q31_t acc0, acc1; + q15_t out; + + for (i = 0; i < numSamples * 2; i += 2) { + acc0 = pSrc[i] * pSrc[i]; + acc1 = pSrc[i + 1] * pSrc[i + 1]; + out = (q15_t)(((q63_t)acc0 + acc1) >> 17); + *pDst++ = (q15_t)(sqrtf((float)out / 32768.0f) * 32768.0f); + } +} diff --git a/examples/dsp/ComplexMathFunctions/cmplx_mag_squared.c b/examples/dsp/ComplexMathFunctions/cmplx_mag_squared.c new file mode 100644 index 00000000..705fb739 --- /dev/null +++ b/examples/dsp/ComplexMathFunctions/cmplx_mag_squared.c @@ -0,0 +1,35 @@ +#include "ref.h" + +void ref_cmplx_mag_squared_f32(float32_t *pSrc, float32_t *pDst, + uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples * 2; i += 2) { + *pDst++ = pSrc[i] * pSrc[i] + pSrc[i + 1] * pSrc[i + 1]; + } +} + +void ref_cmplx_mag_squared_q31(q31_t *pSrc, q31_t *pDst, uint32_t numSamples) +{ + uint32_t i; + q31_t acc0, acc1; + + for (i = 0; i < numSamples * 2; i += 2) { + acc0 = (q31_t)(((q63_t)pSrc[i] * pSrc[i]) >> 33); + acc1 = (q31_t)(((q63_t)pSrc[i + 1] * pSrc[i + 1]) >> 33); + *pDst++ = acc0 + acc1; + } +} + +void ref_cmplx_mag_squared_q15(q15_t *pSrc, q15_t *pDst, uint32_t numSamples) +{ + uint32_t i; + q31_t acc0, acc1; + + for (i = 0; i < numSamples * 2; i += 2) { + acc0 = pSrc[i] * pSrc[i]; + acc1 = pSrc[i + 1] * pSrc[i + 1]; + *pDst++ = (q15_t)(((q63_t)acc0 + acc1) >> 17); + } +} diff --git a/examples/dsp/ComplexMathFunctions/cmplx_mult_cmplx.c b/examples/dsp/ComplexMathFunctions/cmplx_mult_cmplx.c new file mode 100644 index 00000000..b923f350 --- /dev/null +++ b/examples/dsp/ComplexMathFunctions/cmplx_mult_cmplx.c @@ -0,0 +1,44 @@ +#include "ref.h" + +void ref_cmplx_mult_cmplx_f32(float32_t *pSrcA, float32_t *pSrcB, + float32_t *pDst, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples * 2; i += 2) { + pDst[i] = pSrcA[i] * pSrcB[i] - pSrcA[i + 1] * pSrcB[i + 1]; + pDst[i + 1] = pSrcA[i] * pSrcB[i + 1] + pSrcA[i + 1] * pSrcB[i]; + } +} + +void ref_cmplx_mult_cmplx_q31(q31_t *pSrcA, q31_t *pSrcB, q31_t *pDst, + uint32_t numSamples) +{ + uint32_t i; + q31_t mul1, mul2, mul3, mul4; + + for (i = 0; i < numSamples * 2; i += 2) { + mul1 = ((q63_t)pSrcA[i] * pSrcB[i]) >> 33; + mul2 = ((q63_t)pSrcA[i + 1] * pSrcB[i + 1]) >> 33; + mul3 = ((q63_t)pSrcA[i] * pSrcB[i + 1]) >> 33; + mul4 = ((q63_t)pSrcA[i + 1] * pSrcB[i]) >> 33; + pDst[i] = mul1 - mul2; + pDst[i + 1] = mul3 + mul4; + } +} + +void ref_cmplx_mult_cmplx_q15(q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, + uint32_t numSamples) +{ + uint32_t i; + q31_t mul1, mul2, mul3, mul4; + + for (i = 0; i < numSamples * 2; i += 2) { + mul1 = ((q31_t)pSrcA[i] * pSrcB[i]) >> 17; + mul2 = ((q31_t)pSrcA[i + 1] * pSrcB[i + 1]) >> 17; + mul3 = ((q31_t)pSrcA[i] * pSrcB[i + 1]) >> 17; + mul4 = ((q31_t)pSrcA[i + 1] * pSrcB[i]) >> 17; + pDst[i] = mul1 - mul2; + pDst[i + 1] = mul3 + mul4; + } +} diff --git a/examples/dsp/ComplexMathFunctions/cmplx_mult_real.c b/examples/dsp/ComplexMathFunctions/cmplx_mult_real.c new file mode 100644 index 00000000..dc32beb4 --- /dev/null +++ b/examples/dsp/ComplexMathFunctions/cmplx_mult_real.c @@ -0,0 +1,40 @@ +#include "ref.h" + +void ref_cmplx_mult_real_f32(float32_t *pSrcCmplx, float32_t *pSrcReal, + float32_t *pCmplxDst, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) { + pCmplxDst[2 * i + 0] = pSrcCmplx[2 * i + 0] * pSrcReal[i]; + pCmplxDst[2 * i + 1] = pSrcCmplx[2 * i + 1] * pSrcReal[i]; + } +} + +void ref_cmplx_mult_real_q31(q31_t *pSrcCmplx, q31_t *pSrcReal, + q31_t *pCmplxDst, uint32_t numSamples) +{ + uint32_t i; + q31_t tempR, tempI; + + for (i = 0; i < numSamples; i++) { + tempR = ((q63_t)pSrcCmplx[2 * i + 0] * pSrcReal[i]) >> 32; + tempI = ((q63_t)pSrcCmplx[2 * i + 1] * pSrcReal[i]) >> 32; + pCmplxDst[2 * i + 0] = ref_sat_n(tempR, 31) << 1; + pCmplxDst[2 * i + 1] = ref_sat_n(tempI, 31) << 1; + } +} + +void ref_cmplx_mult_real_q15(q15_t *pSrcCmplx, q15_t *pSrcReal, + q15_t *pCmplxDst, uint32_t numSamples) +{ + uint32_t i; + q31_t tempR, tempI; + + for (i = 0; i < numSamples; i++) { + tempR = ((q31_t)pSrcCmplx[2 * i + 0] * pSrcReal[i]) >> 15; + tempI = ((q31_t)pSrcCmplx[2 * i + 1] * pSrcReal[i]) >> 15; + pCmplxDst[2 * i + 0] = ref_sat_q15(tempR); + pCmplxDst[2 * i + 1] = ref_sat_q15(tempI); + } +} diff --git a/examples/dsp/ComplexMathFunctions/main.c b/examples/dsp/ComplexMathFunctions/main.c new file mode 100644 index 00000000..dd3f92fc --- /dev/null +++ b/examples/dsp/ComplexMathFunctions/main.c @@ -0,0 +1,399 @@ +// +// Created by lujun on 19-6-28. +// +// This contains complx calculate in Conjugate, Dot Product, Magnitude, +// Magnitude Squared, by-Complex Multiplication, by-Real Multiplication each one +// has it's own function. All function can be found in main function. If you +// don't want to use it, then comment it. contains following functions,eachone +// includes q15,q31 and f32 versions +#include "riscv_math.h" +#include +#include "array.h" +#include "../common.h" + +#include "../HelperFunctions/math_helper.c" +#include "../HelperFunctions/ref_helper.c" + +#include +#include +#define DELTAF32 (2.0f) +#define DELTAQ31 (63) +#define DELTAQ15 (1) +#define DELTAQ7 (1) + +#define ENABLE_ALL +#define CmplxMag +#define CmplxDotProduct +#define CONJ +#define MagSquared +#define CmplxMult +#define CmplxMultReal + +int test_flag_error = 0; + +/* +********************************************************************************************************* +* DSP_MagSquared +********************************************************************************************************* +*/ +static int DSP_MagSquared(void) +{ + uint8_t i; + /**********************************************************************************/ + BENCH_START(riscv_cmplx_mag_squared_f32); + riscv_cmplx_mag_squared_f32(f32_pSrcA, f32_pDst, ARRAY_SIZE); + BENCH_END(riscv_cmplx_mag_squared_f32); + ref_cmplx_mag_squared_f32(f32_pSrcA, f32_pDst_ref, ARRAY_SIZE); + for (i = 0; i < ARRAY_SIZE; i++) { + if (fabs(f32_pDst[i] - f32_pDst_ref[i]) > DELTAF32) { + BENCH_ERROR(riscv_cmplx_mag_squared_f32); + printf("index: %d, expect: %f, actual: %f\n", i, f32_pDst_ref[i], + f32_pDst[i]); + test_flag_error = 1; + } + } + BENCH_STATUS(riscv_cmplx_mag_squared_f32); + /***Q31*******************************************************************************/ + BENCH_START(riscv_cmplx_mag_squared_q31); + riscv_cmplx_mag_squared_q31(q31_pSrcA, q31_pDst, ARRAY_SIZE); + BENCH_END(riscv_cmplx_mag_squared_q31); + ref_cmplx_mag_squared_q31(q31_pSrcA, q31_pDst_ref, ARRAY_SIZE); + for (i = 0; i < ARRAY_SIZE; i++) { + if (labs(q31_pDst[i] - q31_pDst_ref[i]) > DELTAQ31) { + BENCH_ERROR(riscv_cmplx_mag_squared_q31); + printf("index: %d, expect: %x, actual: %x\n", i, q31_pDst_ref[i], + q31_pDst[i]); + test_flag_error = 1; + } + } + BENCH_STATUS(riscv_cmplx_mag_squared_q31); + /***Q15*******************************************************************************/ + BENCH_START(riscv_cmplx_mag_squared_q15); + riscv_cmplx_mag_squared_q15(q15_pSrcA, q15_pDst, ARRAY_SIZE); + BENCH_END(riscv_cmplx_mag_squared_q15); + ref_cmplx_mag_squared_q15(q15_pSrcA, q15_pDst_ref, ARRAY_SIZE); + for (i = 0; i < ARRAY_SIZE; i++) { + if (abs(q15_pDst[i] - q15_pDst_ref[i]) > DELTAQ15) { + BENCH_ERROR(riscv_cmplx_mag_squared_q15); + printf("index: %d, expect: %x, actual: %x\n", i, q15_pDst_ref[i], + q15_pDst[i]); + test_flag_error = 1; + } + } + BENCH_STATUS(riscv_cmplx_mag_squared_q15); +} +/* +********************************************************************************************************* +* DSP_CmplxMult +********************************************************************************************************* +*/ +static int DSP_CmplxMult(void) +{ + uint8_t i; + /**********************************************************************************/ + BENCH_START(riscv_cmplx_mult_cmplx_f32); + riscv_cmplx_mult_cmplx_f32(f32_pSrcA, f32_pSrcB, f32_pDst, ARRAY_SIZE); + BENCH_END(riscv_cmplx_mult_cmplx_f32); + ref_cmplx_mult_cmplx_f32(f32_pSrcA, f32_pSrcB, f32_pDst_ref, ARRAY_SIZE); + for (i = 0; i < ARRAY_SIZE; i++) { + if (fabs(f32_pDst[i] - f32_pDst_ref[i]) > DELTAF32) { + BENCH_ERROR(riscv_cmplx_mult_cmplx_f32); + printf("index: %d, expect: %f, actual: %f\n", i, f32_pDst_ref[i], + f32_pDst[i]); + test_flag_error = 1; + } + } + BENCH_STATUS(riscv_cmplx_mult_cmplx_f32); + /***Q31*******************************************************************************/ + BENCH_START(riscv_cmplx_mult_cmplx_q31); + riscv_cmplx_mult_cmplx_q31(q31_pSrcA, q31_pSrcB, q31_pDst, ARRAY_SIZE); + BENCH_END(riscv_cmplx_mult_cmplx_q31); + ref_cmplx_mult_cmplx_q31(q31_pSrcA, q31_pSrcB, q31_pDst_ref, ARRAY_SIZE); + for (i = 0; i < ARRAY_SIZE; i++) { + if (labs(q31_pDst[i] - q31_pDst_ref[i]) > DELTAQ31) { + BENCH_ERROR(riscv_cmplx_mult_cmplx_q31); + printf("index: %d, expect: %x, actual: %x\n", i, q31_pDst_ref[i], + q31_pDst[i]); + test_flag_error = 1; + } + } + BENCH_STATUS(riscv_cmplx_mult_cmplx_q31); + /***Q15*******************************************************************************/ + BENCH_START(riscv_cmplx_mult_cmplx_q15); + riscv_cmplx_mult_cmplx_q15(q15_pSrcA, q15_pSrcB, q15_pDst, ARRAY_SIZE); + BENCH_END(riscv_cmplx_mult_cmplx_q15); + ref_cmplx_mult_cmplx_q15(q15_pSrcA, q15_pSrcB, q15_pDst_ref, ARRAY_SIZE); + for (i = 0; i < ARRAY_SIZE; i++) { + if (abs(q15_pDst[i] - q15_pDst_ref[i]) > DELTAQ15) { + BENCH_ERROR(riscv_cmplx_mult_cmplx_q15); + printf("index: %d, expect: %x, actual: %x\n", i, q15_pDst_ref[i], + q15_pDst[i]); + test_flag_error = 1; + } + } + BENCH_STATUS(riscv_cmplx_mult_cmplx_q15); +} + +/* +********************************************************************************************************* +* DSP_CmplxMultReal +********************************************************************************************************* +*/ +static int DSP_CmplxMultReal(void) +{ + uint8_t i; + /**********************************************************************************/ + BENCH_START(riscv_cmplx_mult_real_f32); + riscv_cmplx_mult_real_f32(f32_pSrcA, f32_pSrcB, f32_pDst, + ARRAY_SIZE); + BENCH_END(riscv_cmplx_mult_real_f32); + ref_cmplx_mult_real_f32(f32_pSrcA, f32_pSrcB, f32_pDst_ref, + ARRAY_SIZE); + for (i = 0; i < ARRAY_SIZE * 2; i++) { + if (fabs(f32_pDst[i] - f32_pDst_ref[i]) > DELTAF32) { + BENCH_ERROR(riscv_cmplx_mult_real_f32); + printf("index: %d, expect: %f, actual: %f\n", i, + f32_pDst_ref[i], f32_pDst[i]); + test_flag_error = 1; + } + } + BENCH_STATUS(riscv_cmplx_mult_real_f32); + /***Q31*******************************************************************************/ + BENCH_START(riscv_cmplx_mult_real_q31); + riscv_cmplx_mult_real_q31(q31_pSrcA, q31_pSrcB, q31_pDst, + ARRAY_SIZE); + BENCH_END(riscv_cmplx_mult_real_q31); + ref_cmplx_mult_real_q31(q31_pSrcA, q31_pSrcB, q31_pDst_ref, + ARRAY_SIZE); + for (i = 0; i < ARRAY_SIZE * 2; i++) { + if (labs(q31_pDst[i] - q31_pDst_ref[i]) > DELTAQ31) { + BENCH_ERROR(riscv_cmplx_mult_real_q31); + printf("index: %d, expect: %x, actual: %x\n", i, + q31_pDst_ref[i], q31_pDst[i]); + test_flag_error = 1; + } + } + BENCH_STATUS(riscv_cmplx_mult_real_q31); + /***Q15*******************************************************************************/ + BENCH_START(riscv_cmplx_mult_real_q15); + riscv_cmplx_mult_real_q15(q15_pSrcA, q15_pSrcB, q15_pDst, + ARRAY_SIZE); + BENCH_END(riscv_cmplx_mult_real_q15); + ref_cmplx_mult_real_q15(q15_pSrcA, q15_pSrcB, q15_pDst_ref, + ARRAY_SIZE); + for (i = 0; i < ARRAY_SIZE * 2; i++) { + if (abs(q15_pDst[i] - q15_pDst_ref[i]) > DELTAQ15) { + BENCH_ERROR(riscv_cmplx_mult_real_q15); + printf("index: %d, expect: %x, actual: %x\n", i, + q15_pDst_ref[i], q15_pDst[i]); + test_flag_error = 1; + } + } + BENCH_STATUS(riscv_cmplx_mult_real_q15); +} + +/* +********************************************************************************************************* +* DSP_CONJ +********************************************************************************************************* +*/ +static int DSP_CONJ(void) +{ + uint8_t i; + /**********************************************************************************/ + BENCH_START(riscv_cmplx_conj_f32); + riscv_cmplx_conj_f32(f32_pSrcA, f32_pDst, ARRAY_SIZE); + BENCH_END(riscv_cmplx_conj_f32); + ref_cmplx_conj_f32(f32_pSrcA, f32_pDst_ref, ARRAY_SIZE); + for (i = 0; i < ARRAY_SIZE; i++) { + if (fabs(f32_pDst[i] - f32_pDst_ref[i]) > DELTAF32) { + BENCH_ERROR(riscv_cmplx_conj_f32); + printf("index: %d, expect: %f, actual: %f\n", i, f32_pDst_ref[i], + f32_pDst[i]); + test_flag_error = 1; + } + } + BENCH_STATUS(riscv_cmplx_conj_f32); + /***Q31*******************************************************************************/ + BENCH_START(riscv_cmplx_conj_q31); + riscv_cmplx_conj_q31(q31_pSrcA, q31_pDst, ARRAY_SIZE); + BENCH_END(riscv_cmplx_conj_q31); + ref_cmplx_conj_q31(q31_pSrcA, q31_pDst_ref, ARRAY_SIZE); + for (i = 0; i < ARRAY_SIZE; i++) { + if (labs(q31_pDst[i] - q31_pDst_ref[i]) > DELTAQ31) { + BENCH_ERROR(riscv_cmplx_conj_q31); + printf("index: %d, expect: %x, actual: %x\n", i, q31_pDst_ref[i], + q31_pDst[i]); + test_flag_error = 1; + } + } + BENCH_STATUS(riscv_cmplx_conj_q31); + /***Q15*******************************************************************************/ + BENCH_START(riscv_cmplx_conj_q15); + riscv_cmplx_conj_q15(q15_pSrcA, q15_pDst, ARRAY_SIZE); + BENCH_END(riscv_cmplx_conj_q15); + ref_cmplx_conj_q15(q15_pSrcA, q15_pDst_ref, ARRAY_SIZE); + for (i = 0; i < ARRAY_SIZE; i++) { + if (abs(q15_pDst[i] - q15_pDst_ref[i]) > DELTAQ15) { + BENCH_ERROR(riscv_cmplx_conj_q15); + printf("index: %d, expect: %x, actual: %x\n", i, q15_pDst_ref[i], + q15_pDst[i]); + test_flag_error = 1; + } + } + BENCH_STATUS(riscv_cmplx_conj_q15); +} + +/* +********************************************************************************************************* +* DSP_CmplxDotProduct +********************************************************************************************************* +*/ +static int DSP_CmplxDotProduct(void) +{ + float32_t f32_realResult; + float32_t f32_imagResult; + float32_t f32_realResult_ref; + float32_t f32_imagResult_ref; + q63_t q31_realResult; + q63_t q31_imagResult; + q63_t q31_realResult_ref; + q63_t q31_imagResult_ref; + q31_t q15_realResult; + q31_t q15_imagResult; + q31_t q15_realResult_ref; + q31_t q15_imagResult_ref; + /* clang-format on */ + + /**********************************************************************************/ + BENCH_START(riscv_cmplx_dot_prod_f32); + riscv_cmplx_dot_prod_f32(f32_pSrcA, f32_pSrcB, ARRAY_SIZE, &f32_realResult, + &f32_imagResult); + BENCH_END(riscv_cmplx_dot_prod_f32); + ref_cmplx_dot_prod_f32(f32_pSrcA, f32_pSrcB, ARRAY_SIZE, + &f32_realResult_ref, &f32_imagResult_ref); + if ((fabs(f32_realResult - f32_realResult_ref) > DELTAF32) || + (fabs(f32_imagResult - f32_imagResult_ref) > DELTAF32)) { + BENCH_ERROR(riscv_cmplx_dot_prod_f32); + printf("real expect: %f, actual: %f\nimag expect: %f, actual: %f\n", + f32_realResult_ref, f32_realResult, f32_imagResult_ref, + f32_imagResult); + test_flag_error = 1; + } + BENCH_STATUS(riscv_cmplx_dot_prod_f32); + /***Q31*******************************************************************************/ + BENCH_START(riscv_cmplx_dot_prod_q31); + riscv_cmplx_dot_prod_q31(q31_pSrcA, q31_pSrcB, ARRAY_SIZE, &q31_realResult, + &q31_imagResult); + BENCH_END(riscv_cmplx_dot_prod_q31); + ref_cmplx_dot_prod_q31(q31_pSrcA, q31_pSrcB, ARRAY_SIZE, + &q31_realResult_ref, &q31_imagResult_ref); + if ((labs(q31_realResult - q31_realResult_ref) > DELTAQ31) || + (labs(q31_imagResult - q31_imagResult_ref) > DELTAQ31)) { + BENCH_ERROR(riscv_cmplx_dot_prod_q31); + printf("real expect: %x, actual: %x\nimag expect: %x, actual: %x\n", + q31_realResult_ref, q31_realResult, q31_imagResult_ref, + q31_imagResult); + test_flag_error = 1; + } + BENCH_STATUS(riscv_cmplx_dot_prod_q31); + /***Q15*******************************************************************************/ + BENCH_START(riscv_cmplx_dot_prod_q15); + riscv_cmplx_dot_prod_q15(q15_pSrcA, q15_pSrcB, ARRAY_SIZE, &q15_realResult, + &q15_imagResult); + BENCH_END(riscv_cmplx_dot_prod_q15); + ref_cmplx_dot_prod_q15(q15_pSrcA, q15_pSrcB, ARRAY_SIZE, + &q15_realResult_ref, &q15_imagResult_ref); + if ((abs(q15_realResult - q15_realResult_ref) > DELTAQ15) || + (abs(q15_imagResult - q15_imagResult_ref) > DELTAQ15)) { + BENCH_ERROR(riscv_cmplx_dot_prod_q15); + printf("real expect: %x, actual: %x\nimag expect: %x, actual: %x\n", + q15_realResult_ref, q15_realResult, q15_imagResult_ref, + q15_imagResult); + test_flag_error = 1; + } + BENCH_STATUS(riscv_cmplx_dot_prod_q15); +} + +/* +********************************************************************************************************* +* DSP_CmplxMag +********************************************************************************************************* +*/ +static int DSP_CmplxMag(void) +{ + uint8_t i; + /**********************************************************************************/ + BENCH_START(riscv_cmplx_mag_f32); + riscv_cmplx_mag_f32(f32_pSrcA, f32_pDst, ARRAY_SIZE); + BENCH_END(riscv_cmplx_mag_f32); + ref_cmplx_mag_f32(f32_pSrcA, f32_pDst_ref, ARRAY_SIZE); + for (i = 0; i < ARRAY_SIZE; i++) { + if (fabs(f32_pDst[i] - f32_pDst_ref[i]) > DELTAF32) { + BENCH_ERROR(riscv_cmplx_mag_f32); + printf("index: %d, expect: %f, actual: %f\n", i, f32_pDst_ref[i], + f32_pDst[i]); + test_flag_error = 1; + } + } + BENCH_STATUS(riscv_cmplx_mag_f32); + /***Q31*******************************************************************************/ + BENCH_START(riscv_cmplx_mag_q31); + riscv_cmplx_mag_q31(q31_pSrcA, q31_pDst, ARRAY_SIZE); + BENCH_END(riscv_cmplx_mag_q31); + ref_cmplx_mag_q31(q31_pSrcA, q31_pDst_ref, ARRAY_SIZE); + for (i = 0; i < ARRAY_SIZE; i++) { + if (labs(q31_pDst[i] - q31_pDst_ref[i]) > DELTAQ31) { + BENCH_ERROR(riscv_cmplx_mag_q31); + printf("index: %d, expect: %x, actual: %x\n", i, q31_pDst_ref[i], + q31_pDst[i]); + test_flag_error = 1; + } + } + BENCH_STATUS(riscv_cmplx_mag_q31); + /***Q15*******************************************************************************/ + BENCH_START(riscv_cmplx_mag_q15); + riscv_cmplx_mag_q15(q15_pSrcA, q15_pDst, ARRAY_SIZE); + BENCH_END(riscv_cmplx_mag_q15); + ref_cmplx_mag_q15(q15_pSrcA, q15_pDst_ref, ARRAY_SIZE); + for (i = 0; i < ARRAY_SIZE; i++) { + if (abs(q15_pDst[i] - q15_pDst_ref[i]) > DELTAQ15) { + BENCH_ERROR(riscv_cmplx_mag_q15); + printf("index: %d, expect: %x, actual: %x\n", i, q15_pDst_ref[i], + q15_pDst[i]); + test_flag_error = 1; + } + } + BENCH_STATUS(riscv_cmplx_mag_q15); +} + +int main() +{ + BENCH_INIT; +#if defined CmplxMag || defined ENABLE_ALL + DSP_CmplxMag(); +#endif +#if defined CmplxDotProduct || defined ENABLE_ALL + DSP_CmplxDotProduct(); +#endif +#if defined CONJ || defined ENABLE_ALL + DSP_CONJ(); +#endif +#if defined MagSquared || defined ENABLE_ALL + DSP_MagSquared(); +#endif +#if defined CmplxMult || defined ENABLE_ALL + DSP_CmplxMult(); +#endif +#if defined CmplxMultReal || defined ENABLE_ALL + DSP_CmplxMultReal(); +#endif + BENCH_FINISH; + if (test_flag_error) { + printf("test error apprears, please recheck.\n"); + return 1; + } else { + printf("all test are passed. Well done!\n"); + } + return 0; +} diff --git a/examples/dsp/ControllerFunctions_pidpart/CMakeLists.txt b/examples/dsp/ControllerFunctions_pidpart/CMakeLists.txt new file mode 100644 index 00000000..c1e4e3c1 --- /dev/null +++ b/examples/dsp/ControllerFunctions_pidpart/CMakeLists.txt @@ -0,0 +1,5 @@ +set(TARGET_REQUIRED_PRIVATE_INCLUDE ${CMAKE_CURRENT_SOURCE_DIR} ${CMAKE_CURRENT_SOURCE_DIR}/..) +set(TARGET_REQUIRED_SRCS pid.c) +set(TARGET_REQUIRED_LIBS nmsis) +set(mains main.c) +generate_bin() \ No newline at end of file diff --git a/examples/dsp/ControllerFunctions_pidpart/array.h b/examples/dsp/ControllerFunctions_pidpart/array.h new file mode 100644 index 00000000..0d5eb55f --- /dev/null +++ b/examples/dsp/ControllerFunctions_pidpart/array.h @@ -0,0 +1,4 @@ +// Array for ControllerFunctions pidpart + float32_t output[100], output_ref[100]; + q31_t output_q31[100], output_q31_ref[100]; + q15_t output_q15[100], output_q15_ref[100]; \ No newline at end of file diff --git a/examples/dsp/ControllerFunctions_pidpart/main.c b/examples/dsp/ControllerFunctions_pidpart/main.c new file mode 100644 index 00000000..5cae2b13 --- /dev/null +++ b/examples/dsp/ControllerFunctions_pidpart/main.c @@ -0,0 +1,414 @@ +// This contains SIN_COS , clarke, inv_clarke, park, inv_park and pid +// each one has it's own function. +// All function can be found in main function. +// If you don't want to use it, then comment it. +#include "riscv_math.h" +#include +#include +#include "array.h" +#include "../common.h" + +#include "../HelperFunctions/math_helper.c" +#include "../HelperFunctions/ref_helper.c" + +#include +#define DELTAF32 (0.05f) +#define DELTAQ31 (63) +#define DELTAQ15 (1) +#define DELTAQ7 (1) + +#define ENABLE_ALL +#define CLARKE +#define INV_CLARKE +#define PARK +#define INV_PARK +#define PID + +int test_flag_error = 0; + +static int DSP_clarke_f32_app() +{ + float32_t Ia = sin(30 * PI / 180); + float32_t Ib = sin(150 * PI / 180); + + float32_t pIalpha, pIalpha_ref; + float32_t pIbeta, pIbeta_ref; + + BENCH_START(riscv_clarke_f32); + for (int i = 0; i < 1000; i++) + riscv_clarke_f32(Ia, Ib, &pIalpha, &pIbeta); + BENCH_END(riscv_clarke_f32); + pIalpha_ref = 0.500000; + pIbeta_ref = 0.866025; + if ((fabs(pIalpha - pIalpha_ref) > DELTAF32) || + (fabs(pIbeta - pIbeta_ref) > DELTAF32)) { + BENCH_ERROR(riscv_clarke_f32); + printf("pIalpha expect: %f, actual: %f\npIbeta expect: %f, actual: %f", + pIalpha_ref, pIalpha, pIbeta_ref, pIbeta); + test_flag_error = 1; + } + BENCH_STATUS(riscv_clarke_f32); +} + +static int DSP_clarke_q31_app() +{ + + const float32_t Ia = sin(30 * PI / 180); + const float32_t Ib = sin(150 * PI / 180); + + q31_t Ia1; + q31_t Ib1; + + riscv_float_to_q31(&Ia, &Ia1, 1); + riscv_float_to_q31(&Ib, &Ib1, 1); + + q31_t pIalpha, pIalpha_ref; + q31_t pIbeta, pIbeta_ref; + + BENCH_START(riscv_clarke_q31); + for (int i = 0; i < 1000; i++) + riscv_clarke_q31(Ia1, Ib1, &pIalpha, &pIbeta); + BENCH_END(riscv_clarke_q31); + pIalpha_ref = 1073741824; + pIbeta_ref = 1859774949; + if ((labs(pIalpha - pIalpha_ref) > DELTAQ31) || + (labs(pIbeta - pIbeta_ref) > DELTAQ31)) { + BENCH_ERROR(riscv_clarke_q31); + printf("pIalpha expect: %x, actual: %x\npIbeta expect: %x, actual: %x", + pIalpha_ref, pIalpha, pIbeta_ref, pIbeta); + test_flag_error = 1; + } + BENCH_STATUS(riscv_clarke_q31); +} + +static int DSP_inv_clarke_f32_app() +{ + float32_t Ia, Ia_ref; + float32_t Ib, Ib_ref; + + float32_t pIalpha = 0.500000; + float32_t pIbeta = 0.866025; + BENCH_START(riscv_inv_clarke_f32); + for (int i = 0; i < 1000; i++) + riscv_inv_clarke_f32(pIalpha, pIbeta, &Ia, &Ib); + BENCH_END(riscv_inv_clarke_f32); + Ia_ref = 0.500000; + Ib_ref = 0.500000; + if ((fabs(Ia - Ia_ref) > DELTAF32) || (fabs(Ib - Ib_ref) > DELTAF32)) { + BENCH_ERROR(riscv_inv_clarke_f32); + printf("Ia expect: %f, actual: %f\nIb expect: %f, actual: %f", Ia_ref, + Ia, Ib_ref, Ib); + test_flag_error = 1; + } + BENCH_STATUS(riscv_inv_clarke_f32); +} + +static int DSP_inv_clarke_q31_app() +{ + q31_t Ia, Ia_ref; + q31_t Ib, Ib_ref; + + float32_t pIalpha = 0.500000; + float32_t pIbeta = 0.866025; + + q31_t pIalpha1; + q31_t pIbeta1; + + riscv_float_to_q31(&pIalpha, &pIalpha1, 1); + riscv_float_to_q31(&pIalpha, &pIbeta1, 1); + + BENCH_START(riscv_inv_clarke_q31); + for (int i = 0; i < 1000; i++) + riscv_inv_clarke_q31(pIalpha1, pIbeta1, &Ia, &Ib); + BENCH_END(riscv_inv_clarke_q31); + Ia_ref = 1073741824; + Ib_ref = 393016784; + if ((labs(Ia - Ia_ref) > DELTAQ31) || (labs(Ib - Ib_ref) > DELTAQ31)) { + BENCH_ERROR(riscv_inv_clarke_q31); + printf("Ia expect: %x, actual: %x\nIb expect: %x, actual: %x", Ia_ref, + Ia, Ib_ref, Ib); + test_flag_error = 1; + } + BENCH_STATUS(riscv_inv_clarke_q31); +} + +static int DSP_park_f32_app() +{ + float32_t Ia = sin(30 * PI / 180); + float32_t Ib = sin(120 * PI / 180); + + float32_t pIalpha; + float32_t Ibeta; + + float32_t pId, pId_ref; + float32_t pIq, pIq_ref; + + float32_t sinVal = sin(30 * PI / 180); + float32_t cosVal = cos(30 * PI / 180); + + BENCH_START(riscv_park_f32); + for (int i = 0; i < 1000; i++) + riscv_park_f32(Ia, Ib, &pId, &pIq, sinVal, cosVal); + BENCH_END(riscv_park_f32); + pId_ref = 0.866025; + pIq_ref = 0.500000; + if ((fabs(pId - pId_ref) > DELTAF32) || (fabs(pIq - pIq_ref) > DELTAF32)) { + BENCH_ERROR(riscv_park_f32); + printf("pId expect: %f, actual: %f\npIq expect: %f, actual: %f", + pId_ref, pId, pIq_ref, pIq); + test_flag_error = 1; + } + BENCH_STATUS(riscv_park_f32); +} + +static int DSP_park_q31_app() +{ + + const float32_t Ia = sin(30 * PI / 180); + const float32_t Ib = sin(150 * PI / 180); + + q31_t Ia1; + q31_t Ib1; + + riscv_float_to_q31(&Ia, &Ia1, 1); + riscv_float_to_q31(&Ib, &Ib1, 1); + + q31_t pIalpha; + q31_t pIbeta; + + q31_t pId, pId_ref; + q31_t pIq, pIq_ref; + + float32_t sinVal = sin(30 * PI / 180); + float32_t cosVal = cos(30 * PI / 180); + + q31_t sinVal1; + q31_t cosVal1; + + riscv_float_to_q31(&sinVal, &sinVal1, 1); + riscv_float_to_q31(&cosVal, &cosVal1, 1); + + BENCH_START(riscv_park_q31); + for (int i = 0; i < 1000; i++) + riscv_park_q31(Ia1, Ib1, &pId, &pIq, sinVal1, cosVal1); + BENCH_END(riscv_park_q31); + pId_ref = 1466758400; + pIq_ref = 393016435; + if ((labs(pId - pId_ref) > DELTAQ31) || (labs(pIq - pIq_ref) > DELTAQ31)) { + BENCH_ERROR(riscv_park_q31); + printf("pId expect: %x, actual: %x\npIq expect: %x, actual: %x", + pId_ref, pId, pIq_ref, pIq); + test_flag_error = 1; + } + BENCH_STATUS(riscv_park_q31); +} + +static int DSP_inv_park_f32_app() +{ + float32_t Ia = 0.866025; + float32_t Ib = 0.500000; + + float32_t pIalpha, pIalpha_ref; + float32_t pIbeta, pIbeta_ref; + + float32_t sinVal = sin(30 * PI / 180); + float32_t cosVal = cos(30 * PI / 180); + + BENCH_START(riscv_inv_park_f32); + for (int i = 0; i < 1000; i++) + riscv_inv_park_f32(Ia, Ib, &pIalpha, &pIbeta, sinVal, cosVal); + BENCH_END(riscv_inv_park_f32); + pIalpha_ref = 0.500000; + pIbeta_ref = 0.866025; + if ((fabs(pIalpha - pIalpha_ref) > DELTAF32) || + (fabs(pIbeta - pIbeta_ref) > DELTAF32)) { + BENCH_ERROR(riscv_inv_park_f32); + printf("pIalpha expect: %f, actual: %f\npIbeta expect: %f, actual: %f", + pIalpha_ref, pIalpha, pIbeta_ref, pIbeta); + test_flag_error = 1; + } + BENCH_STATUS(riscv_inv_park_f32); +} + +static int DSP_inv_park_q31_app() +{ + q31_t Ia1 = 1859774464; + q31_t Ib1 = 1073741824; + + q31_t pIalpha, pIalpha_ref; + q31_t pIbeta, pIbeta_ref; + + q31_t sinValb = 1073741824; + q31_t cosValb = 1859775360; + + BENCH_START(riscv_inv_park_q31); + for (int i = 0; i < 1000; i++) + riscv_inv_park_q31(Ia1, Ib1, &pIalpha, &pIbeta, sinValb, cosValb); + BENCH_END(riscv_inv_park_q31); + pIalpha_ref = 1073740990; + pIbeta_ref = 1859774912; + if ((labs(pIalpha - pIalpha_ref) > DELTAQ31) || + (labs(pIbeta - pIbeta_ref) > DELTAQ31)) { + BENCH_ERROR(riscv_inv_park_q31); + printf( + "pIalpha expect: %x, actual: %x\npIbeta expect: %x, actual: %x\n", + pIalpha_ref, pIalpha, pIbeta_ref, pIbeta); + test_flag_error = 1; + } + BENCH_STATUS(riscv_inv_park_q31); +} + +static int DSP_pid_f32_app() +{ + uint32_t i; + riscv_pid_instance_f32 PIDS; + PIDS.Kp = 0.4; + PIDS.Ki = 0.4; + PIDS.Kd = 0; + float32_t target, ival, ee = 0, ee_ref = 0; + output[0] = 0; + output_ref[0] = 0; + /* Target value*/ + target = 500; + /* Inital value */ + ival = 0; + /* Initial value and target value error */ + ee = target - ival; + ee_ref = target - ival; + /* Initial DSP PID controller function*/ + riscv_pid_init_f32(&PIDS, 1); + BENCH_START(riscv_pid_f32); + for (i = 1; i < 100; i++) { + output[i] = riscv_pid_f32(&PIDS, ee); + ee = target - output[i - 1]; + } + BENCH_END(riscv_pid_f32); + for (i = 1; i < 100; i++) { + output_ref[i] = ref_pid_f32(&PIDS, ee_ref); + ee_ref = target - output_ref[i - 1]; + } + if (fabs(output[99] - output_ref[99]) > DELTAF32) { + BENCH_ERROR(riscv_pid_f32); + printf("index: %d, expect: %f, actual: %f\n", i, output_ref[99], + output[99]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_pid_f32); +} + +static int DSP_pid_q15_app() +{ + uint32_t i; + riscv_pid_instance_f32 PIDS; + riscv_pid_instance_q15 PIDS_q15; + PIDS.Kp = 0.4; + PIDS.Ki = 0.4; + PIDS.Kd = 0; + riscv_float_to_q15(&PIDS.Kp, &PIDS_q15.Kp, 1); + riscv_float_to_q15(&PIDS.Ki, &PIDS_q15.Ki, 1); + riscv_float_to_q15(&PIDS.Kd, &PIDS_q15.Kd, 1); + q15_t ee_q15 = 0, ee_q15_ref = 0,target, ival; + output_q15[0] = 0; + output_q15_ref[0] = 0; + /* Target value*/ + target = 500; + /* Inital value */ + ival = 0; + /* Initial value and target value error */ + ee_q15 = target - ival; + ee_q15_ref = target - ival; + /* Initial DSP PID controller function*/ + riscv_pid_init_q15(&PIDS_q15, 0); + BENCH_START(riscv_pid_q15); + for (i = 1; i < 100; i++) { + output_q15[i] = riscv_pid_q15(&PIDS_q15, ee_q15); + ee_q15 = target - output_q15[i - 1]; + } + BENCH_END(riscv_pid_q15); + riscv_pid_init_q15(&PIDS_q15, 0); + for (i = 1; i < 100; i++) { + output_q15_ref[i] = ref_pid_q15(&PIDS_q15, ee_q15_ref); + ee_q15_ref = target - output_q15_ref[i - 1]; + } + if (abs(output_q15[99] - output_q15_ref[99]) > DELTAQ15) { + BENCH_ERROR(riscv_pid_q15); + printf("index: %d, expect: %x, actual: %x\n", 99, output_q15_ref[99], + output_q15[99]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_pid_q15); +} + +static int DSP_pid_q31_app() +{ + uint32_t i; + riscv_pid_instance_f32 PIDS; + riscv_pid_instance_q31 PIDS_q31; + PIDS.Kp = 0.4; + PIDS.Ki = 0.4; + PIDS.Kd = 0; + riscv_float_to_q31(&PIDS.Kp, &PIDS_q31.Kp, 1); + riscv_float_to_q31(&PIDS.Ki, &PIDS_q31.Ki, 1); + riscv_float_to_q31(&PIDS.Kd, &PIDS_q31.Kd, 1); + q31_t ee_q31 = 0, ee_q31_ref = 0,target, ival; + output_q31[0] = 0; + output_q31_ref[0] = 0; + /* Target value*/ + target = 500; + /* Inital value */ + ival = 0; + /* Initial value and target value error */ + ee_q31 = target - ival; + /* Initial DSP PID controller function*/ + riscv_pid_init_q31(&PIDS_q31, 1); + BENCH_START(riscv_pid_q31); + for (i = 1; i < 100; i++) { + output_q31[i] = riscv_pid_q31(&PIDS_q31, ee_q31); + ee_q31 = target - output_q31[i - 1]; + } + BENCH_END(riscv_pid_q31); + for (i = 1; i < 100; i++) { + output_q31_ref[i] = ref_pid_q31(&PIDS_q31, ee_q31_ref); + ee_q31_ref = target - output_q31_ref[i - 1]; + } + if (labs(output_q31[99] - output_q31_ref[99]) > DELTAQ31) { + BENCH_ERROR(riscv_pid_q31); + printf("index: %d, expect: %x, actual: %x\n", i, output_q31_ref[i], + output_q31[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_pid_q31); +} +int main() +{ + BENCH_INIT; +#if defined CLARKE || defined ENABLE_ALL + DSP_clarke_f32_app(); + DSP_clarke_q31_app(); +#endif +#if defined INV_CLARKE || defined ENABLE_ALL + DSP_inv_clarke_f32_app(); + DSP_inv_clarke_q31_app(); +#endif +#if defined PARK || defined ENABLE_ALL + DSP_park_f32_app(); + DSP_park_q31_app(); +#endif +#if defined INV_PARK || defined ENABLE_ALL + DSP_inv_park_f32_app(); + DSP_inv_park_q31_app(); +#endif +#if defined PID || defined ENABLE_ALL + DSP_pid_f32_app(); + DSP_pid_q15_app(); + DSP_pid_q31_app(); +#endif + BENCH_FINISH; + if (test_flag_error) { + printf("test error apprears, please recheck.\n"); + return 1; + } else { + printf("all test are passed. Well done!\n"); + } + return 0; +} \ No newline at end of file diff --git a/examples/dsp/ControllerFunctions_pidpart/pid.c b/examples/dsp/ControllerFunctions_pidpart/pid.c new file mode 100644 index 00000000..a2b54e18 --- /dev/null +++ b/examples/dsp/ControllerFunctions_pidpart/pid.c @@ -0,0 +1,91 @@ +#include "ref.h" + +float32_t ref_pid_f32(riscv_pid_instance_f32 *S, float32_t in) +{ + float32_t out; + + /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ + out = S->state[2] + S->A0 * in + S->A1 * S->state[0] + S->A2 * S->state[1]; + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); +} + +q31_t ref_pid_q31(riscv_pid_instance_q31 *S, q31_t in) +{ + q63_t acc; + q31_t out; + + /* acc = A0 * x[n] */ + acc = (q63_t)S->A0 * in; + + /* acc += A1 * x[n-1] */ + acc += (q63_t)S->A1 * S->state[0]; + + /* acc += A2 * x[n-2] */ + acc += (q63_t)S->A2 * S->state[1]; + + /* convert output to 1.31 format to add y[n-1] */ + out = (q31_t)(acc >> 31U); + + /* out += y[n-1] */ + out += S->state[2]; + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); +} + +q15_t ref_pid_q15(riscv_pid_instance_q15 *S, q15_t in) +{ + q63_t acc; + q15_t out; + q15_t A1, A2; + +#if defined(riscv_MATH_DSP) + +#ifndef riscv_MATH_BIG_ENDIAN + A2 = S->A1 >> 16; + A1 = (q15_t)S->A1; +#else + A1 = S->A1 >> 16; + A2 = (q15_t)S->A1; +#endif + +#else + + A1 = S->A1; + A2 = S->Kd; + +#endif + + /* acc = A0 * x[n] */ + acc = ((q31_t)S->A0) * in; + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc += (q31_t)A1 * S->state[0]; + acc += (q31_t)A2 * S->state[1]; + + /* acc += y[n-1] */ + acc += (q31_t)S->state[2] << 15; + + /* saturate the output */ + out = ref_sat_q15(acc >> 15); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); +} diff --git a/examples/dsp/ControllerFunctions_sincospart/CMakeLists.txt b/examples/dsp/ControllerFunctions_sincospart/CMakeLists.txt new file mode 100644 index 00000000..4ae2a990 --- /dev/null +++ b/examples/dsp/ControllerFunctions_sincospart/CMakeLists.txt @@ -0,0 +1,5 @@ +set(TARGET_REQUIRED_PRIVATE_INCLUDE ${CMAKE_CURRENT_SOURCE_DIR} ${CMAKE_CURRENT_SOURCE_DIR}/..) +set(TARGET_REQUIRED_SRCS sin_cos.c) +set(TARGET_REQUIRED_LIBS nmsis) +set(mains main.c) +generate_bin() \ No newline at end of file diff --git a/examples/dsp/ControllerFunctions_sincospart/main.c b/examples/dsp/ControllerFunctions_sincospart/main.c new file mode 100644 index 00000000..d3323d63 --- /dev/null +++ b/examples/dsp/ControllerFunctions_sincospart/main.c @@ -0,0 +1,76 @@ +// This contains SIN_COS , clarke, inv_clarke, park, inv_park and pid +// each one has it's own function. +// All function can be found in main function. +// If you don't want to use it, then comment it. +#include "riscv_math.h" +#include +#include +#include "../common.h" + +#include "../HelperFunctions/math_helper.c" +#include "../HelperFunctions/ref_helper.c" + +#include +#define DELTAF32 (0.05f) +#define DELTAQ31 (63) +#define DELTAQ15 (1) +#define DELTAQ7 (1) + +int test_flag_error = 0; + +static int DSP_SIN_COS_F32(void) +{ + int16_t i; + float32_t pSinVal, pSinVal_ref; + float32_t pCosVal, pCosVal_ref; + + BENCH_START(riscv_sin_cos_f32); + for (int i = 0; i < 1000; i++) + riscv_sin_cos_f32(0, &pSinVal, &pCosVal); + BENCH_END(riscv_sin_cos_f32); + ref_sin_cos_f32(0, &pSinVal_ref, &pCosVal_ref); + if ((fabs(pSinVal - pSinVal_ref) > DELTAF32) || + (fabs(pCosVal - pCosVal_ref) > DELTAF32)) { + BENCH_ERROR(riscv_sin_cos_f32); + printf("sin expect: %f, actual: %f\ncos expect: %f, actual: %f", + pSinVal_ref, pSinVal, pCosVal_ref, pCosVal); + test_flag_error = 1; + } + BENCH_STATUS(riscv_sin_cos_f32); +} + +static int DSP_SIN_COS_Q31(void) +{ + int16_t i; + q31_t pSinVal, pSinVal_ref; + q31_t pCosVal, pCosVal_ref; + + BENCH_START(riscv_sin_cos_q31); + for (int i = 0; i < 1000; i++) + riscv_sin_cos_q31(0, &pSinVal, &pCosVal); + BENCH_END(riscv_sin_cos_q31); + ref_sin_cos_q31(0, &pSinVal_ref, &pCosVal_ref); + if ((labs(pSinVal - pSinVal_ref) > DELTAQ31) || + (labs(pCosVal - pCosVal_ref) > DELTAQ31)) { + BENCH_ERROR(riscv_sin_cos_q31); + printf("sin expect: %x, actual: %x\ncos expect: %x, actual: %x", + pSinVal_ref, pSinVal, pCosVal_ref, pCosVal); + test_flag_error = 1; + } + BENCH_STATUS(riscv_sin_cos_q31); +} + +int main() +{ + BENCH_INIT; + DSP_SIN_COS_F32(); + DSP_SIN_COS_Q31(); + BENCH_FINISH; + if (test_flag_error) { + printf("test error apprears, please recheck.\n"); + return 1; + } else { + printf("all test are passed. Well done!\n"); + } + return 0; +} \ No newline at end of file diff --git a/examples/dsp/ControllerFunctions_sincospart/sin_cos.c b/examples/dsp/ControllerFunctions_sincospart/sin_cos.c new file mode 100644 index 00000000..5f029402 --- /dev/null +++ b/examples/dsp/ControllerFunctions_sincospart/sin_cos.c @@ -0,0 +1,19 @@ +#include "ref.h" + +void ref_sin_cos_f32(float32_t theta, float32_t *pSinVal, float32_t *pCosVal) +{ + // theta is given in degrees + *pSinVal = sinf(theta * 6.28318530717959f / 360.0f); + *pCosVal = cosf(theta * 6.28318530717959f / 360.0f); +} + +void ref_sin_cos_q31(q31_t theta, q31_t *pSinVal, q31_t *pCosVal) +{ + // theta is given in the range [-1,1) to represent [-pi,pi) + *pSinVal = + (q31_t)(sinf((float32_t)theta * 3.14159265358979f / 2147483648.0f) * + 2147483648.0f); + *pCosVal = + (q31_t)(cosf((float32_t)theta * 3.14159265358979f / 2147483648.0f) * + 2147483648.0f); +} diff --git a/examples/dsp/ConvolutionFunctions_convPart/CMakeLists.txt b/examples/dsp/ConvolutionFunctions_convPart/CMakeLists.txt new file mode 100644 index 00000000..3e9f0c8e --- /dev/null +++ b/examples/dsp/ConvolutionFunctions_convPart/CMakeLists.txt @@ -0,0 +1,5 @@ +set(TARGET_REQUIRED_PRIVATE_INCLUDE ${CMAKE_CURRENT_SOURCE_DIR} ${CMAKE_CURRENT_SOURCE_DIR}/..) +set(TARGET_REQUIRED_SRCS conv.c) +set(TARGET_REQUIRED_LIBS nmsis) +set(mains main.c) +generate_bin() \ No newline at end of file diff --git a/examples/dsp/ConvolutionFunctions_convPart/array.h b/examples/dsp/ConvolutionFunctions_convPart/array.h new file mode 100644 index 00000000..043ed55d --- /dev/null +++ b/examples/dsp/ConvolutionFunctions_convPart/array.h @@ -0,0 +1,25 @@ +// Array for ConvolutionFunctions convPart +#define max(a,b)(a>b?a:b) +#define min(a,b)(a> 31U); + } +} + +void ref_conv_fast_q31(q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, + uint32_t srcBLen, q31_t *pDst) +{ + q31_t sum; /* Accumulator */ + uint32_t i, j; /* loop counter */ + + /* Loop to calculate output of convolution for output length number of times + */ + for (i = 0; i < srcALen + srcBLen - 1; i++) { + /* Initialize sum with zero to carry on MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0; j <= i; j++) { + /* Check the array limitations */ + if ((i - j < srcBLen) && (j < srcALen)) { + /* z[i] += x[i-j] * y[j] */ + sum = (q31_t)( + (((q63_t)sum << 32) + ((q63_t)pSrcA[j] * pSrcB[i - j])) >> + 32); + } + } + + /* Store the output in the destination buffer */ + pDst[i] = (q31_t)(sum << 1U); + } +} + +riscv_status ref_conv_partial_q31(q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, + uint32_t srcBLen, q31_t *pDst, + uint32_t firstIndex, uint32_t numPoints) +{ + ref_conv_q31(pSrcA, srcALen, pSrcB, srcBLen, pDst); + + return RISCV_MATH_SUCCESS; +} + +riscv_status ref_conv_partial_fast_q31(q31_t *pSrcA, uint32_t srcALen, + q31_t *pSrcB, uint32_t srcBLen, + q31_t *pDst, uint32_t firstIndex, + uint32_t numPoints) +{ + ref_conv_fast_q31(pSrcA, srcALen, pSrcB, srcBLen, pDst); + + return RISCV_MATH_SUCCESS; +} + +void ref_conv_q15(q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, + uint32_t srcBLen, q15_t *pDst) +{ + q63_t sum; /* Accumulator */ + uint32_t i, j; /* loop counter */ + + /* Loop to calculate output of convolution for output length number of times + */ + for (i = 0; i < srcALen + srcBLen - 1; i++) { + /* Initialize sum with zero to carry on MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0; j <= i; j++) { + /* Check the array limitations */ + if ((i - j < srcBLen) && (j < srcALen)) { + /* z[i] += x[i-j] * y[j] */ + sum += (q31_t)pSrcA[j] * pSrcB[i - j]; + } + } + + /* Store the output in the destination buffer */ + pDst[i] = ref_sat_q15(sum >> 15U); + } +} + +riscv_status ref_conv_partial_fast_opt_q15(q15_t *pSrcA, uint32_t srcALen, + q15_t *pSrcB, uint32_t srcBLen, + q15_t *pDst, uint32_t firstIndex, + uint32_t numPoints, q15_t *pScratch1, + q15_t *pScratch2) +{ + q31_t sum; /* Accumulator */ + uint32_t i, j; /* loop counter */ + + /* Loop to calculate output of convolution for output length number of times + */ + for (i = 0; i < srcALen + srcBLen - 1; i++) { + /* Initialize sum with zero to carry on MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0; j <= i; j++) { + /* Check the array limitations */ + if ((i - j < srcBLen) && (j < srcALen)) { + /* z[i] += x[i-j] * y[j] */ + sum += (q31_t)pSrcA[j] * pSrcB[i - j]; + } + } + + /* Store the output in the destination buffer */ + pDst[i] = ref_sat_q15(sum >> 15U); + } + + return RISCV_MATH_SUCCESS; +} + +void ref_conv_fast_q15(q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, + uint32_t srcBLen, q15_t *pDst) +{ + q31_t sum; /* Accumulator */ + uint32_t i, j; /* loop counter */ + + /* Loop to calculate output of convolution for output length number of times + */ + for (i = 0; i < srcALen + srcBLen - 1; i++) { + /* Initialize sum with zero to carry on MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0; j <= i; j++) { + /* Check the array limitations */ + if ((i - j < srcBLen) && (j < srcALen)) { + /* z[i] += x[i-j] * y[j] */ + sum += (q31_t)pSrcA[j] * pSrcB[i - j]; + } + } + + /* Store the output in the destination buffer */ + pDst[i] = sum >> 15U; + } +} + +void ref_conv_fast_opt_q15(q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, + uint32_t srcBLen, q15_t *pDst, q15_t *pScratch1, + q15_t *pScratch2) +{ + q31_t sum; /* Accumulator */ + uint32_t i, j; /* loop counter */ + + /* Loop to calculate output of convolution for output length number of times + */ + for (i = 0; i < srcALen + srcBLen - 1; i++) { + /* Initialize sum with zero to carry on MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0; j <= i; j++) { + /* Check the array limitations */ + if ((i - j < srcBLen) && (j < srcALen)) { + /* z[i] += x[i-j] * y[j] */ + sum += (q31_t)pSrcA[j] * pSrcB[i - j]; + } + } + + /* Store the output in the destination buffer */ + pDst[i] = ref_sat_q15(sum >> 15U); + } +} + +riscv_status ref_conv_partial_q15(q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, + uint32_t srcBLen, q15_t *pDst, + uint32_t firstIndex, uint32_t numPoints) +{ + ref_conv_q15(pSrcA, srcALen, pSrcB, srcBLen, pDst); + + return RISCV_MATH_SUCCESS; +} + +riscv_status ref_conv_partial_fast_q15(q15_t *pSrcA, uint32_t srcALen, + q15_t *pSrcB, uint32_t srcBLen, + q15_t *pDst, uint32_t firstIndex, + uint32_t numPoints) +{ + ref_conv_fast_q15(pSrcA, srcALen, pSrcB, srcBLen, pDst); + + return RISCV_MATH_SUCCESS; +} + +void ref_conv_q7(q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, uint32_t srcBLen, + q7_t *pDst) +{ + q31_t sum; /* Accumulator */ + uint32_t i, j; /* loop counter */ + + /* Loop to calculate output of convolution for output length number of times + */ + for (i = 0; i < srcALen + srcBLen - 1; i++) { + /* Initialize sum with zero to carry on MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0; j <= i; j++) { + /* Check the array limitations */ + if ((i - j < srcBLen) && (j < srcALen)) { + /* z[i] += x[i-j] * y[j] */ + sum += (q15_t)pSrcA[j] * pSrcB[i - j]; + } + } + + /* Store the output in the destination buffer */ + pDst[i] = (q7_t)ref_sat_q7(sum >> 7); + } +} + +riscv_status ref_conv_partial_q7(q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, + uint32_t srcBLen, q7_t *pDst, + uint32_t firstIndex, uint32_t numPoints) +{ + ref_conv_q7(pSrcA, srcALen, pSrcB, srcBLen, pDst); + + return RISCV_MATH_SUCCESS; +} diff --git a/examples/dsp/ConvolutionFunctions_convPart/main.c b/examples/dsp/ConvolutionFunctions_convPart/main.c new file mode 100644 index 00000000..307c2b5e --- /dev/null +++ b/examples/dsp/ConvolutionFunctions_convPart/main.c @@ -0,0 +1,171 @@ +// +// Created by lujun on 19-6-28. +// + +#include "riscv_math.h" +#include +#include +#include "array.h" +#include "../common.h" + +#include "../HelperFunctions/math_helper.c" +#include "../HelperFunctions/ref_helper.c" + +#include +#define DELTAF32 (0.05f) +#define DELTAQ31 (63) +#define DELTAQ15 (2) +#define DELTAQ7 (2) +#define RISCV_MATH_LOOPUNROLL + +int test_flag_error = 0; +int main() +{ + uint16_t i; + BENCH_INIT; + + // ***************************************************** + // conv part + // ***************************************************** + BENCH_START(riscv_conv_f32); + riscv_conv_f32(test_conv_input_f32_A, ARRAYA_SIZE_F32, test_conv_input_f32_B, ARRAYB_SIZE_F32, + output_f32); + BENCH_END(riscv_conv_f32); + ref_conv_f32(test_conv_input_f32_A, ARRAYA_SIZE_F32, test_conv_input_f32_B, ARRAYB_SIZE_F32, + output_f32_ref); + for (int i = 0; i < (ARRAYA_SIZE_F32 + ARRAYB_SIZE_F32 - 1); i++) + if (fabs(output_f32_ref[i] - output_f32[i]) > DELTAF32) { + BENCH_ERROR(riscv_conv_f32); + printf("index:%d, expect: %f, actual: %f\n", i, output_f32_ref[i], + output_f32[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_conv_f32); + + BENCH_START(riscv_conv_q31); + riscv_conv_q31(test_conv_input_q31_A, ARRAYA_SIZE_Q31, test_conv_input_q31_B, ARRAYB_SIZE_Q31, + output_q31); + BENCH_END(riscv_conv_q31); + ref_conv_q31(test_conv_input_q31_A, ARRAYA_SIZE_Q31, test_conv_input_q31_B, ARRAYB_SIZE_Q31, + output_q31_ref); + for (int i = 0; i < (ARRAYA_SIZE_Q31 + ARRAYB_SIZE_Q31 - 1); i++) + if (labs(output_q31_ref[i] - output_q31[i]) > DELTAQ31) { + BENCH_ERROR(riscv_conv_q31); + printf("index:%d, expect: %d, actual: %d\n", i, output_q31_ref[i], + output_q31[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_conv_q31); + + BENCH_START(riscv_conv_q15); + riscv_conv_q15(test_conv_input_q15_A, ARRAYA_SIZE_Q15, test_conv_input_q15_B, ARRAYB_SIZE_Q15, + output_q15); + BENCH_END(riscv_conv_q15); + ref_conv_q15(test_conv_input_q15_A, ARRAYA_SIZE_Q15, test_conv_input_q15_B, ARRAYB_SIZE_Q15, + output_q15_ref); + for (int i = 0; i < (ARRAYA_SIZE_Q15 + ARRAYB_SIZE_Q15 - 1); i++) + if (abs(output_q15_ref[i] - output_q15[i]) > DELTAQ15) { + BENCH_ERROR(riscv_conv_q15); + printf("index:%d, expect: %d, actual: %d\n", i, output_q15_ref[i], + output_q15[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_conv_q15); + + BENCH_START(riscv_conv_q7); + riscv_conv_q7(test_conv_input_q7_A, ARRAYA_SIZE_Q7, test_conv_input_q7_B, ARRAYB_SIZE_Q7, output_q7); + BENCH_END(riscv_conv_q7); + ref_conv_q7(test_conv_input_q7_A, ARRAYA_SIZE_Q7, test_conv_input_q7_B, ARRAYB_SIZE_Q7, + output_q7_ref); + for (int i = 0; i < (ARRAYA_SIZE_Q7 + ARRAYB_SIZE_Q7 - 1); i++) + if (abs(output_q7_ref[i] - output_q7[i]) > DELTAQ7) { + BENCH_ERROR(riscv_conv_q7); + printf("index:%d, expect: %d, actual: %d\n", i, output_q7_ref[i], + output_q7[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_conv_q7); + + BENCH_START(riscv_conv_fast_q15); + riscv_conv_fast_q15(test_conv_input_q15_A, ARRAYA_SIZE_Q15, test_conv_input_q15_B, ARRAYB_SIZE_Q15, + output_q15); + BENCH_END(riscv_conv_fast_q15); + ref_conv_fast_q15(test_conv_input_q15_A, ARRAYA_SIZE_Q15, test_conv_input_q15_B, ARRAYB_SIZE_Q15, + output_q15_ref); + for (int i = 0; i < (ARRAYA_SIZE_Q15 + ARRAYB_SIZE_Q15 - 1); i++) + if (abs(output_q15_ref[i] - output_q15[i]) > DELTAQ15) { + BENCH_ERROR(riscv_conv_fast_q15); + printf("index:%d, expect: %d, actual: %d\n", i, output_q15_ref[i], + output_q15[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_conv_fast_q15); + + BENCH_START(riscv_conv_fast_q31); + riscv_conv_fast_q31(test_conv_input_q31_A, ARRAYA_SIZE_Q31, test_conv_input_q31_B, ARRAYB_SIZE_Q31, + output_q31); + BENCH_END(riscv_conv_fast_q31); + ref_conv_fast_q31(test_conv_input_q31_A, ARRAYA_SIZE_Q31, test_conv_input_q31_B, ARRAYB_SIZE_Q31, + output_q31_ref); + for (int i = 0; i < (ARRAYA_SIZE_Q31 + ARRAYB_SIZE_Q31 - 1); i++) + if (labs(output_q31_ref[i] - output_q31[i]) > DELTAQ31) { + BENCH_ERROR(riscv_conv_fast_q31); + printf("index:%d, expect: %d, actual: %d\n", i, output_q31_ref[i], + output_q31[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_conv_fast_q31); + + BENCH_START(riscv_conv_opt_q15); + riscv_conv_opt_q15(test_conv_input_q15_A, ARRAYA_SIZE_Q15, test_conv_input_q15_B, ARRAYB_SIZE_Q15, + output_q15, pScratch1, pScratch2); + BENCH_END(riscv_conv_opt_q15); + ref_conv_opt_q15(test_conv_input_q15_A, ARRAYA_SIZE_Q15, test_conv_input_q15_B, ARRAYB_SIZE_Q15, + output_q15_ref, pScratch1, pScratch2); + for (int i = 0; i < (ARRAYA_SIZE_Q15 + ARRAYB_SIZE_Q15 - 1); i++) + if (abs(output_q15_ref[i] - output_q15[i]) > DELTAQ15) { + BENCH_ERROR(riscv_conv_opt_q15); + printf("index:%d, expect: %d, actual: %d\n", i, output_q15_ref[i], + output_q15[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_conv_opt_q15); + + BENCH_START(riscv_conv_opt_q7); + riscv_conv_opt_q7(test_conv_input_q7_A, ARRAYA_SIZE_Q7, test_conv_input_q7_B, ARRAYB_SIZE_Q7, + output_q7, pScratch1, pScratch2); + BENCH_END(riscv_conv_opt_q7); + ref_conv_opt_q7(test_conv_input_q7_A, ARRAYA_SIZE_Q7, test_conv_input_q7_B, ARRAYB_SIZE_Q7, + output_q7_ref, pScratch1, pScratch2); + for (int i = 0; i < (ARRAYA_SIZE_Q7 + ARRAYB_SIZE_Q7 - 1); i++) + if (abs(output_q7_ref[i] - output_q7[i]) > DELTAQ7) { + BENCH_ERROR(riscv_conv_opt_q7); + printf("index:%d, expect: %d, actual: %d\n", i, output_q7_ref[i], + output_q7[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_conv_opt_q7); + + BENCH_START(riscv_conv_fast_opt_q15); + riscv_conv_fast_opt_q15(test_conv_input_q15_A, ARRAYA_SIZE_Q15, test_conv_input_q15_B, ARRAYB_SIZE_Q15, + output_q15, pScratch1, pScratch2); + BENCH_END(riscv_conv_fast_opt_q15); + ref_conv_fast_opt_q15(test_conv_input_q15_A, ARRAYA_SIZE_Q15, test_conv_input_q15_B, ARRAYB_SIZE_Q15, + output_q15_ref, pScratch1, pScratch2); + for (int i = 0; i < (ARRAYA_SIZE_Q7 + ARRAYB_SIZE_Q7 - 1); i++) + if (abs(output_q15_ref[i] - output_q15[i]) > DELTAQ15) { + BENCH_ERROR(riscv_conv_fast_opt_q15); + printf("index:%d, expect: %d, actual: %d\n", i, output_q15_ref[i], + output_q15[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_conv_fast_opt_q15); + BENCH_FINISH; + if (test_flag_error) { + printf("test error apprears, please recheck.\n"); + return 1; + } else { + printf("all test are passed. Well done!\n"); + } + return 0; +} diff --git a/examples/dsp/ConvolutionFunctions_correlatePart/CMakeLists.txt b/examples/dsp/ConvolutionFunctions_correlatePart/CMakeLists.txt new file mode 100644 index 00000000..dee48a94 --- /dev/null +++ b/examples/dsp/ConvolutionFunctions_correlatePart/CMakeLists.txt @@ -0,0 +1,5 @@ +set(TARGET_REQUIRED_PRIVATE_INCLUDE ${CMAKE_CURRENT_SOURCE_DIR} ${CMAKE_CURRENT_SOURCE_DIR}/..) +set(TARGET_REQUIRED_SRCS correlate.c) +set(TARGET_REQUIRED_LIBS nmsis) +set(mains main.c) +generate_bin() \ No newline at end of file diff --git a/examples/dsp/ConvolutionFunctions_correlatePart/array.h b/examples/dsp/ConvolutionFunctions_correlatePart/array.h new file mode 100644 index 00000000..d48a9343 --- /dev/null +++ b/examples/dsp/ConvolutionFunctions_correlatePart/array.h @@ -0,0 +1,24 @@ +// Array for ConvolutionFunctions correlatePart +#define max(a,b) (a>b?a:b) +#define min(a,b) (a srcALen, output pointer is made to point to the end of + * the output buffer and a variable, inv is set to 1 If lengths are not + * equal then zero pad has to be done to make the two inputs of same length. + * But to improve the performance, we include zeroes in the output instead + * of zero padding either of the the inputs If srcALen > srcBLen, (srcALen - + * srcBLen) zeroes has to included in the starting of the output buffer If + * srcALen < srcBLen, (srcALen - srcBLen) zeroes has to included in the + * ending of the output buffer + * Once the zero padding is done the remaining of the output is calcualted + * using convolution but with the shorter signal time shifted. + */ + + /* Calculate the length of the remaining sequence */ + tot = srcALen + srcBLen - 2U; + + if (srcALen > srcBLen) { + /* Calculating the number of zeros to be padded to the output */ + /* Initialise the pointer after zero padding */ + pDst += srcALen - srcBLen; + } else if (srcALen < srcBLen) { + /* Initialization to inputB pointer */ + pIn1 = pSrcB; + + /* Initialization to the end of inputA pointer */ + pIn2 = pSrcA + srcALen - 1U; + + /* Initialisation of the pointer after zero padding */ + pDst += tot; + + /* Swapping the lengths */ + j = srcALen; + srcALen = srcBLen; + srcBLen = j; + + /* Setting the reverse flag */ + inv = 1; + } + + /* Loop to calculate convolution for output length number of times */ + for (i = 0U; i <= tot; i++) { + /* Initialize sum with zero to carry on MAC operations */ + sum = 0.0f; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0U; j <= i; j++) { + /* Check the array limitations */ + if ((i - j < srcBLen) && (j < srcALen)) { + /* z[i] += x[i-j] * y[j] */ + sum += pIn1[j] * pIn2[-((int32_t)i - j)]; + } + } + /* Store the output in the destination buffer */ + if (inv == 1) + *pDst-- = sum; + else + *pDst++ = sum; + } +} + +void ref_correlate_q31(q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, + uint32_t srcBLen, q31_t *pDst) +{ + q31_t *pIn1 = pSrcA; /* inputA pointer */ + q31_t *pIn2 = pSrcB + (srcBLen - 1U); /* inputB pointer */ + q63_t sum; /* Accumulators */ + int32_t i = 0U, j; /* loop counters */ + uint32_t inv = 0U; /* Reverse order flag */ + uint32_t tot = 0U; /* Length */ + + /* Calculate the length of the remaining sequence */ + tot = ((srcALen + srcBLen) - 2U); + + if (srcALen > srcBLen) { + /* Calculating the number of zeros to be padded to the output */ + j = srcALen - srcBLen; + + /* Initialise the pointer after zero padding */ + pDst += j; + } + + else if (srcALen < srcBLen) { + /* Initialization to inputB pointer */ + pIn1 = pSrcB; + + /* Initialization to the end of inputA pointer */ + pIn2 = pSrcA + (srcALen - 1U); + + /* Initialisation of the pointer after zero padding */ + pDst = pDst + tot; + + /* Swapping the lengths */ + j = srcALen; + srcALen = srcBLen; + srcBLen = j; + + /* Setting the reverse flag */ + inv = 1; + } + + /* Loop to calculate correlation for output length number of times */ + for (i = 0U; i <= tot; i++) { + /* Initialize sum with zero to carry on MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to correlation equation */ + for (j = 0U; j <= i; j++) { + /* Check the array limitations */ + if ((((i - j) < srcBLen) && (j < srcALen))) { + /* z[i] += x[i-j] * y[j] */ + sum += ((q63_t)pIn1[j] * pIn2[-((int32_t)i - j)]); + } + } + /* Store the output in the destination buffer */ + if (inv == 1) + *pDst-- = (q31_t)(sum >> 31U); + else + *pDst++ = (q31_t)(sum >> 31U); + } +} + +void ref_correlate_fast_q31(q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, + uint32_t srcBLen, q31_t *pDst) +{ + q31_t *pIn1 = pSrcA; /* inputA pointer */ + q31_t *pIn2 = pSrcB + (srcBLen - 1U); /* inputB pointer */ + q63_t sum; /* Accumulators */ + int32_t i = 0U, j; /* loop counters */ + uint32_t inv = 0U; /* Reverse order flag */ + uint32_t tot = 0U; /* Length */ + + /* Calculate the length of the remaining sequence */ + tot = ((srcALen + srcBLen) - 2U); + + if (srcALen > srcBLen) { + /* Calculating the number of zeros to be padded to the output */ + j = srcALen - srcBLen; + + /* Initialise the pointer after zero padding */ + pDst += j; + } + + else if (srcALen < srcBLen) { + /* Initialization to inputB pointer */ + pIn1 = pSrcB; + + /* Initialization to the end of inputA pointer */ + pIn2 = pSrcA + (srcALen - 1U); + + /* Initialisation of the pointer after zero padding */ + pDst = pDst + tot; + + /* Swapping the lengths */ + j = srcALen; + srcALen = srcBLen; + srcBLen = j; + + /* Setting the reverse flag */ + inv = 1; + } + + /* Loop to calculate correlation for output length number of times */ + for (i = 0U; i <= tot; i++) { + /* Initialize sum with zero to carry on MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to correlation equation */ + for (j = 0U; j <= i; j++) { + /* Check the array limitations */ + if ((((i - j) < srcBLen) && (j < srcALen))) { + /* z[i] += x[i-j] * y[j] */ + sum = (q31_t)((((q63_t)sum << 32) + + ((q63_t)pIn1[j] * pIn2[-((int32_t)i - j)])) >> + 32); + } + } + /* Store the output in the destination buffer */ + if (inv == 1) + *pDst-- = (q31_t)(sum << 1U); + else + *pDst++ = (q31_t)(sum << 1U); + } +} + +void ref_correlate_q15(q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, + uint32_t srcBLen, q15_t *pDst) +{ + q15_t *pIn1 = pSrcA; /* inputA pointer */ + q15_t *pIn2 = pSrcB + (srcBLen - 1U); /* inputB pointer */ + q63_t sum; /* Accumulators */ + int32_t i = 0U, j; /* loop counters */ + uint32_t inv = 0U; /* Reverse order flag */ + uint32_t tot = 0U; /* Length */ + + /* Calculate the length of the remaining sequence */ + tot = ((srcALen + srcBLen) - 2U); + + if (srcALen > srcBLen) { + /* Calculating the number of zeros to be padded to the output */ + j = srcALen - srcBLen; + + /* Initialise the pointer after zero padding */ + pDst += j; + } + + else if (srcALen < srcBLen) { + /* Initialization to inputB pointer */ + pIn1 = pSrcB; + + /* Initialization to the end of inputA pointer */ + pIn2 = pSrcA + (srcALen - 1U); + + /* Initialisation of the pointer after zero padding */ + pDst = pDst + tot; + + /* Swapping the lengths */ + j = srcALen; + srcALen = srcBLen; + srcBLen = j; + + /* Setting the reverse flag */ + inv = 1; + } + + /* Loop to calculate convolution for output length number of times */ + for (i = 0U; i <= tot; i++) { + /* Initialize sum with zero to carry on MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0U; j <= i; j++) { + /* Check the array limitations */ + if ((((i - j) < srcBLen) && (j < srcALen))) { + /* z[i] += x[i-j] * y[j] */ + sum += ((q31_t)pIn1[j] * pIn2[-((int32_t)i - j)]); + } + } + /* Store the output in the destination buffer */ + if (inv == 1) + *pDst-- = (q15_t)ref_sat_q15(sum >> 15U); + else + *pDst++ = (q15_t)ref_sat_q15(sum >> 15U); + } +} + +void ref_correlate_fast_q15(q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, + uint32_t srcBLen, q15_t *pDst) +{ + q15_t *pIn1 = pSrcA; /* inputA pointer */ + q15_t *pIn2 = pSrcB + (srcBLen - 1U); /* inputB pointer */ + q63_t sum; /* Accumulators */ + int32_t i = 0U, j; /* loop counters */ + uint32_t inv = 0U; /* Reverse order flag */ + uint32_t tot = 0U; /* Length */ + + /* Calculate the length of the remaining sequence */ + tot = ((srcALen + srcBLen) - 2U); + + if (srcALen > srcBLen) { + /* Calculating the number of zeros to be padded to the output */ + j = srcALen - srcBLen; + + /* Initialise the pointer after zero padding */ + pDst += j; + } + + else if (srcALen < srcBLen) { + /* Initialization to inputB pointer */ + pIn1 = pSrcB; + + /* Initialization to the end of inputA pointer */ + pIn2 = pSrcA + (srcALen - 1U); + + /* Initialisation of the pointer after zero padding */ + pDst = pDst + tot; + + /* Swapping the lengths */ + j = srcALen; + srcALen = srcBLen; + srcBLen = j; + + /* Setting the reverse flag */ + inv = 1; + } + + /* Loop to calculate convolution for output length number of times */ + for (i = 0U; i <= tot; i++) { + /* Initialize sum with zero to carry on MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0U; j <= i; j++) { + /* Check the array limitations */ + if ((((i - j) < srcBLen) && (j < srcALen))) { + /* z[i] += x[i-j] * y[j] */ + sum += ((q31_t)pIn1[j] * pIn2[-((int32_t)i - j)]); + } + } + /* Store the output in the destination buffer */ + if (inv == 1) + *pDst-- = (q15_t)(sum >> 15U); + else + *pDst++ = (q15_t)(sum >> 15U); + } +} + +void ref_correlate_fast_opt_q15(q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, + uint32_t srcBLen, q15_t *pDst, q15_t *pScratch) +{ + q15_t *pIn1 = pSrcA; /* inputA pointer */ + q15_t *pIn2 = pSrcB + (srcBLen - 1U); /* inputB pointer */ + q31_t sum; /* Accumulators */ + int32_t i = 0U, j; /* loop counters */ + uint32_t inv = 0U; /* Reverse order flag */ + uint32_t tot = 0U; /* Length */ + + /* Calculate the length of the remaining sequence */ + tot = ((srcALen + srcBLen) - 2U); + + if (srcALen > srcBLen) { + /* Calculating the number of zeros to be padded to the output */ + j = srcALen - srcBLen; + + /* Initialise the pointer after zero padding */ + pDst += j; + } + + else if (srcALen < srcBLen) { + /* Initialization to inputB pointer */ + pIn1 = pSrcB; + + /* Initialization to the end of inputA pointer */ + pIn2 = pSrcA + (srcALen - 1U); + + /* Initialisation of the pointer after zero padding */ + pDst = pDst + tot; + + /* Swapping the lengths */ + j = srcALen; + srcALen = srcBLen; + srcBLen = j; + + /* Setting the reverse flag */ + inv = 1; + } + + /* Loop to calculate convolution for output length number of times */ + for (i = 0U; i <= tot; i++) { + /* Initialize sum with zero to carry on MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0U; j <= i; j++) { + /* Check the array limitations */ + if ((((i - j) < srcBLen) && (j < srcALen))) { + /* z[i] += x[i-j] * y[j] */ + sum += ((q31_t)pIn1[j] * pIn2[-((int32_t)i - j)]); + } + } + /* Store the output in the destination buffer */ + if (inv == 1) + *pDst-- = (q15_t)ref_sat_q15(sum >> 15U); + else + *pDst++ = (q15_t)ref_sat_q15(sum >> 15U); + } +} + +void ref_correlate_q7(q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, + uint32_t srcBLen, q7_t *pDst) +{ + q7_t *pIn1 = pSrcA; /* inputA pointer */ + q7_t *pIn2 = pSrcB + (srcBLen - 1U); /* inputB pointer */ + q31_t sum; /* Accumulator */ + int32_t i = 0U, j; /* loop counters */ + uint32_t inv = 0U; /* Reverse order flag */ + uint32_t tot = 0U; /* Length */ + + /* Calculate the length of the remaining sequence */ + tot = ((srcALen + srcBLen) - 2U); + + if (srcALen > srcBLen) { + /* Calculating the number of zeros to be padded to the output */ + j = srcALen - srcBLen; + + /* Initialise the pointer after zero padding */ + pDst += j; + } + + else if (srcALen < srcBLen) { + /* Initialization to inputB pointer */ + pIn1 = pSrcB; + + /* Initialization to the end of inputA pointer */ + pIn2 = pSrcA + (srcALen - 1U); + + /* Initialisation of the pointer after zero padding */ + pDst = pDst + tot; + + /* Swapping the lengths */ + j = srcALen; + srcALen = srcBLen; + srcBLen = j; + + /* Setting the reverse flag */ + inv = 1; + } + + /* Loop to calculate convolution for output length number of times */ + for (i = 0U; i <= tot; i++) { + /* Initialize sum with zero to carry on MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0U; j <= i; j++) { + /* Check the array limitations */ + if ((((i - j) < srcBLen) && (j < srcALen))) { + /* z[i] += x[i-j] * y[j] */ + sum += ((q15_t)pIn1[j] * pIn2[-((int32_t)i - j)]); + } + } + /* Store the output in the destination buffer */ + if (inv == 1) + *pDst-- = (q7_t)__SSAT((sum >> 7U), 8U); + else + *pDst++ = (q7_t)__SSAT((sum >> 7U), 8U); + } +} diff --git a/examples/dsp/ConvolutionFunctions_correlatePart/main.c b/examples/dsp/ConvolutionFunctions_correlatePart/main.c new file mode 100644 index 00000000..0258e318 --- /dev/null +++ b/examples/dsp/ConvolutionFunctions_correlatePart/main.c @@ -0,0 +1,177 @@ +// +// Created by lujun on 19-6-28. +// + +#include "riscv_math.h" +#include +#include +#include "array.h" +#include "../common.h" + +#include "../HelperFunctions/math_helper.c" +#include "../HelperFunctions/ref_helper.c" + +#include +#define DELTAF32 (0.05f) +#define DELTAQ31 (63) +#define DELTAQ15 (2) +#define DELTAQ7 (2) + +int test_flag_error = 0; + +int main() +{ + /* clang-format off */ + uint16_t i; + + /* clang-format on */ + + BENCH_INIT; + // ***************************************************** + // Correlation + // ***************************************************** + BENCH_START(riscv_correlate_f32); + riscv_correlate_f32(test_conv_input_f32_A, ARRAYA_SIZE_F32, test_conv_input_f32_B, ARRAYB_SIZE_F32, + output_f32); + BENCH_END(riscv_correlate_f32); + ref_correlate_f32(test_conv_input_f32_A, ARRAYA_SIZE_F32, test_conv_input_f32_B, ARRAYB_SIZE_F32, + output_f32_ref); + for (int i = 0; i < (2*max(ARRAYA_SIZE_F32, ARRAYB_SIZE_F32) - 1); i++) + if (fabs(output_f32_ref[i] - output_f32[i]) > DELTAF32) { + BENCH_ERROR(riscv_correlate_f32); + printf("index:%d, expect: %f, actual: %f\n", i, output_f32_ref[i], + output_f32[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_correlate_f32); + + BENCH_START(riscv_correlate_q31); + riscv_correlate_q31(test_conv_input_q31_A, ARRAYA_SIZE_Q31, test_conv_input_q31_B, ARRAYB_SIZE_Q31, + output_q31); + BENCH_END(riscv_correlate_q31); + ref_correlate_q31(test_conv_input_q31_A, ARRAYA_SIZE_Q31, test_conv_input_q31_B, ARRAYB_SIZE_Q31, + output_q31_ref); + for (int i = 0; i < (2*max(ARRAYA_SIZE_Q31, ARRAYB_SIZE_Q31) - 1); i++) + if (labs(output_q31_ref[i] - output_q31[i]) > DELTAQ31) { + BENCH_ERROR(riscv_correlate_q31); + printf("index:%d, expect: %d, actual: %d\n", i, + output_q31_ref[i - 200], output_q31[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_correlate_q31); + + BENCH_START(riscv_correlate_q15); + riscv_correlate_q15(test_conv_input_q15_A, ARRAYA_SIZE_Q15, test_conv_input_q15_B, ARRAYB_SIZE_Q15, + output_q15); + BENCH_END(riscv_correlate_q15); + ref_correlate_q15(test_conv_input_q15_A, ARRAYA_SIZE_Q15, test_conv_input_q15_B, ARRAYB_SIZE_Q15, + output_q15_ref); + for (int i = 0; i < (2*max(ARRAYA_SIZE_Q15, ARRAYB_SIZE_Q15) - 1); i++) + if (abs(0 - output_q15[i]) > DELTAQ15) { + BENCH_ERROR(riscv_correlate_q15); + printf("index:%d, expect: %d, actual: %d\n", i, output_q15_ref[i], + output_q15[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_correlate_q15); + + BENCH_START(riscv_correlate_q7); + riscv_correlate_q7(test_conv_input_q7_A, ARRAYA_SIZE_Q7, test_conv_input_q7_B, ARRAYB_SIZE_Q7, + output_q7); + BENCH_END(riscv_correlate_q7); + ref_correlate_q7(test_conv_input_q7_A, ARRAYA_SIZE_Q7, test_conv_input_q7_B, ARRAYB_SIZE_Q7, + output_q7_ref); + for (int i = 0; i < (2*max(ARRAYA_SIZE_Q7, ARRAYB_SIZE_Q7) - 1); i++) + if (abs(output_q7_ref[i] - output_q7[i]) > DELTAQ7) { + BENCH_ERROR(riscv_correlate_q7); + printf("index:%d, expect: %d, actual: %d\n", i, output_q7_ref[i], + output_q7[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_correlate_q7); + + BENCH_START(riscv_correlate_fast_q15); + riscv_correlate_fast_q15(test_conv_input_q15_A, ARRAYA_SIZE_Q15, test_conv_input_q15_B, + ARRAYB_SIZE_Q15, output_q15); + BENCH_END(riscv_correlate_fast_q15); + ref_correlate_fast_q15(test_conv_input_q15_A, ARRAYA_SIZE_Q15, test_conv_input_q15_B, + ARRAYB_SIZE_Q15, output_q15_ref); + for (int i = 0; i < (2*max(ARRAYA_SIZE_Q15, ARRAYB_SIZE_Q15) - 1); i++) + if (abs(output_q15_ref[i] - output_q15[i]) > DELTAQ15) { + BENCH_ERROR(riscv_correlate_fast_q15); + printf("index:%d, expect: %d, actual: %d\n", i, output_q15_ref[i], + output_q15[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_correlate_fast_q15); + + BENCH_START(riscv_correlate_fast_q31); + riscv_correlate_fast_q31(test_conv_input_q31_A, ARRAYA_SIZE_Q31, test_conv_input_q31_B, + ARRAYB_SIZE_Q31, output_q31); + BENCH_END(riscv_correlate_fast_q31); + ref_correlate_fast_q31(test_conv_input_q31_A, ARRAYA_SIZE_Q31, test_conv_input_q31_B, + ARRAYB_SIZE_Q31, output_q31_ref); + for (int i = 0; i < (2*max(ARRAYA_SIZE_Q31, ARRAYB_SIZE_Q31) - 1); i++) + if (labs(output_q31_ref[i] - output_q31[i]) > DELTAQ31) { + BENCH_ERROR(riscv_correlate_fast_q31); + printf("index:%d, expect: %d, actual: %d\n", i, output_q31_ref[i], + output_q31[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_correlate_fast_q31); + + BENCH_START(riscv_correlate_opt_q15); + riscv_correlate_opt_q15(test_conv_input_q15_A, ARRAYA_SIZE_Q15, test_conv_input_q15_B, ARRAYB_SIZE_Q15, + output_q15, pScratch1); + BENCH_END(riscv_correlate_opt_q15); + ref_correlate_opt_q15(test_conv_input_q15_A, ARRAYA_SIZE_Q15, test_conv_input_q15_B, ARRAYB_SIZE_Q15, + output_q15_ref, pScratch1); + for (int i = 0; i < (2*max(ARRAYA_SIZE_Q15, ARRAYB_SIZE_Q15) - 1); i++) + if (abs(output_q15_ref[i] - output_q15[i]) > DELTAQ15) { + BENCH_ERROR(riscv_correlate_opt_q15); + printf("index:%d, expect: %d, actual: %d\n", i, output_q15_ref[i], + output_q15[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_correlate_opt_q15); + + BENCH_START(riscv_correlate_opt_q7); + riscv_correlate_opt_q7(test_conv_input_q7_A, ARRAYA_SIZE_Q7, test_conv_input_q7_B, ARRAYB_SIZE_Q7, + output_q7, pScratch1, pScratch2); + BENCH_END(riscv_correlate_opt_q7); + ref_correlate_opt_q7(test_conv_input_q7_A, ARRAYA_SIZE_Q7, test_conv_input_q7_B, ARRAYB_SIZE_Q7, + output_q7_ref, pScratch1, pScratch2); + for (int i = 0; i < (2*max(ARRAYA_SIZE_Q7, ARRAYB_SIZE_Q7) - 1); i++) + if (abs(output_q7_ref[i] - output_q7[i]) > DELTAQ7) { + BENCH_ERROR(riscv_correlate_opt_q7); + printf("index:%d, expect: %d, actual: %d\n", i, output_q7_ref[i], + output_q7[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_correlate_opt_q7); + + BENCH_START(riscv_correlate_fast_opt_q15); + riscv_correlate_fast_opt_q15(test_conv_input_q15_A, ARRAYA_SIZE_Q15, + test_conv_input_q15_B, ARRAYB_SIZE_Q15, output_q15, + pScratch1); + BENCH_END(riscv_correlate_fast_opt_q15); + ref_correlate_fast_opt_q15(test_conv_input_q15_A, ARRAYA_SIZE_Q15, + test_conv_input_q15_B, ARRAYB_SIZE_Q15, output_q15_ref, + pScratch1); + for (int i = 0; i < (2*max(ARRAYA_SIZE_Q15, ARRAYB_SIZE_Q15) - 1); i++) + if (abs(output_q15_ref[i] - output_q15[i]) > DELTAQ15) { + BENCH_ERROR(riscv_correlate_fast_opt_q15); + printf("index:%d, expect: %d, actual: %d\n", i, output_q15_ref[i], + output_q15[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_correlate_fast_opt_q15); + BENCH_FINISH; + if (test_flag_error) { + printf("test error apprears, please recheck.\n"); + return 1; + } else { + printf("all test are passed. Well done!\n"); + } + return 0; +} diff --git a/examples/dsp/ConvolutionFunctions_particalPart/CMakeLists.txt b/examples/dsp/ConvolutionFunctions_particalPart/CMakeLists.txt new file mode 100644 index 00000000..3e9f0c8e --- /dev/null +++ b/examples/dsp/ConvolutionFunctions_particalPart/CMakeLists.txt @@ -0,0 +1,5 @@ +set(TARGET_REQUIRED_PRIVATE_INCLUDE ${CMAKE_CURRENT_SOURCE_DIR} ${CMAKE_CURRENT_SOURCE_DIR}/..) +set(TARGET_REQUIRED_SRCS conv.c) +set(TARGET_REQUIRED_LIBS nmsis) +set(mains main.c) +generate_bin() \ No newline at end of file diff --git a/examples/dsp/ConvolutionFunctions_particalPart/array.h b/examples/dsp/ConvolutionFunctions_particalPart/array.h new file mode 100644 index 00000000..47d38c19 --- /dev/null +++ b/examples/dsp/ConvolutionFunctions_particalPart/array.h @@ -0,0 +1,25 @@ +// Array for ConvolutionFunctions correlatePart +#define max(a,b)(a>b?a:b) +#define min(a,b)(a> 31U); + } +} + +void ref_conv_fast_q31(q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, + uint32_t srcBLen, q31_t *pDst) +{ + q31_t sum; /* Accumulator */ + uint32_t i, j; /* loop counter */ + + /* Loop to calculate output of convolution for output length number of times + */ + for (i = 0; i < srcALen + srcBLen - 1; i++) { + /* Initialize sum with zero to carry on MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0; j <= i; j++) { + /* Check the array limitations */ + if ((i - j < srcBLen) && (j < srcALen)) { + /* z[i] += x[i-j] * y[j] */ + sum = (q31_t)( + (((q63_t)sum << 32) + ((q63_t)pSrcA[j] * pSrcB[i - j])) >> + 32); + } + } + + /* Store the output in the destination buffer */ + pDst[i] = (q31_t)(sum << 1U); + } +} + +riscv_status ref_conv_partial_q31(q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, + uint32_t srcBLen, q31_t *pDst, + uint32_t firstIndex, uint32_t numPoints) +{ + ref_conv_q31(pSrcA, srcALen, pSrcB, srcBLen, pDst); + + return RISCV_MATH_SUCCESS; +} + +riscv_status ref_conv_partial_fast_q31(q31_t *pSrcA, uint32_t srcALen, + q31_t *pSrcB, uint32_t srcBLen, + q31_t *pDst, uint32_t firstIndex, + uint32_t numPoints) +{ + ref_conv_fast_q31(pSrcA, srcALen, pSrcB, srcBLen, pDst); + + return RISCV_MATH_SUCCESS; +} + +void ref_conv_q15(q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, + uint32_t srcBLen, q15_t *pDst) +{ + q63_t sum; /* Accumulator */ + uint32_t i, j; /* loop counter */ + + /* Loop to calculate output of convolution for output length number of times + */ + for (i = 0; i < srcALen + srcBLen - 1; i++) { + /* Initialize sum with zero to carry on MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0; j <= i; j++) { + /* Check the array limitations */ + if ((i - j < srcBLen) && (j < srcALen)) { + /* z[i] += x[i-j] * y[j] */ + sum += (q31_t)pSrcA[j] * pSrcB[i - j]; + } + } + + /* Store the output in the destination buffer */ + pDst[i] = ref_sat_q15(sum >> 15U); + } +} + +riscv_status ref_conv_partial_fast_opt_q15(q15_t *pSrcA, uint32_t srcALen, + q15_t *pSrcB, uint32_t srcBLen, + q15_t *pDst, uint32_t firstIndex, + uint32_t numPoints, q15_t *pScratch1, + q15_t *pScratch2) +{ + q31_t sum; /* Accumulator */ + uint32_t i, j; /* loop counter */ + + /* Loop to calculate output of convolution for output length number of times + */ + for (i = 0; i < srcALen + srcBLen - 1; i++) { + /* Initialize sum with zero to carry on MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0; j <= i; j++) { + /* Check the array limitations */ + if ((i - j < srcBLen) && (j < srcALen)) { + /* z[i] += x[i-j] * y[j] */ + sum += (q31_t)pSrcA[j] * pSrcB[i - j]; + } + } + + /* Store the output in the destination buffer */ + pDst[i] = ref_sat_q15(sum >> 15U); + } + + return RISCV_MATH_SUCCESS; +} + +void ref_conv_fast_q15(q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, + uint32_t srcBLen, q15_t *pDst) +{ + q31_t sum; /* Accumulator */ + uint32_t i, j; /* loop counter */ + + /* Loop to calculate output of convolution for output length number of times + */ + for (i = 0; i < srcALen + srcBLen - 1; i++) { + /* Initialize sum with zero to carry on MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0; j <= i; j++) { + /* Check the array limitations */ + if ((i - j < srcBLen) && (j < srcALen)) { + /* z[i] += x[i-j] * y[j] */ + sum += (q31_t)pSrcA[j] * pSrcB[i - j]; + } + } + + /* Store the output in the destination buffer */ + pDst[i] = sum >> 15U; + } +} + +void ref_conv_fast_opt_q15(q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, + uint32_t srcBLen, q15_t *pDst, q15_t *pScratch1, + q15_t *pScratch2) +{ + q31_t sum; /* Accumulator */ + uint32_t i, j; /* loop counter */ + + /* Loop to calculate output of convolution for output length number of times + */ + for (i = 0; i < srcALen + srcBLen - 1; i++) { + /* Initialize sum with zero to carry on MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0; j <= i; j++) { + /* Check the array limitations */ + if ((i - j < srcBLen) && (j < srcALen)) { + /* z[i] += x[i-j] * y[j] */ + sum += (q31_t)pSrcA[j] * pSrcB[i - j]; + } + } + + /* Store the output in the destination buffer */ + pDst[i] = ref_sat_q15(sum >> 15U); + } +} + +riscv_status ref_conv_partial_q15(q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, + uint32_t srcBLen, q15_t *pDst, + uint32_t firstIndex, uint32_t numPoints) +{ + ref_conv_q15(pSrcA, srcALen, pSrcB, srcBLen, pDst); + + return RISCV_MATH_SUCCESS; +} + +riscv_status ref_conv_partial_fast_q15(q15_t *pSrcA, uint32_t srcALen, + q15_t *pSrcB, uint32_t srcBLen, + q15_t *pDst, uint32_t firstIndex, + uint32_t numPoints) +{ + ref_conv_fast_q15(pSrcA, srcALen, pSrcB, srcBLen, pDst); + + return RISCV_MATH_SUCCESS; +} + +void ref_conv_q7(q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, uint32_t srcBLen, + q7_t *pDst) +{ + q31_t sum; /* Accumulator */ + uint32_t i, j; /* loop counter */ + + /* Loop to calculate output of convolution for output length number of times + */ + for (i = 0; i < srcALen + srcBLen - 1; i++) { + /* Initialize sum with zero to carry on MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0; j <= i; j++) { + /* Check the array limitations */ + if ((i - j < srcBLen) && (j < srcALen)) { + /* z[i] += x[i-j] * y[j] */ + sum += (q15_t)pSrcA[j] * pSrcB[i - j]; + } + } + + /* Store the output in the destination buffer */ + pDst[i] = (q7_t)ref_sat_q7(sum >> 7); + } +} + +riscv_status ref_conv_partial_q7(q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, + uint32_t srcBLen, q7_t *pDst, + uint32_t firstIndex, uint32_t numPoints) +{ + ref_conv_q7(pSrcA, srcALen, pSrcB, srcBLen, pDst); + + return RISCV_MATH_SUCCESS; +} diff --git a/examples/dsp/ConvolutionFunctions_particalPart/main.c b/examples/dsp/ConvolutionFunctions_particalPart/main.c new file mode 100644 index 00000000..9bb385db --- /dev/null +++ b/examples/dsp/ConvolutionFunctions_particalPart/main.c @@ -0,0 +1,175 @@ +// +// Created by lujun on 19-6-28. +// + +#include "riscv_math.h" +#include +#include +#include "array.h" +#include "../common.h" + +#include "../HelperFunctions/math_helper.c" +#include "../HelperFunctions/ref_helper.c" + +#include +#define DELTAF32 (0.05f) +#define DELTAQ31 (63) +#define DELTAQ15 (2) +#define DELTAQ7 (2) + +int test_flag_error = 0; + +int main() +{ + uint16_t i; + + BENCH_INIT; + // ***************************************************** + // conv partical part + // ***************************************************** + BENCH_START(riscv_conv_partial_f32); + riscv_conv_partial_f32(test_conv_input_f32_A, ARRAYA_SIZE_F32, test_conv_input_f32_B, ARRAYB_SIZE_F32, + output_f32, 10, 100); + BENCH_END(riscv_conv_partial_f32); + ref_conv_partial_f32(test_conv_input_f32_A, ARRAYA_SIZE_F32, test_conv_input_f32_B, ARRAYB_SIZE_F32, + output_f32_ref, 10, 100); + for (int i = 10; i < 100; i++) + if (fabs(output_f32_ref[i] - output_f32[i]) > DELTAF32) { + BENCH_ERROR(riscv_conv_partial_f32); + printf("index:%d, expect: %f, actual: %f\n", i, output_f32_ref[i], + output_f32[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_conv_partial_f32); + + BENCH_START(riscv_conv_partial_q31); + riscv_conv_partial_q31(test_conv_input_q31_A, ARRAYA_SIZE_Q31, test_conv_input_q31_B, ARRAYB_SIZE_Q31, + output_q31, 10, 200); + BENCH_END(riscv_conv_partial_q31); + ref_conv_partial_q31(test_conv_input_q31_A, ARRAYA_SIZE_Q31, test_conv_input_q31_B, ARRAYB_SIZE_Q31, + output_q31_ref, 10, 200); + for (int i = 10; i < 200; i++) + if (labs(output_q31_ref[i] - output_q31[i]) > DELTAQ31) { + BENCH_ERROR(riscv_conv_partial_q31); + printf("index:%d, expect: %d, actual: %d\n", i, output_q31_ref[i], + output_q31[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_conv_partial_q31); + + BENCH_START(riscv_conv_partial_q15); + riscv_conv_partial_q15(test_conv_input_q15_A, ARRAYA_SIZE_Q15, test_conv_input_q15_B, ARRAYB_SIZE_Q15, + output_q15, 10, 100); + BENCH_END(riscv_conv_partial_q15); + ref_conv_partial_q15(test_conv_input_q15_A, ARRAYA_SIZE_Q15, test_conv_input_q15_B, ARRAYB_SIZE_Q15, + output_q15_ref, 10, 100); + for (int i = 10; i < 100; i++) + if (abs(output_q15_ref[i] - output_q15[i]) > DELTAQ15) { + BENCH_ERROR(riscv_conv_partial_q15); + printf("index:%d, expect: %d, actual: %d\n", i, output_q15_ref[i], + output_q15[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_conv_partial_q15); + + BENCH_START(riscv_conv_partial_q7); + riscv_conv_partial_q7(test_conv_input_q7_A, ARRAYA_SIZE_Q7, test_conv_input_q7_B, ARRAYB_SIZE_Q7, + output_q7, 2, 14); + BENCH_END(riscv_conv_partial_q7); + ref_conv_partial_q7(test_conv_input_q7_A, ARRAYA_SIZE_Q7, test_conv_input_q7_B, ARRAYB_SIZE_Q7, + output_q7_ref, 2, 14); + for (int i = 2; i < 14; i++) + if (abs(output_q7_ref[i] - output_q7[i]) > DELTAQ7) { + BENCH_ERROR(riscv_conv_partial_q7); + printf("index:%d, expect: %d, actual: %d\n", i, output_q7_ref[i], + output_q7[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_conv_partial_q7); + + BENCH_START(riscv_conv_partial_fast_q31); + riscv_conv_partial_fast_q31(test_conv_input_q31_A, ARRAYA_SIZE_Q31, test_conv_input_q31_B, + ARRAYB_SIZE_Q31, output_q31, 10, 200); + BENCH_END(riscv_conv_partial_fast_q31); + ref_conv_partial_fast_q31(test_conv_input_q31_A, ARRAYA_SIZE_Q31, test_conv_input_q31_B, + ARRAYB_SIZE_Q31, output_q31_ref, 10, 200); + for (int i = 10; i < 200; i++) + if (labs(output_q31_ref[i] - output_q31[i]) > DELTAQ31) { + BENCH_ERROR(riscv_conv_partial_fast_q31); + printf("index:%d, expect: %d, actual: %d\n", i, output_q31_ref[i], + output_q31[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_conv_partial_fast_q31); + + BENCH_START(riscv_conv_partial_fast_q15); + riscv_conv_partial_fast_q15(test_conv_input_q15_A, ARRAYA_SIZE_Q15, test_conv_input_q15_B, + ARRAYB_SIZE_Q15, output_q15, 10, 100); + BENCH_END(riscv_conv_partial_fast_q15); + ref_conv_partial_fast_q15(test_conv_input_q15_A, ARRAYA_SIZE_Q15, test_conv_input_q15_B, + ARRAYB_SIZE_Q15, output_q15_ref, 10, 100); + for (int i = 10; i < 100; i++) + if (abs(output_q15_ref[i] - output_q15[i]) > DELTAQ15) { + BENCH_ERROR(riscv_conv_partial_fast_q15); + printf("index:%d, expect: %d, actual: %d\n", i, output_q15_ref[i], + output_q15[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_conv_partial_fast_q15); + + BENCH_START(riscv_conv_partial_opt_q15); + riscv_conv_partial_opt_q15(test_conv_input_q15_A, ARRAYA_SIZE_Q15, test_conv_input_q15_B, + ARRAYB_SIZE_Q15, output_q15, 10, 100, pScratch1, pScratch2); + BENCH_END(riscv_conv_partial_opt_q15); + ref_conv_partial_opt_q15(test_conv_input_q15_A, ARRAYA_SIZE_Q15, test_conv_input_q15_B, + ARRAYB_SIZE_Q15, output_q15_ref, 10, 100, pScratch1, + pScratch2); + for (int i = 10; i < 100; i++) + if (abs(output_q15_ref[i] - output_q15[i]) > DELTAQ15) { + BENCH_ERROR(riscv_conv_partial_opt_q15); + printf("index:%d, expect: %d, actual: %d\n", i, output_q15_ref[i], + output_q15[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_conv_partial_opt_q15); + + BENCH_START(riscv_conv_partial_opt_q7); + riscv_conv_partial_opt_q7(test_conv_input_q7_A, ARRAYA_SIZE_Q7, test_conv_input_q7_B, ARRAYB_SIZE_Q7, + output_q7, 2, 14, pScratch1, pScratch2); + BENCH_END(riscv_conv_partial_opt_q7); + ref_conv_partial_opt_q7(test_conv_input_q7_A, ARRAYA_SIZE_Q7, test_conv_input_q7_B, ARRAYB_SIZE_Q7, + output_q7_ref, 2, 14, pScratch1, pScratch2); + for (int i = 2; i < 14; i++) + if (abs(output_q7_ref[i] - output_q7[i]) > DELTAQ7) { + BENCH_ERROR(riscv_conv_partial_opt_q7); + printf("index:%d, expect: %d, actual: %d\n", i, output_q7_ref[i], + output_q7[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_conv_partial_opt_q7); + + BENCH_START(riscv_conv_partial_fast_opt_q15); + riscv_conv_partial_fast_opt_q15(test_conv_input_q15_A, ARRAYA_SIZE_Q15, + test_conv_input_q15_B, ARRAYB_SIZE_Q15, output_q15, 10, + 100, pScratch1, pScratch2); + BENCH_END(riscv_conv_partial_fast_opt_q15); + ref_conv_partial_fast_opt_q15(test_conv_input_q15_A, ARRAYA_SIZE_Q15, + test_conv_input_q15_B, ARRAYB_SIZE_Q15, output_q15_ref, + 10, 100, pScratch1, pScratch2); + for (int i = 10; i < 100; i++) + if (abs(output_q15_ref[i] - output_q15[i]) > DELTAQ15) { + BENCH_ERROR(riscv_conv_partial_fast_opt_q15); + printf("index:%d, expect: %d, actual: %d\n", i, output_q15_ref[i], + output_q15[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_conv_partial_fast_opt_q15); + BENCH_FINISH; + if (test_flag_error) { + printf("test error apprears, please recheck.\n"); + return 1; + } else { + printf("all test are passed. Well done!\n"); + } + return 0; +} diff --git a/examples/dsp/DistanceFunctions_part1/CMakeLists.txt b/examples/dsp/DistanceFunctions_part1/CMakeLists.txt new file mode 100644 index 00000000..6a0b0998 --- /dev/null +++ b/examples/dsp/DistanceFunctions_part1/CMakeLists.txt @@ -0,0 +1,4 @@ +set(TARGET_REQUIRED_PRIVATE_INCLUDE ${CMAKE_CURRENT_SOURCE_DIR} ${CMAKE_CURRENT_SOURCE_DIR}/..) +set(TARGET_REQUIRED_LIBS nmsis) +set(mains main.c) +generate_bin() \ No newline at end of file diff --git a/examples/dsp/DistanceFunctions_part1/array.h b/examples/dsp/DistanceFunctions_part1/array.h new file mode 100644 index 00000000..9eff91fe --- /dev/null +++ b/examples/dsp/DistanceFunctions_part1/array.h @@ -0,0 +1,27 @@ +// Array for DistanceFunctions part1 +float32_t f32_braycurtis_a_array[10] = {10,2,10,7,1,3,6,10,10,2}; +float32_t f32_braycurtis_b_array[10] = {10,10,5,9,2,5,10,8,10,7}; + +float32_t f32_canberra_a_array[10] = {0.0318328463774207,0.276922984960890,0.0461713906311539,0.0971317812358475,0.823457828327293,0.694828622975817,0.317099480060861,0.950222048838355,0.0344460805029088,0.438744359656398}; +float32_t f32_canberra_b_array[10] = {0.0357116785741896,0.849129305868777,0.933993247757551,0.678735154857774,0.757740130578333,0.743132468124916,0.392227019534168,0.655477890177557,0.171186687811562,0.706046088019609}; + +float32_t f32_chebyshev_a_array[10] = {0.0318328463774207,0.276922984960890,0.0461713906311539,0.0971317812358475,0.823457828327293,0.694828622975817,0.317099480060861,0.950222048838355,0.0344460805029088,0.438744359656398}; +float32_t f32_chebyshev_b_array[10] = {0.0357116785741896,0.849129305868777,0.933993247757551,0.678735154857774,0.757740130578333,0.743132468124916,0.392227019534168,0.655477890177557,0.171186687811562,0.706046088019609}; + +float32_t f32_cityblock_a_array[10] = {0.0318328463774207,0.276922984960890,0.0461713906311539,0.0971317812358475,0.823457828327293,0.694828622975817,0.317099480060861,0.950222048838355,0.0344460805029088,0.438744359656398}; +float32_t f32_cityblock_b_array[10] = {0.0357116785741896,0.849129305868777,0.933993247757551,0.678735154857774,0.757740130578333,0.743132468124916,0.392227019534168,0.655477890177557,0.171186687811562,0.706046088019609}; + +float32_t f32_correlation_a_array[10] = {0.0318328463774207,0.276922984960890,0.0461713906311539,0.0971317812358475,0.823457828327293,0.694828622975817,0.317099480060861,0.950222048838355,0.0344460805029088,0.438744359656398}; +float32_t f32_correlation_b_array[10] = {0.0357116785741896,0.849129305868777,0.933993247757551,0.678735154857774,0.757740130578333,0.743132468124916,0.392227019534168,0.655477890177557,0.171186687811562,0.706046088019609}; + +float32_t f32_cosine_a_array[10] = {0.0318328463774207,0.276922984960890,0.0461713906311539,0.0971317812358475,0.823457828327293,0.694828622975817,0.317099480060861,0.950222048838355,0.0344460805029088,0.438744359656398}; +float32_t f32_cosine_b_array[10] = {0.0357116785741896,0.849129305868777,0.933993247757551,0.678735154857774,0.757740130578333,0.743132468124916,0.392227019534168,0.655477890177557,0.171186687811562,0.706046088019609}; + +float32_t f32_euclidean_a_array[10] = {0.0318328463774207,0.276922984960890,0.0461713906311539,0.0971317812358475,0.823457828327293,0.694828622975817,0.317099480060861,0.950222048838355,0.0344460805029088,0.438744359656398}; +float32_t f32_euclidean_b_array[10] = {0.0357116785741896,0.849129305868777,0.933993247757551,0.678735154857774,0.757740130578333,0.743132468124916,0.392227019534168,0.655477890177557,0.171186687811562,0.706046088019609}; + +float32_t f32_jensenshannon_a_array[10] = {0.0318328463774207,0.276922984960890,0.0461713906311539,0.0971317812358475,0.823457828327293,0.694828622975817,0.317099480060861,0.950222048838355,0.0344460805029088,0.438744359656398}; +float32_t f32_jensenshannon_b_array[10] = {0.0357116785741896,0.849129305868777,0.933993247757551,0.678735154857774,0.757740130578333,0.743132468124916,0.392227019534168,0.655477890177557,0.171186687811562,0.706046088019609}; + +float32_t f32_minkowski_a_array[10] = {0.0318328463774207,0.276922984960890,0.0461713906311539,0.0971317812358475,0.823457828327293,0.694828622975817,0.317099480060861,0.950222048838355,0.0344460805029088,0.438744359656398}; +float32_t f32_minkowski_b_array[10] = {0.0357116785741896,0.849129305868777,0.933993247757551,0.678735154857774,0.757740130578333,0.743132468124916,0.392227019534168,0.655477890177557,0.171186687811562,0.706046088019609}; diff --git a/examples/dsp/DistanceFunctions_part1/main.c b/examples/dsp/DistanceFunctions_part1/main.c new file mode 100644 index 00000000..8ac1d84a --- /dev/null +++ b/examples/dsp/DistanceFunctions_part1/main.c @@ -0,0 +1,129 @@ +#include "riscv_math.h" +#include +#include +#include "array.h" +#include "../common.h" + +#include "../HelperFunctions/math_helper.c" +#include "../HelperFunctions/ref_helper.c" + +#include +#define DELTAF32 (0.05f) +#define DELTAQ31 (63) +#define DELTAQ15 (1) +#define DELTAQ7 (1) + +int test_flag_error = 0; + +int main() +{ + int i; + float32_t f32_output, f32_output_ref = 0.211678832116788; + BENCH_INIT; + //1-2( sun(min(Sai,Sbi)) / (sum(Sai)+sum(Sbi)) ) + BENCH_START(riscv_braycurtis_distance_f32); + f32_output = riscv_braycurtis_distance_f32(f32_braycurtis_a_array, f32_braycurtis_b_array, 10); + BENCH_END(riscv_braycurtis_distance_f32); + if (fabs(f32_output - f32_output_ref) > DELTAF32) { + BENCH_ERROR(riscv_braycurtis_distance_f32); + printf("expect: %f, actual: %f\n", f32_output_ref, f32_output); + test_flag_error = 1; + } + BENCH_STATUS(riscv_braycurtis_distance_f32); + + f32_output_ref = 3.48408251169646; + //sum(|pi-qi|/(|pi|+|qi|)) + BENCH_START(riscv_canberra_distance_f32); + f32_output = riscv_canberra_distance_f32(f32_canberra_a_array, f32_canberra_b_array, 10); + BENCH_END(riscv_canberra_distance_f32); + if (fabs(f32_output - f32_output_ref) > DELTAF32) { + BENCH_ERROR(riscv_canberra_distance_f32); + printf("expect: %f, actual: %f\n", f32_output_ref, f32_output); + test_flag_error = 1; + } + BENCH_STATUS(riscv_canberra_distance_f32); + + f32_output_ref = 0.887821857126397; + //x12=max(|x1i-x2i|) + BENCH_START(riscv_chebyshev_distance_f32); + f32_output = riscv_chebyshev_distance_f32(f32_chebyshev_a_array, f32_chebyshev_b_array, 10); + BENCH_END(riscv_chebyshev_distance_f32); + if (fabs(f32_output - f32_output_ref) > DELTAF32) { + BENCH_ERROR(riscv_chebyshev_distance_f32); + printf("expect: %f, actual: %f\n", f32_output_ref, f32_output); + test_flag_error = 1; + } + BENCH_STATUS(riscv_chebyshev_distance_f32); + + f32_output_ref = 2.93344596055701; + //also known as Manhattan Distance + //x12=sum(|x1i-x2i|) + BENCH_START(riscv_cityblock_distance_f32); + f32_output = riscv_cityblock_distance_f32(f32_cityblock_a_array, f32_cityblock_b_array, 10); + BENCH_END(riscv_cityblock_distance_f32); + if (fabs(f32_output - f32_output_ref) > DELTAF32) { + BENCH_ERROR(riscv_cityblock_distance_f32); + printf("expect: %f, actual: %f\n", f32_output_ref, f32_output); + test_flag_error = 1; + } + BENCH_STATUS(riscv_cityblock_distance_f32); + + f32_output_ref = 0.213739159949741; + //cos(sita)=a.b/|a||b|=sum(x1i*x2i)/ ( sum(abs(x1i)) * sum(abs(x1i)) ) + //actually it outputs 1-cos(sita) + BENCH_START(riscv_cosine_distance_f32); + f32_output = riscv_cosine_distance_f32(f32_cosine_a_array, f32_cosine_b_array, 10); + BENCH_END(riscv_cosine_distance_f32); + if (fabs(f32_output - f32_output_ref) > DELTAF32) { + BENCH_ERROR(riscv_cosine_distance_f32); + printf("expect: %f, actual: %f\n", f32_output_ref, f32_output); + test_flag_error = 1; + } + BENCH_STATUS(riscv_cosine_distance_f32); + + f32_output_ref = 1.28189071468851; + //sqrt(sum(square(x1i-x2i))) + BENCH_START(riscv_euclidean_distance_f32); + f32_output = riscv_euclidean_distance_f32(f32_euclidean_a_array, f32_euclidean_b_array, 10); + BENCH_END(riscv_euclidean_distance_f32); + if (fabs(f32_output - f32_output_ref) > DELTAF32) { + BENCH_ERROR(riscv_euclidean_distance_f32); + printf("expect: %f, actual: %f\n", f32_output_ref, f32_output); + test_flag_error = 1; + } + BENCH_STATUS(riscv_euclidean_distance_f32); + + + f32_output_ref = 0.733638397638707; + //sqrt(sum(square(x1i-x2i))) + BENCH_START(riscv_jensenshannon_distance_f32); + f32_output = riscv_jensenshannon_distance_f32(f32_jensenshannon_a_array, f32_jensenshannon_b_array, 10); + BENCH_END(riscv_jensenshannon_distance_f32); + if (fabs(f32_output - f32_output_ref) > DELTAF32) { + BENCH_ERROR(riscv_jensenshannon_distance_f32); + printf("expect: %f, actual: %f\n", f32_output_ref, f32_output); + test_flag_error = 1; + } + BENCH_STATUS(riscv_jensenshannon_distance_f32); + + f32_output_ref = 1.04218658878953; + //(sum(|xi-yi|p))1/p + //p and 1/p stands for power p and power 1/p + BENCH_START(riscv_minkowski_distance_f32); + f32_output = riscv_minkowski_distance_f32(f32_minkowski_a_array, f32_minkowski_b_array, 3, 10); + BENCH_END(riscv_minkowski_distance_f32); + if (fabs(f32_output - f32_output_ref) > DELTAF32) { + BENCH_ERROR(riscv_minkowski_distance_f32); + printf("expect: %f, actual: %f\n", f32_output_ref, f32_output); + test_flag_error = 1; + } + BENCH_STATUS(riscv_minkowski_distance_f32); + BENCH_FINISH; + if (test_flag_error) { + printf("test error apprears, please recheck.\n"); + return 1; + } else { + printf("all test are passed. Well done!\n"); + } + return 0; +}; diff --git a/examples/dsp/DistanceFunctions_part2/CMakeLists.txt b/examples/dsp/DistanceFunctions_part2/CMakeLists.txt new file mode 100644 index 00000000..6a0b0998 --- /dev/null +++ b/examples/dsp/DistanceFunctions_part2/CMakeLists.txt @@ -0,0 +1,4 @@ +set(TARGET_REQUIRED_PRIVATE_INCLUDE ${CMAKE_CURRENT_SOURCE_DIR} ${CMAKE_CURRENT_SOURCE_DIR}/..) +set(TARGET_REQUIRED_LIBS nmsis) +set(mains main.c) +generate_bin() \ No newline at end of file diff --git a/examples/dsp/DistanceFunctions_part2/array.h b/examples/dsp/DistanceFunctions_part2/array.h new file mode 100644 index 00000000..7693f6b4 --- /dev/null +++ b/examples/dsp/DistanceFunctions_part2/array.h @@ -0,0 +1,45 @@ +// Array for DistanceFunctions part2 +//11111111111111110000000000010000 1111 +uint32_t u32_dice_a_array[2] = {0xffff0010,0xf0000000}; +//11111111000011110000111100000000 1010 +uint32_t u32_dice_b_array[2] = {0xff0f0f00,0xa0000000}; + +//01010001001111011010011101000010 1010 +uint32_t u32_hamming_a_array[2] = {0x513DA742,0xa0000000}; +//11100010111000101110001010000111 0110 +uint32_t u32_hamming_b_array[2] = {0xE2E2E287,0x60000000}; + +//10000000011000100100000111000100 0111 +uint32_t u32_jaccard_a_array[2] = {0x806241C4,0x70000000}; +//01010100110110000111110110111110 0001 +uint32_t u32_jaccard_b_array[2] = {0x54D87DBE,0x10000000}; + +//00000010011000010110000010010110 1001 +uint32_t u32_kulsinski_a_array[2] = {0x02616096,0x90000000}; +//11001100101110001010101111010011 0111 +uint32_t u32_kulsinski_b_array[2] = {0xCCB8ABD3,0x70000000}; + +//11100100011100100101110111110010 0001 +uint32_t u32_rogerstanimoto_a_array[2] = {0xE4725DF2,0x10000000}; +//10010110001000000110100110101111 1001 +uint32_t u32_rogerstanimoto_b_array[2] = {0x962069AF,0x90000000}; + +//00111000101100000100100101110101 1101 +uint32_t u32_russellrao_a_array[2] = {0x38B04975,0xd0000000}; +//00000001011100011011110011000000 1011 +uint32_t u32_russellrao_b_array[2] = {0x0171BCC0,0xb0000000}; + +//11101011000110110101000010100010 0010 +uint32_t u32_sokalmichener_a_array[2] = {0xEB1B50A2,0x20000000}; +//10101000111011111010010011010110 1111 +uint32_t u32_sokalmichener_b_array[2] = {0xA8EFA4D6,0xf0000000}; + +//00011011111110000000111110010111 0011 +uint32_t u32_sokalsneath_a_array[2] = {0x1BF80F97,0x30000000}; +//10010010010101100000010101011001 1010 +uint32_t u32_sokalsneath_b_array[2] = {0x92560559,0xa0000000}; + +//11011111000111010001000001111111 1011 +uint32_t u32_yule_a_array[2] = {0xDF1D107F,0xb0000000}; +//11010011111010111111111001010110 1000 +uint32_t u32_yule_b_array[2] = {0xD3EBFE56,0x80000000}; diff --git a/examples/dsp/DistanceFunctions_part2/main.c b/examples/dsp/DistanceFunctions_part2/main.c new file mode 100644 index 00000000..fa8df30c --- /dev/null +++ b/examples/dsp/DistanceFunctions_part2/main.c @@ -0,0 +1,147 @@ +#include "riscv_math.h" +#include +#include +#include "array.h" +#include "../common.h" + +#include "../HelperFunctions/math_helper.c" +#include "../HelperFunctions/ref_helper.c" + +#include +#define DELTAF32 (0.05f) +#define DELTAQ31 (63) +#define DELTAQ15 (1) +#define DELTAQ7 (1) + +int test_flag_error = 0; + +int main() +{ + int i; + +// Noticing that all the following functions are in Big-end! + + BENCH_INIT; + float32_t f32_output, f32_output_ref = 0.282051282051282; + //1.0*(ctf + cft) / (2.0*ctt + cft + ctf) + //t stands for true,f stands for false + BENCH_START(riscv_dice_distance); + f32_output = riscv_dice_distance(u32_dice_a_array, u32_dice_b_array, 36); + BENCH_END(riscv_dice_distance); + if (fabs(f32_output - f32_output_ref) > DELTAF32) { + BENCH_ERROR(riscv_dice_distance); + printf("expect: %f, actual: %f\n", f32_output_ref, f32_output); + test_flag_error = 1; + } + BENCH_STATUS(riscv_dice_distance); + + f32_output_ref = 0.583333333333333; + //1.0*(ctf + cft) / numberOfBools + BENCH_START(riscv_hamming_distance); + f32_output = riscv_hamming_distance(u32_hamming_a_array, u32_hamming_b_array, 36); + BENCH_END(riscv_hamming_distance); + if (fabs(f32_output - f32_output_ref) > DELTAF32) { + BENCH_ERROR(riscv_hamming_distance); + printf("expect: %f, actual: %f\n", f32_output_ref, f32_output); + test_flag_error = 1; + } + BENCH_STATUS(riscv_hamming_distance); + + f32_output_ref = 0.769230769230769; + //1.0*(ctf + cft) / (ctt + cft + ctf) + BENCH_START(riscv_jaccard_distance); + f32_output = riscv_jaccard_distance(u32_jaccard_a_array, u32_jaccard_b_array, 36); + BENCH_END(riscv_jaccard_distance); + if (fabs(f32_output - f32_output_ref) > DELTAF32) { + BENCH_ERROR(riscv_jaccard_distance); + printf("expect: %f, actual: %f\n", f32_output_ref, f32_output); + test_flag_error = 1; + } + BENCH_STATUS(riscv_jaccard_distance); + + f32_output_ref = 0.894736842105263; + //1.0*(ctf + cft - ctt + numberOfBools) / (cft + ctf + numberOfBools) + BENCH_START(riscv_kulsinski_distance); + f32_output = riscv_kulsinski_distance(u32_kulsinski_a_array, u32_kulsinski_b_array, 36); + BENCH_END(riscv_kulsinski_distance); + if (fabs(f32_output - f32_output_ref) > DELTAF32) { + BENCH_ERROR(riscv_kulsinski_distance); + printf("expect: %f, actual: %f\n", f32_output_ref, f32_output); + test_flag_error = 1; + } + BENCH_STATUS(riscv_kulsinski_distance); + + f32_output_ref = 0.615384615384615; + //r = 2*(ctf + cft) + //return(1.0*r / (r + ctt + cff)) + BENCH_START(riscv_rogerstanimoto_distance); + f32_output = riscv_rogerstanimoto_distance(u32_rogerstanimoto_a_array, u32_rogerstanimoto_b_array, 36); + BENCH_END(riscv_rogerstanimoto_distance); + if (fabs(f32_output - f32_output_ref) > DELTAF32) { + BENCH_ERROR(riscv_rogerstanimoto_distance); + printf("expect: %f, actual: %f\n", f32_output_ref, f32_output); + test_flag_error = 1; + } + BENCH_STATUS(riscv_rogerstanimoto_distance); + + f32_output_ref = 0.833333333333333; + //1.0*(numberOfBools - ctt) / ((float32_t)numberOfBools) + BENCH_START(riscv_russellrao_distance); + f32_output = riscv_russellrao_distance(u32_russellrao_a_array, u32_russellrao_b_array, 36); + BENCH_END(riscv_russellrao_distance); + if (fabs(f32_output - f32_output_ref) > DELTAF32) { + BENCH_ERROR(riscv_russellrao_distance); + printf("expect: %f, actual: %f\n", f32_output_ref, f32_output); + test_flag_error = 1; + } + BENCH_STATUS(riscv_russellrao_distance); + + f32_output_ref = 0.714285714285714; + //r = 2.0*(ctf + cft); + //s = 1.0*(cff + ctt); + //r / (s+r) + BENCH_START(riscv_sokalmichener_distance); + f32_output = riscv_sokalmichener_distance(u32_sokalmichener_a_array, u32_sokalmichener_b_array, 36); + BENCH_END(riscv_sokalmichener_distance); + if (fabs(f32_output - f32_output_ref) > DELTAF32) { + BENCH_ERROR(riscv_sokalmichener_distance); + printf("expect: %f, actual: %f\n", f32_output_ref, f32_output); + test_flag_error = 1; + } + BENCH_STATUS(riscv_sokalmichener_distance); + + f32_output_ref = 0.790697674418605; + //r = 2.0*(ctf + cft); + //r / (r + ctt) + BENCH_START(riscv_sokalsneath_distance); + f32_output = riscv_sokalsneath_distance(u32_sokalsneath_a_array, u32_sokalsneath_b_array, 36); + BENCH_END(riscv_sokalsneath_distance); + if (fabs(f32_output - f32_output_ref) > DELTAF32) { + BENCH_ERROR(riscv_sokalsneath_distance); + printf("expect: %f, actual: %f\n", f32_output_ref, f32_output); + test_flag_error = 1; + } + BENCH_STATUS(riscv_sokalsneath_distance); + + f32_output_ref = 1.26760563380282; + //r = 2*(ctf * cft); + //1.0*r / (r/2.0 + ctt * cff) + BENCH_START(riscv_yule_distance); + f32_output = riscv_yule_distance(u32_yule_a_array, u32_yule_b_array, 36); + BENCH_END(riscv_yule_distance); + if (fabs(f32_output - f32_output_ref) > DELTAF32) { + BENCH_ERROR(riscv_yule_distance); + printf("expect: %f, actual: %f\n", f32_output_ref, f32_output); + test_flag_error = 1; + } + BENCH_STATUS(riscv_yule_distance); + + BENCH_FINISH; + if (test_flag_error) { + printf("test error apprears, please recheck.\n"); + return 1; + } else { + printf("all test are passed. Well done!\n"); + } + return 0; +}; diff --git a/examples/dsp/FastMathFunctions_squareRootPart/CMakeLists.txt b/examples/dsp/FastMathFunctions_squareRootPart/CMakeLists.txt new file mode 100644 index 00000000..8c8a4a1e --- /dev/null +++ b/examples/dsp/FastMathFunctions_squareRootPart/CMakeLists.txt @@ -0,0 +1,5 @@ +set(TARGET_REQUIRED_PRIVATE_INCLUDE ${CMAKE_CURRENT_SOURCE_DIR} ${CMAKE_CURRENT_SOURCE_DIR}/..) +set(TARGET_REQUIRED_SRCS divide.c exp.c log.c sqrt.c) +set(TARGET_REQUIRED_LIBS nmsis) +set(mains main.c) +generate_bin() \ No newline at end of file diff --git a/examples/dsp/FastMathFunctions_squareRootPart/divide.c b/examples/dsp/FastMathFunctions_squareRootPart/divide.c new file mode 100644 index 00000000..835b07e1 --- /dev/null +++ b/examples/dsp/FastMathFunctions_squareRootPart/divide.c @@ -0,0 +1,49 @@ +#include "ref.h" + +riscv_status ref_divide_q15(q15_t numerator, + q15_t denominator, + q15_t *quotient, + int16_t *shift) +{ + int16_t sign=0; + q31_t temp; + int16_t shiftForNormalizing; + + *shift = 0; + + sign = (numerator>>15) ^ (denominator>>15); + + if (denominator == 0) + { + if (sign) + { + *quotient = 0x8000; + } + else + { + *quotient = 0x7FFF; + } + return(RISCV_MATH_NANINF); + } + + numerator = abs(numerator); + denominator = abs(denominator); + + temp = ((q31_t)numerator << 15) / ((q31_t)denominator); + + shiftForNormalizing= 17 - __CLZ(temp); + if (shiftForNormalizing > 0) + { + *shift = shiftForNormalizing; + temp = temp >> shiftForNormalizing; + } + + if (sign) + { + temp = -temp; + } + + *quotient=temp; + + return(RISCV_MATH_SUCCESS); +} \ No newline at end of file diff --git a/examples/dsp/FastMathFunctions_squareRootPart/exp.c b/examples/dsp/FastMathFunctions_squareRootPart/exp.c new file mode 100644 index 00000000..ea567678 --- /dev/null +++ b/examples/dsp/FastMathFunctions_squareRootPart/exp.c @@ -0,0 +1,22 @@ +#include "ref.h" + +void ref_vexp_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; + + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* C = log(A) */ + + /* Calculate log and store result in destination buffer. */ + *pDst++ = expf(*pSrc++); + + /* Decrement loop counter */ + blkCnt--; + } +} \ No newline at end of file diff --git a/examples/dsp/FastMathFunctions_squareRootPart/log.c b/examples/dsp/FastMathFunctions_squareRootPart/log.c new file mode 100644 index 00000000..04988bb9 --- /dev/null +++ b/examples/dsp/FastMathFunctions_squareRootPart/log.c @@ -0,0 +1,22 @@ +#include "ref.h" + +void ref_vlog_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; + + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* C = log(A) */ + + /* Calculate log and store result in destination buffer. */ + *pDst++ = logf(*pSrc++); + + /* Decrement loop counter */ + blkCnt--; + } +} \ No newline at end of file diff --git a/examples/dsp/FastMathFunctions_squareRootPart/main.c b/examples/dsp/FastMathFunctions_squareRootPart/main.c new file mode 100644 index 00000000..57c9caee --- /dev/null +++ b/examples/dsp/FastMathFunctions_squareRootPart/main.c @@ -0,0 +1,144 @@ +// +// Created by lujun on 19-6-28. +// +// This contains sin, cos and sqrt calculates +// each one has it's own function. +// All function can be found in main function. +// If you don't want to use it, then comment it. +#include "riscv_math.h" +#include +#include +#include "../common.h" + +#include "../HelperFunctions/math_helper.c" +#include "../HelperFunctions/ref_helper.c" + +#include +#define DELTAF32 (0.05f) +#define DELTAQ31 (63) +#define DELTAQ15 (1) +#define DELTAQ7 (1) + +int test_flag_error = 0; + +static int DSP_SQRT(void) +{ + float32_t f32_pOUT, f32_pOUT_ref; + q31_t q31_pOUT, q31_pOUT_ref; + q15_t q15_pOUT, q15_pOUT_ref; + // f32_sqrt + BENCH_START(riscv_sqrt_f32); + for (int i = 0; i < 1000; i++) + riscv_sqrt_f32(100, &f32_pOUT); + BENCH_END(riscv_sqrt_f32); + // ref_sqrt_f32(100, &f32_pOUT_ref); + f32_pOUT_ref = 10.0f; + if (fabs(f32_pOUT - f32_pOUT_ref) > DELTAF32) { + BENCH_ERROR(riscv_sqrt_f32); + printf("expect: %f, actual: %f\n", f32_pOUT_ref, f32_pOUT); + test_flag_error = 1; + } + BENCH_STATUS(riscv_sqrt_f32); + // q31_sqrt + BENCH_START(riscv_sqrt_q31); + for (int i = 0; i < 1000; i++) + riscv_sqrt_q31(100, &q31_pOUT); + BENCH_END(riscv_sqrt_q31); + ref_sqrt_q31(100, &q31_pOUT_ref); + if (labs(q31_pOUT - q31_pOUT_ref) > DELTAQ31) { + BENCH_ERROR(riscv_sqrt_q31); + printf("expect: %x, actual: %x\n", q31_pOUT_ref, q31_pOUT); + test_flag_error = 1; + } + BENCH_STATUS(riscv_sqrt_q31); + // q15_sqrt + BENCH_START(riscv_sqrt_q15); + for (int i = 0; i < 1000; i++) + riscv_sqrt_q15(100, &q15_pOUT); + BENCH_END(riscv_sqrt_q15); + ref_sqrt_q15(100, &q15_pOUT_ref); + if (abs(q15_pOUT - q15_pOUT_ref) > DELTAQ15) { + BENCH_ERROR(riscv_sqrt_q15); + printf("expect: %x, actual: %x\n", q15_pOUT_ref, q15_pOUT); + test_flag_error = 1; + } + BENCH_STATUS(riscv_sqrt_q15); +} + +static int DSP_DIVIDE(void) +{ + q15_t q15_pOUT, q15_pOUT_ref; + int16_t shift; + // q15_sqrt + BENCH_START(riscv_divide_q15); + for (int i = 0; i < 1000; i++) + riscv_divide_q15(4203, 2490, &q15_pOUT, &shift); + BENCH_END(riscv_divide_q15); + ref_divide_q15(4203, 2490, &q15_pOUT_ref, &shift); + if (abs(q15_pOUT - q15_pOUT_ref) > DELTAQ15) { + BENCH_ERROR(riscv_divide_q15); + printf("expect: %x, actual: %x\n", q15_pOUT_ref, q15_pOUT); + test_flag_error = 1; + } + BENCH_STATUS(riscv_divide_q15); +} + +static int DSP_EXP(void) +{ + float32_t f32_pOUT[256], f32_pOUT_ref[256]; + float32_t f32_pIN[256]; + for (int i = 0; i < 256; i++) + f32_pIN[i] = (float32_t) rand(); + // f32_sqrt + BENCH_START(riscv_vexp_f32); + for (int i = 0; i < 256; i++) + riscv_vexp_f32(f32_pIN, &f32_pOUT, 256); + BENCH_END(riscv_vexp_f32); + ref_vexp_f32(f32_pIN, &f32_pOUT_ref, 256); + for (int i = 0; i < 256; i++) + if (fabs(f32_pOUT[i] - f32_pOUT_ref[i]) > DELTAF32) { + BENCH_ERROR(riscv_vexp_f32); + printf("index: %d, expect: %f, actual: %f\n", i, f32_pOUT_ref[i], f32_pOUT[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_vexp_f32); +} + +static int DSP_LOG(void) +{ + float32_t f32_pOUT[256], f32_pOUT_ref[256]; + float32_t f32_pIN[256]; + for (int i = 0; i < 256; i++) + f32_pIN[i] = (float32_t) rand(); + // f32_sqrt + BENCH_START(riscv_vlog_f32); + for (int i = 0; i < 256; i++) + riscv_vlog_f32(f32_pIN, &f32_pOUT, 256); + BENCH_END(riscv_vlog_f32); + ref_vlog_f32(f32_pIN, &f32_pOUT_ref, 256); + for (int i = 0; i < 256; i++) + if (fabs(f32_pOUT[i] - f32_pOUT_ref[i]) > DELTAF32) { + BENCH_ERROR(riscv_vlog_f32); + printf("index: %d, expect: %f, actual: %f\n", i, f32_pOUT_ref[i], f32_pOUT[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_vlog_f32); +} + + +int main() +{ + BENCH_INIT; + DSP_SQRT(); + DSP_DIVIDE(); + DSP_EXP(); + DSP_LOG(); + BENCH_FINISH; + if (test_flag_error) { + printf("test error apprears, please recheck.\n"); + return 1; + } else { + printf("all test are passed. Well done!\n"); + } + return 0; +} diff --git a/examples/dsp/FastMathFunctions_squareRootPart/sqrt.c b/examples/dsp/FastMathFunctions_squareRootPart/sqrt.c new file mode 100644 index 00000000..9185e93f --- /dev/null +++ b/examples/dsp/FastMathFunctions_squareRootPart/sqrt.c @@ -0,0 +1,15 @@ +#include "ref.h" + +riscv_status ref_sqrt_q31(q31_t in, q31_t *pOut) +{ + *pOut = (q31_t)(sqrtf((float32_t)in / 2147483648.0f) * 2147483648.0f); + + return RISCV_MATH_SUCCESS; +} + +riscv_status ref_sqrt_q15(q15_t in, q15_t *pOut) +{ + *pOut = (q15_t)(sqrtf((float32_t)in / 32768.0f) * 32768.0f); + + return RISCV_MATH_SUCCESS; +} diff --git a/examples/dsp/FastMathFunctions_trigonometricPart/CMakeLists.txt b/examples/dsp/FastMathFunctions_trigonometricPart/CMakeLists.txt new file mode 100644 index 00000000..14bf0085 --- /dev/null +++ b/examples/dsp/FastMathFunctions_trigonometricPart/CMakeLists.txt @@ -0,0 +1,5 @@ +set(TARGET_REQUIRED_PRIVATE_INCLUDE ${CMAKE_CURRENT_SOURCE_DIR} ${CMAKE_CURRENT_SOURCE_DIR}/..) +set(TARGET_REQUIRED_SRCS sin.c cos.c) +set(TARGET_REQUIRED_LIBS nmsis) +set(mains main.c) +generate_bin() \ No newline at end of file diff --git a/examples/dsp/FastMathFunctions_trigonometricPart/cos.c b/examples/dsp/FastMathFunctions_trigonometricPart/cos.c new file mode 100644 index 00000000..1f1fb0c1 --- /dev/null +++ b/examples/dsp/FastMathFunctions_trigonometricPart/cos.c @@ -0,0 +1,13 @@ +#include "ref.h" + +q31_t ref_cos_q31(q31_t x) +{ + return (q31_t)(cosf((float32_t)x * 6.28318530717959f / 2147483648.0f) * + 2147483648.0f); +} + +q15_t ref_cos_q15(q15_t x) +{ + return (q15_t)(cosf((float32_t)x * 6.28318530717959f / 32768.0f) * + 32768.0f); +} diff --git a/examples/dsp/FastMathFunctions_trigonometricPart/main.c b/examples/dsp/FastMathFunctions_trigonometricPart/main.c new file mode 100644 index 00000000..d287e930 --- /dev/null +++ b/examples/dsp/FastMathFunctions_trigonometricPart/main.c @@ -0,0 +1,134 @@ +// +// Created by lujun on 19-6-28. +// +// This contains sin, cos and sqrt calculates +// each one has it's own function. +// All function can be found in main function. +// If you don't want to use it, then comment it. +#include "riscv_math.h" +#include +#include +#include "../common.h" + +#include "../HelperFunctions/math_helper.c" +#include "../HelperFunctions/ref_helper.c" + +#include +#define DELTAF32 (0.05f) +#define DELTAQ31 (63) +#define DELTAQ15 (1) +#define DELTAQ7 (1) + +int test_flag_error = 0; + +static int DSP_COS(void) +{ + // f32_cos + float32_t f32_cosoutput, f32_cosoutput_ref; + uint16_t i; + BENCH_START(riscv_cos_f32); + for (int i = 0; i < 1000; i++) + f32_cosoutput = riscv_cos_f32(PI); + BENCH_END(riscv_cos_f32); + f32_cosoutput_ref = ref_cos_f32(PI); + if (fabs(f32_cosoutput - f32_cosoutput_ref) > DELTAF32) { + BENCH_ERROR(riscv_cos_f32); + printf("expect: %f, actual: %f\n", f32_cosoutput_ref, f32_cosoutput); + test_flag_error = 1; + } + BENCH_STATUS(riscv_cos_f32); + // q31_cos + q31_t q31_cosoutput, q31_cosoutput_ref; + BENCH_START(riscv_cos_q31); + for (int i = 0; i < 1000; i++) + q31_cosoutput = riscv_cos_q31(0x7ffffff0); + BENCH_END(riscv_cos_q31); + q31_cosoutput_ref = ref_cos_q31(0x7ffffff0); + if (labs(q31_cosoutput - q31_cosoutput_ref) > DELTAQ31) { + BENCH_ERROR(riscv_cos_q31); + printf("expect: %x, actual: %x\n", q31_cosoutput_ref, q31_cosoutput); + test_flag_error = 1; + } + BENCH_STATUS(riscv_cos_q31); + // q15_cos + q15_t q15_cosoutput, q15_cosoutput_ref; + BENCH_START(riscv_cos_q15); + for (int i = 0; i < 1000; i++) + q15_cosoutput = riscv_cos_q15(0x7000); + BENCH_END(riscv_cos_q15); + q15_cosoutput_ref = ref_cos_q15(0x7000); + if (abs(q15_cosoutput - q15_cosoutput_ref) > DELTAQ15) { + BENCH_ERROR(riscv_cos_q15); + printf("expect: %x, actual: %x\n", q15_cosoutput_ref, q15_cosoutput); + test_flag_error = 1; + } + BENCH_STATUS(riscv_cos_q15); + printf("all cos tests are passed,well done!\n"); +} +/* +********************************************************************************************************* +* 函 数 名: DSP_Sine +* 功能说明: 求sine函数 +* 形 参：无 +* 返 回 值: 无 +********************************************************************************************************* +*/ +static int DSP_SIN(void) +{ + // f32_sin + float32_t f32_sinoutput, f32_sinoutput_ref; + uint16_t i; + BENCH_START(riscv_sin_f32); + for (int i = 0; i < 1000; i++) + f32_sinoutput = riscv_sin_f32(PI); + BENCH_END(riscv_sin_f32); + f32_sinoutput_ref = ref_sin_f32(PI); + if (fabs(f32_sinoutput - f32_sinoutput_ref) > DELTAF32) { + BENCH_ERROR(riscv_sin_f32); + printf("expect: %f, actual: %f\n", f32_sinoutput_ref, f32_sinoutput); + test_flag_error = 1; + } + BENCH_STATUS(riscv_sin_f32); + // q31_sin + q31_t q31_sinoutput, q31_sinoutput_ref; + BENCH_START(riscv_sin_q31); + for (int i = 0; i < 1000; i++) + q31_sinoutput = riscv_sin_q31(PI); + BENCH_END(riscv_sin_q31); + q31_sinoutput_ref = ref_sin_q31(PI); + if (labs(q31_sinoutput - q31_sinoutput_ref) > DELTAQ31) { + BENCH_ERROR(riscv_sin_q31); + printf("expect: %x, actual: %x\n", q31_sinoutput_ref, q31_sinoutput); + test_flag_error = 1; + } + BENCH_STATUS(riscv_sin_q31); + // q15_sin + q15_t q15_sinoutput, q15_sinoutput_ref; + BENCH_START(riscv_sin_q15); + for (int i = 0; i < 1000; i++) + q15_sinoutput = riscv_sin_q15(PI); + BENCH_END(riscv_sin_q15); + q15_sinoutput_ref = ref_sin_q15(PI); + if (abs(q15_sinoutput - q15_sinoutput_ref) > DELTAQ15) { + BENCH_ERROR(riscv_sin_q15); + printf("expect: %x, actual: %x\n", q15_sinoutput_ref, q15_sinoutput); + test_flag_error = 1; + } + BENCH_STATUS(riscv_sin_q15); + printf("all sin tests are passed,well done!\n"); +} + +int main() +{ + BENCH_INIT; + DSP_COS(); + DSP_SIN(); + BENCH_FINISH; + if (test_flag_error) { + printf("test error apprears, please recheck.\n"); + return 1; + } else { + printf("all test are passed. Well done!\n"); + } + return 0; +} diff --git a/examples/dsp/FastMathFunctions_trigonometricPart/sin.c b/examples/dsp/FastMathFunctions_trigonometricPart/sin.c new file mode 100644 index 00000000..cc43098f --- /dev/null +++ b/examples/dsp/FastMathFunctions_trigonometricPart/sin.c @@ -0,0 +1,13 @@ +#include "ref.h" + +q31_t ref_sin_q31(q31_t x) +{ + return (q31_t)(sinf((float32_t)x * 6.28318530717959f / 2147483648.0f) * + 2147483648.0f); +} + +q15_t ref_sin_q15(q15_t x) +{ + return (q15_t)(sinf((float32_t)x * 6.28318530717959f / 32768.0f) * + 32768.0f); +} diff --git a/examples/dsp/FilteringFunction_LMSPart/CMakeLists.txt b/examples/dsp/FilteringFunction_LMSPart/CMakeLists.txt new file mode 100644 index 00000000..687f3402 --- /dev/null +++ b/examples/dsp/FilteringFunction_LMSPart/CMakeLists.txt @@ -0,0 +1,5 @@ +set(TARGET_REQUIRED_PRIVATE_INCLUDE ${CMAKE_CURRENT_SOURCE_DIR} ${CMAKE_CURRENT_SOURCE_DIR}/..) +set(TARGET_REQUIRED_SRCS lms.c) +set(TARGET_REQUIRED_LIBS nmsis) +set(mains main.c) +generate_bin() \ No newline at end of file diff --git a/examples/dsp/FilteringFunction_LMSPart/array.h b/examples/dsp/FilteringFunction_LMSPart/array.h new file mode 100644 index 00000000..9c4fe7c9 --- /dev/null +++ b/examples/dsp/FilteringFunction_LMSPart/array.h @@ -0,0 +1,31 @@ +// Array for FilteringFunctions LMSPart +#define TEST_LENGTH_SAMPLES 320 /* ???? */ +#define NUM_TAPS 29 +const float32_t firCoeffs32LP[NUM_TAPS] = { + -0.001822523074f, -0.001587929321f, 1.226008847e-18f, 0.003697750857f, 0.008075430058f, + 0.008530221879f, -4.273456581e-18f, -0.01739769801f, -0.03414586186f, -0.03335915506f, + 8.073562366e-18f, 0.06763084233f, 0.1522061825f, 0.2229246944f, 0.2504960895f, + 0.2229246944f, 0.1522061825f, 0.06763084233f, 8.073562366e-18f, -0.03335915506f, + -0.03414586186f, -0.01739769801f, -4.273456581e-18f, 0.008530221879f, 0.008075430058f, + 0.003697750857f, 1.226008847e-18f, -0.001587929321f, -0.001822523074f}; +// float32_t + float32_t expectoutput_f32_50Hz_200Hz[TEST_LENGTH_SAMPLES] = {0, 0.309016994374947, 0.587785252292473, 0.809016994374948, 0.951056516295154, 1, 0.951056516295154, 0.809016994374948, 0.587785252292473, 0.309016994374948, 1.22464679914735e-16, -0.309016994374947, -0.587785252292473, -0.809016994374947, -0.951056516295154, -1, -0.951056516295154, -0.809016994374947, -0.587785252292473, -0.309016994374948, -2.44929359829471e-16, 0.309016994374948, 0.587785252292473, 0.809016994374947, 0.951056516295154, 1, 0.951056516295154, 0.809016994374948, 0.587785252292473, 0.309016994374948, 3.67394039744206e-16, -0.309016994374947, -0.587785252292473, -0.809016994374948, -0.951056516295154, -1, -0.951056516295154, -0.809016994374948, -0.587785252292474, -0.309016994374948, -4.89858719658941e-16, 0.309016994374949, 0.587785252292474, 0.809016994374947, 0.951056516295153, 1, 0.951056516295154, 0.809016994374948, 0.587785252292472, 0.309016994374946, -1.16403343982657e-15, -0.309016994374945, -0.587785252292473, -0.809016994374948, -0.951056516295153, -1, -0.951056516295154, -0.809016994374947, -0.587785252292474, -0.309016994374950, -7.34788079488412e-16, 0.309016994374948, 0.587785252292473, 0.809016994374948, 0.951056516295153, 1, 0.951056516295153, 0.809016994374947, 0.587785252292471, 0.309016994374947, -2.69546091939735e-15, -0.309016994374945, -0.587785252292473, -0.809016994374946, -0.951056516295153, -1, -0.951056516295154, -0.809016994374947, -0.587785252292474, -0.309016994374947, -9.79717439317883e-16, 0.309016994374948, 0.587785252292475, 0.809016994374948, 0.951056516295154, 1, 0.951056516295154, 0.809016994374949, 0.587785252292474, 0.309016994374950, 1.10218211923262e-15, -0.309016994374948, -0.587785252292472, -0.809016994374948, -0.951056516295153, -1, -0.951056516295153, -0.809016994374947, -0.587785252292471, -0.309016994374947, 2.32806687965315e-15, 0.309016994374948, 0.587785252292469, 0.809016994374946, 0.951056516295153, 1, 0.951056516295153, 0.809016994374949, 0.587785252292474, 0.309016994374947, -2.20560219973841e-15, -0.309016994374951, -0.587785252292472, -0.809016994374948, -0.951056516295154, -1, -0.951056516295154, -0.809016994374947, -0.587785252292477, -0.309016994374951, -1.46957615897682e-15, 0.309016994374948, 0.587785252292475, 0.809016994374946, 0.951056516295153, 1, 0.951056516295153, 0.809016994374945, 0.587785252292474, 0.309016994374947, -1.96067283990894e-15, -0.309016994374951, -0.587785252292478, -0.809016994374948, -0.951056516295154, -1, -0.951056516295152, -0.809016994374947, -0.587785252292472, -0.309016994374944, 5.39092183879471e-15, 0.309016994374941, 0.587785252292469, 0.809016994374945, 0.951056516295153, 1, 0.951056516295155, 0.809016994374950, 0.587785252292475, 0.309016994374947, -1.71574348007947e-15, -0.309016994374944, -0.587785252292472, -0.809016994374947, -0.951056516295154, -1, -0.951056516295154, -0.809016994374948, -0.587785252292472, -0.309016994374944, -1.95943487863577e-15, 0.309016994374947, 0.587785252292474, 0.809016994374949, 0.951056516295155, 1, 0.951056516295153, 0.809016994374946, 0.587785252292469, 0.309016994374941, -1.47081412025000e-15, -0.309016994374951, -0.587785252292472, -0.809016994374947, -0.951056516295152, -1, -0.951056516295154, -0.809016994374948, -0.587785252292478, -0.309016994374951, -2.20436423846524e-15, 0.309016994374947, 0.587785252292474, 0.809016994374945, 0.951056516295153, 1, 0.951056516295153, 0.809016994374946, 0.587785252292475, 0.309016994374948, -1.22588476042053e-15, -0.309016994374950, -0.587785252292477, -0.809016994374947, -0.951056516295154, -1, -0.951056516295152, -0.809016994374944, -0.587785252292472, -0.309016994374945, 4.65613375930630e-15, 0.309016994374954, 0.587785252292474, 0.809016994374949, 0.951056516295151, 1, 0.951056516295155, 0.809016994374950, 0.587785252292475, 0.309016994374948, -9.80955400591059e-16, -0.309016994374950, -0.587785252292477, -0.809016994374943, -0.951056516295152, -1, -0.951056516295154, -0.809016994374948, -0.587785252292473, -0.309016994374945, 4.41120439947683e-15, 0.309016994374953, 0.587785252292480, 0.809016994374945, 0.951056516295153, 1, 0.951056516295153, 0.809016994374946, 0.587785252292470, 0.309016994374942, -7.84145339836259e-15, -0.309016994374957, -0.587785252292471, -0.809016994374947, -0.951056516295154, -1, -0.951056516295157, -0.809016994374952, -0.587785252292478, -0.309016994374952, -2.93915231795365e-15, 0.309016994374946, 0.587785252292474, 0.809016994374949, 0.951056516295155, 1, 0.951056516295156, 0.809016994374950, 0.587785252292476, 0.309016994374949, -4.91096680932118e-16, -0.309016994374950, -0.587785252292476, -0.809016994374951, -0.951056516295156, -1, -0.951056516295155, -0.809016994374948, -0.587785252292473, -0.309016994374945, 3.92134567981788e-15, 0.309016994374953, 0.587785252292479, 0.809016994374953, 0.951056516295157, 1, 0.951056516295154, 0.809016994374946, 0.587785252292470, 0.309016994374942, -7.35159467870365e-15, -0.309016994374956, -0.587785252292482, -0.809016994374955, -0.951056516295154, -1, -0.951056516295152, -0.809016994374944, -0.587785252292467, -0.309016994374939, 1.07818436775894e-14, 0.309016994374959, 0.587785252292462, 0.809016994374940, 0.951056516295150, 1, 0.951056516295156, 0.809016994374951, 0.587785252292476, 0.309016994374949, -1.23796127317672e-18, -0.309016994374936, -0.587785252292465, -0.809016994374942, -0.951056516295151, -1, -0.951056516295155, -0.809016994374949, -0.587785252292473, -0.309016994374946, 3.43148696015894e-15, 0.309016994374939, 0.587785252292467, 0.809016994374944, 0.951056516295152, 1, 0.951056516295154, 0.809016994374947, 0.587785252292471, 0.309016994374943, -6.86173595904471e-15, -0.309016994374942, -0.587785252292470, -0.809016994374946, -0.951056516295154, -1, -0.951056516295153, -0.809016994374945, -0.587785252292468, -0.309016994374939}; + float32_t error_ones[TEST_LENGTH_SAMPLES]; + float32_t testOutput_f32[TEST_LENGTH_SAMPLES],testOutput_f32_ref[TEST_LENGTH_SAMPLES]; + float32_t firStateF32_LMS[TEST_LENGTH_SAMPLES + NUM_TAPS - 1]={0}; + float32_t testInput_f32_50Hz_200Hz[TEST_LENGTH_SAMPLES] = {0, 1.26007351067010, 1.17557050458495, 0.221231742082474, -1.11022302462516e-16, 1.00000000000000, 1.90211303259031, 1.39680224666742, 4.44089209850063e-16, -0.642039521920206, -3.67394039744206e-16, 0.642039521920206, -1.22124532708767e-15, -1.39680224666742, -1.90211303259031, -1.00000000000000, -3.33066907387547e-16, -0.221231742082476, -1.17557050458495, -1.26007351067010, -1.22464679914735e-15, 1.26007351067010, 1.17557050458495, 0.221231742082475, 8.88178419700125e-16, 1.00000000000000, 1.90211303259031, 1.39680224666742, 1.33226762955019e-15, -0.642039521920206, -1.10218211923262e-15, 0.642039521920206, 1.55431223447522e-15, -1.39680224666743, -1.90211303259031, -0.999999999999995, -7.77156117237610e-16, -0.221231742082473, -1.17557050458495, -1.26007351067010, -2.44929359829471e-15, 1.26007351067010, 1.17557050458494, 0.221231742082476, -7.77156117237610e-16, 0.999999999999998, 1.90211303259031, 1.39680224666742, -4.88498130835069e-15, -0.642039521920206, 3.49210031947972e-15, 0.642039521920206, 2.55351295663786e-15, -1.39680224666742, -1.90211303259031, -0.999999999999996, -9.99200722162641e-16, -0.221231742082477, -1.17557050458494, -1.26007351067011, -3.67394039744206e-15, 1.26007351067010, 1.17557050458495, 0.221231742082472, -1.22124532708767e-15, 1.00000000000000, 1.90211303259031, 1.39680224666742, -1.09912079437891e-14, -0.642039521920206, 8.08638275819206e-15, 0.642039521920205, 3.55271367880050e-15, -1.39680224666741, -1.90211303259031, -0.999999999999997, -1.44328993201270e-15, -0.221231742082476, -1.17557050458494, -1.26007351067010, -4.89858719658941e-15, 1.26007351067010, 1.17557050458494, 0.221231742082472, 3.88578058618805e-15, 1.00000000000000, 1.90211303259031, 1.39680224666743, 4.44089209850063e-15, -0.642039521920207, -3.30654635769785e-15, 0.642039521920206, 4.55191440096314e-15, -1.39680224666742, -1.90211303259031, -0.999999999999998, 3.66373598126302e-15, -0.221231742082476, -1.17557050458495, -1.26007351067010, 1.16403343982657e-14, 1.26007351067010, 1.17557050458496, 0.221231742082482, -1.99840144432528e-15, 1.00000000000000, 1.90211303259031, 1.39680224666743, 5.44009282066327e-15, -0.642039521920206, 6.61680659921524e-15, 0.642039521920207, 5.55111512312578e-15, -1.39680224666742, -1.90211303259031, -0.999999999999984, -2.10942374678780e-15, -0.221231742082475, -1.17557050458493, -1.26007351067011, -7.34788079488412e-15, 1.26007351067010, 1.17557050458494, 0.221231742082483, -2.33146835171283e-15, 1.00000000000000, 1.90211303259031, 1.39680224666741, 6.32827124036339e-15, -0.642039521920206, 5.88201851972683e-15, 0.642039521920207, -2.22044604925031e-14, -1.39680224666742, -1.90211303259031, -0.999999999999985, 8.43769498715119e-15, -0.221231742082475, -1.17557050458495, -1.26007351067009, 2.69546091939735e-14, 1.26007351067009, 1.17557050458496, 0.221231742082484, -2.77555756156289e-15, 1, 1.90211303259030, 1.39680224666743, 7.32747196252603e-15, -0.642039521920206, 5.14723044023841e-15, 0.642039521920205, 7.54951656745106e-15, -1.39680224666742, -1.90211303259031, -0.999999999999986, -2.99760216648792e-15, -0.221231742082474, -1.17557050458495, -1.26007351067009, -9.79717439317883e-15, 1.26007351067010, 1.17557050458494, 0.221231742082465, 7.88258347483861e-15, 0.999999999999999, 1.90211303259031, 1.39680224666741, -2.04281036531029e-14, -0.642039521920204, 4.41244236075000e-15, 0.642039521920207, 8.43769498715119e-15, -1.39680224666742, -1.90211303259031, -1.00000000000002, -3.33066907387547e-15, -0.221231742082473, -1.17557050458493, -1.26007351067011, -1.10218211923262e-14, 1.26007351067010, 1.17557050458494, 0.221231742082485, -3.44169137633799e-15, 0.999999999999998, 1.90211303259031, 1.39680224666741, 9.32587340685132e-15, -0.642039521920206, 3.67765428126159e-15, 0.642039521920207, -1.93178806284777e-14, -1.39680224666742, -1.90211303259031, -0.999999999999988, 7.32747196252603e-15, -0.221231742082492, -1.17557050458495, -1.26007351067009, 2.32806687965315e-14, 1.26007351067012, 1.17557050458494, 0.221231742082467, -1.47659662275146e-14, 0.999999999999969, 1.90211303259030, 1.39680224666744, 1.02140518265514e-14, -0.642039521920206, 2.94286620177318e-15, 0.642039521920207, -1.83186799063151e-14, -1.39680224666739, -1.90211303259031, -1.00000000000002, -4.10782519111308e-15, -0.221231742082472, -1.17557050458495, -1.26007351067010, 2.20560219973841e-14, 1.26007351067011, 1.17557050458493, 0.221231742082486, -4.21884749357560e-15, 0.999999999999996, 1.90211303259031, 1.39680224666741, -1.75415237890775e-14, -0.642039521920204, 2.35243601950878e-14, 0.642039521920209, 1.15463194561016e-14, -1.39680224666742, -1.90211303259031, -0.999999999999990, -1.54321000422897e-14, -0.221231742082452, -1.17557050458493, -1.26007351067011, -1.46957615897682e-14, 1.26007351067010, 1.17557050458495, 0.221231742082468, 6.32827124036339e-15, 1.00000000000002, 1.90211303259030, 1.39680224666744, 1.23234755733392e-14, -0.642039521920207, 1.47329004279635e-15, 0.642039521920207, -1.62092561595273e-14, -1.39680224666744, -1.90211303259030, -1.00000000000002, -4.88498130835069e-15, -0.221231742082471, -1.17557050458495, -1.26007351067010, 1.96067283990894e-14, 1.26007351067011, 1.17557050458493, 0.221231742082450, 1.69864122767649e-14, 0.999999999999994, 1.90211303259031, 1.39680224666741, -1.54321000422897e-14, -0.642039521920205, 2.20547840361110e-14, 0.642039521920209, -4.39648317751562e-14, -1.39680224666747, -1.90211303259031, -0.999999999999992, 5.77315972805081e-15, -0.221231742082489, -1.17557050458496, -1.26007351067008, 5.39092183879471e-14, 1.26007351067013, 1.17557050458498, 0.221231742082507, -1.63202784619898e-14, 0.999999999999965, 1.90211303259030, 1.39680224666744, 1.43218770176645e-14, -0.642039521920207, 3.71388381953015e-18, 0.642039521920203, 4.31876756579186e-14, -1.39680224666739, -1.90211303259031, -1.00000000000002, -5.55111512312578e-15, -0.221231742082469, -1.17557050458495, -1.26007351067010, 1.71574348007947e-14, 1.26007351067008, 1.17557050458496, 0.221231742082489, -5.77315972805081e-15, 0.999999999999992, 1.90211303259031, 1.39680224666741, -1.34336985979644e-14, -0.642039521920205, 2.05852078771341e-14, 0.642039521920205, 1.54321000422897e-14, -1.39680224666741, -1.90211303259031, -0.999999999999994, 4.99600361081320e-15, -0.221231742082488, -1.17557050458496, -1.26007351067008}; + +//q31_t + q31_t expectoutput_q31_50Hz_200Hz[TEST_LENGTH_SAMPLES]; + q31_t error_ones_q31[TEST_LENGTH_SAMPLES]; + q31_t firStateq31_LMS[TEST_LENGTH_SAMPLES + NUM_TAPS - 1]; + q31_t testInput_q31_50Hz_200Hz[TEST_LENGTH_SAMPLES] = {0}, testOutput_q31[TEST_LENGTH_SAMPLES] = {0},testOutput_q31_ref[TEST_LENGTH_SAMPLES] = {0}; + q31_t firCoeffs32LP_q31[NUM_TAPS] = {0}; + +//q15_t + q15_t expectoutput_q15_50Hz_200Hz[TEST_LENGTH_SAMPLES]; + q15_t error_ones_q15[TEST_LENGTH_SAMPLES]; + q15_t firStateq15_LMS[TEST_LENGTH_SAMPLES + NUM_TAPS - 1]; + q15_t testInput_q15_50Hz_200Hz[TEST_LENGTH_SAMPLES] = {0}, testOutput_q15[TEST_LENGTH_SAMPLES] = {0},testOutput_q15_ref[TEST_LENGTH_SAMPLES] = {0}; + q15_t firCoeffs32LP_q15[NUM_TAPS] = {0}; + diff --git a/examples/dsp/FilteringFunction_LMSPart/lms.c b/examples/dsp/FilteringFunction_LMSPart/lms.c new file mode 100644 index 00000000..6cec08a2 --- /dev/null +++ b/examples/dsp/FilteringFunction_LMSPart/lms.c @@ -0,0 +1,663 @@ +#include "ref.h" + +void ref_lms_f32(const riscv_lms_instance_f32 *S, float32_t *pSrc, + float32_t *pRef, float32_t *pOut, float32_t *pErr, + uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *pStateCurnt; /* Points to the current sample of the state */ + float32_t mu = S->mu; /* Adaptive factor */ + uint32_t numTaps = + S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i, blkCnt; /* Loop counters */ + float32_t sum, e, d; /* accumulator, error, reference data sample */ + float32_t w = 0.0f; /* weight factor */ + + e = 0.0f; + d = 0.0f; + + /* S->pState points to state array which contains previous frame (numTaps - + * 1) samples */ + /* pStateCurnt points to the location where the new input data should be + * written */ + pStateCurnt = &(S->pState[numTaps - 1U]); + + blkCnt = blockSize; + + while (blkCnt > 0U) { + /* Copy the new input sample into the state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Set the accumulator to zero */ + sum = 0.0f; + + for (i = 0; i < numTaps; i++) { /* Perform the multiply-accumulate */ + sum += pState[i] * pCoeffs[i]; + } + + /* The result is stored in the destination buffer. */ + *pOut++ = sum; + + /* Compute and store error */ + d = *pRef++; + e = d - sum; + *pErr++ = e; + + /* Weighting factor for the LMS version */ + w = e * mu; + + for (i = 0; i < numTaps; i++) { /* Perform the multiply-accumulate */ + pCoeffs[i] += w * pState[i]; + } + + /* Advance state pointer by 1 for the next sample */ + pState++; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Processing is complete. Now copy the last numTaps - 1 samples to the + * start of the state buffer. This prepares the state buffer for the + * next function call. */ + for (i = 0; i < numTaps - 1; i++) { + S->pState[i] = pState[i]; + } +} + +void ref_lms_norm_f32(riscv_lms_norm_instance_f32 *S, float32_t *pSrc, + float32_t *pRef, float32_t *pOut, float32_t *pErr, + uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *pStateCurnt; /* Points to the current sample of the state */ + float32_t mu = S->mu; /* Adaptive factor */ + uint32_t numTaps = + S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i, blkCnt; /* Loop counters */ + float32_t energy; /* Energy of the input */ + float32_t sum, e, d; /* accumulator, error, reference data sample */ + float32_t w, x0, in; /* weight factor, temporary variable to hold input + sample and state */ + + /* Initializations of error, difference, Coefficient update */ + e = 0.0f; + d = 0.0f; + w = 0.0f; + + energy = S->energy; + x0 = S->x0; + + /* S->pState points to buffer which contains previous frame (numTaps - 1) + * samples */ + /* pStateCurnt points to the location where the new input data should be + * written */ + pStateCurnt = &(S->pState[numTaps - 1U]); + + for (blkCnt = blockSize; blkCnt > 0U; blkCnt--) { + /* Copy the new input sample into the state buffer */ + *pStateCurnt++ = *pSrc; + + /* Read the sample from input buffer */ + in = *pSrc++; + + /* Update the energy calculation */ + energy -= x0 * x0; + energy += in * in; + + /* Set the accumulator to zero */ + sum = 0.0f; + + for (i = 0; i < numTaps; i++) { /* Perform the multiply-accumulate */ + sum += pState[i] * pCoeffs[i]; + } + + /* The result in the accumulator is stored in the destination buffer. */ + *pOut++ = sum; + + /* Compute and store error */ + d = *pRef++; + e = d - sum; + *pErr++ = e; + + /* Calculation of Weighting factor for updating filter coefficients */ + /* epsilon value 0.000000119209289f */ + w = e * mu / (energy + 0.000000119209289f); + + for (i = 0; i < numTaps; i++) { + /* Perform the multiply-accumulate */ + pCoeffs[i] += w * pState[i]; + } + + x0 = *pState; + + /* Advance state pointer by 1 for the next sample */ + pState++; + } + + S->energy = energy; + S->x0 = x0; + + /* Processing is complete. Now copy the last numTaps - 1 samples to the + * start of the state buffer. This prepares the state buffer for the + * next function call. */ + for (i = 0; i < numTaps - 1; i++) { + S->pState[i] = pState[i]; + } +} + +void ref_lms_q31(const riscv_lms_instance_q31 *S, q31_t *pSrc, q31_t *pRef, + q31_t *pOut, q31_t *pErr, uint32_t blockSize) +{ + q31_t *pState = S->pState; /* State pointer */ + uint32_t numTaps = + S->numTaps; /* Number of filter coefficients in the filter */ + q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *pStateCurnt; /* Points to the current sample of the state */ + q31_t mu = S->mu; /* Adaptive factor */ + q31_t *px; /* Temporary pointer for state */ + q31_t *pb; /* Temporary pointer for coefficient buffer */ + uint32_t tapCnt, blkCnt; /* Loop counters */ + q63_t acc; /* Accumulator */ + q31_t e = 0; /* error of data sample */ + q31_t alpha; /* Intermediate constant for taps update */ + q31_t coef; /* Temporary variable for coef */ + q31_t acc_l, acc_h; /* temporary input */ + uint32_t uShift = (uint32_t)S->postShift + 1; + uint32_t lShift = 32U - uShift; /* Shift to be applied to the output */ + + /* S->pState points to buffer which contains previous frame (numTaps - 1) + * samples */ + /* pStateCurnt points to the location where the new input data should be + * written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + + for (blkCnt = blockSize; blkCnt > 0U; blkCnt--) { + /* Copy the new input sample into the state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Initialize pState pointer */ + px = pState; + + /* Initialize pCoeffs pointer */ + pb = pCoeffs; + + /* Set the accumulator to zero */ + acc = 0; + + /* Loop over numTaps number of values */ + tapCnt = numTaps; + + while (tapCnt > 0U) { + /* Perform the multiply-accumulate */ + acc += (q63_t)(*px++) * (*pb++); + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Converting the result to 1.31 format */ + /* Store the result from accumulator into the destination buffer. */ + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + acc = (uint32_t)acc_l >> lShift | acc_h << uShift; + + *pOut++ = (q31_t)acc; + + /* Compute and store error */ + e = *pRef++ - (q31_t)acc; + + *pErr++ = (q31_t)e; + + /* Weighting factor for the LMS version */ + alpha = (q31_t)(((q63_t)e * mu) >> 31); + + /* Initialize pState pointer */ + /* Advance state pointer by 1 for the next sample */ + px = pState++; + + /* Initialize pCoeffs pointer */ + pb = pCoeffs; + + /* Loop over numTaps number of values */ + tapCnt = numTaps; + + while (tapCnt > 0U) { + /* Perform the multiply-accumulate */ + coef = (q31_t)(((q63_t)alpha * (*px++)) >> 32); + *pb = ref_sat_q31((q63_t)*pb + (coef << 1)); + pb++; + + /* Decrement the loop counter */ + tapCnt--; + } + } + + /* Processing is complete. Now copy the last numTaps - 1 samples to the + start of the state buffer. This prepares the state buffer for the + next function call. */ + + /* Points to the start of the pState buffer */ + pStateCurnt = S->pState; + + /* Copy (numTaps - 1U) samples */ + tapCnt = numTaps - 1; + + /* Copy the data */ + while (tapCnt > 0U) { + *pStateCurnt++ = *pState++; + + /* Decrement the loop counter */ + tapCnt--; + } +} + +void ref_lms_norm_q31(riscv_lms_norm_instance_q31 *S, q31_t *pSrc, q31_t *pRef, + q31_t *pOut, q31_t *pErr, uint32_t blockSize) +{ + q31_t *pState = S->pState; /* State pointer */ + q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *pStateCurnt; /* Points to the current sample of the state */ + q31_t *px, *pb; /* Temporary pointers for state and coefficient buffers */ + q31_t mu = S->mu; /* Adaptive factor */ + uint32_t numTaps = + S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t tapCnt, blkCnt; /* Loop counters */ + q63_t energy; /* Energy of the input */ + q63_t acc; /* Accumulator */ + q31_t e = 0, d = 0; /* error, reference data sample */ + q31_t w = 0, in; /* weight factor and state */ + q31_t x0; /* temporary variable to hold input sample */ + q63_t errorXmu; /* Temporary variables to store error and mu product and + reciprocal of energy */ + q31_t coef; /* Temporary variable for coef */ + q31_t acc_l, acc_h; /* temporary input */ + uint32_t uShift = ((uint32_t)S->postShift + 1U); + uint32_t lShift = 32U - uShift; /* Shift to be applied to the output */ + + energy = S->energy; + x0 = S->x0; + + /* S->pState points to buffer which contains previous frame (numTaps - 1) + * samples */ + /* pStateCurnt points to the location where the new input data should be + * written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + + for (blkCnt = blockSize; blkCnt > 0U; blkCnt--) { + + /* Copy the new input sample into the state buffer */ + *pStateCurnt++ = *pSrc; + + /* Initialize pState pointer */ + px = pState; + + /* Initialize pCoeffs pointer */ + pb = pCoeffs; + + /* Read the sample from input buffer */ + in = *pSrc++; + + /* Update the energy calculation */ + energy = + (q31_t)((((q63_t)energy << 32) - (((q63_t)x0 * x0) << 1)) >> 32) & + 0xffffffff; + energy = + (q31_t)(((((q63_t)in * in) << 1) + ((q63_t)energy << 32)) >> 32) & + 0xffffffff; + + /* Set the accumulator to zero */ + acc = 0; + + /* Loop over numTaps number of values */ + tapCnt = numTaps; + + while (tapCnt > 0U) { + /* Perform the multiply-accumulate */ + acc += ((q63_t)(*px++)) * (*pb++); + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Converting the result to 1.31 format */ + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + acc = (uint32_t)acc_l >> lShift | acc_h << uShift; + + /* Store the result from accumulator into the destination buffer. */ + *pOut++ = (q31_t)acc; + + /* Compute and store error */ + d = *pRef++; + e = d - (q31_t)acc; + *pErr++ = e; + + /* Calculation of product of (e * mu) */ + errorXmu = (q63_t)e * mu; + + /* Weighting factor for the normalized version */ + w = ref_sat_q31(errorXmu / (energy + DELTA_Q31)); + + /* Initialize pState pointer */ + px = pState; + + /* Initialize coeff pointer */ + pb = pCoeffs; + + /* Loop over numTaps number of values */ + tapCnt = numTaps; + + while (tapCnt > 0U) { + /* Perform the multiply-accumulate */ + /* coef is in 2.30 format */ + coef = (q31_t)(((q63_t)w * (*px++)) >> 32); + /* get coef in 1.31 format by left shifting */ + *pb = ref_sat_q31((q63_t)*pb + (coef << 1U)); + /* update coefficient buffer to next coefficient */ + pb++; + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Read the sample from state buffer */ + x0 = *pState; + + /* Advance state pointer by 1 for the next sample */ + pState++; + } + + /* Save energy and x0 values for the next frame */ + S->energy = (q31_t)energy; + S->x0 = x0; + + /* Processing is complete. Now copy the last numTaps - 1 samples to the + start of the state buffer. This prepares the state buffer for the + next function call. */ + + /* Points to the start of the pState buffer */ + pStateCurnt = S->pState; + + /* Loop for (numTaps - 1U) samples copy */ + tapCnt = numTaps - 1; + + /* Copy the remaining q31_t data */ + while (tapCnt > 0U) { + *pStateCurnt++ = *pState++; + + /* Decrement the loop counter */ + tapCnt--; + } +} + +void ref_lms_q15(const riscv_lms_instance_q15 *S, q15_t *pSrc, q15_t *pRef, + q15_t *pOut, q15_t *pErr, uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + uint32_t numTaps = + S->numTaps; /* Number of filter coefficients in the filter */ + q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCurnt; /* Points to the current sample of the state */ + q15_t mu = S->mu; /* Adaptive factor */ + q15_t *px; /* Temporary pointer for state */ + q15_t *pb; /* Temporary pointer for coefficient buffer */ + uint32_t tapCnt, blkCnt; /* Loop counters */ + q63_t acc; /* Accumulator */ + q15_t e = 0; /* error of data sample */ + q15_t alpha; /* Intermediate constant for taps update */ + q31_t coef; /* Teporary variable for coefficient */ + q31_t acc_l, acc_h; + int32_t lShift = 15 - (int32_t)S->postShift; /* Post shift */ + int32_t uShift = 32 - lShift; + + /* S->pState points to buffer which contains previous frame (numTaps - 1) + * samples */ + /* pStateCurnt points to the location where the new input data should be + * written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + + for (blkCnt = blockSize; blkCnt > 0U; blkCnt--) { + /* Copy the new input sample into the state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Initialize pState pointer */ + px = pState; + + /* Initialize pCoeffs pointer */ + pb = pCoeffs; + + /* Set the accumulator to zero */ + acc = 0; + + /* Loop over numTaps number of values */ + tapCnt = numTaps; + + while (tapCnt > 0U) { + /* Perform the multiply-accumulate */ + acc += (q63_t)((q31_t)(*px++) * (*pb++)); + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + /* Apply shift for lower part of acc and upper part of acc */ + acc = (uint32_t)acc_l >> lShift | acc_h << uShift; + + /* Converting the result to 1.15 format and saturate the output */ + acc = ref_sat_q15(acc); + + /* Store the result from accumulator into the destination buffer. */ + *pOut++ = (q15_t)acc; + + /* Compute and store error */ + e = *pRef++ - (q15_t)acc; + + *pErr++ = (q15_t)e; + + /* Compute alpha i.e. intermediate constant for taps update */ + alpha = (q15_t)(((q31_t)e * mu) >> 15); + + /* Initialize pState pointer */ + /* Advance state pointer by 1 for the next sample */ + px = pState++; + + /* Initialize pCoeffs pointer */ + pb = pCoeffs; + + /* Loop over numTaps number of values */ + tapCnt = numTaps; + + while (tapCnt > 0U) { + /* Perform the multiply-accumulate */ + coef = (q31_t)*pb + (((q31_t)alpha * (*px++)) >> 15); + *pb++ = (q15_t)ref_sat_q15(coef); + + /* Decrement the loop counter */ + tapCnt--; + } + } + + /* Processing is complete. Now copy the last numTaps - 1 samples to the + start of the state buffer. This prepares the state buffer for the + next function call. */ + + /* Points to the start of the pState buffer */ + pStateCurnt = S->pState; + + /* Copy (numTaps - 1U) samples */ + tapCnt = numTaps - 1; + + /* Copy the data */ + while (tapCnt > 0U) { + *pStateCurnt++ = *pState++; + + /* Decrement the loop counter */ + tapCnt--; + } +} + +void ref_lms_norm_q15(riscv_lms_norm_instance_q15 *S, q15_t *pSrc, q15_t *pRef, + q15_t *pOut, q15_t *pErr, uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCurnt; /* Points to the current sample of the state */ + q15_t *px, *pb; /* Temporary pointers for state and coefficient buffers */ + q15_t mu = S->mu; /* Adaptive factor */ + uint32_t numTaps = + S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t tapCnt, blkCnt; /* Loop counters */ + q31_t energy; /* Energy of the input */ + q63_t acc; /* Accumulator */ + q15_t e = 0, d = 0; /* error, reference data sample */ + q15_t w = 0, in; /* weight factor and state */ + q15_t x0; /* temporary variable to hold input sample */ + q15_t errorXmu, oneByEnergy; /* Temporary variables to store error and mu + product and reciprocal of energy */ + // q31_t errorXmu; /* Temporary variables to store + // error and mu product and reciprocal of energy */ + q15_t postShift; /* Post shift to be applied to weight after reciprocal + calculation */ + q31_t coef; /* Teporary variable for coefficient */ + q31_t acc_l, acc_h; + int32_t lShift = 15 - (int32_t)S->postShift; /* Post shift */ + int32_t uShift = 32 - lShift; + + energy = S->energy; + x0 = S->x0; + + /* S->pState points to buffer which contains previous frame (numTaps - 1) + * samples */ + /* pStateCurnt points to the location where the new input data should be + * written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + + for (blkCnt = blockSize; blkCnt > 0U; blkCnt--) { + /* Copy the new input sample into the state buffer */ + *pStateCurnt++ = *pSrc; + + /* Initialize pState pointer */ + px = pState; + + /* Initialize pCoeffs pointer */ + pb = pCoeffs; + + /* Read the sample from input buffer */ + in = *pSrc++; + + /* Update the energy calculation */ + energy -= (((q31_t)x0 * x0) >> 15) & 0xffff; + energy += (((q31_t)in * in) >> 15) & 0xffff; + + /* Set the accumulator to zero */ + acc = 0; + + /* Loop over numTaps number of values */ + tapCnt = numTaps; + + while (tapCnt > 0U) { + /* Perform the multiply-accumulate */ + acc += (q31_t)*px++ * (*pb++); + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + /* Apply shift for lower part of acc and upper part of acc */ + acc = (uint32_t)acc_l >> lShift | acc_h << uShift; + + /* Converting the result to 1.15 format and saturate the output */ + acc = ref_sat_q15(acc); + + /* Store the result from accumulator into the destination buffer. */ + *pOut++ = (q15_t)acc; + + /* Compute and store error */ + d = *pRef++; + e = d - (q15_t)acc; + *pErr++ = e; + + + /* Calculation of 1/energy */ + postShift = riscv_recip_q15((q15_t)energy + DELTA_Q15, &oneByEnergy, + S->recipTable); + + /* Calculation of e * mu value */ + errorXmu = (q15_t)(((q31_t)e * mu) >> 15); + + /* Calculation of (e * mu) * (1/energy) value */ + acc = (((q31_t)errorXmu * oneByEnergy) >> (15 - postShift)); + + /* Weighting factor for the normalized version */ + w = ref_sat_q15((q31_t)acc); + + /* Initialize pState pointer */ + px = pState; + + /* Initialize coeff pointer */ + pb = pCoeffs; + + /* Loop over numTaps number of values */ + tapCnt = numTaps; + + while (tapCnt > 0U) { + /* Perform the multiply-accumulate */ + coef = *pb + (((q31_t)w * (*px++)) >> 15); + *pb++ = ref_sat_q15(coef); + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Read the sample from state buffer */ + x0 = *pState; + + /* Advance state pointer by 1 for the next sample */ + pState = pState + 1U; + } + + /* Save energy and x0 values for the next frame */ + S->energy = (q15_t)energy; + S->x0 = x0; + + /* Processing is complete. Now copy the last numTaps - 1 samples to the + satrt of the state buffer. This prepares the state buffer for the + next function call. */ + + /* Points to the start of the pState buffer */ + pStateCurnt = S->pState; + + /* copy (numTaps - 1U) data */ + tapCnt = numTaps - 1; + + /* copy data */ + while (tapCnt > 0U) { + *pStateCurnt++ = *pState++; + + /* Decrement the loop counter */ + tapCnt--; + } +} diff --git a/examples/dsp/FilteringFunction_LMSPart/main.c b/examples/dsp/FilteringFunction_LMSPart/main.c new file mode 100644 index 00000000..9dcd4284 --- /dev/null +++ b/examples/dsp/FilteringFunction_LMSPart/main.c @@ -0,0 +1,168 @@ +// +// Created by lujun on 19-6-28. +// +// This contains fir, iir and lms filters +// each one has it's own function. +// All function can be found in main function. +// If you don't want to use it, then comment it. +// +// This part only tests result after 50 dots.If you want to test results' all +// dots, please define WITH_FRONT +// +// If there are too much numbers which makes it hard to read,in VScode you can +// press alt and z can shrimp them to one line +// +// You MUST be careful about overflow. +#include "riscv_math.h" +#include "array.h" +#include +#include "../common.h" + +#include "../HelperFunctions/math_helper.c" +#include "../HelperFunctions/ref_helper.c" + +#include +#define DELTAF32 (0.05f) +#define DELTAQ31 (63) +#define DELTAQ15 (1) +#define DELTAQ7 (1) +#define SNR_THRESHOLD_F32 (80.0f) + +int test_flag_error = 0; + +// #define WITH_FRONT + +//*************************************************************************************** +// lms Filters +//*************************************************************************************** +static void riscv_fir_f32_LMS_lp(void) +{ + uint32_t i; + /* clang-format off */ + riscv_lms_instance_f32 S; + /* clang-format on */ + for (i = 0; i < 320; i++) + error_ones[i] = 1; + riscv_lms_init_f32(&S, NUM_TAPS, &firCoeffs32LP[0], &firStateF32_LMS[0], 0.00000001f, TEST_LENGTH_SAMPLES); + BENCH_START(riscv_lms_f32); + riscv_lms_f32(&S, testInput_f32_50Hz_200Hz, expectoutput_f32_50Hz_200Hz, testOutput_f32, &error_ones[0], TEST_LENGTH_SAMPLES); + BENCH_END(riscv_lms_f32); + riscv_lms_init_f32(&S, NUM_TAPS, &firCoeffs32LP[0], &firStateF32_LMS[0], 0.00000001f, TEST_LENGTH_SAMPLES); + ref_lms_f32(&S, testInput_f32_50Hz_200Hz, expectoutput_f32_50Hz_200Hz, testOutput_f32_ref, &error_ones[0], TEST_LENGTH_SAMPLES); +#ifndef WITH_FRONT + float snr = riscv_snr_f32(&testOutput_f32_ref[50], &testOutput_f32[50], 269); + + if (snr < SNR_THRESHOLD_F32) { + BENCH_ERROR(riscv_lms_f32); + printf("f32 lms failed with snr:%f\n", snr); + test_flag_error = 1; + } + BENCH_STATUS(riscv_lms_f32); +#else + float snr = + riscv_snr_f32(&testOutput_ref[0], &testOutput[0], TEST_LENGTH_SAMPLES); + + if (snr < SNR_THRESHOLD_F32) { + BENCH_ERROR(riscv_lms_f32); + printf("f32 lms failed with snr:%f\n", snr); + test_flag_error = 1; + } + BENCH_STATUS(riscv_lms_f32); +#endif +} +static void riscv_fir_q31_LMS_lp(void) +{ + uint32_t i; + /* clang-format off */ + riscv_lms_instance_q31 S; + /* clang-format on */ + for (i = 0; i < TEST_LENGTH_SAMPLES; i++) + error_ones_q31[i] = 1; + riscv_float_to_q31(testInput_f32_50Hz_200Hz, testInput_q31_50Hz_200Hz, TEST_LENGTH_SAMPLES); + riscv_float_to_q31(expectoutput_f32_50Hz_200Hz, expectoutput_q31_50Hz_200Hz, TEST_LENGTH_SAMPLES); + riscv_float_to_q31(firCoeffs32LP, firCoeffs32LP_q31, NUM_TAPS); + riscv_lms_init_q31(&S, NUM_TAPS, &firCoeffs32LP_q31[0], &firStateq31_LMS[0], 215, TEST_LENGTH_SAMPLES, 1); + BENCH_START(riscv_lms_q31); + riscv_lms_q31(&S, testInput_q31_50Hz_200Hz, expectoutput_q31_50Hz_200Hz, testOutput_q31, error_ones_q31, TEST_LENGTH_SAMPLES); + BENCH_END(riscv_lms_q31); + riscv_lms_init_q31(&S, NUM_TAPS, &firCoeffs32LP_q31[0], &firStateq31_LMS[0], 215, TEST_LENGTH_SAMPLES, 1); + ref_lms_q31(&S, testInput_q31_50Hz_200Hz, expectoutput_q31_50Hz_200Hz, testOutput_q31_ref, error_ones_q31, TEST_LENGTH_SAMPLES); + riscv_q31_to_float(testOutput_q31, testOutput_f32, TEST_LENGTH_SAMPLES); + riscv_q31_to_float(testOutput_q31_ref, testOutput_f32_ref, TEST_LENGTH_SAMPLES); +#ifndef WITH_FRONT + float snr = riscv_snr_f32(&testOutput_f32_ref[50], &testOutput_f32[50], 269); + + if (snr < SNR_THRESHOLD_F32) { + BENCH_ERROR(riscv_lms_q31); + printf("q31 lms failed with snr:%f\n", snr); + test_flag_error = 1; + } + BENCH_STATUS(riscv_lms_q31); +#else + float snr = riscv_snr_f32(&testOutput_f32_ref[0], &testOutput_f32[0], + TEST_LENGTH_SAMPLES); + + if (snr < SNR_THRESHOLD_F32) { + BENCH_ERROR(riscv_lms_q31); + printf("q31 lms failed with snr:%f\n", snr); + test_flag_error = 1; + } + BENCH_STATUS(riscv_lms_q31); +#endif +} +static void riscv_fir_q15_LMS_lp(void) +{ + uint32_t i; + /* clang-format off */ + riscv_lms_instance_q15 S; + /* clang-format on */ + for (i = 0; i < TEST_LENGTH_SAMPLES; i++) + error_ones_q15[i] = 1; + riscv_float_to_q15(testInput_f32_50Hz_200Hz, testInput_q15_50Hz_200Hz, TEST_LENGTH_SAMPLES); + riscv_float_to_q15(expectoutput_f32_50Hz_200Hz, expectoutput_q15_50Hz_200Hz, TEST_LENGTH_SAMPLES); + riscv_float_to_q15(firCoeffs32LP, firCoeffs32LP_q15, NUM_TAPS); + riscv_lms_init_q15(&S, NUM_TAPS, &firCoeffs32LP_q15[0], &firStateq15_LMS[0], 0, TEST_LENGTH_SAMPLES, 1); + BENCH_START(riscv_lms_q15); + riscv_lms_q15(&S, testInput_q15_50Hz_200Hz, expectoutput_q15_50Hz_200Hz, testOutput_q15, error_ones_q15, TEST_LENGTH_SAMPLES); + BENCH_END(riscv_lms_q15); + riscv_lms_init_q15(&S, NUM_TAPS, &firCoeffs32LP_q15[0], &firStateq15_LMS[0], 0, TEST_LENGTH_SAMPLES, 1); + ref_lms_q15(&S, testInput_q15_50Hz_200Hz, expectoutput_q15_50Hz_200Hz, testOutput_q15_ref, error_ones_q15, TEST_LENGTH_SAMPLES); + riscv_q15_to_float(testOutput_q15, testOutput_f32, TEST_LENGTH_SAMPLES); + riscv_q15_to_float(testOutput_q15_ref, testOutput_f32_ref, TEST_LENGTH_SAMPLES); +#ifndef WITH_FRONT + float snr = riscv_snr_f32(&testOutput_f32_ref[50], &testOutput_f32[50], 269); + + if (snr < SNR_THRESHOLD_F32) { + BENCH_ERROR(riscv_lms_q15); + printf("q15 lms failed with snr:%f\n", snr); + test_flag_error = 1; + } + BENCH_STATUS(riscv_lms_q15); +#else + float snr = riscv_snr_f32(&testOutput_f32_ref[0], &testOutput_f32[0], + TEST_LENGTH_SAMPLES); + + if (snr < SNR_THRESHOLD_F32) { + BENCH_ERROR(riscv_lms_q15); + printf("q15 lms failed with snr:%f\n", snr); + test_flag_error = 1; + } + BENCH_STATUS(riscv_lms_q15); +#endif +} + +int main() +{ + BENCH_INIT; + riscv_fir_f32_LMS_lp(); + riscv_fir_q31_LMS_lp(); + riscv_fir_q15_LMS_lp(); + BENCH_FINISH; + if (test_flag_error) { + printf("test error apprears, please recheck.\n"); + return 1; + } else { + printf("all test are passed. Well done!\n"); + } + return 0; +} diff --git a/examples/dsp/FilteringFunction_NLMSPart/CMakeLists.txt b/examples/dsp/FilteringFunction_NLMSPart/CMakeLists.txt new file mode 100644 index 00000000..687f3402 --- /dev/null +++ b/examples/dsp/FilteringFunction_NLMSPart/CMakeLists.txt @@ -0,0 +1,5 @@ +set(TARGET_REQUIRED_PRIVATE_INCLUDE ${CMAKE_CURRENT_SOURCE_DIR} ${CMAKE_CURRENT_SOURCE_DIR}/..) +set(TARGET_REQUIRED_SRCS lms.c) +set(TARGET_REQUIRED_LIBS nmsis) +set(mains main.c) +generate_bin() \ No newline at end of file diff --git a/examples/dsp/FilteringFunction_NLMSPart/array.h b/examples/dsp/FilteringFunction_NLMSPart/array.h new file mode 100644 index 00000000..37ffa2de --- /dev/null +++ b/examples/dsp/FilteringFunction_NLMSPart/array.h @@ -0,0 +1,31 @@ +// Array for FilteringFunctions NLMSPart +#define TEST_LENGTH_SAMPLES 320 /* ???? */ +#define NUM_TAPS 29 +const float32_t firCoeffs32LP[NUM_TAPS] = { + -0.001822523074f, -0.001587929321f, 1.226008847e-18f, 0.003697750857f, 0.008075430058f, + 0.008530221879f, -4.273456581e-18f, -0.01739769801f, -0.03414586186f, -0.03335915506f, + 8.073562366e-18f, 0.06763084233f, 0.1522061825f, 0.2229246944f, 0.2504960895f, + 0.2229246944f, 0.1522061825f, 0.06763084233f, 8.073562366e-18f, -0.03335915506f, + -0.03414586186f, -0.01739769801f, -4.273456581e-18f, 0.008530221879f, 0.008075430058f, + 0.003697750857f, 1.226008847e-18f, -0.001587929321f, -0.001822523074f}; +// float32_t + float32_t expectoutput_f32_50Hz_200Hz[TEST_LENGTH_SAMPLES] = {0, 0.309016994374947, 0.587785252292473, 0.809016994374948, 0.951056516295154, 1, 0.951056516295154, 0.809016994374948, 0.587785252292473, 0.309016994374948, 1.22464679914735e-16, -0.309016994374947, -0.587785252292473, -0.809016994374947, -0.951056516295154, -1, -0.951056516295154, -0.809016994374947, -0.587785252292473, -0.309016994374948, -2.44929359829471e-16, 0.309016994374948, 0.587785252292473, 0.809016994374947, 0.951056516295154, 1, 0.951056516295154, 0.809016994374948, 0.587785252292473, 0.309016994374948, 3.67394039744206e-16, -0.309016994374947, -0.587785252292473, -0.809016994374948, -0.951056516295154, -1, -0.951056516295154, -0.809016994374948, -0.587785252292474, -0.309016994374948, -4.89858719658941e-16, 0.309016994374949, 0.587785252292474, 0.809016994374947, 0.951056516295153, 1, 0.951056516295154, 0.809016994374948, 0.587785252292472, 0.309016994374946, -1.16403343982657e-15, -0.309016994374945, -0.587785252292473, -0.809016994374948, -0.951056516295153, -1, -0.951056516295154, -0.809016994374947, -0.587785252292474, -0.309016994374950, -7.34788079488412e-16, 0.309016994374948, 0.587785252292473, 0.809016994374948, 0.951056516295153, 1, 0.951056516295153, 0.809016994374947, 0.587785252292471, 0.309016994374947, -2.69546091939735e-15, -0.309016994374945, -0.587785252292473, -0.809016994374946, -0.951056516295153, -1, -0.951056516295154, -0.809016994374947, -0.587785252292474, -0.309016994374947, -9.79717439317883e-16, 0.309016994374948, 0.587785252292475, 0.809016994374948, 0.951056516295154, 1, 0.951056516295154, 0.809016994374949, 0.587785252292474, 0.309016994374950, 1.10218211923262e-15, -0.309016994374948, -0.587785252292472, -0.809016994374948, -0.951056516295153, -1, -0.951056516295153, -0.809016994374947, -0.587785252292471, -0.309016994374947, 2.32806687965315e-15, 0.309016994374948, 0.587785252292469, 0.809016994374946, 0.951056516295153, 1, 0.951056516295153, 0.809016994374949, 0.587785252292474, 0.309016994374947, -2.20560219973841e-15, -0.309016994374951, -0.587785252292472, -0.809016994374948, -0.951056516295154, -1, -0.951056516295154, -0.809016994374947, -0.587785252292477, -0.309016994374951, -1.46957615897682e-15, 0.309016994374948, 0.587785252292475, 0.809016994374946, 0.951056516295153, 1, 0.951056516295153, 0.809016994374945, 0.587785252292474, 0.309016994374947, -1.96067283990894e-15, -0.309016994374951, -0.587785252292478, -0.809016994374948, -0.951056516295154, -1, -0.951056516295152, -0.809016994374947, -0.587785252292472, -0.309016994374944, 5.39092183879471e-15, 0.309016994374941, 0.587785252292469, 0.809016994374945, 0.951056516295153, 1, 0.951056516295155, 0.809016994374950, 0.587785252292475, 0.309016994374947, -1.71574348007947e-15, -0.309016994374944, -0.587785252292472, -0.809016994374947, -0.951056516295154, -1, -0.951056516295154, -0.809016994374948, -0.587785252292472, -0.309016994374944, -1.95943487863577e-15, 0.309016994374947, 0.587785252292474, 0.809016994374949, 0.951056516295155, 1, 0.951056516295153, 0.809016994374946, 0.587785252292469, 0.309016994374941, -1.47081412025000e-15, -0.309016994374951, -0.587785252292472, -0.809016994374947, -0.951056516295152, -1, -0.951056516295154, -0.809016994374948, -0.587785252292478, -0.309016994374951, -2.20436423846524e-15, 0.309016994374947, 0.587785252292474, 0.809016994374945, 0.951056516295153, 1, 0.951056516295153, 0.809016994374946, 0.587785252292475, 0.309016994374948, -1.22588476042053e-15, -0.309016994374950, -0.587785252292477, -0.809016994374947, -0.951056516295154, -1, -0.951056516295152, -0.809016994374944, -0.587785252292472, -0.309016994374945, 4.65613375930630e-15, 0.309016994374954, 0.587785252292474, 0.809016994374949, 0.951056516295151, 1, 0.951056516295155, 0.809016994374950, 0.587785252292475, 0.309016994374948, -9.80955400591059e-16, -0.309016994374950, -0.587785252292477, -0.809016994374943, -0.951056516295152, -1, -0.951056516295154, -0.809016994374948, -0.587785252292473, -0.309016994374945, 4.41120439947683e-15, 0.309016994374953, 0.587785252292480, 0.809016994374945, 0.951056516295153, 1, 0.951056516295153, 0.809016994374946, 0.587785252292470, 0.309016994374942, -7.84145339836259e-15, -0.309016994374957, -0.587785252292471, -0.809016994374947, -0.951056516295154, -1, -0.951056516295157, -0.809016994374952, -0.587785252292478, -0.309016994374952, -2.93915231795365e-15, 0.309016994374946, 0.587785252292474, 0.809016994374949, 0.951056516295155, 1, 0.951056516295156, 0.809016994374950, 0.587785252292476, 0.309016994374949, -4.91096680932118e-16, -0.309016994374950, -0.587785252292476, -0.809016994374951, -0.951056516295156, -1, -0.951056516295155, -0.809016994374948, -0.587785252292473, -0.309016994374945, 3.92134567981788e-15, 0.309016994374953, 0.587785252292479, 0.809016994374953, 0.951056516295157, 1, 0.951056516295154, 0.809016994374946, 0.587785252292470, 0.309016994374942, -7.35159467870365e-15, -0.309016994374956, -0.587785252292482, -0.809016994374955, -0.951056516295154, -1, -0.951056516295152, -0.809016994374944, -0.587785252292467, -0.309016994374939, 1.07818436775894e-14, 0.309016994374959, 0.587785252292462, 0.809016994374940, 0.951056516295150, 1, 0.951056516295156, 0.809016994374951, 0.587785252292476, 0.309016994374949, -1.23796127317672e-18, -0.309016994374936, -0.587785252292465, -0.809016994374942, -0.951056516295151, -1, -0.951056516295155, -0.809016994374949, -0.587785252292473, -0.309016994374946, 3.43148696015894e-15, 0.309016994374939, 0.587785252292467, 0.809016994374944, 0.951056516295152, 1, 0.951056516295154, 0.809016994374947, 0.587785252292471, 0.309016994374943, -6.86173595904471e-15, -0.309016994374942, -0.587785252292470, -0.809016994374946, -0.951056516295154, -1, -0.951056516295153, -0.809016994374945, -0.587785252292468, -0.309016994374939}; + float32_t error_ones[TEST_LENGTH_SAMPLES]; + float32_t testOutput_f32[TEST_LENGTH_SAMPLES],testOutput_f32_ref[TEST_LENGTH_SAMPLES]; + float32_t firStateF32_LMS[TEST_LENGTH_SAMPLES + NUM_TAPS - 1]={0}; + float32_t testInput_f32_50Hz_200Hz[TEST_LENGTH_SAMPLES] = {0, 1.26007351067010, 1.17557050458495, 0.221231742082474, -1.11022302462516e-16, 1.00000000000000, 1.90211303259031, 1.39680224666742, 4.44089209850063e-16, -0.642039521920206, -3.67394039744206e-16, 0.642039521920206, -1.22124532708767e-15, -1.39680224666742, -1.90211303259031, -1.00000000000000, -3.33066907387547e-16, -0.221231742082476, -1.17557050458495, -1.26007351067010, -1.22464679914735e-15, 1.26007351067010, 1.17557050458495, 0.221231742082475, 8.88178419700125e-16, 1.00000000000000, 1.90211303259031, 1.39680224666742, 1.33226762955019e-15, -0.642039521920206, -1.10218211923262e-15, 0.642039521920206, 1.55431223447522e-15, -1.39680224666743, -1.90211303259031, -0.999999999999995, -7.77156117237610e-16, -0.221231742082473, -1.17557050458495, -1.26007351067010, -2.44929359829471e-15, 1.26007351067010, 1.17557050458494, 0.221231742082476, -7.77156117237610e-16, 0.999999999999998, 1.90211303259031, 1.39680224666742, -4.88498130835069e-15, -0.642039521920206, 3.49210031947972e-15, 0.642039521920206, 2.55351295663786e-15, -1.39680224666742, -1.90211303259031, -0.999999999999996, -9.99200722162641e-16, -0.221231742082477, -1.17557050458494, -1.26007351067011, -3.67394039744206e-15, 1.26007351067010, 1.17557050458495, 0.221231742082472, -1.22124532708767e-15, 1.00000000000000, 1.90211303259031, 1.39680224666742, -1.09912079437891e-14, -0.642039521920206, 8.08638275819206e-15, 0.642039521920205, 3.55271367880050e-15, -1.39680224666741, -1.90211303259031, -0.999999999999997, -1.44328993201270e-15, -0.221231742082476, -1.17557050458494, -1.26007351067010, -4.89858719658941e-15, 1.26007351067010, 1.17557050458494, 0.221231742082472, 3.88578058618805e-15, 1.00000000000000, 1.90211303259031, 1.39680224666743, 4.44089209850063e-15, -0.642039521920207, -3.30654635769785e-15, 0.642039521920206, 4.55191440096314e-15, -1.39680224666742, -1.90211303259031, -0.999999999999998, 3.66373598126302e-15, -0.221231742082476, -1.17557050458495, -1.26007351067010, 1.16403343982657e-14, 1.26007351067010, 1.17557050458496, 0.221231742082482, -1.99840144432528e-15, 1.00000000000000, 1.90211303259031, 1.39680224666743, 5.44009282066327e-15, -0.642039521920206, 6.61680659921524e-15, 0.642039521920207, 5.55111512312578e-15, -1.39680224666742, -1.90211303259031, -0.999999999999984, -2.10942374678780e-15, -0.221231742082475, -1.17557050458493, -1.26007351067011, -7.34788079488412e-15, 1.26007351067010, 1.17557050458494, 0.221231742082483, -2.33146835171283e-15, 1.00000000000000, 1.90211303259031, 1.39680224666741, 6.32827124036339e-15, -0.642039521920206, 5.88201851972683e-15, 0.642039521920207, -2.22044604925031e-14, -1.39680224666742, -1.90211303259031, -0.999999999999985, 8.43769498715119e-15, -0.221231742082475, -1.17557050458495, -1.26007351067009, 2.69546091939735e-14, 1.26007351067009, 1.17557050458496, 0.221231742082484, -2.77555756156289e-15, 1, 1.90211303259030, 1.39680224666743, 7.32747196252603e-15, -0.642039521920206, 5.14723044023841e-15, 0.642039521920205, 7.54951656745106e-15, -1.39680224666742, -1.90211303259031, -0.999999999999986, -2.99760216648792e-15, -0.221231742082474, -1.17557050458495, -1.26007351067009, -9.79717439317883e-15, 1.26007351067010, 1.17557050458494, 0.221231742082465, 7.88258347483861e-15, 0.999999999999999, 1.90211303259031, 1.39680224666741, -2.04281036531029e-14, -0.642039521920204, 4.41244236075000e-15, 0.642039521920207, 8.43769498715119e-15, -1.39680224666742, -1.90211303259031, -1.00000000000002, -3.33066907387547e-15, -0.221231742082473, -1.17557050458493, -1.26007351067011, -1.10218211923262e-14, 1.26007351067010, 1.17557050458494, 0.221231742082485, -3.44169137633799e-15, 0.999999999999998, 1.90211303259031, 1.39680224666741, 9.32587340685132e-15, -0.642039521920206, 3.67765428126159e-15, 0.642039521920207, -1.93178806284777e-14, -1.39680224666742, -1.90211303259031, -0.999999999999988, 7.32747196252603e-15, -0.221231742082492, -1.17557050458495, -1.26007351067009, 2.32806687965315e-14, 1.26007351067012, 1.17557050458494, 0.221231742082467, -1.47659662275146e-14, 0.999999999999969, 1.90211303259030, 1.39680224666744, 1.02140518265514e-14, -0.642039521920206, 2.94286620177318e-15, 0.642039521920207, -1.83186799063151e-14, -1.39680224666739, -1.90211303259031, -1.00000000000002, -4.10782519111308e-15, -0.221231742082472, -1.17557050458495, -1.26007351067010, 2.20560219973841e-14, 1.26007351067011, 1.17557050458493, 0.221231742082486, -4.21884749357560e-15, 0.999999999999996, 1.90211303259031, 1.39680224666741, -1.75415237890775e-14, -0.642039521920204, 2.35243601950878e-14, 0.642039521920209, 1.15463194561016e-14, -1.39680224666742, -1.90211303259031, -0.999999999999990, -1.54321000422897e-14, -0.221231742082452, -1.17557050458493, -1.26007351067011, -1.46957615897682e-14, 1.26007351067010, 1.17557050458495, 0.221231742082468, 6.32827124036339e-15, 1.00000000000002, 1.90211303259030, 1.39680224666744, 1.23234755733392e-14, -0.642039521920207, 1.47329004279635e-15, 0.642039521920207, -1.62092561595273e-14, -1.39680224666744, -1.90211303259030, -1.00000000000002, -4.88498130835069e-15, -0.221231742082471, -1.17557050458495, -1.26007351067010, 1.96067283990894e-14, 1.26007351067011, 1.17557050458493, 0.221231742082450, 1.69864122767649e-14, 0.999999999999994, 1.90211303259031, 1.39680224666741, -1.54321000422897e-14, -0.642039521920205, 2.20547840361110e-14, 0.642039521920209, -4.39648317751562e-14, -1.39680224666747, -1.90211303259031, -0.999999999999992, 5.77315972805081e-15, -0.221231742082489, -1.17557050458496, -1.26007351067008, 5.39092183879471e-14, 1.26007351067013, 1.17557050458498, 0.221231742082507, -1.63202784619898e-14, 0.999999999999965, 1.90211303259030, 1.39680224666744, 1.43218770176645e-14, -0.642039521920207, 3.71388381953015e-18, 0.642039521920203, 4.31876756579186e-14, -1.39680224666739, -1.90211303259031, -1.00000000000002, -5.55111512312578e-15, -0.221231742082469, -1.17557050458495, -1.26007351067010, 1.71574348007947e-14, 1.26007351067008, 1.17557050458496, 0.221231742082489, -5.77315972805081e-15, 0.999999999999992, 1.90211303259031, 1.39680224666741, -1.34336985979644e-14, -0.642039521920205, 2.05852078771341e-14, 0.642039521920205, 1.54321000422897e-14, -1.39680224666741, -1.90211303259031, -0.999999999999994, 4.99600361081320e-15, -0.221231742082488, -1.17557050458496, -1.26007351067008}; + +//q31_t + q31_t expectoutput_q31_50Hz_200Hz[TEST_LENGTH_SAMPLES]; + q31_t error_ones_q31[TEST_LENGTH_SAMPLES]; + q31_t firStateq31_LMS[TEST_LENGTH_SAMPLES + NUM_TAPS - 1]; + q31_t testInput_q31_50Hz_200Hz[TEST_LENGTH_SAMPLES] = {0}, testOutput_q31[TEST_LENGTH_SAMPLES] = {0},testOutput_q31_ref[TEST_LENGTH_SAMPLES] = {0}; + q31_t firCoeffs32LP_q31[NUM_TAPS] = {0}; + +//q15_t + q15_t expectoutput_q15_50Hz_200Hz[TEST_LENGTH_SAMPLES]; + q15_t error_ones_q15[TEST_LENGTH_SAMPLES]; + q15_t firStateq15_LMS[TEST_LENGTH_SAMPLES + NUM_TAPS - 1]; + q15_t testInput_q15_50Hz_200Hz[TEST_LENGTH_SAMPLES] = {0}, testOutput_q15[TEST_LENGTH_SAMPLES] = {0},testOutput_q15_ref[TEST_LENGTH_SAMPLES] = {0}; + q15_t firCoeffs32LP_q15[NUM_TAPS] = {0}; + diff --git a/examples/dsp/FilteringFunction_NLMSPart/lms.c b/examples/dsp/FilteringFunction_NLMSPart/lms.c new file mode 100644 index 00000000..6cec08a2 --- /dev/null +++ b/examples/dsp/FilteringFunction_NLMSPart/lms.c @@ -0,0 +1,663 @@ +#include "ref.h" + +void ref_lms_f32(const riscv_lms_instance_f32 *S, float32_t *pSrc, + float32_t *pRef, float32_t *pOut, float32_t *pErr, + uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *pStateCurnt; /* Points to the current sample of the state */ + float32_t mu = S->mu; /* Adaptive factor */ + uint32_t numTaps = + S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i, blkCnt; /* Loop counters */ + float32_t sum, e, d; /* accumulator, error, reference data sample */ + float32_t w = 0.0f; /* weight factor */ + + e = 0.0f; + d = 0.0f; + + /* S->pState points to state array which contains previous frame (numTaps - + * 1) samples */ + /* pStateCurnt points to the location where the new input data should be + * written */ + pStateCurnt = &(S->pState[numTaps - 1U]); + + blkCnt = blockSize; + + while (blkCnt > 0U) { + /* Copy the new input sample into the state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Set the accumulator to zero */ + sum = 0.0f; + + for (i = 0; i < numTaps; i++) { /* Perform the multiply-accumulate */ + sum += pState[i] * pCoeffs[i]; + } + + /* The result is stored in the destination buffer. */ + *pOut++ = sum; + + /* Compute and store error */ + d = *pRef++; + e = d - sum; + *pErr++ = e; + + /* Weighting factor for the LMS version */ + w = e * mu; + + for (i = 0; i < numTaps; i++) { /* Perform the multiply-accumulate */ + pCoeffs[i] += w * pState[i]; + } + + /* Advance state pointer by 1 for the next sample */ + pState++; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Processing is complete. Now copy the last numTaps - 1 samples to the + * start of the state buffer. This prepares the state buffer for the + * next function call. */ + for (i = 0; i < numTaps - 1; i++) { + S->pState[i] = pState[i]; + } +} + +void ref_lms_norm_f32(riscv_lms_norm_instance_f32 *S, float32_t *pSrc, + float32_t *pRef, float32_t *pOut, float32_t *pErr, + uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *pStateCurnt; /* Points to the current sample of the state */ + float32_t mu = S->mu; /* Adaptive factor */ + uint32_t numTaps = + S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i, blkCnt; /* Loop counters */ + float32_t energy; /* Energy of the input */ + float32_t sum, e, d; /* accumulator, error, reference data sample */ + float32_t w, x0, in; /* weight factor, temporary variable to hold input + sample and state */ + + /* Initializations of error, difference, Coefficient update */ + e = 0.0f; + d = 0.0f; + w = 0.0f; + + energy = S->energy; + x0 = S->x0; + + /* S->pState points to buffer which contains previous frame (numTaps - 1) + * samples */ + /* pStateCurnt points to the location where the new input data should be + * written */ + pStateCurnt = &(S->pState[numTaps - 1U]); + + for (blkCnt = blockSize; blkCnt > 0U; blkCnt--) { + /* Copy the new input sample into the state buffer */ + *pStateCurnt++ = *pSrc; + + /* Read the sample from input buffer */ + in = *pSrc++; + + /* Update the energy calculation */ + energy -= x0 * x0; + energy += in * in; + + /* Set the accumulator to zero */ + sum = 0.0f; + + for (i = 0; i < numTaps; i++) { /* Perform the multiply-accumulate */ + sum += pState[i] * pCoeffs[i]; + } + + /* The result in the accumulator is stored in the destination buffer. */ + *pOut++ = sum; + + /* Compute and store error */ + d = *pRef++; + e = d - sum; + *pErr++ = e; + + /* Calculation of Weighting factor for updating filter coefficients */ + /* epsilon value 0.000000119209289f */ + w = e * mu / (energy + 0.000000119209289f); + + for (i = 0; i < numTaps; i++) { + /* Perform the multiply-accumulate */ + pCoeffs[i] += w * pState[i]; + } + + x0 = *pState; + + /* Advance state pointer by 1 for the next sample */ + pState++; + } + + S->energy = energy; + S->x0 = x0; + + /* Processing is complete. Now copy the last numTaps - 1 samples to the + * start of the state buffer. This prepares the state buffer for the + * next function call. */ + for (i = 0; i < numTaps - 1; i++) { + S->pState[i] = pState[i]; + } +} + +void ref_lms_q31(const riscv_lms_instance_q31 *S, q31_t *pSrc, q31_t *pRef, + q31_t *pOut, q31_t *pErr, uint32_t blockSize) +{ + q31_t *pState = S->pState; /* State pointer */ + uint32_t numTaps = + S->numTaps; /* Number of filter coefficients in the filter */ + q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *pStateCurnt; /* Points to the current sample of the state */ + q31_t mu = S->mu; /* Adaptive factor */ + q31_t *px; /* Temporary pointer for state */ + q31_t *pb; /* Temporary pointer for coefficient buffer */ + uint32_t tapCnt, blkCnt; /* Loop counters */ + q63_t acc; /* Accumulator */ + q31_t e = 0; /* error of data sample */ + q31_t alpha; /* Intermediate constant for taps update */ + q31_t coef; /* Temporary variable for coef */ + q31_t acc_l, acc_h; /* temporary input */ + uint32_t uShift = (uint32_t)S->postShift + 1; + uint32_t lShift = 32U - uShift; /* Shift to be applied to the output */ + + /* S->pState points to buffer which contains previous frame (numTaps - 1) + * samples */ + /* pStateCurnt points to the location where the new input data should be + * written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + + for (blkCnt = blockSize; blkCnt > 0U; blkCnt--) { + /* Copy the new input sample into the state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Initialize pState pointer */ + px = pState; + + /* Initialize pCoeffs pointer */ + pb = pCoeffs; + + /* Set the accumulator to zero */ + acc = 0; + + /* Loop over numTaps number of values */ + tapCnt = numTaps; + + while (tapCnt > 0U) { + /* Perform the multiply-accumulate */ + acc += (q63_t)(*px++) * (*pb++); + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Converting the result to 1.31 format */ + /* Store the result from accumulator into the destination buffer. */ + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + acc = (uint32_t)acc_l >> lShift | acc_h << uShift; + + *pOut++ = (q31_t)acc; + + /* Compute and store error */ + e = *pRef++ - (q31_t)acc; + + *pErr++ = (q31_t)e; + + /* Weighting factor for the LMS version */ + alpha = (q31_t)(((q63_t)e * mu) >> 31); + + /* Initialize pState pointer */ + /* Advance state pointer by 1 for the next sample */ + px = pState++; + + /* Initialize pCoeffs pointer */ + pb = pCoeffs; + + /* Loop over numTaps number of values */ + tapCnt = numTaps; + + while (tapCnt > 0U) { + /* Perform the multiply-accumulate */ + coef = (q31_t)(((q63_t)alpha * (*px++)) >> 32); + *pb = ref_sat_q31((q63_t)*pb + (coef << 1)); + pb++; + + /* Decrement the loop counter */ + tapCnt--; + } + } + + /* Processing is complete. Now copy the last numTaps - 1 samples to the + start of the state buffer. This prepares the state buffer for the + next function call. */ + + /* Points to the start of the pState buffer */ + pStateCurnt = S->pState; + + /* Copy (numTaps - 1U) samples */ + tapCnt = numTaps - 1; + + /* Copy the data */ + while (tapCnt > 0U) { + *pStateCurnt++ = *pState++; + + /* Decrement the loop counter */ + tapCnt--; + } +} + +void ref_lms_norm_q31(riscv_lms_norm_instance_q31 *S, q31_t *pSrc, q31_t *pRef, + q31_t *pOut, q31_t *pErr, uint32_t blockSize) +{ + q31_t *pState = S->pState; /* State pointer */ + q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *pStateCurnt; /* Points to the current sample of the state */ + q31_t *px, *pb; /* Temporary pointers for state and coefficient buffers */ + q31_t mu = S->mu; /* Adaptive factor */ + uint32_t numTaps = + S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t tapCnt, blkCnt; /* Loop counters */ + q63_t energy; /* Energy of the input */ + q63_t acc; /* Accumulator */ + q31_t e = 0, d = 0; /* error, reference data sample */ + q31_t w = 0, in; /* weight factor and state */ + q31_t x0; /* temporary variable to hold input sample */ + q63_t errorXmu; /* Temporary variables to store error and mu product and + reciprocal of energy */ + q31_t coef; /* Temporary variable for coef */ + q31_t acc_l, acc_h; /* temporary input */ + uint32_t uShift = ((uint32_t)S->postShift + 1U); + uint32_t lShift = 32U - uShift; /* Shift to be applied to the output */ + + energy = S->energy; + x0 = S->x0; + + /* S->pState points to buffer which contains previous frame (numTaps - 1) + * samples */ + /* pStateCurnt points to the location where the new input data should be + * written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + + for (blkCnt = blockSize; blkCnt > 0U; blkCnt--) { + + /* Copy the new input sample into the state buffer */ + *pStateCurnt++ = *pSrc; + + /* Initialize pState pointer */ + px = pState; + + /* Initialize pCoeffs pointer */ + pb = pCoeffs; + + /* Read the sample from input buffer */ + in = *pSrc++; + + /* Update the energy calculation */ + energy = + (q31_t)((((q63_t)energy << 32) - (((q63_t)x0 * x0) << 1)) >> 32) & + 0xffffffff; + energy = + (q31_t)(((((q63_t)in * in) << 1) + ((q63_t)energy << 32)) >> 32) & + 0xffffffff; + + /* Set the accumulator to zero */ + acc = 0; + + /* Loop over numTaps number of values */ + tapCnt = numTaps; + + while (tapCnt > 0U) { + /* Perform the multiply-accumulate */ + acc += ((q63_t)(*px++)) * (*pb++); + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Converting the result to 1.31 format */ + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + acc = (uint32_t)acc_l >> lShift | acc_h << uShift; + + /* Store the result from accumulator into the destination buffer. */ + *pOut++ = (q31_t)acc; + + /* Compute and store error */ + d = *pRef++; + e = d - (q31_t)acc; + *pErr++ = e; + + /* Calculation of product of (e * mu) */ + errorXmu = (q63_t)e * mu; + + /* Weighting factor for the normalized version */ + w = ref_sat_q31(errorXmu / (energy + DELTA_Q31)); + + /* Initialize pState pointer */ + px = pState; + + /* Initialize coeff pointer */ + pb = pCoeffs; + + /* Loop over numTaps number of values */ + tapCnt = numTaps; + + while (tapCnt > 0U) { + /* Perform the multiply-accumulate */ + /* coef is in 2.30 format */ + coef = (q31_t)(((q63_t)w * (*px++)) >> 32); + /* get coef in 1.31 format by left shifting */ + *pb = ref_sat_q31((q63_t)*pb + (coef << 1U)); + /* update coefficient buffer to next coefficient */ + pb++; + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Read the sample from state buffer */ + x0 = *pState; + + /* Advance state pointer by 1 for the next sample */ + pState++; + } + + /* Save energy and x0 values for the next frame */ + S->energy = (q31_t)energy; + S->x0 = x0; + + /* Processing is complete. Now copy the last numTaps - 1 samples to the + start of the state buffer. This prepares the state buffer for the + next function call. */ + + /* Points to the start of the pState buffer */ + pStateCurnt = S->pState; + + /* Loop for (numTaps - 1U) samples copy */ + tapCnt = numTaps - 1; + + /* Copy the remaining q31_t data */ + while (tapCnt > 0U) { + *pStateCurnt++ = *pState++; + + /* Decrement the loop counter */ + tapCnt--; + } +} + +void ref_lms_q15(const riscv_lms_instance_q15 *S, q15_t *pSrc, q15_t *pRef, + q15_t *pOut, q15_t *pErr, uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + uint32_t numTaps = + S->numTaps; /* Number of filter coefficients in the filter */ + q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCurnt; /* Points to the current sample of the state */ + q15_t mu = S->mu; /* Adaptive factor */ + q15_t *px; /* Temporary pointer for state */ + q15_t *pb; /* Temporary pointer for coefficient buffer */ + uint32_t tapCnt, blkCnt; /* Loop counters */ + q63_t acc; /* Accumulator */ + q15_t e = 0; /* error of data sample */ + q15_t alpha; /* Intermediate constant for taps update */ + q31_t coef; /* Teporary variable for coefficient */ + q31_t acc_l, acc_h; + int32_t lShift = 15 - (int32_t)S->postShift; /* Post shift */ + int32_t uShift = 32 - lShift; + + /* S->pState points to buffer which contains previous frame (numTaps - 1) + * samples */ + /* pStateCurnt points to the location where the new input data should be + * written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + + for (blkCnt = blockSize; blkCnt > 0U; blkCnt--) { + /* Copy the new input sample into the state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Initialize pState pointer */ + px = pState; + + /* Initialize pCoeffs pointer */ + pb = pCoeffs; + + /* Set the accumulator to zero */ + acc = 0; + + /* Loop over numTaps number of values */ + tapCnt = numTaps; + + while (tapCnt > 0U) { + /* Perform the multiply-accumulate */ + acc += (q63_t)((q31_t)(*px++) * (*pb++)); + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + /* Apply shift for lower part of acc and upper part of acc */ + acc = (uint32_t)acc_l >> lShift | acc_h << uShift; + + /* Converting the result to 1.15 format and saturate the output */ + acc = ref_sat_q15(acc); + + /* Store the result from accumulator into the destination buffer. */ + *pOut++ = (q15_t)acc; + + /* Compute and store error */ + e = *pRef++ - (q15_t)acc; + + *pErr++ = (q15_t)e; + + /* Compute alpha i.e. intermediate constant for taps update */ + alpha = (q15_t)(((q31_t)e * mu) >> 15); + + /* Initialize pState pointer */ + /* Advance state pointer by 1 for the next sample */ + px = pState++; + + /* Initialize pCoeffs pointer */ + pb = pCoeffs; + + /* Loop over numTaps number of values */ + tapCnt = numTaps; + + while (tapCnt > 0U) { + /* Perform the multiply-accumulate */ + coef = (q31_t)*pb + (((q31_t)alpha * (*px++)) >> 15); + *pb++ = (q15_t)ref_sat_q15(coef); + + /* Decrement the loop counter */ + tapCnt--; + } + } + + /* Processing is complete. Now copy the last numTaps - 1 samples to the + start of the state buffer. This prepares the state buffer for the + next function call. */ + + /* Points to the start of the pState buffer */ + pStateCurnt = S->pState; + + /* Copy (numTaps - 1U) samples */ + tapCnt = numTaps - 1; + + /* Copy the data */ + while (tapCnt > 0U) { + *pStateCurnt++ = *pState++; + + /* Decrement the loop counter */ + tapCnt--; + } +} + +void ref_lms_norm_q15(riscv_lms_norm_instance_q15 *S, q15_t *pSrc, q15_t *pRef, + q15_t *pOut, q15_t *pErr, uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCurnt; /* Points to the current sample of the state */ + q15_t *px, *pb; /* Temporary pointers for state and coefficient buffers */ + q15_t mu = S->mu; /* Adaptive factor */ + uint32_t numTaps = + S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t tapCnt, blkCnt; /* Loop counters */ + q31_t energy; /* Energy of the input */ + q63_t acc; /* Accumulator */ + q15_t e = 0, d = 0; /* error, reference data sample */ + q15_t w = 0, in; /* weight factor and state */ + q15_t x0; /* temporary variable to hold input sample */ + q15_t errorXmu, oneByEnergy; /* Temporary variables to store error and mu + product and reciprocal of energy */ + // q31_t errorXmu; /* Temporary variables to store + // error and mu product and reciprocal of energy */ + q15_t postShift; /* Post shift to be applied to weight after reciprocal + calculation */ + q31_t coef; /* Teporary variable for coefficient */ + q31_t acc_l, acc_h; + int32_t lShift = 15 - (int32_t)S->postShift; /* Post shift */ + int32_t uShift = 32 - lShift; + + energy = S->energy; + x0 = S->x0; + + /* S->pState points to buffer which contains previous frame (numTaps - 1) + * samples */ + /* pStateCurnt points to the location where the new input data should be + * written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + + for (blkCnt = blockSize; blkCnt > 0U; blkCnt--) { + /* Copy the new input sample into the state buffer */ + *pStateCurnt++ = *pSrc; + + /* Initialize pState pointer */ + px = pState; + + /* Initialize pCoeffs pointer */ + pb = pCoeffs; + + /* Read the sample from input buffer */ + in = *pSrc++; + + /* Update the energy calculation */ + energy -= (((q31_t)x0 * x0) >> 15) & 0xffff; + energy += (((q31_t)in * in) >> 15) & 0xffff; + + /* Set the accumulator to zero */ + acc = 0; + + /* Loop over numTaps number of values */ + tapCnt = numTaps; + + while (tapCnt > 0U) { + /* Perform the multiply-accumulate */ + acc += (q31_t)*px++ * (*pb++); + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + /* Apply shift for lower part of acc and upper part of acc */ + acc = (uint32_t)acc_l >> lShift | acc_h << uShift; + + /* Converting the result to 1.15 format and saturate the output */ + acc = ref_sat_q15(acc); + + /* Store the result from accumulator into the destination buffer. */ + *pOut++ = (q15_t)acc; + + /* Compute and store error */ + d = *pRef++; + e = d - (q15_t)acc; + *pErr++ = e; + + + /* Calculation of 1/energy */ + postShift = riscv_recip_q15((q15_t)energy + DELTA_Q15, &oneByEnergy, + S->recipTable); + + /* Calculation of e * mu value */ + errorXmu = (q15_t)(((q31_t)e * mu) >> 15); + + /* Calculation of (e * mu) * (1/energy) value */ + acc = (((q31_t)errorXmu * oneByEnergy) >> (15 - postShift)); + + /* Weighting factor for the normalized version */ + w = ref_sat_q15((q31_t)acc); + + /* Initialize pState pointer */ + px = pState; + + /* Initialize coeff pointer */ + pb = pCoeffs; + + /* Loop over numTaps number of values */ + tapCnt = numTaps; + + while (tapCnt > 0U) { + /* Perform the multiply-accumulate */ + coef = *pb + (((q31_t)w * (*px++)) >> 15); + *pb++ = ref_sat_q15(coef); + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Read the sample from state buffer */ + x0 = *pState; + + /* Advance state pointer by 1 for the next sample */ + pState = pState + 1U; + } + + /* Save energy and x0 values for the next frame */ + S->energy = (q15_t)energy; + S->x0 = x0; + + /* Processing is complete. Now copy the last numTaps - 1 samples to the + satrt of the state buffer. This prepares the state buffer for the + next function call. */ + + /* Points to the start of the pState buffer */ + pStateCurnt = S->pState; + + /* copy (numTaps - 1U) data */ + tapCnt = numTaps - 1; + + /* copy data */ + while (tapCnt > 0U) { + *pStateCurnt++ = *pState++; + + /* Decrement the loop counter */ + tapCnt--; + } +} diff --git a/examples/dsp/FilteringFunction_NLMSPart/main.c b/examples/dsp/FilteringFunction_NLMSPart/main.c new file mode 100644 index 00000000..ad1866da --- /dev/null +++ b/examples/dsp/FilteringFunction_NLMSPart/main.c @@ -0,0 +1,168 @@ +// +// Created by lujun on 19-6-28. +// +// This contains fir, iir and lms filters +// each one has it's own function. +// All function can be found in main function. +// If you don't want to use it, then comment it. +// +// This part only tests result after 50 dots.If you want to test results' all +// dots, please define WITH_FRONT +// +// If there are too much numbers which makes it hard to read,in VScode you can +// press alt and z can shrimp them to one line +// +// You MUST be careful about overflow. +#include "riscv_math.h" +#include "array.h" +#include +#include "../common.h" + +#include "../HelperFunctions/math_helper.c" +#include "../HelperFunctions/ref_helper.c" + +#include +#define DELTAF32 (0.05f) +#define DELTAQ31 (63) +#define DELTAQ15 (1) +#define DELTAQ7 (1) +#define SNR_THRESHOLD_F32 (80.0f) + +int test_flag_error = 0; + +// #define WITH_FRONT + +//*************************************************************************************** +// Normalized LMS Filters +//*************************************************************************************** +static void riscv_fir_f32_NLMS_lp(void) +{ + uint32_t i; + /* clang-format off */ + riscv_lms_norm_instance_f32 S; + /* clang-format on */ + for (i = 0; i < TEST_LENGTH_SAMPLES; i++) + error_ones[i] = 1; + riscv_lms_norm_init_f32(&S, NUM_TAPS, &firCoeffs32LP[0], &firStateF32_LMS[0], 0.00000001f, TEST_LENGTH_SAMPLES); + BENCH_START(riscv_lms_norm_f32); + riscv_lms_norm_f32(&S, testInput_f32_50Hz_200Hz, expectoutput_f32_50Hz_200Hz, testOutput_f32, &error_ones[0], TEST_LENGTH_SAMPLES); + BENCH_END(riscv_lms_norm_f32); + riscv_lms_norm_init_f32(&S, NUM_TAPS, &firCoeffs32LP[0], &firStateF32_LMS[0], 0.00000001f, TEST_LENGTH_SAMPLES); + ref_lms_norm_f32(&S, testInput_f32_50Hz_200Hz, expectoutput_f32_50Hz_200Hz, testOutput_f32_ref, &error_ones[0], TEST_LENGTH_SAMPLES); +#ifndef WITH_FRONT + float snr = riscv_snr_f32(&testOutput_f32_ref[50], &testOutput_f32[50], 269); + + if (snr < SNR_THRESHOLD_F32) { + BENCH_ERROR(riscv_lms_norm_f32); + printf("f32 lms_norm failed with snr:%f\n", snr); + test_flag_error = 1; + } + BENCH_STATUS(riscv_lms_norm_f32); +#else + float snr = + riscv_snr_f32(&testOutput_f32_ref[0], &testOutput_f32[0], TEST_LENGTH_SAMPLES); + + if (snr < SNR_THRESHOLD_F32) { + BENCH_ERROR(riscv_lms_norm_f32); + printf("f32 lms_norm failed with snr:%f\n", snr); + test_flag_error = 1; + } + BENCH_STATUS(riscv_lms_norm_f32); +#endif +} +static void riscv_fir_q31_NLMS_lp(void) +{ + uint32_t i; + /* clang-format off */ + riscv_lms_norm_instance_q31 S; + /* clang-format on */ + for (i = 0; i < TEST_LENGTH_SAMPLES; i++) + error_ones_q31[i] = 1; + riscv_float_to_q31(testInput_f32_50Hz_200Hz, testInput_q31_50Hz_200Hz, TEST_LENGTH_SAMPLES); + riscv_float_to_q31(expectoutput_f32_50Hz_200Hz, expectoutput_q31_50Hz_200Hz, TEST_LENGTH_SAMPLES); + riscv_float_to_q31(firCoeffs32LP, firCoeffs32LP_q31, NUM_TAPS); + riscv_lms_norm_init_q31(&S, NUM_TAPS, &firCoeffs32LP_q31[0], &firStateq31_LMS[0], 15, TEST_LENGTH_SAMPLES, 1); + BENCH_START(riscv_lms_norm_q31); + riscv_lms_norm_q31(&S, testInput_q31_50Hz_200Hz, expectoutput_q31_50Hz_200Hz, testOutput_q31, error_ones_q31, TEST_LENGTH_SAMPLES); + BENCH_END(riscv_lms_norm_q31); + riscv_lms_norm_init_q31(&S, NUM_TAPS, &firCoeffs32LP_q31[0], &firStateq31_LMS[0], 15, TEST_LENGTH_SAMPLES, 1); + ref_lms_norm_q31(&S, testInput_q31_50Hz_200Hz, expectoutput_q31_50Hz_200Hz, testOutput_q31_ref, error_ones_q31, TEST_LENGTH_SAMPLES); + riscv_q31_to_float(testOutput_q31, testOutput_f32, TEST_LENGTH_SAMPLES); + riscv_q31_to_float(testOutput_q31_ref, testOutput_f32_ref, TEST_LENGTH_SAMPLES); +#ifndef WITH_FRONT + float snr = riscv_snr_f32(&testOutput_f32_ref[50], &testOutput_f32[50], 269); + + if (snr < SNR_THRESHOLD_F32) { + BENCH_ERROR(riscv_lms_norm_q31); + printf("q31 lms_norm failed with snr:%f\n", snr); + test_flag_error = 1; + } + BENCH_STATUS(riscv_lms_norm_q31); +#else + float snr = riscv_snr_f32(&testOutput_f32_ref[0], &testOutput_f32[0], + TEST_LENGTH_SAMPLES); + + if (snr < SNR_THRESHOLD_F32) { + BENCH_ERROR(riscv_lms_norm_q31); + printf("q31 lms_norm failed with snr:%f\n", snr); + test_flag_error = 1; + } + BENCH_STATUS(riscv_lms_norm_q31); +#endif +} +static void riscv_fir_q15_NLMS_lp(void) +{ + uint32_t i; + /* clang-format off */ + riscv_lms_norm_instance_q15 S; + /* clang-format on */ + for (i = 0; i < TEST_LENGTH_SAMPLES; i++) + error_ones_q15[i] = 1; + riscv_float_to_q15(testInput_f32_50Hz_200Hz, testInput_q15_50Hz_200Hz, TEST_LENGTH_SAMPLES); + riscv_float_to_q15(expectoutput_f32_50Hz_200Hz, expectoutput_q15_50Hz_200Hz, TEST_LENGTH_SAMPLES); + riscv_float_to_q15(firCoeffs32LP, firCoeffs32LP_q15, NUM_TAPS); + riscv_lms_norm_init_q15(&S, NUM_TAPS, &firCoeffs32LP_q15[0], &firStateq15_LMS[0], 0, TEST_LENGTH_SAMPLES, 1); + BENCH_START(riscv_lms_norm_q15); + riscv_lms_norm_q15(&S, testInput_q15_50Hz_200Hz, expectoutput_q15_50Hz_200Hz, testOutput_q15, error_ones_q15, TEST_LENGTH_SAMPLES); + BENCH_END(riscv_lms_norm_q15); + riscv_lms_norm_init_q15(&S, NUM_TAPS, &firCoeffs32LP_q15[0], &firStateq15_LMS[0], 0, TEST_LENGTH_SAMPLES, 1); + ref_lms_norm_q15(&S, testInput_q15_50Hz_200Hz, expectoutput_q15_50Hz_200Hz, testOutput_q15_ref, error_ones_q15, TEST_LENGTH_SAMPLES); + riscv_q15_to_float(testOutput_q15, testOutput_f32, TEST_LENGTH_SAMPLES); + riscv_q15_to_float(testOutput_q15_ref, testOutput_f32_ref, TEST_LENGTH_SAMPLES); +#ifndef WITH_FRONT + float snr = riscv_snr_f32(&testOutput_f32_ref[50], &testOutput_f32[50], 269); + + if (snr < SNR_THRESHOLD_F32) { + BENCH_ERROR(riscv_lms_norm_q15); + printf("q15 lms_norm failed with snr:%f\n", snr); + test_flag_error = 1; + } + BENCH_STATUS(riscv_lms_norm_q15); +#else + float snr = riscv_snr_f32(&testOutput_f32_ref[0], &testOutput_f32[0], + TEST_LENGTH_SAMPLES); + + if (snr < SNR_THRESHOLD_F32) { + BENCH_ERROR(riscv_lms_norm_q15); + printf("q15 lms_norm failed with snr:%f\n", snr); + test_flag_error = 1; + } + BENCH_STATUS(riscv_lms_norm_q15); +#endif +} + +int main() +{ + BENCH_INIT; + riscv_fir_f32_NLMS_lp(); + riscv_fir_q31_NLMS_lp(); + riscv_fir_q15_NLMS_lp(); + BENCH_FINISH; + if (test_flag_error) { + printf("test error apprears, please recheck.\n"); + return 1; + } else { + printf("all test are passed. Well done!\n"); + } + return 0; +} diff --git a/examples/dsp/FilteringFunction_firDecimatorPart/CMakeLists.txt b/examples/dsp/FilteringFunction_firDecimatorPart/CMakeLists.txt new file mode 100644 index 00000000..289b0629 --- /dev/null +++ b/examples/dsp/FilteringFunction_firDecimatorPart/CMakeLists.txt @@ -0,0 +1,5 @@ +set(TARGET_REQUIRED_PRIVATE_INCLUDE ${CMAKE_CURRENT_SOURCE_DIR} ${CMAKE_CURRENT_SOURCE_DIR}/..) +set(TARGET_REQUIRED_SRCS fir_decimate.c) +set(TARGET_REQUIRED_LIBS nmsis) +set(mains main.c) +generate_bin() \ No newline at end of file diff --git a/examples/dsp/FilteringFunction_firDecimatorPart/array.h b/examples/dsp/FilteringFunction_firDecimatorPart/array.h new file mode 100644 index 00000000..2ff3d341 --- /dev/null +++ b/examples/dsp/FilteringFunction_firDecimatorPart/array.h @@ -0,0 +1,25 @@ +// Array for FilteringFunctions firDecimatorPart +#define TEST_LENGTH_SAMPLES 320 /* ???? */ +#define NUM_TAPS 29 /* ??????? */ + +const float32_t firCoeffs32LP[NUM_TAPS] = { + -0.001822523074f, -0.001587929321f, 1.226008847e-18f, 0.003697750857f, 0.008075430058f, + 0.008530221879f, -4.273456581e-18f, -0.01739769801f, -0.03414586186f, -0.03335915506f, + 8.073562366e-18f, 0.06763084233f, 0.1522061825f, 0.2229246944f, 0.2504960895f, + 0.2229246944f, 0.1522061825f, 0.06763084233f, 8.073562366e-18f, -0.03335915506f, + -0.03414586186f, -0.01739769801f, -4.273456581e-18f, 0.008530221879f, 0.008075430058f, + 0.003697750857f, 1.226008847e-18f, -0.001587929321f, -0.001822523074f}; +// float32_t + float32_t testOutput_f32[TEST_LENGTH_SAMPLES/2],testOutput_f32_ref[TEST_LENGTH_SAMPLES/2]; + float32_t firStatef32[TEST_LENGTH_SAMPLES + NUM_TAPS - 1]={0}; + float32_t testInput_f32_50Hz_200Hz[TEST_LENGTH_SAMPLES] = {0, 1.26007351067010, 1.17557050458495, 0.221231742082474, -1.11022302462516e-16, 1.00000000000000, 1.90211303259031, 1.39680224666742, 4.44089209850063e-16, -0.642039521920206, -3.67394039744206e-16, 0.642039521920206, -1.22124532708767e-15, -1.39680224666742, -1.90211303259031, -1.00000000000000, -3.33066907387547e-16, -0.221231742082476, -1.17557050458495, -1.26007351067010, -1.22464679914735e-15, 1.26007351067010, 1.17557050458495, 0.221231742082475, 8.88178419700125e-16, 1.00000000000000, 1.90211303259031, 1.39680224666742, 1.33226762955019e-15, -0.642039521920206, -1.10218211923262e-15, 0.642039521920206, 1.55431223447522e-15, -1.39680224666743, -1.90211303259031, -0.999999999999995, -7.77156117237610e-16, -0.221231742082473, -1.17557050458495, -1.26007351067010, -2.44929359829471e-15, 1.26007351067010, 1.17557050458494, 0.221231742082476, -7.77156117237610e-16, 0.999999999999998, 1.90211303259031, 1.39680224666742, -4.88498130835069e-15, -0.642039521920206, 3.49210031947972e-15, 0.642039521920206, 2.55351295663786e-15, -1.39680224666742, -1.90211303259031, -0.999999999999996, -9.99200722162641e-16, -0.221231742082477, -1.17557050458494, -1.26007351067011, -3.67394039744206e-15, 1.26007351067010, 1.17557050458495, 0.221231742082472, -1.22124532708767e-15, 1.00000000000000, 1.90211303259031, 1.39680224666742, -1.09912079437891e-14, -0.642039521920206, 8.08638275819206e-15, 0.642039521920205, 3.55271367880050e-15, -1.39680224666741, -1.90211303259031, -0.999999999999997, -1.44328993201270e-15, -0.221231742082476, -1.17557050458494, -1.26007351067010, -4.89858719658941e-15, 1.26007351067010, 1.17557050458494, 0.221231742082472, 3.88578058618805e-15, 1.00000000000000, 1.90211303259031, 1.39680224666743, 4.44089209850063e-15, -0.642039521920207, -3.30654635769785e-15, 0.642039521920206, 4.55191440096314e-15, -1.39680224666742, -1.90211303259031, -0.999999999999998, 3.66373598126302e-15, -0.221231742082476, -1.17557050458495, -1.26007351067010, 1.16403343982657e-14, 1.26007351067010, 1.17557050458496, 0.221231742082482, -1.99840144432528e-15, 1.00000000000000, 1.90211303259031, 1.39680224666743, 5.44009282066327e-15, -0.642039521920206, 6.61680659921524e-15, 0.642039521920207, 5.55111512312578e-15, -1.39680224666742, -1.90211303259031, -0.999999999999984, -2.10942374678780e-15, -0.221231742082475, -1.17557050458493, -1.26007351067011, -7.34788079488412e-15, 1.26007351067010, 1.17557050458494, 0.221231742082483, -2.33146835171283e-15, 1.00000000000000, 1.90211303259031, 1.39680224666741, 6.32827124036339e-15, -0.642039521920206, 5.88201851972683e-15, 0.642039521920207, -2.22044604925031e-14, -1.39680224666742, -1.90211303259031, -0.999999999999985, 8.43769498715119e-15, -0.221231742082475, -1.17557050458495, -1.26007351067009, 2.69546091939735e-14, 1.26007351067009, 1.17557050458496, 0.221231742082484, -2.77555756156289e-15, 1, 1.90211303259030, 1.39680224666743, 7.32747196252603e-15, -0.642039521920206, 5.14723044023841e-15, 0.642039521920205, 7.54951656745106e-15, -1.39680224666742, -1.90211303259031, -0.999999999999986, -2.99760216648792e-15, -0.221231742082474, -1.17557050458495, -1.26007351067009, -9.79717439317883e-15, 1.26007351067010, 1.17557050458494, 0.221231742082465, 7.88258347483861e-15, 0.999999999999999, 1.90211303259031, 1.39680224666741, -2.04281036531029e-14, -0.642039521920204, 4.41244236075000e-15, 0.642039521920207, 8.43769498715119e-15, -1.39680224666742, -1.90211303259031, -1.00000000000002, -3.33066907387547e-15, -0.221231742082473, -1.17557050458493, -1.26007351067011, -1.10218211923262e-14, 1.26007351067010, 1.17557050458494, 0.221231742082485, -3.44169137633799e-15, 0.999999999999998, 1.90211303259031, 1.39680224666741, 9.32587340685132e-15, -0.642039521920206, 3.67765428126159e-15, 0.642039521920207, -1.93178806284777e-14, -1.39680224666742, -1.90211303259031, -0.999999999999988, 7.32747196252603e-15, -0.221231742082492, -1.17557050458495, -1.26007351067009, 2.32806687965315e-14, 1.26007351067012, 1.17557050458494, 0.221231742082467, -1.47659662275146e-14, 0.999999999999969, 1.90211303259030, 1.39680224666744, 1.02140518265514e-14, -0.642039521920206, 2.94286620177318e-15, 0.642039521920207, -1.83186799063151e-14, -1.39680224666739, -1.90211303259031, -1.00000000000002, -4.10782519111308e-15, -0.221231742082472, -1.17557050458495, -1.26007351067010, 2.20560219973841e-14, 1.26007351067011, 1.17557050458493, 0.221231742082486, -4.21884749357560e-15, 0.999999999999996, 1.90211303259031, 1.39680224666741, -1.75415237890775e-14, -0.642039521920204, 2.35243601950878e-14, 0.642039521920209, 1.15463194561016e-14, -1.39680224666742, -1.90211303259031, -0.999999999999990, -1.54321000422897e-14, -0.221231742082452, -1.17557050458493, -1.26007351067011, -1.46957615897682e-14, 1.26007351067010, 1.17557050458495, 0.221231742082468, 6.32827124036339e-15, 1.00000000000002, 1.90211303259030, 1.39680224666744, 1.23234755733392e-14, -0.642039521920207, 1.47329004279635e-15, 0.642039521920207, -1.62092561595273e-14, -1.39680224666744, -1.90211303259030, -1.00000000000002, -4.88498130835069e-15, -0.221231742082471, -1.17557050458495, -1.26007351067010, 1.96067283990894e-14, 1.26007351067011, 1.17557050458493, 0.221231742082450, 1.69864122767649e-14, 0.999999999999994, 1.90211303259031, 1.39680224666741, -1.54321000422897e-14, -0.642039521920205, 2.20547840361110e-14, 0.642039521920209, -4.39648317751562e-14, -1.39680224666747, -1.90211303259031, -0.999999999999992, 5.77315972805081e-15, -0.221231742082489, -1.17557050458496, -1.26007351067008, 5.39092183879471e-14, 1.26007351067013, 1.17557050458498, 0.221231742082507, -1.63202784619898e-14, 0.999999999999965, 1.90211303259030, 1.39680224666744, 1.43218770176645e-14, -0.642039521920207, 3.71388381953015e-18, 0.642039521920203, 4.31876756579186e-14, -1.39680224666739, -1.90211303259031, -1.00000000000002, -5.55111512312578e-15, -0.221231742082469, -1.17557050458495, -1.26007351067010, 1.71574348007947e-14, 1.26007351067008, 1.17557050458496, 0.221231742082489, -5.77315972805081e-15, 0.999999999999992, 1.90211303259031, 1.39680224666741, -1.34336985979644e-14, -0.642039521920205, 2.05852078771341e-14, 0.642039521920205, 1.54321000422897e-14, -1.39680224666741, -1.90211303259031, -0.999999999999994, 4.99600361081320e-15, -0.221231742082488, -1.17557050458496, -1.26007351067008}; + +//q31_t + q31_t firStateq31[TEST_LENGTH_SAMPLES + NUM_TAPS - 1]; + q31_t testInput_q31_50Hz_200Hz[TEST_LENGTH_SAMPLES] = {0}, testOutput_q31[TEST_LENGTH_SAMPLES/2] = {0},testOutput_q31_ref[TEST_LENGTH_SAMPLES/2] = {0}; + q31_t firCoeffs32LP_q31[NUM_TAPS] = {0}; + +//q15_t + q15_t firStateq15[TEST_LENGTH_SAMPLES + NUM_TAPS - 1]; + q15_t testInput_q15_50Hz_200Hz[TEST_LENGTH_SAMPLES] = {0}, testOutput_q15[TEST_LENGTH_SAMPLES/2] = {0},testOutput_q15_ref[TEST_LENGTH_SAMPLES/2] = {0}; + q15_t firCoeffs32LP_q15[NUM_TAPS] = {0}; \ No newline at end of file diff --git a/examples/dsp/FilteringFunction_firDecimatorPart/fir_decimate.c b/examples/dsp/FilteringFunction_firDecimatorPart/fir_decimate.c new file mode 100644 index 00000000..b3a86402 --- /dev/null +++ b/examples/dsp/FilteringFunction_firDecimatorPart/fir_decimate.c @@ -0,0 +1,362 @@ +#include "ref.h" + +void ref_fir_decimate_f32(const riscv_fir_decimate_instance_f32 *S, + float32_t *pSrc, float32_t *pDst, uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *pStateCurnt; /* Points to the current sample of the state */ + float32_t sum0; /* Accumulator */ + float32_t x0, + c0; /* Temporary variables to hold state and coefficient values */ + uint32_t numTaps = + S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i, blkCnt; /* Loop counters */ + + /* S->pState buffer contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be + * written */ + pStateCurnt = S->pState + numTaps - 1U; + + /* Total number of output samples to be computed */ + blkCnt = blockSize / S->M; + + while (blkCnt > 0U) { + /* Copy decimation factor number of new input samples into the state + * buffer */ + i = S->M; + + do { + *pStateCurnt++ = *pSrc++; + } while (--i); + + /* Set accumulator to zero */ + sum0 = 0.0f; + + for (i = 0; i < numTaps; i++) { + /* Read coefficients */ + c0 = pCoeffs[i]; + + /* Fetch 1 state variable */ + x0 = pState[i]; + + /* Perform the multiply-accumulate */ + sum0 += x0 * c0; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState += S->M; + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst++ = sum0; + + /* Decrement the loop counter */ + blkCnt--; + } + /* Processing is complete. + ** Now copy the last numTaps - 1 samples to the start of the state buffer. + ** This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + + /* Copy numTaps number of values */ + i = numTaps - 1U; + + /* copy data */ + while (i > 0U) { + *pStateCurnt++ = *pState++; + + /* Decrement the loop counter */ + i--; + } +} + +void ref_fir_decimate_q31(const riscv_fir_decimate_instance_q31 *S, q31_t *pSrc, + q31_t *pDst, uint32_t blockSize) +{ + q31_t *pState = S->pState; /* State pointer */ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *pStateCurnt; /* Points to the current sample of the state */ + q31_t x0, c0; /* Temporary variables to hold state and coefficient values */ + q63_t sum0; /* Accumulator */ + uint32_t numTaps = S->numTaps; /* Number of taps */ + uint32_t i, blkCnt; /* Loop counters */ + + /* S->pState buffer contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be + * written */ + pStateCurnt = S->pState + numTaps - 1U; + + /* Total number of output samples to be computed */ + blkCnt = blockSize / S->M; + + while (blkCnt > 0U) { + /* Copy decimation factor number of new input samples into the state + * buffer */ + i = S->M; + + do { + *pStateCurnt++ = *pSrc++; + + } while (--i); + + /* Set accumulator to zero */ + sum0 = 0; + + for (i = 0; i < numTaps; i++) { + /* Read coefficients */ + c0 = pCoeffs[i]; + + /* Fetch 1 state variable */ + x0 = pState[i]; + + /* Perform the multiply-accumulate */ + sum0 += (q63_t)x0 * c0; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + S->M; + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst++ = (q31_t)(sum0 >> 31); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Processing is complete. + ** Now copy the last numTaps - 1 samples to the start of the state buffer. + ** This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + + i = numTaps - 1U; + + /* copy data */ + while (i > 0U) { + *pStateCurnt++ = *pState++; + + /* Decrement the loop counter */ + i--; + } +} + +void ref_fir_decimate_fast_q31(const riscv_fir_decimate_instance_q31 *S, + q31_t *pSrc, q31_t *pDst, uint32_t blockSize) +{ + q31_t *pState = S->pState; /* State pointer */ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *pStateCurnt; /* Points to the current sample of the state */ + q31_t x0, c0; /* Temporary variables to hold state and coefficient values */ + q31_t sum0; /* Accumulator */ + uint32_t numTaps = S->numTaps; /* Number of taps */ + uint32_t i, blkCnt; /* Loop counters */ + + /* S->pState buffer contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be + * written */ + pStateCurnt = S->pState + numTaps - 1U; + + /* Total number of output samples to be computed */ + blkCnt = blockSize / S->M; + + while (blkCnt > 0U) { + /* Copy decimation factor number of new input samples into the state + * buffer */ + i = S->M; + + do { + *pStateCurnt++ = *pSrc++; + + } while (--i); + + /* Set accumulator to zero */ + sum0 = 0; + + for (i = 0; i < numTaps; i++) { + /* Read coefficients */ + c0 = pCoeffs[i]; + + /* Fetch 1 state variable */ + x0 = pState[i]; + + /* Perform the multiply-accumulate */ + sum0 = (q31_t)((((q63_t)sum0 << 32) + ((q63_t)x0 * c0)) >> 32); + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + S->M; + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst++ = (q31_t)(sum0 << 1); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Processing is complete. + ** Now copy the last numTaps - 1 samples to the start of the state buffer. + ** This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + + i = numTaps - 1U; + + /* copy data */ + while (i > 0U) { + *pStateCurnt++ = *pState++; + + /* Decrement the loop counter */ + i--; + } +} + +void ref_fir_decimate_q15(const riscv_fir_decimate_instance_q15 *S, q15_t *pSrc, + q15_t *pDst, uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCurnt; /* Points to the current sample of the state */ + q31_t x0, c0; /* Temporary variables to hold state and coefficient values */ + q63_t sum0; /* Accumulator */ + uint32_t numTaps = S->numTaps; /* Number of taps */ + uint32_t i, blkCnt; /* Loop counters */ + + /* S->pState buffer contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be + * written */ + pStateCurnt = S->pState + numTaps - 1U; + + /* Total number of output samples to be computed */ + blkCnt = blockSize / S->M; + + while (blkCnt > 0U) { + /* Copy decimation factor number of new input samples into the state + * buffer */ + i = S->M; + + do { + *pStateCurnt++ = *pSrc++; + + } while (--i); + + /* Set accumulator to zero */ + sum0 = 0; + + for (i = 0; i < numTaps; i++) { + /* Read coefficients */ + c0 = pCoeffs[i]; + + /* Fetch 1 state variable */ + x0 = pState[i]; + + /* Perform the multiply-accumulate */ + sum0 += (q31_t)x0 * c0; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + S->M; + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst++ = ref_sat_q15(sum0 >> 15); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Processing is complete. + ** Now copy the last numTaps - 1 samples to the start of the state buffer. + ** This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + + i = numTaps - 1U; + + /* copy data */ + while (i > 0U) { + *pStateCurnt++ = *pState++; + + /* Decrement the loop counter */ + i--; + } +} + +void ref_fir_decimate_fast_q15(const riscv_fir_decimate_instance_q15 *S, + q15_t *pSrc, q15_t *pDst, uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCurnt; /* Points to the current sample of the state */ + q15_t x0, c0; /* Temporary variables to hold state and coefficient values */ + q31_t sum0; /* Accumulator */ + uint32_t numTaps = S->numTaps; /* Number of taps */ + uint32_t i, blkCnt; /* Loop counters */ + + /* S->pState buffer contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be + * written */ + pStateCurnt = S->pState + numTaps - 1U; + + /* Total number of output samples to be computed */ + blkCnt = blockSize / S->M; + + while (blkCnt > 0U) { + /* Copy decimation factor number of new input samples into the state + * buffer */ + i = S->M; + + do { + *pStateCurnt++ = *pSrc++; + + } while (--i); + + /* Set accumulator to zero */ + sum0 = 0; + + for (i = 0; i < numTaps; i++) { + /* Read coefficients */ + c0 = pCoeffs[i]; + + /* Fetch 1 state variable */ + x0 = pState[i]; + + /* Perform the multiply-accumulate */ + sum0 += x0 * c0; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + S->M; + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst++ = ref_sat_q15(sum0 >> 15); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Processing is complete. + ** Now copy the last numTaps - 1 samples to the start of the state buffer. + ** This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + + i = numTaps - 1U; + + /* copy data */ + while (i > 0U) { + *pStateCurnt++ = *pState++; + + /* Decrement the loop counter */ + i--; + } +} diff --git a/examples/dsp/FilteringFunction_firDecimatorPart/main.c b/examples/dsp/FilteringFunction_firDecimatorPart/main.c new file mode 100644 index 00000000..08a11739 --- /dev/null +++ b/examples/dsp/FilteringFunction_firDecimatorPart/main.c @@ -0,0 +1,245 @@ +// +// Created by lujun on 19-6-28. +// +// This contains fir, iir and lms filters +// each one has it's own function. +// All function can be found in main function. +// If you don't want to use it, then comment it. +// +// This part only tests result after 50 dots.If you want to test results' all +// dots, please define WITH_FRONT +// +// If there are too much numbers which makes it hard to read,in VScode you can +// press alt and z can shrimp them to one line +// +// You MUST be careful about overflow. +#include "riscv_math.h" +#include "array.h" +#include +#include "../common.h" + +#include "../HelperFunctions/math_helper.c" +#include "../HelperFunctions/ref_helper.c" + +#include +#define DELTAF32 (0.05f) +#define DELTAQ31 (63) +#define DELTAQ15 (1) +#define DELTAQ7 (1) +#define SNR_THRESHOLD_F32 (80.0f) + +int test_flag_error = 0; + +// #define WITH_FRONT + +//*************************************************************************************** +// fir Decimator +//*************************************************************************************** +static void riscv_fir_decimate_f32_lp(void) +{ + uint32_t i; + /* clang-format off */ + riscv_fir_decimate_instance_f32 S; + /* clang-format on */ + riscv_fir_decimate_init_f32(&S, NUM_TAPS, 2, &firCoeffs32LP[0], &firStatef32[0], + TEST_LENGTH_SAMPLES); + BENCH_START(riscv_fir_decimate_f32); + riscv_fir_decimate_f32(&S, &testInput_f32_50Hz_200Hz, &testOutput_f32, TEST_LENGTH_SAMPLES); + BENCH_END(riscv_fir_decimate_f32); + riscv_fir_decimate_init_f32(&S, NUM_TAPS, 2, &firCoeffs32LP[0], &firStatef32[0], + TEST_LENGTH_SAMPLES); + ref_fir_decimate_f32(&S, &testInput_f32_50Hz_200Hz, &testOutput_f32_ref, TEST_LENGTH_SAMPLES); +#ifndef WITH_FRONT + float snr = riscv_snr_f32(&testOutput_f32_ref[60], &testOutput_f32[60], 100); + if (snr < SNR_THRESHOLD_F32) { + BENCH_ERROR(riscv_fir_decimate_f32); + printf("f32 fir_decimate failed with snr:%f\n", snr); + test_flag_error = 1; + } + BENCH_STATUS(riscv_fir_decimate_f32); +#else + float snr = + riscv_snr_f32(&testOutput_f32_ref[0], &testOutput_f32[0], TEST_LENGTH_SAMPLES/2); + if (snr < SNR_THRESHOLD_F32) { + BENCH_ERROR(riscv_fir_decimate_f32); + printf("f32 fir_decimate failed with snr:%f\n", snr); + test_flag_error = 1; + } + BENCH_STATUS(riscv_fir_decimate_f32); +#endif +} +static void riscv_fir_decimate_q31_lp(void) +{ + uint32_t i; + /* clang-format off */ + riscv_fir_decimate_instance_q31 S; + + /* clang-format on */ + riscv_float_to_q31(testInput_f32_50Hz_200Hz, testInput_q31_50Hz_200Hz, TEST_LENGTH_SAMPLES); + riscv_float_to_q31(firCoeffs32LP, firCoeffs32LP_q31, NUM_TAPS); + riscv_fir_decimate_init_q31(&S, NUM_TAPS, 2, &firCoeffs32LP_q31[0], &firStateq31[0], + TEST_LENGTH_SAMPLES); + BENCH_START(riscv_fir_decimate_q31); + riscv_fir_decimate_q31(&S, testInput_q31_50Hz_200Hz, testOutput_q31, TEST_LENGTH_SAMPLES); + BENCH_END(riscv_fir_decimate_q31); + riscv_fir_decimate_init_q31(&S, NUM_TAPS, 2, &firCoeffs32LP_q31[0], &firStateq31[0], + TEST_LENGTH_SAMPLES); + ref_fir_decimate_q31(&S, testInput_q31_50Hz_200Hz, testOutput_q31_ref, TEST_LENGTH_SAMPLES); + riscv_q31_to_float(testOutput_q31, testOutput_f32, TEST_LENGTH_SAMPLES); + riscv_q31_to_float(testOutput_q31_ref, testOutput_f32_ref, TEST_LENGTH_SAMPLES); +#ifndef WITH_FRONT + float snr = riscv_snr_f32(&testOutput_f32_ref[50], &testOutput_f32[50], 100); + + if (snr < SNR_THRESHOLD_F32) { + BENCH_ERROR(riscv_fir_decimate_q31); + printf("q31 fir_decimate failed with snr:%f\n", snr); + test_flag_error = 1; + } + BENCH_STATUS(riscv_fir_decimate_q31); +#else + float snr = riscv_snr_f32(&testOutput_f32_ref[0], &testOutput_f32[0], + TEST_LENGTH_SAMPLES/2; + + if (snr < SNR_THRESHOLD_F32) { + BENCH_ERROR(riscv_fir_decimate_q31); + printf("q31 fir_decimate failed with snr:%f\n", snr); + test_flag_error = 1; + } + BENCH_STATUS(riscv_fir_decimate_q31); +#endif +} +static void riscv_fir_decimate_q15_lp(void) +{ + uint32_t i; + /* clang-format off */ + riscv_fir_decimate_instance_q15 S; + /* clang-format on */ + riscv_float_to_q15(testInput_f32_50Hz_200Hz, testInput_q15_50Hz_200Hz, TEST_LENGTH_SAMPLES); + riscv_float_to_q15(firCoeffs32LP, firCoeffs32LP_q15, NUM_TAPS); + riscv_fir_decimate_init_q15(&S, NUM_TAPS, 2, &firCoeffs32LP_q15[0], &firStateq15[0], + TEST_LENGTH_SAMPLES); + BENCH_START(riscv_fir_decimate_q15); + riscv_fir_decimate_q15(&S, testInput_q15_50Hz_200Hz, testOutput_q15, TEST_LENGTH_SAMPLES); + BENCH_END(riscv_fir_decimate_q15); + riscv_fir_decimate_init_q15(&S, NUM_TAPS, 2, &firCoeffs32LP_q15[0], &firStateq15[0], + TEST_LENGTH_SAMPLES); + ref_fir_decimate_q15(&S, testInput_q15_50Hz_200Hz, testOutput_q15_ref, TEST_LENGTH_SAMPLES); + riscv_q15_to_float(testOutput_q15, testOutput_f32, TEST_LENGTH_SAMPLES); + riscv_q15_to_float(testOutput_q15_ref, testOutput_f32_ref, TEST_LENGTH_SAMPLES); +#ifndef WITH_FRONT + float snr = riscv_snr_f32(&testOutput_f32_ref[50], &testOutput_f32[50], 100); + + if (snr < SNR_THRESHOLD_F32) { + BENCH_ERROR(riscv_fir_decimate_q15); + printf("q15 fir_decimate failed with snr:%f\n", snr); + test_flag_error = 1; + } + BENCH_STATUS(riscv_fir_decimate_q15); +#else + float snr = riscv_snr_f32(&testOutput_f32_ref[0], &testOutput_f32[0], + TEST_LENGTH_SAMPLES/2); + + if (snr < SNR_THRESHOLD_F32) { + BENCH_ERROR(riscv_fir_decimate_q15); + printf("q15 fir_decimate failed with snr:%f\n", snr); + test_flag_error = 1; + } + BENCH_STATUS(riscv_fir_decimate_q15); +#endif +} +static void riscv_fir_decimate_fast_q31_lp(void) +{ + uint32_t i; + /* clang-format off */ + riscv_fir_decimate_instance_q31 S; + /* clang-format on */ + riscv_float_to_q31(testInput_f32_50Hz_200Hz, testInput_q31_50Hz_200Hz, TEST_LENGTH_SAMPLES); + riscv_float_to_q31(firCoeffs32LP, firCoeffs32LP_q31, NUM_TAPS); + riscv_fir_decimate_init_q31(&S, NUM_TAPS, 2, &firCoeffs32LP_q31[0], &firStateq31[0], + TEST_LENGTH_SAMPLES); + BENCH_START(riscv_fir_decimate_fast_q31); + riscv_fir_decimate_fast_q31(&S, testInput_q31_50Hz_200Hz, testOutput_q31, TEST_LENGTH_SAMPLES); + BENCH_END(riscv_fir_decimate_fast_q31); + riscv_fir_decimate_init_q31(&S, NUM_TAPS, 2, &firCoeffs32LP_q31[0], &firStateq31[0], + TEST_LENGTH_SAMPLES); + ref_fir_decimate_fast_q31(&S, testInput_q31_50Hz_200Hz, testOutput_q31_ref, TEST_LENGTH_SAMPLES); + riscv_q31_to_float(testOutput_q31, testOutput_f32, TEST_LENGTH_SAMPLES); + riscv_q31_to_float(testOutput_q31_ref, testOutput_f32_ref, TEST_LENGTH_SAMPLES); +#ifndef WITH_FRONT + float snr = riscv_snr_f32(&testOutput_f32_ref[50], &testOutput_f32[50], 100); + + if (snr < SNR_THRESHOLD_F32) { + BENCH_ERROR(riscv_fir_decimate_fast_q31); + printf("q31 fir_decimate_fast failed with snr:%f\n", snr); + test_flag_error = 1; + } + BENCH_STATUS(riscv_fir_decimate_fast_q31); +#else + float snr = riscv_snr_f32(&testOutput_f32_ref[0], &testOutput_f32[0], + TEST_LENGTH_SAMPLES/2); + + if (snr < SNR_THRESHOLD_F32) { + BENCH_ERROR(riscv_fir_decimate_fast_q31); + printf("q31 fir_decimate_fast failed with snr:%f\n", snr); + test_flag_error = 1; + } + BENCH_STATUS(riscv_fir_decimate_fast_q31); +#endif +} +static void riscv_fir_decimate_fast_q15_lp(void) +{ + uint32_t i; + /* clang-format off */ + riscv_fir_decimate_instance_q15 S; + riscv_scale_f32(testInput_f32_50Hz_200Hz,0.001,testInput_f32_50Hz_200Hz,TEST_LENGTH_SAMPLES); + riscv_float_to_q15(testInput_f32_50Hz_200Hz, testInput_q15_50Hz_200Hz, TEST_LENGTH_SAMPLES); + riscv_float_to_q15(firCoeffs32LP, firCoeffs32LP_q15, NUM_TAPS); + riscv_fir_decimate_init_q15(&S, NUM_TAPS, 2, &firCoeffs32LP_q15[0], &firStateq15[0], TEST_LENGTH_SAMPLES); + /* clang-format on */ + BENCH_START(riscv_fir_decimate_fast_q15); + riscv_fir_decimate_fast_q15(&S, testInput_q15_50Hz_200Hz, testOutput_q15, TEST_LENGTH_SAMPLES); + BENCH_END(riscv_fir_decimate_fast_q15); + riscv_fir_decimate_init_q15(&S, NUM_TAPS, 2, &firCoeffs32LP_q15[0], &firStateq15[0], + TEST_LENGTH_SAMPLES); + ref_fir_decimate_fast_q15(&S, testInput_q15_50Hz_200Hz, testOutput_q15_ref, TEST_LENGTH_SAMPLES); + riscv_q15_to_float(testOutput_q15, testOutput_f32, TEST_LENGTH_SAMPLES); + riscv_q15_to_float(testOutput_q15_ref, testOutput_f32_ref, TEST_LENGTH_SAMPLES); +#ifndef WITH_FRONT + float snr = riscv_snr_f32(&testOutput_f32_ref[50], &testOutput_f32[50], 100); + + if (snr < SNR_THRESHOLD_F32) { + BENCH_ERROR(riscv_fir_decimate_fast_q15); + printf("q15 fir_decimate_fast failed with snr:%f\n", snr); + test_flag_error = 1; + } + BENCH_STATUS(riscv_fir_decimate_fast_q15); +#else + float snr = riscv_snr_f32(&testOutput_f32_ref[0], &testOutput_f32[0], + TEST_LENGTH_SAMPLES/2); + + if (snr < SNR_THRESHOLD_F32) { + BENCH_ERROR(riscv_fir_decimate_fast_q15); + printf("q15 fir_decimate_fast failed with snr:%f\n", snr); + test_flag_error = 1; + } + BENCH_STATUS(riscv_fir_decimate_fast_q15); +#endif +} + +int main() +{ + BENCH_INIT; + riscv_fir_decimate_f32_lp(); + riscv_fir_decimate_q31_lp(); + riscv_fir_decimate_q15_lp(); + riscv_fir_decimate_fast_q31_lp(); + riscv_fir_decimate_fast_q15_lp(); + BENCH_FINISH; + if (test_flag_error) { + printf("test error apprears, please recheck.\n"); + return 1; + } else { + printf("all test are passed. Well done!\n"); + } + return 0; +} diff --git a/examples/dsp/FilteringFunction_firInterpolatePart/CMakeLists.txt b/examples/dsp/FilteringFunction_firInterpolatePart/CMakeLists.txt new file mode 100644 index 00000000..53a5a8cd --- /dev/null +++ b/examples/dsp/FilteringFunction_firInterpolatePart/CMakeLists.txt @@ -0,0 +1,5 @@ +set(TARGET_REQUIRED_PRIVATE_INCLUDE ${CMAKE_CURRENT_SOURCE_DIR} ${CMAKE_CURRENT_SOURCE_DIR}/..) +set(TARGET_REQUIRED_SRCS fir_interpolate.c) +set(TARGET_REQUIRED_LIBS nmsis) +set(mains main.c) +generate_bin() \ No newline at end of file diff --git a/examples/dsp/FilteringFunction_firInterpolatePart/array.h b/examples/dsp/FilteringFunction_firInterpolatePart/array.h new file mode 100644 index 00000000..760e0b8d --- /dev/null +++ b/examples/dsp/FilteringFunction_firInterpolatePart/array.h @@ -0,0 +1,25 @@ +// Array for FilteringFunctions firInterpolatePart +#define TEST_LENGTH_SAMPLES 320 /* ???? */ +#define NUM_TAPS 30 /* must be multply of L */ + +const float32_t firCoeffs32LP[NUM_TAPS] = { + -0.001822523074f, -0.001587929321f, 1.226008847e-18f, 0.003697750857f, 0.008075430058f, + 0.008530221879f, -4.273456581e-18f, -0.01739769801f, -0.03414586186f, -0.03335915506f, + 8.073562366e-18f, 0.06763084233f, 0.1522061825f, 0.2229246944f, 0.2504960895f, + 0.2229246944f, 0.1522061825f, 0.06763084233f, 8.073562366e-18f, -0.03335915506f, + -0.03414586186f, -0.01739769801f, -4.273456581e-18f, 0.008530221879f, 0.008075430058f, + 0.003697750857f, 1.226008847e-18f, -0.001587929321f, -0.001822523074f}; +// float32_t + float32_t testOutput_f32[TEST_LENGTH_SAMPLES*2],testOutput_f32_ref[TEST_LENGTH_SAMPLES*2]; + float32_t firStatef32[TEST_LENGTH_SAMPLES + NUM_TAPS/2 - 1]={0}; + float32_t testInput_f32_50Hz_200Hz[TEST_LENGTH_SAMPLES] = {0, 1.26007351067010, 1.17557050458495, 0.221231742082474, -1.11022302462516e-16, 1.00000000000000, 1.90211303259031, 1.39680224666742, 4.44089209850063e-16, -0.642039521920206, -3.67394039744206e-16, 0.642039521920206, -1.22124532708767e-15, -1.39680224666742, -1.90211303259031, -1.00000000000000, -3.33066907387547e-16, -0.221231742082476, -1.17557050458495, -1.26007351067010, -1.22464679914735e-15, 1.26007351067010, 1.17557050458495, 0.221231742082475, 8.88178419700125e-16, 1.00000000000000, 1.90211303259031, 1.39680224666742, 1.33226762955019e-15, -0.642039521920206, -1.10218211923262e-15, 0.642039521920206, 1.55431223447522e-15, -1.39680224666743, -1.90211303259031, -0.999999999999995, -7.77156117237610e-16, -0.221231742082473, -1.17557050458495, -1.26007351067010, -2.44929359829471e-15, 1.26007351067010, 1.17557050458494, 0.221231742082476, -7.77156117237610e-16, 0.999999999999998, 1.90211303259031, 1.39680224666742, -4.88498130835069e-15, -0.642039521920206, 3.49210031947972e-15, 0.642039521920206, 2.55351295663786e-15, -1.39680224666742, -1.90211303259031, -0.999999999999996, -9.99200722162641e-16, -0.221231742082477, -1.17557050458494, -1.26007351067011, -3.67394039744206e-15, 1.26007351067010, 1.17557050458495, 0.221231742082472, -1.22124532708767e-15, 1.00000000000000, 1.90211303259031, 1.39680224666742, -1.09912079437891e-14, -0.642039521920206, 8.08638275819206e-15, 0.642039521920205, 3.55271367880050e-15, -1.39680224666741, -1.90211303259031, -0.999999999999997, -1.44328993201270e-15, -0.221231742082476, -1.17557050458494, -1.26007351067010, -4.89858719658941e-15, 1.26007351067010, 1.17557050458494, 0.221231742082472, 3.88578058618805e-15, 1.00000000000000, 1.90211303259031, 1.39680224666743, 4.44089209850063e-15, -0.642039521920207, -3.30654635769785e-15, 0.642039521920206, 4.55191440096314e-15, -1.39680224666742, -1.90211303259031, -0.999999999999998, 3.66373598126302e-15, -0.221231742082476, -1.17557050458495, -1.26007351067010, 1.16403343982657e-14, 1.26007351067010, 1.17557050458496, 0.221231742082482, -1.99840144432528e-15, 1.00000000000000, 1.90211303259031, 1.39680224666743, 5.44009282066327e-15, -0.642039521920206, 6.61680659921524e-15, 0.642039521920207, 5.55111512312578e-15, -1.39680224666742, -1.90211303259031, -0.999999999999984, -2.10942374678780e-15, -0.221231742082475, -1.17557050458493, -1.26007351067011, -7.34788079488412e-15, 1.26007351067010, 1.17557050458494, 0.221231742082483, -2.33146835171283e-15, 1.00000000000000, 1.90211303259031, 1.39680224666741, 6.32827124036339e-15, -0.642039521920206, 5.88201851972683e-15, 0.642039521920207, -2.22044604925031e-14, -1.39680224666742, -1.90211303259031, -0.999999999999985, 8.43769498715119e-15, -0.221231742082475, -1.17557050458495, -1.26007351067009, 2.69546091939735e-14, 1.26007351067009, 1.17557050458496, 0.221231742082484, -2.77555756156289e-15, 1, 1.90211303259030, 1.39680224666743, 7.32747196252603e-15, -0.642039521920206, 5.14723044023841e-15, 0.642039521920205, 7.54951656745106e-15, -1.39680224666742, -1.90211303259031, -0.999999999999986, -2.99760216648792e-15, -0.221231742082474, -1.17557050458495, -1.26007351067009, -9.79717439317883e-15, 1.26007351067010, 1.17557050458494, 0.221231742082465, 7.88258347483861e-15, 0.999999999999999, 1.90211303259031, 1.39680224666741, -2.04281036531029e-14, -0.642039521920204, 4.41244236075000e-15, 0.642039521920207, 8.43769498715119e-15, -1.39680224666742, -1.90211303259031, -1.00000000000002, -3.33066907387547e-15, -0.221231742082473, -1.17557050458493, -1.26007351067011, -1.10218211923262e-14, 1.26007351067010, 1.17557050458494, 0.221231742082485, -3.44169137633799e-15, 0.999999999999998, 1.90211303259031, 1.39680224666741, 9.32587340685132e-15, -0.642039521920206, 3.67765428126159e-15, 0.642039521920207, -1.93178806284777e-14, -1.39680224666742, -1.90211303259031, -0.999999999999988, 7.32747196252603e-15, -0.221231742082492, -1.17557050458495, -1.26007351067009, 2.32806687965315e-14, 1.26007351067012, 1.17557050458494, 0.221231742082467, -1.47659662275146e-14, 0.999999999999969, 1.90211303259030, 1.39680224666744, 1.02140518265514e-14, -0.642039521920206, 2.94286620177318e-15, 0.642039521920207, -1.83186799063151e-14, -1.39680224666739, -1.90211303259031, -1.00000000000002, -4.10782519111308e-15, -0.221231742082472, -1.17557050458495, -1.26007351067010, 2.20560219973841e-14, 1.26007351067011, 1.17557050458493, 0.221231742082486, -4.21884749357560e-15, 0.999999999999996, 1.90211303259031, 1.39680224666741, -1.75415237890775e-14, -0.642039521920204, 2.35243601950878e-14, 0.642039521920209, 1.15463194561016e-14, -1.39680224666742, -1.90211303259031, -0.999999999999990, -1.54321000422897e-14, -0.221231742082452, -1.17557050458493, -1.26007351067011, -1.46957615897682e-14, 1.26007351067010, 1.17557050458495, 0.221231742082468, 6.32827124036339e-15, 1.00000000000002, 1.90211303259030, 1.39680224666744, 1.23234755733392e-14, -0.642039521920207, 1.47329004279635e-15, 0.642039521920207, -1.62092561595273e-14, -1.39680224666744, -1.90211303259030, -1.00000000000002, -4.88498130835069e-15, -0.221231742082471, -1.17557050458495, -1.26007351067010, 1.96067283990894e-14, 1.26007351067011, 1.17557050458493, 0.221231742082450, 1.69864122767649e-14, 0.999999999999994, 1.90211303259031, 1.39680224666741, -1.54321000422897e-14, -0.642039521920205, 2.20547840361110e-14, 0.642039521920209, -4.39648317751562e-14, -1.39680224666747, -1.90211303259031, -0.999999999999992, 5.77315972805081e-15, -0.221231742082489, -1.17557050458496, -1.26007351067008, 5.39092183879471e-14, 1.26007351067013, 1.17557050458498, 0.221231742082507, -1.63202784619898e-14, 0.999999999999965, 1.90211303259030, 1.39680224666744, 1.43218770176645e-14, -0.642039521920207, 3.71388381953015e-18, 0.642039521920203, 4.31876756579186e-14, -1.39680224666739, -1.90211303259031, -1.00000000000002, -5.55111512312578e-15, -0.221231742082469, -1.17557050458495, -1.26007351067010, 1.71574348007947e-14, 1.26007351067008, 1.17557050458496, 0.221231742082489, -5.77315972805081e-15, 0.999999999999992, 1.90211303259031, 1.39680224666741, -1.34336985979644e-14, -0.642039521920205, 2.05852078771341e-14, 0.642039521920205, 1.54321000422897e-14, -1.39680224666741, -1.90211303259031, -0.999999999999994, 4.99600361081320e-15, -0.221231742082488, -1.17557050458496, -1.26007351067008}; + +//q31_t + q31_t firStateq31[TEST_LENGTH_SAMPLES + NUM_TAPS/2 - 1]; + q31_t testInput_q31_50Hz_200Hz[TEST_LENGTH_SAMPLES] = {0}, testOutput_q31[TEST_LENGTH_SAMPLES*2] = {0},testOutput_q31_ref[TEST_LENGTH_SAMPLES*2] = {0}; + q31_t firCoeffs32LP_q31[NUM_TAPS] = {0}; + +//q15_t + q15_t firStateq15[TEST_LENGTH_SAMPLES + NUM_TAPS/2 - 1]; + q15_t testInput_q15_50Hz_200Hz[TEST_LENGTH_SAMPLES] = {0}, testOutput_q15[TEST_LENGTH_SAMPLES*2] = {0},testOutput_q15_ref[TEST_LENGTH_SAMPLES*2] = {0}; + q15_t firCoeffs32LP_q15[NUM_TAPS] = {0}; \ No newline at end of file diff --git a/examples/dsp/FilteringFunction_firInterpolatePart/fir_interpolate.c b/examples/dsp/FilteringFunction_firInterpolatePart/fir_interpolate.c new file mode 100644 index 00000000..017b4efc --- /dev/null +++ b/examples/dsp/FilteringFunction_firInterpolatePart/fir_interpolate.c @@ -0,0 +1,277 @@ +#include "ref.h" + +void ref_fir_interpolate_f32(const riscv_fir_interpolate_instance_f32 *S, + float32_t *pSrc, float32_t *pDst, + uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *pStateCurnt; /* Points to the current sample of the state */ + float32_t *ptr1; /* Temporary pointer for state buffer */ + const float32_t *ptr2; /* Temporary pointer for coefficient buffer */ + float32_t sum; /* Accumulator */ + uint32_t i, blkCnt; /* Loop counters */ + uint16_t phaseLen = S->phaseLength, + tapCnt; /* Length of each polyphase filter component */ + + /* S->pState buffer contains previous frame (phaseLen - 1) samples */ + /* pStateCurnt points to the location where the new input data should be + * written */ + pStateCurnt = S->pState + phaseLen - 1; + + /* Total number of intput samples */ + blkCnt = blockSize; + + /* Loop over the blockSize. */ + while (blkCnt > 0U) { + /* Copy new input sample into the state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Loop over the Interpolation factor. */ + i = S->L; + + while (i > 0U) { + /* Set accumulator to zero */ + sum = 0.0f; + + /* Initialize state pointer */ + ptr1 = pState; + + /* Initialize coefficient pointer */ + ptr2 = pCoeffs + i - 1; + + /* Loop over the polyPhase length */ + tapCnt = phaseLen; + + while (tapCnt > 0U) { + /* Perform the multiply-accumulate */ + sum += *ptr1++ * *ptr2; + + /* Increment the coefficient pointer by interpolation factor + * times. */ + ptr2 += S->L; + + /* Decrement the loop counter */ + tapCnt--; + } + + /* The result is in the accumulator, store in the destination + * buffer. */ + *pDst++ = sum; + + /* Decrement the loop counter */ + i--; + } + + /* Advance the state pointer by 1 + * to process the next group of interpolation factor number samples */ + pState = pState + 1; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Processing is complete. + ** Now copy the last phaseLen - 1 samples to the start of the state buffer. + ** This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + + tapCnt = phaseLen - 1U; + + while (tapCnt > 0U) { + *pStateCurnt++ = *pState++; + + /* Decrement the loop counter */ + tapCnt--; + } +} + +void ref_fir_interpolate_q31(const riscv_fir_interpolate_instance_q31 *S, + q31_t *pSrc, q31_t *pDst, uint32_t blockSize) +{ + q31_t *pState = S->pState; /* State pointer */ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *pStateCurnt; /* Points to the current sample of the state */ + q31_t *ptr1; /* Temporary pointer for state buffer */ + const q31_t *ptr2; /* Temporary pointer for coefficient buffer */ + q63_t sum; /* Accumulator */ + q31_t x0, c0; /* Temporary variables to hold state and coefficient values */ + uint32_t i, blkCnt; /* Loop counters */ + uint16_t phaseLen = S->phaseLength, + tapCnt; /* Length of each polyphase filter component */ + + /* S->pState buffer contains previous frame (phaseLen - 1) samples */ + /* pStateCurnt points to the location where the new input data should be + * written */ + pStateCurnt = S->pState + (q31_t)phaseLen - 1; + + /* Total number of intput samples */ + blkCnt = blockSize; + + /* Loop over the blockSize. */ + while (blkCnt > 0U) { + /* Copy new input sample into the state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Loop over the Interpolation factor. */ + i = S->L; + + while (i > 0U) { + /* Set accumulator to zero */ + sum = 0; + + /* Initialize state pointer */ + ptr1 = pState; + + /* Initialize coefficient pointer */ + ptr2 = pCoeffs + i - 1; + + tapCnt = phaseLen; + + while (tapCnt > 0U) { + /* Read the coefficient */ + c0 = *(ptr2); + + /* Increment the coefficient pointer by interpolation factor + * times. */ + ptr2 += S->L; + + /* Read the input sample */ + x0 = *ptr1++; + + /* Perform the multiply-accumulate */ + sum += (q63_t)x0 * c0; + + /* Decrement the loop counter */ + tapCnt--; + } + + /* The result is in the accumulator, store in the destination + * buffer. */ + *pDst++ = (q31_t)(sum >> 31); + + /* Decrement the loop counter */ + i--; + } + + /* Advance the state pointer by 1 + * to process the next group of interpolation factor number samples */ + pState = pState + 1; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Processing is complete. + ** Now copy the last phaseLen - 1 samples to the satrt of the state buffer. + ** This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + + tapCnt = phaseLen - 1U; + + /* copy data */ + while (tapCnt > 0U) { + *pStateCurnt++ = *pState++; + + /* Decrement the loop counter */ + tapCnt--; + } +} + +void ref_fir_interpolate_q15(const riscv_fir_interpolate_instance_q15 *S, + q15_t *pSrc, q15_t *pDst, uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCurnt; /* Points to the current sample of the state */ + q15_t *ptr1; /* Temporary pointer for state buffer */ + const q15_t *ptr2; /* Temporary pointer for coefficient buffer */ + q63_t sum; /* Accumulator */ + q15_t x0, c0; /* Temporary variables to hold state and coefficient values */ + uint32_t i, blkCnt, tapCnt; /* Loop counters */ + uint16_t phaseLen = + S->phaseLength; /* Length of each polyphase filter component */ + + /* S->pState buffer contains previous frame (phaseLen - 1) samples */ + /* pStateCurnt points to the location where the new input data should be + * written */ + pStateCurnt = S->pState + phaseLen - 1; + + /* Total number of intput samples */ + blkCnt = blockSize; + + /* Loop over the blockSize. */ + while (blkCnt > 0U) { + /* Copy new input sample into the state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Loop over the Interpolation factor. */ + i = S->L; + + while (i > 0U) { + /* Set accumulator to zero */ + sum = 0; + + /* Initialize state pointer */ + ptr1 = pState; + + /* Initialize coefficient pointer */ + ptr2 = pCoeffs + i - 1; + + /* Loop over the polyPhase length */ + tapCnt = (uint32_t)phaseLen; + + while (tapCnt > 0U) { + /* Read the coefficient */ + c0 = *ptr2; + + /* Increment the coefficient pointer by interpolation factor + * times. */ + ptr2 += S->L; + + /* Read the input sample */ + x0 = *ptr1++; + + /* Perform the multiply-accumulate */ + sum += (q31_t)x0 * c0; + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Store the result after converting to 1.15 format in the + * destination buffer */ + *pDst++ = ref_sat_q15(sum >> 15); + + /* Decrement the loop counter */ + i--; + } + + /* Advance the state pointer by 1 + * to process the next group of interpolation factor number samples */ + pState = pState + 1; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Processing is complete. + ** Now copy the last phaseLen - 1 samples to the start of the state buffer. + ** This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + + i = (uint32_t)phaseLen - 1U; + + while (i > 0U) { + *pStateCurnt++ = *pState++; + + /* Decrement the loop counter */ + i--; + } +} diff --git a/examples/dsp/FilteringFunction_firInterpolatePart/main.c b/examples/dsp/FilteringFunction_firInterpolatePart/main.c new file mode 100644 index 00000000..89b6813b --- /dev/null +++ b/examples/dsp/FilteringFunction_firInterpolatePart/main.c @@ -0,0 +1,169 @@ +// +// Created by lujun on 19-6-28. +// +// This contains fir, iir and lms filters +// each one has it's own function. +// All function can be found in main function. +// If you don't want to use it, then comment it. +// +// This part only tests result after 50 dots.If you want to test results' all +// dots, please define WITH_FRONT +// +// If there are too much numbers which makes it hard to read,in VScode you can +// press alt and z can shrimp them to one line +// +// You MUST be careful about overflow. +#include "riscv_math.h" +#include "array.h" +#include +#include "../common.h" + +#include "../HelperFunctions/math_helper.c" +#include "../HelperFunctions/ref_helper.c" + +#include +#define DELTAF32 (0.05f) +#define DELTAQ31 (63) +#define DELTAQ15 (1) +#define DELTAQ7 (1) +#define SNR_THRESHOLD_F32 (80.0f) + +int test_flag_error = 0; + +// #define WITH_FRONT + + +//*************************************************************************************** +// fir Interpolator +//*************************************************************************************** +static void riscv_fir_interpolate_f32_lp(void) +{ + /* clang-format off */ + riscv_fir_interpolate_instance_f32 S; + /* clang-format on */ + riscv_fir_interpolate_init_f32(&S, 2, NUM_TAPS, &firCoeffs32LP[0], &firStatef32[0], + TEST_LENGTH_SAMPLES); + BENCH_START(riscv_fir_interpolate_f32); + riscv_fir_interpolate_f32(&S, testInput_f32_50Hz_200Hz, + testOutput_f32, TEST_LENGTH_SAMPLES); + BENCH_END(riscv_fir_interpolate_f32); + riscv_fir_interpolate_init_f32(&S, 2, NUM_TAPS, &firCoeffs32LP[0], &firStatef32[0], + TEST_LENGTH_SAMPLES); + ref_fir_interpolate_f32(&S, testInput_f32_50Hz_200Hz, + testOutput_f32_ref, TEST_LENGTH_SAMPLES); +#ifndef WITH_FRONT + float snr = riscv_snr_f32(&testOutput_f32_ref[50], &testOutput_f32[50], 269); + + if (snr < SNR_THRESHOLD_F32) { + BENCH_ERROR(riscv_fir_interpolate_f32); + printf("f32 fir_interpolate failed with snr:%f\n", snr); + test_flag_error = 1; + } + BENCH_STATUS(riscv_fir_interpolate_f32); +#else + float snr = + riscv_snr_f32(&testOutput_f32_ref[0], &testOutput_f32[0], TEST_LENGTH_SAMPLES*2); + + if (snr < SNR_THRESHOLD_F32) { + BENCH_ERROR(riscv_fir_interpolate_f32); + printf("f32 fir_interpolate failed with snr:%f\n", snr); + test_flag_error = 1; + } + BENCH_STATUS(riscv_fir_interpolate_f32); +#endif +} +static void riscv_fir_interpolate_q31_lp(void) +{ + /* clang-format off */ + riscv_fir_interpolate_instance_q31 S; + /* clang-format on */ + riscv_float_to_q31(testInput_f32_50Hz_200Hz, testInput_q31_50Hz_200Hz, TEST_LENGTH_SAMPLES); + riscv_float_to_q31(firCoeffs32LP, firCoeffs32LP_q31, NUM_TAPS); + riscv_fir_interpolate_init_q31(&S, 2, NUM_TAPS, &firCoeffs32LP_q31[0], + &firStateq31[0], TEST_LENGTH_SAMPLES); + BENCH_START(riscv_fir_interpolate_q31); + riscv_fir_interpolate_q31(&S, testInput_q31_50Hz_200Hz, testOutput_q31, TEST_LENGTH_SAMPLES); + BENCH_END(riscv_fir_interpolate_q31); + riscv_fir_interpolate_init_q31(&S, 2, NUM_TAPS, &firCoeffs32LP_q31[0], + &firStateq31[0], TEST_LENGTH_SAMPLES); + ref_fir_interpolate_q31(&S, testInput_q31_50Hz_200Hz,testOutput_q31_ref, TEST_LENGTH_SAMPLES); + riscv_q31_to_float(testOutput_q31, testOutput_f32, TEST_LENGTH_SAMPLES); + riscv_q31_to_float(testOutput_q31_ref, testOutput_f32_ref, TEST_LENGTH_SAMPLES); +#ifndef WITH_FRONT + float snr = + riscv_snr_f32(&testOutput_f32_ref[100], &testOutput_f32[100], 200); + + if (snr < SNR_THRESHOLD_F32) { + BENCH_ERROR(riscv_fir_interpolate_q31); + printf("q31 fir_interpolate failed with snr:%f\n", snr); + test_flag_error = 1; + } + BENCH_STATUS(riscv_fir_interpolate_q31); +#else + float snr = riscv_snr_f32(&testOutput_f32_ref[0], &testOutput_f32[0], + TEST_LENGTH_SAMPLES*2); + + if (snr < SNR_THRESHOLD_F32) { + BENCH_ERROR(riscv_fir_interpolate_q31); + printf("q31 fir_interpolate failed with snr:%f\n", snr); + test_flag_error = 1; + } + BENCH_STATUS(riscv_fir_interpolate_q31); +#endif +} +static void riscv_fir_interpolate_q15_lp(void) +{ + uint32_t i; + /* clang-format off */ + riscv_fir_interpolate_instance_q15 S; + /* clang-format on */ + riscv_float_to_q15(testInput_f32_50Hz_200Hz, testInput_q15_50Hz_200Hz, TEST_LENGTH_SAMPLES); + riscv_float_to_q15(firCoeffs32LP, firCoeffs32LP_q15, NUM_TAPS); + riscv_fir_interpolate_init_q15(&S, 2, NUM_TAPS, &firCoeffs32LP_q15[0], + &firStateq15[0], TEST_LENGTH_SAMPLES); + BENCH_START(riscv_fir_interpolate_q15); + riscv_fir_interpolate_q15(&S, testInput_q15_50Hz_200Hz, testOutput_q15, TEST_LENGTH_SAMPLES); + BENCH_END(riscv_fir_interpolate_q15); + riscv_fir_interpolate_init_q15(&S, 2, NUM_TAPS, &firCoeffs32LP_q15[0], + &firStateq15[0], TEST_LENGTH_SAMPLES); + ref_fir_interpolate_q15(&S, testInput_q15_50Hz_200Hz, testOutput_q15_ref, TEST_LENGTH_SAMPLES); + riscv_q15_to_float(testOutput_q15, testOutput_f32, TEST_LENGTH_SAMPLES); + riscv_q15_to_float(testOutput_q15_ref, testOutput_f32_ref, TEST_LENGTH_SAMPLES); +#ifndef WITH_FRONT + float snr = + riscv_snr_f32(&testOutput_f32_ref[100], &testOutput_f32[100], 200); + + if (snr < SNR_THRESHOLD_F32) { + BENCH_ERROR(riscv_fir_interpolate_q15); + printf("q15 fir_interpolate failed with snr:%f\n", snr); + test_flag_error = 1; + } + BENCH_STATUS(riscv_fir_interpolate_q15); +#else + float snr = riscv_snr_f32(&testOutput_f32_ref[0], &testOutput_f32[0], + TEST_LENGTH_SAMPLES*2); + + if (snr < SNR_THRESHOLD_F32) { + BENCH_ERROR(riscv_fir_interpolate_q15); + printf("q15 fir_interpolate failed with snr:%f\n", snr); + test_flag_error = 1; + } + BENCH_STATUS(riscv_fir_interpolate_q15); +#endif +} + +int main() +{ + BENCH_INIT; + riscv_fir_interpolate_f32_lp(); + riscv_fir_interpolate_q31_lp(); + riscv_fir_interpolate_q15_lp(); + BENCH_FINISH; + if (test_flag_error) { + printf("test error apprears, please recheck.\n"); + return 1; + } else { + printf("all test are passed. Well done!\n"); + } + return 0; +} diff --git a/examples/dsp/FilteringFunction_firLatticePart/CMakeLists.txt b/examples/dsp/FilteringFunction_firLatticePart/CMakeLists.txt new file mode 100644 index 00000000..2a48c9c6 --- /dev/null +++ b/examples/dsp/FilteringFunction_firLatticePart/CMakeLists.txt @@ -0,0 +1,5 @@ +set(TARGET_REQUIRED_PRIVATE_INCLUDE ${CMAKE_CURRENT_SOURCE_DIR} ${CMAKE_CURRENT_SOURCE_DIR}/..) +set(TARGET_REQUIRED_SRCS fir_lattice.c) +set(TARGET_REQUIRED_LIBS nmsis) +set(mains main.c) +generate_bin() \ No newline at end of file diff --git a/examples/dsp/FilteringFunction_firLatticePart/array.h b/examples/dsp/FilteringFunction_firLatticePart/array.h new file mode 100644 index 00000000..29485cdd --- /dev/null +++ b/examples/dsp/FilteringFunction_firLatticePart/array.h @@ -0,0 +1,25 @@ +// Array for FilteringFunctions firLatticePart +#define TEST_LENGTH_SAMPLES 320 /* ???? */ +#define NUM_TAPS 29 /* ??????? */ + +const float32_t firCoeffs32LP[NUM_TAPS] = { + -0.001822523074f, -0.001587929321f, 1.226008847e-18f, 0.003697750857f, 0.008075430058f, + 0.008530221879f, -4.273456581e-18f, -0.01739769801f, -0.03414586186f, -0.03335915506f, + 8.073562366e-18f, 0.06763084233f, 0.1522061825f, 0.2229246944f, 0.2504960895f, + 0.2229246944f, 0.1522061825f, 0.06763084233f, 8.073562366e-18f, -0.03335915506f, + -0.03414586186f, -0.01739769801f, -4.273456581e-18f, 0.008530221879f, 0.008075430058f, + 0.003697750857f, 1.226008847e-18f, -0.001587929321f, -0.001822523074f}; +// float32_t + float32_t testOutput_f32[TEST_LENGTH_SAMPLES],testOutput_f32_ref[TEST_LENGTH_SAMPLES]; + float32_t firStatef32[TEST_LENGTH_SAMPLES + NUM_TAPS - 1]={0}; + float32_t testInput_f32_50Hz_200Hz[TEST_LENGTH_SAMPLES] = {0, 1.26007351067010, 1.17557050458495, 0.221231742082474, -1.11022302462516e-16, 1.00000000000000, 1.90211303259031, 1.39680224666742, 4.44089209850063e-16, -0.642039521920206, -3.67394039744206e-16, 0.642039521920206, -1.22124532708767e-15, -1.39680224666742, -1.90211303259031, -1.00000000000000, -3.33066907387547e-16, -0.221231742082476, -1.17557050458495, -1.26007351067010, -1.22464679914735e-15, 1.26007351067010, 1.17557050458495, 0.221231742082475, 8.88178419700125e-16, 1.00000000000000, 1.90211303259031, 1.39680224666742, 1.33226762955019e-15, -0.642039521920206, -1.10218211923262e-15, 0.642039521920206, 1.55431223447522e-15, -1.39680224666743, -1.90211303259031, -0.999999999999995, -7.77156117237610e-16, -0.221231742082473, -1.17557050458495, -1.26007351067010, -2.44929359829471e-15, 1.26007351067010, 1.17557050458494, 0.221231742082476, -7.77156117237610e-16, 0.999999999999998, 1.90211303259031, 1.39680224666742, -4.88498130835069e-15, -0.642039521920206, 3.49210031947972e-15, 0.642039521920206, 2.55351295663786e-15, -1.39680224666742, -1.90211303259031, -0.999999999999996, -9.99200722162641e-16, -0.221231742082477, -1.17557050458494, -1.26007351067011, -3.67394039744206e-15, 1.26007351067010, 1.17557050458495, 0.221231742082472, -1.22124532708767e-15, 1.00000000000000, 1.90211303259031, 1.39680224666742, -1.09912079437891e-14, -0.642039521920206, 8.08638275819206e-15, 0.642039521920205, 3.55271367880050e-15, -1.39680224666741, -1.90211303259031, -0.999999999999997, -1.44328993201270e-15, -0.221231742082476, -1.17557050458494, -1.26007351067010, -4.89858719658941e-15, 1.26007351067010, 1.17557050458494, 0.221231742082472, 3.88578058618805e-15, 1.00000000000000, 1.90211303259031, 1.39680224666743, 4.44089209850063e-15, -0.642039521920207, -3.30654635769785e-15, 0.642039521920206, 4.55191440096314e-15, -1.39680224666742, -1.90211303259031, -0.999999999999998, 3.66373598126302e-15, -0.221231742082476, -1.17557050458495, -1.26007351067010, 1.16403343982657e-14, 1.26007351067010, 1.17557050458496, 0.221231742082482, -1.99840144432528e-15, 1.00000000000000, 1.90211303259031, 1.39680224666743, 5.44009282066327e-15, -0.642039521920206, 6.61680659921524e-15, 0.642039521920207, 5.55111512312578e-15, -1.39680224666742, -1.90211303259031, -0.999999999999984, -2.10942374678780e-15, -0.221231742082475, -1.17557050458493, -1.26007351067011, -7.34788079488412e-15, 1.26007351067010, 1.17557050458494, 0.221231742082483, -2.33146835171283e-15, 1.00000000000000, 1.90211303259031, 1.39680224666741, 6.32827124036339e-15, -0.642039521920206, 5.88201851972683e-15, 0.642039521920207, -2.22044604925031e-14, -1.39680224666742, -1.90211303259031, -0.999999999999985, 8.43769498715119e-15, -0.221231742082475, -1.17557050458495, -1.26007351067009, 2.69546091939735e-14, 1.26007351067009, 1.17557050458496, 0.221231742082484, -2.77555756156289e-15, 1, 1.90211303259030, 1.39680224666743, 7.32747196252603e-15, -0.642039521920206, 5.14723044023841e-15, 0.642039521920205, 7.54951656745106e-15, -1.39680224666742, -1.90211303259031, -0.999999999999986, -2.99760216648792e-15, -0.221231742082474, -1.17557050458495, -1.26007351067009, -9.79717439317883e-15, 1.26007351067010, 1.17557050458494, 0.221231742082465, 7.88258347483861e-15, 0.999999999999999, 1.90211303259031, 1.39680224666741, -2.04281036531029e-14, -0.642039521920204, 4.41244236075000e-15, 0.642039521920207, 8.43769498715119e-15, -1.39680224666742, -1.90211303259031, -1.00000000000002, -3.33066907387547e-15, -0.221231742082473, -1.17557050458493, -1.26007351067011, -1.10218211923262e-14, 1.26007351067010, 1.17557050458494, 0.221231742082485, -3.44169137633799e-15, 0.999999999999998, 1.90211303259031, 1.39680224666741, 9.32587340685132e-15, -0.642039521920206, 3.67765428126159e-15, 0.642039521920207, -1.93178806284777e-14, -1.39680224666742, -1.90211303259031, -0.999999999999988, 7.32747196252603e-15, -0.221231742082492, -1.17557050458495, -1.26007351067009, 2.32806687965315e-14, 1.26007351067012, 1.17557050458494, 0.221231742082467, -1.47659662275146e-14, 0.999999999999969, 1.90211303259030, 1.39680224666744, 1.02140518265514e-14, -0.642039521920206, 2.94286620177318e-15, 0.642039521920207, -1.83186799063151e-14, -1.39680224666739, -1.90211303259031, -1.00000000000002, -4.10782519111308e-15, -0.221231742082472, -1.17557050458495, -1.26007351067010, 2.20560219973841e-14, 1.26007351067011, 1.17557050458493, 0.221231742082486, -4.21884749357560e-15, 0.999999999999996, 1.90211303259031, 1.39680224666741, -1.75415237890775e-14, -0.642039521920204, 2.35243601950878e-14, 0.642039521920209, 1.15463194561016e-14, -1.39680224666742, -1.90211303259031, -0.999999999999990, -1.54321000422897e-14, -0.221231742082452, -1.17557050458493, -1.26007351067011, -1.46957615897682e-14, 1.26007351067010, 1.17557050458495, 0.221231742082468, 6.32827124036339e-15, 1.00000000000002, 1.90211303259030, 1.39680224666744, 1.23234755733392e-14, -0.642039521920207, 1.47329004279635e-15, 0.642039521920207, -1.62092561595273e-14, -1.39680224666744, -1.90211303259030, -1.00000000000002, -4.88498130835069e-15, -0.221231742082471, -1.17557050458495, -1.26007351067010, 1.96067283990894e-14, 1.26007351067011, 1.17557050458493, 0.221231742082450, 1.69864122767649e-14, 0.999999999999994, 1.90211303259031, 1.39680224666741, -1.54321000422897e-14, -0.642039521920205, 2.20547840361110e-14, 0.642039521920209, -4.39648317751562e-14, -1.39680224666747, -1.90211303259031, -0.999999999999992, 5.77315972805081e-15, -0.221231742082489, -1.17557050458496, -1.26007351067008, 5.39092183879471e-14, 1.26007351067013, 1.17557050458498, 0.221231742082507, -1.63202784619898e-14, 0.999999999999965, 1.90211303259030, 1.39680224666744, 1.43218770176645e-14, -0.642039521920207, 3.71388381953015e-18, 0.642039521920203, 4.31876756579186e-14, -1.39680224666739, -1.90211303259031, -1.00000000000002, -5.55111512312578e-15, -0.221231742082469, -1.17557050458495, -1.26007351067010, 1.71574348007947e-14, 1.26007351067008, 1.17557050458496, 0.221231742082489, -5.77315972805081e-15, 0.999999999999992, 1.90211303259031, 1.39680224666741, -1.34336985979644e-14, -0.642039521920205, 2.05852078771341e-14, 0.642039521920205, 1.54321000422897e-14, -1.39680224666741, -1.90211303259031, -0.999999999999994, 4.99600361081320e-15, -0.221231742082488, -1.17557050458496, -1.26007351067008}; + +//q31_t + q31_t firStateq31[TEST_LENGTH_SAMPLES + NUM_TAPS - 1]; + q31_t testInput_q31_50Hz_200Hz[TEST_LENGTH_SAMPLES] = {0}, testOutput_q31[TEST_LENGTH_SAMPLES] = {0},testOutput_q31_ref[TEST_LENGTH_SAMPLES] = {0}; + q31_t firCoeffs32LP_q31[NUM_TAPS] = {0}; + +//q15_t + q15_t firStateq15[TEST_LENGTH_SAMPLES + NUM_TAPS - 1]; + q15_t testInput_q15_50Hz_200Hz[TEST_LENGTH_SAMPLES] = {0}, testOutput_q15[TEST_LENGTH_SAMPLES] = {0},testOutput_q15_ref[TEST_LENGTH_SAMPLES] = {0}; + q15_t firCoeffs32LP_q15[NUM_TAPS] = {0}; \ No newline at end of file diff --git a/examples/dsp/FilteringFunction_firLatticePart/fir_lattice.c b/examples/dsp/FilteringFunction_firLatticePart/fir_lattice.c new file mode 100644 index 00000000..2310a24f --- /dev/null +++ b/examples/dsp/FilteringFunction_firLatticePart/fir_lattice.c @@ -0,0 +1,219 @@ +#include "ref.h" + +void ref_fir_lattice_f32(const riscv_fir_lattice_instance_f32 *S, float32_t *pSrc, + float32_t *pDst, uint32_t blockSize) +{ + float32_t *pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *px; /* temporary state pointer */ + const float32_t *pk; /* temporary coefficient pointer */ + float32_t fcurr, fnext, gcurr, gnext; /* temporary variables */ + uint32_t numStages = S->numStages; /* Length of the filter */ + uint32_t blkCnt, stageCnt; /* temporary variables for counts */ + + pState = &S->pState[0]; + + blkCnt = blockSize; + + while (blkCnt > 0U) { + /* f0(n) = x(n) */ + fcurr = *pSrc++; + + /* Initialize coeff pointer */ + pk = pCoeffs; + + /* Initialize state pointer */ + px = pState; + + /* read g0(n-1) from state buffer */ + gcurr = *px; + + /* for sample 1 processing */ + /* f1(n) = f0(n) + K1 * g0(n-1) */ + fnext = fcurr + ((*pk) * gcurr); + /* g1(n) = f0(n) * K1 + g0(n-1) */ + gnext = (fcurr * (*pk++)) + gcurr; + + /* save f0(n) in state buffer */ + *px++ = fcurr; + + /* f1(n) is saved in fcurr + for next stage processing */ + fcurr = fnext; + + stageCnt = (numStages - 1U); + + /* stage loop */ + while (stageCnt > 0U) { + /* read g2(n) from state buffer */ + gcurr = *px; + + /* save g1(n) in state buffer */ + *px++ = gnext; + + /* Sample processing for K2, K3.... */ + /* f2(n) = f1(n) + K2 * g1(n-1) */ + fnext = fcurr + ((*pk) * gcurr); + /* g2(n) = f1(n) * K2 + g1(n-1) */ + gnext = (fcurr * (*pk++)) + gcurr; + + /* f1(n) is saved in fcurr1 + for next stage processing */ + fcurr = fnext; + + stageCnt--; + } + + /* y(n) = fN(n) */ + *pDst++ = fcurr; + + blkCnt--; + } +} + +void ref_fir_lattice_q31(const riscv_fir_lattice_instance_q31 *S, q31_t *pSrc, + q31_t *pDst, uint32_t blockSize) +{ + q31_t *pState; /* State pointer */ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *px; /* temporary state pointer */ + const q31_t *pk; /* temporary coefficient pointer */ + q31_t fcurr, fnext, gcurr, gnext; /* temporary variables */ + uint32_t numStages = S->numStages; /* Length of the filter */ + uint32_t blkCnt, stageCnt; /* temporary variables for counts */ + + pState = &S->pState[0]; + + blkCnt = blockSize; + + while (blkCnt > 0U) { + /* f0(n) = x(n) */ + fcurr = *pSrc++; + + /* Initialize coeff pointer */ + pk = pCoeffs; + + /* Initialize state pointer */ + px = pState; + + /* read g0(n-1) from state buffer */ + gcurr = *px; + + /* for sample 1 processing */ + /* f1(n) = f0(n) + K1 * g0(n-1) */ + fnext = (q31_t)(((q63_t)gcurr * (*pk)) >> 31) + fcurr; + /* g1(n) = f0(n) * K1 + g0(n-1) */ + gnext = (q31_t)(((q63_t)fcurr * (*pk++)) >> 31) + gcurr; + /* save g1(n) in state buffer */ + *px++ = fcurr; + + /* f1(n) is saved in fcurr1 + for next stage processing */ + fcurr = fnext; + + stageCnt = (numStages - 1U); + + /* stage loop */ + while (stageCnt > 0U) { + /* read g2(n) from state buffer */ + gcurr = *px; + + /* save g1(n) in state buffer */ + *px++ = gnext; + + /* Sample processing for K2, K3.... */ + /* f2(n) = f1(n) + K2 * g1(n-1) */ + fnext = (q31_t)(((q63_t)gcurr * (*pk)) >> 31) + fcurr; + /* g2(n) = f1(n) * K2 + g1(n-1) */ + gnext = (q31_t)(((q63_t)fcurr * (*pk++)) >> 31) + gcurr; + + /* f1(n) is saved in fcurr1 + for next stage processing */ + fcurr = fnext; + + stageCnt--; + } + + /* y(n) = fN(n) */ + *pDst++ = fcurr; + + blkCnt--; + } +} + +void ref_fir_lattice_q15(const riscv_fir_lattice_instance_q15 *S, q15_t *pSrc, + q15_t *pDst, uint32_t blockSize) +{ + q15_t *pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *px; /* temporary state pointer */ + const q15_t *pk; /* temporary coefficient pointer */ + q31_t fcurnt, fnext, gcurnt, gnext; /* temporary variables */ + uint32_t numStages = S->numStages; /* Length of the filter */ + uint32_t blkCnt, stageCnt; /* temporary variables for counts */ + + pState = &S->pState[0]; + + blkCnt = blockSize; + + while (blkCnt > 0U) { + /* f0(n) = x(n) */ + fcurnt = *pSrc++; + + /* Initialize coeff pointer */ + pk = (pCoeffs); + + /* Initialize state pointer */ + px = pState; + + /* read g0(n-1) from state buffer */ + gcurnt = *px; + + /* for sample 1 processing */ + /* f1(n) = f0(n) + K1 * g0(n-1) */ + fnext = ((gcurnt * (*pk)) >> 15U) + fcurnt; + fnext = ref_sat_q15(fnext); + + /* g1(n) = f0(n) * K1 + g0(n-1) */ + gnext = ((fcurnt * (*pk++)) >> 15U) + gcurnt; + gnext = ref_sat_q15(gnext); + + /* save f0(n) in state buffer */ + *px++ = (q15_t)fcurnt; + + /* f1(n) is saved in fcurnt + for next stage processing */ + fcurnt = fnext; + + stageCnt = (numStages - 1U); + + /* stage loop */ + while (stageCnt > 0U) { + /* read g1(n-1) from state buffer */ + gcurnt = *px; + + /* save g0(n-1) in state buffer */ + *px++ = (q15_t)gnext; + + /* Sample processing for K2, K3.... */ + /* f2(n) = f1(n) + K2 * g1(n-1) */ + fnext = ((gcurnt * (*pk)) >> 15U) + fcurnt; + fnext = ref_sat_q15(fnext); + + /* g2(n) = f1(n) * K2 + g1(n-1) */ + gnext = ((fcurnt * (*pk++)) >> 15U) + gcurnt; + gnext = ref_sat_q15(gnext); + + /* f1(n) is saved in fcurnt + for next stage processing */ + fcurnt = fnext; + + stageCnt--; + } + + /* y(n) = fN(n) */ + *pDst++ = ref_sat_q15(fcurnt); + + blkCnt--; + } +} diff --git a/examples/dsp/FilteringFunction_firLatticePart/main.c b/examples/dsp/FilteringFunction_firLatticePart/main.c new file mode 100644 index 00000000..25b0c946 --- /dev/null +++ b/examples/dsp/FilteringFunction_firLatticePart/main.c @@ -0,0 +1,160 @@ +// +// Created by lujun on 19-6-28. +// +// This contains fir, iir and lms filters +// each one has it's own function. +// All function can be found in main function. +// If you don't want to use it, then comment it. +// +// This part only tests result after 50 dots.If you want to test results' all +// dots, please define WITH_FRONT +// +// If there are too much numbers which makes it hard to read,in VScode you can +// press alt and z can shrimp them to one line +// +// You MUST be careful about overflow. +#include "riscv_math.h" +#include "array.h" +#include +#include "../common.h" + +#include "../HelperFunctions/math_helper.c" +#include "../HelperFunctions/ref_helper.c" + +#include +#define DELTAF32 (0.05f) +#define DELTAQ31 (63) +#define DELTAQ15 (1) +#define DELTAQ7 (1) +#define SNR_THRESHOLD_F32 (80.0f) + +int test_flag_error = 0; + +// #define WITH_FRONT + +//*************************************************************************************** +// fir Lattice Filters +//*************************************************************************************** +static void riscv_fir_lattice_f32_lp(void) +{ + uint32_t i; + /* clang-format off */ + riscv_fir_lattice_instance_f32 S; + /* clang-format on */ + riscv_fir_lattice_init_f32(&S, 29, &firCoeffs32LP[0], &firStatef32[0]); + BENCH_START(riscv_fir_lattice_f32); + riscv_fir_lattice_f32(&S, testInput_f32_50Hz_200Hz, testOutput_f32, TEST_LENGTH_SAMPLES); + BENCH_END(riscv_fir_lattice_f32); + riscv_fir_lattice_init_f32(&S, 29, &firCoeffs32LP[0], &firStatef32[0]); + ref_fir_lattice_f32(&S, testInput_f32_50Hz_200Hz, testOutput_f32_ref, TEST_LENGTH_SAMPLES); +#ifndef WITH_FRONT + float snr = riscv_snr_f32(&testOutput_f32_ref[50], &testOutput_f32[50], 269); + + if (snr < SNR_THRESHOLD_F32) { + BENCH_ERROR(riscv_fir_lattice_f32); + printf("f32 fir_lattice failed with snr:%f\n", snr); + test_flag_error = 1; + } + BENCH_STATUS(riscv_fir_lattice_f32); +#else + float snr = + riscv_snr_f32(&testOutput_ref[0], &testOutput[0], TEST_LENGTH_SAMPLES); + + if (snr < SNR_THRESHOLD_F32) { + BENCH_ERROR(riscv_fir_lattice_f32); + printf("f32 fir_lattice failed with snr:%f\n", snr); + test_flag_error = 1; + } + BENCH_STATUS(riscv_fir_lattice_f32); +#endif +} +static void riscv_fir_lattice_q31_lp(void) +{ + uint32_t i; + /* clang-format off */ + riscv_fir_lattice_instance_q31 S; + /* clang-format on */ + riscv_float_to_q31(testInput_f32_50Hz_200Hz, testInput_q31_50Hz_200Hz, TEST_LENGTH_SAMPLES); + riscv_float_to_q31(firCoeffs32LP, firCoeffs32LP_q31, NUM_TAPS); + riscv_fir_lattice_init_q31(&S, NUM_TAPS, &firCoeffs32LP_q31[0], &firStateq31[0]); + BENCH_START(riscv_fir_lattice_q31); + riscv_fir_lattice_q31(&S, testInput_q31_50Hz_200Hz, testOutput_q31, TEST_LENGTH_SAMPLES); + BENCH_END(riscv_fir_lattice_q31); + riscv_fir_lattice_init_q31(&S, NUM_TAPS, &firCoeffs32LP_q31[0], &firStateq31[0]); + ref_fir_lattice_q31(&S, testInput_q31_50Hz_200Hz, testOutput_q31_ref, TEST_LENGTH_SAMPLES); + riscv_q31_to_float(testOutput_q31, testOutput_f32, TEST_LENGTH_SAMPLES); + riscv_q31_to_float(testOutput_q31_ref, testOutput_f32_ref, TEST_LENGTH_SAMPLES); +#ifndef WITH_FRONT + float snr = riscv_snr_f32(&testOutput_f32_ref[50], &testOutput_f32[50], 269); + + if (snr < SNR_THRESHOLD_F32) { + BENCH_ERROR(riscv_fir_lattice_q31); + printf("q31 fir_lattice failed with snr:%f\n", snr); + test_flag_error = 1; + } + BENCH_STATUS(riscv_fir_lattice_q31); +#else + float snr = riscv_snr_f32(&testOutput_f32_ref[0], &testOutput_f32[0], + TEST_LENGTH_SAMPLES); + + if (snr < SNR_THRESHOLD_F32) { + BENCH_ERROR(riscv_fir_lattice_q31); + printf("q31 fir_lattice failed with snr:%f\n", snr); + test_flag_error = 1; + } + BENCH_STATUS(riscv_fir_lattice_q31); +#endif +} +static void riscv_fir_lattice_q15_lp(void) +{ + uint32_t i; + /* clang-format off */ + riscv_fir_lattice_instance_q15 S; + /* clang-format on */ + riscv_float_to_q15(testInput_f32_50Hz_200Hz, testInput_q15_50Hz_200Hz, TEST_LENGTH_SAMPLES); + riscv_float_to_q15(firCoeffs32LP, firCoeffs32LP_q15, NUM_TAPS); + riscv_fir_lattice_init_q15(&S, NUM_TAPS, &firCoeffs32LP_q15[0], &firStateq15[0]); + BENCH_START(riscv_fir_lattice_q15); + riscv_fir_lattice_q15(&S, testInput_q15_50Hz_200Hz, testOutput_q15, TEST_LENGTH_SAMPLES); + BENCH_END(riscv_fir_lattice_q15); + riscv_fir_lattice_init_q15(&S, NUM_TAPS, &firCoeffs32LP_q15[0], &firStateq15[0]); + ref_fir_lattice_q15(&S, testInput_q15_50Hz_200Hz, testOutput_q15_ref, TEST_LENGTH_SAMPLES); + riscv_q15_to_float(testOutput_q15, testOutput_f32, TEST_LENGTH_SAMPLES); + riscv_q15_to_float(testOutput_q15_ref, testOutput_f32_ref, TEST_LENGTH_SAMPLES); +#ifndef WITH_FRONT + float snr = riscv_snr_f32(&testOutput_f32_ref[50], &testOutput_f32[50], 269); + + if (snr < SNR_THRESHOLD_F32) { + BENCH_ERROR(riscv_fir_lattice_q15); + printf("q15 fir_lattice failed with snr:%f\n", snr); + test_flag_error = 1; + } + BENCH_STATUS(riscv_fir_lattice_q15); +#else + float snr = riscv_snr_f32(&testOutput_f32_ref[0], &testOutput_f32[0], + TEST_LENGTH_SAMPLES); + + if (snr < SNR_THRESHOLD_F32) { + BENCH_ERROR(riscv_fir_lattice_q15); + printf("q15 fir_lattice failed with snr:%f\n", snr); + test_flag_error = 1; + } + BENCH_STATUS(riscv_fir_lattice_q15); +#endif +} + +int main() +{ + BENCH_INIT; + riscv_fir_lattice_f32_lp(); + riscv_fir_lattice_q31_lp(); + riscv_fir_lattice_q15_lp(); + BENCH_FINISH; + if (test_flag_error) { + printf("test error apprears, please recheck.\n"); + return 1; + } else { + printf("all test are passed. Well done!\n"); + } + return 0; +} diff --git a/examples/dsp/FilteringFunction_firPart/CMakeLists.txt b/examples/dsp/FilteringFunction_firPart/CMakeLists.txt new file mode 100644 index 00000000..f690ff3a --- /dev/null +++ b/examples/dsp/FilteringFunction_firPart/CMakeLists.txt @@ -0,0 +1,5 @@ +set(TARGET_REQUIRED_PRIVATE_INCLUDE ${CMAKE_CURRENT_SOURCE_DIR} ${CMAKE_CURRENT_SOURCE_DIR}/..) +set(TARGET_REQUIRED_SRCS fir.c) +set(TARGET_REQUIRED_LIBS nmsis) +set(mains main.c) +generate_bin() \ No newline at end of file diff --git a/examples/dsp/FilteringFunction_firPart/array.h b/examples/dsp/FilteringFunction_firPart/array.h new file mode 100644 index 00000000..0900cac1 --- /dev/null +++ b/examples/dsp/FilteringFunction_firPart/array.h @@ -0,0 +1,30 @@ +// Array for FilteringFunctions firPart +#define TEST_LENGTH_SAMPLES 320 /* ???? */ +#define NUM_TAPS 30 /* Must be even */ + +const float32_t firCoeffs32LP[NUM_TAPS] = { + -0.001822523074f, -0.001587929321f, 1.226008847e-18f, 0.003697750857f, 0.008075430058f, + 0.008530221879f, -4.273456581e-18f, -0.01739769801f, -0.03414586186f, -0.03335915506f, + 8.073562366e-18f, 0.06763084233f, 0.1522061825f, 0.2229246944f, 0.2504960895f, + 0.2229246944f, 0.1522061825f, 0.06763084233f, 8.073562366e-18f, -0.03335915506f, + -0.03414586186f, -0.01739769801f, -4.273456581e-18f, 0.008530221879f, 0.008075430058f, + 0.003697750857f, 1.226008847e-18f, -0.001587929321f, -0.001822523074f, 0.0f}; +// float32_t + float32_t testOutput_f32[TEST_LENGTH_SAMPLES],testOutput_f32_ref[TEST_LENGTH_SAMPLES]; + float32_t firStatef32[TEST_LENGTH_SAMPLES + NUM_TAPS - 1]={0}; + float32_t testInput_f32_50Hz_200Hz[TEST_LENGTH_SAMPLES] = {0, 1.26007351067010, 1.17557050458495, 0.221231742082474, -1.11022302462516e-16, 1.00000000000000, 1.90211303259031, 1.39680224666742, 4.44089209850063e-16, -0.642039521920206, -3.67394039744206e-16, 0.642039521920206, -1.22124532708767e-15, -1.39680224666742, -1.90211303259031, -1.00000000000000, -3.33066907387547e-16, -0.221231742082476, -1.17557050458495, -1.26007351067010, -1.22464679914735e-15, 1.26007351067010, 1.17557050458495, 0.221231742082475, 8.88178419700125e-16, 1.00000000000000, 1.90211303259031, 1.39680224666742, 1.33226762955019e-15, -0.642039521920206, -1.10218211923262e-15, 0.642039521920206, 1.55431223447522e-15, -1.39680224666743, -1.90211303259031, -0.999999999999995, -7.77156117237610e-16, -0.221231742082473, -1.17557050458495, -1.26007351067010, -2.44929359829471e-15, 1.26007351067010, 1.17557050458494, 0.221231742082476, -7.77156117237610e-16, 0.999999999999998, 1.90211303259031, 1.39680224666742, -4.88498130835069e-15, -0.642039521920206, 3.49210031947972e-15, 0.642039521920206, 2.55351295663786e-15, -1.39680224666742, -1.90211303259031, -0.999999999999996, -9.99200722162641e-16, -0.221231742082477, -1.17557050458494, -1.26007351067011, -3.67394039744206e-15, 1.26007351067010, 1.17557050458495, 0.221231742082472, -1.22124532708767e-15, 1.00000000000000, 1.90211303259031, 1.39680224666742, -1.09912079437891e-14, -0.642039521920206, 8.08638275819206e-15, 0.642039521920205, 3.55271367880050e-15, -1.39680224666741, -1.90211303259031, -0.999999999999997, -1.44328993201270e-15, -0.221231742082476, -1.17557050458494, -1.26007351067010, -4.89858719658941e-15, 1.26007351067010, 1.17557050458494, 0.221231742082472, 3.88578058618805e-15, 1.00000000000000, 1.90211303259031, 1.39680224666743, 4.44089209850063e-15, -0.642039521920207, -3.30654635769785e-15, 0.642039521920206, 4.55191440096314e-15, -1.39680224666742, -1.90211303259031, -0.999999999999998, 3.66373598126302e-15, -0.221231742082476, -1.17557050458495, -1.26007351067010, 1.16403343982657e-14, 1.26007351067010, 1.17557050458496, 0.221231742082482, -1.99840144432528e-15, 1.00000000000000, 1.90211303259031, 1.39680224666743, 5.44009282066327e-15, -0.642039521920206, 6.61680659921524e-15, 0.642039521920207, 5.55111512312578e-15, -1.39680224666742, -1.90211303259031, -0.999999999999984, -2.10942374678780e-15, -0.221231742082475, -1.17557050458493, -1.26007351067011, -7.34788079488412e-15, 1.26007351067010, 1.17557050458494, 0.221231742082483, -2.33146835171283e-15, 1.00000000000000, 1.90211303259031, 1.39680224666741, 6.32827124036339e-15, -0.642039521920206, 5.88201851972683e-15, 0.642039521920207, -2.22044604925031e-14, -1.39680224666742, -1.90211303259031, -0.999999999999985, 8.43769498715119e-15, -0.221231742082475, -1.17557050458495, -1.26007351067009, 2.69546091939735e-14, 1.26007351067009, 1.17557050458496, 0.221231742082484, -2.77555756156289e-15, 1, 1.90211303259030, 1.39680224666743, 7.32747196252603e-15, -0.642039521920206, 5.14723044023841e-15, 0.642039521920205, 7.54951656745106e-15, -1.39680224666742, -1.90211303259031, -0.999999999999986, -2.99760216648792e-15, -0.221231742082474, -1.17557050458495, -1.26007351067009, -9.79717439317883e-15, 1.26007351067010, 1.17557050458494, 0.221231742082465, 7.88258347483861e-15, 0.999999999999999, 1.90211303259031, 1.39680224666741, -2.04281036531029e-14, -0.642039521920204, 4.41244236075000e-15, 0.642039521920207, 8.43769498715119e-15, -1.39680224666742, -1.90211303259031, -1.00000000000002, -3.33066907387547e-15, -0.221231742082473, -1.17557050458493, -1.26007351067011, -1.10218211923262e-14, 1.26007351067010, 1.17557050458494, 0.221231742082485, -3.44169137633799e-15, 0.999999999999998, 1.90211303259031, 1.39680224666741, 9.32587340685132e-15, -0.642039521920206, 3.67765428126159e-15, 0.642039521920207, -1.93178806284777e-14, -1.39680224666742, -1.90211303259031, -0.999999999999988, 7.32747196252603e-15, -0.221231742082492, -1.17557050458495, -1.26007351067009, 2.32806687965315e-14, 1.26007351067012, 1.17557050458494, 0.221231742082467, -1.47659662275146e-14, 0.999999999999969, 1.90211303259030, 1.39680224666744, 1.02140518265514e-14, -0.642039521920206, 2.94286620177318e-15, 0.642039521920207, -1.83186799063151e-14, -1.39680224666739, -1.90211303259031, -1.00000000000002, -4.10782519111308e-15, -0.221231742082472, -1.17557050458495, -1.26007351067010, 2.20560219973841e-14, 1.26007351067011, 1.17557050458493, 0.221231742082486, -4.21884749357560e-15, 0.999999999999996, 1.90211303259031, 1.39680224666741, -1.75415237890775e-14, -0.642039521920204, 2.35243601950878e-14, 0.642039521920209, 1.15463194561016e-14, -1.39680224666742, -1.90211303259031, -0.999999999999990, -1.54321000422897e-14, -0.221231742082452, -1.17557050458493, -1.26007351067011, -1.46957615897682e-14, 1.26007351067010, 1.17557050458495, 0.221231742082468, 6.32827124036339e-15, 1.00000000000002, 1.90211303259030, 1.39680224666744, 1.23234755733392e-14, -0.642039521920207, 1.47329004279635e-15, 0.642039521920207, -1.62092561595273e-14, -1.39680224666744, -1.90211303259030, -1.00000000000002, -4.88498130835069e-15, -0.221231742082471, -1.17557050458495, -1.26007351067010, 1.96067283990894e-14, 1.26007351067011, 1.17557050458493, 0.221231742082450, 1.69864122767649e-14, 0.999999999999994, 1.90211303259031, 1.39680224666741, -1.54321000422897e-14, -0.642039521920205, 2.20547840361110e-14, 0.642039521920209, -4.39648317751562e-14, -1.39680224666747, -1.90211303259031, -0.999999999999992, 5.77315972805081e-15, -0.221231742082489, -1.17557050458496, -1.26007351067008, 5.39092183879471e-14, 1.26007351067013, 1.17557050458498, 0.221231742082507, -1.63202784619898e-14, 0.999999999999965, 1.90211303259030, 1.39680224666744, 1.43218770176645e-14, -0.642039521920207, 3.71388381953015e-18, 0.642039521920203, 4.31876756579186e-14, -1.39680224666739, -1.90211303259031, -1.00000000000002, -5.55111512312578e-15, -0.221231742082469, -1.17557050458495, -1.26007351067010, 1.71574348007947e-14, 1.26007351067008, 1.17557050458496, 0.221231742082489, -5.77315972805081e-15, 0.999999999999992, 1.90211303259031, 1.39680224666741, -1.34336985979644e-14, -0.642039521920205, 2.05852078771341e-14, 0.642039521920205, 1.54321000422897e-14, -1.39680224666741, -1.90211303259031, -0.999999999999994, 4.99600361081320e-15, -0.221231742082488, -1.17557050458496, -1.26007351067008}; + +//q31_t + q31_t firStateq31[TEST_LENGTH_SAMPLES + NUM_TAPS - 1]; + q31_t testInput_q31_50Hz_200Hz[TEST_LENGTH_SAMPLES] = {0}, testOutput_q31[TEST_LENGTH_SAMPLES] = {0},testOutput_q31_ref[TEST_LENGTH_SAMPLES] = {0}; + q31_t firCoeffs32LP_q31[NUM_TAPS] = {0}; + +//q15_t + q15_t firStateq15[TEST_LENGTH_SAMPLES + NUM_TAPS - 1]; + q15_t testInput_q15_50Hz_200Hz[TEST_LENGTH_SAMPLES] = {0}, testOutput_q15[TEST_LENGTH_SAMPLES] = {0},testOutput_q15_ref[TEST_LENGTH_SAMPLES] = {0}; + q15_t firCoeffs32LP_q15[NUM_TAPS] = {0}; + +//q7_t + q7_t firStateq7[TEST_LENGTH_SAMPLES + NUM_TAPS - 1]; + q7_t testInput_q7_50Hz_200Hz[TEST_LENGTH_SAMPLES] = {0}, testOutput_q7[TEST_LENGTH_SAMPLES] = {0},testOutput_q7_ref[TEST_LENGTH_SAMPLES] = {0}; + q7_t firCoeffs32LP_q7[NUM_TAPS] = {0}; \ No newline at end of file diff --git a/examples/dsp/FilteringFunction_firPart/fir.c b/examples/dsp/FilteringFunction_firPart/fir.c new file mode 100644 index 00000000..953b3c35 --- /dev/null +++ b/examples/dsp/FilteringFunction_firPart/fir.c @@ -0,0 +1,315 @@ +#include "ref.h" + +void ref_fir_f32(const riscv_fir_instance_f32 *S, float32_t *pSrc, + float32_t *pDst, uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *pStateCurnt; /* Points to the current sample of the state */ + uint32_t numTaps = + S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i; /* Loop counters */ + float32_t acc; + + /* S->pState points to state array which contains previous frame (numTaps - + * 1) samples */ + /* pStateCurnt points to the location where the new input data should be + * written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + + while (blockSize > 0U) { + /* Copy one sample at a time into state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Set the accumulator to zero */ + acc = 0.0f; + + for (i = 0; i < numTaps; i++) { + /* Perform the multiply-accumulates */ + acc += pState[i] * pCoeffs[i]; + } + + /* The result is store in the destination buffer. */ + *pDst++ = acc; + + /* Advance state pointer by 1 for the next sample */ + pState++; + + blockSize--; + } + + /* Processing is complete. + ** Now copy the last numTaps - 1 samples to the starting of the state + *buffer. + ** This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + + /* Copy data */ + for (i = 0; i < numTaps - 1; i++) { + pStateCurnt[i] = pState[i]; + } +} + +void ref_fir_q31(const riscv_fir_instance_q31 *S, q31_t *pSrc, q31_t *pDst, + uint32_t blockSize) +{ + q31_t *pState = S->pState; /* State pointer */ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *pStateCurnt; /* Points to the current sample of the state */ + uint32_t numTaps = + S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i; /* Loop counter */ + q63_t acc; + + /* S->pState points to state array which contains previous frame (numTaps - + * 1) samples */ + /* pStateCurnt points to the location where the new input data should be + * written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + + while (blockSize > 0U) { + /* Copy one sample at a time into state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Set the accumulator to zero */ + acc = 0.0f; + + for (i = 0; i < numTaps; i++) { + /* Perform the multiply-accumulates */ + acc += (q63_t)pState[i] * pCoeffs[i]; + } + + /* The result is store in the destination buffer. */ + *pDst++ = (q31_t)(acc >> 31); + + /* Advance state pointer by 1 for the next sample */ + pState++; + + blockSize--; + } + + /* Processing is complete. + ** Now copy the last numTaps - 1 samples to the starting of the state + *buffer. + ** This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + + /* Copy data */ + for (i = 0; i < numTaps - 1; i++) { + pStateCurnt[i] = pState[i]; + } +} + +void ref_fir_fast_q31(const riscv_fir_instance_q31 *S, q31_t *pSrc, q31_t *pDst, + uint32_t blockSize) +{ + q31_t *pState = S->pState; /* State pointer */ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *pStateCurnt; /* Points to the current sample of the state */ + uint32_t numTaps = + S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i; /* Loop counter */ + q31_t acc; + + /* S->pState points to state array which contains previous frame (numTaps - + * 1) samples */ + /* pStateCurnt points to the location where the new input data should be + * written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + + while (blockSize > 0U) { + /* Copy one sample at a time into state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Set the accumulator to zero */ + acc = 0.0f; + + for (i = 0; i < numTaps; i++) { + /* Perform the multiply-accumulates */ + acc = (q31_t)(((((q63_t)acc) << 32) + + ((q63_t)pState[i] * pCoeffs[i]) + 0x80000000LL) >> + 32); + } + + /* The result is store in the destination buffer. */ + *pDst++ = (q31_t)(acc << 1); + + /* Advance state pointer by 1 for the next sample */ + pState++; + + blockSize--; + } + + /* Processing is complete. + ** Now copy the last numTaps - 1 samples to the starting of the state + *buffer. + ** This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + + /* Copy data */ + for (i = 0; i < numTaps - 1; i++) { + pStateCurnt[i] = pState[i]; + } +} + +void ref_fir_q15(const riscv_fir_instance_q15 *S, q15_t *pSrc, q15_t *pDst, + uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCurnt; /* Points to the current sample of the state */ + uint32_t numTaps = + S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i; /* Loop counter */ + q63_t acc; + + /* S->pState points to state array which contains previous frame (numTaps - + * 1) samples */ + /* pStateCurnt points to the location where the new input data should be + * written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + + while (blockSize > 0U) { + /* Copy one sample at a time into state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Set the accumulator to zero */ + acc = 0.0f; + + for (i = 0; i < numTaps; i++) { + /* Perform the multiply-accumulates */ + acc += (q31_t)pState[i] * pCoeffs[i]; + } + + /* The result is store in the destination buffer. */ + *pDst++ = ref_sat_q15(acc >> 15); + + /* Advance state pointer by 1 for the next sample */ + pState++; + + blockSize--; + } + + /* Processing is complete. + ** Now copy the last numTaps - 1 samples to the starting of the state + *buffer. + ** This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + + /* Copy data */ + for (i = 0; i < numTaps; i++) { + pStateCurnt[i] = pState[i]; + } +} + +void ref_fir_fast_q15(const riscv_fir_instance_q15 *S, q15_t *pSrc, q15_t *pDst, + uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCurnt; /* Points to the current sample of the state */ + uint32_t numTaps = + S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i; /* Loop counter */ + q31_t acc; + + /* S->pState points to state array which contains previous frame (numTaps - + * 1) samples */ + /* pStateCurnt points to the location where the new input data should be + * written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + + while (blockSize > 0U) { + /* Copy one sample at a time into state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Set the accumulator to zero */ + acc = 0.0f; + + for (i = 0; i < numTaps; i++) { + /* Perform the multiply-accumulates */ + acc += (q31_t)pState[i] * pCoeffs[i]; + } + + /* The result is store in the destination buffer. */ + *pDst++ = ref_sat_q15(acc >> 15); + + /* Advance state pointer by 1 for the next sample */ + pState++; + + blockSize--; + } + + /* Processing is complete. + ** Now copy the last numTaps - 1 samples to the starting of the state + *buffer. + ** This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + + /* Copy data */ + for (i = 0; i < numTaps - 1; i++) { + pStateCurnt[i] = pState[i]; + } +} + +void ref_fir_q7(const riscv_fir_instance_q7 *S, q7_t *pSrc, q7_t *pDst, + uint32_t blockSize) +{ + q7_t *pState = S->pState; /* State pointer */ + const q7_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q7_t *pStateCurnt; /* Points to the current sample of the state */ + uint32_t numTaps = + S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i; /* Loop counter */ + q31_t acc; + + /* S->pState points to state array which contains previous frame (numTaps - + * 1) samples */ + /* pStateCurnt points to the location where the new input data should be + * written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + + while (blockSize > 0U) { + /* Copy one sample at a time into state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Set the accumulator to zero */ + acc = 0.0f; + + for (i = 0; i < numTaps; i++) { + /* Perform the multiply-accumulates */ + acc += (q31_t)pState[i] * pCoeffs[i]; + } + + /* The result is store in the destination buffer. */ + *pDst++ = ref_sat_q7(acc >> 7); + + /* Advance state pointer by 1 for the next sample */ + pState++; + + blockSize--; + } + + /* Processing is complete. + ** Now copy the last numTaps - 1 samples to the starting of the state + *buffer. + ** This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + + /* Copy data */ + for (i = 0; i < numTaps - 1; i++) { + pStateCurnt[i] = pState[i]; + } +} diff --git a/examples/dsp/FilteringFunction_firPart/main.c b/examples/dsp/FilteringFunction_firPart/main.c new file mode 100644 index 00000000..b96c0415 --- /dev/null +++ b/examples/dsp/FilteringFunction_firPart/main.c @@ -0,0 +1,273 @@ +// +// Created by lujun on 19-6-28. +// +// This contains fir, iir and lms filters +// each one has it's own function. +// All function can be found in main function. +// If you don't want to use it, then comment it. +// +// This part only tests result after 50 dots.If you want to test results' all +// dots, please define WITH_FRONT +// +// If there are too much numbers which makes it hard to read,in VScode you can +// press alt and z can shrimp them to one line +// +// You MUST be careful about overflow. +#include "riscv_math.h" +#include "array.h" +#include +#include "../common.h" + +#include "../HelperFunctions/math_helper.c" +#include "../HelperFunctions/ref_helper.c" + +#include +#define DELTAF32 (0.05f) +#define DELTAQ31 (63) +#define DELTAQ15 (1) +#define DELTAQ7 (1) +#define SNR_THRESHOLD_F32 (80.0f) + +int test_flag_error = 0; + +// #define WITH_FRONT + +/* clang-format on */ +//*************************************************************************************** +// fir +//*************************************************************************************** +static int riscv_fir_f32_lp(void) +{ + uint32_t i; + /* clang-format off */ + riscv_fir_instance_f32 S; + /* clang-format on */ + riscv_fir_init_f32(&S, NUM_TAPS, &firCoeffs32LP[0], &firStatef32[0], TEST_LENGTH_SAMPLES); + BENCH_START(riscv_fir_f32); + riscv_fir_f32(&S, testInput_f32_50Hz_200Hz, testOutput_f32, TEST_LENGTH_SAMPLES); + BENCH_END(riscv_fir_f32); + riscv_fir_init_f32(&S, NUM_TAPS, &firCoeffs32LP[0], &firStatef32[0], TEST_LENGTH_SAMPLES); + ref_fir_f32(&S, testInput_f32_50Hz_200Hz, testOutput_f32_ref, TEST_LENGTH_SAMPLES); +#ifndef WITH_FRONT + float snr = riscv_snr_f32(&testOutput_f32_ref[50], &testOutput_f32[50], 269); + + if (snr < SNR_THRESHOLD_F32) { + BENCH_ERROR(riscv_fir_f32); + printf("f32 fir failed with snr:%f\n", snr); + test_flag_error = 1; + } + BENCH_STATUS(riscv_fir_f32); +#else + float snr = + riscv_snr_f32(&testOutput_ref[0], &testOutput[0], TEST_LENGTH_SAMPLES); + + if (snr < SNR_THRESHOLD_F32) { + BENCH_ERROR(riscv_fir_f32); + printf("f32 fir failed with snr:%f\n", snr); + test_flag_error = 1; + } + BENCH_STATUS(riscv_fir_f32); +#endif +} +static int riscv_fir_q31_lp(void) +{ + uint32_t i; + /* clang-format off */ + riscv_fir_instance_q31 S; + /* clang-format on */ + riscv_float_to_q31(testInput_f32_50Hz_200Hz, testInput_q31_50Hz_200Hz, TEST_LENGTH_SAMPLES); + riscv_float_to_q31(firCoeffs32LP, firCoeffs32LP_q31, NUM_TAPS); + riscv_fir_init_q31(&S, NUM_TAPS, &firCoeffs32LP_q31[0], &firStateq31[0], TEST_LENGTH_SAMPLES); + BENCH_START(riscv_fir_q31); + riscv_fir_q31(&S, testInput_q31_50Hz_200Hz, testOutput_q31, TEST_LENGTH_SAMPLES); + BENCH_END(riscv_fir_q31); + riscv_fir_init_q31(&S, NUM_TAPS, &firCoeffs32LP_q31[0], &firStateq31[0], TEST_LENGTH_SAMPLES); + ref_fir_q31(&S, testInput_q31_50Hz_200Hz, testOutput_q31_ref, TEST_LENGTH_SAMPLES); + riscv_q31_to_float(testOutput_q31, testOutput_f32, TEST_LENGTH_SAMPLES); + riscv_q31_to_float(testOutput_q31_ref, testOutput_f32_ref, TEST_LENGTH_SAMPLES); +#ifndef WITH_FRONT + float snr = riscv_snr_f32(&testOutput_f32_ref[50], &testOutput_f32[50], 269); + + if (snr < SNR_THRESHOLD_F32) { + BENCH_ERROR(riscv_fir_q31); + printf("q31 fir failed with snr:%f\n", snr); + test_flag_error = 1; + } + BENCH_STATUS(riscv_fir_q31); +#else + float snr = riscv_snr_f32(&testOutput_f32_ref[0], &testOutput_f32[0], + TEST_LENGTH_SAMPLES); + + if (snr < SNR_THRESHOLD_F32) { + BENCH_ERROR(riscv_fir_q31); + printf("q31 fir failed with snr:%f\n", snr); + test_flag_error = 1; + } + BENCH_STATUS(riscv_fir_q31); +#endif +} +static int riscv_fir_q15_lp(void) +{ + uint32_t i; + /* clang-format off */ + riscv_fir_instance_q15 S; + /* clang-format on */ + riscv_float_to_q15(testInput_f32_50Hz_200Hz, testInput_q15_50Hz_200Hz, TEST_LENGTH_SAMPLES); + riscv_float_to_q15(firCoeffs32LP, firCoeffs32LP_q15, NUM_TAPS); + riscv_fir_init_q15(&S, NUM_TAPS, &firCoeffs32LP_q15[0], &firStateq15[0], TEST_LENGTH_SAMPLES); + BENCH_START(riscv_fir_q15); + riscv_fir_q15(&S, testInput_q15_50Hz_200Hz, testOutput_q15, TEST_LENGTH_SAMPLES); + BENCH_END(riscv_fir_q15); + riscv_fir_init_q15(&S, NUM_TAPS, &firCoeffs32LP_q15[0], &firStateq15[0], TEST_LENGTH_SAMPLES); + ref_fir_q15(&S, testInput_q15_50Hz_200Hz, testOutput_q15_ref, TEST_LENGTH_SAMPLES); + riscv_q15_to_float(testOutput_q15, testOutput_f32, TEST_LENGTH_SAMPLES); + riscv_q15_to_float(testOutput_q15_ref, testOutput_f32_ref, TEST_LENGTH_SAMPLES); +#ifndef WITH_FRONT + float snr = riscv_snr_f32(&testOutput_f32_ref[50], &testOutput_f32[50], 269); + + if (snr < SNR_THRESHOLD_F32) { + BENCH_ERROR(riscv_fir_q15); + printf("q15 fir failed with snr:%f\n", snr); + test_flag_error = 1; + } + BENCH_STATUS(riscv_fir_q15); +#else + float snr = riscv_snr_f32(&testOutput_f32_ref[0], &testOutput_f32[0], + TEST_LENGTH_SAMPLES); + + if (snr < SNR_THRESHOLD_F32) { + BENCH_ERROR(riscv_fir_q15); + printf("q15 fir failed with snr:%f\n", snr); + test_flag_error = 1; + } + BENCH_STATUS(riscv_fir_q15); +#endif +} +static int riscv_fir_q7_lp(void) +{ + uint32_t i; + /* clang-format off */ + riscv_fir_instance_q7 S; + /* clang-format on */ + riscv_float_to_q7(testInput_f32_50Hz_200Hz, testInput_q7_50Hz_200Hz, TEST_LENGTH_SAMPLES); + riscv_float_to_q7(firCoeffs32LP, firCoeffs32LP_q7, NUM_TAPS); + riscv_fir_init_q7(&S, NUM_TAPS, &firCoeffs32LP_q7[0], &firStateq7[0], TEST_LENGTH_SAMPLES); + BENCH_START(riscv_fir_q7); + riscv_fir_q7(&S, testInput_q7_50Hz_200Hz, testOutput_q7, TEST_LENGTH_SAMPLES); + BENCH_END(riscv_fir_q7); + riscv_fir_init_q7(&S, NUM_TAPS, &firCoeffs32LP_q7[0], &firStateq7[0], TEST_LENGTH_SAMPLES); + ref_fir_q7(&S, testInput_q7_50Hz_200Hz, testOutput_q7_ref, TEST_LENGTH_SAMPLES); + riscv_q7_to_float(testOutput_q7, testOutput_f32, TEST_LENGTH_SAMPLES); + riscv_q7_to_float(testOutput_q7_ref, testOutput_f32_ref, TEST_LENGTH_SAMPLES); +#ifndef WITH_FRONT + float snr = riscv_snr_f32(&testOutput_f32_ref[50], &testOutput_f32[50], 269); + if (snr < SNR_THRESHOLD_F32) { + BENCH_ERROR(riscv_fir_q7); + printf("q7 fir failed with snr:%f\n", snr); + test_flag_error = 1; + } + BENCH_STATUS(riscv_fir_q7); +#else + float snr = riscv_snr_f32(&testOutput_f32_ref[0], &testOutput_f32[0], + TEST_LENGTH_SAMPLES); + + if (snr < SNR_THRESHOLD_F32) { + BENCH_ERROR(riscv_fir_q7); + printf("q7 fir failed with snr:%f\n", snr); + test_flag_error = 1; + } + BENCH_STATUS(riscv_fir_q7); +#endif +} +static int riscv_fir_fast_q31_lp(void) +{ + uint32_t i; + /* clang-format off */ + riscv_fir_instance_q31 S; + /* clang-format on */ + riscv_float_to_q31(testInput_f32_50Hz_200Hz, testInput_q31_50Hz_200Hz, TEST_LENGTH_SAMPLES); + riscv_float_to_q31(firCoeffs32LP, firCoeffs32LP_q31, NUM_TAPS); + riscv_fir_init_q31(&S, NUM_TAPS, &firCoeffs32LP_q31[0], &firStateq31[0], TEST_LENGTH_SAMPLES); + BENCH_START(riscv_fir_fast_q31); + riscv_fir_fast_q31(&S, testInput_q31_50Hz_200Hz, + testOutput_q31, TEST_LENGTH_SAMPLES); + BENCH_END(riscv_fir_fast_q31); + riscv_fir_init_q31(&S, NUM_TAPS, &firCoeffs32LP_q31[0], &firStateq31[0], TEST_LENGTH_SAMPLES); + ref_fir_fast_q31(&S, testInput_q31_50Hz_200Hz, + testOutput_q31_ref, TEST_LENGTH_SAMPLES); + riscv_q31_to_float(testOutput_q31, testOutput_f32, TEST_LENGTH_SAMPLES); + riscv_q31_to_float(testOutput_q31_ref, testOutput_f32_ref, TEST_LENGTH_SAMPLES); +#ifndef WITH_FRONT + float snr = riscv_snr_f32(&testOutput_f32_ref[50], &testOutput_f32[50], 269); + if (snr < SNR_THRESHOLD_F32) { + BENCH_ERROR(riscv_fir_fast_q31); + printf("q31 fir_fast failed with snr:%f\n", snr); + test_flag_error = 1; + } + BENCH_STATUS(riscv_fir_fast_q31); +#else + float snr = riscv_snr_f32(&testOutput_f32_ref[0], &testOutput_f32[0], + TEST_LENGTH_SAMPLES); + + if (snr < SNR_THRESHOLD_F32) { + BENCH_ERROR(riscv_fir_fast_q31); + printf("q31 fir_fast failed with snr:%f\n", snr); + test_flag_error = 1; + } + BENCH_STATUS(riscv_fir_fast_q31); +#endif +} +static int riscv_fir_fast_q15_lp(void) +{ + uint32_t i; + /* clang-format off */ + riscv_fir_instance_q15 S; + /* clang-format on */ + riscv_float_to_q15(testInput_f32_50Hz_200Hz, testInput_q15_50Hz_200Hz, TEST_LENGTH_SAMPLES); + riscv_float_to_q15(firCoeffs32LP, firCoeffs32LP_q15, NUM_TAPS); + riscv_fir_init_q15(&S, NUM_TAPS, &firCoeffs32LP_q15[0], &firStateq15[0], TEST_LENGTH_SAMPLES); + BENCH_START(riscv_fir_fast_q15); + riscv_fir_fast_q15(&S, testInput_q15_50Hz_200Hz, testOutput_q15, TEST_LENGTH_SAMPLES); + BENCH_END(riscv_fir_fast_q15); + riscv_fir_init_q15(&S, NUM_TAPS, &firCoeffs32LP_q15[0], &firStateq15[0], TEST_LENGTH_SAMPLES); + ref_fir_fast_q15(&S, testInput_q15_50Hz_200Hz, testOutput_q15_ref, TEST_LENGTH_SAMPLES); + riscv_q15_to_float(testOutput_q15, testOutput_f32, TEST_LENGTH_SAMPLES); + riscv_q15_to_float(testOutput_q15_ref, testOutput_f32_ref, TEST_LENGTH_SAMPLES); +#ifndef WITH_FRONT + float snr = riscv_snr_f32(&testOutput_f32_ref[50], &testOutput_f32[50], 269); + if (snr < SNR_THRESHOLD_F32) { + BENCH_ERROR(riscv_fir_fast_q15); + printf("q15 fir_fast failed with snr:%f\n", snr); + test_flag_error = 1; + } + BENCH_STATUS(riscv_fir_fast_q15); +#else + float snr = riscv_snr_f32(&testOutput_f32_ref[0], &testOutput_f32[0], + TEST_LENGTH_SAMPLES); + if (snr < SNR_THRESHOLD_F32) { + BENCH_ERROR(riscv_fir_fast_q15); + printf("q15 fir_fast failed with snr:%f\n", snr); + test_flag_error = 1; + } + BENCH_STATUS(riscv_fir_fast_q15); +#endif +} + +int main() +{ + BENCH_INIT; + riscv_fir_f32_lp(); + riscv_fir_q31_lp(); + riscv_fir_q15_lp(); + riscv_fir_q7_lp(); + riscv_fir_fast_q31_lp(); + riscv_fir_fast_q15_lp(); + BENCH_FINISH; + if (test_flag_error) { + printf("test error apprears, please recheck.\n"); + return 1; + } else { + printf("all test are passed. Well done!\n"); + } + return 0; +} diff --git a/examples/dsp/FilteringFunction_firSparsePart/CMakeLists.txt b/examples/dsp/FilteringFunction_firSparsePart/CMakeLists.txt new file mode 100644 index 00000000..bfede98e --- /dev/null +++ b/examples/dsp/FilteringFunction_firSparsePart/CMakeLists.txt @@ -0,0 +1,5 @@ +set(TARGET_REQUIRED_PRIVATE_INCLUDE ${CMAKE_CURRENT_SOURCE_DIR} ${CMAKE_CURRENT_SOURCE_DIR}/..) +set(TARGET_REQUIRED_SRCS fir_sparse.c) +set(TARGET_REQUIRED_LIBS nmsis) +set(mains main.c) +generate_bin() \ No newline at end of file diff --git a/examples/dsp/FilteringFunction_firSparsePart/array.h b/examples/dsp/FilteringFunction_firSparsePart/array.h new file mode 100644 index 00000000..2cc4f3cb --- /dev/null +++ b/examples/dsp/FilteringFunction_firSparsePart/array.h @@ -0,0 +1,36 @@ +// Array for FilteringFunctions firSparsePart +#define TEST_LENGTH_SAMPLES 320 /* ???? */ +#define NUM_TAPS 29 /* Must be even */ +#define MAXDelay 29 /* Must be even */ + int32_t pTapDelay[NUM_TAPS] = {0}; +const float32_t firCoeffs32LP[NUM_TAPS] = { + -0.001822523074f, -0.001587929321f, 1.226008847e-18f, 0.003697750857f, 0.008075430058f, + 0.008530221879f, -4.273456581e-18f, -0.01739769801f, -0.03414586186f, -0.03335915506f, + 8.073562366e-18f, 0.06763084233f, 0.1522061825f, 0.2229246944f, 0.2504960895f, + 0.2229246944f, 0.1522061825f, 0.06763084233f, 8.073562366e-18f, -0.03335915506f, + -0.03414586186f, -0.01739769801f, -4.273456581e-18f, 0.008530221879f, 0.008075430058f, + 0.003697750857f, 1.226008847e-18f, -0.001587929321f, -0.001822523074f}; +// float32_t + float32_t testOutput_f32[TEST_LENGTH_SAMPLES],testOutput_f32_ref[TEST_LENGTH_SAMPLES]; + float32_t firStatef32[TEST_LENGTH_SAMPLES + NUM_TAPS - 1]={0}; + float32_t testInput_f32_50Hz_200Hz[TEST_LENGTH_SAMPLES] = {0, 1.26007351067010, 1.17557050458495, 0.221231742082474, -1.11022302462516e-16, 1.00000000000000, 1.90211303259031, 1.39680224666742, 4.44089209850063e-16, -0.642039521920206, -3.67394039744206e-16, 0.642039521920206, -1.22124532708767e-15, -1.39680224666742, -1.90211303259031, -1.00000000000000, -3.33066907387547e-16, -0.221231742082476, -1.17557050458495, -1.26007351067010, -1.22464679914735e-15, 1.26007351067010, 1.17557050458495, 0.221231742082475, 8.88178419700125e-16, 1.00000000000000, 1.90211303259031, 1.39680224666742, 1.33226762955019e-15, -0.642039521920206, -1.10218211923262e-15, 0.642039521920206, 1.55431223447522e-15, -1.39680224666743, -1.90211303259031, -0.999999999999995, -7.77156117237610e-16, -0.221231742082473, -1.17557050458495, -1.26007351067010, -2.44929359829471e-15, 1.26007351067010, 1.17557050458494, 0.221231742082476, -7.77156117237610e-16, 0.999999999999998, 1.90211303259031, 1.39680224666742, -4.88498130835069e-15, -0.642039521920206, 3.49210031947972e-15, 0.642039521920206, 2.55351295663786e-15, -1.39680224666742, -1.90211303259031, -0.999999999999996, -9.99200722162641e-16, -0.221231742082477, -1.17557050458494, -1.26007351067011, -3.67394039744206e-15, 1.26007351067010, 1.17557050458495, 0.221231742082472, -1.22124532708767e-15, 1.00000000000000, 1.90211303259031, 1.39680224666742, -1.09912079437891e-14, -0.642039521920206, 8.08638275819206e-15, 0.642039521920205, 3.55271367880050e-15, -1.39680224666741, -1.90211303259031, -0.999999999999997, -1.44328993201270e-15, -0.221231742082476, -1.17557050458494, -1.26007351067010, -4.89858719658941e-15, 1.26007351067010, 1.17557050458494, 0.221231742082472, 3.88578058618805e-15, 1.00000000000000, 1.90211303259031, 1.39680224666743, 4.44089209850063e-15, -0.642039521920207, -3.30654635769785e-15, 0.642039521920206, 4.55191440096314e-15, -1.39680224666742, -1.90211303259031, -0.999999999999998, 3.66373598126302e-15, -0.221231742082476, -1.17557050458495, -1.26007351067010, 1.16403343982657e-14, 1.26007351067010, 1.17557050458496, 0.221231742082482, -1.99840144432528e-15, 1.00000000000000, 1.90211303259031, 1.39680224666743, 5.44009282066327e-15, -0.642039521920206, 6.61680659921524e-15, 0.642039521920207, 5.55111512312578e-15, -1.39680224666742, -1.90211303259031, -0.999999999999984, -2.10942374678780e-15, -0.221231742082475, -1.17557050458493, -1.26007351067011, -7.34788079488412e-15, 1.26007351067010, 1.17557050458494, 0.221231742082483, -2.33146835171283e-15, 1.00000000000000, 1.90211303259031, 1.39680224666741, 6.32827124036339e-15, -0.642039521920206, 5.88201851972683e-15, 0.642039521920207, -2.22044604925031e-14, -1.39680224666742, -1.90211303259031, -0.999999999999985, 8.43769498715119e-15, -0.221231742082475, -1.17557050458495, -1.26007351067009, 2.69546091939735e-14, 1.26007351067009, 1.17557050458496, 0.221231742082484, -2.77555756156289e-15, 1, 1.90211303259030, 1.39680224666743, 7.32747196252603e-15, -0.642039521920206, 5.14723044023841e-15, 0.642039521920205, 7.54951656745106e-15, -1.39680224666742, -1.90211303259031, -0.999999999999986, -2.99760216648792e-15, -0.221231742082474, -1.17557050458495, -1.26007351067009, -9.79717439317883e-15, 1.26007351067010, 1.17557050458494, 0.221231742082465, 7.88258347483861e-15, 0.999999999999999, 1.90211303259031, 1.39680224666741, -2.04281036531029e-14, -0.642039521920204, 4.41244236075000e-15, 0.642039521920207, 8.43769498715119e-15, -1.39680224666742, -1.90211303259031, -1.00000000000002, -3.33066907387547e-15, -0.221231742082473, -1.17557050458493, -1.26007351067011, -1.10218211923262e-14, 1.26007351067010, 1.17557050458494, 0.221231742082485, -3.44169137633799e-15, 0.999999999999998, 1.90211303259031, 1.39680224666741, 9.32587340685132e-15, -0.642039521920206, 3.67765428126159e-15, 0.642039521920207, -1.93178806284777e-14, -1.39680224666742, -1.90211303259031, -0.999999999999988, 7.32747196252603e-15, -0.221231742082492, -1.17557050458495, -1.26007351067009, 2.32806687965315e-14, 1.26007351067012, 1.17557050458494, 0.221231742082467, -1.47659662275146e-14, 0.999999999999969, 1.90211303259030, 1.39680224666744, 1.02140518265514e-14, -0.642039521920206, 2.94286620177318e-15, 0.642039521920207, -1.83186799063151e-14, -1.39680224666739, -1.90211303259031, -1.00000000000002, -4.10782519111308e-15, -0.221231742082472, -1.17557050458495, -1.26007351067010, 2.20560219973841e-14, 1.26007351067011, 1.17557050458493, 0.221231742082486, -4.21884749357560e-15, 0.999999999999996, 1.90211303259031, 1.39680224666741, -1.75415237890775e-14, -0.642039521920204, 2.35243601950878e-14, 0.642039521920209, 1.15463194561016e-14, -1.39680224666742, -1.90211303259031, -0.999999999999990, -1.54321000422897e-14, -0.221231742082452, -1.17557050458493, -1.26007351067011, -1.46957615897682e-14, 1.26007351067010, 1.17557050458495, 0.221231742082468, 6.32827124036339e-15, 1.00000000000002, 1.90211303259030, 1.39680224666744, 1.23234755733392e-14, -0.642039521920207, 1.47329004279635e-15, 0.642039521920207, -1.62092561595273e-14, -1.39680224666744, -1.90211303259030, -1.00000000000002, -4.88498130835069e-15, -0.221231742082471, -1.17557050458495, -1.26007351067010, 1.96067283990894e-14, 1.26007351067011, 1.17557050458493, 0.221231742082450, 1.69864122767649e-14, 0.999999999999994, 1.90211303259031, 1.39680224666741, -1.54321000422897e-14, -0.642039521920205, 2.20547840361110e-14, 0.642039521920209, -4.39648317751562e-14, -1.39680224666747, -1.90211303259031, -0.999999999999992, 5.77315972805081e-15, -0.221231742082489, -1.17557050458496, -1.26007351067008, 5.39092183879471e-14, 1.26007351067013, 1.17557050458498, 0.221231742082507, -1.63202784619898e-14, 0.999999999999965, 1.90211303259030, 1.39680224666744, 1.43218770176645e-14, -0.642039521920207, 3.71388381953015e-18, 0.642039521920203, 4.31876756579186e-14, -1.39680224666739, -1.90211303259031, -1.00000000000002, -5.55111512312578e-15, -0.221231742082469, -1.17557050458495, -1.26007351067010, 1.71574348007947e-14, 1.26007351067008, 1.17557050458496, 0.221231742082489, -5.77315972805081e-15, 0.999999999999992, 1.90211303259031, 1.39680224666741, -1.34336985979644e-14, -0.642039521920205, 2.05852078771341e-14, 0.642039521920205, 1.54321000422897e-14, -1.39680224666741, -1.90211303259031, -0.999999999999994, 4.99600361081320e-15, -0.221231742082488, -1.17557050458496, -1.26007351067008}; + float32_t pTapDelayScratch_f32[TEST_LENGTH_SAMPLES] = {0}; + +//q31_t + q31_t firStateq31[TEST_LENGTH_SAMPLES + NUM_TAPS - 1]; + q31_t testInput_q31_50Hz_200Hz[TEST_LENGTH_SAMPLES] = {0}, testOutput_q31[TEST_LENGTH_SAMPLES] = {0},testOutput_q31_ref[TEST_LENGTH_SAMPLES] = {0}; + q31_t firCoeffs32LP_q31[NUM_TAPS] = {0}; + q31_t pTapDelayScratch_q31[TEST_LENGTH_SAMPLES] = {0}; + +//q15_t + q15_t firStateq15[TEST_LENGTH_SAMPLES + NUM_TAPS - 1]; + q15_t testInput_q15_50Hz_200Hz[TEST_LENGTH_SAMPLES] = {0}, testOutput_q15[TEST_LENGTH_SAMPLES] = {0},testOutput_q15_ref[TEST_LENGTH_SAMPLES] = {0}; + q15_t firCoeffs32LP_q15[NUM_TAPS] = {0}; + q15_t pTapDelayScratch_q15[TEST_LENGTH_SAMPLES] = {0}; + q31_t pTapDelayScratchOUT[TEST_LENGTH_SAMPLES] = {0}; + +//q7_t + q7_t firStateq7[TEST_LENGTH_SAMPLES + NUM_TAPS - 1]; + q7_t testInput_q7_50Hz_200Hz[TEST_LENGTH_SAMPLES] = {0}, testOutput_q7[TEST_LENGTH_SAMPLES] = {0},testOutput_q7_ref[TEST_LENGTH_SAMPLES] = {0}; + q7_t firCoeffs32LP_q7[NUM_TAPS] = {0}; + q7_t pTapDelayScratch_q7[TEST_LENGTH_SAMPLES] = {0}; diff --git a/examples/dsp/FilteringFunction_firSparsePart/fir_sparse.c b/examples/dsp/FilteringFunction_firSparsePart/fir_sparse.c new file mode 100644 index 00000000..b12264b1 --- /dev/null +++ b/examples/dsp/FilteringFunction_firSparsePart/fir_sparse.c @@ -0,0 +1,459 @@ +#include "ref.h" + +void ref_fir_sparse_f32(riscv_fir_sparse_instance_f32 *S, float32_t *pSrc, + float32_t *pDst, float32_t *pScratchIn, + uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *px; /* Scratch buffer pointer */ + float32_t *py = pState; /* Temporary pointers for state buffer */ + float32_t *pb = pScratchIn; /* Temporary pointers for scratch buffer */ + float32_t *pOut; /* Destination pointer */ + int32_t *pTapDelay = S->pTapDelay; /* Pointer to the array containing offset + of the non-zero tap values. */ + uint32_t delaySize = S->maxDelay + blockSize; /* state length */ + uint16_t numTaps = + S->numTaps; /* Number of filter coefficients in the filter */ + int32_t readIndex; /* Read index of the state buffer */ + uint32_t tapCnt, blkCnt; /* loop counters */ + float32_t coeff = *pCoeffs++; /* Read the first coefficient value */ + + /* BlockSize of Input samples are copied into the state buffer */ + /* StateIndex points to the starting position to write in the state buffer + */ + riscv_circularWrite_f32((int32_t *)py, delaySize, &S->stateIndex, 1, + (int32_t *)pSrc, 1, blockSize); + + /* Read Index, from where the state buffer should be read, is calculated. */ + readIndex = ((int32_t)S->stateIndex - (int32_t)blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) { + readIndex += (int32_t)delaySize; + } + + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + riscv_circularRead_f32((int32_t *)py, delaySize, &readIndex, 1, (int32_t *)pb, + (int32_t *)pb, blockSize, 1, blockSize); + + /* Working pointer for the scratch buffer */ + px = pb; + + /* Working pointer for destination buffer */ + pOut = pDst; + + blkCnt = blockSize; + + while (blkCnt > 0U) { + /* Perform Multiplications and store in destination buffer */ + *pOut++ = *px++ * coeff; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Loop over the number of taps. */ + tapCnt = (uint32_t)numTaps - 1U; + + while (tapCnt > 0U) { + /* Load the coefficient value and + * increment the coefficient buffer for the next set of state values */ + coeff = *pCoeffs++; + + /* Read Index, from where the state buffer should be read, is + * calculated. */ + readIndex = + ((int32_t)S->stateIndex - (int32_t)blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) { + readIndex += (int32_t)delaySize; + } + + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + riscv_circularRead_f32((int32_t *)py, delaySize, &readIndex, 1, + (int32_t *)pb, (int32_t *)pb, blockSize, 1, + blockSize); + + /* Working pointer for the scratch buffer */ + px = pb; + + /* Working pointer for destination buffer */ + pOut = pDst; + + blkCnt = blockSize; + + while (blkCnt > 0U) { + /* Perform Multiply-Accumulate */ + *pOut++ += *px++ * coeff; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Decrement the tap loop counter */ + tapCnt--; + } +} + +void ref_fir_sparse_q31(riscv_fir_sparse_instance_q31 *S, q31_t *pSrc, + q31_t *pDst, q31_t *pScratchIn, uint32_t blockSize) +{ + q31_t *pState = S->pState; /* State pointer */ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *px; /* Scratch buffer pointer */ + q31_t *py = pState; /* Temporary pointers for state buffer */ + q31_t *pb = pScratchIn; /* Temporary pointers for scratch buffer */ + q31_t *pOut; /* Destination pointer */ + q63_t out; /* Temporary output variable */ + int32_t *pTapDelay = S->pTapDelay; /* Pointer to the array containing offset + of the non-zero tap values. */ + uint32_t delaySize = S->maxDelay + blockSize; /* state length */ + uint16_t numTaps = S->numTaps; /* Filter order */ + int32_t readIndex; /* Read index of the state buffer */ + uint32_t tapCnt, blkCnt; /* loop counters */ + q31_t coeff = *pCoeffs++; /* Read the first coefficient value */ + q31_t in; + + /* BlockSize of Input samples are copied into the state buffer */ + /* StateIndex points to the starting position to write in the state buffer + */ + riscv_circularWrite_f32((int32_t *)py, delaySize, &S->stateIndex, 1, + (int32_t *)pSrc, 1, blockSize); + + /* Read Index, from where the state buffer should be read, is calculated. */ + readIndex = (int32_t)(S->stateIndex - blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) { + readIndex += (int32_t)delaySize; + } + + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + riscv_circularRead_f32((int32_t *)py, delaySize, &readIndex, 1, (int32_t *)pb, + (int32_t *)pb, blockSize, 1, blockSize); + + /* Working pointer for the scratch buffer of state values */ + px = pb; + + /* Working pointer for scratch buffer of output values */ + pOut = pDst; + + blkCnt = blockSize; + + while (blkCnt > 0U) { + /* Perform Multiplications and store in the destination buffer */ + *pOut++ = (q31_t)(((q63_t)*px++ * coeff) >> 32); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Loop over the number of taps. */ + tapCnt = (uint32_t)numTaps - 1U; + + while (tapCnt > 0U) { + /* Load the coefficient value and + * increment the coefficient buffer for the next set of state values */ + coeff = *pCoeffs++; + + /* Read Index, from where the state buffer should be read, is + * calculated. */ + readIndex = (int32_t)(S->stateIndex - blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) { + readIndex += (int32_t)delaySize; + } + + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + riscv_circularRead_f32((int32_t *)py, delaySize, &readIndex, 1, + (int32_t *)pb, (int32_t *)pb, blockSize, 1, + blockSize); + + /* Working pointer for the scratch buffer of state values */ + px = pb; + + /* Working pointer for scratch buffer of output values */ + pOut = pDst; + + blkCnt = blockSize; + + while (blkCnt > 0U) { + /* Perform Multiply-Accumulate */ + out = *pOut; + out += ((q63_t)*px++ * coeff) >> 32; + *pOut++ = (q31_t)(out); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Decrement the tap loop counter */ + tapCnt--; + } + + /* Working output pointer is updated */ + pOut = pDst; + + /* Output is converted into 1.31 format. */ + blkCnt = blockSize; + + while (blkCnt > 0U) { + in = *pOut << 1; + *pOut++ = in; + + /* Decrement the loop counter */ + blkCnt--; + } +} + +void ref_fir_sparse_q15(riscv_fir_sparse_instance_q15 *S, q15_t *pSrc, + q15_t *pDst, q15_t *pScratchIn, q31_t *pScratchOut, + uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pIn = pSrc; /* Working pointer for input */ + q15_t *pOut = pDst; /* Working pointer for output */ + q15_t *px; /* Temporary pointers for scratch buffer */ + q15_t *pb = pScratchIn; /* Temporary pointers for scratch buffer */ + q15_t *py = pState; /* Temporary pointers for state buffer */ + int32_t *pTapDelay = S->pTapDelay; /* Pointer to the array containing offset + of the non-zero tap values. */ + uint32_t delaySize = S->maxDelay + blockSize; /* state length */ + uint16_t numTaps = S->numTaps; /* Filter order */ + int32_t readIndex; /* Read index of the state buffer */ + uint32_t tapCnt, blkCnt; /* loop counters */ + q15_t coeff = *pCoeffs++; /* Read the first coefficient value */ + q31_t *pScr2 = pScratchOut; /* Working pointer for pScratchOut */ + + /* BlockSize of Input samples are copied into the state buffer */ + /* StateIndex points to the starting position to write in the state buffer + */ + riscv_circularWrite_q15(py, delaySize, &S->stateIndex, 1, pIn, 1, blockSize); + + /* Loop over the number of taps. */ + tapCnt = numTaps; + + /* Read Index, from where the state buffer should be read, is calculated. */ + readIndex = (S->stateIndex - blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) { + readIndex += (int32_t)delaySize; + } + + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + riscv_circularRead_q15(py, delaySize, &readIndex, 1, pb, pb, blockSize, 1, + blockSize); + + /* Working pointer for the scratch buffer of state values */ + px = pb; + + /* Working pointer for scratch buffer of output values */ + pScratchOut = pScr2; + + blkCnt = blockSize; + + while (blkCnt > 0U) { + /* Perform multiplication and store in the scratch buffer */ + *pScratchOut++ = ((q31_t)*px++ * coeff); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Loop over the number of taps. */ + tapCnt = (uint32_t)numTaps - 1U; + + while (tapCnt > 0U) { + /* Load the coefficient value and + * increment the coefficient buffer for the next set of state values */ + coeff = *pCoeffs++; + + /* Read Index, from where the state buffer should be read, is + * calculated. */ + readIndex = (S->stateIndex - blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) { + readIndex += (int32_t)delaySize; + } + + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + riscv_circularRead_q15(py, delaySize, &readIndex, 1, pb, pb, blockSize, 1, + blockSize); + + /* Working pointer for the scratch buffer of state values */ + px = pb; + + /* Working pointer for scratch buffer of output values */ + pScratchOut = pScr2; + + blkCnt = blockSize; + + while (blkCnt > 0U) { + /* Perform Multiply-Accumulate */ + *pScratchOut++ += (q31_t)*px++ * coeff; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Decrement the tap loop counter */ + tapCnt--; + } + + /* All the output values are in pScratchOut buffer. + Convert them into 1.15 format, saturate and store in the destination + buffer. */ + /* Loop over the blockSize. */ + blkCnt = blockSize; + + while (blkCnt > 0U) { + *pOut++ = (q15_t)__SSAT(*pScr2++ >> 15, 16); + blkCnt--; + } +} + +void ref_fir_sparse_q7(riscv_fir_sparse_instance_q7 *S, q7_t *pSrc, q7_t *pDst, + q7_t *pScratchIn, q31_t *pScratchOut, uint32_t blockSize) +{ + q7_t *pState = S->pState; /* State pointer */ + const q7_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q7_t *px; /* Scratch buffer pointer */ + q7_t *py = pState; /* Temporary pointers for state buffer */ + q7_t *pb = pScratchIn; /* Temporary pointers for scratch buffer */ + q7_t *pOut = pDst; /* Destination pointer */ + int32_t *pTapDelay = S->pTapDelay; /* Pointer to the array containing offset + of the non-zero tap values. */ + uint32_t delaySize = S->maxDelay + blockSize; /* state length */ + uint16_t numTaps = S->numTaps; /* Filter order */ + int32_t readIndex; /* Read index of the state buffer */ + uint32_t tapCnt, blkCnt; /* loop counters */ + q7_t coeff = *pCoeffs++; /* Read the coefficient value */ + q31_t *pScr2 = + pScratchOut; /* Working pointer for scratch buffer of output values */ + q31_t in; + + /* BlockSize of Input samples are copied into the state buffer */ + /* StateIndex points to the starting position to write in the state buffer + */ + riscv_circularWrite_q7(py, (int32_t)delaySize, &S->stateIndex, 1, pSrc, 1, + blockSize); + + /* Loop over the number of taps. */ + tapCnt = numTaps; + + /* Read Index, from where the state buffer should be read, is calculated. */ + readIndex = ((int32_t)S->stateIndex - (int32_t)blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) { + readIndex += (int32_t)delaySize; + } + + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + riscv_circularRead_q7(py, (int32_t)delaySize, &readIndex, 1, pb, pb, + (int32_t)blockSize, 1, blockSize); + + /* Working pointer for the scratch buffer of state values */ + px = pb; + + /* Working pointer for scratch buffer of output values */ + pScratchOut = pScr2; + + /* Loop over the blockSize */ + blkCnt = blockSize; + + while (blkCnt > 0U) { + /* Perform multiplication and store in the scratch buffer */ + *pScratchOut++ = ((q31_t)*px++ * coeff); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Loop over the number of taps. */ + tapCnt = (uint32_t)numTaps - 1U; + + while (tapCnt > 0U) { + /* Load the coefficient value and + * increment the coefficient buffer for the next set of state values */ + coeff = *pCoeffs++; + + /* Read Index, from where the state buffer should be read, is + * calculated. */ + readIndex = + ((int32_t)S->stateIndex - (int32_t)blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) { + readIndex += (int32_t)delaySize; + } + + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + riscv_circularRead_q7(py, (int32_t)delaySize, &readIndex, 1, pb, pb, + (int32_t)blockSize, 1, blockSize); + + /* Working pointer for the scratch buffer of state values */ + px = pb; + + /* Working pointer for scratch buffer of output values */ + pScratchOut = pScr2; + + /* Loop over the blockSize */ + blkCnt = blockSize; + + while (blkCnt > 0U) { + /* Perform Multiply-Accumulate */ + in = *pScratchOut + ((q31_t)*px++ * coeff); + *pScratchOut++ = in; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Decrement the tap loop counter */ + tapCnt--; + } + + /* All the output values are in pScratchOut buffer. + Convert them into 1.15 format, saturate and store in the destination + buffer. */ + /* Loop over the blockSize. */ + blkCnt = blockSize; + + while (blkCnt > 0U) { + *pOut++ = (q7_t)__SSAT(*pScr2++ >> 7, 8); + + /* Decrement the blockSize loop counter */ + blkCnt--; + } +} diff --git a/examples/dsp/FilteringFunction_firSparsePart/main.c b/examples/dsp/FilteringFunction_firSparsePart/main.c new file mode 100644 index 00000000..1a8fc92a --- /dev/null +++ b/examples/dsp/FilteringFunction_firSparsePart/main.c @@ -0,0 +1,206 @@ +// +// Created by lujun on 19-6-28. +// +// This contains fir, iir and lms filters +// each one has it's own function. +// All function can be found in main function. +// If you don't want to use it, then comment it. +// +// This part only tests result after 50 dots.If you want to test results' all +// dots, please define WITH_FRONT +// +// If there are too much numbers which makes it hard to read,in VScode you can +// press alt and z can shrimp them to one line +// +// You MUST be careful about overflow. +#include "riscv_math.h" +#include "array.h" +#include +#include "../common.h" + +#include "../HelperFunctions/math_helper.c" +#include "../HelperFunctions/ref_helper.c" + +#include +#define DELTAF32 (0.05f) +#define DELTAQ31 (63) +#define DELTAQ15 (1) +#define DELTAQ7 (1) +#define SNR_THRESHOLD_F32 (80.0f) + +int test_flag_error = 0; + +// #define WITH_FRONT + +//*************************************************************************************** +// fir Sparse Filters +//*************************************************************************************** +static void riscv_fir_Sparse_f32_lp(void) +{ + uint32_t i; + /* clang-format off */ + riscv_fir_sparse_instance_f32 S; + /* clang-format on */ + for (i = 0; i < NUM_TAPS; i++) + pTapDelay[i] = i + 1; + riscv_fir_sparse_init_f32(&S, NUM_TAPS, &firCoeffs32LP[0], &firStatef32[0], &pTapDelay[0], MAXDelay, TEST_LENGTH_SAMPLES); + BENCH_START(riscv_fir_sparse_f32); + riscv_fir_sparse_f32(&S, testInput_f32_50Hz_200Hz, testOutput_f32, &pTapDelayScratch_f32[0], TEST_LENGTH_SAMPLES); + BENCH_END(riscv_fir_sparse_f32); + riscv_fir_sparse_init_f32(&S, NUM_TAPS, &firCoeffs32LP[0], &firStatef32[0], &pTapDelay[0], MAXDelay, TEST_LENGTH_SAMPLES); + ref_fir_sparse_f32(&S, testInput_f32_50Hz_200Hz, testOutput_f32_ref, &pTapDelayScratch_f32[0], TEST_LENGTH_SAMPLES); +#ifndef WITH_FRONT + float snr = riscv_snr_f32(&testOutput_f32_ref[50], &testOutput_f32[50], 269); + + if (snr < SNR_THRESHOLD_F32) { + BENCH_ERROR(riscv_fir_sparse_f32); + printf("f32 fir_Sparse failed with snr:%f\n", snr); + test_flag_error = 1; + } + BENCH_STATUS(riscv_fir_sparse_f32); +#else + float snr = + riscv_snr_f32(&testOutput_ref[0], &testOutput[0], TEST_LENGTH_SAMPLES); + + if (snr < SNR_THRESHOLD_F32) { + BENCH_ERROR(riscv_fir_sparse_f32); + printf("f32 fir_Sparse failed with snr:%f\n", snr); + test_flag_error = 1; + } + BENCH_STATUS(riscv_fir_sparse_f32); +#endif +} +static void riscv_fir_Sparse_q31_lp(void) +{ + uint32_t i; + /* clang-format off */ + riscv_fir_sparse_instance_q31 S; + /* clang-format on */ + riscv_float_to_q31(testInput_f32_50Hz_200Hz, testInput_q31_50Hz_200Hz, TEST_LENGTH_SAMPLES); + riscv_float_to_q31(firCoeffs32LP, firCoeffs32LP_q31, NUM_TAPS); + for (i = 0; i < NUM_TAPS; i++) + pTapDelay[i] = i + 1; + riscv_fir_sparse_init_q31(&S, NUM_TAPS, &firCoeffs32LP_q31[0], &firStateq31[0], &pTapDelay[0], MAXDelay, TEST_LENGTH_SAMPLES); + BENCH_START(riscv_fir_sparse_q31); + riscv_fir_sparse_q31(&S, testInput_q31_50Hz_200Hz, testOutput_q31, &pTapDelayScratch_q31[0], TEST_LENGTH_SAMPLES); + BENCH_END(riscv_fir_sparse_q31); + riscv_fir_sparse_init_q31(&S, NUM_TAPS, &firCoeffs32LP_q31[0], &firStateq31[0], &pTapDelay[0], MAXDelay, TEST_LENGTH_SAMPLES); + ref_fir_sparse_q31(&S, testInput_q31_50Hz_200Hz, testOutput_q31_ref, &pTapDelayScratch_q31[0], TEST_LENGTH_SAMPLES); + riscv_q31_to_float(testOutput_q31, testOutput_f32, TEST_LENGTH_SAMPLES); + riscv_q31_to_float(testOutput_q31_ref, testOutput_f32_ref, TEST_LENGTH_SAMPLES); +#ifndef WITH_FRONT + float snr = riscv_snr_f32(&testOutput_f32_ref[50], &testOutput_f32[50], 269); + + if (snr < SNR_THRESHOLD_F32) { + BENCH_ERROR(riscv_fir_sparse_q31); + printf("q31 fir_Sparse failed with snr:%f\n", snr); + test_flag_error = 1; + } + BENCH_STATUS(riscv_fir_sparse_q31); +#else + float snr = riscv_snr_f32(&testOutput_f32_ref[0], &testOutput_f32[0], + TEST_LENGTH_SAMPLES); + + if (snr < SNR_THRESHOLD_F32) { + BENCH_ERROR(riscv_fir_sparse_q31); + printf("q31 fir_Sparse failed with snr:%f\n", snr); + test_flag_error = 1; + } + BENCH_STATUS(riscv_fir_sparse_q31); +#endif +} +static void riscv_fir_Sparse_q15_lp(void) +{ + uint32_t i; + /* clang-format off */ + riscv_fir_sparse_instance_q15 S; + /* clang-format on */ + riscv_float_to_q15(testInput_f32_50Hz_200Hz, testInput_q15_50Hz_200Hz, TEST_LENGTH_SAMPLES); + riscv_float_to_q15(firCoeffs32LP, firCoeffs32LP_q15, 29); + for (i = 0; i < NUM_TAPS; i++) + pTapDelay[i] = i + 1; + riscv_fir_sparse_init_q15(&S, NUM_TAPS, &firCoeffs32LP_q15[0], &firStateq15[0], &pTapDelay[0], MAXDelay, TEST_LENGTH_SAMPLES); + BENCH_START(riscv_fir_sparse_q15); + riscv_fir_sparse_q15(&S, testInput_q15_50Hz_200Hz, testOutput_q15, pTapDelayScratch_q15, pTapDelayScratchOUT, TEST_LENGTH_SAMPLES); + BENCH_END(riscv_fir_sparse_q15); + riscv_fir_sparse_init_q15(&S, NUM_TAPS, &firCoeffs32LP_q15[0], &firStateq15[0], &pTapDelay[0], MAXDelay, TEST_LENGTH_SAMPLES); + ref_fir_sparse_q15(&S, testInput_q15_50Hz_200Hz, testOutput_q15_ref, pTapDelayScratch_q15, pTapDelayScratchOUT, TEST_LENGTH_SAMPLES); + riscv_q15_to_float(testOutput_q15, testOutput_f32, TEST_LENGTH_SAMPLES); + riscv_q15_to_float(testOutput_q15_ref, testOutput_f32_ref, TEST_LENGTH_SAMPLES); +#ifndef WITH_FRONT + float snr = riscv_snr_f32(&testOutput_f32_ref[50], &testOutput_f32[50], 269); + + if (snr < SNR_THRESHOLD_F32) { + BENCH_ERROR(riscv_fir_sparse_q15); + printf("q15 fir_Sparse failed with snr:%f\n", snr); + test_flag_error = 1; + } + BENCH_STATUS(riscv_fir_sparse_q15); +#else + float snr = riscv_snr_f32(&testOutput_f32_ref[0], &testOutput_f32[0], + TEST_LENGTH_SAMPLES); + + if (snr < SNR_THRESHOLD_F32) { + BENCH_ERROR(riscv_fir_sparse_q15); + printf("q15 fir_Sparse failed with snr:%f\n", snr); + test_flag_error = 1; + } + BENCH_STATUS(riscv_fir_sparse_q15); +#endif +} +static void riscv_fir_Sparse_q7_lp(void) +{ + uint32_t i; + /* clang-format off */ + riscv_fir_sparse_instance_q7 S; + /* clang-format on */ + riscv_float_to_q7(testInput_f32_50Hz_200Hz, testInput_q7_50Hz_200Hz, TEST_LENGTH_SAMPLES); + riscv_float_to_q7(firCoeffs32LP, firCoeffs32LP_q7, NUM_TAPS); + for (i = 0; i < NUM_TAPS; i++) + pTapDelay[i] = i + 1; + riscv_fir_sparse_init_q7(&S, NUM_TAPS, &firCoeffs32LP_q7[0], &firStateq7[0], &pTapDelay[0], MAXDelay, TEST_LENGTH_SAMPLES); + BENCH_START(riscv_fir_sparse_q7); + riscv_fir_sparse_q7(&S, testInput_q7_50Hz_200Hz, testOutput_q7, &pTapDelayScratch_q7[0], pTapDelayScratchOUT, TEST_LENGTH_SAMPLES); + BENCH_END(riscv_fir_sparse_q7); + riscv_fir_sparse_init_q7(&S, NUM_TAPS, &firCoeffs32LP_q7[0], &firStateq7[0], &pTapDelay[0], MAXDelay, TEST_LENGTH_SAMPLES); + ref_fir_sparse_q7(&S, testInput_q7_50Hz_200Hz, testOutput_q7_ref, &pTapDelayScratch_q7[0], pTapDelayScratchOUT, TEST_LENGTH_SAMPLES); + riscv_q7_to_float(testOutput_q7, testOutput_f32, TEST_LENGTH_SAMPLES); + riscv_q7_to_float(testOutput_q7_ref, testOutput_f32_ref, TEST_LENGTH_SAMPLES); +#ifndef WITH_FRONT + float snr = riscv_snr_f32(&testOutput_f32_ref[50], &testOutput_f32[50], 269); + + if (snr < SNR_THRESHOLD_F32) { + BENCH_ERROR(riscv_fir_sparse_q7); + printf("q7 fir_Sparse failed with snr:%f\n", snr); + test_flag_error = 1; + } + BENCH_STATUS(riscv_fir_sparse_q7); +#else + float snr = riscv_snr_f32(&testOutput_f32_ref[0], &testOutput_f32[0], + TEST_LENGTH_SAMPLES); + + if (snr < SNR_THRESHOLD_F32) { + BENCH_ERROR(riscv_fir_sparse_q7); + printf("q7 fir_Sparse failed with snr:%f\n", snr); + test_flag_error = 1; + } + BENCH_STATUS(riscv_fir_sparse_q7); +#endif +} + +int main() +{ + BENCH_INIT; + riscv_fir_Sparse_f32_lp(); + riscv_fir_Sparse_q31_lp(); + riscv_fir_Sparse_q15_lp(); + riscv_fir_Sparse_q7_lp(); + BENCH_FINISH; + if (test_flag_error) { + printf("test error apprears, please recheck.\n"); + return 1; + } else { + printf("all test are passed. Well done!\n"); + } + return 0; +} diff --git a/examples/dsp/FilteringFunction_iirLatticePart/CMakeLists.txt b/examples/dsp/FilteringFunction_iirLatticePart/CMakeLists.txt new file mode 100644 index 00000000..9507b479 --- /dev/null +++ b/examples/dsp/FilteringFunction_iirLatticePart/CMakeLists.txt @@ -0,0 +1,5 @@ +set(TARGET_REQUIRED_PRIVATE_INCLUDE ${CMAKE_CURRENT_SOURCE_DIR} ${CMAKE_CURRENT_SOURCE_DIR}/..) +set(TARGET_REQUIRED_SRCS iir_lattice.c) +set(TARGET_REQUIRED_LIBS nmsis) +set(mains main.c) +generate_bin() \ No newline at end of file diff --git a/examples/dsp/FilteringFunction_iirLatticePart/array.h b/examples/dsp/FilteringFunction_iirLatticePart/array.h new file mode 100644 index 00000000..cc73c19e --- /dev/null +++ b/examples/dsp/FilteringFunction_iirLatticePart/array.h @@ -0,0 +1,24 @@ +// Array for FilteringFunctions iirLatticePart +#define TEST_LENGTH_SAMPLES 320 /* 采样点数 */ +#define numStages 8 /* 2阶IIR滤波的个数 */ +// float32_t +// stereo requires 2*TEST_LENGTH_SAMPLES + float32_t testOutput_f32[TEST_LENGTH_SAMPLES],testOutput_f32_ref[TEST_LENGTH_SAMPLES]; + float32_t IIRStateF32[TEST_LENGTH_SAMPLES+numStages]={0}; + float32_t IIRCoeffs32LP_K[numStages] = {-0.9490513802f, 0.960866034f, -0.950527668f, 0.9305356741f, -0.8808346987f, 0.7298035026f, -0.3796664774f, 0.07335939258f}; + float32_t IIRCoeffs32LP_V[numStages+1] = {0.0004670530325f, 0.002966811415f, 0.006142409053f, 0.006682873704f, 0.004372655414f, 0.00177692459f, 0.0004465713282f, 6.86832791e-05f, 5.115610293e-06f}; + float32_t testInput_f32_50Hz_200Hz[TEST_LENGTH_SAMPLES] = {0, 1.26007351067010, 1.17557050458495, 0.221231742082474, -1.11022302462516e-16, 1.00000000000000, 1.90211303259031, 1.39680224666742, 4.44089209850063e-16, -0.642039521920206, -3.67394039744206e-16, 0.642039521920206, -1.22124532708767e-15, -1.39680224666742, -1.90211303259031, -1.00000000000000, -3.33066907387547e-16, -0.221231742082476, -1.17557050458495, -1.26007351067010, -1.22464679914735e-15, 1.26007351067010, 1.17557050458495, 0.221231742082475, 8.88178419700125e-16, 1.00000000000000, 1.90211303259031, 1.39680224666742, 1.33226762955019e-15, -0.642039521920206, -1.10218211923262e-15, 0.642039521920206, 1.55431223447522e-15, -1.39680224666743, -1.90211303259031, -0.999999999999995, -7.77156117237610e-16, -0.221231742082473, -1.17557050458495, -1.26007351067010, -2.44929359829471e-15, 1.26007351067010, 1.17557050458494, 0.221231742082476, -7.77156117237610e-16, 0.999999999999998, 1.90211303259031, 1.39680224666742, -4.88498130835069e-15, -0.642039521920206, 3.49210031947972e-15, 0.642039521920206, 2.55351295663786e-15, -1.39680224666742, -1.90211303259031, -0.999999999999996, -9.99200722162641e-16, -0.221231742082477, -1.17557050458494, -1.26007351067011, -3.67394039744206e-15, 1.26007351067010, 1.17557050458495, 0.221231742082472, -1.22124532708767e-15, 1.00000000000000, 1.90211303259031, 1.39680224666742, -1.09912079437891e-14, -0.642039521920206, 8.08638275819206e-15, 0.642039521920205, 3.55271367880050e-15, -1.39680224666741, -1.90211303259031, -0.999999999999997, -1.44328993201270e-15, -0.221231742082476, -1.17557050458494, -1.26007351067010, -4.89858719658941e-15, 1.26007351067010, 1.17557050458494, 0.221231742082472, 3.88578058618805e-15, 1.00000000000000, 1.90211303259031, 1.39680224666743, 4.44089209850063e-15, -0.642039521920207, -3.30654635769785e-15, 0.642039521920206, 4.55191440096314e-15, -1.39680224666742, -1.90211303259031, -0.999999999999998, 3.66373598126302e-15, -0.221231742082476, -1.17557050458495, -1.26007351067010, 1.16403343982657e-14, 1.26007351067010, 1.17557050458496, 0.221231742082482, -1.99840144432528e-15, 1.00000000000000, 1.90211303259031, 1.39680224666743, 5.44009282066327e-15, -0.642039521920206, 6.61680659921524e-15, 0.642039521920207, 5.55111512312578e-15, -1.39680224666742, -1.90211303259031, -0.999999999999984, -2.10942374678780e-15, -0.221231742082475, -1.17557050458493, -1.26007351067011, -7.34788079488412e-15, 1.26007351067010, 1.17557050458494, 0.221231742082483, -2.33146835171283e-15, 1.00000000000000, 1.90211303259031, 1.39680224666741, 6.32827124036339e-15, -0.642039521920206, 5.88201851972683e-15, 0.642039521920207, -2.22044604925031e-14, -1.39680224666742, -1.90211303259031, -0.999999999999985, 8.43769498715119e-15, -0.221231742082475, -1.17557050458495, -1.26007351067009, 2.69546091939735e-14, 1.26007351067009, 1.17557050458496, 0.221231742082484, -2.77555756156289e-15, 1, 1.90211303259030, 1.39680224666743, 7.32747196252603e-15, -0.642039521920206, 5.14723044023841e-15, 0.642039521920205, 7.54951656745106e-15, -1.39680224666742, -1.90211303259031, -0.999999999999986, -2.99760216648792e-15, -0.221231742082474, -1.17557050458495, -1.26007351067009, -9.79717439317883e-15, 1.26007351067010, 1.17557050458494, 0.221231742082465, 7.88258347483861e-15, 0.999999999999999, 1.90211303259031, 1.39680224666741, -2.04281036531029e-14, -0.642039521920204, 4.41244236075000e-15, 0.642039521920207, 8.43769498715119e-15, -1.39680224666742, -1.90211303259031, -1.00000000000002, -3.33066907387547e-15, -0.221231742082473, -1.17557050458493, -1.26007351067011, -1.10218211923262e-14, 1.26007351067010, 1.17557050458494, 0.221231742082485, -3.44169137633799e-15, 0.999999999999998, 1.90211303259031, 1.39680224666741, 9.32587340685132e-15, -0.642039521920206, 3.67765428126159e-15, 0.642039521920207, -1.93178806284777e-14, -1.39680224666742, -1.90211303259031, -0.999999999999988, 7.32747196252603e-15, -0.221231742082492, -1.17557050458495, -1.26007351067009, 2.32806687965315e-14, 1.26007351067012, 1.17557050458494, 0.221231742082467, -1.47659662275146e-14, 0.999999999999969, 1.90211303259030, 1.39680224666744, 1.02140518265514e-14, -0.642039521920206, 2.94286620177318e-15, 0.642039521920207, -1.83186799063151e-14, -1.39680224666739, -1.90211303259031, -1.00000000000002, -4.10782519111308e-15, -0.221231742082472, -1.17557050458495, -1.26007351067010, 2.20560219973841e-14, 1.26007351067011, 1.17557050458493, 0.221231742082486, -4.21884749357560e-15, 0.999999999999996, 1.90211303259031, 1.39680224666741, -1.75415237890775e-14, -0.642039521920204, 2.35243601950878e-14, 0.642039521920209, 1.15463194561016e-14, -1.39680224666742, -1.90211303259031, -0.999999999999990, -1.54321000422897e-14, -0.221231742082452, -1.17557050458493, -1.26007351067011, -1.46957615897682e-14, 1.26007351067010, 1.17557050458495, 0.221231742082468, 6.32827124036339e-15, 1.00000000000002, 1.90211303259030, 1.39680224666744, 1.23234755733392e-14, -0.642039521920207, 1.47329004279635e-15, 0.642039521920207, -1.62092561595273e-14, -1.39680224666744, -1.90211303259030, -1.00000000000002, -4.88498130835069e-15, -0.221231742082471, -1.17557050458495, -1.26007351067010, 1.96067283990894e-14, 1.26007351067011, 1.17557050458493, 0.221231742082450, 1.69864122767649e-14, 0.999999999999994, 1.90211303259031, 1.39680224666741, -1.54321000422897e-14, -0.642039521920205, 2.20547840361110e-14, 0.642039521920209, -4.39648317751562e-14, -1.39680224666747, -1.90211303259031, -0.999999999999992, 5.77315972805081e-15, -0.221231742082489, -1.17557050458496, -1.26007351067008, 5.39092183879471e-14, 1.26007351067013, 1.17557050458498, 0.221231742082507, -1.63202784619898e-14, 0.999999999999965, 1.90211303259030, 1.39680224666744, 1.43218770176645e-14, -0.642039521920207, 3.71388381953015e-18, 0.642039521920203, 4.31876756579186e-14, -1.39680224666739, -1.90211303259031, -1.00000000000002, -5.55111512312578e-15, -0.221231742082469, -1.17557050458495, -1.26007351067010, 1.71574348007947e-14, 1.26007351067008, 1.17557050458496, 0.221231742082489, -5.77315972805081e-15, 0.999999999999992, 1.90211303259031, 1.39680224666741, -1.34336985979644e-14, -0.642039521920205, 2.05852078771341e-14, 0.642039521920205, 1.54321000422897e-14, -1.39680224666741, -1.90211303259031, -0.999999999999994, 4.99600361081320e-15, -0.221231742082488, -1.17557050458496, -1.26007351067008}; + +// q31_t + q31_t testOutput_q31[TEST_LENGTH_SAMPLES],testOutput_q31_ref[TEST_LENGTH_SAMPLES]; + q31_t IIRStateQ31[TEST_LENGTH_SAMPLES+numStages]={0}; + q31_t IIRCoeffs32LP_K_q31[numStages]; + q31_t IIRCoeffs32LP_V_q31[numStages+1]; + q31_t testInput_q31_50Hz_200Hz[TEST_LENGTH_SAMPLES]; + +// q15_t + q15_t testOutput_q15[TEST_LENGTH_SAMPLES],testOutput_q15_ref[TEST_LENGTH_SAMPLES]; + q15_t IIRStateQ15[TEST_LENGTH_SAMPLES+numStages]={0}; + q15_t IIRCoeffs32LP_K_q15[numStages]; + q15_t IIRCoeffs32LP_V_q15[numStages+1]; + q15_t testInput_q15_50Hz_200Hz[TEST_LENGTH_SAMPLES]; \ No newline at end of file diff --git a/examples/dsp/FilteringFunction_iirLatticePart/iir_lattice.c b/examples/dsp/FilteringFunction_iirLatticePart/iir_lattice.c new file mode 100644 index 00000000..21e27eff --- /dev/null +++ b/examples/dsp/FilteringFunction_iirLatticePart/iir_lattice.c @@ -0,0 +1,257 @@ +#include "ref.h" + +void ref_iir_lattice_f32(const riscv_iir_lattice_instance_f32 *S, float32_t *pSrc, + float32_t *pDst, uint32_t blockSize) +{ + float32_t fcurr, fnext = 0, gcurr, + gnext; /* Temporary variables for lattice stages */ + float32_t acc; /* Accumlator */ + uint32_t blkCnt, tapCnt; /* temporary variables for counts */ + float32_t *px1, *px2, *pk, *pv; /* temporary pointers for state and coef */ + uint32_t numStages = S->numStages; /* number of stages */ + float32_t *pState; /* State pointer */ + float32_t *pStateCurnt; /* State current pointer */ + + blkCnt = blockSize; + pState = &S->pState[0]; + + /* Sample processing */ + while (blkCnt > 0U) { + /* Read Sample from input buffer */ + /* fN(n) = x(n) */ + fcurr = *pSrc++; + + /* Initialize state read pointer */ + px1 = pState; + /* Initialize state write pointer */ + px2 = pState; + /* Set accumulator to zero */ + acc = 0.0f; + /* Initialize Ladder coeff pointer */ + pv = &S->pvCoeffs[0]; + /* Initialize Reflection coeff pointer */ + pk = &S->pkCoeffs[0]; + + /* Process sample for numStages */ + tapCnt = numStages; + + while (tapCnt > 0U) { + gcurr = *px1++; + /* Process sample for last taps */ + fnext = fcurr - (*pk) * gcurr; + gnext = fnext * (*pk++) + gcurr; + + /* Output samples for last taps */ + acc += gnext * (*pv++); + *px2++ = gnext; + fcurr = fnext; + + /* Decrementing loop counter */ + tapCnt--; + } + + /* y(n) += g0(n) * v0 */ + acc += fnext * (*pv); + + *px2++ = fnext; + + /* write out into pDst */ + *pDst++ = acc; + + /* Advance the state pointer by 1 to process the next group of samples + */ + pState = pState + 1U; + blkCnt--; + } + + /* Processing is complete. Now copy last S->numStages samples to start of + the buffer for the preperation of next frame process */ + + /* Points to the start of the state buffer */ + pStateCurnt = &S->pState[0]; + pState = &S->pState[blockSize]; + + tapCnt = numStages; + + /* Copy the data */ + while (tapCnt > 0U) { + *pStateCurnt++ = *pState++; + + /* Decrement the loop counter */ + tapCnt--; + } +} + +void ref_iir_lattice_q31(const riscv_iir_lattice_instance_q31 *S, q31_t *pSrc, + q31_t *pDst, uint32_t blockSize) +{ + q31_t fcurr, fnext = 0, gcurr = 0, + gnext; /* Temporary variables for lattice stages */ + q63_t acc; /* Accumlator */ + uint32_t blkCnt, tapCnt; /* Temporary variables for counts */ + q31_t *px1, *px2, *pk, *pv; /* Temporary pointers for state and coef */ + uint32_t numStages = S->numStages; /* number of stages */ + q31_t *pState; /* State pointer */ + q31_t *pStateCurnt; /* State current pointer */ + + blkCnt = blockSize; + pState = &S->pState[0]; + + /* Sample processing */ + while (blkCnt > 0U) { + /* Read Sample from input buffer */ + /* fN(n) = x(n) */ + fcurr = *pSrc++; + + /* Initialize state read pointer */ + px1 = pState; + /* Initialize state write pointer */ + px2 = pState; + /* Set accumulator to zero */ + acc = 0; + /* Initialize Ladder coeff pointer */ + pv = &S->pvCoeffs[0]; + /* Initialize Reflection coeff pointer */ + pk = &S->pkCoeffs[0]; + + tapCnt = numStages; + + while (tapCnt > 0U) { + gcurr = *px1++; + /* Process sample */ + /* fN-1(n) = fN(n) - kN * gN-1(n-1) */ + fnext = ref_sat_q31( + ((q63_t)fcurr - ((q31_t)(((q63_t)gcurr * (*pk)) >> 31)))); + /* gN(n) = kN * fN-1(n) + gN-1(n-1) */ + gnext = ref_sat_q31( + ((q63_t)gcurr + ((q31_t)(((q63_t)fnext * (*pk++)) >> 31)))); + /* Output samples */ + /* y(n) += gN(n) * vN */ + acc += ((q63_t)gnext * *pv++); + /* write gN-1(n-1) into state for next sample processing */ + *px2++ = gnext; + /* Update f values for next coefficient processing */ + fcurr = fnext; + + tapCnt--; + } + + /* y(n) += g0(n) * v0 */ + acc += (q63_t)fnext * (*pv++); + + *px2++ = fnext; + + /* write out into pDst */ + *pDst++ = (q31_t)(acc >> 31U); + + /* Advance the state pointer by 1 to process the next group of samples + */ + pState = pState + 1U; + blkCnt--; + } + + /* Processing is complete. Now copy last S->numStages samples to start of + the buffer for the preperation of next frame process */ + + /* Points to the start of the state buffer */ + pStateCurnt = &S->pState[0]; + pState = &S->pState[blockSize]; + + tapCnt = numStages; + + /* Copy the remaining q31_t data */ + while (tapCnt > 0U) { + *pStateCurnt++ = *pState++; + + /* Decrement the loop counter */ + tapCnt--; + } +} + +void ref_iir_lattice_q15(const riscv_iir_lattice_instance_q15 *S, q15_t *pSrc, + q15_t *pDst, uint32_t blockSize) +{ + q31_t fcurr, fnext = 0, gcurr = 0, + gnext; /* Temporary variables for lattice stages */ + uint32_t stgCnt; /* Temporary variables for counts */ + q63_t acc; /* Accumlator */ + uint32_t blkCnt, tapCnt; /* Temporary variables for counts */ + q15_t *px1, *px2, *pk, *pv; /* temporary pointers for state and coef */ + uint32_t numStages = S->numStages; /* number of stages */ + q15_t *pState; /* State pointer */ + q15_t *pStateCurnt; /* State current pointer */ + q15_t out; /* Temporary variable for output */ + + blkCnt = blockSize; + pState = &S->pState[0]; + + /* Sample processing */ + while (blkCnt > 0U) { + /* Read Sample from input buffer */ + /* fN(n) = x(n) */ + fcurr = *pSrc++; + + /* Initialize state read pointer */ + px1 = pState; + /* Initialize state write pointer */ + px2 = pState; + /* Set accumulator to zero */ + acc = 0; + /* Initialize Ladder coeff pointer */ + pv = &S->pvCoeffs[0]; + /* Initialize Reflection coeff pointer */ + pk = &S->pkCoeffs[0]; + + tapCnt = numStages; + + while (tapCnt > 0U) { + gcurr = *px1++; + /* Process sample */ + /* fN-1(n) = fN(n) - kN * gN-1(n-1) */ + fnext = fcurr - ((gcurr * (*pk)) >> 15); + fnext = ref_sat_q15(fnext); + /* gN(n) = kN * fN-1(n) + gN-1(n-1) */ + gnext = ((fnext * (*pk++)) >> 15) + gcurr; + gnext = ref_sat_q15(gnext); + /* Output samples */ + /* y(n) += gN(n) * vN */ + acc += (q31_t)((gnext * (*pv++))); + /* write gN(n) into state for next sample processing */ + *px2++ = (q15_t)gnext; + /* Update f values for next coefficient processing */ + fcurr = fnext; + + tapCnt--; + } + + /* y(n) += g0(n) * v0 */ + acc += (q31_t)((fnext * (*pv++))); + + out = ref_sat_q15(acc >> 15); + *px2++ = (q15_t)fnext; + + /* write out into pDst */ + *pDst++ = out; + + /* Advance the state pointer by 1 to process the next group of samples + */ + pState = pState + 1U; + blkCnt--; + } + + /* Processing is complete. Now copy last S->numStages samples to start of + the buffer for the preperation of next frame process */ + /* Points to the start of the state buffer */ + pStateCurnt = &S->pState[0]; + pState = &S->pState[blockSize]; + + stgCnt = numStages; + + /* copy data */ + while (stgCnt > 0U) { + *pStateCurnt++ = *pState++; + + /* Decrement the loop counter */ + stgCnt--; + } +} diff --git a/examples/dsp/FilteringFunction_iirLatticePart/main.c b/examples/dsp/FilteringFunction_iirLatticePart/main.c new file mode 100644 index 00000000..aa7a45b3 --- /dev/null +++ b/examples/dsp/FilteringFunction_iirLatticePart/main.c @@ -0,0 +1,167 @@ +// +// Created by lujun on 19-6-28. +// +// This contains IIR, iir and lms filters +// each one has it's own function. +// All function can be found in main function. +// If you don't want to use it, then comment it. +// +// This part only tests result after 50 dots.If you want to test results' all +// dots, please define WITH_FRONT +// +// If there are too much numbers which makes it hard to read,in VScode you can +// press alt and z can shrimp them to one line +// +// You MUST be careful about overflow. +#include "riscv_math.h" +#include "array.h" +#include +#include "../common.h" + +#include "../HelperFunctions/math_helper.c" +#include "../HelperFunctions/ref_helper.c" + +#include +#define DELTAF32 (0.05f) +#define DELTAQ31 (63) +#define DELTAQ15 (1) +#define DELTAQ7 (1) +#define SNR_THRESHOLD_F32 (80.0f) + +int test_flag_error = 0; + +// #define WITH_FRONT + +//*************************************************************************************** +// iir Lattice Filters +//*************************************************************************************** +static void riscv_iir_f32_lattice_lp(void) +{ + uint32_t i; + /* clang-format off */ + riscv_iir_lattice_instance_f32 S; + /* clang-format on */ + riscv_iir_lattice_init_f32(&S, numStages, IIRCoeffs32LP_K, IIRCoeffs32LP_V, &IIRStateF32[0], TEST_LENGTH_SAMPLES); + BENCH_START(riscv_iir_lattice_f32); + riscv_iir_lattice_f32(&S, testInput_f32_50Hz_200Hz, testOutput_f32, TEST_LENGTH_SAMPLES); + BENCH_END(riscv_iir_lattice_f32); + riscv_iir_lattice_init_f32(&S, numStages, IIRCoeffs32LP_K, IIRCoeffs32LP_V, &IIRStateF32[0], TEST_LENGTH_SAMPLES); + ref_iir_lattice_f32(&S, testInput_f32_50Hz_200Hz, testOutput_f32_ref, TEST_LENGTH_SAMPLES); + // ScaleValue = 0.052219514664161221f * 0.04279801741658381f; +#ifndef WITH_FRONT + float snr = riscv_snr_f32(&testOutput_f32_ref[50], &testOutput_f32[50], 269); + + if (snr < SNR_THRESHOLD_F32) { + BENCH_ERROR(riscv_iir_lattice_f32); + printf("f32 iir_lattice failed with snr:%f\n", snr); + test_flag_error = 1; + } + BENCH_STATUS(riscv_iir_lattice_f32); +#else + float snr = + riscv_snr_f32(&testOutput_f32_ref[0], &testOutput_f32[0], TEST_LENGTH_SAMPLES); + + if (snr < SNR_THRESHOLD_F32) { + BENCH_ERROR(riscv_iir_lattice_f32); + printf("f32 iir_lattice failed with snr:%f\n", snr); + test_flag_error = 1; + } + BENCH_STATUS(riscv_iir_lattice_f32); +#endif +} +static void riscv_iir_q31_lattice_lp(void) +{ + uint32_t i; + /* clang-format off */ + riscv_iir_lattice_instance_q31 S; + /* clang-format on */ + riscv_float_to_q31(testInput_f32_50Hz_200Hz, testInput_q31_50Hz_200Hz, TEST_LENGTH_SAMPLES); + riscv_float_to_q31(IIRCoeffs32LP_K, IIRCoeffs32LP_K_q31, numStages); + riscv_float_to_q31(IIRCoeffs32LP_V, IIRCoeffs32LP_V_q31, numStages+1); + riscv_iir_lattice_init_q31(&S, numStages, IIRCoeffs32LP_K_q31, IIRCoeffs32LP_V_q31, &IIRStateQ31[0], TEST_LENGTH_SAMPLES); + BENCH_START(riscv_iir_lattice_q31); + riscv_iir_lattice_q31(&S, testInput_q31_50Hz_200Hz, testOutput_q31, TEST_LENGTH_SAMPLES); + BENCH_END(riscv_iir_lattice_q31); + riscv_iir_lattice_init_q31(&S, numStages, IIRCoeffs32LP_K_q31, IIRCoeffs32LP_V_q31, &IIRStateQ31[0], TEST_LENGTH_SAMPLES); + ref_iir_lattice_q31(&S, testInput_q31_50Hz_200Hz, testOutput_q31_ref, TEST_LENGTH_SAMPLES); + // ScaleValue = 0.052219514664161221f * 0.04279801741658381f; + riscv_q31_to_float(testOutput_q31, testOutput_f32, TEST_LENGTH_SAMPLES); + riscv_q31_to_float(testOutput_q31_ref, testOutput_f32_ref, TEST_LENGTH_SAMPLES); +#ifndef WITH_FRONT + float snr = + riscv_snr_f32(&testOutput_f32_ref[200], &testOutput_f32[200], 119); + + if (snr < SNR_THRESHOLD_F32) { + BENCH_ERROR(riscv_iir_lattice_q31); + printf("q31 iir_lattice failed with snr:%f\n", snr); + test_flag_error = 1; + } + BENCH_STATUS(riscv_iir_lattice_q31); +#else + float snr = riscv_snr_f32(&testOutput_f32_ref[0], &testOutput_f32[0], + TEST_LENGTH_SAMPLES); + + if (snr < SNR_THRESHOLD_F32) { + BENCH_ERROR(riscv_iir_lattice_q31); + printf("q31 iir_lattice failed with snr:%f\n", snr); + test_flag_error = 1; + } + BENCH_STATUS(riscv_iir_lattice_q31); +#endif +} +static void riscv_iir_q15_lattice_lp(void) +{ + uint32_t i; + /* clang-format off */ + riscv_iir_lattice_instance_q15 S; + /* clang-format on */ + riscv_float_to_q15(testInput_f32_50Hz_200Hz, testInput_q15_50Hz_200Hz, TEST_LENGTH_SAMPLES); + riscv_float_to_q15(IIRCoeffs32LP_K, IIRCoeffs32LP_K_q15, numStages); + riscv_float_to_q15(IIRCoeffs32LP_V, IIRCoeffs32LP_V_q15, numStages+1); + riscv_iir_lattice_init_q15(&S, numStages, IIRCoeffs32LP_K_q15, IIRCoeffs32LP_V_q15, &IIRStateQ15[0], TEST_LENGTH_SAMPLES); + BENCH_START(riscv_iir_lattice_q15); + riscv_iir_lattice_q15(&S, testInput_q15_50Hz_200Hz, testOutput_q15, TEST_LENGTH_SAMPLES); + BENCH_END(riscv_iir_lattice_q15); + riscv_iir_lattice_init_q15(&S, numStages, IIRCoeffs32LP_K_q15, IIRCoeffs32LP_V_q15, &IIRStateQ15[0], TEST_LENGTH_SAMPLES); + ref_iir_lattice_q15(&S, testInput_q15_50Hz_200Hz, testOutput_q15_ref, TEST_LENGTH_SAMPLES); + // ScaleValue = 0.052219514664161221f * 0.04279801741658381f; + riscv_q15_to_float(testOutput_q15, testOutput_f32, TEST_LENGTH_SAMPLES); + riscv_q15_to_float(testOutput_q15_ref, testOutput_f32_ref, TEST_LENGTH_SAMPLES); +#ifndef WITH_FRONT + float snr = + riscv_snr_f32(&testOutput_f32_ref[200], &testOutput_f32[200], 119); + + if (snr < SNR_THRESHOLD_F32) { + BENCH_ERROR(riscv_iir_lattice_q15); + printf("q15 iir_lattice failed with snr:%f\n", snr); + test_flag_error = 1; + } + BENCH_STATUS(riscv_iir_lattice_q15); +#else + float snr = riscv_snr_f32(&testOutput_f32_ref[0], &testOutput_f32[0], + TEST_LENGTH_SAMPLES); + + if (snr < SNR_THRESHOLD_F32) { + BENCH_ERROR(riscv_iir_lattice_q15); + printf("q15 iir_lattice failed with snr:%f\n", snr); + test_flag_error = 1; + } + BENCH_STATUS(riscv_iir_lattice_q15); +#endif +} + +int main() +{ + BENCH_INIT; + riscv_iir_f32_lattice_lp(); + riscv_iir_q31_lattice_lp(); + riscv_iir_q15_lattice_lp(); + BENCH_FINISH; + if (test_flag_error) { + printf("test error apprears, please recheck.\n"); + return 1; + } else { + printf("all test are passed. Well done!\n"); + } + return 0; +} diff --git a/examples/dsp/FilteringFunction_iirdf1/CMakeLists.txt b/examples/dsp/FilteringFunction_iirdf1/CMakeLists.txt new file mode 100644 index 00000000..941f6763 --- /dev/null +++ b/examples/dsp/FilteringFunction_iirdf1/CMakeLists.txt @@ -0,0 +1,5 @@ +set(TARGET_REQUIRED_PRIVATE_INCLUDE ${CMAKE_CURRENT_SOURCE_DIR} ${CMAKE_CURRENT_SOURCE_DIR}/..) +set(TARGET_REQUIRED_SRCS biquad.c) +set(TARGET_REQUIRED_LIBS nmsis) +set(mains main.c) +generate_bin() \ No newline at end of file diff --git a/examples/dsp/FilteringFunction_iirdf1/array.h b/examples/dsp/FilteringFunction_iirdf1/array.h new file mode 100644 index 00000000..a53a2448 --- /dev/null +++ b/examples/dsp/FilteringFunction_iirdf1/array.h @@ -0,0 +1,27 @@ +// Array for FilteringFunctions iirdf1 +#define TEST_LENGTH_SAMPLES 320 /* 采样点数 */ +#define numStages 2 /* 2阶IIR滤波的个数 */ +// float32_t + float32_t testOutput_f32[TEST_LENGTH_SAMPLES],testOutput_f32_ref[TEST_LENGTH_SAMPLES]; + float32_t IIRStateF32[4*numStages]={0}; + float32_t IIRCoeffs32LP[5*numStages] = {1.0f, 2.0f, 1.0f, 1.11302985416334787593939381622476503253f, - 0.574061915083954765748330828500911593437f,1.0f, 2.0f, 1.0f, 0.855397932775170177777113167394418269396f, - 0.209715357756554754420363906319835223258f}; + float32_t testInput_f32_50Hz_200Hz[TEST_LENGTH_SAMPLES] = {0, 1.26007351067010, 1.17557050458495, 0.221231742082474, -1.11022302462516e-16, 1.00000000000000, 1.90211303259031, 1.39680224666742, 4.44089209850063e-16, -0.642039521920206, -3.67394039744206e-16, 0.642039521920206, -1.22124532708767e-15, -1.39680224666742, -1.90211303259031, -1.00000000000000, -3.33066907387547e-16, -0.221231742082476, -1.17557050458495, -1.26007351067010, -1.22464679914735e-15, 1.26007351067010, 1.17557050458495, 0.221231742082475, 8.88178419700125e-16, 1.00000000000000, 1.90211303259031, 1.39680224666742, 1.33226762955019e-15, -0.642039521920206, -1.10218211923262e-15, 0.642039521920206, 1.55431223447522e-15, -1.39680224666743, -1.90211303259031, -0.999999999999995, -7.77156117237610e-16, -0.221231742082473, -1.17557050458495, -1.26007351067010, -2.44929359829471e-15, 1.26007351067010, 1.17557050458494, 0.221231742082476, -7.77156117237610e-16, 0.999999999999998, 1.90211303259031, 1.39680224666742, -4.88498130835069e-15, -0.642039521920206, 3.49210031947972e-15, 0.642039521920206, 2.55351295663786e-15, -1.39680224666742, -1.90211303259031, -0.999999999999996, -9.99200722162641e-16, -0.221231742082477, -1.17557050458494, -1.26007351067011, -3.67394039744206e-15, 1.26007351067010, 1.17557050458495, 0.221231742082472, -1.22124532708767e-15, 1.00000000000000, 1.90211303259031, 1.39680224666742, -1.09912079437891e-14, -0.642039521920206, 8.08638275819206e-15, 0.642039521920205, 3.55271367880050e-15, -1.39680224666741, -1.90211303259031, -0.999999999999997, -1.44328993201270e-15, -0.221231742082476, -1.17557050458494, -1.26007351067010, -4.89858719658941e-15, 1.26007351067010, 1.17557050458494, 0.221231742082472, 3.88578058618805e-15, 1.00000000000000, 1.90211303259031, 1.39680224666743, 4.44089209850063e-15, -0.642039521920207, -3.30654635769785e-15, 0.642039521920206, 4.55191440096314e-15, -1.39680224666742, -1.90211303259031, -0.999999999999998, 3.66373598126302e-15, -0.221231742082476, -1.17557050458495, -1.26007351067010, 1.16403343982657e-14, 1.26007351067010, 1.17557050458496, 0.221231742082482, -1.99840144432528e-15, 1.00000000000000, 1.90211303259031, 1.39680224666743, 5.44009282066327e-15, -0.642039521920206, 6.61680659921524e-15, 0.642039521920207, 5.55111512312578e-15, -1.39680224666742, -1.90211303259031, -0.999999999999984, -2.10942374678780e-15, -0.221231742082475, -1.17557050458493, -1.26007351067011, -7.34788079488412e-15, 1.26007351067010, 1.17557050458494, 0.221231742082483, -2.33146835171283e-15, 1.00000000000000, 1.90211303259031, 1.39680224666741, 6.32827124036339e-15, -0.642039521920206, 5.88201851972683e-15, 0.642039521920207, -2.22044604925031e-14, -1.39680224666742, -1.90211303259031, -0.999999999999985, 8.43769498715119e-15, -0.221231742082475, -1.17557050458495, -1.26007351067009, 2.69546091939735e-14, 1.26007351067009, 1.17557050458496, 0.221231742082484, -2.77555756156289e-15, 1, 1.90211303259030, 1.39680224666743, 7.32747196252603e-15, -0.642039521920206, 5.14723044023841e-15, 0.642039521920205, 7.54951656745106e-15, -1.39680224666742, -1.90211303259031, -0.999999999999986, -2.99760216648792e-15, -0.221231742082474, -1.17557050458495, -1.26007351067009, -9.79717439317883e-15, 1.26007351067010, 1.17557050458494, 0.221231742082465, 7.88258347483861e-15, 0.999999999999999, 1.90211303259031, 1.39680224666741, -2.04281036531029e-14, -0.642039521920204, 4.41244236075000e-15, 0.642039521920207, 8.43769498715119e-15, -1.39680224666742, -1.90211303259031, -1.00000000000002, -3.33066907387547e-15, -0.221231742082473, -1.17557050458493, -1.26007351067011, -1.10218211923262e-14, 1.26007351067010, 1.17557050458494, 0.221231742082485, -3.44169137633799e-15, 0.999999999999998, 1.90211303259031, 1.39680224666741, 9.32587340685132e-15, -0.642039521920206, 3.67765428126159e-15, 0.642039521920207, -1.93178806284777e-14, -1.39680224666742, -1.90211303259031, -0.999999999999988, 7.32747196252603e-15, -0.221231742082492, -1.17557050458495, -1.26007351067009, 2.32806687965315e-14, 1.26007351067012, 1.17557050458494, 0.221231742082467, -1.47659662275146e-14, 0.999999999999969, 1.90211303259030, 1.39680224666744, 1.02140518265514e-14, -0.642039521920206, 2.94286620177318e-15, 0.642039521920207, -1.83186799063151e-14, -1.39680224666739, -1.90211303259031, -1.00000000000002, -4.10782519111308e-15, -0.221231742082472, -1.17557050458495, -1.26007351067010, 2.20560219973841e-14, 1.26007351067011, 1.17557050458493, 0.221231742082486, -4.21884749357560e-15, 0.999999999999996, 1.90211303259031, 1.39680224666741, -1.75415237890775e-14, -0.642039521920204, 2.35243601950878e-14, 0.642039521920209, 1.15463194561016e-14, -1.39680224666742, -1.90211303259031, -0.999999999999990, -1.54321000422897e-14, -0.221231742082452, -1.17557050458493, -1.26007351067011, -1.46957615897682e-14, 1.26007351067010, 1.17557050458495, 0.221231742082468, 6.32827124036339e-15, 1.00000000000002, 1.90211303259030, 1.39680224666744, 1.23234755733392e-14, -0.642039521920207, 1.47329004279635e-15, 0.642039521920207, -1.62092561595273e-14, -1.39680224666744, -1.90211303259030, -1.00000000000002, -4.88498130835069e-15, -0.221231742082471, -1.17557050458495, -1.26007351067010, 1.96067283990894e-14, 1.26007351067011, 1.17557050458493, 0.221231742082450, 1.69864122767649e-14, 0.999999999999994, 1.90211303259031, 1.39680224666741, -1.54321000422897e-14, -0.642039521920205, 2.20547840361110e-14, 0.642039521920209, -4.39648317751562e-14, -1.39680224666747, -1.90211303259031, -0.999999999999992, 5.77315972805081e-15, -0.221231742082489, -1.17557050458496, -1.26007351067008, 5.39092183879471e-14, 1.26007351067013, 1.17557050458498, 0.221231742082507, -1.63202784619898e-14, 0.999999999999965, 1.90211303259030, 1.39680224666744, 1.43218770176645e-14, -0.642039521920207, 3.71388381953015e-18, 0.642039521920203, 4.31876756579186e-14, -1.39680224666739, -1.90211303259031, -1.00000000000002, -5.55111512312578e-15, -0.221231742082469, -1.17557050458495, -1.26007351067010, 1.71574348007947e-14, 1.26007351067008, 1.17557050458496, 0.221231742082489, -5.77315972805081e-15, 0.999999999999992, 1.90211303259031, 1.39680224666741, -1.34336985979644e-14, -0.642039521920205, 2.05852078771341e-14, 0.642039521920205, 1.54321000422897e-14, -1.39680224666741, -1.90211303259031, -0.999999999999994, 4.99600361081320e-15, -0.221231742082488, -1.17557050458496, -1.26007351067008}; + float32_t testInput_f32_50Hz_200Hz_temp[TEST_LENGTH_SAMPLES] = {0, 1.26007351067010, 1.17557050458495, 0.221231742082474, -1.11022302462516e-16, 1.00000000000000, 1.90211303259031, 1.39680224666742, 4.44089209850063e-16, -0.642039521920206, -3.67394039744206e-16, 0.642039521920206, -1.22124532708767e-15, -1.39680224666742, -1.90211303259031, -1.00000000000000, -3.33066907387547e-16, -0.221231742082476, -1.17557050458495, -1.26007351067010, -1.22464679914735e-15, 1.26007351067010, 1.17557050458495, 0.221231742082475, 8.88178419700125e-16, 1.00000000000000, 1.90211303259031, 1.39680224666742, 1.33226762955019e-15, -0.642039521920206, -1.10218211923262e-15, 0.642039521920206, 1.55431223447522e-15, -1.39680224666743, -1.90211303259031, -0.999999999999995, -7.77156117237610e-16, -0.221231742082473, -1.17557050458495, -1.26007351067010, -2.44929359829471e-15, 1.26007351067010, 1.17557050458494, 0.221231742082476, -7.77156117237610e-16, 0.999999999999998, 1.90211303259031, 1.39680224666742, -4.88498130835069e-15, -0.642039521920206, 3.49210031947972e-15, 0.642039521920206, 2.55351295663786e-15, -1.39680224666742, -1.90211303259031, -0.999999999999996, -9.99200722162641e-16, -0.221231742082477, -1.17557050458494, -1.26007351067011, -3.67394039744206e-15, 1.26007351067010, 1.17557050458495, 0.221231742082472, -1.22124532708767e-15, 1.00000000000000, 1.90211303259031, 1.39680224666742, -1.09912079437891e-14, -0.642039521920206, 8.08638275819206e-15, 0.642039521920205, 3.55271367880050e-15, -1.39680224666741, -1.90211303259031, -0.999999999999997, -1.44328993201270e-15, -0.221231742082476, -1.17557050458494, -1.26007351067010, -4.89858719658941e-15, 1.26007351067010, 1.17557050458494, 0.221231742082472, 3.88578058618805e-15, 1.00000000000000, 1.90211303259031, 1.39680224666743, 4.44089209850063e-15, -0.642039521920207, -3.30654635769785e-15, 0.642039521920206, 4.55191440096314e-15, -1.39680224666742, -1.90211303259031, -0.999999999999998, 3.66373598126302e-15, -0.221231742082476, -1.17557050458495, -1.26007351067010, 1.16403343982657e-14, 1.26007351067010, 1.17557050458496, 0.221231742082482, -1.99840144432528e-15, 1.00000000000000, 1.90211303259031, 1.39680224666743, 5.44009282066327e-15, -0.642039521920206, 6.61680659921524e-15, 0.642039521920207, 5.55111512312578e-15, -1.39680224666742, -1.90211303259031, -0.999999999999984, -2.10942374678780e-15, -0.221231742082475, -1.17557050458493, -1.26007351067011, -7.34788079488412e-15, 1.26007351067010, 1.17557050458494, 0.221231742082483, -2.33146835171283e-15, 1.00000000000000, 1.90211303259031, 1.39680224666741, 6.32827124036339e-15, -0.642039521920206, 5.88201851972683e-15, 0.642039521920207, -2.22044604925031e-14, -1.39680224666742, -1.90211303259031, -0.999999999999985, 8.43769498715119e-15, -0.221231742082475, -1.17557050458495, -1.26007351067009, 2.69546091939735e-14, 1.26007351067009, 1.17557050458496, 0.221231742082484, -2.77555756156289e-15, 1, 1.90211303259030, 1.39680224666743, 7.32747196252603e-15, -0.642039521920206, 5.14723044023841e-15, 0.642039521920205, 7.54951656745106e-15, -1.39680224666742, -1.90211303259031, -0.999999999999986, -2.99760216648792e-15, -0.221231742082474, -1.17557050458495, -1.26007351067009, -9.79717439317883e-15, 1.26007351067010, 1.17557050458494, 0.221231742082465, 7.88258347483861e-15, 0.999999999999999, 1.90211303259031, 1.39680224666741, -2.04281036531029e-14, -0.642039521920204, 4.41244236075000e-15, 0.642039521920207, 8.43769498715119e-15, -1.39680224666742, -1.90211303259031, -1.00000000000002, -3.33066907387547e-15, -0.221231742082473, -1.17557050458493, -1.26007351067011, -1.10218211923262e-14, 1.26007351067010, 1.17557050458494, 0.221231742082485, -3.44169137633799e-15, 0.999999999999998, 1.90211303259031, 1.39680224666741, 9.32587340685132e-15, -0.642039521920206, 3.67765428126159e-15, 0.642039521920207, -1.93178806284777e-14, -1.39680224666742, -1.90211303259031, -0.999999999999988, 7.32747196252603e-15, -0.221231742082492, -1.17557050458495, -1.26007351067009, 2.32806687965315e-14, 1.26007351067012, 1.17557050458494, 0.221231742082467, -1.47659662275146e-14, 0.999999999999969, 1.90211303259030, 1.39680224666744, 1.02140518265514e-14, -0.642039521920206, 2.94286620177318e-15, 0.642039521920207, -1.83186799063151e-14, -1.39680224666739, -1.90211303259031, -1.00000000000002, -4.10782519111308e-15, -0.221231742082472, -1.17557050458495, -1.26007351067010, 2.20560219973841e-14, 1.26007351067011, 1.17557050458493, 0.221231742082486, -4.21884749357560e-15, 0.999999999999996, 1.90211303259031, 1.39680224666741, -1.75415237890775e-14, -0.642039521920204, 2.35243601950878e-14, 0.642039521920209, 1.15463194561016e-14, -1.39680224666742, -1.90211303259031, -0.999999999999990, -1.54321000422897e-14, -0.221231742082452, -1.17557050458493, -1.26007351067011, -1.46957615897682e-14, 1.26007351067010, 1.17557050458495, 0.221231742082468, 6.32827124036339e-15, 1.00000000000002, 1.90211303259030, 1.39680224666744, 1.23234755733392e-14, -0.642039521920207, 1.47329004279635e-15, 0.642039521920207, -1.62092561595273e-14, -1.39680224666744, -1.90211303259030, -1.00000000000002, -4.88498130835069e-15, -0.221231742082471, -1.17557050458495, -1.26007351067010, 1.96067283990894e-14, 1.26007351067011, 1.17557050458493, 0.221231742082450, 1.69864122767649e-14, 0.999999999999994, 1.90211303259031, 1.39680224666741, -1.54321000422897e-14, -0.642039521920205, 2.20547840361110e-14, 0.642039521920209, -4.39648317751562e-14, -1.39680224666747, -1.90211303259031, -0.999999999999992, 5.77315972805081e-15, -0.221231742082489, -1.17557050458496, -1.26007351067008, 5.39092183879471e-14, 1.26007351067013, 1.17557050458498, 0.221231742082507, -1.63202784619898e-14, 0.999999999999965, 1.90211303259030, 1.39680224666744, 1.43218770176645e-14, -0.642039521920207, 3.71388381953015e-18, 0.642039521920203, 4.31876756579186e-14, -1.39680224666739, -1.90211303259031, -1.00000000000002, -5.55111512312578e-15, -0.221231742082469, -1.17557050458495, -1.26007351067010, 1.71574348007947e-14, 1.26007351067008, 1.17557050458496, 0.221231742082489, -5.77315972805081e-15, 0.999999999999992, 1.90211303259031, 1.39680224666741, -1.34336985979644e-14, -0.642039521920205, 2.05852078771341e-14, 0.642039521920205, 1.54321000422897e-14, -1.39680224666741, -1.90211303259031, -0.999999999999994, 4.99600361081320e-15, -0.221231742082488, -1.17557050458496, -1.26007351067008}; + +//q31_t + q31_t IIRStateq31[4*numStages]; + q31_t testInput_q31_50Hz_200Hz[TEST_LENGTH_SAMPLES] = {0}, testOutput_q31[TEST_LENGTH_SAMPLES] = {0},testOutput_q31_ref[TEST_LENGTH_SAMPLES] = {0}; + q31_t IIRCoeffsQ31LP[5*numStages] = {0}; + q63_t IIRState32x64[4*numStages] = {0}; + +//q15_t + q15_t IIRStateq15[4*numStages]; + q15_t testInput_q15_50Hz_200Hz[TEST_LENGTH_SAMPLES] = {0}, testOutput_q15[TEST_LENGTH_SAMPLES] = {0}; + // coeffs must follow {b10, 0, b11, b12, a11, a12, b20, 0, b21, b22, a21, a22, ...} + q15_t IIRCoeffsQ15LP[6*numStages] = {32767,0,32767,32767,32767,-18810,32767,0,32767,32767,28029,-6871}; + q15_t testOutput_q15_ref[TEST_LENGTH_SAMPLES] = {0,325,2167,8070,21732,32767,32767,32767,32767,32767,32767,32767,32767,32767,30067,4776,-32768,-32768,-32768,-32768,-32768,-32768,-32768,-28565,26648,32767,32767,32767,32767,32767,32767,32767,9979,-32768,-32768,-32768,-32768,-32768,-32768,11146,32767,32767,32767,32767,32767,32767,-16258,-32768,-32768,-32768,-32768,-32768,-32768,32767,32767,32767,32767,32767,32767,21057,-32768,-32768,-32768,-32768,-32768,-32768,32767,32767,32767,32767,32767,32767,-22798,-32768,-32768,-32768,-32768,-32768,-32768,11146,32767,32767,32767,32767,32767,32767,-16258,-32768,-32768,-32768,-32768,-32768,-32768,32767,32767,32767,32767,32767,32767,21057,-32768,-32768,-32768,-32768,-32768,-32768,32767,32767,32767,32767,32767,32767,-22798,-32768,-32768,-32768,-32768,-32768,-32768,11146,32767,32767,32767,32767,32767,32767,-16258,-32768,-32768,-32768,-32768,-32768,-32768,32767,32767,32767,32767,32767,32767,21057,-32768,-32768,-32768,-32768,-32768,-32768,32767,32767,32767,32767,32767,32767,-22798,-32768,-32768,-32768,-32768,-32768,-32768,11146,32767,32767,32767,32767,32767,32767,-16258,-32768,-32768,-32768,-32768,-32768,-32768,32767,32767,32767,32767,32767,32767,21057,-32768,-32768,-32768,-32768,-32768,-32768,32767,32767,32767,32767,32767,32767,-22798,-32768,-32768,-32768,-32768,-32768,-32768,11146,32767,32767,32767,32767,32767,32767,-16258,-32768,-32768,-32768,-32768,-32768,-32768,32767,32767,32767,32767,32767,32767,21057,-32768,-32768,-32768,-32768,-32768,-32768,32767,32767,32767,32767,32767,32767,-22798,-32768,-32768,-32768,-32768,-32768,-32768,11146,32767,32767,32767,32767,32767,32767,-16258,-32768,-32768,-32768,-32768,-32768,-32768,32767,32767,32767,32767,32767,32767,21057,-32768,-32768,-32768,-32768,-32768,-32768,32767,32767,32767,32767,32767,32767,-22798,-32768,-32768,-32768,-32768,-32768,-32768,11146,32767,32767,32767,32767,32767,32767,-16258,-32768,-32768,-32768,-32768,-32768,-32768,32767,32767,32767,32767,32767,32767,21057,-32768,-32768,-32768,-32768,-32768,-32768,32767,32767,32767,32767,32767,32767,-22798,-32768,-32768,-32768,-32768,-32768,-32768,11146}; +#if defined RISCV_MATH_DSP + q15_t testOutput_fast_ref[320] = {0,161,1075,4003,10777,23629,32767,32767,32767,32767,32767,32767,32767,32767,32767,26037,3818,-32768,-32768,-32768,-32768,-32768,-32768,-32768,-11801,32767,32767,32767,32767,32767,32767,32767,26469,-30438,-32768,-32768,-32768,-32768,-32768,-32768,-32768,5688,32767,32767,32767,32767,32767,32767,-24690,-32768,-32768,-32768,-32768,-32768,-32768,30285,32767,32767,32767,32767,32767,32767,-32768,-32768,-32768,-32768,-32768,-32768,4432,32767,32767,32767,32767,32767,32767,-32768,-32768,-32768,-32768,-32768,-32768,-32768,32767,32767,32767,32767,32767,32767,-24690,-32768,-32768,-32768,-32768,-32768,-32768,30285,32767,32767,32767,32767,32767,32767,-32768,-32768,-32768,-32768,-32768,-32768,4432,32767,32767,32767,32767,32767,32767,-32768,-32768,-32768,-32768,-32768,-32768,-32768,32767,32767,32767,32767,32767,32767,-24690,-32768,-32768,-32768,-32768,-32768,-32768,30285,32767,32767,32767,32767,32767,32767,-32768,-32768,-32768,-32768,-32768,-32768,4432,32767,32767,32767,32767,32767,32767,-32768,-32768,-32768,-32768,-32768,-32768,-32768,32767,32767,32767,32767,32767,32767,-24690,-32768,-32768,-32768,-32768,-32768,-32768,30285,32767,32767,32767,32767,32767,32767,-32768,-32768,-32768,-32768,-32768,-32768,4432,32767,32767,32767,32767,32767,32767,-32768,-32768,-32768,-32768,-32768,-32768,-32768,32767,32767,32767,32767,32767,32767,-24690,-32768,-32768,-32768,-32768,-32768,-32768,30285,32767,32767,32767,32767,32767,32767,-32768,-32768,-32768,-32768,-32768,-32768,4432,32767,32767,32767,32767,32767,32767,-32768,-32768,-32768,-32768,-32768,-32768,-32768,32767,32767,32767,32767,32767,32767,-24690,-32768,-32768,-32768,-32768,-32768,-32768,30285,32767,32767,32767,32767,32767,32767,-32768,-32768,-32768,-32768,-32768,-32768,4432,32767,32767,32767,32767,32767,32767,-32768,-32768,-32768,-32768,-32768,-32768,-32768,32767,32767,32767,32767,32767,32767,-24690,-32768,-32768,-32768,-32768,-32768,-32768,30285,32767,32767,32767,32767,32767,32767,-32768,-32768,-32768,-32768,-32768,-32768,4432,32767,32767,32767,32767,32767,32767,-32768,-32768,-32768,-32768,-32768}; +#else + q15_t testOutput_fast_ref[320] = {0,161,1075,4003,10777,23629,32767,32767,32767,32767,32767,32767,32767,32767,32767,26037,3818,-32768,-32768,-32768,-32768,-32768,-32768,-32768,-11801,32767,-32768,16631,-32768,18068,32767,32767,26469,-30438,32767,-32768,28257,-32768,32767,-28499,-32768,3898,-32768,32767,-5278,-32768,32767,32767,-24690,32767,-32768,5450,32767,-32768,-32768,30285,-32768,32767,-6886,32767,-32768,-32768,-32768,32767,-32768,24581,-32768,-32768,4432,-32768,32767,-5458,-32768,32767,32767,-32768,32767,-32768,15287,-32768,32767,32767,-32768,32767,-5278,-32768,32767,32767,-24690,32767,-32768,5450,32767,-32768,-32768,30285,-32768,32767,-6886,32767,-32768,-32768,-32768,32767,-32768,24581,-32768,-32768,4432,-32768,32767,-5458,-32768,32767,32767,-32768,32767,-32768,15287,-32768,32767,32767,-32768,32767,-5278,-32768,32767,32767,-24690,32767,-32768,5450,32767,-32768,-32768,30285,-32768,32767,-6886,32767,-32768,-32768,-32768,32767,-32768,24581,-32768,-32768,4432,-32768,32767,-5458,-32768,32767,32767,-32768,32767,-32768,15287,-32768,32767,32767,-32768,32767,-5278,-32768,32767,32767,-24690,32767,-32768,5450,32767,-32768,-32768,30285,-32768,32767,-6886,32767,-32768,-32768,-32768,32767,-32768,24581,-32768,-32768,4432,-32768,32767,-5458,-32768,32767,32767,-32768,32767,-32768,15287,-32768,32767,32767,-32768,32767,-5278,-32768,32767,32767,-24690,32767,-32768,5450,32767,-32768,-32768,30285,-32768,32767,-6886,32767,-32768,-32768,-32768,32767,-32768,24581,-32768,-32768,4432,-32768,32767,-5458,-32768,32767,32767,-32768,32767,-32768,15287,-32768,32767,32767,-32768,32767,-5278,-32768,32767,32767,-24690,32767,-32768,5450,32767,-32768,-32768,30285,-32768,32767,-6886,32767,-32768,-32768,-32768,32767,-32768,24581,-32768,-32768,4432,-32768,32767,-5458,-32768,32767,32767,-32768,32767,-32768,15287,-32768,32767,32767,-32768,32767,-5278,-32768,32767,32767,-24690,32767,-32768,5450,32767,-32768,-32768,30285,-32768,32767,-6886,32767,-32768,-32768,-32768,32767,-32768,24581,-32768,-32768,4432,-32768,32767,-5458,-32768,32767,32767,-32768,32767,-32768,15287,-32768}; +#endif diff --git a/examples/dsp/FilteringFunction_iirdf1/biquad.c b/examples/dsp/FilteringFunction_iirdf1/biquad.c new file mode 100644 index 00000000..88e23e8e --- /dev/null +++ b/examples/dsp/FilteringFunction_iirdf1/biquad.c @@ -0,0 +1,699 @@ +#include "ref.h" + +void ref_biquad_cascade_df2T_f32(const riscv_biquad_cascade_df2T_instance_f32 *S, + float32_t *pSrc, float32_t *pDst, + uint32_t blockSize) +{ + float32_t *pIn = pSrc; /* source pointer */ + float32_t *pOut = pDst; /* destination pointer */ + float32_t *pState = S->pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* coefficient pointer */ + float32_t acc; /* accumulator */ + float32_t b0, b1, b2, a1, a2; /* Filter coefficients */ + float32_t Xn; /* temporary input */ + float32_t d1, d2; /* state variables */ + uint32_t sample, stage = S->numStages; /* loop counters */ + + do { + /* Reading the coefficients */ + b0 = *pCoeffs++; + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + /*Reading the state values */ + d1 = pState[0]; + d2 = pState[1]; + + sample = blockSize; + + while (sample > 0U) { + /* Read the input */ + Xn = *pIn++; + + /* y[n] = b0 * x[n] + d1 */ + acc = (b0 * Xn) + d1; + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = acc; + + /* Every time after the output is computed state should be updated. + */ + /* d1 = b1 * x[n] + a1 * y[n] + d2 */ + d1 = (b1 * Xn + a1 * acc) + d2; + + /* d2 = b2 * x[n] + a2 * y[n] */ + d2 = (b2 * Xn) + (a2 * acc); + + /* decrement the loop counter */ + sample--; + } + + /* Store the updated state variables back into the state array */ + *pState++ = d1; + *pState++ = d2; + + /* The current stage input is given as the output to the next stage */ + pIn = pDst; + + /*Reset the output working pointer */ + pOut = pDst; + + /* decrement the loop counter */ + stage--; + + } while (stage > 0U); +} + +void ref_biquad_cascade_stereo_df2T_f32( + const riscv_biquad_cascade_stereo_df2T_instance_f32 *S, float32_t *pSrc, + float32_t *pDst, uint32_t blockSize) +{ + float32_t *pIn = pSrc; /* source pointer */ + float32_t *pOut = pDst; /* destination pointer */ + float32_t *pState = S->pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* coefficient pointer */ + float32_t acc1a, acc1b; /* accumulator */ + float32_t b0, b1, b2, a1, a2; /* Filter coefficients */ + float32_t Xn1a, Xn1b; /* temporary input */ + float32_t d1a, d2a, d1b, d2b; /* state variables */ + uint32_t sample, stage = S->numStages; /* loop counters */ + + do { + /* Reading the coefficients */ + b0 = *pCoeffs++; + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + /*Reading the state values */ + d1a = pState[0]; + d2a = pState[1]; + d1b = pState[2]; + d2b = pState[3]; + + sample = blockSize; + + while (sample > 0U) { + /* Read the input */ + Xn1a = *pIn++; // Channel a + Xn1b = *pIn++; // Channel b + + /* y[n] = b0 * x[n] + d1 */ + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = acc1a; + *pOut++ = acc1b; + + /* Every time after the output is computed state should be updated. + */ + /* d1 = b1 * x[n] + a1 * y[n] + d2 */ + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + /* d2 = b2 * x[n] + a2 * y[n] */ + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + + /* decrement the loop counter */ + sample--; + } + + /* Store the updated state variables back into the state array */ + *pState++ = d1a; + *pState++ = d2a; + *pState++ = d1b; + *pState++ = d2b; + + /* The current stage input is given as the output to the next stage */ + pIn = pDst; + + /*Reset the output working pointer */ + pOut = pDst; + + /* decrement the loop counter */ + stage--; + + } while (stage > 0U); +} + +void ref_biquad_cascade_df2T_f64(const riscv_biquad_cascade_df2T_instance_f64 *S, + float64_t *pSrc, float64_t *pDst, + uint32_t blockSize) +{ + float64_t *pIn = pSrc; /* source pointer */ + float64_t *pOut = pDst; /* destination pointer */ + float64_t *pState = S->pState; /* State pointer */ + float64_t *pCoeffs = S->pCoeffs; /* coefficient pointer */ + float64_t acc; /* accumulator */ + float64_t b0, b1, b2, a1, a2; /* Filter coefficients */ + float64_t Xn; /* temporary input */ + float64_t d1, d2; /* state variables */ + uint32_t sample, stage = S->numStages; /* loop counters */ + + do { + /* Reading the coefficients */ + b0 = *pCoeffs++; + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + /*Reading the state values */ + d1 = pState[0]; + d2 = pState[1]; + + sample = blockSize; + + while (sample > 0U) { + /* Read the input */ + Xn = *pIn++; + + /* y[n] = b0 * x[n] + d1 */ + acc = (b0 * Xn) + d1; + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = acc; + + /* Every time after the output is computed state should be updated. + */ + /* d1 = b1 * x[n] + a1 * y[n] + d2 */ + d1 = (b1 * Xn + a1 * acc) + d2; + + /* d2 = b2 * x[n] + a2 * y[n] */ + d2 = (b2 * Xn) + (a2 * acc); + + /* decrement the loop counter */ + sample--; + } + + /* Store the updated state variables back into the state array */ + *pState++ = d1; + *pState++ = d2; + + /* The current stage input is given as the output to the next stage */ + pIn = pDst; + + /*Reset the output working pointer */ + pOut = pDst; + + /* decrement the loop counter */ + stage--; + + } while (stage > 0U); +} + +void ref_biquad_cascade_df1_f32(const riscv_biquad_casd_df1_inst_f32 *S, + float32_t *pSrc, float32_t *pDst, + uint32_t blockSize) +{ + float32_t *pIn = pSrc; /* source pointer */ + float32_t *pOut = pDst; /* destination pointer */ + float32_t *pState = S->pState; /* pState pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* coefficient pointer */ + float32_t acc; /* Simulates the accumulator */ + float32_t b0, b1, b2, a1, a2; /* Filter coefficients */ + float32_t Xn1, Xn2, Yn1, Yn2; /* Filter pState variables */ + float32_t Xn; /* temporary input */ + uint32_t sample, stage = S->numStages; /* loop counters */ + + do { + /* Reading the coefficients */ + b0 = *pCoeffs++; + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + /* Reading the pState values */ + Xn1 = pState[0]; + Xn2 = pState[1]; + Yn1 = pState[2]; + Yn2 = pState[3]; + + /* The variables acc holds the output value that is computed: + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 + * * y[n-2] + */ + + sample = blockSize; + + while (sample > 0U) { + /* Read the input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * + * y[n-2] */ + acc = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn1) + (a2 * Yn2); + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = acc; + + /* Every time after the output is computed state should be updated. + */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + Xn2 = Xn1; + Xn1 = Xn; + Yn2 = Yn1; + Yn1 = acc; + + /* decrement the loop counter */ + sample--; + } + + /* Store the updated state variables back into the pState array */ + *pState++ = Xn1; + *pState++ = Xn2; + *pState++ = Yn1; + *pState++ = Yn2; + + /* The first stage goes from the input buffer to the output buffer. */ + /* Subsequent numStages occur in-place in the output buffer */ + pIn = pDst; + + /* Reset the output pointer */ + pOut = pDst; + + /* decrement the loop counter */ + stage--; + + } while (stage > 0U); +} + +void ref_biquad_cas_df1_32x64_q31(const riscv_biquad_cas_df1_32x64_ins_q31 *S, + q31_t *pSrc, q31_t *pDst, uint32_t blockSize) +{ + q31_t *pIn = pSrc; /* input pointer initialization */ + q31_t *pOut = pDst; /* output pointer initialization */ + q63_t *pState = + S->pState; /* state pointer initialization */ + const q31_t *pCoeffs = + S->pCoeffs; /* coeff pointer initialization */ + q63_t acc; /* accumulator */ + q31_t Xn1, Xn2; /* Input Filter state variables */ + q63_t Yn1, Yn2; /* Output Filter state variables */ + q31_t b0, b1, b2, a1, a2; /* Filter coefficients */ + q31_t Xn; /* temporary input */ + int32_t shift = (int32_t)S->postShift + + 1; /* Shift to be applied to the output */ + uint32_t sample, stage = S->numStages; /* loop counters */ + q31_t acc_l, acc_h; /* temporary output */ + uint32_t uShift = ((uint32_t)S->postShift + 1U); + uint32_t lShift = 32U - uShift; /* Shift to be applied to the output + */ + + do { + /* Reading the coefficients */ + b0 = *pCoeffs++; + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + /* Reading the state values */ + Xn1 = pState[0]; + Xn2 = pState[1]; + Yn1 = pState[2]; + Yn2 = pState[3]; + + sample = blockSize; + + while (sample > 0U) { + /* Read the input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * + * y[n-2] */ + acc = (q63_t)Xn * b0 + (q63_t)Xn1 * b1 + (q63_t)Xn2 * b2; + /* acc += a1 * y[n-1] */ + acc += mult32x64(Yn1, a1); + /* acc += a2 * y[n-2] */ + acc += mult32x64(Yn2, a2); + + /* Every time after the output is computed state should be updated. + */ + Xn2 = Xn1; + Xn1 = Xn; + Yn2 = Yn1; + + /* The result is converted to 1.63, Yn1 variable is reused */ + Yn1 = acc << shift; + + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + /* Apply shift for lower part of acc and upper part of acc */ + acc_h = (uint32_t)acc_l >> lShift | acc_h << uShift; + + /* Store the output in the destination buffer in 1.31 format. */ + *pOut++ = acc_h; + + /* decrement the loop counter */ + sample--; + } + + /* The first stage output is given as input to the second stage. */ + pIn = pDst; + + /* Reset to destination buffer working pointer */ + pOut = pDst; + + /* Store the updated state variables back into the pState array */ + *pState++ = (q63_t)Xn1; + *pState++ = (q63_t)Xn2; + *pState++ = Yn1; + *pState++ = Yn2; + + } while (--stage); +} + +void ref_biquad_cascade_df1_q31(const riscv_biquad_casd_df1_inst_q31 *S, + q31_t *pSrc, q31_t *pDst, uint32_t blockSize) +{ + q63_t acc; /* accumulator */ + uint32_t uShift = ((uint32_t)S->postShift + 1U); + uint32_t lShift = 32U - uShift; /* Shift to be applied to the output */ + q31_t *pIn = pSrc; /* input pointer initialization */ + q31_t *pOut = pDst; /* output pointer initialization */ + q31_t *pState = S->pState; /* pState pointer initialization */ + const q31_t *pCoeffs = S->pCoeffs; /* coeff pointer initialization */ + q31_t Xn1, Xn2, Yn1, Yn2; /* Filter state variables */ + q31_t b0, b1, b2, a1, a2; /* Filter coefficients */ + q31_t Xn; /* temporary input */ + uint32_t sample, stage = S->numStages; /* loop counters */ + + do { + /* Reading the coefficients */ + b0 = *pCoeffs++; + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + /* Reading the state values */ + Xn1 = pState[0]; + Xn2 = pState[1]; + Yn1 = pState[2]; + Yn2 = pState[3]; + + /* The variables acc holds the output value that is computed: + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * + * y[n-2] + */ + + sample = blockSize; + + while (sample > 0U) { + /* Read the input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * + * y[n-2] */ + /* acc = b0 * x[n] */ + acc = (q63_t)b0 * Xn; + + /* acc += b1 * x[n-1] */ + acc += (q63_t)b1 * Xn1; + /* acc += b[2] * x[n-2] */ + acc += (q63_t)b2 * Xn2; + /* acc += a1 * y[n-1] */ + acc += (q63_t)a1 * Yn1; + /* acc += a2 * y[n-2] */ + acc += (q63_t)a2 * Yn2; + + /* The result is converted to 1.31 */ + acc = acc >> lShift; + + /* Every time after the output is computed state should be updated. + */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + Xn2 = Xn1; + Xn1 = Xn; + Yn2 = Yn1; + Yn1 = (q31_t)acc; + + /* Store the output in the destination buffer. */ + *pOut++ = (q31_t)acc; + + /* decrement the loop counter */ + sample--; + } + + /* The first stage goes from the input buffer to the output buffer. */ + /* Subsequent stages occur in-place in the output buffer */ + pIn = pDst; + + /* Reset to destination pointer */ + pOut = pDst; + + /* Store the updated state variables back into the pState array */ + *pState++ = Xn1; + *pState++ = Xn2; + *pState++ = Yn1; + *pState++ = Yn2; + + } while (--stage); +} + +void ref_biquad_cascade_df1_fast_q31(const riscv_biquad_casd_df1_inst_q31 *S, + q31_t *pSrc, q31_t *pDst, + uint32_t blockSize) +{ + q31_t acc = 0; /* accumulator */ + q31_t Xn1, Xn2, Yn1, Yn2; /* Filter state variables */ + q31_t b0, b1, b2, a1, a2; /* Filter coefficients */ + q31_t *pIn = pSrc; /* input pointer initialization */ + q31_t *pOut = pDst; /* output pointer initialization */ + q31_t *pState = S->pState; /* pState pointer initialization */ + const q31_t *pCoeffs = S->pCoeffs; /* coeff pointer initialization */ + q31_t Xn; /* temporary input */ + int32_t shift = + (int32_t)S->postShift + 1; /* Shift to be applied to the output */ + uint32_t sample, stage = S->numStages; /* loop counters */ + + do { + /* Reading the coefficients */ + b0 = *pCoeffs++; + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + /* Reading the state values */ + Xn1 = pState[0]; + Xn2 = pState[1]; + Yn1 = pState[2]; + Yn2 = pState[3]; + + sample = blockSize; + + while (sample > 0U) { + /* Read the input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * + * y[n-2] */ + mult_32x32_keep32_R(acc, b0, Xn); + multAcc_32x32_keep32_R(acc, b1, Xn1); + multAcc_32x32_keep32_R(acc, b2, Xn2); + multAcc_32x32_keep32_R(acc, a1, Yn1); + multAcc_32x32_keep32_R(acc, a2, Yn2); + + /* The result is converted to 1.31 */ + acc <<= shift; + + /* Every time after the output is computed state should be updated. + */ + Xn2 = Xn1; + Xn1 = Xn; + Yn2 = Yn1; + Yn1 = acc; + + /* Store the output in the destination buffer. */ + *pOut++ = acc; + + /* decrement the loop counter */ + sample--; + } + + /* The first stage goes from the input buffer to the output buffer. */ + /* Subsequent stages occur in-place in the output buffer */ + pIn = pDst; + + /* Reset to destination pointer */ + pOut = pDst; + + /* Store the updated state variables back into the pState array */ + *pState++ = Xn1; + *pState++ = Xn2; + *pState++ = Yn1; + *pState++ = Yn2; + + } while (--stage); +} + +void ref_biquad_cascade_df1_fast_q15(const riscv_biquad_casd_df1_inst_q15 *S, + q15_t *pSrc, q15_t *pDst, + uint32_t blockSize) +{ + q15_t *pIn = pSrc; /* Source pointer */ + q15_t *pOut = pDst; /* Destination pointer */ + q15_t b0, b1, b2, a1, + a2; /* Filter coefficients */ + q15_t Xn1, Xn2, Yn1, + Yn2; /* Filter state variables */ + q15_t Xn; /* temporary input */ + q31_t acc; /* Accumulator */ + int32_t shift = (15 - (int32_t)S->postShift); /* Post shift */ + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + uint32_t sample, stage = (uint32_t)S->numStages; /* Stage loop counter */ + + do { + /* Reading the coefficients */ + b0 = *pCoeffs++; + pCoeffs++; // skip the 0 coefficient + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + /* Reading the state values */ + Xn1 = pState[0]; + Xn2 = pState[1]; + Yn1 = pState[2]; + Yn2 = pState[3]; + + sample = blockSize; + + while (sample > 0U) { + /* Read the input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * + * y[n-2] */ + acc = (q31_t)b0 * Xn + (q31_t)b1 * Xn1 + (q31_t)b2 * Xn2 + + (q31_t)a1 * Yn1 + (q31_t)a2 * Yn2; + + /* The result is converted to 1.15 */ + acc = ref_sat_q15(acc >> shift); + + /* Every time after the output is computed state should be updated. + */ + Xn2 = Xn1; + Xn1 = Xn; + Yn2 = Yn1; + Yn1 = (q15_t)acc; + + /* Store the output in the destination buffer. */ + *pOut++ = (q15_t)acc; + + /* decrement the loop counter */ + sample--; + } + + /* The first stage goes from the input buffer to the output buffer. */ + /* Subsequent stages occur in-place in the output buffer */ + pIn = pDst; + + /* Reset to destination pointer */ + pOut = pDst; + + /* Store the updated state variables back into the pState array */ + *pState++ = Xn1; + *pState++ = Xn2; + *pState++ = Yn1; + *pState++ = Yn2; + + } while (--stage); +} + +void ref_biquad_cascade_df1_q15(const riscv_biquad_casd_df1_inst_q15 *S, + q15_t *pSrc, q15_t *pDst, uint32_t blockSize) +{ + q15_t *pIn = pSrc; /* Source pointer */ + q15_t *pOut = pDst; /* Destination pointer */ + q15_t b0, b1, b2, a1, + a2; /* Filter coefficients */ + q15_t Xn1, Xn2, Yn1, + Yn2; /* Filter state variables */ + q15_t Xn; /* temporary input */ + q63_t acc; /* Accumulator */ + int32_t shift = (15 - (int32_t)S->postShift); /* Post shift */ + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + uint32_t sample, stage = (uint32_t)S->numStages; /* Stage loop counter */ + + do { + /* Reading the coefficients */ + b0 = *pCoeffs++; + pCoeffs++; // skip the 0 coefficient + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + /* Reading the state values */ + Xn1 = pState[0]; + Xn2 = pState[1]; + Yn1 = pState[2]; + Yn2 = pState[3]; + + sample = blockSize; + + while (sample > 0U) { + /* Read the input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * + * y[n-2] */ + acc = (q31_t)b0 * Xn + (q31_t)b1 * Xn1 + (q31_t)b2 * Xn2 + + (q31_t)a1 * Yn1 + (q31_t)a2 * Yn2; + + /* The result is converted to 1.15 */ + acc = ref_sat_q15(acc >> shift); + + /* Every time after the output is computed state should be updated. + */ + Xn2 = Xn1; + Xn1 = Xn; + Yn2 = Yn1; + Yn1 = (q15_t)acc; + + /* Store the output in the destination buffer. */ + *pOut++ = (q15_t)acc; + + /* decrement the loop counter */ + sample--; + } + + /* The first stage goes from the input buffer to the output buffer. */ + /* Subsequent stages occur in-place in the output buffer */ + pIn = pDst; + + /* Reset to destination pointer */ + pOut = pDst; + + /* Store the updated state variables back into the pState array */ + *pState++ = Xn1; + *pState++ = Xn2; + *pState++ = Yn1; + *pState++ = Yn2; + + } while (--stage); +} diff --git a/examples/dsp/FilteringFunction_iirdf1/main.c b/examples/dsp/FilteringFunction_iirdf1/main.c new file mode 100644 index 00000000..969fca4e --- /dev/null +++ b/examples/dsp/FilteringFunction_iirdf1/main.c @@ -0,0 +1,287 @@ +// +// Created by lujun on 19-6-28. +// +// This contains IIR, iir and lms filters +// each one has it's own function. +// All function can be found in main function. +// If you don't want to use it, then comment it. +// +// This part only tests result after 50 dots.If you want to test results' all +// dots, please define WITH_FRONT +// +// If there are too much numbers which makes it hard to read,in VScode you can +// press alt and z can shrimp them to one line +// +// You MUST be careful about overflow. +#include "riscv_math.h" +#include "array.h" +#include +#include +#include "../common.h" + +#include "../HelperFunctions/math_helper.c" +#include "../HelperFunctions/ref_helper.c" + +#define DELTAF32 (0.05f) +#define DELTAQ31 (63) +#define DELTAQ15 (1) +#define DELTAQ7 (1) +#define SNR_THRESHOLD_F32 (80.0f) + +int test_flag_error = 0; + +// #define WITH_FRONT + +//*************************************************************************************** +// iir df1 +//*************************************************************************************** +static void riscv_iir_f32_lp(void) +{ + uint32_t i; + /* clang-format off */ + riscv_biquad_casd_df1_inst_f32 S; + /* clang-format on */ + // float32_t ScaleValue; + riscv_biquad_cascade_df1_init_f32(&S, numStages, IIRCoeffs32LP, &IIRStateF32[0]); + BENCH_START(riscv_biquad_cascade_df1_f32); + riscv_biquad_cascade_df1_f32(&S, testInput_f32_50Hz_200Hz, testOutput_f32, TEST_LENGTH_SAMPLES); + BENCH_END(riscv_biquad_cascade_df1_f32); + riscv_biquad_cascade_df1_init_f32(&S, numStages, IIRCoeffs32LP, &IIRStateF32[0]); + ref_biquad_cascade_df1_f32(&S, testInput_f32_50Hz_200Hz, testOutput_f32_ref, TEST_LENGTH_SAMPLES); + // ScaleValue = 0.052219514664161221f * 0.04279801741658381f; + // 0.115258015230151708574446445254579884931 + // 0.08857935624534613028302487691689748317 +#ifndef WITH_FRONT + float snr = riscv_snr_f32(&testOutput_f32_ref[50], &testOutput_f32[50], 269); + + if (snr < SNR_THRESHOLD_F32) { + BENCH_ERROR(riscv_biquad_cascade_df1_f32); + printf("f32 biquad_cascade_df1 failed with snr:%f\n", snr); + test_flag_error = 1; + } + BENCH_STATUS(riscv_biquad_cascade_df1_f32); +#else + float snr = + riscv_snr_f32(&testOutput_ref[0], &testOutput[0], TEST_LENGTH_SAMPLES); + + if (snr < SNR_THRESHOLD_F32) { + BENCH_ERROR(riscv_biquad_cascade_df1_f32); + printf("f32 biquad_cascade_df1 failed with snr:%f\n", snr); + test_flag_error = 1; + } + BENCH_STATUS(riscv_biquad_cascade_df1_f32); +#endif +} +static void riscv_iir_q31_lp(void) +{ + uint32_t i; + /* clang-format off */ + riscv_biquad_casd_df1_inst_q31 S; + /* clang-format on */ + // riscv_scale_f32(testInput_f32_50Hz_200Hz, 0.001, testInput_f32_50Hz_200Hz, TEST_LENGTH_SAMPLES); + riscv_float_to_q31(testInput_f32_50Hz_200Hz, testInput_q31_50Hz_200Hz, TEST_LENGTH_SAMPLES); + riscv_float_to_q31(IIRCoeffs32LP, IIRCoeffsQ31LP, 5*numStages); + // float32_t ScaleValue; + riscv_biquad_cascade_df1_init_q31(&S, numStages, IIRCoeffsQ31LP, &IIRStateq31[0], 0); + BENCH_START(riscv_biquad_cascade_df1_q31); + riscv_biquad_cascade_df1_q31(&S, testInput_q31_50Hz_200Hz, testOutput_q31, TEST_LENGTH_SAMPLES); + BENCH_END(riscv_biquad_cascade_df1_q31); + riscv_biquad_cascade_df1_init_q31(&S, numStages, IIRCoeffsQ31LP, &IIRStateq31[0], 0); + ref_biquad_cascade_df1_q31(&S, testInput_q31_50Hz_200Hz, testOutput_q31_ref, TEST_LENGTH_SAMPLES); + // ScaleValue = 0.052219514664161221f * 0.04279801741658381f; + riscv_q31_to_float(testOutput_q31, testOutput_f32, TEST_LENGTH_SAMPLES); + riscv_q31_to_float(testOutput_q31_ref, testOutput_f32_ref, TEST_LENGTH_SAMPLES); +#ifndef WITH_FRONT + float snr = riscv_snr_f32(&testOutput_f32_ref[50], &testOutput_f32[50], 269); + + if (snr < SNR_THRESHOLD_F32) { + BENCH_ERROR(riscv_biquad_cascade_df1_q31); + printf("q31 biquad_cascade_df1 failed with snr:%f\n", snr); + test_flag_error = 1; + } + BENCH_STATUS(riscv_biquad_cascade_df1_q31); +#else + float snr = riscv_snr_f32(&testOutput_f32_ref[0], &testOutput_f32[0], + TEST_LENGTH_SAMPLES); + + if (snr < SNR_THRESHOLD_F32) { + BENCH_ERROR(riscv_biquad_cascade_df1_q31); + printf("q31 biquad_cascade_df1 failed with snr:%f\n", snr); + test_flag_error = 1; + } + BENCH_STATUS(riscv_biquad_cascade_df1_q31); +#endif +} +static void riscv_iir_q15_lp(void) +{ + /* clang-format off */ + riscv_biquad_casd_df1_inst_q15 S; + /* clang-format on */ + riscv_scale_f32(testInput_f32_50Hz_200Hz_temp, 0.002, testInput_f32_50Hz_200Hz, TEST_LENGTH_SAMPLES); + riscv_float_to_q15(testInput_f32_50Hz_200Hz, testInput_q15_50Hz_200Hz, TEST_LENGTH_SAMPLES); + float32_t ScaleValue; + riscv_biquad_cascade_df1_init_q15(&S, numStages, IIRCoeffsQ15LP, &IIRStateq15[0], 1); + BENCH_START(riscv_biquad_cascade_df1_q15); + riscv_biquad_cascade_df1_q15(&S, testInput_q15_50Hz_200Hz, testOutput_q15, TEST_LENGTH_SAMPLES); + BENCH_END(riscv_biquad_cascade_df1_q15); + // ScaleValue = 0.052219514664161221f * 0.04279801741658381f; + riscv_q15_to_float(testOutput_q15, testOutput_f32, TEST_LENGTH_SAMPLES); + riscv_q15_to_float(testOutput_q15_ref, testOutput_f32_ref, TEST_LENGTH_SAMPLES); +#ifndef WITH_FRONT + float snr = riscv_snr_f32(&testOutput_f32_ref[50], &testOutput_f32[50], 200); + + if (snr < SNR_THRESHOLD_F32) { + BENCH_ERROR(riscv_biquad_cascade_df1_q15); + printf("q15 biquad_cascade_df1 failed with snr:%f\n", snr); + test_flag_error = 1; + } + BENCH_STATUS(riscv_biquad_cascade_df1_q15); +#else + float snr = riscv_snr_f32(&testOutput_f32_ref[0], &testOutput_f32[0], + TEST_LENGTH_SAMPLES); + + if (snr < SNR_THRESHOLD_F32) { + BENCH_ERROR(riscv_biquad_cascade_df1_q15); + printf("q15 biquad_cascade_df1 failed with snr:%f\n", snr); + test_flag_error = 1; + } + BENCH_STATUS(riscv_biquad_cascade_df1_q15); +#endif +} +static void riscv_iir_q31_fast_lp(void) +{ + uint32_t i; + /* clang-format off */ + riscv_biquad_casd_df1_inst_q31 S; + /* clang-format on */ + // riscv_scale_f32(testInput_f32_50Hz_200Hz, 0.001, testInput_f32_50Hz_200Hz, TEST_LENGTH_SAMPLES); + riscv_float_to_q31(testInput_f32_50Hz_200Hz, testInput_q31_50Hz_200Hz, TEST_LENGTH_SAMPLES); + riscv_float_to_q31(IIRCoeffs32LP, IIRCoeffsQ31LP, 5*numStages); + // float32_t ScaleValue; + riscv_biquad_cascade_df1_init_q31(&S, numStages, IIRCoeffsQ31LP, &IIRStateq31[0], 0); + BENCH_START(riscv_biquad_cascade_df1_fast_q31); + riscv_biquad_cascade_df1_fast_q31(&S, testInput_q31_50Hz_200Hz, testOutput_q31, TEST_LENGTH_SAMPLES); + BENCH_END(riscv_biquad_cascade_df1_fast_q31); + riscv_biquad_cascade_df1_init_q31(&S, numStages, IIRCoeffsQ31LP, &IIRStateq31[0], 0); + ref_biquad_cascade_df1_fast_q31(&S, testInput_q31_50Hz_200Hz, testOutput_q31_ref, TEST_LENGTH_SAMPLES); + // ScaleValue = 0.052219514664161221f * 0.04279801741658381f; + riscv_q31_to_float(testOutput_q31, testOutput_f32, TEST_LENGTH_SAMPLES); + riscv_q31_to_float(testOutput_q31_ref, testOutput_f32_ref, TEST_LENGTH_SAMPLES); +#ifndef WITH_FRONT + float snr = riscv_snr_f32(&testOutput_f32_ref[50], &testOutput_f32[50], 269); + + if (snr < SNR_THRESHOLD_F32) { + BENCH_ERROR(riscv_biquad_cascade_df1_fast_q31); + printf("q31 biquad_cascade_df1_fast failed with snr:%f\n", snr); + test_flag_error = 1; + } + BENCH_STATUS(riscv_biquad_cascade_df1_fast_q31); +#else + float snr = riscv_snr_f32(&testOutput_f32_ref[0], &testOutput_f32[0], + TEST_LENGTH_SAMPLES); + + if (snr < SNR_THRESHOLD_F32) { + BENCH_ERROR(riscv_biquad_cascade_df1_fast_q31); + printf("q31 biquad_cascade_df1_fast failed with snr:%f\n", snr); + test_flag_error = 1; + } + BENCH_STATUS(riscv_biquad_cascade_df1_fast_q31); +#endif +} +static void riscv_iir_q15_fast_lp(void) +{ + uint32_t i; + /* clang-format off */ + riscv_biquad_casd_df1_inst_q15 S; + /* clang-format on */ + riscv_scale_f32(testInput_f32_50Hz_200Hz_temp, 0.001, testInput_f32_50Hz_200Hz, TEST_LENGTH_SAMPLES); + riscv_float_to_q15(testInput_f32_50Hz_200Hz, testInput_q15_50Hz_200Hz, TEST_LENGTH_SAMPLES); + // float32_t ScaleValue; + riscv_biquad_cascade_df1_init_q15(&S, numStages, IIRCoeffsQ15LP, &IIRStateq15[0], 1); + BENCH_START(riscv_biquad_cascade_df1_fast_q15); + riscv_biquad_cascade_df1_fast_q15(&S, testInput_q15_50Hz_200Hz, testOutput_q15, TEST_LENGTH_SAMPLES); + BENCH_END(riscv_biquad_cascade_df1_fast_q15); + // ScaleValue + // = 0.052219514664161221f * 0.04279801741658381f; + riscv_q15_to_float(testOutput_q15, testOutput_f32, TEST_LENGTH_SAMPLES); + riscv_q15_to_float(testOutput_fast_ref, testOutput_f32_ref, TEST_LENGTH_SAMPLES); +#ifndef WITH_FRONT + float snr = riscv_snr_f32(&testOutput_f32_ref[50], &testOutput_f32[50], 269); + + if (snr < SNR_THRESHOLD_F32) { + BENCH_ERROR(riscv_biquad_cascade_df1_fast_q15); + printf("q15 biquad_cascade_df1_fast failed with snr:%f\n", snr); + test_flag_error = 1; + } + BENCH_STATUS(riscv_biquad_cascade_df1_fast_q15); +#else + float snr = riscv_snr_f32(&testOutput_f32_ref[0], &testOutput_f32[0], + TEST_LENGTH_SAMPLES); + + if (snr < SNR_THRESHOLD_F32) { + BENCH_ERROR(riscv_biquad_cascade_df1_fast_q15); + printf("q15 biquad_cascade_df1_fast failed with snr:%f\n", snr); + test_flag_error = 1; + } + BENCH_STATUS(riscv_biquad_cascade_df1_fast_q15); +#endif +} +static void riscv_iir_q31_32x64_lp(void) +{ + uint32_t i; + /* clang-format off */ + riscv_biquad_cas_df1_32x64_ins_q31 S; + /* clang-format on */ + // riscv_scale_f32(testInput_f32_50Hz_200Hz, 0.001, testInput_f32_50Hz_200Hz, TEST_LENGTH_SAMPLES); + riscv_float_to_q31(testInput_f32_50Hz_200Hz, testInput_q31_50Hz_200Hz, TEST_LENGTH_SAMPLES); + riscv_float_to_q31(IIRCoeffs32LP, IIRCoeffsQ31LP, 5*numStages); + // float32_t ScaleValue; + riscv_biquad_cas_df1_32x64_init_q31(&S, numStages, IIRCoeffsQ31LP, &IIRState32x64[0], 0); + BENCH_START(riscv_biquad_cas_df1_32x64_q31); + riscv_biquad_cas_df1_32x64_q31(&S, testInput_q31_50Hz_200Hz, testOutput_q31, TEST_LENGTH_SAMPLES); + BENCH_END(riscv_biquad_cas_df1_32x64_q31); + riscv_biquad_cas_df1_32x64_init_q31(&S, numStages, IIRCoeffsQ31LP, &IIRState32x64[0], 0); + ref_biquad_cas_df1_32x64_q31(&S, testInput_q31_50Hz_200Hz, testOutput_q31_ref, TEST_LENGTH_SAMPLES); + // ScaleValue = 0.052219514664161221f * 0.04279801741658381f; + riscv_q31_to_float(testOutput_q31, testOutput_f32, TEST_LENGTH_SAMPLES); + riscv_q31_to_float(testOutput_q31_ref, testOutput_f32_ref, TEST_LENGTH_SAMPLES); +#ifndef WITH_FRONT + float snr = riscv_snr_f32(&testOutput_f32_ref[50], &testOutput_f32[50], 269); + + if (snr < SNR_THRESHOLD_F32) { + BENCH_ERROR(riscv_biquad_cas_df1_32x64_q31); + printf("q31 biquad_cas_df1_32x64 failed with snr:%f\n", snr); + test_flag_error = 1; + } + BENCH_STATUS(riscv_biquad_cas_df1_32x64_q31); +#else + float snr = riscv_snr_f32(&testOutput_f32_ref[0], &testOutput_f32[0], + TEST_LENGTH_SAMPLES); + + if (snr < SNR_THRESHOLD_F32) { + BENCH_ERROR(riscv_biquad_cas_df1_32x64_q31); + printf("q31 biquad_cas_df1_32x64 failed with snr:%f\n", snr); + test_flag_error = 1; + } + BENCH_STATUS(riscv_biquad_cas_df1_32x64_q31); +#endif +} + +int main() +{ + BENCH_INIT; + riscv_iir_f32_lp(); + riscv_iir_q31_lp(); + riscv_iir_q15_lp(); + riscv_iir_q31_fast_lp(); + riscv_iir_q15_fast_lp(); + riscv_iir_q31_32x64_lp(); + BENCH_FINISH; + if (test_flag_error) { + printf("test error apprears, please recheck.\n"); + return 1; + } else { + printf("all test are passed. Well done!\n"); + } + return 0; +} diff --git a/examples/dsp/FilteringFunction_iirdf2t/CMakeLists.txt b/examples/dsp/FilteringFunction_iirdf2t/CMakeLists.txt new file mode 100644 index 00000000..941f6763 --- /dev/null +++ b/examples/dsp/FilteringFunction_iirdf2t/CMakeLists.txt @@ -0,0 +1,5 @@ +set(TARGET_REQUIRED_PRIVATE_INCLUDE ${CMAKE_CURRENT_SOURCE_DIR} ${CMAKE_CURRENT_SOURCE_DIR}/..) +set(TARGET_REQUIRED_SRCS biquad.c) +set(TARGET_REQUIRED_LIBS nmsis) +set(mains main.c) +generate_bin() \ No newline at end of file diff --git a/examples/dsp/FilteringFunction_iirdf2t/array.h b/examples/dsp/FilteringFunction_iirdf2t/array.h new file mode 100644 index 00000000..130c253b --- /dev/null +++ b/examples/dsp/FilteringFunction_iirdf2t/array.h @@ -0,0 +1,16 @@ +// Array for FilteringFunctions iirdf2t +#define TEST_LENGTH_SAMPLES 320 /* 采样点数 */ +#define numStages 2 /* 2阶IIR滤波的个数 */ +// float32_t +// stereo requires 2*TEST_LENGTH_SAMPLES + float32_t testOutput_f32[TEST_LENGTH_SAMPLES*2],testOutput_f32_ref[TEST_LENGTH_SAMPLES*2]; + float32_t IIRStateF32[2*numStages]={0}; + float32_t IIRCoeffs32LP[5*numStages] = {1.0f, 2.0f, 1.0f, 1.11302985416334787593939381622476503253f, - 0.574061915083954765748330828500911593437f,1.0f, 2.0f, 1.0f, 0.855397932775170177777113167394418269396f, - 0.209715357756554754420363906319835223258f}; + float32_t testInput_f32_50Hz_200Hz[TEST_LENGTH_SAMPLES] = {0, 1.26007351067010, 1.17557050458495, 0.221231742082474, -1.11022302462516e-16, 1.00000000000000, 1.90211303259031, 1.39680224666742, 4.44089209850063e-16, -0.642039521920206, -3.67394039744206e-16, 0.642039521920206, -1.22124532708767e-15, -1.39680224666742, -1.90211303259031, -1.00000000000000, -3.33066907387547e-16, -0.221231742082476, -1.17557050458495, -1.26007351067010, -1.22464679914735e-15, 1.26007351067010, 1.17557050458495, 0.221231742082475, 8.88178419700125e-16, 1.00000000000000, 1.90211303259031, 1.39680224666742, 1.33226762955019e-15, -0.642039521920206, -1.10218211923262e-15, 0.642039521920206, 1.55431223447522e-15, -1.39680224666743, -1.90211303259031, -0.999999999999995, -7.77156117237610e-16, -0.221231742082473, -1.17557050458495, -1.26007351067010, -2.44929359829471e-15, 1.26007351067010, 1.17557050458494, 0.221231742082476, -7.77156117237610e-16, 0.999999999999998, 1.90211303259031, 1.39680224666742, -4.88498130835069e-15, -0.642039521920206, 3.49210031947972e-15, 0.642039521920206, 2.55351295663786e-15, -1.39680224666742, -1.90211303259031, -0.999999999999996, -9.99200722162641e-16, -0.221231742082477, -1.17557050458494, -1.26007351067011, -3.67394039744206e-15, 1.26007351067010, 1.17557050458495, 0.221231742082472, -1.22124532708767e-15, 1.00000000000000, 1.90211303259031, 1.39680224666742, -1.09912079437891e-14, -0.642039521920206, 8.08638275819206e-15, 0.642039521920205, 3.55271367880050e-15, -1.39680224666741, -1.90211303259031, -0.999999999999997, -1.44328993201270e-15, -0.221231742082476, -1.17557050458494, -1.26007351067010, -4.89858719658941e-15, 1.26007351067010, 1.17557050458494, 0.221231742082472, 3.88578058618805e-15, 1.00000000000000, 1.90211303259031, 1.39680224666743, 4.44089209850063e-15, -0.642039521920207, -3.30654635769785e-15, 0.642039521920206, 4.55191440096314e-15, -1.39680224666742, -1.90211303259031, -0.999999999999998, 3.66373598126302e-15, -0.221231742082476, -1.17557050458495, -1.26007351067010, 1.16403343982657e-14, 1.26007351067010, 1.17557050458496, 0.221231742082482, -1.99840144432528e-15, 1.00000000000000, 1.90211303259031, 1.39680224666743, 5.44009282066327e-15, -0.642039521920206, 6.61680659921524e-15, 0.642039521920207, 5.55111512312578e-15, -1.39680224666742, -1.90211303259031, -0.999999999999984, -2.10942374678780e-15, -0.221231742082475, -1.17557050458493, -1.26007351067011, -7.34788079488412e-15, 1.26007351067010, 1.17557050458494, 0.221231742082483, -2.33146835171283e-15, 1.00000000000000, 1.90211303259031, 1.39680224666741, 6.32827124036339e-15, -0.642039521920206, 5.88201851972683e-15, 0.642039521920207, -2.22044604925031e-14, -1.39680224666742, -1.90211303259031, -0.999999999999985, 8.43769498715119e-15, -0.221231742082475, -1.17557050458495, -1.26007351067009, 2.69546091939735e-14, 1.26007351067009, 1.17557050458496, 0.221231742082484, -2.77555756156289e-15, 1, 1.90211303259030, 1.39680224666743, 7.32747196252603e-15, -0.642039521920206, 5.14723044023841e-15, 0.642039521920205, 7.54951656745106e-15, -1.39680224666742, -1.90211303259031, -0.999999999999986, -2.99760216648792e-15, -0.221231742082474, -1.17557050458495, -1.26007351067009, -9.79717439317883e-15, 1.26007351067010, 1.17557050458494, 0.221231742082465, 7.88258347483861e-15, 0.999999999999999, 1.90211303259031, 1.39680224666741, -2.04281036531029e-14, -0.642039521920204, 4.41244236075000e-15, 0.642039521920207, 8.43769498715119e-15, -1.39680224666742, -1.90211303259031, -1.00000000000002, -3.33066907387547e-15, -0.221231742082473, -1.17557050458493, -1.26007351067011, -1.10218211923262e-14, 1.26007351067010, 1.17557050458494, 0.221231742082485, -3.44169137633799e-15, 0.999999999999998, 1.90211303259031, 1.39680224666741, 9.32587340685132e-15, -0.642039521920206, 3.67765428126159e-15, 0.642039521920207, -1.93178806284777e-14, -1.39680224666742, -1.90211303259031, -0.999999999999988, 7.32747196252603e-15, -0.221231742082492, -1.17557050458495, -1.26007351067009, 2.32806687965315e-14, 1.26007351067012, 1.17557050458494, 0.221231742082467, -1.47659662275146e-14, 0.999999999999969, 1.90211303259030, 1.39680224666744, 1.02140518265514e-14, -0.642039521920206, 2.94286620177318e-15, 0.642039521920207, -1.83186799063151e-14, -1.39680224666739, -1.90211303259031, -1.00000000000002, -4.10782519111308e-15, -0.221231742082472, -1.17557050458495, -1.26007351067010, 2.20560219973841e-14, 1.26007351067011, 1.17557050458493, 0.221231742082486, -4.21884749357560e-15, 0.999999999999996, 1.90211303259031, 1.39680224666741, -1.75415237890775e-14, -0.642039521920204, 2.35243601950878e-14, 0.642039521920209, 1.15463194561016e-14, -1.39680224666742, -1.90211303259031, -0.999999999999990, -1.54321000422897e-14, -0.221231742082452, -1.17557050458493, -1.26007351067011, -1.46957615897682e-14, 1.26007351067010, 1.17557050458495, 0.221231742082468, 6.32827124036339e-15, 1.00000000000002, 1.90211303259030, 1.39680224666744, 1.23234755733392e-14, -0.642039521920207, 1.47329004279635e-15, 0.642039521920207, -1.62092561595273e-14, -1.39680224666744, -1.90211303259030, -1.00000000000002, -4.88498130835069e-15, -0.221231742082471, -1.17557050458495, -1.26007351067010, 1.96067283990894e-14, 1.26007351067011, 1.17557050458493, 0.221231742082450, 1.69864122767649e-14, 0.999999999999994, 1.90211303259031, 1.39680224666741, -1.54321000422897e-14, -0.642039521920205, 2.20547840361110e-14, 0.642039521920209, -4.39648317751562e-14, -1.39680224666747, -1.90211303259031, -0.999999999999992, 5.77315972805081e-15, -0.221231742082489, -1.17557050458496, -1.26007351067008, 5.39092183879471e-14, 1.26007351067013, 1.17557050458498, 0.221231742082507, -1.63202784619898e-14, 0.999999999999965, 1.90211303259030, 1.39680224666744, 1.43218770176645e-14, -0.642039521920207, 3.71388381953015e-18, 0.642039521920203, 4.31876756579186e-14, -1.39680224666739, -1.90211303259031, -1.00000000000002, -5.55111512312578e-15, -0.221231742082469, -1.17557050458495, -1.26007351067010, 1.71574348007947e-14, 1.26007351067008, 1.17557050458496, 0.221231742082489, -5.77315972805081e-15, 0.999999999999992, 1.90211303259031, 1.39680224666741, -1.34336985979644e-14, -0.642039521920205, 2.05852078771341e-14, 0.642039521920205, 1.54321000422897e-14, -1.39680224666741, -1.90211303259031, -0.999999999999994, 4.99600361081320e-15, -0.221231742082488, -1.17557050458496, -1.26007351067008}; + +// float64_t + float64_t testOutput_f64[TEST_LENGTH_SAMPLES],testOutput_f64_ref[TEST_LENGTH_SAMPLES]; + float64_t IIRStateF64[2*numStages]={0}; + float64_t IIRCoeffs64LP[5*numStages] = {1.0f, 2.0f, 1.0f, 1.11302985416334787593939381622476503253f, - 0.574061915083954765748330828500911593437f,1.0f, 2.0f, 1.0f, 0.855397932775170177777113167394418269396f, - 0.209715357756554754420363906319835223258f}; + float64_t testInput_f64_50Hz_200Hz[TEST_LENGTH_SAMPLES] = {0, 1.26007351067010, 1.17557050458495, 0.221231742082474, -1.11022302462516e-16, 1.00000000000000, 1.90211303259031, 1.39680224666742, 4.44089209850063e-16, -0.642039521920206, -3.67394039744206e-16, 0.642039521920206, -1.22124532708767e-15, -1.39680224666742, -1.90211303259031, -1.00000000000000, -3.33066907387547e-16, -0.221231742082476, -1.17557050458495, -1.26007351067010, -1.22464679914735e-15, 1.26007351067010, 1.17557050458495, 0.221231742082475, 8.88178419700125e-16, 1.00000000000000, 1.90211303259031, 1.39680224666742, 1.33226762955019e-15, -0.642039521920206, -1.10218211923262e-15, 0.642039521920206, 1.55431223447522e-15, -1.39680224666743, -1.90211303259031, -0.999999999999995, -7.77156117237610e-16, -0.221231742082473, -1.17557050458495, -1.26007351067010, -2.44929359829471e-15, 1.26007351067010, 1.17557050458494, 0.221231742082476, -7.77156117237610e-16, 0.999999999999998, 1.90211303259031, 1.39680224666742, -4.88498130835069e-15, -0.642039521920206, 3.49210031947972e-15, 0.642039521920206, 2.55351295663786e-15, -1.39680224666742, -1.90211303259031, -0.999999999999996, -9.99200722162641e-16, -0.221231742082477, -1.17557050458494, -1.26007351067011, -3.67394039744206e-15, 1.26007351067010, 1.17557050458495, 0.221231742082472, -1.22124532708767e-15, 1.00000000000000, 1.90211303259031, 1.39680224666742, -1.09912079437891e-14, -0.642039521920206, 8.08638275819206e-15, 0.642039521920205, 3.55271367880050e-15, -1.39680224666741, -1.90211303259031, -0.999999999999997, -1.44328993201270e-15, -0.221231742082476, -1.17557050458494, -1.26007351067010, -4.89858719658941e-15, 1.26007351067010, 1.17557050458494, 0.221231742082472, 3.88578058618805e-15, 1.00000000000000, 1.90211303259031, 1.39680224666743, 4.44089209850063e-15, -0.642039521920207, -3.30654635769785e-15, 0.642039521920206, 4.55191440096314e-15, -1.39680224666742, -1.90211303259031, -0.999999999999998, 3.66373598126302e-15, -0.221231742082476, -1.17557050458495, -1.26007351067010, 1.16403343982657e-14, 1.26007351067010, 1.17557050458496, 0.221231742082482, -1.99840144432528e-15, 1.00000000000000, 1.90211303259031, 1.39680224666743, 5.44009282066327e-15, -0.642039521920206, 6.61680659921524e-15, 0.642039521920207, 5.55111512312578e-15, -1.39680224666742, -1.90211303259031, -0.999999999999984, -2.10942374678780e-15, -0.221231742082475, -1.17557050458493, -1.26007351067011, -7.34788079488412e-15, 1.26007351067010, 1.17557050458494, 0.221231742082483, -2.33146835171283e-15, 1.00000000000000, 1.90211303259031, 1.39680224666741, 6.32827124036339e-15, -0.642039521920206, 5.88201851972683e-15, 0.642039521920207, -2.22044604925031e-14, -1.39680224666742, -1.90211303259031, -0.999999999999985, 8.43769498715119e-15, -0.221231742082475, -1.17557050458495, -1.26007351067009, 2.69546091939735e-14, 1.26007351067009, 1.17557050458496, 0.221231742082484, -2.77555756156289e-15, 1, 1.90211303259030, 1.39680224666743, 7.32747196252603e-15, -0.642039521920206, 5.14723044023841e-15, 0.642039521920205, 7.54951656745106e-15, -1.39680224666742, -1.90211303259031, -0.999999999999986, -2.99760216648792e-15, -0.221231742082474, -1.17557050458495, -1.26007351067009, -9.79717439317883e-15, 1.26007351067010, 1.17557050458494, 0.221231742082465, 7.88258347483861e-15, 0.999999999999999, 1.90211303259031, 1.39680224666741, -2.04281036531029e-14, -0.642039521920204, 4.41244236075000e-15, 0.642039521920207, 8.43769498715119e-15, -1.39680224666742, -1.90211303259031, -1.00000000000002, -3.33066907387547e-15, -0.221231742082473, -1.17557050458493, -1.26007351067011, -1.10218211923262e-14, 1.26007351067010, 1.17557050458494, 0.221231742082485, -3.44169137633799e-15, 0.999999999999998, 1.90211303259031, 1.39680224666741, 9.32587340685132e-15, -0.642039521920206, 3.67765428126159e-15, 0.642039521920207, -1.93178806284777e-14, -1.39680224666742, -1.90211303259031, -0.999999999999988, 7.32747196252603e-15, -0.221231742082492, -1.17557050458495, -1.26007351067009, 2.32806687965315e-14, 1.26007351067012, 1.17557050458494, 0.221231742082467, -1.47659662275146e-14, 0.999999999999969, 1.90211303259030, 1.39680224666744, 1.02140518265514e-14, -0.642039521920206, 2.94286620177318e-15, 0.642039521920207, -1.83186799063151e-14, -1.39680224666739, -1.90211303259031, -1.00000000000002, -4.10782519111308e-15, -0.221231742082472, -1.17557050458495, -1.26007351067010, 2.20560219973841e-14, 1.26007351067011, 1.17557050458493, 0.221231742082486, -4.21884749357560e-15, 0.999999999999996, 1.90211303259031, 1.39680224666741, -1.75415237890775e-14, -0.642039521920204, 2.35243601950878e-14, 0.642039521920209, 1.15463194561016e-14, -1.39680224666742, -1.90211303259031, -0.999999999999990, -1.54321000422897e-14, -0.221231742082452, -1.17557050458493, -1.26007351067011, -1.46957615897682e-14, 1.26007351067010, 1.17557050458495, 0.221231742082468, 6.32827124036339e-15, 1.00000000000002, 1.90211303259030, 1.39680224666744, 1.23234755733392e-14, -0.642039521920207, 1.47329004279635e-15, 0.642039521920207, -1.62092561595273e-14, -1.39680224666744, -1.90211303259030, -1.00000000000002, -4.88498130835069e-15, -0.221231742082471, -1.17557050458495, -1.26007351067010, 1.96067283990894e-14, 1.26007351067011, 1.17557050458493, 0.221231742082450, 1.69864122767649e-14, 0.999999999999994, 1.90211303259031, 1.39680224666741, -1.54321000422897e-14, -0.642039521920205, 2.20547840361110e-14, 0.642039521920209, -4.39648317751562e-14, -1.39680224666747, -1.90211303259031, -0.999999999999992, 5.77315972805081e-15, -0.221231742082489, -1.17557050458496, -1.26007351067008, 5.39092183879471e-14, 1.26007351067013, 1.17557050458498, 0.221231742082507, -1.63202784619898e-14, 0.999999999999965, 1.90211303259030, 1.39680224666744, 1.43218770176645e-14, -0.642039521920207, 3.71388381953015e-18, 0.642039521920203, 4.31876756579186e-14, -1.39680224666739, -1.90211303259031, -1.00000000000002, -5.55111512312578e-15, -0.221231742082469, -1.17557050458495, -1.26007351067010, 1.71574348007947e-14, 1.26007351067008, 1.17557050458496, 0.221231742082489, -5.77315972805081e-15, 0.999999999999992, 1.90211303259031, 1.39680224666741, -1.34336985979644e-14, -0.642039521920205, 2.05852078771341e-14, 0.642039521920205, 1.54321000422897e-14, -1.39680224666741, -1.90211303259031, -0.999999999999994, 4.99600361081320e-15, -0.221231742082488, -1.17557050458496, -1.26007351067008}; + diff --git a/examples/dsp/FilteringFunction_iirdf2t/biquad.c b/examples/dsp/FilteringFunction_iirdf2t/biquad.c new file mode 100644 index 00000000..88e23e8e --- /dev/null +++ b/examples/dsp/FilteringFunction_iirdf2t/biquad.c @@ -0,0 +1,699 @@ +#include "ref.h" + +void ref_biquad_cascade_df2T_f32(const riscv_biquad_cascade_df2T_instance_f32 *S, + float32_t *pSrc, float32_t *pDst, + uint32_t blockSize) +{ + float32_t *pIn = pSrc; /* source pointer */ + float32_t *pOut = pDst; /* destination pointer */ + float32_t *pState = S->pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* coefficient pointer */ + float32_t acc; /* accumulator */ + float32_t b0, b1, b2, a1, a2; /* Filter coefficients */ + float32_t Xn; /* temporary input */ + float32_t d1, d2; /* state variables */ + uint32_t sample, stage = S->numStages; /* loop counters */ + + do { + /* Reading the coefficients */ + b0 = *pCoeffs++; + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + /*Reading the state values */ + d1 = pState[0]; + d2 = pState[1]; + + sample = blockSize; + + while (sample > 0U) { + /* Read the input */ + Xn = *pIn++; + + /* y[n] = b0 * x[n] + d1 */ + acc = (b0 * Xn) + d1; + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = acc; + + /* Every time after the output is computed state should be updated. + */ + /* d1 = b1 * x[n] + a1 * y[n] + d2 */ + d1 = (b1 * Xn + a1 * acc) + d2; + + /* d2 = b2 * x[n] + a2 * y[n] */ + d2 = (b2 * Xn) + (a2 * acc); + + /* decrement the loop counter */ + sample--; + } + + /* Store the updated state variables back into the state array */ + *pState++ = d1; + *pState++ = d2; + + /* The current stage input is given as the output to the next stage */ + pIn = pDst; + + /*Reset the output working pointer */ + pOut = pDst; + + /* decrement the loop counter */ + stage--; + + } while (stage > 0U); +} + +void ref_biquad_cascade_stereo_df2T_f32( + const riscv_biquad_cascade_stereo_df2T_instance_f32 *S, float32_t *pSrc, + float32_t *pDst, uint32_t blockSize) +{ + float32_t *pIn = pSrc; /* source pointer */ + float32_t *pOut = pDst; /* destination pointer */ + float32_t *pState = S->pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* coefficient pointer */ + float32_t acc1a, acc1b; /* accumulator */ + float32_t b0, b1, b2, a1, a2; /* Filter coefficients */ + float32_t Xn1a, Xn1b; /* temporary input */ + float32_t d1a, d2a, d1b, d2b; /* state variables */ + uint32_t sample, stage = S->numStages; /* loop counters */ + + do { + /* Reading the coefficients */ + b0 = *pCoeffs++; + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + /*Reading the state values */ + d1a = pState[0]; + d2a = pState[1]; + d1b = pState[2]; + d2b = pState[3]; + + sample = blockSize; + + while (sample > 0U) { + /* Read the input */ + Xn1a = *pIn++; // Channel a + Xn1b = *pIn++; // Channel b + + /* y[n] = b0 * x[n] + d1 */ + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = acc1a; + *pOut++ = acc1b; + + /* Every time after the output is computed state should be updated. + */ + /* d1 = b1 * x[n] + a1 * y[n] + d2 */ + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + /* d2 = b2 * x[n] + a2 * y[n] */ + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + + /* decrement the loop counter */ + sample--; + } + + /* Store the updated state variables back into the state array */ + *pState++ = d1a; + *pState++ = d2a; + *pState++ = d1b; + *pState++ = d2b; + + /* The current stage input is given as the output to the next stage */ + pIn = pDst; + + /*Reset the output working pointer */ + pOut = pDst; + + /* decrement the loop counter */ + stage--; + + } while (stage > 0U); +} + +void ref_biquad_cascade_df2T_f64(const riscv_biquad_cascade_df2T_instance_f64 *S, + float64_t *pSrc, float64_t *pDst, + uint32_t blockSize) +{ + float64_t *pIn = pSrc; /* source pointer */ + float64_t *pOut = pDst; /* destination pointer */ + float64_t *pState = S->pState; /* State pointer */ + float64_t *pCoeffs = S->pCoeffs; /* coefficient pointer */ + float64_t acc; /* accumulator */ + float64_t b0, b1, b2, a1, a2; /* Filter coefficients */ + float64_t Xn; /* temporary input */ + float64_t d1, d2; /* state variables */ + uint32_t sample, stage = S->numStages; /* loop counters */ + + do { + /* Reading the coefficients */ + b0 = *pCoeffs++; + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + /*Reading the state values */ + d1 = pState[0]; + d2 = pState[1]; + + sample = blockSize; + + while (sample > 0U) { + /* Read the input */ + Xn = *pIn++; + + /* y[n] = b0 * x[n] + d1 */ + acc = (b0 * Xn) + d1; + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = acc; + + /* Every time after the output is computed state should be updated. + */ + /* d1 = b1 * x[n] + a1 * y[n] + d2 */ + d1 = (b1 * Xn + a1 * acc) + d2; + + /* d2 = b2 * x[n] + a2 * y[n] */ + d2 = (b2 * Xn) + (a2 * acc); + + /* decrement the loop counter */ + sample--; + } + + /* Store the updated state variables back into the state array */ + *pState++ = d1; + *pState++ = d2; + + /* The current stage input is given as the output to the next stage */ + pIn = pDst; + + /*Reset the output working pointer */ + pOut = pDst; + + /* decrement the loop counter */ + stage--; + + } while (stage > 0U); +} + +void ref_biquad_cascade_df1_f32(const riscv_biquad_casd_df1_inst_f32 *S, + float32_t *pSrc, float32_t *pDst, + uint32_t blockSize) +{ + float32_t *pIn = pSrc; /* source pointer */ + float32_t *pOut = pDst; /* destination pointer */ + float32_t *pState = S->pState; /* pState pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* coefficient pointer */ + float32_t acc; /* Simulates the accumulator */ + float32_t b0, b1, b2, a1, a2; /* Filter coefficients */ + float32_t Xn1, Xn2, Yn1, Yn2; /* Filter pState variables */ + float32_t Xn; /* temporary input */ + uint32_t sample, stage = S->numStages; /* loop counters */ + + do { + /* Reading the coefficients */ + b0 = *pCoeffs++; + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + /* Reading the pState values */ + Xn1 = pState[0]; + Xn2 = pState[1]; + Yn1 = pState[2]; + Yn2 = pState[3]; + + /* The variables acc holds the output value that is computed: + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 + * * y[n-2] + */ + + sample = blockSize; + + while (sample > 0U) { + /* Read the input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * + * y[n-2] */ + acc = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn1) + (a2 * Yn2); + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = acc; + + /* Every time after the output is computed state should be updated. + */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + Xn2 = Xn1; + Xn1 = Xn; + Yn2 = Yn1; + Yn1 = acc; + + /* decrement the loop counter */ + sample--; + } + + /* Store the updated state variables back into the pState array */ + *pState++ = Xn1; + *pState++ = Xn2; + *pState++ = Yn1; + *pState++ = Yn2; + + /* The first stage goes from the input buffer to the output buffer. */ + /* Subsequent numStages occur in-place in the output buffer */ + pIn = pDst; + + /* Reset the output pointer */ + pOut = pDst; + + /* decrement the loop counter */ + stage--; + + } while (stage > 0U); +} + +void ref_biquad_cas_df1_32x64_q31(const riscv_biquad_cas_df1_32x64_ins_q31 *S, + q31_t *pSrc, q31_t *pDst, uint32_t blockSize) +{ + q31_t *pIn = pSrc; /* input pointer initialization */ + q31_t *pOut = pDst; /* output pointer initialization */ + q63_t *pState = + S->pState; /* state pointer initialization */ + const q31_t *pCoeffs = + S->pCoeffs; /* coeff pointer initialization */ + q63_t acc; /* accumulator */ + q31_t Xn1, Xn2; /* Input Filter state variables */ + q63_t Yn1, Yn2; /* Output Filter state variables */ + q31_t b0, b1, b2, a1, a2; /* Filter coefficients */ + q31_t Xn; /* temporary input */ + int32_t shift = (int32_t)S->postShift + + 1; /* Shift to be applied to the output */ + uint32_t sample, stage = S->numStages; /* loop counters */ + q31_t acc_l, acc_h; /* temporary output */ + uint32_t uShift = ((uint32_t)S->postShift + 1U); + uint32_t lShift = 32U - uShift; /* Shift to be applied to the output + */ + + do { + /* Reading the coefficients */ + b0 = *pCoeffs++; + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + /* Reading the state values */ + Xn1 = pState[0]; + Xn2 = pState[1]; + Yn1 = pState[2]; + Yn2 = pState[3]; + + sample = blockSize; + + while (sample > 0U) { + /* Read the input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * + * y[n-2] */ + acc = (q63_t)Xn * b0 + (q63_t)Xn1 * b1 + (q63_t)Xn2 * b2; + /* acc += a1 * y[n-1] */ + acc += mult32x64(Yn1, a1); + /* acc += a2 * y[n-2] */ + acc += mult32x64(Yn2, a2); + + /* Every time after the output is computed state should be updated. + */ + Xn2 = Xn1; + Xn1 = Xn; + Yn2 = Yn1; + + /* The result is converted to 1.63, Yn1 variable is reused */ + Yn1 = acc << shift; + + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + /* Apply shift for lower part of acc and upper part of acc */ + acc_h = (uint32_t)acc_l >> lShift | acc_h << uShift; + + /* Store the output in the destination buffer in 1.31 format. */ + *pOut++ = acc_h; + + /* decrement the loop counter */ + sample--; + } + + /* The first stage output is given as input to the second stage. */ + pIn = pDst; + + /* Reset to destination buffer working pointer */ + pOut = pDst; + + /* Store the updated state variables back into the pState array */ + *pState++ = (q63_t)Xn1; + *pState++ = (q63_t)Xn2; + *pState++ = Yn1; + *pState++ = Yn2; + + } while (--stage); +} + +void ref_biquad_cascade_df1_q31(const riscv_biquad_casd_df1_inst_q31 *S, + q31_t *pSrc, q31_t *pDst, uint32_t blockSize) +{ + q63_t acc; /* accumulator */ + uint32_t uShift = ((uint32_t)S->postShift + 1U); + uint32_t lShift = 32U - uShift; /* Shift to be applied to the output */ + q31_t *pIn = pSrc; /* input pointer initialization */ + q31_t *pOut = pDst; /* output pointer initialization */ + q31_t *pState = S->pState; /* pState pointer initialization */ + const q31_t *pCoeffs = S->pCoeffs; /* coeff pointer initialization */ + q31_t Xn1, Xn2, Yn1, Yn2; /* Filter state variables */ + q31_t b0, b1, b2, a1, a2; /* Filter coefficients */ + q31_t Xn; /* temporary input */ + uint32_t sample, stage = S->numStages; /* loop counters */ + + do { + /* Reading the coefficients */ + b0 = *pCoeffs++; + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + /* Reading the state values */ + Xn1 = pState[0]; + Xn2 = pState[1]; + Yn1 = pState[2]; + Yn2 = pState[3]; + + /* The variables acc holds the output value that is computed: + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * + * y[n-2] + */ + + sample = blockSize; + + while (sample > 0U) { + /* Read the input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * + * y[n-2] */ + /* acc = b0 * x[n] */ + acc = (q63_t)b0 * Xn; + + /* acc += b1 * x[n-1] */ + acc += (q63_t)b1 * Xn1; + /* acc += b[2] * x[n-2] */ + acc += (q63_t)b2 * Xn2; + /* acc += a1 * y[n-1] */ + acc += (q63_t)a1 * Yn1; + /* acc += a2 * y[n-2] */ + acc += (q63_t)a2 * Yn2; + + /* The result is converted to 1.31 */ + acc = acc >> lShift; + + /* Every time after the output is computed state should be updated. + */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + Xn2 = Xn1; + Xn1 = Xn; + Yn2 = Yn1; + Yn1 = (q31_t)acc; + + /* Store the output in the destination buffer. */ + *pOut++ = (q31_t)acc; + + /* decrement the loop counter */ + sample--; + } + + /* The first stage goes from the input buffer to the output buffer. */ + /* Subsequent stages occur in-place in the output buffer */ + pIn = pDst; + + /* Reset to destination pointer */ + pOut = pDst; + + /* Store the updated state variables back into the pState array */ + *pState++ = Xn1; + *pState++ = Xn2; + *pState++ = Yn1; + *pState++ = Yn2; + + } while (--stage); +} + +void ref_biquad_cascade_df1_fast_q31(const riscv_biquad_casd_df1_inst_q31 *S, + q31_t *pSrc, q31_t *pDst, + uint32_t blockSize) +{ + q31_t acc = 0; /* accumulator */ + q31_t Xn1, Xn2, Yn1, Yn2; /* Filter state variables */ + q31_t b0, b1, b2, a1, a2; /* Filter coefficients */ + q31_t *pIn = pSrc; /* input pointer initialization */ + q31_t *pOut = pDst; /* output pointer initialization */ + q31_t *pState = S->pState; /* pState pointer initialization */ + const q31_t *pCoeffs = S->pCoeffs; /* coeff pointer initialization */ + q31_t Xn; /* temporary input */ + int32_t shift = + (int32_t)S->postShift + 1; /* Shift to be applied to the output */ + uint32_t sample, stage = S->numStages; /* loop counters */ + + do { + /* Reading the coefficients */ + b0 = *pCoeffs++; + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + /* Reading the state values */ + Xn1 = pState[0]; + Xn2 = pState[1]; + Yn1 = pState[2]; + Yn2 = pState[3]; + + sample = blockSize; + + while (sample > 0U) { + /* Read the input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * + * y[n-2] */ + mult_32x32_keep32_R(acc, b0, Xn); + multAcc_32x32_keep32_R(acc, b1, Xn1); + multAcc_32x32_keep32_R(acc, b2, Xn2); + multAcc_32x32_keep32_R(acc, a1, Yn1); + multAcc_32x32_keep32_R(acc, a2, Yn2); + + /* The result is converted to 1.31 */ + acc <<= shift; + + /* Every time after the output is computed state should be updated. + */ + Xn2 = Xn1; + Xn1 = Xn; + Yn2 = Yn1; + Yn1 = acc; + + /* Store the output in the destination buffer. */ + *pOut++ = acc; + + /* decrement the loop counter */ + sample--; + } + + /* The first stage goes from the input buffer to the output buffer. */ + /* Subsequent stages occur in-place in the output buffer */ + pIn = pDst; + + /* Reset to destination pointer */ + pOut = pDst; + + /* Store the updated state variables back into the pState array */ + *pState++ = Xn1; + *pState++ = Xn2; + *pState++ = Yn1; + *pState++ = Yn2; + + } while (--stage); +} + +void ref_biquad_cascade_df1_fast_q15(const riscv_biquad_casd_df1_inst_q15 *S, + q15_t *pSrc, q15_t *pDst, + uint32_t blockSize) +{ + q15_t *pIn = pSrc; /* Source pointer */ + q15_t *pOut = pDst; /* Destination pointer */ + q15_t b0, b1, b2, a1, + a2; /* Filter coefficients */ + q15_t Xn1, Xn2, Yn1, + Yn2; /* Filter state variables */ + q15_t Xn; /* temporary input */ + q31_t acc; /* Accumulator */ + int32_t shift = (15 - (int32_t)S->postShift); /* Post shift */ + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + uint32_t sample, stage = (uint32_t)S->numStages; /* Stage loop counter */ + + do { + /* Reading the coefficients */ + b0 = *pCoeffs++; + pCoeffs++; // skip the 0 coefficient + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + /* Reading the state values */ + Xn1 = pState[0]; + Xn2 = pState[1]; + Yn1 = pState[2]; + Yn2 = pState[3]; + + sample = blockSize; + + while (sample > 0U) { + /* Read the input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * + * y[n-2] */ + acc = (q31_t)b0 * Xn + (q31_t)b1 * Xn1 + (q31_t)b2 * Xn2 + + (q31_t)a1 * Yn1 + (q31_t)a2 * Yn2; + + /* The result is converted to 1.15 */ + acc = ref_sat_q15(acc >> shift); + + /* Every time after the output is computed state should be updated. + */ + Xn2 = Xn1; + Xn1 = Xn; + Yn2 = Yn1; + Yn1 = (q15_t)acc; + + /* Store the output in the destination buffer. */ + *pOut++ = (q15_t)acc; + + /* decrement the loop counter */ + sample--; + } + + /* The first stage goes from the input buffer to the output buffer. */ + /* Subsequent stages occur in-place in the output buffer */ + pIn = pDst; + + /* Reset to destination pointer */ + pOut = pDst; + + /* Store the updated state variables back into the pState array */ + *pState++ = Xn1; + *pState++ = Xn2; + *pState++ = Yn1; + *pState++ = Yn2; + + } while (--stage); +} + +void ref_biquad_cascade_df1_q15(const riscv_biquad_casd_df1_inst_q15 *S, + q15_t *pSrc, q15_t *pDst, uint32_t blockSize) +{ + q15_t *pIn = pSrc; /* Source pointer */ + q15_t *pOut = pDst; /* Destination pointer */ + q15_t b0, b1, b2, a1, + a2; /* Filter coefficients */ + q15_t Xn1, Xn2, Yn1, + Yn2; /* Filter state variables */ + q15_t Xn; /* temporary input */ + q63_t acc; /* Accumulator */ + int32_t shift = (15 - (int32_t)S->postShift); /* Post shift */ + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + uint32_t sample, stage = (uint32_t)S->numStages; /* Stage loop counter */ + + do { + /* Reading the coefficients */ + b0 = *pCoeffs++; + pCoeffs++; // skip the 0 coefficient + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + /* Reading the state values */ + Xn1 = pState[0]; + Xn2 = pState[1]; + Yn1 = pState[2]; + Yn2 = pState[3]; + + sample = blockSize; + + while (sample > 0U) { + /* Read the input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * + * y[n-2] */ + acc = (q31_t)b0 * Xn + (q31_t)b1 * Xn1 + (q31_t)b2 * Xn2 + + (q31_t)a1 * Yn1 + (q31_t)a2 * Yn2; + + /* The result is converted to 1.15 */ + acc = ref_sat_q15(acc >> shift); + + /* Every time after the output is computed state should be updated. + */ + Xn2 = Xn1; + Xn1 = Xn; + Yn2 = Yn1; + Yn1 = (q15_t)acc; + + /* Store the output in the destination buffer. */ + *pOut++ = (q15_t)acc; + + /* decrement the loop counter */ + sample--; + } + + /* The first stage goes from the input buffer to the output buffer. */ + /* Subsequent stages occur in-place in the output buffer */ + pIn = pDst; + + /* Reset to destination pointer */ + pOut = pDst; + + /* Store the updated state variables back into the pState array */ + *pState++ = Xn1; + *pState++ = Xn2; + *pState++ = Yn1; + *pState++ = Yn2; + + } while (--stage); +} diff --git a/examples/dsp/FilteringFunction_iirdf2t/main.c b/examples/dsp/FilteringFunction_iirdf2t/main.c new file mode 100644 index 00000000..18bb7c98 --- /dev/null +++ b/examples/dsp/FilteringFunction_iirdf2t/main.c @@ -0,0 +1,159 @@ +// +// Created by lujun on 19-6-28. +// +// This contains fir, iir and lms filters +// each one has it's own function. +// All function can be found in main function. +// If you don't want to use it, then comment it. +// +// This part only tests result after 50 dots.If you want to test results' all +// dots, please define WITH_FRONT +// +// If there are too much numbers which makes it hard to read,in VScode you can +// press alt and z can shrimp them to one line +// +// You MUST be careful about overflow. +#include "riscv_math.h" +#include "array.h" +#include +#include "../common.h" + +#include "../HelperFunctions/math_helper.c" +#include "../HelperFunctions/ref_helper.c" + +#include +#define DELTAF32 (0.05f) +#define DELTAQ31 (63) +#define DELTAQ15 (1) +#define DELTAQ7 (1) +#define SNR_THRESHOLD_F32 (80.0f) + +int test_flag_error = 0; + +// #define WITH_FRONT + +/* clang-format on */ +//*************************************************************************************** +// iir df2t +//*************************************************************************************** +static void riscv_iir_df2t_f32_lp(void) +{ + uint32_t i; + /* clang-format off */ + riscv_biquad_cascade_df2T_instance_f32 S; + /* clang-format on */ + float32_t ScaleValue; + riscv_biquad_cascade_df2T_init_f32(&S, numStages, IIRCoeffs32LP, &IIRStateF32[0]); + BENCH_START(riscv_biquad_cascade_df2T_f32); + riscv_biquad_cascade_df2T_f32(&S, testInput_f32_50Hz_200Hz, testOutput_f32, TEST_LENGTH_SAMPLES); + BENCH_END(riscv_biquad_cascade_df2T_f32); + riscv_biquad_cascade_df2T_init_f32(&S, numStages, IIRCoeffs32LP, &IIRStateF32[0]); + ref_biquad_cascade_df2T_f32(&S, testInput_f32_50Hz_200Hz, testOutput_f32_ref, TEST_LENGTH_SAMPLES); + // ScaleValue = 0.052219514664161221f * 0.04279801741658381f; +#ifndef WITH_FRONT + float snr = riscv_snr_f32(&testOutput_f32_ref[50], &testOutput_f32[50], 269); + + if (snr < SNR_THRESHOLD_F32) { + BENCH_ERROR(riscv_biquad_cascade_df2T_f32); + printf("f32 biquad_cascade_df2T failed with snr:%f\n", snr); + test_flag_error = 1; + } + BENCH_STATUS(riscv_biquad_cascade_df2T_f32); +#else + float snr = + riscv_snr_f32(&testOutput_f32_ref[0], &testOutput_f32[0], TEST_LENGTH_SAMPLES); + + if (snr < SNR_THRESHOLD_F32) { + BENCH_ERROR(riscv_biquad_cascade_df2T_f32); + printf("f32 biquad_cascade_df2T failed with snr:%f\n", snr); + test_flag_error = 1; + } + BENCH_STATUS(riscv_biquad_cascade_df2T_f32); +#endif +} +static void riscv_iir_stereo_df2t_f32_lp(void) +{ + uint32_t i; + /* clang-format off */ + riscv_biquad_cascade_stereo_df2T_instance_f32 S; + /* clang-format on */ + // float32_t ScaleValue; + riscv_biquad_cascade_stereo_df2T_init_f32(&S, numStages, IIRCoeffs32LP, IIRStateF32); + BENCH_START(riscv_biquad_cascade_stereo_df2T_f32); + riscv_biquad_cascade_stereo_df2T_f32(&S, testInput_f32_50Hz_200Hz, testOutput_f32, TEST_LENGTH_SAMPLES); + BENCH_END(riscv_biquad_cascade_stereo_df2T_f32); + riscv_biquad_cascade_stereo_df2T_init_f32(&S, numStages, IIRCoeffs32LP, IIRStateF32); + ref_biquad_cascade_stereo_df2T_f32(&S, testInput_f32_50Hz_200Hz, testOutput_f32_ref, TEST_LENGTH_SAMPLES); + // ScaleValue = 0.052219514664161221f * 0.04279801741658381f; +#ifndef WITH_FRONT + float snr = riscv_snr_f32(&testOutput_f32_ref[50], &testOutput_f32[50], 269); + + if (snr < SNR_THRESHOLD_F32) { + BENCH_ERROR(riscv_biquad_cascade_stereo_df2T_f32); + printf("f32 biquad_cascade_stereo_df2T failed with snr:%f\n", snr); + test_flag_error = 1; + } + BENCH_STATUS(riscv_biquad_cascade_stereo_df2T_f32); +#else + float snr = + riscv_snr_f32(&testOutput_f32_ref[0], &testOutput_f32[0], TEST_LENGTH_SAMPLES); + + if (snr < SNR_THRESHOLD_F32) { + BENCH_ERROR(riscv_biquad_cascade_stereo_df2T_f32); + printf("f32 biquad_cascade_stereo_df2T failed with snr:%f\n", snr); + test_flag_error = 1; + } + BENCH_STATUS(riscv_biquad_cascade_stereo_df2T_f32); +#endif +} +static void riscv_iir_df2t_f64_lp(void) +{ + uint32_t i; + /* clang-format off */ + riscv_biquad_cascade_df2T_instance_f64 S; + /* clang-format on */ + // float32_t ScaleValue; + riscv_biquad_cascade_df2T_init_f64(&S, numStages, IIRCoeffs64LP, &IIRStateF64[0]); + BENCH_START(riscv_biquad_cascade_df2T_f64); + riscv_biquad_cascade_df2T_f64(&S, testInput_f64_50Hz_200Hz, testOutput_f64, TEST_LENGTH_SAMPLES); + BENCH_END(riscv_biquad_cascade_df2T_f64); + riscv_biquad_cascade_df2T_init_f64(&S, numStages, IIRCoeffs32LP, &IIRStateF64[0]); + ref_biquad_cascade_df2T_f64(&S, testInput_f64_50Hz_200Hz, testOutput_f64_ref, TEST_LENGTH_SAMPLES); + // ScaleValue = 0.052219514664161221f * 0.04279801741658381f; +#ifndef WITH_FRONT + float snr = riscv_snr_f32((float32_t *)&testOutput_f64_ref[50], (float32_t *)&testOutput_f64[50], 269); + + if (snr < SNR_THRESHOLD_F32) { + BENCH_ERROR(riscv_biquad_cascade_df2T_f64); + printf("f32 biquad_cascade_df2T failed with snr:%f\n", snr); + test_flag_error = 1; + } + BENCH_STATUS(riscv_biquad_cascade_df2T_f64); +#else + float snr = + riscv_snr_f32(&testOutput_ref[0], &testOutput[0], TEST_LENGTH_SAMPLES); + + if (snr < SNR_THRESHOLD_F32) { + BENCH_ERROR(riscv_biquad_cascade_df2T_f64); + printf("f32 biquad_cascade_df2T failed with snr:%f\n", snr); + test_flag_error = 1; + } + BENCH_STATUS(riscv_biquad_cascade_df2T_f64); +#endif +} + +int main() +{ + BENCH_INIT; + riscv_iir_df2t_f32_lp(); + riscv_iir_stereo_df2t_f32_lp(); + riscv_iir_df2t_f64_lp(); + BENCH_FINISH; + if (test_flag_error) { + printf("test error apprears, please recheck.\n"); + return 1; + } else { + printf("all test are passed. Well done!\n"); + } + return 0; +} diff --git a/examples/dsp/FilteringFunction_levinsonDurbin/CMakeLists.txt b/examples/dsp/FilteringFunction_levinsonDurbin/CMakeLists.txt new file mode 100644 index 00000000..be5bfa95 --- /dev/null +++ b/examples/dsp/FilteringFunction_levinsonDurbin/CMakeLists.txt @@ -0,0 +1,5 @@ +set(TARGET_REQUIRED_PRIVATE_INCLUDE ${CMAKE_CURRENT_SOURCE_DIR} ${CMAKE_CURRENT_SOURCE_DIR}/..) +set(TARGET_REQUIRED_SRCS levinson_durbin.c) +set(TARGET_REQUIRED_LIBS nmsis) +set(mains main.c) +generate_bin() \ No newline at end of file diff --git a/examples/dsp/FilteringFunction_levinsonDurbin/array.h b/examples/dsp/FilteringFunction_levinsonDurbin/array.h new file mode 100644 index 00000000..cc73c19e --- /dev/null +++ b/examples/dsp/FilteringFunction_levinsonDurbin/array.h @@ -0,0 +1,24 @@ +// Array for FilteringFunctions iirLatticePart +#define TEST_LENGTH_SAMPLES 320 /* 采样点数 */ +#define numStages 8 /* 2阶IIR滤波的个数 */ +// float32_t +// stereo requires 2*TEST_LENGTH_SAMPLES + float32_t testOutput_f32[TEST_LENGTH_SAMPLES],testOutput_f32_ref[TEST_LENGTH_SAMPLES]; + float32_t IIRStateF32[TEST_LENGTH_SAMPLES+numStages]={0}; + float32_t IIRCoeffs32LP_K[numStages] = {-0.9490513802f, 0.960866034f, -0.950527668f, 0.9305356741f, -0.8808346987f, 0.7298035026f, -0.3796664774f, 0.07335939258f}; + float32_t IIRCoeffs32LP_V[numStages+1] = {0.0004670530325f, 0.002966811415f, 0.006142409053f, 0.006682873704f, 0.004372655414f, 0.00177692459f, 0.0004465713282f, 6.86832791e-05f, 5.115610293e-06f}; + float32_t testInput_f32_50Hz_200Hz[TEST_LENGTH_SAMPLES] = {0, 1.26007351067010, 1.17557050458495, 0.221231742082474, -1.11022302462516e-16, 1.00000000000000, 1.90211303259031, 1.39680224666742, 4.44089209850063e-16, -0.642039521920206, -3.67394039744206e-16, 0.642039521920206, -1.22124532708767e-15, -1.39680224666742, -1.90211303259031, -1.00000000000000, -3.33066907387547e-16, -0.221231742082476, -1.17557050458495, -1.26007351067010, -1.22464679914735e-15, 1.26007351067010, 1.17557050458495, 0.221231742082475, 8.88178419700125e-16, 1.00000000000000, 1.90211303259031, 1.39680224666742, 1.33226762955019e-15, -0.642039521920206, -1.10218211923262e-15, 0.642039521920206, 1.55431223447522e-15, -1.39680224666743, -1.90211303259031, -0.999999999999995, -7.77156117237610e-16, -0.221231742082473, -1.17557050458495, -1.26007351067010, -2.44929359829471e-15, 1.26007351067010, 1.17557050458494, 0.221231742082476, -7.77156117237610e-16, 0.999999999999998, 1.90211303259031, 1.39680224666742, -4.88498130835069e-15, -0.642039521920206, 3.49210031947972e-15, 0.642039521920206, 2.55351295663786e-15, -1.39680224666742, -1.90211303259031, -0.999999999999996, -9.99200722162641e-16, -0.221231742082477, -1.17557050458494, -1.26007351067011, -3.67394039744206e-15, 1.26007351067010, 1.17557050458495, 0.221231742082472, -1.22124532708767e-15, 1.00000000000000, 1.90211303259031, 1.39680224666742, -1.09912079437891e-14, -0.642039521920206, 8.08638275819206e-15, 0.642039521920205, 3.55271367880050e-15, -1.39680224666741, -1.90211303259031, -0.999999999999997, -1.44328993201270e-15, -0.221231742082476, -1.17557050458494, -1.26007351067010, -4.89858719658941e-15, 1.26007351067010, 1.17557050458494, 0.221231742082472, 3.88578058618805e-15, 1.00000000000000, 1.90211303259031, 1.39680224666743, 4.44089209850063e-15, -0.642039521920207, -3.30654635769785e-15, 0.642039521920206, 4.55191440096314e-15, -1.39680224666742, -1.90211303259031, -0.999999999999998, 3.66373598126302e-15, -0.221231742082476, -1.17557050458495, -1.26007351067010, 1.16403343982657e-14, 1.26007351067010, 1.17557050458496, 0.221231742082482, -1.99840144432528e-15, 1.00000000000000, 1.90211303259031, 1.39680224666743, 5.44009282066327e-15, -0.642039521920206, 6.61680659921524e-15, 0.642039521920207, 5.55111512312578e-15, -1.39680224666742, -1.90211303259031, -0.999999999999984, -2.10942374678780e-15, -0.221231742082475, -1.17557050458493, -1.26007351067011, -7.34788079488412e-15, 1.26007351067010, 1.17557050458494, 0.221231742082483, -2.33146835171283e-15, 1.00000000000000, 1.90211303259031, 1.39680224666741, 6.32827124036339e-15, -0.642039521920206, 5.88201851972683e-15, 0.642039521920207, -2.22044604925031e-14, -1.39680224666742, -1.90211303259031, -0.999999999999985, 8.43769498715119e-15, -0.221231742082475, -1.17557050458495, -1.26007351067009, 2.69546091939735e-14, 1.26007351067009, 1.17557050458496, 0.221231742082484, -2.77555756156289e-15, 1, 1.90211303259030, 1.39680224666743, 7.32747196252603e-15, -0.642039521920206, 5.14723044023841e-15, 0.642039521920205, 7.54951656745106e-15, -1.39680224666742, -1.90211303259031, -0.999999999999986, -2.99760216648792e-15, -0.221231742082474, -1.17557050458495, -1.26007351067009, -9.79717439317883e-15, 1.26007351067010, 1.17557050458494, 0.221231742082465, 7.88258347483861e-15, 0.999999999999999, 1.90211303259031, 1.39680224666741, -2.04281036531029e-14, -0.642039521920204, 4.41244236075000e-15, 0.642039521920207, 8.43769498715119e-15, -1.39680224666742, -1.90211303259031, -1.00000000000002, -3.33066907387547e-15, -0.221231742082473, -1.17557050458493, -1.26007351067011, -1.10218211923262e-14, 1.26007351067010, 1.17557050458494, 0.221231742082485, -3.44169137633799e-15, 0.999999999999998, 1.90211303259031, 1.39680224666741, 9.32587340685132e-15, -0.642039521920206, 3.67765428126159e-15, 0.642039521920207, -1.93178806284777e-14, -1.39680224666742, -1.90211303259031, -0.999999999999988, 7.32747196252603e-15, -0.221231742082492, -1.17557050458495, -1.26007351067009, 2.32806687965315e-14, 1.26007351067012, 1.17557050458494, 0.221231742082467, -1.47659662275146e-14, 0.999999999999969, 1.90211303259030, 1.39680224666744, 1.02140518265514e-14, -0.642039521920206, 2.94286620177318e-15, 0.642039521920207, -1.83186799063151e-14, -1.39680224666739, -1.90211303259031, -1.00000000000002, -4.10782519111308e-15, -0.221231742082472, -1.17557050458495, -1.26007351067010, 2.20560219973841e-14, 1.26007351067011, 1.17557050458493, 0.221231742082486, -4.21884749357560e-15, 0.999999999999996, 1.90211303259031, 1.39680224666741, -1.75415237890775e-14, -0.642039521920204, 2.35243601950878e-14, 0.642039521920209, 1.15463194561016e-14, -1.39680224666742, -1.90211303259031, -0.999999999999990, -1.54321000422897e-14, -0.221231742082452, -1.17557050458493, -1.26007351067011, -1.46957615897682e-14, 1.26007351067010, 1.17557050458495, 0.221231742082468, 6.32827124036339e-15, 1.00000000000002, 1.90211303259030, 1.39680224666744, 1.23234755733392e-14, -0.642039521920207, 1.47329004279635e-15, 0.642039521920207, -1.62092561595273e-14, -1.39680224666744, -1.90211303259030, -1.00000000000002, -4.88498130835069e-15, -0.221231742082471, -1.17557050458495, -1.26007351067010, 1.96067283990894e-14, 1.26007351067011, 1.17557050458493, 0.221231742082450, 1.69864122767649e-14, 0.999999999999994, 1.90211303259031, 1.39680224666741, -1.54321000422897e-14, -0.642039521920205, 2.20547840361110e-14, 0.642039521920209, -4.39648317751562e-14, -1.39680224666747, -1.90211303259031, -0.999999999999992, 5.77315972805081e-15, -0.221231742082489, -1.17557050458496, -1.26007351067008, 5.39092183879471e-14, 1.26007351067013, 1.17557050458498, 0.221231742082507, -1.63202784619898e-14, 0.999999999999965, 1.90211303259030, 1.39680224666744, 1.43218770176645e-14, -0.642039521920207, 3.71388381953015e-18, 0.642039521920203, 4.31876756579186e-14, -1.39680224666739, -1.90211303259031, -1.00000000000002, -5.55111512312578e-15, -0.221231742082469, -1.17557050458495, -1.26007351067010, 1.71574348007947e-14, 1.26007351067008, 1.17557050458496, 0.221231742082489, -5.77315972805081e-15, 0.999999999999992, 1.90211303259031, 1.39680224666741, -1.34336985979644e-14, -0.642039521920205, 2.05852078771341e-14, 0.642039521920205, 1.54321000422897e-14, -1.39680224666741, -1.90211303259031, -0.999999999999994, 4.99600361081320e-15, -0.221231742082488, -1.17557050458496, -1.26007351067008}; + +// q31_t + q31_t testOutput_q31[TEST_LENGTH_SAMPLES],testOutput_q31_ref[TEST_LENGTH_SAMPLES]; + q31_t IIRStateQ31[TEST_LENGTH_SAMPLES+numStages]={0}; + q31_t IIRCoeffs32LP_K_q31[numStages]; + q31_t IIRCoeffs32LP_V_q31[numStages+1]; + q31_t testInput_q31_50Hz_200Hz[TEST_LENGTH_SAMPLES]; + +// q15_t + q15_t testOutput_q15[TEST_LENGTH_SAMPLES],testOutput_q15_ref[TEST_LENGTH_SAMPLES]; + q15_t IIRStateQ15[TEST_LENGTH_SAMPLES+numStages]={0}; + q15_t IIRCoeffs32LP_K_q15[numStages]; + q15_t IIRCoeffs32LP_V_q15[numStages+1]; + q15_t testInput_q15_50Hz_200Hz[TEST_LENGTH_SAMPLES]; \ No newline at end of file diff --git a/examples/dsp/FilteringFunction_levinsonDurbin/levinson_durbin.c b/examples/dsp/FilteringFunction_levinsonDurbin/levinson_durbin.c new file mode 100644 index 00000000..d3f0f8b2 --- /dev/null +++ b/examples/dsp/FilteringFunction_levinsonDurbin/levinson_durbin.c @@ -0,0 +1,190 @@ +#include "ref.h" + +void ref_levinson_durbin_f32(const float32_t *phi, + float32_t *a, + float32_t *err, + int nbCoefs) +{ + float32_t e; + + a[0] = phi[1] / phi[0]; + + e = phi[0] - phi[1] * a[0]; + for(int p=1; p < nbCoefs; p++) + { + float32_t suma=0.0f; + float32_t sumb=0.0f; + float32_t k; + int nb,j; + + for(int i=0; i < p; i++) + { + suma += a[i] * phi[p - i]; + sumb += a[i] * phi[i + 1]; + } + + k = (phi[p+1]-suma)/(phi[0] - sumb); + + + nb = p >> 1; + j=0; + for(int i =0; i < nb ; i++) + { + float32_t x,y; + + x=a[j] - k * a[p-1-j]; + y=a[p-1-j] - k * a[j]; + + a[j] = x; + a[p-1-j] = y; + + j++; + } + + nb = p & 1; + if (nb) + { + a[j]=a[j]- k * a[p-1-j]; + } + + a[p] = k; + e = e * (1.0f - k*k); + + + } + *err = e; +} + +#include "dsp/filtering_functions.h" + +#define ONE_Q31 0x7FFFFFFFL +#define TWO_Q30 0x7FFFFFFFL + +#define HALF_Q31 0x00008000L +#define ONE_Q15 0x7FFF +#define HALF_Q15 0x3FFF +#define LOWPART_MASK 0x07FFF + +__STATIC_FORCEINLINE q31_t mul32x16(q31_t a, q15_t b) +{ + q31_t r = ((q63_t)a * (q63_t)b) >> 15; + + return(r); + +} + +__STATIC_FORCEINLINE q31_t mul32x32(q31_t a, q31_t b) +{ + //q31_t r = __SSAT(((q63_t)a * b) >> 31,31); + q31_t r = ((q63_t)a * b) >> 31; + + return(r); + +} + +__STATIC_FORCEINLINE q31_t divide(q31_t n, q31_t d) +{ + riscv_status status; + int16_t shift; + q15_t inverse; + q31_t r; + // We are computing: + // n / d = n / (h + l) where h and l are the high end and low end part. + // 1 / (h + l) = 1 / h (1 - l / h) + // Our division algorithm has a shift. So it is returning a scaled value sh. + // So we need a << shift to convert 1/ sh to 1/h. + // In below code, we are organizing the computation differently. Instead of computing: + // 1 / h (1 - l / h) + // we are computing + // 1 / h (2 - (l + h) / h) + // 1 / h (2 - d / h) + // Also, we are not computing 1/h in Q15 but in Q14. + // 2 is expressed in Q30. + // So at the end of all computation we need a << 2 + + // Result is in Q14 because of use of HALF_Q15 instead of ONE_Q15. + status=riscv_divide_q15(HALF_Q15,d>>16,&inverse,&shift); + (void)status; + + // d is used instead of l + // So we will need to substract to 2 instead of 1. + r = mul32x16(d,inverse); + r = TWO_Q30 - (r << shift); + r = mul32x16(r, inverse); + r = mul32x32(r,n) ; + r = r << (shift + 2); + + return(r); + +} + +void ref_levinson_durbin_q31(const q31_t *phi, + q31_t *a, + q31_t *err, + int nbCoefs) +{ + q31_t e; + + //a[0] = phi[1] / phi[0]; + a[0] = divide(phi[1], phi[0]); + + + //e = phi[0] - phi[1] * a[0]; + e = phi[0] - mul32x32(phi[1],a[0]); + + for(int p=1; p < nbCoefs; p++) + { + q63_t suma=0; + q63_t sumb=0; + q31_t k; + int nb,j; + + for(int i=0; i < p; i++) + { + suma += ((q63_t)a[i] * phi[p - i]); + sumb += ((q63_t)a[i] * phi[i + 1]); + } + + suma = suma >> 31; + sumb = sumb >> 31; + + + + //k = (phi[p+1]-suma)/(phi[0] - sumb); + k = divide(phi[p+1]-(q31_t)suma,phi[0] - (q31_t)sumb); + + + nb = p >> 1; + j=0; + for(int i =0;i < nb ; i++) + { + q31_t x,y; + + //x = a[j] - k * a[p-1-j]; + x = a[j] - mul32x32(k,a[p-1-j]); + + //y = a[p-1-j] - k * a[j]; + y = a[p-1-j] - mul32x32(k , a[j]); + + a[j] = x; + a[p-1-j] = y; + + j++; + } + + nb = p & 1; + if (nb) + { + //a[j] = a[j]- k * a[p-1-j]; + a[j] = a[j] - mul32x32(k,a[p-1-j]); + } + + a[p] = k; + + // e = e * (1 - k*k); + e = mul32x32(e,ONE_Q31 - mul32x32(k,k)); + + + } + *err = e; +} diff --git a/examples/dsp/FilteringFunction_levinsonDurbin/main.c b/examples/dsp/FilteringFunction_levinsonDurbin/main.c new file mode 100644 index 00000000..e8b7997a --- /dev/null +++ b/examples/dsp/FilteringFunction_levinsonDurbin/main.c @@ -0,0 +1,103 @@ +// +// Created by lujun on 19-6-28. +// +// This contains IIR, iir and lms filters +// each one has it's own function. +// All function can be found in main function. +// If you don't want to use it, then comment it. +// +// This part only tests result after 50 dots.If you want to test results' all +// dots, please define WITH_FRONT +// +// If there are too much numbers which makes it hard to read,in VScode you can +// press alt and z can shrimp them to one line +// +// You MUST be careful about overflow. +#include "riscv_math.h" +#include "array.h" +#include +#include "../common.h" + +#include "../HelperFunctions/math_helper.c" +#include "../HelperFunctions/ref_helper.c" + +#include +#define DELTAF32 (0.05f) +#define DELTAQ31 (63) +#define DELTAQ15 (1) +#define DELTAQ7 (1) +#define SNR_THRESHOLD_F32 (80.0f) + +int test_flag_error = 0; + +//*************************************************************************************** +// iir Lattice Filters +//*************************************************************************************** +static void DSP_levinson_durbin_f32(void) +{ + int nbCoefs = 180; + float32_t phi[256]; + float32_t a[256], a_ref[256]; + float32_t err, err_ref; + for(int i=0;i<256;i++) + phi[i] = (float32_t) rand(); + BENCH_START(riscv_levinson_durbin_f32); + riscv_levinson_durbin_f32(&phi, &a, &err, nbCoefs); + BENCH_END(riscv_levinson_durbin_f32); + ref_levinson_durbin_f32(&phi, &a_ref, &err_ref, nbCoefs); + // ScaleValue = 0.052219514664161221f * 0.04279801741658381f; + for(int i=0;i 0) { + posMax = (posMax - 1); + + if (num > posMax) { + num = posMax; + } + } else { + negMin = -posMax; + + if (num < negMin) { + num = negMin; + } + } + return (num); +} + +q31_t ref_sat_q31(q63_t num) +{ + if (num > (q63_t)INT_MAX) { + return INT_MAX; + } else if (num < (q63_t)0xffffffff80000000ll) { + return INT_MIN; + } else { + return (q31_t)num; + } +} + +q15_t ref_sat_q15(q31_t num) +{ + if (num > (q31_t)SHRT_MAX) { + return SHRT_MAX; + } else if (num < (q31_t)0xffff8000) { + return SHRT_MIN; + } else { + return (q15_t)num; + } +} + +q7_t ref_sat_q7(q15_t num) +{ + if (num > (q15_t)SCHAR_MAX) { + return SCHAR_MAX; + } else if (num < (q15_t)0xff80) { + return SCHAR_MIN; + } else { + return (q7_t)num; + } +} + +float32_t ref_pow(float32_t a, uint32_t b) +{ + uint32_t i; + float32_t r = a; + + for (i = 1; i < b; i++) { + r *= a; + } + + if (b == 0) { + return 1; + } + + return r; +} diff --git a/examples/dsp/InterpolationFunctions_Bilinearpart/CMakeLists.txt b/examples/dsp/InterpolationFunctions_Bilinearpart/CMakeLists.txt new file mode 100644 index 00000000..6a0b0998 --- /dev/null +++ b/examples/dsp/InterpolationFunctions_Bilinearpart/CMakeLists.txt @@ -0,0 +1,4 @@ +set(TARGET_REQUIRED_PRIVATE_INCLUDE ${CMAKE_CURRENT_SOURCE_DIR} ${CMAKE_CURRENT_SOURCE_DIR}/..) +set(TARGET_REQUIRED_LIBS nmsis) +set(mains main.c) +generate_bin() \ No newline at end of file diff --git a/examples/dsp/InterpolationFunctions_Bilinearpart/array.h b/examples/dsp/InterpolationFunctions_Bilinearpart/array.h new file mode 100644 index 00000000..6bb26399 --- /dev/null +++ b/examples/dsp/InterpolationFunctions_Bilinearpart/array.h @@ -0,0 +1,9 @@ +// Array for InterpolationFunctions BilinearPart +#define ARRAY_SIZE 90 +float32_t f32_z_array[400] = {1.25000000000000,4.35000000000000,7.45000000000000,10.5500000000000,13.6500000000000,16.7500000000000,19.8500000000000,22.9500000000000,26.0500000000000,29.1500000000000,32.2500000000000,35.3500000000000,38.4500000000000,41.5500000000000,44.6500000000000,47.7500000000000,50.8500000000000,53.9500000000000,57.0500000000000,60.1500000000000,8.45000000000000,11.5500000000000,14.6500000000000,17.7500000000000,20.8500000000000,23.9500000000000,27.0500000000000,30.1500000000000,33.2500000000000,36.3500000000000,39.4500000000000,42.5500000000000,45.6500000000000,48.7500000000000,51.8500000000000,54.9500000000000,58.0500000000000,61.1500000000000,64.2500000000000,67.3500000000000,15.6500000000000,18.7500000000000,21.8500000000000,24.9500000000000,28.0500000000000,31.1500000000000,34.2500000000000,37.3500000000000,40.4500000000000,43.5500000000000,46.6500000000000,49.7500000000000,52.8500000000000,55.9500000000000,59.0500000000000,62.1500000000000,65.2500000000000,68.3500000000000,71.4500000000000,74.5500000000000,22.8500000000000,25.9500000000000,29.0500000000000,32.1500000000000,35.2500000000000,38.3500000000000,41.4500000000000,44.5500000000000,47.6500000000000,50.7500000000000,53.8500000000000,56.9500000000000,60.0500000000000,63.1500000000000,66.2500000000000,69.3500000000000,72.4500000000000,75.5500000000000,78.6500000000000,81.7500000000000,30.0500000000000,33.1500000000000,36.2500000000000,39.3500000000000,42.4500000000000,45.5500000000000,48.6500000000000,51.7500000000000,54.8500000000000,57.9500000000000,61.0500000000000,64.1500000000000,67.2500000000000,70.3500000000000,73.4500000000000,76.5500000000000,79.6500000000000,82.7500000000000,85.8500000000000,88.9500000000000,37.2500000000000,40.3500000000000,43.4500000000000,46.5500000000000,49.6500000000000,52.7500000000000,55.8500000000000,58.9500000000000,62.0500000000000,65.1500000000000,68.2500000000000,71.3500000000000,74.4500000000000,77.5500000000000,80.6500000000000,83.7500000000000,86.8500000000000,89.9500000000000,93.0500000000000,96.1500000000000,44.4500000000000,47.5500000000000,50.6500000000000,53.7500000000000,56.8500000000000,59.9500000000000,63.0500000000000,66.1500000000000,69.2500000000000,72.3500000000000,75.4500000000000,78.5500000000000,81.6500000000000,84.7500000000000,87.8500000000000,90.9500000000000,94.0500000000000,97.1500000000000,100.250000000000,103.350000000000,51.6500000000000,54.7500000000000,57.8500000000000,60.9500000000000,64.0500000000000,67.1500000000000,70.2500000000000,73.3500000000000,76.4500000000000,79.5500000000000,82.6500000000000,85.7500000000000,88.8500000000000,91.9500000000000,95.0500000000000,98.1500000000000,101.250000000000,104.350000000000,107.450000000000,110.550000000000,58.8500000000000,61.9500000000000,65.0500000000000,68.1500000000000,71.2500000000000,74.3500000000000,77.4500000000000,80.5500000000000,83.6500000000000,86.7500000000000,89.8500000000000,92.9500000000000,96.0500000000000,99.1500000000000,102.250000000000,105.350000000000,108.450000000000,111.550000000000,114.650000000000,117.750000000000,66.0500000000000,69.1500000000000,72.2500000000000,75.3500000000000,78.4500000000000,81.5500000000000,84.6500000000000,87.7500000000000,90.8500000000000,93.9500000000000,97.0500000000000,100.150000000000,103.250000000000,106.350000000000,109.450000000000,112.550000000000,115.650000000000,118.750000000000,121.850000000000,124.950000000000,73.2500000000000,76.3500000000000,79.4500000000000,82.5500000000000,85.6500000000000,88.7500000000000,91.8500000000000,94.9500000000000,98.0500000000000,101.150000000000,104.250000000000,107.350000000000,110.450000000000,113.550000000000,116.650000000000,119.750000000000,122.850000000000,125.950000000000,129.050000000000,132.150000000000,80.4500000000000,83.5500000000000,86.6500000000000,89.7500000000000,92.8500000000000,95.9500000000000,99.0500000000000,102.150000000000,105.250000000000,108.350000000000,111.450000000000,114.550000000000,117.650000000000,120.750000000000,123.850000000000,126.950000000000,130.050000000000,133.150000000000,136.250000000000,139.350000000000,87.6500000000000,90.7500000000000,93.8500000000000,96.9500000000000,100.050000000000,103.150000000000,106.250000000000,109.350000000000,112.450000000000,115.550000000000,118.650000000000,121.750000000000,124.850000000000,127.950000000000,131.050000000000,134.150000000000,137.250000000000,140.350000000000,143.450000000000,146.550000000000,94.8500000000000,97.9500000000000,101.050000000000,104.150000000000,107.250000000000,110.350000000000,113.450000000000,116.550000000000,119.650000000000,122.750000000000,125.850000000000,128.950000000000,132.050000000000,135.150000000000,138.250000000000,141.350000000000,144.450000000000,147.550000000000,150.650000000000,153.750000000000,102.050000000000,105.150000000000,108.250000000000,111.350000000000,114.450000000000,117.550000000000,120.650000000000,123.750000000000,126.850000000000,129.950000000000,133.050000000000,136.150000000000,139.250000000000,142.350000000000,145.450000000000,148.550000000000,151.650000000000,154.750000000000,157.850000000000,160.950000000000,109.250000000000,112.350000000000,115.450000000000,118.550000000000,121.650000000000,124.750000000000,127.850000000000,130.950000000000,134.050000000000,137.150000000000,140.250000000000,143.350000000000,146.450000000000,149.550000000000,152.650000000000,155.750000000000,158.850000000000,161.950000000000,165.050000000000,168.150000000000,116.450000000000,119.550000000000,122.650000000000,125.750000000000,128.850000000000,131.950000000000,135.050000000000,138.150000000000,141.250000000000,144.350000000000,147.450000000000,150.550000000000,153.650000000000,156.750000000000,159.850000000000,162.950000000000,166.050000000000,169.150000000000,172.250000000000,175.350000000000,123.650000000000,126.750000000000,129.850000000000,132.950000000000,136.050000000000,139.150000000000,142.250000000000,145.350000000000,148.450000000000,151.550000000000,154.650000000000,157.750000000000,160.850000000000,163.950000000000,167.050000000000,170.150000000000,173.250000000000,176.350000000000,179.450000000000,182.550000000000,130.850000000000,133.950000000000,137.050000000000,140.150000000000,143.250000000000,146.350000000000,149.450000000000,152.550000000000,155.650000000000,158.750000000000,161.850000000000,164.950000000000,168.050000000000,171.150000000000,174.250000000000,177.350000000000,180.450000000000,183.550000000000,186.650000000000,189.750000000000,138.050000000000,141.150000000000,144.250000000000,147.350000000000,150.450000000000,153.550000000000,156.650000000000,159.750000000000,162.850000000000,165.950000000000,169.050000000000,172.150000000000,175.250000000000,178.350000000000,181.450000000000,184.550000000000,187.650000000000,190.750000000000,193.850000000000,196.950000000000}; + +q31_t q31_z_array[400] = {5600,10320,15040,19760,24480,29200,33920,38640,43360,48080,52800,57520,62240,66960,71680,76400,81120,85840,90560,95280,9575,14295,19015,23735,28455,33175,37895,42615,47335,52055,56775,61495,66215,70935,75655,80375,85095,89815,94535,99255,13550,18270,22990,27710,32430,37150,41870,46590,51310,56030,60750,65470,70190,74910,79630,84350,89070,93790,98510,103230,17525,22245,26965,31685,36405,41125,45845,50565,55285,60005,64725,69445,74165,78885,83605,88325,93045,97765,102485,107205,21500,26220,30940,35660,40380,45100,49820,54540,59260,63980,68700,73420,78140,82860,87580,92300,97020,101740,106460,111180,25475,30195,34915,39635,44355,49075,53795,58515,63235,67955,72675,77395,82115,86835,91555,96275,100995,105715,110435,115155,29450,34170,38890,43610,48330,53050,57770,62490,67210,71930,76650,81370,86090,90810,95530,100250,104970,109690,114410,119130,33425,38145,42865,47585,52305,57025,61745,66465,71185,75905,80625,85345,90065,94785,99505,104225,108945,113665,118385,123105,37400,42120,46840,51560,56280,61000,65720,70440,75160,79880,84600,89320,94040,98760,103480,108200,112920,117640,122360,127080,41375,46095,50815,55535,60255,64975,69695,74415,79135,83855,88575,93295,98015,102735,107455,112175,116895,121615,126335,131055,45350,50070,54790,59510,64230,68950,73670,78390,83110,87830,92550,97270,101990,106710,111430,116150,120870,125590,130310,135030,49325,54045,58765,63485,68205,72925,77645,82365,87085,91805,96525,101245,105965,110685,115405,120125,124845,129565,134285,139005,53300,58020,62740,67460,72180,76900,81620,86340,91060,95780,100500,105220,109940,114660,119380,124100,128820,133540,138260,142980,57275,61995,66715,71435,76155,80875,85595,90315,95035,99755,104475,109195,113915,118635,123355,128075,132795,137515,142235,146955,61250,65970,70690,75410,80130,84850,89570,94290,99010,103730,108450,113170,117890,122610,127330,132050,136770,141490,146210,150930,65225,69945,74665,79385,84105,88825,93545,98265,102985,107705,112425,117145,121865,126585,131305,136025,140745,145465,150185,154905,69200,73920,78640,83360,88080,92800,97520,102240,106960,111680,116400,121120,125840,130560,135280,140000,144720,149440,154160,158880,73175,77895,82615,87335,92055,96775,101495,106215,110935,115655,120375,125095,129815,134535,139255,143975,148695,153415,158135,162855,77150,81870,86590,91310,96030,100750,105470,110190,114910,119630,124350,129070,133790,138510,143230,147950,152670,157390,162110,166830,81125,85845,90565,95285,100005,104725,109445,114165,118885,123605,128325,133045,137765,142485,147205,151925,156645,161365,166085,170805}; + +q15_t q15_z_array[400] = {328,369,410,451,492,533,574,615,656,697,738,779,820,861,902,943,984,1025,1066,1107,533,574,615,656,697,738,779,820,861,902,943,984,1025,1066,1107,1148,1189,1230,1271,1312,738,779,820,861,902,943,984,1025,1066,1107,1148,1189,1230,1271,1312,1353,1394,1435,1476,1517,943,984,1025,1066,1107,1148,1189,1230,1271,1312,1353,1394,1435,1476,1517,1558,1599,1640,1681,1722,1148,1189,1230,1271,1312,1353,1394,1435,1476,1517,1558,1599,1640,1681,1722,1763,1804,1845,1886,1927,1353,1394,1435,1476,1517,1558,1599,1640,1681,1722,1763,1804,1845,1886,1927,1968,2009,2050,2091,2132,1558,1599,1640,1681,1722,1763,1804,1845,1886,1927,1968,2009,2050,2091,2132,2173,2214,2255,2296,2337,1763,1804,1845,1886,1927,1968,2009,2050,2091,2132,2173,2214,2255,2296,2337,2378,2419,2460,2501,2542,1968,2009,2050,2091,2132,2173,2214,2255,2296,2337,2378,2419,2460,2501,2542,2583,2624,2665,2706,2747,2173,2214,2255,2296,2337,2378,2419,2460,2501,2542,2583,2624,2665,2706,2747,2788,2829,2870,2911,2952,2378,2419,2460,2501,2542,2583,2624,2665,2706,2747,2788,2829,2870,2911,2952,2993,3034,3075,3116,3157,2583,2624,2665,2706,2747,2788,2829,2870,2911,2952,2993,3034,3075,3116,3157,3198,3239,3280,3321,3362,2788,2829,2870,2911,2952,2993,3034,3075,3116,3157,3198,3239,3280,3321,3362,3403,3444,3485,3526,3567,2993,3034,3075,3116,3157,3198,3239,3280,3321,3362,3403,3444,3485,3526,3567,3608,3649,3690,3731,3772,3198,3239,3280,3321,3362,3403,3444,3485,3526,3567,3608,3649,3690,3731,3772,3813,3854,3895,3936,3977,3403,3444,3485,3526,3567,3608,3649,3690,3731,3772,3813,3854,3895,3936,3977,4018,4059,4100,4141,4182,3608,3649,3690,3731,3772,3813,3854,3895,3936,3977,4018,4059,4100,4141,4182,4223,4264,4305,4346,4387,3813,3854,3895,3936,3977,4018,4059,4100,4141,4182,4223,4264,4305,4346,4387,4428,4469,4510,4551,4592,4018,4059,4100,4141,4182,4223,4264,4305,4346,4387,4428,4469,4510,4551,4592,4633,4674,4715,4756,4797,4223,4264,4305,4346,4387,4428,4469,4510,4551,4592,4633,4674,4715,4756,4797,4838,4879,4920,4961,5002}; + +q7_t q7_z_array[400] = {1,17,33,49,65,81,97,113,128,128,128,128,128,128,128,128,128,128,128,128,4,20,36,52,68,84,100,116,128,128,128,128,128,128,128,128,128,128,128,128,7,23,39,55,71,87,103,119,128,128,128,128,128,128,128,128,128,128,128,128,10,26,42,58,74,90,106,122,128,128,128,128,128,128,128,128,128,128,128,128,13,29,45,61,77,93,109,125,128,128,128,128,128,128,128,128,128,128,128,128,16,32,48,64,80,96,112,128,128,128,128,128,128,128,128,128,128,128,128,128,19,35,51,67,83,99,115,128,128,128,128,128,128,128,128,128,128,128,128,128,22,38,54,70,86,102,118,128,128,128,128,128,128,128,128,128,128,128,128,128,25,41,57,73,89,105,121,128,128,128,128,128,128,128,128,128,128,128,128,128,28,44,60,76,92,108,124,128,128,128,128,128,128,128,128,128,128,128,128,128,31,47,63,79,95,111,127,128,128,128,128,128,128,128,128,128,128,128,128,128,34,50,66,82,98,114,128,128,128,128,128,128,128,128,128,128,128,128,128,128,37,53,69,85,101,117,128,128,128,128,128,128,128,128,128,128,128,128,128,128,40,56,72,88,104,120,128,128,128,128,128,128,128,128,128,128,128,128,128,128,43,59,75,91,107,123,128,128,128,128,128,128,128,128,128,128,128,128,128,128,46,62,78,94,110,126,128,128,128,128,128,128,128,128,128,128,128,128,128,128,49,65,81,97,113,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,52,68,84,100,116,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,55,71,87,103,119,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,58,74,90,106,122,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128}; diff --git a/examples/dsp/InterpolationFunctions_Bilinearpart/main.c b/examples/dsp/InterpolationFunctions_Bilinearpart/main.c new file mode 100644 index 00000000..4190a0be --- /dev/null +++ b/examples/dsp/InterpolationFunctions_Bilinearpart/main.c @@ -0,0 +1,113 @@ +#include "riscv_math.h" +#include +#include +#include "array.h" +#include "../common.h" + +#include "../HelperFunctions/math_helper.c" +#include "../HelperFunctions/ref_helper.c" + +#include +#define DELTAF32 (0.05f) +#define DELTAQ31 (63) +#define DELTAQ15 (1) +#define DELTAQ7 (1) + +int test_flag_error = 0; + +int main() +{ + int i; + + BENCH_INIT; + //simulate z=3.1*x + 7.2*y + 1.25 + riscv_bilinear_interp_instance_f32 S_f32 = { + 20, /*number of Rows*/ + 20, /*number of Columns*/ + f32_z_array, /*value of y*/ + }; + float32_t x_f32_input = 5.12, y_f32_input = 6.24, z_f32_output, z_f32_output_ref = 62.0500000000000; + BENCH_START(riscv_bilinear_interp_f32); + z_f32_output = riscv_bilinear_interp_f32(&S_f32, x_f32_input, y_f32_input); + BENCH_END(riscv_bilinear_interp_f32); + if (fabs(z_f32_output - z_f32_output_ref) > DELTAF32) { + BENCH_ERROR(riscv_bilinear_interp_f32); + printf("expect: %f, actual: %f\n", z_f32_output_ref, z_f32_output); + test_flag_error = 1; + } + BENCH_STATUS(riscv_bilinear_interp_f32); + + //simulate z=47120*x + 39675*y + 96200 + //stands for z=0.000022*x + 0.000018*y + 0.000045 + //test:x:5.12 y:6.24 + riscv_bilinear_interp_instance_q31 S_q31 = { + 20, /*number of Rows*/ + 20, /*number of Columns*/ + q31_z_array, /*value of y*/ + }; + q31_t x_q31_input = 5305794, y_q31_input = 6417285, z_q31_output, z_q31_output_ref = 579735; + BENCH_START(riscv_bilinear_interp_q31); + z_q31_output = riscv_bilinear_interp_q31(&S_q31, x_q31_input, y_q31_input); + BENCH_END(riscv_bilinear_interp_q31); + riscv_q31_to_float(&z_q31_output, &z_f32_output, 1); + riscv_q31_to_float(&z_q31_output_ref, &z_f32_output_ref, 1); + if (fabs(z_f32_output - z_f32_output_ref) > DELTAF32) { + BENCH_ERROR(riscv_bilinear_interp_q31); + printf("expect: %f, actual: %f\n", z_f32_output_ref, z_f32_output); + test_flag_error = 1; + } + BENCH_STATUS(riscv_bilinear_interp_q31); + + //simulate z=41*x + 205*y + 328 + //stands for z=0.00125*x + 0.00625*y + 0.01 + //test:x:5.12 y:6.24 + riscv_bilinear_interp_instance_q15 S_q15 = { + 20, /*number of Rows*/ + 20, /*number of Columns*/ + q15_z_array, /*value of y*/ + }; + q31_t x_q15_input = 5305794, y_q15_input = 6417285; + q15_t z_q15_output, z_q15_output_ref = 1815; + BENCH_START(riscv_bilinear_interp_q15); + z_q15_output = riscv_bilinear_interp_q15(&S_q15, x_q15_input, y_q15_input); + BENCH_END(riscv_bilinear_interp_q15); + riscv_q15_to_float(&z_q15_output, &z_f32_output, 1); + riscv_q15_to_float(&z_q15_output_ref, &z_f32_output_ref, 1); + if (fabs(z_f32_output - z_f32_output_ref) > DELTAF32) { + BENCH_ERROR(riscv_bilinear_interp_q15); + printf("expect: %f, actual: %f\n", z_f32_output_ref, z_f32_output); + test_flag_error = 1; + } + BENCH_STATUS(riscv_bilinear_interp_q15); + + //simulate z=16*x + 3*y + 1 + //stands for z=0.125*x + 0.025*y + 0.01 + //test:x:5.12 y:6.24 + riscv_bilinear_interp_instance_q7 S_q7 = { + 20, /*number of Rows*/ + 20, /*number of Columns*/ + q7_z_array, /*value of y*/ + }; + q31_t x_q7_input = 5305794, y_q7_input = 6417285; + q7_t z_q7_output, z_q7_output_ref = 103; + BENCH_START(riscv_bilinear_interp_q7); + z_q7_output = riscv_bilinear_interp_q7(&S_q7, x_q7_input, y_q7_input); + BENCH_END(riscv_bilinear_interp_q7); + riscv_q7_to_float(&z_q7_output, &z_f32_output, 1); + riscv_q7_to_float(&z_q7_output_ref, &z_f32_output_ref, 1); + if (fabs(z_f32_output - z_f32_output_ref) > DELTAF32) { + BENCH_ERROR(riscv_bilinear_interp_q7); + printf("expect: %f, actual: %f\n", z_f32_output_ref, z_f32_output); + test_flag_error = 1; + } + BENCH_STATUS(riscv_bilinear_interp_q7); + + BENCH_FINISH; + if (test_flag_error) { + printf("test error apprears, please recheck.\n"); + return 1; + } else { + printf("all test are passed. Well done!\n"); + } + return 0; +}; diff --git a/examples/dsp/InterpolationFunctions_Linearpart/CMakeLists.txt b/examples/dsp/InterpolationFunctions_Linearpart/CMakeLists.txt new file mode 100644 index 00000000..6a0b0998 --- /dev/null +++ b/examples/dsp/InterpolationFunctions_Linearpart/CMakeLists.txt @@ -0,0 +1,4 @@ +set(TARGET_REQUIRED_PRIVATE_INCLUDE ${CMAKE_CURRENT_SOURCE_DIR} ${CMAKE_CURRENT_SOURCE_DIR}/..) +set(TARGET_REQUIRED_LIBS nmsis) +set(mains main.c) +generate_bin() \ No newline at end of file diff --git a/examples/dsp/InterpolationFunctions_Linearpart/array.h b/examples/dsp/InterpolationFunctions_Linearpart/array.h new file mode 100644 index 00000000..c1996758 --- /dev/null +++ b/examples/dsp/InterpolationFunctions_Linearpart/array.h @@ -0,0 +1,12 @@ +// Array for InterpolationFunctions LinearPart +#define ARRAY_SIZE 90 +float32_t f32_x_array[ARRAY_SIZE] = {0,0.100000000000000,0.200000000000000,0.300000000000000,0.400000000000000,0.500000000000000,0.600000000000000,0.700000000000000,0.800000000000000,0.900000000000000,1,1.10000000000000,1.20000000000000,1.30000000000000,1.40000000000000,1.50000000000000,1.60000000000000,1.70000000000000,1.80000000000000,1.90000000000000,2,2.10000000000000,2.20000000000000,2.30000000000000,2.40000000000000,2.50000000000000,2.60000000000000,2.70000000000000,2.80000000000000,2.90000000000000,3,3.10000000000000,3.20000000000000,3.30000000000000,3.40000000000000,3.50000000000000,3.60000000000000,3.70000000000000,3.80000000000000,3.90000000000000,4,4.10000000000000,4.20000000000000,4.30000000000000,4.40000000000000,4.50000000000000,4.60000000000000,4.70000000000000,4.80000000000000,4.90000000000000,5,5.10000000000000,5.20000000000000,5.30000000000000,5.40000000000000,5.50000000000000,5.60000000000000,5.70000000000000,5.80000000000000,5.90000000000000,6,6.10000000000000,6.20000000000000,6.30000000000000,6.40000000000000,6.50000000000000,6.60000000000000,6.70000000000000,6.80000000000000,6.90000000000000,7,7.10000000000000,7.20000000000000,7.30000000000000,7.40000000000000,7.50000000000000,7.60000000000000,7.70000000000000,7.80000000000000,7.90000000000000,8,8.10000000000000,8.20000000000000,8.30000000000000,8.40000000000000,8.50000000000000,8.60000000000000,8.70000000000000,8.80000000000000,8.90000000000000}; + +float32_t f32_y_array[ARRAY_SIZE] = {1.57079632679490,1.88495559215388,2.19911485751286,2.51327412287183,2.82743338823081,3.14159265358979,3.45575191894877,3.76991118430775,4.08407044966673,4.39822971502571,4.71238898038469,5.02654824574367,5.34070751110265,5.65486677646163,5.96902604182061,6.28318530717959,6.59734457253857,6.91150383789755,7.22566310325652,7.53982236861550,7.85398163397448,8.16814089933346,8.48230016469244,8.79645943005142,9.11061869541040,9.42477796076938,9.73893722612836,10.0530964914873,10.3672557568463,10.6814150222053,10.9955742875643,11.3097335529233,11.6238928182822,11.9380520836412,12.2522113490002,12.5663706143592,12.8805298797182,13.1946891450771,13.5088484104361,13.8230076757951,14.1371669411541,14.4513262065131,14.7654854718720,15.0796447372310,15.3938040025900,15.7079632679490,16.0221225333079,16.3362817986669,16.6504410640259,16.9646003293849,17.2787595947439,17.5929188601028,17.9070781254618,18.2212373908208,18.5353966561798,18.8495559215388,19.1637151868977,19.4778744522567,19.7920337176157,20.1061929829747,20.4203522483337,20.7345115136926,21.0486707790516,21.3628300444106,21.6769893097696,21.9911485751286,22.3053078404875,22.6194671058465,22.9336263712055,23.2477856365645,23.5619449019234,23.8761041672824,24.1902634326414,24.5044226980004,24.8185819633594,25.1327412287183,25.4469004940773,25.7610597594363,26.0752190247953,26.3893782901543,26.7035375555132,27.0176968208722,27.3318560862312,27.6460153515902,27.9601746169492,28.2743338823081,28.5884931476671,28.9026524130261,29.2168116783851,29.5309709437441}; + +q31_t q31_y_array[ARRAY_SIZE] = {13421,281821,550221,818621,1087021,1355421,1623821,1892221,2160621,2429021,2697421,2965821,3234221,3502621,3771021,4039421,4307821,4576221,4844621,5113021,5381421,5649821,5918221,6186621,6455021,6723421,6991821,7260221,7528621,7797021,8065421,8333821,8602221,8870621,9139021,9407421,9675821,9944221,10212621,10481021,10749421,11017821,11286221,11554621,11823021,12091421,12359821,12628221,12896621,13165021,13433421,13701821,13970221,14238621,14507021,14775421,15043821,15312221,15580621,15849021,16117421,16385821,16654221,16922621,17191021,17459421,17727821,17996221,18264621,18533021,18801421,19069821,19338221,19606621,19875021,20143421,20411821,20680221,20948621,21217021,21485421,21753821,22022221,22290621,22559021,22827421,23095821,23364221,23632621,23901021}; + +q15_t q15_y_array[ARRAY_SIZE] = {20,420,820,1220,1620,2020,2420,2820,3220,3620,4020,4420,4820,5220,5620,6020,6420,6820,7220,7620,8020,8420,8820,9220,9620,10020,10420,10820,11220,11620,12020,12420,12820,13220,13620,14020,14420,14820,15220,15620,16020,16420,16820,17220,17620,18020,18420,18820,19220,19620,20020,20420,20820,21220,21620,22020,22420,22820,23220,23620,24020,24420,24820,25220,25620,26020,26420,26820,27220,27620,28020,28420,28820,29220,29620,30020,30420,30820,31220,31620,32020,32420,32820,33220,33620,34020,34420,34820,35220,35620}; + +q7_t q7_y_array[9] = {3,13,23,33,43,53,63,73,83}; + diff --git a/examples/dsp/InterpolationFunctions_Linearpart/main.c b/examples/dsp/InterpolationFunctions_Linearpart/main.c new file mode 100644 index 00000000..59681d55 --- /dev/null +++ b/examples/dsp/InterpolationFunctions_Linearpart/main.c @@ -0,0 +1,112 @@ +#include "riscv_math.h" +#include +#include +#include "array.h" +#include "../common.h" + +#include "../HelperFunctions/math_helper.c" +#include "../HelperFunctions/ref_helper.c" + +#include +#define DELTAF32 (0.05f) +#define DELTAQ31 (63) +#define DELTAQ15 (1) +#define DELTAQ7 (1) + +int test_flag_error = 0; + +int main() +{ + int i; + + BENCH_INIT; + //simulate y=pi*x + pi/2 + riscv_linear_interp_instance_f32 S_f32 = { + ARRAY_SIZE, /*number of values*/ + 0, /*start value of x*/ + 0.1, /*x's spacing*/ + f32_y_array, /*value of y*/ + }; + float32_t x_f32_input = 5.12, y_f32_output, y_f32_output_ref = 17.6557507131746; + BENCH_START(riscv_linear_interp_f32); + y_f32_output = riscv_linear_interp_f32(&S_f32, x_f32_input); + BENCH_END(riscv_linear_interp_f32); + if (fabs(y_f32_output - y_f32_output_ref) > DELTAF32) { + BENCH_ERROR(riscv_linear_interp_f32); + printf("expect: %f, actual: %f\n", y_f32_output_ref, y_f32_output); + test_flag_error = 1; + } + BENCH_STATUS(riscv_linear_interp_f32); + + + //simulate y=0.00000125x+0.00000625 + //in q31 is y=2684x+13421 + //the x_input is 3972. + //x_q31_input is in 12.20 format. 12 for start position, 20 for format(calculate before). + //first calculate the format, then shift right 12 bits. At last move expected index to the high 12 bits + //this is 39 and 0.72 + q31_t x_q31_input = 41271951, y_q31_output, y_q31_output_ref = 10674269; + BENCH_START(riscv_linear_interp_q31); + y_q31_output = riscv_linear_interp_q31(q31_y_array, x_q31_input, ARRAY_SIZE); + BENCH_END(riscv_linear_interp_q31); + //change result to float32_t to compare + riscv_q31_to_float(&y_q31_output, &y_f32_output, 1); + riscv_q31_to_float(&y_q31_output_ref, &y_f32_output_ref, 1); + if (fabs(y_f32_output - y_f32_output_ref) > DELTAF32) { + BENCH_ERROR(riscv_linear_interp_q31); + printf("expect: %f, actual: %f\n", y_f32_output_ref, y_f32_output); + test_flag_error = 1; + } + BENCH_STATUS(riscv_linear_interp_q31); + + //simulate y=0.000125x+0.000625 + //in q15 is y=4x+20 + //the x_input is 3972. + //x_q15_input is in 12.20 format. 12 for start position, 20 for format(calculate before). + //first calculate the format, then shift right 12 bits. At last move expected index to the high 12 bits + //this is 39 and 0.72 + q31_t x_q15_input = 41271951; + q15_t y_q15_output, y_q15_output_ref = 15908; + BENCH_START(riscv_linear_interp_q31); + y_q15_output = riscv_linear_interp_q15(q15_y_array, x_q15_input, ARRAY_SIZE); + BENCH_END(riscv_linear_interp_q15); + //change result to float32_t to compare + riscv_q15_to_float(&y_q15_output, &y_f32_output, 1); + riscv_q15_to_float(&y_q15_output_ref, &y_f32_output_ref, 1); + if (fabs(y_f32_output - y_f32_output_ref) > DELTAF32) { + BENCH_ERROR(riscv_linear_interp_q15); + printf("expect: %f, actual: %f\n", y_f32_output_ref, y_f32_output); + test_flag_error = 1; + } + BENCH_STATUS(riscv_linear_interp_q15); + + //simulate y=0.02x+0.03 + //in q7 is y=2x+3 + //the x_input is 39. + //x_q7_input is in 12.20 format. 12 for start position, 20 for format(calculate before). + //first calculate the format, then shift right 12 bits. At last move expected index to the high 12 bits + //this is 35 and 0.8 + q31_t x_q7_input = 37119590; + q7_t y_q7_output, y_q7_output_ref = 81; + BENCH_START(riscv_linear_interp_q31); + y_q7_output = riscv_linear_interp_q7(q7_y_array, x_q7_input, 9); + BENCH_END(riscv_linear_interp_q7); + //change result to float32_t to compare + riscv_q7_to_float(&y_q7_output, &y_f32_output, 1); + riscv_q7_to_float(&y_q7_output_ref, &y_f32_output_ref, 1); + if (fabs(y_f32_output - y_f32_output_ref) > DELTAF32) { + BENCH_ERROR(riscv_linear_interp_q7); + printf("expect: %f, actual: %f\n", y_f32_output_ref, y_f32_output); + test_flag_error = 1; + } + BENCH_STATUS(riscv_linear_interp_q7); + + BENCH_FINISH; + if (test_flag_error) { + printf("test error apprears, please recheck.\n"); + return 1; + } else { + printf("all test are passed. Well done!\n"); + } + return 0; +}; diff --git a/examples/dsp/MatrixFunctions_f32Part/CMakeLists.txt b/examples/dsp/MatrixFunctions_f32Part/CMakeLists.txt new file mode 100644 index 00000000..7fba6da4 --- /dev/null +++ b/examples/dsp/MatrixFunctions_f32Part/CMakeLists.txt @@ -0,0 +1,6 @@ +set(TARGET_REQUIRED_PRIVATE_INCLUDE ${CMAKE_CURRENT_SOURCE_DIR} ${CMAKE_CURRENT_SOURCE_DIR}/..) +list(APPEND TARGET_REQUIRED_SRCS mat_add.c mat_cholesky.c mat_cmplx_mult.c mat_inverse.c mat_ldlt.c) +list(APPEND TARGET_REQUIRED_SRCS mat_lower_solver.c mat_mult.c mat_scale.c mat_sub.c mat_trans.c mat_upper_solver.c) +set(TARGET_REQUIRED_LIBS nmsis) +set(mains main.c) +# generate_bin() \ No newline at end of file diff --git a/examples/dsp/MatrixFunctions_f32Part/array.h b/examples/dsp/MatrixFunctions_f32Part/array.h new file mode 100644 index 00000000..6a0dd6e5 --- /dev/null +++ b/examples/dsp/MatrixFunctions_f32Part/array.h @@ -0,0 +1,24 @@ +// Array for MatrixFunctions f32Part +#define ROWS 64 +#define COLUMNS 64 +/* clang-format off */ +float32_t f32_a_array[ROWS * COLUMNS] = { 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+float32_t f32_b_array[ROWS * COLUMNS] = { + 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+ float32_t f32_output[ROWS * COLUMNS]; + float32_t f32_output_ref[ROWS * COLUMNS]; + float32_t f32_output_back[ROWS * COLUMNS]; + float32_t f32_inv_output_ref[ROWS * COLUMNS] = { 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+ +float64_t f64_a_array[ROWS * COLUMNS] = { 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+float64_t f64_b_array[ROWS * COLUMNS] = { + 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+ float64_t f64_output[ROWS * COLUMNS]; + float64_t f64_output_ref[ROWS * COLUMNS]; + float64_t f64_output_back[ROWS * COLUMNS]; + float64_t f64_inv_output_ref[ROWS * COLUMNS] = { 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+ \ No newline at end of file diff --git a/examples/dsp/MatrixFunctions_f32Part/main.c b/examples/dsp/MatrixFunctions_f32Part/main.c new file mode 100644 index 00000000..f98157eb --- /dev/null +++ b/examples/dsp/MatrixFunctions_f32Part/main.c @@ -0,0 +1,358 @@ +// +// Created by lujun on 19-6-28. +// +// This contains f32, q31 and q15 versions of matrix +// each one has it's own function. +// All function can be found in main function. +// If you don't want to use it, then comment it. +#include "riscv_math.h" +#include "array.h" +#include +#include "../common.h" + +#include "../HelperFunctions/math_helper.c" +#include "../HelperFunctions/ref_helper.c" + +#include +#define DELTAF32 (0.05f) +#define DELTAF64 (0.05f) +#define DELTAQ31 (63) +#define DELTAQ15 (1) +#define DELTAQ7 (1) + +int test_flag_error = 0; + + + + + + + +int DSP_matrix_f32(void) +{ + riscv_matrix_instance_f32 f32_A; + riscv_matrix_instance_f32 f32_B; + riscv_matrix_instance_f32 f32_ref; + riscv_matrix_instance_f32 f32_des; + riscv_matrix_instance_f32 f32_back; + int i; + riscv_mat_init_f32(&f32_A, ROWS, COLUMNS, (float32_t *)f32_a_array); + riscv_mat_init_f32(&f32_B, ROWS, COLUMNS, (float32_t *)f32_b_array); + riscv_mat_init_f32(&f32_des, ROWS, COLUMNS, f32_output); + riscv_mat_init_f32(&f32_back, ROWS, COLUMNS, f32_output_back); + riscv_mat_init_f32(&f32_ref, ROWS, COLUMNS, f32_output_ref); + + BENCH_START(riscv_mat_add_f32); + riscv_mat_add_f32(&f32_A, &f32_B, &f32_des); + BENCH_END(riscv_mat_add_f32); + ref_mat_add_f32(&f32_A, &f32_B, &f32_ref); + for (int i = 0; i < (ROWS * COLUMNS); i++) + if (fabs(f32_output[i] - f32_output_ref[i]) > DELTAF32) { + BENCH_ERROR(riscv_mat_add_f32); + printf("index: %d,expect: %f, actual: %f\n", i, f32_output_ref[i], + f32_output[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_mat_add_f32); + // inverse + BENCH_START(riscv_mat_inverse_f32); + riscv_mat_inverse_f32(&f32_A, &f32_des); + BENCH_END(riscv_mat_inverse_f32); + // ref_mat_inverse_f32(&f32_A, &f32_ref); + for (int i = 0; i < (ROWS * COLUMNS); i++) + if (fabs(f32_output[i] - f32_inv_output_ref[i]) > DELTAF32) { + BENCH_ERROR(riscv_mat_inverse_f32); + printf("index: %d,expect: %f, actual: %f\n", i, + f32_inv_output_ref[i], f32_output[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_mat_inverse_f32); + // mult + BENCH_START(riscv_mat_mult_f32); + riscv_mat_mult_f32(&f32_A, &f32_B, &f32_des); + BENCH_END(riscv_mat_mult_f32); + ref_mat_mult_f32(&f32_A, &f32_B, &f32_ref); + for (int i = 0; i < (ROWS * COLUMNS); i++) + if (fabs(f32_output[i] - f32_output_ref[i]) > DELTAF32) { + BENCH_ERROR(riscv_mat_mult_f32); + printf("index: %d,expect: %f, actual: %f\n", i, f32_output_ref[i], + f32_output[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_mat_mult_f32); + // scale + BENCH_START(riscv_mat_scale_f32); + riscv_mat_scale_f32(&f32_A, 8.73f, &f32_des); + BENCH_END(riscv_mat_scale_f32); + ref_mat_scale_f32(&f32_A, 8.73f, &f32_ref); + for (int i = 0; i < (ROWS * COLUMNS); i++) + if (fabs(f32_output[i] - f32_output_ref[i]) > DELTAF32) { + BENCH_ERROR(riscv_mat_scale_f32); + printf("index: %d,expect: %f, actual: %f\n", i, f32_output_ref[i], + f32_output[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_mat_scale_f32); + // sub + BENCH_START(riscv_mat_sub_f32); + riscv_mat_sub_f32(&f32_A, &f32_B, &f32_des); + BENCH_END(riscv_mat_sub_f32); + ref_mat_sub_f32(&f32_A, &f32_B, &f32_ref); + for (int i = 0; i < (ROWS * COLUMNS); i++) + if (fabs(f32_output[i] - f32_output_ref[i]) > DELTAF32) { + BENCH_ERROR(riscv_mat_sub_f32); + printf("index: %d,expect: %f, actual: %f\n", i, f32_output_ref[i], + f32_output[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_mat_sub_f32); + // trans + BENCH_START(riscv_mat_trans_f32); + riscv_mat_trans_f32(&f32_A, &f32_des); + BENCH_END(riscv_mat_trans_f32); + ref_mat_trans_f32(&f32_A, &f32_ref); + for (int i = 0; i < (ROWS * COLUMNS); i++) + if (fabs(f32_output[i] - f32_output_ref[i]) > DELTAF32) { + BENCH_ERROR(riscv_mat_trans_f32); + printf("index: %d,expect: %f, actual: %f\n", i, f32_output_ref[i], + f32_output[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_mat_trans_f32); + // cmplx_mult + riscv_mat_init_f32(&f32_A, ROWS/2, COLUMNS/2, (float32_t *)f32_a_array); + riscv_mat_init_f32(&f32_B, ROWS/2, COLUMNS/2, (float32_t *)f32_b_array); + riscv_mat_init_f32(&f32_des, ROWS/2, COLUMNS/2, f32_output); + riscv_mat_init_f32(&f32_ref, ROWS/2, COLUMNS/2, f32_output_ref); + BENCH_START(riscv_mat_cmplx_mult_f32); + riscv_mat_cmplx_mult_f32(&f32_A, &f32_B, &f32_des); + BENCH_END(riscv_mat_cmplx_mult_f32); + ref_mat_cmplx_mult_f32(&f32_A, &f32_B, &f32_ref); + for (i = 0; i < (ROWS/2 * COLUMNS/2); i++) + if (fabs(f32_output[i] - f32_output_ref[i]) > DELTAF32) { + BENCH_ERROR(riscv_mat_cmplx_mult_f32); + printf("index: %d,expect: %f, actual: %f\n", i, f32_output_ref[i], + f32_output[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_mat_cmplx_mult_f32); + // cholesky + riscv_mat_init_f32(&f32_A, ROWS, COLUMNS, (float32_t *)f32_a_array); + riscv_mat_init_f32(&f32_des, ROWS, COLUMNS, f32_output); + riscv_mat_init_f32(&f32_ref, ROWS, COLUMNS, f32_output_ref); + + BENCH_START(riscv_mat_cholesky_f32); + riscv_mat_cholesky_f32(&f32_A, &f32_des); + BENCH_END(riscv_mat_cholesky_f32); + ref_mat_cholesky_f32(&f32_A, &f32_ref); + for (int i = 0; i < (ROWS * COLUMNS); i++) + if (fabs(f32_output[i] - f32_output_ref[i]) > DELTAF32) { + BENCH_ERROR(riscv_mat_cholesky_f32); + printf("index: %d,expect: %f, actual: %f\n", i, f32_output_ref[i], + f32_output[i]); + test_flag_error = 1; + } + // if(a == RISCV_MATH_DECOMPOSITION_FAILURE) printf("!!!!!!!!!!!!!!!!!!!!!"); + BENCH_STATUS(riscv_mat_cholesky_f32); + // solve upper triangular matrix + // initialize upper triangular matrix by setting 0 to lower elements in matrix + for(int i=0;i DELTAF32) { + BENCH_ERROR(riscv_mat_solve_upper_triangular_f32); + printf("index: %d,expect: %f, actual: %f\n", i, f32_output_ref[i], + f32_output[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_mat_solve_upper_triangular_f32); + + // solve lower triangular matrix + // initialize lower triangular matrix by setting 0 to upper elements in matrix + for(int i=0;ii;j--){ + f32_a_array[i*COLUMNS+j] = 0; + } + } + BENCH_START(riscv_mat_solve_lower_triangular_f32); + riscv_mat_solve_lower_triangular_f32(&f32_A, &f32_B, &f32_des); + BENCH_END(riscv_mat_solve_lower_triangular_f32); + ref_mat_solve_lower_triangular_f32(&f32_A, &f32_B, &f32_ref); + for (int i = 0; i < (ROWS * 1); i++) + if (fabs(f32_output[i] - f32_output_ref[i]) > DELTAF32) { + BENCH_ERROR(riscv_mat_solve_lower_triangular_f32); + printf("index: %d,expect: %f, actual: %f\n", i, f32_output_ref[i], + f32_output[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_mat_solve_lower_triangular_f32); + + // // Initialize Symmetric Matrices + uint16_t pp[ROWS], pp_ref[ROWS]; + for(int i=0;ii;j--){ + if(i==j) break; + f32_a_array[i*COLUMNS+j] = f32_a_array[j*COLUMNS+i]; + } + } + riscv_mat_init_f32(&f32_B, ROWS, COLUMNS, (float32_t *)f32_b_array); + BENCH_START(riscv_mat_ldlt_f32); + riscv_mat_ldlt_f32(&f32_A, &f32_B, &f32_des, pp); + BENCH_END(riscv_mat_ldlt_f32); + ref_mat_ldlt_f32(&f32_A, &f32_back, &f32_ref, pp_ref); + for (int i = 0; i < (ROWS * COLUMNS); i++) + if (fabs(f32_output[i] - f32_output_ref[i]) > DELTAF32) { + BENCH_ERROR(riscv_mat_ldlt_f32); + printf("index: %d,expect: %f, actual: %f\n", i, f32_output_ref[i], + f32_output[i]); + test_flag_error = 1; + } + for (int i = 0; i < (ROWS * COLUMNS); i++) + if (fabs(f32_b_array[i] - f32_output_back[i]) > DELTAF32) { + BENCH_ERROR(riscv_mat_ldlt_f32); + printf("index: %d,expect: %f, actual: %f\n", i, f32_output_back[i], + f32_b_array[i]); + test_flag_error = 1; + } + for (int i = 0; i < ROWS; i++) + if ((pp - pp_ref) > DELTAF32) { + BENCH_ERROR(riscv_mat_ldlt_f32); + printf("expect: %f, actual: %f\n", pp_ref, pp); + test_flag_error = 1; + } + BENCH_STATUS(riscv_mat_ldlt_f32); + + printf("all tests are passed,well done!\n"); +} + +int DSP_matrix_f64(void) +{ + riscv_matrix_instance_f64 f64_A; + riscv_matrix_instance_f64 f64_B; + riscv_matrix_instance_f64 f64_back; + riscv_matrix_instance_f64 f64_ref; + riscv_matrix_instance_f64 f64_des; + int i; + riscv_mat_init_f64(&f64_A, ROWS, COLUMNS, (float64_t *)f64_a_array); + riscv_mat_init_f64(&f64_B, ROWS, COLUMNS, (float64_t *)f64_b_array); + riscv_mat_init_f64(&f64_des, ROWS, COLUMNS, f64_output); + riscv_mat_init_f64(&f64_back, ROWS, COLUMNS, f64_output_back); + riscv_mat_init_f64(&f64_ref, ROWS, COLUMNS, f64_output_ref); + + BENCH_START(riscv_mat_cholesky_f64); + riscv_mat_cholesky_f64(&f64_A, &f64_des); + BENCH_END(riscv_mat_cholesky_f64); + ref_mat_cholesky_f64(&f64_A, &f64_ref); + for (int i = 0; i < (ROWS * COLUMNS); i++) + if (fabs(f64_output[i] - f64_output_ref[i]) > DELTAF64) { + BENCH_ERROR(riscv_mat_cholesky_f64); + printf("index: %d,expect: %f, actual: %f\n", i, f64_output_ref[i], + f64_output[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_mat_cholesky_f64); + + // solve upper triangular matrix + // initialize upper triangular matrix by setting 0 to lower elements in matrix + for(int i=0;i DELTAF64) { + BENCH_ERROR(riscv_mat_solve_upper_triangular_f64); + printf("index: %d,expect: %f, actual: %f\n", i, f64_output_ref[i], + f64_output[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_mat_solve_upper_triangular_f64); + + // solve lower triangular matrix + // initialize lower triangular matrix by setting 0 to upper elements in matrix + for(int i=0;ii;j--){ + f64_a_array[i*COLUMNS+j] = 0; + } + } + BENCH_START(riscv_mat_solve_lower_triangular_f64); + riscv_mat_solve_lower_triangular_f64(&f64_A, &f64_B, &f64_des); + BENCH_END(riscv_mat_solve_lower_triangular_f64); + ref_mat_solve_lower_triangular_f64(&f64_A, &f64_B, &f64_ref); + for (int i = 0; i < (ROWS * 1); i++) + if (fabs(f64_output[i] - f64_output_ref[i]) > DELTAF64) { + BENCH_ERROR(riscv_mat_solve_lower_triangular_f64); + printf("index: %d,expect: %f, actual: %f\n", i, f64_output_ref[i], + f64_output[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_mat_solve_lower_triangular_f64); + + // Initialize Symmetric Matrices + uint16_t pp[ROWS], pp_ref[ROWS]; + for(int i=0;ii;j--){ + if(i==j) break; + f64_a_array[i*COLUMNS+j] = f64_a_array[j*COLUMNS+i]; + } + } + riscv_mat_init_f64(&f64_B, ROWS, COLUMNS, (float64_t *)f64_b_array); + BENCH_START(riscv_mat_ldlt_f64); + riscv_mat_ldlt_f64(&f64_A, &f64_B, &f64_des, pp); + BENCH_END(riscv_mat_ldlt_f64); + ref_mat_ldlt_f64(&f64_A, &f64_back, &f64_ref, pp_ref); + for (int i = 0; i < (ROWS * COLUMNS); i++) + if (fabs(f64_output[i] - f64_output_ref[i]) > DELTAF64) { + BENCH_ERROR(riscv_mat_ldlt_f64); + printf("index: %d,expect: %f, actual: %f\n", i, f64_output_ref[i], + f64_output[i]); + test_flag_error = 1; + } + for (int i = 0; i < (ROWS * COLUMNS); i++) + if (fabs(f64_b_array[i] - f64_output_back[i]) > DELTAF64) { + BENCH_ERROR(riscv_mat_ldlt_f64); + printf("index: %d,expect: %f, actual: %f\n", i, f64_output_back[i], + f64_b_array[i]); + test_flag_error = 1; + } + for (int i = 0; i < ROWS; i++) + if ((pp - pp_ref) > DELTAF64) { + BENCH_ERROR(riscv_mat_ldlt_f64); + printf("expect: %f, actual: %f\n", pp_ref, pp); + test_flag_error = 1; + } + BENCH_STATUS(riscv_mat_ldlt_f64); + + printf("all tests are passed,well done!\n"); +} + + +int main() +{ + BENCH_INIT; + // DSP_matrix_f32(); + DSP_matrix_f64(); + BENCH_FINISH; + if (test_flag_error) { + printf("test error apprears, please recheck.\n"); + return 1; + } else { + printf("all test are passed. Well done!\n"); + } + return 0; +} diff --git a/examples/dsp/MatrixFunctions_f32Part/mat_add.c b/examples/dsp/MatrixFunctions_f32Part/mat_add.c new file mode 100644 index 00000000..eccec2e0 --- /dev/null +++ b/examples/dsp/MatrixFunctions_f32Part/mat_add.c @@ -0,0 +1,52 @@ +#include "ref.h" + +riscv_status ref_mat_add_f32(const riscv_matrix_instance_f32 *pSrcA, + const riscv_matrix_instance_f32 *pSrcB, + riscv_matrix_instance_f32 *pDst) +{ + uint32_t i; + uint32_t numSamples; /* total number of elements in the matrix */ + + /* Total number of samples in the input matrix */ + numSamples = (uint32_t)pSrcA->numRows * pSrcA->numCols; + + for (i = 0; i < numSamples; i++) { + pDst->pData[i] = pSrcA->pData[i] + pSrcB->pData[i]; + } + + return RISCV_MATH_SUCCESS; +} + +riscv_status ref_mat_add_q31(const riscv_matrix_instance_q31 *pSrcA, + const riscv_matrix_instance_q31 *pSrcB, + riscv_matrix_instance_q31 *pDst) +{ + uint32_t i; + uint32_t numSamples; /* total number of elements in the matrix */ + + /* Total number of samples in the input matrix */ + numSamples = (uint32_t)pSrcA->numRows * pSrcA->numCols; + + for (i = 0; i < numSamples; i++) { + pDst->pData[i] = ref_sat_q31((q63_t)pSrcA->pData[i] + pSrcB->pData[i]); + } + + return RISCV_MATH_SUCCESS; +} + +riscv_status ref_mat_add_q15(const riscv_matrix_instance_q15 *pSrcA, + const riscv_matrix_instance_q15 *pSrcB, + riscv_matrix_instance_q15 *pDst) +{ + uint32_t i; + uint32_t numSamples; /* total number of elements in the matrix */ + + /* Total number of samples in the input matrix */ + numSamples = (uint32_t)pSrcA->numRows * pSrcA->numCols; + + for (i = 0; i < numSamples; i++) { + pDst->pData[i] = ref_sat_q15((q31_t)pSrcA->pData[i] + pSrcB->pData[i]); + } + + return RISCV_MATH_SUCCESS; +} diff --git a/examples/dsp/MatrixFunctions_f32Part/mat_cholesky.c b/examples/dsp/MatrixFunctions_f32Part/mat_cholesky.c new file mode 100644 index 00000000..753ed212 --- /dev/null +++ b/examples/dsp/MatrixFunctions_f32Part/mat_cholesky.c @@ -0,0 +1,102 @@ +#include "ref.h" + +#include "dsp/matrix_functions.h" + +riscv_status ref_mat_cholesky_f32( + const riscv_matrix_instance_f32 * pSrc, + riscv_matrix_instance_f32 * pDst) +{ + + riscv_status status; /* status of matrix inverse */ + + { + int i,j,k; + int n = pSrc->numRows; + float32_t invSqrtVj; + float32_t *pA,*pG; + + pA = pSrc->pData; + pG = pDst->pData; + + + for(i=0 ; i < n ; i++) + { + for(j=i ; j < n ; j++) + { + pG[j * n + i] = pA[j * n + i]; + + for(k=0; k < i ; k++) + { + pG[j * n + i] = pG[j * n + i] - pG[i * n + k] * pG[j * n + k]; + } + } + + if (pG[i * n + i] <= 0.0f) + { + return(RISCV_MATH_DECOMPOSITION_FAILURE); + } + + invSqrtVj = 1.0f/sqrtf(pG[i * n + i]); + for(j=i ; j < n ; j++) + { + pG[j * n + i] = pG[j * n + i] * invSqrtVj ; + } + } + + status = RISCV_MATH_SUCCESS; + + } + + + /* Return to application */ + return (status); +} + +riscv_status ref_mat_cholesky_f64( + const riscv_matrix_instance_f64 * pSrc, + riscv_matrix_instance_f64 * pDst) +{ + riscv_status status; /* status of matrix inverse */ + + { + int i,j,k; + int n = pSrc->numRows; + float64_t invSqrtVj; + float64_t *pA,*pG; + + pA = pSrc->pData; + pG = pDst->pData; + + + for(i=0 ; i < n ; i++) + { + for(j=i ; j < n ; j++) + { + pG[j * n + i] = pA[j * n + i]; + + for(k=0; k < i ; k++) + { + pG[j * n + i] = pG[j * n + i] - pG[i * n + k] * pG[j * n + k]; + } + } + + if (pG[i * n + i] <= 0.0f) + { + return(RISCV_MATH_DECOMPOSITION_FAILURE); + } + + invSqrtVj = 1.0/sqrt(pG[i * n + i]); + for(j=i ; j < n ; j++) + { + pG[j * n + i] = pG[j * n + i] * invSqrtVj ; + } + } + + status = RISCV_MATH_SUCCESS; + + } + + + /* Return to application */ + return (status); +} \ No newline at end of file diff --git a/examples/dsp/MatrixFunctions_f32Part/mat_cmplx_mult.c b/examples/dsp/MatrixFunctions_f32Part/mat_cmplx_mult.c new file mode 100644 index 00000000..a9a99cd1 --- /dev/null +++ b/examples/dsp/MatrixFunctions_f32Part/mat_cmplx_mult.c @@ -0,0 +1,114 @@ +#include "ref.h" + +//#include "riscv_math.h" +//#include "../common.h" + +//#include "../HelperFunctions/ref_helper.c" +//#include "FastMathFunctions.c" +// /#include +#define DELTA (0.05f) + +riscv_status ref_mat_cmplx_mult_f32(const riscv_matrix_instance_f32 *pSrcA, + const riscv_matrix_instance_f32 *pSrcB, + riscv_matrix_instance_f32 *pDst) +{ + uint32_t r, c, i, outR, outC, innerSize; + float32_t sumR, sumI; + float32_t a0, b0, c0, d0; + + outR = pSrcA->numRows; + outC = pSrcB->numCols; + innerSize = pSrcA->numCols; + + for (r = 0; r < outR; r++) { + for (c = 0; c < outC; c++) { + sumR = 0; + sumI = 0; + + for (i = 0; i < innerSize; i++) { + a0 = pSrcA->pData[2 * (r * innerSize + i) + 0]; + b0 = pSrcA->pData[2 * (r * innerSize + i) + 1]; + c0 = pSrcB->pData[2 * (i * outC + c) + 0]; + d0 = pSrcB->pData[2 * (i * outC + c) + 1]; + + sumR += a0 * c0 - b0 * d0; + sumI += b0 * c0 + a0 * d0; + } + + pDst->pData[2 * (r * outC + c) + 0] = sumR; + pDst->pData[2 * (r * outC + c) + 1] = sumI; + } + } + + return RISCV_MATH_SUCCESS; +} + +riscv_status ref_mat_cmplx_mult_q31(const riscv_matrix_instance_q31 *pSrcA, + const riscv_matrix_instance_q31 *pSrcB, + riscv_matrix_instance_q31 *pDst) +{ + uint32_t r, c, i, outR, outC, innerSize; + q63_t sumR, sumI; + q31_t a0, b0, c0, d0; + + outR = pSrcA->numRows; + outC = pSrcB->numCols; + innerSize = pSrcA->numCols; + + for (r = 0; r < outR; r++) { + for (c = 0; c < outC; c++) { + sumR = 0; + sumI = 0; + + for (i = 0; i < innerSize; i++) { + a0 = pSrcA->pData[2 * (r * innerSize + i) + 0]; + b0 = pSrcA->pData[2 * (r * innerSize + i) + 1]; + c0 = pSrcB->pData[2 * (i * outC + c) + 0]; + d0 = pSrcB->pData[2 * (i * outC + c) + 1]; + + sumR += (q63_t)a0 * c0 - (q63_t)b0 * d0; + sumI += (q63_t)b0 * c0 + (q63_t)a0 * d0; + } + + pDst->pData[2 * (r * outC + c) + 0] = ref_sat_q31(sumR >> 31); + pDst->pData[2 * (r * outC + c) + 1] = ref_sat_q31(sumI >> 31); + } + } + + return RISCV_MATH_SUCCESS; +} + +riscv_status ref_mat_cmplx_mult_q15(const riscv_matrix_instance_q15 *pSrcA, + const riscv_matrix_instance_q15 *pSrcB, + riscv_matrix_instance_q15 *pDst) +{ + uint32_t r, c, i, outR, outC, innerSize; + q63_t sumR, sumI; + q15_t a0, b0, c0, d0; + + outR = pSrcA->numRows; + outC = pSrcB->numCols; + innerSize = pSrcA->numCols; + + for (r = 0; r < outR; r++) { + for (c = 0; c < outC; c++) { + sumR = 0; + sumI = 0; + + for (i = 0; i < innerSize; i++) { + a0 = pSrcA->pData[2 * (r * innerSize + i) + 0]; + b0 = pSrcA->pData[2 * (r * innerSize + i) + 1]; + c0 = pSrcB->pData[2 * (i * outC + c) + 0]; + d0 = pSrcB->pData[2 * (i * outC + c) + 1]; + + sumR += (q31_t)a0 * c0 - (q31_t)b0 * d0; + sumI += (q31_t)b0 * c0 + (q31_t)a0 * d0; + } + + pDst->pData[2 * (r * outC + c) + 0] = ref_sat_q15(sumR >> 15); + pDst->pData[2 * (r * outC + c) + 1] = ref_sat_q15(sumI >> 15); + } + } + + return RISCV_MATH_SUCCESS; +} diff --git a/examples/dsp/MatrixFunctions_f32Part/mat_inverse.c b/examples/dsp/MatrixFunctions_f32Part/mat_inverse.c new file mode 100644 index 00000000..696ce4fc --- /dev/null +++ b/examples/dsp/MatrixFunctions_f32Part/mat_inverse.c @@ -0,0 +1,54 @@ +#include "ref.h" + +riscv_status ref_mat_inverse_f32(const riscv_matrix_instance_f32 *pSrc, + riscv_matrix_instance_f32 *pDst) +{ + float32_t det; + uint32_t i, size; + riscv_matrix_instance_f32 tmp; + + tmp.numCols = pSrc->numCols; + tmp.numRows = pSrc->numRows; + tmp.pData = scratchArray; + + det = ref_detrm(pSrc->pData, scratchArray, pSrc->numCols); + + size = pSrc->numCols * pSrc->numCols; + + ref_cofact(pSrc->pData, scratchArray, scratchArray + size, pSrc->numCols); + + ref_mat_trans_f32(&tmp, pDst); + + for (i = 0; i < size; i++) { + pDst->pData[i] /= det; + } + + return RISCV_MATH_SUCCESS; +} + +riscv_status ref_mat_inverse_f64(const riscv_matrix_instance_f64 *pSrc, + riscv_matrix_instance_f64 *pDst) +{ + float64_t det; + uint32_t i, size; + riscv_matrix_instance_f64 tmp; + + tmp.numCols = pSrc->numCols; + tmp.numRows = pSrc->numRows; + tmp.pData = (float64_t *)scratchArray; + + det = ref_detrm64(pSrc->pData, (float64_t *)scratchArray, pSrc->numCols); + + size = pSrc->numCols * pSrc->numCols; + + ref_cofact64(pSrc->pData, (float64_t *)scratchArray, + (float64_t *)scratchArray + size, pSrc->numCols); + + ref_mat_trans_f64(&tmp, pDst); + + for (i = 0; i < size; i++) { + pDst->pData[i] /= det; + } + + return RISCV_MATH_SUCCESS; +} diff --git a/examples/dsp/MatrixFunctions_f32Part/mat_ldlt.c b/examples/dsp/MatrixFunctions_f32Part/mat_ldlt.c new file mode 100644 index 00000000..48b4d3f2 --- /dev/null +++ b/examples/dsp/MatrixFunctions_f32Part/mat_ldlt.c @@ -0,0 +1,259 @@ +#include "ref.h" + +/// @private +#define SWAP_ROWS_F32(A,i,j) \ + for(int w=0;w < n; w++) \ + { \ + float32_t tmp; \ + tmp = A[i*n + w]; \ + A[i*n + w] = A[j*n + w];\ + A[j*n + w] = tmp; \ + } + +/// @private +#define SWAP_COLS_F32(A,i,j) \ + for(int w=0;w < n; w++) \ + { \ + float32_t tmp; \ + tmp = A[w*n + i]; \ + A[w*n + i] = A[w*n + j];\ + A[w*n + j] = tmp; \ + } + +riscv_status ref_mat_ldlt_f32( + const riscv_matrix_instance_f32 * pSrc, + riscv_matrix_instance_f32 * pl, + riscv_matrix_instance_f32 * pd, + uint16_t * pp) +{ + + riscv_status status; /* status of matrix inverse */ + { + + const int n=pSrc->numRows; + int fullRank = 1, diag,k; + float32_t *pA; + + memcpy(pl->pData,pSrc->pData,n*n*sizeof(float32_t)); + pA = pl->pData; + + for(int k=0;k < n; k++) + { + pp[k] = k; + } + + + for(k=0;k < n; k++) + { + /* Find pivot */ + float32_t m=F32_MIN,a; + int j=k; + + + for(int r=k;r m) + { + m = pA[r*n+r]; + j = r; + } + } + + if(j != k) + { + SWAP_ROWS_F32(pA,k,j); + SWAP_COLS_F32(pA,k,j); + } + + + pp[k] = j; + + a = pA[k*n+k]; + + if (fabs(a) < 1.0e-8) + { + + fullRank = 0; + break; + } + + for(int w=k+1;wpData[row*n+col]=0.0; + } + } + } + + for(int row=0; row < n;row++) + { + for(int col=row+1; col < n;col++) + { + pl->pData[row*n+col] = 0.0; + } + } + + for(int d=0; d < diag;d++) + { + pd->pData[d*n+d] = pl->pData[d*n+d]; + pl->pData[d*n+d] = 1.0; + } + + status = RISCV_MATH_SUCCESS; + + } + + + /* Return to application */ + return (status); +} + +/// @private +#define SWAP_ROWS_F64(A,i,j) \ + for(int w=0;w < n; w++) \ + { \ + float64_t tmp; \ + tmp = A[i*n + w]; \ + A[i*n + w] = A[j*n + w];\ + A[j*n + w] = tmp; \ + } +/// @private +#define SWAP_COLS_F64(A,i,j) \ + for(int w=0;w < n; w++) \ + { \ + float64_t tmp; \ + tmp = A[w*n + i]; \ + A[w*n + i] = A[w*n + j];\ + A[w*n + j] = tmp; \ + } + +riscv_status ref_mat_ldlt_f64( + const riscv_matrix_instance_f64 * pSrc, + riscv_matrix_instance_f64 * pl, + riscv_matrix_instance_f64 * pd, + uint16_t * pp) +{ + + riscv_status status; /* status of matrix inverse */ + { + + const int n=pSrc->numRows; + int fullRank = 1, diag,k; + float64_t *pA; + + memcpy(pl->pData,pSrc->pData,n*n*sizeof(float64_t)); + pA = pl->pData; + + for(int k=0;k < n; k++) + { + pp[k] = k; + } + + + for(k=0;k < n; k++) + { + /* Find pivot */ + float64_t m=F64_MIN,a; + int j=k; + + + for(int r=k;r m) + { + m = pA[r*n+r]; + j = r; + } + } + + if(j != k) + { + SWAP_ROWS_F64(pA,k,j); + SWAP_COLS_F64(pA,k,j); + } + + + pp[k] = j; + + a = pA[k*n+k]; + + if (fabs(a) < 1.0e-18) + { + + fullRank = 0; + break; + } + + for(int w=k+1;wpData[row*n+col]=0.0; + } + } + } + + for(int row=0; row < n;row++) + { + for(int col=row+1; col < n;col++) + { + pl->pData[row*n+col] = 0.0; + } + } + + for(int d=0; d < diag;d++) + { + pd->pData[d*n+d] = pl->pData[d*n+d]; + pl->pData[d*n+d] = 1.0; + } + + status = RISCV_MATH_SUCCESS; + + } + + + /* Return to application */ + return (status); +} \ No newline at end of file diff --git a/examples/dsp/MatrixFunctions_f32Part/mat_lower_solver.c b/examples/dsp/MatrixFunctions_f32Part/mat_lower_solver.c new file mode 100644 index 00000000..c06f6aaa --- /dev/null +++ b/examples/dsp/MatrixFunctions_f32Part/mat_lower_solver.c @@ -0,0 +1,118 @@ +#include "ref.h" + +riscv_status ref_mat_solve_lower_triangular_f32( + const riscv_matrix_instance_f32 * lt, + const riscv_matrix_instance_f32 * a, + riscv_matrix_instance_f32 * dst) + { + riscv_status status; /* status of matrix inverse */ + { + /* a1 b1 c1 x1 = a1 + b2 c2 x2 a2 + c3 x3 a3 + + x3 = a3 / c3 + x2 = (a2 - c2 x3) / b2 + + */ + int i,j,k,n; + + n = dst->numRows; + + float32_t *pX = dst->pData; + float32_t *pLT = lt->pData; + float32_t *pA = a->pData; + + float32_t *lt_row; + float32_t *a_col; + + for(j=0; j < n; j ++) + { + a_col = &pA[j]; + + for(i=0; i < n ; i++) + { + lt_row = &pLT[n*i]; + + float32_t tmp=a_col[i * n]; + + for(k=0; k < i; k++) + { + tmp -= lt_row[k] * pX[n*k+j]; + } + + if (lt_row[i]==0.0f) + { + return(RISCV_MATH_SINGULAR); + } + tmp = tmp / lt_row[i]; + pX[i*n+j] = tmp; + } + + } + status = RISCV_MATH_SUCCESS; + + } + + /* Return to application */ + return (status); +} + + riscv_status ref_mat_solve_lower_triangular_f64( + const riscv_matrix_instance_f64 * lt, + const riscv_matrix_instance_f64 * a, + riscv_matrix_instance_f64 * dst) + { + riscv_status status; /* status of matrix inverse */ + + { + /* a1 b1 c1 x1 = a1 + b2 c2 x2 a2 + c3 x3 a3 + + x3 = a3 / c3 + x2 = (a2 - c2 x3) / b2 + + */ + int i,j,k,n; + + n = dst->numRows; + + float64_t *pX = dst->pData; + float64_t *pLT = lt->pData; + float64_t *pA = a->pData; + + float64_t *lt_row; + float64_t *a_col; + + for(j=0; j < n; j ++) + { + a_col = &pA[j]; + + for(i=0; i < n ; i++) + { + lt_row = &pLT[n*i]; + + float64_t tmp=a_col[i * n]; + + for(k=0; k < i; k++) + { + tmp -= lt_row[k] * pX[n*k+j]; + } + + if (lt_row[i]==0.0f) + { + return(RISCV_MATH_SINGULAR); + } + tmp = tmp / lt_row[i]; + pX[i*n+j] = tmp; + } + + } + status = RISCV_MATH_SUCCESS; + + } + + /* Return to application */ + return (status); +} \ No newline at end of file diff --git a/examples/dsp/MatrixFunctions_f32Part/mat_mult.c b/examples/dsp/MatrixFunctions_f32Part/mat_mult.c new file mode 100644 index 00000000..59ab8217 --- /dev/null +++ b/examples/dsp/MatrixFunctions_f32Part/mat_mult.c @@ -0,0 +1,82 @@ +#include "ref.h" + +riscv_status ref_mat_mult_f32(const riscv_matrix_instance_f32 *pSrcA, + const riscv_matrix_instance_f32 *pSrcB, + riscv_matrix_instance_f32 *pDst) +{ + uint32_t r, c, i, outR, outC, innerSize; + float32_t sum; + + outR = pSrcA->numRows; + outC = pSrcB->numCols; + innerSize = pSrcA->numCols; + + for (r = 0; r < outR; r++) { + for (c = 0; c < outC; c++) { + sum = 0; + + for (i = 0; i < innerSize; i++) { + sum += pSrcA->pData[r * innerSize + i] * + pSrcB->pData[i * outC + c]; + } + + pDst->pData[r * outC + c] = sum; + } + } + + return RISCV_MATH_SUCCESS; +} + +riscv_status ref_mat_mult_q31(const riscv_matrix_instance_q31 *pSrcA, + const riscv_matrix_instance_q31 *pSrcB, + riscv_matrix_instance_q31 *pDst) +{ + uint32_t r, c, i, outR, outC, innerSize; + q63_t sum; + + outR = pSrcA->numRows; + outC = pSrcB->numCols; + innerSize = pSrcA->numCols; + + for (r = 0; r < outR; r++) { + for (c = 0; c < outC; c++) { + sum = 0; + + for (i = 0; i < innerSize; i++) { + sum += (q63_t)(pSrcA->pData[r * innerSize + i]) * + pSrcB->pData[i * outC + c]; + } + + pDst->pData[r * outC + c] = ref_sat_q31(sum >> 31); + } + } + + return RISCV_MATH_SUCCESS; +} + +riscv_status ref_mat_mult_q15(const riscv_matrix_instance_q15 *pSrcA, + const riscv_matrix_instance_q15 *pSrcB, + riscv_matrix_instance_q15 *pDst) +{ + uint32_t r, c, i, outR, outC, innerSize; + q63_t sum; + + outR = pSrcA->numRows; + outC = pSrcB->numCols; + innerSize = pSrcA->numCols; + + for (r = 0; r < outR; r++) { + for (c = 0; c < outC; c++) { + sum = 0; + + for (i = 0; i < innerSize; i++) { + sum += (q31_t)(pSrcA->pData[r * innerSize + i]) * + pSrcB->pData[i * outC + c]; + } + + pDst->pData[r * outC + c] = ref_sat_q15(sum >> 15); + } + } + + return RISCV_MATH_SUCCESS; +} diff --git a/examples/dsp/MatrixFunctions_f32Part/mat_scale.c b/examples/dsp/MatrixFunctions_f32Part/mat_scale.c new file mode 100644 index 00000000..b72308fa --- /dev/null +++ b/examples/dsp/MatrixFunctions_f32Part/mat_scale.c @@ -0,0 +1,54 @@ +#include "ref.h" + +riscv_status ref_mat_scale_f32(const riscv_matrix_instance_f32 *pSrc, + float32_t scale, riscv_matrix_instance_f32 *pDst) +{ + uint32_t i; + uint32_t numSamples; /* total number of elements in the matrix */ + + /* Total number of samples in the input matrix */ + numSamples = (uint32_t)pSrc->numRows * pSrc->numCols; + + for (i = 0; i < numSamples; i++) { + pDst->pData[i] = pSrc->pData[i] * scale; + } + + return RISCV_MATH_SUCCESS; +} + +riscv_status ref_mat_scale_q31(const riscv_matrix_instance_q31 *pSrc, q31_t scale, + int32_t shift, riscv_matrix_instance_q31 *pDst) +{ + uint32_t i; + uint32_t numSamples; /* total number of elements in the matrix */ + int32_t totShift = shift + 1; + q31_t tmp; + + /* Total number of samples in the input matrix */ + numSamples = (uint32_t)pSrc->numRows * pSrc->numCols; + + for (i = 0; i < numSamples; i++) { + tmp = ((q63_t)pSrc->pData[i] * scale) >> 32; + pDst->pData[i] = ref_sat_q31((q63_t)tmp << totShift); + } + + return RISCV_MATH_SUCCESS; +} + +riscv_status ref_mat_scale_q15(const riscv_matrix_instance_q15 *pSrc, q15_t scale, + int32_t shift, riscv_matrix_instance_q15 *pDst) +{ + uint32_t i; + uint32_t numSamples; /* total number of elements in the matrix */ + int32_t totShift = 15 - shift; + + /* Total number of samples in the input matrix */ + numSamples = (uint32_t)pSrc->numRows * pSrc->numCols; + + for (i = 0; i < numSamples; i++) { + pDst->pData[i] = + ref_sat_q15(((q31_t)pSrc->pData[i] * scale) >> totShift); + } + + return RISCV_MATH_SUCCESS; +} diff --git a/examples/dsp/MatrixFunctions_f32Part/mat_sub.c b/examples/dsp/MatrixFunctions_f32Part/mat_sub.c new file mode 100644 index 00000000..339e86ae --- /dev/null +++ b/examples/dsp/MatrixFunctions_f32Part/mat_sub.c @@ -0,0 +1,53 @@ +#include "ref.h" +//#include "../HelperFunctions/ref_helper.c" + +riscv_status ref_mat_sub_f32(const riscv_matrix_instance_f32 *pSrcA, + const riscv_matrix_instance_f32 *pSrcB, + riscv_matrix_instance_f32 *pDst) +{ + uint32_t i; + uint32_t numSamples; /* total number of elements in the matrix */ + + /* Total number of samples in the input matrix */ + numSamples = (uint32_t)pSrcA->numRows * pSrcA->numCols; + + for (i = 0; i < numSamples; i++) { + pDst->pData[i] = pSrcA->pData[i] - pSrcB->pData[i]; + } + + return RISCV_MATH_SUCCESS; +} + +riscv_status ref_mat_sub_q31(const riscv_matrix_instance_q31 *pSrcA, + const riscv_matrix_instance_q31 *pSrcB, + riscv_matrix_instance_q31 *pDst) +{ + uint32_t i; + uint32_t numSamples; /* total number of elements in the matrix */ + + /* Total number of samples in the input matrix */ + numSamples = (uint32_t)pSrcA->numRows * pSrcA->numCols; + + for (i = 0; i < numSamples; i++) { + pDst->pData[i] = ref_sat_q31((q63_t)pSrcA->pData[i] - pSrcB->pData[i]); + } + + return RISCV_MATH_SUCCESS; +} + +riscv_status ref_mat_sub_q15(const riscv_matrix_instance_q15 *pSrcA, + const riscv_matrix_instance_q15 *pSrcB, + riscv_matrix_instance_q15 *pDst) +{ + uint32_t i; + uint32_t numSamples; /* total number of elements in the matrix */ + + /* Total number of samples in the input matrix */ + numSamples = (uint32_t)pSrcA->numRows * pSrcA->numCols; + + for (i = 0; i < numSamples; i++) { + pDst->pData[i] = ref_sat_q15((q31_t)pSrcA->pData[i] - pSrcB->pData[i]); + } + + return RISCV_MATH_SUCCESS; +} diff --git a/examples/dsp/MatrixFunctions_f32Part/mat_trans.c b/examples/dsp/MatrixFunctions_f32Part/mat_trans.c new file mode 100644 index 00000000..8c6c9348 --- /dev/null +++ b/examples/dsp/MatrixFunctions_f32Part/mat_trans.c @@ -0,0 +1,65 @@ +#include "ref.h" + +riscv_status ref_mat_trans_f64(const riscv_matrix_instance_f64 *pSrc, + riscv_matrix_instance_f64 *pDst) +{ + uint64_t r, c; + uint64_t numR = pSrc->numRows; + uint64_t numC = pSrc->numCols; + + for (r = 0; r < numR; r++) { + for (c = 0; c < numC; c++) { + pDst->pData[c * numR + r] = pSrc->pData[r * numC + c]; + } + } + + return RISCV_MATH_SUCCESS; +} + +riscv_status ref_mat_trans_f32(const riscv_matrix_instance_f32 *pSrc, + riscv_matrix_instance_f32 *pDst) +{ + uint32_t r, c; + uint32_t numR = pSrc->numRows; + uint32_t numC = pSrc->numCols; + + for (r = 0; r < numR; r++) { + for (c = 0; c < numC; c++) { + pDst->pData[c * numR + r] = pSrc->pData[r * numC + c]; + } + } + + return RISCV_MATH_SUCCESS; +} + +riscv_status ref_mat_trans_q31(const riscv_matrix_instance_q31 *pSrc, + riscv_matrix_instance_q31 *pDst) +{ + uint32_t r, c; + uint32_t numR = pSrc->numRows; + uint32_t numC = pSrc->numCols; + + for (r = 0; r < numR; r++) { + for (c = 0; c < numC; c++) { + pDst->pData[c * numR + r] = pSrc->pData[r * numC + c]; + } + } + + return RISCV_MATH_SUCCESS; +} + +riscv_status ref_mat_trans_q15(const riscv_matrix_instance_q15 *pSrc, + riscv_matrix_instance_q15 *pDst) +{ + uint32_t r, c; + uint32_t numR = pSrc->numRows; + uint32_t numC = pSrc->numCols; + + for (r = 0; r < numR; r++) { + for (c = 0; c < numC; c++) { + pDst->pData[c * numR + r] = pSrc->pData[r * numC + c]; + } + } + + return RISCV_MATH_SUCCESS; +} diff --git a/examples/dsp/MatrixFunctions_f32Part/mat_upper_solver.c b/examples/dsp/MatrixFunctions_f32Part/mat_upper_solver.c new file mode 100644 index 00000000..f5c5169f --- /dev/null +++ b/examples/dsp/MatrixFunctions_f32Part/mat_upper_solver.c @@ -0,0 +1,105 @@ +#include "ref.h" + +riscv_status ref_mat_solve_upper_triangular_f32( + const riscv_matrix_instance_f32 * ut, + const riscv_matrix_instance_f32 * a, + riscv_matrix_instance_f32 * dst) +{ +riscv_status status; /* status of matrix inverse */ + { + int i,j,k,n; + + n = dst->numRows; + + float32_t *pX = dst->pData; + float32_t *pUT = ut->pData; + float32_t *pA = a->pData; + + float32_t *ut_row; + float32_t *a_col; + + for(j=0; j < n; j ++) + { + a_col = &pA[j]; + + for(i=n-1; i >= 0 ; i--) + { + ut_row = &pUT[n*i]; + + float32_t tmp=a_col[i * n]; + + for(k=n-1; k > i; k--) + { + tmp -= ut_row[k] * pX[n*k+j]; + } + + if (ut_row[i]==0.0f) + { + return(RISCV_MATH_SINGULAR); + } + tmp = tmp / ut_row[i]; + pX[i*n+j] = tmp; + } + + } + status = RISCV_MATH_SUCCESS; + + } + + + /* Return to application */ + return (status); +} + +riscv_status ref_mat_solve_upper_triangular_f64( + const riscv_matrix_instance_f64 * ut, + const riscv_matrix_instance_f64 * a, + riscv_matrix_instance_f64 * dst) +{ +riscv_status status; /* status of matrix inverse */ + + { + + int i,j,k,n; + + n = dst->numRows; + + float64_t *pX = dst->pData; + float64_t *pUT = ut->pData; + float64_t *pA = a->pData; + + float64_t *ut_row; + float64_t *a_col; + + for(j=0; j < n; j ++) + { + a_col = &pA[j]; + + for(i=n-1; i >= 0 ; i--) + { + ut_row = &pUT[n*i]; + + float64_t tmp=a_col[i * n]; + + for(k=n-1; k > i; k--) + { + tmp -= ut_row[k] * pX[n*k+j]; + } + + if (ut_row[i]==0.0f) + { + return(RISCV_MATH_SINGULAR); + } + tmp = tmp / ut_row[i]; + pX[i*n+j] = tmp; + } + + } + status = RISCV_MATH_SUCCESS; + + } + + + /* Return to application */ + return (status); +} \ No newline at end of file diff --git a/examples/dsp/MatrixFunctions_q15Part/CMakeLists.txt b/examples/dsp/MatrixFunctions_q15Part/CMakeLists.txt new file mode 100644 index 00000000..3c131064 --- /dev/null +++ b/examples/dsp/MatrixFunctions_q15Part/CMakeLists.txt @@ -0,0 +1,6 @@ +set(TARGET_REQUIRED_PRIVATE_INCLUDE ${CMAKE_CURRENT_SOURCE_DIR} ${CMAKE_CURRENT_SOURCE_DIR}/..) +list(APPEND TARGET_REQUIRED_SRCS mat_add.c mat_cmplx_mult.c mat_inverse.c) +list(APPEND TARGET_REQUIRED_SRCS mat_mult.c mat_scale.c mat_sub.c mat_trans.c) +set(TARGET_REQUIRED_LIBS nmsis) +set(mains main.c) +generate_bin() \ No newline at end of file diff --git a/examples/dsp/MatrixFunctions_q15Part/array.h b/examples/dsp/MatrixFunctions_q15Part/array.h new file mode 100644 index 00000000..6062e309 --- /dev/null +++ b/examples/dsp/MatrixFunctions_q15Part/array.h @@ -0,0 +1,13 @@ +// Array for MatrixFunctions q15Part +#define ROWS 64 +#define COLUMNS 64 + +/* clang-format off */ +q15_t q15_a_array[ROWS * COLUMNS] = { +32,12,94,6995,4800,6409,5579,6534,5552,7353,593,1000,282,1891,171,7098,481,645,357,737,636,782,941,958,208,164,740,10,53,54,87,49,40,68,75,53,35,15,59,27,5,76,25,45,69,36,74,40,69,71,45,2,34,43,28,20,83,43,89,40,77,40,81,76,38,22,80,95,33,68,44,84,77,17,87,99,52,89,59,16,20,41,75,83,79,32,54,9,12,14,68,50,19,50,15,6,86,57,93,70}; +q15_t q15_b_array[ROWS * COLUMNS] = { +59,82,88,99,1,87,620,99,53,48,81,23,50,91,58,85,74,59,25,67,9,63,67,73,90,99,77,59,93,59,2,13,87,49,85,21,56,63,4,62,37,5,49,20,13,21,15,19,5,64,29,54,70,50,54,45,13,50,86,88,28,21,57,65,42,21,95,9,11,15,17,63,58,6,94,73,74,7,87,94,99,86,79,52,18,40,14,4,94,31,30,34,47,65,3,85,56,86,35,4559,82,88,99,1,87,62,99,53,48,81,23,50,91,58,85,74,59,25,67,9,63,67,73,90,99,77,59,93,59,2,13,87,49,85,21,56,63,4,62,37,5,49,20,13,21,15,19,5,64,29,54,70,50,54,45,13,50,86,88,28,21,57,65,42,21,95,9,11,15,17,63,58,6,94,73,74,7,87,94,99,86,79,52,18,40,14,4,94,31,30,34,47,65,3,85,56,86,35,45}; +/* clang-format on */ + q15_t q15_output[ROWS * COLUMNS]; + q15_t q15_output_back[ROWS * COLUMNS]; + q15_t q15_output_ref[ROWS * COLUMNS]; \ No newline at end of file diff --git a/examples/dsp/MatrixFunctions_q15Part/main.c b/examples/dsp/MatrixFunctions_q15Part/main.c new file mode 100644 index 00000000..76a8e9dd --- /dev/null +++ b/examples/dsp/MatrixFunctions_q15Part/main.c @@ -0,0 +1,151 @@ +// +// Created by lujun on 19-6-28. +// +// This contains f32, q31 and q15 versions of matrix +// each one has it's own function. +// All function can be found in main function. +// If you don't want to use it, then comment it. +#include "riscv_math.h" +#include "array.h" +#include +#include +#include "../common.h" + +#include "../HelperFunctions/math_helper.c" +#include "../HelperFunctions/ref_helper.c" + +#include +#define DELTAF32 (0.05f) +#define DELTAQ31 (63) +#define DELTAQ15 (1) +#define DELTAQ7 (1) + +int test_flag_error = 0; + +int DSP_matrix_q15(void) +{ + riscv_matrix_instance_q15 q15_A; + riscv_matrix_instance_q15 q15_B; + riscv_matrix_instance_q15 q15_ref; + riscv_matrix_instance_q15 q15_des; + int i; + + // **************** f32 ********************* + + riscv_mat_init_q15(&q15_A, ROWS, COLUMNS, (q15_t *)q15_a_array); + riscv_mat_init_q15(&q15_B, ROWS, COLUMNS, (q15_t *)q15_b_array); + riscv_mat_init_q15(&q15_des, ROWS, COLUMNS, q15_output); + riscv_mat_init_q15(&q15_ref, ROWS, COLUMNS, q15_output_ref); + + // **************** q15 ********************* + // add + BENCH_START(riscv_mat_add_q15); + riscv_mat_add_q15(&q15_A, &q15_B, &q15_des); + BENCH_END(riscv_mat_add_q15); + ref_mat_add_q15(&q15_A, &q15_B, &q15_ref); + for (int i = 0; i < (ROWS * COLUMNS); i++) + if (abs(q15_output[i] - q15_output_ref[i]) > DELTAQ15) { + BENCH_ERROR(riscv_mat_add_q15); + printf("index: %d,expect: %x, actual: %x\n", i, q15_output_ref[i], + q15_output[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_mat_add_q15); + // mult + BENCH_START(riscv_mat_mult_q15); + riscv_mat_mult_q15(&q15_A, &q15_B, &q15_des, q15_output_back); + BENCH_END(riscv_mat_mult_q15); + ref_mat_mult_q15(&q15_A, &q15_B, &q15_ref); + for (int i = 0; i < 100; i++) + if (abs(q15_output[i] - q15_output_ref[i]) > DELTAQ15) { + BENCH_ERROR(riscv_mat_mult_q15); + printf("index: %d,expect: %x, actual: %x\t", i, q15_output_ref[i], + q15_output[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_mat_mult_q15); + // sub + BENCH_START(riscv_mat_sub_q15); + riscv_mat_sub_q15(&q15_A, &q15_B, &q15_des); + BENCH_END(riscv_mat_sub_q15); + ref_mat_sub_q15(&q15_A, &q15_B, &q15_ref); + for (int i = 0; i < (ROWS * COLUMNS); i++) + if (abs(q15_output[i] - q15_output_ref[i]) > DELTAQ15) { + BENCH_ERROR(riscv_mat_sub_q15); + printf("index: %d,expect: %x, actual: %x\n", i, q15_output_ref[i], + q15_output[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_mat_sub_q15); + // trans + BENCH_START(riscv_mat_trans_q15); + riscv_mat_trans_q15(&q15_A, &q15_des); + BENCH_END(riscv_mat_trans_q15); + ref_mat_trans_q15(&q15_A, &q15_ref); + for (int i = 0; i < (ROWS * COLUMNS); i++) + if (abs(q15_output[i] - q15_output_ref[i]) > DELTAQ15) { + BENCH_ERROR(riscv_mat_trans_q15); + printf("index: %d,expect: %x, actual: %x\n", i, q15_output_ref[i], + q15_output[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_mat_trans_q15); + // scale + BENCH_START(riscv_mat_scale_q15); + riscv_mat_scale_q15(&q15_A, 8, 2, &q15_des); + BENCH_END(riscv_mat_scale_q15); + ref_mat_scale_q15(&q15_A, 8, 2, &q15_ref); + for (int i = 0; i < (ROWS * COLUMNS); i++) + if (abs(q15_output[i] - q15_output_ref[i]) > DELTAQ15) { + BENCH_ERROR(riscv_mat_scale_q15); + printf("index: %d,expect: %x, actual: %x\n", i, q15_output_ref[i], + q15_output[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_mat_scale_q15); + // cmplx_mult + riscv_mat_init_q15(&q15_A, 32, 32, (q15_t *)q15_a_array); + riscv_mat_init_q15(&q15_B, 32, 32, (q15_t *)q15_b_array); + riscv_mat_init_q15(&q15_des, 32, 32, q15_output); + riscv_mat_init_q15(&q15_ref, 32, 32, q15_output_ref); + BENCH_START(riscv_mat_cmplx_mult_q15); + riscv_mat_cmplx_mult_q15(&q15_A, &q15_B, &q15_des, q15_output_back); + BENCH_END(riscv_mat_cmplx_mult_q15); + ref_mat_cmplx_mult_q15(&q15_A, &q15_B, &q15_ref); + for (int i = 0; i < (32 * 32); i++) + if (abs(q15_output[i] - q15_output_ref[i]) > DELTAQ15) { + BENCH_ERROR(riscv_mat_cmplx_mult_q15); + printf("index: %d,expect: %x, actual: %x\n", i, q15_output_ref[i], + q15_output[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_mat_cmplx_mult_q15); + // mult_fast + BENCH_START(riscv_mat_mult_fast_q15); + riscv_mat_mult_fast_q15(&q15_A, &q15_B, &q15_des, q15_output_back); + BENCH_END(riscv_mat_mult_fast_q15); + ref_mat_mult_fast_q15(&q15_A, &q15_B, &q15_ref); + for (int i = 0; i < (10 * 10); i++) + if (abs(q15_output[i] - q15_output_ref[i]) > DELTAQ15) { + BENCH_ERROR(riscv_mat_mult_fast_q15); + printf("index: %d,expect: %x, actual: %x\n", i, q15_output_ref[i], + q15_output[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_mat_mult_fast_q15); + printf("all tests are passed,well done!\n"); +} + +int main() +{ + BENCH_INIT; + DSP_matrix_q15(); + BENCH_FINISH; + if (test_flag_error) { + printf("test error apprears, please recheck.\n"); + return 1; + } else { + printf("all test are passed. Well done!\n"); + } + return 0; +} diff --git a/examples/dsp/MatrixFunctions_q15Part/mat_add.c b/examples/dsp/MatrixFunctions_q15Part/mat_add.c new file mode 100644 index 00000000..eccec2e0 --- /dev/null +++ b/examples/dsp/MatrixFunctions_q15Part/mat_add.c @@ -0,0 +1,52 @@ +#include "ref.h" + +riscv_status ref_mat_add_f32(const riscv_matrix_instance_f32 *pSrcA, + const riscv_matrix_instance_f32 *pSrcB, + riscv_matrix_instance_f32 *pDst) +{ + uint32_t i; + uint32_t numSamples; /* total number of elements in the matrix */ + + /* Total number of samples in the input matrix */ + numSamples = (uint32_t)pSrcA->numRows * pSrcA->numCols; + + for (i = 0; i < numSamples; i++) { + pDst->pData[i] = pSrcA->pData[i] + pSrcB->pData[i]; + } + + return RISCV_MATH_SUCCESS; +} + +riscv_status ref_mat_add_q31(const riscv_matrix_instance_q31 *pSrcA, + const riscv_matrix_instance_q31 *pSrcB, + riscv_matrix_instance_q31 *pDst) +{ + uint32_t i; + uint32_t numSamples; /* total number of elements in the matrix */ + + /* Total number of samples in the input matrix */ + numSamples = (uint32_t)pSrcA->numRows * pSrcA->numCols; + + for (i = 0; i < numSamples; i++) { + pDst->pData[i] = ref_sat_q31((q63_t)pSrcA->pData[i] + pSrcB->pData[i]); + } + + return RISCV_MATH_SUCCESS; +} + +riscv_status ref_mat_add_q15(const riscv_matrix_instance_q15 *pSrcA, + const riscv_matrix_instance_q15 *pSrcB, + riscv_matrix_instance_q15 *pDst) +{ + uint32_t i; + uint32_t numSamples; /* total number of elements in the matrix */ + + /* Total number of samples in the input matrix */ + numSamples = (uint32_t)pSrcA->numRows * pSrcA->numCols; + + for (i = 0; i < numSamples; i++) { + pDst->pData[i] = ref_sat_q15((q31_t)pSrcA->pData[i] + pSrcB->pData[i]); + } + + return RISCV_MATH_SUCCESS; +} diff --git a/examples/dsp/MatrixFunctions_q15Part/mat_cmplx_mult.c b/examples/dsp/MatrixFunctions_q15Part/mat_cmplx_mult.c new file mode 100644 index 00000000..a9a99cd1 --- /dev/null +++ b/examples/dsp/MatrixFunctions_q15Part/mat_cmplx_mult.c @@ -0,0 +1,114 @@ +#include "ref.h" + +//#include "riscv_math.h" +//#include "../common.h" + +//#include "../HelperFunctions/ref_helper.c" +//#include "FastMathFunctions.c" +// /#include +#define DELTA (0.05f) + +riscv_status ref_mat_cmplx_mult_f32(const riscv_matrix_instance_f32 *pSrcA, + const riscv_matrix_instance_f32 *pSrcB, + riscv_matrix_instance_f32 *pDst) +{ + uint32_t r, c, i, outR, outC, innerSize; + float32_t sumR, sumI; + float32_t a0, b0, c0, d0; + + outR = pSrcA->numRows; + outC = pSrcB->numCols; + innerSize = pSrcA->numCols; + + for (r = 0; r < outR; r++) { + for (c = 0; c < outC; c++) { + sumR = 0; + sumI = 0; + + for (i = 0; i < innerSize; i++) { + a0 = pSrcA->pData[2 * (r * innerSize + i) + 0]; + b0 = pSrcA->pData[2 * (r * innerSize + i) + 1]; + c0 = pSrcB->pData[2 * (i * outC + c) + 0]; + d0 = pSrcB->pData[2 * (i * outC + c) + 1]; + + sumR += a0 * c0 - b0 * d0; + sumI += b0 * c0 + a0 * d0; + } + + pDst->pData[2 * (r * outC + c) + 0] = sumR; + pDst->pData[2 * (r * outC + c) + 1] = sumI; + } + } + + return RISCV_MATH_SUCCESS; +} + +riscv_status ref_mat_cmplx_mult_q31(const riscv_matrix_instance_q31 *pSrcA, + const riscv_matrix_instance_q31 *pSrcB, + riscv_matrix_instance_q31 *pDst) +{ + uint32_t r, c, i, outR, outC, innerSize; + q63_t sumR, sumI; + q31_t a0, b0, c0, d0; + + outR = pSrcA->numRows; + outC = pSrcB->numCols; + innerSize = pSrcA->numCols; + + for (r = 0; r < outR; r++) { + for (c = 0; c < outC; c++) { + sumR = 0; + sumI = 0; + + for (i = 0; i < innerSize; i++) { + a0 = pSrcA->pData[2 * (r * innerSize + i) + 0]; + b0 = pSrcA->pData[2 * (r * innerSize + i) + 1]; + c0 = pSrcB->pData[2 * (i * outC + c) + 0]; + d0 = pSrcB->pData[2 * (i * outC + c) + 1]; + + sumR += (q63_t)a0 * c0 - (q63_t)b0 * d0; + sumI += (q63_t)b0 * c0 + (q63_t)a0 * d0; + } + + pDst->pData[2 * (r * outC + c) + 0] = ref_sat_q31(sumR >> 31); + pDst->pData[2 * (r * outC + c) + 1] = ref_sat_q31(sumI >> 31); + } + } + + return RISCV_MATH_SUCCESS; +} + +riscv_status ref_mat_cmplx_mult_q15(const riscv_matrix_instance_q15 *pSrcA, + const riscv_matrix_instance_q15 *pSrcB, + riscv_matrix_instance_q15 *pDst) +{ + uint32_t r, c, i, outR, outC, innerSize; + q63_t sumR, sumI; + q15_t a0, b0, c0, d0; + + outR = pSrcA->numRows; + outC = pSrcB->numCols; + innerSize = pSrcA->numCols; + + for (r = 0; r < outR; r++) { + for (c = 0; c < outC; c++) { + sumR = 0; + sumI = 0; + + for (i = 0; i < innerSize; i++) { + a0 = pSrcA->pData[2 * (r * innerSize + i) + 0]; + b0 = pSrcA->pData[2 * (r * innerSize + i) + 1]; + c0 = pSrcB->pData[2 * (i * outC + c) + 0]; + d0 = pSrcB->pData[2 * (i * outC + c) + 1]; + + sumR += (q31_t)a0 * c0 - (q31_t)b0 * d0; + sumI += (q31_t)b0 * c0 + (q31_t)a0 * d0; + } + + pDst->pData[2 * (r * outC + c) + 0] = ref_sat_q15(sumR >> 15); + pDst->pData[2 * (r * outC + c) + 1] = ref_sat_q15(sumI >> 15); + } + } + + return RISCV_MATH_SUCCESS; +} diff --git a/examples/dsp/MatrixFunctions_q15Part/mat_inverse.c b/examples/dsp/MatrixFunctions_q15Part/mat_inverse.c new file mode 100644 index 00000000..696ce4fc --- /dev/null +++ b/examples/dsp/MatrixFunctions_q15Part/mat_inverse.c @@ -0,0 +1,54 @@ +#include "ref.h" + +riscv_status ref_mat_inverse_f32(const riscv_matrix_instance_f32 *pSrc, + riscv_matrix_instance_f32 *pDst) +{ + float32_t det; + uint32_t i, size; + riscv_matrix_instance_f32 tmp; + + tmp.numCols = pSrc->numCols; + tmp.numRows = pSrc->numRows; + tmp.pData = scratchArray; + + det = ref_detrm(pSrc->pData, scratchArray, pSrc->numCols); + + size = pSrc->numCols * pSrc->numCols; + + ref_cofact(pSrc->pData, scratchArray, scratchArray + size, pSrc->numCols); + + ref_mat_trans_f32(&tmp, pDst); + + for (i = 0; i < size; i++) { + pDst->pData[i] /= det; + } + + return RISCV_MATH_SUCCESS; +} + +riscv_status ref_mat_inverse_f64(const riscv_matrix_instance_f64 *pSrc, + riscv_matrix_instance_f64 *pDst) +{ + float64_t det; + uint32_t i, size; + riscv_matrix_instance_f64 tmp; + + tmp.numCols = pSrc->numCols; + tmp.numRows = pSrc->numRows; + tmp.pData = (float64_t *)scratchArray; + + det = ref_detrm64(pSrc->pData, (float64_t *)scratchArray, pSrc->numCols); + + size = pSrc->numCols * pSrc->numCols; + + ref_cofact64(pSrc->pData, (float64_t *)scratchArray, + (float64_t *)scratchArray + size, pSrc->numCols); + + ref_mat_trans_f64(&tmp, pDst); + + for (i = 0; i < size; i++) { + pDst->pData[i] /= det; + } + + return RISCV_MATH_SUCCESS; +} diff --git a/examples/dsp/MatrixFunctions_q15Part/mat_mult.c b/examples/dsp/MatrixFunctions_q15Part/mat_mult.c new file mode 100644 index 00000000..59ab8217 --- /dev/null +++ b/examples/dsp/MatrixFunctions_q15Part/mat_mult.c @@ -0,0 +1,82 @@ +#include "ref.h" + +riscv_status ref_mat_mult_f32(const riscv_matrix_instance_f32 *pSrcA, + const riscv_matrix_instance_f32 *pSrcB, + riscv_matrix_instance_f32 *pDst) +{ + uint32_t r, c, i, outR, outC, innerSize; + float32_t sum; + + outR = pSrcA->numRows; + outC = pSrcB->numCols; + innerSize = pSrcA->numCols; + + for (r = 0; r < outR; r++) { + for (c = 0; c < outC; c++) { + sum = 0; + + for (i = 0; i < innerSize; i++) { + sum += pSrcA->pData[r * innerSize + i] * + pSrcB->pData[i * outC + c]; + } + + pDst->pData[r * outC + c] = sum; + } + } + + return RISCV_MATH_SUCCESS; +} + +riscv_status ref_mat_mult_q31(const riscv_matrix_instance_q31 *pSrcA, + const riscv_matrix_instance_q31 *pSrcB, + riscv_matrix_instance_q31 *pDst) +{ + uint32_t r, c, i, outR, outC, innerSize; + q63_t sum; + + outR = pSrcA->numRows; + outC = pSrcB->numCols; + innerSize = pSrcA->numCols; + + for (r = 0; r < outR; r++) { + for (c = 0; c < outC; c++) { + sum = 0; + + for (i = 0; i < innerSize; i++) { + sum += (q63_t)(pSrcA->pData[r * innerSize + i]) * + pSrcB->pData[i * outC + c]; + } + + pDst->pData[r * outC + c] = ref_sat_q31(sum >> 31); + } + } + + return RISCV_MATH_SUCCESS; +} + +riscv_status ref_mat_mult_q15(const riscv_matrix_instance_q15 *pSrcA, + const riscv_matrix_instance_q15 *pSrcB, + riscv_matrix_instance_q15 *pDst) +{ + uint32_t r, c, i, outR, outC, innerSize; + q63_t sum; + + outR = pSrcA->numRows; + outC = pSrcB->numCols; + innerSize = pSrcA->numCols; + + for (r = 0; r < outR; r++) { + for (c = 0; c < outC; c++) { + sum = 0; + + for (i = 0; i < innerSize; i++) { + sum += (q31_t)(pSrcA->pData[r * innerSize + i]) * + pSrcB->pData[i * outC + c]; + } + + pDst->pData[r * outC + c] = ref_sat_q15(sum >> 15); + } + } + + return RISCV_MATH_SUCCESS; +} diff --git a/examples/dsp/MatrixFunctions_q15Part/mat_scale.c b/examples/dsp/MatrixFunctions_q15Part/mat_scale.c new file mode 100644 index 00000000..b72308fa --- /dev/null +++ b/examples/dsp/MatrixFunctions_q15Part/mat_scale.c @@ -0,0 +1,54 @@ +#include "ref.h" + +riscv_status ref_mat_scale_f32(const riscv_matrix_instance_f32 *pSrc, + float32_t scale, riscv_matrix_instance_f32 *pDst) +{ + uint32_t i; + uint32_t numSamples; /* total number of elements in the matrix */ + + /* Total number of samples in the input matrix */ + numSamples = (uint32_t)pSrc->numRows * pSrc->numCols; + + for (i = 0; i < numSamples; i++) { + pDst->pData[i] = pSrc->pData[i] * scale; + } + + return RISCV_MATH_SUCCESS; +} + +riscv_status ref_mat_scale_q31(const riscv_matrix_instance_q31 *pSrc, q31_t scale, + int32_t shift, riscv_matrix_instance_q31 *pDst) +{ + uint32_t i; + uint32_t numSamples; /* total number of elements in the matrix */ + int32_t totShift = shift + 1; + q31_t tmp; + + /* Total number of samples in the input matrix */ + numSamples = (uint32_t)pSrc->numRows * pSrc->numCols; + + for (i = 0; i < numSamples; i++) { + tmp = ((q63_t)pSrc->pData[i] * scale) >> 32; + pDst->pData[i] = ref_sat_q31((q63_t)tmp << totShift); + } + + return RISCV_MATH_SUCCESS; +} + +riscv_status ref_mat_scale_q15(const riscv_matrix_instance_q15 *pSrc, q15_t scale, + int32_t shift, riscv_matrix_instance_q15 *pDst) +{ + uint32_t i; + uint32_t numSamples; /* total number of elements in the matrix */ + int32_t totShift = 15 - shift; + + /* Total number of samples in the input matrix */ + numSamples = (uint32_t)pSrc->numRows * pSrc->numCols; + + for (i = 0; i < numSamples; i++) { + pDst->pData[i] = + ref_sat_q15(((q31_t)pSrc->pData[i] * scale) >> totShift); + } + + return RISCV_MATH_SUCCESS; +} diff --git a/examples/dsp/MatrixFunctions_q15Part/mat_sub.c b/examples/dsp/MatrixFunctions_q15Part/mat_sub.c new file mode 100644 index 00000000..339e86ae --- /dev/null +++ b/examples/dsp/MatrixFunctions_q15Part/mat_sub.c @@ -0,0 +1,53 @@ +#include "ref.h" +//#include "../HelperFunctions/ref_helper.c" + +riscv_status ref_mat_sub_f32(const riscv_matrix_instance_f32 *pSrcA, + const riscv_matrix_instance_f32 *pSrcB, + riscv_matrix_instance_f32 *pDst) +{ + uint32_t i; + uint32_t numSamples; /* total number of elements in the matrix */ + + /* Total number of samples in the input matrix */ + numSamples = (uint32_t)pSrcA->numRows * pSrcA->numCols; + + for (i = 0; i < numSamples; i++) { + pDst->pData[i] = pSrcA->pData[i] - pSrcB->pData[i]; + } + + return RISCV_MATH_SUCCESS; +} + +riscv_status ref_mat_sub_q31(const riscv_matrix_instance_q31 *pSrcA, + const riscv_matrix_instance_q31 *pSrcB, + riscv_matrix_instance_q31 *pDst) +{ + uint32_t i; + uint32_t numSamples; /* total number of elements in the matrix */ + + /* Total number of samples in the input matrix */ + numSamples = (uint32_t)pSrcA->numRows * pSrcA->numCols; + + for (i = 0; i < numSamples; i++) { + pDst->pData[i] = ref_sat_q31((q63_t)pSrcA->pData[i] - pSrcB->pData[i]); + } + + return RISCV_MATH_SUCCESS; +} + +riscv_status ref_mat_sub_q15(const riscv_matrix_instance_q15 *pSrcA, + const riscv_matrix_instance_q15 *pSrcB, + riscv_matrix_instance_q15 *pDst) +{ + uint32_t i; + uint32_t numSamples; /* total number of elements in the matrix */ + + /* Total number of samples in the input matrix */ + numSamples = (uint32_t)pSrcA->numRows * pSrcA->numCols; + + for (i = 0; i < numSamples; i++) { + pDst->pData[i] = ref_sat_q15((q31_t)pSrcA->pData[i] - pSrcB->pData[i]); + } + + return RISCV_MATH_SUCCESS; +} diff --git a/examples/dsp/MatrixFunctions_q15Part/mat_trans.c b/examples/dsp/MatrixFunctions_q15Part/mat_trans.c new file mode 100644 index 00000000..8c6c9348 --- /dev/null +++ b/examples/dsp/MatrixFunctions_q15Part/mat_trans.c @@ -0,0 +1,65 @@ +#include "ref.h" + +riscv_status ref_mat_trans_f64(const riscv_matrix_instance_f64 *pSrc, + riscv_matrix_instance_f64 *pDst) +{ + uint64_t r, c; + uint64_t numR = pSrc->numRows; + uint64_t numC = pSrc->numCols; + + for (r = 0; r < numR; r++) { + for (c = 0; c < numC; c++) { + pDst->pData[c * numR + r] = pSrc->pData[r * numC + c]; + } + } + + return RISCV_MATH_SUCCESS; +} + +riscv_status ref_mat_trans_f32(const riscv_matrix_instance_f32 *pSrc, + riscv_matrix_instance_f32 *pDst) +{ + uint32_t r, c; + uint32_t numR = pSrc->numRows; + uint32_t numC = pSrc->numCols; + + for (r = 0; r < numR; r++) { + for (c = 0; c < numC; c++) { + pDst->pData[c * numR + r] = pSrc->pData[r * numC + c]; + } + } + + return RISCV_MATH_SUCCESS; +} + +riscv_status ref_mat_trans_q31(const riscv_matrix_instance_q31 *pSrc, + riscv_matrix_instance_q31 *pDst) +{ + uint32_t r, c; + uint32_t numR = pSrc->numRows; + uint32_t numC = pSrc->numCols; + + for (r = 0; r < numR; r++) { + for (c = 0; c < numC; c++) { + pDst->pData[c * numR + r] = pSrc->pData[r * numC + c]; + } + } + + return RISCV_MATH_SUCCESS; +} + +riscv_status ref_mat_trans_q15(const riscv_matrix_instance_q15 *pSrc, + riscv_matrix_instance_q15 *pDst) +{ + uint32_t r, c; + uint32_t numR = pSrc->numRows; + uint32_t numC = pSrc->numCols; + + for (r = 0; r < numR; r++) { + for (c = 0; c < numC; c++) { + pDst->pData[c * numR + r] = pSrc->pData[r * numC + c]; + } + } + + return RISCV_MATH_SUCCESS; +} diff --git a/examples/dsp/MatrixFunctions_q31Part/CMakeLists.txt b/examples/dsp/MatrixFunctions_q31Part/CMakeLists.txt new file mode 100644 index 00000000..3c131064 --- /dev/null +++ b/examples/dsp/MatrixFunctions_q31Part/CMakeLists.txt @@ -0,0 +1,6 @@ +set(TARGET_REQUIRED_PRIVATE_INCLUDE ${CMAKE_CURRENT_SOURCE_DIR} ${CMAKE_CURRENT_SOURCE_DIR}/..) +list(APPEND TARGET_REQUIRED_SRCS mat_add.c mat_cmplx_mult.c mat_inverse.c) +list(APPEND TARGET_REQUIRED_SRCS mat_mult.c mat_scale.c mat_sub.c mat_trans.c) +set(TARGET_REQUIRED_LIBS nmsis) +set(mains main.c) +generate_bin() \ No newline at end of file diff --git a/examples/dsp/MatrixFunctions_q31Part/array.h b/examples/dsp/MatrixFunctions_q31Part/array.h new file mode 100644 index 00000000..96bf3661 --- /dev/null +++ b/examples/dsp/MatrixFunctions_q31Part/array.h @@ -0,0 +1,26 @@ +// Array for MatrixFunctions q31Part +#define ROWS 64 +#define COLUMNS 64 +q31_t q31_a_array[ROWS * COLUMNS] = { + 497, 1806, 789, 1963, 2068, 2245, 1352, 252, 687, 2741, 458, 2478, + 1616, 2989, 235, 1329, 320, 2886, 14, 2325, 2452, 2607, 254, 1200, + 780, 2401, 1295, 2732, 546, 792, 437, 409, 2608, 1740, 1650, 435, + 2560, 1867, 1053, 1540, 1206, 228, 720, 370, 552, 720, 1252, 149, + 2709, 2835, 1473, 1468, 1014, 2701, 1108, 334, 2341, 1170, 726, 1212, + 290, 396, 2827, 2869, 1726, 180, 705, 1060, 2464, 47, 130, 507, + 1948, 2196, 1944, 1353, 1642, 889, 2235, 567, 2061, 551, 1106, 1877, + 2341, 244, 2789, 2328, 1461, 1308, 1341, 920, 1526, 1533, 2453, 2385, + 1933, 1136, 2435, 1599}; +q31_t q31_b_array[ROWS * COLUMNS] = { + 1053, 2818, 2628, 1651, 1868, 1762, 624, 904, 1413, 692, 2533, 585, + 678, 513, 683, 1308, 934, 2771, 1291, 555, 2715, 2940, 1317, 334, + 775, 1227, 1785, 787, 1809, 2134, 666, 353, 891, 957, 1273, 1524, + 257, 788, 2404, 88, 2787, 2191, 1466, 1736, 712, 1377, 2890, 1641, + 1564, 695, 1467, 1873, 2038, 1187, 1103, 2964, 114, 2656, 2740, 2389, + 297, 786, 1007, 2040, 410, 2164, 321, 1962, 1483, 2338, 2146, 2712, + 2673, 1003, 2097, 594, 92, 2233, 1501, 1440, 2715, 1830, 1853, 2579, + 2417, 1731, 549, 720, 2660, 87, 1470, 504, 2937, 2139, 1502, 1414, + 179, 2046, 128, 215}; + q31_t q31_output[ROWS * COLUMNS]; + q31_t q31_output_back[ROWS * COLUMNS]; + q31_t q31_output_ref[ROWS * COLUMNS]; \ No newline at end of file diff --git a/examples/dsp/MatrixFunctions_q31Part/main.c b/examples/dsp/MatrixFunctions_q31Part/main.c new file mode 100644 index 00000000..00f27d64 --- /dev/null +++ b/examples/dsp/MatrixFunctions_q31Part/main.c @@ -0,0 +1,148 @@ +// +// Created by lujun on 19-6-28. +// +// This contains f32, q31 and q15 versions of matrix +// each one has it's own function. +// All function can be found in main function. +// If you don't want to use it, then comment it. +#include "riscv_math.h" +#include "array.h" +#include +#include +#include "../common.h" + +#include "../HelperFunctions/math_helper.c" +#include "../HelperFunctions/ref_helper.c" + +#include +#define DELTAF32 (0.05f) +#define DELTAQ31 (63) +#define DELTAQ15 (1) +#define DELTAQ7 (1) + +int test_flag_error = 0; + +int DSP_matrix_q31(void) +{ + riscv_matrix_instance_q31 q31_A; + riscv_matrix_instance_q31 q31_B; + riscv_matrix_instance_q31 q31_ref; + riscv_matrix_instance_q31 q31_des; + int i; + riscv_mat_init_q31(&q31_A, ROWS, COLUMNS, (q31_t *)q31_a_array); + riscv_mat_init_q31(&q31_B, ROWS, COLUMNS, (q31_t *)q31_b_array); + riscv_mat_init_q31(&q31_des, ROWS, COLUMNS, q31_output); + riscv_mat_init_q31(&q31_ref, ROWS, COLUMNS, q31_output_ref); + + // **************** q31 ********************* + // add + BENCH_START(riscv_mat_add_q31); + riscv_mat_add_q31(&q31_A, &q31_B, &q31_des); + BENCH_END(riscv_mat_add_q31); + ref_mat_add_q31(&q31_A, &q31_B, &q31_ref); + for (int i = 0; i < (ROWS * COLUMNS); i++) + if (labs(q31_output[i] - q31_output_ref[i]) > DELTAQ31) { + BENCH_ERROR(riscv_mat_add_q31); + printf("index: %d,expect: %x, actual: %x\n", i, q31_output_ref[i], + q31_output[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_mat_add_q31); + // mult + BENCH_START(riscv_mat_mult_q31); + riscv_mat_mult_q31(&q31_A, &q31_B, &q31_des); + BENCH_END(riscv_mat_mult_q31); + ref_mat_mult_q31(&q31_A, &q31_B, &q31_ref); + for (int i = 0; i < (ROWS * COLUMNS); i++) + if (labs(q31_output[i] - q31_output_ref[i]) > DELTAQ31) { + BENCH_ERROR(riscv_mat_mult_q31); + printf("index: %d,expect: %x, actual: %x\n", i, q31_output_ref[i], + q31_output[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_mat_mult_q31); + // sub + BENCH_START(riscv_mat_sub_q31); + riscv_mat_sub_q31(&q31_A, &q31_B, &q31_des); + BENCH_END(riscv_mat_sub_q31); + ref_mat_sub_q31(&q31_A, &q31_B, &q31_ref); + for (int i = 0; i < (ROWS * COLUMNS); i++) + if (labs(q31_output[i] - q31_output_ref[i]) > DELTAQ31) { + BENCH_ERROR(riscv_mat_sub_q31); + printf("index: %d,expect: %x, actual: %x\n", i, q31_output_ref[i], + q31_output[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_mat_sub_q31); + // trans + BENCH_START(riscv_mat_trans_q31); + riscv_mat_trans_q31(&q31_A, &q31_des); + BENCH_END(riscv_mat_trans_q31); + ref_mat_trans_q31(&q31_A, &q31_ref); + for (int i = 0; i < (ROWS * COLUMNS); i++) + if (labs(q31_output[i] - q31_output_ref[i]) > DELTAQ31) { + BENCH_ERROR(riscv_mat_trans_q31); + printf("index: %d,expect: %x, actual: %x\n", i, q31_output_ref[i], + q31_output[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_mat_trans_q31); + // scale + BENCH_START(riscv_mat_scale_q31); + riscv_mat_scale_q31(&q31_A, 8, 2, &q31_des); + BENCH_END(riscv_mat_scale_q31); + ref_mat_scale_q31(&q31_A, 8, 2, &q31_ref); + for (int i = 0; i < (ROWS * COLUMNS); i++) + if (labs(q31_output[i] - q31_output_ref[i]) > DELTAQ31) { + BENCH_ERROR(riscv_mat_scale_q31); + printf("index: %d,expect: %x, actual: %x\n", i, q31_output_ref[i], + q31_output[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_mat_scale_q31); + // cmplx_mult + riscv_mat_init_q31(&q31_A, 32, 32, (q31_t *)q31_a_array); + riscv_mat_init_q31(&q31_B, 32, 32, (q31_t *)q31_b_array); + riscv_mat_init_q31(&q31_des, 32, 32, q31_output); + riscv_mat_init_q31(&q31_ref, 32, 32, q31_output_ref); + BENCH_START(riscv_mat_cmplx_mult_q31); + riscv_mat_cmplx_mult_q31(&q31_A, &q31_B, &q31_des); + BENCH_END(riscv_mat_cmplx_mult_q31); + ref_mat_cmplx_mult_q31(&q31_A, &q31_B, &q31_ref); + for (int i = 0; i < (32 * 32); i++) + if (labs(q31_output[i] - q31_output_ref[i]) > DELTAQ31) { + BENCH_ERROR(riscv_mat_cmplx_mult_q31); + printf("index: %d,expect: %x, actual: %x\n", i, q31_output_ref[i], + q31_output[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_mat_cmplx_mult_q31); + // mult_fast + BENCH_START(riscv_mat_mult_fast_q31); + riscv_mat_mult_fast_q31(&q31_A, &q31_B, &q31_des); + BENCH_END(riscv_mat_mult_fast_q31); + ref_mat_mult_fast_q31(&q31_A, &q31_B, &q31_ref); + for (int i = 0; i < (ROWS * COLUMNS); i++) + if (labs(q31_output[i] - q31_output_ref[i]) > DELTAQ31) { + BENCH_ERROR(riscv_mat_mult_fast_q31); + printf("index: %d,expect: %x, actual: %x\n", i, q31_output_ref[i], + q31_output[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_mat_mult_fast_q31); + printf("all tests are passed,well done!\n"); +} + +int main() +{ + BENCH_INIT; + DSP_matrix_q31(); + BENCH_FINISH; + if (test_flag_error) { + printf("test error apprears, please recheck.\n"); + return 1; + } else { + printf("all test are passed. Well done!\n"); + } + return 0; +} diff --git a/examples/dsp/MatrixFunctions_q31Part/mat_add.c b/examples/dsp/MatrixFunctions_q31Part/mat_add.c new file mode 100644 index 00000000..eccec2e0 --- /dev/null +++ b/examples/dsp/MatrixFunctions_q31Part/mat_add.c @@ -0,0 +1,52 @@ +#include "ref.h" + +riscv_status ref_mat_add_f32(const riscv_matrix_instance_f32 *pSrcA, + const riscv_matrix_instance_f32 *pSrcB, + riscv_matrix_instance_f32 *pDst) +{ + uint32_t i; + uint32_t numSamples; /* total number of elements in the matrix */ + + /* Total number of samples in the input matrix */ + numSamples = (uint32_t)pSrcA->numRows * pSrcA->numCols; + + for (i = 0; i < numSamples; i++) { + pDst->pData[i] = pSrcA->pData[i] + pSrcB->pData[i]; + } + + return RISCV_MATH_SUCCESS; +} + +riscv_status ref_mat_add_q31(const riscv_matrix_instance_q31 *pSrcA, + const riscv_matrix_instance_q31 *pSrcB, + riscv_matrix_instance_q31 *pDst) +{ + uint32_t i; + uint32_t numSamples; /* total number of elements in the matrix */ + + /* Total number of samples in the input matrix */ + numSamples = (uint32_t)pSrcA->numRows * pSrcA->numCols; + + for (i = 0; i < numSamples; i++) { + pDst->pData[i] = ref_sat_q31((q63_t)pSrcA->pData[i] + pSrcB->pData[i]); + } + + return RISCV_MATH_SUCCESS; +} + +riscv_status ref_mat_add_q15(const riscv_matrix_instance_q15 *pSrcA, + const riscv_matrix_instance_q15 *pSrcB, + riscv_matrix_instance_q15 *pDst) +{ + uint32_t i; + uint32_t numSamples; /* total number of elements in the matrix */ + + /* Total number of samples in the input matrix */ + numSamples = (uint32_t)pSrcA->numRows * pSrcA->numCols; + + for (i = 0; i < numSamples; i++) { + pDst->pData[i] = ref_sat_q15((q31_t)pSrcA->pData[i] + pSrcB->pData[i]); + } + + return RISCV_MATH_SUCCESS; +} diff --git a/examples/dsp/MatrixFunctions_q31Part/mat_cmplx_mult.c b/examples/dsp/MatrixFunctions_q31Part/mat_cmplx_mult.c new file mode 100644 index 00000000..a9a99cd1 --- /dev/null +++ b/examples/dsp/MatrixFunctions_q31Part/mat_cmplx_mult.c @@ -0,0 +1,114 @@ +#include "ref.h" + +//#include "riscv_math.h" +//#include "../common.h" + +//#include "../HelperFunctions/ref_helper.c" +//#include "FastMathFunctions.c" +// /#include +#define DELTA (0.05f) + +riscv_status ref_mat_cmplx_mult_f32(const riscv_matrix_instance_f32 *pSrcA, + const riscv_matrix_instance_f32 *pSrcB, + riscv_matrix_instance_f32 *pDst) +{ + uint32_t r, c, i, outR, outC, innerSize; + float32_t sumR, sumI; + float32_t a0, b0, c0, d0; + + outR = pSrcA->numRows; + outC = pSrcB->numCols; + innerSize = pSrcA->numCols; + + for (r = 0; r < outR; r++) { + for (c = 0; c < outC; c++) { + sumR = 0; + sumI = 0; + + for (i = 0; i < innerSize; i++) { + a0 = pSrcA->pData[2 * (r * innerSize + i) + 0]; + b0 = pSrcA->pData[2 * (r * innerSize + i) + 1]; + c0 = pSrcB->pData[2 * (i * outC + c) + 0]; + d0 = pSrcB->pData[2 * (i * outC + c) + 1]; + + sumR += a0 * c0 - b0 * d0; + sumI += b0 * c0 + a0 * d0; + } + + pDst->pData[2 * (r * outC + c) + 0] = sumR; + pDst->pData[2 * (r * outC + c) + 1] = sumI; + } + } + + return RISCV_MATH_SUCCESS; +} + +riscv_status ref_mat_cmplx_mult_q31(const riscv_matrix_instance_q31 *pSrcA, + const riscv_matrix_instance_q31 *pSrcB, + riscv_matrix_instance_q31 *pDst) +{ + uint32_t r, c, i, outR, outC, innerSize; + q63_t sumR, sumI; + q31_t a0, b0, c0, d0; + + outR = pSrcA->numRows; + outC = pSrcB->numCols; + innerSize = pSrcA->numCols; + + for (r = 0; r < outR; r++) { + for (c = 0; c < outC; c++) { + sumR = 0; + sumI = 0; + + for (i = 0; i < innerSize; i++) { + a0 = pSrcA->pData[2 * (r * innerSize + i) + 0]; + b0 = pSrcA->pData[2 * (r * innerSize + i) + 1]; + c0 = pSrcB->pData[2 * (i * outC + c) + 0]; + d0 = pSrcB->pData[2 * (i * outC + c) + 1]; + + sumR += (q63_t)a0 * c0 - (q63_t)b0 * d0; + sumI += (q63_t)b0 * c0 + (q63_t)a0 * d0; + } + + pDst->pData[2 * (r * outC + c) + 0] = ref_sat_q31(sumR >> 31); + pDst->pData[2 * (r * outC + c) + 1] = ref_sat_q31(sumI >> 31); + } + } + + return RISCV_MATH_SUCCESS; +} + +riscv_status ref_mat_cmplx_mult_q15(const riscv_matrix_instance_q15 *pSrcA, + const riscv_matrix_instance_q15 *pSrcB, + riscv_matrix_instance_q15 *pDst) +{ + uint32_t r, c, i, outR, outC, innerSize; + q63_t sumR, sumI; + q15_t a0, b0, c0, d0; + + outR = pSrcA->numRows; + outC = pSrcB->numCols; + innerSize = pSrcA->numCols; + + for (r = 0; r < outR; r++) { + for (c = 0; c < outC; c++) { + sumR = 0; + sumI = 0; + + for (i = 0; i < innerSize; i++) { + a0 = pSrcA->pData[2 * (r * innerSize + i) + 0]; + b0 = pSrcA->pData[2 * (r * innerSize + i) + 1]; + c0 = pSrcB->pData[2 * (i * outC + c) + 0]; + d0 = pSrcB->pData[2 * (i * outC + c) + 1]; + + sumR += (q31_t)a0 * c0 - (q31_t)b0 * d0; + sumI += (q31_t)b0 * c0 + (q31_t)a0 * d0; + } + + pDst->pData[2 * (r * outC + c) + 0] = ref_sat_q15(sumR >> 15); + pDst->pData[2 * (r * outC + c) + 1] = ref_sat_q15(sumI >> 15); + } + } + + return RISCV_MATH_SUCCESS; +} diff --git a/examples/dsp/MatrixFunctions_q31Part/mat_inverse.c b/examples/dsp/MatrixFunctions_q31Part/mat_inverse.c new file mode 100644 index 00000000..696ce4fc --- /dev/null +++ b/examples/dsp/MatrixFunctions_q31Part/mat_inverse.c @@ -0,0 +1,54 @@ +#include "ref.h" + +riscv_status ref_mat_inverse_f32(const riscv_matrix_instance_f32 *pSrc, + riscv_matrix_instance_f32 *pDst) +{ + float32_t det; + uint32_t i, size; + riscv_matrix_instance_f32 tmp; + + tmp.numCols = pSrc->numCols; + tmp.numRows = pSrc->numRows; + tmp.pData = scratchArray; + + det = ref_detrm(pSrc->pData, scratchArray, pSrc->numCols); + + size = pSrc->numCols * pSrc->numCols; + + ref_cofact(pSrc->pData, scratchArray, scratchArray + size, pSrc->numCols); + + ref_mat_trans_f32(&tmp, pDst); + + for (i = 0; i < size; i++) { + pDst->pData[i] /= det; + } + + return RISCV_MATH_SUCCESS; +} + +riscv_status ref_mat_inverse_f64(const riscv_matrix_instance_f64 *pSrc, + riscv_matrix_instance_f64 *pDst) +{ + float64_t det; + uint32_t i, size; + riscv_matrix_instance_f64 tmp; + + tmp.numCols = pSrc->numCols; + tmp.numRows = pSrc->numRows; + tmp.pData = (float64_t *)scratchArray; + + det = ref_detrm64(pSrc->pData, (float64_t *)scratchArray, pSrc->numCols); + + size = pSrc->numCols * pSrc->numCols; + + ref_cofact64(pSrc->pData, (float64_t *)scratchArray, + (float64_t *)scratchArray + size, pSrc->numCols); + + ref_mat_trans_f64(&tmp, pDst); + + for (i = 0; i < size; i++) { + pDst->pData[i] /= det; + } + + return RISCV_MATH_SUCCESS; +} diff --git a/examples/dsp/MatrixFunctions_q31Part/mat_mult.c b/examples/dsp/MatrixFunctions_q31Part/mat_mult.c new file mode 100644 index 00000000..59ab8217 --- /dev/null +++ b/examples/dsp/MatrixFunctions_q31Part/mat_mult.c @@ -0,0 +1,82 @@ +#include "ref.h" + +riscv_status ref_mat_mult_f32(const riscv_matrix_instance_f32 *pSrcA, + const riscv_matrix_instance_f32 *pSrcB, + riscv_matrix_instance_f32 *pDst) +{ + uint32_t r, c, i, outR, outC, innerSize; + float32_t sum; + + outR = pSrcA->numRows; + outC = pSrcB->numCols; + innerSize = pSrcA->numCols; + + for (r = 0; r < outR; r++) { + for (c = 0; c < outC; c++) { + sum = 0; + + for (i = 0; i < innerSize; i++) { + sum += pSrcA->pData[r * innerSize + i] * + pSrcB->pData[i * outC + c]; + } + + pDst->pData[r * outC + c] = sum; + } + } + + return RISCV_MATH_SUCCESS; +} + +riscv_status ref_mat_mult_q31(const riscv_matrix_instance_q31 *pSrcA, + const riscv_matrix_instance_q31 *pSrcB, + riscv_matrix_instance_q31 *pDst) +{ + uint32_t r, c, i, outR, outC, innerSize; + q63_t sum; + + outR = pSrcA->numRows; + outC = pSrcB->numCols; + innerSize = pSrcA->numCols; + + for (r = 0; r < outR; r++) { + for (c = 0; c < outC; c++) { + sum = 0; + + for (i = 0; i < innerSize; i++) { + sum += (q63_t)(pSrcA->pData[r * innerSize + i]) * + pSrcB->pData[i * outC + c]; + } + + pDst->pData[r * outC + c] = ref_sat_q31(sum >> 31); + } + } + + return RISCV_MATH_SUCCESS; +} + +riscv_status ref_mat_mult_q15(const riscv_matrix_instance_q15 *pSrcA, + const riscv_matrix_instance_q15 *pSrcB, + riscv_matrix_instance_q15 *pDst) +{ + uint32_t r, c, i, outR, outC, innerSize; + q63_t sum; + + outR = pSrcA->numRows; + outC = pSrcB->numCols; + innerSize = pSrcA->numCols; + + for (r = 0; r < outR; r++) { + for (c = 0; c < outC; c++) { + sum = 0; + + for (i = 0; i < innerSize; i++) { + sum += (q31_t)(pSrcA->pData[r * innerSize + i]) * + pSrcB->pData[i * outC + c]; + } + + pDst->pData[r * outC + c] = ref_sat_q15(sum >> 15); + } + } + + return RISCV_MATH_SUCCESS; +} diff --git a/examples/dsp/MatrixFunctions_q31Part/mat_scale.c b/examples/dsp/MatrixFunctions_q31Part/mat_scale.c new file mode 100644 index 00000000..b72308fa --- /dev/null +++ b/examples/dsp/MatrixFunctions_q31Part/mat_scale.c @@ -0,0 +1,54 @@ +#include "ref.h" + +riscv_status ref_mat_scale_f32(const riscv_matrix_instance_f32 *pSrc, + float32_t scale, riscv_matrix_instance_f32 *pDst) +{ + uint32_t i; + uint32_t numSamples; /* total number of elements in the matrix */ + + /* Total number of samples in the input matrix */ + numSamples = (uint32_t)pSrc->numRows * pSrc->numCols; + + for (i = 0; i < numSamples; i++) { + pDst->pData[i] = pSrc->pData[i] * scale; + } + + return RISCV_MATH_SUCCESS; +} + +riscv_status ref_mat_scale_q31(const riscv_matrix_instance_q31 *pSrc, q31_t scale, + int32_t shift, riscv_matrix_instance_q31 *pDst) +{ + uint32_t i; + uint32_t numSamples; /* total number of elements in the matrix */ + int32_t totShift = shift + 1; + q31_t tmp; + + /* Total number of samples in the input matrix */ + numSamples = (uint32_t)pSrc->numRows * pSrc->numCols; + + for (i = 0; i < numSamples; i++) { + tmp = ((q63_t)pSrc->pData[i] * scale) >> 32; + pDst->pData[i] = ref_sat_q31((q63_t)tmp << totShift); + } + + return RISCV_MATH_SUCCESS; +} + +riscv_status ref_mat_scale_q15(const riscv_matrix_instance_q15 *pSrc, q15_t scale, + int32_t shift, riscv_matrix_instance_q15 *pDst) +{ + uint32_t i; + uint32_t numSamples; /* total number of elements in the matrix */ + int32_t totShift = 15 - shift; + + /* Total number of samples in the input matrix */ + numSamples = (uint32_t)pSrc->numRows * pSrc->numCols; + + for (i = 0; i < numSamples; i++) { + pDst->pData[i] = + ref_sat_q15(((q31_t)pSrc->pData[i] * scale) >> totShift); + } + + return RISCV_MATH_SUCCESS; +} diff --git a/examples/dsp/MatrixFunctions_q31Part/mat_sub.c b/examples/dsp/MatrixFunctions_q31Part/mat_sub.c new file mode 100644 index 00000000..339e86ae --- /dev/null +++ b/examples/dsp/MatrixFunctions_q31Part/mat_sub.c @@ -0,0 +1,53 @@ +#include "ref.h" +//#include "../HelperFunctions/ref_helper.c" + +riscv_status ref_mat_sub_f32(const riscv_matrix_instance_f32 *pSrcA, + const riscv_matrix_instance_f32 *pSrcB, + riscv_matrix_instance_f32 *pDst) +{ + uint32_t i; + uint32_t numSamples; /* total number of elements in the matrix */ + + /* Total number of samples in the input matrix */ + numSamples = (uint32_t)pSrcA->numRows * pSrcA->numCols; + + for (i = 0; i < numSamples; i++) { + pDst->pData[i] = pSrcA->pData[i] - pSrcB->pData[i]; + } + + return RISCV_MATH_SUCCESS; +} + +riscv_status ref_mat_sub_q31(const riscv_matrix_instance_q31 *pSrcA, + const riscv_matrix_instance_q31 *pSrcB, + riscv_matrix_instance_q31 *pDst) +{ + uint32_t i; + uint32_t numSamples; /* total number of elements in the matrix */ + + /* Total number of samples in the input matrix */ + numSamples = (uint32_t)pSrcA->numRows * pSrcA->numCols; + + for (i = 0; i < numSamples; i++) { + pDst->pData[i] = ref_sat_q31((q63_t)pSrcA->pData[i] - pSrcB->pData[i]); + } + + return RISCV_MATH_SUCCESS; +} + +riscv_status ref_mat_sub_q15(const riscv_matrix_instance_q15 *pSrcA, + const riscv_matrix_instance_q15 *pSrcB, + riscv_matrix_instance_q15 *pDst) +{ + uint32_t i; + uint32_t numSamples; /* total number of elements in the matrix */ + + /* Total number of samples in the input matrix */ + numSamples = (uint32_t)pSrcA->numRows * pSrcA->numCols; + + for (i = 0; i < numSamples; i++) { + pDst->pData[i] = ref_sat_q15((q31_t)pSrcA->pData[i] - pSrcB->pData[i]); + } + + return RISCV_MATH_SUCCESS; +} diff --git a/examples/dsp/MatrixFunctions_q31Part/mat_trans.c b/examples/dsp/MatrixFunctions_q31Part/mat_trans.c new file mode 100644 index 00000000..8c6c9348 --- /dev/null +++ b/examples/dsp/MatrixFunctions_q31Part/mat_trans.c @@ -0,0 +1,65 @@ +#include "ref.h" + +riscv_status ref_mat_trans_f64(const riscv_matrix_instance_f64 *pSrc, + riscv_matrix_instance_f64 *pDst) +{ + uint64_t r, c; + uint64_t numR = pSrc->numRows; + uint64_t numC = pSrc->numCols; + + for (r = 0; r < numR; r++) { + for (c = 0; c < numC; c++) { + pDst->pData[c * numR + r] = pSrc->pData[r * numC + c]; + } + } + + return RISCV_MATH_SUCCESS; +} + +riscv_status ref_mat_trans_f32(const riscv_matrix_instance_f32 *pSrc, + riscv_matrix_instance_f32 *pDst) +{ + uint32_t r, c; + uint32_t numR = pSrc->numRows; + uint32_t numC = pSrc->numCols; + + for (r = 0; r < numR; r++) { + for (c = 0; c < numC; c++) { + pDst->pData[c * numR + r] = pSrc->pData[r * numC + c]; + } + } + + return RISCV_MATH_SUCCESS; +} + +riscv_status ref_mat_trans_q31(const riscv_matrix_instance_q31 *pSrc, + riscv_matrix_instance_q31 *pDst) +{ + uint32_t r, c; + uint32_t numR = pSrc->numRows; + uint32_t numC = pSrc->numCols; + + for (r = 0; r < numR; r++) { + for (c = 0; c < numC; c++) { + pDst->pData[c * numR + r] = pSrc->pData[r * numC + c]; + } + } + + return RISCV_MATH_SUCCESS; +} + +riscv_status ref_mat_trans_q15(const riscv_matrix_instance_q15 *pSrc, + riscv_matrix_instance_q15 *pDst) +{ + uint32_t r, c; + uint32_t numR = pSrc->numRows; + uint32_t numC = pSrc->numCols; + + for (r = 0; r < numR; r++) { + for (c = 0; c < numC; c++) { + pDst->pData[c * numR + r] = pSrc->pData[r * numC + c]; + } + } + + return RISCV_MATH_SUCCESS; +} diff --git a/examples/dsp/QuaternionMathFunctions_part1/CMakeLists.txt b/examples/dsp/QuaternionMathFunctions_part1/CMakeLists.txt new file mode 100644 index 00000000..08b5a4fb --- /dev/null +++ b/examples/dsp/QuaternionMathFunctions_part1/CMakeLists.txt @@ -0,0 +1,6 @@ +set(TARGET_REQUIRED_PRIVATE_INCLUDE ${CMAKE_CURRENT_SOURCE_DIR} ${CMAKE_CURRENT_SOURCE_DIR}/..) +list(APPEND TARGET_REQUIRED_SRCS conjugate.c inverse.c norm.c) +list(APPEND TARGET_REQUIRED_SRCS normalize.c product_single.c product.c quaternion2rotation.c rotation2quaternion.c) +set(TARGET_REQUIRED_LIBS nmsis) +set(mains main.c) +generate_bin() \ No newline at end of file diff --git a/examples/dsp/QuaternionMathFunctions_part1/array.h b/examples/dsp/QuaternionMathFunctions_part1/array.h new file mode 100644 index 00000000..34defba1 --- /dev/null +++ b/examples/dsp/QuaternionMathFunctions_part1/array.h @@ -0,0 +1,11 @@ +// Array for StatisticsFunctions part1 +#define ARRAY_SIZE 232 + +float32_t f32_array[ARRAY_SIZE] = { +0.814723686393179,0.905791937075619,0.126986816293506,0.913375856139019,0.632359246225410,0.0975404049994095,0.278498218867048,0.546881519204984,0.957506835434298,0.964888535199277,0.157613081677548,0.970592781760616,0.957166948242946,0.485375648722841,0.800280468888800,0.141886338627215,0.421761282626275,0.915735525189067,0.792207329559554,0.959492426392903,0.655740699156587,0.0357116785741896,0.849129305868777,0.933993247757551,0.678735154857774,0.757740130578333,0.743132468124916,0.392227019534168,0.655477890177557,0.171186687811562,0.706046088019609,0.0318328463774207,0.276922984960890,0.0461713906311539,0.0971317812358475,0.823457828327293,0.694828622975817,0.317099480060861,0.950222048838355,0.0344460805029088,0.438744359656398,0.381558457093008,0.765516788149002,0.795199901137063,0.186872604554379,0.489764395788231,0.445586200710900,0.646313010111265,0.709364830858073,0.754686681982361,0.276025076998578,0.679702676853675,0.655098003973841,0.162611735194631,0.118997681558377,0.498364051982143,0.959743958516081,0.340385726666133,0.585267750979777,0.223811939491137,0.751267059305653,0.255095115459269,0.505957051665142,0.699076722656686,0.890903252535799,0.959291425205444,0.547215529963803,0.138624442828679,0.149294005559057,0.257508254123736,0.840717255983663,0.254282178971531,0.814284826068816,0.243524968724989,0.929263623187228,0.349983765984809,0.196595250431208,0.251083857976031,0.616044676146639,0.473288848902729,0.351659507062997,0.830828627896291,0.585264091152724,0.549723608291140,0.917193663829810,0.285839018820374,0.757200229110721,0.753729094278495,0.380445846975357,0.567821640725221,0.0758542895630636,0.0539501186666072,0.530797553008973,0.779167230102011,0.934010684229183,0.129906208473730,0.568823660872193,0.469390641058206,0.0119020695012414,0.337122644398882,0.162182308193243,0.794284540683907,0.311215042044805,0.528533135506213,0.165648729499781,0.601981941401637,0.262971284540144,0.654079098476782,0.689214503140008,0.748151592823710,0.450541598502498,0.0838213779969326,0.228976968716819,0.913337361501670,0.152378018969223,0.825816977489547,0.538342435260057,0.996134716626886,0.0781755287531837,0.442678269775446,0.106652770180584,0.961898080855054,0.00463422413406744,0.774910464711502,0.817303220653433,0.868694705363510,0.0844358455109103,0.399782649098897,0.259870402850654,0.800068480224308,0.431413827463545,0.910647594429523,0.181847028302853,0.263802916521990,0.145538980384717,0.136068558708664,0.869292207640089,0.579704587365570,0.549860201836332,0.144954798223727,0.853031117721894,0.622055131485066,0.350952380892271,0.513249539867053,0.401808033751942,0.0759666916908419,0.239916153553658,0.123318934835166,0.183907788282417,0.239952525664903,0.417267069084370,0.0496544303257421,0.902716109915281,0.944787189721646,0.490864092468080,0.489252638400019,0.337719409821377,0.900053846417662,0.369246781120215,0.111202755293787,0.780252068321138,0.389738836961253,0.241691285913833,0.403912145588115,0.0964545251683886,0.131973292606335,0.942050590775485,0.956134540229802,0.575208595078466,0.0597795429471558,0.234779913372406,0.353158571222071,0.821194040197959,0.0154034376515551,0.0430238016578078,0.168990029462704,0.649115474956452,0.731722385658670,0.647745963136307,0.450923706430945,0.547008892286345,0.296320805607773,0.744692807074156,0.188955015032545,0.686775433365315,0.183511155737270,0.368484596490337,0.625618560729690,0.780227435151377,0.0811257688657853,0.929385970968730,0.775712678608402,0.486791632403172,0.435858588580919,0.446783749429806,0.306349472016557,0.508508655381127,0.510771564172110,0.817627708322262,0.794831416883453,0.644318130193692,0.378609382660268,0.811580458282477,0.532825588799455,0.350727103576883,0.939001561999887,0.875942811492984,0.550156342898422,0.622475086001228,0.587044704531417,0.207742292733028,0.301246330279491,0.470923348517591,0.230488160211559,0.844308792695389,0.194764289567049,0.225921780972399,0.170708047147859,0.227664297816554,0.435698684103899,0.311102286650413,0.923379642103244,0.430207391329584,0.184816320124136,0.904880968679893,0.979748378356085,0.438869973126103,0.111119223440599,0.258064695912067,0.408719846112552,0.594896074008614,0.262211747780845}; + +float32_t f32_b_array[ARRAY_SIZE] = { +0.814723686393179,0.905791937075619,0.126986816293506,0.913375856139019,0.632359246225410,0.0975404049994095,0.278498218867048,0.546881519204984,0.957506835434298,0.964888535199277,0.157613081677548,0.970592781760616,0.957166948242946,0.485375648722841,0.800280468888800,0.141886338627215,0.421761282626275,0.915735525189067,0.792207329559554,0.959492426392903,0.655740699156587,0.0357116785741896,0.849129305868777,0.933993247757551,0.678735154857774,0.757740130578333,0.743132468124916,0.392227019534168,0.655477890177557,0.171186687811562,0.706046088019609,0.0318328463774207,0.276922984960890,0.0461713906311539,0.0971317812358475,0.823457828327293,0.694828622975817,0.317099480060861,0.950222048838355,0.0344460805029088,0.438744359656398,0.381558457093008,0.765516788149002,0.795199901137063,0.186872604554379,0.489764395788231,0.445586200710900,0.646313010111265,0.709364830858073,0.754686681982361,0.276025076998578,0.679702676853675,0.655098003973841,0.162611735194631,0.118997681558377,0.498364051982143,0.959743958516081,0.340385726666133,0.585267750979777,0.223811939491137,0.751267059305653,0.255095115459269,0.505957051665142,0.699076722656686,0.890903252535799,0.959291425205444,0.547215529963803,0.138624442828679,0.149294005559057,0.257508254123736,0.840717255983663,0.254282178971531,0.814284826068816,0.243524968724989,0.929263623187228,0.349983765984809,0.196595250431208,0.251083857976031,0.616044676146639,0.473288848902729,0.351659507062997,0.830828627896291,0.585264091152724,0.549723608291140,0.917193663829810,0.285839018820374,0.757200229110721,0.753729094278495,0.380445846975357,0.567821640725221,0.0758542895630636,0.0539501186666072,0.530797553008973,0.779167230102011,0.934010684229183,0.129906208473730,0.568823660872193,0.469390641058206,0.0119020695012414,0.337122644398882,0.162182308193243,0.794284540683907,0.311215042044805,0.528533135506213,0.165648729499781,0.601981941401637,0.262971284540144,0.654079098476782,0.689214503140008,0.748151592823710,0.450541598502498,0.0838213779969326,0.228976968716819,0.913337361501670,0.152378018969223,0.825816977489547,0.538342435260057,0.996134716626886,0.0781755287531837,0.442678269775446,0.106652770180584,0.961898080855054,0.00463422413406744,0.774910464711502,0.817303220653433,0.868694705363510,0.0844358455109103,0.399782649098897,0.259870402850654,0.800068480224308,0.431413827463545,0.910647594429523,0.181847028302853,0.263802916521990,0.145538980384717,0.136068558708664,0.869292207640089,0.579704587365570,0.549860201836332,0.144954798223727,0.853031117721894,0.622055131485066,0.350952380892271,0.513249539867053,0.401808033751942,0.0759666916908419,0.239916153553658,0.123318934835166,0.183907788282417,0.239952525664903,0.417267069084370,0.0496544303257421,0.902716109915281,0.944787189721646,0.490864092468080,0.489252638400019,0.337719409821377,0.900053846417662,0.369246781120215,0.111202755293787,0.780252068321138,0.389738836961253,0.241691285913833,0.403912145588115,0.0964545251683886,0.131973292606335,0.942050590775485,0.956134540229802,0.575208595078466,0.0597795429471558,0.234779913372406,0.353158571222071,0.821194040197959,0.0154034376515551,0.0430238016578078,0.168990029462704,0.649115474956452,0.731722385658670,0.647745963136307,0.450923706430945,0.547008892286345,0.296320805607773,0.744692807074156,0.188955015032545,0.686775433365315,0.183511155737270,0.368484596490337,0.625618560729690,0.780227435151377,0.0811257688657853,0.929385970968730,0.775712678608402,0.486791632403172,0.435858588580919,0.446783749429806,0.306349472016557,0.508508655381127,0.510771564172110,0.817627708322262,0.794831416883453,0.644318130193692,0.378609382660268,0.811580458282477,0.532825588799455,0.350727103576883,0.939001561999887,0.875942811492984,0.550156342898422,0.622475086001228,0.587044704531417,0.207742292733028,0.301246330279491,0.470923348517591,0.230488160211559,0.844308792695389,0.194764289567049,0.225921780972399,0.170708047147859,0.227664297816554,0.435698684103899,0.311102286650413,0.923379642103244,0.430207391329584,0.184816320124136,0.904880968679893,0.979748378356085,0.438869973126103,0.111119223440599,0.258064695912067,0.408719846112552,0.594896074008614,0.262211747780845}; + +f32_array_opt[ARRAY_SIZE]; +f32_array_ref[ARRAY_SIZE]; diff --git a/examples/dsp/QuaternionMathFunctions_part1/conjugate.c b/examples/dsp/QuaternionMathFunctions_part1/conjugate.c new file mode 100644 index 00000000..ff0c4c87 --- /dev/null +++ b/examples/dsp/QuaternionMathFunctions_part1/conjugate.c @@ -0,0 +1,17 @@ +#include "ref.h" + +void ref_quaternion_conjugate_f32(const float32_t *pInputQuaternions, + float32_t *pConjugateQuaternions, + uint32_t nbQuaternions) +{ + for(uint32_t i=0; i < nbQuaternions; i++) + { + + pConjugateQuaternions[4 * i + 0] = pInputQuaternions[4 * i + 0]; + pConjugateQuaternions[4 * i + 1] = -pInputQuaternions[4 * i + 1]; + pConjugateQuaternions[4 * i + 2] = -pInputQuaternions[4 * i + 2]; + pConjugateQuaternions[4 * i + 3] = -pInputQuaternions[4 * i + 3]; + } +} + + diff --git a/examples/dsp/QuaternionMathFunctions_part1/inverse.c b/examples/dsp/QuaternionMathFunctions_part1/inverse.c new file mode 100644 index 00000000..6ef2c419 --- /dev/null +++ b/examples/dsp/QuaternionMathFunctions_part1/inverse.c @@ -0,0 +1,24 @@ +#include "ref.h" + +void ref_quaternion_inverse_f32(const float32_t *pInputQuaternions, + float32_t *pInverseQuaternions, + uint32_t nbQuaternions) +{ + float32_t temp; + + for(uint32_t i=0; i < nbQuaternions; i++) + { + + temp = SQ(pInputQuaternions[4 * i + 0]) + + SQ(pInputQuaternions[4 * i + 1]) + + SQ(pInputQuaternions[4 * i + 2]) + + SQ(pInputQuaternions[4 * i + 3]); + + pInverseQuaternions[4 * i + 0] = pInputQuaternions[4 * i + 0] / temp; + pInverseQuaternions[4 * i + 1] = -pInputQuaternions[4 * i + 1] / temp; + pInverseQuaternions[4 * i + 2] = -pInputQuaternions[4 * i + 2] / temp; + pInverseQuaternions[4 * i + 3] = -pInputQuaternions[4 * i + 3] / temp; + } +} + + diff --git a/examples/dsp/QuaternionMathFunctions_part1/main.c b/examples/dsp/QuaternionMathFunctions_part1/main.c new file mode 100644 index 00000000..1fd6f2c4 --- /dev/null +++ b/examples/dsp/QuaternionMathFunctions_part1/main.c @@ -0,0 +1,145 @@ +// +// Created by lujun on 19-6-28.DELTAF32 +// + +#include "riscv_math.h" +#include "array.h" +#include +#include +#include "../common.h" + +#include "../HelperFunctions/math_helper.c" +#include "../HelperFunctions/ref_helper.c" + +#include +#define DELTAF32 (0.05f) +#define DELTAQ31 (63) +#define DELTAQ15 (1) +#define DELTAQ7 (1) + +#define ENABLE_ALL +#define F32 +#define Q31 +#define Q15 +#define Q7 + +int test_flag_error = 0; + +int main() +{ + float32_t f32_out[ARRAY_SIZE], f32_out_ref[ARRAY_SIZE]; + + BENCH_INIT; + // conjugate + BENCH_START(riscv_quaternion_conjugate_f32); + riscv_quaternion_conjugate_f32(f32_array, f32_array_opt, ARRAY_SIZE/4); + BENCH_END(riscv_quaternion_conjugate_f32); + ref_quaternion_conjugate_f32(f32_array, f32_array_ref, ARRAY_SIZE/4); + for(int i = 0;i DELTAF32) { + BENCH_ERROR(riscv_quaternion_conjugate_f32); + printf("index: %d, expect: %f, actual: %f\n", i, f32_array_ref[i], f32_array_opt[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_quaternion_conjugate_f32); + + // inverse + BENCH_START(riscv_quaternion_inverse_f32); + riscv_quaternion_inverse_f32(f32_array, f32_array_opt, ARRAY_SIZE/4); + BENCH_END(riscv_quaternion_inverse_f32); + ref_quaternion_inverse_f32(f32_array, f32_array_ref, ARRAY_SIZE/4); + for(int i = 0;i3) { + BENCH_ERROR(riscv_quaternion_inverse_f32); + printf("index: %d, expect: %f, actual: %f\n", i, f32_array_ref[i], f32_array_opt[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_quaternion_inverse_f32); + + // norm + BENCH_START(riscv_quaternion_norm_f32); + riscv_quaternion_norm_f32(f32_array, f32_array_opt, ARRAY_SIZE/4); + BENCH_END(riscv_quaternion_norm_f32); + ref_quaternion_norm_f32(f32_array, f32_array_ref, ARRAY_SIZE/4); + for(int i = 0;i 2) { + BENCH_ERROR(riscv_quaternion_norm_f32); + printf("index: %d, expect: %f, actual: %f\n", i, f32_array_ref[i], f32_array_opt[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_quaternion_norm_f32); + + // normalize + BENCH_START(riscv_quaternion_normalize_f32); + riscv_quaternion_normalize_f32(f32_array, f32_array_opt, ARRAY_SIZE/4); + BENCH_END(riscv_quaternion_normalize_f32); + ref_quaternion_normalize_f32(f32_array, f32_array_ref, ARRAY_SIZE/4); + for(int i = 0;i 3) { + BENCH_ERROR(riscv_quaternion_normalize_f32); + printf("index: %d, expect: %x, actual: %x\n", i, f32_array_ref[i], f32_array_opt[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_quaternion_normalize_f32); + + // product + BENCH_START(riscv_quaternion_product_f32); + riscv_quaternion_product_f32(f32_array, f32_b_array, f32_out, ARRAY_SIZE/4); + BENCH_END(riscv_quaternion_product_f32); + ref_quaternion_product_f32(f32_array, f32_b_array, f32_out_ref, ARRAY_SIZE/4); + for(int i = 0;i DELTAF32) { + BENCH_ERROR(riscv_quaternion_product_f32); + printf("index: %d, expect: %f, actual: %f\n", i, f32_out_ref[i], f32_out[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_quaternion_product_f32); + + // product_single + BENCH_START(riscv_quaternion_product_single_f32); + riscv_quaternion_product_single_f32(f32_array, f32_array_opt, f32_out); + BENCH_END(riscv_quaternion_product_single_f32); + ref_quaternion_product_single_f32(f32_array, f32_array_ref, f32_out_ref); + for(int i = 0;i<4;i++) + if (abs(f32_out_ref[i] - f32_out[i]) > DELTAF32) { + BENCH_ERROR(riscv_quaternion_product_single_f32); + printf("index: %d, expect: %f, actual: %f\n", i, f32_out_ref[i], f32_out[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_quaternion_product_single_f32); + + // quaternion2rotation + BENCH_START(riscv_quaternion2rotation_f32); + riscv_quaternion2rotation_f32(f32_array, f32_out, ARRAY_SIZE/9); + BENCH_END(riscv_quaternion2rotation_f32); + ref_quaternion2rotation_f32(f32_array, f32_out_ref, ARRAY_SIZE/9); + for(int i = 0;i<(ARRAY_SIZE/9*9);i++) + if (abs(f32_out[i] - f32_out_ref[i]) > DELTAF32) { + BENCH_ERROR(riscv_quaternion2rotation_f32); + printf("index: %d, expect: %f, actual: %f\n", i, f32_out_ref[i], f32_out[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_quaternion2rotation_f32); + + // rotation2quaternion + BENCH_START(riscv_rotation2quaternion_f32); + riscv_rotation2quaternion_f32(f32_array, f32_out, ARRAY_SIZE/9); + BENCH_END(riscv_rotation2quaternion_f32); + ref_rotation2quaternion_f32(f32_array, f32_out_ref, ARRAY_SIZE/9); + for(int i = 0;i DELTAF32) { + BENCH_ERROR(riscv_rotation2quaternion_f32); + printf("index: %d, expect: %f, actual: %f\n", i, f32_out_ref[i], f32_out[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_rotation2quaternion_f32); + + BENCH_FINISH; + if (test_flag_error) { + printf("test error apprears, please recheck.\n"); + return 1; + } else { + printf("all test are passed. Well done!\n"); + } + return 0; +} diff --git a/examples/dsp/QuaternionMathFunctions_part1/norm.c b/examples/dsp/QuaternionMathFunctions_part1/norm.c new file mode 100644 index 00000000..df7b840e --- /dev/null +++ b/examples/dsp/QuaternionMathFunctions_part1/norm.c @@ -0,0 +1,19 @@ +#include "ref.h" + +void ref_quaternion_norm_f32(const float32_t *pInputQuaternions, + float32_t *pNorms, + uint32_t nbQuaternions) +{ + float32_t temp; + + for(uint32_t i=0; i < nbQuaternions; i++) + { + temp = SQ(pInputQuaternions[4 * i + 0]) + + SQ(pInputQuaternions[4 * i + 1]) + + SQ(pInputQuaternions[4 * i + 2]) + + SQ(pInputQuaternions[4 * i + 3]); + pNorms[i] = sqrtf(temp); + } +} + + diff --git a/examples/dsp/QuaternionMathFunctions_part1/normalize.c b/examples/dsp/QuaternionMathFunctions_part1/normalize.c new file mode 100644 index 00000000..2a57cf83 --- /dev/null +++ b/examples/dsp/QuaternionMathFunctions_part1/normalize.c @@ -0,0 +1,24 @@ +#include "ref.h" + +void ref_quaternion_normalize_f32(const float32_t *pInputQuaternions, + float32_t *pNormalizedQuaternions, + uint32_t nbQuaternions) +{ + float32_t temp; + + for(uint32_t i=0; i < nbQuaternions; i++) + { + temp = SQ(pInputQuaternions[4 * i + 0]) + + SQ(pInputQuaternions[4 * i + 1]) + + SQ(pInputQuaternions[4 * i + 2]) + + SQ(pInputQuaternions[4 * i + 3]); + temp = sqrtf(temp); + + pNormalizedQuaternions[4 * i + 0] = pInputQuaternions[4 * i + 0] / temp; + pNormalizedQuaternions[4 * i + 1] = pInputQuaternions[4 * i + 1] / temp; + pNormalizedQuaternions[4 * i + 2] = pInputQuaternions[4 * i + 2] / temp; + pNormalizedQuaternions[4 * i + 3] = pInputQuaternions[4 * i + 3] / temp; + } +} + + diff --git a/examples/dsp/QuaternionMathFunctions_part1/product.c b/examples/dsp/QuaternionMathFunctions_part1/product.c new file mode 100644 index 00000000..9c718af6 --- /dev/null +++ b/examples/dsp/QuaternionMathFunctions_part1/product.c @@ -0,0 +1,18 @@ +#include "ref.h" + +void ref_quaternion_product_f32(const float32_t *qa, + const float32_t *qb, + float32_t *qr, + uint32_t nbQuaternions) +{ + for(uint32_t i=0; i < nbQuaternions; i++) + { + ref_quaternion_product_single_f32(qa, qb, qr); + + qa += 4; + qb += 4; + qr += 4; + } +} + + diff --git a/examples/dsp/QuaternionMathFunctions_part1/product_single.c b/examples/dsp/QuaternionMathFunctions_part1/product_single.c new file mode 100644 index 00000000..2eb94b53 --- /dev/null +++ b/examples/dsp/QuaternionMathFunctions_part1/product_single.c @@ -0,0 +1,13 @@ +#include "ref.h" + +void ref_quaternion_product_single_f32(const float32_t *qa, + const float32_t *qb, + float32_t *qr) +{ + qr[0] = qa[0] * qb[0] - qa[1] * qb[1] - qa[2] * qb[2] - qa[3] * qb[3]; + qr[1] = qa[0] * qb[1] + qa[1] * qb[0] + qa[2] * qb[3] - qa[3] * qb[2]; + qr[2] = qa[0] * qb[2] + qa[2] * qb[0] + qa[3] * qb[1] - qa[1] * qb[3]; + qr[3] = qa[0] * qb[3] + qa[3] * qb[0] + qa[1] * qb[2] - qa[2] * qb[1]; +} + + diff --git a/examples/dsp/QuaternionMathFunctions_part1/quaternion2rotation.c b/examples/dsp/QuaternionMathFunctions_part1/quaternion2rotation.c new file mode 100644 index 00000000..c64cf894 --- /dev/null +++ b/examples/dsp/QuaternionMathFunctions_part1/quaternion2rotation.c @@ -0,0 +1,35 @@ +#include "ref.h" + +void ref_quaternion2rotation_f32(const float32_t *pInputQuaternions, + float32_t *pOutputRotations, + uint32_t nbQuaternions) +{ + for(uint32_t nb=0; nb < nbQuaternions; nb++) + { + float32_t q00 = SQ(pInputQuaternions[0 + nb * 4]); + float32_t q11 = SQ(pInputQuaternions[1 + nb * 4]); + float32_t q22 = SQ(pInputQuaternions[2 + nb * 4]); + float32_t q33 = SQ(pInputQuaternions[3 + nb * 4]); + float32_t q01 = pInputQuaternions[0 + nb * 4]*pInputQuaternions[1 + nb * 4]; + float32_t q02 = pInputQuaternions[0 + nb * 4]*pInputQuaternions[2 + nb * 4]; + float32_t q03 = pInputQuaternions[0 + nb * 4]*pInputQuaternions[3 + nb * 4]; + float32_t q12 = pInputQuaternions[1 + nb * 4]*pInputQuaternions[2 + nb * 4]; + float32_t q13 = pInputQuaternions[1 + nb * 4]*pInputQuaternions[3 + nb * 4]; + float32_t q23 = pInputQuaternions[2 + nb * 4]*pInputQuaternions[3 + nb * 4]; + + float32_t xx = q00 + q11 - q22 - q33; + float32_t yy = q00 - q11 + q22 - q33; + float32_t zz = q00 - q11 - q22 + q33; + float32_t xy = 2*(q12 - q03); + float32_t xz = 2*(q13 + q02); + float32_t yx = 2*(q12 + q03); + float32_t yz = 2*(q23 - q01); + float32_t zx = 2*(q13 - q02); + float32_t zy = 2*(q23 + q01); + + pOutputRotations[0 + nb * 9] = xx; pOutputRotations[1 + nb * 9] = xy; pOutputRotations[2 + nb * 9] = xz; + pOutputRotations[3 + nb * 9] = yx; pOutputRotations[4 + nb * 9] = yy; pOutputRotations[5 + nb * 9] = yz; + pOutputRotations[6 + nb * 9] = zx; pOutputRotations[7 + nb * 9] = zy; pOutputRotations[8 + nb * 9] = zz; + } +} + diff --git a/examples/dsp/QuaternionMathFunctions_part1/rotation2quaternion.c b/examples/dsp/QuaternionMathFunctions_part1/rotation2quaternion.c new file mode 100644 index 00000000..b3b1ed2f --- /dev/null +++ b/examples/dsp/QuaternionMathFunctions_part1/rotation2quaternion.c @@ -0,0 +1,57 @@ +#include "ref.h" + +#define RI(x,y) r[(3*(x) + (y))] + +void ref_rotation2quaternion_f32(const float32_t *pInputRotations, + float32_t *pOutputQuaternions, + uint32_t nbQuaternions) +{ + for(uint32_t nb=0; nb < nbQuaternions; nb++) + { + const float32_t *r=&pInputRotations[nb*9]; + float32_t *q=&pOutputQuaternions[nb*4]; + + float32_t trace = RI(0,0) + RI(1,1) + RI(2,2); + + float32_t doubler; + float32_t s; + + if (trace > 0) + { + doubler = sqrtf(trace + 1.0) * 2; // invs=4*qw + s = 1.0 / doubler; + q[0] = 0.25 * doubler; + q[1] = (RI(2,1) - RI(1,2)) * s; + q[2] = (RI(0,2) - RI(2,0)) * s; + q[3] = (RI(1,0) - RI(0,1)) * s; + } + else if ((RI(0,0) > RI(1,1)) && (RI(0,0) > RI(2,2)) ) + { + doubler = sqrtf(1.0 + RI(0,0) - RI(1,1) - RI(2,2)) * 2; // invs=4*qx + s = 1.0 / doubler; + q[0] = (RI(2,1) - RI(1,2)) * s; + q[1] = 0.25 * doubler; + q[2] = (RI(0,1) + RI(1,0)) * s; + q[3] = (RI(0,2) + RI(2,0)) * s; + } + else if (RI(1,1) > RI(2,2)) + { + doubler = sqrtf(1.0 + RI(1,1) - RI(0,0) - RI(2,2)) * 2; // invs=4*qy + s = 1.0 / doubler; + q[0] = (RI(0,2) - RI(2,0)) * s; + q[1] = (RI(0,1) + RI(1,0)) * s; + q[2] = 0.25 * doubler; + q[3] = (RI(1,2) + RI(2,1)) * s; + } + else + { + doubler = sqrtf(1.0 + RI(2,2) - RI(0,0) - RI(1,1)) * 2; // invs=4*qz + s = 1.0 / doubler; + q[0] = (RI(1,0) - RI(0,1)) * s; + q[1] = (RI(0,2) + RI(2,0)) * s; + q[2] = (RI(1,2) + RI(2,1)) * s; + q[3] = 0.25 * doubler; + } + + } +} \ No newline at end of file diff --git a/examples/dsp/Readme.md b/examples/dsp/Readme.md new file mode 100644 index 00000000..7a6bc1d9 --- /dev/null +++ b/examples/dsp/Readme.md @@ -0,0 +1,51 @@ + +# Bouffalo Lab Microcontroller Software Interface Standard + +The **NMSIS** is a vendor-independent hardware abstraction layer for micro-controllers that are based on Bl70x Serial processors. + +The **NMSIS** defines generic tool interfaces and enables consistent device support. +It provides simple software interfaces to the processor and the peripherals, simplifying software re-use, reducing the learning +curve for micro-controller developers, and reducing the time to market for new devices. + +## NMSIS Componments + +* **NMSIS CORE** + + All Risc-V Class Processors Standardized API for the Bouffalo Lab processor core and peripherals. + +* **NMSIS DSP** + + All Bouffalo Lab Bl70x Class Processors DSP library collection with a lot of functions for various data types: + fixed-point (fractional q7, q15, q31) and single precision floating-point (32-bit). + Implementations optimized for the Bl70x processor core which has RISC-V SIMD instruction set. + +* **NMSIS NN** + + All Bouffalo Lab Bl70x Class Processors Collection of efficient neural network kernels developed to maximize + the performance and minimize the memory footprint Bouffalo Lab Bl70x processor core. + +## Directory Structure + +| Directory | Content | +|:-------------------------- |:--------------------------------------------------------- | +| components/nmsis/core | NMSIS-Core related files | +| components/NMSIS/DSP | NMSIS-DSP related files | +| components/NMSIS/NN | NMSIS-NN related files | +| examples/dsp | dsp examples | +| examples/nn | nn examples | +| examples/mfcc | mfcc compile examples | + +## Build Command + +In the bl_mcu_sdk root directory, input +`` make APP=BasicMathFunctions_part1 `` + +BasicMathFunctions_part1 is project foldor name which is placed in examples/dsp or examples/nn. +User can replace APP=xxx to change build target. + + +## License + +This NMSIS is modified based on open-source project CMSIS to match Boufflao Lab requirements. +This project transplant NMSIS into bl_mcu_sdk structure for Bouffalo Lab Device Adapting. +NMSIS is licensed under Apache-2.0. diff --git a/examples/dsp/SVMFunctions_linearSVM/CMakeLists.txt b/examples/dsp/SVMFunctions_linearSVM/CMakeLists.txt new file mode 100644 index 00000000..6a0b0998 --- /dev/null +++ b/examples/dsp/SVMFunctions_linearSVM/CMakeLists.txt @@ -0,0 +1,4 @@ +set(TARGET_REQUIRED_PRIVATE_INCLUDE ${CMAKE_CURRENT_SOURCE_DIR} ${CMAKE_CURRENT_SOURCE_DIR}/..) +set(TARGET_REQUIRED_LIBS nmsis) +set(mains main.c) +generate_bin() \ No newline at end of file diff --git a/examples/dsp/SVMFunctions_linearSVM/main.c b/examples/dsp/SVMFunctions_linearSVM/main.c new file mode 100644 index 00000000..54ebd9f2 --- /dev/null +++ b/examples/dsp/SVMFunctions_linearSVM/main.c @@ -0,0 +1,116 @@ +#include "riscv_math.h" +#include +#include +#include "../common.h" + +#include "../HelperFunctions/math_helper.c" +#include "../HelperFunctions/ref_helper.c" + +#include +#define DELTAF32 (0.05f) +#define DELTAQ31 (63) +#define DELTAQ15 (1) +#define DELTAQ7 (1) + +int test_flag_error = 0; + +/* + The linear SVM instance containing all parameters. + Those parameters can be generated with the python library scikit-learn. + */ +riscv_svm_linear_instance_f32 params; + +/* + Parameters generated by a training of the SVM classifier + using scikit-learn and some random input data. + */ +#define NB_SUPPORT_VECTORS 5 + +/* + Dimension of the vector space. A vector is your feature. + It could, for instance, be the pixels of a picture or the FFT of a signal. + */ +#define VECTOR_DIMENSION 2 + +const float32_t dualCoefficients[NB_SUPPORT_VECTORS]={-0.35546785f,-1.0f,-0.36854031f,1.0f,0.72400816f}; /* Dual coefficients */ + +const float32_t supportVectors[NB_SUPPORT_VECTORS*VECTOR_DIMENSION]={0.72036631f,1.03756244f,-0.38866912f,-0.12420514f,-2.2480224f,1.06849044f,-0.85917311f,0.1668838f,-0.15631996f,-0.82489954f}; /* Support vectors */ + +/* + Class A is identified with value 0. + Class B is identified with value 1. + + This array is used by the SVM functions to do a conversion and ease the comparison + with the Python code where different values could be used. + */ +const int32_t classes[2]={0,1}; + +int main() +{ + int i; + BENCH_INIT; + /* Array of input data */ + float32_t in[VECTOR_DIMENSION]; + + /* Result of the classifier */ + int32_t result; + + + /* + Initialization of the SVM instance parameters. + Additional parameters (intercept, degree, coef0 and gamma) are also coming from Python. + */ + riscv_svm_linear_init_f32(¶ms, + NB_SUPPORT_VECTORS, + VECTOR_DIMENSION, + 0.116755f, /* Intercept */ + dualCoefficients, + supportVectors, + classes + ); + + + /* + Input data. + */ + in[0] = 0.8f; + in[1] = 1.1f; + + BENCH_START(riscv_svm_linear_predict_f32); + riscv_svm_linear_predict_f32(¶ms, in, &result); + BENCH_END(riscv_svm_linear_predict_f32); + + /* Result should be 0 : First class */ + if (result != 0) { + BENCH_ERROR(riscv_svm_linear_predict_f32); + printf("expect: %d, actual: %d\n", 0, result); + test_flag_error = 1; + } + BENCH_STATUS(riscv_svm_linear_predict_f32); + + /* + Input data. + */ + in[0] = 3.0f; + in[1] = -2.0f; + + riscv_svm_linear_predict_f32(¶ms, in, &result); + + /* Result should be 1 : Second class */ + if (result != 1) { + BENCH_ERROR(riscv_svm_linear_predict_f32); + printf("expect: %d, actual: %d\n", 1, result); + test_flag_error = 1; + } + BENCH_STATUS(riscv_svm_linear_predict_f32); + + + BENCH_FINISH; + if (test_flag_error) { + printf("test error apprears, please recheck.\n"); + return 1; + } else { + printf("all test are passed. Well done!\n"); + } + return 0; +}; diff --git a/examples/dsp/SVMFunctions_polynomialSVM/CMakeLists.txt b/examples/dsp/SVMFunctions_polynomialSVM/CMakeLists.txt new file mode 100644 index 00000000..6a0b0998 --- /dev/null +++ b/examples/dsp/SVMFunctions_polynomialSVM/CMakeLists.txt @@ -0,0 +1,4 @@ +set(TARGET_REQUIRED_PRIVATE_INCLUDE ${CMAKE_CURRENT_SOURCE_DIR} ${CMAKE_CURRENT_SOURCE_DIR}/..) +set(TARGET_REQUIRED_LIBS nmsis) +set(mains main.c) +generate_bin() \ No newline at end of file diff --git a/examples/dsp/SVMFunctions_polynomialSVM/main.c b/examples/dsp/SVMFunctions_polynomialSVM/main.c new file mode 100644 index 00000000..a379a0ee --- /dev/null +++ b/examples/dsp/SVMFunctions_polynomialSVM/main.c @@ -0,0 +1,118 @@ +#include "riscv_math.h" +#include +#include +#include "../common.h" + +#include "../HelperFunctions/math_helper.c" +#include "../HelperFunctions/ref_helper.c" + +#include +#define DELTAF32 (0.05f) +#define DELTAQ31 (63) +#define DELTAQ15 (1) +#define DELTAQ7 (1) + +int test_flag_error = 0; + +/* + The polynomial SVM instance containing all parameters. + Those parameters can be generated with the python library scikit-learn. + */ +riscv_svm_polynomial_instance_f32 params; + +/* + Parameters generated by a training of the SVM classifier + using scikit-learn and some random input data. + */ +#define NB_SUPPORT_VECTORS 9 + +/* + Dimension of the vector space. A vector is your feature. + It could, for instance, be the pixels of a picture or the FFT of a signal. + */ +#define VECTOR_DIMENSION 2 + +const float32_t dualCoefficients[NB_SUPPORT_VECTORS]={-0.05355985f,-0.08799571f,0.03355538f,0.03568506f,0.02952993f,0.00270412f,0.01743034f,0.01808445f,0.00456627f}; /* Dual coefficients */ + +const float32_t supportVectors[NB_SUPPORT_VECTORS*VECTOR_DIMENSION]={1.35662086f,0.39208881f,-1.01276844f,-1.13381492f,2.18118916f,1.76274021f,-2.62629126f,-0.81061583f,-0.86876703f,-2.74531146f,-0.82722208f,2.77116307f,-1.51435674f,2.40297933f,2.61838172f,-1.22023814f,2.0558457f,-2.00230947f}; /* Support vectors */ + +/* + Class A is identified with value 0. + Class B is identified with value 1. + + This array is used by the SVM functions to do a conversion and ease the comparison + with the Python code where different values could be used. + */ +const int32_t classes[2]={0,1}; + +int main() +{ + int i; + BENCH_INIT; + /* Array of input data */ + float32_t in[VECTOR_DIMENSION]; + + /* Result of the classifier */ + int32_t result; + + + /* + Initialization of the SVM instance parameters. + Additional parameters (intercept, degree, coef0 and gamma) are also coming from Python. + */ + riscv_svm_polynomial_init_f32(¶ms, + NB_SUPPORT_VECTORS, + VECTOR_DIMENSION, + -1.704476f, /* Intercept */ + dualCoefficients, + supportVectors, + classes, + 3, /* degree */ + 1.100000f, /* Coef0 */ + 0.500000f /* Gamma */ + ); + + + /* + Input data. + It is corresponding to a point inside the first class. + */ + in[0] = 0.4f; + in[1] = 0.1f; + BENCH_START(riscv_svm_polynomial_predict_f32); + riscv_svm_polynomial_predict_f32(¶ms, in, &result); + BENCH_END(riscv_svm_polynomial_predict_f32); + /* Result should be 0 : First class */ + if (result != 0) { + BENCH_ERROR(riscv_svm_polynomial_predict_f32); + printf("expect: %d, actual: %d\n", 0, result); + test_flag_error = 1; + } + BENCH_STATUS(riscv_svm_polynomial_predict_f32); + + /* + This input vector is corresponding to a point inside the second class. + */ + in[0] = 3.0f; + in[1] = 0.0f; + + riscv_svm_polynomial_predict_f32(¶ms, in, &result); + + /* Result should be 0 : First class */ + if (result != 1) { + BENCH_ERROR(riscv_svm_polynomial_predict_f32); + printf("expect: %d, actual: %d\n", 1, result); + test_flag_error = 1; + } + BENCH_STATUS(riscv_svm_polynomial_predict_f32); + + + BENCH_FINISH; + if (test_flag_error) { + printf("test error apprears, please recheck.\n"); + return 1; + } else { + printf("all test are passed. Well done!\n"); + } + return 0; +}; diff --git a/examples/dsp/SVMFunctions_rbfSVM/CMakeLists.txt b/examples/dsp/SVMFunctions_rbfSVM/CMakeLists.txt new file mode 100644 index 00000000..6a0b0998 --- /dev/null +++ b/examples/dsp/SVMFunctions_rbfSVM/CMakeLists.txt @@ -0,0 +1,4 @@ +set(TARGET_REQUIRED_PRIVATE_INCLUDE ${CMAKE_CURRENT_SOURCE_DIR} ${CMAKE_CURRENT_SOURCE_DIR}/..) +set(TARGET_REQUIRED_LIBS nmsis) +set(mains main.c) +generate_bin() \ No newline at end of file diff --git a/examples/dsp/SVMFunctions_rbfSVM/main.c b/examples/dsp/SVMFunctions_rbfSVM/main.c new file mode 100644 index 00000000..885ae51f --- /dev/null +++ b/examples/dsp/SVMFunctions_rbfSVM/main.c @@ -0,0 +1,116 @@ +#include "riscv_math.h" +#include +#include +#include "../common.h" + +#include "../HelperFunctions/math_helper.c" +#include "../HelperFunctions/ref_helper.c" + +#include +#define DELTAF32 (0.05f) +#define DELTAQ31 (63) +#define DELTAQ15 (1) +#define DELTAQ7 (1) + +int test_flag_error = 0; + +/* + The rbf SVM instance containing all parameters. + Those parameters can be generated with the python library scikit-learn. + */ +riscv_svm_rbf_instance_f32 params; + +/* + Parameters generated by a training of the SVM classifier + using scikit-learn and some random input data. + */ +#define NB_SUPPORT_VECTORS 12 + +/* + Dimension of the vector space. A vector is your feature. + It could, for instance, be the pixels of a picture or the FFT of a signal. + */ +#define VECTOR_DIMENSION 2 + +const float32_t dualCoefficients[NB_SUPPORT_VECTORS]={-1.0f,-0.24755389f,-0.25096047f,-1.0f,0.46499702f,0.0444816f,0.2506171f,0.33291225f,0.40335676f,0.39688342f,0.41563006f,0.18963614f}; /* Dual coefficients */ + +const float32_t supportVectors[NB_SUPPORT_VECTORS*VECTOR_DIMENSION]={0.63477121f,-0.59986042f,-0.12523598f,0.63629978f,0.06312245f,-0.59010787f,-0.45084347f,0.5881345f,2.95843437f,-0.42401806f,-0.59248704f,-2.96471627f,-2.15141529f,-1.92858494f,0.55448567f,3.17860023f,-1.1236758f,2.7331152f,-0.05251905f,-3.00311314f,-2.86027661f,0.78232224f,-2.77279855f,-1.32510909f}; /* Support vectors */ + +/* + Class A is identified with value 0. + Class B is identified with value 1. + + This array is used by the SVM functions to do a conversion and ease the comparison + with the Python code where different values could be used. + */ +const int32_t classes[2]={0,1}; + +int main() +{ + int i; + BENCH_INIT; + /* Array of input data */ + float32_t in[VECTOR_DIMENSION]; + + /* Result of the classifier */ + int32_t result; + + + /* + Initialization of the SVM instance parameters. + Additional parameters (intercept, degree, coef0 and gamma) are also coming from Python. + */ + riscv_svm_rbf_init_f32(¶ms, + NB_SUPPORT_VECTORS, + VECTOR_DIMENSION, + 0.607375f, /* Intercept */ + dualCoefficients, + supportVectors, + classes, + 0.500000f /* Gamma */ + ); + + + /* + Input data. + It is corresponding to a point inside the first class. + */ + in[0] = 0.4f; + in[1] = 0.1f; + BENCH_START(riscv_svm_rbf_predict_f32); + riscv_svm_rbf_predict_f32(¶ms, in, &result); + BENCH_END(riscv_svm_rbf_predict_f32); + /* Result should be 0 : First class */ + if (result != 0) { + BENCH_ERROR(riscv_svm_rbf_predict_f32); + printf("expect: %d, actual: %d\n", 0, result); + test_flag_error = 1; + } + BENCH_STATUS(riscv_svm_rbf_predict_f32); + + /* + This input vector is corresponding to a point inside the second class. + */ + in[0] = 3.0f; + in[1] = 0.0f; + + riscv_svm_rbf_predict_f32(¶ms, in, &result); + + /* Result should be 0 : First class */ + if (result != 1) { + BENCH_ERROR(riscv_svm_rbf_predict_f32); + printf("expect: %d, actual: %d\n", 1, result); + test_flag_error = 1; + } + BENCH_STATUS(riscv_svm_rbf_predict_f32); + + + BENCH_FINISH; + if (test_flag_error) { + printf("test error apprears, please recheck.\n"); + return 1; + } else { + printf("all test are passed. Well done!\n"); + } + return 0; +}; diff --git a/examples/dsp/SVMFunctions_sigmoidSVM/CMakeLists.txt b/examples/dsp/SVMFunctions_sigmoidSVM/CMakeLists.txt new file mode 100644 index 00000000..6a0b0998 --- /dev/null +++ b/examples/dsp/SVMFunctions_sigmoidSVM/CMakeLists.txt @@ -0,0 +1,4 @@ +set(TARGET_REQUIRED_PRIVATE_INCLUDE ${CMAKE_CURRENT_SOURCE_DIR} ${CMAKE_CURRENT_SOURCE_DIR}/..) +set(TARGET_REQUIRED_LIBS nmsis) +set(mains main.c) +generate_bin() \ No newline at end of file diff --git a/examples/dsp/SVMFunctions_sigmoidSVM/main.c b/examples/dsp/SVMFunctions_sigmoidSVM/main.c new file mode 100644 index 00000000..b9af652d --- /dev/null +++ b/examples/dsp/SVMFunctions_sigmoidSVM/main.c @@ -0,0 +1,117 @@ +#include "riscv_math.h" +#include +#include +#include "../common.h" + +#include "../HelperFunctions/math_helper.c" +#include "../HelperFunctions/ref_helper.c" + +#include +#define DELTAF32 (0.05f) +#define DELTAQ31 (63) +#define DELTAQ15 (1) +#define DELTAQ7 (1) + +int test_flag_error = 0; + +/* + The sigmoid SVM instance containing all parameters. + Those parameters can be generated with the python library scikit-learn. + */ +riscv_svm_sigmoid_instance_f32 params; + +/* + Parameters generated by a training of the SVM classifier + using scikit-learn and some random input data. + */ +#define NB_SUPPORT_VECTORS 2 + +/* + Dimension of the vector space. A vector is your feature. + It could, for instance, be the pixels of a picture or the FFT of a signal. + */ +#define VECTOR_DIMENSION 2 + +const float32_t dualCoefficients[NB_SUPPORT_VECTORS]={-0.5006101f,0.5006101f}; /* Dual coefficients */ + +const float32_t supportVectors[NB_SUPPORT_VECTORS*VECTOR_DIMENSION]={-1.33358633f,3.46798561f,-0.56781298f,-2.79117593f}; /* Support vectors */ + +/* + Class A is identified with value 0. + Class B is identified with value 1. + + This array is used by the SVM functions to do a conversion and ease the comparison + with the Python code where different values could be used. + */ +const int32_t classes[2]={0,1}; + +int main() +{ + int i; + BENCH_INIT; + /* Array of input data */ + float32_t in[VECTOR_DIMENSION]; + + /* Result of the classifier */ + int32_t result; + + + /* + Initialization of the SVM instance parameters. + Additional parameters (intercept, degree, coef0 and gamma) are also coming from Python. + */ + riscv_svm_sigmoid_init_f32(¶ms, + NB_SUPPORT_VECTORS, + VECTOR_DIMENSION, + 0.000017f, /* Intercept */ + dualCoefficients, + supportVectors, + classes, + 1.100000f, /* Coef0 */ + 0.500000f /* Gamma */ + ); + + + /* + Input data. + It is corresponding to a point inside the first class. + */ + in[0] = 0.4f; + in[1] = 0.1f; + BENCH_START(riscv_svm_sigmoid_predict_f32); + riscv_svm_sigmoid_predict_f32(¶ms, in, &result); + BENCH_END(riscv_svm_sigmoid_predict_f32); + /* Result should be 0 : First class */ + if (result != 0) { + BENCH_ERROR(riscv_svm_sigmoid_predict_f32); + printf("expect: %d, actual: %d\n", 0, result); + test_flag_error = 1; + } + BENCH_STATUS(riscv_svm_sigmoid_predict_f32); + + /* + This input vector is corresponding to a point inside the second class. + */ + in[0] = 3.0f; + in[1] = 0.0f; + + riscv_svm_sigmoid_predict_f32(¶ms, in, &result); + + /* Result should be 0 : First class */ + if (result != 1) { + BENCH_ERROR(riscv_svm_sigmoid_predict_f32); + printf("expect: %d, actual: %d\n", 1, result); + test_flag_error = 1; + } + BENCH_STATUS(riscv_svm_sigmoid_predict_f32); + + + BENCH_FINISH; + if (test_flag_error) { + printf("test error apprears, please recheck.\n"); + return 1; + } else { + printf("all test are passed. Well done!\n"); + } + return 0; +}; diff --git a/examples/dsp/StatisticsFunctions_part1/CMakeLists.txt b/examples/dsp/StatisticsFunctions_part1/CMakeLists.txt new file mode 100644 index 00000000..f05a2074 --- /dev/null +++ b/examples/dsp/StatisticsFunctions_part1/CMakeLists.txt @@ -0,0 +1,6 @@ +set(TARGET_REQUIRED_PRIVATE_INCLUDE ${CMAKE_CURRENT_SOURCE_DIR} ${CMAKE_CURRENT_SOURCE_DIR}/..) +list(APPEND TARGET_REQUIRED_SRCS absmax.c absmin.c max.c) +list(APPEND TARGET_REQUIRED_SRCS mean.c min.c power.c rms.c std.c var.c) +set(TARGET_REQUIRED_LIBS nmsis) +set(mains main.c) +generate_bin() \ No newline at end of file diff --git a/examples/dsp/StatisticsFunctions_part1/absmax.c b/examples/dsp/StatisticsFunctions_part1/absmax.c new file mode 100644 index 00000000..fd1e8a9f --- /dev/null +++ b/examples/dsp/StatisticsFunctions_part1/absmax.c @@ -0,0 +1,167 @@ +#include "ref.h" + +void ref_absmax_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex) +{ + float32_t maxVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + + /* Initialise index value to zero. */ + outIndex = 0U; + + /* Load first input value that act as reference value for comparision */ + out = fabsf(*pSrc++); + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal = fabsf(*pSrc++); + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the maximum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} + +void ref_absmax_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex) +{ + q7_t maxVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + + + /* Initialise index value to zero. */ + outIndex = 0U; + /* Load first input value that act as reference value for comparision */ + out = (*pSrc > 0) ? *pSrc : ((*pSrc == (q7_t) 0x80) ? (q7_t) 0x7f : -*pSrc); + pSrc++; + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal = (*pSrc > 0) ? *pSrc : ((*pSrc == (q7_t) 0x80) ? (q7_t) 0x7f : -*pSrc); + pSrc++; + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the maximum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} + +void ref_absmax_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex) +{ + q15_t maxVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + + /* Initialise index value to zero. */ + outIndex = 0U; + /* Load first input value that act as reference value for comparision */ + out = (*pSrc > 0) ? *pSrc : ((*pSrc == (q15_t) 0x8000) ? 0x7fff : -*pSrc); + pSrc++; + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal = (*pSrc > 0) ? *pSrc : ((*pSrc == (q15_t) 0x8000) ? 0x7fff : -*pSrc); + pSrc++; + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the maximum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} + +void ref_absmax_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex) +{ + q31_t maxVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + + + /* Initialise index value to zero. */ + outIndex = 0U; + /* Load first input value that act as reference value for comparision */ + out = (*pSrc > 0) ? *pSrc : ((*pSrc == INT32_MIN) ? INT32_MAX : -*pSrc); + pSrc++; + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal = (*pSrc > 0) ? *pSrc : ((*pSrc == INT32_MIN) ? INT32_MAX : -*pSrc); + pSrc++; + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the maximum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} diff --git a/examples/dsp/StatisticsFunctions_part1/absmin.c b/examples/dsp/StatisticsFunctions_part1/absmin.c new file mode 100644 index 00000000..55806a78 --- /dev/null +++ b/examples/dsp/StatisticsFunctions_part1/absmin.c @@ -0,0 +1,165 @@ +#include "ref.h" + +void ref_absmin_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex) +{ + float32_t minVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + + /* Initialise index value to zero. */ + outIndex = 0U; + + /* Load first input value that act as reference value for comparision */ + out = fabsf(*pSrc++); + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal = fabsf(*pSrc++); + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the minimum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} + +void ref_absmin_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex) +{ + q7_t minVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + + /* Initialise index value to zero. */ + outIndex = 0U; + /* Load first input value that act as reference value for comparision */ + out = (*pSrc > 0) ? *pSrc : ((*pSrc == (q7_t) 0x80) ? (q7_t) 0x7f : -*pSrc); + pSrc++; + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal = (*pSrc > 0) ? *pSrc : ((*pSrc == (q7_t) 0x80) ? (q7_t) 0x7f : -*pSrc); + pSrc++; + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the minimum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} + +void ref_absmin_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex) +{ + q15_t minVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + + + /* Initialise index value to zero. */ + outIndex = 0U; + /* Load first input value that act as reference value for comparision */ + out = (*pSrc > 0) ? *pSrc : ((*pSrc == (q15_t) 0x8000) ? 0x7fff : -*pSrc); + pSrc++; + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal = (*pSrc > 0) ? *pSrc : ((*pSrc == (q15_t) 0x8000) ? 0x7fff : -*pSrc); + pSrc++; + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the minimum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} + +void ref_absmin_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex) +{ + q31_t minVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + + /* Initialise index value to zero. */ + outIndex = 0U; + /* Load first input value that act as reference value for comparision */ + out = (*pSrc > 0) ? *pSrc : ((*pSrc == INT32_MIN) ? INT32_MAX : -*pSrc); + pSrc++; + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal = (*pSrc > 0) ? *pSrc : ((*pSrc == INT32_MIN) ? INT32_MAX : -*pSrc); + pSrc++; + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the minimum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} diff --git a/examples/dsp/StatisticsFunctions_part1/array.h b/examples/dsp/StatisticsFunctions_part1/array.h new file mode 100644 index 00000000..9eefaad0 --- /dev/null +++ b/examples/dsp/StatisticsFunctions_part1/array.h @@ -0,0 +1,11 @@ +// Array for StatisticsFunctions part1 +#define ARRAY_SIZE 230 + +float32_t f32_array[ARRAY_SIZE] = { +-94.118553, 91.433388, -2.924870, 60.056095, -71.622734, -15.647743, 83.147102, 58.441467, 99.898483, 31.148140, -92.857666, 69.825859, 86.798653, 35.747032, 51.548027, 48.626495, -21.554596, 31.095577, -65.762665, 41.209217, -93.633430, -44.615402, -90.765724, 0}; +q7_t q7_array[ARRAY_SIZE] = { +-104, 82, 49, -47, 115, -120, -16, -31, 67, 75, -81, -3, -14, 37, 53, 65, -58, 46, 39, -87, -98, -1, 117, 0}; +q15_t q15_array[ARRAY_SIZE] = { +-41, 21, -71, 64, -63, 1, 50, 100, 117, 12, -93, -90, -63, 87, -63, 80, -66, 109, -39, -78, -64, 29, -7, 0}; +q31_t q31_array[ARRAY_SIZE] = { +-9722, 21681, 5587, 3258, 27341, -14036, 16855, 16628, -7836, 4444, -27797, -29233, 2018, 18295, 28443, -24255, 4510, -2007, -31988, -10675, -22140, 19286, -12373, 0}; diff --git a/examples/dsp/StatisticsFunctions_part1/main.c b/examples/dsp/StatisticsFunctions_part1/main.c new file mode 100644 index 00000000..11b1b885 --- /dev/null +++ b/examples/dsp/StatisticsFunctions_part1/main.c @@ -0,0 +1,484 @@ +// +// Created by lujun on 19-6-28.DELTAF32 +// + +#include "riscv_math.h" +#include "array.h" +#include +#include +#include "../common.h" + +#include "../HelperFunctions/math_helper.c" +#include "../HelperFunctions/ref_helper.c" + +#include +#define DELTAF32 (0.05f) +#define DELTAQ31 (63) +#define DELTAQ15 (1) +#define DELTAQ7 (1) + +#define ENABLE_ALL +#define F32 +#define Q31 +#define Q15 +#define Q7 + +int test_flag_error = 0; + +int main() +{ + q63_t q63_out, q63_out_ref; + float32_t f32_out, f32_out_ref; + q31_t q31_out, q31_out_ref; + q15_t q15_out, q15_out_ref; + q7_t q7_out, q7_out_ref; + uint32_t index, index_ref; + + BENCH_INIT; +#if defined F32 || defined ENABLE_ALL + //***************************** f32 ************************* + // max + BENCH_START(riscv_max_f32); + riscv_max_f32(f32_array, ARRAY_SIZE, &f32_out, &index); + BENCH_END(riscv_max_f32); + ref_max_f32(f32_array, ARRAY_SIZE, &f32_out_ref, &index_ref); + if ((fabs(f32_out - f32_out_ref) > DELTAF32) || (index != index_ref)) { + BENCH_ERROR(riscv_max_f32); + printf("value expect: %f, actual: %f\nindex expect: %f, actual: %f", + f32_out_ref, f32_out, index_ref, index); + test_flag_error = 1; + } + BENCH_STATUS(riscv_max_f32); + // max_no_idx + BENCH_START(riscv_max_no_idx_f32); + riscv_max_no_idx_f32(f32_array, ARRAY_SIZE, &f32_out); + BENCH_END(riscv_max_no_idx_f32); + ref_max_no_idx_f32(f32_array, ARRAY_SIZE, &f32_out_ref); + if ((fabs(f32_out - f32_out_ref) > DELTAF32) ) { + BENCH_ERROR(riscv_max_no_idx_f32); + printf("value expect: %f, actual: %f\nindex expect: %f, actual: %f", + f32_out_ref, f32_out); + test_flag_error = 1; + } + BENCH_STATUS(riscv_max_no_idx_f32); + // mean + BENCH_START(riscv_mean_f32); + riscv_mean_f32(f32_array, ARRAY_SIZE, &f32_out); + BENCH_END(riscv_mean_f32); + ref_mean_f32(f32_array, ARRAY_SIZE, &f32_out_ref); + if (fabs(f32_out - f32_out_ref) > DELTAF32) { + BENCH_ERROR(riscv_mean_f32); + printf("expect: %f, actual: %f\n", f32_out_ref, f32_out); + test_flag_error = 1; + } + BENCH_STATUS(riscv_mean_f32); + // min + BENCH_START(riscv_min_f32); + riscv_min_f32(f32_array, ARRAY_SIZE, &f32_out, &index); + BENCH_END(riscv_min_f32); + ref_min_f32(f32_array, ARRAY_SIZE, &f32_out_ref, &index_ref); + if ((fabs(f32_out - f32_out_ref) > DELTAF32) || (index != index_ref)) { + BENCH_ERROR(riscv_min_f32); + printf("value expect: %f, actual: %f\nindex expect: %f, actual: %f", + f32_out_ref, f32_out, index_ref, index); + test_flag_error = 1; + } + BENCH_STATUS(riscv_min_f32); + // power + BENCH_START(riscv_power_f32); + riscv_power_f32(f32_array, ARRAY_SIZE, &f32_out); + BENCH_END(riscv_power_f32); + ref_power_f32(f32_array, ARRAY_SIZE, &f32_out_ref); + for (int i = 0; i < ARRAY_SIZE; i++) + if (fabs(f32_out - f32_out_ref) > DELTAF32) { + BENCH_ERROR(riscv_power_f32); + printf("index: %d, expect: %f, actual: %f\n", i, f32_out_ref, + f32_out); + test_flag_error = 1; + } + BENCH_STATUS(riscv_power_f32); + // rms + BENCH_START(riscv_rms_f32); + riscv_rms_f32(f32_array, ARRAY_SIZE, &f32_out); + BENCH_END(riscv_rms_f32); + ref_rms_f32(f32_array, ARRAY_SIZE, &f32_out_ref); + if (fabs(f32_out - f32_out_ref) > DELTAF32) { + BENCH_ERROR(riscv_rms_f32); + printf("expect: %f, actual: %f\n", f32_out_ref, f32_out); + test_flag_error = 1; + } + BENCH_STATUS(riscv_rms_f32); + // std + BENCH_START(riscv_std_f32); + riscv_std_f32(f32_array, ARRAY_SIZE, &f32_out); + BENCH_END(riscv_std_f32); + ref_std_f32(f32_array, ARRAY_SIZE, &f32_out_ref); + if (fabs(f32_out - f32_out_ref) > DELTAF32) { + BENCH_ERROR(riscv_std_f32); + printf("expect: %f, actual: %f\n", f32_out_ref, f32_out); + test_flag_error = 1; + } + BENCH_STATUS(riscv_std_f32); + // var + BENCH_START(riscv_var_f32); + riscv_var_f32(f32_array, ARRAY_SIZE, &f32_out); + BENCH_END(riscv_var_f32); + ref_var_f32(f32_array, ARRAY_SIZE, &f32_out_ref); + if (fabs(f32_out - f32_out_ref) > DELTAF32) { + BENCH_ERROR(riscv_var_f32); + printf("expect: %f, actual: %f\n", f32_out_ref, f32_out); + test_flag_error = 1; + } + BENCH_STATUS(riscv_var_f32); + //absmax + BENCH_START(riscv_absmax_f32); + riscv_absmax_f32(f32_array, ARRAY_SIZE, &f32_out, &index); + BENCH_END(riscv_absmax_f32); + ref_absmax_f32(f32_array, ARRAY_SIZE, &f32_out_ref, &index_ref); + if (fabs(f32_out - f32_out_ref) > DELTAF32) { + BENCH_ERROR(riscv_absmax_f32); + printf("expect: %f, actual: %f\n", f32_out_ref, f32_out); + test_flag_error = 1; + } + if (fabs(index - index_ref) > DELTAF32) { + BENCH_ERROR(riscv_absmax_f32); + printf("expect: %f, actual: %f\n", index_ref, index); + test_flag_error = 1; + } + BENCH_STATUS(riscv_absmax_f32); + //absmin + BENCH_START(riscv_absmin_f32); + riscv_absmin_f32(f32_array, ARRAY_SIZE, &f32_out, &index); + BENCH_END(riscv_absmin_f32); + ref_absmin_f32(f32_array, ARRAY_SIZE, &f32_out_ref, &index_ref); + if (fabs(f32_out - f32_out_ref) > DELTAF32) { + BENCH_ERROR(riscv_absmin_f32); + printf("expect: %f, actual: %f\n", f32_out_ref, f32_out); + test_flag_error = 1; + } + if (fabs(index - index_ref) > DELTAF32) { + BENCH_ERROR(riscv_absmin_f32); + printf("expect: %d, actual: %d\n", index_ref, index); + test_flag_error = 1; + } + BENCH_STATUS(riscv_absmin_f32); +#endif +#if defined Q31 || defined ENABLE_ALL + // ********************************* q31 ***************************** + // max + BENCH_START(riscv_max_q31); + riscv_max_q31(q31_array, ARRAY_SIZE, &q31_out, &index); + BENCH_END(riscv_max_q31); + ref_max_q31(q31_array, ARRAY_SIZE, &q31_out_ref, &index_ref); + if ((labs(q31_out - q31_out_ref) > DELTAQ31) || (index != index_ref)) { + BENCH_ERROR(riscv_max_q31); + printf("value expect: %x, actual: %x\nindex expect: %x, actual: %x\n", + q31_out_ref, q31_out, index_ref, index); + test_flag_error = 1; + } + BENCH_STATUS(riscv_max_q31); + // mean + BENCH_START(riscv_mean_q31); + riscv_mean_q31(q31_array, ARRAY_SIZE, &q31_out); + BENCH_END(riscv_mean_q31); + ref_mean_q31(q31_array, ARRAY_SIZE, &q31_out_ref); + if (labs(q31_out - q31_out_ref) > DELTAQ31) { + BENCH_ERROR(riscv_mean_q31); + printf("expect: %x, actual: %x\n", q31_out_ref, q31_out); + test_flag_error = 1; + } + BENCH_STATUS(riscv_mean_q31); + // min + BENCH_START(riscv_min_q31); + riscv_min_q31(q31_array, ARRAY_SIZE, &q31_out, &index); + BENCH_END(riscv_min_q31); + ref_min_q31(q31_array, ARRAY_SIZE, &q31_out_ref, &index_ref); + if ((labs(q31_out - q31_out_ref) > DELTAQ31) || (index != index_ref)) { + BENCH_ERROR(riscv_min_q31); + printf("value expect: %x, actual: %x\nindex expect: %d, actual: %d", + q31_out_ref, q31_out, index_ref, index); + test_flag_error = 1; + } + BENCH_STATUS(riscv_min_q31); + // power + BENCH_START(riscv_power_q31); + riscv_power_q31(q31_array, ARRAY_SIZE, &q63_out); + BENCH_END(riscv_power_q31); + ref_power_q31(q31_array, ARRAY_SIZE, &q63_out_ref); + if (labs(q31_out - q31_out_ref) > DELTAQ31) { + BENCH_ERROR(riscv_power_q31); + printf("expect: %x, actual: %x\n", q63_out_ref, q63_out); + test_flag_error = 1; + } + BENCH_STATUS(riscv_power_q31); + // rms + BENCH_START(riscv_rms_q31); + riscv_rms_q31(q31_array, ARRAY_SIZE, &q31_out); + BENCH_END(riscv_rms_q31); + ref_rms_q31(q31_array, ARRAY_SIZE, &q31_out_ref); + if (labs(q31_out - q31_out_ref) > DELTAQ31) { + BENCH_ERROR(riscv_rms_q31); + printf("expect: %x, actual: %x\n", q31_out_ref, q31_out); + test_flag_error = 1; + } + BENCH_STATUS(riscv_rms_q31); + // std + BENCH_START(riscv_std_q31); + riscv_std_q31(q31_array, ARRAY_SIZE, &q31_out); + BENCH_END(riscv_std_q31); + ref_std_q31(q31_array, ARRAY_SIZE, &q31_out_ref); + if (labs(q31_out - q31_out_ref) > DELTAQ31) { + BENCH_ERROR(riscv_std_q31); + printf("expect: %x, actual: %x\n", q31_out_ref, q31_out); + test_flag_error = 1; + } + BENCH_STATUS(riscv_std_q31); + // var + BENCH_START(riscv_var_q31); + riscv_var_q31(q31_array, ARRAY_SIZE, &q31_out); + BENCH_END(riscv_var_q31); + ref_var_q31(q31_array, ARRAY_SIZE, &q31_out_ref); + if (labs(q31_out - q31_out_ref) > DELTAQ31) { + BENCH_ERROR(riscv_var_q31); + printf("expect: %x, actual: %x\n", q31_out_ref, q31_out); + test_flag_error = 1; + } + BENCH_STATUS(riscv_var_q31); + //absmax + BENCH_START(riscv_absmax_q31); + riscv_absmax_q31(q31_array, ARRAY_SIZE, &q31_out, &index); + BENCH_END(riscv_absmax_q31); + ref_absmax_q31(q31_array, ARRAY_SIZE, &q31_out_ref, &index_ref); + if (fabs(q31_out - q31_out_ref) > DELTAQ31) { + BENCH_ERROR(riscv_absmax_q31); + printf("expect: %f, actual: %f\n", q31_out_ref, q31_out); + test_flag_error = 1; + } + if (fabs(index - index_ref) > DELTAQ31) { + BENCH_ERROR(riscv_absmax_q31); + printf("expect: %f, actual: %f\n", index_ref, index); + test_flag_error = 1; + } + BENCH_STATUS(riscv_absmax_q31); + //absmin + BENCH_START(riscv_absmin_q31); + riscv_absmin_q31(q31_array, ARRAY_SIZE, &q31_out, &index); + BENCH_END(riscv_absmin_q31); + ref_absmin_q31(q31_array, ARRAY_SIZE, &q31_out_ref, &index_ref); + if (fabs(q31_out - q31_out_ref) > DELTAQ31) { + BENCH_ERROR(riscv_absmin_q31); + printf("expect: %f, actual: %f\n", q31_out_ref, q31_out); + test_flag_error = 1; + } + if (fabs(index - index_ref) > DELTAQ31) { + BENCH_ERROR(riscv_absmin_q31); + printf("expect: %f, actual: %f\n", index_ref, index); + test_flag_error = 1; + } + BENCH_STATUS(riscv_absmin_q31); +#endif +#if defined Q15 || defined ENABLE_ALL + // ********************************* q15 ***************************** + // max + BENCH_START(riscv_max_q15); + riscv_max_q15(q15_array, ARRAY_SIZE, &q15_out, &index); + BENCH_END(riscv_max_q15); + ref_max_q15(q15_array, ARRAY_SIZE, &q15_out_ref, &index_ref); + if ((abs(q15_out - q15_out_ref) > DELTAQ15) || (index != index_ref)) { + BENCH_ERROR(riscv_max_q15); + printf("value expect: %x, actual: %x\nindex expect: %d, actual: %d", + q15_out_ref, q15_out, index_ref, index); + test_flag_error = 1; + } + BENCH_STATUS(riscv_max_q15); + // mean + BENCH_START(riscv_mean_q15); + riscv_mean_q15(q15_array, ARRAY_SIZE, &q15_out); + BENCH_END(riscv_mean_q15); + ref_mean_q15(q15_array, ARRAY_SIZE, &q15_out_ref); + if (abs(q15_out - q15_out_ref) > DELTAQ15) { + BENCH_ERROR(riscv_mean_q15); + printf("expect: %x, actual: %x\n", q15_out_ref, q15_out); + test_flag_error = 1; + } + BENCH_STATUS(riscv_mean_q15); + // min + BENCH_START(riscv_min_q15); + riscv_min_q15(q15_array, ARRAY_SIZE, &q15_out, &index); + BENCH_END(riscv_min_q15); + ref_min_q15(q15_array, ARRAY_SIZE, &q15_out_ref, &index_ref); + if ((abs(q15_out - q15_out_ref) > DELTAQ15) || (index != index_ref)) { + BENCH_ERROR(riscv_min_q15); + printf("value expect: %x, actual: %x\nindex expect: %d, actual: %d", + q15_out_ref, q15_out, index_ref, index); + test_flag_error = 1; + } + BENCH_STATUS(riscv_min_q15); + // power + BENCH_START(riscv_power_q15); + riscv_power_q15(q15_array, ARRAY_SIZE, &q63_out); + BENCH_END(riscv_power_q15); + ref_power_q15(q15_array, ARRAY_SIZE, &q63_out_ref); + if (abs(q15_out - q15_out_ref) > DELTAQ15) { + BENCH_ERROR(riscv_power_q15); + printf("expect: %x, actual: %x\n", q63_out_ref, q63_out); + test_flag_error = 1; + } + BENCH_STATUS(riscv_power_q15); + // rms + BENCH_START(riscv_rms_q15); + riscv_rms_q15(q15_array, ARRAY_SIZE, &q15_out); + BENCH_END(riscv_rms_q15); + ref_rms_q15(q15_array, ARRAY_SIZE, &q15_out_ref); + if (abs(q15_out - q15_out_ref) > DELTAQ15) { + BENCH_ERROR(riscv_rms_q15); + printf("expect: %x, actual: %x\n", q15_out_ref, q15_out); + test_flag_error = 1; + } + BENCH_STATUS(riscv_rms_q15); + // std + BENCH_START(riscv_std_q15); + riscv_std_q15(q15_array, ARRAY_SIZE, &q15_out); + BENCH_END(riscv_std_q15); + ref_std_q15(q15_array, ARRAY_SIZE, &q15_out_ref); + if (abs(q15_out - q15_out_ref) > DELTAQ15) { + BENCH_ERROR(riscv_std_q15); + printf("expect: %x, actual: %x\n", q15_out_ref, q15_out); + test_flag_error = 1; + } + BENCH_STATUS(riscv_std_q15); + // var + BENCH_START(riscv_var_q15); + riscv_var_q15(q15_array, ARRAY_SIZE, &q15_out); + BENCH_END(riscv_var_q15); + ref_var_q15(q15_array, ARRAY_SIZE, &q15_out_ref); + if (abs(q15_out - q15_out_ref) > DELTAQ15) { + BENCH_ERROR(riscv_var_q15); + printf("expect: %x, actual: %x\n", q15_out_ref, q15_out); + test_flag_error = 1; + } + BENCH_STATUS(riscv_var_q15); + //absmax + BENCH_START(riscv_absmax_q15); + riscv_absmax_q15(q15_array, ARRAY_SIZE, &q15_out, &index); + BENCH_END(riscv_absmax_q15); + ref_absmax_q15(q15_array, ARRAY_SIZE, &q15_out_ref, &index_ref); + if (fabs(q15_out - q15_out_ref) > DELTAQ15) { + BENCH_ERROR(riscv_absmax_q15); + printf("expect: %f, actual: %f\n", q15_out_ref, q15_out); + test_flag_error = 1; + } + if (fabs(index - index_ref) > DELTAQ15) { + BENCH_ERROR(riscv_absmax_q15); + printf("expect: %f, actual: %f\n", index_ref, index); + test_flag_error = 1; + } + BENCH_STATUS(riscv_absmax_q15); + //absmin + BENCH_START(riscv_absmin_q15); + riscv_absmin_q15(q15_array, ARRAY_SIZE, &q15_out, &index); + BENCH_END(riscv_absmin_q15); + ref_absmin_q15(q15_array, ARRAY_SIZE, &q15_out_ref, &index_ref); + if (fabs(q15_out - q15_out_ref) > DELTAQ15) { + BENCH_ERROR(riscv_absmin_q15); + printf("expect: %f, actual: %f\n", q15_out_ref, q15_out); + test_flag_error = 1; + } + if (fabs(index - index_ref) > DELTAQ15) { + BENCH_ERROR(riscv_absmin_q15); + printf("expect: %f, actual: %f\n", index_ref, index); + test_flag_error = 1; + } + BENCH_STATUS(riscv_absmin_q15); +#endif +#if defined Q7 || defined ENABLE_ALL + // ********************************* q7 ***************************** + // max + BENCH_START(riscv_max_q7); + riscv_max_q7(q7_array, ARRAY_SIZE, &q7_out, &index); + BENCH_END(riscv_max_q7); + ref_max_q7(q7_array, ARRAY_SIZE, &q7_out_ref, &index_ref); + if ((abs(q7_out - q7_out_ref) > DELTAQ7) || (index != index_ref)) { + BENCH_ERROR(riscv_max_q7); + printf("value expect: %x, actual: %x\nindex expect: %d, actual: %d", + q7_out_ref, q7_out, index_ref, index); + test_flag_error = 1; + } + BENCH_STATUS(riscv_max_q7); + // mean + BENCH_START(riscv_mean_q7); + riscv_mean_q7(q7_array, ARRAY_SIZE, &q7_out); + BENCH_END(riscv_mean_q7); + ref_mean_q7(q7_array, ARRAY_SIZE, &q7_out_ref); + if (abs(q7_out - q7_out_ref) > DELTAQ7) { + BENCH_ERROR(riscv_mean_q7); + printf("expect: %x, actual: %x\n", q7_out_ref, q7_out); + test_flag_error = 1; + } + BENCH_STATUS(riscv_mean_q7); + // min + BENCH_START(riscv_min_q7); + riscv_min_q7(q7_array, ARRAY_SIZE, &q7_out, &index); + BENCH_END(riscv_min_q7); + ref_min_q7(q7_array, ARRAY_SIZE, &q7_out_ref, &index_ref); + if ((abs(q7_out - q7_out_ref) > DELTAQ7) || (index != index_ref)) { + BENCH_ERROR(riscv_min_q7); + printf("value expect: %x, actual: %x\nindex expect: %d, actual: %d", + q7_out_ref, q7_out, index_ref, index); + test_flag_error = 1; + } + BENCH_STATUS(riscv_min_q7); + // power + BENCH_START(riscv_power_q7); + riscv_power_q7(q7_array, ARRAY_SIZE, &q31_out); + BENCH_END(riscv_power_q7); + ref_power_q7(q7_array, ARRAY_SIZE, &q31_out_ref); + if (abs(q31_out - q31_out_ref) > DELTAQ7) { + BENCH_ERROR(riscv_power_q7); + printf("expect: %x, actual: %x\n", q63_out_ref, q63_out); + test_flag_error = 1; + } + BENCH_STATUS(riscv_power_q7); + //absmax + BENCH_START(riscv_absmax_q7); + riscv_absmax_q7(q7_array, ARRAY_SIZE, &q7_out, &index); + BENCH_END(riscv_absmax_q7); + ref_absmax_q7(q7_array, ARRAY_SIZE, &q7_out_ref, &index_ref); + if (fabs(q7_out - q7_out_ref) > DELTAQ7) { + BENCH_ERROR(riscv_absmax_q7); + printf("expect: %f, actual: %f\n", q7_out_ref, q7_out); + test_flag_error = 1; + } + if (fabs(index - index_ref) > DELTAQ7) { + BENCH_ERROR(riscv_absmax_q7); + printf("expect: %f, actual: %f\n", index_ref, index); + test_flag_error = 1; + } + BENCH_STATUS(riscv_absmax_q7); + //absmin + BENCH_START(riscv_absmin_q7); + riscv_absmin_q7(q7_array, ARRAY_SIZE, &q7_out, &index); + BENCH_END(riscv_absmin_q7); + ref_absmin_q7(q7_array, ARRAY_SIZE, &q7_out_ref, &index_ref); + if (fabs(q7_out - q7_out_ref) > DELTAQ7) { + BENCH_ERROR(riscv_absmin_q7); + printf("expect: %f, actual: %f\n", q7_out_ref, q7_out); + test_flag_error = 1; + } + if (fabs(index - index_ref) > DELTAQ7) { + BENCH_ERROR(riscv_absmin_q7); + printf("expect: %f, actual: %f\n", index_ref, index); + test_flag_error = 1; + } + BENCH_STATUS(riscv_absmin_q7); + printf("all tests are passed,well done!\n"); +#endif + BENCH_FINISH; + if (test_flag_error) { + printf("test error apprears, please recheck.\n"); + return 1; + } else { + printf("all test are passed. Well done!\n"); + } + return 0; +} diff --git a/examples/dsp/StatisticsFunctions_part1/max.c b/examples/dsp/StatisticsFunctions_part1/max.c new file mode 100644 index 00000000..ac2b3574 --- /dev/null +++ b/examples/dsp/StatisticsFunctions_part1/max.c @@ -0,0 +1,77 @@ +#include "ref.h" + +void ref_max_f32(float32_t *pSrc, uint32_t blockSize, float32_t *pResult, + uint32_t *pIndex) +{ + uint32_t i, ind = 0; + float32_t max = -FLT_MAX; + + for (i = 0; i < blockSize; i++) { + if (max < pSrc[i]) { + max = pSrc[i]; + ind = i; + } + } + *pResult = max; + *pIndex = ind; +} + +void ref_max_no_idx_f32(float32_t *pSrc, uint32_t blockSize, float32_t *pResult) +{ + uint32_t i = 0; + float32_t max = -FLT_MAX; + + for (i = 0; i < blockSize; i++) { + if (max < pSrc[i]) { + max = pSrc[i]; + } + } + *pResult = max; +} + +void ref_max_q31(q31_t *pSrc, uint32_t blockSize, q31_t *pResult, + uint32_t *pIndex) +{ + uint32_t i, ind = 0; + q31_t max = INT_MIN; + + for (i = 0; i < blockSize; i++) { + if (max < pSrc[i]) { + max = pSrc[i]; + ind = i; + } + } + *pResult = max; + *pIndex = ind; +} + +void ref_max_q15(q15_t *pSrc, uint32_t blockSize, q15_t *pResult, + uint32_t *pIndex) +{ + uint32_t i, ind = 0; + q15_t max = SHRT_MIN; + + for (i = 0; i < blockSize; i++) { + if (max < pSrc[i]) { + max = pSrc[i]; + ind = i; + } + } + *pResult = max; + *pIndex = ind; +} + +void ref_max_q7(q7_t *pSrc, uint32_t blockSize, q7_t *pResult, uint32_t *pIndex) +{ + uint32_t i, ind = 0; + q7_t max = SCHAR_MIN; + + for (i = 0; i < blockSize; i++) { + if (max < pSrc[i]) { + max = pSrc[i]; + ind = i; + } + } + *pResult = max; + *pIndex = ind; +} diff --git a/examples/dsp/StatisticsFunctions_part1/mean.c b/examples/dsp/StatisticsFunctions_part1/mean.c new file mode 100644 index 00000000..965b0b2b --- /dev/null +++ b/examples/dsp/StatisticsFunctions_part1/mean.c @@ -0,0 +1,45 @@ +#include "ref.h" + +void ref_mean_f32(float32_t *pSrc, uint32_t blockSize, float32_t *pResult) +{ + uint32_t i; + float32_t sum = 0; + + for (i = 0; i < blockSize; i++) { + sum += pSrc[i]; + } + *pResult = sum / (float32_t)blockSize; +} + +void ref_mean_q31(q31_t *pSrc, uint32_t blockSize, q31_t *pResult) +{ + uint32_t i; + q63_t sum = 0; + + for (i = 0; i < blockSize; i++) { + sum += pSrc[i]; + } + *pResult = (q31_t)(sum / (int32_t)blockSize); +} + +void ref_mean_q15(q15_t *pSrc, uint32_t blockSize, q15_t *pResult) +{ + uint32_t i; + q31_t sum = 0; + + for (i = 0; i < blockSize; i++) { + sum += pSrc[i]; + } + *pResult = (q15_t)(sum / (int32_t)blockSize); +} + +void ref_mean_q7(q7_t *pSrc, uint32_t blockSize, q7_t *pResult) +{ + uint32_t i; + q31_t sum = 0; + + for (i = 0; i < blockSize; i++) { + sum += pSrc[i]; + } + *pResult = (q7_t)(sum / (int32_t)blockSize); +} diff --git a/examples/dsp/StatisticsFunctions_part1/min.c b/examples/dsp/StatisticsFunctions_part1/min.c new file mode 100644 index 00000000..94791f47 --- /dev/null +++ b/examples/dsp/StatisticsFunctions_part1/min.c @@ -0,0 +1,64 @@ +#include "ref.h" + +void ref_min_f32(float32_t *pSrc, uint32_t blockSize, float32_t *pResult, + uint32_t *pIndex) +{ + uint32_t i, ind = 0; + float32_t min = FLT_MAX; + + for (i = 0; i < blockSize; i++) { + if (min > pSrc[i]) { + min = pSrc[i]; + ind = i; + } + } + *pResult = min; + *pIndex = ind; +} + +void ref_min_q31(q31_t *pSrc, uint32_t blockSize, q31_t *pResult, + uint32_t *pIndex) +{ + uint32_t i, ind = 0; + q31_t min = INT_MAX; + + for (i = 0; i < blockSize; i++) { + if (min > pSrc[i]) { + min = pSrc[i]; + ind = i; + } + } + *pResult = min; + *pIndex = ind; +} + +void ref_min_q15(q15_t *pSrc, uint32_t blockSize, q15_t *pResult, + uint32_t *pIndex) +{ + uint32_t i, ind = 0; + q15_t min = SHRT_MAX; + + for (i = 0; i < blockSize; i++) { + if (min > pSrc[i]) { + min = pSrc[i]; + ind = i; + } + } + *pResult = min; + *pIndex = ind; +} + +void ref_min_q7(q7_t *pSrc, uint32_t blockSize, q7_t *pResult, uint32_t *pIndex) +{ + uint32_t i, ind = 0; + q7_t min = SCHAR_MAX; + + for (i = 0; i < blockSize; i++) { + if (min > pSrc[i]) { + min = pSrc[i]; + ind = i; + } + } + *pResult = min; + *pIndex = ind; +} diff --git a/examples/dsp/StatisticsFunctions_part1/power.c b/examples/dsp/StatisticsFunctions_part1/power.c new file mode 100644 index 00000000..aa719777 --- /dev/null +++ b/examples/dsp/StatisticsFunctions_part1/power.c @@ -0,0 +1,45 @@ +#include "ref.h" + +void ref_power_f32(float32_t *pSrc, uint32_t blockSize, float32_t *pResult) +{ + uint32_t i; + float32_t sumsq = 0; + + for (i = 0; i < blockSize; i++) { + sumsq += pSrc[i] * pSrc[i]; + } + *pResult = sumsq; +} + +void ref_power_q31(q31_t *pSrc, uint32_t blockSize, q63_t *pResult) +{ + uint32_t i; + q63_t sumsq = 0; + + for (i = 0; i < blockSize; i++) { + sumsq += ((q63_t)pSrc[i] * pSrc[i]) >> 14; + } + *pResult = sumsq; +} + +void ref_power_q15(q15_t *pSrc, uint32_t blockSize, q63_t *pResult) +{ + uint32_t i; + q63_t sumsq = 0; + + for (i = 0; i < blockSize; i++) { + sumsq += (q63_t)pSrc[i] * pSrc[i]; + } + *pResult = sumsq; +} + +void ref_power_q7(q7_t *pSrc, uint32_t blockSize, q31_t *pResult) +{ + uint32_t i; + q31_t sumsq = 0; + + for (i = 0; i < blockSize; i++) { + sumsq += (q31_t)pSrc[i] * pSrc[i]; + } + *pResult = sumsq; +} diff --git a/examples/dsp/StatisticsFunctions_part1/rms.c b/examples/dsp/StatisticsFunctions_part1/rms.c new file mode 100644 index 00000000..32c11ed1 --- /dev/null +++ b/examples/dsp/StatisticsFunctions_part1/rms.c @@ -0,0 +1,54 @@ +#include "ref.h" + +void ref_rms_f32(float32_t *pSrc, uint32_t blockSize, float32_t *pResult) +{ + uint32_t i; + float32_t sumsq = 0; + + for (i = 0; i < blockSize; i++) { + sumsq += pSrc[i] * pSrc[i]; + } + *pResult = sqrtf(sumsq / (float32_t)blockSize); +} + +void ref_rms_q31(q31_t *pSrc, uint32_t blockSize, q31_t *pResult) +{ + uint32_t i; + uint64_t sumsq = 0; /* accumulator (can get never negative. changed type + from q63 to uint64 */ + q63_t tmp1; + q31_t tmp2; + + float help_float; + + for (i = 0; i < blockSize; i++) { + sumsq += (q63_t)pSrc[i] * pSrc[i]; + } + tmp1 = (sumsq / (q63_t)blockSize) >> 31; + tmp2 = ref_sat_q31(tmp1); + + /* GCC M0 problem: __aeabi_f2iz(QNAN) returns not 0 */ + help_float = (sqrtf((float)tmp2 / 2147483648.0f) * 2147483648.0f); + /* Checking for a NAN value in help_float */ + if (((*((int *)(&help_float))) & 0x7FC00000) == 0x7FC00000) { + help_float = 0; + } + *pResult = (q31_t)(help_float); + + // *pResult = (q31_t)(sqrtf((float)tmp2 / 2147483648.0f) * 2147483648.0f); +} + +void ref_rms_q15(q15_t *pSrc, uint32_t blockSize, q15_t *pResult) +{ + uint32_t i; + q63_t sumsq = 0; + q31_t tmp1; + q15_t tmp2; + + for (i = 0; i < blockSize; i++) { + sumsq += (q63_t)pSrc[i] * pSrc[i]; + } + tmp1 = (sumsq / (q63_t)blockSize) >> 15; + tmp2 = ref_sat_q15(tmp1); + *pResult = (q15_t)(sqrtf((float)tmp2 / 32768.0f) * 32768.0f); +} diff --git a/examples/dsp/StatisticsFunctions_part1/std.c b/examples/dsp/StatisticsFunctions_part1/std.c new file mode 100644 index 00000000..1d451097 --- /dev/null +++ b/examples/dsp/StatisticsFunctions_part1/std.c @@ -0,0 +1,62 @@ +#include "ref.h" + +void ref_std_f32(float32_t *pSrc, uint32_t blockSize, float32_t *pResult) +{ + uint32_t i; + float32_t sum = 0, sumsq = 0; + + if (blockSize == 1) { + *pResult = 0; + return; + } + + for (i = 0; i < blockSize; i++) { + sum += pSrc[i]; + sumsq += pSrc[i] * pSrc[i]; + } + *pResult = sqrtf((sumsq - sum * sum / (float32_t)blockSize) / + ((float32_t)blockSize - 1)); +} + +void ref_std_q31(q31_t *pSrc, uint32_t blockSize, q31_t *pResult) +{ + uint32_t i; + q63_t sum = 0, sumsq = 0; + q31_t in; + + if (blockSize == 1) { + *pResult = 0; + return; + } + + for (i = 0; i < blockSize; i++) { + in = pSrc[i] >> 8; + sum += in; + sumsq += (q63_t)in * in; + } + sumsq /= (q63_t)(blockSize - 1); + sum = sum * sum / (q63_t)(blockSize * (blockSize - 1)); + *pResult = (q31_t)(sqrtf((float)((sumsq - sum) >> 15) / 2147483648.0f) * + 2147483648.0f); +} + +void ref_std_q15(q15_t *pSrc, uint32_t blockSize, q15_t *pResult) +{ + uint32_t i; + q31_t sum = 0; + q63_t sumsq = 0; + + if (blockSize == 1) { + *pResult = 0; + return; + } + + for (i = 0; i < blockSize; i++) { + sum += pSrc[i]; + sumsq += (q63_t)pSrc[i] * pSrc[i]; + } + sumsq /= (q63_t)(blockSize - 1); + sum = (q31_t)((q63_t)sum * sum / (q63_t)(blockSize * (blockSize - 1))); + *pResult = (q15_t)( + sqrtf((float)ref_sat_q15((sumsq - sum) >> 15) / 32768.0f) * 32768.0f); +} diff --git a/examples/dsp/StatisticsFunctions_part1/var.c b/examples/dsp/StatisticsFunctions_part1/var.c new file mode 100644 index 00000000..286c857b --- /dev/null +++ b/examples/dsp/StatisticsFunctions_part1/var.c @@ -0,0 +1,59 @@ +#include "ref.h" + +void ref_var_f32(float32_t *pSrc, uint32_t blockSize, float32_t *pResult) +{ + uint32_t i; + float32_t sum = 0, sumsq = 0; + + if (blockSize == 1) { + *pResult = 0; + return; + } + + for (i = 0; i < blockSize; i++) { + sum += pSrc[i]; + sumsq += pSrc[i] * pSrc[i]; + } + *pResult = + (sumsq - sum * sum / (float32_t)blockSize) / ((float32_t)blockSize - 1); +} + +void ref_var_q31(q31_t *pSrc, uint32_t blockSize, q31_t *pResult) +{ + uint32_t i; + q63_t sum = 0, sumsq = 0; + q31_t in; + + if (blockSize == 1) { + *pResult = 0; + return; + } + + for (i = 0; i < blockSize; i++) { + in = pSrc[i] >> 8; + sum += in; + sumsq += (q63_t)in * in; + } + *pResult = + (sumsq - sum * sum / (q31_t)blockSize) / ((q31_t)blockSize - 1) >> 15; +} + +void ref_var_q15(q15_t *pSrc, uint32_t blockSize, q15_t *pResult) +{ + uint32_t i; + q31_t sum = 0; + q63_t sumsq = 0; + + if (blockSize == 1) { + *pResult = 0; + return; + } + + for (i = 0; i < blockSize; i++) { + sum += pSrc[i]; + sumsq += (q63_t)pSrc[i] * pSrc[i]; + } + *pResult = (q31_t)((sumsq - (q63_t)sum * sum / (q63_t)blockSize) / + ((q63_t)blockSize - 1)) >> + 15; +} diff --git a/examples/dsp/StatisticsFunctions_part2/CMakeLists.txt b/examples/dsp/StatisticsFunctions_part2/CMakeLists.txt new file mode 100644 index 00000000..6a0b0998 --- /dev/null +++ b/examples/dsp/StatisticsFunctions_part2/CMakeLists.txt @@ -0,0 +1,4 @@ +set(TARGET_REQUIRED_PRIVATE_INCLUDE ${CMAKE_CURRENT_SOURCE_DIR} ${CMAKE_CURRENT_SOURCE_DIR}/..) +set(TARGET_REQUIRED_LIBS nmsis) +set(mains main.c) +generate_bin() \ No newline at end of file diff --git a/examples/dsp/StatisticsFunctions_part2/array.h b/examples/dsp/StatisticsFunctions_part2/array.h new file mode 100644 index 00000000..4a8c2f5c --- /dev/null +++ b/examples/dsp/StatisticsFunctions_part2/array.h @@ -0,0 +1,19 @@ +// Array for StatisticsFunctions part2 +#define ARRAY_SIZE 230 + +float32_t f32_a_array[ARRAY_SIZE] = {471.092893010197,1341.75099585638,370.536268896060,466.018523868974,613.303362063257,1062.01634109608,215.456392589239,1306.98309985953,124.733845130190,692.606757552197,45.5835354917271,1129.80079906328,1050.06400429443,321.768369245987,1019.85702828513,835.939021034893,1276.01835388515,837.848237704328,1352.66049607134,629.276556019778,537.192529183555,733.481276069230,383.943211503286,1393.75390348859,700.135221315654,381.011775835417,646.827670917111,1053.79501687851,603.494801979902,272.760117998532,1284.37667422002,876.301836804898,560.368174019847,332.541820152597,328.491176567751,783.348664538250,650.134070231642,1111.95598244783,105.674448492617,1271.00015459577,1019.82035183686,204.977282847870,1287.60328286803,299.751187000612,911.009882646318,814.567475481582,243.487038048755,8.47960219026828,1157.22772074811,1147.18133438301,631.604028542823,85.2197714604486,878.620492851342,261.232866651047,1092.91599084947,801.436574911544,379.596431627119,1375.58512242838,1137.29179457312,1330.54609834202,103.197256655575,275.292293291760,1105.60898187988,1045.07227897458,1165.48935855904,752.855128730616,638.245242003940,916.855696161452,1283.65783704260,1006.19566347033,785.388067066741,448.223115160533,1055.95361797679,572.416313983323,851.527496702230,1331.79143296684,1264.42393349293,1348.19783374828,1408.50463716983,1223.15273390812,2.03674317904662,4.63604633619774,131.203224478127,391.091026806480,34.1980059614002,636.127228208819,511.597453363843,812.030899961557,1389.25362387461,447.749170588859,507.127190776923,1289.22016081018,510.717466148149,207.180604575130,761.698433028904,1284.98471533754,576.470426823920,1043.53639024315,941.856266685823,675.582231527888,710.426913148327,1424.55953025530,125.246342683996,419.743380000319,670.510964002057,881.356895992970,1316.45120762178,703.650780343529,656.127713552581,1119.27740996227,701.865698711619,1291.24102658681,699.768018572231,747.156730684064,731.145981623168,344.203162122025,128.328348613586,101.074970413360,1332.58640220687,349.751528504490,1292.39363997655,1067.60263951188,1309.21948956428,1407.00301037945,209.533917821251,590.850217276505,1470.84424457258,967.191038978064,1344.61466918090,723.345608155198,21.1396127835349,934.320516652193,346.643044666702,791.150944164951,1087.48794203586,911.123686717403,882.549668692876,650.152260049587,366.259340260538,643.440530667011,15.2661832826656,913.232173566540,1436.96278229604,143.169785324401,53.3858450702215,1329.35266698863,370.412047586245,13.3725843800055,1222.38040717206,210.749154823150,1319.79966042600,143.065179135787,528.840151872959,890.130851681237,877.772457717889,1001.52264627675,972.040672583557,650.053601007888,209.638138648886,1127.89426196263,362.680190380828,975.688983717094,1286.06109125170,126.555706567723,1458.13374256926,47.1899033386738,1253.10682566729,1253.57002225629,74.7862520183895,818.829313336245,1414.75475948322,482.209604804984,1209.70020569000,902.098132879214,1184.43069768456,1198.77755256647,74.3471483673165,424.797950761418,980.185235969947,734.483017992707,1459.27835551620,1122.73486496562,851.761724608211,448.446245185796,384.164671592757,1329.84569161732,670.201294174201,1223.98087994431,147.505952616957,1289.39018021291,41.4435122417626,1348.73465138455,1349.90325078926,786.159014426045,180.299268970702,266.691137733418,1059.16139176292,1247.03963458057,52.2507308515935,1136.75806557890,1435.66826700175,514.305772495271,957.365564137059,514.508717955488,324.707094273811,1179.30094054582,1084.63493931821,418.258357181186,873.647143056720,631.508672052420,138.103060131552,36.0409875101228,736.718706017048,417.400530227819,509.635746226597,431.024414272614,256.354852874218,598.894971422144,1046.47435268685,305.514655693522,999.489732734265,664.599134112410,649.942898363545,262.859163591893,289.803467640586,924.631997470142,403.515911810080,839.516897423862,1417.17598763146,1071.70745362342}; +float32_t f32_b_array[ARRAY_SIZE] = {1018.82948309101,1439.07087196063,1163.00146793848,911.590449483158,1422.00353900003,89.4624353780488,403.068517864190,1480.02006597042,1158.31009814104,713.031449936692,1021.34933333093,625.402132397133,570.223804339772,319.905583612813,574.406983701215,44.5016272651557,708.481597626110,500.059030265681,1463.76720616498,833.165307929636,1269.45545667536,612.095241602866,693.027245660839,1239.46008126965,1486.80479980312,785.921473895413,1388.15533444717,1108.53279228289,851.145084257881,1453.16649441436,1236.74912972838,1439.41391849683,969.519098166034,569.360228160433,714.862021320494,1367.83471875108,22.2807836518102,235.040770850944,707.351814794773,814.487542267885,89.5365485787125,987.045458442124,1334.45295506856,164.448909172818,656.659671327171,420.345134410986,1477.86946867680,913.138061001606,380.623810377669,198.922090272544,817.507336827635,1241.70589720638,1255.50940653424,1250.02297055163,305.573151440874,816.626548873160,1312.41408231352,181.500129254501,1284.52615280590,1349.66402844349,326.797685904706,115.468627402338,711.322740722808,1252.54119860199,704.090253062752,620.654908874243,754.119395774998,188.159939999483,198.427988141908,1305.71304771163,904.425271952830,397.952589080699,1297.20387008540,87.1641873359634,686.630827653129,1083.31446614928,508.498727394120,601.829785389469,790.469628292241,1341.35357169677,1167.54098746997,104.051404003504,418.176792931567,569.054752029098,1297.00881957456,629.940554116049,359.816210237825,896.481774620518,719.106605402989,1347.82125275280,1402.06385687072,1226.83025071668,1063.36346835273,1114.83085560676,1349.56467377482,97.8597072595381,503.866757018789,6.50260891319743,1242.14340472408,761.153065954764,549.243654223593,339.959576466555,802.247564395346,434.227299584348,102.556346167806,127.456118350390,102.509202201003,614.724748725753,185.072073464071,664.524888993354,1348.40960544645,530.458502678491,180.267179328792,853.666538165562,1312.54908954824,522.862465655838,62.8815073631544,213.509579082587,114.889252314626,1110.78988395133,684.787690978500,1002.37397297329,1048.86911340469,857.035818586137,943.040012931663,1316.64588763508,993.527609442058,1313.12041781220,701.275528257341,212.004042504997,102.201685848883,1071.36361037981,461.979042274480,1006.74595756734,978.631253133396,796.573257517653,1072.66054764346,757.215934534622,731.999037757843,746.757463545002,1403.96332998664,583.922524194788,175.717748591364,360.635330956858,1027.36274194372,1258.88042258939,1455.21694934705,322.754419206050,1140.51501962736,876.154274787049,604.427366356862,765.060506636351,743.466328627572,977.052513797571,1115.55921693442,452.930203690848,134.417902803186,1238.94822372637,584.380513382540,1162.95727990326,269.053642925965,164.041814576682,1357.73750713746,1314.52650588375,1499.68884666713,1296.38202908563,55.3162834258090,817.023663010871,1496.42427327536,766.512231369070,1310.26826390358,105.332208504808,1481.30810524199,1384.07014432006,846.391379399667,647.193080511517,506.766847884738,1081.08514177088,20.4833499950027,561.090289163736,1384.02783058825,819.719472043909,710.830304628188,744.805977660292,463.456621829089,1426.25633826136,1472.98992130953,770.344655313867,1488.88472770811,683.765553097876,639.061321338148,319.822168196867,289.874220643913,1249.13136895550,1089.95564940744,794.618540858662,1243.62110624899,767.811647007381,827.942769381820,319.927341023844,881.730939484095,214.144838022211,78.3352917377257,1024.96187295890,912.839217617892,329.483902171741,609.419913452017,944.861917143720,832.961437088180,191.368593057394,253.797497483421,1.49912717513012,627.243706795685,732.728518314667,239.803264728705,1000.25786583564,26.8805535768832,179.513034778863,1428.18796331699,1463.78095639829,46.3718080026087,740.822765630155,1294.08319220824,364.314249439665,1251.40524557820,1220.38678860430,943.459656113446,3.35729784124994,569.585909590402,1356.60854473865}; +float32_t f32_out_array; +float32_t f32_out_entropy_array_ref = -1175041.33630915; +float32_t f32_out_kl_array_ref = 79161.1759381185; +float32_t f32_out_lsedp_array_ref = 2957.82258923639; +float32_t f32_out_lse_array_ref = 1470.84425707590; +float32_t f32_temp_array[ARRAY_SIZE]; + +float64_t f64_a_array[ARRAY_SIZE] = {102052.749759703,56823.4696089255,94793.2066053501,36490.4283705885,85711.9607405845,147259.316066463,127452.302835828,42516.6278533591,102368.649667533,53718.6796473001,148039.015494278,12597.9443634283,37545.8829542551,121701.992297251,12663.4655817128,79688.0945612786,120093.446872193,110823.486288160,21249.4470453688,65684.1386857534,52557.0558620204,71774.6245796534,88110.5100186141,21870.8542829282,135799.591086655,96029.1372498333,24440.9357161005,84886.5886502486,139742.420546579,117465.282552695,102853.070546848,69932.8927474113,39047.7143499795,85390.2256615529,37315.5994332115,47895.2387281346,136620.334832541,132783.006149162,119188.413624878,138871.471075032,26825.9926163817,77631.1722354698,94050.7974613964,136977.351885136,99595.2380758212,58378.9234488920,111001.137212423,122645.228956310,90051.7189764740,12749.5596754054,138353.700163508,8039.67229748372,79053.7429016049,17827.9914929622,57021.4485361507,121924.879952266,36614.3873357535,132663.398864036,106897.019213872,56722.2657123215,37337.9416493900,37928.0617858910,115086.539179040,7479.28275708605,102793.285141336,93041.7183226502,112002.694495309,146588.347251850,57587.0268990923,39030.8403470584,131620.430402119,120914.397526597,69168.1619669549,13644.2531886332,84640.3237909797,28107.4333722910,79753.4378842099,53254.9982660074,47217.5257133241,109011.220326404,77365.9287200307,118596.734686872,30673.8872038435,101715.911633969,7872.83139570354,120175.854354375,101785.295822897,141901.341762609,13733.7214312245,136265.755586727,76492.9555579806,92235.5347710083,47410.6801328940,11623.1222273133,127592.109900556,21679.0360422768,55572.8688981018,93358.7149621877,149632.785364706,77601.6199868539,148576.682272547,33980.1693833758,59700.7779630321,104485.303426746,9696.11391802840,112149.237356755,63060.0646849220,121697.613035704,56940.7928655917,47860.1730325177,147907.660008992,107727.135781459,61977.5037854846,14794.5355864371,110183.868774961,95595.9435530224,11076.2815104099,18076.2249602968,147239.431337457,74519.9132668724,3362.04816602296,8074.73234542661,21131.0696402762,134021.146761028,69873.0109674072,84128.5107200314,74168.4521075098,10167.8232728723,134646.981356054,43284.7963321891,40357.0222130275,89129.1263145544,71381.8536084462,55246.6557110104,98341.6635744749,140730.060870639,93063.7778675992,42426.0137421488,30777.1877899480,65870.1122390679,4087.53294912248,131427.650394052,91513.8369411683,30538.8570431128,77987.5237185602,8073.64532251805,129328.114667532,66440.1999080804,82201.3736003488,85029.1247683862,102059.248682146,55706.7867139638,11734.3063778528,68452.6085475043,7176.57002404490,110738.548804018,5700.23030939413,143136.648653912,111355.850169542,140617.435056109,77004.5979236482,36135.7198616592,38994.7918075302,113846.124201311,149001.414576226,53505.8624886849,112928.676165451,16507.2745669000,89556.7844421605,64589.2800480905,109607.702598239,39176.4255856882,14221.1522375346,67644.5233936757,96011.1765401612,19805.8226053224,67923.3644736077,97829.9398422216,124049.749733710,46211.5362630318,60354.5368507581,132634.697406967,105086.926508271,36280.8442721381,113974.772357938,43638.8605790144,41615.8078433238,916.170453989845,56206.6711718337,65539.9171097982,45644.7703262517,43629.0495913559,36377.4463327501,140502.541503350,129028.536124055,59584.2390656753,71912.8656537923,84749.4139642289,73442.9084319818,40471.7449010724,148461.021309332,27551.3544399186,129248.508738603,4894.88581596843,49793.7029379979,112312.049367444,96654.9687272466,25385.6943977497,142830.765108365,81490.5353088374,37712.0214233729,86785.8464780416,137321.489855006,134339.478921659,72375.9926070059,66410.9966645603,46763.2428372462,8297.06579725013,113068.766011307,19792.1219641378,53388.3178625076,59380.6446022052,132828.184123445,3185.93229329237,126612.107881162,43210.5965733352,37551.4323804707,73256.9452537448,109355.417301752,30392.4144245693}; +float64_t f64_b_array[ARRAY_SIZE] = {32441.4308154764,146450.177216913,88985.3688654827,45660.5367140201,145155.432479299,134395.474597748,28503.8215188420,269.898581873490,106764.564497290,130159.018336481,17746.1864756993,5853.44650914640,89729.1788144667,90647.0258446992,77464.8615673332,1126.11061399260,103340.004538218,141903.056309214,131030.468469633,16991.4678785973,53185.4011788780,36290.5245940051,84049.9964760927,91909.0661324827,45121.3635991087,119721.257129273,119346.244009006,117163.839886558,52664.7648621900,8144.60308499656,106305.692546884,148939.266195599,24371.4727784830,17034.9508008070,136931.313882982,72248.5470558833,127770.892801253,121487.070465631,28013.9316404760,37079.9785118495,8128.32620509041,91344.2184680817,116584.864385177,76659.6133669083,4162.51326724076,148557.792235031,75140.9885630408,49799.6230441735,26082.4709916760,93845.4592273259,86270.2249209490,112647.807678817,23027.8199664879,53518.0794903538,21592.6200369218,127591.148286787,50680.4610462509,41279.4739268013,901.645967567427,120286.795292625,74611.2427107856,80676.4261986182,130636.878693199,108426.535299967,100212.889751227,26824.1688455563,82574.3032311899,143981.261803196,89403.2507979449,121285.606312858,147679.853229517,132888.667150491,32075.5504669667,5194.50919687001,67668.5687104762,2069.18351671421,71056.6123699364,142679.563609319,37342.8418058150,57963.4200831626,64715.0064639081,124632.972712356,123697.022944925,67949.7918451668,57084.0254921517,138880.281426095,111126.544117675,110644.961013424,142037.399851804,76514.9558148571,118781.877734513,67826.0253493588,127379.806132348,58564.6244193747,110756.476725943,146465.783602778,78494.8587322665,64487.2952564662,31073.7123879836,48510.2069215567,16630.5327540165,56281.5081363168,49485.5968701054,51315.7758291929,122567.827696067,79752.7971356347,78168.3072763322,116146.456347997,18039.4156169968,93817.5227876288,51997.3028325820,50192.9078759813,86192.4845071463,129590.646158817,29784.4608255979,100867.644554647,135274.705647011,29873.5772428429,44742.6224744974,74478.0405395063,133485.634752702,75212.1884802897,41549.2858655962,80093.7268000274,86137.4330678462,61920.6602581588,2214.54942075641,105414.720514238,76012.0727230487,57189.9147640440,9739.73023107826,53786.9940991522,35137.6863798364,30525.6079333455,122066.937474633,59015.1890390209,8036.27562922407,56257.7367408703,116249.126612651,24794.6431306165,136832.834555499,47880.8672713849,49466.9502425923,30635.3505142663,115082.210456972,10495.9723429238,142505.092202042,23731.4677360328,42966.8799601505,103069.367210543,21172.4735456687,76812.9975725149,108199.039094125,139326.770342978,109815.577502439,112477.203110719,61097.9404658257,35923.7543381825,78127.5712624559,32861.6040163355,126358.185584812,99439.9363576941,122435.292774968,119081.640015386,70365.7805327643,46428.7469001861,103136.887127061,148027.833508495,115490.081378331,124437.127008779,105912.714817547,89300.4627971623,112931.118012381,74508.3305737858,129769.898101809,10204.1541194119,145281.891031949,14813.4467956500,82046.5629682912,60445.4863469301,16056.0233100274,108624.925572093,92052.3521940863,117445.228877709,84993.0873662466,121697.873806038,86516.3790361486,141604.379076250,130717.822341252,76140.3311917153,118323.474751869,70954.5961349549,124320.254773266,48372.2382092929,146421.980284103,41731.6560394715,10924.6207218643,112683.540880801,124678.293080125,138350.713999670,49053.6440055022,120610.389385607,80737.5499950851,69494.2318618961,123112.537628201,142785.975928718,11440.9334159658,106300.659628174,35238.9665755482,59834.3336578518,40218.6640359914,124876.997489330,149306.071551931,97462.6474131960,105592.924656640,139845.479695314,103147.882210428,85253.0878004913,57127.1293934291,95186.9227215633,54484.2931640948,61142.9167418858,55304.9585363686,70259.8140585537,75512.0764925943,136580.367359807,30964.6533110713,50790.5512916074,86118.8432982536,73039.8659144469}; +float64_t f64_out_array; +float64_t f64_out_entropy_array_ref = -197945362.477341; +float64_t f64_out_kl_array_ref = 6839705.86036978; + + diff --git a/examples/dsp/StatisticsFunctions_part2/main.c b/examples/dsp/StatisticsFunctions_part2/main.c new file mode 100644 index 00000000..8ca37dbc --- /dev/null +++ b/examples/dsp/StatisticsFunctions_part2/main.c @@ -0,0 +1,108 @@ +// +// Created by lujun on 19-6-28.DELTAF32 +// + +#include "riscv_math.h" +#include "array.h" +#include +#include +#include "../common.h" + +#include "../HelperFunctions/math_helper.c" +#include "../HelperFunctions/ref_helper.c" + +#include +#define DELTAF32 (1.0f) +#define DELTAF64 (1.0f) +#define DELTAQ31 (63) +#define DELTAQ15 (1) +#define DELTAQ7 (1) + +#define ENABLE_ALL +#define F32 +#define Q31 +#define Q15 +#define Q7 + +int test_flag_error = 0; + +int main() +{ + BENCH_INIT; +//entropy -Sum(p ln p) + BENCH_START(riscv_entropy_f32); + f32_out_array = riscv_entropy_f32(f32_a_array, ARRAY_SIZE); + BENCH_END(riscv_entropy_f32); + if (fabs(f32_out_array - f32_out_entropy_array_ref) > DELTAF32) { + BENCH_ERROR(riscv_entropy_f32); + printf("value expect: %f, actual: %f\n", + f32_out_entropy_array_ref, f32_out_array); + test_flag_error = 1; + } + BENCH_STATUS(riscv_entropy_f32); + +//entropy -Sum(p ln p) + BENCH_START(riscv_entropy_f64); + f64_out_array = riscv_entropy_f64(f64_a_array, ARRAY_SIZE); + BENCH_END(riscv_entropy_f64); + if (fabs(f64_out_array - f64_out_entropy_array_ref) > DELTAF64) { + BENCH_ERROR(riscv_entropy_f64); + printf("value expect: %f, actual: %f\n", + f64_out_entropy_array_ref, f64_out_array); + test_flag_error = 1; + } + BENCH_STATUS(riscv_entropy_f64); + + BENCH_START(riscv_kullback_leibler_f32); + f32_out_array = riscv_kullback_leibler_f32(f32_a_array, f32_b_array, ARRAY_SIZE); + BENCH_END(riscv_kullback_leibler_f32); + if (fabs(f32_out_array - f32_out_kl_array_ref) > DELTAF32) { + BENCH_ERROR(riscv_kullback_leibler_f32); + printf("value expect: %f, actual: %f\n", + f32_out_kl_array_ref, f32_out_array); + test_flag_error = 1; + } + BENCH_STATUS(riscv_kullback_leibler_f32); + + BENCH_START(riscv_kullback_leibler_f64); + f64_out_array = riscv_kullback_leibler_f64(f64_a_array, f64_b_array, ARRAY_SIZE); + BENCH_END(riscv_kullback_leibler_f64); + if (fabs(f64_out_array - f64_out_kl_array_ref) > DELTAF64) { + BENCH_ERROR(riscv_kullback_leibler_f64); + printf("value expect: %f, actual: %f\n", + f64_out_kl_array_ref, f64_out_array); + test_flag_error = 1; + } + BENCH_STATUS(riscv_kullback_leibler_f64); + + BENCH_START(riscv_logsumexp_dot_prod_f32); + f32_out_array = riscv_logsumexp_dot_prod_f32(f32_a_array, f32_b_array, ARRAY_SIZE, f32_temp_array); + BENCH_END(riscv_logsumexp_dot_prod_f32); + if (fabs(f32_out_array - f32_out_lsedp_array_ref) > DELTAF32) { + BENCH_ERROR(riscv_logsumexp_dot_prod_f32); + printf("value expect: %f, actual: %f\n", + f32_out_lsedp_array_ref, f32_out_array); + test_flag_error = 1; + } + BENCH_STATUS(riscv_logsumexp_dot_prod_f32); + + BENCH_START(riscv_logsumexp_f32); + f32_out_array = riscv_logsumexp_f32(f32_a_array, ARRAY_SIZE); + BENCH_END(riscv_logsumexp_f32); + if (fabs(f32_out_array - f32_out_lse_array_ref) > DELTAF32) { + BENCH_ERROR(riscv_logsumexp_f32); + printf("value expect: %f, actual: %f\n", + f32_out_lse_array_ref, f32_out_array); + test_flag_error = 1; + } + BENCH_STATUS(riscv_logsumexp_f32); + + BENCH_FINISH; + if (test_flag_error) { + printf("test error apprears, please recheck.\n"); + return 1; + } else { + printf("all test are passed. Well done!\n"); + } + return 0; +} diff --git a/examples/dsp/SupportFunctions_part1/CMakeLists.txt b/examples/dsp/SupportFunctions_part1/CMakeLists.txt new file mode 100644 index 00000000..8f8ef120 --- /dev/null +++ b/examples/dsp/SupportFunctions_part1/CMakeLists.txt @@ -0,0 +1,6 @@ +set(TARGET_REQUIRED_PRIVATE_INCLUDE ${CMAKE_CURRENT_SOURCE_DIR} ${CMAKE_CURRENT_SOURCE_DIR}/..) +list(APPEND TARGET_REQUIRED_SRCS copy.c fill.c fixed_to_fixed.c) +list(APPEND TARGET_REQUIRED_SRCS fixed_to_float.c float_to_fixed.c) +set(TARGET_REQUIRED_LIBS nmsis) +set(mains main.c) +generate_bin() \ No newline at end of file diff --git a/examples/dsp/SupportFunctions_part1/array.h b/examples/dsp/SupportFunctions_part1/array.h new file mode 100644 index 00000000..a57163e8 --- /dev/null +++ b/examples/dsp/SupportFunctions_part1/array.h @@ -0,0 +1,18 @@ +// Array for SupportFunctions part1 +#define ARRAY_SIZE 100 +//float32_t + float32_t pSrc_f32[ARRAY_SIZE] = {20.39555272,69.43808947,138.9623858,23.57269888,111.5766755,99.21706672,198.3668436,83.40872903,234.2156252,203.2140441,242.7198492,157.0662297,93.7683404,42.90922006,127.0980773,250.0454402,190.0614437,42.82248933,110.2323227,193.3968141,140.0188746,81.43157606,195.3348183,118.7319612,236.7608807,117.9225219,128.39934,69.81043159,229.7454592,137.8044226,30.86866847,39.32231734,7.617649884,76.52100068,161.1355615,182.3718526,96.70066118,175.8406297,140.9852626,87.53840225,143.0505089,203.1299175,204.6099717,217.1714687,231.7938132,9.521066869,58.69767709,54.95233612,22.80817162,107.2485878,56.5443697,136.7085334,10.9362835,26.95924602,53.83168607,93.34431341,190.9785771,78.89296021,3.625528806,132.3334201,218.2421958,196.3453834,98.63455846,229.1104051,118.7256651,158.774126,115.0331893,59.8731672,147.6531161,108.6452233,148.1654485,15.43569885,32.62009978,241.9434,178.2646682,48.9345664,200.8207849,25.12652038,132.448625,143.3524922,208.341847,218.5387817,11.22744941,198.3567017,206.5296846,218.4644039,46.22294294,124.2749536,254.0652378,141.1116973,225.4114845,146.6257091,4.672279142,91.83285837,81.21283754,39.11067216,104.5063162,111.5837379,220.5485356,53.17381258}; + float32_t pDst_f32[ARRAY_SIZE]; + float32_t pDst_f32_ref[ARRAY_SIZE]; +//q31_t + q31_t pSrc_q31[ARRAY_SIZE] = {139339,-144438,24052,-53314,99246,30847,107399,-126254,-49836,45525,108669,-66159,-56061,22548,-67664,-39257,26492,18548,-79833,-8229,-135464,142775,-97422,25412,-141575,-122474,-32285,122746,-16435,-117693,144453,103087,123678,-23187,-121853,-106604,65172,85808,92942,109998,108180,-123204,-123578,-104258,143940,96853,-117103,90774,-37162,105727,60763,-92541,-100354,113724,-12346,-140402,107840,-128688,5241,131533,73574,-40476,-39738,73799,34792,43772,64468,-45714,-131539,-94620,-101695,102779,-53682,145207,128016,77555,-18589,82125,-9758,59287,-41416,117678,104021,23335,95501,130562,-112378,-142917,-37372,-141906,-33184,78343,-9363,18373,46357,-122491,-43281,-49528,44929,-12610}; + q31_t pDst_q31[ARRAY_SIZE]; + q31_t pDst_q31_ref[ARRAY_SIZE]; +//q15_t + q15_t pSrc_q15[ARRAY_SIZE] = {-7253,-6429,-12831,3674,9310,-445,-1954,-306,1275,-13870,-1649,2483,-14937,-7182,11376,9766,-9842,2987,11120,-7545,6014,7783,10442,-10339,1790,14409,5814,-6931,14253,2608,-2249,3399,-4085,-6732,12018,-13461,-4428,11435,1244,13573,10889,-8873,4072,-7562,5838,-10672,-1848,-2287,1548,-6030,11200,-2591,-13034,-4952,5370,-4927,10194,-4160,950,7510,-4723,-8251,-562,-9482,-3501,-14200,-7679,9840,7918,-9077,-11926,-12047,12618,9198,-9707,-9700,-14208,-58,5754,11468,7997,-4256,-11839,12175,-9462,6453,5467,-9232,7534,-2237,6082,11215,1131,12930,12112,3475,-5859,3247,11553,-10560}; + q15_t pDst_q15[ARRAY_SIZE]; + q15_t pDst_q15_ref[ARRAY_SIZE]; +//q7_t + q7_t pSrc_q7[ARRAY_SIZE] = {-63,12,49,-23,71,-89,-59,-37,95,79,85,30,-53,36,19,-100,-16,-80,-31,-82,74,72,-107,33,-97,-93,-18,-36,69,27,94,10,-99,-44,82,-104,-45,64,21,87,-89,32,93,0,99,-62,-10,46,34,75,-51,79,-23,47,108,-22,75,-80,-106,-26,-25,-8,78,-5,-113,104,-47,-42,-101,87,-50,-110,54,2,-82,52,-31,-36,76,50,49,13,-66,30,75,-17,-47,-98,-72,-92,71,-15,-110,100,-60,92,-39,111,5,14}; + q7_t pDst_q7[ARRAY_SIZE]; + q7_t pDst_q7_ref[ARRAY_SIZE]; \ No newline at end of file diff --git a/examples/dsp/SupportFunctions_part1/copy.c b/examples/dsp/SupportFunctions_part1/copy.c new file mode 100644 index 00000000..6ff79c26 --- /dev/null +++ b/examples/dsp/SupportFunctions_part1/copy.c @@ -0,0 +1,37 @@ +#include "ref.h" + +void ref_copy_f32(float32_t *pSrc, float32_t *pDst, uint32_t blockSize) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) { + pDst[i] = pSrc[i]; + } +} + +void ref_copy_q31(q31_t *pSrc, q31_t *pDst, uint32_t blockSize) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) { + pDst[i] = pSrc[i]; + } +} + +void ref_copy_q15(q15_t *pSrc, q15_t *pDst, uint32_t blockSize) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) { + pDst[i] = pSrc[i]; + } +} + +void ref_copy_q7(q7_t *pSrc, q7_t *pDst, uint32_t blockSize) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) { + pDst[i] = pSrc[i]; + } +} diff --git a/examples/dsp/SupportFunctions_part1/fill.c b/examples/dsp/SupportFunctions_part1/fill.c new file mode 100644 index 00000000..1ab20492 --- /dev/null +++ b/examples/dsp/SupportFunctions_part1/fill.c @@ -0,0 +1,37 @@ +#include "ref.h" + +void ref_fill_f32(float32_t value, float32_t *pDst, uint32_t blockSize) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) { + pDst[i] = value; + } +} + +void ref_fill_q31(q31_t value, q31_t *pDst, uint32_t blockSize) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) { + pDst[i] = value; + } +} + +void ref_fill_q15(q15_t value, q15_t *pDst, uint32_t blockSize) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) { + pDst[i] = value; + } +} + +void ref_fill_q7(q7_t value, q7_t *pDst, uint32_t blockSize) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) { + pDst[i] = value; + } +} diff --git a/examples/dsp/SupportFunctions_part1/fixed_to_fixed.c b/examples/dsp/SupportFunctions_part1/fixed_to_fixed.c new file mode 100644 index 00000000..a1046300 --- /dev/null +++ b/examples/dsp/SupportFunctions_part1/fixed_to_fixed.c @@ -0,0 +1,55 @@ +#include "ref.h" + +void ref_q31_to_q15(q31_t *pSrc, q15_t *pDst, uint32_t blockSize) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) { + pDst[i] = pSrc[i] >> 16; + } +} + +void ref_q31_to_q7(q31_t *pSrc, q7_t *pDst, uint32_t blockSize) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) { + pDst[i] = pSrc[i] >> 24; + } +} + +void ref_q15_to_q31(q15_t *pSrc, q31_t *pDst, uint32_t blockSize) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) { + pDst[i] = ((q31_t)pSrc[i]) << 16; + } +} + +void ref_q15_to_q7(q15_t *pSrc, q7_t *pDst, uint32_t blockSize) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) { + pDst[i] = pSrc[i] >> 8; + } +} + +void ref_q7_to_q31(q7_t *pSrc, q31_t *pDst, uint32_t blockSize) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) { + pDst[i] = ((q31_t)pSrc[i]) << 24; + } +} + +void ref_q7_to_q15(q7_t *pSrc, q15_t *pDst, uint32_t blockSize) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) { + pDst[i] = ((q15_t)pSrc[i]) << 8; + } +} diff --git a/examples/dsp/SupportFunctions_part1/fixed_to_float.c b/examples/dsp/SupportFunctions_part1/fixed_to_float.c new file mode 100644 index 00000000..2ac796d2 --- /dev/null +++ b/examples/dsp/SupportFunctions_part1/fixed_to_float.c @@ -0,0 +1,37 @@ +#include "ref.h" + +void ref_q63_to_float(q63_t *pSrc, float32_t *pDst, uint32_t blockSize) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) { + pDst[i] = ((float32_t)pSrc[i]) / 9223372036854775808.0f; + } +} + +void ref_q31_to_float(q31_t *pSrc, float32_t *pDst, uint32_t blockSize) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) { + pDst[i] = ((float32_t)pSrc[i]) / 2147483648.0f; + } +} + +void ref_q15_to_float(q15_t *pSrc, float32_t *pDst, uint32_t blockSize) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) { + pDst[i] = ((float32_t)pSrc[i]) / 32768.0f; + } +} + +void ref_q7_to_float(q7_t *pSrc, float32_t *pDst, uint32_t blockSize) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) { + pDst[i] = ((float32_t)pSrc[i]) / 128.0f; + } +} diff --git a/examples/dsp/SupportFunctions_part1/float_to_fixed.c b/examples/dsp/SupportFunctions_part1/float_to_fixed.c new file mode 100644 index 00000000..677af34b --- /dev/null +++ b/examples/dsp/SupportFunctions_part1/float_to_fixed.c @@ -0,0 +1,40 @@ +#include "ref.h" + +void ref_float_to_q31(float32_t *pSrc, q31_t *pDst, uint32_t blockSize) +{ + uint32_t i; + float32_t in; + + for (i = 0; i < blockSize; i++) { + in = pSrc[i]; + in *= 2147483648.0f; // scale up + in += in > 0.0f ? 0.5f : -0.5f; // round + pDst[i] = ref_sat_q31((q63_t)in); // cast and saturate + } +} + +void ref_float_to_q15(float32_t *pSrc, q15_t *pDst, uint32_t blockSize) +{ + uint32_t i; + float32_t in; + + for (i = 0; i < blockSize; i++) { + in = pSrc[i]; + in *= 32768.0f; + in += in > 0.0f ? 0.5f : -0.5f; + pDst[i] = ref_sat_q15((q31_t)in); + } +} + +void ref_float_to_q7(float32_t *pSrc, q7_t *pDst, uint32_t blockSize) +{ + uint32_t i; + float32_t in; + + for (i = 0; i < blockSize; i++) { + in = pSrc[i]; + in *= 128.0f; + in += in > 0.0f ? 0.5f : -0.5f; + pDst[i] = ref_sat_q7((q15_t)in); + } +} diff --git a/examples/dsp/SupportFunctions_part1/main.c b/examples/dsp/SupportFunctions_part1/main.c new file mode 100644 index 00000000..c1a3156a --- /dev/null +++ b/examples/dsp/SupportFunctions_part1/main.c @@ -0,0 +1,419 @@ +// +// Created by lujun on 19-6-28. +// +// This contains f32, q31, q15, q7 to eachother, fill and copy +// each one has it's own function. +// All function can be found in main function. +// If you don't want to use it, then comment it. +#include "riscv_math.h" +#include +#include +#include +#include +#include "array.h" + +#include "../HelperFunctions/math_helper.c" +#include "../HelperFunctions/ref_helper.c" + +#include "../common.h" + +#define DELTAF32 (0.05f) +#define DELTAQ31 (63) +#define DELTAQ15 (1) +#define DELTAQ7 (1) + +int test_flag_error = 0; + +/* +********************************************************************************************************* +* ? ? ?: DSP_Copy +* ????: ???? +* ? ?:? +* ? ? ?: ? +********************************************************************************************************* +*/ +static int DSP_Copy(void) +{ + int i; + BENCH_START(riscv_copy_f32); + riscv_copy_f32(pSrc_f32, pDst_f32, ARRAY_SIZE); + BENCH_END(riscv_copy_f32); + ref_copy_f32(pSrc_f32, pDst_f32_ref, ARRAY_SIZE); + for (i = 0; i < ARRAY_SIZE; i++) { + if (fabs(pDst_f32[i] - pDst_f32_ref[i]) > DELTAF32) { + BENCH_ERROR(riscv_copy_f32); + printf("index: %d,expect: %f, actual: %f\n", i, pDst_f32_ref[i], + pDst_f32[i]); + test_flag_error = 1; + } + } + BENCH_STATUS(riscv_copy_f32); + + /*****************************************************************/ + BENCH_START(riscv_copy_q31); + riscv_copy_q31(pSrc_q31, pDst_q31, ARRAY_SIZE); + BENCH_END(riscv_copy_q31); + ref_copy_q31(pSrc_q31, pDst_q31_ref, ARRAY_SIZE); + + for (i = 0; i < ARRAY_SIZE; i++) { + if (abs(pDst_q31_ref[i] - pDst_q31[i]) > DELTAQ31) { + BENCH_ERROR(riscv_copy_q31); + printf("index: %d,expect: %d, actual: %d\n", i, pDst_q31_ref[i], + pDst_q31[i]); + test_flag_error = 1; + } + } + BENCH_STATUS(riscv_copy_q31); + + /*****************************************************************/ + BENCH_START(riscv_copy_q15); + riscv_copy_q15(pSrc_q15, pDst_q15, ARRAY_SIZE); + BENCH_END(riscv_copy_q15); + ref_copy_q15(pSrc_q15, pDst_q15_ref, ARRAY_SIZE); + for (i = 0; i < ARRAY_SIZE; i++) { + if (abs(pDst_q15_ref[i] - pDst_q15[i]) > DELTAQ15) { + BENCH_ERROR(riscv_copy_q15); + printf("index: %d,expect: %d, actual: %d\n", pDst_q15_ref[i], pDst_q15[i]); + test_flag_error = 1; + } + } + BENCH_STATUS(riscv_copy_q15); + + /*****************************************************************/ + BENCH_START(riscv_copy_q7); + riscv_copy_q7(pSrc_q7, pDst_q7, ARRAY_SIZE); + BENCH_END(riscv_copy_q7); + ref_copy_q7(pSrc_q7, pDst_q7_ref, ARRAY_SIZE); + for (i = 0; i < ARRAY_SIZE; i++) { + if (abs(pDst_q7_ref[i] - pDst_q7[i]) > DELTAQ7) { + BENCH_ERROR(riscv_copy_q7); + printf("index: %d,expect: %f, actual: %f\n", i, pDst_q7_ref[i], + pDst_q7[i]); + test_flag_error = 1; + } + } + BENCH_STATUS(riscv_copy_q7); + + /*****************************************************************/ + printf("all copy tests are passed,well done!\n"); +} + +/* +********************************************************************************************************* +* ? ? ?: DSP_Fill +* ????: ???? +* ? ?:? +* ? ? ?: ? +********************************************************************************************************* +*/ +static int DSP_Fill(void) +{ + int i; + BENCH_START(riscv_fill_f32); + riscv_fill_f32(3.33f, pDst_f32, ARRAY_SIZE); + BENCH_END(riscv_fill_f32); + ref_fill_f32(3.33f, pDst_f32_ref, ARRAY_SIZE); + for (i = 0; i < ARRAY_SIZE; i++) { + if (fabs(pDst_f32[i] - pDst_f32_ref[i]) > DELTAF32) { + BENCH_ERROR(riscv_fill_f32); + printf("index: %d,expect: %f, actual: %f\n", i, pDst_f32_ref[i], + pDst_f32[i]); + test_flag_error = 1; + } + } + BENCH_STATUS(riscv_fill_f32); + + /*****************************************************************/ + BENCH_START(riscv_fill_q31); + riscv_fill_q31(0x11111111, pDst_q31, ARRAY_SIZE); + BENCH_END(riscv_fill_q31); + ref_fill_q31(0x11111111, pDst_q31_ref, ARRAY_SIZE); + for (i = 0; i < ARRAY_SIZE; i++) { + if (abs(pDst_q31_ref[i] - pDst_q31[i]) > DELTAQ31) { + BENCH_ERROR(riscv_fill_q31); + printf("index: %d,expect: %d, actual: %d\n", i, pDst_q31_ref[i], + pDst_q31[i]); + test_flag_error = 1; + } + } + BENCH_STATUS(riscv_fill_q31); + + /*****************************************************************/ + BENCH_START(riscv_fill_q15); + riscv_fill_q15(0x1111, pDst_q15, ARRAY_SIZE); + BENCH_END(riscv_fill_q15); + ref_fill_q15(0x1111, pDst_q15_ref, ARRAY_SIZE); + for (i = 0; i < ARRAY_SIZE; i++) { + if (abs(pDst_q15_ref[i] - pDst_q15[i]) > DELTAQ15) { + BENCH_ERROR(riscv_fill_q15); + printf("index: %d,expect: %d, actual: %d\n", i, pDst_q15_ref[i], + pDst_q15[i]); + test_flag_error = 1; + } + } + BENCH_STATUS(riscv_fill_q15); + + /*****************************************************************/ + BENCH_START(riscv_fill_q7); + riscv_fill_q7(0x11, pDst_q7, ARRAY_SIZE); + BENCH_END(riscv_fill_q7); + ref_fill_q7(0x11, pDst_q7_ref, ARRAY_SIZE); + for (i = 0; i < ARRAY_SIZE; i++) { + if (abs(pDst_q7_ref[i] - pDst_q7[i]) > DELTAQ7) { + BENCH_ERROR(riscv_fill_q7); + printf("index: %d,expect: %d, actual: %d\n", i, pDst_q7_ref[i], + pDst_q7[i]); + test_flag_error = 1; + } + } + BENCH_STATUS(riscv_fill_q7); + + /*****************************************************************/ + printf("all fill tests are passed,well done!\n"); +} + +/* +********************************************************************************************************* +* ? ? ?: DSP_FloatToFix +* ????: ??????? +* ? ?:? +* ? ? ?: ? +********************************************************************************************************* +*/ +static int DSP_FloatToFix(void) +{ + int i; + /*****************************************************************/ + BENCH_START(riscv_float_to_q31); + riscv_float_to_q31(pSrc_f32, pDst_q31, ARRAY_SIZE); + BENCH_END(riscv_float_to_q31); + ref_float_to_q31(pSrc_f32, pDst_q31_ref, ARRAY_SIZE); + for (i = 0; i < ARRAY_SIZE; i++) { + if (abs(pDst_q31_ref[i] - pDst_q31[i]) > DELTAQ31) { + BENCH_ERROR(riscv_float_to_q31); + printf("index: %d,expect: %d, actual: %d\n", i, pDst_q31_ref[i], + pDst_q31[i]); + test_flag_error = 1; + } + } + BENCH_STATUS(riscv_float_to_q31); + + /*****************************************************************/ + BENCH_START(riscv_float_to_q15); + riscv_float_to_q15(pSrc_f32, pDst_q15, ARRAY_SIZE); + BENCH_END(riscv_float_to_q15); + ref_float_to_q15(pSrc_f32, pDst_q15_ref, ARRAY_SIZE); + for (i = 0; i < ARRAY_SIZE; i++) { + if (abs(pDst_q15_ref[i] - pDst_q15[i]) > DELTAQ15) { + BENCH_ERROR(riscv_float_to_q15); + printf("index: %d, expect: %d, actual: %d\n", i, + pDst_q15_ref[i], pDst_q15[i]); + test_flag_error = 1; + } + } + BENCH_STATUS(riscv_float_to_q15); + + /*****************************************************************/ + BENCH_START(riscv_float_to_q7); + riscv_float_to_q7(pSrc_f32, pDst_q7, ARRAY_SIZE); + BENCH_END(riscv_float_to_q7); + ref_float_to_q7(pSrc_f32, pDst_q7_ref, ARRAY_SIZE); + for (i = 0; i < ARRAY_SIZE; i++) { + if (abs(pDst_q7_ref[i] - pDst_q7[i]) > DELTAQ7) { + BENCH_ERROR(riscv_float_to_q7); + printf("index: %d,expect: %d, actual: %d\n", i, pDst_q7_ref[i], pDst_q7[i]); + test_flag_error = 1; + } + } + BENCH_STATUS(riscv_float_to_q7); + + /*****************************************************************/ + printf("all float to fix tests are passed,well done!\n"); +} + +/* +********************************************************************************************************* +* ? ? ?: DSP_Q7 +* ????: Q7??????????? +* ? ?:? +* ? ? ?: ? +********************************************************************************************************* +*/ +static int DSP_Q7(void) +{ + int i; + BENCH_START(riscv_q7_to_float); + riscv_q7_to_float(pSrc_q7, pDst_f32, ARRAY_SIZE); + BENCH_END(riscv_q7_to_float); + ref_q7_to_float(pSrc_q7, pDst_f32_ref, ARRAY_SIZE); + for (i = 0; i < ARRAY_SIZE; i++) { + if (fabs(pDst_f32[i] - pDst_f32_ref[i]) > DELTAF32) { + BENCH_ERROR(riscv_q7_to_float); + printf("expect: %f, actual: %f\n", pDst_f32_ref[i], pDst_f32[i]); + test_flag_error = 1; + } + } + BENCH_STATUS(riscv_q7_to_float); + + /*****************************************************************/ + BENCH_START(riscv_q7_to_q31); + riscv_q7_to_q31(pSrc_q7, pDst_q31, ARRAY_SIZE); + BENCH_END(riscv_q7_to_q31); + ref_q7_to_q31(pSrc_q7, pDst_q31_ref, ARRAY_SIZE); + for (i = 0; i < ARRAY_SIZE; i++) { + if (abs(pDst_q31[i] - pDst_q31_ref[i]) > DELTAQ31) { + BENCH_ERROR(riscv_q7_to_q31); + printf("expect: %d, actual: %d\n", pDst_q31_ref[i], pDst_q31[i]); + test_flag_error = 1; + } + } + BENCH_STATUS(riscv_q7_to_q31); + + /*****************************************************************/ + BENCH_START(riscv_q7_to_q15); + riscv_q7_to_q15(pSrc_q7, pDst_q15, ARRAY_SIZE); + BENCH_END(riscv_q7_to_q15); + ref_q7_to_q15(pSrc_q7, pDst_q15_ref, ARRAY_SIZE); + for (i = 0; i < ARRAY_SIZE; i++) { + if (abs(pDst_q15[i] - pDst_q15_ref[i]) > DELTAQ15) { + BENCH_ERROR(riscv_q7_to_q15); + printf("expect: %d, actual: %d\n", pDst_q15_ref[i], pDst_q15[i]); + test_flag_error = 1; + } + } + BENCH_STATUS(riscv_q7_to_q15); + + /*****************************************************************/ + printf("all q7 to others tests are passed,well done!\n"); +} + +/* +********************************************************************************************************* +* ? ? ?: DSP_Q15 +* ????: Q15??????????? +* ? ?:? +* ? ? ?: ? +********************************************************************************************************* +*/ +static int DSP_Q15(void) +{ + int i; + BENCH_START(riscv_q15_to_float); + riscv_q15_to_float(pSrc_q15, pDst_f32, ARRAY_SIZE); + BENCH_END(riscv_q15_to_float); + ref_q15_to_float(pSrc_q15, pDst_f32_ref, ARRAY_SIZE); + for (i = 0; i < ARRAY_SIZE; i++) { + if (fabs(pDst_f32[i] - pDst_f32_ref[i]) > DELTAF32) { + BENCH_ERROR(riscv_q15_to_float); + printf("expect: %f, actual: %f\n", pDst_f32_ref[i], pDst_f32[i]); + test_flag_error = 1; + } + } + BENCH_STATUS(riscv_q15_to_float); + + /*****************************************************************/ + BENCH_START(riscv_q15_to_q31); + riscv_q15_to_q31(pSrc_q15, pDst_q31, ARRAY_SIZE); + BENCH_END(riscv_q15_to_q31); + ref_q15_to_q31(pSrc_q15, pDst_q31_ref, ARRAY_SIZE); + for (i = 0; i < ARRAY_SIZE; i++) { + if (abs(pDst_q31[i] - pDst_q31_ref[i]) > DELTAQ31) { + BENCH_ERROR(riscv_q15_to_q31); + printf("expect: %d, actual: %d\n", pDst_q31_ref[i], pDst_q31[i]); + test_flag_error = 1; + } + } + BENCH_STATUS(riscv_q15_to_q31); + + /*****************************************************************/ + BENCH_START(riscv_q15_to_q7); + riscv_q15_to_q7(pSrc_q15, pDst_q7, ARRAY_SIZE); + BENCH_END(riscv_q15_to_q7); + ref_q15_to_q7(pSrc_q15, pDst_q7_ref, ARRAY_SIZE); + for (i = 0; i < ARRAY_SIZE; i++) { + if (abs(pDst_q7[i] - pDst_q7_ref[i]) > DELTAQ7) { + BENCH_ERROR(riscv_q15_to_q7); + printf("expect: %d, actual: %d\n", pDst_q7_ref[i], pDst_q7[i]); + test_flag_error = 1; + } + } + BENCH_STATUS(riscv_q15_to_q7); + + /*****************************************************************/ + printf("all q15 to others tests are passed,well done!\n"); +} + +/* +********************************************************************************************************* +* ? ? ?: DSP_Q31 +* ????: Q31??????????? +* ? ?:? +* ? ? ?: ? +********************************************************************************************************* +*/ +static int DSP_Q31(void) +{ + int i; + BENCH_START(riscv_q31_to_float); + riscv_q31_to_float(pSrc_q31, pDst_f32, ARRAY_SIZE); + BENCH_END(riscv_q31_to_float); + ref_q31_to_float(pSrc_q31, pDst_f32_ref, ARRAY_SIZE); + for (i = 0; i < ARRAY_SIZE; i++) { + if (fabs(pDst_f32[i] - pDst_f32_ref[i]) > DELTAF32) { + BENCH_ERROR(riscv_q31_to_float); + printf("expect: %f, actual: %f\n", pDst_f32_ref[i], pDst_f32[i]); + test_flag_error = 1; + } + } + BENCH_STATUS(riscv_q31_to_float); + + /*****************************************************************/ + BENCH_START(riscv_q31_to_q15); + riscv_q31_to_q15(pSrc_q31, pDst_q15, ARRAY_SIZE); + BENCH_END(riscv_q31_to_q15); + ref_q31_to_q15(pSrc_q31, pDst_q15_ref, ARRAY_SIZE); + for (i = 0; i < ARRAY_SIZE; i++) { + if (abs(pDst_q15[i] - pDst_q15_ref[i]) > DELTAQ15) { + BENCH_ERROR(riscv_q31_to_q15); + printf("expect: %d, actual: %d\n", pDst_q15_ref[i], pDst_q15[i]); + test_flag_error = 1; + } + } + BENCH_STATUS(riscv_q31_to_q15); + + /*****************************************************************/ + BENCH_START(riscv_q31_to_q7); + riscv_q31_to_q7(pSrc_q31, pDst_q7, ARRAY_SIZE); + BENCH_END(riscv_q31_to_q7); + ref_q31_to_q7(pSrc_q31, pDst_q7_ref, ARRAY_SIZE); + for (i = 0; i < ARRAY_SIZE; i++) { + if (abs(pDst_q7[i] - pDst_q7_ref[i]) > DELTAQ7) { + BENCH_ERROR(riscv_q31_to_q7); + printf("expect: %d, actual: %d\n", pDst_q7_ref[i], pDst_q7[i]); + test_flag_error = 1; + } + } + BENCH_STATUS(riscv_q31_to_q7); + + /*****************************************************************/ + printf("all q31 to others tests are passed,well done!\n"); +} + +int main() +{ + BENCH_INIT; + DSP_Q7(); + DSP_Q15(); + DSP_Q31(); + DSP_Fill(); + DSP_Copy(); + DSP_FloatToFix(); + BENCH_FINISH; + if (test_flag_error) { + printf("test error apprears, please recheck.\n"); + return 1; + } else { + printf("all test are passed. Well done!\n"); + } + return 0; +} diff --git a/examples/dsp/SupportFunctions_part2/CMakeLists.txt b/examples/dsp/SupportFunctions_part2/CMakeLists.txt new file mode 100644 index 00000000..6a0b0998 --- /dev/null +++ b/examples/dsp/SupportFunctions_part2/CMakeLists.txt @@ -0,0 +1,4 @@ +set(TARGET_REQUIRED_PRIVATE_INCLUDE ${CMAKE_CURRENT_SOURCE_DIR} ${CMAKE_CURRENT_SOURCE_DIR}/..) +set(TARGET_REQUIRED_LIBS nmsis) +set(mains main.c) +generate_bin() \ No newline at end of file diff --git a/examples/dsp/SupportFunctions_part2/array.h b/examples/dsp/SupportFunctions_part2/array.h new file mode 100644 index 00000000..8dd674dd --- /dev/null +++ b/examples/dsp/SupportFunctions_part2/array.h @@ -0,0 +1,27 @@ +// Array for SupportFunctions part2 +#define ARRAY_SIZE 100 +float32_t f32_a_array[ARRAY_SIZE] = {743.009927045267,-539.269325687355,-21.1970440734126,-835.041736572152,1317.82122796889,-53.0841319259901,119.988260621840,-836.828700889102,-1212.16499453655,-1319.50375062156,958.526624826807,814.434914178113,-912.912806940790,1185.35446365948,552.900438672434,470.539443742849,1471.14360446386,-1398.92462063696,-227.240188727542,-30.0489815812393,250.513411401834,-1250.19075725612,480.463889933351,-1343.08433768882,170.491602395987,636.075747404832,-36.2681242197864,352.801937717937,-858.667275713906,436.975986184069,-358.073126146119,-1188.86147943933,-367.465443711760,-711.417577474041,-776.143162040997,368.772151123542,68.7832864726499,-260.286760517472,-846.623893422403,1075.66085136249,1083.02475989890,-648.182965305507,346.178546835372,838.468505531921,1364.54193425827,1258.80973867878,-345.552889339436,-1012.07095078118,890.254259327152,-1158.54846109760,-1023.52710397374,-432.515651242719,1043.27569318718,248.343590966966,258.532995720154,1277.51396684951,225.234803122616,-1470.06781511938,928.131857453607,326.425078773474,-60.2589588713261,-694.679525126799,-725.710848012301,-56.9713922129747,-817.975548068616,-1354.19310527432,-992.274556373222,-724.661076748110,-906.269827331516,317.079192549062,971.110936139761,931.844888014813,906.711048089800,624.340129220240,1078.13356290908,843.253554004147,-888.609446857969,1480.02974979276,-1219.12641534045,451.855631723180,-854.470421647909,-768.380693573041,-480.936584775896,-906.412978483751,20.5001299076594,1352.27394823767,-316.178345089647,253.394520954319,319.611737856872,643.928601263737,-295.390938632055,1076.07306581393,1261.45494648416,752.516668479376,-643.224884415321,890.447363664160,-1071.70250961137,13.6505718248136,332.063854445703,611.390206054590}; +float32_t f32_out_array[ARRAY_SIZE]; +float32_t f32_out_sort_array_ref[ARRAY_SIZE] = {-1470.06781511938,-1398.92462063696,-1354.19310527432,-1343.08433768882,-1319.50375062156,-1250.19075725612,-1219.12641534045,-1212.16499453655,-1188.86147943933,-1158.54846109760,-1071.70250961137,-1023.52710397374,-1012.07095078118,-992.274556373222,-912.912806940790,-906.412978483751,-906.269827331516,-888.609446857969,-858.667275713906,-854.470421647909,-846.623893422403,-836.828700889102,-835.041736572152,-817.975548068616,-776.143162040997,-768.380693573041,-725.710848012301,-724.661076748110,-711.417577474041,-694.679525126799,-648.182965305507,-643.224884415321,-539.269325687355,-480.936584775896,-432.515651242719,-367.465443711760,-358.073126146119,-345.552889339436,-316.178345089647,-295.390938632055,-260.286760517472,-227.240188727542,-60.2589588713261,-56.9713922129747,-53.0841319259901,-36.2681242197864,-30.0489815812393,-21.1970440734126,13.6505718248136,20.5001299076594,68.7832864726499,119.988260621840,170.491602395987,225.234803122616,248.343590966966,250.513411401834,253.394520954319,258.532995720154,317.079192549062,319.611737856872,326.425078773474,332.063854445703,346.178546835372,352.801937717937,368.772151123542,436.975986184069,451.855631723180,470.539443742849,480.463889933351,552.900438672434,611.390206054590,624.340129220240,636.075747404832,643.928601263737,743.009927045267,752.516668479376,814.434914178113,838.468505531921,843.253554004147,890.254259327152,890.447363664160,906.711048089800,928.131857453607,931.844888014813,958.526624826807,971.110936139761,1043.27569318718,1075.66085136249,1076.07306581393,1078.13356290908,1083.02475989890,1185.35446365948,1258.80973867878,1261.45494648416,1277.51396684951,1317.82122796889,1352.27394823767,1364.54193425827,1471.14360446386,1480.02974979276}; +float32_t f32_temp_array[ARRAY_SIZE]; +#define FUNC_SIZE 42 +#define SPLINE_FUNC_SIZE 58 +float32_t f32_x_array[FUNC_SIZE] = {0,0.150000000000000,0.300000000000000,0.450000000000000,0.600000000000000,0.750000000000000,0.900000000000000,1.05000000000000,1.20000000000000,1.35000000000000,1.50000000000000,1.65000000000000,1.80000000000000,1.95000000000000,2.10000000000000,2.25000000000000,2.40000000000000,2.55000000000000,2.70000000000000,2.85000000000000,3,3.15000000000000,3.30000000000000,3.45000000000000,3.60000000000000,3.75000000000000,3.90000000000000,4.05000000000000,4.20000000000000,4.35000000000000,4.50000000000000,4.65000000000000,4.80000000000000,4.95000000000000,5.10000000000000,5.25000000000000,5.40000000000000,5.55000000000000,5.70000000000000,5.85000000000000,6.00000000000000,6.15000000000000}; +float32_t f32_y_array[FUNC_SIZE] = {0,0.149438132473599,0.295520206661340,0.434965534111230,0.564642473395035,0.681638760023334,0.783326909627483,0.867423225594017,0.932039085967226,0.975723357826659,0.997494986604054,0.996865028453919,0.973847630878195,0.928959715003869,0.863209366648874,0.778073196887921,0.675463180551151,0.557683717391417,0.427379880233830,0.287478012342544,0.141120008059867,-0.00840724736714817,-0.157745694143248,-0.303541512708429,-0.442520443294852,-0.571561318742343,-0.687766159183973,-0.788525254426195,-0.871575772413588,-0.935052577558449,-0.977530117665097,-0.998054438758879,-0.996164608835841,-0.971903069401821,-0.925814682327733,-0.858934493426592,-0.772764487555988,-0.669239857276262,-0.550685542597638,-0.419764017839860,-0.279415498198927,-0.132791908852518}; +float32_t f32_spline_coef_array[(FUNC_SIZE-1)*3]; +float32_t f32_spline_temp_array[FUNC_SIZE*2-1]; +float32_t f32_test_x_array[SPLINE_FUNC_SIZE] = {0,0.100000000000000,0.200000000000000,0.300000000000000,0.400000000000000,0.500000000000000,0.600000000000000,0.700000000000000,0.800000000000000,0.900000000000000,1,1.10000000000000,1.20000000000000,1.30000000000000,1.40000000000000,1.50000000000000,1.60000000000000,1.70000000000000,1.80000000000000,1.90000000000000,2,2.10000000000000,2.20000000000000,2.30000000000000,2.40000000000000,2.50000000000000,2.60000000000000,2.70000000000000,2.80000000000000,2.90000000000000,3,3.10000000000000,3.20000000000000,3.30000000000000,3.40000000000000,3.50000000000000,3.60000000000000,3.70000000000000,3.80000000000000,3.90000000000000,4,4.10000000000000,4.20000000000000,4.30000000000000,4.40000000000000,4.50000000000000,4.60000000000000,4.70000000000000,4.80000000000000,4.90000000000000,5,5.10000000000000,5.20000000000000,5.30000000000000,5.40000000000000,5.50000000000000,5.60000000000000,5.70000000000000}; +float32_t f32_out_spline_array_ref[SPLINE_FUNC_SIZE] = {0,0.0998334166468282,0.198669330795061,0.295520206661340,0.389418342308651,0.479425538604203,0.564642473395036,0.644217687237691,0.717356090899523,0.783326909627483,0.841470984807897,0.891207360061435,0.932039085967226,0.963558185417193,0.985449729988460,0.997494986604054,0.999573603041505,0.991664810452469,0.973847630878195,0.946300087687415,0.909297426825682,0.863209366648874,0.808496403819590,0.745705212176720,0.675463180551151,0.598472144103956,0.515501371821464,0.427379880233830,0.334988150155905,0.239249329213982,0.141120008059867,0.0415806624332905,-0.0583741434275801,-0.157745694143248,-0.255541102026831,-0.350783227689620,-0.442520443294852,-0.529836140908493,-0.611857890942719,-0.687766159183974,-0.756802495307928,-0.818277111064410,-0.871575772413588,-0.916165936749455,-0.951602073889516,-0.977530117665097,-0.993691003633464,-0.999923257564101,-0.996164608835841,-0.982452612624333,-0.958924274663139,-0.925814682327733,-0.883454655720153,-0.832267442223901,-0.772764487555987,-0.705540325570392,-0.631266637872321,-0.550685542597638}; + +#define VEC_NUM 36 +#define DIMENSION 3 +float32_t f32_barycenter_array[VEC_NUM*DIMENSION] = {0.629447372786358,0.811583874151238,-0.746026367412988,0.826751712278039,0.264718492450819,-0.804919190001181,-0.443003562265903,0.0937630384099677,0.915013670868595,0.929777070398553,-0.684773836644903,0.941185563521231,0.914333896485891,-0.0292487025543176,0.600560937777600,-0.716227322745569,-0.156477434747450,0.831471050378134,0.584414659119109,0.918984852785806,0.311481398313174,-0.928576642851621,0.698258611737554,0.867986495515101,0.357470309715547,0.515480261156667,0.486264936249832,-0.215545960931664,0.310955780355113,-0.657626624376877,0.412092176039218,-0.936334307245159,-0.446154030078220,-0.907657218737692,-0.805736437528305,0.646915656654585,0.389657245951634,-0.365801039878279,0.900444097676710,-0.931107838994183,-0.122511280687204,-0.236883085813983,0.531033576298005,0.590399802274126,-0.626254790891243,-0.0204712084235379,-0.108827598578201,0.292626020222529,0.418729661716145,0.509373363964722,-0.447949846002843,0.359405353707350,0.310196007947681,-0.674776529610739,-0.762004636883247,-0.00327189603571409,0.919487917032162,-0.319228546667734,0.170535501959555,-0.552376121017726,0.502534118611306,-0.489809769081462,0.0119141033302848,0.398153445313372,0.781806505071597,0.918582850410889,0.0944310599276061,-0.722751114342642,-0.701411988881885,-0.484983491752527,0.681434511967325,-0.491435642056938,0.628569652137633,-0.512950062550021,0.858527246374456,-0.300032468030383,-0.606809499137584,-0.497832284047938,0.232089352293278,-0.0534223021945415,-0.296680985874007,0.661657255792582,0.170528182305449,0.0994472165822791,0.834387327659620,-0.428321962359253,0.514400458221443,0.507458188556991,-0.239108306049287,0.135643281450442,-0.848291420873873,-0.892099762666786,0.0615951060179454,0.558334460204022,0.868021368458366,-0.740187583052540,0.137647321744385,-0.0612187178835884,-0.976195860997517,-0.325754711202237,-0.675635383613515,0.588569081367814,-0.377569915910390,0.0570662710124255,-0.668702541000438,0.203963882803273,-0.474057430919711,0.308158196953565}; +float32_t f32_barycenter_weights_array[VEC_NUM] = {0.689214503140008,0.748151592823710,0.450541598502498,0.0838213779969326,0.228976968716819,0.913337361501670,0.152378018969223,0.825816977489547,0.538342435260057,0.996134716626886,0.0781755287531837,0.442678269775446,0.106652770180584,0.961898080855054,0.00463422413406744,0.774910464711502,0.817303220653433,0.868694705363510,0.0844358455109103,0.399782649098897,0.259870402850654,0.800068480224308,0.431413827463545,0.910647594429523,0.181847028302853,0.263802916521990,0.145538980384717,0.136068558708664,0.869292207640089,0.579704587365570,0.549860201836332,0.144954798223727,0.853031117721894,0.622055131485066,0.350952380892271,0.513249539867053}; +float32_t f32_out_barycenter_array_ref[VEC_NUM] = {-0.0000463740575945459,0.000174314946142534,-0.0000386186251002168}; + +#define WEIGHT_NUM 36 +float32_t f32_weighted_sum_array[WEIGHT_NUM] = {0.629447372786358,0.811583874151238,-0.746026367412988,0.826751712278039,0.264718492450819,-0.804919190001181,-0.443003562265903,0.0937630384099677,0.915013670868595,0.929777070398553,-0.684773836644903,0.941185563521231,0.914333896485891,-0.0292487025543176,0.600560937777600,-0.716227322745569,-0.156477434747450,0.831471050378134,0.584414659119109,0.918984852785806,0.311481398313174,-0.928576642851621,0.698258611737554,0.867986495515101,0.357470309715547,0.515480261156667,0.486264936249832,-0.215545960931664,0.310955780355113,-0.657626624376877,0.412092176039218,-0.936334307245159,-0.446154030078220,-0.907657218737692,-0.805736437528305,0.646915656654585}; +float32_t f32_weighted_array[WEIGHT_NUM] = {0.814284826068816,0.243524968724989,0.929263623187228,0.349983765984809,0.196595250431208,0.251083857976031,0.616044676146639,0.473288848902729,0.351659507062997,0.830828627896291,0.585264091152724,0.549723608291140,0.917193663829810,0.285839018820374,0.757200229110721,0.753729094278495,0.380445846975357,0.567821640725221,0.0758542895630636,0.0539501186666072,0.530797553008973,0.779167230102011,0.934010684229183,0.129906208473730,0.568823660872193,0.469390641058206,0.0119020695012414,0.337122644398882,0.162182308193243,0.794284540683907,0.311215042044805,0.528533135506213,0.165648729499781,0.601981941401637,0.262971284540144,0.654079098476782}; +float32_t f32_weighted_output, f32_weighted_output_ref = 0.200610794551382; + + diff --git a/examples/dsp/SupportFunctions_part2/main.c b/examples/dsp/SupportFunctions_part2/main.c new file mode 100644 index 00000000..1ba03b19 --- /dev/null +++ b/examples/dsp/SupportFunctions_part2/main.c @@ -0,0 +1,110 @@ +// +// Created by lujun on 19-6-28.DELTAF32 +// + +#include "riscv_math.h" +#include "array.h" +#include +#include +#include "../common.h" + +#include "../HelperFunctions/math_helper.c" +#include "../HelperFunctions/ref_helper.c" + +#include +#define DELTAF32 (1.0f) +#define DELTAF64 (1.0f) +#define DELTAQ31 (63) +#define DELTAQ15 (1) +#define DELTAQ7 (1) + +#define ENABLE_ALL +#define F32 +#define Q31 +#define Q15 +#define Q7 + +int test_flag_error = 0; + +int main() +{ + int i; + BENCH_INIT; + riscv_sort_instance_f32 S_sort; + riscv_sort_init_f32(&S_sort, RISCV_SORT_BUBBLE, RISCV_SORT_ASCENDING); + BENCH_START(riscv_sort_f32); + riscv_sort_f32(&S_sort, f32_a_array, f32_out_array, ARRAY_SIZE); + BENCH_END(riscv_sort_f32); + for(i=0;i DELTAF32) { + BENCH_ERROR(riscv_sort_f32); + printf("value expect: %f, actual: %f\n", + f32_out_sort_array_ref[i], f32_out_array[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_sort_f32); + + riscv_merge_sort_instance_f32 S_merge_sort; + riscv_merge_sort_init_f32(&S_merge_sort, RISCV_SORT_ASCENDING, f32_temp_array); + BENCH_START(riscv_merge_sort_f32); + riscv_merge_sort_f32(&S_merge_sort, f32_a_array, f32_out_array, ARRAY_SIZE); + BENCH_END(riscv_merge_sort_f32); + for(i=0;i DELTAF32) { + BENCH_ERROR(riscv_merge_sort_f32); + printf("value expect: %f, actual: %f\n", + f32_out_sort_array_ref[i], f32_out_array[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_merge_sort_f32); + +//simulate y = sin(x) + riscv_spline_instance_f32 S_spline; + BENCH_START(riscv_spline_init_f32); + riscv_spline_init_f32(&S_spline, RISCV_SPLINE_NATURAL, f32_x_array, f32_y_array, FUNC_SIZE, f32_spline_coef_array, f32_spline_temp_array); + BENCH_END(riscv_spline_init_f32); + BENCH_START(riscv_spline_f32); + riscv_spline_f32(&S_spline, &f32_test_x_array, f32_out_array, SPLINE_FUNC_SIZE); + BENCH_END(riscv_spline_f32); + for(i=0;i DELTAF32) { + BENCH_ERROR(riscv_spline_f32); + printf("index: %d, value expect: %f, actual: %f\n", i, + f32_out_spline_array_ref[i], f32_out_array[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_spline_f32); + + BENCH_START(riscv_barycenter_f32); + riscv_barycenter_f32(&f32_barycenter_array, f32_barycenter_weights_array, f32_out_array, VEC_NUM, DIMENSION); + BENCH_END(riscv_barycenter_f32); + for(i=0;i DELTAF32) { + BENCH_ERROR(riscv_barycenter_f32); + printf("value expect: %f, actual: %f\n", + f32_out_barycenter_array_ref[i], f32_out_array[i]); + test_flag_error = 1; + } + BENCH_STATUS(riscv_barycenter_f32); + + BENCH_START(riscv_weighted_sum_f32); + f32_weighted_output = riscv_weighted_sum_f32(&f32_weighted_sum_array, f32_weighted_array, WEIGHT_NUM); + BENCH_END(riscv_weighted_sum_f32); + for(i=0;i DELTAF32) { + BENCH_ERROR(riscv_weighted_sum_f32); + printf("value expect: %f, actual: %f\n", + f32_weighted_output_ref, f32_weighted_output); + test_flag_error = 1; + } + BENCH_STATUS(riscv_weighted_sum_f32); + + BENCH_FINISH; + if (test_flag_error) { + printf("test error apprears, please recheck.\n"); + return 1; + } else { + printf("all test are passed. Well done!\n"); + } + return 0; +} diff --git a/examples/dsp/TransformFunction_cfft/CMakeLists.txt b/examples/dsp/TransformFunction_cfft/CMakeLists.txt new file mode 100644 index 00000000..29a4e88e --- /dev/null +++ b/examples/dsp/TransformFunction_cfft/CMakeLists.txt @@ -0,0 +1,5 @@ +set(TARGET_REQUIRED_PRIVATE_INCLUDE ${CMAKE_CURRENT_SOURCE_DIR} ${CMAKE_CURRENT_SOURCE_DIR}/..) +set(TARGET_REQUIRED_LIBS nmsis) +list(APPEND TARGET_REQUIRED_SRCS cfft.c) +set(mains main.c) +# generate_bin() \ No newline at end of file diff --git a/examples/dsp/TransformFunction_cfft/array.h b/examples/dsp/TransformFunction_cfft/array.h new file mode 100644 index 00000000..8004bda9 --- /dev/null +++ b/examples/dsp/TransformFunction_cfft/array.h @@ -0,0 +1,1143 @@ +// Array for TransformFunctions cfft +#define ARRAY_SIZE 100 +//float32_t + float32_t cfft_testinput_f32_50hz_200Hz[1024] = { + 2.00000000000000, 0.00000000000000, 1.26007351067010, + 1.26007351067010, 1.11022302462516e-16, 1.17557050458495, + -0.221231742082474, 0.221231742082474, 0.618033988749895, + -1.11022302462516e-16, 1.00000000000000, 1.00000000000000, + -7.21644966006352e-16, 1.90211303259031, -1.39680224666742, + 1.39680224666742, -1.61803398874990, 4.44089209850063e-16, + -0.642039521920207, -0.642039521920206, 0.00000000000000, + -3.67394039744206e-16, -0.642039521920206, 0.642039521920206, + -1.61803398874990, -1.22124532708767e-15, -1.39680224666742, + -1.39680224666742, -7.77156117237610e-16, -1.90211303259031, + 1.00000000000000, -1.00000000000000, 0.618033988749895, + -3.33066907387547e-16, -0.221231742082475, -0.221231742082476, + -5.55111512312578e-16, -1.17557050458495, 1.26007351067010, + -1.26007351067010, 2.00000000000000, -1.22464679914735e-15, + 1.26007351067010, 1.26007351067010, 7.77156117237610e-16, + 1.17557050458495, -0.221231742082475, 0.221231742082475, + 0.618033988749897, 8.88178419700125e-16, 0.999999999999999, + 1.00000000000000, 1.49880108324396e-15, 1.90211303259031, + -1.39680224666742, 1.39680224666742, -1.61803398874990, + 1.33226762955019e-15, -0.642039521920207, -0.642039521920206, + 0.00000000000000, -1.10218211923262e-15, -0.642039521920205, + 0.642039521920206, -1.61803398874989, 1.55431223447522e-15, + -1.39680224666742, -1.39680224666743, 6.49480469405717e-15, + -1.90211303259031, 1.00000000000000, -0.999999999999995, + 0.618033988749896, -7.77156117237610e-16, -0.221231742082474, + -0.221231742082473, -1.44328993201270e-15, -1.17557050458495, + 1.26007351067010, -1.26007351067010, 2.00000000000000, + -2.44929359829471e-15, 1.26007351067010, 1.26007351067010, + -3.77475828372553e-15, 1.17557050458494, -0.221231742082475, + 0.221231742082476, 0.618033988749893, -7.77156117237610e-16, + 1.00000000000000, 0.999999999999998, 2.66453525910038e-15, + 1.90211303259031, -1.39680224666742, 1.39680224666742, + -1.61803398874989, -4.88498130835069e-15, -0.642039521920202, + -0.642039521920206, 0.00000000000000, 3.49210031947972e-15, + -0.642039521920198, 0.642039521920206, -1.61803398874989, + 2.55351295663786e-15, -1.39680224666742, -1.39680224666742, + -3.16413562018170e-15, -1.90211303259031, 1.00000000000000, + -0.999999999999996, 0.618033988749897, -9.99200722162641e-16, + -0.221231742082476, -0.221231742082477, -2.10942374678780e-15, + -1.17557050458494, 1.26007351067009, -1.26007351067011, + 2.00000000000000, -3.67394039744206e-15, 1.26007351067010, + 1.26007351067010, 2.22044604925031e-15, 1.17557050458495, + -0.221231742082473, 0.221231742082472, 0.618033988749893, + -1.22124532708767e-15, 0.999999999999999, 1.00000000000000, + -1.31006316905768e-14, 1.90211303259031, -1.39680224666742, + 1.39680224666742, -1.61803398874989, -1.09912079437891e-14, + -0.642039521920203, -0.642039521920206, 0.00000000000000, + 8.08638275819206e-15, -0.642039521920197, 0.642039521920205, + -1.61803398874989, 3.55271367880050e-15, -1.39680224666743, + -1.39680224666741, -4.32986979603811e-15, -1.90211303259031, + 1.00000000000000, -0.999999999999997, 0.618033988749898, + -1.44328993201270e-15, -0.221231742082476, -0.221231742082476, + -2.77555756156289e-15, -1.17557050458494, 1.26007351067010, + -1.26007351067010, 2.00000000000000, -4.89858719658941e-15, + 1.26007351067010, 1.26007351067010, -7.54951656745106e-15, + 1.17557050458494, -0.221231742082473, 0.221231742082472, + 0.618033988749902, 3.88578058618805e-15, 0.999999999999999, + 1.00000000000000, 5.05151476204446e-15, 1.90211303259031, + -1.39680224666741, 1.39680224666743, -1.61803398874990, + 4.44089209850063e-15, -0.642039521920216, -0.642039521920207, + 0.00000000000000, -3.30654635769785e-15, -0.642039521920209, + 0.642039521920206, -1.61803398874989, 4.55191440096314e-15, + -1.39680224666742, -1.39680224666742, -5.44009282066327e-15, + -1.90211303259031, 1.00000000000000, -0.999999999999998, + 0.618033988749888, 3.66373598126302e-15, -0.221231742082475, + -0.221231742082476, 6.88338275267597e-15, -1.17557050458495, + 1.26007351067010, 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+void ref_cfft_f32(const riscv_cfft_instance_f32 *S, float32_t *p1, + uint8_t ifftFlag, uint8_t bitReverseFlag) +{ + int n, mmax, m, j, istep, i; + float32_t wtemp, wr, wpr, wpi, wi, theta; + float32_t tempr, tempi; + float32_t *data = p1; + uint32_t N = S->fftLen; + int32_t dir = (ifftFlag) ? -1 : 1; + + // decrement pointer since the original version used fortran style indexing. + data--; + + n = N << 1; + j = 1; + for (i = 1; i < n; i += 2) { + if (j > i) { + tempr = data[j]; + data[j] = data[i]; + data[i] = tempr; + tempr = data[j + 1]; + data[j + 1] = data[i + 1]; + data[i + 1] = tempr; + } + m = n >> 1; + while (m >= 2 && j > m) { + j -= m; + m >>= 1; + } + j += m; + } + mmax = 2; + while (n > mmax) { + istep = 2 * mmax; + theta = -6.283185307179586f / (dir * mmax); + wtemp = sinf(0.5f * theta); + wpr = -2.0f * wtemp * wtemp; + wpi = sinf(theta); + wr = 1.0f; + wi = 0.0f; + for (m = 1; m < mmax; m += 2) { + for (i = m; i <= n; i += istep) { + j = i + mmax; + tempr = wr * data[j] - wi * data[j + 1]; + tempi = wr * data[j + 1] + wi * data[j]; + data[j] = data[i] - tempr; + data[j + 1] = data[i + 1] - tempi; + data[i] += tempr; + data[i + 1] += tempi; + } + wr = (wtemp = wr) * wpr - wi * wpi + wr; + wi = wi * wpr + wtemp * wpi + wi; + } + mmax = istep; + } + + // Inverse transform is scaled by 1/N + if (ifftFlag) { + data++; + for (i = 0; i < 2 * N; i++) { + data[i] /= N; + } + } +} + +void ref_cfft_q31(const riscv_cfft_instance_q31 *S, q31_t *p1, uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + uint32_t i; + // float32_t *fSrc = (float32_t*)p1; + float32_t fSrc[S->fftLen * 2]; + riscv_q31_to_float(p1, fSrc, S->fftLen * 2); + for (i = 0; i < S->fftLen * 2; i++) { + // read the q31 data, cast to float, scale down for float + fSrc[i] = (float32_t)p1[i] / 2147483648.0f; + } + + switch (S->fftLen) { + case 16: + ref_cfft_f32(&riscv_cfft_sR_f32_len16, fSrc, ifftFlag, + bitReverseFlag); + break; + + case 32: + ref_cfft_f32(&riscv_cfft_sR_f32_len32, fSrc, ifftFlag, + bitReverseFlag); + break; + + case 64: + ref_cfft_f32(&riscv_cfft_sR_f32_len64, fSrc, ifftFlag, + bitReverseFlag); + break; + + case 128: + ref_cfft_f32(&riscv_cfft_sR_f32_len128, fSrc, ifftFlag, + bitReverseFlag); + break; + + case 256: + ref_cfft_f32(&riscv_cfft_sR_f32_len256, fSrc, ifftFlag, + bitReverseFlag); + break; + + case 512: + ref_cfft_f32(&riscv_cfft_sR_f32_len512, fSrc, ifftFlag, + bitReverseFlag); + break; + + case 1024: + ref_cfft_f32(&riscv_cfft_sR_f32_len1024, fSrc, ifftFlag, + bitReverseFlag); + break; + + case 2048: + ref_cfft_f32(&riscv_cfft_sR_f32_len2048, fSrc, ifftFlag, + bitReverseFlag); + break; + + case 4096: + ref_cfft_f32(&riscv_cfft_sR_f32_len4096, fSrc, ifftFlag, + bitReverseFlag); + break; + } + + if (ifftFlag) { + for (i = 0; i < S->fftLen * 2; i++) { + // read the float data, scale up for q31, cast to q31 + p1[i] = (q31_t)(fSrc[i] * 2147483648.0f); + } + } else { + for (i = 0; i < S->fftLen * 2; i++) { + // read the float data, scale up for q31, cast to q31 + p1[i] = (q31_t)(fSrc[i] * 2147483648.0f / (float32_t)S->fftLen); + } + } +} + +void ref_cfft_q15(const riscv_cfft_instance_q15 *S, q15_t *pSrc, uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + uint32_t i; + // float32_t *fSrc = (float32_t*)pSrc; + float32_t fSrc[S->fftLen * 2]; + riscv_q15_to_float(pSrc, fSrc, S->fftLen * 2); + + for (i = 0; i < S->fftLen * 2; i++) { + // read the q15 data, cast to float, scale down for float, place in + // temporary buffer + scratchArray[i] = (float32_t)pSrc[i] / 32768.0f; + } + + for (i = 0; i < S->fftLen * 2; i++) { + // copy from temp buffer to final buffer + fSrc[i] = scratchArray[i]; + } + + switch (S->fftLen) { + case 16: + ref_cfft_f32(&riscv_cfft_sR_f32_len16, fSrc, ifftFlag, + bitReverseFlag); + break; + + case 32: + ref_cfft_f32(&riscv_cfft_sR_f32_len32, fSrc, ifftFlag, + bitReverseFlag); + break; + + case 64: + ref_cfft_f32(&riscv_cfft_sR_f32_len64, fSrc, ifftFlag, + bitReverseFlag); + break; + + case 128: + ref_cfft_f32(&riscv_cfft_sR_f32_len128, fSrc, ifftFlag, + bitReverseFlag); + break; + + case 256: + ref_cfft_f32(&riscv_cfft_sR_f32_len256, fSrc, ifftFlag, + bitReverseFlag); + break; + + case 512: + ref_cfft_f32(&riscv_cfft_sR_f32_len512, fSrc, ifftFlag, + bitReverseFlag); + break; + + case 1024: + ref_cfft_f32(&riscv_cfft_sR_f32_len1024, fSrc, ifftFlag, + bitReverseFlag); + break; + + case 2048: + ref_cfft_f32(&riscv_cfft_sR_f32_len2048, fSrc, ifftFlag, + bitReverseFlag); + break; + + case 4096: + ref_cfft_f32(&riscv_cfft_sR_f32_len4096, fSrc, ifftFlag, + bitReverseFlag); + break; + } + + if (ifftFlag) { + for (i = 0; i < S->fftLen * 2; i++) { + // read the float data, scale up for q15, cast to q15 + pSrc[i] = (q15_t)(fSrc[i] * 32768.0f); + } + } else { + for (i = 0; i < S->fftLen * 2; i++) { + // read the float data, scale up for q15, cast to q15 + pSrc[i] = (q15_t)(fSrc[i] * 32768.0f / (float32_t)S->fftLen); + } + } +} + +void ref_cfft_radix2_f32(const riscv_cfft_radix2_instance_f32 *S, float32_t *pSrc) +{ + switch (S->fftLen) { + case 16: + ref_cfft_f32(&riscv_cfft_sR_f32_len16, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 32: + ref_cfft_f32(&riscv_cfft_sR_f32_len32, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 64: + ref_cfft_f32(&riscv_cfft_sR_f32_len64, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 128: + ref_cfft_f32(&riscv_cfft_sR_f32_len128, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 256: + ref_cfft_f32(&riscv_cfft_sR_f32_len256, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 512: + ref_cfft_f32(&riscv_cfft_sR_f32_len512, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 1024: + ref_cfft_f32(&riscv_cfft_sR_f32_len1024, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 2048: + ref_cfft_f32(&riscv_cfft_sR_f32_len2048, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 4096: + ref_cfft_f32(&riscv_cfft_sR_f32_len4096, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + } +} + +void ref_cfft_radix2_q31(const riscv_cfft_radix2_instance_q31 *S, q31_t *pSrc) +{ + uint32_t i; + // float32_t *fSrc = (float32_t*)pSrc; + float32_t fSrc[S->fftLen * 2]; + riscv_q31_to_float(pSrc, fSrc, S->fftLen * 2); + + for (i = 0; i < S->fftLen * 2; i++) { + // read the q31 data, cast to float, scale down for float + fSrc[i] = (float32_t)pSrc[i] / 2147483648.0f; + } + + switch (S->fftLen) { + case 16: + ref_cfft_f32(&riscv_cfft_sR_f32_len16, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 32: + ref_cfft_f32(&riscv_cfft_sR_f32_len32, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 64: + ref_cfft_f32(&riscv_cfft_sR_f32_len64, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 128: + ref_cfft_f32(&riscv_cfft_sR_f32_len128, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 256: + ref_cfft_f32(&riscv_cfft_sR_f32_len256, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 512: + ref_cfft_f32(&riscv_cfft_sR_f32_len512, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 1024: + ref_cfft_f32(&riscv_cfft_sR_f32_len1024, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 2048: + ref_cfft_f32(&riscv_cfft_sR_f32_len2048, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 4096: + ref_cfft_f32(&riscv_cfft_sR_f32_len4096, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + } + + if (S->ifftFlag) { + for (i = 0; i < S->fftLen * 2; i++) { + // read the float data, scale up for q31, cast to q31 + pSrc[i] = (q31_t)(fSrc[i] * 2147483648.0f); + } + } else { + for (i = 0; i < S->fftLen * 2; i++) { + // read the float data, scale up for q31, cast to q31 + pSrc[i] = (q31_t)(fSrc[i] * 2147483648.0f / (float32_t)S->fftLen); + } + } +} + +void ref_cfft_radix2_q15(const riscv_cfft_radix2_instance_q15 *S, q15_t *pSrc) +{ + uint32_t i; + // float32_t *fSrc = (float32_t*)pSrc; + float32_t fSrc[S->fftLen * 2]; + riscv_q15_to_float(pSrc, fSrc, S->fftLen * 2); + + for (i = 0; i < S->fftLen * 2; i++) { + // read the q15 data, cast to float, scale down for float, place in + // temporary buffer + scratchArray[i] = (float32_t)pSrc[i] / 32768.0f; + } + + for (i = 0; i < S->fftLen * 2; i++) { + // copy from temp buffer to final buffer + fSrc[i] = scratchArray[i]; + } + + switch (S->fftLen) { + case 16: + ref_cfft_f32(&riscv_cfft_sR_f32_len16, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 32: + ref_cfft_f32(&riscv_cfft_sR_f32_len32, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 64: + ref_cfft_f32(&riscv_cfft_sR_f32_len64, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 128: + ref_cfft_f32(&riscv_cfft_sR_f32_len128, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 256: + ref_cfft_f32(&riscv_cfft_sR_f32_len256, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 512: + ref_cfft_f32(&riscv_cfft_sR_f32_len512, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 1024: + ref_cfft_f32(&riscv_cfft_sR_f32_len1024, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 2048: + ref_cfft_f32(&riscv_cfft_sR_f32_len2048, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 4096: + ref_cfft_f32(&riscv_cfft_sR_f32_len4096, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + } + + if (S->ifftFlag) { + for (i = 0; i < S->fftLen * 2; i++) { + // read the float data, scale up for q15, cast to q15 + pSrc[i] = (q15_t)(fSrc[i] * 32768.0f); + } + } else { + for (i = 0; i < S->fftLen * 2; i++) { + // read the float data, scale up for q15, cast to q15 + pSrc[i] = (q15_t)(fSrc[i] * 32768.0f / (float32_t)S->fftLen); + } + } +} + +void ref_cfft_radix4_f32(const riscv_cfft_radix4_instance_f32 *S, float32_t *pSrc) +{ + switch (S->fftLen) { + case 16: + ref_cfft_f32(&riscv_cfft_sR_f32_len16, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 32: + ref_cfft_f32(&riscv_cfft_sR_f32_len32, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 64: + ref_cfft_f32(&riscv_cfft_sR_f32_len64, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 128: + ref_cfft_f32(&riscv_cfft_sR_f32_len128, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 256: + ref_cfft_f32(&riscv_cfft_sR_f32_len256, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 512: + ref_cfft_f32(&riscv_cfft_sR_f32_len512, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 1024: + ref_cfft_f32(&riscv_cfft_sR_f32_len1024, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 2048: + ref_cfft_f32(&riscv_cfft_sR_f32_len2048, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 4096: + ref_cfft_f32(&riscv_cfft_sR_f32_len4096, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + } +} + +void ref_cfft_radix4_q31(const riscv_cfft_radix4_instance_q31 *S, q31_t *pSrc) +{ + uint32_t i; + // float32_t *fSrc = (float32_t*)pSrc; + float32_t fSrc[S->fftLen * 2]; + riscv_q31_to_float(pSrc, fSrc, S->fftLen * 2); + + for (i = 0; i < S->fftLen * 2; i++) { + // read the q31 data, cast to float, scale down for float + fSrc[i] = (float32_t)pSrc[i] / 2147483648.0f; + } + + switch (S->fftLen) { + case 16: + ref_cfft_f32(&riscv_cfft_sR_f32_len16, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 32: + ref_cfft_f32(&riscv_cfft_sR_f32_len32, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 64: + ref_cfft_f32(&riscv_cfft_sR_f32_len64, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 128: + ref_cfft_f32(&riscv_cfft_sR_f32_len128, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 256: + ref_cfft_f32(&riscv_cfft_sR_f32_len256, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 512: + ref_cfft_f32(&riscv_cfft_sR_f32_len512, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 1024: + ref_cfft_f32(&riscv_cfft_sR_f32_len1024, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 2048: + ref_cfft_f32(&riscv_cfft_sR_f32_len2048, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 4096: + ref_cfft_f32(&riscv_cfft_sR_f32_len4096, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + } + + if (S->ifftFlag) { + for (i = 0; i < S->fftLen * 2; i++) { + // read the float data, scale up for q31, cast to q31 + pSrc[i] = (q31_t)(fSrc[i] * 2147483648.0f); + } + } else { + for (i = 0; i < S->fftLen * 2; i++) { + // read the float data, scale up for q31, cast to q31 + pSrc[i] = (q31_t)(fSrc[i] * 2147483648.0f / (float32_t)S->fftLen); + } + } +} + +void ref_cfft_radix4_q15(const riscv_cfft_radix4_instance_q15 *S, q15_t *pSrc) +{ + uint32_t i; + // float32_t *fSrc = (float32_t*)pSrc; + float32_t fSrc[S->fftLen * 2]; + riscv_q15_to_float(pSrc, fSrc, S->fftLen * 2); + + for (i = 0; i < S->fftLen * 2; i++) { + // read the q15 data, cast to float, scale down for float, place in + // temporary buffer + scratchArray[i] = (float32_t)pSrc[i] / 32768.0f; + } + + for (i = 0; i < S->fftLen * 2; i++) { + // copy from temp buffer to final buffer + fSrc[i] = scratchArray[i]; + } + + switch (S->fftLen) { + case 16: + ref_cfft_f32(&riscv_cfft_sR_f32_len16, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 32: + ref_cfft_f32(&riscv_cfft_sR_f32_len32, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 64: + ref_cfft_f32(&riscv_cfft_sR_f32_len64, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 128: + ref_cfft_f32(&riscv_cfft_sR_f32_len128, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 256: + ref_cfft_f32(&riscv_cfft_sR_f32_len256, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 512: + ref_cfft_f32(&riscv_cfft_sR_f32_len512, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 1024: + ref_cfft_f32(&riscv_cfft_sR_f32_len1024, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 2048: + ref_cfft_f32(&riscv_cfft_sR_f32_len2048, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 4096: + ref_cfft_f32(&riscv_cfft_sR_f32_len4096, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + } + + if (S->ifftFlag) { + for (i = 0; i < S->fftLen * 2; i++) { + // read the float data, scale up for q15, cast to q15 + pSrc[i] = (q15_t)(fSrc[i] * 32768.0f); + } + } else { + for (i = 0; i < S->fftLen * 2; i++) { + // read the float data, scale up for q15, cast to q15 + pSrc[i] = (q15_t)(fSrc[i] * 32768.0f / (float32_t)S->fftLen); + } + } +} diff --git a/examples/dsp/TransformFunction_cfft/main.c b/examples/dsp/TransformFunction_cfft/main.c new file mode 100644 index 00000000..6eeb5577 --- /dev/null +++ b/examples/dsp/TransformFunction_cfft/main.c @@ -0,0 +1,123 @@ +// +// Created by lujun on 19-6-28. +// +// This contains SIN_COS , clarke, inv_clarke, park, inv_park and pid +// each one has it's own function. +// All function can be found in main function. +// If you don't want to use it, then comment it. +#include "riscv_common_tables.h" +#include "riscv_const_structs.h" +#include "riscv_math.h" +#include "array.h" +#include +#include "../common.h" + +#include "../HelperFunctions/math_helper.c" +#include "../HelperFunctions/ref_helper.c" + +#include +#define DELTAF32 (0.05f) +#define DELTAQ31 (63) +#define DELTAQ15 (1) +#define DELTAQ7 (1) + +int test_flag_error = 0; + +uint32_t fftSize = 1024; +uint32_t ifftFlag = 0; +uint32_t doBitReverse = 1; + +static int DSP_cfft_f32(void) +{ + uint16_t i; + uint8_t ifftFlag = 0, doBitReverse = 1; + BENCH_START(riscv_cfft_f32); + riscv_cfft_f32(&riscv_cfft_sR_f32_len512, cfft_testinput_f32_50hz_200Hz, + ifftFlag, doBitReverse); + BENCH_END(riscv_cfft_f32); + ref_cfft_f32(&riscv_cfft_sR_f32_len512, cfft_testinput_f32_50hz_200Hz_ref, + ifftFlag, doBitReverse); + float32_t resault, resault_ref; + uint32_t index, index_ref; + riscv_max_f32(cfft_testinput_f32_50hz_200Hz, 1024, &resault, &index); + riscv_max_f32(cfft_testinput_f32_50hz_200Hz_ref, 1024, &resault_ref, + &index_ref); + if (index != index_ref) { + BENCH_ERROR(riscv_cfft_f32); + printf("expect: %d, actual: %d\n", index_ref, index); + test_flag_error = 1; + } + BENCH_STATUS(riscv_cfft_f32); +} +static int DSP_cfft_q31(void) +{ + uint16_t i; + riscv_float_to_q31(cfft_testinput_f32_50hz_200Hz, + cfft_testinput_q31_50hz_200Hz, 1024); + riscv_float_to_q31(cfft_testinput_f32_50hz_200Hz_ref, + cfft_testinput_q31_50hz_200Hz_ref, 1024); + fftSize = 512; + uint8_t ifftFlag = 0, doBitReverse = 1; + BENCH_START(riscv_cfft_q31); + riscv_cfft_q31(&riscv_cfft_sR_q31_len512, cfft_testinput_q31_50hz_200Hz, + ifftFlag, doBitReverse); + BENCH_END(riscv_cfft_q31); + ref_cfft_q31(&riscv_cfft_sR_q31_len512, cfft_testinput_q31_50hz_200Hz_ref, + ifftFlag, doBitReverse); + riscv_q31_to_float(cfft_testinput_q31_50hz_200Hz, + cfft_testinput_f32_50hz_200Hz, 1024); + q31_t resault, resault_ref; + uint32_t index, index_ref; + riscv_max_q31(cfft_testinput_q31_50hz_200Hz, 1024, &resault, &index); + riscv_max_q31(cfft_testinput_q31_50hz_200Hz_ref, 1024, &resault_ref, + &index_ref); + if (index != index_ref) { + BENCH_ERROR(riscv_cfft_q31); + printf("expect: %d, actual: %d\n", index_ref, index); + test_flag_error = 1; + } + BENCH_STATUS(riscv_cfft_q31); +} +static int DSP_cfft_q15(void) +{ + uint16_t i; + riscv_float_to_q15(cfft_testinput_f32_50hz_200Hz_q15, + cfft_testinput_q15_50hz_200Hz, 1024); + riscv_float_to_q15(cfft_testinput_f32_50hz_200Hz_q15, + cfft_testinput_q15_50hz_200Hz_ref, 1024); + fftSize = 512; + uint8_t ifftFlag = 0, doBitReverse = 1; + BENCH_START(riscv_cfft_q15); + riscv_cfft_q15(&riscv_cfft_sR_q15_len512, cfft_testinput_q15_50hz_200Hz, + ifftFlag, doBitReverse); + BENCH_END(riscv_cfft_q15); + ref_cfft_q15(&riscv_cfft_sR_q15_len512, cfft_testinput_q15_50hz_200Hz_ref, + ifftFlag, doBitReverse); + q15_t resault, resault_ref; + uint32_t index, index_ref; + riscv_max_q15(cfft_testinput_q15_50hz_200Hz, 1024, &resault, &index); + riscv_max_q15(cfft_testinput_q15_50hz_200Hz_ref, 1024, &resault_ref, + &index_ref); + if (index != index_ref) { + BENCH_ERROR(riscv_cfft_q15); + printf("expect: %d, actual: %d\n", index_ref, index); + test_flag_error = 1; + } + BENCH_STATUS(riscv_cfft_q15); +} + +int main() +{ + BENCH_INIT; + DSP_cfft_f32(); + DSP_cfft_q31(); + DSP_cfft_q15(); + BENCH_FINISH; + if (test_flag_error) { + printf("test error apprears, please recheck.\n"); + return 1; + } else { + printf("all test are passed. Well done!\n"); + } + return 0; +} diff --git a/examples/dsp/TransformFunction_cfftx2/CMakeLists.txt b/examples/dsp/TransformFunction_cfftx2/CMakeLists.txt new file mode 100644 index 00000000..18bc21c1 --- /dev/null +++ b/examples/dsp/TransformFunction_cfftx2/CMakeLists.txt @@ -0,0 +1,5 @@ +set(TARGET_REQUIRED_PRIVATE_INCLUDE ${CMAKE_CURRENT_SOURCE_DIR} ${CMAKE_CURRENT_SOURCE_DIR}/..) +set(TARGET_REQUIRED_LIBS nmsis) +list(APPEND TARGET_REQUIRED_SRCS cfft.c) +set(mains main.c) +generate_bin() \ No newline at end of file diff --git a/examples/dsp/TransformFunction_cfftx2/array.h b/examples/dsp/TransformFunction_cfftx2/array.h new file mode 100644 index 00000000..42b58c42 --- /dev/null +++ b/examples/dsp/TransformFunction_cfftx2/array.h @@ -0,0 +1,698 @@ +// Array for TransformFunctions cfftx2 +#define ARRAY_SIZE 100 +//float32_t + float32_t cfft_testinput_f32_50hz_200Hz[1024] = { + 2.00000000000000, 0.00000000000000, 1.26007351067010, + 1.26007351067010, 1.11022302462516e-16, 1.17557050458495, + -0.221231742082474, 0.221231742082474, 0.618033988749895, + -1.11022302462516e-16, 1.00000000000000, 1.00000000000000, + -7.21644966006352e-16, 1.90211303259031, -1.39680224666742, + 1.39680224666742, -1.61803398874990, 4.44089209850063e-16, + -0.642039521920207, -0.642039521920206, 0.00000000000000, + -3.67394039744206e-16, -0.642039521920206, 0.642039521920206, + -1.61803398874990, -1.22124532708767e-15, -1.39680224666742, + -1.39680224666742, -7.77156117237610e-16, -1.90211303259031, + 1.00000000000000, -1.00000000000000, 0.618033988749895, + -3.33066907387547e-16, -0.221231742082475, -0.221231742082476, + -5.55111512312578e-16, -1.17557050458495, 1.26007351067010, + -1.26007351067010, 2.00000000000000, -1.22464679914735e-15, + 1.26007351067010, 1.26007351067010, 7.77156117237610e-16, + 1.17557050458495, -0.221231742082475, 0.221231742082475, + 0.618033988749897, 8.88178419700125e-16, 0.999999999999999, + 1.00000000000000, 1.49880108324396e-15, 1.90211303259031, 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+ -1.39680224666742, 1.39680224666742, -1.61803398874987, + -6.10622663543836e-14, -0.642039521920197, -0.642039521920205, + 0.00000000000000, -2.93952370633560e-14, -0.642039521920228, + 0.642039521920208}; + +//q31_t + q31_t cfft_testinput_q31_50hz_200Hz[1024] = {0}, + cfft_testinput_q31_50hz_200Hz_ref[1024] = {0}; + +//q15_t + q15_t cfft_testinput_q15_50hz_200Hz[1024] = {0}, + cfft_testinput_q15_50hz_200Hz_ref[1024] = {0}; + diff --git a/examples/dsp/TransformFunction_cfftx2/cfft.c b/examples/dsp/TransformFunction_cfftx2/cfft.c new file mode 100644 index 00000000..98c71c22 --- /dev/null +++ b/examples/dsp/TransformFunction_cfftx2/cfft.c @@ -0,0 +1,618 @@ +#include "riscv_const_structs.h" +#include "ref.h" + +void ref_cfft_f32(const riscv_cfft_instance_f32 *S, float32_t *p1, + uint8_t ifftFlag, uint8_t bitReverseFlag) +{ + int n, mmax, m, j, istep, i; + float32_t wtemp, wr, wpr, wpi, wi, theta; + float32_t tempr, tempi; + float32_t *data = p1; + uint32_t N = S->fftLen; + int32_t dir = (ifftFlag) ? -1 : 1; + + // decrement pointer since the original version used fortran style indexing. + data--; + + n = N << 1; + j = 1; + for (i = 1; i < n; i += 2) { + if (j > i) { + tempr = data[j]; + data[j] = data[i]; + data[i] = tempr; + tempr = data[j + 1]; + data[j + 1] = data[i + 1]; + data[i + 1] = tempr; + } + m = n >> 1; + while (m >= 2 && j > m) { + j -= m; + m >>= 1; + } + j += m; + } + mmax = 2; + while (n > mmax) { + istep = 2 * mmax; + theta = -6.283185307179586f / (dir * mmax); + wtemp = sinf(0.5f * theta); + wpr = -2.0f * wtemp * wtemp; + wpi = sinf(theta); + wr = 1.0f; + wi = 0.0f; + for (m = 1; m < mmax; m += 2) { + for (i = m; i <= n; i += istep) { + j = i + mmax; + tempr = wr * data[j] - wi * data[j + 1]; + tempi = wr * data[j + 1] + wi * data[j]; + data[j] = data[i] - tempr; + data[j + 1] = data[i + 1] - tempi; + data[i] += tempr; + data[i + 1] += tempi; + } + wr = (wtemp = wr) * wpr - wi * wpi + wr; + wi = wi * wpr + wtemp * wpi + wi; + } + mmax = istep; + } + + // Inverse transform is scaled by 1/N + if (ifftFlag) { + data++; + for (i = 0; i < 2 * N; i++) { + data[i] /= N; + } + } +} + +void ref_cfft_q31(const riscv_cfft_instance_q31 *S, q31_t *p1, uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + uint32_t i; + // float32_t *fSrc = (float32_t*)p1; + float32_t fSrc[S->fftLen * 2]; + riscv_q31_to_float(p1, fSrc, S->fftLen * 2); + for (i = 0; i < S->fftLen * 2; i++) { + // read the q31 data, cast to float, scale down for float + fSrc[i] = (float32_t)p1[i] / 2147483648.0f; + } + + switch (S->fftLen) { + case 16: + ref_cfft_f32(&riscv_cfft_sR_f32_len16, fSrc, ifftFlag, + bitReverseFlag); + break; + + case 32: + ref_cfft_f32(&riscv_cfft_sR_f32_len32, fSrc, ifftFlag, + bitReverseFlag); + break; + + case 64: + ref_cfft_f32(&riscv_cfft_sR_f32_len64, fSrc, ifftFlag, + bitReverseFlag); + break; + + case 128: + ref_cfft_f32(&riscv_cfft_sR_f32_len128, fSrc, ifftFlag, + bitReverseFlag); + break; + + case 256: + ref_cfft_f32(&riscv_cfft_sR_f32_len256, fSrc, ifftFlag, + bitReverseFlag); + break; + + case 512: + ref_cfft_f32(&riscv_cfft_sR_f32_len512, fSrc, ifftFlag, + bitReverseFlag); + break; + + case 1024: + ref_cfft_f32(&riscv_cfft_sR_f32_len1024, fSrc, ifftFlag, + bitReverseFlag); + break; + + case 2048: + ref_cfft_f32(&riscv_cfft_sR_f32_len2048, fSrc, ifftFlag, + bitReverseFlag); + break; + + case 4096: + ref_cfft_f32(&riscv_cfft_sR_f32_len4096, fSrc, ifftFlag, + bitReverseFlag); + break; + } + + if (ifftFlag) { + for (i = 0; i < S->fftLen * 2; i++) { + // read the float data, scale up for q31, cast to q31 + p1[i] = (q31_t)(fSrc[i] * 2147483648.0f); + } + } else { + for (i = 0; i < S->fftLen * 2; i++) { + // read the float data, scale up for q31, cast to q31 + p1[i] = (q31_t)(fSrc[i] * 2147483648.0f / (float32_t)S->fftLen); + } + } +} + +void ref_cfft_q15(const riscv_cfft_instance_q15 *S, q15_t *pSrc, uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + uint32_t i; + // float32_t *fSrc = (float32_t*)pSrc; + float32_t fSrc[S->fftLen * 2]; + riscv_q15_to_float(pSrc, fSrc, S->fftLen * 2); + + for (i = 0; i < S->fftLen * 2; i++) { + // read the q15 data, cast to float, scale down for float, place in + // temporary buffer + scratchArray[i] = (float32_t)pSrc[i] / 32768.0f; + } + + for (i = 0; i < S->fftLen * 2; i++) { + // copy from temp buffer to final buffer + fSrc[i] = scratchArray[i]; + } + + switch (S->fftLen) { + case 16: + ref_cfft_f32(&riscv_cfft_sR_f32_len16, fSrc, ifftFlag, + bitReverseFlag); + break; + + case 32: + ref_cfft_f32(&riscv_cfft_sR_f32_len32, fSrc, ifftFlag, + bitReverseFlag); + break; + + case 64: + ref_cfft_f32(&riscv_cfft_sR_f32_len64, fSrc, ifftFlag, + bitReverseFlag); + break; + + case 128: + ref_cfft_f32(&riscv_cfft_sR_f32_len128, fSrc, ifftFlag, + bitReverseFlag); + break; + + case 256: + ref_cfft_f32(&riscv_cfft_sR_f32_len256, fSrc, ifftFlag, + bitReverseFlag); + break; + + case 512: + ref_cfft_f32(&riscv_cfft_sR_f32_len512, fSrc, ifftFlag, + bitReverseFlag); + break; + + case 1024: + ref_cfft_f32(&riscv_cfft_sR_f32_len1024, fSrc, ifftFlag, + bitReverseFlag); + break; + + case 2048: + ref_cfft_f32(&riscv_cfft_sR_f32_len2048, fSrc, ifftFlag, + bitReverseFlag); + break; + + case 4096: + ref_cfft_f32(&riscv_cfft_sR_f32_len4096, fSrc, ifftFlag, + bitReverseFlag); + break; + } + + if (ifftFlag) { + for (i = 0; i < S->fftLen * 2; i++) { + // read the float data, scale up for q15, cast to q15 + pSrc[i] = (q15_t)(fSrc[i] * 32768.0f); + } + } else { + for (i = 0; i < S->fftLen * 2; i++) { + // read the float data, scale up for q15, cast to q15 + pSrc[i] = (q15_t)(fSrc[i] * 32768.0f / (float32_t)S->fftLen); + } + } +} + +void ref_cfft_radix2_f32(const riscv_cfft_radix2_instance_f32 *S, float32_t *pSrc) +{ + switch (S->fftLen) { + case 16: + ref_cfft_f32(&riscv_cfft_sR_f32_len16, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 32: + ref_cfft_f32(&riscv_cfft_sR_f32_len32, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 64: + ref_cfft_f32(&riscv_cfft_sR_f32_len64, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 128: + ref_cfft_f32(&riscv_cfft_sR_f32_len128, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 256: + ref_cfft_f32(&riscv_cfft_sR_f32_len256, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 512: + ref_cfft_f32(&riscv_cfft_sR_f32_len512, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 1024: + ref_cfft_f32(&riscv_cfft_sR_f32_len1024, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 2048: + ref_cfft_f32(&riscv_cfft_sR_f32_len2048, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 4096: + ref_cfft_f32(&riscv_cfft_sR_f32_len4096, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + } +} + +void ref_cfft_radix2_q31(const riscv_cfft_radix2_instance_q31 *S, q31_t *pSrc) +{ + uint32_t i; + // float32_t *fSrc = (float32_t*)pSrc; + float32_t fSrc[S->fftLen * 2]; + riscv_q31_to_float(pSrc, fSrc, S->fftLen * 2); + + for (i = 0; i < S->fftLen * 2; i++) { + // read the q31 data, cast to float, scale down for float + fSrc[i] = (float32_t)pSrc[i] / 2147483648.0f; + } + + switch (S->fftLen) { + case 16: + ref_cfft_f32(&riscv_cfft_sR_f32_len16, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 32: + ref_cfft_f32(&riscv_cfft_sR_f32_len32, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 64: + ref_cfft_f32(&riscv_cfft_sR_f32_len64, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 128: + ref_cfft_f32(&riscv_cfft_sR_f32_len128, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 256: + ref_cfft_f32(&riscv_cfft_sR_f32_len256, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 512: + ref_cfft_f32(&riscv_cfft_sR_f32_len512, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 1024: + ref_cfft_f32(&riscv_cfft_sR_f32_len1024, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 2048: + ref_cfft_f32(&riscv_cfft_sR_f32_len2048, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 4096: + ref_cfft_f32(&riscv_cfft_sR_f32_len4096, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + } + + if (S->ifftFlag) { + for (i = 0; i < S->fftLen * 2; i++) { + // read the float data, scale up for q31, cast to q31 + pSrc[i] = (q31_t)(fSrc[i] * 2147483648.0f); + } + } else { + for (i = 0; i < S->fftLen * 2; i++) { + // read the float data, scale up for q31, cast to q31 + pSrc[i] = (q31_t)(fSrc[i] * 2147483648.0f / (float32_t)S->fftLen); + } + } +} + +void ref_cfft_radix2_q15(const riscv_cfft_radix2_instance_q15 *S, q15_t *pSrc) +{ + uint32_t i; + // float32_t *fSrc = (float32_t*)pSrc; + float32_t fSrc[S->fftLen * 2]; + riscv_q15_to_float(pSrc, fSrc, S->fftLen * 2); + + for (i = 0; i < S->fftLen * 2; i++) { + // read the q15 data, cast to float, scale down for float, place in + // temporary buffer + scratchArray[i] = (float32_t)pSrc[i] / 32768.0f; + } + + for (i = 0; i < S->fftLen * 2; i++) { + // copy from temp buffer to final buffer + fSrc[i] = scratchArray[i]; + } + + switch (S->fftLen) { + case 16: + ref_cfft_f32(&riscv_cfft_sR_f32_len16, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 32: + ref_cfft_f32(&riscv_cfft_sR_f32_len32, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 64: + ref_cfft_f32(&riscv_cfft_sR_f32_len64, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 128: + ref_cfft_f32(&riscv_cfft_sR_f32_len128, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 256: + ref_cfft_f32(&riscv_cfft_sR_f32_len256, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 512: + ref_cfft_f32(&riscv_cfft_sR_f32_len512, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 1024: + ref_cfft_f32(&riscv_cfft_sR_f32_len1024, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 2048: + ref_cfft_f32(&riscv_cfft_sR_f32_len2048, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 4096: + ref_cfft_f32(&riscv_cfft_sR_f32_len4096, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + } + + if (S->ifftFlag) { + for (i = 0; i < S->fftLen * 2; i++) { + // read the float data, scale up for q15, cast to q15 + pSrc[i] = (q15_t)(fSrc[i] * 32768.0f); + } + } else { + for (i = 0; i < S->fftLen * 2; i++) { + // read the float data, scale up for q15, cast to q15 + pSrc[i] = (q15_t)(fSrc[i] * 32768.0f / (float32_t)S->fftLen); + } + } +} + +void ref_cfft_radix4_f32(const riscv_cfft_radix4_instance_f32 *S, float32_t *pSrc) +{ + switch (S->fftLen) { + case 16: + ref_cfft_f32(&riscv_cfft_sR_f32_len16, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 32: + ref_cfft_f32(&riscv_cfft_sR_f32_len32, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 64: + ref_cfft_f32(&riscv_cfft_sR_f32_len64, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 128: + ref_cfft_f32(&riscv_cfft_sR_f32_len128, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 256: + ref_cfft_f32(&riscv_cfft_sR_f32_len256, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 512: + ref_cfft_f32(&riscv_cfft_sR_f32_len512, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 1024: + ref_cfft_f32(&riscv_cfft_sR_f32_len1024, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 2048: + ref_cfft_f32(&riscv_cfft_sR_f32_len2048, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 4096: + ref_cfft_f32(&riscv_cfft_sR_f32_len4096, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + } +} + +void ref_cfft_radix4_q31(const riscv_cfft_radix4_instance_q31 *S, q31_t *pSrc) +{ + uint32_t i; + // float32_t *fSrc = (float32_t*)pSrc; + float32_t fSrc[S->fftLen * 2]; + riscv_q31_to_float(pSrc, fSrc, S->fftLen * 2); + + for (i = 0; i < S->fftLen * 2; i++) { + // read the q31 data, cast to float, scale down for float + fSrc[i] = (float32_t)pSrc[i] / 2147483648.0f; + } + + switch (S->fftLen) { + case 16: + ref_cfft_f32(&riscv_cfft_sR_f32_len16, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 32: + ref_cfft_f32(&riscv_cfft_sR_f32_len32, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 64: + ref_cfft_f32(&riscv_cfft_sR_f32_len64, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 128: + ref_cfft_f32(&riscv_cfft_sR_f32_len128, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 256: + ref_cfft_f32(&riscv_cfft_sR_f32_len256, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 512: + ref_cfft_f32(&riscv_cfft_sR_f32_len512, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 1024: + ref_cfft_f32(&riscv_cfft_sR_f32_len1024, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 2048: + ref_cfft_f32(&riscv_cfft_sR_f32_len2048, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 4096: + ref_cfft_f32(&riscv_cfft_sR_f32_len4096, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + } + + if (S->ifftFlag) { + for (i = 0; i < S->fftLen * 2; i++) { + // read the float data, scale up for q31, cast to q31 + pSrc[i] = (q31_t)(fSrc[i] * 2147483648.0f); + } + } else { + for (i = 0; i < S->fftLen * 2; i++) { + // read the float data, scale up for q31, cast to q31 + pSrc[i] = (q31_t)(fSrc[i] * 2147483648.0f / (float32_t)S->fftLen); + } + } +} + +void ref_cfft_radix4_q15(const riscv_cfft_radix4_instance_q15 *S, q15_t *pSrc) +{ + uint32_t i; + // float32_t *fSrc = (float32_t*)pSrc; + float32_t fSrc[S->fftLen * 2]; + riscv_q15_to_float(pSrc, fSrc, S->fftLen * 2); + + for (i = 0; i < S->fftLen * 2; i++) { + // read the q15 data, cast to float, scale down for float, place in + // temporary buffer + scratchArray[i] = (float32_t)pSrc[i] / 32768.0f; + } + + for (i = 0; i < S->fftLen * 2; i++) { + // copy from temp buffer to final buffer + fSrc[i] = scratchArray[i]; + } + + switch (S->fftLen) { + case 16: + ref_cfft_f32(&riscv_cfft_sR_f32_len16, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 32: + ref_cfft_f32(&riscv_cfft_sR_f32_len32, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 64: + ref_cfft_f32(&riscv_cfft_sR_f32_len64, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 128: + ref_cfft_f32(&riscv_cfft_sR_f32_len128, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 256: + ref_cfft_f32(&riscv_cfft_sR_f32_len256, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 512: + ref_cfft_f32(&riscv_cfft_sR_f32_len512, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 1024: + ref_cfft_f32(&riscv_cfft_sR_f32_len1024, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 2048: + ref_cfft_f32(&riscv_cfft_sR_f32_len2048, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 4096: + ref_cfft_f32(&riscv_cfft_sR_f32_len4096, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + } + + if (S->ifftFlag) { + for (i = 0; i < S->fftLen * 2; i++) { + // read the float data, scale up for q15, cast to q15 + pSrc[i] = (q15_t)(fSrc[i] * 32768.0f); + } + } else { + for (i = 0; i < S->fftLen * 2; i++) { + // read the float data, scale up for q15, cast to q15 + pSrc[i] = (q15_t)(fSrc[i] * 32768.0f / (float32_t)S->fftLen); + } + } +} diff --git a/examples/dsp/TransformFunction_cfftx2/main.c b/examples/dsp/TransformFunction_cfftx2/main.c new file mode 100644 index 00000000..11216cc5 --- /dev/null +++ b/examples/dsp/TransformFunction_cfftx2/main.c @@ -0,0 +1,117 @@ +// +// Created by lujun on 19-6-28. +// +// This contains SIN_COS , clarke, inv_clarke, park, inv_park and pid +// each one has it's own function. +// All function can be found in main function. +// If you don't want to use it, then comment it. +#include "riscv_common_tables.h" +#include "riscv_const_structs.h" +#include "riscv_math.h" +#include "array.h" +#include +#include "../common.h" + +#include "../HelperFunctions/math_helper.c" +#include "../HelperFunctions/ref_helper.c" + +#include +#define DELTAF32 (0.05f) +#define DELTAQ31 (63) +#define DELTAQ15 (1) +#define DELTAQ7 (1) + +int test_flag_error = 0; + +uint32_t fftSize = 1024; +uint32_t ifftFlag = 0; +uint32_t doBitReverse = 1; + +static int DSP_cfft_radix2_q15(void) +{ + uint16_t i; + riscv_float_to_q15(cfft_testinput_f32_50hz_200Hz, + cfft_testinput_q15_50hz_200Hz, 1024); + fftSize = 512; + riscv_cfft_radix2_instance_q15 S; + uint8_t ifftFlag = 0, doBitReverse = 1; + riscv_cfft_radix2_init_q15(&S, 512, ifftFlag, doBitReverse); + BENCH_START(riscv_cfft_radix2_q15); + riscv_cfft_radix2_q15(&S, cfft_testinput_q15_50hz_200Hz); + BENCH_END(riscv_cfft_radix2_q15); + q15_t resault, resault_ref; + uint32_t index, index_ref = 205; + riscv_max_q15(cfft_testinput_q15_50hz_200Hz, 1024, &resault, &index); + if (index != index_ref) { + BENCH_ERROR(riscv_cfft_radix2_q15); + printf("expect: %d, actual: %d\n", index_ref, index); + test_flag_error = 1; + } + BENCH_STATUS(riscv_cfft_radix2_q15); +} +static int DSP_cfft_radix2_q31(void) +{ + uint16_t i; + riscv_float_to_q31(cfft_testinput_f32_50hz_200Hz, + cfft_testinput_q31_50hz_200Hz, 1024); + riscv_float_to_q31(cfft_testinput_f32_50hz_200Hz_ref, + cfft_testinput_q31_50hz_200Hz_ref, 1024); + fftSize = 512; + riscv_cfft_radix2_instance_q31 S; + uint8_t ifftFlag = 0, doBitReverse = 1; + riscv_cfft_radix2_init_q31(&S, 512, ifftFlag, doBitReverse); + BENCH_START(riscv_cfft_radix2_q31); + riscv_cfft_radix2_q31(&S, cfft_testinput_q31_50hz_200Hz); + BENCH_END(riscv_cfft_radix2_q31); + ref_cfft_radix2_q31(&S, cfft_testinput_q31_50hz_200Hz_ref); + q31_t resault, resault_ref; + uint32_t index, index_ref; + riscv_max_q31(cfft_testinput_q31_50hz_200Hz, 1024, &resault, &index); + riscv_max_q31(cfft_testinput_q31_50hz_200Hz_ref, 1024, &resault_ref, + &index_ref); + if (index != index_ref) { + BENCH_ERROR(riscv_cfft_radix2_q31); + printf("expect: %d, actual: %d\n", index_ref, index); + test_flag_error = 1; + } + BENCH_STATUS(riscv_cfft_radix2_q31); +} +static int DSP_cfft_radix2_f32(void) +{ + uint16_t i; + fftSize = 512; + riscv_cfft_radix2_instance_f32 S; + uint8_t ifftFlag = 0, doBitReverse = 1; + riscv_cfft_radix2_init_f32(&S, 512, ifftFlag, doBitReverse); + BENCH_START(riscv_cfft_radix2_f32); + riscv_cfft_radix2_f32(&S, cfft_testinput_f32_50hz_200Hz); + BENCH_END(riscv_cfft_radix2_f32); + ref_cfft_radix2_f32(&S, cfft_testinput_f32_50hz_200Hz_ref); + float32_t resault, resault_ref; + uint32_t index, index_ref; + riscv_max_f32(cfft_testinput_f32_50hz_200Hz, 1024, &resault, &index); + riscv_max_f32(cfft_testinput_f32_50hz_200Hz_ref, 1024, &resault_ref, + &index_ref); + if (index != index_ref) { + BENCH_ERROR(riscv_cfft_radix2_f32); + printf("expect: %d, actual: %d\n", index_ref, index); + test_flag_error = 1; + } + BENCH_STATUS(riscv_cfft_radix2_f32); +} + +int main() +{ + BENCH_INIT; + DSP_cfft_radix2_q15(); + DSP_cfft_radix2_q31(); + DSP_cfft_radix2_f32(); + BENCH_FINISH; + if (test_flag_error) { + printf("test error apprears, please recheck.\n"); + return 1; + } else { + printf("all test are passed. Well done!\n"); + } + return 0; +} diff --git a/examples/dsp/TransformFunction_cfftx4/CMakeLists.txt b/examples/dsp/TransformFunction_cfftx4/CMakeLists.txt new file mode 100644 index 00000000..18bc21c1 --- /dev/null +++ b/examples/dsp/TransformFunction_cfftx4/CMakeLists.txt @@ -0,0 +1,5 @@ +set(TARGET_REQUIRED_PRIVATE_INCLUDE ${CMAKE_CURRENT_SOURCE_DIR} ${CMAKE_CURRENT_SOURCE_DIR}/..) +set(TARGET_REQUIRED_LIBS nmsis) +list(APPEND TARGET_REQUIRED_SRCS cfft.c) +set(mains main.c) +generate_bin() \ No newline at end of file diff --git a/examples/dsp/TransformFunction_cfftx4/array.h b/examples/dsp/TransformFunction_cfftx4/array.h new file mode 100644 index 00000000..baf6b1f2 --- /dev/null +++ b/examples/dsp/TransformFunction_cfftx4/array.h @@ -0,0 +1,469 @@ +// Array for TransformFunctions cfftx4 +#define ARRAY_SIZE 100 +//float32_t + float32_t cfft_testinput_f32_50hz_200Hz[512] = { + 2.00000000000000, 0.00000000000000, 1.79670533497009, + -0.744219717332704, 1.26007351067010, -1.26007351067010, + 0.581989529813420, -1.40504701603470, 1.11022302462516e-16, + -1.17557050458495, -0.292893218813452, -0.707106781186548, + -0.221231742082474, -0.221231742082474, 0.144973505364599, + 0.0600499921067857, 0.618033988749895, 1.11022302462516e-16, + 0.965451459415178, -0.399903088302664, 1.00000000000000, + -1.00000000000000, 0.652582529334717, -1.57547359288761, + -7.21644966006352e-16, -1.90211303259031, -0.763007494114494, + -1.84206304048352, -1.39680224666742, -1.39680224666742, + -1.70710678118655, -0.707106781186548, -1.61803398874990, + -4.44089209850063e-16, -1.20002351856331, 0.497066016555608, + -0.642039521920207, 0.642039521920206, -0.178671346220191, + 0.431350787252243, 0.00000000000000, 3.67394039744206e-16, + -0.178671346220191, -0.431350787252243, -0.642039521920206, + -0.642039521920206, -1.20002351856331, -0.497066016555607, + -1.61803398874990, 1.22124532708767e-15, -1.70710678118655, + 0.707106781186549, -1.39680224666742, 1.39680224666742, + -0.763007494114495, 1.84206304048352, -7.77156117237610e-16, + 1.90211303259031, 0.652582529334716, 1.57547359288761, + 1.00000000000000, 1.00000000000000, 0.965451459415179, + 0.399903088302665, 0.618033988749895, 3.33066907387547e-16, + 0.144973505364597, -0.0600499921067852, -0.221231742082475, + 0.221231742082476, -0.292893218813452, 0.707106781186550, + -5.55111512312578e-16, 1.17557050458495, 0.581989529813419, + 1.40504701603470, 1.26007351067010, 1.26007351067010, + 1.79670533497008, 0.744219717332705, 2.00000000000000, + 1.22464679914735e-15, 1.79670533497008, -0.744219717332707, + 1.26007351067010, -1.26007351067010, 0.581989529813422, + -1.40504701603470, 7.77156117237610e-16, -1.17557050458495, + -0.292893218813452, -0.707106781186549, -0.221231742082475, + -0.221231742082475, 0.144973505364599, 0.0600499921067854, + 0.618033988749897, -8.88178419700125e-16, 0.965451459415179, + -0.399903088302667, 0.999999999999999, -1.00000000000000, + 0.652582529334721, -1.57547359288761, 1.49880108324396e-15, + -1.90211303259031, -0.763007494114497, -1.84206304048352, + -1.39680224666742, -1.39680224666742, -1.70710678118655, + -0.707106781186545, -1.61803398874990, -1.33226762955019e-15, + -1.20002351856331, 0.497066016555608, -0.642039521920207, + 0.642039521920206, -0.178671346220193, 0.431350787252245, + 0.00000000000000, 1.10218211923262e-15, -0.178671346220191, + -0.431350787252243, -0.642039521920205, -0.642039521920206, + -1.20002351856332, -0.497066016555606, -1.61803398874989, + -1.55431223447522e-15, -1.70710678118655, 0.707106781186550, + -1.39680224666742, 1.39680224666743, -0.763007494114492, + 1.84206304048352, 6.49480469405717e-15, 1.90211303259031, + 0.652582529334718, 1.57547359288761, 1.00000000000000, + 0.999999999999995, 0.965451459415180, 0.399903088302669, + 0.618033988749896, 7.77156117237610e-16, 0.144973505364603, + -0.0600499921067867, -0.221231742082474, 0.221231742082473, + -0.292893218813452, 0.707106781186549, -1.44328993201270e-15, + 1.17557050458495, 0.581989529813422, 1.40504701603470, + 1.26007351067010, 1.26007351067010, 1.79670533497009, + 0.744219717332702, 2.00000000000000, 2.44929359829471e-15, + 1.79670533497008, -0.744219717332706, 1.26007351067010, + -1.26007351067010, 0.581989529813419, -1.40504701603470, + -3.77475828372553e-15, -1.17557050458494, -0.292893218813453, + -0.707106781186546, -0.221231742082475, -0.221231742082476, + 0.144973505364595, 0.0600499921067846, 0.618033988749893, + 7.77156117237610e-16, 0.965451459415176, -0.399903088302660, + 1.00000000000000, -0.999999999999998, 0.652582529334716, + -1.57547359288761, 2.66453525910038e-15, -1.90211303259031, + -0.763007494114496, -1.84206304048352, -1.39680224666742, + -1.39680224666742, -1.70710678118655, -0.707106781186546, + -1.61803398874989, 4.88498130835069e-15, -1.20002351856331, + 0.497066016555607, -0.642039521920202, 0.642039521920206, + -0.178671346220190, 0.431350787252242, 0.00000000000000, + -3.49210031947972e-15, -0.178671346220191, -0.431350787252243, + -0.642039521920198, -0.642039521920206, -1.20002351856331, + -0.497066016555610, -1.61803398874989, -2.55351295663786e-15, + -1.70710678118655, 0.707106781186549, -1.39680224666742, + 1.39680224666742, -0.763007494114502, 1.84206304048352, + -3.16413562018170e-15, 1.90211303259031, 0.652582529334717, + 1.57547359288761, 1.00000000000000, 0.999999999999996, + 0.965451459415176, 0.399903088302658, 0.618033988749897, + 9.99200722162641e-16, 0.144973505364599, -0.0600499921067855, + -0.221231742082476, 0.221231742082477, -0.292893218813451, + 0.707106781186554, -2.10942374678780e-15, 1.17557050458494, + 0.581989529813421, 1.40504701603470, 1.26007351067009, + 1.26007351067011, 1.79670533497008, 0.744219717332711, + 2.00000000000000, 3.67394039744206e-15, 1.79670533497008, + -0.744219717332705, 1.26007351067010, -1.26007351067010, + 0.581989529813427, -1.40504701603470, 2.22044604925031e-15, + -1.17557050458495, -0.292893218813453, -0.707106781186547, + -0.221231742082473, -0.221231742082472, 0.144973505364605, + 0.0600499921067872, 0.618033988749893, 1.22124532708767e-15, + 0.965451459415178, -0.399903088302665, 0.999999999999999, + -1.00000000000000, 0.652582529334710, -1.57547359288762, + -1.31006316905768e-14, -1.90211303259031, -0.763007494114495, + -1.84206304048352, -1.39680224666742, -1.39680224666742, + -1.70710678118655, -0.707106781186539, -1.61803398874989, + 1.09912079437891e-14, -1.20002351856332, 0.497066016555607, + -0.642039521920203, 0.642039521920206, -0.178671346220186, + 0.431350787252238, 0.00000000000000, -8.08638275819206e-15, + -0.178671346220183, -0.431350787252234, -0.642039521920197, + -0.642039521920205, -1.20002351856331, -0.497066016555611, + -1.61803398874989, -3.55271367880050e-15, -1.70710678118655, + 0.707106781186548, -1.39680224666743, 1.39680224666741, + -0.763007494114503, 1.84206304048352, -4.32986979603811e-15, + 1.90211303259031, 0.652582529334717, 1.57547359288761, + 1.00000000000000, 0.999999999999997, 0.965451459415181, + 0.399903088302671, 0.618033988749898, 1.44328993201270e-15, + 0.144973505364600, -0.0600499921067857, -0.221231742082476, + 0.221231742082476, -0.292893218813451, 0.707106781186553, + -2.77555756156289e-15, 1.17557050458494, 0.581989529813420, + 1.40504701603470, 1.26007351067010, 1.26007351067010, + 1.79670533497009, 0.744219717332697, 2.00000000000000, + 4.89858719658941e-15, 1.79670533497009, -0.744219717332704, + 1.26007351067010, -1.26007351067010, 0.581989529813413, + -1.40504701603470, -7.54951656745106e-15, -1.17557050458494, + -0.292893218813452, -0.707106781186548, -0.221231742082473, + -0.221231742082472, 0.144973505364604, 0.0600499921067871, + 0.618033988749902, -3.88578058618805e-15, 0.965451459415183, + -0.399903088302676, 0.999999999999999, -1.00000000000000, + 0.652582529334711, -1.57547359288762, 5.05151476204446e-15, + -1.90211303259031, -0.763007494114493, -1.84206304048352, + -1.39680224666741, -1.39680224666743, -1.70710678118655, + -0.707106781186557, -1.61803398874990, -4.44089209850063e-15, + -1.20002351856332, 0.497066016555606, -0.642039521920216, + 0.642039521920207, -0.178671346220195, 0.431350787252247, + 0.00000000000000, 3.30654635769785e-15, -0.178671346220190, + -0.431350787252242, -0.642039521920209, -0.642039521920206, + -1.20002351856331, -0.497066016555611, -1.61803398874989, + -4.55191440096314e-15, -1.70710678118655, 0.707106781186546, + -1.39680224666742, 1.39680224666742, -0.763007494114487, + 1.84206304048352, -5.44009282066327e-15, 1.90211303259031, + 0.652582529334716, 1.57547359288761, 1.00000000000000, + 0.999999999999998, 0.965451459415176, 0.399903088302660, + 0.618033988749888, -3.66373598126302e-15, 0.144973505364600, + -0.0600499921067860, -0.221231742082475, 0.221231742082476, + -0.292893218813451, 0.707106781186552, 6.88338275267597e-15, + 1.17557050458495, 0.581989529813434, 1.40504701603470, + 1.26007351067010, 1.26007351067010, 1.79670533497009, + 0.744219717332698, 2.00000000000000, -1.16403343982657e-14, + 1.79670533497008, -0.744219717332718, 1.26007351067010, + -1.26007351067010, 0.581989529813414, -1.40504701603470, + 1.40998324127395e-14, -1.17557050458496, -0.292893218813450, + -0.707106781186561, -0.221231742082479, -0.221231742082482, + 0.144973505364593, 0.0600499921067840, 0.618033988749891, + 1.99840144432528e-15, 0.965451459415178, -0.399903088302663, + 1.00000000000000, -1.00000000000000, 0.652582529334712, + -1.57547359288762, -1.07136521876328e-14, -1.90211303259031, + -0.763007494114476, -1.84206304048353, -1.39680224666741, + -1.39680224666743, -1.70710678118655, -0.707106781186558, + -1.61803398874990, -5.44009282066327e-15, -1.20002351856332, + 0.497066016555606, -0.642039521920205, 0.642039521920206, + -0.178671346220187, 0.431350787252239, 0.00000000000000, + -6.61680659921524e-15, -0.178671346220197, -0.431350787252249, + -0.642039521920220, -0.642039521920207, -1.20002351856331, + -0.497066016555612, -1.61803398874989, -5.55111512312578e-15, + -1.70710678118655, 0.707106781186545, -1.39680224666742, + 1.39680224666742, -0.763007494114488, 1.84206304048352, + 1.02140518265514e-14, 1.90211303259031, 0.652582529334727, + 1.57547359288760, 1.00000000000000, 0.999999999999984, + 0.965451459415172, 0.399903088302648, 0.618033988749899, + 2.10942374678780e-15, 0.144973505364601, -0.0600499921067861, + -0.221231742082475, 0.221231742082475, -0.292893218813452, + 0.707106781186552, -1.47659662275146e-14, 1.17557050458493, + 0.581989529813403, 1.40504701603470, 1.26007351067009, + 1.26007351067011, 1.79670533497008, 0.744219717332714, + 2.00000000000000, 7.34788079488412e-15, 1.79670533497009, + -0.744219717332702, 1.26007351067010, -1.26007351067010, + 0.581989529813416, -1.40504701603470, -5.99520433297585e-15, + -1.17557050458494, -0.292893218813455, -0.707106781186538, + -0.221231742082479, -0.221231742082483, 0.144973505364592, + 0.0600499921067839, 0.618033988749891, 2.33146835171283e-15, + 0.965451459415177, -0.399903088302663, 1.00000000000000, + -1.00000000000000, 0.652582529334713, -1.57547359288761, + -9.54791801177635e-15, -1.90211303259031, -0.763007494114508, + -1.84206304048352, -1.39680224666743, -1.39680224666741, + -1.70710678118655, -0.707106781186559}; + float32_t cfft_testinput_f32_50hz_200Hz_ref[512] = { + 2.00000000000000, 0.00000000000000, 1.79670533497009, + -0.744219717332704, 1.26007351067010, -1.26007351067010, + 0.581989529813420, -1.40504701603470, 1.11022302462516e-16, + -1.17557050458495, -0.292893218813452, -0.707106781186548, + -0.221231742082474, -0.221231742082474, 0.144973505364599, + 0.0600499921067857, 0.618033988749895, 1.11022302462516e-16, + 0.965451459415178, -0.399903088302664, 1.00000000000000, + -1.00000000000000, 0.652582529334717, -1.57547359288761, + -7.21644966006352e-16, -1.90211303259031, -0.763007494114494, + -1.84206304048352, -1.39680224666742, -1.39680224666742, + -1.70710678118655, -0.707106781186548, -1.61803398874990, + -4.44089209850063e-16, -1.20002351856331, 0.497066016555608, + -0.642039521920207, 0.642039521920206, -0.178671346220191, + 0.431350787252243, 0.00000000000000, 3.67394039744206e-16, + -0.178671346220191, -0.431350787252243, -0.642039521920206, + -0.642039521920206, -1.20002351856331, -0.497066016555607, + -1.61803398874990, 1.22124532708767e-15, -1.70710678118655, + 0.707106781186549, -1.39680224666742, 1.39680224666742, + -0.763007494114495, 1.84206304048352, -7.77156117237610e-16, + 1.90211303259031, 0.652582529334716, 1.57547359288761, + 1.00000000000000, 1.00000000000000, 0.965451459415179, + 0.399903088302665, 0.618033988749895, 3.33066907387547e-16, + 0.144973505364597, -0.0600499921067852, -0.221231742082475, + 0.221231742082476, -0.292893218813452, 0.707106781186550, + -5.55111512312578e-16, 1.17557050458495, 0.581989529813419, + 1.40504701603470, 1.26007351067010, 1.26007351067010, + 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0.707106781186552, -1.47659662275146e-14, 1.17557050458493, + 0.581989529813403, 1.40504701603470, 1.26007351067009, + 1.26007351067011, 1.79670533497008, 0.744219717332714, + 2.00000000000000, 7.34788079488412e-15, 1.79670533497009, + -0.744219717332702, 1.26007351067010, -1.26007351067010, + 0.581989529813416, -1.40504701603470, -5.99520433297585e-15, + -1.17557050458494, -0.292893218813455, -0.707106781186538, + -0.221231742082479, -0.221231742082483, 0.144973505364592, + 0.0600499921067839, 0.618033988749891, 2.33146835171283e-15, + 0.965451459415177, -0.399903088302663, 1.00000000000000, + -1.00000000000000, 0.652582529334713, -1.57547359288761, + -9.54791801177635e-15, -1.90211303259031, -0.763007494114508, + -1.84206304048352, -1.39680224666743, -1.39680224666741, + -1.70710678118655, -0.707106781186559}; + +//q31_t + q31_t cfft_testinput_q31_50hz_200Hz[512] = {0}, + cfft_testinput_q31_50hz_200Hz_ref[512] = {0}; + +//q15_t + q15_t cfft_testinput_q15_50hz_200Hz[512] = { + 32767, 0, 32767, -24386, 32767, -32768, 19070, -32768, 0, + -32768, -9597, -23170, -7249, -7249, 4750, 1967, 20251, 0, + 31635, -13104, 32767, -32768, 21383, -32768, 0, -32768, -25002, + -32768, -32768, -32768, -32768, -23170, -32768, 0, -32768, 16287, + -21038, 21038, -5854, 14134, 0, 0, -5854, -14134, -21038, + -21038, -32768, -16287, -32768, 0, -32768, 23170, -32768, 32767, + -25002, 32767, 0, 32767, 21383, 32767, 32767, 32767, 31635, + 13104, 20251, 0, 4750, -1967, -7249, 7249, -9597, 23170, + 0, 32767, 19070, 32767, 32767, 32767, 32767, 24386, 32767, + 0, 32767, -24386, 32767, -32768, 19070, -32768, 0, -32768, + -9597, -23170, -7249, -7249, 4750, 1967, 20251, 0, 31635, + -13104, 32767, -32768, 21383, -32768, 0, -32768, -25002, -32768, + -32768, -32768, -32768, -23170, -32768, 0, -32768, 16287, -21038, + 21038, -5854, 14134, 0, 0, -5854, -14134, -21038, -21038, + -32768, -16287, -32768, 0, -32768, 23170, -32768, 32767, -25002, + 32767, 0, 32767, 21383, 32767, 32767, 32767, 31635, 13104, + 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-23170, + -32768, 0, -32768, 16287, -21038, 21038, -5854, 14134, 0, + 0, -5854, -14134, -21038, -21038, -32768, -16287, -32768, 0, + -32768, 23170, -32768, 32767, -25002, 32767, 0, 32767, 21383, + 32767, 32767, 32767, 31635, 13104, 20251, 0, 4750, -1967, + -7249, 7249, -9597, 23170, 0, 32767, 19070, 32767, 32767, + 32767, 32767, 24386, 32767, 0, 32767, -24386, 32767, -32768, + 19070, -32768, 0, -32768, -9597, -23170, -7249, -7249, 4750, + 1967, 20251, 0, 31635, -13104, 32767, -32768, 21383, -32768, + 0, -32768, -25002, -32768, -32768, -32768, -32768, -23170}; + q15_t cfft_testinput_q15_50hz_200Hz_ref[512] = { + 32767, 0, 32767, -24386, 32767, -32768, 19070, -32768, 0, + -32768, -9597, -23170, -7249, -7249, 4750, 1967, 20251, 0, + 31635, -13104, 32767, -32768, 21383, -32768, 0, -32768, -25002, + -32768, -32768, -32768, -32768, -23170, -32768, 0, -32768, 16287, + -21038, 21038, -5854, 14134, 0, 0, -5854, -14134, -21038, + -21038, -32768, -16287, -32768, 0, -32768, 23170, -32768, 32767, + -25002, 32767, 0, 32767, 21383, 32767, 32767, 32767, 31635, + 13104, 20251, 0, 4750, -1967, -7249, 7249, -9597, 23170, + 0, 32767, 19070, 32767, 32767, 32767, 32767, 24386, 32767, + 0, 32767, -24386, 32767, -32768, 19070, -32768, 0, -32768, + -9597, -23170, -7249, -7249, 4750, 1967, 20251, 0, 31635, + -13104, 32767, -32768, 21383, -32768, 0, -32768, -25002, -32768, + -32768, -32768, -32768, -23170, -32768, 0, -32768, 16287, -21038, + 21038, -5854, 14134, 0, 0, -5854, -14134, -21038, -21038, + -32768, -16287, -32768, 0, -32768, 23170, -32768, 32767, -25002, + 32767, 0, 32767, 21383, 32767, 32767, 32767, 31635, 13104, + 20251, 0, 4750, -1967, -7249, 7249, -9597, 23170, 0, + 32767, 19070, 32767, 32767, 32767, 32767, 24386, 32767, 0, + 32767, -24386, 32767, -32768, 19070, -32768, 0, -32768, -9597, + -23170, -7249, -7249, 4750, 1967, 20251, 0, 31635, -13104, + 32767, -32768, 21383, -32768, 0, -32768, -25002, -32768, -32768, + -32768, -32768, -23170, -32768, 0, -32768, 16287, -21038, 21038, + -5854, 14134, 0, 0, -5854, -14134, -21038, -21038, -32768, + -16287, -32768, 0, -32768, 23170, -32768, 32767, -25002, 32767, + 0, 32767, 21383, 32767, 32767, 32767, 31635, 13104, 20251, + 0, 4750, -1967, -7249, 7249, -9597, 23170, 0, 32767, + 19070, 32767, 32767, 32767, 32767, 24386, 32767, 0, 32767, + -24386, 32767, -32768, 19070, -32768, 0, -32768, -9597, -23170, + -7249, -7249, 4750, 1967, 20251, 0, 31635, -13104, 32767, + -32768, 21383, -32768, 0, -32768, -25002, -32768, -32768, -32768, + -32768, -23170, -32768, 0, -32768, 16287, -21038, 21038, -5854, + 14134, 0, 0, -5854, -14134, -21038, -21038, -32768, -16287, + -32768, 0, -32768, 23170, -32768, 32767, -25002, 32767, 0, + 32767, 21383, 32767, 32767, 32767, 31635, 13104, 20251, 0, + 4750, -1967, -7249, 7249, -9597, 23170, 0, 32767, 19070, + 32767, 32767, 32767, 32767, 24386, 32767, 0, 32767, -24386, + 32767, -32768, 19070, -32768, 0, -32768, -9597, -23170, -7249, + -7249, 4750, 1967, 20251, 0, 31635, -13104, 32767, -32768, + 21383, -32768, 0, -32768, -25002, -32768, -32768, -32768, -32768, + -23170, -32768, 0, -32768, 16287, -21038, 21038, -5854, 14134, + 0, 0, -5854, -14134, -21038, -21038, -32768, -16287, -32768, + 0, -32768, 23170, -32768, 32767, -25002, 32767, 0, 32767, + 21383, 32767, 32767, 32767, 31635, 13104, 20251, 0, 4750, + -1967, -7249, 7249, -9597, 23170, 0, 32767, 19070, 32767, + 32767, 32767, 32767, 24386, 32767, 0, 32767, -24386, 32767, + -32768, 19070, -32768, 0, -32768, -9597, -23170, -7249, -7249, + 4750, 1967, 20251, 0, 31635, -13104, 32767, -32768, 21383, + -32768, 0, -32768, -25002, -32768, -32768, -32768, -32768, -23170, + -32768, 0, -32768, 16287, -21038, 21038, -5854, 14134, 0, + 0, -5854, -14134, -21038, -21038, -32768, -16287, -32768, 0, + -32768, 23170, -32768, 32767, -25002, 32767, 0, 32767, 21383, + 32767, 32767, 32767, 31635, 13104, 20251, 0, 4750, -1967, + -7249, 7249, -9597, 23170, 0, 32767, 19070, 32767, 32767, + 32767, 32767, 24386, 32767, 0, 32767, -24386, 32767, -32768, + 19070, -32768, 0, -32768, -9597, -23170, -7249, -7249, 4750, + 1967, 20251, 0, 31635, -13104, 32767, -32768, 21383, -32768, + 0, -32768, -25002, -32768, -32768, -32768, -32768, -23170}; diff --git a/examples/dsp/TransformFunction_cfftx4/cfft.c b/examples/dsp/TransformFunction_cfftx4/cfft.c new file mode 100644 index 00000000..98c71c22 --- /dev/null +++ b/examples/dsp/TransformFunction_cfftx4/cfft.c @@ -0,0 +1,618 @@ +#include "riscv_const_structs.h" +#include "ref.h" + +void ref_cfft_f32(const riscv_cfft_instance_f32 *S, float32_t *p1, + uint8_t ifftFlag, uint8_t bitReverseFlag) +{ + int n, mmax, m, j, istep, i; + float32_t wtemp, wr, wpr, wpi, wi, theta; + float32_t tempr, tempi; + float32_t *data = p1; + uint32_t N = S->fftLen; + int32_t dir = (ifftFlag) ? -1 : 1; + + // decrement pointer since the original version used fortran style indexing. + data--; + + n = N << 1; + j = 1; + for (i = 1; i < n; i += 2) { + if (j > i) { + tempr = data[j]; + data[j] = data[i]; + data[i] = tempr; + tempr = data[j + 1]; + data[j + 1] = data[i + 1]; + data[i + 1] = tempr; + } + m = n >> 1; + while (m >= 2 && j > m) { + j -= m; + m >>= 1; + } + j += m; + } + mmax = 2; + while (n > mmax) { + istep = 2 * mmax; + theta = -6.283185307179586f / (dir * mmax); + wtemp = sinf(0.5f * theta); + wpr = -2.0f * wtemp * wtemp; + wpi = sinf(theta); + wr = 1.0f; + wi = 0.0f; + for (m = 1; m < mmax; m += 2) { + for (i = m; i <= n; i += istep) { + j = i + mmax; + tempr = wr * data[j] - wi * data[j + 1]; + tempi = wr * data[j + 1] + wi * data[j]; + data[j] = data[i] - tempr; + data[j + 1] = data[i + 1] - tempi; + data[i] += tempr; + data[i + 1] += tempi; + } + wr = (wtemp = wr) * wpr - wi * wpi + wr; + wi = wi * wpr + wtemp * wpi + wi; + } + mmax = istep; + } + + // Inverse transform is scaled by 1/N + if (ifftFlag) { + data++; + for (i = 0; i < 2 * N; i++) { + data[i] /= N; + } + } +} + +void ref_cfft_q31(const riscv_cfft_instance_q31 *S, q31_t *p1, uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + uint32_t i; + // float32_t *fSrc = (float32_t*)p1; + float32_t fSrc[S->fftLen * 2]; + riscv_q31_to_float(p1, fSrc, S->fftLen * 2); + for (i = 0; i < S->fftLen * 2; i++) { + // read the q31 data, cast to float, scale down for float + fSrc[i] = (float32_t)p1[i] / 2147483648.0f; + } + + switch (S->fftLen) { + case 16: + ref_cfft_f32(&riscv_cfft_sR_f32_len16, fSrc, ifftFlag, + bitReverseFlag); + break; + + case 32: + ref_cfft_f32(&riscv_cfft_sR_f32_len32, fSrc, ifftFlag, + bitReverseFlag); + break; + + case 64: + ref_cfft_f32(&riscv_cfft_sR_f32_len64, fSrc, ifftFlag, + bitReverseFlag); + break; + + case 128: + ref_cfft_f32(&riscv_cfft_sR_f32_len128, fSrc, ifftFlag, + bitReverseFlag); + break; + + case 256: + ref_cfft_f32(&riscv_cfft_sR_f32_len256, fSrc, ifftFlag, + bitReverseFlag); + break; + + case 512: + ref_cfft_f32(&riscv_cfft_sR_f32_len512, fSrc, ifftFlag, + bitReverseFlag); + break; + + case 1024: + ref_cfft_f32(&riscv_cfft_sR_f32_len1024, fSrc, ifftFlag, + bitReverseFlag); + break; + + case 2048: + ref_cfft_f32(&riscv_cfft_sR_f32_len2048, fSrc, ifftFlag, + bitReverseFlag); + break; + + case 4096: + ref_cfft_f32(&riscv_cfft_sR_f32_len4096, fSrc, ifftFlag, + bitReverseFlag); + break; + } + + if (ifftFlag) { + for (i = 0; i < S->fftLen * 2; i++) { + // read the float data, scale up for q31, cast to q31 + p1[i] = (q31_t)(fSrc[i] * 2147483648.0f); + } + } else { + for (i = 0; i < S->fftLen * 2; i++) { + // read the float data, scale up for q31, cast to q31 + p1[i] = (q31_t)(fSrc[i] * 2147483648.0f / (float32_t)S->fftLen); + } + } +} + +void ref_cfft_q15(const riscv_cfft_instance_q15 *S, q15_t *pSrc, uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + uint32_t i; + // float32_t *fSrc = (float32_t*)pSrc; + float32_t fSrc[S->fftLen * 2]; + riscv_q15_to_float(pSrc, fSrc, S->fftLen * 2); + + for (i = 0; i < S->fftLen * 2; i++) { + // read the q15 data, cast to float, scale down for float, place in + // temporary buffer + scratchArray[i] = (float32_t)pSrc[i] / 32768.0f; + } + + for (i = 0; i < S->fftLen * 2; i++) { + // copy from temp buffer to final buffer + fSrc[i] = scratchArray[i]; + } + + switch (S->fftLen) { + case 16: + ref_cfft_f32(&riscv_cfft_sR_f32_len16, fSrc, ifftFlag, + bitReverseFlag); + break; + + case 32: + ref_cfft_f32(&riscv_cfft_sR_f32_len32, fSrc, ifftFlag, + bitReverseFlag); + break; + + case 64: + ref_cfft_f32(&riscv_cfft_sR_f32_len64, fSrc, ifftFlag, + bitReverseFlag); + break; + + case 128: + ref_cfft_f32(&riscv_cfft_sR_f32_len128, fSrc, ifftFlag, + bitReverseFlag); + break; + + case 256: + ref_cfft_f32(&riscv_cfft_sR_f32_len256, fSrc, ifftFlag, + bitReverseFlag); + break; + + case 512: + ref_cfft_f32(&riscv_cfft_sR_f32_len512, fSrc, ifftFlag, + bitReverseFlag); + break; + + case 1024: + ref_cfft_f32(&riscv_cfft_sR_f32_len1024, fSrc, ifftFlag, + bitReverseFlag); + break; + + case 2048: + ref_cfft_f32(&riscv_cfft_sR_f32_len2048, fSrc, ifftFlag, + bitReverseFlag); + break; + + case 4096: + ref_cfft_f32(&riscv_cfft_sR_f32_len4096, fSrc, ifftFlag, + bitReverseFlag); + break; + } + + if (ifftFlag) { + for (i = 0; i < S->fftLen * 2; i++) { + // read the float data, scale up for q15, cast to q15 + pSrc[i] = (q15_t)(fSrc[i] * 32768.0f); + } + } else { + for (i = 0; i < S->fftLen * 2; i++) { + // read the float data, scale up for q15, cast to q15 + pSrc[i] = (q15_t)(fSrc[i] * 32768.0f / (float32_t)S->fftLen); + } + } +} + +void ref_cfft_radix2_f32(const riscv_cfft_radix2_instance_f32 *S, float32_t *pSrc) +{ + switch (S->fftLen) { + case 16: + ref_cfft_f32(&riscv_cfft_sR_f32_len16, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 32: + ref_cfft_f32(&riscv_cfft_sR_f32_len32, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 64: + ref_cfft_f32(&riscv_cfft_sR_f32_len64, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 128: + ref_cfft_f32(&riscv_cfft_sR_f32_len128, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 256: + ref_cfft_f32(&riscv_cfft_sR_f32_len256, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 512: + ref_cfft_f32(&riscv_cfft_sR_f32_len512, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 1024: + ref_cfft_f32(&riscv_cfft_sR_f32_len1024, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 2048: + ref_cfft_f32(&riscv_cfft_sR_f32_len2048, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 4096: + ref_cfft_f32(&riscv_cfft_sR_f32_len4096, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + } +} + +void ref_cfft_radix2_q31(const riscv_cfft_radix2_instance_q31 *S, q31_t *pSrc) +{ + uint32_t i; + // float32_t *fSrc = (float32_t*)pSrc; + float32_t fSrc[S->fftLen * 2]; + riscv_q31_to_float(pSrc, fSrc, S->fftLen * 2); + + for (i = 0; i < S->fftLen * 2; i++) { + // read the q31 data, cast to float, scale down for float + fSrc[i] = (float32_t)pSrc[i] / 2147483648.0f; + } + + switch (S->fftLen) { + case 16: + ref_cfft_f32(&riscv_cfft_sR_f32_len16, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 32: + ref_cfft_f32(&riscv_cfft_sR_f32_len32, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 64: + ref_cfft_f32(&riscv_cfft_sR_f32_len64, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 128: + ref_cfft_f32(&riscv_cfft_sR_f32_len128, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 256: + ref_cfft_f32(&riscv_cfft_sR_f32_len256, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 512: + ref_cfft_f32(&riscv_cfft_sR_f32_len512, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 1024: + ref_cfft_f32(&riscv_cfft_sR_f32_len1024, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 2048: + ref_cfft_f32(&riscv_cfft_sR_f32_len2048, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 4096: + ref_cfft_f32(&riscv_cfft_sR_f32_len4096, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + } + + if (S->ifftFlag) { + for (i = 0; i < S->fftLen * 2; i++) { + // read the float data, scale up for q31, cast to q31 + pSrc[i] = (q31_t)(fSrc[i] * 2147483648.0f); + } + } else { + for (i = 0; i < S->fftLen * 2; i++) { + // read the float data, scale up for q31, cast to q31 + pSrc[i] = (q31_t)(fSrc[i] * 2147483648.0f / (float32_t)S->fftLen); + } + } +} + +void ref_cfft_radix2_q15(const riscv_cfft_radix2_instance_q15 *S, q15_t *pSrc) +{ + uint32_t i; + // float32_t *fSrc = (float32_t*)pSrc; + float32_t fSrc[S->fftLen * 2]; + riscv_q15_to_float(pSrc, fSrc, S->fftLen * 2); + + for (i = 0; i < S->fftLen * 2; i++) { + // read the q15 data, cast to float, scale down for float, place in + // temporary buffer + scratchArray[i] = (float32_t)pSrc[i] / 32768.0f; + } + + for (i = 0; i < S->fftLen * 2; i++) { + // copy from temp buffer to final buffer + fSrc[i] = scratchArray[i]; + } + + switch (S->fftLen) { + case 16: + ref_cfft_f32(&riscv_cfft_sR_f32_len16, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 32: + ref_cfft_f32(&riscv_cfft_sR_f32_len32, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 64: + ref_cfft_f32(&riscv_cfft_sR_f32_len64, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 128: + ref_cfft_f32(&riscv_cfft_sR_f32_len128, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 256: + ref_cfft_f32(&riscv_cfft_sR_f32_len256, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 512: + ref_cfft_f32(&riscv_cfft_sR_f32_len512, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 1024: + ref_cfft_f32(&riscv_cfft_sR_f32_len1024, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 2048: + ref_cfft_f32(&riscv_cfft_sR_f32_len2048, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 4096: + ref_cfft_f32(&riscv_cfft_sR_f32_len4096, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + } + + if (S->ifftFlag) { + for (i = 0; i < S->fftLen * 2; i++) { + // read the float data, scale up for q15, cast to q15 + pSrc[i] = (q15_t)(fSrc[i] * 32768.0f); + } + } else { + for (i = 0; i < S->fftLen * 2; i++) { + // read the float data, scale up for q15, cast to q15 + pSrc[i] = (q15_t)(fSrc[i] * 32768.0f / (float32_t)S->fftLen); + } + } +} + +void ref_cfft_radix4_f32(const riscv_cfft_radix4_instance_f32 *S, float32_t *pSrc) +{ + switch (S->fftLen) { + case 16: + ref_cfft_f32(&riscv_cfft_sR_f32_len16, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 32: + ref_cfft_f32(&riscv_cfft_sR_f32_len32, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 64: + ref_cfft_f32(&riscv_cfft_sR_f32_len64, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 128: + ref_cfft_f32(&riscv_cfft_sR_f32_len128, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 256: + ref_cfft_f32(&riscv_cfft_sR_f32_len256, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 512: + ref_cfft_f32(&riscv_cfft_sR_f32_len512, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 1024: + ref_cfft_f32(&riscv_cfft_sR_f32_len1024, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 2048: + ref_cfft_f32(&riscv_cfft_sR_f32_len2048, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 4096: + ref_cfft_f32(&riscv_cfft_sR_f32_len4096, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + } +} + +void ref_cfft_radix4_q31(const riscv_cfft_radix4_instance_q31 *S, q31_t *pSrc) +{ + uint32_t i; + // float32_t *fSrc = (float32_t*)pSrc; + float32_t fSrc[S->fftLen * 2]; + riscv_q31_to_float(pSrc, fSrc, S->fftLen * 2); + + for (i = 0; i < S->fftLen * 2; i++) { + // read the q31 data, cast to float, scale down for float + fSrc[i] = (float32_t)pSrc[i] / 2147483648.0f; + } + + switch (S->fftLen) { + case 16: + ref_cfft_f32(&riscv_cfft_sR_f32_len16, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 32: + ref_cfft_f32(&riscv_cfft_sR_f32_len32, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 64: + ref_cfft_f32(&riscv_cfft_sR_f32_len64, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 128: + ref_cfft_f32(&riscv_cfft_sR_f32_len128, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 256: + ref_cfft_f32(&riscv_cfft_sR_f32_len256, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 512: + ref_cfft_f32(&riscv_cfft_sR_f32_len512, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 1024: + ref_cfft_f32(&riscv_cfft_sR_f32_len1024, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 2048: + ref_cfft_f32(&riscv_cfft_sR_f32_len2048, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 4096: + ref_cfft_f32(&riscv_cfft_sR_f32_len4096, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + } + + if (S->ifftFlag) { + for (i = 0; i < S->fftLen * 2; i++) { + // read the float data, scale up for q31, cast to q31 + pSrc[i] = (q31_t)(fSrc[i] * 2147483648.0f); + } + } else { + for (i = 0; i < S->fftLen * 2; i++) { + // read the float data, scale up for q31, cast to q31 + pSrc[i] = (q31_t)(fSrc[i] * 2147483648.0f / (float32_t)S->fftLen); + } + } +} + +void ref_cfft_radix4_q15(const riscv_cfft_radix4_instance_q15 *S, q15_t *pSrc) +{ + uint32_t i; + // float32_t *fSrc = (float32_t*)pSrc; + float32_t fSrc[S->fftLen * 2]; + riscv_q15_to_float(pSrc, fSrc, S->fftLen * 2); + + for (i = 0; i < S->fftLen * 2; i++) { + // read the q15 data, cast to float, scale down for float, place in + // temporary buffer + scratchArray[i] = (float32_t)pSrc[i] / 32768.0f; + } + + for (i = 0; i < S->fftLen * 2; i++) { + // copy from temp buffer to final buffer + fSrc[i] = scratchArray[i]; + } + + switch (S->fftLen) { + case 16: + ref_cfft_f32(&riscv_cfft_sR_f32_len16, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 32: + ref_cfft_f32(&riscv_cfft_sR_f32_len32, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 64: + ref_cfft_f32(&riscv_cfft_sR_f32_len64, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 128: + ref_cfft_f32(&riscv_cfft_sR_f32_len128, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 256: + ref_cfft_f32(&riscv_cfft_sR_f32_len256, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 512: + ref_cfft_f32(&riscv_cfft_sR_f32_len512, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 1024: + ref_cfft_f32(&riscv_cfft_sR_f32_len1024, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 2048: + ref_cfft_f32(&riscv_cfft_sR_f32_len2048, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 4096: + ref_cfft_f32(&riscv_cfft_sR_f32_len4096, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + } + + if (S->ifftFlag) { + for (i = 0; i < S->fftLen * 2; i++) { + // read the float data, scale up for q15, cast to q15 + pSrc[i] = (q15_t)(fSrc[i] * 32768.0f); + } + } else { + for (i = 0; i < S->fftLen * 2; i++) { + // read the float data, scale up for q15, cast to q15 + pSrc[i] = (q15_t)(fSrc[i] * 32768.0f / (float32_t)S->fftLen); + } + } +} diff --git a/examples/dsp/TransformFunction_cfftx4/main.c b/examples/dsp/TransformFunction_cfftx4/main.c new file mode 100644 index 00000000..add416cc --- /dev/null +++ b/examples/dsp/TransformFunction_cfftx4/main.c @@ -0,0 +1,125 @@ +// +// Created by lujun on 19-6-28. +// +// This contains SIN_COS , clarke, inv_clarke, park, inv_park and pid +// each one has it's own function. +// All function can be found in main function. +// If you don't want to use it, then comment it. +#include "riscv_common_tables.h" +#include "riscv_const_structs.h" +#include "riscv_math.h" +#include "array.h" +#include +#include "../common.h" + +#include "../HelperFunctions/math_helper.c" +#include "../HelperFunctions/ref_helper.c" + +#include +#define DELTAF32 (0.05f) +#define DELTAQ31 (63) +#define DELTAQ15 (1) +#define DELTAQ7 (1) + +int test_flag_error = 0; + +uint32_t fftSize = 1024; +uint32_t ifftFlag = 0; +uint32_t doBitReverse = 1; + +static int DSP_cfft_radix4_f32(void) +{ + uint16_t i; + + fftSize = 256; + + riscv_cfft_radix4_instance_f32 S; + uint8_t ifftFlag = 0, doBitReverse = 1; + riscv_cfft_radix4_init_f32(&S, 256, ifftFlag, doBitReverse); + BENCH_START(riscv_cfft_radix4_f32); + riscv_cfft_radix4_f32(&S, cfft_testinput_f32_50hz_200Hz); + BENCH_END(riscv_cfft_radix4_f32); + ref_cfft_radix4_f32(&S, cfft_testinput_f32_50hz_200Hz_ref); + float32_t resault, resault_ref; + uint32_t index, index_ref; + riscv_max_f32(cfft_testinput_f32_50hz_200Hz, 256, &resault, &index); + riscv_max_f32(cfft_testinput_f32_50hz_200Hz_ref, 256, &resault_ref, + &index_ref); + if (index != index_ref) { + BENCH_ERROR(riscv_cfft_radix4_f32); + printf("expect: %d, actual: %d\n", index_ref, index); + test_flag_error = 1; + } + BENCH_STATUS(riscv_cfft_radix4_f32); +} + +static int DSP_cfft_radix4_q15(void) +{ + uint16_t i; + fftSize = 256; + riscv_cfft_radix4_instance_q15 S; + uint8_t ifftFlag = 0, doBitReverse = 1; + riscv_cfft_radix4_init_q15(&S, 256, ifftFlag, doBitReverse); + BENCH_START(riscv_cfft_radix4_q15); + riscv_cfft_radix4_q15(&S, cfft_testinput_q15_50hz_200Hz); + BENCH_END(riscv_cfft_radix4_q15); + ref_cfft_radix4_q15(&S, cfft_testinput_q15_50hz_200Hz_ref); + q15_t resault, resault_ref; + uint32_t index, index_ref = 117; + riscv_shift_q15(cfft_testinput_q15_50hz_200Hz, 8, + cfft_testinput_q15_50hz_200Hz, fftSize); + riscv_max_q15(cfft_testinput_q15_50hz_200Hz, 256, &resault, &index); + riscv_shift_q15(cfft_testinput_q15_50hz_200Hz_ref, 8, + cfft_testinput_q15_50hz_200Hz_ref, fftSize); + riscv_max_q15(cfft_testinput_q15_50hz_200Hz_ref, 256, &resault_ref, + &index_ref); + if (index != index_ref) { + BENCH_ERROR(riscv_cfft_radix4_q15); + printf("expect: %d, actual: %d\n", index_ref, index); + test_flag_error = 1; + } + BENCH_STATUS(riscv_cfft_radix4_q15); +} +static int DSP_cfft_radix4_q31(void) +{ + uint16_t i; + riscv_float_to_q31(cfft_testinput_f32_50hz_200Hz, + cfft_testinput_q31_50hz_200Hz, 512); + riscv_float_to_q31(cfft_testinput_f32_50hz_200Hz_ref, + cfft_testinput_q31_50hz_200Hz_ref, 512); + fftSize = 256; + riscv_cfft_radix4_instance_q31 S; + uint8_t ifftFlag = 0, doBitReverse = 1; + riscv_cfft_radix4_init_q31(&S, 256, ifftFlag, doBitReverse); + BENCH_START(riscv_cfft_radix4_q31); + riscv_cfft_radix4_q31(&S, cfft_testinput_q31_50hz_200Hz); + BENCH_END(riscv_cfft_radix4_q31); + ref_cfft_radix4_q31(&S, cfft_testinput_q31_50hz_200Hz_ref); + q31_t resault, resault_ref; + uint32_t index, index_ref; + riscv_max_q31(cfft_testinput_q31_50hz_200Hz, 256, &resault, &index); + riscv_max_q31(cfft_testinput_q31_50hz_200Hz_ref, 256, &resault_ref, + &index_ref); + if (index != index_ref) { + BENCH_ERROR(riscv_cfft_radix4_q31); + printf("expect: %d, actual: %d\n", index_ref, index); + test_flag_error = 1; + } + BENCH_STATUS(riscv_cfft_radix4_q31); +} + +int main() +{ + BENCH_INIT; + DSP_cfft_radix4_f32(); + DSP_cfft_radix4_q15(); + DSP_cfft_radix4_q31(); + BENCH_FINISH; + if (test_flag_error) { + printf("test error apprears, please recheck.\n"); + return 1; + } else { + printf("all test are passed. Well done!\n"); + } + return 0; +} diff --git a/examples/dsp/TransformFunction_dct4/CMakeLists.txt b/examples/dsp/TransformFunction_dct4/CMakeLists.txt new file mode 100644 index 00000000..0dcb5c77 --- /dev/null +++ b/examples/dsp/TransformFunction_dct4/CMakeLists.txt @@ -0,0 +1,5 @@ +set(TARGET_REQUIRED_PRIVATE_INCLUDE ${CMAKE_CURRENT_SOURCE_DIR} ${CMAKE_CURRENT_SOURCE_DIR}/..) +set(TARGET_REQUIRED_LIBS nmsis) +list(APPEND TARGET_REQUIRED_SRCS dct4.c) +set(mains main.c) +generate_bin() \ No newline at end of file diff --git a/examples/dsp/TransformFunction_dct4/array.h b/examples/dsp/TransformFunction_dct4/array.h new file mode 100644 index 00000000..02c1dc9b --- /dev/null +++ b/examples/dsp/TransformFunction_dct4/array.h @@ -0,0 +1,20 @@ +// Array for TransformFunctions dct4 +#define ARRAY_SIZE 100 +//float32_t + float32_t f32_state[256] = {0}; + float32_t dct4_testinput_f32_50hz_200Hz[256] = { + 0,0.744219717332704,1.26007351067010,1.40504701603470,1.17557050458495,0.707106781186548,0.221231742082474,-0.0600499921067857,-1.11022302462516e-16,0.399903088302664,1.00000000000000,1.57547359288761,1.90211303259031,1.84206304048352,1.39680224666742,0.707106781186548,4.44089209850063e-16,-0.497066016555608,-0.642039521920206,-0.431350787252243,-3.67394039744206e-16,0.431350787252243,0.642039521920206,0.497066016555607,-1.22124532708767e-15,-0.707106781186549,-1.39680224666742,-1.84206304048352,-1.90211303259031,-1.57547359288761,-1.00000000000000,-0.399903088302665,-3.33066907387547e-16,0.0600499921067852,-0.221231742082476,-0.707106781186550,-1.17557050458495,-1.40504701603470,-1.26007351067010,-0.744219717332705,-1.22464679914735e-15,0.744219717332707,1.26007351067010,1.40504701603470,1.17557050458495,0.707106781186549,0.221231742082475,-0.0600499921067854,8.88178419700125e-16,0.399903088302667,1.00000000000000,1.57547359288761,1.90211303259031,1.84206304048352,1.39680224666742,0.707106781186545,1.33226762955019e-15,-0.497066016555608,-0.642039521920206,-0.431350787252245,-1.10218211923262e-15,0.431350787252243,0.642039521920206,0.497066016555606,1.55431223447522e-15,-0.707106781186550,-1.39680224666743,-1.84206304048352,-1.90211303259031,-1.57547359288761,-0.999999999999995,-0.399903088302669,-7.77156117237610e-16,0.0600499921067867,-0.221231742082473,-0.707106781186549,-1.17557050458495,-1.40504701603470,-1.26007351067010,-0.744219717332702,-2.44929359829471e-15,0.744219717332706,1.26007351067010,1.40504701603470,1.17557050458494,0.707106781186546,0.221231742082476,-0.0600499921067846,-7.77156117237610e-16,0.399903088302660,0.999999999999998,1.57547359288761,1.90211303259031,1.84206304048352,1.39680224666742,0.707106781186546,-4.88498130835069e-15,-0.497066016555607,-0.642039521920206,-0.431350787252242,3.49210031947972e-15,0.431350787252243,0.642039521920206,0.497066016555610,2.55351295663786e-15,-0.707106781186549,-1.39680224666742,-1.84206304048352,-1.90211303259031,-1.57547359288761,-0.999999999999996,-0.399903088302658,-9.99200722162641e-16,0.0600499921067855,-0.221231742082477,-0.707106781186554,-1.17557050458494,-1.40504701603470,-1.26007351067011,-0.744219717332711,-3.67394039744206e-15,0.744219717332705,1.26007351067010,1.40504701603470,1.17557050458495,0.707106781186547,0.221231742082472,-0.0600499921067872,-1.22124532708767e-15,0.399903088302665,1.00000000000000,1.57547359288762,1.90211303259031,1.84206304048352,1.39680224666742,0.707106781186539,-1.09912079437891e-14,-0.497066016555607,-0.642039521920206,-0.431350787252238,8.08638275819206e-15,0.431350787252234,0.642039521920205,0.497066016555611,3.55271367880050e-15,-0.707106781186548,-1.39680224666741,-1.84206304048352,-1.90211303259031,-1.57547359288761,-0.999999999999997,-0.399903088302671,-1.44328993201270e-15,0.0600499921067857,-0.221231742082476,-0.707106781186553,-1.17557050458494,-1.40504701603470,-1.26007351067010,-0.744219717332697,-4.89858719658941e-15,0.744219717332704,1.26007351067010,1.40504701603470,1.17557050458494,0.707106781186548,0.221231742082472,-0.0600499921067871,3.88578058618805e-15,0.399903088302676,1.00000000000000,1.57547359288762,1.90211303259031,1.84206304048352,1.39680224666743,0.707106781186557,4.44089209850063e-15,-0.497066016555606,-0.642039521920207,-0.431350787252247,-3.30654635769785e-15,0.431350787252242,0.642039521920206,0.497066016555611,4.55191440096314e-15,-0.707106781186546,-1.39680224666742,-1.84206304048352,-1.90211303259031,-1.57547359288761,-0.999999999999998,-0.399903088302660,3.66373598126302e-15,0.0600499921067860,-0.221231742082476,-0.707106781186552,-1.17557050458495,-1.40504701603470,-1.26007351067010,-0.744219717332698,1.16403343982657e-14,0.744219717332718,1.26007351067010,1.40504701603470,1.17557050458496,0.707106781186561,0.221231742082482,-0.0600499921067840,-1.99840144432528e-15,0.399903088302663,1.00000000000000,1.57547359288762,1.90211303259031,1.84206304048353,1.39680224666743,0.707106781186558,5.44009282066327e-15,-0.497066016555606,-0.642039521920206,-0.431350787252239,6.61680659921524e-15,0.431350787252249,0.642039521920207,0.497066016555612,5.55111512312578e-15,-0.707106781186545,-1.39680224666742,-1.84206304048352,-1.90211303259031,-1.57547359288760,-0.999999999999984,-0.399903088302648,-2.10942374678780e-15,0.0600499921067861,-0.221231742082475,-0.707106781186552,-1.17557050458493,-1.40504701603470,-1.26007351067011,-0.744219717332714,-7.34788079488412e-15,0.744219717332702,1.26007351067010,1.40504701603470,1.17557050458494,0.707106781186538,0.221231742082483,-0.0600499921067839,-2.33146835171283e-15,0.399903088302663,1.00000000000000,1.57547359288761,1.90211303259031,1.84206304048352,1.39680224666741,0.707106781186559}; + float32_t dct4_testinput_f32_50hz_200Hz_ref[256] = { + 0,0.744219717332704,1.26007351067010,1.40504701603470,1.17557050458495,0.707106781186548,0.221231742082474,-0.0600499921067857,-1.11022302462516e-16,0.399903088302664,1.00000000000000,1.57547359288761,1.90211303259031,1.84206304048352,1.39680224666742,0.707106781186548,4.44089209850063e-16,-0.497066016555608,-0.642039521920206,-0.431350787252243,-3.67394039744206e-16,0.431350787252243,0.642039521920206,0.497066016555607,-1.22124532708767e-15,-0.707106781186549,-1.39680224666742,-1.84206304048352,-1.90211303259031,-1.57547359288761,-1.00000000000000,-0.399903088302665,-3.33066907387547e-16,0.0600499921067852,-0.221231742082476,-0.707106781186550,-1.17557050458495,-1.40504701603470,-1.26007351067010,-0.744219717332705,-1.22464679914735e-15,0.744219717332707,1.26007351067010,1.40504701603470,1.17557050458495,0.707106781186549,0.221231742082475,-0.0600499921067854,8.88178419700125e-16,0.399903088302667,1.00000000000000,1.57547359288761,1.90211303259031,1.84206304048352,1.39680224666742,0.707106781186545,1.33226762955019e-15,-0.497066016555608,-0.642039521920206,-0.431350787252245,-1.10218211923262e-15,0.431350787252243,0.642039521920206,0.497066016555606,1.55431223447522e-15,-0.707106781186550,-1.39680224666743,-1.84206304048352,-1.90211303259031,-1.57547359288761,-0.999999999999995,-0.399903088302669,-7.77156117237610e-16,0.0600499921067867,-0.221231742082473,-0.707106781186549,-1.17557050458495,-1.40504701603470,-1.26007351067010,-0.744219717332702,-2.44929359829471e-15,0.744219717332706,1.26007351067010,1.40504701603470,1.17557050458494,0.707106781186546,0.221231742082476,-0.0600499921067846,-7.77156117237610e-16,0.399903088302660,0.999999999999998,1.57547359288761,1.90211303259031,1.84206304048352,1.39680224666742,0.707106781186546,-4.88498130835069e-15,-0.497066016555607,-0.642039521920206,-0.431350787252242,3.49210031947972e-15,0.431350787252243,0.642039521920206,0.497066016555610,2.55351295663786e-15,-0.707106781186549,-1.39680224666742,-1.84206304048352,-1.90211303259031,-1.57547359288761,-0.999999999999996,-0.399903088302658,-9.99200722162641e-16,0.0600499921067855,-0.221231742082477,-0.707106781186554,-1.17557050458494,-1.40504701603470,-1.26007351067011,-0.744219717332711,-3.67394039744206e-15,0.744219717332705,1.26007351067010,1.40504701603470,1.17557050458495,0.707106781186547,0.221231742082472,-0.0600499921067872,-1.22124532708767e-15,0.399903088302665,1.00000000000000,1.57547359288762,1.90211303259031,1.84206304048352,1.39680224666742,0.707106781186539,-1.09912079437891e-14,-0.497066016555607,-0.642039521920206,-0.431350787252238,8.08638275819206e-15,0.431350787252234,0.642039521920205,0.497066016555611,3.55271367880050e-15,-0.707106781186548,-1.39680224666741,-1.84206304048352,-1.90211303259031,-1.57547359288761,-0.999999999999997,-0.399903088302671,-1.44328993201270e-15,0.0600499921067857,-0.221231742082476,-0.707106781186553,-1.17557050458494,-1.40504701603470,-1.26007351067010,-0.744219717332697,-4.89858719658941e-15,0.744219717332704,1.26007351067010,1.40504701603470,1.17557050458494,0.707106781186548,0.221231742082472,-0.0600499921067871,3.88578058618805e-15,0.399903088302676,1.00000000000000,1.57547359288762,1.90211303259031,1.84206304048352,1.39680224666743,0.707106781186557,4.44089209850063e-15,-0.497066016555606,-0.642039521920207,-0.431350787252247,-3.30654635769785e-15,0.431350787252242,0.642039521920206,0.497066016555611,4.55191440096314e-15,-0.707106781186546,-1.39680224666742,-1.84206304048352,-1.90211303259031,-1.57547359288761,-0.999999999999998,-0.399903088302660,3.66373598126302e-15,0.0600499921067860,-0.221231742082476,-0.707106781186552,-1.17557050458495,-1.40504701603470,-1.26007351067010,-0.744219717332698,1.16403343982657e-14,0.744219717332718,1.26007351067010,1.40504701603470,1.17557050458496,0.707106781186561,0.221231742082482,-0.0600499921067840,-1.99840144432528e-15,0.399903088302663,1.00000000000000,1.57547359288762,1.90211303259031,1.84206304048353,1.39680224666743,0.707106781186558,5.44009282066327e-15,-0.497066016555606,-0.642039521920206,-0.431350787252239,6.61680659921524e-15,0.431350787252249,0.642039521920207,0.497066016555612,5.55111512312578e-15,-0.707106781186545,-1.39680224666742,-1.84206304048352,-1.90211303259031,-1.57547359288760,-0.999999999999984,-0.399903088302648,-2.10942374678780e-15,0.0600499921067861,-0.221231742082475,-0.707106781186552,-1.17557050458493,-1.40504701603470,-1.26007351067011,-0.744219717332714,-7.34788079488412e-15,0.744219717332702,1.26007351067010,1.40504701603470,1.17557050458494,0.707106781186538,0.221231742082483,-0.0600499921067839,-2.33146835171283e-15,0.399903088302663,1.00000000000000,1.57547359288761,1.90211303259031,1.84206304048352,1.39680224666741,0.707106781186559}; + +//q31_t + float32_t dct4_testinput_f32_50hz_200Hz_q31[256] = { + 0,0.744219717332704,1.26007351067010,1.40504701603470,1.17557050458495,0.707106781186548,0.221231742082474,-0.0600499921067857,-1.11022302462516e-16,0.399903088302664,1.00000000000000,1.57547359288761,1.90211303259031,1.84206304048352,1.39680224666742,0.707106781186548,4.44089209850063e-16,-0.497066016555608,-0.642039521920206,-0.431350787252243,-3.67394039744206e-16,0.431350787252243,0.642039521920206,0.497066016555607,-1.22124532708767e-15,-0.707106781186549,-1.39680224666742,-1.84206304048352,-1.90211303259031,-1.57547359288761,-1.00000000000000,-0.399903088302665,-3.33066907387547e-16,0.0600499921067852,-0.221231742082476,-0.707106781186550,-1.17557050458495,-1.40504701603470,-1.26007351067010,-0.744219717332705,-1.22464679914735e-15,0.744219717332707,1.26007351067010,1.40504701603470,1.17557050458495,0.707106781186549,0.221231742082475,-0.0600499921067854,8.88178419700125e-16,0.399903088302667,1.00000000000000,1.57547359288761,1.90211303259031,1.84206304048352,1.39680224666742,0.707106781186545,1.33226762955019e-15,-0.497066016555608,-0.642039521920206,-0.431350787252245,-1.10218211923262e-15,0.431350787252243,0.642039521920206,0.497066016555606,1.55431223447522e-15,-0.707106781186550,-1.39680224666743,-1.84206304048352,-1.90211303259031,-1.57547359288761,-0.999999999999995,-0.399903088302669,-7.77156117237610e-16,0.0600499921067867,-0.221231742082473,-0.707106781186549,-1.17557050458495,-1.40504701603470,-1.26007351067010,-0.744219717332702,-2.44929359829471e-15,0.744219717332706,1.26007351067010,1.40504701603470,1.17557050458494,0.707106781186546,0.221231742082476,-0.0600499921067846,-7.77156117237610e-16,0.399903088302660,0.999999999999998,1.57547359288761,1.90211303259031,1.84206304048352,1.39680224666742,0.707106781186546,-4.88498130835069e-15,-0.497066016555607,-0.642039521920206,-0.431350787252242,3.49210031947972e-15,0.431350787252243,0.642039521920206,0.497066016555610,2.55351295663786e-15,-0.707106781186549,-1.39680224666742,-1.84206304048352,-1.90211303259031,-1.57547359288761,-0.999999999999996,-0.399903088302658,-9.99200722162641e-16,0.0600499921067855,-0.221231742082477,-0.707106781186554,-1.17557050458494,-1.40504701603470,-1.26007351067011,-0.744219717332711,-3.67394039744206e-15,0.744219717332705,1.26007351067010,1.40504701603470,1.17557050458495,0.707106781186547,0.221231742082472,-0.0600499921067872,-1.22124532708767e-15,0.399903088302665,1.00000000000000,1.57547359288762,1.90211303259031,1.84206304048352,1.39680224666742,0.707106781186539,-1.09912079437891e-14,-0.497066016555607,-0.642039521920206,-0.431350787252238,8.08638275819206e-15,0.431350787252234,0.642039521920205,0.497066016555611,3.55271367880050e-15,-0.707106781186548,-1.39680224666741,-1.84206304048352,-1.90211303259031,-1.57547359288761,-0.999999999999997,-0.399903088302671,-1.44328993201270e-15,0.0600499921067857,-0.221231742082476,-0.707106781186553,-1.17557050458494,-1.40504701603470,-1.26007351067010,-0.744219717332697,-4.89858719658941e-15,0.744219717332704,1.26007351067010,1.40504701603470,1.17557050458494,0.707106781186548,0.221231742082472,-0.0600499921067871,3.88578058618805e-15,0.399903088302676,1.00000000000000,1.57547359288762,1.90211303259031,1.84206304048352,1.39680224666743,0.707106781186557,4.44089209850063e-15,-0.497066016555606,-0.642039521920207,-0.431350787252247,-3.30654635769785e-15,0.431350787252242,0.642039521920206,0.497066016555611,4.55191440096314e-15,-0.707106781186546,-1.39680224666742,-1.84206304048352,-1.90211303259031,-1.57547359288761,-0.999999999999998,-0.399903088302660,3.66373598126302e-15,0.0600499921067860,-0.221231742082476,-0.707106781186552,-1.17557050458495,-1.40504701603470,-1.26007351067010,-0.744219717332698,1.16403343982657e-14,0.744219717332718,1.26007351067010,1.40504701603470,1.17557050458496,0.707106781186561,0.221231742082482,-0.0600499921067840,-1.99840144432528e-15,0.399903088302663,1.00000000000000,1.57547359288762,1.90211303259031,1.84206304048353,1.39680224666743,0.707106781186558,5.44009282066327e-15,-0.497066016555606,-0.642039521920206,-0.431350787252239,6.61680659921524e-15,0.431350787252249,0.642039521920207,0.497066016555612,5.55111512312578e-15,-0.707106781186545,-1.39680224666742,-1.84206304048352,-1.90211303259031,-1.57547359288760,-0.999999999999984,-0.399903088302648,-2.10942374678780e-15,0.0600499921067861,-0.221231742082475,-0.707106781186552,-1.17557050458493,-1.40504701603470,-1.26007351067011,-0.744219717332714,-7.34788079488412e-15,0.744219717332702,1.26007351067010,1.40504701603470,1.17557050458494,0.707106781186538,0.221231742082483,-0.0600499921067839,-2.33146835171283e-15,0.399903088302663,1.00000000000000,1.57547359288761,1.90211303259031,1.84206304048352,1.39680224666741,0.707106781186559}; + q31_t q31_state[256] = {0}; + q31_t dct4_testinput_q31_50hz_200Hz[256], dct4_testinput_q31_50hz_200Hz_ref[256]; + +//q15_t + float32_t dct4_testinput_f32_50hz_200Hz_q15[256] = { + 0,0.744219717332704,1.26007351067010,1.40504701603470,1.17557050458495,0.707106781186548,0.221231742082474,-0.0600499921067857,-1.11022302462516e-16,0.399903088302664,1.00000000000000,1.57547359288761,1.90211303259031,1.84206304048352,1.39680224666742,0.707106781186548,4.44089209850063e-16,-0.497066016555608,-0.642039521920206,-0.431350787252243,-3.67394039744206e-16,0.431350787252243,0.642039521920206,0.497066016555607,-1.22124532708767e-15,-0.707106781186549,-1.39680224666742,-1.84206304048352,-1.90211303259031,-1.57547359288761,-1.00000000000000,-0.399903088302665,-3.33066907387547e-16,0.0600499921067852,-0.221231742082476,-0.707106781186550,-1.17557050458495,-1.40504701603470,-1.26007351067010,-0.744219717332705,-1.22464679914735e-15,0.744219717332707,1.26007351067010,1.40504701603470,1.17557050458495,0.707106781186549,0.221231742082475,-0.0600499921067854,8.88178419700125e-16,0.399903088302667,1.00000000000000,1.57547359288761,1.90211303259031,1.84206304048352,1.39680224666742,0.707106781186545,1.33226762955019e-15,-0.497066016555608,-0.642039521920206,-0.431350787252245,-1.10218211923262e-15,0.431350787252243,0.642039521920206,0.497066016555606,1.55431223447522e-15,-0.707106781186550,-1.39680224666743,-1.84206304048352,-1.90211303259031,-1.57547359288761,-0.999999999999995,-0.399903088302669,-7.77156117237610e-16,0.0600499921067867,-0.221231742082473,-0.707106781186549,-1.17557050458495,-1.40504701603470,-1.26007351067010,-0.744219717332702,-2.44929359829471e-15,0.744219717332706,1.26007351067010,1.40504701603470,1.17557050458494,0.707106781186546,0.221231742082476,-0.0600499921067846,-7.77156117237610e-16,0.399903088302660,0.999999999999998,1.57547359288761,1.90211303259031,1.84206304048352,1.39680224666742,0.707106781186546,-4.88498130835069e-15,-0.497066016555607,-0.642039521920206,-0.431350787252242,3.49210031947972e-15,0.431350787252243,0.642039521920206,0.497066016555610,2.55351295663786e-15,-0.707106781186549,-1.39680224666742,-1.84206304048352,-1.90211303259031,-1.57547359288761,-0.999999999999996,-0.399903088302658,-9.99200722162641e-16,0.0600499921067855,-0.221231742082477,-0.707106781186554,-1.17557050458494,-1.40504701603470,-1.26007351067011,-0.744219717332711,-3.67394039744206e-15,0.744219717332705,1.26007351067010,1.40504701603470,1.17557050458495,0.707106781186547,0.221231742082472,-0.0600499921067872,-1.22124532708767e-15,0.399903088302665,1.00000000000000,1.57547359288762,1.90211303259031,1.84206304048352,1.39680224666742,0.707106781186539,-1.09912079437891e-14,-0.497066016555607,-0.642039521920206,-0.431350787252238,8.08638275819206e-15,0.431350787252234,0.642039521920205,0.497066016555611,3.55271367880050e-15,-0.707106781186548,-1.39680224666741,-1.84206304048352,-1.90211303259031,-1.57547359288761,-0.999999999999997,-0.399903088302671,-1.44328993201270e-15,0.0600499921067857,-0.221231742082476,-0.707106781186553,-1.17557050458494,-1.40504701603470,-1.26007351067010,-0.744219717332697,-4.89858719658941e-15,0.744219717332704,1.26007351067010,1.40504701603470,1.17557050458494,0.707106781186548,0.221231742082472,-0.0600499921067871,3.88578058618805e-15,0.399903088302676,1.00000000000000,1.57547359288762,1.90211303259031,1.84206304048352,1.39680224666743,0.707106781186557,4.44089209850063e-15,-0.497066016555606,-0.642039521920207,-0.431350787252247,-3.30654635769785e-15,0.431350787252242,0.642039521920206,0.497066016555611,4.55191440096314e-15,-0.707106781186546,-1.39680224666742,-1.84206304048352,-1.90211303259031,-1.57547359288761,-0.999999999999998,-0.399903088302660,3.66373598126302e-15,0.0600499921067860,-0.221231742082476,-0.707106781186552,-1.17557050458495,-1.40504701603470,-1.26007351067010,-0.744219717332698,1.16403343982657e-14,0.744219717332718,1.26007351067010,1.40504701603470,1.17557050458496,0.707106781186561,0.221231742082482,-0.0600499921067840,-1.99840144432528e-15,0.399903088302663,1.00000000000000,1.57547359288762,1.90211303259031,1.84206304048353,1.39680224666743,0.707106781186558,5.44009282066327e-15,-0.497066016555606,-0.642039521920206,-0.431350787252239,6.61680659921524e-15,0.431350787252249,0.642039521920207,0.497066016555612,5.55111512312578e-15,-0.707106781186545,-1.39680224666742,-1.84206304048352,-1.90211303259031,-1.57547359288760,-0.999999999999984,-0.399903088302648,-2.10942374678780e-15,0.0600499921067861,-0.221231742082475,-0.707106781186552,-1.17557050458493,-1.40504701603470,-1.26007351067011,-0.744219717332714,-7.34788079488412e-15,0.744219717332702,1.26007351067010,1.40504701603470,1.17557050458494,0.707106781186538,0.221231742082483,-0.0600499921067839,-2.33146835171283e-15,0.399903088302663,1.00000000000000,1.57547359288761,1.90211303259031,1.84206304048352,1.39680224666741,0.707106781186559}; + q15_t q15_state[256] = {0}; + q15_t dct4_testinput_q15_50hz_200Hz[256], dct4_testinput_q15_50hz_200Hz_ref[256]; diff --git a/examples/dsp/TransformFunction_dct4/dct4.c b/examples/dsp/TransformFunction_dct4/dct4.c new file mode 100644 index 00000000..ad25b595 --- /dev/null +++ b/examples/dsp/TransformFunction_dct4/dct4.c @@ -0,0 +1,80 @@ +#include "ref.h" + +void ref_dct4_f32(const riscv_dct4_instance_f32 *S, float32_t *pState, + float32_t *pInlineBuffer) +{ + uint32_t n, k; + float32_t sum; + float32_t pi_by_N = 3.14159265358979f / (float32_t)S->N; + float32_t tmp; + float32_t normalize = sqrtf(2.0f / (float32_t)S->N); + + for (k = 0; k < S->N; k++) { + sum = 0.0f; + tmp = ((float32_t)k + 0.5f) * pi_by_N; + for (n = 0; n < S->N; n++) { + sum += pInlineBuffer[n] * cosf(tmp * ((float32_t)n + 0.5f)); + } + scratchArray[k] = normalize * sum; + } + + for (k = 0; k < S->N; k++) { + pInlineBuffer[k] = scratchArray[k]; + } +} + +void ref_dct4_q31(const riscv_dct4_instance_q31 *S, q31_t *pState, + q31_t *pInlineBuffer) +{ + riscv_dct4_instance_f32 SS; + // float32_t *fSrc = (float32_t*)pInlineBuffer; + float32_t fSrc[S->N]; + riscv_q31_to_float(pInlineBuffer, fSrc, S->N); + uint32_t i; + + SS.N = S->N; + + for (i = 0; i < S->N; i++) { + // read the q31 data, cast to float, scale down for float + fSrc[i] = (float32_t)pInlineBuffer[i] / 2147483648.0f; + } + + ref_dct4_f32(&SS, (float32_t *)0, fSrc); + + for (i = 0; i < S->N; i++) { + fSrc[i] = fSrc[i] * 2147483648.0f / (float32_t)S->N; + fSrc[i] += (fSrc[i] > 0) ? 0.5f : -0.5f; + pInlineBuffer[i] = (q31_t)fSrc[i]; + } +} + +void ref_dct4_q15(const riscv_dct4_instance_q15 *S, q15_t *pState, + q15_t *pInlineBuffer) +{ + riscv_dct4_instance_f32 SS; + // float32_t *fSrc = (float32_t*)pInlineBuffer; + float32_t fSrc[S->N]; + riscv_q15_to_float(pInlineBuffer, fSrc, S->N); + uint32_t i; + + SS.N = S->N; + + for (i = 0; i < S->N; i++) { + // read the q15 data, cast to float, scale down for float, place in + // temporary buffer + scratchArray[i] = (float32_t)pInlineBuffer[i] / 32768.0f; + } + + for (i = 0; i < S->N; i++) { + // copy from temp buffer to final buffer + fSrc[i] = scratchArray[i]; + } + + ref_dct4_f32(&SS, (float32_t *)0, fSrc); + + for (i = 0; i < S->N; i++) { + fSrc[i] = fSrc[i] * 32768.0f / (float32_t)S->N; + fSrc[i] += (fSrc[i] > 0) ? 0.5f : -0.5f; + pInlineBuffer[i] = (q15_t)fSrc[i]; + } +} diff --git a/examples/dsp/TransformFunction_dct4/main.c b/examples/dsp/TransformFunction_dct4/main.c new file mode 100644 index 00000000..4ea5c4bc --- /dev/null +++ b/examples/dsp/TransformFunction_dct4/main.c @@ -0,0 +1,147 @@ +// +// Created by lujun on 19-6-28. +// +// This contains SIN_COS , clarke, inv_clarke, park, inv_park and pid +// each one has it's own function. +// All function can be found in main function. +// If you don't want to use it, then comment it. +#include "riscv_common_tables.h" +#include "riscv_const_structs.h" +#include "riscv_math.h" +#include "array.h" +#include +#include "../common.h" + +#include "../HelperFunctions/math_helper.c" +#include "../HelperFunctions/ref_helper.c" + +#include +#define DELTAF32 (0.05f) +#define DELTAQ31 (63) +#define DELTAQ15 (1) +#define DELTAQ7 (1) +int test_flag_error = 0; + +uint32_t fftSize = 1024; +uint32_t ifftFlag = 0; +uint32_t doBitReverse = 1; + +static int DSP_dct4_f32(void) +{ + uint16_t i; + /* clang-format off */ + fftSize = 128; + riscv_cfft_radix4_instance_f32 S; + uint8_t ifftFlag = 0, doBitReverse = 1; + /* clang-format on */ + riscv_cfft_radix4_init_f32(&S, 64, ifftFlag, doBitReverse); + riscv_rfft_instance_f32 SS; + ifftFlag = 0; + doBitReverse = 1; + riscv_rfft_init_f32(&SS, &S, fftSize, ifftFlag, doBitReverse); + riscv_dct4_instance_f32 SSS = {128, 64, 0.125, Weights_128, cos_factors_128, + &SS, &S}; + BENCH_START(riscv_dct4_f32); + riscv_dct4_f32(&SSS, f32_state, dct4_testinput_f32_50hz_200Hz); + BENCH_END(riscv_dct4_f32); + // ref_dct4_f32(&SSS, f32_state, dct4_testinput_f32_50hz_200Hz_ref); + float32_t resault, resault_ref; + uint32_t index, index_ref = 5; + riscv_max_f32(dct4_testinput_f32_50hz_200Hz, 128, &resault, &index); + // riscv_max_f32(dct4_testinput_f32_50hz_200Hz_ref,128,&resault_ref,&index_ref); + if (index != index_ref) { + BENCH_ERROR(riscv_dct4_f32); + printf("expect: %d, actual: %d\n", index_ref, index); + test_flag_error = 1; + } + BENCH_STATUS(riscv_dct4_f32); +} +static int DSP_dct4_q31(void) +{ + uint16_t i; + /* clang-format off */ + /* clang-format on */ + riscv_float_to_q31(dct4_testinput_f32_50hz_200Hz_q31, + dct4_testinput_q31_50hz_200Hz, 256); + riscv_float_to_q31(dct4_testinput_f32_50hz_200Hz_q31, + dct4_testinput_q31_50hz_200Hz_ref, 256); + fftSize = 128; + + riscv_cfft_radix4_instance_q31 S; + // uint8_t ifftFlag = 0, doBitReverse = 1; + // riscv_cfft_radix4_init_q31(&S, 64, ifftFlag, doBitReverse); + + riscv_rfft_instance_q31 SS; + // riscv_rfft_init_q31(&SS, fftSize, ifftFlag, doBitReverse); + riscv_dct4_instance_q31 SSS; + // riscv_dct4_instance_q31 SSS = {128, 64, 0x10000000, WeightsQ31_128, + // cos_factorsQ31_128, &SS, &S}; + riscv_dct4_init_q31(&SSS, &SS, &S, 128, 64, 0x10000000); + BENCH_START(riscv_dct4_q31); + riscv_dct4_q31(&SSS, q31_state, dct4_testinput_q31_50hz_200Hz); + BENCH_END(riscv_dct4_q31); + // riscv_dct4_init_q31(&SSS,&SS,&S,128,64,0x10000000); + // ref_dct4_q31(&SSS, q31_state, dct4_testinput_q31_50hz_200Hz_ref); + q31_t resault, resault_ref; + uint32_t index, index_ref = 5; + riscv_shift_q31(dct4_testinput_q31_50hz_200Hz, 7, + dct4_testinput_q31_50hz_200Hz, fftSize); + // riscv_shift_q31(dct4_testinput_q31_50hz_200Hz_ref,9,dct4_testinput_q31_50hz_200Hz_ref,fftSize); + riscv_max_q31(dct4_testinput_q31_50hz_200Hz, 128, &resault, &index); + // riscv_max_q31(dct4_testinput_q31_50hz_200Hz_ref,128,&resault_ref,&index_ref); + if (index != index_ref) { + BENCH_ERROR(riscv_dct4_q31); + printf("expect: %d, actual: %d\n", index_ref, index); + test_flag_error = 1; + } + BENCH_STATUS(riscv_dct4_q31); +} +static int DSP_dct4_q15(void) +{ + uint16_t i; + /* clang-format off */ + /* clang-format on */ + riscv_float_to_q15(dct4_testinput_f32_50hz_200Hz_q15, + dct4_testinput_q15_50hz_200Hz, 256); + riscv_float_to_q15(dct4_testinput_f32_50hz_200Hz_q15, + dct4_testinput_q15_50hz_200Hz_ref, 256); + fftSize = 128; + + riscv_cfft_radix4_instance_q15 S; + riscv_rfft_instance_q15 SS; + riscv_dct4_instance_q15 SSS; + riscv_dct4_init_q15(&SSS, &SS, &S, fftSize, fftSize / 2, 0x1000); + BENCH_START(riscv_dct4_q15); + riscv_dct4_q15(&SSS, q15_state, dct4_testinput_q15_50hz_200Hz); + BENCH_END(riscv_dct4_q15); + // riscv_dct4_init_q15(&SSS,&SS,&S,fftSize,fftSize/2,0x1000); + // ref_dct4_q15(&SSS, q15_state, dct4_testinput_q15_50hz_200Hz_ref); + q15_t resault, resault_ref; + uint32_t index, index_ref = 5; + riscv_shift_q15(dct4_testinput_q15_50hz_200Hz, 6, + dct4_testinput_q15_50hz_200Hz, fftSize); + riscv_max_q15(dct4_testinput_q15_50hz_200Hz, fftSize, &resault, &index); + // riscv_shift_q15(dct4_testinput_q15_50hz_200Hz_ref,6,dct4_testinput_q15_50hz_200Hz_ref,fftSize); + // riscv_max_q15(dct4_testinput_q15_50hz_200Hz_ref,fftSize,&resault,&index_ref); + if (index != index_ref) { + BENCH_ERROR(riscv_dct4_q15); + printf("expect: %d, actual: %d\n", index_ref, index); + test_flag_error = 1; + } + BENCH_STATUS(riscv_dct4_q15); +} +int main() +{ + BENCH_INIT; + DSP_dct4_f32(); + DSP_dct4_q31(); + DSP_dct4_q15(); + BENCH_FINISH; + if (test_flag_error) { + printf("test error apprears, please recheck.\n"); + return 1; + } else { + printf("all test are passed. Well done!\n"); + } + return 0; +} diff --git a/examples/dsp/TransformFunction_rfft/CMakeLists.txt b/examples/dsp/TransformFunction_rfft/CMakeLists.txt new file mode 100644 index 00000000..b8ab380d --- /dev/null +++ b/examples/dsp/TransformFunction_rfft/CMakeLists.txt @@ -0,0 +1,5 @@ +set(TARGET_REQUIRED_PRIVATE_INCLUDE ${CMAKE_CURRENT_SOURCE_DIR} ${CMAKE_CURRENT_SOURCE_DIR}/..) +set(TARGET_REQUIRED_LIBS nmsis) +list(APPEND TARGET_REQUIRED_SRCS rfft.c cfft.c) +set(mains main.c) +generate_bin() \ No newline at end of file diff --git a/examples/dsp/TransformFunction_rfft/array.h b/examples/dsp/TransformFunction_rfft/array.h new file mode 100644 index 00000000..97228161 --- /dev/null +++ b/examples/dsp/TransformFunction_rfft/array.h @@ -0,0 +1,14 @@ +// Array for TransformFunctions rfft +#define ARRAY_SIZE 100 +//float32_t + float32_t rfft_testinput_f32_50hz_200Hz[1024] = { + 0,0.744219717332704,1.26007351067010,1.40504701603470,1.17557050458495,0.707106781186548,0.221231742082474,-0.0600499921067857,-1.11022302462516e-16,0.399903088302664,1.00000000000000,1.57547359288761,1.90211303259031,1.84206304048352,1.39680224666742,0.707106781186548,4.44089209850063e-16,-0.497066016555608,-0.642039521920206,-0.431350787252243,-3.67394039744206e-16,0.431350787252243,0.642039521920206,0.497066016555607,-1.22124532708767e-15,-0.707106781186549,-1.39680224666742,-1.84206304048352,-1.90211303259031,-1.57547359288761,-1.00000000000000,-0.399903088302665,-3.33066907387547e-16,0.0600499921067852,-0.221231742082476,-0.707106781186550,-1.17557050458495,-1.40504701603470,-1.26007351067010,-0.744219717332705,-1.22464679914735e-15,0.744219717332707,1.26007351067010,1.40504701603470,1.17557050458495,0.707106781186549,0.221231742082475,-0.0600499921067854,8.88178419700125e-16,0.399903088302667,1.00000000000000,1.57547359288761,1.90211303259031,1.84206304048352,1.39680224666742,0.707106781186545,1.33226762955019e-15,-0.497066016555608,-0.642039521920206,-0.431350787252245,-1.10218211923262e-15,0.431350787252243,0.642039521920206,0.497066016555606,1.55431223447522e-15,-0.707106781186550,-1.39680224666743,-1.84206304048352,-1.90211303259031,-1.57547359288761,-0.999999999999995,-0.399903088302669,-7.77156117237610e-16,0.0600499921067867,-0.221231742082473,-0.707106781186549,-1.17557050458495,-1.40504701603470,-1.26007351067010,-0.744219717332702,-2.44929359829471e-15,0.744219717332706,1.26007351067010,1.40504701603470,1.17557050458494,0.707106781186546,0.221231742082476,-0.0600499921067846,-7.77156117237610e-16,0.399903088302660,0.999999999999998,1.57547359288761,1.90211303259031,1.84206304048352,1.39680224666742,0.707106781186546,-4.88498130835069e-15,-0.497066016555607,-0.642039521920206,-0.431350787252242,3.49210031947972e-15,0.431350787252243,0.642039521920206,0.497066016555610,2.55351295663786e-15,-0.707106781186549,-1.39680224666742,-1.84206304048352,-1.90211303259031,-1.57547359288761,-0.999999999999996,-0.399903088302658,-9.99200722162641e-16,0.0600499921067855,-0.221231742082477,-0.707106781186554,-1.17557050458494,-1.40504701603470,-1.26007351067011,-0.744219717332711,-3.67394039744206e-15,0.744219717332705,1.26007351067010,1.40504701603470,1.17557050458495,0.707106781186547,0.221231742082472,-0.0600499921067872,-1.22124532708767e-15,0.399903088302665,1.00000000000000,1.57547359288762,1.90211303259031,1.84206304048352,1.39680224666742,0.707106781186539,-1.09912079437891e-14,-0.497066016555607,-0.642039521920206,-0.431350787252238,8.08638275819206e-15,0.431350787252234,0.642039521920205,0.497066016555611,3.55271367880050e-15,-0.707106781186548,-1.39680224666741,-1.84206304048352,-1.90211303259031,-1.57547359288761,-0.999999999999997,-0.399903088302671,-1.44328993201270e-15,0.0600499921067857,-0.221231742082476,-0.707106781186553,-1.17557050458494,-1.40504701603470,-1.26007351067010,-0.744219717332697,-4.89858719658941e-15,0.744219717332704,1.26007351067010,1.40504701603470,1.17557050458494,0.707106781186548,0.221231742082472,-0.0600499921067871,3.88578058618805e-15,0.399903088302676,1.00000000000000,1.57547359288762,1.90211303259031,1.84206304048352,1.39680224666743,0.707106781186557,4.44089209850063e-15,-0.497066016555606,-0.642039521920207,-0.431350787252247,-3.30654635769785e-15,0.431350787252242,0.642039521920206,0.497066016555611,4.55191440096314e-15,-0.707106781186546,-1.39680224666742,-1.84206304048352,-1.90211303259031,-1.57547359288761,-0.999999999999998,-0.399903088302660,3.66373598126302e-15,0.0600499921067860,-0.221231742082476,-0.707106781186552,-1.17557050458495,-1.40504701603470,-1.26007351067010,-0.744219717332698,1.16403343982657e-14,0.744219717332718,1.26007351067010,1.40504701603470,1.17557050458496,0.707106781186561,0.221231742082482,-0.0600499921067840,-1.99840144432528e-15,0.399903088302663,1.00000000000000,1.57547359288762,1.90211303259031,1.84206304048353,1.39680224666743,0.707106781186558,5.44009282066327e-15,-0.497066016555606,-0.642039521920206,-0.431350787252239,6.61680659921524e-15,0.431350787252249,0.642039521920207,0.497066016555612,5.55111512312578e-15,-0.707106781186545,-1.39680224666742,-1.84206304048352,-1.90211303259031,-1.57547359288760,-0.999999999999984,-0.399903088302648,-2.10942374678780e-15,0.0600499921067861,-0.221231742082475,-0.707106781186552,-1.17557050458493,-1.40504701603470,-1.26007351067011,-0.744219717332714,-7.34788079488412e-15,0.744219717332702,1.26007351067010,1.40504701603470,1.17557050458494,0.707106781186538,0.221231742082483,-0.0600499921067839,-2.33146835171283e-15,0.399903088302663,1.00000000000000,1.57547359288761,1.90211303259031,1.84206304048352,1.39680224666741,0.707106781186559,6.32827124036339e-15,-0.497066016555605,-0.642039521920206,-0.431350787252240,5.88201851972683e-15,0.431350787252249,0.642039521920207,0.497066016555597,-2.22044604925031e-14,-0.707106781186544,-1.39680224666742,-1.84206304048352,-1.90211303259031,-1.57547359288760,-0.999999999999985,-0.399903088302649,8.43769498715119e-15,0.0600499921067808,-0.221231742082475,-0.707106781186551,-1.17557050458495,-1.40504701603470,-1.26007351067009,-0.744219717332685,2.69546091939735e-14,0.744219717332731,1.26007351067009,1.40504701603470,1.17557050458496,0.707106781186562,0.221231742082484,-0.0600499921067836,-2.77555756156289e-15,0.399903088302662,1,1.57547359288759,1.90211303259030,1.84206304048353,1.39680224666743,0.707106781186560,7.32747196252603e-15,-0.497066016555605,-0.642039521920206,-0.431350787252240,5.14723044023841e-15,0.431350787252232,0.642039521920205,0.497066016555613,7.54951656745106e-15,-0.707106781186543,-1.39680224666742,-1.84206304048352,-1.90211303259031,-1.57547359288760,-0.999999999999986,-0.399903088302674,-2.99760216648792e-15,0.0600499921067865,-0.221231742082474,-0.707106781186550,-1.17557050458495,-1.40504701603470,-1.26007351067009,-0.744219717332686,-9.79717439317883e-15,0.744219717332699,1.26007351067010,1.40504701603470,1.17557050458494,0.707106781186540,0.221231742082465,-0.0600499921067890,7.88258347483861e-15,0.399903088302685,0.999999999999999,1.57547359288761,1.90211303259031,1.84206304048352,1.39680224666741,0.707106781186528,-2.04281036531029e-14,-0.497066016555619,-0.642039521920204,-0.431350787252241,4.41244236075000e-15,0.431350787252248,0.642039521920207,0.497066016555598,8.43769498715119e-15,-0.707106781186542,-1.39680224666742,-1.84206304048351,-1.90211303259031,-1.57547359288763,-1.00000000000002,-0.399903088302675,-3.33066907387547e-15,0.0600499921067867,-0.221231742082473,-0.707106781186549,-1.17557050458493,-1.40504701603470,-1.26007351067011,-0.744219717332717,-1.10218211923262e-14,0.744219717332698,1.26007351067010,1.40504701603470,1.17557050458494,0.707106781186540,0.221231742082485,-0.0600499921067832,-3.44169137633799e-15,0.399903088302660,0.999999999999998,1.57547359288761,1.90211303259031,1.84206304048352,1.39680224666741,0.707106781186563,9.32587340685132e-15,-0.497066016555604,-0.642039521920206,-0.431350787252242,3.67765428126159e-15,0.431350787252247,0.642039521920207,0.497066016555599,-1.93178806284777e-14,-0.707106781186541,-1.39680224666742,-1.84206304048352,-1.90211303259031,-1.57547359288760,-0.999999999999988,-0.399903088302652,7.32747196252603e-15,0.0600499921067813,-0.221231742082492,-0.707106781186548,-1.17557050458495,-1.40504701603470,-1.26007351067009,-0.744219717332688,2.32806687965315e-14,0.744219717332727,1.26007351067012,1.40504701603470,1.17557050458494,0.707106781186541,0.221231742082467,-0.0600499921067831,-1.47659662275146e-14,0.399903088302659,0.999999999999969,1.57547359288761,1.90211303259030,1.84206304048352,1.39680224666744,0.707106781186530,1.02140518265514e-14,-0.497066016555588,-0.642039521920206,-0.431350787252258,2.94286620177318e-15,0.431350787252230,0.642039521920207,0.497066016555614,-1.83186799063151e-14,-0.707106781186540,-1.39680224666739,-1.84206304048352,-1.90211303259031,-1.57547359288761,-1.00000000000002,-0.399903088302653,-4.10782519111308e-15,0.0600499921067815,-0.221231742082472,-0.707106781186571,-1.17557050458495,-1.40504701603470,-1.26007351067010,-0.744219717332719,2.20560219973841e-14,0.744219717332696,1.26007351067011,1.40504701603470,1.17557050458493,0.707106781186542,0.221231742082486,-0.0600499921067884,-4.21884749357560e-15,0.399903088302682,0.999999999999996,1.57547359288763,1.90211303259031,1.84206304048351,1.39680224666741,0.707106781186565,-1.75415237890775e-14,-0.497066016555603,-0.642039521920204,-0.431350787252243,2.35243601950878e-14,0.431350787252246,0.642039521920209,0.497066016555600,1.15463194561016e-14,-0.707106781186572,-1.39680224666742,-1.84206304048353,-1.90211303259031,-1.57547359288763,-0.999999999999990,-0.399903088302677,-1.54321000422897e-14,0.0600499921067873,-0.221231742082452,-0.707106781186547,-1.17557050458493,-1.40504701603470,-1.26007351067011,-0.744219717332690,-1.46957615897682e-14,0.744219717332665,1.26007351067010,1.40504701603470,1.17557050458495,0.707106781186566,0.221231742082468,-0.0600499921067826,6.32827124036339e-15,0.399903088302658,1.00000000000002,1.57547359288761,1.90211303259030,1.84206304048352,1.39680224666744,0.707106781186533,1.23234755733392e-14,-0.497066016555617,-0.642039521920207,-0.431350787252227,1.47329004279635e-15,0.431350787252229,0.642039521920207,0.497066016555615,-1.62092561595273e-14,-0.707106781186537,-1.39680224666744,-1.84206304048352,-1.90211303259030,-1.57547359288761,-1.00000000000002,-0.399903088302654}; + +//q31_t + q31_t rfft_testinput_q31_50hz_200Hz[1024] = {0}, rfft_testinput_q31_50hz_200Hz_ref[1024] = {0}; + q31_t q31_testOutput[1024], q31_testOutput_ref[1024]; + +//q15_t + q15_t rfft_testinput_q15_50hz_200Hz[1024] = {0}, rfft_testinput_q15_50hz_200Hz_ref[1024] = {0}; + q15_t q15_testOutput[1024], q15_testOutput_ref[1024]; + diff --git a/examples/dsp/TransformFunction_rfft/cfft.c b/examples/dsp/TransformFunction_rfft/cfft.c new file mode 100644 index 00000000..98c71c22 --- /dev/null +++ b/examples/dsp/TransformFunction_rfft/cfft.c @@ -0,0 +1,618 @@ +#include "riscv_const_structs.h" +#include "ref.h" + +void ref_cfft_f32(const riscv_cfft_instance_f32 *S, float32_t *p1, + uint8_t ifftFlag, uint8_t bitReverseFlag) +{ + int n, mmax, m, j, istep, i; + float32_t wtemp, wr, wpr, wpi, wi, theta; + float32_t tempr, tempi; + float32_t *data = p1; + uint32_t N = S->fftLen; + int32_t dir = (ifftFlag) ? -1 : 1; + + // decrement pointer since the original version used fortran style indexing. + data--; + + n = N << 1; + j = 1; + for (i = 1; i < n; i += 2) { + if (j > i) { + tempr = data[j]; + data[j] = data[i]; + data[i] = tempr; + tempr = data[j + 1]; + data[j + 1] = data[i + 1]; + data[i + 1] = tempr; + } + m = n >> 1; + while (m >= 2 && j > m) { + j -= m; + m >>= 1; + } + j += m; + } + mmax = 2; + while (n > mmax) { + istep = 2 * mmax; + theta = -6.283185307179586f / (dir * mmax); + wtemp = sinf(0.5f * theta); + wpr = -2.0f * wtemp * wtemp; + wpi = sinf(theta); + wr = 1.0f; + wi = 0.0f; + for (m = 1; m < mmax; m += 2) { + for (i = m; i <= n; i += istep) { + j = i + mmax; + tempr = wr * data[j] - wi * data[j + 1]; + tempi = wr * data[j + 1] + wi * data[j]; + data[j] = data[i] - tempr; + data[j + 1] = data[i + 1] - tempi; + data[i] += tempr; + data[i + 1] += tempi; + } + wr = (wtemp = wr) * wpr - wi * wpi + wr; + wi = wi * wpr + wtemp * wpi + wi; + } + mmax = istep; + } + + // Inverse transform is scaled by 1/N + if (ifftFlag) { + data++; + for (i = 0; i < 2 * N; i++) { + data[i] /= N; + } + } +} + +void ref_cfft_q31(const riscv_cfft_instance_q31 *S, q31_t *p1, uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + uint32_t i; + // float32_t *fSrc = (float32_t*)p1; + float32_t fSrc[S->fftLen * 2]; + riscv_q31_to_float(p1, fSrc, S->fftLen * 2); + for (i = 0; i < S->fftLen * 2; i++) { + // read the q31 data, cast to float, scale down for float + fSrc[i] = (float32_t)p1[i] / 2147483648.0f; + } + + switch (S->fftLen) { + case 16: + ref_cfft_f32(&riscv_cfft_sR_f32_len16, fSrc, ifftFlag, + bitReverseFlag); + break; + + case 32: + ref_cfft_f32(&riscv_cfft_sR_f32_len32, fSrc, ifftFlag, + bitReverseFlag); + break; + + case 64: + ref_cfft_f32(&riscv_cfft_sR_f32_len64, fSrc, ifftFlag, + bitReverseFlag); + break; + + case 128: + ref_cfft_f32(&riscv_cfft_sR_f32_len128, fSrc, ifftFlag, + bitReverseFlag); + break; + + case 256: + ref_cfft_f32(&riscv_cfft_sR_f32_len256, fSrc, ifftFlag, + bitReverseFlag); + break; + + case 512: + ref_cfft_f32(&riscv_cfft_sR_f32_len512, fSrc, ifftFlag, + bitReverseFlag); + break; + + case 1024: + ref_cfft_f32(&riscv_cfft_sR_f32_len1024, fSrc, ifftFlag, + bitReverseFlag); + break; + + case 2048: + ref_cfft_f32(&riscv_cfft_sR_f32_len2048, fSrc, ifftFlag, + bitReverseFlag); + break; + + case 4096: + ref_cfft_f32(&riscv_cfft_sR_f32_len4096, fSrc, ifftFlag, + bitReverseFlag); + break; + } + + if (ifftFlag) { + for (i = 0; i < S->fftLen * 2; i++) { + // read the float data, scale up for q31, cast to q31 + p1[i] = (q31_t)(fSrc[i] * 2147483648.0f); + } + } else { + for (i = 0; i < S->fftLen * 2; i++) { + // read the float data, scale up for q31, cast to q31 + p1[i] = (q31_t)(fSrc[i] * 2147483648.0f / (float32_t)S->fftLen); + } + } +} + +void ref_cfft_q15(const riscv_cfft_instance_q15 *S, q15_t *pSrc, uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + uint32_t i; + // float32_t *fSrc = (float32_t*)pSrc; + float32_t fSrc[S->fftLen * 2]; + riscv_q15_to_float(pSrc, fSrc, S->fftLen * 2); + + for (i = 0; i < S->fftLen * 2; i++) { + // read the q15 data, cast to float, scale down for float, place in + // temporary buffer + scratchArray[i] = (float32_t)pSrc[i] / 32768.0f; + } + + for (i = 0; i < S->fftLen * 2; i++) { + // copy from temp buffer to final buffer + fSrc[i] = scratchArray[i]; + } + + switch (S->fftLen) { + case 16: + ref_cfft_f32(&riscv_cfft_sR_f32_len16, fSrc, ifftFlag, + bitReverseFlag); + break; + + case 32: + ref_cfft_f32(&riscv_cfft_sR_f32_len32, fSrc, ifftFlag, + bitReverseFlag); + break; + + case 64: + ref_cfft_f32(&riscv_cfft_sR_f32_len64, fSrc, ifftFlag, + bitReverseFlag); + break; + + case 128: + ref_cfft_f32(&riscv_cfft_sR_f32_len128, fSrc, ifftFlag, + bitReverseFlag); + break; + + case 256: + ref_cfft_f32(&riscv_cfft_sR_f32_len256, fSrc, ifftFlag, + bitReverseFlag); + break; + + case 512: + ref_cfft_f32(&riscv_cfft_sR_f32_len512, fSrc, ifftFlag, + bitReverseFlag); + break; + + case 1024: + ref_cfft_f32(&riscv_cfft_sR_f32_len1024, fSrc, ifftFlag, + bitReverseFlag); + break; + + case 2048: + ref_cfft_f32(&riscv_cfft_sR_f32_len2048, fSrc, ifftFlag, + bitReverseFlag); + break; + + case 4096: + ref_cfft_f32(&riscv_cfft_sR_f32_len4096, fSrc, ifftFlag, + bitReverseFlag); + break; + } + + if (ifftFlag) { + for (i = 0; i < S->fftLen * 2; i++) { + // read the float data, scale up for q15, cast to q15 + pSrc[i] = (q15_t)(fSrc[i] * 32768.0f); + } + } else { + for (i = 0; i < S->fftLen * 2; i++) { + // read the float data, scale up for q15, cast to q15 + pSrc[i] = (q15_t)(fSrc[i] * 32768.0f / (float32_t)S->fftLen); + } + } +} + +void ref_cfft_radix2_f32(const riscv_cfft_radix2_instance_f32 *S, float32_t *pSrc) +{ + switch (S->fftLen) { + case 16: + ref_cfft_f32(&riscv_cfft_sR_f32_len16, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 32: + ref_cfft_f32(&riscv_cfft_sR_f32_len32, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 64: + ref_cfft_f32(&riscv_cfft_sR_f32_len64, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 128: + ref_cfft_f32(&riscv_cfft_sR_f32_len128, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 256: + ref_cfft_f32(&riscv_cfft_sR_f32_len256, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 512: + ref_cfft_f32(&riscv_cfft_sR_f32_len512, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 1024: + ref_cfft_f32(&riscv_cfft_sR_f32_len1024, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 2048: + ref_cfft_f32(&riscv_cfft_sR_f32_len2048, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 4096: + ref_cfft_f32(&riscv_cfft_sR_f32_len4096, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + } +} + +void ref_cfft_radix2_q31(const riscv_cfft_radix2_instance_q31 *S, q31_t *pSrc) +{ + uint32_t i; + // float32_t *fSrc = (float32_t*)pSrc; + float32_t fSrc[S->fftLen * 2]; + riscv_q31_to_float(pSrc, fSrc, S->fftLen * 2); + + for (i = 0; i < S->fftLen * 2; i++) { + // read the q31 data, cast to float, scale down for float + fSrc[i] = (float32_t)pSrc[i] / 2147483648.0f; + } + + switch (S->fftLen) { + case 16: + ref_cfft_f32(&riscv_cfft_sR_f32_len16, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 32: + ref_cfft_f32(&riscv_cfft_sR_f32_len32, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 64: + ref_cfft_f32(&riscv_cfft_sR_f32_len64, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 128: + ref_cfft_f32(&riscv_cfft_sR_f32_len128, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 256: + ref_cfft_f32(&riscv_cfft_sR_f32_len256, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 512: + ref_cfft_f32(&riscv_cfft_sR_f32_len512, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 1024: + ref_cfft_f32(&riscv_cfft_sR_f32_len1024, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 2048: + ref_cfft_f32(&riscv_cfft_sR_f32_len2048, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 4096: + ref_cfft_f32(&riscv_cfft_sR_f32_len4096, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + } + + if (S->ifftFlag) { + for (i = 0; i < S->fftLen * 2; i++) { + // read the float data, scale up for q31, cast to q31 + pSrc[i] = (q31_t)(fSrc[i] * 2147483648.0f); + } + } else { + for (i = 0; i < S->fftLen * 2; i++) { + // read the float data, scale up for q31, cast to q31 + pSrc[i] = (q31_t)(fSrc[i] * 2147483648.0f / (float32_t)S->fftLen); + } + } +} + +void ref_cfft_radix2_q15(const riscv_cfft_radix2_instance_q15 *S, q15_t *pSrc) +{ + uint32_t i; + // float32_t *fSrc = (float32_t*)pSrc; + float32_t fSrc[S->fftLen * 2]; + riscv_q15_to_float(pSrc, fSrc, S->fftLen * 2); + + for (i = 0; i < S->fftLen * 2; i++) { + // read the q15 data, cast to float, scale down for float, place in + // temporary buffer + scratchArray[i] = (float32_t)pSrc[i] / 32768.0f; + } + + for (i = 0; i < S->fftLen * 2; i++) { + // copy from temp buffer to final buffer + fSrc[i] = scratchArray[i]; + } + + switch (S->fftLen) { + case 16: + ref_cfft_f32(&riscv_cfft_sR_f32_len16, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 32: + ref_cfft_f32(&riscv_cfft_sR_f32_len32, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 64: + ref_cfft_f32(&riscv_cfft_sR_f32_len64, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 128: + ref_cfft_f32(&riscv_cfft_sR_f32_len128, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 256: + ref_cfft_f32(&riscv_cfft_sR_f32_len256, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 512: + ref_cfft_f32(&riscv_cfft_sR_f32_len512, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 1024: + ref_cfft_f32(&riscv_cfft_sR_f32_len1024, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 2048: + ref_cfft_f32(&riscv_cfft_sR_f32_len2048, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 4096: + ref_cfft_f32(&riscv_cfft_sR_f32_len4096, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + } + + if (S->ifftFlag) { + for (i = 0; i < S->fftLen * 2; i++) { + // read the float data, scale up for q15, cast to q15 + pSrc[i] = (q15_t)(fSrc[i] * 32768.0f); + } + } else { + for (i = 0; i < S->fftLen * 2; i++) { + // read the float data, scale up for q15, cast to q15 + pSrc[i] = (q15_t)(fSrc[i] * 32768.0f / (float32_t)S->fftLen); + } + } +} + +void ref_cfft_radix4_f32(const riscv_cfft_radix4_instance_f32 *S, float32_t *pSrc) +{ + switch (S->fftLen) { + case 16: + ref_cfft_f32(&riscv_cfft_sR_f32_len16, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 32: + ref_cfft_f32(&riscv_cfft_sR_f32_len32, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 64: + ref_cfft_f32(&riscv_cfft_sR_f32_len64, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 128: + ref_cfft_f32(&riscv_cfft_sR_f32_len128, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 256: + ref_cfft_f32(&riscv_cfft_sR_f32_len256, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 512: + ref_cfft_f32(&riscv_cfft_sR_f32_len512, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 1024: + ref_cfft_f32(&riscv_cfft_sR_f32_len1024, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 2048: + ref_cfft_f32(&riscv_cfft_sR_f32_len2048, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 4096: + ref_cfft_f32(&riscv_cfft_sR_f32_len4096, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + } +} + +void ref_cfft_radix4_q31(const riscv_cfft_radix4_instance_q31 *S, q31_t *pSrc) +{ + uint32_t i; + // float32_t *fSrc = (float32_t*)pSrc; + float32_t fSrc[S->fftLen * 2]; + riscv_q31_to_float(pSrc, fSrc, S->fftLen * 2); + + for (i = 0; i < S->fftLen * 2; i++) { + // read the q31 data, cast to float, scale down for float + fSrc[i] = (float32_t)pSrc[i] / 2147483648.0f; + } + + switch (S->fftLen) { + case 16: + ref_cfft_f32(&riscv_cfft_sR_f32_len16, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 32: + ref_cfft_f32(&riscv_cfft_sR_f32_len32, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 64: + ref_cfft_f32(&riscv_cfft_sR_f32_len64, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 128: + ref_cfft_f32(&riscv_cfft_sR_f32_len128, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 256: + ref_cfft_f32(&riscv_cfft_sR_f32_len256, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 512: + ref_cfft_f32(&riscv_cfft_sR_f32_len512, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 1024: + ref_cfft_f32(&riscv_cfft_sR_f32_len1024, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 2048: + ref_cfft_f32(&riscv_cfft_sR_f32_len2048, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 4096: + ref_cfft_f32(&riscv_cfft_sR_f32_len4096, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + } + + if (S->ifftFlag) { + for (i = 0; i < S->fftLen * 2; i++) { + // read the float data, scale up for q31, cast to q31 + pSrc[i] = (q31_t)(fSrc[i] * 2147483648.0f); + } + } else { + for (i = 0; i < S->fftLen * 2; i++) { + // read the float data, scale up for q31, cast to q31 + pSrc[i] = (q31_t)(fSrc[i] * 2147483648.0f / (float32_t)S->fftLen); + } + } +} + +void ref_cfft_radix4_q15(const riscv_cfft_radix4_instance_q15 *S, q15_t *pSrc) +{ + uint32_t i; + // float32_t *fSrc = (float32_t*)pSrc; + float32_t fSrc[S->fftLen * 2]; + riscv_q15_to_float(pSrc, fSrc, S->fftLen * 2); + + for (i = 0; i < S->fftLen * 2; i++) { + // read the q15 data, cast to float, scale down for float, place in + // temporary buffer + scratchArray[i] = (float32_t)pSrc[i] / 32768.0f; + } + + for (i = 0; i < S->fftLen * 2; i++) { + // copy from temp buffer to final buffer + fSrc[i] = scratchArray[i]; + } + + switch (S->fftLen) { + case 16: + ref_cfft_f32(&riscv_cfft_sR_f32_len16, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 32: + ref_cfft_f32(&riscv_cfft_sR_f32_len32, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 64: + ref_cfft_f32(&riscv_cfft_sR_f32_len64, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 128: + ref_cfft_f32(&riscv_cfft_sR_f32_len128, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 256: + ref_cfft_f32(&riscv_cfft_sR_f32_len256, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 512: + ref_cfft_f32(&riscv_cfft_sR_f32_len512, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 1024: + ref_cfft_f32(&riscv_cfft_sR_f32_len1024, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 2048: + ref_cfft_f32(&riscv_cfft_sR_f32_len2048, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 4096: + ref_cfft_f32(&riscv_cfft_sR_f32_len4096, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + } + + if (S->ifftFlag) { + for (i = 0; i < S->fftLen * 2; i++) { + // read the float data, scale up for q15, cast to q15 + pSrc[i] = (q15_t)(fSrc[i] * 32768.0f); + } + } else { + for (i = 0; i < S->fftLen * 2; i++) { + // read the float data, scale up for q15, cast to q15 + pSrc[i] = (q15_t)(fSrc[i] * 32768.0f / (float32_t)S->fftLen); + } + } +} diff --git a/examples/dsp/TransformFunction_rfft/main.c b/examples/dsp/TransformFunction_rfft/main.c new file mode 100644 index 00000000..029ec2ed --- /dev/null +++ b/examples/dsp/TransformFunction_rfft/main.c @@ -0,0 +1,108 @@ +// +// Created by lujun on 19-6-28. +// +// This contains SIN_COS , clarke, inv_clarke, park, inv_park and pid +// each one has it's own function. +// All function can be found in main function. +// If you don't want to use it, then comment it. +#include "riscv_common_tables.h" +#include "riscv_const_structs.h" +#include "riscv_math.h" +#include "array.h" +#include +#include "../common.h" + +#include "../HelperFunctions/math_helper.c" +#include "../HelperFunctions/ref_helper.c" + +#include +#define DELTAF32 (0.05f) +#define DELTAQ31 (63) +#define DELTAQ15 (1) +#define DELTAQ7 (1) + +int test_flag_error = 0; + +uint32_t fftSize = 1024; +uint32_t ifftFlag = 0; +uint32_t doBitReverse = 1; + +static int DSP_rfft_q31(void) +{ + /* clang-format off */ + uint16_t i, j; + /* clang-format on */ + riscv_float_to_q31(rfft_testinput_f32_50hz_200Hz, + rfft_testinput_q31_50hz_200Hz, 1024); + riscv_float_to_q31(rfft_testinput_f32_50hz_200Hz, + rfft_testinput_q31_50hz_200Hz_ref, 1024); + riscv_rfft_instance_q31 SS; + fftSize = 512; + ifftFlag = 0; + doBitReverse = 1; + riscv_rfft_init_q31(&SS, fftSize, ifftFlag, doBitReverse); + BENCH_START(riscv_rfft_q31); + riscv_rfft_q31(&SS, rfft_testinput_q31_50hz_200Hz, q31_testOutput); + BENCH_END(riscv_rfft_q31); + riscv_rfft_init_q31(&SS, fftSize, ifftFlag, doBitReverse); + ref_rfft_q31(&SS, rfft_testinput_q31_50hz_200Hz_ref, q31_testOutput_ref); + q31_t resault, resault_ref; + uint32_t index, index_ref; + riscv_shift_q31(q31_testOutput, 8, q31_testOutput, fftSize); + riscv_shift_q31(q31_testOutput_ref, 8, q31_testOutput_ref, fftSize); + riscv_max_q31(q31_testOutput, 512, &resault, &index); + riscv_max_q31(q31_testOutput_ref, 512, &resault_ref, &index_ref); + if (index != index_ref) { + BENCH_ERROR(riscv_rfft_q31); + printf("expect: %d, actual: %d\n", index_ref, index); + test_flag_error = 1; + } + BENCH_STATUS(riscv_rfft_q31); +} +static int DSP_rfft_q15(void) +{ + /* clang-format off */ + uint16_t i, j; + /* clang-format on */ + riscv_float_to_q15(rfft_testinput_f32_50hz_200Hz, + rfft_testinput_q15_50hz_200Hz, 1024); + riscv_float_to_q15(rfft_testinput_f32_50hz_200Hz, + rfft_testinput_q15_50hz_200Hz_ref, 1024); + riscv_rfft_instance_q15 SS; + fftSize = 512; + ifftFlag = 0; + doBitReverse = 1; + riscv_rfft_init_q15(&SS, fftSize, ifftFlag, doBitReverse); + BENCH_START(riscv_rfft_q15); + riscv_rfft_q15(&SS, rfft_testinput_q15_50hz_200Hz, q15_testOutput); + BENCH_END(riscv_rfft_q15); + riscv_rfft_init_q15(&SS, fftSize, ifftFlag, doBitReverse); + ref_rfft_q15(&SS, rfft_testinput_q15_50hz_200Hz_ref, q15_testOutput_ref); + q15_t resault, resault_ref; + riscv_shift_q15(q15_testOutput, 6, q15_testOutput, fftSize); + riscv_shift_q15(q15_testOutput_ref, 6, q15_testOutput_ref, fftSize); + uint32_t index, index_ref; + riscv_max_q15(q15_testOutput, fftSize, &resault, &index); + riscv_max_q15(q15_testOutput_ref, fftSize, &resault_ref, &index_ref); + if (index != index_ref) { + BENCH_ERROR(riscv_rfft_q15); + printf("expect: %d, actual: %d\n", index_ref, index); + test_flag_error = 1; + } + BENCH_STATUS(riscv_rfft_q15); +} + +int main() +{ + BENCH_INIT; + DSP_rfft_q31(); + DSP_rfft_q15(); + BENCH_FINISH; + if (test_flag_error) { + printf("test error apprears, please recheck.\n"); + return 1; + } else { + printf("all test are passed. Well done!\n"); + } + return 0; +} diff --git a/examples/dsp/TransformFunction_rfft/rfft.c b/examples/dsp/TransformFunction_rfft/rfft.c new file mode 100644 index 00000000..90bc7e3a --- /dev/null +++ b/examples/dsp/TransformFunction_rfft/rfft.c @@ -0,0 +1,276 @@ +#include "riscv_const_structs.h" +#include "ref.h" + +void ref_rfft_f32(riscv_rfft_instance_f32 *S, float32_t *pSrc, float32_t *pDst) +{ + uint32_t i; + + if (S->ifftFlagR) { + for (i = 0; i < S->fftLenReal * 2; i++) { + pDst[i] = pSrc[i]; + } + } else { + for (i = 0; i < S->fftLenReal; i++) { + pDst[2 * i + 0] = pSrc[i]; + pDst[2 * i + 1] = 0.0f; + } + } + + switch (S->fftLenReal) { + case 128: + ref_cfft_f32(&riscv_cfft_sR_f32_len128, pDst, S->ifftFlagR, + S->bitReverseFlagR); + break; + + case 512: + ref_cfft_f32(&riscv_cfft_sR_f32_len512, pDst, S->ifftFlagR, + S->bitReverseFlagR); + break; + + case 2048: + ref_cfft_f32(&riscv_cfft_sR_f32_len2048, pDst, S->ifftFlagR, + S->bitReverseFlagR); + break; + + case 8192: + ref_cfft_f32(&ref_cfft_sR_f32_len8192, pDst, S->ifftFlagR, + S->bitReverseFlagR); + break; + } + + if (S->ifftFlagR) { + // throw away the imaginary part which should be all zeros + for (i = 0; i < S->fftLenReal; i++) { + pDst[i] = pDst[2 * i]; + } + } +} + +void ref_rfft_fast_f32(riscv_rfft_fast_instance_f32 *S, float32_t *p, + float32_t *pOut, uint8_t ifftFlag) +{ + uint32_t i, j; + + if (ifftFlag) { + for (i = 0; i < S->fftLenRFFT; i++) { + pOut[i] = p[i]; + } + // unpack first sample's complex part into middle sample's real part + pOut[S->fftLenRFFT] = pOut[1]; + pOut[S->fftLenRFFT + 1] = 0; + pOut[1] = 0; + j = 4; + for (i = S->fftLenRFFT / 2 + 1; i < S->fftLenRFFT; i++) { + pOut[2 * i + 0] = p[2 * i + 0 - j]; + pOut[2 * i + 1] = -p[2 * i + 1 - j]; + j += 4; + } + } else { + for (i = 0; i < S->fftLenRFFT; i++) { + pOut[2 * i + 0] = p[i]; + pOut[2 * i + 1] = 0.0f; + } + } + + switch (S->fftLenRFFT) { + case 32: + ref_cfft_f32(&riscv_cfft_sR_f32_len32, pOut, ifftFlag, 1); + break; + + case 64: + ref_cfft_f32(&riscv_cfft_sR_f32_len64, pOut, ifftFlag, 1); + break; + + case 128: + ref_cfft_f32(&riscv_cfft_sR_f32_len128, pOut, ifftFlag, 1); + break; + + case 256: + ref_cfft_f32(&riscv_cfft_sR_f32_len256, pOut, ifftFlag, 1); + break; + + case 512: + ref_cfft_f32(&riscv_cfft_sR_f32_len512, pOut, ifftFlag, 1); + break; + + case 1024: + ref_cfft_f32(&riscv_cfft_sR_f32_len1024, pOut, ifftFlag, 1); + break; + + case 2048: + ref_cfft_f32(&riscv_cfft_sR_f32_len2048, pOut, ifftFlag, 1); + break; + + case 4096: + ref_cfft_f32(&riscv_cfft_sR_f32_len4096, pOut, ifftFlag, 1); + break; + } + + if (ifftFlag) { + // throw away the imaginary part which should be all zeros + for (i = 0; i < S->fftLenRFFT; i++) { + pOut[i] = pOut[2 * i]; + } + } else { + // pack last sample's real part into first sample's complex part + pOut[1] = pOut[S->fftLenRFFT]; + } +} + +void ref_rfft_q31(const riscv_rfft_instance_q31 *S, q31_t *pSrc, q31_t *pDst) +{ + uint32_t i; + // float32_t *fDst = (float32_t*)pDst; + float32_t fDst[S->fftLenReal * 2]; + riscv_q31_to_float(pSrc, fDst, S->fftLenReal * 2); + + if (S->ifftFlagR) { + for (i = 0; i < S->fftLenReal * 2; i++) { + fDst[i] = (float32_t)pSrc[i] / 2147483648.0f; + } + } else { + for (i = 0; i < S->fftLenReal; i++) { + fDst[2 * i + 0] = (float32_t)pSrc[i] / 2147483648.0f; + fDst[2 * i + 1] = 0.0f; + } + } + + switch (S->fftLenReal) { + case 32: + ref_cfft_f32(&riscv_cfft_sR_f32_len32, fDst, S->ifftFlagR, + S->bitReverseFlagR); + break; + + case 64: + ref_cfft_f32(&riscv_cfft_sR_f32_len64, fDst, S->ifftFlagR, + S->bitReverseFlagR); + break; + + case 128: + ref_cfft_f32(&riscv_cfft_sR_f32_len128, fDst, S->ifftFlagR, + S->bitReverseFlagR); + break; + + case 256: + ref_cfft_f32(&riscv_cfft_sR_f32_len256, fDst, S->ifftFlagR, + S->bitReverseFlagR); + break; + + case 512: + ref_cfft_f32(&riscv_cfft_sR_f32_len512, fDst, S->ifftFlagR, + S->bitReverseFlagR); + break; + + case 1024: + ref_cfft_f32(&riscv_cfft_sR_f32_len1024, fDst, S->ifftFlagR, + S->bitReverseFlagR); + break; + + case 2048: + ref_cfft_f32(&riscv_cfft_sR_f32_len2048, fDst, S->ifftFlagR, + S->bitReverseFlagR); + break; + + case 4096: + ref_cfft_f32(&riscv_cfft_sR_f32_len4096, fDst, S->ifftFlagR, + S->bitReverseFlagR); + break; + + case 8192: + ref_cfft_f32(&ref_cfft_sR_f32_len8192, fDst, S->ifftFlagR, + S->bitReverseFlagR); + break; + } + + if (S->ifftFlagR) { + // throw away the imaginary part which should be all zeros + for (i = 0; i < S->fftLenReal; i++) { + // read the float data, scale up for q31, cast to q31 + pDst[i] = (q31_t)(fDst[2 * i] * 2147483648.0f); + } + } else { + for (i = 0; i < S->fftLenReal; i++) { + // read the float data, scale up for q31, cast to q31 + pDst[i] = + (q31_t)(fDst[i] * 2147483648.0f / (float32_t)S->fftLenReal); + } + } +} + +void ref_rfft_q15(const riscv_rfft_instance_q15 *S, q15_t *pSrc, q15_t *pDst) +{ + uint32_t i; + // float32_t *fDst = (float32_t*)pDst; + float32_t fDst[S->fftLenReal * 2]; + riscv_q15_to_float(pSrc, fDst, S->fftLenReal * 2); + + if (S->ifftFlagR) { + for (i = 0; i < S->fftLenReal * 2; i++) { + fDst[i] = (float32_t)pSrc[i] / 32768.0f; + } + } else { + for (i = 0; i < S->fftLenReal; i++) { + // read the q15 data, cast to float, scale down for float + fDst[2 * i + 0] = (float32_t)pSrc[i] / 32768.0f; + fDst[2 * i + 1] = 0.0f; + } + } + + switch (S->fftLenReal) { + case 32: + ref_cfft_f32(&riscv_cfft_sR_f32_len32, fDst, S->ifftFlagR, + S->bitReverseFlagR); + break; + + case 64: + ref_cfft_f32(&riscv_cfft_sR_f32_len64, fDst, S->ifftFlagR, + S->bitReverseFlagR); + break; + + case 128: + ref_cfft_f32(&riscv_cfft_sR_f32_len128, fDst, S->ifftFlagR, + S->bitReverseFlagR); + break; + + case 256: + ref_cfft_f32(&riscv_cfft_sR_f32_len256, fDst, S->ifftFlagR, + S->bitReverseFlagR); + break; + + case 512: + ref_cfft_f32(&riscv_cfft_sR_f32_len512, fDst, S->ifftFlagR, + S->bitReverseFlagR); + break; + + case 1024: + ref_cfft_f32(&riscv_cfft_sR_f32_len1024, fDst, S->ifftFlagR, + S->bitReverseFlagR); + break; + + case 2048: + ref_cfft_f32(&riscv_cfft_sR_f32_len2048, fDst, S->ifftFlagR, + S->bitReverseFlagR); + break; + + case 4096: + ref_cfft_f32(&riscv_cfft_sR_f32_len4096, fDst, S->ifftFlagR, + S->bitReverseFlagR); + break; + + case 8192: + ref_cfft_f32(&ref_cfft_sR_f32_len8192, fDst, S->ifftFlagR, + S->bitReverseFlagR); + break; + } + + if (S->ifftFlagR) { + // throw away the imaginary part which should be all zeros + for (i = 0; i < S->fftLenReal; i++) { + pDst[i] = (q15_t)(fDst[2 * i] * 32768.0f); + } + } else { + for (i = 0; i < S->fftLenReal; i++) { + pDst[i] = (q15_t)(fDst[i] * 32768.0f / (float32_t)S->fftLenReal); + } + } +} diff --git a/examples/dsp/TransformFunction_rfftf32/CMakeLists.txt b/examples/dsp/TransformFunction_rfftf32/CMakeLists.txt new file mode 100644 index 00000000..5b15ff10 --- /dev/null +++ b/examples/dsp/TransformFunction_rfftf32/CMakeLists.txt @@ -0,0 +1,5 @@ +set(TARGET_REQUIRED_PRIVATE_INCLUDE ${CMAKE_CURRENT_SOURCE_DIR} ${CMAKE_CURRENT_SOURCE_DIR}/..) +set(TARGET_REQUIRED_LIBS nmsis) +list(APPEND TARGET_REQUIRED_SRCS cfft.c rfft.c) +set(mains main.c) +generate_bin() \ No newline at end of file diff --git a/examples/dsp/TransformFunction_rfftf32/array.h b/examples/dsp/TransformFunction_rfftf32/array.h new file mode 100644 index 00000000..c65cc755 --- /dev/null +++ b/examples/dsp/TransformFunction_rfftf32/array.h @@ -0,0 +1,14 @@ +// Array for TransformFunctions rfftf32 +#define ARRAY_SIZE 100 +//float32_t + float32_t rfft_testinput_f32_50hz_200Hz[512] = { + 0,0.744219717332704,1.26007351067010,1.40504701603470,1.17557050458495,0.707106781186548,0.221231742082474,-0.0600499921067857,-1.11022302462516e-16,0.399903088302664,1.00000000000000,1.57547359288761,1.90211303259031,1.84206304048352,1.39680224666742,0.707106781186548,4.44089209850063e-16,-0.497066016555608,-0.642039521920206,-0.431350787252243,-3.67394039744206e-16,0.431350787252243,0.642039521920206,0.497066016555607,-1.22124532708767e-15,-0.707106781186549,-1.39680224666742,-1.84206304048352,-1.90211303259031,-1.57547359288761,-1.00000000000000,-0.399903088302665,-3.33066907387547e-16,0.0600499921067852,-0.221231742082476,-0.707106781186550,-1.17557050458495,-1.40504701603470,-1.26007351067010,-0.744219717332705,-1.22464679914735e-15,0.744219717332707,1.26007351067010,1.40504701603470,1.17557050458495,0.707106781186549,0.221231742082475,-0.0600499921067854,8.88178419700125e-16,0.399903088302667,1.00000000000000,1.57547359288761,1.90211303259031,1.84206304048352,1.39680224666742,0.707106781186545,1.33226762955019e-15,-0.497066016555608,-0.642039521920206,-0.431350787252245,-1.10218211923262e-15,0.431350787252243,0.642039521920206,0.497066016555606,1.55431223447522e-15,-0.707106781186550,-1.39680224666743,-1.84206304048352,-1.90211303259031,-1.57547359288761,-0.999999999999995,-0.399903088302669,-7.77156117237610e-16,0.0600499921067867,-0.221231742082473,-0.707106781186549,-1.17557050458495,-1.40504701603470,-1.26007351067010,-0.744219717332702,-2.44929359829471e-15,0.744219717332706,1.26007351067010,1.40504701603470,1.17557050458494,0.707106781186546,0.221231742082476,-0.0600499921067846,-7.77156117237610e-16,0.399903088302660,0.999999999999998,1.57547359288761,1.90211303259031,1.84206304048352,1.39680224666742,0.707106781186546,-4.88498130835069e-15,-0.497066016555607,-0.642039521920206,-0.431350787252242,3.49210031947972e-15,0.431350787252243,0.642039521920206,0.497066016555610,2.55351295663786e-15,-0.707106781186549,-1.39680224666742,-1.84206304048352,-1.90211303259031,-1.57547359288761,-0.999999999999996,-0.399903088302658,-9.99200722162641e-16,0.0600499921067855,-0.221231742082477,-0.707106781186554,-1.17557050458494,-1.40504701603470,-1.26007351067011,-0.744219717332711,-3.67394039744206e-15,0.744219717332705,1.26007351067010,1.40504701603470,1.17557050458495,0.707106781186547,0.221231742082472,-0.0600499921067872,-1.22124532708767e-15,0.399903088302665,1.00000000000000,1.57547359288762,1.90211303259031,1.84206304048352,1.39680224666742,0.707106781186539,-1.09912079437891e-14,-0.497066016555607,-0.642039521920206,-0.431350787252238,8.08638275819206e-15,0.431350787252234,0.642039521920205,0.497066016555611,3.55271367880050e-15,-0.707106781186548,-1.39680224666741,-1.84206304048352,-1.90211303259031,-1.57547359288761,-0.999999999999997,-0.399903088302671,-1.44328993201270e-15,0.0600499921067857,-0.221231742082476,-0.707106781186553,-1.17557050458494,-1.40504701603470,-1.26007351067010,-0.744219717332697,-4.89858719658941e-15,0.744219717332704,1.26007351067010,1.40504701603470,1.17557050458494,0.707106781186548,0.221231742082472,-0.0600499921067871,3.88578058618805e-15,0.399903088302676,1.00000000000000,1.57547359288762,1.90211303259031,1.84206304048352,1.39680224666743,0.707106781186557,4.44089209850063e-15,-0.497066016555606,-0.642039521920207,-0.431350787252247,-3.30654635769785e-15,0.431350787252242,0.642039521920206,0.497066016555611,4.55191440096314e-15,-0.707106781186546,-1.39680224666742,-1.84206304048352,-1.90211303259031,-1.57547359288761,-0.999999999999998,-0.399903088302660,3.66373598126302e-15,0.0600499921067860,-0.221231742082476,-0.707106781186552,-1.17557050458495,-1.40504701603470,-1.26007351067010,-0.744219717332698,1.16403343982657e-14,0.744219717332718,1.26007351067010,1.40504701603470,1.17557050458496,0.707106781186561,0.221231742082482,-0.0600499921067840,-1.99840144432528e-15,0.399903088302663,1.00000000000000,1.57547359288762,1.90211303259031,1.84206304048353,1.39680224666743,0.707106781186558,5.44009282066327e-15,-0.497066016555606,-0.642039521920206,-0.431350787252239,6.61680659921524e-15,0.431350787252249,0.642039521920207,0.497066016555612,5.55111512312578e-15,-0.707106781186545,-1.39680224666742,-1.84206304048352,-1.90211303259031,-1.57547359288760,-0.999999999999984,-0.399903088302648,-2.10942374678780e-15,0.0600499921067861,-0.221231742082475,-0.707106781186552,-1.17557050458493,-1.40504701603470,-1.26007351067011,-0.744219717332714,-7.34788079488412e-15,0.744219717332702,1.26007351067010,1.40504701603470,1.17557050458494,0.707106781186538,0.221231742082483,-0.0600499921067839,-2.33146835171283e-15,0.399903088302663,1.00000000000000,1.57547359288761,1.90211303259031,1.84206304048352,1.39680224666741,0.707106781186559,6.32827124036339e-15,-0.497066016555605,-0.642039521920206,-0.431350787252240,5.88201851972683e-15,0.431350787252249,0.642039521920207,0.497066016555597,-2.22044604925031e-14,-0.707106781186544,-1.39680224666742,-1.84206304048352,-1.90211303259031,-1.5754735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+ float32_t rfft_testinput_f32_50hz_200Hz_ref[512] = { + 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+ float32_t f32_testOutput[1024], f32_testOutput_ref[1024]; + + float32_t rfft_testinput_f32_50hz_200Hz_fast[512] = { + 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+ float32_t rfft_testinput_f32_50hz_200Hz_fast_ref[512] = { + 0,0.744219717332704,1.26007351067010,1.40504701603470,1.17557050458495,0.707106781186548,0.221231742082474,-0.0600499921067857,-1.11022302462516e-16,0.399903088302664,1.00000000000000,1.57547359288761,1.90211303259031,1.84206304048352,1.39680224666742,0.707106781186548,4.44089209850063e-16,-0.497066016555608,-0.642039521920206,-0.431350787252243,-3.67394039744206e-16,0.431350787252243,0.642039521920206,0.497066016555607,-1.22124532708767e-15,-0.707106781186549,-1.39680224666742,-1.84206304048352,-1.90211303259031,-1.57547359288761,-1.00000000000000,-0.399903088302665,-3.33066907387547e-16,0.0600499921067852,-0.221231742082476,-0.707106781186550,-1.17557050458495,-1.40504701603470,-1.26007351067010,-0.744219717332705,-1.22464679914735e-15,0.744219717332707,1.26007351067010,1.40504701603470,1.17557050458495,0.707106781186549,0.221231742082475,-0.0600499921067854,8.88178419700125e-16,0.399903088302667,1.00000000000000,1.57547359288761,1.90211303259031,1.84206304048352,1.39680224666742,0.707106781186545,1.33226762955019e-15,-0.497066016555608,-0.642039521920206,-0.431350787252245,-1.10218211923262e-15,0.431350787252243,0.642039521920206,0.497066016555606,1.55431223447522e-15,-0.707106781186550,-1.39680224666743,-1.84206304048352,-1.90211303259031,-1.57547359288761,-0.999999999999995,-0.399903088302669,-7.77156117237610e-16,0.0600499921067867,-0.221231742082473,-0.707106781186549,-1.17557050458495,-1.40504701603470,-1.26007351067010,-0.744219717332702,-2.44929359829471e-15,0.744219717332706,1.26007351067010,1.40504701603470,1.17557050458494,0.707106781186546,0.221231742082476,-0.0600499921067846,-7.77156117237610e-16,0.399903088302660,0.999999999999998,1.57547359288761,1.90211303259031,1.84206304048352,1.39680224666742,0.707106781186546,-4.88498130835069e-15,-0.497066016555607,-0.642039521920206,-0.431350787252242,3.49210031947972e-15,0.431350787252243,0.642039521920206,0.497066016555610,2.55351295663786e-15,-0.707106781186549,-1.39680224666742,-1.84206304048352,-1.90211303259031,-1.57547359288761,-0.999999999999996,-0.399903088302658,-9.99200722162641e-16,0.0600499921067855,-0.221231742082477,-0.707106781186554,-1.17557050458494,-1.40504701603470,-1.26007351067011,-0.744219717332711,-3.67394039744206e-15,0.744219717332705,1.26007351067010,1.40504701603470,1.17557050458495,0.707106781186547,0.221231742082472,-0.0600499921067872,-1.22124532708767e-15,0.399903088302665,1.00000000000000,1.57547359288762,1.90211303259031,1.84206304048352,1.39680224666742,0.707106781186539,-1.09912079437891e-14,-0.497066016555607,-0.642039521920206,-0.431350787252238,8.08638275819206e-15,0.431350787252234,0.642039521920205,0.497066016555611,3.55271367880050e-15,-0.707106781186548,-1.39680224666741,-1.84206304048352,-1.90211303259031,-1.57547359288761,-0.999999999999997,-0.399903088302671,-1.44328993201270e-15,0.0600499921067857,-0.221231742082476,-0.707106781186553,-1.17557050458494,-1.40504701603470,-1.26007351067010,-0.744219717332697,-4.89858719658941e-15,0.744219717332704,1.26007351067010,1.40504701603470,1.17557050458494,0.707106781186548,0.221231742082472,-0.0600499921067871,3.88578058618805e-15,0.399903088302676,1.00000000000000,1.57547359288762,1.90211303259031,1.84206304048352,1.39680224666743,0.707106781186557,4.44089209850063e-15,-0.497066016555606,-0.642039521920207,-0.431350787252247,-3.30654635769785e-15,0.431350787252242,0.642039521920206,0.497066016555611,4.55191440096314e-15,-0.707106781186546,-1.39680224666742,-1.84206304048352,-1.90211303259031,-1.57547359288761,-0.999999999999998,-0.399903088302660,3.66373598126302e-15,0.0600499921067860,-0.221231742082476,-0.707106781186552,-1.17557050458495,-1.40504701603470,-1.26007351067010,-0.744219717332698,1.16403343982657e-14,0.744219717332718,1.26007351067010,1.40504701603470,1.17557050458496,0.707106781186561,0.221231742082482,-0.0600499921067840,-1.99840144432528e-15,0.399903088302663,1.00000000000000,1.57547359288762,1.90211303259031,1.84206304048353,1.39680224666743,0.707106781186558,5.44009282066327e-15,-0.497066016555606,-0.642039521920206,-0.431350787252239,6.61680659921524e-15,0.431350787252249,0.642039521920207,0.497066016555612,5.55111512312578e-15,-0.707106781186545,-1.39680224666742,-1.84206304048352,-1.90211303259031,-1.57547359288760,-0.999999999999984,-0.399903088302648,-2.10942374678780e-15,0.0600499921067861,-0.221231742082475,-0.707106781186552,-1.17557050458493,-1.40504701603470,-1.26007351067011,-0.744219717332714,-7.34788079488412e-15,0.744219717332702,1.26007351067010,1.40504701603470,1.17557050458494,0.707106781186538,0.221231742082483,-0.0600499921067839,-2.33146835171283e-15,0.399903088302663,1.00000000000000,1.57547359288761,1.90211303259031,1.84206304048352,1.39680224666741,0.707106781186559,6.32827124036339e-15,-0.497066016555605,-0.642039521920206,-0.431350787252240,5.88201851972683e-15,0.431350787252249,0.642039521920207,0.497066016555597,-2.22044604925031e-14,-0.707106781186544,-1.39680224666742,-1.84206304048352,-1.90211303259031,-1.5754735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+ diff --git a/examples/dsp/TransformFunction_rfftf32/cfft.c b/examples/dsp/TransformFunction_rfftf32/cfft.c new file mode 100644 index 00000000..98c71c22 --- /dev/null +++ b/examples/dsp/TransformFunction_rfftf32/cfft.c @@ -0,0 +1,618 @@ +#include "riscv_const_structs.h" +#include "ref.h" + +void ref_cfft_f32(const riscv_cfft_instance_f32 *S, float32_t *p1, + uint8_t ifftFlag, uint8_t bitReverseFlag) +{ + int n, mmax, m, j, istep, i; + float32_t wtemp, wr, wpr, wpi, wi, theta; + float32_t tempr, tempi; + float32_t *data = p1; + uint32_t N = S->fftLen; + int32_t dir = (ifftFlag) ? -1 : 1; + + // decrement pointer since the original version used fortran style indexing. + data--; + + n = N << 1; + j = 1; + for (i = 1; i < n; i += 2) { + if (j > i) { + tempr = data[j]; + data[j] = data[i]; + data[i] = tempr; + tempr = data[j + 1]; + data[j + 1] = data[i + 1]; + data[i + 1] = tempr; + } + m = n >> 1; + while (m >= 2 && j > m) { + j -= m; + m >>= 1; + } + j += m; + } + mmax = 2; + while (n > mmax) { + istep = 2 * mmax; + theta = -6.283185307179586f / (dir * mmax); + wtemp = sinf(0.5f * theta); + wpr = -2.0f * wtemp * wtemp; + wpi = sinf(theta); + wr = 1.0f; + wi = 0.0f; + for (m = 1; m < mmax; m += 2) { + for (i = m; i <= n; i += istep) { + j = i + mmax; + tempr = wr * data[j] - wi * data[j + 1]; + tempi = wr * data[j + 1] + wi * data[j]; + data[j] = data[i] - tempr; + data[j + 1] = data[i + 1] - tempi; + data[i] += tempr; + data[i + 1] += tempi; + } + wr = (wtemp = wr) * wpr - wi * wpi + wr; + wi = wi * wpr + wtemp * wpi + wi; + } + mmax = istep; + } + + // Inverse transform is scaled by 1/N + if (ifftFlag) { + data++; + for (i = 0; i < 2 * N; i++) { + data[i] /= N; + } + } +} + +void ref_cfft_q31(const riscv_cfft_instance_q31 *S, q31_t *p1, uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + uint32_t i; + // float32_t *fSrc = (float32_t*)p1; + float32_t fSrc[S->fftLen * 2]; + riscv_q31_to_float(p1, fSrc, S->fftLen * 2); + for (i = 0; i < S->fftLen * 2; i++) { + // read the q31 data, cast to float, scale down for float + fSrc[i] = (float32_t)p1[i] / 2147483648.0f; + } + + switch (S->fftLen) { + case 16: + ref_cfft_f32(&riscv_cfft_sR_f32_len16, fSrc, ifftFlag, + bitReverseFlag); + break; + + case 32: + ref_cfft_f32(&riscv_cfft_sR_f32_len32, fSrc, ifftFlag, + bitReverseFlag); + break; + + case 64: + ref_cfft_f32(&riscv_cfft_sR_f32_len64, fSrc, ifftFlag, + bitReverseFlag); + break; + + case 128: + ref_cfft_f32(&riscv_cfft_sR_f32_len128, fSrc, ifftFlag, + bitReverseFlag); + break; + + case 256: + ref_cfft_f32(&riscv_cfft_sR_f32_len256, fSrc, ifftFlag, + bitReverseFlag); + break; + + case 512: + ref_cfft_f32(&riscv_cfft_sR_f32_len512, fSrc, ifftFlag, + bitReverseFlag); + break; + + case 1024: + ref_cfft_f32(&riscv_cfft_sR_f32_len1024, fSrc, ifftFlag, + bitReverseFlag); + break; + + case 2048: + ref_cfft_f32(&riscv_cfft_sR_f32_len2048, fSrc, ifftFlag, + bitReverseFlag); + break; + + case 4096: + ref_cfft_f32(&riscv_cfft_sR_f32_len4096, fSrc, ifftFlag, + bitReverseFlag); + break; + } + + if (ifftFlag) { + for (i = 0; i < S->fftLen * 2; i++) { + // read the float data, scale up for q31, cast to q31 + p1[i] = (q31_t)(fSrc[i] * 2147483648.0f); + } + } else { + for (i = 0; i < S->fftLen * 2; i++) { + // read the float data, scale up for q31, cast to q31 + p1[i] = (q31_t)(fSrc[i] * 2147483648.0f / (float32_t)S->fftLen); + } + } +} + +void ref_cfft_q15(const riscv_cfft_instance_q15 *S, q15_t *pSrc, uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + uint32_t i; + // float32_t *fSrc = (float32_t*)pSrc; + float32_t fSrc[S->fftLen * 2]; + riscv_q15_to_float(pSrc, fSrc, S->fftLen * 2); + + for (i = 0; i < S->fftLen * 2; i++) { + // read the q15 data, cast to float, scale down for float, place in + // temporary buffer + scratchArray[i] = (float32_t)pSrc[i] / 32768.0f; + } + + for (i = 0; i < S->fftLen * 2; i++) { + // copy from temp buffer to final buffer + fSrc[i] = scratchArray[i]; + } + + switch (S->fftLen) { + case 16: + ref_cfft_f32(&riscv_cfft_sR_f32_len16, fSrc, ifftFlag, + bitReverseFlag); + break; + + case 32: + ref_cfft_f32(&riscv_cfft_sR_f32_len32, fSrc, ifftFlag, + bitReverseFlag); + break; + + case 64: + ref_cfft_f32(&riscv_cfft_sR_f32_len64, fSrc, ifftFlag, + bitReverseFlag); + break; + + case 128: + ref_cfft_f32(&riscv_cfft_sR_f32_len128, fSrc, ifftFlag, + bitReverseFlag); + break; + + case 256: + ref_cfft_f32(&riscv_cfft_sR_f32_len256, fSrc, ifftFlag, + bitReverseFlag); + break; + + case 512: + ref_cfft_f32(&riscv_cfft_sR_f32_len512, fSrc, ifftFlag, + bitReverseFlag); + break; + + case 1024: + ref_cfft_f32(&riscv_cfft_sR_f32_len1024, fSrc, ifftFlag, + bitReverseFlag); + break; + + case 2048: + ref_cfft_f32(&riscv_cfft_sR_f32_len2048, fSrc, ifftFlag, + bitReverseFlag); + break; + + case 4096: + ref_cfft_f32(&riscv_cfft_sR_f32_len4096, fSrc, ifftFlag, + bitReverseFlag); + break; + } + + if (ifftFlag) { + for (i = 0; i < S->fftLen * 2; i++) { + // read the float data, scale up for q15, cast to q15 + pSrc[i] = (q15_t)(fSrc[i] * 32768.0f); + } + } else { + for (i = 0; i < S->fftLen * 2; i++) { + // read the float data, scale up for q15, cast to q15 + pSrc[i] = (q15_t)(fSrc[i] * 32768.0f / (float32_t)S->fftLen); + } + } +} + +void ref_cfft_radix2_f32(const riscv_cfft_radix2_instance_f32 *S, float32_t *pSrc) +{ + switch (S->fftLen) { + case 16: + ref_cfft_f32(&riscv_cfft_sR_f32_len16, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 32: + ref_cfft_f32(&riscv_cfft_sR_f32_len32, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 64: + ref_cfft_f32(&riscv_cfft_sR_f32_len64, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 128: + ref_cfft_f32(&riscv_cfft_sR_f32_len128, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 256: + ref_cfft_f32(&riscv_cfft_sR_f32_len256, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 512: + ref_cfft_f32(&riscv_cfft_sR_f32_len512, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 1024: + ref_cfft_f32(&riscv_cfft_sR_f32_len1024, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 2048: + ref_cfft_f32(&riscv_cfft_sR_f32_len2048, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 4096: + ref_cfft_f32(&riscv_cfft_sR_f32_len4096, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + } +} + +void ref_cfft_radix2_q31(const riscv_cfft_radix2_instance_q31 *S, q31_t *pSrc) +{ + uint32_t i; + // float32_t *fSrc = (float32_t*)pSrc; + float32_t fSrc[S->fftLen * 2]; + riscv_q31_to_float(pSrc, fSrc, S->fftLen * 2); + + for (i = 0; i < S->fftLen * 2; i++) { + // read the q31 data, cast to float, scale down for float + fSrc[i] = (float32_t)pSrc[i] / 2147483648.0f; + } + + switch (S->fftLen) { + case 16: + ref_cfft_f32(&riscv_cfft_sR_f32_len16, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 32: + ref_cfft_f32(&riscv_cfft_sR_f32_len32, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 64: + ref_cfft_f32(&riscv_cfft_sR_f32_len64, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 128: + ref_cfft_f32(&riscv_cfft_sR_f32_len128, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 256: + ref_cfft_f32(&riscv_cfft_sR_f32_len256, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 512: + ref_cfft_f32(&riscv_cfft_sR_f32_len512, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 1024: + ref_cfft_f32(&riscv_cfft_sR_f32_len1024, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 2048: + ref_cfft_f32(&riscv_cfft_sR_f32_len2048, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 4096: + ref_cfft_f32(&riscv_cfft_sR_f32_len4096, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + } + + if (S->ifftFlag) { + for (i = 0; i < S->fftLen * 2; i++) { + // read the float data, scale up for q31, cast to q31 + pSrc[i] = (q31_t)(fSrc[i] * 2147483648.0f); + } + } else { + for (i = 0; i < S->fftLen * 2; i++) { + // read the float data, scale up for q31, cast to q31 + pSrc[i] = (q31_t)(fSrc[i] * 2147483648.0f / (float32_t)S->fftLen); + } + } +} + +void ref_cfft_radix2_q15(const riscv_cfft_radix2_instance_q15 *S, q15_t *pSrc) +{ + uint32_t i; + // float32_t *fSrc = (float32_t*)pSrc; + float32_t fSrc[S->fftLen * 2]; + riscv_q15_to_float(pSrc, fSrc, S->fftLen * 2); + + for (i = 0; i < S->fftLen * 2; i++) { + // read the q15 data, cast to float, scale down for float, place in + // temporary buffer + scratchArray[i] = (float32_t)pSrc[i] / 32768.0f; + } + + for (i = 0; i < S->fftLen * 2; i++) { + // copy from temp buffer to final buffer + fSrc[i] = scratchArray[i]; + } + + switch (S->fftLen) { + case 16: + ref_cfft_f32(&riscv_cfft_sR_f32_len16, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 32: + ref_cfft_f32(&riscv_cfft_sR_f32_len32, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 64: + ref_cfft_f32(&riscv_cfft_sR_f32_len64, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 128: + ref_cfft_f32(&riscv_cfft_sR_f32_len128, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 256: + ref_cfft_f32(&riscv_cfft_sR_f32_len256, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 512: + ref_cfft_f32(&riscv_cfft_sR_f32_len512, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 1024: + ref_cfft_f32(&riscv_cfft_sR_f32_len1024, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 2048: + ref_cfft_f32(&riscv_cfft_sR_f32_len2048, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 4096: + ref_cfft_f32(&riscv_cfft_sR_f32_len4096, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + } + + if (S->ifftFlag) { + for (i = 0; i < S->fftLen * 2; i++) { + // read the float data, scale up for q15, cast to q15 + pSrc[i] = (q15_t)(fSrc[i] * 32768.0f); + } + } else { + for (i = 0; i < S->fftLen * 2; i++) { + // read the float data, scale up for q15, cast to q15 + pSrc[i] = (q15_t)(fSrc[i] * 32768.0f / (float32_t)S->fftLen); + } + } +} + +void ref_cfft_radix4_f32(const riscv_cfft_radix4_instance_f32 *S, float32_t *pSrc) +{ + switch (S->fftLen) { + case 16: + ref_cfft_f32(&riscv_cfft_sR_f32_len16, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 32: + ref_cfft_f32(&riscv_cfft_sR_f32_len32, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 64: + ref_cfft_f32(&riscv_cfft_sR_f32_len64, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 128: + ref_cfft_f32(&riscv_cfft_sR_f32_len128, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 256: + ref_cfft_f32(&riscv_cfft_sR_f32_len256, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 512: + ref_cfft_f32(&riscv_cfft_sR_f32_len512, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 1024: + ref_cfft_f32(&riscv_cfft_sR_f32_len1024, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 2048: + ref_cfft_f32(&riscv_cfft_sR_f32_len2048, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 4096: + ref_cfft_f32(&riscv_cfft_sR_f32_len4096, pSrc, S->ifftFlag, + S->bitReverseFlag); + break; + } +} + +void ref_cfft_radix4_q31(const riscv_cfft_radix4_instance_q31 *S, q31_t *pSrc) +{ + uint32_t i; + // float32_t *fSrc = (float32_t*)pSrc; + float32_t fSrc[S->fftLen * 2]; + riscv_q31_to_float(pSrc, fSrc, S->fftLen * 2); + + for (i = 0; i < S->fftLen * 2; i++) { + // read the q31 data, cast to float, scale down for float + fSrc[i] = (float32_t)pSrc[i] / 2147483648.0f; + } + + switch (S->fftLen) { + case 16: + ref_cfft_f32(&riscv_cfft_sR_f32_len16, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 32: + ref_cfft_f32(&riscv_cfft_sR_f32_len32, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 64: + ref_cfft_f32(&riscv_cfft_sR_f32_len64, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 128: + ref_cfft_f32(&riscv_cfft_sR_f32_len128, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 256: + ref_cfft_f32(&riscv_cfft_sR_f32_len256, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 512: + ref_cfft_f32(&riscv_cfft_sR_f32_len512, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 1024: + ref_cfft_f32(&riscv_cfft_sR_f32_len1024, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 2048: + ref_cfft_f32(&riscv_cfft_sR_f32_len2048, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 4096: + ref_cfft_f32(&riscv_cfft_sR_f32_len4096, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + } + + if (S->ifftFlag) { + for (i = 0; i < S->fftLen * 2; i++) { + // read the float data, scale up for q31, cast to q31 + pSrc[i] = (q31_t)(fSrc[i] * 2147483648.0f); + } + } else { + for (i = 0; i < S->fftLen * 2; i++) { + // read the float data, scale up for q31, cast to q31 + pSrc[i] = (q31_t)(fSrc[i] * 2147483648.0f / (float32_t)S->fftLen); + } + } +} + +void ref_cfft_radix4_q15(const riscv_cfft_radix4_instance_q15 *S, q15_t *pSrc) +{ + uint32_t i; + // float32_t *fSrc = (float32_t*)pSrc; + float32_t fSrc[S->fftLen * 2]; + riscv_q15_to_float(pSrc, fSrc, S->fftLen * 2); + + for (i = 0; i < S->fftLen * 2; i++) { + // read the q15 data, cast to float, scale down for float, place in + // temporary buffer + scratchArray[i] = (float32_t)pSrc[i] / 32768.0f; + } + + for (i = 0; i < S->fftLen * 2; i++) { + // copy from temp buffer to final buffer + fSrc[i] = scratchArray[i]; + } + + switch (S->fftLen) { + case 16: + ref_cfft_f32(&riscv_cfft_sR_f32_len16, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 32: + ref_cfft_f32(&riscv_cfft_sR_f32_len32, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 64: + ref_cfft_f32(&riscv_cfft_sR_f32_len64, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 128: + ref_cfft_f32(&riscv_cfft_sR_f32_len128, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 256: + ref_cfft_f32(&riscv_cfft_sR_f32_len256, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 512: + ref_cfft_f32(&riscv_cfft_sR_f32_len512, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 1024: + ref_cfft_f32(&riscv_cfft_sR_f32_len1024, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 2048: + ref_cfft_f32(&riscv_cfft_sR_f32_len2048, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + + case 4096: + ref_cfft_f32(&riscv_cfft_sR_f32_len4096, fSrc, S->ifftFlag, + S->bitReverseFlag); + break; + } + + if (S->ifftFlag) { + for (i = 0; i < S->fftLen * 2; i++) { + // read the float data, scale up for q15, cast to q15 + pSrc[i] = (q15_t)(fSrc[i] * 32768.0f); + } + } else { + for (i = 0; i < S->fftLen * 2; i++) { + // read the float data, scale up for q15, cast to q15 + pSrc[i] = (q15_t)(fSrc[i] * 32768.0f / (float32_t)S->fftLen); + } + } +} diff --git a/examples/dsp/TransformFunction_rfftf32/main.c b/examples/dsp/TransformFunction_rfftf32/main.c new file mode 100644 index 00000000..efdc7018 --- /dev/null +++ b/examples/dsp/TransformFunction_rfftf32/main.c @@ -0,0 +1,97 @@ +// +// Created by lujun on 19-6-28. +// +// This contains SIN_COS , clarke, inv_clarke, park, inv_park and pid +// each one has it's own function. +// All function can be found in main function. +// If you don't want to use it, then comment it. +#include "riscv_common_tables.h" +#include "riscv_const_structs.h" +#include "riscv_math.h" +#include "array.h" +#include +#include "../common.h" + +#include "../HelperFunctions/math_helper.c" +#include "../HelperFunctions/ref_helper.c" + +#include +#define DELTAF32 (0.05f) +#define DELTAQ31 (63) +#define DELTAQ15 (1) +#define DELTAQ7 (1) + +int test_flag_error = 0; + +uint32_t fftSize = 1024; +uint32_t ifftFlag = 0; +uint32_t doBitReverse = 1; + +static int DSP_rfft_fast_f32(void) +{ + uint16_t i; + /* clang-format off */ + riscv_rfft_fast_instance_f32 SS; + /* clang-format on */ + riscv_rfft_fast_init_f32(&SS, 512); + BENCH_START(riscv_rfft_fast_f32); + riscv_rfft_fast_f32(&SS, rfft_testinput_f32_50hz_200Hz_fast, f32_testOutput, 0); + BENCH_END(riscv_rfft_fast_f32); + ref_rfft_fast_f32(&SS, rfft_testinput_f32_50hz_200Hz_fast_ref, + f32_testOutput_ref, 0); + float32_t resault, resault_ref; + uint32_t index, index_ref; + riscv_max_f32(f32_testOutput, 512, &resault, &index); + riscv_max_f32(f32_testOutput_ref, 512, &resault_ref, &index_ref); + + if (index != index_ref) { + BENCH_ERROR(riscv_rfft_fast_f32); + printf("expect: %d, actual: %d\n", index_ref, index); + test_flag_error = 1; + } + BENCH_STATUS(riscv_rfft_fast_f32); +} +static int DSP_rfft_f32(void) +{ + /* clang-format off */ + uint16_t i, j; + riscv_rfft_instance_f32 SS; + riscv_cfft_radix4_instance_f32 S_CFFT; + /* clang-format on */ + fftSize = 512; + ifftFlag = 0; + doBitReverse = 1; + riscv_cfft_radix4_init_f32(&S_CFFT, 256, ifftFlag, doBitReverse); + riscv_rfft_init_f32(&SS, &S_CFFT, fftSize, ifftFlag, doBitReverse); + BENCH_START(riscv_rfft_f32); + riscv_rfft_f32(&SS, rfft_testinput_f32_50hz_200Hz, f32_testOutput); + BENCH_END(riscv_rfft_f32); + riscv_cfft_radix4_init_f32(&S_CFFT, 256, ifftFlag, doBitReverse); + riscv_rfft_init_f32(&SS, &S_CFFT, fftSize, ifftFlag, doBitReverse); + ref_rfft_f32(&SS, rfft_testinput_f32_50hz_200Hz_ref, f32_testOutput_ref); + float32_t resault, resault_ref; + uint32_t index, index_ref; + riscv_max_f32(f32_testOutput, fftSize, &resault, &index); + riscv_max_f32(f32_testOutput_ref, fftSize, &resault_ref, &index_ref); + if (index != index_ref) { + BENCH_ERROR(riscv_rfft_f32); + printf("expect: %d, actual: %d\n", index_ref, index); + test_flag_error = 1; + } + BENCH_STATUS(riscv_rfft_f32); +} + +int main() +{ + BENCH_INIT; + DSP_rfft_fast_f32(); + DSP_rfft_f32(); + BENCH_FINISH; + if (test_flag_error) { + printf("test error apprears, please recheck.\n"); + return 1; + } else { + printf("all test are passed. Well done!\n"); + } + return 0; +} diff --git a/examples/dsp/TransformFunction_rfftf32/rfft.c b/examples/dsp/TransformFunction_rfftf32/rfft.c new file mode 100644 index 00000000..90bc7e3a --- /dev/null +++ b/examples/dsp/TransformFunction_rfftf32/rfft.c @@ -0,0 +1,276 @@ +#include "riscv_const_structs.h" +#include "ref.h" + +void ref_rfft_f32(riscv_rfft_instance_f32 *S, float32_t *pSrc, float32_t *pDst) +{ + uint32_t i; + + if (S->ifftFlagR) { + for (i = 0; i < S->fftLenReal * 2; i++) { + pDst[i] = pSrc[i]; + } + } else { + for (i = 0; i < S->fftLenReal; i++) { + pDst[2 * i + 0] = pSrc[i]; + pDst[2 * i + 1] = 0.0f; + } + } + + switch (S->fftLenReal) { + case 128: + ref_cfft_f32(&riscv_cfft_sR_f32_len128, pDst, S->ifftFlagR, + S->bitReverseFlagR); + break; + + case 512: + ref_cfft_f32(&riscv_cfft_sR_f32_len512, pDst, S->ifftFlagR, + S->bitReverseFlagR); + break; + + case 2048: + ref_cfft_f32(&riscv_cfft_sR_f32_len2048, pDst, S->ifftFlagR, + S->bitReverseFlagR); + break; + + case 8192: + ref_cfft_f32(&ref_cfft_sR_f32_len8192, pDst, S->ifftFlagR, + S->bitReverseFlagR); + break; + } + + if (S->ifftFlagR) { + // throw away the imaginary part which should be all zeros + for (i = 0; i < S->fftLenReal; i++) { + pDst[i] = pDst[2 * i]; + } + } +} + +void ref_rfft_fast_f32(riscv_rfft_fast_instance_f32 *S, float32_t *p, + float32_t *pOut, uint8_t ifftFlag) +{ + uint32_t i, j; + + if (ifftFlag) { + for (i = 0; i < S->fftLenRFFT; i++) { + pOut[i] = p[i]; + } + // unpack first sample's complex part into middle sample's real part + pOut[S->fftLenRFFT] = pOut[1]; + pOut[S->fftLenRFFT + 1] = 0; + pOut[1] = 0; + j = 4; + for (i = S->fftLenRFFT / 2 + 1; i < S->fftLenRFFT; i++) { + pOut[2 * i + 0] = p[2 * i + 0 - j]; + pOut[2 * i + 1] = -p[2 * i + 1 - j]; + j += 4; + } + } else { + for (i = 0; i < S->fftLenRFFT; i++) { + pOut[2 * i + 0] = p[i]; + pOut[2 * i + 1] = 0.0f; + } + } + + switch (S->fftLenRFFT) { + case 32: + ref_cfft_f32(&riscv_cfft_sR_f32_len32, pOut, ifftFlag, 1); + break; + + case 64: + ref_cfft_f32(&riscv_cfft_sR_f32_len64, pOut, ifftFlag, 1); + break; + + case 128: + ref_cfft_f32(&riscv_cfft_sR_f32_len128, pOut, ifftFlag, 1); + break; + + case 256: + ref_cfft_f32(&riscv_cfft_sR_f32_len256, pOut, ifftFlag, 1); + break; + + case 512: + ref_cfft_f32(&riscv_cfft_sR_f32_len512, pOut, ifftFlag, 1); + break; + + case 1024: + ref_cfft_f32(&riscv_cfft_sR_f32_len1024, pOut, ifftFlag, 1); + break; + + case 2048: + ref_cfft_f32(&riscv_cfft_sR_f32_len2048, pOut, ifftFlag, 1); + break; + + case 4096: + ref_cfft_f32(&riscv_cfft_sR_f32_len4096, pOut, ifftFlag, 1); + break; + } + + if (ifftFlag) { + // throw away the imaginary part which should be all zeros + for (i = 0; i < S->fftLenRFFT; i++) { + pOut[i] = pOut[2 * i]; + } + } else { + // pack last sample's real part into first sample's complex part + pOut[1] = pOut[S->fftLenRFFT]; + } +} + +void ref_rfft_q31(const riscv_rfft_instance_q31 *S, q31_t *pSrc, q31_t *pDst) +{ + uint32_t i; + // float32_t *fDst = (float32_t*)pDst; + float32_t fDst[S->fftLenReal * 2]; + riscv_q31_to_float(pSrc, fDst, S->fftLenReal * 2); + + if (S->ifftFlagR) { + for (i = 0; i < S->fftLenReal * 2; i++) { + fDst[i] = (float32_t)pSrc[i] / 2147483648.0f; + } + } else { + for (i = 0; i < S->fftLenReal; i++) { + fDst[2 * i + 0] = (float32_t)pSrc[i] / 2147483648.0f; + fDst[2 * i + 1] = 0.0f; + } + } + + switch (S->fftLenReal) { + case 32: + ref_cfft_f32(&riscv_cfft_sR_f32_len32, fDst, S->ifftFlagR, + S->bitReverseFlagR); + break; + + case 64: + ref_cfft_f32(&riscv_cfft_sR_f32_len64, fDst, S->ifftFlagR, + S->bitReverseFlagR); + break; + + case 128: + ref_cfft_f32(&riscv_cfft_sR_f32_len128, fDst, S->ifftFlagR, + S->bitReverseFlagR); + break; + + case 256: + ref_cfft_f32(&riscv_cfft_sR_f32_len256, fDst, S->ifftFlagR, + S->bitReverseFlagR); + break; + + case 512: + ref_cfft_f32(&riscv_cfft_sR_f32_len512, fDst, S->ifftFlagR, + S->bitReverseFlagR); + break; + + case 1024: + ref_cfft_f32(&riscv_cfft_sR_f32_len1024, fDst, S->ifftFlagR, + S->bitReverseFlagR); + break; + + case 2048: + ref_cfft_f32(&riscv_cfft_sR_f32_len2048, fDst, S->ifftFlagR, + S->bitReverseFlagR); + break; + + case 4096: + ref_cfft_f32(&riscv_cfft_sR_f32_len4096, fDst, S->ifftFlagR, + S->bitReverseFlagR); + break; + + case 8192: + ref_cfft_f32(&ref_cfft_sR_f32_len8192, fDst, S->ifftFlagR, + S->bitReverseFlagR); + break; + } + + if (S->ifftFlagR) { + // throw away the imaginary part which should be all zeros + for (i = 0; i < S->fftLenReal; i++) { + // read the float data, scale up for q31, cast to q31 + pDst[i] = (q31_t)(fDst[2 * i] * 2147483648.0f); + } + } else { + for (i = 0; i < S->fftLenReal; i++) { + // read the float data, scale up for q31, cast to q31 + pDst[i] = + (q31_t)(fDst[i] * 2147483648.0f / (float32_t)S->fftLenReal); + } + } +} + +void ref_rfft_q15(const riscv_rfft_instance_q15 *S, q15_t *pSrc, q15_t *pDst) +{ + uint32_t i; + // float32_t *fDst = (float32_t*)pDst; + float32_t fDst[S->fftLenReal * 2]; + riscv_q15_to_float(pSrc, fDst, S->fftLenReal * 2); + + if (S->ifftFlagR) { + for (i = 0; i < S->fftLenReal * 2; i++) { + fDst[i] = (float32_t)pSrc[i] / 32768.0f; + } + } else { + for (i = 0; i < S->fftLenReal; i++) { + // read the q15 data, cast to float, scale down for float + fDst[2 * i + 0] = (float32_t)pSrc[i] / 32768.0f; + fDst[2 * i + 1] = 0.0f; + } + } + + switch (S->fftLenReal) { + case 32: + ref_cfft_f32(&riscv_cfft_sR_f32_len32, fDst, S->ifftFlagR, + S->bitReverseFlagR); + break; + + case 64: + ref_cfft_f32(&riscv_cfft_sR_f32_len64, fDst, S->ifftFlagR, + S->bitReverseFlagR); + break; + + case 128: + ref_cfft_f32(&riscv_cfft_sR_f32_len128, fDst, S->ifftFlagR, + S->bitReverseFlagR); + break; + + case 256: + ref_cfft_f32(&riscv_cfft_sR_f32_len256, fDst, S->ifftFlagR, + S->bitReverseFlagR); + break; + + case 512: + ref_cfft_f32(&riscv_cfft_sR_f32_len512, fDst, S->ifftFlagR, + S->bitReverseFlagR); + break; + + case 1024: + ref_cfft_f32(&riscv_cfft_sR_f32_len1024, fDst, S->ifftFlagR, + S->bitReverseFlagR); + break; + + case 2048: + ref_cfft_f32(&riscv_cfft_sR_f32_len2048, fDst, S->ifftFlagR, + S->bitReverseFlagR); + break; + + case 4096: + ref_cfft_f32(&riscv_cfft_sR_f32_len4096, fDst, S->ifftFlagR, + S->bitReverseFlagR); + break; + + case 8192: + ref_cfft_f32(&ref_cfft_sR_f32_len8192, fDst, S->ifftFlagR, + S->bitReverseFlagR); + break; + } + + if (S->ifftFlagR) { + // throw away the imaginary part which should be all zeros + for (i = 0; i < S->fftLenReal; i++) { + pDst[i] = (q15_t)(fDst[2 * i] * 32768.0f); + } + } else { + for (i = 0; i < S->fftLenReal; i++) { + pDst[i] = (q15_t)(fDst[i] * 32768.0f / (float32_t)S->fftLenReal); + } + } +} diff --git a/examples/dsp/common.h b/examples/dsp/common.h new file mode 100644 index 00000000..2217af23 --- /dev/null +++ b/examples/dsp/common.h @@ -0,0 +1,138 @@ +// +// Created by lujun on 7/13/19. +// + +#ifndef DSP_COMMON_H +#define DSP_COMMON_H + +#include +#include +#include "hal_mtimer.h" + +extern void bflb_platform_printf(char *fmt, ...); +extern void bflb_platform_init(uint32_t baudrate); + +#define MSG(a, ...) bflb_platform_printf(a, ##__VA_ARGS__) +#define MSG_DBG(a, ...) bflb_platform_printf(a, ##__VA_ARGS__) +#define MSG_ERR(a, ...) bflb_platform_printf(a, ##__VA_ARGS__) + +#undef printf +#define printf(a, ...) bflb_platform_printf(a, ##__VA_ARGS__) +#ifdef __riscv + +#define read_csr(reg) \ + ({ \ + unsigned int __temp; \ + __ASM volatile("csrr %0, " #reg : "=r"(__temp)); \ + __temp; \ + }) + +#if __riscv_xlen == 32 +static inline uint64_t read_cpu_cycle(void) +{ + uint32_t hi = 0, hi1 = 0, lo = 0; + uint64_t val = 0; + hi = read_csr(cycleh); + lo = read_csr(cycle); + hi1 = read_csr(cycleh); + if (hi != hi1) { + hi = read_csr(cycleh); + lo = read_csr(cycle); + } + val = (((uint64_t)hi) << 32) | lo; + return val; +} +static inline uint64_t read_cpu_instret(void) +{ + uint32_t hi = 0, hi1 = 0, lo = 0; + uint64_t val = 0; + hi = read_csr(instreth); + lo = read_csr(instret); + hi1 = read_csr(instreth); + if (hi != hi1) { + hi = read_csr(instreth); + lo = read_csr(instret); + } + val = (((uint64_t)hi) << 32) | lo; + return val; +} +#else +static inline uint64_t read_cpu_cycle(void) +{ + uint64_t val = 0; + val = read_csr(cycle); + return val; +} +static inline uint64_t read_cpu_instret(void) +{ + uint64_t val = 0; + val = read_csr(instret); + return val; +} +#endif +static inline void reset_cpu_cycle(void) { ; } +static inline void setup_vector(void) +{ +#if (defined (__RISCV_FEATURE_VECTOR) && (__RISCV_FEATURE_VECTOR == 1)) + __RV_CSR_SET(CSR_MSTATUS, 0x200); +#endif +} +#endif /*__riscv*/ + + +#ifndef READ_CYCLE +#define READ_CYCLE mtimer_get_time_us +#endif + +#ifndef RESET_CYCLE +#define RESET_CYCLE reset_cpu_cycle +#endif + +#ifndef INIT_VECTOR +#define INIT_VECTOR setup_vector +#endif + +uint64_t enter_cycle; +uint64_t exit_cycle; +uint64_t start_cycle; +uint64_t end_cycle; +uint64_t cycle; +uint64_t extra_cost = 0; +uint32_t bench_ercd; + +#define BENCH_TRST RESET_CYCLE(); + +#define BENCH_INIT \ + bflb_platform_init(0); \ + MSG("Benchmark Initialized\n"); \ + INIT_VECTOR(); \ + BENCH_TRST \ + start_cycle = READ_CYCLE(); \ + end_cycle = READ_CYCLE(); \ + extra_cost = end_cycle - start_cycle; \ + enter_cycle = READ_CYCLE(); + +#define BENCH_START(func) \ + bench_ercd = 0; \ + BENCH_TRST \ + start_cycle = READ_CYCLE(); + +#define BENCH_END(func) \ + end_cycle = READ_CYCLE(); \ + cycle = end_cycle - start_cycle - extra_cost; \ + MSG("CSV, %s, %lu\n", #func, cycle); + +#define BENCH_ERROR(func) bench_ercd = 1; +#define BENCH_STATUS(func) \ + if (bench_ercd) { \ + MSG("ERROR, %s\n", #func); \ + } else { \ + MSG("SUCCESS, %s\n", #func); \ + } + +#define BENCH_FINISH \ + exit_cycle = READ_CYCLE(); \ + cycle = exit_cycle - enter_cycle - extra_cost; \ + MSG("CSV, BENCH END, %llu\n", cycle); + +#endif // DSP_COMMON_H diff --git a/examples/dsp/ref.h b/examples/dsp/ref.h new file mode 100644 index 00000000..f43fcfa4 --- /dev/null +++ b/examples/dsp/ref.h @@ -0,0 +1,882 @@ + +#ifndef _REF_H +#define _REF_H + +#include "riscv_math.h" +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef PI +#define PI 3.14159265358979f +#endif + +/** + * @brief 8-bit fractional data type in 1.7 format. + */ +// typedef int8_t q7_t; + +/** + * @brief 16-bit fractional data type in 1.15 format. + */ +// typedef int16_t q15_t; + +/** + * @brief 32-bit fractional data type in 1.31 format. + */ +// typedef int32_t q31_t; + +/** + * @brief 64-bit fractional data type in 1.63 format. + */ +// typedef int64_t q63_t; + +/** + * @brief 32-bit floating-point type definition. + */ +// typedef float float32_t; + +/** + * @brief 64-bit floating-point type definition. + */ +// typedef double float64_t; + +/** + * @brief Error status returned by some functions in the library. + */ + +typedef enum { + REF_Q7 = 0, + REF_Q15, + REF_Q31, + REF_F32, +} dataType; + +#ifndef FLT_MAX +#define FLT_MAX 3.40282347e+38F +#endif + +#ifndef DBL_MAX +#define DBL_MAX 1.79769313486231571e+308 +#endif + +#ifndef FLT_MIN +#define FLT_MIN 1.175494351e-38F +#endif + +#ifndef DBL_MIN +#define DBL_MIN 2.22507385850720138e-308 +#endif + +#ifndef SCHAR_MIN +/* mimimum value for an object of type signed char */ +#define SCHAR_MIN (-128) +#endif + +#ifndef SCHAR_MAX +/* maximum value for an object of type signed char */ +#define SCHAR_MAX 127 +#endif + +#ifndef UCHAR_MAX +/* maximum value for an object of type unsigned char */ +#define UCHAR_MAX 255 +#endif + +#ifndef SHRT_MIN +/* minimum value for an object of type short int */ +#define SHRT_MIN (-0x8000) +#endif + +#ifndef SHRT_MAX +/* maximum value for an object of type short int */ +#define SHRT_MAX 0x7fff +#endif + +#ifndef USHRT_MAX +/* maximum value for an object of type unsigned short int */ +#define USHRT_MAX 65535 +#endif + +#ifndef INT_MIN +/* minimum value for an object of type int */ +#define INT_MIN (~0x7fffffff) /* -2147483648 and 0x80000000 are unsigned */ +#endif + +#ifndef INT_MAX +/* maximum value for an object of type int */ +#define INT_MAX 0x7fffffff +#endif + +#ifndef UINT_MAX +/* maximum value for an object of type unsigned int */ +#define UINT_MAX 0xffffffffU +#endif + +#ifndef LONG_MIN +/* minimum value for an object of type long int */ +#define LONG_MIN (~0x7fffffffL) +#endif + +#ifndef LONG_MAX +/* maximum value for an object of type long int */ +#define LONG_MAX 0x7fffffffL +#endif + +#ifndef ULONG_MAX +/* maximum value for an object of type unsigned long int */ +#define ULONG_MAX 0xffffffffUL +#endif + +/* + * Ref Lib Global Variables + */ +extern float32_t scratchArray[]; +extern riscv_cfft_instance_f32 ref_cfft_sR_f32_len8192; + +/* + * Ref Lib Functions + */ + +/* + * Helper Functions + */ +q31_t ref_sat_n(q31_t num, uint32_t bits); + +q31_t ref_sat_q31(q63_t num); + +q15_t ref_sat_q15(q31_t num); + +q7_t ref_sat_q7(q15_t num); + +float32_t ref_pow(float32_t a, uint32_t b); + +extern float32_t tempMatrixArray[]; + +float32_t ref_detrm(float32_t *pSrc, float32_t *temp, uint32_t size); + +void ref_cofact(float32_t *pSrc, float32_t *pDst, float32_t *temp, + uint32_t size); + +float64_t ref_detrm64(float64_t *pSrc, float64_t *temp, uint32_t size); + +void ref_cofact64(float64_t *pSrc, float64_t *pDst, float64_t *temp, + uint32_t size); + +/* + * Basic Math Functions + */ +void ref_abs_f32(float32_t *pSrc, float32_t *pDst, uint32_t blockSize); + +void ref_abs_q31(q31_t *pSrc, q31_t *pDst, uint32_t blockSize); + +void ref_abs_q15(q15_t *pSrc, q15_t *pDst, uint32_t blockSize); + +void ref_abs_q7(q7_t *pSrc, q7_t *pDst, uint32_t blockSize); + +void ref_add_f32(float32_t *pSrcA, float32_t *pSrcB, float32_t *pDst, + uint32_t blockSize); + +void ref_add_q31(q31_t *pSrcA, q31_t *pSrcB, q31_t *pDst, uint32_t blockSize); + +void ref_add_q15(q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, uint32_t blockSize); + +void ref_add_q7(q7_t *pSrcA, q7_t *pSrcB, q7_t *pDst, uint32_t blockSize); + +void ref_dot_prod_f32(float32_t *pSrcA, float32_t *pSrcB, uint32_t blockSize, + float32_t *result); + +void ref_dot_prod_q31(q31_t *pSrcA, q31_t *pSrcB, uint32_t blockSize, + q63_t *result); + +void ref_dot_prod_q15(q15_t *pSrcA, q15_t *pSrcB, uint32_t blockSize, + q63_t *result); + +void ref_dot_prod_q7(q7_t *pSrcA, q7_t *pSrcB, uint32_t blockSize, + q31_t *result); + +void ref_mult_f32(float32_t *pSrcA, float32_t *pSrcB, float32_t *pDst, + uint32_t blockSize); + +void ref_mult_q31(q31_t *pSrcA, q31_t *pSrcB, q31_t *pDst, uint32_t blockSize); + +void ref_mult_q15(q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, uint32_t blockSize); + +void ref_mult_q7(q7_t *pSrcA, q7_t *pSrcB, q7_t *pDst, uint32_t blockSize); + +void ref_negate_f32(float32_t *pSrc, float32_t *pDst, uint32_t blockSize); + +void ref_negate_q31(q31_t *pSrc, q31_t *pDst, uint32_t blockSize); + +void ref_negate_q15(q15_t *pSrc, q15_t *pDst, uint32_t blockSize); + +void ref_negate_q7(q7_t *pSrc, q7_t *pDst, uint32_t blockSize); + +void ref_offset_f32(float32_t *pSrc, float32_t offset, float32_t *pDst, + uint32_t blockSize); + +void ref_offset_q31(q31_t *pSrc, q31_t offset, q31_t *pDst, uint32_t blockSize); + +void ref_offset_q15(q15_t *pSrc, q15_t offset, q15_t *pDst, uint32_t blockSize); + +void ref_offset_q7(q7_t *pSrc, q7_t offset, q7_t *pDst, uint32_t blockSize); + +void ref_scale_f32(float32_t *pSrc, float32_t scale, float32_t *pDst, + uint32_t blockSize); + +void ref_scale_q31(q31_t *pSrc, q31_t scaleFract, int8_t shift, q31_t *pDst, + uint32_t blockSize); + +void ref_scale_q15(q15_t *pSrc, q15_t scaleFract, int8_t shift, q15_t *pDst, + uint32_t blockSize); + +void ref_scale_q7(q7_t *pSrc, q7_t scaleFract, int8_t shift, q7_t *pDst, + uint32_t blockSize); + +void ref_shift_q31(q31_t *pSrc, int8_t shiftBits, q31_t *pDst, + uint32_t blockSize); + +void ref_shift_q15(q15_t *pSrc, int8_t shiftBits, q15_t *pDst, + uint32_t blockSize); + +void ref_shift_q7(q7_t *pSrc, int8_t shiftBits, q7_t *pDst, uint32_t blockSize); + +void ref_sub_f32(float32_t *pSrcA, float32_t *pSrcB, float32_t *pDst, + uint32_t blockSize); + +void ref_sub_q31(q31_t *pSrcA, q31_t *pSrcB, q31_t *pDst, uint32_t blockSize); + +void ref_sub_q15(q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, uint32_t blockSize); + +void ref_sub_q7(q7_t *pSrcA, q7_t *pSrcB, q7_t *pDst, uint32_t blockSize); + +void ref_clip_f32(const float32_t * pSrc, float32_t * pDst, float32_t low, float32_t high, uint32_t numSamples); + +void ref_clip_q7(const q7_t * pSrc, q7_t * pDst, q7_t low, q7_t high, uint32_t numSamples); + +void ref_clip_q15(const q15_t * pSrc, q15_t * pDst, q15_t low, q15_t high, uint32_t numSamples); + +void ref_clip_q31(const q31_t * pSrc, q31_t * pDst, q31_t low, q31_t high, uint32_t numSamples); + +void ref_and_u16(const uint16_t * pSrcA, const uint16_t * pSrcB, uint16_t * pDst, uint32_t blockSize); + +void ref_and_u32(const uint32_t * pSrcA, const uint32_t * pSrcB, uint32_t * pDst, uint32_t blockSize); + +void ref_and_u8(const uint8_t * pSrcA, const uint8_t * pSrcB, uint8_t * pDst, uint32_t blockSize); + +void ref_or_u16(const uint16_t * pSrcA, const uint16_t * pSrcB, uint16_t * pDst, uint32_t blockSize); + +void ref_or_u32(const uint32_t * pSrcA, const uint32_t * pSrcB, uint32_t * pDst, uint32_t blockSize); + +void ref_or_u8(const uint8_t * pSrcA, const uint8_t * pSrcB, uint8_t * pDst, uint32_t blockSize); + +void ref_not_u16(const uint16_t * pSrc, uint16_t * pDst, uint32_t blockSize); + +void ref_not_u32(const uint32_t * pSrc, uint32_t * pDst, uint32_t blockSize); + +void ref_not_u8(const uint8_t * pSrc, uint8_t * pDst, uint32_t blockSize); + +void ref_xor_u16(const uint16_t * pSrcA, const uint16_t * pSrcB, uint16_t * pDst, uint32_t blockSize); + +void ref_xor_u32(const uint32_t * pSrcA, const uint32_t * pSrcB, uint32_t * pDst, uint32_t blockSize); + +void ref_xor_u8(const uint8_t * pSrcA, const uint8_t * pSrcB, uint8_t * pDst, uint32_t blockSize); + +/* + * Complex Math Functions + */ +void ref_cmplx_conj_f32(float32_t *pSrc, float32_t *pDst, uint32_t numSamples); + +void ref_cmplx_conj_q31(q31_t *pSrc, q31_t *pDst, uint32_t numSamples); + +void ref_cmplx_conj_q15(q15_t *pSrc, q15_t *pDst, uint32_t numSamples); + +void ref_cmplx_dot_prod_f32(float32_t *pSrcA, float32_t *pSrcB, + uint32_t numSamples, float32_t *realResult, + float32_t *imagResult); + +void ref_cmplx_dot_prod_q31(q31_t *pSrcA, q31_t *pSrcB, uint32_t numSamples, + q63_t *realResult, q63_t *imagResult); + +void ref_cmplx_dot_prod_q15(q15_t *pSrcA, q15_t *pSrcB, uint32_t numSamples, + q31_t *realResult, q31_t *imagResult); + +void ref_cmplx_mag_f32(float32_t *pSrc, float32_t *pDst, uint32_t numSamples); + +void ref_cmplx_mag_q31(q31_t *pSrc, q31_t *pDst, uint32_t numSamples); + +void ref_cmplx_mag_q15(q15_t *pSrc, q15_t *pDst, uint32_t numSamples); + +void ref_cmplx_mag_squared_f32(float32_t *pSrc, float32_t *pDst, + uint32_t numSamples); + +void ref_cmplx_mag_squared_q31(q31_t *pSrc, q31_t *pDst, uint32_t numSamples); + +void ref_cmplx_mag_squared_q15(q15_t *pSrc, q15_t *pDst, uint32_t numSamples); + +void ref_cmplx_mult_cmplx_f32(float32_t *pSrcA, float32_t *pSrcB, + float32_t *pDst, uint32_t numSamples); + +void ref_cmplx_mult_cmplx_q31(q31_t *pSrcA, q31_t *pSrcB, q31_t *pDst, + uint32_t numSamples); + +void ref_cmplx_mult_cmplx_q15(q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, + uint32_t numSamples); + +void ref_cmplx_mult_real_f32(float32_t *pSrcCmplx, float32_t *pSrcReal, + float32_t *pCmplxDst, uint32_t numSamples); + +void ref_cmplx_mult_real_q31(q31_t *pSrcCmplx, q31_t *pSrcReal, + q31_t *pCmplxDst, uint32_t numSamples); + +void ref_cmplx_mult_real_q15(q15_t *pSrcCmplx, q15_t *pSrcReal, + q15_t *pCmplxDst, uint32_t numSamples); + +/* + * Controller Functions + */ +void ref_sin_cos_f32(float32_t theta, float32_t *pSinVal, float32_t *pCosVal); + +void ref_sin_cos_q31(q31_t theta, q31_t *pSinVal, q31_t *pCosVal); + +float32_t ref_pid_f32(riscv_pid_instance_f32 *S, float32_t in); + +q31_t ref_pid_q31(riscv_pid_instance_q31 *S, q31_t in); + +q15_t ref_pid_q15(riscv_pid_instance_q15 *S, q15_t in); + +/* + * Fast Math Functions + */ +#define ref_sin_f32(a) sinf(a) + +q31_t ref_sin_q31(q31_t x); + +q15_t ref_sin_q15(q15_t x); + +#define ref_cos_f32(a) cosf(a) + +q31_t ref_cos_q31(q31_t x); + +q15_t ref_cos_q15(q15_t x); + +riscv_status ref_sqrt_q31(q31_t in, q31_t *pOut); + +riscv_status ref_sqrt_q15(q15_t in, q15_t *pOut); + +riscv_status ref_divide_q15(q15_t numerator, q15_t denominator, q15_t *quotient, int16_t *shift); + +/* + * Filtering Functions + */ +void ref_biquad_cascade_df2T_f32(const riscv_biquad_cascade_df2T_instance_f32 *S, + float32_t *pSrc, float32_t *pDst, + uint32_t blockSize); + +void ref_biquad_cascade_stereo_df2T_f32( + const riscv_biquad_cascade_stereo_df2T_instance_f32 *S, float32_t *pSrc, + float32_t *pDst, uint32_t blockSize); + +void ref_biquad_cascade_df2T_f64(const riscv_biquad_cascade_df2T_instance_f64 *S, + float64_t *pSrc, float64_t *pDst, + uint32_t blockSize); + +void ref_biquad_cascade_df1_f32(const riscv_biquad_casd_df1_inst_f32 *S, + float32_t *pSrc, float32_t *pDst, + uint32_t blockSize); + +void ref_biquad_cas_df1_32x64_q31(const riscv_biquad_cas_df1_32x64_ins_q31 *S, + q31_t *pSrc, q31_t *pDst, uint32_t blockSize); + +void ref_biquad_cascade_df1_q31(const riscv_biquad_casd_df1_inst_q31 *S, + q31_t *pSrc, q31_t *pDst, uint32_t blockSize); + +void ref_biquad_cascade_df1_fast_q31(const riscv_biquad_casd_df1_inst_q31 *S, + q31_t *pSrc, q31_t *pDst, + uint32_t blockSize); + +void ref_biquad_cascade_df1_fast_q15(const riscv_biquad_casd_df1_inst_q15 *S, + q15_t *pSrc, q15_t *pDst, + uint32_t blockSize); + +void ref_biquad_cascade_df1_q15(const riscv_biquad_casd_df1_inst_q15 *S, + q15_t *pSrc, q15_t *pDst, uint32_t blockSize); + +void ref_conv_f32(float32_t *pSrcA, uint32_t srcALen, float32_t *pSrcB, + uint32_t srcBLen, float32_t *pDst); + +riscv_status ref_conv_partial_f32(float32_t *pSrcA, uint32_t srcALen, + float32_t *pSrcB, uint32_t srcBLen, + float32_t *pDst, uint32_t firstIndex, + uint32_t numPoints); + +void ref_conv_q31(q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, + uint32_t srcBLen, q31_t *pDst); + +void ref_conv_fast_q31(q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, + uint32_t srcBLen, q31_t *pDst); + +riscv_status ref_conv_partial_q31(q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, + uint32_t srcBLen, q31_t *pDst, + uint32_t firstIndex, uint32_t numPoints); + +riscv_status ref_conv_partial_fast_q31(q31_t *pSrcA, uint32_t srcALen, + q31_t *pSrcB, uint32_t srcBLen, + q31_t *pDst, uint32_t firstIndex, + uint32_t numPoints); + +void ref_conv_q15(q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, + uint32_t srcBLen, q15_t *pDst); + +#define ref_conv_opt_q15(pSrcA, srcALen, pSrcB, srcBLen, pDst, pScratch1, \ + pScratch2) \ + ref_conv_q15(pSrcA, srcALen, pSrcB, srcBLen, pDst) + +void ref_conv_fast_q15(q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, + uint32_t srcBLen, q15_t *pDst); + +void ref_conv_fast_opt_q15(q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, + uint32_t srcBLen, q15_t *pDst, q15_t *pScratch1, + q15_t *pScratch2); + +riscv_status ref_conv_partial_q15(q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, + uint32_t srcBLen, q15_t *pDst, + uint32_t firstIndex, uint32_t numPoints); + +#define ref_conv_partial_opt_q15(pSrcA, srcALen, pSrcB, srcBLen, pDst, \ + firstIndex, numPoints, pScratch1, pScratch2) \ + ref_conv_partial_q15(pSrcA, srcALen, pSrcB, srcBLen, pDst, firstIndex, \ + numPoints) + +riscv_status ref_conv_partial_fast_q15(q15_t *pSrcA, uint32_t srcALen, + q15_t *pSrcB, uint32_t srcBLen, + q15_t *pDst, uint32_t firstIndex, + uint32_t numPoints); + +riscv_status ref_conv_partial_fast_opt_q15(q15_t *pSrcA, uint32_t srcALen, + q15_t *pSrcB, uint32_t srcBLen, + q15_t *pDst, uint32_t firstIndex, + uint32_t numPoints, q15_t *pScratch1, + q15_t *pScratch2); + +void ref_conv_q7(q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, uint32_t srcBLen, + q7_t *pDst); + +#define ref_conv_opt_q7(pSrcA, srcALen, pSrcB, srcBLen, pDst, pScratch1, \ + pScratch2) \ + ref_conv_q7(pSrcA, srcALen, pSrcB, srcBLen, pDst) + +riscv_status ref_conv_partial_q7(q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, + uint32_t srcBLen, q7_t *pDst, + uint32_t firstIndex, uint32_t numPoints); + +#define ref_conv_partial_opt_q7(pSrcA, srcALen, pSrcB, srcBLen, pDst, \ + firstIndex, numPoints, pScratch1, pScratch2) \ + ref_conv_partial_q7(pSrcA, srcALen, pSrcB, srcBLen, pDst, firstIndex, \ + numPoints) + +void ref_correlate_f32(float32_t *pSrcA, uint32_t srcALen, float32_t *pSrcB, + uint32_t srcBLen, float32_t *pDst); + +void ref_correlate_q31(q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, + uint32_t srcBLen, q31_t *pDst); + +void ref_correlate_fast_q31(q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, + uint32_t srcBLen, q31_t *pDst); + +void ref_correlate_q15(q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, + uint32_t srcBLen, q15_t *pDst); + +#define ref_correlate_opt_q15(pSrcA, srcALen, pSrcB, srcBLen, pDst, pScratch1) \ + ref_correlate_q15(pSrcA, srcALen, pSrcB, srcBLen, pDst) + +void ref_correlate_fast_q15(q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, + uint32_t srcBLen, q15_t *pDst); + +void ref_correlate_fast_opt_q15(q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, + uint32_t srcBLen, q15_t *pDst, q15_t *pScratch); + +void ref_correlate_q7(q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, + uint32_t srcBLen, q7_t *pDst); + +#define ref_correlate_opt_q7(pSrcA, srcALen, pSrcB, srcBLen, pDst, pScratch1, \ + pScratch2) \ + ref_correlate_q7(pSrcA, srcALen, pSrcB, srcBLen, pDst) + +void ref_fir_f32(const riscv_fir_instance_f32 *S, float32_t *pSrc, + float32_t *pDst, uint32_t blockSize); + +void ref_fir_q31(const riscv_fir_instance_q31 *S, q31_t *pSrc, q31_t *pDst, + uint32_t blockSize); + +void ref_fir_fast_q31(const riscv_fir_instance_q31 *S, q31_t *pSrc, q31_t *pDst, + uint32_t blockSize); + +void ref_fir_q15(const riscv_fir_instance_q15 *S, q15_t *pSrc, q15_t *pDst, + uint32_t blockSize); + +void ref_fir_fast_q15(const riscv_fir_instance_q15 *S, q15_t *pSrc, q15_t *pDst, + uint32_t blockSize); + +void ref_fir_q7(const riscv_fir_instance_q7 *S, q7_t *pSrc, q7_t *pDst, + uint32_t blockSize); + +void ref_fir_decimate_f32(const riscv_fir_decimate_instance_f32 *S, + float32_t *pSrc, float32_t *pDst, uint32_t blockSize); + +void ref_fir_decimate_q31(const riscv_fir_decimate_instance_q31 *S, q31_t *pSrc, + q31_t *pDst, uint32_t blockSize); + +void ref_fir_decimate_fast_q31(const riscv_fir_decimate_instance_q31 *S, + q31_t *pSrc, q31_t *pDst, uint32_t blockSize); + +void ref_fir_decimate_q15(const riscv_fir_decimate_instance_q15 *S, q15_t *pSrc, + q15_t *pDst, uint32_t blockSize); + +void ref_fir_decimate_fast_q15(const riscv_fir_decimate_instance_q15 *S, + q15_t *pSrc, q15_t *pDst, uint32_t blockSize); + +void ref_fir_lattice_f32(const riscv_fir_lattice_instance_f32 *S, float32_t *pSrc, + float32_t *pDst, uint32_t blockSize); + +void ref_fir_lattice_q31(const riscv_fir_lattice_instance_q31 *S, q31_t *pSrc, + q31_t *pDst, uint32_t blockSize); + +void ref_fir_lattice_q15(const riscv_fir_lattice_instance_q15 *S, q15_t *pSrc, + q15_t *pDst, uint32_t blockSize); + +void ref_fir_sparse_f32(riscv_fir_sparse_instance_f32 *S, float32_t *pSrc, + float32_t *pDst, float32_t *pScratchIn, + uint32_t blockSize); + +void ref_fir_sparse_q31(riscv_fir_sparse_instance_q31 *S, q31_t *pSrc, + q31_t *pDst, q31_t *pScratchIn, uint32_t blockSize); + +void ref_fir_sparse_q15(riscv_fir_sparse_instance_q15 *S, q15_t *pSrc, + q15_t *pDst, q15_t *pScratchIn, q31_t *pScratchOut, + uint32_t blockSize); + +void ref_fir_sparse_q7(riscv_fir_sparse_instance_q7 *S, q7_t *pSrc, q7_t *pDst, + q7_t *pScratchIn, q31_t *pScratchOut, + uint32_t blockSize); + +void ref_iir_lattice_f32(const riscv_iir_lattice_instance_f32 *S, float32_t *pSrc, + float32_t *pDst, uint32_t blockSize); + +void ref_iir_lattice_q31(const riscv_iir_lattice_instance_q31 *S, q31_t *pSrc, + q31_t *pDst, uint32_t blockSize); + +void ref_iir_lattice_q15(const riscv_iir_lattice_instance_q15 *S, q15_t *pSrc, + q15_t *pDst, uint32_t blockSize); + +void ref_lms_f32(const riscv_lms_instance_f32 *S, float32_t *pSrc, + float32_t *pRef, float32_t *pOut, float32_t *pErr, + uint32_t blockSize); + +void ref_lms_norm_f32(riscv_lms_norm_instance_f32 *S, float32_t *pSrc, + float32_t *pRef, float32_t *pOut, float32_t *pErr, + uint32_t blockSize); + +void ref_lms_q31(const riscv_lms_instance_q31 *S, q31_t *pSrc, q31_t *pRef, + q31_t *pOut, q31_t *pErr, uint32_t blockSize); + +void ref_lms_norm_q31(riscv_lms_norm_instance_q31 *S, q31_t *pSrc, q31_t *pRef, + q31_t *pOut, q31_t *pErr, uint32_t blockSize); + +void ref_lms_q15(const riscv_lms_instance_q15 *S, q15_t *pSrc, q15_t *pRef, + q15_t *pOut, q15_t *pErr, uint32_t blockSize); + +void ref_lms_norm_q15(riscv_lms_norm_instance_q15 *S, q15_t *pSrc, q15_t *pRef, + q15_t *pOut, q15_t *pErr, uint32_t blockSize); + +void ref_fir_interpolate_f32(const riscv_fir_interpolate_instance_f32 *S, + float32_t *pSrc, float32_t *pDst, + uint32_t blockSize); + +void ref_fir_interpolate_q31(const riscv_fir_interpolate_instance_q31 *S, + q31_t *pSrc, q31_t *pDst, uint32_t blockSize); + +void ref_fir_interpolate_q15(const riscv_fir_interpolate_instance_q15 *S, + q15_t *pSrc, q15_t *pDst, uint32_t blockSize); + +/* + * Matrix Functions + */ +riscv_status ref_mat_cmplx_mult_f32(const riscv_matrix_instance_f32 *pSrcA, + const riscv_matrix_instance_f32 *pSrcB, + riscv_matrix_instance_f32 *pDst); + +riscv_status ref_mat_cmplx_mult_q31(const riscv_matrix_instance_q31 *pSrcA, + const riscv_matrix_instance_q31 *pSrcB, + riscv_matrix_instance_q31 *pDst); + +riscv_status ref_mat_cmplx_mult_q15(const riscv_matrix_instance_q15 *pSrcA, + const riscv_matrix_instance_q15 *pSrcB, + riscv_matrix_instance_q15 *pDst); + +riscv_status ref_mat_inverse_f32(const riscv_matrix_instance_f32 *pSrc, + riscv_matrix_instance_f32 *pDst); + +riscv_status ref_mat_inverse_f64(const riscv_matrix_instance_f64 *pSrc, + riscv_matrix_instance_f64 *pDst); + +riscv_status ref_mat_mult_f32(const riscv_matrix_instance_f32 *pSrcA, + const riscv_matrix_instance_f32 *pSrcB, + riscv_matrix_instance_f32 *pDst); + +riscv_status ref_mat_mult_q31(const riscv_matrix_instance_q31 *pSrcA, + const riscv_matrix_instance_q31 *pSrcB, + riscv_matrix_instance_q31 *pDst); + +/* Alias for testing purposes*/ +#define ref_mat_mult_fast_q31 ref_mat_mult_q31 + +riscv_status ref_mat_mult_q15(const riscv_matrix_instance_q15 *pSrcA, + const riscv_matrix_instance_q15 *pSrcB, + riscv_matrix_instance_q15 *pDst); + +/* Alias for testing purposes*/ +#define ref_mat_mult_fast_q15 ref_mat_mult_q15 + +riscv_status ref_mat_scale_f32(const riscv_matrix_instance_f32 *pSrc, + float32_t scale, riscv_matrix_instance_f32 *pDst); + +riscv_status ref_mat_scale_q31(const riscv_matrix_instance_q31 *pSrc, q31_t scale, + int32_t shift, riscv_matrix_instance_q31 *pDst); + +riscv_status ref_mat_scale_q15(const riscv_matrix_instance_q15 *pSrc, q15_t scale, + int32_t shift, riscv_matrix_instance_q15 *pDst); + +riscv_status ref_mat_sub_f32(const riscv_matrix_instance_f32 *pSrcA, + const riscv_matrix_instance_f32 *pSrcB, + riscv_matrix_instance_f32 *pDst); + +riscv_status ref_mat_sub_q31(const riscv_matrix_instance_q31 *pSrcA, + const riscv_matrix_instance_q31 *pSrcB, + riscv_matrix_instance_q31 *pDst); + +riscv_status ref_mat_sub_q15(const riscv_matrix_instance_q15 *pSrcA, + const riscv_matrix_instance_q15 *pSrcB, + riscv_matrix_instance_q15 *pDst); + +riscv_status ref_mat_trans_f64(const riscv_matrix_instance_f64 *pSrc, + riscv_matrix_instance_f64 *pDst); + +riscv_status ref_mat_trans_f32(const riscv_matrix_instance_f32 *pSrc, + riscv_matrix_instance_f32 *pDst); + +riscv_status ref_mat_trans_q31(const riscv_matrix_instance_q31 *pSrc, + riscv_matrix_instance_q31 *pDst); + +riscv_status ref_mat_trans_q15(const riscv_matrix_instance_q15 *pSrc, + riscv_matrix_instance_q15 *pDst); + +riscv_status ref_mat_add_f32(const riscv_matrix_instance_f32 *pSrcA, + const riscv_matrix_instance_f32 *pSrcB, + riscv_matrix_instance_f32 *pDst); + +riscv_status ref_mat_add_q31(const riscv_matrix_instance_q31 *pSrcA, + const riscv_matrix_instance_q31 *pSrcB, + riscv_matrix_instance_q31 *pDst); + +riscv_status ref_mat_add_q15(const riscv_matrix_instance_q15 *pSrcA, + const riscv_matrix_instance_q15 *pSrcB, + riscv_matrix_instance_q15 *pDst); + +/* + * Statistics Functions + */ +void ref_max_f32(float32_t *pSrc, uint32_t blockSize, float32_t *pResult, + uint32_t *pIndex); +void ref_max_no_idx_f32(float32_t * pSrc, uint32_t blockSize, float32_t * pResult); + +void ref_max_q31(q31_t *pSrc, uint32_t blockSize, q31_t *pResult, + uint32_t *pIndex); + +void ref_max_q15(q15_t *pSrc, uint32_t blockSize, q15_t *pResult, + uint32_t *pIndex); + +void ref_max_q7(q7_t *pSrc, uint32_t blockSize, q7_t *pResult, + uint32_t *pIndex); + +void ref_mean_f32(float32_t *pSrc, uint32_t blockSize, float32_t *pResult); + +void ref_mean_q31(q31_t *pSrc, uint32_t blockSize, q31_t *pResult); + +void ref_mean_q15(q15_t *pSrc, uint32_t blockSize, q15_t *pResult); + +void ref_mean_q7(q7_t *pSrc, uint32_t blockSize, q7_t *pResult); + +void ref_min_f32(float32_t *pSrc, uint32_t blockSize, float32_t *pResult, + uint32_t *pIndex); + +void ref_min_q31(q31_t *pSrc, uint32_t blockSize, q31_t *pResult, + uint32_t *pIndex); + +void ref_min_q15(q15_t *pSrc, uint32_t blockSize, q15_t *pResult, + uint32_t *pIndex); + +void ref_min_q7(q7_t *pSrc, uint32_t blockSize, q7_t *pResult, + uint32_t *pIndex); + +void ref_power_f32(float32_t *pSrc, uint32_t blockSize, float32_t *pResult); + +void ref_power_q31(q31_t *pSrc, uint32_t blockSize, q63_t *pResult); + +void ref_power_q15(q15_t *pSrc, uint32_t blockSize, q63_t *pResult); + +void ref_power_q7(q7_t *pSrc, uint32_t blockSize, q31_t *pResult); + +void ref_rms_f32(float32_t *pSrc, uint32_t blockSize, float32_t *pResult); + +void ref_rms_q31(q31_t *pSrc, uint32_t blockSize, q31_t *pResult); + +void ref_rms_q15(q15_t *pSrc, uint32_t blockSize, q15_t *pResult); + +void ref_std_f32(float32_t *pSrc, uint32_t blockSize, float32_t *pResult); + +void ref_std_q31(q31_t *pSrc, uint32_t blockSize, q31_t *pResult); + +void ref_std_q15(q15_t *pSrc, uint32_t blockSize, q15_t *pResult); + +void ref_var_f32(float32_t *pSrc, uint32_t blockSize, float32_t *pResult); + +void ref_var_q31(q31_t *pSrc, uint32_t blockSize, q31_t *pResult); + +void ref_var_q15(q15_t *pSrc, uint32_t blockSize, q15_t *pResult); + +/* + * Support Functions + */ +void ref_copy_f32(float32_t *pSrc, float32_t *pDst, uint32_t blockSize); + +void ref_copy_q31(q31_t *pSrc, q31_t *pDst, uint32_t blockSize); + +void ref_copy_q15(q15_t *pSrc, q15_t *pDst, uint32_t blockSize); + +void ref_copy_q7(q7_t *pSrc, q7_t *pDst, uint32_t blockSize); + +void ref_fill_f32(float32_t value, float32_t *pDst, uint32_t blockSize); + +void ref_fill_q31(q31_t value, q31_t *pDst, uint32_t blockSize); + +void ref_fill_q15(q15_t value, q15_t *pDst, uint32_t blockSize); + +void ref_fill_q7(q7_t value, q7_t *pDst, uint32_t blockSize); + +void ref_q31_to_q15(q31_t *pSrc, q15_t *pDst, uint32_t blockSize); + +void ref_q31_to_q7(q31_t *pSrc, q7_t *pDst, uint32_t blockSize); + +void ref_q15_to_q31(q15_t *pSrc, q31_t *pDst, uint32_t blockSize); + +void ref_q15_to_q7(q15_t *pSrc, q7_t *pDst, uint32_t blockSize); + +void ref_q7_to_q31(q7_t *pSrc, q31_t *pDst, uint32_t blockSize); + +void ref_q7_to_q15(q7_t *pSrc, q15_t *pDst, uint32_t blockSize); + +void ref_q63_to_float(q63_t *pSrc, float32_t *pDst, uint32_t blockSize); + +void ref_q31_to_float(q31_t *pSrc, float32_t *pDst, uint32_t blockSize); + +void ref_q15_to_float(q15_t *pSrc, float32_t *pDst, uint32_t blockSize); + +void ref_q7_to_float(q7_t *pSrc, float32_t *pDst, uint32_t blockSize); + +void ref_float_to_q31(float32_t *pSrc, q31_t *pDst, uint32_t blockSize); + +void ref_float_to_q15(float32_t *pSrc, q15_t *pDst, uint32_t blockSize); + +void ref_float_to_q7(float32_t *pSrc, q7_t *pDst, uint32_t blockSize); + +/* + * Transform Functions + */ +void ref_cfft_f32(const riscv_cfft_instance_f32 *S, float32_t *p1, + uint8_t ifftFlag, uint8_t bitReverseFlag); + +void ref_cfft_q31(const riscv_cfft_instance_q31 *S, q31_t *p1, uint8_t ifftFlag, + uint8_t bitReverseFlag); + +void ref_cfft_q15(const riscv_cfft_instance_q15 *S, q15_t *p1, uint8_t ifftFlag, + uint8_t bitReverseFlag); + +void ref_cfft_radix2_f32(const riscv_cfft_radix2_instance_f32 *S, + float32_t *pSrc); + +void ref_cfft_radix2_q31(const riscv_cfft_radix2_instance_q31 *S, q31_t *pSrc); + +void ref_cfft_radix2_q15(const riscv_cfft_radix2_instance_q15 *S, q15_t *pSrc); + +void ref_cfft_radix4_f32(const riscv_cfft_radix4_instance_f32 *S, + float32_t *pSrc); + +void ref_cfft_radix4_q31(const riscv_cfft_radix4_instance_q31 *S, q31_t *pSrc); + +void ref_cfft_radix4_q15(const riscv_cfft_radix4_instance_q15 *S, q15_t *pSrc); + +void ref_rfft_f32(riscv_rfft_instance_f32 *S, float32_t *pSrc, float32_t *pDst); + +void ref_rfft_fast_f32(riscv_rfft_fast_instance_f32 *S, float32_t *p, + float32_t *pOut, uint8_t ifftFlag); + +void ref_rfft_q31(const riscv_rfft_instance_q31 *S, q31_t *pSrc, q31_t *pDst); + +void ref_rfft_q15(const riscv_rfft_instance_q15 *S, q15_t *pSrc, q15_t *pDst); + +void ref_dct4_f32(const riscv_dct4_instance_f32 *S, float32_t *pState, + float32_t *pInlineBuffer); + +void ref_dct4_q31(const riscv_dct4_instance_q31 *S, q31_t *pState, + q31_t *pInlineBuffer); + +void ref_dct4_q15(const riscv_dct4_instance_q15 *S, q15_t *pState, + q15_t *pInlineBuffer); + + + + + + + + + + + + + +/* + * Intrinsics + */ +q31_t ref__QADD8(q31_t x, q31_t y); +q31_t ref__QSUB8(q31_t x, q31_t y); +q31_t ref__QADD16(q31_t x, q31_t y); +q31_t ref__SHADD16(q31_t x, q31_t y); +q31_t ref__QSUB16(q31_t x, q31_t y); +q31_t ref__SHSUB16(q31_t x, q31_t y); +q31_t ref__QASX(q31_t x, q31_t y); +q31_t ref__SHASX(q31_t x, q31_t y); +q31_t ref__QSAX(q31_t x, q31_t y); +q31_t ref__SHSAX(q31_t x, q31_t y); +q31_t ref__SMUSDX(q31_t x, q31_t y); +q31_t ref__SMUADX(q31_t x, q31_t y); +q31_t ref__QADD(q31_t x, q31_t y); +q31_t ref__QSUB(q31_t x, q31_t y); +q31_t ref__SMLAD(q31_t x, q31_t y, q31_t sum); +q31_t ref__SMLADX(q31_t x, q31_t y, q31_t sum); +q31_t ref__SMLSDX(q31_t x, q31_t y, q31_t sum); +q63_t ref__SMLALD(q31_t x, q31_t y, q63_t sum); +q63_t ref__SMLALDX(q31_t x, q31_t y, q63_t sum); +q31_t ref__SMUAD(q31_t x, q31_t y); +q31_t ref__SMUSD(q31_t x, q31_t y); +q31_t ref__SXTB16(q31_t x); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/examples/nn/MFCC/CMakeLists.txt b/examples/nn/MFCC/CMakeLists.txt new file mode 100644 index 00000000..247f5e15 --- /dev/null +++ b/examples/nn/MFCC/CMakeLists.txt @@ -0,0 +1,7 @@ +set(mains main.cc) +set(BSP_COMMON_DIR ${CMAKE_SOURCE_DIR}/bsp/bsp_common) +set(TARGET_REQUIRED_SRCS ${BSP_COMMON_DIR}/platform/cpp_new.cpp ) +set(TARGET_REQUIRED_LIBS nmsis) +set(TARGET_REQUIRED_PRIVATE_INCLUDE ${CMAKE_CURRENT_SOURCE_DIR}) +generate_bin() + diff --git a/examples/nn/MFCC/main.cc b/examples/nn/MFCC/main.cc new file mode 100644 index 00000000..292315f5 --- /dev/null +++ b/examples/nn/MFCC/main.cc @@ -0,0 +1,228 @@ +/* + * Copyright (C) 2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * Description: MFCC feature extraction to match with TensorFlow MFCC Op + */ + +#include + +#include "mfcc.h" +#include "float.h" + +#include + +#include "mfcc.h" +#include "float.h" + +#include "bflb_platform.h" +#include "hal_uart.h" +#include "hal_mtimer.h" + +MFCC::MFCC(int num_mfcc_features, int frame_len, int mfcc_dec_bits) + : num_mfcc_features(num_mfcc_features), + frame_len(frame_len), + mfcc_dec_bits(mfcc_dec_bits) +{ + // Round-up to nearest power of 2. + frame_len_padded = pow(2, ceil((log(frame_len) / log(2)))); + + frame = new float[frame_len_padded]; + buffer = new float[frame_len_padded]; + mel_energies = new float[NUM_FBANK_BINS]; + + //create window function + window_func = new float[frame_len]; + for (int i = 0; i < frame_len; i++) + window_func[i] = 0.5 - 0.5 * cos(M_2PI * ((float)i) / (frame_len)); + + //create mel filterbank + fbank_filter_first = new int32_t[NUM_FBANK_BINS]; + fbank_filter_last = new int32_t[NUM_FBANK_BINS]; + + mel_fbank = create_mel_fbank(); + + //create DCT matrix + dct_matrix = create_dct_matrix(NUM_FBANK_BINS, num_mfcc_features); + + //initialize FFT + rfft = new riscv_rfft_fast_instance_f32; + riscv_rfft_fast_init_f32(rfft, frame_len_padded); +} + +MFCC::~MFCC() +{ + delete[] frame; + delete[] buffer; + delete[] mel_energies; + delete[] window_func; + delete[] fbank_filter_first; + delete[] fbank_filter_last; + delete[] dct_matrix; + delete rfft; + for (int i = 0; i < NUM_FBANK_BINS; i++) + delete mel_fbank[i]; + delete mel_fbank; +} + +float *MFCC::create_dct_matrix(int32_t input_length, int32_t coefficient_count) +{ + int32_t k, n; + float *M = new float[input_length * coefficient_count]; + float normalizer; + riscv_sqrt_f32(2.0 / (float)input_length, &normalizer); + for (k = 0; k < coefficient_count; k++) { + for (n = 0; n < input_length; n++) { + M[k * input_length + n] = normalizer * cos(((double)M_PI) / input_length * (n + 0.5) * k); + } + } + return M; +} + +float **MFCC::create_mel_fbank() +{ + int32_t bin, i; + + int32_t num_fft_bins = frame_len_padded / 2; + float fft_bin_width = ((float)SAMP_FREQ) / frame_len_padded; + float mel_low_freq = MelScale(MEL_LOW_FREQ); + float mel_high_freq = MelScale(MEL_HIGH_FREQ); + float mel_freq_delta = (mel_high_freq - mel_low_freq) / (NUM_FBANK_BINS + 1); + + float *this_bin = new float[num_fft_bins]; + + float **mel_fbank = new float *[NUM_FBANK_BINS]; + + for (bin = 0; bin < NUM_FBANK_BINS; bin++) { + float left_mel = mel_low_freq + bin * mel_freq_delta; + float center_mel = mel_low_freq + (bin + 1) * mel_freq_delta; + float right_mel = mel_low_freq + (bin + 2) * mel_freq_delta; + + int32_t first_index = -1, last_index = -1; + + for (i = 0; i < num_fft_bins; i++) { + float freq = (fft_bin_width * i); // center freq of this fft bin. + float mel = MelScale(freq); + this_bin[i] = 0.0; + + if (mel > left_mel && mel < right_mel) { + float weight; + if (mel <= center_mel) { + weight = (mel - left_mel) / (center_mel - left_mel); + } else { + weight = (right_mel - mel) / (right_mel - center_mel); + } + this_bin[i] = weight; + if (first_index == -1) + first_index = i; + last_index = i; + } + } + fbank_filter_first[bin] = first_index; + fbank_filter_last[bin] = last_index; + mel_fbank[bin] = new float[last_index - first_index + 1]; + int32_t j = 0; + //copy the part we care about + for (i = first_index; i <= last_index; i++) { + mel_fbank[bin][j++] = this_bin[i]; + }; + } + delete[] this_bin; + return mel_fbank; +} + +void MFCC::mfcc_compute(const int16_t *audio_data, q7_t *mfcc_out) +{ + int32_t i, j, bin; + + //TensorFlow way of normalizing .wav data to (-1,1) + for (i = 0; i < frame_len; i++) { + frame[i] = (float)audio_data[i] / (1 << 15); + } + //Fill up remaining with zeros + memset(&frame[frame_len], 0, sizeof(float) * (frame_len_padded - frame_len)); + + for (i = 0; i < frame_len; i++) { + frame[i] *= window_func[i]; + } + + //Compute FFT + riscv_rfft_fast_f32(rfft, frame, buffer, 0); + + //Convert to power spectrum + //frame is stored as [real0, realN/2-1, real1, im1, real2, im2, ...] + int32_t half_dim = frame_len_padded / 2; + float first_energy = buffer[0] * buffer[0], + last_energy = buffer[1] * buffer[1]; // handle this special case + for (i = 1; i < half_dim; i++) { + float real = buffer[i * 2], im = buffer[i * 2 + 1]; + buffer[i] = real * real + im * im; + } + buffer[0] = first_energy; + buffer[half_dim] = last_energy; + + float sqrt_data; + //Apply mel filterbanks + for (bin = 0; bin < NUM_FBANK_BINS; bin++) { + j = 0; + float mel_energy = 0; + int32_t first_index = fbank_filter_first[bin]; + int32_t last_index = fbank_filter_last[bin]; + for (i = first_index; i <= last_index; i++) { + riscv_sqrt_f32(buffer[i], &sqrt_data); + mel_energy += (sqrt_data)*mel_fbank[bin][j++]; + } + mel_energies[bin] = mel_energy; + + //avoid log of zero + if (mel_energy == 0.0) + mel_energies[bin] = FLT_MIN; + } + + //Take log + for (bin = 0; bin < NUM_FBANK_BINS; bin++) + mel_energies[bin] = logf(mel_energies[bin]); + + //Take DCT. Uses matrix mul. + for (i = 0; i < num_mfcc_features; i++) { + float sum = 0.0; + for (j = 0; j < NUM_FBANK_BINS; j++) { + sum += dct_matrix[i * NUM_FBANK_BINS + j] * mel_energies[j]; + } + + //Input is Qx.mfcc_dec_bits (from quantization step) + sum *= (0x1 << mfcc_dec_bits); + sum = round(sum); + if (sum >= 127) + mfcc_out[i] = 127; + else if (sum <= -128) + mfcc_out[i] = -128; + else + mfcc_out[i] = sum; + } +} +int main() +{ + bflb_platform_init(0); + + MFCC *mfcc = new MFCC(100, 100, 100); + + MSG("MFCC Create Success! MFCC handle is 0x%x\r\n", mfcc); + + return 0; +} \ No newline at end of file diff --git a/examples/nn/MFCC/mfcc.h b/examples/nn/MFCC/mfcc.h new file mode 100644 index 00000000..d9773745 --- /dev/null +++ b/examples/nn/MFCC/mfcc.h @@ -0,0 +1,66 @@ +/* + * Copyright (C) 2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __KWS_MFCC_H__ +#define __KWS_MFCC_H__ + +#include "riscv_math.h" +#include "string.h" + +#define SAMP_FREQ 16000 +#define NUM_FBANK_BINS 40 +#define MEL_LOW_FREQ 20 +#define MEL_HIGH_FREQ 4000 + +#define M_2PI 6.283185307179586476925286766559005 +#define M_PI 3.14159265358979323846 +class MFCC { +private: + int num_mfcc_features; + int frame_len; + int frame_len_padded; + int mfcc_dec_bits; + float *frame; + float *buffer; + float *mel_energies; + float *window_func; + int32_t *fbank_filter_first; + int32_t *fbank_filter_last; + float **mel_fbank; + float *dct_matrix; + riscv_rfft_fast_instance_f32 *rfft; + float *create_dct_matrix(int32_t input_length, int32_t coefficient_count); + float **create_mel_fbank(); + + static inline float InverseMelScale(float mel_freq) + { + return 700.0f * (expf(mel_freq / 1127.0f) - 1.0f); + } + + static inline float MelScale(float freq) + { + return 1127.0f * logf(1.0f + freq / 700.0f); + } + +public: + MFCC(int num_mfcc_features, int frame_len, int mfcc_dec_bits); + ~MFCC(); + void mfcc_compute(const int16_t *data, q7_t *mfcc_out); +}; + +#endif \ No newline at end of file diff --git a/examples/nn/Readme.md b/examples/nn/Readme.md new file mode 100644 index 00000000..7a6bc1d9 --- /dev/null +++ b/examples/nn/Readme.md @@ -0,0 +1,51 @@ + +# Bouffalo Lab Microcontroller Software Interface Standard + +The **NMSIS** is a vendor-independent hardware abstraction layer for micro-controllers that are based on Bl70x Serial processors. + +The **NMSIS** defines generic tool interfaces and enables consistent device support. +It provides simple software interfaces to the processor and the peripherals, simplifying software re-use, reducing the learning +curve for micro-controller developers, and reducing the time to market for new devices. + +## NMSIS Componments + +* **NMSIS CORE** + + All Risc-V Class Processors Standardized API for the Bouffalo Lab processor core and peripherals. + +* **NMSIS DSP** + + All Bouffalo Lab Bl70x Class Processors DSP library collection with a lot of functions for various data types: + fixed-point (fractional q7, q15, q31) and single precision floating-point (32-bit). + Implementations optimized for the Bl70x processor core which has RISC-V SIMD instruction set. + +* **NMSIS NN** + + All Bouffalo Lab Bl70x Class Processors Collection of efficient neural network kernels developed to maximize + the performance and minimize the memory footprint Bouffalo Lab Bl70x processor core. + +## Directory Structure + +| Directory | Content | +|:-------------------------- |:--------------------------------------------------------- | +| components/nmsis/core | NMSIS-Core related files | +| components/NMSIS/DSP | NMSIS-DSP related files | +| components/NMSIS/NN | NMSIS-NN related files | +| examples/dsp | dsp examples | +| examples/nn | nn examples | +| examples/mfcc | mfcc compile examples | + +## Build Command + +In the bl_mcu_sdk root directory, input +`` make APP=BasicMathFunctions_part1 `` + +BasicMathFunctions_part1 is project foldor name which is placed in examples/dsp or examples/nn. +User can replace APP=xxx to change build target. + + +## License + +This NMSIS is modified based on open-source project CMSIS to match Boufflao Lab requirements. +This project transplant NMSIS into bl_mcu_sdk structure for Bouffalo Lab Device Adapting. +NMSIS is licensed under Apache-2.0. diff --git a/examples/nn/nnTest/CMakeLists.txt b/examples/nn/nnTest/CMakeLists.txt new file mode 100644 index 00000000..c2dfb3cf --- /dev/null +++ b/examples/nn/nnTest/CMakeLists.txt @@ -0,0 +1,11 @@ +set(mains main.cc) +set(BSP_COMMON_DIR ${CMAKE_SOURCE_DIR}/bsp/bsp_common) + +file(GLOB_RECURSE ref +"${CMAKE_CURRENT_SOURCE_DIR}/Ref_Implementations/*.c" +) +set(TARGET_REQUIRED_SRCS ${BSP_COMMON_DIR}/platform/cpp_new.cpp ${ref}) +set(TARGET_REQUIRED_LIBS nmsis) +set(TARGET_REQUIRED_PRIVATE_INCLUDE ${CMAKE_CURRENT_SOURCE_DIR}/Ref_Implementations) +generate_bin() + diff --git a/examples/nn/nnTest/Ref_Implementations/ActivationFunctions/riscv_nn_activations_q15_ref.c b/examples/nn/nnTest/Ref_Implementations/ActivationFunctions/riscv_nn_activations_q15_ref.c new file mode 100644 index 00000000..12230ded --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/ActivationFunctions/riscv_nn_activations_q15_ref.c @@ -0,0 +1,97 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_nn_activations_q15.c + * Description: Q15 neural network activation function using direct table look-up + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "riscv_nn_tables.h" +#include "ref_functions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Acti + * @{ + */ + +/** + * @brief neural network activation function using direct table look-up + * + * @note Refer header file for details. + * + */ + +void riscv_nn_activations_direct_q15_ref(q15_t * data, uint16_t size, uint16_t int_width, riscv_nn_activation_type type) +{ + uint16_t i = size; + q15_t *pIn = data; + q15_t *pOut = data; + uint16_t shift_size = 8 + 3 - int_width; + uint32_t bit_mask = 0x7FF >> int_width; + uint32_t full_frac = bit_mask + 1; + const q15_t *lookup_table; + + switch (type) + { + case RISCV_SIGMOID: + lookup_table = sigmoidTable_q15; + break; + case RISCV_TANH: + default: + lookup_table = tanhTable_q15; + break; + } + + while (i) + { + q15_t out; + q15_t in = *pIn++; + q15_t frac = (uint32_t) in & bit_mask; + q15_t value = lookup_table[(uint8_t)(in >> shift_size)]; + if ((in >> shift_size) != 0x7f) + { + q15_t value2 = lookup_table[(uint8_t)(1 + ((uint8_t)(in >> shift_size)))]; + /* doing the interpolation here for better accuracy */ + out = ((q31_t) (full_frac - frac) * value + (q31_t) value2 * frac) >> shift_size; + } else + { + /* the largest positive value does not have a right side for linear interpolation */ + out = value; + } + + *pOut++ = out; + i--; + } + +} + +/** + * @} end of Acti group + */ diff --git a/examples/nn/nnTest/Ref_Implementations/ActivationFunctions/riscv_nn_activations_q7_ref.c b/examples/nn/nnTest/Ref_Implementations/ActivationFunctions/riscv_nn_activations_q7_ref.c new file mode 100644 index 00000000..69c93c43 --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/ActivationFunctions/riscv_nn_activations_q7_ref.c @@ -0,0 +1,89 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_nn_activations_q7.c + * Description: Q7 neural network activation function using direct table look-up + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "riscv_nn_tables.h" +#include "ref_functions.h" +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Acti + * @{ + */ + + /** + * @brief Q7 neural network activation function using direct table look-up + * @param[in,out] data pointer to input + * @param[in] size number of elements + * @param[in] int_width bit-width of the integer part, assume to be smaller than 3 + * @param[in] type type of activation functions + * + * @details + * + * This is the direct table look-up approach. + * + * Assume here the integer part of the fixed-point is <= 3. + * More than 3 just not making much sense, makes no difference with + * saturation followed by any of these activation functions. + */ + +void riscv_nn_activations_direct_q7_ref(q7_t * data, uint16_t size, uint16_t int_width, riscv_nn_activation_type type) +{ + uint16_t i = size; + q7_t *pIn = data; + q7_t *pOut = data; + q7_t in; + q7_t out; + uint16_t shift_size = 3 - int_width; + const q7_t *lookup_table; + switch (type) + { + case RISCV_SIGMOID: + lookup_table = sigmoidTable_q7; + break; + case RISCV_TANH: + default: + lookup_table = tanhTable_q7; + break; + } + while (i) + { + in = *pIn++; + out = lookup_table[(uint8_t) (in >> shift_size)]; + *pOut++ = out; + i--; + } +} + +/** + * @} end of Acti group + */ diff --git a/examples/nn/nnTest/Ref_Implementations/ActivationFunctions/riscv_relu6_s8_ref.c b/examples/nn/nnTest/Ref_Implementations/ActivationFunctions/riscv_relu6_s8_ref.c new file mode 100644 index 00000000..a617c8a3 --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/ActivationFunctions/riscv_relu6_s8_ref.c @@ -0,0 +1,66 @@ +/* + * Copyright (C) 2010-2019 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_relu6_s8.c + * Description: Basic s8 version of ReLU6 + * + * $Date: Spetember 2019 + * $Revision: V.1.0.0 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "ref_functions.h" +#include "riscv_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Acti + * @{ + */ + + /* + * Basic ReLU6 function + * + * Refer to header file for details. + * + */ + +void riscv_relu6_s8_ref(q7_t *data, uint16_t size) +{ + int32_t i; + + for (i = 0; i < size; i++) + { + int32_t ip = data[i]; + + ip = MAX(ip, 0); + data[i] = MIN(ip, 6); + } +} + +/** + * @} end of Acti group + */ diff --git a/examples/nn/nnTest/Ref_Implementations/ActivationFunctions/riscv_relu_q15_ref.c b/examples/nn/nnTest/Ref_Implementations/ActivationFunctions/riscv_relu_q15_ref.c new file mode 100644 index 00000000..1cda6638 --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/ActivationFunctions/riscv_relu_q15_ref.c @@ -0,0 +1,71 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_relu_q15.c + * Description: Q15 version of ReLU + * + * $Date: February 27, 2020 + * $Revision: V.1.0.1 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "ref_functions.h" +#include "riscv_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Acti + * @{ + */ + +/** + * @brief Q15 RELU function + * @param[in,out] data pointer to input + * @param[in] size number of elements + * + * @details + * + * Optimized relu with QSUB instructions. + * + */ + +void riscv_relu_q15_ref(q15_t *data, uint16_t size) +{ + + /* Run the following code as reference implementation for M cores without DSP extension */ + uint16_t i; + + for (i = 0; i < size; i++) + { + if (data[i] < 0) + data[i] = 0; + } + +} + +/** + * @} end of Acti group + */ diff --git a/examples/nn/nnTest/Ref_Implementations/ActivationFunctions/riscv_relu_q7_ref.c b/examples/nn/nnTest/Ref_Implementations/ActivationFunctions/riscv_relu_q7_ref.c new file mode 100644 index 00000000..12bc143a --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/ActivationFunctions/riscv_relu_q7_ref.c @@ -0,0 +1,69 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_relu_q7.c + * Description: Q7 version of ReLU + * + * $Date: May 29, 2020 + * $Revision: V.1.0.2 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "ref_functions.h" +#include "riscv_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Acti + * @{ + */ + + /** + * @brief Q7 RELU function + * @param[in,out] data pointer to input + * @param[in] size number of elements + * + * @details + * + * Optimized relu with QSUB instructions. + * + */ + +void riscv_relu_q7_ref(q7_t *data, uint16_t size) +{ + uint16_t i; + + for (i = 0; i < size; i++) + { + if (data[i] < 0) + data[i] = 0; + } + +} + +/** + * @} end of Acti group + */ diff --git a/examples/nn/nnTest/Ref_Implementations/BasicMathFunctions/riscv_elementwise_add_s8_ref.c b/examples/nn/nnTest/Ref_Implementations/BasicMathFunctions/riscv_elementwise_add_s8_ref.c new file mode 100644 index 00000000..ee40972f --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/BasicMathFunctions/riscv_elementwise_add_s8_ref.c @@ -0,0 +1,119 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_elementwise_add_s8 + * Description: Element wise add + * + * $Date: July 31, 2020 + * $Revision: V.2.5.1 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "ref_functions.h" +#include "riscv_nnsupportfunctions.h" + +/** + * @note The *_no_sat API does not mean that the input not saturated, Since + * __MULT is a positive integer, it is saturated. The API definition + * has more info about it. + */ +#define SAT_INPUT(__INPUT, __MULT, __SHIFT) \ + __INPUT = riscv_nn_doubling_high_mult_no_sat(__INPUT, __MULT); \ + __INPUT = riscv_nn_divide_by_power_of_two(__INPUT, -__SHIFT); + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup BasicMath + * @{ + */ + +/* + * s8 element wise add + * + * Refer header file for details. + * + */ + +/* Note: __SHIFT is expected to be <=0 */ + + +riscv_status +riscv_elementwise_add_s8_ref(const int8_t *input_1_vect, + const int8_t *input_2_vect, + const int32_t input_1_offset, + const int32_t input_1_mult, + const int32_t input_1_shift, + const int32_t input_2_offset, + const int32_t input_2_mult, + const int32_t input_2_shift, + const int32_t left_shift, + int8_t *output, + const int32_t out_offset, + const int32_t out_mult, + const int32_t out_shift, + const int32_t out_activation_min, + const int32_t out_activation_max, + const uint32_t block_size) +{ + uint32_t loop_count; + int32_t input_1; + int32_t input_2; + int32_t sum; + + loop_count = block_size; + + while (loop_count > 0U) + { + /* C = A + B */ + + input_1 = (*input_1_vect++ + input_1_offset) << left_shift; + input_2 = (*input_2_vect++ + input_2_offset) << left_shift; + + input_1 = riscv_nn_doubling_high_mult(input_1, input_1_mult); + input_1 = riscv_nn_divide_by_power_of_two(input_1, -input_1_shift); + + input_2 = riscv_nn_doubling_high_mult(input_2, input_2_mult); + input_2 = riscv_nn_divide_by_power_of_two(input_2, -input_2_shift); + + sum = input_1 + input_2; + SAT_INPUT(sum, out_mult, out_shift); + sum += out_offset; + + sum = MAX(sum, out_activation_min); + sum = MIN(sum, out_activation_max); + + *output++ = (q7_t)sum; + + /* Decrement loop counter */ + loop_count--; + } + + return (RISCV_MATH_SUCCESS); +} + +/** + * @} end of BasicMath group + */ diff --git a/examples/nn/nnTest/Ref_Implementations/BasicMathFunctions/riscv_elementwise_mul_s8_ref.c b/examples/nn/nnTest/Ref_Implementations/BasicMathFunctions/riscv_elementwise_mul_s8_ref.c new file mode 100644 index 00000000..ab44644b --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/BasicMathFunctions/riscv_elementwise_mul_s8_ref.c @@ -0,0 +1,98 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_elementwise_mul_s8 + * Description: Element wise multiplication + * + * $Date: May 29, 2020 + * $Revision: V.1.0.3 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "ref_functions.h" +#include "riscv_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup BasicMath + * @{ + */ + +/** + * @brief s8 element wise multiplication of two vectors + * + * @note Refer header file for details. + * + */ + +riscv_status +riscv_elementwise_mul_s8_ref(const int8_t *input_1_vect, + const int8_t *input_2_vect, + const int32_t input_1_offset, + const int32_t input_2_offset, + int8_t *output, + const int32_t out_offset, + const int32_t out_mult, + const int32_t out_shift, + const int32_t out_activation_min, + const int32_t out_activation_max, + const uint32_t block_size) +{ + + int32_t loop_count; + + int32_t input_1; + int32_t input_2; + int32_t mul_res; + + + loop_count = block_size; + + + while (loop_count > 0U) + { + /* C = A * B */ + + input_1 = *input_1_vect++ + input_1_offset; + input_2 = *input_2_vect++ + input_2_offset; + + mul_res = input_1 * input_2; + mul_res = riscv_nn_requantize(mul_res, out_mult, out_shift) + out_offset; + + mul_res = MAX(mul_res, out_activation_min); + mul_res = MIN(mul_res, out_activation_max); + + *output++ = (q7_t)mul_res; + + /* Decrement loop counter */ + loop_count--; + } + return RISCV_MATH_SUCCESS; +} + +/** + * @} end of BasicMath group + */ diff --git a/examples/nn/nnTest/Ref_Implementations/ConcatenationFunctions/riscv_concatenation_s8_w_ref.c b/examples/nn/nnTest/Ref_Implementations/ConcatenationFunctions/riscv_concatenation_s8_w_ref.c new file mode 100644 index 00000000..75d20e26 --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/ConcatenationFunctions/riscv_concatenation_s8_w_ref.c @@ -0,0 +1,66 @@ +/* + * Copyright (C) 2010-2019 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_concatenation_s8_w.c + * Description: s8 version of concatenation along the W axis + * + * $Date: October 2019 + * $Revision: V.1.0.0 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "ref_functions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Concatenation + * @{ + */ + + /* + * s8 version of concatenation along the W axis + * + * Refer to header file for details. + * + */ +void riscv_concatenation_s8_w_ref(const int8_t *input, + const uint16_t input_x, + const uint16_t input_y, + const uint16_t input_z, + const uint16_t input_w, + int8_t *output, + const uint32_t offset_w) +{ + const uint32_t input_copy_size = input_x * input_y * input_z * input_w; + + output += offset_w * (input_x * input_y * input_z); + + memcpy(output, input, input_copy_size); +} + +/** + * @} end of Concatenation group + */ diff --git a/examples/nn/nnTest/Ref_Implementations/ConcatenationFunctions/riscv_concatenation_s8_x_ref.c b/examples/nn/nnTest/Ref_Implementations/ConcatenationFunctions/riscv_concatenation_s8_x_ref.c new file mode 100644 index 00000000..3aa19f19 --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/ConcatenationFunctions/riscv_concatenation_s8_x_ref.c @@ -0,0 +1,75 @@ +/* + * Copyright (C) 2010-2019 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_concatenation_s8_x.c + * Description: s8 version of concatenation along the X axis + * + * $Date: October 2019 + * $Revision: V.1.0.0 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "ref_functions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Concatenation + * @{ + */ + + /* + * s8 version of concatenation along the X axis + * + * Refer to header file for details. + * + */ +void riscv_concatenation_s8_x_ref(const int8_t *input, + const uint16_t input_x, + const uint16_t input_y, + const uint16_t input_z, + const uint16_t input_w, + int8_t *output, + const uint16_t output_x, + const uint32_t offset_x) +{ + const uint32_t num_iterations = input_y * input_z * input_w; + + output += offset_x; + + uint32_t i; + + // Copy per row + for (i = 0; i < num_iterations; ++i) + { + memcpy(output, input, input_x); + input += input_x; + output += output_x; + } +} + +/** + * @} end of Concatenation group + */ diff --git a/examples/nn/nnTest/Ref_Implementations/ConcatenationFunctions/riscv_concatenation_s8_y_ref.c b/examples/nn/nnTest/Ref_Implementations/ConcatenationFunctions/riscv_concatenation_s8_y_ref.c new file mode 100644 index 00000000..98ba375f --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/ConcatenationFunctions/riscv_concatenation_s8_y_ref.c @@ -0,0 +1,76 @@ +/* + * Copyright (C) 2010-2019 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_concatenation_s8_y.c + * Description: s8 version of concatenation along the Y axis + * + * $Date: October 2019 + * $Revision: V.1.0.0 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "ref_functions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Concatenation + * @{ + */ + + /* + * s8 version of concatenation along the Y axis + * + * Refer to header file for details. + * + */ +void riscv_concatenation_s8_y_ref(const int8_t *input, + const uint16_t input_x, + const uint16_t input_y, + const uint16_t input_z, + const uint16_t input_w, + int8_t *output, + const uint16_t output_y, + const uint32_t offset_y) +{ + const uint32_t num_iterations = input_z * input_w; + const uint32_t input_copy_size = input_x * input_y; + const uint32_t output_stride = input_x * output_y; + + output += offset_y * input_x; + uint32_t i; + + // Copy per tile + for (i = 0; i < num_iterations; ++i) + { + memcpy(output, input, input_copy_size); + input += input_copy_size; + output += output_stride; + } +} + +/** + * @} end of Concatenation group + */ diff --git a/examples/nn/nnTest/Ref_Implementations/ConcatenationFunctions/riscv_concatenation_s8_z_ref.c b/examples/nn/nnTest/Ref_Implementations/ConcatenationFunctions/riscv_concatenation_s8_z_ref.c new file mode 100644 index 00000000..cd08b6d6 --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/ConcatenationFunctions/riscv_concatenation_s8_z_ref.c @@ -0,0 +1,75 @@ +/* + * Copyright (C) 2010-2019 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_concatenation_s8_z.c + * Description: s8 version of concatenation along the Z axis + * + * $Date: October 2019 + * $Revision: V.1.0.0 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "ref_functions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Concatenation + * @{ + */ + + /* + * s8 version of concatenation along the Z axis + * + * Refer to header file for details. + * + */ +void riscv_concatenation_s8_z_ref(const int8_t *input, + const uint16_t input_x, + const uint16_t input_y, + const uint16_t input_z, + const uint16_t input_w, + int8_t *output, + const uint16_t output_z, + const uint32_t offset_z) +{ + const uint32_t input_copy_size = input_x * input_y * input_z; + const uint32_t output_stride = input_x * input_y * output_z; + + output += offset_z * (input_x * input_y); + + uint32_t i; + + for (i = 0; i < input_w; ++i) + { + memcpy(output, input, input_copy_size); + input += input_copy_size; + output += output_stride; + } +} + +/** + * @} end of Concatenation group + */ diff --git a/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_convolve_1_x_n_s8_ref.c b/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_convolve_1_x_n_s8_ref.c new file mode 100644 index 00000000..e013722b --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_convolve_1_x_n_s8_ref.c @@ -0,0 +1,97 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_convolve_1_x_n_s8.c + * Description: s8 version of 1xN convolution using symmetric quantization. + * + * $Date: July 27, 2020 + * $Revision: V.2.0.1 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ +#include "ref_functions.h" +#include "riscv_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/* + * 1xN s8 convolution function. + * + * Refer header file for details. + * + */ + +riscv_status riscv_convolve_1_x_n_s8_ref(const nmsis_nn_context* ctx, + const nmsis_nn_conv_params* conv_params, + const nmsis_nn_per_channel_quant_params* quant_params, + const nmsis_nn_dims* input_dims, + const q7_t *input_data, + const nmsis_nn_dims* filter_dims, + const q7_t *filter_data, + const nmsis_nn_dims* bias_dims, + const int32_t *bias_data, + const nmsis_nn_dims* output_dims, + q7_t *output_data) +{ + (void)bias_dims; + riscv_status status = RISCV_MATH_SUCCESS; + if (output_dims->w % 4 != 0) + { + status = RISCV_MATH_SIZE_MISMATCH; + goto out; + } + + status = riscv_convolve_s8_ref(ctx, + conv_params, + quant_params, + input_dims, + input_data, + filter_dims, + filter_data, + bias_dims, + bias_data, + output_dims, + output_data); + +out: + /* Return to application */ + return status; +} + +int32_t riscv_convolve_1_x_n_s8_get_buffer_size_ref(const nmsis_nn_dims* input_dims, + const nmsis_nn_dims* filter_dims) +{ + (void)input_dims; + (void)filter_dims; + return 0; +} + +/** + * @} end of NNConv group + */ diff --git a/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_convolve_1x1_HWC_q7_fast_nonsquare_ref.c b/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_convolve_1x1_HWC_q7_fast_nonsquare_ref.c new file mode 100644 index 00000000..a314c2c7 --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_convolve_1x1_HWC_q7_fast_nonsquare_ref.c @@ -0,0 +1,151 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_convolve_1x1_HWC_q7_fast_nonsquare.c + * Description: Fast Q7 version of 1x1 convolution (non-square shape) + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "ref_functions.h" +#include "riscv_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/** + * @brief Fast Q7 version of 1x1 convolution (non-sqaure shape) + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in_x input tensor dimention x + * @param[in] dim_im_in_y input tensor dimention y + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel_x filter kernel size x + * @param[in] dim_kernel_y filter kernel size y + * @param[in] padding_x padding size x + * @param[in] padding_y padding size y + * @param[in] stride_x convolution stride x + * @param[in] stride_y convolution stride y + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out_x output tensor dimension x + * @param[in] dim_im_out_y output tensor dimension y + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * RISCV_MATH_SIZE_MISMATCH or RISCV_MATH_SUCCESS based on the outcome of size checking. + * + * This function is optimized for convolution with 1x1 kernel size (i.e., dim_kernel_x=1 + * and dim_kernel_y=1). It can be used for the second half of MobileNets [1] after depthwise + * separable convolution. + * + * This function is the version with full list of optimization tricks, but with + * some contraints: + * ch_im_in is multiple of 4 + * ch_im_out is multiple of 2 + * + * [1] MobileNets: Efficient Convolutional Neural Networks for Mobile Vision Applications + * https://arxiv.org/abs/1704.04861 + */ + +riscv_status riscv_convolve_1x1_HWC_q7_fast_nonsquare_ref(const q7_t * Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q7_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q7_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t * Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t * bufferA, + q7_t * bufferB) +{ + (void)bufferB; + /* Run the following code as reference implementation for RISC-V Core without DSP */ + + int i, j, k, l, m, n; + int conv_out; + int in_row, in_col; + + if (ch_im_in % 4 != 0 || ch_im_out % 2 != 0 || dim_kernel_x != 1 || dim_kernel_y != 1 + || padding_x != 0 || padding_y != 0 || stride_x != 1 || stride_y != 1) + { + /* check if the input dimension meets the constraints */ + return RISCV_MATH_SIZE_MISMATCH; + } + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out_y; j++) + { + for (k = 0; k < dim_im_out_x; k++) + { + conv_out = ((q31_t)(bias[i]) << bias_shift) + NN_ROUND(out_shift); + for (m = 0; m < dim_kernel_y; m++) + { + for (n = 0; n < dim_kernel_x; n++) + { + // if-for implementation + in_row = stride_y * j + m - padding_y; + in_col = stride_x * k + n - padding_x; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in_y && in_col < dim_im_in_x) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += Im_in[(in_row * dim_im_in_x + in_col) * ch_im_in + l] * + wt[i * ch_im_in * dim_kernel_y * dim_kernel_x + (m * dim_kernel_y + n) * ch_im_in + l]; + } + } + } + } + Im_out[i + (j * dim_im_out_x + k) * ch_im_out] = (q7_t) __SSAT((conv_out >> out_shift), 8); + } + } + } + /* Return to application */ + return RISCV_MATH_SUCCESS; +} + +/** + * @} end of NNConv group + */ diff --git a/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_convolve_1x1_s8_fast_ref.c b/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_convolve_1x1_s8_fast_ref.c new file mode 100644 index 00000000..c323788a --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_convolve_1x1_s8_fast_ref.c @@ -0,0 +1,110 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_convolve_1x1_s8_fast.c + * Description: Fast q7 version of 1x1 convolution (non-square shape) + * + * $Date: July 27, 2020 + * $Revision: V.2.0.2 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "ref_functions.h" +#include "riscv_nnsupportfunctions.h" + +#define DIM_KER_X (1U) +#define DIM_KER_Y (1U) + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/* + * Fast s8 version for 1x1 convolution (non-square shape) + * + * Refer header file for details. + * + */ + +riscv_status riscv_convolve_1x1_s8_fast_ref(const nmsis_nn_context *ctx, + const nmsis_nn_conv_params *conv_params, + const nmsis_nn_per_channel_quant_params *quant_params, + const nmsis_nn_dims *input_dims, + const q7_t *input_data, + const nmsis_nn_dims *filter_dims, + const q7_t *filter_data, + const nmsis_nn_dims *bias_dims, + const int32_t *bias_data, + const nmsis_nn_dims *output_dims, + q7_t *output_data) +{ + if (input_dims->c % 4 != 0 || + conv_params->padding.w != 0 || conv_params->padding.h != 0 || + conv_params->stride.w != 1 || conv_params->stride.h != 1) + { + return RISCV_MATH_SIZE_MISMATCH; + } + + (void)ctx; + (void)filter_dims; + (void)bias_dims; + + /* Run the following code as reference implementation for RISC-V processors with or without DSP extension */ + + const int32_t lhs_rows = input_dims->w * input_dims->h * input_dims->n; + const int32_t rhs_rows = output_dims->c; + const int32_t rhs_cols = input_dims->c; + + riscv_nn_mat_mult_nt_t_s8_ref(input_data, + filter_data, + bias_data, + output_data, + quant_params->multiplier, + quant_params->shift, + lhs_rows, + rhs_rows, + rhs_cols, + conv_params->input_offset, + conv_params->output_offset, + conv_params->activation.min, + conv_params->activation.max); + + + /* Return to application */ + return RISCV_MATH_SUCCESS; +} + +int32_t riscv_convolve_1x1_s8_fast_get_buffer_size_ref(const nmsis_nn_dims *input_dims) +{ + (void)input_dims; + return 0; +} + +/** + * @} end of NNConv group + */ diff --git a/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_convolve_HWC_q15_basic_ref.c b/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_convolve_HWC_q15_basic_ref.c new file mode 100644 index 00000000..99ca774c --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_convolve_HWC_q15_basic_ref.c @@ -0,0 +1,133 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_convolve_HWC_q15_basic.c + * Description: Q15 version of convolution + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "ref_functions.h" +#include "riscv_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + + /** + * @brief Basic Q15 convolution function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimention + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns RISCV_MATH_SUCCESS + * + * @details + * + * Buffer size: + * + * bufferA size: ch_im_in*dim_kernel*dim_kernel + * + * bufferB size: 0 + * + * This basic version is designed to work for any input tensor and weight + * dimension. + */ + +riscv_status +riscv_convolve_HWC_q15_basic_ref(const q15_t * Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q15_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q15_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q15_t * Im_out, + const uint16_t dim_im_out, + q15_t * bufferA, + q7_t * bufferB) +{ + (void)bufferB; + /* Run the following code as reference implementation for RISC-V Core without DSP */ + int i, j, k, l, m, n; + int conv_out; + int in_row, in_col; + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out; j++) + { + for (k = 0; k < dim_im_out; k++) + { + conv_out = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + for (m = 0; m < dim_kernel; m++) + { + for (n = 0; n < dim_kernel; n++) + { + in_row = stride * j + m - padding; + in_col = stride * k + n - padding; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in && in_col < dim_im_in) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += + Im_in[(in_row * dim_im_in + in_col) * ch_im_in + + l] * wt[i * ch_im_in * dim_kernel * dim_kernel + (m * dim_kernel + + n) * ch_im_in + l]; + } + } + } + } + Im_out[i + (j * dim_im_out + k) * ch_im_out] = (q15_t) __SSAT((conv_out >> out_shift), 16); + } + } + } + /* Return to application */ + return RISCV_MATH_SUCCESS; +} + +/** + * @} end of NNConv group + */ diff --git a/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_convolve_HWC_q15_fast_nonsquare_ref.c b/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_convolve_HWC_q15_fast_nonsquare_ref.c new file mode 100644 index 00000000..db0bb876 --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_convolve_HWC_q15_fast_nonsquare_ref.c @@ -0,0 +1,154 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_convolve_HWC_q15_fast.c + * Description: Fast Q15 version of convolution + * + * $Date: 24. May 2018 + * $Revision: V.1.0.0 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "ref_functions.h" +#include "riscv_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + + /** + * @brief Fast Q15 convolution function (non-sqaure shape) + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in_x input tensor dimention x + * @param[in] dim_im_in_y input tensor dimention y + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel_x filter kernel size x + * @param[in] dim_kernel_y filter kernel size y + * @param[in] padding_x padding size x + * @param[in] padding_y padding size y + * @param[in] stride_x convolution stride x + * @param[in] stride_y convolution stride y + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out_x output tensor dimension x + * @param[in] dim_im_out_y output tensor dimension y + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * RISCV_MATH_SIZE_MISMATCH or RISCV_MATH_SUCCESS based on the outcome of size checking. + * + * @details + * + * Buffer size: + * + * bufferA size: 2*ch_im_in*dim_kernel*dim_kernel + * + * bufferB size: 0 + * + * Input dimension constraints: + * + * ch_im_in is multiple of 2 + * + * ch_im_out is multipe of 2 + * + */ + +riscv_status +riscv_convolve_HWC_q15_fast_nonsquare_ref(const q15_t * Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q15_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q15_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q15_t * Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t * bufferA, + q7_t * bufferB) +{ + (void)bufferB; + /* Run the following code as reference implementation for RISC-V Core without DSP */ + int i, j, k, l, m, n; + int conv_out; + int in_row, in_col; + + if (ch_im_in % 2 != 0 || ch_im_out % 2 != 0) + { + /* check if the input dimension meets the constraints */ + return RISCV_MATH_SIZE_MISMATCH; + } + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out_y; j++) + { + for (k = 0; k < dim_im_out_x; k++) + { + conv_out = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + for (m = 0; m < dim_kernel_y; m++) + { + for (n = 0; n < dim_kernel_x; n++) + { + in_row = stride_y * j + m - padding_y; + in_col = stride_x * k + n - padding_x; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in_y && in_col < dim_im_in_x) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += + Im_in[(in_row * dim_im_in_x + in_col) * ch_im_in + + l] * wt[i * ch_im_in * dim_kernel_x * dim_kernel_y + (m * dim_kernel_x + + n) * ch_im_in + l]; + } + } + } + } + Im_out[i + (j * dim_im_out_x + k) * ch_im_out] = (q15_t) __SSAT((conv_out >> out_shift), 16); + } + } + } + /* Return to application */ + return RISCV_MATH_SUCCESS; +} + +/** + * @} end of NNConv group + */ diff --git a/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_convolve_HWC_q15_fast_ref.c b/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_convolve_HWC_q15_fast_ref.c new file mode 100644 index 00000000..43fdabe4 --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_convolve_HWC_q15_fast_ref.c @@ -0,0 +1,144 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_convolve_HWC_q15_fast.c + * Description: Fast Q15 version of convolution + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "ref_functions.h" +#include "riscv_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + + /** + * @brief Fast Q15 convolution function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimention + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * RISCV_MATH_SIZE_MISMATCH or RISCV_MATH_SUCCESS based on the outcome of size checking. + * + * @details + * + * Buffer size: + * + * bufferA size: 2*ch_im_in*dim_kernel*dim_kernel + * + * bufferB size: 0 + * + * Input dimension constraints: + * + * ch_im_in is multiple of 2 + * + * ch_im_out is multipe of 2 + * + */ + +riscv_status +riscv_convolve_HWC_q15_fast_ref(const q15_t * Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q15_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q15_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q15_t * Im_out, + const uint16_t dim_im_out, + q15_t * bufferA, + q7_t * bufferB) +{ + (void)bufferB; + /* Run the following code as reference implementation for RISC-V Core without DSP */ + int i, j, k, l, m, n; + int conv_out; + int in_row, in_col; + + if (ch_im_in % 2 != 0 || ch_im_out % 2 != 0) + { + /* check if the input dimension meets the constraints */ + return RISCV_MATH_SIZE_MISMATCH; + } + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out; j++) + { + for (k = 0; k < dim_im_out; k++) + { + conv_out = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + for (m = 0; m < dim_kernel; m++) + { + for (n = 0; n < dim_kernel; n++) + { + in_row = stride * j + m - padding; + in_col = stride * k + n - padding; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in && in_col < dim_im_in) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += + Im_in[(in_row * dim_im_in + in_col) * ch_im_in + + l] * wt[i * ch_im_in * dim_kernel * dim_kernel + (m * dim_kernel + + n) * ch_im_in + l]; + } + } + } + } + Im_out[i + (j * dim_im_out + k) * ch_im_out] = (q15_t) __SSAT((conv_out >> out_shift), 16); + } + } + } + /* Return to application */ + return RISCV_MATH_SUCCESS; +} + +/** + * @} end of NNConv group + */ diff --git a/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_convolve_HWC_q7_RGB_ref.c b/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_convolve_HWC_q7_RGB_ref.c new file mode 100644 index 00000000..a71f4c79 --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_convolve_HWC_q7_RGB_ref.c @@ -0,0 +1,143 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_convolve_HWC_q7_RGB.c + * Description: Q7 version of convolution for RGB image + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ +#include "ref_functions.h" +#include "riscv_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + + /** + * @brief Q7 convolution function for RGB image + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimention + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * RISCV_MATH_SIZE_MISMATCH or RISCV_MATH_SUCCESS based on the outcome of size checking. + * + * @details + * + * Buffer size: + * + * bufferA size: 2*ch_im_in*dim_kernel*dim_kernel + * + * bufferB size: 0 + * + * Input dimension constraints: + * + * ch_im_in equals 3 + * + * This kernel is written exclusively for convolution with ch_im_in + * equals 3. This applies on the first layer of CNNs which has input + * image with RGB format. + */ + +riscv_status +riscv_convolve_HWC_q7_RGB_ref(const q7_t * Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q7_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q7_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t * Im_out, const uint16_t dim_im_out, q15_t * bufferA, q7_t * bufferB) +{ + (void)bufferB; + /* Run the following code as reference implementation for RISC-V Core without DSP */ + + int i, j, k, l, m, n; + int conv_out; + int in_row, in_col; + + // check if number of input channels is 3 + if (ch_im_in != 3) + { + return RISCV_MATH_SIZE_MISMATCH; + } + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out; j++) + { + for (k = 0; k < dim_im_out; k++) + { + conv_out = (bias[i] << bias_shift) + NN_ROUND(out_shift); + for (m = 0; m < dim_kernel; m++) + { + for (n = 0; n < dim_kernel; n++) + { + /* if-for implementation */ + in_row = stride * j + m - padding; + in_col = stride * k + n - padding; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in && in_col < dim_im_in) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += + Im_in[(in_row * dim_im_in + in_col) * ch_im_in + + l] * wt[i * ch_im_in * dim_kernel * dim_kernel + (m * dim_kernel + + n) * ch_im_in + l]; + } + } + } + } + Im_out[i + (j * dim_im_out + k) * ch_im_out] = (q7_t) __SSAT((conv_out >> out_shift), 8); + } + } + } + /* Return to application */ + return (RISCV_MATH_SUCCESS); +} + +/** + * @} end of NNConv group + */ diff --git a/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_convolve_HWC_q7_basic_nonsquare_ref.c b/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_convolve_HWC_q7_basic_nonsquare_ref.c new file mode 100644 index 00000000..0b41ebc6 --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_convolve_HWC_q7_basic_nonsquare_ref.c @@ -0,0 +1,133 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_convolve_HWC_q7_basic.c + * Description: Q7 version of convolution + * + * $Date: 13. July 2018 + * $Revision: V.1.0.0 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ +#include "ref_functions.h" +#include "riscv_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + + /** + * @brief Basic Q7 convolution function (non-sqaure shape) + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in_x input tensor dimention x + * @param[in] dim_im_in_y input tensor dimention y + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel_x filter kernel size x + * @param[in] dim_kernel_y filter kernel size y + * @param[in] padding_x padding size x + * @param[in] padding_y padding size y + * @param[in] stride_x convolution stride x + * @param[in] stride_y convolution stride y + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out_x output tensor dimension x + * @param[in] dim_im_out_y output tensor dimension y + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns RISCV_MATH_SUCCESS + */ + +riscv_status riscv_convolve_HWC_q7_basic_nonsquare_ref(const q7_t * Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q7_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q7_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t * Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t * bufferA, + q7_t * bufferB) +{ + (void)bufferB; + /* Run the following code as reference implementation for RISC-V Core without DSP */ + + int i, j, k, l, m, n; + int conv_out; + int in_row, in_col; + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out_y; j++) + { + for (k = 0; k < dim_im_out_x; k++) + { + conv_out = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + for (m = 0; m < dim_kernel_y; m++) + { + for (n = 0; n < dim_kernel_x; n++) + { + // if-for implementation + in_row = stride_y * j + m - padding_y; + in_col = stride_x * k + n - padding_x; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in_y && in_col < dim_im_in_x) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += + Im_in[(in_row * dim_im_in_x + in_col) * ch_im_in + l] * + wt[i * ch_im_in * dim_kernel_y * dim_kernel_x + + (m * dim_kernel_x + n) * ch_im_in + l]; + } + } + } + } + Im_out[i + (j * dim_im_out_x + k) * ch_im_out] = (q7_t) __SSAT((conv_out >> out_shift), 8); + } + } + } + + /* Return to application */ + return RISCV_MATH_SUCCESS; +} + +/** + * @} end of NNConv group + */ diff --git a/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_convolve_HWC_q7_basic_ref.c b/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_convolve_HWC_q7_basic_ref.c new file mode 100644 index 00000000..6f84cbf0 --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_convolve_HWC_q7_basic_ref.c @@ -0,0 +1,135 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_convolve_HWC_q7_basic.c + * Description: Q7 version of convolution + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ +#include "ref_functions.h" +#include "riscv_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + + /** + * @brief Basic Q7 convolution function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimention + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns RISCV_MATH_SUCCESS + * + * @details + * + * Buffer size: + * + * bufferA size: 2*ch_im_in*dim_kernel*dim_kernel + * + * bufferB size: 0 + * + * This basic version is designed to work for any input tensor and weight + * dimension. + */ + +riscv_status +riscv_convolve_HWC_q7_basic_ref(const q7_t * Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q7_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q7_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t * Im_out, + const uint16_t dim_im_out, + q15_t * bufferA, + q7_t * bufferB) +{ + (void)bufferB; + /* Run the following code as reference implementation for RISC-V Core without DSP */ + + int i, j, k, l, m, n; + int conv_out; + int in_row, in_col; + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out; j++) + { + for (k = 0; k < dim_im_out; k++) + { + conv_out = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + for (m = 0; m < dim_kernel; m++) + { + for (n = 0; n < dim_kernel; n++) + { + // if-for implementation + in_row = stride * j + m - padding; + in_col = stride * k + n - padding; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in && in_col < dim_im_in) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += + Im_in[(in_row * dim_im_in + in_col) * ch_im_in + + l] * wt[i * ch_im_in * dim_kernel * dim_kernel + (m * dim_kernel + + n) * ch_im_in + l]; + } + } + } + } + Im_out[i + (j * dim_im_out + k) * ch_im_out] = (q7_t) __SSAT((conv_out >> out_shift), 8); + } + } + } + + /* Return to application */ + return RISCV_MATH_SUCCESS; +} + +/** + * @} end of NNConv group + */ diff --git a/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_convolve_HWC_q7_fast_nonsquare_ref.c b/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_convolve_HWC_q7_fast_nonsquare_ref.c new file mode 100644 index 00000000..0e35990a --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_convolve_HWC_q7_fast_nonsquare_ref.c @@ -0,0 +1,143 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_convolve_HWC_q7_fast_nonsquare.c + * Description: Fast Q7 version of convolution (non-sqaure shape) + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "ref_functions.h" +#include "riscv_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/** + * @brief Fast Q7 convolution function (non-sqaure shape) + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in_x input tensor dimention x + * @param[in] dim_im_in_y input tensor dimention y + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel_x filter kernel size x + * @param[in] dim_kernel_y filter kernel size y + * @param[in] padding_x padding size x + * @param[in] padding_y padding size y + * @param[in] stride_x convolution stride x + * @param[in] stride_y convolution stride y + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out_x output tensor dimension x + * @param[in] dim_im_out_y output tensor dimension y + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * RISCV_MATH_SIZE_MISMATCH or RISCV_MATH_SUCCESS based on the outcome of size checking. + * + * This function is the version with full list of optimization tricks, but with + * some contraints: + * ch_im_in is multiple of 4 + * ch_im_out is multiple of 2 + */ + +riscv_status riscv_convolve_HWC_q7_fast_nonsquare_ref(const q7_t * Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q7_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q7_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t * Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t * bufferA, + q7_t * bufferB) +{ + (void)bufferB; + /* Run the following code as reference implementation for RISC-V Core without DSP */ + int i, j, k, l, m, n; + int conv_out; + int in_row, in_col; + + if (ch_im_in % 4 != 0 || ch_im_out % 2 != 0) + { + /* check if the input dimension meets the constraints */ + return RISCV_MATH_SIZE_MISMATCH; + } + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out_y; j++) + { + for (k = 0; k < dim_im_out_x; k++) + { + conv_out = ((q31_t)(bias[i]) << bias_shift) + NN_ROUND(out_shift); + for (m = 0; m < dim_kernel_y; m++) + { + for (n = 0; n < dim_kernel_x; n++) + { + /* if-for implementation */ + in_row = stride_y * j + m - padding_y; + in_col = stride_x * k + n - padding_x; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in_y && in_col < dim_im_in_x) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += Im_in[(in_row * dim_im_in_x + in_col) * ch_im_in + l] * + wt[i * ch_im_in * dim_kernel_y * dim_kernel_x + (m * dim_kernel_x + n) * ch_im_in + l]; + } + } + } + } + Im_out[i + (j * dim_im_out_x + k) * ch_im_out] = (q7_t) __SSAT((conv_out >> out_shift), 8); + } + } + } + + /* Return to application */ + return RISCV_MATH_SUCCESS; +} + +/** + * @} end of NNConv group + */ diff --git a/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_convolve_HWC_q7_fast_ref.c b/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_convolve_HWC_q7_fast_ref.c new file mode 100644 index 00000000..267b1f80 --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_convolve_HWC_q7_fast_ref.c @@ -0,0 +1,159 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_convolve_HWC_q7_fast.c + * Description: Fast Q7 version of convolution + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "ref_functions.h" +#include "riscv_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + + /** + * @brief Fast Q7 convolution function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimention + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * RISCV_MATH_SIZE_MISMATCH or RISCV_MATH_SUCCESS based on the outcome of size checking. + * + * @details + * + * Buffer size: + * + * bufferA size: 2*ch_im_in*dim_kernel*dim_kernel + * + * bufferB size: 0 + * + * Input dimension constraints: + * + * ch_im_in is multiple of 4 ( because of the SIMD32 read and swap ) + * + * ch_im_out is multipe of 2 ( bacause 2x2 mat_mult kernel ) + * + * The im2col converts the Q7 tensor input into Q15 column, which is stored in + * bufferA. There is reordering happenning during this im2col process with + * riscv_q7_to_q15_reordered_no_shift. For every four elements, the second and + * third elements are swapped. + * + * The computation kernel riscv_nn_mat_mult_kernel_q7_q15_reordered does the + * GEMM computation with the reordered columns. + * + * To speed-up the determination of the padding condition, we split the + * computation into 3x3 parts, i.e., {top, mid, bottom} X {left, mid, right}. + * This reduces the total number of boundary condition checks and improves + * the data copying performance. + */ + +riscv_status +riscv_convolve_HWC_q7_fast_ref(const q7_t * Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q7_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q7_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t * Im_out, + const uint16_t dim_im_out, + q15_t * bufferA, + q7_t * bufferB) +{ + (void)bufferB; + /* Run the following code as reference implementation for RISC-V Core without DSP */ + + int i, j, k, l, m, n; + int conv_out; + int in_row, in_col; + + if (ch_im_in % 4 != 0 || ch_im_out % 2 != 0) + { + /* check if the input dimension meets the constraints */ + return RISCV_MATH_SIZE_MISMATCH; + } + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out; j++) + { + for (k = 0; k < dim_im_out; k++) + { + conv_out = (bias[i] << bias_shift) + NN_ROUND(out_shift); + for (m = 0; m < dim_kernel; m++) + { + for (n = 0; n < dim_kernel; n++) + { + // if-for implementation + in_row = stride * j + m - padding; + in_col = stride * k + n - padding; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in && in_col < dim_im_in) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += + Im_in[(in_row * dim_im_in + in_col) * ch_im_in + + l] * wt[i * ch_im_in * dim_kernel * dim_kernel + (m * dim_kernel + + n) * ch_im_in + l]; + } + } + } + } + Im_out[i + (j * dim_im_out + k) * ch_im_out] = (q7_t) __SSAT((conv_out >> out_shift), 8); + } + } + } + + /* Return to application */ + return RISCV_MATH_SUCCESS; +} + +/** + * @} end of NNConv group + */ diff --git a/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_convolve_s8_ref.c b/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_convolve_s8_ref.c new file mode 100644 index 00000000..f8e30410 --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_convolve_s8_ref.c @@ -0,0 +1,158 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_convolve_s8.c + * Description: s8 version of convolution using symmetric quantization. + * + * $Date: July 27, 2020 + * $Revision: V.2.0.2 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ +#include "ref_functions.h" +#include "riscv_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/* + * Basic s8 convolution function. + * + * Refer header file for details. Optimal use case for the DSP implementation is when input and output channels + * are multiples of 4 or atleast greater than 4. + * + */ + +riscv_status riscv_convolve_s8_ref(const nmsis_nn_context* ctx, + const nmsis_nn_conv_params* conv_params, + const nmsis_nn_per_channel_quant_params* quant_params, + const nmsis_nn_dims* input_dims, + const q7_t *input_data, + const nmsis_nn_dims* filter_dims, + const q7_t *filter_data, + const nmsis_nn_dims* bias_dims, + const int32_t *bias_data, + const nmsis_nn_dims* output_dims, + q7_t *output_data) +{ + q15_t *buffer_a = (q15_t *)ctx->buf; + + const uint16_t input_batches = input_dims->n; + const uint16_t input_x = input_dims->w; + const uint16_t input_y = input_dims->h; + const uint16_t input_ch = input_dims->c; + const uint16_t kernel_x = filter_dims->w; + const uint16_t kernel_y = filter_dims->h; + const uint16_t output_x = output_dims->w; + const uint16_t output_y = output_dims->h; + const uint16_t output_ch = output_dims->c; + + const uint16_t pad_x = conv_params->padding.w; + const uint16_t pad_y = conv_params->padding.h; + const uint16_t stride_x = conv_params->stride.w; + const uint16_t stride_y = conv_params->stride.h; + + const int32_t input_offset = conv_params->input_offset; + const int32_t out_offset = conv_params->output_offset; + const int32_t out_activation_min = conv_params->activation.min; + const int32_t out_activation_max = conv_params->activation.max; + int32_t *output_mult = quant_params->multiplier; + int32_t *output_shift = quant_params->shift; + + int i_batch; + for (i_batch = 0; i_batch < input_batches; i_batch++) + { + /* Run the following code as reference implementation for RISC-V Core without DSP */ + (void)buffer_a; + int32_t i_out_ch, i_out_y, i_out_x, i_input_ch, i_ker_y, i_ker_x; + int32_t conv_out; + + for (i_out_ch = 0; i_out_ch < output_ch; i_out_ch++) + { + for (i_out_y = 0; i_out_y < output_y; i_out_y++) + { + for (i_out_x = 0; i_out_x < output_x; i_out_x++) + { + conv_out = 0; + + const int32_t base_idx_y = stride_y * i_out_y - pad_y; + const int32_t base_idx_x = stride_x * i_out_x - pad_x; + + const int32_t ker_y_start = MAX(0, -base_idx_y); + const int32_t ker_x_start = MAX(0, -base_idx_x); + + const int32_t ker_y_end = MIN(kernel_y, input_y - base_idx_y); + const int32_t ker_x_end = MIN(kernel_x, input_x - base_idx_x); + + for (i_ker_y = ker_y_start; i_ker_y < ker_y_end; i_ker_y++) + { + for (i_ker_x = ker_x_start; i_ker_x < ker_x_end; i_ker_x++) + { + const int32_t in_row = base_idx_y + i_ker_y; + const int32_t in_col = base_idx_x + i_ker_x; + for (i_input_ch = 0; i_input_ch < input_ch; i_input_ch++) + { + conv_out += + (input_data[(in_row * input_x + in_col) * input_ch + i_input_ch] + input_offset) * + filter_data[i_out_ch * input_ch * kernel_y * kernel_x + + (i_ker_y * kernel_x + i_ker_x) * input_ch + i_input_ch]; + } + } + } + if (bias_data) + { + conv_out += bias_data[i_out_ch]; + } + conv_out = riscv_nn_requantize(conv_out, output_mult[i_out_ch], output_shift[i_out_ch]); + conv_out += out_offset; + conv_out = MAX(conv_out, out_activation_min); + conv_out = MIN(conv_out, out_activation_max); + output_data[i_out_ch + (i_out_y * output_x + i_out_x) * output_ch] = (int8_t)conv_out; + } + } + } + /* Advance to the next batch */ + input_data += (input_x * input_y * input_ch); + output_data += (output_x * output_y * output_ch); + } + + /* Return to application */ + return RISCV_MATH_SUCCESS; +} + +int32_t riscv_convolve_s8_get_buffer_size_ref(const nmsis_nn_dims* input_dims, + const nmsis_nn_dims* filter_dims) +{ + (void)input_dims; + (void)filter_dims; + return 0; +} + +/** + * @} end of NNConv group + */ diff --git a/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_convolve_wrapper_s8_ref.c b/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_convolve_wrapper_s8_ref.c new file mode 100644 index 00000000..04551b16 --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_convolve_wrapper_s8_ref.c @@ -0,0 +1,148 @@ +/* + * Copyright (C) 2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_convolve_wrapper_s8.c + * Description: s8 convolution layer wrapper function with the main purpose to call the optimal kernel available in nmsis-nn to perform the convolution. + * + * $Date: May 18, 2020 + * $Revision: V.1.0.0 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "ref_functions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/* + * Convolution layer + * + * Refer header file for details. + * + */ + +riscv_status riscv_convolve_wrapper_s8_ref(const nmsis_nn_context* ctx, + const nmsis_nn_conv_params* conv_params, + const nmsis_nn_per_channel_quant_params* quant_params, + const nmsis_nn_dims* input_dims, + const q7_t *input_data, + const nmsis_nn_dims* filter_dims, + const q7_t *filter_data, + const nmsis_nn_dims* bias_dims, + const int32_t *bias_data, + const nmsis_nn_dims* output_dims, + q7_t *output_data) +{ + if ((conv_params->padding.w == 0) && + (conv_params->padding.h == 0) && + (input_dims->c % 4 == 0) && + (conv_params->stride.w == 1) && + (conv_params->stride.h == 1) && + (filter_dims->w == 1) && + (filter_dims->h == 1)) + { + return riscv_convolve_1x1_s8_fast_ref(ctx, + conv_params, + quant_params, + input_dims, + input_data, + filter_dims, + filter_data, + bias_dims, + bias_data, + output_dims, + output_data); + } + else if ((output_dims->h == 1) && + (input_dims->h == 1) && + (filter_dims->h == 1) && + (output_dims->w % 4 == 0) && + (input_dims->n == 1)) + { + return riscv_convolve_1_x_n_s8_ref(ctx, + conv_params, + quant_params, + input_dims, + input_data, + filter_dims, + filter_data, + bias_dims, + bias_data, + output_dims, + output_data); + } + else + { + return riscv_convolve_s8_ref(ctx, + conv_params, + quant_params, + input_dims, + input_data, + filter_dims, + filter_data, + bias_dims, + bias_data, + output_dims, + output_data); + } +} + +int32_t riscv_convolve_wrapper_s8_get_buffer_size_ref(const nmsis_nn_conv_params* conv_params, + const nmsis_nn_dims* input_dims, + const nmsis_nn_dims* filter_dims, + const nmsis_nn_dims* output_dims) +{ + if ((conv_params->padding.w == 0) && + (conv_params->padding.h == 0) && + (input_dims->c % 4 == 0) && + (conv_params->stride.w == 1) && + (conv_params->stride.h == 1) && + (filter_dims->w == 1) && + (filter_dims->h == 1)) + { + return riscv_convolve_1x1_s8_fast_get_buffer_size_ref(input_dims); + } + else if ((output_dims->h == 1) && + (input_dims->h == 1) && + (filter_dims->h == 1) && + (output_dims->w % 4 == 0) && + (input_dims->n == 1)) + { + return riscv_convolve_1_x_n_s8_get_buffer_size_ref(input_dims, filter_dims); + } + else + { + return riscv_convolve_s8_get_buffer_size_ref(input_dims, filter_dims); + } +} + +/** + * @} end of NNConv group + */ + diff --git a/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_depthwise_conv_3x3_s8_ref.c b/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_depthwise_conv_3x3_s8_ref.c new file mode 100644 index 00000000..28bf5af4 --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_depthwise_conv_3x3_s8_ref.c @@ -0,0 +1,213 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_depthwise_conv_3x3_s8.c + * Description: Optimized s8 depthwise convolution function for channel + * multiplier of 1 and 3x3 kernel size. + * + * $Date: May 14, 2020 + * $Revision: V.2.0.0 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "ref_functions.h" +#include "riscv_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/* + * Optimized s8 depthwise convolution function with constraint that + * in_channel == out_channel and kernel_x == kernel_y == 3 with pads at most 1 + * + * Refer prototype header file for details. + * + */ + +riscv_status riscv_depthwise_conv_3x3_s8_ref(const nmsis_nn_context *ctx, + const nmsis_nn_dw_conv_params *dw_conv_params, + const nmsis_nn_per_channel_quant_params *quant_params, + const nmsis_nn_dims *input_dims, + const q7_t *input, + const nmsis_nn_dims *filter_dims, + const q7_t *kernel, + const nmsis_nn_dims *bias_dims, + const int32_t *bias, + const nmsis_nn_dims *output_dims, + q7_t *output) +{ + (void)ctx; + (void)bias_dims; + + const int32_t input_x = input_dims->w; + const int32_t input_y = input_dims->h; + const int32_t input_ch = input_dims->c; + const int32_t output_ch = output_dims->c; + const int32_t pad_x = dw_conv_params->padding.w; + const int32_t pad_y = dw_conv_params->padding.h; + const int32_t stride_x = dw_conv_params->stride.w; + const int32_t stride_y = dw_conv_params->stride.h; + const int32_t *output_shift = quant_params->shift; + const int32_t *output_mult = quant_params->multiplier; + const int32_t output_x = output_dims->w; + const int32_t output_y = output_dims->h; + const int32_t output_offset = dw_conv_params->output_offset; + const int32_t input_offset = dw_conv_params->input_offset; + const int32_t output_activation_min = dw_conv_params->activation.min; + const int32_t output_activation_max = dw_conv_params->activation.max; + + /* Check input constraints input_ch == output_ch */ + if (input_ch != output_ch) + { + return RISCV_MATH_SIZE_MISMATCH; + } + /* Check input constraints pad_x <= 1 */ + if (pad_x > 1 || filter_dims->w != 3 || filter_dims->h != 3) + { + return RISCV_MATH_ARGUMENT_ERROR; + } + + for (int32_t in_h = -pad_y, out_h = 0, out_idx = 0; out_h < output_y; in_h += stride_y, ++out_h) + { + for (int32_t in_w = -pad_x, out_w = 0, ker_h_start = MAX(0, -in_h); out_w < output_x; in_w += stride_x, ++out_w) + { + int32_t in_ch = 0; + int32_t ker_w_start = MAX(0, -in_w); + + for (; in_ch <= (input_ch - 4); in_ch += 4) + { + int32_t out_buff0 = bias[in_ch + 0]; + int32_t out_buff1 = bias[in_ch + 1]; + int32_t out_buff2 = bias[in_ch + 2]; + int32_t out_buff3 = bias[in_ch + 3]; + + const int8_t *input_ptr = input + (in_h + ker_h_start) * (input_ch * input_x) + in_w * input_ch + in_ch; + const int8_t *kernel_ptr = kernel + ker_h_start * (input_ch * 3) + in_ch; + + for (int32_t ker_h = ker_h_start; ker_h < MIN(3, input_y - in_h); ++ker_h) + { + int32_t in_val = 0; + int32_t ker_val = 0; + + if (ker_w_start == 0) + { + in_val = riscv_nn_read_q7x4(input_ptr); + ker_val = riscv_nn_read_q7x4(kernel_ptr); + + out_buff0 += ((int8_t)in_val + input_offset) * (int8_t)ker_val; + out_buff1 += ((int8_t)(in_val >> 8) + input_offset) * (int8_t)(ker_val >> 8); + out_buff2 += ((int8_t)(in_val >> 16) + input_offset) * (int8_t)(ker_val >> 16); + out_buff3 += ((int8_t)(in_val >> 24) + input_offset) * (int8_t)(ker_val >> 24); + } + + in_val = riscv_nn_read_q7x4(input_ptr + input_ch); + ker_val = riscv_nn_read_q7x4(kernel_ptr + input_ch); + + out_buff0 += ((int8_t)in_val + input_offset) * (int8_t)ker_val; + out_buff1 += ((int8_t)(in_val >> 8) + input_offset) * (int8_t)(ker_val >> 8); + out_buff2 += ((int8_t)(in_val >> 16) + input_offset) * (int8_t)(ker_val >> 16); + out_buff3 += ((int8_t)(in_val >> 24) + input_offset) * (int8_t)(ker_val >> 24); + + if ((input_x - in_w) >= 3) + { + in_val = riscv_nn_read_q7x4(input_ptr + (input_ch << 1)); + ker_val = riscv_nn_read_q7x4(kernel_ptr + (input_ch << 1)); + + out_buff0 += ((int8_t)in_val + input_offset) * (int8_t)ker_val; + out_buff1 += ((int8_t)(in_val >> 8) + input_offset) * (int8_t)(ker_val >> 8); + out_buff2 += ((int8_t)(in_val >> 16) + input_offset) * (int8_t)(ker_val >> 16); + out_buff3 += ((int8_t)(in_val >> 24) + input_offset) * (int8_t)(ker_val >> 24); + } + + input_ptr += (input_ch * input_x); + kernel_ptr += (input_ch * 3); + } + + out_buff0 = riscv_nn_requantize(out_buff0, output_mult[in_ch + 0], output_shift[in_ch + 0]); + out_buff1 = riscv_nn_requantize(out_buff1, output_mult[in_ch + 1], output_shift[in_ch + 1]); + out_buff2 = riscv_nn_requantize(out_buff2, output_mult[in_ch + 2], output_shift[in_ch + 2]); + out_buff3 = riscv_nn_requantize(out_buff3, output_mult[in_ch + 3], output_shift[in_ch + 3]); + + out_buff0 += output_offset; + out_buff1 += output_offset; + out_buff2 += output_offset; + out_buff3 += output_offset; + + out_buff0 = MIN(MAX(out_buff0, output_activation_min), output_activation_max); + out_buff1 = MIN(MAX(out_buff1, output_activation_min), output_activation_max); + out_buff2 = MIN(MAX(out_buff2, output_activation_min), output_activation_max); + out_buff3 = MIN(MAX(out_buff3, output_activation_min), output_activation_max); + + output[out_idx++] = (int8_t)out_buff0; + output[out_idx++] = (int8_t)out_buff1; + output[out_idx++] = (int8_t)out_buff2; + output[out_idx++] = (int8_t)out_buff3; + } + + // Leftover + for (; in_ch < input_ch; ++in_ch) + { + int32_t out_buff = bias[in_ch]; + + const int8_t *input_ptr = input + (in_h + ker_h_start) * (input_ch * input_x) + in_w * input_ch + in_ch; + const int8_t *kernel_ptr = kernel + ker_h_start * (input_ch * 3) + in_ch; + + for (int32_t ker_h = ker_h_start; ker_h < MIN(3, input_y - in_h); ++ker_h) + { + if (ker_w_start == 0) + { + out_buff += (*(input_ptr) + input_offset) * *(kernel_ptr); + } + + out_buff += (*(input_ptr + input_ch) + input_offset) * *(kernel_ptr + input_ch); + + if ((input_x - in_w) >= 3) + { + out_buff += (*(input_ptr + (input_ch << 1)) + input_offset) * *(kernel_ptr + (input_ch << 1)); + } + + input_ptr += (input_ch * input_x); + kernel_ptr += (input_ch * 3); + } + + out_buff = riscv_nn_requantize(out_buff, output_mult[in_ch], output_shift[in_ch]); + out_buff += output_offset; + out_buff = MIN(MAX(out_buff, output_activation_min), output_activation_max); + output[out_idx++] = (int8_t)out_buff; + } + } + } + + /* Return to application */ + return RISCV_MATH_SUCCESS; +} + +/** + * @} end of NNConv group + */ diff --git a/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_depthwise_conv_s8_opt_ref.c b/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_depthwise_conv_s8_opt_ref.c new file mode 100644 index 00000000..0c16ef05 --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_depthwise_conv_s8_opt_ref.c @@ -0,0 +1,116 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_depthwise_conv_s8_opt.c + * Description: Optimized s8 depthwise separable convolution function for + * channel multiplier of 1. + * + * $Date: May 29, 2020 + * $Revision: V.2.0.1 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "ref_functions.h" +#include "riscv_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/* + * Optimized s8 depthwise convolution function with constraint that in_channel equals out_channel + * + * Refer prototype header file for details. + * + */ + +riscv_status riscv_depthwise_conv_s8_opt_ref(const nmsis_nn_context *ctx, + const nmsis_nn_dw_conv_params *dw_conv_params, + const nmsis_nn_per_channel_quant_params *quant_params, + const nmsis_nn_dims *input_dims, + const q7_t *input, + const nmsis_nn_dims *filter_dims, + const q7_t *kernel, + const nmsis_nn_dims *bias_dims, + const int32_t *bias, + const nmsis_nn_dims *output_dims, + q7_t *output) +{ + const int32_t input_x = input_dims->w; + const int32_t input_y = input_dims->h; + const int32_t input_ch = input_dims->c; + const int32_t output_ch = output_dims->c; + const int32_t kernel_x = filter_dims->w; + const int32_t kernel_y = filter_dims->h; + const int32_t pad_x = dw_conv_params->padding.w; + const int32_t pad_y = dw_conv_params->padding.h; + const int32_t stride_x = dw_conv_params->stride.w; + const int32_t stride_y = dw_conv_params->stride.h; + const int32_t *output_shift = quant_params->shift; + const int32_t *output_mult = quant_params->multiplier; + const int32_t output_x = output_dims->w; + const int32_t output_y = output_dims->h; + const int32_t output_offset = dw_conv_params->output_offset; + const int32_t input_offset = dw_conv_params->input_offset; + const int32_t output_activation_min = dw_conv_params->activation.min; + const int32_t output_activation_max = dw_conv_params->activation.max; + q15_t *buffer_a = (q15_t *)ctx->buf; + + /* Check input constraints input_ch == output_ch */ + if (input_ch != output_ch) + { + return RISCV_MATH_SIZE_MISMATCH; + } + /* Run the following code as reference implementation for RISC-V Core without DSP */ + return riscv_depthwise_conv_s8_ref(ctx, + dw_conv_params, + quant_params, + input_dims, + input, + filter_dims, + kernel, + bias_dims, + bias, + output_dims, + output); + + /* Return to application */ + return RISCV_MATH_SUCCESS; +} + +int32_t riscv_depthwise_conv_s8_opt_get_buffer_size_ref(const nmsis_nn_dims *input_dims, + const nmsis_nn_dims *filter_dims) +{ + (void)input_dims; + (void)filter_dims; + return 0; +} + +/** + * @} end of NNConv group + */ diff --git a/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_depthwise_conv_s8_ref.c b/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_depthwise_conv_s8_ref.c new file mode 100644 index 00000000..756179ee --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_depthwise_conv_s8_ref.c @@ -0,0 +1,236 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_depthwise_conv_s8.c + * Description: s8 version of depthwise convolution. + * + * $Date: May 14, 2020 + * $Revision: V.2.0.0 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ +#include "ref_functions.h" +#include "riscv_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +static void depthwise_conv_s8_mult_4_ref(const int8_t *input, + const int32_t input_x, + const int32_t input_y, + const int32_t input_ch, + const int8_t *kernel, + const int32_t output_ch, + const int32_t ch_mult, + const int32_t kernel_x, + const int32_t kernel_y, + const int32_t pad_x, + const int32_t pad_y, + const int32_t stride_x, + const int32_t stride_y, + const int32_t *bias, + int8_t *output, + const int32_t *output_shift, + const int32_t *output_mult, + const int32_t output_x, + const int32_t output_y, + const int32_t output_offset, + const int32_t input_offset, + const int32_t output_activation_min, + const int32_t output_activation_max) +{ + for (int32_t in_h = -pad_y, out_h = 0, out_idx = 0; out_h < output_y; in_h += stride_y, ++out_h) + { + for (int32_t in_w = -pad_x, out_w = 0, ker_h_start = MAX(0, -in_h); out_w < output_x; in_w += stride_x, ++out_w) + { + for (int32_t in_ch = 0, out_ch = 0, ker_w_start = MAX(0, -in_w); out_ch < output_ch; ++in_ch, out_ch += ch_mult) + { + for (int mult_tile = 0; mult_tile < ch_mult; mult_tile += 4) + { + int32_t out_buff[4]; + + out_buff[0] = bias[out_ch + 0 + mult_tile]; + out_buff[1] = bias[out_ch + 1 + mult_tile]; + out_buff[2] = bias[out_ch + 2 + mult_tile]; + out_buff[3] = bias[out_ch + 3 + mult_tile]; + + for (int32_t ker_h = ker_h_start; ker_h < MIN(kernel_y, input_y - in_h); ++ker_h) + { + int32_t ker_idx = ker_h * (output_ch * kernel_x) + ker_w_start * output_ch + out_ch; + int32_t in_idx = (in_h + ker_h) * (input_ch * input_x) + in_w * input_ch + in_ch; + + for (int32_t ker_w = ker_w_start; ker_w < MIN(kernel_x, input_x - in_w); ++ker_w, ker_idx += output_ch) + { + int32_t in_val = input[in_idx + ker_w * input_ch] + input_offset; + out_buff[0] += in_val * kernel[ker_idx + 0 + mult_tile]; + out_buff[1] += in_val * kernel[ker_idx + 1 + mult_tile]; + out_buff[2] += in_val * kernel[ker_idx + 2 + mult_tile]; + out_buff[3] += in_val * kernel[ker_idx + 3 + mult_tile]; + } + } + out_buff[0] = riscv_nn_requantize(out_buff[0], output_mult[out_ch + 0 + mult_tile], output_shift[out_ch + 0 + mult_tile]); + out_buff[1] = riscv_nn_requantize(out_buff[1], output_mult[out_ch + 1 + mult_tile], output_shift[out_ch + 1 + mult_tile]); + out_buff[2] = riscv_nn_requantize(out_buff[2], output_mult[out_ch + 2 + mult_tile], output_shift[out_ch + 2 + mult_tile]); + out_buff[3] = riscv_nn_requantize(out_buff[3], output_mult[out_ch + 3 + mult_tile], output_shift[out_ch + 3 + mult_tile]); + + out_buff[0] += output_offset; + out_buff[1] += output_offset; + out_buff[2] += output_offset; + out_buff[3] += output_offset; + + out_buff[0] = MIN(MAX(out_buff[0], output_activation_min), output_activation_max); + out_buff[1] = MIN(MAX(out_buff[1], output_activation_min), output_activation_max); + out_buff[2] = MIN(MAX(out_buff[2], output_activation_min), output_activation_max); + out_buff[3] = MIN(MAX(out_buff[3], output_activation_min), output_activation_max); + + output[out_idx++] = (int8_t)out_buff[0]; + output[out_idx++] = (int8_t)out_buff[1]; + output[out_idx++] = (int8_t)out_buff[2]; + output[out_idx++] = (int8_t)out_buff[3]; + } + } + } + } +} + +static void depthwise_conv_s8_generic_ref(const q7_t *input, + const uint16_t input_x, + const uint16_t input_y, + const uint16_t input_ch, + const q7_t *kernel, + const uint16_t output_ch, + const uint16_t ch_mult, + const uint16_t kernel_x, + const uint16_t kernel_y, + const uint16_t pad_x, + const uint16_t pad_y, + const uint16_t stride_x, + const uint16_t stride_y, + const int32_t *bias, + q7_t *output, + const int32_t *output_shift, + const int32_t *output_mult, + const uint16_t output_x, + const uint16_t output_y, + const int32_t output_offset, + const int32_t input_offset, + const int32_t output_activation_min, + const int32_t output_activation_max) +{ + (void)output_ch; + int i_out = 0; + for (int i_out_y = 0; i_out_y < output_y; i_out_y++) + { + const int16_t base_idx_y = (i_out_y * stride_y) - pad_y; + for (int i_out_x = 0; i_out_x < output_x; i_out_x++) + { + const int16_t base_idx_x = (i_out_x * stride_x) - pad_x; + for (int i_input_ch = 0; i_input_ch < input_ch; i_input_ch++) + { + for (int i_ch_mult = 0; i_ch_mult < ch_mult; i_ch_mult++) + { + const int idx_out_ch = i_ch_mult + i_input_ch * ch_mult; + int32_t acc_0; + /* Condition for kernel start dimension: (base_idx_ + ker__start) >= 0 */ + const int ker_y_start = MAX(0, -base_idx_y); + const int ker_x_start = MAX(0, -base_idx_x); + /* Condition for kernel end dimension: (base_idx_ + ker__end) < input_ */ + const int ker_y_end = MIN(kernel_y, input_y - base_idx_y); + const int ker_x_end = MIN(kernel_x, input_x - base_idx_x); + acc_0 = bias[idx_out_ch]; + + for (int i_ker_y = ker_y_start; i_ker_y < ker_y_end; i_ker_y++) + { + const int32_t idx_y = base_idx_y + i_ker_y; + for (int i_ker_x = ker_x_start; i_ker_x < ker_x_end; i_ker_x++) + { + const int32_t idx_x = base_idx_x + i_ker_x; + int32_t idx_0 = (idx_y * input_x + idx_x) * input_ch + i_input_ch; + int32_t ker_idx_0 = (i_ker_y * kernel_x + i_ker_x) * (input_ch * ch_mult) + idx_out_ch; + + acc_0 += (input[idx_0] + input_offset) * kernel[ker_idx_0]; + } + } + + /* Requantize and clamp output to provided range */ + acc_0 = riscv_nn_requantize(acc_0, output_mult[idx_out_ch], output_shift[idx_out_ch]); + acc_0 += output_offset; + acc_0 = MAX(acc_0, output_activation_min); + acc_0 = MIN(acc_0, output_activation_max); + + output[i_out++] = acc_0; + } + } + } + } +} + +/* + * Basic s8 depthwise convolution function. + * + * Refer header file for details. + * Optimization using DSP extension is not available for the generic case where channel multiplier is > 1. + * + */ +riscv_status riscv_depthwise_conv_s8_ref(const nmsis_nn_context *ctx, + const nmsis_nn_dw_conv_params *dw_conv_params, + const nmsis_nn_per_channel_quant_params *quant_params, + const nmsis_nn_dims *input_dims, + const q7_t *input, + const nmsis_nn_dims *filter_dims, + const q7_t *kernel, + const nmsis_nn_dims *bias_dims, + const int32_t *bias, + const nmsis_nn_dims *output_dims, + q7_t *output) +{ + (void)dw_conv_params->dilation; + (void)ctx; + + if (dw_conv_params->ch_mult % 4 == 0) + { + depthwise_conv_s8_mult_4_ref(input, input_dims->w, input_dims->h, input_dims->c, kernel, output_dims->c, dw_conv_params->ch_mult, filter_dims->w, filter_dims->h, + dw_conv_params->padding.w, dw_conv_params->padding.h, dw_conv_params->stride.w, dw_conv_params->stride.h, bias, output, + quant_params->shift, quant_params->multiplier, output_dims->w, output_dims->h, dw_conv_params->output_offset, + dw_conv_params->input_offset, dw_conv_params->activation.min, dw_conv_params->activation.max); + } + else + { + depthwise_conv_s8_generic_ref(input, input_dims->w, input_dims->h, input_dims->c, kernel, output_dims->c, dw_conv_params->ch_mult, filter_dims->w, filter_dims->h, + dw_conv_params->padding.w, dw_conv_params->padding.h, dw_conv_params->stride.w, dw_conv_params->stride.h, bias, output, + quant_params->shift, quant_params->multiplier, output_dims->w, output_dims->h, dw_conv_params->output_offset, + dw_conv_params->input_offset, dw_conv_params->activation.min, dw_conv_params->activation.max); + } + + /* Return to application */ + return RISCV_MATH_SUCCESS; +} + +/** + * @} end of NNConv group + */ diff --git a/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_depthwise_conv_u8_basic_ver1_ref.c b/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_depthwise_conv_u8_basic_ver1_ref.c new file mode 100644 index 00000000..3f266b11 --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_depthwise_conv_u8_basic_ver1_ref.c @@ -0,0 +1,295 @@ +/* + * Copyright (C) 2010-2019 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_depthwise_conv_u8_basic_ver1.c + * Description: u8 depthwise convolution function + * + * $Date: May 29, 2020 + * $Revision: V.1.1.0 + * + * Target : RISC-V CPUs + * + * -------------------------------------------------------------------- */ + +#include "ref_functions.h" +#include "riscv_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +static void depthwise_conv_u8_mult_4_ref(const uint8_t *input, + const int32_t input_x, + const int32_t input_y, + const int32_t input_ch, + const uint8_t *kernel, + const int32_t output_ch, + const int32_t ch_mult, + const int32_t kernel_x, + const int32_t kernel_y, + const int32_t pad_x, + const int32_t pad_y, + const int32_t stride_x, + const int32_t stride_y, + const int32_t *bias, + uint8_t *output, + const int32_t output_shift, + const int32_t output_mult, + const int32_t output_x, + const int32_t output_y, + const int32_t output_offset, + const int32_t input_offset, + const int32_t filter_offset, + const int32_t output_activation_min, + const int32_t output_activation_max) +{ + for (int32_t in_h = -pad_y, out_h = 0, out_idx = 0; out_h < output_y; in_h += stride_y, ++out_h) + { + for (int32_t in_w = -pad_x, out_w = 0, ker_h_start = MAX(0, -in_h); out_w < output_x; in_w += stride_x, ++out_w) + { + for (int32_t in_ch = 0, out_ch = 0, ker_w_start = MAX(0, -in_w); out_ch < output_ch; ++in_ch, out_ch += ch_mult) + { + for (int mult_tile = 0; mult_tile < ch_mult; mult_tile += 4) + { + int32_t out_buff[4]; + + out_buff[0] = 0; + out_buff[1] = 0; + out_buff[2] = 0; + out_buff[3] = 0; + + for (int32_t ker_h = ker_h_start; ker_h < MIN(kernel_y, input_y - in_h); ++ker_h) + { + int32_t ker_idx = ker_h * (output_ch * kernel_x) + ker_w_start * output_ch + out_ch; + int32_t in_idx = (in_h + ker_h) * (input_ch * input_x) + in_w * input_ch + in_ch; + + for (int32_t ker_w = ker_w_start; ker_w < MIN(kernel_x, input_x - in_w); ++ker_w, ker_idx += output_ch) + { + int32_t in_val = input[in_idx + ker_w * input_ch] + input_offset; + out_buff[0] += in_val * (kernel[ker_idx + 0 + mult_tile] + filter_offset); + out_buff[1] += in_val * (kernel[ker_idx + 1 + mult_tile] + filter_offset); + out_buff[2] += in_val * (kernel[ker_idx + 2 + mult_tile] + filter_offset); + out_buff[3] += in_val * (kernel[ker_idx + 3 + mult_tile] + filter_offset); + } + } + + if (bias != NULL) + { + out_buff[0] += bias[out_ch + 0 + mult_tile]; + out_buff[1] += bias[out_ch + 1 + mult_tile]; + out_buff[2] += bias[out_ch + 2 + mult_tile]; + out_buff[3] += bias[out_ch + 3 + mult_tile]; + } + out_buff[0] = riscv_nn_requantize(out_buff[0], output_mult, output_shift); + out_buff[1] = riscv_nn_requantize(out_buff[1], output_mult, output_shift); + out_buff[2] = riscv_nn_requantize(out_buff[2], output_mult, output_shift); + out_buff[3] = riscv_nn_requantize(out_buff[3], output_mult, output_shift); + + out_buff[0] += output_offset; + out_buff[1] += output_offset; + out_buff[2] += output_offset; + out_buff[3] += output_offset; + + out_buff[0] = MIN(MAX(out_buff[0], output_activation_min), output_activation_max); + out_buff[1] = MIN(MAX(out_buff[1], output_activation_min), output_activation_max); + out_buff[2] = MIN(MAX(out_buff[2], output_activation_min), output_activation_max); + out_buff[3] = MIN(MAX(out_buff[3], output_activation_min), output_activation_max); + + output[out_idx++] = (uint8_t)out_buff[0]; + output[out_idx++] = (uint8_t)out_buff[1]; + output[out_idx++] = (uint8_t)out_buff[2]; + output[out_idx++] = (uint8_t)out_buff[3]; + } + } + } + } +} + +static void depthwise_conv_u8_generic_ref(const uint8_t *input, + const int32_t input_x, + const int32_t input_y, + const int32_t input_ch, + const uint8_t *kernel, + const int32_t output_ch, + const int32_t ch_mult, + const int32_t kernel_x, + const int32_t kernel_y, + const int32_t pad_x, + const int32_t pad_y, + const int32_t stride_x, + const int32_t stride_y, + const int32_t *bias, + uint8_t *output, + const int32_t output_shift, + const int32_t output_mult, + const int32_t output_x, + const int32_t output_y, + const int32_t output_offset, + const int32_t input_offset, + const int32_t filter_offset, + const int32_t output_activation_min, + const int32_t output_activation_max) +{ + (void)output_ch; + int i_out = 0; + for (int i_out_y = 0; i_out_y < output_y; i_out_y++) + { + const int16_t base_idx_y = (i_out_y * stride_y) - pad_y; + for (int i_out_x = 0; i_out_x < output_x; i_out_x++) + { + const int16_t base_idx_x = (i_out_x * stride_x) - pad_x; + for (int i_input_ch = 0; i_input_ch < input_ch; i_input_ch++) + { + for (int i_ch_mult = 0; i_ch_mult < ch_mult; i_ch_mult++) + { + const int idx_out_ch = i_ch_mult + i_input_ch * ch_mult; + int32_t acc_0; + /* Condition for kernel start dimension: (base_idx_ + ker__start) >= 0 */ + const int ker_y_start = MAX(0, -base_idx_y); + const int ker_x_start = MAX(0, -base_idx_x); + /* Condition for kernel end dimension: (base_idx_ + ker__end) < input_ */ + const int ker_y_end = MIN(kernel_y, input_y - base_idx_y); + const int ker_x_end = MIN(kernel_x, input_x - base_idx_x); + acc_0 = 0; + + for (int i_ker_y = ker_y_start; i_ker_y < ker_y_end; i_ker_y++) + { + const int32_t idx_y = base_idx_y + i_ker_y; + for (int i_ker_x = ker_x_start; i_ker_x < ker_x_end; i_ker_x++) + { + const int32_t idx_x = base_idx_x + i_ker_x; + int32_t idx_0 = (idx_y * input_x + idx_x) * input_ch + i_input_ch; + int32_t ker_idx_0 = (i_ker_y * kernel_x + i_ker_x) * (input_ch * ch_mult) + idx_out_ch; + + acc_0 += (input[idx_0] + input_offset) * (kernel[ker_idx_0] + filter_offset); + } + } + if (bias != NULL) + { + acc_0 += bias[idx_out_ch]; + } + + /* Requantize and clamp output to provided range */ + acc_0 = riscv_nn_requantize(acc_0, output_mult, output_shift); + acc_0 += output_offset; + acc_0 = MAX(acc_0, output_activation_min); + acc_0 = MIN(acc_0, output_activation_max); + + output[i_out++] = acc_0; + } + } + } + } +} + +/** + * @brief uint8 depthwise convolution function with asymmetric quantization + * + * @param[in] input Pointer to input tensor + * @param[in] input_x Width of input tensor + * @param[in] input_y Height of input tensor + * @param[in] input_ch Channels in input tensor + * @param[in] kernel Pointer to kernel weights + * @param[in] kernel_x Width of kernel + * @param[in] kernel_y Height of kernel + * @param[in] ch_mult Number of channel multiplier + * @param[in] pad_x Padding sizes x + * @param[in] pad_y Padding sizes y + * @param[in] stride_x Convolution stride along the width + * @param[in] stride_y Convolution stride along the height + * @param[in] dilation_x Dilation along width. Not used and intended for future enhancement. + * @param[in] dilation_y Dilation along height. Not used and intended for future enhancement. + * @param[in] bias Pointer to optional bias values. If no bias is + * availble, NULL is expected + * @param[in] input_offset Input tensor zero offset + * @param[in] filter_offset Kernel tensor zero offset + * @param[in] output_offset Output tensor zero offset + * @param[in,out] output Pointer to output tensor + * @param[in] output_x Width of output tensor + * @param[in] output_y Height of output tensor + * @param[in] output_activation_min Minimum value to clamp the output to. Range : {0, 255} + * @param[in] output_activation_max Minimum value to clamp the output to. Range : {0, 255} + * @param[in] output_shift Amount of right-shift for output + * @param[in] output_mult Output multiplier for requantization + * @return The function returns one of the following + * RISCV_MATH_SIZE_MISMATCH - Not supported dimension of tensors + * RISCV_MATH_SUCCESS - Successful operation + * RISCV_MATH_ARGUMENT_ERROR - Implementation not available + * + * + */ + +riscv_status riscv_depthwise_conv_u8_basic_ver1_ref(const uint8_t *input, + const uint16_t input_x, + const uint16_t input_y, + const uint16_t input_ch, + const uint8_t *kernel, + const uint16_t kernel_x, + const uint16_t kernel_y, + const int16_t ch_mult, + const int16_t pad_x, + const int16_t pad_y, + const int16_t stride_x, + const int16_t stride_y, + const int16_t dilation_x, + const int16_t dilation_y, + const int32_t *bias, + const int32_t input_offset, + const int32_t filter_offset, + const int32_t output_offset, + uint8_t *output, + const uint16_t output_x, + const uint16_t output_y, + const int32_t output_activation_min, + const int32_t output_activation_max, + const int32_t output_shift, + const int32_t output_mult) +{ + (void)dilation_x; + (void)dilation_y; + + if (ch_mult % 4 == 0) + { + depthwise_conv_u8_mult_4_ref(input, input_x, input_y, input_ch, kernel, ch_mult * input_ch, ch_mult, + kernel_x, kernel_y, pad_x, pad_y, stride_x, stride_y, bias, output, + output_shift, output_mult, output_x, output_y, output_offset, input_offset, + filter_offset, output_activation_min, output_activation_max); + } + else + { + depthwise_conv_u8_generic_ref(input, input_x, input_y, input_ch, kernel, ch_mult * input_ch, ch_mult, + kernel_x, kernel_y, pad_x, pad_y, stride_x, stride_y, bias, + output, output_shift, output_mult, output_x, output_y, output_offset, + input_offset, filter_offset, output_activation_min, output_activation_max); + } + + /* Return to application */ + return RISCV_MATH_SUCCESS; +} + +/** + * @} end of NNConv group + */ diff --git a/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_depthwise_conv_wrapper_s8_ref.c b/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_depthwise_conv_wrapper_s8_ref.c new file mode 100644 index 00000000..7b0bbbd4 --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_depthwise_conv_wrapper_s8_ref.c @@ -0,0 +1,130 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_depthwise_conv_wrapper_s8.c + * Description: Wrapper API to select appropriate depthwise conv API based + * on dimensions. + * + * $Date: May 29, 2020 + * $Revision: V.1.0.1 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ +#include "ref_functions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/* + * s8 Depthwise conv wrapper function + * + * Refer header file for details. + * + */ +riscv_status riscv_depthwise_conv_wrapper_s8_ref(const nmsis_nn_context *ctx, + const nmsis_nn_dw_conv_params *dw_conv_params, + const nmsis_nn_per_channel_quant_params *quant_params, + const nmsis_nn_dims *input_dims, + const q7_t *input, + const nmsis_nn_dims *filter_dims, + const q7_t *filter, + const nmsis_nn_dims *bias_dims, + const int32_t *bias, + const nmsis_nn_dims *output_dims, + q7_t *output) +{ + riscv_status status = RISCV_MATH_SUCCESS; + if (1 == dw_conv_params->ch_mult) + { + if ((filter_dims->w == 3) && (filter_dims->h == 3) && (dw_conv_params->padding.h <= 1)) + { + status = riscv_depthwise_conv_3x3_s8_ref(ctx, + quant_params, + dw_conv_params, + input_dims, + input, + filter_dims, + filter, + bias_dims, + bias, + output_dims, + output); + } + else + { + status = riscv_depthwise_conv_s8_opt_ref(ctx, + dw_conv_params, + quant_params, + input_dims, + input, + filter_dims, + filter, + bias_dims, + bias, + output_dims, + output); + } + } + else + { + status = riscv_depthwise_conv_s8_ref(ctx, + dw_conv_params, + quant_params, + input_dims, + input, + filter_dims, + filter, + bias_dims, + bias, + output_dims, + output); + } + + /* Return to application */ + return status; +} + +int32_t riscv_depthwise_conv_wrapper_s8_get_buffer_size_ref(const nmsis_nn_dw_conv_params *dw_conv_params, + const nmsis_nn_dims *input_dims, + const nmsis_nn_dims *filter_dims, + const nmsis_nn_dims *output_dims) +{ + (void)dw_conv_params; + int32_t size = 0; + + if (input_dims->c == output_dims->c) + { + size = riscv_depthwise_conv_s8_opt_get_buffer_size_ref(input_dims, filter_dims); + } + + return size; +} + +/** + * @} end of NNConv group + */ diff --git a/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_depthwise_separable_conv_HWC_q7_nonsquare_ref.c b/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_depthwise_separable_conv_HWC_q7_nonsquare_ref.c new file mode 100644 index 00000000..5edd9ce7 --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_depthwise_separable_conv_HWC_q7_nonsquare_ref.c @@ -0,0 +1,142 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_depthwise_separable_conv_HWC_q7_nonsquare.c + * Description: Q7 depthwise separable convolution function (non-square shape) + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "ref_functions.h" +#include "riscv_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/** + * @brief Q7 depthwise separable convolution function (non-square shape) + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in_x input tensor dimention x + * @param[in] dim_im_in_y input tensor dimention y + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel_x filter kernel size x + * @param[in] dim_kernel_y filter kernel size y + * @param[in] padding_x padding sizes x + * @param[in] padding_y padding sizes y + * @param[in] stride_x convolution stride x + * @param[in] stride_y convolution stride y + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out_x output tensor dimension x + * @param[in] dim_im_out_y output tensor dimension y + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * RISCV_MATH_SIZE_MISMATCH or RISCV_MATH_SUCCESS based on the outcome of size checking. + * + * This function is the version with full list of optimization tricks, but with + * some contraints: + * ch_im_in is equal to ch_im_out + * + */ + +riscv_status riscv_depthwise_separable_conv_HWC_q7_nonsquare_ref(const q7_t * Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q7_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q7_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t * Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t * bufferA, + q7_t * bufferB) +{ + + (void)bufferB; + + /* Run the following code as reference implementation for RISC-V Core without DSP */ + int i_out_y, i_out_x, i_ch_out; + int i_ker_y, i_ker_x; + + /* do some checking here, basically ch_im_in == ch_im_out */ + if (ch_im_in != ch_im_out) + { + return RISCV_MATH_SIZE_MISMATCH; + } + + for (i_out_y = 0; i_out_y < dim_im_out_y; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out_x; i_out_x++) + { + for (i_ch_out = 0; i_ch_out < ch_im_out; i_ch_out++) + { + // for each output + int conv_out = ((q31_t)(bias[i_ch_out]) << bias_shift) + NN_ROUND(out_shift); + for (i_ker_y = 0; i_ker_y < dim_kernel_y; i_ker_y++) + { + for (i_ker_x = 0; i_ker_x < dim_kernel_x; i_ker_x++) + { + int in_row = stride_y * i_out_y + i_ker_y - padding_y; + int in_col = stride_x * i_out_x + i_ker_x - padding_x; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in_y && in_col < dim_im_in_x) + { + conv_out += Im_in[(in_row * dim_im_in_x + in_col) * ch_im_in + i_ch_out] * + wt[(i_ker_y * dim_kernel_x + i_ker_x) * ch_im_out + i_ch_out]; + } + } + } + Im_out[(i_out_y * dim_im_out_x + i_out_x) * ch_im_out + i_ch_out] = + (q7_t) __SSAT((conv_out >> out_shift), 8); + } + } + } + /* Return to application */ + return RISCV_MATH_SUCCESS; + +} + +/** + * @} end of NNConv group + */ diff --git a/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_depthwise_separable_conv_HWC_q7_ref.c b/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_depthwise_separable_conv_HWC_q7_ref.c new file mode 100644 index 00000000..344ac9de --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_depthwise_separable_conv_HWC_q7_ref.c @@ -0,0 +1,149 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_depthwise_separable_conv_HWC_q7.c + * Description: Q7 depthwise separable convolution function + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "ref_functions.h" +#include "riscv_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/** + * @brief Q7 depthwise separable convolution function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimention + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * RISCV_MATH_SIZE_MISMATCH or RISCV_MATH_SUCCESS based on the outcome of size checking. + * + * @details + * + * Buffer size: + * + * bufferA size: 2*ch_im_in*dim_kernel*dim_kernel + * + * bufferB size: 0 + * + * Input dimension constraints: + * + * ch_im_in equals ch_im_out + * + * Implementation: + * There are 3 nested loop here: + * Inner loop: calculate each output value with MAC instruction over an accumulator + * Mid loop: loop over different output channel + * Outer loop: loop over different output (x, y) + */ +// +// REMOVED +// +// riscv_status riscv_depthwise_separable_conv_HWC_q7_ref(const q7_t * Im_in, +// const uint16_t dim_im_in, +// const uint16_t ch_im_in, +// const q7_t * wt, +// const uint16_t ch_im_out, +// const uint16_t dim_kernel, +// const uint16_t padding, +// const uint16_t stride, +// const q7_t * bias, +// const uint16_t bias_shift, +// const uint16_t out_shift, +// q7_t * Im_out, +// const uint16_t dim_im_out, +// q15_t * bufferA, +// q7_t * bufferB) +// { +// (void)bufferB; +// /* Run the following code as reference implementation for RISC-V Core without DSP */ +// int i_out_y, i_out_x, i_ch_out, i_ker_x, i_ker_y; +// int conv_out; + +// /* do some checking here, basically ch_im_in == ch_im_out */ +// if (ch_im_in != ch_im_out) +// { +// return RISCV_MATH_SIZE_MISMATCH; +// } + +// for (i_out_y = 0; i_out_y < dim_im_out; i_out_y++) +// { +// for (i_out_x = 0; i_out_x < dim_im_out; i_out_x++) +// { +// for (i_ch_out = 0; i_ch_out < ch_im_out; i_ch_out++) +// { +// // for each output +// conv_out = ((q31_t)(bias[i_ch_out]) << bias_shift) + NN_ROUND(out_shift); +// for (i_ker_y = 0; i_ker_y < dim_kernel; i_ker_y++) +// { +// for (i_ker_x = 0; i_ker_x < dim_kernel; i_ker_x++) +// { +// int in_row = stride * i_out_y + i_ker_y - padding; +// int in_col = stride * i_out_x + i_ker_x - padding; +// if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in && in_col < dim_im_in) +// { +// conv_out += +// Im_in[(in_row * +// dim_im_in + +// in_col) * +// ch_im_in + +// i_ch_out] * wt[(i_ker_y * dim_kernel + i_ker_x) * ch_im_out + i_ch_out]; +// } +// } +// } +// Im_out[(i_out_y * dim_im_out + +// i_out_x) * ch_im_out + i_ch_out] = (q7_t) __SSAT((conv_out >> out_shift), 8); +// } +// } +// } +// /* Return to application */ +// return RISCV_MATH_SUCCESS; + +// } + +/** + * @} end of NNConv group + */ diff --git a/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_nn_depthwise_conv_s8_core_ref.c b/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_nn_depthwise_conv_s8_core_ref.c new file mode 100644 index 00000000..309c39bd --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_nn_depthwise_conv_s8_core_ref.c @@ -0,0 +1,66 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_nn_depthwise_conv_s8_core.c + * Description: Depthwise convolution on im2col buffers. + * + * $Date: May 29, 2020 + * $Revision: V.1.0.3 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ + +#include "riscv_nnsupportfunctions.h" +#include "ref_functions.h" + +/* + * Depthwise conv on an im2col buffer where the input channel equals + * output channel. + * + * Refer header file for details. + * + */ + +q7_t *riscv_nn_depthwise_conv_s8_core_ref(const q7_t *row, + const q15_t *col, + const uint16_t num_ch, + const int32_t *out_shift, + const int32_t *out_mult, + const int32_t out_offset, + const int32_t activation_min, + const int32_t activation_max, + const uint16_t kernel_size, + const int32_t *const output_bias, + q7_t *out) +{ + (void)row; + (void)col; + (void)num_ch; + (void)out_shift; + (void)out_mult; + (void)out_offset; + (void)activation_min; + (void)activation_max; + (void)kernel_size; + (void)output_bias; + (void)out; + return NULL; +} diff --git a/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_nn_mat_mult_kernel_q7_q15_ref.c b/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_nn_mat_mult_kernel_q7_q15_ref.c new file mode 100644 index 00000000..3de0ce22 --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_nn_mat_mult_kernel_q7_q15_ref.c @@ -0,0 +1,53 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_nn_mat_mult_kernel_q7_q15.c + * Description: Matrix-multiplication function for convolution + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ + +#include "ref_functions.h" +#include "riscv_nnsupportfunctions.h" + + /** + * @brief Matrix-multiplication function for convolution. + * + * @details Refer to header file for details. + * + */ + +q7_t *riscv_nn_mat_mult_kernel_q7_q15_ref(const q7_t * pA, + const q15_t * pInBuffer, + const uint16_t ch_im_out, + const uint16_t numCol_A, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t * bias, + q7_t * pOut) +{ + /* To be completed */ + return NULL; + +} diff --git a/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_nn_mat_mult_kernel_q7_q15_reordered_ref.c b/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_nn_mat_mult_kernel_q7_q15_reordered_ref.c new file mode 100644 index 00000000..dfb2e6c9 --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_nn_mat_mult_kernel_q7_q15_reordered_ref.c @@ -0,0 +1,53 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_nn_mat_mult_kernel_q7_q15_reordered.c + * Description: Matrix-multiplication function for convolution with reordered columns + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ + +#include "ref_functions.h" +#include "riscv_nnsupportfunctions.h" + + /** + * @brief Matrix-multiplication function for convolution with re-ordered input. + * + * @details Refer to header file for details. + * + */ + +q7_t *riscv_nn_mat_mult_kernel_q7_q15_reordered_ref(const q7_t * pA, + const q15_t * pInBuffer, + const uint16_t ch_im_out, + const uint16_t numCol_A, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t * bias, + q7_t * pOut) +{ + + /* To be completed */ + return NULL; +} diff --git a/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_nn_mat_mult_kernel_q7_reordered_ref.c b/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_nn_mat_mult_kernel_q7_reordered_ref.c new file mode 100644 index 00000000..c5c516ee --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_nn_mat_mult_kernel_q7_reordered_ref.c @@ -0,0 +1,64 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_nn_mat_mult_kernel_q7_q15_reordered.c + * Description: Matrix-multiplication function for convolution with reordered columns + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ + +#include "ref_functions.h" +#include "riscv_math.h" + + /** + * @brief Matrix-multiplication function for convolution with reordered columns + * @param[in] pA pointer to operand A + * @param[in] pInBuffer pointer to operand B, always conssists of 2 vectors + * @param[in] ch_im_out numRow of A + * @param[in] numCol_A numCol of A + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias the bias + * @param[in,out] pOut pointer to output + * @return The function returns the incremented output pointer + * + * @details + * + * This function assumes that data in pInBuffer are reordered + */ + +q7_t *riscv_nn_mat_mult_kernel_q7_reordered_ref(const q7_t * pA, + const q7_t * pInBuffer, + const uint16_t ch_im_out, + const uint16_t numCol_A, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t * bias, + q7_t * pOut) +{ + + + /* To be completed */ + return NULL; +} diff --git a/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_nn_mat_mult_kernel_s8_s16_ref.c b/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_nn_mat_mult_kernel_s8_s16_ref.c new file mode 100644 index 00000000..a03684c5 --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_nn_mat_mult_kernel_s8_s16_ref.c @@ -0,0 +1,67 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_nn_mat_mult_kernel_s8_s16.c + * Description: Matrix-multiplication function for convolution + * + * $Date: May 29, 2020 + * $Revision: V.1.0.2 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ + +#include "ref_functions.h" +#include "riscv_nnsupportfunctions.h" + + +/* + * Matrix-multiplication function for convolution with per-channel requantization. + * + * Refer header file for details. + * + */ + +q7_t *riscv_nn_mat_mult_kernel_s8_s16_ref(const q7_t *input_a, + const q15_t *input_b, + const uint16_t output_ch, + const int32_t *out_shift, + const int32_t *out_mult, + const int32_t out_offset, + const int16_t activation_min, + const int16_t activation_max, + const uint16_t num_col_a, + const int32_t *const output_bias, + q7_t *out_0) +{ + (void)input_a; + (void)input_b; + (void)output_ch; + (void)out_shift; + (void)out_mult; + (void)out_offset; + (void)activation_min; + (void)activation_max; + (void)num_col_a; + (void)output_bias; + (void)out_0; + /* To be completed */ + return NULL; +} diff --git a/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_nn_mat_mult_kernel_s8_s16_reordered_ref.c b/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_nn_mat_mult_kernel_s8_s16_reordered_ref.c new file mode 100644 index 00000000..f613ee98 --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_nn_mat_mult_kernel_s8_s16_reordered_ref.c @@ -0,0 +1,69 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_nn_mat_mult_kernel_s8_s16_reordered.c + * Description: Matrix-multiplication function for convolution with reordered columns + * + * $Date: February 27, 2020 + * $Revision: V.1.0.2 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ + +#include "ref_functions.h" +#include "riscv_nnsupportfunctions.h" + +/* + * Matrix-multiplication with re-ordered input and bias inputs for convolution with per-channel + * requantization. The re-ordering is a consequence of sign extension is done by the SXTB16 command. + * + * Refer header file for details. This function differs from riscv_nn_mat_mult_kernel_s8_s16(), in that it uses + * read_and_pad_reordered() instead of riscv_nn_mat_mult_kernel_s8_s16(). Investigating the cycles impact and + * unifying these two functions is a potential future improvement. + * + */ + +q7_t *riscv_nn_mat_mult_kernel_s8_s16_reordered_ref(const q7_t *input_a, + const q15_t *input_b, + const uint16_t output_ch, + const int32_t *out_shift, + const int32_t *out_mult, + const int32_t out_offset, + const int16_t activation_min, + const int16_t activation_max, + const uint16_t num_col_a, + const int32_t *const output_bias, + q7_t *out_0) +{ + (void)input_a; + (void)input_b; + (void)output_ch; + (void)out_shift; + (void)out_mult; + (void)out_offset; + (void)activation_min; + (void)activation_max; + (void)num_col_a; + (void)output_bias; + (void)out_0; + /* To be completed */ + return NULL; +} diff --git a/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_nn_mat_mult_s8_ref.c b/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_nn_mat_mult_s8_ref.c new file mode 100644 index 00000000..6548171f --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/ConvolutionFunctions/riscv_nn_mat_mult_s8_ref.c @@ -0,0 +1,71 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_nn_mat_mult_s8.c + * Description: General Matrix-multiplication function + * + * $Date: July 27, 2020 + * $Revision: V.2.0.4 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ + +#include "riscv_nnsupportfunctions.h" +#include "ref_functions.h" + +/* + * s8 General matrix multiplication function with per-channel requantization for upto 4 column batches. + * + * Refer header file for details. + * + */ + +q7_t *riscv_nn_mat_mult_s8_ref(const q7_t *input_row, + const q7_t *input_col, + const uint16_t output_ch, + const uint16_t col_batches, + const int32_t *output_shift, + const int32_t *output_mult, + const int32_t out_offset, + const int32_t col_offset, + const int32_t row_offset, + const int16_t activation_min, + const int16_t activation_max, + const uint16_t row_len, + const int32_t *const bias, + q7_t *out) +{ + (void)input_row; + (void)input_col; + (void)output_ch; + (void)col_batches; + (void)output_shift; + (void)output_mult; + (void)out_offset; + (void)col_offset; + (void)row_offset; + (void)activation_min; + (void)activation_max; + (void)row_len; + (void)bias; + (void)out; + return NULL; +} diff --git a/examples/nn/nnTest/Ref_Implementations/FullyConnectedFunctions/riscv_fully_connected_mat_q7_vec_q15_opt_ref.c b/examples/nn/nnTest/Ref_Implementations/FullyConnectedFunctions/riscv_fully_connected_mat_q7_vec_q15_opt_ref.c new file mode 100644 index 00000000..fe7de3ad --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/FullyConnectedFunctions/riscv_fully_connected_mat_q7_vec_q15_opt_ref.c @@ -0,0 +1,218 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_fully_connected_mat_q7_vec_q15_opt.c + * Description: Mixed Q15-Q7 opt fully-connected layer function + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "ref_functions.h" +#include "riscv_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup FC + * @{ + */ + + /** + * @brief Mixed Q15-Q7 opt fully-connected layer function + * @param[in] pV pointer to input vector + * @param[in] pM pointer to matrix weights + * @param[in] dim_vec length of the vector + * @param[in] num_of_rows number of rows in weight matrix + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias pointer to bias + * @param[in,out] pOut pointer to output vector + * @param[in,out] vec_buffer pointer to buffer space for input + * @return The function returns RISCV_MATH_SUCCESS + * + * @details + * + * Buffer size: + * + * vec_buffer size: 0 + * + * Q7_Q15 version of the fully connected layer + * + * Weights are in q7_t and Activations are in q15_t + * + * Limitation: x4 version requires weight reordering to work + * + * Here we use only one pointer to read 4 rows in the weight + * matrix. So if the original q7_t matrix looks like this: + * + * | a11 | a12 | a13 | a14 | a15 | a16 | a17 | + * + * | a21 | a22 | a23 | a24 | a25 | a26 | a27 | + * + * | a31 | a32 | a33 | a34 | a35 | a36 | a37 | + * + * | a41 | a42 | a43 | a44 | a45 | a46 | a47 | + * + * | a51 | a52 | a53 | a54 | a55 | a56 | a57 | + * + * | a61 | a62 | a63 | a64 | a65 | a66 | a67 | + * + * We operates on multiple-of-4 rows, so the first four rows becomes + * + * | a11 | a21 | a12 | a22 | a31 | a41 | a32 | a42 | + * + * | a13 | a23 | a14 | a24 | a33 | a43 | a34 | a44 | + * + * | a15 | a25 | a16 | a26 | a35 | a45 | a36 | a46 | + * + * The column left over will be in-order. + * which is: + * | a17 | a27 | a37 | a47 | + * + * For the left-over rows, we do 1x1 computation, so the data remains + * as its original order. + * + * So the stored weight matrix looks like this: + * + * | a11 | a21 | a12 | a22 | a31 | a41 | + * + * | a32 | a42 | a13 | a23 | a14 | a24 | + * + * | a33 | a43 | a34 | a44 | a15 | a25 | + * + * | a16 | a26 | a35 | a45 | a36 | a46 | + * + * | a17 | a27 | a37 | a47 | a51 | a52 | + * + * | a53 | a54 | a55 | a56 | a57 | a61 | + * + * | a62 | a63 | a64 | a65 | a66 | a67 | + * + */ + +// REMOVED + +// riscv_status +// riscv_fully_connected_mat_q7_vec_q15_opt_ref(const q15_t * pV, +// const q7_t * pM, +// const uint16_t dim_vec, +// const uint16_t num_of_rows, +// const uint16_t bias_shift, +// const uint16_t out_shift, const q7_t * bias, q15_t * pOut, q15_t * vec_buffer) +// { + +// (void)vec_buffer; +// /* Run the following code as reference implementation for RISC-V Core without DSP */ +// uint16_t rowCnt = num_of_rows >> 2; +// const q7_t *pB = pM; +// const q15_t *pA; +// q15_t *pO = pOut; +// const q7_t *pBias = bias; + +// while (rowCnt) +// { +// q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); +// q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); +// q31_t sum3 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); +// q31_t sum4 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); +// uint16_t colCnt = dim_vec >> 1; + +// pA = pV; + +// while (colCnt) +// { +// q15_t inA1 = *pA++; +// q15_t inA2 = *pA++; + +// q7_t inB1 = *pB++; +// q7_t inB3 = *pB++; +// q7_t inB2 = *pB++; +// q7_t inB4 = *pB++; + +// sum += inA1 * inB1 + inA2 * inB2; +// sum2 += inA1 * inB3 + inA2 * inB4; + +// inB1 = *pB++; +// inB3 = *pB++; +// inB2 = *pB++; +// inB4 = *pB++; + +// sum3 += inA1 * inB1 + inA2 * inB2; +// sum4 += inA1 * inB3 + inA2 * inB4; + +// colCnt--; +// } + +// colCnt = dim_vec & 0x1; +// while (colCnt) +// { +// q15_t inA = *pA++; +// q7_t inB = *pB++; +// sum += inA * inB; +// inB = *pB++; +// sum2 += inA * inB; +// inB = *pB++; +// sum3 += inA * inB; +// inB = *pB++; +// sum4 += inA * inB; + +// colCnt--; +// } +// *pO++ = (q15_t) __SSAT((sum >> out_shift), 16); +// *pO++ = (q15_t) __SSAT((sum2 >> out_shift), 16); +// *pO++ = (q15_t) __SSAT((sum3 >> out_shift), 16); +// *pO++ = (q15_t) __SSAT((sum4 >> out_shift), 16); + +// rowCnt--; +// } + +// rowCnt = num_of_rows & 0x3; + +// while (rowCnt) +// { +// int ip_out = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); +// int j; + +// pA = pV; +// for (j = 0; j < dim_vec; j++) +// { +// q15_t inA = *pA++; +// q7_t inB = *pB++; +// ip_out += inA * inB; +// } +// *pO++ = (q15_t) __SSAT((ip_out >> out_shift), 16); + +// rowCnt--; +// } +// /* Return to RISCV_MATH_SUCCESS */ +// return (RISCV_MATH_SUCCESS); + +// } + +/** + * @} end of FC group + */ diff --git a/examples/nn/nnTest/Ref_Implementations/FullyConnectedFunctions/riscv_fully_connected_mat_q7_vec_q15_ref.c b/examples/nn/nnTest/Ref_Implementations/FullyConnectedFunctions/riscv_fully_connected_mat_q7_vec_q15_ref.c new file mode 100644 index 00000000..9a7a2a1c --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/FullyConnectedFunctions/riscv_fully_connected_mat_q7_vec_q15_ref.c @@ -0,0 +1,102 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_fully_connected_mat_q7_vec_q15.c + * Description: Mixed Q15-Q7 fully-connected layer function + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "ref_functions.h" +#include "riscv_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup FC + * @{ + */ + + /** + * @brief Mixed Q15-Q7 fully-connected layer function + * @param[in] pV pointer to input vector + * @param[in] pM pointer to matrix weights + * @param[in] dim_vec length of the vector + * @param[in] num_of_rows number of rows in weight matrix + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias pointer to bias + * @param[in,out] pOut pointer to output vector + * @param[in,out] vec_buffer pointer to buffer space for input + * @return The function returns RISCV_MATH_SUCCESS + * + * @details + * + * Buffer size: + * + * vec_buffer size: 0 + * + * Q7_Q15 version of the fully connected layer + * + * Weights are in q7_t and Activations are in q15_t + * + */ + + // REMOVED + +// riscv_status +// riscv_fully_connected_mat_q7_vec_q15_ref(const q15_t * pV, +// const q7_t * pM, +// const uint16_t dim_vec, +// const uint16_t num_of_rows, +// const uint16_t bias_shift, +// const uint16_t out_shift, +// const q7_t * bias, +// q15_t * pOut, +// q15_t * vec_buffer) +// { +// (void)vec_buffer; +// int i, j; +// /* Run the following code as reference implementation for RISC-V Core without DSP */ +// for (i = 0; i < num_of_rows; i++) +// { +// int ip_out = ((q31_t)(bias[i]) << bias_shift) + NN_ROUND(out_shift); +// for (j = 0; j < dim_vec; j++) +// { +// ip_out += pV[j] * pM[i * dim_vec + j]; +// } +// pOut[i] = (q15_t) __SSAT((ip_out >> out_shift), 16); +// } + +// /* Return to RISCV_MATH_SUCCESS */ +// return (RISCV_MATH_SUCCESS); + +// } + +/** + * @} end of FC group + */ diff --git a/examples/nn/nnTest/Ref_Implementations/FullyConnectedFunctions/riscv_fully_connected_q15_opt_ref.c b/examples/nn/nnTest/Ref_Implementations/FullyConnectedFunctions/riscv_fully_connected_q15_opt_ref.c new file mode 100644 index 00000000..370e3aba --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/FullyConnectedFunctions/riscv_fully_connected_q15_opt_ref.c @@ -0,0 +1,197 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_fully_connected_q15_opt.c + * Description: Q15 opt fully-connected layer function + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "ref_functions.h" +#include "riscv_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup FC + * @{ + */ + + /** + * @brief Q15 opt fully-connected layer function + * @param[in] pV pointer to input vector + * @param[in] pM pointer to matrix weights + * @param[in] dim_vec length of the vector + * @param[in] num_of_rows number of rows in weight matrix + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias pointer to bias + * @param[in,out] pOut pointer to output vector + * @param[in,out] vec_buffer pointer to buffer space for input + * @return The function returns RISCV_MATH_SUCCESS + * + * + * @details + * + * Buffer size: + * + * vec_buffer size: 0 + * + * Here we use only one pointer to read 4 rows in the weight + * matrix. So if the original matrix looks like this: + * + * | a11 | a12 | a13 | + * + * | a21 | a22 | a23 | + * + * | a31 | a32 | a33 | + * + * | a41 | a42 | a43 | + * + * | a51 | a52 | a53 | + * + * | a61 | a62 | a63 | + * + * We operates on multiple-of-4 rows, so the first four rows becomes + * + * | a11 | a12 | a21 | a22 | a31 | a32 | a41 | a42 | + * + * | a13 | a23 | a33 | a43 | + * + * Remaining rows are kept the same original order. + * + * So the stored weight matrix looks like this: + * + * + * | a11 | a12 | a21 | a22 | a31 | a32 | a41 | a42 | + * + * | a13 | a23 | a33 | a43 | a51 | a52 | a53 | a61 | + * + * | a62 | a63 | + */ + + // REMOVED + +// riscv_status +// riscv_fully_connected_q15_opt_ref(const q15_t * pV, +// const q15_t * pM, +// const uint16_t dim_vec, +// const uint16_t num_of_rows, +// const uint16_t bias_shift, +// const uint16_t out_shift, +// const q15_t * bias, +// q15_t * pOut, +// q15_t * vec_buffer) +// { +// (void)vec_buffer; +// /* Run the following code as reference implementation for RISC-V Core without DSP */ +// uint16_t rowCnt = num_of_rows >> 2; +// const q15_t *pB = pM; +// const q15_t *pA; +// q15_t *pO = pOut; +// const q15_t *pBias = bias; + +// while (rowCnt) +// { +// q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); +// q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); +// q31_t sum3 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); +// q31_t sum4 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + +// uint16_t colCnt = dim_vec >> 1; + +// pA = pV; +// while (colCnt) +// { +// q15_t inA1 = *pA++; +// q15_t inA2 = *pA++; + +// q15_t inB1 = *pB++; +// q15_t inB2 = *pB++; +// sum += inA1 * inB1 + inA2 * inB2; + +// inB1 = *pB++; +// inB2 = *pB++; +// sum2 += inA1 * inB1 + inA2 * inB2; + +// inB1 = *pB++; +// inB2 = *pB++; +// sum3 += inA1 * inB1 + inA2 * inB2; + +// inB1 = *pB++; +// inB2 = *pB++; +// sum4 += inA1 * inB1 + inA2 * inB2; + +// colCnt--; +// } +// colCnt = dim_vec & 0x1; +// while (colCnt) +// { +// q15_t inA = *pA++; +// q15_t inB = *pB++; +// sum += inA * inB; +// inB = *pB++; +// sum2 += inA * inB; +// inB = *pB++; +// sum3 += inA * inB; +// inB = *pB++; +// sum4 += inA * inB; +// colCnt--; +// } +// *pO++ = (q15_t) __SSAT((sum >> out_shift), 16); +// *pO++ = (q15_t) __SSAT((sum2 >> out_shift), 16); +// *pO++ = (q15_t) __SSAT((sum3 >> out_shift), 16); +// *pO++ = (q15_t) __SSAT((sum4 >> out_shift), 16); + +// rowCnt--; +// } +// rowCnt = num_of_rows & 0x3; + +// while (rowCnt) +// { +// int ip_out = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); +// int j; + +// pA = pV; +// for (j = 0; j < dim_vec; j++) +// { +// q15_t inA = *pA++; +// q15_t inB = *pB++; +// ip_out += inA * inB; +// } +// *pO++ = (q15_t) __SSAT((ip_out >> out_shift), 16); + +// rowCnt--; +// } +// /* Return to RISCV_MATH_SUCCESS */ +// return (RISCV_MATH_SUCCESS); + +// } + +/** + * @} end of FC group + */ diff --git a/examples/nn/nnTest/Ref_Implementations/FullyConnectedFunctions/riscv_fully_connected_q15_ref.c b/examples/nn/nnTest/Ref_Implementations/FullyConnectedFunctions/riscv_fully_connected_q15_ref.c new file mode 100644 index 00000000..26018722 --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/FullyConnectedFunctions/riscv_fully_connected_q15_ref.c @@ -0,0 +1,98 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_fully_connected_q15.c + * Description: Q15 basic fully-connected layer function + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "ref_functions.h" +#include "riscv_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup FC + * @{ + */ + + /** + * @brief Q15 opt fully-connected layer function + * @param[in] pV pointer to input vector + * @param[in] pM pointer to matrix weights + * @param[in] dim_vec length of the vector + * @param[in] num_of_rows number of rows in weight matrix + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias pointer to bias + * @param[in,out] pOut pointer to output vector + * @param[in,out] vec_buffer pointer to buffer space for input + * @return The function returns RISCV_MATH_SUCCESS + * + * + * @details + * + * Buffer size: + * + * vec_buffer size: 0 + * + */ + + // REMOVED + +// riscv_status +// riscv_fully_connected_q15_ref(const q15_t * pV, +// const q15_t * pM, +// const uint16_t dim_vec, +// const uint16_t num_of_rows, +// const uint16_t bias_shift, +// const uint16_t out_shift, +// const q15_t * bias, +// q15_t * pOut, +// q15_t * vec_buffer) +// { +// (void)vec_buffer; +// int i, j; +// /* Run the following code as reference implementation for RISC-V Core without DSP */ +// for (i = 0; i < num_of_rows; i++) +// { +// int ip_out = ((q31_t)(bias[i]) << bias_shift) + NN_ROUND(out_shift); +// for (j = 0; j < dim_vec; j++) +// { +// ip_out += pV[j] * pM[i * dim_vec + j]; +// } +// pOut[i] = (q15_t) __SSAT((ip_out >> out_shift), 16); +// } +// /* Return to application */ +// return (RISCV_MATH_SUCCESS); + +// } + +/** + * @} end of FC group + */ diff --git a/examples/nn/nnTest/Ref_Implementations/FullyConnectedFunctions/riscv_fully_connected_q7_opt_ref.c b/examples/nn/nnTest/Ref_Implementations/FullyConnectedFunctions/riscv_fully_connected_q7_opt_ref.c new file mode 100644 index 00000000..6afd846c --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/FullyConnectedFunctions/riscv_fully_connected_q7_opt_ref.c @@ -0,0 +1,251 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_fully_connected_q7_opt.c + * Description: Q7 basic fully-connected layer function + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "ref_functions.h" +#include "riscv_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup FC + * @{ + */ + + /** + * @brief Q7 opt fully-connected layer function + * @param[in] pV pointer to input vector + * @param[in] pM pointer to matrix weights + * @param[in] dim_vec length of the vector + * @param[in] num_of_rows number of rows in weight matrix + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias pointer to bias + * @param[in,out] pOut pointer to output vector + * @param[in,out] vec_buffer pointer to buffer space for input + * @return The function returns RISCV_MATH_SUCCESS + * + * @details + * + * Buffer size: + * + * vec_buffer size: dim_vec + * + * This opt function is designed to work with interleaved weight + * matrix. The vector input is assumed in q7_t format, we call + * riscv_q7_to_q15_no_shift_shuffle function to expand into + * q15_t format with certain weight re-ordering, refer to the function + * comments for more details. + * Here we use only one pointer to read 4 rows in the weight + * matrix. So if the original q7_t matrix looks like this: + * + * | a11 | a12 | a13 | a14 | a15 | a16 | a17 | + * + * | a21 | a22 | a23 | a24 | a25 | a26 | a27 | + * + * | a31 | a32 | a33 | a34 | a35 | a36 | a37 | + * + * | a41 | a42 | a43 | a44 | a45 | a46 | a47 | + * + * | a51 | a52 | a53 | a54 | a55 | a56 | a57 | + * + * | a61 | a62 | a63 | a64 | a65 | a66 | a67 | + * + * + * We operates on multiple-of-4 rows, so the first four rows becomes + * + * | a11 | a21 | a13 | a23 | a31 | a41 | a33 | a43 | + * + * | a12 | a22 | a14 | a24 | a32 | a42 | a34 | a44 | + * + * | a15 | a25 | a35 | a45 | a16 | a26 | a36 | a46 | + * + * So within the kernel, we first read the re-ordered vector in as: + * + * | b1 | b3 | and | b2 | b4 | + * + * the four q31_t weights will look like + * + * | a11 | a13 |, | a21 | a23 |, | a31 | a33 |, | a41 | a43 | + * + * | a12 | a14 |, | a22 | a24 |, | a32 | a34 |, | a42 | a44 | + * + * The column left over will be in-order. + * which is: + * + * | a17 | a27 | a37 | a47 | + * + * For the left-over rows, we do 1x1 computation, so the data remains + * as its original order. + * + * So the stored weight matrix looks like this: + * + * | a11 | a21 | a13 | a23 | a31 | a41 | + * + * | a33 | a43 | a12 | a22 | a14 | a24 | + * + * | a32 | a42 | a34 | a44 | a15 | a25 | + * + * | a35 | a45 | a16 | a26 | a36 | a46 | + * + * | a17 | a27 | a37 | a47 | a51 | a52 | + * + * | a53 | a54 | a55 | a56 | a57 | a61 | + * + * | a62 | a63 | a64 | a65 | a66 | a67 | + * + * + */ + +// REMOVED + +// riscv_status +// riscv_fully_connected_q7_opt_ref(const q7_t * pV, +// const q7_t * pM, +// const uint16_t dim_vec, +// const uint16_t num_of_rows, +// const uint16_t bias_shift, +// const uint16_t out_shift, +// const q7_t * bias, +// q7_t * pOut, +// q15_t * vec_buffer) +// { + +// /* Run the following code as reference implementation for RISC-V Core without DSP */ +// uint16_t rowCnt = num_of_rows >> 2; +// const q7_t *pB = pM; +// const q7_t *pA; +// q7_t *pO = pOut; +// const q7_t *pBias = bias; + +// while (rowCnt) +// { +// q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); +// q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); +// q31_t sum3 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); +// q31_t sum4 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + +// uint16_t colCnt = dim_vec >> 2; + +// pA = pV; + +// while (colCnt) +// { +// q7_t inA1 = *pA++; +// q7_t inA3 = *pA++; +// q7_t inA2 = *pA++; +// q7_t inA4 = *pA++; + +// q7_t inB1 = *pB++; +// q7_t inB3 = *pB++; +// q7_t inB2 = *pB++; +// q7_t inB4 = *pB++; + +// sum += inA1 * inB1 + inA2 * inB2; +// sum2 += inA1 * inB3 + inA2 * inB4; + +// inB1 = *pB++; +// inB3 = *pB++; +// inB2 = *pB++; +// inB4 = *pB++; + +// sum3 += inA1 * inB1 + inA2 * inB2; +// sum4 += inA1 * inB3 + inA2 * inB4; + +// inB1 = *pB++; +// inB3 = *pB++; +// inB2 = *pB++; +// inB4 = *pB++; + +// sum += inA3 * inB1 + inA4 * inB2; +// sum2 += inA3 * inB3 + inA4 * inB4; + +// inB1 = *pB++; +// inB3 = *pB++; +// inB2 = *pB++; +// inB4 = *pB++; + +// sum3 += inA3 * inB1 + inA4 * inB2; +// sum4 += inA3 * inB3 + inA4 * inB4; + +// colCnt--; +// } +// colCnt = dim_vec & 0x3; +// while (colCnt) +// { +// q7_t inA = *pA++; +// q7_t inB = *pB++; +// sum += inA * inB; +// inB = *pB++; +// sum2 += inA * inB; +// inB = *pB++; +// sum3 += inA * inB; +// inB = *pB++; +// sum4 += inA * inB; + +// colCnt--; +// } +// *pO++ = (q7_t) __SSAT((sum >> out_shift), 8); +// *pO++ = (q7_t) __SSAT((sum2 >> out_shift), 8); +// *pO++ = (q7_t) __SSAT((sum3 >> out_shift), 8); +// *pO++ = (q7_t) __SSAT((sum4 >> out_shift), 8); + +// rowCnt--; +// } + +// rowCnt = num_of_rows & 0x3; + +// while (rowCnt) +// { +// int ip_out = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + +// int j; + +// pA = pV; +// for (j = 0; j < dim_vec; j++) +// { +// q7_t inA = *pA++; +// q7_t inB = *pB++; +// ip_out += inA * inB; +// } +// *pO++ = (q7_t) __SSAT((ip_out >> out_shift), 8); + +// rowCnt--; +// } +// /* Return to RISCV_MATH_SUCCESS */ +// return (RISCV_MATH_SUCCESS); + +// } + +/** + * @} end of FC group + */ diff --git a/examples/nn/nnTest/Ref_Implementations/FullyConnectedFunctions/riscv_fully_connected_q7_ref.c b/examples/nn/nnTest/Ref_Implementations/FullyConnectedFunctions/riscv_fully_connected_q7_ref.c new file mode 100644 index 00000000..7adbb094 --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/FullyConnectedFunctions/riscv_fully_connected_q7_ref.c @@ -0,0 +1,101 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_fully_connected_q7.c + * Description: Q7 basic fully-connected layer function + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "ref_functions.h" +#include "riscv_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup FC + * @{ + */ + + /** + * @brief Q7 basic fully-connected layer function + * @param[in] pV pointer to input vector + * @param[in] pM pointer to matrix weights + * @param[in] dim_vec length of the vector + * @param[in] num_of_rows number of rows in weight matrix + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias pointer to bias + * @param[in,out] pOut pointer to output vector + * @param[in,out] vec_buffer pointer to buffer space for input + * @return The function returns RISCV_MATH_SUCCESS + * + * @details + * + * Buffer size: + * + * vec_buffer size: dim_vec + * + * This basic function is designed to work with regular weight + * matrix without interleaving. + * + */ + + +// +// REMOVED +// + +// riscv_status +// riscv_fully_connected_q7_ref(const q7_t * pV, +// const q7_t * pM, +// const uint16_t dim_vec, +// const uint16_t num_of_rows, +// const uint16_t bias_shift, +// const uint16_t out_shift, const q7_t * bias, q7_t * pOut, q15_t * vec_buffer) +// { + +// int i, j; + +// /* Run the following code as reference implementation for RISC-V Core without DSP */ +// for (i = 0; i < num_of_rows; i++) +// { +// int ip_out = ((q31_t)(bias[i]) << bias_shift) + NN_ROUND(out_shift); +// for (j = 0; j < dim_vec; j++) +// { +// ip_out += pV[j] * pM[i * dim_vec + j]; +// } +// pOut[i] = (q7_t) __SSAT((ip_out >> out_shift), 8); +// } +// /* Return to RISCV_MATH_SUCCESS */ +// return (RISCV_MATH_SUCCESS); + +// } + +/** + * @} end of FC group + */ diff --git a/examples/nn/nnTest/Ref_Implementations/FullyConnectedFunctions/riscv_fully_connected_s8_ref.c b/examples/nn/nnTest/Ref_Implementations/FullyConnectedFunctions/riscv_fully_connected_s8_ref.c new file mode 100644 index 00000000..221fc8b7 --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/FullyConnectedFunctions/riscv_fully_connected_s8_ref.c @@ -0,0 +1,98 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_fully_connected_s8 + * Description: Fully connected function compatible with TF Lite. + * + * $Date: May 2, 2020 + * $Revision: V.2.0.0 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "ref_functions.h" +#include "riscv_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup FC + * @{ + */ + +/* + * S8 basic fully-connected and matrix multiplication layer function for TensorFlow Lite + * + * Refer header file for details. + * + */ + +riscv_status +riscv_fully_connected_s8_ref(const nmsis_nn_context *ctx, + const nmsis_nn_fc_params *fc_params, + const nmsis_nn_per_tensor_quant_params *quant_params, + const nmsis_nn_dims *input_dims, + const q7_t *input, + const nmsis_nn_dims *filter_dims, + const q7_t *kernel, + const nmsis_nn_dims *bias_dims, + const int32_t *bias, + const nmsis_nn_dims *output_dims, + q7_t *output) +{ + (void)bias_dims; + (void)ctx; + int32_t batch_cnt = input_dims->n; + + while (batch_cnt) + { + riscv_nn_vec_mat_mult_t_s8_ref(input, + kernel, + bias, + output, + fc_params->input_offset, + fc_params->filter_offset, + fc_params->output_offset, + quant_params->multiplier, + quant_params->shift, + filter_dims->n, /* col_dim or accum_depth */ + output_dims->c, /* row_dim or output_depth */ + fc_params->activation.min, + fc_params->activation.max); + input += filter_dims->n; + output += output_dims->c; + batch_cnt--; + } + return (RISCV_MATH_SUCCESS); +} + +int32_t riscv_fully_connected_s8_get_buffer_size_ref(const nmsis_nn_dims *filter_dims) +{ + (void)filter_dims; + return 0; +} + +/** + * @} end of FC group + */ diff --git a/examples/nn/nnTest/Ref_Implementations/NNSupportFunctions/riscv_nn_accumulate_q7_to_q15_ref.c b/examples/nn/nnTest/Ref_Implementations/NNSupportFunctions/riscv_nn_accumulate_q7_to_q15_ref.c new file mode 100644 index 00000000..b4b9fc20 --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/NNSupportFunctions/riscv_nn_accumulate_q7_to_q15_ref.c @@ -0,0 +1,77 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_nn_accumulate_q7_to_q15.c + * Description: Accumulate q7 vector into q15 one. + * + * $Date: May 29, 2020 + * $Revision: V.1.0.1 + * + * pSrc Processor: RISC-V CPUs + * + * -------------------------------------------------------------------- */ +#include "riscv_math.h" +#include "ref_functions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup NNBasicMath + * @{ + */ + +void riscv_nn_accumulate_q7_to_q15_ref(q15_t *pDst, const q7_t *pSrc, uint32_t length) +{ + q15_t *pCnt = pDst; + const q7_t *pV = pSrc; + q31_t v1, v2, vo1, vo2; + int32_t cnt = length >> 2; + q31_t in; + + while (cnt > 0l) + { + q31_t value = riscv_nn_read_q7x4_ia(&pV); + v1 = __SXTB16(__ROR((uint32_t)value, 8)); + v2 = __SXTB16(value); + vo2 = (q31_t)__PKHTB(v1, v2, 16); + vo1 = (q31_t)__PKHBT(v2, v1, 16); + + in = riscv_nn_read_q15x2(pCnt); + write_q15x2_ia(&pCnt, __QADD16(vo1, in)); + + in = riscv_nn_read_q15x2(pCnt); + write_q15x2_ia(&pCnt, __QADD16(vo2, in)); + + cnt--; + } + cnt = length & 0x3; + while (cnt > 0l) + { + *pCnt++ += *pV++; + cnt--; + } +} + +/** + * @} end of NNBasicMath group + */ \ No newline at end of file diff --git a/examples/nn/nnTest/Ref_Implementations/NNSupportFunctions/riscv_nn_add_q7_ref.c b/examples/nn/nnTest/Ref_Implementations/NNSupportFunctions/riscv_nn_add_q7_ref.c new file mode 100644 index 00000000..caa5b674 --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/NNSupportFunctions/riscv_nn_add_q7_ref.c @@ -0,0 +1,63 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_nn_add_q7.c + * Description: Non saturating addition of elements of a q7 vector. + * + * $Date: July 2019 + * $Revision: V.1.0.0 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ +#include "ref_functions.h" +#include "riscv_nn_tables.h" +#include "riscv_nnsupportfunctions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup NNBasicMath + * @{ + */ + +void riscv_nn_add_q7_ref(const q7_t *input, q31_t *output, uint32_t block_size) +{ + uint32_t block_count; + q31_t result = 0; + block_count = block_size; + while (block_count > 0U) + { + /* Add and store result in destination buffer. */ + result += *input++; + + /* Decrement loop counter */ + block_count--; + } + + *output = result; +} + +/** + * @} end of NNBasicMath group + */ \ No newline at end of file diff --git a/examples/nn/nnTest/Ref_Implementations/NNSupportFunctions/riscv_nn_depthwise_conv_nt_t_padded_s8_ref.c b/examples/nn/nnTest/Ref_Implementations/NNSupportFunctions/riscv_nn_depthwise_conv_nt_t_padded_s8_ref.c new file mode 100644 index 00000000..e22284c8 --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/NNSupportFunctions/riscv_nn_depthwise_conv_nt_t_padded_s8_ref.c @@ -0,0 +1,81 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_nn_depthwise_conv_nt_t_padded_s8.c + * Description: Depthwise convolution with padded matrices. + * + * $Date: March 17, 2020 + * $Revision: V.1.0.1 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ + +#include "riscv_nnsupportfunctions.h" +#include "ref_functions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup NNBasicMath + * @{ + */ + +/* + * Depthwise convolution of transposed rhs matrix with 4 lhs matrices. One or more of the rhs matrices are padded. + * Dimensions are the same for lhs and rhs. + * + * Refer header file for details. + * + */ + +q7_t *riscv_nn_depthwise_conv_nt_t_padded_s8_ref(const q7_t *lhs, + const q7_t *rhs, + const int32_t input_offset, + const uint16_t num_ch, + const int32_t *out_shift, + const int32_t *out_mult, + const int32_t out_offset, + const int32_t activation_min, + const int32_t activation_max, + const uint16_t row_x_col, + const int32_t *const output_bias, + q7_t *out) +{ + (void)lhs; + (void)rhs; + (void)input_offset; + (void)num_ch; + (void)out_shift; + (void)out_mult; + (void)out_offset; + (void)activation_min; + (void)activation_max; + (void)row_x_col; + (void)output_bias; + (void)out; + return NULL; +} + +/** + * @} end of NNBasicMath group + */ diff --git a/examples/nn/nnTest/Ref_Implementations/NNSupportFunctions/riscv_nn_depthwise_conv_nt_t_s8_ref.c b/examples/nn/nnTest/Ref_Implementations/NNSupportFunctions/riscv_nn_depthwise_conv_nt_t_s8_ref.c new file mode 100644 index 00000000..f3990ee5 --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/NNSupportFunctions/riscv_nn_depthwise_conv_nt_t_s8_ref.c @@ -0,0 +1,80 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_nn_depthwise_conv_nt_t_s8.c + * Description: Depthwise convolution on matrices with no padding. + * + * $Date: March 17, 2020 + * $Revision: V.1.0.1 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ + +#include "riscv_nnsupportfunctions.h" +#include "ref_functions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup NNBasicMath + * @{ + */ + +/* + * Depthwise convolution of rhs matrix with 4 lhs matrices with no padding. Dimensions are the same for lhs and rhs. + * + * Refer header file for details. + * + */ + +q7_t *riscv_nn_depthwise_conv_nt_t_s8_ref(const q7_t *lhs, + const q7_t *rhs, + const int32_t input_offset, + const uint16_t num_ch, + const int32_t *out_shift, + const int32_t *out_mult, + const int32_t out_offset, + const int32_t activation_min, + const int32_t activation_max, + const uint16_t row_x_col, + const int32_t *const output_bias, + q7_t *out) +{ + (void)lhs; + (void)rhs; + (void)input_offset; + (void)num_ch; + (void)out_shift; + (void)out_mult; + (void)out_offset; + (void)activation_min; + (void)activation_max; + (void)row_x_col; + (void)output_bias; + (void)out; + return NULL; +} + +/** + * @} end of NNBasicMath group + */ diff --git a/examples/nn/nnTest/Ref_Implementations/NNSupportFunctions/riscv_nn_mat_mul_core_1x_s8_ref.c b/examples/nn/nnTest/Ref_Implementations/NNSupportFunctions/riscv_nn_mat_mul_core_1x_s8_ref.c new file mode 100644 index 00000000..18c27264 --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/NNSupportFunctions/riscv_nn_mat_mul_core_1x_s8_ref.c @@ -0,0 +1,72 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_nn_mat_mul_core_1x_s8.c + * Description: General Matrix-multiplication function + * + * $Date: January 20, 2020 + * $Revision: V.1.0.1 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ + +#include "riscv_nnsupportfunctions.h" +#include "ref_functions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup NNBasicMath + * @{ + */ + +/* + * s8 matrix multiplication to process 1 row + * + * Refer header file for details. + * + */ + +riscv_status riscv_nn_mat_mul_core_1x_s8_ref(int32_t row_elements, + const int8_t *row_base, + const int8_t *col_base, + int32_t *const sum_col, + int32_t *const output) +{ + int32_t acc_n0 = 0; + int32_t sum_tmp = 0; + + for (int i = 0; i < row_elements; i++) + { + sum_tmp += col_base[i]; + acc_n0 += row_base[i] * col_base[i]; + } + + *sum_col = sum_tmp; + *output = acc_n0; + return RISCV_MATH_SUCCESS; +} + +/** + * @} end of NNBasicMath group + */ diff --git a/examples/nn/nnTest/Ref_Implementations/NNSupportFunctions/riscv_nn_mat_mul_core_4x_s8_ref.c b/examples/nn/nnTest/Ref_Implementations/NNSupportFunctions/riscv_nn_mat_mul_core_4x_s8_ref.c new file mode 100644 index 00000000..517c1ca1 --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/NNSupportFunctions/riscv_nn_mat_mul_core_4x_s8_ref.c @@ -0,0 +1,88 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_nn_mat_mul_core_4x_s8.c + * Description: General matrix multiplication function for MVE extension + * + * $Date: January 20, 2020 + * $Revision: V.2.0.0 + * + * Target Processor: RISC-V Cores + * -------------------------------------------------------------------- */ + +#include "riscv_nnsupportfunctions.h" +#include "ref_functions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup NNBasicMath + * @{ + */ + +/* + * s8 matrix multiplication to process 4 rows and one column + * + * Refer header file for details. + * + */ +riscv_status riscv_nn_mat_mul_core_4x_s8_ref(const int32_t row_elements, + const int32_t offset, + const int8_t *row_base, + const int8_t *col_base, + int32_t *const sum_col, + int32_t *const output) +{ + int32_t acc_n0 = 0; + int32_t acc_n1 = 0; + int32_t acc_n2 = 0; + int32_t acc_n3 = 0; + + const int8_t *ip_row_0 = row_base; + const int8_t *ip_row_1 = row_base + offset; + const int8_t *ip_row_2 = row_base + (2 * offset); + const int8_t *ip_row_3 = row_base + (3 * offset); + int32_t sum_tmp = 0; + + for (int i = 0; i < row_elements; i++) + { + int32_t col = col_base[i]; + sum_tmp += col; + acc_n0 += ip_row_0[i] * col; + acc_n1 += ip_row_1[i] * col; + acc_n2 += ip_row_2[i] * col; + acc_n3 += ip_row_3[i] * col; + } + output[0] = acc_n0; + output[1] = acc_n1; + output[2] = acc_n2; + output[3] = acc_n3; + + *sum_col = sum_tmp; + + return RISCV_MATH_SUCCESS; +} + +/** + * @} end of NNBasicMath group + */ diff --git a/examples/nn/nnTest/Ref_Implementations/NNSupportFunctions/riscv_nn_mat_mult_nt_t_s8_ref.c b/examples/nn/nnTest/Ref_Implementations/NNSupportFunctions/riscv_nn_mat_mult_nt_t_s8_ref.c new file mode 100644 index 00000000..349f19b3 --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/NNSupportFunctions/riscv_nn_mat_mult_nt_t_s8_ref.c @@ -0,0 +1,235 @@ +/* + * Copyright (C) 2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_nn_mat_mult_s8_nt_t_s8 + * Description: Matrix multiplication support function with the right-hand-side (rhs) matrix transposed + * + * $Date: July 27 2020 + * $Revision: V.1.0.2 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "riscv_nnsupportfunctions.h" +#include "ref_functions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup NNBasicMath + * @{ + */ + +/* + * s8 matrix multiplication with the right-hand-side matrix transposed + * + * Refer header file for details. + * + */ +riscv_status riscv_nn_mat_mult_nt_t_s8_ref(const q7_t *lhs, + const q7_t *rhs, + const q31_t *bias, + q7_t *dst, + const int32_t *dst_multipliers, + const int32_t *dst_shifts, + const int32_t lhs_rows, + const int32_t rhs_rows, + const int32_t rhs_cols, + const int32_t lhs_offset, + const int32_t dst_offset, + const int32_t activation_min, + const int32_t activation_max) +{ + for (int32_t rhs_rows_idx = 0; rhs_rows_idx <= (rhs_rows - 2); rhs_rows_idx += 2) + { + const q7_t *lhs_ptr = &lhs[0]; + q7_t *dst_ptr = &dst[0]; + + q31_t lhs_offset_contribution0 = 0; + q31_t lhs_offset_contribution1 = 0; + + for (int32_t x = 0; x < rhs_cols; ++x) + { + lhs_offset_contribution0 += rhs[x]; + lhs_offset_contribution1 += rhs[x + rhs_cols]; + } + + lhs_offset_contribution0 *= lhs_offset; + lhs_offset_contribution1 *= lhs_offset; + if (bias) + { + lhs_offset_contribution0 += bias[rhs_rows_idx]; + lhs_offset_contribution1 += bias[rhs_rows_idx + 1]; + } + + int32_t lhs_rows_idx = lhs_rows >> 1; + + while (lhs_rows_idx) + { + const q7_t *rhs_ptr = &rhs[0]; + + q31_t res00 = lhs_offset_contribution0; + q31_t res01 = lhs_offset_contribution1; + q31_t res10 = lhs_offset_contribution0; + q31_t res11 = lhs_offset_contribution1; + + for (int32_t rhs_cols_idx = 0; rhs_cols_idx < rhs_cols; ++rhs_cols_idx) + { + q7_t rhs_value0 = rhs_ptr[0]; + q7_t rhs_value1 = rhs_ptr[rhs_cols]; + q7_t lhs_value = lhs_ptr[0]; + + res00 += lhs_value * rhs_value0; + res01 += lhs_value * rhs_value1; + + lhs_value = lhs_ptr[rhs_cols]; + res10 += lhs_value * rhs_value0; + res11 += lhs_value * rhs_value1; + + ++rhs_ptr; + ++lhs_ptr; + } + + // Quantize down + res00 = riscv_nn_requantize(res00, dst_multipliers[rhs_rows_idx], dst_shifts[rhs_rows_idx]); + res01 = riscv_nn_requantize(res01, dst_multipliers[rhs_rows_idx + 1], dst_shifts[rhs_rows_idx + 1]); + res10 = riscv_nn_requantize(res10, dst_multipliers[rhs_rows_idx], dst_shifts[rhs_rows_idx]); + res11 = riscv_nn_requantize(res11, dst_multipliers[rhs_rows_idx + 1], dst_shifts[rhs_rows_idx + 1]); + + // Add offset + res00 += dst_offset; + res01 += dst_offset; + res10 += dst_offset; + res11 += dst_offset; + + // Clamp the result + res00 = MAX(res00, activation_min); + res00 = MIN(res00, activation_max); + res01 = MAX(res01, activation_min); + res01 = MIN(res01, activation_max); + res10 = MAX(res10, activation_min); + res10 = MIN(res10, activation_max); + res11 = MAX(res11, activation_min); + res11 = MIN(res11, activation_max); + + dst_ptr[0] = (q7_t)res00; + dst_ptr[1] = (q7_t)res01; + dst_ptr += rhs_rows; + dst_ptr[0] = (q7_t)res10; + dst_ptr[1] = (q7_t)res11; + dst_ptr += rhs_rows; + + lhs_ptr += rhs_cols; + + lhs_rows_idx--; + } + + // Left-over rows + if (lhs_rows % 2) + { + const q7_t *rhs_ptr = &rhs[0]; + + q31_t res00 = lhs_offset_contribution0; + q31_t res01 = lhs_offset_contribution1; + + for (int32_t rhs_cols_idx = 0; rhs_cols_idx < rhs_cols; ++rhs_cols_idx) + { + q7_t rhs_value0 = rhs_ptr[0]; + q7_t rhs_value1 = rhs_ptr[rhs_cols]; + q7_t lhs_value = lhs_ptr[0]; + + res00 += lhs_value * rhs_value0; + res01 += lhs_value * rhs_value1; + + ++rhs_ptr; + ++lhs_ptr; + } + + // Quantize down + res00 = riscv_nn_requantize(res00, dst_multipliers[rhs_rows_idx], dst_shifts[rhs_rows_idx]); + res01 = riscv_nn_requantize(res01, dst_multipliers[rhs_rows_idx + 1], dst_shifts[rhs_rows_idx + 1]); + + // Add offset + res00 += dst_offset; + res01 += dst_offset; + + // Clamp the result + res00 = MAX(res00, activation_min); + res00 = MIN(res00, activation_max); + res01 = MAX(res01, activation_min); + res01 = MIN(res01, activation_max); + + dst_ptr[0] = (q7_t)res00; + dst_ptr[1] = (q7_t)res01; + } + + rhs += 2 * rhs_cols; + dst += 2; + } + + if (rhs_rows % 2) + { + const q7_t *lhs_ptr = &lhs[0]; + q7_t *dst_ptr = &dst[0]; + + for (int32_t lhs_rows_idx = 0; lhs_rows_idx < lhs_rows; ++lhs_rows_idx) + { + const q7_t *rhs_ptr = &rhs[0]; + q31_t res00 = 0; + if (bias) + { + res00 = bias[rhs_rows - 1]; + } + + for (int32_t rhs_cols_idx = 0; rhs_cols_idx < rhs_cols; ++rhs_cols_idx) + { + q31_t rhs_value = rhs_ptr[0]; + q31_t lhs_value = lhs_ptr[0] + lhs_offset; + + res00 += lhs_value * rhs_value; + + ++rhs_ptr; + ++lhs_ptr; + } + + // Quantize down + res00 = riscv_nn_requantize(res00, dst_multipliers[rhs_rows - 1], dst_shifts[rhs_rows - 1]); + + // Add offset + res00 += dst_offset; + + // Clamp the result + res00 = MAX(res00, activation_min); + res00 = MIN(res00, activation_max); + + dst_ptr[0] = (q7_t)res00; + dst_ptr += rhs_rows; + } + } + return RISCV_MATH_SUCCESS; +} + +/** + * @} end of NNBasicMath group + */ diff --git a/examples/nn/nnTest/Ref_Implementations/NNSupportFunctions/riscv_nn_mult_q15_ref.c b/examples/nn/nnTest/Ref_Implementations/NNSupportFunctions/riscv_nn_mult_q15_ref.c new file mode 100644 index 00000000..badd1992 --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/NNSupportFunctions/riscv_nn_mult_q15_ref.c @@ -0,0 +1,85 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_nn_mult_q15.c + * Description: Q15 vector multiplication with variable output shifts + * + * $Date: 29. April 2020 + * $Revision: V.1.0.1 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ +#include "riscv_nnsupportfunctions.h" +#include "ref_functions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup NNBasicMath + * @{ + */ + + +/** + * @brief Q7 vector multiplication with variable output shifts + * @param[in] *pSrcA pointer to the first input vector + * @param[in] *pSrcB pointer to the second input vector + * @param[out] *pDst pointer to the output vector + * @param[in] out_shift amount of right-shift for output + * @param[in] blockSize number of samples in each vector + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated. + */ + +void riscv_nn_mult_q15_ref( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + const uint16_t out_shift, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + + /* Run the below code for RISC-V Core without DSP */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* C = A * B */ + /* Multiply the inputs and store the result in the destination buffer */ + *pDst++ = (q15_t) __SSAT(((q31_t) ((q31_t) (*pSrcA++) * (*pSrcB++) + NN_ROUND(out_shift)) >> out_shift), 16); + + /* Decrement the blockSize loop counter */ + blkCnt--; + } +} + +/** + * @} end of NNBasicMath group + */ diff --git a/examples/nn/nnTest/Ref_Implementations/NNSupportFunctions/riscv_nn_mult_q7_ref.c b/examples/nn/nnTest/Ref_Implementations/NNSupportFunctions/riscv_nn_mult_q7_ref.c new file mode 100644 index 00000000..4645432f --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/NNSupportFunctions/riscv_nn_mult_q7_ref.c @@ -0,0 +1,84 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_nn_mult_q7.c + * Description: Q7 vector multiplication with variable output shifts + * + * $Date: 29. April 2020 + * $Revision: V.1.0.1 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ +#include "riscv_nnsupportfunctions.h" +#include "ref_functions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup NNBasicMath + * @{ + */ + +/** + * @brief Q7 vector multiplication with variable output shifts + * @param[in] *pSrcA pointer to the first input vector + * @param[in] *pSrcB pointer to the second input vector + * @param[out] *pDst pointer to the output vector + * @param[in] out_shift amount of right-shift for output + * @param[in] blockSize number of samples in each vector + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q7 range [0x80 0x7F] will be saturated. + */ + +void riscv_nn_mult_q7_ref( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + const uint16_t out_shift, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + + /* Run the below code for RISC-V Core without DSP */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* C = A * B */ + /* Multiply the inputs and store the result in the destination buffer */ + *pDst++ = (q7_t) __SSAT(((q15_t) ((q15_t) (*pSrcA++) * (*pSrcB++) + NN_ROUND(out_shift)) >> out_shift), 8); + + /* Decrement the blockSize loop counter */ + blkCnt--; + } +} + +/** + * @} end of NNBasicMath group + */ diff --git a/examples/nn/nnTest/Ref_Implementations/NNSupportFunctions/riscv_nn_vec_mat_mult_t_s8_ref.c b/examples/nn/nnTest/Ref_Implementations/NNSupportFunctions/riscv_nn_vec_mat_mult_t_s8_ref.c new file mode 100644 index 00000000..6fd04476 --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/NNSupportFunctions/riscv_nn_vec_mat_mult_t_s8_ref.c @@ -0,0 +1,142 @@ +/* + * Copyright (C) 2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_nn_vec_mat_mult_t_s8 + * Description: s8 vector by matrix (transposed) multiplication + * + * $Date: April 2, 2020 + * $Revision: V.1.5.0 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "riscv_nnsupportfunctions.h" +#include "ref_functions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup NNBasicMath + * @{ + */ + +/* + * s8 vector(lhs) by matrix (transposed) multiplication + * + * Refer header file for details. + * + */ +riscv_status riscv_nn_vec_mat_mult_t_s8_ref(const q7_t *lhs, + const q7_t *rhs, + const q31_t *bias, + q7_t *dst, + const int32_t lhs_offset, + const int32_t rhs_offset, + const int32_t dst_offset, + const int32_t dst_multiplier, + const int32_t dst_shift, + const int32_t rhs_cols, + const int32_t rhs_rows, + const int32_t activation_min, + const int32_t activation_max) +{ + + for (int32_t rhs_rows_idx = 0; rhs_rows_idx <= (rhs_rows - 2); rhs_rows_idx += 2) + { + const q7_t *lhs_ptr = &lhs[0]; + const q7_t *rhs_ptr = &rhs[0]; + + q31_t res00 = *bias++; + q31_t res01 = *bias++; + + for (int32_t rhs_cols_idx = 0; rhs_cols_idx < rhs_cols; ++rhs_cols_idx) + { + q31_t rhs_value0 = rhs_ptr[0] + rhs_offset; + q31_t rhs_value1 = rhs_ptr[rhs_cols] + rhs_offset; + q31_t lhs_value = lhs_ptr[0] + lhs_offset; + + res00 += lhs_value * rhs_value0; + res01 += lhs_value * rhs_value1; + + ++rhs_ptr; + ++lhs_ptr; + } + + // Quantize down + res00 = riscv_nn_requantize(res00, dst_multiplier, dst_shift); + res01 = riscv_nn_requantize(res01, dst_multiplier, dst_shift); + + // Add offset + res00 += dst_offset; + res01 += dst_offset; + + // Clamp the result + res00 = MAX(res00, activation_min); + res00 = MIN(res00, activation_max); + res01 = MAX(res01, activation_min); + res01 = MIN(res01, activation_max); + + *dst++ = (q7_t)res00; + *dst++ = (q7_t)res01; + + rhs += 2 * rhs_cols; + } + + if (rhs_rows % 2) + { + const q7_t *lhs_ptr = &lhs[0]; + const q7_t *rhs_ptr = &rhs[0]; + + q31_t res00 = *bias++; + + for (int32_t rhs_cols_idx = 0; rhs_cols_idx < rhs_cols; ++rhs_cols_idx) + { + q31_t rhs_value0 = rhs_ptr[0] + rhs_offset; + q31_t lhs_value = lhs_ptr[0] + lhs_offset; + + res00 += lhs_value * rhs_value0; + + ++rhs_ptr; + ++lhs_ptr; + } + + // Quantize down + res00 = riscv_nn_requantize(res00, dst_multiplier, dst_shift); + + // Add offset + res00 += dst_offset; + + // Clamp the result + res00 = MAX(res00, activation_min); + res00 = MIN(res00, activation_max); + + *dst = (q7_t)res00; + } + + return RISCV_MATH_SUCCESS; +} + +/** + * @} end of NNBasicMath group + */ diff --git a/examples/nn/nnTest/Ref_Implementations/NNSupportFunctions/riscv_nn_vec_mat_mult_t_svdf_s8.c b/examples/nn/nnTest/Ref_Implementations/NNSupportFunctions/riscv_nn_vec_mat_mult_t_svdf_s8.c new file mode 100644 index 00000000..301cecef --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/NNSupportFunctions/riscv_nn_vec_mat_mult_t_svdf_s8.c @@ -0,0 +1,246 @@ +/* + * Copyright (C) 2021 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_nn_vec_mat_mult_t_svdf_s8 + * Description: s8 vector by matrix (transposed) multiplication with + * s16 output. Targetted at SVDF operator. + * + * $Date: 15. April 2021 + * $Revision: V.1.0.0 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "riscv_nnsupportfunctions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup NNBasicMath + * @{ + */ + +/* + * s8 vector(lhs) by matrix (transposed) multiplication + * + * Refer header file for details. + * + */ +riscv_status ref_nn_vec_mat_mult_t_svdf_s8(const q7_t *lhs, + const q7_t *rhs, + q15_t *dst, + const int32_t lhs_offset, + const int32_t rhs_offset, + const int32_t dst_offset, + const int32_t dst_multiplier, + const int32_t dst_shift, + const int32_t rhs_cols, + const int32_t rhs_rows, + const int32_t activation_min, + const int32_t activation_max) +{ + (void)rhs_offset; + if (rhs_cols < 0 || (Q31_MAX - rhs_cols) < 16 || dst_offset < 0) + { + return RISCV_MATH_ARGUMENT_ERROR; + } + + (void)rhs_offset; +#if defined(RISCV_MATH_DSP) + int32_t row_loop_cnt = rhs_rows / 2; + + const int16_t lhs_offset_s16 = lhs_offset; + const int16_t rhs_offset_s16 = rhs_offset; + + const uint32_t lhs_offset_s16x2 = __PKHBT(lhs_offset_s16, lhs_offset_s16, 16); + const uint32_t rhs_offset_s16x2 = __PKHBT(rhs_offset_s16, rhs_offset_s16, 16); + for (int32_t i = 0; i < row_loop_cnt; i++) + { + int32_t acc_0 = 0; + int32_t acc_1 = 0; + + const int32_t col_loop_cnt = rhs_cols / 4; + const int8_t *lhs_vec = lhs; + const int8_t *rhs_0 = rhs; + const int8_t *rhs_1 = rhs + rhs_cols; + rhs += 2 * rhs_cols; + for (int j = col_loop_cnt; j != 0; j--) + { + int32_t vec_0 = riscv_nn_read_q7x4_ia(&lhs_vec); + int32_t vec_1 = __SXTAB16_RORn(lhs_offset_s16x2, (uint32_t)vec_0, 8); + vec_0 = __SXTAB16(lhs_offset_s16x2, vec_0); + int32_t ker_0 = riscv_nn_read_q7x4_ia(&rhs_0); + int32_t ker_1 = __SXTAB16_RORn(rhs_offset_s16x2, (uint32_t)ker_0, 8); + ker_0 = __SXTAB16(rhs_offset_s16x2, ker_0); + acc_0 = __SMLAD(ker_1, vec_1, acc_0); + acc_0 = __SMLAD(ker_0, vec_0, acc_0); + ker_0 = riscv_nn_read_q7x4_ia(&rhs_1); + ker_1 = __SXTAB16_RORn(rhs_offset_s16x2, (uint32_t)ker_0, 8); + ker_0 = __SXTAB16(rhs_offset_s16x2, ker_0); + acc_1 = __SMLAD(ker_1, vec_1, acc_1); + acc_1 = __SMLAD(ker_0, vec_0, acc_1); + } + for (int k = col_loop_cnt * 4; k < rhs_cols; k++) + { + const int32_t lhs_temp = (*lhs_vec + lhs_offset); + lhs_vec++; + acc_0 += lhs_temp * (*rhs_0 + rhs_offset); + rhs_0++; + acc_1 += lhs_temp * (*rhs_1 + rhs_offset); + rhs_1++; + } + acc_0 = riscv_nn_requantize(acc_0, dst_multiplier, dst_shift); + acc_1 = riscv_nn_requantize(acc_1, dst_multiplier, dst_shift); + + // Clamp the result + acc_0 = MAX(acc_0, activation_min); + acc_0 = MIN(acc_0, activation_max); + acc_1 = MAX(acc_1, activation_min); + acc_1 = MIN(acc_1, activation_max); + *dst = (q15_t)acc_0; + *(dst + dst_offset) = (q15_t)acc_1; + dst += 2 * dst_offset; + } + if (rhs_rows & 0x1) + { + int32_t acc_0 = 0; + const int32_t col_loop_cnt = rhs_cols / 4; + const int8_t *lhs_vec = lhs; + const int8_t *rhs_0 = rhs; + for (int i = col_loop_cnt; i != 0; i--) + { + int32_t vec_0 = riscv_nn_read_q7x4_ia(&lhs_vec); + int32_t vec_1 = __SXTAB16(lhs_offset_s16x2, __ROR((uint32_t)vec_0, 8)); + vec_0 = __SXTAB16(lhs_offset_s16x2, vec_0); + int32_t ker_0 = riscv_nn_read_q7x4_ia(&rhs_0); + int32_t ker_1 = __SXTAB16(rhs_offset_s16x2, __ROR((uint32_t)ker_0, 8)); + ker_0 = __SXTAB16(rhs_offset_s16x2, ker_0); + acc_0 = __SMLAD(ker_1, vec_1, acc_0); + acc_0 = __SMLAD(ker_0, vec_0, acc_0); + } + for (int j = col_loop_cnt * 4; j < rhs_cols; j++) + { + const int32_t lhs_temp = (*lhs_vec + lhs_offset); + lhs_vec++; + acc_0 += lhs_temp * (*rhs_0 + rhs_offset); + rhs_0++; + } + acc_0 = riscv_nn_requantize(acc_0, dst_multiplier, dst_shift); + + // Clamp the result + acc_0 = MAX(acc_0, activation_min); + acc_0 = MIN(acc_0, activation_max); + *dst = (q15_t)acc_0; + dst += dst_offset; + } + +#else + + int32_t row_loop_cnt = rhs_rows / 3; + + for (int i_row_loop_cnt = 0; i_row_loop_cnt < row_loop_cnt; i_row_loop_cnt++) + { + const q7_t *lhs_ptr = lhs; + const q7_t *rhs_ptr_0 = &rhs[0]; + const q7_t *rhs_ptr_1 = &rhs[rhs_cols]; + const q7_t *rhs_ptr_2 = &rhs[rhs_cols * 2]; + + q31_t res00 = 0; + q31_t res01 = 0; + q31_t res02 = 0; + for (int32_t rhs_cols_idx = 0; rhs_cols_idx < rhs_cols; ++rhs_cols_idx) + { + const q31_t rhs_value0 = (int8_t)*rhs_ptr_0; + const q31_t rhs_value1 = (int8_t)*rhs_ptr_1; + const q31_t rhs_value2 = (int8_t)*rhs_ptr_2; + const q31_t lhs_value = (int8_t)*lhs_ptr + lhs_offset; + + res00 += lhs_value * rhs_value0; + res01 += lhs_value * rhs_value1; + res02 += lhs_value * rhs_value2; + + ++rhs_ptr_0; + ++rhs_ptr_1; + ++rhs_ptr_2; + ++lhs_ptr; + } + // Quantize down + res00 = riscv_nn_requantize(res00, dst_multiplier, dst_shift); + res01 = riscv_nn_requantize(res01, dst_multiplier, dst_shift); + res02 = riscv_nn_requantize(res02, dst_multiplier, dst_shift); + + // Clamp the result + res00 = MAX(res00, activation_min); + res00 = MIN(res00, activation_max); + res01 = MAX(res01, activation_min); + res01 = MIN(res01, activation_max); + res02 = MAX(res02, activation_min); + res02 = MIN(res02, activation_max); + + *dst = (q15_t)res00; + *(dst + dst_offset) = (q15_t)res01; + *(dst + 2 * dst_offset) = (q15_t)res02; + dst += 3 * dst_offset; + rhs += 3 * rhs_cols; + } + + const int loop_cnt = rhs_rows % 3; + + for (int i_loop_cnt = 0; i_loop_cnt < loop_cnt; i_loop_cnt++) + { + const q7_t *lhs_ptr = &lhs[0]; + const q7_t *rhs_ptr = &rhs[0]; + + q31_t res00 = 0; + + for (int32_t rhs_cols_idx = 0; rhs_cols_idx < rhs_cols; ++rhs_cols_idx) + { + q31_t rhs_value0 = (int8_t)rhs_ptr[0] + rhs_offset; + q31_t lhs_value = (int8_t)lhs_ptr[0] + lhs_offset; + + res00 += lhs_value * rhs_value0; + + ++rhs_ptr; + ++lhs_ptr; + } + + // Quantize down + res00 = riscv_nn_requantize(res00, dst_multiplier, dst_shift); + + // Clamp the result + res00 = MAX(res00, activation_min); + res00 = MIN(res00, activation_max); + + *dst = (q15_t)res00; + dst += dst_offset; + rhs += rhs_cols; + } +#endif + + return RISCV_MATH_SUCCESS; +} + +/** + * @} end of NNBasicMath group + */ diff --git a/examples/nn/nnTest/Ref_Implementations/NNSupportFunctions/riscv_nntables.c b/examples/nn/nnTest/Ref_Implementations/NNSupportFunctions/riscv_nntables.c new file mode 100644 index 00000000..975b3dc1 --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/NNSupportFunctions/riscv_nntables.c @@ -0,0 +1,298 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_nntables.c + * Description: Converts the elements of the Q7 vector to Q15 vector without left-shift + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "riscv_nnsupportfunctions.h" + +/** + * @brief tables for various activation functions + * + * This file include the declaration of common tables. + * Most of them are used for activation functions + * + * Assumption: + * Unified table: input is 3.x format, i.e, range of [-8, 8) + * sigmoid(8) = 0.9996646498695336 + * tanh(8) = 0.9999997749296758 + * The accuracy here should be good enough + * + * 2-stage HL table: + * + * The entire input range is divided into two parts: + * + * Low range table: 0x000x xxxx or 0x111x xxxx + * table entry will be the binary number excluding the first + * two digits, i.e., 0x0x xxxx or 0x1x xxxx + * + * + * + * High range table 0x0010 0000 -- 0x0111 1111 + * 0x1000 0000 -- 0x1101 1111 + * + * For positive numbers, table entry will be + * 0x0010 0000 -- 0x0111 1111 minus 0x0010 0000 + * i.e., 0x0000 0000 - 0x0101 11111 + * + * same thing for the negative numbers, table entry will be + * 0x1000 0000 -- 0x1101 1111 minux 0x0010 0000 + * i.e., 0x0110 0000 - 0x1011 1111 + */ + +const q7_t sigmoidTable_q7[256] = { + 0x40, 0x42, 0x44, 0x46, 0x48, 0x4a, 0x4c, 0x4e, + 0x50, 0x52, 0x53, 0x55, 0x57, 0x59, 0x5a, 0x5c, + 0x5e, 0x5f, 0x61, 0x62, 0x63, 0x65, 0x66, 0x67, + 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x70, + 0x71, 0x72, 0x72, 0x73, 0x74, 0x74, 0x75, 0x76, + 0x76, 0x77, 0x77, 0x78, 0x78, 0x79, 0x79, 0x7a, + 0x7a, 0x7a, 0x7b, 0x7b, 0x7b, 0x7c, 0x7c, 0x7c, + 0x7c, 0x7c, 0x7d, 0x7d, 0x7d, 0x7d, 0x7d, 0x7e, + 0x7e, 0x7e, 0x7e, 0x7e, 0x7e, 0x7e, 0x7e, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, + 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, + 0x01, 0x01, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, + 0x02, 0x02, 0x03, 0x03, 0x03, 0x03, 0x03, 0x04, + 0x04, 0x04, 0x04, 0x04, 0x05, 0x05, 0x05, 0x06, + 0x06, 0x06, 0x07, 0x07, 0x08, 0x08, 0x09, 0x09, + 0x0a, 0x0a, 0x0b, 0x0c, 0x0c, 0x0d, 0x0e, 0x0e, + 0x0f, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, + 0x17, 0x19, 0x1a, 0x1b, 0x1d, 0x1e, 0x1f, 0x21, + 0x22, 0x24, 0x26, 0x27, 0x29, 0x2b, 0x2d, 0x2e, + 0x30, 0x32, 0x34, 0x36, 0x38, 0x3a, 0x3c, 0x3e, +}; + +const q15_t sigmoidTable_q15[256] = { + 0x4000, 0x4200, 0x43ff, 0x45fc, 0x47f5, 0x49eb, 0x4bdc, 0x4dc8, + 0x4fad, 0x518a, 0x5360, 0x552c, 0x56ef, 0x58a8, 0x5a57, 0x5bfb, + 0x5d93, 0x5f20, 0x60a1, 0x6216, 0x637f, 0x64db, 0x662b, 0x676f, + 0x68a6, 0x69d2, 0x6af1, 0x6c05, 0x6d0d, 0x6e09, 0x6efb, 0x6fe2, + 0x70be, 0x7190, 0x7258, 0x7316, 0x73cc, 0x7478, 0x751b, 0x75b7, + 0x764a, 0x76d6, 0x775b, 0x77d8, 0x784f, 0x78c0, 0x792a, 0x798f, + 0x79ee, 0x7a48, 0x7a9d, 0x7aed, 0x7b39, 0x7b80, 0x7bc4, 0x7c03, + 0x7c3f, 0x7c78, 0x7cad, 0x7ce0, 0x7d0f, 0x7d3c, 0x7d66, 0x7d8d, + 0x7db3, 0x7dd6, 0x7df7, 0x7e16, 0x7e33, 0x7e4f, 0x7e69, 0x7e81, + 0x7e98, 0x7eae, 0x7ec2, 0x7ed5, 0x7ee7, 0x7ef8, 0x7f08, 0x7f17, + 0x7f25, 0x7f32, 0x7f3e, 0x7f4a, 0x7f55, 0x7f5f, 0x7f69, 0x7f72, + 0x7f7b, 0x7f83, 0x7f8a, 0x7f91, 0x7f98, 0x7f9e, 0x7fa4, 0x7faa, + 0x7faf, 0x7fb4, 0x7fb8, 0x7fbd, 0x7fc1, 0x7fc5, 0x7fc8, 0x7fcc, + 0x7fcf, 0x7fd2, 0x7fd5, 0x7fd7, 0x7fda, 0x7fdc, 0x7fde, 0x7fe0, + 0x7fe2, 0x7fe4, 0x7fe6, 0x7fe7, 0x7fe9, 0x7fea, 0x7feb, 0x7fed, + 0x7fee, 0x7fef, 0x7ff0, 0x7ff1, 0x7ff2, 0x7ff3, 0x7ff4, 0x7ff4, + 0x000b, 0x000c, 0x000c, 0x000d, 0x000e, 0x000f, 0x0010, 0x0011, + 0x0012, 0x0013, 0x0015, 0x0016, 0x0017, 0x0019, 0x001a, 0x001c, + 0x001e, 0x0020, 0x0022, 0x0024, 0x0026, 0x0029, 0x002b, 0x002e, + 0x0031, 0x0034, 0x0038, 0x003b, 0x003f, 0x0043, 0x0048, 0x004c, + 0x0051, 0x0056, 0x005c, 0x0062, 0x0068, 0x006f, 0x0076, 0x007d, + 0x0085, 0x008e, 0x0097, 0x00a1, 0x00ab, 0x00b6, 0x00c2, 0x00ce, + 0x00db, 0x00e9, 0x00f8, 0x0108, 0x0119, 0x012b, 0x013e, 0x0152, + 0x0168, 0x017f, 0x0197, 0x01b1, 0x01cd, 0x01ea, 0x0209, 0x022a, + 0x024d, 0x0273, 0x029a, 0x02c4, 0x02f1, 0x0320, 0x0353, 0x0388, + 0x03c1, 0x03fd, 0x043c, 0x0480, 0x04c7, 0x0513, 0x0563, 0x05b8, + 0x0612, 0x0671, 0x06d6, 0x0740, 0x07b1, 0x0828, 0x08a5, 0x092a, + 0x09b6, 0x0a49, 0x0ae5, 0x0b88, 0x0c34, 0x0cea, 0x0da8, 0x0e70, + 0x0f42, 0x101e, 0x1105, 0x11f7, 0x12f3, 0x13fb, 0x150f, 0x162e, + 0x175a, 0x1891, 0x19d5, 0x1b25, 0x1c81, 0x1dea, 0x1f5f, 0x20e0, + 0x226d, 0x2405, 0x25a9, 0x2758, 0x2911, 0x2ad4, 0x2ca0, 0x2e76, + 0x3053, 0x3238, 0x3424, 0x3615, 0x380b, 0x3a04, 0x3c01, 0x3e00, +}; + +const q15_t sigmoidLTable_q15[128] = { + 0x4000, 0x4100, 0x4200, 0x42ff, 0x43ff, 0x44fd, 0x45fc, 0x46f9, + 0x47f5, 0x48f1, 0x49eb, 0x4ae5, 0x4bdc, 0x4cd3, 0x4dc8, 0x4ebb, + 0x4fad, 0x509c, 0x518a, 0x5276, 0x5360, 0x5447, 0x552c, 0x560f, + 0x56ef, 0x57cd, 0x58a8, 0x5981, 0x5a57, 0x5b2a, 0x5bfb, 0x5cc9, + 0x5d93, 0x5e5b, 0x5f20, 0x5fe2, 0x60a1, 0x615d, 0x6216, 0x62cc, + 0x637f, 0x642e, 0x64db, 0x6584, 0x662b, 0x66ce, 0x676f, 0x680c, + 0x68a6, 0x693d, 0x69d2, 0x6a63, 0x6af1, 0x6b7c, 0x6c05, 0x6c8a, + 0x6d0d, 0x6d8d, 0x6e09, 0x6e84, 0x6efb, 0x6f70, 0x6fe2, 0x7051, + 0x0f42, 0x0faf, 0x101e, 0x1090, 0x1105, 0x117c, 0x11f7, 0x1273, + 0x12f3, 0x1376, 0x13fb, 0x1484, 0x150f, 0x159d, 0x162e, 0x16c3, + 0x175a, 0x17f4, 0x1891, 0x1932, 0x19d5, 0x1a7c, 0x1b25, 0x1bd2, + 0x1c81, 0x1d34, 0x1dea, 0x1ea3, 0x1f5f, 0x201e, 0x20e0, 0x21a5, + 0x226d, 0x2337, 0x2405, 0x24d6, 0x25a9, 0x267f, 0x2758, 0x2833, + 0x2911, 0x29f1, 0x2ad4, 0x2bb9, 0x2ca0, 0x2d8a, 0x2e76, 0x2f64, + 0x3053, 0x3145, 0x3238, 0x332d, 0x3424, 0x351b, 0x3615, 0x370f, + 0x380b, 0x3907, 0x3a04, 0x3b03, 0x3c01, 0x3d01, 0x3e00, 0x3f00, +}; + +const q15_t sigmoidHTable_q15[192] = { + 0x70be, 0x7190, 0x7258, 0x7316, 0x73cc, 0x7478, 0x751b, 0x75b7, + 0x764a, 0x76d6, 0x775b, 0x77d8, 0x784f, 0x78c0, 0x792a, 0x798f, + 0x79ee, 0x7a48, 0x7a9d, 0x7aed, 0x7b39, 0x7b80, 0x7bc4, 0x7c03, + 0x7c3f, 0x7c78, 0x7cad, 0x7ce0, 0x7d0f, 0x7d3c, 0x7d66, 0x7d8d, + 0x7db3, 0x7dd6, 0x7df7, 0x7e16, 0x7e33, 0x7e4f, 0x7e69, 0x7e81, + 0x7e98, 0x7eae, 0x7ec2, 0x7ed5, 0x7ee7, 0x7ef8, 0x7f08, 0x7f17, + 0x7f25, 0x7f32, 0x7f3e, 0x7f4a, 0x7f55, 0x7f5f, 0x7f69, 0x7f72, + 0x7f7b, 0x7f83, 0x7f8a, 0x7f91, 0x7f98, 0x7f9e, 0x7fa4, 0x7faa, + 0x7faf, 0x7fb4, 0x7fb8, 0x7fbd, 0x7fc1, 0x7fc5, 0x7fc8, 0x7fcc, + 0x7fcf, 0x7fd2, 0x7fd5, 0x7fd7, 0x7fda, 0x7fdc, 0x7fde, 0x7fe0, + 0x7fe2, 0x7fe4, 0x7fe6, 0x7fe7, 0x7fe9, 0x7fea, 0x7feb, 0x7fed, + 0x7fee, 0x7fef, 0x7ff0, 0x7ff1, 0x7ff2, 0x7ff3, 0x7ff4, 0x7ff4, + 0x000b, 0x000c, 0x000c, 0x000d, 0x000e, 0x000f, 0x0010, 0x0011, + 0x0012, 0x0013, 0x0015, 0x0016, 0x0017, 0x0019, 0x001a, 0x001c, + 0x001e, 0x0020, 0x0022, 0x0024, 0x0026, 0x0029, 0x002b, 0x002e, + 0x0031, 0x0034, 0x0038, 0x003b, 0x003f, 0x0043, 0x0048, 0x004c, + 0x0051, 0x0056, 0x005c, 0x0062, 0x0068, 0x006f, 0x0076, 0x007d, + 0x0085, 0x008e, 0x0097, 0x00a1, 0x00ab, 0x00b6, 0x00c2, 0x00ce, + 0x00db, 0x00e9, 0x00f8, 0x0108, 0x0119, 0x012b, 0x013e, 0x0152, + 0x0168, 0x017f, 0x0197, 0x01b1, 0x01cd, 0x01ea, 0x0209, 0x022a, + 0x024d, 0x0273, 0x029a, 0x02c4, 0x02f1, 0x0320, 0x0353, 0x0388, + 0x03c1, 0x03fd, 0x043c, 0x0480, 0x04c7, 0x0513, 0x0563, 0x05b8, + 0x0612, 0x0671, 0x06d6, 0x0740, 0x07b1, 0x0828, 0x08a5, 0x092a, + 0x09b6, 0x0a49, 0x0ae5, 0x0b88, 0x0c34, 0x0cea, 0x0da8, 0x0e70, +}; + +const q7_t tanhTable_q7[256] = { + 0x00, 0x08, 0x10, 0x18, 0x1f, 0x27, 0x2e, 0x35, + 0x3b, 0x41, 0x47, 0x4c, 0x51, 0x56, 0x5a, 0x5e, + 0x61, 0x65, 0x68, 0x6a, 0x6d, 0x6f, 0x71, 0x72, + 0x74, 0x75, 0x76, 0x78, 0x78, 0x79, 0x7a, 0x7b, + 0x7b, 0x7c, 0x7c, 0x7d, 0x7d, 0x7e, 0x7e, 0x7e, + 0x7e, 0x7e, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x81, + 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x82, + 0x82, 0x82, 0x82, 0x82, 0x83, 0x83, 0x84, 0x84, + 0x85, 0x85, 0x86, 0x87, 0x88, 0x88, 0x8a, 0x8b, + 0x8c, 0x8e, 0x8f, 0x91, 0x93, 0x96, 0x98, 0x9b, + 0x9f, 0xa2, 0xa6, 0xaa, 0xaf, 0xb4, 0xb9, 0xbf, + 0xc5, 0xcb, 0xd2, 0xd9, 0xe1, 0xe8, 0xf0, 0xf8, +}; + +const q15_t tanhTable_q15[256] = { + 0x0000, 0x07fd, 0x0feb, 0x17b9, 0x1f59, 0x26bf, 0x2ddf, 0x34ae, + 0x3b27, 0x4142, 0x46fd, 0x4c56, 0x514d, 0x55e2, 0x5a1a, 0x5df6, + 0x617c, 0x64b0, 0x6797, 0x6a37, 0x6c95, 0x6eb5, 0x709e, 0x7254, + 0x73dc, 0x753a, 0x7672, 0x7788, 0x787f, 0x795b, 0x7a1e, 0x7acb, + 0x7b65, 0x7bee, 0x7c66, 0x7cd1, 0x7d30, 0x7d84, 0x7dce, 0x7e0f, + 0x7e49, 0x7e7d, 0x7eaa, 0x7ed2, 0x7ef5, 0x7f14, 0x7f30, 0x7f48, + 0x7f5e, 0x7f71, 0x7f82, 0x7f91, 0x7f9e, 0x7fa9, 0x7fb3, 0x7fbc, + 0x7fc4, 0x7fcb, 0x7fd1, 0x7fd7, 0x7fdc, 0x7fe0, 0x7fe4, 0x7fe7, + 0x7fea, 0x7fed, 0x7fef, 0x7ff1, 0x7ff3, 0x7ff4, 0x7ff6, 0x7ff7, + 0x7ff8, 0x7ff9, 0x7ffa, 0x7ffa, 0x7ffb, 0x7ffc, 0x7ffc, 0x7ffd, + 0x7ffd, 0x7ffd, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7fff, 0x7fff, + 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, + 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, + 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, + 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, + 0x8000, 0x8000, 0x8001, 0x8001, 0x8001, 0x8001, 0x8001, 0x8001, + 0x8001, 0x8001, 0x8001, 0x8002, 0x8002, 0x8002, 0x8002, 0x8003, + 0x8003, 0x8003, 0x8004, 0x8004, 0x8005, 0x8006, 0x8006, 0x8007, + 0x8008, 0x8009, 0x800a, 0x800c, 0x800d, 0x800f, 0x8011, 0x8013, + 0x8016, 0x8019, 0x801c, 0x8020, 0x8024, 0x8029, 0x802f, 0x8035, + 0x803c, 0x8044, 0x804d, 0x8057, 0x8062, 0x806f, 0x807e, 0x808f, + 0x80a2, 0x80b8, 0x80d0, 0x80ec, 0x810b, 0x812e, 0x8156, 0x8183, + 0x81b7, 0x81f1, 0x8232, 0x827c, 0x82d0, 0x832f, 0x839a, 0x8412, + 0x849b, 0x8535, 0x85e2, 0x86a5, 0x8781, 0x8878, 0x898e, 0x8ac6, + 0x8c24, 0x8dac, 0x8f62, 0x914b, 0x936b, 0x95c9, 0x9869, 0x9b50, + 0x9e84, 0xa20a, 0xa5e6, 0xaa1e, 0xaeb3, 0xb3aa, 0xb903, 0xbebe, + 0xc4d9, 0xcb52, 0xd221, 0xd941, 0xe0a7, 0xe847, 0xf015, 0xf803, +}; + +const q15_t tanhLTable_q15[128] = { + 0x0000, 0x0400, 0x07fd, 0x0bf7, 0x0feb, 0x13d7, 0x17b9, 0x1b90, + 0x1f59, 0x2314, 0x26bf, 0x2a58, 0x2ddf, 0x3151, 0x34ae, 0x37f6, + 0x3b27, 0x3e40, 0x4142, 0x442c, 0x46fd, 0x49b6, 0x4c56, 0x4edd, + 0x514d, 0x53a3, 0x55e2, 0x580a, 0x5a1a, 0x5c13, 0x5df6, 0x5fc4, + 0x617c, 0x6320, 0x64b0, 0x662d, 0x6797, 0x68f0, 0x6a37, 0x6b6e, + 0x6c95, 0x6dac, 0x6eb5, 0x6fb0, 0x709e, 0x717f, 0x7254, 0x731e, + 0x73dc, 0x7490, 0x753a, 0x75da, 0x7672, 0x7701, 0x7788, 0x7807, + 0x787f, 0x78f0, 0x795b, 0x79bf, 0x7a1e, 0x7a77, 0x7acb, 0x7b1b, + 0x849b, 0x84e5, 0x8535, 0x8589, 0x85e2, 0x8641, 0x86a5, 0x8710, + 0x8781, 0x87f9, 0x8878, 0x88ff, 0x898e, 0x8a26, 0x8ac6, 0x8b70, + 0x8c24, 0x8ce2, 0x8dac, 0x8e81, 0x8f62, 0x9050, 0x914b, 0x9254, + 0x936b, 0x9492, 0x95c9, 0x9710, 0x9869, 0x99d3, 0x9b50, 0x9ce0, + 0x9e84, 0xa03c, 0xa20a, 0xa3ed, 0xa5e6, 0xa7f6, 0xaa1e, 0xac5d, + 0xaeb3, 0xb123, 0xb3aa, 0xb64a, 0xb903, 0xbbd4, 0xbebe, 0xc1c0, + 0xc4d9, 0xc80a, 0xcb52, 0xceaf, 0xd221, 0xd5a8, 0xd941, 0xdcec, + 0xe0a7, 0xe470, 0xe847, 0xec29, 0xf015, 0xf409, 0xf803, 0xfc00, +}; + +const q15_t tanhHTable_q15[192] = { + 0x7b65, 0x7bee, 0x7c66, 0x7cd1, 0x7d30, 0x7d84, 0x7dce, 0x7e0f, + 0x7e49, 0x7e7d, 0x7eaa, 0x7ed2, 0x7ef5, 0x7f14, 0x7f30, 0x7f48, + 0x7f5e, 0x7f71, 0x7f82, 0x7f91, 0x7f9e, 0x7fa9, 0x7fb3, 0x7fbc, + 0x7fc4, 0x7fcb, 0x7fd1, 0x7fd7, 0x7fdc, 0x7fe0, 0x7fe4, 0x7fe7, + 0x7fea, 0x7fed, 0x7fef, 0x7ff1, 0x7ff3, 0x7ff4, 0x7ff6, 0x7ff7, + 0x7ff8, 0x7ff9, 0x7ffa, 0x7ffa, 0x7ffb, 0x7ffc, 0x7ffc, 0x7ffd, + 0x7ffd, 0x7ffd, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7fff, 0x7fff, + 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, + 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, + 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, + 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, + 0x8000, 0x8000, 0x8001, 0x8001, 0x8001, 0x8001, 0x8001, 0x8001, + 0x8001, 0x8001, 0x8001, 0x8002, 0x8002, 0x8002, 0x8002, 0x8003, + 0x8003, 0x8003, 0x8004, 0x8004, 0x8005, 0x8006, 0x8006, 0x8007, + 0x8008, 0x8009, 0x800a, 0x800c, 0x800d, 0x800f, 0x8011, 0x8013, + 0x8016, 0x8019, 0x801c, 0x8020, 0x8024, 0x8029, 0x802f, 0x8035, + 0x803c, 0x8044, 0x804d, 0x8057, 0x8062, 0x806f, 0x807e, 0x808f, + 0x80a2, 0x80b8, 0x80d0, 0x80ec, 0x810b, 0x812e, 0x8156, 0x8183, + 0x81b7, 0x81f1, 0x8232, 0x827c, 0x82d0, 0x832f, 0x839a, 0x8412, +}; diff --git a/examples/nn/nnTest/Ref_Implementations/NNSupportFunctions/riscv_q7_to_q15_no_shift_ref.c b/examples/nn/nnTest/Ref_Implementations/NNSupportFunctions/riscv_q7_to_q15_no_shift_ref.c new file mode 100644 index 00000000..51d16422 --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/NNSupportFunctions/riscv_q7_to_q15_no_shift_ref.c @@ -0,0 +1,82 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_q7_to_q15_no_shift.c + * Description: Converts the elements of the Q7 vector to Q15 vector without left-shift + * + * $Date: May 29, 2020 + * $Revision: V.1.0.2 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "riscv_nnsupportfunctions.h" +#include "ref_functions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup nndata_convert + * @{ + */ + +/** + * @brief Converts the elements of the Q7 vector to Q15 vector without left-shift + * @param[in] *pSrc points to the Q7 input vector + * @param[out] *pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + * + * \par Description: + * + * The equation used for the conversion process is: + * + * 
+ * 	pDst[n] = (q15_t) pSrc[n];   0 <= n < blockSize.
+ *
+ * + */ + +void riscv_q7_to_q15_no_shift_ref(const q7_t * pSrc, q15_t * pDst, uint32_t blockSize) +{ + const q7_t *pIn = pSrc; + uint32_t blkCnt; + + /* Run the below code for RISC-V Core without DSP */ + + /* Loop over blockSize number of values */ + blkCnt = blockSize; + while (blkCnt > 0u) + { + /* convert from q7 to q15 and then store the results in the destination buffer */ + *pDst++ = (q15_t)*pIn++; + + /* Decrement the loop counter */ + blkCnt--; + } + +} + +/** + * @} end of nndata_convert group + */ diff --git a/examples/nn/nnTest/Ref_Implementations/NNSupportFunctions/riscv_q7_to_q15_reordered_no_shift_ref.c b/examples/nn/nnTest/Ref_Implementations/NNSupportFunctions/riscv_q7_to_q15_reordered_no_shift_ref.c new file mode 100644 index 00000000..e4a85ed7 --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/NNSupportFunctions/riscv_q7_to_q15_reordered_no_shift_ref.c @@ -0,0 +1,132 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_q7_to_q15_reordered_no_shift.c + * Description: Converts the elements of the Q7 vector to reordered Q15 vector without left-shift + * + * $Date: May 29, 2020 + * $Revision: V.1.0.1 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "riscv_nnsupportfunctions.h" +#include "ref_functions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup nndata_convert + * @{ + */ + +/** + * @brief Converts the elements of the Q7 vector to reordered Q15 vector without left-shift + * @param[in] *pSrc points to the Q7 input vector + * @param[out] *pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + * + * @details + * + * This function does the q7 to q15 expansion with re-ordering + * + * 
+ *                          |   A1   |   A2   |   A3   |   A4   |
+ *
+ *                           0      7 8     15 16    23 24    31
+ *
+ * + * is converted into: + * + * 
+ *  |       A1       |       A3       |   and  |       A2       |       A4       |
+ *
+ *   0             15 16            31          0             15 16            31
+ *
+ * + * + * This looks strange but is natural considering how sign-extension is done at + * assembly level. + * + * The expansion of other other oprand will follow the same rule so that the end + * results are the same. + * + * The tail (i.e., last (N % 4) elements) will still be in original order. + * + */ + +void riscv_q7_to_q15_reordered_no_shift_ref(const q7_t * pSrc, q15_t * pDst, uint32_t blockSize) +{ + const q7_t *pIn = pSrc; /* Src pointer */ + uint32_t blkCnt; /* loop counter */ + + q31_t in; + q31_t in1, in2; + + /* Run the below code for RISC-V Core with DSP enabled */ + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0u) + { + /* C = (q15_t) A << 8 */ + /* convert from q7 to q15 and then store the results in the destination buffer */ + in = riscv_nn_read_q7x4_ia(&pIn); + + /* rotatate in by 8 and extend two q7_t values to q15_t values */ + in1 = __SXTB16(__ROR((uint32_t)in, 8)); + + /* extend remainig two q7_t values to q15_t values */ + in2 = __SXTB16(in); + + *__SIMD32(pDst)++ = in2; + *__SIMD32(pDst)++ = in1; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + + + while (blkCnt > 0u) + { + /* C = (q15_t) A << 8 */ + /* convert from q7 to q15 and then store the results in the destination buffer */ + *pDst++ = (q15_t) * pIn++; + + /* Decrement the loop counter */ + blkCnt--; + } + +} + +/** + * @} end of q7_to_x group + */ diff --git a/examples/nn/nnTest/Ref_Implementations/NNSupportFunctions/riscv_q7_to_q15_reordered_with_offset_ref.c b/examples/nn/nnTest/Ref_Implementations/NNSupportFunctions/riscv_q7_to_q15_reordered_with_offset_ref.c new file mode 100644 index 00000000..66df0f26 --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/NNSupportFunctions/riscv_q7_to_q15_reordered_with_offset_ref.c @@ -0,0 +1,64 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_q7_to_q15_reordered_with_offset.c + * Description: Converts the elements of the Q7 vector to a reordered Q15 vector with an added offset. The re-ordering + * is a signature of sign extension intrinsic(DSP extension). + * + * $Date: May 29, 2020 + * $Revision: V.2.0.3 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "riscv_nnsupportfunctions.h" +#include "ref_functions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup nndata_convert + * @{ + */ + +/** + * @brief Converts the elements of the Q7 vector to a reordered Q15 vector with an added offset. + * + * @note Refer header file for details. + * + */ + +void riscv_q7_to_q15_reordered_with_offset_ref(const q7_t *src, q15_t *dst, uint32_t block_size, q15_t offset) +{ + + (void)src; + (void)dst; + (void)block_size; + (void)offset; + /* Not available */ +} + +/** + * @} end of nndata_convert group + */ diff --git a/examples/nn/nnTest/Ref_Implementations/NNSupportFunctions/riscv_q7_to_q15_with_offset_ref.c b/examples/nn/nnTest/Ref_Implementations/NNSupportFunctions/riscv_q7_to_q15_with_offset_ref.c new file mode 100644 index 00000000..73d33ce9 --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/NNSupportFunctions/riscv_q7_to_q15_with_offset_ref.c @@ -0,0 +1,66 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in_q7x4 compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in_q7x4 writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_q7_to_q15_with_offset.c + * Description: Converts the elements of the Q7 vector to Q15 vector with an added offset + * + * $Date: March 3, 2020 + * $Revision: V.2.0.2 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "riscv_nnsupportfunctions.h" +#include "ref_functions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup nndata_convert + * @{ + */ + +void riscv_q7_to_q15_with_offset_ref(const q7_t *src, + q15_t *dst, + uint32_t block_size, + q15_t offset) +{ + int block_cnt; + + /* Run the below code for RISC-V Core without DSP */ + /* Loop over block_size number of values */ + block_cnt = block_size; + + while (block_cnt > 0) + { + *dst++ = (q15_t)*src++ + offset; + + /* Decrement the loop counter */ + block_cnt--; + } +} + +/** + * @} end of nndata_convert group + */ diff --git a/examples/nn/nnTest/Ref_Implementations/NNSupportFunctions/riscv_q7_to_q7_no_shift_ref.c b/examples/nn/nnTest/Ref_Implementations/NNSupportFunctions/riscv_q7_to_q7_no_shift_ref.c new file mode 100644 index 00000000..030e45a4 --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/NNSupportFunctions/riscv_q7_to_q7_no_shift_ref.c @@ -0,0 +1,85 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_q7_to_q7_no_shift.c + * Description: Converts the elements of the Q7 vector to Q7 vector without left-shift + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "riscv_nnsupportfunctions.h" +#include "ref_functions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup nndata_convert + * @{ + */ + +/** + * @brief Converts the elements of the Q7 vector to Q7 vector without left-shift + * @param[in] *pSrc points to the Q7 input vector + * @param[out] *pDst points to the Q7 output vector + * @param[in] blockSize length of the input vector + * @return none. + * + * \par Description: + * + * The equation used for the conversion process is: + * + * 
+ * 	pDst[n] = (q15_t) pSrc[n];   0 <= n < blockSize.
+ *
+ * + */ + +void riscv_q7_to_q7_no_shift_ref(const q7_t * pSrc, q7_t * pDst, uint32_t blockSize) +{ + const q7_t *pIn = pSrc; + uint32_t blkCnt; + + /* Run the below code for RISC-V Core without DSP */ + + /* Loop over blockSize number of values */ + blkCnt = blockSize; + + while (blkCnt > 0u) + { + /* convert from q7 to q7 and then store the results in the destination buffer */ + + *pDst++ = *pIn++; + + /* Decrement the loop counter */ + blkCnt--; + } + +} + +/** + * @} end of nndata_convert group + */ diff --git a/examples/nn/nnTest/Ref_Implementations/NNSupportFunctions/riscv_q7_to_q7_reordered_no_shift_ref.c b/examples/nn/nnTest/Ref_Implementations/NNSupportFunctions/riscv_q7_to_q7_reordered_no_shift_ref.c new file mode 100644 index 00000000..053a2c3f --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/NNSupportFunctions/riscv_q7_to_q7_reordered_no_shift_ref.c @@ -0,0 +1,126 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_q7_to_q15_reordered_no_shift.c + * Description: Converts the elements of the Q7 vector to reordered Q15 vector without left-shift + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "riscv_nnsupportfunctions.h" +#include "ref_functions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup nndata_convert + * @{ + */ + +/** + * @brief Converts the elements of the Q7 vector to reordered Q7 vector without left-shift + * @param[in] *pSrc points to the Q7 input vector + * @param[out] *pDst points to the Q7 output vector + * @param[in] blockSize length of the input vector + * @return none. + * + * @details + * + * This function does the q7 to q7 expansion with re-ordering + * + * 
+ *                          |   A1   |   A2   |   A3   |   A4   |
+ *
+ *                           0      7 8     15 16    23 24    31
+ *
+ * + * is converted into: + * + * 
+ *  |       A1       |       A3       |   and  |       A2       |       A4       |
+ *
+ *   0             15 16            31          0             15 16            31
+ *
+ * + * + * This looks strange but is natural considering how sign-extension is done at + * assembly level. + * + * The expansion of other other oprand will follow the same rule so that the end + * results are the same. + * + * The tail (i.e., last (N % 4) elements) will still be in original order. + * + */ + +void riscv_q7_to_q7_reordered_no_shift_ref(const q7_t * pSrc, q7_t * pDst, uint32_t blockSize) +{ + const q7_t *pIn = pSrc; /* Src pointer */ + uint32_t blkCnt; /* loop counter */ + + + q31_t in; + //q31_t in1, in2; + q31_t out; + /* Run the below code for RISC-V Core with DSP enabled */ + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0u) + { + /* C = (q15_t) A << 8 */ + /* convert from q7 to q7 and then store the results in the destination buffer */ + in = *__SIMD32(pIn)++; + + *__SIMD32(pDst)++ = in; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + + while (blkCnt > 0u) + { + /* C = (q15_t) A << 8 */ + /* convert from q7 to q7 and then store the results in the destination buffer */ + *pDst++ = (q7_t) * pIn++; + + /* Decrement the loop counter */ + blkCnt--; + } + +} + +/** + * @} end of q7_to_x group + */ diff --git a/examples/nn/nnTest/Ref_Implementations/PoolingFunctions/riscv_avgpool_s8_ref.c b/examples/nn/nnTest/Ref_Implementations/PoolingFunctions/riscv_avgpool_s8_ref.c new file mode 100644 index 00000000..fdb1ef26 --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/PoolingFunctions/riscv_avgpool_s8_ref.c @@ -0,0 +1,123 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_avgpool_s8.c + * Description: Pooling function implementations + * + * $Date: May 29,2020 + * $Revision: V.2.0.1 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "ref_functions.h" +#include "riscv_nnsupportfunctions.h" + + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Pooling + * @{ + */ + +/* + * s8 average pooling function + * + * Refer to header file for details. + * + */ + +riscv_status riscv_avgpool_s8_ref(const nmsis_nn_context *ctx, + const nmsis_nn_pool_params *pool_params, + const nmsis_nn_dims *input_dims, + const q7_t *src, + const nmsis_nn_dims *filter_dims, + const nmsis_nn_dims *output_dims, + q7_t *dst) +{ + const int32_t dim_src_height = input_dims->h; + const int32_t dim_src_width = input_dims->w; + const int32_t dim_dst_height = output_dims->h; + const int32_t dim_dst_width = output_dims->w; + const int32_t stride_height = pool_params->stride.h; + const int32_t stride_width = pool_params->stride.w; + const int32_t dim_kernel_height = filter_dims->h; + const int32_t dim_kernel_width = filter_dims->w; + const int32_t padding_height = pool_params->padding.h; + const int32_t padding_width = pool_params->padding.w; + const int32_t act_min = pool_params->activation.min; + const int32_t act_max = pool_params->activation.max; + const int32_t ch_src = input_dims->c; + q15_t *bufferA = (q15_t *)ctx->buf; + + /* Reference C code adapted from NMSIS-NN riscv_avepool_q7_HWC. + */ + (void)bufferA; + int16_t i_ch_in, i_x, i_y; + int16_t k_x, k_y; + + for (i_y = 0; i_y < dim_dst_height; i_y++) + { + for (i_x = 0; i_x < dim_dst_width; i_x++) + { + for (i_ch_in = 0; i_ch_in < ch_src; i_ch_in++) + { + int sum = 0; + int count = 0; + for (k_y = i_y * stride_height - padding_height; k_y < i_y * stride_height - padding_height + dim_kernel_height; k_y++) + { + for (k_x = i_x * stride_width - padding_width; k_x < i_x * stride_width - padding_width + dim_kernel_width; k_x++) + { + if (k_y >= 0 && k_x >= 0 && k_y < dim_src_height && k_x < dim_src_width) + { + sum += src[i_ch_in + ch_src * (k_x + k_y * dim_src_width)]; + count++; + } + } + } + sum = sum > 0 ? (sum + count / 2) / count : (sum - count / 2) / count; + sum = MAX(sum, act_min); + sum = MIN(sum, act_max); + + dst[i_ch_in + ch_src * (i_x + i_y * dim_dst_width)] = sum; + } + } + } + + return RISCV_MATH_SUCCESS; +} + + +int32_t riscv_avgpool_s8_get_buffer_size_ref(const int dim_dst_width, + const int ch_src) +{ + (void)dim_dst_width; + + (void)ch_src; + return 0; +} +/** + * @} end of Pooling group + */ diff --git a/examples/nn/nnTest/Ref_Implementations/PoolingFunctions/riscv_max_pool_s8_ref.c b/examples/nn/nnTest/Ref_Implementations/PoolingFunctions/riscv_max_pool_s8_ref.c new file mode 100644 index 00000000..b8cae171 --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/PoolingFunctions/riscv_max_pool_s8_ref.c @@ -0,0 +1,204 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_max_pool_s8.c + * Description: Pooling function implementations + * + * $Date: June 11, 2020 + * $Revision: V.2.0.0 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "ref_functions.h" +#include "riscv_nnsupportfunctions.h" + +static void compare_and_replace_if_larger_q7_ref(q7_t *base, + const q7_t *target, + int32_t length) +{ + q7_t *dst = base; + const q7_t *src = target; + union riscv_nnword ref_max; + union riscv_nnword comp_max; + int32_t cnt = length >> 2; + + while (cnt > 0l) + { + ref_max.word = riscv_nn_read_q7x4(dst); + comp_max.word = riscv_nn_read_q7x4_ia(&src); + + if (comp_max.bytes[0] > ref_max.bytes[0]) + { + ref_max.bytes[0] = comp_max.bytes[0]; + } + if (comp_max.bytes[1] > ref_max.bytes[1]) + { + ref_max.bytes[1] = comp_max.bytes[1]; + } + if (comp_max.bytes[2] > ref_max.bytes[2]) + { + ref_max.bytes[2] = comp_max.bytes[2]; + } + if (comp_max.bytes[3] > ref_max.bytes[3]) + { + ref_max.bytes[3] = comp_max.bytes[3]; + } + + write_q7x4_ia(&dst, ref_max.word); + + cnt--; + } + + cnt = length & 0x3; + while (cnt > 0l) + { + if (*src > *dst) + { + *dst = *src; + } + dst++; + src++; + cnt--; + } + +} + +static void +clamp_output_ref(q7_t *source, int32_t length, const int32_t act_min, const int32_t act_max) +{ + union riscv_nnword in; + int32_t cnt = length >> 2; + + while (cnt > 0l) + { + in.word = riscv_nn_read_q7x4(source); + + in.bytes[0] = MAX(in.bytes[0], act_min); + in.bytes[0] = MIN(in.bytes[0], act_max); + in.bytes[1] = MAX(in.bytes[1], act_min); + in.bytes[1] = MIN(in.bytes[1], act_max); + in.bytes[2] = MAX(in.bytes[2], act_min); + in.bytes[2] = MIN(in.bytes[2], act_max); + in.bytes[3] = MAX(in.bytes[3], act_min); + in.bytes[3] = MIN(in.bytes[3], act_max); + + write_q7x4_ia(&source, in.word); + cnt--; + } + + cnt = length & 0x3; + while (cnt > 0l) + { + int32_t comp = *source; + comp = MAX(comp, act_min); + comp = MIN(comp, act_max); + *source++ = (int8_t)comp; + cnt--; + } +} + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Pooling + * @{ + */ + +/* + * Optimized s8 max pooling function + * + * Refer to header file for details. + * + */ + +riscv_status +riscv_max_pool_s8_ref(const nmsis_nn_context *ctx, + const nmsis_nn_pool_params *pool_params, + const nmsis_nn_dims *input_dims, + const q7_t *src, + const nmsis_nn_dims *filter_dims, + const nmsis_nn_dims *output_dims, + q7_t *dst) +{ + const int32_t input_y = input_dims->h; + const int32_t input_x = input_dims->w; + const int32_t output_y = output_dims->h; + const int32_t output_x = output_dims->w; + const int32_t stride_y = pool_params->stride.h; + const int32_t stride_x = pool_params->stride.w; + const int32_t kernel_y = filter_dims->h; + const int32_t kernel_x = filter_dims->w; + const int32_t pad_y = pool_params->padding.h; + const int32_t pad_x = pool_params->padding.w; + const int32_t act_min = pool_params->activation.min; + const int32_t act_max = pool_params->activation.max; + const int32_t channel_in = input_dims->c; + (void)ctx; + q7_t *dst_base = dst; + + for (int i_y = 0, base_idx_y = -pad_y; i_y < output_y; base_idx_y += stride_y, i_y++) + { + for (int i_x = 0, base_idx_x = -pad_x; i_x < output_x; base_idx_x += stride_x, i_x++) + { + /* Condition for kernel start dimension: (base_idx_ + kernel__start) >= 0 */ + const int32_t ker_y_start = MAX(0, -base_idx_y); + const int32_t ker_x_start = MAX(0, -base_idx_x); + + /* Condition for kernel end dimension: (base_idx_ + kernel__end) < dim_src_ */ + const int32_t kernel_y_end = MIN(kernel_y, input_y - base_idx_y); + const int32_t kernel_x_end = MIN(kernel_x, input_x - base_idx_x); + + int count = 0; + + for (int k_y = ker_y_start; k_y < kernel_y_end; k_y++) + { + for (int k_x = ker_x_start; k_x < kernel_x_end; k_x++) + { + const q7_t *start = src + channel_in * (k_x + base_idx_x + (k_y + base_idx_y) * input_x); + + if (count == 0) + { + memcpy(dst, start, channel_in); + count++; + } + else + { + compare_and_replace_if_larger_q7_ref(dst, start, channel_in); + } + } + } + /* 'count' is expected to be non-zero here. */ + dst += channel_in; + } + } + + clamp_output_ref(dst_base, output_x * output_y * channel_in, act_min, act_max); + + return RISCV_MATH_SUCCESS; +} + +/** + * @} end of Pooling group + */ diff --git a/examples/nn/nnTest/Ref_Implementations/PoolingFunctions/riscv_pool_q7_HWC_ref.c b/examples/nn/nnTest/Ref_Implementations/PoolingFunctions/riscv_pool_q7_HWC_ref.c new file mode 100644 index 00000000..199aae25 --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/PoolingFunctions/riscv_pool_q7_HWC_ref.c @@ -0,0 +1,177 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_pool_q7_HWC.c + * Description: Pooling function implementations + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "ref_functions.h" +#include "riscv_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Pooling + * @{ + */ + + /** + * @brief Q7 max pooling function + * @param[in, out] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimention + * @param[in] ch_im_in number of input tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA Not used + * @param[in,out] Im_out pointer to output tensor + * + * @details + * + * The pooling function is implemented as split x-pooling then + * y-pooling. + * + * This pooling function is input-destructive. Input data is undefined + * after calling this function. + * + */ + +// REMOVED + +// void +// riscv_maxpool_q7_HWC_ref(q7_t * Im_in, +// const uint16_t dim_im_in, +// const uint16_t ch_im_in, +// const uint16_t dim_kernel, +// const uint16_t padding, +// const uint16_t stride, const uint16_t dim_im_out, q7_t * bufferA, q7_t * Im_out) +// { +// (void)bufferA; +// /* Run the following code as reference implementation for RISC-V Core without DSP */ +// int16_t i_ch_in, i_x, i_y; +// int16_t k_x, k_y; + +// for (i_ch_in = 0; i_ch_in < ch_im_in; i_ch_in++) +// { +// for (i_y = 0; i_y < dim_im_out; i_y++) +// { +// for (i_x = 0; i_x < dim_im_out; i_x++) +// { +// int max = -129; +// for (k_y = i_y * stride - padding; k_y < i_y * stride - padding + dim_kernel; k_y++) +// { +// for (k_x = i_x * stride - padding; k_x < i_x * stride - padding + dim_kernel; k_x++) +// { +// if (k_y >= 0 && k_x >= 0 && k_y < dim_im_in && k_x < dim_im_in) +// { +// if (Im_in[i_ch_in + ch_im_in * (k_x + k_y * dim_im_in)] > max) +// { +// max = Im_in[i_ch_in + ch_im_in * (k_x + k_y * dim_im_in)]; +// } +// } +// } +// } +// Im_out[i_ch_in + ch_im_in * (i_x + i_y * dim_im_out)] = max; +// } +// } +// } +// } + + /** + * @brief Q7 average pooling function + * @param[in,out] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimention + * @param[in] ch_im_in number of input tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] Im_out pointer to output tensor + * + * @details + * + * Buffer size: + * + * bufferA size: 2*dim_im_out*ch_im_in + * + * The pooling function is implemented as split x-pooling then + * y-pooling. + * + * This pooling function is input-destructive. Input data is undefined + * after calling this function. + * + */ + + // REMOVED + +// void +// riscv_avepool_q7_HWC_ref(q7_t * Im_in, +// const uint16_t dim_im_in, +// const uint16_t ch_im_in, +// const uint16_t dim_kernel, +// const uint16_t padding, +// const uint16_t stride, const uint16_t dim_im_out, q7_t * bufferA, q7_t * Im_out) +// { + +// /* Run the following code as reference implementation for RISC-V Core without DSP */ + +// (void)bufferA; +// int16_t i_ch_in, i_x, i_y; +// int16_t k_x, k_y; + +// for (i_ch_in = 0; i_ch_in < ch_im_in; i_ch_in++) +// { +// for (i_y = 0; i_y < dim_im_out; i_y++) +// { +// for (i_x = 0; i_x < dim_im_out; i_x++) +// { +// int sum = 0; +// int count = 0; +// for (k_y = i_y * stride - padding; k_y < i_y * stride - padding + dim_kernel; k_y++) +// { +// for (k_x = i_x * stride - padding; k_x < i_x * stride - padding + dim_kernel; k_x++) +// { +// if (k_y >= 0 && k_x >= 0 && k_y < dim_im_in && k_x < dim_im_in) +// { +// sum += Im_in[i_ch_in + ch_im_in * (k_x + k_y * dim_im_in)]; +// count++; +// } +// } +// } +// Im_out[i_ch_in + ch_im_in * (i_x + i_y * dim_im_out)] = sum / count; +// } +// } +// } +// } + +/** + * @} end of Pooling group + */ diff --git a/examples/nn/nnTest/Ref_Implementations/ReshapeFunctions/riscv_reshape_s8_ref.c b/examples/nn/nnTest/Ref_Implementations/ReshapeFunctions/riscv_reshape_s8_ref.c new file mode 100644 index 00000000..36fc18bb --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/ReshapeFunctions/riscv_reshape_s8_ref.c @@ -0,0 +1,59 @@ +/* + * Copyright (C) 2010-2019 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_reshape_s8.c + * Description: Reshape a s8 vector + * + * $Date: September 2019 + * $Revision: V.1.0.0 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "ref_functions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Reshape + * @{ + */ + +/** + * Basic s8 reshape function. + * + * Refer header file for details. + * + */ + +void riscv_reshape_s8_ref(const int8_t *input, + int8_t *output, + const uint32_t total_size) +{ + memcpy(output, input, total_size); +} + +/** + * @} end of Reshape group + */ \ No newline at end of file diff --git a/examples/nn/nnTest/Ref_Implementations/SVDFunctions/riscv_svdf_s8.c b/examples/nn/nnTest/Ref_Implementations/SVDFunctions/riscv_svdf_s8.c new file mode 100644 index 00000000..a59efa28 --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/SVDFunctions/riscv_svdf_s8.c @@ -0,0 +1,235 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_svdf_s8.c + * Description: S8 basic SVDF layer function + * + * $Date: 15. April 2021 + * $Revision: V.1.5.0 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "ref_functions.h" +#include "riscv_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup SVDF + * @{ + */ + +/* + * S8 SVDF layer function for TensorFlow Lite + * + * Refer to header file for details. + * + */ + +riscv_status ref_svdf_s8(const nmsis_nn_context *input_ctx, + const nmsis_nn_context *output_ctx, + const nmsis_nn_svdf_params *svdf_params, + const nmsis_nn_per_tensor_quant_params *input_quant_params, + const nmsis_nn_per_tensor_quant_params *output_quant_params, + const nmsis_nn_dims *input_dims, + const q7_t *input_data, + const nmsis_nn_dims *state_dims, + q15_t *state_data, + const nmsis_nn_dims *weights_feature_dims, + const q7_t *weights_feature_data, + const nmsis_nn_dims *weights_time_dims, + const q15_t *weights_time_data, + const nmsis_nn_dims *bias_dims, + const q31_t *bias_data, + const nmsis_nn_dims *output_dims, + q7_t *output_data) +{ + (void)bias_dims; + (void)state_dims; + (void)output_dims; + + const q31_t multiplier_in = input_quant_params->multiplier; + const q31_t shift_in = input_quant_params->shift; + const q31_t multiplier_out = output_quant_params->multiplier; + const q31_t shift_2 = output_quant_params->shift; + const int32_t zp_in = svdf_params->input_offset; + const int32_t zp_out = svdf_params->output_offset; + const int32_t in_activation_min = svdf_params->input_activation.min; + const int32_t in_activation_max = svdf_params->input_activation.max; + const int32_t out_activation_min = svdf_params->output_activation.min; + const int32_t out_activation_max = svdf_params->output_activation.max; + const int16_t rank = svdf_params->rank; + + const int32_t input_batches = input_dims->n; + const int32_t input_height = input_dims->h; + const int32_t feature_batches = weights_feature_dims->n; + const int32_t time_batches = weights_time_dims->h; + const int32_t unit_count = feature_batches / rank; + + q31_t *buffer_a = (q31_t *)input_ctx->buf; + q31_t *buffer_b = (q31_t *)output_ctx->buf; + + memmove((q15_t *)state_data, + (q15_t *)state_data + 1, + (size_t)(input_batches * feature_batches * time_batches * (int32_t)sizeof(int16_t))); + + for (int i_batch = 0; i_batch < input_batches; i_batch++) + { + q15_t *res_ptr = state_data + (time_batches * i_batch * feature_batches) + (time_batches - 1); + const q7_t *weight = weights_feature_data; + const q7_t *input = input_data + i_batch * input_height; + + riscv_status res = riscv_nn_vec_mat_mult_t_svdf_s8(input, + weight, + res_ptr, + -zp_in, + 0, + time_batches, + multiplier_in, + shift_in, + input_height, + feature_batches, + in_activation_min, + in_activation_max); + + if (res != RISCV_MATH_SUCCESS) + { + return res; + } + } + + { + q31_t *ptr_a = buffer_a; + const q15_t *v2 = state_data; + for (int i_batch = 0; i_batch < input_batches; i_batch++) + { + const q15_t *v1 = weights_time_data; + + for (int i_feature_batch = 0; i_feature_batch < feature_batches; i_feature_batch++) + { + *ptr_a = 0; + int32_t sum = 0; +#if defined(RISCV_MATH_DSP) + int j = 0; + int32_t block_count = time_batches >> 1; + for (int i = 0; i < block_count; i++) + { + j += 2; + q31_t r1 = riscv_nn_read_q15x2_ia(&v1); + q31_t r2 = riscv_nn_read_q15x2_ia(&v2); + + sum = __SMLAD(r1, r2, sum); + } + + // Process the remaining data + for (; j < time_batches; j++) + { + sum += *v1 * *v2; + v1++; + v2++; + } +#else + for (int j = 0; j < time_batches; j++) + { + sum += *v1 * *v2; + v1++; + v2++; + } +#endif + + *ptr_a = sum; + ptr_a++; + } + } + } + + if (bias_data) + { + if (unit_count == feature_batches) + { + for (int i = 0; i < input_batches; i++) + { + q31_t *output_temp = buffer_b + i * feature_batches; + const q31_t *ptr_a = buffer_a + i * feature_batches; + + const int32_t *bi = bias_data; + for (int j = 0; j < feature_batches; j++) + { + output_temp[j] = ptr_a[j] + bi[j]; + } + } + } + else + { + for (int i_batch = 0; i_batch < input_batches; i_batch++) + { + q31_t *output_data_temp = buffer_b + i_batch * unit_count; + q31_t *ptr_a = buffer_a + i_batch * feature_batches; + + for (int i = 0; i < unit_count; i++) + { + int32_t sum = bias_data[i]; + for (int j = 0; j < rank; j++) + { + sum += *ptr_a; + ptr_a++; + } + output_data_temp[i] = sum; + } + } + } + } + else + { + for (int i_batch = 0; i_batch < input_batches; i_batch++) + { + q31_t *output_data_temp = buffer_b + i_batch * unit_count; + q31_t *ptr_a = buffer_a + i_batch * feature_batches; + + for (int i = 0; i < unit_count; i++) + { + int32_t sum = 0; + for (int j = 0; j < rank; j++) + { + sum += *ptr_a; + ptr_a++; + } + output_data_temp[i] = sum; + } + } + } + + for (int i = 0; i < input_batches * unit_count; i++) + { + output_data[i] = (q7_t)CLAMP( + riscv_nn_requantize(buffer_b[i], multiplier_out, shift_2) + zp_out, out_activation_max, out_activation_min); + } + + return (RISCV_MATH_SUCCESS); +} + +/** + * @} end of SVDF group + */ diff --git a/examples/nn/nnTest/Ref_Implementations/SoftmaxFunctions/riscv_softmax_q15_ref.c b/examples/nn/nnTest/Ref_Implementations/SoftmaxFunctions/riscv_softmax_q15_ref.c new file mode 100644 index 00000000..b98b7931 --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/SoftmaxFunctions/riscv_softmax_q15_ref.c @@ -0,0 +1,119 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_softmax_q15.c + * Description: Q15 softmax function + * + * $Date: 20. February 2018 + * $Revision: V.1.0.0 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "ref_functions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Softmax + * @{ + */ + + /** + * @brief Q15 softmax function + * @param[in] vec_in pointer to input vector + * @param[in] dim_vec input vector dimention + * @param[out] p_out pointer to output vector + * + * @details + * + * Here, instead of typical e based softmax, we use + * 2-based softmax, i.e.,: + * + * y_i = 2^(x_i) / sum(2^x_j) + * + * The relative output will be different here. + * But mathematically, the gradient will be the same + * with a log(2) scaling factor. + * + */ + +void riscv_softmax_q15_ref(const q15_t * vec_in, const uint16_t dim_vec, q15_t * p_out) +{ + q31_t sum; + int16_t i; + uint8_t shift; + q31_t base; + base = -1 * 0x100000; + for (i = 0; i < dim_vec; i++) + { + if (vec_in[i] > base) + { + base = vec_in[i]; + } + } + + /* we ignore really small values + * anyway, they will be 0 after shrinking + * to q15_t + */ + base = base - 16; + + sum = 0; + + for (i = 0; i < dim_vec; i++) + { + if (vec_in[i] > base) + { + shift = (uint8_t)__USAT(vec_in[i] - base, 5); + sum += 0x1 << shift; + } + } + + /* This is effectively (0x1 << 32) / sum */ + int64_t div_base = 0x100000000LL; + int output_base = (int32_t)(div_base / sum); + + /* Final confidence will be output_base >> ( 17 - (vec_in[i] - base) ) + * so 32768 (0x1<<15) -> 100% confidence when sum = 0x1 << 16, output_base = 0x1 << 16 + * and vec_in[i]-base = 16 + */ + for (i = 0; i < dim_vec; i++) + { + if (vec_in[i] > base) + { + /* Here minimum value of 17+base-vec[i] will be 1 */ + shift = (uint8_t)__USAT(17+base-vec_in[i], 5); + p_out[i] = (q15_t) __SSAT((output_base >> shift), 16); + } else + { + p_out[i] = 0; + } + } + +} + +/** + * @} end of Softmax group + */ diff --git a/examples/nn/nnTest/Ref_Implementations/SoftmaxFunctions/riscv_softmax_q7_ref.c b/examples/nn/nnTest/Ref_Implementations/SoftmaxFunctions/riscv_softmax_q7_ref.c new file mode 100644 index 00000000..b77076d1 --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/SoftmaxFunctions/riscv_softmax_q7_ref.c @@ -0,0 +1,108 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_softmax_q7.c + * Description: Q7 softmax function + * + * $Date: June 8, 2020 + * $Revision: V.1.0.1 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "ref_functions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Softmax + * @{ + */ + + /** + * @brief Q7 softmax function + * @param[in] vec_in pointer to input vector + * @param[in] dim_vec input vector dimention + * @param[out] p_out pointer to output vector + * + * @details + * + * Here, instead of typical natural logarithm e based softmax, we use + * 2-based softmax here, i.e.,: + * + * y_i = 2^(x_i) / sum(2^x_j) + * + * The relative output will be different here. + * But mathematically, the gradient will be the same + * with a log(2) scaling factor. + * + */ + +void riscv_softmax_q7_ref(const q7_t * vec_in, const uint16_t dim_vec, q7_t * p_out ) +{ + q31_t sum; + int16_t i; + uint8_t shift; + q15_t base; + base = -128; + + /* We first search for the maximum */ + for (i = 0; i < dim_vec; i++) + { + if (vec_in[i] > base) + { + base = vec_in[i]; + } + } + + /* + * So the base is set to max-8, meaning + * that we ignore really small values. + * anyway, they will be 0 after shrinking to q7_t. + */ + base = base - 8; + + sum = 0; + + for (i = 0; i < dim_vec; i++) + { + shift = (uint8_t)__USAT(vec_in[i] - base, 3); + sum += 0x1 << shift; + } + + /* This is effectively (0x1 << 20) / sum */ + int output_base = (1 << 20) / sum; + + for (i = 0; i < dim_vec; i++) + { + + /* Here minimum value of 13+base-vec_in[i] will be 5 */ + shift = (uint8_t)__USAT(13 + base - vec_in[i], 5); + p_out[i] = (q7_t)__SSAT((output_base >> shift), 8); + } +} + +/** + * @} end of Softmax group + */ diff --git a/examples/nn/nnTest/Ref_Implementations/SoftmaxFunctions/riscv_softmax_s8_ref.c b/examples/nn/nnTest/Ref_Implementations/SoftmaxFunctions/riscv_softmax_s8_ref.c new file mode 100644 index 00000000..28b17475 --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/SoftmaxFunctions/riscv_softmax_s8_ref.c @@ -0,0 +1,104 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_softmax_s8.c + * Description: S8 softmax function + * + * $Date: April 6, 2020 + * $Revision: V.2.0.0 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "ref_functions.h" +#include "riscv_nnsupportfunctions.h" + +#define ACCUM_BITS 12 + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Softmax + * @{ + */ + +void riscv_softmax_s8_ref(const int8_t *input, + const int32_t num_rows, + const int32_t row_size, + const int32_t mult, + const int32_t shift, + const int32_t diff_min, + int8_t *output) +{ + const int32_t mask = (1 << shift); + + int32_t col = 0; + int32_t row_idx; + + for (row_idx = 0; row_idx < num_rows; ++row_idx) + { + // Find the maximum value in order to ensure numerical stability + int8_t max = *input; + + for (col = 1; col < row_size; ++col) + { + max = MAX(max, input[col]); + } + + int32_t diff = 0; + int32_t sum = 0; + + for (col = 0; col < row_size; ++col) + { + diff = input[col] - max; + if (diff >= diff_min) + { + sum += DIV_POW2(EXP_ON_NEG(MUL_SAT(diff * mask, mult)), ACCUM_BITS); + } + } + + const int32_t headroom = __CLZ(sum); + const int32_t bits_over_unit = ACCUM_BITS - headroom + 23; + const int32_t shifted_scale = ONE_OVER1((sum << headroom) - (1 << 31)); + + for (col = 0; col < row_size; ++col) + { + diff = input[col] - max; + if (diff >= diff_min) + { + const int32_t res = DIV_POW2(MUL_SAT(shifted_scale, EXP_ON_NEG(MUL_SAT(diff * mask, mult))), bits_over_unit) - 128; + output[col] = (int8_t)CLAMP(res, (int32_t)127, (int32_t)-128); + } + else + { + output[col] = -128; + } + } + input += row_size; + output += row_size; + } +} +/** + * @} end of Softmax group + */ diff --git a/examples/nn/nnTest/Ref_Implementations/SoftmaxFunctions/riscv_softmax_u8_ref.c b/examples/nn/nnTest/Ref_Implementations/SoftmaxFunctions/riscv_softmax_u8_ref.c new file mode 100644 index 00000000..57ba658a --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/SoftmaxFunctions/riscv_softmax_u8_ref.c @@ -0,0 +1,103 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_softmax_u8.c + * Description: U8 softmax function + * + * $Date: May 29, 2020 + * $Revision: V.1.0.1 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "ref_functions.h" +#include "riscv_nnsupportfunctions.h" + +#define ACCUM_BITS 12 + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Softmax + * @{ + */ +void riscv_softmax_u8_ref(const uint8_t *input, + const int32_t num_rows, + const int32_t row_size, + const int32_t mult, + const int32_t shift, + const int32_t diff_min, + uint8_t *output) +{ + const int32_t mask = (1 << shift); + + int32_t col = 0; + int32_t row_idx; + + for(row_idx = 0; row_idx < num_rows; ++row_idx) + { + // Find the maximum value in order to ensure numerical stability + uint8_t max = *input; + + for (col = 1; col < row_size; ++col) + { + max = MAX(max, input[col]); + } + + int32_t diff = 0; + int32_t sum = 0; + + for (col = 0; col < row_size; ++col) + { + diff = input[col] - max; + if(diff >= diff_min) + { + sum += DIV_POW2(EXP_ON_NEG(MUL_SAT(diff * mask, mult)), ACCUM_BITS); + } + } + + const int32_t headroom = __CLZ((uint32_t)sum); + const int32_t bits_over_unit = ACCUM_BITS - headroom + 23; + const int32_t shifted_scale = ONE_OVER1((sum << headroom) - (1 << 31)); + + for (col = 0; col < row_size; ++col) + { + diff = input[col] - max; + if (diff >= diff_min) + { + const int32_t res = DIV_POW2(MUL_SAT(shifted_scale, EXP_ON_NEG(MUL_SAT(diff * mask, mult))), bits_over_unit); + output[col] = (uint8_t) CLAMP(res, (int32_t)255, (int32_t)0); + } + else + { + output[col] = 0; + } + } + input += row_size; + output += row_size; + } +} +/** + * @} end of Softmax group + */ \ No newline at end of file diff --git a/examples/nn/nnTest/Ref_Implementations/SoftmaxFunctions/riscv_softmax_with_batch_q7_ref.c b/examples/nn/nnTest/Ref_Implementations/SoftmaxFunctions/riscv_softmax_with_batch_q7_ref.c new file mode 100644 index 00000000..370d2142 --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/SoftmaxFunctions/riscv_softmax_with_batch_q7_ref.c @@ -0,0 +1,75 @@ +/* + * Copyright (C) 2010-2019 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: NMSIS NN Library + * Title: riscv_softmax_with_batch_q7.c + * Description: Q7 softmax function + * + * $Date: 05. August 2019 + * $Revision: V.1.0.0 + * + * Target Processor: RISC-V Cores + * + * -------------------------------------------------------------------- */ + +#include "ref_functions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Softmax + * @{ + */ + + /** + * @brief Q7 softmax function with batch parameter + * @param[in] vec_in pointer to input vector + * @param[in] nb_batches number of batches + * @param[in] dim_vec input vector dimention + * @param[out] p_out pointer to output vector + * + * @details + * + * Here, instead of typical natural logarithm e based softmax, we use + * 2-based softmax here, i.e.,: + * + * y_i = 2^(x_i) / sum(2^x_j) + * + * The relative output will be different here. + * But mathematically, the gradient will be the same + * with a log(2) scaling factor. + * + */ + +void riscv_softmax_with_batch_q7_ref(const q7_t * vec_in, const uint16_t nb_batches,const uint16_t dim_vec, q7_t * p_out ) +{ + for(int i=0; i= 0 && in_col >= 0 && in_row < dim_im_in && in_col < dim_im_in) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += Im_in[(in_row * dim_im_in + in_col) * ch_im_in + l] * + wt[i * ch_im_in * dim_kernel * dim_kernel + (m * dim_kernel + n) * ch_im_in + l]; + } + } + } + } + Im_out[i + (j * dim_im_out + k) * ch_im_out] = (q15_t) __SSAT((conv_out >> out_shift), 16); + } + } + } +} diff --git a/examples/nn/nnTest/Ref_Implementations/riscv_convolve_HWC_q15_ref_nonsquare.c b/examples/nn/nnTest/Ref_Implementations/riscv_convolve_HWC_q15_ref_nonsquare.c new file mode 100644 index 00000000..8f148f7c --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/riscv_convolve_HWC_q15_ref_nonsquare.c @@ -0,0 +1,85 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ref_functions.h" +#include "riscv_nnsupportfunctions.h" + +void +riscv_convolve_HWC_q15_nonsquare_ref(const q15_t * Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q15_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q15_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q15_t * Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t * bufferA, + q7_t * bufferB) + +{ + uint16_t i, j, k, l, m, n; + int conv_out; + signed char in_row, in_col; + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out_y; j++) + { + for (k = 0; k < dim_im_out_x; k++) + { +#ifndef RISCV_NN_TRUNCATE + conv_out = (bias[i] << bias_shift) + (0x1 << (out_shift - 1)); +#else + conv_out = bias[i] << bias_shift; +#endif + for (m = 0; m < dim_kernel_y; m++) + { + for (n = 0; n < dim_kernel_x; n++) + { + in_row = stride_y * j + m - padding_y; + in_col = stride_x * k + n - padding_x; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in_y && in_col < dim_im_in_x) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += + Im_in[(in_row * dim_im_in_x + in_col) * ch_im_in + + l] * wt[i * ch_im_in * dim_kernel_x * dim_kernel_y + (m * dim_kernel_x + + n) * ch_im_in + l]; + } + } + } + } + Im_out[i + (j * dim_im_out_x + k) * ch_im_out] = (q15_t) __SSAT((conv_out >> out_shift), 16); + } + } + } +} + + diff --git a/examples/nn/nnTest/Ref_Implementations/riscv_convolve_HWC_q7_ref.c b/examples/nn/nnTest/Ref_Implementations/riscv_convolve_HWC_q7_ref.c new file mode 100644 index 00000000..5ea24c0b --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/riscv_convolve_HWC_q7_ref.c @@ -0,0 +1,74 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ref_functions.h" +#include "riscv_nnsupportfunctions.h" + +void riscv_convolve_HWC_q7_ref(const q7_t * Im_in, // input image + const uint16_t dim_im_in, // input image dimention + const uint16_t ch_im_in, // number of input image channels + const q7_t * wt, // kernel weights + const uint16_t ch_im_out, // number of filters, i.e., output image channels + const uint16_t dim_kernel, // filter kernel size + const uint16_t padding, // padding sizes + const uint16_t stride, // stride + const q7_t * bias, // bias + const uint16_t bias_shift, const uint16_t out_shift, q7_t * Im_out, // output image + const uint16_t dim_im_out, // output image dimension + q15_t * bufferA, //buffer space for input + q7_t * bufferB //buffer space for output + ) +{ + int i, j, k, l, m, n; + int conv_out; + int in_row, in_col; + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out; j++) + { + for (k = 0; k < dim_im_out; k++) + { +#ifndef RISCV_NN_TRUNCATE + conv_out = ((q31_t) (bias[i]) << bias_shift) + (0x1 << (out_shift - 1)); +#else + conv_out = bias[i] << bias_shift; +#endif + for (m = 0; m < dim_kernel; m++) + { + for (n = 0; n < dim_kernel; n++) + { + // if-for implementation + in_row = stride * j + m - padding; + in_col = stride * k + n - padding; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in && in_col < dim_im_in) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += Im_in[(in_row * dim_im_in + in_col) * ch_im_in + l] * + wt[i * ch_im_in * dim_kernel * dim_kernel + (m * dim_kernel + n) * ch_im_in + l]; + } + } + } + } + Im_out[i + (j * dim_im_out + k) * ch_im_out] = (q7_t) __SSAT((conv_out >> out_shift), 8); + } + } + } +} diff --git a/examples/nn/nnTest/Ref_Implementations/riscv_convolve_HWC_q7_ref_nonsquare.c b/examples/nn/nnTest/Ref_Implementations/riscv_convolve_HWC_q7_ref_nonsquare.c new file mode 100644 index 00000000..218152ea --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/riscv_convolve_HWC_q7_ref_nonsquare.c @@ -0,0 +1,77 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ref_functions.h" +#include "riscv_nnsupportfunctions.h" + +void riscv_convolve_HWC_q7_ref_nonsquare(const q7_t * Im_in, // input image + const uint16_t dim_im_in_x, // input image dimention x + const uint16_t dim_im_in_y, // input image dimention y + const uint16_t ch_im_in, // number of input image channels + const q7_t * wt, // kernel weights + const uint16_t ch_im_out, // number of filters, i.e., output image channels + const uint16_t dim_kernel_x, // filter kernel size x + const uint16_t dim_kernel_y, // filter kernel size y + const uint16_t padding_x, // padding sizes x + const uint16_t padding_y, // padding sizes y + const uint16_t stride_x, // stride x + const uint16_t stride_y, // stride y + const q7_t * bias, // bias + const uint16_t bias_shift, const uint16_t out_shift, q7_t * Im_out, // output image + const uint16_t dim_im_out_x, // output image dimension x + const uint16_t dim_im_out_y, // output image dimension y + q15_t * bufferA, //buffer space for input + q7_t * bufferB //buffer space for output + ) +{ + int i, j, k, l, m, n; + int conv_out; + int in_row, in_col; + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out_y; j++) + { + for (k = 0; k < dim_im_out_x; k++) + { + conv_out = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + for (m = 0; m < dim_kernel_y; m++) + { + for (n = 0; n < dim_kernel_x; n++) + { + // if-for implementation + in_row = stride_y * j + m - padding_y; + in_col = stride_x * k + n - padding_x; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in_y && in_col < dim_im_in_x) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += + Im_in[(in_row * dim_im_in_x + in_col) * ch_im_in + l] * + wt[i * ch_im_in * dim_kernel_y * dim_kernel_x + + (m * dim_kernel_x + n) * ch_im_in + l]; + } + } + } + } + Im_out[i + (j * dim_im_out_x + k) * ch_im_out] = (q7_t) __SSAT((conv_out >> out_shift), 8); + } + } + } +} diff --git a/examples/nn/nnTest/Ref_Implementations/riscv_depthwise_separable_conv_HWC_q7_ref.c b/examples/nn/nnTest/Ref_Implementations/riscv_depthwise_separable_conv_HWC_q7_ref.c new file mode 100644 index 00000000..6358d364 --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/riscv_depthwise_separable_conv_HWC_q7_ref.c @@ -0,0 +1,72 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ref_functions.h" +#include "riscv_nnsupportfunctions.h" + +void riscv_depthwise_separable_conv_HWC_q7_ref(const q7_t * Im_in, // input image + const uint16_t dim_im_in, // input image dimention + const uint16_t ch_im_in, // number of input image channels + const q7_t * wt, // kernel weights + const uint16_t ch_im_out, // number of filters, i.e., output image channels + const uint16_t dim_kernel, // filter kernel size + const uint16_t padding, // padding sizes + const uint16_t stride, // stride + const q7_t * bias, // bias + const uint16_t bias_shift, // amount of left-shift for bias + const uint16_t out_shift, // amount of right-shift for output + q7_t * Im_out, // output image + const uint16_t dim_im_out, // output image dimension + q15_t * bufferA, //buffer space for input + q7_t * bufferB //buffer space for output + ) +{ + int i_out_y, i_out_x, i_ch_out; + int i_ker_y, i_ker_x; + for (i_out_y = 0; i_out_y < dim_im_out; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out; i_out_x++) + { + for (i_ch_out = 0; i_ch_out < ch_im_out; i_ch_out++) + { + // for each output +#ifndef RISCV_NN_TRUNCATE + int conv_out = (bias[i_ch_out] << bias_shift) + (0x1 << (out_shift - 1)); +#else + int conv_out = bias[i_ch_out] << bias_shift; +#endif + for (i_ker_y = 0; i_ker_y < dim_kernel; i_ker_y++) + { + for (i_ker_x = 0; i_ker_x < dim_kernel; i_ker_x++) + { + int in_row = stride * i_out_y + i_ker_y - padding; + int in_col = stride * i_out_x + i_ker_x - padding; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in && in_col < dim_im_in) + { + conv_out += Im_in[(in_row * dim_im_in + in_col) * ch_im_in + i_ch_out] * + wt[(i_ker_y * dim_kernel + i_ker_x) * ch_im_out + i_ch_out]; + } + } + } + Im_out[(i_out_y * dim_im_out + i_out_x) * ch_im_out + i_ch_out] = + (q7_t) __SSAT((conv_out >> out_shift), 8); + } + } + } +} diff --git a/examples/nn/nnTest/Ref_Implementations/riscv_depthwise_separable_conv_HWC_q7_ref_nonsquare.c b/examples/nn/nnTest/Ref_Implementations/riscv_depthwise_separable_conv_HWC_q7_ref_nonsquare.c new file mode 100644 index 00000000..637a8e48 --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/riscv_depthwise_separable_conv_HWC_q7_ref_nonsquare.c @@ -0,0 +1,77 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ref_functions.h" +#include "riscv_nnsupportfunctions.h" + +void riscv_depthwise_separable_conv_HWC_q7_ref_nonsquare(const q7_t * Im_in, // input image + const uint16_t dim_im_in_x, // input image dimention x + const uint16_t dim_im_in_y, // input image dimention y + const uint16_t ch_im_in, // number of input image channels + const q7_t * wt, // kernel weights + const uint16_t ch_im_out, // number of filters, i.e., output image channels + const uint16_t dim_kernel_x, // filter kernel size x + const uint16_t dim_kernel_y, // filter kernel size y + const uint16_t padding_x, // padding sizes x + const uint16_t padding_y, // padding sizes y + const uint16_t stride_x, // stride x + const uint16_t stride_y, // stride y + const q7_t * bias, // bias + const uint16_t bias_shift, // amount of left-shift for bias + const uint16_t out_shift, // amount of right-shift for output + q7_t * Im_out, // output image + const uint16_t dim_im_out_x, // output image dimension x + const uint16_t dim_im_out_y, // output image dimension y + q15_t * bufferA, //buffer space for input + q7_t * bufferB //buffer space for output + ) +{ + int i_out_y, i_out_x, i_ch_out; + int i_ker_y, i_ker_x; + for (i_out_y = 0; i_out_y < dim_im_out_y; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out_x; i_out_x++) + { + for (i_ch_out = 0; i_ch_out < ch_im_out; i_ch_out++) + { + // for each output +#ifndef RISCV_NN_TRUNCATE + int conv_out = (bias[i_ch_out] << bias_shift) + (0x1 << (out_shift - 1)); +#else + int conv_out = bias[i_ch_out] << bias_shift; +#endif + for (i_ker_y = 0; i_ker_y < dim_kernel_y; i_ker_y++) + { + for (i_ker_x = 0; i_ker_x < dim_kernel_x; i_ker_x++) + { + int in_row = stride_y * i_out_y + i_ker_y - padding_y; + int in_col = stride_x * i_out_x + i_ker_x - padding_x; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in_y && in_col < dim_im_in_x) + { + conv_out += Im_in[(in_row * dim_im_in_x + in_col) * ch_im_in + i_ch_out] * + wt[(i_ker_y * dim_kernel_x + i_ker_x) * ch_im_out + i_ch_out]; + } + } + } + Im_out[(i_out_y * dim_im_out_x + i_out_x) * ch_im_out + i_ch_out] = + (q7_t) __SSAT((conv_out >> out_shift), 8); + } + } + } +} diff --git a/examples/nn/nnTest/Ref_Implementations/riscv_fully_connected_mat_q7_vec_q15_opt_ref.c b/examples/nn/nnTest/Ref_Implementations/riscv_fully_connected_mat_q7_vec_q15_opt_ref.c new file mode 100644 index 00000000..c5e53686 --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/riscv_fully_connected_mat_q7_vec_q15_opt_ref.c @@ -0,0 +1,122 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ref_functions.h" +#include "riscv_nnsupportfunctions.h" + +void riscv_fully_connected_mat_q7_vec_q15_opt_ref(const q15_t * pV, // pointer to vector + const q7_t * pM, // pointer to matrix + const uint16_t dim_vec, // length of the vector + const uint16_t num_of_rows, // numCol of A + const uint16_t bias_shift, // amount of left-shift for bias + const uint16_t out_shift, // amount of right-shift for output + const q7_t * bias, q15_t * pOut, // output operand + q15_t * vec_buffer) +{ + + uint16_t rowCnt = num_of_rows >> 2; + const q7_t *pB = pM; + const q15_t *pA; + q15_t *pO = pOut; + const q7_t *pBias = bias; + + while (rowCnt) + { + pA = pV; +#ifndef RISCV_NN_TRUNCATE + q31_t sum = (*pBias++ << bias_shift) + (0x1 << (out_shift - 1)); + q31_t sum2 = (*pBias++ << bias_shift) + (0x1 << (out_shift - 1)); + q31_t sum3 = (*pBias++ << bias_shift) + (0x1 << (out_shift - 1)); + q31_t sum4 = (*pBias++ << bias_shift) + (0x1 << (out_shift - 1)); +#else + q31_t sum = *pBias++ << bias_shift; + q31_t sum2 = *pBias++ << bias_shift; + q31_t sum3 = *pBias++ << bias_shift; + q31_t sum4 = *pBias++ << bias_shift; +#endif + + uint16_t colCnt = dim_vec >> 1; + + while (colCnt) + { + q15_t inA1 = *pA++; + q15_t inA2 = *pA++; + + q7_t inB1 = *pB++; + q7_t inB3 = *pB++; + q7_t inB2 = *pB++; + q7_t inB4 = *pB++; + + sum += inA1 * inB1 + inA2 * inB2; + sum2 += inA1 * inB3 + inA2 * inB4; + + inB1 = *pB++; + inB3 = *pB++; + inB2 = *pB++; + inB4 = *pB++; + + sum3 += inA1 * inB1 + inA2 * inB2; + sum4 += inA1 * inB3 + inA2 * inB4; + + colCnt--; + } + colCnt = dim_vec & 0x1; + while (colCnt) + { + q15_t inA = *pA++; + q7_t inB = *pB++; + sum += inA * inB; + inB = *pB++; + sum2 += inA * inB; + inB = *pB++; + sum3 += inA * inB; + inB = *pB++; + sum4 += inA * inB; + + colCnt--; + } + *pO++ = (q15_t) __SSAT((sum >> out_shift), 16); + *pO++ = (q15_t) __SSAT((sum2 >> out_shift), 16); + *pO++ = (q15_t) __SSAT((sum3 >> out_shift), 16); + *pO++ = (q15_t) __SSAT((sum4 >> out_shift), 16); + + rowCnt--; + } + + rowCnt = num_of_rows & 0x3; + + while (rowCnt) + { + pA = pV; +#ifndef RISCV_NN_TRUNCATE + int ip_out = (*pBias++ << bias_shift) + (0x1 << (out_shift - 1)); +#else + int ip_out = *pBias++ << bias_shift; +#endif + for (int j = 0; j < dim_vec; j++) + { + q15_t inA = *pA++; + q7_t inB = *pB++; + ip_out += inA * inB; + } + *pO++ = (q15_t) __SSAT((ip_out >> out_shift), 16); + + rowCnt--; + } +} diff --git a/examples/nn/nnTest/Ref_Implementations/riscv_fully_connected_mat_q7_vec_q15_ref.c b/examples/nn/nnTest/Ref_Implementations/riscv_fully_connected_mat_q7_vec_q15_ref.c new file mode 100644 index 00000000..09b59921 --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/riscv_fully_connected_mat_q7_vec_q15_ref.c @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ref_functions.h" +#include "riscv_nnsupportfunctions.h" + +void riscv_fully_connected_mat_q7_vec_q15_ref(const q15_t * pV, // pointer to vector + const q7_t * pM, // pointer to matrix + const uint16_t dim_vec, // length of the vector + const uint16_t num_of_rows, // numCol of A + const uint16_t bias_shift, // amount of left-shift for bias + const uint16_t out_shift, // amount of right-shift for output + const q7_t * bias, q15_t * pOut, // output operand + q15_t * vec_buffer) +{ + for (int i = 0; i < num_of_rows; i++) + { +#ifndef RISCV_NN_TRUNCATE + int ip_out = (bias[i] << bias_shift) + (0x1 << (out_shift - 1)); +#else + int ip_out = bias[i] << bias_shift; +#endif + for (int j = 0; j < dim_vec; j++) + { + ip_out += pV[j] * pM[i * dim_vec + j]; + } + pOut[i] = (q15_t) __SSAT((ip_out >> out_shift), 16); + } +} diff --git a/examples/nn/nnTest/Ref_Implementations/riscv_fully_connected_q15_opt_ref.c b/examples/nn/nnTest/Ref_Implementations/riscv_fully_connected_q15_opt_ref.c new file mode 100644 index 00000000..b9135c18 --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/riscv_fully_connected_q15_opt_ref.c @@ -0,0 +1,121 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ref_functions.h" +#include "riscv_nnsupportfunctions.h" + +void riscv_fully_connected_q15_opt_ref(const q15_t * pV, // pointer to vector + const q15_t * pM, // pointer to matrix + const uint16_t dim_vec, // length of the vector + const uint16_t num_of_rows, // numCol of A + const uint16_t bias_shift, // amount of left-shift for bias + const uint16_t out_shift, // amount of right-shift for output + const q15_t * bias, q15_t * pOut, // output operand + q15_t * vec_buffer) +{ + + uint16_t rowCnt = num_of_rows >> 2; + const q15_t *pB = pM; + const q15_t *pA; + q15_t *pO = pOut; + const q15_t *pBias = bias; + + while (rowCnt) + { + pA = pV; +#ifndef RISCV_NN_TRUNCATE + q31_t sum = (*pBias++ << bias_shift) + (0x1 << (out_shift - 1)); + q31_t sum2 = (*pBias++ << bias_shift) + (0x1 << (out_shift - 1)); + q31_t sum3 = (*pBias++ << bias_shift) + (0x1 << (out_shift - 1)); + q31_t sum4 = (*pBias++ << bias_shift) + (0x1 << (out_shift - 1)); +#else + q31_t sum = *pBias++ << bias_shift; + q31_t sum2 = *pBias++ << bias_shift; + q31_t sum3 = *pBias++ << bias_shift; + q31_t sum4 = *pBias++ << bias_shift; +#endif + + uint16_t colCnt = dim_vec >> 1; + + while (colCnt) + { + q15_t inA1 = *pA++; + q15_t inA2 = *pA++; + + q15_t inB1 = *pB++; + q15_t inB2 = *pB++; + sum += inA1 * inB1 + inA2 * inB2; + + inB1 = *pB++; + inB2 = *pB++; + sum2 += inA1 * inB1 + inA2 * inB2; + + inB1 = *pB++; + inB2 = *pB++; + sum3 += inA1 * inB1 + inA2 * inB2; + + inB1 = *pB++; + inB2 = *pB++; + sum4 += inA1 * inB1 + inA2 * inB2; + + colCnt--; + } + colCnt = dim_vec & 0x1; + while (colCnt) + { + q15_t inA = *pA++; + q15_t inB = *pB++; + sum += inA * inB; + inB = *pB++; + sum2 += inA * inB; + inB = *pB++; + sum3 += inA * inB; + inB = *pB++; + sum4 += inA * inB; + colCnt--; + } + *pO++ = (q15_t) __SSAT((sum >> out_shift), 16); + *pO++ = (q15_t) __SSAT((sum2 >> out_shift), 16); + *pO++ = (q15_t) __SSAT((sum3 >> out_shift), 16); + *pO++ = (q15_t) __SSAT((sum4 >> out_shift), 16); + + rowCnt--; + } + + rowCnt = num_of_rows & 0x3; + + while (rowCnt) + { + pA = pV; +#ifndef RISCV_NN_TRUNCATE + int ip_out = (*pBias++ << bias_shift) + (0x1 << (out_shift - 1)); +#else + int ip_out = *pBias++ << bias_shift; +#endif + for (int j = 0; j < dim_vec; j++) + { + q15_t inA = *pA++; + q15_t inB = *pB++; + ip_out += inA * inB; + } + *pO++ = (q15_t) __SSAT((ip_out >> out_shift), 16); + + rowCnt--; + } +} diff --git a/examples/nn/nnTest/Ref_Implementations/riscv_fully_connected_q15_ref.c b/examples/nn/nnTest/Ref_Implementations/riscv_fully_connected_q15_ref.c new file mode 100644 index 00000000..702f2df1 --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/riscv_fully_connected_q15_ref.c @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ref_functions.h" +#include "riscv_nnsupportfunctions.h" + +void riscv_fully_connected_q15_ref(const q15_t * pV, // pointer to vector + const q15_t * pM, // pointer to matrix + const uint16_t dim_vec, // length of the vector + const uint16_t num_of_rows, // numCol of A + const uint16_t bias_shift, // amount of left-shift for bias + const uint16_t out_shift, // amount of right-shift for output + const q15_t * bias, q15_t * pOut, // output operand + q15_t * vec_buffer) +{ + for (int i = 0; i < num_of_rows; i++) + { +#ifndef RISCV_NN_TRUNCATE + int ip_out = (bias[i] << bias_shift) + (0x1 << (out_shift - 1)); +#else + int ip_out = bias[i] << bias_shift; +#endif + for (int j = 0; j < dim_vec; j++) + { + ip_out += pV[j] * pM[i * dim_vec + j]; + } + pOut[i] = (q15_t) __SSAT((ip_out >> out_shift), 16); + } +} diff --git a/examples/nn/nnTest/Ref_Implementations/riscv_fully_connected_q7_opt_ref.c b/examples/nn/nnTest/Ref_Implementations/riscv_fully_connected_q7_opt_ref.c new file mode 100644 index 00000000..8bc2edc4 --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/riscv_fully_connected_q7_opt_ref.c @@ -0,0 +1,140 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ref_functions.h" +#include "riscv_nnsupportfunctions.h" + +void riscv_fully_connected_q7_opt_ref(const q7_t * pV, // pointer to vector + const q7_t * pM, // pointer to matrix + const uint16_t dim_vec, // length of the vector + const uint16_t num_of_rows, // numCol of A + const uint16_t bias_shift, // amount of left-shift for bias + const uint16_t out_shift, // amount of right-shift for output + const q7_t * bias, q7_t * pOut, // output operand + q15_t * vec_buffer) +{ + + uint16_t rowCnt = num_of_rows >> 2; + const q7_t *pB = pM; + const q7_t *pA; + q7_t *pO = pOut; + const q7_t *pBias = bias; + + while (rowCnt) + { + pA = pV; +#ifndef RISCV_NN_TRUNCATE + q31_t sum = (*pBias++ << bias_shift) + (0x1 << (out_shift - 1)); + q31_t sum2 = (*pBias++ << bias_shift) + (0x1 << (out_shift - 1)); + q31_t sum3 = (*pBias++ << bias_shift) + (0x1 << (out_shift - 1)); + q31_t sum4 = (*pBias++ << bias_shift) + (0x1 << (out_shift - 1)); +#else + q31_t sum = *pBias++ << bias_shift; + q31_t sum2 = *pBias++ << bias_shift; + q31_t sum3 = *pBias++ << bias_shift; + q31_t sum4 = *pBias++ << bias_shift; +#endif + + uint16_t colCnt = dim_vec >> 2; + + while (colCnt) + { + q7_t inA1 = *pA++; + q7_t inA3 = *pA++; + q7_t inA2 = *pA++; + q7_t inA4 = *pA++; + + q7_t inB1 = *pB++; + q7_t inB3 = *pB++; + q7_t inB2 = *pB++; + q7_t inB4 = *pB++; + + sum += inA1 * inB1 + inA2 * inB2; + sum2 += inA1 * inB3 + inA2 * inB4; + + inB1 = *pB++; + inB3 = *pB++; + inB2 = *pB++; + inB4 = *pB++; + + sum3 += inA1 * inB1 + inA2 * inB2; + sum4 += inA1 * inB3 + inA2 * inB4; + + inB1 = *pB++; + inB3 = *pB++; + inB2 = *pB++; + inB4 = *pB++; + + sum += inA3 * inB1 + inA4 * inB2; + sum2 += inA3 * inB3 + inA4 * inB4; + + inB1 = *pB++; + inB3 = *pB++; + inB2 = *pB++; + inB4 = *pB++; + + sum3 += inA3 * inB1 + inA4 * inB2; + sum4 += inA3 * inB3 + inA4 * inB4; + + colCnt--; + } + colCnt = dim_vec & 0x3; + while (colCnt) + { + q7_t inA = *pA++; + q7_t inB = *pB++; + sum += inA * inB; + inB = *pB++; + sum2 += inA * inB; + inB = *pB++; + sum3 += inA * inB; + inB = *pB++; + sum4 += inA * inB; + + colCnt--; + } + *pO++ = (q7_t) __SSAT((sum >> out_shift), 8); + *pO++ = (q7_t) __SSAT((sum2 >> out_shift), 8); + *pO++ = (q7_t) __SSAT((sum3 >> out_shift), 8); + *pO++ = (q7_t) __SSAT((sum4 >> out_shift), 8); + + rowCnt--; + } + + rowCnt = num_of_rows & 0x3; + + while (rowCnt) + { + pA = pV; +#ifndef RISCV_NN_TRUNCATE + int ip_out = (*pBias++ << bias_shift) + (0x1 << (out_shift - 1)); +#else + int ip_out = *pBias++ << bias_shift; +#endif + for (int j = 0; j < dim_vec; j++) + { + q7_t inA = *pA++; + q7_t inB = *pB++; + ip_out += inA * inB; + } + *pO++ = (q7_t) __SSAT((ip_out >> out_shift), 8); + + rowCnt--; + } +} diff --git a/examples/nn/nnTest/Ref_Implementations/riscv_fully_connected_q7_ref.c b/examples/nn/nnTest/Ref_Implementations/riscv_fully_connected_q7_ref.c new file mode 100644 index 00000000..407fa44c --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/riscv_fully_connected_q7_ref.c @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ref_functions.h" +#include "riscv_nnsupportfunctions.h" + +void riscv_fully_connected_q7_ref(const q7_t * pV, // pointer to vector + const q7_t * pM, // pointer to matrix + const uint16_t dim_vec, // length of the vector + const uint16_t num_of_rows, // numCol of A + const uint16_t bias_shift, // amount of left-shift for bias + const uint16_t out_shift, // amount of right-shift for output + const q7_t * bias, q7_t * pOut, // output operand + q15_t * vec_buffer) +{ + for (int i = 0; i < num_of_rows; i++) + { +#ifndef RISCV_NN_TRUNCATE + int ip_out = (bias[i] << bias_shift) + (0x1 << (out_shift - 1)); +#else + int ip_out = bias[i] << bias_shift; +#endif + for (int j = 0; j < dim_vec; j++) + { + ip_out += pV[j] * pM[i * dim_vec + j]; + } + pOut[i] = (q7_t) __SSAT((ip_out >> out_shift), 8); + } +} diff --git a/examples/nn/nnTest/Ref_Implementations/riscv_pool_ref.c b/examples/nn/nnTest/Ref_Implementations/riscv_pool_ref.c new file mode 100644 index 00000000..c37923f3 --- /dev/null +++ b/examples/nn/nnTest/Ref_Implementations/riscv_pool_ref.c @@ -0,0 +1,98 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019 Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ref_functions.h" +#include "riscv_nnsupportfunctions.h" + +void riscv_avepool_q7_HWC_ref(const q7_t * Im_in, // input image + const uint16_t dim_im_in, // input image dimension + const uint16_t ch_im_in, // number of input image channels + const uint16_t dim_kernel, // window kernel size + const uint16_t padding, // padding sizes + const uint16_t stride, // stride + const uint16_t dim_im_out, // output image dimension + q7_t * bufferA, // a buffer for local storage + q7_t * Im_out) +{ + int16_t i_ch_in, i_x, i_y; + int16_t k_x, k_y; + + for (i_ch_in = 0; i_ch_in < ch_im_in; i_ch_in++) + { + for (i_y = 0; i_y < dim_im_out; i_y++) + { + for (i_x = 0; i_x < dim_im_out; i_x++) + { + int sum = 0; + int count = 0; + for (k_y = i_y * stride - padding; k_y < i_y * stride - padding + dim_kernel; k_y++) + { + for (k_x = i_x * stride - padding; k_x < i_x * stride - padding + dim_kernel; k_x++) + { + if (k_y >= 0 && k_x >= 0 && k_y < dim_im_in && k_x < dim_im_in) + { + sum += Im_in[i_ch_in + ch_im_in * (k_x + k_y * dim_im_in)]; + count++; + } + } + } + Im_out[i_ch_in + ch_im_in * (i_x + i_y * dim_im_out)] = sum / count; + } + } + } +} + +void riscv_maxpool_q7_HWC_ref(const q7_t * Im_in, // input image + const uint16_t dim_im_in, // input image dimension + const uint16_t ch_im_in, // number of input image channels + const uint16_t dim_kernel, // window kernel size + const uint16_t padding, // padding sizes + const uint16_t stride, // stride + const uint16_t dim_im_out, // output image dimension + q7_t * bufferA, // a buffer for local storage + q7_t * Im_out) +{ + int16_t i_ch_in, i_x, i_y; + int16_t k_x, k_y; + + for (i_ch_in = 0; i_ch_in < ch_im_in; i_ch_in++) + { + for (i_y = 0; i_y < dim_im_out; i_y++) + { + for (i_x = 0; i_x < dim_im_out; i_x++) + { + int max = -129; + for (k_y = i_y * stride - padding; k_y < i_y * stride - padding + dim_kernel; k_y++) + { + for (k_x = i_x * stride - padding; k_x < i_x * stride - padding + dim_kernel; k_x++) + { + if (k_y >= 0 && k_x >= 0 && k_y < dim_im_in && k_x < dim_im_in) + { + if (Im_in[i_ch_in + ch_im_in * (k_x + k_y * dim_im_in)] > max) + { + max = Im_in[i_ch_in + ch_im_in * (k_x + k_y * dim_im_in)]; + } + } + } + } + Im_out[i_ch_in + ch_im_in * (i_x + i_y * dim_im_out)] = max; + } + } + } +} diff --git a/examples/nn/nnTest/bench.h b/examples/nn/nnTest/bench.h new file mode 100644 index 00000000..8936b15a --- /dev/null +++ b/examples/nn/nnTest/bench.h @@ -0,0 +1,131 @@ +#ifndef _RISCV_BENCH_H_ +#define _RISCV_BENCH_H_ + +#include +#include +#include "hal_mtimer.h" +#include "hal_uart.h" + +extern void bflb_platform_printf(char *fmt, ...); +extern void bflb_platform_init(uint32_t baudrate); + +#define MSG(a, ...) bflb_platform_printf(a, ##__VA_ARGS__) +#define MSG_DBG(a, ...) bflb_platform_printf(a, ##__VA_ARGS__) +#define MSG_ERR(a, ...) bflb_platform_printf(a, ##__VA_ARGS__) + +#undef printf +#define printf(a, ...) bflb_platform_printf(a, ##__VA_ARGS__) + +#define read_csr(reg) ({ \ + unsigned int __temp; \ + __ASM volatile("csrr %0, " #reg: "=r"(__temp)); \ + __temp; \ +}) + +#if __riscv_xlen == 32 +static inline uint64_t read_cpu_cycle(void) +{ + uint32_t hi = 0, hi1 = 0, lo = 0; + uint64_t val = 0; + hi = read_csr(cycleh); + lo = read_csr(cycle); + hi1 = read_csr(cycleh); + if (hi != hi1) { + hi = read_csr(cycleh); + lo = read_csr(cycle); + } + val = (((uint64_t)hi) << 32) | lo; + return val; +} +static inline uint64_t read_cpu_instret(void) +{ + uint32_t hi = 0, hi1 = 0, lo = 0; + uint64_t val = 0; + hi = read_csr(instreth); + lo = read_csr(instret); + hi1 = read_csr(instreth); + if (hi != hi1) { + hi = read_csr(instreth); + lo = read_csr(instret); + } + val = (((uint64_t)hi) << 32) | lo; + return val; +} +static inline void setup_vector(void) +{ +#if (defined (__RISCV_FEATURE_VECTOR) && (__RISCV_FEATURE_VECTOR == 1)) + __RV_CSR_SET(CSR_MSTATUS, 0x200); +#endif +} +#else +static inline uint64_t read_cpu_cycle(void) +{ + uint64_t val = 0; + val = read_csr(cycle); + return val; +} +static inline uint64_t read_cpu_instret(void) +{ + uint64_t val = 0; + val = read_csr(instret); + return val; +} +static inline void setup_vector(void) +{ +#if (defined (__RISCV_FEATURE_VECTOR) && (__RISCV_FEATURE_VECTOR == 1)) + __RV_CSR_SET(CSR_MSTATUS, 0x200); +#endif +} +#endif + +#ifndef READ_CYCLE +#define READ_CYCLE mtimer_get_time_us +#endif + +#ifndef INIT_VECTOR +#define INIT_VECTOR setup_vector +#endif + +#define BENCH_TRST + +uint64_t enter_cycle; +uint64_t exit_cycle; +uint64_t start_cycle; +uint64_t end_cycle; +uint64_t cycle; +uint64_t extra_cost = 0; +uint32_t bench_ercd; + +#define BENCH_INIT \ + bflb_platform_init(0); \ + MSG("Benchmark Initialized\n"); \ + INIT_VECTOR(); \ + BENCH_TRST \ + start_cycle = READ_CYCLE(); \ + end_cycle = READ_CYCLE(); \ + extra_cost = end_cycle - start_cycle; \ + enter_cycle = READ_CYCLE(); + + +#define BENCH_START(func) bench_ercd = 0; \ + BENCH_TRST \ + start_cycle = READ_CYCLE(); + +#define BENCH_END(func) end_cycle = READ_CYCLE(); \ + cycle = end_cycle - start_cycle - extra_cost; \ + MSG("CSV, %s, %lu\n", #func, cycle); + + +#define BENCH_ERROR(func) bench_ercd = 1; +#define BENCH_STATUS(func) if (bench_ercd) { \ + MSG("ERROR, %s\n", #func); \ + } else { \ + MSG("SUCCESS, %s\n", #func); \ + } + +#define BENCH_FINISH exit_cycle = READ_CYCLE(); \ + cycle = exit_cycle - enter_cycle - extra_cost; \ + MSG("CSV, BENCH END, %llu\n", cycle); + + +#endif //_RISCV_BENCH_H_ diff --git a/examples/nn/nnTest/main.cc b/examples/nn/nnTest/main.cc new file mode 100644 index 00000000..c8a4b3a2 --- /dev/null +++ b/examples/nn/nnTest/main.cc @@ -0,0 +1,2270 @@ +#include "riscv_nnexamples_nn_test.h" +#include "bench.h" +#include + +// New ones and Old ones can not be enabled at same time + +//------------Old ones------------ +//#define TEST_SIGMOID +//#define TEST_TANH +// #define TEST_POOL +// #define TEST_RELU +// #define TEST_IP +// #define TEST_CONV +// #define TEST_NONSQUARE +// #define TEST_NNMULT + +//------------New ones------------ +#define TEST_Activation +//#define TEST_BasicMath +//#define TEST_Concatenation +//#define TEST_Convolution_part1 +//#define TEST_Convolution_part2 +//#define TEST_Convolution_part3 +//#define TEST_Pooling + +//#define TEST_Softmax +//#define TEST_NNDataConversion +//#define TEST_BasicMathforNN + +//TODO +//#define TEST_SVD //TODO memory limit +//#define TEST_Fully_connectedLayer // TODO memory limit + +// #define TEST_Reshape +int test_index = 0; +q7_t test_flags[100]; +bool test_pass; + +int main() +{ + // common pointers for testing data + q7_t *test1; + q15_t *test2; + q7_t *test3; + q15_t *test4; + + BENCH_INIT; + + for (test_index = 0; test_index < 100; test_index++) { + test_flags[test_index] = -1; + } + test_index = 0; + +#ifdef TEST_Activation +#define Activation_SIZE 128 + test1 = new q7_t[Activation_SIZE]; + test2 = new q15_t[Activation_SIZE]; + test3 = new q7_t[Activation_SIZE]; + test4 = new q15_t[Activation_SIZE]; + + for (int i = 0; i < Activation_SIZE; i++) { + test1[i] = (rand() % 256 - 128); + test3[i] = test1[i]; + test2[i] = (rand() % 65536 - 32768); + test4[i] = test2[i]; + } + + printf("Start opt activations_direct q7 implementation\n"); + + BENCH_START(riscv_nn_activations_direct_q7); + riscv_nn_activations_direct_q7(test1, Activation_SIZE, 3, RISCV_SIGMOID); + BENCH_END(riscv_nn_activations_direct_q7); + + printf("Start ref activations_direct q7 implementation\n"); + + BENCH_START(riscv_nn_activations_direct_q7_ref); + riscv_nn_activations_direct_q7_ref(test3, Activation_SIZE, 3, RISCV_SIGMOID); + BENCH_END(riscv_nn_activations_direct_q7_ref); + + verify_results_q7(test1, test3, Activation_SIZE); + + printf("Start opt activations_direct q15 implementation\n"); + + BENCH_START(riscv_nn_activations_direct_q15); + riscv_nn_activations_direct_q15(test2, Activation_SIZE, 3, RISCV_SIGMOID); + BENCH_END(riscv_nn_activations_direct_q15); + + printf("Start ref activations_direct q15 implementation\n"); + + BENCH_START(riscv_nn_activations_direct_q15_ref); + riscv_nn_activations_direct_q15_ref(test4, Activation_SIZE, 3, RISCV_SIGMOID); + BENCH_END(riscv_nn_activations_direct_q15_ref); + + verify_results_q15(test2, test4, Activation_SIZE); + + q7_t *relu_ref_data_q7 = test1; + q7_t *relu_opt_data_q7 = test3; + q15_t *relu_ref_data_q15 = test2; + q15_t *relu_opt_data_q15 = test4; + + printf("Start ref relu q7 implementation\n"); + + BENCH_START(riscv_relu_q7_ref); + riscv_relu_q7_ref(relu_ref_data_q7, Activation_SIZE); + BENCH_END(riscv_relu_q7_ref); + + printf("Start opt relu q7 implementation\n"); + + BENCH_START(riscv_relu_q7); + riscv_relu_q7(relu_opt_data_q7, Activation_SIZE); + BENCH_END(riscv_relu_q7); + + verify_results_q7(relu_ref_data_q7, relu_opt_data_q7, Activation_SIZE); + + printf("Start ref relu q15 implementation\n"); + + BENCH_START(riscv_relu_q15_ref); + riscv_relu_q15_ref(relu_ref_data_q15, Activation_SIZE); + BENCH_END(riscv_relu_q15_ref); + + printf("Start opt relu q15 implementation\n"); + + BENCH_START(riscv_relu_q15); + riscv_relu_q15(relu_opt_data_q15, Activation_SIZE); + BENCH_END(riscv_relu_q15); + + verify_results_q15(relu_ref_data_q15, relu_opt_data_q15, Activation_SIZE); + + printf("Start ref relu s8 implementation\n"); + + BENCH_START(riscv_relu_s8_ref); + riscv_relu6_s8_ref(relu_ref_data_q7, Activation_SIZE / 4); + BENCH_END(riscv_relu_s8_ref); + + printf("Start opt relu s8 implementation\n"); + + BENCH_START(riscv_relu_s8); + riscv_relu6_s8(relu_opt_data_q7, Activation_SIZE / 4); + BENCH_END(riscv_relu_s8); + + verify_results_q7(relu_ref_data_q7, relu_opt_data_q7, Activation_SIZE - (Activation_SIZE % 4)); + + // delete[]test1; + // delete[]test2; + // delete[]test3; + // delete[]test4; + +#endif + +#ifdef TEST_BasicMath +#define BasicMath_SIZE 200 + test1 = new q7_t[BasicMath_SIZE * 2]; + test3 = new q7_t[BasicMath_SIZE * 2]; + + for (int i = 0; i < BasicMath_SIZE * 2; i++) { + test1[i] = (rand() % 256 - 128); + } + + for (int i = 0; i < BasicMath_SIZE; i++) { + test3[i] = test3[i + BasicMath_SIZE] = 0; + } + + printf("Start ref elementwise_add s8 implementation\n"); + + BENCH_START(riscv_elementwise_add_s8_ref); + riscv_elementwise_add_s8_ref(test1, test1 + BasicMath_SIZE, 9, 1073741824, 0, -5, 1073741824, -1, 20, test3, 14, 1073741824, -18, -128, 128, 32); + BENCH_END(riscv_elementwise_add_s8_ref); + + printf("Start opt elementwise_add s8 implementation\n"); + + BENCH_START(riscv_elementwise_add_s8); + riscv_elementwise_add_s8(test1, test1 + BasicMath_SIZE, 9, 1073741824, 0, -5, 1073741824, -1, 20, test3 + BasicMath_SIZE, 14, 1073741824, -18, -128, 128, 32); + BENCH_END(riscv_elementwise_add_s8); + + verify_results_q7(test3, test3 + BasicMath_SIZE, 32); + + printf("Start ref elementwise_mul s8 implementation\n"); + + BENCH_START(riscv_elementwise_mul_s8_ref); + riscv_elementwise_mul_s8_ref(test1, test1 + BasicMath_SIZE, 0, 0, test3, 0, 1, 0, -100, 100, BasicMath_SIZE); + BENCH_END(riscv_elementwise_mul_s8_ref); + + printf("Start opt elementwise_mul s8 implementation\n"); + + BENCH_START(riscv_elementwise_mul_s8); + riscv_elementwise_mul_s8(test1, test1 + BasicMath_SIZE, 0, 0, test3 + BasicMath_SIZE, 0, 1, 0, -100, 100, BasicMath_SIZE); + BENCH_END(riscv_elementwise_mul_s8); + + verify_results_q7(test3, test3 + BasicMath_SIZE, BasicMath_SIZE); + + // delete[]test1; + // delete[]test3; + +#endif + +#ifdef TEST_Concatenation +#define Concatenation_SIZE 100 + test1 = new q7_t[Concatenation_SIZE]; + test3 = new q7_t[Concatenation_SIZE * 2]; + + for (int i = 0; i < Concatenation_SIZE; i++) { + test1[i] = (rand() % 256 - 128); + } + + printf("Start ref concatenation s8 w implementation\n"); + + BENCH_START(riscv_concatenation_s8_w_ref); + riscv_concatenation_s8_w_ref(test1, 10, 2, 2, 2, test3, 0); + BENCH_END(riscv_concatenation_s8_w_ref); + + printf("Start opt concatenation s8 w implementation\n"); + + BENCH_START(riscv_concatenation_s8_w); + riscv_concatenation_s8_w(test1, 10, 2, 2, 2, test3 + Concatenation_SIZE, 0); + BENCH_END(riscv_concatenation_s8_w); + + verify_results_q7(test3, test3 + Concatenation_SIZE, 80); + + printf("Start ref concatenation s8 x implementation\n"); + + BENCH_START(riscv_concatenation_s8_x_ref); + riscv_concatenation_s8_x_ref(test1, 10, 2, 2, 2, test3, 10, 0); + BENCH_END(riscv_concatenation_s8_x_ref); + + printf("Start opt concatenation s8 x implementation\n"); + + BENCH_START(riscv_concatenation_s8_x); + riscv_concatenation_s8_x(test1, 10, 2, 2, 2, test3 + Concatenation_SIZE, 10, 0); + BENCH_END(riscv_concatenation_s8_x); + + verify_results_q7(test3, test3 + Concatenation_SIZE, 80); + + printf("Start ref concatenation s8 y implementation\n"); + + BENCH_START(riscv_concatenation_s8_y_ref); + riscv_concatenation_s8_y_ref(test1, 10, 2, 2, 2, test3, 2, 0); + BENCH_END(riscv_concatenation_s8_y_ref); + + printf("Start opt concatenation s8 y implementation\n"); + + BENCH_START(riscv_concatenation_s8_y); + riscv_concatenation_s8_y(test1, 10, 2, 2, 2, test3 + Concatenation_SIZE, 2, 0); + BENCH_END(riscv_concatenation_s8_y); + + verify_results_q7(test3, test3 + Concatenation_SIZE, 80); + + printf("Start ref concatenation s8 z implementation\n"); + + BENCH_START(riscv_concatenation_s8_z_ref); + riscv_concatenation_s8_z_ref(test1, 10, 2, 2, 2, test3, 2, 0); + BENCH_END(riscv_concatenation_s8_z_ref); + + printf("Start opt concatenation s8 z implementation\n"); + + BENCH_START(riscv_concatenation_s8_z); + riscv_concatenation_s8_z(test1, 10, 2, 2, 2, test3 + Concatenation_SIZE, 2, 0); + BENCH_END(riscv_concatenation_s8_z); + + verify_results_q7(test3, test3 + Concatenation_SIZE, 80); + + delete[] test1; + delete[] test3; + +#endif + +#ifdef TEST_Convolution_part1 +#define Convolution_SIZE 2000 + test1 = new q7_t[Convolution_SIZE * 4]; + test3 = new q7_t[Convolution_SIZE * 2]; + test4 = new q15_t[Convolution_SIZE * 2]; + + q7_t *temp_buffer = new q7_t[Convolution_SIZE]; + // int32_t multiplier = 1082196480; + // int32_t shift = -4; + int32_t multiplier = 1374389535; + int32_t shift = -5; + int32_t *test7 = new int32_t[Convolution_SIZE * 2]; + for (int i = 0; i < Convolution_SIZE; i++) { + test7[i] = (rand() % 256 - 128); + test7[i + Convolution_SIZE] = test7[i]; + test1[i] = (rand() % 256 - 128); + test1[i + Convolution_SIZE] = test1[i]; + test1[i + Convolution_SIZE * 2] = test1[i]; + test1[i + Convolution_SIZE * 3] = test1[i]; + } + q7_t input[32] = { 60, 57, 62, 68, 56, 34, 34, 42, 63, 57, 28, 26, 36, 24, 7, 25, 31, 0, 29, 35, 1, 11, 1, 30, 31, 22, 17, 9, 19, 35, -2, 1 }; + q7_t conv_input[16] = { -85, -85, -85, -85, -43, -43, -43, -43, -85, -43, 0, 42, -85, -43, 0, 42 }; + q7_t conv_filter[12] = { 32, 64, 95, 127, -127, 127, -127, 127, -127, -127, 127, 127 }; + int32_t conv_bias[3] = { 1349, 10795, -16193 }; + + for (int i = 0; i < Convolution_SIZE * 2; i++) { + test3[i] = (rand() % 256 - 128); + test3[i + Convolution_SIZE] = test3[i]; + } + nmsis_nn_context ctx = { temp_buffer, 0 }; + // nmsis_nn_tile stride = {2,2}, padding = {0,0}, dilation = {1,1}; + nmsis_nn_tile stride = { 1, 1 }, padding = { 0, 0 }, dilation = { 1, 1 }; + // stride = padding = dilation = {2,2}; + nmsis_nn_activation activation = { -128, 127 }; + nmsis_nn_conv_params conv_params = { 128, -128, stride, padding, dilation, activation }; + nmsis_nn_per_channel_quant_params quant_params = { &multiplier, &shift }; + nmsis_nn_dims input_dims = { 1, 1, 1, 32 }; + nmsis_nn_dims filter_dims = { 32, 1, 1, 32 }; + nmsis_nn_dims bias_dims = { 1, 1, 1, 32 }; + nmsis_nn_dims output_dims = { 1, 1, 1, 32 }; + nmsis_nn_dw_conv_params dw_conv_params = { 0, 0, 1, stride, padding, dilation, activation }; + printf("Start ref convolve_1_x_n s8 implementation\n"); + + BENCH_START(riscv_convolve_1_x_n_s8_ref); + riscv_convolve_1_x_n_s8_ref(&ctx, &conv_params, &quant_params, &input_dims, test1, &filter_dims, test1 + Convolution_SIZE, &bias_dims, test7, &output_dims, test3); + BENCH_END(riscv_convolve_1_x_n_s8_ref); + + printf("Start opt convolve_1_x_n s8 implementation\n"); + + BENCH_START(riscv_convolve_1_x_n_s8); + riscv_convolve_1_x_n_s8(&ctx, &conv_params, &quant_params, &input_dims, test1, &filter_dims, test1 + Convolution_SIZE, &bias_dims, test7 + Convolution_SIZE, &output_dims, test3); + BENCH_END(riscv_convolve_1_x_n_s8); + + verify_results_int32(test7, test7 + Convolution_SIZE, 320); + + for (int i = 0; i < Convolution_SIZE; i++) { + test3[i] = 0; + test3[i + Convolution_SIZE] = test3[i]; + } + //This function may have problem + printf("Start ref convolve_1x1_HWC_fast_nonsquare q7 implementation\n"); + + BENCH_START(riscv_convolve_1x1_HWC_q7_fast_nonsquare_ref); + riscv_convolve_1x1_HWC_q7_fast_nonsquare_ref(test1, 1, 1, 40, test1 + Convolution_SIZE, 40, 1, 1, 0, 0, 1, 1, test1 + Convolution_SIZE * 2, 0, 0, test3, 2, 2, test4, test1 + Convolution_SIZE * 3); + BENCH_END(riscv_convolve_1x1_HWC_q7_fast_nonsquare_ref); + + printf("Start opt convolve_1x1_HWC_fast_nonsquare q7 implementation\n"); + BENCH_START(riscv_convolve_1x1_HWC_q7_fast_nonsquare); + riscv_convolve_1x1_HWC_q7_fast_nonsquare(test1, 1, 1, 40, test1 + Convolution_SIZE, 40, 1, 1, 0, 0, 1, 1, test1 + Convolution_SIZE * 2, 0, 0, test3 + Convolution_SIZE, 2, 2, test4, test1 + Convolution_SIZE * 3); + BENCH_END(riscv_convolve_1x1_HWC_q7_fast_nonsquare); + + verify_results_q7(test3, test3 + Convolution_SIZE, 40); + + printf("Start ref convolve s8 implementation\n"); + + BENCH_START(riscv_convolve_s8_ref); + riscv_convolve_s8_ref(&ctx, &conv_params, &quant_params, &input_dims, conv_input, &filter_dims, conv_filter, &bias_dims, conv_bias, &output_dims, test3); + BENCH_END(riscv_convolve_s8_ref); + + printf("Start opt convolve s8 implementation\n"); + + BENCH_START(riscv_convolve_s8); + riscv_convolve_s8(&ctx, &conv_params, &quant_params, &input_dims, conv_input, &filter_dims, conv_filter, &bias_dims, conv_bias, &output_dims, test3 + Convolution_SIZE); + BENCH_END(riscv_convolve_s8); + verify_results_q7(test3, test3 + Convolution_SIZE, 12); + filter_dims.w = 3; + filter_dims.h = 3; + dw_conv_params.padding.w = 0; + input_dims.c = 4; + printf("Start ref depthwise_conv_3x3 s8 implementation\n"); + + BENCH_START(riscv_depthwise_conv_3x3_s8_ref); + riscv_depthwise_conv_3x3_s8_ref(&ctx, &dw_conv_params, &quant_params, &input_dims, test1, &filter_dims, test1 + Convolution_SIZE, &bias_dims, test7, &output_dims, test3); + BENCH_END(riscv_depthwise_conv_3x3_s8_ref); + + printf("Start opt depthwise_conv_3x3 s8 implementation\n"); + + BENCH_START(riscv_depthwise_conv_3x3_s8); + riscv_depthwise_conv_3x3_s8(&ctx, &dw_conv_params, &quant_params, &input_dims, test1, &filter_dims, test1 + Convolution_SIZE, &bias_dims, test7 + Convolution_SIZE, &output_dims, test3); + BENCH_END(riscv_depthwise_conv_3x3_s8); + + verify_results_int32(test7, test7 + Convolution_SIZE, 360); + dw_conv_params.ch_mult = 3; + + printf("Start ref depthwise_conv_s8 s8 implementation\n"); + + BENCH_START(riscv_depthwise_conv_s8_ref); + riscv_depthwise_conv_s8_ref(&ctx, &dw_conv_params, &quant_params, &input_dims, test1, &filter_dims, test1 + Convolution_SIZE, &bias_dims, test7, &output_dims, test3); + BENCH_END(riscv_depthwise_conv_s8_ref); + + printf("Start opt depthwise_conv_s8 s8 implementation\n"); + + BENCH_START(riscv_depthwise_conv_s8); + riscv_depthwise_conv_s8(&ctx, &dw_conv_params, &quant_params, &input_dims, test1, &filter_dims, test1 + Convolution_SIZE, &bias_dims, test7 + Convolution_SIZE, &output_dims, test3); + BENCH_END(riscv_depthwise_conv_s8); + + verify_results_int32(test7, test7 + Convolution_SIZE, 140); + dw_conv_params.ch_mult = 4; + + printf("Start ref depthwise_conv_s8_opt s8 implementation\n"); + + for (int i = 0; i < Convolution_SIZE; i++) { + test3[i] = 0; + test3[i + Convolution_SIZE] = test3[i]; + } + + BENCH_START(riscv_depthwise_conv_s8_opt_ref); + riscv_depthwise_conv_s8_opt_ref(&ctx, &dw_conv_params, &quant_params, &input_dims, input, &filter_dims, test1 + Convolution_SIZE, &bias_dims, test7, &output_dims, test3); + BENCH_END(riscv_depthwise_conv_s8_opt_ref); + + printf("Start opt depthwise_conv_s8_opt s8 implementation\n"); + + BENCH_START(riscv_depthwise_conv_s8_opt); + riscv_depthwise_conv_s8_opt(&ctx, &dw_conv_params, &quant_params, &input_dims, input, &filter_dims, test1 + Convolution_SIZE, &bias_dims, test7, &output_dims, test3 + Convolution_SIZE); + BENCH_END(riscv_depthwise_conv_s8_opt); + + verify_results_q7(test3, test3 + Convolution_SIZE, 32); + uint8_t *test10 = new uint8_t[Convolution_SIZE]; + uint8_t *test11 = new uint8_t[Convolution_SIZE]; + int32_t *test12 = new int32_t[Convolution_SIZE]; + uint8_t *test13 = new uint8_t[Convolution_SIZE * 2]; + for (int i = 0; i < Convolution_SIZE; i++) { + test10[i] = (rand() % 256 - 128); + test11[i] = (rand() % 256 - 128); + test12[i] = (rand() % 65536 - 32768); + } + + printf("Start ref depthwise_conv_u8_basic_ver1 s8 implementation\n"); + + BENCH_START(riscv_depthwise_conv_u8_basic_ver1_ref); + riscv_depthwise_conv_u8_basic_ver1_ref(test10, 4, 4, 4, test11, 4, 4, 4, 4, 4, 4, 4, 4, 4, test12, 0, 0, 0, test13, 4, 4, -100, 100, 0, 1); + BENCH_END(riscv_depthwise_conv_u8_basic_ver1_ref); + + printf("Start opt depthwise_conv_u8_basic_ver1 s8 implementation\n"); + + BENCH_START(riscv_depthwise_conv_u8_basic_ver1); + riscv_depthwise_conv_u8_basic_ver1(test10, 4, 4, 4, test11, 4, 4, 4, 4, 4, 4, 4, 4, 4, test12, 0, 0, 0, test13 + Convolution_SIZE, 4, 4, -100, 100, 0, 1); + BENCH_END(riscv_depthwise_conv_u8_basic_ver1); + + verify_results_q7((q7_t *)test13, (q7_t *)(test13 + Convolution_SIZE), 64); + + // set default value + input_dims.c = 4; + conv_params.padding.w = 0; + conv_params.padding.h = 0; + conv_params.stride.w = 1; + conv_params.stride.h = 1; + input_dims.w = 5; + input_dims.h = 5; + input_dims.n = 1; + ctx = { temp_buffer + 40, 10 }; + //This function does not have connected read & write especially write size not connected + printf("Start ref convolve_1x1_HWC_fast_nonsquare q7 implementation\n"); + + BENCH_START(riscv_convolve_1x1_s8_fast_ref); + riscv_convolve_1x1_s8_fast_ref(&ctx, &conv_params, &quant_params, &input_dims, test1, &filter_dims, test1 + Convolution_SIZE * 2, &bias_dims, test7, &output_dims, test3); + BENCH_END(riscv_convolve_1x1_s8_fast_ref); + + printf("Start opt convolve_1x1_HWC_fast_nonsquare q7 implementation\n"); + BENCH_START(riscv_convolve_1x1_s8_fast); + riscv_convolve_1x1_s8_fast(&ctx, &conv_params, &quant_params, &input_dims, test1, &filter_dims, test1 + Convolution_SIZE * 3, &bias_dims, test7, &output_dims, test3 + Convolution_SIZE); + BENCH_END(riscv_convolve_1x1_s8_fast); + + verify_results_q7(test3, test3 + Convolution_SIZE, 100); + + // delete[]test1; + // delete[]test3; + // delete[]test4; + // delete[]test10; + // delete[]test11; + // delete[]test12; + // delete[]test13; + +#endif + +#ifdef TEST_Convolution_part2 +#define CONV_IM_DIM 8 +#define CONV_IM_CH 8 +#define CONV_KER_DIM 5 +#define CONV_OUT_CH 8 +#define CONV_OUT_DIM 8 + + test1 = new q7_t[CONV_KER_DIM * CONV_KER_DIM * CONV_IM_CH * CONV_OUT_CH + CONV_OUT_CH]; + test2 = + new q15_t[CONV_KER_DIM * CONV_KER_DIM * CONV_IM_CH * CONV_OUT_CH + + 2 * CONV_KER_DIM * CONV_KER_DIM * CONV_IM_CH * CONV_OUT_CH + CONV_OUT_CH]; + test3 = new q7_t[CONV_IM_DIM * CONV_IM_DIM * CONV_IM_CH + 2 * CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH]; + test4 = new q15_t[CONV_IM_DIM * CONV_IM_DIM * CONV_IM_CH + 2 * CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH]; + + for (int i = 0; i < CONV_KER_DIM * CONV_KER_DIM * CONV_IM_CH * CONV_OUT_CH + CONV_OUT_CH; i++) { + test1[i] = rand() % 200 - 100; + } + + for (int i = 0; + i < + CONV_KER_DIM * CONV_KER_DIM * CONV_IM_CH * CONV_OUT_CH + + 2 * CONV_KER_DIM * CONV_KER_DIM * CONV_IM_CH * CONV_OUT_CH + CONV_OUT_CH; + i++) { + test2[i] = (rand() % 65536 - 32768); + } + + for (int i = 0; i < CONV_IM_DIM * CONV_IM_DIM * CONV_IM_CH + 2 * CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH; i++) { + test3[i] = rand() % 200 - 100; + } + + for (int i = 0; i < CONV_IM_DIM * CONV_IM_DIM * CONV_IM_CH + 2 * CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH; i++) { + test4[i] = (rand() % 65536 - 32768); + } + + q7_t *conv_weight_q7 = test1; + q7_t *conv_bias_q7 = test1 + CONV_KER_DIM * CONV_KER_DIM * CONV_IM_CH * CONV_OUT_CH; + + q15_t *conv_weight_q15 = test2; + q15_t *conv_buf = test2 + CONV_KER_DIM * CONV_KER_DIM * CONV_IM_CH * CONV_OUT_CH; + q15_t *conv_bias_q15 = + test2 + CONV_KER_DIM * CONV_KER_DIM * CONV_IM_CH * CONV_OUT_CH + + 2 * CONV_KER_DIM * CONV_KER_DIM * CONV_IM_CH * CONV_OUT_CH; + + q7_t *conv_im_in_q7 = test3; + q7_t *conv_im_out_ref_q7 = test3 + CONV_IM_DIM * CONV_IM_DIM * CONV_IM_CH; + q7_t *conv_im_out_opt_q7 = + test3 + CONV_IM_DIM * CONV_IM_DIM * CONV_IM_CH + CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH; + + q15_t *conv_im_in_q15 = test4; + q15_t *conv_im_out_ref_q15 = test4 + CONV_IM_DIM * CONV_IM_DIM * CONV_IM_CH; + q15_t *conv_im_out_opt_q15 = + test4 + CONV_IM_DIM * CONV_IM_DIM * CONV_IM_CH + CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH; + + initialize_results_q7(conv_im_out_ref_q7, conv_im_out_opt_q7, CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH); + + printf("start q7 ref implementation\n"); + + BENCH_START(riscv_convolve_HWC_q7_ref); + riscv_convolve_HWC_q7_ref(conv_im_in_q7, CONV_IM_DIM, CONV_IM_CH, conv_weight_q7, + CONV_OUT_CH, CONV_KER_DIM, 2, 1, conv_bias_q7, 1, 7, conv_im_out_ref_q7, + CONV_OUT_DIM, conv_buf, NULL); + BENCH_END(riscv_convolve_HWC_q7_ref); + + printf("start q7 basic implementation\n"); + + BENCH_START(riscv_convolve_HWC_q7_basic); + riscv_convolve_HWC_q7_basic(conv_im_in_q7, CONV_IM_DIM, CONV_IM_CH, conv_weight_q7, + CONV_OUT_CH, CONV_KER_DIM, 2, 1, conv_bias_q7, 1, 7, conv_im_out_opt_q7, + CONV_OUT_DIM, conv_buf, NULL); + BENCH_END(riscv_convolve_HWC_q7_basic); + + verify_results_q7(conv_im_out_ref_q7, conv_im_out_opt_q7, CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH); + + printf("start q7 fast implementation\n"); + + BENCH_START(riscv_convolve_HWC_q7_fast); + riscv_convolve_HWC_q7_fast(conv_im_in_q7, CONV_IM_DIM, CONV_IM_CH, conv_weight_q7, + CONV_OUT_CH, CONV_KER_DIM, 2, 1, conv_bias_q7, 1, 7, conv_im_out_opt_q7, + CONV_OUT_DIM, conv_buf, NULL); + BENCH_END(riscv_convolve_HWC_q7_fast); + + verify_results_q7(conv_im_out_ref_q7, conv_im_out_opt_q7, CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH); + + printf("start q7 ref implementation for RGB\n"); + + BENCH_START(riscv_convolve_HWC_q7_ref); + riscv_convolve_HWC_q7_ref(conv_im_in_q7, CONV_IM_DIM, 3, conv_weight_q7, + CONV_OUT_CH, CONV_KER_DIM, 2, 1, conv_bias_q7, 1, 7, conv_im_out_ref_q7, + CONV_OUT_DIM, conv_buf, NULL); + BENCH_END(riscv_convolve_HWC_q7_ref); + + printf("start q7 RGB implementation for RGB\n"); + + BENCH_START(riscv_convolve_HWC_q7_RGB); + riscv_convolve_HWC_q7_RGB(conv_im_in_q7, CONV_IM_DIM, 3, conv_weight_q7, + CONV_OUT_CH, CONV_KER_DIM, 2, 1, conv_bias_q7, 1, 7, conv_im_out_opt_q7, + CONV_OUT_DIM, conv_buf, NULL); + BENCH_END(riscv_convolve_HWC_q7_RGB); + + verify_results_q7(conv_im_out_ref_q7, conv_im_out_opt_q7, CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH); + + // delete[]test1; + // delete[]test2; + // delete[]test3; + // delete[]test4; +#endif + +#ifdef TEST_Convolution_part3 +#define RCONV_IM_DIM_X 10 +#define RCONV_IM_DIM_Y 8 +#define RCONV_IM_CH 4 +#define RCONV_KER_DIM_X 5 +#define RCONV_KER_DIM_Y 3 +#define RCONV_STRIDE_X 1 +#define RCONV_STRIDE_Y 1 +#define RCONV_PADDING_X 2 +#define RCONV_PADDING_Y 1 +#define RCONV_OUT_CH 4 +#define RCONV_OUT_DIM_X 10 +#define RCONV_OUT_DIM_Y 8 + + test1 = new q7_t[RCONV_KER_DIM_Y * RCONV_KER_DIM_X * RCONV_IM_CH * RCONV_OUT_CH + RCONV_OUT_CH]; + test2 = new q15_t[2 * RCONV_KER_DIM_Y * RCONV_KER_DIM_X * RCONV_IM_CH]; + test3 = + new q7_t[RCONV_IM_DIM_Y * RCONV_IM_DIM_X * RCONV_IM_CH + 2 * RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH]; + + for (int i = 0; i < RCONV_KER_DIM_Y * RCONV_KER_DIM_X * RCONV_IM_CH * RCONV_OUT_CH + RCONV_OUT_CH; i++) { + test1[i] = rand() % 200 - 100; + } + + for (int i = 0; + i < RCONV_IM_DIM_Y * RCONV_IM_DIM_X * RCONV_IM_CH + 2 * RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH; i++) { + test3[i] = rand() % 256 - 100; + } + + q7_t *rconv_weight_q7 = test1; + q7_t *rconv_bias_q7 = test1 + RCONV_KER_DIM_Y * RCONV_KER_DIM_X * RCONV_IM_CH * RCONV_OUT_CH; + + q15_t *rconv_buf = test2; + + q7_t *rconv_im_in_q7 = test3; + q7_t *rconv_im_out_ref_q7 = test3 + RCONV_IM_DIM_Y * RCONV_IM_DIM_X * RCONV_IM_CH; + q7_t *rconv_im_out_opt_q7 = + test3 + RCONV_IM_DIM_Y * RCONV_IM_DIM_X * RCONV_IM_CH + RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH; + + initialize_results_q7(rconv_im_out_ref_q7, rconv_im_out_opt_q7, RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH); + + printf("start conv q7 nonsquare ref implementation\n"); + BENCH_START(riscv_convolve_HWC_q7_ref_nonsquare); + riscv_convolve_HWC_q7_ref_nonsquare(rconv_im_in_q7, RCONV_IM_DIM_X, RCONV_IM_DIM_Y, RCONV_IM_CH, rconv_weight_q7, + RCONV_OUT_CH, RCONV_KER_DIM_X, RCONV_KER_DIM_Y, RCONV_PADDING_X, RCONV_PADDING_Y, + RCONV_STRIDE_X, RCONV_STRIDE_Y, rconv_bias_q7, 1, 7, rconv_im_out_ref_q7, + RCONV_OUT_DIM_X, RCONV_OUT_DIM_Y, rconv_buf, NULL); + BENCH_END(riscv_convolve_HWC_q7_ref_nonsquare); + + printf("start conv q7 nonsquare opt implementation\n"); + BENCH_START(riscv_convolve_HWC_q7_fast_nonsquare); + riscv_convolve_HWC_q7_fast_nonsquare(rconv_im_in_q7, RCONV_IM_DIM_X, RCONV_IM_DIM_Y, RCONV_IM_CH, rconv_weight_q7, + RCONV_OUT_CH, RCONV_KER_DIM_X, RCONV_KER_DIM_Y, RCONV_PADDING_X, RCONV_PADDING_Y, + RCONV_STRIDE_X, RCONV_STRIDE_Y, rconv_bias_q7, 1, 7, rconv_im_out_opt_q7, + RCONV_OUT_DIM_X, RCONV_OUT_DIM_Y, rconv_buf, NULL); + BENCH_END(riscv_convolve_HWC_q7_fast_nonsquare); + + verify_results_q7(rconv_im_out_ref_q7, rconv_im_out_opt_q7, RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH); + + initialize_results_q7(rconv_im_out_ref_q7, rconv_im_out_opt_q7, RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH); + + printf("start conv q7 nonsquare ref implementation\n"); + BENCH_START(riscv_convolve_HWC_q7_ref_nonsquare); + riscv_convolve_HWC_q7_ref_nonsquare(rconv_im_in_q7, RCONV_IM_DIM_X, RCONV_IM_DIM_Y, RCONV_IM_CH, rconv_weight_q7, + RCONV_OUT_CH, RCONV_KER_DIM_X, RCONV_KER_DIM_Y, RCONV_PADDING_X, RCONV_PADDING_Y, + RCONV_STRIDE_X, RCONV_STRIDE_Y, rconv_bias_q7, 1, 7, rconv_im_out_ref_q7, + RCONV_OUT_DIM_X, RCONV_OUT_DIM_Y, rconv_buf, NULL); + BENCH_END(riscv_convolve_HWC_q7_ref_nonsquare); + + printf("start conv q7 nonsquare basic implementation\n"); + BENCH_START(riscv_convolve_HWC_q7_basic_nonsquare); + riscv_convolve_HWC_q7_basic_nonsquare(rconv_im_in_q7, RCONV_IM_DIM_X, RCONV_IM_DIM_Y, RCONV_IM_CH, rconv_weight_q7, + RCONV_OUT_CH, RCONV_KER_DIM_X, RCONV_KER_DIM_Y, RCONV_PADDING_X, RCONV_PADDING_Y, + RCONV_STRIDE_X, RCONV_STRIDE_Y, rconv_bias_q7, 1, 7, rconv_im_out_opt_q7, + RCONV_OUT_DIM_X, RCONV_OUT_DIM_Y, rconv_buf, NULL); + BENCH_END(riscv_convolve_HWC_q7_basic_nonsquare); + + verify_results_q7(rconv_im_out_ref_q7, rconv_im_out_opt_q7, RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH); + + initialize_results_q7(rconv_im_out_ref_q7, rconv_im_out_opt_q7, RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH); + + printf("start 1x1 conv q7 nonsquare fast implementation\n"); + BENCH_START(riscv_convolve_HWC_q7_fast_nonsquare); + riscv_convolve_HWC_q7_fast_nonsquare(rconv_im_in_q7, RCONV_IM_DIM_X, RCONV_IM_DIM_Y, RCONV_IM_CH, rconv_weight_q7, + RCONV_OUT_CH, 1, 1, 0, 0, RCONV_STRIDE_X, + RCONV_STRIDE_Y, rconv_bias_q7, 1, 7, rconv_im_out_ref_q7, RCONV_OUT_DIM_X, + RCONV_OUT_DIM_Y, rconv_buf, NULL); + BENCH_END(riscv_convolve_HWC_q7_fast_nonsquare); + + printf("start 1x1 conv q7 nonsquare dedicated function implementation\n"); + BENCH_START(riscv_convolve_1x1_HWC_q7_fast_nonsquare); + riscv_convolve_1x1_HWC_q7_fast_nonsquare(rconv_im_in_q7, RCONV_IM_DIM_X, RCONV_IM_DIM_Y, RCONV_IM_CH, rconv_weight_q7, + RCONV_OUT_CH, 1, 1, 0, 0, RCONV_STRIDE_X, + RCONV_STRIDE_Y, rconv_bias_q7, 1, 7, rconv_im_out_opt_q7, RCONV_OUT_DIM_X, + RCONV_OUT_DIM_Y, rconv_buf, NULL); + BENCH_END(riscv_convolve_1x1_HWC_q7_fast_nonsquare); + + verify_results_q7(rconv_im_out_ref_q7, rconv_im_out_opt_q7, RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH); + + printf("start depthwise separable conv q7 nonsquare ref implementation\n"); + BENCH_START(riscv_depthwise_separable_conv_HWC_q7_ref_nonsquare); + riscv_depthwise_separable_conv_HWC_q7_ref_nonsquare(rconv_im_in_q7, RCONV_IM_DIM_X, RCONV_IM_DIM_Y, RCONV_IM_CH, + rconv_weight_q7, RCONV_OUT_CH, RCONV_KER_DIM_X, RCONV_KER_DIM_Y, + RCONV_PADDING_X, RCONV_PADDING_Y, RCONV_STRIDE_X, RCONV_STRIDE_Y, + rconv_bias_q7, 1, 7, rconv_im_out_ref_q7, RCONV_OUT_DIM_X, + RCONV_OUT_DIM_Y, rconv_buf, NULL); + BENCH_END(riscv_depthwise_separable_conv_HWC_q7_ref_nonsquare); + + printf("start depthwise separable conv q7 nonsquare opt implementation\n"); + BENCH_START(riscv_depthwise_separable_conv_HWC_q7_nonsquare); + riscv_depthwise_separable_conv_HWC_q7_nonsquare(rconv_im_in_q7, RCONV_IM_DIM_X, RCONV_IM_DIM_Y, RCONV_IM_CH, + rconv_weight_q7, RCONV_OUT_CH, RCONV_KER_DIM_X, RCONV_KER_DIM_Y, + RCONV_PADDING_X, RCONV_PADDING_Y, RCONV_STRIDE_X, RCONV_STRIDE_Y, + rconv_bias_q7, 1, 7, rconv_im_out_opt_q7, RCONV_OUT_DIM_X, + RCONV_OUT_DIM_Y, rconv_buf, NULL); + BENCH_END(riscv_depthwise_separable_conv_HWC_q7_nonsquare); + + verify_results_q7(rconv_im_out_ref_q7, rconv_im_out_opt_q7, RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH); + + delete[] test1; + delete[] test3; + + test2 = new q15_t[RCONV_KER_DIM_Y * RCONV_KER_DIM_X * RCONV_IM_CH * RCONV_OUT_CH + RCONV_OUT_CH]; // weights + bias + test4 = new q15_t[2 * RCONV_KER_DIM_Y * RCONV_KER_DIM_X * RCONV_IM_CH //buffer + + RCONV_IM_DIM_Y * RCONV_IM_DIM_X * RCONV_IM_CH + 2 * RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH]; // i/o + + for (int i = 0; i < RCONV_KER_DIM_Y * RCONV_KER_DIM_X * RCONV_IM_CH * RCONV_OUT_CH + RCONV_OUT_CH; i++) { + test2[i] = rand() % 256 - 100; + } + + for (int i = 0; + i < 2 * RCONV_KER_DIM_Y * RCONV_KER_DIM_X * RCONV_IM_CH + RCONV_IM_DIM_Y * RCONV_IM_DIM_X * RCONV_IM_CH + 2 * RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH; + i++) { + test4[i] = rand() % 256 - 100; + } + + q15_t *rconv_weight_q15 = test2; + q15_t *rconv_bias_q15 = test2 + RCONV_KER_DIM_Y * RCONV_KER_DIM_X * RCONV_IM_CH * RCONV_OUT_CH; + + rconv_buf = test4; + + q15_t *rconv_im_in_q15 = test4 + 2 * RCONV_KER_DIM_Y * RCONV_KER_DIM_X * RCONV_IM_CH; + q15_t *rconv_im_out_ref_q15 = rconv_im_in_q15 + RCONV_IM_DIM_Y * RCONV_IM_DIM_X * RCONV_IM_CH; + q15_t *rconv_im_out_opt_q15 = rconv_im_out_ref_q15 + RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH; + + initialize_results_q15(rconv_im_out_ref_q15, rconv_im_out_opt_q15, RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH); + + printf("start conv q15 nonsquare ref implementation\n"); + BENCH_START(riscv_convolve_HWC_q15_nonsquare_ref); + riscv_convolve_HWC_q15_nonsquare_ref(rconv_im_in_q15, RCONV_IM_DIM_X, RCONV_IM_DIM_Y, RCONV_IM_CH, rconv_weight_q15, + RCONV_OUT_CH, RCONV_KER_DIM_X, RCONV_KER_DIM_Y, RCONV_PADDING_X, RCONV_PADDING_Y, + RCONV_STRIDE_X, RCONV_STRIDE_Y, rconv_bias_q15, 1, 7, rconv_im_out_ref_q15, + RCONV_OUT_DIM_X, RCONV_OUT_DIM_Y, rconv_buf, NULL); + BENCH_END(riscv_convolve_HWC_q15_nonsquare_ref); + + printf("start conv q5 nonsquare opt implementation\n"); + BENCH_START(riscv_convolve_HWC_q15_fast_nonsquare); + riscv_convolve_HWC_q15_fast_nonsquare(rconv_im_in_q15, RCONV_IM_DIM_X, RCONV_IM_DIM_Y, RCONV_IM_CH, rconv_weight_q15, + RCONV_OUT_CH, RCONV_KER_DIM_X, RCONV_KER_DIM_Y, RCONV_PADDING_X, RCONV_PADDING_Y, + RCONV_STRIDE_X, RCONV_STRIDE_Y, rconv_bias_q15, 1, 7, rconv_im_out_opt_q15, + RCONV_OUT_DIM_X, RCONV_OUT_DIM_Y, rconv_buf, NULL); + BENCH_END(riscv_convolve_HWC_q15_fast_nonsquare); + + verify_results_q15(rconv_im_out_ref_q15, rconv_im_out_opt_q15, RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH); + +#endif + +#ifdef TEST_Fully_connectedLayer +#define IP_ROW_DIM 127 +#define IP_COL_DIM 127 + + q7_t ip_weights[IP_ROW_DIM * IP_COL_DIM] = IP2_WEIGHT; + q7_t ip_q7_opt_weights[IP_ROW_DIM * IP_COL_DIM] = IP4_WEIGHT; + q7_t ip_q7_q15_opt_weights[IP_ROW_DIM * IP_COL_DIM] = IP4_q7_q15_WEIGHT; + q15_t ip_q15_weights[IP_ROW_DIM * IP_COL_DIM] = IP2_WEIGHT; + q15_t ip_q15_opt_weights[IP_ROW_DIM * IP_COL_DIM] = IP4_WEIGHT_Q15; + + test1 = new q7_t[IP_COL_DIM * 2 + IP_ROW_DIM * 2]; + test2 = new q15_t[IP_COL_DIM]; + test3 = new q7_t[IP_COL_DIM * 2 + IP_ROW_DIM * 3]; + test4 = new q15_t[IP_COL_DIM * 2 + IP_ROW_DIM * 2]; + + for (int i = 0; i < IP_ROW_DIM + IP_COL_DIM; i++) { + test1[i] = rand() % 256 - 100; + } + for (int i = 0; i < IP_ROW_DIM * 3; i++) { + test3[i] = 0; + } + + q7_t *ip_bias_q7 = test1 + IP_COL_DIM; + + q7_t *ip_out_q7_ref = test3; + q7_t *ip_out_q7_opt = test3 + IP_ROW_DIM; + q7_t *ip_out_q7_opt_fast = test3 + 2 * IP_ROW_DIM; + q15_t *ip_out_q15_ref = test4 + IP_COL_DIM; + q15_t *ip_out_q15_opt = test4 + IP_COL_DIM + IP_ROW_DIM; + + initialize_results_q7(ip_out_q7_ref, ip_out_q7_opt, IP_ROW_DIM); + initialize_results_q7(ip_out_q7_ref, ip_out_q7_opt_fast, IP_ROW_DIM); + initialize_results_q7(ip_out_q7_ref, ip_out_q7_opt_fast, IP_ROW_DIM); + + printf("Start ref q7 implementation\n"); + + BENCH_START(riscv_fully_connected_q7_ref); + riscv_fully_connected_q7_ref(test1, ip_weights, IP_COL_DIM, IP_ROW_DIM, 1, 7, ip_bias_q7, ip_out_q7_ref, test2); + BENCH_END(riscv_fully_connected_q7_ref); + + printf("Start q7 implementation\n"); + + BENCH_START(riscv_fully_connected_q7); + riscv_fully_connected_q7(test1, ip_weights, IP_COL_DIM, IP_ROW_DIM, 1, 7, ip_bias_q7, ip_out_q7_opt, test2); + BENCH_END(riscv_fully_connected_q7); + + verify_results_q7(ip_out_q7_ref, ip_out_q7_opt, IP_ROW_DIM); + + printf("Start q7 ref opt implementation\n"); + + BENCH_START(riscv_fully_connected_q7_opt_ref); + riscv_fully_connected_q7_opt_ref(test1, ip_q7_opt_weights, IP_COL_DIM, IP_ROW_DIM, 1, 7, ip_bias_q7, + ip_out_q7_opt_fast, test2); + BENCH_END(riscv_fully_connected_q7_opt_ref); + + verify_results_q7(ip_out_q7_ref, ip_out_q7_opt_fast, IP_ROW_DIM); + + printf("Start q7 opt implementation\n"); + + BENCH_START(riscv_fully_connected_q7_opt); + riscv_fully_connected_q7_opt(test1, ip_q7_opt_weights, IP_COL_DIM, IP_ROW_DIM, 1, 7, ip_bias_q7, ip_out_q7_opt_fast, + test2); + BENCH_END(riscv_fully_connected_q7_opt); + + verify_results_q7(ip_out_q7_ref, ip_out_q7_opt_fast, IP_ROW_DIM); + + for (int i = 0; i < IP_ROW_DIM + IP_COL_DIM; i++) { + test4[i] = (rand() % 20500 - 10700); + } + + initialize_results_q15(ip_out_q15_ref, ip_out_q15_opt, IP_ROW_DIM); + + printf("Start ref q15 implementation\n"); + + BENCH_START(riscv_fully_connected_q15_ref); + riscv_fully_connected_q15_ref(test4, ip_q15_weights, IP_COL_DIM, IP_ROW_DIM, 1, 7, test2, ip_out_q15_ref, NULL); + BENCH_END(riscv_fully_connected_q15_ref); + + printf("Start q15 implementation\n"); + + BENCH_START(riscv_fully_connected_q15); + riscv_fully_connected_q15(test4, ip_q15_weights, IP_COL_DIM, IP_ROW_DIM, 1, 7, test2, ip_out_q15_opt, NULL); + BENCH_END(riscv_fully_connected_q15); + + verify_results_q15(ip_out_q15_ref, ip_out_q15_opt, IP_ROW_DIM); + + printf("Start ref opt q15 implementation\n"); + + BENCH_START(riscv_fully_connected_q15_opt_ref); + riscv_fully_connected_q15_opt_ref(test4, ip_q15_opt_weights, IP_COL_DIM, IP_ROW_DIM, 1, 7, test2, ip_out_q15_opt, + NULL); + BENCH_END(riscv_fully_connected_q15_opt_ref); + + verify_results_q15(ip_out_q15_ref, ip_out_q15_opt, IP_ROW_DIM); + + printf("Start opt q15 implementation\n"); + + BENCH_START(riscv_fully_connected_q15_opt); + riscv_fully_connected_q15_opt(test4, ip_q15_opt_weights, IP_COL_DIM, IP_ROW_DIM, 1, 7, test2, ip_out_q15_opt, NULL); + BENCH_END(riscv_fully_connected_q15_opt); + + verify_results_q15(ip_out_q15_ref, ip_out_q15_opt, IP_ROW_DIM); + + initialize_results_q15(ip_out_q15_ref, ip_out_q15_opt, IP_ROW_DIM); + + printf("Start ref q7_q15 implementation\n"); + + BENCH_START(riscv_fully_connected_mat_q7_vec_q15_ref); + riscv_fully_connected_mat_q7_vec_q15_ref(test4, ip_weights, IP_COL_DIM, IP_ROW_DIM, 1, 7, ip_bias_q7, ip_out_q15_ref, + test2); + BENCH_END(riscv_fully_connected_mat_q7_vec_q15_ref); + + printf("Start q7_q15 implementation\n"); + + BENCH_START(riscv_fully_connected_mat_q7_vec_q15); + riscv_fully_connected_mat_q7_vec_q15(test4, ip_weights, IP_COL_DIM, IP_ROW_DIM, 1, 7, ip_bias_q7, ip_out_q15_opt, + test2); + BENCH_END(riscv_fully_connected_mat_q7_vec_q15); + + verify_results_q15(ip_out_q15_ref, ip_out_q15_opt, IP_ROW_DIM); + + printf("Start ref opt q7_q15 implementation\n"); + + BENCH_START(riscv_fully_connected_mat_q7_vec_q15_opt_ref); + riscv_fully_connected_mat_q7_vec_q15_opt_ref(test4, ip_q7_q15_opt_weights, IP_COL_DIM, IP_ROW_DIM, 1, 7, ip_bias_q7, + ip_out_q15_opt, test2); + BENCH_END(riscv_fully_connected_mat_q7_vec_q15_opt_ref); + + verify_results_q15(ip_out_q15_ref, ip_out_q15_opt, IP_ROW_DIM); + + printf("Start opt q7_q15 implementation\n"); + + BENCH_START(riscv_fully_connected_mat_q7_vec_q15_opt); + riscv_fully_connected_mat_q7_vec_q15_opt(test4, ip_q7_q15_opt_weights, IP_COL_DIM, IP_ROW_DIM, 1, 7, ip_bias_q7, + ip_out_q15_opt, test2); + BENCH_END(riscv_fully_connected_mat_q7_vec_q15_opt); + + verify_results_q15(ip_out_q15_ref, ip_out_q15_opt, IP_ROW_DIM); + + int32_t fc_multiplier = 1; + int32_t fc_shift = 0; + test1 = new q7_t[320 * 2]; + test3 = new q7_t[320 * 2]; + q7_t *fc_temp_buffer = new q7_t[320]; + int32_t *fc_test12 = new int32_t[320]; + nmsis_nn_context fc_ctx = { fc_temp_buffer, 10 }; + nmsis_nn_tile fc_stride = { 2, 2 }; + nmsis_nn_tile fc_padding = { 2, 2 }; + nmsis_nn_tile fc_dilation = { 2, 2 }; + nmsis_nn_activation fc_activation = { -100, 100 }; + nmsis_nn_conv_params fc_conv_params = { 1, 1, fc_stride, fc_padding, fc_dilation, fc_activation }; + nmsis_nn_per_tensor_quant_params fc_quant_params = { fc_multiplier, fc_shift }; + nmsis_nn_dims fc_input_dims = { 20, 2, 4, 2 }; + nmsis_nn_dims fc_filter_dims = { 20, 2, 4, 2 }; + nmsis_nn_dims fc_bias_dims = { 20, 2, 4, 2 }; + nmsis_nn_dims fc_output_dims = { 20, 2, 4, 2 }; + nmsis_nn_fc_params fc_fc_params = { 0, 0, 0, fc_activation }; + + printf("Start ref opt s8 implementation\n"); + + BENCH_START(riscv_fully_connected_s8_ref); + riscv_fully_connected_s8_ref(&fc_ctx, &fc_fc_params, &fc_quant_params, &fc_input_dims, test1, &fc_filter_dims, test1 + 320, &fc_bias_dims, fc_test12, &fc_output_dims, test3); + BENCH_END(riscv_fully_connected_s8_ref); + + printf("Start opt s8 implementation\n"); + + BENCH_START(riscv_fully_connected_s8); + riscv_fully_connected_s8(&fc_ctx, &fc_fc_params, &fc_quant_params, &fc_input_dims, test1, &fc_filter_dims, test1 + 320, &fc_bias_dims, fc_test12, &fc_output_dims, test3 + 320); + BENCH_END(riscv_fully_connected_s8); + + verify_results_q7(test3, test3 + 320, 40); + + delete[] test1; + delete[] test2; + delete[] test3; + delete[] test4; + // delete[]fc_temp_buffer; + // delete[]fc_test12; + +#endif + +#ifdef TEST_Pooling +#define Pooling_SIZE 600 + test1 = new q7_t[Pooling_SIZE * 4]; + test2 = new q15_t[Pooling_SIZE * 2]; + test3 = new q7_t[Pooling_SIZE * 2]; + + q7_t *pool_temp_buffer = new q7_t[Pooling_SIZE * 2]; + int32_t pool_multiplier = 1; + int32_t pool_shift = 0; + for (int i = 0; i < Pooling_SIZE; i++) { + test2[i] = (rand() % 65536 - 32768); + pool_temp_buffer[i] = 0; + pool_temp_buffer[i + Pooling_SIZE] = pool_temp_buffer[i]; + } + for (int i = 0; i < Pooling_SIZE * 2; i++) { + test1[i] = (rand() % 210 - 105); + test1[i + Pooling_SIZE * 2] = test1[i]; + } + nmsis_nn_context pool_ctx = { pool_temp_buffer, 10 }; + nmsis_nn_tile pool_stride = { 0, 0 }; + nmsis_nn_tile pool_padding = { 0, 0 }; + nmsis_nn_tile pool_dilation = { 2, 2 }; + nmsis_nn_activation pool_activation = { -100, 100 }; + nmsis_nn_conv_params pool_conv_params = { 1, 1, pool_stride, pool_padding, pool_dilation, pool_activation }; + nmsis_nn_per_channel_quant_params pool_quant_params = { &pool_multiplier, &pool_shift }; + nmsis_nn_dims pool_input_dims = { 2, 3, 3, 2 }; + nmsis_nn_dims pool_filter_dims = { 2, 3, 3, 2 }; + nmsis_nn_dims pool_bias_dims = { 2, 3, 3, 2 }; + nmsis_nn_dims pool_output_dims = { 2, 9, 9, 2 }; + nmsis_nn_dw_conv_params pool_dw_conv_params = { 0, 0, 1, pool_stride, pool_padding, pool_dilation, pool_activation }; + nmsis_nn_pool_params pool_pool_params = { pool_stride, pool_padding, pool_activation }; + + printf("Start ref max_pool s8 implementation\n"); + + BENCH_START(riscv_max_pool_s8_ref); + riscv_max_pool_s8_ref(&pool_ctx, &pool_pool_params, &pool_input_dims, test1, &pool_filter_dims, &pool_output_dims, test3); + BENCH_END(riscv_max_pool_s8_ref); + + printf("Start opt max_pool s8 implementation\n"); + + BENCH_START(riscv_max_pool_s8); + riscv_max_pool_s8(&pool_ctx, &pool_pool_params, &pool_input_dims, test1, &pool_filter_dims, &pool_output_dims, test3 + Pooling_SIZE); + BENCH_END(riscv_max_pool_s8); + + verify_results_q7(test3, test3 + Pooling_SIZE, 18); + + printf("Start ref avgpool s8 implementation\n"); + + BENCH_START(riscv_avgpool_s8_ref); + riscv_avgpool_s8_ref(&pool_ctx, &pool_pool_params, &pool_input_dims, test1, &pool_filter_dims, &pool_output_dims, test3); + BENCH_END(riscv_avgpool_s8_ref); + + printf("Start opt avgpool s8 implementation\n"); + + BENCH_START(riscv_avgpool_s8); + riscv_avgpool_s8(&pool_ctx, &pool_pool_params, &pool_input_dims, test1, &pool_filter_dims, &pool_output_dims, test3 + Pooling_SIZE); + BENCH_END(riscv_avgpool_s8); + + verify_results_q7(test3, test3 + Pooling_SIZE, 18); + +#define POOL_IM_DIM 32 +#define POOL_IM_CH 8 + test1 = new q7_t[POOL_IM_DIM * POOL_IM_DIM * POOL_IM_CH * 2]; + test2 = new q15_t[POOL_IM_DIM * POOL_IM_CH]; + test3 = new q7_t[POOL_IM_DIM * POOL_IM_DIM * POOL_IM_CH]; + + q7_t *img_in = test1 + POOL_IM_DIM * POOL_IM_DIM * POOL_IM_CH; + q7_t *pool_out_ref = test3; + q7_t *pool_out_opt = test3 + POOL_IM_DIM * POOL_IM_DIM * POOL_IM_CH / 2; + + // copy over the img input + for (int i = 0; i < POOL_IM_DIM * POOL_IM_DIM * POOL_IM_CH; i++) { + img_in[i] = test1[i]; + } + + printf("Start maxpool reference implementation\n"); + + BENCH_START(riscv_maxpool_q7_HWC_ref); + riscv_maxpool_q7_HWC_ref(img_in, POOL_IM_DIM, POOL_IM_CH, 3, 0, 2, POOL_IM_DIM / 2, (q7_t *)test2, pool_out_ref); + BENCH_END(riscv_maxpool_q7_HWC_ref); + + printf("Start maxpool opt implementation\n"); + for (int i = 0; i < POOL_IM_DIM * POOL_IM_DIM * POOL_IM_CH; i++) { + img_in[i] = test1[i]; + } + + BENCH_START(riscv_maxpool_q7_HWC); + riscv_maxpool_q7_HWC(img_in, POOL_IM_DIM, POOL_IM_CH, 3, 0, 2, POOL_IM_DIM / 2, (q7_t *)test2, pool_out_opt); + BENCH_END(riscv_maxpool_q7_HWC); + + verify_results_q7(pool_out_ref, pool_out_opt, POOL_IM_DIM / 2 * POOL_IM_DIM / 2 * POOL_IM_CH); + // copy over the img input + for (int i = 0; i < POOL_IM_DIM * POOL_IM_DIM * POOL_IM_CH; i++) { + img_in[i] = test1[i]; + } + + printf("Start avepool ref implementation\n"); + + BENCH_START(riscv_avepool_q7_HWC_ref); + riscv_avepool_q7_HWC_ref(img_in, POOL_IM_DIM, POOL_IM_CH, 3, 0, 2, POOL_IM_DIM / 2, (q7_t *)test2, pool_out_ref); + BENCH_END(riscv_avepool_q7_HWC_ref); + + // copy over the img input + for (int i = 0; i < POOL_IM_DIM * POOL_IM_DIM * POOL_IM_CH; i++) { + img_in[i] = test1[i]; + } + + printf("Start avepool opt implementation\n"); + + BENCH_START(riscv_avepool_q7_HWC); + riscv_avepool_q7_HWC(img_in, POOL_IM_DIM, POOL_IM_CH, 3, 0, 2, POOL_IM_DIM / 2, (q7_t *)test2, pool_out_opt); + BENCH_END(riscv_avepool_q7_HWC); + + verify_results_q7(pool_out_ref, pool_out_opt, POOL_IM_DIM / 2 * POOL_IM_DIM / 2 * POOL_IM_CH); + + delete[] test1; + delete[] test2; + delete[] test3; + delete[] pool_temp_buffer; + +#endif + +#ifdef TEST_Softmax +#define Softmax_SIZE 100 + test1 = new q7_t[Softmax_SIZE * 2]; + test2 = new q15_t[Softmax_SIZE * 2]; + test3 = new q7_t[Softmax_SIZE * 2]; + test4 = new q15_t[Softmax_SIZE * 2]; + uint8_t *test5 = new uint8_t[Softmax_SIZE]; + uint8_t *test6 = new uint8_t[Softmax_SIZE * 2]; + + int8_t *Softmax_test7 = new int8_t[Softmax_SIZE * 2]; + for (int i = 0; i < Softmax_SIZE; i++) { + test5[i] = (rand() % 256); + } + for (int i = 0; i < Softmax_SIZE * 2; i++) { + test2[i] = (rand() % 65536 - 32768); + test1[i] = (rand() % 256 - 128); + } + + printf("Start ref softmax q15 implementation\n"); + + BENCH_START(riscv_softmax_q15_ref); + riscv_softmax_q15_ref(test2, 6, test4); + BENCH_END(riscv_softmax_q15_ref); + + printf("Start opt softmax q15 implementation\n"); + + BENCH_START(riscv_softmax_q15); + riscv_softmax_q15(test2, 6, test4 + Softmax_SIZE); + BENCH_END(riscv_softmax_q15); + + verify_results_q15(test4, test4 + Softmax_SIZE, 6); + + printf("Start ref softmax q7 implementation\n"); + + BENCH_START(riscv_softmax_q7_ref); + riscv_softmax_q7_ref(test1, Softmax_SIZE, test3); + BENCH_END(riscv_softmax_q7_ref); + + printf("Start opt softmax q7 implementation\n"); + + BENCH_START(riscv_softmax_q7); + riscv_softmax_q7(test1, Softmax_SIZE, test3 + Softmax_SIZE); + BENCH_END(riscv_softmax_q7); + + verify_results_q7(test3, test3 + Softmax_SIZE, Softmax_SIZE); + + printf("Start ref softmax s8 implementation\n"); + + BENCH_START(riscv_softmax_s8_ref); + riscv_softmax_s8_ref(test1, 3, 30, 1, 0, -100, Softmax_test7); + BENCH_END(riscv_softmax_s8_ref); + + printf("Start opt softmax s8 implementation\n"); + + BENCH_START(riscv_softmax_s8); + riscv_softmax_s8(test1, 3, 30, 1, 0, -100, Softmax_test7 + Softmax_SIZE); + BENCH_END(riscv_softmax_s8); + + verify_results_q7(Softmax_test7, Softmax_test7 + Softmax_SIZE, 6); + + printf("Start ref softmax u8 implementation\n"); + + BENCH_START(riscv_softmax_u8_ref); + riscv_softmax_u8_ref(test5, 3, 30, 1, 0, -100, test6); + BENCH_END(riscv_softmax_u8_ref); + + printf("Start opt softmax u8 implementation\n"); + + BENCH_START(riscv_softmax_u8); + riscv_softmax_u8(test5, 3, 30, 1, 0, -100, test6 + Softmax_SIZE); + BENCH_END(riscv_softmax_u8); + + verify_results_q7((q7_t *)test6, (q7_t *)(test6 + Softmax_SIZE), 6); + + printf("Start ref softmax_with_batch q7 implementation\n"); + + BENCH_START(riscv_softmax_with_batch_q7_ref); + riscv_softmax_with_batch_q7_ref(test1, 2, 20, test3); + BENCH_END(riscv_softmax_with_batch_q7_ref); + + printf("Start opt softmax_with_batch q7 implementation\n"); + + BENCH_START(riscv_softmax_with_batch_q7); + riscv_softmax_with_batch_q7(test1, 2, 20, test3 + Softmax_SIZE); + BENCH_END(riscv_softmax_with_batch_q7); + + verify_results_q7(test3, test3 + Softmax_SIZE, 40); + + delete[] test1; + delete[] test2; + delete[] test3; + // delete[]test4; + // delete[]test5; + // delete[]test6; + // delete[]Softmax_test7; +#endif + +#ifdef TEST_SVD +#define SVD_SIZE 32 + test1 = new q7_t[SVD_SIZE * 2]; + test2 = new q15_t[SVD_SIZE * 2]; + test3 = new q7_t[SVD_SIZE * 2]; + + q7_t *test20; + test20 = new q7_t[SVD_SIZE * 2]; + + q7_t *test21; + test21 = new q7_t[SVD_SIZE * 2]; + + q31_t *test22; + test22 = new q31_t[SVD_SIZE * 2]; + + for (int i = 0; i < SVD_SIZE * 2; i++) { + test1[i] = (rand() % 256 - 128); + test20[i] = (rand() % 256 - 128); + test21[i] = (rand() % 256 - 128); + test22[i] = (rand() % 65535 - 32767); + } + + nmsis_nn_context SVD_input_ctx = { test1, SVD_SIZE }; + nmsis_nn_context SVD_output_ctx_opt = { test20, SVD_SIZE }; + nmsis_nn_context SVD_output_ctx_ref = { test20 + SVD_SIZE, SVD_SIZE }; + nmsis_nn_svdf_params SVD_svdf_params = { 32, 0, 0, -100, 100, -100, 100 }; + nmsis_nn_per_tensor_quant_params SVD_input_quant_params = { 1, 0 }; + nmsis_nn_per_tensor_quant_params SVD_output_quant_params = { 1, 0 }; + nmsis_nn_dims SVD_input_dims = { 20, 32, 32, 1 }; + nmsis_nn_dims SVD_weights_feature_dims = { 20, 32, 32, 1 }; + nmsis_nn_dims SVD_weights_time_dims = { 20, 32, 32, 1 }; + // Does not matter what these arguments are + nmsis_nn_dims SVD_state_dims = { 20, 32, 32, 1 }; + nmsis_nn_dims SVD_output_dims = { 20, 32, 32, 1 }; + nmsis_nn_dims SVD_bias_dims = { 20, 32, 32, 1 }; + + printf("Start ref SVD implementation\n"); + + BENCH_START(ref_svdf_s8); + ref_svdf_s8(&SVD_input_ctx, &SVD_output_ctx_ref, &SVD_svdf_params, &SVD_input_quant_params, + &SVD_output_quant_params, &SVD_input_dims, test1 + SVD_SIZE, &SVD_state_dims, + test2, &SVD_weights_feature_dims, test21, &SVD_weights_time_dims, + test2 + SVD_SIZE, &SVD_bias_dims, test22, &SVD_output_dims, test3); + BENCH_END(ref_svdf_s8); + + printf("Start opt SVD implementation\n"); + + BENCH_START(riscv_svdf_s8); + riscv_svdf_s8(&SVD_input_ctx, &SVD_output_ctx_ref, &SVD_svdf_params, &SVD_input_quant_params, + &SVD_output_quant_params, &SVD_input_dims, test1 + SVD_SIZE, &SVD_state_dims, + test2, &SVD_weights_feature_dims, test21, &SVD_weights_time_dims, + test2 + SVD_SIZE, &SVD_bias_dims, test22, &SVD_output_dims, test3 + SVD_SIZE); + BENCH_END(riscv_svdf_s8); + + verify_results_q7(test3, test3 + SVD_SIZE, SVD_SIZE); + +#endif + +#ifdef TEST_NNDataConversion +#define NNDataConversion_SIZE 100 + test1 = new q7_t[NNDataConversion_SIZE * 2]; + test3 = new q7_t[NNDataConversion_SIZE * 2]; + test4 = new q15_t[NNDataConversion_SIZE * 2]; + + for (int i = 0; i < NNDataConversion_SIZE * 2; i++) { + test1[i] = (rand() % 256 - 128); + } + + printf("Start ref q7 to q15 no shift implementation\n"); + + BENCH_START(riscv_q7_to_q15_no_shift_ref); + riscv_q7_to_q15_no_shift_ref(test1, test4, NNDataConversion_SIZE); + BENCH_END(riscv_q7_to_q15_no_shift_ref); + + printf("Start opt q7 to q15 no shift implementation\n"); + + BENCH_START(riscv_q7_to_q15_no_shift); + riscv_q7_to_q15_no_shift(test1, test4 + NNDataConversion_SIZE, NNDataConversion_SIZE); + BENCH_END(riscv_q7_to_q15_no_shift); + + verify_results_q15(test4, test4 + NNDataConversion_SIZE, NNDataConversion_SIZE); + + printf("Start ref q7 to q15 reordered no shift implementation\n"); + + BENCH_START(riscv_q7_to_q15_reordered_no_shift_ref); + riscv_q7_to_q15_reordered_no_shift_ref(test1, test4, NNDataConversion_SIZE); + BENCH_END(riscv_q7_to_q15_reordered_no_shift_ref); + + printf("Start opt q7 to q15 reordered no shift implementation\n"); + + BENCH_START(riscv_q7_to_q15_reordered_no_shift); + riscv_q7_to_q15_reordered_no_shift(test1, test4 + NNDataConversion_SIZE, NNDataConversion_SIZE); + BENCH_END(riscv_q7_to_q15_reordered_no_shift); + + verify_results_q15(test4, test4 + NNDataConversion_SIZE, NNDataConversion_SIZE); + + //Only available for DSP_ON + // printf("Start ref q7 to q15 reordered with offset implementation\n"); + + // BENCH_START(riscv_q7_to_q15_reordered_with_offset_ref); + // riscv_q7_to_q15_reordered_with_offset_ref(test1, test4, NNDataConversion_SIZE,0); + // BENCH_END(riscv_q7_to_q15_reordered_with_offset_ref); + + // printf("Start opt q7 to q15 reordered with offset implementation\n"); + + // BENCH_START(riscv_q7_to_q15_reordered_with_offset); + // riscv_q7_to_q15_reordered_with_offset(test1, test4 + NNDataConversion_SIZE, NNDataConversion_SIZE,0); + // BENCH_END(riscv_q7_to_q15_reordered_with_offset); + + // verify_results_q15(test4, test4 + NNDataConversion_SIZE, NNDataConversion_SIZE); + + // printf("Start ref q7 to q15 offset implementation\n"); + + BENCH_START(riscv_q7_to_q15_with_offset_ref); + riscv_q7_to_q15_with_offset_ref(test1, test4, NNDataConversion_SIZE, 0); + BENCH_END(riscv_q7_to_q15_with_offset_ref); + + printf("Start opt q7 to q15 offset implementation\n"); + + BENCH_START(riscv_q7_to_q15_with_offset); + riscv_q7_to_q15_with_offset(test1, test4 + NNDataConversion_SIZE, NNDataConversion_SIZE, 0); + BENCH_END(riscv_q7_to_q15_with_offset); + + verify_results_q15(test4, test4 + NNDataConversion_SIZE, NNDataConversion_SIZE); + + delete[] test1; + delete[] test3; + delete[] test4; +#endif + +#ifdef TEST_BasicMathforNN +#define BasicMathforNN_SIZE 100 + test1 = new q7_t[BasicMathforNN_SIZE * 2]; + test2 = new q15_t[BasicMathforNN_SIZE * 2]; + test3 = new q7_t[BasicMathforNN_SIZE * 2]; + test4 = new q15_t[BasicMathforNN_SIZE * 2]; + + int8_t *test8 = new int8_t[BasicMathforNN_SIZE * 2]; + int32_t *test9 = new int32_t[BasicMathforNN_SIZE * 2]; + int32_t *test14 = new int32_t[BasicMathforNN_SIZE * 2]; + + q7_t *mult_out_q7 = test3; + q7_t *mult_ref_q7 = test3 + BasicMathforNN_SIZE; + q15_t *mult_out_q15 = test4; + q15_t *mult_ref_q15 = test4 + BasicMathforNN_SIZE; + + for (int i = 0; i < BasicMathforNN_SIZE * 2; i++) { + test1[i] = (rand() % 256 - 128); + test2[i] = (rand() % 65536 - 32768); + test9[i] = (rand() % 65536 - 32768); + test14[i] = (rand() % 1); + } + + printf("start testing q7_t riscv_nn_mult_q7 case 1\n\n"); + // Test q7 + BENCH_START(riscv_nn_mult_q7); + riscv_nn_mult_q7(test1, test1 + BasicMathforNN_SIZE, mult_out_q7, 5, BasicMathforNN_SIZE); + BENCH_END(riscv_nn_mult_q7); + + BENCH_START(riscv_nn_mult_q7_ref); + riscv_nn_mult_q7_ref(test1, test1 + BasicMathforNN_SIZE, mult_ref_q7, 5, BasicMathforNN_SIZE); + BENCH_END(riscv_nn_mult_q7_ref); + + verify_results_q7(mult_out_q7, mult_ref_q7, BasicMathforNN_SIZE); + + printf("start testing q7_t riscv_nn_mult_q7 case 2\n\n"); + + BENCH_START(riscv_nn_mult_q7); + riscv_nn_mult_q7(test1, test1 + BasicMathforNN_SIZE, mult_out_q7, 9, BasicMathforNN_SIZE); + BENCH_END(riscv_nn_mult_q7); + + BENCH_START(riscv_nn_mult_q7_ref); + riscv_nn_mult_q7_ref(test1, test1 + BasicMathforNN_SIZE, mult_ref_q7, 9, BasicMathforNN_SIZE); + BENCH_END(riscv_nn_mult_q7_ref); + + verify_results_q7(mult_out_q7, mult_ref_q7, BasicMathforNN_SIZE); + + // Test q15 + printf("start testing q7_t riscv_nn_mult_q15 case 1\n\n"); + BENCH_START(riscv_nn_mult_q15); + riscv_nn_mult_q15(test2, test2 + BasicMathforNN_SIZE, mult_out_q15, 13, BasicMathforNN_SIZE); + BENCH_END(riscv_nn_mult_q15); + + BENCH_START(riscv_nn_mult_q15_ref); + riscv_nn_mult_q15_ref(test2, test2 + BasicMathforNN_SIZE, mult_ref_q15, 13, BasicMathforNN_SIZE); + BENCH_END(riscv_nn_mult_q15_ref); + + verify_results_q15(mult_out_q15, mult_ref_q15, BasicMathforNN_SIZE); + + printf("start testing q7_t riscv_nn_mult_q15 case 2\n\n"); + BENCH_START(riscv_nn_mult_q15); + riscv_nn_mult_q15(test2, test2 + BasicMathforNN_SIZE, mult_out_q15, 18, BasicMathforNN_SIZE); + BENCH_END(riscv_nn_mult_q15); + + BENCH_START(riscv_nn_mult_q15_ref); + riscv_nn_mult_q15_ref(test2, test2 + BasicMathforNN_SIZE, mult_ref_q15, 18, BasicMathforNN_SIZE); + BENCH_END(riscv_nn_mult_q15_ref); + + verify_results_q15(mult_out_q15, mult_ref_q15, BasicMathforNN_SIZE); + + printf("Start ref q7 to q15 accumulate implementation\n"); + + BENCH_START(riscv_nn_accumulate_q7_to_q15_ref); + riscv_nn_accumulate_q7_to_q15_ref(test4, test1, BasicMathforNN_SIZE); + BENCH_END(riscv_nn_accumulate_q7_to_q15_ref); + + printf("Start opt q7 to q15 accumulate implementation\n"); + + BENCH_START(riscv_nn_accumulate_q7_to_q15); + riscv_nn_accumulate_q7_to_q15(test4 + BasicMathforNN_SIZE, test1, BasicMathforNN_SIZE); + BENCH_END(riscv_nn_accumulate_q7_to_q15); + + verify_results_q15(test4, test4 + BasicMathforNN_SIZE, BasicMathforNN_SIZE); + + q31_t output_opt = 0, output_ref = 0; + + printf("Start ref q7 add implementation\n"); + + BENCH_START(riscv_nn_add_q7_ref); + riscv_nn_add_q7_ref(test1, &output_ref, BasicMathforNN_SIZE); + BENCH_END(riscv_nn_add_q7_ref); + + printf("Start opt q7 add implementation\n"); + + BENCH_START(riscv_nn_add_q7); + riscv_nn_add_q7(test1, &output_opt, BasicMathforNN_SIZE); + BENCH_END(riscv_nn_add_q7); + + verify_results_int32(&output_ref, &output_opt, 1); + + //Only available for RISCV_MATH_MVEI + // printf("Start ref q7 add implementation\n"); + + // BENCH_START(riscv_nn_depthwise_conv_nt_t_padded_s8_ref); + // riscv_nn_depthwise_conv_nt_t_padded_s8_ref(test1, &output_ref, BasicMathforNN_SIZE); + // BENCH_END(riscv_nn_depthwise_conv_nt_t_padded_s8_ref); + + // printf("Start opt q7 add implementation\n"); + + // BENCH_START(riscv_nn_depthwise_conv_nt_t_padded_s8); + // riscv_nn_depthwise_conv_nt_t_padded_s8(test1, &output_opt, BasicMathforNN_SIZE); + // BENCH_END(riscv_nn_depthwise_conv_nt_t_padded_s8); + + // verify_results_int32(&output_ref, &output_opt, 1); + + // printf("Start ref q7 add implementation\n"); + + // BENCH_START(riscv_nn_depthwise_conv_nt_t_s8_ref); + // riscv_nn_depthwise_conv_nt_t_s8_ref(test1, &output_ref, BasicMathforNN_SIZE); + // BENCH_END(riscv_nn_depthwise_conv_nt_t_s8_ref); + + // printf("Start opt q7 add implementation\n"); + + // BENCH_START(riscv_nn_depthwise_conv_nt_t_s8); + // riscv_nn_depthwise_conv_nt_t_s8(test1, &output_opt, BasicMathforNN_SIZE); + // BENCH_END(riscv_nn_depthwise_conv_nt_t_s8); + + // verify_results_int32(&output_ref, &output_opt, 1); + int32_t sum_col_opt = 0, output_opt_s8[4] = { 0 }; + int32_t sum_col_ref = 0, output_ref_s8[4] = { 0 }; + printf("Start ref q7 add implementation\n"); + + BENCH_START(riscv_nn_mat_mul_core_1x_s8_ref); + riscv_nn_mat_mul_core_1x_s8_ref(BasicMathforNN_SIZE, test8, test8 + BasicMathforNN_SIZE, &sum_col_ref, &output_ref_s8[0]); + BENCH_END(riscv_nn_mat_mul_core_1x_s8_ref); + + printf("Start opt q7 add implementation\n"); + + BENCH_START(riscv_nn_mat_mul_core_1x_s8); + riscv_nn_mat_mul_core_1x_s8(BasicMathforNN_SIZE, test8, test8 + BasicMathforNN_SIZE, &sum_col_opt, &output_opt_s8[0]); + BENCH_END(riscv_nn_mat_mul_core_1x_s8); + + verify_results_int32(&sum_col_opt, &sum_col_ref, 1); + verify_results_int32(output_opt_s8, output_ref_s8, 1); + + printf("Start ref q7 add implementation\n"); + + BENCH_START(riscv_nn_mat_mul_core_4x_s8_ref); + riscv_nn_mat_mul_core_4x_s8_ref(BasicMathforNN_SIZE, 0, test8, test8 + BasicMathforNN_SIZE, &sum_col_ref, &output_ref_s8[0]); + BENCH_END(riscv_nn_mat_mul_core_4x_s8_ref); + + printf("Start opt q7 add implementation\n"); + + BENCH_START(riscv_nn_mat_mul_core_4x_s8); + riscv_nn_mat_mul_core_4x_s8(BasicMathforNN_SIZE, 0, test8, test8 + BasicMathforNN_SIZE, &sum_col_opt, &output_opt_s8[0]); + BENCH_END(riscv_nn_mat_mul_core_4x_s8); + + verify_results_int32(&sum_col_opt, &sum_col_ref, 1); + verify_results_int32(output_opt_s8, output_ref_s8, 1); + + printf("Start ref mat_mult implementation\n"); + test1 = new q7_t[500]; + test3 = new q7_t[500]; + BENCH_START(riscv_nn_mat_mult_nt_t_s8_ref); + riscv_nn_mat_mult_nt_t_s8_ref(test1, test1 + 250, test9, test3, test9, test14, 50, 50, 50, 0, 0, -100, 100); + BENCH_END(riscv_nn_mat_mult_nt_t_s8_ref); + + printf("Start opt mat_mult implementation\n"); + + BENCH_START(riscv_nn_mat_mult_nt_t_s8); + riscv_nn_mat_mult_nt_t_s8(test1, test1 + 250, test9, test3 + 250, test9, test14, 50, 50, 50, 0, 0, -100, 100); + BENCH_END(riscv_nn_mat_mult_nt_t_s8); + + verify_results_q7(test3, test3 + BasicMathforNN_SIZE, 250); + + printf("Start ref s8 mat_mult_nt_t implementation\n"); + + BENCH_START(riscv_nn_vec_mat_mult_t_s8_ref); + riscv_nn_vec_mat_mult_t_s8_ref(test1, test1 + 250, test9, test3, 0, 0, 0, 1, 0, 50, 50, -100, 100); + BENCH_END(riscv_nn_vec_mat_mult_t_s8_ref); + + printf("Start opt s8 mat_mult_nt_t implementation\n"); + + BENCH_START(riscv_nn_vec_mat_mult_t_s8); + riscv_nn_vec_mat_mult_t_s8(test1, test1 + 250, test9, test3 + 250, 0, 0, 0, 1, 0, 50, 50, -100, 100); + BENCH_END(riscv_nn_vec_mat_mult_t_s8); + + verify_results_q7(test3, test3 + BasicMathforNN_SIZE, 250); + + delete[] test1; + delete[] test2; + delete[] test3; + delete[] test4; + delete[] test8; + delete[] test9; + delete[] test14; + +#endif + + // Old ones + +#ifdef TEST_NNMULT +#define NNMULT_DIM 100 + test1 = new q7_t[NNMULT_DIM * 2]; + test2 = new q15_t[NNMULT_DIM * 2]; + test3 = new q7_t[NNMULT_DIM * 2]; + test4 = new q15_t[NNMULT_DIM * 2]; + + q7_t *mult_out_q7 = test3; + q7_t *mult_ref_q7 = test3 + NNMULT_DIM; + q15_t *mult_out_q15 = test4; + q15_t *mult_ref_q15 = test4 + NNMULT_DIM; + + for (int i = 0; i < NNMULT_DIM * 2; i++) { + test1[i] = (rand() % 256 - 128); + test2[i] = (rand() % 65536 - 32768); + } + + printf("start testing q7_t riscv_nn_mult_q7 case 1\n\n"); + // Test q7 + BENCH_START(riscv_nn_mult_q7); + riscv_nn_mult_q7(test1, test1 + NNMULT_DIM, mult_out_q7, 5, NNMULT_DIM); + BENCH_END(riscv_nn_mult_q7); + + BENCH_START(riscv_nn_mult_q7_ref); + riscv_nn_mult_q7_ref(test1, test1 + NNMULT_DIM, mult_ref_q7, 5, NNMULT_DIM); + BENCH_END(riscv_nn_mult_q7_ref); + + verify_results_q7(mult_out_q7, mult_ref_q7, NNMULT_DIM); + + printf("start testing q7_t riscv_nn_mult_q7 case 2\n\n"); + + BENCH_START(riscv_nn_mult_q7); + riscv_nn_mult_q7(test1, test1 + NNMULT_DIM, mult_out_q7, 9, NNMULT_DIM); + BENCH_END(riscv_nn_mult_q7); + + BENCH_START(riscv_nn_mult_q7_ref); + riscv_nn_mult_q7_ref(test1, test1 + NNMULT_DIM, mult_ref_q7, 9, NNMULT_DIM); + BENCH_END(riscv_nn_mult_q7_ref); + + verify_results_q7(mult_out_q7, mult_ref_q7, NNMULT_DIM); + + // Test q15 + printf("start testing q7_t riscv_nn_mult_q15 case 1\n\n"); + BENCH_START(riscv_nn_mult_q15); + riscv_nn_mult_q15(test2, test2 + NNMULT_DIM, mult_out_q15, 13, NNMULT_DIM); + BENCH_END(riscv_nn_mult_q15); + + BENCH_START(riscv_nn_mult_q15_ref); + riscv_nn_mult_q15_ref(test2, test2 + NNMULT_DIM, mult_ref_q15, 13, NNMULT_DIM); + BENCH_END(riscv_nn_mult_q15_ref); + + verify_results_q15(mult_out_q15, mult_ref_q15, NNMULT_DIM); + + printf("start testing q7_t riscv_nn_mult_q15 case 2\n\n"); + BENCH_START(riscv_nn_mult_q15); + riscv_nn_mult_q15(test2, test2 + NNMULT_DIM, mult_out_q15, 18, NNMULT_DIM); + BENCH_END(riscv_nn_mult_q15); + + BENCH_START(riscv_nn_mult_q15_ref); + riscv_nn_mult_q15_ref(test2, test2 + NNMULT_DIM, mult_ref_q15, 18, NNMULT_DIM); + BENCH_END(riscv_nn_mult_q15_ref); + + verify_results_q15(mult_out_q15, mult_ref_q15, NNMULT_DIM); + +#endif + +#ifdef TEST_SIGMOID + +#define SIGMOID_DIM 128 + + /* This part tests the running of sigmoid functions */ + + test1 = new q7_t[SIGMOID_DIM]; + test2 = new q15_t[SIGMOID_DIM]; + test3 = new q7_t[SIGMOID_DIM]; + test4 = new q15_t[SIGMOID_DIM]; + + for (int i = 0; i < SIGMOID_DIM; i++) { + test1[i] = (rand() % 256 - 128); + test2[i] = (rand() % 65536 - 32768); + test3[i] = test1[i]; + test4[i] = test2[i]; + } + + riscv_nn_activations_direct_q7(test3, SIGMOID_DIM, 3, RISCV_SIGMOID); + + for (int i = 0; i < SIGMOID_DIM; i++) { + printf("in: %d out: %d\n", test1[i], test3[i]); + } + + printf("start testing q15_t sigmoid\n\n"); + + riscv_nn_activations_direct_q15(test4, SIGMOID_DIM, 3, RISCV_SIGMOID); + + for (int i = 0; i < SIGMOID_DIM; i++) { + printf("in: %d out: %d\n", test2[i], test4[i]); + } + + delete[] test1; + delete[] test2; + delete[] test3; + delete[] test4; + +#endif + +#ifdef TEST_TANH + +#define TANH_DIM 128 + + /* This part tests the running of sigmoid functions */ + + test1 = new q7_t[TANH_DIM]; + test2 = new q15_t[TANH_DIM]; + test3 = new q7_t[TANH_DIM]; + test4 = new q15_t[TANH_DIM]; + + for (int i = 0; i < TANH_DIM; i++) { + test1[i] = (rand() % 256 - 128); + test2[i] = (rand() % 65536 - 32768); + test3[i] = test1[i]; + test4[i] = test2[i]; + } + + riscv_nn_activations_direct_q7(test3, TANH_DIM, 3, RISCV_TANH); + + printf("start testing q7_t tanh\n\n"); + + for (int i = 0; i < TANH_DIM; i++) { + printf("in: %d out: %d\n", test1[i], test3[i]); + } + + printf("start testing q15_t tanh\n\n"); + + riscv_nn_activations_direct_q15(test4, TANH_DIM, 3, RISCV_TANH); + + for (int i = 0; i < TANH_DIM; i++) { + printf("in: %d out: %d\n", test2[i], test4[i]); + } + + delete[] test1; + delete[] test2; + delete[] test3; + delete[] test4; + +#endif + +#ifdef TEST_POOL + +#define POOL_IM_DIM 32 +#define POOL_IM_CH 8 + + test1 = new q7_t[POOL_IM_DIM * POOL_IM_DIM * POOL_IM_CH * 2]; + test2 = new q15_t[POOL_IM_DIM * POOL_IM_CH]; + test3 = new q7_t[POOL_IM_DIM * POOL_IM_DIM * POOL_IM_CH]; + + for (int i = 0; i < POOL_IM_DIM * POOL_IM_DIM * POOL_IM_CH; i++) { + test1[i] = (rand() % 256 - 128); + } + + q7_t *img_in = test1 + POOL_IM_DIM * POOL_IM_DIM * POOL_IM_CH; + q7_t *pool_out_ref = test3; + q7_t *pool_out_opt = test3 + POOL_IM_DIM * POOL_IM_DIM * POOL_IM_CH / 2; + + for (int i = 0; i < POOL_IM_DIM * POOL_IM_DIM * POOL_IM_CH; i++) { + test3[i] = 0; + } + + // copy over the img input + for (int i = 0; i < POOL_IM_DIM * POOL_IM_DIM * POOL_IM_CH; i++) { + img_in[i] = test1[i]; + } + + initialize_results_q7(pool_out_ref, pool_out_opt, POOL_IM_DIM / 2 * POOL_IM_DIM / 2 * POOL_IM_CH); + + printf("Start maxpool reference implementation\n"); + + BENCH_START(riscv_maxpool_q7_HWC_ref); + riscv_maxpool_q7_HWC_ref(img_in, POOL_IM_DIM, POOL_IM_CH, 3, 0, 2, POOL_IM_DIM / 2, (q7_t *)test2, pool_out_ref); + BENCH_END(riscv_maxpool_q7_HWC_ref); + + // copy over the img input + for (int i = 0; i < POOL_IM_DIM * POOL_IM_DIM * POOL_IM_CH; i++) { + img_in[i] = test1[i]; + } + + printf("Start maxpool opt implementation\n"); + + BENCH_START(riscv_maxpool_q7_HWC); + riscv_maxpool_q7_HWC(img_in, POOL_IM_DIM, POOL_IM_CH, 3, 0, 2, POOL_IM_DIM / 2, (q7_t *)test2, pool_out_opt); + BENCH_END(riscv_maxpool_q7_HWC); + + verify_results_q7(pool_out_ref, pool_out_opt, POOL_IM_DIM / 2 * POOL_IM_DIM / 2 * POOL_IM_CH); + + // copy over the img input + for (int i = 0; i < POOL_IM_DIM * POOL_IM_DIM * POOL_IM_CH; i++) { + img_in[i] = test1[i]; + } + + // copy over the img input + for (int i = 0; i < POOL_IM_DIM * POOL_IM_DIM * POOL_IM_CH; i++) { + img_in[i] = test1[i]; + } + + printf("Start avepool ref implementation\n"); + + BENCH_START(riscv_avepool_q7_HWC_ref); + riscv_avepool_q7_HWC_ref(img_in, POOL_IM_DIM, POOL_IM_CH, 3, 0, 2, POOL_IM_DIM / 2, (q7_t *)test2, pool_out_ref); + BENCH_END(riscv_avepool_q7_HWC_ref); + + // copy over the img input + for (int i = 0; i < POOL_IM_DIM * POOL_IM_DIM * POOL_IM_CH; i++) { + img_in[i] = test1[i]; + } + + printf("Start avepool opt implementation\n"); + + BENCH_START(riscv_avepool_q7_HWC); + riscv_avepool_q7_HWC(img_in, POOL_IM_DIM, POOL_IM_CH, 3, 0, 2, POOL_IM_DIM / 2, (q7_t *)test2, pool_out_opt); + BENCH_END(riscv_avepool_q7_HWC); + + // special check here + bool if_ave_pool_match = true; + for (int i = 0; i < POOL_IM_DIM / 2 * POOL_IM_DIM / 2 * POOL_IM_CH; i++) { + // we tolerate at most difference of 1 here because of rounding errors + if (pool_out_ref[i] - pool_out_opt[i] >= 2 || pool_out_opt[i] - pool_out_ref[i] >= 2) { + printf("Output mismatch at %d, expected %d, actual %d\n", i, pool_out_ref[i], pool_out_opt[i]); + if_ave_pool_match = false; + } + } + if (if_ave_pool_match == true) { + printf("Outputs match.\n"); + } + + delete[] test1; + delete[] test2; + delete[] test3; + +#endif + +#ifdef TEST_RELU + +#define RELU_DIM 127 + + test1 = new q7_t[RELU_DIM]; + test2 = new q15_t[RELU_DIM]; + test3 = new q7_t[RELU_DIM]; + test4 = new q15_t[RELU_DIM]; + + for (int i = 0; i < RELU_DIM; i++) { + test1[i] = (rand() % 256 - 128); + test2[i] = (rand() % 65536 - 32768); + test3[i] = test1[i]; + test4[i] = test2[i]; + } + + q7_t *relu_ref_data_q7 = test1; + q7_t *relu_opt_data_q7 = test3; + q15_t *relu_ref_data_q15 = test2; + q15_t *relu_opt_data_q15 = test4; + + printf("Start ref relu q7 implementation\n"); + + BENCH_START(riscv_relu_q7_ref); + riscv_relu_q7_ref(relu_ref_data_q7, RELU_DIM); + BENCH_END(riscv_relu_q7_ref); + + printf("Start opt relu q7 implementation\n"); + + BENCH_START(riscv_relu_q7); + riscv_relu_q7(relu_opt_data_q7, RELU_DIM); + BENCH_END(riscv_relu_q7); + + verify_results_q7(relu_ref_data_q7, relu_opt_data_q7, RELU_DIM); + + printf("Start ref relu q15 implementation\n"); + + BENCH_START(riscv_relu_q15_ref); + riscv_relu_q15_ref(relu_ref_data_q15, RELU_DIM); + BENCH_END(riscv_relu_q15_ref); + + printf("Start opt relu q15 implementation\n"); + + BENCH_START(riscv_relu_q15); + riscv_relu_q15(relu_opt_data_q15, RELU_DIM); + BENCH_END(riscv_relu_q15); + + verify_results_q15(relu_ref_data_q15, relu_opt_data_q15, RELU_DIM); + + delete[] test1; + delete[] test2; + delete[] test3; + delete[] test4; + +#endif + +#ifdef TEST_IP + +#define IP_ROW_DIM 127 +#define IP_COL_DIM 127 + + q7_t ip_weights[IP_ROW_DIM * IP_COL_DIM] = IP2_WEIGHT; + q7_t ip_q7_opt_weights[IP_ROW_DIM * IP_COL_DIM] = IP4_WEIGHT; + q7_t ip_q7_q15_opt_weights[IP_ROW_DIM * IP_COL_DIM] = IP4_q7_q15_WEIGHT; + q15_t ip_q15_weights[IP_ROW_DIM * IP_COL_DIM] = IP2_WEIGHT; + q15_t ip_q15_opt_weights[IP_ROW_DIM * IP_COL_DIM] = IP4_WEIGHT_Q15; + + test1 = new q7_t[IP_COL_DIM + IP_ROW_DIM]; + test2 = new q15_t[IP_COL_DIM]; + test3 = new q7_t[IP_ROW_DIM * 3]; + test4 = new q15_t[IP_COL_DIM + IP_ROW_DIM * 2]; + + for (int i = 0; i < IP_ROW_DIM + IP_COL_DIM; i++) { + test1[i] = rand() % 256 - 100; + } + for (int i = 0; i < IP_ROW_DIM * 3; i++) { + test3[i] = 0; + } + + q7_t *ip_bias_q7 = test1 + IP_COL_DIM; + + q7_t *ip_out_q7_ref = test3; + q7_t *ip_out_q7_opt = test3 + IP_ROW_DIM; + q7_t *ip_out_q7_opt_fast = test3 + 2 * IP_ROW_DIM; + q15_t *ip_out_q15_ref = test4 + IP_COL_DIM; + q15_t *ip_out_q15_opt = test4 + IP_COL_DIM + IP_ROW_DIM; + + initialize_results_q7(ip_out_q7_ref, ip_out_q7_opt, IP_ROW_DIM); + initialize_results_q7(ip_out_q7_ref, ip_out_q7_opt_fast, IP_ROW_DIM); + initialize_results_q7(ip_out_q7_ref, ip_out_q7_opt_fast, IP_ROW_DIM); + + printf("Start ref q7 implementation\n"); + + BENCH_START(riscv_fully_connected_q7_ref); + riscv_fully_connected_q7_ref(test1, ip_weights, IP_COL_DIM, IP_ROW_DIM, 1, 7, ip_bias_q7, ip_out_q7_ref, test2); + BENCH_END(riscv_fully_connected_q7_ref); + + printf("Start q7 implementation\n"); + + BENCH_START(riscv_fully_connected_q7); + riscv_fully_connected_q7(test1, ip_weights, IP_COL_DIM, IP_ROW_DIM, 1, 7, ip_bias_q7, ip_out_q7_opt, test2); + BENCH_END(riscv_fully_connected_q7); + + verify_results_q7(ip_out_q7_ref, ip_out_q7_opt, IP_ROW_DIM); + + printf("Start q7 ref opt implementation\n"); + + BENCH_START(riscv_fully_connected_q7_opt_ref); + riscv_fully_connected_q7_opt_ref(test1, ip_q7_opt_weights, IP_COL_DIM, IP_ROW_DIM, 1, 7, ip_bias_q7, + ip_out_q7_opt_fast, test2); + BENCH_END(riscv_fully_connected_q7_opt_ref); + + verify_results_q7(ip_out_q7_ref, ip_out_q7_opt_fast, IP_ROW_DIM); + + printf("Start q7 opt implementation\n"); + + BENCH_START(riscv_fully_connected_q7_opt); + riscv_fully_connected_q7_opt(test1, ip_q7_opt_weights, IP_COL_DIM, IP_ROW_DIM, 1, 7, ip_bias_q7, ip_out_q7_opt_fast, + test2); + BENCH_END(riscv_fully_connected_q7_opt); + + verify_results_q7(ip_out_q7_ref, ip_out_q7_opt_fast, IP_ROW_DIM); + + for (int i = 0; i < IP_ROW_DIM + IP_COL_DIM; i++) { + test4[i] = (rand() % 65536 - 32768); + } + + initialize_results_q15(ip_out_q15_ref, ip_out_q15_opt, IP_ROW_DIM); + + printf("Start ref q15 implementation\n"); + + BENCH_START(riscv_fully_connected_q15_ref); + riscv_fully_connected_q15_ref(test4, ip_q15_weights, IP_COL_DIM, IP_ROW_DIM, 1, 7, test2, ip_out_q15_ref, NULL); + BENCH_END(riscv_fully_connected_q15_ref); + + printf("Start q15 implementation\n"); + + BENCH_START(riscv_fully_connected_q15); + riscv_fully_connected_q15(test4, ip_q15_weights, IP_COL_DIM, IP_ROW_DIM, 1, 7, test2, ip_out_q15_opt, NULL); + BENCH_END(riscv_fully_connected_q15); + + verify_results_q15(ip_out_q15_ref, ip_out_q15_opt, IP_ROW_DIM); + + printf("Start ref opt q15 implementation\n"); + + BENCH_START(riscv_fully_connected_q15_opt_ref); + riscv_fully_connected_q15_opt_ref(test4, ip_q15_opt_weights, IP_COL_DIM, IP_ROW_DIM, 1, 7, test2, ip_out_q15_opt, + NULL); + BENCH_END(riscv_fully_connected_q15_opt_ref); + + verify_results_q15(ip_out_q15_ref, ip_out_q15_opt, IP_ROW_DIM); + + printf("Start opt q15 implementation\n"); + + BENCH_START(riscv_fully_connected_q15_opt); + riscv_fully_connected_q15_opt(test4, ip_q15_opt_weights, IP_COL_DIM, IP_ROW_DIM, 1, 7, test2, ip_out_q15_opt, NULL); + BENCH_END(riscv_fully_connected_q15_opt); + + verify_results_q15(ip_out_q15_ref, ip_out_q15_opt, IP_ROW_DIM); + + initialize_results_q15(ip_out_q15_ref, ip_out_q15_opt, IP_ROW_DIM); + + printf("Start ref q7_q15 implementation\n"); + + BENCH_START(riscv_fully_connected_mat_q7_vec_q15_ref); + riscv_fully_connected_mat_q7_vec_q15_ref(test4, ip_weights, IP_COL_DIM, IP_ROW_DIM, 1, 7, ip_bias_q7, ip_out_q15_ref, + test2); + BENCH_END(riscv_fully_connected_mat_q7_vec_q15_ref); + + printf("Start q7_q15 implementation\n"); + + BENCH_START(riscv_fully_connected_mat_q7_vec_q15); + riscv_fully_connected_mat_q7_vec_q15(test4, ip_weights, IP_COL_DIM, IP_ROW_DIM, 1, 7, ip_bias_q7, ip_out_q15_opt, + test2); + BENCH_END(riscv_fully_connected_mat_q7_vec_q15); + + verify_results_q15(ip_out_q15_ref, ip_out_q15_opt, IP_ROW_DIM); + + printf("Start ref opt q7_q15 implementation\n"); + + BENCH_START(riscv_fully_connected_mat_q7_vec_q15_opt_ref); + riscv_fully_connected_mat_q7_vec_q15_opt_ref(test4, ip_q7_q15_opt_weights, IP_COL_DIM, IP_ROW_DIM, 1, 7, ip_bias_q7, + ip_out_q15_opt, test2); + BENCH_END(riscv_fully_connected_mat_q7_vec_q15_opt_ref); + + verify_results_q15(ip_out_q15_ref, ip_out_q15_opt, IP_ROW_DIM); + + printf("Start opt q7_q15 implementation\n"); + + BENCH_START(riscv_fully_connected_mat_q7_vec_q15_opt); + riscv_fully_connected_mat_q7_vec_q15_opt(test4, ip_q7_q15_opt_weights, IP_COL_DIM, IP_ROW_DIM, 1, 7, ip_bias_q7, + ip_out_q15_opt, test2); + BENCH_END(riscv_fully_connected_mat_q7_vec_q15_opt); + + verify_results_q15(ip_out_q15_ref, ip_out_q15_opt, IP_ROW_DIM); + + delete[] test1; + delete[] test2; + delete[] test3; + delete[] test4; + +#endif + +#ifdef TEST_NONSQUARE + + /* Use RCONV to differential with square CONV */ + +#define RCONV_IM_DIM_X 10 +#define RCONV_IM_DIM_Y 8 +#define RCONV_IM_CH 4 +#define RCONV_KER_DIM_X 5 +#define RCONV_KER_DIM_Y 3 +#define RCONV_STRIDE_X 1 +#define RCONV_STRIDE_Y 1 +#define RCONV_PADDING_X 2 +#define RCONV_PADDING_Y 1 +#define RCONV_OUT_CH 4 +#define RCONV_OUT_DIM_X 10 +#define RCONV_OUT_DIM_Y 8 + + test1 = new q7_t[RCONV_KER_DIM_Y * RCONV_KER_DIM_X * RCONV_IM_CH * RCONV_OUT_CH + RCONV_OUT_CH]; + test2 = new q15_t[2 * RCONV_KER_DIM_Y * RCONV_KER_DIM_X * RCONV_IM_CH]; + test3 = + new q7_t[RCONV_IM_DIM_Y * RCONV_IM_DIM_X * RCONV_IM_CH + 2 * RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH]; + + for (int i = 0; i < RCONV_KER_DIM_Y * RCONV_KER_DIM_X * RCONV_IM_CH * RCONV_OUT_CH + RCONV_OUT_CH; i++) { + test1[i] = rand() % 256 - 100; + } + + for (int i = 0; + i < RCONV_IM_DIM_Y * RCONV_IM_DIM_X * RCONV_IM_CH + 2 * RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH; i++) { + test3[i] = rand() % 256 - 100; + } + + q7_t *rconv_weight_q7 = test1; + q7_t *rconv_bias_q7 = test1 + RCONV_KER_DIM_Y * RCONV_KER_DIM_X * RCONV_IM_CH * RCONV_OUT_CH; + + q15_t *rconv_buf = test2; + + q7_t *rconv_im_in_q7 = test3; + q7_t *rconv_im_out_ref_q7 = test3 + RCONV_IM_DIM_Y * RCONV_IM_DIM_X * RCONV_IM_CH; + q7_t *rconv_im_out_opt_q7 = + test3 + RCONV_IM_DIM_Y * RCONV_IM_DIM_X * RCONV_IM_CH + RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH; + + initialize_results_q7(rconv_im_out_ref_q7, rconv_im_out_opt_q7, RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH); + + printf("start conv q7 nonsquare ref implementation\n"); + BENCH_START(riscv_convolve_HWC_q7_ref_nonsquare); + riscv_convolve_HWC_q7_ref_nonsquare(rconv_im_in_q7, RCONV_IM_DIM_X, RCONV_IM_DIM_Y, RCONV_IM_CH, rconv_weight_q7, + RCONV_OUT_CH, RCONV_KER_DIM_X, RCONV_KER_DIM_Y, RCONV_PADDING_X, RCONV_PADDING_Y, + RCONV_STRIDE_X, RCONV_STRIDE_Y, rconv_bias_q7, 1, 7, rconv_im_out_ref_q7, + RCONV_OUT_DIM_X, RCONV_OUT_DIM_Y, rconv_buf, NULL); + BENCH_END(riscv_convolve_HWC_q7_ref_nonsquare); + + printf("start conv q7 nonsquare opt implementation\n"); + BENCH_START(riscv_convolve_HWC_q7_fast_nonsquare); + riscv_convolve_HWC_q7_fast_nonsquare(rconv_im_in_q7, RCONV_IM_DIM_X, RCONV_IM_DIM_Y, RCONV_IM_CH, rconv_weight_q7, + RCONV_OUT_CH, RCONV_KER_DIM_X, RCONV_KER_DIM_Y, RCONV_PADDING_X, RCONV_PADDING_Y, + RCONV_STRIDE_X, RCONV_STRIDE_Y, rconv_bias_q7, 1, 7, rconv_im_out_opt_q7, + RCONV_OUT_DIM_X, RCONV_OUT_DIM_Y, rconv_buf, NULL); + BENCH_END(riscv_convolve_HWC_q7_fast_nonsquare); + + verify_results_q7(rconv_im_out_ref_q7, rconv_im_out_opt_q7, RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH); + + initialize_results_q7(rconv_im_out_ref_q7, rconv_im_out_opt_q7, RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH); + + printf("start conv q7 nonsquare ref implementation\n"); + BENCH_START(riscv_convolve_HWC_q7_ref_nonsquare); + riscv_convolve_HWC_q7_ref_nonsquare(rconv_im_in_q7, RCONV_IM_DIM_X, RCONV_IM_DIM_Y, RCONV_IM_CH, rconv_weight_q7, + RCONV_OUT_CH, RCONV_KER_DIM_X, RCONV_KER_DIM_Y, RCONV_PADDING_X, RCONV_PADDING_Y, + RCONV_STRIDE_X, RCONV_STRIDE_Y, rconv_bias_q7, 1, 7, rconv_im_out_ref_q7, + RCONV_OUT_DIM_X, RCONV_OUT_DIM_Y, rconv_buf, NULL); + BENCH_END(riscv_convolve_HWC_q7_ref_nonsquare); + + printf("start conv q7 nonsquare basic implementation\n"); + BENCH_START(riscv_convolve_HWC_q7_basic_nonsquare); + riscv_convolve_HWC_q7_basic_nonsquare(rconv_im_in_q7, RCONV_IM_DIM_X, RCONV_IM_DIM_Y, RCONV_IM_CH, rconv_weight_q7, + RCONV_OUT_CH, RCONV_KER_DIM_X, RCONV_KER_DIM_Y, RCONV_PADDING_X, RCONV_PADDING_Y, + RCONV_STRIDE_X, RCONV_STRIDE_Y, rconv_bias_q7, 1, 7, rconv_im_out_opt_q7, + RCONV_OUT_DIM_X, RCONV_OUT_DIM_Y, rconv_buf, NULL); + BENCH_END(riscv_convolve_HWC_q7_basic_nonsquare); + + verify_results_q7(rconv_im_out_ref_q7, rconv_im_out_opt_q7, RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH); + + initialize_results_q7(rconv_im_out_ref_q7, rconv_im_out_opt_q7, RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH); + + printf("start 1x1 conv q7 nonsquare fast implementation\n"); + BENCH_START(riscv_convolve_HWC_q7_fast_nonsquare); + riscv_convolve_HWC_q7_fast_nonsquare(rconv_im_in_q7, RCONV_IM_DIM_X, RCONV_IM_DIM_Y, RCONV_IM_CH, rconv_weight_q7, + RCONV_OUT_CH, 1, 1, 0, 0, RCONV_STRIDE_X, + RCONV_STRIDE_Y, rconv_bias_q7, 1, 7, rconv_im_out_ref_q7, RCONV_OUT_DIM_X, + RCONV_OUT_DIM_Y, rconv_buf, NULL); + BENCH_END(riscv_convolve_HWC_q7_fast_nonsquare); + + printf("start 1x1 conv q7 nonsquare dedicated function implementation\n"); + BENCH_START(riscv_convolve_1x1_HWC_q7_fast_nonsquare); + riscv_convolve_1x1_HWC_q7_fast_nonsquare(rconv_im_in_q7, RCONV_IM_DIM_X, RCONV_IM_DIM_Y, RCONV_IM_CH, rconv_weight_q7, + RCONV_OUT_CH, 1, 1, 0, 0, RCONV_STRIDE_X, + RCONV_STRIDE_Y, rconv_bias_q7, 1, 7, rconv_im_out_opt_q7, RCONV_OUT_DIM_X, + RCONV_OUT_DIM_Y, rconv_buf, NULL); + BENCH_END(riscv_convolve_1x1_HWC_q7_fast_nonsquare); + + verify_results_q7(rconv_im_out_ref_q7, rconv_im_out_opt_q7, RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH); + + printf("start depthwise separable conv q7 nonsquare ref implementation\n"); + BENCH_START(riscv_depthwise_separable_conv_HWC_q7_ref_nonsquare); + riscv_depthwise_separable_conv_HWC_q7_ref_nonsquare(rconv_im_in_q7, RCONV_IM_DIM_X, RCONV_IM_DIM_Y, RCONV_IM_CH, + rconv_weight_q7, RCONV_OUT_CH, RCONV_KER_DIM_X, RCONV_KER_DIM_Y, + RCONV_PADDING_X, RCONV_PADDING_Y, RCONV_STRIDE_X, RCONV_STRIDE_Y, + rconv_bias_q7, 1, 7, rconv_im_out_ref_q7, RCONV_OUT_DIM_X, + RCONV_OUT_DIM_Y, rconv_buf, NULL); + BENCH_END(riscv_depthwise_separable_conv_HWC_q7_ref_nonsquare); + + printf("start depthwise separable conv q7 nonsquare opt implementation\n"); + BENCH_START(riscv_depthwise_separable_conv_HWC_q7_nonsquare); + riscv_depthwise_separable_conv_HWC_q7_nonsquare(rconv_im_in_q7, RCONV_IM_DIM_X, RCONV_IM_DIM_Y, RCONV_IM_CH, + rconv_weight_q7, RCONV_OUT_CH, RCONV_KER_DIM_X, RCONV_KER_DIM_Y, + RCONV_PADDING_X, RCONV_PADDING_Y, RCONV_STRIDE_X, RCONV_STRIDE_Y, + rconv_bias_q7, 1, 7, rconv_im_out_opt_q7, RCONV_OUT_DIM_X, + RCONV_OUT_DIM_Y, rconv_buf, NULL); + BENCH_END(riscv_depthwise_separable_conv_HWC_q7_nonsquare); + + verify_results_q7(rconv_im_out_ref_q7, rconv_im_out_opt_q7, RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH); + + delete[] test1; + delete[] test2; + delete[] test3; + + test2 = new q15_t[RCONV_KER_DIM_Y * RCONV_KER_DIM_X * RCONV_IM_CH * RCONV_OUT_CH + RCONV_OUT_CH]; // weights + bias + test4 = new q15_t[2 * RCONV_KER_DIM_Y * RCONV_KER_DIM_X * RCONV_IM_CH //buffer + + RCONV_IM_DIM_Y * RCONV_IM_DIM_X * RCONV_IM_CH + 2 * RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH]; // i/o + + for (int i = 0; i < RCONV_KER_DIM_Y * RCONV_KER_DIM_X * RCONV_IM_CH * RCONV_OUT_CH + RCONV_OUT_CH; i++) { + test2[i] = rand() % 256 - 100; + } + + for (int i = 0; + i < 2 * RCONV_KER_DIM_Y * RCONV_KER_DIM_X * RCONV_IM_CH + RCONV_IM_DIM_Y * RCONV_IM_DIM_X * RCONV_IM_CH + 2 * RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH; + i++) { + test4[i] = rand() % 256 - 100; + } + + q15_t *rconv_weight_q15 = test2; + q15_t *rconv_bias_q15 = test2 + RCONV_KER_DIM_Y * RCONV_KER_DIM_X * RCONV_IM_CH * RCONV_OUT_CH; + + rconv_buf = test4; + + q15_t *rconv_im_in_q15 = test4 + 2 * RCONV_KER_DIM_Y * RCONV_KER_DIM_X * RCONV_IM_CH; + q15_t *rconv_im_out_ref_q15 = rconv_im_in_q15 + RCONV_IM_DIM_Y * RCONV_IM_DIM_X * RCONV_IM_CH; + q15_t *rconv_im_out_opt_q15 = rconv_im_out_ref_q15 + RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH; + + initialize_results_q15(rconv_im_out_ref_q15, rconv_im_out_opt_q15, RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH); + + printf("start conv q15 nonsquare ref implementation\n"); + BENCH_START(riscv_convolve_HWC_q15_nonsquare_ref); + riscv_convolve_HWC_q15_nonsquare_ref(rconv_im_in_q15, RCONV_IM_DIM_X, RCONV_IM_DIM_Y, RCONV_IM_CH, rconv_weight_q15, + RCONV_OUT_CH, RCONV_KER_DIM_X, RCONV_KER_DIM_Y, RCONV_PADDING_X, RCONV_PADDING_Y, + RCONV_STRIDE_X, RCONV_STRIDE_Y, rconv_bias_q15, 1, 7, rconv_im_out_ref_q15, + RCONV_OUT_DIM_X, RCONV_OUT_DIM_Y, rconv_buf, NULL); + BENCH_END(riscv_convolve_HWC_q15_nonsquare_ref); + + printf("start conv q5 nonsquare opt implementation\n"); + BENCH_START(riscv_convolve_HWC_q15_fast_nonsquare); + riscv_convolve_HWC_q15_fast_nonsquare(rconv_im_in_q15, RCONV_IM_DIM_X, RCONV_IM_DIM_Y, RCONV_IM_CH, rconv_weight_q15, + RCONV_OUT_CH, RCONV_KER_DIM_X, RCONV_KER_DIM_Y, RCONV_PADDING_X, RCONV_PADDING_Y, + RCONV_STRIDE_X, RCONV_STRIDE_Y, rconv_bias_q15, 1, 7, rconv_im_out_opt_q15, + RCONV_OUT_DIM_X, RCONV_OUT_DIM_Y, rconv_buf, NULL); + BENCH_END(riscv_convolve_HWC_q15_fast_nonsquare); + + verify_results_q15(rconv_im_out_ref_q15, rconv_im_out_opt_q15, RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH); + + delete[] test2; + delete[] test4; +#endif + +#ifdef TEST_CONV + +#define CONV_IM_DIM 16 +#define CONV_IM_CH 16 +#define CONV_KER_DIM 5 +#define CONV_OUT_CH 16 +#define CONV_OUT_DIM 16 + + test1 = new q7_t[CONV_KER_DIM * CONV_KER_DIM * CONV_IM_CH * CONV_OUT_CH + CONV_OUT_CH]; + test2 = + new q15_t[CONV_KER_DIM * CONV_KER_DIM * CONV_IM_CH * CONV_OUT_CH + + 2 * CONV_KER_DIM * CONV_KER_DIM * CONV_IM_CH * CONV_OUT_CH + CONV_OUT_CH]; + test3 = new q7_t[CONV_IM_DIM * CONV_IM_DIM * CONV_IM_CH + 2 * CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH]; + test4 = new q15_t[CONV_IM_DIM * CONV_IM_DIM * CONV_IM_CH + 2 * CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH]; + + for (int i = 0; i < CONV_KER_DIM * CONV_KER_DIM * CONV_IM_CH * CONV_OUT_CH + CONV_OUT_CH; i++) { + test1[i] = rand() % 256 - 100; + } + + for (int i = 0; + i < + CONV_KER_DIM * CONV_KER_DIM * CONV_IM_CH * CONV_OUT_CH + + 2 * CONV_KER_DIM * CONV_KER_DIM * CONV_IM_CH * CONV_OUT_CH + CONV_OUT_CH; + i++) { + test2[i] = (rand() % 65536 - 32768); + } + + for (int i = 0; i < CONV_IM_DIM * CONV_IM_DIM * CONV_IM_CH + 2 * CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH; i++) { + test3[i] = rand() % 256 - 100; + } + + for (int i = 0; i < CONV_IM_DIM * CONV_IM_DIM * CONV_IM_CH + 2 * CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH; i++) { + test4[i] = (rand() % 65536 - 32768); + } + + q7_t *conv_weight_q7 = test1; + q7_t *conv_bias_q7 = test1 + CONV_KER_DIM * CONV_KER_DIM * CONV_IM_CH * CONV_OUT_CH; + + q15_t *conv_weight_q15 = test2; + q15_t *conv_buf = test2 + CONV_KER_DIM * CONV_KER_DIM * CONV_IM_CH * CONV_OUT_CH; + q15_t *conv_bias_q15 = + test2 + CONV_KER_DIM * CONV_KER_DIM * CONV_IM_CH * CONV_OUT_CH + + 2 * CONV_KER_DIM * CONV_KER_DIM * CONV_IM_CH * CONV_OUT_CH; + + q7_t *conv_im_in_q7 = test3; + q7_t *conv_im_out_ref_q7 = test3 + CONV_IM_DIM * CONV_IM_DIM * CONV_IM_CH; + q7_t *conv_im_out_opt_q7 = + test3 + CONV_IM_DIM * CONV_IM_DIM * CONV_IM_CH + CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH; + + q15_t *conv_im_in_q15 = test4; + q15_t *conv_im_out_ref_q15 = test4 + CONV_IM_DIM * CONV_IM_DIM * CONV_IM_CH; + q15_t *conv_im_out_opt_q15 = + test4 + CONV_IM_DIM * CONV_IM_DIM * CONV_IM_CH + CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH; + + initialize_results_q7(conv_im_out_ref_q7, conv_im_out_opt_q7, CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH); + + printf("start q7 ref implementation\n"); + + BENCH_START(riscv_convolve_HWC_q7_ref); + riscv_convolve_HWC_q7_ref(conv_im_in_q7, CONV_IM_DIM, CONV_IM_CH, conv_weight_q7, + CONV_OUT_CH, CONV_KER_DIM, 2, 1, conv_bias_q7, 1, 7, conv_im_out_ref_q7, + CONV_OUT_DIM, conv_buf, NULL); + BENCH_END(riscv_convolve_HWC_q7_ref); + + printf("start q7 basic implementation\n"); + + BENCH_START(riscv_convolve_HWC_q7_basic); + riscv_convolve_HWC_q7_basic(conv_im_in_q7, CONV_IM_DIM, CONV_IM_CH, conv_weight_q7, + CONV_OUT_CH, CONV_KER_DIM, 2, 1, conv_bias_q7, 1, 7, conv_im_out_opt_q7, + CONV_OUT_DIM, conv_buf, NULL); + BENCH_END(riscv_convolve_HWC_q7_basic); + + verify_results_q7(conv_im_out_ref_q7, conv_im_out_opt_q7, CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH); + + printf("start q7 fast implementation\n"); + + BENCH_START(riscv_convolve_HWC_q7_fast); + riscv_convolve_HWC_q7_fast(conv_im_in_q7, CONV_IM_DIM, CONV_IM_CH, conv_weight_q7, + CONV_OUT_CH, CONV_KER_DIM, 2, 1, conv_bias_q7, 1, 7, conv_im_out_opt_q7, + CONV_OUT_DIM, conv_buf, NULL); + BENCH_END(riscv_convolve_HWC_q7_fast); + + verify_results_q7(conv_im_out_ref_q7, conv_im_out_opt_q7, CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH); + + // testing with RGB + printf("start q7 ref implementation for RGB\n"); + + BENCH_START(riscv_convolve_HWC_q7_ref); + riscv_convolve_HWC_q7_ref(conv_im_in_q7, CONV_IM_DIM, 3, conv_weight_q7, + CONV_OUT_CH, CONV_KER_DIM, 2, 1, conv_bias_q7, 1, 7, conv_im_out_ref_q7, + CONV_OUT_DIM, conv_buf, NULL); + BENCH_END(riscv_convolve_HWC_q7_ref); + + printf("start q7 basic implementation for RGB\n"); + + BENCH_START(riscv_convolve_HWC_q7_basic); + riscv_convolve_HWC_q7_basic(conv_im_in_q7, CONV_IM_DIM, 3, conv_weight_q7, + CONV_OUT_CH, CONV_KER_DIM, 2, 1, conv_bias_q7, 1, 7, conv_im_out_opt_q7, + CONV_OUT_DIM, conv_buf, NULL); + BENCH_END(riscv_convolve_HWC_q7_basic); + + verify_results_q7(conv_im_out_ref_q7, conv_im_out_opt_q7, CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH); + + printf("start q7 RGB implementation for RGB\n"); + + BENCH_START(riscv_convolve_HWC_q7_RGB); + riscv_convolve_HWC_q7_RGB(conv_im_in_q7, CONV_IM_DIM, 3, conv_weight_q7, + CONV_OUT_CH, CONV_KER_DIM, 2, 1, conv_bias_q7, 1, 7, conv_im_out_opt_q7, + CONV_OUT_DIM, conv_buf, NULL); + BENCH_END(riscv_convolve_HWC_q7_RGB); + + verify_results_q7(conv_im_out_ref_q7, conv_im_out_opt_q7, CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH); + + // testing q15 + initialize_results_q15(conv_im_out_ref_q15, conv_im_out_opt_q15, CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH); + + printf("start q15 ref implementation\n"); + + BENCH_START(riscv_convolve_HWC_q15_ref); + riscv_convolve_HWC_q15_ref(conv_im_in_q15, CONV_IM_DIM, CONV_IM_CH, conv_weight_q15, + CONV_OUT_CH, CONV_KER_DIM, 2, 1, conv_bias_q15, 0, 15, conv_im_out_ref_q15, + CONV_OUT_DIM, conv_buf, NULL); + BENCH_END(riscv_convolve_HWC_q15_ref); + + printf("start q15 basic implementation\n"); + + BENCH_START(riscv_convolve_HWC_q15_basic); + riscv_convolve_HWC_q15_basic(conv_im_in_q15, CONV_IM_DIM, CONV_IM_CH, conv_weight_q15, + CONV_OUT_CH, CONV_KER_DIM, 2, 1, conv_bias_q15, 0, 15, conv_im_out_opt_q15, + CONV_OUT_DIM, conv_buf, NULL); + BENCH_END(riscv_convolve_HWC_q15_basic); + + verify_results_q15(conv_im_out_ref_q15, conv_im_out_opt_q15, CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH); + + printf("start q15 fast implementation\n"); + + BENCH_START(riscv_convolve_HWC_q15_fast); + riscv_convolve_HWC_q15_fast(conv_im_in_q15, CONV_IM_DIM, CONV_IM_CH, conv_weight_q15, + CONV_OUT_CH, CONV_KER_DIM, 2, 1, conv_bias_q15, 0, 15, conv_im_out_opt_q15, + CONV_OUT_DIM, conv_buf, NULL); + BENCH_END(riscv_convolve_HWC_q15_fast); + + verify_results_q15(conv_im_out_ref_q15, conv_im_out_opt_q15, CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH); + + // depthwise separable conv + initialize_results_q7(conv_im_out_ref_q7, conv_im_out_opt_q7, CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH); + + printf("start q7 depthwise_separable_conv ref implementation\n"); + + BENCH_START(riscv_depthwise_separable_conv_HWC_q7_ref); + riscv_depthwise_separable_conv_HWC_q7_ref(conv_im_in_q7, CONV_IM_DIM, CONV_IM_CH, conv_weight_q7, + CONV_OUT_CH, CONV_KER_DIM, 2, 1, conv_bias_q7, 1, 7, conv_im_out_ref_q7, + CONV_OUT_DIM, conv_buf, NULL); + BENCH_END(riscv_depthwise_separable_conv_HWC_q7_ref); + + printf("start q7 depthwise_separable_conv implementation\n"); + + BENCH_START(riscv_depthwise_separable_conv_HWC_q7); + riscv_depthwise_separable_conv_HWC_q7(conv_im_in_q7, CONV_IM_DIM, CONV_IM_CH, conv_weight_q7, + CONV_OUT_CH, CONV_KER_DIM, 2, 1, conv_bias_q7, 1, 7, conv_im_out_opt_q7, + CONV_OUT_DIM, conv_buf, NULL); + BENCH_END(riscv_depthwise_separable_conv_HWC_q7); + + verify_results_q7(conv_im_out_ref_q7, conv_im_out_opt_q7, CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH); + + delete[] test1; + delete[] test2; + delete[] test3; + delete[] test4; + +#endif + + test_pass = true; + test_index = 0; + while (test_flags[test_index] != -1) { + if (test_flags[test_index]) { + test_pass = false; + } + test_index++; + } + if (test_pass) { + printf("All tests passed\n"); + } else { + printf("Test failed\n"); + } + BENCH_FINISH; + if (test_pass) { + return 0; + } else { + return 1; + } +} diff --git a/examples/nn/nnTest/riscv_nnexamples_nn_test.h b/examples/nn/nnTest/riscv_nnexamples_nn_test.h new file mode 100644 index 00000000..530befbe --- /dev/null +++ b/examples/nn/nnTest/riscv_nnexamples_nn_test.h @@ -0,0 +1,128 @@ +#ifndef _MAIN_H_ +#define _MAIN_H_ + +#include +#include +#include + +#include "riscv_math.h" + +#include "riscv_nnfunctions.h" +#include "ref_functions.h" + +extern int test_index; +extern q7_t test_flags[100]; + +void initialize_results_q7(q7_t * ref, q7_t * opt, int length) +{ + riscv_fill_q7(0, ref, length); + riscv_fill_q7(37, opt, length); +} + +void initialize_results_q15(q15_t * ref, q15_t * opt, int length) +{ + riscv_fill_q15(0, ref, length); + riscv_fill_q15(0x5F5, opt, length); +} + +void verify_results_q7(q7_t * ref, q7_t * opt, int length) +{ + + bool if_match = true; + + for (int i = 0; i < length; i++) + { + if (abs(ref[i] - opt[i])>1) + { + printf("Q7 Output mismatch at %d, expected %d, actual %d\r\n", i, ref[i], opt[i]); + + if_match = false; + } + } + + if (if_match == true) + { + printf("Q7 Outputs match.\r\n\r\n"); + test_flags[test_index++] = 0; + } else { + test_flags[test_index++] = 1; + } + +} + +void verify_results_q15(q15_t * ref, q15_t * opt, int length) +{ + + bool if_match = true; + + for (int i = 0; i < length; i++) + { + if (ref[i] != opt[i]) + { + printf("Q15 Output mismatch at %d, expected %d, actual %d\r\n", i, ref[i], opt[i]); + + if_match = false; + } + } + + if (if_match == true) + { + printf("Q15 Outputs match.\r\n\r\n"); + test_flags[test_index++] = 0; + } else { + test_flags[test_index++] = 1; + } + +} + +void verify_results_int32(int32_t * ref, int32_t * opt, int length) +{ + + bool if_match = true; + + for (int i = 0; i < length; i++) + { + if (ref[i] != opt[i]) + { + printf("Q7 Output mismatch at %d, expected %d, actual %d\r\n", i, ref[i], opt[i]); + + if_match = false; + } + } + + if (if_match == true) + { + printf("int32 Outputs match.\r\n\r\n"); + test_flags[test_index++] = 0; + } else { + test_flags[test_index++] = 1; + } + +} + +void verify_results_u8(uint8_t * ref, uint8_t * opt, int length) +{ + + bool if_match = true; + + for (int i = 0; i < length; i++) + { + if (ref[i] != opt[i]) + { + printf("uint8_t Output mismatch at %d, expected %d, actual %d\r\n", i, ref[i], opt[i]); + + if_match = false; + } + } + + if (if_match == true) + { + printf("uint8_t Outputs match.\r\n\r\n"); + test_flags[test_index++] = 0; + } else { + test_flags[test_index++] = 1; + } + +} + +#endif