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[feat][bl602_driver] update bl602 driver

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This commit is contained in:
jzlv 2021-08-25 19:15:03 +08:00
parent d8a91f4313
commit 7105b56150
25 changed files with 651 additions and 65 deletions
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3
drivers/bl602_driver/CMakeLists.txt
View file

@ -50,6 +50,9 @@ list(APPEND ADD_REQUIREMENTS common)
############ Add global compile option ################
#add components denpend on this component
if("${SUPPORT_ROMAPI}" STREQUAL "y")
list(APPEND ADD_DEFINITIONS -DBFLB_USE_ROM_DRIVER)
endif()
list(APPEND ADD_DEFINITIONS -DARCH_RISCV)
#######################################################

3
drivers/bl602_driver/cpu_flags.cmake
View file

@ -6,4 +6,5 @@ SET(MABI "ilp32f")
list(APPEND GLOBAL_C_FLAGS -march=${MARCH} -mabi=${MABI})
list(APPEND GLOBAL_LD_FLAGS -march=${MARCH} -mabi=${MABI})
SET(LINKER_SCRIPT ${CMAKE_CURRENT_LIST_DIR}/bl602_flash.ld)
SET(LINKER_SCRIPT ${CMAKE_CURRENT_LIST_DIR}/bl602_flash.ld)
SET(BOOT2_LINKER_SCRIPT ${CMAKE_CURRENT_LIST_DIR}/blsp_boot2_iap_flash.ld)

2
drivers/bl602_driver/hal_drv/default_config/uart_config.h
View file

@ -7,6 +7,6 @@
#define UART_RX_DEGLITCH_ENABLE (0)
#define UART_MSB_FIRST_ENABLE (0)
#define UART_FIFO_MAX_LEN 128
#define UART_FIFO_MAX_LEN 32
#define UART_DEFAULT_RTO_TIMEOUT 255
#endif

43
drivers/bl602_driver/hal_drv/inc/hal_clock.h
View file

@ -26,39 +26,33 @@
#include "drv_device.h"
#include "bl602_config.h"
#define EXTERNAL_XTAL_NONE 0
/*XTAL_TYPE*/
#define XTAL_NONE 0
#define EXTERNAL_XTAL_24M 1
#define EXTERNAL_XTAL_32M 2
#define EXTERNAL_XTAL_38P4M 3
#define EXTERNAL_XTAL_40M 4
#define EXTERNAL_XTAL_26M 5
#define INTERAL_XTAL_RC32M 6
#define INTERNAL_RC_32M 6
#define ROOT_CLOCK_SOURCE_RC_32K 0
#define ROOT_CLOCK_SOURCE_XTAL_32K 1
#define ROOT_CLOCK_SOURCE_RC_32M 2
/*CLOCK_32K_XTAL*/
#define EXTERNAL_XTAL_32K 1
#define INTERNAL_RC_32K 0
#define ROOT_CLOCK_SOURCE_XTAL_32M 3
#define ROOT_CLOCK_SOURCE_PLL_48M 4
#define ROOT_CLOCK_SOURCE_PLL_120M 5
#define ROOT_CLOCK_SOURCE_PLL_160M 6
#define ROOT_CLOCK_SOURCE_PLL_192M 7
#define ROOT_CLOCK_SOURCE_XCLK ROOT_CLOCK_SOURCE_XTAL_32M
#define ROOT_CLOCK_SOURCE_FCLK 8
#define ROOT_CLOCK_SOURCE_HCLK 8
#define ROOT_CLOCK_SOURCE_BCLK 9
#define ROOT_CLOCK_SOURCE_AUPLL 9
#define OUTPUT_REF_CLOCK_SOURCE_NONE 0
#define OUTPUT_REF_CLOCK_SOURCE_I2S 1
#if (BSP_ROOT_CLOCK_SOURCE > 2) && (BSP_ROOT_CLOCK_SOURCE < 8)
#define CLOCK_XTAL EXTERNAL_XTAL_40M
/*BSP_ROOT_CLOCK_SOURCE*/
#if (XTAL_TYPE == INTERNAL_RC_32M) || (XTAL_TYPE == XTAL_NONE)
#define ROOT_CLOCK_SOURCE_XCLK 0
#else
#define CLOCK_XTAL INTERAL_XTAL_RC32M
#define ROOT_CLOCK_SOURCE_XCLK 1
#endif
#define ROOT_CLOCK_SOURCE_PLL_48M 2
#define ROOT_CLOCK_SOURCE_PLL_120M 3
#define ROOT_CLOCK_SOURCE_PLL_160M 4
#define ROOT_CLOCK_SOURCE_PLL_192M 5
/*BSP_XXX_CLOCK_SOURCE*/
#define ROOT_CLOCK_SOURCE_FCLK 6
#define ROOT_CLOCK_SOURCE_BCLK 7
enum system_clock_type {
SYSTEM_CLOCK_ROOT_CLOCK = 0,
@ -75,6 +69,7 @@ enum peripheral_clock_type {
};
void system_clock_init(void);
void system_mtimer_clock_init(void);
void peripheral_clock_init(void);
uint32_t system_clock_get(enum system_clock_type type);
uint32_t peripheral_clock_get(enum peripheral_clock_type type);

41
drivers/bl602_driver/hal_drv/inc/hal_flash.h Normal file
View file

@ -0,0 +1,41 @@
/**
* @file hal_flash.h
* @brief
*
* Copyright 2019-2030 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#ifndef __HAL_FLASH__H__
#define __HAL_FLASH__H__
#include "drv_device.h"
#define BL_FLASH_XIP_BASE BL602_FLASH_XIP_BASE
#define FLASH_NOT_DETECT 0x10
BL_Err_Type flash_init(void);
BL_Err_Type flash_read_jedec_id(uint8_t *data);
BL_Err_Type flash_read_via_xip(uint32_t addr, uint8_t *data, uint32_t len);
BL_Err_Type flash_read(uint32_t addr, uint8_t *data, uint32_t len);
BL_Err_Type flash_write(uint32_t addr, uint8_t *data, uint32_t len);
BL_Err_Type flash_erase(uint32_t startaddr, uint32_t len);
BL_Err_Type flash_set_cache(uint8_t cont_read, uint8_t cache_enable, uint8_t cache_way_disable, uint32_t flash_offset);
BL_Err_Type flash_get_cfg(uint8_t **cfg_addr,uint32_t *len);
#endif

8
drivers/bl602_driver/hal_drv/inc/hal_uart.h
View file

@ -81,9 +81,10 @@ typedef enum {
* This enumeration defines the UART stop bits.
*/
typedef enum {
UART_STOP_ONE = 0, /*!< One stop bit */
UART_STOP_ONE_D_FIVE = 0, /*!< 1.5 stop bit */
UART_STOP_TWO = 1 /*!< Two stop bits */
UART_STOP_ZERO_D_FIVE = 0, /*!< One stop bit */
UART_STOP_ONE = 1, /*!< One stop bit */
UART_STOP_ONE_D_FIVE = 2, /*!< 1.5 stop bit */
UART_STOP_TWO = 3 /*!< Two stop bits */
} uart_stopbits_t;
/*!
@ -147,6 +148,7 @@ typedef struct uart_device {
void *rx_dma;
} uart_device_t;
#define UART_DEV(dev) ((uart_device_t *)dev)
int uart_register(enum uart_index_type index, const char *name);
#endif

45
drivers/bl602_driver/hal_drv/src/hal_clock.c
View file

@ -9,11 +9,29 @@ static uint32_t mtimer_get_clk_src_div(void)
void system_clock_init(void)
{
/*select root clock*/
GLB_Set_System_CLK(CLOCK_XTAL, BSP_ROOT_CLOCK_SOURCE - 2);
GLB_Set_System_CLK(XTAL_TYPE, BSP_ROOT_CLOCK_SOURCE);
/*set fclk/hclk and bclk clock*/
GLB_Set_System_CLK_Div(BSP_HCLK_DIV, BSP_BCLK_DIV);
GLB_Set_System_CLK_Div(BSP_FCLK_DIV, BSP_BCLK_DIV);
GLB_Set_MTimer_CLK(1, GLB_MTIMER_CLK_BCLK, mtimer_get_clk_src_div());
#if 1
HBN_32K_Sel(HBN_32K_RC);
HBN_Power_Off_Xtal_32K();
#else
HBN_32K_Sel(HBN_32K_XTAL);
HBN_Power_On_Xtal_32K();
#endif
if ((XTAL_TYPE == INTERNAL_RC_32M) || (XTAL_TYPE == XTAL_NONE)) {
HBN_Set_XCLK_CLK_Sel(HBN_XCLK_CLK_RC32M);
} else {
HBN_Set_XCLK_CLK_Sel(HBN_XCLK_CLK_XTAL);
}
}
void system_mtimer_clock_init(void)
{
GLB_Set_MTimer_CLK(1, GLB_MTIMER_CLK_BCLK, mtimer_get_clk_src_div());
}
void peripheral_clock_init(void)
{
#if defined(BSP_USING_UART0) || defined(BSP_USING_UART1)
@ -67,16 +85,33 @@ uint32_t system_clock_get(enum system_clock_type type)
{
switch (type) {
case SYSTEM_CLOCK_ROOT_CLOCK:
return SystemCoreClockGet();
return SystemCoreClockGet() * (GLB_Get_HCLK_Div() + 1);
case SYSTEM_CLOCK_FCLK:
return (SystemCoreClockGet() / (GLB_Get_HCLK_Div() + 1));
return SystemCoreClockGet();
case SYSTEM_CLOCK_BCLK:
return (SystemCoreClockGet() / ((GLB_Get_HCLK_Div() + 1) * (GLB_Get_BCLK_Div() + 1)));
case SYSTEM_CLOCK_XCLK:
return 32000000;
switch (XTAL_TYPE) {
case XTAL_NONE:
return 32000000;
case EXTERNAL_XTAL_24M:
return 24000000;
case EXTERNAL_XTAL_32M:
return 32000000;
case EXTERNAL_XTAL_38P4M:
return 38400000;
case EXTERNAL_XTAL_40M:
return 40000000;
case EXTERNAL_XTAL_26M:
return 26000000;
case INTERNAL_RC_32M:
return 32000000;
default:
break;
}
default:
break;

7
drivers/bl602_driver/hal_drv/src/hal_dma.c
View file

@ -248,7 +248,6 @@ int dma_allocate_register(const char *name)
// dev->write = dma_write;
// dev->read = dma_read;
dev->status = DEVICE_UNREGISTER;
dev->type = DEVICE_CLASS_DMA;
dev->handle = NULL;
@ -321,10 +320,10 @@ int dma_reload(struct device *dev, uint32_t src_addr, uint32_t dst_addr, uint32_
}
if (dma_device->lli_cfg) {
mmheap_free(dma_device->lli_cfg);
dma_device->lli_cfg = (dma_lli_ctrl_t *)mmheap_alloc(sizeof(dma_lli_ctrl_t) * malloc_count);
free(dma_device->lli_cfg);
dma_device->lli_cfg = (dma_lli_ctrl_t *)malloc(sizeof(dma_lli_ctrl_t) * malloc_count);
} else {
dma_device->lli_cfg = (dma_lli_ctrl_t *)mmheap_alloc(sizeof(dma_lli_ctrl_t) * malloc_count);
dma_device->lli_cfg = (dma_lli_ctrl_t *)malloc(sizeof(dma_lli_ctrl_t) * malloc_count);
}
if (dma_device->lli_cfg) {

291
drivers/bl602_driver/hal_drv/src/hal_flash.c Normal file
View file

@ -0,0 +1,291 @@
/**
* @file hal_flash.c
* @brief
*
* Copyright (c) 2021 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#include "bl602_glb.h"
#include "bl602_xip_sflash.h"
#include "bl602_xip_sflash_ext.h"
#include "bl602_sf_cfg.h"
#include "bl602_sf_cfg_ext.h"
#include "hal_flash.h"
static SPI_Flash_Cfg_Type g_flash_cfg;
/**
* @brief flash_get_cfg
*
* @return BL_Err_Type
*/
BL_Err_Type flash_get_cfg(uint8_t **cfg_addr,uint32_t *len)
{
*cfg_addr = (uint8_t *)&g_flash_cfg;
*len = sizeof(SPI_Flash_Cfg_Type);
return SUCCESS;
}
/**
* @brief flash_set_qspi_enable
*
* @return BL_Err_Type
*/
BL_Err_Type ATTR_TCM_SECTION flash_set_qspi_enable(SPI_Flash_Cfg_Type *p_flash_cfg)
{
if ((p_flash_cfg->ioMode & 0x0f) == SF_CTRL_QO_MODE || (p_flash_cfg->ioMode & 0x0f) == SF_CTRL_QIO_MODE) {
SFlash_Qspi_Enable(p_flash_cfg);
}
return SUCCESS;
}
/**
* @brief flash_set_l1c_wrap
*
* @return BL_Err_Type
*/
BL_Err_Type ATTR_TCM_SECTION flash_set_l1c_wrap(SPI_Flash_Cfg_Type *p_flash_cfg)
{
if (((p_flash_cfg->ioMode >> 4) & 0x01) == 1) {
L1C_Set_Wrap(DISABLE);
} else {
L1C_Set_Wrap(ENABLE);
if((p_flash_cfg->ioMode&0x0f)==SF_CTRL_QO_MODE || (p_flash_cfg->ioMode&0x0f)==SF_CTRL_QIO_MODE) {
SFlash_SetBurstWrap(p_flash_cfg);
}
}
return SUCCESS;
}
/**
* @brief flash_config_init
*
* @return BL_Err_Type
*/
static BL_Err_Type ATTR_TCM_SECTION flash_config_init(SPI_Flash_Cfg_Type *p_flash_cfg, uint8_t *jedec_id)
{
BL_Err_Type ret = ERROR;
uint8_t isAesEnable = 0;
uint32_t jid = 0;
uint32_t offset = 0;
__disable_irq();
XIP_SFlash_Opt_Enter(&isAesEnable);
XIP_SFlash_State_Save(p_flash_cfg, &offset);
SFlash_GetJedecId(p_flash_cfg, (uint8_t *)&jid);
arch_memcpy(jedec_id, (uint8_t *)&jid, 3);
jid &= 0xFFFFFF;
ret = SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(jid, p_flash_cfg);
if (ret == SUCCESS) {
p_flash_cfg->mid = (jid&0xff);
}
/* Set flash controler from p_flash_cfg */
flash_set_qspi_enable(p_flash_cfg);
flash_set_l1c_wrap(p_flash_cfg);
XIP_SFlash_State_Restore_Ext(p_flash_cfg, offset);
XIP_SFlash_Opt_Exit(isAesEnable);
__enable_irq();
return ret;
}
/**
* @brief multi flash adapter
*
* @return BL_Err_Type
*/
BL_Err_Type ATTR_TCM_SECTION flash_init(void)
{
BL_Err_Type ret = ERROR;
uint8_t clkDelay = 1;
uint8_t clkInvert = 1;
uint32_t jedec_id = 0;
__disable_irq();
SFlash_Cache_Flush();
SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(0, &g_flash_cfg);
SFlash_Cache_Flush();
__enable_irq();
if (g_flash_cfg.mid != 0xff) {
return SUCCESS;
}
clkDelay = g_flash_cfg.clkDelay;
clkInvert = g_flash_cfg.clkInvert;
g_flash_cfg.ioMode = g_flash_cfg.ioMode & 0x0f;
ret = flash_config_init(&g_flash_cfg, (uint8_t *)&jedec_id);
MSG("flash ID = %08x\r\n", jedec_id);
bflb_platform_dump((uint8_t *)&g_flash_cfg, sizeof(g_flash_cfg));
if (ret != SUCCESS) {
MSG("flash config init fail!\r\n");
}
g_flash_cfg.clkDelay = clkDelay;
g_flash_cfg.clkInvert = clkInvert;
return ret;
}
/**
* @brief read jedec id
*
* @param data
* @return BL_Err_Type
*/
BL_Err_Type ATTR_TCM_SECTION flash_read_jedec_id(uint8_t *data)
{
uint8_t isAesEnable = 0;
uint32_t jid = 0;
__disable_irq();
XIP_SFlash_Opt_Enter(&isAesEnable);
XIP_SFlash_GetJedecId_Need_Lock_Ext(&g_flash_cfg /*, g_flash_cfg.ioMode & 0x0f*/, (uint8_t *)&jid);
XIP_SFlash_Opt_Exit(isAesEnable);
__enable_irq();
jid &= 0xFFFFFF;
arch_memcpy(data, (void *)&jid, 4);
return SUCCESS;
}
/**
* @brief read flash data via xip
*
* @param addr
* @param data
* @param len
* @return BL_Err_Type
*/
BL_Err_Type ATTR_TCM_SECTION flash_read_via_xip(uint32_t addr, uint8_t *data, uint32_t len)
{
__disable_irq();
SFlash_Cache_Flush();
XIP_SFlash_Read_Via_Cache_Need_Lock(addr, data, len);
SFlash_Cache_Flush();
__enable_irq();
return SUCCESS;
}
/**
* @brief flash read data
*
* @param addr
* @param data
* @param len
* @return BL_Err_Type
*/
BL_Err_Type ATTR_TCM_SECTION flash_read(uint32_t addr, uint8_t *data, uint32_t len)
{
BL_Err_Type ret = ERROR;
uint8_t isAesEnable = 0;
XIP_SFlash_Opt_Enter(&isAesEnable);
ret = XIP_SFlash_Read_With_Lock_Ext(&g_flash_cfg, addr, data, len);
XIP_SFlash_Opt_Exit(isAesEnable);
return ret;
}
/**
* @brief flash write data
*
* @param addr
* @param data
* @param len
* @return BL_Err_Type
*/
BL_Err_Type ATTR_TCM_SECTION flash_write(uint32_t addr, uint8_t *data, uint32_t len)
{
BL_Err_Type ret = ERROR;
uint8_t isAesEnable = 0;
XIP_SFlash_Opt_Enter(&isAesEnable);
ret = XIP_SFlash_Write_With_Lock_Ext(&g_flash_cfg, addr, data, len);
XIP_SFlash_Opt_Exit(isAesEnable);
return ret;
}
/**
* @brief flash erase
*
* @param startaddr
* @param endaddr
* @return BL_Err_Type
*/
BL_Err_Type ATTR_TCM_SECTION flash_erase(uint32_t startaddr, uint32_t len)
{
BL_Err_Type ret = ERROR;
uint8_t isAesEnable = 0;
XIP_SFlash_Opt_Enter(&isAesEnable);
ret = XIP_SFlash_Erase_With_Lock_Ext(&g_flash_cfg, startaddr, len);
XIP_SFlash_Opt_Exit(isAesEnable);
return ret;
}
/**
* @brief set flash cache
*
* @param cont_read
* @param cache_enable
* @param cache_way_disable
* @param flash_offset
* @return BL_Err_Type
*/
BL_Err_Type ATTR_TCM_SECTION flash_set_cache(uint8_t cont_read, uint8_t cache_enable, uint8_t cache_way_disable, uint32_t flash_offset)
{
uint8_t isAesEnable = 0;
uint32_t tmp[1];
BL_Err_Type stat;
SF_Ctrl_Set_Owner(SF_CTRL_OWNER_SAHB);
XIP_SFlash_Opt_Enter(&isAesEnable);
/* To make it simple, exit cont read anyway */
SFlash_Reset_Continue_Read(&g_flash_cfg);
if (g_flash_cfg.cReadSupport == 0) {
cont_read = 0;
}
if (cont_read == 1) {
stat = SFlash_Read(&g_flash_cfg, g_flash_cfg.ioMode & 0xf, 1, 0x00000000, (uint8_t *)tmp, sizeof(tmp));
if (SUCCESS != stat) {
XIP_SFlash_Opt_Exit(isAesEnable);
return ERROR;
}
}
/* Set default value */
SFlash_Cache_Enable_Set(0xf);
if (cache_enable) {
SF_Ctrl_Set_Flash_Image_Offset(flash_offset);
SFlash_Cache_Read_Enable(&g_flash_cfg, g_flash_cfg.ioMode & 0xf, cont_read, cache_way_disable);
}
XIP_SFlash_Opt_Exit(isAesEnable);
return SUCCESS;
}

8
drivers/bl602_driver/hal_drv/src/hal_uart.c
View file

@ -342,7 +342,6 @@ int uart_register(enum uart_index_type index, const char *name)
dev->write = uart_write;
dev->read = uart_read;
dev->status = DEVICE_UNREGISTER;
dev->type = DEVICE_CLASS_UART;
dev->handle = NULL;
@ -358,6 +357,7 @@ void uart_isr(uart_device_t *handle)
uint32_t tmpVal = 0;
uint32_t maskVal = 0;
uint32_t UARTx = (UART0_BASE + handle->id * 0x100);
uint16_t len;
tmpVal = BL_RD_REG(UARTx, UART_INT_STS);
maskVal = BL_RD_REG(UARTx, UART_INT_MASK);
@ -386,14 +386,14 @@ void uart_isr(uart_device_t *handle)
/* Rx fifo ready interrupt,auto-cleared when data is popped */
if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_FIFO_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_FIFO_MASK)) {
uint8_t buffer[UART_FIFO_MAX_LEN];
UART_ReceiveData(handle->id, buffer, handle->fifo_threshold);
handle->parent.callback(&handle->parent, &buffer[0], handle->fifo_threshold, UART_EVENT_RX_FIFO);
len = UART_ReceiveData(handle->id, buffer, handle->fifo_threshold);
handle->parent.callback(&handle->parent, &buffer[0], len, UART_EVENT_RX_FIFO);
}
/* Rx time-out interrupt */
if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_RTO_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_RTO_MASK)) {
uint8_t buffer[UART_FIFO_MAX_LEN];
uint8_t len = UART_ReceiveData(handle->id, buffer, handle->fifo_threshold);
len = UART_ReceiveData(handle->id, buffer, handle->fifo_threshold);
handle->parent.callback(&handle->parent, &buffer[0], len, UART_EVENT_RTO);
BL_WR_REG(UARTx, UART_INT_CLEAR, 0x10);
}

2
drivers/bl602_driver/risc-v/Core/Include/cmsis_compatible_gcc.h
View file

@ -124,7 +124,7 @@ extern void clic_clear_pending(uint32_t source);
#define CPU_Interrupt_Disable clic_disable_interrupt
#define NVIC_ClearPendingIRQ clic_clear_pending
#define CPU_Interrupt_Pending_Clear clic_clear_pending
//#define __set_MSP(val) __ASM volatile ("lw sp,0(%0)":: "r"(val))
#define __set_MSP(msp) __ASM volatile("add sp, x0, %0" ::"r"(msp))

1
drivers/bl602_driver/startup/GCC/entry.S
View file

@ -78,6 +78,7 @@ _enter:
/* start load code to itcm like. */
call start_load
jal System_Post_Init
/* At this point we can enter the C runtime's startup file. The arguments
* to this function are designed to match those provided to the SEE, just
* so we don't have to write another ABI. */

2
drivers/bl602_driver/startup/interrupt.c
View file

@ -68,7 +68,7 @@ const pFunc __Vectors[] __attribute__((section(".init"), aligned(64))) = {
clic_mtimer_handler_Wrapper, /* */
(pFunc)0x00000004, /* */
(pFunc)0x00001007, /* */
(pFunc)0x00010002, /* */
(pFunc)0x00010102, /* *///disable log as default
clic_mext_handler_Wrapper, /* */
clic_csoft_handler_Wrapper, /* */
(pFunc)2000000, /* */

15
drivers/bl602_driver/startup/system_bl602.c
View file

@ -30,11 +30,8 @@ void SystemInit(void)
uint32_t i = 0;
uint32_t tmpVal = 0;
<<<<<<< HEAD
=======
__disable_irq();
>>>>>>> [feat][global_irq] add nesting for global irq enable and disable
/* disable hardware_pullup_pull_down (reg_en_hw_pu_pd = 0) */
tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_REG_EN_HW_PU_PD);
@ -82,6 +79,18 @@ void SystemInit(void)
__enable_irq();
}
/*identify flash config automaticly*/
extern BL_Err_Type flash_init(void);
extern void bflb_platform_print_set(uint8_t disable);
void System_Post_Init(void)
{
PDS_Trim_RC32M();
HBN_Trim_RC32K();
bflb_platform_print_set(1);
flash_init();
bflb_platform_print_set(0);
}
void System_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
}

1
drivers/bl602_driver/std_drv/inc/bl602_hbn.h
View file

@ -440,6 +440,7 @@ BL_Err_Type HBN_Set_Ldo11_All_Vout(HBN_LDO_LEVEL_Type ldoLevel);
BL_Err_Type HBN_32K_Sel(HBN_32K_CLK_Type clkType);
BL_Err_Type HBN_Set_UART_CLK_Sel(HBN_UART_CLK_Type clkSel);
BL_Err_Type HBN_Set_XCLK_CLK_Sel(HBN_XCLK_CLK_Type xClk);
HBN_ROOT_CLK_Type HBN_Get_Root_CLK_Sel(void);
BL_Err_Type HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_Type rootClk);
/*----------*/
BL_Err_Type HBN_Set_HRAM_slp(void);

1
drivers/bl602_driver/std_drv/inc/bl602_i2c.h
View file

@ -178,6 +178,7 @@ void I2C_SendWord(I2C_ID_Type i2cNo, uint32_t data);
uint32_t I2C_RecieveWord(I2C_ID_Type i2cNo);
void I2C_Enable(I2C_ID_Type i2cNo);
void I2C_Disable(I2C_ID_Type i2cNo);
BL_Err_Type I2C_SetDeglitchCount(I2C_ID_Type i2cNo, uint8_t cnt);
BL_Err_Type I2C_Reset(I2C_ID_Type i2cNo);
void I2C_SetPrd(I2C_ID_Type i2cNo, uint8_t phase);
void I2C_ClockSet(I2C_ID_Type i2cNo, uint32_t clk);

4
drivers/bl602_driver/std_drv/inc/bl602_ir.h
View file

@ -244,9 +244,9 @@ uint8_t IR_GetRxFIFOCount(void);
IR_RxMode_Type IR_LearnToInit(uint32_t *data, uint8_t *length);
BL_Err_Type IR_LearnToSend(IR_RxMode_Type mode, uint32_t *data, uint8_t length);
uint8_t IR_LearnToReceive(IR_RxMode_Type mode, uint32_t *data);
BL_Sts_Type IR_LEDInit(HBN_XCLK_CLK_Type clk, uint8_t div, uint8_t unit, uint8_t code0H, uint8_t code0L, uint8_t code1H,
BL_Err_Type IR_LEDInit(HBN_XCLK_CLK_Type clk, uint8_t div, uint8_t unit, uint8_t code0H, uint8_t code0L, uint8_t code1H,
uint8_t code1L);
BL_Sts_Type IR_LEDSend(uint32_t data);
BL_Err_Type IR_LEDSend(uint32_t data);
/*@} end of group IR_Public_Functions */

1
drivers/bl602_driver/std_drv/inc/bl602_uart.h
View file

@ -92,6 +92,7 @@ typedef enum {
* @brief UART stop bits type definiton
*/
typedef enum {
UART_STOPBITS_0_5, /*!< UART data stop bits length:0.5 bits */
UART_STOPBITS_1, /*!< UART data stop bits length:1 bits */
UART_STOPBITS_1_5, /*!< UART data stop bits length:1.5 bits */
UART_STOPBITS_2, /*!< UART data stop bits length:2 bits */

28
drivers/bl602_driver/std_drv/src/bl602_hbn.c
View file

@ -939,6 +939,34 @@ BL_Err_Type HBN_Set_XCLK_CLK_Sel(HBN_XCLK_CLK_Type xClk)
return SUCCESS;
}
/****************************************************************************/ /**
* @brief get root clock selection
*
* @param None
*
* @return root clock selection
*
*******************************************************************************/
HBN_ROOT_CLK_Type ATTR_CLOCK_SECTION HBN_Get_Root_CLK_Sel(void)
{
uint32_t tmpVal = 0;
tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
switch (BL_GET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL)) {
case 0:
return HBN_ROOT_CLK_RC32M;
case 1:
return HBN_ROOT_CLK_XTAL;
case 2:
return HBN_ROOT_CLK_PLL;
case 3:
return HBN_ROOT_CLK_PLL;
default:
return HBN_ROOT_CLK_RC32M;
}
}
/****************************************************************************/ /**
* @brief Select root clk source
*

36
drivers/bl602_driver/std_drv/src/bl602_i2c.c
View file

@ -312,6 +312,42 @@ void I2C_Init(I2C_ID_Type i2cNo, I2C_Direction_Type direct, I2C_Transfer_Cfg *cf
#endif
}
/****************************************************************************/ /**
* @brief Set de-glitch function cycle count value
*
* @param i2cNo: I2C ID type
* @param cnt: De-glitch function cycle count
*
* @return SUCCESS
*
*******************************************************************************/
BL_Err_Type I2C_SetDeglitchCount(I2C_ID_Type i2cNo, uint8_t cnt)
{
uint32_t tmpVal;
uint32_t I2Cx = I2C_BASE;
/* Check the parameters */
CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo));
tmpVal = BL_RD_REG(I2Cx, I2C_CONFIG);
if (cnt > 0) {
/* enable de-glitch function */
tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_DEG_EN);
} else if (cnt == 0) {
/* disable de-glitch function */
tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_DEG_EN);
} else {
return ERROR;
}
/* Set count value */
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_DEG_CNT, cnt);
BL_WR_REG(I2Cx, I2C_CONFIG, tmpVal);
return SUCCESS;
}
/****************************************************************************/ /**
* @brief Set i2c prd
*

6
drivers/bl602_driver/std_drv/src/bl602_ir.c
View file

@ -905,7 +905,7 @@ IR_RxMode_Type IR_LearnToInit(uint32_t *data, uint8_t *length)
if (timeoutCnt == 0) {
IR_Disable(IR_RX);
return TIMEOUT;
return IR_RX_SWM;
}
}
@ -1078,7 +1078,7 @@ BL_Err_Type IR_LearnToSend(IR_RxMode_Type mode, uint32_t *data, uint8_t length)
* @return SUCCESS
*
*******************************************************************************/
BL_Sts_Type IR_LEDInit(HBN_XCLK_CLK_Type clk, uint8_t div, uint8_t unit, uint8_t code0H, uint8_t code0L, uint8_t code1H, uint8_t code1L)
BL_Err_Type IR_LEDInit(HBN_XCLK_CLK_Type clk, uint8_t div, uint8_t unit, uint8_t code0H, uint8_t code0L, uint8_t code1H, uint8_t code1L)
{
IR_TxCfg_Type txCfg = {
24, /* 24-bit data */
@ -1128,7 +1128,7 @@ BL_Sts_Type IR_LEDInit(HBN_XCLK_CLK_Type clk, uint8_t div, uint8_t unit, uint8_t
* @return SUCCESS
*
*******************************************************************************/
BL_Sts_Type IR_LEDSend(uint32_t data)
BL_Err_Type IR_LEDSend(uint32_t data)
{
/* Change MSB_first to LSB_first */
data = ((data >> 1) & 0x55555555) | ((data << 1) & 0xaaaaaaaa);

156
drivers/bl602_driver/std_drv/src/bl602_sf_cfg_ext.c
View file

@ -121,7 +121,7 @@ static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_FM_25Q08={
.ioMode=SF_CTRL_QIO_MODE,
.clkDelay=1,
.clkInvert=0x3f,
.clkInvert=0x01,
.resetEnCmd=0x66,
.resetCmd=0x99,
@ -162,7 +162,7 @@ static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_FM_25Q08={
.timeE32k=1200,
.timeE64k=1200,
.timePagePgm=5,
.timeCe=20*1000,
.timeCe=33000,
.pdDelay=20,
.qeData=0,
};
@ -217,9 +217,9 @@ static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Gd_Md_40D={
.qpageProgramCmd=0x32,
.qppAddrMode=SF_CTRL_ADDR_1_LINE,
.ioMode=SF_CTRL_DO_MODE,
.ioMode=0x11,
.clkDelay=1,
.clkInvert=0x3f,
.clkInvert=0x01,
.resetEnCmd=0x66,
.resetCmd=0x99,
@ -260,7 +260,7 @@ static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Gd_Md_40D={
.timeE32k=1200,
.timeE64k=1200,
.timePagePgm=5,
.timeCe=20*1000,
.timeCe=33000,
.pdDelay=20,
.qeData=0,
};
@ -317,7 +317,7 @@ static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_XM25QH16={
.ioMode=SF_CTRL_QIO_MODE,
.clkDelay=1,
.clkInvert=0x3f,
.clkInvert=0x01,
.resetEnCmd=0x66,
.resetCmd=0x99,
@ -358,7 +358,7 @@ static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_XM25QH16={
.timeE32k=1600,
.timeE64k=2000,
.timePagePgm=5,
.timeCe=20*1000,
.timeCe=33000,
.pdDelay=3,
.qeData=0,
};
@ -415,7 +415,7 @@ static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_MX_KH25={
.ioMode=0x11,
.clkDelay=1,
.clkInvert=0x3f,
.clkInvert=0x01,
.resetEnCmd=0x66,
.resetCmd=0x99,
@ -456,7 +456,105 @@ static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_MX_KH25={
.timeE32k=1200,
.timeE64k=1200,
.timePagePgm=5,
.timeCe=20*1000,
.timeCe=33000,
.pdDelay=20,
.qeData=0,
};
static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_ZD_25Q16B={
.resetCreadCmd=0xff,
.resetCreadCmdSize=3,
.mid=0xba,
.deBurstWrapCmd=0x77,
.deBurstWrapCmdDmyClk=0x3,
.deBurstWrapDataMode=SF_CTRL_DATA_4_LINES,
.deBurstWrapData=0xF0,
/*reg*/
.writeEnableCmd=0x06,
.wrEnableIndex=0x00,
.wrEnableBit=0x01,
.wrEnableReadRegLen=0x01,
.qeIndex=1,
.qeBit=0x01,
.qeWriteRegLen=0x02,
.qeReadRegLen=0x1,
.busyIndex=0,
.busyBit=0x00,
.busyReadRegLen=0x1,
.releasePowerDown=0xab,
.readRegCmd[0]=0x05,
.readRegCmd[1]=0x35,
.writeRegCmd[0]=0x01,
.writeRegCmd[1]=0x01,
.fastReadQioCmd=0xeb,
.frQioDmyClk=16/8,
.cReadSupport=1,
.cReadMode=0xa0,
.burstWrapCmd=0x77,
.burstWrapCmdDmyClk=0x3,
.burstWrapDataMode=SF_CTRL_DATA_4_LINES,
.burstWrapData=0x40,
/*erase*/
.chipEraseCmd=0xc7,
.sectorEraseCmd=0x20,
.blk32EraseCmd=0x52,
.blk64EraseCmd=0xd8,
/*write*/
.pageProgramCmd=0x02,
.qpageProgramCmd=0x32,
.qppAddrMode=SF_CTRL_ADDR_1_LINE,
.ioMode=0x14,
.clkDelay=1,
.clkInvert=0x01,
.resetEnCmd=0x66,
.resetCmd=0x99,
.cRExit=0xff,
.wrEnableWriteRegLen=0x00,
/*id*/
.jedecIdCmd=0x9f,
.jedecIdCmdDmyClk=0,
.qpiJedecIdCmd=0x9f,
.qpiJedecIdCmdDmyClk=0x00,
.sectorSize=4,
.pageSize=256,
/*read*/
.fastReadCmd=0x0b,
.frDmyClk=8/8,
.qpiFastReadCmd =0x0b,
.qpiFrDmyClk=8/8,
.fastReadDoCmd=0x3b,
.frDoDmyClk=8/8,
.fastReadDioCmd=0xbb,
.frDioDmyClk=0,
.fastReadQoCmd=0x6b,
.frQoDmyClk=8/8,
.qpiFastReadQioCmd=0xeb,
.qpiFrQioDmyClk=16/8,
.qpiPageProgramCmd=0x02,
.writeVregEnableCmd=0x50,
/* qpi mode */
.enterQpi=0x38,
.exitQpi=0xff,
/*AC*/
.timeEsector=300,
.timeE32k=1200,
.timeE64k=1200,
.timePagePgm=5,
.timeCe=33000,
.pdDelay=20,
.qeData=0,
};
@ -487,6 +585,11 @@ static const ATTR_TCM_CONST_SECTION Flash_Info_t flashInfos[]={
//.name="XM_25QH32_32_33",
.cfg=&flashCfg_XM25QH16,
},
{
.jedecID=0x174020,
//.name="XM_25QH64_64_33",
.cfg=&flashCfg_XM25QH16,
},
{
.jedecID=0x1320C2,
//.name="MX_KH40_04_33",
@ -512,6 +615,21 @@ static const ATTR_TCM_CONST_SECTION Flash_Info_t flashInfos[]={
//.name="ZB_D80B_80_33",
.cfg=&flashCfg_MX_KH25,
},
{
.jedecID=0x15405E,
//.name="ZB_25Q16B_15_33",
.cfg=&flashCfg_XM25QH16,
},
{
.jedecID=0x16405E,
//.name="ZB_25Q32B_16_33",
.cfg=&flashCfg_XM25QH16,
},
{
.jedecID=0x17405E,
//.name="ZB_25VQ64_64_33",
.cfg=&flashCfg_XM25QH16,
},
{
.jedecID=0x15605E,
//.name="ZB_25VQ16_16_33",
@ -527,6 +645,26 @@ static const ATTR_TCM_CONST_SECTION Flash_Info_t flashInfos[]={
//.name="TH_25Q16",
.cfg=&flashCfg_FM_25Q08,
},
{
.jedecID=0x1740C8,
//.name="GD_25Q64E_64_33",
.cfg=&flashCfg_XM25QH16,
},
{
.jedecID=0x176085,
//.name="Puya_P25Q64H_64_33",
.cfg=&flashCfg_XM25QH16,
},
{
.jedecID=0x17400B,
//.name="XT_25F64B",
.cfg=&flashCfg_FM_25Q08,
},
{
.jedecID=0x1560BA,
//.name="ZD_25Q16B",
.cfg=&flashCfg_ZD_25Q16B,
},
};
/*@} end of group SF_CFG_EXT_Private_Variables */

2
drivers/bl602_driver/std_drv/src/bl602_spi.c
View file

@ -434,7 +434,7 @@ BL_Err_Type SPI_SetDeglitchCount(SPI_ID_Type spiNo, uint8_t cnt)
/* Set count value */
tmpVal = BL_RD_REG(SPIx, SPI_CONFIG);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_DEG_CNT, cnt - 1);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_DEG_CNT, cnt);
BL_WR_REG(SPIx, SPI_CONFIG, tmpVal);
return SUCCESS;

4
drivers/bl602_driver/std_drv/src/bl602_uart.c
View file

@ -246,7 +246,7 @@ BL_Err_Type UART_Init(UART_ID_Type uartId, UART_CFG_Type *uartCfg)
tmpValRxCfg = BL_SET_REG_BITS_VAL(tmpValRxCfg, UART_CR_URX_BIT_CNT_D, (uartCfg->dataBits + 4));
/* Configure tx stop bits */
tmpValTxCfg = BL_SET_REG_BITS_VAL(tmpValTxCfg, UART_CR_UTX_BIT_CNT_P, (uartCfg->stopBits + 1));
tmpValTxCfg = BL_SET_REG_BITS_VAL(tmpValTxCfg, UART_CR_UTX_BIT_CNT_P, uartCfg->stopBits);
/* Configure tx cts flow control function */
if (ENABLE == uartCfg->ctsFlowControl) {
@ -576,7 +576,7 @@ BL_Err_Type UART_SetDeglitchCount(UART_ID_Type uartId, uint8_t deglitchCnt)
/* Set count value */
tmpVal = BL_RD_REG(UARTx, UART_URX_CONFIG);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, UART_CR_URX_DEG_CNT, deglitchCnt - 1);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, UART_CR_URX_DEG_CNT, deglitchCnt);
BL_WR_REG(UARTx, UART_URX_CONFIG, tmpVal);
return SUCCESS;

6
drivers/bl602_driver/std_drv/src/bl602_xip_sflash_ext.c
View file

@ -108,7 +108,11 @@ BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_State_Restore_Ext(SPI_Flash_Cfg_Type *pF
SF_Ctrl_Set_Flash_Image_Offset(offset);
SFlash_SetBurstWrap(pFlashCfg);
if(((pFlashCfg->ioMode>>4)&0x01) == 0) {
if((pFlashCfg->ioMode&0x0f)==SF_CTRL_QO_MODE || (pFlashCfg->ioMode&0x0f)==SF_CTRL_QIO_MODE) {
SFlash_SetBurstWrap(pFlashCfg);
}
}
SFlash_Read(pFlashCfg,ioMode,1,0x0,(uint8_t *)tmp, sizeof(tmp));
SFlash_Set_IDbus_Cfg(pFlashCfg,ioMode,1,0,32);