mirror of
https://github.com/Fishwaldo/bl_mcu_sdk.git
synced 2025-07-08 05:48:28 +00:00
[fix][pm] enable gpio ie in pds31 mode when pds pin reawakens
This commit is contained in:
jzlv
parent
8b587dbed2
commit
8f233e91d6
2 changed files with 150 additions and 81 deletions
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@ -38,7 +38,6 @@ uint32_t flash_offset = 0;
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SPI_Flash_Cfg_Type *flash_cfg;
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#define PM_PDS_GPIO_IE_PUPD 0
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#define PM_PDS_FLASH_POWER_OFF 1
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#define PM_PDS_DLL_POWER_OFF 1
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#define PM_PDS_PLL_POWER_OFF 1
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@ -857,15 +856,11 @@ static ATTR_TCM_SECTION void PDS_Update_Flash_Ctrl_Setting(uint8_t fastClock)
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SF_Ctrl_Set_Clock_Delay(fastClock);
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}
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ATTR_TCM_SECTION void pm_pds_enter_done(bool store_flag)
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ATTR_TCM_SECTION void pm_pds_enter_done(void)
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{
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if (store_flag) {
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__asm__ __volatile__(
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"la a2, __ld_pds_bak_addr\n\t"
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"sw ra, 0(a2)\n\t");
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}
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BL702_Delay_MS(1);
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__WFI(); /* if(.wfiMask==0){CPU won't power down until PDS module had seen __wfi} */
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}
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@ -887,27 +882,10 @@ ATTR_TCM_SECTION void pm_pds_enter_done(bool store_flag)
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*/
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ATTR_TCM_SECTION void pm_pds_mode_enter(enum pm_pds_sleep_level pds_level, uint32_t sleep_time)
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{
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bool store_flag = 0;
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PDS_DEFAULT_LV_CFG_Type *pPdsCfg = NULL;
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uint32_t tmpVal;
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uint32_t flash_cfg_len;
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if (HBN_STATUS_ENTER_FLAG == BL_RD_REG(HBN_BASE, HBN_RSV0)) {
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store_flag = 1;
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// Get cache way disable setting
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cacheWayDisable = (*(volatile uint32_t *)(L1C_BASE + 0x00) >> 8) & 0x0F;
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// Get psram io configuration
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psramIoCfg = *(volatile uint32_t *)(GLB_BASE + 0x88);
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// Get flash offset
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flash_offset = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_ID0_OFFSET);
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} else {
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store_flag = 0;
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}
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/* To make it simple and safe*/
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cpu_global_irq_disable();
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@ -1003,9 +981,9 @@ ATTR_TCM_SECTION void pm_pds_mode_enter(enum pm_pds_sleep_level pds_level, uint3
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pPdsCfg->pdsCtl.pdsLdoVol = PM_PDS_LDO_LEVEL_DEFAULT;
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pPdsCfg->pdsCtl.pdsLdoVselEn = 1;
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#if PM_PDS_GPIO_IE_PUPD == 0
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if (BL_GET_REG_BITS_VAL(BL_RD_REG(PDS_BASE, PDS_GPIO_INT), PDS_GPIO_INT_MASK)) {
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pPdsCfg->pdsCtl.gpioIePuPd = 0;
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#endif
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}
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#if PM_PDS_RF_POWER_OFF == 0
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pPdsCfg->pdsCtl.pdsCtlRfSel = 0;
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@ -1014,7 +992,110 @@ ATTR_TCM_SECTION void pm_pds_mode_enter(enum pm_pds_sleep_level pds_level, uint3
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AON_Set_LDO11_SOC_Sstart_Delay(0x2);
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PDS_Default_Level_Config(pPdsCfg, sleep_time);
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if (store_flag) {
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__WFI(); /* if(.wfiMask==0){CPU won't power down until PDS module had seen __wfi} */
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#if PM_PDS_PLL_POWER_OFF
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GLB_Set_System_CLK(XTAL_TYPE, BSP_ROOT_CLOCK_SOURCE);
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PDS_Update_Flash_Ctrl_Setting(1);
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#endif
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#if PM_PDS_FLASH_POWER_OFF
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HBN_Set_Pad_23_28_Pullnone();
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/* Init flash gpio */
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SF_Cfg_Init_Flash_Gpio(0, 1);
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SF_Ctrl_Set_Owner(SF_CTRL_OWNER_SAHB);
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SFlash_Restore_From_Powerdown(flash_cfg, 0);
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#endif
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cpu_global_irq_enable();
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}
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ATTR_TCM_SECTION void pm_pds31_fast_mode_enter(enum pm_pds_sleep_level pds_level, uint32_t sleep_time)
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{
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PDS_DEFAULT_LV_CFG_Type *pPdsCfg = &pdsCfgLevel31;
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uint32_t tmpVal;
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uint32_t flash_cfg_len;
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// Get cache way disable setting
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cacheWayDisable = (*(volatile uint32_t *)(L1C_BASE + 0x00) >> 8) & 0x0F;
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// Get psram io configuration
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psramIoCfg = *(volatile uint32_t *)(GLB_BASE + 0x88);
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// Get flash offset
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flash_offset = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_ID0_OFFSET);
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/* To make it simple and safe*/
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cpu_global_irq_disable();
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flash_get_cfg((uint8_t **)&flash_cfg, &flash_cfg_len);
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HBN_Set_Ldo11_All_Vout(PM_PDS_LDO_LEVEL_DEFAULT);
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PDS_WAKEUP_IRQHandler_Install();
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BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, 0xffffffff);
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BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, 0);
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tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
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tmpVal &= ~(1 << 8); //unmask pds wakeup
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if (!BL_GET_REG_BITS_VAL(BL_RD_REG(PDS_BASE, PDS_GPIO_INT), PDS_GPIO_INT_MASK))
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tmpVal |= (1 << 19); //enable gpio wakeup for pds
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if (BL_GET_REG_BITS_VAL(BL_RD_REG(HBN_BASE, HBN_IRQ_MODE), HBN_REG_AON_PAD_IE_SMT))
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tmpVal |= (1 << 17); //enable hbn out0 wakeup for pds
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if (sleep_time)
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tmpVal |= (1 << 16); //unmask pds sleep time wakeup
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BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);
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PDS_IntClear();
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/* enable PDS interrupt to wakeup CPU (PDS1:CPU not powerdown, CPU __WFI) */
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CPU_Interrupt_Enable(PDS_WAKEUP_IRQn);
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#if PM_PDS_FLASH_POWER_OFF
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HBN_Power_Down_Flash(flash_cfg);
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/* turn_off_ext_flash_pin, GPIO23 - GPIO28 */
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for (uint32_t pin = 23; pin <= 28; pin++) {
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GLB_GPIO_Set_HZ(pin);
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}
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/* SF io select from efuse value */
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uint32_t flash_select = BL_RD_WORD(0x40007074);
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if (((flash_select >> 26) & 7) == 0) {
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HBN_Set_Pad_23_28_Pullup();
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}
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pPdsCfg->pdsCtl.puFlash = 1;
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#endif
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#if PM_PDS_PLL_POWER_OFF
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PDS_Power_Off_PLL();
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#endif
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#if PM_PDS_DLL_POWER_OFF
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GLB_Set_System_CLK(GLB_DLL_XTAL_NONE, GLB_SYS_CLK_RC32M);
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AON_Power_Off_XTAL();
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GLB_Power_Off_DLL();
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PDS_Update_Flash_Ctrl_Setting(0);
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#endif
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/* pds31 : ldo11rt_iload_sel=1 */
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HBN_Set_Ldo11rt_Drive_Strength(HBN_LDO11RT_DRIVE_STRENGTH_10_100UA);
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pPdsCfg->pdsCtl.pdsLdoVol = PM_PDS_LDO_LEVEL_DEFAULT;
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pPdsCfg->pdsCtl.pdsLdoVselEn = 1;
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if (BL_GET_REG_BITS_VAL(BL_RD_REG(PDS_BASE, PDS_GPIO_INT), PDS_GPIO_INT_MASK)) {
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pPdsCfg->pdsCtl.gpioIePuPd = 0;
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}
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#if PM_PDS_RF_POWER_OFF == 0
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pPdsCfg->pdsCtl.pdsCtlRfSel = 0;
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#endif
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/* config ldo11soc_sstart_delay_aon =2 , cr_pds_pd_ldo11=0 to speedup ldo11soc_rdy_aon */
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AON_Set_LDO11_SOC_Sstart_Delay(0x2);
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PDS_Default_Level_Config(pPdsCfg, sleep_time);
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__asm__ __volatile__(
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"csrr a0, mtvec\n\t"
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"csrr a1, mstatus\n\t"
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@ -1047,35 +1128,22 @@ ATTR_TCM_SECTION void pm_pds_mode_enter(enum pm_pds_sleep_level pds_level, uint3
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"sw t4, 26*4(a2)\n\t"
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"sw t5, 27*4(a2)\n\t"
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"sw t6, 28*4(a2)\n\t");
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}
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pm_pds_enter_done(store_flag);
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pm_pds_enter_done();
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#if PM_PDS_PLL_POWER_OFF
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GLB_Set_System_CLK(XTAL_TYPE, BSP_ROOT_CLOCK_SOURCE);
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PDS_Update_Flash_Ctrl_Setting(1);
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#endif
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#if PM_PDS_FLASH_POWER_OFF
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if (pds_level < PM_PDS_LEVEL_4) {
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HBN_Set_Pad_23_28_Pullnone();
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/* Init flash gpio */
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SF_Cfg_Init_Flash_Gpio(0, 1);
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SF_Ctrl_Set_Owner(SF_CTRL_OWNER_SAHB);
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SFlash_Restore_From_Powerdown(flash_cfg, 0);
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}
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#endif
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cpu_global_irq_enable();
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if (store_flag) {
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// Get cache way disable setting
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*(volatile uint32_t *)(L1C_BASE + 0x00) &= ~(0x0F < 8);
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*(volatile uint32_t *)(L1C_BASE + 0x00) |= cacheWayDisable;
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// Get psram io configuration
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*(volatile uint32_t *)(GLB_BASE + 0x88) = psramIoCfg;
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}
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}
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/**
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* @brief
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@ -35,6 +35,8 @@ extern uint32_t psramIoCfg;
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/* Flash offset value, will get from sf_ctrl register */
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extern uint32_t flash_offset;
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extern void pm_pds31_fast_mode_enter(enum pm_pds_sleep_level pds_level, uint32_t sleep_time);
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extern SPI_Flash_Cfg_Type *flash_cfg;
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void ATTR_PDS_RAM_SECTION pm_pds_fastboot_entry(void);
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@ -58,12 +60,11 @@ uint32_t hal_pds_enter_with_time_compensation(uint32_t pdsLevel, uint32_t pdsSle
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uint32_t actualSleepDuration_32768cycles = 0;
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uint32_t actualSleepDuration_ms = 0;
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if (pdsLevel >= 4 && HBN_Get_Status_Flag() != HBN_STATUS_ENTER_FLAG) {
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pm_set_wakeup_callback(pm_pds_fastboot_entry);
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}
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HBN_Get_RTC_Timer_Val(&rtcLowBeforeSleep, &rtcHighBeforeSleep);
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pm_pds_mode_enter(pdsLevel, pdsSleepCycles);
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pm_pds31_fast_mode_enter(pdsLevel, pdsSleepCycles);
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HBN_Get_RTC_Timer_Val(&rtcLowAfterSleep, &rtcHighAfterSleep);
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