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[update][drivers] update bl602 and bl702 drivers

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This commit is contained in:
jzlv 2022-01-13 16:31:12 +08:00
parent b71a70ec2b
commit b6c09e3e2b
45 changed files with 2680 additions and 1006 deletions
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14
drivers/bl602_driver/hal_drv/default_config/dac_config.h Normal file
View file

@ -0,0 +1,14 @@
#ifndef _DAC_CONFIG_H
#define _DAC_CONFIG_H
/* | vref source | rng | output range |
* | Internal | 0 | 0.2~1V |
* | Internal | 1/2 | 0.224~1.425V |
* | Internal | 3 | 0.2~1.8V |
* | Extern | 0 | 0.1Vref~0.5Vref |
* | Extern | 1/2 | 0.1125Vref~0.7125Vref |
* | Extern | 3 | 0.1Vref~0.9Vref |
*/
#define DAC_REF_RNG_DEFAULT_SELECT (0x3) /*!< ADC 1.8V select */
#endif

127
drivers/bl602_driver/hal_drv/inc/hal_boot2.h
View file

@ -52,6 +52,20 @@
#define HAL_BOOT2_SUPPORT_EFLASH_LOADER_RAM 1 /* 1 support decompress, 0 not support */
#define HAL_BOOT2_SUPPORT_EFLASH_LOADER_FLASH 0 /* 1 support decompress, 0 not support */
#define HAL_BOOT2_FW_IMG_OFFSET_AFTER_HEADER 4*1024
#define HAL_BOOT2_HASH_SIZE 256 / 8
#define HAL_BOOT2_ECC_KEYXSIZE 256 / 8
#define HAL_BOOT2_ECC_KEYYSIZE 256 / 8
#define HAL_BOOT2_SIGN_MAXSIZE 2048 / 8
#define HAL_BOOT2_DEADBEEF_VAL 0xdeadbeef
#define HAL_BOOT2_CPU_MAX 1
#define HAL_BOOT2_CPU0_MAGIC "BFNP"
#define HAL_BOOT2_CPU1_MAGIC "BFAP"
typedef struct
{
uint8_t encrypted[HAL_EFUSE_CPU_MAX];
@ -89,6 +103,115 @@ typedef struct
uint32_t crc32;
} hal_flash_config;
struct hal_bootheader_t
{
uint32_t magicCode; /*'BFXP'*/
uint32_t rivison;
hal_flash_config flash_cfg;
hal_pll_config clk_cfg;
__PACKED_UNION
{
__PACKED_STRUCT
{
uint32_t sign : 2; /* [1: 0] for sign*/
uint32_t encrypt_type : 2; /* [3: 2] for encrypt */
uint32_t key_sel : 2; /* [5: 4] for key sel in boot interface*/
uint32_t rsvd6_7 : 2; /* [7: 6] for encrypt*/
uint32_t no_segment : 1; /* [8] no segment info */
uint32_t cache_enable : 1; /* [9] for cache */
uint32_t notLoadInBoot : 1; /* [10] not load this img in bootrom */
uint32_t aes_region_lock : 1; /* [11] aes region lock */
uint32_t cache_way_disable : 4; /* [15: 12] cache way disable info*/
uint32_t crcIgnore : 1; /* [16] ignore crc */
uint32_t hash_ignore : 1; /* [17] hash crc */
uint32_t halt_cpu1 : 1; /* [18] halt ap */
uint32_t rsvd19_31 : 13; /* [31:19] rsvd */
}
bval;
uint32_t wval;
}
bootCfg;
__PACKED_UNION
{
uint32_t segment_cnt;
uint32_t img_len;
}
img_segment_info;
uint32_t bootEntry; /* entry point of the image*/
__PACKED_UNION
{
uint32_t ram_addr;
uint32_t flash_offset;
}
img_start;
uint8_t hash[HAL_BOOT2_HASH_SIZE]; /*hash of the image*/
uint32_t rsv1;
uint32_t rsv2;
uint32_t crc32;
} ;
typedef struct
{
uint8_t encrypt_type;
uint8_t sign_type;
uint8_t key_sel;
uint8_t img_valid;
uint8_t no_segment;
uint8_t cache_enable;
uint8_t cache_way_disable;
uint8_t hash_ignore;
uint8_t aes_region_lock;
uint8_t halt_cpu1;
uint8_t cpu_type;
uint8_t r[1];
__PACKED_UNION
{
uint32_t segment_cnt;
uint32_t img_len;
}
img_segment_info;
uint32_t msp_val;
uint32_t entry_point;
__PACKED_UNION
{
uint32_t ram_addr;
uint32_t flash_offset;
}
img_start;
uint32_t sig_len;
uint32_t sig_len2;
uint32_t deal_len;
uint32_t max_input_len;
uint8_t img_hash[HAL_BOOT2_HASH_SIZE]; //hash of the whole (all)images
uint8_t aes_iv[16 + 4]; //iv in boot header
uint8_t eckye_x[HAL_BOOT2_ECC_KEYXSIZE]; //ec key in boot header
uint8_t eckey_y[HAL_BOOT2_ECC_KEYYSIZE]; //ec key in boot header
uint8_t eckey_x2[HAL_BOOT2_ECC_KEYXSIZE]; //ec key in boot header
uint8_t eckey_y2[HAL_BOOT2_ECC_KEYYSIZE]; //ec key in boot header
uint8_t signature[HAL_BOOT2_SIGN_MAXSIZE]; //signature in boot header
uint8_t signature2[HAL_BOOT2_SIGN_MAXSIZE]; //signature in boot header
} boot2_image_config;
extern boot2_efuse_hw_config g_efuse_cfg;
extern uint8_t g_ps_mode;
extern uint32_t g_user_hash_ignored;
extern struct device *dev_check_hash;
uint32_t hal_boot2_custom(void);
void hal_boot2_reset_sec_eng(void);
void hal_boot2_sw_system_reset(void);
@ -96,11 +219,13 @@ void hal_boot2_set_psmode_status(uint32_t flag);
uint32_t hal_boot2_get_psmode_status(void);
uint32_t hal_boot2_get_user_fw(void);
void hal_boot2_clr_user_fw(void);
void hal_boot2_get_efuse_cfg(boot2_efuse_hw_config *g_efuse_cfg);
void hal_boot2_get_efuse_cfg(boot2_efuse_hw_config *efuse_cfg);
int32_t hal_boot2_get_clk_cfg(hal_pll_config *cfg);
void hal_boot2_sboot_finish(void);
void hal_boot2_uart_gpio_init(void);
void hal_boot2_debug_uart_gpio_init(void);
void hal_boot2_debug_uart_gpio_deinit(void);
int32_t hal_boot_parse_bootheader(boot2_image_config *boot_img_cfg, uint8_t *data);
void hal_boot2_clean_cache(void);
#endif

83
drivers/bl602_driver/hal_drv/inc/hal_dac.h Normal file
View file

@ -0,0 +1,83 @@
/**
* @file hal_dac.h
* @brief
*
* Copyright (c) 2021 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#ifndef __HAL_DAC__H__
#define __HAL_DAC__H__
#ifdef __cplusplus
extern "C" {
#endif
#include "hal_common.h"
#include "drv_device.h"
#include "bl602_config.h"
enum dac_index_type {
#ifdef BSP_USING_DAC0
DAC0_INDEX,
#endif
DAC_MAX_INDEX
};
#define DAC_CHANNEL_0 (1 << 0)
#define DAC_CHANNEL_1 (1 << 1)
#define DAC_CHANNEL_ALL (DAC_CHANNEL_0 | DAC_CHANNEL_1)
/* default a_rng and b_rng is 0x03*/
/*output Voltage = (1.8V-0.2V) * digital_val/1024 + 0.2V */
#define DAC_VREF_INTERNAL 0 /*0.2V~1.8V*/
/*output Voltage = (0.9vref-0.1vref) * digital_val/1024 + 0.1vref */
#define DAC_VREF_EXTERNAL 1 /*0.1vref~0.9vref,using gpio7 for GPIO_FUN_ADC*/
enum dac_sample_frequence {
DAC_SAMPLE_FREQ_8KHZ,
DAC_SAMPLE_FREQ_16KHZ,
DAC_SAMPLE_FREQ_44P1KHZ,
DAC_SAMPLE_FREQ_500KHZ,
};
/**
* @brief DAC clock divider type definition
*/
typedef enum {
DAC_CLK_DIV_16, /*!< ADC clock:on 32M clock is 2M */
DAC_CLK_DIV_32, /*!< ADC clock:on 32M clock is 1M */
DAC_CLK_DIV_RESERVE, /*!< reserved */
DAC_CLK_DIV_64, /*!< ADC clock:on 32M clock is 0.5M */
DAC_CLK_DIV_1, /*!< ADC clock:on 32M clock is 32M */
} DAC_CLK_Type;
typedef struct dac_device {
struct device parent;
enum dac_sample_frequence sample_freq;
uint8_t channels;
uint8_t vref;
void *tx_dma;
} dac_device_t;
#define DAC_DEV(dev) ((adc_device_t *)dev)
int dac_register(enum dac_index_type index, const char *name);
#ifdef __cplusplus
}
#endif
#endif

20
drivers/bl602_driver/hal_drv/inc/hal_dma.h
View file

@ -27,12 +27,12 @@
#include "drv_device.h"
#include "bl602_config.h"
#define DMA_CHANNEL_GET_STATUS 0x10
#define DMA_CHANNEL_START 0x11
#define DMA_CHANNEL_STOP 0x12
#define DMA_CHANNEL_UPDATE 0x13
#define DEVICE_CTRL_DMA_CONFIG_SI 0x14
#define DEVICE_CTRL_DMA_CONFIG_DI 0x15
#define DEVICE_CTRL_DMA_CHANNEL_GET_STATUS 0x10
#define DEVICE_CTRL_DMA_CHANNEL_START 0x11
#define DEVICE_CTRL_DMA_CHANNEL_STOP 0x12
#define DEVICE_CTRL_DMA_CHANNEL_UPDATE 0x13
#define DEVICE_CTRL_DMA_CONFIG_SI 0x14
#define DEVICE_CTRL_DMA_CONFIG_DI 0x15
enum dma_index_type {
#ifdef BSP_USING_DMA0_CH0
@ -62,10 +62,10 @@ enum dma_index_type {
DMA_MAX_INDEX
};
#define dma_channel_start(dev) device_control(dev, DMA_CHANNEL_START, NULL)
#define dma_channel_stop(dev) device_control(dev, DMA_CHANNEL_STOP, NULL)
#define dma_channel_update(dev, list) device_control(dev, DMA_CHANNEL_UPDATE, list)
#define dma_channel_check_busy(dev) device_control(dev, DMA_CHANNEL_GET_STATUS, NULL)
#define dma_channel_start(dev) device_control(dev, DEVICE_CTRL_DMA_CHANNEL_START, NULL)
#define dma_channel_stop(dev) device_control(dev, DEVICE_CTRL_DMA_CHANNEL_STOP, NULL)
#define dma_channel_update(dev, list) device_control(dev, DEVICE_CTRL_DMA_CHANNEL_UPDATE, list)
#define dma_channel_check_busy(dev) device_control(dev, DEVICE_CTRL_DMA_CHANNEL_GET_STATUS, NULL)
#define DMA_LLI_ONCE_MODE 0
#define DMA_LLI_CYCLE_MODE 1

2
drivers/bl602_driver/hal_drv/inc/hal_flash.h
View file

@ -24,10 +24,12 @@
#define __HAL_FLASH__H__
#include "hal_common.h"
#include "bl602_sflash.h"
#define BL_FLASH_XIP_BASE BL602_FLASH_XIP_BASE
#define FLASH_NOT_DETECT 0x10
uint32_t flash_get_jedecid(void);
BL_Err_Type flash_init(void);
BL_Err_Type flash_read_jedec_id(uint8_t *data);
BL_Err_Type flash_read_via_xip(uint32_t addr, uint8_t *data, uint32_t len);

156
drivers/bl602_driver/hal_drv/src/hal_boot2.c
View file

@ -1,3 +1,4 @@
#include "hal_boot2.h"
#include "hal_gpio.h"
#include "hal_flash.h"
@ -10,6 +11,8 @@
#include "bl602_glb.h"
#include "bl602_xip_sflash_ext.h"
#include "tzc_sec_reg.h"
#include "softcrc.h"
#include "hal_sec_hash.h"
/**
* @brief boot2 custom
@ -45,7 +48,7 @@ uint32_t hal_boot2_custom(void)
* @param
* @return None
*/
void hal_boot2_get_efuse_cfg(boot2_efuse_hw_config *g_efuse_cfg)
void hal_boot2_get_efuse_cfg(boot2_efuse_hw_config *efuse_cfg)
{
uint32_t tmp;
uint32_t rootClk;
@ -60,13 +63,13 @@ void hal_boot2_get_efuse_cfg(boot2_efuse_hw_config *g_efuse_cfg)
HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_RC32M);
/* Get sign and aes type*/
EF_Ctrl_Read_Secure_Boot((EF_Ctrl_Sign_Type *)g_efuse_cfg->sign, (EF_Ctrl_SF_AES_Type *)g_efuse_cfg->encrypted);
EF_Ctrl_Read_Secure_Boot((EF_Ctrl_Sign_Type *)efuse_cfg->sign, (EF_Ctrl_SF_AES_Type *)efuse_cfg->encrypted);
/* Get hash:aes key slot 0 and slot1*/
EF_Ctrl_Read_AES_Key(0, (uint32_t *)g_efuse_cfg->pk_hash_cpu0, 8);
EF_Ctrl_Read_Chip_ID(g_efuse_cfg->chip_id);
EF_Ctrl_Read_AES_Key(0, (uint32_t *)efuse_cfg->pk_hash_cpu0, 8);
EF_Ctrl_Read_Chip_ID(efuse_cfg->chip_id);
/* Get HBN check sign config */
EF_Ctrl_Read_Sw_Usage(0, &tmp);
g_efuse_cfg->hbn_check_sign = (tmp >> 22) & 0x01;
efuse_cfg->hbn_check_sign = (tmp >> 22) & 0x01;
/* restore bclk fclk div and root clock sel */
GLB_Set_System_CLK_Div(hdiv, bdiv);
@ -203,3 +206,146 @@ void hal_boot2_debug_uart_gpio_deinit(void)
GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_UART1);
GLB_UART_Sig_Swap_Set(UART_SIG_SWAP_NONE);
}
/****************************************************************************/ /**
* @brief Check if the input public key is the same as burned in the efuse
*
* @param g_boot_img_cfg: Boot image config pointer
* @param data: Image data pointer
*
* @return boot_error_code type
*
*******************************************************************************/
int32_t hal_boot_parse_bootheader(boot2_image_config *boot_img_cfg, uint8_t *data)
{
struct hal_bootheader_t *header = (struct hal_bootheader_t *)data;
uint32_t crc;
uint32_t crc_pass = 0;
uint32_t i = 0;
uint32_t *phash = (uint32_t *)header->hash;
int32_t ret;
if (header->bootCfg.bval.crcIgnore == 1 && header->crc32 == HAL_BOOT2_DEADBEEF_VAL) {
//MSG("Crc ignored\r\n");
crc_pass = 1;
} else {
crc = BFLB_Soft_CRC32((uint8_t *)header, sizeof(struct hal_bootheader_t) - sizeof(header->crc32));
if (header->crc32 == crc) {
crc_pass = 1;
}
}
if (crc_pass) {
if (header->bootCfg.bval.notLoadInBoot) {
return 0x0202;
}
/* Get which CPU's img it is*/
for (i = 0; i < HAL_BOOT2_CPU_MAX; i++) {
if (0 == memcmp((void *)&header->magicCode, HAL_BOOT2_CPU0_MAGIC,
sizeof(header->magicCode))) {
break;
} else if (0 == memcmp((void *)&header->magicCode, HAL_BOOT2_CPU1_MAGIC,
sizeof(header->magicCode))) {
break;
}
}
if (i == HAL_BOOT2_CPU_MAX) {
/* No cpu img magic match */
//MSG_ERR("Magic code error\r\n");
return 0x0203;
}
boot_img_cfg->cpu_type = i;
boot_img_cfg->entry_point = 0;
/* Set image valid 0 as default */
boot_img_cfg->img_valid = 0;
/* Deal with pll config */
/* Encrypt and sign */
boot_img_cfg->encrypt_type = header->bootCfg.bval.encrypt_type;
boot_img_cfg->sign_type = header->bootCfg.bval.sign;
boot_img_cfg->key_sel = header->bootCfg.bval.key_sel;
/* Xip relative */
boot_img_cfg->no_segment = header->bootCfg.bval.no_segment;
boot_img_cfg->cache_enable = header->bootCfg.bval.cache_enable;
boot_img_cfg->aes_region_lock = header->bootCfg.bval.aes_region_lock;
boot_img_cfg->halt_cpu1 = header->bootCfg.bval.halt_cpu1;
boot_img_cfg->cache_way_disable = header->bootCfg.bval.cache_way_disable;
boot_img_cfg->hash_ignore = header->bootCfg.bval.hash_ignore;
/* Firmware len*/
boot_img_cfg->img_segment_info.img_len = header->img_segment_info.img_len;
/* Boot entry and flash offset */
boot_img_cfg->entry_point = header->bootEntry;
boot_img_cfg->img_start.flash_offset = header->img_start.flash_offset;
//MSG("sign %d,encrypt:%d\r\n", boot_img_cfg->sign_type,boot_img_cfg->encrypt_type);
/* Check encrypt and sign match*/
if (g_efuse_cfg.encrypted[i] != 0) {
if (boot_img_cfg->encrypt_type == 0) {
//MSG_ERR("Encrypt not fit\r\n");
return 0x0205;
}
}
if (g_efuse_cfg.sign[i] ^ boot_img_cfg->sign_type) {
//MSG_ERR("sign not fit\r\n");
boot_img_cfg->sign_type = g_efuse_cfg.sign[i];
return 0x0206;
}
if (g_ps_mode == 1 && (!g_efuse_cfg.hbn_check_sign)) {
/* In HBN Mode, if user select to ignore hash and sign*/
boot_img_cfg->hash_ignore = 1;
} else if ((boot_img_cfg->hash_ignore == 1 && *phash != HAL_BOOT2_DEADBEEF_VAL) ||
g_efuse_cfg.sign[i] != 0) {
/* If signed or user not really want to ignore, hash can't be ignored*/
boot_img_cfg->hash_ignore = 0;
}
if (g_user_hash_ignored) {
boot_img_cfg->hash_ignore = 1;
}
ARCH_MemCpy_Fast(boot_img_cfg->img_hash, header->hash, sizeof(header->hash));
if (boot_img_cfg->img_segment_info.img_len == 0) {
return 0x0207;
}
/* Start hash here*/
//Sec_Eng_SHA256_Init(&g_sha_ctx, SEC_ENG_SHA_ID0, SEC_ENG_SHA256, g_sha_tmp_buf, g_padding);
//Sec_Eng_SHA_Start(SEC_ENG_SHA_ID0);
device_unregister("dev_check_hash");
sec_hash_sha256_register(0,"dev_check_hash");
dev_check_hash = device_find("dev_check_hash");
if(dev_check_hash){
ret = device_open(dev_check_hash, 0);
if(ret){
//MSG_ERR("hash dev open err\r\n");
return 0xffff;
}
}else{
//MSG_ERR("hash dev find err\r\n");
return 0xffff;
}
} else {
//MSG_ERR("bootheader crc error\r\n");
//blsp_dump_data((uint8_t *)&crc, 4);
return 0x0204;
}
return 0;
}
void hal_boot2_clean_cache(void)
{
}

5
drivers/bl602_driver/hal_drv/src/hal_clock.c
View file

@ -80,12 +80,8 @@ void peripheral_clock_init(void)
#endif
#if defined(BSP_USING_DAC0)
#if BSP_ADC_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_AUPLL
GLB_Set_DAC_CLK(ENABLE, GLB_ADC_CLK_AUDIO_PLL, BSP_DAC_CLOCK_DIV);
#elif BSP_ADC_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK
GLB_Set_DAC_CLK(ENABLE, GLB_ADC_CLK_XCLK, BSP_DAC_CLOCK_DIV);
#endif
#endif
}
uint32_t system_clock_get(enum system_clock_type type)
{
@ -176,6 +172,7 @@ uint32_t peripheral_clock_get(enum peripheral_clock_type type)
#endif
case PERIPHERAL_CLOCK_ADC:
case PERIPHERAL_CLOCK_DAC:
return 32000000;
default:

330
drivers/bl602_driver/hal_drv/src/hal_dac.c Normal file
View file

@ -0,0 +1,330 @@
/**
* @file hal_dac.c
* @brief
*
* Copyright (c) 2021 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#include "hal_dac.h"
#include "hal_dma.h"
#include "hal_clock.h"
#include "bl602_dac.h"
#include "bl602_glb.h"
#include "dac_config.h"
static dac_device_t dacx_device[] = {
#ifdef BSP_USING_DAC0
DAC_CONFIG,
#endif
};
static uint8_t dac_channel_enable_check = 0;
/**
* @brief
*
* @param dev
* @param oflag
* @return int
*/
int dac_open(struct device *dev, uint16_t oflag)
{
dac_device_t *dac_device = (dac_device_t *)dev;
uint8_t dac_div = 0;
uint32_t tmpVal;
uint32_t dac_clk = peripheral_clock_get(PERIPHERAL_CLOCK_DAC);
if ((GLB_GPIO_Get_Fun(GLB_GPIO_PIN_13) == GPIO_FUN_ANALOG) && (dac_device->channels & DAC_CHANNEL_0)) {
dac_channel_enable_check |= DAC_CHANNEL_0;
}
if ((GLB_GPIO_Get_Fun(GLB_GPIO_PIN_14) == GPIO_FUN_ANALOG) && (dac_device->channels & DAC_CHANNEL_1)) {
dac_channel_enable_check |= DAC_CHANNEL_1;
}
if (dac_channel_enable_check == 0) {
return -1;
}
switch (dac_device->sample_freq) {
case DAC_SAMPLE_FREQ_500KHZ:
dac_div = dac_clk / 500000;
break;
case DAC_SAMPLE_FREQ_8KHZ:
dac_div = dac_clk / 8000;
break;
case DAC_SAMPLE_FREQ_16KHZ:
dac_div = dac_clk / 16000;
break;
case DAC_SAMPLE_FREQ_44P1KHZ:
dac_div = dac_clk / 441000;
break;
default:
break;
}
if (dac_div == 1) {
dac_div = DAC_CLK_DIV_1;
} else if (dac_div == 16) {
dac_div = DAC_CLK_DIV_16;
} else if (dac_div == 32) {
dac_div = DAC_CLK_DIV_32;
} else if (dac_div == 64) {
dac_div = DAC_CLK_DIV_64;
} else
return -2;
tmpVal = BL_RD_REG(GLB_BASE, GLB_GPDAC_CTRL);
/*dac vref select*/
if (dac_device->vref == DAC_VREF_EXTERNAL) {
if (GLB_GPIO_Get_Fun(GLB_GPIO_PIN_12) != GPIO_FUN_ANALOG)
return -1;
tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPDAC_REF_SEL);
} else {
tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_GPDAC_REF_SEL);
}
BL_WR_REG(GLB_BASE, GLB_GPDAC_CTRL, tmpVal);
/*dac reset*/
tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_GPDACA_RSTN_ANA);
BL_WR_REG(GLB_BASE, GLB_GPDAC_CTRL, tmpVal);
__NOP();
__NOP();
__NOP();
__NOP();
tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_GPDACB_RSTN_ANA);
BL_WR_REG(GLB_BASE, GLB_GPDAC_CTRL, tmpVal);
__NOP();
__NOP();
__NOP();
__NOP();
/* dac clear reset */
tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPDACA_RSTN_ANA);
tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPDACB_RSTN_ANA);
BL_WR_REG(GLB_BASE, GLB_GPDAC_CTRL, tmpVal);
/* Set DAC div */
tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_MODE, dac_div);
BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal);
/* select source */
tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_CH_A_SEL, GPIP_DAC_ChanA_SRC_REG);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_CH_B_SEL, GPIP_DAC_ChanB_SRC_REG);
BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal);
/* GPIP enable or disable channel */
tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG);
if (dac_channel_enable_check & DAC_CHANNEL_0) {
tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPDAC_EN);
}
if (dac_channel_enable_check & DAC_CHANNEL_1) {
tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPDAC_EN2);
}
BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal);
/* GLB enable or disable channel */
if (dac_channel_enable_check) {
/* a channel */
tmpVal = BL_RD_REG(GLB_BASE, GLB_GPDAC_ACTRL);
tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPDAC_IOA_EN);
tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPDAC_A_EN);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_A_RNG, DAC_REF_RNG_DEFAULT_SELECT);
tmpVal = BL_WR_REG(GLB_BASE, GLB_GPDAC_ACTRL, tmpVal);
}
if (dac_channel_enable_check) {
/* b channel */
tmpVal = BL_RD_REG(GLB_BASE, GLB_GPDAC_BCTRL);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_B_RNG, DAC_REF_RNG_DEFAULT_SELECT);
tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPDAC_IOB_EN);
tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPDAC_B_EN);
tmpVal = BL_WR_REG(GLB_BASE, GLB_GPDAC_BCTRL, tmpVal);
}
/* GPIP disable DMA */
tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_DMA_CONFIG);
tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPDAC_DMA_TX_EN);
BL_WR_REG(GPIP_BASE, GPIP_GPDAC_DMA_CONFIG, tmpVal);
if (oflag & DEVICE_OFLAG_DMA_TX) {
/* GPIP select source */
tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_CH_A_SEL, GPIP_DAC_ChanA_SRC_DMA);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_CH_B_SEL, GPIP_DAC_ChanB_SRC_DMA);
BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal);
/* GPIP enable DMA */
tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_DMA_CONFIG);
if (dac_channel_enable_check == 2) {
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_DMA_FORMAT, GPIP_DAC_DMA_FORMAT_1);
} else {
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_DMA_FORMAT, GPIP_DAC_DMA_FORMAT_0);
}
tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPDAC_DMA_TX_EN);
BL_WR_REG(GPIP_BASE, GPIP_GPDAC_DMA_CONFIG, tmpVal);
}
return 0;
}
/**
* @brief
*
* @param dev
* @return int
*/
int dac_close(struct device *dev)
{
GLB_GPIP_DAC_ChanA_Cfg_Type chCfg = { 0 };
GLB_GPIP_DAC_Cfg_Type dacCfg = { 0 };
GLB_GPIP_DAC_Init(&dacCfg);
GLB_GPIP_DAC_Set_ChanA_Config(&chCfg);
GLB_GPIP_DAC_Set_ChanB_Config((GLB_GPIP_DAC_ChanB_Cfg_Type *)&chCfg);
GPIP_Set_DAC_DMA_TX_Disable();
return 0;
}
/**
* @brief
*
* @param dev
* @param cmd
* @param args
* @return int
*/
int dac_control(struct device *dev, int cmd, void *args)
{
dac_device_t *dac_device = (dac_device_t *)dev;
switch (cmd) {
case DEVICE_CTRL_SET_INT:
break;
case DEVICE_CTRL_CLR_INT:
break;
case DEVICE_CTRL_GET_INT:
/* code */
break;
case DEVICE_CTRL_CONFIG:
/* code */
break;
case DEVICE_CTRL_RESUME:
break;
case DEVICE_CTRL_SUSPEND:
break;
case DEVICE_CTRL_ATTACH_TX_DMA:
dac_device->tx_dma = (struct device *)args;
break;
default:
break;
}
return 0;
}
/**
* @brief
*
* @param dev
* @param pos
* @param buffer
* @param size
* @return int
*/
int dac_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t size)
{
int ret = 0;
enum dac_sample_frequence channel = (enum dac_sample_frequence)pos;
dac_device_t *dac_device = (dac_device_t *)dev;
uint32_t i = 0;
if (dev->oflag & DEVICE_OFLAG_DMA_TX) {
struct device *dma_ch = (struct device *)dac_device->tx_dma;
if (!dma_ch) {
return -1;
}
ret = dma_reload(dma_ch, (uint32_t)buffer, (uint32_t)DMA_ADDR_DAC_TDR, size);
dma_channel_start(dma_ch);
return ret;
} else if (dev->oflag & DEVICE_OFLAG_STREAM_TX) {
if ((channel & DAC_CHANNEL_ALL) == DAC_CHANNEL_ALL) {
for (i = 0; i < size; i++) {
GLB_DAC_Set_ChanA_Value(*((uint16_t *)buffer + i));
GLB_DAC_Set_ChanB_Value(*((uint16_t *)buffer + i));
}
} else if (channel & DAC_CHANNEL_0) {
for (i = 0; i < size; i++) {
GLB_DAC_Set_ChanA_Value(*((uint16_t *)buffer + i));
}
} else if (channel & DAC_CHANNEL_1) {
for (i = 0; i < size; i++) {
GLB_DAC_Set_ChanB_Value(*((uint16_t *)buffer + i));
}
} else {
return -1;
}
return 0;
}
return -1;
}
/**
* @brief
*
* @param index
* @param name
* @return int
*/
int dac_register(enum dac_index_type index, const char *name)
{
struct device *dev;
if (DAC_MAX_INDEX == 0) {
return -DEVICE_EINVAL;
}
dev = &(dacx_device[index].parent);
dev->open = dac_open;
dev->close = dac_close;
dev->control = dac_control;
dev->write = dac_write;
dev->read = NULL;
dev->type = DEVICE_CLASS_DAC;
dev->handle = NULL;
device_register(dev, name);
return 0;
}

8
drivers/bl602_driver/hal_drv/src/hal_dma.c
View file

@ -141,18 +141,18 @@ int dma_control(struct device *dev, int cmd, void *args)
break;
case DMA_CHANNEL_UPDATE:
case DEVICE_CTRL_DMA_CHANNEL_UPDATE:
DMA_LLI_Update(dma_device->ch, (uint32_t)args);
break;
case DMA_CHANNEL_GET_STATUS:
case DEVICE_CTRL_DMA_CHANNEL_GET_STATUS:
return DMA_Channel_Is_Busy(dma_device->ch);
case DMA_CHANNEL_START:
case DEVICE_CTRL_DMA_CHANNEL_START:
DMA_Channel_Enable(dma_device->ch);
break;
case DMA_CHANNEL_STOP:
case DEVICE_CTRL_DMA_CHANNEL_STOP:
DMA_Channel_Disable(dma_device->ch);
break;
case DEVICE_CTRL_DMA_CONFIG_SI: {

15
drivers/bl602_driver/hal_drv/src/hal_flash.c
View file

@ -27,8 +27,22 @@
#include "bl602_sf_cfg_ext.h"
#include "hal_flash.h"
static uint32_t g_jedec_id = 0;
static SPI_Flash_Cfg_Type g_flash_cfg;
/**
* @brief flash_get_jedecid
*
* @return BL_Err_Type
*/
uint32_t flash_get_jedecid(void)
{
uint32_t jid = 0;
jid = ((g_jedec_id&0xff)<<16) + (g_jedec_id&0xff00) + ((g_jedec_id&0xff0000)>>16);
return jid;
}
/**
* @brief flash_get_cfg
*
@ -93,6 +107,7 @@ static BL_Err_Type ATTR_TCM_SECTION flash_config_init(SPI_Flash_Cfg_Type *p_flas
SFlash_GetJedecId(p_flash_cfg, (uint8_t *)&jid);
arch_memcpy(jedec_id, (uint8_t *)&jid, 3);
jid &= 0xFFFFFF;
g_jedec_id = jid;
ret = SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(jid, p_flash_cfg);
if (ret == SUCCESS) {
p_flash_cfg->mid = (jid & 0xff);

4
drivers/bl602_driver/hal_drv/src/hal_uart.c
View file

@ -385,14 +385,14 @@ void uart_isr(uart_device_t *handle)
/* Rx fifo ready interrupt,auto-cleared when data is popped */
if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_FIFO_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_FIFO_MASK)) {
uint8_t buffer[UART_FIFO_MAX_LEN];
len = UART_ReceiveData(handle->id, buffer, handle->fifo_threshold);
len = UART_ReceiveData(handle->id, buffer, UART_FIFO_MAX_LEN);
handle->parent.callback(&handle->parent, &buffer[0], len, UART_EVENT_RX_FIFO);
}
/* Rx time-out interrupt */
if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_RTO_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_RTO_MASK)) {
uint8_t buffer[UART_FIFO_MAX_LEN];
len = UART_ReceiveData(handle->id, buffer, handle->fifo_threshold);
len = UART_ReceiveData(handle->id, buffer, UART_FIFO_MAX_LEN);
handle->parent.callback(&handle->parent, &buffer[0], len, UART_EVENT_RTO);
BL_WR_REG(UARTx, UART_INT_CLEAR, 0x10);
}

3
drivers/bl602_driver/startup/system_bl602.c
View file

@ -79,11 +79,8 @@ void SystemInit(void)
__enable_irq();
}
/*identify flash config automaticly*/
extern BL_Err_Type flash_init(void);
void System_Post_Init(void)
{
PDS_Trim_RC32M();
HBN_Trim_RC32K();
flash_init();
}

31
drivers/bl602_driver/std_drv/src/bl602_hbn.c
View file

@ -1301,7 +1301,7 @@ BL_Err_Type HBN_Set_RTC_Timer(HBN_RTC_INT_Delay_Type delay, uint32_t compValLow,
}
/****************************************************************************/ /**
* @brief HBN get RTC timer count value
* @brief HBN get RTC async timer count value
*
* @param valLow: RTC count value pointer for low 32 bits
* @param valHigh: RTC count value pointer for high 8 bits
@ -1309,7 +1309,7 @@ BL_Err_Type HBN_Set_RTC_Timer(HBN_RTC_INT_Delay_Type delay, uint32_t compValLow,
* @return SUCCESS or ERROR
*
*******************************************************************************/
BL_Err_Type HBN_Get_RTC_Timer_Val(uint32_t *valLow, uint32_t *valHigh)
static BL_Err_Type HBN_Get_RTC_Timer_Async_Val(uint32_t *valLow, uint32_t *valHigh)
{
uint32_t tmpVal;
@ -1327,6 +1327,33 @@ BL_Err_Type HBN_Get_RTC_Timer_Val(uint32_t *valLow, uint32_t *valHigh)
return SUCCESS;
}
/****************************************************************************/ /**
* @brief HBN get RTC timer count value
*
* @param valLow: RTC count value pointer for low 32 bits
* @param valHigh: RTC count value pointer for high 8 bits
*
* @return SUCCESS or ERROR
*
*******************************************************************************/
BL_Err_Type HBN_Get_RTC_Timer_Val(uint32_t *valLow, uint32_t *valHigh)
{
uint32_t tmpValLow, tmpValHigh, tmpValLow1, tmpValHigh1;
uint64_t val, val1;
do {
HBN_Get_RTC_Timer_Async_Val(&tmpValLow, &tmpValHigh);
val = ((uint64_t)tmpValHigh << 32) | ((uint64_t)tmpValLow);
HBN_Get_RTC_Timer_Async_Val(&tmpValLow1, &tmpValHigh1);
val1 = ((uint64_t)tmpValHigh1 << 32) | ((uint64_t)tmpValLow1);
} while (val1 < val);
*valLow = tmpValLow1;
*valHigh = tmpValHigh1;
return SUCCESS;
}
/****************************************************************************/ /**
* @brief HBN clear RTC timer interrupt,this function must be called to clear delayed rtc IRQ
*

13
drivers/bl602_driver/std_drv/src/bl602_sf_cfg_ext.c
View file

@ -650,6 +650,11 @@ static const ATTR_TCM_CONST_SECTION Flash_Info_t flashInfos[]={
//.name="GD_25Q64E_64_33",
.cfg=&flashCfg_XM25QH16,
},
{
.jedecID=0x1840C8,
//.name="GD_25Q127C_128_33",
.cfg=&flashCfg_XM25QH16,
},
{
.jedecID=0x176085,
//.name="Puya_P25Q64H_64_33",
@ -670,6 +675,11 @@ static const ATTR_TCM_CONST_SECTION Flash_Info_t flashInfos[]={
//.name="TH_25Q80HB",
.cfg=&flashCfg_FM_25Q08,
},
{
.jedecID=0x1870EF,
//.name="W25Q128JV_128_33",
.cfg=&flashCfg_XM25QH16,
},
};
/*@} end of group SF_CFG_EXT_Private_Variables */
@ -704,10 +714,11 @@ BL_Err_Type ATTR_TCM_SECTION SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(uint32_t flashID
uint32_t i;
uint8_t buf[sizeof(SPI_Flash_Cfg_Type)+8];
uint32_t crc,*pCrc;
char flashCfgMagic[] = "FCFG";
if(flashID==0){
XIP_SFlash_Read_Via_Cache_Need_Lock(8+BL602_FLASH_XIP_BASE,buf,sizeof(SPI_Flash_Cfg_Type)+8);
if(BL602_MemCmp(buf,BFLB_FLASH_CFG_MAGIC,4)==0){
if(BL602_MemCmp(buf,flashCfgMagic,4)==0){
crc=BFLB_Soft_CRC32((uint8_t *)buf+4,sizeof(SPI_Flash_Cfg_Type));
pCrc=(uint32_t *)(buf+4+sizeof(SPI_Flash_Cfg_Type));
if(*pCrc==crc){

4
drivers/bl602_driver/std_drv/src/bl602_spi.c
View file

@ -323,8 +323,8 @@ BL_Err_Type SPI_FifoConfig(SPI_ID_Type spiNo, SPI_FifoCfg_Type *fifoCfg)
/* Set fifo threshold value */
tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_1);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_TX_FIFO_TH, fifoCfg->txFifoThreshold - 1);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_RX_FIFO_TH, fifoCfg->rxFifoThreshold - 1);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_TX_FIFO_TH, fifoCfg->txFifoThreshold);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_RX_FIFO_TH, fifoCfg->rxFifoThreshold);
BL_WR_REG(SPIx, SPI_FIFO_CONFIG_1, tmpVal);
/* Enable or disable dma function */

4
drivers/bl602_driver/std_drv/src/bl602_uart.c
View file

@ -330,9 +330,9 @@ BL_Err_Type UART_FifoConfig(UART_ID_Type uartId, UART_FifoCfg_Type *fifoCfg)
/* Deal with uart fifo configure register */
tmpVal = BL_RD_REG(UARTx, UART_FIFO_CONFIG_1);
/* Configure dma tx fifo threshold */
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, UART_TX_FIFO_TH, fifoCfg->txFifoDmaThreshold - 1);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, UART_TX_FIFO_TH, fifoCfg->txFifoDmaThreshold);
/* Configure dma rx fifo threshold */
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, UART_RX_FIFO_TH, fifoCfg->rxFifoDmaThreshold - 1);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, UART_RX_FIFO_TH, fifoCfg->rxFifoDmaThreshold);
/* Write back */
BL_WR_REG(UARTx, UART_FIFO_CONFIG_1, tmpVal);

52
drivers/bl602_driver/std_drv/src/bl602_xip_sflash.c
View file

@ -341,6 +341,58 @@ BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Read_Via_Cache_Need_Lock(uint32_t addr,
}
/****************************************************************************/ /**
* @return 0
*
*******************************************************************************/
__WEAK
int ATTR_TCM_SECTION XIP_SFlash_Read_With_Lock(SPI_Flash_Cfg_Type *pFlashCfg,uint32_t addr, uint8_t *dst, int len)
{
__disable_irq();
XIP_SFlash_Read_Need_Lock(pFlashCfg, addr, dst, len);
__enable_irq();
return 0;
}
/****************************************************************************//**
* @brief Program flash one region with lock
*
* @param pFlashCfg: Flash config pointer
* @param addr: Start address to be programed
* @param src: Data pointer to be programed
* @param len: Data length to be programed
*
* @return 0
*
*******************************************************************************/
__WEAK
int ATTR_TCM_SECTION XIP_SFlash_Write_With_Lock(SPI_Flash_Cfg_Type *pFlashCfg,uint32_t addr, uint8_t *src, int len)
{
__disable_irq();
XIP_SFlash_Write_Need_Lock(pFlashCfg, addr, src, len);
__enable_irq();
return 0;
}
/****************************************************************************//**
* @brief Erase flash one region with lock
*
* @param pFlashCfg: Flash config pointer
* @param addr: Start address to be erased
* @param len: Data length to be erased
*
* @return 0
*
*******************************************************************************/
__WEAK
int ATTR_TCM_SECTION XIP_SFlash_Erase_With_Lock(SPI_Flash_Cfg_Type *pFlashCfg,uint32_t addr, int len)
{
__disable_irq();
XIP_SFlash_Erase_Need_Lock(pFlashCfg, addr, addr + len - 1);
__enable_irq();
return 0;
}
/****************************************************************************//**
* @brief XIP SFlash option save
*
* @param aesEnable: AES enable status pointer

275
drivers/bl602_driver/std_drv/src/bl602_xip_sflash_ext.c
View file

@ -64,6 +64,9 @@
* @{
*/
static SPI_Flash_Cfg_Type flashCfg;
static uint8_t aesEnable;
/*@} end of group XIP_SFLASH_EXT_Private_Variables */
/** @defgroup XIP_SFLASH_EXT_Global_Variables
@ -88,7 +91,44 @@
* @{
*/
/****************************************************************************/ /**
/****************************************************************************//**
* @brief Save flash controller state
*
* @param pFlashCfg: Flash config pointer
* @param offset: CPU XIP flash offset pointer
*
* @return SUCCESS or ERROR
*
*******************************************************************************/
__WEAK
BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_State_Save_Ext(SPI_Flash_Cfg_Type *pFlashCfg,uint32_t *offset)
{
/* XIP_SFlash_Delay */
volatile uint32_t i=32*2;
while(i--);
SF_Ctrl_Set_Owner(SF_CTRL_OWNER_SAHB);
/* Exit form continous read for accepting command */
SFlash_Reset_Continue_Read(pFlashCfg);
/* Send software reset command(80bv has no this command)to deburst wrap for ISSI like */
SFlash_Software_Reset(pFlashCfg);
/* For disable command that is setting register instaed of send command, we need write enable */
SFlash_DisableBurstWrap(pFlashCfg);
if ((pFlashCfg->ioMode & 0x0f) == SF_CTRL_QO_MODE || (pFlashCfg->ioMode & 0x0f) == SF_CTRL_QIO_MODE) {
/* Enable QE again in case reset command make it reset */
SFlash_Qspi_Enable(pFlashCfg);
}
/* Deburst again to make sure */
SFlash_DisableBurstWrap(pFlashCfg);
/* Clear offset setting*/
*offset=SF_Ctrl_Get_Flash_Image_Offset();
SF_Ctrl_Set_Flash_Image_Offset(0);
return SUCCESS;
}
/****************************************************************************//**
* @brief Restore flash controller state
*
* @param pFlashCfg: Flash config pointer
@ -137,15 +177,17 @@ BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Erase_Need_Lock_Ext(SPI_Flash_Cfg_Type *
{
BL_Err_Type stat;
uint32_t offset;
SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode & 0xf;
SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode&0xf;
stat = XIP_SFlash_State_Save(pFlashCfg, &offset);
if (stat != SUCCESS) {
SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32);
} else {
stat = SFlash_Erase(pFlashCfg, startaddr, endaddr);
XIP_SFlash_State_Restore_Ext(pFlashCfg, offset);
XIP_SFlash_Opt_Enter(&aesEnable);
stat=XIP_SFlash_State_Save(pFlashCfg,&offset);
if(stat!=SUCCESS){
SFlash_Set_IDbus_Cfg(pFlashCfg,ioMode,1,0,32);
}else{
stat=SFlash_Erase(pFlashCfg,startaddr,endaddr);
XIP_SFlash_State_Restore_Ext(pFlashCfg,offset);
}
XIP_SFlash_Opt_Exit(aesEnable);
return stat;
}
@ -166,15 +208,17 @@ BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Write_Need_Lock_Ext(SPI_Flash_Cfg_Type *
{
BL_Err_Type stat;
uint32_t offset;
SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode & 0xf;
SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode&0xf;
stat = XIP_SFlash_State_Save(pFlashCfg, &offset);
if (stat != SUCCESS) {
SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32);
} else {
stat = SFlash_Program(pFlashCfg, ioMode, addr, data, len);
XIP_SFlash_State_Restore_Ext(pFlashCfg, offset);
XIP_SFlash_Opt_Enter(&aesEnable);
stat=XIP_SFlash_State_Save(pFlashCfg,&offset);
if(stat!=SUCCESS){
SFlash_Set_IDbus_Cfg(pFlashCfg,ioMode,1,0,32);
}else{
stat= SFlash_Program(pFlashCfg,ioMode,addr,data,len);
XIP_SFlash_State_Restore_Ext(pFlashCfg,offset);
}
XIP_SFlash_Opt_Exit(aesEnable);
return stat;
}
@ -195,15 +239,17 @@ BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Read_Need_Lock_Ext(SPI_Flash_Cfg_Type *p
{
BL_Err_Type stat;
uint32_t offset;
SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode & 0xf;
SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode&0xf;
stat = XIP_SFlash_State_Save(pFlashCfg, &offset);
if (stat != SUCCESS) {
SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32);
} else {
stat = SFlash_Read(pFlashCfg, ioMode, 0, addr, data, len);
XIP_SFlash_State_Restore_Ext(pFlashCfg, offset);
XIP_SFlash_Opt_Enter(&aesEnable);
stat=XIP_SFlash_State_Save(pFlashCfg,&offset);
if(stat!=SUCCESS){
SFlash_Set_IDbus_Cfg(pFlashCfg,ioMode,1,0,32);
}else{
stat=SFlash_Read(pFlashCfg,ioMode,0,addr, data,len);
XIP_SFlash_State_Restore_Ext(pFlashCfg,offset);
}
XIP_SFlash_Opt_Exit(aesEnable);
return stat;
}
@ -345,6 +391,191 @@ BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_RCV_Enable_Need_Lock(SPI_Flash_Cfg_Type
return stat;
}
/****************************************************************************//**
* @brief Read data from flash with lock
*
* @param pFlashCfg: Flash config pointer
* @param addr: flash read start address
* @param dst: data pointer to store data read from flash
* @param len: data length to read
*
* @return 0
*
*******************************************************************************/
__WEAK
int ATTR_TCM_SECTION XIP_SFlash_Read_With_Lock_Ext(SPI_Flash_Cfg_Type *pFlashCfg,uint32_t addr, uint8_t *dst, int len)
{
__disable_irq();
XIP_SFlash_Read_Need_Lock_Ext(pFlashCfg, addr, dst, len);
__enable_irq();
return 0;
}
/****************************************************************************//**
* @brief Program flash one region with lock
*
* @param pFlashCfg: Flash config pointer
* @param addr: Start address to be programed
* @param src: Data pointer to be programed
* @param len: Data length to be programed
*
* @return 0
*
*******************************************************************************/
__WEAK
int ATTR_TCM_SECTION XIP_SFlash_Write_With_Lock_Ext(SPI_Flash_Cfg_Type *pFlashCfg,uint32_t addr, uint8_t *src, int len)
{
__disable_irq();
XIP_SFlash_Write_Need_Lock_Ext(pFlashCfg, addr, src, len);
__enable_irq();
return 0;
}
/****************************************************************************//**
* @brief Erase flash one region with lock
*
* @param pFlashCfg: Flash config pointer
* @param addr: Start address to be erased
* @param len: Data length to be erased
*
* @return 0
*
*******************************************************************************/
__WEAK
int ATTR_TCM_SECTION XIP_SFlash_Erase_With_Lock_Ext(SPI_Flash_Cfg_Type *pFlashCfg,uint32_t addr, int len)
{
__disable_irq();
XIP_SFlash_Erase_Need_Lock_Ext(pFlashCfg, addr, addr + len - 1);
__enable_irq();
return 0;
}
/****************************************************************************//**
* @brief Clear flash status register with lock
*
* @param pFlashCfg: Flash config pointer
*
* @return 0
*
*******************************************************************************/
__WEAK
int ATTR_TCM_SECTION XIP_SFlash_Clear_Status_Register_With_Lock(SPI_Flash_Cfg_Type *pFlashCfg)
{
__disable_irq();
XIP_SFlash_Clear_Status_Register_Need_Lock(pFlashCfg);
__enable_irq();
return 0;
}
/****************************************************************************//**
* @brief Sflash enable RCV mode to recovery for erase while power drop with lock
*
* @param pFlashCfg: Flash config pointer
* @param rCmd: Read RCV register cmd
* @param wCmd: Write RCV register cmd
* @param bitPos: RCV register bit pos
*
* @return 0
*
*******************************************************************************/
__WEAK
int ATTR_TCM_SECTION XIP_SFlash_RCV_Enable_With_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t rCmd, uint8_t wCmd, uint8_t bitPos)
{
__disable_irq();
XIP_SFlash_RCV_Enable_Need_Lock(pFlashCfg, rCmd, wCmd, bitPos);
__enable_irq();
return 0;
}
/****************************************************************************//**
* @brief Read data from flash with lock
*
* @param pFlashCfg:Flash config pointer
*
* @return SUCCESS or ERROR
*
*******************************************************************************/
__WEAK
BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Init(SPI_Flash_Cfg_Type *pFlashCfg)
{
uint32_t ret;
if(pFlashCfg==NULL){
/* Get flash config identify */
XIP_SFlash_Opt_Enter(&aesEnable);
ret=SF_Cfg_Flash_Identify_Ext(1,1,0,0,&flashCfg);
XIP_SFlash_Opt_Exit(aesEnable);
if((ret&BFLB_FLASH_ID_VALID_FLAG)==0){
return ERROR;
}
}else{
memcpy(&flashCfg,pFlashCfg,sizeof(flashCfg));
}
return SUCCESS;
}
/****************************************************************************//**
* @brief Read data from flash with lock
*
* @param addr: flash read start address
* @param dst: data pointer to store data read from flash
* @param len: data length to read
*
* @return 0
*
*******************************************************************************/
__WEAK
int ATTR_TCM_SECTION XIP_SFlash_Read(uint32_t addr, uint8_t *dst, int len)
{
__disable_irq();
XIP_SFlash_Opt_Enter(&aesEnable);
XIP_SFlash_Read_Need_Lock_Ext(&flashCfg, addr, dst, len);
XIP_SFlash_Opt_Exit(aesEnable);
__enable_irq();
return 0;
}
/****************************************************************************//**
* @brief Program flash one region with lock
*
* @param addr: Start address to be programed
* @param src: Data pointer to be programed
* @param len: Data length to be programed
*
* @return 0
*
*******************************************************************************/
__WEAK
int ATTR_TCM_SECTION XIP_SFlash_Write(uint32_t addr, uint8_t *src, int len)
{
__disable_irq();
XIP_SFlash_Opt_Enter(&aesEnable);
XIP_SFlash_Write_Need_Lock_Ext(&flashCfg, addr, src, len);
XIP_SFlash_Opt_Exit(aesEnable);
__enable_irq();
return 0;
}
/****************************************************************************//**
* @brief Erase flash one region with lock
*
* @param addr: Start address to be erased
* @param len: Data length to be erased
*
* @return 0
*
*******************************************************************************/
__WEAK
int ATTR_TCM_SECTION XIP_SFlash_Erase(uint32_t addr, int len)
{
__disable_irq();
XIP_SFlash_Opt_Enter(&aesEnable);
XIP_SFlash_Erase_Need_Lock_Ext(&flashCfg, addr, addr + len - 1);
XIP_SFlash_Opt_Exit(aesEnable);
__enable_irq();
return 0;
}
/*@} end of group XIP_SFLASH_EXT_Public_Functions */
/*@} end of group XIP_SFLASH_EXT */

131
drivers/bl702_driver/hal_drv/inc/hal_boot2.h
View file

@ -44,6 +44,7 @@ extern "C"{
#include "bl702_sflash.h"
#include "bl702_glb.h"
#define HAL_EFUSE_CPU_MAX 2
#define HAL_EFUSE_PK_HASH_SIZE 256 / 8
@ -58,6 +59,22 @@ extern "C"{
#define HAL_BOOT2_SUPPORT_EFLASH_LOADER_RAM 0 /* 1 support decompress, 0 not support */
#define HAL_BOOT2_SUPPORT_EFLASH_LOADER_FLASH 1 /* 1 support decompress, 0 not support */
#define HAL_BOOT2_FW_IMG_OFFSET_AFTER_HEADER 4*1024
#define HAL_BOOT2_HASH_SIZE 256 / 8
#define HAL_BOOT2_ECC_KEYXSIZE 256 / 8
#define HAL_BOOT2_ECC_KEYYSIZE 256 / 8
#define HAL_BOOT2_SIGN_MAXSIZE 2048 / 8
#define HAL_BOOT2_DEADBEEF_VAL 0xdeadbeef
#define HAL_BOOT2_CPU_MAX 1
#define HAL_BOOT2_CPU0_MAGIC "BFNP"
#define HAL_BOOT2_CPU1_MAGIC "BFAP"
typedef struct
{
uint8_t encrypted[HAL_EFUSE_CPU_MAX];
@ -95,6 +112,116 @@ typedef struct
uint32_t crc32;
} hal_flash_config;
struct hal_bootheader_t
{
uint32_t magicCode; /*'BFXP'*/
uint32_t rivison;
hal_flash_config flash_cfg;
hal_pll_config clk_cfg;
__PACKED_UNION
{
__PACKED_STRUCT
{
uint32_t sign : 2; /* [1: 0] for sign*/
uint32_t encrypt_type : 2; /* [3: 2] for encrypt */
uint32_t key_sel : 2; /* [5: 4] for key sel in boot interface*/
uint32_t rsvd6_7 : 2; /* [7: 6] for encrypt*/
uint32_t no_segment : 1; /* [8] no segment info */
uint32_t cache_enable : 1; /* [9] for cache */
uint32_t notLoadInBoot : 1; /* [10] not load this img in bootrom */
uint32_t aes_region_lock : 1; /* [11] aes region lock */
uint32_t cache_way_disable : 4; /* [15: 12] cache way disable info*/
uint32_t crcIgnore : 1; /* [16] ignore crc */
uint32_t hash_ignore : 1; /* [17] hash crc */
uint32_t halt_cpu1 : 1; /* [18] halt ap */
uint32_t rsvd19_31 : 13; /* [31:19] rsvd */
}
bval;
uint32_t wval;
}
bootCfg;
__PACKED_UNION
{
uint32_t segment_cnt;
uint32_t img_len;
}
img_segment_info;
uint32_t bootEntry; /* entry point of the image*/
__PACKED_UNION
{
uint32_t ram_addr;
uint32_t flash_offset;
}
img_start;
uint8_t hash[HAL_BOOT2_HASH_SIZE]; /*hash of the image*/
uint32_t rsv1;
uint32_t rsv2;
uint32_t crc32;
} ;
typedef struct
{
uint8_t encrypt_type;
uint8_t sign_type;
uint8_t key_sel;
uint8_t img_valid;
uint8_t no_segment;
uint8_t cache_enable;
uint8_t cache_way_disable;
uint8_t hash_ignore;
uint8_t aes_region_lock;
uint8_t halt_cpu1;
uint8_t cpu_type;
uint8_t r[1];
__PACKED_UNION
{
uint32_t segment_cnt;
uint32_t img_len;
}
img_segment_info;
uint32_t msp_val;
uint32_t entry_point;
__PACKED_UNION
{
uint32_t ram_addr;
uint32_t flash_offset;
}
img_start;
uint32_t sig_len;
uint32_t sig_len2;
uint32_t deal_len;
uint32_t max_input_len;
uint8_t img_hash[HAL_BOOT2_HASH_SIZE]; //hash of the whole (all)images
uint8_t aes_iv[16 + 4]; //iv in boot header
uint8_t eckye_x[HAL_BOOT2_ECC_KEYXSIZE]; //ec key in boot header
uint8_t eckey_y[HAL_BOOT2_ECC_KEYYSIZE]; //ec key in boot header
uint8_t eckey_x2[HAL_BOOT2_ECC_KEYXSIZE]; //ec key in boot header
uint8_t eckey_y2[HAL_BOOT2_ECC_KEYYSIZE]; //ec key in boot header
uint8_t signature[HAL_BOOT2_SIGN_MAXSIZE]; //signature in boot header
uint8_t signature2[HAL_BOOT2_SIGN_MAXSIZE]; //signature in boot header
} boot2_image_config;
extern boot2_efuse_hw_config g_efuse_cfg;
extern uint8_t g_ps_mode;
extern uint32_t g_user_hash_ignored;
extern struct device *dev_check_hash;
uint32_t hal_boot2_custom(void);
void hal_boot2_reset_sec_eng(void);
void hal_boot2_sw_system_reset(void);
@ -102,7 +229,7 @@ void hal_boot2_set_psmode_status(uint32_t flag);
uint32_t hal_boot2_get_psmode_status(void);
uint32_t hal_boot2_get_user_fw(void);
void hal_boot2_clr_user_fw(void);
void hal_boot2_get_efuse_cfg(boot2_efuse_hw_config *g_efuse_cfg);
void hal_boot2_get_efuse_cfg(boot2_efuse_hw_config *efuse_cfg);
int32_t hal_boot2_get_clk_cfg(hal_pll_config *cfg);
void hal_boot2_sboot_finish(void);
void hal_boot2_uart_gpio_init(void);
@ -112,6 +239,8 @@ void hal_boot2_debug_usb_port_init(void);
#endif
void hal_boot2_debug_uart_gpio_deinit(void);
int32_t hal_boot_parse_bootheader(boot2_image_config *boot_img_cfg, uint8_t *data);
void hal_boot2_clean_cache(void);
#ifdef __cplusplus
}

22
drivers/bl702_driver/hal_drv/inc/hal_dma.h
View file

@ -31,12 +31,12 @@ extern "C" {
#include "drv_device.h"
#include "bl702_config.h"
#define DMA_CHANNEL_GET_STATUS 0x10
#define DMA_CHANNEL_START 0x11
#define DMA_CHANNEL_STOP 0x12
#define DMA_CHANNEL_UPDATE 0x13
#define DEVICE_CTRL_DMA_CONFIG_SI 0x14
#define DEVICE_CTRL_DMA_CONFIG_DI 0x15
#define DEVICE_CTRL_DMA_CHANNEL_GET_STATUS 0x10
#define DEVICE_CTRL_DMA_CHANNEL_START 0x11
#define DEVICE_CTRL_DMA_CHANNEL_STOP 0x12
#define DEVICE_CTRL_DMA_CHANNEL_UPDATE 0x13
#define DEVICE_CTRL_DMA_CONFIG_SI 0x14
#define DEVICE_CTRL_DMA_CONFIG_DI 0x15
enum dma_index_type {
#ifdef BSP_USING_DMA0_CH0
@ -66,10 +66,10 @@ enum dma_index_type {
DMA_MAX_INDEX
};
#define dma_channel_start(dev) device_control(dev, DMA_CHANNEL_START, NULL)
#define dma_channel_stop(dev) device_control(dev, DMA_CHANNEL_STOP, NULL)
#define dma_channel_update(dev, list) device_control(dev, DMA_CHANNEL_UPDATE, list)
#define dma_channel_check_busy(dev) device_control(dev, DMA_CHANNEL_GET_STATUS, NULL)
#define dma_channel_start(dev) device_control(dev, DEVICE_CTRL_DMA_CHANNEL_START, NULL)
#define dma_channel_stop(dev) device_control(dev, DEVICE_CTRL_DMA_CHANNEL_STOP, NULL)
#define dma_channel_update(dev, list) device_control(dev, DEVICE_CTRL_DMA_CHANNEL_UPDATE, list)
#define dma_channel_check_busy(dev) device_control(dev, DEVICE_CTRL_DMA_CHANNEL_GET_STATUS, NULL)
#define DMA_LLI_ONCE_MODE 0
#define DMA_LLI_CYCLE_MODE 1
@ -96,7 +96,7 @@ enum dma_index_type {
#define DMA_ADDR_SPI_RDR (0x4000A200 + 0x8C)
#define DMA_ADDR_I2S_TDR (0x4000AA00 + 0x88)
#define DMA_ADDR_I2S_RDR (0x4000AA00 + 0x8C)
#define DMA_ADDR_ADC0_DR (0x40002000 + 0x04)
#define DMA_ADDR_ADC_RDR (0x40002000 + 0x04)
#define DMA_ADDR_DAC_TDR (0x40002000 + 0X48)
#define DMA_REQUEST_NONE 0x00000000 /*!< DMA request peripheral:None */

4
drivers/bl702_driver/hal_drv/inc/hal_flash.h
View file

@ -28,10 +28,13 @@ extern "C"{
#endif
#include "hal_common.h"
#include "bl702_sflash.h"
#include "bl702_sflash_ext.h"
#define FLASH_NOT_DETECT 0x10
#define BL_FLASH_XIP_BASE BL702_FLASH_XIP_BASE
uint32_t flash_get_jedecid(void);
BL_Err_Type flash_init(void);
BL_Err_Type flash_read_jedec_id(uint8_t *data);
BL_Err_Type flash_read_via_xip(uint32_t addr, uint8_t *data, uint32_t len);
@ -40,6 +43,7 @@ BL_Err_Type flash_write(uint32_t addr, uint8_t *data, uint32_t len);
BL_Err_Type flash_erase(uint32_t startaddr, uint32_t len);
BL_Err_Type flash_set_cache(uint8_t cont_read, uint8_t cache_enable, uint8_t cache_way_disable, uint32_t flash_offset);
BL_Err_Type flash_get_cfg(uint8_t **cfg_addr, uint32_t *len);
BL_Err_Type flash_write_protect_set(SFlash_Protect_Kh25v40_Type protect);
#ifdef __cplusplus
}
#endif

4
drivers/bl702_driver/hal_drv/inc/hal_pm_util.h
View file

@ -29,7 +29,5 @@
#define ATTR_PDS_RAM_CONST_SECTION __attribute__((section(".pds_ram_data")))
uint32_t hal_pds_enter_with_time_compensation(uint32_t pdsLevel, uint32_t pdsSleepCycles);
void pm_set_tcm_recovery_callback(void (*tcm_recovery_cb)(void));
void pm_set_board_recovery_callback(void (*board_recovery_cb)(void));
void pm_set_hardware_recovery_callback(void (*hardware_recovery_cb)(void));
#endif

4
drivers/bl702_driver/hal_drv/inc/hal_sec_ecdsa.h
View file

@ -24,13 +24,15 @@
#define __HAL_SEC_ECDSA__H__
#ifdef __cplusplus
extern "C"{
extern "C" {
#endif
#include "hal_common.h"
typedef enum {
ECP_SECP256R1 = 0,
ECP_SECP256K1 = 1,
ECP_TYPE_MAX = 2,
} sec_ecp_type;
typedef struct

6
drivers/bl702_driver/hal_drv/src/hal_adc.c
View file

@ -380,16 +380,17 @@ void adc_isr(adc_device_t *handle)
}
if (ADC_GetIntStatus(ADC_INT_FIFO_UNDERRUN) == SET && ADC_IntGetMask(ADC_INT_FIFO_UNDERRUN) == UNMASK) {
handle->parent.callback(&handle->parent, NULL, 0, ADC_EVENT_UNDERRUN);
ADC_IntClr(ADC_INT_FIFO_UNDERRUN);
handle->parent.callback(&handle->parent, NULL, 0, ADC_EVENT_UNDERRUN);
}
if (ADC_GetIntStatus(ADC_INT_FIFO_OVERRUN) == SET && ADC_IntGetMask(ADC_INT_FIFO_OVERRUN) == UNMASK) {
handle->parent.callback(&handle->parent, NULL, 0, ADC_EVENT_OVERRUN);
ADC_IntClr(ADC_INT_FIFO_OVERRUN);
handle->parent.callback(&handle->parent, NULL, 0, ADC_EVENT_OVERRUN);
}
if (ADC_GetIntStatus(ADC_INT_FIFO_READY) == SET && ADC_IntGetMask(ADC_INT_FIFO_READY) == UNMASK) {
ADC_IntClr(ADC_INT_FIFO_READY);
uint32_t adc_count = ADC_Get_FIFO_Count();
uint32_t adc_fifo_val[32];
adc_channel_val_t adc_parse_val[32];
@ -398,7 +399,6 @@ void adc_isr(adc_device_t *handle)
}
ADC_Parse_Result(adc_fifo_val, adc_count, (ADC_Result_Type *)adc_parse_val);
handle->parent.callback(&handle->parent, (void *)adc_parse_val, adc_count, ADC_EVENT_FIFO);
ADC_IntClr(ADC_INT_FIFO_READY);
}
}
#ifdef BSP_USING_ADC0

158
drivers/bl702_driver/hal_drv/src/hal_boot2.c
View file

@ -6,6 +6,8 @@
#include "bl702_xip_sflash.h"
#include "tzc_sec_reg.h"
#include "hal_gpio.h"
#include "softcrc.h"
#include "hal_sec_hash.h"
/**
* @brief boot2 custom
@ -26,7 +28,7 @@ uint32_t hal_boot2_custom(void)
* @param
* @return None
*/
void hal_boot2_get_efuse_cfg(boot2_efuse_hw_config *g_efuse_cfg)
void hal_boot2_get_efuse_cfg(boot2_efuse_hw_config *efuse_cfg)
{
uint32_t tmp;
uint32_t rootClk;
@ -41,13 +43,13 @@ void hal_boot2_get_efuse_cfg(boot2_efuse_hw_config *g_efuse_cfg)
HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_RC32M);
/* Get sign and aes type*/
EF_Ctrl_Read_Secure_Boot((EF_Ctrl_Sign_Type *)g_efuse_cfg->sign, (EF_Ctrl_SF_AES_Type *)g_efuse_cfg->encrypted);
EF_Ctrl_Read_Secure_Boot((EF_Ctrl_Sign_Type *)efuse_cfg->sign, (EF_Ctrl_SF_AES_Type *)efuse_cfg->encrypted);
/* Get hash:aes key slot 0 and slot1*/
EF_Ctrl_Read_AES_Key(0, (uint32_t *)g_efuse_cfg->pk_hash_cpu0, 8);
EF_Ctrl_Read_Chip_ID(g_efuse_cfg->chip_id);
EF_Ctrl_Read_AES_Key(0, (uint32_t *)efuse_cfg->pk_hash_cpu0, 8);
EF_Ctrl_Read_Chip_ID(efuse_cfg->chip_id);
/* Get HBN check sign config */
EF_Ctrl_Read_Sw_Usage(0, &tmp);
g_efuse_cfg->hbn_check_sign = (tmp >> 22) & 0x01;
efuse_cfg->hbn_check_sign = (tmp >> 22) & 0x01;
/* restore bclk fclk div and root clock sel */
GLB_Set_System_CLK_Div(hdiv, bdiv);
@ -203,3 +205,149 @@ void hal_boot2_debug_uart_gpio_deinit(void)
GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_UART1);
GLB_UART_Sig_Swap_Set(UART_SIG_SWAP_NONE);
}
/****************************************************************************/ /**
* @brief Check if the input public key is the same as burned in the efuse
*
* @param g_boot_img_cfg: Boot image config pointer
* @param data: Image data pointer
*
* @return boot_error_code type
*
*******************************************************************************/
int32_t hal_boot_parse_bootheader(boot2_image_config *boot_img_cfg, uint8_t *data)
{
struct hal_bootheader_t *header = (struct hal_bootheader_t *)data;
uint32_t crc;
uint32_t crc_pass = 0;
uint32_t i = 0;
uint32_t *phash = (uint32_t *)header->hash;
int32_t ret;
if (header->bootCfg.bval.crcIgnore == 1 && header->crc32 == HAL_BOOT2_DEADBEEF_VAL) {
//MSG("Crc ignored\r\n");
crc_pass = 1;
} else {
crc = BFLB_Soft_CRC32((uint8_t *)header, sizeof(struct hal_bootheader_t) - sizeof(header->crc32));
if (header->crc32 == crc) {
crc_pass = 1;
}
}
if (crc_pass) {
if (header->bootCfg.bval.notLoadInBoot) {
return 0x0202;
}
/* Get which CPU's img it is*/
for (i = 0; i < HAL_BOOT2_CPU_MAX; i++) {
if (0 == memcmp((void *)&header->magicCode, HAL_BOOT2_CPU0_MAGIC,
sizeof(header->magicCode))) {
break;
} else if (0 == memcmp((void *)&header->magicCode, HAL_BOOT2_CPU1_MAGIC,
sizeof(header->magicCode))) {
break;
}
}
if (i == HAL_BOOT2_CPU_MAX) {
/* No cpu img magic match */
//MSG_ERR("Magic code error\r\n");
return 0x0203;
}
boot_img_cfg->cpu_type = i;
boot_img_cfg->entry_point = 0;
/* Set image valid 0 as default */
boot_img_cfg->img_valid = 0;
/* Deal with pll config */
/* Encrypt and sign */
boot_img_cfg->encrypt_type = header->bootCfg.bval.encrypt_type;
boot_img_cfg->sign_type = header->bootCfg.bval.sign;
boot_img_cfg->key_sel = header->bootCfg.bval.key_sel;
/* Xip relative */
boot_img_cfg->no_segment = header->bootCfg.bval.no_segment;
boot_img_cfg->cache_enable = header->bootCfg.bval.cache_enable;
boot_img_cfg->aes_region_lock = header->bootCfg.bval.aes_region_lock;
boot_img_cfg->halt_cpu1 = header->bootCfg.bval.halt_cpu1;
boot_img_cfg->cache_way_disable = header->bootCfg.bval.cache_way_disable;
boot_img_cfg->hash_ignore = header->bootCfg.bval.hash_ignore;
/* Firmware len*/
boot_img_cfg->img_segment_info.img_len = header->img_segment_info.img_len;
/* Boot entry and flash offset */
boot_img_cfg->entry_point = header->bootEntry;
boot_img_cfg->img_start.flash_offset = header->img_start.flash_offset;
//MSG("sign %d,encrypt:%d\r\n", boot_img_cfg->sign_type,boot_img_cfg->encrypt_type);
/* Check encrypt and sign match*/
if (g_efuse_cfg.encrypted[i] != 0) {
if (boot_img_cfg->encrypt_type == 0) {
//MSG_ERR("Encrypt not fit\r\n");
return 0x0205;
}
}
if (g_efuse_cfg.sign[i] ^ boot_img_cfg->sign_type) {
//MSG_ERR("sign not fit\r\n");
boot_img_cfg->sign_type = g_efuse_cfg.sign[i];
return 0x0206;
}
if (g_ps_mode == 1 && (!g_efuse_cfg.hbn_check_sign)) {
/* In HBN Mode, if user select to ignore hash and sign*/
boot_img_cfg->hash_ignore = 1;
} else if ((boot_img_cfg->hash_ignore == 1 && *phash != HAL_BOOT2_DEADBEEF_VAL) ||
g_efuse_cfg.sign[i] != 0) {
/* If signed or user not really want to ignore, hash can't be ignored*/
boot_img_cfg->hash_ignore = 0;
}
if (g_user_hash_ignored) {
boot_img_cfg->hash_ignore = 1;
}
ARCH_MemCpy_Fast(boot_img_cfg->img_hash, header->hash, sizeof(header->hash));
if (boot_img_cfg->img_segment_info.img_len == 0) {
return 0x0207;
}
/* Start hash here*/
//Sec_Eng_SHA256_Init(&g_sha_ctx, SEC_ENG_SHA_ID0, SEC_ENG_SHA256, g_sha_tmp_buf, g_padding);
//Sec_Eng_SHA_Start(SEC_ENG_SHA_ID0);
device_unregister("dev_check_hash");
sec_hash_sha256_register(0,"dev_check_hash");
dev_check_hash = device_find("dev_check_hash");
if(dev_check_hash){
ret = device_open(dev_check_hash, 0);
if(ret){
//MSG_ERR("hash dev open err\r\n");
return 0xffff;
}
}else{
//MSG_ERR("hash dev find err\r\n");
return 0xffff;
}
} else {
//MSG_ERR("bootheader crc error\r\n");
//blsp_dump_data((uint8_t *)&crc, 4);
return 0x0204;
}
return 0;
}
void hal_boot2_clean_cache(void)
{
}

2
drivers/bl702_driver/hal_drv/src/hal_cam.c
View file

@ -220,8 +220,8 @@ void cam_isr(cam_device_t *handle)
tmpVal = BL_RD_REG(CAM_BASE, CAM_DVP_STATUS_AND_ERROR);
if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_NORMAL_INT_0)) {
handle->parent.callback(&handle->parent, NULL, 0, CAM_EVENT_FRAME);
CAM_IntClr(CAM_INT_NORMAL_0);
handle->parent.callback(&handle->parent, NULL, 0, CAM_EVENT_FRAME);
}
if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_NORMAL_INT_1)) {
CAM_IntClr(CAM_INT_NORMAL_1);

2
drivers/bl702_driver/hal_drv/src/hal_dac.c
View file

@ -275,7 +275,7 @@ int dac_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t siz
dma_channel_start(dma_ch);
return ret;
} else if (dev->oflag & DEVICE_OFLAG_STREAM_TX) {
if (channel & DAC_CHANNEL_ALL) {
if ((channel & DAC_CHANNEL_ALL) == DAC_CHANNEL_ALL) {
for (i = 0; i < size; i++) {
GLB_DAC_Set_ChanA_Value(*((uint16_t *)buffer + i));
GLB_DAC_Set_ChanB_Value(*((uint16_t *)buffer + i));

82
drivers/bl702_driver/hal_drv/src/hal_dma.c
View file

@ -140,18 +140,18 @@ int dma_control(struct device *dev, int cmd, void *args)
case DEVICE_CTRL_CONFIG:
break;
case DMA_CHANNEL_UPDATE:
case DEVICE_CTRL_DMA_CHANNEL_UPDATE:
DMA_LLI_Update(dma_device->ch, (uint32_t)args);
break;
case DMA_CHANNEL_GET_STATUS:
case DEVICE_CTRL_DMA_CHANNEL_GET_STATUS:
return DMA_Channel_Is_Busy(dma_device->ch);
case DMA_CHANNEL_START:
case DEVICE_CTRL_DMA_CHANNEL_START:
DMA_Channel_Enable(dma_device->ch);
break;
case DMA_CHANNEL_STOP:
case DEVICE_CTRL_DMA_CHANNEL_STOP:
DMA_Channel_Disable(dma_device->ch);
break;
case DEVICE_CTRL_DMA_CONFIG_SI: {
@ -329,12 +329,7 @@ int dma_reload(struct device *dev, uint32_t src_addr, uint32_t dst_addr, uint32_
malloc_count++;
}
if (dma_device->lli_cfg) {
free(dma_device->lli_cfg);
dma_device->lli_cfg = (dma_lli_ctrl_t *)malloc(sizeof(dma_lli_ctrl_t) * malloc_count);
} else {
dma_device->lli_cfg = (dma_lli_ctrl_t *)malloc(sizeof(dma_lli_ctrl_t) * malloc_count);
}
dma_device->lli_cfg = (dma_lli_ctrl_t *)realloc(dma_device->lli_cfg, sizeof(dma_lli_ctrl_t) * malloc_count);
if (dma_device->lli_cfg) {
/*transfer_size will be integer multiple of 4095*n or 4095*2*n or 4095*4*n,(n>0) */
@ -369,7 +364,8 @@ int dma_reload(struct device *dev, uint32_t src_addr, uint32_t dst_addr, uint32_
dma_device->lli_cfg[i - 1].nextlli = (uint32_t)&dma_device->lli_cfg[i];
}
memcpy(&dma_device->lli_cfg[i].cfg, &dma_ctrl_cfg, sizeof(dma_control_data_t));
dma_device->lli_cfg[i].cfg = dma_ctrl_cfg;
}
BL_WR_REG(dma_channel_base[dma_device->id][dma_device->ch], DMA_SRCADDR, dma_device->lli_cfg[0].src_addr);
BL_WR_REG(dma_channel_base[dma_device->id][dma_device->ch], DMA_DSTADDR, dma_device->lli_cfg[0].dst_addr);
@ -381,54 +377,44 @@ int dma_reload(struct device *dev, uint32_t src_addr, uint32_t dst_addr, uint32_
return 0;
}
/**
* @brief
*
* @param handle
*/
void dma_isr(dma_device_t *handle)
void dma_channel_isr(dma_device_t *handle)
{
uint32_t tmpVal;
uint32_t intClr;
/* Get DMA register */
if (handle->id == 0) {
uint32_t DMAChs = DMA_BASE;
uint32_t DMAChs = DMA_BASE;
for (uint8_t i = 0; i < DMA_MAX_INDEX; i++) {
tmpVal = BL_RD_REG(DMAChs, DMA_INTTCSTATUS);
if (!handle->parent.callback) {
return;
}
if ((BL_GET_REG_BITS_VAL(tmpVal, DMA_INTTCSTATUS) & (1 << handle[i].ch)) != 0) {
/* Clear interrupt */
tmpVal = BL_RD_REG(DMAChs, DMA_INTTCCLEAR);
intClr = BL_GET_REG_BITS_VAL(tmpVal, DMA_INTTCCLEAR);
intClr |= (1 << handle[i].ch);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_INTTCCLEAR, intClr);
BL_WR_REG(DMAChs, DMA_INTTCCLEAR, tmpVal);
tmpVal = BL_RD_REG(DMAChs, DMA_INTTCSTATUS);
if ((BL_GET_REG_BITS_VAL(tmpVal, DMA_INTTCSTATUS) & (1 << handle->ch)) != 0) {
/* Clear interrupt */
tmpVal = BL_RD_REG(DMAChs, DMA_INTTCCLEAR);
intClr = BL_GET_REG_BITS_VAL(tmpVal, DMA_INTTCCLEAR);
intClr |= (1 << handle->ch);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_INTTCCLEAR, intClr);
BL_WR_REG(DMAChs, DMA_INTTCCLEAR, tmpVal);
handle->parent.callback(&handle->parent, NULL, 0, DMA_INT_TCOMPLETED);
}
if (handle[i].parent.callback) {
handle[i].parent.callback(&handle[i].parent, NULL, 0, DMA_INT_TCOMPLETED);
}
}
}
for (uint8_t i = 0; i < DMA_MAX_INDEX; i++) {
tmpVal = BL_RD_REG(DMAChs, DMA_INTERRORSTATUS);
if ((BL_GET_REG_BITS_VAL(tmpVal, DMA_INTERRORSTATUS) & (1 << handle[i].ch)) != 0) {
/*Clear interrupt */
tmpVal = BL_RD_REG(DMAChs, DMA_INTERRCLR);
intClr = BL_GET_REG_BITS_VAL(tmpVal, DMA_INTERRCLR);
intClr |= (1 << handle[i].ch);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_INTERRCLR, intClr);
BL_WR_REG(DMAChs, DMA_INTERRCLR, tmpVal);
if (handle[i].parent.callback) {
handle[i].parent.callback(&handle->parent, NULL, 0, DMA_INT_ERR);
}
}
}
} else {
tmpVal = BL_RD_REG(DMAChs, DMA_INTERRORSTATUS);
if ((BL_GET_REG_BITS_VAL(tmpVal, DMA_INTERRORSTATUS) & (1 << handle->ch)) != 0) {
/*Clear interrupt */
tmpVal = BL_RD_REG(DMAChs, DMA_INTERRCLR);
intClr = BL_GET_REG_BITS_VAL(tmpVal, DMA_INTERRCLR);
intClr |= (1 << handle->ch);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_INTERRCLR, intClr);
BL_WR_REG(DMAChs, DMA_INTERRCLR, tmpVal);
handle->parent.callback(&handle->parent, NULL, 0, DMA_INT_ERR);
}
}
/**
@ -437,5 +423,7 @@ void dma_isr(dma_device_t *handle)
*/
void DMA0_IRQ(void)
{
dma_isr(&dmax_device[0]);
for (uint8_t i = 0; i < DMA_MAX_INDEX; i++) {
dma_channel_isr(&dmax_device[i]);
}
}

34
drivers/bl702_driver/hal_drv/src/hal_flash.c
View file

@ -27,8 +27,22 @@
#include "bl702_sf_cfg_ext.h"
#include "hal_flash.h"
static uint32_t g_jedec_id = 0;
static SPI_Flash_Cfg_Type g_flash_cfg;
/**
* @brief flash_get_jedecid
*
* @return BL_Err_Type
*/
uint32_t flash_get_jedecid(void)
{
uint32_t jid = 0;
jid = ((g_jedec_id&0xff)<<16) + (g_jedec_id&0xff00) + ((g_jedec_id&0xff0000)>>16);
return jid;
}
/**
* @brief flash_get_cfg
*
@ -92,6 +106,7 @@ static BL_Err_Type ATTR_TCM_SECTION flash_config_init(SPI_Flash_Cfg_Type *p_flas
SFlash_GetJedecId(p_flash_cfg, (uint8_t *)&jid);
arch_memcpy(jedec_id, (uint8_t *)&jid, 3);
jid &= 0xFFFFFF;
g_jedec_id = jid;
ret = SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(jid, p_flash_cfg);
if (ret == SUCCESS) {
p_flash_cfg->mid = (jid & 0xff);
@ -247,6 +262,25 @@ BL_Err_Type ATTR_TCM_SECTION flash_erase(uint32_t startaddr, uint32_t len)
return ret;
}
/**
* @brief flash write protect set
*
* @param protect
* @return BL_Err_Type
*/
BL_Err_Type ATTR_TCM_SECTION flash_write_protect_set(SFlash_Protect_Kh25v40_Type protect)
{
BL_Err_Type ret = ERROR;
cpu_global_irq_disable();
XIP_SFlash_Opt_Enter();
ret = XIP_SFlash_KH25V40_Write_Protect_Need_Lock(&g_flash_cfg, protect);
XIP_SFlash_Opt_Exit();
cpu_global_irq_enable();
return ret;
}
/**
* @brief flash clear status register
*

25
drivers/bl702_driver/hal_drv/src/hal_pm.c
View file

@ -901,13 +901,16 @@ ATTR_TCM_SECTION void pm_pds_mode_enter(enum pm_pds_sleep_level pds_level, uint3
tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
tmpVal &= ~(1 << 8); //unmask pds wakeup
if (!BL_GET_REG_BITS_VAL(BL_RD_REG(PDS_BASE, PDS_GPIO_INT), PDS_GPIO_INT_MASK) || !(BL_RD_REG(GLB_BASE, GLB_GPIO_INT_MASK1) == 0xffffffff))
if (!BL_GET_REG_BITS_VAL(BL_RD_REG(PDS_BASE, PDS_GPIO_INT), PDS_GPIO_INT_MASK) || !(BL_RD_REG(GLB_BASE, GLB_GPIO_INT_MASK1) == 0xffffffff)) {
tmpVal |= (1 << 19); //enable gpio wakeup for pds
if (BL_GET_REG_BITS_VAL(BL_RD_REG(HBN_BASE, HBN_IRQ_MODE), HBN_REG_AON_PAD_IE_SMT))
}
if (BL_GET_REG_BITS_VAL(BL_RD_REG(HBN_BASE, HBN_IRQ_MODE), HBN_REG_AON_PAD_IE_SMT)) {
tmpVal |= (1 << 17); //enable hbn out0 wakeup for pds
}
if (sleep_time)
if (sleep_time) {
tmpVal |= (1 << 16); //unmask pds sleep time wakeup
}
BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);
PDS_Set_Vddcore_GPIO_IntClear();
@ -968,7 +971,7 @@ ATTR_TCM_SECTION void pm_pds_mode_enter(enum pm_pds_sleep_level pds_level, uint3
/* pds0-pds7 : ldo11rt_iload_sel=3 */
/* pds31 : ldo11rt_iload_sel=1 */
if ((pds_level >= 0) && (pds_level <= 7)) {
if (pds_level <= PM_PDS_LEVEL_7) {
HBN_Set_Ldo11rt_Drive_Strength(HBN_LDO11RT_DRIVE_STRENGTH_25_250UA);
} else if (pds_level == PM_PDS_LEVEL_31) {
HBN_Set_Ldo11rt_Drive_Strength(HBN_LDO11RT_DRIVE_STRENGTH_10_100UA);
@ -1038,13 +1041,16 @@ ATTR_TCM_SECTION void pm_pds31_fast_mode_enter(enum pm_pds_sleep_level pds_level
tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
tmpVal &= ~(1 << 8); //unmask pds wakeup
if (!BL_GET_REG_BITS_VAL(BL_RD_REG(PDS_BASE, PDS_GPIO_INT), PDS_GPIO_INT_MASK))
if (!BL_GET_REG_BITS_VAL(BL_RD_REG(PDS_BASE, PDS_GPIO_INT), PDS_GPIO_INT_MASK)) {
tmpVal |= (1 << 19); //enable gpio wakeup for pds
if (BL_GET_REG_BITS_VAL(BL_RD_REG(HBN_BASE, HBN_IRQ_MODE), HBN_REG_AON_PAD_IE_SMT))
}
if (BL_GET_REG_BITS_VAL(BL_RD_REG(HBN_BASE, HBN_IRQ_MODE), HBN_REG_AON_PAD_IE_SMT)) {
tmpVal |= (1 << 17); //enable hbn out0 wakeup for pds
}
if (sleep_time)
if (sleep_time) {
tmpVal |= (1 << 16); //unmask pds sleep time wakeup
}
BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);
PDS_IntClear();
@ -1129,11 +1135,6 @@ ATTR_TCM_SECTION void pm_pds31_fast_mode_enter(enum pm_pds_sleep_level pds_level
pm_pds_enter_done();
#if PM_PDS_PLL_POWER_OFF
GLB_Set_System_CLK(XTAL_TYPE, BSP_ROOT_CLOCK_SOURCE);
PDS_Update_Flash_Ctrl_Setting(1);
#endif
cpu_global_irq_enable();
// Get cache way disable setting

63
drivers/bl702_driver/hal_drv/src/hal_pm_util.c
View file

@ -23,6 +23,8 @@
#include "bl702_romdriver.h"
#include "bl702_sf_ctrl.h"
#include "bl702_glb.h"
#include "hal_clock.h"
#include "hal_pm.h"
#include "hal_pm_util.h"
@ -41,8 +43,7 @@ extern SPI_Flash_Cfg_Type *flash_cfg;
void ATTR_PDS_RAM_SECTION pm_pds_fastboot_entry(void);
void (*tcm_recovery)(void) = NULL;
void (*board_recovery)(void) = NULL;
void (*hardware_recovery)(void) = NULL;
/**
* @brief hal_pds_enter_with_time_compensation
@ -151,7 +152,8 @@ int32_t ATTR_PDS_RAM_SECTION pm_spi_flash_init(uint8_t media_boot)
uint32_t flash_read_try = 0;
/*use fclk as flash clok */
RomDriver_GLB_Set_SF_CLK(1, GLB_SFLASH_CLK_BCLK, 0); // 32M
RomDriver_GLB_Set_SF_CLK(1, GLB_SFLASH_CLK_XCLK, 0); // 32M
RomDriver_SF_Ctrl_Set_Clock_Delay(0);
bflb_spi_flash_set_sf_ctrl(flash_cfg);
@ -254,7 +256,36 @@ static void ATTR_PDS_RAM_SECTION pm_pds_restore_cpu_reg(void)
"csrw mstatus,a1\n\t"
"ret\n\t");
}
void ATTR_PDS_RAM_SECTION sf_io_select(void)
{
uint32_t tmpVal = 0;
uint8_t flashCfg = 0;
uint8_t psramCfg = 0;
uint8_t isInternalFlash = 0;
uint8_t isInternalPsram = 0;
/* SF io select from efuse value */
tmpVal = BL_RD_WORD(0x40007074);
flashCfg = ((tmpVal >> 26) & 7);
psramCfg = ((tmpVal >> 24) & 3);
if (flashCfg == 1 || flashCfg == 2) {
isInternalFlash = 1;
} else {
isInternalFlash = 0;
}
if (psramCfg == 1) {
isInternalPsram = 1;
} else {
isInternalPsram = 0;
}
tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO);
if (isInternalFlash == 1 && isInternalPsram == 0) {
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CFG_GPIO_USE_PSRAM_IO, 0x3f);
} else {
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CFG_GPIO_USE_PSRAM_IO, 0x00);
}
BL_WR_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO, tmpVal);
}
// must be placed in pds section
void ATTR_PDS_RAM_SECTION pm_pds_fastboot_entry(void)
{
@ -265,28 +296,26 @@ void ATTR_PDS_RAM_SECTION pm_pds_fastboot_entry(void)
"la gp, __global_pointer$\n\t"
".option pop\n\t");
#if XTAL_TYPE != INTERNAL_RC_32M
/* power on Xtal_32M*/
(*(volatile uint32_t *)(AON_BASE + AON_RF_TOP_AON_OFFSET)) |= (3 << 4);
#endif
// recovery flash pad and param
RomDriver_SF_Cfg_Init_Flash_Gpio(0, 1);
pm_spi_flash_init(1);
sf_io_select();
// Restore tcm code
if (tcm_recovery)
tcm_recovery();
// Recovery gpio and clock
if (board_recovery)
board_recovery();
/* Recovery hardware , include tcm , gpio and clock */
if (hardware_recovery) {
hardware_recovery();
}
// Restore cpu registers
pm_pds_restore_cpu_reg();
}
void pm_set_tcm_recovery_callback(void (*tcm_recovery_cb)(void))
void pm_set_hardware_recovery_callback(void (*hardware_recovery_cb)(void))
{
tcm_recovery = tcm_recovery_cb;
}
void pm_set_board_recovery_callback(void (*board_recovery_cb)(void))
{
board_recovery = board_recovery_cb;
hardware_recovery = hardware_recovery_cb;
}

308
drivers/bl702_driver/hal_drv/src/hal_sec_ecdsa.c
View file

@ -20,12 +20,31 @@
//#define ECDSA_DBG 1
//#define ECDSA_DBG_DETAIL 1
#define secp256r1
#define secp256k1
#define SEC_ECC_POINT_MUL_PARAM_CFG(G) sec_ecc_point_mul_cfg( \
(uint32_t *)G##P, \
(uint32_t *)G##PrimeN_P, \
(uint32_t *)G##_1, \
(uint32_t *)G##_BAR2, \
(uint32_t *)G##_BAR3, \
(uint32_t *)G##_BAR4, \
(uint32_t *)G##_BAR8, \
(uint32_t *)G##_1P1, \
(uint32_t *)G##_1M1)
#define SEC_ECC_BASIC_PARAM_CFG(G) sec_ecc_basic_parameter_cfg( \
(uint32_t *)G##N, \
(uint32_t *)G##PrimeN_N, \
(uint32_t *)G##InvR_N)
void bflb_platform_dump(uint8_t *data, uint32_t len);
#if (defined(ECDSA_DBG) || defined(ECDSA_DBG_DETAIL))
uint32_t pka_tmp[32] = { 0 };
#endif
/********************************************** secp256r1 *******************************************/
const uint8_t secp256r1P[32] ALIGN4 = {
0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
@ -107,28 +126,139 @@ const uint8_t secp256r1_Gy[32] ALIGN4 = {
0x8b, 0x4a, 0xb8, 0xe4, 0xba, 0x19, 0xe4, 0x5c, 0xdd, 0xf2, 0x53, 0x57, 0xce, 0x95, 0x56, 0x0a
};
static int sec_ecc_basic_parameter_init(uint8_t id)
{
Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, (uint32_t *)secp256r1N, ECP_SECP256R1_SIZE / 4, 0);
Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_NPRIME_N_REG_INDEX, (uint32_t *)secp256r1PrimeN_N, ECP_SECP256R1_SIZE / 4, 0);
Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_INVR_N_REG_INDEX, (uint32_t *)secp256r1InvR_N, ECP_SECP256R1_SIZE / 4, 0);
/********************************************** secp256k1 *******************************************/
const uint8_t secp256k1P[32] ALIGN4 = {
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFC, 0x2F
};
const uint8_t secp256k1B[32] ALIGN4 = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07
};
const uint8_t secp256k1Gx[32] ALIGN4 = {
0x79, 0xBE, 0x66, 0x7E, 0xF9, 0xDC, 0xBB, 0xAC, 0x55, 0xA0, 0x62, 0x95, 0xCE, 0x87, 0x0B, 0x07,
0x02, 0x9B, 0xFC, 0xDB, 0x2D, 0xCE, 0x28, 0xD9, 0x59, 0xF2, 0x81, 0x5B, 0x16, 0xF8, 0x17, 0x98
};
const uint8_t secp256k1Gy[32] ALIGN4 = {
0x4f, 0xe3, 0x42, 0xe2, 0xfe, 0x1a, 0x7f, 0x9b, 0x8e, 0xe7, 0xeb, 0x4a, 0x7c, 0x0f, 0x9e, 0x16,
0x2b, 0xce, 0x33, 0x57, 0x6b, 0x31, 0x5e, 0xce, 0xcb, 0xb6, 0x40, 0x68, 0x37, 0xbf, 0x51, 0xf5
};
const uint8_t secp256k1N[32] ALIGN4 = {
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE,
0xBA, 0xAE, 0xDC, 0xE6, 0xAF, 0x48, 0xA0, 0x3B, 0xBF, 0xD2, 0x5E, 0x8C, 0xD0, 0x36, 0x41, 0x41
};
const uint8_t secp256k1PrimeN_N[32] ALIGN4 = {
0xd9, 0xe8, 0x89, 0xd, 0x64, 0x94, 0xef, 0x93, 0x89, 0x7f, 0x30, 0xc1, 0x27, 0xcf, 0xab, 0x5e,
0x50, 0xa5, 0x1a, 0xc8, 0x34, 0xb9, 0xec, 0x24, 0x4b, 0xd, 0xff, 0x66, 0x55, 0x88, 0xb1, 0x3f
};
const uint8_t secp256k1InvR_N[32] ALIGN4 = {
0xd9, 0xe8, 0x89, 0xd, 0x64, 0x94, 0xef, 0x93, 0x89, 0x7f, 0x30, 0xc1, 0x27, 0xcf, 0xab, 0x5d,
0x3b, 0xbb, 0xd4, 0x56, 0x7f, 0xa5, 0xc, 0x3c, 0x80, 0xfd, 0x22, 0x93, 0x80, 0x97, 0xc0, 0x16
};
const uint8_t secp256k1PrimeN_P[32] ALIGN4 = {
0xc9, 0xbd, 0x19, 0x5, 0x15, 0x53, 0x83, 0x99, 0x9c, 0x46, 0xc2, 0xc2, 0x95, 0xf2, 0xb7, 0x61,
0xbc, 0xb2, 0x23, 0xfe, 0xdc, 0x24, 0xa0, 0x59, 0xd8, 0x38, 0x9, 0x1d, 0xd2, 0x25, 0x35, 0x31
};
const uint8_t secp256k1InvR_P[32] ALIGN4 = {
0xc9, 0xbd, 0x19, 0x5, 0x15, 0x53, 0x83, 0x99, 0x9c, 0x46, 0xc2, 0xc2, 0x95, 0xf2, 0xb7, 0x61,
0xbc, 0xb2, 0x23, 0xfe, 0xdc, 0x24, 0xa0, 0x59, 0xd8, 0x38, 0x9, 0x1d, 0x8, 0x68, 0x19, 0x2a
};
const uint8_t secp256k1_1[32] ALIGN4 = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01
};
const uint8_t secp256k1_BAR2[32] ALIGN4 = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x07, 0xa2
};
const uint8_t secp256k1_BAR3[32] ALIGN4 = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x0b, 0x73
};
const uint8_t secp256k1_BAR4[32] ALIGN4 = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x0f, 0x44
};
const uint8_t secp256k1_BAR8[32] ALIGN4 = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x1e, 0x88
};
const uint8_t secp256k1_1P1[32] ALIGN4 = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x03, 0xd2
};
const uint8_t secp256k1_1M1[32] ALIGN4 = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x03, 0xd0
};
const uint8_t secp256k1_Zerox[32] ALIGN4 = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
};
const uint8_t secp256k1_Zeroy[32] ALIGN4 = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x03, 0xd1
};
const uint8_t secp256k1_Gx[32] ALIGN4 = {
0x99, 0x81, 0xe6, 0x43, 0xe9, 0x08, 0x9f, 0x48, 0x97, 0x9f, 0x48, 0xc0, 0x33, 0xfd, 0x12, 0x9c,
0x23, 0x1e, 0x29, 0x53, 0x29, 0xbc, 0x66, 0xdb, 0xd7, 0x36, 0x2e, 0x5a, 0x48, 0x7e, 0x20, 0x97
};
const uint8_t secp256k1_Gy[32] ALIGN4 = {
0xcf, 0x3f, 0x85, 0x1f, 0xd4, 0xa5, 0x82, 0xd6, 0x70, 0xb6, 0xb5, 0x9a, 0xac, 0x19, 0xc1, 0x36,
0x8d, 0xfc, 0x5d, 0x5d, 0x1f, 0x1d, 0xc6, 0x4d, 0xb1, 0x5e, 0xa6, 0xd2, 0xd3, 0xdb, 0xab, 0xe2
};
return 0;
static BL_Err_Type sec_ecc_basic_parameter_cfg(uint32_t *n, uint32_t *prime_n, uint32_t *invr_n)
{
Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, (uint32_t *)n, ECP_SECP256R1_SIZE / 4, 0);
Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_NPRIME_N_REG_INDEX, (uint32_t *)prime_n, ECP_SECP256R1_SIZE / 4, 0);
Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_INVR_N_REG_INDEX, (uint32_t *)invr_n, ECP_SECP256R1_SIZE / 4, 0);
return SUCCESS;
}
static BL_Err_Type sec_ecc_basic_parameter_init(uint8_t id)
{
if (id >= ECP_TYPE_MAX) {
return ERROR;
}
if (id == ECP_SECP256R1) {
SEC_ECC_BASIC_PARAM_CFG(secp256r1);
} else if (id == ECP_SECP256K1) {
SEC_ECC_BASIC_PARAM_CFG(secp256k1);
}
return SUCCESS;
}
static BL_Err_Type sec_ecc_point_mul_cfg(uint32_t *p, uint32_t *primeN_p, uint32_t *ori_1, uint32_t *bar2,
uint32_t *bar3, uint32_t *bar4, uint32_t *bar8, uint32_t *bar1p1, uint32_t *bar1m1)
{
Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 0, (uint32_t *)p, ECP_SECP256R1_SIZE / 4, 0);
Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 1, (uint32_t *)primeN_p, ECP_SECP256R1_SIZE / 4, 0);
Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 8, (uint32_t *)ori_1, ECP_SECP256R1_SIZE / 4, 0);
Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 9, (uint32_t *)bar2, ECP_SECP256R1_SIZE / 4, 0);
Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 10, (uint32_t *)bar3, ECP_SECP256R1_SIZE / 4, 0);
Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 11, (uint32_t *)bar4, ECP_SECP256R1_SIZE / 4, 0);
Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 12, (uint32_t *)bar8, ECP_SECP256R1_SIZE / 4, 0);
Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 19, (uint32_t *)bar1p1, ECP_SECP256R1_SIZE / 4, 0);
Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 20, (uint32_t *)bar1m1, ECP_SECP256R1_SIZE / 4, 0);
return SUCCESS;
}
static int sec_ecc_point_mul_init(uint8_t id)
{
Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 0, (uint32_t *)secp256r1P, ECP_SECP256R1_SIZE / 4, 0);
Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 1, (uint32_t *)secp256r1PrimeN_P, ECP_SECP256R1_SIZE / 4, 0);
Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 8, (uint32_t *)secp256r1_1, ECP_SECP256R1_SIZE / 4, 0);
Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 9, (uint32_t *)secp256r1_BAR2, ECP_SECP256R1_SIZE / 4, 0);
Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 10, (uint32_t *)secp256r1_BAR3, ECP_SECP256R1_SIZE / 4, 0);
Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 11, (uint32_t *)secp256r1_BAR4, ECP_SECP256R1_SIZE / 4, 0);
Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 12, (uint32_t *)secp256r1_BAR8, ECP_SECP256R1_SIZE / 4, 0);
Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 19, (uint32_t *)secp256r1_1P1, ECP_SECP256R1_SIZE / 4, 0);
Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 20, (uint32_t *)secp256r1_1M1, ECP_SECP256R1_SIZE / 4, 0);
if (id >= ECP_TYPE_MAX) {
return ERROR;
}
return 0;
if (id == ECP_SECP256R1) {
SEC_ECC_POINT_MUL_PARAM_CFG(secp256r1);
} else if (id == ECP_SECP256K1) {
SEC_ECC_POINT_MUL_PARAM_CFG(secp256k1);
}
return SUCCESS;
}
static void sec_ecdsa_point_add_inf_check(uint8_t *pka_p1_eq_inf, uint8_t *pka_p2_eq_inf)
@ -284,23 +414,13 @@ static void sec_ecdsa_point_add(uint8_t id)
//PKA_MSUB(1,3, 3,3, 3,3,14,3,0);
Sec_Eng_PKA_MSUB(3, 3, 3, 3, 3, 14, 3, 0, 1);
}
static void sec_ecdsa_point_double(uint8_t id)
/**
* @brief calculate secp256r1's W
*
* @note index 13:W = 3X^2-3Z^2
*/
static void sec_ecdsa_cal_secp256r1_w(void)
{
/* index 2:BAR_Zero_x
* index 3:BAR_Zero_y
* index 4:BAR_Zero_z
* index 5:BAR_G_x
* index 6:BAR_G_y
* index 7:BAR_G_z
* index 8:1
* index 9:2
* index 10:3
* index 11:4
* index 12:8
* index 19:1P1
* index 20:1m1*/
//X1^2
//PKA_MMUL(0,3,13,3, 5,3, 5,3,0);//d_reg_type,d_reg_idx,s0_reg_type,s0_reg_idx,s1_reg_type,s1_reg_idx,s2_reg_type,s2_reg_idx
Sec_Eng_PKA_MMUL(3, 13, 3, 5, 3, 5, 3, 0, 0);
@ -316,6 +436,47 @@ static void sec_ecdsa_point_double(uint8_t id)
//W = 3*(X1^2-Z1^2)
//PKA_MMUL(0,3,13,3,10,3,13,3,0);
Sec_Eng_PKA_MMUL(3, 13, 3, 10, 3, 13, 3, 0, 0);
}
/**
* @brief calculate secp256k1's W
*
* @note index 13:W = 3X^2
*/
static void sec_ecdsa_cal_secp256k1_w(void)
{
//X1^2
Sec_Eng_PKA_MMUL(3, 13, 3, 5, 3, 5, 3, 0, 0);
//W = 3* (X1^2)
Sec_Eng_PKA_MMUL(3, 13, 3, 10, 3, 13, 3, 0, 0);
}
static BL_Err_Type sec_ecdsa_point_double(sec_ecp_type id)
{
/* index 2:BAR_Zero_x
* index 3:BAR_Zero_y
* index 4:BAR_Zero_z
* index 5:BAR_G_x
* index 6:BAR_G_y
* index 7:BAR_G_z
* index 8:1
* index 9:2
* index 10:3
* index 11:4
* index 12:8
* index 19:1P1
* index 20:1m1*/
if (id >= ECP_TYPE_MAX) {
return ERROR;
}
if (id == ECP_SECP256R1) {
sec_ecdsa_cal_secp256r1_w();
} else if (id == ECP_SECP256K1) {
sec_ecdsa_cal_secp256k1_w();
}
//S = Y1*Z1
//PKA_MMUL(0,3,14,3, 6,3, 7,3,0);
@ -388,6 +549,8 @@ static void sec_ecdsa_point_double(uint8_t id)
//Z2 = 8*S^3
//PKA_MMUL(1,3, 7,3,12,3, 7,3,0);
Sec_Eng_PKA_MMUL(3, 7, 3, 12, 3, 7, 3, 0, 1);
return SUCCESS;
}
#ifdef ECDSA_DBG_DETAIL
static void sec_ecdsa_dump_temp_result()
@ -485,6 +648,10 @@ static int32_t sec_ecdh_get_scalar_point(uint8_t id, const uint32_t *pkX, const
uint32_t pk_z[8];
#endif
if (id >= ECP_TYPE_MAX) {
return ERROR;
}
/* Pointer check */
if (private_key == NULL) {
return -1;
@ -501,24 +668,38 @@ static int32_t sec_ecdh_get_scalar_point(uint8_t id, const uint32_t *pkX, const
sec_ecc_point_mul_init(id);
//X1
//PKA_CTREG(3, 2,8,bar_Zero_x);
Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 2, (uint32_t *)secp256r1_Zerox, ECP_SECP256R1_SIZE / 4, 0);
//Y1
//PKA_CTREG(3, 3,8,bar_Zero_y);
Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 3, (uint32_t *)secp256r1_Zeroy, ECP_SECP256R1_SIZE / 4, 0);
if (id == ECP_SECP256R1) {
//X1
//PKA_CTREG(3, 2,8,bar_Zero_x);
Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 2, (uint32_t *)secp256r1_Zerox, ECP_SECP256R1_SIZE / 4, 0);
//Y1
//PKA_CTREG(3, 3,8,bar_Zero_y);
Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 3, (uint32_t *)secp256r1_Zeroy, ECP_SECP256R1_SIZE / 4, 0);
} else if (id == ECP_SECP256K1) {
//X1
Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 2, (uint32_t *)secp256k1_Zerox, ECP_SECP256R1_SIZE / 4, 0);
//Y1
Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 3, (uint32_t *)secp256k1_Zeroy, ECP_SECP256R1_SIZE / 4, 0);
}
//Z1
//PKA_CTREG(3, 4,8,bar_Zero_z);
//PKA_MOVDAT(1,3, 4,3, 2);
Sec_Eng_PKA_Move_Data(3, 4, 3, 2, 1);
if (pkX == NULL) {
//X2
//PKA_CTREG(3, 5,8,bar_G_x);
Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)secp256r1_Gx, ECP_SECP256R1_SIZE / 4, 0);
//Y2
//PKA_CTREG(3, 6,8,bar_G_y);
Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)secp256r1_Gy, ECP_SECP256R1_SIZE / 4, 0);
if (id == ECP_SECP256R1) {
//X2
//PKA_CTREG(3, 5,8,bar_G_x);
Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)secp256r1_Gx, ECP_SECP256R1_SIZE / 4, 0);
//Y2
//PKA_CTREG(3, 6,8,bar_G_y);
Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)secp256r1_Gy, ECP_SECP256R1_SIZE / 4, 0);
} else if (id == ECP_SECP256K1) {
//X2
Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)secp256k1_Gx, ECP_SECP256R1_SIZE / 4, 0);
//Y2
Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)secp256k1_Gy, ECP_SECP256R1_SIZE / 4, 0);
}
} else {
/* chaneg peer's public key to mont domain*/
//PUB_x
@ -582,9 +763,13 @@ static int32_t sec_ecdh_get_scalar_point(uint8_t id, const uint32_t *pkX, const
//get R.x
//R.z ^ -1
Sec_Eng_PKA_MINV(ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 4, ECP_SECP256R1_REG_TYPE, 0, 1);
//inv_r
//PKA_CTREG(3, 6,8,inv_r);
Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)secp256r1InvR_P, ECP_SECP256R1_SIZE / 4, 0);
if (id == ECP_SECP256R1) {
//inv_r
//PKA_CTREG(3, 6,8,inv_r);
Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)secp256r1InvR_P, ECP_SECP256R1_SIZE / 4, 0);
} else if (id == ECP_SECP256K1) {
Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)secp256k1InvR_P, ECP_SECP256R1_SIZE / 4, 0);
}
//R.z ^ -1
Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX - 1, ECP_SECP256R1_SIZE / 4, 1);
Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_SIZE / 4, 1);
@ -606,7 +791,12 @@ static int32_t sec_ecdh_get_scalar_point(uint8_t id, const uint32_t *pkX, const
MSG("R.x=\r\n");
bflb_platform_dump(pRx, ECP_SECP256R1_SIZE);
#endif
Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, (uint32_t *)secp256r1N, ECP_SECP256R1_SIZE / 4, 0);
if (id == ECP_SECP256R1) {
Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, (uint32_t *)secp256r1N, ECP_SECP256R1_SIZE / 4, 0);
} else if (id == ECP_SECP256K1) {
Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, (uint32_t *)secp256k1N, ECP_SECP256R1_SIZE / 4, 0);
}
Sec_Eng_PKA_MREM(ECP_SECP256R1_REG_TYPE, 2, ECP_SECP256R1_REG_TYPE, 2,
ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, 1);
Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 2, (uint32_t *)pRx, ECP_SECP256R1_SIZE / 4);
@ -614,15 +804,23 @@ static int32_t sec_ecdh_get_scalar_point(uint8_t id, const uint32_t *pkX, const
MSG("R.x%n=\r\n");
bflb_platform_dump(pRx, ECP_SECP256R1_SIZE);
#endif
if (id == ECP_SECP256R1) {
/*after %n,re write p*/
Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 0, (uint32_t *)secp256r1P, ECP_SECP256R1_SIZE / 4, 0);
} else if (id == ECP_SECP256K1) {
Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 0, (uint32_t *)secp256k1P, ECP_SECP256R1_SIZE / 4, 0);
}
/*after %n,re write p*/
Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 0, (uint32_t *)secp256r1P, ECP_SECP256R1_SIZE / 4, 0);
//get R.y
//R.z ^ -1
Sec_Eng_PKA_MINV(ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 4, ECP_SECP256R1_REG_TYPE, 0, 1);
//inv_r
//PKA_CTREG(3, 6,8,inv_r);
Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)secp256r1InvR_P, ECP_SECP256R1_SIZE / 4, 0);
if (id == ECP_SECP256R1) {
Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)secp256r1InvR_P, ECP_SECP256R1_SIZE / 4, 0);
} else if (id == ECP_SECP256K1) {
Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)secp256k1InvR_P, ECP_SECP256R1_SIZE / 4, 0);
}
//R.z ^ -1
Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX - 1, ECP_SECP256R1_SIZE / 4, 1);
Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_SIZE / 4, 1);
@ -643,7 +841,11 @@ static int32_t sec_ecdh_get_scalar_point(uint8_t id, const uint32_t *pkX, const
MSG("R.y=\r\n");
bflb_platform_dump(pRy, ECP_SECP256R1_SIZE);
#endif
Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, (uint32_t *)secp256r1N, ECP_SECP256R1_SIZE / 4, 0);
if (id == ECP_SECP256R1) {
Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, (uint32_t *)secp256r1N, ECP_SECP256R1_SIZE / 4, 0);
} else if (id == ECP_SECP256K1) {
Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, (uint32_t *)secp256k1N, ECP_SECP256R1_SIZE / 4, 0);
}
Sec_Eng_PKA_MREM(ECP_SECP256R1_REG_TYPE, 3, ECP_SECP256R1_REG_TYPE, 3,
ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, 1);
Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 3, (uint32_t *)pRy, ECP_SECP256R1_SIZE / 4);

7
drivers/bl702_driver/hal_drv/src/hal_timer.c
View file

@ -346,20 +346,21 @@ void timer_isr(timer_device_t *handle)
/* Comparator 0 match interrupt */
if (BL_IS_REG_BIT_SET(intId, TIMER_TMSR_0)) {
handle->parent.callback(&handle->parent, NULL, 0, TIMER_EVENT_COMP0);
BL_WR_WORD(tmpAddr, BL_SET_REG_BIT(tmpVal, TIMER_TCLR_0));
handle->parent.callback(&handle->parent, NULL, 0, TIMER_EVENT_COMP0);
}
/* Comparator 1 match interrupt */
if (BL_IS_REG_BIT_SET(intId, TIMER_TMSR_1)) {
handle->parent.callback(&handle->parent, NULL, 0, TIMER_EVENT_COMP1);
BL_WR_WORD(tmpAddr, BL_SET_REG_BIT(tmpVal, TIMER_TCLR_1));
handle->parent.callback(&handle->parent, NULL, 0, TIMER_EVENT_COMP1);
}
/* Comparator 2 match interrupt */
if (BL_IS_REG_BIT_SET(intId, TIMER_TMSR_2)) {
handle->parent.callback(&handle->parent, NULL, 0, TIMER_EVENT_COMP2);
BL_WR_WORD(tmpAddr, BL_SET_REG_BIT(tmpVal, TIMER_TCLR_2));
handle->parent.callback(&handle->parent, NULL, 0, TIMER_EVENT_COMP2);
}
}

9
drivers/bl702_driver/hal_drv/src/hal_uart.c
View file

@ -148,7 +148,7 @@ int uart_control(struct device *dev, int cmd, void *args)
switch (cmd) {
case DEVICE_CTRL_SET_INT /* constant-expression */: {
uint32_t offset = __builtin_ctz((uint32_t)args);
while ((0 <= offset) && (offset < 9)) {
while (offset < 9) {
if ((uint32_t)args & (1 << offset)) {
UART_IntMask(uart_device->id, offset, UNMASK);
}
@ -163,7 +163,7 @@ int uart_control(struct device *dev, int cmd, void *args)
}
case DEVICE_CTRL_CLR_INT /* constant-expression */: {
uint32_t offset = __builtin_ctz((uint32_t)args);
while ((0 <= offset) && (offset < 9)) {
while (offset < 9) {
if ((uint32_t)args & (1 << offset)) {
UART_IntMask(uart_device->id, offset, MASK);
}
@ -387,7 +387,7 @@ void uart_isr(uart_device_t *handle)
/* Rx fifo ready interrupt,auto-cleared when data is popped */
if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_FIFO_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_FIFO_MASK)) {
uint8_t buffer[UART_FIFO_MAX_LEN];
uint8_t len = UART_ReceiveData(handle->id, buffer, handle->fifo_threshold);
uint8_t len = UART_ReceiveData(handle->id, buffer, UART_FIFO_MAX_LEN);
if (len) {
handle->parent.callback(&handle->parent, &buffer[0], len, UART_EVENT_RX_FIFO);
}
@ -395,13 +395,12 @@ void uart_isr(uart_device_t *handle)
/* Rx time-out interrupt */
if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_RTO_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_RTO_MASK)) {
BL_WR_REG(UARTx, UART_INT_CLEAR, 0x10);
uint8_t buffer[UART_FIFO_MAX_LEN];
uint8_t len = UART_ReceiveData(handle->id, buffer, UART_FIFO_MAX_LEN);
if (len) {
handle->parent.callback(&handle->parent, &buffer[0], len, UART_EVENT_RTO);
}
BL_WR_REG(UARTx, UART_INT_CLEAR, 0x10);
}
/* Rx parity check error interrupt */

100
drivers/bl702_driver/hal_drv/src/hal_usb.c
View file

@ -27,7 +27,9 @@
#include "bl702_glb.h"
#define USE_INTERNAL_TRANSCEIVER
// #define ENABLE_LPM_INT
//#define ENABLE_LPM_INT
//#define ENABLE_SOF3MS_INT
//#define ENABLE_ERROR_INT
#define MIN(a, b) (((a) < (b)) ? (a) : (b))
@ -408,7 +410,7 @@ int usb_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t siz
usb_lli_list.cfg.bits.SI = 1;
usb_lli_list.cfg.bits.SBSize = DMA_BURST_16BYTE;
usb_lli_list.cfg.bits.DBSize = DMA_BURST_1BYTE;
device_control(usb_device->tx_dma, DMA_CHANNEL_UPDATE, (void *)((uint32_t)&usb_lli_list));
dma_channel_update(usb_device->tx_dma, (void *)((uint32_t)&usb_lli_list));
dma_channel_start(usb_device->tx_dma);
return 0;
} else {
@ -433,7 +435,7 @@ int usb_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size)
usb_lli_list.cfg.bits.SI = 0;
usb_lli_list.cfg.bits.SBSize = DMA_BURST_1BYTE;
usb_lli_list.cfg.bits.DBSize = DMA_BURST_16BYTE;
device_control(usb_device->rx_dma, DMA_CHANNEL_UPDATE, (void *)((uint32_t)&usb_lli_list));
dma_channel_update(usb_device->rx_dma, (void *)((uint32_t)&usb_lli_list));
dma_channel_start(usb_device->rx_dma);
return 0;
} else {
@ -509,6 +511,10 @@ int usb_dc_ep_open(struct device *dev, const struct usb_dc_ep_cfg *ep_cfg)
USB_DC_LOG_DBG("%s ep %x, mps %d, type %d\r\n", __func__, ep, ep_cfg->ep_mps, ep_cfg->ep_type);
if (ep_idx == 0) {
return 0;
}
if (USB_EP_DIR_IS_OUT(ep)) {
epCfg.dir = EP_OUT;
epCfg.EPMaxPacketSize = ep_cfg->ep_mps;
@ -1027,12 +1033,6 @@ int usb_dc_send_from_ringbuffer(struct device *dev, Ring_Buffer_Type *rb, uint8_
}
}
/**
* @brief This function handles PCD interrupt request.
* @param hpcd PCD handle
* @retval HAL status
*/
/**
* @brief
*
@ -1048,11 +1048,10 @@ void usb_dc_isr(usb_dc_device_t *device)
epnum = (epint - USB_INT_EP0_OUT_CMD) >> 1;
if (!USB_Is_EPx_RDY_Free(epnum) && (device->out_ep[epnum].ep_cfg.ep_type != USBD_EP_TYPE_ISOC)) {
USB_DC_LOG_ERR("ep%d out busy\r\n", epnum);
return;
continue;
}
device->parent.callback(&device->parent, (void *)((uint32_t)USB_SET_EP_OUT(epnum)), 0, USB_DC_EVENT_EP_OUT_NOTIFY);
USB_Clr_IntStatus(epint);
return;
device->parent.callback(&device->parent, (void *)((uint32_t)USB_SET_EP_OUT(epnum)), 0, USB_DC_EVENT_EP_OUT_NOTIFY);
}
}
@ -1062,101 +1061,83 @@ void usb_dc_isr(usb_dc_device_t *device)
epnum = (epint - USB_INT_EP0_OUT_CMD) >> 1;
if (!USB_Is_EPx_RDY_Free(epnum) && (device->in_ep[epnum].ep_cfg.ep_type != USBD_EP_TYPE_ISOC)) {
USB_DC_LOG_DBG("ep%d in busy\r\n", epnum);
return;
continue;
}
device->parent.callback(&device->parent, (void *)((uint32_t)USB_SET_EP_IN(epnum)), 0, USB_DC_EVENT_EP_IN_NOTIFY);
USB_Clr_IntStatus(epint);
return;
device->parent.callback(&device->parent, (void *)((uint32_t)USB_SET_EP_IN(epnum)), 0, USB_DC_EVENT_EP_IN_NOTIFY);
}
}
/* sof */
if (USB_Get_IntStatus(USB_INT_SOF)) {
USB_DC_LOG("sof\r\n");
device->parent.callback(&device->parent, NULL, 0, USB_DC_EVENT_SOF);
USB_Clr_IntStatus(USB_INT_SOF);
return;
}
/* reset */
if (USB_Get_IntStatus(USB_INT_RESET)) {
USB_DC_LOG("reset\r\n");
device->parent.callback(&device->parent, NULL, 0, USB_DC_EVENT_RESET);
USB_Clr_IntStatus(USB_INT_RESET);
return;
}
/* vbus toggle */
if (USB_Get_IntStatus(USB_INT_VBUS_TGL)) {
USB_DC_LOG("vbus toggle\r\n");
/*************************************/
/*************************************/
USB_Clr_IntStatus(USB_INT_VBUS_TGL);
return;
}
/* EP0 setup done */
if (USB_Get_IntStatus(USB_INT_EP0_SETUP_DONE)) {
USB_DC_LOG("S\r\n");
if (!USB_Is_EPx_RDY_Free(0)) {
USB_DC_LOG_DBG("ep0 setup busy\r\n");
return;
}
USB_Clr_IntStatus(USB_INT_EP0_SETUP_DONE);
device->parent.callback(&device->parent, NULL, 0, USB_DC_EVENT_SETUP_NOTIFY);
USB_Set_EPx_Rdy(EP_ID0);
USB_Clr_IntStatus(USB_INT_EP0_SETUP_DONE);
return;
}
/* EP0 in done */
if (USB_Get_IntStatus(USB_INT_EP0_IN_DONE)) {
USB_DC_LOG("I\r\n");
if (!USB_Is_EPx_RDY_Free(0)) {
USB_DC_LOG_DBG("ep0 in busy\r\n");
return;
}
USB_Clr_IntStatus(USB_INT_EP0_IN_DONE);
device->parent.callback(&device->parent, (void *)0x80, 0, USB_DC_EVENT_EP0_IN_NOTIFY);
USB_Set_EPx_Rdy(EP_ID0);
USB_Clr_IntStatus(USB_INT_EP0_IN_DONE);
return;
}
/* EP0 out done */
if (USB_Get_IntStatus(USB_INT_EP0_OUT_DONE)) {
USB_DC_LOG("O\r\n");
if (!USB_Is_EPx_RDY_Free(0)) {
USB_DC_LOG_DBG("ep0 out busy\r\n");
return;
}
USB_Clr_IntStatus(USB_INT_EP0_OUT_DONE);
device->parent.callback(&device->parent, (void *)0x00, 0, USB_DC_EVENT_EP0_OUT_NOTIFY);
USB_Set_EPx_Rdy(EP_ID0);
/*************************************/
USB_Clr_IntStatus(USB_INT_EP0_OUT_DONE);
return;
}
/* sof */
if (USB_Get_IntStatus(USB_INT_SOF)) {
USB_Clr_IntStatus(USB_INT_SOF);
device->parent.callback(&device->parent, NULL, 0, USB_DC_EVENT_SOF);
return;
}
/* reset */
if (USB_Get_IntStatus(USB_INT_RESET)) {
USB_Clr_IntStatus(USB_INT_RESET);
device->parent.callback(&device->parent, NULL, 0, USB_DC_EVENT_RESET);
return;
}
/* reset end */
if (USB_Get_IntStatus(USB_INT_RESET_END)) {
USB_DC_LOG("re\r\n");
/*************************************/
USB_Set_EPx_Rdy(EP_ID0);
/*************************************/
USB_Clr_IntStatus(USB_INT_RESET_END);
USB_Set_EPx_Rdy(EP_ID0);
return;
}
/* vbus toggle */
if (USB_Get_IntStatus(USB_INT_VBUS_TGL)) {
USB_Clr_IntStatus(USB_INT_VBUS_TGL);
return;
}
#ifdef ENABLE_LPM_INT
/* LPM wakeup */
/* usb wakeup interrupt, need update by reg_excel_files */
if (USB_Get_IntStatus(USB_INT_LPM_WAKEUP)) {
/*************************************/
/*set wInterrupt_Mask global variable*/
/*************************************/
USB_Clr_IntStatus(USB_INT_LPM_WAKEUP);
return;
}
/* LPM packet */
/* usb suspend interrupt, need update by reg_excel_files */
if (USB_Get_IntStatus(USB_INT_LPM_PACKET)) {
/*************************************/
/* Force low-power mode in the macrocell */
@ -1167,7 +1148,8 @@ void usb_dc_isr(usb_dc_device_t *device)
USB_Clr_IntStatus(USB_INT_LPM_PACKET);
return;
}
#endif
#ifdef ENABLE_SOF3MS_INT
/* lost 3 SOF */
if (USB_Get_IntStatus(USB_INT_LOST_SOF_3_TIMES)) {
USB_DC_LOG_ERR("Lost 3 SOFs\r\n");
@ -1176,7 +1158,8 @@ void usb_dc_isr(usb_dc_device_t *device)
USB_Clr_IntStatus(USB_INT_LOST_SOF_3_TIMES);
return;
}
#endif
#ifdef ENABLE_ERROR_INT
/* error */
if (USB_Get_IntStatus(USB_INT_ERROR)) {
USB_DC_LOG("USB bus error 0x%08x; EP2 fifo status 0x%08x\r\n", *(volatile uint32_t *)(0x4000D81C), *(volatile uint32_t *)(0x4000D920));
@ -1186,6 +1169,7 @@ void usb_dc_isr(usb_dc_device_t *device)
USB_Clr_IntStatus(USB_INT_ERROR);
return;
}
#endif
}
/**
* @brief

4
drivers/bl702_driver/startup/system_bl702.c
View file

@ -134,11 +134,9 @@ void SystemInit(void)
/* global IRQ enable */
__enable_irq();
}
/*identify flash config automaticly*/
extern BL_Err_Type flash_init(void);
void System_Post_Init(void)
{
PDS_Trim_RC32M();
HBN_Trim_RC32K();
flash_init();
}

21
drivers/bl702_driver/std_drv/inc/bl702_sflash_ext.h
View file

@ -51,12 +51,32 @@
* @{
*/
/**
* @brief Serail flash protect KH25V40 type definition
*/
typedef enum {
SFLASH_KH25V40_PROTECT_NONE, /*!< SFlash no protect KH25V40 */
SFLASH_KH25V40_PROTECT_448KTO512K, /*!< SFlash protect KH25V40 448K to 512K */
SFLASH_KH25V40_PROTECT_384KTO512K, /*!< SFlash protect KH25V40 384K to 512K */
SFLASH_KH25V40_PROTECT_256KTO512K, /*!< SFlash protect KH25V40 256K to 512K */
SFLASH_KH25V40_PROTECT_ALL, /*!< SFlash protect KH25V40 0K to 512K */
} SFlash_Protect_Kh25v40_Type;
/*@} end of group SFLAH_EXT_Public_Types */
/** @defgroup SFLAH_EXT_Public_Constants
* @{
*/
/** @defgroup SFLASH_PROTECT_KH25V40_TYPE
* @{
*/
#define IS_SFLASH_PROTECT_KH25V40_TYPE(type) (((type) == SFLASH_KH25V40_PROTECT_NONE) || \
((type) == SFLASH_KH25V40_PROTECT_448KTO512K) || \
((type) == SFLASH_KH25V40_PROTECT_384KTO512K) || \
((type) == SFLASH_KH25V40_PROTECT_256KTO512K) || \
((type) == SFLASH_KH25V40_PROTECT_ALL))
/*@} end of group SFLAH_EXT_Public_Constants */
/** @defgroup SFLAH_EXT_Public_Macros
@ -68,6 +88,7 @@
/** @defgroup SFLAH_EXT_Public_Functions
* @{
*/
BL_Err_Type SFlash_KH25V40_Write_Protect(SPI_Flash_Cfg_Type *flashCfg, SFlash_Protect_Kh25v40_Type protect);
BL_Err_Type SFlash_Read_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t readRegCmd, uint8_t *regValue,
uint8_t regLen);
BL_Err_Type SFlash_Write_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t writeRegCmd, uint8_t *regValue,

1
drivers/bl702_driver/std_drv/inc/bl702_xip_sflash_ext.h
View file

@ -74,6 +74,7 @@
* @{
*/
BL_Err_Type XIP_SFlash_KH25V40_Write_Protect_Need_Lock(SPI_Flash_Cfg_Type *flashCfg, SFlash_Protect_Kh25v40_Type protect);
BL_Err_Type XIP_SFlash_Clear_Status_Register_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg);
/*@} end of group XIP_SFLASH_EXT_Public_Functions */

54
drivers/bl702_driver/std_drv/src/bl702_glb.c
View file

@ -3456,6 +3456,10 @@ BL_Err_Type ATTR_TCM_SECTION GLB_Set_Flash_Pad_HZ(void)
uint32_t tmpVal;
uint32_t offset;
if (BL_RD_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO) != 0x00) {
return ERROR;
}
for (offset = 23; offset <= 28; offset++) {
tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + offset / 2 * 4);
/* pu=0, pd=0, ie=0 */
@ -3466,18 +3470,16 @@ BL_Err_Type ATTR_TCM_SECTION GLB_Set_Flash_Pad_HZ(void)
}
BL_WR_WORD(GLB_BASE + GLB_GPIO_OFFSET + offset / 2 * 4, tmpVal);
if ((BL_RD_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO) & (1 << (offset - 23))) == 0) {
tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + offset / 2 * 4);
/* func_sel=swgpio */
if (offset % 2 == 0) {
tmpVal = (tmpVal & 0xffff00ff);
tmpVal |= 0x0B00;
} else {
tmpVal = (tmpVal & 0x00ffffff);
tmpVal |= (0x0B00 << 16);
}
BL_WR_WORD(GLB_BASE + GLB_GPIO_OFFSET + offset / 2 * 4, tmpVal);
tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + offset / 2 * 4);
/* func_sel=swgpio */
if (offset % 2 == 0) {
tmpVal = (tmpVal & 0xffff00ff);
tmpVal |= 0x0B00;
} else {
tmpVal = (tmpVal & 0x00ffffff);
tmpVal |= (0x0B00 << 16);
}
BL_WR_WORD(GLB_BASE + GLB_GPIO_OFFSET + offset / 2 * 4, tmpVal);
}
tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OUTPUT_EN_OFFSET);
@ -3492,6 +3494,10 @@ BL_Err_Type ATTR_TCM_SECTION GLB_Set_Psram_Pad_HZ(void)
uint32_t tmpVal;
uint32_t offset;
if (BL_RD_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO) != 0x3F) {
return ERROR;
}
for (offset = 32; offset <= 37; offset++) {
tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + offset / 2 * 4);
/* pu=0, pd=0, ie=0 */
@ -3502,23 +3508,21 @@ BL_Err_Type ATTR_TCM_SECTION GLB_Set_Psram_Pad_HZ(void)
}
BL_WR_WORD(GLB_BASE + GLB_GPIO_OFFSET + offset / 2 * 4, tmpVal);
if ((BL_RD_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO) & (1 << (offset - 32))) > 0) {
tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + (offset - 9) / 2 * 4);
/* func_sel=swgpio */
if ((offset - 9) % 2 == 0) {
tmpVal = (tmpVal & 0xffff00ff);
tmpVal |= 0x0B00;
} else {
tmpVal = (tmpVal & 0x00ffffff);
tmpVal |= (0x0B00 << 16);
}
BL_WR_WORD(GLB_BASE + GLB_GPIO_OFFSET + (offset - 9) / 2 * 4, tmpVal);
tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + (offset - 9) / 2 * 4);
/* func_sel=swgpio */
if ((offset - 9) % 2 == 0) {
tmpVal = (tmpVal & 0xffff00ff);
tmpVal |= 0x0B00;
} else {
tmpVal = (tmpVal & 0x00ffffff);
tmpVal |= (0x0B00 << 16);
}
BL_WR_WORD(GLB_BASE + GLB_GPIO_OFFSET + (offset - 9) / 2 * 4, tmpVal);
}
tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OUTPUT_EN_OFFSET + 4);
tmpVal &= 0xFFFFFFC0;
BL_WR_WORD(GLB_BASE + GLB_GPIO_OUTPUT_EN_OFFSET + 4, tmpVal);
tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OUTPUT_EN_OFFSET);
tmpVal &= 0xE07FFFFF;
BL_WR_WORD(GLB_BASE + GLB_GPIO_OUTPUT_EN_OFFSET, tmpVal);
return SUCCESS;
}

31
drivers/bl702_driver/std_drv/src/bl702_hbn.c
View file

@ -1162,7 +1162,7 @@ BL_Err_Type HBN_Set_RTC_Timer(HBN_RTC_INT_Delay_Type delay, uint32_t compValLow,
}
/****************************************************************************/ /**
* @brief HBN get RTC timer count value
* @brief HBN get RTC async timer count value
*
* @param valLow: RTC count value pointer for low 32 bits
* @param valHigh: RTC count value pointer for high 8 bits
@ -1170,7 +1170,7 @@ BL_Err_Type HBN_Set_RTC_Timer(HBN_RTC_INT_Delay_Type delay, uint32_t compValLow,
* @return SUCCESS or ERROR
*
*******************************************************************************/
BL_Err_Type HBN_Get_RTC_Timer_Val(uint32_t *valLow, uint32_t *valHigh)
static BL_Err_Type HBN_Get_RTC_Timer_Async_Val(uint32_t *valLow, uint32_t *valHigh)
{
uint32_t tmpVal;
@ -1188,6 +1188,33 @@ BL_Err_Type HBN_Get_RTC_Timer_Val(uint32_t *valLow, uint32_t *valHigh)
return SUCCESS;
}
/****************************************************************************/ /**
* @brief HBN get RTC timer count value
*
* @param valLow: RTC count value pointer for low 32 bits
* @param valHigh: RTC count value pointer for high 8 bits
*
* @return SUCCESS or ERROR
*
*******************************************************************************/
BL_Err_Type HBN_Get_RTC_Timer_Val(uint32_t *valLow, uint32_t *valHigh)
{
uint32_t tmpValLow, tmpValHigh, tmpValLow1, tmpValHigh1;
uint64_t val, val1;
do {
HBN_Get_RTC_Timer_Async_Val(&tmpValLow, &tmpValHigh);
val = ((uint64_t)tmpValHigh << 32) | ((uint64_t)tmpValLow);
HBN_Get_RTC_Timer_Async_Val(&tmpValLow1, &tmpValHigh1);
val1 = ((uint64_t)tmpValHigh1 << 32) | ((uint64_t)tmpValLow1);
} while (val1 < val);
*valLow = tmpValLow1;
*valHigh = tmpValHigh1;
return SUCCESS;
}
/****************************************************************************/ /**
* @brief HBN clear RTC timer interrupt,this function must be called to clear delayed rtc IRQ
*

1398
drivers/bl702_driver/std_drv/src/bl702_sf_cfg_ext.c
View file

File diff suppressed because it is too large Load diff

35
drivers/bl702_driver/std_drv/src/bl702_sflash_ext.c
View file

@ -86,6 +86,41 @@
* @{
*/
/****************************************************************************/ /**
* @brief KH25V40 flash write protect set
*
* @param flashCfg: Serial flash parameter configuration pointer
* @param protect: protect area
*
* @return SUCCESS or ERROR
*
*******************************************************************************/
__WEAK
BL_Err_Type ATTR_TCM_SECTION SFlash_KH25V40_Write_Protect(SPI_Flash_Cfg_Type *flashCfg, SFlash_Protect_Kh25v40_Type protect)
{
uint32_t stat = 0, ret;
SFlash_Read_Reg(flashCfg, 0, (uint8_t *)&stat, 1);
if (((stat >> 2) & 0xf) == protect) {
return SUCCESS;
}
stat |= ((protect << 2) & 0xff);
ret = SFlash_Write_Enable(flashCfg);
if (SUCCESS != ret) {
return ERROR;
}
SFlash_Write_Reg(flashCfg, 0, (uint8_t *)&stat, 1);
SFlash_Read_Reg(flashCfg, 0, (uint8_t *)&stat, 1);
if (((stat >> 2) & 0xf) == protect) {
return SUCCESS;
}
return ERROR;
}
/****************************************************************************/ /**
* @brief Read flash register with read command
*

4
drivers/bl702_driver/std_drv/src/bl702_spi.c
View file

@ -275,8 +275,8 @@ BL_Err_Type SPI_FifoConfig(SPI_ID_Type spiNo, SPI_FifoCfg_Type *fifoCfg)
/* Set fifo threshold value */
tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_1);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_TX_FIFO_TH, fifoCfg->txFifoThreshold - 1);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_RX_FIFO_TH, fifoCfg->rxFifoThreshold - 1);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_TX_FIFO_TH, fifoCfg->txFifoThreshold);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_RX_FIFO_TH, fifoCfg->rxFifoThreshold);
BL_WR_REG(SPIx, SPI_FIFO_CONFIG_1, tmpVal);
/* Enable or disable dma function */

4
drivers/bl702_driver/std_drv/src/bl702_uart.c
View file

@ -340,9 +340,9 @@ BL_Err_Type UART_FifoConfig(UART_ID_Type uartId, UART_FifoCfg_Type *fifoCfg)
/* Deal with uart fifo configure register */
tmpVal = BL_RD_REG(UARTx, UART_FIFO_CONFIG_1);
/* Configure dma tx fifo threshold */
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, UART_TX_FIFO_TH, fifoCfg->txFifoDmaThreshold - 1);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, UART_TX_FIFO_TH, fifoCfg->txFifoDmaThreshold);
/* Configure dma rx fifo threshold */
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, UART_RX_FIFO_TH, fifoCfg->rxFifoDmaThreshold - 1);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, UART_RX_FIFO_TH, fifoCfg->rxFifoDmaThreshold);
/* Write back */
BL_WR_REG(UARTx, UART_FIFO_CONFIG_1, tmpVal);

27
drivers/bl702_driver/std_drv/src/bl702_xip_sflash_ext.c
View file

@ -79,6 +79,33 @@
* @{
*/
/****************************************************************************//**
* @brief XIP KH25V40 flash write protect set
*
* @param pFlashCfg: Flash config pointer
* @param protect: protect area
*
* @return SUCCESS or ERROR
*
*******************************************************************************/
__WEAK
BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_KH25V40_Write_Protect_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SFlash_Protect_Kh25v40_Type protect)
{
BL_Err_Type stat;
uint32_t offset;
SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode&0xf;
stat = XIP_SFlash_State_Save(pFlashCfg, &offset);
if (stat != SUCCESS) {
SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32);
} else {
stat = SFlash_KH25V40_Write_Protect(pFlashCfg, protect);
XIP_SFlash_State_Restore(pFlashCfg, ioMode, offset);
}
return stat;
}
/****************************************************************************//**
* @brief Clear flash status register need lock
*